From 273f500c914f21d4d8270435c69a9c7a77a5aaa4 Mon Sep 17 00:00:00 2001 From: Arunpravin Paneer Selvam Date: Wed, 16 Jul 2025 13:21:24 +0530 Subject: [PATCH 0001/2653] drm/amdgpu: Reset the clear flag in buddy during resume MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Added a handler in DRM buddy manager to reset the cleared flag for the blocks in the freelist. - This is necessary because, upon resuming, the VRAM becomes cluttered with BIOS data, yet the VRAM backend manager believes that everything has been cleared. v2: - Add lock before accessing drm_buddy_clear_reset_blocks()(Matthew Auld) - Force merge the two dirty blocks.(Matthew Auld) - Add a new unit test case for this issue.(Matthew Auld) - Having this function being able to flip the state either way would be good. (Matthew Brost) v3(Matthew Auld): - Do merge step first to avoid the use of extra reset flag. Signed-off-by: Arunpravin Paneer Selvam Suggested-by: Christian König Acked-by: Christian König Reviewed-by: Matthew Auld Cc: stable@vger.kernel.org Fixes: a68c7eaa7a8f ("drm/amdgpu: Enable clear page functionality") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3812 Signed-off-by: Christian König Link: https://lore.kernel.org/r/20250716075125.240637-2-Arunpravin.PaneerSelvam@amd.com (cherry picked from commit 95a16160ca1d75c66bf7a1c5e0bcaffb18e7c7fc) --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 17 ++++++++ drivers/gpu/drm/drm_buddy.c | 43 ++++++++++++++++++++ include/drm/drm_buddy.h | 2 + 5 files changed, 65 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 79d0ff0bda290..713f1a5bb3107 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5303,6 +5303,8 @@ int amdgpu_device_resume(struct drm_device *dev, bool notify_clients) dev->dev->power.disable_depth--; #endif } + + amdgpu_vram_mgr_clear_reset_blocks(adev); adev->in_suspend = false; if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DEV_D0)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 215c198e4aff7..2309df3f68a9c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -155,6 +155,7 @@ int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr, uint64_t start, uint64_t size); int amdgpu_vram_mgr_query_page_status(struct amdgpu_vram_mgr *mgr, uint64_t start); +void amdgpu_vram_mgr_clear_reset_blocks(struct amdgpu_device *adev); bool amdgpu_res_cpu_visible(struct amdgpu_device *adev, struct ttm_resource *res); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index abdc52b0895a6..07c936e90d8e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -782,6 +782,23 @@ uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr) return atomic64_read(&mgr->vis_usage); } +/** + * amdgpu_vram_mgr_clear_reset_blocks - reset clear blocks + * + * @adev: amdgpu device pointer + * + * Reset the cleared drm buddy blocks. + */ +void amdgpu_vram_mgr_clear_reset_blocks(struct amdgpu_device *adev) +{ + struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; + struct drm_buddy *mm = &mgr->mm; + + mutex_lock(&mgr->lock); + drm_buddy_reset_clear(mm, false); + mutex_unlock(&mgr->lock); +} + /** * amdgpu_vram_mgr_intersects - test each drm buddy block for intersection * diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c index a1e652b7631de..a94061f373de5 100644 --- a/drivers/gpu/drm/drm_buddy.c +++ b/drivers/gpu/drm/drm_buddy.c @@ -405,6 +405,49 @@ drm_get_buddy(struct drm_buddy_block *block) } EXPORT_SYMBOL(drm_get_buddy); +/** + * drm_buddy_reset_clear - reset blocks clear state + * + * @mm: DRM buddy manager + * @is_clear: blocks clear state + * + * Reset the clear state based on @is_clear value for each block + * in the freelist. + */ +void drm_buddy_reset_clear(struct drm_buddy *mm, bool is_clear) +{ + u64 root_size, size, start; + unsigned int order; + int i; + + size = mm->size; + for (i = 0; i < mm->n_roots; ++i) { + order = ilog2(size) - ilog2(mm->chunk_size); + start = drm_buddy_block_offset(mm->roots[i]); + __force_merge(mm, start, start + size, order); + + root_size = mm->chunk_size << order; + size -= root_size; + } + + for (i = 0; i <= mm->max_order; ++i) { + struct drm_buddy_block *block; + + list_for_each_entry_reverse(block, &mm->free_list[i], link) { + if (is_clear != drm_buddy_block_is_clear(block)) { + if (is_clear) { + mark_cleared(block); + mm->clear_avail += drm_buddy_block_size(mm, block); + } else { + clear_reset(block); + mm->clear_avail -= drm_buddy_block_size(mm, block); + } + } + } + } +} +EXPORT_SYMBOL(drm_buddy_reset_clear); + /** * drm_buddy_free_block - free a block * diff --git a/include/drm/drm_buddy.h b/include/drm/drm_buddy.h index 9689a7c5dd36b..513837632b7d3 100644 --- a/include/drm/drm_buddy.h +++ b/include/drm/drm_buddy.h @@ -160,6 +160,8 @@ int drm_buddy_block_trim(struct drm_buddy *mm, u64 new_size, struct list_head *blocks); +void drm_buddy_reset_clear(struct drm_buddy *mm, bool is_clear); + void drm_buddy_free_block(struct drm_buddy *mm, struct drm_buddy_block *block); void drm_buddy_free_list(struct drm_buddy *mm, From 48ec500705e81c062d10d23d881ff0c56b005f29 Mon Sep 17 00:00:00 2001 From: "Lin.Cao" Date: Thu, 17 Jul 2025 16:44:53 +0800 Subject: [PATCH 0002/2653] drm/sched: Remove optimization that causes hang when killing dependent jobs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When application A submits jobs and application B submits a job with a dependency on A's fence, the normal flow wakes up the scheduler after processing each job. However, the optimization in drm_sched_entity_add_dependency_cb() uses a callback that only clears dependencies without waking up the scheduler. When application A is killed before its jobs can run, the callback gets triggered but only clears the dependency without waking up the scheduler, causing the scheduler to enter sleep state and application B to hang. Remove the optimization by deleting drm_sched_entity_clear_dep() and its usage, ensuring the scheduler is always woken up when dependencies are cleared. Fixes: 777dbd458c89 ("drm/amdgpu: drop a dummy wakeup scheduler") Cc: stable@vger.kernel.org # v4.6+ Signed-off-by: Lin.Cao Reviewed-by: Christian König Signed-off-by: Philipp Stanner Link: https://lore.kernel.org/r/20250717084453.921097-1-lincao12@amd.com (cherry picked from commit 15f77764e90a713ee3916ca424757688e4f565b9) --- drivers/gpu/drm/scheduler/sched_entity.c | 21 ++------------------- 1 file changed, 2 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c index 5635b3a826d87..8867b95ab089c 100644 --- a/drivers/gpu/drm/scheduler/sched_entity.c +++ b/drivers/gpu/drm/scheduler/sched_entity.c @@ -355,17 +355,6 @@ void drm_sched_entity_destroy(struct drm_sched_entity *entity) } EXPORT_SYMBOL(drm_sched_entity_destroy); -/* drm_sched_entity_clear_dep - callback to clear the entities dependency */ -static void drm_sched_entity_clear_dep(struct dma_fence *f, - struct dma_fence_cb *cb) -{ - struct drm_sched_entity *entity = - container_of(cb, struct drm_sched_entity, cb); - - entity->dependency = NULL; - dma_fence_put(f); -} - /* * drm_sched_entity_wakeup - callback to clear the entity's dependency and * wake up the scheduler @@ -376,7 +365,8 @@ static void drm_sched_entity_wakeup(struct dma_fence *f, struct drm_sched_entity *entity = container_of(cb, struct drm_sched_entity, cb); - drm_sched_entity_clear_dep(f, cb); + entity->dependency = NULL; + dma_fence_put(f); drm_sched_wakeup(entity->rq->sched); } @@ -429,13 +419,6 @@ static bool drm_sched_entity_add_dependency_cb(struct drm_sched_entity *entity) fence = dma_fence_get(&s_fence->scheduled); dma_fence_put(entity->dependency); entity->dependency = fence; - if (!dma_fence_add_callback(fence, &entity->cb, - drm_sched_entity_clear_dep)) - return true; - - /* Ignore it when it is already scheduled */ - dma_fence_put(fence); - return false; } if (!dma_fence_add_callback(entity->dependency, &entity->cb, From db454c8fb64c3291795e9360bb2698ae8b94c183 Mon Sep 17 00:00:00 2001 From: Samuel Zhang Date: Thu, 10 Jul 2025 14:23:09 +0800 Subject: [PATCH 0003/2653] drm/ttm: add new api ttm_device_prepare_hibernation() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This new api is used for hibernation to move GTT BOs to shmem after VRAM eviction. shmem will be flushed to swap disk later to reduce the system memory usage for hibernation. Signed-off-by: Samuel Zhang Reviewed-by: Christian König Link: https://lore.kernel.org/r/20250710062313.3226149-2-guoqing.zhang@amd.com Signed-off-by: Mario Limonciello (cherry picked from commit 40b6a946d21ee7b2b6d394bb2f1cdd3973aa9da5) --- drivers/gpu/drm/ttm/ttm_device.c | 22 ++++++++++++++++++++++ include/drm/ttm/ttm_device.h | 1 + 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c index 816e2cba6016e..c3e2fcbdd2cc6 100644 --- a/drivers/gpu/drm/ttm/ttm_device.c +++ b/drivers/gpu/drm/ttm/ttm_device.c @@ -125,6 +125,28 @@ static int ttm_global_init(void) return ret; } +/** + * ttm_device_prepare_hibernation - move GTT BOs to shmem for hibernation. + * + * @bdev: A pointer to a struct ttm_device to prepare hibernation for. + * + * Return: 0 on success, negative number on failure. + */ +int ttm_device_prepare_hibernation(struct ttm_device *bdev) +{ + struct ttm_operation_ctx ctx = { + .interruptible = false, + .no_wait_gpu = false, + }; + int ret; + + do { + ret = ttm_device_swapout(bdev, &ctx, GFP_KERNEL); + } while (ret > 0); + return ret; +} +EXPORT_SYMBOL(ttm_device_prepare_hibernation); + /* * A buffer object shrink method that tries to swap out the first * buffer object on the global::swap_lru list. diff --git a/include/drm/ttm/ttm_device.h b/include/drm/ttm/ttm_device.h index 39b8636b18451..592b5f8028599 100644 --- a/include/drm/ttm/ttm_device.h +++ b/include/drm/ttm/ttm_device.h @@ -272,6 +272,7 @@ struct ttm_device { int ttm_global_swapout(struct ttm_operation_ctx *ctx, gfp_t gfp_flags); int ttm_device_swapout(struct ttm_device *bdev, struct ttm_operation_ctx *ctx, gfp_t gfp_flags); +int ttm_device_prepare_hibernation(struct ttm_device *bdev); static inline struct ttm_resource_manager * ttm_manager_type(struct ttm_device *bdev, int mem_type) From 8ac0ae7abcda15683b529588f4d2782930b83538 Mon Sep 17 00:00:00 2001 From: Samuel Zhang Date: Thu, 10 Jul 2025 14:23:10 +0800 Subject: [PATCH 0004/2653] drm/amdgpu: move GTT to shmem after eviction for hibernation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When hibernate with data center dGPUs, huge number of VRAM BOs evicted to GTT and takes too much system memory. This will cause hibernation fail due to insufficient memory for creating the hibernation image. Move GTT BOs to shmem in KMD, then shmem to swap disk in kernel hibernation code to make room for hibernation image. Signed-off-by: Samuel Zhang Reviewed-by: Christian König Link: https://lore.kernel.org/r/20250710062313.3226149-3-guoqing.zhang@amd.com Signed-off-by: Mario Limonciello (cherry picked from commit 924dda024f3bea64be5f3ac067a075e466739dc9) --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 713f1a5bb3107..6f93473436bed 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5013,8 +5013,16 @@ static int amdgpu_device_evict_resources(struct amdgpu_device *adev) return 0; ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM); - if (ret) + if (ret) { dev_warn(adev->dev, "evicting device resources failed\n"); + return ret; + } + + if (adev->in_s4) { + ret = ttm_device_prepare_hibernation(&adev->mman.bdev); + if (ret) + dev_err(adev->dev, "prepare hibernation failed, %d\n", ret); + } return ret; } From f1e78274267fd1b2d737e5594196d1db2410e1ce Mon Sep 17 00:00:00 2001 From: Samuel Zhang Date: Thu, 10 Jul 2025 14:23:11 +0800 Subject: [PATCH 0005/2653] PM: hibernate: shrink shmem pages after dev_pm_ops.prepare() When hibernate with data center dGPUs, huge number of VRAM data will be moved to shmem during dev_pm_ops.prepare(). These shmem pages take a lot of system memory so that there's no enough free memory for creating the hibernation image. This will cause hibernation fail and abort. After dev_pm_ops.prepare(), call shrink_all_memory() to force move shmem pages to swap disk and reclaim the pages, so that there's enough system memory for hibernation image and less pages needed to copy to the image. This patch can only flush and free about half shmem pages. It will be better to flush and free more pages, even all of shmem pages, so that there're less pages to be copied to the hibernation image and the overall hibernation time can be reduced. Signed-off-by: Samuel Zhang Acked-by: Rafael J. Wysocki Link: https://lore.kernel.org/r/20250710062313.3226149-4-guoqing.zhang@amd.com Signed-off-by: Mario Limonciello (cherry picked from commit 2640e819474f4a9ec78aa3cdb9063e4b5cf18ae4) --- kernel/power/hibernate.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/kernel/power/hibernate.c b/kernel/power/hibernate.c index 9216e3b91d3b3..1f1f30cca5732 100644 --- a/kernel/power/hibernate.c +++ b/kernel/power/hibernate.c @@ -381,6 +381,23 @@ static int create_image(int platform_mode) return error; } +static void shrink_shmem_memory(void) +{ + struct sysinfo info; + unsigned long nr_shmem_pages, nr_freed_pages; + + si_meminfo(&info); + nr_shmem_pages = info.sharedram; /* current page count used for shmem */ + /* + * The intent is to reclaim all shmem pages. Though shrink_all_memory() can + * only reclaim about half of them, it's enough for creating the hibernation + * image. + */ + nr_freed_pages = shrink_all_memory(nr_shmem_pages); + pr_debug("requested to reclaim %lu shmem pages, actually freed %lu pages\n", + nr_shmem_pages, nr_freed_pages); +} + /** * hibernation_snapshot - Quiesce devices and create a hibernation image. * @platform_mode: If set, use platform driver to prepare for the transition. @@ -422,6 +439,15 @@ int hibernation_snapshot(int platform_mode) goto Thaw; } + /* + * Device drivers may move lots of data to shmem in dpm_prepare(). The shmem + * pages will use lots of system memory, causing hibernation image creation + * fail due to insufficient free memory. + * This call is to force flush the shmem pages to swap disk and reclaim + * the system memory so that image creation can succeed. + */ + shrink_shmem_memory(); + console_suspend_all(); error = dpm_suspend(PMSG_FREEZE); From 9b934e465aafdd3b2f103022883dfcc40f37843f Mon Sep 17 00:00:00 2001 From: Samuel Zhang Date: Thu, 10 Jul 2025 14:23:12 +0800 Subject: [PATCH 0006/2653] PM: hibernate: add new api pm_hibernate_is_recovering() dev_pm_ops.thaw() is called in following cases: * normal case: after hibernation image has been created. * error case 1: creation of a hibernation image has failed. * error case 2: restoration from a hibernation image has failed. For normal case, it is called mainly for resume storage devices for saving the hibernation image. Other devices that are not involved in the image saving do not need to resume the device. But since there's no api to know which case thaw() is called, device drivers can't conditionally resume device in thaw(). The new pm_hibernate_is_recovering() is such a api to query if thaw() is called in normal case. Signed-off-by: Samuel Zhang Acked-by: Rafael J. Wysocki Link: https://lore.kernel.org/r/20250710062313.3226149-5-guoqing.zhang@amd.com Signed-off-by: Mario Limonciello (cherry picked from commit c2aaddbd2deded9d3301f1bafed242a0f71baba8) --- drivers/base/power/main.c | 14 ++++++++++++++ include/linux/suspend.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/drivers/base/power/main.c b/drivers/base/power/main.c index a6ab666ef48ae..90c2ea7dd6203 100644 --- a/drivers/base/power/main.c +++ b/drivers/base/power/main.c @@ -66,6 +66,20 @@ static pm_message_t pm_transition; static DEFINE_MUTEX(async_wip_mtx); static int async_error; +/** + * pm_hibernate_is_recovering - if recovering from hibernate due to error. + * + * Used to query if dev_pm_ops.thaw() is called for normal hibernation case or + * recovering from some error. + * + * Return: true for error case, false for normal case. + */ +bool pm_hibernate_is_recovering(void) +{ + return pm_transition.event == PM_EVENT_RECOVER; +} +EXPORT_SYMBOL_GPL(pm_hibernate_is_recovering); + static const char *pm_verb(int event) { switch (event) { diff --git a/include/linux/suspend.h b/include/linux/suspend.h index 6a3f920988720..d11a124b7a919 100644 --- a/include/linux/suspend.h +++ b/include/linux/suspend.h @@ -426,6 +426,8 @@ int is_hibernate_resume_dev(dev_t dev); static inline int is_hibernate_resume_dev(dev_t dev) { return 0; } #endif +bool pm_hibernate_is_recovering(void); + /* Hibernation and suspend events */ #define PM_HIBERNATION_PREPARE 0x0001 /* Going to hibernate */ #define PM_POST_HIBERNATION 0x0002 /* Hibernation finished */ From aba06c660d01fc8c8634d45cdb451439c4695d6c Mon Sep 17 00:00:00 2001 From: Samuel Zhang Date: Thu, 10 Jul 2025 14:23:13 +0800 Subject: [PATCH 0007/2653] drm/amdgpu: do not resume device in thaw for normal hibernation For normal hibernation, GPU do not need to be resumed in thaw since it is not involved in writing the hibernation image. Skip resume in this case can reduce the hibernation time. On VM with 8 * 192GB VRAM dGPUs, 98% VRAM usage and 1.7TB system memory, this can save 50 minutes. Signed-off-by: Samuel Zhang Tested-by: Mario Limonciello Reviewed-by: Mario Limonciello Reviewed-by: Lijo Lazar Link: https://lore.kernel.org/r/20250710062313.3226149-6-guoqing.zhang@amd.com Signed-off-by: Mario Limonciello (cherry picked from commit 530694f54dd5e097866999bbaebc5c133e5507b6) --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 3bb9b25cd1219..395c6be901ce7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2542,6 +2542,10 @@ amdgpu_pci_shutdown(struct pci_dev *pdev) if (amdgpu_ras_intr_triggered()) return; + /* device maybe not resumed here, return immediately in this case */ + if (adev->in_s4 && adev->in_suspend) + return; + /* if we are running in a VM, make sure the device * torn down properly on reboot/shutdown. * unfortunately we can't detect certain @@ -2558,6 +2562,10 @@ static int amdgpu_pmops_prepare(struct device *dev) struct drm_device *drm_dev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(drm_dev); + /* device maybe not resumed here, return immediately in this case */ + if (adev->in_s4 && adev->in_suspend) + return 0; + /* Return a positive number here so * DPM_FLAG_SMART_SUSPEND works properly */ @@ -2656,12 +2664,21 @@ static int amdgpu_pmops_thaw(struct device *dev) { struct drm_device *drm_dev = dev_get_drvdata(dev); + /* do not resume device if it's normal hibernation */ + if (!pm_hibernate_is_recovering()) + return 0; + return amdgpu_device_resume(drm_dev, true); } static int amdgpu_pmops_poweroff(struct device *dev) { struct drm_device *drm_dev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(drm_dev); + + /* device maybe not resumed here, return immediately in this case */ + if (adev->in_s4 && adev->in_suspend) + return 0; return amdgpu_device_suspend(drm_dev, true); } From 53de7ad2ec3f339271f517bd75e0a9edfc2541da Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Sat, 12 Jul 2025 18:37:12 -0500 Subject: [PATCH 0008/2653] PM: hibernate: Add stub for pm_hibernate_is_recovering() Randy reports that amdgpu fails to compile with the following error: ERROR: modpost: "pm_hibernate_is_recovering" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! This happens because pm_hibernate_is_recovering() is only compiled when CONFIG_PM_SLEEP is set. Add a stub for it so that drivers don't need to depend upon CONFIG_PM. Cc: Samuel Zhang Reported-by: Randy Dunlap Closes: https://lore.kernel.org/dri-devel/CAJZ5v0h1CX+aTu7dFy6vB-9LM6t5J4rt7Su3qVnq1xx-BFAm=Q@mail.gmail.com/T/#m2b9fe212b35fde11d58fcbc4e0727bc02ebba7b0 Fixes: c2aaddbd2dede ("PM: hibernate: add new api pm_hibernate_is_recovering()") Acked-by: Rafael J. Wysocki Reviewed-by: Randy Dunlap Tested-by: Randy Dunlap Link: https://lore.kernel.org/r/20250712233715.821424-1-superm1@kernel.org Signed-off-by: Mario Limonciello (cherry picked from commit a6cfa4c8833944f8912c1fa7f95795753f6376ea) --- include/linux/suspend.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/suspend.h b/include/linux/suspend.h index d11a124b7a919..317ae31e89b37 100644 --- a/include/linux/suspend.h +++ b/include/linux/suspend.h @@ -426,8 +426,6 @@ int is_hibernate_resume_dev(dev_t dev); static inline int is_hibernate_resume_dev(dev_t dev) { return 0; } #endif -bool pm_hibernate_is_recovering(void); - /* Hibernation and suspend events */ #define PM_HIBERNATION_PREPARE 0x0001 /* Going to hibernate */ #define PM_POST_HIBERNATION 0x0002 /* Hibernation finished */ @@ -480,6 +478,7 @@ extern unsigned int lock_system_sleep(void); extern void unlock_system_sleep(unsigned int); extern bool pm_sleep_transition_in_progress(void); +bool pm_hibernate_is_recovering(void); #else /* !CONFIG_PM_SLEEP */ @@ -513,6 +512,7 @@ static inline unsigned int lock_system_sleep(void) { return 0; } static inline void unlock_system_sleep(unsigned int flags) {} static inline bool pm_sleep_transition_in_progress(void) { return false; } +static inline bool pm_hibernate_is_recovering(void) { return false; } #endif /* !CONFIG_PM_SLEEP */ From b2491ae9d85d5f51be2cffcef622090e95aff0f7 Mon Sep 17 00:00:00 2001 From: Yong Zhao Date: Tue, 10 Sep 2019 11:24:42 -0400 Subject: [PATCH 0009/2653] Add rock-dbg_defconfig which turns on KFD This file only turns on a substantial smaller set of kernel options, together with all AMD stuff, and supports most use cases on common HW configurations. As a result, building kernel with this config is super fast. Moreover, with this config, KFD folks can easily build the kernel with build_kernel.sh script and verify the change before we push the commit out for review on amd-gfx mailist. Signed-off-by: Yong Zhao Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 4688 +++++++++++++++++++++++++++ 1 file changed, 4688 insertions(+) create mode 100644 arch/x86/configs/rock-dbg_defconfig diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig new file mode 100644 index 0000000000000..5e1de51be9553 --- /dev/null +++ b/arch/x86/configs/rock-dbg_defconfig @@ -0,0 +1,4688 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/x86 5.3.0-rc3 Kernel Configuration +# + +# +# Compiler: gcc (Ubuntu 7.4.0-1ubuntu1~18.04.1) 7.4.0 +# +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=70400 +CONFIG_CLANG_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +# CONFIG_HEADER_TEST is not set +CONFIG_LOCALVERSION="-kfd" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_BUILD_SALT="" +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_USELIB=y +CONFIG_AUDIT=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_PENDING_IRQ=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y +CONFIG_GENERIC_IRQ_RESERVATION_MODE=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# end of IRQ subsystem + +CONFIG_CLOCKSOURCE_WATCHDOG=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_CLOCKSOURCE_INIT=y +CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y +CONFIG_GENERIC_CMOS_UPDATE=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +CONFIG_PREEMPT_COUNT=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +# CONFIG_PSI is not set +# end of CPU/Task time and stats accounting + +# CONFIG_CPU_ISOLATION is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +# end of RCU Subsystem + +CONFIG_BUILD_BIN2C=y +# CONFIG_IKCONFIG is not set +# CONFIG_IKHEADERS is not set +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y + +# +# Scheduler features +# +# end of Scheduler features + +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +CONFIG_CGROUPS=y +CONFIG_PAGE_COUNTER=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +# CONFIG_MEMCG_SWAP_ENABLED is not set +CONFIG_MEMCG_KMEM=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_WRITEBACK=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_CGROUP_PIDS=y +# CONFIG_CGROUP_RDMA is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_HAVE_UID16=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_HAVE_PCSPKR_PLATFORM=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +CONFIG_SGETMASK_SYSCALL=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_BPF_SYSCALL=y +# CONFIG_USERFAULTFD is not set +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_MEMCG_SYSFS_ON is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SYSTEM_DATA_VERIFICATION=y +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# end of General setup + +CONFIG_64BIT=y +CONFIG_X86_64=y +CONFIG_X86=y +CONFIG_INSTRUCTION_DECODER=y +CONFIG_OUTPUT_FORMAT="elf64-x86-64" +CONFIG_ARCH_DEFCONFIG="arch/x86/configs/x86_64_defconfig" +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_MMU=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=28 +CONFIG_ARCH_MMAP_RND_BITS_MAX=32 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_HAS_CPU_RELAX=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_HAS_FILTER_PGPROT=y +CONFIG_HAVE_SETUP_PER_CPU_AREA=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ZONE_DMA32=y +CONFIG_AUDIT_ARCH=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_X86_64_SMP=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=4 +CONFIG_CC_HAS_SANE_STACKPROTECTOR=y + +# +# Processor type and features +# +CONFIG_ZONE_DMA=y +CONFIG_SMP=y +CONFIG_X86_FEATURE_NAMES=y +# CONFIG_X86_X2APIC is not set +CONFIG_X86_MPPARSE=y +# CONFIG_GOLDFISH is not set +# CONFIG_RETPOLINE is not set +# CONFIG_X86_CPU_RESCTRL is not set +CONFIG_X86_EXTENDED_PLATFORM=y +# CONFIG_X86_VSMP is not set +# CONFIG_X86_GOLDFISH is not set +CONFIG_X86_INTEL_LPSS=y +# CONFIG_X86_AMD_PLATFORM_DEVICE is not set +CONFIG_IOSF_MBI=y +CONFIG_IOSF_MBI_DEBUG=y +CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_HYPERVISOR_GUEST=y +CONFIG_PARAVIRT=y +# CONFIG_PARAVIRT_DEBUG is not set +CONFIG_PARAVIRT_SPINLOCKS=y +# CONFIG_XEN is not set +CONFIG_KVM_GUEST=y +# CONFIG_PVH is not set +CONFIG_KVM_DEBUG_FS=y +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +CONFIG_PARAVIRT_CLOCK=y +# CONFIG_JAILHOUSE_GUEST is not set +# CONFIG_ACRN_GUEST is not set +# CONFIG_MK8 is not set +# CONFIG_MPSC is not set +# CONFIG_MCORE2 is not set +# CONFIG_MATOM is not set +CONFIG_GENERIC_CPU=y +CONFIG_X86_INTERNODE_CACHE_SHIFT=6 +CONFIG_X86_L1_CACHE_SHIFT=6 +CONFIG_X86_TSC=y +CONFIG_X86_CMPXCHG64=y +CONFIG_X86_CMOV=y +CONFIG_X86_MINIMUM_CPU_FAMILY=64 +CONFIG_X86_DEBUGCTLMSR=y +CONFIG_PROCESSOR_SELECT=y +CONFIG_CPU_SUP_INTEL=y +CONFIG_CPU_SUP_AMD=y +CONFIG_CPU_SUP_HYGON=y +CONFIG_CPU_SUP_CENTAUR=y +CONFIG_CPU_SUP_ZHAOXIN=y +CONFIG_HPET_TIMER=y +CONFIG_HPET_EMULATE_RTC=y +CONFIG_DMI=y +CONFIG_GART_IOMMU=y +CONFIG_CALGARY_IOMMU=y +CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y +# CONFIG_MAXSMP is not set +CONFIG_NR_CPUS_RANGE_BEGIN=2 +CONFIG_NR_CPUS_RANGE_END=512 +CONFIG_NR_CPUS_DEFAULT=64 +CONFIG_NR_CPUS=256 +CONFIG_SCHED_SMT=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_MC_PRIO=y +CONFIG_X86_LOCAL_APIC=y +CONFIG_X86_IO_APIC=y +CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y +CONFIG_X86_MCE=y +# CONFIG_X86_MCELOG_LEGACY is not set +CONFIG_X86_MCE_INTEL=y +CONFIG_X86_MCE_AMD=y +CONFIG_X86_MCE_THRESHOLD=y +# CONFIG_X86_MCE_INJECT is not set +CONFIG_X86_THERMAL_VECTOR=y + +# +# Performance monitoring +# +CONFIG_PERF_EVENTS_INTEL_UNCORE=y +CONFIG_PERF_EVENTS_INTEL_RAPL=y +CONFIG_PERF_EVENTS_INTEL_CSTATE=y +# CONFIG_PERF_EVENTS_AMD_POWER is not set +# end of Performance monitoring + +CONFIG_X86_16BIT=y +CONFIG_X86_ESPFIX64=y +CONFIG_X86_VSYSCALL_EMULATION=y +CONFIG_I8K=m +CONFIG_MICROCODE=y +CONFIG_MICROCODE_INTEL=y +CONFIG_MICROCODE_AMD=y +CONFIG_MICROCODE_OLD_INTERFACE=y +CONFIG_X86_MSR=m +CONFIG_X86_CPUID=m +# CONFIG_X86_5LEVEL is not set +CONFIG_X86_DIRECT_GBPAGES=y +# CONFIG_X86_CPA_STATISTICS is not set +CONFIG_ARCH_HAS_MEM_ENCRYPT=y +# CONFIG_AMD_MEM_ENCRYPT is not set +CONFIG_NUMA=y +CONFIG_AMD_NUMA=y +CONFIG_X86_64_ACPI_NUMA=y +CONFIG_NODES_SPAN_OTHER_NODES=y +# CONFIG_NUMA_EMU is not set +CONFIG_NODES_SHIFT=6 +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_MEMORY_PROBE=y +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +# CONFIG_X86_PMEM_LEGACY is not set +CONFIG_X86_CHECK_BIOS_CORRUPTION=y +CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y +CONFIG_X86_RESERVE_LOW=64 +CONFIG_MTRR=y +CONFIG_MTRR_SANITIZER=y +CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=1 +CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1 +CONFIG_X86_PAT=y +CONFIG_ARCH_USES_PG_UNCACHED=y +CONFIG_ARCH_RANDOM=y +CONFIG_X86_SMAP=y +CONFIG_X86_INTEL_UMIP=y +# CONFIG_X86_INTEL_MPX is not set +CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y +CONFIG_EFI=y +CONFIG_EFI_STUB=y +CONFIG_EFI_MIXED=y +CONFIG_SECCOMP=y +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_SCHED_HRTICK=y +CONFIG_KEXEC=y +CONFIG_KEXEC_FILE=y +CONFIG_ARCH_HAS_KEXEC_PURGATORY=y +CONFIG_KEXEC_VERIFY_SIG=y +CONFIG_CRASH_DUMP=y +CONFIG_KEXEC_JUMP=y +CONFIG_PHYSICAL_START=0x1000000 +CONFIG_RELOCATABLE=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_X86_NEED_RELOCS=y +CONFIG_PHYSICAL_ALIGN=0x1000000 +CONFIG_DYNAMIC_MEMORY_LAYOUT=y +CONFIG_RANDOMIZE_MEMORY=y +CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa +CONFIG_HOTPLUG_CPU=y +# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set +# CONFIG_DEBUG_HOTPLUG_CPU0 is not set +# CONFIG_COMPAT_VDSO is not set +CONFIG_LEGACY_VSYSCALL_EMULATE=y +# CONFIG_LEGACY_VSYSCALL_XONLY is not set +# CONFIG_LEGACY_VSYSCALL_NONE is not set +# CONFIG_CMDLINE_BOOL is not set +CONFIG_MODIFY_LDT_SYSCALL=y +CONFIG_HAVE_LIVEPATCH=y +# CONFIG_LIVEPATCH is not set +# end of Processor type and features + +CONFIG_ARCH_HAS_ADD_PAGES=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y + +# +# Power management and ACPI options +# +CONFIG_ARCH_HIBERNATION_HEADER=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +CONFIG_PM_STD_PARTITION="" +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=100 +CONFIG_PM_WAKELOCKS_GC=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_PM_SLEEP_DEBUG=y +# CONFIG_DPM_WATCHDOG is not set +CONFIG_PM_TRACE=y +CONFIG_PM_TRACE_RTC=y +CONFIG_PM_CLK=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +# CONFIG_ENERGY_MODEL is not set +CONFIG_ARCH_SUPPORTS_ACPI=y +CONFIG_ACPI=y +CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y +CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y +CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y +# CONFIG_ACPI_DEBUGGER is not set +CONFIG_ACPI_SPCR_TABLE=y +CONFIG_ACPI_LPIT=y +CONFIG_ACPI_SLEEP=y +# CONFIG_ACPI_PROCFS_POWER is not set +CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y +CONFIG_ACPI_EC_DEBUGFS=m +CONFIG_ACPI_AC=y +CONFIG_ACPI_BATTERY=y +CONFIG_ACPI_BUTTON=y +CONFIG_ACPI_VIDEO=m +CONFIG_ACPI_FAN=y +# CONFIG_ACPI_TAD is not set +CONFIG_ACPI_DOCK=y +CONFIG_ACPI_CPU_FREQ_PSS=y +CONFIG_ACPI_PROCESSOR_CSTATE=y +CONFIG_ACPI_PROCESSOR_IDLE=y +CONFIG_ACPI_CPPC_LIB=y +CONFIG_ACPI_PROCESSOR=y +CONFIG_ACPI_HOTPLUG_CPU=y +CONFIG_ACPI_PROCESSOR_AGGREGATOR=m +CONFIG_ACPI_THERMAL=y +CONFIG_ACPI_NUMA=y +CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y +CONFIG_ACPI_TABLE_UPGRADE=y +# CONFIG_ACPI_DEBUG is not set +CONFIG_ACPI_PCI_SLOT=y +CONFIG_ACPI_CONTAINER=y +CONFIG_ACPI_HOTPLUG_MEMORY=y +CONFIG_ACPI_HOTPLUG_IOAPIC=y +CONFIG_ACPI_SBS=m +CONFIG_ACPI_HED=y +# CONFIG_ACPI_CUSTOM_METHOD is not set +CONFIG_ACPI_BGRT=y +# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set +# CONFIG_ACPI_NFIT is not set +# CONFIG_ACPI_HMAT is not set +CONFIG_HAVE_ACPI_APEI=y +CONFIG_HAVE_ACPI_APEI_NMI=y +CONFIG_ACPI_APEI=y +CONFIG_ACPI_APEI_GHES=y +CONFIG_ACPI_APEI_PCIEAER=y +CONFIG_ACPI_APEI_MEMORY_FAILURE=y +CONFIG_ACPI_APEI_EINJ=m +# CONFIG_ACPI_APEI_ERST_DEBUG is not set +# CONFIG_DPTF_POWER is not set +# CONFIG_PMIC_OPREGION is not set +# CONFIG_ACPI_CONFIGFS is not set +CONFIG_X86_PM_TIMER=y +CONFIG_SFI=y + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set + +# +# CPU frequency scaling drivers +# +CONFIG_X86_INTEL_PSTATE=y +# CONFIG_X86_PCC_CPUFREQ is not set +CONFIG_X86_ACPI_CPUFREQ=y +# CONFIG_X86_ACPI_CPUFREQ_CPB is not set +# CONFIG_X86_POWERNOW_K8 is not set +# CONFIG_X86_AMD_FREQ_SENSITIVITY is not set +# CONFIG_X86_SPEEDSTEP_CENTRINO is not set +# CONFIG_X86_P4_CLOCKMOD is not set + +# +# shared options +# +# end of CPU Frequency scaling + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE_GOV_TEO is not set +# end of CPU Idle + +# CONFIG_INTEL_IDLE is not set +# end of Power management and ACPI options + +# +# Bus options (PCI etc.) +# +CONFIG_PCI_DIRECT=y +CONFIG_PCI_MMCONFIG=y +CONFIG_MMCONF_FAM10H=y +# CONFIG_PCI_CNB20LE_QUIRK is not set +# CONFIG_ISA_BUS is not set +CONFIG_ISA_DMA_API=y +CONFIG_AMD_NB=y +# CONFIG_X86_SYSFB is not set +# end of Bus options (PCI etc.) + +# +# Binary Emulations +# +CONFIG_IA32_EMULATION=y +# CONFIG_X86_X32 is not set +CONFIG_COMPAT_32=y +CONFIG_COMPAT=y +CONFIG_COMPAT_FOR_U64_ALIGNMENT=y +CONFIG_SYSVIPC_COMPAT=y +# end of Binary Emulations + +# +# Firmware Drivers +# +# CONFIG_EDD is not set +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_DMIID=y +# CONFIG_DMI_SYSFS is not set +CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_VARS=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_VARS_PSTORE=y +# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set +CONFIG_EFI_RUNTIME_MAP=y +# CONFIG_EFI_FAKE_MEMMAP is not set +CONFIG_EFI_RUNTIME_WRAPPERS=y +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_TEST is not set +# CONFIG_APPLE_PROPERTIES is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +# end of EFI (Extensible Firmware Interface) Support + +CONFIG_UEFI_CPER=y +CONFIG_UEFI_CPER_X86=y +CONFIG_EFI_EARLYCON=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +CONFIG_HAVE_KVM=y +CONFIG_VIRTUALIZATION=y +# CONFIG_KVM is not set +# CONFIG_VHOST_NET is not set +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set + +# +# General architecture-dependent options +# +CONFIG_CRASH_CORE=y +CONFIG_KEXEC_CORE=y +CONFIG_HOTPLUG_SMT=y +CONFIG_OPROFILE=m +# CONFIG_OPROFILE_EVENT_MULTIPLEX is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_OPROFILE_NMI_TIMER=y +CONFIG_KPROBES=y +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +CONFIG_OPTPROBES=y +CONFIG_KPROBES_ON_FTRACE=y +CONFIG_UPROBES=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_KRETPROBES=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_KPROBES_ON_FTRACE=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y +CONFIG_HAVE_USER_RETURN_NOTIFIER=y +CONFIG_HAVE_PERF_EVENTS_NMI=y +CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_STACKLEAK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_CC_HAS_STACKPROTECTOR_NONE=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_HAVE_ARCH_SOFT_DIRTY=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS=28 +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 +CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y +CONFIG_HAVE_COPY_THREAD_TLS=y +CONFIG_HAVE_STACK_VALIDATION=y +CONFIG_HAVE_RELIABLE_STACKTRACE=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_COMPAT_OLD_SIGACTION=y +CONFIG_64BIT_TIME=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_REFCOUNT=y +# CONFIG_REFCOUNT_FULL is not set +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +# CONFIG_LOCK_EVENT_COUNTS is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_PLUGIN_HOSTCC="" +CONFIG_HAVE_GCC_PLUGINS=y +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_SIG=y +# CONFIG_MODULE_SIG_FORCE is not set +CONFIG_MODULE_SIG_ALL=y +# CONFIG_MODULE_SIG_SHA1 is not set +# CONFIG_MODULE_SIG_SHA224 is not set +# CONFIG_MODULE_SIG_SHA256 is not set +# CONFIG_MODULE_SIG_SHA384 is not set +CONFIG_MODULE_SIG_SHA512=y +CONFIG_MODULE_SIG_HASH="sha512" +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +# CONFIG_BLK_DEV_ZONED is not set +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +CONFIG_BLK_CMDLINE_PARSER=y +# CONFIG_BLK_WBT is not set +# CONFIG_BLK_CGROUP_IOLATENCY is not set +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_SED_OPAL is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set +# end of Partition Types + +CONFIG_BLOCK_COMPAT=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +# CONFIG_IOSCHED_BFQ is not set +# end of IO Schedulers + +CONFIG_ASN1=y +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +CONFIG_BINFMT_MISC=y +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_NEED_MULTIPLE_NODES=y +CONFIG_HAVE_MEMORY_PRESENT=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_HAVE_BOOTMEM_INFO_NODE=y +CONFIG_MEMORY_HOTPLUG=y +CONFIG_MEMORY_HOTPLUG_SPARSE=y +# CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set +CONFIG_MEMORY_HOTREMOVE=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +CONFIG_CONTIG_ALLOC=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_MMU_NOTIFIER=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +CONFIG_MEMORY_FAILURE=y +CONFIG_HWPOISON_INJECT=m +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_THP_SWAP=y +CONFIG_TRANSPARENT_HUGE_PAGECACHE=y +CONFIG_CLEANCACHE=y +CONFIG_FRONTSWAP=y +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_AREAS=7 +CONFIG_MEM_SOFT_DIRTY=y +CONFIG_ZSWAP=y +CONFIG_ZPOOL=y +CONFIG_ZBUD=y +# CONFIG_Z3FOLD is not set +CONFIG_ZSMALLOC=y +CONFIG_PGTABLE_MAPPING=y +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_PTE_DEVMAP=y +CONFIG_ZONE_DEVICE=y +CONFIG_HMM_MIRROR=y +# CONFIG_DEVICE_PRIVATE is not set +CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y +CONFIG_ARCH_HAS_PKEYS=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_BENCHMARK is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +# end of Memory Management options + +CONFIG_NET=y +CONFIG_NET_INGRESS=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=y +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +CONFIG_UNIX_DIAG=y +# CONFIG_TLS is not set +CONFIG_XFRM=y +CONFIG_XFRM_ALGO=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_INTERFACE is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +# CONFIG_XDP_SOCKETS is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE=y +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_RAW_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +CONFIG_TCP_CONG_ADVANCED=y +# CONFIG_TCP_CONG_BIC is not set +CONFIG_TCP_CONG_CUBIC=y +# CONFIG_TCP_CONG_WESTWOOD is not set +# CONFIG_TCP_CONG_HTCP is not set +# CONFIG_TCP_CONG_HSTCP is not set +# CONFIG_TCP_CONG_HYBLA is not set +# CONFIG_TCP_CONG_VEGAS is not set +# CONFIG_TCP_CONG_NV is not set +# CONFIG_TCP_CONG_SCALABLE is not set +# CONFIG_TCP_CONG_LP is not set +# CONFIG_TCP_CONG_VENO is not set +# CONFIG_TCP_CONG_YEAH is not set +# CONFIG_TCP_CONG_ILLINOIS is not set +# CONFIG_TCP_CONG_DCTCP is not set +# CONFIG_TCP_CONG_CDG is not set +# CONFIG_TCP_CONG_BBR is not set +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +# CONFIG_INET6_ESP_OFFLOAD is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_IPV6_ILA is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +CONFIG_NETLABEL=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NET_PTP_CLASSIFY=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=m + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_FAMILY_ARP=y +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_COMMON=m +# CONFIG_NF_LOG_NETDEV is not set +CONFIG_NETFILTER_CONNCOUNT=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +# CONFIG_NF_CONNTRACK_AMANDA is not set +# CONFIG_NF_CONNTRACK_FTP is not set +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +# CONFIG_NF_CT_NETLINK is not set +# CONFIG_NF_CT_NETLINK_TIMEOUT is not set +CONFIG_NF_NAT=m +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_SET=m +# CONFIG_NF_TABLES_INET is not set +CONFIG_NF_TABLES_NETDEV=y +# CONFIG_NFT_NUMGEN is not set +CONFIG_NFT_CT=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +# CONFIG_NFT_OBJREF is not set +# CONFIG_NFT_QUEUE is not set +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +# CONFIG_NFT_COMPAT is not set +# CONFIG_NFT_HASH is not set +CONFIG_NFT_FIB=m +CONFIG_NFT_XFRM=m +# CONFIG_NFT_SOCKET is not set +# CONFIG_NFT_OSF is not set +# CONFIG_NFT_TPROXY is not set +# CONFIG_NFT_SYNPROXY is not set +CONFIG_NF_DUP_NETDEV=m +# CONFIG_NFT_DUP_NETDEV is not set +# CONFIG_NFT_FWD_NETDEV is not set +# CONFIG_NFT_FIB_NETDEV is not set +# CONFIG_NF_FLOW_TABLE is not set +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# end of Core Netfilter Configuration + +# CONFIG_IP_SET is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +# CONFIG_NF_SOCKET_IPV4 is not set +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TABLES_IPV4=y +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_DUP_IPV4=m +# CONFIG_NF_LOG_ARP is not set +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +# end of IP: Netfilter Configuration + +# +# IPv6: Netfilter Configuration +# +# CONFIG_NF_SOCKET_IPV6 is not set +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NF_TABLES_IPV6=y +CONFIG_NFT_REJECT_IPV6=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_LOG_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_RPFILTER is not set +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_MATCH_SRH is not set +# CONFIG_IP6_NF_TARGET_HL is not set +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +# CONFIG_IP6_NF_TARGET_SYNPROXY is not set +CONFIG_IP6_NF_MANGLE=m +# CONFIG_IP6_NF_RAW is not set +# CONFIG_IP6_NF_SECURITY is not set +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +# CONFIG_IP6_NF_TARGET_NPT is not set +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=m +# CONFIG_NF_TABLES_BRIDGE is not set +# CONFIG_NF_CONNTRACK_BRIDGE is not set +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_BPFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_STP=y +CONFIG_BRIDGE=y +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_BRIDGE_VLAN_FILTERING is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_VLAN_8021Q_MVRP is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFB is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_CBS is not set +# CONFIG_NET_SCH_ETF is not set +# CONFIG_NET_SCH_TAPRIO is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_SKBPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_CODEL is not set +# CONFIG_NET_SCH_FQ_CODEL is not set +# CONFIG_NET_SCH_CAKE is not set +# CONFIG_NET_SCH_FQ is not set +# CONFIG_NET_SCH_HHF is not set +# CONFIG_NET_SCH_PIE is not set +# CONFIG_NET_SCH_INGRESS is not set +# CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +# CONFIG_NET_CLS_U32 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_CLS_CGROUP is not set +# CONFIG_NET_CLS_BPF is not set +# CONFIG_NET_CLS_FLOWER is not set +# CONFIG_NET_CLS_MATCHALL is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +# CONFIG_NET_EMATCH_CMP is not set +# CONFIG_NET_EMATCH_NBYTE is not set +# CONFIG_NET_EMATCH_U32 is not set +# CONFIG_NET_EMATCH_META is not set +# CONFIG_NET_EMATCH_TEXT is not set +# CONFIG_NET_EMATCH_IPT is not set +CONFIG_NET_CLS_ACT=y +# CONFIG_NET_ACT_POLICE is not set +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_SAMPLE is not set +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_ACT_MPLS is not set +# CONFIG_NET_ACT_VLAN is not set +# CONFIG_NET_ACT_BPF is not set +# CONFIG_NET_ACT_CONNMARK is not set +# CONFIG_NET_ACT_CTINFO is not set +# CONFIG_NET_ACT_SKBMOD is not set +# CONFIG_NET_ACT_IFE is not set +# CONFIG_NET_ACT_TUNNEL_KEY is not set +# CONFIG_NET_ACT_CT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +CONFIG_NETLINK_DIAG=y +# CONFIG_MPLS is not set +# CONFIG_NET_NSH is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +# CONFIG_CGROUP_NET_PRIO is not set +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set +# CONFIG_BPF_STREAM_PARSER is not set +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_DROP_MONITOR is not set +# end of Network testing +# end of Networking options + +CONFIG_HAMRADIO=y + +# +# Packet Radio protocols +# +# CONFIG_AX25 is not set +# CONFIG_CAN is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +CONFIG_RFKILL_LEDS=y +CONFIG_RFKILL_INPUT=y +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_PSAMPLE is not set +# CONFIG_NET_IFE is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +# CONFIG_FAILOVER is not set +CONFIG_HAVE_EBPF_JIT=y + +# +# Device Drivers +# +CONFIG_HAVE_EISA=y +# CONFIG_EISA is not set +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCIEPORTBUS=y +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_PCIEAER=y +# CONFIG_PCIEAER_INJECT is not set +# CONFIG_PCIE_ECRC is not set +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEBUG=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +CONFIG_PCIE_PME=y +# CONFIG_PCIE_DPC is not set +# CONFIG_PCIE_PTM is not set +# CONFIG_PCIE_BW is not set +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=y +# CONFIG_PCI_PF_STUB is not set +CONFIG_PCI_ATS=y +CONFIG_PCI_LOCKLESS_CONFIG=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +# CONFIG_PCI_P2PDMA is not set +CONFIG_PCI_LABEL=y +CONFIG_HOTPLUG_PCI=y +# CONFIG_HOTPLUG_PCI_ACPI is not set +# CONFIG_HOTPLUG_PCI_CPCI is not set +# CONFIG_HOTPLUG_PCI_SHPC is not set + +# +# PCI controller drivers +# + +# +# Cadence PCIe controllers support +# +# end of Cadence PCIe controllers support + +# CONFIG_VMD is not set + +# +# DesignWare PCI Core Support +# +# CONFIG_PCIE_DW_PLAT_HOST is not set +# CONFIG_PCI_MESON is not set +# end of DesignWare PCI Core Support +# end of PCI controller drivers + +# +# PCI Endpoint +# +# CONFIG_PCI_ENDPOINT is not set +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +# CONFIG_PCI_SW_SWITCHTEC is not set +# end of PCI switch controller drivers + +# CONFIG_PCCARD is not set +CONFIG_RAPIDIO=y +# CONFIG_RAPIDIO_TSI721 is not set +CONFIG_RAPIDIO_DISC_TIMEOUT=30 +# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set +CONFIG_RAPIDIO_DMA_ENGINE=y +# CONFIG_RAPIDIO_DEBUG is not set +# CONFIG_RAPIDIO_ENUM_BASIC is not set +# CONFIG_RAPIDIO_CHMAN is not set +# CONFIG_RAPIDIO_MPORT_CDEV is not set + +# +# RapidIO Switch drivers +# +# CONFIG_RAPIDIO_TSI57X is not set +# CONFIG_RAPIDIO_CPS_XX is not set +# CONFIG_RAPIDIO_TSI568 is not set +# CONFIG_RAPIDIO_CPS_GEN2 is not set +# CONFIG_RAPIDIO_RXS_GEN3 is not set +# end of RapidIO Switch drivers + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_COMPRESS is not set +# end of Firmware loader + +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +# end of Generic Driver Options + +# +# Bus devices +# +# end of Bus devices + +# CONFIG_CONNECTOR is not set +# CONFIG_GNSS is not set +# CONFIG_MTD is not set +# CONFIG_OF is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_PARPORT=y +CONFIG_PARPORT_PC=y +CONFIG_PARPORT_SERIAL=y +# CONFIG_PARPORT_PC_FIFO is not set +# CONFIG_PARPORT_PC_SUPERIO is not set +# CONFIG_PARPORT_AX88796 is not set +# CONFIG_PARPORT_1284 is not set +CONFIG_PNP=y +CONFIG_PNP_DEBUG_MESSAGES=y + +# +# Protocols +# +CONFIG_PNPACPI=y +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +# CONFIG_BLK_DEV_FD is not set +CONFIG_CDROM=y +# CONFIG_PARIDE is not set +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_ZRAM is not set +# CONFIG_BLK_DEV_UMEM is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SKD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set + +# +# NVME Support +# +CONFIG_NVME_CORE=y +CONFIG_BLK_DEV_NVME=y +# CONFIG_NVME_MULTIPATH is not set +# CONFIG_NVME_FC is not set +# CONFIG_NVME_TCP is not set +# CONFIG_NVME_TARGET is not set +# end of NVME Support + +# +# Misc devices +# +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_IBM_ASM is not set +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_SRAM is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_XILINX_SDFEC is not set +# CONFIG_PVPANIC is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_EE1004 is not set +# end of EEPROM support + +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# end of Texas Instruments shared transport line discipline + +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_ALTERA_STAPL is not set +# CONFIG_INTEL_MEI is not set +# CONFIG_INTEL_MEI_ME is not set +# CONFIG_INTEL_MEI_TXE is not set +# CONFIG_VMWARE_VMCI is not set + +# +# Intel MIC & related support +# + +# +# Intel MIC Bus Driver +# +# CONFIG_INTEL_MIC_BUS is not set + +# +# SCIF Bus Driver +# +# CONFIG_SCIF_BUS is not set + +# +# VOP Bus Driver +# +# CONFIG_VOP_BUS is not set + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# end of Intel MIC & related support + +# CONFIG_GENWQE is not set +# CONFIG_ECHO is not set +# CONFIG_MISC_ALCOR_PCI is not set +# CONFIG_MISC_RTSX_PCI is not set +# CONFIG_MISC_RTSX_USB is not set +# CONFIG_HABANA_AI is not set +# end of Misc devices + +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=y +# CONFIG_SCSI_FC_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=y +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# end of SCSI Transports + +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# end of SCSI device support + +CONFIG_ATA=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_ACPI=y +# CONFIG_SATA_ZPODD is not set +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI=y +CONFIG_SATA_MOBILE_LPM_POLICY=0 +CONFIG_SATA_AHCI_PLATFORM=y +# CONFIG_SATA_INIC162X is not set +# CONFIG_SATA_ACARD_AHCI is not set +CONFIG_SATA_SIL24=y +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +CONFIG_SATA_SX4=y +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +CONFIG_ATA_PIIX=y +# CONFIG_SATA_DWC is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +CONFIG_SATA_PROMISE=y +CONFIG_SATA_SIL=y +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_SVW is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set + +# +# PATA SFF controllers with BMDMA +# +# CONFIG_PATA_ALI is not set +CONFIG_PATA_AMD=y +# CONFIG_PATA_ARTOP is not set +CONFIG_PATA_ATIIXP=y +# CONFIG_PATA_ATP867X is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87415 is not set +CONFIG_PATA_OLDPIIX=y +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +CONFIG_PATA_SCH=y +CONFIG_PATA_SERVERWORKS=y +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set + +# +# PIO-only SFF controllers +# +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_RZ1000 is not set + +# +# Generic fallback / legacy drivers +# +# CONFIG_PATA_ACPI is not set +CONFIG_ATA_GENERIC=y +# CONFIG_PATA_LEGACY is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_RAID0 is not set +# CONFIG_MD_RAID1 is not set +# CONFIG_MD_RAID10 is not set +# CONFIG_MD_RAID456 is not set +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +# CONFIG_BCACHE is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +# CONFIG_DM_UNSTRIPED is not set +# CONFIG_DM_CRYPT is not set +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_THIN_PROVISIONING is not set +# CONFIG_DM_CACHE is not set +# CONFIG_DM_WRITECACHE is not set +# CONFIG_DM_ERA is not set +CONFIG_DM_MIRROR=y +# CONFIG_DM_LOG_USERSPACE is not set +# CONFIG_DM_RAID is not set +CONFIG_DM_ZERO=y +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_DUST is not set +# CONFIG_DM_INIT is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_DM_FLAKEY is not set +# CONFIG_DM_VERITY is not set +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_LOG_WRITES is not set +# CONFIG_DM_INTEGRITY is not set +# CONFIG_TARGET_CORE is not set +CONFIG_FUSION=y +CONFIG_FUSION_SPI=y +# CONFIG_FUSION_SAS is not set +CONFIG_FUSION_MAX_SGE=128 +# CONFIG_FUSION_CTL is not set +# CONFIG_FUSION_LOGGING is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# end of IEEE 1394 (FireWire) support + +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +# CONFIG_IFB is not set +# CONFIG_NET_TEAM is not set +CONFIG_MACVLAN=y +# CONFIG_MACVTAP is not set +# CONFIG_IPVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_GENEVE is not set +# CONFIG_GTP is not set +# CONFIG_MACSEC is not set +CONFIG_NETCONSOLE=y +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_NETPOLL=y +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_RIONET is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=y +# CONFIG_NLMON is not set +# CONFIG_ARCNET is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +# end of Distributed Switch Architecture drivers + +CONFIG_ETHERNET=y +CONFIG_MDIO=y +CONFIG_NET_VENDOR_3COM=y +# CONFIG_VORTEX is not set +# CONFIG_TYPHOON is not set +CONFIG_NET_VENDOR_ADAPTEC=y +# CONFIG_ADAPTEC_STARFIRE is not set +CONFIG_NET_VENDOR_AGERE=y +# CONFIG_ET131X is not set +CONFIG_NET_VENDOR_ALACRITECH=y +# CONFIG_SLICOSS is not set +CONFIG_NET_VENDOR_ALTEON=y +# CONFIG_ACENIC is not set +# CONFIG_ALTERA_TSE is not set +CONFIG_NET_VENDOR_AMAZON=y +# CONFIG_ENA_ETHERNET is not set +CONFIG_NET_VENDOR_AMD=y +# CONFIG_AMD8111_ETH is not set +# CONFIG_PCNET32 is not set +# CONFIG_AMD_XGBE is not set +CONFIG_NET_VENDOR_AQUANTIA=y +# CONFIG_AQTION is not set +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ATHEROS=y +# CONFIG_ATL2 is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +CONFIG_ALX=y +# CONFIG_NET_VENDOR_AURORA is not set +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_B44 is not set +# CONFIG_BCMGENET is not set +CONFIG_BNX2=y +# CONFIG_CNIC is not set +CONFIG_TIGON3=y +CONFIG_TIGON3_HWMON=y +# CONFIG_BNX2X is not set +# CONFIG_SYSTEMPORT is not set +# CONFIG_BNXT is not set +CONFIG_NET_VENDOR_BROCADE=y +# CONFIG_BNA is not set +CONFIG_NET_VENDOR_CADENCE=y +# CONFIG_MACB is not set +CONFIG_NET_VENDOR_CAVIUM=y +# CONFIG_THUNDER_NIC_PF is not set +# CONFIG_THUNDER_NIC_VF is not set +# CONFIG_THUNDER_NIC_BGX is not set +# CONFIG_THUNDER_NIC_RGX is not set +CONFIG_CAVIUM_PTP=y +# CONFIG_LIQUIDIO is not set +# CONFIG_LIQUIDIO_VF is not set +CONFIG_NET_VENDOR_CHELSIO=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_CHELSIO_T4 is not set +# CONFIG_CHELSIO_T4VF is not set +CONFIG_NET_VENDOR_CISCO=y +# CONFIG_ENIC is not set +CONFIG_NET_VENDOR_CORTINA=y +# CONFIG_CX_ECAT is not set +# CONFIG_DNET is not set +CONFIG_NET_VENDOR_DEC=y +CONFIG_NET_TULIP=y +# CONFIG_DE2104X is not set +# CONFIG_TULIP is not set +# CONFIG_DE4X5 is not set +# CONFIG_WINBOND_840 is not set +# CONFIG_DM9102 is not set +# CONFIG_ULI526X is not set +CONFIG_NET_VENDOR_DLINK=y +# CONFIG_DL2K is not set +# CONFIG_SUNDANCE is not set +CONFIG_NET_VENDOR_EMULEX=y +# CONFIG_BE2NET is not set +CONFIG_NET_VENDOR_EZCHIP=y +CONFIG_NET_VENDOR_GOOGLE=y +# CONFIG_GVE is not set +CONFIG_NET_VENDOR_HP=y +# CONFIG_HP100 is not set +CONFIG_NET_VENDOR_HUAWEI=y +# CONFIG_HINIC is not set +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_INTEL=y +CONFIG_E100=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_E1000E_HWTS=y +CONFIG_IGB=y +CONFIG_IGB_HWMON=y +CONFIG_IGBVF=y +CONFIG_IXGB=y +CONFIG_IXGBE=y +CONFIG_IXGBE_HWMON=y +# CONFIG_IXGBEVF is not set +CONFIG_I40E=y +# CONFIG_I40EVF is not set +# CONFIG_ICE is not set +# CONFIG_FM10K is not set +# CONFIG_IGC is not set +# CONFIG_JME is not set +CONFIG_NET_VENDOR_MARVELL=y +# CONFIG_MVMDIO is not set +# CONFIG_SKGE is not set +CONFIG_SKY2=y +# CONFIG_SKY2_DEBUG is not set +CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_MLX4_EN is not set +# CONFIG_MLX5_CORE is not set +# CONFIG_MLXSW_CORE is not set +# CONFIG_MLXFW is not set +CONFIG_NET_VENDOR_MICREL=y +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_KSZ884X_PCI is not set +CONFIG_NET_VENDOR_MICROCHIP=y +# CONFIG_LAN743X is not set +CONFIG_NET_VENDOR_MICROSEMI=y +CONFIG_NET_VENDOR_MYRI=y +# CONFIG_MYRI10GE is not set +# CONFIG_FEALNX is not set +CONFIG_NET_VENDOR_NATSEMI=y +# CONFIG_NATSEMI is not set +# CONFIG_NS83820 is not set +CONFIG_NET_VENDOR_NETERION=y +# CONFIG_S2IO is not set +# CONFIG_VXGE is not set +CONFIG_NET_VENDOR_NETRONOME=y +# CONFIG_NFP is not set +CONFIG_NET_VENDOR_NI=y +# CONFIG_NI_XGE_MANAGEMENT_ENET is not set +CONFIG_NET_VENDOR_8390=y +# CONFIG_NE2K_PCI is not set +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_FORCEDETH=y +CONFIG_NET_VENDOR_OKI=y +# CONFIG_ETHOC is not set +CONFIG_NET_VENDOR_PACKET_ENGINES=y +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +CONFIG_NET_VENDOR_QLOGIC=y +# CONFIG_QLA3XXX is not set +# CONFIG_QLCNIC is not set +# CONFIG_QLGE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_QED is not set +CONFIG_NET_VENDOR_QUALCOMM=y +# CONFIG_QCOM_EMAC is not set +# CONFIG_RMNET is not set +CONFIG_NET_VENDOR_RDC=y +# CONFIG_R6040 is not set +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_ATP is not set +CONFIG_8139CP=y +CONFIG_8139TOO=y +CONFIG_8139TOO_PIO=y +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139TOO_8129 is not set +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_R8169=y +CONFIG_NET_VENDOR_RENESAS=y +CONFIG_NET_VENDOR_ROCKER=y +CONFIG_NET_VENDOR_SAMSUNG=y +# CONFIG_SXGBE_ETH is not set +CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SOLARFLARE=y +# CONFIG_SFC is not set +# CONFIG_SFC_FALCON is not set +CONFIG_NET_VENDOR_SILAN=y +# CONFIG_SC92031 is not set +CONFIG_NET_VENDOR_SIS=y +# CONFIG_SIS900 is not set +# CONFIG_SIS190 is not set +CONFIG_NET_VENDOR_SMSC=y +# CONFIG_EPIC100 is not set +# CONFIG_SMSC911X is not set +# CONFIG_SMSC9420 is not set +CONFIG_NET_VENDOR_SOCIONEXT=y +CONFIG_NET_VENDOR_STMICRO=y +# CONFIG_STMMAC_ETH is not set +CONFIG_NET_VENDOR_SUN=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NIU is not set +CONFIG_NET_VENDOR_SYNOPSYS=y +# CONFIG_DWC_XLGMAC is not set +CONFIG_NET_VENDOR_TEHUTI=y +# CONFIG_TEHUTI is not set +CONFIG_NET_VENDOR_TI=y +# CONFIG_TI_CPSW_PHY_SEL is not set +# CONFIG_TLAN is not set +CONFIG_NET_VENDOR_VIA=y +# CONFIG_VIA_RHINE is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_NET_VENDOR_WIZNET=y +CONFIG_WIZNET_W5100=y +CONFIG_WIZNET_W5300=y +# CONFIG_WIZNET_BUS_DIRECT is not set +# CONFIG_WIZNET_BUS_INDIRECT is not set +CONFIG_WIZNET_BUS_ANY=y +CONFIG_NET_VENDOR_XILINX=y +# CONFIG_XILINX_AXI_EMAC is not set +# CONFIG_XILINX_LL_TEMAC is not set +CONFIG_FDDI=y +# CONFIG_DEFXX is not set +# CONFIG_SKFP is not set +# CONFIG_HIPPI is not set +# CONFIG_NET_SB1000 is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_THUNDER is not set +CONFIG_PHYLIB=y +# CONFIG_LED_TRIGGER_PHY is not set + +# +# MII PHY device drivers +# +CONFIG_AMD_PHY=y +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AX88796B_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CORTINA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +# CONFIG_QSEMI_PHY is not set +CONFIG_REALTEK_PHY=y +# CONFIG_RENESAS_PHY is not set +# CONFIG_ROCKCHIP_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_PLIP is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=m +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +CONFIG_USB_RTL8152=m +# CONFIG_USB_LAN78XX is not set +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +# CONFIG_USB_NET_CDC_EEM is not set +CONFIG_USB_NET_CDC_NCM=m +# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set +# CONFIG_USB_NET_CDC_MBIM is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SR9700 is not set +# CONFIG_USB_NET_SR9800 is not set +# CONFIG_USB_NET_SMSC75XX is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_GL620A is not set +CONFIG_USB_NET_NET1080=m +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +CONFIG_USB_NET_CDC_SUBSET_ENABLE=m +CONFIG_USB_NET_CDC_SUBSET=m +# CONFIG_USB_ALI_M5632 is not set +# CONFIG_USB_AN2720 is not set +CONFIG_USB_BELKIN=y +# CONFIG_USB_ARMLINUX is not set +# CONFIG_USB_EPSON2888 is not set +# CONFIG_USB_KC2190 is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_USB_NET_CX82310_ETH is not set +# CONFIG_USB_NET_KALMIA is not set +# CONFIG_USB_NET_QMI_WWAN is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_USB_SIERRA_NET is not set +# CONFIG_USB_VL600 is not set +# CONFIG_USB_NET_CH9200 is not set +# CONFIG_USB_NET_AQC111 is not set +CONFIG_WLAN=y +# CONFIG_WIRELESS_WDS is not set +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH5K_PCI is not set +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_WLAN_VENDOR_BROADCOM=y +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +# CONFIG_HOSTAP is not set +# CONFIG_PRISM54 is not set +CONFIG_WLAN_VENDOR_MARVELL=y +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +CONFIG_WLAN_VENDOR_QUANTENNA=y + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_FUJITSU_ES is not set +# CONFIG_NETDEVSIM is not set +# CONFIG_NET_FAILOVER is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_FF_MEMLESS=y +CONFIG_INPUT_POLLDEV=y +CONFIG_INPUT_SPARSEKMAP=y +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_PS2_FOCALTECH=y +# CONFIG_MOUSE_PS2_VMMOUSE is not set +CONFIG_MOUSE_PS2_SMBUS=y +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +# CONFIG_MOUSE_ELAN_I2C is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_PARKBD is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_USERIO is not set +# CONFIG_GAMEPORT is not set +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_ROCKETPORT is not set +# CONFIG_CYCLADES is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_SYNCLINK is not set +# CONFIG_SYNCLINKMP is not set +# CONFIG_SYNCLINK_GT is not set +# CONFIG_NOZOMI is not set +# CONFIG_ISI is not set +# CONFIG_N_HDLC is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +# CONFIG_NULL_TTY is not set +CONFIG_LDISC_AUTOLOAD=y +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_PNP=y +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y +# CONFIG_SERIAL_8250_DW is not set +# CONFIG_SERIAL_8250_RT288X is not set +CONFIG_SERIAL_8250_LPSS=y +# CONFIG_SERIAL_8250_MID is not set +# CONFIG_SERIAL_8250_MOXA is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_KGDB_NMI is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# end of Serial drivers + +# CONFIG_SERIAL_DEV_BUS is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_PRINTER is not set +# CONFIG_PPDEV is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_APPLICOM is not set +# CONFIG_MWAVE is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HPET is not set +# CONFIG_HANGCHECK_TIMER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_TELCLOCK is not set +CONFIG_DEVPORT=y +# CONFIG_XILLYBUS is not set +# end of Character devices + +# CONFIG_RANDOM_TRUST_CPU is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_ACPI_I2C_OPREGION=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +# CONFIG_I2C_CHARDEV is not set +# CONFIG_I2C_MUX is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_SMBUS=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_AMD_MP2 is not set +CONFIG_I2C_I801=y +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_ISMT is not set +CONFIG_I2C_PIIX4=m +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_NVIDIA_GPU is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# ACPI drivers +# +# CONFIG_I2C_SCMI is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_MLXCPLD is not set +# end of I2C Hardware Bus support + +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +# CONFIG_I3C is not set +# CONFIG_SPI is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_PARPORT is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PTP_1588_CLOCK_KVM=y +# end of PTP clock support + +CONFIG_PINCTRL=y +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_SX150X is not set +# CONFIG_PINCTRL_BAYTRAIL is not set +# CONFIG_PINCTRL_CHERRYVIEW is not set +# CONFIG_PINCTRL_BROXTON is not set +# CONFIG_PINCTRL_CANNONLAKE is not set +# CONFIG_PINCTRL_CEDARFORK is not set +# CONFIG_PINCTRL_DENVERTON is not set +# CONFIG_PINCTRL_GEMINILAKE is not set +# CONFIG_PINCTRL_ICELAKE is not set +# CONFIG_PINCTRL_LEWISBURG is not set +# CONFIG_PINCTRL_SUNRISEPOINT is not set +# CONFIG_GPIOLIB is not set +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +# CONFIG_POWER_RESET is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_CHARGER_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_ABITUGURU3 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_K8TEMP is not set +CONFIG_SENSORS_K10TEMP=m +# CONFIG_SENSORS_FAM15H_POWER is not set +# CONFIG_SENSORS_APPLESMC is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ASPEED is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +CONFIG_SENSORS_DELL_SMM=m +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_FSCHMD is not set +# CONFIG_SENSORS_FTSTEUTATES is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_I5500 is not set +# CONFIG_SENSORS_CORETEMP is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX6621 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MAX31790 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_TC74 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP108 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VIA_CPUTEMP is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83773G is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_XGENE is not set + +# +# ACPI drivers +# +# CONFIG_SENSORS_ACPI_POWER is not set +# CONFIG_SENSORS_ATK0110 is not set +CONFIG_THERMAL=y +# CONFIG_THERMAL_STATISTICS is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_BANG_BANG is not set +CONFIG_THERMAL_GOV_USER_SPACE=y +# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set +# CONFIG_THERMAL_EMULATION is not set + +# +# Intel thermal drivers +# +# CONFIG_INTEL_POWERCLAMP is not set +CONFIG_X86_PKG_TEMP_THERMAL=m +# CONFIG_INTEL_SOC_DTS_THERMAL is not set + +# +# ACPI INT340X thermal drivers +# +# CONFIG_INT340X_THERMAL is not set +# end of ACPI INT340X thermal drivers + +# CONFIG_INTEL_PCH_THERMAL is not set +# end of Intel thermal drivers + +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Pretimeout Governors +# + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_WDAT_WDT is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_ACQUIRE_WDT is not set +# CONFIG_ADVANTECH_WDT is not set +# CONFIG_ALIM1535_WDT is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_EBC_C384_WDT is not set +# CONFIG_F71808E_WDT is not set +# CONFIG_SP5100_TCO is not set +# CONFIG_SBC_FITPC2_WATCHDOG is not set +# CONFIG_EUROTECH_WDT is not set +# CONFIG_IB700_WDT is not set +# CONFIG_IBMASR is not set +# CONFIG_WAFER_WDT is not set +# CONFIG_I6300ESB_WDT is not set +# CONFIG_IE6XX_WDT is not set +# CONFIG_ITCO_WDT is not set +# CONFIG_IT8712F_WDT is not set +# CONFIG_IT87_WDT is not set +# CONFIG_HP_WATCHDOG is not set +# CONFIG_SC1200_WDT is not set +# CONFIG_PC87413_WDT is not set +# CONFIG_NV_TCO is not set +# CONFIG_60XX_WDT is not set +# CONFIG_CPU5_WDT is not set +# CONFIG_SMSC_SCH311X_WDT is not set +# CONFIG_SMSC37B787_WDT is not set +# CONFIG_TQMX86_WDT is not set +# CONFIG_VIA_WDT is not set +# CONFIG_W83627HF_WDT is not set +# CONFIG_W83877F_WDT is not set +# CONFIG_W83977F_WDT is not set +# CONFIG_MACHZ_WDT is not set +# CONFIG_SBC_EPX_C3_WATCHDOG is not set +# CONFIG_NI903X_WDT is not set +# CONFIG_NIC7018_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_AS3711 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_INTEL_LPSS_ACPI is not set +# CONFIG_MFD_INTEL_LPSS_PCI is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# end of Multifunction device drivers + +# CONFIG_REGULATOR is not set +CONFIG_RC_CORE=y +CONFIG_RC_MAP=y +# CONFIG_LIRC is not set +CONFIG_RC_DECODERS=y +CONFIG_IR_NEC_DECODER=y +CONFIG_IR_RC5_DECODER=y +CONFIG_IR_RC6_DECODER=y +CONFIG_IR_JVC_DECODER=y +CONFIG_IR_SONY_DECODER=y +CONFIG_IR_SANYO_DECODER=y +CONFIG_IR_SHARP_DECODER=y +CONFIG_IR_MCE_KBD_DECODER=y +CONFIG_IR_XMP_DECODER=y +# CONFIG_IR_IMON_DECODER is not set +# CONFIG_IR_RCMM_DECODER is not set +# CONFIG_RC_DEVICES is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +CONFIG_AGP=y +CONFIG_AGP_AMD64=y +CONFIG_AGP_INTEL=y +# CONFIG_AGP_SIS is not set +# CONFIG_AGP_VIA is not set +CONFIG_INTEL_GTT=y +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_VGA_SWITCHEROO is not set +CONFIG_DRM=y +# CONFIG_DRM_DP_AUX_CHARDEV is not set +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DEBUG_SELFTEST is not set +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_KMS_FB_HELPER=y +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +# CONFIG_DRM_DP_CEC is not set +CONFIG_DRM_TTM=m +CONFIG_DRM_VRAM_HELPER=m +CONFIG_DRM_SCHED=m + +# +# I2C encoder or helper chips +# +# CONFIG_DRM_I2C_CH7006 is not set +# CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I2C_NXP_TDA998X is not set +# CONFIG_DRM_I2C_NXP_TDA9950 is not set +# end of I2C encoder or helper chips + +# +# ARM devices +# +# end of ARM devices + +# CONFIG_DRM_RADEON is not set +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_USERPTR=y +# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set + +# +# ACP (Audio CoProcessor) Configuration +# +# CONFIG_DRM_AMD_ACP is not set +# end of ACP (Audio CoProcessor) Configuration + +# +# Display Engine Configuration +# +CONFIG_DRM_AMD_DC=y +CONFIG_DRM_AMD_DC_DCN1_0=y +CONFIG_DRM_AMD_DC_DCN2_0=y +# CONFIG_DRM_AMD_DC_DCN2_1 is not set +CONFIG_DRM_AMD_DC_DSC_SUPPORT=y +# CONFIG_DRM_AMD_DC_HDCP is not set +# CONFIG_DEBUG_KERNEL_DC is not set +# end of Display Engine Configuration + +CONFIG_HSA_AMD=y +# CONFIG_DRM_NOUVEAU is not set +# CONFIG_DRM_I915 is not set +# CONFIG_DRM_VGEM is not set +# CONFIG_DRM_VKMS is not set +# CONFIG_DRM_VMWGFX is not set +# CONFIG_DRM_GMA500 is not set +# CONFIG_DRM_UDL is not set +CONFIG_DRM_AST=m +# CONFIG_DRM_MGAG200 is not set +# CONFIG_DRM_CIRRUS_QEMU is not set +# CONFIG_DRM_QXL is not set +# CONFIG_DRM_BOCHS is not set +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +# end of Display Panels + +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PANEL_BRIDGE=y + +# +# Display Interface Bridges +# +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +# end of Display Interface Bridges + +# CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_VBOXVIDEO is not set +# CONFIG_DRM_LEGACY is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y + +# +# Frame buffer Devices +# +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ARC is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_VESA is not set +# CONFIG_FB_EFI is not set +# CONFIG_FB_N411 is not set +# CONFIG_FB_HGA is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_LE80578 is not set +# CONFIG_FB_INTEL is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SM712 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_APPLE is not set +# CONFIG_BACKLIGHT_PM8941_WLED is not set +# CONFIG_BACKLIGHT_SAHARA is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +# end of Backlight & LCD device support + +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_VGACON_SOFT_SCROLLBACK=y +CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 +# CONFIG_VGACON_SOFT_SCROLLBACK_PERSISTENT_ENABLE_BY_DEFAULT is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +# end of Console display driver support + +# CONFIG_LOGO is not set +# end of Graphics support + +# CONFIG_SOUND is not set + +# +# HID support +# +CONFIG_HID=y +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=y +# CONFIG_HID_ACCUTOUCH is not set +# CONFIG_HID_ACRUX is not set +CONFIG_HID_APPLE=y +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_ASUS is not set +# CONFIG_HID_AUREAL is not set +CONFIG_HID_BELKIN=y +# CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_BIGBEN_FF is not set +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +# CONFIG_HID_CORSAIR is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_MACALLY is not set +# CONFIG_HID_CMEDIA is not set +CONFIG_HID_CYPRESS=y +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELAN is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +CONFIG_HID_EZKEY=y +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_GT683R is not set +# CONFIG_HID_KEYTOUCH is not set +CONFIG_HID_KYE=y +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_JABRA is not set +# CONFIG_HID_TWINHAN is not set +CONFIG_HID_KENSINGTON=y +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LED is not set +# CONFIG_HID_LENOVO is not set +CONFIG_HID_LOGITECH=y +# CONFIG_HID_LOGITECH_DJ is not set +# CONFIG_HID_LOGITECH_HIDPP is not set +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +# CONFIG_LOGIG940_FF is not set +# CONFIG_LOGIWHEELS_FF is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_REDRAGON is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTI is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +CONFIG_HID_PLANTRONICS=y +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_RETRODE is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEAM is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_ALPS is not set +# end of Special HID drivers + +# +# USB HID support +# +CONFIG_USB_HID=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y +# end of USB HID support + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +# end of I2C HID support + +# +# Intel ISH HID support +# +# CONFIG_INTEL_ISH_HID is not set +# end of Intel ISH HID support +# end of HID support + +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_PCI=y +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PLATFORM is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=y +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD_PLATFORM=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PCI=y +# CONFIG_USB_OHCI_HCD_PLATFORM is not set +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_UAS is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_USS720 is not set +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_ISP1301 is not set +# end of USB Physical Layer drivers + +# CONFIG_USB_GADGET is not set +# CONFIG_TYPEC is not set +# CONFIG_USB_ROLE_SWITCH is not set +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +# CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set + +# +# LED drivers +# +# CONFIG_LEDS_APU is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3532 is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_LP5562 is not set +# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_CLEVO_MAIL is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_INTEL_SS4200 is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_LM355x is not set + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +# CONFIG_LEDS_BLINKM is not set +# CONFIG_LEDS_MLXCPLD is not set +# CONFIG_LEDS_MLXREG is not set +# CONFIG_LEDS_USER is not set +# CONFIG_LEDS_NIC78BX is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_ONESHOT is not set +# CONFIG_LEDS_TRIGGER_DISK is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_CPU is not set +# CONFIG_LEDS_TRIGGER_ACTIVITY is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set +# CONFIG_LEDS_TRIGGER_CAMERA is not set +# CONFIG_LEDS_TRIGGER_PANIC is not set +# CONFIG_LEDS_TRIGGER_NETDEV is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +# CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_MC146818_LIB=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_HCTOSYS is not set +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABEOZ9 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF85363 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BD70528 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_SD3078 is not set + +# +# SPI RTC drivers +# +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# Platform RTC drivers +# +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_FTRTC010 is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ACPI=y +# CONFIG_ALTERA_MSGDMA is not set +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_INTEL_IOATDMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set +CONFIG_DW_DMAC_CORE=y +# CONFIG_DW_DMAC is not set +CONFIG_DW_DMAC_PCI=y +# CONFIG_DW_EDMA is not set +# CONFIG_DW_EDMA_PCIE is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +CONFIG_SYNC_FILE=y +# CONFIG_SW_SYNC is not set +# CONFIG_UDMABUF is not set +# CONFIG_DMABUF_SELFTESTS is not set +# end of DMABUF options + +# CONFIG_AUXDISPLAY is not set +# CONFIG_PANEL is not set +# CONFIG_UIO is not set +# CONFIG_VFIO is not set +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRTIO_MENU=y +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_HYPERV is not set +# end of Microsoft Hyper-V guest support + +# CONFIG_STAGING is not set +# CONFIG_X86_PLATFORM_DEVICES is not set +CONFIG_PMC_ATOM=y +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_MELLANOX_PLATFORM is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# end of Common Clock Framework + +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_CLKEVT_I8253=y +CONFIG_I8253_LOCK=y +CONFIG_CLKBLD_I8253=y +# end of Clock Source drivers + +CONFIG_MAILBOX=y +CONFIG_PCC=y +# CONFIG_ALTERA_MBOX is not set +CONFIG_IOMMU_IOVA=y +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_AMD_IOMMU=y +CONFIG_AMD_IOMMU_V2=m +# CONFIG_INTEL_IOMMU is not set +# CONFIG_IRQ_REMAP is not set + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_VIRTIO is not set +# end of Rpmsg drivers + +# CONFIG_SOUNDWIRE is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Aspeed SoC drivers +# +# end of Aspeed SoC drivers + +# +# Broadcom SoC drivers +# +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# end of NXP/Freescale QorIQ SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# IXP4xx SoC drivers +# +# CONFIG_IXP4XX_QMGR is not set +# CONFIG_IXP4XX_NPE is not set +# end of IXP4xx SoC drivers + +# +# Qualcomm SoC drivers +# +# end of Qualcomm SoC drivers + +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# CONFIG_XILINX_VCU is not set +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_NTB is not set +# CONFIG_VME_BUS is not set +# CONFIG_PWM is not set + +# +# IRQ chip support +# +# end of IRQ chip support + +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# end of PHY Subsystem + +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# end of Performance monitor support + +CONFIG_RAS=y +# CONFIG_RAS_CEC is not set +# CONFIG_THUNDERBOLT is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# end of Android + +# CONFIG_LIBNVDIMM is not set +CONFIG_DAX=y +# CONFIG_DEV_DAX is not set +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +# CONFIG_FPGA is not set +# CONFIG_UNISYS_VISORBUS is not set +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set +# CONFIG_COUNTER is not set +# end of Device Drivers + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_FS_IOMAP=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +# CONFIG_XFS_ONLINE_SCRUB is not set +CONFIG_XFS_WARN=y +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_DAX is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +CONFIG_QUOTACTL_COMPAT=y +CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=y +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVERLAY_FS_METACOPY is not set + +# +# Caches +# +CONFIG_FSCACHE=y +# CONFIG_FSCACHE_STATS is not set +# CONFIG_FSCACHE_HISTOGRAM is not set +# CONFIG_FSCACHE_DEBUG is not set +# CONFIG_FSCACHE_OBJECT_LIST is not set +# CONFIG_CACHEFILES is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +# CONFIG_UDF_FS is not set +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y +# end of DOS/FAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_VMCORE=y +# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_CHILDREN=y +CONFIG_PROC_PID_ARCH_STATUS=y +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_CONFIGFS_FS=y +# CONFIG_EFIVAR_FS is not set +# end of Pseudo filesystems + +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_PSTORE=y +CONFIG_PSTORE_DEFLATE_COMPRESS=y +# CONFIG_PSTORE_LZO_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +# CONFIG_PSTORE_LZ4HC_COMPRESS is not set +# CONFIG_PSTORE_842_COMPRESS is not set +# CONFIG_PSTORE_ZSTD_COMPRESS is not set +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_PMSG is not set +# CONFIG_PSTORE_FTRACE is not set +# CONFIG_PSTORE_RAM is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_SWAP is not set +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFS_FSCACHE is not set +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=y +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_UPCALL is not set +# CONFIG_CIFS_XATTR is not set +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +# CONFIG_CIFS_DFS_UPCALL is not set +CONFIG_CIFS_FSCACHE=y +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set +# CONFIG_UNICODE is not set +# end of File systems + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_COMPAT=y +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY=y +CONFIG_SECURITY_WRITABLE_HOOKS=y +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_NETWORK=y +CONFIG_PAGE_TABLE_ISOLATION=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +# CONFIG_SECURITY_PATH is not set +CONFIG_LSM_MMAP_MIN_ADDR=65536 +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +# CONFIG_HARDENED_USERCOPY is not set +# CONFIG_FORTIFY_SOURCE is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +# CONFIG_SECURITY_APPARMOR is not set +# CONFIG_SECURITY_LOADPIN is not set +# CONFIG_SECURITY_YAMA is not set +# CONFIG_SECURITY_SAFESETID is not set +CONFIG_INTEGRITY=y +# CONFIG_INTEGRITY_SIGNATURE is not set +CONFIG_INTEGRITY_AUDIT=y +# CONFIG_IMA is not set +# CONFIG_EVM is not set +CONFIG_DEFAULT_SECURITY_SELINUX=y +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# end of Memory initialization +# end of Kernel hardening options +# end of Security options + +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=y +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +# CONFIG_CRYPTO_ECRDSA is not set + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_AEGIS128 is not set +# CONFIG_CRYPTO_AEGIS128L is not set +# CONFIG_CRYPTO_AEGIS256 is not set +# CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set +# CONFIG_CRYPTO_AEGIS128L_AESNI_SSE2 is not set +# CONFIG_CRYPTO_AEGIS256_AESNI_SSE2 is not set +# CONFIG_CRYPTO_MORUS640 is not set +# CONFIG_CRYPTO_MORUS640_SSE2 is not set +# CONFIG_CRYPTO_MORUS1280 is not set +# CONFIG_CRYPTO_MORUS1280_SSE2 is not set +# CONFIG_CRYPTO_MORUS1280_AVX2 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CFB is not set +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set +# CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set +# CONFIG_CRYPTO_ADIANTUM is not set + +# +# Hash modes +# +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32C_INTEL is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRC32_PCLMUL is not set +# CONFIG_CRYPTO_XXHASH is not set +CONFIG_CRYPTO_CRCT10DIF=y +# CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set +CONFIG_CRYPTO_GHASH=y +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_POLY1305_X86_64 is not set +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA1_SSSE3 is not set +# CONFIG_CRYPTO_SHA256_SSSE3 is not set +# CONFIG_CRYPTO_SHA512_SSSE3 is not set +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +# CONFIG_CRYPTO_AES_X86_64 is not set +# CONFIG_CRYPTO_AES_NI_INTEL is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_BLOWFISH_X86_64 is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAMELLIA_X86_64 is not set +# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set +# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_CHACHA20_X86_64 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set +# CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set +# CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set +# CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_TWOFISH_X86_64 is not set +# CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set +# CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_PADLOCK is not set +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_CCP is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C62X is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set +# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set +# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set + +# +# Certificates for signature checking +# +CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# end of Certificates for signature checking + +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +# CONFIG_PACKING is not set +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_FIND_FIRST_BIT=y +# CONFIG_CORDIC is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IOMAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set +# CONFIG_CRC4 is not set +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +# CONFIG_CRC8 is not set +CONFIG_XXHASH=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_INTERVAL_TREE=y +CONFIG_XARRAY_MULTI=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_SWIOTLB=y +# CONFIG_DMA_CMA is not set +# CONFIG_DMA_API_DEBUG is not set +CONFIG_SGL_ALLOC=y +CONFIG_IOMMU_HELPER=y +CONFIG_CHECK_SIGNATURE=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_CLZ_TAB=y +# CONFIG_IRQ_POLL is not set +CONFIG_MPILIB=y +CONFIG_DIMLIB=y +CONFIG_OID_REGISTRY=y +CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_FONT_SUPPORT=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_SG_POOL=y +CONFIG_ARCH_HAS_PMEM_API=y +CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y +CONFIG_ARCH_HAS_UACCESS_MCSAFE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_SBITMAP=y +# CONFIG_STRING_SELFTEST is not set +# end of Library routines + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_DYNAMIC_DEBUG=y +# end of printk and dmesg options + +# +# Compile-time checks and compiler options +# +# CONFIG_DEBUG_INFO is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_INSTALL is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_STACK_VALIDATION=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# end of Compile-time checks and compiler options + +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_PAGE_REF is not set +CONFIG_DEBUG_RODATA_TEST=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=400 +# CONFIG_DEBUG_KMEMLEAK_TEST is not set +CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y +CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_VM is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_CC_HAS_KASAN_GENERIC=y +# CONFIG_KASAN is not set +CONFIG_KASAN_STACK=1 +# end of Memory Debugging + +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +CONFIG_DEBUG_SHIRQ=y + +# +# Debug Lockups and Hangs +# +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_HARDLOCKUP_DETECTOR_PERF=y +CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y +CONFIG_HARDLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_WQ_WATCHDOG is not set +# end of Debug Lockups and Hangs + +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_SCHED_DEBUG=y +CONFIG_SCHED_INFO=y +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_STACK_END_CHECK=y +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_PROVE_LOCKING=y +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y +CONFIG_DEBUG_RWSEMS=y +CONFIG_DEBUG_LOCK_ALLOC=y +CONFIG_LOCKDEP=y +# CONFIG_DEBUG_LOCKDEP is not set +CONFIG_DEBUG_ATOMIC_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +CONFIG_TRACE_IRQFLAGS=y +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +CONFIG_PROVE_RCU=y +# CONFIG_RCU_PERF_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_FENTRY=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_TRACE_CLOCK=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_PREEMPTIRQ_TRACEPOINTS=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_GRAPH_TRACER=y +# CONFIG_PREEMPTIRQ_EVENTS is not set +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_SCHED_TRACER=y +CONFIG_HWLAT_TRACER=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_TRACER_SNAPSHOT=y +# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +CONFIG_STACK_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_KPROBE_EVENTS=y +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +CONFIG_UPROBE_EVENTS=y +CONFIG_BPF_EVENTS=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_PROBE_EVENTS=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_FUNCTION_PROFILER=y +# CONFIG_BPF_KPROBE_OVERRIDE is not set +CONFIG_FTRACE_MCOUNT_RECORD=y +# CONFIG_FTRACE_STARTUP_TEST is not set +CONFIG_MMIOTRACE=y +CONFIG_TRACING_MAP=y +CONFIG_HIST_TRIGGERS=y +# CONFIG_MMIOTRACE_TEST is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_MEMTEST=y +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_KGDB=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +CONFIG_KGDB_LOW_LEVEL_TRAP=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_DEFAULT_ENABLE=0x1 +CONFIG_KDB_KEYBOARD=y +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_UBSAN_ALIGNMENT=y +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_X86_VERBOSE_BOOTUP is not set +CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK_DBGP is not set +# CONFIG_EARLY_PRINTK_USB_XDBC is not set +# CONFIG_X86_PTDUMP is not set +# CONFIG_EFI_PGT_DUMP is not set +# CONFIG_DEBUG_WX is not set +CONFIG_DOUBLEFAULT=y +# CONFIG_DEBUG_TLBFLUSH is not set +# CONFIG_IOMMU_DEBUG is not set +CONFIG_HAVE_MMIOTRACE_SUPPORT=y +# CONFIG_X86_DECODER_SELFTEST is not set +# CONFIG_IO_DELAY_0X80 is not set +CONFIG_IO_DELAY_0XED=y +# CONFIG_IO_DELAY_UDELAY is not set +# CONFIG_IO_DELAY_NONE is not set +# CONFIG_DEBUG_BOOT_PARAMS is not set +# CONFIG_CPA_DEBUG is not set +# CONFIG_DEBUG_ENTRY is not set +# CONFIG_DEBUG_NMI_SELFTEST is not set +CONFIG_X86_DEBUG_FPU=y +# CONFIG_PUNIT_ATOM_DEBUG is not set +CONFIG_UNWINDER_ORC=y +# CONFIG_UNWINDER_FRAME_POINTER is not set +# CONFIG_UNWINDER_GUESS is not set +# end of Kernel hacking From 086031787b19a9ad3b5de4cb6c23b0c78e443cad Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 30 Mar 2021 18:43:07 -0400 Subject: [PATCH 0010/2653] rock-dbg_defconfig: update to 5.11 and enable DEVICE_PRIVATE Update rock-dbg_defconfig for the 5.11 kernel. Enable CONFIG_DEVICE_PRIVATE, which is needed by the new HMM-based SVM memory manager. Signed-off-by: Felix Kuehling Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 711 +++++++++++++++++----------- 1 file changed, 443 insertions(+), 268 deletions(-) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index 5e1de51be9553..55fa96bf27502 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -1,19 +1,19 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/x86 5.3.0-rc3 Kernel Configuration -# - -# -# Compiler: gcc (Ubuntu 7.4.0-1ubuntu1~18.04.1) 7.4.0 +# Linux/x86 5.11.0 Kernel Configuration # +CONFIG_CC_VERSION_TEXT="gcc (Ubuntu 7.5.0-3ubuntu1~18.04) 7.5.0" CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=70400 +CONFIG_GCC_VERSION=70500 +CONFIG_LD_VERSION=230000000 CONFIG_CLANG_VERSION=0 +CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO=y -CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y +CONFIG_CC_HAS_ASM_INLINE=y CONFIG_IRQ_WORK=y -CONFIG_BUILDTIME_EXTABLE_SORT=y +CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y # @@ -21,7 +21,6 @@ CONFIG_THREAD_INFO_IN_TASK=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set -# CONFIG_HEADER_TEST is not set CONFIG_LOCALVERSION="-kfd" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_BUILD_SALT="" @@ -31,18 +30,22 @@ CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_XZ=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_ZSTD=y CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_BZIP2 is not set # CONFIG_KERNEL_LZMA is not set # CONFIG_KERNEL_XZ is not set # CONFIG_KERNEL_LZO is not set # CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_ZSTD is not set +CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_WATCH_QUEUE is not set CONFIG_CROSS_MEMORY_ATTACH=y CONFIG_USELIB=y CONFIG_AUDIT=y @@ -57,10 +60,12 @@ CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_PENDING_IRQ=y CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_HARDIRQS_SW_RESEND=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_IRQ_MSI_IOMMU=y CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y CONFIG_GENERIC_IRQ_RESERVATION_MODE=y CONFIG_IRQ_FORCED_THREADING=y @@ -69,7 +74,6 @@ CONFIG_SPARSE_IRQ=y # end of IRQ subsystem CONFIG_CLOCKSOURCE_WATCHDOG=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y CONFIG_ARCH_CLOCKSOURCE_INIT=y CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y CONFIG_GENERIC_TIME_VSYSCALL=y @@ -77,6 +81,8 @@ CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y # # Timers subsystem @@ -119,6 +125,9 @@ CONFIG_TREE_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RUDE_RCU=y +CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y # end of RCU Subsystem @@ -134,10 +143,12 @@ CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y # # Scheduler features # +# CONFIG_UCLAMP_TASK is not set # end of Scheduler features CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y +CONFIG_CC_HAS_INT128=y CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_NUMA_BALANCING=y CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y @@ -145,7 +156,6 @@ CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y CONFIG_MEMCG=y CONFIG_MEMCG_SWAP=y -# CONFIG_MEMCG_SWAP_ENABLED is not set CONFIG_MEMCG_KMEM=y CONFIG_BLK_CGROUP=y CONFIG_CGROUP_WRITEBACK=y @@ -167,6 +177,7 @@ CONFIG_CGROUP_BPF=y CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y CONFIG_UTS_NS=y +CONFIG_TIME_NS=y CONFIG_IPC_NS=y CONFIG_USER_NS=y CONFIG_PID_NS=y @@ -183,8 +194,11 @@ CONFIG_RD_LZMA=y CONFIG_RD_XZ=y CONFIG_RD_LZO=y CONFIG_RD_LZ4=y +CONFIG_RD_ZSTD=y +# CONFIG_BOOT_CONFIG is not set CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y @@ -195,7 +209,6 @@ CONFIG_UID16=y CONFIG_MULTIUSER=y CONFIG_SGETMASK_SYSCALL=y CONFIG_SYSFS_SYSCALL=y -CONFIG_SYSCTL_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y @@ -220,8 +233,11 @@ CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_BPF_SYSCALL=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y +# CONFIG_BPF_PRELOAD is not set # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_KCMP=y CONFIG_RSEQ=y # CONFIG_DEBUG_RSEQ is not set # CONFIG_EMBEDDED is not set @@ -257,7 +273,6 @@ CONFIG_X86_64=y CONFIG_X86=y CONFIG_INSTRUCTION_DECODER=y CONFIG_OUTPUT_FORMAT="elf64-x86-64" -CONFIG_ARCH_DEFCONFIG="arch/x86/configs/x86_64_defconfig" CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_MMU=y @@ -281,7 +296,6 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_ZONE_DMA32=y CONFIG_AUDIT_ARCH=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_X86_64_SMP=y CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_FIX_EARLYCON_MEM=y @@ -312,10 +326,11 @@ CONFIG_HYPERVISOR_GUEST=y CONFIG_PARAVIRT=y # CONFIG_PARAVIRT_DEBUG is not set CONFIG_PARAVIRT_SPINLOCKS=y +CONFIG_X86_HV_CALLBACK_VECTOR=y # CONFIG_XEN is not set CONFIG_KVM_GUEST=y +CONFIG_ARCH_CPUIDLE_HALTPOLL=y # CONFIG_PVH is not set -CONFIG_KVM_DEBUG_FS=y # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set CONFIG_PARAVIRT_CLOCK=y # CONFIG_JAILHOUSE_GUEST is not set @@ -332,6 +347,8 @@ CONFIG_X86_CMPXCHG64=y CONFIG_X86_CMOV=y CONFIG_X86_MINIMUM_CPU_FAMILY=64 CONFIG_X86_DEBUGCTLMSR=y +CONFIG_IA32_FEAT_CTL=y +CONFIG_X86_VMX_FEATURE_NAMES=y CONFIG_PROCESSOR_SELECT=y CONFIG_CPU_SUP_INTEL=y CONFIG_CPU_SUP_AMD=y @@ -342,8 +359,6 @@ CONFIG_HPET_TIMER=y CONFIG_HPET_EMULATE_RTC=y CONFIG_DMI=y CONFIG_GART_IOMMU=y -CONFIG_CALGARY_IOMMU=y -CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y # CONFIG_MAXSMP is not set CONFIG_NR_CPUS_RANGE_BEGIN=2 CONFIG_NR_CPUS_RANGE_END=512 @@ -375,6 +390,7 @@ CONFIG_PERF_EVENTS_INTEL_CSTATE=y CONFIG_X86_16BIT=y CONFIG_X86_ESPFIX64=y CONFIG_X86_VSYSCALL_EMULATION=y +CONFIG_X86_IOPL_IOPERM=y CONFIG_I8K=m CONFIG_MICROCODE=y CONFIG_MICROCODE_INTEL=y @@ -385,12 +401,10 @@ CONFIG_X86_CPUID=m # CONFIG_X86_5LEVEL is not set CONFIG_X86_DIRECT_GBPAGES=y # CONFIG_X86_CPA_STATISTICS is not set -CONFIG_ARCH_HAS_MEM_ENCRYPT=y # CONFIG_AMD_MEM_ENCRYPT is not set CONFIG_NUMA=y CONFIG_AMD_NUMA=y CONFIG_X86_64_ACPI_NUMA=y -CONFIG_NODES_SPAN_OTHER_NODES=y # CONFIG_NUMA_EMU is not set CONFIG_NODES_SHIFT=6 CONFIG_ARCH_SPARSEMEM_ENABLE=y @@ -411,13 +425,15 @@ CONFIG_X86_PAT=y CONFIG_ARCH_USES_PG_UNCACHED=y CONFIG_ARCH_RANDOM=y CONFIG_X86_SMAP=y -CONFIG_X86_INTEL_UMIP=y -# CONFIG_X86_INTEL_MPX is not set +CONFIG_X86_UMIP=y CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y +CONFIG_X86_INTEL_TSX_MODE_OFF=y +# CONFIG_X86_INTEL_TSX_MODE_ON is not set +# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set +# CONFIG_X86_SGX is not set CONFIG_EFI=y CONFIG_EFI_STUB=y CONFIG_EFI_MIXED=y -CONFIG_SECCOMP=y # CONFIG_HZ_100 is not set CONFIG_HZ_250=y # CONFIG_HZ_300 is not set @@ -427,7 +443,7 @@ CONFIG_SCHED_HRTICK=y CONFIG_KEXEC=y CONFIG_KEXEC_FILE=y CONFIG_ARCH_HAS_KEXEC_PURGATORY=y -CONFIG_KEXEC_VERIFY_SIG=y +# CONFIG_KEXEC_SIG is not set CONFIG_CRASH_DUMP=y CONFIG_KEXEC_JUMP=y CONFIG_PHYSICAL_START=0x1000000 @@ -468,6 +484,7 @@ CONFIG_SUSPEND_FREEZER=y # CONFIG_SUSPEND_SKIP_SYNC is not set CONFIG_HIBERNATE_CALLBACKS=y CONFIG_HIBERNATION=y +CONFIG_HIBERNATION_SNAPSHOT_DEV=y CONFIG_PM_STD_PARTITION="" CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y @@ -495,7 +512,6 @@ CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y CONFIG_ACPI_SPCR_TABLE=y CONFIG_ACPI_LPIT=y CONFIG_ACPI_SLEEP=y -# CONFIG_ACPI_PROCFS_POWER is not set CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y CONFIG_ACPI_EC_DEBUGFS=m CONFIG_ACPI_AC=y @@ -513,7 +529,6 @@ CONFIG_ACPI_PROCESSOR=y CONFIG_ACPI_HOTPLUG_CPU=y CONFIG_ACPI_PROCESSOR_AGGREGATOR=m CONFIG_ACPI_THERMAL=y -CONFIG_ACPI_NUMA=y CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y CONFIG_ACPI_TABLE_UPGRADE=y # CONFIG_ACPI_DEBUG is not set @@ -536,9 +551,9 @@ CONFIG_ACPI_APEI_PCIEAER=y CONFIG_ACPI_APEI_MEMORY_FAILURE=y CONFIG_ACPI_APEI_EINJ=m # CONFIG_ACPI_APEI_ERST_DEBUG is not set -# CONFIG_DPTF_POWER is not set -# CONFIG_PMIC_OPREGION is not set +# CONFIG_ACPI_DPTF is not set # CONFIG_ACPI_CONFIGFS is not set +# CONFIG_PMIC_OPREGION is not set CONFIG_X86_PM_TIMER=y CONFIG_SFI=y @@ -552,15 +567,13 @@ CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set CONFIG_CPU_FREQ_GOV_PERFORMANCE=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y # # CPU frequency scaling drivers @@ -586,6 +599,8 @@ CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y # CONFIG_CPU_IDLE_GOV_TEO is not set +# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set +CONFIG_HALTPOLL_CPUIDLE=y # end of CPU Idle # CONFIG_INTEL_IDLE is not set @@ -636,16 +651,20 @@ CONFIG_EFI_VARS_PSTORE=y CONFIG_EFI_RUNTIME_MAP=y # CONFIG_EFI_FAKE_MEMMAP is not set CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y # CONFIG_EFI_BOOTLOADER_CONTROL is not set # CONFIG_EFI_CAPSULE_LOADER is not set # CONFIG_EFI_TEST is not set # CONFIG_APPLE_PROPERTIES is not set # CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_RCI2_TABLE is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set # end of EFI (Extensible Firmware Interface) Support CONFIG_UEFI_CPER=y CONFIG_UEFI_CPER_X86=y CONFIG_EFI_EARLYCON=y +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y # # Tegra firmware driver @@ -656,8 +675,9 @@ CONFIG_EFI_EARLYCON=y CONFIG_HAVE_KVM=y CONFIG_VIRTUALIZATION=y # CONFIG_KVM is not set -# CONFIG_VHOST_NET is not set -# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set +CONFIG_AS_AVX512=y +CONFIG_AS_SHA1_NI=y +CONFIG_AS_SHA256_NI=y # # General architecture-dependent options @@ -665,6 +685,7 @@ CONFIG_VIRTUALIZATION=y CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y CONFIG_HOTPLUG_SMT=y +CONFIG_GENERIC_ENTRY=y CONFIG_OPROFILE=m # CONFIG_OPROFILE_EVENT_MULTIPLEX is not set CONFIG_HAVE_OPROFILE=y @@ -672,6 +693,7 @@ CONFIG_OPROFILE_NMI_TIMER=y CONFIG_KPROBES=y CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_STATIC_CALL_SELFTEST is not set CONFIG_OPTPROBES=y CONFIG_KPROBES_ON_FTRACE=y CONFIG_UPROBES=y @@ -693,10 +715,10 @@ CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_ARCH_HAS_SET_DIRECT_MAP=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y +CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y -CONFIG_HAVE_CLK=y CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y CONFIG_HAVE_USER_RETURN_NOTIFIER=y @@ -706,24 +728,29 @@ CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y -CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y CONFIG_HAVE_CMPXCHG_LOCAL=y CONFIG_HAVE_CMPXCHG_DOUBLE=y CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y +CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y -CONFIG_CC_HAS_STACKPROTECTOR_NONE=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_CONTEXT_TRACKING_OFFSTACK=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y CONFIG_HAVE_MOVE_PMD=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y @@ -732,7 +759,6 @@ CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_HAVE_ARCH_SOFT_DIRTY=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y @@ -740,12 +766,10 @@ CONFIG_ARCH_MMAP_RND_BITS=28 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y -CONFIG_HAVE_COPY_THREAD_TLS=y CONFIG_HAVE_STACK_VALIDATION=y CONFIG_HAVE_RELIABLE_STACKTRACE=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_COMPAT_OLD_SIGACTION=y -CONFIG_64BIT_TIME=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y @@ -753,11 +777,14 @@ CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_REFCOUNT=y -# CONFIG_REFCOUNT_FULL is not set CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y CONFIG_ARCH_USE_MEMREMAP_PROT=y # CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_ARCH_HAS_MEM_ENCRYPT=y +CONFIG_HAVE_STATIC_CALL=y +CONFIG_HAVE_STATIC_CALL_INLINE=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y # # GCOV-based kernel profiling @@ -766,17 +793,18 @@ CONFIG_ARCH_USE_MEMREMAP_PROT=y CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling -CONFIG_PLUGIN_HOSTCC="" CONFIG_HAVE_GCC_PLUGINS=y # end of General architecture-dependent options CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 +CONFIG_MODULE_SIG_FORMAT=y CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y +CONFIG_ASM_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_MODULE_SIG=y # CONFIG_MODULE_SIG_FORCE is not set @@ -788,21 +816,27 @@ CONFIG_MODULE_SIG_ALL=y CONFIG_MODULE_SIG_SHA512=y CONFIG_MODULE_SIG_HASH="sha512" # CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_CGROUP_RWSTAT=y CONFIG_BLK_DEV_BSG=y CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=y # CONFIG_BLK_DEV_ZONED is not set CONFIG_BLK_DEV_THROTTLING=y # CONFIG_BLK_DEV_THROTTLING_LOW is not set CONFIG_BLK_CMDLINE_PARSER=y # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set +# CONFIG_BLK_CGROUP_IOCOST is not set CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set +# CONFIG_BLK_INLINE_ENCRYPTION is not set # # Partition Types @@ -851,6 +885,7 @@ CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y CONFIG_QUEUED_SPINLOCKS=y CONFIG_ARCH_USE_QUEUED_RWLOCKS=y CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y CONFIG_FREEZER=y @@ -874,12 +909,11 @@ CONFIG_SELECT_MEMORY_MODEL=y CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_NEED_MULTIPLE_NODES=y -CONFIG_HAVE_MEMORY_PRESENT=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_HAVE_MEMBLOCK_NODE_MAP=y CONFIG_HAVE_FAST_GUP=y +CONFIG_NUMA_KEEP_MEMINFO=y CONFIG_MEMORY_ISOLATION=y CONFIG_HAVE_BOOTMEM_INFO_NODE=y CONFIG_MEMORY_HOTPLUG=y @@ -888,6 +922,7 @@ CONFIG_MEMORY_HOTPLUG_SPARSE=y CONFIG_MEMORY_HOTREMOVE=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_COMPACTION=y +# CONFIG_PAGE_REPORTING is not set CONFIG_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y @@ -904,7 +939,6 @@ CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set CONFIG_ARCH_WANTS_THP_SWAP=y CONFIG_THP_SWAP=y -CONFIG_TRANSPARENT_HUGE_PAGECACHE=y CONFIG_CLEANCACHE=y CONFIG_FRONTSWAP=y CONFIG_CMA=y @@ -913,23 +947,36 @@ CONFIG_CMA=y CONFIG_CMA_AREAS=7 CONFIG_MEM_SOFT_DIRTY=y CONFIG_ZSWAP=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo" +CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y +# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set +# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set +CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud" +# CONFIG_ZSWAP_DEFAULT_ON is not set CONFIG_ZPOOL=y CONFIG_ZBUD=y # CONFIG_Z3FOLD is not set CONFIG_ZSMALLOC=y -CONFIG_PGTABLE_MAPPING=y # CONFIG_ZSMALLOC_STAT is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ZONE_DEVICE=y +CONFIG_DEV_PAGEMAP_OPS=y CONFIG_HMM_MIRROR=y -# CONFIG_DEVICE_PRIVATE is not set +CONFIG_DEVICE_PRIVATE=y CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y CONFIG_ARCH_HAS_PKEYS=y # CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_BENCHMARK is not set +# CONFIG_GUP_TEST is not set +# CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y # end of Memory Management options @@ -949,10 +996,13 @@ CONFIG_UNIX_DIAG=y CONFIG_XFRM=y CONFIG_XFRM_ALGO=y CONFIG_XFRM_USER=y +# CONFIG_XFRM_USER_COMPAT is not set # CONFIG_XFRM_INTERFACE is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set # CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_AH=y +CONFIG_XFRM_ESP=y # CONFIG_NET_KEY is not set # CONFIG_XDP_SOCKETS is not set CONFIG_INET=y @@ -1015,6 +1065,7 @@ CONFIG_IPV6=y CONFIG_INET6_AH=y CONFIG_INET6_ESP=y # CONFIG_INET6_ESP_OFFLOAD is not set +# CONFIG_INET6_ESPINTCP is not set # CONFIG_INET6_IPCOMP is not set # CONFIG_IPV6_MIP6 is not set # CONFIG_IPV6_ILA is not set @@ -1027,7 +1078,9 @@ CONFIG_IPV6_NDISC_NODETYPE=y # CONFIG_IPV6_MROUTE is not set # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_RPL_LWTUNNEL is not set CONFIG_NETLABEL=y +# CONFIG_MPTCP is not set CONFIG_NETWORK_SECMARK=y CONFIG_NET_PTP_CLASSIFY=y # CONFIG_NETWORK_PHY_TIMESTAMPING is not set @@ -1078,7 +1131,6 @@ CONFIG_NF_NAT_REDIRECT=y CONFIG_NF_NAT_MASQUERADE=y CONFIG_NETFILTER_SYNPROXY=m CONFIG_NF_TABLES=m -CONFIG_NF_TABLES_SET=m # CONFIG_NF_TABLES_INET is not set CONFIG_NF_TABLES_NETDEV=y # CONFIG_NFT_NUMGEN is not set @@ -1107,6 +1159,7 @@ CONFIG_NF_DUP_NETDEV=m # CONFIG_NFT_DUP_NETDEV is not set # CONFIG_NFT_FWD_NETDEV is not set # CONFIG_NFT_FIB_NETDEV is not set +# CONFIG_NFT_REJECT_NETDEV is not set # CONFIG_NF_FLOW_TABLE is not set CONFIG_NETFILTER_XTABLES=m @@ -1288,6 +1341,8 @@ CONFIG_STP=y CONFIG_BRIDGE=y CONFIG_BRIDGE_IGMP_SNOOPING=y # CONFIG_BRIDGE_VLAN_FILTERING is not set +# CONFIG_BRIDGE_MRP is not set +# CONFIG_BRIDGE_CFM is not set CONFIG_HAVE_NET_DSA=y # CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=y @@ -1336,6 +1391,7 @@ CONFIG_NET_SCHED=y # CONFIG_NET_SCH_PIE is not set # CONFIG_NET_SCH_INGRESS is not set # CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_ETS is not set # CONFIG_NET_SCH_DEFAULT is not set # @@ -1381,7 +1437,8 @@ CONFIG_NET_CLS_ACT=y # CONFIG_NET_ACT_SKBMOD is not set # CONFIG_NET_ACT_IFE is not set # CONFIG_NET_ACT_TUNNEL_KEY is not set -# CONFIG_NET_ACT_CT is not set +# CONFIG_NET_ACT_GATE is not set +# CONFIG_NET_TC_SKB_EXT is not set CONFIG_NET_SCH_FIFO=y # CONFIG_DCB is not set CONFIG_DNS_RESOLVER=y @@ -1394,6 +1451,7 @@ CONFIG_NETLINK_DIAG=y # CONFIG_HSR is not set # CONFIG_NET_SWITCHDEV is not set # CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set CONFIG_RPS=y CONFIG_RFS_ACCEL=y @@ -1432,7 +1490,6 @@ CONFIG_WIRELESS=y # CFG80211 needs to be enabled for MAC80211 # CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -# CONFIG_WIMAX is not set CONFIG_RFKILL=y CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y @@ -1446,6 +1503,7 @@ CONFIG_RFKILL_INPUT=y CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y # CONFIG_FAILOVER is not set +CONFIG_ETHTOOL_NETLINK=y CONFIG_HAVE_EBPF_JIT=y # @@ -1462,7 +1520,6 @@ CONFIG_PCIEAER=y # CONFIG_PCIEAER_INJECT is not set # CONFIG_PCIE_ECRC is not set CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEBUG=y CONFIG_PCIEASPM_DEFAULT=y # CONFIG_PCIEASPM_POWERSAVE is not set # CONFIG_PCIEASPM_POWER_SUPERSAVE is not set @@ -1485,6 +1542,11 @@ CONFIG_PCI_PRI=y CONFIG_PCI_PASID=y # CONFIG_PCI_P2PDMA is not set CONFIG_PCI_LABEL=y +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set CONFIG_HOTPLUG_PCI=y # CONFIG_HOTPLUG_PCI_ACPI is not set # CONFIG_HOTPLUG_PCI_CPCI is not set @@ -1493,12 +1555,6 @@ CONFIG_HOTPLUG_PCI=y # # PCI controller drivers # - -# -# Cadence PCIe controllers support -# -# end of Cadence PCIe controllers support - # CONFIG_VMD is not set # @@ -1507,6 +1563,16 @@ CONFIG_HOTPLUG_PCI=y # CONFIG_PCIE_DW_PLAT_HOST is not set # CONFIG_PCI_MESON is not set # end of DesignWare PCI Core Support + +# +# Mobiveil PCIe Core Support +# +# end of Mobiveil PCIe Core Support + +# +# Cadence PCIe controllers support +# +# end of Cadence PCIe controllers support # end of PCI controller drivers # @@ -1559,6 +1625,7 @@ CONFIG_FW_LOADER=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_FW_LOADER_USER_HELPER is not set # CONFIG_FW_LOADER_COMPRESS is not set +CONFIG_FW_CACHE=y # end of Firmware loader CONFIG_ALLOW_DEV_COREDUMP=y @@ -1568,8 +1635,6 @@ CONFIG_ALLOW_DEV_COREDUMP=y # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y CONFIG_DMA_SHARED_BUFFER=y # CONFIG_DMA_FENCE_TRACE is not set # end of Generic Driver Options @@ -1577,6 +1642,7 @@ CONFIG_DMA_SHARED_BUFFER=y # # Bus devices # +# CONFIG_MHI_BUS is not set # end of Bus devices # CONFIG_CONNECTOR is not set @@ -1627,6 +1693,7 @@ CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_NVME_CORE=y CONFIG_BLK_DEV_NVME=y # CONFIG_NVME_MULTIPATH is not set +# CONFIG_NVME_HWMON is not set # CONFIG_NVME_FC is not set # CONFIG_NVME_TCP is not set # CONFIG_NVME_TARGET is not set @@ -1639,7 +1706,6 @@ CONFIG_BLK_DEV_NVME=y # CONFIG_DUMMY_IRQ is not set # CONFIG_IBM_ASM is not set # CONFIG_PHANTOM is not set -# CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set @@ -1682,53 +1748,13 @@ CONFIG_BLK_DEV_NVME=y # CONFIG_INTEL_MEI_ME is not set # CONFIG_INTEL_MEI_TXE is not set # CONFIG_VMWARE_VMCI is not set - -# -# Intel MIC & related support -# - -# -# Intel MIC Bus Driver -# -# CONFIG_INTEL_MIC_BUS is not set - -# -# SCIF Bus Driver -# -# CONFIG_SCIF_BUS is not set - -# -# VOP Bus Driver -# -# CONFIG_VOP_BUS is not set - -# -# Intel MIC Host Driver -# - -# -# Intel MIC Card Driver -# - -# -# SCIF Driver -# - -# -# Intel MIC Coprocessor State Management (COSM) Drivers -# - -# -# VOP Driver -# -# end of Intel MIC & related support - # CONFIG_GENWQE is not set # CONFIG_ECHO is not set # CONFIG_MISC_ALCOR_PCI is not set # CONFIG_MISC_RTSX_PCI is not set # CONFIG_MISC_RTSX_USB is not set # CONFIG_HABANA_AI is not set +# CONFIG_UACCE is not set # end of Misc devices CONFIG_HAVE_IDE=y @@ -1749,7 +1775,6 @@ CONFIG_SCSI_PROC_FS=y CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set CONFIG_SCSI_CONSTANTS=y @@ -1772,7 +1797,10 @@ CONFIG_SCSI_ISCSI_ATTRS=y # end of SCSI device support CONFIG_ATA=y +CONFIG_SATA_HOST=y +CONFIG_PATA_TIMINGS=y CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_FORCE=y CONFIG_ATA_ACPI=y # CONFIG_SATA_ZPODD is not set CONFIG_SATA_PMP=y @@ -1884,7 +1912,9 @@ CONFIG_BLK_DEV_DM=y # CONFIG_DM_THIN_PROVISIONING is not set # CONFIG_DM_CACHE is not set # CONFIG_DM_WRITECACHE is not set +# CONFIG_DM_EBS is not set # CONFIG_DM_ERA is not set +# CONFIG_DM_CLONE is not set CONFIG_DM_MIRROR=y # CONFIG_DM_LOG_USERSPACE is not set # CONFIG_DM_RAID is not set @@ -1920,6 +1950,7 @@ CONFIG_MII=y CONFIG_NET_CORE=y # CONFIG_BONDING is not set # CONFIG_DUMMY is not set +# CONFIG_WIREGUARD is not set # CONFIG_EQUALIZER is not set # CONFIG_NET_FC is not set # CONFIG_IFB is not set @@ -1929,6 +1960,7 @@ CONFIG_MACVLAN=y # CONFIG_IPVLAN is not set # CONFIG_VXLAN is not set # CONFIG_GENEVE is not set +# CONFIG_BAREUDP is not set # CONFIG_GTP is not set # CONFIG_MACSEC is not set CONFIG_NETCONSOLE=y @@ -1942,10 +1974,6 @@ CONFIG_VETH=y # CONFIG_NLMON is not set # CONFIG_ARCNET is not set -# -# CAIF transport drivers -# - # # Distributed Switch Architecture drivers # @@ -2029,8 +2057,6 @@ CONFIG_NET_VENDOR_EMULEX=y CONFIG_NET_VENDOR_EZCHIP=y CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_GVE is not set -CONFIG_NET_VENDOR_HP=y -# CONFIG_HP100 is not set CONFIG_NET_VENDOR_HUAWEI=y # CONFIG_HINIC is not set CONFIG_NET_VENDOR_I825XX=y @@ -2091,10 +2117,11 @@ CONFIG_NET_VENDOR_OKI=y CONFIG_NET_VENDOR_PACKET_ENGINES=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set +CONFIG_NET_VENDOR_PENSANDO=y +# CONFIG_IONIC is not set CONFIG_NET_VENDOR_QLOGIC=y # CONFIG_QLA3XXX is not set # CONFIG_QLCNIC is not set -# CONFIG_QLGE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_QED is not set CONFIG_NET_VENDOR_QUALCOMM=y @@ -2160,37 +2187,29 @@ CONFIG_FDDI=y # CONFIG_SKFP is not set # CONFIG_HIPPI is not set # CONFIG_NET_SB1000 is not set -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_BUS=y -# CONFIG_MDIO_BCM_UNIMAC is not set -# CONFIG_MDIO_BITBANG is not set -# CONFIG_MDIO_MSCC_MIIM is not set -# CONFIG_MDIO_THUNDER is not set CONFIG_PHYLIB=y # CONFIG_LED_TRIGGER_PHY is not set +# CONFIG_FIXED_PHY is not set # # MII PHY device drivers # CONFIG_AMD_PHY=y +# CONFIG_ADIN_PHY is not set # CONFIG_AQUANTIA_PHY is not set # CONFIG_AX88796B_PHY is not set -# CONFIG_AT803X_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM54140_PHY is not set # CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM84881_PHY is not set # CONFIG_BCM87XX_PHY is not set -# CONFIG_BROADCOM_PHY is not set # CONFIG_CICADA_PHY is not set # CONFIG_CORTINA_PHY is not set # CONFIG_DAVICOM_PHY is not set -# CONFIG_DP83822_PHY is not set -# CONFIG_DP83TC811_PHY is not set -# CONFIG_DP83848_PHY is not set -# CONFIG_DP83867_PHY is not set -# CONFIG_FIXED_PHY is not set # CONFIG_ICPLUS_PHY is not set +# CONFIG_LXT_PHY is not set # CONFIG_INTEL_XWAY_PHY is not set # CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_LXT_PHY is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set # CONFIG_MICREL_PHY is not set @@ -2206,8 +2225,32 @@ CONFIG_REALTEK_PHY=y # CONFIG_SMSC_PHY is not set # CONFIG_STE10XP is not set # CONFIG_TERANETICS_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_DP83869_PHY is not set # CONFIG_VITESSE_PHY is not set # CONFIG_XILINX_GMII2RGMII is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_MVUSB is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_THUNDER is not set + +# +# MDIO Multiplexers +# + +# +# PCS device drivers +# +# CONFIG_PCS_XPCS is not set +# end of PCS device drivers + # CONFIG_PLIP is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -2255,8 +2298,8 @@ CONFIG_USB_BELKIN=y # CONFIG_USB_VL600 is not set # CONFIG_USB_NET_CH9200 is not set # CONFIG_USB_NET_AQC111 is not set +# CONFIG_USB_RTL8153_ECM is not set CONFIG_WLAN=y -# CONFIG_WIRELESS_WDS is not set CONFIG_WLAN_VENDOR_ADMTEK=y CONFIG_WLAN_VENDOR_ATH=y # CONFIG_ATH_DEBUG is not set @@ -2270,6 +2313,7 @@ CONFIG_WLAN_VENDOR_INTERSIL=y # CONFIG_PRISM54 is not set CONFIG_WLAN_VENDOR_MARVELL=y CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_MICROCHIP=y CONFIG_WLAN_VENDOR_RALINK=y CONFIG_WLAN_VENDOR_REALTEK=y CONFIG_WLAN_VENDOR_RSI=y @@ -2277,10 +2321,6 @@ CONFIG_WLAN_VENDOR_ST=y CONFIG_WLAN_VENDOR_TI=y CONFIG_WLAN_VENDOR_ZYDAS=y CONFIG_WLAN_VENDOR_QUANTENNA=y - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# # CONFIG_WAN is not set # CONFIG_VMXNET3 is not set # CONFIG_FUJITSU_ES is not set @@ -2295,7 +2335,6 @@ CONFIG_WLAN_VENDOR_QUANTENNA=y CONFIG_INPUT=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_POLLDEV=y CONFIG_INPUT_SPARSEKMAP=y # CONFIG_INPUT_MATRIXKMAP is not set @@ -2398,23 +2437,7 @@ CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_NONSTANDARD=y -# CONFIG_ROCKETPORT is not set -# CONFIG_CYCLADES is not set -# CONFIG_MOXA_INTELLIO is not set -# CONFIG_MOXA_SMARTIO is not set -# CONFIG_SYNCLINK is not set -# CONFIG_SYNCLINKMP is not set -# CONFIG_SYNCLINK_GT is not set -# CONFIG_NOZOMI is not set -# CONFIG_ISI is not set -# CONFIG_N_HDLC is not set -# CONFIG_N_GSM is not set -# CONFIG_TRACE_SINK is not set -# CONFIG_NULL_TTY is not set CONFIG_LDISC_AUTOLOAD=y -CONFIG_DEVMEM=y -# CONFIG_DEVKMEM is not set # # Serial drivers @@ -2423,6 +2446,7 @@ CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y CONFIG_SERIAL_8250_PNP=y +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set # CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DMA=y @@ -2435,11 +2459,11 @@ CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_8250_DWLIB=y # CONFIG_SERIAL_8250_DW is not set # CONFIG_SERIAL_8250_RT288X is not set CONFIG_SERIAL_8250_LPSS=y # CONFIG_SERIAL_8250_MID is not set -# CONFIG_SERIAL_8250_MOXA is not set # # Non-8250 serial port support @@ -2450,34 +2474,54 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_CONSOLE_POLL=y # CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_LANTIQ is not set # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set # CONFIG_SERIAL_ARC is not set # CONFIG_SERIAL_RP2 is not set # CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_SPRD is not set # end of Serial drivers +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_ROCKETPORT is not set +# CONFIG_CYCLADES is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_SYNCLINK_GT is not set +# CONFIG_ISI is not set +# CONFIG_N_HDLC is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set +# CONFIG_NULL_TTY is not set +# CONFIG_TRACE_SINK is not set # CONFIG_SERIAL_DEV_BUS is not set # CONFIG_TTY_PRINTK is not set # CONFIG_PRINTER is not set # CONFIG_PPDEV is not set +# CONFIG_VIRTIO_CONSOLE is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set -# CONFIG_NVRAM is not set # CONFIG_APPLICOM is not set # CONFIG_MWAVE is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set +# CONFIG_NVRAM is not set # CONFIG_RAW_DRIVER is not set +CONFIG_DEVPORT=y # CONFIG_HPET is not set # CONFIG_HANGCHECK_TIMER is not set # CONFIG_TCG_TPM is not set # CONFIG_TELCLOCK is not set -CONFIG_DEVPORT=y # CONFIG_XILLYBUS is not set # end of Character devices # CONFIG_RANDOM_TRUST_CPU is not set +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set # # I2C support @@ -2538,7 +2582,6 @@ CONFIG_I2C_PIIX4=m # # CONFIG_I2C_DIOLAN_U2C is not set # CONFIG_I2C_PARPORT is not set -# CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -2584,6 +2627,10 @@ CONFIG_PTP_1588_CLOCK=y # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # CONFIG_PTP_1588_CLOCK_KVM=y +# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set +# CONFIG_PTP_1588_CLOCK_IDTCM is not set +# CONFIG_PTP_1588_CLOCK_VMW is not set +# CONFIG_PTP_1588_CLOCK_OCP is not set # end of PTP clock support CONFIG_PINCTRL=y @@ -2593,17 +2640,29 @@ CONFIG_PINCTRL=y # CONFIG_PINCTRL_SX150X is not set # CONFIG_PINCTRL_BAYTRAIL is not set # CONFIG_PINCTRL_CHERRYVIEW is not set +# CONFIG_PINCTRL_LYNXPOINT is not set +# CONFIG_PINCTRL_ALDERLAKE is not set # CONFIG_PINCTRL_BROXTON is not set # CONFIG_PINCTRL_CANNONLAKE is not set # CONFIG_PINCTRL_CEDARFORK is not set # CONFIG_PINCTRL_DENVERTON is not set +# CONFIG_PINCTRL_ELKHARTLAKE is not set +# CONFIG_PINCTRL_EMMITSBURG is not set # CONFIG_PINCTRL_GEMINILAKE is not set # CONFIG_PINCTRL_ICELAKE is not set +# CONFIG_PINCTRL_JASPERLAKE is not set +# CONFIG_PINCTRL_LAKEFIELD is not set # CONFIG_PINCTRL_LEWISBURG is not set # CONFIG_PINCTRL_SUNRISEPOINT is not set +# CONFIG_PINCTRL_TIGERLAKE is not set + +# +# Renesas pinctrl drivers +# +# end of Renesas pinctrl drivers + # CONFIG_GPIOLIB is not set # CONFIG_W1 is not set -# CONFIG_POWER_AVS is not set # CONFIG_POWER_RESET is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set @@ -2611,6 +2670,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_PDA_POWER is not set # CONFIG_TEST_POWER is not set # CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_CW2015 is not set # CONFIG_BATTERY_DS2780 is not set # CONFIG_BATTERY_DS2781 is not set # CONFIG_BATTERY_DS2782 is not set @@ -2624,6 +2684,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_CHARGER_BD99954 is not set CONFIG_HWMON=y # CONFIG_HWMON_DEBUG_CHIP is not set @@ -2639,20 +2700,27 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM1177 is not set # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7410 is not set # CONFIG_SENSORS_ADT7411 is not set # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_K8TEMP is not set CONFIG_SENSORS_K10TEMP=m # CONFIG_SENSORS_FAM15H_POWER is not set +# CONFIG_SENSORS_AMD_ENERGY is not set # CONFIG_SENSORS_APPLESMC is not set # CONFIG_SENSORS_ASB100 is not set # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set +# CONFIG_SENSORS_DRIVETEMP is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set CONFIG_SENSORS_DELL_SMM=m @@ -2674,6 +2742,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_POWR1220 is not set # CONFIG_SENSORS_LINEAGE is not set # CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2990 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set @@ -2681,10 +2750,12 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX1668 is not set # CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX31730 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set # CONFIG_SENSORS_MAX6642 is not set @@ -2693,6 +2764,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM73 is not set # CONFIG_SENSORS_LM75 is not set @@ -2718,6 +2790,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set +# CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set # CONFIG_SENSORS_SHTC1 is not set @@ -2734,7 +2807,6 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SMM665 is not set # CONFIG_SENSORS_ADC128D818 is not set -# CONFIG_SENSORS_ADS1015 is not set # CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_INA209 is not set @@ -2747,6 +2819,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_TMP108 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TMP513 is not set # CONFIG_SENSORS_VIA_CPUTEMP is not set # CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VT1211 is not set @@ -2769,6 +2842,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_ACPI_POWER is not set # CONFIG_SENSORS_ATK0110 is not set CONFIG_THERMAL=y +# CONFIG_THERMAL_NETLINK is not set # CONFIG_THERMAL_STATISTICS is not set CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y @@ -2776,12 +2850,10 @@ CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set -# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set # CONFIG_THERMAL_GOV_FAIR_SHARE is not set CONFIG_THERMAL_GOV_STEP_WISE=y # CONFIG_THERMAL_GOV_BANG_BANG is not set CONFIG_THERMAL_GOV_USER_SPACE=y -# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set # CONFIG_THERMAL_EMULATION is not set # @@ -2879,7 +2951,6 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_AXP20X_I2C is not set -# CONFIG_MFD_CROS_EC is not set # CONFIG_MFD_MADERA is not set # CONFIG_PMIC_DA903X is not set # CONFIG_MFD_DA9052_I2C is not set @@ -2889,12 +2960,15 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_DA9150 is not set # CONFIG_MFD_DLN2 is not set # CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MP2629 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set # CONFIG_LPC_ICH is not set # CONFIG_LPC_SCH is not set # CONFIG_MFD_INTEL_LPSS_ACPI is not set # CONFIG_MFD_INTEL_LPSS_PCI is not set +# CONFIG_MFD_INTEL_PMT is not set +# CONFIG_MFD_IQS62X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_KEMPLD is not set # CONFIG_MFD_88PM800 is not set @@ -2907,6 +2981,7 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_MAX8997 is not set # CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6360 is not set # CONFIG_MFD_MT6397 is not set # CONFIG_MFD_MENF21BMC is not set # CONFIG_MFD_VIPERBOARD is not set @@ -2919,7 +2994,6 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_MFD_SMSC is not set # CONFIG_ABX500_CORE is not set # CONFIG_MFD_SYSCON is not set # CONFIG_MFD_TI_AM335X_TSCADC is not set @@ -2965,6 +3039,7 @@ CONFIG_IR_XMP_DECODER=y # CONFIG_IR_IMON_DECODER is not set # CONFIG_IR_RCMM_DECODER is not set # CONFIG_RC_DEVICES is not set +# CONFIG_MEDIA_CEC_SUPPORT is not set # CONFIG_MEDIA_SUPPORT is not set # @@ -2985,6 +3060,7 @@ CONFIG_DRM=y # CONFIG_DRM_DEBUG_SELFTEST is not set CONFIG_DRM_KMS_HELPER=y CONFIG_DRM_KMS_FB_HELPER=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set @@ -2992,6 +3068,7 @@ CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_DP_CEC is not set CONFIG_DRM_TTM=m CONFIG_DRM_VRAM_HELPER=m +CONFIG_DRM_TTM_HELPER=m CONFIG_DRM_SCHED=m # @@ -3013,7 +3090,6 @@ CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_CIK=y CONFIG_DRM_AMDGPU_USERPTR=y -# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set # # ACP (Audio CoProcessor) Configuration @@ -3025,12 +3101,11 @@ CONFIG_DRM_AMDGPU_USERPTR=y # Display Engine Configuration # CONFIG_DRM_AMD_DC=y -CONFIG_DRM_AMD_DC_DCN1_0=y -CONFIG_DRM_AMD_DC_DCN2_0=y -# CONFIG_DRM_AMD_DC_DCN2_1 is not set -CONFIG_DRM_AMD_DC_DSC_SUPPORT=y +CONFIG_DRM_AMD_DC_DCN=y # CONFIG_DRM_AMD_DC_HDCP is not set +# CONFIG_DRM_AMD_DC_SI is not set # CONFIG_DEBUG_KERNEL_DC is not set +# CONFIG_DRM_AMD_SECURE_DISPLAY is not set # end of Display Engine Configuration CONFIG_HSA_AMD=y @@ -3043,9 +3118,9 @@ CONFIG_HSA_AMD=y # CONFIG_DRM_UDL is not set CONFIG_DRM_AST=m # CONFIG_DRM_MGAG200 is not set -# CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_QXL is not set # CONFIG_DRM_BOCHS is not set +# CONFIG_DRM_VIRTIO_GPU is not set CONFIG_DRM_PANEL=y # @@ -3063,6 +3138,7 @@ CONFIG_DRM_PANEL_BRIDGE=y # end of Display Interface Bridges # CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_VBOXVIDEO is not set # CONFIG_DRM_LEGACY is not set @@ -3139,9 +3215,8 @@ CONFIG_FB_DEFERRED_IO=y # # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set # CONFIG_BACKLIGHT_APPLE is not set -# CONFIG_BACKLIGHT_PM8941_WLED is not set +# CONFIG_BACKLIGHT_QCOM_WLED is not set # CONFIG_BACKLIGHT_SAHARA is not set # CONFIG_BACKLIGHT_ADP8860 is not set # CONFIG_BACKLIGHT_ADP8870 is not set @@ -3157,9 +3232,6 @@ CONFIG_HDMI=y # Console display driver support # CONFIG_VGA_CONSOLE=y -CONFIG_VGACON_SOFT_SCROLLBACK=y -CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 -# CONFIG_VGACON_SOFT_SCROLLBACK_PERSISTENT_ENABLE_BY_DEFAULT is not set CONFIG_DUMMY_CONSOLE=y CONFIG_DUMMY_CONSOLE_COLUMNS=80 CONFIG_DUMMY_CONSOLE_ROWS=25 @@ -3202,6 +3274,7 @@ CONFIG_HID_CHICONY=y # CONFIG_HID_COUGAR is not set # CONFIG_HID_MACALLY is not set # CONFIG_HID_CMEDIA is not set +# CONFIG_HID_CREATIVE_SB0540 is not set CONFIG_HID_CYPRESS=y # CONFIG_HID_DRAGONRISE is not set # CONFIG_HID_EMS_FF is not set @@ -3211,7 +3284,9 @@ CONFIG_HID_CYPRESS=y CONFIG_HID_EZKEY=y # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set +# CONFIG_HID_GLORIOUS is not set # CONFIG_HID_HOLTEK is not set +# CONFIG_HID_VIVALDI is not set # CONFIG_HID_GT683R is not set # CONFIG_HID_KEYTOUCH is not set CONFIG_HID_KYE=y @@ -3295,11 +3370,19 @@ CONFIG_USB_HIDDEV=y # # CONFIG_INTEL_ISH_HID is not set # end of Intel ISH HID support + +# +# AMD SFH HID Support +# +# CONFIG_AMD_SFH_HID is not set +# end of AMD SFH HID Support # end of HID support CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_SUPPORT=y CONFIG_USB_COMMON=y +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_ULPI_BUS is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y CONFIG_USB_PCI=y @@ -3309,14 +3392,14 @@ CONFIG_USB_PCI=y # Miscellaneous USB options # CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set CONFIG_USB_AUTOSUSPEND_DELAY=2 # CONFIG_USB_MON is not set -# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -3325,6 +3408,7 @@ CONFIG_USB_AUTOSUSPEND_DELAY=2 CONFIG_USB_XHCI_HCD=y # CONFIG_USB_XHCI_DBGCAP is not set CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PCI_RENESAS is not set # CONFIG_USB_XHCI_PLATFORM is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y @@ -3381,6 +3465,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set +# CONFIG_USB_CDNS3 is not set # CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_DWC3 is not set # CONFIG_USB_DWC2 is not set @@ -3400,7 +3485,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set # CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set # CONFIG_USB_CYPRESS_CY7C63 is not set @@ -3408,6 +3492,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_APPLE_MFI_FASTCHARGE is not set # CONFIG_USB_SISUSBVGA is not set # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set @@ -3432,14 +3517,12 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_GADGET is not set # CONFIG_TYPEC is not set # CONFIG_USB_ROLE_SWITCH is not set -# CONFIG_USB_LED_TRIG is not set -# CONFIG_USB_ULPI_BUS is not set -# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y # CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_CLASS_MULTICOLOR is not set # CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set # @@ -3451,10 +3534,6 @@ CONFIG_LEDS_CLASS=y # CONFIG_LEDS_LM3642 is not set # CONFIG_LEDS_PCA9532 is not set # CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_LP5521 is not set -# CONFIG_LEDS_LP5523 is not set -# CONFIG_LEDS_LP5562 is not set -# CONFIG_LEDS_LP8501 is not set # CONFIG_LEDS_CLEVO_MAIL is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set @@ -3472,7 +3551,10 @@ CONFIG_LEDS_CLASS=y # CONFIG_LEDS_MLXREG is not set # CONFIG_LEDS_USER is not set # CONFIG_LEDS_NIC78BX is not set -# CONFIG_LEDS_TI_LMU_COMMON is not set + +# +# Flash and Torch LED drivers +# # # LED Triggers @@ -3539,7 +3621,6 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_PCF8563 is not set # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_BD70528 is not set # CONFIG_RTC_DRV_BQ32K is not set # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set @@ -3548,6 +3629,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_RX8025 is not set # CONFIG_RTC_DRV_EM3027 is not set # CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV3032 is not set # CONFIG_RTC_DRV_RV8803 is not set # CONFIG_RTC_DRV_SD3078 is not set @@ -3562,6 +3644,7 @@ CONFIG_RTC_I2C_AND_SPI=y # CONFIG_RTC_DRV_DS3232 is not set # CONFIG_RTC_DRV_PCF2127 is not set # CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set # # Platform RTC drivers @@ -3600,7 +3683,10 @@ CONFIG_DMA_ENGINE=y CONFIG_DMA_ACPI=y # CONFIG_ALTERA_MSGDMA is not set # CONFIG_INTEL_IDMA64 is not set +# CONFIG_INTEL_IDXD is not set # CONFIG_INTEL_IOATDMA is not set +# CONFIG_PLX_DMA is not set +# CONFIG_XILINX_ZYNQMP_DPDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_HIDMA is not set CONFIG_DW_DMAC_CORE=y @@ -3608,6 +3694,7 @@ CONFIG_DW_DMAC_CORE=y CONFIG_DW_DMAC_PCI=y # CONFIG_DW_EDMA is not set # CONFIG_DW_EDMA_PCIE is not set +# CONFIG_SF_PDMA is not set # # DMA Clients @@ -3621,7 +3708,10 @@ CONFIG_DW_DMAC_PCI=y CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_HEAPS is not set # end of DMABUF options # CONFIG_AUXDISPLAY is not set @@ -3632,6 +3722,10 @@ CONFIG_SYNC_FILE=y CONFIG_VIRTIO_MENU=y # CONFIG_VIRTIO_PCI is not set # CONFIG_VIRTIO_MMIO is not set +# CONFIG_VDPA is not set +CONFIG_VHOST_MENU=y +# CONFIG_VHOST_NET is not set +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set # # Microsoft Hyper-V guest support @@ -3639,26 +3733,26 @@ CONFIG_VIRTIO_MENU=y # CONFIG_HYPERV is not set # end of Microsoft Hyper-V guest support +# CONFIG_GREYBUS is not set # CONFIG_STAGING is not set # CONFIG_X86_PLATFORM_DEVICES is not set CONFIG_PMC_ATOM=y # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set +CONFIG_SURFACE_PLATFORMS=y +# CONFIG_SURFACE_3_POWER_OPREGION is not set +# CONFIG_SURFACE_GPE is not set +# CONFIG_SURFACE_PRO3_BUTTON is not set +CONFIG_HAVE_CLK=y CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y - -# -# Common Clock Framework -# # CONFIG_COMMON_CLK_MAX9485 is not set # CONFIG_COMMON_CLK_SI5341 is not set # CONFIG_COMMON_CLK_SI5351 is not set # CONFIG_COMMON_CLK_SI544 is not set # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set -# end of Common Clock Framework - # CONFIG_HWSPINLOCK is not set # @@ -3683,6 +3777,7 @@ CONFIG_IOMMU_SUPPORT=y # CONFIG_IOMMU_DEBUGFS is not set # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_IOMMU_DMA=y CONFIG_AMD_IOMMU=y CONFIG_AMD_IOMMU_V2=m # CONFIG_INTEL_IOMMU is not set @@ -3712,11 +3807,6 @@ CONFIG_AMD_IOMMU_V2=m # # end of Amlogic SoC drivers -# -# Aspeed SoC drivers -# -# end of Aspeed SoC drivers - # # Broadcom SoC drivers # @@ -3733,11 +3823,9 @@ CONFIG_AMD_IOMMU_V2=m # end of i.MX SoC drivers # -# IXP4xx SoC drivers +# Enable LiteX SoC Builder specific drivers # -# CONFIG_IXP4XX_QMGR is not set -# CONFIG_IXP4XX_NPE is not set -# end of IXP4xx SoC drivers +# end of Enable LiteX SoC Builder specific drivers # # Qualcomm SoC drivers @@ -3773,9 +3861,11 @@ CONFIG_AMD_IOMMU_V2=m # PHY Subsystem # # CONFIG_GENERIC_PHY is not set +# CONFIG_USB_LGM_PHY is not set # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_INTEL_LGM_EMMC is not set # end of PHY Subsystem # CONFIG_POWERCAP is not set @@ -3788,7 +3878,7 @@ CONFIG_AMD_IOMMU_V2=m CONFIG_RAS=y # CONFIG_RAS_CEC is not set -# CONFIG_THUNDERBOLT is not set +# CONFIG_USB4 is not set # # Android @@ -3799,6 +3889,7 @@ CONFIG_RAS=y # CONFIG_LIBNVDIMM is not set CONFIG_DAX=y # CONFIG_DEV_DAX is not set +# CONFIG_DEV_DAX_HMEM is not set CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y @@ -3810,11 +3901,13 @@ CONFIG_NVMEM_SYSFS=y # end of HW tracing support # CONFIG_FPGA is not set +# CONFIG_TEE is not set # CONFIG_UNISYS_VISORBUS is not set # CONFIG_SIOX is not set # CONFIG_SLIMBUS is not set # CONFIG_INTERCONNECT is not set # CONFIG_COUNTER is not set +# CONFIG_MOST is not set # end of Device Drivers # @@ -3836,6 +3929,7 @@ CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_XFS_FS=y +CONFIG_XFS_SUPPORT_V4=y CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y CONFIG_XFS_RT=y @@ -3854,6 +3948,7 @@ CONFIG_EXPORTFS=y CONFIG_FILE_LOCKING=y CONFIG_MANDATORY_FILE_LOCKING=y # CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y @@ -3866,11 +3961,11 @@ CONFIG_QUOTA_TREE=y # CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=y CONFIG_QUOTACTL=y -CONFIG_QUOTACTL_COMPAT=y CONFIG_AUTOFS4_FS=y CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=m CONFIG_CUSE=m +# CONFIG_VIRTIO_FS is not set CONFIG_OVERLAY_FS=y # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y @@ -3899,7 +3994,7 @@ CONFIG_ZISOFS=y # end of CD-ROM/DVD Filesystems # -# DOS/FAT/NT Filesystems +# DOS/FAT/EXFAT/NT Filesystems # CONFIG_FAT_FS=y CONFIG_MSDOS_FS=y @@ -3907,10 +4002,11 @@ CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_EXFAT_FS is not set CONFIG_NTFS_FS=y # CONFIG_NTFS_DEBUG is not set CONFIG_NTFS_RW=y -# end of DOS/FAT/NT Filesystems +# end of DOS/FAT/EXFAT/NT Filesystems # # Pseudo filesystems @@ -3928,6 +4024,7 @@ CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y +# CONFIG_TMPFS_INODE64 is not set CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y CONFIG_MEMFD_CREATE=y @@ -3956,6 +4053,7 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_QNX6FS_FS is not set # CONFIG_ROMFS_FS is not set CONFIG_PSTORE=y +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 CONFIG_PSTORE_DEFLATE_COMPRESS=y # CONFIG_PSTORE_LZO_COMPRESS is not set # CONFIG_PSTORE_LZ4_COMPRESS is not set @@ -3969,8 +4067,10 @@ CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" # CONFIG_PSTORE_PMSG is not set # CONFIG_PSTORE_FTRACE is not set # CONFIG_PSTORE_RAM is not set +# CONFIG_PSTORE_BLK is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set +# CONFIG_EROFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V2=y @@ -3983,6 +4083,7 @@ CONFIG_ROOT_NFS=y # CONFIG_NFS_FSCACHE is not set # CONFIG_NFS_USE_LEGACY_DNS is not set CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y # CONFIG_NFSD is not set CONFIG_GRACE_PERIOD=y CONFIG_LOCKD=y @@ -4003,7 +4104,9 @@ CONFIG_CIFS_DEBUG=y # CONFIG_CIFS_DEBUG2 is not set # CONFIG_CIFS_DEBUG_DUMP_KEYS is not set # CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y +# CONFIG_CIFS_ROOT is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set CONFIG_NLS=y @@ -4059,16 +4162,15 @@ CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=y # CONFIG_DLM is not set # CONFIG_UNICODE is not set +CONFIG_IO_WQ=y # end of File systems # # Security options # CONFIG_KEYS=y -CONFIG_KEYS_COMPAT=y # CONFIG_KEYS_REQUEST_CACHE is not set # CONFIG_PERSISTENT_KEYRINGS is not set -# CONFIG_BIG_KEYS is not set # CONFIG_ENCRYPTED_KEYS is not set # CONFIG_KEY_DH_OPERATIONS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set @@ -4090,16 +4192,20 @@ CONFIG_SECURITY_SELINUX_DISABLE=y CONFIG_SECURITY_SELINUX_DEVELOP=y CONFIG_SECURITY_SELINUX_AVC_STATS=y CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 +CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 # CONFIG_SECURITY_SMACK is not set # CONFIG_SECURITY_TOMOYO is not set # CONFIG_SECURITY_APPARMOR is not set # CONFIG_SECURITY_LOADPIN is not set # CONFIG_SECURITY_YAMA is not set # CONFIG_SECURITY_SAFESETID is not set +# CONFIG_SECURITY_LOCKDOWN_LSM is not set CONFIG_INTEGRITY=y # CONFIG_INTEGRITY_SIGNATURE is not set CONFIG_INTEGRITY_AUDIT=y # CONFIG_IMA is not set +# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set # CONFIG_EVM is not set CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SECURITY_DAC is not set @@ -4128,8 +4234,8 @@ CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=y @@ -4158,6 +4264,9 @@ CONFIG_CRYPTO_RSA=y # CONFIG_CRYPTO_DH is not set # CONFIG_CRYPTO_ECDH is not set # CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_CURVE25519 is not set +# CONFIG_CRYPTO_CURVE25519_X86 is not set # # Authenticated Encryption with Associated Data @@ -4166,16 +4275,7 @@ CONFIG_CRYPTO_CCM=y CONFIG_CRYPTO_GCM=y # CONFIG_CRYPTO_CHACHA20POLY1305 is not set # CONFIG_CRYPTO_AEGIS128 is not set -# CONFIG_CRYPTO_AEGIS128L is not set -# CONFIG_CRYPTO_AEGIS256 is not set # CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set -# CONFIG_CRYPTO_AEGIS128L_AESNI_SSE2 is not set -# CONFIG_CRYPTO_AEGIS256_AESNI_SSE2 is not set -# CONFIG_CRYPTO_MORUS640 is not set -# CONFIG_CRYPTO_MORUS640_SSE2 is not set -# CONFIG_CRYPTO_MORUS1280 is not set -# CONFIG_CRYPTO_MORUS1280_SSE2 is not set -# CONFIG_CRYPTO_MORUS1280_AVX2 is not set CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_ECHAINIV=y @@ -4195,6 +4295,7 @@ CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set # CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set # CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_ESSIV is not set # # Hash modes @@ -4212,6 +4313,9 @@ CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_CRC32 is not set # CONFIG_CRYPTO_CRC32_PCLMUL is not set # CONFIG_CRYPTO_XXHASH is not set +# CONFIG_CRYPTO_BLAKE2B is not set +# CONFIG_CRYPTO_BLAKE2S is not set +# CONFIG_CRYPTO_BLAKE2S_X86 is not set CONFIG_CRYPTO_CRCT10DIF=y # CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set CONFIG_CRYPTO_GHASH=y @@ -4242,11 +4346,7 @@ CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_TI is not set -# CONFIG_CRYPTO_AES_X86_64 is not set # CONFIG_CRYPTO_AES_NI_INTEL is not set -# CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_LIB_ARC4=y -CONFIG_CRYPTO_ARC4=y # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_BLOWFISH_X86_64 is not set # CONFIG_CRYPTO_CAMELLIA is not set @@ -4260,17 +4360,14 @@ CONFIG_CRYPTO_ARC4=y CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_DES3_EDE_X86_64 is not set # CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_CHACHA20 is not set # CONFIG_CRYPTO_CHACHA20_X86_64 is not set -# CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set # CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set # CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set # CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set # CONFIG_CRYPTO_SM4 is not set -# CONFIG_CRYPTO_TEA is not set # CONFIG_CRYPTO_TWOFISH is not set # CONFIG_CRYPTO_TWOFISH_X86_64 is not set # CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set @@ -4301,6 +4398,20 @@ CONFIG_CRYPTO_JITTERENTROPY=y # CONFIG_CRYPTO_USER_API_RNG is not set # CONFIG_CRYPTO_USER_API_AEAD is not set CONFIG_CRYPTO_HASH_INFO=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=y +# CONFIG_CRYPTO_LIB_BLAKE2S is not set +# CONFIG_CRYPTO_LIB_CHACHA is not set +# CONFIG_CRYPTO_LIB_CURVE25519 is not set +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 +# CONFIG_CRYPTO_LIB_POLY1305 is not set +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_PADLOCK is not set # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set @@ -4309,10 +4420,13 @@ CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set # CONFIG_CRYPTO_DEV_QAT_C3XXX is not set # CONFIG_CRYPTO_DEV_QAT_C62X is not set +# CONFIG_CRYPTO_DEV_QAT_4XXX is not set # CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set # CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set # CONFIG_CRYPTO_DEV_QAT_C62XVF is not set # CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y @@ -4344,11 +4458,13 @@ CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y CONFIG_GENERIC_FIND_FIRST_BIT=y # CONFIG_CORDIC is not set +# CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_USE_SYM_ANNOTATIONS=y CONFIG_CRC_CCITT=y CONFIG_CRC16=y CONFIG_CRC_T10DIF=y @@ -4371,6 +4487,7 @@ CONFIG_ZLIB_DEFLATE=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y CONFIG_XZ_DEC_POWERPC=y @@ -4386,6 +4503,7 @@ CONFIG_DECOMPRESS_LZMA=y CONFIG_DECOMPRESS_XZ=y CONFIG_DECOMPRESS_LZO=y CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_ZSTD=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m @@ -4397,12 +4515,14 @@ CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y +CONFIG_DMA_OPS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y CONFIG_SWIOTLB=y # CONFIG_DMA_CMA is not set # CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_IOMMU_HELPER=y CONFIG_CHECK_SIGNATURE=y @@ -4414,11 +4534,11 @@ CONFIG_NLATTR=y CONFIG_CLZ_TAB=y # CONFIG_IRQ_POLL is not set CONFIG_MPILIB=y -CONFIG_DIMLIB=y CONFIG_OID_REGISTRY=y CONFIG_UCS2_STRING=y CONFIG_HAVE_GENERIC_VDSO=y CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_TIME_NS=y CONFIG_FONT_SUPPORT=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y @@ -4426,7 +4546,7 @@ CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_ARCH_HAS_PMEM_API=y CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y -CONFIG_ARCH_HAS_UACCESS_MCSAFE=y +CONFIG_ARCH_HAS_COPY_MC=y CONFIG_ARCH_STACKWALK=y CONFIG_SBITMAP=y # CONFIG_STRING_SELFTEST is not set @@ -4446,29 +4566,53 @@ CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_BOOT_PRINTK_DELAY is not set CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options # # Compile-time checks and compiler options # # CONFIG_DEBUG_INFO is not set -CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y # CONFIG_HEADERS_INSTALL is not set -CONFIG_OPTIMIZE_INLINING=y # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set CONFIG_STACK_VALIDATION=y # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options +# +# Generic Kernel Debugging Instruments +# CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_KGDB=y +CONFIG_KGDB_HONOUR_BLOCKLIST=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +CONFIG_KGDB_LOW_LEVEL_TRAP=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_DEFAULT_ENABLE=0x1 +CONFIG_KDB_KEYBOARD=y +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_ARCH_HAS_EARLY_DEBUG=y +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_HAVE_ARCH_KCSAN=y +# end of Generic Kernel Debugging Instruments + CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y @@ -4481,35 +4625,43 @@ CONFIG_DEBUG_MISC=y # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_PAGE_REF is not set CONFIG_DEBUG_RODATA_TEST=y +CONFIG_ARCH_HAS_DEBUG_WX=y +# CONFIG_DEBUG_WX is not set +CONFIG_GENERIC_PTDUMP=y +# CONFIG_PTDUMP_DEBUGFS is not set # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y CONFIG_DEBUG_KMEMLEAK=y -CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=400 +CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE=16000 # CONFIG_DEBUG_KMEMLEAK_TEST is not set CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y # CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y # CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y +# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y -# CONFIG_KASAN is not set -CONFIG_KASAN_STACK=1 # end of Memory Debugging -CONFIG_ARCH_HAS_KCOV=y -CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set CONFIG_DEBUG_SHIRQ=y # -# Debug Lockups and Hangs +# Debug Oops, Lockups and Hangs # +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 CONFIG_LOCKUP_DETECTOR=y CONFIG_SOFTLOCKUP_DETECTOR=y # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set @@ -4524,15 +4676,17 @@ CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 # CONFIG_WQ_WATCHDOG is not set -# end of Debug Lockups and Hangs +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 +# +# Scheduler Debugging +# CONFIG_SCHED_DEBUG=y CONFIG_SCHED_INFO=y CONFIG_SCHEDSTATS=y -CONFIG_SCHED_STACK_END_CHECK=y +# end of Scheduler Debugging + # CONFIG_DEBUG_TIMEKEEPING is not set # @@ -4540,6 +4694,7 @@ CONFIG_SCHED_STACK_END_CHECK=y # CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_PROVE_LOCKING=y +# CONFIG_PROVE_RAW_LOCK_NESTING is not set # CONFIG_LOCK_STAT is not set CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y @@ -4553,25 +4708,35 @@ CONFIG_DEBUG_ATOMIC_SLEEP=y # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_LOCK_TORTURE_TEST is not set # CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set # end of Lock Debugging (spinlocks, mutexes, etc...) CONFIG_TRACE_IRQFLAGS=y +CONFIG_TRACE_IRQFLAGS_NMI=y CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_BUGVERBOSE=y + +# +# Debug kernel data structures +# # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_PLIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Debug kernel data structures + # CONFIG_DEBUG_CREDENTIALS is not set # # RCU Debugging # CONFIG_PROVE_RCU=y -# CONFIG_RCU_PERF_TEST is not set +# CONFIG_RCU_SCALE_TEST is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set CONFIG_RCU_CPU_STALL_TIMEOUT=60 # CONFIG_RCU_TRACE is not set # CONFIG_RCU_EQS_DEBUG is not set @@ -4580,9 +4745,6 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=60 # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -# CONFIG_NOTIFIER_ERROR_INJECTION is not set -CONFIG_FUNCTION_ERROR_INJECTION=y -# CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_USER_STACKTRACE_SUPPORT=y CONFIG_NOP_TRACER=y @@ -4590,6 +4752,8 @@ CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_FENTRY=y @@ -4602,22 +4766,28 @@ CONFIG_CONTEXT_SWITCH_TRACER=y CONFIG_RING_BUFFER_ALLOW_SWAP=y CONFIG_PREEMPTIRQ_TRACEPOINTS=y CONFIG_TRACING=y +CONFIG_GLOBAL_TRACE_BUF_SIZE=1441792 CONFIG_GENERIC_TRACER=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y +# CONFIG_BOOTTIME_TRACING is not set CONFIG_FUNCTION_TRACER=y CONFIG_FUNCTION_GRAPH_TRACER=y -# CONFIG_PREEMPTIRQ_EVENTS is not set +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y # CONFIG_IRQSOFF_TRACER is not set CONFIG_SCHED_TRACER=y CONFIG_HWLAT_TRACER=y +CONFIG_MMIOTRACE=y CONFIG_FTRACE_SYSCALLS=y CONFIG_TRACER_SNAPSHOT=y # CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set CONFIG_BRANCH_PROFILE_NONE=y # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set # CONFIG_PROFILE_ALL_BRANCHES is not set -CONFIG_STACK_TRACER=y CONFIG_BLK_DEV_IO_TRACE=y CONFIG_KPROBE_EVENTS=y # CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set @@ -4625,49 +4795,39 @@ CONFIG_UPROBE_EVENTS=y CONFIG_BPF_EVENTS=y CONFIG_DYNAMIC_EVENTS=y CONFIG_PROBE_EVENTS=y -CONFIG_DYNAMIC_FTRACE=y -CONFIG_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_FUNCTION_PROFILER=y # CONFIG_BPF_KPROBE_OVERRIDE is not set CONFIG_FTRACE_MCOUNT_RECORD=y -# CONFIG_FTRACE_STARTUP_TEST is not set -CONFIG_MMIOTRACE=y CONFIG_TRACING_MAP=y +CONFIG_SYNTH_EVENTS=y CONFIG_HIST_TRIGGERS=y -# CONFIG_MMIOTRACE_TEST is not set +# CONFIG_TRACE_EVENT_INJECT is not set # CONFIG_TRACEPOINT_BENCHMARK is not set # CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_STARTUP_TEST is not set # CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +# CONFIG_MMIOTRACE_TEST is not set # CONFIG_PREEMPTIRQ_DELAY_TEST is not set -# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_SYNTH_EVENT_GEN_TEST is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +# CONFIG_HIST_TRIGGERS_DEBUG is not set # CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set -# CONFIG_RUNTIME_TESTING_MENU is not set -CONFIG_MEMTEST=y -# CONFIG_BUG_ON_DATA_CORRUPTION is not set # CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_KGDB=y -CONFIG_KGDB_SERIAL_CONSOLE=y -# CONFIG_KGDB_TESTS is not set -CONFIG_KGDB_LOW_LEVEL_TRAP=y -CONFIG_KGDB_KDB=y -CONFIG_KDB_DEFAULT_ENABLE=0x1 -CONFIG_KDB_KEYBOARD=y -CONFIG_KDB_CONTINUE_CATASTROPHIC=0 -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y -# CONFIG_UBSAN is not set -CONFIG_UBSAN_ALIGNMENT=y CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # CONFIG_STRICT_DEVMEM is not set + +# +# x86 Debugging +# CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y # CONFIG_X86_VERBOSE_BOOTUP is not set CONFIG_EARLY_PRINTK=y # CONFIG_EARLY_PRINTK_DBGP is not set # CONFIG_EARLY_PRINTK_USB_XDBC is not set -# CONFIG_X86_PTDUMP is not set # CONFIG_EFI_PGT_DUMP is not set -# CONFIG_DEBUG_WX is not set -CONFIG_DOUBLEFAULT=y # CONFIG_DEBUG_TLBFLUSH is not set # CONFIG_IOMMU_DEBUG is not set CONFIG_HAVE_MMIOTRACE_SUPPORT=y @@ -4685,4 +4845,19 @@ CONFIG_X86_DEBUG_FPU=y CONFIG_UNWINDER_ORC=y # CONFIG_UNWINDER_FRAME_POINTER is not set # CONFIG_UNWINDER_GUESS is not set +# end of x86 Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_MEMTEST=y +# end of Kernel Testing and Coverage # end of Kernel hacking From f38911414137a9c5b127f6b656f6ecac4f8a7c5f Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 14 Apr 2021 20:13:19 -0400 Subject: [PATCH 0011/2653] rock-dbg_defconfig: Enable Intel IOMMU Enable the Intel IOMMU driver in the rock-dbg_defconfig. This enables testing of DMA mappings on systems with an Intel IOMMU. Signed-off-by: Felix Kuehling Acked-by: Oak Zeng Acked-by: Ramesh Errabolu Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index 55fa96bf27502..32191eaa2556f 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -296,6 +296,7 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_ZONE_DMA32=y CONFIG_AUDIT_ARCH=y +CONFIG_HAVE_INTEL_TXT=y CONFIG_X86_64_SMP=y CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_FIX_EARLYCON_MEM=y @@ -3109,6 +3110,7 @@ CONFIG_DRM_AMD_DC_DCN=y # end of Display Engine Configuration CONFIG_HSA_AMD=y +CONFIG_HSA_AMD_SVM=y # CONFIG_DRM_NOUVEAU is not set # CONFIG_DRM_I915 is not set # CONFIG_DRM_VGEM is not set @@ -3767,6 +3769,7 @@ CONFIG_MAILBOX=y CONFIG_PCC=y # CONFIG_ALTERA_MBOX is not set CONFIG_IOMMU_IOVA=y +CONFIG_IOASID=y CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y @@ -3780,7 +3783,12 @@ CONFIG_IOMMU_SUPPORT=y CONFIG_IOMMU_DMA=y CONFIG_AMD_IOMMU=y CONFIG_AMD_IOMMU_V2=m -# CONFIG_INTEL_IOMMU is not set +CONFIG_DMAR_TABLE=y +CONFIG_INTEL_IOMMU=y +# CONFIG_INTEL_IOMMU_SVM is not set +CONFIG_INTEL_IOMMU_DEFAULT_ON=y +CONFIG_INTEL_IOMMU_FLOPPY_WA=y +# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set # CONFIG_IRQ_REMAP is not set # @@ -4181,6 +4189,7 @@ CONFIG_SECURITY_NETWORK=y CONFIG_PAGE_TABLE_ISOLATION=y # CONFIG_SECURITY_NETWORK_XFRM is not set # CONFIG_SECURITY_PATH is not set +# CONFIG_INTEL_TXT is not set CONFIG_LSM_MMAP_MIN_ADDR=65536 CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y # CONFIG_HARDENED_USERCOPY is not set From 6f03e7d5894de12eb279555bbebfe8dc7f590326 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 7 Jul 2021 17:54:53 -0400 Subject: [PATCH 0012/2653] rock-dbg_defconfig: Update for 5.13 Also build drm as module to make debugging easier. Signed-off-by: Felix Kuehling Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 177 +++++++++++++++++----------- 1 file changed, 108 insertions(+), 69 deletions(-) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index 32191eaa2556f..4877da183599f 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -1,12 +1,15 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/x86 5.11.0 Kernel Configuration +# Linux/x86 5.13.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="gcc (Ubuntu 7.5.0-3ubuntu1~18.04) 7.5.0" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=70500 -CONFIG_LD_VERSION=230000000 CONFIG_CLANG_VERSION=0 +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=23000 +CONFIG_LD_IS_BFD=y +CONFIG_LD_VERSION=23000 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y @@ -96,6 +99,19 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +# CONFIG_BPF_JIT is not set +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +# CONFIG_BPF_PRELOAD is not set +# end of BPF subsystem + # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set @@ -173,6 +189,7 @@ CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_MISC is not set # CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y @@ -203,7 +220,6 @@ CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_HAVE_PCSPKR_PLATFORM=y -CONFIG_BPF=y CONFIG_EXPERT=y CONFIG_UID16=y CONFIG_MULTIUSER=y @@ -232,9 +248,6 @@ CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y CONFIG_KALLSYMS_BASE_RELATIVE=y -CONFIG_BPF_SYSCALL=y -CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y -# CONFIG_BPF_PRELOAD is not set # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y @@ -253,7 +266,6 @@ CONFIG_PERF_EVENTS=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y -# CONFIG_SLUB_MEMCG_SYSFS_ON is not set # CONFIG_COMPAT_BRK is not set # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -286,7 +298,6 @@ CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ARCH_HAS_CPU_RELAX=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_FILTER_PGPROT=y CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y @@ -377,7 +388,6 @@ CONFIG_X86_MCE_INTEL=y CONFIG_X86_MCE_AMD=y CONFIG_X86_MCE_THRESHOLD=y # CONFIG_X86_MCE_INJECT is not set -CONFIG_X86_THERMAL_VECTOR=y # # Performance monitoring @@ -469,12 +479,8 @@ CONFIG_HAVE_LIVEPATCH=y # end of Processor type and features CONFIG_ARCH_HAS_ADD_PAGES=y -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y CONFIG_USE_PERCPU_NUMA_NODE_ID=y -CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y -CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y -CONFIG_ARCH_ENABLE_THP_MIGRATION=y # # Power management and ACPI options @@ -511,6 +517,7 @@ CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y # CONFIG_ACPI_DEBUGGER is not set CONFIG_ACPI_SPCR_TABLE=y +# CONFIG_ACPI_FPDT is not set CONFIG_ACPI_LPIT=y CONFIG_ACPI_SLEEP=y CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y @@ -543,6 +550,7 @@ CONFIG_ACPI_HED=y CONFIG_ACPI_BGRT=y # CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set # CONFIG_ACPI_NFIT is not set +CONFIG_ACPI_NUMA=y # CONFIG_ACPI_HMAT is not set CONFIG_HAVE_ACPI_APEI=y CONFIG_HAVE_ACPI_APEI_NMI=y @@ -556,7 +564,6 @@ CONFIG_ACPI_APEI_EINJ=m # CONFIG_ACPI_CONFIGFS is not set # CONFIG_PMIC_OPREGION is not set CONFIG_X86_PM_TIMER=y -CONFIG_SFI=y # # CPU Frequency scaling @@ -687,10 +694,6 @@ CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y CONFIG_HOTPLUG_SMT=y CONFIG_GENERIC_ENTRY=y -CONFIG_OPROFILE=m -# CONFIG_OPROFILE_EVENT_MULTIPLEX is not set -CONFIG_HAVE_OPROFILE=y -CONFIG_OPROFILE_NMI_TIMER=y CONFIG_KPROBES=y CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set @@ -746,6 +749,9 @@ CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_LTO_NONE=y CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_CONTEXT_TRACKING_OFFSTACK=y @@ -760,6 +766,8 @@ CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_HAVE_ARCH_SOFT_DIRTY=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y @@ -774,6 +782,8 @@ CONFIG_COMPAT_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y @@ -784,8 +794,10 @@ CONFIG_ARCH_USE_MEMREMAP_PROT=y CONFIG_ARCH_HAS_MEM_ENCRYPT=y CONFIG_HAVE_STATIC_CALL=y CONFIG_HAVE_STATIC_CALL_INLINE=y +CONFIG_HAVE_PREEMPT_DYNAMIC=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_HAS_ELFCORE_COMPAT=y # # GCOV-based kernel profiling @@ -816,9 +828,12 @@ CONFIG_MODULE_SIG_ALL=y # CONFIG_MODULE_SIG_SHA384 is not set CONFIG_MODULE_SIG_SHA512=y CONFIG_MODULE_SIG_HASH="sha512" -# CONFIG_MODULE_COMPRESS is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y @@ -917,17 +932,22 @@ CONFIG_HAVE_FAST_GUP=y CONFIG_NUMA_KEEP_MEMINFO=y CONFIG_MEMORY_ISOLATION=y CONFIG_HAVE_BOOTMEM_INFO_NODE=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_MEMORY_HOTPLUG=y CONFIG_MEMORY_HOTPLUG_SPARSE=y # CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_MEMORY_HOTREMOVE=y +CONFIG_MHP_MEMMAP_ON_MEMORY=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y CONFIG_COMPACTION=y # CONFIG_PAGE_REPORTING is not set CONFIG_MIGRATION=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y CONFIG_MMU_NOTIFIER=y CONFIG_KSM=y @@ -945,6 +965,7 @@ CONFIG_FRONTSWAP=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set +# CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 CONFIG_MEM_SOFT_DIRTY=y CONFIG_ZSWAP=y @@ -968,6 +989,7 @@ CONFIG_ZSMALLOC=y CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ZONE_DEVICE=y CONFIG_DEV_PAGEMAP_OPS=y @@ -1101,8 +1123,7 @@ CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NETFILTER_NETLINK_LOG=m CONFIG_NETFILTER_NETLINK_OSF=m CONFIG_NF_CONNTRACK=m -CONFIG_NF_LOG_COMMON=m -# CONFIG_NF_LOG_NETDEV is not set +CONFIG_NF_LOG_SYSLOG=m CONFIG_NETFILTER_CONNCOUNT=m CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y @@ -1163,6 +1184,7 @@ CONFIG_NF_DUP_NETDEV=m # CONFIG_NFT_REJECT_NETDEV is not set # CONFIG_NF_FLOW_TABLE is not set CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XTABLES_COMPAT=y # # Xtables combined modules @@ -1344,7 +1366,6 @@ CONFIG_BRIDGE_IGMP_SNOOPING=y # CONFIG_BRIDGE_VLAN_FILTERING is not set # CONFIG_BRIDGE_MRP is not set # CONFIG_BRIDGE_CFM is not set -CONFIG_HAVE_NET_DSA=y # CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=y # CONFIG_VLAN_8021Q_GVRP is not set @@ -1454,14 +1475,15 @@ CONFIG_NETLINK_DIAG=y # CONFIG_NET_L3_MASTER_DEV is not set # CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set +CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y # CONFIG_CGROUP_NET_PRIO is not set CONFIG_CGROUP_NET_CLASSID=y CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y -# CONFIG_BPF_JIT is not set # CONFIG_BPF_STREAM_PARSER is not set CONFIG_NET_FLOW_LIMIT=y @@ -1503,9 +1525,10 @@ CONFIG_RFKILL_INPUT=y # CONFIG_LWTUNNEL is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y # CONFIG_FAILOVER is not set CONFIG_ETHTOOL_NETLINK=y -CONFIG_HAVE_EBPF_JIT=y # # Device Drivers @@ -1528,7 +1551,6 @@ CONFIG_PCIEASPM_DEFAULT=y CONFIG_PCIE_PME=y # CONFIG_PCIE_DPC is not set # CONFIG_PCIE_PTM is not set -# CONFIG_PCIE_BW is not set CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PCI_QUIRKS=y @@ -1588,6 +1610,7 @@ CONFIG_HOTPLUG_PCI=y # CONFIG_PCI_SW_SWITCHTEC is not set # end of PCI switch controller drivers +# CONFIG_CXL_BUS is not set # CONFIG_PCCARD is not set CONFIG_RAPIDIO=y # CONFIG_RAPIDIO_TSI721 is not set @@ -1672,13 +1695,11 @@ CONFIG_CDROM=y # CONFIG_PARIDE is not set # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set # CONFIG_ZRAM is not set -# CONFIG_BLK_DEV_UMEM is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_DRBD is not set # CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SKD is not set # CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 @@ -1720,9 +1741,9 @@ CONFIG_BLK_DEV_NVME=y # CONFIG_HMC6352 is not set # CONFIG_DS1682 is not set # CONFIG_SRAM is not set +# CONFIG_DW_XDATA_PCIE is not set # CONFIG_PCI_ENDPOINT_TEST is not set # CONFIG_XILINX_SDFEC is not set -# CONFIG_PVPANIC is not set # CONFIG_C2PORT is not set # @@ -1751,11 +1772,13 @@ CONFIG_BLK_DEV_NVME=y # CONFIG_VMWARE_VMCI is not set # CONFIG_GENWQE is not set # CONFIG_ECHO is not set +# CONFIG_BCM_VK is not set # CONFIG_MISC_ALCOR_PCI is not set # CONFIG_MISC_RTSX_PCI is not set # CONFIG_MISC_RTSX_USB is not set # CONFIG_HABANA_AI is not set # CONFIG_UACCE is not set +# CONFIG_PVPANIC is not set # end of Misc devices CONFIG_HAVE_IDE=y @@ -1974,12 +1997,6 @@ CONFIG_NET_POLL_CONTROLLER=y CONFIG_VETH=y # CONFIG_NLMON is not set # CONFIG_ARCNET is not set - -# -# Distributed Switch Architecture drivers -# -# end of Distributed Switch Architecture drivers - CONFIG_ETHERNET=y CONFIG_MDIO=y CONFIG_NET_VENDOR_3COM=y @@ -2009,7 +2026,6 @@ CONFIG_NET_VENDOR_ATHEROS=y # CONFIG_ATL1E is not set # CONFIG_ATL1C is not set CONFIG_ALX=y -# CONFIG_NET_VENDOR_AURORA is not set CONFIG_NET_VENDOR_BROADCOM=y # CONFIG_B44 is not set # CONFIG_BCMGENET is not set @@ -2078,6 +2094,7 @@ CONFIG_I40E=y # CONFIG_ICE is not set # CONFIG_FM10K is not set # CONFIG_IGC is not set +CONFIG_NET_VENDOR_MICROSOFT=y # CONFIG_JME is not set CONFIG_NET_VENDOR_MARVELL=y # CONFIG_MVMDIO is not set @@ -2181,6 +2198,7 @@ CONFIG_WIZNET_W5300=y # CONFIG_WIZNET_BUS_INDIRECT is not set CONFIG_WIZNET_BUS_ANY=y CONFIG_NET_VENDOR_XILINX=y +# CONFIG_XILINX_EMACLITE is not set # CONFIG_XILINX_AXI_EMAC is not set # CONFIG_XILINX_LL_TEMAC is not set CONFIG_FDDI=y @@ -2213,11 +2231,13 @@ CONFIG_AMD_PHY=y # CONFIG_LSI_ET1011C_PHY is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set # CONFIG_MICREL_PHY is not set # CONFIG_MICROCHIP_PHY is not set # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_QSEMI_PHY is not set CONFIG_REALTEK_PHY=y @@ -2323,6 +2343,7 @@ CONFIG_WLAN_VENDOR_TI=y CONFIG_WLAN_VENDOR_ZYDAS=y CONFIG_WLAN_VENDOR_QUANTENNA=y # CONFIG_WAN is not set +# CONFIG_WWAN is not set # CONFIG_VMXNET3 is not set # CONFIG_FUJITSU_ES is not set # CONFIG_NETDEVSIM is not set @@ -2489,17 +2510,13 @@ CONFIG_CONSOLE_POLL=y # end of Serial drivers CONFIG_SERIAL_NONSTANDARD=y -# CONFIG_ROCKETPORT is not set -# CONFIG_CYCLADES is not set # CONFIG_MOXA_INTELLIO is not set # CONFIG_MOXA_SMARTIO is not set # CONFIG_SYNCLINK_GT is not set -# CONFIG_ISI is not set # CONFIG_N_HDLC is not set # CONFIG_N_GSM is not set # CONFIG_NOZOMI is not set # CONFIG_NULL_TTY is not set -# CONFIG_TRACE_SINK is not set # CONFIG_SERIAL_DEV_BUS is not set # CONFIG_TTY_PRINTK is not set # CONFIG_PRINTER is not set @@ -2510,7 +2527,6 @@ CONFIG_SERIAL_NONSTANDARD=y # CONFIG_APPLICOM is not set # CONFIG_MWAVE is not set CONFIG_DEVMEM=y -# CONFIG_DEVKMEM is not set # CONFIG_NVRAM is not set # CONFIG_RAW_DRIVER is not set CONFIG_DEVPORT=y @@ -2582,6 +2598,7 @@ CONFIG_I2C_PIIX4=m # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_CP2615 is not set # CONFIG_I2C_PARPORT is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set @@ -2682,9 +2699,11 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_BATTERY_MAX17042 is not set # CONFIG_CHARGER_MAX8903 is not set # CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set # CONFIG_CHARGER_BD99954 is not set CONFIG_HWMON=y # CONFIG_HWMON_DEBUG_CHIP is not set @@ -2708,13 +2727,13 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AHT10 is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_K8TEMP is not set CONFIG_SENSORS_K10TEMP=m # CONFIG_SENSORS_FAM15H_POWER is not set -# CONFIG_SENSORS_AMD_ENERGY is not set # CONFIG_SENSORS_APPLESMC is not set # CONFIG_SENSORS_ASB100 is not set # CONFIG_SENSORS_ASPEED is not set @@ -2765,6 +2784,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_TPS23861 is not set # CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM73 is not set @@ -2789,6 +2809,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_NCT7802 is not set # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set # CONFIG_SENSORS_SBTSI is not set @@ -2861,6 +2882,7 @@ CONFIG_THERMAL_GOV_USER_SPACE=y # Intel thermal drivers # # CONFIG_INTEL_POWERCLAMP is not set +CONFIG_X86_THERMAL_VECTOR=y CONFIG_X86_PKG_TEMP_THERMAL=m # CONFIG_INTEL_SOC_DTS_THERMAL is not set @@ -2871,6 +2893,7 @@ CONFIG_X86_PKG_TEMP_THERMAL=m # end of ACPI INT340X thermal drivers # CONFIG_INTEL_PCH_THERMAL is not set +# CONFIG_INTEL_TCC_COOLING is not set # end of Intel thermal drivers CONFIG_WATCHDOG=y @@ -2995,7 +3018,6 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_ABX500_CORE is not set # CONFIG_MFD_SYSCON is not set # CONFIG_MFD_TI_AM335X_TSCADC is not set # CONFIG_MFD_LP3943 is not set @@ -3021,6 +3043,7 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_WM831X_I2C is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ATC260X_I2C is not set # end of Multifunction device drivers # CONFIG_REGULATOR is not set @@ -3055,12 +3078,10 @@ CONFIG_INTEL_GTT=y CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 # CONFIG_VGA_SWITCHEROO is not set -CONFIG_DRM=y +CONFIG_DRM=m # CONFIG_DRM_DP_AUX_CHARDEV is not set -# CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y +CONFIG_DRM_KMS_HELPER=m # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 @@ -3142,9 +3163,11 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_ETNAVIV is not set # CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_SIMPLEDRM is not set # CONFIG_DRM_VBOXVIDEO is not set +# CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m # # Frame buffer Devices @@ -3153,14 +3176,14 @@ CONFIG_FB_CMDLINE=y CONFIG_FB_NOTIFY=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FB_CFB_FILLRECT=m +CONFIG_FB_CFB_COPYAREA=m +CONFIG_FB_CFB_IMAGEBLIT=m +CONFIG_FB_SYS_FILLRECT=m +CONFIG_FB_SYS_COPYAREA=m +CONFIG_FB_SYS_IMAGEBLIT=m # CONFIG_FB_FOREIGN_ENDIAN is not set -CONFIG_FB_SYS_FOPS=y +CONFIG_FB_SYS_FOPS=m CONFIG_FB_DEFERRED_IO=y # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set @@ -3284,6 +3307,7 @@ CONFIG_HID_CYPRESS=y # CONFIG_HID_ELECOM is not set # CONFIG_HID_ELO is not set CONFIG_HID_EZKEY=y +# CONFIG_HID_FT260 is not set # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set # CONFIG_HID_GLORIOUS is not set @@ -3326,11 +3350,13 @@ CONFIG_HID_MONTEREY=y # CONFIG_HID_PETALYNX is not set # CONFIG_HID_PICOLCD is not set CONFIG_HID_PLANTRONICS=y +# CONFIG_HID_PLAYSTATION is not set # CONFIG_HID_PRIMAX is not set # CONFIG_HID_RETRODE is not set # CONFIG_HID_ROCCAT is not set # CONFIG_HID_SAITEK is not set # CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SEMITEK is not set # CONFIG_HID_SONY is not set # CONFIG_HID_SPEEDLINK is not set # CONFIG_HID_STEAM is not set @@ -3364,7 +3390,7 @@ CONFIG_USB_HIDDEV=y # # I2C HID support # -# CONFIG_I2C_HID is not set +# CONFIG_I2C_HID_ACPI is not set # end of I2C HID support # @@ -3467,7 +3493,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set -# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_CDNS_SUPPORT is not set # CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_DWC3 is not set # CONFIG_USB_DWC2 is not set @@ -3580,6 +3606,7 @@ CONFIG_LEDS_TRIGGERS=y # CONFIG_LEDS_TRIGGER_NETDEV is not set # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_LEDS_TRIGGER_TTY is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y @@ -3675,6 +3702,7 @@ CONFIG_RTC_DRV_CMOS=y # # HID Sensor RTC drivers # +# CONFIG_RTC_DRV_GOLDFISH is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -3688,7 +3716,6 @@ CONFIG_DMA_ACPI=y # CONFIG_INTEL_IDXD is not set # CONFIG_INTEL_IOATDMA is not set # CONFIG_PLX_DMA is not set -# CONFIG_XILINX_ZYNQMP_DPDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_HIDMA is not set CONFIG_DW_DMAC_CORE=y @@ -3697,6 +3724,7 @@ CONFIG_DW_DMAC_PCI=y # CONFIG_DW_EDMA is not set # CONFIG_DW_EDMA_PCIE is not set # CONFIG_SF_PDMA is not set +# CONFIG_INTEL_LDMA is not set # # DMA Clients @@ -3736,6 +3764,7 @@ CONFIG_VHOST_MENU=y # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set # CONFIG_STAGING is not set # CONFIG_X86_PLATFORM_DEVICES is not set CONFIG_PMC_ATOM=y @@ -3755,6 +3784,7 @@ CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_SI544 is not set # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_XILINX_VCU is not set # CONFIG_HWSPINLOCK is not set # @@ -3776,6 +3806,7 @@ CONFIG_IOMMU_SUPPORT=y # # Generic IOMMU Pagetable Support # +CONFIG_IOMMU_IO_PGTABLE=y # end of Generic IOMMU Pagetable Support # CONFIG_IOMMU_DEBUGFS is not set @@ -3845,7 +3876,6 @@ CONFIG_INTEL_IOMMU_FLOPPY_WA=y # # Xilinx SoC drivers # -# CONFIG_XILINX_VCU is not set # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers @@ -3897,9 +3927,9 @@ CONFIG_RAS=y # CONFIG_LIBNVDIMM is not set CONFIG_DAX=y # CONFIG_DEV_DAX is not set -# CONFIG_DEV_DAX_HMEM is not set CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y +# CONFIG_NVMEM_RMEM is not set # # HW tracing support @@ -3984,6 +4014,8 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # # Caches # +CONFIG_NETFS_SUPPORT=y +# CONFIG_NETFS_STATS is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set # CONFIG_FSCACHE_HISTOGRAM is not set @@ -4210,6 +4242,7 @@ CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 # CONFIG_SECURITY_YAMA is not set # CONFIG_SECURITY_SAFESETID is not set # CONFIG_SECURITY_LOCKDOWN_LSM is not set +# CONFIG_SECURITY_LANDLOCK is not set CONFIG_INTEGRITY=y # CONFIG_INTEGRITY_SIGNATURE is not set CONFIG_INTEGRITY_AUDIT=y @@ -4272,6 +4305,7 @@ CONFIG_CRYPTO_AUTHENC=y CONFIG_CRYPTO_RSA=y # CONFIG_CRYPTO_DH is not set # CONFIG_CRYPTO_ECDH is not set +# CONFIG_CRYPTO_ECDSA is not set # CONFIG_CRYPTO_ECRDSA is not set # CONFIG_CRYPTO_SM2 is not set # CONFIG_CRYPTO_CURVE25519 is not set @@ -4333,10 +4367,7 @@ CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y # CONFIG_CRYPTO_SHA1_SSSE3 is not set # CONFIG_CRYPTO_SHA256_SSSE3 is not set @@ -4346,7 +4377,6 @@ CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_SHA3 is not set # CONFIG_CRYPTO_SM3 is not set # CONFIG_CRYPTO_STREEBOG is not set -# CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set @@ -4369,7 +4399,6 @@ CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_DES3_EDE_X86_64 is not set # CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_CHACHA20 is not set # CONFIG_CRYPTO_CHACHA20_X86_64 is not set # CONFIG_CRYPTO_SERPENT is not set @@ -4592,6 +4621,7 @@ CONFIG_FRAME_WARN=2048 CONFIG_SECTION_MISMATCH_WARN_ONLY=y # CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set CONFIG_STACK_VALIDATION=y +# CONFIG_VMLINUX_MAP is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options @@ -4661,6 +4691,8 @@ CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set # end of Memory Debugging CONFIG_DEBUG_SHIRQ=y @@ -4712,6 +4744,11 @@ CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y CONFIG_DEBUG_RWSEMS=y CONFIG_DEBUG_LOCK_ALLOC=y CONFIG_LOCKDEP=y +CONFIG_LOCKDEP_BITS=15 +CONFIG_LOCKDEP_CHAINS_BITS=16 +CONFIG_LOCKDEP_STACK_TRACE_BITS=19 +CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14 +CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12 # CONFIG_DEBUG_LOCKDEP is not set CONFIG_DEBUG_ATOMIC_SLEEP=y # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set @@ -4723,6 +4760,7 @@ CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_TRACE_IRQFLAGS=y CONFIG_TRACE_IRQFLAGS_NMI=y +# CONFIG_DEBUG_IRQFLAGS is not set CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set @@ -4766,16 +4804,15 @@ CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_FENTRY=y +CONFIG_HAVE_OBJTOOL_MCOUNT=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACER_MAX_TRACE=y CONFIG_TRACE_CLOCK=y CONFIG_RING_BUFFER=y CONFIG_EVENT_TRACING=y CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_RING_BUFFER_ALLOW_SWAP=y CONFIG_PREEMPTIRQ_TRACEPOINTS=y CONFIG_TRACING=y -CONFIG_GLOBAL_TRACE_BUF_SIZE=1441792 CONFIG_GENERIC_TRACER=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y @@ -4806,6 +4843,7 @@ CONFIG_DYNAMIC_EVENTS=y CONFIG_PROBE_EVENTS=y # CONFIG_BPF_KPROBE_OVERRIDE is not set CONFIG_FTRACE_MCOUNT_RECORD=y +CONFIG_FTRACE_MCOUNT_USE_CC=y CONFIG_TRACING_MAP=y CONFIG_SYNTH_EVENTS=y CONFIG_HIST_TRIGGERS=y @@ -4867,6 +4905,7 @@ CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set # CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y # end of Kernel Testing and Coverage # end of Kernel hacking From 4a7252c2a89a0724e48fe3696e67dc5619b2b223 Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Thu, 25 Feb 2021 15:54:30 -0500 Subject: [PATCH 0013/2653] x86/configs: CRIU update debug rock defconfig - Update debug config for Checkpoint-Restore (CR) support - Also include necessary options for CR with docker containers. Reviewed-by: Felix Kuehling Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 53 ++++++++++++++++++----------- 1 file changed, 34 insertions(+), 19 deletions(-) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index 4877da183599f..bc2a34666c1d9 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -249,6 +249,7 @@ CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y CONFIG_KALLSYMS_BASE_RELATIVE=y # CONFIG_USERFAULTFD is not set +CONFIG_USERFAULTFD=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y CONFIG_RSEQ=y @@ -1015,6 +1016,11 @@ CONFIG_PACKET_DIAG=y CONFIG_UNIX=y CONFIG_UNIX_SCM=y CONFIG_UNIX_DIAG=y +CONFIG_SMC_DIAG=y +CONFIG_XDP_SOCKETS_DIAG=y +CONFIG_INET_MPTCP_DIAG=y +CONFIG_TIPC_DIAG=y +CONFIG_VSOCKETS_DIAG=y # CONFIG_TLS is not set CONFIG_XFRM=y CONFIG_XFRM_ALGO=y @@ -1052,15 +1058,17 @@ CONFIG_SYN_COOKIES=y # CONFIG_NET_IPVTI is not set # CONFIG_NET_FOU is not set # CONFIG_NET_FOU_IP_TUNNELS is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_INET_UDP_DIAG is not set -# CONFIG_INET_RAW_DIAG is not set -# CONFIG_INET_DIAG_DESTROY is not set +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_INET_DIAG_DESTROY=y CONFIG_TCP_CONG_ADVANCED=y # CONFIG_TCP_CONG_BIC is not set CONFIG_TCP_CONG_CUBIC=y @@ -1085,12 +1093,14 @@ CONFIG_TCP_MD5SIG=y CONFIG_IPV6=y # CONFIG_IPV6_ROUTER_PREF is not set # CONFIG_IPV6_OPTIMISTIC_DAD is not set -CONFIG_INET6_AH=y -CONFIG_INET6_ESP=y -# CONFIG_INET6_ESP_OFFLOAD is not set -# CONFIG_INET6_ESPINTCP is not set -# CONFIG_INET6_IPCOMP is not set -# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET_DCCP_DIAG=m +CONFIG_INET_SCTP_DIAG=m # CONFIG_IPV6_ILA is not set # CONFIG_IPV6_VTI is not set CONFIG_IPV6_SIT=y @@ -1146,8 +1156,13 @@ CONFIG_NF_CT_PROTO_UDPLITE=y # CONFIG_NF_CONNTRACK_SANE is not set # CONFIG_NF_CONNTRACK_SIP is not set # CONFIG_NF_CONNTRACK_TFTP is not set -# CONFIG_NF_CT_NETLINK is not set -# CONFIG_NF_CT_NETLINK_TIMEOUT is not set +CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_SCSI_NETLINK=y +CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_NF_NAT=m CONFIG_NF_NAT_REDIRECT=y CONFIG_NF_NAT_MASQUERADE=y @@ -1992,7 +2007,7 @@ CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_NETPOLL=y CONFIG_NET_POLL_CONTROLLER=y # CONFIG_RIONET is not set -# CONFIG_TUN is not set +CONFIG_TUN=y # CONFIG_TUN_VNET_CROSS_LE is not set CONFIG_VETH=y # CONFIG_NLMON is not set @@ -3990,7 +4005,7 @@ CONFIG_MANDATORY_FILE_LOCKING=y CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y -# CONFIG_FANOTIFY is not set +CONFIG_FANOTIFY=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set From 3b9dfb29170a99c1c2a33540e04029ef6cd46b89 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Wed, 23 Mar 2022 10:30:01 -0400 Subject: [PATCH 0014/2653] rock-dbg_defconfig: Update for 5.16 Also enable ACPI HMAT support, to fix boot crash or amdgpu init failure on ALDEBARAN. v2: - Use make savedefconfig to minimize the changes, skipping redundant configs that are implied by others or have same value as default. Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 4384 +-------------------------- 1 file changed, 3 insertions(+), 4381 deletions(-) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index bc2a34666c1d9..406fdfaceb550 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -1,1176 +1,182 @@ -# -# Automatically generated file; DO NOT EDIT. -# Linux/x86 5.13.0 Kernel Configuration -# -CONFIG_CC_VERSION_TEXT="gcc (Ubuntu 7.5.0-3ubuntu1~18.04) 7.5.0" -CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=70500 -CONFIG_CLANG_VERSION=0 -CONFIG_AS_IS_GNU=y -CONFIG_AS_VERSION=23000 -CONFIG_LD_IS_BFD=y -CONFIG_LD_VERSION=23000 -CONFIG_LLD_VERSION=0 -CONFIG_CC_CAN_LINK=y -CONFIG_CC_CAN_LINK_STATIC=y -CONFIG_CC_HAS_ASM_GOTO=y -CONFIG_CC_HAS_ASM_INLINE=y -CONFIG_IRQ_WORK=y -CONFIG_BUILDTIME_TABLE_SORT=y -CONFIG_THREAD_INFO_IN_TASK=y - -# -# General setup -# -CONFIG_INIT_ENV_ARG_LIMIT=32 -# CONFIG_COMPILE_TEST is not set CONFIG_LOCALVERSION="-kfd" # CONFIG_LOCALVERSION_AUTO is not set -CONFIG_BUILD_SALT="" -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -CONFIG_HAVE_KERNEL_XZ=y -CONFIG_HAVE_KERNEL_LZO=y -CONFIG_HAVE_KERNEL_LZ4=y -CONFIG_HAVE_KERNEL_ZSTD=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_BZIP2 is not set -# CONFIG_KERNEL_LZMA is not set -# CONFIG_KERNEL_XZ is not set -# CONFIG_KERNEL_LZO is not set -# CONFIG_KERNEL_LZ4 is not set -# CONFIG_KERNEL_ZSTD is not set -CONFIG_DEFAULT_INIT="" -CONFIG_DEFAULT_HOSTNAME="(none)" -CONFIG_SWAP=y CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y -CONFIG_POSIX_MQUEUE_SYSCTL=y -# CONFIG_WATCH_QUEUE is not set -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_USELIB=y CONFIG_AUDIT=y -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -CONFIG_AUDITSYSCALL=y - -# -# IRQ subsystem -# -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_PENDING_IRQ=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_IRQ_MSI_IOMMU=y -CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y -CONFIG_GENERIC_IRQ_RESERVATION_MODE=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_SPARSE_IRQ=y -# CONFIG_GENERIC_IRQ_DEBUGFS is not set -# end of IRQ subsystem - -CONFIG_CLOCKSOURCE_WATCHDOG=y -CONFIG_ARCH_CLOCKSOURCE_INIT=y -CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y - -# -# Timers subsystem -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ_COMMON=y -# CONFIG_HZ_PERIODIC is not set -CONFIG_NO_HZ_IDLE=y -# CONFIG_NO_HZ_FULL is not set CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y -# end of Timers subsystem - -CONFIG_BPF=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y - -# -# BPF subsystem -# CONFIG_BPF_SYSCALL=y -# CONFIG_BPF_JIT is not set # CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set -# CONFIG_BPF_PRELOAD is not set -# end of BPF subsystem - -# CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y -# CONFIG_PREEMPT is not set -CONFIG_PREEMPT_COUNT=y - -# -# CPU/Task time and stats accounting -# -CONFIG_TICK_CPU_ACCOUNTING=y -# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set -# CONFIG_IRQ_TIME_ACCOUNTING is not set CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_TASKSTATS=y CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y -# CONFIG_PSI is not set -# end of CPU/Task time and stats accounting - # CONFIG_CPU_ISOLATION is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_RCU_EXPERT is not set -CONFIG_SRCU=y -CONFIG_TREE_SRCU=y -CONFIG_TASKS_RCU_GENERIC=y -CONFIG_TASKS_RUDE_RCU=y -CONFIG_TASKS_TRACE_RCU=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_RCU_NEED_SEGCBLIST=y -# end of RCU Subsystem - -CONFIG_BUILD_BIN2C=y -# CONFIG_IKCONFIG is not set -# CONFIG_IKHEADERS is not set CONFIG_LOG_BUF_SHIFT=18 -CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 -CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 -CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y - -# -# Scheduler features -# -# CONFIG_UCLAMP_TASK is not set -# end of Scheduler features - -CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y -CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y -CONFIG_CC_HAS_INT128=y -CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_NUMA_BALANCING=y -CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y -CONFIG_CGROUPS=y -CONFIG_PAGE_COUNTER=y CONFIG_MEMCG=y -CONFIG_MEMCG_SWAP=y -CONFIG_MEMCG_KMEM=y CONFIG_BLK_CGROUP=y -CONFIG_CGROUP_WRITEBACK=y -CONFIG_CGROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y -# CONFIG_RT_GROUP_SCHED is not set CONFIG_CGROUP_PIDS=y -# CONFIG_CGROUP_RDMA is not set CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_HUGETLB=y CONFIG_CPUSETS=y -CONFIG_PROC_PID_CPUSET=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y -# CONFIG_CGROUP_MISC is not set -# CONFIG_CGROUP_DEBUG is not set -CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y -CONFIG_UTS_NS=y -CONFIG_TIME_NS=y -CONFIG_IPC_NS=y CONFIG_USER_NS=y -CONFIG_PID_NS=y -CONFIG_NET_NS=y CONFIG_CHECKPOINT_RESTORE=y CONFIG_SCHED_AUTOGROUP=y -# CONFIG_SYSFS_DEPRECATED is not set -CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -CONFIG_RD_BZIP2=y -CONFIG_RD_LZMA=y -CONFIG_RD_XZ=y -CONFIG_RD_LZO=y -CONFIG_RD_LZ4=y -CONFIG_RD_ZSTD=y -# CONFIG_BOOT_CONFIG is not set -CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_LD_ORPHAN_WARN=y -CONFIG_SYSCTL=y -CONFIG_HAVE_UID16=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_HAVE_PCSPKR_PLATFORM=y CONFIG_EXPERT=y -CONFIG_UID16=y -CONFIG_MULTIUSER=y -CONFIG_SGETMASK_SYSCALL=y -CONFIG_SYSFS_SYSCALL=y -CONFIG_FHANDLE=y -CONFIG_POSIX_TIMERS=y -CONFIG_PRINTK=y -CONFIG_PRINTK_NMI=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_FUTEX_PI=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y -CONFIG_IO_URING=y -CONFIG_ADVISE_SYSCALLS=y -CONFIG_MEMBARRIER=y -CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_ALL=y -CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y -CONFIG_KALLSYMS_BASE_RELATIVE=y -# CONFIG_USERFAULTFD is not set CONFIG_USERFAULTFD=y -CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y -CONFIG_KCMP=y -CONFIG_RSEQ=y -# CONFIG_DEBUG_RSEQ is not set -# CONFIG_EMBEDDED is not set -CONFIG_HAVE_PERF_EVENTS=y -# CONFIG_PC104 is not set - -# -# Kernel Performance Events And Counters -# -CONFIG_PERF_EVENTS=y -# CONFIG_DEBUG_PERF_USE_VMALLOC is not set -# end of Kernel Performance Events And Counters - -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLUB_DEBUG=y # CONFIG_COMPAT_BRK is not set -# CONFIG_SLAB is not set -CONFIG_SLUB=y -# CONFIG_SLOB is not set -CONFIG_SLAB_MERGE_DEFAULT=y -# CONFIG_SLAB_FREELIST_RANDOM is not set -# CONFIG_SLAB_FREELIST_HARDENED is not set -# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set -CONFIG_SLUB_CPU_PARTIAL=y -CONFIG_SYSTEM_DATA_VERIFICATION=y CONFIG_PROFILING=y -CONFIG_TRACEPOINTS=y -# end of General setup - -CONFIG_64BIT=y -CONFIG_X86_64=y -CONFIG_X86=y -CONFIG_INSTRUCTION_DECODER=y -CONFIG_OUTPUT_FORMAT="elf64-x86-64" -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_MMU=y -CONFIG_ARCH_MMAP_RND_BITS_MIN=28 -CONFIG_ARCH_MMAP_RND_BITS_MAX=32 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 -CONFIG_GENERIC_ISA_DMA=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ARCH_HAS_CPU_RELAX=y -CONFIG_ARCH_HAS_FILTER_PGPROT=y -CONFIG_HAVE_SETUP_PER_CPU_AREA=y -CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y -CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ZONE_DMA32=y -CONFIG_AUDIT_ARCH=y -CONFIG_HAVE_INTEL_TXT=y -CONFIG_X86_64_SMP=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_PGTABLE_LEVELS=4 -CONFIG_CC_HAS_SANE_STACKPROTECTOR=y - -# -# Processor type and features -# -CONFIG_ZONE_DMA=y CONFIG_SMP=y -CONFIG_X86_FEATURE_NAMES=y -# CONFIG_X86_X2APIC is not set -CONFIG_X86_MPPARSE=y -# CONFIG_GOLDFISH is not set # CONFIG_RETPOLINE is not set -# CONFIG_X86_CPU_RESCTRL is not set -CONFIG_X86_EXTENDED_PLATFORM=y -# CONFIG_X86_VSMP is not set -# CONFIG_X86_GOLDFISH is not set CONFIG_X86_INTEL_LPSS=y -# CONFIG_X86_AMD_PLATFORM_DEVICE is not set -CONFIG_IOSF_MBI=y CONFIG_IOSF_MBI_DEBUG=y -CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y -CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_HYPERVISOR_GUEST=y CONFIG_PARAVIRT=y -# CONFIG_PARAVIRT_DEBUG is not set CONFIG_PARAVIRT_SPINLOCKS=y -CONFIG_X86_HV_CALLBACK_VECTOR=y -# CONFIG_XEN is not set -CONFIG_KVM_GUEST=y -CONFIG_ARCH_CPUIDLE_HALTPOLL=y -# CONFIG_PVH is not set -# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set -CONFIG_PARAVIRT_CLOCK=y -# CONFIG_JAILHOUSE_GUEST is not set -# CONFIG_ACRN_GUEST is not set -# CONFIG_MK8 is not set -# CONFIG_MPSC is not set -# CONFIG_MCORE2 is not set -# CONFIG_MATOM is not set -CONFIG_GENERIC_CPU=y -CONFIG_X86_INTERNODE_CACHE_SHIFT=6 -CONFIG_X86_L1_CACHE_SHIFT=6 -CONFIG_X86_TSC=y -CONFIG_X86_CMPXCHG64=y -CONFIG_X86_CMOV=y -CONFIG_X86_MINIMUM_CPU_FAMILY=64 -CONFIG_X86_DEBUGCTLMSR=y -CONFIG_IA32_FEAT_CTL=y -CONFIG_X86_VMX_FEATURE_NAMES=y CONFIG_PROCESSOR_SELECT=y -CONFIG_CPU_SUP_INTEL=y -CONFIG_CPU_SUP_AMD=y -CONFIG_CPU_SUP_HYGON=y -CONFIG_CPU_SUP_CENTAUR=y -CONFIG_CPU_SUP_ZHAOXIN=y -CONFIG_HPET_TIMER=y -CONFIG_HPET_EMULATE_RTC=y -CONFIG_DMI=y CONFIG_GART_IOMMU=y -# CONFIG_MAXSMP is not set -CONFIG_NR_CPUS_RANGE_BEGIN=2 -CONFIG_NR_CPUS_RANGE_END=512 -CONFIG_NR_CPUS_DEFAULT=64 CONFIG_NR_CPUS=256 -CONFIG_SCHED_SMT=y -CONFIG_SCHED_MC=y -CONFIG_SCHED_MC_PRIO=y -CONFIG_X86_LOCAL_APIC=y -CONFIG_X86_IO_APIC=y CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y -CONFIG_X86_MCE=y -# CONFIG_X86_MCELOG_LEGACY is not set -CONFIG_X86_MCE_INTEL=y -CONFIG_X86_MCE_AMD=y -CONFIG_X86_MCE_THRESHOLD=y -# CONFIG_X86_MCE_INJECT is not set - -# -# Performance monitoring -# -CONFIG_PERF_EVENTS_INTEL_UNCORE=y -CONFIG_PERF_EVENTS_INTEL_RAPL=y -CONFIG_PERF_EVENTS_INTEL_CSTATE=y -# CONFIG_PERF_EVENTS_AMD_POWER is not set -# end of Performance monitoring - -CONFIG_X86_16BIT=y -CONFIG_X86_ESPFIX64=y -CONFIG_X86_VSYSCALL_EMULATION=y -CONFIG_X86_IOPL_IOPERM=y CONFIG_I8K=m -CONFIG_MICROCODE=y -CONFIG_MICROCODE_INTEL=y CONFIG_MICROCODE_AMD=y CONFIG_MICROCODE_OLD_INTERFACE=y CONFIG_X86_MSR=m CONFIG_X86_CPUID=m # CONFIG_X86_5LEVEL is not set -CONFIG_X86_DIRECT_GBPAGES=y -# CONFIG_X86_CPA_STATISTICS is not set -# CONFIG_AMD_MEM_ENCRYPT is not set CONFIG_NUMA=y -CONFIG_AMD_NUMA=y -CONFIG_X86_64_ACPI_NUMA=y -# CONFIG_NUMA_EMU is not set -CONFIG_NODES_SHIFT=6 -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_MEMORY_PROBE=y -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -# CONFIG_X86_PMEM_LEGACY is not set CONFIG_X86_CHECK_BIOS_CORRUPTION=y -CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y -CONFIG_X86_RESERVE_LOW=64 -CONFIG_MTRR=y -CONFIG_MTRR_SANITIZER=y CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=1 -CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1 -CONFIG_X86_PAT=y -CONFIG_ARCH_USES_PG_UNCACHED=y -CONFIG_ARCH_RANDOM=y -CONFIG_X86_SMAP=y -CONFIG_X86_UMIP=y -CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y -CONFIG_X86_INTEL_TSX_MODE_OFF=y -# CONFIG_X86_INTEL_TSX_MODE_ON is not set -# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set -# CONFIG_X86_SGX is not set CONFIG_EFI=y CONFIG_EFI_STUB=y CONFIG_EFI_MIXED=y -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_300 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=250 -CONFIG_SCHED_HRTICK=y CONFIG_KEXEC=y CONFIG_KEXEC_FILE=y -CONFIG_ARCH_HAS_KEXEC_PURGATORY=y -# CONFIG_KEXEC_SIG is not set CONFIG_CRASH_DUMP=y CONFIG_KEXEC_JUMP=y -CONFIG_PHYSICAL_START=0x1000000 -CONFIG_RELOCATABLE=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_X86_NEED_RELOCS=y CONFIG_PHYSICAL_ALIGN=0x1000000 -CONFIG_DYNAMIC_MEMORY_LAYOUT=y -CONFIG_RANDOMIZE_MEMORY=y -CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa -CONFIG_HOTPLUG_CPU=y -# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set -# CONFIG_DEBUG_HOTPLUG_CPU0 is not set -# CONFIG_COMPAT_VDSO is not set CONFIG_LEGACY_VSYSCALL_EMULATE=y -# CONFIG_LEGACY_VSYSCALL_XONLY is not set -# CONFIG_LEGACY_VSYSCALL_NONE is not set -# CONFIG_CMDLINE_BOOL is not set -CONFIG_MODIFY_LDT_SYSCALL=y -CONFIG_HAVE_LIVEPATCH=y -# CONFIG_LIVEPATCH is not set -# end of Processor type and features - -CONFIG_ARCH_HAS_ADD_PAGES=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_USE_PERCPU_NUMA_NODE_ID=y - -# -# Power management and ACPI options -# -CONFIG_ARCH_HIBERNATION_HEADER=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -# CONFIG_SUSPEND_SKIP_SYNC is not set -CONFIG_HIBERNATE_CALLBACKS=y CONFIG_HIBERNATION=y -CONFIG_HIBERNATION_SNAPSHOT_DEV=y -CONFIG_PM_STD_PARTITION="" -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -# CONFIG_PM_AUTOSLEEP is not set CONFIG_PM_WAKELOCKS=y -CONFIG_PM_WAKELOCKS_LIMIT=100 -CONFIG_PM_WAKELOCKS_GC=y -CONFIG_PM=y CONFIG_PM_DEBUG=y CONFIG_PM_ADVANCED_DEBUG=y -# CONFIG_PM_TEST_SUSPEND is not set -CONFIG_PM_SLEEP_DEBUG=y -# CONFIG_DPM_WATCHDOG is not set -CONFIG_PM_TRACE=y CONFIG_PM_TRACE_RTC=y -CONFIG_PM_CLK=y CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -# CONFIG_ENERGY_MODEL is not set -CONFIG_ARCH_SUPPORTS_ACPI=y -CONFIG_ACPI=y -CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y -CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y -CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y -# CONFIG_ACPI_DEBUGGER is not set -CONFIG_ACPI_SPCR_TABLE=y -# CONFIG_ACPI_FPDT is not set -CONFIG_ACPI_LPIT=y -CONFIG_ACPI_SLEEP=y -CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y CONFIG_ACPI_EC_DEBUGFS=m -CONFIG_ACPI_AC=y -CONFIG_ACPI_BATTERY=y -CONFIG_ACPI_BUTTON=y CONFIG_ACPI_VIDEO=m -CONFIG_ACPI_FAN=y -# CONFIG_ACPI_TAD is not set CONFIG_ACPI_DOCK=y -CONFIG_ACPI_CPU_FREQ_PSS=y -CONFIG_ACPI_PROCESSOR_CSTATE=y -CONFIG_ACPI_PROCESSOR_IDLE=y -CONFIG_ACPI_CPPC_LIB=y -CONFIG_ACPI_PROCESSOR=y -CONFIG_ACPI_HOTPLUG_CPU=y CONFIG_ACPI_PROCESSOR_AGGREGATOR=m -CONFIG_ACPI_THERMAL=y -CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y -CONFIG_ACPI_TABLE_UPGRADE=y -# CONFIG_ACPI_DEBUG is not set CONFIG_ACPI_PCI_SLOT=y -CONFIG_ACPI_CONTAINER=y CONFIG_ACPI_HOTPLUG_MEMORY=y -CONFIG_ACPI_HOTPLUG_IOAPIC=y CONFIG_ACPI_SBS=m -CONFIG_ACPI_HED=y -# CONFIG_ACPI_CUSTOM_METHOD is not set CONFIG_ACPI_BGRT=y -# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set -# CONFIG_ACPI_NFIT is not set -CONFIG_ACPI_NUMA=y -# CONFIG_ACPI_HMAT is not set -CONFIG_HAVE_ACPI_APEI=y -CONFIG_HAVE_ACPI_APEI_NMI=y +CONFIG_ACPI_HMAT=y CONFIG_ACPI_APEI=y CONFIG_ACPI_APEI_GHES=y CONFIG_ACPI_APEI_PCIEAER=y CONFIG_ACPI_APEI_MEMORY_FAILURE=y CONFIG_ACPI_APEI_EINJ=m -# CONFIG_ACPI_APEI_ERST_DEBUG is not set -# CONFIG_ACPI_DPTF is not set -# CONFIG_ACPI_CONFIGFS is not set -# CONFIG_PMIC_OPREGION is not set -CONFIG_X86_PM_TIMER=y - -# -# CPU Frequency scaling -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y - -# -# CPU frequency scaling drivers -# -CONFIG_X86_INTEL_PSTATE=y -# CONFIG_X86_PCC_CPUFREQ is not set CONFIG_X86_ACPI_CPUFREQ=y # CONFIG_X86_ACPI_CPUFREQ_CPB is not set -# CONFIG_X86_POWERNOW_K8 is not set -# CONFIG_X86_AMD_FREQ_SENSITIVITY is not set -# CONFIG_X86_SPEEDSTEP_CENTRINO is not set -# CONFIG_X86_P4_CLOCKMOD is not set - -# -# shared options -# -# end of CPU Frequency scaling - -# -# CPU Idle -# -CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -# CONFIG_CPU_IDLE_GOV_TEO is not set -# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set -CONFIG_HALTPOLL_CPUIDLE=y -# end of CPU Idle - -# CONFIG_INTEL_IDLE is not set -# end of Power management and ACPI options - -# -# Bus options (PCI etc.) -# -CONFIG_PCI_DIRECT=y -CONFIG_PCI_MMCONFIG=y -CONFIG_MMCONF_FAM10H=y -# CONFIG_PCI_CNB20LE_QUIRK is not set -# CONFIG_ISA_BUS is not set -CONFIG_ISA_DMA_API=y -CONFIG_AMD_NB=y -# CONFIG_X86_SYSFB is not set -# end of Bus options (PCI etc.) - -# -# Binary Emulations -# CONFIG_IA32_EMULATION=y -# CONFIG_X86_X32 is not set -CONFIG_COMPAT_32=y -CONFIG_COMPAT=y -CONFIG_COMPAT_FOR_U64_ALIGNMENT=y -CONFIG_SYSVIPC_COMPAT=y -# end of Binary Emulations - -# -# Firmware Drivers -# -# CONFIG_EDD is not set -CONFIG_FIRMWARE_MEMMAP=y -CONFIG_DMIID=y -# CONFIG_DMI_SYSFS is not set -CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y -# CONFIG_FW_CFG_SYSFS is not set -# CONFIG_GOOGLE_FIRMWARE is not set - -# -# EFI (Extensible Firmware Interface) Support -# -CONFIG_EFI_VARS=y -CONFIG_EFI_ESRT=y -CONFIG_EFI_VARS_PSTORE=y -# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set -CONFIG_EFI_RUNTIME_MAP=y -# CONFIG_EFI_FAKE_MEMMAP is not set -CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y -# CONFIG_EFI_BOOTLOADER_CONTROL is not set -# CONFIG_EFI_CAPSULE_LOADER is not set -# CONFIG_EFI_TEST is not set -# CONFIG_APPLE_PROPERTIES is not set -# CONFIG_RESET_ATTACK_MITIGATION is not set -# CONFIG_EFI_RCI2_TABLE is not set -# CONFIG_EFI_DISABLE_PCI_DMA is not set -# end of EFI (Extensible Firmware Interface) Support - -CONFIG_UEFI_CPER=y -CONFIG_UEFI_CPER_X86=y -CONFIG_EFI_EARLYCON=y -CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y - -# -# Tegra firmware driver -# -# end of Tegra firmware driver -# end of Firmware Drivers - -CONFIG_HAVE_KVM=y -CONFIG_VIRTUALIZATION=y -# CONFIG_KVM is not set -CONFIG_AS_AVX512=y -CONFIG_AS_SHA1_NI=y -CONFIG_AS_SHA256_NI=y - -# -# General architecture-dependent options -# -CONFIG_CRASH_CORE=y -CONFIG_KEXEC_CORE=y -CONFIG_HOTPLUG_SMT=y -CONFIG_GENERIC_ENTRY=y -CONFIG_KPROBES=y CONFIG_JUMP_LABEL=y -# CONFIG_STATIC_KEYS_SELFTEST is not set -# CONFIG_STATIC_CALL_SELFTEST is not set -CONFIG_OPTPROBES=y -CONFIG_KPROBES_ON_FTRACE=y -CONFIG_UPROBES=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_KRETPROBES=y -CONFIG_HAVE_IOREMAP_PROT=y -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_KPROBES_ON_FTRACE=y -CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y -CONFIG_HAVE_NMI=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_ARCH_HAS_SET_DIRECT_MAP=y -CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y -CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y -CONFIG_HAVE_ASM_MODVERSIONS=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_RSEQ=y -CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y -CONFIG_HAVE_HW_BREAKPOINT=y -CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y -CONFIG_HAVE_USER_RETURN_NOTIFIER=y -CONFIG_HAVE_PERF_EVENTS_NMI=y -CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y -CONFIG_MMU_GATHER_TABLE_FREE=y -CONFIG_MMU_GATHER_RCU_TABLE_FREE=y -CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y -CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y -CONFIG_HAVE_CMPXCHG_LOCAL=y -CONFIG_HAVE_CMPXCHG_DOUBLE=y -CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y -CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y -CONFIG_HAVE_ARCH_SECCOMP=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_SECCOMP=y -CONFIG_SECCOMP_FILTER=y -# CONFIG_SECCOMP_CACHE_DEBUG is not set -CONFIG_HAVE_ARCH_STACKLEAK=y -CONFIG_HAVE_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR_STRONG=y -CONFIG_ARCH_SUPPORTS_LTO_CLANG=y -CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y -CONFIG_LTO_NONE=y -CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_CONTEXT_TRACKING_OFFSTACK=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_MOVE_PUD=y -CONFIG_HAVE_MOVE_PMD=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y -CONFIG_HAVE_ARCH_HUGE_VMAP=y -CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -CONFIG_HAVE_ARCH_SOFT_DIRTY=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y -CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_HAVE_ARCH_MMAP_RND_BITS=y -CONFIG_HAVE_EXIT_THREAD=y -CONFIG_ARCH_MMAP_RND_BITS=28 -CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y -CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 -CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y -CONFIG_HAVE_STACK_VALIDATION=y -CONFIG_HAVE_RELIABLE_STACKTRACE=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_COMPAT_OLD_SIGACTION=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_HAVE_ARCH_VMAP_STACK=y -CONFIG_VMAP_STACK=y -CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y -# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_STRICT_MODULE_RWX=y -CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y -CONFIG_ARCH_USE_MEMREMAP_PROT=y -# CONFIG_LOCK_EVENT_COUNTS is not set -CONFIG_ARCH_HAS_MEM_ENCRYPT=y -CONFIG_HAVE_STATIC_CALL=y -CONFIG_HAVE_STATIC_CALL_INLINE=y -CONFIG_HAVE_PREEMPT_DYNAMIC=y -CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y -CONFIG_ARCH_HAS_ELFCORE_COMPAT=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -# end of GCOV-based kernel profiling - -CONFIG_HAVE_GCC_PLUGINS=y -# end of General architecture-dependent options - -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULE_SIG_FORMAT=y CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y -CONFIG_ASM_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_MODULE_SIG=y -# CONFIG_MODULE_SIG_FORCE is not set -CONFIG_MODULE_SIG_ALL=y -# CONFIG_MODULE_SIG_SHA1 is not set -# CONFIG_MODULE_SIG_SHA224 is not set -# CONFIG_MODULE_SIG_SHA256 is not set -# CONFIG_MODULE_SIG_SHA384 is not set CONFIG_MODULE_SIG_SHA512=y -CONFIG_MODULE_SIG_HASH="sha512" -CONFIG_MODULE_COMPRESS_NONE=y -# CONFIG_MODULE_COMPRESS_GZIP is not set -# CONFIG_MODULE_COMPRESS_XZ is not set -# CONFIG_MODULE_COMPRESS_ZSTD is not set -# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -CONFIG_MODPROBE_PATH="/sbin/modprobe" -# CONFIG_TRIM_UNUSED_KSYMS is not set -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_BLOCK=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BLK_CGROUP_RWSTAT=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_BLK_DEV_INTEGRITY_T10=y -# CONFIG_BLK_DEV_ZONED is not set CONFIG_BLK_DEV_THROTTLING=y -# CONFIG_BLK_DEV_THROTTLING_LOW is not set -CONFIG_BLK_CMDLINE_PARSER=y -# CONFIG_BLK_WBT is not set -# CONFIG_BLK_CGROUP_IOLATENCY is not set -# CONFIG_BLK_CGROUP_IOCOST is not set -CONFIG_BLK_DEBUG_FS=y -# CONFIG_BLK_SED_OPAL is not set -# CONFIG_BLK_INLINE_ENCRYPTION is not set - -# -# Partition Types -# CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_AIX_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -CONFIG_EFI_PARTITION=y -# CONFIG_SYSV68_PARTITION is not set -# CONFIG_CMDLINE_PARTITION is not set -# end of Partition Types - -CONFIG_BLOCK_COMPAT=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y - -# -# IO Schedulers -# -CONFIG_MQ_IOSCHED_DEADLINE=y -CONFIG_MQ_IOSCHED_KYBER=y -# CONFIG_IOSCHED_BFQ is not set -# end of IO Schedulers - -CONFIG_ASN1=y -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_ARCH_USE_QUEUED_RWLOCKS=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y -CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y -CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y -CONFIG_FREEZER=y - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -CONFIG_COMPAT_BINFMT_ELF=y -CONFIG_ELFCORE=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_BINFMT_SCRIPT=y CONFIG_BINFMT_MISC=y -CONFIG_COREDUMP=y -# end of Executable file formats - -# -# Memory Management options -# -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM=y -CONFIG_NEED_MULTIPLE_NODES=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_HAVE_FAST_GUP=y -CONFIG_NUMA_KEEP_MEMINFO=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_HAVE_BOOTMEM_INFO_NODE=y -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_MEMORY_HOTPLUG=y -CONFIG_MEMORY_HOTPLUG_SPARSE=y -# CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set -CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_MEMORY_HOTREMOVE=y -CONFIG_MHP_MEMMAP_ON_MEMORY=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y -CONFIG_COMPACTION=y -# CONFIG_PAGE_REPORTING is not set -CONFIG_MIGRATION=y -CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y -CONFIG_ARCH_ENABLE_THP_MIGRATION=y -CONFIG_CONTIG_ALLOC=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_VIRT_TO_BUS=y -CONFIG_MMU_NOTIFIER=y CONFIG_KSM=y CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 -CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y CONFIG_MEMORY_FAILURE=y CONFIG_HWPOISON_INJECT=m CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y -# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_THP_SWAP=y CONFIG_CLEANCACHE=y CONFIG_FRONTSWAP=y CONFIG_CMA=y -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -# CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 CONFIG_MEM_SOFT_DIRTY=y CONFIG_ZSWAP=y -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set -CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set -CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo" -CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y -# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set -# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set -CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud" -# CONFIG_ZSWAP_DEFAULT_ON is not set -CONFIG_ZPOOL=y -CONFIG_ZBUD=y -# CONFIG_Z3FOLD is not set CONFIG_ZSMALLOC=y -# CONFIG_ZSMALLOC_STAT is not set -CONFIG_GENERIC_EARLY_IOREMAP=y -# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set -# CONFIG_IDLE_PAGE_TRACKING is not set -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ZONE_DEVICE=y -CONFIG_DEV_PAGEMAP_OPS=y -CONFIG_HMM_MIRROR=y CONFIG_DEVICE_PRIVATE=y -CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y -CONFIG_ARCH_HAS_PKEYS=y -# CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_TEST is not set -# CONFIG_READ_ONLY_THP_FOR_FS is not set -CONFIG_ARCH_HAS_PTE_SPECIAL=y -# end of Memory Management options - CONFIG_NET=y -CONFIG_NET_INGRESS=y -CONFIG_SKB_EXTENSIONS=y - -# -# Networking options -# CONFIG_PACKET=y CONFIG_PACKET_DIAG=y CONFIG_UNIX=y -CONFIG_UNIX_SCM=y CONFIG_UNIX_DIAG=y -CONFIG_SMC_DIAG=y -CONFIG_XDP_SOCKETS_DIAG=y -CONFIG_INET_MPTCP_DIAG=y -CONFIG_TIPC_DIAG=y -CONFIG_VSOCKETS_DIAG=y -# CONFIG_TLS is not set -CONFIG_XFRM=y -CONFIG_XFRM_ALGO=y CONFIG_XFRM_USER=y -# CONFIG_XFRM_USER_COMPAT is not set -# CONFIG_XFRM_INTERFACE is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -CONFIG_XFRM_AH=y -CONFIG_XFRM_ESP=y -# CONFIG_NET_KEY is not set -# CONFIG_XDP_SOCKETS is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y -# CONFIG_IP_FIB_TRIE_STATS is not set CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_ROUTE_CLASSID=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE_DEMUX is not set -CONFIG_NET_IP_TUNNEL=y -CONFIG_IP_MROUTE_COMMON=y CONFIG_IP_MROUTE=y -# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y -CONFIG_SYN_COOKIES=y -# CONFIG_NET_IPVTI is not set -# CONFIG_NET_FOU is not set -# CONFIG_NET_FOU_IP_TUNNELS is not set CONFIG_INET_AH=m CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m CONFIG_INET_ESP_OFFLOAD=m -CONFIG_INET_TUNNEL=m -CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_IPCOMP=m CONFIG_INET_DIAG=m -CONFIG_INET_TCP_DIAG=m CONFIG_INET_UDP_DIAG=m CONFIG_INET_RAW_DIAG=m CONFIG_INET_DIAG_DESTROY=y CONFIG_TCP_CONG_ADVANCED=y # CONFIG_TCP_CONG_BIC is not set -CONFIG_TCP_CONG_CUBIC=y # CONFIG_TCP_CONG_WESTWOOD is not set # CONFIG_TCP_CONG_HTCP is not set -# CONFIG_TCP_CONG_HSTCP is not set -# CONFIG_TCP_CONG_HYBLA is not set -# CONFIG_TCP_CONG_VEGAS is not set -# CONFIG_TCP_CONG_NV is not set -# CONFIG_TCP_CONG_SCALABLE is not set -# CONFIG_TCP_CONG_LP is not set -# CONFIG_TCP_CONG_VENO is not set -# CONFIG_TCP_CONG_YEAH is not set -# CONFIG_TCP_CONG_ILLINOIS is not set -# CONFIG_TCP_CONG_DCTCP is not set -# CONFIG_TCP_CONG_CDG is not set -# CONFIG_TCP_CONG_BBR is not set -CONFIG_DEFAULT_CUBIC=y -# CONFIG_DEFAULT_RENO is not set -CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_TCP_MD5SIG=y -CONFIG_IPV6=y -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_ESP_OFFLOAD=m CONFIG_INET6_IPCOMP=m CONFIG_IPV6_MIP6=m -CONFIG_INET6_XFRM_TUNNEL=m -CONFIG_INET_DCCP_DIAG=m -CONFIG_INET_SCTP_DIAG=m -# CONFIG_IPV6_ILA is not set -# CONFIG_IPV6_VTI is not set -CONFIG_IPV6_SIT=y -# CONFIG_IPV6_SIT_6RD is not set -CONFIG_IPV6_NDISC_NODETYPE=y -# CONFIG_IPV6_TUNNEL is not set -# CONFIG_IPV6_MULTIPLE_TABLES is not set -# CONFIG_IPV6_MROUTE is not set -# CONFIG_IPV6_SEG6_LWTUNNEL is not set -# CONFIG_IPV6_SEG6_HMAC is not set -# CONFIG_IPV6_RPL_LWTUNNEL is not set CONFIG_NETLABEL=y -# CONFIG_MPTCP is not set -CONFIG_NETWORK_SECMARK=y -CONFIG_NET_PTP_CLASSIFY=y -# CONFIG_NETWORK_PHY_TIMESTAMPING is not set CONFIG_NETFILTER=y -CONFIG_NETFILTER_ADVANCED=y CONFIG_BRIDGE_NETFILTER=m - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_INGRESS=y -CONFIG_NETFILTER_NETLINK=m -CONFIG_NETFILTER_FAMILY_BRIDGE=y -CONFIG_NETFILTER_FAMILY_ARP=y -CONFIG_NETFILTER_NETLINK_ACCT=m -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NETFILTER_NETLINK_OSF=m CONFIG_NF_CONNTRACK=m -CONFIG_NF_LOG_SYSLOG=m -CONFIG_NETFILTER_CONNCOUNT=m -CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_ZONES=y # CONFIG_NF_CONNTRACK_PROCFS is not set CONFIG_NF_CONNTRACK_EVENTS=y CONFIG_NF_CONNTRACK_TIMEOUT=y CONFIG_NF_CONNTRACK_TIMESTAMP=y -CONFIG_NF_CONNTRACK_LABELS=y -CONFIG_NF_CT_PROTO_DCCP=y -CONFIG_NF_CT_PROTO_SCTP=y -CONFIG_NF_CT_PROTO_UDPLITE=y -# CONFIG_NF_CONNTRACK_AMANDA is not set -# CONFIG_NF_CONNTRACK_FTP is not set -# CONFIG_NF_CONNTRACK_H323 is not set -# CONFIG_NF_CONNTRACK_IRC is not set -# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set -# CONFIG_NF_CONNTRACK_SNMP is not set -# CONFIG_NF_CONNTRACK_PPTP is not set -# CONFIG_NF_CONNTRACK_SANE is not set -# CONFIG_NF_CONNTRACK_SIP is not set -# CONFIG_NF_CONNTRACK_TFTP is not set -CONFIG_COMPAT_NETLINK_MESSAGES=y CONFIG_NF_CT_NETLINK=m CONFIG_NF_CT_NETLINK_TIMEOUT=m CONFIG_NF_CT_NETLINK_HELPER=m CONFIG_NETFILTER_NETLINK_GLUE_CT=y -CONFIG_SCSI_NETLINK=y -CONFIG_QUOTA_NETLINK_INTERFACE=y -CONFIG_NF_NAT=m -CONFIG_NF_NAT_REDIRECT=y -CONFIG_NF_NAT_MASQUERADE=y -CONFIG_NETFILTER_SYNPROXY=m CONFIG_NF_TABLES=m -# CONFIG_NF_TABLES_INET is not set CONFIG_NF_TABLES_NETDEV=y -# CONFIG_NFT_NUMGEN is not set CONFIG_NFT_CT=m CONFIG_NFT_COUNTER=m CONFIG_NFT_CONNLIMIT=m @@ -1180,36 +186,10 @@ CONFIG_NFT_MASQ=m CONFIG_NFT_REDIR=m CONFIG_NFT_NAT=m CONFIG_NFT_TUNNEL=m -# CONFIG_NFT_OBJREF is not set -# CONFIG_NFT_QUEUE is not set CONFIG_NFT_QUOTA=m CONFIG_NFT_REJECT=m -# CONFIG_NFT_COMPAT is not set -# CONFIG_NFT_HASH is not set -CONFIG_NFT_FIB=m CONFIG_NFT_XFRM=m -# CONFIG_NFT_SOCKET is not set -# CONFIG_NFT_OSF is not set -# CONFIG_NFT_TPROXY is not set -# CONFIG_NFT_SYNPROXY is not set CONFIG_NF_DUP_NETDEV=m -# CONFIG_NFT_DUP_NETDEV is not set -# CONFIG_NFT_FWD_NETDEV is not set -# CONFIG_NFT_FIB_NETDEV is not set -# CONFIG_NFT_REJECT_NETDEV is not set -# CONFIG_NF_FLOW_TABLE is not set -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XTABLES_COMPAT=y - -# -# Xtables combined modules -# -CONFIG_NETFILTER_XT_MARK=m -CONFIG_NETFILTER_XT_CONNMARK=m - -# -# Xtables targets -# CONFIG_NETFILTER_XT_TARGET_AUDIT=m CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m @@ -1217,30 +197,19 @@ CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m CONFIG_NETFILTER_XT_TARGET_CT=m CONFIG_NETFILTER_XT_TARGET_DSCP=m -CONFIG_NETFILTER_XT_TARGET_HL=m CONFIG_NETFILTER_XT_TARGET_HMARK=m CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m CONFIG_NETFILTER_XT_TARGET_LED=m CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_NAT=m -CONFIG_NETFILTER_XT_TARGET_NETMAP=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set -CONFIG_NETFILTER_XT_TARGET_RATEEST=m -CONFIG_NETFILTER_XT_TARGET_REDIRECT=m -CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_SECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m - -# -# Xtables matches -# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m CONFIG_NETFILTER_XT_MATCH_BPF=m CONFIG_NETFILTER_XT_MATCH_CGROUP=m @@ -1255,11 +224,9 @@ CONFIG_NETFILTER_XT_MATCH_CPU=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ECN=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_HL=m CONFIG_NETFILTER_XT_MATCH_IPCOMP=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_L2TP=m @@ -1279,33 +246,17 @@ CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m CONFIG_NETFILTER_XT_MATCH_RECENT=m CONFIG_NETFILTER_XT_MATCH_SCTP=m -# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -# end of Core Netfilter Configuration - -# CONFIG_IP_SET is not set -# CONFIG_IP_VS is not set - -# -# IP: Netfilter Configuration -# -CONFIG_NF_DEFRAG_IPV4=m -# CONFIG_NF_SOCKET_IPV4 is not set -CONFIG_NF_TPROXY_IPV4=m CONFIG_NF_TABLES_IPV4=y -CONFIG_NFT_REJECT_IPV4=m CONFIG_NFT_DUP_IPV4=m CONFIG_NFT_FIB_IPV4=m CONFIG_NF_TABLES_ARP=y -CONFIG_NF_DUP_IPV4=m -# CONFIG_NF_LOG_ARP is not set CONFIG_NF_LOG_IPV4=m -CONFIG_NF_REJECT_IPV4=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m @@ -1327,1744 +278,127 @@ CONFIG_IP_NF_SECURITY=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m -# end of IP: Netfilter Configuration - -# -# IPv6: Netfilter Configuration -# -# CONFIG_NF_SOCKET_IPV6 is not set -CONFIG_NF_TPROXY_IPV6=m CONFIG_NF_TABLES_IPV6=y -CONFIG_NFT_REJECT_IPV6=m CONFIG_NFT_DUP_IPV6=m CONFIG_NFT_FIB_IPV6=m -CONFIG_NF_DUP_IPV6=m -CONFIG_NF_REJECT_IPV6=m -CONFIG_NF_LOG_IPV6=m CONFIG_IP6_NF_IPTABLES=m -# CONFIG_IP6_NF_MATCH_AH is not set -# CONFIG_IP6_NF_MATCH_EUI64 is not set -# CONFIG_IP6_NF_MATCH_FRAG is not set -# CONFIG_IP6_NF_MATCH_OPTS is not set -# CONFIG_IP6_NF_MATCH_HL is not set -# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set -# CONFIG_IP6_NF_MATCH_MH is not set -# CONFIG_IP6_NF_MATCH_RPFILTER is not set -# CONFIG_IP6_NF_MATCH_RT is not set -# CONFIG_IP6_NF_MATCH_SRH is not set -# CONFIG_IP6_NF_TARGET_HL is not set CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m -# CONFIG_IP6_NF_TARGET_SYNPROXY is not set CONFIG_IP6_NF_MANGLE=m -# CONFIG_IP6_NF_RAW is not set -# CONFIG_IP6_NF_SECURITY is not set CONFIG_IP6_NF_NAT=m CONFIG_IP6_NF_TARGET_MASQUERADE=m -# CONFIG_IP6_NF_TARGET_NPT is not set -# end of IPv6: Netfilter Configuration - -CONFIG_NF_DEFRAG_IPV6=m -# CONFIG_NF_TABLES_BRIDGE is not set -# CONFIG_NF_CONNTRACK_BRIDGE is not set -# CONFIG_BRIDGE_NF_EBTABLES is not set -# CONFIG_BPFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_L2TP is not set -CONFIG_STP=y CONFIG_BRIDGE=y -CONFIG_BRIDGE_IGMP_SNOOPING=y -# CONFIG_BRIDGE_VLAN_FILTERING is not set -# CONFIG_BRIDGE_MRP is not set -# CONFIG_BRIDGE_CFM is not set -# CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=y -# CONFIG_VLAN_8021Q_GVRP is not set -# CONFIG_VLAN_8021Q_MVRP is not set -# CONFIG_DECNET is not set -CONFIG_LLC=y -# CONFIG_LLC2 is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_PHONET is not set -# CONFIG_6LOWPAN is not set -# CONFIG_IEEE802154 is not set CONFIG_NET_SCHED=y - -# -# Queueing/Scheduling -# -# CONFIG_NET_SCH_CBQ is not set -# CONFIG_NET_SCH_HTB is not set -# CONFIG_NET_SCH_HFSC is not set -# CONFIG_NET_SCH_PRIO is not set -# CONFIG_NET_SCH_MULTIQ is not set -# CONFIG_NET_SCH_RED is not set -# CONFIG_NET_SCH_SFB is not set -# CONFIG_NET_SCH_SFQ is not set -# CONFIG_NET_SCH_TEQL is not set -# CONFIG_NET_SCH_TBF is not set -# CONFIG_NET_SCH_CBS is not set -# CONFIG_NET_SCH_ETF is not set -# CONFIG_NET_SCH_TAPRIO is not set -# CONFIG_NET_SCH_GRED is not set -# CONFIG_NET_SCH_DSMARK is not set -# CONFIG_NET_SCH_NETEM is not set -# CONFIG_NET_SCH_DRR is not set -# CONFIG_NET_SCH_MQPRIO is not set -# CONFIG_NET_SCH_SKBPRIO is not set -# CONFIG_NET_SCH_CHOKE is not set -# CONFIG_NET_SCH_QFQ is not set -# CONFIG_NET_SCH_CODEL is not set -# CONFIG_NET_SCH_FQ_CODEL is not set -# CONFIG_NET_SCH_CAKE is not set -# CONFIG_NET_SCH_FQ is not set -# CONFIG_NET_SCH_HHF is not set -# CONFIG_NET_SCH_PIE is not set -# CONFIG_NET_SCH_INGRESS is not set -# CONFIG_NET_SCH_PLUG is not set -# CONFIG_NET_SCH_ETS is not set -# CONFIG_NET_SCH_DEFAULT is not set - -# -# Classification -# -CONFIG_NET_CLS=y -# CONFIG_NET_CLS_BASIC is not set -# CONFIG_NET_CLS_TCINDEX is not set -# CONFIG_NET_CLS_ROUTE4 is not set -# CONFIG_NET_CLS_FW is not set -# CONFIG_NET_CLS_U32 is not set -# CONFIG_NET_CLS_RSVP is not set -# CONFIG_NET_CLS_RSVP6 is not set -# CONFIG_NET_CLS_FLOW is not set -# CONFIG_NET_CLS_CGROUP is not set -# CONFIG_NET_CLS_BPF is not set -# CONFIG_NET_CLS_FLOWER is not set -# CONFIG_NET_CLS_MATCHALL is not set CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_STACK=32 -# CONFIG_NET_EMATCH_CMP is not set -# CONFIG_NET_EMATCH_NBYTE is not set -# CONFIG_NET_EMATCH_U32 is not set -# CONFIG_NET_EMATCH_META is not set -# CONFIG_NET_EMATCH_TEXT is not set -# CONFIG_NET_EMATCH_IPT is not set CONFIG_NET_CLS_ACT=y -# CONFIG_NET_ACT_POLICE is not set -# CONFIG_NET_ACT_GACT is not set -# CONFIG_NET_ACT_MIRRED is not set -# CONFIG_NET_ACT_SAMPLE is not set -# CONFIG_NET_ACT_IPT is not set -# CONFIG_NET_ACT_NAT is not set -# CONFIG_NET_ACT_PEDIT is not set -# CONFIG_NET_ACT_SIMP is not set -# CONFIG_NET_ACT_SKBEDIT is not set -# CONFIG_NET_ACT_CSUM is not set -# CONFIG_NET_ACT_MPLS is not set -# CONFIG_NET_ACT_VLAN is not set -# CONFIG_NET_ACT_BPF is not set -# CONFIG_NET_ACT_CONNMARK is not set -# CONFIG_NET_ACT_CTINFO is not set -# CONFIG_NET_ACT_SKBMOD is not set -# CONFIG_NET_ACT_IFE is not set -# CONFIG_NET_ACT_TUNNEL_KEY is not set -# CONFIG_NET_ACT_GATE is not set -# CONFIG_NET_TC_SKB_EXT is not set -CONFIG_NET_SCH_FIFO=y -# CONFIG_DCB is not set -CONFIG_DNS_RESOLVER=y -# CONFIG_BATMAN_ADV is not set -# CONFIG_OPENVSWITCH is not set -# CONFIG_VSOCKETS is not set CONFIG_NETLINK_DIAG=y -# CONFIG_MPLS is not set -# CONFIG_NET_NSH is not set -# CONFIG_HSR is not set -# CONFIG_NET_SWITCHDEV is not set -# CONFIG_NET_L3_MASTER_DEV is not set -# CONFIG_QRTR is not set -# CONFIG_NET_NCSI is not set -CONFIG_PCPU_DEV_REFCNT=y -CONFIG_RPS=y -CONFIG_RFS_ACCEL=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_XPS=y -# CONFIG_CGROUP_NET_PRIO is not set -CONFIG_CGROUP_NET_CLASSID=y -CONFIG_NET_RX_BUSY_POLL=y -CONFIG_BQL=y -# CONFIG_BPF_STREAM_PARSER is not set -CONFIG_NET_FLOW_LIMIT=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_DROP_MONITOR is not set -# end of Network testing -# end of Networking options - CONFIG_HAMRADIO=y - -# -# Packet Radio protocols -# -# CONFIG_AX25 is not set -# CONFIG_CAN is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -# CONFIG_AF_KCM is not set -CONFIG_FIB_RULES=y -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set - -# -# CFG80211 needs to be enabled for MAC80211 -# -CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 CONFIG_RFKILL=y -CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y -# CONFIG_NET_9P is not set -# CONFIG_CAIF is not set -# CONFIG_CEPH_LIB is not set -# CONFIG_NFC is not set -# CONFIG_PSAMPLE is not set -# CONFIG_NET_IFE is not set -# CONFIG_LWTUNNEL is not set -CONFIG_DST_CACHE=y -CONFIG_GRO_CELLS=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SOCK_MSG=y -# CONFIG_FAILOVER is not set -CONFIG_ETHTOOL_NETLINK=y - -# -# Device Drivers -# -CONFIG_HAVE_EISA=y -# CONFIG_EISA is not set -CONFIG_HAVE_PCI=y CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y CONFIG_PCIEPORTBUS=y CONFIG_HOTPLUG_PCI_PCIE=y CONFIG_PCIEAER=y -# CONFIG_PCIEAER_INJECT is not set -# CONFIG_PCIE_ECRC is not set -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -# CONFIG_PCIEASPM_PERFORMANCE is not set -CONFIG_PCIE_PME=y -# CONFIG_PCIE_DPC is not set -# CONFIG_PCIE_PTM is not set -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCI_QUIRKS=y -# CONFIG_PCI_DEBUG is not set CONFIG_PCI_REALLOC_ENABLE_AUTO=y CONFIG_PCI_STUB=y -# CONFIG_PCI_PF_STUB is not set -CONFIG_PCI_ATS=y -CONFIG_PCI_LOCKLESS_CONFIG=y CONFIG_PCI_IOV=y -CONFIG_PCI_PRI=y -CONFIG_PCI_PASID=y -# CONFIG_PCI_P2PDMA is not set -CONFIG_PCI_LABEL=y -# CONFIG_PCIE_BUS_TUNE_OFF is not set -CONFIG_PCIE_BUS_DEFAULT=y -# CONFIG_PCIE_BUS_SAFE is not set -# CONFIG_PCIE_BUS_PERFORMANCE is not set -# CONFIG_PCIE_BUS_PEER2PEER is not set CONFIG_HOTPLUG_PCI=y -# CONFIG_HOTPLUG_PCI_ACPI is not set -# CONFIG_HOTPLUG_PCI_CPCI is not set -# CONFIG_HOTPLUG_PCI_SHPC is not set - -# -# PCI controller drivers -# -# CONFIG_VMD is not set - -# -# DesignWare PCI Core Support -# -# CONFIG_PCIE_DW_PLAT_HOST is not set -# CONFIG_PCI_MESON is not set -# end of DesignWare PCI Core Support - -# -# Mobiveil PCIe Core Support -# -# end of Mobiveil PCIe Core Support - -# -# Cadence PCIe controllers support -# -# end of Cadence PCIe controllers support -# end of PCI controller drivers - -# -# PCI Endpoint -# -# CONFIG_PCI_ENDPOINT is not set -# end of PCI Endpoint - -# -# PCI switch controller drivers -# -# CONFIG_PCI_SW_SWITCHTEC is not set -# end of PCI switch controller drivers - -# CONFIG_CXL_BUS is not set -# CONFIG_PCCARD is not set CONFIG_RAPIDIO=y -# CONFIG_RAPIDIO_TSI721 is not set -CONFIG_RAPIDIO_DISC_TIMEOUT=30 -# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set CONFIG_RAPIDIO_DMA_ENGINE=y -# CONFIG_RAPIDIO_DEBUG is not set -# CONFIG_RAPIDIO_ENUM_BASIC is not set -# CONFIG_RAPIDIO_CHMAN is not set -# CONFIG_RAPIDIO_MPORT_CDEV is not set - -# -# RapidIO Switch drivers -# -# CONFIG_RAPIDIO_TSI57X is not set -# CONFIG_RAPIDIO_CPS_XX is not set -# CONFIG_RAPIDIO_TSI568 is not set -# CONFIG_RAPIDIO_CPS_GEN2 is not set -# CONFIG_RAPIDIO_RXS_GEN3 is not set -# end of RapidIO Switch drivers - -# -# Generic Driver Options -# CONFIG_UEVENT_HELPER=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y # CONFIG_PREVENT_FIRMWARE_BUILD is not set - -# -# Firmware loader -# -CONFIG_FW_LOADER=y -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_FW_LOADER_USER_HELPER is not set -# CONFIG_FW_LOADER_COMPRESS is not set -CONFIG_FW_CACHE=y -# end of Firmware loader - -CONFIG_ALLOW_DEV_COREDUMP=y -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set -# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_DMA_SHARED_BUFFER=y -# CONFIG_DMA_FENCE_TRACE is not set -# end of Generic Driver Options - -# -# Bus devices -# -# CONFIG_MHI_BUS is not set -# end of Bus devices - -# CONFIG_CONNECTOR is not set -# CONFIG_GNSS is not set -# CONFIG_MTD is not set -# CONFIG_OF is not set -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_EFI_VARS=y CONFIG_PARPORT=y CONFIG_PARPORT_PC=y CONFIG_PARPORT_SERIAL=y -# CONFIG_PARPORT_PC_FIFO is not set -# CONFIG_PARPORT_PC_SUPERIO is not set -# CONFIG_PARPORT_AX88796 is not set -# CONFIG_PARPORT_1284 is not set -CONFIG_PNP=y -CONFIG_PNP_DEBUG_MESSAGES=y - -# -# Protocols -# -CONFIG_PNPACPI=y -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_NULL_BLK is not set -# CONFIG_BLK_DEV_FD is not set -CONFIG_CDROM=y -# CONFIG_PARIDE is not set -# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set -# CONFIG_ZRAM is not set CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_DRBD is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_RBD is not set -# CONFIG_BLK_DEV_RSXX is not set - -# -# NVME Support -# -CONFIG_NVME_CORE=y CONFIG_BLK_DEV_NVME=y -# CONFIG_NVME_MULTIPATH is not set -# CONFIG_NVME_HWMON is not set -# CONFIG_NVME_FC is not set -# CONFIG_NVME_TCP is not set -# CONFIG_NVME_TARGET is not set -# end of NVME Support - -# -# Misc devices -# -# CONFIG_AD525X_DPOT is not set -# CONFIG_DUMMY_IRQ is not set -# CONFIG_IBM_ASM is not set -# CONFIG_PHANTOM is not set -# CONFIG_TIFM_CORE is not set -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_HP_ILO is not set -# CONFIG_APDS9802ALS is not set -# CONFIG_ISL29003 is not set -# CONFIG_ISL29020 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_SENSORS_BH1770 is not set -# CONFIG_SENSORS_APDS990X is not set -# CONFIG_HMC6352 is not set -# CONFIG_DS1682 is not set -# CONFIG_SRAM is not set -# CONFIG_DW_XDATA_PCIE is not set -# CONFIG_PCI_ENDPOINT_TEST is not set -# CONFIG_XILINX_SDFEC is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -# CONFIG_EEPROM_93CX6 is not set -# CONFIG_EEPROM_IDT_89HPESX is not set -# CONFIG_EEPROM_EE1004 is not set -# end of EEPROM support - -# CONFIG_CB710_CORE is not set - -# -# Texas Instruments shared transport line discipline -# -# end of Texas Instruments shared transport line discipline - -# CONFIG_SENSORS_LIS3_I2C is not set -# CONFIG_ALTERA_STAPL is not set -# CONFIG_INTEL_MEI is not set -# CONFIG_INTEL_MEI_ME is not set -# CONFIG_INTEL_MEI_TXE is not set -# CONFIG_VMWARE_VMCI is not set -# CONFIG_GENWQE is not set -# CONFIG_ECHO is not set -# CONFIG_BCM_VK is not set -# CONFIG_MISC_ALCOR_PCI is not set -# CONFIG_MISC_RTSX_PCI is not set -# CONFIG_MISC_RTSX_USB is not set -# CONFIG_HABANA_AI is not set -# CONFIG_UACCE is not set -# CONFIG_PVPANIC is not set -# end of Misc devices - -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_SCSI_MOD=y -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set CONFIG_BLK_DEV_SR=y CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_SCH is not set CONFIG_SCSI_CONSTANTS=y -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set - -# -# SCSI Transports -# -CONFIG_SCSI_SPI_ATTRS=y -# CONFIG_SCSI_FC_ATTRS is not set CONFIG_SCSI_ISCSI_ATTRS=y -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -# end of SCSI Transports - # CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_DH is not set -# end of SCSI device support - CONFIG_ATA=y -CONFIG_SATA_HOST=y -CONFIG_PATA_TIMINGS=y -CONFIG_ATA_VERBOSE_ERROR=y -CONFIG_ATA_FORCE=y -CONFIG_ATA_ACPI=y -# CONFIG_SATA_ZPODD is not set -CONFIG_SATA_PMP=y - -# -# Controllers with non-SFF native interface -# CONFIG_SATA_AHCI=y -CONFIG_SATA_MOBILE_LPM_POLICY=0 CONFIG_SATA_AHCI_PLATFORM=y -# CONFIG_SATA_INIC162X is not set -# CONFIG_SATA_ACARD_AHCI is not set CONFIG_SATA_SIL24=y -CONFIG_ATA_SFF=y - -# -# SFF controllers with custom DMA interface -# -# CONFIG_PDC_ADMA is not set -# CONFIG_SATA_QSTOR is not set CONFIG_SATA_SX4=y -CONFIG_ATA_BMDMA=y - -# -# SATA SFF controllers with BMDMA -# CONFIG_ATA_PIIX=y -# CONFIG_SATA_DWC is not set -# CONFIG_SATA_MV is not set -# CONFIG_SATA_NV is not set CONFIG_SATA_PROMISE=y CONFIG_SATA_SIL=y -# CONFIG_SATA_SIS is not set -# CONFIG_SATA_SVW is not set -# CONFIG_SATA_ULI is not set -# CONFIG_SATA_VIA is not set -# CONFIG_SATA_VITESSE is not set - -# -# PATA SFF controllers with BMDMA -# -# CONFIG_PATA_ALI is not set CONFIG_PATA_AMD=y -# CONFIG_PATA_ARTOP is not set CONFIG_PATA_ATIIXP=y -# CONFIG_PATA_ATP867X is not set -# CONFIG_PATA_CMD64X is not set -# CONFIG_PATA_CYPRESS is not set -# CONFIG_PATA_EFAR is not set -# CONFIG_PATA_HPT366 is not set -# CONFIG_PATA_HPT37X is not set -# CONFIG_PATA_HPT3X2N is not set -# CONFIG_PATA_HPT3X3 is not set -# CONFIG_PATA_IT8213 is not set -# CONFIG_PATA_IT821X is not set -# CONFIG_PATA_JMICRON is not set -# CONFIG_PATA_MARVELL is not set -# CONFIG_PATA_NETCELL is not set -# CONFIG_PATA_NINJA32 is not set -# CONFIG_PATA_NS87415 is not set CONFIG_PATA_OLDPIIX=y -# CONFIG_PATA_OPTIDMA is not set -# CONFIG_PATA_PDC2027X is not set -# CONFIG_PATA_PDC_OLD is not set -# CONFIG_PATA_RADISYS is not set -# CONFIG_PATA_RDC is not set CONFIG_PATA_SCH=y CONFIG_PATA_SERVERWORKS=y -# CONFIG_PATA_SIL680 is not set -# CONFIG_PATA_SIS is not set -# CONFIG_PATA_TOSHIBA is not set -# CONFIG_PATA_TRIFLEX is not set -# CONFIG_PATA_VIA is not set -# CONFIG_PATA_WINBOND is not set - -# -# PIO-only SFF controllers -# -# CONFIG_PATA_CMD640_PCI is not set -# CONFIG_PATA_MPIIX is not set -# CONFIG_PATA_NS87410 is not set -# CONFIG_PATA_OPTI is not set -# CONFIG_PATA_PLATFORM is not set -# CONFIG_PATA_RZ1000 is not set - -# -# Generic fallback / legacy drivers -# -# CONFIG_PATA_ACPI is not set CONFIG_ATA_GENERIC=y -# CONFIG_PATA_LEGACY is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=y -CONFIG_MD_AUTODETECT=y -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID10 is not set -# CONFIG_MD_RAID456 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_MD_FAULTY is not set -# CONFIG_BCACHE is not set -CONFIG_BLK_DEV_DM_BUILTIN=y CONFIG_BLK_DEV_DM=y -# CONFIG_DM_DEBUG is not set -# CONFIG_DM_UNSTRIPED is not set -# CONFIG_DM_CRYPT is not set -# CONFIG_DM_SNAPSHOT is not set -# CONFIG_DM_THIN_PROVISIONING is not set -# CONFIG_DM_CACHE is not set -# CONFIG_DM_WRITECACHE is not set -# CONFIG_DM_EBS is not set -# CONFIG_DM_ERA is not set -# CONFIG_DM_CLONE is not set CONFIG_DM_MIRROR=y -# CONFIG_DM_LOG_USERSPACE is not set -# CONFIG_DM_RAID is not set CONFIG_DM_ZERO=y -# CONFIG_DM_MULTIPATH is not set -# CONFIG_DM_DELAY is not set -# CONFIG_DM_DUST is not set -# CONFIG_DM_INIT is not set -# CONFIG_DM_UEVENT is not set -# CONFIG_DM_FLAKEY is not set -# CONFIG_DM_VERITY is not set -# CONFIG_DM_SWITCH is not set -# CONFIG_DM_LOG_WRITES is not set -# CONFIG_DM_INTEGRITY is not set -# CONFIG_TARGET_CORE is not set CONFIG_FUSION=y CONFIG_FUSION_SPI=y -# CONFIG_FUSION_SAS is not set -CONFIG_FUSION_MAX_SGE=128 -# CONFIG_FUSION_CTL is not set -# CONFIG_FUSION_LOGGING is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_FIREWIRE is not set -# CONFIG_FIREWIRE_NOSY is not set -# end of IEEE 1394 (FireWire) support - -# CONFIG_MACINTOSH_DRIVERS is not set CONFIG_NETDEVICES=y -CONFIG_MII=y -CONFIG_NET_CORE=y -# CONFIG_BONDING is not set -# CONFIG_DUMMY is not set -# CONFIG_WIREGUARD is not set -# CONFIG_EQUALIZER is not set -# CONFIG_NET_FC is not set -# CONFIG_IFB is not set -# CONFIG_NET_TEAM is not set CONFIG_MACVLAN=y -# CONFIG_MACVTAP is not set -# CONFIG_IPVLAN is not set -# CONFIG_VXLAN is not set -# CONFIG_GENEVE is not set -# CONFIG_BAREUDP is not set -# CONFIG_GTP is not set -# CONFIG_MACSEC is not set CONFIG_NETCONSOLE=y CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_NETPOLL=y -CONFIG_NET_POLL_CONTROLLER=y -# CONFIG_RIONET is not set CONFIG_TUN=y -# CONFIG_TUN_VNET_CROSS_LE is not set CONFIG_VETH=y -# CONFIG_NLMON is not set -# CONFIG_ARCNET is not set -CONFIG_ETHERNET=y -CONFIG_MDIO=y -CONFIG_NET_VENDOR_3COM=y -# CONFIG_VORTEX is not set -# CONFIG_TYPHOON is not set -CONFIG_NET_VENDOR_ADAPTEC=y -# CONFIG_ADAPTEC_STARFIRE is not set -CONFIG_NET_VENDOR_AGERE=y -# CONFIG_ET131X is not set -CONFIG_NET_VENDOR_ALACRITECH=y -# CONFIG_SLICOSS is not set -CONFIG_NET_VENDOR_ALTEON=y -# CONFIG_ACENIC is not set -# CONFIG_ALTERA_TSE is not set -CONFIG_NET_VENDOR_AMAZON=y -# CONFIG_ENA_ETHERNET is not set -CONFIG_NET_VENDOR_AMD=y -# CONFIG_AMD8111_ETH is not set -# CONFIG_PCNET32 is not set -# CONFIG_AMD_XGBE is not set -CONFIG_NET_VENDOR_AQUANTIA=y -# CONFIG_AQTION is not set -CONFIG_NET_VENDOR_ARC=y -CONFIG_NET_VENDOR_ATHEROS=y -# CONFIG_ATL2 is not set -# CONFIG_ATL1 is not set -# CONFIG_ATL1E is not set -# CONFIG_ATL1C is not set CONFIG_ALX=y -CONFIG_NET_VENDOR_BROADCOM=y -# CONFIG_B44 is not set -# CONFIG_BCMGENET is not set CONFIG_BNX2=y -# CONFIG_CNIC is not set CONFIG_TIGON3=y -CONFIG_TIGON3_HWMON=y -# CONFIG_BNX2X is not set -# CONFIG_SYSTEMPORT is not set -# CONFIG_BNXT is not set -CONFIG_NET_VENDOR_BROCADE=y -# CONFIG_BNA is not set -CONFIG_NET_VENDOR_CADENCE=y -# CONFIG_MACB is not set -CONFIG_NET_VENDOR_CAVIUM=y -# CONFIG_THUNDER_NIC_PF is not set -# CONFIG_THUNDER_NIC_VF is not set -# CONFIG_THUNDER_NIC_BGX is not set -# CONFIG_THUNDER_NIC_RGX is not set CONFIG_CAVIUM_PTP=y -# CONFIG_LIQUIDIO is not set -# CONFIG_LIQUIDIO_VF is not set -CONFIG_NET_VENDOR_CHELSIO=y -# CONFIG_CHELSIO_T1 is not set -# CONFIG_CHELSIO_T3 is not set -# CONFIG_CHELSIO_T4 is not set -# CONFIG_CHELSIO_T4VF is not set -CONFIG_NET_VENDOR_CISCO=y -# CONFIG_ENIC is not set -CONFIG_NET_VENDOR_CORTINA=y -# CONFIG_CX_ECAT is not set -# CONFIG_DNET is not set -CONFIG_NET_VENDOR_DEC=y CONFIG_NET_TULIP=y -# CONFIG_DE2104X is not set -# CONFIG_TULIP is not set -# CONFIG_DE4X5 is not set -# CONFIG_WINBOND_840 is not set -# CONFIG_DM9102 is not set -# CONFIG_ULI526X is not set -CONFIG_NET_VENDOR_DLINK=y -# CONFIG_DL2K is not set -# CONFIG_SUNDANCE is not set -CONFIG_NET_VENDOR_EMULEX=y -# CONFIG_BE2NET is not set -CONFIG_NET_VENDOR_EZCHIP=y -CONFIG_NET_VENDOR_GOOGLE=y -# CONFIG_GVE is not set -CONFIG_NET_VENDOR_HUAWEI=y -# CONFIG_HINIC is not set -CONFIG_NET_VENDOR_I825XX=y -CONFIG_NET_VENDOR_INTEL=y CONFIG_E100=y CONFIG_E1000=y CONFIG_E1000E=y -CONFIG_E1000E_HWTS=y CONFIG_IGB=y -CONFIG_IGB_HWMON=y CONFIG_IGBVF=y CONFIG_IXGB=y CONFIG_IXGBE=y -CONFIG_IXGBE_HWMON=y -# CONFIG_IXGBEVF is not set CONFIG_I40E=y -# CONFIG_I40EVF is not set -# CONFIG_ICE is not set -# CONFIG_FM10K is not set -# CONFIG_IGC is not set -CONFIG_NET_VENDOR_MICROSOFT=y -# CONFIG_JME is not set -CONFIG_NET_VENDOR_MARVELL=y -# CONFIG_MVMDIO is not set -# CONFIG_SKGE is not set CONFIG_SKY2=y -# CONFIG_SKY2_DEBUG is not set -CONFIG_NET_VENDOR_MELLANOX=y -# CONFIG_MLX4_EN is not set -# CONFIG_MLX5_CORE is not set -# CONFIG_MLXSW_CORE is not set -# CONFIG_MLXFW is not set -CONFIG_NET_VENDOR_MICREL=y -# CONFIG_KS8842 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_KSZ884X_PCI is not set -CONFIG_NET_VENDOR_MICROCHIP=y -# CONFIG_LAN743X is not set -CONFIG_NET_VENDOR_MICROSEMI=y -CONFIG_NET_VENDOR_MYRI=y -# CONFIG_MYRI10GE is not set -# CONFIG_FEALNX is not set -CONFIG_NET_VENDOR_NATSEMI=y -# CONFIG_NATSEMI is not set -# CONFIG_NS83820 is not set -CONFIG_NET_VENDOR_NETERION=y -# CONFIG_S2IO is not set -# CONFIG_VXGE is not set -CONFIG_NET_VENDOR_NETRONOME=y -# CONFIG_NFP is not set -CONFIG_NET_VENDOR_NI=y -# CONFIG_NI_XGE_MANAGEMENT_ENET is not set -CONFIG_NET_VENDOR_8390=y -# CONFIG_NE2K_PCI is not set -CONFIG_NET_VENDOR_NVIDIA=y CONFIG_FORCEDETH=y -CONFIG_NET_VENDOR_OKI=y -# CONFIG_ETHOC is not set -CONFIG_NET_VENDOR_PACKET_ENGINES=y -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -CONFIG_NET_VENDOR_PENSANDO=y -# CONFIG_IONIC is not set -CONFIG_NET_VENDOR_QLOGIC=y -# CONFIG_QLA3XXX is not set -# CONFIG_QLCNIC is not set -# CONFIG_NETXEN_NIC is not set -# CONFIG_QED is not set -CONFIG_NET_VENDOR_QUALCOMM=y -# CONFIG_QCOM_EMAC is not set -# CONFIG_RMNET is not set -CONFIG_NET_VENDOR_RDC=y -# CONFIG_R6040 is not set -CONFIG_NET_VENDOR_REALTEK=y -# CONFIG_ATP is not set CONFIG_8139CP=y CONFIG_8139TOO=y -CONFIG_8139TOO_PIO=y -# CONFIG_8139TOO_TUNE_TWISTER is not set -# CONFIG_8139TOO_8129 is not set -# CONFIG_8139_OLD_RX_RESET is not set CONFIG_R8169=y -CONFIG_NET_VENDOR_RENESAS=y -CONFIG_NET_VENDOR_ROCKER=y -CONFIG_NET_VENDOR_SAMSUNG=y -# CONFIG_SXGBE_ETH is not set -CONFIG_NET_VENDOR_SEEQ=y -CONFIG_NET_VENDOR_SOLARFLARE=y -# CONFIG_SFC is not set -# CONFIG_SFC_FALCON is not set -CONFIG_NET_VENDOR_SILAN=y -# CONFIG_SC92031 is not set -CONFIG_NET_VENDOR_SIS=y -# CONFIG_SIS900 is not set -# CONFIG_SIS190 is not set -CONFIG_NET_VENDOR_SMSC=y -# CONFIG_EPIC100 is not set -# CONFIG_SMSC911X is not set -# CONFIG_SMSC9420 is not set -CONFIG_NET_VENDOR_SOCIONEXT=y -CONFIG_NET_VENDOR_STMICRO=y -# CONFIG_STMMAC_ETH is not set -CONFIG_NET_VENDOR_SUN=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NIU is not set -CONFIG_NET_VENDOR_SYNOPSYS=y -# CONFIG_DWC_XLGMAC is not set -CONFIG_NET_VENDOR_TEHUTI=y -# CONFIG_TEHUTI is not set -CONFIG_NET_VENDOR_TI=y -# CONFIG_TI_CPSW_PHY_SEL is not set -# CONFIG_TLAN is not set -CONFIG_NET_VENDOR_VIA=y -# CONFIG_VIA_RHINE is not set -# CONFIG_VIA_VELOCITY is not set -CONFIG_NET_VENDOR_WIZNET=y CONFIG_WIZNET_W5100=y CONFIG_WIZNET_W5300=y -# CONFIG_WIZNET_BUS_DIRECT is not set -# CONFIG_WIZNET_BUS_INDIRECT is not set -CONFIG_WIZNET_BUS_ANY=y -CONFIG_NET_VENDOR_XILINX=y -# CONFIG_XILINX_EMACLITE is not set -# CONFIG_XILINX_AXI_EMAC is not set -# CONFIG_XILINX_LL_TEMAC is not set CONFIG_FDDI=y -# CONFIG_DEFXX is not set -# CONFIG_SKFP is not set -# CONFIG_HIPPI is not set -# CONFIG_NET_SB1000 is not set -CONFIG_PHYLIB=y -# CONFIG_LED_TRIGGER_PHY is not set -# CONFIG_FIXED_PHY is not set - -# -# MII PHY device drivers -# CONFIG_AMD_PHY=y -# CONFIG_ADIN_PHY is not set -# CONFIG_AQUANTIA_PHY is not set -# CONFIG_AX88796B_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_BCM54140_PHY is not set -# CONFIG_BCM7XXX_PHY is not set -# CONFIG_BCM84881_PHY is not set -# CONFIG_BCM87XX_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_CORTINA_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_INTEL_XWAY_PHY is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_MARVELL_PHY is not set -# CONFIG_MARVELL_10G_PHY is not set -# CONFIG_MARVELL_88X2222_PHY is not set -# CONFIG_MICREL_PHY is not set -# CONFIG_MICROCHIP_PHY is not set -# CONFIG_MICROCHIP_T1_PHY is not set -# CONFIG_MICROSEMI_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_NXP_C45_TJA11XX_PHY is not set -# CONFIG_NXP_TJA11XX_PHY is not set -# CONFIG_QSEMI_PHY is not set -CONFIG_REALTEK_PHY=y -# CONFIG_RENESAS_PHY is not set -# CONFIG_ROCKCHIP_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_TERANETICS_PHY is not set -# CONFIG_DP83822_PHY is not set -# CONFIG_DP83TC811_PHY is not set -# CONFIG_DP83848_PHY is not set -# CONFIG_DP83867_PHY is not set -# CONFIG_DP83869_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_XILINX_GMII2RGMII is not set -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVRES=y -# CONFIG_MDIO_BITBANG is not set -# CONFIG_MDIO_BCM_UNIMAC is not set -# CONFIG_MDIO_MVUSB is not set -# CONFIG_MDIO_MSCC_MIIM is not set -# CONFIG_MDIO_THUNDER is not set - -# -# MDIO Multiplexers -# - -# -# PCS device drivers -# -# CONFIG_PCS_XPCS is not set -# end of PCS device drivers - -# CONFIG_PLIP is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set CONFIG_USB_NET_DRIVERS=m -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set CONFIG_USB_RTL8152=m -# CONFIG_USB_LAN78XX is not set CONFIG_USB_USBNET=m -CONFIG_USB_NET_AX8817X=m -CONFIG_USB_NET_AX88179_178A=m -CONFIG_USB_NET_CDCETHER=m -# CONFIG_USB_NET_CDC_EEM is not set -CONFIG_USB_NET_CDC_NCM=m -# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set -# CONFIG_USB_NET_CDC_MBIM is not set -# CONFIG_USB_NET_DM9601 is not set -# CONFIG_USB_NET_SR9700 is not set -# CONFIG_USB_NET_SR9800 is not set -# CONFIG_USB_NET_SMSC75XX is not set -# CONFIG_USB_NET_SMSC95XX is not set -# CONFIG_USB_NET_GL620A is not set -CONFIG_USB_NET_NET1080=m -# CONFIG_USB_NET_PLUSB is not set -# CONFIG_USB_NET_MCS7830 is not set -# CONFIG_USB_NET_RNDIS_HOST is not set -CONFIG_USB_NET_CDC_SUBSET_ENABLE=m -CONFIG_USB_NET_CDC_SUBSET=m -# CONFIG_USB_ALI_M5632 is not set -# CONFIG_USB_AN2720 is not set -CONFIG_USB_BELKIN=y # CONFIG_USB_ARMLINUX is not set -# CONFIG_USB_EPSON2888 is not set -# CONFIG_USB_KC2190 is not set # CONFIG_USB_NET_ZAURUS is not set -# CONFIG_USB_NET_CX82310_ETH is not set -# CONFIG_USB_NET_KALMIA is not set -# CONFIG_USB_NET_QMI_WWAN is not set -# CONFIG_USB_HSO is not set -# CONFIG_USB_NET_INT51X1 is not set -# CONFIG_USB_IPHETH is not set -# CONFIG_USB_SIERRA_NET is not set -# CONFIG_USB_VL600 is not set -# CONFIG_USB_NET_CH9200 is not set -# CONFIG_USB_NET_AQC111 is not set -# CONFIG_USB_RTL8153_ECM is not set -CONFIG_WLAN=y -CONFIG_WLAN_VENDOR_ADMTEK=y -CONFIG_WLAN_VENDOR_ATH=y -# CONFIG_ATH_DEBUG is not set -# CONFIG_ATH5K_PCI is not set -CONFIG_WLAN_VENDOR_ATMEL=y -CONFIG_WLAN_VENDOR_BROADCOM=y -CONFIG_WLAN_VENDOR_CISCO=y -CONFIG_WLAN_VENDOR_INTEL=y -CONFIG_WLAN_VENDOR_INTERSIL=y -# CONFIG_HOSTAP is not set -# CONFIG_PRISM54 is not set -CONFIG_WLAN_VENDOR_MARVELL=y -CONFIG_WLAN_VENDOR_MEDIATEK=y -CONFIG_WLAN_VENDOR_MICROCHIP=y -CONFIG_WLAN_VENDOR_RALINK=y -CONFIG_WLAN_VENDOR_REALTEK=y -CONFIG_WLAN_VENDOR_RSI=y -CONFIG_WLAN_VENDOR_ST=y -CONFIG_WLAN_VENDOR_TI=y -CONFIG_WLAN_VENDOR_ZYDAS=y -CONFIG_WLAN_VENDOR_QUANTENNA=y -# CONFIG_WAN is not set -# CONFIG_WWAN is not set -# CONFIG_VMXNET3 is not set -# CONFIG_FUJITSU_ES is not set -# CONFIG_NETDEVSIM is not set -# CONFIG_NET_FAILOVER is not set -# CONFIG_ISDN is not set -# CONFIG_NVM is not set - -# -# Input device support -# -CONFIG_INPUT=y -CONFIG_INPUT_LEDS=y -CONFIG_INPUT_FF_MEMLESS=y CONFIG_INPUT_SPARSEKMAP=y -# CONFIG_INPUT_MATRIXKMAP is not set - -# -# Userland interfaces -# CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ADP5589 is not set -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_QT1050 is not set -# CONFIG_KEYBOARD_QT1070 is not set -# CONFIG_KEYBOARD_QT2160 is not set -# CONFIG_KEYBOARD_DLINK_DIR685 is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_TCA6416 is not set -# CONFIG_KEYBOARD_TCA8418 is not set -# CONFIG_KEYBOARD_LM8323 is not set -# CONFIG_KEYBOARD_LM8333 is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_MCS is not set -# CONFIG_KEYBOARD_MPR121 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_SAMSUNG is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_BYD=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y -CONFIG_MOUSE_PS2_CYPRESS=y -CONFIG_MOUSE_PS2_LIFEBOOK=y -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_ELANTECH is not set -# CONFIG_MOUSE_PS2_SENTELIC is not set -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -CONFIG_MOUSE_PS2_FOCALTECH=y -# CONFIG_MOUSE_PS2_VMMOUSE is not set -CONFIG_MOUSE_PS2_SMBUS=y -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_CYAPA is not set -# CONFIG_MOUSE_ELAN_I2C is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MOUSE_SYNAPTICS_I2C is not set -# CONFIG_MOUSE_SYNAPTICS_USB is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set -# CONFIG_RMI4_CORE is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PARKBD is not set -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_ALTERA_PS2 is not set -# CONFIG_SERIO_PS2MULT is not set -# CONFIG_SERIO_ARC_PS2 is not set -# CONFIG_USERIO is not set -# CONFIG_GAMEPORT is not set -# end of Hardware I/O ports -# end of Input device support - -# -# Character devices -# -CONFIG_TTY=y -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set -CONFIG_LDISC_AUTOLOAD=y - -# -# Serial drivers -# -CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_PNP=y -# CONFIG_SERIAL_8250_16550A_VARIANTS is not set -# CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_DMA=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_EXAR=y CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_RSA=y -CONFIG_SERIAL_8250_DWLIB=y -# CONFIG_SERIAL_8250_DW is not set -# CONFIG_SERIAL_8250_RT288X is not set -CONFIG_SERIAL_8250_LPSS=y # CONFIG_SERIAL_8250_MID is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_KGDB_NMI is not set -# CONFIG_SERIAL_UARTLITE is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_CONSOLE_POLL=y -# CONFIG_SERIAL_JSM is not set -# CONFIG_SERIAL_LANTIQ is not set -# CONFIG_SERIAL_SCCNXP is not set -# CONFIG_SERIAL_SC16IS7XX is not set -# CONFIG_SERIAL_BCM63XX is not set -# CONFIG_SERIAL_ALTERA_JTAGUART is not set -# CONFIG_SERIAL_ALTERA_UART is not set -# CONFIG_SERIAL_ARC is not set -# CONFIG_SERIAL_RP2 is not set -# CONFIG_SERIAL_FSL_LPUART is not set -# CONFIG_SERIAL_FSL_LINFLEXUART is not set -# CONFIG_SERIAL_SPRD is not set -# end of Serial drivers - CONFIG_SERIAL_NONSTANDARD=y -# CONFIG_MOXA_INTELLIO is not set -# CONFIG_MOXA_SMARTIO is not set -# CONFIG_SYNCLINK_GT is not set -# CONFIG_N_HDLC is not set -# CONFIG_N_GSM is not set -# CONFIG_NOZOMI is not set -# CONFIG_NULL_TTY is not set -# CONFIG_SERIAL_DEV_BUS is not set -# CONFIG_TTY_PRINTK is not set -# CONFIG_PRINTER is not set -# CONFIG_PPDEV is not set -# CONFIG_VIRTIO_CONSOLE is not set -# CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set -# CONFIG_APPLICOM is not set -# CONFIG_MWAVE is not set -CONFIG_DEVMEM=y -# CONFIG_NVRAM is not set -# CONFIG_RAW_DRIVER is not set -CONFIG_DEVPORT=y -# CONFIG_HPET is not set -# CONFIG_HANGCHECK_TIMER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set -# CONFIG_XILLYBUS is not set -# end of Character devices - -# CONFIG_RANDOM_TRUST_CPU is not set -# CONFIG_RANDOM_TRUST_BOOTLOADER is not set - -# -# I2C support -# -CONFIG_I2C=y -CONFIG_ACPI_I2C_OPREGION=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -# CONFIG_I2C_CHARDEV is not set -# CONFIG_I2C_MUX is not set -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_SMBUS=y -CONFIG_I2C_ALGOBIT=y - -# -# I2C Hardware Bus support -# - -# -# PC SMBus host controller drivers -# -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_AMD_MP2 is not set CONFIG_I2C_I801=y -# CONFIG_I2C_ISCH is not set -# CONFIG_I2C_ISMT is not set CONFIG_I2C_PIIX4=m -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_NVIDIA_GPU is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set - -# -# ACPI drivers -# -# CONFIG_I2C_SCMI is not set - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_DESIGNWARE_PLATFORM is not set -# CONFIG_I2C_DESIGNWARE_PCI is not set -# CONFIG_I2C_EMEV2 is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_SIMTEC is not set -# CONFIG_I2C_XILINX is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_DIOLAN_U2C is not set -# CONFIG_I2C_CP2615 is not set -# CONFIG_I2C_PARPORT is not set -# CONFIG_I2C_ROBOTFUZZ_OSIF is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_MLXCPLD is not set -# end of I2C Hardware Bus support - -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_SLAVE is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# end of I2C support - -# CONFIG_I3C is not set -# CONFIG_SPI is not set -# CONFIG_SPMI is not set -# CONFIG_HSI is not set -CONFIG_PPS=y -# CONFIG_PPS_DEBUG is not set - -# -# PPS clients support -# -# CONFIG_PPS_CLIENT_KTIMER is not set -# CONFIG_PPS_CLIENT_LDISC is not set -# CONFIG_PPS_CLIENT_PARPORT is not set -# CONFIG_PPS_CLIENT_GPIO is not set - -# -# PPS generators support -# - -# -# PTP clock support -# -CONFIG_PTP_1588_CLOCK=y - -# -# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. -# -CONFIG_PTP_1588_CLOCK_KVM=y -# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set -# CONFIG_PTP_1588_CLOCK_IDTCM is not set -# CONFIG_PTP_1588_CLOCK_VMW is not set -# CONFIG_PTP_1588_CLOCK_OCP is not set -# end of PTP clock support - -CONFIG_PINCTRL=y -# CONFIG_DEBUG_PINCTRL is not set -# CONFIG_PINCTRL_AMD is not set -# CONFIG_PINCTRL_MCP23S08 is not set -# CONFIG_PINCTRL_SX150X is not set -# CONFIG_PINCTRL_BAYTRAIL is not set -# CONFIG_PINCTRL_CHERRYVIEW is not set -# CONFIG_PINCTRL_LYNXPOINT is not set -# CONFIG_PINCTRL_ALDERLAKE is not set -# CONFIG_PINCTRL_BROXTON is not set -# CONFIG_PINCTRL_CANNONLAKE is not set -# CONFIG_PINCTRL_CEDARFORK is not set -# CONFIG_PINCTRL_DENVERTON is not set -# CONFIG_PINCTRL_ELKHARTLAKE is not set -# CONFIG_PINCTRL_EMMITSBURG is not set -# CONFIG_PINCTRL_GEMINILAKE is not set -# CONFIG_PINCTRL_ICELAKE is not set -# CONFIG_PINCTRL_JASPERLAKE is not set -# CONFIG_PINCTRL_LAKEFIELD is not set -# CONFIG_PINCTRL_LEWISBURG is not set -# CONFIG_PINCTRL_SUNRISEPOINT is not set -# CONFIG_PINCTRL_TIGERLAKE is not set - -# -# Renesas pinctrl drivers -# -# end of Renesas pinctrl drivers - -# CONFIG_GPIOLIB is not set -# CONFIG_W1 is not set -# CONFIG_POWER_RESET is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -CONFIG_POWER_SUPPLY_HWMON=y -# CONFIG_PDA_POWER is not set -# CONFIG_TEST_POWER is not set -# CONFIG_CHARGER_ADP5061 is not set -# CONFIG_BATTERY_CW2015 is not set -# CONFIG_BATTERY_DS2780 is not set -# CONFIG_BATTERY_DS2781 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_SBS is not set -# CONFIG_CHARGER_SBS is not set -# CONFIG_BATTERY_BQ27XXX is not set -# CONFIG_BATTERY_MAX17040 is not set -# CONFIG_BATTERY_MAX17042 is not set -# CONFIG_CHARGER_MAX8903 is not set -# CONFIG_CHARGER_LP8727 is not set -# CONFIG_CHARGER_LTC4162L is not set -# CONFIG_CHARGER_BQ2415X is not set -# CONFIG_CHARGER_SMB347 is not set -# CONFIG_BATTERY_GAUGE_LTC2941 is not set -# CONFIG_BATTERY_GOLDFISH is not set -# CONFIG_CHARGER_BD99954 is not set -CONFIG_HWMON=y -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Native drivers -# -# CONFIG_SENSORS_ABITUGURU is not set -# CONFIG_SENSORS_ABITUGURU3 is not set -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM1177 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7410 is not set -# CONFIG_SENSORS_ADT7411 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_AHT10 is not set -# CONFIG_SENSORS_AS370 is not set -# CONFIG_SENSORS_ASC7621 is not set -# CONFIG_SENSORS_AXI_FAN_CONTROL is not set -# CONFIG_SENSORS_K8TEMP is not set CONFIG_SENSORS_K10TEMP=m -# CONFIG_SENSORS_FAM15H_POWER is not set -# CONFIG_SENSORS_APPLESMC is not set -# CONFIG_SENSORS_ASB100 is not set -# CONFIG_SENSORS_ASPEED is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_CORSAIR_CPRO is not set -# CONFIG_SENSORS_CORSAIR_PSU is not set -# CONFIG_SENSORS_DRIVETEMP is not set -# CONFIG_SENSORS_DS620 is not set -# CONFIG_SENSORS_DS1621 is not set -CONFIG_SENSORS_DELL_SMM=m -# CONFIG_SENSORS_I5K_AMB is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_FSCHMD is not set -# CONFIG_SENSORS_FTSTEUTATES is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_G762 is not set -# CONFIG_SENSORS_HIH6130 is not set -# CONFIG_SENSORS_I5500 is not set -# CONFIG_SENSORS_CORETEMP is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_JC42 is not set -# CONFIG_SENSORS_POWR1220 is not set -# CONFIG_SENSORS_LINEAGE is not set -# CONFIG_SENSORS_LTC2945 is not set -# CONFIG_SENSORS_LTC2947_I2C is not set -# CONFIG_SENSORS_LTC2990 is not set -# CONFIG_SENSORS_LTC4151 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4222 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LTC4260 is not set -# CONFIG_SENSORS_LTC4261 is not set -# CONFIG_SENSORS_MAX127 is not set -# CONFIG_SENSORS_MAX16065 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX1668 is not set -# CONFIG_SENSORS_MAX197 is not set -# CONFIG_SENSORS_MAX31730 is not set -# CONFIG_SENSORS_MAX6621 is not set -# CONFIG_SENSORS_MAX6639 is not set -# CONFIG_SENSORS_MAX6642 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_MAX6697 is not set -# CONFIG_SENSORS_MAX31790 is not set -# CONFIG_SENSORS_MCP3021 is not set -# CONFIG_SENSORS_TC654 is not set -# CONFIG_SENSORS_TPS23861 is not set -# CONFIG_SENSORS_MR75203 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM73 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LM95234 is not set -# CONFIG_SENSORS_LM95241 is not set -# CONFIG_SENSORS_LM95245 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_NTC_THERMISTOR is not set -# CONFIG_SENSORS_NCT6683 is not set -# CONFIG_SENSORS_NCT6775 is not set -# CONFIG_SENSORS_NCT7802 is not set -# CONFIG_SENSORS_NCT7904 is not set -# CONFIG_SENSORS_NPCM7XX is not set -# CONFIG_SENSORS_NZXT_KRAKEN2 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_PMBUS is not set -# CONFIG_SENSORS_SBTSI is not set -# CONFIG_SENSORS_SHT21 is not set -# CONFIG_SENSORS_SHT3x is not set -# CONFIG_SENSORS_SHTC1 is not set -# CONFIG_SENSORS_SIS5595 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_EMC1403 is not set -# CONFIG_SENSORS_EMC2103 is not set -# CONFIG_SENSORS_EMC6W201 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_SCH5627 is not set -# CONFIG_SENSORS_SCH5636 is not set -# CONFIG_SENSORS_STTS751 is not set -# CONFIG_SENSORS_SMM665 is not set -# CONFIG_SENSORS_ADC128D818 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_AMC6821 is not set -# CONFIG_SENSORS_INA209 is not set -# CONFIG_SENSORS_INA2XX is not set -# CONFIG_SENSORS_INA3221 is not set -# CONFIG_SENSORS_TC74 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TMP102 is not set -# CONFIG_SENSORS_TMP103 is not set -# CONFIG_SENSORS_TMP108 is not set -# CONFIG_SENSORS_TMP401 is not set -# CONFIG_SENSORS_TMP421 is not set -# CONFIG_SENSORS_TMP513 is not set -# CONFIG_SENSORS_VIA_CPUTEMP is not set -# CONFIG_SENSORS_VIA686A is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_VT8231 is not set -# CONFIG_SENSORS_W83773G is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83795 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_SENSORS_XGENE is not set - -# -# ACPI drivers -# -# CONFIG_SENSORS_ACPI_POWER is not set -# CONFIG_SENSORS_ATK0110 is not set -CONFIG_THERMAL=y -# CONFIG_THERMAL_NETLINK is not set -# CONFIG_THERMAL_STATISTICS is not set -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set -# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set -# CONFIG_THERMAL_GOV_FAIR_SHARE is not set -CONFIG_THERMAL_GOV_STEP_WISE=y -# CONFIG_THERMAL_GOV_BANG_BANG is not set -CONFIG_THERMAL_GOV_USER_SPACE=y -# CONFIG_THERMAL_EMULATION is not set - -# -# Intel thermal drivers -# -# CONFIG_INTEL_POWERCLAMP is not set -CONFIG_X86_THERMAL_VECTOR=y -CONFIG_X86_PKG_TEMP_THERMAL=m -# CONFIG_INTEL_SOC_DTS_THERMAL is not set - -# -# ACPI INT340X thermal drivers -# -# CONFIG_INT340X_THERMAL is not set -# end of ACPI INT340X thermal drivers - -# CONFIG_INTEL_PCH_THERMAL is not set -# CONFIG_INTEL_TCC_COOLING is not set -# end of Intel thermal drivers - CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_CORE is not set -# CONFIG_WATCHDOG_NOWAYOUT is not set -CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y -CONFIG_WATCHDOG_OPEN_TIMEOUT=0 -# CONFIG_WATCHDOG_SYSFS is not set - -# -# Watchdog Pretimeout Governors -# - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -# CONFIG_WDAT_WDT is not set -# CONFIG_XILINX_WATCHDOG is not set -# CONFIG_ZIIRAVE_WATCHDOG is not set -# CONFIG_CADENCE_WATCHDOG is not set -# CONFIG_DW_WATCHDOG is not set -# CONFIG_MAX63XX_WATCHDOG is not set -# CONFIG_ACQUIRE_WDT is not set -# CONFIG_ADVANTECH_WDT is not set -# CONFIG_ALIM1535_WDT is not set -# CONFIG_ALIM7101_WDT is not set -# CONFIG_EBC_C384_WDT is not set -# CONFIG_F71808E_WDT is not set -# CONFIG_SP5100_TCO is not set -# CONFIG_SBC_FITPC2_WATCHDOG is not set -# CONFIG_EUROTECH_WDT is not set -# CONFIG_IB700_WDT is not set -# CONFIG_IBMASR is not set -# CONFIG_WAFER_WDT is not set -# CONFIG_I6300ESB_WDT is not set -# CONFIG_IE6XX_WDT is not set -# CONFIG_ITCO_WDT is not set -# CONFIG_IT8712F_WDT is not set -# CONFIG_IT87_WDT is not set -# CONFIG_HP_WATCHDOG is not set -# CONFIG_SC1200_WDT is not set -# CONFIG_PC87413_WDT is not set -# CONFIG_NV_TCO is not set -# CONFIG_60XX_WDT is not set -# CONFIG_CPU5_WDT is not set -# CONFIG_SMSC_SCH311X_WDT is not set -# CONFIG_SMSC37B787_WDT is not set -# CONFIG_TQMX86_WDT is not set -# CONFIG_VIA_WDT is not set -# CONFIG_W83627HF_WDT is not set -# CONFIG_W83877F_WDT is not set -# CONFIG_W83977F_WDT is not set -# CONFIG_MACHZ_WDT is not set -# CONFIG_SBC_EPX_C3_WATCHDOG is not set -# CONFIG_NI903X_WDT is not set -# CONFIG_NIC7018_WDT is not set - -# -# PCI-based Watchdog Cards -# -# CONFIG_PCIPCWATCHDOG is not set -# CONFIG_WDTPCI is not set - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y -# CONFIG_SSB is not set -CONFIG_BCMA_POSSIBLE=y -# CONFIG_BCMA is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_AS3711 is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_BCM590XX is not set -# CONFIG_MFD_BD9571MWV is not set -# CONFIG_MFD_AXP20X_I2C is not set -# CONFIG_MFD_MADERA is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_DA9052_I2C is not set -# CONFIG_MFD_DA9055 is not set -# CONFIG_MFD_DA9062 is not set -# CONFIG_MFD_DA9063 is not set -# CONFIG_MFD_DA9150 is not set -# CONFIG_MFD_DLN2 is not set -# CONFIG_MFD_MC13XXX_I2C is not set -# CONFIG_MFD_MP2629 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set -# CONFIG_LPC_ICH is not set -# CONFIG_LPC_SCH is not set -# CONFIG_MFD_INTEL_LPSS_ACPI is not set -# CONFIG_MFD_INTEL_LPSS_PCI is not set -# CONFIG_MFD_INTEL_PMT is not set -# CONFIG_MFD_IQS62X is not set -# CONFIG_MFD_JANZ_CMODIO is not set -# CONFIG_MFD_KEMPLD is not set -# CONFIG_MFD_88PM800 is not set -# CONFIG_MFD_88PM805 is not set -# CONFIG_MFD_88PM860X is not set -# CONFIG_MFD_MAX14577 is not set -# CONFIG_MFD_MAX77693 is not set -# CONFIG_MFD_MAX77843 is not set -# CONFIG_MFD_MAX8907 is not set -# CONFIG_MFD_MAX8925 is not set -# CONFIG_MFD_MAX8997 is not set -# CONFIG_MFD_MAX8998 is not set -# CONFIG_MFD_MT6360 is not set -# CONFIG_MFD_MT6397 is not set -# CONFIG_MFD_MENF21BMC is not set -# CONFIG_MFD_VIPERBOARD is not set -# CONFIG_MFD_RETU is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_RDC321X is not set -# CONFIG_MFD_RT5033 is not set -# CONFIG_MFD_RC5T583 is not set -# CONFIG_MFD_SEC_CORE is not set -# CONFIG_MFD_SI476X_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_SKY81452 is not set -# CONFIG_MFD_SYSCON is not set -# CONFIG_MFD_TI_AM335X_TSCADC is not set -# CONFIG_MFD_LP3943 is not set -# CONFIG_MFD_LP8788 is not set -# CONFIG_MFD_TI_LMU is not set -# CONFIG_MFD_PALMAS is not set -# CONFIG_TPS6105X is not set -# CONFIG_TPS6507X is not set -# CONFIG_MFD_TPS65086 is not set -# CONFIG_MFD_TPS65090 is not set -# CONFIG_MFD_TI_LP873X is not set -# CONFIG_MFD_TPS6586X is not set -# CONFIG_MFD_TPS65912_I2C is not set -# CONFIG_MFD_TPS80031 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_TWL6040_CORE is not set -# CONFIG_MFD_WL1273_CORE is not set -# CONFIG_MFD_LM3533 is not set -# CONFIG_MFD_TQMX86 is not set -# CONFIG_MFD_VX855 is not set -# CONFIG_MFD_ARIZONA_I2C is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X_I2C is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_WM8994 is not set -# CONFIG_MFD_ATC260X_I2C is not set -# end of Multifunction device drivers - -# CONFIG_REGULATOR is not set CONFIG_RC_CORE=y -CONFIG_RC_MAP=y -# CONFIG_LIRC is not set CONFIG_RC_DECODERS=y CONFIG_IR_NEC_DECODER=y CONFIG_IR_RC5_DECODER=y @@ -3075,1852 +409,140 @@ CONFIG_IR_SANYO_DECODER=y CONFIG_IR_SHARP_DECODER=y CONFIG_IR_MCE_KBD_DECODER=y CONFIG_IR_XMP_DECODER=y -# CONFIG_IR_IMON_DECODER is not set -# CONFIG_IR_RCMM_DECODER is not set -# CONFIG_RC_DEVICES is not set -# CONFIG_MEDIA_CEC_SUPPORT is not set -# CONFIG_MEDIA_SUPPORT is not set - -# -# Graphics support -# CONFIG_AGP=y CONFIG_AGP_AMD64=y CONFIG_AGP_INTEL=y -# CONFIG_AGP_SIS is not set -# CONFIG_AGP_VIA is not set -CONFIG_INTEL_GTT=y -CONFIG_VGA_ARB=y -CONFIG_VGA_ARB_MAX_GPUS=16 -# CONFIG_VGA_SWITCHEROO is not set CONFIG_DRM=m -# CONFIG_DRM_DP_AUX_CHARDEV is not set -# CONFIG_DRM_DEBUG_SELFTEST is not set -CONFIG_DRM_KMS_HELPER=m -# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set -# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set -# CONFIG_DRM_DP_CEC is not set -CONFIG_DRM_TTM=m -CONFIG_DRM_VRAM_HELPER=m -CONFIG_DRM_TTM_HELPER=m -CONFIG_DRM_SCHED=m - -# -# I2C encoder or helper chips -# -# CONFIG_DRM_I2C_CH7006 is not set -# CONFIG_DRM_I2C_SIL164 is not set -# CONFIG_DRM_I2C_NXP_TDA998X is not set -# CONFIG_DRM_I2C_NXP_TDA9950 is not set -# end of I2C encoder or helper chips - -# -# ARM devices -# -# end of ARM devices - -# CONFIG_DRM_RADEON is not set CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_CIK=y -CONFIG_DRM_AMDGPU_USERPTR=y - -# -# ACP (Audio CoProcessor) Configuration -# -# CONFIG_DRM_AMD_ACP is not set -# end of ACP (Audio CoProcessor) Configuration - -# -# Display Engine Configuration -# -CONFIG_DRM_AMD_DC=y -CONFIG_DRM_AMD_DC_DCN=y -# CONFIG_DRM_AMD_DC_HDCP is not set -# CONFIG_DRM_AMD_DC_SI is not set -# CONFIG_DEBUG_KERNEL_DC is not set -# CONFIG_DRM_AMD_SECURE_DISPLAY is not set -# end of Display Engine Configuration - CONFIG_HSA_AMD=y -CONFIG_HSA_AMD_SVM=y -# CONFIG_DRM_NOUVEAU is not set -# CONFIG_DRM_I915 is not set -# CONFIG_DRM_VGEM is not set -# CONFIG_DRM_VKMS is not set -# CONFIG_DRM_VMWGFX is not set -# CONFIG_DRM_GMA500 is not set -# CONFIG_DRM_UDL is not set CONFIG_DRM_AST=m -# CONFIG_DRM_MGAG200 is not set -# CONFIG_DRM_QXL is not set -# CONFIG_DRM_BOCHS is not set -# CONFIG_DRM_VIRTIO_GPU is not set -CONFIG_DRM_PANEL=y - -# -# Display Panels -# -# end of Display Panels - -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_PANEL_BRIDGE=y - -# -# Display Interface Bridges -# -# CONFIG_DRM_ANALOGIX_ANX78XX is not set -# end of Display Interface Bridges - -# CONFIG_DRM_ETNAVIV is not set -# CONFIG_DRM_CIRRUS_QEMU is not set -# CONFIG_DRM_GM12U320 is not set -# CONFIG_DRM_SIMPLEDRM is not set -# CONFIG_DRM_VBOXVIDEO is not set -# CONFIG_DRM_GUD is not set -# CONFIG_DRM_LEGACY is not set -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m - -# -# Frame buffer Devices -# -CONFIG_FB_CMDLINE=y -CONFIG_FB_NOTIFY=y CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -CONFIG_FB_CFB_FILLRECT=m -CONFIG_FB_CFB_COPYAREA=m -CONFIG_FB_CFB_IMAGEBLIT=m -CONFIG_FB_SYS_FILLRECT=m -CONFIG_FB_SYS_COPYAREA=m -CONFIG_FB_SYS_IMAGEBLIT=m -# CONFIG_FB_FOREIGN_ENDIAN is not set -CONFIG_FB_SYS_FOPS=m -CONFIG_FB_DEFERRED_IO=y -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_CIRRUS is not set -# CONFIG_FB_PM2 is not set -# CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_ARC is not set -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_IMSTT is not set -# CONFIG_FB_VGA16 is not set -# CONFIG_FB_VESA is not set -# CONFIG_FB_EFI is not set -# CONFIG_FB_N411 is not set -# CONFIG_FB_HGA is not set -# CONFIG_FB_OPENCORES is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_NVIDIA is not set -# CONFIG_FB_RIVA is not set -# CONFIG_FB_I740 is not set -# CONFIG_FB_LE80578 is not set -# CONFIG_FB_INTEL is not set -# CONFIG_FB_MATROX is not set -# CONFIG_FB_RADEON is not set -# CONFIG_FB_ATY128 is not set -# CONFIG_FB_ATY is not set -# CONFIG_FB_S3 is not set -# CONFIG_FB_SAVAGE is not set -# CONFIG_FB_SIS is not set -# CONFIG_FB_NEOMAGIC is not set -# CONFIG_FB_KYRO is not set -# CONFIG_FB_3DFX is not set -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_VT8623 is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_ARK is not set -# CONFIG_FB_PM3 is not set -# CONFIG_FB_CARMINE is not set -# CONFIG_FB_SMSCUFX is not set -# CONFIG_FB_UDL is not set -# CONFIG_FB_IBM_GXT4500 is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_SIMPLE is not set -# CONFIG_FB_SM712 is not set -# end of Frame buffer Devices - -# -# Backlight & LCD device support -# -# CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_APPLE is not set -# CONFIG_BACKLIGHT_QCOM_WLED is not set -# CONFIG_BACKLIGHT_SAHARA is not set -# CONFIG_BACKLIGHT_ADP8860 is not set -# CONFIG_BACKLIGHT_ADP8870 is not set -# CONFIG_BACKLIGHT_LM3639 is not set -# CONFIG_BACKLIGHT_LV5207LP is not set -# CONFIG_BACKLIGHT_BD6107 is not set -# CONFIG_BACKLIGHT_ARCXCNN is not set -# end of Backlight & LCD device support - -CONFIG_HDMI=y - -# -# Console display driver support -# -CONFIG_VGA_CONSOLE=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_DUMMY_CONSOLE_COLUMNS=80 -CONFIG_DUMMY_CONSOLE_ROWS=25 CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set -# end of Console display driver support - -# CONFIG_LOGO is not set -# end of Graphics support - -# CONFIG_SOUND is not set - -# -# HID support -# -CONFIG_HID=y CONFIG_HID_BATTERY_STRENGTH=y CONFIG_HIDRAW=y -# CONFIG_UHID is not set -CONFIG_HID_GENERIC=y - -# -# Special HID drivers -# CONFIG_HID_A4TECH=y -# CONFIG_HID_ACCUTOUCH is not set -# CONFIG_HID_ACRUX is not set CONFIG_HID_APPLE=y -# CONFIG_HID_APPLEIR is not set -# CONFIG_HID_ASUS is not set -# CONFIG_HID_AUREAL is not set CONFIG_HID_BELKIN=y -# CONFIG_HID_BETOP_FF is not set -# CONFIG_HID_BIGBEN_FF is not set CONFIG_HID_CHERRY=y CONFIG_HID_CHICONY=y -# CONFIG_HID_CORSAIR is not set -# CONFIG_HID_COUGAR is not set -# CONFIG_HID_MACALLY is not set -# CONFIG_HID_CMEDIA is not set -# CONFIG_HID_CREATIVE_SB0540 is not set CONFIG_HID_CYPRESS=y -# CONFIG_HID_DRAGONRISE is not set -# CONFIG_HID_EMS_FF is not set -# CONFIG_HID_ELAN is not set -# CONFIG_HID_ELECOM is not set -# CONFIG_HID_ELO is not set CONFIG_HID_EZKEY=y -# CONFIG_HID_FT260 is not set -# CONFIG_HID_GEMBIRD is not set -# CONFIG_HID_GFRM is not set -# CONFIG_HID_GLORIOUS is not set -# CONFIG_HID_HOLTEK is not set -# CONFIG_HID_VIVALDI is not set -# CONFIG_HID_GT683R is not set -# CONFIG_HID_KEYTOUCH is not set CONFIG_HID_KYE=y -# CONFIG_HID_UCLOGIC is not set -# CONFIG_HID_WALTOP is not set -# CONFIG_HID_VIEWSONIC is not set -# CONFIG_HID_GYRATION is not set -# CONFIG_HID_ICADE is not set -# CONFIG_HID_ITE is not set -# CONFIG_HID_JABRA is not set -# CONFIG_HID_TWINHAN is not set CONFIG_HID_KENSINGTON=y -# CONFIG_HID_LCPOWER is not set -# CONFIG_HID_LED is not set -# CONFIG_HID_LENOVO is not set CONFIG_HID_LOGITECH=y -# CONFIG_HID_LOGITECH_DJ is not set -# CONFIG_HID_LOGITECH_HIDPP is not set -# CONFIG_LOGITECH_FF is not set -# CONFIG_LOGIRUMBLEPAD2_FF is not set -# CONFIG_LOGIG940_FF is not set -# CONFIG_LOGIWHEELS_FF is not set -# CONFIG_HID_MAGICMOUSE is not set -# CONFIG_HID_MALTRON is not set -# CONFIG_HID_MAYFLASH is not set -# CONFIG_HID_REDRAGON is not set CONFIG_HID_MICROSOFT=y CONFIG_HID_MONTEREY=y -# CONFIG_HID_MULTITOUCH is not set -# CONFIG_HID_NTI is not set -# CONFIG_HID_NTRIG is not set -# CONFIG_HID_ORTEK is not set -# CONFIG_HID_PANTHERLORD is not set -# CONFIG_HID_PENMOUNT is not set -# CONFIG_HID_PETALYNX is not set -# CONFIG_HID_PICOLCD is not set CONFIG_HID_PLANTRONICS=y -# CONFIG_HID_PLAYSTATION is not set -# CONFIG_HID_PRIMAX is not set -# CONFIG_HID_RETRODE is not set -# CONFIG_HID_ROCCAT is not set -# CONFIG_HID_SAITEK is not set -# CONFIG_HID_SAMSUNG is not set -# CONFIG_HID_SEMITEK is not set -# CONFIG_HID_SONY is not set -# CONFIG_HID_SPEEDLINK is not set -# CONFIG_HID_STEAM is not set -# CONFIG_HID_STEELSERIES is not set -# CONFIG_HID_SUNPLUS is not set -# CONFIG_HID_RMI is not set -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TIVO is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THINGM is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_UDRAW_PS3 is not set -# CONFIG_HID_WACOM is not set -# CONFIG_HID_WIIMOTE is not set -# CONFIG_HID_XINMO is not set -# CONFIG_HID_ZEROPLUS is not set -# CONFIG_HID_ZYDACRON is not set -# CONFIG_HID_SENSOR_HUB is not set -# CONFIG_HID_ALPS is not set -# end of Special HID drivers - -# -# USB HID support -# -CONFIG_USB_HID=y CONFIG_HID_PID=y CONFIG_USB_HIDDEV=y -# end of USB HID support - -# -# I2C HID support -# -# CONFIG_I2C_HID_ACPI is not set -# end of I2C HID support - -# -# Intel ISH HID support -# -# CONFIG_INTEL_ISH_HID is not set -# end of Intel ISH HID support - -# -# AMD SFH HID Support -# -# CONFIG_AMD_SFH_HID is not set -# end of AMD SFH HID Support -# end of HID support - -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_COMMON=y -# CONFIG_USB_LED_TRIG is not set -# CONFIG_USB_ULPI_BUS is not set -CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y -CONFIG_USB_PCI=y -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set - -# -# Miscellaneous USB options -# -CONFIG_USB_DEFAULT_PERSIST=y -# CONFIG_USB_FEW_INIT_RETRIES is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_PRODUCTLIST is not set -# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set -# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set -CONFIG_USB_AUTOSUSPEND_DELAY=2 -# CONFIG_USB_MON is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set CONFIG_USB_XHCI_HCD=y -# CONFIG_USB_XHCI_DBGCAP is not set -CONFIG_USB_XHCI_PCI=y -# CONFIG_USB_XHCI_PCI_RENESAS is not set -# CONFIG_USB_XHCI_PLATFORM is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -CONFIG_USB_EHCI_PCI=y -# CONFIG_USB_EHCI_FSL is not set CONFIG_USB_EHCI_HCD_PLATFORM=y -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_FOTG210_HCD is not set CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PCI=y -# CONFIG_USB_OHCI_HCD_PLATFORM is not set CONFIG_USB_UHCI_HCD=y -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HCD_TEST_MODE is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_REALTEK is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_STORAGE_ENE_UB6250 is not set -# CONFIG_USB_UAS is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USBIP_CORE is not set -# CONFIG_USB_CDNS_SUPPORT is not set -# CONFIG_USB_MUSB_HDRC is not set -# CONFIG_USB_DWC3 is not set -# CONFIG_USB_DWC2 is not set -# CONFIG_USB_CHIPIDEA is not set -# CONFIG_USB_ISP1760 is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_APPLE_MFI_FASTCHARGE is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_EHSET_TEST_FIXTURE is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_YUREX is not set -# CONFIG_USB_EZUSB_FX2 is not set -# CONFIG_USB_HUB_USB251XB is not set -# CONFIG_USB_HSIC_USB3503 is not set -# CONFIG_USB_HSIC_USB4604 is not set -# CONFIG_USB_LINK_LAYER_TEST is not set - -# -# USB Physical Layer drivers -# -# CONFIG_NOP_USB_XCEIV is not set -# CONFIG_USB_ISP1301 is not set -# end of USB Physical Layer drivers - -# CONFIG_USB_GADGET is not set -# CONFIG_TYPEC is not set -# CONFIG_USB_ROLE_SWITCH is not set -# CONFIG_MMC is not set -# CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y -# CONFIG_LEDS_CLASS_FLASH is not set -# CONFIG_LEDS_CLASS_MULTICOLOR is not set -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set - -# -# LED drivers -# -# CONFIG_LEDS_APU is not set -# CONFIG_LEDS_LM3530 is not set -# CONFIG_LEDS_LM3532 is not set -# CONFIG_LEDS_LM3642 is not set -# CONFIG_LEDS_PCA9532 is not set -# CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_CLEVO_MAIL is not set -# CONFIG_LEDS_PCA955X is not set -# CONFIG_LEDS_PCA963X is not set -# CONFIG_LEDS_BD2802 is not set -# CONFIG_LEDS_INTEL_SS4200 is not set -# CONFIG_LEDS_TCA6507 is not set -# CONFIG_LEDS_TLC591XX is not set -# CONFIG_LEDS_LM355x is not set - -# -# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) -# -# CONFIG_LEDS_BLINKM is not set -# CONFIG_LEDS_MLXCPLD is not set -# CONFIG_LEDS_MLXREG is not set -# CONFIG_LEDS_USER is not set -# CONFIG_LEDS_NIC78BX is not set - -# -# Flash and Torch LED drivers -# - -# -# LED Triggers -# CONFIG_LEDS_TRIGGERS=y -# CONFIG_LEDS_TRIGGER_TIMER is not set -# CONFIG_LEDS_TRIGGER_ONESHOT is not set -# CONFIG_LEDS_TRIGGER_DISK is not set -# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set -# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set -# CONFIG_LEDS_TRIGGER_CPU is not set -# CONFIG_LEDS_TRIGGER_ACTIVITY is not set -# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set - -# -# iptables trigger is under Netfilter config (LED target) -# -# CONFIG_LEDS_TRIGGER_TRANSIENT is not set -# CONFIG_LEDS_TRIGGER_CAMERA is not set -# CONFIG_LEDS_TRIGGER_PANIC is not set -# CONFIG_LEDS_TRIGGER_NETDEV is not set -# CONFIG_LEDS_TRIGGER_PATTERN is not set -# CONFIG_LEDS_TRIGGER_AUDIO is not set -# CONFIG_LEDS_TRIGGER_TTY is not set -# CONFIG_ACCESSIBILITY is not set -# CONFIG_INFINIBAND is not set -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -# CONFIG_EDAC is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_MC146818_LIB=y CONFIG_RTC_CLASS=y # CONFIG_RTC_HCTOSYS is not set -CONFIG_RTC_SYSTOHC=y -CONFIG_RTC_SYSTOHC_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set -CONFIG_RTC_NVMEM=y - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_ABB5ZES3 is not set -# CONFIG_RTC_DRV_ABEOZ9 is not set -# CONFIG_RTC_DRV_ABX80X is not set -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_ISL12022 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8523 is not set -# CONFIG_RTC_DRV_PCF85063 is not set -# CONFIG_RTC_DRV_PCF85363 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_BQ32K is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8010 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set -# CONFIG_RTC_DRV_EM3027 is not set -# CONFIG_RTC_DRV_RV3028 is not set -# CONFIG_RTC_DRV_RV3032 is not set -# CONFIG_RTC_DRV_RV8803 is not set -# CONFIG_RTC_DRV_SD3078 is not set - -# -# SPI RTC drivers -# -CONFIG_RTC_I2C_AND_SPI=y - -# -# SPI and I2C RTC drivers -# -# CONFIG_RTC_DRV_DS3232 is not set -# CONFIG_RTC_DRV_PCF2127 is not set -# CONFIG_RTC_DRV_RV3029C2 is not set -# CONFIG_RTC_DRV_RX6110 is not set - -# -# Platform RTC drivers -# -CONFIG_RTC_DRV_CMOS=y -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1685_FAMILY is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_DS2404 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_RTC_DRV_FTRTC010 is not set - -# -# HID Sensor RTC drivers -# -# CONFIG_RTC_DRV_GOLDFISH is not set CONFIG_DMADEVICES=y -# CONFIG_DMADEVICES_DEBUG is not set - -# -# DMA Devices -# -CONFIG_DMA_ENGINE=y -CONFIG_DMA_ACPI=y -# CONFIG_ALTERA_MSGDMA is not set -# CONFIG_INTEL_IDMA64 is not set -# CONFIG_INTEL_IDXD is not set -# CONFIG_INTEL_IOATDMA is not set -# CONFIG_PLX_DMA is not set -# CONFIG_QCOM_HIDMA_MGMT is not set -# CONFIG_QCOM_HIDMA is not set -CONFIG_DW_DMAC_CORE=y -# CONFIG_DW_DMAC is not set -CONFIG_DW_DMAC_PCI=y -# CONFIG_DW_EDMA is not set -# CONFIG_DW_EDMA_PCIE is not set -# CONFIG_SF_PDMA is not set -# CONFIG_INTEL_LDMA is not set - -# -# DMA Clients -# -# CONFIG_ASYNC_TX_DMA is not set -# CONFIG_DMATEST is not set - -# -# DMABUF options -# -CONFIG_SYNC_FILE=y -# CONFIG_SW_SYNC is not set -# CONFIG_UDMABUF is not set -# CONFIG_DMABUF_MOVE_NOTIFY is not set -# CONFIG_DMABUF_DEBUG is not set -# CONFIG_DMABUF_SELFTESTS is not set -# CONFIG_DMABUF_HEAPS is not set -# end of DMABUF options - -# CONFIG_AUXDISPLAY is not set -# CONFIG_PANEL is not set -# CONFIG_UIO is not set -# CONFIG_VFIO is not set -# CONFIG_VIRT_DRIVERS is not set -CONFIG_VIRTIO_MENU=y -# CONFIG_VIRTIO_PCI is not set -# CONFIG_VIRTIO_MMIO is not set -# CONFIG_VDPA is not set -CONFIG_VHOST_MENU=y -# CONFIG_VHOST_NET is not set -# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set - -# -# Microsoft Hyper-V guest support -# -# CONFIG_HYPERV is not set -# end of Microsoft Hyper-V guest support - -# CONFIG_GREYBUS is not set -# CONFIG_COMEDI is not set -# CONFIG_STAGING is not set # CONFIG_X86_PLATFORM_DEVICES is not set -CONFIG_PMC_ATOM=y -# CONFIG_CHROME_PLATFORMS is not set -# CONFIG_MELLANOX_PLATFORM is not set -CONFIG_SURFACE_PLATFORMS=y -# CONFIG_SURFACE_3_POWER_OPREGION is not set -# CONFIG_SURFACE_GPE is not set -# CONFIG_SURFACE_PRO3_BUTTON is not set -CONFIG_HAVE_CLK=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_MAX9485 is not set -# CONFIG_COMMON_CLK_SI5341 is not set -# CONFIG_COMMON_CLK_SI5351 is not set -# CONFIG_COMMON_CLK_SI544 is not set -# CONFIG_COMMON_CLK_CDCE706 is not set -# CONFIG_COMMON_CLK_CS2000_CP is not set -# CONFIG_XILINX_VCU is not set -# CONFIG_HWSPINLOCK is not set - -# -# Clock Source drivers -# -CONFIG_CLKEVT_I8253=y -CONFIG_I8253_LOCK=y -CONFIG_CLKBLD_I8253=y -# end of Clock Source drivers - -CONFIG_MAILBOX=y -CONFIG_PCC=y -# CONFIG_ALTERA_MBOX is not set -CONFIG_IOMMU_IOVA=y -CONFIG_IOASID=y -CONFIG_IOMMU_API=y -CONFIG_IOMMU_SUPPORT=y - -# -# Generic IOMMU Pagetable Support -# -CONFIG_IOMMU_IO_PGTABLE=y -# end of Generic IOMMU Pagetable Support - -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set -CONFIG_IOMMU_DMA=y CONFIG_AMD_IOMMU=y -CONFIG_AMD_IOMMU_V2=m -CONFIG_DMAR_TABLE=y CONFIG_INTEL_IOMMU=y -# CONFIG_INTEL_IOMMU_SVM is not set -CONFIG_INTEL_IOMMU_DEFAULT_ON=y -CONFIG_INTEL_IOMMU_FLOPPY_WA=y # CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set -# CONFIG_IRQ_REMAP is not set - -# -# Remoteproc drivers -# -# CONFIG_REMOTEPROC is not set -# end of Remoteproc drivers - -# -# Rpmsg drivers -# -# CONFIG_RPMSG_QCOM_GLINK_RPM is not set -# CONFIG_RPMSG_VIRTIO is not set -# end of Rpmsg drivers - -# CONFIG_SOUNDWIRE is not set - -# -# SOC (System On Chip) specific Drivers -# - -# -# Amlogic SoC drivers -# -# end of Amlogic SoC drivers - -# -# Broadcom SoC drivers -# -# end of Broadcom SoC drivers - -# -# NXP/Freescale QorIQ SoC drivers -# -# end of NXP/Freescale QorIQ SoC drivers - -# -# i.MX SoC drivers -# -# end of i.MX SoC drivers - -# -# Enable LiteX SoC Builder specific drivers -# -# end of Enable LiteX SoC Builder specific drivers - -# -# Qualcomm SoC drivers -# -# end of Qualcomm SoC drivers - -# CONFIG_SOC_TI is not set - -# -# Xilinx SoC drivers -# -# end of Xilinx SoC drivers -# end of SOC (System On Chip) specific Drivers - -# CONFIG_PM_DEVFREQ is not set -# CONFIG_EXTCON is not set -# CONFIG_MEMORY is not set -# CONFIG_IIO is not set -# CONFIG_NTB is not set -# CONFIG_VME_BUS is not set -# CONFIG_PWM is not set - -# -# IRQ chip support -# -# end of IRQ chip support - -# CONFIG_IPACK_BUS is not set -# CONFIG_RESET_CONTROLLER is not set - -# -# PHY Subsystem -# -# CONFIG_GENERIC_PHY is not set -# CONFIG_USB_LGM_PHY is not set -# CONFIG_BCM_KONA_USB2_PHY is not set -# CONFIG_PHY_PXA_28NM_HSIC is not set -# CONFIG_PHY_PXA_28NM_USB2 is not set -# CONFIG_PHY_INTEL_LGM_EMMC is not set -# end of PHY Subsystem - -# CONFIG_POWERCAP is not set -# CONFIG_MCB is not set - -# -# Performance monitor support -# -# end of Performance monitor support - -CONFIG_RAS=y -# CONFIG_RAS_CEC is not set -# CONFIG_USB4 is not set - -# -# Android -# -# CONFIG_ANDROID is not set -# end of Android - -# CONFIG_LIBNVDIMM is not set CONFIG_DAX=y -# CONFIG_DEV_DAX is not set -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -# CONFIG_NVMEM_RMEM is not set - -# -# HW tracing support -# -# CONFIG_STM is not set -# CONFIG_INTEL_TH is not set -# end of HW tracing support - -# CONFIG_FPGA is not set -# CONFIG_TEE is not set -# CONFIG_UNISYS_VISORBUS is not set -# CONFIG_SIOX is not set -# CONFIG_SLIMBUS is not set -# CONFIG_INTERCONNECT is not set -# CONFIG_COUNTER is not set -# CONFIG_MOST is not set -# end of Device Drivers - -# -# File systems -# -CONFIG_DCACHE_WORD_ACCESS=y CONFIG_VALIDATE_FS_PARSER=y -CONFIG_FS_IOMAP=y -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set CONFIG_EXT4_FS=y -CONFIG_EXT4_USE_FOR_EXT2=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y -# CONFIG_EXT4_DEBUG is not set -CONFIG_JBD2=y -# CONFIG_JBD2_DEBUG is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set CONFIG_XFS_FS=y -CONFIG_XFS_SUPPORT_V4=y CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y CONFIG_XFS_RT=y -# CONFIG_XFS_ONLINE_SCRUB is not set CONFIG_XFS_WARN=y -# CONFIG_XFS_DEBUG is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -# CONFIG_F2FS_FS is not set -# CONFIG_FS_DAX is not set -CONFIG_FS_POSIX_ACL=y -CONFIG_EXPORTFS=y -# CONFIG_EXPORTFS_BLOCK_OPS is not set -CONFIG_FILE_LOCKING=y -CONFIG_MANDATORY_FILE_LOCKING=y -# CONFIG_FS_ENCRYPTION is not set -# CONFIG_FS_VERITY is not set -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY_USER=y CONFIG_FANOTIFY=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set -# CONFIG_QUOTA_DEBUG is not set -CONFIG_QUOTA_TREE=y -# CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y CONFIG_AUTOFS4_FS=y -CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=m CONFIG_CUSE=m -# CONFIG_VIRTIO_FS is not set CONFIG_OVERLAY_FS=y -# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set -CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y -# CONFIG_OVERLAY_FS_INDEX is not set -# CONFIG_OVERLAY_FS_XINO_AUTO is not set -# CONFIG_OVERLAY_FS_METACOPY is not set - -# -# Caches -# -CONFIG_NETFS_SUPPORT=y -# CONFIG_NETFS_STATS is not set CONFIG_FSCACHE=y -# CONFIG_FSCACHE_STATS is not set -# CONFIG_FSCACHE_HISTOGRAM is not set -# CONFIG_FSCACHE_DEBUG is not set -# CONFIG_FSCACHE_OBJECT_LIST is not set -# CONFIG_CACHEFILES is not set -# end of Caches - -# -# CD-ROM/DVD Filesystems -# CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y -# CONFIG_UDF_FS is not set -# end of CD-ROM/DVD Filesystems - -# -# DOS/FAT/EXFAT/NT Filesystems -# -CONFIG_FAT_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_FAT_DEFAULT_UTF8 is not set -# CONFIG_EXFAT_FS is not set CONFIG_NTFS_FS=y -# CONFIG_NTFS_DEBUG is not set CONFIG_NTFS_RW=y -# end of DOS/FAT/EXFAT/NT Filesystems - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y -CONFIG_PROC_VMCORE=y -# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PROC_CHILDREN=y -CONFIG_PROC_PID_ARCH_STATUS=y -CONFIG_KERNFS=y -CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y -CONFIG_TMPFS_XATTR=y -# CONFIG_TMPFS_INODE64 is not set CONFIG_HUGETLBFS=y -CONFIG_HUGETLB_PAGE=y -CONFIG_MEMFD_CREATE=y -CONFIG_ARCH_HAS_GIGANTIC_PAGE=y CONFIG_CONFIGFS_FS=y # CONFIG_EFIVAR_FS is not set -# end of Pseudo filesystems - -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ORANGEFS_FS is not set -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_ECRYPT_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX6FS_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_PSTORE=y -CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 -CONFIG_PSTORE_DEFLATE_COMPRESS=y -# CONFIG_PSTORE_LZO_COMPRESS is not set -# CONFIG_PSTORE_LZ4_COMPRESS is not set -# CONFIG_PSTORE_LZ4HC_COMPRESS is not set -# CONFIG_PSTORE_842_COMPRESS is not set -# CONFIG_PSTORE_ZSTD_COMPRESS is not set -CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" -# CONFIG_PSTORE_CONSOLE is not set -# CONFIG_PSTORE_PMSG is not set -# CONFIG_PSTORE_FTRACE is not set -# CONFIG_PSTORE_RAM is not set -# CONFIG_PSTORE_BLK is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -# CONFIG_EROFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y -CONFIG_NFS_V2=y -CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y -# CONFIG_NFS_SWAP is not set -# CONFIG_NFS_V4_1 is not set CONFIG_ROOT_NFS=y -# CONFIG_NFS_FSCACHE is not set -# CONFIG_NFS_USE_LEGACY_DNS is not set -CONFIG_NFS_USE_KERNEL_DNS=y -CONFIG_NFS_DISABLE_UDP_SUPPORT=y -# CONFIG_NFSD is not set -CONFIG_GRACE_PERIOD=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -# CONFIG_SUNRPC_DEBUG is not set -# CONFIG_CEPH_FS is not set CONFIG_CIFS=y # CONFIG_CIFS_STATS2 is not set -CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y -# CONFIG_CIFS_WEAK_PW_HASH is not set -# CONFIG_CIFS_UPCALL is not set -# CONFIG_CIFS_XATTR is not set -CONFIG_CIFS_DEBUG=y -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set -# CONFIG_CIFS_DFS_UPCALL is not set -# CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y -# CONFIG_CIFS_ROOT is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -CONFIG_NLS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_MAC_ROMAN is not set -# CONFIG_NLS_MAC_CELTIC is not set -# CONFIG_NLS_MAC_CENTEURO is not set -# CONFIG_NLS_MAC_CROATIAN is not set -# CONFIG_NLS_MAC_CYRILLIC is not set -# CONFIG_NLS_MAC_GAELIC is not set -# CONFIG_NLS_MAC_GREEK is not set -# CONFIG_NLS_MAC_ICELAND is not set -# CONFIG_NLS_MAC_INUIT is not set -# CONFIG_NLS_MAC_ROMANIAN is not set -# CONFIG_NLS_MAC_TURKISH is not set CONFIG_NLS_UTF8=y -# CONFIG_DLM is not set -# CONFIG_UNICODE is not set -CONFIG_IO_WQ=y -# end of File systems - -# -# Security options -# -CONFIG_KEYS=y -# CONFIG_KEYS_REQUEST_CACHE is not set -# CONFIG_PERSISTENT_KEYRINGS is not set -# CONFIG_ENCRYPTED_KEYS is not set -# CONFIG_KEY_DH_OPERATIONS is not set -# CONFIG_SECURITY_DMESG_RESTRICT is not set CONFIG_SECURITY=y -CONFIG_SECURITY_WRITABLE_HOOKS=y -# CONFIG_SECURITYFS is not set CONFIG_SECURITY_NETWORK=y -CONFIG_PAGE_TABLE_ISOLATION=y -# CONFIG_SECURITY_NETWORK_XFRM is not set -# CONFIG_SECURITY_PATH is not set -# CONFIG_INTEL_TXT is not set -CONFIG_LSM_MMAP_MIN_ADDR=65536 -CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y -# CONFIG_HARDENED_USERCOPY is not set -# CONFIG_FORTIFY_SOURCE is not set -# CONFIG_STATIC_USERMODEHELPER is not set CONFIG_SECURITY_SELINUX=y CONFIG_SECURITY_SELINUX_BOOTPARAM=y CONFIG_SECURITY_SELINUX_DISABLE=y -CONFIG_SECURITY_SELINUX_DEVELOP=y -CONFIG_SECURITY_SELINUX_AVC_STATS=y CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 -CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 -CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 -# CONFIG_SECURITY_SMACK is not set -# CONFIG_SECURITY_TOMOYO is not set -# CONFIG_SECURITY_APPARMOR is not set -# CONFIG_SECURITY_LOADPIN is not set -# CONFIG_SECURITY_YAMA is not set -# CONFIG_SECURITY_SAFESETID is not set -# CONFIG_SECURITY_LOCKDOWN_LSM is not set -# CONFIG_SECURITY_LANDLOCK is not set -CONFIG_INTEGRITY=y -# CONFIG_INTEGRITY_SIGNATURE is not set -CONFIG_INTEGRITY_AUDIT=y -# CONFIG_IMA is not set -# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set -# CONFIG_EVM is not set -CONFIG_DEFAULT_SECURITY_SELINUX=y -# CONFIG_DEFAULT_SECURITY_DAC is not set CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" - -# -# Kernel hardening options -# - -# -# Memory initialization -# -CONFIG_INIT_STACK_NONE=y -# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set -# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set -# end of Memory initialization -# end of Kernel hardening options -# end of Security options - -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_SKCIPHER=y -CONFIG_CRYPTO_SKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_AKCIPHER2=y -CONFIG_CRYPTO_AKCIPHER=y -CONFIG_CRYPTO_KPP2=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_USER is not set -CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y -CONFIG_CRYPTO_GF128MUL=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_NULL2=y -# CONFIG_CRYPTO_PCRYPT is not set -# CONFIG_CRYPTO_CRYPTD is not set CONFIG_CRYPTO_AUTHENC=y -# CONFIG_CRYPTO_TEST is not set - -# -# Public-key cryptography -# -CONFIG_CRYPTO_RSA=y -# CONFIG_CRYPTO_DH is not set -# CONFIG_CRYPTO_ECDH is not set -# CONFIG_CRYPTO_ECDSA is not set -# CONFIG_CRYPTO_ECRDSA is not set -# CONFIG_CRYPTO_SM2 is not set -# CONFIG_CRYPTO_CURVE25519 is not set -# CONFIG_CRYPTO_CURVE25519_X86 is not set - -# -# Authenticated Encryption with Associated Data -# -CONFIG_CRYPTO_CCM=y -CONFIG_CRYPTO_GCM=y -# CONFIG_CRYPTO_CHACHA20POLY1305 is not set -# CONFIG_CRYPTO_AEGIS128 is not set -# CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_ECHAINIV=y - -# -# Block modes -# CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CFB is not set -CONFIG_CRYPTO_CTR=y -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=y -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_OFB is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set -# CONFIG_CRYPTO_KEYWRAP is not set -# CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set -# CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set -# CONFIG_CRYPTO_ADIANTUM is not set -# CONFIG_CRYPTO_ESSIV is not set - -# -# Hash modes -# -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_HMAC=y -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_CRC32C_INTEL is not set -# CONFIG_CRYPTO_CRC32 is not set -# CONFIG_CRYPTO_CRC32_PCLMUL is not set -# CONFIG_CRYPTO_XXHASH is not set -# CONFIG_CRYPTO_BLAKE2B is not set -# CONFIG_CRYPTO_BLAKE2S is not set -# CONFIG_CRYPTO_BLAKE2S_X86 is not set -CONFIG_CRYPTO_CRCT10DIF=y -# CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set -CONFIG_CRYPTO_GHASH=y -# CONFIG_CRYPTO_POLY1305 is not set -# CONFIG_CRYPTO_POLY1305_X86_64 is not set CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD160 is not set CONFIG_CRYPTO_SHA1=y -# CONFIG_CRYPTO_SHA1_SSSE3 is not set -# CONFIG_CRYPTO_SHA256_SSSE3 is not set -# CONFIG_CRYPTO_SHA512_SSSE3 is not set -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -# CONFIG_CRYPTO_SHA3 is not set -# CONFIG_CRYPTO_SM3 is not set -# CONFIG_CRYPTO_STREEBOG is not set -# CONFIG_CRYPTO_WP512 is not set -# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set - -# -# Ciphers -# -CONFIG_CRYPTO_AES=y -# CONFIG_CRYPTO_AES_TI is not set -# CONFIG_CRYPTO_AES_NI_INTEL is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_BLOWFISH_X86_64 is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAMELLIA_X86_64 is not set -# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set -# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_CHACHA20 is not set -# CONFIG_CRYPTO_CHACHA20_X86_64 is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set -# CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set -# CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set -# CONFIG_CRYPTO_SM4 is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_TWOFISH_X86_64 is not set -# CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set -# CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set - -# -# Compression -# -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -# CONFIG_CRYPTO_842 is not set -# CONFIG_CRYPTO_LZ4 is not set -# CONFIG_CRYPTO_LZ4HC is not set -# CONFIG_CRYPTO_ZSTD is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_DRBG_HMAC=y -# CONFIG_CRYPTO_DRBG_HASH is not set -# CONFIG_CRYPTO_DRBG_CTR is not set -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_JITTERENTROPY=y -# CONFIG_CRYPTO_USER_API_HASH is not set -# CONFIG_CRYPTO_USER_API_SKCIPHER is not set -# CONFIG_CRYPTO_USER_API_RNG is not set -# CONFIG_CRYPTO_USER_API_AEAD is not set -CONFIG_CRYPTO_HASH_INFO=y - -# -# Crypto library routines -# -CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=y -# CONFIG_CRYPTO_LIB_BLAKE2S is not set -# CONFIG_CRYPTO_LIB_CHACHA is not set -# CONFIG_CRYPTO_LIB_CURVE25519 is not set -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 -# CONFIG_CRYPTO_LIB_POLY1305 is not set -# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_HW=y -# CONFIG_CRYPTO_DEV_PADLOCK is not set -# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set -# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set -# CONFIG_CRYPTO_DEV_CCP is not set -# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set -# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set -# CONFIG_CRYPTO_DEV_QAT_C62X is not set -# CONFIG_CRYPTO_DEV_QAT_4XXX is not set -# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set -# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set -# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set -# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set -# CONFIG_CRYPTO_DEV_SAFEXCEL is not set -# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set -CONFIG_ASYMMETRIC_KEY_TYPE=y -CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y -CONFIG_X509_CERTIFICATE_PARSER=y -# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set -CONFIG_PKCS7_MESSAGE_PARSER=y -# CONFIG_PKCS7_TEST_KEY is not set -# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set - -# -# Certificates for signature checking -# -CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" -CONFIG_SYSTEM_TRUSTED_KEYRING=y -CONFIG_SYSTEM_TRUSTED_KEYS="" -# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set -# CONFIG_SECONDARY_TRUSTED_KEYRING is not set -# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set -# end of Certificates for signature checking - -CONFIG_BINARY_PRINTF=y - -# -# Library routines -# -# CONFIG_PACKING is not set -CONFIG_BITREVERSE=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_NET_UTILS=y -CONFIG_GENERIC_FIND_FIRST_BIT=y -# CONFIG_CORDIC is not set -# CONFIG_PRIME_NUMBERS is not set -CONFIG_RATIONAL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_IOMAP=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_HAS_FAST_MULTIPLIER=y -CONFIG_ARCH_USE_SYM_ANNOTATIONS=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -CONFIG_CRC_T10DIF=y -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC32_SELFTEST is not set -CONFIG_CRC32_SLICEBY8=y -# CONFIG_CRC32_SLICEBY4 is not set -# CONFIG_CRC32_SARWATE is not set -# CONFIG_CRC32_BIT is not set -# CONFIG_CRC64 is not set -# CONFIG_CRC4 is not set -# CONFIG_CRC7 is not set -CONFIG_LIBCRC32C=y -# CONFIG_CRC8 is not set -CONFIG_XXHASH=y -# CONFIG_RANDOM32_SELFTEST is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_LZ4_DECOMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y -CONFIG_XZ_DEC=y -CONFIG_XZ_DEC_X86=y -CONFIG_XZ_DEC_POWERPC=y -CONFIG_XZ_DEC_IA64=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_SPARC=y -CONFIG_XZ_DEC_BCJ=y -# CONFIG_XZ_DEC_TEST is not set -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_LZMA=y -CONFIG_DECOMPRESS_XZ=y -CONFIG_DECOMPRESS_LZO=y -CONFIG_DECOMPRESS_LZ4=y -CONFIG_DECOMPRESS_ZSTD=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_INTERVAL_TREE=y -CONFIG_XARRAY_MULTI=y -CONFIG_ASSOCIATIVE_ARRAY=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAS_DMA=y -CONFIG_DMA_OPS=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_SWIOTLB=y -# CONFIG_DMA_CMA is not set -# CONFIG_DMA_API_DEBUG is not set -# CONFIG_DMA_MAP_BENCHMARK is not set -CONFIG_SGL_ALLOC=y -CONFIG_IOMMU_HELPER=y -CONFIG_CHECK_SIGNATURE=y -CONFIG_CPU_RMAP=y -CONFIG_DQL=y -CONFIG_GLOB=y -# CONFIG_GLOB_SELFTEST is not set -CONFIG_NLATTR=y -CONFIG_CLZ_TAB=y -# CONFIG_IRQ_POLL is not set -CONFIG_MPILIB=y -CONFIG_OID_REGISTRY=y -CONFIG_UCS2_STRING=y -CONFIG_HAVE_GENERIC_VDSO=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_VDSO_TIME_NS=y -CONFIG_FONT_SUPPORT=y -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -CONFIG_SG_POOL=y -CONFIG_ARCH_HAS_PMEM_API=y -CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y -CONFIG_ARCH_HAS_COPY_MC=y -CONFIG_ARCH_STACKWALK=y -CONFIG_SBITMAP=y -# CONFIG_STRING_SELFTEST is not set -# end of Library routines - -# -# Kernel hacking -# - -# -# printk and dmesg options -# CONFIG_PRINTK_TIME=y -# CONFIG_PRINTK_CALLER is not set -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 -CONFIG_CONSOLE_LOGLEVEL_QUIET=4 -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 -# CONFIG_BOOT_PRINTK_DELAY is not set CONFIG_DYNAMIC_DEBUG=y -CONFIG_DYNAMIC_DEBUG_CORE=y -CONFIG_SYMBOLIC_ERRNAME=y -CONFIG_DEBUG_BUGVERBOSE=y -# end of printk and dmesg options - -# -# Compile-time checks and compiler options -# -# CONFIG_DEBUG_INFO is not set -CONFIG_FRAME_WARN=2048 -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_READABLE_ASM is not set -# CONFIG_HEADERS_INSTALL is not set -# CONFIG_DEBUG_SECTION_MISMATCH is not set -CONFIG_SECTION_MISMATCH_WARN_ONLY=y -# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set -CONFIG_STACK_VALIDATION=y -# CONFIG_VMLINUX_MAP is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# end of Compile-time checks and compiler options - -# -# Generic Kernel Debugging Instruments -# -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 -CONFIG_MAGIC_SYSRQ_SERIAL=y -CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_FS_ALLOW_ALL=y -# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set -# CONFIG_DEBUG_FS_ALLOW_NONE is not set -CONFIG_HAVE_ARCH_KGDB=y CONFIG_KGDB=y -CONFIG_KGDB_HONOUR_BLOCKLIST=y -CONFIG_KGDB_SERIAL_CONSOLE=y -# CONFIG_KGDB_TESTS is not set CONFIG_KGDB_LOW_LEVEL_TRAP=y CONFIG_KGDB_KDB=y -CONFIG_KDB_DEFAULT_ENABLE=0x1 CONFIG_KDB_KEYBOARD=y -CONFIG_KDB_CONTINUE_CATASTROPHIC=0 -CONFIG_ARCH_HAS_EARLY_DEBUG=y -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y -# CONFIG_UBSAN is not set -CONFIG_HAVE_ARCH_KCSAN=y -# end of Generic Kernel Debugging Instruments - -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MISC=y - -# -# Memory Debugging -# -# CONFIG_PAGE_EXTENSION is not set -# CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_PAGE_OWNER is not set -# CONFIG_PAGE_POISONING is not set -# CONFIG_DEBUG_PAGE_REF is not set CONFIG_DEBUG_RODATA_TEST=y -CONFIG_ARCH_HAS_DEBUG_WX=y -# CONFIG_DEBUG_WX is not set -CONFIG_GENERIC_PTDUMP=y -# CONFIG_PTDUMP_DEBUGFS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_SLUB_DEBUG_ON is not set -# CONFIG_SLUB_STATS is not set -CONFIG_HAVE_DEBUG_KMEMLEAK=y CONFIG_DEBUG_KMEMLEAK=y -CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE=16000 -# CONFIG_DEBUG_KMEMLEAK_TEST is not set CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y -CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y -# CONFIG_DEBUG_STACK_USAGE is not set CONFIG_SCHED_STACK_END_CHECK=y -CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_VM_PGTABLE is not set -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -# CONFIG_DEBUG_VIRTUAL is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_PER_CPU_MAPS is not set -CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y -# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set -CONFIG_HAVE_ARCH_KASAN=y -CONFIG_HAVE_ARCH_KASAN_VMALLOC=y -CONFIG_CC_HAS_KASAN_GENERIC=y -CONFIG_HAVE_ARCH_KFENCE=y -# CONFIG_KFENCE is not set -# end of Memory Debugging - CONFIG_DEBUG_SHIRQ=y - -# -# Debug Oops, Lockups and Hangs -# -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -CONFIG_LOCKUP_DETECTOR=y -CONFIG_SOFTLOCKUP_DETECTOR=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_HARDLOCKUP_DETECTOR_PERF=y -CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y CONFIG_HARDLOCKUP_DETECTOR=y -# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_WQ_WATCHDOG is not set -# CONFIG_TEST_LOCKUP is not set -# end of Debug Oops, Lockups and Hangs - -# -# Scheduler Debugging -# -CONFIG_SCHED_DEBUG=y -CONFIG_SCHED_INFO=y CONFIG_SCHEDSTATS=y -# end of Scheduler Debugging - -# CONFIG_DEBUG_TIMEKEEPING is not set - -# -# Lock Debugging (spinlocks, mutexes, etc...) -# -CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_PROVE_LOCKING=y -# CONFIG_PROVE_RAW_LOCK_NESTING is not set -# CONFIG_LOCK_STAT is not set -CONFIG_DEBUG_RT_MUTEXES=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y -CONFIG_DEBUG_RWSEMS=y -CONFIG_DEBUG_LOCK_ALLOC=y -CONFIG_LOCKDEP=y -CONFIG_LOCKDEP_BITS=15 -CONFIG_LOCKDEP_CHAINS_BITS=16 -CONFIG_LOCKDEP_STACK_TRACE_BITS=19 -CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14 -CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12 -# CONFIG_DEBUG_LOCKDEP is not set CONFIG_DEBUG_ATOMIC_SLEEP=y -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_LOCK_TORTURE_TEST is not set -# CONFIG_WW_MUTEX_SELFTEST is not set -# CONFIG_SCF_TORTURE_TEST is not set -# CONFIG_CSD_LOCK_WAIT_DEBUG is not set -# end of Lock Debugging (spinlocks, mutexes, etc...) - -CONFIG_TRACE_IRQFLAGS=y -CONFIG_TRACE_IRQFLAGS_NMI=y -# CONFIG_DEBUG_IRQFLAGS is not set -CONFIG_STACKTRACE=y -# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set -# CONFIG_DEBUG_KOBJECT is not set - -# -# Debug kernel data structures -# -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_PLIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_BUG_ON_DATA_CORRUPTION is not set -# end of Debug kernel data structures - -# CONFIG_DEBUG_CREDENTIALS is not set - -# -# RCU Debugging -# -CONFIG_PROVE_RCU=y -# CONFIG_RCU_SCALE_TEST is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_REF_SCALE_TEST is not set CONFIG_RCU_CPU_STALL_TIMEOUT=60 # CONFIG_RCU_TRACE is not set -# CONFIG_RCU_EQS_DEBUG is not set -# end of RCU Debugging - -# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -# CONFIG_LATENCYTOP is not set -CONFIG_USER_STACKTRACE_SUPPORT=y -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_FENTRY=y -CONFIG_HAVE_OBJTOOL_MCOUNT=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_TRACER_MAX_TRACE=y -CONFIG_TRACE_CLOCK=y -CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_PREEMPTIRQ_TRACEPOINTS=y -CONFIG_TRACING=y -CONFIG_GENERIC_TRACER=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_BOOTTIME_TRACING is not set -CONFIG_FUNCTION_TRACER=y -CONFIG_FUNCTION_GRAPH_TRACER=y -CONFIG_DYNAMIC_FTRACE=y -CONFIG_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y CONFIG_FUNCTION_PROFILER=y CONFIG_STACK_TRACER=y -# CONFIG_IRQSOFF_TRACER is not set CONFIG_SCHED_TRACER=y CONFIG_HWLAT_TRACER=y CONFIG_MMIOTRACE=y CONFIG_FTRACE_SYSCALLS=y -CONFIG_TRACER_SNAPSHOT=y -# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_KPROBE_EVENTS=y -# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set -CONFIG_UPROBE_EVENTS=y -CONFIG_BPF_EVENTS=y -CONFIG_DYNAMIC_EVENTS=y -CONFIG_PROBE_EVENTS=y -# CONFIG_BPF_KPROBE_OVERRIDE is not set -CONFIG_FTRACE_MCOUNT_RECORD=y -CONFIG_FTRACE_MCOUNT_USE_CC=y -CONFIG_TRACING_MAP=y -CONFIG_SYNTH_EVENTS=y CONFIG_HIST_TRIGGERS=y -# CONFIG_TRACE_EVENT_INJECT is not set -# CONFIG_TRACEPOINT_BENCHMARK is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_TRACE_EVAL_MAP_FILE is not set -# CONFIG_FTRACE_RECORD_RECURSION is not set -# CONFIG_FTRACE_STARTUP_TEST is not set -# CONFIG_RING_BUFFER_STARTUP_TEST is not set -# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set -# CONFIG_MMIOTRACE_TEST is not set -# CONFIG_PREEMPTIRQ_DELAY_TEST is not set -# CONFIG_SYNTH_EVENT_GEN_TEST is not set -# CONFIG_KPROBE_EVENT_GEN_TEST is not set -# CONFIG_HIST_TRIGGERS_DEBUG is not set -# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set -# CONFIG_SAMPLES is not set -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # CONFIG_STRICT_DEVMEM is not set - -# -# x86 Debugging -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y # CONFIG_X86_VERBOSE_BOOTUP is not set -CONFIG_EARLY_PRINTK=y -# CONFIG_EARLY_PRINTK_DBGP is not set -# CONFIG_EARLY_PRINTK_USB_XDBC is not set -# CONFIG_EFI_PGT_DUMP is not set -# CONFIG_DEBUG_TLBFLUSH is not set -# CONFIG_IOMMU_DEBUG is not set -CONFIG_HAVE_MMIOTRACE_SUPPORT=y -# CONFIG_X86_DECODER_SELFTEST is not set -# CONFIG_IO_DELAY_0X80 is not set CONFIG_IO_DELAY_0XED=y -# CONFIG_IO_DELAY_UDELAY is not set -# CONFIG_IO_DELAY_NONE is not set -# CONFIG_DEBUG_BOOT_PARAMS is not set -# CONFIG_CPA_DEBUG is not set -# CONFIG_DEBUG_ENTRY is not set -# CONFIG_DEBUG_NMI_SELFTEST is not set -CONFIG_X86_DEBUG_FPU=y -# CONFIG_PUNIT_ATOM_DEBUG is not set -CONFIG_UNWINDER_ORC=y -# CONFIG_UNWINDER_FRAME_POINTER is not set -# CONFIG_UNWINDER_GUESS is not set -# end of x86 Debugging - -# -# Kernel Testing and Coverage -# -# CONFIG_KUNIT is not set -# CONFIG_NOTIFIER_ERROR_INJECTION is not set -CONFIG_FUNCTION_ERROR_INJECTION=y -# CONFIG_FAULT_INJECTION is not set -CONFIG_ARCH_HAS_KCOV=y -CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set # CONFIG_RUNTIME_TESTING_MENU is not set -CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y -# end of Kernel Testing and Coverage -# end of Kernel hacking From 545a7026bb55b81499c5805a63dbecc954bd3450 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 29 Jun 2022 12:43:19 -0500 Subject: [PATCH 0015/2653] x86/configs: Update defconfig with peer-to-peer configs - Update defconfig for PCI_P2PDMA - Update defconfig for DMABUF_MOVE_NOTIFY - Update defconfig for HSA_AMD_P2P Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index 406fdfaceb550..0ad80a8c8eab0 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -303,6 +303,7 @@ CONFIG_PCIEAER=y CONFIG_PCI_REALLOC_ENABLE_AUTO=y CONFIG_PCI_STUB=y CONFIG_PCI_IOV=y +CONFIG_PCI_P2PDMA=y CONFIG_HOTPLUG_PCI=y CONFIG_RAPIDIO=y CONFIG_RAPIDIO_DMA_ENGINE=y @@ -417,6 +418,7 @@ CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_CIK=y CONFIG_HSA_AMD=y +CONFIG_HSA_AMD_P2P=y CONFIG_DRM_AST=m CONFIG_FB=y CONFIG_BACKLIGHT_CLASS_DEVICE=y @@ -453,6 +455,7 @@ CONFIG_LEDS_TRIGGERS=y CONFIG_RTC_CLASS=y # CONFIG_RTC_HCTOSYS is not set CONFIG_DMADEVICES=y +CONFIG_DMABUF_MOVE_NOTIFY=y # CONFIG_X86_PLATFORM_DEVICES is not set CONFIG_AMD_IOMMU=y CONFIG_INTEL_IOMMU=y From ab7228c4a23b46311455bfffdd9f503bd9a193f8 Mon Sep 17 00:00:00 2001 From: Max Erenberg Date: Tue, 5 Nov 2024 21:36:41 -0500 Subject: [PATCH 0016/2653] x86/configs: add VIRTIO configs to debug rock defconfig These options are necessary to use virtio devices with QEMU. Signed-off-by: Max Erenberg Reviewed-by: Amber Lin --- arch/x86/configs/rock-dbg_defconfig | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index 0ad80a8c8eab0..565e447c6230b 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -353,6 +353,20 @@ CONFIG_NETCONSOLE=y CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_TUN=y CONFIG_VETH=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LIB=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_MENU=y +CONFIG_NET_9P=y +CONFIG_NET_9P_VIRTIO=y +CONFIG_9P_FS=y +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_BLK=y +CONFIG_DRM_VIRTIO_GPU=y CONFIG_ALX=y CONFIG_BNX2=y CONFIG_TIGON3=y From 4451dccfb283b06233d1bf209433069c573bca84 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Mon, 7 Jul 2025 12:38:00 -0400 Subject: [PATCH 0017/2653] drm/amd/display: [FW Promotion] Release 0.1.18.0 Add new mode in struct ips_residency_mode Acked-by: Tom Chung Signed-off-by: Taimur Hassan Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index c587b3441e070..686de58a0412f 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -882,7 +882,7 @@ enum dmub_shared_state_feature_id { /** * struct dmub_shared_state_ips_fw - Firmware signals for IPS. */ - union dmub_shared_state_ips_fw_signals { +union dmub_shared_state_ips_fw_signals { struct { uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */ uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ @@ -897,7 +897,7 @@ enum dmub_shared_state_feature_id { /** * struct dmub_shared_state_ips_signals - Firmware signals for IPS. */ - union dmub_shared_state_ips_driver_signals { +union dmub_shared_state_ips_driver_signals { struct { uint32_t allow_pg : 1; /**< 1 if PG is allowed */ uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ @@ -4099,7 +4099,6 @@ struct dmub_cmd_replay_copy_settings_data { * Use for AUX-less ALPM LFPS wake operation */ struct dmub_alpm_auxless_data auxless_alpm_data; - /** * @pad: Align structure to 4 byte boundary. */ @@ -5914,6 +5913,7 @@ enum ips_residency_mode { IPS_RESIDENCY__IPS2, IPS_RESIDENCY__IPS1_RCG, IPS_RESIDENCY__IPS1_ONO2_ON, + IPS_RESIDENCY__IPS1_Z8_RETENTION, }; #define NUM_IPS_HISTOGRAM_BUCKETS 16 From 8ee053f54a0020e4b8200e670014de3ca16ea273 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Wed, 9 Jul 2025 14:31:41 -0500 Subject: [PATCH 0018/2653] drm/amd/display: Promote DAL to 3.2.341 This version brings along following fixes: - Fixes for DCN401, DCN32 - Initial support of SmartMux - Improvements for Replay, IPS, and IPS2 - Refactor of DSC Reviewed-by: Martin Leung Signed-off-by: Taimur Hassan Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 59c07756130d5..d0c78f94a7a3f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.340" +#define DC_VER "3.2.341" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From 8f8fd042de5d909154bc17aaaf371b1a2b68de3a Mon Sep 17 00:00:00 2001 From: Ostrowski Rafal Date: Tue, 24 Jun 2025 14:13:53 +0200 Subject: [PATCH 0019/2653] drm/amd/display: Update tiled to tiled copy command [Why & How] Tiled command rect dimensions is 1 based, do rect_x/y - 1 internally Reviewed-by: Alvin Lee Signed-off-by: Ostrowski Rafal Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index f5ef1a07078e5..714c468c010d3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -2072,8 +2072,8 @@ bool dmub_lsdma_send_tiled_to_tiled_copy_command( lsdma_data->u.tiled_copy_data.dst_swizzle_mode = params.swizzle_mode; lsdma_data->u.tiled_copy_data.src_element_size = params.element_size; lsdma_data->u.tiled_copy_data.dst_element_size = params.element_size; - lsdma_data->u.tiled_copy_data.rect_x = params.rect_x; - lsdma_data->u.tiled_copy_data.rect_y = params.rect_y; + lsdma_data->u.tiled_copy_data.rect_x = params.rect_x - 1; + lsdma_data->u.tiled_copy_data.rect_y = params.rect_y - 1; lsdma_data->u.tiled_copy_data.dcc = params.dcc; lsdma_data->u.tiled_copy_data.tmz = params.tmz; lsdma_data->u.tiled_copy_data.read_compress = params.read_compress; From 144aca435ac03a5657c72ce64f8412cc142617b2 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Wed, 25 Jun 2025 10:11:22 -0400 Subject: [PATCH 0020/2653] drm/amd/display: fix condition for setting timing_adjust_pending timing_adjust_pending is used to defer certain programming sequences when OTG timing is about to be changed, like with VRR. Insufficient checking for timing change in this case caused a regression which reduces PSR Replay residency. Reviewed-by: Tom Chung Signed-off-by: Aurabindo Pillai Signed-off-by: Robin Chen Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index c31f7f8e409f2..61d0940cd41f8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -446,7 +446,9 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, * avoid conflicting with firmware updates. */ if (dc->ctx->dce_version > DCE_VERSION_MAX) { - if (dc->optimized_required || dc->wm_optimized_required) { + if ((dc->optimized_required || dc->wm_optimized_required) && + (stream->adjust.v_total_max != adjust->v_total_max || + stream->adjust.v_total_min != adjust->v_total_min)) { stream->adjust.timing_adjust_pending = true; return false; } From 4e28c2de6407d97329826459c724c082d6cf02d3 Mon Sep 17 00:00:00 2001 From: Gabe Teeger Date: Wed, 9 Jul 2025 14:12:22 -0400 Subject: [PATCH 0021/2653] drm/amd/display: Revert Add HPO encoder support to Replay This reverts commits: commit e6bd65ba7323 ("drm/amd/display: Add HPO encoder support to Replay") commit 2595b2de3005 ("drm/amd/display: Add support for Panel Replay on DP1 eDP (panel_inst=1)") due to visual confirm issue. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Gabe Teeger Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dc/dce/dmub_replay.c | 43 ++----------------- .../gpu/drm/amd/display/dc/dce/dmub_replay.h | 2 +- .../link/protocols/link_edp_panel_control.c | 2 +- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 20 --------- 4 files changed, 5 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c index e7a318e26d38a..fcd3d86ad5173 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c @@ -4,7 +4,6 @@ #include "dc.h" #include "dc_dmub_srv.h" -#include "dc_dp_types.h" #include "dmub/dmub_srv.h" #include "core_types.h" #include "dmub_replay.h" @@ -44,45 +43,21 @@ static void dmub_replay_get_state(struct dmub_replay *dmub, enum replay_state *s /* * Enable/Disable Replay. */ -static void dmub_replay_enable(struct dmub_replay *dmub, bool enable, bool wait, uint8_t panel_inst, - struct dc_link *link) +static void dmub_replay_enable(struct dmub_replay *dmub, bool enable, bool wait, uint8_t panel_inst) { union dmub_rb_cmd cmd; struct dc_context *dc = dmub->ctx; uint32_t retry_count; enum replay_state state = REPLAY_STATE_0; - struct pipe_ctx *pipe_ctx = NULL; - struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; - uint8_t i; memset(&cmd, 0, sizeof(cmd)); cmd.replay_enable.header.type = DMUB_CMD__REPLAY; cmd.replay_enable.data.panel_inst = panel_inst; cmd.replay_enable.header.sub_type = DMUB_CMD__REPLAY_ENABLE; - if (enable) { + if (enable) cmd.replay_enable.data.enable = REPLAY_ENABLE; - // hpo stream/link encoder assignments are not static, need to update everytime we try to enable replay - if (link->cur_link_settings.link_rate >= LINK_RATE_UHBR10) { - for (i = 0; i < MAX_PIPES; i++) { - if (res_ctx && - res_ctx->pipe_ctx[i].stream && - res_ctx->pipe_ctx[i].stream->link && - res_ctx->pipe_ctx[i].stream->link == link && - res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { - pipe_ctx = &res_ctx->pipe_ctx[i]; - //TODO: refactor for multi edp support - break; - } - } - - if (!pipe_ctx) - return; - - cmd.replay_enable.data.hpo_stream_enc_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; - cmd.replay_enable.data.hpo_link_enc_inst = pipe_ctx->link_res.hpo_dp_link_enc->inst; - } - } else + else cmd.replay_enable.data.enable = REPLAY_DISABLE; cmd.replay_enable.header.payload_bytes = sizeof(struct dmub_rb_cmd_replay_enable_data); @@ -174,17 +149,6 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub, copy_settings_data->digbe_inst = replay_context->digbe_inst; copy_settings_data->digfe_inst = replay_context->digfe_inst; - if (link->cur_link_settings.link_rate >= LINK_RATE_UHBR10) { - if (pipe_ctx->stream_res.hpo_dp_stream_enc) - copy_settings_data->hpo_stream_enc_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; - else - copy_settings_data->hpo_stream_enc_inst = 0; - if (pipe_ctx->link_res.hpo_dp_link_enc) - copy_settings_data->hpo_link_enc_inst = pipe_ctx->link_res.hpo_dp_link_enc->inst; - else - copy_settings_data->hpo_link_enc_inst = 0; - } - if (pipe_ctx->plane_res.dpp) copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; else @@ -247,7 +211,6 @@ static void dmub_replay_set_coasting_vtotal(struct dmub_replay *dmub, pCmd->header.type = DMUB_CMD__REPLAY; pCmd->header.sub_type = DMUB_CMD__REPLAY_SET_COASTING_VTOTAL; pCmd->header.payload_bytes = sizeof(struct dmub_cmd_replay_set_coasting_vtotal_data); - pCmd->replay_set_coasting_vtotal_data.panel_inst = panel_inst; pCmd->replay_set_coasting_vtotal_data.coasting_vtotal = (coasting_vtotal & 0xFFFF); pCmd->replay_set_coasting_vtotal_data.coasting_vtotal_high = (coasting_vtotal & 0xFFFF0000) >> 16; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h index ccbe385e132c4..e6346c0ffc0e4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h @@ -19,7 +19,7 @@ struct dmub_replay_funcs { void (*replay_get_state)(struct dmub_replay *dmub, enum replay_state *state, uint8_t panel_inst); void (*replay_enable)(struct dmub_replay *dmub, bool enable, bool wait, - uint8_t panel_inst, struct dc_link *link); + uint8_t panel_inst); bool (*replay_copy_settings)(struct dmub_replay *dmub, struct dc_link *link, struct replay_context *replay_context, uint8_t panel_inst); void (*replay_set_power_opt)(struct dmub_replay *dmub, unsigned int power_opt, diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index e7927b8f5ba35..98ec9b5a559c8 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -944,7 +944,7 @@ bool edp_set_replay_allow_active(struct dc_link *link, const bool *allow_active, // TODO: Handle mux change case if force_static is set // If force_static is set, just change the replay_allow_active state directly if (replay != NULL && link->replay_settings.replay_feature_enabled) - replay->funcs->replay_enable(replay, *allow_active, wait, panel_inst, link); + replay->funcs->replay_enable(replay, *allow_active, wait, panel_inst); link->replay_settings.replay_allow_active = *allow_active; } diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 686de58a0412f..1fb1472737ad2 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -4047,14 +4047,6 @@ struct dmub_cmd_replay_copy_settings_data { * DIG BE HW instance. */ uint8_t digbe_inst; - /** - * @hpo_stream_enc_inst: HPO stream encoder instance - */ - uint8_t hpo_stream_enc_inst; - /** - * @hpo_link_enc_inst: HPO link encoder instance - */ - uint8_t hpo_link_enc_inst; /** * AUX HW instance. */ @@ -4158,18 +4150,6 @@ struct dmub_rb_cmd_replay_enable_data { * This does not support HDMI/DP2 for now. */ uint8_t phy_rate; - /** - * @hpo_stream_enc_inst: HPO stream encoder instance - */ - uint8_t hpo_stream_enc_inst; - /** - * @hpo_link_enc_inst: HPO link encoder instance - */ - uint8_t hpo_link_enc_inst; - /** - * @pad: Align structure to 4 byte boundary. - */ - uint8_t pad[2]; }; /** From 38eb86639b2cef29889138a9b2e8e98b4cff9f88 Mon Sep 17 00:00:00 2001 From: Clay King Date: Mon, 7 Jul 2025 13:21:30 -0400 Subject: [PATCH 0022/2653] drm/amd/display: ensure committing streams is seamless [Why] When transitioning between topologies such as multi-display to single display ODM 2:1, pipes might not be freed before use. [How] In dc_commit_streams, commit an additional, minimal transition if original transition is not seamless to ensure pipes are freed. Reviewed-by: Alvin Lee Signed-off-by: Clay King Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 61d0940cd41f8..c17e5843e8b79 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2399,6 +2399,18 @@ enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params goto fail; } + /* + * If not already seamless, make transition seamless by inserting intermediate minimal transition + */ + if (dc->hwss.is_pipe_topology_transition_seamless && + !dc->hwss.is_pipe_topology_transition_seamless(dc, dc->current_state, context)) { + res = commit_minimal_transition_state(dc, context); + if (res != DC_OK) { + BREAK_TO_DEBUGGER(); + goto fail; + } + } + res = dc_commit_state_no_check(dc, context); for (i = 0; i < params->stream_count; i++) { From 1b13b822942847c9397e698e343c8afde2a52ef7 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Wed, 25 Jun 2025 10:23:13 -0500 Subject: [PATCH 0023/2653] drm/amd/display: Drop unnecessary 'rc' variable in amdgpu_dm_backlight_get_level() [Why] amdgpu_dm_backlight_get_level() returns a boolean value but is assigned to a variable named 'rc' which is generally used for return codes. This can be confusing while looking at the code for other issues. [How] Drop the variable and just look directly at the return value of amdgpu_dm_backlight_get_level() in the if statement. Reviewed-by: Alex Hung Signed-off-by: Mario Limonciello Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 096b23ad4845d..129476b6d5fa9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4924,10 +4924,8 @@ static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, if (caps.aux_support) { u32 avg, peak; - bool rc; - rc = dc_link_get_backlight_level_nits(link, &avg, &peak); - if (!rc) + if (!dc_link_get_backlight_level_nits(link, &avg, &peak)) return dm->brightness[bl_idx]; return convert_brightness_to_user(&caps, avg); } From fddc0b9ef16662c73913d3773447d2e5d3b9677d Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Thu, 10 Jul 2025 20:57:37 -0400 Subject: [PATCH 0024/2653] drm/amd/display: Fix divide by zero when calculating min ODM factor [WHY&HOW] If the debug option is set to disable_dsc the max slice width and/or dispclk can be zero. This causes a divide by zero when calculating the min ODM combine factor. Add a check to ensure they are valid first. Reviewed-by: Wenjing Liu Signed-off-by: Dillon Varone Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 29 +++++++++++---------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index a454d16e6586b..1f53a9f0c0ac3 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -152,7 +152,7 @@ uint32_t dc_bandwidth_in_kbps_from_timing( } /* Forward Declerations */ -static unsigned int get_min_slice_count_for_odm( +static unsigned int get_min_dsc_slice_count_for_odm( const struct display_stream_compressor *dsc, const struct dsc_enc_caps *dsc_enc_caps, const struct dc_crtc_timing *timing); @@ -466,7 +466,7 @@ bool dc_dsc_compute_bandwidth_range( struct dc_dsc_bw_range *range) { bool is_dsc_possible = false; - unsigned int min_slice_count; + unsigned int min_dsc_slice_count; struct dsc_enc_caps dsc_enc_caps; struct dsc_enc_caps dsc_common_caps; struct dc_dsc_config config = {0}; @@ -478,14 +478,14 @@ bool dc_dsc_compute_bandwidth_range( get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz); - min_slice_count = get_min_slice_count_for_odm(dsc, &dsc_enc_caps, timing); + min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &dsc_enc_caps, timing); is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, &dsc_enc_caps, timing->pixel_encoding, &dsc_common_caps); if (is_dsc_possible) is_dsc_possible = setup_dsc_config(dsc_sink_caps, &dsc_enc_caps, 0, timing, - &options, link_encoding, min_slice_count, &config); + &options, link_encoding, min_dsc_slice_count, &config); if (is_dsc_possible) is_dsc_possible = decide_dsc_bandwidth_range(min_bpp_x16, max_bpp_x16, @@ -593,14 +593,12 @@ static void build_dsc_enc_caps( struct dc *dc; - memset(&single_dsc_enc_caps, 0, sizeof(struct dsc_enc_caps)); - if (!dsc || !dsc->ctx || !dsc->ctx->dc || !dsc->funcs->dsc_get_single_enc_caps) return; dc = dsc->ctx->dc; - if (!dc->clk_mgr || !dc->clk_mgr->funcs->get_max_clock_khz || !dc->res_pool) + if (!dc->clk_mgr || !dc->clk_mgr->funcs->get_max_clock_khz || !dc->res_pool || dc->debug.disable_dsc) return; /* get max DSCCLK from clk_mgr */ @@ -634,7 +632,7 @@ static inline uint32_t dsc_div_by_10_round_up(uint32_t value) return (value + 9) / 10; } -static unsigned int get_min_slice_count_for_odm( +static unsigned int get_min_dsc_slice_count_for_odm( const struct display_stream_compressor *dsc, const struct dsc_enc_caps *dsc_enc_caps, const struct dc_crtc_timing *timing) @@ -651,6 +649,10 @@ static unsigned int get_min_slice_count_for_odm( } } + /* validate parameters */ + if (max_dispclk_khz == 0 || dsc_enc_caps->max_slice_width == 0) + return 1; + /* consider minimum odm slices required due to * 1) display pipe throughput (dispclk) * 2) max image width per slice @@ -669,13 +671,12 @@ static void get_dsc_enc_caps( { memset(dsc_enc_caps, 0, sizeof(struct dsc_enc_caps)); - if (!dsc) + if (!dsc || !dsc->ctx || !dsc->ctx->dc || dsc->ctx->dc->debug.disable_dsc) return; /* check if reported cap global or only for a single DCN DSC enc */ if (dsc->funcs->dsc_get_enc_caps) { - if (!dsc->ctx->dc->debug.disable_dsc) - dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz); + dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz); } else { build_dsc_enc_caps(dsc, dsc_enc_caps); } @@ -1295,10 +1296,10 @@ bool dc_dsc_compute_config( { bool is_dsc_possible = false; struct dsc_enc_caps dsc_enc_caps; - unsigned int min_slice_count; + unsigned int min_dsc_slice_count; get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz); - min_slice_count = get_min_slice_count_for_odm(dsc, &dsc_enc_caps, timing); + min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &dsc_enc_caps, timing); is_dsc_possible = setup_dsc_config(dsc_sink_caps, &dsc_enc_caps, @@ -1306,7 +1307,7 @@ bool dc_dsc_compute_config( timing, options, link_encoding, - min_slice_count, + min_dsc_slice_count, dsc_cfg); return is_dsc_possible; } From f14be7975d24b3f72896daaf713e70dbe08817da Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Sun, 13 Jul 2025 11:28:43 -0400 Subject: [PATCH 0025/2653] drm/amd/display: [FW Promotion] Release 0.1.19.0 Update DMUB related command structure. Acked-by: Tom Chung Signed-off-by: Taimur Hassan Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 89 +++++++++++++++---- 1 file changed, 73 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 1fb1472737ad2..a89bf08ffd379 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -1990,18 +1990,19 @@ struct dmub_cmd_lsdma_data { struct lsdma_tiled_copy_data { uint32_t src_addr_lo; uint32_t src_addr_hi; + uint32_t dst_addr_lo; uint32_t dst_addr_hi; uint32_t src_x : 16; uint32_t src_y : 16; - uint32_t src_width : 16; - uint32_t src_height : 16; - uint32_t dst_x : 16; uint32_t dst_y : 16; + uint32_t src_width : 16; + uint32_t src_height : 16; + uint32_t dst_width : 16; uint32_t dst_height : 16; @@ -2034,23 +2035,58 @@ struct dmub_cmd_lsdma_data { uint32_t padding : 30; } tiled_copy_data; struct lsdma_linear_copy_data { + uint32_t src_lo; + uint32_t src_hi; + + uint32_t dst_lo; + uint32_t dst_hi; + uint32_t count : 30; uint32_t cache_policy_dst : 2; uint32_t tmz : 1; uint32_t cache_policy_src : 2; uint32_t padding : 29; - + } linear_copy_data; + struct lsdma_linear_sub_window_copy_data { uint32_t src_lo; uint32_t src_hi; + uint32_t dst_lo; uint32_t dst_hi; - } linear_copy_data; + + uint32_t src_x : 16; + uint32_t src_y : 16; + + uint32_t dst_x : 16; + uint32_t dst_y : 16; + + uint32_t rect_x : 16; + uint32_t rect_y : 16; + + uint32_t src_pitch : 16; + uint32_t dst_pitch : 16; + + uint32_t src_slice_pitch; + uint32_t dst_slice_pitch; + + uint32_t tmz : 1; + uint32_t element_size : 3; + uint32_t src_cache_policy : 3; + uint32_t dst_cache_policy : 3; + uint32_t reserved0 : 22; + } linear_sub_window_copy_data; struct lsdma_reg_write_data { uint32_t reg_addr; uint32_t reg_data; } reg_write_data; struct lsdma_pio_copy_data { + uint32_t src_lo; + uint32_t src_hi; + + uint32_t dst_lo; + uint32_t dst_hi; + union { struct { uint32_t byte_count : 26; @@ -2063,12 +2099,11 @@ struct dmub_cmd_lsdma_data { } fields; uint32_t raw; } packet; - uint32_t src_lo; - uint32_t src_hi; - uint32_t dst_lo; - uint32_t dst_hi; } pio_copy_data; struct lsdma_pio_constfill_data { + uint32_t dst_lo; + uint32_t dst_hi; + union { struct { uint32_t byte_count : 26; @@ -2081,14 +2116,12 @@ struct dmub_cmd_lsdma_data { } fields; uint32_t raw; } packet; - uint32_t dst_lo; - uint32_t dst_hi; + uint32_t data; } pio_constfill_data; uint32_t all[14]; } u; - }; struct dmub_rb_cmd_lsdma { @@ -4047,6 +4080,14 @@ struct dmub_cmd_replay_copy_settings_data { * DIG BE HW instance. */ uint8_t digbe_inst; + /** + * @hpo_stream_enc_inst: HPO stream encoder instance + */ + uint8_t hpo_stream_enc_inst; + /** + * @hpo_link_enc_inst: HPO link encoder instance + */ + uint8_t hpo_link_enc_inst; /** * AUX HW instance. */ @@ -4150,6 +4191,18 @@ struct dmub_rb_cmd_replay_enable_data { * This does not support HDMI/DP2 for now. */ uint8_t phy_rate; + /** + * @hpo_stream_enc_inst: HPO stream encoder instance + */ + uint8_t hpo_stream_enc_inst; + /** + * @hpo_link_enc_inst: HPO link encoder instance + */ + uint8_t hpo_link_enc_inst; + /** + * @pad: Align structure to 4 byte boundary. + */ + uint8_t pad[2]; }; /** @@ -4663,22 +4716,26 @@ enum dmub_cmd_lsdma_type { * LSDMA copies data from source to destination linearly */ DMUB_CMD__LSDMA_LINEAR_COPY = 1, + /** + * LSDMA copies data from source to destination linearly in sub window + */ + DMUB_CMD__LSDMA_LINEAR_SUB_WINDOW_COPY = 2, /** * Send the tiled-to-tiled copy command */ - DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 2, + DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 3, /** * Send the poll reg write command */ - DMUB_CMD__LSDMA_POLL_REG_WRITE = 3, + DMUB_CMD__LSDMA_POLL_REG_WRITE = 4, /** * Send the pio copy command */ - DMUB_CMD__LSDMA_PIO_COPY = 4, + DMUB_CMD__LSDMA_PIO_COPY = 5, /** * Send the pio constfill command */ - DMUB_CMD__LSDMA_PIO_CONSTFILL = 5, + DMUB_CMD__LSDMA_PIO_CONSTFILL = 6, }; struct abm_ace_curve { From 5d1093bee21f717a65b83e3f68db1190e4af7edc Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Sun, 13 Jul 2025 12:42:07 -0500 Subject: [PATCH 0026/2653] drm/amd/display: Promote DAL to 3.2.342 This version brings along following fixes: - Fix divide by zero when calculating min ODM factor - Ensure committing streams is seamless when transitioning between topologies - Fix condition for setting timing_adjust_pending - Update DMUB tiled to tiled copy command Acked-by: Tom Chung Signed-off-by: Taimur Hassan Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d0c78f94a7a3f..779b39e334436 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.341" +#define DC_VER "3.2.342" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From 53ef2703cb7dbc49ba0e942fe09dbe05b0150af2 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Thu, 10 Jul 2025 13:51:57 +0800 Subject: [PATCH 0027/2653] drm/amdgpu: query the allocated vram address block info The bad pages that need to be retired are not all allocated in the same poison consumption process, so an interface is needed to query the processes that allocate the bad pages. By killing all the processes that allocate the bad pages, the bad pages can be reserved immediately. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 38 ++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h | 17 +++++++++ 2 files changed, 55 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 07c936e90d8e4..77ce9cf280518 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -396,6 +396,35 @@ int amdgpu_vram_mgr_query_page_status(struct amdgpu_vram_mgr *mgr, return ret; } +int amdgpu_vram_mgr_query_address_block_info(struct amdgpu_vram_mgr *mgr, + uint64_t address, struct amdgpu_vram_block_info *info) +{ + struct amdgpu_vram_mgr_resource *vres; + struct drm_buddy_block *block; + u64 start, size; + int ret = -ENOENT; + + mutex_lock(&mgr->lock); + list_for_each_entry(vres, &mgr->allocated_vres_list, vres_node) { + list_for_each_entry(block, &vres->blocks, link) { + start = amdgpu_vram_mgr_block_start(block); + size = amdgpu_vram_mgr_block_size(block); + if ((start <= address) && (address < (start + size))) { + info->start = start; + info->size = size; + memcpy(&info->task, &vres->task, sizeof(vres->task)); + ret = 0; + goto out; + } + } + } + +out: + mutex_unlock(&mgr->lock); + + return ret; +} + static void amdgpu_dummy_vram_mgr_debug(struct ttm_resource_manager *man, struct drm_printer *printer) { @@ -568,6 +597,10 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man, remaining_size -= size; } + vres->task.pid = task_pid_nr(current); + get_task_comm(vres->task.comm, current); + list_add_tail(&vres->vres_node, &mgr->allocated_vres_list); + if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS && adjust_dcc_size) { struct drm_buddy_block *dcc_block; unsigned long dcc_start; @@ -645,6 +678,10 @@ static void amdgpu_vram_mgr_del(struct ttm_resource_manager *man, uint64_t vis_usage = 0; mutex_lock(&mgr->lock); + + list_del(&vres->vres_node); + memset(&vres->task, 0, sizeof(vres->task)); + list_for_each_entry(block, &vres->blocks, link) vis_usage += amdgpu_vram_mgr_vis_size(adev, block); @@ -934,6 +971,7 @@ int amdgpu_vram_mgr_init(struct amdgpu_device *adev) mutex_init(&mgr->lock); INIT_LIST_HEAD(&mgr->reservations_pending); INIT_LIST_HEAD(&mgr->reserved_pages); + INIT_LIST_HEAD(&mgr->allocated_vres_list); mgr->default_page_size = PAGE_SIZE; if (!adev->gmc.is_app_apu) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h index 2c88d5fd87da2..5f5fd9a911c26 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h @@ -35,12 +35,26 @@ struct amdgpu_vram_mgr { struct list_head reserved_pages; atomic64_t vis_usage; u64 default_page_size; + struct list_head allocated_vres_list; +}; + +struct amdgpu_vres_task { + pid_t pid; + char comm[TASK_COMM_LEN]; +}; + +struct amdgpu_vram_block_info { + u64 start; + u64 size; + struct amdgpu_vres_task task; }; struct amdgpu_vram_mgr_resource { struct ttm_resource base; struct list_head blocks; unsigned long flags; + struct list_head vres_node; + struct amdgpu_vres_task task; }; static inline u64 amdgpu_vram_mgr_block_start(struct drm_buddy_block *block) @@ -72,4 +86,7 @@ static inline void amdgpu_vram_mgr_set_cleared(struct ttm_resource *res) ares->flags |= DRM_BUDDY_CLEARED; } +int amdgpu_vram_mgr_query_address_block_info(struct amdgpu_vram_mgr *mgr, + uint64_t address, struct amdgpu_vram_block_info *info); + #endif From a47d28668cc1cb622fe79aa69a221b18e9da1111 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Wed, 16 Jul 2025 11:16:20 +0800 Subject: [PATCH 0028/2653] drm/amdgpu: add command to check address validity Add command to check address validity and remove unused command codes. v2: The command interface adds new parameters to support multiple check address strategies. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 63 +++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 3 ++ 2 files changed, 66 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index a0a14370745e4..527ffad475638 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -128,6 +128,9 @@ const char *get_ras_block_str(struct ras_common_if *ras_block) #define MAX_FLUSH_RETIRE_DWORK_TIMES 100 +#define BYPASS_ALLOCATED_ADDRESS 0x0 +#define BYPASS_INITIALIZATION_ADDRESS 0x1 + enum amdgpu_ras_retire_page_reservation { AMDGPU_RAS_RETIRE_PAGE_RESERVED, AMDGPU_RAS_RETIRE_PAGE_PENDING, @@ -207,6 +210,49 @@ static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t addre return 0; } +static int amdgpu_check_address_validity(struct amdgpu_device *adev, + uint64_t address, uint64_t flags) +{ + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + struct amdgpu_vram_block_info blk_info; + uint64_t page_pfns[32] = {0}; + int i, ret, count; + + if (amdgpu_ip_version(adev, UMC_HWIP, 0) < IP_VERSION(12, 0, 0)) + return 0; + + if ((address >= adev->gmc.mc_vram_size) || + (address >= RAS_UMC_INJECT_ADDR_LIMIT)) + return -EFAULT; + + count = amdgpu_umc_lookup_bad_pages_in_a_row(adev, + address, page_pfns, ARRAY_SIZE(page_pfns)); + if (count <= 0) + return -EPERM; + + for (i = 0; i < count; i++) { + memset(&blk_info, 0, sizeof(blk_info)); + ret = amdgpu_vram_mgr_query_address_block_info(&adev->mman.vram_mgr, + page_pfns[i] << AMDGPU_GPU_PAGE_SHIFT, &blk_info); + if (!ret) { + /* The input address that needs to be checked is allocated by + * current calling process, so it is necessary to exclude + * the calling process. + */ + if ((flags == BYPASS_ALLOCATED_ADDRESS) && + ((blk_info.task.pid != task_pid_nr(current)) || + strncmp(blk_info.task.comm, current->comm, TASK_COMM_LEN))) + return -EACCES; + else if ((flags == BYPASS_INITIALIZATION_ADDRESS) && + (blk_info.task.pid == con->init_task_pid) && + !strncmp(blk_info.task.comm, con->init_task_comm, TASK_COMM_LEN)) + return -EACCES; + } + } + + return 0; +} + static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { @@ -297,6 +343,8 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, op = 2; else if (strstr(str, "retire_page") != NULL) op = 3; + else if (strstr(str, "check_address") != NULL) + op = 4; else if (str[0] && str[1] && str[2] && str[3]) /* ascii string, but commands are not matched. */ return -EINVAL; @@ -310,6 +358,15 @@ static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, data->op = op; data->inject.address = address; + return 0; + } else if (op == 4) { + if (sscanf(str, "%*s 0x%llx 0x%llx", &address, &value) != 2 && + sscanf(str, "%*s %llu %llu", &address, &value) != 2) + return -EINVAL; + + data->op = op; + data->inject.address = address; + data->inject.value = value; return 0; } @@ -500,6 +557,9 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, return size; else return ret; + } else if (data.op == 4) { + ret = amdgpu_check_address_validity(adev, data.inject.address, data.inject.value); + return ret ? ret : size; } if (!amdgpu_ras_is_supported(adev, data.head.block)) @@ -4087,6 +4147,9 @@ int amdgpu_ras_init(struct amdgpu_device *adev) goto release_con; } + con->init_task_pid = task_pid_nr(current); + get_task_comm(con->init_task_comm, current); + dev_info(adev->dev, "RAS INFO: ras initialized successfully, " "hardware ability[%x] ras_mask[%x]\n", adev->ras_hw_enabled, adev->ras_enabled); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index 927d6bff734ae..7f10a74021600 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -570,6 +570,9 @@ struct amdgpu_ras { struct ras_event_manager *event_mgr; uint64_t reserved_pages_in_bytes; + + pid_t init_task_pid; + char init_task_comm[TASK_COMM_LEN]; }; struct ras_fs_data { From 358fb9efd2fd7f73df7872d06e7abb408a903585 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Tue, 15 Jul 2025 16:50:22 -0700 Subject: [PATCH 0029/2653] drm/amdgpu: Initialize data to NULL in imu_v12_0_program_rlc_ram() After a recent change in clang to expose uninitialized warnings from const variables and pointers [1], there is a warning in imu_v12_0_program_rlc_ram() because data is passed uninitialized to program_imu_rlc_ram(): drivers/gpu/drm/amd/amdgpu/imu_v12_0.c:374:30: error: variable 'data' is uninitialized when used here [-Werror,-Wuninitialized] 374 | program_imu_rlc_ram(adev, data, (const u32)size); | ^~~~ As this warning happens early in clang's frontend, it does not realize that due to the assignment of r to -EINVAL, program_imu_rlc_ram() is never actually called, and even if it were, data would not be dereferenced because size is 0. Just initialize data to NULL to silence the warning, as the commit that added program_imu_rlc_ram() mentioned it would eventually be used over the old method, at which point data can be properly initialized and used. Cc: stable@vger.kernel.org Closes: https://github.com/ClangBuiltLinux/linux/issues/2107 Fixes: 56159fffaab5 ("drm/amdgpu: use new method to program rlc ram") Link: https://github.com/llvm/llvm-project/commit/2464313eef01c5b1edf0eccf57a32cdee01472c7 [1] Signed-off-by: Nathan Chancellor Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/imu_v12_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c index df898dbb746e3..8cb6b1854d245 100644 --- a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c @@ -362,7 +362,7 @@ static void program_imu_rlc_ram(struct amdgpu_device *adev, static void imu_v12_0_program_rlc_ram(struct amdgpu_device *adev) { u32 reg_data, size = 0; - const u32 *data; + const u32 *data = NULL; int r = -EINVAL; WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, 0x2); From a27f11a530981d2145564e26d5dcc7c8a83980d1 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 24 Jun 2025 11:22:26 -0400 Subject: [PATCH 0030/2653] drm/amdgpu: track whether a queue is a kernel queue in amdgpu_mqd_prop MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Used to to set the MQD appropriately for each queue type. Kernel queues have additional privileges. Acked-by: Christian König Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org # 6.16.x --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index a1737556a77eb..ef3af170dda4e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -883,6 +883,7 @@ struct amdgpu_mqd_prop { uint64_t csa_addr; uint64_t fence_address; bool tmz_queue; + bool kernel_queue; }; struct amdgpu_mqd { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index acac646a4e4e9..3048ba9d18233 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -719,6 +719,7 @@ static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring, prop->eop_gpu_addr = ring->eop_gpu_addr; prop->use_doorbell = ring->use_doorbell; prop->doorbell_index = ring->doorbell_index; + prop->kernel_queue = true; /* map_queues packet doesn't need activate the queue, * so only kiq need set this field. From 627254b1556a26cfa3c00d5e0e9b63ac7c4b71cd Mon Sep 17 00:00:00 2001 From: Peter Shkenev Date: Thu, 17 Jul 2025 23:48:17 +0300 Subject: [PATCH 0031/2653] drm/amdgpu: check if hubbub is NULL in debugfs/amdgpu_dm_capabilities HUBBUB structure is not initialized on DCE hardware, so check if it is NULL to avoid null dereference while accessing amdgpu_dm_capabilities file in debugfs. Signed-off-by: Peter Shkenev Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index c7d13e743e6c8..b726bcd18e298 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3988,7 +3988,7 @@ static int capabilities_show(struct seq_file *m, void *unused) struct hubbub *hubbub = dc->res_pool->hubbub; - if (hubbub->funcs->get_mall_en) + if (hubbub && hubbub->funcs->get_mall_en) hubbub->funcs->get_mall_en(hubbub, &mall_in_use); if (dc->cap_funcs.get_subvp_en) From 51564e9f06f08a6a768546db4d7f7e6a712740c1 Mon Sep 17 00:00:00 2001 From: Gang Ba Date: Tue, 8 Jul 2025 14:36:13 -0400 Subject: [PATCH 0032/2653] drm/amdgpu: Avoid extra evict-restore process. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If vm belongs to another process, this is fclose after fork, wait may enable signaling KFD eviction fence and cause parent process queue evicted. [677852.634569] amdkfd_fence_enable_signaling+0x56/0x70 [amdgpu] [677852.634814] __dma_fence_enable_signaling+0x3e/0xe0 [677852.634820] dma_fence_wait_timeout+0x3a/0x140 [677852.634825] amddma_resv_wait_timeout+0x7f/0xf0 [amdkcl] [677852.634831] amdgpu_vm_wait_idle+0x2d/0x60 [amdgpu] [677852.635026] amdgpu_flush+0x34/0x50 [amdgpu] [677852.635208] filp_flush+0x38/0x90 [677852.635213] filp_close+0x14/0x30 [677852.635216] do_close_on_exec+0xdd/0x130 [677852.635221] begin_new_exec+0x1da/0x490 [677852.635225] load_elf_binary+0x307/0xea0 [677852.635231] ? srso_alias_return_thunk+0x5/0xfbef5 [677852.635235] ? ima_bprm_check+0xa2/0xd0 [677852.635240] search_binary_handler+0xda/0x260 [677852.635245] exec_binprm+0x58/0x1a0 [677852.635249] bprm_execve.part.0+0x16f/0x210 [677852.635254] bprm_execve+0x45/0x80 [677852.635257] do_execveat_common.isra.0+0x190/0x200 Suggested-by: Christian König Signed-off-by: Gang Ba Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index d5c0637d73928..5cacf5717016a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2414,13 +2414,11 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, */ long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout) { - timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv, - DMA_RESV_USAGE_BOOKKEEP, - true, timeout); + timeout = drm_sched_entity_flush(&vm->immediate, timeout); if (timeout <= 0) return timeout; - return dma_fence_wait_timeout(vm->last_unlocked, true, timeout); + return drm_sched_entity_flush(&vm->delayed, timeout); } static void amdgpu_vm_destroy_task_info(struct kref *kref) From 820770db9e63c9065256eeaf7ebbe3d92fd3da62 Mon Sep 17 00:00:00 2001 From: Lauri Tirkkonen Date: Mon, 21 Jul 2025 09:59:40 +0900 Subject: [PATCH 0033/2653] drm/amd/display: fix initial backlight brightness calculation DIV_ROUND_CLOSEST(x, 100) returns either 0 or 1 if 0 Cc: stable@vger.kernel.org Reviewed-by: Mario Limonciello Link: https://lore.kernel.org/r/aH2Q_HJvxKbW74vU@hacktheplanet.fi Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 129476b6d5fa9..28ced6c47e8aa 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4981,9 +4981,9 @@ amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) caps = &dm->backlight_caps[aconnector->bl_idx]; if (get_brightness_range(caps, &min, &max)) { if (power_supply_is_system_supplied() > 0) - props.brightness = (max - min) * DIV_ROUND_CLOSEST(caps->ac_level, 100); + props.brightness = DIV_ROUND_CLOSEST((max - min) * caps->ac_level, 100); else - props.brightness = (max - min) * DIV_ROUND_CLOSEST(caps->dc_level, 100); + props.brightness = DIV_ROUND_CLOSEST((max - min) * caps->dc_level, 100); /* min is zero, so max needs to be adjusted */ props.max_brightness = max - min; drm_dbg(drm, "Backlight caps: min: %d, max: %d, ac %d, dc %d\n", min, max, From a1584d1613294251e476525539a8289f4a4e9ee6 Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Wed, 2 Jul 2025 16:16:02 +0800 Subject: [PATCH 0034/2653] drm/amdgpu: add range check for RAS bad page address Exclude invalid bad pages. Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 58 ++++++++++++------------- 1 file changed, 28 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 527ffad475638..f0ffa2f1d0e95 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -139,9 +139,9 @@ enum amdgpu_ras_retire_page_reservation { atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); -static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, +static int amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, uint64_t addr); -static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, +static int amdgpu_ras_check_bad_page(struct amdgpu_device *adev, uint64_t addr); #ifdef CONFIG_X86_MCE_AMD static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev); @@ -172,18 +172,16 @@ static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t addre struct eeprom_table_record err_rec; int ret; - if ((address >= adev->gmc.mc_vram_size) || - (address >= RAS_UMC_INJECT_ADDR_LIMIT)) { + ret = amdgpu_ras_check_bad_page(adev, address); + if (ret == -EINVAL) { dev_warn(adev->dev, - "RAS WARN: input address 0x%llx is invalid.\n", - address); + "RAS WARN: input address 0x%llx is invalid.\n", + address); return -EINVAL; - } - - if (amdgpu_ras_check_bad_page(adev, address)) { + } else if (ret == 1) { dev_warn(adev->dev, - "RAS WARN: 0x%llx has already been marked as bad page!\n", - address); + "RAS WARN: 0x%llx has already been marked as bad page!\n", + address); return 0; } @@ -573,22 +571,16 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, ret = amdgpu_ras_feature_enable(adev, &data.head, 1); break; case 2: - if ((data.inject.address >= adev->gmc.mc_vram_size && - adev->gmc.mc_vram_size) || - (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { - dev_warn(adev->dev, "RAS WARN: input address " - "0x%llx is invalid.", + /* umc ce/ue error injection for a bad page is not allowed */ + if (data.head.block == AMDGPU_RAS_BLOCK__UMC) + ret = amdgpu_ras_check_bad_page(adev, data.inject.address); + if (ret == -EINVAL) { + dev_warn(adev->dev, "RAS WARN: input address 0x%llx is invalid.", data.inject.address); - ret = -EINVAL; break; - } - - /* umc ce/ue error injection for a bad page is not allowed */ - if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && - amdgpu_ras_check_bad_page(adev, data.inject.address)) { - dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has " - "already been marked as bad!\n", - data.inject.address); + } else if (ret == 1) { + dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has already been marked as bad!\n", + data.inject.address); break; } @@ -3194,18 +3186,24 @@ static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) return ret; } -static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, +static int amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, uint64_t addr) { struct ras_err_handler_data *data = con->eh_data; + struct amdgpu_device *adev = con->adev; int i; + if ((addr >= adev->gmc.mc_vram_size && + adev->gmc.mc_vram_size) || + (addr >= RAS_UMC_INJECT_ADDR_LIMIT)) + return -EINVAL; + addr >>= AMDGPU_GPU_PAGE_SHIFT; for (i = 0; i < data->count; i++) if (addr == data->bps[i].retired_page) - return true; + return 1; - return false; + return 0; } /* @@ -3213,11 +3211,11 @@ static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, * * Note: this check is only for umc block */ -static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, +static int amdgpu_ras_check_bad_page(struct amdgpu_device *adev, uint64_t addr) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); - bool ret = false; + int ret = 0; if (!con || !con->eh_data) return ret; From 1df4eac253149651e42b5942010322dcf871c9f6 Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Fri, 4 Jul 2025 17:12:24 +0800 Subject: [PATCH 0035/2653] drm/amdgpu: adjust the update of RAS bad page number One eeprom record may not map to unit number of bad pages, the accurate bad page number is gotten after bad page address check. Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 41 +++++++++++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 3 ++ .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 6 +-- 3 files changed, 30 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index f0ffa2f1d0e95..d49671a2ecd5b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2625,6 +2625,9 @@ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, } for (; i < data->count; i++) { + if (!data->bps[i].ts) + continue; + (*bps)[i] = (struct ras_badpage){ .bp = data->bps[i].retired_page, .size = AMDGPU_GPU_PAGE_SIZE, @@ -2638,7 +2641,7 @@ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; } - *count = data->count; + *count = con->bad_page_num; out: mutex_unlock(&con->recovery_lock); return ret; @@ -2866,8 +2869,11 @@ static int __amdgpu_ras_restore_bad_pages(struct amdgpu_device *adev, for (j = 0; j < count; j++) { if (amdgpu_ras_check_bad_page_unlock(con, - bps[j].retired_page << AMDGPU_GPU_PAGE_SHIFT)) + bps[j].retired_page << AMDGPU_GPU_PAGE_SHIFT)) { + data->count++; + data->space_left--; continue; + } if (!data->space_left && amdgpu_ras_realloc_eh_data_space(adev, data, 256)) { @@ -2880,6 +2886,7 @@ static int __amdgpu_ras_restore_bad_pages(struct amdgpu_device *adev, sizeof(struct eeprom_table_record)); data->count++; data->space_left--; + con->bad_page_num++; } return 0; @@ -3026,7 +3033,7 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, ret = __amdgpu_ras_convert_rec_array_from_rom(adev, &bps[i], &err_data, nps); if (ret) - control->ras_num_bad_pages -= adev->umc.retire_unit; + con->bad_page_num -= adev->umc.retire_unit; i += (adev->umc.retire_unit - 1); } else { break; @@ -3040,8 +3047,10 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, ret = __amdgpu_ras_convert_rec_from_rom(adev, &bps[i], &err_data, nps); if (ret) - control->ras_num_bad_pages -= adev->umc.retire_unit; + con->bad_page_num -= adev->umc.retire_unit; } + + con->eh_data->count_saved = con->eh_data->count; } else { ret = __amdgpu_ras_restore_bad_pages(adev, bps, pages); } @@ -3064,7 +3073,7 @@ int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev, struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct ras_err_handler_data *data; struct amdgpu_ras_eeprom_control *control; - int save_count, unit_num, bad_page_num, i; + int save_count, unit_num, i; if (!con || !con->eh_data) { if (new_cnt) @@ -3085,27 +3094,26 @@ int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev, mutex_lock(&con->recovery_lock); control = &con->eeprom_control; data = con->eh_data; - bad_page_num = control->ras_num_bad_pages; - save_count = data->count - bad_page_num; + unit_num = data->count / adev->umc.retire_unit - control->ras_num_recs; + save_count = con->bad_page_num - control->ras_num_bad_pages; mutex_unlock(&con->recovery_lock); - unit_num = save_count / adev->umc.retire_unit; if (new_cnt) *new_cnt = unit_num; /* only new entries are saved */ - if (save_count > 0) { + if (unit_num > 0) { /*old asics only save pa to eeprom like before*/ if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12) { if (amdgpu_ras_eeprom_append(control, - &data->bps[bad_page_num], save_count)) { + &data->bps[data->count_saved], unit_num)) { dev_err(adev->dev, "Failed to save EEPROM table data!"); return -EIO; } } else { for (i = 0; i < unit_num; i++) { if (amdgpu_ras_eeprom_append(control, - &data->bps[bad_page_num + + &data->bps[data->count_saved + i * adev->umc.retire_unit], 1)) { dev_err(adev->dev, "Failed to save EEPROM table data!"); return -EIO; @@ -3114,6 +3122,7 @@ int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev, } dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count); + data->count_saved = data->count; } return 0; @@ -3168,17 +3177,17 @@ static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) } } + ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs, true); + if (ret) + goto out; + ret = amdgpu_ras_eeprom_check(control); if (ret) goto out; /* HW not usable */ - if (amdgpu_ras_is_rma(adev)) { + if (amdgpu_ras_is_rma(adev)) ret = -EHWPOISON; - goto out; - } - - ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs, true); } out: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index 7f10a74021600..aa155cb5d58e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -573,6 +573,8 @@ struct amdgpu_ras { pid_t init_task_pid; char init_task_comm[TASK_COMM_LEN]; + + int bad_page_num; }; struct ras_fs_data { @@ -611,6 +613,7 @@ struct ras_err_handler_data { struct eeprom_table_record *bps; /* the count of entries */ int count; + int count_saved; /* the space can place new entries */ int space_left; }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 9bda9ad13f882..c3c908cc08595 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -743,8 +743,7 @@ amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, else control->ras_num_mca_recs += num; - control->ras_num_bad_pages = control->ras_num_pa_recs + - control->ras_num_mca_recs * adev->umc.retire_unit; + control->ras_num_bad_pages = con->bad_page_num; Out: kfree(buf); return res; @@ -1457,8 +1456,7 @@ int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) if (!__get_eeprom_i2c_addr(adev, control)) return -EINVAL; - control->ras_num_bad_pages = control->ras_num_pa_recs + - control->ras_num_mca_recs * adev->umc.retire_unit; + control->ras_num_bad_pages = ras->bad_page_num; if (hdr->header == RAS_TABLE_HDR_VAL) { dev_dbg(adev->dev, From ea376b669a48e29e6b456ab8fa0c4a4df8fca4ec Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Mon, 21 Jul 2025 18:52:36 +0530 Subject: [PATCH 0036/2653] drm/amd/display: Fix misuse of /** to /* in 'dce_i2c_hw.c' Fix the comment style before cntl_stuck_hw_workaround() by replacing '/**' with '/*' since it is not a kdoc comment. Fixes the below with gcc W=1: display/dc/dce/dce_i2c_hw.c:380: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * If we boot without an HDMI display, the I2C engine does not get initialized Fixes: c9130176a41e ("drm/amd/display: Workaround for stuck I2C arbitrage") Cc: Alvin Lee Cc: Dominik Kaszewski Cc: Ivan Lipski Cc: Harry Wentland Cc: Tom Chung Cc: Roman Li Cc: Alex Hung Cc: Aurabindo Pillai Signed-off-by: Srinivasan Shanmugam Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c index 4e06468a62842..0421b267a0b5f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c @@ -377,10 +377,16 @@ static bool setup_engine( } /** + * cntl_stuck_hw_workaround - Workaround for I2C engine stuck state + * @dce_i2c_hw: Pointer to dce_i2c_hw structure + * * If we boot without an HDMI display, the I2C engine does not get initialized * correctly. One of its symptoms is that SW_USE_I2C does not get cleared after - * acquire, so that after setting SW_DONE_USING_I2C on release, the engine gets + * acquire. After setting SW_DONE_USING_I2C on release, the engine gets * immediately reacquired by SW, preventing DMUB from using it. + * + * This function checks the I2C arbitration status and applies a release + * workaround if necessary. */ static void cntl_stuck_hw_workaround(struct dce_i2c_hw *dce_i2c_hw) { From 5cf91787bf76e18ff3d68ef6b69fc18262c87a10 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Thu, 24 Jul 2025 15:34:29 +0800 Subject: [PATCH 0037/2653] drm/amdgpu: support ras critical address check Support ras critical address check. Signed-off-by: YiPeng Chai Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 89 +++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 14 ++++ 2 files changed, 103 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index d49671a2ecd5b..b75a0dc22acec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -143,6 +143,10 @@ static int amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, uint64_t addr); static int amdgpu_ras_check_bad_page(struct amdgpu_device *adev, uint64_t addr); + +static void amdgpu_ras_critical_region_init(struct amdgpu_device *adev); +static void amdgpu_ras_critical_region_fini(struct amdgpu_device *adev); + #ifdef CONFIG_X86_MCE_AMD static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev); struct mce_notifier_adev_list { @@ -3728,6 +3732,8 @@ static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) kfree(data); mutex_unlock(&con->recovery_lock); + amdgpu_ras_critical_region_init(adev); + return 0; } /* recovery end */ @@ -4157,6 +4163,9 @@ int amdgpu_ras_init(struct amdgpu_device *adev) con->init_task_pid = task_pid_nr(current); get_task_comm(con->init_task_comm, current); + mutex_init(&con->critical_region_lock); + INIT_LIST_HEAD(&con->critical_region_head); + dev_info(adev->dev, "RAS INFO: ras initialized successfully, " "hardware ability[%x] ras_mask[%x]\n", adev->ras_hw_enabled, adev->ras_enabled); @@ -4436,6 +4445,9 @@ int amdgpu_ras_fini(struct amdgpu_device *adev) if (!adev->ras_enabled || !con) return 0; + amdgpu_ras_critical_region_fini(adev); + mutex_destroy(&con->critical_region_lock); + list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) { if (ras_node->ras_obj) { obj = ras_node->ras_obj; @@ -5380,3 +5392,80 @@ bool amdgpu_ras_is_rma(struct amdgpu_device *adev) return con->is_rma; } + +int amdgpu_ras_add_critical_region(struct amdgpu_device *adev, + struct amdgpu_bo *bo) +{ + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + struct amdgpu_vram_mgr_resource *vres; + struct ras_critical_region *region; + struct drm_buddy_block *block; + int ret = 0; + + if (!bo || !bo->tbo.resource) + return -EINVAL; + + vres = to_amdgpu_vram_mgr_resource(bo->tbo.resource); + + mutex_lock(&con->critical_region_lock); + + /* Check if the bo had been recorded */ + list_for_each_entry(region, &con->critical_region_head, node) + if (region->bo == bo) + goto out; + + /* Record new critical amdgpu bo */ + list_for_each_entry(block, &vres->blocks, link) { + region = kzalloc(sizeof(*region), GFP_KERNEL); + if (!region) { + ret = -ENOMEM; + goto out; + } + region->bo = bo; + region->start = amdgpu_vram_mgr_block_start(block); + region->size = amdgpu_vram_mgr_block_size(block); + list_add_tail(®ion->node, &con->critical_region_head); + } + +out: + mutex_unlock(&con->critical_region_lock); + + return ret; +} + +static void amdgpu_ras_critical_region_init(struct amdgpu_device *adev) +{ + amdgpu_ras_add_critical_region(adev, adev->mman.fw_reserved_memory); +} + +static void amdgpu_ras_critical_region_fini(struct amdgpu_device *adev) +{ + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + struct ras_critical_region *region, *tmp; + + mutex_lock(&con->critical_region_lock); + list_for_each_entry_safe(region, tmp, &con->critical_region_head, node) { + list_del(®ion->node); + kfree(region); + } + mutex_unlock(&con->critical_region_lock); +} + +bool amdgpu_ras_check_critical_address(struct amdgpu_device *adev, uint64_t addr) +{ + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + struct ras_critical_region *region; + bool ret = false; + + mutex_lock(&con->critical_region_lock); + list_for_each_entry(region, &con->critical_region_head, node) { + if ((region->start <= addr) && + (addr < (region->start + region->size))) { + ret = true; + break; + } + } + mutex_unlock(&con->critical_region_lock); + + return ret; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index aa155cb5d58e9..434e23c84962e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -496,6 +496,13 @@ struct ras_ecc_log_info { uint64_t prev_de_queried_count; }; +struct ras_critical_region { + struct list_head node; + struct amdgpu_bo *bo; + uint64_t start; + uint64_t size; +}; + struct amdgpu_ras { /* ras infrastructure */ /* for ras itself. */ @@ -575,6 +582,10 @@ struct amdgpu_ras { char init_task_comm[TASK_COMM_LEN]; int bad_page_num; + + struct list_head critical_region_head; + struct mutex critical_region_lock; + }; struct ras_fs_data { @@ -979,6 +990,9 @@ int amdgpu_ras_mark_ras_event_caller(struct amdgpu_device *adev, enum ras_event_ int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn); +int amdgpu_ras_add_critical_region(struct amdgpu_device *adev, struct amdgpu_bo *bo); +bool amdgpu_ras_check_critical_address(struct amdgpu_device *adev, uint64_t addr); + int amdgpu_ras_put_poison_req(struct amdgpu_device *adev, enum amdgpu_ras_block block, uint16_t pasid, pasid_notify pasid_fn, void *data, uint32_t reset); From d836535cde818c4a8e4a3afcd2dff64d26fffbbf Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 8 Jul 2025 13:17:18 +0530 Subject: [PATCH 0038/2653] drm/amdgpu: Update supported modes for GC v9.5.0 For GC v9.5.0 SOCs, both CPX and QPX compute modes are also supported in NPS2 mode. Signed-off-by: Lijo Lazar Acked-by: Mangesh Gadre Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c index 914cf4bfb0333..811124ff88a88 100644 --- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c +++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c @@ -227,6 +227,7 @@ static int __aqua_vanjaram_get_px_mode_info(struct amdgpu_xcp_mgr *xcp_mgr, uint16_t *nps_modes) { struct amdgpu_device *adev = xcp_mgr->adev; + uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); if (!num_xcp || !nps_modes || !(xcp_mgr->supp_xcp_modes & BIT(px_mode))) return -EINVAL; @@ -250,12 +251,14 @@ static int __aqua_vanjaram_get_px_mode_info(struct amdgpu_xcp_mgr *xcp_mgr, *num_xcp = 4; *nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | BIT(AMDGPU_NPS4_PARTITION_MODE); + if (gc_ver == IP_VERSION(9, 5, 0)) + *nps_modes |= BIT(AMDGPU_NPS2_PARTITION_MODE); break; case AMDGPU_CPX_PARTITION_MODE: *num_xcp = NUM_XCC(adev->gfx.xcc_mask); *nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | BIT(AMDGPU_NPS4_PARTITION_MODE); - if (amdgpu_sriov_vf(adev)) + if (gc_ver == IP_VERSION(9, 5, 0)) *nps_modes |= BIT(AMDGPU_NPS2_PARTITION_MODE); break; default: From 17d72e1a1b7d61c2cd73b98036273401b3c67192 Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Sun, 13 Jul 2025 01:28:02 +0530 Subject: [PATCH 0039/2653] drm/amdgpu: Check vcn sram load return value Log an error when vcn sram load fails in indirect mode and return the same error value. Signed-off-by: Sathishkumar S Reviewed-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 10 ++++++++-- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 10 ++++++++-- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 10 ++++++++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 10 ++++++++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 11 ++++++++--- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 10 ++++++++-- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 9 +++++++-- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 11 ++++++++--- 8 files changed, 63 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index 68b4371df0f1b..d1481e6d57ecd 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -865,6 +865,7 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; uint32_t rb_bufsz, tmp; + int ret; vcn_v2_0_enable_static_power_gating(vinst); @@ -948,8 +949,13 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) UVD, 0, mmUVD_MASTINT_EN), UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); - if (indirect) - amdgpu_vcn_psp_update_sram(adev, 0, 0); + if (indirect) { + ret = amdgpu_vcn_psp_update_sram(adev, 0, 0); + if (ret) { + dev_err(adev->dev, "vcn sram load failed %d\n", ret); + return ret; + } + } /* force RBC into idle state */ rb_bufsz = order_base_2(ring->ring_size); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index bc30a5326866c..d7b2668ab0d94 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -1035,6 +1035,7 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; struct amdgpu_ring *ring; uint32_t rb_bufsz, tmp; + int ret; /* disable register anti-hang mechanism */ WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, @@ -1125,8 +1126,13 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) VCN, 0, mmUVD_MASTINT_EN), UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); - if (indirect) - amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); + if (indirect) { + ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); + if (ret) { + dev_err(adev->dev, "vcn sram load failed %d\n", ret); + return ret; + } + } ring = &adev->vcn.inst[inst_idx].ring_dec; /* force RBC into idle state */ diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 4b8f4407047fc..a89662c97c9ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -1042,6 +1042,7 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; struct amdgpu_ring *ring; uint32_t rb_bufsz, tmp; + int ret; /* disable register anti-hang mechanism */ WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, @@ -1134,8 +1135,13 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); - if (indirect) - amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); + if (indirect) { + ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); + if (ret) { + dev_err(adev->dev, "vcn sram load failed %d\n", ret); + return ret; + } + } ring = &adev->vcn.inst[inst_idx].ring_dec; /* force RBC into idle state */ diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index f642a06a77b56..bf7d8c2e3d50a 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -1012,6 +1012,7 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; struct amdgpu_ring *ring; uint32_t tmp; + int ret; /* disable register anti-hang mechanism */ WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, @@ -1094,8 +1095,13 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); - if (indirect) - amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); + if (indirect) { + ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); + if (ret) { + dev_err(adev->dev, "vcn sram load failed %d\n", ret); + return ret; + } + } ring = &adev->vcn.inst[inst_idx].ring_enc[0]; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 3bda19b92cde7..6c4523d000532 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -851,7 +851,7 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_vcn_inst *vinst, volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; struct amdgpu_ring *ring; - int vcn_inst; + int vcn_inst, ret; uint32_t tmp; vcn_inst = GET_INST(VCN, inst_idx); @@ -944,8 +944,13 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_vcn_inst *vinst, VCN, 0, regUVD_MASTINT_EN), UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); - if (indirect) - amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); + if (indirect) { + ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); + if (ret) { + dev_err(adev->dev, "vcn sram load failed %d\n", ret); + return ret; + } + } ring = &adev->vcn.inst[inst_idx].ring_enc[0]; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index 039989ab452ad..5ab607962e799 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -926,6 +926,7 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; struct amdgpu_ring *ring; uint32_t tmp; + int ret; /* disable register anti-hang mechanism */ WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, @@ -1006,8 +1007,13 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, VCN, inst_idx, regUVD_MASTINT_EN), UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); - if (indirect) - amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); + if (indirect) { + ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); + if (ret) { + dev_err(adev->dev, "vcn sram load failed %d\n", ret); + return ret; + } + } ring = &adev->vcn.inst[inst_idx].ring_enc[0]; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index ec0268b5666cc..d74832f28b106 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -713,6 +713,7 @@ static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, volatile struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; struct amdgpu_ring *ring; uint32_t tmp; + int ret; /* disable register anti-hang mechanism */ WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, @@ -766,8 +767,12 @@ static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, VCN, inst_idx, regUVD_MASTINT_EN), UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); - if (indirect) - amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); + if (indirect) { + ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); + dev_err(adev->dev, "%s: vcn sram load failed %d\n", __func__, ret); + if (ret) + return ret; + } ring = &adev->vcn.inst[inst_idx].ring_enc[0]; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c index cdefd7fcb0da6..d8bbb93767318 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c @@ -605,7 +605,7 @@ static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst *vinst, adev->vcn.inst[inst_idx].fw_shared.cpu_addr; struct amdgpu_ring *ring; struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__PAUSE}; - int vcn_inst; + int vcn_inst, ret; uint32_t tmp; vcn_inst = GET_INST(VCN, inst_idx); @@ -666,8 +666,13 @@ static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst *vinst, VCN, 0, regUVD_MASTINT_EN), UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); - if (indirect) - amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); + if (indirect) { + ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); + if (ret) { + dev_err(adev->dev, "vcn sram load failed %d\n", ret); + return ret; + } + } /* resetting ring, fw should not check RB ring */ fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; From 8a0d2e0ef7f1795cd5261ac6cf27daddf75ae887 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Tue, 22 Jul 2025 14:17:29 +0800 Subject: [PATCH 0040/2653] drm/amdgpu: add critical address check for bad page retirement Add critical address check for bad page retirement. Signed-off-by: YiPeng Chai Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index b75a0dc22acec..1e31ef5592f22 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2637,6 +2637,11 @@ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, .size = AMDGPU_GPU_PAGE_SIZE, .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, }; + + if (amdgpu_ras_check_critical_address(adev, + data->bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT)) + continue; + status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr, data->bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT); if (status == -EBUSY) @@ -5356,6 +5361,9 @@ int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn) uint64_t start = pfn << AMDGPU_GPU_PAGE_SHIFT; int ret = 0; + if (amdgpu_ras_check_critical_address(adev, start)) + return 0; + mutex_lock(&con->page_rsv_lock); ret = amdgpu_vram_mgr_query_page_status(mgr, start); if (ret == -ENOENT) From 1a2a6809053e6b1fecdf6391251c3f3df72e4b33 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Thu, 24 Jul 2025 15:16:18 +0800 Subject: [PATCH 0041/2653] drm/amd/amdgpu: fix missing lock for cper.ring->rptr/wptr access Add lock protection for 'ring->wptr'/'ring->rptr' to ensure the correct execution. Fixes: 8652920d2c00 ("drm/amdgpu: add mutex lock for cper ring") Signed-off-by: Yang Wang Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c index 15dde1f503284..25252231a68a9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c @@ -459,7 +459,7 @@ static u32 amdgpu_cper_ring_get_ent_sz(struct amdgpu_ring *ring, u64 pos) void amdgpu_cper_ring_write(struct amdgpu_ring *ring, void *src, int count) { - u64 pos, wptr_old, rptr = *ring->rptr_cpu_addr & ring->ptr_mask; + u64 pos, wptr_old, rptr; int rec_cnt_dw = count >> 2; u32 chunk, ent_sz; u8 *s = (u8 *)src; @@ -472,9 +472,11 @@ void amdgpu_cper_ring_write(struct amdgpu_ring *ring, void *src, int count) return; } + mutex_lock(&ring->adev->cper.ring_lock); + wptr_old = ring->wptr; + rptr = *ring->rptr_cpu_addr & ring->ptr_mask; - mutex_lock(&ring->adev->cper.ring_lock); while (count) { ent_sz = amdgpu_cper_ring_get_ent_sz(ring, ring->wptr); chunk = umin(ent_sz, count); From 1c223363d924c70b74e1ec6270997ce2c4aa6477 Mon Sep 17 00:00:00 2001 From: Frank Min Date: Wed, 4 Jun 2025 21:39:34 +0800 Subject: [PATCH 0042/2653] drm/amdgpu: add kicker fws loading for gfx12/smu14/psp14 1. Add kicker firmwares loading for gfx12/smu14/psp14 2. Register additional MODULE_FIRMWARE entries for kicker fws - gc_12_0_1_rlc_kicker.bin - gc_12_0_1_imu_kicker.bin - psp_14_0_3_sos_kicker.bin - psp_14_0_3_ta_kicker.bin - smu_14_0_3_kicker.bin Signed-off-by: Frank Min Reviewed-by: Gui Chengming --- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 14 ++++++++++---- drivers/gpu/drm/amd/amdgpu/imu_v12_0.c | 11 ++++++++--- drivers/gpu/drm/amd/amdgpu/psp_v14_0.c | 2 ++ drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 11 ++++++++--- 5 files changed, 29 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index a0b50a8ac9c4e..e96f24e9ad571 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -32,6 +32,7 @@ static const struct kicker_device kicker_device_list[] = { {0x744B, 0x00}, + {0x7551, 0xC8} }; static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 7220ed2fa2a33..f54cbb8907b3f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -79,6 +79,7 @@ MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin"); MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin"); MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin"); MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin"); +MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc_kicker.bin"); MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin"); static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = { @@ -586,7 +587,7 @@ static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char * static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) { - char ucode_prefix[15]; + char ucode_prefix[30]; int err; const struct rlc_firmware_header_v2_0 *rlc_hdr; uint16_t version_major; @@ -613,9 +614,14 @@ static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK); if (!amdgpu_sriov_vf(adev)) { - err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, - AMDGPU_UCODE_REQUIRED, - "amdgpu/%s_rlc.bin", ucode_prefix); + if (amdgpu_is_kicker_fw(adev)) + err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, + AMDGPU_UCODE_REQUIRED, + "amdgpu/%s_rlc_kicker.bin", ucode_prefix); + else + err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, + AMDGPU_UCODE_REQUIRED, + "amdgpu/%s_rlc.bin", ucode_prefix); if (err) goto out; rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c index 8cb6b1854d245..58cd87db80619 100644 --- a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c @@ -34,12 +34,13 @@ MODULE_FIRMWARE("amdgpu/gc_12_0_0_imu.bin"); MODULE_FIRMWARE("amdgpu/gc_12_0_1_imu.bin"); +MODULE_FIRMWARE("amdgpu/gc_12_0_1_imu_kicker.bin"); #define TRANSFER_RAM_MASK 0x001c0000 static int imu_v12_0_init_microcode(struct amdgpu_device *adev) { - char ucode_prefix[15]; + char ucode_prefix[30]; int err; const struct imu_firmware_header_v1_0 *imu_hdr; struct amdgpu_firmware_info *info = NULL; @@ -47,8 +48,12 @@ static int imu_v12_0_init_microcode(struct amdgpu_device *adev) DRM_DEBUG("\n"); amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); - err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, - "amdgpu/%s_imu.bin", ucode_prefix); + if (amdgpu_is_kicker_fw(adev)) + err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, + "amdgpu/%s_imu_kicker.bin", ucode_prefix); + else + err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, + "amdgpu/%s_imu.bin", ucode_prefix); if (err) goto out; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c index 36ef4a72ad1d5..38dfc5c19f2a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c @@ -34,7 +34,9 @@ MODULE_FIRMWARE("amdgpu/psp_14_0_2_sos.bin"); MODULE_FIRMWARE("amdgpu/psp_14_0_2_ta.bin"); MODULE_FIRMWARE("amdgpu/psp_14_0_3_sos.bin"); +MODULE_FIRMWARE("amdgpu/psp_14_0_3_sos_kicker.bin"); MODULE_FIRMWARE("amdgpu/psp_14_0_3_ta.bin"); +MODULE_FIRMWARE("amdgpu/psp_14_0_3_ta_kicker.bin"); MODULE_FIRMWARE("amdgpu/psp_14_0_5_toc.bin"); MODULE_FIRMWARE("amdgpu/psp_14_0_5_ta.bin"); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c index 76c1adda83dbc..f9b0938c57ea7 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c @@ -62,13 +62,14 @@ const int decoded_link_width[8] = {0, 1, 2, 4, 8, 12, 16, 32}; MODULE_FIRMWARE("amdgpu/smu_14_0_2.bin"); MODULE_FIRMWARE("amdgpu/smu_14_0_3.bin"); +MODULE_FIRMWARE("amdgpu/smu_14_0_3_kicker.bin"); #define ENABLE_IMU_ARG_GFXOFF_ENABLE 1 int smu_v14_0_init_microcode(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - char ucode_prefix[15]; + char ucode_prefix[30]; int err = 0; const struct smc_firmware_header_v1_0 *hdr; const struct common_firmware_header *header; @@ -79,8 +80,12 @@ int smu_v14_0_init_microcode(struct smu_context *smu) return 0; amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); - err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED, - "amdgpu/%s.bin", ucode_prefix); + if (amdgpu_is_kicker_fw(adev)) + err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED, + "amdgpu/%s_kicker.bin", ucode_prefix); + else + err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED, + "amdgpu/%s.bin", ucode_prefix); if (err) goto out; From 925f576e8bc836b6f8d4810da289a289e3e31bd0 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 25 Jul 2025 10:21:10 +0530 Subject: [PATCH 0043/2653] drm/amdgpu: Update external revid for GC v9.5.0 Use different external revid for GC v9.5.0 SOCs. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index c457be3a3c56f..9e74c9822e622 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -1218,6 +1218,8 @@ static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) AMD_PG_SUPPORT_JPEG; /*TODO: need a new external_rev_id for GC 9.4.4? */ adev->external_rev_id = adev->rev_id + 0x46; + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) + adev->external_rev_id = adev->rev_id + 0x50; break; default: /* FIXME: not supported yet */ From 82879151360257e8c15b92527fbf51cbca5313bc Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Thu, 24 Jul 2025 13:02:18 +0530 Subject: [PATCH 0044/2653] drm/amd/display: Reduce Stack Usage by moving 'audio_output' into 'stream_res' v4 The function `dp_retrain_link_dp_test` currently allocates a large audio_output array on the stack, causing the stack frame size to exceed the compiler limit (1080 bytes > 1024 bytes). This change prevents stack overflow issues: amdgpu/../display/dc/link/accessories/link_dp_cts.c:65:13: warning: stack frame size (1080) exceeds limit (1024) in 'dp_retrain_link_dp_test' [-Wframe-larger-than] static void dp_retrain_link_dp_test(struct dc_link *link, v2: Move audio-related data like `audio_output` is kept "per pipe" to manage the audio for that specific display pipeline/display output path (stream). (Wenjing) v3: Update in all the places where `build_audio_output` is currently called with a separate audio_output variable on the stack & wherever `audio_output` is passed to other functions `dce110_apply_single_controller_ctx_to_hw()` & `dce110_setup_audio_dto()` (like `az_configure`, `wall_dto_setup`) replace with usage of `pipe_ctx->stream_res.audio_output` to centralize audio data per pipe. v4: Remove empty lines before `build_audio_output`. (Alex) 'Fixes: 9437059b4bfb ("drm/amd/display: Fix Link Override Sequencing When Switching Between DIO/HPO")' Cc: Wayne Lin Cc: George Shen Cc: Michael Strauss Cc: Alvin Lee Cc: Ray Wu Cc: Wenjing Liu Cc: Harry Wentland Cc: Tom Chung Cc: Roman Li Cc: Alex Hung Cc: Aurabindo Pillai Signed-off-by: Srinivasan Shanmugam Reviewed-by: Wenjing Liu --- .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 32 ++++++++----------- .../gpu/drm/amd/display/dc/inc/core_types.h | 5 +-- .../display/dc/link/accessories/link_dp_cts.c | 12 +++---- .../dc/resource/dcn31/dcn31_resource.c | 5 ++- .../dc/resource/dcn31/dcn31_resource.h | 3 +- 5 files changed, 26 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 4ea13d0bf815e..c69194e04ff93 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -1600,19 +1600,17 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw( } if (pipe_ctx->stream_res.audio != NULL) { - struct audio_output audio_output = {0}; + build_audio_output(context, pipe_ctx, &pipe_ctx->stream_res.audio_output); - build_audio_output(context, pipe_ctx, &audio_output); - - link_hwss->setup_audio_output(pipe_ctx, &audio_output, + link_hwss->setup_audio_output(pipe_ctx, &pipe_ctx->stream_res.audio_output, pipe_ctx->stream_res.audio->inst); pipe_ctx->stream_res.audio->funcs->az_configure( pipe_ctx->stream_res.audio, pipe_ctx->stream->signal, - &audio_output.crtc_info, + &pipe_ctx->stream_res.audio_output.crtc_info, &pipe_ctx->stream->audio_info, - &audio_output.dp_link_info); + &pipe_ctx->stream_res.audio_output.dp_link_info); if (dc->config.disable_hbr_audio_dp2) if (pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio && @@ -2386,9 +2384,7 @@ static void dce110_setup_audio_dto( if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) continue; if (pipe_ctx->stream_res.audio != NULL) { - struct audio_output audio_output; - - build_audio_output(context, pipe_ctx, &audio_output); + build_audio_output(context, pipe_ctx, &pipe_ctx->stream_res.audio_output); if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { struct dtbclk_dto_params dto_params = {0}; @@ -2399,14 +2395,14 @@ static void dce110_setup_audio_dto( pipe_ctx->stream_res.audio->funcs->wall_dto_setup( pipe_ctx->stream_res.audio, pipe_ctx->stream->signal, - &audio_output.crtc_info, - &audio_output.pll_info); + &pipe_ctx->stream_res.audio_output.crtc_info, + &pipe_ctx->stream_res.audio_output.pll_info); } else pipe_ctx->stream_res.audio->funcs->wall_dto_setup( pipe_ctx->stream_res.audio, pipe_ctx->stream->signal, - &audio_output.crtc_info, - &audio_output.pll_info); + &pipe_ctx->stream_res.audio_output.crtc_info, + &pipe_ctx->stream_res.audio_output.pll_info); break; } } @@ -2426,15 +2422,15 @@ static void dce110_setup_audio_dto( continue; if (pipe_ctx->stream_res.audio != NULL) { - struct audio_output audio_output = {0}; - - build_audio_output(context, pipe_ctx, &audio_output); + build_audio_output(context, + pipe_ctx, + &pipe_ctx->stream_res.audio_output); pipe_ctx->stream_res.audio->funcs->wall_dto_setup( pipe_ctx->stream_res.audio, pipe_ctx->stream->signal, - &audio_output.crtc_info, - &audio_output.pll_info); + &pipe_ctx->stream_res.audio_output.crtc_info, + &pipe_ctx->stream_res.audio_output.pll_info); break; } } diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index f0d7185153b2a..f896cce87b8d4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -228,8 +228,7 @@ struct resource_funcs { enum dc_status (*update_dc_state_for_encoder_switch)(struct dc_link *link, struct dc_link_settings *link_setting, uint8_t pipe_count, - struct pipe_ctx *pipes, - struct audio_output *audio_output); + struct pipe_ctx *pipes); }; struct audio_support{ @@ -361,6 +360,8 @@ struct stream_resource { uint8_t gsl_group; struct test_pattern_params test_pattern_params; + + struct audio_output audio_output; }; struct plane_resource { diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c index 2956c2b3ad1aa..b12d61701d4d9 100644 --- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c +++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c @@ -75,7 +75,6 @@ static void dp_retrain_link_dp_test(struct dc_link *link, bool is_hpo_acquired; uint8_t count; int i; - struct audio_output audio_output[MAX_PIPES]; needs_divider_update = (link->dc->link_srv->dp_get_encoding_format(link_setting) != link->dc->link_srv->dp_get_encoding_format((const struct dc_link_settings *) &link->cur_link_settings)); @@ -99,7 +98,7 @@ static void dp_retrain_link_dp_test(struct dc_link *link, if (needs_divider_update && link->dc->res_pool->funcs->update_dc_state_for_encoder_switch) { link->dc->res_pool->funcs->update_dc_state_for_encoder_switch(link, link_setting, count, - *pipes, &audio_output[0]); + *pipes); for (i = 0; i < count; i++) { pipes[i]->clock_source->funcs->program_pix_clk( pipes[i]->clock_source, @@ -111,15 +110,16 @@ static void dp_retrain_link_dp_test(struct dc_link *link, const struct link_hwss *link_hwss = get_link_hwss( link, &pipes[i]->link_res); - link_hwss->setup_audio_output(pipes[i], &audio_output[i], - pipes[i]->stream_res.audio->inst); + link_hwss->setup_audio_output(pipes[i], + &pipes[i]->stream_res.audio_output, + pipes[i]->stream_res.audio->inst); pipes[i]->stream_res.audio->funcs->az_configure( pipes[i]->stream_res.audio, pipes[i]->stream->signal, - &audio_output[i].crtc_info, + &pipes[i]->stream_res.audio_output.crtc_info, &pipes[i]->stream->audio_info, - &audio_output[i].dp_link_info); + &pipes[i]->stream_res.audio_output.dp_link_info); if (link->dc->config.disable_hbr_audio_dp2 && pipes[i]->stream_res.audio->funcs->az_disable_hbr_audio && diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c index 3ed7f50554e21..ca17e5d8fdc2a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c @@ -2239,8 +2239,7 @@ struct resource_pool *dcn31_create_resource_pool( enum dc_status dcn31_update_dc_state_for_encoder_switch(struct dc_link *link, struct dc_link_settings *link_setting, uint8_t pipe_count, - struct pipe_ctx *pipes, - struct audio_output *audio_output) + struct pipe_ctx *pipes) { struct dc_state *state = link->dc->current_state; int i; @@ -2255,7 +2254,7 @@ enum dc_status dcn31_update_dc_state_for_encoder_switch(struct dc_link *link, // Setup audio if (pipes[i].stream_res.audio != NULL) - build_audio_output(state, &pipes[i], &audio_output[i]); + build_audio_output(state, &pipes[i], &pipes[i].stream_res.audio_output); } #else /* This DCN requires rate divider updates and audio reprogramming to allow DP1<-->DP2 link rate switching, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h index c32c85ef0ba47..7e8fde65528f1 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h @@ -69,8 +69,7 @@ unsigned int dcn31_get_det_buffer_size( enum dc_status dcn31_update_dc_state_for_encoder_switch(struct dc_link *link, struct dc_link_settings *link_setting, uint8_t pipe_count, - struct pipe_ctx *pipes, - struct audio_output *audio_output); + struct pipe_ctx *pipes); /*temp: B0 specific before switch to dcn313 headers*/ #ifndef regPHYPLLF_PIXCLK_RESYNC_CNTL From 191267a88ab05e33b80fec474ff7e27c5bb64c48 Mon Sep 17 00:00:00 2001 From: Karthi Kandasamy Date: Thu, 26 Jun 2025 15:10:01 +0200 Subject: [PATCH 0045/2653] drm/amd/display: Add DC EDID read policy struct [Why & How] Add a struct to allow DMs that utilize the EDID parser in DC to modify the default settings. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Karthi Kandasamy Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc_types.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 375ca2f13b7ac..2a86058c3bfa6 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -563,6 +563,12 @@ struct dc_info_packet_128 { uint8_t sb[128]; }; +struct dc_edid_read_policy { + uint32_t max_retry_count; + uint32_t delay_time_ms; + uint32_t ignore_checksum; +}; + #define DC_PLANE_UPDATE_TIMES_MAX 10 struct dc_plane_flip_time { From af4a8a957879ce98e64e66eaf7710d1b40f57189 Mon Sep 17 00:00:00 2001 From: Cruise Hung Date: Wed, 9 Jul 2025 19:04:31 +0800 Subject: [PATCH 0046/2653] drm/amd/display: Remove check DPIA HPD status for BW Allocation [Why & How] Link hpd_status is for embedded DPIA only. Do not check hpd_status for BW allocation logic. Reviewed-by: Meenakshikumar Somasundaram Signed-off-by: Cruise Hung Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/link/link_validation.c | 6 +- .../dc/link/protocols/link_dp_dpia_bw.c | 60 +++++++++---------- 2 files changed, 32 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c index aecaf37eee352..acdc162de5353 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c @@ -408,8 +408,10 @@ enum dc_status link_validate_dp_tunnel_bandwidth(const struct dc *dc, const stru link = stream->link; if (!(link && (stream->signal == SIGNAL_TYPE_DISPLAY_PORT - || stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) - && link->hpd_status)) + || stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST))) + continue; + + if ((link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) && (link->hpd_status == false)) continue; dp_tunnel_settings = get_dp_tunnel_settings(new_ctx, stream); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c index 819bf2d8ba530..906d85ca89569 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c @@ -48,8 +48,7 @@ */ static bool link_dp_is_bw_alloc_available(struct dc_link *link) { - return (link && link->hpd_status - && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling + return (link && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc && link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support); } @@ -226,35 +225,35 @@ bool link_dpia_enable_usb4_dp_bw_alloc_mode(struct dc_link *link) bool ret = false; uint8_t val; - if (link->hpd_status) { - val = DPTX_BW_ALLOC_MODE_ENABLE | DPTX_BW_ALLOC_UNMASK_IRQ; + val = DPTX_BW_ALLOC_MODE_ENABLE | DPTX_BW_ALLOC_UNMASK_IRQ; - if (core_link_write_dpcd(link, DPTX_BW_ALLOCATION_MODE_CONTROL, &val, sizeof(uint8_t)) == DC_OK) { - DC_LOG_DEBUG("%s: link[%d] DPTX BW allocation mode enabled", __func__, link->link_index); + if (core_link_write_dpcd(link, DPTX_BW_ALLOCATION_MODE_CONTROL, &val, sizeof(uint8_t)) == DC_OK) { + DC_LOG_DEBUG("%s: link[%d] DPTX BW allocation mode enabled", __func__, link->link_index); - retrieve_usb4_dp_bw_allocation_info(link); + retrieve_usb4_dp_bw_allocation_info(link); - if (link->dpia_bw_alloc_config.nrd_max_link_rate && link->dpia_bw_alloc_config.nrd_max_lane_count) { - link->reported_link_cap.link_rate = link->dpia_bw_alloc_config.nrd_max_link_rate; - link->reported_link_cap.lane_count = link->dpia_bw_alloc_config.nrd_max_lane_count; - } + if ( + link->dpia_bw_alloc_config.nrd_max_link_rate + && link->dpia_bw_alloc_config.nrd_max_lane_count) { + link->reported_link_cap.link_rate = link->dpia_bw_alloc_config.nrd_max_link_rate; + link->reported_link_cap.lane_count = link->dpia_bw_alloc_config.nrd_max_lane_count; + } - link->dpia_bw_alloc_config.bw_alloc_enabled = true; - ret = true; - - if (link->dc->debug.dpia_debug.bits.enable_usb4_bw_zero_alloc_patch) { - /* - * During DP tunnel creation, the CM preallocates BW - * and reduces the estimated BW of other DPIAs. - * The CM releases the preallocation only when the allocation is complete. - * Perform a zero allocation to make the CM release the preallocation - * and correctly update the estimated BW for all DPIAs per host router. - */ - link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, 0); - } - } else - DC_LOG_DEBUG("%s: link[%d] failed to enable DPTX BW allocation mode", __func__, link->link_index); - } + link->dpia_bw_alloc_config.bw_alloc_enabled = true; + ret = true; + + if (link->dc->debug.dpia_debug.bits.enable_usb4_bw_zero_alloc_patch) { + /* + * During DP tunnel creation, the CM preallocates BW + * and reduces the estimated BW of other DPIAs. + * The CM releases the preallocation only when the allocation is complete. + * Perform a zero allocation to make the CM release the preallocation + * and correctly update the estimated BW for all DPIAs per host router. + */ + link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, 0); + } + } else + DC_LOG_DEBUG("%s: link[%d] failed to enable DPTX BW allocation mode", __func__, link->link_index); return ret; } @@ -297,15 +296,12 @@ void dpia_handle_usb4_bandwidth_allocation_for_link(struct dc_link *link, int pe { if (link && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling && link->dpia_bw_alloc_config.bw_alloc_enabled) { - //1. Hot Plug - if (link->hpd_status && peak_bw > 0) { + if (peak_bw > 0) { // If DP over USB4 then we need to check BW allocation link->dpia_bw_alloc_config.link_max_bw = peak_bw; link_dpia_send_bw_alloc_request(link, peak_bw); - } - //2. Cold Unplug - else if (!link->hpd_status) + } else dpia_bw_alloc_unplug(link); } } From e686322f73e406d2f2c52bcee1851ba56200ae90 Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Fri, 11 Jul 2025 15:23:35 -0400 Subject: [PATCH 0047/2653] drm/amd/display: Add comma to last entry of enum for consistency [Why&How] Add comma to last entry of enum for consistency. Reviewed-by: Jun Lei Signed-off-by: Alvin Lee Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index f896cce87b8d4..4387de044469b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -434,7 +434,7 @@ enum p_state_switch_method { P_STATE_V_ACTIVE, P_STATE_SUB_VP, P_STATE_DRR_SUB_VP, - P_STATE_V_BLANK_SUB_VP + P_STATE_V_BLANK_SUB_VP, }; struct pipe_ctx { From e6e95393cf5c1c0309131f2d00e2df6a139d4ac0 Mon Sep 17 00:00:00 2001 From: Michael Strauss Date: Wed, 12 Feb 2025 14:08:08 -0500 Subject: [PATCH 0048/2653] drm/amd/display: Move setup_stream_attribute [WHY] If symclk RCO is enabled, stream encoder may not be receiving an ungated clock by the time we attempt to set stream attributes when setting dpms on. Since the clock is gated, register writes to the stream encoder fail. [HOW] Move set_stream_attribute call into enable_stream, just after the point where symclk32_se is ungated. Logically there is no need to set stream attributes as early as is currently done in link_set_dpms_on, so this should have no impact beyond the RCO fix. Reviewed-by: Ovidiu (Ovi) Bunea Signed-off-by: Michael Strauss Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 1 + drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 ++ drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 2 ++ drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 3 --- .../drm/amd/display/dc/virtual/virtual_stream_encoder.c | 7 +++++++ 5 files changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index c69194e04ff93..32fd6bdc18d73 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -671,6 +671,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) uint32_t early_control = 0; struct timing_generator *tg = pipe_ctx->stream_res.tg; + link_hwss->setup_stream_attribute(pipe_ctx); link_hwss->setup_stream_encoder(pipe_ctx); dc->hwss.update_info_frame(pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 3207addbd4ebb..7d24fa1517bf1 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -3054,6 +3054,8 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) link_enc->transmitter - TRANSMITTER_UNIPHY_A); } + link_hwss->setup_stream_attribute(pipe_ctx); + if (dc->res_pool->dccg->funcs->set_pixel_rate_div) dc->res_pool->dccg->funcs->set_pixel_rate_div( dc->res_pool->dccg, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index cc9f40d97af2f..fb949aeb12443 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -965,6 +965,8 @@ void dcn401_enable_stream(struct pipe_ctx *pipe_ctx) } } + link_hwss->setup_stream_attribute(pipe_ctx); + if (dc->res_pool->dccg->funcs->set_pixel_rate_div) { dc->res_pool->dccg->funcs->set_pixel_rate_div( dc->res_pool->dccg, diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index 8c8682f743d6f..cb80b45999360 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -2458,7 +2458,6 @@ void link_set_dpms_on( struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; - const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); bool apply_edp_fast_boot_optimization = pipe_ctx->stream->apply_edp_fast_boot_optimization; @@ -2502,8 +2501,6 @@ void link_set_dpms_on( pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); } - link_hwss->setup_stream_attribute(pipe_ctx); - pipe_ctx->stream->apply_edp_fast_boot_optimization = false; // Enable VPG before building infoframe diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c index ad088d70e1893..6ffc74fc9dcd8 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c @@ -44,6 +44,11 @@ static void virtual_stream_encoder_dvi_set_stream_attribute( struct dc_crtc_timing *crtc_timing, bool is_dual_link) {} +static void virtual_stream_encoder_lvds_set_stream_attribute( + struct stream_encoder *enc, + struct dc_crtc_timing *crtc_timing) +{} + static void virtual_stream_encoder_set_throttled_vcp_size( struct stream_encoder *enc, struct fixed31_32 avg_time_slots_per_mtp) @@ -115,6 +120,8 @@ static const struct stream_encoder_funcs virtual_str_enc_funcs = { virtual_stream_encoder_hdmi_set_stream_attribute, .dvi_set_stream_attribute = virtual_stream_encoder_dvi_set_stream_attribute, + .lvds_set_stream_attribute = + virtual_stream_encoder_lvds_set_stream_attribute, .set_throttled_vcp_size = virtual_stream_encoder_set_throttled_vcp_size, .update_hdmi_info_packets = From b54ee2872e785f6ae2df9215a0819335c0f3fefb Mon Sep 17 00:00:00 2001 From: Jingwen Zhu Date: Mon, 14 Jul 2025 16:18:19 +0800 Subject: [PATCH 0049/2653] drm/amd/display: Add a config flag for limited_pll_vco [Why/How] Added a new config flag to pass to the DMUB during boot. This workaround will solves black screen issue on reboot. Reviewed-by: Hansen Dsouza Signed-off-by: Jingwen Zhu Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 + drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 ++- drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index 0bafb67107618..87b761ac3135d 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -316,6 +316,7 @@ struct dmub_srv_hw_params { bool disable_sldo_opt; bool enable_non_transparent_setconfig; bool lower_hbr3_phy_ssc; + bool override_hbr3_pll_vco; }; /** diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index a89bf08ffd379..e2e5f71c03f2b 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -843,7 +843,8 @@ union dmub_fw_boot_options { uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ - uint32_t reserved : 6; /**< reserved */ + uint32_t override_hbr3_pll_vco: 1; /**< 1 to override the hbr3 pll vco to 0 */ + uint32_t reserved : 5; /**< reserved */ } bits; /**< boot bits */ uint32_t all; /**< 32-bit access to bits */ }; diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c index 3f38db752b844..4777c7203b2c2 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c @@ -377,6 +377,7 @@ void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported; boot_options.bits.power_optimization = params->power_optimization; boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc; + boot_options.bits.override_hbr3_pll_vco = params->override_hbr3_pll_vco; boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic == DMUB_ASIC_DCN31B) ? 1 : 0; From 98b2344b3a5f9e5cf1c2206bde6ad8a8cfa89f41 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Mon, 14 Jul 2025 14:37:33 -0400 Subject: [PATCH 0050/2653] drm/amd/display: Disable dsc_power_gate for dcn314 by default [Why] "REG_WAIT timeout 1us * 1000 tries - dcn314_dsc_pg_control line" warnings seen after resuming from s2idle. DCN314 has issues with DSC power gating that cause REG_WAIT timeouts when attempting to power down DSC blocks. [How] Disable dsc_power_gate for dcn314 by default. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Roman Li Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c index de708fdc1e809..663c49cce4aa3 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c @@ -926,6 +926,7 @@ static const struct dc_debug_options debug_defaults_drv = { .seamless_boot_odm_combine = true, .enable_legacy_fast_update = true, .using_dml2 = false, + .disable_dsc_power_gate = true, }; static const struct dc_panel_config panel_config_defaults = { From 82626fcc8486d2b2af5c07cec5141dd5e07152a5 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Fri, 27 Jun 2025 16:58:26 -0500 Subject: [PATCH 0051/2653] drm/amd/display: Add missing SPDX license identifier [Why] All files should be properly classified. [How] Add missing SPDX-License-Identifier. Reviewed-by: Sun peng (Leo) Li Signed-off-by: Mario Limonciello Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h | 1 + 22 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 28ced6c47e8aa..2983663625580 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: MIT /* * Copyright 2015 Advanced Micro Devices, Inc. * @@ -10392,6 +10393,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) if (amdgpu_dm_crc_window_is_activated(crtc)) { uint8_t cnt; + spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); for (cnt = 0; cnt < MAX_CRC_WINDOW_NUM; cnt++) { if (acrtc->dm_irq_params.window_param[cnt].enable) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index b937da0a4e4a0..67c3a7a967f2f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: MIT */ /* * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index ebabfe3a512f4..ff97785b60a27 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: MIT /* * Copyright 2018 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index 033bd817d871a..e20aa74380665 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: MIT /* * Copyright 2015 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h index 3da056c8d20bb..95bdb8699d7fa 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: MIT */ /* * Copyright 2019 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index b726bcd18e298..484691335fd62 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: MIT /* * Copyright 2018 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h index 071200473c27c..122cdc124b3b7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: MIT */ /* * Copyright 2018 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index c16962256514e..4a973c85cb322 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: MIT /* * Copyright 2019 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h index 69b445b011c8c..4faa344f196e7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: MIT */ /* * Copyright 2019 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 9e3e51a2dc496..fe100e4c98010 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: MIT /* * Copyright 2015 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index b61e210f62464..a1c722112c224 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: MIT /* * Copyright 2015 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h index ba17c23b27064..4f6b58f4f90d7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: MIT */ /* * Copyright 2015 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h index 6c9de834455b3..3c9995275cbda 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: MIT */ /* * Copyright 2020 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 7187d5aedf0a5..137f18d41f1b1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: MIT /* * Copyright 2012-15 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h index 600d6e2210111..65f76a7d00dbf 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: MIT */ /* * Copyright 2012-15 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c index 848c5b4bb301a..e5771f490f2e3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: MIT /* * Copyright 2018 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c index f984cb0cb8897..5d7098c337d0a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: MIT /* * Copyright 2021 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h index e2366321a3c1b..4fb8626913cfb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: MIT */ /* * Copyright 2021 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c index 41f07f13a7b57..82ea3fe5e764f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: MIT /* * Copyright 2023 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h index 8126bdb1eb6b8..73b6c67ae5e76 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: MIT */ /* * Copyright 2021 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c index 0005f5f8f34f6..132de4071efd4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c @@ -1,3 +1,4 @@ +//SPDX-License-Identifier: MIT /* * Copyright 2015 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h index 95f890fda8aaa..aa56fd6d56c34 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h @@ -1,3 +1,4 @@ +//SPDX-License-Identifier: MIT /* * Copyright 2018 Advanced Micro Devices, Inc. * From f060cc5211e7db0357289d2380f54e2b8fbd88a3 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Sun, 6 Jul 2025 09:55:58 -0500 Subject: [PATCH 0052/2653] drm/amd/display: Drop unused include [Why] Extra includes slow down compile time. [How] Drop unnecessary include. Reviewed-by: Sun peng (Leo) Li Signed-off-by: Mario Limonciello Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c index 5d7098c337d0a..d5a3768bf002a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c @@ -27,7 +27,6 @@ #include "amdgpu_dm_psr.h" #include "dc_dmub_srv.h" #include "dc.h" -#include "dm_helpers.h" #include "amdgpu_dm.h" #include "modules/power/power_helpers.h" From ebb97b7b3f3fe2875821d56361ab7aa81cacb55a Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Fri, 27 Jun 2025 16:55:03 -0500 Subject: [PATCH 0053/2653] drm/amd/display: Remove unnecessary whitespace [Why] Whitespace before a new line is unnecessary. [How] Remove whitespace. Reviewed-by: Sun peng (Leo) Li Signed-off-by: Mario Limonciello Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2983663625580..dbda59b86f669 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6386,13 +6386,15 @@ static void fill_stream_properties_from_drm_display_mode( (struct drm_connector *)connector, mode_in); if (err < 0) - drm_warn_once(connector->dev, "Failed to setup avi infoframe on connector %s: %zd \n", connector->name, err); + drm_warn_once(connector->dev, "Failed to setup avi infoframe on connector %s: %zd\n", + connector->name, err); timing_out->vic = avi_frame.video_code; err = drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); if (err < 0) - drm_warn_once(connector->dev, "Failed to setup vendor infoframe on connector %s: %zd \n", connector->name, err); + drm_warn_once(connector->dev, "Failed to setup vendor infoframe on connector %s: %zd\n", + connector->name, err); timing_out->hdmi_vic = hv_frame.vic; } From 26cdf96e8f3b9116a1a3fc29bc74079577f7e24a Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Fri, 27 Jun 2025 16:53:39 -0500 Subject: [PATCH 0054/2653] drm/amd/display: Remove unnecessary includes [Why] Extra includes aren't needed for compilation and can slow down the preprocessor. [How] Drop unneeded includes. Reviewed-by: Sun peng (Leo) Li Signed-off-by: Mario Limonciello Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ------------ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 1 - 2 files changed, 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index dbda59b86f669..a14a656df31b2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -40,13 +40,11 @@ #include "dc/dc_stat.h" #include "dc/dc_state.h" #include "amdgpu_dm_trace.h" -#include "dpcd_defs.h" #include "link/protocols/link_dpcd.h" #include "link_service_types.h" #include "link/protocols/link_dp_capability.h" #include "link/protocols/link_ddc.h" -#include "vid.h" #include "amdgpu.h" #include "amdgpu_display.h" #include "amdgpu_ucode.h" @@ -57,7 +55,6 @@ #include "amdgpu_dm_hdcp.h" #include #include "amdgpu_dm_wb.h" -#include "amdgpu_pm.h" #include "amdgpu_atombios.h" #include "amd_shared.h" @@ -103,15 +100,6 @@ #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" -#include "dcn/dcn_1_0_offset.h" -#include "dcn/dcn_1_0_sh_mask.h" -#include "soc15_hw_ip.h" -#include "soc15_common.h" -#include "vega10_ip_offset.h" - -#include "gc/gc_11_0_0_offset.h" -#include "gc/gc_11_0_0_sh_mask.h" - #include "modules/inc/mod_freesync.h" #include "modules/power/power_helpers.h" diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index ff97785b60a27..c7387af725d6a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -28,7 +28,6 @@ #include "amdgpu_dm.h" #include "dc.h" #include "modules/color/color_gamma.h" -#include "basics/conversion.h" /** * DOC: overview From 012dce4442fded6ac32a44c30fe3e1a108bfbaf7 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Sun, 6 Jul 2025 08:38:05 -0500 Subject: [PATCH 0055/2653] drm/amd/display: Avoid configuring PSR granularity if PSR-SU not supported [Why] If PSR-SU is disabled on the link, then configuring su_y granularity in mod_power_calc_psr_configs() can lead to assertions in psr_su_set_dsc_slice_height(). [How] Check the PSR version in amdgpu_dm_link_setup_psr() to determine whether or not to configure granularity. Reviewed-by: Sun peng (Leo) Li Signed-off-by: Mario Limonciello Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c index d5a3768bf002a..fd491b7a3cd70 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c @@ -119,8 +119,10 @@ bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream) psr_config.allow_multi_disp_optimizations = (amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT); - if (!psr_su_set_dsc_slice_height(dc, link, stream, &psr_config)) - return false; + if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) { + if (!psr_su_set_dsc_slice_height(dc, link, stream, &psr_config)) + return false; + } ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context); From d5763cdb5123b358ef89e7d5bee6864a19cc50b8 Mon Sep 17 00:00:00 2001 From: Duncan Ma Date: Wed, 4 Dec 2024 12:35:05 -0500 Subject: [PATCH 0056/2653] drm/amd/display: Add eDP AUXless ALPM [Why & How] Add AUX-less ALPM capability check and initialization Reviewed-by: Charlene Liu Signed-off-by: Duncan Ma Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/core/dc_link_exports.c | 7 ++++ drivers/gpu/drm/amd/display/dc/dc.h | 11 ++++++ drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 16 +++++--- drivers/gpu/drm/amd/display/dc/dc_types.h | 8 ++++ .../gpu/drm/amd/display/dc/dce/dmub_replay.c | 13 +++++++ drivers/gpu/drm/amd/display/dc/inc/link.h | 5 ++- .../drm/amd/display/dc/link/link_factory.c | 2 + .../dc/link/protocols/link_dp_capability.c | 37 +++++++++++++++++++ .../dc/link/protocols/link_dp_capability.h | 6 +++ .../link/protocols/link_edp_panel_control.c | 8 +++- 10 files changed, 105 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c index 130455f2802a7..b7a5de4ecb61e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c @@ -520,3 +520,10 @@ enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, cons return dc->link_srv->validate_dp_tunnel_bandwidth(dc, new_ctx); } +void dc_link_get_alpm_support(struct dc_link *link, + bool *auxless_support, + bool *auxwake_support) +{ + link->dc->link_srv->edp_get_alpm_support(link, auxless_support, auxwake_support); +} + diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 779b39e334436..fee54cc0f7d48 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1145,6 +1145,11 @@ struct dc_debug_options { bool enable_hblank_borrow; bool force_subvp_df_throttle; uint32_t acpi_transition_bitmasks[MAX_PIPES]; + unsigned int auxless_alpm_lfps_setup_ns; + unsigned int auxless_alpm_lfps_period_ns; + unsigned int auxless_alpm_lfps_silence_ns; + unsigned int auxless_alpm_lfps_t1t2_us; + short auxless_alpm_lfps_t1t2_offset_us; }; @@ -2447,6 +2452,12 @@ void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( */ enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx); +/* + * Get if ALPM is supported by the link + */ +void dc_link_get_alpm_support(struct dc_link *link, bool *auxless_support, + bool *auxwake_support); + /* Sink Interfaces - A sink corresponds to a display output device */ struct dc_container_id { diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index 5ce1be362534d..3a3ec38cdf8be 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -1021,7 +1021,8 @@ union dp_128b_132b_supported_lttpr_link_rates { union dp_alpm_lttpr_cap { struct { uint8_t AUX_LESS_ALPM_SUPPORTED :1; - uint8_t RESERVED :7; + uint8_t ASSR_SUPPORTED :1; + uint8_t RESERVED :6; } bits; uint8_t raw; }; @@ -1119,10 +1120,11 @@ union dp_128b_132b_training_aux_rd_interval { union edp_alpm_caps { struct { - uint8_t AUX_WAKE_ALPM_CAP :1; - uint8_t PM_STATE_2A_SUPPORT :1; - uint8_t AUX_LESS_ALPM_CAP :1; - uint8_t RESERVED :5; + uint8_t AUX_WAKE_ALPM_CAP :1; + uint8_t PM_STATE_2A_SUPPORT :1; + uint8_t AUX_LESS_ALPM_CAP :1; + uint8_t AUX_LESS_ALPM_ML_PHY_SLEEP_STATUS_SUPPORTED :1; + uint8_t RESERVED :4; } bits; uint8_t raw; }; @@ -1347,7 +1349,9 @@ union dpcd_alpm_configuration { struct { unsigned char ENABLE : 1; unsigned char IRQ_HPD_ENABLE : 1; - unsigned char RESERVED : 6; + unsigned char ALPM_MODE_SEL : 1; + unsigned char ACDS_PERIOD_DURATION : 1; + unsigned char RESERVED : 4; } bits; unsigned char raw; }; diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 2a86058c3bfa6..2e2dea21b3321 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -577,6 +577,12 @@ struct dc_plane_flip_time { unsigned int prev_update_time_in_us; }; +enum dc_alpm_mode { + DC_ALPM_AUXWAKE = 0, + DC_ALPM_AUXLESS = 1, + DC_ALPM_UNSUPPORTED = 0xF, +}; + enum dc_psr_state { PSR_STATE0 = 0x0, PSR_STATE1, @@ -1143,6 +1149,8 @@ struct replay_config { bool low_rr_supported; /* Replay Video Conferencing Optimization Enabled */ bool replay_video_conferencing_optimization_enabled; + /* Replay alpm mode */ + enum dc_alpm_mode alpm_mode; }; /* Replay feature flags*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c index fcd3d86ad5173..65b979617b0cf 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c @@ -3,6 +3,7 @@ // Copyright 2024 Advanced Micro Devices, Inc. #include "dc.h" +#include "link.h" #include "dc_dmub_srv.h" #include "dmub/dmub_srv.h" #include "core_types.h" @@ -189,6 +190,18 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub, else copy_settings_data->flags.bitfields.force_wakeup_by_tps3 = 0; + copy_settings_data->flags.bitfields.alpm_mode = (enum dmub_alpm_mode)link->replay_settings.config.alpm_mode; + if (link->replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) { + copy_settings_data->auxless_alpm_data.lfps_setup_ns = dc->dc->debug.auxless_alpm_lfps_setup_ns; + copy_settings_data->auxless_alpm_data.lfps_period_ns = dc->dc->debug.auxless_alpm_lfps_period_ns; + copy_settings_data->auxless_alpm_data.lfps_silence_ns = dc->dc->debug.auxless_alpm_lfps_silence_ns; + copy_settings_data->auxless_alpm_data.lfps_t1_t2_override_us = + dc->dc->debug.auxless_alpm_lfps_t1t2_us; + copy_settings_data->auxless_alpm_data.lfps_t1_t2_offset_us = + dc->dc->debug.auxless_alpm_lfps_t1t2_offset_us; + copy_settings_data->auxless_alpm_data.lttpr_count = link->dc->link_srv->dp_get_lttpr_count(link); + } + dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); return true; diff --git a/drivers/gpu/drm/amd/display/dc/inc/link.h b/drivers/gpu/drm/amd/display/dc/inc/link.h index f2503402c10e7..0cce49d95e261 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/link.h +++ b/drivers/gpu/drm/amd/display/dc/inc/link.h @@ -218,7 +218,10 @@ struct link_service { bool (*dp_overwrite_extended_receiver_cap)(struct dc_link *link); enum lttpr_mode (*dp_decide_lttpr_mode)(struct dc_link *link, struct dc_link_settings *link_setting); - + uint8_t (*dp_get_lttpr_count)(struct dc_link *link); + void (*edp_get_alpm_support)(struct dc_link *link, + bool *auxless_support, + bool *auxwake_support); /*************************** DP DPIA/PHY ******************************/ void (*dpia_handle_usb4_bandwidth_allocation_for_link)( diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c index de1143dbbd25f..31a73867cd4cf 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@ -165,6 +165,8 @@ static void construct_link_service_dp_capability(struct link_service *link_srv) link_srv->dp_overwrite_extended_receiver_cap = dp_overwrite_extended_receiver_cap; link_srv->dp_decide_lttpr_mode = dp_decide_lttpr_mode; + link_srv->dp_get_lttpr_count = dp_get_lttpr_count; + link_srv->edp_get_alpm_support = edp_get_alpm_support; } /* link dp phy/dpia implements basic dp phy/dpia functionality such as diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 651926e547b90..e0c4416993d94 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -2506,3 +2506,40 @@ bool dp_is_sink_present(struct dc_link *link) return present; } + +uint8_t dp_get_lttpr_count(struct dc_link *link) +{ + if (dp_is_lttpr_present(link)) + return dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); + + return 0; +} + +void edp_get_alpm_support(struct dc_link *link, + bool *auxless_support, + bool *auxwake_support) +{ + bool lttpr_present = dp_is_lttpr_present(link); + + if (auxless_support == NULL || auxwake_support == NULL) + return; + + *auxless_support = false; + *auxwake_support = false; + + if (!dc_is_embedded_signal(link->connector_signal)) + return; + + if (link->dpcd_caps.alpm_caps.bits.AUX_LESS_ALPM_CAP) { + if (lttpr_present) { + if (link->dpcd_caps.lttpr_caps.alpm.bits.AUX_LESS_ALPM_SUPPORTED) + *auxless_support = true; + } else + *auxless_support = true; + } + + if (link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP) { + if (!lttpr_present) + *auxwake_support = true; + } +} diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h index 940b147cc5d42..7170db5a1c13e 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h @@ -108,4 +108,10 @@ uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw); bool dp_overwrite_extended_receiver_cap(struct dc_link *link); +uint8_t dp_get_lttpr_count(struct dc_link *link); + +void edp_get_alpm_support(struct dc_link *link, + bool *auxless_support, + bool *auxwake_support); + #endif /* __DC_LINK_DP_CAPABILITY_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 98ec9b5a559c8..be714cbf66155 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -1042,7 +1042,13 @@ bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream (uint8_t *)&(replay_config.raw), sizeof(uint8_t)); memset(&alpm_config, 0, sizeof(alpm_config)); - alpm_config.bits.ENABLE = 1; + alpm_config.bits.ENABLE = link->replay_settings.config.alpm_mode != DC_ALPM_UNSUPPORTED ? 1 : 0; + + if (link->replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) { + alpm_config.bits.ALPM_MODE_SEL = 1; + alpm_config.bits.ACDS_PERIOD_DURATION = 1; + } + dm_helpers_dp_write_dpcd( link->ctx, link, From 3f4d1332d3fabd84147c83678ac260442b8b34d9 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Tue, 15 Jul 2025 14:41:46 -0500 Subject: [PATCH 0057/2653] drm/amd/display: Only finalize atomic_obj if it was initialized [Why] If amdgpu_dm failed to initalize before amdgpu_dm_initialize_drm_device() completed then freeing atomic_obj will lead to list corruption. [How] Check if atomic_obj state is initialized before trying to free. Reviewed-by: Harry Wentland Signed-off-by: Mario Limonciello Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a14a656df31b2..b78633b80ac42 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5397,7 +5397,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) { - drm_atomic_private_obj_fini(&dm->atomic_obj); + if (dm->atomic_obj.state) + drm_atomic_private_obj_fini(&dm->atomic_obj); } /****************************************************************************** From 9bf45d2f64610f3504cb2a423a0dc1b9d7c3b909 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Wed, 16 Jul 2025 15:53:43 -0500 Subject: [PATCH 0058/2653] drm/amd/display: Rename dcn31 string shown to user [Why] DCN31 isn't a product, but DCN312 is. Matching against documentation users might not understand the code. [How] Change DCN 3.1 string to be DCN 3.1.2. Reviewed-by: Alex Hung Signed-off-by: Mario Limonciello Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index 7217de2588511..51e41aed7316c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -732,7 +732,7 @@ char *dce_version_to_string(const int version) case DCN_VERSION_3_03: return "DCN 3.0.3"; case DCN_VERSION_3_1: - return "DCN 3.1"; + return "DCN 3.1.2"; case DCN_VERSION_3_14: return "DCN 3.1.4"; case DCN_VERSION_3_15: From cbeba9871cef926334c928c0ce530e3e160f167f Mon Sep 17 00:00:00 2001 From: "Chiang, Richard" Date: Tue, 15 Jul 2025 21:59:54 +0800 Subject: [PATCH 0059/2653] drm/amd/display: Remove update_planes_and_stream_v1 sequence [Why]/How] Remove the update_planes_and_stream_v1 sequence to make the logic the same. Reviewed-by: Charlene Liu Signed-off-by: Chiang, Richard Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 129 +---------------------- 1 file changed, 2 insertions(+), 127 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index c17e5843e8b79..d8e4bdef76a36 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -5102,129 +5102,6 @@ static bool fast_update_only(struct dc *dc, && !full_update_required(dc, srf_updates, surface_count, stream_update, stream); } -static bool update_planes_and_stream_v1(struct dc *dc, - struct dc_surface_update *srf_updates, int surface_count, - struct dc_stream_state *stream, - struct dc_stream_update *stream_update, - struct dc_state *state) -{ - const struct dc_stream_status *stream_status; - enum surface_update_type update_type; - struct dc_state *context; - struct dc_context *dc_ctx = dc->ctx; - int i, j; - struct dc_fast_update fast_update[MAX_SURFACES] = {0}; - - dc_exit_ips_for_hw_access(dc); - - populate_fast_updates(fast_update, srf_updates, surface_count, stream_update); - stream_status = dc_stream_get_status(stream); - context = dc->current_state; - - update_type = dc_check_update_surfaces_for_stream( - dc, srf_updates, surface_count, stream_update, stream_status); - /* It is possible to receive a flip for one plane while there are multiple flip_immediate planes in the same stream. - * E.g. Desktop and MPO plane are flip_immediate but only the MPO plane received a flip - * Force the other flip_immediate planes to flip so GSL doesn't wait for a flip that won't come. - */ - force_immediate_gsl_plane_flip(dc, srf_updates, surface_count); - - if (update_type >= UPDATE_TYPE_FULL) { - - /* initialize scratch memory for building context */ - context = dc_state_create_copy(state); - if (context == NULL) { - DC_ERROR("Failed to allocate new validate context!\n"); - return false; - } - - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; - struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; - - if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state) - new_pipe->plane_state->force_full_update = true; - } - } else if (update_type == UPDATE_TYPE_FAST) { - /* - * Previous frame finished and HW is ready for optimization. - */ - dc_post_update_surfaces_to_stream(dc); - } - - for (i = 0; i < surface_count; i++) { - struct dc_plane_state *surface = srf_updates[i].surface; - - copy_surface_update_to_plane(surface, &srf_updates[i]); - - if (update_type >= UPDATE_TYPE_MED) { - for (j = 0; j < dc->res_pool->pipe_count; j++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[j]; - - if (pipe_ctx->plane_state != surface) - continue; - - resource_build_scaling_params(pipe_ctx); - } - } - } - - copy_stream_update_to_stream(dc, context, stream, stream_update); - - if (update_type >= UPDATE_TYPE_FULL) { - if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK) { - DC_ERROR("Mode validation failed for stream update!\n"); - dc_state_release(context); - return false; - } - } - - TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES); - - if (fast_update_only(dc, fast_update, srf_updates, surface_count, stream_update, stream) && - !dc->debug.enable_legacy_fast_update) { - commit_planes_for_stream_fast(dc, - srf_updates, - surface_count, - stream, - stream_update, - update_type, - context); - } else { - commit_planes_for_stream( - dc, - srf_updates, - surface_count, - stream, - stream_update, - update_type, - context); - } - /*update current_State*/ - if (dc->current_state != context) { - - struct dc_state *old = dc->current_state; - - dc->current_state = context; - dc_state_release(old); - - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - - if (pipe_ctx->plane_state && pipe_ctx->stream == stream) - pipe_ctx->plane_state->force_full_update = false; - } - } - - /* Legacy optimization path for DCE. */ - if (update_type >= UPDATE_TYPE_FULL && dc_ctx->dce_version < DCE_VERSION_MAX) { - dc_post_update_surfaces_to_stream(dc); - TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); - } - return true; -} - static bool update_planes_and_stream_v2(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, struct dc_stream_state *stream, @@ -5481,12 +5358,10 @@ void dc_commit_updates_for_stream(struct dc *dc, if (dc->ctx->dce_version >= DCN_VERSION_4_01) { ret = update_planes_and_stream_v3(dc, srf_updates, surface_count, stream, stream_update); - } else if (dc->ctx->dce_version >= DCN_VERSION_3_2) { + } else { ret = update_planes_and_stream_v2(dc, srf_updates, surface_count, stream, stream_update); - } else - ret = update_planes_and_stream_v1(dc, srf_updates, surface_count, stream, - stream_update, state); + } if (ret && dc->ctx->dce_version >= DCN_VERSION_3_2) clear_update_flags(srf_updates, surface_count, stream); From 0bf318c45d8f5db4ca9834a6878cb2d2cbfc4b63 Mon Sep 17 00:00:00 2001 From: Relja Vojvodic Date: Mon, 14 Jul 2025 11:56:50 -0400 Subject: [PATCH 0060/2653] drm/amd/display: Allow for sharing of some link and audio link functions [Why&How] Allow for sharing of some link and audio link functions by removing static keyword from function definitions. Expose those functions in the HWSEQ header. Reviewed-by: Alvin Lee Signed-off-by: Relja Vojvodic Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 6 +++--- drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h | 7 +++++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 32fd6bdc18d73..153d68375fa3a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -1270,7 +1270,7 @@ void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); } -static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) +enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) { switch (crtc_id) { case CONTROLLER_ID_D0: @@ -1290,7 +1290,7 @@ static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) } } -static void populate_audio_dp_link_info( +void populate_audio_dp_link_info( const struct pipe_ctx *pipe_ctx, struct audio_dp_link_info *dp_link_info) { @@ -2253,7 +2253,7 @@ static bool should_enable_fbc(struct dc *dc, /* * Enable FBC */ -static void enable_fbc( +void enable_fbc( struct dc *dc, struct dc_state *context) { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h index 7cd8c15769881..9c032e449481f 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h @@ -114,5 +114,12 @@ void build_audio_output( struct dc_state *state, const struct pipe_ctx *pipe_ctx, struct audio_output *audio_output); +enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id); +void populate_audio_dp_link_info( + const struct pipe_ctx *pipe_ctx, + struct audio_dp_link_info *dp_link_info); +void enable_fbc( + struct dc *dc, + struct dc_state *context); #endif /* __DC_HWSS_DCE110_H__ */ From 74324b75ad20dbcc02f85483df86144c2acfd4fd Mon Sep 17 00:00:00 2001 From: Cruise Hung Date: Tue, 15 Jul 2025 16:36:44 +0800 Subject: [PATCH 0061/2653] drm/amd/display: Add debug option to control BW Allocation mode [Why & How] Add debug option to control BW Allocation mode. Reviewed-by: Meenakshikumar Somasundaram Reviewed-by: PeiChen (Pei-Chen) Huang Signed-off-by: Cruise Hung Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 3 ++- .../gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c | 5 +++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index fee54cc0f7d48..57f4a9445b7ed 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -839,7 +839,8 @@ union dpia_debug_options { uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ uint32_t disable_usb4_pm_support:1; /* bit 5 */ uint32_t enable_usb4_bw_zero_alloc_patch:1; /* bit 6 */ - uint32_t reserved:25; + uint32_t enable_bw_allocation_mode:1; /* bit 7 */ + uint32_t reserved:24; } bits; uint32_t raw; }; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c index 906d85ca89569..8a3c18ae97a7b 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c @@ -225,6 +225,11 @@ bool link_dpia_enable_usb4_dp_bw_alloc_mode(struct dc_link *link) bool ret = false; uint8_t val; + if (link->dc->debug.dpia_debug.bits.enable_bw_allocation_mode == false) { + DC_LOG_DEBUG("%s: link[%d] DPTX BW allocation mode disabled", __func__, link->link_index); + return false; + } + val = DPTX_BW_ALLOC_MODE_ENABLE | DPTX_BW_ALLOC_UNMASK_IRQ; if (core_link_write_dpcd(link, DPTX_BW_ALLOCATION_MODE_CONTROL, &val, sizeof(uint8_t)) == DC_OK) { From 263d0f9f54a506aeaeed8898527eb5f10463e3fb Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 15 May 2025 15:16:17 -0500 Subject: [PATCH 0062/2653] drm/amd/display: Pass up errors for reset GPU that fails to init HW [Why] If a GPU is in reset and the hardware fails to initialize the rest of the resume sequence shouldn't be run. [How] Pass error code up to caller of dm_resume(). Reviewed-by: Alex Hung Signed-off-by: Mario Limonciello Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b78633b80ac42..c71167ffdb76b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3387,8 +3387,10 @@ static int dm_resume(struct amdgpu_ip_block *ip_block) link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); r = dm_dmub_hw_init(adev); - if (r) + if (r) { drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r); + return r; + } dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); From c400d17489809cdd6a7e43ec96f0e6f815933fee Mon Sep 17 00:00:00 2001 From: Michael Strauss Date: Wed, 19 Mar 2025 18:04:01 -0400 Subject: [PATCH 0063/2653] drm/amd/display: Increase AUX Intra-Hop Done Max Wait Duration [WHY] In the worst case, AUX intra-hop done can take hundreds of milliseconds as each retimer in a link might have to wait a full AUX_RD_INTERVAL to send LT abort downstream. [HOW] Wait 300ms for each retimer in a link to allow time to propagate a LT abort without infinitely waiting on intra-hop done. For no-retimer case, keep the max duration at 10ms. Reviewed-by: Wenjing Liu Signed-off-by: Michael Strauss Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/link/protocols/link_dp_training.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c index 2dc1a660e5045..134093ce5a8e8 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c @@ -1018,7 +1018,12 @@ static enum link_training_result dpcd_exit_training_mode(struct dc_link *link, e { enum dc_status status; uint8_t sink_status = 0; - uint8_t i; + uint32_t i; + uint8_t lttpr_count = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); + uint32_t intra_hop_disable_time_ms = (lttpr_count > 0 ? lttpr_count * 300 : 10); + + // Each hop could theoretically take over 256ms (max 128b/132b AUX RD INTERVAL) + // To be safe, allow 300ms per LTTPR and 10ms for no LTTPR case /* clear training pattern set */ status = dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE); @@ -1028,7 +1033,7 @@ static enum link_training_result dpcd_exit_training_mode(struct dc_link *link, e if (encoding == DP_128b_132b_ENCODING) { /* poll for intra-hop disable */ - for (i = 0; i < 10; i++) { + for (i = 0; i < intra_hop_disable_time_ms; i++) { if ((core_link_read_dpcd(link, DP_SINK_STATUS, &sink_status, 1) == DC_OK) && (sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION) == 0) break; From 0b17f654a5109bd4d9e9e0cef8b6f8a567e1a428 Mon Sep 17 00:00:00 2001 From: Ray Wu Date: Wed, 11 Jun 2025 14:02:25 +0800 Subject: [PATCH 0064/2653] drm/amd/display: Add Replay residency in debugfs [Why] Users can access the replay residency to get PHY off percentage [How] Start capture residency: sudo echo 1 /sys/kernel/debug/dri/0/eDP-1/replay_residency Stop and Get replay residency: sudo cat /sys/kernel/debug/dri/0/eDP-1/replay_residency Reviewed-by: ChiaHsuan (Tom) Chung Signed-off-by: Ray Wu Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 34 ++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 484691335fd62..f263e1a4537e1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3106,6 +3106,35 @@ static int replay_get_state(void *data, u64 *val) return 0; } +/* + * Start / Stop capture Replay residency + */ +static int replay_set_residency(void *data, u64 val) +{ + struct amdgpu_dm_connector *connector = data; + struct dc_link *link = connector->dc_link; + bool is_start = (val != 0); + u32 residency = 0; + + link->dc->link_srv->edp_replay_residency(link, &residency, is_start, PR_RESIDENCY_MODE_PHY); + return 0; +} + +/* + * Read Replay residency + */ +static int replay_get_residency(void *data, u64 *val) +{ + struct amdgpu_dm_connector *connector = data; + struct dc_link *link = connector->dc_link; + u32 residency = 0; + + link->dc->link_srv->edp_replay_residency(link, &residency, false, PR_RESIDENCY_MODE_PHY); + *val = (u64)residency; + + return 0; +} + /* * Read PSR state */ @@ -3325,7 +3354,8 @@ DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_g dmcub_trace_event_state_set, "%llu\n"); DEFINE_DEBUGFS_ATTRIBUTE(replay_state_fops, replay_get_state, NULL, "%llu\n"); - +DEFINE_DEBUGFS_ATTRIBUTE(replay_residency_fops, replay_get_residency, replay_set_residency, + "%llu\n"); DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL, "%llu\n"); @@ -3503,6 +3533,8 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) debugfs_create_file("replay_capability", 0444, dir, connector, &replay_capability_fops); debugfs_create_file("replay_state", 0444, dir, connector, &replay_state_fops); + debugfs_create_file_unsafe("replay_residency", 0444, dir, + connector, &replay_residency_fops); debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops); debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); debugfs_create_file_unsafe("psr_residency", 0444, dir, From b96d22e0ef4aecb188466fe8ffd5152c0bb34247 Mon Sep 17 00:00:00 2001 From: Ovidiu Bunea Date: Thu, 17 Jul 2025 10:41:41 -0400 Subject: [PATCH 0065/2653] drm/amd/display: Revert "Add a config flag for limited_pll_vco" This reverts commit c97eef97dd74 [why & how] DMUB header changes should be submitted to firmware branch first and allowed to propagate to driver. Currently, this change breaks linux builds so need to revert it until it's ready. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Ovidiu Bunea Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 - drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 +-- drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 1 - 3 files changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index 87b761ac3135d..0bafb67107618 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -316,7 +316,6 @@ struct dmub_srv_hw_params { bool disable_sldo_opt; bool enable_non_transparent_setconfig; bool lower_hbr3_phy_ssc; - bool override_hbr3_pll_vco; }; /** diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index e2e5f71c03f2b..a89bf08ffd379 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -843,8 +843,7 @@ union dmub_fw_boot_options { uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ - uint32_t override_hbr3_pll_vco: 1; /**< 1 to override the hbr3 pll vco to 0 */ - uint32_t reserved : 5; /**< reserved */ + uint32_t reserved : 6; /**< reserved */ } bits; /**< boot bits */ uint32_t all; /**< 32-bit access to bits */ }; diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c index 4777c7203b2c2..3f38db752b844 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c @@ -377,7 +377,6 @@ void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported; boot_options.bits.power_optimization = params->power_optimization; boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc; - boot_options.bits.override_hbr3_pll_vco = params->override_hbr3_pll_vco; boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic == DMUB_ASIC_DCN31B) ? 1 : 0; From fe20a2c70e9d634794d2766eee753463080b048f Mon Sep 17 00:00:00 2001 From: Ovidiu Bunea Date: Tue, 15 Jul 2025 17:26:39 -0400 Subject: [PATCH 0066/2653] drm/amd/display: Fix dmub_cmd header alignment [why & how] Header misalignment in struct dmub_cmd_replay_copy_settings_data and struct dmub_alpm_auxless_data causes incorrect data read between driver and dmub. Fix the misalignment and ensure that everything is aligned to 4-byte boundaries. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Ovidiu Bunea Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 20 +++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index a89bf08ffd379..dcae768c2cf44 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -4048,6 +4048,10 @@ struct dmub_alpm_auxless_data { uint16_t lfps_t1_t2_override_us; short lfps_t1_t2_offset_us; uint8_t lttpr_count; + /* + * Padding to align structure to 4 byte boundary. + */ + uint8_t pad[1]; }; /** @@ -4080,14 +4084,6 @@ struct dmub_cmd_replay_copy_settings_data { * DIG BE HW instance. */ uint8_t digbe_inst; - /** - * @hpo_stream_enc_inst: HPO stream encoder instance - */ - uint8_t hpo_stream_enc_inst; - /** - * @hpo_link_enc_inst: HPO link encoder instance - */ - uint8_t hpo_link_enc_inst; /** * AUX HW instance. */ @@ -4132,6 +4128,14 @@ struct dmub_cmd_replay_copy_settings_data { * Use for AUX-less ALPM LFPS wake operation */ struct dmub_alpm_auxless_data auxless_alpm_data; + /** + * @hpo_stream_enc_inst: HPO stream encoder instance + */ + uint8_t hpo_stream_enc_inst; + /** + * @hpo_link_enc_inst: HPO link encoder instance + */ + uint8_t hpo_link_enc_inst; /** * @pad: Align structure to 4 byte boundary. */ From fabdf83d9b4c3ac48ee65a4bacf724d566090309 Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Thu, 17 Jul 2025 13:58:35 -0400 Subject: [PATCH 0067/2653] drm/amd/display: Allow DCN301 to clear update flags [Why & How] Not letting DCN301 to clear after surface/stream update results in artifacts when switching between active overlay planes. The issue is known and has been solved initially. See below: (https://gitlab.freedesktop.org/drm/amd/-/issues/3441) Fixes: e1bd5e0bb4ca ("drm/amd/display: limit clear_update_flags t dcn32 and above") Reviewed-by: Mario Limonciello Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index d8e4bdef76a36..cf3893a2f8ce3 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -5334,7 +5334,8 @@ bool dc_update_planes_and_stream(struct dc *dc, else ret = update_planes_and_stream_v2(dc, srf_updates, surface_count, stream, stream_update); - if (ret && dc->ctx->dce_version >= DCN_VERSION_3_2) + if (ret && (dc->ctx->dce_version >= DCN_VERSION_3_2 || + dc->ctx->dce_version == DCN_VERSION_3_01)) clear_update_flags(srf_updates, surface_count, stream); return ret; From 217f5ffc530f108d9be3ce49f592c18558f70e38 Mon Sep 17 00:00:00 2001 From: Michael Strauss Date: Thu, 17 Jul 2025 16:18:58 -0400 Subject: [PATCH 0068/2653] drm/amd/display: Cache streams targeting link when performing LT automation [WHY] Last LT automation update can cause crash by referencing current_state and calling into dc_update_planes_and_stream which may clobber current_state. [HOW] Cache relevant stream pointers and iterate through them instead of relying on the current_state. Reviewed-by: Wenjing Liu Signed-off-by: Michael Strauss Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- .../display/dc/link/accessories/link_dp_cts.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c index b12d61701d4d9..23f41c99fa38c 100644 --- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c +++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c @@ -76,6 +76,9 @@ static void dp_retrain_link_dp_test(struct dc_link *link, uint8_t count; int i; + struct dc_stream_state *streams_on_link[MAX_PIPES]; + int num_streams_on_link = 0; + needs_divider_update = (link->dc->link_srv->dp_get_encoding_format(link_setting) != link->dc->link_srv->dp_get_encoding_format((const struct dc_link_settings *) &link->cur_link_settings)); @@ -138,12 +141,19 @@ static void dp_retrain_link_dp_test(struct dc_link *link, pipes[i]->stream_res.tg->funcs->enable_crtc(pipes[i]->stream_res.tg); // Set DPMS on with stream update - for (i = 0; i < state->stream_count; i++) - if (state->streams[i] && state->streams[i]->link && state->streams[i]->link == link) { - stream_update.stream = state->streams[i]; + // Cache all streams on current link since dc_update_planes_and_stream might kill current_state + for (i = 0; i < MAX_PIPES; i++) { + if (state->streams[i] && state->streams[i]->link && state->streams[i]->link == link) + streams_on_link[num_streams_on_link++] = state->streams[i]; + } + + for (i = 0; i < num_streams_on_link; i++) { + if (streams_on_link[i] && streams_on_link[i]->link && streams_on_link[i]->link == link) { + stream_update.stream = streams_on_link[i]; stream_update.dpms_off = &dpms_off; - dc_update_planes_and_stream(state->clk_mgr->ctx->dc, NULL, 0, state->streams[i], &stream_update); + dc_update_planes_and_stream(state->clk_mgr->ctx->dc, NULL, 0, streams_on_link[i], &stream_update); } + } } static void dp_test_send_link_training(struct dc_link *link) From bfcce1016c95f156b2b37f00d9972e9ecd40914d Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 18 Jul 2025 19:26:12 -0500 Subject: [PATCH 0069/2653] drm/amd/display: Promote DAL to 3.2.343 Summary: * Fix caching streams for LT automation * Fix DMUB command alignment * Disabling DSC power gating on DCN314 * Add debugfs for Replay * Add debug option for BW allocation mode * Removal of unnecessary includes for faster compilation * Refactor of code, including adding SPDX license to amdgpu_dm Acked-by: Sun peng (Leo) Li Signed-off-by: Taimur Hassan Signed-off-by: Ivan Lipski Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 57f4a9445b7ed..5653c1673aece 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.342" +#define DC_VER "3.2.343" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From 61666073e6fd5683339313dde446af6465383b4d Mon Sep 17 00:00:00 2001 From: Amber Lin Date: Thu, 17 Jul 2025 11:39:58 -0400 Subject: [PATCH 0070/2653] drm/amdgpu: Add chain runlists support to GC9.4.2 Starting from MEC v97, GC 9.4.2 supports chain runlists of XNACK+/XNACK- processes. Signed-off-by: Amber Lin Reviewed-by: Philip Yang --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 +++ drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 12 ++++++++++++ drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h | 1 + 3 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ac058697054f9..fe951668f61fd 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2650,6 +2650,9 @@ static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev) !READ_ONCE(adev->barrier_has_auto_waitcnt)); WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp); break; + case IP_VERSION(9, 4, 2): + gfx_v9_4_2_init_sq(adev); + break; default: break; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c index c48cd47b531f5..8058ea91ecafd 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c @@ -748,6 +748,18 @@ void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev, } } +void gfx_v9_4_2_init_sq(struct amdgpu_device *adev) +{ + uint32_t data; + + if (adev->gfx.mec_fw_version >= 98) { + adev->gmc.xnack_flags |= AMDGPU_GMC_XNACK_FLAG_CHAIN; + data = RREG32_SOC15(GC, 0, regSQ_CONFIG1); + data = REG_SET_FIELD(data, SQ_CONFIG1, DISABLE_XNACK_CHECK_IN_RETRY_DISABLE, 1); + WREG32_SOC15(GC, 0, regSQ_CONFIG1, data); + } +} + void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev, uint32_t first_vmid, uint32_t last_vmid) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h index 7584624b641ca..a603724c1dfc5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h @@ -28,6 +28,7 @@ void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev, uint32_t first_vmid, uint32_t last_vmid); void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev, uint32_t die_id); +void gfx_v9_4_2_init_sq(struct amdgpu_device *adev); void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev); int gfx_v9_4_2_do_edc_gpr_workarounds(struct amdgpu_device *adev); From 171d743752f9436eb10a4e368de01803f483de15 Mon Sep 17 00:00:00 2001 From: Yann Dirson Date: Sun, 20 Jul 2025 16:13:16 +0200 Subject: [PATCH 0071/2653] Documentation/amdgpu: fix 'in the amdgfx' formulation Clarify the mailing list. Signed-off-by: Yann Dirson Signed-off-by: Alex Deucher --- Documentation/gpu/amdgpu/display/dc-glossary.rst | 2 +- Documentation/gpu/amdgpu/display/display-contributing.rst | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst b/Documentation/gpu/amdgpu/display/dc-glossary.rst index 7dc034e9e5862..cbe737d1fcead 100644 --- a/Documentation/gpu/amdgpu/display/dc-glossary.rst +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst @@ -5,7 +5,7 @@ DC Glossary On this page, we try to keep track of acronyms related to the display component. If you do not find what you are looking for, look at the 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere, -consider asking in the amdgfx and update this page. +consider asking on the amd-gfx mailing list and update this page. .. glossary:: diff --git a/Documentation/gpu/amdgpu/display/display-contributing.rst b/Documentation/gpu/amdgpu/display/display-contributing.rst index 36f3077eee003..2f741c52dce58 100644 --- a/Documentation/gpu/amdgpu/display/display-contributing.rst +++ b/Documentation/gpu/amdgpu/display/display-contributing.rst @@ -9,8 +9,8 @@ contribution to the display code, and for that, we say thank you :) This page summarizes some of the issues you can help with; keep in mind that this is a static page, and it is always a good idea to try to reach developers -in the amdgfx or some of the maintainers. Finally, this page follows the DRM -way of creating a TODO list; for more information, check +on the amd-gfx mailing list or some of the maintainers. Finally, this page +follows the DRM way of creating a TODO list; for more information, check 'Documentation/gpu/todo.rst'. Gitlab issues From edd90db56abb882c61b3abaa5ba7024c3a62d988 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 18 Jul 2025 15:53:54 -0400 Subject: [PATCH 0072/2653] drm/amdgpu: update mmhub 4.1.0 client id mappings Update the client id mapping so the correct clients get printed when there is a mmhub page fault. Tested-by: David (Ming Qiang) Wu Reviewed-by: David (Ming Qiang) Wu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c | 34 +++++++++-------------- 1 file changed, 13 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c index f2ab5001b4924..951998454b257 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c @@ -37,39 +37,31 @@ static const char *mmhub_client_ids_v4_1_0[][2] = { [0][0] = "VMC", [4][0] = "DCEDMC", - [5][0] = "DCEVGA", [6][0] = "MP0", [7][0] = "MP1", [8][0] = "MPIO", - [16][0] = "HDP", - [17][0] = "LSDMA", - [18][0] = "JPEG", - [19][0] = "VCNU0", - [21][0] = "VSCH", - [22][0] = "VCNU1", - [23][0] = "VCN1", - [32+20][0] = "VCN0", - [2][1] = "DBGUNBIO", + [16][0] = "LSDMA", + [17][0] = "JPEG", + [19][0] = "VCNU", + [22][0] = "VSCH", + [23][0] = "HDP", + [32+23][0] = "VCNRD", [3][1] = "DCEDWB", [4][1] = "DCEDMC", - [5][1] = "DCEVGA", [6][1] = "MP0", [7][1] = "MP1", [8][1] = "MPIO", [10][1] = "DBGU0", [11][1] = "DBGU1", - [12][1] = "DBGU2", - [13][1] = "DBGU3", + [12][1] = "DBGUNBIO", [14][1] = "XDP", [15][1] = "OSSSYS", - [16][1] = "HDP", - [17][1] = "LSDMA", - [18][1] = "JPEG", - [19][1] = "VCNU0", - [20][1] = "VCN0", - [21][1] = "VSCH", - [22][1] = "VCNU1", - [23][1] = "VCN1", + [16][1] = "LSDMA", + [17][1] = "JPEG", + [18][1] = "VCNWR", + [19][1] = "VCNU", + [22][1] = "VSCH", + [23][1] = "HDP", }; static uint32_t mmhub_v4_1_0_get_invalidate_req(unsigned int vmid, From 973dd6e742b8dcb4307161f8bc6faa6d9dc426f2 Mon Sep 17 00:00:00 2001 From: Yann Dirson Date: Sun, 20 Jul 2025 16:13:17 +0200 Subject: [PATCH 0073/2653] drm/amdgpu: fix module parameter description Fix dcdebugmask description. Signed-off-by: Yann Dirson Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 395c6be901ce7..efb54c23ba173 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -886,7 +886,7 @@ module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); /** * DOC: dcdebugmask (uint) - * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. + * Display debug options. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. */ MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); From 0fdf257286d770a5facd1f0fff7a556124de03be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Fri, 6 Jun 2025 14:13:37 +0200 Subject: [PATCH 0074/2653] drm/amdgpu: rework how PTE flags are generated v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Previously we tried to keep the HW specific PTE flags in each mapping, but for CRIU that isn't sufficient any more since the original value is needed for the checkpoint procedure. So rework the whole handling, nuke the early mapping function, keep the UAPI flags in each mapping instead of the HW flags and translate them to the HW flags while filling in the PTEs. Only tested on Navi 23 for now, so probably needs quite a bit of more work. v2: fix KFD and SVN handling v3: one more SVN fix pointed out by Felix Signed-off-by: Christian König Reviewed-by: Felix Kuehling --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 7 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 37 +---------- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 15 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c | 8 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 +- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 57 +++++++++-------- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 57 +++++++++-------- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 56 ++++++++--------- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 +- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 +- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 10 ++- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 61 +++++++++---------- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 13 ++-- 16 files changed, 162 insertions(+), 191 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 260165bbe3736..37d8a7034a7ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -494,7 +494,8 @@ static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync) return amdgpu_sync_fence(sync, vm->last_update, GFP_KERNEL); } -static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem) +static uint64_t get_pte_flags(struct amdgpu_device *adev, struct amdgpu_vm *vm, + struct kgd_mem *mem) { uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_MTYPE_DEFAULT; @@ -504,7 +505,7 @@ static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem) if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE) mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE; - return amdgpu_gem_va_map_flags(adev, mapping_flags); + return mapping_flags; } /** @@ -961,7 +962,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, goto unwind; } attachment[i]->va = va; - attachment[i]->pte_flags = get_pte_flags(adev, mem); + attachment[i]->pte_flags = get_pte_flags(adev, vm, mem); attachment[i]->adev = adev; list_add(&attachment[i]->list, &mem->attachments); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 6626a6e64ff5f..d5e685c5e28b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -790,36 +790,6 @@ amdgpu_gem_va_update_vm(struct amdgpu_device *adev, return fence; } -/** - * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags - * - * @adev: amdgpu_device pointer - * @flags: GEM UAPI flags - * - * Returns the GEM UAPI flags mapped into hardware for the ASIC. - */ -uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags) -{ - uint64_t pte_flag = 0; - - if (flags & AMDGPU_VM_PAGE_EXECUTABLE) - pte_flag |= AMDGPU_PTE_EXECUTABLE; - if (flags & AMDGPU_VM_PAGE_READABLE) - pte_flag |= AMDGPU_PTE_READABLE; - if (flags & AMDGPU_VM_PAGE_WRITEABLE) - pte_flag |= AMDGPU_PTE_WRITEABLE; - if (flags & AMDGPU_VM_PAGE_PRT) - pte_flag |= AMDGPU_PTE_PRT_FLAG(adev); - if (flags & AMDGPU_VM_PAGE_NOALLOC) - pte_flag |= AMDGPU_PTE_NOALLOC; - - if (adev->gmc.gmc_funcs->map_mtype) - pte_flag |= amdgpu_gmc_map_mtype(adev, - flags & AMDGPU_VM_MTYPE_MASK); - - return pte_flag; -} - int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { @@ -840,7 +810,6 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, struct dma_fence_chain *timeline_chain = NULL; struct dma_fence *fence; struct drm_exec exec; - uint64_t va_flags; uint64_t vm_size; int r = 0; @@ -944,10 +913,9 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, switch (args->operation) { case AMDGPU_VA_OP_MAP: - va_flags = amdgpu_gem_va_map_flags(adev, args->flags); r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, args->offset_in_bo, args->map_size, - va_flags); + args->flags); break; case AMDGPU_VA_OP_UNMAP: r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); @@ -959,10 +927,9 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, args->map_size); break; case AMDGPU_VA_OP_REPLACE: - va_flags = amdgpu_gem_va_map_flags(adev, args->flags); r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, args->offset_in_bo, args->map_size, - va_flags); + args->flags); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h index 3a8f57900a3aa..b51e8f95ee86d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h @@ -63,7 +63,6 @@ int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); -uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags); int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index 397c6ccdb9033..55097ca107382 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -154,15 +154,15 @@ struct amdgpu_gmc_funcs { unsigned pasid); /* enable/disable PRT support */ void (*set_prt)(struct amdgpu_device *adev, bool enable); - /* map mtype to hardware flags */ - uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags); /* get the pde for a given mc addr */ void (*get_vm_pde)(struct amdgpu_device *adev, int level, u64 *dst, u64 *flags); - /* get the pte flags to use for a BO VA mapping */ + /* get the pte flags to use for PTEs */ void (*get_vm_pte)(struct amdgpu_device *adev, - struct amdgpu_bo_va_mapping *mapping, - uint64_t *flags); + struct amdgpu_vm *vm, + struct amdgpu_bo *bo, + uint32_t vm_flags, + uint64_t *pte_flags); /* override per-page pte flags */ void (*override_vm_pte_flags)(struct amdgpu_device *dev, struct amdgpu_vm *vm, @@ -356,9 +356,10 @@ struct amdgpu_gmc { #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) -#define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags)) #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) -#define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags)) +#define amdgpu_gmc_get_vm_pte(adev, vm, bo, vm_flags, pte_flags) \ + ((adev)->gmc.gmc_funcs->get_vm_pte((adev), (vm), (bo), (vm_flags), \ + (pte_flags))) #define amdgpu_gmc_override_vm_pte_flags(adev, vm, addr, pte_flags) \ (adev)->gmc.gmc_funcs->override_vm_pte_flags \ ((adev), (vm), (addr), (pte_flags)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index c316920f34509..87523fcd43863 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -69,7 +69,7 @@ struct amdgpu_bo_va_mapping { uint64_t last; uint64_t __subtree_last; uint64_t offset; - uint64_t flags; + uint32_t flags; }; /* User space allocated BO in a VM */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c index d45ebfb642ca9..a0b479d5fff19 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c @@ -67,9 +67,9 @@ static inline u64 amdgpu_seq64_get_va_base(struct amdgpu_device *adev) int amdgpu_seq64_map(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct amdgpu_bo_va **bo_va) { - u64 seq64_addr, va_flags; struct amdgpu_bo *bo; struct drm_exec exec; + u64 seq64_addr; int r; bo = adev->seq64.sbo; @@ -94,9 +94,9 @@ int amdgpu_seq64_map(struct amdgpu_device *adev, struct amdgpu_vm *vm, seq64_addr = amdgpu_seq64_get_va_base(adev) & AMDGPU_GMC_HOLE_MASK; - va_flags = amdgpu_gem_va_map_flags(adev, AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_MTYPE_UC); - r = amdgpu_vm_bo_map(adev, *bo_va, seq64_addr, 0, AMDGPU_VA_RESERVED_SEQ64_SIZE, - va_flags); + r = amdgpu_vm_bo_map(adev, *bo_va, seq64_addr, 0, + AMDGPU_VA_RESERVED_SEQ64_SIZE, + AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_MTYPE_UC); if (r) { DRM_ERROR("failed to do bo_map on userq sem, err=%d\n", r); amdgpu_vm_bo_del(adev, *bo_va); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 5cacf5717016a..39b4250ede0ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1332,13 +1332,14 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here * but in case of something, we filter the flags in first place */ - if (!(mapping->flags & AMDGPU_PTE_READABLE)) + if (!(mapping->flags & AMDGPU_VM_PAGE_READABLE)) update_flags &= ~AMDGPU_PTE_READABLE; - if (!(mapping->flags & AMDGPU_PTE_WRITEABLE)) + if (!(mapping->flags & AMDGPU_VM_PAGE_WRITEABLE)) update_flags &= ~AMDGPU_PTE_WRITEABLE; /* Apply ASIC specific mapping flags */ - amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags); + amdgpu_gmc_get_vm_pte(adev, vm, bo, mapping->flags, + &update_flags); trace_amdgpu_vm_bo_update(mapping); @@ -1479,7 +1480,7 @@ static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, struct amdgpu_bo_va_mapping *mapping, struct dma_fence *fence) { - if (mapping->flags & AMDGPU_PTE_PRT_FLAG(adev)) + if (mapping->flags & AMDGPU_VM_PAGE_PRT) amdgpu_vm_add_prt_cb(adev, fence); kfree(mapping); } @@ -1758,7 +1759,7 @@ static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev, list_add(&mapping->list, &bo_va->invalids); amdgpu_vm_it_insert(mapping, &vm->va); - if (mapping->flags & AMDGPU_PTE_PRT_FLAG(adev)) + if (mapping->flags & AMDGPU_VM_PAGE_PRT) amdgpu_vm_prt_get(adev); if (amdgpu_vm_is_bo_always_valid(vm, bo) && !bo_va->base.moved) @@ -1818,7 +1819,7 @@ static int amdgpu_vm_verify_parameters(struct amdgpu_device *adev, int amdgpu_vm_bo_map(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, uint64_t saddr, uint64_t offset, - uint64_t size, uint64_t flags) + uint64_t size, uint32_t flags) { struct amdgpu_bo_va_mapping *mapping, *tmp; struct amdgpu_bo *bo = bo_va->base.bo; @@ -1877,7 +1878,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, uint64_t saddr, uint64_t offset, - uint64_t size, uint64_t flags) + uint64_t size, uint32_t flags) { struct amdgpu_bo_va_mapping *mapping; struct amdgpu_bo *bo = bo_va->base.bo; @@ -2734,7 +2735,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) dma_fence_put(vm->last_tlb_flush); list_for_each_entry_safe(mapping, tmp, &vm->freed, list) { - if (mapping->flags & AMDGPU_PTE_PRT_FLAG(adev) && prt_fini_needed) { + if (mapping->flags & AMDGPU_VM_PAGE_PRT && prt_fini_needed) { amdgpu_vm_prt_fini(adev, vm); prt_fini_needed = false; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index fd086efd8457e..3b4fa3246675f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -538,11 +538,11 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, int amdgpu_vm_bo_map(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, uint64_t addr, uint64_t offset, - uint64_t size, uint64_t flags); + uint64_t size, uint32_t flags); int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, uint64_t addr, uint64_t offset, - uint64_t size, uint64_t flags); + uint64_t size, uint32_t flags); int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, uint64_t addr); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 7923f491cf733..7031dd8c3c5eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -466,24 +466,6 @@ static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int * 0 valid */ -static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) -{ - switch (flags) { - case AMDGPU_VM_MTYPE_DEFAULT: - return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_NC); - case AMDGPU_VM_MTYPE_NC: - return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_NC); - case AMDGPU_VM_MTYPE_WC: - return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_WC); - case AMDGPU_VM_MTYPE_CC: - return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_CC); - case AMDGPU_VM_MTYPE_UC: - return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC); - default: - return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_NC); - } -} - static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, uint64_t *addr, uint64_t *flags) { @@ -508,21 +490,39 @@ static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, } static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, - struct amdgpu_bo_va_mapping *mapping, + struct amdgpu_vm *vm, + struct amdgpu_bo *bo, + uint32_t vm_flags, uint64_t *flags) { - struct amdgpu_bo *bo = mapping->bo_va->base.bo; - - *flags &= ~AMDGPU_PTE_EXECUTABLE; - *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; + if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) + *flags |= AMDGPU_PTE_EXECUTABLE; + else + *flags &= ~AMDGPU_PTE_EXECUTABLE; - *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; - *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); + switch (vm_flags & AMDGPU_VM_MTYPE_MASK) { + case AMDGPU_VM_MTYPE_DEFAULT: + case AMDGPU_VM_MTYPE_NC: + default: + *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_NC); + break; + case AMDGPU_VM_MTYPE_WC: + *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_WC); + break; + case AMDGPU_VM_MTYPE_CC: + *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_CC); + break; + case AMDGPU_VM_MTYPE_UC: + *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC); + break; + } - *flags &= ~AMDGPU_PTE_NOALLOC; - *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); + if (vm_flags & AMDGPU_VM_PAGE_NOALLOC) + *flags |= AMDGPU_PTE_NOALLOC; + else + *flags &= ~AMDGPU_PTE_NOALLOC; - if (mapping->flags & AMDGPU_PTE_PRT) { + if (vm_flags & AMDGPU_VM_PAGE_PRT) { *flags |= AMDGPU_PTE_PRT; *flags |= AMDGPU_PTE_SNOOPED; *flags |= AMDGPU_PTE_LOG; @@ -563,7 +563,6 @@ static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, - .map_mtype = gmc_v10_0_map_mtype, .get_vm_pde = gmc_v10_0_get_vm_pde, .get_vm_pte = gmc_v10_0_get_vm_pte, .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index f15d691e9a203..93d2b0bbe6419 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -430,24 +430,6 @@ static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int * 0 valid */ -static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) -{ - switch (flags) { - case AMDGPU_VM_MTYPE_DEFAULT: - return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_NC); - case AMDGPU_VM_MTYPE_NC: - return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_NC); - case AMDGPU_VM_MTYPE_WC: - return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_WC); - case AMDGPU_VM_MTYPE_CC: - return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_CC); - case AMDGPU_VM_MTYPE_UC: - return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC); - default: - return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_NC); - } -} - static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level, uint64_t *addr, uint64_t *flags) { @@ -472,21 +454,39 @@ static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level, } static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev, - struct amdgpu_bo_va_mapping *mapping, + struct amdgpu_vm *vm, + struct amdgpu_bo *bo, + uint32_t vm_flags, uint64_t *flags) { - struct amdgpu_bo *bo = mapping->bo_va->base.bo; - - *flags &= ~AMDGPU_PTE_EXECUTABLE; - *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; + if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) + *flags |= AMDGPU_PTE_EXECUTABLE; + else + *flags &= ~AMDGPU_PTE_EXECUTABLE; - *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; - *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); + switch (vm_flags & AMDGPU_VM_MTYPE_MASK) { + case AMDGPU_VM_MTYPE_DEFAULT: + case AMDGPU_VM_MTYPE_NC: + default: + *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_NC); + break; + case AMDGPU_VM_MTYPE_WC: + *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_WC); + break; + case AMDGPU_VM_MTYPE_CC: + *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_CC); + break; + case AMDGPU_VM_MTYPE_UC: + *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC); + break; + } - *flags &= ~AMDGPU_PTE_NOALLOC; - *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); + if (vm_flags & AMDGPU_VM_PAGE_NOALLOC) + *flags |= AMDGPU_PTE_NOALLOC; + else + *flags &= ~AMDGPU_PTE_NOALLOC; - if (mapping->flags & AMDGPU_PTE_PRT) { + if (vm_flags & AMDGPU_VM_PAGE_PRT) { *flags |= AMDGPU_PTE_PRT; *flags |= AMDGPU_PTE_SNOOPED; *flags |= AMDGPU_PTE_LOG; @@ -527,7 +527,6 @@ static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = { .flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid, .emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb, .emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping, - .map_mtype = gmc_v11_0_map_mtype, .get_vm_pde = gmc_v11_0_get_vm_pde, .get_vm_pte = gmc_v11_0_get_vm_pte, .get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index de763105fdfd1..5e9aeaa69d284 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -453,20 +453,6 @@ static void gmc_v12_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid * 0 valid */ -static uint64_t gmc_v12_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) -{ - switch (flags) { - case AMDGPU_VM_MTYPE_DEFAULT: - return AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_NC); - case AMDGPU_VM_MTYPE_NC: - return AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_NC); - case AMDGPU_VM_MTYPE_UC: - return AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_UC); - default: - return AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_NC); - } -} - static void gmc_v12_0_get_vm_pde(struct amdgpu_device *adev, int level, uint64_t *addr, uint64_t *flags) { @@ -490,30 +476,45 @@ static void gmc_v12_0_get_vm_pde(struct amdgpu_device *adev, int level, } static void gmc_v12_0_get_vm_pte(struct amdgpu_device *adev, - struct amdgpu_bo_va_mapping *mapping, + struct amdgpu_vm *vm, + struct amdgpu_bo *bo, + uint32_t vm_flags, uint64_t *flags) { - struct amdgpu_bo *bo = mapping->bo_va->base.bo; + if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) + *flags |= AMDGPU_PTE_EXECUTABLE; + else + *flags &= ~AMDGPU_PTE_EXECUTABLE; - *flags &= ~AMDGPU_PTE_EXECUTABLE; - *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; + switch (vm_flags & AMDGPU_VM_MTYPE_MASK) { + case AMDGPU_VM_MTYPE_DEFAULT: + *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC); + break; + case AMDGPU_VM_MTYPE_NC: + default: + *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC); + break; + case AMDGPU_VM_MTYPE_UC: + *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC); + break; + } - *flags &= ~AMDGPU_PTE_MTYPE_GFX12_MASK; - *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_GFX12_MASK); + if (vm_flags & AMDGPU_VM_PAGE_NOALLOC) + *flags |= AMDGPU_PTE_NOALLOC; + else + *flags &= ~AMDGPU_PTE_NOALLOC; - if (mapping->flags & AMDGPU_PTE_PRT_GFX12) { - *flags |= AMDGPU_PTE_PRT_GFX12; + if (vm_flags & AMDGPU_VM_PAGE_PRT) { *flags |= AMDGPU_PTE_SNOOPED; *flags |= AMDGPU_PTE_SYSTEM; *flags |= AMDGPU_PTE_IS_PTE; *flags &= ~AMDGPU_PTE_VALID; } - if (bo && bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC) - *flags |= AMDGPU_PTE_DCC; - - if (bo && bo->flags & AMDGPU_GEM_CREATE_UNCACHED) - *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC); + if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | + AMDGPU_GEM_CREATE_EXT_COHERENT | + AMDGPU_GEM_CREATE_UNCACHED)) + *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC); } static unsigned gmc_v12_0_get_vbios_fb_size(struct amdgpu_device *adev) @@ -543,7 +544,6 @@ static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = { .flush_gpu_tlb_pasid = gmc_v12_0_flush_gpu_tlb_pasid, .emit_flush_gpu_tlb = gmc_v12_0_emit_flush_gpu_tlb, .emit_pasid_mapping = gmc_v12_0_emit_pasid_mapping, - .map_mtype = gmc_v12_0_map_mtype, .get_vm_pde = gmc_v12_0_get_vm_pde, .get_vm_pte = gmc_v12_0_get_vm_pte, .get_vbios_fb_size = gmc_v12_0_get_vbios_fb_size, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 8030fcd642106..f6ad7911f1e6f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -382,7 +382,9 @@ static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level, } static void gmc_v6_0_get_vm_pte(struct amdgpu_device *adev, - struct amdgpu_bo_va_mapping *mapping, + struct amdgpu_vm *vm, + struct amdgpu_bo *bo, + uint32_t vm_flags, uint64_t *flags) { *flags &= ~AMDGPU_PTE_EXECUTABLE; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index a8d5795084fc9..93d7ccb7d013a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -504,7 +504,9 @@ static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level, } static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev, - struct amdgpu_bo_va_mapping *mapping, + struct amdgpu_vm *vm, + struct amdgpu_bo *bo, + uint32_t vm_flags, uint64_t *flags) { *flags &= ~AMDGPU_PTE_EXECUTABLE; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index b45fa0cea9d27..c5e2a2c41e065 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -716,11 +716,15 @@ static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level, } static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev, - struct amdgpu_bo_va_mapping *mapping, + struct amdgpu_vm *vm, + struct amdgpu_bo *bo, + uint32_t vm_flags, uint64_t *flags) { - *flags &= ~AMDGPU_PTE_EXECUTABLE; - *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; + if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) + *flags |= AMDGPU_PTE_EXECUTABLE; + else + *flags &= ~AMDGPU_PTE_EXECUTABLE; *flags &= ~AMDGPU_PTE_PRT; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index c4d69cf4e06c7..8404695eb13fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1073,27 +1073,6 @@ static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int v * 0 valid */ -static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) - -{ - switch (flags) { - case AMDGPU_VM_MTYPE_DEFAULT: - return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); - case AMDGPU_VM_MTYPE_NC: - return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); - case AMDGPU_VM_MTYPE_WC: - return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_WC); - case AMDGPU_VM_MTYPE_RW: - return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_RW); - case AMDGPU_VM_MTYPE_CC: - return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_CC); - case AMDGPU_VM_MTYPE_UC: - return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC); - default: - return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); - } -} - static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, uint64_t *addr, uint64_t *flags) { @@ -1123,6 +1102,7 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct amdgpu_bo *bo, + uint32_t vm_flags, uint64_t *flags) { struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); @@ -1236,25 +1216,43 @@ static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, } static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, - struct amdgpu_bo_va_mapping *mapping, + struct amdgpu_vm *vm, + struct amdgpu_bo *bo, + uint32_t vm_flags, uint64_t *flags) { - struct amdgpu_bo *bo = mapping->bo_va->base.bo; - - *flags &= ~AMDGPU_PTE_EXECUTABLE; - *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; + if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) + *flags |= AMDGPU_PTE_EXECUTABLE; + else + *flags &= ~AMDGPU_PTE_EXECUTABLE; - *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; - *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; + switch (vm_flags & AMDGPU_VM_MTYPE_MASK) { + case AMDGPU_VM_MTYPE_DEFAULT: + case AMDGPU_VM_MTYPE_NC: + default: + *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_NC); + break; + case AMDGPU_VM_MTYPE_WC: + *flags |= AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_WC); + break; + case AMDGPU_VM_MTYPE_RW: + *flags |= AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_RW); + break; + case AMDGPU_VM_MTYPE_CC: + *flags |= AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC); + break; + case AMDGPU_VM_MTYPE_UC: + *flags |= AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_UC); + break; + } - if (mapping->flags & AMDGPU_PTE_PRT) { + if (vm_flags & AMDGPU_VM_PAGE_PRT) { *flags |= AMDGPU_PTE_PRT; *flags &= ~AMDGPU_PTE_VALID; } if ((*flags & AMDGPU_PTE_VALID) && bo) - gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.vm, bo, - flags); + gmc_v9_0_get_coherence_flags(adev, vm, bo, vm_flags, flags); } static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, @@ -1391,7 +1389,6 @@ static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, - .map_mtype = gmc_v9_0_map_mtype, .get_vm_pde = gmc_v9_0_get_vm_pde, .get_vm_pte = gmc_v9_0_get_vm_pte, .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index a0f22ea6d15af..e23b5a0f31f2b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1189,7 +1189,7 @@ svm_nodes_in_same_hive(struct kfd_node *node_a, struct kfd_node *node_b) } static uint64_t -svm_range_get_pte_flags(struct kfd_node *node, +svm_range_get_pte_flags(struct kfd_node *node, struct amdgpu_vm *vm, struct svm_range *prange, int domain) { struct kfd_node *bo_node; @@ -1292,10 +1292,6 @@ svm_range_get_pte_flags(struct kfd_node *node, AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; } - mapping_flags |= AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE; - - if (flags & KFD_IOCTL_SVM_FLAG_GPU_RO) - mapping_flags &= ~AMDGPU_VM_PAGE_WRITEABLE; if (flags & KFD_IOCTL_SVM_FLAG_GPU_EXEC) mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE; @@ -1305,7 +1301,10 @@ svm_range_get_pte_flags(struct kfd_node *node, if (gc_ip_version >= IP_VERSION(12, 0, 0)) pte_flags |= AMDGPU_PTE_IS_PTE; - pte_flags |= amdgpu_gem_va_map_flags(node->adev, mapping_flags); + amdgpu_gmc_get_vm_pte(node->adev, vm, NULL, mapping_flags, &pte_flags); + pte_flags |= AMDGPU_PTE_READABLE; + if (!(flags & KFD_IOCTL_SVM_FLAG_GPU_RO)) + pte_flags |= AMDGPU_PTE_WRITEABLE; return pte_flags; } @@ -1412,7 +1411,7 @@ svm_range_map_to_gpu(struct kfd_process_device *pdd, struct svm_range *prange, pr_debug("Mapping range [0x%lx 0x%llx] on domain: %s\n", last_start, prange->start + i, last_domain ? "GPU" : "CPU"); - pte_flags = svm_range_get_pte_flags(pdd->dev, prange, last_domain); + pte_flags = svm_range_get_pte_flags(pdd->dev, vm, prange, last_domain); if (readonly) pte_flags &= ~AMDGPU_PTE_WRITEABLE; From 526b60e65536ee9e7bf3bdd7414b9176630d6cf8 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 24 Jun 2025 11:37:16 -0400 Subject: [PATCH 0075/2653] drm/amdgpu/gfx11: set MQD as appriopriate for queue types MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set the MQD as appropriate for the kernel vs user queues. Acked-by: Christian König Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org # 6.16.x --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 372dceceff359..9dd49b1caa605 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4129,6 +4129,8 @@ static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, #endif if (prop->tmz_queue) tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); + if (!prop->kernel_queue) + tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1); mqd->cp_gfx_hqd_cntl = tmp; /* set up cp_doorbell_control */ @@ -4281,8 +4283,10 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, prop->allow_tunneling); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); + if (prop->kernel_queue) { + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); + } if (prop->tmz_queue) tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); mqd->cp_hqd_pq_control = tmp; From 63de58467f86f5fec7b8da805837b876708ec5bb Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 24 Jun 2025 11:38:14 -0400 Subject: [PATCH 0076/2653] drm/amdgpu/gfx12: set MQD as appriopriate for queue types MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set the MQD as appropriate for the kernel vs user queues. Acked-by: Christian König Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org # 6.16.x --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index f54cbb8907b3f..7905d646ea4cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -3026,6 +3026,8 @@ static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, #endif if (prop->tmz_queue) tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, TMZ_MATCH, 1); + if (!prop->kernel_queue) + tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_NON_PRIV, 1); mqd->cp_gfx_hqd_cntl = tmp; /* set up cp_doorbell_control */ @@ -3175,8 +3177,10 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); + if (prop->kernel_queue) { + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); + } if (prop->tmz_queue) tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TMZ, 1); mqd->cp_hqd_pq_control = tmp; From 9aaadf55f934b15c20168bf812ef5474fbcaa4a3 Mon Sep 17 00:00:00 2001 From: David Francis Date: Fri, 7 Feb 2025 14:23:22 -0500 Subject: [PATCH 0077/2653] drm: Add DRM prime interface to reassign GEM handle MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CRIU restore of drm buffer objects requires the ability to create or import a buffer object with a specific gem handle. Add new drm ioctl DRM_IOCTL_GEM_CHANGE_HANDLE, which takes the gem handle of an object and moves that object to a specified new gem handle. This ioctl needs to call drm_prime_remove_buf_handle, but that function acquires the prime lock, which the ioctl needs to hold for other purposes. Make drm_prime_remove_buf_handle not acquire the prime lock, and change its other caller to reflect this. The rest of the kernel patches required to enable CRIU can be found at https://lore.kernel.org/dri-devel/20250617194536.538681-1-David.Francis@amd.com/ v2 - Move documentation to UAPI headers v3 - Always return 0 on success Signed-off-by: David Francis Reviewed-by: Christian König --- drivers/gpu/drm/drm_gem.c | 56 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/drm_internal.h | 4 +++ drivers/gpu/drm/drm_ioctl.c | 1 + drivers/gpu/drm/drm_prime.c | 8 ++--- include/uapi/drm/drm.h | 23 ++++++++++++++ 5 files changed, 86 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c index 6a44351e58b77..4f3fc8284f48f 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -332,7 +332,12 @@ drm_gem_object_release_handle(int id, void *ptr, void *data) if (obj->funcs->close) obj->funcs->close(obj, file_priv); + mutex_lock(&file_priv->prime.lock); + drm_prime_remove_buf_handle(&file_priv->prime, id); + + mutex_unlock(&file_priv->prime.lock); + drm_vma_node_revoke(&obj->vma_node, file_priv); drm_gem_object_handle_put_unlocked(obj); @@ -988,6 +993,57 @@ drm_gem_open_ioctl(struct drm_device *dev, void *data, return ret; } +int drm_gem_change_handle_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + struct drm_gem_change_handle *args = data; + struct drm_gem_object *obj; + int ret; + + if (!drm_core_check_feature(dev, DRIVER_GEM)) + return -EOPNOTSUPP; + + obj = drm_gem_object_lookup(file_priv, args->handle); + if (!obj) + return -ENOENT; + + if (args->handle == args->new_handle) + return 0; + + mutex_lock(&file_priv->prime.lock); + + spin_lock(&file_priv->table_lock); + ret = idr_alloc(&file_priv->object_idr, obj, + args->new_handle, args->new_handle + 1, GFP_NOWAIT); + spin_unlock(&file_priv->table_lock); + + if (ret < 0) + goto out_unlock; + + if (obj->dma_buf) { + ret = drm_prime_add_buf_handle(&file_priv->prime, obj->dma_buf, args->new_handle); + if (ret < 0) { + spin_lock(&file_priv->table_lock); + idr_remove(&file_priv->object_idr, args->new_handle); + spin_unlock(&file_priv->table_lock); + goto out_unlock; + } + + drm_prime_remove_buf_handle(&file_priv->prime, args->handle); + } + + ret = 0; + + spin_lock(&file_priv->table_lock); + idr_remove(&file_priv->object_idr, args->handle); + spin_unlock(&file_priv->table_lock); + +out_unlock: + mutex_unlock(&file_priv->prime.lock); + + return ret; +} + /** * drm_gem_open - initializes GEM file-private structures at devnode open time * @dev: drm_device which is being opened by userspace diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h index e79c3c623c9ab..5a3bed48ab1f1 100644 --- a/drivers/gpu/drm/drm_internal.h +++ b/drivers/gpu/drm/drm_internal.h @@ -85,6 +85,8 @@ int drm_prime_fd_to_handle_ioctl(struct drm_device *dev, void *data, void drm_prime_init_file_private(struct drm_prime_file_private *prime_fpriv); void drm_prime_destroy_file_private(struct drm_prime_file_private *prime_fpriv); +int drm_prime_add_buf_handle(struct drm_prime_file_private *prime_fpriv, + struct dma_buf *dma_buf, uint32_t handle); void drm_prime_remove_buf_handle(struct drm_prime_file_private *prime_fpriv, uint32_t handle); @@ -170,6 +172,8 @@ int drm_gem_close_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); int drm_gem_flink_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); +int drm_gem_change_handle_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); int drm_gem_open_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); void drm_gem_open(struct drm_device *dev, struct drm_file *file_private); diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index f593dc569d319..d8a24875a7bab 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -653,6 +653,7 @@ static const struct drm_ioctl_desc drm_ioctls[] = { DRM_IOCTL_DEF(DRM_IOCTL_GEM_CLOSE, drm_gem_close_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF(DRM_IOCTL_GEM_FLINK, drm_gem_flink_ioctl, DRM_AUTH), DRM_IOCTL_DEF(DRM_IOCTL_GEM_OPEN, drm_gem_open_ioctl, DRM_AUTH), + DRM_IOCTL_DEF(DRM_IOCTL_GEM_CHANGE_HANDLE, drm_gem_change_handle_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETRESOURCES, drm_mode_getresources, 0), diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c index a23fc712a8b73..49235c8642bd2 100644 --- a/drivers/gpu/drm/drm_prime.c +++ b/drivers/gpu/drm/drm_prime.c @@ -93,8 +93,8 @@ struct drm_prime_member { struct rb_node handle_rb; }; -static int drm_prime_add_buf_handle(struct drm_prime_file_private *prime_fpriv, - struct dma_buf *dma_buf, uint32_t handle) +int drm_prime_add_buf_handle(struct drm_prime_file_private *prime_fpriv, + struct dma_buf *dma_buf, uint32_t handle) { struct drm_prime_member *member; struct rb_node **p, *rb; @@ -190,8 +190,6 @@ void drm_prime_remove_buf_handle(struct drm_prime_file_private *prime_fpriv, { struct rb_node *rb; - mutex_lock(&prime_fpriv->lock); - rb = prime_fpriv->handles.rb_node; while (rb) { struct drm_prime_member *member; @@ -210,8 +208,6 @@ void drm_prime_remove_buf_handle(struct drm_prime_file_private *prime_fpriv, rb = rb->rb_left; } } - - mutex_unlock(&prime_fpriv->lock); } void drm_prime_init_file_private(struct drm_prime_file_private *prime_fpriv) diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index e63a71d3c607a..7fa123e11c3f5 100644 --- a/include/uapi/drm/drm.h +++ b/include/uapi/drm/drm.h @@ -625,6 +625,21 @@ struct drm_gem_open { __u64 size; }; +/** + * struct drm_gem_change_handle - Argument for &DRM_IOCTL_GEM_CHANGE_HANDLE ioctl. + * @handle: The handle of a gem object. + * @new_handle: An available gem handle. + * + * This ioctl changes the handle of a GEM object to the specified one. + * The new handle must be unused. On success the old handle is closed + * and all further IOCTL should refer to the new handle only. + * Calls to DRM_IOCTL_PRIME_FD_TO_HANDLE will return the new handle. + */ +struct drm_gem_change_handle { + __u32 handle; + __u32 new_handle; +}; + /** * DRM_CAP_DUMB_BUFFER * @@ -1309,6 +1324,14 @@ extern "C" { */ #define DRM_IOCTL_SET_CLIENT_NAME DRM_IOWR(0xD1, struct drm_set_client_name) +/** + * DRM_IOCTL_GEM_CHANGE_HANDLE - Move an object to a different handle + * + * Some applications (notably CRIU) need objects to have specific gem handles. + * This ioctl changes the object at one gem handle to use a new gem handle. + */ +#define DRM_IOCTL_GEM_CHANGE_HANDLE DRM_IOWR(0xD2, struct drm_gem_change_handle) + /* * Device specific ioctls should only be in their respective headers * The device specific ioctl range is from 0x40 to 0x9f. From 25eb0db97be8cf579f22da46cd1e858600f4525c Mon Sep 17 00:00:00 2001 From: David Francis Date: Fri, 11 Jul 2025 10:23:03 -0400 Subject: [PATCH 0078/2653] drm: Move drm_gem ioctl kerneldoc to uapi file The drm_gem ioctls were documented in internal file drm_gem.c instead of uapi header drm.h. Move them there and change to appropriate kerneldoc formatting. Signed-off-by: David Francis Reviewed-by: Simona Vetter --- drivers/gpu/drm/drm_gem.c | 30 ----------------------------- include/uapi/drm/drm.h | 40 +++++++++++++++++++++++++++------------ 2 files changed, 28 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c index 4f3fc8284f48f..d97c4e452a384 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -875,14 +875,6 @@ long drm_gem_dma_resv_wait(struct drm_file *filep, u32 handle, } EXPORT_SYMBOL(drm_gem_dma_resv_wait); -/** - * drm_gem_close_ioctl - implementation of the GEM_CLOSE ioctl - * @dev: drm_device - * @data: ioctl data - * @file_priv: drm file-private structure - * - * Releases the handle to an mm object. - */ int drm_gem_close_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) @@ -898,17 +890,6 @@ drm_gem_close_ioctl(struct drm_device *dev, void *data, return ret; } -/** - * drm_gem_flink_ioctl - implementation of the GEM_FLINK ioctl - * @dev: drm_device - * @data: ioctl data - * @file_priv: drm file-private structure - * - * Create a global name for an object, returning the name. - * - * Note that the name does not hold a reference; when the object - * is freed, the name goes away. - */ int drm_gem_flink_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) @@ -948,17 +929,6 @@ drm_gem_flink_ioctl(struct drm_device *dev, void *data, return ret; } -/** - * drm_gem_open_ioctl - implementation of the GEM_OPEN ioctl - * @dev: drm_device - * @data: ioctl data - * @file_priv: drm file-private structure - * - * Open an object using the global name, returning a handle and the size. - * - * This handle (of course) holds a reference to the object, so the object - * will not go away until the handle is deleted. - */ int drm_gem_open_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index 7fa123e11c3f5..3cd5cf15e3c9c 100644 --- a/include/uapi/drm/drm.h +++ b/include/uapi/drm/drm.h @@ -597,31 +597,47 @@ struct drm_set_version { int drm_dd_minor; }; -/* DRM_IOCTL_GEM_CLOSE ioctl argument type */ +/** + * struct drm_gem_close - Argument for &DRM_IOCTL_GEM_CLOSE ioctl. + * @handle: Handle of the object to be closed. + * @pad: Padding. + * + * Releases the handle to an mm object. + */ struct drm_gem_close { - /** Handle of the object to be closed. */ __u32 handle; __u32 pad; }; -/* DRM_IOCTL_GEM_FLINK ioctl argument type */ +/** + * struct drm_gem_flink - Argument for &DRM_IOCTL_GEM_FLINK ioctl. + * @handle: Handle for the object being named. + * @name: Returned global name. + * + * Create a global name for an object, returning the name. + * + * Note that the name does not hold a reference; when the object + * is freed, the name goes away. + */ struct drm_gem_flink { - /** Handle for the object being named */ __u32 handle; - - /** Returned global name */ __u32 name; }; -/* DRM_IOCTL_GEM_OPEN ioctl argument type */ +/** + * struct drm_gem_open - Argument for &DRM_IOCTL_GEM_OPEN ioctl. + * @name: Name of object being opened. + * @handle: Returned handle for the object. + * @size: Returned size of the object + * + * Open an object using the global name, returning a handle and the size. + * + * This handle (of course) holds a reference to the object, so the object + * will not go away until the handle is deleted. + */ struct drm_gem_open { - /** Name of object being opened */ __u32 name; - - /** Returned handle for the object */ __u32 handle; - - /** Returned size of the object */ __u64 size; }; From d1abdd4144de5fd9d33352aedd2eb81f20275d5f Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Wed, 13 Nov 2019 11:12:23 +0800 Subject: [PATCH 0079/2653] drm/amdkcl: add dkms support It's a squash of 6a2ef7359800 drm/amdkcl: fix include path in schduler 6d5954b6cff6 drm/amdkcl: describe the 'sources' file format 5579697e0041 drm/amdkcl: update sources file 3f3db2b92b63 drm/amdkcl: properly define and initialize Makefile variables d96876c7258e drm/amdkcl: cleanup LINUXINCLUDE in dkms package fdc3c5d4df0e drm/amdkcl: add dkms support Signed-off-by: Junwei Zhang Signed-off-by: Adam Yang Reviewed-by: Qiang Yu Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/symbols | 1 + drivers/gpu/drm/amd/dkms/Makefile | 23 +++++++++++++ drivers/gpu/drm/amd/dkms/dkms.conf | 40 ++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 48 +++++++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/sources | 26 +++++++++++++++ 5 files changed, 138 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/symbols create mode 100644 drivers/gpu/drm/amd/dkms/Makefile create mode 100644 drivers/gpu/drm/amd/dkms/dkms.conf create mode 100755 drivers/gpu/drm/amd/dkms/pre-build.sh create mode 100644 drivers/gpu/drm/amd/dkms/sources diff --git a/drivers/gpu/drm/amd/amdkcl/symbols b/drivers/gpu/drm/amd/amdkcl/symbols new file mode 100644 index 0000000000000..fe167314985be --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/symbols @@ -0,0 +1 @@ +SYMS="" diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile new file mode 100644 index 0000000000000..f5d9b8d250ed6 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -0,0 +1,23 @@ +LINUXINCLUDE := \ + -I$(src)/include \ + -I$(src)/include/uapi \ + -include $(src)/include/kcl/kcl_version.h \ + -include $(src)/include/rename_symbol.h \ + $(LINUXINCLUDE) + +export CONFIG_DRM_TTM=m +export CONFIG_DRM_AMDGPU=m +export CONFIG_DRM_SCHED=m +export CONFIG_DRM_AMDGPU_CIK=y +export CONFIG_DRM_AMDGPU_SI=y +export CONFIG_DRM_AMDGPU_USERPTR=y +export CONFIG_DRM_AMD_DC=y +export CONFIG_DRM_AMD_DC_DCN1_0=y + +subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK +subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI +subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 + +obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf new file mode 100644 index 0000000000000..e9e8db1bdd64e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -0,0 +1,40 @@ +PACKAGE_NAME="amdgpu" +PACKAGE_VERSION="1.0" +AUTOINSTALL="yes" +REMAKE_INITRD="yes" +PRE_BUILD="pre-build.sh $kernelver" + +# not work with RHEL DKMS +#MODULES_CONF[0]="blacklist radeon" + +BUILT_MODULE_NAME[0]="amdgpu" +BUILT_MODULE_LOCATION[0]="amd/amdgpu" +DEST_MODULE_LOCATION[0]="/updates" + +BUILT_MODULE_NAME[1]="amdttm" +BUILT_MODULE_LOCATION[1]="ttm" +DEST_MODULE_LOCATION[1]="/updates" + +BUILT_MODULE_NAME[2]="amdkcl" +BUILT_MODULE_LOCATION[2]="amd/amdkcl" +DEST_MODULE_LOCATION[2]="/updates" + +BUILT_MODULE_NAME[3]="amd-sched" +BUILT_MODULE_LOCATION[3]="scheduler" +DEST_MODULE_LOCATION[3]="/updates" + +# Find out how many CPU cores can be use if we pass appropriate -j option to make. +# DKMS could use all cores on multicore systems to build the kernel module. +num_cpu_cores() +{ + if [ -x /usr/bin/nproc ]; then + nproc + else + echo "1" + fi +} + +MAKE[0]="make -j$(num_cpu_cores) TTM_NAME=${BUILT_MODULE_NAME[1]} \ + SCHED_NAME=${BUILT_MODULE_NAME[3]} \ + -C $kernel_source_dir \ + M=$dkms_tree/$module/$module_version/build" diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh new file mode 100755 index 0000000000000..72929ce8ae064 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -0,0 +1,48 @@ +#!/bin/bash + +KCL="amd/amdkcl" +INC="include" +SRC="amd/dkms" + +KERNELVER=$1 +KERNELVER_BASE=${KERNELVER%%-*} + +version_lt () { + newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) + [ "$KERNELVER_BASE" != "$newest" ] +} + +version_ge () { + newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) + [ "$KERNELVER_BASE" = "$newest" ] +} + +version_gt () { + oldest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | head -n1) + [ "$KERNELVER_BASE" != "$oldest" ] +} + +version_le () { + oldest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | head -n1) + [ "$KERNELVER_BASE" = "$oldest" ] +} + +source $KCL/symbols + +# lookup symbol address. obsolete. +echo '// auto generated by DKMS pre-build.sh' > $KCL/symbols.c +for sym in $SYMS; do + addr=$(grep "\<$sym\>" /boot/System.map-$KERNELVER | awk -F' ' '{print $1}') + echo "void *_kcl_$sym = (void *)0x$addr;" >> $KCL/symbols.c +done + +# add amd prefix to exported symbols +find ttm -name '*.c' -exec grep EXPORT_SYMBOL {} + \ + | sort -u \ + | awk -F'[()]' '{print "#define "$2" amd"$2" //"$0}'\ + >> $INC/rename_symbol.h + +find scheduler -name '*.c' -exec grep EXPORT_SYMBOL {} + \ + | sort -u \ + | awk -F'[()]' '{print "#define "$2" amd"$2" //"$0}'\ + >> $INC/rename_symbol.h diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources new file mode 100644 index 0000000000000..b8f2af052e55a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/sources @@ -0,0 +1,26 @@ +# +# The 'sources' file contains source/destination directives to be used +# by the build framework to construct the DKMS source tree +# +# File format: +# source destination +# ------ ----------- +# directory[/file] name directory/[file] name +# must exist at the directory: must have explicit directory name +# source path e.g. dir/ (with '/'). The name without +# slash is treated as a file if it does +# not exist +# the directory will be created if it +# does not exist +# file: optional file name at the destination +# +drivers/gpu/drm/amd . +drivers/gpu/drm/ttm . +include/drm/ttm include/drm/ +include/uapi/drm/amdgpu_drm.h include/uapi/drm/ +include/kcl include/ +drivers/gpu/drm/scheduler . +include/drm/gpu_scheduler.h include/drm/ +include/drm/amd_asic_type.h include/drm/ +include/drm/spsc_queue.h include/drm/ +include/uapi/linux/kfd_ioctl.h include/uapi/linux/ From 23cd7034e19a4221317ecb1ee31ac410af4659f1 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 18 Nov 2020 10:13:46 -0500 Subject: [PATCH 0080/2653] drm/amdkcl:Fix values of DEST_MODULE_LOCATION directives The directive is used for finding original modules and must point to the original module locations. If it points to /updates the original module is placed to /updates after DKMS uninstallation that breaks the /lib/modules/ directory integrity. v2: fix quotation mark typo on dkms.conf. The path string should be enclosed in quotion marks. Signed-off-by: Slava Grigorev Signed-off-by: Rui Teng Reviewed-by: Flora Cui Change-Id: Id48f89a190c0d354147db346a468573775548c9f --- drivers/gpu/drm/amd/dkms/dkms.conf | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index e9e8db1bdd64e..86826daa80072 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -9,19 +9,19 @@ PRE_BUILD="pre-build.sh $kernelver" BUILT_MODULE_NAME[0]="amdgpu" BUILT_MODULE_LOCATION[0]="amd/amdgpu" -DEST_MODULE_LOCATION[0]="/updates" +DEST_MODULE_LOCATION[0]="/kernel/drivers/gpu/drm/amd/amdgpu" BUILT_MODULE_NAME[1]="amdttm" BUILT_MODULE_LOCATION[1]="ttm" -DEST_MODULE_LOCATION[1]="/updates" +DEST_MODULE_LOCATION[1]="/kernel/drivers/gpu/drm/ttm" BUILT_MODULE_NAME[2]="amdkcl" BUILT_MODULE_LOCATION[2]="amd/amdkcl" -DEST_MODULE_LOCATION[2]="/updates" +DEST_MODULE_LOCATION[2]="/kernel/drivers/gpu/drm/amd/amdkcl" BUILT_MODULE_NAME[3]="amd-sched" BUILT_MODULE_LOCATION[3]="scheduler" -DEST_MODULE_LOCATION[3]="/updates" +DEST_MODULE_LOCATION[3]="/kernel/drivers/gpu/drm/scheduler" # Find out how many CPU cores can be use if we pass appropriate -j option to make. # DKMS could use all cores on multicore systems to build the kernel module. From 777b825ce0251bdb22a5b5581ac7f63d874e0767 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 30 Oct 2019 10:27:35 +0800 Subject: [PATCH 0081/2653] drm/amdkcl: add amdkcl/files to include all files containing EXPORT_SYMBOL to deal with Signed-off-by: Flora Cui Reviewed-by: Kevin Wang --- drivers/gpu/drm/amd/amdkcl/files | 1 + drivers/gpu/drm/amd/dkms/pre-build.sh | 16 +++++++--------- 2 files changed, 8 insertions(+), 9 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/files diff --git a/drivers/gpu/drm/amd/amdkcl/files b/drivers/gpu/drm/amd/amdkcl/files new file mode 100644 index 0000000000000..501b9055ad408 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/files @@ -0,0 +1 @@ +FILES="ttm/*.c scheduler/*.c" diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 72929ce8ae064..0970ec311e687 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -28,6 +28,7 @@ version_le () { } source $KCL/symbols +source $KCL/files # lookup symbol address. obsolete. echo '// auto generated by DKMS pre-build.sh' > $KCL/symbols.c @@ -37,12 +38,9 @@ for sym in $SYMS; do done # add amd prefix to exported symbols -find ttm -name '*.c' -exec grep EXPORT_SYMBOL {} + \ - | sort -u \ - | awk -F'[()]' '{print "#define "$2" amd"$2" //"$0}'\ - >> $INC/rename_symbol.h - -find scheduler -name '*.c' -exec grep EXPORT_SYMBOL {} + \ - | sort -u \ - | awk -F'[()]' '{print "#define "$2" amd"$2" //"$0}'\ - >> $INC/rename_symbol.h +for file in $FILES; do + grep EXPORT_SYMBOL $file \ + | sort -u \ + | awk -F'[()]' '{print "#define "$2" amd"$2" //"$0}'\ + >> $INC/rename_symbol.h +done From 7abf206c5e7643b3d136b03d515f3ef77820f453 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Mon, 16 Mar 2020 10:55:26 -0400 Subject: [PATCH 0082/2653] amd/amdkcl: simplify pre-build.sh script code Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/pre-build.sh | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 0970ec311e687..5e6a61aa8d83e 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -33,14 +33,14 @@ source $KCL/files # lookup symbol address. obsolete. echo '// auto generated by DKMS pre-build.sh' > $KCL/symbols.c for sym in $SYMS; do - addr=$(grep "\<$sym\>" /boot/System.map-$KERNELVER | awk -F' ' '{print $1}') - echo "void *_kcl_$sym = (void *)0x$addr;" >> $KCL/symbols.c + awk -v sym=$sym '/\/ { + print "void *_kcl_" $3 " = (void *)0x" $1 ";" + }' /boot/System.map-$KERNELVER >>$KCL/symbols.c done # add amd prefix to exported symbols for file in $FILES; do - grep EXPORT_SYMBOL $file \ - | sort -u \ - | awk -F'[()]' '{print "#define "$2" amd"$2" //"$0}'\ - >> $INC/rename_symbol.h + awk -F'[()]' '/EXPORT_SYMBOL/ { + print "#define "$2" amd"$2" //"$0 + }' $file | sort -u >>$INC/rename_symbol.h done From 63d27072ca3a282824c5f4b84f973e01d33b9cb9 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 22 Jul 2020 11:10:32 +0800 Subject: [PATCH 0083/2653] drm/amdkcl: rename CONFIG_DRM_xxx & amdgpu configs otherwise kernel config would override dkms package config v2: update ttm/schduler configs, incase ttm/schduler is built-in Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/dkms/pre-build.sh | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 5e6a61aa8d83e..9fb471b43a708 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -44,3 +44,15 @@ for file in $FILES; do print "#define "$2" amd"$2" //"$0 }' $file | sort -u >>$INC/rename_symbol.h done + +# rename CONFIG_xxx to CONFIG_xxx_AMDKCL +# otherwise kernel config would override dkms package config +AMDGPU_CONFIG=$(find -name Kconfig -exec grep -h '^config' {} + | sed 's/ /_/' | tr 'a-z' 'A-Z') +TTM_CONFIG=$(awk '/CONFIG_DRM/{gsub(".*\\(CONFIG_DRM","CONFIG_DRM");gsub("\\).*","");print $0}' ttm/Makefile) +SCHED_CONFIG=$(awk '/CONFIG_DRM/{gsub(".*\\(CONFIG_DRM","CONFIG_DRM");gsub("\\).*","");print $0}' scheduler/Makefile) +for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do + for file in $(grep -rl $config ./); do + sed -i "s/\<$config\>/&_AMDKCL/" $file + done + sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile +done From c7fdfa0fe3b9eddf794d9f0688326b9f9b57ac5e Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Fri, 23 Dec 2016 14:23:29 +0800 Subject: [PATCH 0084/2653] drm/amdkcl: add backport support for amdgpu v2: drop kcl_amdgpu.o It's a squash of 221c1ea7b3dbd drm/amdkcl: fix license 3f3db2b92b63 drm/amdkcl: properly define and initialize Makefile variables 0275f0fd138c drm/amdkcl: fix out of tree build 383595ad14e1 drm/amdkcl: add backport support for amdgpu Signed-off-by: Junwei Zhang Signed-off-by: Flora Cui Reviewed-by: Qiang Yu Signed-off-by: Qiang Yu Reviewed-by: Junwei Zhang Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 ++ drivers/gpu/drm/amd/backport/Makefile | 8 ++++++++ drivers/gpu/drm/amd/backport/backport.h | 7 +++++++ 3 files changed, 17 insertions(+) create mode 100644 drivers/gpu/drm/amd/backport/Makefile create mode 100644 drivers/gpu/drm/amd/backport/backport.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 930de203d533c..574cc10948e67 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -324,4 +324,6 @@ amdgpu-y += \ isp_v4_1_1.o endif +include $(FULL_AMD_PATH)/backport/Makefile + obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile new file mode 100644 index 0000000000000..ca667992f6f72 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: MIT +BACKPORT_OBJS := + +amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) + +ccflags-y += \ + -I$(FULL_AMD_PATH)/backport/include \ + -include ../backport/backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h new file mode 100644 index 0000000000000..89cd9143a9c0a --- /dev/null +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDGPU_BACKPORT_H +#define AMDGPU_BACKPORT_H + +#include +#include +#endif /* AMDGPU_BACKPORT_H */ From 8e57645a91ae83080812fc689402aa33d20ddef8 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Wed, 13 Nov 2019 11:15:31 +0800 Subject: [PATCH 0085/2653] drm/amdkcl: add backport support for scheduler It's a squash of 6a2ef7359800 drm/amdkcl: fix include path in schduler 221c1ea7b3dbd drm/amdkcl: fix license 6e5bc9b8e7ea amd/amdkcl: drop use of BUILD_AS_DKMS in Makefile files 3f3db2b92b63 drm/amdkcl: properly define and initialize Makefile variables de12801935af drm/amdkcl: add backport support for scheduler Signed-off-by: Le.Ma Reviewed-by: Qiang Yu Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/scheduler/Makefile | 11 +++++++++-- drivers/gpu/drm/scheduler/backport/Makefile | 4 ++++ drivers/gpu/drm/scheduler/backport/backport.h | 7 +++++++ 3 files changed, 20 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/scheduler/backport/Makefile create mode 100644 drivers/gpu/drm/scheduler/backport/backport.h diff --git a/drivers/gpu/drm/scheduler/Makefile b/drivers/gpu/drm/scheduler/Makefile index 6e13e4c63e9d8..a5ad916153351 100644 --- a/drivers/gpu/drm/scheduler/Makefile +++ b/drivers/gpu/drm/scheduler/Makefile @@ -20,8 +20,15 @@ # OTHER DEALINGS IN THE SOFTWARE. # # -gpu-sched-y := sched_main.o sched_fence.o sched_entity.o +SCHED_NAME = gpu-sched -obj-$(CONFIG_DRM_SCHED) += gpu-sched.o +$(SCHED_NAME)-y := sched_main.o sched_fence.o sched_entity.o +obj-$(CONFIG_DRM_SCHED) += $(SCHED_NAME).o obj-$(CONFIG_DRM_SCHED_KUNIT_TEST) += tests/ + +SCHED_FULL_PATH = $(src) + +ccflags-y := -I$(SCHED_FULL_PATH) + +include $(SCHED_FULL_PATH)/backport/Makefile diff --git a/drivers/gpu/drm/scheduler/backport/Makefile b/drivers/gpu/drm/scheduler/backport/Makefile new file mode 100644 index 0000000000000..5fe7a0b580f33 --- /dev/null +++ b/drivers/gpu/drm/scheduler/backport/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT +ccflags-y += \ + -I$(SCHED_FULL_PATH) \ + -include backport/backport.h diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h new file mode 100644 index 0000000000000..b8c8be307a2e7 --- /dev/null +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDSCHED_BACKPORT_H +#define AMDSCHED_BACKPORT_H + +#include + +#endif From 1f24bf09c20efe4c6cffa7cb8a52ee55d9279e78 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Wed, 13 Nov 2019 11:16:11 +0800 Subject: [PATCH 0086/2653] drm/amdkcl: add backport support for ttm It's a squash of 221c1ea7b3dbd drm/amdkcl: fix license 6e5bc9b8e7ea amd/amdkcl: drop use of BUILD_AS_DKMS in Makefile files 3f3db2b92b63 drm/amdkcl: properly define and initialize Makefile variables e173231be48f drm/amdkcl: add backport support for ttm Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui --- drivers/gpu/drm/ttm/Makefile | 15 ++++++++++++--- drivers/gpu/drm/ttm/backport/Makefile | 4 ++++ drivers/gpu/drm/ttm/backport/backport.h | 7 +++++++ 3 files changed, 23 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/ttm/backport/Makefile create mode 100644 drivers/gpu/drm/ttm/backport/backport.h diff --git a/drivers/gpu/drm/ttm/Makefile b/drivers/gpu/drm/ttm/Makefile index 40d07a35293a7..e10443408f593 100644 --- a/drivers/gpu/drm/ttm/Makefile +++ b/drivers/gpu/drm/ttm/Makefile @@ -2,10 +2,19 @@ # # Makefile for the drm device driver. This driver provides support for the -ttm-y := ttm_tt.o ttm_bo.o ttm_bo_util.o ttm_bo_vm.o ttm_module.o \ +# +# In DKMS mode the module can be renamed by passing TTM_NAME as a parameter +# to 'make' if required +# +TTM_NAME = ttm + +$(TTM_NAME)-y := ttm_tt.o ttm_bo.o ttm_bo_util.o ttm_bo_vm.o ttm_module.o \ ttm_execbuf_util.o ttm_range_manager.o ttm_resource.o ttm_pool.o \ ttm_device.o ttm_sys_manager.o ttm_backup.o -ttm-$(CONFIG_AGP) += ttm_agp_backend.o +$(TTM_NAME)-$(CONFIG_AGP) += ttm_agp_backend.o -obj-$(CONFIG_DRM_TTM) += ttm.o +obj-$(CONFIG_DRM_TTM) += $(TTM_NAME).o obj-$(CONFIG_DRM_TTM_KUNIT_TEST) += tests/ + +TTM_FULL_PATH = $(src) +include $(TTM_FULL_PATH)/backport/Makefile diff --git a/drivers/gpu/drm/ttm/backport/Makefile b/drivers/gpu/drm/ttm/backport/Makefile new file mode 100644 index 0000000000000..839110332c785 --- /dev/null +++ b/drivers/gpu/drm/ttm/backport/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT +ccflags-y += \ + -I$(TTM_FULL_PATH) \ + -include backport/backport.h diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h new file mode 100644 index 0000000000000..524d2a01b50df --- /dev/null +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDTTM_BACKPORT_H +#define AMDTTM_BACKPORT_H + +#include + +#endif From 61a94caade38585ca8c57c15ad43bf10782d4e88 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 15 Dec 2016 11:52:56 +0800 Subject: [PATCH 0087/2653] drm/amdkcl[ttm]: rename the device name to amdttm v2: fix ttm name to differentia package driver Signed-off-by: Qiang Yu Reviewed-by: Junwei Zhang Signed-off-by: Jack Gui Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/ttm/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/ttm/Makefile b/drivers/gpu/drm/ttm/Makefile index e10443408f593..d01dfb469a208 100644 --- a/drivers/gpu/drm/ttm/Makefile +++ b/drivers/gpu/drm/ttm/Makefile @@ -7,6 +7,8 @@ # to 'make' if required # TTM_NAME = ttm +ccflags-y += \ + -DTTM_NAME="\"$(TTM_NAME)\"" $(TTM_NAME)-y := ttm_tt.o ttm_bo.o ttm_bo_util.o ttm_bo_vm.o ttm_module.o \ ttm_execbuf_util.o ttm_range_manager.o ttm_resource.o ttm_pool.o \ From 428011a8847e7ee55d63a899b4f64f5d7b096e17 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Mon, 16 Sep 2019 11:48:05 +0800 Subject: [PATCH 0088/2653] drm/amdkcl: use $(src) in Makefile when built with dkms v2: Properly define ..._FULL_PATH variables in amdgpu, ttm, and scheduler trees. That fixes 'make -C ... M=... modiles' build to succeed correctly. It's a squash of 3f3db2b92b63 drm/amdkcl: properly define and initialize Makefile variables a5abb9e0c999 drm/amdkcl: use $(src) in Makefile when built with dkms Signed-off-by: Adam Yang Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/scheduler/Makefile | 2 +- drivers/gpu/drm/ttm/Makefile | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 574cc10948e67..e9246467898bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -23,7 +23,7 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -FULL_AMD_PATH=$(src)/.. +FULL_AMD_PATH := $(patsubst %/amdgpu,%,$(src)) DISPLAY_FOLDER_NAME=display FULL_AMD_DISPLAY_PATH = $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME) diff --git a/drivers/gpu/drm/scheduler/Makefile b/drivers/gpu/drm/scheduler/Makefile index a5ad916153351..705573ee221aa 100644 --- a/drivers/gpu/drm/scheduler/Makefile +++ b/drivers/gpu/drm/scheduler/Makefile @@ -27,7 +27,7 @@ obj-$(CONFIG_DRM_SCHED) += $(SCHED_NAME).o obj-$(CONFIG_DRM_SCHED_KUNIT_TEST) += tests/ -SCHED_FULL_PATH = $(src) +SCHED_FULL_PATH := $(src) ccflags-y := -I$(SCHED_FULL_PATH) diff --git a/drivers/gpu/drm/ttm/Makefile b/drivers/gpu/drm/ttm/Makefile index d01dfb469a208..56d5f0704c155 100644 --- a/drivers/gpu/drm/ttm/Makefile +++ b/drivers/gpu/drm/ttm/Makefile @@ -18,5 +18,5 @@ $(TTM_NAME)-$(CONFIG_AGP) += ttm_agp_backend.o obj-$(CONFIG_DRM_TTM) += $(TTM_NAME).o obj-$(CONFIG_DRM_TTM_KUNIT_TEST) += tests/ -TTM_FULL_PATH = $(src) +TTM_FULL_PATH := $(src) include $(TTM_FULL_PATH)/backport/Makefile From fc14c65b8584581d7a272de2e38c346bf604a101 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Sat, 21 Mar 2020 19:19:35 -0400 Subject: [PATCH 0089/2653] amd/amdkcl: drop use of BUILD_AS_DKMS in Makefile files Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 2 +- drivers/gpu/drm/scheduler/gpu_scheduler_trace.h | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index e9246467898bd..3e0e0e28d53cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -327,3 +327,5 @@ endif include $(FULL_AMD_PATH)/backport/Makefile obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o + +CFLAGS_amdgpu_trace_points.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index d13e64a69e255..72f13cd5f5407 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -583,5 +583,5 @@ TRACE_EVENT(amdgpu_reset_reg_dumps, /* This part must be outside protection */ #undef TRACE_INCLUDE_PATH -#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/amd/amdgpu +#define TRACE_INCLUDE_PATH . #include diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h b/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h index 261713dd7d5a1..0f965676764f7 100644 --- a/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h +++ b/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h @@ -155,5 +155,5 @@ TRACE_EVENT(drm_sched_job_unschedulable, /* This part must be outside protection */ #undef TRACE_INCLUDE_PATH -#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/scheduler +#define TRACE_INCLUDE_PATH . #include From 4f5f31630a086b6dd193a1733b019b10ba1c1651 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Fri, 8 Nov 2019 12:13:34 +0800 Subject: [PATCH 0090/2653] drm/amdkcl: add amdkcl support It's a squash of 221c1ea7b3dbd drm/amdkcl: fix license 3f3db2b92b63 drm/amdkcl: properly define and initialize Makefile variables 079a1dd78a42 drm/amdkcl: add amdkcl support Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Flora Cui Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkcl/Makefile | 4 ++++ drivers/gpu/drm/amd/amdkcl/main.c | 20 ++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/Makefile create mode 100644 drivers/gpu/drm/amd/amdkcl/main.c diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile new file mode 100644 index 0000000000000..018792c49a249 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT +amdkcl-y += main.o + +obj-m += amdkcl.o diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c new file mode 100644 index 0000000000000..59f4520c9a8bd --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: MIT */ +#include +#include + +int __init amdkcl_init(void) +{ + return 0; +} +module_init(amdkcl_init); + +void __exit amdkcl_exit(void) +{ +} + +module_exit(amdkcl_exit); + +MODULE_AUTHOR("AMD linux driver team"); +MODULE_DESCRIPTION("Module for OS kernel compatible layer"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); From 0029df2f3ccc123f6a4348f8cfe4df694b33c931 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Thu, 29 Dec 2016 15:07:05 +0800 Subject: [PATCH 0091/2653] drm/amdkcl: use system drm header include uapi/drm/drm.h in $(srctree) Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Flora Cui --- include/uapi/drm/amdgpu_drm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index bdedbaccf776d..dab5a759d9f4a 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -32,7 +32,7 @@ #ifndef __AMDGPU_DRM_H__ #define __AMDGPU_DRM_H__ -#include "drm.h" +#include #if defined(__cplusplus) extern "C" { From 18356f03bf91dd895e7fac92ea373a2eedf649d2 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Fri, 10 Aug 2018 16:36:26 +0800 Subject: [PATCH 0092/2653] drm/amdkcl: add drm version support (v3) v2: detect building kernel automatically custom kernel build support v3: support specific kbuild path v4: VERSION & PATCHLEVEL are exported in kernel Makefile and can be accessed directly It's a squash of 5eb73682006d drm/amdkcl: refactor dkms/Makefile b3160e09da52 drm/amdkcl: simplify DRM_VER retrieve 225506373f54 drm/amdkcl: add drm version support (v3) Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Reviewed-by: Yang Xiong Signed-off-by: Flora Cui --- Makefile | 7 ++++++- drivers/gpu/drm/amd/dkms/Makefile | 12 ++++++++++++ include/kcl/kcl_version.h | 8 ++++++++ 3 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 include/kcl/kcl_version.h diff --git a/Makefile b/Makefile index 478f2004602da..b907e0b7a7332 100644 --- a/Makefile +++ b/Makefile @@ -1322,7 +1322,12 @@ define filechk_version.h ((c) > 255 ? 255 : (c)))'; \ echo \#define LINUX_VERSION_MAJOR $(VERSION); \ echo \#define LINUX_VERSION_PATCHLEVEL $(PATCHLEVEL); \ - echo \#define LINUX_VERSION_SUBLEVEL $(SUBLEVEL) + echo \#define LINUX_VERSION_SUBLEVEL $(SUBLEVEL); \ + echo '#define DRM_VER $(VERSION)'; \ + echo '#define DRM_PATCH $(PATCHLEVEL)'; \ + echo '#define DRM_SUB $(SUBLEVEL)'; \ + echo \#define DRM_VERSION_CODE LINUX_VERSION_CODE; \ + echo '#define DRM_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))' endef $(version_h): private PATCHLEVEL := $(or $(PATCHLEVEL), 0) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index f5d9b8d250ed6..359ad88155b58 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -1,3 +1,15 @@ +DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) +DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) +ifeq ($(DRM_VER),) +DRM_VER = $(VERSION) +DRM_PATCH = $(PATCHLEVEL) +endif + +subdir-ccflags-y += \ + -DDRM_VER=$(DRM_VER) \ + -DDRM_PATCH=$(DRM_PATCH) \ + -DDRM_SUB="0" + LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/uapi \ diff --git a/include/kcl/kcl_version.h b/include/kcl/kcl_version.h new file mode 100644 index 0000000000000..4a470ef6dbbc7 --- /dev/null +++ b/include/kcl/kcl_version.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_VERSION_H +#define AMDKCL_VERSION_H + +#define DRM_VERSION(a, b, c) (((a) << 16) + ((b) << 8) + (c)) +#define DRM_VERSION_CODE DRM_VERSION(DRM_VER, DRM_PATCH, DRM_SUB) + +#endif From a6865fc9c5b283683806c1b2cc134fe85d242040 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Mon, 17 Aug 2020 17:05:09 +0800 Subject: [PATCH 0093/2653] drm/amdkcl: add RHEL_MAJOR/RHEL_MINOR v2: for not generic RHEL OS eg:rhel6 rootfs + rhel7.2 kernel before: define macro OS_NAME_RHEL_6 (error) after: define macro OS_NAME_RHEL_7_2 (ok) It's a squash of 10fee5987c68 drm/amdkcl: refactor get_rhel_version 5eb73682006d drm/amdkcl: refactor dkms/Makefile 2b4eefb780d3 drm/amdkcl: drop kdir in dkms package 01253fdd953b drm/amdkcl: fix RHEL_ version check for rhel8.x 1dbfa0ac3b7f drm/amdkcl: update dkms detect OS method fdc3c5d4df0e drm/amdkcl: add dkms support Signed-off-by: Junwei Zhang Signed-off-by: Adam Yang Reviewed-by: Qiang Yu Reviewed-by: Flora Cui Signed-off-by: Kevin Wang Reviewed-by: Junwei Zhang Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/dkms/Makefile | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 359ad88155b58..37cfe6546b880 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -10,6 +10,12 @@ subdir-ccflags-y += \ -DDRM_PATCH=$(DRM_PATCH) \ -DDRM_SUB="0" +define get_rhel_version +printf "#include \n$(1)" | $(CC) $(LINUXINCLUDE) -E -x c - | tail -n 1 | grep -v $(1) +endef +RHEL_MAJOR := $(shell $(call get_rhel_version,RHEL_MAJOR)) +RHEL_MINOR := $(shell $(call get_rhel_version,RHEL_MINOR)) + LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/uapi \ From 3b74d3d420b828fc802b4b5af59ed63c5e449f3a Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Mon, 17 Aug 2020 17:12:12 +0800 Subject: [PATCH 0094/2653] drm/amdkcl: add various os support for RHEL 8.0: (Changfeng.Zhu@amd.com) Both KERNEL VERSION and DRM VERSION of redhat 8.0 are 4.18.0.So it needs some changes in Makefile for redhat 8.0. There is no drm_backport.h for RHEL 8.0.So it doesn't need to include drm_backport.h for customized CentOS/RHEL: (Amber.Lin@amd.com) When RHEL_MAJOR doesn't exist in kernel's Makefile, this is not a standard kernel source distributed from CentOS/RHEL. If /etc/os-release identifies a CentOS/RHEL OS, we should treat it as a customized rhel platform. An example is to install upstream 4.16 kernel from elrepo.org on CentOS 7.5. /etc/centos-release-upstream tells OS version as 7.5 but this is not a 3.10.0-862 kernel. for DEBIAN 9.3 (with kernel-4.19): (yttao@amd.com) Because there are two Makefile path in Debian. One is at xxx-amd64(kernel version is always 2.6) and another is at xxx-common(kernel version is correct). And the real one is actually located at xxx-common. So we need manually specify the Makefile at xxx-common in order to read the correct kernel version. for Debian (custom kernels): (63921018+emollier@users.noreply.github.com) The current rock-dkms Makefile takes properly into account the specificities of the Debian native kernel. However, when a custom upstream kernel is installed, notably through packages obtained via `make deb-pkg`, the driver is not built against that specific kernel. Falling back to the initial kdir value when there is no source/ directory allows to build against such kernels on Debian. for OS_VERSION str: (Flora.Cui@amd.com) simplify OS_VERSION macro handling Signed-off-by: changzhu Reviewed-by: Rui Teng Signed-off-by: Keivn Wang Reviewed-by: Junwei Zhang Signed-off-by: Amber Lin Acked-by: Felix Kuehling Reviewed-by: Junwei Zhang Signed-off-by: Jeremy Newton Reviewed-by: Slava Abramov Signed-off-by: Yintian Tao Reviewed-by: changzhu Signed-off-by: changzhu Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Reviewed-by: Rui Teng Signed-off-by: Adam Yang Reviewed-by: Flora Cui Reviewed-by: Rui Teng Signed-off-by: Slava Grigorev Signed-off-by: Etienne Mollier Signed-off-by: Kent Russell Signed-off-by: Anatoli Antonovitch Tested-by: Anatoli Antonovitch Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/dkms/Makefile | 78 +++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 37cfe6546b880..cb38a2549c569 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -16,6 +16,84 @@ endef RHEL_MAJOR := $(shell $(call get_rhel_version,RHEL_MAJOR)) RHEL_MINOR := $(shell $(call get_rhel_version,RHEL_MINOR)) +ifneq (,$(RHEL_MAJOR)) +OS_NAME = "rhel" +OS_VERSION = "$(RHEL_MAJOR).$(RHEL_MINOR)" +else ifneq (,$(wildcard /etc/os-release)) +OS_NAME = "$(shell sed -n 's/^ID=\(.*\)/\1/p' /etc/os-release | tr -d '\"')" +# On CentOS/RHEL, users could have installed a kernel not distributed from RHEL +ifeq ("centos",$(OS_NAME)) +OS_NAME="custom-rhel" +else ifeq ("rhel",$(OS_NAME)) +OS_NAME="custom-rhel" +else ifeq ("linuxmint",$(OS_NAME)) +OS_NAME="ubuntu" +endif +OS_VERSION = $(shell sed -n 's/^VERSION_ID=\(.*\)/\1/p' /etc/os-release) +else +OS_NAME = "unknown" +OS_VERSION = "0.0" +endif + +OS_VERSION_STR = $(subst .,_,$(OS_VERSION)) + +ifeq ("ubuntu",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_UBUNTU +else ifeq ("rhel",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_RHEL +else ifeq ("steamos",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_STEAMOS +else ifeq ("sled",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_SLE +else ifeq ("sles",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_SLE +else ifeq ("amzn",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_AMZ +else ifeq ("debian",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_DEBIAN +else +subdir-ccflags-y += -DOS_NAME_UNKNOWN +endif + +subdir-ccflags-y += \ + -DOS_VERSION_MAJOR=$(shell echo $(OS_VERSION).0 | cut -d. -f1) \ + -DOS_VERSION_MINOR=$(shell echo $(OS_VERSION).0 | cut -d. -f2) + +ifeq ($(OS_NAME),"opensuse-leap") +subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"sled") +subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"sles") +subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"ubuntu") +OS_BUILD_NUM = $(shell echo $(KERNELRELEASE) | cut -d '-' -f 2) +subdir-ccflags-y += -DUBUNTU_BUILD_NUM=$(OS_BUILD_NUM) +OS_OEM = "$(shell echo $(KERNELRELEASE) | cut -d '-' -f 3)" +ifeq ($(OS_OEM),"oem") +subdir-ccflags-y += -DOS_NAME_UBUNTU_OEM +endif +subdir-ccflags-y += -DOS_NAME_UBUNTU_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"rhel") +subdir-ccflags-y += -DOS_NAME_RHEL_$(OS_VERSION_STR) + +ifeq ($(RHEL_MAJOR),7) +subdir-ccflags-y += -DOS_NAME_RHEL_7_X \ + -include /usr/src/kernels/$(KERNELRELEASE)/include/drm/drm_backport.h +else ifeq ($(RHEL_MAJOR),8) +subdir-ccflags-y += -DOS_NAME_RHEL_8_X +endif +endif + +export OS_NAME OS_VERSION + LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/uapi \ From 8099e6b3cd1fa7a5331f5573f5fbfd0fb375944c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 27 Jul 2020 15:13:05 +0800 Subject: [PATCH 0095/2653] drm/amdkcl: check the prerequisites first fail early if DRM is disabled or DRM_AMDGPU is built-in. Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/dkms/Makefile | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index cb38a2549c569..940586b3cebf1 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -1,3 +1,11 @@ +ifndef CONFIG_DRM +$(error CONFIG_DRM disabled, exit...) +endif + +ifeq (y,$(CONFIG_DRM_AMDGPU)) +$(error DRM_AMDGPU is built-in, exit...) +endif + DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) From cd998805b7f518d491d2feb887b1604cd010c41a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 19 Aug 2020 15:16:19 +0800 Subject: [PATCH 0096/2653] drm/amdkcl: add dependency for CONFIG_KALLSYMS kallsyms_lookup_name() is a must for legacy kernel support. fail dkms install if CONFIG_KALLSYMS disabled. Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 940586b3cebf1..a23742b01fa26 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -6,6 +6,10 @@ ifeq (y,$(CONFIG_DRM_AMDGPU)) $(error DRM_AMDGPU is built-in, exit...) endif +ifndef CONFIG_KALLSYMS +$(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) +endif + DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) From bafbd814650a23534a7115da30a9c3768ee424d6 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 16 Oct 2020 13:47:30 +0800 Subject: [PATCH 0097/2653] drm/amdkcl: extract _is_kcl_macro_defined to check a macro defined in config.h Signed-off-by: Flora Cui Reviewed-by: shiwu.zhang --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index a23742b01fa26..509625a2b36e0 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -10,6 +10,8 @@ ifndef CONFIG_KALLSYMS $(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) endif +_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") + DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) From 745cc2db517f7119256e8c5348221ce7ca5546f0 Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Tue, 28 Jul 2020 13:22:40 -0400 Subject: [PATCH 0098/2653] drm/amdkcl: Add warning when GCCs do not match v2 If the GCC used to compile the kernel doesn't match the current GCC on the system, print a warning to let the user know. This can hopefully help to find bugs from differing GCC versions causing unexpected and hard-to-track-down errors v2: Avoid quirks with cc-ifversion, don't hardcode gcc v3: drm/amdkcl: update the func to get gcc version get gcc version the same way with $(srctree)/scripts/gcc-version.sh can't leverage gcc-version.sh/gcc-version as the interface changes. the history for gcc-version.sh/gcc-version is: v5.6-12065-g77342a02ff6e gcc-plugins: drop support for GCC <= 4.7 v5.0-rc4-38-gfa7295ab69a3 kbuild: clean up scripts/gcc-version.sh v4.17-6942-g59f53855babf gcc-plugins: test plugin support in Kconfig and clean up Makefile v4.17-6936-ga4353898980c kconfig: add CC_IS_GCC and GCC_VERSION Signed-off-by: Kent Russell Reviewed-by: Felix Kuehling Reviewed-by: Kent Russell Signed-off-by: Flora Cui Change-Id: Ibf64db43988609d8b48865d1eeee8efdc2ed98e2 --- drivers/gpu/drm/amd/dkms/Makefile | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 509625a2b36e0..8ca4f3cba1457 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -12,6 +12,18 @@ endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") +ifdef CONFIG_CC_IS_GCC +GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) +GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) +GCCPAT=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) +# CONFIG_GCC_VERSION returns x.xx.xx as the version format +GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) +ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) +$(warning "Local GCC version $(GCCSTR) does not match kernel compiler GCC version $(CONFIG_GCC_VERSION)") +$(warning "This may cause unexpected and hard-to-isolate compiler-related issues") +endif +endif + DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) From 750ac74ce296dcb423b94e117285b3ec0219f202 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Wed, 22 Aug 2018 12:42:06 +0800 Subject: [PATCH 0099/2653] drm/amdkcl: enable CONFIG_HSA_AMD v1: 05b0848bf51c drm/amdkcl: [KFD] add kfd dkms support v2: 5fb3731bafd8 drm/amdkcl: fix amdkfd module confusion by correcting value of CONFIG_HSA_AMD v3: 77843fb3174f drm/amdkcl: add DKMS support for amdkfd module build in amdgpu. Signed-off-by: Kevin Wang Signed-off-by: changzhu Signed-off-by: Prike Liang Reviewed-by: Junwei Zhang Reviewed-by: Tianci Yin Reviewed-by: Xiaojie Yuan --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 8ca4f3cba1457..e147eaa68e72d 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -127,6 +127,7 @@ LINUXINCLUDE := \ -include $(src)/include/rename_symbol.h \ $(LINUXINCLUDE) +export CONFIG_HSA_AMD=y export CONFIG_DRM_TTM=m export CONFIG_DRM_AMDGPU=m export CONFIG_DRM_SCHED=m @@ -136,6 +137,7 @@ export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y export CONFIG_DRM_AMD_DC_DCN1_0=y +subdir-ccflags-y += -DCONFIG_HSA_AMD subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR From 98ff16777b2a54b94a7994d6deea5176e9e38f3c Mon Sep 17 00:00:00 2001 From: Huang Rui Date: Fri, 26 Jan 2018 10:27:17 +0800 Subject: [PATCH 0100/2653] drm/amdkcl: enable dcn2_x support in dkms Reviewed-by: Hawking Zhang Signed-off-by: Jack Xiao Signed-off-by: chen gong Reviewed-by: Roman Li Reviewed-by: changzhu Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index e147eaa68e72d..20c23f2ebf2fb 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -136,6 +136,7 @@ export CONFIG_DRM_AMDGPU_SI=y export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y export CONFIG_DRM_AMD_DC_DCN1_0=y +export CONFIG_DRM_AMD_DC_DCN2_x=y subdir-ccflags-y += -DCONFIG_HSA_AMD subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK @@ -143,5 +144,6 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN2_x obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ From f45bd8317b93a817ebb76932e228a9ee11edbaa6 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 5 Jun 2020 13:50:05 +0800 Subject: [PATCH 0101/2653] drm/amdkcl: enable dcn3_x in dkms package Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 20c23f2ebf2fb..4ed76a92cf2b1 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -137,6 +137,7 @@ export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y export CONFIG_DRM_AMD_DC_DCN1_0=y export CONFIG_DRM_AMD_DC_DCN2_x=y +export CONFIG_DRM_AMD_DC_DCN3_x=y subdir-ccflags-y += -DCONFIG_HSA_AMD subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK @@ -145,5 +146,6 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN2_x +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN3_x obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ From 6d99a21d455a44ff20728c0a9f44894e92667b81 Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Thu, 30 Jul 2020 09:18:22 -0400 Subject: [PATCH 0102/2653] drm/amd/dkms: Guard DCN2/3 with regard to core2 These won't work with core2, so we can guard it for now until code consolidation takes place. This avoids a hack in packaging, and also makes transitioning to removing the DCN guards easier in the future Signed-off-by: Kent Russell Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 4ed76a92cf2b1..ce753462ac58c 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -136,8 +136,6 @@ export CONFIG_DRM_AMDGPU_SI=y export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y export CONFIG_DRM_AMD_DC_DCN1_0=y -export CONFIG_DRM_AMD_DC_DCN2_x=y -export CONFIG_DRM_AMD_DC_DCN3_x=y subdir-ccflags-y += -DCONFIG_HSA_AMD subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK @@ -145,7 +143,17 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 + + +# Trying to enable DCN2/3 with core2 optimizations will result in +# older versions of GCC hanging during building/installing. Check +# if the compiler is using core2 optimizations and only build DCN2/3 +# if core2 isn't in the compiler flags +ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) +export CONFIG_DRM_AMD_DC_DCN2_x=y +export CONFIG_DRM_AMD_DC_DCN3_x=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN2_x subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN3_x +endif obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ From ca6d9384b99796226ad32ad5ca135b8919d5e473 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 25 May 2018 16:51:17 -0400 Subject: [PATCH 0103/2653] drm/amdkcl/autoconf: Add initial autoconf framework to DKMS build Signed-off-by: Slava Grigorev Reviewed-by: Feifei Xu Change-Id: I6c9a8dd9e6eb51f40ef4c448038654c09372f200 --- drivers/gpu/drm/amd/dkms/Makefile | 2 + drivers/gpu/drm/amd/dkms/autogen.sh | 4 + drivers/gpu/drm/amd/dkms/config/install-sh | 508 +++++++++++++++++++++ drivers/gpu/drm/amd/dkms/configure.ac | 7 + drivers/gpu/drm/amd/dkms/pre-build.sh | 3 + 5 files changed, 524 insertions(+) create mode 100755 drivers/gpu/drm/amd/dkms/autogen.sh create mode 100755 drivers/gpu/drm/amd/dkms/config/install-sh create mode 100644 drivers/gpu/drm/amd/dkms/configure.ac diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index ce753462ac58c..d628e1b4340ad 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -120,6 +120,8 @@ endif export OS_NAME OS_VERSION +subdir-ccflags-y += -include $(src)/config/config.h + LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/uapi \ diff --git a/drivers/gpu/drm/amd/dkms/autogen.sh b/drivers/gpu/drm/amd/dkms/autogen.sh new file mode 100755 index 0000000000000..992eac90a5a18 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/autogen.sh @@ -0,0 +1,4 @@ +#!/bin/bash + +autoreconf -fiv +rm -Rf autom4te.cache diff --git a/drivers/gpu/drm/amd/dkms/config/install-sh b/drivers/gpu/drm/amd/dkms/config/install-sh new file mode 100755 index 0000000000000..59990a1049267 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/config/install-sh @@ -0,0 +1,508 @@ +#!/bin/sh +# install - install a program, script, or datafile + +scriptversion=2014-09-12.12; # UTC + +# This originates from X11R5 (mit/util/scripts/install.sh), which was +# later released in X11R6 (xc/config/util/install.sh) with the +# following copyright and license. +# +# Copyright (C) 1994 X Consortium +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to +# deal in the Software without restriction, including without limitation the +# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +# sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +# AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNEC- +# TION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# +# Except as contained in this notice, the name of the X Consortium shall not +# be used in advertising or otherwise to promote the sale, use or other deal- +# ings in this Software without prior written authorization from the X Consor- +# tium. +# +# +# FSF changes to this file are in the public domain. +# +# Calling this script install-sh is preferred over install.sh, to prevent +# 'make' implicit rules from creating a file called install from it +# when there is no Makefile. +# +# This script is compatible with the BSD install script, but was written +# from scratch. + +tab=' ' +nl=' +' +IFS=" $tab$nl" + +# Set DOITPROG to "echo" to test this script. + +doit=${DOITPROG-} +doit_exec=${doit:-exec} + +# Put in absolute file names if you don't have them in your path; +# or use environment vars. + +chgrpprog=${CHGRPPROG-chgrp} +chmodprog=${CHMODPROG-chmod} +chownprog=${CHOWNPROG-chown} +cmpprog=${CMPPROG-cmp} +cpprog=${CPPROG-cp} +mkdirprog=${MKDIRPROG-mkdir} +mvprog=${MVPROG-mv} +rmprog=${RMPROG-rm} +stripprog=${STRIPPROG-strip} + +posix_mkdir= + +# Desired mode of installed file. +mode=0755 + +chgrpcmd= +chmodcmd=$chmodprog +chowncmd= +mvcmd=$mvprog +rmcmd="$rmprog -f" +stripcmd= + +src= +dst= +dir_arg= +dst_arg= + +copy_on_change=false +is_target_a_directory=possibly + +usage="\ +Usage: $0 [OPTION]... [-T] SRCFILE DSTFILE + or: $0 [OPTION]... SRCFILES... DIRECTORY + or: $0 [OPTION]... -t DIRECTORY SRCFILES... + or: $0 [OPTION]... -d DIRECTORIES... + +In the 1st form, copy SRCFILE to DSTFILE. +In the 2nd and 3rd, copy all SRCFILES to DIRECTORY. +In the 4th, create DIRECTORIES. + +Options: + --help display this help and exit. + --version display version info and exit. + + -c (ignored) + -C install only if different (preserve the last data modification time) + -d create directories instead of installing files. + -g GROUP $chgrpprog installed files to GROUP. + -m MODE $chmodprog installed files to MODE. + -o USER $chownprog installed files to USER. + -s $stripprog installed files. + -t DIRECTORY install into DIRECTORY. + -T report an error if DSTFILE is a directory. + +Environment variables override the default commands: + CHGRPPROG CHMODPROG CHOWNPROG CMPPROG CPPROG MKDIRPROG MVPROG + RMPROG STRIPPROG +" + +while test $# -ne 0; do + case $1 in + -c) ;; + + -C) copy_on_change=true;; + + -d) dir_arg=true;; + + -g) chgrpcmd="$chgrpprog $2" + shift;; + + --help) echo "$usage"; exit $?;; + + -m) mode=$2 + case $mode in + *' '* | *"$tab"* | *"$nl"* | *'*'* | *'?'* | *'['*) + echo "$0: invalid mode: $mode" >&2 + exit 1;; + esac + shift;; + + -o) chowncmd="$chownprog $2" + shift;; + + -s) stripcmd=$stripprog;; + + -t) + is_target_a_directory=always + dst_arg=$2 + # Protect names problematic for 'test' and other utilities. + case $dst_arg in + -* | [=\(\)!]) dst_arg=./$dst_arg;; + esac + shift;; + + -T) is_target_a_directory=never;; + + --version) echo "$0 $scriptversion"; exit $?;; + + --) shift + break;; + + -*) echo "$0: invalid option: $1" >&2 + exit 1;; + + *) break;; + esac + shift +done + +# We allow the use of options -d and -T together, by making -d +# take the precedence; this is for compatibility with GNU install. + +if test -n "$dir_arg"; then + if test -n "$dst_arg"; then + echo "$0: target directory not allowed when installing a directory." >&2 + exit 1 + fi +fi + +if test $# -ne 0 && test -z "$dir_arg$dst_arg"; then + # When -d is used, all remaining arguments are directories to create. + # When -t is used, the destination is already specified. + # Otherwise, the last argument is the destination. Remove it from $@. + for arg + do + if test -n "$dst_arg"; then + # $@ is not empty: it contains at least $arg. + set fnord "$@" "$dst_arg" + shift # fnord + fi + shift # arg + dst_arg=$arg + # Protect names problematic for 'test' and other utilities. + case $dst_arg in + -* | [=\(\)!]) dst_arg=./$dst_arg;; + esac + done +fi + +if test $# -eq 0; then + if test -z "$dir_arg"; then + echo "$0: no input file specified." >&2 + exit 1 + fi + # It's OK to call 'install-sh -d' without argument. + # This can happen when creating conditional directories. + exit 0 +fi + +if test -z "$dir_arg"; then + if test $# -gt 1 || test "$is_target_a_directory" = always; then + if test ! -d "$dst_arg"; then + echo "$0: $dst_arg: Is not a directory." >&2 + exit 1 + fi + fi +fi + +if test -z "$dir_arg"; then + do_exit='(exit $ret); exit $ret' + trap "ret=129; $do_exit" 1 + trap "ret=130; $do_exit" 2 + trap "ret=141; $do_exit" 13 + trap "ret=143; $do_exit" 15 + + # Set umask so as not to create temps with too-generous modes. + # However, 'strip' requires both read and write access to temps. + case $mode in + # Optimize common cases. + *644) cp_umask=133;; + *755) cp_umask=22;; + + *[0-7]) + if test -z "$stripcmd"; then + u_plus_rw= + else + u_plus_rw='% 200' + fi + cp_umask=`expr '(' 777 - $mode % 1000 ')' $u_plus_rw`;; + *) + if test -z "$stripcmd"; then + u_plus_rw= + else + u_plus_rw=,u+rw + fi + cp_umask=$mode$u_plus_rw;; + esac +fi + +for src +do + # Protect names problematic for 'test' and other utilities. + case $src in + -* | [=\(\)!]) src=./$src;; + esac + + if test -n "$dir_arg"; then + dst=$src + dstdir=$dst + test -d "$dstdir" + dstdir_status=$? + else + + # Waiting for this to be detected by the "$cpprog $src $dsttmp" command + # might cause directories to be created, which would be especially bad + # if $src (and thus $dsttmp) contains '*'. + if test ! -f "$src" && test ! -d "$src"; then + echo "$0: $src does not exist." >&2 + exit 1 + fi + + if test -z "$dst_arg"; then + echo "$0: no destination specified." >&2 + exit 1 + fi + dst=$dst_arg + + # If destination is a directory, append the input filename; won't work + # if double slashes aren't ignored. + if test -d "$dst"; then + if test "$is_target_a_directory" = never; then + echo "$0: $dst_arg: Is a directory" >&2 + exit 1 + fi + dstdir=$dst + dst=$dstdir/`basename "$src"` + dstdir_status=0 + else + dstdir=`dirname "$dst"` + test -d "$dstdir" + dstdir_status=$? + fi + fi + + obsolete_mkdir_used=false + + if test $dstdir_status != 0; then + case $posix_mkdir in + '') + # Create intermediate dirs using mode 755 as modified by the umask. + # This is like FreeBSD 'install' as of 1997-10-28. + umask=`umask` + case $stripcmd.$umask in + # Optimize common cases. + *[2367][2367]) mkdir_umask=$umask;; + .*0[02][02] | .[02][02] | .[02]) mkdir_umask=22;; + + *[0-7]) + mkdir_umask=`expr $umask + 22 \ + - $umask % 100 % 40 + $umask % 20 \ + - $umask % 10 % 4 + $umask % 2 + `;; + *) mkdir_umask=$umask,go-w;; + esac + + # With -d, create the new directory with the user-specified mode. + # Otherwise, rely on $mkdir_umask. + if test -n "$dir_arg"; then + mkdir_mode=-m$mode + else + mkdir_mode= + fi + + posix_mkdir=false + case $umask in + *[123567][0-7][0-7]) + # POSIX mkdir -p sets u+wx bits regardless of umask, which + # is incompatible with FreeBSD 'install' when (umask & 300) != 0. + ;; + *) + # $RANDOM is not portable (e.g. dash); use it when possible to + # lower collision chance + tmpdir=${TMPDIR-/tmp}/ins$RANDOM-$$ + trap 'ret=$?; rmdir "$tmpdir/a/b" "$tmpdir/a" "$tmpdir" 2>/dev/null; exit $ret' 0 + + # As "mkdir -p" follows symlinks and we work in /tmp possibly; so + # create the $tmpdir first (and fail if unsuccessful) to make sure + # that nobody tries to guess the $tmpdir name. + if (umask $mkdir_umask && + $mkdirprog $mkdir_mode "$tmpdir" && + exec $mkdirprog $mkdir_mode -p -- "$tmpdir/a/b") >/dev/null 2>&1 + then + if test -z "$dir_arg" || { + # Check for POSIX incompatibilities with -m. + # HP-UX 11.23 and IRIX 6.5 mkdir -m -p sets group- or + # other-writable bit of parent directory when it shouldn't. + # FreeBSD 6.1 mkdir -m -p sets mode of existing directory. + test_tmpdir="$tmpdir/a" + ls_ld_tmpdir=`ls -ld "$test_tmpdir"` + case $ls_ld_tmpdir in + d????-?r-*) different_mode=700;; + d????-?--*) different_mode=755;; + *) false;; + esac && + $mkdirprog -m$different_mode -p -- "$test_tmpdir" && { + ls_ld_tmpdir_1=`ls -ld "$test_tmpdir"` + test "$ls_ld_tmpdir" = "$ls_ld_tmpdir_1" + } + } + then posix_mkdir=: + fi + rmdir "$tmpdir/a/b" "$tmpdir/a" "$tmpdir" + else + # Remove any dirs left behind by ancient mkdir implementations. + rmdir ./$mkdir_mode ./-p ./-- "$tmpdir" 2>/dev/null + fi + trap '' 0;; + esac;; + esac + + if + $posix_mkdir && ( + umask $mkdir_umask && + $doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir" + ) + then : + else + + # The umask is ridiculous, or mkdir does not conform to POSIX, + # or it failed possibly due to a race condition. Create the + # directory the slow way, step by step, checking for races as we go. + + case $dstdir in + /*) prefix='/';; + [-=\(\)!]*) prefix='./';; + *) prefix='';; + esac + + oIFS=$IFS + IFS=/ + set -f + set fnord $dstdir + shift + set +f + IFS=$oIFS + + prefixes= + + for d + do + test X"$d" = X && continue + + prefix=$prefix$d + if test -d "$prefix"; then + prefixes= + else + if $posix_mkdir; then + (umask=$mkdir_umask && + $doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir") && break + # Don't fail if two instances are running concurrently. + test -d "$prefix" || exit 1 + else + case $prefix in + *\'*) qprefix=`echo "$prefix" | sed "s/'/'\\\\\\\\''/g"`;; + *) qprefix=$prefix;; + esac + prefixes="$prefixes '$qprefix'" + fi + fi + prefix=$prefix/ + done + + if test -n "$prefixes"; then + # Don't fail if two instances are running concurrently. + (umask $mkdir_umask && + eval "\$doit_exec \$mkdirprog $prefixes") || + test -d "$dstdir" || exit 1 + obsolete_mkdir_used=true + fi + fi + fi + + if test -n "$dir_arg"; then + { test -z "$chowncmd" || $doit $chowncmd "$dst"; } && + { test -z "$chgrpcmd" || $doit $chgrpcmd "$dst"; } && + { test "$obsolete_mkdir_used$chowncmd$chgrpcmd" = false || + test -z "$chmodcmd" || $doit $chmodcmd $mode "$dst"; } || exit 1 + else + + # Make a couple of temp file names in the proper directory. + dsttmp=$dstdir/_inst.$$_ + rmtmp=$dstdir/_rm.$$_ + + # Trap to clean up those temp files at exit. + trap 'ret=$?; rm -f "$dsttmp" "$rmtmp" && exit $ret' 0 + + # Copy the file name to the temp name. + (umask $cp_umask && $doit_exec $cpprog "$src" "$dsttmp") && + + # and set any options; do chmod last to preserve setuid bits. + # + # If any of these fail, we abort the whole thing. If we want to + # ignore errors from any of these, just make sure not to ignore + # errors from the above "$doit $cpprog $src $dsttmp" command. + # + { test -z "$chowncmd" || $doit $chowncmd "$dsttmp"; } && + { test -z "$chgrpcmd" || $doit $chgrpcmd "$dsttmp"; } && + { test -z "$stripcmd" || $doit $stripcmd "$dsttmp"; } && + { test -z "$chmodcmd" || $doit $chmodcmd $mode "$dsttmp"; } && + + # If -C, don't bother to copy if it wouldn't change the file. + if $copy_on_change && + old=`LC_ALL=C ls -dlL "$dst" 2>/dev/null` && + new=`LC_ALL=C ls -dlL "$dsttmp" 2>/dev/null` && + set -f && + set X $old && old=:$2:$4:$5:$6 && + set X $new && new=:$2:$4:$5:$6 && + set +f && + test "$old" = "$new" && + $cmpprog "$dst" "$dsttmp" >/dev/null 2>&1 + then + rm -f "$dsttmp" + else + # Rename the file to the real destination. + $doit $mvcmd -f "$dsttmp" "$dst" 2>/dev/null || + + # The rename failed, perhaps because mv can't rename something else + # to itself, or perhaps because mv is so ancient that it does not + # support -f. + { + # Now remove or move aside any old file at destination location. + # We try this two ways since rm can't unlink itself on some + # systems and the destination file might be busy for other + # reasons. In this case, the final cleanup might fail but the new + # file should still install successfully. + { + test ! -f "$dst" || + $doit $rmcmd -f "$dst" 2>/dev/null || + { $doit $mvcmd -f "$dst" "$rmtmp" 2>/dev/null && + { $doit $rmcmd -f "$rmtmp" 2>/dev/null; :; } + } || + { echo "$0: cannot unlink or rename $dst" >&2 + (exit 1); exit 1 + } + } && + + # Now rename the file to the real destination. + $doit $mvcmd "$dsttmp" "$dst" + } + fi || exit 1 + + trap '' 0 + fi +done + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "scriptversion=" +# time-stamp-format: "%:y-%02m-%02d.%02H" +# time-stamp-time-zone: "UTC" +# time-stamp-end: "; # UTC" +# End: diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac new file mode 100644 index 0000000000000..385dda9ac3bfc --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -0,0 +1,7 @@ +AC_INIT(amdgpu-dkms, 19.40) +AC_LANG(C) +AC_CONFIG_AUX_DIR([config]) +AC_CONFIG_HEADERS([config/config.h]) +AC_PROG_INSTALL +AC_PROG_CC +AC_OUTPUT diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 9fb471b43a708..070b72aedb1ab 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -56,3 +56,6 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do done sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile done + +./autogen.sh +./configure From 2bdc1ffa30be70bc9dc230b8cd958eb5b54ca89b Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 1 Apr 2020 17:55:00 -0400 Subject: [PATCH 0104/2653] drm/amdkcl/autoconf: make autogen.sh script return status on exit Change-Id: I3248f3f121f28ac821802b25ccc0b2faca075ee7 Signed-off-by: Slava Grigorev Reviewed-by: Jeremy Newton --- drivers/gpu/drm/amd/dkms/autogen.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/autogen.sh b/drivers/gpu/drm/amd/dkms/autogen.sh index 992eac90a5a18..d72f86b5a2f97 100755 --- a/drivers/gpu/drm/amd/dkms/autogen.sh +++ b/drivers/gpu/drm/amd/dkms/autogen.sh @@ -1,4 +1,5 @@ #!/bin/bash autoreconf -fiv +[[ $? -eq 0 ]] || exit $? rm -Rf autom4te.cache From 9f342fd7909368490679c6b88910ae3904697a1e Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 12 Feb 2020 09:56:54 -0500 Subject: [PATCH 0105/2653] drm/amdkcl/autoconf: use AC_CONFIG_MACRO_DIR macro to include m4 files Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/configure.ac | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 385dda9ac3bfc..ed144e0a2a235 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -4,4 +4,6 @@ AC_CONFIG_AUX_DIR([config]) AC_CONFIG_HEADERS([config/config.h]) AC_PROG_INSTALL AC_PROG_CC +AC_CONFIG_MACRO_DIR([m4]) + AC_OUTPUT From 9a926001c0d66852c8483544912be1718e67e7da Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 29 May 2018 12:46:20 -0400 Subject: [PATCH 0106/2653] drm/amdkcl/autoconf: Add AC_KERNEL_TRY_COMPILE macro Signed-off-by: Slava Grigorev Reviewed-by: Feifei Xu --- drivers/gpu/drm/amd/dkms/configure.ac | 3 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 212 ++++++++++++++++++++++++++ 2 files changed, 215 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/kernel.m4 diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index ed144e0a2a235..20954e53b8326 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,5 @@ AC_INIT(amdgpu-dkms, 19.40) + AC_LANG(C) AC_CONFIG_AUX_DIR([config]) AC_CONFIG_HEADERS([config/config.h]) @@ -6,4 +7,6 @@ AC_PROG_INSTALL AC_PROG_CC AC_CONFIG_MACRO_DIR([m4]) +AC_CONFIG_KERNEL + AC_OUTPUT diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 new file mode 100644 index 0000000000000..50fe3cba42270 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -0,0 +1,212 @@ +dnl # +dnl # Default kernel configuration +dnl # +AC_DEFUN([AC_CONFIG_KERNEL], [ + AC_KERNEL + + AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ + KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" + ]) + + AC_SUBST(KERNEL_MAKE) +]) + +dnl # +dnl # Detect name used for Module.symvers file in kernel +dnl # +AC_DEFUN([AC_MODULE_SYMVERS], [ + modpost=$LINUX/scripts/Makefile.modpost + AC_MSG_CHECKING([kernel file name for module symbols]) + AS_IF([test "x$enable_linux_builtin" != xyes -a -f "$modpost"], [ + AS_IF([grep -q Modules.symvers $modpost], [ + LINUX_SYMBOLS=Modules.symvers + ], [ + LINUX_SYMBOLS=Module.symvers + ]) + + AS_IF([test ! -f "$LINUX_OBJ/$LINUX_SYMBOLS"], [ + AC_MSG_ERROR([ + *** Please make sure the kernel devel package for your distribution + *** is installed. If you are building with a custom kernel, make sure the + *** kernel is configured, built, and the '--with-linux=PATH' configure + *** option refers to the location of the kernel source.]) + ]) + ], [ + LINUX_SYMBOLS=NONE + ]) + AC_MSG_RESULT($LINUX_SYMBOLS) + AC_SUBST(LINUX_SYMBOLS) +]) + +dnl # +dnl # Detect the kernel to be built against +dnl # +AC_DEFUN([AC_KERNEL], [ + AC_ARG_WITH([linux], + AS_HELP_STRING([--with-linux=PATH], + [Path to kernel source]), + [kernelsrc="$withval"]) + + AC_ARG_WITH(linux-obj, + AS_HELP_STRING([--with-linux-obj=PATH], + [Path to kernel build objects]), + [kernelbuild="$withval"]) + + AC_MSG_CHECKING([kernel source directory]) + AS_IF([test -z "$kernelsrc"], [ + AS_IF([test -e "/lib/modules/$(uname -r)/source"], [ + headersdir="/lib/modules/$(uname -r)/source" + sourcelink=$(readlink -f "$headersdir") + ], [test -e "/lib/modules/$(uname -r)/build"], [ + headersdir="/lib/modules/$(uname -r)/build" + sourcelink=$(readlink -f "$headersdir") + ], [ + sourcelink=$(ls -1d /usr/src/kernels/* \ + /usr/src/linux-* \ + 2>/dev/null | grep -v obj | tail -1) + ]) + + AS_IF([test -n "$sourcelink" && test -e ${sourcelink}], [ + kernelsrc=`readlink -f ${sourcelink}` + ], [ + kernelsrc="[Not found]" + ]) + ], [ + AS_IF([test "$kernelsrc" = "NONE"], [ + kernsrcver=NONE + ]) + withlinux=yes + ]) + + AC_MSG_RESULT([$kernelsrc]) + AS_IF([test ! -d "$kernelsrc"], [ + AC_MSG_ERROR([ + *** Please make sure the kernel devel package for your distribution + *** is installed and then try again. If that fails, you can specify the + *** location of the kernel source with the '--with-linux=PATH' option.]) + ]) + + AC_MSG_CHECKING([kernel build directory]) + AS_IF([test -z "$kernelbuild"], [ + AS_IF([test x$withlinux != xyes -a -e "/lib/modules/$(uname -r)/build"], [ + kernelbuild=`readlink -f /lib/modules/$(uname -r)/build` + ], [test -d ${kernelsrc}-obj/${target_cpu}/${target_cpu}], [ + kernelbuild=${kernelsrc}-obj/${target_cpu}/${target_cpu} + ], [test -d ${kernelsrc}-obj/${target_cpu}/default], [ + kernelbuild=${kernelsrc}-obj/${target_cpu}/default + ], [test -d `dirname ${kernelsrc}`/build-${target_cpu}], [ + kernelbuild=`dirname ${kernelsrc}`/build-${target_cpu} + ], [ + kernelbuild=${kernelsrc} + ]) + ]) + AC_MSG_RESULT([$kernelbuild]) + + AC_MSG_CHECKING([kernel source version]) + utsrelease1=$kernelbuild/include/linux/version.h + utsrelease2=$kernelbuild/include/linux/utsrelease.h + utsrelease3=$kernelbuild/include/generated/utsrelease.h + AS_IF([test -r $utsrelease1 && fgrep -q UTS_RELEASE $utsrelease1], [ + utsrelease=linux/version.h + ], [test -r $utsrelease2 && fgrep -q UTS_RELEASE $utsrelease2], [ + utsrelease=linux/utsrelease.h + ], [test -r $utsrelease3 && fgrep -q UTS_RELEASE $utsrelease3], [ + utsrelease=generated/utsrelease.h + ]) + + AS_IF([test "$utsrelease"], [ + kernsrcver=`(echo "#include <$utsrelease>"; + echo "kernsrcver=UTS_RELEASE") | + cpp -I $kernelbuild/include | + grep "^kernsrcver=" | cut -d \" -f 2` + + AS_IF([test -z "$kernsrcver"], [ + AC_MSG_RESULT([Not found]) + AC_MSG_ERROR([*** Cannot determine kernel version.]) + ]) + ], [ + AC_MSG_RESULT([Not found]) + if test "x$enable_linux_builtin" != xyes; then + AC_MSG_ERROR([*** Cannot find UTS_RELEASE definition.]) + else + AC_MSG_ERROR([ + *** Cannot find UTS_RELEASE definition. + *** Please run 'make prepare' inside the kernel source tree.]) + fi + ]) + + AC_MSG_RESULT([$kernsrcver]) + + LINUX=${kernelsrc} + LINUX_OBJ=${kernelbuild} + LINUX_VERSION=${kernsrcver} + + AC_SUBST(LINUX) + AC_SUBST(LINUX_OBJ) + AC_SUBST(LINUX_VERSION) + + AC_MODULE_SYMVERS +]) + +dnl # +dnl # AC_KERNEL_CONFTEST_H +dnl # +AC_DEFUN([AC_KERNEL_CONFTEST_H], [ +cat - <<_ACEOF >conftest.h +$1 +_ACEOF +]) + +dnl # +dnl # AC_KERNEL_CONFTEST_C +dnl # +AC_DEFUN([AC_KERNEL_CONFTEST_C], [ +cat confdefs.h - <<_ACEOF >conftest.c +$1 +_ACEOF +]) + +dnl # +dnl # AC_KERNEL_LANG_PROGRAM(C)([PROLOGUE], [BODY]) +dnl # +AC_DEFUN([AC_KERNEL_LANG_PROGRAM], [ +$1 +int +main (void) +{ +dnl Do *not* indent the following line: there may be CPP directives. +dnl Don't move the `;' right after for the same reason. +$2 + ; + return 0; +} +]) + +dnl # +dnl # AC_KERNEL_COMPILE_IFELSE / like AC_COMPILE_IFELSE +dnl # +AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ + m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) + m4_ifvaln([$6], [AC_KERNEL_CONFTEST_H([$6])], [AC_KERNEL_CONFTEST_H([])]) + rm -Rf build && mkdir -p build && touch build/conftest.mod.c + echo "obj-m := conftest.o" >build/Makefile + modpost_flag='' + test "x$enable_linux_builtin" = xyes && modpost_flag='modpost=true' # fake modpost stage + AS_IF( + [AC_TRY_COMMAND(cp conftest.c conftest.h build && make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror" M=$PWD/build $modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], + [$4], + [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] + ) + rm -Rf build +]) + +dnl # +dnl # AC_KERNEL_TRY_COMPILE like AC_TRY_COMPILE +dnl # +AC_DEFUN([AC_KERNEL_TRY_COMPILE], + [AC_KERNEL_COMPILE_IFELSE( + [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], + [modules], + [test -s build/conftest.o], + [$3], [$4]) +]) From 6550030cf2010c698d2d9a0bca4b67f517ee71a6 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 1 Jun 2018 12:00:42 -0400 Subject: [PATCH 0107/2653] drm/amdkcl/autoconf: Add AC_AMDGPU_CONFIG macro with basic configuration it is a squash of: drm/amdkcl/autoconf: Add AC_AMDGPU_CONFIG macro with basic configuration Signed-off-by: Slava Grigorev Reviewed-by: Feifei Xu Signed-off-by: Yifan Zhang commit b979e488f77894bb89aee6424cd803f76f6d760d Author: Slava Grigorev Date: Wed Feb 12 09:56:54 2020 -0500 drm/amdkcl: use AC_CONFIG_MACRO_DIR macro to include m4 files Change-Id: I01581d410f6c45d41c40852ed44a0e451bbe8622 Signed-off-by: Slava Grigorev Change-Id: If3a07ed5064cc5cdddeb0abd0ce562be582d32ad --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- drivers/gpu/drm/amd/dkms/m4/config.m4 | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/config.m4 diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 20954e53b8326..b367e452d4cbb 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -7,6 +7,6 @@ AC_PROG_INSTALL AC_PROG_CC AC_CONFIG_MACRO_DIR([m4]) -AC_CONFIG_KERNEL +AC_AMDGPU_CONFIG AC_OUTPUT diff --git a/drivers/gpu/drm/amd/dkms/m4/config.m4 b/drivers/gpu/drm/amd/dkms/m4/config.m4 new file mode 100644 index 0000000000000..e22a4a49a5233 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/config.m4 @@ -0,0 +1,9 @@ +AC_DEFUN([AC_AMDGPU_CONFIG], [ + AC_ARG_ENABLE([linux-builtin], + [AC_HELP_STRING([--enable-linux-builtin], + [Configure for builtin kernel modules @<:@default=no@:>@])], + [], + [enable_linux_builtin=no]) + + AC_CONFIG_KERNEL +]) From bc17b82d962db90bb0929ff66c023b515609a25a Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Mon, 3 Jun 2019 13:32:52 +0800 Subject: [PATCH 0108/2653] drm/amdkcl/autoconf: Add AC_KERNEL_TRY_COMPILE_SYMBOL macro v2: Correct AC_KERNEL_CHECK_SYMBOL_EXPORT macro to handle multiple symbols v3: Make 'AC_KERNEL_CHECK_SYMBOL_EXPORT' applicable to mawk Signed-off-by: Slava Grigorev Signed-off-by: chen gong Reviewed-by: Feifei Xu --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 73 +++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 50fe3cba42270..05612f1db34fa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -210,3 +210,76 @@ AC_DEFUN([AC_KERNEL_TRY_COMPILE], [test -s build/conftest.o], [$3], [$4]) ]) + +dnl # +dnl # AC_KERNEL_CHECK_SYMBOL_EXPORT +dnl # check symbol exported or not +dnl # +AC_DEFUN([AC_KERNEL_CHECK_SYMBOL_EXPORT], [ + awk -v s="$1" ' + BEGIN { + n = 0; + num = split(s, symbols, " ") + } { + for (i in symbols) + if (symbols[[i]] == $[2]) + n++ + } END { + if (num == n) + exit 0; + else + exit 1 + }' $LINUX_OBJ/$LINUX_SYMBOLS 2>/dev/null + rc=$? + if test $rc -ne 0; then + n=0 + export=0 + for file in $2; do + n=$(awk -v s="$1" ' + BEGIN { + n = 0; + split(s, symbols, " ") + } { + for (i in symbols) { + s="EXPORT_SYMBOL.*"symbols[[i]]; + if ($[0] ~ s) + n++ + } + } END { + print n + }' $LINUX/$file 2>/dev/null) + rc=$? + if test $rc -eq 0; then + (( export+=n )) + fi + done + if test $(wc -w <<< "$1") -eq $export; then : + $3 + else : + $4 + fi + else : + $3 + fi +]) + +dnl # +dnl # AC_KERNEL_TRY_COMPILE_SYMBOL +dnl # like AC_KERNEL_TRY_COMPILE, except AC_KERNEL_CHECK_SYMBOL_EXPORT +dnl # is called if not compiling for builtin +dnl # +AC_DEFUN([AC_KERNEL_TRY_COMPILE_SYMBOL], [ + AC_KERNEL_TRY_COMPILE([$1], [$2], [rc=0], [rc=1]) + if test $rc -ne 0; then : + $6 + else + if test "x$enable_linux_builtin" != xyes; then + AC_KERNEL_CHECK_SYMBOL_EXPORT([$3], [$4], [rc=0], [rc=1]) + fi + if test $rc -ne 0; then : + $6 + else : + $5 + fi + fi +]) From e8b5e986da18323fae8cbb21fbc7bdf736a572d5 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 5 Jul 2019 15:26:46 -0400 Subject: [PATCH 0109/2653] drm/amdkcl/autoconf: Drop autogen.sh call Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/pre-build.sh | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 070b72aedb1ab..87b972dc63e5e 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -57,5 +57,4 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile done -./autogen.sh ./configure From 70cf9669726a2773c56861b375bfd778420acadc Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 8 Aug 2019 09:45:06 +0800 Subject: [PATCH 0110/2653] drm/amdkcl/autoconf: fix in-tree check for exported symbols Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 05612f1db34fa..3f79152c41c8d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -17,14 +17,14 @@ dnl # AC_DEFUN([AC_MODULE_SYMVERS], [ modpost=$LINUX/scripts/Makefile.modpost AC_MSG_CHECKING([kernel file name for module symbols]) - AS_IF([test "x$enable_linux_builtin" != xyes -a -f "$modpost"], [ + AS_IF([test -f "$modpost"], [ AS_IF([grep -q Modules.symvers $modpost], [ LINUX_SYMBOLS=Modules.symvers ], [ LINUX_SYMBOLS=Module.symvers ]) - AS_IF([test ! -f "$LINUX_OBJ/$LINUX_SYMBOLS"], [ + AS_IF([test "x$enable_linux_builtin" != xyes -a ! -f "$LINUX_OBJ/$LINUX_SYMBOLS"], [ AC_MSG_ERROR([ *** Please make sure the kernel devel package for your distribution *** is installed. If you are building with a custom kernel, make sure the @@ -273,9 +273,7 @@ AC_DEFUN([AC_KERNEL_TRY_COMPILE_SYMBOL], [ if test $rc -ne 0; then : $6 else - if test "x$enable_linux_builtin" != xyes; then - AC_KERNEL_CHECK_SYMBOL_EXPORT([$3], [$4], [rc=0], [rc=1]) - fi + AC_KERNEL_CHECK_SYMBOL_EXPORT([$3], [$4], [rc=0], [rc=1]) if test $rc -ne 0; then : $6 else : From 83937be2d937750cc61972a0fee883e129a5ad86 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Thu, 8 Aug 2019 09:43:50 +0800 Subject: [PATCH 0111/2653] drm/amdkcl/autoconf: fix awk syntax error this could fix in-tree build error on ubuntu16.04.4 Signed-off-by: Adam Yang Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3f79152c41c8d..b2fb779404579 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -241,7 +241,7 @@ AC_DEFUN([AC_KERNEL_CHECK_SYMBOL_EXPORT], [ split(s, symbols, " ") } { for (i in symbols) { - s="EXPORT_SYMBOL.*"symbols[[i]]; + s="EXPORT_SYMBOL.*\\("symbols[[i]]"\\);" if ($[0] ~ s) n++ } From 55ecb9f5b738aff3bee76e618e61d446345dce87 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 25 Jul 2019 16:10:42 +0800 Subject: [PATCH 0112/2653] drm/amdkcl/autoconf: fix dkms build kernel version check the original behavior install dkms package with the current kernel, which is not expected. Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 12 ++++++------ drivers/gpu/drm/amd/dkms/pre-build.sh | 1 + 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b2fb779404579..fd06f6ee28951 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -54,11 +54,11 @@ AC_DEFUN([AC_KERNEL], [ AC_MSG_CHECKING([kernel source directory]) AS_IF([test -z "$kernelsrc"], [ - AS_IF([test -e "/lib/modules/$(uname -r)/source"], [ - headersdir="/lib/modules/$(uname -r)/source" + AS_IF([test -e "/lib/modules/$KERNELVER/source"], [ + headersdir="/lib/modules/$KERNELVER/source" sourcelink=$(readlink -f "$headersdir") - ], [test -e "/lib/modules/$(uname -r)/build"], [ - headersdir="/lib/modules/$(uname -r)/build" + ], [test -e "/lib/modules/$KERNELVER/build"], [ + headersdir="/lib/modules/$KERNELVER/build" sourcelink=$(readlink -f "$headersdir") ], [ sourcelink=$(ls -1d /usr/src/kernels/* \ @@ -88,8 +88,8 @@ AC_DEFUN([AC_KERNEL], [ AC_MSG_CHECKING([kernel build directory]) AS_IF([test -z "$kernelbuild"], [ - AS_IF([test x$withlinux != xyes -a -e "/lib/modules/$(uname -r)/build"], [ - kernelbuild=`readlink -f /lib/modules/$(uname -r)/build` + AS_IF([test x$withlinux != xyes -a -e "/lib/modules/$KERNELVER/build"], [ + kernelbuild=`readlink -f /lib/modules/$KERNELVER/build` ], [test -d ${kernelsrc}-obj/${target_cpu}/${target_cpu}], [ kernelbuild=${kernelsrc}-obj/${target_cpu}/${target_cpu} ], [test -d ${kernelsrc}-obj/${target_cpu}/default], [ diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 87b972dc63e5e..264b42dd2af4d 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -57,4 +57,5 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile done +export KERNELVER ./configure From 806cb570b4b76410c6eb39918527364232fe6eb9 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 30 Jul 2019 14:03:13 +0800 Subject: [PATCH 0113/2653] drm/amdkcl/autoconf: add documentation for autoconf macros Add documentation for AC_KERNEL_* macros. Signed-off-by: Flora Cui Reviewed-by: Feifei Xu --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fd06f6ee28951..ea4b86472c6e4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -150,6 +150,7 @@ AC_DEFUN([AC_KERNEL], [ dnl # dnl # AC_KERNEL_CONFTEST_H +dnl # $1: contents to be filled in conftest.h dnl # AC_DEFUN([AC_KERNEL_CONFTEST_H], [ cat - <<_ACEOF >conftest.h @@ -159,6 +160,8 @@ _ACEOF dnl # dnl # AC_KERNEL_CONFTEST_C +dnl # fill in contents of conftest.h and $1 to conftest.c +dnl # $1: contents to be filled in conftest.c dnl # AC_DEFUN([AC_KERNEL_CONFTEST_C], [ cat confdefs.h - <<_ACEOF >conftest.c @@ -167,7 +170,7 @@ _ACEOF ]) dnl # -dnl # AC_KERNEL_LANG_PROGRAM(C)([PROLOGUE], [BODY]) +dnl # AC_KERNEL_LANG_PROGRAM([PROLOGUE], [BODY]) dnl # AC_DEFUN([AC_KERNEL_LANG_PROGRAM], [ $1 @@ -184,6 +187,12 @@ $2 dnl # dnl # AC_KERNEL_COMPILE_IFELSE / like AC_COMPILE_IFELSE +dnl # $1: contents to be filled in conftest.c +dnl # $2: make target. "modules" for most case +dnl # $3: user defined commands. It "AND" the make command to check the result. If true, expands to $4. Otherwise $5. +dnl # $4: run it if make & $3 pass. +dnl # $5: run it if make & $3 fail. +dnl # $6: contents to be filled in conftest.h. Could be null. dnl # AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) @@ -202,6 +211,10 @@ AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ dnl # dnl # AC_KERNEL_TRY_COMPILE like AC_TRY_COMPILE +dnl # $1: Prologue for conftest.c. including header files, extends, etc +dnl # $2: Body for conftest.c. +dnl # $3: run it if compile pass. +dnl # $4: run it if compile fail. dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], [AC_KERNEL_COMPILE_IFELSE( @@ -214,6 +227,10 @@ AC_DEFUN([AC_KERNEL_TRY_COMPILE], dnl # dnl # AC_KERNEL_CHECK_SYMBOL_EXPORT dnl # check symbol exported or not +dnl # $1: symbol list to look for +dnl # $2: file list to look for $1 +dnl # $3: run it if pass. +dnl # $4: run it if fail. dnl # AC_DEFUN([AC_KERNEL_CHECK_SYMBOL_EXPORT], [ awk -v s="$1" ' @@ -267,6 +284,12 @@ dnl # dnl # AC_KERNEL_TRY_COMPILE_SYMBOL dnl # like AC_KERNEL_TRY_COMPILE, except AC_KERNEL_CHECK_SYMBOL_EXPORT dnl # is called if not compiling for builtin +dnl # $1: Prologue for conftest.c. including header files, extends, etc +dnl # $2: Body for conftest.c. +dnl # $3: AC_KERNEL_CHECK_SYMBOL_EXPORT $1 +dnl # $4: AC_KERNEL_CHECK_SYMBOL_EXPORT $2 +dnl # $5: run it if checking pass +dnl # $6: run it if checking fail dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE_SYMBOL], [ AC_KERNEL_TRY_COMPILE([$1], [$2], [rc=0], [rc=1]) From 71ef664a45cd3eaa719a2646b6ed838e61d5ae8e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 26 Jul 2019 11:28:47 +0800 Subject: [PATCH 0114/2653] drm/amdkcl/autoconf: add more flags to compile conftest v1: b1c3905f5703 drm/amdkcl/autoconf: make uninitialized warning not error v2: ab8d6b1a69d6 drm/amdkcl/autoconf: add more flags to compile conftest Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ea4b86472c6e4..d491a3d205ded 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -202,7 +202,7 @@ AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ modpost_flag='' test "x$enable_linux_builtin" = xyes && modpost_flag='modpost=true' # fake modpost stage AS_IF( - [AC_TRY_COMMAND(cp conftest.c conftest.h build && make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror" M=$PWD/build $modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], + [AC_TRY_COMMAND(cp conftest.c conftest.h build && make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=uninitialized -Wno-error=unused-variable" M=$PWD/build $modpost_flag $kbuild_src_flag) >/dev/null && AC_TRY_COMMAND([$3])], [$4], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] ) From 483f9a561ecf4546beeace6c27da3e5e2e5dd9fa Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 1 Aug 2019 17:27:15 +0800 Subject: [PATCH 0115/2653] drm/amdkcl/autoconf: add AC_KERNEL_TEST_HEADER_FILE_EXIST macro AC_KERNEL_TEST_HEADER_FILE_EXIST is added to detect whether the desired header file is available. It could save dkms install time. and could help to avoid errors that the depent header files missing in conftest.c due to kernel version changes. v1: 77102303c630 drm/amd/autoconf: add AC_KERNEL_TEST_HEADER_FILE_EXIST v2: ecb0feb54350 drm/amd/autoconf: fix test header exists error in SLED15.1 v3: bae172b63d85 drm/amd/autoconf: fix AC_KERNEL_TEST_HEADER_FILE_EXIST() Signed-off-by: Flora Cui Signed-off-by: Yifan Zhang Reviewed-by: Feifei Xu Reviewed-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d491a3d205ded..75cf807577c7c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -304,3 +304,21 @@ AC_DEFUN([AC_KERNEL_TRY_COMPILE_SYMBOL], [ fi fi ]) + +dnl # +dnl # AC_KERNEL_TEST_HEADER_FILE_EXIST +dnl # check header file exist +dnl # $1: header file to check +dnl # $2: run it if header file exist +dnl # $3: run it if header file nonexistent +dnl # +AC_DEFUN([AC_KERNEL_TEST_HEADER_FILE_EXIST], [ + header_file=m4_normalize([$1]) + header_file_obj=$LINUX_OBJ/include/$header_file + header_file_src=$LINUX/include/$header_file + AS_IF([test -e $header_file_obj -o -e $header_file_src], [ + $2 + ], [ + $3 + ]) +]) From c4787582a94c919d3dffcba1a48c781baa5192d3 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 10 Apr 2020 10:55:37 +0800 Subject: [PATCH 0116/2653] drm/amdkcl/autoconf: introduce parallel autoconf tests execution Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 69 +++++++++++++++++++++++---- 1 file changed, 60 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 75cf807577c7c..7f07aafc7cc59 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -4,6 +4,7 @@ dnl # AC_DEFUN([AC_CONFIG_KERNEL], [ AC_KERNEL + AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" ]) @@ -164,7 +165,7 @@ dnl # fill in contents of conftest.h and $1 to conftest.c dnl # $1: contents to be filled in conftest.c dnl # AC_DEFUN([AC_KERNEL_CONFTEST_C], [ -cat confdefs.h - <<_ACEOF >conftest.c +cat $ac_build_root_dir/confdefs.h - <<_ACEOF >conftest.c $1 _ACEOF ]) @@ -197,16 +198,34 @@ dnl # AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) m4_ifvaln([$6], [AC_KERNEL_CONFTEST_H([$6])], [AC_KERNEL_CONFTEST_H([])]) - rm -Rf build && mkdir -p build && touch build/conftest.mod.c - echo "obj-m := conftest.o" >build/Makefile - modpost_flag='' - test "x$enable_linux_builtin" = xyes && modpost_flag='modpost=true' # fake modpost stage + touch conftest.mod.c + echo "obj-m := conftest.o" >Makefile + kbuild_src_flag='' + kbuild_modpost_flag='KBUILD_MODPOST_NOFINAL=1 KBUILD_MODPOST_WARN=1' + kbuild_workaround_flag='' + test "x$enable_linux_builtin" = xyes && kbuild_src_flag='KBUILD_SRC=' # override KBUILD_SRC + test "x$enable_linux_builtin" = xyes && kbuild_workaround_flag='sub_make_done=' # override sub_make_done AS_IF( - [AC_TRY_COMMAND(cp conftest.c conftest.h build && make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=uninitialized -Wno-error=unused-variable" M=$PWD/build $modpost_flag $kbuild_src_flag) >/dev/null && AC_TRY_COMMAND([$3])], + [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=uninitialized -Wno-error=unused-variable" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], [$4], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] ) - rm -Rf build +]) + +dnl # +dnl # AC_KERNEL_TMP_BUILD_DIR +dnl # $1: contents to be executed in a temporary directory +dnl # +AC_DEFUN([AC_KERNEL_TMP_BUILD_DIR], [ + local build_dir=$(mktemp -d -t build-XXXXXXXX -p .) + pushd $build_dir >/dev/null + $1 + build_dir=$PWD + popd >/dev/null + AS_IF([test -s $build_dir/confdefs.h], [ + cat $build_dir/confdefs.h >>$ac_build_root_dir/confdefs.h + ]) + rm -rf $build_dir ]) dnl # @@ -217,11 +236,15 @@ dnl # $3: run it if compile pass. dnl # $4: run it if compile fail. dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], + target='modules' + test "x$enable_linux_builtin" = xyes && target='conftest.o' + [AC_KERNEL_TMP_BUILD_DIR( [AC_KERNEL_COMPILE_IFELSE( [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], - [modules], - [test -s build/conftest.o], + [$target], + [test -s conftest.o], [$3], [$4]) + ]) ]) dnl # @@ -322,3 +345,31 @@ AC_DEFUN([AC_KERNEL_TEST_HEADER_FILE_EXIST], [ $3 ]) ]) + +dnl # +dnl # AC_KERNEL_DO_BACKGROUND +dnl # $1: contents to be executed +dnl # +AC_DEFUN([AC_KERNEL_DO_BACKGROUND], [ + do_background() { + $1 + } + do_background & + procs+=( "$!" ) +]) + +dnl # +dnl # AC_KERNEL_WAIT +dnl # wait for all tests to be finished +dnl # +AC_DEFUN([AC_KERNEL_WAIT], [ + AC_MSG_CHECKING([for module configuration]) + wait ${procs[[@]]} + AS_IF([[[ $? -eq 0 ]]], [ + AC_MSG_RESULT([done]) + ], [ + AC_MSG_RESULT([failed]) + ]) +]) + +ac_build_root_dir=$PWD From 6ca01018795d9f0c00d42d7eac3323326c42babb Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 22 Jul 2020 10:39:05 +0800 Subject: [PATCH 0117/2653] drm/amdkcl/autoconf: drop compile target for conftest use the default one Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7f07aafc7cc59..7fd72165bb096 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -189,7 +189,7 @@ $2 dnl # dnl # AC_KERNEL_COMPILE_IFELSE / like AC_COMPILE_IFELSE dnl # $1: contents to be filled in conftest.c -dnl # $2: make target. "modules" for most case +dnl # $2: make target. dnl # $3: user defined commands. It "AND" the make command to check the result. If true, expands to $4. Otherwise $5. dnl # $4: run it if make & $3 pass. dnl # $5: run it if make & $3 fail. @@ -236,7 +236,7 @@ dnl # $3: run it if compile pass. dnl # $4: run it if compile fail. dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], - target='modules' + target='' test "x$enable_linux_builtin" = xyes && target='conftest.o' [AC_KERNEL_TMP_BUILD_DIR( [AC_KERNEL_COMPILE_IFELSE( From 2296319bc0746a94fac01c3d8c9a0b5ce6cfaf26 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 13 Feb 2020 12:43:57 -0500 Subject: [PATCH 0118/2653] drm/amdkcl/autoconf: properly define the root of the build directories Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7fd72165bb096..9f789fb192974 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -141,6 +141,7 @@ AC_DEFUN([AC_KERNEL], [ LINUX=${kernelsrc} LINUX_OBJ=${kernelbuild} LINUX_VERSION=${kernsrcver} + build_dir_root=$(cd "${0%/*}" && pwd) AC_SUBST(LINUX) AC_SUBST(LINUX_OBJ) @@ -165,7 +166,7 @@ dnl # fill in contents of conftest.h and $1 to conftest.c dnl # $1: contents to be filled in conftest.c dnl # AC_DEFUN([AC_KERNEL_CONFTEST_C], [ -cat $ac_build_root_dir/confdefs.h - <<_ACEOF >conftest.c +cat $build_dir_root/confdefs.h - <<_ACEOF >conftest.c $1 _ACEOF ]) @@ -223,7 +224,7 @@ AC_DEFUN([AC_KERNEL_TMP_BUILD_DIR], [ build_dir=$PWD popd >/dev/null AS_IF([test -s $build_dir/confdefs.h], [ - cat $build_dir/confdefs.h >>$ac_build_root_dir/confdefs.h + cat $build_dir/confdefs.h >>$build_dir_root/confdefs.h ]) rm -rf $build_dir ]) @@ -371,5 +372,3 @@ AC_DEFUN([AC_KERNEL_WAIT], [ AC_MSG_RESULT([failed]) ]) ]) - -ac_build_root_dir=$PWD From f66f0d17d1ab71d34e754b30dcca67a3929f5a75 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 14 Feb 2020 22:28:57 -0500 Subject: [PATCH 0119/2653] drm/amdkcl/autoconf: fix background function execution Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9f789fb192974..fc1ec9b67a109 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -239,13 +239,11 @@ dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], target='' test "x$enable_linux_builtin" = xyes && target='conftest.o' - [AC_KERNEL_TMP_BUILD_DIR( [AC_KERNEL_COMPILE_IFELSE( [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], [$target], [test -s conftest.o], [$3], [$4]) - ]) ]) dnl # @@ -353,7 +351,7 @@ dnl # $1: contents to be executed dnl # AC_DEFUN([AC_KERNEL_DO_BACKGROUND], [ do_background() { - $1 + AC_KERNEL_TMP_BUILD_DIR([$1]) } do_background & procs+=( "$!" ) From 7f26076c7ab0550686ef7ac9065049ac87d0a38b Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Mon, 2 Dec 2019 10:37:07 +0800 Subject: [PATCH 0120/2653] drm/amdkcl/autoconf: remove bash specific commands squash of 9b50ddbd026a drm/amdkcl/autoconf: remove bash specific commands 4d0397689a82 drm/amdkcl/autoconf: fix in-tree failure for v5.4 Signed-off-by: Slava Grigorev Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fc1ec9b67a109..ed40d9a3728a8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -218,14 +218,13 @@ dnl # AC_KERNEL_TMP_BUILD_DIR dnl # $1: contents to be executed in a temporary directory dnl # AC_DEFUN([AC_KERNEL_TMP_BUILD_DIR], [ - local build_dir=$(mktemp -d -t build-XXXXXXXX -p .) - pushd $build_dir >/dev/null + build_dir=$(mktemp -d -t build-XXXXXXXX -p $build_dir_root) + cd $build_dir $1 - build_dir=$PWD - popd >/dev/null - AS_IF([test -s $build_dir/confdefs.h], [ - cat $build_dir/confdefs.h >>$build_dir_root/confdefs.h + AS_IF([test -s confdefs.h], [ + cat confdefs.h >>$build_dir_root/confdefs.h ]) + cd $build_dir_root rm -rf $build_dir ]) @@ -289,10 +288,10 @@ AC_DEFUN([AC_KERNEL_CHECK_SYMBOL_EXPORT], [ }' $LINUX/$file 2>/dev/null) rc=$? if test $rc -eq 0; then - (( export+=n )) + export=$(( $export+$n )) fi done - if test $(wc -w <<< "$1") -eq $export; then : + if test $(echo "$1" | wc -w) -eq $export; then : $3 else : $4 @@ -354,7 +353,7 @@ AC_DEFUN([AC_KERNEL_DO_BACKGROUND], [ AC_KERNEL_TMP_BUILD_DIR([$1]) } do_background & - procs+=( "$!" ) + procs="$! $procs" ]) dnl # @@ -363,7 +362,7 @@ dnl # wait for all tests to be finished dnl # AC_DEFUN([AC_KERNEL_WAIT], [ AC_MSG_CHECKING([for module configuration]) - wait ${procs[[@]]} + wait $procs AS_IF([[[ $? -eq 0 ]]], [ AC_MSG_RESULT([done]) ], [ From 6117c24a2cde000fa17e9b047930a285b696f963 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 10 Apr 2020 11:10:41 +0800 Subject: [PATCH 0121/2653] drm/amdkcl/autoconf: add AC_KERNEL_CHECK_HEADERS macro The macro uses autoconf AC_CHECK_HEADER to find kernel header files by using the preprocessor Squash of c1b19bb1c3cd drm/amdkcl: fix SUSE DKMS build a67541030f43 drm/amdkcl/autoconf: add AC_KERNEL_CHECK_HEADERS macro Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 9 +++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 23 ++++++++++++++++++++++- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ed40d9a3728a8..0f35e04f1f51c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -344,6 +344,15 @@ AC_DEFUN([AC_KERNEL_TEST_HEADER_FILE_EXIST], [ ]) ]) +dnl # +dnl # AC_KERNEL_CHECK_HEADERS +dnl # check whether header file(s) is(are) present +dnl # $1: header filei(s) to check +dnl # +AC_DEFUN([AC_KERNEL_CHECK_HEADERS], [ + AC_CHECK_HEADERS([$1],[AS_TR_CPP([HAVE_$1])=1],,[-]) +]) + dnl # dnl # AC_KERNEL_DO_BACKGROUND dnl # $1: contents to be executed diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 264b42dd2af4d..7d1dca12d6f33 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -6,6 +6,21 @@ SRC="amd/dkms" KERNELVER=$1 KERNELVER_BASE=${KERNELVER%%-*} +SRCTREE=/lib/modules/$KERNELVER + +if [ -L $SRCTREE/source ]; then + BLDTREE="$SRCTREE/build" + SRCTREE="$SRCTREE/source" +else + SRCTREE="$SRCTREE/build" + BLDTREE="$SRCTREE" +fi + +SRCARCH=$(uname -m | sed -e "s/i.86/x86/" -e "s/x86_64/x86/" \ + -e "s/sun4u/sparc64/" -e "s/arm.*/arm/" -e "s/sa110/arm/" \ + -e "s/s390x/s390/" -e "s/parisc64/parisc/" \ + -e "s/ppc.*/powerpc/" -e "s/mips.*/mips/" \ + -e "s/sh[234].*/sh/" -e "s/aarch64.*/arm64/") version_lt () { newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) @@ -58,4 +73,10 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do done export KERNELVER -./configure +CPPFLAGS="-I$SRCTREE/arch/$SRCARCH/include \ + -I$BLDTREE/arch/$SRCARCH/include/generated \ + -I$SRCTREE/include \ + -I$BLDTREE/include \ + -I$SRCTREE/include/uapi \ + -include linux/kconfig.h" \ + ./configure From a9392cff17902089a59d29f5460c4c0faca16b7a Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 10 Mar 2020 13:49:38 -0400 Subject: [PATCH 0122/2653] drm/amdkcl/autoconf: add Makefile.config to DKMS code The Makefile helps developers to regenerate config.h file after changes made to either configure.ac or .m4 files Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/Makefile.config | 40 ++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/Makefile.config diff --git a/drivers/gpu/drm/amd/dkms/Makefile.config b/drivers/gpu/drm/amd/dkms/Makefile.config new file mode 100644 index 0000000000000..2b1a73c63bee3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.config @@ -0,0 +1,40 @@ +dkmstree := drivers/gpu/drm/amd/dkms +srctree := $(subst /$(dkmstree),,$(realpath $(dir $(lastword $(MAKEFILE_LIST))))) + +srcarch := $(shell uname -m | sed -e "s/i.86/x86/" -e "s/x86_64/x86/" \ + -e "s/sun4u/sparc64/" -e "s/arm.*/arm/" -e "s/sa110/arm/" \ + -e "s/s390x/s390/" -e "s/parisc64/parisc/" \ + -e "s/ppc.*/powerpc/" -e "s/mips.*/mips/" \ + -e "s/sh[234].*/sh/" -e "s/aarch64.*/arm64/") + +userinclude := \ + -I$(srctree)/arch/$(srcarch)/include/uapi \ + -I$(srctree)/arch/$(srcarch)/include/generated/uapi \ + -I$(srctree)/include/uapi \ + -I$(srctree)/include/generated/uapi \ + -include $(srctree)/include/linux/kconfig.h + +linuxinclude := \ + -I$(srctree)/arch/$(srcarch)/include \ + -I$(srctree)/arch/$(srcarch)/include/generated \ + -I$(srctree)/include \ + $(userinclude) + +all: config clean + +config: force + @( \ + cd $(srctree)/$(dkmstree); \ + ./autogen.sh; \ + CPPFLAGS="$(linuxinclude)" ./configure \ + --enable-linux-builtin \ + --with-linux=$(srctree) \ + ) + +clean: force + @( \ + cd $(srctree)/$(dkmstree); \ + rm -f aclocal.m4 config.* configure config/*.in* \ + ) + +.PHONY: all force From dcdbeb29d6cfbd970a0eb615f498ade24dfe8a65 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 11 Mar 2020 18:13:25 -0400 Subject: [PATCH 0123/2653] drm/amdkcl/autoconf: properly define and initialize Makefile variables 1. Properly define ..._FULL_PATH variables in amdgpu, ttm, and scheduler trees. That fixes 'make -C ... M=... modiles' build to succeed correctly. 2. Cleanup of the DKMS Makefile and modified DKMS pre-build.sh script to execute 'configure' from the original directory location It's a squash of 65727463b0e9 drm/ttm,scheduler,amdgpu: properly define and initialize Makefile variables db30b3d31f5f amd/amdkcl: fix Makefile include paths 08ebd9dfa583 amd/amdkcl: use relative path in DKMS pre-build.sh Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/Makefile | 6 +++--- drivers/gpu/drm/amd/dkms/Makefile | 2 +- drivers/gpu/drm/amd/dkms/dkms.conf | 2 +- drivers/gpu/drm/amd/dkms/pre-build.sh | 6 +++--- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 3e0e0e28d53cc..05130f47e5d1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -24,8 +24,8 @@ # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. FULL_AMD_PATH := $(patsubst %/amdgpu,%,$(src)) -DISPLAY_FOLDER_NAME=display -FULL_AMD_DISPLAY_PATH = $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME) +DISPLAY_FOLDER_NAME := display +FULL_AMD_DISPLAY_PATH := $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME) ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \ -I$(FULL_AMD_PATH)/include \ @@ -309,7 +309,7 @@ amdgpu-y += $(AMD_POWERPLAY_FILES) ifneq ($(CONFIG_DRM_AMD_DC),) -RELATIVE_AMD_DISPLAY_PATH = ../$(DISPLAY_FOLDER_NAME) +RELATIVE_AMD_DISPLAY_PATH := ../$(DISPLAY_FOLDER_NAME) include $(FULL_AMD_DISPLAY_PATH)/Makefile amdgpu-y += $(AMD_DISPLAY_FILES) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index d628e1b4340ad..f960a4375859e 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -120,7 +120,7 @@ endif export OS_NAME OS_VERSION -subdir-ccflags-y += -include $(src)/config/config.h +subdir-ccflags-y += -include $(src)/amd/dkms/config/config.h LINUXINCLUDE := \ -I$(src)/include \ diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 86826daa80072..7a6075f32cb5a 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -2,7 +2,7 @@ PACKAGE_NAME="amdgpu" PACKAGE_VERSION="1.0" AUTOINSTALL="yes" REMAKE_INITRD="yes" -PRE_BUILD="pre-build.sh $kernelver" +PRE_BUILD="amd/dkms/pre-build.sh $kernelver" # not work with RHEL DKMS #MODULES_CONF[0]="blacklist radeon" diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 7d1dca12d6f33..a6be48877eec8 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -73,10 +73,10 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do done export KERNELVER -CPPFLAGS="-I$SRCTREE/arch/$SRCARCH/include \ +(cd $SRC && CPPFLAGS="-I$SRCTREE/arch/$SRCARCH/include \ -I$BLDTREE/arch/$SRCARCH/include/generated \ -I$SRCTREE/include \ -I$BLDTREE/include \ -I$SRCTREE/include/uapi \ - -include linux/kconfig.h" \ - ./configure + -include $SRCTREE/include/linux/kconfig.h" \ + ./configure) From 9cd12bc85499908b479838d8ccdc31ed16aa9c15 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 8 Jan 2021 10:29:46 +0800 Subject: [PATCH 0124/2653] drm/amdkcl/autoconf: build conftest.o directly no need to build a module v2: detect single target build capability in autoconf test instead of grep Makefile directly. Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 8 ++++++-- .../gpu/drm/amd/dkms/m4/kernel_single_target.m4 | 16 ++++++++++++++++ 2 files changed, 22 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0f35e04f1f51c..51e88cfc25d17 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -3,6 +3,7 @@ dnl # Default kernel configuration dnl # AC_DEFUN([AC_CONFIG_KERNEL], [ AC_KERNEL + AC_KERNEL_SINGLE_TARGET AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ @@ -200,6 +201,10 @@ AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) m4_ifvaln([$6], [AC_KERNEL_CONFTEST_H([$6])], [AC_KERNEL_CONFTEST_H([])]) touch conftest.mod.c + if test "x$SINGLE_TARGET_BUILD_NO_TMP_VERSIONS" = x1; then + test -d $SINGLE_TARGET_BUILD_MODVERDIR || mkdir $SINGLE_TARGET_BUILD_MODVERDIR + rm -f $SINGLE_TARGET_BUILD_MODVERDIR/* + fi echo "obj-m := conftest.o" >Makefile kbuild_src_flag='' kbuild_modpost_flag='KBUILD_MODPOST_NOFINAL=1 KBUILD_MODPOST_WARN=1' @@ -236,8 +241,7 @@ dnl # $3: run it if compile pass. dnl # $4: run it if compile fail. dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], - target='' - test "x$enable_linux_builtin" = xyes && target='conftest.o' + target='conftest.o' [AC_KERNEL_COMPILE_IFELSE( [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], [$target], diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 new file mode 100644 index 0000000000000..6793169a5624d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v4.20-rc2-10-ge07db28eea38 +dnl # kbuild: fix single target build for external module +dnl # +AC_DEFUN([AC_KERNEL_SINGLE_TARGET], [ + AC_KERNEL_TMP_BUILD_DIR([ + AC_KERNEL_TRY_COMPILE([], [], [], [ + SINGLE_TARGET_BUILD_MODVERDIR=.tmp_versions + AS_IF([test ! -d $SINGLE_TARGET_BUILD_MODVERDIR], [ + SINGLE_TARGET_BUILD_NO_TMP_VERSIONS=1 + ], [ + AC_MSG_WARN([compile single target fail expectedly]) + ]) + ]) + ]) +]) From 206ccb494db25eb1d42c904fd676e1937e0e33c3 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 11 Jan 2021 14:12:52 +0800 Subject: [PATCH 0125/2653] drm/amdkcl/autoconf: extract cc&&cppflags to test header files Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile.config | 21 +---------- .../drm/amd/dkms/m4/kernel_single_target.m4 | 36 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 23 +----------- 3 files changed, 38 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile.config b/drivers/gpu/drm/amd/dkms/Makefile.config index 2b1a73c63bee3..f6d23defbaae6 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile.config +++ b/drivers/gpu/drm/amd/dkms/Makefile.config @@ -1,32 +1,13 @@ dkmstree := drivers/gpu/drm/amd/dkms srctree := $(subst /$(dkmstree),,$(realpath $(dir $(lastword $(MAKEFILE_LIST))))) -srcarch := $(shell uname -m | sed -e "s/i.86/x86/" -e "s/x86_64/x86/" \ - -e "s/sun4u/sparc64/" -e "s/arm.*/arm/" -e "s/sa110/arm/" \ - -e "s/s390x/s390/" -e "s/parisc64/parisc/" \ - -e "s/ppc.*/powerpc/" -e "s/mips.*/mips/" \ - -e "s/sh[234].*/sh/" -e "s/aarch64.*/arm64/") - -userinclude := \ - -I$(srctree)/arch/$(srcarch)/include/uapi \ - -I$(srctree)/arch/$(srcarch)/include/generated/uapi \ - -I$(srctree)/include/uapi \ - -I$(srctree)/include/generated/uapi \ - -include $(srctree)/include/linux/kconfig.h - -linuxinclude := \ - -I$(srctree)/arch/$(srcarch)/include \ - -I$(srctree)/arch/$(srcarch)/include/generated \ - -I$(srctree)/include \ - $(userinclude) - all: config clean config: force @( \ cd $(srctree)/$(dkmstree); \ ./autogen.sh; \ - CPPFLAGS="$(linuxinclude)" ./configure \ + ./configure \ --enable-linux-builtin \ --with-linux=$(srctree) \ ) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index 6793169a5624d..ca2404840d5cb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -1,3 +1,38 @@ +dnl # +dnl # extract cc, cflags, cppflags +dnl # +AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ + AS_IF([test -s .conftest.o.cmd], [ + _base_cflags="-DKBUILD_BASENAME='\"conftest\"' -DKBUILD_MODNAME='\"conftest\"'" + _base_dir=$(basename $PWD) + _conftest_cmd=$(head -1 .conftest.o.cmd) + + CC=$(echo $_conftest_cmd | awk -F ' ' '{print $[3]}') + CFLAGS=$(echo $_conftest_cmd | \ + sed -e 's| -|\n&|g' | \ + sed -e "s|\./|${LINUX_OBJ}/|" \ + -e "s|-I\([[[a-z]]]*\)|-I${LINUX_OBJ}/\1|" \ + -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|" \ + -e '/conftest/d' \ + -e '/KBUILD_/d' \ + -e "/$_base_dir/d" | \ + xargs) + CPPFLAGS=$(echo $CFLAGS | \ + sed 's| -|\n&|g' | \ + sed -n '/-I/p; /-include/p; /-isystem/p; /-D/p' | \ + xargs) + + CFLAGS="$CFLAGS $_base_cflags" + CPPFLAGS="$CPPFLAGS $_base_cflags" + + AC_SUBST(CC) + AC_SUBST(CFLAGS) + AC_SUBST(CPPFLAGS) + ], [ + AC_MSG_ERROR([cannot detect CFLAGS...]) + ]) +]) + dnl # dnl # v4.20-rc2-10-ge07db28eea38 dnl # kbuild: fix single target build for external module @@ -12,5 +47,6 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET], [ AC_MSG_WARN([compile single target fail expectedly]) ]) ]) + AC_KERNEL_SINGLE_TARGET_CFLAGS ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index a6be48877eec8..b87289082387a 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -6,21 +6,6 @@ SRC="amd/dkms" KERNELVER=$1 KERNELVER_BASE=${KERNELVER%%-*} -SRCTREE=/lib/modules/$KERNELVER - -if [ -L $SRCTREE/source ]; then - BLDTREE="$SRCTREE/build" - SRCTREE="$SRCTREE/source" -else - SRCTREE="$SRCTREE/build" - BLDTREE="$SRCTREE" -fi - -SRCARCH=$(uname -m | sed -e "s/i.86/x86/" -e "s/x86_64/x86/" \ - -e "s/sun4u/sparc64/" -e "s/arm.*/arm/" -e "s/sa110/arm/" \ - -e "s/s390x/s390/" -e "s/parisc64/parisc/" \ - -e "s/ppc.*/powerpc/" -e "s/mips.*/mips/" \ - -e "s/sh[234].*/sh/" -e "s/aarch64.*/arm64/") version_lt () { newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) @@ -73,10 +58,4 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do done export KERNELVER -(cd $SRC && CPPFLAGS="-I$SRCTREE/arch/$SRCARCH/include \ - -I$BLDTREE/arch/$SRCARCH/include/generated \ - -I$SRCTREE/include \ - -I$BLDTREE/include \ - -I$SRCTREE/include/uapi \ - -include $SRCTREE/include/linux/kconfig.h" \ - ./configure) +(cd $SRC && ./configure) From 58d13b2f154c5473b882cbe4b3fac35d5c19a817 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 11 Jan 2021 14:58:12 +0800 Subject: [PATCH 0126/2653] drm/amdkcl/autoconf: extract cflags to compile contest.o directly Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 39 +++++++++++++++++-- .../drm/amd/dkms/m4/kernel_single_target.m4 | 2 +- 2 files changed, 36 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 51e88cfc25d17..0593e48224aaa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -189,7 +189,7 @@ $2 ]) dnl # -dnl # AC_KERNEL_COMPILE_IFELSE / like AC_COMPILE_IFELSE +dnl # AC_KERNEL_COMPILE_MODULE_IFELSE / like AC_COMPILE_IFELSE dnl # $1: contents to be filled in conftest.c dnl # $2: make target. dnl # $3: user defined commands. It "AND" the make command to check the result. If true, expands to $4. Otherwise $5. @@ -197,7 +197,7 @@ dnl # $4: run it if make & $3 pass. dnl # $5: run it if make & $3 fail. dnl # $6: contents to be filled in conftest.h. Could be null. dnl # -AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ +AC_DEFUN([AC_KERNEL_COMPILE_MODULE_IFELSE], [ m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) m4_ifvaln([$6], [AC_KERNEL_CONFTEST_H([$6])], [AC_KERNEL_CONFTEST_H([])]) touch conftest.mod.c @@ -233,6 +233,39 @@ AC_DEFUN([AC_KERNEL_TMP_BUILD_DIR], [ rm -rf $build_dir ]) +dnl # +dnl # AC_KERNEL_TRY_COMPILE_MODULE like AC_TRY_COMPILE +dnl # $1: Prologue for conftest.c. including header files, extends, etc +dnl # $2: Body for conftest.c. +dnl # $3: run it if compile pass. +dnl # $4: run it if compile fail. +dnl # +AC_DEFUN([AC_KERNEL_TRY_COMPILE_MODULE], + target='conftest.o' + [AC_KERNEL_COMPILE_MODULE_IFELSE( + [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], + [$target], + [test -s conftest.o], + [$3], [$4]) +]) + +dnl # +dnl # AC_KERNEL_COMPILE_IFELSE / like AC_COMPILE_IFELSE +dnl # $1: contents to be filled in conftest.c +dnl # $2: user defined commands. It "AND" the make command to check the result. If true, expands to $4. Otherwise $5. +dnl # $3: run it if make & $3 pass. +dnl # $4: run it if make & $3 fail. +dnl # $5: contents to be filled in conftest.h. Could be null. +dnl # +AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ + m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) + m4_ifvaln([$5], [AC_KERNEL_CONFTEST_H([$5])], [AC_KERNEL_CONFTEST_H([])]) + AS_IF( + [AC_TRY_COMMAND($CC $CFLAGS -o conftest.o conftest.c) >/dev/null && AC_TRY_COMMAND([$2])], + [$3], + [_AC_MSG_LOG_CONFTEST m4_ifvaln([$4],[$4])] + ) +]) dnl # dnl # AC_KERNEL_TRY_COMPILE like AC_TRY_COMPILE dnl # $1: Prologue for conftest.c. including header files, extends, etc @@ -241,10 +274,8 @@ dnl # $3: run it if compile pass. dnl # $4: run it if compile fail. dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], - target='conftest.o' [AC_KERNEL_COMPILE_IFELSE( [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], - [$target], [test -s conftest.o], [$3], [$4]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index ca2404840d5cb..7eb3fe010ee93 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -39,7 +39,7 @@ dnl # kbuild: fix single target build for external module dnl # AC_DEFUN([AC_KERNEL_SINGLE_TARGET], [ AC_KERNEL_TMP_BUILD_DIR([ - AC_KERNEL_TRY_COMPILE([], [], [], [ + AC_KERNEL_TRY_COMPILE_MODULE([], [], [], [ SINGLE_TARGET_BUILD_MODVERDIR=.tmp_versions AS_IF([test ! -d $SINGLE_TARGET_BUILD_MODVERDIR], [ SINGLE_TARGET_BUILD_NO_TMP_VERSIONS=1 From 425db9d2a349d18c49ead076937942d40b1d43ac Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 13 Jan 2021 14:18:20 +0800 Subject: [PATCH 0127/2653] drm/amdkcl/autoconf: rework *FLAGS_.o handle of path Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 | 12 ++++++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 7 +++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index 7eb3fe010ee93..b4af835c8928f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -33,6 +33,17 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ ]) ]) +dnl # +dnl # v5.3-rc4-54-g54b8ae66ae1a +dnl # kbuild: change *FLAGS_.o to take the path relative to $(obj) +dnl # +AC_DEFUN([AC_KERNEL_FLAGS_TAKE_PATH], [ + AS_IF([grep -qsm 1 "target-stem" ${LINUX}/scripts/Makefile.lib], [ + AC_DEFINE(HAVE_AMDKCL_FLAGS_TAKE_PATH, 1, + [*FLAGS_.o support to take the path relative to $(obj)]) + ]) +]) + dnl # dnl # v4.20-rc2-10-ge07db28eea38 dnl # kbuild: fix single target build for external module @@ -48,5 +59,6 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET], [ ]) ]) AC_KERNEL_SINGLE_TARGET_CFLAGS + AC_KERNEL_FLAGS_TAKE_PATH ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index b87289082387a..745124a028bc7 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -59,3 +59,10 @@ done export KERNELVER (cd $SRC && ./configure) + +# rename CFLAGS_target.o to CFLAGS_target.o +if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then + for file in $(grep -rl 'CFLAGS_' amd/display/); do + sed -i 's|$(AMDDALPATH)/.*/\(.*\.o\)|\1|' $file + done +fi From f85b9f9384e34f410bb55e52d2e147959591b5ec Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 24 Mar 2020 19:24:29 -0400 Subject: [PATCH 0128/2653] drm/amdkcl/autoconf: add includes config.h in Makefile It's a squash of 70619a89cb10 amd/amdkcl: drop BUILD_AS_DKMS compilation flag 9bdcf23b7b68 drm/amdkcl: drop DKMS build when in the source tree 4304e2beb859 amd/amdkcl: clean up includes in backport/Makefile Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 5 +++++ drivers/gpu/drm/amd/backport/Makefile | 7 ++++++- drivers/gpu/drm/amd/dkms/Makefile | 2 -- drivers/gpu/drm/scheduler/backport/Makefile | 2 ++ drivers/gpu/drm/ttm/backport/Makefile | 4 ++++ 5 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 018792c49a249..5dcd2f97fc29b 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -1,4 +1,9 @@ # SPDX-License-Identifier: MIT amdkcl-y += main.o +ccflags-y += \ + -include $(src)/../dkms/config/config.h + +ccflags-y += -DHAVE_CONFIG_H + obj-m += amdkcl.o diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index ca667992f6f72..1ad8a02a4b19f 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -4,5 +4,10 @@ BACKPORT_OBJS := amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) ccflags-y += \ + -I$(FULL_AMD_PATH) \ -I$(FULL_AMD_PATH)/backport/include \ - -include ../backport/backport.h + -I$(FULL_AMD_PATH)/dkms \ + -include config/config.h \ + -include backport/backport.h + +ccflags-y += -DHAVE_CONFIG_H diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index f960a4375859e..ce753462ac58c 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -120,8 +120,6 @@ endif export OS_NAME OS_VERSION -subdir-ccflags-y += -include $(src)/amd/dkms/config/config.h - LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/uapi \ diff --git a/drivers/gpu/drm/scheduler/backport/Makefile b/drivers/gpu/drm/scheduler/backport/Makefile index 5fe7a0b580f33..01bf391770a05 100644 --- a/drivers/gpu/drm/scheduler/backport/Makefile +++ b/drivers/gpu/drm/scheduler/backport/Makefile @@ -1,4 +1,6 @@ # SPDX-License-Identifier: MIT ccflags-y += \ -I$(SCHED_FULL_PATH) \ + -I$(SCHED_FULL_PATH)/../amd/dkms \ + -include config/config.h \ -include backport/backport.h diff --git a/drivers/gpu/drm/ttm/backport/Makefile b/drivers/gpu/drm/ttm/backport/Makefile index 839110332c785..0ccfec344b665 100644 --- a/drivers/gpu/drm/ttm/backport/Makefile +++ b/drivers/gpu/drm/ttm/backport/Makefile @@ -1,4 +1,8 @@ # SPDX-License-Identifier: MIT ccflags-y += \ -I$(TTM_FULL_PATH) \ + -I$(TTM_FULL_PATH)/../amd/dkms \ + -include config/config.h \ -include backport/backport.h + +ccflags-y += -DHAVE_CONFIG_H From 26516d08e527397ca3bc37ba06b8c63c62c40ec8 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 20 Jan 2021 17:58:01 +0800 Subject: [PATCH 0129/2653] drm/amdkcl: fix include path for dkms package Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index ce753462ac58c..7c227452be97c 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -120,12 +120,20 @@ endif export OS_NAME OS_VERSION +LINUX_SRCTREE_INCLUDE := \ + $(filter-out -I%/uapi -include %/kconfig.h,$(LINUXINCLUDE)) +USER_INCLUDE := $(filter-out $(LINUX_SRCTREE_INCLUDE), $(LINUXINCLUDE)) + LINUXINCLUDE := \ -I$(src)/include \ - -I$(src)/include/uapi \ + -I$(src)/include/kcl/header \ -include $(src)/include/kcl/kcl_version.h \ -include $(src)/include/rename_symbol.h \ - $(LINUXINCLUDE) + -include $(src)/amd/dkms/config/config.h \ + $(LINUX_SRCTREE_INCLUDE) \ + -I$(src)/include/uapi \ + -I$(src)/include/kcl/header/uapi \ + $(USER_INCLUDE) export CONFIG_HSA_AMD=y export CONFIG_DRM_TTM=m From 8b14dea9dd8b5622995c9bfc6502256ad67f7256 Mon Sep 17 00:00:00 2001 From: Jeremy Newton Date: Fri, 9 Mar 2018 11:23:15 -0500 Subject: [PATCH 0130/2653] drm/amdkcl: Add wattman example script Signed-off-by: Jeremy Newton Acked-by: Slava Grigorev --- .../dkms/docs/examples/wattman-example-script | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/docs/examples/wattman-example-script diff --git a/drivers/gpu/drm/amd/dkms/docs/examples/wattman-example-script b/drivers/gpu/drm/amd/dkms/docs/examples/wattman-example-script new file mode 100644 index 0000000000000..90b14faec6dbf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/docs/examples/wattman-example-script @@ -0,0 +1,74 @@ +## wattman-like functionality +# boot with amdgpu.ppfeaturemask=0xffffffff (make sure PP_OVERDRIVE_MASK bit is set see hwmgr.h) +# see the current dpm clock and voltage levels +cat /sys/class/drm/card0/device/pp_od_clk_voltage +#OD_SCLK: +#0: 300Mhz 900 mV +#1: 484Mhz 925 mV +#2: 709Mhz 962 mV +#3: 858Mhz 1112 mV +#4: 891Mhz 1150 mV +#5: 917Mhz 1175 mV +#6: 949Mhz 1175 mV +#7: 973Mhz 1175 mV +#OD_MCLK: +#0: 150Mhz 900 mV +#1: 1375Mhz 975 mV +# change mclk dpm level 0 from 150 to 155Mhz, no change to voltage +# format is "m dpm_level clock_in_mhz voltage_in_mv" +echo "m 0 155 900" > /sys/class/drm/card0/device/pp_od_clk_voltage +# change sclk dpm level 7 from 973 to 975Mhz, change voltage from 1175 to 1180 mV +# format is "s dpm_level clock_in_mhz voltage_in_mv" +echo "s 7 975 1180" > /sys/class/drm/card0/device/pp_od_clk_voltage +# change sclk dpm level 5 from 917 to 910Mhz, change voltage from 1175 to 1160 mV +# format is "s dpm_level clock_in_mhz voltage_in_mv" +echo "s 7 910 1160" > /sys/class/drm/card0/device/pp_od_clk_voltage +# see the current dpm clock and voltage levels +cat /sys/class/drm/card0/device/pp_od_clk_voltage +#OD_SCLK: +#0: 300Mhz 900 mV +#1: 484Mhz 925 mV +#2: 709Mhz 962 mV +#3: 858Mhz 1112 mV +#4: 891Mhz 1150 mV +#5: 910Mhz 1160 mV +#6: 949Mhz 1175 mV +#7: 975Mhz 1180 mV +#OD_MCLK: +#0: 155Mhz 900 mV +#1: 1375Mhz 975 mV +# commit the changes to the hw +echo "c" > /sys/class/drm/card0/device/pp_od_clk_voltage +# reset to the default dpm states +echo "r" > /sys/class/drm/card0/device/pp_od_clk_voltage +# commit the reset state to the hw +echo "c" > /sys/class/drm/card0/device/pp_od_clk_voltage + +## reading/adjusting hwmon values +# https://www.kernel.org/doc/Documentation/hwmon/sysfs-interface +# see which hwmon device this is +cat /sys/class/hwmon/hwmon0/name +# readback current vddgfx/vddnb voltages +# see which one this is +cat /sys/class/hwmon/hwmon0/in0_label +# read the voltage (mV) +cat /sys/class/hwmon/hwmon0/in0_input +# see current power (microwatts) +cat /sys/class/hwmon/hwmon0/power1_average +# current temp (millidegrees C) +cat /sys/class/hwmon/hwmon0/temp1_input +# see fan speed (rpm) +cat /sys/class/hwmon/hwmon0/fan1_input +# see fan speed pwm (0-255) +cat /sys/class/hwmon/hwmon0/pwm1 +# see min/max pwm limits +cat /sys/class/hwmon/hwmon0/pwm1_min +cat /sys/class/hwmon/hwmon0/pwm1_max +# see current fan control mode (0 none, 1 manual fan control, 2 dynamic fan control) +cat /sys/class/hwmon/hwmon0/pwm1_enable +# enable manual fan control +echo 1 > /sys/class/hwmon/hwmon0/pwm1_enable +# manually set the fan speed (100/255 = 39%) +echo 100 > /sys/class/hwmon/hwmon0/pwm1 +# enable automatic fan control +echo 2 > /sys/class/hwmon/hwmon0/pwm1_enable From dbc490a4992649f6e51ea1ba594645fec5cd44d4 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 17 Dec 2020 16:55:26 +0800 Subject: [PATCH 0131/2653] drm/amdkcl: add prefix for amdkcl log Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 ++- drivers/gpu/drm/amd/amdkcl/kcl_common.h | 10 ++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_common.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 5dcd2f97fc29b..0bed0b09bc09f 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -2,7 +2,8 @@ amdkcl-y += main.o ccflags-y += \ - -include $(src)/../dkms/config/config.h + -include $(src)/../dkms/config/config.h \ + -include $(src)/kcl_common.h ccflags-y += -DHAVE_CONFIG_H diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_common.h b/drivers/gpu/drm/amd/amdkcl/kcl_common.h new file mode 100644 index 0000000000000..d547bd5608e47 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_common.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_COMMON_H +#define AMDKCL_COMMON_H + +#ifdef pr_fmt +#undef pr_fmt +#endif +#define pr_fmt(fmt) "amdkcl: " fmt + +#endif From 06076dae7ba12ea4bcb4ed85f2781aec601527a8 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Fri, 8 Nov 2019 12:14:03 +0800 Subject: [PATCH 0132/2653] drm/amdkcl: add lookpup unexported symbol support v2: test kallsyms_lookup_name() is exported. v3: fix awk syntax to find kallsyms_lookup_name() addr. v4: use kprobe to find out kallsyms_lookup_name() Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Flora Cui Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_common.c | 49 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/kcl_common.h | 5 ++ drivers/gpu/drm/amd/amdkcl/main.c | 3 ++ .../drm/amd/dkms/m4/kallsyms-lookup-name.m4 | 14 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/pre-build.sh | 2 +- 7 files changed, 74 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_common.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 0bed0b09bc09f..a805915aba6b9 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: MIT -amdkcl-y += main.o +amdkcl-y += main.o symbols.o kcl_common.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_common.c b/drivers/gpu/drm/amd/amdkcl/kcl_common.c new file mode 100644 index 0000000000000..5867b4d1a6c38 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_common.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: MIT */ +#include +#include +#include +#include +#include + +unsigned long (*_kcl_kallsyms_lookup_name)(const char *name); + +void *amdkcl_fp_setup(const char *symbol, void *dummy) +{ + unsigned long addr; + void *fp = dummy; + + addr = _kcl_kallsyms_lookup_name(symbol); + if (addr == 0) { + if (fp) + pr_warn("Warning: fail to get symbol %s, replace it with kcl stub\n", symbol); + else { + pr_err("Error: fail to get symbol %s, abort...\n", symbol); + BUG(); + } + } else { + fp = (void *)addr; + } + + return fp; +} + +void amdkcl_symbol_init(void) +{ +#ifndef HAVE_KALLSYMS_LOOKUP_NAME + struct kprobe kp; + int r; + + memset(&kp, 0, sizeof(kp)); + kp.symbol_name = "kallsyms_lookup_name"; + r = register_kprobe(&kp); + if (!r) { + _kcl_kallsyms_lookup_name = (void *)kp.addr; + unregister_kprobe(&kp); + } else { + pr_err("fail to get kallsyms_lookup_name, abort...\n"); + BUG(); + } +#else + _kcl_kallsyms_lookup_name = kallsyms_lookup_name; +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_common.h b/drivers/gpu/drm/amd/amdkcl/kcl_common.h index d547bd5608e47..de8bdd481dc98 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_common.h +++ b/drivers/gpu/drm/amd/amdkcl/kcl_common.h @@ -2,9 +2,14 @@ #ifndef AMDKCL_COMMON_H #define AMDKCL_COMMON_H +#include +#include + #ifdef pr_fmt #undef pr_fmt #endif #define pr_fmt(fmt) "amdkcl: " fmt +void *amdkcl_fp_setup(const char *symbol, void *dummy); + #endif diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 59f4520c9a8bd..4a0f67981e1c4 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -2,8 +2,11 @@ #include #include +extern void amdkcl_symbol_init(void); + int __init amdkcl_init(void) { + amdkcl_symbol_init(); return 0; } module_init(amdkcl_init); diff --git a/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 b/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 new file mode 100644 index 0000000000000..62e540f41a7df --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 @@ -0,0 +1,14 @@ +dnl # +dnl # v5.6-11591-g0bd476e6c671 kallsyms: unexport kallsyms_lookup_name() and kallsyms_on_each_symbol() +dnl # v2.6.32-rc4-272-gf60d24d2ad04 hw-breakpoints: Fix broken hw-breakpoint sample module +dnl # +AC_DEFUN([AC_AMDGPU_KALLSYMS_LOOKUP_NAME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([kallsyms_lookup_name], + [kernel/kallsyms.c], + [ + AC_DEFINE(HAVE_KALLSYMS_LOOKUP_NAME, 1, + [kallsyms_lookup_name is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0593e48224aaa..d3555facee09e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -4,6 +4,7 @@ dnl # AC_DEFUN([AC_CONFIG_KERNEL], [ AC_KERNEL AC_KERNEL_SINGLE_TARGET + AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 745124a028bc7..698e69b364c03 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -33,7 +33,7 @@ source $KCL/files # lookup symbol address. obsolete. echo '// auto generated by DKMS pre-build.sh' > $KCL/symbols.c for sym in $SYMS; do - awk -v sym=$sym '/\/ { + awk -v sym=$sym '$3 == sym { print "void *_kcl_" $3 " = (void *)0x" $1 ";" }' /boot/System.map-$KERNELVER >>$KCL/symbols.c done From d274fec3b08501ccad51052d39aa2754b8293592 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 13 May 2020 15:41:04 +0800 Subject: [PATCH 0133/2653] drm/amdkcl: create dummy func for funcs unavailable Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkcl/kcl_common.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_common.h b/drivers/gpu/drm/amd/amdkcl/kcl_common.h index de8bdd481dc98..9c9eca94212b9 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_common.h +++ b/drivers/gpu/drm/amd/amdkcl/kcl_common.h @@ -12,4 +12,15 @@ void *amdkcl_fp_setup(const char *symbol, void *dummy); +/* + * create dummy func + */ +#define amdkcl_dummy_symbol(name, ret_type, ret, ...) \ +ret_type name(__VA_ARGS__) \ +{ \ + pr_warn_once("%s is not supported\n", #name); \ + ret ;\ +} \ +EXPORT_SYMBOL(name); + #endif From 4508007fa81ad1ebbac5d832278f151c6daf0302 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Mon, 13 Apr 2020 21:51:37 +0800 Subject: [PATCH 0134/2653] drm/amdkcl: add AC_AMDGPU_LINUX_HEADERS it is a squash of: 5ded515e0816 drm/amdkcl: update test for linux/dma-resv.h 0b63eb175dbb drm/amdkcl: drop individual tests for header files 221c1ea7b3db drm/amdkcl: fix license c444a2fe2e49 drm/amdkcl: move kcl wrapper for linux header to header dir 627af54ab135 drm/amdkcl: add AC_AMDGPU_LINUX_HEADERS Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Jack Gui Reviewed-by: Yifan Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 75 +++++++++++++++++++ include/kcl/header/asm/set_memory.h | 11 +++ include/kcl/header/linux/bits.h | 11 +++ include/kcl/header/linux/dma-buf-map.h | 9 +++ .../kcl/header/linux/io-64-nonatomic-lo-hi.h | 11 +++ include/kcl/header/linux/pci-p2pdma.h | 9 +++ include/kcl/header/uapi/linux/sched/types.h | 9 +++ 8 files changed, 136 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 create mode 100644 include/kcl/header/asm/set_memory.h create mode 100644 include/kcl/header/linux/bits.h create mode 100644 include/kcl/header/linux/dma-buf-map.h create mode 100644 include/kcl/header/linux/io-64-nonatomic-lo-hi.h create mode 100644 include/kcl/header/linux/pci-p2pdma.h create mode 100644 include/kcl/header/uapi/linux/sched/types.h diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d3555facee09e..6f85d0821c5f3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -4,6 +4,7 @@ dnl # AC_DEFUN([AC_CONFIG_KERNEL], [ AC_KERNEL AC_KERNEL_SINGLE_TARGET + AC_AMDGPU_LINUX_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_KERNEL_WAIT diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 new file mode 100644 index 0000000000000..38b46427e3689 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -0,0 +1,75 @@ +AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ + + dnl # + dnl # commit 8bd9cb51daac89337295b6f037b0486911e1b408 + dnl # locking/atomics, asm-generic: Move some macros from + dnl # to a new file + dnl # + AC_KERNEL_CHECK_HEADERS([linux/bits.h]) + + dnl # + dnl # commit v4.3-rc4-1-g2f8e2c877784 + dnl # move io-64-nonatomic*.h out of asm-generic + dnl # + AC_KERNEL_CHECK_HEADERS([linux/io-64-nonatomic-lo-hi.h]) + + dnl # + dnl # commit 299878bac326c890699c696ebba26f56fe93fc75 + dnl # treewide: move set_memory_* functions away from cacheflush.h + dnl # + AC_KERNEL_CHECK_HEADERS([asm/set_memory.h]) + + dnl # + dnl # commit df6b35f409af0a8ff1ef62f552b8402f3fef8665 + dnl # x86/fpu: Rename i387.h to fpu/api.h + dnl # + AC_KERNEL_CHECK_HEADERS([asm/fpu/api.h]) + + dnl # + dnl # commit 607ca46e97a1b6594b29647d98a32d545c24bdff + dnl # UAPI: (Scripted) Disintegrate include/linux + dnl # + AC_KERNEL_CHECK_HEADERS([uapi/linux/sched/types.h]) + + dnl # + dnl # v4.19-rc6-7-ga3f8a30f3f00 + dnl # Compiler Attributes: use feature checks instead of version checks + dnl # + AC_KERNEL_CHECK_HEADERS([linux/compiler_attributes.h]) + + dnl # + dnl # v4.9-rc2-299-gf54d1867005c + dnl # dma-buf: Rename struct fence to dma_fence + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-fence.h]) + + dnl # + dnl # v5.3-rc1-449-g52791eeec1d9 + dnl $ dma-buf: rename reservation_object to dma_resv + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-resv.h]) + + dnl # + dnl # v5.7-13149-g9740ca4e95b4 + dnl # mmap locking API: initial implementation as rwsem wrappers + dnl # + AC_KERNEL_CHECK_HEADERS([linux/mmap_lock.h]) + + dnl # + dnl # v4.19-rc4-1-g52916982af48 + dnl # PCI/P2PDMA: Support peer-to-peer memory + dnl # + AC_KERNEL_CHECK_HEADERS([linux/pci-p2pdma.h]) + + dnl # + dnl # v4.7-11546-g00085f1efa38 + dnl # dma-mapping: use unsigned long for dma_attrs + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-attrs.h]) + + dnl # + dnl # 01fd30da0474 + dnl # dma-buf: Add struct dma-buf-map for storing struct dma_buf.vaddr_ptr + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-buf-map.h]) +]) diff --git a/include/kcl/header/asm/set_memory.h b/include/kcl/header/asm/set_memory.h new file mode 100644 index 0000000000000..4614c4c1c4630 --- /dev/null +++ b/include/kcl/header/asm/set_memory.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__ASM_SET_MEMORY_H_H_ +#define _KCL_HEADER__ASM_SET_MEMORY_H_H_ + +#if defined(HAVE_ASM_SET_MEMORY_H) +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/header/linux/bits.h b/include/kcl/header/linux/bits.h new file mode 100644 index 0000000000000..28a84955dc780 --- /dev/null +++ b/include/kcl/header/linux/bits.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__LINUX_BITS_H_H_ +#define _KCL_HEADER__LINUX_BITS_H_H_ + +#if defined(HAVE_LINUX_BITS_H) +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/header/linux/dma-buf-map.h b/include/kcl/header/linux/dma-buf-map.h new file mode 100644 index 0000000000000..523dfcfabda8b --- /dev/null +++ b/include/kcl/header/linux/dma-buf-map.h @@ -0,0 +1,9 @@ +#ifndef _KCL_HEADER___DMA_BUF_MAP_H___H_ +#define _KCL_HEADER___DMA_BUF_MAP_H___H_ + +#ifdef HAVE_LINUX_DMA_BUF_MAP_H +#include_next +#endif + +#endif + diff --git a/include/kcl/header/linux/io-64-nonatomic-lo-hi.h b/include/kcl/header/linux/io-64-nonatomic-lo-hi.h new file mode 100644 index 0000000000000..0fa2e108091b7 --- /dev/null +++ b/include/kcl/header/linux/io-64-nonatomic-lo-hi.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_IO_64_NONATOMIC_LO_HI_H_H_ +#define _KCL_HEADER_LINUX_IO_64_NONATOMIC_LO_HI_H_H_ + +#ifdef HAVE_LINUX_IO_64_NONATOMIC_LO_HI_H +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/header/linux/pci-p2pdma.h b/include/kcl/header/linux/pci-p2pdma.h new file mode 100644 index 0000000000000..84ad226012bdc --- /dev/null +++ b/include/kcl/header/linux/pci-p2pdma.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_PCI_P2PDMA_H_H_ +#define _KCL_HEADER_LINUX_PCI_P2PDMA_H_H_ + +#ifdef HAVE_LINUX_PCI_P2PDMA_H +#include_next +#endif + +#endif diff --git a/include/kcl/header/uapi/linux/sched/types.h b/include/kcl/header/uapi/linux/sched/types.h new file mode 100644 index 0000000000000..871f2abf23d37 --- /dev/null +++ b/include/kcl/header/uapi/linux/sched/types.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_UAPI_LINUX_SCHED_TYPES_H_H_ +#define _KCL_HEADER_UAPI_LINUX_SCHED_TYPES_H_H_ + +#ifdef HAVE_UAPI_LINUX_SCHED_TYPES_H +#include_next +#endif + +#endif From 9d6ef61631aa00123a6d0ebccc03769d2c91c582 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Mon, 13 Apr 2020 21:53:07 +0800 Subject: [PATCH 0135/2653] drm/amdkcl: add AC_AMDGPU_DRM_HEADERS v2: test for drm/drm_backport.h (Flora.Cui@amd.com) RHEL 7.x wraps some API in drm/drm_backport.h header file Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Change-Id: I2717f0cfb3caaeb93f409656c6ce7c88fecc36de Reviewed-by: Yang Xiong Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 41 ++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/header/drm/drmP.h | 9 +++++ include/kcl/header/drm/drm_managed.h | 9 +++++ include/kcl/header/drm/drm_print.h | 10 ++++++ include/kcl/header/drm/drm_probe_helper.h | 11 ++++++ include/kcl/header/drm/task_barrier.h | 9 +++++ 7 files changed, 90 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 create mode 100644 include/kcl/header/drm/drmP.h create mode 100644 include/kcl/header/drm/drm_managed.h create mode 100644 include/kcl/header/drm/drm_print.h create mode 100644 include/kcl/header/drm/drm_probe_helper.h create mode 100644 include/kcl/header/drm/task_barrier.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 new file mode 100644 index 0000000000000..5db23c22d9fe3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -0,0 +1,41 @@ +AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ + dnl # + dnl # RHEL 7.x wrapper + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_backport.h]) + + dnl # + dnl # Optional devices ID for amdgpu driver + dnl # + AC_KERNEL_CHECK_HEADERS([drm/amdgpu_pciid.h]) + + dnl # + dnl # commit v4.9-rc2-477-gd8187177b0b1 + dnl # drm: add helper for printing to log or seq_file + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_print.h]) + + dnl # + dnl # commit v5.0-rc1-342-gfcd70cd36b9b + dnl # drm: Split out drm_probe_helper.h + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_probe_helper.h]) + + dnl # + dnl # v5.4-rc1-214-g4e98f871bcff + dnl # drm: delete drmP.h + drm_os_linux.h + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drmP.h]) + + dnl # + dnl # commit v5.5-rc2-783-g368fd0aad1be + dnl # drm: Add Reusable task barrier. + dnl # + AC_KERNEL_CHECK_HEADERS([drm/task_barrier.h]) + + dnl # + dnl # v5.6-rc5-1258-gc6603c740e0e + dnl # drm: add managed resources tied to drm_device + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_managed.h]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6f85d0821c5f3..a61ba77924c84 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -5,6 +5,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_KERNEL AC_KERNEL_SINGLE_TARGET AC_AMDGPU_LINUX_HEADERS + AC_AMDGPU_DRM_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_KERNEL_WAIT diff --git a/include/kcl/header/drm/drmP.h b/include/kcl/header/drm/drmP.h new file mode 100644 index 0000000000000..008236685b081 --- /dev/null +++ b/include/kcl/header/drm/drmP.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRMP_H_H_ +#define _KCL_HEADER_DRMP_H_H_ + +#ifdef HAVE_DRM_DRMP_H +#include_next +#endif + +#endif diff --git a/include/kcl/header/drm/drm_managed.h b/include/kcl/header/drm/drm_managed.h new file mode 100644 index 0000000000000..d6f211d64b346 --- /dev/null +++ b/include/kcl/header/drm/drm_managed.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_KCL_DRM_MANAGED_H_H +#define _KCL_HEADER_KCL_DRM_MANAGED_H_H + +#ifdef HAVE_DRM_DRM_MANAGED_H +#include_next +#endif + +#endif diff --git a/include/kcl/header/drm/drm_print.h b/include/kcl/header/drm/drm_print.h new file mode 100644 index 0000000000000..0f1db6376a8a3 --- /dev/null +++ b/include/kcl/header/drm/drm_print.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_PRINT_H_H_ +#define _KCL_HEADER_DRM_PRINT_H_H_ + +#if defined(HAVE_DRM_DRM_PRINT_H) +#include_next +#endif +#include + +#endif diff --git a/include/kcl/header/drm/drm_probe_helper.h b/include/kcl/header/drm/drm_probe_helper.h new file mode 100644 index 0000000000000..a454fe92ea203 --- /dev/null +++ b/include/kcl/header/drm/drm_probe_helper.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_PROBE_HELPER_H_H_ +#define _KCL_HEADER_DRM_PROBE_HELPER_H_H_ + +#ifdef HAVE_DRM_DRM_PROBE_HELPER_H +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/header/drm/task_barrier.h b/include/kcl/header/drm/task_barrier.h new file mode 100644 index 0000000000000..e93315f493f3e --- /dev/null +++ b/include/kcl/header/drm/task_barrier.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_TASK_BARRIER_H_H_ +#define _KCL_HEADER_DRM_TASK_BARRIER_H_H_ + +#ifdef HAVE_DRM_TASK_BARRIER_H +#include_next +#endif + +#endif From f16f6d90f0160413fa355b2866e848f06a9d021b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 3 Feb 2021 11:07:04 +0800 Subject: [PATCH 0136/2653] drm/amdkcl: DROPME: include amdgpu_amdkfd.h in kfd_priv.h Change-Id: Ia5f684b21b7cbd3cc98b048cf8a586a6b79c46f1 Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 67694bcd94646..4711a1d1d107c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -46,6 +46,7 @@ #include #include +#include "amdgpu_amdkfd.h" #include "amd_shared.h" #include "amdgpu.h" From ba0356b1e554d6b35588846261ccbeec9bcddd19 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 9 Mar 2021 09:59:48 +0800 Subject: [PATCH 0137/2653] drm/amdkcl: DROPME: include linux/sched/mm.h in ttm_tt.c Change-Id: I3cbc5f6e03c28c7db1895cb8d2015e5f698546ee Signed-off-by: Flora Cui --- drivers/gpu/drm/ttm/ttm_tt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 506e257dfba85..15bad8ef53005 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -37,6 +37,8 @@ #include #include #include +#include +#include #include #include #include From fcda72755f5910c4f7c841dc254e070b154f5a8b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 9 Mar 2021 10:14:58 +0800 Subject: [PATCH 0138/2653] drm/amdkcl: REWORKME: config.h Change-Id: I981875bb459ee1d29553b026e33b316e185250cb Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 147 +++++++++++++++++++++++ 1 file changed, 147 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/config/config.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h new file mode 100644 index 0000000000000..5c604c53ed971 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -0,0 +1,147 @@ +/* config/config.h. Generated from config.h.in by configure. */ +/* config/config.h.in. Generated from configure.ac by autoheader. */ + +/* *FLAGS_.o support to take the path relative to $(obj) */ +#define HAVE_AMDKCL_FLAGS_TAKE_PATH 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_ASM_FPU_API_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_ASM_SET_MEMORY_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_AMDGPU_PCIID_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_DRMP_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_ATOMIC_UAPI_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_AUDIO_COMPONENT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_AUTH_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_DRM_BACKPORT_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_CONNECTOR_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_DEBUGFS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_DEVICE_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_DRV_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_ENCODER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_FILE_H 1 + +/* Define to 1 if you have the header file. + */ +#define HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_HDCP_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_IOCTL_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_IRQ_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_MANAGED_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_PLANE_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_PRINT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_PROBE_HELPER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_UTIL_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_VBLANK_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_TASK_BARRIER_H 1 + +/* kallsyms_lookup_name is available */ +/* #undef HAVE_KALLSYMS_LOOKUP_NAME */ + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_BITS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_COMPILER_ATTRIBUTES_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_LINUX_DMA_ATTRS_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_FENCE_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_RESV_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_IO_64_NONATOMIC_LO_HI_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_MEM_ENCRYPT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_MMAP_LOCK_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_NOSPEC_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_OVERFLOW_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_PCI_P2PDMA_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_SCHED_MM_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_SCHED_SIGNAL_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_SCHED_TASK_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_UAPI_LINUX_SCHED_TYPES_H 1 + +/* Define to the address where bug reports for this package should be sent. */ +#define PACKAGE_BUGREPORT "" + +/* Define to the full name of this package. */ +#define PACKAGE_NAME "amdgpu-dkms" + +/* Define to the full name and version of this package. */ +#define PACKAGE_STRING "amdgpu-dkms 19.40" + +/* Define to the one symbol short name of this package. */ +#define PACKAGE_TARNAME "amdgpu-dkms" + +/* Define to the home page for this package. */ +#define PACKAGE_URL "" + +/* Define to the version of this package. */ +#define PACKAGE_VERSION "19.40" From 329195c89be1e4f00872cd79867f95013b5ba53d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 9 Mar 2021 11:52:01 +0800 Subject: [PATCH 0139/2653] drm/amdkcl: fake hexint support for module_param Change-Id: Ic6b3fd5e2ca1e6e645c658924cc051b6119297b6 Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 ++ .../gpu/drm/amd/amdkcl/kcl_kernel_params.c | 29 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_moduleparam.h | 17 +++++++++++ 4 files changed, 49 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c create mode 100644 include/kcl/kcl_moduleparam.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index a805915aba6b9..6d6d62a8e05a1 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -1,6 +1,8 @@ # SPDX-License-Identifier: MIT amdkcl-y += main.o symbols.o kcl_common.o +amdkcl-y += kcl_kernel_params.o + ccflags-y += \ -include $(src)/../dkms/config/config.h \ -include $(src)/kcl_common.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c b/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c new file mode 100644 index 0000000000000..d350a6bd07769 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Helpers for initial module or kernel cmdline parsing + Copyright (C) 2001 Rusty Russell. + +*/ +#include + +// Copied from kernel/params.c +#define STANDARD_PARAM_DEF(name, type, format, strtolfn) \ + int param_set_##name(const char *val, const struct kernel_param *kp) \ + { \ + return strtolfn(val, 0, (type *)kp->arg); \ + } \ + int param_get_##name(char *buffer, const struct kernel_param *kp) \ + { \ + return scnprintf(buffer, PAGE_SIZE, format "\n", \ + *((type *)kp->arg)); \ + } \ + const struct kernel_param_ops param_ops_##name = { \ + .set = param_set_##name, \ + .get = param_get_##name, \ + }; \ + EXPORT_SYMBOL(param_set_##name); \ + EXPORT_SYMBOL(param_get_##name); \ + EXPORT_SYMBOL(param_ops_##name) + +#ifdef _kcl_param_check_hexint +STANDARD_PARAM_DEF(hexint, unsigned int, "%#08x", kstrtouint); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 89cd9143a9c0a..e30fbea884c07 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -4,4 +4,5 @@ #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_moduleparam.h b/include/kcl/kcl_moduleparam.h new file mode 100644 index 0000000000000..427abe45ea8af --- /dev/null +++ b/include/kcl/kcl_moduleparam.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_LINUX_MODULE_PARAMS_H_H +#define _KCL_KCL_LINUX_MODULE_PARAMS_H_H + +#include +#include + +/* Copied from v5.8-rc2-514-g7d8365771ffb include/linux/moduleparam.h */ +#ifndef param_check_hexint +#define _kcl_param_check_hexint +extern const struct kernel_param_ops param_ops_hexint; +extern int param_set_hexint(const char *val, const struct kernel_param *kp); +extern int param_get_hexint(char *buffer, const struct kernel_param *kp); +#define param_check_hexint(name, p) param_check_uint(name, p) +#endif /* param_check_hexint */ + +#endif From c2d22bbb2fef959fc9e5916a424d94e6870f4357 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Mon, 18 Feb 2019 10:31:07 +0800 Subject: [PATCH 0140/2653] drm/amdkcl: Test whether kref_read() function is available drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling drm/amdkcl: [4.11] fix for kref_read - v2: define a common api instead of referring individually Change-Id: I9ae193c10ab864534a4d64bd8dd71e03284c59b1 Signed-off-by: Evan Quan Reviewed-by: Junwei Zhang Signed-off-by: Jack Gui drm/amdkcl: Test whether kref_read() function is available Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/kref-read.m4 | 16 +++++++++++++++ drivers/gpu/drm/ttm/backport/backport.h | 2 +- include/kcl/kcl_kref.h | 25 ++++++++++++++++++++++++ 5 files changed, 44 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/kref-read.m4 create mode 100644 include/kcl/kcl_kref.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e30fbea884c07..9845b606cb752 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -5,4 +5,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a61ba77924c84..d3c709f916a9c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -7,6 +7,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_HEADERS AC_AMDGPU_DRM_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME + AC_AMDGPU_KREF_READ AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/kref-read.m4 b/drivers/gpu/drm/amd/dkms/m4/kref-read.m4 new file mode 100644 index 0000000000000..da7e2bf0aac37 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kref-read.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 2c935bc57221cc2edc787c72ea0e2d30cdcd3d5e +dnl # locking/atomic, kref: Add kref_read() +dnl # +AC_DEFUN([AC_AMDGPU_KREF_READ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + kref_read(NULL); + ], [ + AC_DEFINE(HAVE_KREF_READ, 1, + [kref_read() function is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 524d2a01b50df..11a9f3a7c0b36 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -3,5 +3,5 @@ #define AMDTTM_BACKPORT_H #include - +#include #endif diff --git a/include/kcl/kcl_kref.h b/include/kcl/kcl_kref.h new file mode 100644 index 0000000000000..0cc53e385e8db --- /dev/null +++ b/include/kcl/kcl_kref.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * kref.h - library routines for handling generic reference counted objects + * + * Copyright (C) 2004 Greg Kroah-Hartman + * Copyright (C) 2004 IBM Corp. + * + * based on kobject.h which was: + * Copyright (C) 2002-2003 Patrick Mochel + * Copyright (C) 2002-2003 Open Source Development Labs + */ +#ifndef AMDKCL_KREF_H +#define AMDKCL_KREF_H + +#include + +/* Copied from include/linux/kref.h */ +#if !defined(HAVE_KREF_READ) +static inline unsigned int kref_read(const struct kref *kref) +{ + return atomic_read(&kref->refcount); +} +#endif + +#endif /* AMDKCL_KREF_H */ From c5d68f26f60705734a9d2f85543affaa80329423 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Mon, 18 Nov 2019 16:52:31 +0800 Subject: [PATCH 0141/2653] drm/amdkcl: check whether idr_for_each_entry_continue is avialable it is a squash of: c1f004d6344b drm/amdkcl: fix license for kcl part 7b1a9f7a702c drm/amdkcl: fake idr_remove() 41a5a48a1668 drm/amdkcl: check whether idr_for_each_entry_continue is avialable Signed-off-by: Chengming Gui Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Jiansong Chen Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 | 19 ++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_idr.h | 38 +++++++++++++++++++++++ 4 files changed, 59 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 create mode 100644 include/kcl/kcl_idr.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 9845b606cb752..b0ee7c7bd37c9 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -5,5 +5,6 @@ #include #include #include +#include #include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 b/drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 new file mode 100644 index 0000000000000..397c76a73ed8e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit d3e709e63e97e5f3f129b639991cfe266da60bae +dnl # Author: Matthew Wilcox +dnl # Date: Thu Dec 22 13:30:22 2016 -0500 +dnl # idr: Return the deleted entry from idr_remove +dnl # +AC_DEFUN([AC_AMDGPU_IDR_REMOVE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + void *i; + i = idr_remove(NULL, 0); + ], [ + AC_DEFINE(HAVE_IDR_REMOVE_RETURN_VOID_POINTER, 1, + [idr_remove return void pointer]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d3c709f916a9c..9813e2f903e53 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -7,6 +7,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_HEADERS AC_AMDGPU_DRM_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME + AC_AMDGPU_IDR_REMOVE AC_AMDGPU_KREF_READ AC_KERNEL_WAIT diff --git a/include/kcl/kcl_idr.h b/include/kcl/kcl_idr.h new file mode 100644 index 0000000000000..63473317c2ead --- /dev/null +++ b/include/kcl/kcl_idr.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * include/linux/idr.h + * + * 2002-10-18 written by Jim Houston jim.houston@ccur.com + * Copyright (C) 2002 by Concurrent Computer Corporation + * + * Small id to pointer translation service avoiding fixed sized + * tables. + */ +#ifndef AMDKCL_IDR_H +#define AMDKCL_IDR_H + +#include + +/* Copied from v4.4-rc2-61-ga55bbd375d18 include/linux/idr.h */ +#ifndef idr_for_each_entry_continue +#define idr_for_each_entry_continue(idr, entry, id) \ + for ((entry) = idr_get_next((idr), &(id)); \ + entry; \ + ++id, (entry) = idr_get_next((idr), &(id))) +#endif + +#ifndef HAVE_IDR_REMOVE_RETURN_VOID_POINTER +static inline void *_kcl_idr_remove(struct idr *idr, int id) +{ + void *ptr; + + ptr = idr_find(idr, id); + if (ptr) + idr_remove(idr, id); + + return ptr; +} +#define idr_remove _kcl_idr_remove +#endif /* HAVE_IDR_REMOVE_RETURN_VOID_POINTER */ + +#endif /* AMDKCL_IDR_H */ From e4d679c2d2b51f5324194cbacebd3083045523ab Mon Sep 17 00:00:00 2001 From: changzhu Date: Fri, 16 Aug 2019 12:18:26 +0800 Subject: [PATCH 0142/2653] drm/amdkcl: Test whether type __poll_t is available [Why] __poll_t is not defined until patch: define __poll_t, annotate constants So there will be build error when using it in kfd_debug_events.c This problem is caused by patch: drm/amdkfd: add debug notification [How] Use autoconf patch to define __poll_t if it's not defined. Change-Id: I56bbeea7c27eb2974f224e8bccafb8bd97c794c1 Signed-off-by: changzhu Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling drm/amd/autoconf: Test whether type __poll_t is available(v2) Change-Id: I397a3403223f9cbcfc29d36d63544ce4ca7ed4c6 Signed-off-by: changzhu Reviewed-by: Flora Cui drm/amdkcl: fix macro define for __POLL_T Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: drop HAVE_TYPE__POLL_T check outside of kcl Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 | 16 ++++++++++++++++ include/kcl/kcl_types.h | 13 +++++++++++++ 4 files changed, 31 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 create mode 100644 include/kcl/kcl_types.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b0ee7c7bd37c9..0ce187a5e10a6 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9813e2f903e53..4f333f126a2a7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -9,6 +9,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_AMDGPU_IDR_REMOVE AC_AMDGPU_KREF_READ + AC_AMDGPU_TYPE__POLL_T AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 b/drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 new file mode 100644 index 0000000000000..a5744a51a8ffb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v4.15-rc1-4-g8ced390c2b18 +dnl # define __poll_t, annotate constants +dnl # +AC_DEFUN([AC_AMDGPU_TYPE__POLL_T], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + __poll_t mask = 0; + ],[ + AC_DEFINE(HAVE_TYPE__POLL_T, 1, [__poll_t is available]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_types.h b/include/kcl/kcl_types.h new file mode 100644 index 0000000000000..66ff65a627e5a --- /dev/null +++ b/include/kcl/kcl_types.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_TYPES_H +#define AMDKCL_TYPES_H + +/* Copied from v4.15-rc1-4-g8ced390c2b18 include/uapi/linux/types.h */ +#ifndef HAVE_TYPE__POLL_T +#ifdef __CHECK_POLL +typedef unsigned __bitwise __poll_t; +#else +typedef unsigned __poll_t; +#endif +#endif +#endif From 3c851d78c9b12ca72aed0c9fdc41a536086cf9cc Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 7 Nov 2019 11:31:51 +0800 Subject: [PATCH 0143/2653] drm/amdkcl: fake DMA_ATTR_NO_WARN if undefined Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: test dma_map_sgtable() is available fake a kcl copy of dma_map_sgtable() & dma_unmap_sgtable() Signed-off-by: Flora Cui Change-Id: I277799b85805aefa105c73c88d0ba01ad44c1912 drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/dkms/m4/dma_map_sgtable.m4 | 21 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_dma_mapping.h | 90 +++++++++++++++++++ 5 files changed, 114 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma_map_sgtable.m4 create mode 100644 include/kcl/kcl_dma_mapping.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 0ce187a5e10a6..352104e6dadfa 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -8,4 +8,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_map_sgtable.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_map_sgtable.m4 new file mode 100644 index 0000000000000..09d1275020880 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_map_sgtable.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # v5.7-rc5-32-gd9d200bcebc1 +dnl # dma-mapping: add generic helpers for mapping sgtable objects +dnl # +AC_DEFUN([AC_AMDGPU_DMA_MAP_SGTABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_map_sgtable(NULL, NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_DMA_MAP_SGTABLE, 1, + [dma_map_sgtable() is enabled]) + ] + dnl # + dnl # v4.7-11546-g00085f1efa38 + dnl # dma-mapping: use unsigned long for dma_attrs + dnl # leverage test for linux/dma-attrs.h + ) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4f333f126a2a7..f8da5e6791870 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -10,6 +10,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IDR_REMOVE AC_AMDGPU_KREF_READ AC_AMDGPU_TYPE__POLL_T + AC_AMDGPU_DMA_MAP_SGTABLE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 11a9f3a7c0b36..fbb66d01e2665 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -4,4 +4,5 @@ #include #include +#include #endif diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h new file mode 100644 index 0000000000000..c7de48cd9aad7 --- /dev/null +++ b/include/kcl/kcl_dma_mapping.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_DMA_MAPPING_H +#define AMDKCL_DMA_MAPPING_H + +#include + +/* + * commit v4.8-11962-ga9a62c938441 + * dma-mapping: introduce the DMA_ATTR_NO_WARN attribute + */ +#ifndef DMA_ATTR_NO_WARN +#define DMA_ATTR_NO_WARN (0UL) +#endif + +#ifdef HAVE_LINUX_DMA_ATTRS_H +static inline +void _kcl_convert_long_to_dma_attrs(struct dma_attrs *dma_attrs, + unsigned long attrs) +{ + int i; + + init_dma_attrs(dma_attrs); + + for (i = 0; i < DMA_ATTR_MAX; i++) { + if (attrs & (1 << i)) + dma_set_attr(i, dma_attrs); + } +} +#endif + +#ifndef HAVE_DMA_MAP_SGTABLE +#ifdef HAVE_LINUX_DMA_ATTRS_H +static inline +int _kcl_dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction dir, unsigned long attrs) +{ + struct dma_attrs dma_attrs; + + _kcl_convert_long_to_dma_attrs(&dma_attrs, attrs); + return dma_map_sg_attrs(dev, sg, nents, dir, &dma_attrs); +} + +static inline +void _kcl_dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir, + unsigned long attrs) + +{ + struct dma_attrs dma_attrs; + + _kcl_convert_long_to_dma_attrs(&dma_attrs, attrs); + dma_unmap_sg_attrs(dev, sg, nents, dir, &dma_attrs); +} + +#else +static inline +int _kcl_dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction dir, unsigned long attrs) +{ + return dma_map_sg_attrs(dev, sg, nents, dir, attrs); +} +static inline +void _kcl_dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir, + unsigned long attrs) +{ + dma_unmap_sg_attrs(dev, sg, nents, dir, attrs); +} +#endif /* HAVE_LINUX_DMA_ATTRS_H */ + +static inline int dma_map_sgtable(struct device *dev, struct sg_table *sgt, + enum dma_data_direction dir, unsigned long attrs) +{ + int nents; + + nents = _kcl_dma_map_sg_attrs(dev, sgt->sgl, sgt->orig_nents, dir, attrs); + if (nents <= 0) + return -EINVAL; + sgt->nents = nents; + return 0; +} + +static inline void dma_unmap_sgtable(struct device *dev, struct sg_table *sgt, + enum dma_data_direction dir, unsigned long attrs) +{ + _kcl_dma_unmap_sg_attrs(dev, sgt->sgl, sgt->orig_nents, dir, attrs); +} +#endif + +#endif From e5713bcfb642a3165bbeb3a8b72272567451a839 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 8 Sep 2020 14:17:21 +0800 Subject: [PATCH 0144/2653] drm/amdkcl: test i2c_new_client_device() is available v2: add extern for i2c_new_client_device() available case for phantom kernel forget to declare the func it is a squash of: b677e39b1c70 drm/amdkcl: test i2c_new_client_device() is available c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../drm/amd/dkms/m4/i2c_new_client_device.m4 | 13 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_i2c.h | 26 +++++++++++++++++++ 4 files changed, 41 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 create mode 100644 include/kcl/kcl_i2c.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 352104e6dadfa..49648f356a682 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -9,4 +9,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 b/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 new file mode 100644 index 0000000000000..cedd29e0fe70e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # v5.1-12318-g7159dbdae3c5 +dnl # i2c: core: improve return value handling of i2c_new_device and i2c_new_dummy +dnl # +AC_DEFUN([AC_AMDGPU_I2C_NEW_CLIENT_DEVICE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([i2c_new_client_device], [drivers/i2c/i2c-core-base.c], + [ + AC_DEFINE(HAVE_I2C_NEW_CLIENT_DEVICE, 1, + [i2c_new_client_device() is enabled]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f8da5e6791870..3ca7e932c5758 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -11,6 +11,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KREF_READ AC_AMDGPU_TYPE__POLL_T AC_AMDGPU_DMA_MAP_SGTABLE + AC_AMDGPU_I2C_NEW_CLIENT_DEVICE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_i2c.h b/include/kcl/kcl_i2c.h new file mode 100644 index 0000000000000..66b3195eff49d --- /dev/null +++ b/include/kcl/kcl_i2c.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * i2c.h - definitions for the Linux i2c bus interface + * Copyright (C) 1995-2000 Simon G. Vogl + * Copyright (C) 2013-2019 Wolfram Sang + * + * With some changes from Kyösti Mälkki and + * Frodo Looijaard + */ +#ifndef _KCL_KCL_I2C_H +#define _KCL_KCL_I2C_H + +#include + +#ifdef HAVE_I2C_NEW_CLIENT_DEVICE +extern struct i2c_client * +i2c_new_client_device(struct i2c_adapter *adap, struct i2c_board_info const *info); +#else +static inline struct i2c_client * +i2c_new_client_device(struct i2c_adapter *adap, struct i2c_board_info const *info) +{ + return i2c_new_device(adap, info); +} +#endif + +#endif From 1fa362f90598fd023089c2377699c5e0c90a026c Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Thu, 20 Sep 2018 20:18:21 +0800 Subject: [PATCH 0145/2653] drm/amdkcl: Test whether request_firmware_direct() is available This is a squash of: v1: drm/amdkcl: [3.14] Add request_firmware_direct adaptor for load_dmcu_fw v2: drm/amdkcl: Test whether request_firmware_direct() is available c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Prike Liang Reviewed-by: Junwei Zhang Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/request-firmware-direct.m4 | 16 ++++++++++++++++ include/kcl/kcl_firmware.h | 12 ++++++++++++ 4 files changed, 31 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/request-firmware-direct.m4 create mode 100644 include/kcl/kcl_firmware.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 49648f356a682..6d65256b54b43 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -10,4 +10,6 @@ #include #include #include +#include + #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3ca7e932c5758..071269037d3d4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -12,6 +12,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TYPE__POLL_T AC_AMDGPU_DMA_MAP_SGTABLE AC_AMDGPU_I2C_NEW_CLIENT_DEVICE + AC_AMDGPU_REQUEST_FIRMWARE_DIRECT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/request-firmware-direct.m4 b/drivers/gpu/drm/amd/dkms/m4/request-firmware-direct.m4 new file mode 100644 index 0000000000000..218e403328bc8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/request-firmware-direct.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v3.13-rc2-51-gbba3a87e982a +dnl # firmware: Introduce request_firmware_direct() +dnl # +AC_DEFUN([AC_AMDGPU_REQUEST_FIRMWARE_DIRECT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + request_firmware_direct(NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_REQUEST_FIRMWARE_DIRECT, 1, + [request_firmware_direct() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_firmware.h b/include/kcl/kcl_firmware.h new file mode 100644 index 0000000000000..b846e2d4eee5d --- /dev/null +++ b/include/kcl/kcl_firmware.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_FIRMWARE_H +#define AMDKCL_FIRMWARE_H + +#if !defined(HAVE_REQUEST_FIRMWARE_DIRECT) +#include + +#define request_firmware_direct request_firmware + +#endif +#endif /* AMDKCL_FIRMWARE_H */ + From 3ee8a9996b417d732538071dead62d9aae3a2884 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Wed, 6 May 2020 17:13:38 +0800 Subject: [PATCH 0146/2653] drm/amdkcl: Test whether backlight_device_set_brightness is available introduced by kernel: v4.7-rc2~9^2^2~5 v2: add kcl copy of backlight_device_set_brightness This is a squash of: c1f004d6344b drm/amdkcl: fix license for kcl part f11810210f8a drm/amdkcl: Test whether backlight_device_set_brightness is available Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 ++ drivers/gpu/drm/amd/amdkcl/kcl_backlight.c | 14 ++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../dkms/m4/backlight-device-set-brightness.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_backlight.h | 16 ++++++++++++++++ 6 files changed, 50 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_backlight.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/backlight-device-set-brightness.m4 create mode 100644 include/kcl/kcl_backlight.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 6d6d62a8e05a1..4b40eff8ae672 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -3,6 +3,8 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o +amdkcl-y += kcl_backlight.o + ccflags-y += \ -include $(src)/../dkms/config/config.h \ -include $(src)/kcl_common.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_backlight.c b/drivers/gpu/drm/amd/amdkcl/kcl_backlight.c new file mode 100644 index 0000000000000..1e1da40b92c05 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_backlight.c @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Backlight Lowlevel Control Abstraction + * + * Copyright (C) 2003,2004 Hewlett-Packard Company + * + */ +#include + +#ifndef HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS +amdkcl_dummy_symbol(backlight_device_set_brightness, int, return 0, + struct backlight_device *bd, unsigned long brightness) +#endif + diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6d65256b54b43..7b2cdba58783f 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -11,5 +11,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/backlight-device-set-brightness.m4 b/drivers/gpu/drm/amd/dkms/m4/backlight-device-set-brightness.m4 new file mode 100644 index 0000000000000..b021cbc2ab976 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/backlight-device-set-brightness.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v4.6-rc6-1-gf6a4790a5471 +dnl # video / backlight: add two APIs for drivers to use +dnl # +AC_DEFUN([AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + backlight_device_set_brightness(NULL, 0); + ], [backlight_device_set_brightness], [drivers/video/backlight/backlight.c], [ + AC_DEFINE(HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS, 1, + [backlight_device_set_brightness() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 071269037d3d4..c821cf258e209 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -13,6 +13,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_MAP_SGTABLE AC_AMDGPU_I2C_NEW_CLIENT_DEVICE AC_AMDGPU_REQUEST_FIRMWARE_DIRECT + AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_backlight.h b/include/kcl/kcl_backlight.h new file mode 100644 index 0000000000000..1d06b61502c3c --- /dev/null +++ b/include/kcl/kcl_backlight.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Backlight Lowlevel Control Abstraction + * + * Copyright (C) 2003,2004 Hewlett-Packard Company + * + */ +#ifndef AMDKCL_BACKLIGHT_H +#define AMDKCL_BACKLIGHT_H + +#include +#ifndef HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS +int backlight_device_set_brightness(struct backlight_device *bd, + unsigned long brightness); +#endif /* HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS */ +#endif From 69af12ffdfe06b2dddfa5da1ae6818539f55e0d1 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Apr 2020 10:31:41 +0800 Subject: [PATCH 0147/2653] drm/amdkcl: fake a kcl copy of compat_ptr_ioctl() This is a squash of: c1f004d6344b drm/amdkcl: fix license for kcl part 2011137fd5d7 drm/amdkcl: fake a kcl copy of compat_ptr_ioctl() Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_ioctl.c | 45 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 2 +- .../gpu/drm/amd/dkms/m4/compat_ptr_ioctl.m4 | 17 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_fs.h | 22 +++++++++ 6 files changed, 87 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_ioctl.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/compat_ptr_ioctl.m4 create mode 100644 include/kcl/kcl_fs.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 4b40eff8ae672..7bb382f7c3e27 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -2,8 +2,7 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o - -amdkcl-y += kcl_backlight.o +amdkcl-y += kcl_backlight.o kcl_ioctl.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_ioctl.c b/drivers/gpu/drm/amd/amdkcl/kcl_ioctl.c new file mode 100644 index 0000000000000..aef47eda7f4ab --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_ioctl.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * linux/fs/ioctl.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ +#include +#include + +/* Copied from v5.4-rc2-1-g2952db0fd51b fs/ioctl.c */ +#ifndef HAVE_COMPAT_PTR_IOCTL +#ifdef CONFIG_COMPAT +/** + * compat_ptr_ioctl - generic implementation of .compat_ioctl file operation + * + * This is not normally called as a function, but instead set in struct + * file_operations as + * + * .compat_ioctl = compat_ptr_ioctl, + * + * On most architectures, the compat_ptr_ioctl() just passes all arguments + * to the corresponding ->ioctl handler. The exception is arch/s390, where + * compat_ptr() clears the top bit of a 32-bit pointer value, so user space + * pointers to the second 2GB alias the first 2GB, as is the case for + * native 32-bit s390 user space. + * + * The compat_ptr_ioctl() function must therefore be used only with ioctl + * functions that either ignore the argument or pass a pointer to a + * compatible data type. + * + * If any ioctl command handled by fops->unlocked_ioctl passes a plain + * integer instead of a pointer, or any of the passed data types + * is incompatible between 32-bit and 64-bit architectures, a proper + * handler is required instead of compat_ptr_ioctl. + */ +long _kcl_compat_ptr_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + if (!file->f_op->unlocked_ioctl) + return -ENOIOCTLCMD; + + return file->f_op->unlocked_ioctl(file, cmd, (unsigned long)compat_ptr(arg)); +} +EXPORT_SYMBOL(_kcl_compat_ptr_ioctl); +#endif /* CONFIG_COMPAT */ +#endif /* HAVE_COMPAT_PTR_IOCTL */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7b2cdba58783f..92dcca954fe64 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -12,5 +12,5 @@ #include #include #include - +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/compat_ptr_ioctl.m4 b/drivers/gpu/drm/amd/dkms/m4/compat_ptr_ioctl.m4 new file mode 100644 index 0000000000000..f9c4c12aa4b75 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/compat_ptr_ioctl.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.4-rc2-1-g2952db0fd51b +dnl # compat_ioctl: add compat_ptr_ioctl() +dnl # +AC_DEFUN([AC_AMDGPU_COMPAT_PTR_IOCTL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + compat_ptr_ioctl(NULL, 0, 0); + ],[compat_ptr_ioctl],[fs/ioctl.c],[ + AC_DEFINE(HAVE_COMPAT_PTR_IOCTL, + 1, + [compat_ptr_ioctl() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c821cf258e209..57066ae880d37 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -14,6 +14,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_I2C_NEW_CLIENT_DEVICE AC_AMDGPU_REQUEST_FIRMWARE_DIRECT AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS + AC_AMDGPU_COMPAT_PTR_IOCTL AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_fs.h b/include/kcl/kcl_fs.h new file mode 100644 index 0000000000000..4a4c208d833e0 --- /dev/null +++ b/include/kcl/kcl_fs.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_FS_H +#define AMDKCL_FS_H + +#include +#include + +/* Copied from v5.4-rc2-1-g2952db0fd51b linux/fs.h */ +#ifndef HAVE_COMPAT_PTR_IOCTL +#ifdef CONFIG_COMPAT +extern long _kcl_compat_ptr_ioctl(struct file *file, unsigned int cmd, + unsigned long arg); +static inline long compat_ptr_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + return _kcl_compat_ptr_ioctl(file, cmd, arg); +} +#else +#define compat_ptr_ioctl NULL +#endif /* CONFIG_COMPAT */ +#endif /* HAVE_COMPAT_PTR_IOCTL */ +#endif From 07e563d5fd9e02ff4d70abff3a32c6871922731d Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Fri, 23 Dec 2016 18:32:20 +0800 Subject: [PATCH 0148/2653] drm/amdkcl: Test whether kthread_{park/unpark/parkme/should_park}() is available History: Introduced by kernel v3.7-rc1~37^2~2^2~1^2~8 Exported by kernel v4.2-rc6~15^2~9 v2: drm/amdkcl: fix kthread functions v3: drm/amdkcl: Test whether kthread_{park/unpark/parkme/should_park}() is available (v2) v4: drm/amdkcl: drop kcl_kthread_xxx v5: drm/amdkcl: update test for kthread_xxx v6: drm/amdkcl: fix license for kcl part Change-Id: I4dfe3fe981c7d4f5f60ae0a862b2c3c52bf3fca9 Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Jack Gui Reviewed-by: Flora Cui Acked-by: Feifei Xu Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_kthread.c | 67 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 3 + drivers/gpu/drm/amd/backport/backport.h | 2 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/kthread-park-xx.m4 | 14 ++++ drivers/gpu/drm/scheduler/backport/backport.h | 1 + include/kcl/backport/kcl_kthread_backport.h | 14 ++++ include/kcl/kcl_kthread.h | 14 ++++ 9 files changed, 118 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_kthread.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/kthread-park-xx.m4 create mode 100644 include/kcl/backport/kcl_kthread_backport.h create mode 100644 include/kcl/kcl_kthread.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 7bb382f7c3e27..daa8a87f99ce2 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -2,7 +2,8 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o -amdkcl-y += kcl_backlight.o kcl_ioctl.o +amdkcl-y += kcl_backlight.o kcl_ioctl.o \ + kcl_kthread.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c b/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c new file mode 100644 index 0000000000000..e6180612eaa97 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Kernel thread helper functions. + * Copyright (C) 2004 IBM Corporation, Rusty Russell. + * Copyright (C) 2009 Red Hat, Inc. + * + * Creation is done via kthreadd, so that we get a clean environment + * even if we're invoked from userspace (think modprobe, hotplug cpu, + * etc.). + */ + +/* +* FIXME: implement below API when kernel version < 4.2 +*/ +#include +#include +#include +#include "kcl_common.h" + +#if !defined(HAVE_KTHREAD_PARK_XX) +bool (*_kcl_kthread_should_park)(void); +EXPORT_SYMBOL(_kcl_kthread_should_park); + +void (*_kcl_kthread_parkme)(void); +EXPORT_SYMBOL(_kcl_kthread_parkme); + +void (*_kcl_kthread_unpark)(struct task_struct *k); +EXPORT_SYMBOL(_kcl_kthread_unpark); + +int (*_kcl_kthread_park)(struct task_struct *k); +EXPORT_SYMBOL(_kcl_kthread_park); + +static bool _kcl_kthread_should_park_stub(void) +{ + printk_once(KERN_WARNING "This kernel version not support API: kthread_should_park!\n"); + return false; +} + +static void _kcl_kthread_parkme_stub(void) +{ + printk_once(KERN_WARNING "This kernel version not support API: kthread_parkme!\n"); +} + +static void _kcl_kthread_unpark_stub(struct task_struct *k) +{ + printk_once(KERN_WARNING "This kernel version not support API: kthread_unpark!\n"); +} + +static int _kcl_kthread_park_stub(struct task_struct *k) +{ + printk_once(KERN_WARNING "This kernel version not support API: kthread_park!\n"); + return 0; +} +#endif + +void amdkcl_kthread_init(void) +{ +#if !defined(HAVE_KTHREAD_PARK_XX) + _kcl_kthread_should_park = amdkcl_fp_setup("kthread_should_park", + _kcl_kthread_should_park_stub); + _kcl_kthread_parkme = amdkcl_fp_setup("kthread_parkme", + _kcl_kthread_parkme_stub); + _kcl_kthread_unpark = amdkcl_fp_setup("kthread_unpark", + _kcl_kthread_unpark_stub); + _kcl_kthread_park = amdkcl_fp_setup("kthread_park", + _kcl_kthread_park_stub); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 4a0f67981e1c4..ecfe2b88b23ea 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -3,10 +3,13 @@ #include extern void amdkcl_symbol_init(void); +extern void amdkcl_kthread_init(void); int __init amdkcl_init(void) { amdkcl_symbol_init(); + amdkcl_kthread_init(); + return 0; } module_init(amdkcl_init); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 92dcca954fe64..258d847dad144 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -13,4 +13,6 @@ #include #include #include +#include + #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 57066ae880d37..af2e814709081 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -15,6 +15,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_REQUEST_FIRMWARE_DIRECT AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS AC_AMDGPU_COMPAT_PTR_IOCTL + AC_AMDGPU_KTHREAD_PARK_XX AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/kthread-park-xx.m4 b/drivers/gpu/drm/amd/dkms/m4/kthread-park-xx.m4 new file mode 100644 index 0000000000000..06a8af53dcfe9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kthread-park-xx.m4 @@ -0,0 +1,14 @@ +dnl # +dnl # introduced commit 2a1d446019f9a5983ec5a335b95e8593fdb6fa2e +dnl # kthread: Implement park/unpark facility +dnl # exported commit 18896451eaeee497ef5c397d76902c6376a8787d +dnl # kthread: export kthread functions +dnl # +AC_DEFUN([AC_AMDGPU_KTHREAD_PARK_XX], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([kthread_parkme kthread_park kthread_unpark kthread_should_park],[kernel/kthread.c],[ + AC_DEFINE(HAVE_KTHREAD_PARK_XX, 1, + [kthread_{park/unpark/parkme/should_park}() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index b8c8be307a2e7..7994c7b3826ac 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -3,5 +3,6 @@ #define AMDSCHED_BACKPORT_H #include +#include #endif diff --git a/include/kcl/backport/kcl_kthread_backport.h b/include/kcl/backport/kcl_kthread_backport.h new file mode 100644 index 0000000000000..03875b32951e0 --- /dev/null +++ b/include/kcl/backport/kcl_kthread_backport.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_KTHREAD_BACKPORT_H +#define AMDKCL_KTHREAD_BACKPORT_H +#include +#include +#include + +#if !defined(HAVE_KTHREAD_PARK_XX) +#define kthread_parkme _kcl_kthread_parkme +#define kthread_unpark _kcl_kthread_unpark +#define kthread_park _kcl_kthread_park +#define kthread_should_park _kcl_kthread_should_park +#endif +#endif diff --git a/include/kcl/kcl_kthread.h b/include/kcl/kcl_kthread.h new file mode 100644 index 0000000000000..44b9dac5abe3b --- /dev/null +++ b/include/kcl/kcl_kthread.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_KTHREAD_H +#define AMDKCL_KTHREAD_H + +#include +#include + +#if !defined(HAVE_KTHREAD_PARK_XX) +extern void (*_kcl_kthread_parkme)(void); +extern void (*_kcl_kthread_unpark)(struct task_struct *k); +extern int (*_kcl_kthread_park)(struct task_struct *k); +extern bool (*_kcl_kthread_should_park)(void); +#endif +#endif /* AMDKCL_KTHREAD_H */ From 8381cc4c9c6185dcfd40a0aa401983527897ea47 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Wed, 13 Nov 2019 15:52:33 +0800 Subject: [PATCH 0149/2653] drm/amdkcl: Test whether __kthread_should_park() is available This is a squash of: 896d32929d9e drm/amdkcl: fix log prefix c1f004d6344b drm/amdkcl: fix license for kcl part caba32ffd8e3 drm/amdkcl: include kcl_common.h in every .c dc15fe910c0e drm/amdkcl: Test whether __kthread_should_park() is available Change-Id: Ibb7a4cc431a9c0791e64f1076cee41cad7b31e82 Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/kcl_kthread.c | 18 +++++++++++++----- .../drm/amd/dkms/m4/__kthread-should-park.m4 | 12 ++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_kthread_backport.h | 4 ++++ include/kcl/kcl_kthread.h | 4 ++++ 5 files changed, 34 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/__kthread-should-park.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c b/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c index e6180612eaa97..bfc57cb644dc9 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c @@ -14,7 +14,15 @@ #include #include #include -#include "kcl_common.h" + +#if !defined(HAVE___KTHREAD_SHOULD_PARK) +bool __kcl_kthread_should_park(struct task_struct *k) +{ + pr_warn_once("This kernel version not support API: __kthread_should_park!\n"); + return false; +} +EXPORT_SYMBOL(__kcl_kthread_should_park); +#endif #if !defined(HAVE_KTHREAD_PARK_XX) bool (*_kcl_kthread_should_park)(void); @@ -31,23 +39,23 @@ EXPORT_SYMBOL(_kcl_kthread_park); static bool _kcl_kthread_should_park_stub(void) { - printk_once(KERN_WARNING "This kernel version not support API: kthread_should_park!\n"); + pr_warn_once("This kernel version not support API: kthread_should_park!\n"); return false; } static void _kcl_kthread_parkme_stub(void) { - printk_once(KERN_WARNING "This kernel version not support API: kthread_parkme!\n"); + pr_warn_once("This kernel version not support API: kthread_parkme!\n"); } static void _kcl_kthread_unpark_stub(struct task_struct *k) { - printk_once(KERN_WARNING "This kernel version not support API: kthread_unpark!\n"); + pr_warn_once("This kernel version not support API: kthread_unpark!\n"); } static int _kcl_kthread_park_stub(struct task_struct *k) { - printk_once(KERN_WARNING "This kernel version not support API: kthread_park!\n"); + pr_warn_once("This kernel version not support API: kthread_park!\n"); return 0; } #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/__kthread-should-park.m4 b/drivers/gpu/drm/amd/dkms/m4/__kthread-should-park.m4 new file mode 100644 index 0000000000000..2cb67699eef67 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/__kthread-should-park.m4 @@ -0,0 +1,12 @@ +dnl # +dnl # introduced commit 0121805d9d2b1fff371e195c28e9b86ae38b5e47 +dnl # kthread: Add __kthread_should_park() +dnl # +AC_DEFUN([AC_AMDGPU___KTHREAD_SHOULD_PARK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([__kthread_should_park],[kernel/kthread.c],[ + AC_DEFINE(HAVE___KTHREAD_SHOULD_PARK, 1, + [__kthread_should_park() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index af2e814709081..37f8a408640fd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -16,6 +16,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS AC_AMDGPU_COMPAT_PTR_IOCTL AC_AMDGPU_KTHREAD_PARK_XX + AC_AMDGPU___KTHREAD_SHOULD_PARK AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_kthread_backport.h b/include/kcl/backport/kcl_kthread_backport.h index 03875b32951e0..898766aa6e427 100644 --- a/include/kcl/backport/kcl_kthread_backport.h +++ b/include/kcl/backport/kcl_kthread_backport.h @@ -5,6 +5,10 @@ #include #include +#if !defined(HAVE___KTHREAD_SHOULD_PARK) +#define __kthread_should_park __kcl_kthread_should_park +#endif + #if !defined(HAVE_KTHREAD_PARK_XX) #define kthread_parkme _kcl_kthread_parkme #define kthread_unpark _kcl_kthread_unpark diff --git a/include/kcl/kcl_kthread.h b/include/kcl/kcl_kthread.h index 44b9dac5abe3b..66298a3726350 100644 --- a/include/kcl/kcl_kthread.h +++ b/include/kcl/kcl_kthread.h @@ -5,6 +5,10 @@ #include #include +#if !defined(HAVE___KTHREAD_SHOULD_PATK) +extern bool __kcl_kthread_should_park(struct task_struct *k); +#endif + #if !defined(HAVE_KTHREAD_PARK_XX) extern void (*_kcl_kthread_parkme)(void); extern void (*_kcl_kthread_unpark)(struct task_struct *k); From 9097e51031a2ddc06e60a9da1caeef59f5b8a472 Mon Sep 17 00:00:00 2001 From: Yang Xiong Date: Tue, 28 Apr 2020 23:22:10 +0800 Subject: [PATCH 0150/2653] drm/amdkcl: Test whether list_rotate_to_front() and list_is_first() is available This is a squash of: b6026ffc104a drm/amdkcl: minor refactor for indent and comment style 588246ddef5a drm/amdkcl: Test whether list_rotate_to_front() and list_is_first() is available Signed-off-by: Yang Xiong Reviewed-by: Yifan Zhang Reviewed-by: Feifei Xu Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 ++ drivers/gpu/drm/amd/dkms/m4/list-is-first.m4 | 18 ++++++++++++++ .../drm/amd/dkms/m4/list-rotate_to_front.m4 | 18 ++++++++++++++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_list.h | 24 +++++++++++++++++++ 6 files changed, 64 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/list-is-first.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/list-rotate_to_front.m4 create mode 100644 include/kcl/kcl_list.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 258d847dad144..f544a1b4f8e2c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -14,5 +14,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 37f8a408640fd..133b418c86745 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -17,6 +17,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_COMPAT_PTR_IOCTL AC_AMDGPU_KTHREAD_PARK_XX AC_AMDGPU___KTHREAD_SHOULD_PARK + AC_AMDGPU_LIST_ROTATE_TO_FRONT + AC_AMDGPU_LIST_IS_FIRST AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/list-is-first.m4 b/drivers/gpu/drm/amd/dkms/m4/list-is-first.m4 new file mode 100644 index 0000000000000..566de635a47da --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/list-is-first.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 70b44595eafe9c7c235f076d653a268ca1ab9fdb +dnl # Author: Mel Gorman +dnl # Date: Tue Mar 5 15:44:54 2019 -0800 +dnl # mm, compaction: use free lists to quickly locate a migration source +dnl # +AC_DEFUN([AC_AMDGPU_LIST_IS_FIRST], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + list_is_first(NULL, NULL); + ], [ + AC_DEFINE(HAVE_LIST_IS_FIRST, 1, + [list_is_first() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/list-rotate_to_front.m4 b/drivers/gpu/drm/amd/dkms/m4/list-rotate_to_front.m4 new file mode 100644 index 0000000000000..2e914f0314652 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/list-rotate_to_front.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit a16b53849913e742d086bb2b6f5e069ea2850c56 +dnl # Author: Tobin C. Harding +dnl # Date: Mon May 13 17:15:59 2019 -0700 +dnl # list: add function list_rotate_to_front() +dnl # +AC_DEFUN([AC_AMDGPU_LIST_ROTATE_TO_FRONT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + list_rotate_to_front(NULL, NULL); + ], [ + AC_DEFINE(HAVE_LIST_ROTATE_TO_FRONT, 1, + [list_rotate_to_front() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index fbb66d01e2665..4dbd06d3e8b6c 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -5,4 +5,5 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_list.h b/include/kcl/kcl_list.h new file mode 100644 index 0000000000000..20e2bee6bef61 --- /dev/null +++ b/include/kcl/kcl_list.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_LIST_H +#define AMDKCL_LIST_H + +#include + +/* Copied from include/linux/list.h */ +#if !defined(HAVE_LIST_ROTATE_TO_FRONT) +static inline void list_rotate_to_front(struct list_head *list, + struct list_head *head) +{ + list_move_tail(head, list); +} +#endif + +#if !defined(HAVE_LIST_IS_FIRST) +static inline int list_is_first(const struct list_head *list, + const struct list_head *head) +{ + return list->prev == head; +} +#endif + +#endif /*AMDKCL_LIST_H*/ From ce917ef38754fe6cb6f9a1edeb41f80b43c55bae Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Mon, 26 Dec 2016 13:42:16 +0800 Subject: [PATCH 0151/2653] drm/amdkcl: Test whether arch_io_{reserve/free}_memtype_wc() are available arch_io_reserve_memtype_wc is introduced in v4.9-rc2-1-g8ef4227615e1. rhel < 7.8 adds an inline define to drm_backport.h squash of e07c4960e087 drm/amdkcl: update test for arch_io_reserve_memtype_wc 1943acaa561d drm/amdkcl: Test whether arch_io_{reserve/free}_memtype_wc() are available c1f004d6344b drm/amdkcl: fix license for kcl part caba32ffd8e3 drm/amdkcl: include kcl_common.h in every .c Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Jack Gui Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Chengming Gui Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui Signed-off-by: Slava Grigorev Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_io.c | 73 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/backport/backport.h | 1 + .../m4/arch-io-reserve-free-memtype-wc.m4 | 34 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_io_backport.h | 47 ++++++++++++ 7 files changed, 159 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_io.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/arch-io-reserve-free-memtype-wc.m4 create mode 100644 include/kcl/backport/kcl_io_backport.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index daa8a87f99ce2..e12717b16961b 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -3,7 +3,7 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ - kcl_kthread.o + kcl_kthread.o kcl_io.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_io.c b/drivers/gpu/drm/amd/amdkcl/kcl_io.c new file mode 100644 index 0000000000000..c1f2307557352 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_io.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Page Attribute Table (PAT) support: handle memory caching attributes in page tables. + * + * Authors: Venkatesh Pallipadi + * Suresh B Siddha + * + * Loosely based on earlier PAT patchset from Eric Biederman and Andi Kleen. + * + * Basic principles: + * + * PAT is a CPU feature supported by all modern x86 CPUs, to allow the firmware and + * the kernel to set one of a handful of 'caching type' attributes for physical + * memory ranges: uncached, write-combining, write-through, write-protected, + * and the most commonly used and default attribute: write-back caching. + * + * PAT support supercedes and augments MTRR support in a compatible fashion: MTRR is + * a hardware interface to enumerate a limited number of physical memory ranges + * and set their caching attributes explicitly, programmed into the CPU via MSRs. + * Even modern CPUs have MTRRs enabled - but these are typically not touched + * by the kernel or by user-space (such as the X server), we rely on PAT for any + * additional cache attribute logic. + * + * PAT doesn't work via explicit memory ranges, but uses page table entries to add + * cache attribute information to the mapped memory range: there's 3 bits used, + * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT), with the 8 possible values mapped by the + * CPU to actual cache attributes via an MSR loaded into the CPU (MSR_IA32_CR_PAT). + * + * ( There's a metric ton of finer details, such as compatibility with CPU quirks + * that only support 4 types of PAT entries, and interaction with MTRRs, see + * below for details. ) + */ +#include +#include + +/* Copied from arch/x86/mm/pat.c and modified for KCL */ +#if !defined(HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC) && \ + defined(CONFIG_X86) +#include + +static int (*_kcl_io_reserve_memtype)(resource_size_t start, resource_size_t end, + enum page_cache_mode *type); +static void (*_kcl_io_free_memtype)(resource_size_t start, resource_size_t end); + +int _kcl_arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size) +{ +#ifdef _PAGE_CACHE_WC + unsigned long type = _PAGE_CACHE_WC; +#else + enum page_cache_mode type = _PAGE_CACHE_MODE_WC; +#endif + + return _kcl_io_reserve_memtype(start, start + size, &type); +} +EXPORT_SYMBOL(_kcl_arch_io_reserve_memtype_wc); + +void _kcl_arch_io_free_memtype_wc(resource_size_t start, resource_size_t size) +{ + _kcl_io_free_memtype(start, start + size); +} +EXPORT_SYMBOL(_kcl_arch_io_free_memtype_wc); + +void amdkcl_io_init(void) +{ + _kcl_io_reserve_memtype = amdkcl_fp_setup("io_reserve_memtype", NULL); + _kcl_io_free_memtype = amdkcl_fp_setup("io_free_memtype", NULL); +} +#else +void amdkcl_io_init(void) +{ + +} +#endif /* HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC */ diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index ecfe2b88b23ea..f28ee41f10753 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -3,11 +3,13 @@ #include extern void amdkcl_symbol_init(void); +extern void amdkcl_io_init(void); extern void amdkcl_kthread_init(void); int __init amdkcl_init(void) { amdkcl_symbol_init(); + amdkcl_io_init(); amdkcl_kthread_init(); return 0; diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index f544a1b4f8e2c..054c67da0b571 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -15,5 +15,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/arch-io-reserve-free-memtype-wc.m4 b/drivers/gpu/drm/amd/dkms/m4/arch-io-reserve-free-memtype-wc.m4 new file mode 100644 index 0000000000000..8245a8d52ee43 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/arch-io-reserve-free-memtype-wc.m4 @@ -0,0 +1,34 @@ +dnl # +dnl # commit v4.9-rc2-1-g8ef4227615e1 +dnl # x86/io: add interface to reserve io memtype for a resource range. (v1.1) +dnl # +AC_DEFUN([AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + arch_io_reserve_memtype_wc(0, 0); + arch_io_free_memtype_wc(0, 0); + ], [arch_io_reserve_memtype_wc arch_io_free_memtype_wc], [arch/x86/mm/pat/memtype.c arch/x86/mm/pat.c], [ + AC_DEFINE(HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC, 1, + [arch_io_{reserve/free}_memtype_wc() are available]) + ], [ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRM_BACKPORT_H + #include + #endif + #include + ], [ + #ifdef CONFIG_X86 + #error stub arch_io_* functions found + #endif + + arch_io_reserve_memtype_wc(0, 0); + arch_io_free_memtype_wc(0, 0); + ], [ + AC_DEFINE(HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC, 1, + [arch_io_{reserve/free}_memtype_wc() are available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 133b418c86745..8fc3300a39266 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -19,6 +19,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___KTHREAD_SHOULD_PARK AC_AMDGPU_LIST_ROTATE_TO_FRONT AC_AMDGPU_LIST_IS_FIRST + AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_io_backport.h b/include/kcl/backport/kcl_io_backport.h new file mode 100644 index 0000000000000..8fe78d238e6f4 --- /dev/null +++ b/include/kcl/backport/kcl_io_backport.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2006 PathScale, Inc. All Rights Reserved. + */ +#ifndef AMDKCL_IO_H +#define AMDKCL_IO_H + +#include +#include + +/* Copied from arch/x86/include/asm/io.h + * include/linux/io.h + */ +#if !defined(HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC) + +#ifdef CONFIG_X86 +extern int _kcl_arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size); +extern void _kcl_arch_io_free_memtype_wc(resource_size_t start, resource_size_t size); +#define arch_io_reserve_memtype_wc _kcl_arch_io_reserve_memtype_wc +#define arch_io_free_memtype_wc _kcl_arch_io_free_memtype_wc +#endif + +#ifndef arch_io_reserve_memtype_wc +/* + * On x86 PAT systems we have memory tracking that keeps track of + * the allowed mappings on memory ranges. This tracking works for + * all the in-kernel mapping APIs (ioremap*), but where the user + * wishes to map a range from a physical device into user memory + * the tracking won't be updated. This API is to be used by + * drivers which remap physical device pages into userspace, + * and wants to make sure they are mapped WC and not UC. + */ +static inline int arch_io_reserve_memtype_wc(resource_size_t base, + resource_size_t size) +{ + return 0; +} + +static inline void arch_io_free_memtype_wc(resource_size_t base, + resource_size_t size) +{ +} +#endif + +#endif /* HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC */ + +#endif /* AMDKCL_IO_H */ From 3c825a2d8e61e995eb6ae567e585dd395a85644a Mon Sep 17 00:00:00 2001 From: chen gong Date: Wed, 5 Jun 2019 12:36:47 +0800 Subject: [PATCH 0152/2653] drm/amdkcl: Test whether access_ok(x, x) is available v2: drop kcl_access_ok Signed-off-by: chen gong Reviewed-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Acked-by: Feifei Xu Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/access-ok.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_uaccess_backport.h | 14 ++++++++++++++ 4 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/access-ok.m4 create mode 100644 include/kcl/backport/kcl_uaccess_backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 054c67da0b571..596f6f5fccf5b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -16,5 +16,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 b/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 new file mode 100644 index 0000000000000..066bd767ddf78 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 96d4f267e40f9509e8a66e2b39e8b95655617693 +dnl # Author: Linus Torvalds +dnl # Date: Thu Jan 3 18:57:57 2019 -0800 +dnl # Remove 'type' argument from access_ok() function +dnl # +AC_DEFUN([AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + access_ok(1, 1); + ],[ + AC_DEFINE(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS, 1, + [whether access_ok(x, x) is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8fc3300a39266..6f58d726463df 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -20,6 +20,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LIST_ROTATE_TO_FRONT AC_AMDGPU_LIST_IS_FIRST AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC + AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_uaccess_backport.h b/include/kcl/backport/kcl_uaccess_backport.h new file mode 100644 index 0000000000000..c7466949cad39 --- /dev/null +++ b/include/kcl/backport/kcl_uaccess_backport.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_UACCESS_BACKPORT_H +#define AMDKCL_UACCESS_BACKPORT_H +#include + +#if !defined(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS) +static inline int _kcl_access_ok(unsigned long addr, unsigned long size) +{ + return access_ok(VERIFY_WRITE, (addr), (size)); +} +#undef access_ok +#define access_ok _kcl_access_ok +#endif +#endif From 717622bc48fbec52c5918fddb7f627224c5185ef Mon Sep 17 00:00:00 2001 From: changzhu Date: Thu, 27 Jun 2019 11:36:46 +0800 Subject: [PATCH 0153/2653] drm/amdkcl: Test whether perf_event_update_userpage() is available (v2) perf_event_update_userpage exported from kernel v4.16-rc1~34^2~88^2~7 v2: remove BUILD_AS_DKMS Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: [4.16] fix perf_event_update_userpage unknown symbol build error [Why] perf_event_update_userpage is not exported in core.c until kernel version 4.16.0. So there will be unknown symbol error when using it before kernel version 4.16.0 [How] look up this symbol by using amdkcl_fp_setup Use kcl_perf_event_update_userpage to replace perf_event_update_userpage This kcl patch is caused by patch: fe96b896:drm/amdgpu: add pmu counters Change-Id: I0805e0116af2026fa0958cbda4755c75eb8bf839 Signed-off-by: changzhu Reviewed-by: Tianci Yin Signed-off-by: Jack Gui drm/amdkcl: fix check for perf_event_update_userpage() this break in-tree build Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: drop kcl_perf_event_update_userpage Signed-off-by: Flora Cui Acked-by: Feifei Xu drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c | 23 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 ++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/perf-event-update-userpage.m4 | 14 +++++++++++ .../kcl/backport/kcl_perf_event_backport.h | 10 ++++++++ include/kcl/kcl_perf_event.h | 22 ++++++++++++++++++ 8 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/perf-event-update-userpage.m4 create mode 100644 include/kcl/backport/kcl_perf_event_backport.h create mode 100644 include/kcl/kcl_perf_event.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index e12717b16961b..849d86edbb6ad 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -3,7 +3,7 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ - kcl_kthread.o kcl_io.o + kcl_kthread.o kcl_io.o kcl_perf_event.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c b/drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c new file mode 100644 index 0000000000000..8c7914b6ff67d --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Performance events core code: + * + * Copyright (C) 2008 Thomas Gleixner + * Copyright (C) 2008-2011 Red Hat, Inc., Ingo Molnar + * Copyright (C) 2008-2011 Red Hat, Inc., Peter Zijlstra + * Copyright © 2009 Paul Mackerras, IBM Corp. + */ +#include + +#if !defined(HAVE_PERF_EVENT_UPDATE_USERPAGE) +void (*_kcl_perf_event_update_userpage)(struct perf_event *event); +EXPORT_SYMBOL(_kcl_perf_event_update_userpage); +#endif + +void amdkcl_perf_event_init(void) +{ +#if !defined(HAVE_PERF_EVENT_UPDATE_USERPAGE) + _kcl_perf_event_update_userpage = amdkcl_fp_setup("perf_event_update_userpage", NULL); +#endif +} + diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index f28ee41f10753..fcffe927688b7 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -5,12 +5,14 @@ extern void amdkcl_symbol_init(void); extern void amdkcl_io_init(void); extern void amdkcl_kthread_init(void); +extern void amdkcl_perf_event_init(void); int __init amdkcl_init(void) { amdkcl_symbol_init(); amdkcl_io_init(); amdkcl_kthread_init(); + amdkcl_perf_event_init(); return 0; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 596f6f5fccf5b..cd7d1737e3114 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -17,5 +17,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6f58d726463df..c5f26561583d5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -21,6 +21,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LIST_IS_FIRST AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS + AC_AMDGPU_PERF_EVENT_UPDATE_USERPAGE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/perf-event-update-userpage.m4 b/drivers/gpu/drm/amd/dkms/m4/perf-event-update-userpage.m4 new file mode 100644 index 0000000000000..bf52b37b31d84 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/perf-event-update-userpage.m4 @@ -0,0 +1,14 @@ +dnl # +dnl # commit v4.15-rc3-1-g82975c46da82 +dnl # perf: Export perf_event_update_userpage +dnl # Export perf_event_update_userpage() so that PMU driver using them, +dnl # can be built as modules +dnl # +AC_DEFUN([AC_AMDGPU_PERF_EVENT_UPDATE_USERPAGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([perf_event_update_userpage],[kernel/events/core.c],[ + AC_DEFINE(HAVE_PERF_EVENT_UPDATE_USERPAGE, 1, + [perf_event_update_userpage() is exported]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_perf_event_backport.h b/include/kcl/backport/kcl_perf_event_backport.h new file mode 100644 index 0000000000000..41f336d7039a7 --- /dev/null +++ b/include/kcl/backport/kcl_perf_event_backport.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMD_KCL_PERF_EVENT_BACKPORT_H +#define AMD_KCL_PERF_EVENT_BACKPORT_H +#include +#include + +#if !defined(HAVE_PERF_EVENT_UPDATE_USERPAGE) +#define perf_event_update_userpage _kcl_perf_event_update_userpage +#endif +#endif diff --git a/include/kcl/kcl_perf_event.h b/include/kcl/kcl_perf_event.h new file mode 100644 index 0000000000000..b22cbc296b484 --- /dev/null +++ b/include/kcl/kcl_perf_event.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Performance events: + * + * Copyright (C) 2008-2009, Thomas Gleixner + * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar + * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra + * + * Data type definitions, declarations, prototypes. + * + * Started by: Thomas Gleixner and Ingo Molnar + * + * For licencing details see kernel-base/COPYING + */ +#ifndef AMD_KCL_PERF_EVENT_H +#define AMD_KCL_PERF_EVENT_H +#include + +#if !defined(HAVE_PERF_EVENT_UPDATE_USERPAGE) +extern void (*_kcl_perf_event_update_userpage)(struct perf_event *event); +#endif +#endif From 0f6980e0026a2af90f15ced8f7228c9849198873 Mon Sep 17 00:00:00 2001 From: changzhu Date: Thu, 6 Jun 2019 14:09:09 +0800 Subject: [PATCH 0154/2653] drm/amdkcl: check whether DEFINE_SHOW_ATTRIBUTE is available [Why] DEFINE_SHOW_ATTRIBUTE is not defined until kernel version(4,16,0).So there is build error when using DEFINE_SHOW_ATTRIBUTE before kernel version(4,16,0). This kcl patch is for patch: drm/amd/display: Add connector debugfs for "output_bpc" [How] Supply the definition of DEFINE_SHOW_ATTRIBUTE before kernel version(4.16.0) Change-Id: I2211b55c64e89d0cd17f746ac6b6cf581f42420d Signed-off-by: changzhu Reviewed-by: Kevin Wang Signed-off-by: Jack Gui Signed-off-by: Flora Cui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_seq_file.h | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 include/kcl/kcl_seq_file.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index cd7d1737e3114..6321179c56ac6 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -18,5 +18,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_seq_file.h b/include/kcl/kcl_seq_file.h new file mode 100644 index 0000000000000..4e7750f341705 --- /dev/null +++ b/include/kcl/kcl_seq_file.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_SEQ_FILE_H +#define AMDKCL_SEQ_FILE_H + +#ifndef DEFINE_SHOW_ATTRIBUTE +#define DEFINE_SHOW_ATTRIBUTE(__name) \ +static int __name ## _open(struct inode *inode, struct file *file) \ +{ \ + return single_open(file, __name ## _show, inode->i_private); \ +} \ + \ +static const struct file_operations __name ## _fops = { \ + .owner = THIS_MODULE, \ + .open = __name ## _open, \ + .read = seq_read, \ + .llseek = seq_lseek, \ + .release = single_release, \ +} +#endif + +#endif From b6d0b17aa8c2289633a31b803167cbbd8dfa7844 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Fri, 11 Oct 2019 18:06:11 +0800 Subject: [PATCH 0155/2653] drm/amdkcl: check whether in_task() is available Signed-off-by: Chengming Gui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_preempt.h | 56 +++++++++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 include/kcl/kcl_preempt.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6321179c56ac6..3ddc21414e365 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -19,5 +19,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_preempt.h b/include/kcl/kcl_preempt.h new file mode 100644 index 0000000000000..d76961463a6e3 --- /dev/null +++ b/include/kcl/kcl_preempt.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_PREEMPT_H +#define AMDKCL_PREEMPT_H +#include + +#ifndef in_task +#ifndef PREEMPT_BITS +/* + * We put the hardirq and softirq counter into the preemption + * counter. The bitmask has the following meaning: + * + * - bits 0-7 are the preemption count (max preemption depth: 256) + * - bits 8-15 are the softirq count (max # of softirqs: 256) + * + * The hardirq count could in theory be the same as the number of + * interrupts in the system, but we run all interrupt handlers with + * interrupts disabled, so we cannot have nesting interrupts. Though + * there are a few palaeontologic drivers which reenable interrupts in + * the handler, so we need more than one bit here. + * + * PREEMPT_MASK: 0x000000ff + * SOFTIRQ_MASK: 0x0000ff00 + * HARDIRQ_MASK: 0x000f0000 + * NMI_MASK: 0x00100000 + * PREEMPT_NEED_RESCHED: 0x80000000 + */ +#define PREEMPT_BITS 8 +#define SOFTIRQ_BITS 8 +#define HARDIRQ_BITS 4 +#define NMI_BITS 1 + +#define PREEMPT_SHIFT 0 +#define SOFTIRQ_SHIFT (PREEMPT_SHIFT + PREEMPT_BITS) +#define HARDIRQ_SHIFT (SOFTIRQ_SHIFT + SOFTIRQ_BITS) +#define NMI_SHIFT (HARDIRQ_SHIFT + HARDIRQ_BITS) + +#define __IRQ_MASK(x) ((1UL << (x))-1) + +#define PREEMPT_MASK (__IRQ_MASK(PREEMPT_BITS) << PREEMPT_SHIFT) +#define SOFTIRQ_MASK (__IRQ_MASK(SOFTIRQ_BITS) << SOFTIRQ_SHIFT) +#define HARDIRQ_MASK (__IRQ_MASK(HARDIRQ_BITS) << HARDIRQ_SHIFT) +#define NMI_MASK (__IRQ_MASK(NMI_BITS) << NMI_SHIFT) + +#define PREEMPT_OFFSET (1UL << PREEMPT_SHIFT) +#define SOFTIRQ_OFFSET (1UL << SOFTIRQ_SHIFT) +#define HARDIRQ_OFFSET (1UL << HARDIRQ_SHIFT) +#define NMI_OFFSET (1UL << NMI_SHIFT) + +#define SOFTIRQ_DISABLE_OFFSET (2 * SOFTIRQ_OFFSET) +#endif + +#define in_task() (!(preempt_count() & \ + (NMI_MASK | HARDIRQ_MASK | SOFTIRQ_OFFSET))) +#endif + +#endif /* AMDKCL_PREEMPT_H */ From 478409ea4c8fe6aa34e8ffdf66f1ee0023aa96c9 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Mon, 9 Sep 2019 16:26:20 +0800 Subject: [PATCH 0156/2653] drm/amdkcl: Test whether ksys_sync_helper() is available ksys_sync_helper() is used in commit: b17092bf14111fa1a35acd3b70ca72b3209a4abe dmr/amdgpu: Add system auto reboot to RAS. ksys_sync_helper() function is introduced in kernel 5.1-rc3 (b5dee3130bb40) in "kernel/power/main.c" which calls to ksys_sync() to do a filesystem sync. ksys_sync() is a helper function for sync() syscall which was refactored in kernel 4.16-rc5 (70f68ee81e2e) in "fs/sync.c". v2: drm/amd/autoconf: Fix typo and optimize ksys_sync_helper() v3: drm/amd/autoconf: Fix sys_sync() is not found after ksys_sync() exists v4: drm/amdkcl: fix test for ksys_sync() v5: drm/amdkcl: fix test for ksys_sync_helper Change-Id: I779764f65e6b6480c2067e2d817eef2f1cbf8482 Signed-off-by: Adam Yang Reviewed-by: Flora Cui Acked-by: Feifei Xu / Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_suspend.c | 51 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/ksys_sync_helper.m4 | 16 ++++++ include/kcl/kcl_suspend.h | 17 +++++++ 8 files changed, 91 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_suspend.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/ksys_sync_helper.m4 create mode 100644 include/kcl/kcl_suspend.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 6f93473436bed..682b855d9f53a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 849d86edbb6ad..f76901fb1b532 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -3,7 +3,8 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ - kcl_kthread.o kcl_io.o kcl_perf_event.o + kcl_kthread.o kcl_io.o kcl_perf_event.o \ + kcl_suspend.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c b/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c new file mode 100644 index 0000000000000..c7f1086ebabd3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * kernel/power/main.c - PM subsystem core functionality. + * + * Copyright (c) 2003 Patrick Mochel + * Copyright (c) 2003 Open Source Development Lab + */ +#include +#include + +#ifndef HAVE_KSYS_SYNC_HELPER +/* Copied from kernel/power/main.c */ +#ifdef CONFIG_PM_SLEEP +long (*_kcl_ksys_sync)(void); + +void _kcl_ksys_sync_helper(void) +{ + pr_info("Syncing filesystems ... "); + _kcl_ksys_sync(); + pr_cont("done.\n"); +} +EXPORT_SYMBOL(_kcl_ksys_sync_helper); + +static bool _kcl_sys_sync_stub(void) +{ + pr_warn_once("kernel symbol [k]sys_sync not found!\n"); + return false; +} +#endif /* CONFIG_PM_SLEEP */ +#endif /* HAVE_KSYS_SYNC_HELPER */ + +void amdkcl_suspend_init(void) +{ +#ifndef HAVE_KSYS_SYNC_HELPER +#ifdef CONFIG_PM_SLEEP + _kcl_ksys_sync = amdkcl_fp_setup("ksys_sync", _kcl_sys_sync_stub); + if (_kcl_ksys_sync != _kcl_sys_sync_stub) { + return; + } + + _kcl_ksys_sync = amdkcl_fp_setup("sys_sync", _kcl_sys_sync_stub); + if (_kcl_ksys_sync != _kcl_sys_sync_stub) { + return; + } + + pr_err_once("Error: fail to get symbol [k]sys_sync!\n"); + BUG(); +#endif /* CONFIG_PM_SLEEP */ +#endif /* HAVE_KSYS_SYNC_HELPER */ +} + diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index fcffe927688b7..47f9a9f4d3099 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -6,6 +6,7 @@ extern void amdkcl_symbol_init(void); extern void amdkcl_io_init(void); extern void amdkcl_kthread_init(void); extern void amdkcl_perf_event_init(void); +extern void amdkcl_suspend_init(void); int __init amdkcl_init(void) { @@ -13,6 +14,7 @@ int __init amdkcl_init(void) amdkcl_io_init(); amdkcl_kthread_init(); amdkcl_perf_event_init(); + amdkcl_suspend_init(); return 0; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 3ddc21414e365..1c4017c8d899c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -20,5 +20,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c5f26561583d5..442e52a5bac1d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -22,6 +22,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS AC_AMDGPU_PERF_EVENT_UPDATE_USERPAGE + AC_AMDGPU_KSYS_SYNC_HELPER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/ksys_sync_helper.m4 b/drivers/gpu/drm/amd/dkms/m4/ksys_sync_helper.m4 new file mode 100644 index 0000000000000..039aafc937e0c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ksys_sync_helper.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit b5dee3130bb4014511f5d0dd46855ed843e3fdc8 +dnl # PM / sleep: Refactor filesystems sync to reduce duplication +dnl # +AC_DEFUN([AC_AMDGPU_KSYS_SYNC_HELPER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ksys_sync_helper(); + ], [ + AC_DEFINE(HAVE_KSYS_SYNC_HELPER, 1, + [ksys_sync_helper() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_suspend.h b/include/kcl/kcl_suspend.h new file mode 100644 index 0000000000000..37a3cab923aa5 --- /dev/null +++ b/include/kcl/kcl_suspend.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_SUSPEND_H +#define AMDKCL_SUSPEND_H + +#ifndef HAVE_KSYS_SYNC_HELPER +#ifdef CONFIG_PM_SLEEP +extern void _kcl_ksys_sync_helper(void); + +static inline void ksys_sync_helper(void) +{ + _kcl_ksys_sync_helper(); +} +#else +static inline void ksys_sync_helper(void) {} +#endif /* CONFIG_PM_SLEEP */ +#endif /* HAVE_KSYS_SYNC_HELPER */ +#endif /* AMDKCL_SUSPEND_H */ From a876edad8452cbad1ec0916b847b19f14563e362 Mon Sep 17 00:00:00 2001 From: tianci yin Date: Thu, 29 Nov 2018 13:14:08 +0800 Subject: [PATCH 0157/2653] drm/amdkcl: Test whether pcie_get_{speed/width}_cap() are available v2: drm/amdkcl: [4.18] fix pcie speed and width relevant build err v3: drm/amdkcl: [4.17] fix pcie_get_speed_cap and pcie_get_width_cap v4: drm/amdkcl: refactor HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP v5: drm/amdkcl: drop kcl_pcie_get_speed_cap Signed-off-by: Slava Grigorev Reviewed-by:Kevin Wang Signed-off-by: Tianci Yin Signed-off-by: Jack Gui Signed-off-by: changzhu Reviewed-by: Junwei Zhang Signed-off-by: Flora Cui Acked-by: Feifei Xu drm/amdkcl: update check for pcie_get_{speed,width}_cap check symbols exported is enough Change-Id: I13b0ecc561a5651af73e22b7294d93eb629062df Signed-off-by: Flora Cui Acked-by: Feifei Xu drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 99 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/pcie-get-speed-width-cap.m4 | 12 +++ include/kcl/backport/kcl_pci_backport.h | 12 +++ include/kcl/kcl_pci.h | 52 ++++++++++ 8 files changed, 180 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_pci.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 create mode 100644 include/kcl/backport/kcl_pci_backport.h create mode 100644 include/kcl/kcl_pci.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index f76901fb1b532..970c396afa2ca 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -4,7 +4,7 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o \ - kcl_suspend.o + kcl_suspend.o kcl_pci.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c new file mode 100644 index 0000000000000..3068db5234542 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCI Bus Services, see include/linux/pci.h for further explanation. + * + * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, + * David Mosberger-Tang + * + * Copyright 1997 -- 2000 Martin Mares + * For codes copied from drivers/pci/pci.c + * + * (C) Copyright 2002-2004 Greg Kroah-Hartman + * (C) Copyright 2002-2004 IBM Corp. + * (C) Copyright 2003 Matthew Wilcox + * (C) Copyright 2003 Hewlett-Packard + * (C) Copyright 2004 Jon Smirl + * (C) Copyright 2004 Silicon Graphics, Inc. Jesse Barnes + * For codes copied from drivers/pci/pci-sysfs.c + */ + +#include +#include + +#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) +/* + * pcie_get_speed_cap - query for the PCI device's link speed capability + * @dev: PCI device to query + * + * Query the PCI device speed capability. Return the maximum link speed + * supported by the device. + */ +enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) +{ + u32 lnkcap2, lnkcap; + + /* + * PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link + * Speeds Vector in Link Capabilities 2 when supported, falling + * back to Max Link Speed in Link Capabilities otherwise. + */ + pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); + if (lnkcap2) { /* PCIe r3.0-compliant */ + if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) + return PCIE_SPEED_16_0GT; + else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) + return PCIE_SPEED_8_0GT; + else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) + return PCIE_SPEED_5_0GT; + else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) + return PCIE_SPEED_2_5GT; + return PCI_SPEED_UNKNOWN; + } + + pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); + if (lnkcap) { + if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) + return PCIE_SPEED_16_0GT; + else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) + return PCIE_SPEED_8_0GT; + else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) + return PCIE_SPEED_5_0GT; + else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) + return PCIE_SPEED_2_5GT; + } + + return PCI_SPEED_UNKNOWN; +} + +/** + * pcie_get_width_cap - query for the PCI device's link width capability + * @dev: PCI device to query + * + * Query the PCI device width capability. Return the maximum link width + * supported by the device. + */ +enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev) +{ + u32 lnkcap; + + pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); + if (lnkcap) + return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; + + return PCIE_LNK_WIDTH_UNKNOWN; +} +#endif + +enum pci_bus_speed (*_kcl_pcie_get_speed_cap)(struct pci_dev *dev); +EXPORT_SYMBOL(_kcl_pcie_get_speed_cap); + +enum pcie_link_width (*_kcl_pcie_get_width_cap)(struct pci_dev *dev); +EXPORT_SYMBOL(_kcl_pcie_get_width_cap); + +void amdkcl_pci_init(void) +{ +#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) + _kcl_pcie_get_speed_cap = amdkcl_fp_setup("pcie_get_speed_cap", pcie_get_speed_cap); + _kcl_pcie_get_width_cap = amdkcl_fp_setup("pcie_get_width_cap", pcie_get_width_cap); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 47f9a9f4d3099..74bc8cf250e36 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -6,6 +6,7 @@ extern void amdkcl_symbol_init(void); extern void amdkcl_io_init(void); extern void amdkcl_kthread_init(void); extern void amdkcl_perf_event_init(void); +extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); int __init amdkcl_init(void) @@ -14,6 +15,7 @@ int __init amdkcl_init(void) amdkcl_io_init(); amdkcl_kthread_init(); amdkcl_perf_event_init(); + amdkcl_pci_init(); amdkcl_suspend_init(); return 0; diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1c4017c8d899c..070fd090c2313 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -21,5 +21,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 442e52a5bac1d..14ca3b10a47cf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -23,6 +23,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS AC_AMDGPU_PERF_EVENT_UPDATE_USERPAGE AC_AMDGPU_KSYS_SYNC_HELPER + AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 b/drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 new file mode 100644 index 0000000000000..905b62bc15628 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 @@ -0,0 +1,12 @@ +dnl # +dnl # commit 576c7218a1546e0153480b208b125509cec71470 +dnl # PCI: Export pcie_get_speed_cap and pcie_get_width_cap +dnl # +AC_DEFUN([AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([pcie_get_speed_cap pcie_get_width_cap], [drivers/pci/pci.c], [ + AC_DEFINE(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP, 1, + [pcie_get_speed_cap() and pcie_get_width_cap() exist]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_pci_backport.h b/include/kcl/backport/kcl_pci_backport.h new file mode 100644 index 0000000000000..cc2af255e21b5 --- /dev/null +++ b/include/kcl/backport/kcl_pci_backport.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_PCI_BACKPORT_H +#define AMDKCL_PCI_BACKPORT_H + +#include +#include +#include + +#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) +#define pcie_get_speed_cap _kcl_pcie_get_speed_cap +#endif +#endif diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h new file mode 100644 index 0000000000000..f6f8425cea3b6 --- /dev/null +++ b/include/kcl/kcl_pci.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * pci.h + * + * PCI defines and function prototypes + * Copyright 1994, Drew Eckhardt + * Copyright 1997--1999 Martin Mares + * + * PCI Express ASPM defines and function prototypes + * Copyright (c) 2007 Intel Corp. + * Zhang Yanmin (yanmin.zhang@intel.com) + * Shaohua Li (shaohua.li@intel.com) + * + * For more information, please consult the following manuals (look at + * http://www.pcisig.com/ for how to get them): + * + * PCI BIOS Specification + * PCI Local Bus Specification + * PCI to PCI Bridge Specification + * PCI Express Specification + * PCI System Design Guide + */ +#ifndef AMDKCL_PCI_H +#define AMDKCL_PCI_H + +#include +#include + +#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) +extern enum pci_bus_speed (*_kcl_pcie_get_speed_cap)(struct pci_dev *dev); +extern enum pcie_link_width (*_kcl_pcie_get_width_cap)(struct pci_dev *dev); +#endif + +static inline enum pci_bus_speed kcl_pcie_get_speed_cap(struct pci_dev *dev) +{ +#if defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) + return pcie_get_speed_cap(dev); +#else + return _kcl_pcie_get_speed_cap(dev); +#endif +} + +static inline enum pcie_link_width kcl_pcie_get_width_cap(struct pci_dev *dev) +{ +#if defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) + return pcie_get_width_cap(dev); +#else + return _kcl_pcie_get_width_cap(dev); +#endif +} + +#endif /* AMDKCL_PCI_H */ From 01975d190eca19be571c0c4a32ef93ca84fdcff0 Mon Sep 17 00:00:00 2001 From: tianci yin Date: Thu, 20 Dec 2018 10:40:10 +0800 Subject: [PATCH 0158/2653] drm/amdkcl: Test whether ktime_get_{ns/boottime_ns}() is available drm/amdkcl: [3.17] add kcl for ktime_get_ns [why] Below commit introduce the reference to ktime_to_ns, that is not defined on linux version < 3.17, so implement it here. drm/amd/display: Use div_u64 for flip timestamp ns to ms Reviewed-by: Prike Liang Signed-off-by: Tianci Yin Signed-off-by: Jack Gui drm/amd/autoconf: Test whether ktime_get_ns() is available ktime_get_ns introduced by kernel v3.17-rc1~109^2~41 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: test whether ktime_get_boottime_ns() is available Signed-off-by: Flora Cui Reviewed-by: Jack Gui Signed-off-by: Jack Gui drm/amdkcl: refactor ktime_xxx in kcl Signed-off-by: Flora Cui Reviewed-by: Jack Gui Signed-off-by: Jack Gui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/ktime-get-boottime-ns.m4 | 32 +++++++++++++++++++ include/kcl/kcl_timekeeping.h | 30 +++++++++++++++++ 4 files changed, 64 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ktime-get-boottime-ns.m4 create mode 100644 include/kcl/kcl_timekeeping.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 070fd090c2313..6b31d63564d30 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -22,5 +22,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 14ca3b10a47cf..4ded23a9914a8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -24,6 +24,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PERF_EVENT_UPDATE_USERPAGE AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP + AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-get-boottime-ns.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-get-boottime-ns.m4 new file mode 100644 index 0000000000000..234ef7efa54b4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ktime-get-boottime-ns.m4 @@ -0,0 +1,32 @@ +dnl # +dnl # commit v5.2-rc5-8-g9285ec4c8b61 +dnl # timekeeping: Use proper clock specifier names in functions +dnl # +AC_DEFUN([AC_AMDGPU_KTIME_GET_BOOTTIME_NS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_get_boottime_ns(); + ], [ + AC_DEFINE(HAVE_KTIME_GET_BOOTTIME_NS, 1, + [ktime_get_boottime_ns() is available]) + AC_DEFINE(HAVE_KTIME_GET_NS, 1, + [ktime_get_ns is available]) + ],[ + dnl # + dnl # commit v3.16-rc5-76-g897994e32b2b + dnl # timekeeping: Provide ktime_get[*]_ns() helpers + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + ktime_get_ns(); + ], [ + AC_DEFINE(HAVE_KTIME_GET_NS, 1, + [ktime_get_ns is available]) + ]) + ]) + ]) +]) diff --git a/include/kcl/kcl_timekeeping.h b/include/kcl/kcl_timekeeping.h new file mode 100644 index 0000000000000..cddc7d78548af --- /dev/null +++ b/include/kcl/kcl_timekeeping.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_LINUX_TIMEKEEPING_H +#define _KCL_LINUX_TIMEKEEPING_H +#include + +#ifndef HAVE_KTIME_GET_NS +static inline u64 ktime_get_ns(void) +{ + return ktime_to_ns(ktime_get()); +} +#endif + +#if !defined(HAVE_KTIME_GET_BOOTTIME_NS) +#if defined(HAVE_KTIME_GET_NS) +static inline u64 ktime_get_boottime_ns(void) +{ + return ktime_get_boot_ns(); +} +#else +static inline u64 ktime_get_boottime_ns(void) +{ + struct timespec time; + + get_monotonic_boottime(&time); + return (u64)timespec_to_ns(&time); +} +#endif /* HAVE_KTIME_GET_NS */ +#endif /* HAVE_KTIME_GET_BOOTTIME_NS */ + +#endif From 2cf5ef7b4973c291b61dae862dffa90aadcbc4dc Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 24 Aug 2020 15:35:12 +0800 Subject: [PATCH 0159/2653] drm/amdkcl: add kcl copy of untagged_addr Signed-off-by: Flora Cui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_mm.h | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 include/kcl/kcl_mm.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6b31d63564d30..e8f422617b83d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -23,5 +23,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h new file mode 100644 index 0000000000000..f300ba76bf794 --- /dev/null +++ b/include/kcl/kcl_mm.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * linux/ipc/util.c + * Copyright (C) 1992 Krishna Balasubramanian + * For kvmalloc/kvzalloc + */ +#ifndef AMDKCL_MM_H +#define AMDKCL_MM_H + +#include + +#ifndef untagged_addr +/* Copied from include/linux/mm.h */ +#define untagged_addr(addr) (addr) +#endif + +#endif /* AMDKCL_MM_H */ From f49d5a82ad12faff5f0907e5c3a476e417d0ef3f Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Mon, 18 Feb 2019 11:00:12 +0800 Subject: [PATCH 0160/2653] drm/amdkcl: Test whether mm_access is available v1: 183d99136d50 - drm/amdkcl: add kcl mm_access funtions v2: 1ef72c2b349f - drm/amd/autoconf: Test whether mm_access is available Signed-off-by: Kevin Wang Reviewed-by: Junwei Zhang Reviewed-by: Felix Kuehling Reviewed-by: Harish Kasiviswanathan Signed-off-by: Chengming Gui Reviewed-by: Flora Cui drm/amdkcl: refactor mm_access() check Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui drm/amdkcl: drop kcl_mm_access Signed-off-by: Flora Cui Acked-by: Feifei Xu Signed-off-by: Flora Cui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 11 +++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 ++ drivers/gpu/drm/amd/backport/backport.h | 2 +- include/kcl/backport/kcl_mm_backport.h | 8 ++++++++ 5 files changed, 23 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_mm.c create mode 100644 include/kcl/backport/kcl_mm_backport.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 970c396afa2ca..d0d3996bbc5e6 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -4,7 +4,7 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o \ - kcl_suspend.o kcl_pci.o + kcl_suspend.o kcl_pci.o kcl_mm.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c new file mode 100644 index 0000000000000..e60ac00cba573 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/kernel/fork.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ +#include + +void amdkcl_mm_init(void) +{ +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 74bc8cf250e36..178c0b724cc9e 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -5,6 +5,7 @@ extern void amdkcl_symbol_init(void); extern void amdkcl_io_init(void); extern void amdkcl_kthread_init(void); +extern void amdkcl_mm_init(void); extern void amdkcl_perf_event_init(void); extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); @@ -14,6 +15,7 @@ int __init amdkcl_init(void) amdkcl_symbol_init(); amdkcl_io_init(); amdkcl_kthread_init(); + amdkcl_mm_init(); amdkcl_perf_event_init(); amdkcl_pci_init(); amdkcl_suspend_init(); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e8f422617b83d..d69a6c2b59c46 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -23,6 +23,6 @@ #include #include #include -#include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/backport/kcl_mm_backport.h b/include/kcl/backport/kcl_mm_backport.h new file mode 100644 index 0000000000000..055945c8728ef --- /dev/null +++ b/include/kcl/backport/kcl_mm_backport.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_MM_BACKPORT_H +#define AMDKCL_MM_BACKPORT_H +#include +#include +#include + +#endif From 60dd677d2cb19fb34a5591a49e508ccfb8dc6894 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Mon, 23 Sep 2019 19:59:17 +0800 Subject: [PATCH 0161/2653] drm/amdkcl: Test whether mmu_notifier_range_blockable() is available v2: drm/amdkcl: refactor kcl copy of mmu_notifier_range_blockable v3: drm/amdkcl: refactor kcl copy of mmu_notifier_range_blockable Signed-off-by: Adam Yang Signed-off-by: Flora Cui Signed-off-by: Jack Gui Reviewed-by: Yifan Zhang drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/mmu-notifier.m4 | 16 +++++++++++++ include/kcl/kcl_mmu_notifier.h | 25 +++++++++++++++++++++ 4 files changed, 43 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mmu-notifier.m4 create mode 100644 include/kcl/kcl_mmu_notifier.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index d69a6c2b59c46..461f8acef66e4 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4ded23a9914a8..03e7884a96ae3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -25,6 +25,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_AMDGPU_KTIME_GET_BOOTTIME_NS + AC_AMDGPU_MMU_NOTIFIER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/mmu-notifier.m4 b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier.m4 new file mode 100644 index 0000000000000..06742541fd0d9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 4a83bfe916f3d2100df5bc8389bd182a537ced3e +dnl # mm/mmu_notifier: helper to test if a range invalidation is blockable +dnl # +AC_DEFUN([AC_AMDGPU_MMU_NOTIFIER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + mmu_notifier_range_blockable(NULL); + ], [ + AC_DEFINE(HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE, 1, + [mmu_notifier_range_blockable() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mmu_notifier.h b/include/kcl/kcl_mmu_notifier.h new file mode 100644 index 0000000000000..1af9433bdbfe5 --- /dev/null +++ b/include/kcl/kcl_mmu_notifier.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_MMU_NOTIFIER_H +#define AMDKCL_MMU_NOTIFIER_H + +#include + +#if !defined(HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE) && \ + defined(HAVE_2ARGS_INVALIDATE_RANGE_START) +/* Copied from v5.1-10225-g4a83bfe916f3 include/linux/mmu_notifier.h */ +#ifdef CONFIG_MMU_NOTIFIER +static inline bool +mmu_notifier_range_blockable(const struct mmu_notifier_range *range) +{ + return range->blockable; +} +#else +static inline bool +mmu_notifier_range_blockable(const struct mmu_notifier_range *range) +{ + return true; +} +#endif +#endif /* HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE */ + +#endif /* AMDKCL_MMU_NOTIFIER_H */ From 1e306af2420a2bcc6ddf187ceb8f6caf561eaea6 Mon Sep 17 00:00:00 2001 From: Anatoli Antonovitch Date: Wed, 9 Jan 2019 14:52:55 -0500 Subject: [PATCH 0162/2653] drm/amdkcl: Test whether release_pages() wants 2 args Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: drop HAVE_2ARGS_MM_RELEASE_PAGES check in amdgpu Signed-off-by: Flora Cui Acked-by: Feifei Xu drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/mm-release-pages.m4 | 19 +++++++++++++++++++ include/kcl/kcl_pagemap.h | 14 ++++++++++++++ 4 files changed, 35 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mm-release-pages.m4 create mode 100644 include/kcl/kcl_pagemap.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 461f8acef66e4..dbc09bd4e19ec 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -25,5 +25,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 03e7884a96ae3..54f143f96c573 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -26,6 +26,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_MMU_NOTIFIER + AC_AMDGPU_MM_RELEASE_PAGES AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/mm-release-pages.m4 b/drivers/gpu/drm/amd/dkms/m4/mm-release-pages.m4 new file mode 100644 index 0000000000000..7db093a925e04 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mm-release-pages.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit c6f92f9fbe7dbcc8903a67229aa88b4077ae4422 +dnl # mm: remove cold parameter for release_pages +dnl # +AC_DEFUN([AC_AMDGPU_MM_RELEASE_PAGES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct page **pages = NULL; + int nr = 0; + + release_pages(pages, nr); + ], [release_pages], [mm/swap.c], [ + AC_DEFINE(HAVE_MM_RELEASE_PAGES_2ARGS, 1, + [release_pages() wants 2 args]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pagemap.h b/include/kcl/kcl_pagemap.h new file mode 100644 index 0000000000000..f95a11d945ebc --- /dev/null +++ b/include/kcl/kcl_pagemap.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_PAGEMAP_H +#define AMDKCL_PAGEMAP_H + +#include + +#ifndef HAVE_MM_RELEASE_PAGES_2ARGS +static inline void _kcl_release_pages(struct page **pages, int nr) +{ + release_pages(pages, nr, 0); +} +#define release_pages _kcl_release_pages +#endif +#endif From 48c79f9ed2dc55c8c3a32a9808fa72a4a252375b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 27 Aug 2020 16:23:54 +0800 Subject: [PATCH 0163/2653] drm/amdkcl: add kcl copy of DPM_FLAG_NO_DIRECT_COMPLETE Signed-off-by: Flora Cui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_pm.h | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 include/kcl/kcl_pm.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index dbc09bd4e19ec..99c0e0097a95b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -26,5 +26,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_pm.h b/include/kcl/kcl_pm.h new file mode 100644 index 0000000000000..157fc65f14708 --- /dev/null +++ b/include/kcl/kcl_pm.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * pm.h - Power management interface + * + * Copyright (C) 2000 Andrew Henroid + */ +#ifndef KCL_KCL_PM_H +#define KCL_KCL_PM_H + +#include + +/* + * v5.7-rc2-7-ge07515563d01 + * PM: sleep: core: Rename DPM_FLAG_NEVER_SKIP + */ +#ifndef DPM_FLAG_NO_DIRECT_COMPLETE +#define DPM_FLAG_NO_DIRECT_COMPLETE DPM_FLAG_NEVER_SKIP +#endif + +#endif From 3f270224d1d431e133b27132771adb898e31997e Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Mon, 13 Apr 2020 16:51:26 +0800 Subject: [PATCH 0164/2653] drm/amdkcl: add AC_AMDGPU_DMA_FENCE_HEADERS it is a squash of: commit e1d2e9c077849c7aa9732709870762117e6c435a Author: Slava Grigorev Date: Tue Feb 25 21:30:21 2020 -0500 drm/amdkcl: Fix in-tree build if locate of output files (O=) specified Signed-off-by: Slava Grigorev commit 671508e545e8b7e6fda2209dfb2aae21e9b7ae54 Author: Slava Grigorev Date: Thu Feb 20 15:57:12 2020 -0500 drm/amdkcl: drop AC_KERNEL_TEST_HEADER_FILE_EXIST macro remove AC_KERNEL_TEST_HEADER_FILE_EXIST macro from AC_AMDGPU_DRM_DEV_SUPPORTED test Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui commit 5ebd41454f8a12b84f590c3c68e4333246ce1b53 Author: Slava Grigorev Date: Thu Feb 20 14:55:08 2020 -0500 drm/amdkcl: modify dma-fence-headers test to use AC_KERENEL_CHECK_HERDERS macro Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui commit c1f004d6344bd8c1c04343526b033c2768adfce7 Author: Flora Cui Date: Mon Nov 16 10:46:04 2020 +0800 drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling commit 49e2c50a5557ee4bd46b80c790bcca4db4cd9f3e Author: Ma Jun Date: Tue Feb 7 13:30:10 2023 +0800 drm/amdkcl: kcl-cleanup HAVE_DMA_FENCE_SET_ERROR Change-Id: I596491f1c0408de56017aa069a2211216fb08564 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi commit 42c151d86739eb7be4b3db0ff66f467e6eb1f2ba Author: Ma Jun Date: Tue Feb 7 13:32:58 2023 +0800 drm/amdkcl: kcl-cleanup HAVE_DMA_FENCE_GET_STUB Change-Id: I9ca75886eed67777eb35c3958e763d485a1d9b1f Signed-off-by: Ma Jun Signed-off-by: Flora Cui Change-Id: I2ceeb8dc72f5ed53ebdd507b71faab67c59b56ab Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 244 ++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c | 149 +++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/dkms/m4/dma-fence-headers.m4 | 18 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/scheduler/backport/backport.h | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/backport/kcl_fence_backport.h | 33 +++ include/kcl/kcl_fence.h | 156 +++++++++++ include/kcl/kcl_fence_array.h | 82 ++++++ 12 files changed, 690 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fence.c create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 create mode 100644 include/kcl/backport/kcl_fence_backport.h create mode 100644 include/kcl/kcl_fence.h create mode 100644 include/kcl/kcl_fence_array.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index d0d3996bbc5e6..f705e8bab0e99 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -4,7 +4,8 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o \ - kcl_suspend.o kcl_pci.o kcl_mm.o + kcl_suspend.o kcl_pci.o kcl_mm.o \ + kcl_fence.o kcl_fence_array.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c new file mode 100644 index 0000000000000..c67cae784f75a --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Fence mechanism for dma-buf and to allow for asynchronous dma access + * + * Copyright (C) 2012 Canonical Ltd + * Copyright (C) 2012 Texas Instruments + * + * Authors: + * Rob Clark + * Maarten Lankhorst + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#define CREATE_TRACE_POINTS +#include "kcl_trace.h" + +/* Copied from drivers/dma-buf/dma-fence.c */ +static bool +dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count, + uint32_t *idx) +{ + int i; + + for (i = 0; i < count; ++i) { + struct dma_fence *fence = fences[i]; + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { + if (idx) + *idx = i; + return true; + } + } + return false; +} + +struct default_wait_cb { + struct dma_fence_cb base; + struct task_struct *task; +}; + +static void (*_kcl_fence_default_wait_cb)(struct dma_fence *fence, struct dma_fence_cb *cb); + +#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT +signed long +_kcl_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) +{ + struct default_wait_cb cb; + unsigned long flags; + signed long ret = timeout ? timeout : 1; + bool was_set; + + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) + return ret; + + spin_lock_irqsave(fence->lock, flags); + + if (intr && signal_pending(current)) { + ret = -ERESTARTSYS; + goto out; + } + + was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, + &fence->flags); + + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) + goto out; + + if (!was_set && fence->ops->enable_signaling) { + /* + * Modifications [2017-03-29] (c) [2017] + * Advanced Micro Devices, Inc. + */ + trace_kcl_fence_enable_signal(fence); + + if (!fence->ops->enable_signaling(fence)) { + dma_fence_signal_locked(fence); + goto out; + } + } + + if (!timeout) { + ret = 0; + goto out; + } + + cb.base.func = _kcl_fence_default_wait_cb; + cb.task = current; + list_add(&cb.base.node, &fence->cb_list); + + while (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags) && ret > 0) { + if (intr) + __set_current_state(TASK_INTERRUPTIBLE); + else + __set_current_state(TASK_UNINTERRUPTIBLE); + spin_unlock_irqrestore(fence->lock, flags); + + ret = schedule_timeout(ret); + + spin_lock_irqsave(fence->lock, flags); + if (ret > 0 && intr && signal_pending(current)) + ret = -ERESTARTSYS; + } + + if (!list_empty(&cb.base.node)) + list_del(&cb.base.node); + __set_current_state(TASK_RUNNING); + +out: + spin_unlock_irqrestore(fence->lock, flags); + return ret; +} +EXPORT_SYMBOL(_kcl_fence_default_wait); +#endif + + +/* + * Modifications [2017-09-19] (c) [2017] + * Advanced Micro Devices, Inc. + */ +#ifdef AMDKCL_FENCE_WAIT_ANY_TIMEOUT +signed long +_kcl_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count, + bool intr, signed long timeout, uint32_t *idx) +{ + struct default_wait_cb *cb; + signed long ret = timeout; + unsigned i; + + if (WARN_ON(!fences || !count || timeout < 0)) + return -EINVAL; + + if (timeout == 0) { + for (i = 0; i < count; ++i) + if (dma_fence_is_signaled(fences[i])) { + if (idx) + *idx = i; + return 1; + } + + return 0; + } + + cb = kcalloc(count, sizeof(struct default_wait_cb), GFP_KERNEL); + if (cb == NULL) { + ret = -ENOMEM; + goto err_free_cb; + } + + for (i = 0; i < count; ++i) { + struct dma_fence *fence = fences[i]; + + + cb[i].task = current; + if (dma_fence_add_callback(fence, &cb[i].base, + _kcl_fence_default_wait_cb)) { + /* This fence is already signaled */ + if (idx) + *idx = i; + goto fence_rm_cb; + } + } + + while (ret > 0) { + if (intr) + set_current_state(TASK_INTERRUPTIBLE); + else + set_current_state(TASK_UNINTERRUPTIBLE); + + if (dma_fence_test_signaled_any(fences, count, idx)) + break; + + ret = schedule_timeout(ret); + + if (ret > 0 && intr && signal_pending(current)) + ret = -ERESTARTSYS; + } + + __set_current_state(TASK_RUNNING); + +fence_rm_cb: + while (i-- > 0) + dma_fence_remove_callback(fences[i], &cb[i].base); + +err_free_cb: + kfree(cb); + + return ret; +} +EXPORT_SYMBOL(_kcl_fence_wait_any_timeout); +#endif + +#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT +signed long +_kcl_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) +{ + signed long ret; + + if (WARN_ON(timeout < 0)) + return -EINVAL; + + /* + * Modifications [2017-03-29] (c) [2017] + * Advanced Micro Devices, Inc. + */ + trace_kcl_fence_wait_start(fence); + if (fence->ops->wait) + ret = fence->ops->wait(fence, intr, timeout); + else + ret = _kcl_fence_default_wait(fence, intr, timeout); + trace_kcl_fence_wait_end(fence); + return ret; +} +EXPORT_SYMBOL(_kcl_fence_wait_timeout); +#endif + +#ifdef AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING +bool _kcl_fence_enable_signaling(struct dma_fence *f) +{ + return true; +} +EXPORT_SYMBOL(_kcl_fence_enable_signaling); +#endif +/* + * Modifications [2016-12-23] (c) [2016] + * Advanced Micro Devices, Inc. + */ +void amdkcl_fence_init(void) +{ +#if defined(HAVE_LINUX_DMA_FENCE_H) + _kcl_fence_default_wait_cb = amdkcl_fp_setup("dma_fence_default_wait_cb", NULL); +#else + _kcl_fence_default_wait_cb = amdkcl_fp_setup("fence_default_wait_cb", NULL); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c new file mode 100644 index 0000000000000..d42a986ecfe1d --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * fence-array: aggregate fences to be waited together + * + * Copyright (C) 2016 Collabora Ltd + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * Authors: + * Gustavo Padovan + * Christian König + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include + +#if !defined(HAVE_LINUX_DMA_FENCE_H) && !defined(HAVE_LINUX_FENCE_ARRAY_H) +static void fence_array_cb_func(struct fence *f, struct fence_cb *cb); + +static const char *fence_array_get_driver_name(struct fence *fence) +{ + return "fence_array"; +} + +static const char *fence_array_get_timeline_name(struct fence *fence) +{ + return "unbound"; +} + +static void fence_array_cb_func(struct fence *f, struct fence_cb *cb) +{ + struct fence_array_cb *array_cb = + container_of(cb, struct fence_array_cb, cb); + struct fence_array *array = array_cb->array; + + if (atomic_dec_and_test(&array->num_pending)) + fence_signal(&array->base); + fence_put(&array->base); +} + +static bool fence_array_enable_signaling(struct fence *fence) +{ + struct fence_array *array = to_fence_array(fence); + struct fence_array_cb *cb = (void *)(&array[1]); + unsigned i; + + for (i = 0; i < array->num_fences; ++i) { + cb[i].array = array; + /* + * As we may report that the fence is signaled before all + * callbacks are complete, we need to take an additional + * reference count on the array so that we do not free it too + * early. The core fence handling will only hold the reference + * until we signal the array as complete (but that is now + * insufficient). + */ + fence_get(&array->base); + if (fence_add_callback(array->fences[i], &cb[i].cb, + fence_array_cb_func)) { + fence_put(&array->base); + if (atomic_dec_and_test(&array->num_pending)) + return false; + } + } + + return true; +} + +static bool fence_array_signaled(struct fence *fence) +{ + struct fence_array *array = to_fence_array(fence); + + return atomic_read(&array->num_pending) <= 0; +} + +static void fence_array_release(struct fence *fence) +{ + struct fence_array *array = to_fence_array(fence); + unsigned i; + + for (i = 0; i < array->num_fences; ++i) + fence_put(array->fences[i]); + + kfree(array->fences); + fence_free(fence); +} + +const struct fence_ops fence_array_ops = { + .get_driver_name = fence_array_get_driver_name, + .get_timeline_name = fence_array_get_timeline_name, + .enable_signaling = fence_array_enable_signaling, + .signaled = fence_array_signaled, + .wait = _kcl_fence_default_wait, + .release = fence_array_release, +}; + +/** + * fence_array_create - Create a custom fence array + * @num_fences: [in] number of fences to add in the array + * @fences: [in] array containing the fences + * @context: [in] fence context to use + * @seqno: [in] sequence number to use + * @signal_on_any [in] signal on any fence in the array + * + * Allocate a fence_array object and initialize the base fence with fence_init(). + * In case of error it returns NULL. + * + * The caller should allocte the fences array with num_fences size + * and fill it with the fences it wants to add to the object. Ownership of this + * array is take and fence_put() is used on each fence on release. + * + * If @signal_on_any is true the fence array signals if any fence in the array + * signals, otherwise it signals when all fences in the array signal. + */ +struct fence_array *fence_array_create(int num_fences, struct fence **fences, + u64 context, unsigned seqno, + bool signal_on_any) +{ + struct fence_array *array; + size_t size = sizeof(*array); + + /* Allocate the callback structures behind the array. */ + size += num_fences * sizeof(struct fence_array_cb); + array = kzalloc(size, GFP_KERNEL); + if (!array) + return NULL; + + spin_lock_init(&array->lock); + fence_init(&array->base, &fence_array_ops, &array->lock, + context, seqno); + + array->num_fences = num_fences; + atomic_set(&array->num_pending, signal_on_any ? 1 : num_fences); + array->fences = fences; + + return array; +} +EXPORT_SYMBOL(fence_array_create); + +#endif /* !defined(HAVE_LINUX_DMA_FENCE_H) && !defined(HAVE_LINUX_FENCE_ARRAY_H) */ diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 178c0b724cc9e..cc35e1e0f4385 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -3,6 +3,7 @@ #include extern void amdkcl_symbol_init(void); +extern void amdkcl_fence_init(void); extern void amdkcl_io_init(void); extern void amdkcl_kthread_init(void); extern void amdkcl_mm_init(void); @@ -13,6 +14,7 @@ extern void amdkcl_suspend_init(void); int __init amdkcl_init(void) { amdkcl_symbol_init(); + amdkcl_fence_init(); amdkcl_io_init(); amdkcl_kthread_init(); amdkcl_mm_init(); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 99c0e0097a95b..722e0b7c215e4 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -27,5 +27,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 new file mode 100644 index 0000000000000..843491bfe3aef --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit f54d1867005c3323f5d8ad83eed823e84226c429 +dnl # dma-buf: Rename struct fence to dma_fence +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_HEADERS], [ + AS_IF([test $HAVE_LINUX_DMA_FENCE_H], [ + AC_KERNEL_DO_BACKGROUND([ + ]) + ], [ + dnl # + dnl # commit b3dfbdf261e076a997f812323edfdba84ba80256 + dnl # dma-buf/fence: add fence_array fences v6 + dnl # + AC_KERNEL_CHECK_HEADERS([linux/fence-array.h]) + AC_KERNEL_DO_BACKGROUND([ + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 54f143f96c573..72720629c9637 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -27,6 +27,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES + AC_AMDGPU_DMA_FENCE_HEADERS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 7994c7b3826ac..28b00db43738f 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -4,5 +4,6 @@ #include #include +#include #endif diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 4dbd06d3e8b6c..48f3f3bc56a71 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -6,4 +6,5 @@ #include #include #include +#include #endif diff --git a/include/kcl/backport/kcl_fence_backport.h b/include/kcl/backport/kcl_fence_backport.h new file mode 100644 index 0000000000000..022951286bb7d --- /dev/null +++ b/include/kcl/backport/kcl_fence_backport.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef AMDKCL_FENCE_BACKPORT_H +#define AMDKCL_FENCE_BACKPORT_H +#include + +/* + * commit v4.18-rc2-533-g418cc6ca0607 + * dma-fence: Allow wait_any_timeout for all fences) + */ +#ifdef AMDKCL_FENCE_WAIT_ANY_TIMEOUT +#define dma_fence_wait_any_timeout _kcl_fence_wait_any_timeout +#endif + +/* + * commit v4.9-rc2-472-gbcc004b629d2 + * dma-buf/fence: make timeout handling in fence_default_wait consistent (v2)) + * + * commit v4.9-rc2-473-g698c0f7ff216 + * dma-buf/fence: revert "don't wait when specified timeout is zero" (v2) + */ +#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT +#define dma_fence_default_wait _kcl_fence_default_wait +#define dma_fence_wait_timeout _kcl_fence_wait_timeout +#endif + +/* + * commit v4.14-rc3-601-g5f72db59160c + * dma-buf/fence: Sparse wants __rcu on the object itself + */ +#ifdef AMDKCL_FENCE_GET_RCU_SAFE +#define dma_fence_get_rcu_safe _kcl_fence_get_rcu_safe +#endif +#endif diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h new file mode 100644 index 0000000000000..7a869acf02b93 --- /dev/null +++ b/include/kcl/kcl_fence.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Fence mechanism for dma-buf to allow for asynchronous dma access + * + * Copyright (C) 2012 Canonical Ltd + * Copyright (C) 2012 Texas Instruments + * + * Authors: + * Rob Clark + * Maarten Lankhorst + */ +#ifndef AMDKCL_FENCE_H +#define AMDKCL_FENCE_H + +#include +#include +#if !defined(HAVE_LINUX_DMA_FENCE_H) +#include +#include +#else +#include +#include +#endif + +#if !defined(HAVE_LINUX_DMA_FENCE_H) +#define dma_fence_cb fence_cb +#define dma_fence_ops fence_ops +#define dma_fence_array fence_array +#define dma_fence fence +#define dma_fence_init fence_init +#define dma_fence_context_alloc fence_context_alloc +#define DMA_FENCE_TRACE FENCE_TRACE +#define DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT FENCE_FLAG_ENABLE_SIGNAL_BIT +#define DMA_FENCE_FLAG_SIGNALED_BIT FENCE_FLAG_SIGNALED_BIT +#define dma_fence_wait fence_wait +#define dma_fence_get fence_get +#define dma_fence_put fence_put +#define dma_fence_is_signaled fence_is_signaled +#define dma_fence_signal fence_signal +#define dma_fence_signal_locked fence_signal_locked +#define dma_fence_get_rcu fence_get_rcu +#define dma_fence_array_create fence_array_create +#define dma_fence_add_callback fence_add_callback +#define dma_fence_remove_callback fence_remove_callback +#define dma_fence_enable_sw_signaling fence_enable_sw_signaling +#define dma_fence_default_wait fence_default_wait + +#define dma_fence_set_error fence_set_error +#endif + +/* commit v4.5-rc3-715-gb47bcb93bbf2 + * fall back to HAVE_LINUX_DMA_FENCE_H check directly + * as it's hard to detect the implementation in kernel + */ +#if !defined(HAVE_LINUX_DMA_FENCE_H) +static inline bool dma_fence_is_later(struct dma_fence *f1, struct dma_fence *f2) +{ + if (WARN_ON(f1->context != f2->context)) + return false; + + return (int)(f1->seqno - f2->seqno) > 0; +} +#endif + +/* + * commit v4.18-rc2-533-g418cc6ca0607 + * dma-fence: Allow wait_any_timeout for all fences) + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 19, 0) +#define AMDKCL_FENCE_WAIT_ANY_TIMEOUT +signed long +_kcl_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count, + bool intr, signed long timeout, uint32_t *idx); +#endif + +/* + * commit v4.9-rc2-472-gbcc004b629d2 + * dma-buf/fence: make timeout handling in fence_default_wait consistent (v2)) + * + * commit v4.9-rc2-473-g698c0f7ff216 + * dma-buf/fence: revert "don't wait when specified timeout is zero" (v2) + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 10, 0) +#define AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT +signed long +_kcl_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout); +extern signed long _kcl_fence_wait_timeout(struct fence *fence, bool intr, + signed long timeout); +#endif + +/* + * commit v4.14-rc3-601-g5f72db59160c + * dma-buf/fence: Sparse wants __rcu on the object itself + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 15, 0) +#define AMDKCL_FENCE_GET_RCU_SAFE +static inline struct dma_fence * +_kcl_fence_get_rcu_safe(struct dma_fence __rcu **fencep) +{ + do { + struct dma_fence *fence; + + fence = rcu_dereference(*fencep); + if (!fence) + return NULL; + + if (!dma_fence_get_rcu(fence)) + continue; + + /* The atomic_inc_not_zero() inside dma_fence_get_rcu() + * provides a full memory barrier upon success (such as now). + * This is paired with the write barrier from assigning + * to the __rcu protected fence pointer so that if that + * pointer still matches the current fence, we know we + * have successfully acquire a reference to it. If it no + * longer matches, we are holding a reference to some other + * reallocated pointer. This is possible if the allocator + * is using a freelist like SLAB_TYPESAFE_BY_RCU where the + * fence remains valid for the RCU grace period, but it + * may be reallocated. When using such allocators, we are + * responsible for ensuring the reference we get is to + * the right fence, as below. + */ + if (fence == rcu_access_pointer(*fencep)) + return rcu_pointer_handoff(fence); + + dma_fence_put(fence); + } while (1); +} +#endif + +/* + * commit v4.18-rc2-519-gc701317a3eb8 + * dma-fence: Make ->enable_signaling optional + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 19, 0) +#define AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING +bool _kcl_fence_enable_signaling(struct dma_fence *f); +#define AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL \ + .enable_signaling = _kcl_fence_enable_signaling, +#else +#define AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL +#endif + +/* + * commit v4.18-rc2-533-g418cc6ca0607 + * dma-fence: Make ->wait callback optional + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 19, 0) +#define AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL \ + .wait = dma_fence_default_wait, +#else +#define AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL +#endif + +#endif /* AMDKCL_FENCE_H */ diff --git a/include/kcl/kcl_fence_array.h b/include/kcl/kcl_fence_array.h new file mode 100644 index 0000000000000..8bce1cf8ff00c --- /dev/null +++ b/include/kcl/kcl_fence_array.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * this file is the copy of include/linux/fence-array.h, don't modify it + * + * fence-array: aggregates fence to be waited together + * + * Copyright (C) 2016 Collabora Ltd + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * Authors: + * Gustavo Padovan + * Christian König + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef AMDKCL_FENCE_ARRAY_H +#define AMDKCL_FENCE_ARRAY_H + +#if !defined(HAVE_LINUX_DMA_FENCE_H) +#if defined(HAVE_LINUX_FENCE_ARRAY_H) +#include +#else +#include + +/** + * struct fence_array_cb - callback helper for fence array + * @cb: fence callback structure for signaling + * @array: reference to the parent fence array object + */ +struct fence_array_cb { + struct fence_cb cb; + struct fence_array *array; +}; + +/** + * struct fence_array - fence to represent an array of fences + * @base: fence base class + * @lock: spinlock for fence handling + * @num_fences: number of fences in the array + * @num_pending: fences in the array still pending + * @fences: array of the fences + */ +struct fence_array { + struct fence base; + + spinlock_t lock; + unsigned num_fences; + atomic_t num_pending; + struct fence **fences; +}; + +extern const struct fence_ops fence_array_ops; + +/** + * to_fence_array - cast a fence to a fence_array + * @fence: fence to cast to a fence_array + * + * Returns NULL if the fence is not a fence_array, + * or the fence_array otherwise. + */ +static inline struct fence_array *to_fence_array(struct fence *fence) +{ + if (fence->ops != &fence_array_ops) + return NULL; + + return container_of(fence, struct fence_array, base); +} + +struct fence_array *fence_array_create(int num_fences, struct fence **fences, + u64 context, unsigned seqno, + bool signal_on_any); +#endif +#endif + +#endif /* __LINUX_FENCE_ARRAY_H */ From 38516b71289aa3b2727ebbc0871978d2b5b63151 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Wed, 29 Mar 2017 09:03:10 +0800 Subject: [PATCH 0165/2653] drm/amdkcl: define kcl tracepoints v2: drop legacy kcl_fence_ defines v3: move kcl_trace.h to amdkcl Signed-off-by: Evan Quan Reviewed-by: Junwei Zhang Reviewed-by: Chunming Zhou Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: rename kcl_trace.h to kcl_fence_trace.h to clarify the trace is for kcl_fence Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 + drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h | 72 ++++++++++++++++++++ 3 files changed, 75 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index f705e8bab0e99..97ed40fbccb56 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -7,6 +7,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_suspend.o kcl_pci.o kcl_mm.o \ kcl_fence.o kcl_fence_array.o +CFLAGS_kcl_fence.o := -I$(src) + ccflags-y += \ -include $(src)/../dkms/config/config.h \ -include $(src)/kcl_common.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index c67cae784f75a..ed889c91b8dd4 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -23,7 +23,7 @@ #include #define CREATE_TRACE_POINTS -#include "kcl_trace.h" +#include "kcl_fence_trace.h" /* Copied from drivers/dma-buf/dma-fence.c */ static bool diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h b/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h new file mode 100644 index 0000000000000..7c857ba3c31c0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copied from include/trace/events/dma_fence.h */ +#if !defined(_TRACE_KCL_FENCE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_KCL_FENCE_H + +#include + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM kcl_fence +#define TRACE_INCLUDE_FILE kcl_fence_trace + +struct dma_fence; + +DECLARE_EVENT_CLASS(kcl_fence, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence), + + TP_STRUCT__entry( + __string(driver, fence->ops->get_driver_name(fence)) + __string(timeline, fence->ops->get_timeline_name(fence)) + __field(unsigned int, context) + __field(unsigned int, seqno) + ), + + TP_fast_assign( + __assign_str(driver, fence->ops->get_driver_name(fence)) + __assign_str(timeline, fence->ops->get_timeline_name(fence)) + __entry->context = fence->context; + __entry->seqno = fence->seqno; + ), + + TP_printk("driver=%s timeline=%s context=%u seqno=%u", + __get_str(driver), __get_str(timeline), __entry->context, + __entry->seqno) +); + +DEFINE_EVENT(kcl_fence, kcl_fence_init, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence) +); + +DEFINE_EVENT(kcl_fence, kcl_fence_enable_signal, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence) +); + +DEFINE_EVENT(kcl_fence, kcl_fence_wait_start, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence) +); + +DEFINE_EVENT(kcl_fence, kcl_fence_wait_end, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence) +); + +#endif /* _TRACE_KCL_FENCE_H */ + +/* This part must be outside protection */ +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#include From b49cd2929899df2e77eec013d829784b209023ab Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Tue, 19 Nov 2019 15:23:53 +0800 Subject: [PATCH 0166/2653] drm/amdkcl: include dma-resv.{c,h} to dkms package introduced by v5.4-rc1~32^2~17^2~36 -commit 52791eeec1d9f4a7e7fe08aaba0b1553149d93bc -dma-buf: rename reservation_object to dma_resv Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: chen gong Signed-off-by: Flora Cui Signed-off-by: Chengming Gui Signed-off-by: Jiansong Chen Signed-off-by: Slava Grigorev Reviewed-by: Jiansong Chen Signed-off-by: Yifan Zhang Signed-off-by: Chengming Gui Signed-off-by: Yifan Zhang Reviewed-by: Yang Xiong Signed-off-by: Flora Cui Change-Id: I9b909f512608759f78d88a02254ab3bcdeb366fd drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 4 +- drivers/gpu/drm/amd/amdkcl/files | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_reservation.c | 41 ++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/dkms/Makefile | 4 ++ drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 51 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/pre-build.sh | 5 ++ drivers/gpu/drm/amd/dkms/sources | 3 + include/kcl/kcl_dma-resv.h | 65 ++++++++++++++++++++ include/kcl/kcl_reservation.h | 12 ++++ include/kcl/reservation.h | 9 +++ 12 files changed, 197 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_reservation.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 create mode 100644 include/kcl/kcl_dma-resv.h create mode 100644 include/kcl/kcl_reservation.h create mode 100644 include/kcl/reservation.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 97ed40fbccb56..6d61493a05b1a 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -2,10 +2,12 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o +amdkcl-y += dma-buf/dma-resv.o + amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o \ kcl_suspend.o kcl_pci.o kcl_mm.o \ - kcl_fence.o kcl_fence_array.o + kcl_fence.o kcl_fence_array.o kcl_reservation.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/files b/drivers/gpu/drm/amd/amdkcl/files index 501b9055ad408..a5a39207c730e 100644 --- a/drivers/gpu/drm/amd/amdkcl/files +++ b/drivers/gpu/drm/amd/amdkcl/files @@ -1 +1 @@ -FILES="ttm/*.c scheduler/*.c" +FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c" diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c new file mode 100644 index 0000000000000..6dc0517f2509a --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2012-2014 Canonical Ltd (Maarten Lankhorst) + * + * Based on bo.c which bears the following copyright notice, + * but is dual licensed: + * + * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ +/* + * Authors: Thomas Hellstrom + */ +#include +#include "kcl_common.h" + +void amdkcl_reservation_init(void) +{ + amdkcl_fp_setup("reservation_ww_class", NULL); +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index cc35e1e0f4385..6dc78f4f4f851 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -4,6 +4,7 @@ extern void amdkcl_symbol_init(void); extern void amdkcl_fence_init(void); +extern void amdkcl_reservation_init(void); extern void amdkcl_io_init(void); extern void amdkcl_kthread_init(void); extern void amdkcl_mm_init(void); @@ -15,6 +16,7 @@ int __init amdkcl_init(void) { amdkcl_symbol_init(); amdkcl_fence_init(); + amdkcl_reservation_init(); amdkcl_io_init(); amdkcl_kthread_init(); amdkcl_mm_init(); diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 7c227452be97c..dbace6b3bc0ae 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -12,6 +12,10 @@ endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") +ifeq ($(shell grep "HAVE_DMA_RESV_SEQ" $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n"),n) +$(error dma_resv->seq is missing., exit...) +endif + ifdef CONFIG_CC_IS_GCC GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 new file mode 100644 index 0000000000000..c1060c688a017 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -0,0 +1,51 @@ +dnl # +dnl # v5.3-rc1-476-gb016cd6ed4b7 dma-buf: Restore seqlock around dma_resv updates +dnl # v5.3-rc1-449-g52791eeec1d9 dma-buf: rename reservation_object to dma_resv +dnl # v5.3-rc1-448-g5d344f58da76 dma-buf: nuke reservation_object seq number +dnl # +AC_DEFUN([AC_AMDGPU_DMA_RESV_SEQ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_LINUX_DMA_RESV_H + #include + #else + #include + #endif + ], [ + #ifdef HAVE_LINUX_DMA_RESV_H + struct dma_resv *resv = NULL; + #else + struct reservation_object *resv = NULL; + #endif + write_seqcount_begin(&resv->seq); + ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQ, 1, + [dma_resv->seq is available]) + ]) + ]) +]) + +dnl # +dnl # v4.19-rc6-1514-g27836b641c1b +dnl # dma-buf: remove shared fence staging in reservation object +dnl # +AC_DEFUN([AC_AMDGPU_RESERVATION_OBJECT_STAGED], [ + AC_KERNEL_DO_BACKGROUND([ + AS_IF([test x$HAVE_LINUX_DMA_RESV_H = x ], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct reservation_object *resv = NULL; + resv->staged = NULL; + ], [ + AC_DEFINE(HAVE_RESERVATION_OBJECT_STAGED, 1, + [reservation_object->staged is available]) + ]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DMA_RESV], [ + AC_AMDGPU_DMA_RESV_SEQ + AC_AMDGPU_RESERVATION_OBJECT_STAGED +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 72720629c9637..26a8405a75aaa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -28,6 +28,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS + AC_AMDGPU_DMA_RESV AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 698e69b364c03..7d481851f944d 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -38,6 +38,11 @@ for sym in $SYMS; do }' /boot/System.map-$KERNELVER >>$KCL/symbols.c done +sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ + -e '/dma_resv_lockdep/,/subsys_initcall/d' $KCL/dma-buf/dma-resv.c +sed -i -e '/extern struct ww_class reservation_ww_class/i #include ' \ + -e '/struct dma_resv {/, /}/d' $INC/linux/dma-resv.h + # add amd prefix to exported symbols for file in $FILES; do awk -F'[()]' '/EXPORT_SYMBOL/ { diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources index b8f2af052e55a..3470a58a43676 100644 --- a/drivers/gpu/drm/amd/dkms/sources +++ b/drivers/gpu/drm/amd/dkms/sources @@ -24,3 +24,6 @@ include/drm/gpu_scheduler.h include/drm/ include/drm/amd_asic_type.h include/drm/ include/drm/spsc_queue.h include/drm/ include/uapi/linux/kfd_ioctl.h include/uapi/linux/ +drivers/dma-buf/dma-resv.c amd/amdkcl/dma-buf/ +include/linux/dma-resv.h include/linux/ +include/kcl/reservation.h include/linux/ diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h new file mode 100644 index 0000000000000..be88ddb4c0d1b --- /dev/null +++ b/include/kcl/kcl_dma-resv.h @@ -0,0 +1,65 @@ +/* + * Header file for reservations for dma-buf and ttm + * + * Copyright(C) 2011 Linaro Limited. All rights reserved. + * Copyright (C) 2012-2013 Canonical Ltd + * Copyright (C) 2012 Texas Instruments + * + * Authors: + * Rob Clark + * Maarten Lankhorst + * Thomas Hellstrom + * + * Based on bo.c which bears the following copyright notice, + * but is dual licensed: + * + * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * NOTICE: + * THIS HEADER IS FOR DMA-RESV.H ONLY + * DO NOT INCLUDE THIS HEADER ANY OTHER PLACE + * INCLUDE LINUX/DMA-RESV.H OR LINUX/RESERVATION.H INSTEAD + */ +#ifndef KCL_KCL_DMA_RESV_H +#define KCL_KCL_DMA_RESV_H + +#include +#include + +struct dma_resv_list; + +struct dma_resv { + struct ww_mutex lock; + seqcount_t seq; + + struct dma_fence __rcu *fence_excl; + struct dma_resv_list __rcu *fence; +}; + +#if !defined(smp_store_mb) +#define smp_store_mb set_mb +#endif +#endif diff --git a/include/kcl/kcl_reservation.h b/include/kcl/kcl_reservation.h new file mode 100644 index 0000000000000..32d6d2b8b7826 --- /dev/null +++ b/include/kcl/kcl_reservation.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef KCL_KCL_RESERVATION_H +#define KCL_KCL_RESERVATION_H + +#include + +#ifndef HAVE_LINUX_DMA_RESV_H +#define reservation_object dma_resv +#define reservation_object_list dma_resv_list +#endif + +#endif /* AMDKCL_RESERVATION_H */ diff --git a/include/kcl/reservation.h b/include/kcl/reservation.h new file mode 100644 index 0000000000000..8dcc5e3c18479 --- /dev/null +++ b/include/kcl/reservation.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef KCL_RESERVATION_H +#define KCL_RESERVATION_H + +#ifndef HAVE_LINUX_DMA_RESV_H +#include +#endif /* HAVE_LINUX_DMA_RESV_H */ + +#endif From e3077648a34e11a84ee9cef1571a81178df634f0 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 18 Aug 2020 12:50:51 +0800 Subject: [PATCH 0167/2653] drm/amdkcl: rework reservatio_object->staged case handle reservation_object->staged incase it get updated by 3rd-party driver. Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/amdkcl/kcl_reservation.c | 147 +++++++++++++++++++ include/kcl/kcl_dma-resv.h | 11 ++ include/kcl/reservation.h | 17 +++ 3 files changed, 175 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c index 6dc0517f2509a..16393735a2f43 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c @@ -39,3 +39,150 @@ void amdkcl_reservation_init(void) { amdkcl_fp_setup("reservation_ww_class", NULL); } + +#if defined(HAVE_RESERVATION_OBJECT_STAGED) +static void +reservation_object_add_shared_inplace(struct reservation_object *obj, + struct reservation_object_list *fobj, + struct dma_fence *fence) +{ + struct dma_fence *signaled = NULL; + u32 i, signaled_idx; + + dma_fence_get(fence); + + preempt_disable(); + write_seqcount_begin(&obj->seq); + + for (i = 0; i < fobj->shared_count; ++i) { + struct dma_fence *old_fence; + + old_fence = rcu_dereference_protected(fobj->shared[i], + dma_resv_held(obj)); + + if (old_fence->context == fence->context) { + /* memory barrier is added by write_seqcount_begin */ + RCU_INIT_POINTER(fobj->shared[i], fence); + write_seqcount_end(&obj->seq); + preempt_enable(); + + dma_fence_put(old_fence); + return; + } + + if (!signaled && dma_fence_is_signaled(old_fence)) { + signaled = old_fence; + signaled_idx = i; + } + } + + /* + * memory barrier is added by write_seqcount_begin, + * fobj->shared_count is protected by this lock too + */ + if (signaled) { + RCU_INIT_POINTER(fobj->shared[signaled_idx], fence); + } else { + BUG_ON(fobj->shared_count >= fobj->shared_max); + RCU_INIT_POINTER(fobj->shared[fobj->shared_count], fence); + fobj->shared_count++; + } + + write_seqcount_end(&obj->seq); + preempt_enable(); + + dma_fence_put(signaled); +} + +static void +reservation_object_add_shared_replace(struct reservation_object *obj, + struct reservation_object_list *old, + struct reservation_object_list *fobj, + struct dma_fence *fence) +{ + unsigned i, j, k; + + dma_fence_get(fence); + + if (!old) { + RCU_INIT_POINTER(fobj->shared[0], fence); + fobj->shared_count = 1; + goto done; + } + + /* + * no need to bump fence refcounts, rcu_read access + * requires the use of kref_get_unless_zero, and the + * references from the old struct are carried over to + * the new. + */ + for (i = 0, j = 0, k = fobj->shared_max; i < old->shared_count; ++i) { + struct dma_fence *check; + + check = rcu_dereference_protected(old->shared[i], + dma_resv_held(obj)); + + if (check->context == fence->context || + dma_fence_is_signaled(check)) + RCU_INIT_POINTER(fobj->shared[--k], check); + else + RCU_INIT_POINTER(fobj->shared[j++], check); + } + fobj->shared_count = j; + RCU_INIT_POINTER(fobj->shared[fobj->shared_count], fence); + fobj->shared_count++; + +done: + preempt_disable(); + write_seqcount_begin(&obj->seq); + /* + * RCU_INIT_POINTER can be used here, + * seqcount provides the necessary barriers + */ + RCU_INIT_POINTER(obj->fence, fobj); + write_seqcount_end(&obj->seq); + preempt_enable(); + + if (!old) + return; + + /* Drop the references to the signaled fences */ + for (i = k; i < fobj->shared_max; ++i) { + struct dma_fence *f; + + f = rcu_dereference_protected(fobj->shared[i], + dma_resv_held(obj)); + dma_fence_put(f); + } + kfree_rcu(old, rcu); +} + +void _kcl_dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fence) +{ + struct dma_resv_list *old, *fobj = obj->staged; + + old = dma_resv_get_list(obj); + obj->staged = NULL; + + if (!fobj) + reservation_object_add_shared_inplace(obj, old, fence); + else + reservation_object_add_shared_replace(obj, old, fobj, fence); +} +EXPORT_SYMBOL(_kcl_dma_resv_add_shared_fence); + +int _kcl_dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src) +{ + int ret; + + ret = dma_resv_copy_fences(dst, src); + if (ret) + return ret; + + kfree(dst->staged); + dst->staged = NULL; + + return ret; +} +EXPORT_SYMBOL(_kcl_dma_resv_copy_fences); +#endif diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index be88ddb4c0d1b..5658e14dad4fe 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -51,13 +51,24 @@ struct dma_resv_list; +#if defined(HAVE_RESERVATION_OBJECT_STAGED) struct dma_resv { struct ww_mutex lock; seqcount_t seq; struct dma_fence __rcu *fence_excl; struct dma_resv_list __rcu *fence; + struct dma_resv_list *staged; }; +#else +struct dma_resv { + struct ww_mutex lock; + seqcount_t seq; + + struct dma_fence __rcu *fence_excl; + struct dma_resv_list __rcu *fence; +}; +#endif #if !defined(smp_store_mb) #define smp_store_mb set_mb diff --git a/include/kcl/reservation.h b/include/kcl/reservation.h index 8dcc5e3c18479..fbd036fdd650d 100644 --- a/include/kcl/reservation.h +++ b/include/kcl/reservation.h @@ -4,6 +4,23 @@ #ifndef HAVE_LINUX_DMA_RESV_H #include + +#if defined(HAVE_RESERVATION_OBJECT_STAGED) +static inline void +_kcl_reservation_object_fini(struct reservation_object *obj) +{ + dma_resv_fini(obj); + kfree(obj->staged); +} +#define amddma_resv_fini _kcl_reservation_object_fini + +void _kcl_dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fence); +#define amddma_resv_add_shared_fence _kcl_dma_resv_add_shared_fence + +int _kcl_dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src); +#define amddma_resv_copy_fences _kcl_dma_resv_copy_fences + +#endif /* HAVE_RESERVATION_OBJECT_STAGED */ #endif /* HAVE_LINUX_DMA_RESV_H */ #endif From 9284b830553f8e09c6c3da6864c8c942b843968a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 3 Sep 2020 16:13:29 +0800 Subject: [PATCH 0168/2653] drm/amdkcl: test seqcount_ww_mutex_init for dma_resv Signed-off-by: Flora Cui drm/amdkcl: include kcl_common.h in every .c Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/kcl_reservation.c | 5 ++- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 42 ++++++++++++++------ include/kcl/kcl_dma-resv.h | 11 ++++- include/kcl/kcl_seqlock.h | 30 ++++++++++++++ 5 files changed, 74 insertions(+), 15 deletions(-) create mode 100644 include/kcl/kcl_seqlock.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c index 16393735a2f43..5bb5b8b68e64e 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c @@ -33,7 +33,6 @@ * Authors: Thomas Hellstrom */ #include -#include "kcl_common.h" void amdkcl_reservation_init(void) { @@ -41,6 +40,10 @@ void amdkcl_reservation_init(void) } #if defined(HAVE_RESERVATION_OBJECT_STAGED) +/* + * Copied from v4.19-rc6-1514-g27836b641c1b^:drivers/dma-buf/reservation.c + * and modified for KCL + */ static void reservation_object_add_shared_inplace(struct reservation_object *obj, struct reservation_object_list *fobj, diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 722e0b7c215e4..93bd18b4053db 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index c1060c688a017..1ede56611c58d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -1,26 +1,42 @@ dnl # -dnl # v5.3-rc1-476-gb016cd6ed4b7 dma-buf: Restore seqlock around dma_resv updates -dnl # v5.3-rc1-449-g52791eeec1d9 dma-buf: rename reservation_object to dma_resv -dnl # v5.3-rc1-448-g5d344f58da76 dma-buf: nuke reservation_object seq number +dnl # v5.8-rc6-36-gcd29f22019ec dma-buf: Use sequence counter with associated wound/wait mutex +dnl # v5.8-rc6-35-g318ce71f3e3a dma-buf: Remove custom seqcount lockdep class key dnl # AC_DEFUN([AC_AMDGPU_DMA_RESV_SEQ], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_LINUX_DMA_RESV_H #include - #else - #include - #endif ], [ - #ifdef HAVE_LINUX_DMA_RESV_H - struct dma_resv *resv = NULL; - #else - struct reservation_object *resv = NULL; - #endif - write_seqcount_begin(&resv->seq); + struct dma_resv *obj = NULL; + seqcount_ww_mutex_init(&obj->seq, &obj->lock); ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T, 1, + [dma_resv->seq is seqcount_ww_mutex_t]) AC_DEFINE(HAVE_DMA_RESV_SEQ, 1, [dma_resv->seq is available]) + ], [ + dnl # + dnl # v5.3-rc1-476-gb016cd6ed4b7 dma-buf: Restore seqlock around dma_resv updates + dnl # v5.3-rc1-449-g52791eeec1d9 dma-buf: rename reservation_object to dma_resv + dnl # v5.3-rc1-448-g5d344f58da76 dma-buf: nuke reservation_object seq number + dnl # + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_LINUX_DMA_RESV_H + #include + #else + #include + #endif + ], [ + #ifdef HAVE_LINUX_DMA_RESV_H + struct dma_resv *resv = NULL; + #else + struct reservation_object *resv = NULL; + #endif + write_seqcount_begin(&resv->seq); + ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQ, 1, + [dma_resv->seq is available]) + ]) ]) ]) ]) diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 5658e14dad4fe..680f1fe9c1757 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -48,10 +48,19 @@ #include #include +#include struct dma_resv_list; -#if defined(HAVE_RESERVATION_OBJECT_STAGED) +#if defined(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T) +struct dma_resv { + struct ww_mutex lock; + seqcount_ww_mutex_t seq; + + struct dma_fence __rcu *fence_excl; + struct dma_resv_list __rcu *fence; +}; +#elif defined(HAVE_RESERVATION_OBJECT_STAGED) struct dma_resv { struct ww_mutex lock; seqcount_t seq; diff --git a/include/kcl/kcl_seqlock.h b/include/kcl/kcl_seqlock.h new file mode 100644 index 0000000000000..39f2aa7baa4e5 --- /dev/null +++ b/include/kcl/kcl_seqlock.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_SEQLOCK_H +#define _KCL_KCL_SEQLOCK_H + +#include + +#ifndef write_seqcount_begin +struct ww_mutex; +static __always_inline void +seqcount_ww_mutex_init(seqcount_t *s, struct ww_mutex *lock) +{ + seqcount_init(s); +} + +static inline void _kcl_write_seqcount_begin(seqcount_t *s) +{ + preempt_disable(); + write_seqcount_begin(s); +} +#define write_seqcount_begin _kcl_write_seqcount_begin + +static inline void _kcl_write_seqcount_end(seqcount_t *s) +{ + write_seqcount_end(s); + preempt_enable(); +} +#define write_seqcount_end _kcl_write_seqcount_end +#endif /* write_seqcount_begin */ + +#endif From 18001b931c48fae6baf878f18b65082f62ec5110 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 22 Jun 2020 13:07:45 +0800 Subject: [PATCH 0169/2653] drm/amdkcl: test for ttm_sg_tt_init the pages array(drm_prime_sg_to_page_addr_arrays) is optional since v4.16-rc1-409-g186ca446aea1 the change history is: v4.16-rc1-1232-g75a57669cbc8 drm/ttm: add ttm_sg_tt_init v4.16-rc1-409-g186ca446aea1 drm/prime: make the pages array optional for drm_prime_sg_to_page_addr_arrays Signed-off-by: Flora Cui Reviewed-by: Yang Xiong drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 | 11 +++++++++++ include/kcl/backport/kcl_ttm_tt_backport.h | 11 +++++++++++ 4 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 create mode 100644 include/kcl/backport/kcl_ttm_tt_backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 93bd18b4053db..64fa219edf63b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -29,5 +29,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 26a8405a75aaa..9f9440a5aff5f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -29,6 +29,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV + AC_AMDGPU_TTM_SG_TT_INIT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 b/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 new file mode 100644 index 0000000000000..9bfcadc878e3c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 @@ -0,0 +1,11 @@ +dnl # +dnl # v4.16-rc1-1232-g75a57669cbc8 +dnl # drm/ttm: add ttm_sg_tt_init +dnl # +AC_DEFUN([AC_AMDGPU_TTM_SG_TT_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([ttm_sg_tt_init], [drivers/gpu/drm/ttm/ttm_tt.c], [ + AC_DEFINE(HAVE_TTM_SG_TT_INIT, 1, [ttm_sg_tt_init() is available]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_ttm_tt_backport.h b/include/kcl/backport/kcl_ttm_tt_backport.h new file mode 100644 index 0000000000000..64f22b0fb609e --- /dev/null +++ b/include/kcl/backport/kcl_ttm_tt_backport.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_BACKPORT_KCL_TTM_TT_BACKPORT_H +#define AMDKCL_BACKPORT_KCL_TTM_TT_BACKPORT_H + +#include + +#ifndef HAVE_TTM_SG_TT_INIT +#define amdttm_sg_tt_init ttm_dma_tt_init +#endif + +#endif From ce53b83878e4bfdf3c6e747469718f365ca94123 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Mon, 23 Sep 2019 16:44:20 +0800 Subject: [PATCH 0170/2653] drm/amdkcl: Test whether drm_need_swiotlb() is available Signed-off-by: Adam Yang Signed-off-by: Jack Gui Change-Id: I14e2af5f5522e3ab8398f137f9d4af1cb144498f drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_cache.c | 66 ++++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-cache.m4 | 16 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_cache.h | 41 ++++++++++++++ 6 files changed, 126 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_cache.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-cache.m4 create mode 100644 include/kcl/kcl_drm_cache.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 6d61493a05b1a..96d530ef4231e 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -7,7 +7,7 @@ amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o \ kcl_suspend.o kcl_pci.o kcl_mm.o \ - kcl_fence.o kcl_fence_array.o kcl_reservation.o + kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_cache.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_cache.c new file mode 100644 index 0000000000000..85894bf3907c6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_cache.c @@ -0,0 +1,66 @@ +/* + * \file drm_memory.c + * Memory management wrappers for DRM + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Created: Thu Feb 4 14:00:34 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include + +#include +#include + +/* Copied from drivers/gpu/drm/drm_memory.c */ +#if !defined(HAVE_DRM_NEED_SWIOTLB) +bool drm_need_swiotlb(int dma_bits) +{ + struct resource *tmp; + resource_size_t max_iomem = 0; + + /* + * Xen paravirtual hosts require swiotlb regardless of requested dma + * transfer size. + * + * NOTE: Really, what it requires is use of the dma_alloc_coherent + * allocator used in ttm_dma_populate() instead of + * ttm_populate_and_map_pages(), which bounce buffers so much in + * Xen it leads to swiotlb buffer exhaustion. + */ + if (xen_pv_domain()) + return true; + + for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) { + max_iomem = max(max_iomem, tmp->end); + } + + return max_iomem > ((u64)1 << dma_bits); +} +EXPORT_SYMBOL(drm_need_swiotlb); +#endif /* HAVE_DRM_NEED_SWIOTLB */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 64fa219edf63b..e13cadeacaad3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -30,5 +30,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-cache.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-cache.m4 new file mode 100644 index 0000000000000..42911c2cc2131 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-cache.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 913b2cb727b7a47ccf8842d54c89f1b873c6deed +dnl # drm: change func to better detect wether swiotlb is needed +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CACHE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_need_swiotlb(0); + ], [ + AC_DEFINE(HAVE_DRM_NEED_SWIOTLB, 1, + [drm_need_swiotlb() is availablea]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9f9440a5aff5f..0dcda800bfca8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -30,6 +30,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_SG_TT_INIT + AC_AMDGPU_DRM_CACHE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_cache.h b/include/kcl/kcl_drm_cache.h new file mode 100644 index 0000000000000..861205f2403bd --- /dev/null +++ b/include/kcl/kcl_drm_cache.h @@ -0,0 +1,41 @@ +/************************************************************************** + * + * Copyright 2009 Red Hat Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * + **************************************************************************/ +/* + * Authors: + * Dave Airlie + */ +#ifndef AMDKCL_DRM_CACHE_H +#define AMDKCL_DRM_CACHE_H +#include +#include + +#if !defined(HAVE_DRM_NEED_SWIOTLB) +bool drm_need_swiotlb(int dma_bits); +#endif /* HAVE_DRM_NEED_SWIOTLB */ + +#endif /* AMDKCL_DRM_CACHE_H */ From 8f2f8e587bb47a12ee29bfe03288fcf83f450d96 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 24 Mar 2020 19:14:53 -0400 Subject: [PATCH 0171/2653] amd/amdkcl: backport drm_arch_can_wc_memory() function Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/backport/backport.h | 2 +- include/kcl/backport/kcl_drm_cache_backport.h | 10 ++++++ include/kcl/kcl_drm_cache.h | 35 +++++++++++++++++++ 3 files changed, 46 insertions(+), 1 deletion(-) create mode 100644 include/kcl/backport/kcl_drm_cache_backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e13cadeacaad3..0e45a4affc45b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -30,6 +30,6 @@ #include #include #include -#include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/backport/kcl_drm_cache_backport.h b/include/kcl/backport/kcl_drm_cache_backport.h new file mode 100644 index 0000000000000..bc936463073e5 --- /dev/null +++ b/include/kcl/backport/kcl_drm_cache_backport.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_DRM_CACHE_BACKPORT_H +#define AMDKCL_DRM_CACHE_BACKPORT_H + +#include +#include + +#define drm_arch_can_wc_memory kcl_drm_arch_can_wc_memory + +#endif /* AMDKCL_DRM_CACHE_BACKPORT_H */ diff --git a/include/kcl/kcl_drm_cache.h b/include/kcl/kcl_drm_cache.h index 861205f2403bd..8350e1faa62b5 100644 --- a/include/kcl/kcl_drm_cache.h +++ b/include/kcl/kcl_drm_cache.h @@ -38,4 +38,39 @@ bool drm_need_swiotlb(int dma_bits); #endif /* HAVE_DRM_NEED_SWIOTLB */ +/* + * Copied from include/drm/drm_cache.h + * v5.4-rc2-80-g268a2d600130 MIPS: Loongson64: Rename CPU TYPES + */ +static inline bool kcl_drm_arch_can_wc_memory(void) +{ +#if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE) + return false; +#elif defined(CONFIG_MIPS) && \ + (defined(CONFIG_CPU_LOONGSON64) || defined(CPU_LOONGSON3)) + + return false; +#elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) + /* + * The DRM driver stack is designed to work with cache coherent devices + * only, but permits an optimization to be enabled in some cases, where + * for some buffers, both the CPU and the GPU use uncached mappings, + * removing the need for DMA snooping and allocation in the CPU caches. + * + * The use of uncached GPU mappings relies on the correct implementation + * of the PCIe NoSnoop TLP attribute by the platform, otherwise the GPU + * will use cached mappings nonetheless. On x86 platforms, this does not + * seem to matter, as uncached CPU mappings will snoop the caches in any + * case. However, on ARM and arm64, enabling this optimization on a + * platform where NoSnoop is ignored results in loss of coherency, which + * breaks correct operation of the device. Since we have no way of + * detecting whether NoSnoop works or not, just disable this + * optimization entirely for ARM and arm64. + */ + return false; +#else + return true; +#endif +} + #endif /* AMDKCL_DRM_CACHE_H */ From 5bc49755908ffeb25deae227235cdd527938ecbe Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 14 Apr 2020 22:41:34 +0800 Subject: [PATCH 0172/2653] drm/amdkcl: test whether drm_debug_enabled() is available Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 | 19 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_print.h | 38 +++++++++++++++++++ 4 files changed, 59 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 create mode 100644 include/kcl/kcl_drm_print.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 0e45a4affc45b..e01f33c789fe6 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -31,5 +31,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 new file mode 100644 index 0000000000000..0baf031bd2e3d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit v5.3-rc1-708-gf0a8f533adc2 +dnl # drm/print: add drm_debug_enabled() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEBUG_ENABLED], [ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drm_print.h], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_debug_enabled(0); + ],[ + AC_DEFINE(HAVE_DRM_DEBUG_ENABLED, + 1, + [drm_debug_enabled() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0dcda800bfca8..25256192d7137 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -31,6 +31,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_SG_TT_INIT AC_AMDGPU_DRM_CACHE + AC_AMDGPU_DRM_DEBUG_ENABLED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h new file mode 100644 index 0000000000000..03dce456987d5 --- /dev/null +++ b/include/kcl/kcl_drm_print.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2016 Red Hat + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + */ +#ifndef AMDKCL_DRM_PRINT_H +#define AMDKCL_DRM_PRINT_H + +#include +#include + +#ifndef HAVE_DRM_DEBUG_ENABLED +/* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ +static inline bool drm_debug_enabled(unsigned int category) +{ + return unlikely(drm_debug & category); +} +#endif /* HAVE_DRM_DEBUG_ENABLED */ +#endif From eb9477ed4698005907c4e38f846ad3dfe5307de4 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 12 Jul 2018 14:38:53 -0400 Subject: [PATCH 0173/2653] drm/amdkcl: Test whether drm_fb_helper_remove_conflicting_pci_framebuffers() is available v1: drm/amdkcl: Test whether remove_conflicting_framebuffers() returns int v2: drm/amdkcl: Test whether drm_fb_helper_remove_conflicting_framebuffers() is available v3: drm/amdkcl: refactor drm_fb_helper_remove_conflicting_pci_framebuffers() check v4: drm/amdkcl: accommodate to drmP.h removal for drm-fb-helper-remove-conflicting-pci-framebuffers.m4 v5: for drm_fb_helper_remove_conflicting_pci_framebuffers v6: split to kcl_drm_fb.c v7: drm/amdkcl: fix license for kcl drm part v8: drm/amdkcl: split fbmem related stuff Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Reviewed-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Slava Grigorev Signed-off-by: Flora Cui Reviewed-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Change-Id: I0bfd8baf89e77660fe2d017610a3c997001e39a2 --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 43 ++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + ...per-remove-conflicting-pci-framebuffers.m4 | 57 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_fb.h | 31 +++++++ include/kcl/kcl_drm_fb.h | 80 +++++++++++++++++++ 7 files changed, 215 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 create mode 100644 include/kcl/backport/kcl_drm_fb.h create mode 100644 include/kcl/kcl_drm_fb.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 96d530ef4231e..704e31fc89a3d 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -7,7 +7,8 @@ amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o \ kcl_suspend.o kcl_pci.o kcl_mm.o \ - kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o + kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ + kcl_drm_fb.o kcl_fbmem.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c new file mode 100644 index 0000000000000..11a2fe7ab066e --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -0,0 +1,43 @@ +/* + * linux/drivers/video/fbmem.c + * + * Copyright (C) 1994 Martin Schaller + * + * 2001 - Documented with DocBook + * - Brad Douglas + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include + +/* Copied from drivers/video/fbdev/core/fbmem.c and modified for KCL */ +#if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) +int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const char *name) +{ + struct apertures_struct *ap; + bool primary = false; + int err = 0; + + ap = alloc_apertures(1); + if (!ap) + return -ENOMEM; + + ap->ranges[0].base = pci_resource_start(pdev, res_id); + ap->ranges[0].size = pci_resource_len(pdev, res_id); +#ifdef CONFIG_X86 + primary = pdev->resource[PCI_ROM_RESOURCE].flags & + IORESOURCE_ROM_SHADOW; +#endif +#ifdef HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT + err = remove_conflicting_framebuffers(ap, name, primary); +#else + remove_conflicting_framebuffers(ap, name, primary); +#endif + kfree(ap); + return err; +} +EXPORT_SYMBOL(remove_conflicting_pci_framebuffers); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e01f33c789fe6..05cff055dd4f0 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -32,5 +32,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 new file mode 100644 index 0000000000000..fe519aa4941d2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 @@ -0,0 +1,57 @@ +dnl # +dnl # commit v5.3-rc1-541-g35616a4aa919 +dnl # fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args]) + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) + ], [ + dnl # + dnl # commit v4.19-rc1-110-g4d18975c78f2 + dnl # Author: Michał Mirosław + dnl # Date: Sat Sep 1 16:08:45 2018 +0200 + dnl # fbdev: add remove_conflicting_pci_framebuffers() + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, 0, NULL); + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args]) + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) + ], [ + dnl # + dnl # commit 46eeb2c144956e88197439b5ee5cf221a91b0a81 + dnl # video/fb: Propagate error code from failing to unregister conflicting fb + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + int ret = remove_conflicting_framebuffers(NULL, NULL, false); + ], [remove_conflicting_framebuffers], [drivers/video/fbdev/core/fbmem.c], [ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT, 1, + [remove_conflicting_framebuffers() returns int]) + ]) + ]) + ]) + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args]) + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 25256192d7137..a9df4cd3d5d78 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -32,6 +32,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TTM_SG_TT_INIT AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED + AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h new file mode 100644 index 0000000000000..c83d4ffd135b4 --- /dev/null +++ b/include/kcl/backport/kcl_drm_fb.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ +#ifndef KCL_BACKPORT_KCL_DRM_FB_H +#define KCL_BACKPORT_KCL_DRM_FB_H + +#include +#include + +#if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP) +#define drm_fb_helper_remove_conflicting_pci_framebuffers _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers +#endif +#endif diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h new file mode 100644 index 0000000000000..b05eecd7ae2bf --- /dev/null +++ b/include/kcl/kcl_drm_fb.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2006-2009 Red Hat Inc. + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * + * DRM framebuffer helper functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Dave Airlie + * Jesse Barnes + */ +#ifndef KCL_KCL_DRM_FB_H +#define KCL_KCL_DRM_FB_H + +#include +#include +#include + +#if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) +#if !defined(IS_REACHABLE) +/* Copied from include/linux/kconfig.h */ +#define __ARG_PLACEHOLDER_1 0, +#define __take_second_arg(__ignored, val, ...) val + +/* + * The use of "&&" / "||" is limited in certain expressions. + * The followings enable to calculate "and" / "or" with macro expansion only. + */ +#define __and(x, y) ___and(x, y) +#define ___and(x, y) ____and(__ARG_PLACEHOLDER_##x, y) +#define ____and(arg1_or_junk, y) __take_second_arg(arg1_or_junk y, 0) + +#define __or(x, y) ___or(x, y) +#define ___or(x, y) ____or(__ARG_PLACEHOLDER_##x, y) +#define ____or(arg1_or_junk, y) __take_second_arg(arg1_or_junk 1, y) + +#define IS_REACHABLE(option) __or(IS_BUILTIN(option), \ + __and(IS_MODULE(option), __is_defined(MODULE))) +#endif /*IS_REACHABLE*/ + +extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, + const char *name); +static inline int +_kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const char *name) +{ +#if IS_REACHABLE(CONFIG_FB) + return remove_conflicting_pci_framebuffers(pdev, 0, name); +#else + return 0; +#endif +} +#elif !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP) +static inline int +_kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const char *name) +{ + return drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, name); +} +#endif /* HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ + +#endif From dc75b86e5218254c58fd9906dd6aceecbf8aa9cc Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Wed, 26 Aug 2020 10:06:31 +0800 Subject: [PATCH 0174/2653] drm/amdkcl: add macro DRM_MODE_ROTATE_xxx v2: move to kcl_drm_crtc.h v3: fix license for kcl drm part Signed-off-by: Evan Quan Reviewed-by: Junwei Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- include/kcl/kcl_drm_crtc.h | 76 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 include/kcl/kcl_drm_crtc.h diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h new file mode 100644 index 0000000000000..f027ec142c74e --- /dev/null +++ b/include/kcl/kcl_drm_crtc.h @@ -0,0 +1,76 @@ +/* + * Copyright © 2006 Keith Packard + * Copyright © 2007-2008 Dave Airlie + * Copyright © 2007-2008 Intel Corporation + * Jesse Barnes + * For codes copied from include/drm/drm_crtc.h + * + * Copyright © 2006 Keith Packard + * Copyright © 2007-2008 Dave Airlie + * Copyright © 2007-2008 Intel Corporation + * Jesse Barnes + * For codes copied from include/drm/drm_crtc_helper.h + * + * Copyright (c) 2007 Dave Airlie + * Copyright (c) 2007 Jakob Bornecrantz + * Copyright (c) 2008 Red Hat Inc. + * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA + * Copyright (c) 2007-2008 Intel Corporation + * For codes copied from include/drm/drm_mode.h + * + * Copyright 2018 Intel Corporation + * For codes copied from include/drm/drm_util.h + * + * Copyright (c) 2016 Intel Corporation + * For codes copied from include/drm/drm_encoder.h + * + * Copyright (c) 2016 Intel Corporation + * For codes copied from include/drm/drm_framebuffer.h + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef KCL_KCL_DRM_CRTC_H +#define KCL_KCL_DRM_CRTC_H + +#include +#include + +/* Copied from include/drm/drm_mode.h */ +#ifndef DRM_MODE_ROTATE_0 +#define DRM_MODE_ROTATE_0 (1<<0) +#endif +#ifndef DRM_MODE_ROTATE_90 +#define DRM_MODE_ROTATE_90 (1<<1) +#endif +#ifndef DRM_MODE_ROTATE_180 +#define DRM_MODE_ROTATE_180 (1<<2) +#endif +#ifndef DRM_MODE_ROTATE_270 +#define DRM_MODE_ROTATE_270 (1<<3) +#endif + +#ifndef DRM_MODE_ROTATE_MASK +#define DRM_MODE_ROTATE_MASK (\ + DRM_MODE_ROTATE_0 | \ + DRM_MODE_ROTATE_90 | \ + DRM_MODE_ROTATE_180 | \ + DRM_MODE_ROTATE_270) +#endif + +#endif From 53e96f49639c5aac1635fd9cc830e34d59092b63 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 29 Aug 2019 16:50:23 +0800 Subject: [PATCH 0175/2653] drm/amdkcl: Test whether drm_connector_update_edid_property() is available Introduced by kernel v4.19-rc1~28^2~27^2~22 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: fix license for kcl drm part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../m4/drm-connector-update-edid-property.m4 | 16 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 32 +++++++++++++++++++ 4 files changed, 50 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 create mode 100644 include/kcl/kcl_drm_connector.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 05cff055dd4f0..ea1f38e85da3d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -33,5 +33,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 new file mode 100644 index 0000000000000..eade2ed63d298 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit c555f02371c338b06752577aebf738dbdb6907bd +dnl # drm: drop _mode_ from update_edit_property() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_connector_update_edid_property(NULL, NULL); + ],[drm_connector_update_edid_property],[drivers/gpu/drm/drm_connector.c],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_UPDATE_EDID_PROPERTY, 1, + [drm_connector_update_edid_property() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a9df4cd3d5d78..f6480c620e89e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -33,6 +33,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS + AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h new file mode 100644 index 0000000000000..ce58a5236fbac --- /dev/null +++ b/include/kcl/kcl_drm_connector.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ +#ifndef AMDKCL_DRM_CONNECTOR_H +#define AMDKCL_DRM_CONNECTOR_H + +#include +#include + +#ifndef HAVE_DRM_CONNECTOR_UPDATE_EDID_PROPERTY +#define drm_connector_update_edid_property drm_mode_connector_update_edid_property +#endif + +#endif /* AMDKCL_DRM_CONNECTOR_H */ From 9e98720fbb37356cac47d180cfa243c1915ee7e1 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 29 Aug 2019 16:58:01 +0800 Subject: [PATCH 0176/2653] drm/amdkcl: Test whether drm_connector_attach_encoder() is available Introduced by kernel v4.19-rc1~28^2~27^2~21 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui --- .../amd/dkms/m4/drm-connector-attach-encoder.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 4 ++++ 3 files changed, 21 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 new file mode 100644 index 0000000000000..9b4bd0e561b64 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit cde4c44d8769c1be16074c097592c46c7d64092b +dnl # drm: drop _mode_ from drm_mode_connector_attach_encode +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_connector_attach_encoder(NULL, NULL); + ],[drm_connector_attach_encoder],[drivers/gpu/drm/drm_connector.c],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_ATTACH_ENCODER, 1, + [drm_connector_attach_encoder() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f6480c620e89e..201d629dd6831 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -34,6 +34,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY + AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index ce58a5236fbac..5e26174b89b97 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -29,4 +29,8 @@ #define drm_connector_update_edid_property drm_mode_connector_update_edid_property #endif +#ifndef HAVE_DRM_CONNECTOR_ATTACH_ENCODER +#define drm_connector_attach_encoder drm_mode_connector_attach_encoder +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From cb6853b27a658511c835b5502af30d92ea6bd655 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 29 Aug 2019 17:03:30 +0800 Subject: [PATCH 0177/2653] drm/amdkcl: Test whether drm_connector_set_path_property() is available Introduced by kernel v4.19-rc1~28^2~27^2~20 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui --- .../dkms/m4/drm-connector-set-path-property.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 4 ++++ 3 files changed, 21 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 new file mode 100644 index 0000000000000..f872d0db19a2e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 97e14fbeb53fe060c5f6a7a07e37fd24c087ed0c +dnl # drm: drop _mode_ from remaining connector functions +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_connector_set_path_property(NULL, NULL); + ],[drm_connector_set_path_property],[drivers/gpu/drm/drm_connector.c],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_SET_PATH_PROPERTY, 1, + [drm_connector_set_path_property() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 201d629dd6831..0df51593ebe56 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -35,6 +35,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER + AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 5e26174b89b97..557629af9c283 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -33,4 +33,8 @@ #define drm_connector_attach_encoder drm_mode_connector_attach_encoder #endif +#ifndef HAVE_DRM_CONNECTOR_SET_PATH_PROPERTY +#define drm_connector_set_path_property drm_mode_connector_set_path_property +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From 859dd767c15c28ddd53deacb8432ee0ef7f169d7 Mon Sep 17 00:00:00 2001 From: tianci yin Date: Thu, 14 Feb 2019 10:08:11 +0800 Subject: [PATCH 0178/2653] drm/amdkcl: check whether drm_connector_for_each_possible_encoder is available drm_connector_for_each_possible_encoder was introduced by the below commit since 4.19-rc1, add kcl implement for older kernel. "drm: Add drm_connector_for_each_possible_encoder()" for_each_if is introduce from v4.5-rc1 . so it's not available on drm < 4.5 like rhel6.10 . v1: drm/amdkcl: [4.19] kcl for drm_connector_for_each_possible_encoder v2: drm/amdkcl: check whether drm_connector_for_each_possible_encoder is available v3: drm_connector_for_each_possible_encoder Reviewed-by: changzhu Signed-off-by: Tianci Yin Signed-off-by: Chengming Gui Signed-off-by: Flora Cui Signed-off-by: Jack Gui Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- include/kcl/kcl_drm_connector.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 557629af9c283..313ab68fc65f5 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -24,6 +24,7 @@ #include #include +#include #ifndef HAVE_DRM_CONNECTOR_UPDATE_EDID_PROPERTY #define drm_connector_update_edid_property drm_mode_connector_update_edid_property @@ -37,4 +38,20 @@ #define drm_connector_set_path_property drm_mode_connector_set_path_property #endif +/** + * drm_connector_for_each_possible_encoder - iterate connector's possible encoders + * @connector: &struct drm_connector pointer + * @encoder: &struct drm_encoder pointer used as cursor + * @__i: int iteration cursor, for macro-internal use + */ +#ifndef drm_connector_for_each_possible_encoder +#define drm_connector_for_each_possible_encoder(connector, encoder, __i) \ + for ((__i) = 0; (__i) < ARRAY_SIZE((connector)->encoder_ids) && \ + (connector)->encoder_ids[(__i)] != 0; (__i)++) \ + for_each_if((encoder) = \ + drm_encoder_find((connector)->dev, NULL, \ + (connector)->encoder_ids[(__i)])) \ + +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From 8635491760b990ef03efdf713bb961c491c92a85 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 5 Dec 2019 15:22:06 +0800 Subject: [PATCH 0179/2653] drm/amdkcl: Test whether drm_connector_init_with_ddc is available introduced by kernel v5.3-rc1-330-g100163df4203 v2: fix typo Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 ++- drivers/gpu/drm/amd/amdkcl/kcl_connector.c | 14 ++++++++++++++ .../amd/dkms/m4/drm-connector-init-with-ddc.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 17 +++++++++++++++++ 5 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_connector.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-init-with-ddc.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 704e31fc89a3d..e63bff1e7554b 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -8,7 +8,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o \ kcl_suspend.o kcl_pci.o kcl_mm.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ - kcl_drm_fb.o kcl_fbmem.o + kcl_drm_fb.o kcl_fbmem.o \ + kcl_connector.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_connector.c new file mode 100644 index 0000000000000..ff900e261cb43 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_connector.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#include + +#ifndef HAVE_DRM_CONNECTOR_INIT_WITH_DDC +int _kcl_drm_connector_init_with_ddc(struct drm_device *dev, + struct drm_connector *connector, + const struct drm_connector_funcs *funcs, + int connector_type, + struct i2c_adapter *ddc) +{ + return drm_connector_init(dev, connector, funcs, connector_type); +} +EXPORT_SYMBOL(_kcl_drm_connector_init_with_ddc); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-init-with-ddc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-init-with-ddc.m4 new file mode 100644 index 0000000000000..9af2f9f8226b4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-init-with-ddc.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.3-rc1-330-g100163df4203 +dnl # drm: Add drm_connector_init() variant with ddc +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_connector_init_with_ddc(NULL, NULL, NULL, 0, NULL); + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_INIT_WITH_DDC, 1, + [drm_connector_init_with_ddc() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0df51593ebe56..876fda15fdb41 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -36,6 +36,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY + AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 313ab68fc65f5..ac6c066aa3376 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -54,4 +54,21 @@ #endif +#ifndef HAVE_DRM_CONNECTOR_INIT_WITH_DDC +int _kcl_drm_connector_init_with_ddc(struct drm_device *dev, + struct drm_connector *connector, + const struct drm_connector_funcs *funcs, + int connector_type, + struct i2c_adapter *ddc); +static inline +int drm_connector_init_with_ddc(struct drm_device *dev, + struct drm_connector *connector, + const struct drm_connector_funcs *funcs, + int connector_type, + struct i2c_adapter *ddc) +{ + return _kcl_drm_connector_init_with_ddc(dev, connector, funcs, connector_type, ddc); +} +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From 20e86d5c2a170f11c2e008bd5de5ad7bfba9bac3 Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Thu, 11 Oct 2018 13:46:20 +0800 Subject: [PATCH 0180/2653] drm/amdkcl: check whether ACPI_VIDEO_NOTIFY_PROBE is available Signed-off-by: Prike Liang Signed-off-by: Jack Gui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_video.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/kcl/kcl_video.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index ea1f38e85da3d..682284f3d2967 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_video.h b/include/kcl/kcl_video.h new file mode 100644 index 0000000000000..414cfdc2439a7 --- /dev/null +++ b/include/kcl/kcl_video.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_VIDEO_H +#define AMDKCL_VIDEO_H + +#include + +#ifndef ACPI_VIDEO_NOTIFY_PROBE +#define ACPI_VIDEO_NOTIFY_PROBE 0x81 +#endif + +#endif/*AMDKCL_VIDEO_H*/ From 9e2219fd13d5ffc5d545584e775ce9524459028d Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Mon, 18 Feb 2019 10:46:23 +0800 Subject: [PATCH 0181/2653] drm/amdkcl: Test whether ACPI_HANDLE is defined This is a squash of: drm/amdkcl: [RHEL 6] fix ACPI_HANDLE missing Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Jack Gui drm/amdkcl: Test whether ACPI_HANDLE is defined Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: add comments for kcl_acpi.h Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_acpi.h | 26 +++++++++++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 include/kcl/kcl_acpi.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 682284f3d2967..2df777a72095f 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_acpi.h b/include/kcl/kcl_acpi.h new file mode 100644 index 0000000000000..d6f499640f0b8 --- /dev/null +++ b/include/kcl/kcl_acpi.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * acpi.h - ACPI Interface + * + * Copyright (C) 2001 Paul Diefenbaugh + */ +#ifndef AMDKCL_ACPI_H +#define AMDKCL_ACPI_H + +/** + * interface change in mainline kernel 3.13 + * but only affect RHEL6 without backport + * v3.7-rc5-12-g95f8a082b9b1 ACPI / driver core: Introduce struct acpi_dev_node + * and related macros + * v3.12-8048-g7b1998116bbb ACPI / driver core: Store an ACPI device pointer in + * struct acpi_dev_node + */ + +#include + +/* Copied from include/linux/acpi.h> */ +#ifndef ACPI_HANDLE +#define ACPI_HANDLE(dev) DEVICE_ACPI_HANDLE(dev) +#endif + +#endif /* AMDKCL_ACPI_H */ From 63c3ea113b752c8fb72c8bc3558a3eaf16e54bd5 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 26 Aug 2020 15:35:29 +0800 Subject: [PATCH 0182/2653] drm/amdkcl: test kthread_{use,unuse}_mm() introduced in commit f5678e7f2ac3 ("kernel: better document the use_mm/unuse_mm API contract") Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 | 11 +++++++++++ include/kcl/kcl_kthread.h | 17 +++++++++++++++++ 3 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 876fda15fdb41..7f29ac453df37 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -37,6 +37,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC + AC_AMDGPU_KTHREAD_USE_MM AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 b/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 new file mode 100644 index 0000000000000..0b62fc9008c6b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 @@ -0,0 +1,11 @@ +dnl # +dnl # f5678e7f2ac3 kernel: better document the use_mm/unuse_mm API contract +dnl # 9bf5b9eb232b kernel: move use_mm/unuse_mm to kthread.c +dnl # +AC_DEFUN([AC_AMDGPU_KTHREAD_USE_MM], [ + AC_KERNEL_CHECK_SYMBOL_EXPORT([kthread_use_mm kthread_unuse_mm], + [kernel/kthread.c], [ + AC_DEFINE(HAVE_KTHREAD_USE_MM, 1, + [kthread_{use,unuse}_mm() is available]) + ]) +]) diff --git a/include/kcl/kcl_kthread.h b/include/kcl/kcl_kthread.h index 66298a3726350..ecb650acee90e 100644 --- a/include/kcl/kcl_kthread.h +++ b/include/kcl/kcl_kthread.h @@ -4,6 +4,9 @@ #include #include +#ifndef HAVE_KTHREAD_USE_MM +#include +#endif #if !defined(HAVE___KTHREAD_SHOULD_PATK) extern bool __kcl_kthread_should_park(struct task_struct *k); @@ -15,4 +18,18 @@ extern void (*_kcl_kthread_unpark)(struct task_struct *k); extern int (*_kcl_kthread_park)(struct task_struct *k); extern bool (*_kcl_kthread_should_park)(void); #endif + +#ifndef HAVE_KTHREAD_USE_MM +static inline +void kthread_use_mm(struct mm_struct *mm) +{ + use_mm(mm); +} +static inline +void kthread_unuse_mm(struct mm_struct *mm) +{ + unuse_mm(mm); +} +#endif + #endif /* AMDKCL_KTHREAD_H */ From a2eae7f5eed7667a0b951e4cbee14b4e004e0a90 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 27 Aug 2020 16:18:17 +0800 Subject: [PATCH 0183/2653] drm/amdkcl: test fault_flag_allow_retry_first() Signed-off-by: Flora Cui --- .../amd/dkms/m4/fault_flag_allow_retry_first.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_mm.h | 8 ++++++++ 3 files changed, 25 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/fault_flag_allow_retry_first.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/fault_flag_allow_retry_first.m4 b/drivers/gpu/drm/amd/dkms/m4/fault_flag_allow_retry_first.m4 new file mode 100644 index 0000000000000..ce4b655254f91 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/fault_flag_allow_retry_first.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.6-5709-g4064b9827063 +dnl # mm: allow VM_FAULT_RETRY for multiple times +dnl # +AC_DEFUN([AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + fault_flag_allow_retry_first(0); + ], [ + AC_DEFINE(HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST, 1, + [fault_flag_allow_retry_first() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7f29ac453df37..5fdb1075e4658 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -38,6 +38,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_KTHREAD_USE_MM + AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index f300ba76bf794..f7616dde77031 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -14,4 +14,12 @@ #define untagged_addr(addr) (addr) #endif +#ifndef HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST +static inline bool fault_flag_allow_retry_first(unsigned int flags) +{ + return (flags & FAULT_FLAG_ALLOW_RETRY) && + (!(flags & FAULT_FLAG_TRIED)); +} +#endif + #endif /* AMDKCL_MM_H */ From f380a3b8c911b5124e197df132446c44e2a36b45 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 12 Jun 2019 11:03:57 -0400 Subject: [PATCH 0184/2653] drm/amdkcl: Test whether drm_printf() function is available Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui drm/amdkcl: split drm_print stuff to kcl_drm_print.[ch] Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 41 +++++++++++++++++++ drivers/gpu/drm/scheduler/backport/backport.h | 2 +- drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_drm_print.h | 15 ++++++- 5 files changed, 57 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index e63bff1e7554b..dc2f9b9255877 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -8,7 +8,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o \ kcl_suspend.o kcl_pci.o kcl_mm.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ - kcl_drm_fb.o kcl_fbmem.o \ + kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_connector.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c new file mode 100644 index 0000000000000..47b68ba76db6f --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2016 Red Hat + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + */ +#include +#include + +#if !defined(HAVE_DRM_DRM_PRINT_H) +void drm_printf(struct drm_printer *p, const char *f, ...) +{ + struct va_format vaf; + va_list args; + + va_start(args, f); + vaf.fmt = f; + vaf.va = &args; + p->printfn(p, &vaf); + va_end(args); +} +EXPORT_SYMBOL(drm_printf); +#endif diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 28b00db43738f..4a62c9677187a 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -5,5 +5,5 @@ #include #include #include - +#include #endif diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 48f3f3bc56a71..9f3fbf350006e 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -7,4 +7,5 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 03dce456987d5..4cdae9fe3968d 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -25,8 +25,19 @@ #ifndef AMDKCL_DRM_PRINT_H #define AMDKCL_DRM_PRINT_H -#include -#include +#include +#include + +#if !defined(HAVE_DRM_DRM_PRINT_H) +/* Copied from include/drm/drm_print.h */ +struct drm_printer { + void (*printfn)(struct drm_printer *p, struct va_format *vaf); + void *arg; + const char *prefix; +}; + +void drm_printf(struct drm_printer *p, const char *f, ...); +#endif #ifndef HAVE_DRM_DEBUG_ENABLED /* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ From 75494d6b5a8f0dd5c68fb8f0c8707ee8a2584ed8 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 14 Aug 2019 12:58:05 +0800 Subject: [PATCH 0185/2653] drm/amdkcl: Test whether drm_debug_printer is available v1: drm/amdkcl: Test whether drm_debug_printer() function is available v2: drm/amdkcl: fix the struct drm_printer error. v3: drm/amdkcl: fix drm_printer related checks v4: drm/amdkcl: accommodate to drmP.h removal for drm-mm-print.m4 Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Slava Grigorev Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: split drm_print stuff to kcl_drm_print.[ch] Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 12 ++++++++++ .../gpu/drm/amd/dkms/m4/drm-debug-printer.m4 | 16 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_print.h | 22 +++++++++++++++++++ 4 files changed, 51 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 47b68ba76db6f..3b5945b8bee0a 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -39,3 +39,15 @@ void drm_printf(struct drm_printer *p, const char *f, ...) } EXPORT_SYMBOL(drm_printf); #endif + +#if !defined(HAVE_DRM_DEBUG_PRINTER) +void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf) +{ +#if !defined(HAVE_DRM_DRM_PRINT_H) + pr_debug("%s %pV", p->prefix, vaf); +#else + pr_debug("%s %pV", "no prefix < 4.11", vaf); +#endif +} +EXPORT_SYMBOL(__drm_printfn_debug); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 new file mode 100644 index 0000000000000..3fdcea368bf1e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 3d387d923c18afbacef8f14ccaa2ace2a297df74 +dnl # drm/printer: add debug printer +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEBUG_PRINTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_debug_printer(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DEBUG_PRINTER, 1, + [drm_debug_printer() function is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5fdb1075e4658..7e2af6cbb3cd5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -39,6 +39,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST + AC_AMDGPU_DRM_DEBUG_PRINTER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 4cdae9fe3968d..bd2996d38f602 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -39,6 +39,28 @@ struct drm_printer { void drm_printf(struct drm_printer *p, const char *f, ...); #endif +/** + * drm_debug_printer - construct a &drm_printer that outputs to pr_debug() + * @prefix: debug output prefix + * + * RETURNS: + * The &drm_printer object + */ +#if !defined(HAVE_DRM_DEBUG_PRINTER) +extern void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf); + +static inline struct drm_printer drm_debug_printer(const char *prefix) +{ + struct drm_printer p = { + .printfn = __drm_printfn_debug, +#if !defined(HAVE_DRM_DRM_PRINT_H) + .prefix = prefix +#endif + }; + return p; +} +#endif + #ifndef HAVE_DRM_DEBUG_ENABLED /* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ static inline bool drm_debug_enabled(unsigned int category) From 437026939272393424c565cd530b81cb061e0a7b Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Fri, 22 Nov 2019 13:09:50 +0800 Subject: [PATCH 0186/2653] drm/amdkcl: check whether DRM_DEV_{ERROR/DEBUG} are available v2: move DRM_DEV_ERROR to kcl_drm.h v3: drm/amdkcl: split drm_print stuff to kcl_drm_print.[ch] Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Reviewed-by: Felix Kuehling --- include/kcl/kcl_drm_print.h | 52 +++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index bd2996d38f602..65db884854a3d 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -61,6 +61,58 @@ static inline struct drm_printer drm_debug_printer(const char *prefix) } #endif +#ifndef _DRM_PRINTK +#define _DRM_PRINTK(once, level, fmt, ...) \ + do { \ + printk##once(KERN_##level "[" DRM_NAME "] " fmt, \ + ##__VA_ARGS__); \ + } while (0) +#endif + +#ifndef DRM_WARN +#define DRM_WARN(fmt, ...) \ + _DRM_PRINTK(, WARNING, fmt, ##__VA_ARGS__) +#endif + +#ifndef DRM_WARN_ONCE +#define DRM_WARN_ONCE(fmt, ...) \ + _DRM_PRINTK(_once, WARNING, fmt, ##__VA_ARGS__) +#endif + +#ifndef DRM_NOTE +#define DRM_NOTE(fmt, ...) \ + _DRM_PRINTK(, NOTICE, fmt, ##__VA_ARGS__) +#endif + +#ifndef DRM_NOTE_ONCE +#define DRM_NOTE_ONCE(fmt, ...) \ + _DRM_PRINTK(_once, NOTICE, fmt, ##__VA_ARGS__) +#endif + +#ifndef DRM_ERROR +#define DRM_ERROR(fmt, ...) \ + drm_printk(KERN_ERR, DRM_UT_NONE, fmt, ##__VA_ARGS__) +#endif + +#if !defined(DRM_DEV_DEBUG) +#define DRM_DEV_DEBUG(dev, fmt, ...) \ + DRM_DEBUG(fmt, ##__VA_ARGS__) +#endif + +#if !defined(DRM_DEV_ERROR) +#define DRM_DEV_ERROR(dev, fmt, ...) \ + DRM_ERROR(fmt, ##__VA_ARGS__) +#endif + +#ifndef DRM_DEBUG_VBL +#define DRM_UT_VBL 0x20 +#define DRM_DEBUG_VBL(fmt, args...) \ + do { \ + if (unlikely(drm_debug & DRM_UT_VBL)) \ + drm_ut_debug_printk(__func__, fmt, ##args); \ + } while (0) +#endif + #ifndef HAVE_DRM_DEBUG_ENABLED /* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ static inline bool drm_debug_enabled(unsigned int category) From 87d3d97897da436040a1f57286ac46cee860309b Mon Sep 17 00:00:00 2001 From: Anatoli Antonovitch Date: Mon, 24 Sep 2018 15:29:41 -0400 Subject: [PATCH 0187/2653] drm/amdkcl: Test whether drm_gem_object_put_unlocked() is available v2: drop kcl_drm_gem_object_put_unlocked v3: Add wrap for drm_gem_object_get v4: add wrap for drm_gem_object_put() v5: drm/amdkcl: split drm_gem related stuff Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui Acked-by: Feifei Xu / Signed-off-by: Jack Gui Signed-off-by: Flora Cui Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 | 28 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_gem.h | 45 ++++++++++++++ include/kcl/kcl_drm_gem.h | 60 +++++++++++++++++++ 5 files changed, 135 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 create mode 100644 include/kcl/backport/kcl_drm_gem.h create mode 100644 include/kcl/kcl_drm_gem.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 2df777a72095f..ffe385190e8ee 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -34,6 +34,7 @@ #include #include #include +#include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 new file mode 100644 index 0000000000000..f73dc8440b756 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 @@ -0,0 +1,28 @@ +dnl # +dnl # v5.7-rc1-518-gab15d56e27be drm: remove transient drm_gem_object_put_unlocked() +dnl # v5.7-rc1-491-geecd7fd8bf58 drm/gem: add _locked suffix to drm_gem_object_put +dnl # v5.7-rc1-490-gb5d250744ccc drm/gem: fold drm_gem_object_put_unlocked and __drm_gem_object_put() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT( + [drm_gem_object_put_locked], [drivers/gpu/drm/drm_gem.c], + [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_LOCKED, 1, + [drm_gem_object_put_locked() is available]) + ], [ + dnl # + dnl # commit v4.10-rc8-1302-ge6b62714e87c + dnl # drm: Introduce drm_gem_object_{get,put}() + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_gem_object_put_unlocked(NULL); + ], [drm_gem_object_put_unlocked], [drivers/gpu/drm/drm_gem.c], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED, 1, + [drm_gem_object_put_unlocked() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7e2af6cbb3cd5..3067457e3882d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -32,6 +32,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TTM_SG_TT_INIT AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED + AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER diff --git a/include/kcl/backport/kcl_drm_gem.h b/include/kcl/backport/kcl_drm_gem.h new file mode 100644 index 0000000000000..373e3719b4c57 --- /dev/null +++ b/include/kcl/backport/kcl_drm_gem.h @@ -0,0 +1,45 @@ +/* + * GEM Graphics Execution Manager Driver Interfaces + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * All rights reserved. + * Copyright © 2014 Intel Corporation + * Daniel Vetter + * + * Author: Rickard E. (Rik) Faith + * Author: Gareth Hughes + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __KCL_BACKPORT_KCL_DRM_GEM_H__ +#define __KCL_BACKPORT_KCL_DRM_GEM_H__ + +#include + +#if !defined(HAVE_DRM_GEM_OBJECT_PUT_LOCKED) +#if defined(HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED) +#define drm_gem_object_put _kcl_drm_gem_object_put +#endif +#endif + +#endif diff --git a/include/kcl/kcl_drm_gem.h b/include/kcl/kcl_drm_gem.h new file mode 100644 index 0000000000000..a0f90deb18b06 --- /dev/null +++ b/include/kcl/kcl_drm_gem.h @@ -0,0 +1,60 @@ +/* + * GEM Graphics Execution Manager Driver Interfaces + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * All rights reserved. + * Copyright © 2014 Intel Corporation + * Daniel Vetter + * + * Author: Rickard E. (Rik) Faith + * Author: Gareth Hughes + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __KCL_KCL_DRM_GEM_H__ +#define __KCL_KCL_DRM_GEM_H__ + +#include +#if !defined(HAVE_DRM_GEM_OBJECT_PUT_LOCKED) +#if defined(HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED) +static inline void +_kcl_drm_gem_object_put(struct drm_gem_object *obj) +{ + return drm_gem_object_put_unlocked(obj); +} +#else +static inline void +drm_gem_object_put(struct drm_gem_object *obj) +{ + return drm_gem_object_unreference_unlocked(obj); +} + +static inline void +drm_gem_object_get(struct drm_gem_object *obj) +{ + kref_get(&obj->refcount); +} +#endif +#endif /* HAVE_DRM_GEM_OBJECT_PUT_LOCKED */ + +#endif From d9fafd7edc09be72a4bf4c61e88d54f3f654209b Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 19 Sep 2019 13:44:02 +0800 Subject: [PATCH 0188/2653] drm/amdkcl: Test whether drm_fb_helper_fill_info() is available Introduced by kernel v5.2-rc1~48^2~37^2~7 v2: implement drm_fb_helper_fill_info() for kernel don't have it. v3: drm/amdkcl: drop symbol check for drm_fb_helper_fill_info v4: drm/amdkcl: accommodate to drmP.h removal for drm-fb-helper-fill-info.m4 v5: move to kcl_drm_fb.h Signed-off-by: Chengming Gui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c | 30 +++++++++++++++++++ .../amd/dkms/m4/drm-fb-helper-fill-info.m4 | 22 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_fb.h | 6 ++++ 4 files changed, 59 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c new file mode 100644 index 0000000000000..d803603612ab8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: MIT */ +#include +#include +#include +#include +#include +#include + +#ifndef HAVE_DRM_FB_HELPER_FILL_INFO +void drm_fb_helper_fill_info(struct fb_info *info, + struct drm_fb_helper *fb_helper, + struct drm_fb_helper_surface_size *sizes) +{ + struct drm_framebuffer *fb = fb_helper->fb; + +#ifdef HAVE_DRM_FRAMEBUFFER_FORMAT + drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth); +#else + drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth); +#endif + drm_fb_helper_fill_var(info, fb_helper, + sizes->fb_width, sizes->fb_height); + + info->par = fb_helper; + snprintf(info->fix.id, sizeof(info->fix.id), "%sdrmfb", + fb_helper->dev->driver->name); + +} +EXPORT_SYMBOL(drm_fb_helper_fill_info); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 new file mode 100644 index 0000000000000..23832e30bd48e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 @@ -0,0 +1,22 @@ +dnl # +dnl # commit ec8bf1942567bf0736314da9723e93bcc73c131f +dnl # drm/fb-helper: Fixup fill_info cleanup +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_FILL_INFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + drm_fb_helper_fill_info(NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_FILL_INFO, 1, + [drm_fb_helper_fill_info() is available]) + ]) + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_FILL_INFO, 1, + [drm_fb_helper_fill_info() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3067457e3882d..30f36e74b2326 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -41,6 +41,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_AMDGPU_DRM_DEBUG_PRINTER + AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index b05eecd7ae2bf..46fdedd66a9ca 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -77,4 +77,10 @@ _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, } #endif /* HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ +#ifndef HAVE_DRM_FB_HELPER_FILL_INFO +void drm_fb_helper_fill_info(struct fb_info *info, + struct drm_fb_helper *fb_helper, + struct drm_fb_helper_surface_size *sizes); +#endif + #endif From 6333cf24572413d9a885f16998f49f79625078f7 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 22 Aug 2019 09:52:00 +0800 Subject: [PATCH 0189/2653] drm/amdkcl: Test whehter drm_fb_helper_set_suspend_unlocked() is available drm_fb_helper_set_suspend_unlocked() introduced and exported by kernel v4.9-rc1~41^2~39^2~4 v1: drm/amdkcl: drop kcl_drm_fb_helper_set_suspend_unlocked v2: drm/amdkcl: drop symbol check for drm_fb_helper_set_suspend_unlocked v3: drm/amdkcl: accommodate to drmP.h removal for drm-fb-helper-set-suspend-unlocked.m4 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Acked-by: Feifei Xu / Signed-off-by: Jack Gui Reviewed-by: Yifan Zhang Signed-off-by: Jiansong Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c | 21 ++++++++++++++++++ .../m4/drm-fb-helper-set-suspend-unlocked.m4 | 22 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_fb.h | 11 ++++++++++ 4 files changed, 55 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c index d803603612ab8..900629e0dc0ed 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: MIT */ #include #include +#include #include #include #include @@ -28,3 +29,23 @@ void drm_fb_helper_fill_info(struct fb_info *info, } EXPORT_SYMBOL(drm_fb_helper_fill_info); #endif + +#ifndef HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED +/** + * _kcl_drm_fb_helper_set_suspend_stub - wrapper around fb_set_suspend + * @fb_helper: driver-allocated fbdev helper + * @state: desired state, zero to resume, non-zero to suspend + * + * A wrapper around fb_set_suspend implemented by fbdev core + */ +void _kcl_drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, int state) +{ + if (!fb_helper || !fb_helper->fbdev) + return; + + console_lock(); + fb_set_suspend(fb_helper->fbdev, state); + console_unlock(); +} +EXPORT_SYMBOL(_kcl_drm_fb_helper_set_suspend_unlocked); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 new file mode 100644 index 0000000000000..cd00b4a9ac55c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 @@ -0,0 +1,22 @@ +dnl # +dnl # commit cfe63423d9be3e7020296c3dfb512768a83cd099 +dnl # drm/fb-helper: Add drm_fb_helper_set_suspend_unlocked() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + drm_fb_helper_set_suspend_unlocked(NULL,0); + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED, 1, + [drm_fb_helper_set_suspend_unlocked() is available]) + ]) + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED, 1, + [drm_fb_helper_set_suspend_unlocked() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 30f36e74b2326..42eb904bcfbf9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -42,6 +42,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO + AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 46fdedd66a9ca..76b6ade463704 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -83,4 +83,15 @@ void drm_fb_helper_fill_info(struct fb_info *info, struct drm_fb_helper_surface_size *sizes); #endif +#ifndef HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED +extern void _kcl_drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, int state); +static inline +void drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, + bool suspend) + +{ + _kcl_drm_fb_helper_set_suspend_unlocked(fb_helper, suspend); +} +#endif + #endif From 1fd844b0f2951cb025bfd2632ac1062bac026aa7 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sat, 12 Oct 2019 10:26:05 +0800 Subject: [PATCH 0190/2653] drm/amdkcl: check whether dev_err_once() is available Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- include/kcl/kcl_device.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 include/kcl/kcl_device.h diff --git a/include/kcl/kcl_device.h b/include/kcl/kcl_device.h new file mode 100644 index 0000000000000..41e786bc632fb --- /dev/null +++ b/include/kcl/kcl_device.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_DEVICE_H +#define AMDKCL_DEVICE_H + +/* Copied from include/linux/dev_printk.h */ +#if !defined(dev_err_once) +#ifdef CONFIG_PRINTK +#define dev_level_once(dev_level, dev, fmt, ...) \ +do { \ + static bool __print_once __read_mostly; \ + \ + if (!__print_once) { \ + __print_once = true; \ + dev_level(dev, fmt, ##__VA_ARGS__); \ + } \ +} while (0) +#else +#define dev_level_once(dev_level, dev, fmt, ...) \ +do { \ + if (0) \ + dev_level(dev, fmt, ##__VA_ARGS__); \ +} while (0) +#endif + +#define dev_err_once(dev, fmt, ...) \ + dev_level_once(dev_err, dev, fmt, ##__VA_ARGS__) +#endif +#endif /* AMDKCL_DEVICE_H */ From 4cd76e0cd1a19c7229cf025b3b70dc2ce74f6f57 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sat, 12 Oct 2019 10:34:57 +0800 Subject: [PATCH 0191/2653] drm/amdkcl: check whether dev_err_ratelimited() is available Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Yifan Zhang --- include/kcl/kcl_device.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/include/kcl/kcl_device.h b/include/kcl/kcl_device.h index 41e786bc632fb..d8d3ee5263d06 100644 --- a/include/kcl/kcl_device.h +++ b/include/kcl/kcl_device.h @@ -2,7 +2,8 @@ #ifndef AMDKCL_DEVICE_H #define AMDKCL_DEVICE_H -/* Copied from include/linux/dev_printk.h */ +#include + #if !defined(dev_err_once) #ifdef CONFIG_PRINTK #define dev_level_once(dev_level, dev, fmt, ...) \ @@ -25,4 +26,18 @@ do { \ #define dev_err_once(dev, fmt, ...) \ dev_level_once(dev_err, dev, fmt, ##__VA_ARGS__) #endif + +#if !defined(dev_err_ratelimited) +#define dev_level_ratelimited(dev_level, dev, fmt, ...) \ +do { \ + static DEFINE_RATELIMIT_STATE(_rs, \ + DEFAULT_RATELIMIT_INTERVAL, \ + DEFAULT_RATELIMIT_BURST); \ + if (__ratelimit(&_rs)) \ + dev_level(dev, fmt, ##__VA_ARGS__); \ +} while (0) + +#define dev_err_ratelimited(dev, fmt, ...) \ + dev_level_ratelimited(dev_err, dev, fmt, ##__VA_ARGS__) +#endif #endif /* AMDKCL_DEVICE_H */ From b1c22620d631f0aa0ee30a6fe61ddf8095cc7c07 Mon Sep 17 00:00:00 2001 From: chen gong Date: Thu, 6 Jun 2019 16:24:01 +0800 Subject: [PATCH 0192/2653] drm/amdkcl: Test whether dev_pm_set_driver_flags() is available v2: fake dev_pm_set_driver_flags() Signed-off-by: chen gong Reviewed-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Jiansong Chen Signed-off-by: Yifan Zhang --- .../drm/amd/dkms/m4/dev-pm-set-driver-flags.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_device.h | 15 +++++++++++++++ 3 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dev-pm-set-driver-flags.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/dev-pm-set-driver-flags.m4 b/drivers/gpu/drm/amd/dkms/m4/dev-pm-set-driver-flags.m4 new file mode 100644 index 0000000000000..d1fba526e26d1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dev-pm-set-driver-flags.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v4.14-rc4-21-g08810a4119aa +dnl # Author: Rafael J. Wysocki +dnl # Date: Wed Oct 25 14:12:29 2017 +0200 +dnl # PM / core: Add NEVER_SKIP and SMART_PREPARE driver flags +dnl # +AC_DEFUN([AC_AMDGPU_DEV_PM_SET_DRIVER_FLAGS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dev_pm_set_driver_flags(NULL, 1); + ], [ + AC_DEFINE(HAVE_DEV_PM_SET_DRIVER_FLAGS, 1, + [dev_pm_set_driver_flags() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 42eb904bcfbf9..b431ffea2542b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -14,6 +14,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_I2C_NEW_CLIENT_DEVICE AC_AMDGPU_REQUEST_FIRMWARE_DIRECT AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS + AC_AMDGPU_DEV_PM_SET_DRIVER_FLAGS AC_AMDGPU_COMPAT_PTR_IOCTL AC_AMDGPU_KTHREAD_PARK_XX AC_AMDGPU___KTHREAD_SHOULD_PARK diff --git a/include/kcl/kcl_device.h b/include/kcl/kcl_device.h index d8d3ee5263d06..078622c69af21 100644 --- a/include/kcl/kcl_device.h +++ b/include/kcl/kcl_device.h @@ -3,6 +3,7 @@ #define AMDKCL_DEVICE_H #include +#include #if !defined(dev_err_once) #ifdef CONFIG_PRINTK @@ -40,4 +41,18 @@ do { \ #define dev_err_ratelimited(dev, fmt, ...) \ dev_level_ratelimited(dev_err, dev, fmt, ##__VA_ARGS__) #endif + +#if !defined(HAVE_DEV_PM_SET_DRIVER_FLAGS) +/* rhel7.7 wrap macro dev_pm_set_driver_flags in drm/drm_backport.h */ +#ifdef dev_pm_set_driver_flags +#undef dev_pm_set_driver_flags +#endif +#define DPM_FLAG_NEVER_SKIP BIT(0) +#define DPM_FLAG_SMART_PREPARE BIT(1) +static inline void dev_pm_set_driver_flags(struct device *dev, u32 flags) +{ + printk_once(KERN_WARNING "%s is not available\n", __func__); +} +#endif + #endif /* AMDKCL_DEVICE_H */ From 2cda7f50df1bb127616b3e5b22f8bde40b9499e1 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 11 Oct 2019 13:02:02 +0800 Subject: [PATCH 0193/2653] drm/amdkcl: test whether in_compat_syscall exists in_compat_syscall() is introduced in v4.5-11126-g5180e3e24fd3("compat: add in_compat_syscall to ask whether we're in a compat syscall") macro in_compat_syscall in arch/x86 is introduced in v4.5-11141-gf970165beeaa("x86/compat: remove is_compat_task()") macro in_compat_syscall in include/linux/compat.h is introduced in v4.19-7730-ga846446b1914("x86/compat: Adjust in_compat_syscall() to generic code under !COMPAT") v1: 1c0e722ee1bf drm/amdkcl: [KFD] ALL in One KFD KCL Fix for 4.18 rebase v2: 1f0b1b8c91b5 drm/amd/autoconf: test whether in_compat_syscall exists v3: d37f1868c1b5 drm/amdkcl: refactor test for in_compat_syscall v4: c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Kevin Wang Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Junwei Zhang Reviewed-by: Harish Kasiviswanathan Reviewed-by: Feifei Xu Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Acked-by: Feifei Xu Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/dkms/m4/in-compat-syscall.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_compat.h | 15 +++++++++++++++ 3 files changed, 32 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/in-compat-syscall.m4 create mode 100644 include/kcl/kcl_compat.h diff --git a/drivers/gpu/drm/amd/dkms/m4/in-compat-syscall.m4 b/drivers/gpu/drm/amd/dkms/m4/in-compat-syscall.m4 new file mode 100644 index 0000000000000..45f413011ba01 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/in-compat-syscall.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v4.5-11126-g5180e3e24fd3 +dnl # compat: add in_compat_syscall to ask whether we're in a compat syscall +dnl # +AC_DEFUN([AC_AMDGPU_IN_COMPAT_SYSCALL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + in_compat_syscall(); + ],[ + AC_DEFINE(HAVE_IN_COMPAT_SYSCALL, 1, + [in_compat_syscall is defined]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b431ffea2542b..bc63d79ad4b08 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -22,6 +22,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LIST_IS_FIRST AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS + AC_AMDGPU_IN_COMPAT_SYSCALL AC_AMDGPU_PERF_EVENT_UPDATE_USERPAGE AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP diff --git a/include/kcl/kcl_compat.h b/include/kcl/kcl_compat.h new file mode 100644 index 0000000000000..80bcd236bd4de --- /dev/null +++ b/include/kcl/kcl_compat.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_COMPATE_H +#define AMDKCL_COMPATE_H + +#include + +#if !defined(HAVE_IN_COMPAT_SYSCALL) +#ifdef CONFIG_COMPAT +static inline bool in_compat_syscall(void) { return is_compat_task(); } +#else +static inline bool in_compat_syscall(void) { return false; } +#endif +#endif + +#endif /* AMDKCL_COMPATE_H */ From 089de4c212f36e0a0a80660c218073462bd4f5ce Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Tue, 27 Aug 2019 14:37:02 +0800 Subject: [PATCH 0194/2653] drm/amdkcl: Test whether seq_hex_dump() is available (v2) seq_hex_dump() introduced by kernel v4.3-rc1~22^2~26 v2: fix typo, autconf --> autoconf v3: c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: add kcl copy of seq_hex_dump Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Reviewed-by: Felix Kuehling Change-Id: I040b0b311b0fb9ab81ed32ef57f94407bdffa013 --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c | 57 +++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 | 16 ++++++ include/kcl/kcl_seq_file.h | 17 +++++- 5 files changed, 91 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index dc2f9b9255877..fa37dcffda9fb 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -5,7 +5,7 @@ amdkcl-y += kcl_kernel_params.o amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ - kcl_kthread.o kcl_io.o kcl_perf_event.o \ + kcl_kthread.o kcl_io.o kcl_perf_event.o kcl_seq_file.o\ kcl_suspend.o kcl_pci.o kcl_mm.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c b/drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c new file mode 100644 index 0000000000000..725ca1cafbfc8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * linux/fs/seq_file.c + * + * helper functions for making synthetic files from sequences of records. + * initial implementation -- AV, Oct 2001. + */ +#include + +/* Copied from fs/seq_file.c */ +#ifndef HAVE_SEQ_HEX_DUMP +static void seq_set_overflow(struct seq_file *m) +{ + m->count = m->size; +} + +/* A complete analogue of print_hex_dump() */ +void _kcl_seq_hex_dump(struct seq_file *m, const char *prefix_str, int prefix_type, + int rowsize, int groupsize, const void *buf, size_t len, + bool ascii) +{ + const u8 *ptr = buf; + int i, linelen, remaining = len; + int ret; + + if (rowsize != 16 && rowsize != 32) + rowsize = 16; + + for (i = 0; i < len && !seq_has_overflowed(m); i += rowsize) { + linelen = min(remaining, rowsize); + remaining -= rowsize; + + switch (prefix_type) { + case DUMP_PREFIX_ADDRESS: + seq_printf(m, "%s%p: ", prefix_str, ptr + i); + break; + case DUMP_PREFIX_OFFSET: + seq_printf(m, "%s%.8x: ", prefix_str, i); + break; + default: + seq_printf(m, "%s", prefix_str); + break; + } + + ret = hex_dump_to_buffer(ptr + i, linelen, rowsize, groupsize, + m->buf + m->count, m->size - m->count, + ascii); + if (ret >= m->size - m->count) { + seq_set_overflow(m); + } else { + m->count += ret; + seq_putc(m, '\n'); + } + } +} +EXPORT_SYMBOL(_kcl_seq_hex_dump); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index bc63d79ad4b08..9056ca9df5291 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -24,6 +24,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS AC_AMDGPU_IN_COMPAT_SYSCALL AC_AMDGPU_PERF_EVENT_UPDATE_USERPAGE + AC_AMDGPU_SEQ_HEX_DUMP AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_AMDGPU_KTIME_GET_BOOTTIME_NS diff --git a/drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 b/drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 new file mode 100644 index 0000000000000..5765baa40af2d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 37607102c4426cf92aeb5da1b1d9a79ba6d95e3f +dnl # seq_file: provide an analogue of print_hex_dump() +dnl # +AC_DEFUN([AC_AMDGPU_SEQ_HEX_DUMP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + seq_hex_dump(NULL,NULL,0,0,0,NULL,0,0); + ], [seq_hex_dump],[fs/seq_file.c], [ + AC_DEFINE(HAVE_SEQ_HEX_DUMP, 1, + [seq_hex_dump() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_seq_file.h b/include/kcl/kcl_seq_file.h index 4e7750f341705..b884645a14388 100644 --- a/include/kcl/kcl_seq_file.h +++ b/include/kcl/kcl_seq_file.h @@ -1,7 +1,10 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef AMDKCL_SEQ_FILE_H #define AMDKCL_SEQ_FILE_H +#include + +/* Copied from linux/seq_file.h */ #ifndef DEFINE_SHOW_ATTRIBUTE #define DEFINE_SHOW_ATTRIBUTE(__name) \ static int __name ## _open(struct inode *inode, struct file *file) \ @@ -18,4 +21,16 @@ static const struct file_operations __name ## _fops = { \ } #endif +#ifndef HAVE_SEQ_HEX_DUMP +void _kcl_seq_hex_dump(struct seq_file *m, const char *prefix_str, int prefix_type, + int rowsize, int groupsize, const void *buf, size_t len, + bool ascii); + +static inline void seq_hex_dump(struct seq_file *m, const char *prefix_str, int prefix_type, + int rowsize, int groupsize, const void *buf, size_t len, + bool ascii) +{ + _kcl_seq_hex_dump(m, prefix_str, prefix_type, rowsize, groupsize, buf, len, ascii); +} +#endif #endif From 7c3ddc96594e6b8a14052c0d728958605b0e861a Mon Sep 17 00:00:00 2001 From: Anatoli Antonovitch Date: Thu, 6 Jun 2019 15:58:38 -0400 Subject: [PATCH 0195/2653] drm/amdkcl: Test whether pci_enable_atomic_ops_to_root() is available Signed-off-by: Anatoli Antonovitch Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 87 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../dkms/m4/pcie-enable-atomic-ops-to-root.m4 | 18 ++++ include/kcl/kcl_pci.h | 9 ++ 4 files changed, 115 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pcie-enable-atomic-ops-to-root.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index 3068db5234542..ff2cfbce1e93d 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -97,3 +97,90 @@ void amdkcl_pci_init(void) _kcl_pcie_get_width_cap = amdkcl_fp_setup("pcie_get_width_cap", pcie_get_width_cap); #endif } + +#if !defined(HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT) +/** + * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port + * @dev: the PCI device + * @comp_caps: Caps required for atomic request completion + * + * Return 0 if all upstream bridges support AtomicOp routing, egress + * blocking is disabled on all upstream ports, and the root port + * supports the requested completion capabilities (32-bit, 64-bit + * and/or 128-bit AtomicOp completion), or negative otherwise. + * + */ +int _kcl_pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 comp_caps) +{ + struct pci_bus *bus = dev->bus; + + if (!pci_is_pcie(dev)) + return -EINVAL; + + switch (pci_pcie_type(dev)) { + /* + * PCIe 3.0, 6.15 specifies that endpoints and root ports are permitted + * to implement AtomicOp requester capabilities. + */ + case PCI_EXP_TYPE_ENDPOINT: + case PCI_EXP_TYPE_LEG_END: + case PCI_EXP_TYPE_RC_END: + break; + default: + return -EINVAL; + } + + while (bus->parent) { + struct pci_dev *bridge = bus->self; + u32 cap; + + pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); + + switch (pci_pcie_type(bridge)) { + /* + * Upstream, downstream and root ports may implement AtomicOp + * routing capabilities. AtomicOp routing via a root port is + * not considered. + */ + case PCI_EXP_TYPE_UPSTREAM: + case PCI_EXP_TYPE_DOWNSTREAM: + if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) + return -EINVAL; + break; + + /* + * Root ports are permitted to implement AtomicOp completion + * capabilities. + */ + case PCI_EXP_TYPE_ROOT_PORT: + if ((cap & comp_caps) != comp_caps) + return -EINVAL; + break; + } + + /* + * Upstream ports may block AtomicOps on egress. + */ +#if defined(OS_NAME_RHEL_6) + if (pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM) { +#else + if (!bridge->has_secondary_link) { +#endif + u32 ctl2; + + pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, + &ctl2); + if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_BLOCK) + return -EINVAL; + } + + bus = bus->parent; + } + + pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, + PCI_EXP_DEVCTL2_ATOMIC_REQ); + + return 0; +} +EXPORT_SYMBOL(_kcl_pci_enable_atomic_ops_to_root); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9056ca9df5291..c5c1f79dbcaab 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -27,6 +27,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SEQ_HEX_DUMP AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP + AC_AMDGPU_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES diff --git a/drivers/gpu/drm/amd/dkms/m4/pcie-enable-atomic-ops-to-root.m4 b/drivers/gpu/drm/amd/dkms/m4/pcie-enable-atomic-ops-to-root.m4 new file mode 100644 index 0000000000000..fe1539a268b96 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pcie-enable-atomic-ops-to-root.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 430a23689dea2e36ae5a0fc75a67301fd46b18bf +dnl # Author: Jay Cornwall +dnl # Date: Thu Jan 4 19:44:59 2018 -0500 +dnl # PCI: Add pci_enable_atomic_ops_to_root() +dnl # +AC_DEFUN([AC_AMDGPU_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + pci_enable_atomic_ops_to_root(NULL, 0); + ], [pci_enable_atomic_ops_to_root], [drivers/pci/pci.c], [ + AC_DEFINE(HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT, 1, + [pci_enable_atomic_ops_to_root() exist]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index f6f8425cea3b6..f2d5f416c42cc 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -49,4 +49,13 @@ static inline enum pcie_link_width kcl_pcie_get_width_cap(struct pci_dev *dev) #endif } +#if !defined(HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT) +int _kcl_pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 comp_caps); +static inline +int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) +{ + return _kcl_pci_enable_atomic_ops_to_root(dev, cap_mask); +} +#endif + #endif /* AMDKCL_PCI_H */ From fc37944d713510741a7feeeec6f40d74c0720b80 Mon Sep 17 00:00:00 2001 From: changzhu Date: Mon, 11 Feb 2019 18:10:17 +0800 Subject: [PATCH 0196/2653] drm/amdkcl: Test whether pci_upstream_bridge() is available drm/amdkcl: [3.13] fix implicit declaration of pci_upstream_bridge error [Why] pci_upstream_bridge is not defined before kernel_version(3,13,0). So there is build error when using pci_upstream_bridge in function amdgpu_device_get_min_pci_speed_width(amdgpu_device.c) on redhat 6.10. This kcl patch is for patch: drm/amdgpu: Fix pci platform speed and width [How] Define pci_upstream_bridge in kcl_pci.h when kernel_version<3,13,0. Besides,pci_upstream_bridge is defined on redhat 7.6,although the kernel_version of redha 7.6 is 3.10.0. So we need to use to complete the definition of pci_upstream_bridge. Change-Id: I686d3ad551159a23b28dfc02ed7a4781b053770a Signed-off-by: changzhu Reviewed-by: Rui Teng Signed-off-by: Jack Gui drm/amdkcl: Test whether pci_upstream_bridge() is available Change-Id: I7c0373d0151f6291a188096c299c7c1143c85eaf Signed-off-by: chen gong Reviewed-by: Anatoli Antonovitch Cherry-picked-by: Jack Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/pci-upstream-bridge.m4 | 18 ++++++++++++++++++ include/kcl/kcl_pci.h | 10 ++++++++++ 3 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci-upstream-bridge.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c5c1f79dbcaab..90063d75cf386 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -28,6 +28,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_AMDGPU_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT + AC_AMDGPU_PCI_UPSTREAM_BRIDGE AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-upstream-bridge.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-upstream-bridge.m4 new file mode 100644 index 0000000000000..7d8e48fd14555 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci-upstream-bridge.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit c6bde215acfd637708142ae671843b6f0eadbc6d +dnl # Author: Bjorn Helgaas +dnl # Date: Wed Nov 6 10:11:48 2013 -0700 +dnl # PCI: Add pci_upstream_bridge() +dnl # +AC_DEFUN([AC_AMDGPU_PCI_UPSTREAM_BRIDGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pci_upstream_bridge(NULL); + ], [ + AC_DEFINE(HAVE_PCI_UPSTREAM_BRIDGE, 1, + [pci_upstream_bridge() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index f2d5f416c42cc..8f63e4d16c4f6 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -58,4 +58,14 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) } #endif +#if !defined(HAVE_PCI_UPSTREAM_BRIDGE) +static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) +{ + dev = pci_physfn(dev); + if (pci_is_root_bus(dev->bus)) + return NULL; + + return dev->bus->self; +} +#endif #endif /* AMDKCL_PCI_H */ From 982e52f07a5553a4d6703186951a5757fc5f01b7 Mon Sep 17 00:00:00 2001 From: Amber Lin Date: Mon, 13 May 2019 15:51:11 -0400 Subject: [PATCH 0197/2653] drm/amdkcl: Test whether pcie_bandwidth_available is available Add pcie_bandwidth_available() into autoconf test whether it's available in the kernel. Signed-off-by: Amber Lin Reviewed-by: Slava Grigorev Cherry-picked-by: Jack Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: refactore check for pcie_link_speed Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 86 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/pcie-bandwidth-available.m4 | 16 ++++ include/kcl/kcl_pci.h | 14 +++ 4 files changed, 117 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pcie-bandwidth-available.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index ff2cfbce1e93d..96e4a0c859c83 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -20,6 +20,87 @@ #include #include +#if !defined(HAVE_PCIE_BANDWIDTH_AVAILABLE) +const unsigned char *_kcl_pcie_link_speed; + +const unsigned char _kcl_pcie_link_speed_stub[] = { + PCI_SPEED_UNKNOWN, /* 0 */ + PCIE_SPEED_2_5GT, /* 1 */ + PCIE_SPEED_5_0GT, /* 2 */ + PCIE_SPEED_8_0GT, /* 3 */ + PCI_SPEED_UNKNOWN, /* 4 */ + PCI_SPEED_UNKNOWN, /* 5 */ + PCI_SPEED_UNKNOWN, /* 6 */ + PCI_SPEED_UNKNOWN, /* 7 */ + PCI_SPEED_UNKNOWN, /* 8 */ + PCI_SPEED_UNKNOWN, /* 9 */ + PCI_SPEED_UNKNOWN, /* A */ + PCI_SPEED_UNKNOWN, /* B */ + PCI_SPEED_UNKNOWN, /* C */ + PCI_SPEED_UNKNOWN, /* D */ + PCI_SPEED_UNKNOWN, /* E */ + PCI_SPEED_UNKNOWN /* F */ +}; + +/** + * pcie_bandwidth_available - determine minimum link settings of a PCIe + * device and its bandwidth limitation + * @dev: PCI device to query + * @limiting_dev: storage for device causing the bandwidth limitation + * @speed: storage for speed of limiting device + * @width: storage for width of limiting device + * + * Walk up the PCI device chain and find the point where the minimum + * bandwidth is available. Return the bandwidth available there and (if + * limiting_dev, speed, and width pointers are supplied) information about + * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of + * raw bandwidth. + */ +u32 _kcl_pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, + enum pci_bus_speed *speed, + enum pcie_link_width *width) +{ + u16 lnksta; + enum pci_bus_speed next_speed; + enum pcie_link_width next_width; + u32 bw, next_bw; + + if (speed) + *speed = PCI_SPEED_UNKNOWN; + if (width) + *width = PCIE_LNK_WIDTH_UNKNOWN; + + bw = 0; + + while (dev) { + pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); + + next_speed = _kcl_pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; + next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> + PCI_EXP_LNKSTA_NLW_SHIFT; + + next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed); + + /* Check if current device limits the total bandwidth */ + if (!bw || next_bw <= bw) { + bw = next_bw; + + if (limiting_dev) + *limiting_dev = dev; + if (speed) + *speed = next_speed; + if (width) + *width = next_width; + } + + dev = pci_upstream_bridge(dev); + } + + return bw; +} +EXPORT_SYMBOL(_kcl_pcie_bandwidth_available); +#endif /* HAVE_PCIE_BANDWIDTH_AVAILABLE */ + #if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) /* * pcie_get_speed_cap - query for the PCI device's link speed capability @@ -96,6 +177,9 @@ void amdkcl_pci_init(void) _kcl_pcie_get_speed_cap = amdkcl_fp_setup("pcie_get_speed_cap", pcie_get_speed_cap); _kcl_pcie_get_width_cap = amdkcl_fp_setup("pcie_get_width_cap", pcie_get_width_cap); #endif +#if !defined(HAVE_PCIE_BANDWIDTH_AVAILABLE) + _kcl_pcie_link_speed = (const unsigned char *) amdkcl_fp_setup("pcie_link_speed", _kcl_pcie_link_speed_stub); +#endif } #if !defined(HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT) @@ -184,3 +268,5 @@ int _kcl_pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 comp_caps) } EXPORT_SYMBOL(_kcl_pci_enable_atomic_ops_to_root); #endif + + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 90063d75cf386..0de158e8179fa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -29,6 +29,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_AMDGPU_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT AC_AMDGPU_PCI_UPSTREAM_BRIDGE + AC_AMDGPU_PCIE_BANDWIDTH_AVAILABLE AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES diff --git a/drivers/gpu/drm/amd/dkms/m4/pcie-bandwidth-available.m4 b/drivers/gpu/drm/amd/dkms/m4/pcie-bandwidth-available.m4 new file mode 100644 index 0000000000000..e733ecc72488c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pcie-bandwidth-available.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 6db79a88c67e4679d9c1e4a3f05c6385e21f6e9a +dnl # PCI: Add pcie_bandwidth_available() to compute bandwidth available to device +dnl # +AC_DEFUN([AC_AMDGPU_PCIE_BANDWIDTH_AVAILABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + pcie_bandwidth_available(NULL, NULL, NULL, NULL); + ], [pcie_bandwidth_available], [drivers/pci/pci.c], [ + AC_DEFINE(HAVE_PCIE_BANDWIDTH_AVAILABLE, 1, + [pcie_bandwidth_available() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 8f63e4d16c4f6..7bf37b2644419 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -68,4 +68,18 @@ static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) return dev->bus->self; } #endif + +#if !defined(HAVE_PCIE_BANDWIDTH_AVAILABLE) +u32 _kcl_pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, + enum pci_bus_speed *speed, + enum pcie_link_width *width); +static inline +u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, + enum pci_bus_speed *speed, + enum pcie_link_width *width) +{ + return _kcl_pcie_bandwidth_available(dev, limiting_dev, speed, width); +} +#endif + #endif /* AMDKCL_PCI_H */ From 1807496e280a0d12075ba2fe3a96d2513b531e35 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 13 Sep 2018 15:01:36 +0800 Subject: [PATCH 0198/2653] drm/amdkcl: Enable PCIe Extended Tags if supported commit 60db3a4d8cc9 ("PCI: Enable PCIe Extended Tags if supported") fix rocm bandwidth test H2D case. add the change for kernel < 4.11 v2: export _kcl_pci_configure_extended_tags for dkms support. v3: amd/amdkcl: make sure to enable PCIe Extended Tags if supported Signed-off-by: Flora Cui Reviewed-by: Hawking Zhang Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 + drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 27 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../dkms/m4/pci-configure-extended-tags.m4 | 17 ++++++++++++ include/kcl/kcl_pci.h | 11 ++++++++ 5 files changed, 57 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci-configure-extended-tags.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index efb54c23ba173..f128f8f2f2507 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2403,6 +2403,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; + kcl_pci_configure_extended_tags(pdev); ret = pci_enable_device(pdev); if (ret) return ret; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index 96e4a0c859c83..bf095e454ed06 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -269,4 +269,31 @@ int _kcl_pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 comp_caps) EXPORT_SYMBOL(_kcl_pci_enable_atomic_ops_to_root); #endif +#if !defined(HAVE_PCI_CONFIGURE_EXTENDED_TAGS) +void _kcl_pci_configure_extended_tags(struct pci_dev *dev) +{ + u32 cap; + u16 ctl; + int ret; + + if (!pci_is_pcie(dev)) + return; + + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); + if (ret) + return; + + if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) + return; + ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); + if (ret) + return; + + if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { + pcie_capability_set_word(dev, PCI_EXP_DEVCTL, + PCI_EXP_DEVCTL_EXT_TAG); + } +} +EXPORT_SYMBOL(_kcl_pci_configure_extended_tags); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0de158e8179fa..44686641e93b0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -30,6 +30,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT AC_AMDGPU_PCI_UPSTREAM_BRIDGE AC_AMDGPU_PCIE_BANDWIDTH_AVAILABLE + AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-configure-extended-tags.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-configure-extended-tags.m4 new file mode 100644 index 0000000000000..c46dfedbf7a34 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci-configure-extended-tags.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 62ce94a7a5a54aac80975f5e6731707225d4077e +dnl # PCI: Mark Broadcom HT2100 Root Port Extended Tags as broken +dnl # +AC_DEFUN([AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct pci_host_bridge bridge; + bridge.no_ext_tags = 0; + ], [ + AC_DEFINE(HAVE_PCI_CONFIGURE_EXTENDED_TAGS, 1, + [PCI driver handles extended tags]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 7bf37b2644419..a8f30439b39a8 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -82,4 +82,15 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, } #endif +#if !defined(HAVE_PCI_CONFIGURE_EXTENDED_TAGS) +void _kcl_pci_configure_extended_tags(struct pci_dev *dev); +#endif + +static inline void kcl_pci_configure_extended_tags(struct pci_dev *dev) +{ +#if !defined(HAVE_PCI_CONFIGURE_EXTENDED_TAGS) + _kcl_pci_configure_extended_tags(dev); +#endif +} + #endif /* AMDKCL_PCI_H */ From ed749914bb197076e0767940fef18b8d949fe92c Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Mon, 23 Sep 2019 17:10:03 +0800 Subject: [PATCH 0199/2653] drm/amdkcl: Test whether pci_dev_id() is available Signed-off-by: Adam Yang Signed-off-by: Jack Gui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 | 16 ++++++++++++++++ include/kcl/kcl_pci.h | 6 ++++++ 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 44686641e93b0..2d9f1f12aa0f5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -31,6 +31,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_UPSTREAM_BRIDGE AC_AMDGPU_PCIE_BANDWIDTH_AVAILABLE AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS + AC_AMDGPU_PCI_DEV_ID AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 new file mode 100644 index 0000000000000..29c0928f6bd40 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 4e544bac8267f65a0bf06aed1bde9964da4812ed +dnl # PCI: Add pci_dev_id() helper +dnl # +AC_DEFUN([AC_AMDGPU_PCI_DEV_ID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pci_dev_id(NULL); + ], [ + AC_DEFINE(HAVE_PCI_DEV_ID, 1, + [pci_dev_id() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index a8f30439b39a8..68246cdd08768 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -93,4 +93,10 @@ static inline void kcl_pci_configure_extended_tags(struct pci_dev *dev) #endif } +#if !defined(HAVE_PCI_DEV_ID) +static inline u16 pci_dev_id(struct pci_dev *dev) +{ + return PCI_DEVID(dev->bus->number, dev->devfn); +} +#endif /* HAVE_PCI_DEV_ID */ #endif /* AMDKCL_PCI_H */ From 673ab40b8e4e623cd287a633d6bd6306efb755ad Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Mon, 24 Aug 2020 15:01:34 +0800 Subject: [PATCH 0200/2653] drm/amdkcl: Test whether ktime_get_raw_ns() is available ktime_get_raw_ns introduced by kernel v3.17-rc1~109^2~18 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/ktime-get-raw-ns.m4 | 18 ++++++++++++++++++ include/kcl/kcl_timekeeping.h | 10 ++++++++++ 3 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ktime-get-raw-ns.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2d9f1f12aa0f5..3eb2dadd86279 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -33,6 +33,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS AC_AMDGPU_PCI_DEV_ID AC_AMDGPU_KTIME_GET_BOOTTIME_NS + AC_AMDGPU_KTIME_GET_RAW_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-get-raw-ns.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-get-raw-ns.m4 new file mode 100644 index 0000000000000..e6ae5ff3a6fe0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ktime-get-raw-ns.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v3.16-rc5-99-gf519b1a2e08c +dnl # timekeeping: Provide ktime_get_raw() +dnl # Provide a ktime_t based interface for raw monotonic time. +dnl # +AC_DEFUN([AC_AMDGPU_KTIME_GET_RAW_NS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + ktime_get_raw_ns(); + ], [ + AC_DEFINE(HAVE_KTIME_GET_RAW_NS, 1, + [ktime_get_raw_ns is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_timekeeping.h b/include/kcl/kcl_timekeeping.h index cddc7d78548af..add67d130b167 100644 --- a/include/kcl/kcl_timekeeping.h +++ b/include/kcl/kcl_timekeeping.h @@ -27,4 +27,14 @@ static inline u64 ktime_get_boottime_ns(void) #endif /* HAVE_KTIME_GET_NS */ #endif /* HAVE_KTIME_GET_BOOTTIME_NS */ +#if !defined(HAVE_KTIME_GET_RAW_NS) +static inline u64 ktime_get_raw_ns(void) +{ + struct timespec time; + + getrawmonotonic(&time); + return (u64)timespec_to_ns(&time); +} +#endif + #endif From 34f7af79d87eaa15401c404d66d2870282ae818a Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 19 Sep 2019 16:35:57 +0800 Subject: [PATCH 0201/2653] drm/amdkcl: Test whether ktime_get_real_seconds is available Introduced by kernel v3.19-rc1~153^2 Change-Id: I4fb478b1e84247fb839073fed4cce9ae1a91e06c Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/ktime-get-real-seconds.m4 | 34 +++++++++++++++++++ include/kcl/kcl_timekeeping.h | 10 ++++++ 3 files changed, 45 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3eb2dadd86279..9e93a78cdd592 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -34,6 +34,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_DEV_ID AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_KTIME_GET_RAW_NS + AC_AMDGPU_KTIME_GET_REAL_SECONDS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 new file mode 100644 index 0000000000000..53fe6c0af4523 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 @@ -0,0 +1,34 @@ +dnl # +dnl # commit dbe7aa622db96b5cd601f59d09c4f00b98b76079 +dnl # timekeeping: Provide y2038 safe accessor to the seconds portion of CLOCK_REALTIME +dnl # +AC_DEFUN([AC_AMDGPU_KTIME_GET_REAL_SECONDS_REAL], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ],[ + ktime_get_real_seconds(); + ],[ktime_get_real_seconds],[kernel/time/timekeeping.c],[ + AC_DEFINE(HAVE_KTIME_GET_REAL_SECONDS, 1, + [ktime_get_real_seconds() is available]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_KTIME_GET_REAL_SECONDS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drm_backport.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_get_real_seconds(); + ], [ + AC_DEFINE(HAVE_KTIME_GET_REAL_SECONDS, 1, + [ktime_get_real_seconds() is available in drm_backport.h]) + ], [ + AC_AMDGPU_KTIME_GET_REAL_SECONDS_REAL + ]) + ], [ + AC_AMDGPU_KTIME_GET_REAL_SECONDS_REAL + ]) + ]) +]) diff --git a/include/kcl/kcl_timekeeping.h b/include/kcl/kcl_timekeeping.h index add67d130b167..95378dc3e862b 100644 --- a/include/kcl/kcl_timekeeping.h +++ b/include/kcl/kcl_timekeeping.h @@ -38,3 +38,13 @@ static inline u64 ktime_get_raw_ns(void) #endif #endif + +#ifndef HAVE_KTIME_GET_REAL_SECONDS +static inline time64_t ktime_get_real_seconds(void) +{ + struct timeval ts; + + do_gettimeofday(&ts); + return (time64_t)ts.tv_sec; +} +#endif From 795069a0f8b0d2721b3f35848dd6521491a379a8 Mon Sep 17 00:00:00 2001 From: Jiansong Chen Date: Thu, 7 May 2020 18:00:20 +0800 Subject: [PATCH 0202/2653] drm/amdkcl: add kcl for ktime_get_mono_fast_ns It is introduced in v3.17-rc1, and not available for CentOS7.3 kernel. Now a compromised implementation is added to overcome build issue. Change-Id: Ie04c15f45aeb44a721b573303e1afcd368fe9c0b Signed-off-by: Jiansong Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 | 16 ++++++++++++++++ include/kcl/kcl_timekeeping.h | 11 +++++++++-- 3 files changed, 26 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9e93a78cdd592..387246b62bfb3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -35,6 +35,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_KTIME_GET_RAW_NS AC_AMDGPU_KTIME_GET_REAL_SECONDS + AC_AMDGPU_KTIME_GET_FAST_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 new file mode 100644 index 0000000000000..9e7158950fcbb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v3.16-rc5-111-g4396e058c52e +dnl # timekeeping: Provide fast and NMI safe access to CLOCK_MONOTONIC +dnl # +AC_DEFUN([AC_AMDGPU_KTIME_GET_FAST_NS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_get_mono_fast_ns(); + ], [ + AC_DEFINE(HAVE_KTIME_GET_MONO_FAST_NS, 1, + [ktime_get_mono_fast_ns is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_timekeeping.h b/include/kcl/kcl_timekeeping.h index 95378dc3e862b..7c5bd5b28cb65 100644 --- a/include/kcl/kcl_timekeeping.h +++ b/include/kcl/kcl_timekeeping.h @@ -37,8 +37,6 @@ static inline u64 ktime_get_raw_ns(void) } #endif -#endif - #ifndef HAVE_KTIME_GET_REAL_SECONDS static inline time64_t ktime_get_real_seconds(void) { @@ -48,3 +46,12 @@ static inline time64_t ktime_get_real_seconds(void) return (time64_t)ts.tv_sec; } #endif + +#if !defined(HAVE_KTIME_GET_MONO_FAST_NS) +static inline u64 ktime_get_mono_fast_ns(void) +{ + return ktime_to_ns(ktime_get()); +} +#endif + +#endif From bd1538998537856163e8e34c9966027f26ea3c67 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 16:43:38 +0800 Subject: [PATCH 0203/2653] drm/amdkcl: Test whether memalloc_nofs_{save/restore}() are available Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/memalloc-nofs-save.m4 | 17 +++++++++++++++++ include/kcl/kcl_mm.h | 11 +++++++++++ 3 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/memalloc-nofs-save.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 387246b62bfb3..ebcca8071fd0e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -36,6 +36,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTIME_GET_RAW_NS AC_AMDGPU_KTIME_GET_REAL_SECONDS AC_AMDGPU_KTIME_GET_FAST_NS + AC_AMDGPU_MEMALLOC_NOFS_SAVE AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/memalloc-nofs-save.m4 b/drivers/gpu/drm/amd/dkms/m4/memalloc-nofs-save.m4 new file mode 100644 index 0000000000000..64d78a728898d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/memalloc-nofs-save.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 7dea19f9ee636cb244109a4dba426bbb3e5304b7 +dnl # mm: introduce memalloc_nofs_{save,restore} API +dnl # +AC_DEFUN([AC_AMDGPU_MEMALLOC_NOFS_SAVE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + memalloc_nofs_save(); + memalloc_nofs_restore(0); + ], [ + AC_DEFINE(HAVE_MEMALLOC_NOFS_SAVE, 1, + [memalloc_nofs_{save,restore}() are available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index f7616dde77031..cd1a3de986863 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -22,4 +22,15 @@ static inline bool fault_flag_allow_retry_first(unsigned int flags) } #endif +#if !defined(HAVE_MEMALLOC_NOFS_SAVE) +static inline unsigned int memalloc_nofs_save(void) +{ + return current->flags; +} + +static inline void memalloc_nofs_restore(unsigned int flags) +{ +} +#endif + #endif /* AMDKCL_MM_H */ From 86e28acc0a4804ea270c886100fc5d0001bad32d Mon Sep 17 00:00:00 2001 From: chen gong Date: Tue, 4 Jun 2019 16:33:34 +0800 Subject: [PATCH 0204/2653] drm/amdkcl: Test whether zone_managed_pages() is available Signed-off-by: chen gong Reviewed-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/zone-managed-pages.m4 | 32 +++++++++++++++++++ include/kcl/kcl_mm.h | 13 ++++++++ 3 files changed, 46 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/zone-managed-pages.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ebcca8071fd0e..238cf6ece6a42 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -37,6 +37,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTIME_GET_REAL_SECONDS AC_AMDGPU_KTIME_GET_FAST_NS AC_AMDGPU_MEMALLOC_NOFS_SAVE + AC_AMDGPU_ZONE_MANAGED_PAGES AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/zone-managed-pages.m4 b/drivers/gpu/drm/amd/dkms/m4/zone-managed-pages.m4 new file mode 100644 index 0000000000000..a1228bf4f67ac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/zone-managed-pages.m4 @@ -0,0 +1,32 @@ +dnl # +dnl # commit v4.20-6505-g9705bea5f833 +dnl # Author: Arun KS +dnl # Date: Fri Dec 28 00:34:24 2018 -0800 +dnl # mm: convert zone->managed_pages to atomic variable +dnl # +AC_DEFUN([AC_AMDGPU_ZONE_MANAGED_PAGES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + zone_managed_pages(NULL); + ],[ + AC_DEFINE(HAVE_ZONE_MANAGED_PAGES, 1, + [zone_managed_pages() is available]) + ],[ + dnl # + dnl # commit v3.7-4152-g9feedc9d831e + dnl # mm: introduce new field "managed_pages" to struct zone + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct zone *z = NULL; + z->managed_pages = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_ZONE_MANAGED_PAGES, 1, + [zone->managed_pages is available]) + ]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index cd1a3de986863..00c4b4edd62be 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -33,4 +33,17 @@ static inline void memalloc_nofs_restore(unsigned int flags) } #endif +#if !defined(HAVE_ZONE_MANAGED_PAGES) +static inline unsigned long zone_managed_pages(struct zone *zone) +{ +#if defined(HAVE_STRUCT_ZONE_MANAGED_PAGES) + return (unsigned long)zone->managed_pages; +#else + /* zone->managed_pages is introduced in v3.7-4152-g9feedc9d831e */ + WARN_ONCE(1, "struct zone->managed_pages don't exist. kernel is a bit old..."); + return 0; +#endif +} +#endif /* HAVE_ZONE_MANAGED_PAGES */ + #endif /* AMDKCL_MM_H */ From 190b5711d8635f61cb916529de97a0ccd895bbc2 Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Tue, 26 Jun 2018 10:31:19 +0800 Subject: [PATCH 0205/2653] drm/amdkcl: Test whether vmf_insert_*() functions are available drm/amdkcl: [4.16] add kcl/kcl_mm_types.h file for ttm compatibility Signed-off-by: Prike Liang Reviewed-by: Tao Zhou Signed-off-by: Jack Gui drm/amdkcl: Test whether vmf_insert_*() functions are available Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amd/autoconf: refactor kcl_mm_types.h Signed-off-by: Flora Cui Reviewed-by: Jack Gui drm/amdkcl: drop HAVE_PFN_T check outside of kcl Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: move kcl copy of vmf_* to kcl_mm.h Reviewed-by: Yifan Zhang Signed-off-by: Flora Cui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 | 45 +++++++++++++++++++++++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_memory.h | 39 ++++++++++++++++++++ include/kcl/kcl_mm.h | 7 ++++ include/kcl/kcl_mm_types.h | 39 ++++++++++++++++++++ 6 files changed, 133 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 create mode 100644 include/kcl/kcl_memory.h create mode 100644 include/kcl/kcl_mm_types.h diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 238cf6ece6a42..95dfc6fcbd59b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -38,6 +38,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTIME_GET_FAST_NS AC_AMDGPU_MEMALLOC_NOFS_SAVE AC_AMDGPU_ZONE_MANAGED_PAGES + AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST + AC_AMDGPU_VMF_INSERT AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS @@ -52,7 +54,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_KTHREAD_USE_MM - AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 new file mode 100644 index 0000000000000..89789fd059839 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 @@ -0,0 +1,45 @@ +dnl # +dnl # commit v4.4-6466-g34c0fd540e79 +dnl # mm, dax, pmem: introduce pfn_t +dnl # +AC_DEFUN([AC_AMDGPU_VMF_INSERT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pfn_t pfn; + pfn.val = 0; + ], [ + dnl # + dnl # commit v4.16-7358-g1c8f422059ae + dnl # mm: change return type to vm_fault_t + dnl # + AC_DEFINE(HAVE_PFN_T, 1, [pfn_t is defined]) + + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pfn_t pfn = {}; + vmf_insert_mixed(NULL, 0, pfn); + vmf_insert_pfn(NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_VMF_INSERT, 1, + [vmf_insert_*() are available]) + ], [ + dnl # + dnl # commit v4.4-6475-g01c8f1c44b83 + dnl # mm, dax, gpu: convert vm_insert_mixed to pfn_t + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + pfn_t pfn = {}; + vm_insert_mixed(NULL, 0, pfn); + ], [vm_insert_mixed], [mm/memory.c], [ + AC_DEFINE(HAVE_PFN_T_VM_INSERT_MIXED, 1, + [vm_insert_mixed() wants pfn_t arg]) + ]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 9f3fbf350006e..659a7f1e254c4 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -8,4 +8,5 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_memory.h b/include/kcl/kcl_memory.h new file mode 100644 index 0000000000000..f5ad19a510fe8 --- /dev/null +++ b/include/kcl/kcl_memory.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_MEMORY_H +#define _KCL_KCL_MEMORY_H + +#ifndef HAVE_VMF_INSERT +static inline vm_fault_t vmf_insert_mixed(struct vm_area_struct *vma, + unsigned long addr, + pfn_t pfn) +{ + int err; +#if !defined(HAVE_PFN_T_VM_INSERT_MIXED) + err = vm_insert_mixed(vma, addr, pfn_t_to_pfn(pfn)); +#else + err = vm_insert_mixed(vma, addr, pfn); +#endif + if (err == -ENOMEM) + return VM_FAULT_OOM; + if (err < 0 && err != -EBUSY) + return VM_FAULT_SIGBUS; + + return VM_FAULT_NOPAGE; +} + +static inline vm_fault_t vmf_insert_pfn(struct vm_area_struct *vma, + unsigned long addr, unsigned long pfn) +{ + int err = vm_insert_pfn(vma, addr, pfn); + + if (err == -ENOMEM) + return VM_FAULT_OOM; + if (err < 0 && err != -EBUSY) + return VM_FAULT_SIGBUS; + + return VM_FAULT_NOPAGE; +} + +#endif /* HAVE_VMF_INSERT */ + +#endif diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 00c4b4edd62be..348b7570b6726 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -7,7 +7,14 @@ #ifndef AMDKCL_MM_H #define AMDKCL_MM_H +#include +#include +#include #include +#include +#include +#include +#include #ifndef untagged_addr /* Copied from include/linux/mm.h */ diff --git a/include/kcl/kcl_mm_types.h b/include/kcl/kcl_mm_types.h new file mode 100644 index 0000000000000..6cf223e559d02 --- /dev/null +++ b/include/kcl/kcl_mm_types.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_MM_TYPES_H +#define AMDKCL_MM_TYPES_H + +#include +#ifdef HAVE_PFN_T +#include +#else +/* Copied from include/linux/pfn_t.h */ +typedef struct { + u64 val; +} pfn_t; + +#define PFN_FLAGS_MASK (((unsigned long) ~PAGE_MASK) \ + << (BITS_PER_LONG - PAGE_SHIFT)) +#define PFN_SG_CHAIN (1UL << (BITS_PER_LONG - 1)) +#define PFN_SG_LAST (1UL << (BITS_PER_LONG - 2)) +#define PFN_DEV (1UL << (BITS_PER_LONG - 3)) +#define PFN_MAP (1UL << (BITS_PER_LONG - 4)) + +static inline pfn_t __pfn_to_pfn_t(unsigned long pfn, unsigned long flags) +{ + pfn_t pfn_t = { .val = pfn | (flags & PFN_FLAGS_MASK), }; + + return pfn_t; +} + +static inline unsigned long pfn_t_to_pfn(pfn_t pfn) +{ + return pfn.val & ~PFN_FLAGS_MASK; +} +#endif + +#ifndef HAVE_VMF_INSERT +typedef int vm_fault_t; +#endif + +#endif /* AMDKCL_MM_TYPES_H */ + From 17d5d12d6b325a01d602bf564f4d1d99516f5daf Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 27 Aug 2020 16:31:58 +0800 Subject: [PATCH 0206/2653] drm/amdkcl: fake kcl copy of mmap_read_lock/unlock apis v2: c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- include/kcl/kcl_mm.h | 1 + include/kcl/kcl_mmap_lock.h | 48 +++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 include/kcl/kcl_mmap_lock.h diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 348b7570b6726..b4e18dfd764fe 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -13,6 +13,7 @@ #include #include #include +#include #include #include diff --git a/include/kcl/kcl_mmap_lock.h b/include/kcl/kcl_mmap_lock.h new file mode 100644 index 0000000000000..b677506d80cf1 --- /dev/null +++ b/include/kcl/kcl_mmap_lock.h @@ -0,0 +1,48 @@ +#ifndef KCL_KCL_MMAP_LOCK_H +#define KCL_KCL_MMAP_LOCK_H + +#ifdef HAVE_LINUX_MMAP_LOCK_H +#include +#else +/* Copied from include/linux/mmap_lock.h */ +static inline void mmap_init_lock(struct mm_struct *mm) +{ + init_rwsem(&mm->mmap_sem); +} + +static inline void mmap_write_lock(struct mm_struct *mm) +{ + down_write(&mm->mmap_sem); +} + +static inline bool mmap_write_trylock(struct mm_struct *mm) +{ + return down_write_trylock(&mm->mmap_sem) != 0; +} + +static inline void mmap_write_unlock(struct mm_struct *mm) +{ + up_write(&mm->mmap_sem); +} + +static inline void mmap_write_downgrade(struct mm_struct *mm) +{ + downgrade_write(&mm->mmap_sem); +} + +static inline void mmap_read_lock(struct mm_struct *mm) +{ + down_read(&mm->mmap_sem); +} + +static inline bool mmap_read_trylock(struct mm_struct *mm) +{ + return down_read_trylock(&mm->mmap_sem) != 0; +} + +static inline void mmap_read_unlock(struct mm_struct *mm) +{ + up_read(&mm->mmap_sem); +} +#endif +#endif /* KCL_KCL_MMAP_LOCK_H */ From cbdecd60ecb82c4571783423f0baf55f149035ae Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 14 Apr 2020 18:18:15 +0800 Subject: [PATCH 0207/2653] drm/amdkcl: test whether vmf_insert_mixed_prot() is available Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_memory.c | 15 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 | 20 +++++++++++++++++++ include/kcl/kcl_memory.h | 11 ++++++++++ 5 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_memory.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index fa37dcffda9fb..d2b9a7043ca89 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -6,7 +6,7 @@ amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o kcl_seq_file.o\ - kcl_suspend.o kcl_pci.o kcl_mm.o \ + kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o\ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_connector.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c new file mode 100644 index 0000000000000..fa13000906721 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +#include + +#ifndef HAVE_VMF_INSERT_MIXED_PROT +vm_fault_t _kcl_vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, + pfn_t pfn, pgprot_t pgprot) +{ + struct vm_area_struct cvma = *vma; + + cvma.vm_page_prot = pgprot; + + return vmf_insert_mixed(&cvma, addr, pfn); +} +EXPORT_SYMBOL(_kcl_vmf_insert_mixed_prot); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 95dfc6fcbd59b..71ddfb7706886 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -40,6 +40,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ZONE_MANAGED_PAGES AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_AMDGPU_VMF_INSERT + AC_AMDGPU_VMF_INSERT_MIXED_PROT AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 new file mode 100644 index 0000000000000..53da9747196ea --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # 5379e4dd3220 mm, drm/ttm: Fix vm page protection handling +dnl # 574c5b3d0e4c mm: Add a vmf_insert_mixed_prot() function +dnl # +AC_DEFUN([AC_AMDGPU_VMF_INSERT_MIXED_PROT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ],[ + pfn_t pfn; + pgprot_t prot; + vmf_insert_mixed_prot(NULL, 0, pfn, prot); + ],[vmf_insert_mixed_prot],[mm/memory.c],[ + AC_DEFINE(HAVE_VMF_INSERT_MIXED_PROT, + 1, + [vmf_insert_mixed_prot() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_memory.h b/include/kcl/kcl_memory.h index f5ad19a510fe8..5c7e4817d92f9 100644 --- a/include/kcl/kcl_memory.h +++ b/include/kcl/kcl_memory.h @@ -36,4 +36,15 @@ static inline vm_fault_t vmf_insert_pfn(struct vm_area_struct *vma, #endif /* HAVE_VMF_INSERT */ +#ifndef HAVE_VMF_INSERT_MIXED_PROT +vm_fault_t _kcl_vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, + pfn_t pfn, pgprot_t pgprot); +static inline +vm_fault_t vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, + pfn_t pfn, pgprot_t pgprot) +{ + return _kcl_vmf_insert_mixed_prot(vma, addr, pfn, pgprot); +} +#endif /* HAVE_VMF_INSERT_MIXED_PROT */ + #endif From a4f6f8e904e3769f70acb0aeb74b156390b0f570 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Apr 2020 18:07:17 +0800 Subject: [PATCH 0208/2653] drm/amdkcl: fake a kcl copy of vmf_insert_pfn_prot() Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_memory.c | 28 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 | 35 +++++++++++++++++++ include/kcl/kcl_memory.h | 11 ++++++ 4 files changed, 75 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c index fa13000906721..9d5358ca93b48 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c @@ -13,3 +13,31 @@ vm_fault_t _kcl_vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long } EXPORT_SYMBOL(_kcl_vmf_insert_mixed_prot); #endif + +#ifndef HAVE_VMF_INSERT_PFN_PROT +#ifndef HAVE_VM_INSERT_PFN_PROT +int vm_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn, pgprot_t pgprot) +{ + struct vm_area_struct cvma = *vma; + + cvma.vm_page_prot = pgprot; + + return vm_insert_pfn(&cvma, addr, pfn); +} +#endif + +vm_fault_t _kcl_vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn, pgprot_t pgprot) +{ + int err = vm_insert_pfn_prot(vma, addr, pfn, pgprot); + + if (err == -ENOMEM) + return VM_FAULT_OOM; + if (err < 0 && err != -EBUSY) + return VM_FAULT_SIGBUS; + + return VM_FAULT_NOPAGE; +} +EXPORT_SYMBOL(_kcl_vmf_insert_pfn_prot); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 71ddfb7706886..86e431587638c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -41,6 +41,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_AMDGPU_VMF_INSERT AC_AMDGPU_VMF_INSERT_MIXED_PROT + AC_AMDGPU_VMF_INSERT_PFN_PROT AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 new file mode 100644 index 0000000000000..d1f869507e4dd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 @@ -0,0 +1,35 @@ +dnl # +dnl # commit v4.19-6927-gf5e6d1d5f8f3 +dnl # mm: introduce vmf_insert_pfn_prot() +dnl # +AC_DEFUN([AC_AMDGPU_VMF_INSERT_PFN_PROT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + pgprot_t prot; + vmf_insert_pfn_prot(NULL, 0, 0, prot); + ],[ + AC_DEFINE(HAVE_VMF_INSERT_PFN_PROT, + 1, + [vmf_insert_pfn_prot() is available]) + ],[ + dnl # + dnl # commit v4.4-528-g1745cbc5d0de + dnl # mm: Add vm_insert_pfn_prot() + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + pgprot_t prot; + vm_insert_pfn_prot(NULL, 0, 0, prot); + ],[ + AC_DEFINE(HAVE_VM_INSERT_PFN_PROT, + 1, + [vm_insert_pfn_prot() is available]) + ]) + ]) + ]) +]) diff --git a/include/kcl/kcl_memory.h b/include/kcl/kcl_memory.h index 5c7e4817d92f9..e0dac3be04b47 100644 --- a/include/kcl/kcl_memory.h +++ b/include/kcl/kcl_memory.h @@ -47,4 +47,15 @@ vm_fault_t vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, } #endif /* HAVE_VMF_INSERT_MIXED_PROT */ +#ifndef HAVE_VMF_INSERT_PFN_PROT +vm_fault_t _kcl_vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn, pgprot_t pgprot); +static inline +vm_fault_t vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn, pgprot_t pgprot) +{ + return _kcl_vmf_insert_pfn_prot(vma, addr, pfn, pgprot); +} +#endif /* HAVE_VMF_INSERT_PFN_PROT */ + #endif From ee7369af5210816c70f90c856ba2cd2e93a980db Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 3 Sep 2020 17:40:25 +0800 Subject: [PATCH 0209/2653] drm/amdkcl: test sched_set_fifo_low() v2: c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 4 +-- drivers/gpu/drm/amd/amdkcl/kcl_sched.c | 30 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 | 13 ++++++++ drivers/gpu/drm/scheduler/backport/backport.h | 1 + include/kcl/kcl_sched.h | 12 ++++++++ 7 files changed, 61 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_sched.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 create mode 100644 include/kcl/kcl_sched.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index d2b9a7043ca89..893aca5bc08d2 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -5,8 +5,8 @@ amdkcl-y += kcl_kernel_params.o amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ - kcl_kthread.o kcl_io.o kcl_perf_event.o kcl_seq_file.o\ - kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o\ + kcl_kthread.o kcl_io.o kcl_perf_event.o kcl_seq_file.o \ + kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_connector.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_sched.c b/drivers/gpu/drm/amd/amdkcl/kcl_sched.c new file mode 100644 index 0000000000000..e57b29e7a7a73 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_sched.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * kernel/sched/core.c + * + * Core kernel scheduler code and related syscalls + * + * Copyright (C) 1991-2002 Linus Torvalds + */ + +#include + +/* Copied from kernel/sched/core.c and modified for KCL */ +#ifndef HAVE_SCHED_SET_FIFO_LOW +int (*_kcl_sched_setscheduler_nocheck)(struct task_struct *p, int policy, + const struct sched_param *param); +void sched_set_fifo_low(struct task_struct *p) +{ + struct sched_param sp = { .sched_priority = 1 }; + WARN_ON_ONCE(_kcl_sched_setscheduler_nocheck(p, SCHED_FIFO, &sp) != 0); +} +EXPORT_SYMBOL_GPL(sched_set_fifo_low); +#endif + +void amdkcl_sched_init(void) +{ +#ifndef HAVE_SCHED_SET_FIFO_LOW + _kcl_sched_setscheduler_nocheck = amdkcl_fp_setup("sched_setscheduler_nocheck", + NULL); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 6dc78f4f4f851..b99b4ca0f9880 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -11,6 +11,7 @@ extern void amdkcl_mm_init(void); extern void amdkcl_perf_event_init(void); extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); +extern void amdkcl_sched_init(void); int __init amdkcl_init(void) { @@ -23,6 +24,7 @@ int __init amdkcl_init(void) amdkcl_perf_event_init(); amdkcl_pci_init(); amdkcl_suspend_init(); + amdkcl_sched_init(); return 0; } diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 86e431587638c..014b74e5b590f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -44,6 +44,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMF_INSERT_PFN_PROT AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES + AC_AMDGPU_SCHED_SET_FIFO_LOW AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_SG_TT_INIT diff --git a/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 b/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 new file mode 100644 index 0000000000000..422b5d833b653 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # v5.8-rc1-23-g7318d4cc14c8 +dnl # sched: Provide sched_set_fifo() +dnl # +AC_DEFUN([AC_AMDGPU_SCHED_SET_FIFO_LOW], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([sched_set_fifo_low], + [kernel/sched/core.c], [ + AC_DEFINE(HAVE_SCHED_SET_FIFO_LOW, 1, + [sched_set_fifo_low() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 4a62c9677187a..46537c0094114 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -6,4 +6,5 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_sched.h b/include/kcl/kcl_sched.h new file mode 100644 index 0000000000000..2ed8d6a01cd1f --- /dev/null +++ b/include/kcl/kcl_sched.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_SCHED_H +#define _KCL_KCL_SCHED_H + +#include +#include + +#ifndef HAVE_SCHED_SET_FIFO_LOW +void sched_set_fifo_low(struct task_struct *p); +#endif + +#endif From 7863d10c5280ce5fe0db50cc32ed61b233e7250c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 17 Jun 2020 13:08:42 +0800 Subject: [PATCH 0210/2653] drm/amdkcl: fake drm_helper_mode_fill_fb_struct() drm_helper_mode_fill_fb_struct() prototype change in commit v4.9-rc8-1643-ga3f913ca9892 Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c | 11 +++++++++++ .../dkms/m4/drm_helper_mode_fill_fb_struct.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_fb.h | 5 +++++ include/kcl/kcl_drm_fb.h | 7 +++++++ 5 files changed, 40 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c index 900629e0dc0ed..c2203e2ede030 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -49,3 +49,14 @@ void _kcl_drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, in } EXPORT_SYMBOL(_kcl_drm_fb_helper_set_suspend_unlocked); #endif + +#ifndef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV +void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, + struct drm_framebuffer *fb, + const struct drm_mode_fb_cmd2 *mode_cmd) +{ + fb->dev = dev; + drm_helper_mode_fill_fb_struct(fb, mode_cmd); +} +EXPORT_SYMBOL(_kcl_drm_helper_mode_fill_fb_struct); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 new file mode 100644 index 0000000000000..3d662319c8e11 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v4.9-rc8-1647-g95bce7601581 drm: Populate fb->dev from drm_helper_mode_fill_fb_struct() +dnl # v4.9-rc8-1643-ga3f913ca9892 drm: Pass 'dev' to drm_helper_mode_fill_fb_struct() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_helper_mode_fill_fb_struct(NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV, 1, + [drm_helper_mode_fill_fb_struct() wants dev arg]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 014b74e5b590f..e4d58dc65dc7b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -60,6 +60,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED + AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index c83d4ffd135b4..85af1711c5a92 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -28,4 +28,9 @@ #if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP) #define drm_fb_helper_remove_conflicting_pci_framebuffers _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers #endif + +#ifndef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV +#define drm_helper_mode_fill_fb_struct _kcl_drm_helper_mode_fill_fb_struct +#endif + #endif diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 76b6ade463704..cd950f495e36b 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -32,6 +32,7 @@ #include #include +#include #include #if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) @@ -94,4 +95,10 @@ void drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, } #endif +#ifndef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV +void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, + struct drm_framebuffer *fb, + const struct drm_mode_fb_cmd2 *mode_cmd); +#endif + #endif From aa28a1628287ab750bb37a44b6798ddb780f45f6 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 16 Dec 2020 16:41:10 +0800 Subject: [PATCH 0211/2653] drm/amdkcl: rework kcl faked drm_helper_mode_fill_fb_struct no need to add a _kcl_ symbol Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c | 11 ----------- include/kcl/backport/kcl_drm_fb.h | 9 +++++++++ include/kcl/kcl_drm_fb.h | 7 ------- 3 files changed, 9 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c index c2203e2ede030..900629e0dc0ed 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -49,14 +49,3 @@ void _kcl_drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, in } EXPORT_SYMBOL(_kcl_drm_fb_helper_set_suspend_unlocked); #endif - -#ifndef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV -void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, - struct drm_framebuffer *fb, - const struct drm_mode_fb_cmd2 *mode_cmd) -{ - fb->dev = dev; - drm_helper_mode_fill_fb_struct(fb, mode_cmd); -} -EXPORT_SYMBOL(_kcl_drm_helper_mode_fill_fb_struct); -#endif diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index 85af1711c5a92..fd7f828ca96fd 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -30,6 +30,15 @@ #endif #ifndef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV +static inline +void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, + struct drm_framebuffer *fb, + const struct drm_mode_fb_cmd2 *mode_cmd) +{ + fb->dev = dev; + drm_helper_mode_fill_fb_struct(fb, mode_cmd); +} + #define drm_helper_mode_fill_fb_struct _kcl_drm_helper_mode_fill_fb_struct #endif diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index cd950f495e36b..0954d658644a8 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -94,11 +94,4 @@ void drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, _kcl_drm_fb_helper_set_suspend_unlocked(fb_helper, suspend); } #endif - -#ifndef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV -void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, - struct drm_framebuffer *fb, - const struct drm_mode_fb_cmd2 *mode_cmd); -#endif - #endif From 0e57d7830f0c2a617df624cc65567dc662fc3f8d Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 10 Jul 2018 16:25:09 -0400 Subject: [PATCH 0212/2653] drm/amdkcl: Test whether drm_crtc_force_disable_all() is available v2: drm/amdkcl: fix drm_crtc_force_disable_all v3: drm/amdkcl: fix license for kcl drm part Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Reviewed-by: Felix Kuehling Change-Id: Iceb48227e9cf51f819af21ceb5ba231e3750dd6b --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c | 79 +++++++++++++++++++ .../amd/dkms/m4/drm-crtc-force-disable-all.m4 | 16 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_crtc.h | 6 ++ 5 files changed, 103 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-crtc-force-disable-all.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 893aca5bc08d2..3de8b0d51ffcb 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -9,7 +9,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ - kcl_connector.o + kcl_drm_crtc.o kcl_connector.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c new file mode 100644 index 0000000000000..0dab372fcb93f --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * Copyright (c) 2008 Red Hat Inc. + * + * DRM core CRTC related functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Keith Packard + * Eric Anholt + * Dave Airlie + * Jesse Barnes + */ +#include + +#if !defined(HAVE_DRM_CRTC_FORCE_DISABLE_ALL) +/** + * drm_crtc_force_disable - Forcibly turn off a CRTC + * @crtc: CRTC to turn off + * + * Returns: + * Zero on success, error code on failure. + */ +int drm_crtc_force_disable(struct drm_crtc *crtc) +{ + struct drm_mode_set set = { + .crtc = crtc, + }; + + return drm_mode_set_config_internal(&set); +} +EXPORT_SYMBOL(drm_crtc_force_disable); + +/** + * drm_crtc_force_disable_all - Forcibly turn off all enabled CRTCs + * @dev: DRM device whose CRTCs to turn off + * + * Drivers may want to call this on unload to ensure that all displays are + * unlit and the GPU is in a consistent, low power state. Takes modeset locks. + * + * Returns: + * Zero on success, error code on failure. + */ +int drm_crtc_force_disable_all(struct drm_device *dev) +{ + struct drm_crtc *crtc; + int ret = 0; + + drm_modeset_lock_all(dev); + drm_for_each_crtc(crtc, dev) + if (crtc->enabled) { + ret = drm_crtc_force_disable(crtc); + if (ret) + goto out; + } +out: + drm_modeset_unlock_all(dev); + return ret; +} +EXPORT_SYMBOL(drm_crtc_force_disable_all); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-force-disable-all.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-force-disable-all.m4 new file mode 100644 index 0000000000000..68ccba497ae81 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-force-disable-all.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 6a0d95285035c43361c72776b4c618f60c0f4ab4 +dnl # drm: Add helpers to turn off CRTCs +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_FORCE_DISABLE_ALL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_crtc_force_disable_all(NULL); + ], [drm_crtc_force_disable_all], [drivers/gpu/drm/drm_crtc.c], [ + AC_DEFINE(HAVE_DRM_CRTC_FORCE_DISABLE_ALL, 1, + [drm_crtc_force_disable_all() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e4d58dc65dc7b..1d23e06f8e2b4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -61,6 +61,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT + AC_AMDGPU_DRM_CRTC_FORCE_DISABLE_ALL AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h index f027ec142c74e..38861d70bd9bb 100644 --- a/include/kcl/kcl_drm_crtc.h +++ b/include/kcl/kcl_drm_crtc.h @@ -50,6 +50,7 @@ #include #include +#include /* Copied from include/drm/drm_mode.h */ #ifndef DRM_MODE_ROTATE_0 @@ -73,4 +74,9 @@ DRM_MODE_ROTATE_270) #endif +#if !defined(HAVE_DRM_CRTC_FORCE_DISABLE_ALL) +extern int drm_crtc_force_disable(struct drm_crtc *crtc); +extern int drm_crtc_force_disable_all(struct drm_device *dev); +#endif + #endif From df69b0743fe7aac7534e3c5cb5cd00619a77c784 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 22 Oct 2019 14:16:22 +0800 Subject: [PATCH 0213/2653] drm/amdkcl: fix drm_add_edid_modes & drm_edid_to_eld drm_edid_to_eld() is moved to drm_add_edid_modes() in commit v4.14-rc3-592-gc945b8c14bb7 and is set to static in commit v4.14-rc3-594-g79436a1c9bcc HAVE_DRM_EDID_TO_ELD check could help to avoid duplicated drm_edid_to_eld() in most cases. Signed-off-by: Flora Cui Reviewed-by: Nicholas Kazlauskas Signed-off-by: Jiansong Chen Signed-off-by: Yifan Zhang Change-Id: Id7c442179d03f891274ecfa549ea26c16e68fa4e --- .../gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 | 19 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_encoder.h | 56 +++++++++++++++++++ 3 files changed, 76 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 create mode 100644 include/kcl/backport/kcl_drm_encoder.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 new file mode 100644 index 0000000000000..f0efb113db67b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit v4.14-rc3-594-g79436a1c9bcc +dnl # drm/edid: make drm_edid_to_eld() static +dnl # +dnl # commit v3.1-rc6-139-g76adaa34db40 +dnl # drm: support routines for HDMI/DP ELD +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_TO_ELD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_edid_to_eld(NULL, NULL); + ], [drm_edid_to_eld], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_EDID_TO_ELD, 1, + [drm_edid_to_eld() are available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1d23e06f8e2b4..a7b5ccceb8d07 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -62,6 +62,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_CRTC_FORCE_DISABLE_ALL + AC_AMDGPU_DRM_EDID_TO_ELD AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_encoder.h b/include/kcl/backport/kcl_drm_encoder.h new file mode 100644 index 0000000000000..07e3a75541b80 --- /dev/null +++ b/include/kcl/backport/kcl_drm_encoder.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2006 Luc Verhaegen (quirks list) + * Copyright (c) 2007-2008 Intel Corporation + * Jesse Barnes + * Copyright 2010 Red Hat, Inc. + * + * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from + * FB layer. + * Copyright (C) 2006 Dennis Munsie + * For codes copied from drivers/gpu/drm/drm_edid.c + * + * Copyright (c) 2016 Intel Corporation + * For codes copied from include/drm/drm_encoder.h + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef KCL_BACKPORT_KCL_DRM_ENCODER_H +#define KCL_BACKPORT_KCL_DRM_ENCODER_H + +#include +#include + +#if defined(HAVE_DRM_EDID_TO_ELD) +static inline +int _kcl_drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) +{ + int ret; + + ret = drm_add_edid_modes(connector, edid); + + if (drm_edid_is_valid(edid)) + drm_edid_to_eld(connector, edid); + + return ret; +} +#define drm_add_edid_modes _kcl_drm_add_edid_modes +#endif + +#endif From 34ed65521d24cf23466b33c8f6a225cb895d97b9 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Tue, 7 Jan 2020 11:41:45 +0800 Subject: [PATCH 0214/2653] drm/amdkcl: Test whether drm_dp_atomic_find_vcpi_slots() wants five arguments it is a squash of: commit 60952ca580bfaa25cb57731bd7803bae5ec5293d Author: Stanley.Yang Date: Tue Jan 7 11:41:45 2020 +0800 drm/amdkcl: Test whether drm_dp_atomic_find_vcpi_slots() wants five arguments Signed-off-by: Stanley.Yang commit 6bbc6aadcb87e88d0f7976230b8292674b835785 Author: Slava Grigorev Date: Thu Jan 23 17:08:59 2020 -0500 drm/amdkcl: fix AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS test - a logical error in the test - compiler warning about ingnoring return value Signed-off-by: Slava Grigorev commit 655092d31b7e37020ef98bda5a0401f6a13f603c Author: Flora Cui Date: Mon Nov 16 16:34:47 2020 +0800 drm/amdkcl: move kcl copy for drm_dp_mst_helper into backport part the macros definition should be in backport to warn amdkcl to NOT include it. Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 | 33 ++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../backport/kcl_drm_dp_mst_helper_backport.h | 54 +++++++++++++++++++ 4 files changed, 89 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 create mode 100644 include/kcl/backport/kcl_drm_dp_mst_helper_backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index ffe385190e8ee..8ca380f5f6412 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -37,5 +37,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 new file mode 100644 index 0000000000000..448c9066f274a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 @@ -0,0 +1,33 @@ +dnl # +dnl # commit edb1ed1ab7d314e114de84003f763da34c0f34c0 +dnl # drm/dp: Add DP MST helpers to atomically find and release vcpi slots +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + int retval; + retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0); + ], [drm_dp_atomic_find_vcpi_slots], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS, 1, + [drm_dp_atomic_find_vcpi_slots() is available]) + ], [ + dnl # + dnl # commit dad1c2499a8f6d7ee01db8148f05ebba73cc41bd + dnl # drm/dp_mst: Manually overwrite PBN divider for calculating timeslots + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int retval; + retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS, 1, + [drm_dp_atomic_find_vcpi_slots() wants 5args]) + AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS, 1, + [drm_dp_atomic_find_vcpi_slots() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a7b5ccceb8d07..d1d9788795673 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -56,6 +56,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC + AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h new file mode 100644 index 0000000000000..500c939856d17 --- /dev/null +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -0,0 +1,54 @@ +/* + * Copyright © 2014 Red Hat + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ +#ifndef _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ +#define _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ + +#include + +#if defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS) +#if !defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS) +static inline +int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, + struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, int pbn, + int pbn_div) +{ + int pbn_backup; + int req_slots; + + if (pbn_div > 0) { + pbn_backup = mgr->pbn_div; + mgr->pbn_div = pbn_div; + } + + req_slots = drm_dp_atomic_find_vcpi_slots(state, mgr, port, pbn); + + if (pbn_div > 0) + mgr->pbn_div = pbn_backup; + + return req_slots; +} +#define drm_dp_atomic_find_vcpi_slots _kcl_drm_dp_atomic_find_vcpi_slots +#endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ +#endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS */ + +#endif From 4ad3101cc9a46d8b40eb0401b7dde79a10e23e87 Mon Sep 17 00:00:00 2001 From: tianci yin Date: Fri, 11 Jan 2019 15:39:47 +0800 Subject: [PATCH 0215/2653] drm/amdkcl: Test whether drm_dp_cec_xxx functions are available v1: drm/amdkcl: [4.19] kcl for drm_dp_cec_* functions v2: drm/amdkcl: Test whether drm_dp_cec_xxx functions are available v3: drm/amdkcl: fix kcl_drm_dp_cec_xxx v4: drm/amdkcl: fix drm_dp_cec_xxx check v5: drm_dp_cec_xxx are inlines with CONFIG_DRM_DP_CEC undefined. v6: drm/amdkcl: drop kcl_drm_dp_cec_xxx v7: drm/amdkcl: refactor kcl check for drm_dp_cec_irq v8: drm/amdkcl: split drm_dp_cec related stuff [why] commit "drm: add support for DisplayPort CEC-Tunneling-over-AUX" introduced drm_dp_cec_* functions. commit "drm/amdgpu: add DisplayPort CEC-Tunneling-over-AUX suppor" introduced the reference of drm_dp_cec_* functions. but for kernel < 4.19, drm_dp_cec_* functions are not available. [how] "DisplayPort CEC-Tunneling-over-AUX" is a new feature, for old kernel, we can just skip it, so we just define empty drm_dp_cec* functions like CONFIG_DRM_DP_CEC is not set. Reviewed-by: changzhu Signed-off-by: Tianci Yin Signed-off-by: chen gong Reviewed-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Jack Gui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../m4/drm-dp-cec-correlation-functions.m4 | 31 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../kcl/backport/kcl_drm_dp_helper_backport.h | 21 +++++ include/kcl/kcl_drm_dp_cec.h | 86 +++++++++++++++++++ 5 files changed, 140 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 create mode 100644 include/kcl/backport/kcl_drm_dp_helper_backport.h create mode 100644 include/kcl/kcl_drm_dp_cec.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 8ca380f5f6412..a581beee14b3d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -37,6 +37,7 @@ #include #include #include +#include #include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 new file mode 100644 index 0000000000000..52f51298caf4d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 @@ -0,0 +1,31 @@ +dnl # +dnl # commit v5.3-rc1-555-gae85b0df124f +dnl # drm_dp_cec: add connector info support. +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_cec_register_connector(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP, 1, + [drm_dp_cec_register_connector() wants p,p interface]) + AC_DEFINE(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS, 1, + [drm_dp_cec* correlation functions are available]) + ], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_cec_irq(NULL); + drm_dp_cec_register_connector(NULL, NULL, NULL); + drm_dp_cec_unregister_connector(NULL); + drm_dp_cec_set_edid(NULL, NULL); + drm_dp_cec_unset_edid(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS, 1, + [drm_dp_cec* correlation functions are available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d1d9788795673..74f263a93aeee 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -57,6 +57,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS + AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/backport/kcl_drm_dp_helper_backport.h b/include/kcl/backport/kcl_drm_dp_helper_backport.h new file mode 100644 index 0000000000000..8a932361c9e0e --- /dev/null +++ b/include/kcl/backport/kcl_drm_dp_helper_backport.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_DRM_DP_HELPER_BACKPORT_H_ +#define _KCL_DRM_DP_HELPER_BACKPORT_H_ + +#include +#include + +/* + * commit v4.19-rc1-100-g5ce70c799ac2 + * drm_dp_cec: check that aux has a transfer function + */ +#if defined(AMDKCL_DRM_DP_CEC_XXX_CHECK_CB) +#define drm_dp_cec_irq _kcl_drm_dp_cec_irq +#define drm_dp_cec_set_edid _kcl_drm_dp_cec_set_edid +#define drm_dp_cec_unset_edid _kcl_drm_dp_cec_unset_edid +#endif + +#if !defined(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP) +#define drm_dp_cec_register_connector _kcl_drm_dp_cec_register_connector +#endif +#endif diff --git a/include/kcl/kcl_drm_dp_cec.h b/include/kcl/kcl_drm_dp_cec.h new file mode 100644 index 0000000000000..984b5d320f4fa --- /dev/null +++ b/include/kcl/kcl_drm_dp_cec.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * DisplayPort CEC-Tunneling-over-AUX support + * + * Copyright 2018 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + */ + +#ifndef __KCL_KCL_DRM_DP_CEC_H__ +#define __KCL_KCL_DRM_DP_CEC_H__ + +#include + +/* + * commit v4.19-rc1-100-g5ce70c799ac2 + * drm_dp_cec: check that aux has a transfer function + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 20, 0) +#define AMDKCL_DRM_DP_CEC_XXX_CHECK_CB +#endif + +/* Copied from gpu/drm/drm_dp_cec.c and modified for KCL */ +#if defined(AMDKCL_DRM_DP_CEC_XXX_CHECK_CB) +static inline void _kcl_drm_dp_cec_irq(struct drm_dp_aux *aux) +{ +#if defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) +#ifdef CONFIG_DRM_DP_CEC + /* No transfer function was set, so not a DP connector */ + if (!aux->transfer) + return; +#endif + + drm_dp_cec_irq(aux); +#endif +} + +static inline void _kcl_drm_dp_cec_set_edid(struct drm_dp_aux *aux, + const struct edid *edid) +{ +#if defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) +#ifdef CONFIG_DRM_DP_CEC + /* No transfer function was set, so not a DP connector */ + if (!aux->transfer) + return; +#endif + + drm_dp_cec_set_edid(aux, edid); +#endif +} + +static inline void _kcl_drm_dp_cec_unset_edid(struct drm_dp_aux *aux) +{ +#if defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) +#ifdef CONFIG_DRM_DP_CEC + /* No transfer function was set, so not a DP connector */ + if (!aux->transfer) + return; +#endif + + drm_dp_cec_unset_edid(aux); +#endif +} +#endif + +#if !defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) +static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) +{ +} +#endif + +#if !defined(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP) +static inline void _kcl_drm_dp_cec_register_connector(struct drm_dp_aux *aux, + struct drm_connector *connector) +{ +#if defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) +#ifdef CONFIG_DRM_DP_CEC + if (WARN_ON(!aux->transfer)) + return; +#endif + + drm_dp_cec_register_connector(aux, connector->name, connector->dev->dev); +#endif +} +#endif + + +#endif From 6046d7f94322c339fe9c4d46b03066b3f5d09185 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 6 Dec 2019 15:29:49 +0800 Subject: [PATCH 0216/2653] drm/amdkcl: Test whether drm_dp_mst_topology_mgr_resume is available Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- .../dkms/m4/drm-dp-mst-topology-mgr-resume.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../backport/kcl_drm_dp_mst_helper_backport.h | 10 ++++++++++ 3 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 new file mode 100644 index 0000000000000..3c491e182062e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.4-rc4-759-g6f85f73821f6 +dnl # drm/dp_mst: Add basic topology reprobing when resuming +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int ret; + ret = drm_dp_mst_topology_mgr_resume(NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS, 1, + [drm_dp_mst_topology_mgr_resume() wants 2 args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 74f263a93aeee..e5fcd0612b4b8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -58,6 +58,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 500c939856d17..85fa328d0aa09 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -51,4 +51,14 @@ int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, #endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ #endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS */ +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS +static inline int +_kcl_drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr, + bool sync) +{ + return drm_dp_mst_topology_mgr_resume(mgr); +} +#define drm_dp_mst_topology_mgr_resume _kcl_drm_dp_mst_topology_mgr_resume +#endif + #endif From ec21a915289f661ebba6f70f97775849a9703642 Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Mon, 18 Feb 2019 10:56:56 +0800 Subject: [PATCH 0217/2653] drm/amdkcl: Test whether __devcgroup_check_permission() is available v1: drm/amdkcl: [4.15] Export __devcgroup_check_permission base on DKMS V2: EXport __devcgroup_check_permission by looking up the kallsys. v3: drm/amdkcl: Test whether __devcgroup_check_permission() is available v4: drm/amdkcl: fix devcgroup_check_permission() check v5: update for commit d16020d7429fffd47cfb2f3ab3b6b5b362108a6e : v6: drm/amdkcl: drop kcl_devcgroup_check_permission v7: drm/amdkcl: fix license for kcl part Signed-off-by: Prike Liang Reviewed-by: Junwei Zhang Signed-off-by: Flora Cui Reviewed-by: Jack Gui Reviewed-by: Rui Teng Acked-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- .../gpu/drm/amd/amdkcl/kcl_device_cgroup.c | 35 +++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 +- drivers/gpu/drm/amd/backport/backport.h | 1 + .../amd/dkms/m4/devcgroup-check-permission.m4 | 15 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../kcl/backport/kcl_device_cgroup_backport.h | 10 +++++ include/kcl/kcl_device_cgroup.h | 45 +++++++++++++++++++ 9 files changed, 114 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_device_cgroup.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/devcgroup-check-permission.m4 create mode 100644 include/kcl/backport/kcl_device_cgroup_backport.h create mode 100644 include/kcl/kcl_device_cgroup.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 3de8b0d51ffcb..e0736cc39adb9 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -9,7 +9,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ - kcl_drm_crtc.o kcl_connector.o + kcl_drm_crtc.o kcl_connector.o \ + kcl_device_cgroup.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_device_cgroup.c b/drivers/gpu/drm/amd/amdkcl/kcl_device_cgroup.c new file mode 100644 index 0000000000000..1fb1830aa5039 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_device_cgroup.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * device_cgroup.c - device cgroup subsystem + * + * Copyright 2007 IBM Corp + */ +#include +#include + +#if defined(CONFIG_CGROUP_DEVICE) && \ + !defined(HAVE_DEVCGROUP_CHECK_PERMISSION) +/* + * __devcgroup_check_permission is introduced in v3.6-6796-gad676077a2ae + * as: + * static int __devcgroup_check_permission(struct dev_cgroup *dev_cgroup, + * short type, u32 major, u32 minor, + * short access) + * + * prototype change in v3.7-rc2-147-g8c9506d16925 to: + * static int __devcgroup_check_permission(short type, u32 major, u32 minor, + * short access) + * + * the current amdkcl don't support kernel earilier than v3.7-rc2-147-g8c9506d16925 + */ +int (*__kcl_devcgroup_check_permission)(short type, u32 major, u32 minor, + short access); +EXPORT_SYMBOL(__kcl_devcgroup_check_permission); +#endif +void amdkcl_dev_cgroup_init(void) +{ +#if defined(CONFIG_CGROUP_DEVICE) && \ + !defined(HAVE_DEVCGROUP_CHECK_PERMISSION) + __kcl_devcgroup_check_permission = amdkcl_fp_setup("__devcgroup_check_permission", NULL); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index b99b4ca0f9880..aa767fa0aa014 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -3,6 +3,7 @@ #include extern void amdkcl_symbol_init(void); +extern void amdkcl_dev_cgroup_init(void); extern void amdkcl_fence_init(void); extern void amdkcl_reservation_init(void); extern void amdkcl_io_init(void); @@ -16,6 +17,7 @@ extern void amdkcl_sched_init(void); int __init amdkcl_init(void) { amdkcl_symbol_init(); + amdkcl_dev_cgroup_init(); amdkcl_fence_init(); amdkcl_reservation_init(); amdkcl_io_init(); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 4711a1d1d107c..4590d4ea1d271 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -38,7 +38,9 @@ #include #include #include -#include +#include +/* amdkcl: this header file is included in kcl_device_cgroup.h +#include */ #include #include #include diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a581beee14b3d..6ad8181770628 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/devcgroup-check-permission.m4 b/drivers/gpu/drm/amd/dkms/m4/devcgroup-check-permission.m4 new file mode 100644 index 0000000000000..0341249c5457b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/devcgroup-check-permission.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit v5.3-rc3-2427-g4b7d4d453fc4 +dnl # device_cgroup: Export devcgroup_check_permission +dnl # +AC_DEFUN([AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + devcgroup_check_permission(0, 0, 0, 0); + ], [devcgroup_check_permission], [security/device_cgroup.c], [ + AC_DEFINE(HAVE_DEVCGROUP_CHECK_PERMISSION, 1, [devcgroup_check_permission() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e5fcd0612b4b8..6cfbed4fb46bb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -48,6 +48,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_SG_TT_INIT + AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED diff --git a/include/kcl/backport/kcl_device_cgroup_backport.h b/include/kcl/backport/kcl_device_cgroup_backport.h new file mode 100644 index 0000000000000..9bac47907e956 --- /dev/null +++ b/include/kcl/backport/kcl_device_cgroup_backport.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_DEVICE_CGROUP_BACKPORT_H +#define AMDKCL_DEVICE_CGROUP_BACKPORT_H + +#include + +#ifndef HAVE_DEVCGROUP_CHECK_PERMISSION +#define devcgroup_check_permission _kcl_devcgroup_check_permission +#endif /* HAVE_DEVCGROUP_CHECK_PERMISSION */ +#endif diff --git a/include/kcl/kcl_device_cgroup.h b/include/kcl/kcl_device_cgroup.h new file mode 100644 index 0000000000000..3eba9b4697856 --- /dev/null +++ b/include/kcl/kcl_device_cgroup.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_DEVICE_CGROUP_H +#define AMDKCL_DEVICE_CGROUP_H + +#include + +/* Copied from include/linux/device_cgroup.h */ +#ifndef DEVCG_DEV_CHAR +#define DEVCG_DEV_CHAR 2 +#endif +#ifndef DEVCG_ACC_READ +#define DEVCG_ACC_READ 2 +#endif +#ifndef DEVCG_ACC_WRITE +#define DEVCG_ACC_WRITE 4 +#endif + +/* Copied from security/device_cgroup.c and modified for KCL */ +#ifndef HAVE_DEVCGROUP_CHECK_PERMISSION +#if defined(CONFIG_CGROUP_DEVICE) +extern int (*__kcl_devcgroup_check_permission)(short type, u32 major, u32 minor, + short access); + +static inline int _kcl_devcgroup_check_permission(short type, u32 major, u32 minor, + short access) +{ +#ifdef BPF_CGROUP_RUN_PROG_DEVICE_CGROUP + int rc = BPF_CGROUP_RUN_PROG_DEVICE_CGROUP(type, major, minor, access); + + if (rc) + return -EPERM; +#endif + + return __kcl_devcgroup_check_permission(type, major, minor, access); +} +#else +static inline int _kcl_devcgroup_check_permission(short type, u32 major, u32 minor, + short access) +{ + return 0; +} +#endif /* CONFIG_CGROUP_DEVICE */ +#endif /* HAVE_DEVCGROUP_CHECK_PERMISSION */ + +#endif /* AMDKCL_DEVICE_CGROUP_H */ From d1b0d2b34fae678d4118e210341503c6d42f1379 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Mon, 18 Feb 2019 10:45:06 +0800 Subject: [PATCH 0218/2653] drm/amdkcl: Test whether mmu_notifier_call_srcu() is available It's a squash of 1d849edd9801 drm/amdkcl: Test whether mmu_notifier_call_srcu() is available fd62e7af6cd9 drm/amdkcl: refactor mmu_notifier_unregister_no_release() c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Jack Gui Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Signed-off-by: Slava Grigorev Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_mn.c | 43 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/mmu-notifier-call-srcu.m4 | 18 ++++++++ include/kcl/kcl_mn.h | 16 +++++++ 6 files changed, 80 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_mn.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/mmu-notifier-call-srcu.m4 create mode 100644 include/kcl/kcl_mn.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index e0736cc39adb9..dd2587a0a67ee 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -10,7 +10,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_connector.o \ - kcl_device_cgroup.o + kcl_device_cgroup.o kcl_mn.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mn.c b/drivers/gpu/drm/amd/amdkcl/kcl_mn.c new file mode 100644 index 0000000000000..20a0c2c5a9280 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mn.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include +#include + +/* Copied from v3.16-6588-gb972216e27d1 mm/mmu_notifier.c */ +#if !defined(HAVE_MMU_NOTIFIER_CALL_SRCU) && \ + !defined(HAVE_MMU_NOTIFIER_PUT) +/* + * Modifications [2017-03-14] (c) [2017] + */ + +/* + * This function allows mmu_notifier::release callback to delay a call to + * a function that will free appropriate resources. The function must be + * quick and must not block. + */ +void mmu_notifier_call_srcu(struct rcu_head *rcu, + void (*func)(struct rcu_head *rcu)) +{ + /* changed from call_srcu to call_rcu */ + call_rcu(rcu, func); +} +EXPORT_SYMBOL_GPL(mmu_notifier_call_srcu); + +void mmu_notifier_unregister_no_release(struct mmu_notifier *mn, + struct mm_struct *mm) +{ + spin_lock(&mm->mmu_notifier_mm->lock); + /* + * Can not use list_del_rcu() since __mmu_notifier_release + * can delete it before we hold the lock. + */ + hlist_del_init_rcu(&mn->hlist); + spin_unlock(&mm->mmu_notifier_mm->lock); + + BUG_ON(atomic_read(&mm->mm_count) <= 0); + mmdrop(mm); +} +EXPORT_SYMBOL_GPL(mmu_notifier_unregister_no_release); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6ad8181770628..499bef7ff56a2 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6cfbed4fb46bb..d02e92e074b9c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -43,6 +43,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMF_INSERT_MIXED_PROT AC_AMDGPU_VMF_INSERT_PFN_PROT AC_AMDGPU_MMU_NOTIFIER + AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_SCHED_SET_FIFO_LOW AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-call-srcu.m4 b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-call-srcu.m4 new file mode 100644 index 0000000000000..8b1aad73065f7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-call-srcu.m4 @@ -0,0 +1,18 @@ +dnl # commit b972216e27d1c853eced33f8638926636c606341 +dnl # mmu_notifier: add call_srcu and sync function +dnl # for listener to delay call and sync +dnl # +dnl # commit v5.3-rc5-63-gc96245148c1e +dnl # mm/mmu_notifiers: remove unregister_no_release +dnl # +AC_DEFUN([AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + mmu_notifier_call_srcu(NULL, NULL); + ],[ + AC_DEFINE(HAVE_MMU_NOTIFIER_CALL_SRCU, 1, [mmu_notifier_call_srcu() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mn.h b/include/kcl/kcl_mn.h new file mode 100644 index 0000000000000..02e80c3b4e386 --- /dev/null +++ b/include/kcl/kcl_mn.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_MN_H +#define AMDKCL_MN_H + +#include + +/* Copied from v3.16-6588-gb972216e27d1 include/linux/mmu_notifier.h */ +#if !defined(HAVE_MMU_NOTIFIER_CALL_SRCU) && \ + !defined(HAVE_MMU_NOTIFIER_PUT) +extern void mmu_notifier_call_srcu(struct rcu_head *rcu, + void (*func)(struct rcu_head *rcu)); +extern void mmu_notifier_unregister_no_release(struct mmu_notifier *mn, + struct mm_struct *mm); +#endif + +#endif /* AMDKCL_MN_H */ From c4a7bff5dfed6986ad486b932214531518498398 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 1 Jun 2020 12:48:26 +0800 Subject: [PATCH 0219/2653] drm/amdkcl: fake drm_atomic_helper_plane_reset to commit v4.19-rc1-206-ge267364a6e1b. v2: 69a65a9c531c drm/amdkcl: fix license for kcl drm part Signed-off-by: Flora Cui Acked-by: Rodrigo Siqueira Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../drm/amd/amdkcl/kcl_drm_atomic_helper.c | 48 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../backport/kcl_drm_atomic_helper_backport.h | 11 +++++ include/kcl/kcl_drm_atomic_helper.h | 47 ++++++++++++++++++ 5 files changed, 108 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c create mode 100644 include/kcl/backport/kcl_drm_atomic_helper_backport.h create mode 100644 include/kcl/kcl_drm_atomic_helper.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index dd2587a0a67ee..065f205b662a8 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -9,7 +9,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ - kcl_drm_crtc.o kcl_connector.o \ + kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c new file mode 100644 index 0000000000000..c6c37ceca85c8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2014 Red Hat + * Copyright (C) 2014 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + * Daniel Vetter + */ +#include +#include + +#ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET +void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, + struct drm_plane_state *state) +{ + state->plane = plane; + state->rotation = DRM_MODE_ROTATE_0; + +#ifdef DRM_BLEND_ALPHA_OPAQUE + state->alpha = DRM_BLEND_ALPHA_OPAQUE; +#endif +#ifdef DRM_MODE_BLEND_PREMULTI + state->pixel_blend_mode = DRM_MODE_BLEND_PREMULTI; +#endif + + plane->state = state; +} +EXPORT_SYMBOL(_kcl__drm_atomic_helper_plane_reset); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 499bef7ff56a2..68d11a14a5029 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -41,5 +41,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/backport/kcl_drm_atomic_helper_backport.h b/include/kcl/backport/kcl_drm_atomic_helper_backport.h new file mode 100644 index 0000000000000..bcb45b685a034 --- /dev/null +++ b/include/kcl/backport/kcl_drm_atomic_helper_backport.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_DRM_ATOMIC_HELPER_BACKPORT_H +#define AMDKCL_DRM_ATOMIC_HELPER_BACKPORT_H + +#include + +#ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET +#define __drm_atomic_helper_plane_reset _kcl__drm_atomic_helper_plane_reset +#endif /* AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET */ + +#endif diff --git a/include/kcl/kcl_drm_atomic_helper.h b/include/kcl/kcl_drm_atomic_helper.h new file mode 100644 index 0000000000000..661b8cd643ff2 --- /dev/null +++ b/include/kcl/kcl_drm_atomic_helper.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2014 Red Hat + * Copyright (C) 2014 Intel Corp. + * Copyright (C) 2018 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + * Daniel Vetter + */ +#ifndef AMDKCL_DRM_ATOMIC_HELPER_H +#define AMDKCL_DRM_ATOMIC_HELPER_H + +#include +#include +#include +#include +#include + +/* + * v4.19-rc1-206-ge267364a6e1b + * drm/atomic: Initialise planes with opaque alpha values + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 20, 0) +#define AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET +void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, + struct drm_plane_state *state); +#endif + +#endif From 0aee700a2525ea810e78e483322e0ef63cda2e32 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 22 Sep 2020 11:02:03 +0800 Subject: [PATCH 0220/2653] drm/amdkcl: test __drm_atomic_helper_crtc_reset() is available Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c | 13 +++++++++++++ .../amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 | 14 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_atomic_helper.h | 5 +++++ 4 files changed, 33 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c index c6c37ceca85c8..c11911f2dcbc8 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -46,3 +46,16 @@ void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, } EXPORT_SYMBOL(_kcl__drm_atomic_helper_plane_reset); #endif + +#ifndef HAVE___DRM_ATOMIC_HELPER_CRTC_RESET +void +__drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state) +{ + if (crtc_state) + crtc_state->crtc = crtc; + + crtc->state = crtc_state; +} +EXPORT_SYMBOL(__drm_atomic_helper_crtc_reset); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 b/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 new file mode 100644 index 0000000000000..637a0bc453cd7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 @@ -0,0 +1,14 @@ +dnl # +dnl # v5.1-rc2-1163-g7d26097b4beb +dnl # drm/atomic: Create __drm_atomic_helper_crtc_reset() for subclassing crtc_state. +dnl # +AC_DEFUN([AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([__drm_atomic_helper_crtc_reset], + [drivers/gpu/drm/drm_atomic_state_helper.c], + [ + AC_DEFINE(HAVE___DRM_ATOMIC_HELPER_CRTC_RESET, 1, + [__drm_atomic_helper_crtc_reset() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d02e92e074b9c..5be2f1a8cbabb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -61,6 +61,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME + AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_drm_atomic_helper.h b/include/kcl/kcl_drm_atomic_helper.h index 661b8cd643ff2..cb5c49c24cb94 100644 --- a/include/kcl/kcl_drm_atomic_helper.h +++ b/include/kcl/kcl_drm_atomic_helper.h @@ -44,4 +44,9 @@ void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, struct drm_plane_state *state); #endif +#ifndef HAVE___DRM_ATOMIC_HELPER_CRTC_RESET +void __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state); +#endif + #endif From e7ed8520aeec77d38218ac07cd1377e136ef2c8e Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Fri, 31 Jul 2020 17:56:07 -0400 Subject: [PATCH 0221/2653] drm/amdkcl: Enable HDCP Build by default Add HDCP config flag to the makefile It's a squash of drm/amdkcl: test whether drm_hdcp_update_content_protection is available drm/amdkcl: add kcl/kcl_drm_hdcp.h drm/amdkcl: test drm_hdcp.h for enabling hdcp Signed-off-by: Yang Xiong Reviewed-by: Flora Cui Acked-by: Bhawanpreet Lakha drm/amdkcl: fix missing CONFIG_DRM_AMD_DC_HDCP check Signed-off-by: Rui Teng Reviewed-by: Jack Gui drm/amdkcl: move hdcp related stuff to kcl_drm_hdcp.c and fix license Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Signed-off-by: Bhawanpreet Lakha Signed-off-by: Yang Xiong Reviewed-by: Flora Cui Change-Id: Iecbc2d3cefce447cbb2a1cc10703fea226a469e5 --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 + drivers/gpu/drm/amd/amdkcl/kcl_drm_hdcp.c | 25 ++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 + drivers/gpu/drm/amd/dkms/Makefile | 4 + .../m4/drm-hdcp-update-content-protection.m4 | 16 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_hdcp.h | 316 ++++++++++++++++++ 8 files changed, 368 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_hdcp.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 create mode 100644 include/kcl/kcl_drm_hdcp.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 065f205b662a8..b49fb6e31328d 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,6 +12,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o +amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o + CFLAGS_kcl_fence.o := -I$(src) ccflags-y += \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_hdcp.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_hdcp.c new file mode 100644 index 0000000000000..21686ff9a5950 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_hdcp.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation. + * + * Authors: + * Ramalingam C + */ +#include + +#ifndef HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION +/* Copied from v5.3-rc1-380-gbb5a45d40d50 drivers/gpu/drm/drm_hdcp.c */ +void _kcl_drm_hdcp_update_content_protection(struct drm_connector *connector, + u64 val) +{ + struct drm_device *dev = connector->dev; + struct drm_connector_state *state = connector->state; + + WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); + if (state->content_protection == val) + return; + + state->content_protection = val; +} +EXPORT_SYMBOL(_kcl_drm_hdcp_update_content_protection); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 68d11a14a5029..0af51f73cf470 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -42,5 +42,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c71167ffdb76b..769d7406481af 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -94,6 +94,9 @@ #include #include #include +#ifdef CONFIG_DRM_AMD_DC_HDCP +#include +#endif #include #include diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index dbace6b3bc0ae..25f48546e8d01 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -156,6 +156,10 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 +ifeq ($(shell grep "HAVE_DRM_DRM_HDCP_H" $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n"),y) +export CONFIG_DRM_AMD_DC_HDCP=y +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP +endif # Trying to enable DCN2/3 with core2 optimizations will result in # older versions of GCC hanging during building/installing. Check diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 new file mode 100644 index 0000000000000..5b8c871002830 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.3-rc1-380-gbb5a45d40d50 +dnl # drm/hdcp: update content protection property with uevent +dnl # +AC_DEFUN([AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_hdcp_update_content_protection(NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION, 1, + [drm_hdcp_update_content_protection is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5be2f1a8cbabb..ab625eda42a47 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -62,6 +62,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET + AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_drm_hdcp.h b/include/kcl/kcl_drm_hdcp.h new file mode 100644 index 0000000000000..ba77fb5c0973a --- /dev/null +++ b/include/kcl/kcl_drm_hdcp.h @@ -0,0 +1,316 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2017 Google, Inc. + * + * Authors: + * Sean Paul + */ +#ifndef AMDKCL_DRM_HDCP_H +#define AMDKCL_DRM_HDCP_H + +#ifdef CONFIG_DRM_AMD_DC_HDCP +#include +#include + +/* changed in v4.16-rc7-1717-gb8e47d87be65 + * drm: Fix HDCP downstream dev count read + */ +#ifdef DRM_HDCP_NUM_DOWNSTREAM +#undef DRM_HDCP_NUM_DOWNSTREAM +#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f) +#endif + +/* introduced in v5.3-rc1-377-g7672dbba85d3 + * drm: Add Content protection type property + */ +#ifndef DRM_MODE_HDCP_CONTENT_TYPE0 +#define DRM_MODE_HDCP_CONTENT_TYPE0 0 +#define DRM_MODE_HDCP_CONTENT_TYPE1 1 +#endif + +/* introduced in v4.19-rc2-1221-gaf5aad059885 + * drm: hdcp2.2 authentication msg definitions + */ +#ifndef DRM_HDCP_1_4_SRM_ID +#define DRM_HDCP_1_4_SRM_ID 0x8 +#define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3 +#define DRM_HDCP_1_4_DCP_SIG_SIZE 40 + +/* Protocol message definition for HDCP2.2 specification */ +/* + * Protected content streams are classified into 2 types: + * - Type0: Can be transmitted with HDCP 1.4+ + * - Type1: Can be transmitted with HDCP 2.2+ + */ +#define HDCP_STREAM_TYPE0 0x00 +#define HDCP_STREAM_TYPE1 0x01 + +/* HDCP2.2 Msg IDs */ +#define HDCP_2_2_NULL_MSG 1 +#define HDCP_2_2_AKE_INIT 2 +#define HDCP_2_2_AKE_SEND_CERT 3 +#define HDCP_2_2_AKE_NO_STORED_KM 4 +#define HDCP_2_2_AKE_STORED_KM 5 +#define HDCP_2_2_AKE_SEND_HPRIME 7 +#define HDCP_2_2_AKE_SEND_PAIRING_INFO 8 +#define HDCP_2_2_LC_INIT 9 +#define HDCP_2_2_LC_SEND_LPRIME 10 +#define HDCP_2_2_SKE_SEND_EKS 11 +#define HDCP_2_2_REP_SEND_RECVID_LIST 12 +#define HDCP_2_2_REP_SEND_ACK 15 +#define HDCP_2_2_REP_STREAM_MANAGE 16 +#define HDCP_2_2_REP_STREAM_READY 17 +#define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 + +#define HDCP_2_2_RTX_LEN 8 +#define HDCP_2_2_RRX_LEN 8 + +#define HDCP_2_2_K_PUB_RX_MOD_N_LEN 128 +#define HDCP_2_2_K_PUB_RX_EXP_E_LEN 3 +#define HDCP_2_2_K_PUB_RX_LEN (HDCP_2_2_K_PUB_RX_MOD_N_LEN + \ + HDCP_2_2_K_PUB_RX_EXP_E_LEN) + +#define HDCP_2_2_DCP_LLC_SIG_LEN 384 + +#define HDCP_2_2_E_KPUB_KM_LEN 128 +#define HDCP_2_2_E_KH_KM_M_LEN (16 + 16) +#define HDCP_2_2_H_PRIME_LEN 32 +#define HDCP_2_2_E_KH_KM_LEN 16 +#define HDCP_2_2_RN_LEN 8 +#define HDCP_2_2_L_PRIME_LEN 32 +#define HDCP_2_2_E_DKEY_KS_LEN 16 +#define HDCP_2_2_RIV_LEN 8 +#define HDCP_2_2_SEQ_NUM_LEN 3 +#define HDCP_2_2_V_PRIME_HALF_LEN (HDCP_2_2_L_PRIME_LEN / 2) +#define HDCP_2_2_RECEIVER_ID_LEN DRM_HDCP_KSV_LEN +#define HDCP_2_2_MAX_DEVICE_COUNT 31 +#define HDCP_2_2_RECEIVER_IDS_MAX_LEN (HDCP_2_2_RECEIVER_ID_LEN * \ + HDCP_2_2_MAX_DEVICE_COUNT) +#define HDCP_2_2_MPRIME_LEN 32 + +/* Following Macros take a byte at a time for bit(s) masking */ +/* + * TODO: This has to be changed for DP MST, as multiple stream on + * same port is possible. + * For HDCP2.2 on HDMI and DP SST this value is always 1. + */ +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1 +#define HDCP_2_2_TXCAP_MASK_LEN 2 +#define HDCP_2_2_RXCAPS_LEN 3 +#define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0)) +#define HDCP_2_2_DP_HDCP_CAPABLE(x) ((x) & BIT(1)) +#define HDCP_2_2_RXINFO_LEN 2 + +/* HDCP1.x compliant device in downstream */ +#define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x) ((x) & BIT(0)) + +/* HDCP2.0 Compliant repeater in downstream */ +#define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x) ((x) & BIT(1)) +#define HDCP_2_2_MAX_CASCADE_EXCEEDED(x) ((x) & BIT(2)) +#define HDCP_2_2_MAX_DEVS_EXCEEDED(x) ((x) & BIT(3)) +#define HDCP_2_2_DEV_COUNT_LO(x) (((x) & (0xF << 4)) >> 4) +#define HDCP_2_2_DEV_COUNT_HI(x) ((x) & BIT(0)) +#define HDCP_2_2_DEPTH(x) (((x) & (0x7 << 1)) >> 1) + +struct hdcp2_cert_rx { + u8 receiver_id[HDCP_2_2_RECEIVER_ID_LEN]; + u8 kpub_rx[HDCP_2_2_K_PUB_RX_LEN]; + u8 reserved[2]; + u8 dcp_signature[HDCP_2_2_DCP_LLC_SIG_LEN]; +} __packed; + +struct hdcp2_streamid_type { + u8 stream_id; + u8 stream_type; +} __packed; + +/* + * The TxCaps field specified in the HDCP HDMI, DP specs + * This field is big endian as specified in the errata. + */ +struct hdcp2_tx_caps { + /* Transmitter must set this to 0x2 */ + u8 version; + + /* Reserved for HDCP and DP Spec. Read as Zero */ + u8 tx_cap_mask[HDCP_2_2_TXCAP_MASK_LEN]; +} __packed; + +/* Main structures for HDCP2.2 protocol communication */ +struct hdcp2_ake_init { + u8 msg_id; + u8 r_tx[HDCP_2_2_RTX_LEN]; + struct hdcp2_tx_caps tx_caps; +} __packed; + +struct hdcp2_ake_send_cert { + u8 msg_id; + struct hdcp2_cert_rx cert_rx; + u8 r_rx[HDCP_2_2_RRX_LEN]; + u8 rx_caps[HDCP_2_2_RXCAPS_LEN]; +} __packed; + +struct hdcp2_ake_no_stored_km { + u8 msg_id; + u8 e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN]; +} __packed; + +struct hdcp2_ake_stored_km { + u8 msg_id; + u8 e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN]; +} __packed; + +struct hdcp2_ake_send_hprime { + u8 msg_id; + u8 h_prime[HDCP_2_2_H_PRIME_LEN]; +} __packed; + +struct hdcp2_ake_send_pairing_info { + u8 msg_id; + u8 e_kh_km[HDCP_2_2_E_KH_KM_LEN]; +} __packed; + +struct hdcp2_lc_init { + u8 msg_id; + u8 r_n[HDCP_2_2_RN_LEN]; +} __packed; + +struct hdcp2_lc_send_lprime { + u8 msg_id; + u8 l_prime[HDCP_2_2_L_PRIME_LEN]; +} __packed; + +struct hdcp2_ske_send_eks { + u8 msg_id; + u8 e_dkey_ks[HDCP_2_2_E_DKEY_KS_LEN]; + u8 riv[HDCP_2_2_RIV_LEN]; +} __packed; + +struct hdcp2_rep_send_receiverid_list { + u8 msg_id; + u8 rx_info[HDCP_2_2_RXINFO_LEN]; + u8 seq_num_v[HDCP_2_2_SEQ_NUM_LEN]; + u8 v_prime[HDCP_2_2_V_PRIME_HALF_LEN]; + u8 receiver_ids[HDCP_2_2_RECEIVER_IDS_MAX_LEN]; +} __packed; + +struct hdcp2_rep_send_ack { + u8 msg_id; + u8 v[HDCP_2_2_V_PRIME_HALF_LEN]; +} __packed; + +struct hdcp2_rep_stream_manage { + u8 msg_id; + u8 seq_num_m[HDCP_2_2_SEQ_NUM_LEN]; + __be16 k; + struct hdcp2_streamid_type streams[HDCP_2_2_MAX_CONTENT_STREAMS_CNT]; +} __packed; + +struct hdcp2_rep_stream_ready { + u8 msg_id; + u8 m_prime[HDCP_2_2_MPRIME_LEN]; +} __packed; + +struct hdcp2_dp_errata_stream_type { + u8 msg_id; + u8 stream_type; +} __packed; +#endif /* DRM_HDCP_1_4_SRM_ID */ + +/* introduced in v4.19-rc2-1222-g8b44fefee694 + * drm: HDMI and DP specific HDCP2.2 defines + */ +#ifndef HDCP_2_2_CERT_TIMEOUT_MS +/* HDCP2.2 TIMEOUTs in mSec */ +#define HDCP_2_2_CERT_TIMEOUT_MS 100 +#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS 1000 +#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS 200 +#define HDCP_2_2_PAIRING_TIMEOUT_MS 200 +#define HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS 20 +#define HDCP_2_2_DP_LPRIME_TIMEOUT_MS 7 +#define HDCP_2_2_RECVID_LIST_TIMEOUT_MS 3000 +#define HDCP_2_2_STREAM_READY_TIMEOUT_MS 100 + +/* HDMI HDCP2.2 Register Offsets */ +#define HDCP_2_2_HDMI_REG_VER_OFFSET 0x50 +#define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET 0x60 +#define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET 0x70 +#define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET 0x80 +#define HDCP_2_2_HDMI_REG_DBG_OFFSET 0xC0 + +#define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2) +#define HDCP_2_2_RX_CAPS_VERSION_VAL 0x02 +#define HDCP_2_2_SEQ_NUM_MAX 0xFFFFFF +#define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200 + +/* Below macros take a byte at a time and mask the bit(s) */ +#define HDCP_2_2_HDMI_RXSTATUS_LEN 2 +#define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3) +#define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2)) +#define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) +/* DP HDCP2.2 parameter offsets in DPCD address space */ +#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000 +#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008 +#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B +#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215 +#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D +#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220 +#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0 +#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0 +#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0 +#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0 +#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0 +#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8 +#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318 +#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328 +#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330 +#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332 +#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335 +#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345 +#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0 +#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0 +#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3 +#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5 +#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473 +#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493 +#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494 +#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518 + +/* DP HDCP message start offsets in DPCD address space */ +#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET +#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET +#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET +#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET +#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET +#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \ + DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET +#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET +#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET +#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET +#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET +#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET +#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET +#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET + +#define HDCP_2_2_DP_RXSTATUS_LEN 1 +#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0)) +#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1)) +#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2)) +#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) +#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4)) +#endif /* HDCP_2_2_CERT_TIMEOUT_MS */ + +#ifndef HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION +void _kcl_drm_hdcp_update_content_protection(struct drm_connector *connector, + u64 val); +static inline +void drm_hdcp_update_content_protection(struct drm_connector *connector, + u64 val) +{ + _kcl_drm_hdcp_update_content_protection(connector, val); +} +#endif /* HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION */ + +#endif /* CONFIG_DRM_AMD_DC_HDCP */ + +#endif /* AMDKCL_DRM_HDCP_H */ From 11e804cadf8084e5ffc6b4cb14f5622732dc16c1 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 21 Sep 2020 19:13:19 +0800 Subject: [PATCH 0222/2653] drm/amdkcl: test mem_encrypt_active() is available fake a kcl copy if not available. mem_encrypt_active() is introduced in v4.14-rc8-89-gd8aa7eea78a1 This patch is introduced by v5.9-rc2-389-gc2bc2643976e 'drm/amdgpu/dc: Fail to load on RAVEN if SME is active' v2: c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Shiwu Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Change-Id: Ia5e4eab8c3362d76ca6a40e635271f3f4f4644e9 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 | 16 ++++++++++++ include/kcl/kcl_dma_mapping.h | 1 + include/kcl/kcl_mem_encrypt.h | 26 +++++++++++++++++++ 4 files changed, 44 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 create mode 100644 include/kcl/kcl_mem_encrypt.h diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ab625eda42a47..f8049c2cee34e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -63,6 +63,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION + AC_AMDGPU_MEM_ENCRYPT_ACTIVE AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 b/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 new file mode 100644 index 0000000000000..ad484a873022a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v4.14-rc8-89-gd8aa7eea78a1 +dnl # x86/mm: Add Secure Encrypted Virtualization (SEV) support +dnl # +AC_DEFUN([AC_AMDGPU_MEM_ENCRYPT_ACTIVE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + mem_encrypt_active(); + ], [ + AC_DEFINE(HAVE_MEM_ENCRYPT_ACTIVE, 1, + [mem_encrypt_active() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h index c7de48cd9aad7..1b7609d8ee876 100644 --- a/include/kcl/kcl_dma_mapping.h +++ b/include/kcl/kcl_dma_mapping.h @@ -3,6 +3,7 @@ #define AMDKCL_DMA_MAPPING_H #include +#include /* * commit v4.8-11962-ga9a62c938441 diff --git a/include/kcl/kcl_mem_encrypt.h b/include/kcl/kcl_mem_encrypt.h new file mode 100644 index 0000000000000..60d24e198587e --- /dev/null +++ b/include/kcl/kcl_mem_encrypt.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AMD Memory Encryption Support + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Author: Tom Lendacky + */ +#ifndef KCL_KCL_MEM_ENCRYPT_H +#define KCL_KCL_MEM_ENCRYPT_H + +#ifdef HAVE_LINUX_MEM_ENCRYPT_H +#include +#ifndef HAVE_MEM_ENCRYPT_ACTIVE +static inline bool mem_encrypt_active(void) +{ + return sme_me_mask; +} +#endif +#else +static inline bool mem_encrypt_active(void) +{ + return false; +} +#endif +#endif From cde36fbcc4bf0f4d09333f95655c494bfa1d5ecc Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 13 Oct 2020 08:54:27 +0800 Subject: [PATCH 0223/2653] drm/amdkcl: test jiffies64_to_msecs() fake a kcl copy for legacy kernel support. v2: c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Guchun Chen Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_time.c | 40 +++++++++++++++++++ .../gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 | 11 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_timekeeping.h | 4 ++ 5 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_time.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index b49fb6e31328d..8089fe0c6b4f8 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -10,7 +10,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ - kcl_device_cgroup.o kcl_mn.o + kcl_device_cgroup.o kcl_mn.o kcl_time.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_time.c b/drivers/gpu/drm/amd/amdkcl/kcl_time.c new file mode 100644 index 0000000000000..a6394747da818 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_time.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 1991, 1992 Linus Torvalds + * + * This file contains the interface functions for the various time related + * system calls: time, stime, gettimeofday, settimeofday, adjtime + * + * Modification history: + * + * 1993-09-02 Philip Gladstone + * Created file with time related functions from sched/core.c and adjtimex() + * 1993-10-08 Torsten Duwe + * adjtime interface update and CMOS clock write code + * 1995-08-13 Torsten Duwe + * kernel PLL updated to 1994-12-13 specs (rfc-1589) + * 1999-01-16 Ulrich Windl + * Introduced error checking for many cases in adjtimex(). + * Updated NTP code according to technical memorandum Jan '96 + * "A Kernel Model for Precision Timekeeping" by Dave Mills + * Allow time_constant larger than MAXTC(6) for NTP v4 (MAXTC == 10) + * (Even though the technical memorandum forbids it) + * 2004-07-14 Christoph Lameter + * Added getnstimeofday to allow the posix timer functions to return + * with nanosecond accuracy + */ +#include +#include + +#ifndef HAVE_JIFFIES64_TO_MSECS +/* Copied from kernel/time/time.c */ +u64 jiffies64_to_msecs(const u64 j) +{ +#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) + return (MSEC_PER_SEC / HZ) * j; +#else + return div_u64(j * HZ_TO_MSEC_NUM, HZ_TO_MSEC_DEN); +#endif +} +EXPORT_SYMBOL(jiffies64_to_msecs); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 b/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 new file mode 100644 index 0000000000000..e44504998e830 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 @@ -0,0 +1,11 @@ +dnl # +dnl # v5.1-rc3-699-g3b15d09f7e6d +dnl # time: Introduce jiffies64_to_msecs() +dnl # +AC_DEFUN([AC_AMDGPU_JIFFIES64_TO_MSECS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([jiffies64_to_msecs], [kernel/time/time.c], [ + AC_DEFINE(HAVE_JIFFIES64_TO_MSECS, 1, [jiffies64_to_msecs() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f8049c2cee34e..5533f622938b9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -64,6 +64,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_MEM_ENCRYPT_ACTIVE + AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_timekeeping.h b/include/kcl/kcl_timekeeping.h index 7c5bd5b28cb65..60b8c7fec82e5 100644 --- a/include/kcl/kcl_timekeeping.h +++ b/include/kcl/kcl_timekeeping.h @@ -54,4 +54,8 @@ static inline u64 ktime_get_mono_fast_ns(void) } #endif +#ifndef HAVE_JIFFIES64_TO_MSECS +extern u64 jiffies64_to_msecs(u64 j); +#endif + #endif From ae96768adbfdf4576c89c4357d1111e097484153 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Sun, 11 Oct 2020 20:22:47 +0800 Subject: [PATCH 0224/2653] drm/amdkcl: fake the __print_array macro for trace This is caused by "add new trace event for page table update" v5.9-rc2-514-g0fe7e2764d6f v2: calculate buf_len by count and el_size v3: use HAVE___PRINT_ARRAY instead of HAVE_FTRACE_PRINT_ARRAY_SEQ v4: fix license for kcl part Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c | 56 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../drm/amd/dkms/m4/ftrace_print_array_seq.m4 | 23 ++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_ftrace.h | 17 ++++++ 6 files changed, 99 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/ftrace_print_array_seq.m4 create mode 100644 include/kcl/kcl_ftrace.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 8089fe0c6b4f8..684f04edda134 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -10,7 +10,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ - kcl_device_cgroup.o kcl_mn.o kcl_time.o + kcl_device_cgroup.o kcl_mn.o kcl_time.o kcl_ftrace.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c b/drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c new file mode 100644 index 0000000000000..115bdc26363a5 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * trace_output.c + * + * Copyright (C) 2008 Red Hat Inc, Steven Rostedt + * + */ +#include + +/* Copied from v3.19-rc1-6-g6ea22486ba46 kernel/trace/trace_output.c */ +#if !defined(HAVE___PRINT_ARRAY) +const char * +ftrace_print_array_seq(struct trace_seq *p, const void *buf, int count, + size_t el_size) +{ + const char *ret = trace_seq_buffer_ptr(p); + const char *prefix = ""; + void *ptr = (void *)buf; + size_t buf_len = count * el_size; + + trace_seq_putc(p, '{'); + + while (ptr < buf + buf_len) { + switch (el_size) { + case 1: + trace_seq_printf(p, "%s0x%x", prefix, + *(u8 *)ptr); + break; + case 2: + trace_seq_printf(p, "%s0x%x", prefix, + *(u16 *)ptr); + break; + case 4: + trace_seq_printf(p, "%s0x%x", prefix, + *(u32 *)ptr); + break; + case 8: + trace_seq_printf(p, "%s0x%llx", prefix, + *(u64 *)ptr); + break; + default: + trace_seq_printf(p, "BAD SIZE:%zu 0x%x", el_size, + *(u8 *)ptr); + el_size = 1; + } + prefix = ","; + ptr += el_size; + } + + trace_seq_putc(p, '}'); + trace_seq_putc(p, 0); + + return ret; +} +EXPORT_SYMBOL(ftrace_print_array_seq); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 0af51f73cf470..441239afe128f 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -43,5 +43,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/ftrace_print_array_seq.m4 b/drivers/gpu/drm/amd/dkms/m4/ftrace_print_array_seq.m4 new file mode 100644 index 0000000000000..ecc2aa76f18b1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ftrace_print_array_seq.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # commit 0fe7e2764d6f +dnl # add new trace event for page table update +dnl # ftrace_print_array_seq() is exported in v3.19-rc1-6-g6ea22486ba46 +dnl # +AC_DEFUN([AC_AMDGPU___PRINT_ARRAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([ftrace_print_array_seq], [kernel/trace/trace_output.c], [ + AC_DEFINE(HAVE___PRINT_ARRAY, 1, [__print_array is available]) + ], [ + dnl # + dnl # 645df987f7c + dnl # trace_print_array_seq() is exported in v4.1-rc3-8-g645df987f7c1 + dnl # + AC_KERNEL_CHECK_SYMBOL_EXPORT( + [trace_print_array_seq], + [kernel/trace/trace_output.c],[ + AC_DEFINE(HAVE___PRINT_ARRAY, 1, + [__print_array is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5533f622938b9..9aa4b26097cae 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -65,6 +65,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_MEM_ENCRYPT_ACTIVE AC_AMDGPU_JIFFIES64_TO_MSECS + AC_AMDGPU___PRINT_ARRAY AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_ftrace.h b/include/kcl/kcl_ftrace.h new file mode 100644 index 0000000000000..de98a0a5f345e --- /dev/null +++ b/include/kcl/kcl_ftrace.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_FTRACE_H +#define AMDKCL_FTRACE_H + +/* Copied from v3.19-rc1-6-g6ea22486ba46 include/trace/ftrace.h */ +#if !defined(HAVE___PRINT_ARRAY) +extern const char * ftrace_print_array_seq(struct trace_seq *p, const void *buf, int count, + size_t el_size); +#define __print_array(array, count, el_size) \ + ({ \ + BUILD_BUG_ON(el_size != 1 && el_size != 2 && \ + el_size != 4 && el_size != 8); \ + ftrace_print_array_seq(p, array, count, el_size); \ + }) +#endif + +#endif From 92834dce86eb730b048c7b92afd53de94dcaa528 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Fri, 20 Nov 2020 14:53:01 +0800 Subject: [PATCH 0225/2653] drm/amdkcl: fake the acpi_put_table() This is caused by "Put ACPI table after using it" v5.9-rc5-1537-gc435d35df6c5 v2: c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Shiwu Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 ++- drivers/gpu/drm/amd/amdkcl/kcl_acpi_table.c | 15 +++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_acpi_table.h | 18 ++++++++++++++++++ 6 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_acpi_table.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 create mode 100644 include/kcl/kcl_acpi_table.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 684f04edda134..fafb36606e287 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -10,7 +10,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ - kcl_device_cgroup.o kcl_mn.o kcl_time.o kcl_ftrace.o + kcl_device_cgroup.o kcl_mn.o kcl_time.o kcl_ftrace.o \ + kcl_acpi_table.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_acpi_table.c b/drivers/gpu/drm/amd/amdkcl/kcl_acpi_table.c new file mode 100644 index 0000000000000..554bebabd4adb --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_acpi_table.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 +/****************************************************************************** + * + * Module Name: tbxface - ACPI table-oriented external interfaces + * + * Copyright (C) 2000 - 2020, Intel Corp. + * + *****************************************************************************/ +#include +#include + +#ifndef HAVE_ACPI_PUT_TABLE +amdkcl_dummy_symbol(acpi_put_table, void, return, + struct acpi_table_header *table) +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 441239afe128f..a38fc43d61a54 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -44,5 +44,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 new file mode 100644 index 0000000000000..27001acd98f95 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit: v4.9-rc5-17-g174cc7187e6f +dnl # ACPICA: Tables: Back port acpi_get_table_with_size() and +dnl # early_acpi_os_unmap_memory() from Linux kernel +AC_DEFUN([AC_AMDGPU_ACPI_PUT_TABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([acpi_put_table], + [drivers/acpi/acpica/tbxface.c], [ + AC_DEFINE(HAVE_ACPI_PUT_TABLE, 1, + [acpi_put_table() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9aa4b26097cae..ad80f9a980bfa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -66,6 +66,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MEM_ENCRYPT_ACTIVE AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU___PRINT_ARRAY + AC_AMDGPU_ACPI_PUT_TABLE AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_acpi_table.h b/include/kcl/kcl_acpi_table.h new file mode 100644 index 0000000000000..849e8a58a2dbd --- /dev/null +++ b/include/kcl/kcl_acpi_table.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ +/****************************************************************************** + * + * Name: acpixf.h - External interfaces to the ACPI subsystem + * + * Copyright (C) 2000 - 2020, Intel Corp. + * + *****************************************************************************/ +#ifndef KCL_KCL_ACPI_TABLE_H +#define KCL_KCL_ACPI_TABLE_H + +#include + +#ifndef HAVE_ACPI_PUT_TABLE +void acpi_put_table(struct acpi_table_header *table); +#endif + +#endif From 1d1b86f629530c85691ce47c2647568500cf3f2d Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 8 Dec 2020 15:24:22 +0800 Subject: [PATCH 0226/2653] drm/amdkcl: fake drm_dbg_kms This is caused by "use drm_dbg_kms to log addfb2 failures" v5.9-rc5-1859-g16dba6910508 v2: copy the drm_dev_dbg implementation v3: add the autotest for drm_dev_dbg for sle sp2 support v4: drm/amdkcl: split drm_print stuff to kcl_drm_print.[ch] Signed-off-by: Shiwu Zhang Signed-off-by: Flora Cui Reviewed-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 26 ++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 | 11 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_print.h | 9 ++++++++ 4 files changed, 47 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 3b5945b8bee0a..3d690609edb8f 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -51,3 +51,29 @@ void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf) } EXPORT_SYMBOL(__drm_printfn_debug); #endif + +#if !defined(HAVE_DRM_DEV_DBG) +void drm_dev_dbg(const struct device *dev, int category, + const char *format, ...) +{ + struct va_format vaf; + va_list args; + + if (!drm_debug_enabled(category)) + return; + + va_start(args, format); + vaf.fmt = format; + vaf.va = &args; + + if (dev) + dev_printk(KERN_DEBUG, dev, "[" DRM_NAME ":%ps] %pV", + __builtin_return_address(0), &vaf); + else + printk(KERN_DEBUG "[" DRM_NAME ":%ps] %pV", + __builtin_return_address(0), &vaf); + + va_end(args); +} +EXPORT_SYMBOL(drm_dev_dbg); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 new file mode 100644 index 0000000000000..dfcc85e60e4bf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 @@ -0,0 +1,11 @@ +dnl # +dnl # v4.16-rc1-493-gdb8708649258 +dnl # drm: Reduce object size of DRM_DEV_ uses +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEV_DBG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_dev_dbg], [drivers/gpu/drm/drm_print.c], [ + AC_DEFINE(HAVE_DRM_DEV_DBG, 1, [drm_dev_dbg() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ad80f9a980bfa..911b9dce312b6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -67,6 +67,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU___PRINT_ARRAY AC_AMDGPU_ACPI_PUT_TABLE + AC_AMDGPU_DRM_DEV_DBG AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 65db884854a3d..3ead0ab2b367f 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -113,6 +113,15 @@ static inline struct drm_printer drm_debug_printer(const char *prefix) } while (0) #endif +#if !defined(HAVE_DRM_DEV_DBG) +void drm_dev_dbg(const struct device *dev, int category, const char *format, ...); +#endif + +#if !defined(drm_dbg_kms) +#define drm_dbg_kms(drm, fmt, ...) \ + drm_dev_dbg((drm)->dev, 0x04, fmt, ##__VA_ARGS__) +#endif + #ifndef HAVE_DRM_DEBUG_ENABLED /* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ static inline bool drm_debug_enabled(unsigned int category) From d6c07b9bc5be3cb82c5c2aebdd77426275ad0f58 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Thu, 17 Dec 2020 16:33:45 +0800 Subject: [PATCH 0227/2653] drm/amdkcl: fake pci_pr3_present This is caused by "add check for ACPI power resources" v5.9-rc5-1932-gad02c8dc25c1 v2: dummy the function if CONFIG_ACPI is not defined Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 21 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/pci_pr3_present.m4 | 11 ++++++++++ include/kcl/kcl_pci.h | 13 ++++++++++++ 4 files changed, 46 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index bf095e454ed06..171f3239eeb3a 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -19,6 +19,7 @@ #include #include +#include #if !defined(HAVE_PCIE_BANDWIDTH_AVAILABLE) const unsigned char *_kcl_pcie_link_speed; @@ -297,3 +298,23 @@ void _kcl_pci_configure_extended_tags(struct pci_dev *dev) } EXPORT_SYMBOL(_kcl_pci_configure_extended_tags); #endif + +#ifndef HAVE_PCI_PR3_PRESENT +#ifdef CONFIG_ACPI +bool _kcl_pci_pr3_present(struct pci_dev *pdev) +{ + struct acpi_device *adev; + + if (acpi_disabled) + return false; + + adev = ACPI_COMPANION(&pdev->dev); + if (!adev) + return false; + + return adev->power.flags.power_resources && + acpi_has_method(adev->handle, "_PR3"); +} +EXPORT_SYMBOL_GPL(_kcl_pci_pr3_present); +#endif +#endif /* HAVE_PCI_PR3_PRESENT */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 911b9dce312b6..87b74110b702f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -68,6 +68,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___PRINT_ARRAY AC_AMDGPU_ACPI_PUT_TABLE AC_AMDGPU_DRM_DEV_DBG + AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 b/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 new file mode 100644 index 0000000000000..38e50b2c0766f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 @@ -0,0 +1,11 @@ +dnl # +dnl # v5.4-rc2-37-g52525b7a3cf8 +dnl # PCI: Add a helper to check Power Resource Requirements _PR3 existence +dnl # +AC_DEFUN([AC_AMDGPU_PCI_PR3_PRESENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([pci_pr3_present], [drivers/pci/pci.c], [ + AC_DEFINE(HAVE_PCI_PR3_PRESENT, 1, [pci_pr3_present() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 68246cdd08768..4eefafc20be1a 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -99,4 +99,17 @@ static inline u16 pci_dev_id(struct pci_dev *dev) return PCI_DEVID(dev->bus->number, dev->devfn); } #endif /* HAVE_PCI_DEV_ID */ + +#ifndef HAVE_PCI_PR3_PRESENT +#ifdef CONFIG_ACPI +bool _kcl_pci_pr3_present(struct pci_dev *pdev); +static inline bool pci_pr3_present(struct pci_dev *pdev) +{ + return _kcl_pci_pr3_present(pdev); +} +#else +static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } +#endif +#endif /* HAVE_PCI_PR3_PRESENT */ + #endif /* AMDKCL_PCI_H */ From 3e2e652baa61d6c721e85b5a07b88ea3373f943e Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Wed, 18 Sep 2019 21:55:54 +0800 Subject: [PATCH 0228/2653] drm/amdkcl: Test whether drm_helper_force_disable_all() is defined v2: drm/amdkcl: fix drm_helper_force_disable_all Signed-off-by: Adam Yang Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- .../gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 | 20 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_crtc.h | 8 ++++++++ 3 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 new file mode 100644 index 0000000000000..a0e32e7654867 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit f453ba0460742ad027ae0c4c7d61e62817b3e7ef +dnl # DRM: add mode setting support +dnl # +dnl # commit c2d88e06bcb98540bb83fac874574eaa4f320363 +dnl # drm: Move the legacy kms disable_all helper to crtc helpers +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_helper_force_disable_all(NULL); + ], [ + AC_DEFINE(HAVE_DRM_HELPER_FORCE_DISABLE_ALL, 1, + [drm_helper_force_disable_all() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 87b74110b702f..a219e700c82a9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -75,6 +75,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_CRTC_FORCE_DISABLE_ALL + AC_AMDGPU_DRM_CRTC_HELPER AC_AMDGPU_DRM_EDID_TO_ELD AC_KERNEL_WAIT diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h index 38861d70bd9bb..daca652324951 100644 --- a/include/kcl/kcl_drm_crtc.h +++ b/include/kcl/kcl_drm_crtc.h @@ -79,4 +79,12 @@ extern int drm_crtc_force_disable(struct drm_crtc *crtc); extern int drm_crtc_force_disable_all(struct drm_device *dev); #endif +#if !defined(HAVE_DRM_HELPER_FORCE_DISABLE_ALL) +static inline +int drm_helper_force_disable_all(struct drm_device *dev) +{ + return drm_crtc_force_disable_all(dev); +} +#endif + #endif From 88d7677a5c4a21c9959b6d2c37b7315ed704afca Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 17 Dec 2020 16:30:35 +0800 Subject: [PATCH 0229/2653] drm/amdkcl: rework faked drm_helper_force_disable_all Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c | 57 ++++++------------- ...per.m4 => drm_helper_force_disable_all.m4} | 10 +--- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- include/kcl/kcl_drm_crtc.h | 8 +-- 4 files changed, 23 insertions(+), 55 deletions(-) rename drivers/gpu/drm/amd/dkms/m4/{drm-crtc-helper.m4 => drm_helper_force_disable_all.m4} (60%) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c index 0dab372fcb93f..c4e079c49d8ab 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c @@ -31,49 +31,26 @@ */ #include -#if !defined(HAVE_DRM_CRTC_FORCE_DISABLE_ALL) -/** - * drm_crtc_force_disable - Forcibly turn off a CRTC - * @crtc: CRTC to turn off - * - * Returns: - * Zero on success, error code on failure. - */ -int drm_crtc_force_disable(struct drm_crtc *crtc) +#ifndef HAVE_DRM_HELPER_FORCE_DISABLE_ALL +int _kcl_drm_helper_force_disable_all(struct drm_device *dev) { - struct drm_mode_set set = { - .crtc = crtc, - }; - - return drm_mode_set_config_internal(&set); -} -EXPORT_SYMBOL(drm_crtc_force_disable); + struct drm_crtc *crtc; + int ret = 0; -/** - * drm_crtc_force_disable_all - Forcibly turn off all enabled CRTCs - * @dev: DRM device whose CRTCs to turn off - * - * Drivers may want to call this on unload to ensure that all displays are - * unlit and the GPU is in a consistent, low power state. Takes modeset locks. - * - * Returns: - * Zero on success, error code on failure. - */ -int drm_crtc_force_disable_all(struct drm_device *dev) -{ - struct drm_crtc *crtc; - int ret = 0; + drm_modeset_lock_all(dev); + drm_for_each_crtc(crtc, dev) + if (crtc->enabled) { + struct drm_mode_set set = { + .crtc = crtc, + }; - drm_modeset_lock_all(dev); - drm_for_each_crtc(crtc, dev) - if (crtc->enabled) { - ret = drm_crtc_force_disable(crtc); - if (ret) - goto out; - } + ret = drm_mode_set_config_internal(&set); + if (ret) + goto out; + } out: - drm_modeset_unlock_all(dev); - return ret; + drm_modeset_unlock_all(dev); + return ret; } -EXPORT_SYMBOL(drm_crtc_force_disable_all); +EXPORT_SYMBOL(_kcl_drm_helper_force_disable_all); #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 similarity index 60% rename from drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 rename to drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 index a0e32e7654867..f52b3c10ccd43 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 @@ -2,16 +2,12 @@ dnl # dnl # commit f453ba0460742ad027ae0c4c7d61e62817b3e7ef dnl # DRM: add mode setting support dnl # -dnl # commit c2d88e06bcb98540bb83fac874574eaa4f320363 +dnl # commit v5.0-rc1-118-gc2d88e06bcb9 dnl # drm: Move the legacy kms disable_all helper to crtc helpers dnl # -AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER], [ +AC_DEFUN([AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - drm_helper_force_disable_all(NULL); - ], [ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_helper_force_disable_all], [drivers/gpu/drm/drm_crtc_helper.c],[ AC_DEFINE(HAVE_DRM_HELPER_FORCE_DISABLE_ALL, 1, [drm_helper_force_disable_all() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a219e700c82a9..576f4fe44295a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -74,8 +74,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT - AC_AMDGPU_DRM_CRTC_FORCE_DISABLE_ALL - AC_AMDGPU_DRM_CRTC_HELPER + AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD AC_KERNEL_WAIT diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h index daca652324951..e0eaa2ace66b1 100644 --- a/include/kcl/kcl_drm_crtc.h +++ b/include/kcl/kcl_drm_crtc.h @@ -74,16 +74,12 @@ DRM_MODE_ROTATE_270) #endif -#if !defined(HAVE_DRM_CRTC_FORCE_DISABLE_ALL) -extern int drm_crtc_force_disable(struct drm_crtc *crtc); -extern int drm_crtc_force_disable_all(struct drm_device *dev); -#endif - #if !defined(HAVE_DRM_HELPER_FORCE_DISABLE_ALL) +int _kcl_drm_helper_force_disable_all(struct drm_device *dev); static inline int drm_helper_force_disable_all(struct drm_device *dev) { - return drm_crtc_force_disable_all(dev); + return _kcl_drm_helper_force_disable_all(dev); } #endif From ddf61dd20b6beb3b0c03296f1c7b62fc0f4f1a95 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Thu, 24 Dec 2020 11:43:48 +0800 Subject: [PATCH 0230/2653] drm/amdkcl: fix kthread_use_mm/kthread_unuse_mm redefinition error on sle sp2 server distro with kernel 5.3.18-24 define the kthread_use_mm for kcl only when it is neither defined in kthread.c nor in mmu_context.h Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 | 20 +++++++++++++++---- include/kcl/kcl_kthread.h | 2 -- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 b/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 index 0b62fc9008c6b..6177b3b6fa49e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 @@ -3,9 +3,21 @@ dnl # f5678e7f2ac3 kernel: better document the use_mm/unuse_mm API contract dnl # 9bf5b9eb232b kernel: move use_mm/unuse_mm to kthread.c dnl # AC_DEFUN([AC_AMDGPU_KTHREAD_USE_MM], [ - AC_KERNEL_CHECK_SYMBOL_EXPORT([kthread_use_mm kthread_unuse_mm], - [kernel/kthread.c], [ - AC_DEFINE(HAVE_KTHREAD_USE_MM, 1, - [kthread_{use,unuse}_mm() is available]) + AC_KERNEL_DO_BACKGROUND([ + dnl # + dnl # sle sp2 server distro inlines kthread_use_mm/kthread_unuse_mm + dnl # in mmu_context.h + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + #include + ], [ + kthread_use_mm(NULL); + kthread_unuse_mm(NULL); + ], [ + AC_DEFINE(HAVE_KTHREAD_USE_MM, 1, + [kthread_{use,unuse}_mm() is available]) + ]) ]) ]) diff --git a/include/kcl/kcl_kthread.h b/include/kcl/kcl_kthread.h index ecb650acee90e..90893fd2590b1 100644 --- a/include/kcl/kcl_kthread.h +++ b/include/kcl/kcl_kthread.h @@ -4,9 +4,7 @@ #include #include -#ifndef HAVE_KTHREAD_USE_MM #include -#endif #if !defined(HAVE___KTHREAD_SHOULD_PATK) extern bool __kcl_kthread_should_park(struct task_struct *k); From 90536d0d6311d1821deddf17b0decb3d82af30e8 Mon Sep 17 00:00:00 2001 From: "Le.Ma" Date: Wed, 20 Sep 2017 09:53:26 +0800 Subject: [PATCH 0231/2653] drm/amdkcl: check whether rcu_pointer_handoff is available Change-Id: Ie20100a6353d106bd3cad3e724f0157de6e6b902 Signed-off-by: Le.Ma Reviewed-by: Junwei Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui --- include/kcl/kcl_rcupdate.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 include/kcl/kcl_rcupdate.h diff --git a/include/kcl/kcl_rcupdate.h b/include/kcl/kcl_rcupdate.h new file mode 100644 index 0000000000000..ec31bae327ead --- /dev/null +++ b/include/kcl/kcl_rcupdate.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_RCUPDATE_H +#define AMDKCL_RCUPDATE_H + +#include +#include + +#ifndef rcu_pointer_handoff +#define rcu_pointer_handoff(p) (p) +#endif + +#endif /* AMDKCL_RCUPDATE_H */ From 45720497ccfe7b3f390f8e00364494626e85514e Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 13 May 2020 17:21:35 -0400 Subject: [PATCH 0232/2653] drm/amdkcl: optional devices ID for amdgpu driver Test for amdgpu-pciid.h header file Signed-off-by: Slava Grigorev Reviewed-by: Slava Abramov Reviewed-by: Tim Writer --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index f128f8f2f2507..216d7f7de743f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2198,6 +2198,10 @@ static const struct pci_device_id pciidlist[] = { .class_mask = 0xffffff, .driver_data = CHIP_IP_DISCOVERY }, +#ifdef HAVE_DRM_AMDGPU_PCIID_H +#include +#endif + {0, 0, 0} }; From 5d826eac525927c97cb14385ceee842c304d6e6d Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Fri, 21 Aug 2020 12:44:47 +0800 Subject: [PATCH 0233/2653] drm/amdkcl: add kcl copy of drm/task_barrier.h This is a squash of: drm/amdkcl: rework drm/task_barrier.h handling Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_task_barrier.h | 86 +++++++++++++++++++++++++ 2 files changed, 87 insertions(+) create mode 100644 include/kcl/kcl_task_barrier.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a38fc43d61a54..a0a11812f299c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_task_barrier.h b/include/kcl/kcl_task_barrier.h new file mode 100644 index 0000000000000..341fe8e02a9d9 --- /dev/null +++ b/include/kcl/kcl_task_barrier.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_DRM_TASK_BARRIER_H +#define AMDKCL_DRM_TASK_BARRIER_H + +#ifdef HAVE_DRM_TASK_BARRIER_H +#include +#else +/* + * Reusable 2 PHASE task barrier (randevouz point) implementation for N tasks. + * Based on the Little book of sempahores - https://greenteapress.com/wp/semaphores/ + */ +#include +#include + +/* + * Represents an instance of a task barrier. + */ +struct task_barrier { + unsigned int n; + atomic_t count; + struct semaphore enter_turnstile; + struct semaphore exit_turnstile; +}; + +static inline void task_barrier_signal_turnstile(struct semaphore *turnstile, + unsigned int n) +{ + int i; + + for (i = 0 ; i < n; i++) + up(turnstile); +} + +static inline void task_barrier_init(struct task_barrier *tb) +{ + tb->n = 0; + atomic_set(&tb->count, 0); + sema_init(&tb->enter_turnstile, 0); + sema_init(&tb->exit_turnstile, 0); +} + +static inline void task_barrier_add_task(struct task_barrier *tb) +{ + tb->n++; +} + +static inline void task_barrier_rem_task(struct task_barrier *tb) +{ + tb->n--; +} + +/* + * Lines up all the threads BEFORE the critical point. + * + * When all thread passed this code the entry barrier is back to locked state. + */ +static inline void task_barrier_enter(struct task_barrier *tb) +{ + if (atomic_inc_return(&tb->count) == tb->n) + task_barrier_signal_turnstile(&tb->enter_turnstile, tb->n); + + down(&tb->enter_turnstile); +} + +/* + * Lines up all the threads AFTER the critical point. + * + * This function is used to avoid any one thread running ahead if the barrier is + * used repeatedly . + */ +static inline void task_barrier_exit(struct task_barrier *tb) +{ + if (atomic_dec_return(&tb->count) == 0) + task_barrier_signal_turnstile(&tb->exit_turnstile, tb->n); + + down(&tb->exit_turnstile); +} + +/* Convinieince function when nothing to be done in between entry and exit */ +static inline void task_barrier_full(struct task_barrier *tb) +{ + task_barrier_enter(tb); + task_barrier_exit(tb); +} +#endif +#endif From 8f363d129dd7c292e8571a3f502449a72f137bdb Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 7 Nov 2019 10:37:13 +0800 Subject: [PATCH 0234/2653] drm/amdkcl: increase drm vma offset size limit v2: increase drm vma offset size limit For 8 processes share 256GB system memory application case, 1T Bytes drm vma offset limit is not big enough. Increase the limit to 16TB, for max 44bits address space because the upper bit is encoded with gpu_id. Remove the 64GB size condition check to handle all kernels, 64GB is Ubuntu kernel default setting, CentOS, Redhat kernel default is 1TB. Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Jiansong Chen Signed-off-by: Philip Yang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 + drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + .../backport/kcl_drm_vma_manager_backport.h | 58 +++++++++++++++++++ 4 files changed, 62 insertions(+) create mode 100644 include/kcl/backport/kcl_drm_vma_manager_backport.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 216d7f7de743f..2eda9667f9d19 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2404,6 +2404,8 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, adev->pdev = pdev; ddev = adev_to_drm(adev); + kcl_drm_vma_offset_manager_init(ddev->vma_offset_manager); + if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a0a11812f299c..02f790b540220 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -38,6 +38,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 659a7f1e254c4..acec38aa8d159 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #endif diff --git a/include/kcl/backport/kcl_drm_vma_manager_backport.h b/include/kcl/backport/kcl_drm_vma_manager_backport.h new file mode 100644 index 0000000000000..0a7e1bf34bd82 --- /dev/null +++ b/include/kcl/backport/kcl_drm_vma_manager_backport.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2013 David Herrmann + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef AMDKCL_DRM_VMA_MANAGER_H +#define AMDKCL_DRM_VMA_MANAGER_H + +/* We make up offsets for buffer objects so we can recognize them at + * mmap time. pgoff in mmap is an unsigned long, so we need to make sure + * that the faked up offset will fit + */ +#include +#include + +#if (BITS_PER_LONG == 64) +#ifdef DRM_FILE_PAGE_OFFSET_START +#undef DRM_FILE_PAGE_OFFSET_START +#endif +#ifdef DRM_FILE_PAGE_OFFSET_SIZE +#undef DRM_FILE_PAGE_OFFSET_SIZE +#endif + +#define DRM_FILE_PAGE_OFFSET_START ((0xFFFFFFFFULL >> PAGE_SHIFT) + 1) +#define DRM_FILE_PAGE_OFFSET_SIZE ((0xFFFFFFFFULL >> PAGE_SHIFT) * 4096) + +static inline void +kcl_drm_vma_offset_manager_init(struct drm_vma_offset_manager *mgr) +{ + drm_vma_offset_manager_destroy(mgr); + drm_vma_offset_manager_init(mgr, + DRM_FILE_PAGE_OFFSET_START, + DRM_FILE_PAGE_OFFSET_SIZE); +} +#else +static inline void +kcl_drm_vma_offset_manager_init(struct drm_vma_offset_manager *mgr) +{ +} +#endif + +#endif From f2a34794679b05a4d972e6446c8b4d95e120401f Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Fri, 30 Aug 2019 15:30:41 +0800 Subject: [PATCH 0235/2653] drm/amdkcl: check whether DRM_FB_HELPER_DEFAULT_OPS is available DRM_FB_HELPER_DEFAULT_OPS introduced by kernel v4.9-rc1~41^2~3^2~2 - commit 74064893901ac5103cf101ecef5946e82b6ce9c6 - drm/fb-helper: add DRM_FB_HELPER_DEFAULT_OPS for fb_ops v1: drm/amdkcl: Test whether fb_ops->fb_debug_{enter/leave}() is available v2: drm/amdkcl: add DRM_FB_HELPER_DEFAULT_OPS v3: drm/amdkcl: accommodate to drmP.h removal for fb-ops-fb-debug-xx.m4 v4: drm/amd/autoconf: fix a drm kcl compiling error in CentOS 7.3 v5: drm/amdkcl: drop test for fb_ops->fb_debug_xx Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Flora Cui Acked-by: Feifei Xu / Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Feifei Xu --- include/kcl/kcl_drm_fb.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 0954d658644a8..3a0d30273cf7a 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -35,6 +35,25 @@ #include #include +/* + * Don't add fb_debug_* since the legacy drm_fb_helper_debug_* has segfault + * history: + * v2.6.35-21-gd219adc1228a fb: add hooks to handle KDB enter/exit + * v2.6.35-22-g1a7aba7f4e45 drm: add KGDB/KDB support + * v4.8-rc8-1391-g74064893901a drm/fb-helper: add DRM_FB_HELPER_DEFAULT_OPS for fb_ops + * v4.9-rc4-808-g1e0089288b9b drm/fb-helper: add fb_debug_* to DRM_FB_HELPER_DEFAULT_OPS + * v4.9-rc4-807-g1b99b72489c6 drm/fb-helper: fix segfaults in drm_fb_helper_debug_* + * v4.10-rc8-1367-g0f3bbe074dd1 drm/fb-helper: implement ioctl FBIO_WAITFORVSYNC + */ +#ifndef DRM_FB_HELPER_DEFAULT_OPS +#define DRM_FB_HELPER_DEFAULT_OPS \ + .fb_check_var = drm_fb_helper_check_var, \ + .fb_set_par = drm_fb_helper_set_par, \ + .fb_setcmap = drm_fb_helper_setcmap, \ + .fb_blank = drm_fb_helper_blank, \ + .fb_pan_display = drm_fb_helper_pan_display +#endif + #if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) #if !defined(IS_REACHABLE) /* Copied from include/linux/kconfig.h */ From 217708092ba166a15a47c3afb144fa2c4e033d18 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 26 Aug 2020 16:57:05 +0800 Subject: [PATCH 0236/2653] drm/amdkcl: fake kcl copy of drm_atomic_helper_resume Signed-off-by: Flora Cui --- .../backport/kcl_drm_atomic_helper_backport.h | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/include/kcl/backport/kcl_drm_atomic_helper_backport.h b/include/kcl/backport/kcl_drm_atomic_helper_backport.h index bcb45b685a034..1edfc203e12ce 100644 --- a/include/kcl/backport/kcl_drm_atomic_helper_backport.h +++ b/include/kcl/backport/kcl_drm_atomic_helper_backport.h @@ -4,6 +4,33 @@ #include +/* + * commit v4.14-rc4-1-g78279127253a + * drm/atomic: Unref duplicated drm_atomic_state in drm_atomic_helper_resume() + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 15, 0) +static inline +int _kcl_drm_atomic_helper_resume(struct drm_device *dev, + struct drm_atomic_state *state) +{ + unsigned int prev, after; + int ret; + + prev = kref_read(&state->ref); + + drm_atomic_state_get(state); + ret = drm_atomic_helper_resume(dev, state); + + after = kref_read(&state->ref); + drm_atomic_state_put(state); + if (prev != after) + drm_atomic_state_put(state); + + return ret; +} +#define drm_atomic_helper_resume _kcl_drm_atomic_helper_resume +#endif + #ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET #define __drm_atomic_helper_plane_reset _kcl__drm_atomic_helper_plane_reset #endif /* AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET */ From 7a79c54a0ca4a71e59539deb624d06900d0c1e9a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 7 Sep 2020 14:04:55 +0800 Subject: [PATCH 0237/2653] drm/amdkcl: test dma_buf_ops->allow_peer2peer introduced in commit v5.6-rc5-1663-g09606b5446c2 ("dma-buf: add peer2peer flag") Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 6 ++++++ drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 25 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index ff98c87b2e0b9..d298f9cef0de1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -82,9 +82,11 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); +#ifdef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER if (!amdgpu_dmabuf_is_xgmi_accessible(attach_adev, bo) && pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0) attach->peer2peer = false; +#endif amdgpu_vm_bo_update_shared(bo); @@ -174,11 +176,13 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, struct ttm_operation_ctx ctx = { false, false }; unsigned int domains = AMDGPU_GEM_DOMAIN_GTT; +#ifdef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM && attach->peer2peer) { bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; domains |= AMDGPU_GEM_DOMAIN_VRAM; } +#endif amdgpu_bo_placement_from_domain(bo, domains); r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (r) @@ -447,7 +451,9 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) } static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = { +#ifdef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER .allow_peer2peer = true, +#endif .move_notify = amdgpu_dma_buf_move_notify }; diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 new file mode 100644 index 0000000000000..f499b15204fa8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v5.6-rc5-1663-g09606b5446c2 +dnl # dma-buf: add peer2peer flag +dnl # +AC_DEFUN([AC_AMDGPU_DMA_BUF], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct dma_buf_ops *ptr = NULL; + ptr->allow_peer2peer = false; + ],[ + AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER, + 1, + [struct dma_buf_ops->allow_peer2peer is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 576f4fe44295a..62ecc02eb26be 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -50,6 +50,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_SG_TT_INIT AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION + AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED From 8628cc7657e59cd1cfc2e6d4f7a5f957a5f7e275 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Apr 2020 17:10:16 +0800 Subject: [PATCH 0238/2653] drm/amdkcl: for dma_buf_ops->pin/unpin Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 26 +++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 ++++ drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 20 ++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index d298f9cef0de1..45325beb2f818 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -93,6 +93,7 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, return 0; } +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN /** * amdgpu_dma_buf_pin - &dma_buf_ops.pin implementation * @@ -147,6 +148,7 @@ static void amdgpu_dma_buf_unpin(struct dma_buf_attachment *attach) amdgpu_bo_unpin(bo); } +#endif /** * amdgpu_dma_buf_map - &dma_buf_ops.map_dma_buf implementation @@ -171,6 +173,7 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, struct sg_table *sgt; long r; +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN if (!bo->tbo.pin_count) { /* move buffer into GTT or VRAM */ struct ttm_operation_ctx ctx = { false, false }; @@ -188,6 +191,11 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, if (r) return ERR_PTR(r); } +#else + r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); + if (r) + return ERR_PTR(r); +#endif switch (bo->tbo.resource->mem_type) { case TTM_PL_TT: @@ -239,6 +247,12 @@ static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach, struct sg_table *sgt, enum dma_data_direction dir) { +#ifndef HAVE_STRUCT_DMA_BUF_OPS_PIN + struct dma_buf *dma_buf = attach->dmabuf; + struct drm_gem_object *obj = dma_buf->priv; + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); +#endif + if (sg_page(sgt->sgl)) { dma_unmap_sgtable(attach->dev, sgt, dir, 0); sg_free_table(sgt); @@ -246,6 +260,10 @@ static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach, } else { amdgpu_vram_mgr_free_sgt(attach->dev, dir, sgt); } + +#ifndef HAVE_STRUCT_DMA_BUF_OPS_PIN + amdgpu_bo_unpin(bo); +#endif } /** @@ -291,8 +309,10 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf, const struct dma_buf_ops amdgpu_dmabuf_ops = { .attach = amdgpu_dma_buf_attach, +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN .pin = amdgpu_dma_buf_pin, .unpin = amdgpu_dma_buf_unpin, +#endif .map_dma_buf = amdgpu_dma_buf_map, .unmap_dma_buf = amdgpu_dma_buf_unmap, .release = drm_gem_dmabuf_release, @@ -380,6 +400,7 @@ amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf) return ERR_PTR(ret); } +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN /** * amdgpu_dma_buf_move_notify - &attach.move_notify implementation * @@ -456,6 +477,7 @@ static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = { #endif .move_notify = amdgpu_dma_buf_move_notify }; +#endif /** * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation @@ -489,8 +511,12 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, if (IS_ERR(obj)) return obj; +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN attach = dma_buf_dynamic_attach(dma_buf, dev->dev, &amdgpu_dma_buf_attach_ops, obj); +#else + attach = dma_buf_dynamic_attach(dma_buf, dev->dev, true); +#endif if (IS_ERR(attach)) { drm_gem_object_put(obj); return ERR_CAST(attach); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 122a882948839..2f9dc29dd5f0a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -964,8 +964,10 @@ int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) */ domain = amdgpu_bo_get_preferred_domain(adev, domain); +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN if (drm_gem_is_imported(&bo->tbo.base)) dma_buf_pin(bo->tbo.base.import_attach); +#endif /* force to pin into visible video ram */ if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) @@ -1260,9 +1262,11 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, amdgpu_bo_kunmap(abo); +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN if (abo->tbo.base.dma_buf && !drm_gem_is_imported(&abo->tbo.base) && old_mem && old_mem->mem_type != TTM_PL_SYSTEM) dma_buf_move_notify(abo->tbo.base.dma_buf); +#endif /* move_notify is called before move happens */ trace_amdgpu_bo_move(abo, new_mem ? new_mem->mem_type : -1, diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 index f499b15204fa8..dc74e703be9bd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -13,6 +13,26 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER, 1, [struct dma_buf_ops->allow_peer2peer is available]) + ],[ + dnl # + dnl # 4981cdb063e3 dma-buf: make move_notify mandatory if importer_ops are provided + dnl # bd2275eeed5b dma-buf: drop dynamic_mapping flag + dnl # a448cb003edc drm/amdgpu: implement amdgpu_gem_prime_move_notify v2 + dnl # 2d4dad2734e2 drm/amdgpu: add amdgpu_dma_buf_pin/unpin v2 + dnl # 4993ba02635f drm/amdgpu: use allowed_domains for exported DMA-bufs + dnl # d2588d2ded0f drm/ttm: remove the backing store if no placement is given + dnl # bb42df4662a4 dma-buf: add dynamic DMA-buf handling v15 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct dma_buf_ops *ptr = NULL; + ptr->pin(NULL); + ],[ + AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_PIN, + 1, + [struct dma_buf_ops->pin() is available]) + ]) ]) ]) ]) From 611d0f9506f737219552976830241f08187ddd7e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 4 Dec 2019 21:12:38 +0800 Subject: [PATCH 0239/2653] drm/amdkcl: Test whether drm_gem_object->resv is available It's a squash of b56463fa65e9 amd/amdkcl: drop BUILD_AS_DKMS compilation flag 65727463b0e9 drm/ttm,scheduler,amdgpu: properly define and initialize Makefile variables 5e00d69a73fb drm/amdkcl: introduce parallel autoconf tests execution de56d017a2d3 drm/amdkcl: Test whether drm_gem_object->resv is available Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Jiansong Chen Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Change-Id: Ibbd3ff2eb018141c783a2c6c0ebebac366f8ecc0 --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 21 +++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 18 +++---- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 16 +++--- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 | 23 ++++++++ drivers/gpu/drm/ttm/ttm_bo.c | 52 +++++++++---------- drivers/gpu/drm/ttm/ttm_bo_util.c | 16 +++--- drivers/gpu/drm/ttm/ttm_bo_vm.c | 16 +++--- drivers/gpu/drm/ttm/ttm_execbuf_util.c | 12 ++--- drivers/gpu/drm/ttm/ttm_tt.c | 2 +- include/drm/ttm/ttm_bo.h | 28 +++++++--- 19 files changed, 146 insertions(+), 87 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 37d8a7034a7ee..5a1f2e1df5c9a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -364,7 +364,7 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo, * table update and TLB flush here directly. */ replacement = dma_fence_get_stub(); - dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context, + dma_resv_replace_fences(amdkcl_ttm_resvp(&bo->tbo), ef->base.context, replacement, DMA_RESV_USAGE_BOOKKEEP); dma_fence_put(replacement); return 0; @@ -1337,7 +1337,7 @@ static int process_sync_pds_resv(struct amdkfd_process_info *process_info, vm_list_node) { struct amdgpu_bo *pd = peer_vm->root.bo; - ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv, + ret = amdgpu_sync_resv(NULL, sync, amdkcl_ttm_resvp(&pd->tbo), AMDGPU_SYNC_NE_OWNER, AMDGPU_FENCE_OWNER_KFD); if (ret) @@ -1413,7 +1413,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, AMDGPU_FENCE_OWNER_KFD, false); if (ret) goto wait_pd_fail; - ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(&vm->root.bo->tbo), 1); if (ret) goto reserve_shared_fail; dma_resv_add_fence(vm->root.bo->tbo.base.resv, @@ -3092,7 +3092,7 @@ int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem * Add process eviction fence to bo so they can * evict each other. */ - ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(&gws_bo->tbo), 1); if (ret) goto reserve_shared_fail; dma_resv_add_fence(gws_bo->tbo.base.resv, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index a2adaacf6adb2..7af5277d85083 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -810,7 +810,7 @@ static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo) struct ttm_operation_ctx ctx = { .interruptible = true, .no_wait_gpu = false, - .resv = bo->tbo.base.resv + .resv = amdkcl_ttm_resvp(&bo->tbo), }; uint32_t domain; int r; @@ -1242,7 +1242,7 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) drm_exec_for_each_locked_object(&p->exec, index, obj) { struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); - struct dma_resv *resv = bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&bo->tbo); enum amdgpu_sync_mode sync_mode; sync_mode = amdgpu_bo_explicit_sync(bo) ? @@ -1825,7 +1825,7 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, *map = mapping; /* Double check that the BO is reserved by this CS */ - if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->exec.ticket) + if (dma_resv_locking_ctx(amdkcl_ttm_resvp(&(*bo)->tbo)) != &parser->exec.ticket) return -EINVAL; /* Make sure VRAM is allocated contigiously */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 9e463d3ee9277..feaa4c3e163dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -249,7 +249,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, goto unpin; } - r = dma_resv_get_fences(new_abo->tbo.base.resv, DMA_RESV_USAGE_WRITE, + r = dma_resv_get_fences(amdkcl_ttm_resvp(&new_abo->tbo), DMA_RESV_USAGE_WRITE, &work->shared_count, &work->shared); if (unlikely(r != 0)) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 45325beb2f818..bbaa97fe806d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -88,6 +88,25 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, attach->peer2peer = false; #endif + r = amdgpu_bo_reserve(bo, false); + if (unlikely(r != 0)) + goto out; + + /* + * We only create shared fences for internal use, but importers + * of the dmabuf rely on exclusive fences for implicitly + * tracking write hazards. As any of the current fences may + * correspond to a write, we need to convert all existing + * fences on the reservation object into a single exclusive + * fence. + */ + r = __dma_resv_make_exclusive(amdkcl_ttm_resvp(&bo->tbo)); + if (r) + goto out; + + bo->prime_shared_count++; + amdgpu_bo_unreserve(bo); + amdgpu_vm_bo_update_shared(bo); return 0; @@ -436,7 +455,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { struct amdgpu_vm *vm = bo_base->vm; - struct dma_resv *resv = vm->root.bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&vm->root.base.bo->tbo); if (ticket) { /* When we get an error here it means that somebody diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index d5e685c5e28b9..28f4285213c4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -483,7 +483,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, if (r) return r; - resv = vm->root.bo->tbo.base.resv; + resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); } initial_domain = (u32)(0xffffffff & args->in.domains); @@ -684,7 +684,7 @@ int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, return -ENOENT; robj = gem_to_amdgpu_bo(gobj); - ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ, + ret = dma_resv_wait_timeout(amdkcl_ttm_resvp(&robj->tbo), DMA_RESV_USAGE_READ, true, timeout); /* ret == 0 means not signaled, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index e36fede7f74c3..3c928bc9d48c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -78,7 +78,7 @@ static bool amdgpu_hmm_invalidate_gfx(struct mmu_interval_notifier *mni, mmu_interval_set_seq(mni, cur_seq); - r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP, + r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_BOOKKEEP, false, MAX_SCHEDULE_TIMEOUT); mutex_unlock(&adev->notifier_lock); if (r <= 0) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 8a76960803c65..bd2d21f1698f1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1528,7 +1528,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, amdgpu_vm_fini(adev, &fpriv->vm); if (pasid) - amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); + amdgpu_pasid_free_delayed(amdkcl_ttm_resvp(&pd->tbo), pasid); amdgpu_bo_unref(&pd); idr_for_each_entry(&fpriv->bo_list_handles, list, handle) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 2f9dc29dd5f0a..5bd71734d1567 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -739,7 +739,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev, fail_unreserve: if (!bp->resv) - dma_resv_unlock(bo->tbo.base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(&bo->tbo)); amdgpu_bo_unref(&bo); return r; } @@ -823,7 +823,7 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) return -EPERM; - r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL, + r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL, false, MAX_SCHEDULE_TIMEOUT); if (r < 0) return r; @@ -1142,7 +1142,7 @@ void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) struct amdgpu_bo_user *ubo; BUG_ON(bo->tbo.type == ttm_bo_type_kernel); - dma_resv_assert_held(bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&bo->tbo)); ubo = to_amdgpu_bo_user(bo); if (tiling_flags) @@ -1303,7 +1303,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) * So when this locking here fails something is wrong with the reference * counting. */ - if (WARN_ON_ONCE(!dma_resv_trylock(&bo->base._resv))) + if (WARN_ON_ONCE(!dma_resv_trylock(&amdkcl_ttm_resv(bo)))) return; amdgpu_amdkfd_remove_all_eviction_fences(abo); @@ -1313,7 +1313,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev))) goto out; - r = dma_resv_reserve_fences(&bo->base._resv, 1); + r = dma_resv_reserve_fences(&amdkcl_ttm_resv(bo), 1); if (r) goto out; @@ -1326,7 +1326,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) dma_fence_put(fence); out: - dma_resv_unlock(&bo->base._resv); + dma_resv_unlock(&amdkcl_ttm_resv(bo)); } /** @@ -1391,7 +1391,7 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, bool shared) { - struct dma_resv *resv = bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&bo->tbo); int r; r = dma_resv_reserve_fences(resv, 1); @@ -1447,7 +1447,7 @@ int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); - return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, + return amdgpu_bo_sync_wait_resv(adev, amdkcl_ttm_resvp(&bo->tbo), AMDGPU_SYNC_NE_OWNER, owner, intr); } @@ -1464,7 +1464,7 @@ int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) { WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM); - WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && + WARN_ON_ONCE(!dma_resv_is_locked(amdkcl_ttm_resvp(&bo->tbo)) && !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 27ab4e754b2a9..5d8dade52edf3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -396,7 +396,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo, r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, new_mem->size, amdgpu_bo_encrypted(abo), - bo->base.resv, &fence); + amdkcl_ttm_resvp(bo), &fence); if (r) goto error; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 74758b5ffc6c8..78b272faf10da 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -1170,7 +1170,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, goto err_free; } else { r = drm_sched_job_add_resv_dependencies(&job->base, - bo->tbo.base.resv, + amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL); if (r) goto err_free; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 39b4250ede0ff..ab12fe26b854b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1258,12 +1258,12 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, /* Implicitly sync to command submissions in the same VM before * unmapping. */ - r = amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.base.resv, + r = amdgpu_sync_resv(adev, &sync, amdkcl_ttm_resvp(&vm->root.bo->tbo), AMDGPU_SYNC_EQ_OWNER, vm); if (r) goto error_free; if (bo) { - r = amdgpu_sync_kfd(&sync, bo->tbo.base.resv); + r = amdgpu_sync_kfd(&sync, amdkcl_ttm_resvp(&bo->tbo)); if (r) goto error_free; } @@ -1536,7 +1536,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, * unmapping. */ amdgpu_sync_create(&sync); - r = amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.base.resv, + r = amdgpu_sync_resv(adev, &sync, amdkcl_ttm_resvp(&vm->root.bo->tbo), AMDGPU_SYNC_EQ_OWNER, vm); if (r) goto error_free; @@ -1608,7 +1608,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev, while (!list_empty(&vm->invalidated)) { bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, base.vm_status); - resv = bo_va->base.bo->tbo.base.resv; + resv = amdkcl_ttm_resvp(&bo_va->base.bo->tbo); spin_unlock(&vm->status_lock); /* Try to reserve the BO to avoid clearing its ptes */ @@ -2127,7 +2127,7 @@ void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket) struct amdgpu_bo *bo; bo = mapping->bo_va->base.bo; - if (dma_resv_locking_ctx(bo->tbo.base.resv) != + if (dma_resv_locking_ctx(amdkcl_ttm_resvp(&bo->tbo)) != ticket) continue; } @@ -2214,7 +2214,7 @@ bool amdgpu_vm_evictable(struct amdgpu_bo *bo) return true; /* Don't evict VM page tables while they are busy */ - if (!dma_resv_test_signaled(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP)) + if (!dma_resv_test_signaled(amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_BOOKKEEP)) return false; /* Try to block ongoing updates */ @@ -2602,7 +2602,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, } amdgpu_vm_bo_base_init(&vm->root, vm, root_bo); - r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&root_bo->tbo), 1); if (r) goto error_free_root; @@ -3159,7 +3159,7 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, */ bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo) { - return bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv; + return bo && amdkcl_ttm_resvp(&bo->tbo) == amdkcl_ttm_resvp(&vm->root.bo->tbo); } void amdgpu_vm_print_task_info(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 62ecc02eb26be..308bd76a19a9a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -49,6 +49,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_SG_TT_INIT + AC_AMDGPU_TTM_BUFFER_OBJECT AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE diff --git a/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 b/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 new file mode 100644 index 0000000000000..6bf4a39e9679c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # v5.3-rc1-374-ge7f0141a217f drm/ttm: drop ttm_buffer_object->resv +dnl # v5.3-rc1-370-g5a5011a72489 drm/amdgpu: switch driver from bo->resv to bo->base.resv +dnl # v5.3-rc1-367-ge532a135d704 drm/ttm: switch ttm core from bo->resv to bo->base.resv +dnl # v5.3-rc1-365-gb96f3e7c8069 drm/ttm: use gem vma_node +dnl # v5.3-rc1-364-g1e053b10ba60 drm/ttm: use gem reservation object +dnl # v5.3-rc1-362-gc105de2828e1 drm/amdgpu: use embedded gem object +dnl # v5.3-rc1-358-g8eb8833e7ed3 drm/ttm: add gem base object +dnl # v5.0-rc1-1004-g1ba627148ef5 drm: Add reservation_object to drm_gem_object +dnl # +AC_DEFUN([AC_AMDGPU_TTM_BUFFER_OBJECT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_gem_object *gem_obj = NULL; + gem_obj->resv = &gem_obj->_resv; + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_RESV, 1, + [ttm_buffer_object->base is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index f4d9e68b21e70..63b0733610d86 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -76,7 +76,7 @@ static void ttm_bo_mem_space_debug(struct ttm_buffer_object *bo, */ void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo) { - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (bo->resource) ttm_resource_move_to_lru_tail(bo->resource); @@ -100,7 +100,7 @@ EXPORT_SYMBOL(ttm_bo_move_to_lru_tail); void ttm_bo_set_bulk_move(struct ttm_buffer_object *bo, struct ttm_lru_bulk_move *bulk) { - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (bo->bulk_move == bulk) return; @@ -190,13 +190,13 @@ static int ttm_bo_individualize_resv(struct ttm_buffer_object *bo) { int r; - if (bo->base.resv == &bo->base._resv) + if (amdkcl_ttm_resvp(bo) == &amdkcl_ttm_resv(bo)) return 0; - BUG_ON(!dma_resv_trylock(&bo->base._resv)); + BUG_ON(!dma_resv_trylock(&amdkcl_ttm_resv(bo))); - r = dma_resv_copy_fences(&bo->base._resv, bo->base.resv); - dma_resv_unlock(&bo->base._resv); + r = dma_resv_copy_fences(&amdkcl_ttm_resv(bo), amdkcl_ttm_resvp(bo)); + dma_resv_unlock(&amdkcl_ttm_resv(bo)); if (r) return r; @@ -206,7 +206,7 @@ static int ttm_bo_individualize_resv(struct ttm_buffer_object *bo) * the resv object while holding the lru_lock. */ spin_lock(&bo->bdev->lru_lock); - bo->base.resv = &bo->base._resv; + amdkcl_ttm_resvp(bo) = &amdkcl_ttm_resv(bo); spin_unlock(&bo->bdev->lru_lock); } @@ -215,7 +215,7 @@ static int ttm_bo_individualize_resv(struct ttm_buffer_object *bo) static void ttm_bo_flush_all_fences(struct ttm_buffer_object *bo) { - struct dma_resv *resv = &bo->base._resv; + struct dma_resv *resv = &amdkcl_ttm_resv(bo); struct dma_resv_iter cursor; struct dma_fence *fence; @@ -237,11 +237,11 @@ static void ttm_bo_delayed_delete(struct work_struct *work) bo = container_of(work, typeof(*bo), delayed_delete); - dma_resv_wait_timeout(&bo->base._resv, DMA_RESV_USAGE_BOOKKEEP, false, + dma_resv_wait_timeout(&amdkcl_ttm_resv(bo), DMA_RESV_USAGE_BOOKKEEP, false, MAX_SCHEDULE_TIMEOUT); - dma_resv_lock(bo->base.resv, NULL); + dma_resv_lock(amdkcl_ttm_resvp(bo), NULL); ttm_bo_cleanup_memtype_use(bo); - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); ttm_bo_put(bo); } @@ -261,7 +261,7 @@ static void ttm_bo_release(struct kref *kref) /* Last resort, if we fail to allocate memory for the * fences block for the BO to become idle */ - dma_resv_wait_timeout(bo->base.resv, + dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP, false, 30 * HZ); } @@ -272,11 +272,11 @@ static void ttm_bo_release(struct kref *kref) drm_vma_offset_remove(bdev->vma_manager, &bo->base.vma_node); ttm_mem_io_free(bdev, bo->resource); - if (!dma_resv_test_signaled(&bo->base._resv, + if (!dma_resv_test_signaled(&amdkcl_ttm_resv(bo), DMA_RESV_USAGE_BOOKKEEP) || (want_init_on_free() && (bo->ttm != NULL)) || bo->type == ttm_bo_type_sg || - !dma_resv_trylock(bo->base.resv)) { + !dma_resv_trylock(amdkcl_ttm_resvp(bo))) { /* The BO is not idle, resurrect it for delayed destroy */ ttm_bo_flush_all_fences(bo); bo->deleted = true; @@ -311,7 +311,7 @@ static void ttm_bo_release(struct kref *kref) } ttm_bo_cleanup_memtype_use(bo); - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); } atomic_dec(&ttm_glob.bo_count); @@ -366,7 +366,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, memset(&hop, 0, sizeof(hop)); - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); placement.num_placement = 0; bdev->funcs->evict_flags(bo, &placement); @@ -479,7 +479,7 @@ int ttm_bo_evict_first(struct ttm_device *bdev, struct ttm_resource_manager *man ret = ttm_bo_evict(bo, ctx); } out_bo_moved: - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); out_no_lock: ttm_bo_put(bo); return ret; @@ -681,7 +681,7 @@ static int ttm_bo_add_move_fence(struct ttm_buffer_object *bo, return ret; } - dma_resv_add_fence(bo->base.resv, fence, DMA_RESV_USAGE_KERNEL); + dma_resv_add_fence(amdkcl_ttm_resvp(bo), fence, DMA_RESV_USAGE_KERNEL); ret = dma_resv_reserve_fences(bo->base.resv, 1); dma_fence_put(fence); @@ -717,8 +717,8 @@ static int ttm_bo_alloc_resource(struct ttm_buffer_object *bo, struct ww_acquire_ctx *ticket; int i, ret; - ticket = dma_resv_locking_ctx(bo->base.resv); - ret = dma_resv_reserve_fences(bo->base.resv, 1); + ticket = dma_resv_locking_ctx(amdkcl_ttm_resvp(bo)); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(bo), 1); if (unlikely(ret)) return ret; @@ -824,7 +824,7 @@ int ttm_bo_validate(struct ttm_buffer_object *bo, bool force_space; int ret; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); /* * Remove the backing store if no placement is given. @@ -942,9 +942,9 @@ int ttm_bo_init_reserved(struct ttm_device *bdev, struct ttm_buffer_object *bo, bo->sg = sg; bo->bulk_move = NULL; if (resv) - bo->base.resv = resv; + amdkcl_ttm_resvp(bo) = resv; else - bo->base.resv = &bo->base._resv; + amdkcl_ttm_resvp(bo) = &amdkcl_ttm_resv(bo); atomic_inc(&ttm_glob.bo_count); /* @@ -962,7 +962,7 @@ int ttm_bo_init_reserved(struct ttm_device *bdev, struct ttm_buffer_object *bo, * since otherwise lockdep will be angered in radeon. */ if (!resv) - WARN_ON(!dma_resv_trylock(bo->base.resv)); + WARN_ON(!dma_resv_trylock(amdkcl_ttm_resvp(bo))); else dma_resv_assert_held(resv); @@ -1072,14 +1072,14 @@ int ttm_bo_wait_ctx(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx) long ret; if (ctx->no_wait_gpu) { - if (dma_resv_test_signaled(bo->base.resv, + if (dma_resv_test_signaled(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP)) return 0; else return -EBUSY; } - ret = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP, + ret = dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP, ctx->interruptible, 15 * HZ); if (unlikely(ret < 0)) return ret; diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index acbbca9d5c92f..96b8667db8ec9 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -251,11 +251,11 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo, fbo->base.destroy = &ttm_transfered_destroy; fbo->base.pin_count = 0; if (bo->type != ttm_bo_type_sg) - fbo->base.base.resv = &fbo->base.base._resv; + amdkcl_ttm_resvp(&fbo->base) = &amdkcl_ttm_resv(&fbo->base); - dma_resv_init(&fbo->base.base._resv); + dma_resv_init(&amdkcl_ttm_resv(&fbo->base)); fbo->base.base.dev = NULL; - ret = dma_resv_trylock(&fbo->base.base._resv); + ret = dma_resv_trylock(&amdkcl_ttm_resv(&fbo->base)); WARN_ON(!ret); ret = dma_resv_reserve_fences(&fbo->base.base._resv, 1); @@ -622,7 +622,7 @@ static int ttm_bo_move_to_ghost(struct ttm_buffer_object *bo, if (ret) return ret; - dma_resv_add_fence(&ghost_obj->base._resv, fence, + dma_resv_add_fence(&amdkcl_ttm_resv(ghost_obj), fence, DMA_RESV_USAGE_KERNEL); /** @@ -636,7 +636,7 @@ static int ttm_bo_move_to_ghost(struct ttm_buffer_object *bo, else bo->ttm = NULL; - dma_resv_unlock(&ghost_obj->base._resv); + dma_resv_unlock(&amdkcl_ttm_resv(ghost_obj)); ttm_bo_put(ghost_obj); return 0; } @@ -690,7 +690,7 @@ int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo, struct ttm_resource_manager *man = ttm_manager_type(bdev, new_mem->mem_type); int ret = 0; - dma_resv_add_fence(bo->base.resv, fence, DMA_RESV_USAGE_KERNEL); + dma_resv_add_fence(amdkcl_ttm_resvp(bo), fence, DMA_RESV_USAGE_KERNEL); if (!evict) ret = ttm_bo_move_to_ghost(bo, fence, man->use_tt); else if (!from->use_tt && pipeline) @@ -783,14 +783,14 @@ int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo) if (ret) goto error_destroy_tt; - ret = dma_resv_copy_fences(&ghost->base._resv, bo->base.resv); + ret = dma_resv_copy_fences(&amdkcl_ttm_resv(ghost), amdkcl_ttm_resvp(bo)); /* Last resort, wait for the BO to be idle when we are OOM */ if (ret) { dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP, false, MAX_SCHEDULE_TIMEOUT); } - dma_resv_unlock(&ghost->base._resv); + dma_resv_unlock(&amdkcl_ttm_resv(ghost)); ttm_bo_put(ghost); bo->ttm = ttm; return 0; diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index b47020fca1992..ba7563e7e5a7c 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -62,10 +62,10 @@ static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, drm_gem_object_get(&bo->base); mmap_read_unlock(vmf->vma->vm_mm); - (void)dma_resv_wait_timeout(bo->base.resv, + (void)dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_KERNEL, true, MAX_SCHEDULE_TIMEOUT); - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); drm_gem_object_put(&bo->base); return VM_FAULT_RETRY; } @@ -124,7 +124,7 @@ vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, * for reserve, and if it fails, retry the fault after waiting * for the buffer to become unreserved. */ - if (unlikely(!dma_resv_trylock(bo->base.resv))) { + if (unlikely(!dma_resv_trylock(amdkcl_ttm_resvp(bo)))) { /* * If the fault allows retry and this is the first * fault attempt, we try to release the mmap_lock @@ -134,16 +134,16 @@ vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, if (!(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) { drm_gem_object_get(&bo->base); mmap_read_unlock(vmf->vma->vm_mm); - if (!dma_resv_lock_interruptible(bo->base.resv, + if (!dma_resv_lock_interruptible(amdkcl_ttm_resvp(bo), NULL)) - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); drm_gem_object_put(&bo->base); } return VM_FAULT_RETRY; } - if (dma_resv_lock_interruptible(bo->base.resv, NULL)) + if (dma_resv_lock_interruptible(amdkcl_ttm_resvp(bo), NULL)) return VM_FAULT_NOPAGE; } @@ -153,7 +153,7 @@ vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, */ if (bo->ttm && (bo->ttm->page_flags & TTM_TT_FLAG_EXTERNAL)) { if (!(bo->ttm->page_flags & TTM_TT_FLAG_EXTERNAL_MAPPABLE)) { - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); return VM_FAULT_SIGBUS; } } @@ -342,7 +342,7 @@ vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf) if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) return ret; - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); return ret; } diff --git a/drivers/gpu/drm/ttm/ttm_execbuf_util.c b/drivers/gpu/drm/ttm/ttm_execbuf_util.c index bc7a83a9fe443..2fe50abde4b3e 100644 --- a/drivers/gpu/drm/ttm/ttm_execbuf_util.c +++ b/drivers/gpu/drm/ttm/ttm_execbuf_util.c @@ -37,7 +37,7 @@ static void ttm_eu_backoff_reservation_reverse(struct list_head *list, list_for_each_entry_continue_reverse(entry, list, head) { struct ttm_buffer_object *bo = entry->bo; - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); } } @@ -53,7 +53,7 @@ void ttm_eu_backoff_reservation(struct ww_acquire_ctx *ticket, struct ttm_buffer_object *bo = entry->bo; ttm_bo_move_to_lru_tail_unlocked(bo); - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); } if (ticket) @@ -101,7 +101,7 @@ int ttm_eu_reserve_buffers(struct ww_acquire_ctx *ticket, num_fences = max(entry->num_shared, 1u); if (!ret) { - ret = dma_resv_reserve_fences(bo->base.resv, + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(bo), num_fences); if (!ret) continue; @@ -118,7 +118,7 @@ int ttm_eu_reserve_buffers(struct ww_acquire_ctx *ticket, } if (!ret) - ret = dma_resv_reserve_fences(bo->base.resv, + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(bo), num_fences); if (unlikely(ret != 0)) { @@ -152,10 +152,10 @@ void ttm_eu_fence_buffer_objects(struct ww_acquire_ctx *ticket, list_for_each_entry(entry, list, head) { struct ttm_buffer_object *bo = entry->bo; - dma_resv_add_fence(bo->base.resv, fence, entry->num_shared ? + dma_resv_add_fence(amdkcl_ttm_resvp(bo), fence, entry->num_shared ? DMA_RESV_USAGE_READ : DMA_RESV_USAGE_WRITE); ttm_bo_move_to_lru_tail_unlocked(bo); - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); } if (ticket) ww_acquire_fini(ticket); diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 15bad8ef53005..7559139b73d19 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -71,7 +71,7 @@ int ttm_tt_create(struct ttm_buffer_object *bo, bool zero_alloc) struct drm_device *ddev = bo->base.dev; uint32_t page_flags = 0; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (bo->ttm) return 0; diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h index 479b7ed075c0f..cd5720ef66c21 100644 --- a/include/drm/ttm/ttm_bo.h +++ b/include/drm/ttm/ttm_bo.h @@ -37,6 +37,9 @@ #include #include "ttm_device.h" +#ifndef HAVE_CONFIG_H +#define HAVE_DRM_GEM_OBJECT_RESV 1 +#endif /* Default number of pre-faulted pages in the TTM fault handler */ #define TTM_BO_VM_NUM_PREFAULT 16 @@ -135,6 +138,11 @@ struct ttm_buffer_object { * reservation lock. */ struct sg_table *sg; + +#if !defined(HAVE_DRM_GEM_OBJECT_RESV) + struct dma_resv *resv; + struct dma_resv ttm_resv; +#endif }; #define TTM_BO_MAP_IOMEM_MASK 0x80 @@ -252,6 +260,14 @@ bool ttm_bo_shrink_suitable(struct ttm_buffer_object *bo, struct ttm_operation_c bool ttm_bo_shrink_avoid_wait(void); +#if defined(HAVE_DRM_GEM_OBJECT_RESV) +#define amdkcl_ttm_resv(bo) ((bo)->base._resv) +#define amdkcl_ttm_resvp(bo) ((bo)->base.resv) +#else +#define amdkcl_ttm_resv(bo) ((bo)->ttm_resv) +#define amdkcl_ttm_resvp(bo) ((bo)->resv) +#endif + /** * ttm_bo_reserve: * @@ -286,14 +302,14 @@ static inline int ttm_bo_reserve(struct ttm_buffer_object *bo, if (WARN_ON(ticket)) return -EBUSY; - success = dma_resv_trylock(bo->base.resv); + success = dma_resv_trylock(amdkcl_ttm_resvp(bo)); return success ? 0 : -EBUSY; } if (interruptible) - ret = dma_resv_lock_interruptible(bo->base.resv, ticket); + ret = dma_resv_lock_interruptible(amdkcl_ttm_resvp(bo), ticket); else - ret = dma_resv_lock(bo->base.resv, ticket); + ret = dma_resv_lock(amdkcl_ttm_resvp(bo), ticket); if (ret == -EINTR) return -ERESTARTSYS; return ret; @@ -314,13 +330,13 @@ static inline int ttm_bo_reserve_slowpath(struct ttm_buffer_object *bo, struct ww_acquire_ctx *ticket) { if (interruptible) { - int ret = dma_resv_lock_slow_interruptible(bo->base.resv, + int ret = dma_resv_lock_slow_interruptible(amdkcl_ttm_resvp(bo), ticket); if (ret == -EINTR) ret = -ERESTARTSYS; return ret; } - dma_resv_lock_slow(bo->base.resv, ticket); + dma_resv_lock_slow(amdkcl_ttm_resvp(bo), ticket); return 0; } @@ -365,7 +381,7 @@ static inline void ttm_bo_move_null(struct ttm_buffer_object *bo, static inline void ttm_bo_unreserve(struct ttm_buffer_object *bo) { ttm_bo_move_to_lru_tail_unlocked(bo); - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); } /** From 554ec917190231f60a7d052fb4fb769b429215ce Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 17 Apr 2020 11:36:17 +0800 Subject: [PATCH 0240/2653] drm/amdkcl: Test whether dma-buf dynamic locking is available It's a squash of 5e00d69a73fb drm/amdkcl: introduce parallel autoconf tests execution 57da2736175c drm/amdkcl: Test whether drm_gem_map_attach() wants 2 args a881ad26f08d drm/amdkcl: Test whether dma-buf dynamic locking is available Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Adam Yang Reviewed-by: Flora Cui Reviewed-by: Rui Teng Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 254 ++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 9 + drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 16 ++ .../gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 | 14 + 4 files changed, 293 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index bbaa97fe806d8..b46ebc7f2f2ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -43,6 +43,146 @@ #include #include +static int +__dma_resv_make_exclusive(struct dma_resv *obj) +{ + struct dma_fence **fences; + unsigned int count; + int r; + + if (!dma_resv_shared_list(obj)) /* no shared fences to convert */ + return 0; + + r = dma_resv_get_fences(obj, NULL, &count, &fences); + if (r) + return r; + + if (count == 0) { + /* Now that was unexpected. */ + } else if (count == 1) { + dma_resv_add_excl_fence(obj, fences[0]); + dma_fence_put(fences[0]); + kfree(fences); + } else { + struct dma_fence_array *array; + + array = dma_fence_array_create(count, fences, + dma_fence_context_alloc(1), 0, + false); + if (!array) + goto err_fences_put; + + dma_resv_add_excl_fence(obj, &array->base); + dma_fence_put(&array->base); + } + + return 0; + +err_fences_put: + while (count--) + dma_fence_put(fences[count]); + kfree(fences); + return -ENOMEM; +} + +#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ + !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +/** + * amdgpu_dma_buf_map_attach - &dma_buf_ops.attach implementation + * @dma_buf: Shared DMA buffer + * @attach: DMA-buf attachment + * + * Makes sure that the shared DMA buffer can be accessed by the target device. + * For now, simply pins it to the GTT domain, where it should be accessible by + * all DMA devices. + * + * Returns: + * 0 on success or a negative error code on failure. + */ +static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf, +#ifndef HAVE_DRM_GEM_MAP_ATTACH_2ARGS + struct device *target_dev, +#endif + struct dma_buf_attachment *attach) +{ + struct drm_gem_object *obj = dma_buf->priv; + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + long r; + +#ifdef HAVE_DRM_GEM_MAP_ATTACH_2ARGS + r = drm_gem_map_attach(dma_buf, attach); +#else + r = drm_gem_map_attach(dma_buf, target_dev, attach); +#endif + if (r) + return r; + + r = amdgpu_bo_reserve(bo, false); + if (unlikely(r != 0)) + goto error_detach; + + + if (attach->dev->driver != adev->dev->driver) { + /* + * We only create shared fences for internal use, but importers + * of the dmabuf rely on exclusive fences for implicitly + * tracking write hazards. As any of the current fences may + * correspond to a write, we need to convert all existing + * fences on the reservation object into a single exclusive + * fence. + */ + r = __dma_resv_make_exclusive(amdkcl_ttm_resvp(&bo->tbo)); + if (r) + goto error_unreserve; + } + + /* pin buffer into GTT */ + r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); + if (r) + goto error_unreserve; + + if (attach->dev->driver != adev->dev->driver) + bo->prime_shared_count++; + +error_unreserve: + amdgpu_bo_unreserve(bo); + +error_detach: + if (r) + drm_gem_map_detach(dma_buf, attach); + return r; +} + +/** + * amdgpu_dma_buf_map_detach - &dma_buf_ops.detach implementation + * @dma_buf: Shared DMA buffer + * @attach: DMA-buf attachment + * + * This is called when a shared DMA buffer no longer needs to be accessible by + * another device. For now, simply unpins the buffer from GTT. + */ +static void amdgpu_dma_buf_map_detach(struct dma_buf *dma_buf, + struct dma_buf_attachment *attach) +{ + struct drm_gem_object *obj = dma_buf->priv; + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + int ret = 0; + + ret = amdgpu_bo_reserve(bo, true); + if (unlikely(ret != 0)) + goto error; + + amdgpu_bo_unpin(bo); + if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count) + bo->prime_shared_count--; + amdgpu_bo_unreserve(bo); + +error: + drm_gem_map_detach(dma_buf, attach); +} +#else static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops; /** @@ -284,6 +424,7 @@ static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach, amdgpu_bo_unpin(bo); #endif } +#endif /** * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation @@ -327,6 +468,16 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf, } const struct dma_buf_ops amdgpu_dmabuf_ops = { +#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ + !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) + .attach = amdgpu_dma_buf_map_attach, + .detach = amdgpu_dma_buf_map_detach, + .map_dma_buf = drm_gem_map_dma_buf, + .unmap_dma_buf = drm_gem_unmap_dma_buf, +#else +#ifdef HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING + .dynamic_mapping = true, +#endif .attach = amdgpu_dma_buf_attach, #ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN .pin = amdgpu_dma_buf_pin, @@ -334,6 +485,7 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = { #endif .map_dma_buf = amdgpu_dma_buf_map, .unmap_dma_buf = amdgpu_dma_buf_unmap, +#endif .release = drm_gem_dmabuf_release, .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access, .mmap = drm_gem_dmabuf_mmap, @@ -368,6 +520,107 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, return buf; } +#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ + !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +/** + * amdgpu_gem_prime_get_sg_table - &drm_driver.gem_prime_get_sg_table + * implementation + * @obj: GEM buffer object (BO) + * + * Returns: + * A scatter/gather table for the pinned pages of the BO's memory. + */ +struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + int npages = bo->tbo.ttm->num_pages; + + return drm_prime_pages_to_sg(obj->dev, bo->tbo.ttm->pages, npages); +} + +/** + * amdgpu_gem_prime_import_sg_table - &drm_driver.gem_prime_import_sg_table + * implementation + * @dev: DRM device + * @attach: DMA-buf attachment + * @sg: Scatter/gather table + * + * Imports shared DMA buffer memory exported by another device. + * + * Returns: + * A new GEM BO of the given DRM device, representing the memory + * described by the given DMA-buf attachment and scatter/gather table. + */ +struct drm_gem_object * +amdgpu_gem_prime_import_sg_table(struct drm_device *dev, + struct dma_buf_attachment *attach, + struct sg_table *sg) +{ + struct dma_resv *resv = attach->dmabuf->resv; + struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_bo *bo; + struct amdgpu_bo_param bp; + int ret; + + memset(&bp, 0, sizeof(bp)); + bp.size = attach->dmabuf->size; + bp.byte_align = PAGE_SIZE; + bp.domain = AMDGPU_GEM_DOMAIN_CPU; + bp.flags = 0; + bp.type = ttm_bo_type_sg; + bp.resv = resv; + dma_resv_lock(resv, NULL); + ret = amdgpu_bo_create(adev, &bp, &bo); + if (ret) + goto error; + + bo->tbo.sg = sg; + bo->tbo.ttm->sg = sg; + bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; + bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; + bo->prime_shared_count = 1; + + dma_resv_unlock(resv); + return &bo->tbo.base; + +error: + dma_resv_unlock(resv); + return ERR_PTR(ret); +} + +/** + * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation + * @dev: DRM device + * @dma_buf: Shared DMA buffer + * + * The main work is done by the &drm_gem_prime_import helper, which in turn + * uses &amdgpu_gem_prime_import_sg_table. + * + * Returns: + * GEM BO representing the shared DMA buffer for the given device. + */ +struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, + struct dma_buf *dma_buf) +{ + struct drm_gem_object *obj; + + if (dma_buf->ops == &amdgpu_dmabuf_ops) { + obj = dma_buf->priv; + if (obj->dev == dev) { + /* + * Importing dmabuf exported from out own gem increases + * refcount on gem itself instead of f_count of dmabuf. + */ + drm_gem_object_get(obj); + return obj; + } + } + + return drm_gem_prime_import(dev, dma_buf); +} + +#else + /** * amdgpu_dma_buf_create_obj - create BO for DMA-buf import * @@ -545,6 +798,7 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, obj->import_attach = attach; return obj; } +#endif /** * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h index 3e93b9b407a97..dd7c8ffa41cf4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h @@ -25,6 +25,15 @@ #include +#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ + !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); +struct drm_gem_object * +amdgpu_gem_prime_import_sg_table(struct drm_device *dev, + struct dma_buf_attachment *attach, + struct sg_table *sg); +#endif + struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, int flags); struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 index dc74e703be9bd..3f408896f437b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -32,6 +32,22 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_PIN, 1, [struct dma_buf_ops->pin() is available]) + ], [ + dnl # + dnl # commit v5.4-rc4-863-g15fd552d186c + dnl # dma-buf: change DMA-buf locking convention v3 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_buf_ops *dma_buf_ops = NULL; + dma_buf_ops->dynamic_mapping = true; + ],[ + AC_DEFINE(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING, 1, + [dma_buf dynamic_mapping is available]) + ],[ + AC_AMDGPU_DRM_GEM_MAP_ATTACH + ]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 new file mode 100644 index 0000000000000..031d62f21740f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 @@ -0,0 +1,14 @@ +dnl # +dnl # commit v4.17-rc3-491-ga19741e5e5a9 +dnl # dma_buf: remove device parameter from attach callback v2 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_MAP_ATTACH], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_gem_map_attach(NULL, NULL); + ], [drm_gem_map_attach], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_GEM_MAP_ATTACH_2ARGS, 1, + [drm_gem_map_attach() wants 2 arguments]) + ]) +]) From 1b8d2b0e2efa5cd331c616905c433482efab17bc Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 9 Dec 2019 14:15:16 +0800 Subject: [PATCH 0241/2653] drm/amdkcl: Test whether drm_drv->gem_prime_res_obj() is available It's a squash of 5e00d69a73fb drm/amdkcl: introduce parallel autoconf tests execution 22887005a0ef drm/amdkcl: Test whether drm_drv->gem_prime_res_obj() is available Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Slava Grigorev Change-Id: I60c3bf6ef7409f636ecb9912cda0b35967e170ad --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 16 ++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 +++++++ drivers/gpu/drm/amd/backport/backport.h | 3 +++ .../dkms/m4/drm-driver-gem-prime-res-obj.m4 | 22 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 50 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index b46ebc7f2f2ef..b5c8c36999edf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -520,6 +520,22 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, return buf; } +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ +/** + * amdgpu_gem_prime_res_obj - &drm_driver.gem_prime_res_obj implementation + * @obj: GEM BO + * + * Returns: + * The BO's reservation object. + */ +struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + + return amdkcl_ttm_resvp(&bo->tbo); +} +#endif + #if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 2eda9667f9d19..53dbb0d93a502 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3073,6 +3073,14 @@ static const struct drm_driver amdgpu_kms_driver = { #endif .gem_prime_import = amdgpu_gem_prime_import, +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ + .gem_prime_res_obj = amdgpu_gem_prime_res_obj, +#endif +#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ + !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) + .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, + .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, +#endif .name = DRIVER_NAME, .desc = DRIVER_DESC, diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 02f790b540220..bee3d491206e1 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -34,6 +34,9 @@ #include #include #include +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ +#include +#endif #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 new file mode 100644 index 0000000000000..cf63fed2c4727 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 @@ -0,0 +1,22 @@ +dnl # +dnl # commit v5.3-rc1-325-g51c98747113e +dnl # drm/amdgpu: Fill out gem_object->resv +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #else + #include + #endif + ], [ + struct drm_driver *drv = NULL; + drv->gem_prime_res_obj(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ, 1, + [drm_driver->gem_prime_res_obj() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 308bd76a19a9a..cceaf0c361193 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -63,6 +63,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME + AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_MEM_ENCRYPT_ACTIVE From 1fd7df1d959bfb1a897599127539914e64e323b3 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 6 Nov 2019 13:03:11 +0800 Subject: [PATCH 0242/2653] drm/amdkcl: add AMDKCL_AMDGPU_DMABUF_OPS v2:missing gem_prime_pin pointer Signed-off-by: Flora Cui Acked-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 63 +++++++++++++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 8 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 +++ drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/backport/kcl_drm_backport.h | 9 +++ 7 files changed, 90 insertions(+), 4 deletions(-) create mode 100644 include/kcl/backport/kcl_drm_backport.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index ef3af170dda4e..479b2eac67891 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -439,6 +439,10 @@ struct amdgpu_clock { uint32_t max_pixel_clock; }; +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) +extern const struct dma_buf_ops amdgpu_dmabuf_ops; +#endif + /* sub-allocation manager, it has to be protected by another lock. * By conception this is an helper for other part of the driver * like the indirect buffer or semaphore, which both have their diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index fbe7616555c83..983a1a994ba6b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -534,9 +534,11 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, if (IS_ERR(dma_buf)) return PTR_ERR(dma_buf); +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) if (dma_buf->ops != &amdgpu_dmabuf_ops) /* Can't handle non-graphics buffers */ goto out_put; +#endif obj = dma_buf->priv; if (obj->dev->driver != adev_to_drm(adev)->driver) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index b5c8c36999edf..22b9b692b9083 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -43,6 +43,7 @@ #include #include +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) static int __dma_resv_make_exclusive(struct dma_resv *obj) { @@ -492,6 +493,7 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = { .vmap = drm_gem_dmabuf_vmap, .vunmap = drm_gem_dmabuf_vunmap, }; +#endif /** * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation @@ -514,8 +516,10 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, return ERR_PTR(-EPERM); buf = drm_gem_prime_export(gobj, flags); +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) if (!IS_ERR(buf)) buf->ops = &amdgpu_dmabuf_ops; +#endif return buf; } @@ -594,7 +598,10 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, bo->tbo.ttm->sg = sg; bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; - bo->prime_shared_count = 1; +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) + if (attach->dmabuf->ops != &amdgpu_dmabuf_ops) +#endif + bo->prime_shared_count = 1; dma_resv_unlock(resv); return &bo->tbo.base; @@ -604,6 +611,7 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, return ERR_PTR(ret); } +#ifdef AMDKCL_AMDGPU_DMABUF_OPS /** * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation * @dev: DRM device @@ -634,9 +642,8 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, return drm_gem_prime_import(dev, dma_buf); } - +#endif #else - /** * amdgpu_dma_buf_create_obj - create BO for DMA-buf import * @@ -766,7 +773,6 @@ static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = { .move_notify = amdgpu_dma_buf_move_notify }; #endif - /** * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation * @dev: DRM device @@ -816,6 +822,53 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, } #endif +#ifndef AMDKCL_AMDGPU_DMABUF_OPS +int amdgpu_gem_prime_pin(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + long ret = 0; + + ret = amdgpu_bo_reserve(bo, false); + if (unlikely(ret != 0)) + return ret; + + /* + * Wait for all shared fences to complete before we switch to future + * use of exclusive fence on this prime shared bo. + */ + ret = dma_resv_wait_timeout_rcu(bo->tbo.resv, true, false, + MAX_SCHEDULE_TIMEOUT); + if (unlikely(ret < 0)) { + DRM_DEBUG_PRIME("Fence wait failed: %li\n", ret); + amdgpu_bo_unreserve(bo); + return ret; + } + + /* pin buffer into GTT */ + ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); + if (likely(ret == 0)) + bo->prime_shared_count++; + + amdgpu_bo_unreserve(bo); + return ret; +} + +void amdgpu_gem_prime_unpin(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + int ret = 0; + + ret = amdgpu_bo_reserve(bo, true); + if (unlikely(ret != 0)) + return; + + amdgpu_bo_unpin(bo); + if (bo->prime_shared_count) + bo->prime_shared_count--; + amdgpu_bo_unreserve(bo); +} +#endif + /** * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer * @@ -837,9 +890,11 @@ bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev, if (drm_gem_is_imported(obj)) { struct dma_buf *dma_buf = obj->dma_buf; +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) if (dma_buf->ops != &amdgpu_dmabuf_ops) /* No XGMI with non AMD GPUs */ return false; +#endif gobj = dma_buf->priv; bo = gem_to_amdgpu_bo(gobj); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h index dd7c8ffa41cf4..db75327913c95 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h @@ -36,10 +36,18 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, int flags); +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, struct dma_buf *dma_buf); +#else +int amdgpu_gem_prime_pin(struct drm_gem_object *obj); +void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); +#endif bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev, struct amdgpu_bo *bo); +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ +struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); +#endif extern const struct dma_buf_ops amdgpu_dmabuf_ops; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 53dbb0d93a502..e9581844118b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3072,7 +3072,13 @@ static const struct drm_driver amdgpu_kms_driver = { .show_fdinfo = amdgpu_show_fdinfo, #endif +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) .gem_prime_import = amdgpu_gem_prime_import, +#else + .gem_prime_import = drm_gem_prime_import, + .gem_prime_pin = amdgpu_gem_prime_pin, + .gem_prime_unpin = amdgpu_gem_prime_unpin, +#endif #ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ .gem_prime_res_obj = amdgpu_gem_prime_res_obj, #endif @@ -3082,6 +3088,7 @@ static const struct drm_driver amdgpu_kms_driver = { .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, #endif + .gem_prime_mmap = drm_gem_prime_mmap, .name = DRIVER_NAME, .desc = DRIVER_DESC, .major = KMS_DRIVER_MAJOR, diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index bee3d491206e1..786b0e8246e62 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -40,6 +40,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/backport/kcl_drm_backport.h b/include/kcl/backport/kcl_drm_backport.h new file mode 100644 index 0000000000000..1450036960b9c --- /dev/null +++ b/include/kcl/backport/kcl_drm_backport.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_DRM_BACKPORT_H +#define AMDKCL_DRM_BACKPORT_H + +#if DRM_VERSION_CODE >= DRM_VERSION(4, 17, 0) +#define AMDKCL_AMDGPU_DMABUF_OPS +#endif + +#endif/*AMDKCL_DRM_BACKPORT_H*/ From 411451af1cfc36b2ad8322fd5297e126d7d6cb13 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sat, 10 Oct 2015 17:11:12 +0800 Subject: [PATCH 0243/2653] drm/amdgpu: [hybrid] add query for aperture va range Signed-off-by: Flora Cui Reviewed-by: Jammy Zhou Reviewed-by: Alex Deucher Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 18 +++++++++++++ include/uapi/drm/amdgpu_drm.h | 35 +++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index bd2d21f1698f1..74e291d9f1020 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -632,6 +632,24 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return -EINVAL; switch (info->query) { + case AMDGPU_INFO_VIRTUAL_RANGE: { + struct drm_amdgpu_virtual_range range_info; + + switch (info->virtual_range.aperture) { + case AMDGPU_SUA_APERTURE_PRIVATE: + range_info.start = adev->gmc.private_aperture_start; + range_info.end = adev->gmc.private_aperture_end; + break; + case AMDGPU_SUA_APERTURE_SHARED: + range_info.start = adev->gmc.shared_aperture_start; + range_info.end = adev->gmc.shared_aperture_end; + break; + default: + return -EINVAL; + } + return copy_to_user(out, &range_info, + min((size_t)size, sizeof(range_info))) ? -EFAULT : 0; + } case AMDGPU_INFO_ACCEL_WORKING: ui32 = adev->accel_working; return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index dab5a759d9f4a..69cab011bf980 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -1216,6 +1216,12 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { /* query FW object size and alignment */ #define AMDGPU_INFO_UQ_FW_AREAS 0x24 +/* Hybrid Stack Specific Defs*/ +/* gpu capability */ +#define AMDGPU_INFO_CAPABILITY 0x50 +/* virtual range */ +#define AMDGPU_INFO_VIRTUAL_RANGE 0x51 + #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 @@ -1272,6 +1278,11 @@ struct drm_amdgpu_info { __u32 flags; } read_mmr_reg; + struct { + uint32_t aperture; + uint32_t _pad; + } virtual_range; + struct drm_amdgpu_query_fw query_fw; struct { @@ -1628,6 +1639,30 @@ struct drm_color_ctm_3x4 { __u64 matrix[12]; }; +/** + * Definition of System Unified Address (SUA) apertures + */ +#define AMDGPU_SUA_APERTURE_PRIVATE 1 +#define AMDGPU_SUA_APERTURE_SHARED 2 +struct drm_amdgpu_virtual_range { + uint64_t start; + uint64_t end; +}; + + +/* + * Definition of free sync enter and exit signals + * We may have more options in the future + */ +#define AMDGPU_FREESYNC_FULLSCREEN_ENTER 1 +#define AMDGPU_FREESYNC_FULLSCREEN_EXIT 2 + +struct drm_amdgpu_freesync { + __u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */ + /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */ + __u32 spare[7]; +}; + #if defined(__cplusplus) } #endif From e1cdecb583b8051dcc53c117f6ffd560fe61f494 Mon Sep 17 00:00:00 2001 From: "Le.Ma" Date: Thu, 14 Sep 2017 15:53:13 +0800 Subject: [PATCH 0244/2653] drm/amdgpu: [hybrid] add AMDGPU VERSION Signed-off-by: Le.Ma --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index e9581844118b9..ef8b5fc80abf3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -131,6 +131,7 @@ #define KMS_DRIVER_MINOR 64 #define KMS_DRIVER_PATCHLEVEL 0 +#define AMDGPU_VERSION "19.10.9.418" /* * amdgpu.debug module options. Are all disabled by default */ @@ -3157,6 +3158,10 @@ static int __init amdgpu_init(void) goto error_fence; DRM_INFO("amdgpu kernel modesetting enabled.\n"); + + DRM_INFO("amdgpu version: %s\n", AMDGPU_VERSION); + DRM_INFO("OS DRM version: %d.%d.%d\n", DRM_VER, DRM_PATCH, DRM_SUB); + amdgpu_register_atpx_handler(); amdgpu_acpi_detect(); @@ -3197,3 +3202,4 @@ module_exit(amdgpu_exit); MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); +MODULE_VERSION(AMDGPU_VERSION); From e313bd19b5335e22b7057f4e691d074bd9f752c1 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Thu, 29 Apr 2021 18:05:44 +0800 Subject: [PATCH 0245/2653] drm/amdgpu:[hybrid] use DEFINE_SHOW_ATTRIBUTE to create amdgpu_gpu_recover node This will get rid of the limitation of DEFINE_DEBUGFS_ATTRIBUTE on old distros, otherwise amdgpu_gpu_recover is not exposed. Signed-off-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 9e7506965cab2..fd1c72cf69282 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -993,9 +993,9 @@ static int amdgpu_debugfs_fence_info_show(struct seq_file *m, void *unused) * * Manually trigger a gpu reset at the next fence wait. */ -static int gpu_recover_get(void *data, u64 *val) +static int amdgpu_debugfs_gpu_recover_show(struct seq_file *m, void *unused) { - struct amdgpu_device *adev = (struct amdgpu_device *)data; + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; struct drm_device *dev = adev_to_drm(adev); int r; @@ -1008,7 +1008,7 @@ static int gpu_recover_get(void *data, u64 *val) if (amdgpu_reset_domain_schedule(adev->reset_domain, &adev->reset_work)) flush_work(&adev->reset_work); - *val = atomic_read(&adev->reset_domain->reset_res); + // *val = atomic_read(&adev->reset_domain->reset_res); pm_runtime_mark_last_busy(dev->dev); pm_runtime_put_autosuspend(dev->dev); @@ -1017,8 +1017,7 @@ static int gpu_recover_get(void *data, u64 *val) } DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_fence_info); -DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gpu_recover_fops, gpu_recover_get, NULL, - "%lld\n"); +DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gpu_recover); static void amdgpu_debugfs_reset_work(struct work_struct *work) { From fdd31068b87c2b9de0a77baf92400c396c67170e Mon Sep 17 00:00:00 2001 From: Jammy Zhou Date: Mon, 9 Nov 2015 13:39:37 +0800 Subject: [PATCH 0246/2653] drm/amdgpu: [hybrid] expose the pinning capability to user space The module option amdgpu.no_evict is added, and it is disabled by default now. Signed-off-by: Jammy Zhou Reviewed-by: Chunming Zhou Signed-off-by: Junwei Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8 ++++++++ include/uapi/drm/amdgpu_drm.h | 4 ++++ 5 files changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 479b2eac67891..520bf5bd925ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -190,6 +190,7 @@ extern int amdgpu_exp_hw_support; extern int amdgpu_dc; extern int amdgpu_sched_jobs; extern int amdgpu_sched_hw_submission; +extern int amdgpu_no_evict; extern uint amdgpu_pcie_gen_cap; extern uint amdgpu_pcie_lane_cap; extern u64 amdgpu_cg_mask; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index ef8b5fc80abf3..3c19d1ad22f82 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -175,6 +175,7 @@ int amdgpu_exp_hw_support; int amdgpu_dc = -1; int amdgpu_sched_jobs = 32; int amdgpu_sched_hw_submission = 2; +int amdgpu_no_evict; uint amdgpu_pcie_gen_cap; uint amdgpu_pcie_lane_cap; u64 amdgpu_cg_mask = 0xffffffffffffffff; @@ -504,6 +505,8 @@ module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); +MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); +module_param_named(no_evict, amdgpu_no_evict, int, 0444); /** * DOC: forcelongtraining (uint) * Force long memory training in resume. diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 28f4285213c4a..f0da588910ae2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -450,6 +450,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, AMDGPU_GEM_CREATE_EXPLICIT_SYNC | AMDGPU_GEM_CREATE_ENCRYPTED | AMDGPU_GEM_CREATE_GFX12_DCC | + AMDGPU_GEM_CREATE_NO_EVICT | AMDGPU_GEM_CREATE_DISCARDABLE)) return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 5bd71734d1567..17861c2453c09 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -735,6 +735,14 @@ int amdgpu_bo_create(struct amdgpu_device *adev, if (bp->type == ttm_bo_type_device) bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; + if ((bp->flags & AMDGPU_GEM_CREATE_NO_EVICT) && amdgpu_no_evict) { + r = amdgpu_bo_reserve(bo, false); + if (unlikely(r != 0)) + return r; + r = amdgpu_bo_pin(bo, bp->domain); + amdgpu_bo_unreserve(bo); + } + return 0; fail_unreserve: diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 69cab011bf980..4c403a46a1842 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -180,6 +180,10 @@ extern "C" { /* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */ #define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16) +/* hybrid specific */ +/* Flag that the memory allocation should be pinned */ +#define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31) + struct drm_amdgpu_gem_create_in { /** the requested memory size */ __u64 bo_size; From 273a06ba9c5103fc4b3d9ff810d7a4f0204d053c Mon Sep 17 00:00:00 2001 From: jimqu Date: Mon, 16 Nov 2015 14:03:15 +0800 Subject: [PATCH 0247/2653] drm/amdgpu: [hybrid] add query amdgpu capability function with this function, it could return capability to user space driver. Change-Id: Icad47e8d0621f9e8b8b9baedb751c11ded6c9449 Signed-off-by: JimQu Reviewed-by: Chunming Zhou Reviewed-by: Jammy Zhou Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 9 +++++++++ include/uapi/drm/amdgpu_drm.h | 5 +++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 74e291d9f1020..011c7b0110065 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1139,6 +1139,15 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return -EINVAL; } } + case AMDGPU_INFO_CAPABILITY: { + struct drm_amdgpu_capability cap; + + memset(&cap, 0, sizeof(cap)); + if (amdgpu_no_evict) + cap.flag |= AMDGPU_CAPABILITY_PIN_MEM_FLAG; + return copy_to_user(out, &cap, + min((size_t)size, sizeof(cap))) ? -EFAULT : 0; + } case AMDGPU_INFO_SENSOR: { if (!adev->pm.dpm_enabled) return -ENOENT; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 4c403a46a1842..af5f9df48aada 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -1225,6 +1225,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { #define AMDGPU_INFO_CAPABILITY 0x50 /* virtual range */ #define AMDGPU_INFO_VIRTUAL_RANGE 0x51 +/* query pin memory capability */ +#define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff @@ -1653,6 +1655,9 @@ struct drm_amdgpu_virtual_range { uint64_t end; }; +struct drm_amdgpu_capability { + __u32 flag; +}; /* * Definition of free sync enter and exit signals From 84422e1ba04d9b70f9c13108107f84a92344dd0f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 1 Sep 2016 12:33:01 +0800 Subject: [PATCH 0248/2653] drm/amdgpu: [hybrid] add AMDGPU_GEM_CREATE_TOP_DOWN flag so that the buffer could be allocated from the top of domain Change-Id: I7dc4ba02b78b18330c7fe00841970ab9cccbded5 Signed-off-by: Flora Cui Reviewed-by: Hawking Zhang Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_object.c --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 ++++- include/uapi/drm/amdgpu_drm.h | 2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 17861c2453c09..33dfe413d9c88 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -113,7 +113,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) struct ttm_placement *placement = &abo->placement; struct ttm_place *places = abo->placements; u64 flags = abo->flags; - u32 c = 0; + u32 c = 0, i; if (domain & AMDGPU_GEM_DOMAIN_VRAM) { unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; @@ -212,6 +212,9 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS); + for (i = 0; i < c; i++) + if (flags & AMDGPU_GEM_CREATE_TOP_DOWN) + places[i].flags |= TTM_PL_FLAG_TOPDOWN; placement->num_placement = c; placement->placement = places; } diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index af5f9df48aada..824bc66e96843 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -181,6 +181,8 @@ extern "C" { #define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16) /* hybrid specific */ +/* Flag that the memory allocation should be from top of domain */ +#define AMDGPU_GEM_CREATE_TOP_DOWN (1ULL << 30) /* Flag that the memory allocation should be pinned */ #define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31) From 7dcb5f318f109de01144c1705745b5ff4af2db54 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Thu, 6 Jul 2017 14:45:08 +0800 Subject: [PATCH 0249/2653] drm/amdgpu: [hybrid] always to use amdgpu to support CI/SI asics on hybrid - this patch is needed only by hybrid staging - we may update packing script to add cik_support system config in future. Then this commit will be not needed. Signed-off-by: Kent Russell Signed-off-by: Flora Cui Signed-off-by: Evan Quan Reviewed-by: Junwei Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/Kconfig | 8 ++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++---- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig index 1acfed2f92efb..40cdfd4f5a7fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/Kconfig +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig @@ -59,11 +59,11 @@ config DRM_AMDGPU_CIK Choose this option if you want to enable support for CIK (Sea Islands) asics. - CIK is already supported in radeon. Support for CIK in amdgpu - will be disabled by default and is still provided by radeon. - Use module options to override this: + CIK is already supported in radeon. If you enable this option, + support for CIK will be provided by amdgpu and disabled in + radeon by default. Use module options to override this: - radeon.cik_support=0 amdgpu.cik_support=1 + radeon.cik_support=1 amdgpu.cik_support=0 config DRM_AMDGPU_USERPTR bool "Always enable userptr write support" diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 3c19d1ad22f82..aaf13c8dd70a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -633,14 +633,13 @@ module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); */ #ifdef CONFIG_DRM_AMDGPU_SI -#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) +#if (0 && (IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE))) int amdgpu_si_support; MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); #else int amdgpu_si_support = 1; MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); #endif - module_param_named(si_support, amdgpu_si_support, int, 0444); #endif @@ -652,14 +651,13 @@ module_param_named(si_support, amdgpu_si_support, int, 0444); */ #ifdef CONFIG_DRM_AMDGPU_CIK -#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) +#if (0 && (IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE))) int amdgpu_cik_support; MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); #else int amdgpu_cik_support = 1; MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); #endif - module_param_named(cik_support, amdgpu_cik_support, int, 0444); #endif From 6d7f2c34d7be2a126f4d5b8827ce02b6847c5224 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 23 Apr 2021 16:38:13 +0800 Subject: [PATCH 0250/2653] drm/amdgpu:[hybrid] unpin bo per exit Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index f0da588910ae2..6c3e950538382 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -197,6 +197,13 @@ static void amdgpu_gem_object_free(struct drm_gem_object *gobj) { struct amdgpu_bo *aobj = gem_to_amdgpu_bo(gobj); + if (aobj->flags & AMDGPU_GEM_CREATE_NO_EVICT) { + if (!amdgpu_bo_reserve(aobj, false)) { + amdgpu_bo_unpin(aobj); + amdgpu_bo_unreserve(aobj); + } + } + amdgpu_hmm_unregister(aobj); ttm_bo_put(&aobj->tbo); } From 501fea8deaeea4001e301be31fbcf6934026db74 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Thu, 30 Aug 2018 12:14:28 +0800 Subject: [PATCH 0251/2653] drm/amdgpu: [hybrid] add semaphore object support Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 8 + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 7 + drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c | 462 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h | 64 ++++ include/uapi/drm/amdgpu_drm.h | 37 ++ 11 files changed, 590 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 05130f47e5d1b..6a54652b95b05 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -60,7 +60,7 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \ amdgpu_gtt_mgr.o amdgpu_preempt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o \ amdgpu_atomfirmware.o amdgpu_vf_error.o amdgpu_sched.o \ amdgpu_debugfs.o amdgpu_ids.o amdgpu_gmc.o amdgpu_mmhub.o amdgpu_hdp.o \ - amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \ + amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o amdgpu_sem.o amdgpu_gmc.o \ amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \ amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \ amdgpu_fw_attestation.o amdgpu_securedisplay.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 520bf5bd925ce..a8ec2d19d1317 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -73,6 +73,7 @@ #include "amdgpu_sync.h" #include "amdgpu_ring.h" #include "amdgpu_vm.h" +#include "amdgpu_sem.h" #include "amdgpu_dpm.h" #include "amdgpu_acp.h" #include "amdgpu_uvd.h" @@ -507,6 +508,8 @@ struct amdgpu_fpriv { struct idr bo_list_handles; struct amdgpu_ctx_mgr ctx_mgr; struct amdgpu_userq_mgr userq_mgr; + spinlock_t sem_handles_lock; + struct idr sem_handles; /* Eviction fence infra */ struct amdgpu_eviction_fence_mgr evf_mgr; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 7af5277d85083..f2548e9619955 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -40,6 +40,7 @@ #include "amdgpu_gmc.h" #include "amdgpu_gem.h" #include "amdgpu_ras.h" +#include "amdgpu_display.h" static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, struct amdgpu_device *adev, @@ -616,7 +617,7 @@ static int amdgpu_cs_p2_shadow(struct amdgpu_cs_parser *p, static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) { unsigned int ce_preempt = 0, de_preempt = 0; - int i, r; + int i, r = 0; for (i = 0; i < p->nchunks; ++i) { struct amdgpu_cs_chunk *chunk; @@ -663,7 +664,7 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) } } - return 0; + return amdgpu_sem_add_cs(p->ctx, p->entity, &p->job->sync); } /* Convert microseconds to bytes. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index f5d5c45ddc0d1..fc623067e60ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -216,6 +216,8 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, GFP_KERNEL); if (!entity) return -ENOMEM; + INIT_LIST_HEAD(&entity->sem_dep_list); + mutex_init(&entity->sem_lock); ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? ctx->init_priority : ctx->override_priority; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h index 090dfe86f75ba..18e7d1f82d1d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h @@ -39,6 +39,8 @@ struct amdgpu_ctx_entity { uint32_t hw_ip; uint64_t sequence; struct drm_sched_entity entity; + struct list_head sem_dep_list; + struct mutex sem_lock; struct dma_fence *fences[]; }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index aaf13c8dd70a1..e15ecb9fdd249 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3053,6 +3053,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW) }; static const struct drm_driver amdgpu_kms_driver = { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 7d9bcb72e8dd3..85aad8a233f9a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -141,6 +141,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, unsigned int cond_exec; unsigned int i; int r = 0; + unsigned extra_nop = 0; if (num_ibs == 0) return -EINVAL; @@ -189,6 +190,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, alloc_size = ring->funcs->emit_frame_size + num_ibs * ring->funcs->emit_ib_size; + if (job && !job->vm_needs_flush && ring->funcs->type == AMDGPU_RING_TYPE_GFX) { + extra_nop = 128; + alloc_size += extra_nop; + } + r = amdgpu_ring_alloc(ring, alloc_size); if (r) { dev_err(adev->dev, "scheduling IB failed (%d).\n", r); @@ -219,6 +225,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, ring->funcs->insert_start(ring); if (job) { + amdgpu_ring_insert_nop(ring, extra_nop); /* prevent CE go too fast than DE */ + r = amdgpu_vm_flush(ring, job, need_pipe_sync); if (r) { amdgpu_ring_undo(ring); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 011c7b0110065..2c72c8869f85c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1473,6 +1473,8 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) mutex_init(&fpriv->bo_list_lock); idr_init_base(&fpriv->bo_list_handles, 1); + spin_lock_init(&fpriv->sem_handles_lock); + idr_init(&fpriv->sem_handles); r = amdgpu_userq_mgr_init(&fpriv->userq_mgr, file_priv, adev); if (r) @@ -1520,6 +1522,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv = file_priv->driver_priv; struct amdgpu_bo_list *list; + struct amdgpu_sem *sem; struct amdgpu_bo *pd; u32 pasid; int handle; @@ -1564,6 +1567,10 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, idr_destroy(&fpriv->bo_list_handles); mutex_destroy(&fpriv->bo_list_lock); + idr_for_each_entry(&fpriv->sem_handles, sem, handle) + amdgpu_sem_destroy(fpriv, handle); + idr_destroy(&fpriv->sem_handles); + kfree(fpriv); file_priv->driver_priv = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c new file mode 100644 index 0000000000000..432072b28f5ae --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c @@ -0,0 +1,462 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Chunming Zhou + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "amdgpu.h" +#include "amdgpu_sem.h" + +#define to_amdgpu_ctx_entity(e) \ + container_of((e), struct amdgpu_ctx_entity, entity) + +static int amdgpu_sem_entity_add(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in, + struct amdgpu_sem *sem); + +static void amdgpu_sem_core_free(struct kref *kref) +{ + struct amdgpu_sem_core *core = container_of( + kref, struct amdgpu_sem_core, kref); + + dma_fence_put(core->fence); + mutex_destroy(&core->lock); + kfree(core); +} + +static void amdgpu_sem_free(struct kref *kref) +{ + struct amdgpu_sem *sem = container_of( + kref, struct amdgpu_sem, kref); + + kref_put(&sem->base->kref, amdgpu_sem_core_free); + kfree(sem); +} + +static inline void amdgpu_sem_get(struct amdgpu_sem *sem) +{ + if (sem) + kref_get(&sem->kref); +} + +void amdgpu_sem_put(struct amdgpu_sem *sem) +{ + if (sem) + kref_put(&sem->kref, amdgpu_sem_free); +} + +static int amdgpu_sem_release(struct inode *inode, struct file *file) +{ + struct amdgpu_sem_core *core = file->private_data; + + /* set the core->file to null if file got released */ + mutex_lock(&core->lock); + core->file = NULL; + mutex_unlock(&core->lock); + + kref_put(&core->kref, amdgpu_sem_core_free); + return 0; +} + +static unsigned int amdgpu_sem_poll(struct file *file, poll_table *wait) +{ + return 0; +} + +static long amdgpu_sem_file_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + return 0; +} + +static const struct file_operations amdgpu_sem_fops = { + .release = amdgpu_sem_release, + .poll = amdgpu_sem_poll, + .unlocked_ioctl = amdgpu_sem_file_ioctl, + .compat_ioctl = amdgpu_sem_file_ioctl, +}; + + +static inline struct amdgpu_sem *amdgpu_sem_lookup(struct amdgpu_fpriv *fpriv, u32 handle) +{ + struct amdgpu_sem *sem; + + spin_lock(&fpriv->sem_handles_lock); + + /* Check if we currently have a reference on the object */ + sem = idr_find(&fpriv->sem_handles, handle); + amdgpu_sem_get(sem); + + spin_unlock(&fpriv->sem_handles_lock); + + return sem; +} + +static struct amdgpu_sem_core *amdgpu_sem_core_alloc(void) +{ + struct amdgpu_sem_core *core; + + core = kzalloc(sizeof(*core), GFP_KERNEL); + if (!core) + return NULL; + + kref_init(&core->kref); + mutex_init(&core->lock); + return core; +} + +static struct amdgpu_sem *amdgpu_sem_alloc(void) +{ + struct amdgpu_sem *sem; + + sem = kzalloc(sizeof(*sem), GFP_KERNEL); + if (!sem) + return NULL; + + kref_init(&sem->kref); + INIT_LIST_HEAD(&sem->list); + + return sem; +} + +static int amdgpu_sem_create(struct amdgpu_fpriv *fpriv, u32 *handle) +{ + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + int ret; + + sem = amdgpu_sem_alloc(); + core = amdgpu_sem_core_alloc(); + if (!sem || !core) { + kfree(sem); + kfree(core); + return -ENOMEM; + } + + sem->base = core; + + idr_preload(GFP_KERNEL); + spin_lock(&fpriv->sem_handles_lock); + + ret = idr_alloc(&fpriv->sem_handles, sem, 1, 0, GFP_NOWAIT); + + spin_unlock(&fpriv->sem_handles_lock); + idr_preload_end(); + + if (ret < 0) + return ret; + + *handle = ret; + return 0; +} + +static int amdgpu_sem_signal(struct amdgpu_fpriv *fpriv, + u32 handle, struct dma_fence *fence) +{ + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + + sem = amdgpu_sem_lookup(fpriv, handle); + if (!sem) + return -EINVAL; + + core = sem->base; + mutex_lock(&core->lock); + dma_fence_put(core->fence); + core->fence = dma_fence_get(fence); + mutex_unlock(&core->lock); + + amdgpu_sem_put(sem); + return 0; +} + +static int amdgpu_sem_wait(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in) +{ + struct amdgpu_sem *sem; + int ret; + + sem = amdgpu_sem_lookup(fpriv, in->handle); + if (!sem) + return -EINVAL; + + ret = amdgpu_sem_entity_add(fpriv, in, sem); + amdgpu_sem_put(sem); + + return ret; +} + +static int amdgpu_sem_import(struct amdgpu_fpriv *fpriv, + int fd, u32 *handle) +{ + struct file *file = fget(fd); + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + int ret; + + if (!file) + return -EINVAL; + + core = file->private_data; + if (!core) { + fput(file); + return -EINVAL; + } + + kref_get(&core->kref); + sem = amdgpu_sem_alloc(); + if (!sem) { + ret = -ENOMEM; + goto err_sem; + } + + sem->base = core; + + idr_preload(GFP_KERNEL); + spin_lock(&fpriv->sem_handles_lock); + + ret = idr_alloc(&fpriv->sem_handles, sem, 1, 0, GFP_NOWAIT); + + spin_unlock(&fpriv->sem_handles_lock); + idr_preload_end(); + + if (ret < 0) + goto err_out; + + *handle = ret; + fput(file); + return 0; +err_sem: + kref_put(&core->kref, amdgpu_sem_core_free); +err_out: + amdgpu_sem_put(sem); + fput(file); + return ret; + +} + +static int amdgpu_sem_export(struct amdgpu_fpriv *fpriv, + u32 handle, int *fd) +{ + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + int ret; + + sem = amdgpu_sem_lookup(fpriv, handle); + if (!sem) + return -EINVAL; + + core = sem->base; + kref_get(&core->kref); + mutex_lock(&core->lock); + if (!core->file) { + core->file = anon_inode_getfile("sem_file", + &amdgpu_sem_fops, + core, 0); + if (IS_ERR(core->file)) { + mutex_unlock(&core->lock); + ret = -ENOMEM; + goto err_put_sem; + } + } else { + get_file(core->file); + } + mutex_unlock(&core->lock); + + ret = get_unused_fd_flags(O_CLOEXEC); + if (ret < 0) + goto err_put_file; + + fd_install(ret, core->file); + + *fd = ret; + amdgpu_sem_put(sem); + + return 0; + +err_put_file: + fput(core->file); +err_put_sem: + kref_put(&core->kref, amdgpu_sem_core_free); + amdgpu_sem_put(sem); + return ret; +} + +void amdgpu_sem_destroy(struct amdgpu_fpriv *fpriv, u32 handle) +{ + struct amdgpu_sem *sem = amdgpu_sem_lookup(fpriv, handle); + if (!sem) + return; + + spin_lock(&fpriv->sem_handles_lock); + idr_remove(&fpriv->sem_handles, handle); + spin_unlock(&fpriv->sem_handles_lock); + + kref_put(&sem->kref, amdgpu_sem_free); + kref_put(&sem->kref, amdgpu_sem_free); +} + +static struct dma_fence *amdgpu_sem_get_fence(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in) +{ + struct drm_sched_entity *entity; + struct amdgpu_ctx *ctx; + struct dma_fence *fence; + uint32_t ctx_id, ip_type, ip_instance, ring; + int r; + + ctx_id = in->ctx_id; + ip_type = in->ip_type; + ip_instance = in->ip_instance; + ring = in->ring; + ctx = amdgpu_ctx_get(fpriv, ctx_id); + if (!ctx) + return NULL; + r = amdgpu_ctx_get_entity(ctx, ip_type, + ip_instance, ring, &entity); + if (r) { + amdgpu_ctx_put(ctx); + return NULL; + } + /* get the last fence of this entity */ + fence = amdgpu_ctx_get_fence(ctx, entity, in->seq); + amdgpu_ctx_put(ctx); + + return fence; +} + +static int amdgpu_sem_entity_add(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in, + struct amdgpu_sem *sem) +{ + struct amdgpu_ctx *ctx; + struct amdgpu_sem_dep *dep; + struct drm_sched_entity *entity; + struct amdgpu_ctx_entity *centity; + uint32_t ctx_id, ip_type, ip_instance, ring; + int r; + + ctx_id = in->ctx_id; + ip_type = in->ip_type; + ip_instance = in->ip_instance; + ring = in->ring; + ctx = amdgpu_ctx_get(fpriv, ctx_id); + if (!ctx) + return -EINVAL; + r = amdgpu_ctx_get_entity(ctx, ip_type, + ip_instance, ring, &entity); + if (r) + goto err; + + dep = kzalloc(sizeof(*dep), GFP_KERNEL); + if (!dep) + goto err; + + INIT_LIST_HEAD(&dep->list); + dep->fence = dma_fence_get(sem->base->fence); + + centity = to_amdgpu_ctx_entity(entity); + mutex_lock(¢ity->sem_lock); + list_add(&dep->list, ¢ity->sem_dep_list); + mutex_unlock(¢ity->sem_lock); + +err: + amdgpu_ctx_put(ctx); + return r; +} + +int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct drm_sched_entity *entity, + struct amdgpu_sync *sync) +{ + struct amdgpu_sem_dep *dep, *tmp; + struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); + int r = 0; + + if (list_empty(¢ity->sem_dep_list)) + return 0; + + mutex_lock(¢ity->sem_lock); + list_for_each_entry_safe(dep, tmp, ¢ity->sem_dep_list, + list) { + r = amdgpu_sync_fence(sync, dep->fence); + if (r) + goto err; + dma_fence_put(dep->fence); + list_del_init(&dep->list); + kfree(dep); + } +err: + mutex_unlock(¢ity->sem_lock); + return r; +} + +int amdgpu_sem_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + union drm_amdgpu_sem *args = data; + struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct dma_fence *fence; + int r = 0; + + switch (args->in.op) { + case AMDGPU_SEM_OP_CREATE_SEM: + r = amdgpu_sem_create(fpriv, &args->out.handle); + break; + case AMDGPU_SEM_OP_WAIT_SEM: + r = amdgpu_sem_wait(fpriv, &args->in); + break; + case AMDGPU_SEM_OP_SIGNAL_SEM: + fence = amdgpu_sem_get_fence(fpriv, &args->in); + if (IS_ERR(fence)) { + r = PTR_ERR(fence); + return r; + } + r = amdgpu_sem_signal(fpriv, args->in.handle, fence); + dma_fence_put(fence); + break; + case AMDGPU_SEM_OP_IMPORT_SEM: + r = amdgpu_sem_import(fpriv, args->in.handle, &args->out.handle); + break; + case AMDGPU_SEM_OP_EXPORT_SEM: + r = amdgpu_sem_export(fpriv, args->in.handle, &args->out.fd); + break; + case AMDGPU_SEM_OP_DESTROY_SEM: + amdgpu_sem_destroy(fpriv, args->in.handle); + break; + default: + r = -EINVAL; + break; + } + + return r; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h new file mode 100644 index 0000000000000..dbbb9d4540233 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h @@ -0,0 +1,64 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Chunming Zhou + * + */ + + +#ifndef _LINUX_AMDGPU_SEM_H +#define _LINUX_AMDGPU_SEM_H + +#include +#include +#include +#include +#include + +struct amdgpu_sem_core { + struct file *file; + struct kref kref; + struct dma_fence *fence; + struct mutex lock; +}; + +struct amdgpu_sem_dep { + struct dma_fence *fence; + struct list_head list; +}; + +struct amdgpu_sem { + struct amdgpu_sem_core *base; + struct kref kref; + struct list_head list; +}; + +void amdgpu_sem_put(struct amdgpu_sem *sem); + +int amdgpu_sem_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); + +int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct drm_sched_entity *entity, + struct amdgpu_sync *sync); + +void amdgpu_sem_destroy(struct amdgpu_fpriv *fpriv, u32 handle); + +#endif /* _LINUX_AMDGPU_SEM_H */ diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 824bc66e96843..cdcbb1d6ba3fd 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -58,6 +58,9 @@ extern "C" { #define DRM_AMDGPU_USERQ_SIGNAL 0x17 #define DRM_AMDGPU_USERQ_WAIT 0x18 +/* hybrid specific ioctls */ +#define DRM_AMDGPU_SEM 0x5b + #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) @@ -104,6 +107,9 @@ extern "C" { * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for * signalling user mode queues. */ +/* hybrid specific ioctls */ +#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem) + #define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 @@ -181,6 +187,8 @@ extern "C" { #define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16) /* hybrid specific */ +/* Flag that the memory should be in SPARSE resource */ +#define AMDGPU_GEM_CREATE_SPARSE (1ULL << 29) /* Flag that the memory allocation should be from top of domain */ #define AMDGPU_GEM_CREATE_TOP_DOWN (1ULL << 30) /* Flag that the memory allocation should be pinned */ @@ -585,6 +593,35 @@ struct drm_amdgpu_userq_wait { __u64 out_fences; }; +/* sem related */ +#define AMDGPU_SEM_OP_CREATE_SEM 1 +#define AMDGPU_SEM_OP_WAIT_SEM 2 +#define AMDGPU_SEM_OP_SIGNAL_SEM 3 +#define AMDGPU_SEM_OP_DESTROY_SEM 4 +#define AMDGPU_SEM_OP_IMPORT_SEM 5 +#define AMDGPU_SEM_OP_EXPORT_SEM 6 + +struct drm_amdgpu_sem_in { + /** AMDGPU_SEM_OP_* */ + uint32_t op; + uint32_t handle; + uint32_t ctx_id; + uint32_t ip_type; + uint32_t ip_instance; + uint32_t ring; + uint64_t seq; +}; + +union drm_amdgpu_sem_out { + int32_t fd; + uint32_t handle; +}; + +union drm_amdgpu_sem { + struct drm_amdgpu_sem_in in; + union drm_amdgpu_sem_out out; +}; + /* vm ioctl */ #define AMDGPU_VM_OP_RESERVE_VMID 1 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 From 89529dafc1dd8a5b7948639cf86dea6e1954171b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 21 Aug 2018 17:35:56 +0800 Subject: [PATCH 0252/2653] drm/amdgpu: [hybrid] add direct gma(dgma) support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit v2: rebase on linux 4.18 and cleanup v3: 3f8d459ca0f1("drm/amdgpu: [hybrid] fix DGMA buffer info loss issue (v2)") v4: 814cd038a6b5(drm/amdkcl: modify DGMA setting for new PL_DOORBELL support) Signed-off-by: Bob Zhou Reviewed-by: Flora Cui Reviewed-by: Guchun Chen Signed-off-by: Flora Cui Reviewed-by: Hawking Zhang Signed-off-by: Junwei Zhang (v2) Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui Signed-off-by: Tianci.Yin Acked-by: Christian König Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 15 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 + drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 86 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 28 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 9 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 325 ++++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 13 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 + include/drm/ttm/ttm_resource.h | 2 +- include/uapi/drm/amdgpu_drm.h | 24 +- 11 files changed, 505 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index a8ec2d19d1317..ec61a2c9ec60d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -192,6 +192,7 @@ extern int amdgpu_dc; extern int amdgpu_sched_jobs; extern int amdgpu_sched_hw_submission; extern int amdgpu_no_evict; +extern int amdgpu_direct_gma_size; extern uint amdgpu_pcie_gen_cap; extern uint amdgpu_pcie_lane_cap; extern u64 amdgpu_cg_mask; @@ -726,6 +727,9 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *fi int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); +int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); + /* VRAM scratch page for HDP bug, default vram page */ struct amdgpu_mem_scratch { struct amdgpu_bo *robj; @@ -816,6 +820,14 @@ enum amd_hw_ip_block_type { #define IP_VERSION_SUBREV(ver) ((ver) & 0xF) #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) +struct amdgpu_direct_gma { + /* reserved in visible vram*/ + struct amdgpu_bo *dgma_bo; + atomic64_t vram_usage; + /* reserved in gart */ + atomic64_t gart_usage; +}; + struct amdgpu_ip_map_info { /* Map of logical to actual dev instances/mask */ uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; @@ -984,6 +996,9 @@ struct amdgpu_device { uint32_t bios_scratch_reg_offset; uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; + /* Direct GMA */ + struct amdgpu_direct_gma direct_gma; + /* Register/doorbell mmio */ resource_size_t rmmio_base; resource_size_t rmmio_size; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 682b855d9f53a..9796415b58e3c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2148,6 +2148,7 @@ static int amdgpu_device_check_arguments(struct amdgpu_device *adev) amdgpu_device_check_block_size(adev); adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); + amdgpu_direct_gma_size = min(amdgpu_direct_gma_size, 96); for (i = 0; i < MAX_XCP; i++) { switch (amdgpu_enforce_isolation) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index e15ecb9fdd249..559000216598b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -176,6 +176,7 @@ int amdgpu_dc = -1; int amdgpu_sched_jobs = 32; int amdgpu_sched_hw_submission = 2; int amdgpu_no_evict; +int amdgpu_direct_gma_size; uint amdgpu_pcie_gen_cap; uint amdgpu_pcie_lane_cap; u64 amdgpu_cg_mask = 0xffffffffffffffff; @@ -507,6 +508,10 @@ module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); module_param_named(no_evict, amdgpu_no_evict, int, 0444); + +MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)"); +module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444); + /** * DOC: forcelongtraining (uint) * Force long memory training in resume. @@ -3053,6 +3058,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_DGMA, amdgpu_gem_dgma_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW) }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 6c3e950538382..c3d9a1b90afd0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -196,6 +196,7 @@ static const struct vm_operations_struct amdgpu_gem_vm_ops = { static void amdgpu_gem_object_free(struct drm_gem_object *gobj) { struct amdgpu_bo *aobj = gem_to_amdgpu_bo(gobj); + struct amdgpu_device *adev = amdgpu_ttm_adev(aobj->tbo.bdev); if (aobj->flags & AMDGPU_GEM_CREATE_NO_EVICT) { if (!amdgpu_bo_reserve(aobj, false)) { @@ -204,6 +205,13 @@ static void amdgpu_gem_object_free(struct drm_gem_object *gobj) } } + if (aobj->tbo.resource->mem_type == AMDGPU_PL_DGMA) + atomic64_sub(amdgpu_bo_size(aobj), + &adev->direct_gma.vram_usage); + else if (aobj->tbo.resource->mem_type == AMDGPU_PL_DGMA_IMPORT) + atomic64_sub(amdgpu_bo_size(aobj), + &adev->direct_gma.gart_usage); + amdgpu_hmm_unregister(aobj); ttm_bo_put(&aobj->tbo); } @@ -217,12 +225,30 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, struct amdgpu_bo *bo; struct amdgpu_bo_user *ubo; struct amdgpu_bo_param bp; + unsigned long max_size; int r; memset(&bp, 0, sizeof(bp)); *obj = NULL; flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; + if ((initial_domain & AMDGPU_GEM_DOMAIN_DGMA) || + (initial_domain & AMDGPU_GEM_DOMAIN_DGMA_IMPORT)) { + flags |= AMDGPU_GEM_CREATE_NO_EVICT; + max_size = (unsigned long)amdgpu_direct_gma_size << 20; + + if (initial_domain & AMDGPU_GEM_DOMAIN_DGMA) + max_size -= atomic64_read(&adev->direct_gma.vram_usage); + else if (initial_domain & AMDGPU_GEM_DOMAIN_DGMA_IMPORT) + max_size -= atomic64_read(&adev->direct_gma.gart_usage); + + if (size > max_size) { + DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n", + size >> 20, max_size >> 20); + return -ENOMEM; + } + } + bp.size = size; bp.byte_align = alignment; bp.type = type; @@ -240,6 +266,11 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, bo = &ubo->bo; *obj = &bo->tbo.base; + if (initial_domain & AMDGPU_GEM_DOMAIN_DGMA) + atomic64_add(size, &adev->direct_gma.vram_usage); + else if (initial_domain & AMDGPU_GEM_DOMAIN_DGMA_IMPORT) + atomic64_add(size, &adev->direct_gma.gart_usage); + return 0; } @@ -616,6 +647,61 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, return r; } +int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + struct amdgpu_device *adev = drm_to_adev(dev); + struct drm_amdgpu_gem_dgma *args = data; + struct drm_gem_object *gobj; + struct amdgpu_bo *abo; + dma_addr_t *dma_addr; + uint32_t handle; + int i, r = 0; + + switch (args->op) { + case AMDGPU_GEM_DGMA_IMPORT: + /* create a gem object to contain this object in */ + r = amdgpu_gem_object_create(adev, args->size, 0, + AMDGPU_GEM_DOMAIN_DGMA_IMPORT, 0, + 0, NULL, &gobj); + if (r) + return r; + + abo = gem_to_amdgpu_bo(gobj); + dma_addr = kmalloc_array(abo->tbo.resource->num_pages, sizeof(dma_addr_t), GFP_KERNEL); + if (unlikely(dma_addr == NULL)) + goto release_object; + + for (i = 0; i < abo->tbo.resource->num_pages; i++) + dma_addr[i] = args->addr + i * PAGE_SIZE; + abo->dgma_import_base = args->addr; + abo->dgma_addr = (void *)dma_addr; + r = drm_gem_handle_create(filp, gobj, &handle); + args->handle = handle; + break; + case AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR: + gobj = drm_gem_object_lookup(filp, args->handle); + if (gobj == NULL) + return -ENOENT; + + abo = gem_to_amdgpu_bo(gobj); + if (abo->tbo.resource->mem_type != AMDGPU_PL_DGMA) { + r = -EINVAL; + goto release_object; + } + args->addr = amdgpu_bo_gpu_offset(abo) - + amdgpu_ttm_domain_start(adev, TTM_PL_VRAM) + + adev->gmc.aper_base; + break; + default: + return -EINVAL; + } + +release_object: + drm_gem_object_put(gobj); + return r; +} + int amdgpu_mode_dumb_mmap(struct drm_file *filp, struct drm_device *dev, uint32_t handle, uint64_t *offset_p) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 33dfe413d9c88..75d25b90f1513 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -61,6 +61,8 @@ static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) { struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); + kfree(bo->dgma_addr); + amdgpu_bo_kunmap(bo); if (drm_gem_is_imported(&bo->tbo.base)) @@ -115,6 +117,22 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) u64 flags = abo->flags; u32 c = 0, i; + if ((domain & AMDGPU_GEM_DOMAIN_DGMA) && amdgpu_direct_gma_size) { + places[c].fpfn = 0; + places[c].lpfn = 0; + places[c].mem_type = AMDGPU_PL_DGMA; + places[c].flags = 0; + c++; + } + + if ((domain & AMDGPU_GEM_DOMAIN_DGMA_IMPORT) && amdgpu_direct_gma_size) { + places[c].fpfn = 0; + places[c].lpfn = 0; + places[c].mem_type = AMDGPU_PL_DGMA_IMPORT; + places[c].flags = 0; + c++; + } + if (domain & AMDGPU_GEM_DOMAIN_VRAM) { unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; int8_t mem_id = KFD_XCP_MEM_ID(adev, abo->xcp_id); @@ -738,7 +756,8 @@ int amdgpu_bo_create(struct amdgpu_device *adev, if (bp->type == ttm_bo_type_device) bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; - if ((bp->flags & AMDGPU_GEM_CREATE_NO_EVICT) && amdgpu_no_evict) { + if (((bp->flags & AMDGPU_GEM_CREATE_NO_EVICT) && amdgpu_no_evict) || + bp->domain & (AMDGPU_GEM_DOMAIN_DGMA | AMDGPU_GEM_DOMAIN_DGMA_IMPORT)) { r = amdgpu_bo_reserve(bo, false); if (unlikely(r != 0)) return r; @@ -1480,6 +1499,7 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); + WARN_ON_ONCE(bo->tbo.resource->mem_type == AMDGPU_PL_DGMA_IMPORT); return amdgpu_bo_gpu_offset_no_check(bo); } @@ -1625,6 +1645,12 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) else placement = "VRAM"; break; + case AMDGPU_PL_DGMA: + placement = "DGMA"; + break; + case AMDGPU_PL_DGMA_IMPORT: + placement = "DGMA_IMPORT"; + break; case TTM_PL_TT: placement = "GTT"; break; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 87523fcd43863..1b8685bf4ff05 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -117,6 +117,10 @@ struct amdgpu_bo { #endif struct kgd_mem *kfd_bo; + /* DGMA imported buffer info */ + void *dgma_addr; + phys_addr_t dgma_import_base; + /* * For GPUs with spatial partitioning, xcp partition number, -1 means * any partition. For other ASICs without spatial partition, always 0 @@ -131,7 +135,6 @@ struct amdgpu_bo_user { u64 metadata_flags; void *metadata; u32 metadata_size; - }; struct amdgpu_bo_vm { @@ -167,6 +170,10 @@ static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type) return AMDGPU_GEM_DOMAIN_OA; case AMDGPU_PL_DOORBELL: return AMDGPU_GEM_DOMAIN_DOORBELL; + case AMDGPU_PL_DGMA: + return AMDGPU_GEM_DOMAIN_DGMA; + case AMDGPU_PL_DGMA_IMPORT: + return AMDGPU_GEM_DOMAIN_DGMA_IMPORT; default: break; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 5d8dade52edf3..7f0a25ef8c300 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -65,6 +65,11 @@ MODULE_IMPORT_NS("DMA_BUF"); #define AMDGPU_TTM_VRAM_MAX_DW_READ ((size_t)128) +struct amdgpu_dgma_node { + struct ttm_buffer_object *tbo; + struct ttm_range_mgr_node base; +}; + static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, struct ttm_tt *ttm, struct ttm_resource *bo_mem); @@ -127,6 +132,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, return; case TTM_PL_VRAM: + case AMDGPU_PL_DGMA: if (!adev->mman.buffer_funcs_enabled) { /* Move to system memory */ amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); @@ -153,6 +159,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, } break; case TTM_PL_TT: + case AMDGPU_PL_DGMA_IMPORT: case AMDGPU_PL_PREEMPT: default: amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); @@ -505,6 +512,11 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, } abo = ttm_to_amdgpu_bo(bo); + + if (old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA || + old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA_IMPORT) + return -EINVAL; + adev = amdgpu_ttm_adev(bo->bdev); if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM && @@ -613,7 +625,10 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, case AMDGPU_PL_PREEMPT: break; case TTM_PL_VRAM: - mem->bus.offset = mem->start << PAGE_SHIFT; + case AMDGPU_PL_DGMA: + mem->bus.offset = (mem->start << PAGE_SHIFT) + + amdgpu_ttm_domain_start(adev, mem->mem_type) - + amdgpu_ttm_domain_start(adev, TTM_PL_VRAM); if (adev->mman.aper_base_kaddr && mem->placement & TTM_PL_FLAG_CONTIGUOUS) @@ -629,6 +644,19 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, mem->bus.is_iomem = true; mem->bus.caching = ttm_uncached; break; + case AMDGPU_PL_DGMA_IMPORT: + { + struct amdgpu_dgma_node *node; + struct amdgpu_bo *abo; + + node = container_of(mem, struct amdgpu_dgma_node, base.base); + abo = ttm_to_amdgpu_bo(node->tbo); + mem->bus.addr = abo->dgma_addr; + mem->bus.offset = abo->dgma_import_base; + mem->bus.is_iomem = true; + mem->bus.caching = ttm_write_combined; + break; + } default: return -EINVAL; } @@ -641,6 +669,10 @@ static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); struct amdgpu_res_cursor cursor; + if (bo->resource->mem_type == AMDGPU_PL_DGMA || + bo->resource->mem_type == AMDGPU_PL_DGMA_IMPORT) + return (bo->resource->bus.offset >> PAGE_SHIFT) + page_offset; + amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0, &cursor); @@ -666,6 +698,12 @@ uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) return adev->gmc.gart_start; case TTM_PL_VRAM: return adev->gmc.vram_start; + case AMDGPU_PL_DGMA: + if (adev->direct_gma.dgma_bo) + return amdgpu_bo_gpu_offset(adev->direct_gma.dgma_bo); + fallthrough; + case AMDGPU_PL_DGMA_IMPORT: + return 0; } return 0; @@ -1383,6 +1421,9 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, { uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); + if (mem && mem->mem_type == AMDGPU_PL_DGMA_IMPORT) + flags |= AMDGPU_PTE_SYSTEM; + flags |= adev->gart.gart_pte_flags; flags |= AMDGPU_PTE_READABLE; @@ -1806,6 +1847,252 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) return 0; } +static inline struct amdgpu_dgma_import_mgr *to_dgma_import_mgr(struct ttm_resource_manager *man) +{ + return container_of(man, struct amdgpu_dgma_import_mgr, manager); +} + +static const struct ttm_resource_manager_func amdgpu_dgma_import_mgr_func; +/** + * amdgpu_dgma_import_mgr_init - init DGMA_import manager and DRM MM + * + * @adev: amdgpu_device pointer + * @dgma_size: maximum size of DGMA + * + * Allocate and initialize the DGMA manager. + */ +static int amdgpu_dgma_import_mgr_init(struct amdgpu_device *adev, uint64_t p_size) +{ + struct amdgpu_dgma_import_mgr *mgr = &adev->mman.dgma_import_mgr; + struct ttm_resource_manager *man = &mgr->manager; + + man->func = &amdgpu_dgma_import_mgr_func; + + ttm_resource_manager_init(man, &adev->mman.bdev, p_size); + drm_mm_init(&mgr->mm, 0, p_size); + spin_lock_init(&mgr->lock); + atomic64_set(&mgr->available, p_size); + + ttm_set_driver_manager(&adev->mman.bdev, AMDGPU_PL_DGMA_IMPORT, man); + ttm_resource_manager_set_used(man, true); + return 0; +} + +/** + * amdgpu_dgma_import_mgr_fini - free and destroy DGMA import manager + * + * @adev: amdgpu_device pointer + * + * Destroy and free the DGMA import manager, returns -EBUSY if ranges are still + * allocated inside it. + */ +static void amdgpu_dgma_import_mgr_fini(struct amdgpu_device *adev) +{ + struct amdgpu_dgma_import_mgr *mgr = &adev->mman.dgma_import_mgr; + struct ttm_resource_manager *man = &mgr->manager; + int ret; + + ttm_resource_manager_set_used(man, false); + + ret = ttm_resource_manager_evict_all(&adev->mman.bdev, man); + if (ret) + return; + + spin_lock(&mgr->lock); + drm_mm_takedown(&mgr->mm); + spin_unlock(&mgr->lock); + ttm_resource_manager_cleanup(man); + ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, NULL); +} + +/** + * amdgpu_dgma_import_mgr_new - allocate a new node + * + * @man: TTM memory type manager + * @tbo: TTM BO we need this range for + * @place: placement flags and restrictions + * @mem: the resulting mem object + */ +static int amdgpu_dgma_import_mgr_new(struct ttm_resource_manager *man, + struct ttm_buffer_object *tbo, + const struct ttm_place *place, + struct ttm_resource **res) +{ + struct amdgpu_dgma_import_mgr *mgr = to_dgma_import_mgr(man); + uint32_t num_pages = PFN_UP(tbo->base.size); + struct amdgpu_dgma_node *node; + unsigned long lpfn; + int r; + + spin_lock(&mgr->lock); + if (atomic64_read(&mgr->available) < num_pages) { + spin_unlock(&mgr->lock); + return -ENOSPC; + } + atomic64_sub(num_pages, &mgr->available); + spin_unlock(&mgr->lock); + + lpfn = place->lpfn; + if (!lpfn) + lpfn = man->size; + + node = kzalloc(struct_size(node, base.mm_nodes, 1), GFP_KERNEL); + if (!node) { + r = -ENOMEM; + goto err_out; + } + + node->tbo = tbo; + ttm_resource_init(tbo, place, &node->base.base); + + spin_lock(&mgr->lock); + r = drm_mm_insert_node_in_range(&mgr->mm, &node->base.mm_nodes[0], num_pages, + tbo->page_alignment, 0, place->fpfn, + lpfn, DRM_MM_INSERT_BEST); + spin_unlock(&mgr->lock); + + if (unlikely(r)) + goto err_free; + + *res = &node->base.base; + (*res)->start = node->base.mm_nodes[0].start; + + return 0; + +err_free: + kfree(node); + +err_out: + atomic64_add(num_pages, &mgr->available); + + return r; +} + +/** + * amdgpu_dgma_import_mgr_del - free ranges + * + * @man: TTM memory type manager + * @mem: TTM memory object + * + * Free the allocated node. + */ +static void amdgpu_dgma_import_mgr_del(struct ttm_resource_manager *man, + struct ttm_resource *mem) +{ + struct amdgpu_dgma_import_mgr *mgr = to_dgma_import_mgr(man); + struct amdgpu_dgma_node *node = container_of(mem, struct amdgpu_dgma_node, base.base); + + if (node) { + spin_lock(&mgr->lock); + drm_mm_remove_node(&node->base.mm_nodes[0]); + spin_unlock(&mgr->lock); + kfree(node); + } + + atomic64_add(mem->num_pages, &mgr->available); +} + +static void amdgpu_dgma_import_mgr_debug(struct ttm_resource_manager *man, + struct drm_printer *printer) +{ + struct amdgpu_dgma_import_mgr *rman = to_dgma_import_mgr(man); + + spin_lock(&rman->lock); + drm_mm_print(&rman->mm, printer); + spin_unlock(&rman->lock); +} + +static const struct ttm_resource_manager_func amdgpu_dgma_import_mgr_func = { + .alloc = amdgpu_dgma_import_mgr_new, + .free = amdgpu_dgma_import_mgr_del, + .debug = amdgpu_dgma_import_mgr_debug +}; + +static int amdgpu_direct_gma_init(struct amdgpu_device *adev) +{ + struct amdgpu_bo *abo; + struct amdgpu_bo_param bp; + unsigned long size; + int r; + + if (amdgpu_direct_gma_size == 0) + return 0; + + size = (unsigned long)amdgpu_direct_gma_size << 20; + + memset(&bp, 0, sizeof(bp)); + bp.size = size; + bp.byte_align = PAGE_SIZE; + bp.domain = AMDGPU_GEM_DOMAIN_VRAM; + bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_TOP_DOWN; + bp.type = ttm_bo_type_kernel; + bp.resv = NULL; + + /* reserve in visible vram */ + r = amdgpu_bo_create(adev, &bp, &abo); + if (unlikely(r)) + goto error_out; + + r = amdgpu_bo_reserve(abo, false); + if (unlikely(r)) + goto error_free; + + r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); + amdgpu_bo_unreserve(abo); + if (unlikely(r)) + goto error_free; + + adev->direct_gma.dgma_bo = abo; + + /* reserve in gtt */ + atomic64_add(size, &adev->gart_pin_size); + r = ttm_range_man_init(&adev->mman.bdev, AMDGPU_PL_DGMA, + false, size >> PAGE_SHIFT); + if (unlikely(r)) + goto error_put_node; + + r = amdgpu_dgma_import_mgr_init(adev, size >> PAGE_SHIFT); + if (unlikely(r)) + goto error_release_mm; + + DRM_INFO("%dMB VRAM/GTT reserved for Direct GMA\n", amdgpu_direct_gma_size); + return 0; + +error_release_mm: + ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DGMA); + +error_put_node: + atomic64_sub(size, &adev->gart_pin_size); +error_free: + amdgpu_bo_unref(&abo); + +error_out: + amdgpu_direct_gma_size = 0; + memset(&adev->direct_gma, 0, sizeof(adev->direct_gma)); + DRM_ERROR("Fail to enable Direct GMA\n"); + return r; +} + +static void amdgpu_direct_gma_fini(struct amdgpu_device *adev) +{ + int r; + + if (amdgpu_direct_gma_size == 0) + return; + + ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DGMA); + amdgpu_dgma_import_mgr_fini(adev); + + r = amdgpu_bo_reserve(adev->direct_gma.dgma_bo, false); + if (r == 0) { + amdgpu_bo_unpin(adev->direct_gma.dgma_bo); + amdgpu_bo_unreserve(adev->direct_gma.dgma_bo); + } + amdgpu_bo_unref(&adev->direct_gma.dgma_bo); + atomic64_sub((u64)amdgpu_direct_gma_size << 20, &adev->gart_pin_size); +} + static int amdgpu_ttm_pools_init(struct amdgpu_device *adev) { int i; @@ -1979,6 +2266,8 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) gtt_size = configured_size; } + /* reserve for DGMA import domain */ + gtt_size -= (uint64_t)amdgpu_direct_gma_size << 20; /* Initialize GTT memory pool */ r = amdgpu_gtt_mgr_init(adev, gtt_size); @@ -1989,6 +2278,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) dev_info(adev->dev, "amdgpu: %uM of GTT memory ready.\n", (unsigned int)(gtt_size / (1024 * 1024))); + amdgpu_direct_gma_init(adev); if (adev->flags & AMD_IS_APU) { if (adev->gmc.real_vram_size < gtt_size) adev->apu_prefer_gtt = true; @@ -2082,6 +2372,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) drm_dev_exit(idx); } + amdgpu_direct_gma_fini(adev); amdgpu_vram_mgr_fini(adev); amdgpu_gtt_mgr_fini(adev); amdgpu_preempt_mgr_fini(adev); @@ -2440,7 +2731,32 @@ static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) return ttm_pool_debugfs(&adev->mman.bdev.pool, m); } +static int amdgpu_mm_dgma_table_show(struct seq_file *m, void *unused) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, + AMDGPU_PL_DGMA); + struct drm_printer p = drm_seq_file_printer(m); + + man->func->debug(man, &p); + return 0; +} + +static int amdgpu_mm_dgma_import_table_show(struct seq_file *m, void *unused) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, + AMDGPU_PL_DGMA_IMPORT); + struct drm_printer p = drm_seq_file_printer(m); + + man->func->debug(man, &p); + return 0; +} + DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); +DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_dgma_table); +DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_dgma_import_table); + /* * amdgpu_ttm_vram_read - Linear read access to VRAM @@ -2651,6 +2967,7 @@ void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) &amdgpu_ttm_iomem_fops); debugfs_create_file("ttm_page_pool", 0444, root, adev, &amdgpu_ttm_page_pool_fops); + ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM), root, "amdgpu_vram_mm"); @@ -2667,5 +2984,11 @@ void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) AMDGPU_PL_OA), root, "amdgpu_oa_mm"); + if (amdgpu_direct_gma_size) { + debugfs_create_file("amdgpu_dgma_mm", 0444, root, adev, + &amdgpu_mm_dgma_table_fops); + debugfs_create_file("amdgpu_dgma_import_mm", 0444, root, adev, + &amdgpu_mm_dgma_import_table_fops); + } #endif } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 2309df3f68a9c..188b0c31e51ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -34,7 +34,10 @@ #define AMDGPU_PL_OA (TTM_PL_PRIV + 2) #define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3) #define AMDGPU_PL_DOORBELL (TTM_PL_PRIV + 4) -#define __AMDGPU_PL_NUM (TTM_PL_PRIV + 5) +#define __AMDGPU_PL_LAST (TTM_PL_PRIV + 4) +#define __AMDGPU_PL_NUM (TTM_PL_PRIV + 5) +#define AMDGPU_PL_DGMA (TTM_PL_PRIV + 7) +#define AMDGPU_PL_DGMA_IMPORT (TTM_PL_PRIV + 8) #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2 @@ -50,6 +53,13 @@ struct amdgpu_gtt_mgr { spinlock_t lock; }; +struct amdgpu_dgma_import_mgr { + struct ttm_resource_manager manager; + struct drm_mm mm; + spinlock_t lock; + atomic64_t available; +}; + struct amdgpu_mman { struct ttm_device bdev; struct ttm_pool *ttm_pools; @@ -69,6 +79,7 @@ struct amdgpu_mman { struct amdgpu_vram_mgr vram_mgr; struct amdgpu_gtt_mgr gtt_mgr; + struct amdgpu_dgma_import_mgr dgma_import_mgr; struct ttm_resource_manager preempt_mgr; uint64_t stolen_vga_size; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index ab12fe26b854b..aaf32d03ecd62 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1149,6 +1149,7 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, uint64_t tmp, num_entries, addr; num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT; + if (pages_addr) { bool contiguous = true; @@ -1288,6 +1289,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, if (mem && (mem->mem_type == TTM_PL_TT || mem->mem_type == AMDGPU_PL_PREEMPT)) pages_addr = bo->tbo.ttm->dma_address; + else if (mem->mem_type == AMDGPU_PL_DGMA_IMPORT) + pages_addr = (dma_addr_t *)bo->tbo.mem.bus.addr; /* Implicitly sync to moving fences before mapping anything */ r = amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv, diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h index e52bba15012f7..b873be9597e2e 100644 --- a/include/drm/ttm/ttm_resource.h +++ b/include/drm/ttm/ttm_resource.h @@ -36,7 +36,7 @@ #include #define TTM_MAX_BO_PRIORITY 4U -#define TTM_NUM_MEM_TYPES 8 +#define TTM_NUM_MEM_TYPES 12 struct dmem_cgroup_device; struct ttm_device; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index cdcbb1d6ba3fd..99638a56e7d92 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -57,6 +57,8 @@ extern "C" { #define DRM_AMDGPU_USERQ 0x16 #define DRM_AMDGPU_USERQ_SIGNAL 0x17 #define DRM_AMDGPU_USERQ_WAIT 0x18 +/* not upstream */ +#define DRM_AMDGPU_GEM_DGMA 0x5c /* hybrid specific ioctls */ #define DRM_AMDGPU_SEM 0x5b @@ -81,6 +83,8 @@ extern "C" { #define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal) #define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait) +#define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma) + /** * DOC: memory domains * @@ -117,13 +121,17 @@ extern "C" { #define AMDGPU_GEM_DOMAIN_GWS 0x10 #define AMDGPU_GEM_DOMAIN_OA 0x20 #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 +#define AMDGPU_GEM_DOMAIN_DGMA 0x400 +#define AMDGPU_GEM_DOMAIN_DGMA_IMPORT 0x800 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ AMDGPU_GEM_DOMAIN_GTT | \ AMDGPU_GEM_DOMAIN_VRAM | \ AMDGPU_GEM_DOMAIN_GDS | \ AMDGPU_GEM_DOMAIN_GWS | \ - AMDGPU_GEM_DOMAIN_OA | \ - AMDGPU_GEM_DOMAIN_DOORBELL) + AMDGPU_GEM_DOMAIN_OA |\ + AMDGPU_GEM_DOMAIN_DOORBELL |\ + AMDGPU_GEM_DOMAIN_DGMA |\ + AMDGPU_GEM_DOMAIN_DGMA_IMPORT) /* Flag that CPU access will be required for the case of VRAM domain */ #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) @@ -678,6 +686,15 @@ struct drm_amdgpu_gem_userptr { __u32 handle; }; +#define AMDGPU_GEM_DGMA_IMPORT 0 +#define AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR 1 +struct drm_amdgpu_gem_dgma { + __u64 addr; + __u64 size; + __u32 op; + __u32 handle; +}; + /* SI-CI-VI: */ /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 @@ -1266,6 +1283,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { #define AMDGPU_INFO_VIRTUAL_RANGE 0x51 /* query pin memory capability */ #define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) +/* query direct gma capability */ +#define AMDGPU_CAPABILITY_DIRECT_GMA_FLAG (1 << 1) #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff @@ -1696,6 +1715,7 @@ struct drm_amdgpu_virtual_range { struct drm_amdgpu_capability { __u32 flag; + __u32 direct_gma_size; }; /* From f7aa6fd0fc81495feed37d50ce7288c8433e7f0e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 16 Apr 2021 11:17:58 +0800 Subject: [PATCH 0253/2653] drm/amdgpu: [hybrid] fix bo_ptr_size for dgma Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 7f0a25ef8c300..8a0469a8b4c00 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2028,6 +2028,7 @@ static int amdgpu_direct_gma_init(struct amdgpu_device *adev) AMDGPU_GEM_CREATE_TOP_DOWN; bp.type = ttm_bo_type_kernel; bp.resv = NULL; + bp.bo_ptr_size = sizeof(struct amdgpu_bo); /* reserve in visible vram */ r = amdgpu_bo_create(adev, &bp, &abo); From 352d1926c897288f76f88893214232d52ea9d026 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 16 Apr 2021 15:51:05 +0800 Subject: [PATCH 0254/2653] drm/amdgpu: [hybrid] fix gpu mapping for dgma Signed-off-by: Flora Cui Signed-off-by: xinhui pan Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index aaf32d03ecd62..8f9eaf4e9617c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1290,7 +1290,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, mem->mem_type == AMDGPU_PL_PREEMPT)) pages_addr = bo->tbo.ttm->dma_address; else if (mem->mem_type == AMDGPU_PL_DGMA_IMPORT) - pages_addr = (dma_addr_t *)bo->tbo.mem.bus.addr; + pages_addr = (dma_addr_t *)bo->dgma_addr; /* Implicitly sync to moving fences before mapping anything */ r = amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv, From de7f6cacced3e9e9fd6169847bea46748a38bb4c Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Fri, 17 Sep 2021 11:43:13 +0800 Subject: [PATCH 0255/2653] drm/amdgpu: [hybrid]enable dGMA path in page table mapping Signed-off-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 69 +++++++++++++++----------- 1 file changed, 41 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 8f9eaf4e9617c..72c0b696c389e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1150,45 +1150,58 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT; - if (pages_addr) { - bool contiguous = true; + if (res && (res->mem_type == AMDGPU_PL_DGMA_IMPORT || + res->mem_type == AMDGPU_PL_DGMA)) { + uint64_t pfn = offset >> PAGE_SHIFT; - if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) { - uint64_t pfn = cursor.start >> PAGE_SHIFT; - uint64_t count; + if (res->mem_type == AMDGPU_PL_DGMA_IMPORT) { + addr = 0; + } else { + addr = pfn << PAGE_SHIFT; + addr += vram_base + + cursor.start + amdgpu_ttm_domain_start(adev, res->mem_type) - + amdgpu_ttm_domain_start(adev, TTM_PL_VRAM); + params.pages_addr = NULL; + } + } else { + if (pages_addr) { + bool contiguous = true; - contiguous = pages_addr[pfn + 1] == - pages_addr[pfn] + PAGE_SIZE; + if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) { + uint64_t pfn = cursor.start >> PAGE_SHIFT; + uint64_t count; - tmp = num_entries / - AMDGPU_GPU_PAGES_IN_CPU_PAGE; - for (count = 2; count < tmp; ++count) { - uint64_t idx = pfn + count; + contiguous = pages_addr[pfn + 1] == + pages_addr[pfn] + PAGE_SIZE; + + tmp = num_entries / + AMDGPU_GPU_PAGES_IN_CPU_PAGE; + for (count = 2; count < tmp; ++count) { + uint64_t idx = pfn + count; if (contiguous != (pages_addr[idx] == - pages_addr[idx - 1] + PAGE_SIZE)) + pages_addr[idx - 1] + PAGE_SIZE)) break; - } - if (!contiguous) + } + if (!contiguous) count--; - num_entries = count * - AMDGPU_GPU_PAGES_IN_CPU_PAGE; - } + num_entries = count * + AMDGPU_GPU_PAGES_IN_CPU_PAGE; + } - if (!contiguous) { - addr = cursor.start; - params.pages_addr = pages_addr; + if (!contiguous) { + addr = cursor.start; + params.pages_addr = pages_addr; + } else { + addr = pages_addr[cursor.start >> PAGE_SHIFT]; + params.pages_addr = NULL; + } + } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT_FLAG(adev))) { + addr = vram_base + cursor.start; } else { - addr = pages_addr[cursor.start >> PAGE_SHIFT]; - params.pages_addr = NULL; + addr = 0; } - - } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT_FLAG(adev))) { - addr = vram_base + cursor.start; - } else { - addr = 0; } - tmp = start + num_entries; r = amdgpu_vm_ptes_update(¶ms, start, tmp, addr, flags); if (r) From 4cec809667e2a6a76785a1dad7e30b2047934d41 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 22 Apr 2020 22:53:31 -0400 Subject: [PATCH 0256/2653] drm/amdgpu: Add PCIe P2P support Allow mapping remote GPU memory in GPUVM for large-BAR GPUs with the BAR within the GPU physical address range. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 983a1a994ba6b..3b1240271410b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -42,6 +42,7 @@ */ uint64_t amdgpu_amdkfd_total_mem_size; +extern bool pcie_p2p; static bool kfd_initialized; int amdgpu_amdkfd_init(void) From a80cdc074c303b77651a4f45826d2208ff88e158 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 00:11:19 -0400 Subject: [PATCH 0257/2653] drm/amdkfd: Add IPC API This allows exporting and importing buffers. The API generates handles that can be used with the HIP IPC API, i.e. big numbers rather than file descriptors. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 3 + .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 32 ++- drivers/gpu/drm/amd/amdkfd/Makefile | 1 + drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 73 ++++- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 270 ++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 51 ++++ drivers/gpu/drm/amd/amdkfd/kfd_module.c | 5 + drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 28 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 106 ++++++- include/uapi/linux/kfd_ioctl.h | 22 ++ 10 files changed, 566 insertions(+), 25 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_ipc.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_ipc.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 33eb4826b58b1..1e600a5cb3c91 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -333,6 +333,9 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, uint64_t *mmap_offset); int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, struct dma_buf **dmabuf); +int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_dev *kgd, void *vm, + struct kgd_mem *mem, + struct dma_buf **dmabuf); void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev); int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 5a1f2e1df5c9a..1a701ac055c16 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2347,12 +2347,14 @@ static int import_obj_create(struct amdgpu_device *adev, INIT_LIST_HEAD(&(*mem)->attachments); mutex_init(&(*mem)->lock); - - (*mem)->alloc_flags = - ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? - KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT) - | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE - | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE; + if (bo->kfd_bo) + (*mem)->alloc_flags = bo->kfd_bo->alloc_flags; + else + (*mem)->alloc_flags = + ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? + KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT) + | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE + | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE; get_dma_buf(dma_buf); (*mem)->dmabuf = dma_buf; @@ -2439,6 +2441,24 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, return ret; } +int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_dev *kgd, void *vm, + struct kgd_mem *mem, + struct dma_buf **dmabuf) +{ + struct amdgpu_device *adev = NULL; + + if (!dmabuf || !kgd || !vm || !mem) + return -EINVAL; + + adev = get_amdgpu_device(kgd); + + *dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base, 0); + if (IS_ERR(*dmabuf)) + return -EINVAL; + + return 0; +} + /* Evict a userptr BO by stopping the queues if necessary * * Runs in MMU notifier, may be in RECLAIM_FS context. This means it diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 0ce08113c9f0b..0d690dd859f96 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -58,6 +58,7 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_int_process_v11.o \ $(AMDKFD_PATH)/kfd_smi_events.o \ $(AMDKFD_PATH)/kfd_crat.o \ + $(AMDKFD_PATH)/kfd_ipc.o \ $(AMDKFD_PATH)/kfd_debug.o ifneq ($(CONFIG_DEBUG_FS),) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 828a9ceef1e76..e277aba3007d6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -39,6 +39,7 @@ #include "kfd_priv.h" #include "kfd_device_queue_manager.h" #include "kfd_svm.h" +#include "kfd_ipc.h" #include "amdgpu_amdkfd.h" #include "kfd_smi_events.h" #include "amdgpu_dma_buf.h" @@ -1059,6 +1060,8 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, long err; uint64_t offset = args->mmap_offset; uint32_t flags = args->flags; + uint64_t cpuva = 0; + unsigned int mem_type = 0; if (args->size == 0) return -EINVAL; @@ -1147,7 +1150,13 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, if (err) goto err_unlock; - idr_handle = kfd_process_device_create_obj_handle(pdd, mem); + mem_type = flags & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | + KFD_IOC_ALLOC_MEM_FLAGS_GTT | + KFD_IOC_ALLOC_MEM_FLAGS_USERPTR | + KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | + KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); + idr_handle = kfd_process_device_create_obj_handle(pdd, mem, + args->va_addr, args->size, cpuva, mem_type, NULL); if (idr_handle < 0) { err = -EFAULT; goto err_free; @@ -1191,7 +1200,8 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, { struct kfd_ioctl_free_memory_of_gpu_args *args = data; struct kfd_process_device *pdd; - void *mem; + struct kfd_bo *buf_obj; + struct kfd_dev *dev; int ret; uint64_t size = 0; @@ -1213,15 +1223,15 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, goto err_pdd; } - mem = kfd_process_device_translate_handle( - pdd, GET_IDR_HANDLE(args->handle)); - if (!mem) { + buf_obj = kfd_process_device_find_bo(pdd, + GET_IDR_HANDLE(args->handle)); + if (!buf_obj) { ret = -EINVAL; goto err_unlock; } ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, - (struct kgd_mem *)mem, pdd->drm_priv, &size); + buf_obj->mem, pdd->drm_priv, &size); /* If freeing the buffer failed, leave the handle in place for * clean-up during process tear-down. @@ -1585,7 +1595,8 @@ static int kfd_ioctl_import_dmabuf(struct file *filep, if (r) goto err_unlock; - idr_handle = kfd_process_device_create_obj_handle(pdd, mem); + idr_handle = kfd_process_device_create_obj_handle(pdd, mem, + args->va_addr, size, 0, 0, -1); if (idr_handle < 0) { r = -EFAULT; goto err_free; @@ -1599,12 +1610,52 @@ static int kfd_ioctl_import_dmabuf(struct file *filep, err_free: amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem, - pdd->drm_priv, NULL); + pdd->drm_priv, NULL); err_unlock: mutex_unlock(&p->mutex); return r; } +static int kfd_ioctl_ipc_export_handle(struct file *filep, + struct kfd_process *p, + void *data) +{ + struct kfd_ioctl_ipc_export_handle_args *args = data; + struct kfd_dev *dev; + int r; + + dev = kfd_device_by_id(args->gpu_id); + if (!dev) + return -EINVAL; + + r = kfd_ipc_export_as_handle(dev, p, args->handle, args->share_handle); + if (r) + pr_err("Failed to export IPC handle\n"); + + return r; +} + +static int kfd_ioctl_ipc_import_handle(struct file *filep, + struct kfd_process *p, + void *data) +{ + struct kfd_ioctl_ipc_import_handle_args *args = data; + struct kfd_dev *dev = NULL; + int r; + + dev = kfd_device_by_id(args->gpu_id); + if (!dev) + return -EINVAL; + + r = kfd_ipc_import_handle(dev, p, args->gpu_id, args->share_handle, + args->va_addr, &args->handle, + &args->mmap_offset); + if (r) + pr_err("Failed to import IPC handle\n"); + + return r; +} + static int kfd_ioctl_export_dmabuf(struct file *filep, struct kfd_process *p, void *data) { @@ -3236,6 +3287,12 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP, kfd_ioctl_set_debug_trap, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_IPC_IMPORT_HANDLE, + kfd_ioctl_ipc_import_handle, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_IPC_EXPORT_HANDLE, + kfd_ioctl_ipc_export_handle, 0), }; #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c new file mode 100644 index 0000000000000..51395a88c12a8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -0,0 +1,270 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "kfd_ipc.h" +#include "kfd_priv.h" +#include "amdgpu_amdkfd.h" + +#define KFD_IPC_HASH_TABLE_SIZE_SHIFT 4 +#define KFD_IPC_HASH_TABLE_SIZE_MASK ((1 << KFD_IPC_HASH_TABLE_SIZE_SHIFT) - 1) + +static struct kfd_ipc_handles { + DECLARE_HASHTABLE(handles, KFD_IPC_HASH_TABLE_SIZE_SHIFT); + struct mutex lock; +} kfd_ipc_handles; + +/* Since, handles are random numbers, it can be used directly as hashing key. + * The least 4 bits of the handle are used as key. However, during import all + * 128 bits of the handle are checked to prevent handle snooping. + */ +#define HANDLE_TO_KEY(sh) ((*(uint64_t *)sh) & KFD_IPC_HASH_TABLE_SIZE_MASK) + +static int ipc_store_insert(void *val, void *sh, struct kfd_ipc_obj **ipc_obj) +{ + struct kfd_ipc_obj *obj; + + obj = kmalloc(sizeof(*obj), GFP_KERNEL); + if (!obj) + return -ENOMEM; + + /* The initial ref belongs to the allocator process. + * The IPC object store itself does not hold a ref since + * there is no specific moment in time where that ref should + * be dropped, except "when there are no more userspace processes + * holding a ref to the object". Therefore the removal from IPC + * storage happens at ipc_obj release time. + */ + kref_init(&obj->ref); + obj->data = val; + get_random_bytes(obj->share_handle, sizeof(obj->share_handle)); + + memcpy(sh, obj->share_handle, sizeof(obj->share_handle)); + + mutex_lock(&kfd_ipc_handles.lock); + hlist_add_head(&obj->node, + &kfd_ipc_handles.handles[HANDLE_TO_KEY(obj->share_handle)]); + mutex_unlock(&kfd_ipc_handles.lock); + + if (ipc_obj) + *ipc_obj = obj; + + return 0; +} + +static void ipc_obj_release(struct kref *r) +{ + struct kfd_ipc_obj *obj; + + obj = container_of(r, struct kfd_ipc_obj, ref); + + mutex_lock(&kfd_ipc_handles.lock); + hash_del(&obj->node); + mutex_unlock(&kfd_ipc_handles.lock); + + dma_buf_put(obj->data); + kfree(obj); +} + +void ipc_obj_get(struct kfd_ipc_obj *obj) +{ + kref_get(&obj->ref); +} + +void ipc_obj_put(struct kfd_ipc_obj **obj) +{ + kref_put(&(*obj)->ref, ipc_obj_release); + *obj = NULL; +} + +int kfd_ipc_init(void) +{ + mutex_init(&kfd_ipc_handles.lock); + hash_init(kfd_ipc_handles.handles); + return 0; +} + +static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, + struct kfd_process *p, + uint32_t gpu_id, struct dma_buf *dmabuf, + uint64_t va_addr, uint64_t *handle, + uint64_t *mmap_offset, + struct kfd_ipc_obj *ipc_obj) +{ + int r; + void *mem; + uint64_t size; + int idr_handle; + struct kfd_process_device *pdd = NULL; + + if (!handle) + return -EINVAL; + + if (!dev) + return -EINVAL; + + mutex_lock(&p->mutex); + + pdd = kfd_bind_process_to_device(dev, p); + if (IS_ERR(pdd)) { + r = PTR_ERR(pdd); + goto err_unlock; + } + + r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf, + va_addr, pdd->vm, + (struct kgd_mem **)&mem, &size, + mmap_offset); + if (r) + goto err_unlock; + + idr_handle = kfd_process_device_create_obj_handle(pdd, mem, + va_addr, size, 0, 0, + ipc_obj); + if (idr_handle < 0) { + r = -EFAULT; + goto err_free; + } + + mutex_unlock(&p->mutex); + + *handle = MAKE_HANDLE(gpu_id, idr_handle); + + return 0; + +err_free: + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem, NULL); +err_unlock: + mutex_unlock(&p->mutex); + return r; +} + +int kfd_ipc_import_dmabuf(struct kfd_dev *dev, + struct kfd_process *p, + uint32_t gpu_id, int dmabuf_fd, + uint64_t va_addr, uint64_t *handle, + uint64_t *mmap_offset) +{ + int r; + struct dma_buf *dmabuf = dma_buf_get(dmabuf_fd); + + if (!dmabuf) + return -EINVAL; + + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, dmabuf, + va_addr, handle, mmap_offset, + NULL); + dma_buf_put(dmabuf); + return r; +} + +int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, + uint32_t gpu_id, uint32_t *share_handle, + uint64_t va_addr, uint64_t *handle, + uint64_t *mmap_offset) +{ + int r; + struct kfd_ipc_obj *entry, *found = NULL; + + mutex_lock(&kfd_ipc_handles.lock); + /* Convert the user provided handle to hash key and search only in that + * bucket + */ + hlist_for_each_entry(entry, + &kfd_ipc_handles.handles[HANDLE_TO_KEY(share_handle)], node) { + if (!memcmp(entry->share_handle, share_handle, + sizeof(entry->share_handle))) { + found = entry; + break; + } + } + mutex_unlock(&kfd_ipc_handles.lock); + + if (!found) + return -EINVAL; + ipc_obj_get(found); + + pr_debug("Found ipc_dma_buf: %p\n", found->data); + + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, found->data, + va_addr, handle, mmap_offset, + found); + if (r) + goto error_unref; + + return r; + +error_unref: + ipc_obj_put(&found); + return r; +} + +int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, + uint64_t handle, uint32_t *ipc_handle) +{ + struct kfd_process_device *pdd = NULL; + struct kfd_ipc_obj *obj; + struct kfd_bo *kfd_bo = NULL; + struct dma_buf *dmabuf; + int r; + + if (!dev || !ipc_handle) + return -EINVAL; + + mutex_lock(&p->mutex); + pdd = kfd_bind_process_to_device(dev, p); + if (IS_ERR(pdd)) { + mutex_unlock(&p->mutex); + pr_err("Failed to get pdd\n"); + return PTR_ERR(pdd); + } + + kfd_bo = kfd_process_device_find_bo(pdd, GET_IDR_HANDLE(handle)); + mutex_unlock(&p->mutex); + + if (!kfd_bo) { + pr_err("Failed to get bo"); + return -EINVAL; + } + if (kfd_bo->kfd_ipc_obj) { + memcpy(ipc_handle, kfd_bo->kfd_ipc_obj->share_handle, + sizeof(kfd_bo->kfd_ipc_obj->share_handle)); + return 0; + } + + r = amdgpu_amdkfd_gpuvm_export_dmabuf(dev->kgd, pdd->vm, + (struct kgd_mem *)kfd_bo->mem, + &dmabuf); + if (r) + return r; + + r = ipc_store_insert(dmabuf, ipc_handle, &obj); + if (r) + return r; + + kfd_bo->kfd_ipc_obj = obj; + + return r; +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h new file mode 100644 index 0000000000000..9ee8627b88b08 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -0,0 +1,51 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef KFD_IPC_H_ +#define KFD_IPC_H_ + +#include +#include "kfd_priv.h" + +struct kfd_ipc_obj { + struct hlist_node node; + struct kref ref; + void *data; + uint32_t share_handle[4]; +}; + +int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, + uint32_t gpu_id, uint32_t *share_handle, + uint64_t va_addr, uint64_t *handle, + uint64_t *mmap_offset); +int kfd_ipc_import_dmabuf(struct kfd_dev *kfd, struct kfd_process *p, + uint32_t gpu_id, int dmabuf_fd, + uint64_t va_addr, uint64_t *handle, + uint64_t *mmap_offset); +int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, + uint64_t handle, uint32_t *ipc_handle); + +void ipc_obj_get(struct kfd_ipc_obj *obj); +void ipc_obj_put(struct kfd_ipc_obj **obj); + +#endif /* KFD_IPC_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index aee2212e52f69..a4f3155d0a2b1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -53,6 +53,10 @@ static int kfd_init(void) if (err < 0) goto err_topology; + err = kfd_ipc_init(); + if (err < 0) + goto err_ipc; + err = kfd_process_create_wq(); if (err < 0) goto err_create_wq; @@ -67,6 +71,7 @@ static int kfd_init(void) return 0; err_create_wq: +err_ipc: kfd_topology_shutdown(); err_topology: kfd_chardev_exit(); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 4590d4ea1d271..ffb3435155738 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -380,6 +380,19 @@ struct kfd_dev { int kfd_dev_lock; }; +struct kfd_ipc_obj; + +struct kfd_bo { + void *mem; + struct interval_tree_node it; + struct kfd_dev *dev; + struct list_head cb_data_head; + struct kfd_ipc_obj *kfd_ipc_obj; + /* page-aligned VA address */ + uint64_t cpuva; + unsigned int mem_type; +}; + enum kfd_mempool { KFD_MEMPOOL_SYSTEM_CACHEABLE = 1, KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2, @@ -940,6 +953,8 @@ struct kfd_process { size_t signal_event_count; bool signal_event_limit_reached; + struct rb_root_cached bo_interval_tree; + /* Information used for memory eviction */ void *kgd_process_info; /* Eviction fence that is attached to all the BOs of this process. The @@ -1087,9 +1102,17 @@ int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process, /* KFD process API for creating and translating handles */ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, - void *mem); + void *mem, uint64_t start, + uint64_t length, uint64_t cpuva, + unsigned int mem_type, + struct kfd_ipc_obj *ipc_obj); void *kfd_process_device_translate_handle(struct kfd_process_device *p, int handle); +struct kfd_bo *kfd_process_device_find_bo(struct kfd_process_device *pdd, + int handle); +void *kfd_process_find_bo_from_interval(struct kfd_process *p, + uint64_t start_addr, + uint64_t last_addr); void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, int handle); struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid); @@ -1544,6 +1567,9 @@ int kfd_send_exception_to_runtime(struct kfd_process *p, uint64_t error_reason); bool kfd_is_locked(struct kfd_dev *kfd); +/* IPC Support */ +int kfd_ipc_init(void); + /* Compute profile */ void kfd_inc_compute_active(struct kfd_node *dev); void kfd_dec_compute_active(struct kfd_node *dev); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 5be28c6c4f6aa..b6ea295f5af0e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -32,6 +32,7 @@ #include #include #include +#include "kfd_ipc.h" #include #include "amdgpu_amdkfd.h" #include "amdgpu.h" @@ -742,6 +743,7 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, { struct kfd_node *kdev = pdd->dev; int err; + unsigned int mem_type; err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, gpu_va, size, pdd->drm_priv, mem, NULL, @@ -985,7 +987,7 @@ struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid) static void kfd_process_device_free_bos(struct kfd_process_device *pdd) { struct kfd_process *p = pdd->process; - void *mem; + struct kfd_bo *buf_obj; int id; int i; @@ -993,7 +995,8 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) * Remove all handles from idr and release appropriate * local memory object */ - idr_for_each_entry(&pdd->alloc_idr, mem, id) { + idr_for_each_entry(&pdd->alloc_idr, buf_obj, id) { + struct kfd_process_device *peer_pdd; for (i = 0; i < p->n_pdds; i++) { struct kfd_process_device *peer_pdd = p->pdds[i]; @@ -1001,11 +1004,11 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) if (!peer_pdd->drm_priv) continue; amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( - peer_pdd->dev->adev, mem, peer_pdd->drm_priv); + peer_pdd->dev->kgd, buf_obj->mem, peer_pdd->drm_priv); } amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, mem, - pdd->drm_priv, NULL); + buf_obj->mem, pdd->drm_priv, NULL); kfd_process_device_remove_obj_handle(pdd, id); } } @@ -1783,9 +1786,49 @@ struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev, * Assumes that the process lock is held. */ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, - void *mem) + void *mem, uint64_t start, + uint64_t length, uint64_t cpuva, + unsigned int mem_type, + struct kfd_ipc_obj *ipc_obj) +{ + int handle; + struct kfd_bo *buf_obj; + struct kfd_process *p; + + p = pdd->process; + + buf_obj = kzalloc(sizeof(*buf_obj), GFP_KERNEL); + + if (!buf_obj) + return -ENOMEM; + + buf_obj->it.start = start; + buf_obj->it.last = start + length - 1; + interval_tree_insert(&buf_obj->it, &p->bo_interval_tree); + + buf_obj->mem = mem; + buf_obj->dev = pdd->dev; + buf_obj->kfd_ipc_obj = ipc_obj; + buf_obj->cpuva = cpuva; + buf_obj->mem_type = mem_type; + + INIT_LIST_HEAD(&buf_obj->cb_data_head); + + handle = idr_alloc(&pdd->alloc_idr, buf_obj, 0, 0, GFP_KERNEL); + + if (handle < 0) + kfree(buf_obj); + + return handle; +} + +struct kfd_bo *kfd_process_device_find_bo(struct kfd_process_device *pdd, + int handle) { - return idr_alloc(&pdd->alloc_idr, mem, 0, 0, GFP_KERNEL); + if (handle < 0) + return NULL; + + return (struct kfd_bo *)idr_find(&pdd->alloc_idr, handle); } /* Translate specific handle from process local memory idr @@ -1794,10 +1837,37 @@ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, void *kfd_process_device_translate_handle(struct kfd_process_device *pdd, int handle) { - if (handle < 0) + struct kfd_bo *buf_obj; + + buf_obj = kfd_process_device_find_bo(pdd, handle); + + return buf_obj->mem; +} + +void *kfd_process_find_bo_from_interval(struct kfd_process *p, + uint64_t start_addr, + uint64_t last_addr) +{ + struct interval_tree_node *it_node; + struct kfd_bo *buf_obj; + + it_node = interval_tree_iter_first(&p->bo_interval_tree, + start_addr, last_addr); + if (!it_node) { + pr_err("0x%llx-0x%llx does not relate to an existing buffer\n", + start_addr, last_addr); return NULL; + } + + if (interval_tree_iter_next(it_node, start_addr, last_addr)) { + pr_err("0x%llx-0x%llx spans more than a single BO\n", + start_addr, last_addr); + return NULL; + } + + buf_obj = container_of(it_node, struct kfd_bo, it); - return idr_find(&pdd->alloc_idr, handle); + return buf_obj; } /* Remove specific handle from process local memory idr @@ -1806,8 +1876,24 @@ void *kfd_process_device_translate_handle(struct kfd_process_device *pdd, void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, int handle) { - if (handle >= 0) - idr_remove(&pdd->alloc_idr, handle); + struct kfd_bo *buf_obj; + struct kfd_process *p; + + p = pdd->process; + + if (handle < 0) + return; + + buf_obj = kfd_process_device_find_bo(pdd, handle); + + if (buf_obj->kfd_ipc_obj) + ipc_obj_put(&buf_obj->kfd_ipc_obj); + + idr_remove(&pdd->alloc_idr, handle); + + interval_tree_remove(&buf_obj->it, &p->bo_interval_tree); + + kfree(buf_obj); } static struct kfd_process_device *kfd_lookup_process_device_by_pasid(u32 pasid) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 04c7d283dc7d7..0c47f80a2250e 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -739,6 +739,22 @@ enum kfd_mmio_remap { KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4, }; +struct kfd_ioctl_ipc_export_handle_args { + __u64 handle; /* to KFD */ + __u32 share_handle[4]; /* from KFD */ + __u32 gpu_id; /* to KFD */ + __u32 pad; +}; + +struct kfd_ioctl_ipc_import_handle_args { + __u64 handle; /* from KFD */ + __u64 va_addr; /* to KFD */ + __u64 mmap_offset; /* from KFD */ + __u32 share_handle[4]; /* to KFD */ + __u32 gpu_id; /* to KFD */ + __u32 pad; +}; + /* Guarantee host access to memory */ #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 /* Fine grained coherency between all devices with access */ @@ -1671,6 +1687,12 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_DBG_TRAP \ AMDKFD_IOWR(0x26, struct kfd_ioctl_dbg_trap_args) +#define AMDKFD_IOC_IPC_IMPORT_HANDLE \ + AMDKFD_IOWR(0x80, struct kfd_ioctl_ipc_import_handle_args) + +#define AMDKFD_IOC_IPC_EXPORT_HANDLE \ + AMDKFD_IOWR(0x81, struct kfd_ioctl_ipc_export_handle_args) + #define AMDKFD_COMMAND_START 0x01 #define AMDKFD_COMMAND_END 0x27 From 0cd07f5c10d277e803c159dbbcbcf20eadb4c641 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 01:26:36 -0400 Subject: [PATCH 0258/2653] drm/amdkfd: Add new GPU debugging API This is a completely new debug API that allows a debugger in a separate process to control wave execution, receive asynchronous notifications of events and query queue status. Change-Id: I765b39ebbd4ceb8a75c64c8a1ee24ab043c40330 Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 8 ++++++++ .../drm/amd/include/asic_reg/gc/gc_10_1_0_default.h | 7 +++++++ drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 5 +++++ include/uapi/linux/kfd_ioctl.h | 10 ++++++++++ 5 files changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 2d91027e2a747..ed6d0ef6a57bf 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -2388,7 +2389,6 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm, if (retval) goto out; } - retval = pm_send_unmap_queue(&dqm->packet_mgr, filter, filter_param, reset); if (retval) goto out; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index ffb3435155738..8aea58c6c062c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1117,6 +1117,14 @@ void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, int handle); struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid); +/* Process device data iterator */ +struct kfd_process_device *kfd_get_first_process_device_data( + struct kfd_process *p); +struct kfd_process_device *kfd_get_next_process_device_data( + struct kfd_process *p, + struct kfd_process_device *pdd); +bool kfd_has_process_device_data(struct kfd_process *p); + /* PASIDs */ int kfd_pasid_init(void); void kfd_pasid_exit(void); diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h index 320e1ee5df1a9..2050888f7ec6d 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h @@ -2616,6 +2616,13 @@ #define mmSPI_WCL_PIPE_PERCENT_CS5_DEFAULT 0x0000007f #define mmSPI_WCL_PIPE_PERCENT_CS6_DEFAULT 0x0000007f #define mmSPI_WCL_PIPE_PERCENT_CS7_DEFAULT 0x0000007f +#define mmSPI_GDBG_WAVE_CNTL_DEFAULT 0x00000000 +#define mmSPI_GDBG_TRAP_CONFIG_DEFAULT 0x00000000 +#define mmSPI_GDBG_TRAP_MASK_DEFAULT 0x00000000 +#define mmSPI_GDBG_WAVE_CNTL2_DEFAULT 0x00000000 +#define mmSPI_GDBG_WAVE_CNTL3_DEFAULT 0x00000000 +#define mmSPI_GDBG_TRAP_DATA0_DEFAULT 0x00000000 +#define mmSPI_GDBG_TRAP_DATA1_DEFAULT 0x00000000 #define mmSPI_COMPUTE_QUEUE_RESET_DEFAULT 0x00000000 #define mmSPI_RESOURCE_RESERVE_CU_0_DEFAULT 0x00000000 #define mmSPI_RESOURCE_RESERVE_CU_1_DEFAULT 0x00000000 diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 9aba8596faa7e..ed07155666ab6 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -204,6 +204,11 @@ struct tile_config { * IH ring entry. This function allows the KFD ISR to get the VMID * from the fault status register as early as possible. * + * @get_iq_wait_times: Returns the mmCP_IQ_WAIT_TIME1/2 values + * + * @build_grace_period_packet_info: build a IQ_WAUT_TIME2 reg value with an + * updated grace period value. + * * @get_cu_occupancy: Function pointer that returns to caller the number * of wave fronts that are in flight for all of the queues of a process * as identified by its pasid. It is important to note that the value diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 0c47f80a2250e..db022f11f934e 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -248,6 +248,16 @@ struct kfd_ioctl_dbg_wave_control_args { #define KFD_INVALID_FD 0xffffffff +struct kfd_ioctl_dbg_trap_args { + __u64 ptr; /* to KFD -- used for pointer arguments: queue arrays */ + __u32 pid; /* to KFD */ + __u32 gpu_id; /* to KFD */ + __u32 op; /* to KFD */ + __u32 data1; /* to KFD */ + __u32 data2; /* to KFD */ + __u32 data3; /* to KFD */ +}; + /* Matching HSA_EVENTTYPE */ #define KFD_IOC_EVENT_SIGNAL 0 #define KFD_IOC_EVENT_NODECHANGE 1 From 196d87ff0c08a61494579c2a3fa92d06210a58e5 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 02:23:36 -0400 Subject: [PATCH 0259/2653] drm/amdkfd: Add RDMA and PeerDirect support Both are interfaces between kernel drivers for direct peer-memory access between different devices, e.g. NICs and GPUs. The PeerDirect API is defined by Mellanox and supported by their non-upstream NIC driver. RDMA is an AMD interface and provides the implementation underneath the PeerDirect wrapper. It currently has no external users. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 22 + .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 206 ++++- drivers/gpu/drm/amd/amdkfd/Makefile | 1 + drivers/gpu/drm/amd/amdkfd/kfd_module.c | 3 + drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 702 ++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 9 +- drivers/gpu/drm/amd/dkms/sources | 1 + include/drm/amd_rdma.h | 78 ++ 9 files changed, 1021 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c create mode 100644 include/drm/amd_rdma.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 1e600a5cb3c91..d91e680615c06 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -327,6 +327,28 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info, struct dma_fence __rcu **ef); int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, struct kfd_vm_fault_info *info); + +struct amdgpu_bo *amdgpu_amdkfd_gpuvm_get_bo_ref(struct kgd_mem *mem, + uint32_t *flags); +void amdgpu_amdkfd_gpuvm_put_bo_ref(struct amdgpu_bo *bo); + +int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo); +void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo); + +int amdgpu_amdkfd_gpuvm_get_sg_table(struct kgd_dev *kgd, + struct amdgpu_bo *bo, uint32_t flags, + uint64_t offset, uint64_t size, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table **ret_sg); +void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table *sg); + +int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, + struct dma_buf *dmabuf, + uint64_t va, void *drm_priv, + struct kgd_mem **mem, uint64_t *size, + uint64_t *mmap_offset); int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, uint64_t va, void *drm_priv, struct kgd_mem **mem, uint64_t *size, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 1a701ac055c16..7248bd9f482a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1461,7 +1461,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, * * Return: ZERO if successful in pinning, Non-Zero in case of error. */ -static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) +int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) { int ret = 0; @@ -1504,7 +1504,7 @@ static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their * PIN count decremented. Calls to UNPIN must balance calls to PIN */ -static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo) +void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo) { int ret = 0; @@ -2314,6 +2314,208 @@ int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, return 0; } +struct amdgpu_bo *amdgpu_amdkfd_gpuvm_get_bo_ref(struct kgd_mem *mem, + uint32_t *flags) +{ + struct amdgpu_bo *bo = mem->bo; + + if (flags) + *flags = mem->alloc_flags; + drm_gem_object_get(&bo->tbo.base); + return bo; +} + +void amdgpu_amdkfd_gpuvm_put_bo_ref(struct amdgpu_bo *bo) +{ + drm_gem_object_put(&bo->tbo.base); +} + +#define AMD_GPU_PAGE_SHIFT PAGE_SHIFT +#define AMD_GPU_PAGE_SIZE (_AC(1, UL) << AMD_GPU_PAGE_SHIFT) + +/** + * @get_sg_table_of_mmio_or_doorbel_bo - Builds and returns an instance + * of scatter gather table (sg_table) for BO's that represent MMIO or + * DOORBELL memory. An example of this is the MMIO BO that is used to + * surface HDP registers. + * + * @note: Per current design and implementation MMIO or DOORBELL BO's + * use only one scatterlist node in their sg_table. This is because + * the size of backing memory is relatively small (e.g. 4096 bytes + * for MMIO BO surfacing HDP registers). Implementation of this method + * relies on this design choice. + * + * The method does the following: + * Acquire address to use in building scatterlist nodes + * Acquire size of memory to use in building scatterlist nodes + * Invoke DMA Map service to obtain DMA'able address + * Access sg_table construction service with above parameters + * Return the handle of scatter gather table + * + * @adev: GPU device whose MMIO address needs to be exported + * @bo: Buffer object representing MMIO/DOORBELL memory e.g. HDP registers + * @dma_dev: Handle of peer PCIe device that wishes to access BO's memory + * @dir: Direction of data movement from peer PCIe devices perspective + * + * @sgt: Output parameter that is built and returned + * + * Return: zero if successful, non-zero otherwise + * + * @FIXME: This will only work as long as bo->tbo.sg->sgl->dma_address + * is not a DMA address but a physical BAR address. This will be reworked + * later when we add DMA mapping support for doorbell and MMIO BOs + */ +static int get_sg_table_of_mmio_or_doorbel_bo(struct amdgpu_bo *bo, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table **sgt) +{ + dma_addr_t dma_addr; + s32 size, ret; + u64 addr; + + /* Acquire the address of MMIO or DOORBELL BO being + * exported. By policy the entire backing memory is + * encapsulated in one scatterlist node + */ + size = bo->tbo.sg->sgl->length; + addr = bo->tbo.sg->sgl->dma_address; + pr_debug("MMIO/Doorbell address being exported: %llx\n", addr); + + /* DMA map the acquired address - MMIO or DOORBELL */ + dma_addr = dma_map_resource(dma_dev, addr, size, + dir, DMA_ATTR_SKIP_CPU_SYNC); + ret = dma_mapping_error(dma_dev, dma_addr); + if (ret) + return ret; + + /* Update output parameter with a new sg_table */ + pr_debug("MMIO/Doorbell BO size: %d\n", size); + pr_debug("MMIO/Doorbell's DMA Address: %llx\n", dma_addr); + *sgt = create_doorbell_sg(dma_addr, size); + return 0; +} + +int amdgpu_amdkfd_gpuvm_get_sg_table(struct kgd_dev *kgd, + struct amdgpu_bo *bo, uint32_t flags, + uint64_t offset, uint64_t size, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table **ret_sg) +{ + struct amdgpu_device *adev = get_amdgpu_device(kgd); + struct sg_table *sg = NULL; + struct scatterlist *s; + struct page **pages; + uint64_t offset_in_page; + unsigned int page_size; + unsigned int cur_page; + unsigned int chunks; + unsigned int idx; + int ret; + + /* Determine access does not cross memory boundary */ + if (size + offset > amdgpu_bo_size(bo)) + return -EFAULT; + + /* For GPU memory use VRAM Mgr to build SG Table */ + if (bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM) { + ret = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, offset, + size, dma_dev, dir, &sg); + *ret_sg = (ret == 0) ? sg : NULL; + return ret; + } + + /* Handle BO (type: ttm_bo_type_sg) that is used to surface + * resources from MMIO address space. The allocation flag of + * BO fall in MMIO_REMAP / DOORBELL domain + */ + if (bo->tbo.type == ttm_bo_type_sg && + ((flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) || + (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { + ret = get_sg_table_of_mmio_or_doorbel_bo(bo, dma_dev, dir, &sg); + *ret_sg = (ret == 0) ? sg : NULL; + return ret; + } + + /* Handle BO (type: ttm_bo_type_device) that is used to surface + * memory resources from GPU's GART aperture. The allocation flag + * of BO falls in GTT domain i.e. the physical backing memory is + * part of system memory. Construction of SG Table proceeds + * as follows: + * + * Allocate memory for SG Table + * Determine number of Scatterlist node in table + * Logic uses one Scatterlist node per PAGE_SIZE + * Allocate memory for Scatterlist nodes + * Initialize Scatterlist nodes to zero length + * Walk down system memory pointed by BO while + * Updating Scatterlist nodes with system memory info + */ + sg = kmalloc(sizeof(*sg), GFP_KERNEL); + if (!sg) { + ret = -ENOMEM; + goto out; + } + + page_size = PAGE_SIZE; + offset_in_page = offset & (page_size - 1); + chunks = (size + offset_in_page + page_size - 1) + / page_size; + + ret = sg_alloc_table(sg, chunks, GFP_KERNEL); + if (unlikely(ret)) + goto out; + + for_each_sgtable_sg(sg, s, idx) + s->length = 0; + + pages = bo->tbo.ttm->pages; + cur_page = offset / page_size; + for_each_sg(sg->sgl, s, sg->orig_nents, idx) { + uint64_t chunk_size, length; + + chunk_size = page_size - offset_in_page; + length = min(size, chunk_size); + + sg_set_page(s, pages[cur_page], length, offset_in_page); + s->dma_address = page_to_phys(pages[cur_page]); + s->dma_length = length; + + size -= length; + offset_in_page = 0; + cur_page++; + } + + ret = dma_map_sgtable(dma_dev, sg, dir, DMA_ATTR_SKIP_CPU_SYNC); + if (ret) + goto out_of_range; + + *ret_sg = sg; + return 0; + +out_of_range: + sg_free_table(sg); +out: + kfree(sg); + *ret_sg = NULL; + return ret; +} + +void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table *sgt) +{ + /* Unmap GPU device memory */ + if (bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM) { + amdgpu_vram_mgr_free_sgt(dma_dev, dir, sgt); + return; + } + + /* Unmap system memory */ + dma_unmap_sgtable(dma_dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC); + sg_free_table(sgt); + kfree(sgt); +} + static int import_obj_create(struct amdgpu_device *adev, struct dma_buf *dma_buf, struct drm_gem_object *obj, diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 0d690dd859f96..d4b73964998d0 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -58,6 +58,7 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_int_process_v11.o \ $(AMDKFD_PATH)/kfd_smi_events.o \ $(AMDKFD_PATH)/kfd_crat.o \ + $(AMDKFD_PATH)/kfd_peerdirect.o \ $(AMDKFD_PATH)/kfd_ipc.o \ $(AMDKFD_PATH)/kfd_debug.o diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index a4f3155d0a2b1..5f8093e03d340 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -61,6 +61,8 @@ static int kfd_init(void) if (err < 0) goto err_create_wq; + kfd_init_peer_direct(); + /* Ignore the return value, so that we can continue * to init the KFD, even if procfs isn't craated */ @@ -84,6 +86,7 @@ static void kfd_exit(void) { kfd_cleanup_processes(); kfd_debugfs_fini(); + kfd_close_peer_direct(); kfd_process_destroy_wq(); kfd_procfs_shutdown(); kfd_topology_shutdown(); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c new file mode 100644 index 0000000000000..27fe96b788de6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -0,0 +1,702 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + + +/* NOTE: + * + * This file contains logic to dynamically detect and enable PeerDirect + * suppor. PeerDirect support is delivered e.g. as part of OFED + * from Mellanox. Because we are not able to rely on the fact that the + * corresponding OFED will be installed we should: + * - copy PeerDirect definitions locally to avoid dependency on + * corresponding header file + * - try dynamically detect address of PeerDirect function + * pointers. + * + * If dynamic detection failed then PeerDirect support should be + * enabled using the standard PeerDirect bridge driver from: + * https://github.com/RadeonOpenCompute/ROCnRDMA + * + * + * Logic to support PeerDirect relies only on official public API to be + * non-intrusive as much as possible. + * + **/ + +#include +#include +#include +#include +#include +#include + +#include "kfd_priv.h" + +/* ----------------------- PeerDirect interface ------------------------------*/ + +/* + * Copyright (c) 2013, Mellanox Technologies. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#define IB_PEER_MEMORY_NAME_MAX 64 +#define IB_PEER_MEMORY_VER_MAX 16 + +struct peer_memory_client { + char name[IB_PEER_MEMORY_NAME_MAX]; + char version[IB_PEER_MEMORY_VER_MAX]; + /* acquire return code: 1-mine, 0-not mine */ + int (*acquire)(unsigned long addr, size_t size, + void *peer_mem_private_data, + char *peer_mem_name, + void **client_context); + int (*get_pages)(unsigned long addr, + size_t size, int write, int force, + struct sg_table *sg_head, + void *client_context, void *core_context); + int (*dma_map)(struct sg_table *sg_head, void *client_context, + struct device *dma_device, int dmasync, int *nmap); + int (*dma_unmap)(struct sg_table *sg_head, void *client_context, + struct device *dma_device); + void (*put_pages)(struct sg_table *sg_head, void *client_context); + unsigned long (*get_page_size)(void *client_context); + void (*release)(void *client_context); + void* (*get_context_private_data)(u64 peer_id); + void (*put_context_private_data)(void *context); +}; + +typedef int (*invalidate_peer_memory)(void *reg_handle, + void *core_context); + +void *ib_register_peer_memory_client(struct peer_memory_client *peer_client, + invalidate_peer_memory *invalidate_callback); +void ib_unregister_peer_memory_client(void *reg_handle); + + +/*------------------- PeerDirect bridge driver ------------------------------*/ + +#define AMD_PEER_BRIDGE_DRIVER_VERSION "1.0" +#define AMD_PEER_BRIDGE_DRIVER_NAME "amdkfd" + +static char rdma_name[] = "AMD RDMA"; + + +static void* (*pfn_ib_register_peer_memory_client)(struct peer_memory_client + *peer_client, + invalidate_peer_memory + *invalidate_callback); + +static void (*pfn_ib_unregister_peer_memory_client)(void *reg_handle); + +static void *ib_reg_handle; + +struct amd_mem_context { + uint64_t va; + uint64_t size; + unsigned long offset; + struct amdgpu_bo *bo; + struct kfd_dev *dev; + + struct sg_table *pages; + struct device *dma_dev; + + + /* Context received from PeerDirect call */ + void *core_context; + + pid_t pid; + uint32_t flags; +}; + +/* Workaround: Mellanox peerdirect driver expects sg lists at + * page granularity. This causes failures when an application tries + * to register size < PAGE_SIZE or addr starts at some offset. Fix + * it by aligning the size to page size and addr to page boundary. + */ +static void align_addr_size(unsigned long *addr, size_t *size) +{ + unsigned long end = ALIGN(*addr + *size, PAGE_SIZE); + + *addr = ALIGN_DOWN(*addr, PAGE_SIZE); + *size = end - *addr; +} + +static int amd_acquire(unsigned long addr, size_t size, + void *peer_mem_private_data, + char *peer_mem_name, void **client_context) +{ + struct kfd_process *p; + struct kfd_bo *buf_obj; + struct amd_mem_context *mem_context; + + if (peer_mem_name == rdma_name) { + p = peer_mem_private_data; + } else { + p = kfd_get_process(current); + if (!p) { + pr_debug("Not a KFD process\n"); + return 0; + } + } + + align_addr_size(&addr, &size); + + mutex_lock(&p->mutex); + buf_obj = kfd_process_find_bo_from_interval(p, addr, + addr + size - 1); + if (!buf_obj) { + pr_debug("Cannot find a kfd_bo for the range\n"); + goto out_unlock; + } + + /* Initialize context used for operation with given address */ + mem_context = kzalloc(sizeof(*mem_context), GFP_KERNEL); + if (!mem_context) + goto out_unlock; + + mem_context->pid = p->lead_thread->pid; + + pr_debug("addr: %#lx, size: %#lx, pid: %d\n", + addr, size, mem_context->pid); + + mem_context->va = addr; + mem_context->size = size; + mem_context->offset = addr - buf_obj->it.start; + + mem_context->bo = amdgpu_amdkfd_gpuvm_get_bo_ref(buf_obj->mem, + &mem_context->flags); + mem_context->dev = buf_obj->dev; + + mutex_unlock(&p->mutex); + + pr_debug("Client context: 0x%p\n", mem_context); + + /* Return pointer to allocated context */ + *client_context = mem_context; + + /* Return 1 to inform that this address which will be handled + * by AMD GPU driver + */ + return 1; + +out_unlock: + mutex_unlock(&p->mutex); + return 0; +} + +static int amd_get_pages(unsigned long addr, size_t size, int write, int force, + struct sg_table *sg_head, + void *client_context, void *core_context) +{ + int ret; + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + align_addr_size(&addr, &size); + + pr_debug("addr: %#lx, size: %#lx, core_context: 0x%p\n", + addr, size, core_context); + + if (!mem_context || !mem_context->bo || !mem_context->dev) { + pr_warn("Invalid client context"); + return -EINVAL; + } + + pr_debug("pid: %d\n", mem_context->pid); + + if (addr != mem_context->va) { + pr_warn("Context address (%#llx) is not the same\n", + mem_context->va); + return -EINVAL; + } + + if (size != mem_context->size) { + pr_warn("Context size (%#llx) is not the same\n", + mem_context->size); + return -EINVAL; + } + + ret = amdgpu_amdkfd_gpuvm_pin_bo(mem_context->bo); + if (ret) { + pr_err("Pinning of buffer failed.\n"); + return ret; + } + + /* Mark the device as active */ + kfd_inc_compute_active(mem_context->dev); + + mem_context->core_context = core_context; + + return 0; +} + + +static int amd_dma_map(struct sg_table *sg_head, void *client_context, + struct device *dma_device, int dmasync, int *nmap) +{ + struct sg_table *sg_table_tmp; + int ret; + + /* + * NOTE/TODO: + * We could have potentially three cases for real memory + * location: + * - all memory in the local + * - all memory in the system (RAM) + * - memory is spread (s/g) between local and system. + * + * In the case of all memory in the system we could use + * iommu driver to build DMA addresses but not in the case + * of local memory because currently iommu driver doesn't + * deal with local/device memory addresses (it requires "struct + * page"). + * + * Accordingly returning assumes that iommu funcutionality + * should be disabled so we can assume that sg_table already + * contains DMA addresses. + * + */ + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + pr_debug("Client context: 0x%p, sg_head: 0x%p\n", + client_context, sg_head); + + if (!mem_context || !mem_context->bo || !mem_context->dev) { + pr_warn("Invalid client context"); + return -EINVAL; + } + + pr_debug("pid: %d, address: %#llx, size: %#llx\n", + mem_context->pid, + mem_context->va, + mem_context->size); + + /* Build sg_table for buffer being exported, including DMA mapping */ + ret = amdgpu_amdkfd_gpuvm_get_sg_table( + mem_context->dev->kgd, mem_context->bo, mem_context->flags, + mem_context->offset, mem_context->size, + dma_device, DMA_BIDIRECTIONAL, &sg_table_tmp); + if (ret) { + pr_err("Building of sg_table failed\n"); + return ret; + } + + /* Maintain a copy of the handle to sg_table */ + mem_context->pages = sg_table_tmp; + mem_context->dma_dev = dma_device; + + /* Copy information about previosly allocated sg_table */ + *sg_head = *mem_context->pages; + + /* Return number of pages */ + *nmap = mem_context->pages->nents; + + return ret; +} + +static int amd_dma_unmap(struct sg_table *sg_head, void *client_context, + struct device *dma_device) +{ + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + pr_debug("Client context: 0x%p, sg_table: 0x%p\n", + client_context, sg_head); + + if (!mem_context || !mem_context->bo || !mem_context->dma_dev) { + pr_warn("Invalid client context"); + return -EINVAL; + } + + pr_debug("pid: %d, address: %#llx, size: %#llx\n", + mem_context->pid, + mem_context->va, + mem_context->size); + + /* Release the mapped pages of buffer */ + amdgpu_amdkfd_gpuvm_put_sg_table(mem_context->bo, + mem_context->dma_dev, + DMA_BIDIRECTIONAL, + mem_context->pages); + mem_context->pages = NULL; + + return 0; +} + +static void amd_put_pages(struct sg_table *sg_head, void *client_context) +{ + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + pr_debug("Client context: 0x%p, sg_head: 0x%p\n", + client_context, sg_head); + pr_debug("pid: %d, address: %#llx, size: %#llx\n", + mem_context->pid, + mem_context->va, + mem_context->size); + + amdgpu_amdkfd_gpuvm_unpin_bo(mem_context->bo); + kfd_dec_compute_active(mem_context->dev); +} + +static unsigned long amd_get_page_size(void *client_context) +{ + return PAGE_SIZE; +} + +static void amd_release(void *client_context) +{ + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + pr_debug("Client context: 0x%p\n", client_context); + pr_debug("pid: %d, address: %#llx, size: %#llx\n", + mem_context->pid, + mem_context->va, + mem_context->size); + + amdgpu_amdkfd_gpuvm_put_bo_ref(mem_context->bo); + + kfree(mem_context); +} + + +static struct peer_memory_client amd_mem_client = { + .acquire = amd_acquire, + .get_pages = amd_get_pages, + .dma_map = amd_dma_map, + .dma_unmap = amd_dma_unmap, + .put_pages = amd_put_pages, + .get_page_size = amd_get_page_size, + .release = amd_release, + .get_context_private_data = NULL, + .put_context_private_data = NULL, +}; + +/** Initialize PeerDirect interface with RDMA Network stack. + * + * Because network stack could potentially be loaded later we check + * presence of PeerDirect when HSA process is created. If PeerDirect was + * already initialized we do nothing otherwise try to detect and register. + */ +void kfd_init_peer_direct(void) +{ + if (pfn_ib_unregister_peer_memory_client) { + pr_debug("PeerDirect support was already initialized\n"); + return; + } + + pr_debug("Try to initialize PeerDirect support\n"); + + pfn_ib_register_peer_memory_client = + (void *(*)(struct peer_memory_client *, + invalidate_peer_memory *)) + symbol_request(ib_register_peer_memory_client); + + pfn_ib_unregister_peer_memory_client = (void (*)(void *)) + symbol_request(ib_unregister_peer_memory_client); + + if (!pfn_ib_register_peer_memory_client || + !pfn_ib_unregister_peer_memory_client) { + pr_debug("PeerDirect interface was not detected\n"); + /* Do cleanup */ + kfd_close_peer_direct(); + return; + } + + strcpy(amd_mem_client.name, AMD_PEER_BRIDGE_DRIVER_NAME); + strcpy(amd_mem_client.version, AMD_PEER_BRIDGE_DRIVER_VERSION); + + ib_reg_handle = pfn_ib_register_peer_memory_client(&amd_mem_client, NULL); + + if (!ib_reg_handle) { + pr_err("Cannot register peer memory client\n"); + /* Do cleanup */ + kfd_close_peer_direct(); + return; + } + + pr_info("PeerDirect support was initialized successfully\n"); +} + +/** + * Close connection with PeerDirect interface with RDMA Network stack. + * + */ +void kfd_close_peer_direct(void) +{ + if (pfn_ib_unregister_peer_memory_client) { + if (ib_reg_handle) + pfn_ib_unregister_peer_memory_client(ib_reg_handle); + + symbol_put(ib_unregister_peer_memory_client); + } + + if (pfn_ib_register_peer_memory_client) + symbol_put(ib_register_peer_memory_client); + + + /* Reset pointers to be safe */ + pfn_ib_unregister_peer_memory_client = NULL; + pfn_ib_register_peer_memory_client = NULL; + ib_reg_handle = NULL; +} + +/* ------------------------- AMD RDMA wrapper --------------------------------*/ + +#include "drm/amd_rdma.h" + +struct rdma_p2p_data { + struct amd_p2p_info p2p_info; + void (*free_callback)(void *client_priv); + void *client_priv; +}; + +/** + * This function makes the pages underlying a range of GPU virtual memory + * accessible for DMA operations from another PCIe device + * + * \param address - The start address in the Unified Virtual Address + * space in the specified process + * \param length - The length of requested mapping + * \param pid - Pointer to structure pid to which address belongs. + * Could be NULL for current process address space. + * \param p2p_data - On return: Pointer to structure describing + * underlying pages/locations + * \param free_callback - Pointer to callback which will be called when access + * to such memory must be stopped immediately: Memory + * was freed, GECC events, etc. + * Client should immediately stop any transfer + * operations and returned as soon as possible. + * After return all resources associated with address + * will be release and no access will be allowed. + * \param client_priv - Pointer to be passed as parameter on + * 'free_callback; + * + * \return 0 if operation was successful + */ +static int rdma_get_pages(uint64_t address, uint64_t length, struct pid *pid, + struct device *dma_dev, + struct amd_p2p_info **amd_p2p_data, + void (*free_callback)(void *client_priv), + void *client_priv) +{ + struct rdma_p2p_data *p2p_data; + struct kfd_process *p; + struct sg_table sg_head; + struct amd_mem_context *mem_context; + int nmap; + int r; + + p2p_data = kzalloc(sizeof(*p2p_data), GFP_KERNEL); + if (!p2p_data) + return -ENOMEM; + + p = kfd_lookup_process_by_pid(pid); + if (!p) { + pr_debug("pid lookup failed\n"); + r = -ESRCH; + goto err_lookup_process; + } + + r = amd_acquire(address, length, p, rdma_name, (void **)&mem_context); + kfd_unref_process(p); + if (r == 0) { + pr_debug("acquire failed: %d\n", r); + goto err_acquire; + } + + r = amd_get_pages(address, length, 1, 0, &sg_head, + mem_context, p2p_data); + if (r) { + pr_debug("get_pages failed: %d\n", r); + goto err_get_pages; + } + + r = amd_dma_map(&sg_head, mem_context, dma_dev, 0, &nmap); + if (r) { + pr_debug("dma_map failed: %d\n", r); + goto err_dma_map; + } + + + p2p_data->free_callback = free_callback; + p2p_data->client_priv = client_priv; + p2p_data->p2p_info.va = address; + p2p_data->p2p_info.size = length; + p2p_data->p2p_info.pid = pid; + p2p_data->p2p_info.pages = mem_context->pages; + p2p_data->p2p_info.priv = mem_context; + + *amd_p2p_data = &p2p_data->p2p_info; + + return 0; + +err_dma_map: + amd_put_pages(&sg_head, mem_context); +err_get_pages: + amd_release(mem_context); +err_acquire: +err_lookup_process: + kfree(p2p_data); + + return r; +} + +/** + * + * This function release resources previously allocated by get_pages() call. + * + * \param p_p2p_data - A pointer to pointer to amd_p2p_info entries + * allocated by get_pages() call. + * + * \return 0 if operation was successful + */ +static int rdma_put_pages(struct amd_p2p_info **p_p2p_data) +{ + struct rdma_p2p_data *p2p_data = + container_of(*p_p2p_data, struct rdma_p2p_data, p2p_info); + int r; + + r = amd_dma_unmap(p2p_data->p2p_info.pages, + p2p_data->p2p_info.priv, + NULL); + if (r) + return r; + amd_put_pages(p2p_data->p2p_info.pages, + p2p_data->p2p_info.priv); + amd_release(p2p_data->p2p_info.priv); + kfree(p2p_data); + + *p_p2p_data = NULL; + + return 0; +} + +/** + * Check if given address belongs to GPU address space. + * + * \param address - Address to check + * \param pid - Process to which given address belongs. + * Could be NULL if current one. + * + * \return 0 - This is not GPU address managed by AMD driver + * 1 - This is GPU address managed by AMD driver + */ +static int rdma_is_gpu_address(uint64_t address, struct pid *pid) +{ + struct kfd_bo *buf_obj; + struct kfd_process *p; + + p = kfd_lookup_process_by_pid(pid); + if (!p) { + pr_debug("Could not find the process\n"); + return 0; + } + + buf_obj = kfd_process_find_bo_from_interval(p, address, address); + + kfd_unref_process(p); + if (!buf_obj) + return 0; + + return 1; +} + +/** + * Return the single page size to be used when building scatter/gather table + * for given range. + * + * \param address - Address + * \param length - Range length + * \param pid - Process id structure. Could be NULL if current one. + * \param page_size - On return: Page size + * + * \return 0 if operation was successful + */ +static int rdma_get_page_size(uint64_t address, uint64_t length, + struct pid *pid, unsigned long *page_size) +{ + /* + * As local memory is always consecutive, we can assume the local + * memory page size to be arbitrary. + * Currently we assume the local memory page size to be the same + * as system memory, which is 4KB. + */ + *page_size = PAGE_SIZE; + + return 0; +} + +/** + * Singleton object: rdma interface function pointers + */ +static const struct amd_rdma_interface rdma_ops = { + .get_pages = rdma_get_pages, + .put_pages = rdma_put_pages, + .is_gpu_address = rdma_is_gpu_address, + .get_page_size = rdma_get_page_size +}; + +/** + * amdkfd_query_rdma_interface - Return interface (function pointers table) for + * rdma interface + * + * + * \param interace - OUT: Pointer to interface + * + * \return 0 if operation was successful. + */ +int amdkfd_query_rdma_interface(const struct amd_rdma_interface **ops) +{ + *ops = &rdma_ops; + + return 0; +} +EXPORT_SYMBOL(amdkfd_query_rdma_interface); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 8aea58c6c062c..cceb016f28bd6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -386,7 +386,6 @@ struct kfd_bo { void *mem; struct interval_tree_node it; struct kfd_dev *dev; - struct list_head cb_data_head; struct kfd_ipc_obj *kfd_ipc_obj; /* page-aligned VA address */ uint64_t cpuva; @@ -1575,6 +1574,10 @@ int kfd_send_exception_to_runtime(struct kfd_process *p, uint64_t error_reason); bool kfd_is_locked(struct kfd_dev *kfd); +/* PeerDirect support */ +void kfd_init_peer_direct(void); +void kfd_close_peer_direct(void); + /* IPC Support */ int kfd_ipc_init(void); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index b6ea295f5af0e..db5b93b2c7a7d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1007,7 +1007,8 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) peer_pdd->dev->kgd, buf_obj->mem, peer_pdd->drm_priv); } - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, mem, + run_rdma_free_callback(buf_obj); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, buf_obj->mem, pdd->drm_priv, NULL); kfd_process_device_remove_obj_handle(pdd, id); } @@ -1582,6 +1583,10 @@ static struct kfd_process *create_process(const struct task_struct *thread) kfd_unref_process(process); get_task_struct(process->lead_thread); + /* If PeerDirect interface was not detected try to detect it again + * in case if network driver was loaded later. + */ + kfd_init_peer_direct(); INIT_WORK(&process->debug_event_workarea, debug_event_write_work_handler); return process; @@ -1812,8 +1817,6 @@ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, buf_obj->cpuva = cpuva; buf_obj->mem_type = mem_type; - INIT_LIST_HEAD(&buf_obj->cb_data_head); - handle = idr_alloc(&pdd->alloc_idr, buf_obj, 0, 0, GFP_KERNEL); if (handle < 0) diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources index 3470a58a43676..a1b74441203de 100644 --- a/drivers/gpu/drm/amd/dkms/sources +++ b/drivers/gpu/drm/amd/dkms/sources @@ -24,6 +24,7 @@ include/drm/gpu_scheduler.h include/drm/ include/drm/amd_asic_type.h include/drm/ include/drm/spsc_queue.h include/drm/ include/uapi/linux/kfd_ioctl.h include/uapi/linux/ +include/drm/amd_rdma.h include/drm/ drivers/dma-buf/dma-resv.c amd/amdkcl/dma-buf/ include/linux/dma-resv.h include/linux/ include/kcl/reservation.h include/linux/ diff --git a/include/drm/amd_rdma.h b/include/drm/amd_rdma.h new file mode 100644 index 0000000000000..99682afae6754 --- /dev/null +++ b/include/drm/amd_rdma.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2015-2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* @file This file defined kernel interfaces to communicate with amdkfd */ + +#ifndef AMD_RDMA_H_ +#define AMD_RDMA_H_ + +/* API versions: + * 1.0 Original API until ROCm 4.1, AMD_RDMA_MAJOR/MINOR undefined + * 2.0 Added IOMMU (dma-mapping) support, removed p2p_info.kfd_proc + * Introduced AMD_RDMA_MAJOR/MINOR version definition + */ +#define AMD_RDMA_MAJOR 2 +#define AMD_RDMA_MINOR 0 + +/** + * Structure describing information needed to P2P access from another device + * to specific location of GPU memory + */ +struct amd_p2p_info { + uint64_t va; /**< Specify user virt. address + * which this page table + * described + */ + uint64_t size; /**< Specify total size of + * allocation + */ + struct pid *pid; /**< Specify process pid to which + * virtual address belongs + */ + struct sg_table *pages; /**< Specify DMA/Bus addresses */ + void *priv; /**< Pointer set by AMD kernel + * driver + */ +}; + +/** + * Structure providing function pointers to support rdma/p2p requirements. + * to specific location of GPU memory + */ +struct amd_rdma_interface { + int (*get_pages)(uint64_t address, uint64_t length, struct pid *pid, + struct device *dma_dev, + struct amd_p2p_info **amd_p2p_data, + void (*free_callback)(void *client_priv), + void *client_priv); + int (*put_pages)(struct amd_p2p_info **amd_p2p_data); + int (*is_gpu_address)(uint64_t address, struct pid *pid); + int (*get_page_size)(uint64_t address, uint64_t length, struct pid *pid, + unsigned long *page_size); +}; + + +int amdkfd_query_rdma_interface(const struct amd_rdma_interface **rdma); + + +#endif /* AMD_RDMA_H_ */ From 05a27724418fbfdd01e8729a78b07a8f87182f1b Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 02:34:11 -0400 Subject: [PATCH 0260/2653] drm/amdkfd: Add module param to enable privileged queues This is useful for profiler prototyping in user mode. Change-Id: Ibb3dfedc698fadb5164637642bdd2d540cc00bd0 Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++++++ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 4 ++++ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 3 +++ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 4 +++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 +++++ 5 files changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 559000216598b..132dd82799c93 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -864,6 +864,14 @@ MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = defa int amdgpu_no_queue_eviction_on_vm_fault; MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); + +/** + * DOC: priv_cp_queues (int) + * Enable privileged mode for CP queues. Default value: 0 (off) + */ +int priv_cp_queues; +module_param(priv_cp_queues, int, 0644); +MODULE_PARM_DESC(priv_cp_queues, "Enable privileged mode for CP queues (0 = off (default), 1 = on)"); #endif /** diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index 05f3ac2eaef9e..457e8fdc46418 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -31,6 +31,7 @@ #include "cik_regs.h" #include "cik_structs.h" #include "oss/oss_2_4_sh_mask.h" +#include "gca/gfx_7_2_sh_mask.h" static inline struct cik_mqd *get_mqd(void *mqd) { @@ -199,6 +200,9 @@ static void __update_mqd(struct mqd_manager *mm, void *mqd, if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_pq_control |= NO_UPDATE_RPTR; + if (priv_cp_queues) + m->cp_hqd_pq_control |= + 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT; update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index 97933d2a38032..e743b69f3e983 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -301,6 +301,9 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_doorbell_control |= 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; } + if (priv_cp_queues) + m->cp_hqd_pq_control |= + 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT; if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) m->cp_hqd_ctx_save_control = 0; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index c1fafc5025158..55387793985f3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -225,7 +225,9 @@ static void __update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT; } - + if (priv_cp_queues) + m->cp_hqd_pq_control |= + 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT; if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) m->cp_hqd_ctx_save_control = atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT | diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index cceb016f28bd6..158d8aa2b2d08 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -181,6 +181,11 @@ extern int debug_largebar; /* Set sh_mem_config.retry_disable on GFX v9 */ extern int amdgpu_noretry; +/* + * Enable privileged mode for all CP queues including user queues + */ +extern int priv_cp_queues; + /* Halt if HWS hang is detected */ extern int halt_if_hws_hang; From 3fdab97c5baace5dd2aeb35e8c5333b9d521663f Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 02:48:26 -0400 Subject: [PATCH 0261/2653] drm/amdkfd: Leave idle processes evicted This feature allows leaving processes with idle user mode queues evicted. That way more memory can be used by other processes. This is contolled by a module parameter. It's disabled by default. It needs more rigorous testing before enabling it by default. See FIXMEs below. The basic idea is to detect idle user mode queues when a process is restored after eviction. It it's found to be idle, we unmap the doorbells so the next submission from the host causes a page fault. We catch the page fault and use that to restore the process memory and the doorbells at that time. FIXME: Add check_queue_idle functions in kfd_mqd_manager_v10.c FIXME: Use READ_ONCE/WRITE_ONCE for vma->vm_private_data Change-Id: I03969b82f8fa31ac0e8593f537cc5c45ff8bc16e Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 + .../drm/amd/amdkfd/kfd_device_queue_manager.c | 25 +++ .../drm/amd/amdkfd/kfd_device_queue_manager.h | 2 + drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 145 +++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h | 3 +- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 28 ++++ .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 47 ++++++ .../gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 43 ++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 22 +++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 93 +++++++++++ 10 files changed, 411 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 132dd82799c93..67e82a1752c0d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -872,6 +872,14 @@ module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_evictio int priv_cp_queues; module_param(priv_cp_queues, int, 0644); MODULE_PARM_DESC(priv_cp_queues, "Enable privileged mode for CP queues (0 = off (default), 1 = on)"); + +/** + * DOC: keep_idle_process_evicted (bool) + * Keep an evicted process evicted if it is idle. Default value: false (off) + */ +bool keep_idle_process_evicted; +module_param(keep_idle_process_evicted, bool, 0444); +MODULE_PARM_DESC(keep_idle_process_evicted, "Restore evicted process only if queues are active (N = off(default), Y = on)"); #endif /** diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index ed6d0ef6a57bf..209ec90f7a925 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -156,6 +156,31 @@ void program_sh_mem_settings(struct device_queue_manager *dqm, qpd->sh_mem_bases, xcc_id); } +bool check_if_queues_active(struct device_queue_manager *dqm, + struct qcm_process_device *qpd) +{ + bool busy = false; + struct queue *q; + + dqm_lock(dqm); + list_for_each_entry(q, &qpd->queues_list, list) { + struct mqd_manager *mqd_mgr; + enum KFD_MQD_TYPE type; + + type = get_mqd_type_from_queue_type(q->properties.type); + mqd_mgr = dqm->mqd_mgrs[type]; + if (!mqd_mgr || !mqd_mgr->check_queue_active) + continue; + + busy = mqd_mgr->check_queue_active(q); + if (busy) + break; + } + dqm_unlock(dqm); + + return busy; +} + static void kfd_hws_hang(struct device_queue_manager *dqm) { struct device_process_node *cur; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 74a61b5b2f0b4..5a003901d94ba 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -306,6 +306,8 @@ unsigned int get_queues_per_pipe(struct device_queue_manager *dqm); unsigned int get_pipes_per_mec(struct device_queue_manager *dqm); unsigned int get_num_sdma_queues(struct device_queue_manager *dqm); unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm); +bool check_if_queues_active(struct device_queue_manager *dqm, + struct qcm_process_device *qpd); int reserve_debug_trap_vmid(struct device_queue_manager *dqm, struct qcm_process_device *qpd); int release_debug_trap_vmid(struct device_queue_manager *dqm, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index 05c74887fd6fd..cc97f392c90af 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -103,11 +103,121 @@ void kfd_doorbell_fini(struct kfd_dev *kfd) (void **)&kfd->doorbell_kernel_ptr); } +static void kfd_doorbell_open(struct vm_area_struct *vma) +{ + /* Don't track the parent's PDD in a child process. We do set + * VM_DONTCOPY, but that can be overridden from user mode. + */ + vma->vm_private_data = NULL; +} + +static void kfd_doorbell_close(struct vm_area_struct *vma) +{ + struct kfd_process_device *pdd = vma->vm_private_data; + + if (!pdd) + return; + + mutex_lock(&pdd->qpd.doorbell_lock); + pdd->qpd.doorbell_vma = NULL; + /* Remember if the process was evicted without doorbells + * mapped to user mode. + */ + if (pdd->qpd.doorbell_mapped == 0) + pdd->qpd.doorbell_mapped = -1; + mutex_unlock(&pdd->qpd.doorbell_lock); +} + +static vm_fault_t kfd_doorbell_vm_fault(struct vm_fault *vmf) +{ + struct kfd_process_device *pdd = vmf->vma->vm_private_data; + + if (!pdd) + return VM_FAULT_SIGBUS; + + pr_debug("Process %d doorbell vm page fault\n", pdd->process->pasid); + + kfd_process_remap_doorbells_locked(pdd->process); + + kfd_process_schedule_restore(pdd->process); + + return VM_FAULT_NOPAGE; +} + +static const struct vm_operations_struct kfd_doorbell_vm_ops = { + .open = kfd_doorbell_open, + .close = kfd_doorbell_close, + .fault = kfd_doorbell_vm_fault, +}; + +void kfd_doorbell_unmap_locked(struct kfd_process_device *pdd) +{ + struct kfd_process *process = pdd->process; + struct vm_area_struct *vma; + size_t size; + + vma = pdd->qpd.doorbell_vma; + /* Remember if the process was evicted without doorbells + * mapped to user mode. + */ + if (!vma) { + pdd->qpd.doorbell_mapped = -1; + return; + } + + pr_debug("Process %d unmapping doorbell 0x%lx\n", + process->pasid, vma->vm_start); + + size = kfd_doorbell_process_slice(pdd->dev); + zap_vma_ptes(vma, vma->vm_start, size); + pdd->qpd.doorbell_mapped = 0; +} + +void kfd_doorbell_unmap(struct kfd_process_device *pdd) +{ + mutex_lock(&pdd->qpd.doorbell_lock); + kfd_doorbell_unmap_locked(pdd); + mutex_unlock(&pdd->qpd.doorbell_lock); +} + +int kfd_doorbell_remap(struct kfd_process_device *pdd) +{ + struct kfd_process *process = pdd->process; + phys_addr_t address; + struct vm_area_struct *vma; + size_t size; + int ret = 0; + + mutex_lock(&pdd->qpd.doorbell_lock); + if (pdd->qpd.doorbell_mapped != 0) + goto out_unlock; + + /* Calculate physical address of doorbell */ + address = kfd_get_process_doorbells(pdd); + vma = pdd->qpd.doorbell_vma; + size = kfd_doorbell_process_slice(pdd->dev); + + pr_debug("Process %d remap doorbell 0x%lx\n", process->pasid, + vma->vm_start); + + ret = vm_iomap_memory(vma, address, size); + if (ret) + pr_err("Process %d failed to remap doorbell 0x%lx\n", + process->pasid, vma->vm_start); + +out_unlock: + pdd->qpd.doorbell_mapped = 1; + mutex_unlock(&pdd->qpd.doorbell_lock); + + return ret; +} + int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, struct vm_area_struct *vma) { phys_addr_t address; struct kfd_process_device *pdd; + int ret; /* * For simplicitly we only allow mapping of the entire doorbell @@ -129,20 +239,47 @@ int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); - pr_debug("Mapping doorbell page\n" + pr_debug("Process %d mapping doorbell page\n" " target user address == 0x%08llX\n" " physical address == 0x%08llX\n" " vm_flags == 0x%04lX\n" " size == 0x%04lX\n", - (unsigned long long) vma->vm_start, address, vma->vm_flags, - kfd_doorbell_process_slice(dev->kfd)); + process->pasid, (unsigned long long) vma->vm_start, + address, vma->vm_flags, kfd_doorbell_process_slice(dev)); + pdd = kfd_get_process_device_data(dev, process); + if (WARN_ON_ONCE(!pdd)) + return 0; - return io_remap_pfn_range(vma, + mutex_lock(&pdd->qpd.doorbell_lock); + + ret = io_remap_pfn_range(vma, vma->vm_start, address >> PAGE_SHIFT, kfd_doorbell_process_slice(dev->kfd), vma->vm_page_prot); + + if (!ret && keep_idle_process_evicted) { + vma->vm_ops = &kfd_doorbell_vm_ops; + vma->vm_private_data = pdd; + pdd->qpd.doorbell_vma = vma; + + /* If process is evicted before the first queue is created, + * process will be restored by the page fault when the + * doorbell is accessed the first time + */ + if (pdd->qpd.doorbell_mapped == -1) { + pr_debug("Process %d evicted, unmapping doorbell\n", + process->pasid); + kfd_doorbell_unmap_locked(pdd); + } else { + pdd->qpd.doorbell_mapped = 1; + } + } + + mutex_unlock(&pdd->qpd.doorbell_lock); + + return ret; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h index 17cc1f25c8d08..876cc71473293 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h @@ -102,6 +102,8 @@ struct mqd_manager { u32 *ctl_stack_used_size, u32 *save_area_used_size); + bool (*check_queue_active)(struct queue *q); + void (*get_checkpoint_info)(struct mqd_manager *mm, void *mqd, uint32_t *ctl_stack_size); void (*checkpoint_mqd)(struct mqd_manager *mm, @@ -115,7 +117,6 @@ struct mqd_manager { const void *mqd_src, const void *ctl_stack_src, const u32 ctl_stack_size); - #if defined(CONFIG_DEBUG_FS) int (*debugfs_show_mqd)(struct seq_file *m, void *data); #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index 457e8fdc46418..64adbde8648af 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -43,6 +43,31 @@ static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) return (struct cik_sdma_rlc_registers *)mqd; } +static bool check_sdma_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + struct cik_sdma_rlc_registers *m = get_sdma_mqd(q->mqd); + + rptr = m->sdma_rlc_rb_rptr; + wptr = m->sdma_rlc_rb_wptr; + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + + return (rptr != wptr); +} + +static bool check_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + struct cik_mqd *m = get_mqd(q->mqd); + + rptr = m->cp_hqd_pq_rptr; + wptr = m->cp_hqd_pq_wptr; + + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + + return (rptr != wptr); +} + static void update_cu_mask(struct mqd_manager *mm, void *mqd, struct mqd_update_info *minfo) { @@ -407,6 +432,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->checkpoint_mqd = checkpoint_mqd; mqd->restore_mqd = restore_mqd; mqd->mqd_size = sizeof(struct cik_mqd); @@ -422,6 +448,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_hiq; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct cik_mqd); mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) @@ -451,6 +478,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_sdma; mqd->destroy_mqd = kfd_destroy_mqd_sdma; mqd->is_occupied = kfd_is_occupied_sdma; + mqd->check_queue_active = check_sdma_queue_active; mqd->checkpoint_mqd = checkpoint_mqd_sdma; mqd->restore_mqd = restore_mqd_sdma; mqd->mqd_size = sizeof(struct cik_sdma_rlc_registers); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index e743b69f3e983..b6a282f96bfd9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -59,6 +59,49 @@ static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) return (struct v9_sdma_mqd *)mqd; } +static bool check_sdma_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + uint32_t rptr_hi, wptr_hi; + struct v9_sdma_mqd *m = get_sdma_mqd(q->mqd); + + rptr = m->sdmax_rlcx_rb_rptr; + wptr = m->sdmax_rlcx_rb_wptr; + rptr_hi = m->sdmax_rlcx_rb_rptr_hi; + wptr_hi = m->sdmax_rlcx_rb_wptr_hi; + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + pr_debug("rptr_hi=%d, wptr_hi=%d\n", rptr_hi, wptr_hi); + + return (rptr != wptr || rptr_hi != wptr_hi); +} + +static bool check_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + uint32_t cntl_stack_offset, cntl_stack_size; + struct v9_mqd *m = get_mqd(q->mqd); + + rptr = m->cp_hqd_pq_rptr; + wptr = m->cp_hqd_pq_wptr_lo % q->properties.queue_size; + cntl_stack_offset = m->cp_hqd_cntl_stack_offset; + cntl_stack_size = m->cp_hqd_cntl_stack_size; + + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + pr_debug("m->cp_hqd_cntl_stack_offset=0x%08x\n", cntl_stack_offset); + pr_debug("m->cp_hqd_cntl_stack_size=0x%08x\n", cntl_stack_size); + + if ((rptr == 0 && wptr == 0) || + cntl_stack_offset == 0xffffffff || + cntl_stack_size > 0x5000) + return false; + + /* Process is idle if both conditions are meet: + * queue's rptr equals to wptr + * control stack is empty, cntl_stack_offset = cntl_stack_size + */ + return (rptr != wptr || cntl_stack_offset != cntl_stack_size); +} + static void update_cu_mask(struct mqd_manager *mm, void *mqd, struct mqd_update_info *minfo, uint32_t inst) { @@ -908,6 +951,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, mqd->allocate_mqd = allocate_mqd; mqd->free_mqd = kfd_free_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->get_checkpoint_info = get_checkpoint_info; mqd->checkpoint_mqd = checkpoint_mqd; mqd->mqd_size = sizeof(struct v9_mqd); @@ -938,6 +982,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, mqd->free_mqd = free_mqd_hiq_sdma; mqd->update_mqd = update_mqd; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct v9_mqd); mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) @@ -966,6 +1011,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct v9_mqd); #if defined(CONFIG_DEBUG_FS) mqd->debugfs_show_mqd = debugfs_show_mqd; @@ -979,6 +1025,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_sdma; mqd->destroy_mqd = kfd_destroy_mqd_sdma; mqd->is_occupied = kfd_is_occupied_sdma; + mqd->check_queue_active = check_sdma_queue_active; mqd->checkpoint_mqd = checkpoint_mqd_sdma; mqd->restore_mqd = restore_mqd_sdma; mqd->mqd_size = sizeof(struct v9_sdma_mqd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index 55387793985f3..23669e908d504 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -45,6 +45,45 @@ static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd) return (struct vi_sdma_mqd *)mqd; } +static bool check_sdma_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + struct vi_sdma_mqd *m = get_sdma_mqd(q->mqd); + + rptr = m->sdmax_rlcx_rb_rptr; + wptr = m->sdmax_rlcx_rb_wptr; + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + + return (rptr != wptr); +} + +static bool check_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + uint32_t cntl_stack_offset, cntl_stack_size; + struct vi_mqd *m = get_mqd(q->mqd); + + rptr = m->cp_hqd_pq_rptr; + wptr = m->cp_hqd_pq_wptr; + cntl_stack_offset = m->cp_hqd_cntl_stack_offset; + cntl_stack_size = m->cp_hqd_cntl_stack_size; + + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + pr_debug("m->cp_hqd_cntl_stack_offset=0x%08x\n", cntl_stack_offset); + pr_debug("m->cp_hqd_cntl_stack_size=0x%08x\n", cntl_stack_size); + + if ((rptr == 0 && wptr == 0) || + cntl_stack_offset == 0xffffffff || + cntl_stack_size > 0x5000) + return false; + + /* Process is idle if both conditions are meet: + * queue's rptr equals to wptr + * control stack is empty, cntl_stack_offset = cntl_stack_size + */ + return (rptr != wptr || cntl_stack_offset != cntl_stack_size); +} + static void update_cu_mask(struct mqd_manager *mm, void *mqd, struct mqd_update_info *minfo) { @@ -463,6 +502,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; mqd->get_wave_state = get_wave_state; + mqd->check_queue_active = check_queue_active; mqd->get_checkpoint_info = get_checkpoint_info; mqd->checkpoint_mqd = checkpoint_mqd; mqd->restore_mqd = restore_mqd; @@ -479,6 +519,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_hiq; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct vi_mqd); mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) @@ -494,6 +535,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_hiq; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct vi_mqd); mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) @@ -508,6 +550,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_sdma; mqd->destroy_mqd = kfd_destroy_mqd_sdma; mqd->is_occupied = kfd_is_occupied_sdma; + mqd->check_queue_active = check_sdma_queue_active; mqd->checkpoint_mqd = checkpoint_mqd_sdma; mqd->restore_mqd = restore_mqd_sdma; mqd->mqd_size = sizeof(struct vi_sdma_mqd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 158d8aa2b2d08..b1a40a1f45f8d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -200,6 +200,11 @@ extern int queue_preemption_timeout_ms; */ extern int amdgpu_no_queue_eviction_on_vm_fault; +/* + * Restore evicted process only if queues are active + */ +extern bool keep_idle_process_evicted; + /* Enable eviction debug messages */ extern bool debug_evictions; @@ -727,6 +732,17 @@ struct qcm_process_device { /* bitmap for dynamic doorbell allocation from the bo */ unsigned long *doorbell_bitmap; + /* doorbell user mmap vma */ + struct vm_area_struct *doorbell_vma; + /* lock to serialize doorbell unmap and remap */ + struct mutex doorbell_lock; + + /* Indicate if doorbell is mapped or unmapped + * -1 means doorbells need to be unmapped because queue is evicted + * 0 means doorbells are unmapped + * 1 means doorbells are mapped + */ + int doorbell_mapped; }; /* KFD Memory Eviction */ @@ -738,6 +754,9 @@ struct qcm_process_device { /* Approx. time before evicting the process again */ #define PROCESS_ACTIVE_TIME_MS 10 +void kfd_process_schedule_restore(struct kfd_process *p); +int kfd_process_remap_doorbells_locked(struct kfd_process *p); + /* 8 byte handle containing GPU ID in the most significant 4 bytes and * idr_handle in the least significant 4 bytes */ @@ -976,6 +995,7 @@ struct kfd_process { * restored after an eviction */ unsigned long last_restore_timestamp; + unsigned long last_evict_timestamp; /* Indicates device process is debug attached with reserved vmid. */ bool debug_trap_enabled; @@ -1141,6 +1161,8 @@ int kfd_doorbell_init(struct kfd_dev *kfd); void kfd_doorbell_fini(struct kfd_dev *kfd); int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, struct vm_area_struct *vma); +void kfd_doorbell_unmap(struct kfd_process_device *pdd); +int kfd_doorbell_remap(struct kfd_process_device *pdd); void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, unsigned int *doorbell_off); void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index db5b93b2c7a7d..8dc9307f8cad0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1075,6 +1075,7 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) get_order(KFD_CWSR_TBA_TMA_SIZE)); idr_destroy(&pdd->alloc_idr); + mutex_destroy(&pdd->qpd.doorbell_lock); kfd_free_process_doorbells(pdd->dev->kfd, pdd); @@ -1638,6 +1639,7 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, pdd->qpd.pqm = &p->pqm; pdd->qpd.evicted = 0; pdd->qpd.mapped_gws_queue = false; + mutex_init(&pdd->qpd.doorbell_lock); pdd->process = p; pdd->bound = PDD_UNBOUND; pdd->already_dequeued = false; @@ -2085,6 +2087,95 @@ static int signal_eviction_fence(struct kfd_process *p) return ret; } +void kfd_process_schedule_restore(struct kfd_process *p) +{ + int ret; + unsigned long evicted_jiffies; + unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_RESTORE_TIME_MS); + + /* wait at least PROCESS_RESTORE_TIME_MS before attempting to restore + */ + evicted_jiffies = get_jiffies_64() - p->last_evict_timestamp; + if (delay_jiffies > evicted_jiffies) + delay_jiffies -= evicted_jiffies; + else + delay_jiffies = 0; + + pr_debug("Process %d schedule restore work\n", p->pasid); + ret = queue_delayed_work(kfd_restore_wq, &p->restore_work, + delay_jiffies); + WARN(!ret, "Schedule restore work failed\n"); +} + +static void kfd_process_unmap_doorbells(struct kfd_process *p) +{ + struct kfd_process_device *pdd; + struct mm_struct *mm = p->mm; + + mmap_write_lock(mm); + + list_for_each_entry(pdd, &p->per_device_data, per_device_list) + kfd_doorbell_unmap(pdd); + + mmap_write_unlock(mm); +} + +int kfd_process_remap_doorbells_locked(struct kfd_process *p) +{ + struct kfd_process_device *pdd; + int ret = 0; + + list_for_each_entry(pdd, &p->per_device_data, per_device_list) + ret = kfd_doorbell_remap(pdd); + + return ret; +} + +static int kfd_process_remap_doorbells(struct kfd_process *p) +{ + struct mm_struct *mm = p->mm; + int ret = 0; + + mmap_write_lock(mm); + ret = kfd_process_remap_doorbells_locked(p); + mmap_write_unlock(mm); + + return ret; +} + +/** + * kfd_process_unmap_doorbells_if_idle - Check if queues are active + * + * Returns true if queues are idle, and unmap doorbells. + * Returns false if queues are active + */ +static bool kfd_process_unmap_doorbells_if_idle(struct kfd_process *p) +{ + struct kfd_process_device *pdd; + bool busy = false; + + if (!keep_idle_process_evicted) + return false; + + /* Unmap doorbell first to avoid race conditions. Otherwise while the + * second queue is checked, the first queue may get more work, but we + * won't detect that since it has been checked + */ + kfd_process_unmap_doorbells(p); + + list_for_each_entry(pdd, &p->per_device_data, per_device_list) { + busy = check_if_queues_active(pdd->qpd.dqm, &pdd->qpd); + if (busy) + break; + } + + /* Remap doorbell if process queue is not idle */ + if (busy) + kfd_process_remap_doorbells(p); + + return !busy; +} + static void evict_process_worker(struct work_struct *work) { int ret; @@ -2098,6 +2189,8 @@ static void evict_process_worker(struct work_struct *work) */ p = container_of(dwork, struct kfd_process, eviction_work); + p->last_evict_timestamp = get_jiffies_64(); + pr_debug("Started evicting process pid %d\n", p->lead_thread->pid); ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_TTM); if (!ret) { From 4dc74e1e52beae19d2c42169d27eadde147cafaa Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 03:06:45 -0400 Subject: [PATCH 0262/2653] drm/amdgpu: Workaround incorrect VRAM width reported on Fiji Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 5 +++++ include/uapi/drm/amdgpu_drm.h | 2 ++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index c5e2a2c41e065..ded48f11dc0ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -555,6 +555,11 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) break; } adev->gmc.vram_width = numchan * chansize; + /* FIXME: The above calculation is outdated. + * For HBM provide a temporary fix + */ + if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) + adev->gmc.vram_width = AMDGPU_VRAM_TYPE_HBM_WIDTH; } /* size in MB on si */ tmp = RREG32(mmCONFIG_MEMSIZE); diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 99638a56e7d92..b2c06f61448fa 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -1445,6 +1445,8 @@ struct drm_amdgpu_info_vbios { #define AMDGPU_VRAM_TYPE_LPDDR5 12 #define AMDGPU_VRAM_TYPE_HBM3E 13 +#define AMDGPU_VRAM_TYPE_HBM_WIDTH 4096 + struct drm_amdgpu_info_device { /** PCI Device ID */ __u32 device_id; From 16355729adc298ce96691f0b2e96867025e39968 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 03:14:27 -0400 Subject: [PATCH 0263/2653] drm/amdkfd: Proof of concept for KFD traces Add tracing to a few KFD functions as a proof of concept. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/Makefile | 1 + drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 7 ++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 10 ++ drivers/gpu/drm/amd/amdkfd/kfd_trace.c | 26 ++++ drivers/gpu/drm/amd/amdkfd/kfd_trace.h | 151 +++++++++++++++++++++++ 5 files changed, 195 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_trace.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_trace.h diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index d4b73964998d0..6c776f5dfd481 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -60,6 +60,7 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_crat.o \ $(AMDKFD_PATH)/kfd_peerdirect.o \ $(AMDKFD_PATH)/kfd_ipc.o \ + $(AMDKFD_PATH)/kfd_trace.o \ $(AMDKFD_PATH)/kfd_debug.o ifneq ($(CONFIG_DEBUG_FS),) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index e277aba3007d6..ea4a43faa2155 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -40,6 +40,8 @@ #include "kfd_device_queue_manager.h" #include "kfd_svm.h" #include "kfd_ipc.h" +#include "kfd_trace.h" + #include "amdgpu_amdkfd.h" #include "kfd_smi_events.h" #include "amdgpu_dma_buf.h" @@ -1259,6 +1261,7 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, int i; uint32_t *devices_arr = NULL; + trace_kfd_map_memory_to_gpu_start(p); if (!args->n_devices) { pr_debug("Device IDs array empty\n"); return -EINVAL; @@ -1352,6 +1355,8 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, } kfree(devices_arr); + trace_kfd_map_memory_to_gpu_end(p, + args->n_devices * sizeof(*devices_arr), "Success"); return err; get_process_device_data_failed: @@ -1362,6 +1367,8 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, mutex_unlock(&p->mutex); copy_from_user_failed: kfree(devices_arr); + trace_kfd_map_memory_to_gpu_end(p, + args->n_devices * sizeof(*devices_arr), "Failed"); return err; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 8dc9307f8cad0..e10ea2f569daf 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -43,6 +43,7 @@ struct mm_struct; #include "kfd_priv.h" #include "kfd_device_queue_manager.h" #include "kfd_svm.h" +#include "kfd_trace.h" #include "kfd_smi_events.h" #include "kfd_debug.h" @@ -2188,6 +2189,7 @@ static void evict_process_worker(struct work_struct *work) * lifetime of this thread, kfd_process p will be valid */ p = container_of(dwork, struct kfd_process, eviction_work); + trace_kfd_evict_process_worker_start(p); p->last_evict_timestamp = get_jiffies_64(); @@ -2206,6 +2208,7 @@ static void evict_process_worker(struct work_struct *work) pr_debug("Finished evicting process pid %d\n", p->lead_thread->pid); } else pr_err("Failed to evict queues of process pid %d\n", p->lead_thread->pid); + trace_kfd_evict_process_worker_end(p, ret ? "Failed" : "Success"); } static int restore_process_helper(struct kfd_process *p) @@ -2221,6 +2224,7 @@ static int restore_process_helper(struct kfd_process *p) } ret = kfd_process_restore_queues(p); + trace_kfd_restore_process_worker_end(p, ret ? "Failed" : "Success"); if (!ret) pr_debug("Finished restoring process pid %d\n", p->lead_thread->pid); @@ -2244,6 +2248,7 @@ static void restore_process_worker(struct work_struct *work) */ p = container_of(dwork, struct kfd_process, restore_work); pr_debug("Started restoring process pasid %d\n", (int)p->lead_thread->pid); + trace_kfd_restore_process_worker_start(p); /* Setting last_restore_timestamp before successful restoration. * Otherwise this would have to be set by KGD (restore_process_bos) @@ -2264,6 +2269,11 @@ static void restore_process_worker(struct work_struct *work) if (mod_delayed_work(kfd_restore_wq, &p->restore_work, msecs_to_jiffies(PROCESS_RESTORE_TIME_MS))) kfd_process_restore_queues(p); + trace_kfd_restore_process_worker_end(p, ret ? + "Rescheduled restore" : + "Failed to reschedule restore"); + } else { + trace_kfd_restore_process_worker_end(p, "Success"); } } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_trace.c b/drivers/gpu/drm/amd/amdkfd/kfd_trace.c new file mode 100644 index 0000000000000..805a1da90bb15 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_trace.c @@ -0,0 +1,26 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + + +#define CREATE_TRACE_POINTS +#include "kfd_trace.h" diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_trace.h b/drivers/gpu/drm/amd/amdkfd/kfd_trace.h new file mode 100644 index 0000000000000..5d27a98055377 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_trace.h @@ -0,0 +1,151 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#if !defined(_AMDKFD_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _KFD_TRACE_H_ + + +#include +#include +#include + +#include "kfd_priv.h" +#include + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM amdkfd +#define TRACE_INCLUDE_FILE kfd_trace + + +TRACE_EVENT(kfd_map_memory_to_gpu_start, + TP_PROTO(struct kfd_process *p), + TP_ARGS(p), + TP_STRUCT__entry( + __field(unsigned int, pasid) + ), + TP_fast_assign( + __entry->pasid = p->pasid; + ), + TP_printk("pasid =%u", __entry->pasid) +); + + +TRACE_EVENT(kfd_map_memory_to_gpu_end, + TP_PROTO(struct kfd_process *p, u32 array_size, char *pStatusMsg), + TP_ARGS(p, array_size, pStatusMsg), + TP_STRUCT__entry( + __field(unsigned int, pasid) + __field(unsigned int, array_size) + __string(pStatusMsg, pStatusMsg) + ), + TP_fast_assign( + __entry->pasid = p->pasid; + __entry->array_size = array_size; + __assign_str(pStatusMsg, pStatusMsg); + ), + TP_printk("pasid = %u, array_size = %u, StatusMsg=%s", + __entry->pasid, + __entry->array_size, + __get_str(pStatusMsg)) +); + + +TRACE_EVENT(kfd_kgd2kfd_schedule_evict_and_restore_process, + TP_PROTO(struct kfd_process *p, u32 delay_jiffies), + TP_ARGS(p, delay_jiffies), + TP_STRUCT__entry( + __field(unsigned int, pasid) + __field(unsigned int, delay_jiffies) + ), + TP_fast_assign( + __entry->pasid = p->pasid; + __entry->delay_jiffies = delay_jiffies; + ), + TP_printk("pasid = %u, delay_jiffies = %u", + __entry->pasid, + __entry->delay_jiffies) +); + + +TRACE_EVENT(kfd_evict_process_worker_start, + TP_PROTO(struct kfd_process *p), + TP_ARGS(p), + TP_STRUCT__entry( + __field(unsigned int, pasid) + ), + TP_fast_assign( + __entry->pasid = p->pasid; + ), + TP_printk("pasid=%u", __entry->pasid) +); + + +TRACE_EVENT(kfd_evict_process_worker_end, + TP_PROTO(struct kfd_process *p, char *pStatusMsg), + TP_ARGS(p, pStatusMsg), + TP_STRUCT__entry( + __field(unsigned int, pasid) + __string(pStatusMsg, pStatusMsg) + ), + TP_fast_assign( + __entry->pasid = p->pasid; + __assign_str(pStatusMsg, pStatusMsg); + ), + TP_printk("pasid=%u, StatusMsg=%s", + __entry->pasid, __get_str(pStatusMsg)) +); + + +TRACE_EVENT(kfd_restore_process_worker_start, + TP_PROTO(struct kfd_process *p), + TP_ARGS(p), + TP_STRUCT__entry( + __field(unsigned int, pasid) + ), + TP_fast_assign( + __entry->pasid = p->pasid; + ), + TP_printk("pasid=%u", __entry->pasid) +); + +TRACE_EVENT(kfd_restore_process_worker_end, + TP_PROTO(struct kfd_process *p, char *pStatusMsg), + TP_ARGS(p, pStatusMsg), + TP_STRUCT__entry( + __field(unsigned int, pasid) + __string(pStatusMsg, pStatusMsg) + ), + TP_fast_assign( + entry->pasid = p->pasid; + __assign_str(pStatusMsg, pStatusMsg); + ), + TP_printk("pasid=%u, StatusMsg=%s", + __entry->pasid, __get_str(pStatusMsg)) +); + +#endif + +/* This part must be outside protection */ +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#include From 2d48c2ac6669365a8731e5a96a2028b37ef9004d Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 03:53:39 -0400 Subject: [PATCH 0264/2653] drm/amdkfd: Mapping foreign device memory to GPUVM This adds the possibility to map foreign device memory as a userptr. This assumes that the foreign memory is pinned an cannot be evicted or migrated. This is generally true for doorbells. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 25 +++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index ea4a43faa2155..25b35e7272612 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1062,6 +1062,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, long err; uint64_t offset = args->mmap_offset; uint32_t flags = args->flags; + struct vm_area_struct *vma; uint64_t cpuva = 0; unsigned int mem_type = 0; @@ -1122,7 +1123,29 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, goto err_unlock; } - if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { + if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { + /* Check if the userptr corresponds to another (or third-party) + * device local memory. If so treat is as a doorbell. User + * space will be oblivious of this and will use this doorbell + * BO as a regular userptr BO + */ + vma = find_vma(current->mm, args->mmap_offset); + if (vma && (vma->vm_flags & VM_IO)) { + unsigned long pfn; + + follow_pfn(vma, args->mmap_offset, &pfn); + flags |= KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL; + flags &= ~KFD_IOC_ALLOC_MEM_FLAGS_USERPTR; + offset = (pfn << PAGE_SHIFT); + } else { + if (offset & (PAGE_SIZE - 1)) { + pr_debug("Unaligned userptr address:%llx\n", + offset); + return -EINVAL; + } + cpuva = offset; + } + } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { if (args->size != kfd_doorbell_process_slice(dev->kfd)) { err = -EINVAL; goto err_unlock; From 2f0b47372b38d0b6b80851a3064fb7be308e154b Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 04:00:12 -0400 Subject: [PATCH 0265/2653] drm/amdkfd: Experimental support for architectures w/o ACPI Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index 4a7180b46b719..87494915f4fba 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -1873,8 +1873,6 @@ static int kfd_fill_iolink_info_for_cpu(int numa_node_id, int *avail_size, static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) { struct crat_header *crat_table = (struct crat_header *)pcrat_image; - struct acpi_table_header *acpi_table; - acpi_status status; struct crat_subtype_generic *sub_type_hdr; int avail_size = *size; int numa_node_id; @@ -1882,6 +1880,10 @@ static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) uint32_t entries = 0; #endif int ret = 0; +#ifdef CONFIG_ACPI + struct acpi_table_header *acpi_table; + acpi_status status; +#endif if (!pcrat_image) return -EINVAL; @@ -1898,6 +1900,7 @@ static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) sizeof(crat_table->signature)); crat_table->length = sizeof(struct crat_header); +#ifdef CONFIG_ACPI status = acpi_get_table("DSDT", 0, &acpi_table); if (status != AE_OK) pr_warn("DSDT table not found for OEM information\n"); @@ -1909,6 +1912,11 @@ static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) CRAT_OEMTABLEID_LENGTH); acpi_put_table(acpi_table); } +#else + crat_table->oem_revision = 0; + memcpy(crat_table->oem_id, "INV", CRAT_OEMID_LENGTH); + memcpy(crat_table->oem_table_id, "UNAVAIL", CRAT_OEMTABLEID_LENGTH); +#endif crat_table->total_entries = 0; crat_table->num_domains = 0; From 96ec2a0724b55b339c7911d816980da9dc6a25e5 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 04:07:48 -0400 Subject: [PATCH 0266/2653] drm/amdkfd: Report used GPU memory This change has been rejected upstream. A better solution is needed. Used memory being dynamic doesn't belong in the topology tree, which contains otherwise static information. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 44 +++++++++++++++++++---- drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 3 +- 2 files changed, 40 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 4ec73f33535eb..a2e4e18c7a18d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -206,6 +206,8 @@ struct kfd_topology_device *kfd_create_topology_device( sysfs_show_gen_prop(buffer, offs, "%s %llu\n", name, value) #define sysfs_show_32bit_val(buffer, offs, value) \ sysfs_show_gen_prop(buffer, offs, "%u\n", value) +#define sysfs_show_64bit_val(buffer, offs, value) \ + sysfs_show_gen_prop(buffer, offs, "%llu\n", value) #define sysfs_show_str_val(buffer, offs, value) \ sysfs_show_gen_prop(buffer, offs, "%s\n", value) @@ -295,11 +297,25 @@ static ssize_t mem_show(struct kobject *kobj, struct attribute *attr, { int offs = 0; struct kfd_mem_properties *mem; + uint64_t used_mem; /* Making sure that the buffer is an empty string */ buffer[0] = 0; - mem = container_of(attr, struct kfd_mem_properties, attr); + if (strcmp(attr->name, "used_memory") == 0) { + mem = container_of(attr, struct kfd_mem_properties, + attr_used); + if (mem->gpu) { + if (kfd_devcgroup_check_permission(mem->gpu)) + return -EPERM; + used_mem = amdgpu_amdkfd_get_vram_usage(mem->gpu->kgd); + return sysfs_show_64bit_val(buffer, offs, used_mem); + } + /* TODO: Report APU/CPU-allocated memory; For now return 0 */ + return 0; + } + + mem = container_of(attr, struct kfd_mem_properties, attr_props); if (mem->gpu && kfd_devcgroup_check_permission(mem->gpu)) return -EPERM; sysfs_show_32bit_prop(buffer, offs, "heap_type", mem->heap_type); @@ -602,7 +618,12 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) if (dev->kobj_mem) { list_for_each_entry(mem, &dev->mem_props, list) if (mem->kobj) { - kfd_remove_sysfs_file(mem->kobj, &mem->attr); + /* TODO: Remove when CPU/APU supported */ + if (dev->node_props.cpu_cores_count == 0) + sysfs_remove_file(mem->kobj, + &mem->attr_used); + kfd_remove_sysfs_file(mem->kobj, + &mem->attr_props); mem->kobj = NULL; } kobject_del(dev->kobj_mem); @@ -713,12 +734,23 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, return ret; } - mem->attr.name = "properties"; - mem->attr.mode = KFD_SYSFS_FILE_MODE; - sysfs_attr_init(&mem->attr); - ret = sysfs_create_file(mem->kobj, &mem->attr); + mem->attr_props.name = "properties"; + mem->attr_props.mode = KFD_SYSFS_FILE_MODE; + sysfs_attr_init(&mem->attr_props); + ret = sysfs_create_file(mem->kobj, &mem->attr_props); if (ret < 0) return ret; + + /* TODO: Support APU/CPU memory usage */ + if (dev->node_props.cpu_cores_count == 0) { + mem->attr_used.name = "used_memory"; + mem->attr_used.mode = KFD_SYSFS_FILE_MODE; + sysfs_attr_init(&mem->attr_used); + ret = sysfs_create_file(mem->kobj, &mem->attr_used); + if (ret < 0) + return ret; + } + i++; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index 3de8ec0043bb4..ab7a3bf1bdefe 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -92,7 +92,8 @@ struct kfd_mem_properties { uint32_t mem_clk_max; struct kfd_node *gpu; struct kobject *kobj; - struct attribute attr; + struct attribute attr_props; + struct attribute attr_used; }; #define CACHE_SIBLINGMAP_SIZE 128 From 3658bbc7957e742770b66eb1b9365905d6b81405 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 2 Oct 2019 14:01:27 +0200 Subject: [PATCH 0267/2653] drm/amdgpu: work around llvm bug #42576 Code in the amdgpu driver triggers a bug when using clang to build an arm64 kernel: /tmp/sdma_v4_0-f95fd3.s: Assembler messages: /tmp/sdma_v4_0-f95fd3.s:44: Error: selected processor does not support `bfc w0,#1,#5' I expect this to be fixed in llvm soon, but we can also work around it by inserting a barrier() that prevents the optimization. Link: https://bugs.llvm.org/show_bug.cgi?id=42576 Signed-off-by: Arnd Bergmann Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index f38004e6064e5..919de02efb0ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1068,6 +1068,7 @@ static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) /* Set ring buffer size in dwords */ uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); + barrier(); /* work around https://bugs.llvm.org/show_bug.cgi?id=42576 */ rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); #ifdef __BIG_ENDIAN rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); From ddf00658ea1bcbf708051bcb39595418268dbca0 Mon Sep 17 00:00:00 2001 From: changzhu Date: Fri, 12 Jul 2019 15:53:23 +0800 Subject: [PATCH 0268/2653] Revert "drm/amdgpu: don't invalidate caches in RELEASE_MEM, only do the writeback" Signed-off-by: changzhu --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 506454ed27bde..352bb7f10aef4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -8722,7 +8722,11 @@ static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | PACKET3_RELEASE_MEM_GCR_GL2_WB | - PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ + PACKET3_RELEASE_MEM_GCR_GL2_INV | + PACKET3_RELEASE_MEM_GCR_GL2_US | + PACKET3_RELEASE_MEM_GCR_GL1_INV | + PACKET3_RELEASE_MEM_GCR_GLV_INV | + PACKET3_RELEASE_MEM_GCR_GLM_INV | PACKET3_RELEASE_MEM_GCR_GLM_WB | PACKET3_RELEASE_MEM_CACHE_POLICY(3) | PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | From 306712456bd188d7d9893d3a90078cc483a1f2f5 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Tue, 24 Mar 2020 12:30:28 -0400 Subject: [PATCH 0269/2653] drm/amdkfd: block queue destroy on suspended queues When debugger is attached, queue destroy requests will be blocked until queues have resumed. Note: the debugger owns suspend_queues and resume_queues so there should be no harm blocking queue destroy until queue resume since gdb can halt CPU threads anyways. Debugger also doesn't wait on application threads since suspend is only briefly called to update_waves before resume so halting queue destroy calls shouldn't deadlock the debugger. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling Signed-off-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index c643e0ccec52b..95710a5064d22 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -548,6 +548,10 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) dqm = pqn->q->device->dqm; retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q); + + if (retval == -ERESTARTSYS) + return retval; + if (retval) { pr_err("Pasid 0x%x destroy queue %d failed, ret %d\n", pdd->pasid, From 5f38f8ae48892e9c709cd7568dc90745556863a7 Mon Sep 17 00:00:00 2001 From: Amber Lin Date: Fri, 24 Apr 2020 16:14:01 -0400 Subject: [PATCH 0270/2653] drm/amdkfd: Distance non-upstream ioctls Create a gap between upstream and non-upstream ioctls so when upstream adds an ioctl, we don't need to bump non-upstream ioctl command number. This can avoid the backwards compatibility in the future though it'll happen at this time. Signed-off-by: Amber Lin Reviewed-by: Felix Kuehling Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 8 ++------ include/uapi/linux/kfd_ioctl.h | 8 ++++++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 25b35e7272612..2eb4f337c06d4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -3325,8 +3325,6 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { kfd_ioctl_ipc_export_handle, 0), }; -#define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) - static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) { struct kfd_process *process; @@ -3339,10 +3337,8 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) int retcode = -EINVAL; bool ptrace_attached = false; - if (nr >= AMDKFD_CORE_IOCTL_COUNT) - goto err_i1; - - if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) { + if (((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) || + ((nr >= AMDKFD_COMMAND_START_2) && (nr < AMDKFD_COMMAND_END_2))) { u32 amdkfd_size; ioctl = &amdkfd_ioctls[nr]; diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index db022f11f934e..8ada6ae7dd78c 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1697,13 +1697,17 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_DBG_TRAP \ AMDKFD_IOWR(0x26, struct kfd_ioctl_dbg_trap_args) +#define AMDKFD_COMMAND_START 0x01 +#define AMDKFD_COMMAND_END 0x27 + +/* non-upstream ioctls */ #define AMDKFD_IOC_IPC_IMPORT_HANDLE \ AMDKFD_IOWR(0x80, struct kfd_ioctl_ipc_import_handle_args) #define AMDKFD_IOC_IPC_EXPORT_HANDLE \ AMDKFD_IOWR(0x81, struct kfd_ioctl_ipc_export_handle_args) -#define AMDKFD_COMMAND_START 0x01 -#define AMDKFD_COMMAND_END 0x27 +#define AMDKFD_COMMAND_START_2 0x80 +#define AMDKFD_COMMAND_END_2 0x84 #endif From 260d69bfdefba0b37cd80ff8da34927e3e260bb6 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Fri, 1 May 2020 10:40:05 -0400 Subject: [PATCH 0271/2653] drm/amdkfd: Fix a race condition getting IPC obj handle reference If an IPC object is being released (zero refcount) don't try to take another reference to it. Signed-off-by: Felix Kuehling Tested-by: Alex Sierra Reviewed-by: Alex Sierra --- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 9 +++++---- drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index 51395a88c12a8..ab05edb3a652a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -88,9 +88,11 @@ static void ipc_obj_release(struct kref *r) kfree(obj); } -void ipc_obj_get(struct kfd_ipc_obj *obj) +struct kfd_ipc_obj *ipc_obj_get(struct kfd_ipc_obj *obj) { - kref_get(&obj->ref); + if (kref_get_unless_zero(&obj->ref)) + return obj; + return NULL; } void ipc_obj_put(struct kfd_ipc_obj **obj) @@ -196,7 +198,7 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, &kfd_ipc_handles.handles[HANDLE_TO_KEY(share_handle)], node) { if (!memcmp(entry->share_handle, share_handle, sizeof(entry->share_handle))) { - found = entry; + found = ipc_obj_get(entry); break; } } @@ -204,7 +206,6 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, if (!found) return -EINVAL; - ipc_obj_get(found); pr_debug("Found ipc_dma_buf: %p\n", found->data); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h index 9ee8627b88b08..a6560eae9ff50 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -45,7 +45,7 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *kfd, struct kfd_process *p, int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, uint64_t handle, uint32_t *ipc_handle); -void ipc_obj_get(struct kfd_ipc_obj *obj); +struct kfd_ipc_obj *ipc_obj_get(struct kfd_ipc_obj *obj); void ipc_obj_put(struct kfd_ipc_obj **obj); #endif /* KFD_IPC_H_ */ From e2aa9be13beffae8148cd38ef575f5af7e2aebab Mon Sep 17 00:00:00 2001 From: "Philip.Cox@amd.com" Date: Wed, 1 Apr 2020 13:37:20 -0400 Subject: [PATCH 0272/2653] drm/amdkfd: Initial gfx9 debug address watch Code for new GFX9 kfd debugger address watch code. -- Adding support for: -- add address watch -- clear address watch Change-Id: I51d6494db6881c02b8fbb56c73cf970389c036fc Signed-off-by: Philip.Cox@amd.com Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index b1a40a1f45f8d..92c468a4a2016 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -370,6 +370,15 @@ struct kfd_dev { /* Compute Profile ref. count */ atomic_t compute_profile; + /* + * A bitmask to indicate which watch points have been allocated. + * bit meaning: + * 0: unallocated/available + * 1: allocated/unavailable + */ + uint32_t allocated_debug_watch_points; + spinlock_t watch_points_lock; + struct ida doorbell_ida; unsigned int max_doorbell_slices; @@ -1612,6 +1621,16 @@ int kfd_ipc_init(void); void kfd_inc_compute_active(struct kfd_node *dev); void kfd_dec_compute_active(struct kfd_node *dev); +/* Allocate and free watch point IDs for debugger */ +int kfd_allocate_debug_watch_point(struct kfd_dev *kfd, + uint64_t watch_address, + uint32_t watch_address_mask, + uint32_t *watch_point, + uint32_t watch_mode, + uint32_t debug_vmid); +int kfd_release_debug_watch_points(struct kfd_dev *kfd, + uint32_t watch_point_bit_mask_to_free); + /* Cgroup Support */ /* Check with device cgroup if @kfd device is accessible */ static inline int kfd_devcgroup_check_permission(struct kfd_node *node) From 0c4d48fc76f5b07c7f8c0a6347cd6cda8c6b1453 Mon Sep 17 00:00:00 2001 From: Joseph Greathouse Date: Tue, 30 Jun 2020 18:40:37 -0500 Subject: [PATCH 0273/2653] drm/amdkfd: Prevent GWS+debugger on buggy firmware Some versions of MEC2 firmware do not correctly handle simultaneously setting up debugging on a process while having a GWS-enabled queue in that process. This could lead to CWSR failure and crashing the kernel driver. Prevent this situation from happening when we are on an affected firmware version by preventing both debugging and GWS-enabled queue from both being enabled at the same time. If the process has a GWS enabled queue, attempting to turn on debugging will fail with -EBUSY. If debugging is already enabled, attempting to create a GWS-enabled queue will fail with -EBUSY. v2: Use qpd.num_gws to track GWS usage, even with suspended queues. Signed-off-by: Joseph Greathouse Reviewed-by: Rajneesh Bhardwaj Reviewed-by: Felix Kuehling Change-Id: Id4f1d12665fa6ac5d5402637cf9361bcb2dbfbc6 --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 ++++++ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 9 +++++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 2eb4f337c06d4..7623d73ba7e6e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1515,6 +1515,12 @@ static int kfd_ioctl_alloc_queue_gws(struct file *filep, goto out_unlock; } + pdd = kfd_bind_process_to_device(dev, p); + if (IS_ERR(pdd)) { + retval = -ESRCH; + goto out_unlock; + } + if (!dev->gws) { retval = -ENODEV; goto out_unlock; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 7e749f9b6d69d..7ae3ea36d25dc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -593,6 +593,15 @@ static int kfd_gws_init(struct kfd_node *node) node->adev->gds.gws_size, &node->gws); } + if ((kfd->device_info->asic_family == CHIP_VEGA10 + && kfd->mec2_fw_version < 0x81b6) + || (kfd->device_info->asic_family >= CHIP_VEGA12 + && kfd->device_info->asic_family <= CHIP_RAVEN + && kfd->mec2_fw_version < 0x1b6) + || (kfd->device_info->asic_family == CHIP_ARCTURUS + && kfd->mec2_fw_version < 0x30)) + kfd->gws_debug_workaround = true; + return ret; } From 33502fb8d448f3d0abfca4acdcf9466f292d1327 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Fri, 26 Jun 2020 22:32:01 -0400 Subject: [PATCH 0274/2653] drm/amdkfd: Move ipc_obj from kfd_bo to kgd_mem This should make IPC easier to upstream. struct kfd_bo does not exist upstream and its main purpose is to support RDMA, which is not upstreamable. struct kgd_mem exists upstream and is a KFD-specific buffer object structure that can be used to store a pointer to the ipc_obj. Adding another one layer of tracking in KFD just for IPC cannot be justified when upstreaming IPC. With this change, some of the IPC functionality moves into amdgpu_amdkfd_gpuvm.c with some calls back to kfd_ipc.c. Cleaned up and exported kfd_ipc_obj_put and kfd_ipc_store_insert. Signed-off-by: Felix Kuehling Acked-and-tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 8 ++- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 39 ++++++++--- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 67 ++++++++----------- drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 12 ++-- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 8 +-- 7 files changed, 75 insertions(+), 65 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index d91e680615c06..3d71fff569daa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -70,6 +70,7 @@ struct kfd_mem_attachment { struct kgd_mem { struct mutex lock; struct amdgpu_bo *bo; + struct kfd_ipc_obj *ipc_obj; struct dma_buf *dmabuf; struct hmm_range *range; struct list_head attachments; @@ -346,6 +347,7 @@ void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, struct dma_buf *dmabuf, + struct kfd_ipc_obj *ipc_obj, uint64_t va, void *drm_priv, struct kgd_mem **mem, uint64_t *size, uint64_t *mmap_offset); @@ -355,9 +357,9 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, uint64_t *mmap_offset); int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, struct dma_buf **dmabuf); -int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_dev *kgd, void *vm, - struct kgd_mem *mem, - struct dma_buf **dmabuf); +int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, + struct kgd_mem *mem, + struct kfd_ipc_obj **ipc_obj); void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev); int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 7248bd9f482a8..895ff89716cb5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -35,6 +35,7 @@ #include "amdgpu_hmm.h" #include "amdgpu_amdkfd.h" #include "amdgpu_dma_buf.h" +#include "kfd_ipc.h" #include #include "amdgpu_xgmi.h" #include "kfd_priv.h" @@ -1939,6 +1940,9 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( *size = 0; } + /* Unreference the ipc_obj if applicable */ + kfd_ipc_obj_put(&mem->ipc_obj); + /* Free the BO*/ drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv); drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle); @@ -2561,6 +2565,7 @@ static int import_obj_create(struct amdgpu_device *adev, get_dma_buf(dma_buf); (*mem)->dmabuf = dma_buf; (*mem)->bo = bo; + (*mem)->ipc_obj = ipc_obj; (*mem)->va = va; (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) && !adev->apu_prefer_gtt ? @@ -2643,22 +2648,40 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, return ret; } -int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_dev *kgd, void *vm, - struct kgd_mem *mem, - struct dma_buf **dmabuf) +int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, + struct kgd_mem *mem, + struct kfd_ipc_obj **ipc_obj) { struct amdgpu_device *adev = NULL; + struct dma_buf *dmabuf; + int r = 0; - if (!dmabuf || !kgd || !vm || !mem) + if (!kgd || !vm || !mem) return -EINVAL; adev = get_amdgpu_device(kgd); + mutex_lock(&mem->lock); - *dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base, 0); - if (IS_ERR(*dmabuf)) - return -EINVAL; + if (mem->ipc_obj) { + *ipc_obj = mem->ipc_obj; + goto unlock_out; + } - return 0; + dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base, 0); + if (IS_ERR(dmabuf)) { + r = PTR_ERR(dmabuf); + goto unlock_out; + } + + r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj); + if (r) + dma_buf_put(dmabuf); + else + *ipc_obj = mem->ipc_obj; + +unlock_out: + mutex_unlock(&mem->lock); + return r; } /* Evict a userptr BO by stopping the queues if necessary diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 7623d73ba7e6e..fe0272c46030f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1181,7 +1181,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); idr_handle = kfd_process_device_create_obj_handle(pdd, mem, - args->va_addr, args->size, cpuva, mem_type, NULL); + args->va_addr, args->size, cpuva, mem_type); if (idr_handle < 0) { err = -EFAULT; goto err_free; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index ab05edb3a652a..d52e0f38eef1c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -20,7 +20,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include #include #include @@ -42,7 +41,7 @@ static struct kfd_ipc_handles { */ #define HANDLE_TO_KEY(sh) ((*(uint64_t *)sh) & KFD_IPC_HASH_TABLE_SIZE_MASK) -static int ipc_store_insert(void *val, void *sh, struct kfd_ipc_obj **ipc_obj) +int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj) { struct kfd_ipc_obj *obj; @@ -58,11 +57,9 @@ static int ipc_store_insert(void *val, void *sh, struct kfd_ipc_obj **ipc_obj) * storage happens at ipc_obj release time. */ kref_init(&obj->ref); - obj->data = val; + obj->dmabuf = dmabuf; get_random_bytes(obj->share_handle, sizeof(obj->share_handle)); - memcpy(sh, obj->share_handle, sizeof(obj->share_handle)); - mutex_lock(&kfd_ipc_handles.lock); hlist_add_head(&obj->node, &kfd_ipc_handles.handles[HANDLE_TO_KEY(obj->share_handle)]); @@ -84,21 +81,23 @@ static void ipc_obj_release(struct kref *r) hash_del(&obj->node); mutex_unlock(&kfd_ipc_handles.lock); - dma_buf_put(obj->data); + dma_buf_put(obj->dmabuf); kfree(obj); } -struct kfd_ipc_obj *ipc_obj_get(struct kfd_ipc_obj *obj) +static struct kfd_ipc_obj *ipc_obj_get(struct kfd_ipc_obj *obj) { if (kref_get_unless_zero(&obj->ref)) return obj; return NULL; } -void ipc_obj_put(struct kfd_ipc_obj **obj) +void kfd_ipc_obj_put(struct kfd_ipc_obj **obj) { - kref_put(&(*obj)->ref, ipc_obj_release); - *obj = NULL; + if (*obj) { + kref_put(&(*obj)->ref, ipc_obj_release); + *obj = NULL; + } } int kfd_ipc_init(void) @@ -110,10 +109,10 @@ int kfd_ipc_init(void) static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, struct kfd_process *p, - uint32_t gpu_id, struct dma_buf *dmabuf, + uint32_t gpu_id, + struct dma_buf *dmabuf, struct kfd_ipc_obj *ipc_obj, uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset, - struct kfd_ipc_obj *ipc_obj) + uint64_t *mmap_offset) { int r; void *mem; @@ -135,7 +134,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, goto err_unlock; } - r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf, + r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf, ipc_obj, va_addr, pdd->vm, (struct kgd_mem **)&mem, &size, mmap_offset); @@ -143,8 +142,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, goto err_unlock; idr_handle = kfd_process_device_create_obj_handle(pdd, mem, - va_addr, size, 0, 0, - ipc_obj); + va_addr, size, 0, 0); if (idr_handle < 0) { r = -EFAULT; goto err_free; @@ -175,9 +173,8 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *dev, if (!dmabuf) return -EINVAL; - r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, dmabuf, - va_addr, handle, mmap_offset, - NULL); + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, dmabuf, NULL, + va_addr, handle, mmap_offset); dma_buf_put(dmabuf); return r; } @@ -207,18 +204,18 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, if (!found) return -EINVAL; - pr_debug("Found ipc_dma_buf: %p\n", found->data); + pr_debug("Found ipc_dma_buf: %p\n", found->dmabuf); - r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, found->data, - va_addr, handle, mmap_offset, - found); + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, + found->dmabuf, found, + va_addr, handle, mmap_offset); if (r) goto error_unref; return r; error_unref: - ipc_obj_put(&found); + kfd_ipc_obj_put(&found); return r; } @@ -226,9 +223,9 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, uint64_t handle, uint32_t *ipc_handle) { struct kfd_process_device *pdd = NULL; - struct kfd_ipc_obj *obj; + struct kfd_ipc_obj *ipc_obj; struct kfd_bo *kfd_bo = NULL; - struct dma_buf *dmabuf; + struct kgd_mem *mem; int r; if (!dev || !ipc_handle) @@ -249,23 +246,15 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, pr_err("Failed to get bo"); return -EINVAL; } - if (kfd_bo->kfd_ipc_obj) { - memcpy(ipc_handle, kfd_bo->kfd_ipc_obj->share_handle, - sizeof(kfd_bo->kfd_ipc_obj->share_handle)); - return 0; - } - - r = amdgpu_amdkfd_gpuvm_export_dmabuf(dev->kgd, pdd->vm, - (struct kgd_mem *)kfd_bo->mem, - &dmabuf); - if (r) - return r; + mem = (struct kgd_mem *)kfd_bo->mem; - r = ipc_store_insert(dmabuf, ipc_handle, &obj); + r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->kgd, pdd->vm, mem, + &ipc_obj); if (r) return r; - kfd_bo->kfd_ipc_obj = obj; + memcpy(ipc_handle, ipc_obj->share_handle, + sizeof(ipc_obj->share_handle)); return r; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h index a6560eae9ff50..72fe8e4af2e5c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -25,12 +25,16 @@ #define KFD_IPC_H_ #include -#include "kfd_priv.h" +#include + +/* avoid including kfd_priv.h */ +struct kfd_dev; +struct kfd_process; struct kfd_ipc_obj { struct hlist_node node; struct kref ref; - void *data; + struct dma_buf *dmabuf; uint32_t share_handle[4]; }; @@ -45,7 +49,7 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *kfd, struct kfd_process *p, int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, uint64_t handle, uint32_t *ipc_handle); -struct kfd_ipc_obj *ipc_obj_get(struct kfd_ipc_obj *obj); -void ipc_obj_put(struct kfd_ipc_obj **obj); +int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj); +void kfd_ipc_obj_put(struct kfd_ipc_obj **obj); #endif /* KFD_IPC_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 92c468a4a2016..be2e87f4a5005 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -405,7 +405,6 @@ struct kfd_bo { void *mem; struct interval_tree_node it; struct kfd_dev *dev; - struct kfd_ipc_obj *kfd_ipc_obj; /* page-aligned VA address */ uint64_t cpuva; unsigned int mem_type; @@ -1137,8 +1136,7 @@ int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process, int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, void *mem, uint64_t start, uint64_t length, uint64_t cpuva, - unsigned int mem_type, - struct kfd_ipc_obj *ipc_obj); + unsigned int mem_type); void *kfd_process_device_translate_handle(struct kfd_process_device *p, int handle); struct kfd_bo *kfd_process_device_find_bo(struct kfd_process_device *pdd, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index e10ea2f569daf..bc8cf2190e44e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -32,7 +32,6 @@ #include #include #include -#include "kfd_ipc.h" #include #include "amdgpu_amdkfd.h" #include "amdgpu.h" @@ -1796,8 +1795,7 @@ struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev, int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, void *mem, uint64_t start, uint64_t length, uint64_t cpuva, - unsigned int mem_type, - struct kfd_ipc_obj *ipc_obj) + unsigned int mem_type) { int handle; struct kfd_bo *buf_obj; @@ -1816,7 +1814,6 @@ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, buf_obj->mem = mem; buf_obj->dev = pdd->dev; - buf_obj->kfd_ipc_obj = ipc_obj; buf_obj->cpuva = cpuva; buf_obj->mem_type = mem_type; @@ -1892,9 +1889,6 @@ void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, buf_obj = kfd_process_device_find_bo(pdd, handle); - if (buf_obj->kfd_ipc_obj) - ipc_obj_put(&buf_obj->kfd_ipc_obj); - idr_remove(&pdd->alloc_idr, handle); interval_tree_remove(&buf_obj->it, &p->bo_interval_tree); From a21753a6287c8f1acf20d32dcf7b6cb8b127dfcf Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Fri, 20 Mar 2020 17:07:06 +0800 Subject: [PATCH 0275/2653] drm/amdgpu: move csa to the lower gmc hole location Move csa to the lower gmc hole location as the cp firmware starting from Navi1x firmware can't well handle the address of upper gmc hole space. Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c index 02138aa557935..a096fe34a8a16 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c @@ -28,9 +28,13 @@ uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev) { - uint64_t addr = AMDGPU_VA_RESERVED_CSA_START(adev); - - addr = amdgpu_gmc_sign_extend(addr); + uint64_t addr; + if (adev->asic_type >= CHIP_NAVI10) { + addr = AMDGPU_VA_RESERVED_CSA_SIZE - AMDGPU_CSA_SIZE; + } else { + addr = AMDGPU_VA_RESERVED_CSA_START(adev); + addr = amdgpu_gmc_sign_extend(addr); + } return addr; } From aafd34c91bb479fd15908286d3e65ef2c5cf55d2 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 7 Oct 2020 14:14:28 -0400 Subject: [PATCH 0276/2653] drm/amdkfd: Catch failures from follow_pfn This fixes uninitialized, out-of-range physical addresses being programmed into the GPUVM page table in some corner cases. Signed-off-by: Felix Kuehling Acked-by: Oak Zeng --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index fe0272c46030f..71bf9991a28ca 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1133,7 +1133,11 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, if (vma && (vma->vm_flags & VM_IO)) { unsigned long pfn; - follow_pfn(vma, args->mmap_offset, &pfn); + err = follow_pfn(vma, args->mmap_offset, &pfn); + if (err) { + pr_debug("Failed to get PFN: %ld\n", err); + return err; + } flags |= KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL; flags &= ~KFD_IOC_ALLOC_MEM_FLAGS_USERPTR; offset = (pfn << PAGE_SHIFT); From b286e642bdadca92ac1af439eb6f4942764fd787 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 26 Oct 2020 18:40:58 -0400 Subject: [PATCH 0277/2653] drm/amdkfd: correctly check find_vma success Check that find_vma actually found a VM that matches the address we're looking for. If there is no such VMA, don't try to create an IO mapping. Instead a regular userptr mapping will be created, and is expected to fail later in get_user_pages. Signed-off-by: Felix Kuehling Reviewed-by: Oak Zeng --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 71bf9991a28ca..8e936ee89bb8e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1130,7 +1130,8 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, * BO as a regular userptr BO */ vma = find_vma(current->mm, args->mmap_offset); - if (vma && (vma->vm_flags & VM_IO)) { + if (vma && args->mmap_offset >= vma->vm_start && + (vma->vm_flags & VM_IO)) { unsigned long pfn; err = follow_pfn(vma, args->mmap_offset, &pfn); From 6e01041ae520990a7460ed0d693f70b0779c1465 Mon Sep 17 00:00:00 2001 From: Gang Ba Date: Sat, 31 Oct 2020 20:43:28 -0400 Subject: [PATCH 0278/2653] drm/amdkfd: Create P2P links Create p2p links for peer accessible devices Change-Id: I6cd52e43cba99224bca0eac7b01f29311912185b Signed-off-by: Gang Ba --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index a2e4e18c7a18d..be83f739fc6aa 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -579,6 +579,18 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) struct kfd_mem_properties *mem; struct kfd_perf_properties *perf; + if (dev->kobj_p2plink) { + list_for_each_entry(p2plink, &dev->p2p_link_props, list) + if (p2plink->kobj) { + kfd_remove_sysfs_file(p2plink->kobj, + &p2plink->attr); + p2plink->kobj = NULL; + } + kobject_del(dev->kobj_p2plink); + kobject_put(dev->kobj_p2plink); + dev->kobj_p2plink = NULL; + } + if (dev->kobj_iolink) { list_for_each_entry(iolink, &dev->io_link_props, list) if (iolink->kobj) { From 01732e48d68f48b285c037af712b2ec4d0cc7378 Mon Sep 17 00:00:00 2001 From: Gang Ba Date: Wed, 21 Oct 2020 16:00:55 -0400 Subject: [PATCH 0279/2653] drm/amdgpu: allow function to allocate normal GTT memory amdgpu_amdkfd_alloc_gtt_mem currently allocates USWC memory. It uses write-combining for CPU access, which is slow for reading. Add a new parameter to amdgpu_amdkfd_alloc_gtt_mem to allocate normal GTT memory. Signed-off-by: Gang Ba Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 7 +++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +- 6 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 3b1240271410b..a274a937d8bab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -311,7 +311,7 @@ void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, void **mem_obj, uint64_t *gpu_addr, - void **cpu_ptr, bool cp_mqd_gfx9) + void **cpu_ptr, bool cp_mqd_gfx9, bool is_uswc_mode) { struct amdgpu_bo *bo = NULL; struct amdgpu_bo_param bp; @@ -322,7 +322,10 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, bp.size = size; bp.byte_align = PAGE_SIZE; bp.domain = AMDGPU_GEM_DOMAIN_GTT; - bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; + if (is_uswc_mode) + bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; + else + bp.flags = 0; bp.type = ttm_bo_type_kernel; bp.resv = NULL; bp.bo_ptr_size = sizeof(struct amdgpu_bo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 3d71fff569daa..1aa9e4462aab7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -237,7 +237,7 @@ int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, /* Shared API */ int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, void **mem_obj, uint64_t *gpu_addr, - void **cpu_ptr, bool mqd_gfx9); + void **cpu_ptr, bool mqd_gfx9, bool is_uswc_mode); void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj); int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, void **mem_obj); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 7ae3ea36d25dc..65da9b382c32b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -816,7 +816,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, if (amdgpu_amdkfd_alloc_gtt_mem( kfd->adev, size, &kfd->gtt_mem, &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, - false)) { + false, true)) { dev_err(kfd_device, "Could not allocate %d bytes\n", size); goto alloc_gtt_mem_failure; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 209ec90f7a925..ef7615279ac9b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -2922,7 +2922,7 @@ static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm) retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size, &(mem_obj->gtt_mem), &(mem_obj->gpu_addr), - (void *)&(mem_obj->cpu_ptr), false); + (void *)&(mem_obj->cpu_ptr), false, true); return retval; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index b6a282f96bfd9..e1fa4ed32215d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -184,7 +184,7 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, NUM_XCC(node->xcc_mask), &(mqd_mem_obj->gtt_mem), &(mqd_mem_obj->gpu_addr), - (void *)&(mqd_mem_obj->cpu_ptr), true); + (void *)&(mqd_mem_obj->cpu_ptr), true, true); if (retval) { kfree(mqd_mem_obj); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 95710a5064d22..c58fe0e4bbcdc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -372,7 +372,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, &pdd->proc_ctx_bo, &pdd->proc_ctx_gpu_addr, &pdd->proc_ctx_cpu_ptr, - false); + false, true); if (retval) { dev_err(dev->adev->dev, "failed to allocate process context bo\n"); return retval; From 7391b05105bcb01a50d026fbc4b04ee1303b975d Mon Sep 17 00:00:00 2001 From: Gang Ba Date: Wed, 21 Oct 2020 17:10:42 -0400 Subject: [PATCH 0280/2653] drm/amd: Add Stream Performance Counter Monitors Driver Add Driver code for user to control GPU Stream Performance Counter Monitor and dump the Sample data to measure the GPU performance. Change-Id: Id10682e05ec3fc7456bcd8b25241686e42353462 Signed-off-by: Gang Ba Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/Makefile | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 9 + .../drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 104 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 11 + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 135 +++++ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 137 +++++- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 127 +++++ drivers/gpu/drm/amd/amdkfd/Makefile | 1 + drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 10 + drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 12 + drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 462 ++++++++++++++++++ include/uapi/linux/kfd_ioctl.h | 81 ++- 12 files changed, 1088 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_spm.c diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 6a54652b95b05..abd04072d204a 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -274,7 +274,8 @@ amdgpu-y += \ amdgpu_amdkfd_gfx_v10.o \ amdgpu_amdkfd_gfx_v10_3.o \ amdgpu_amdkfd_gfx_v11.o \ - amdgpu_amdkfd_gfx_v12.o + amdgpu_amdkfd_gfx_v12.o \ + amdgpu_amdkfd_rlc_spm.o ifneq ($(CONFIG_DRM_AMDGPU_CIK),) amdgpu-y += amdgpu_amdkfd_gfx_v7.o diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 1aa9e4462aab7..b3be72ed70373 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -418,6 +418,14 @@ void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) } #endif +void amdgpu_amdkfd_rlc_spm_cntl(struct kgd_dev *kgd, bool cntl); +int amdgpu_amdkfd_rlc_spm(struct kgd_dev *kgd, void *args); +int amdgpu_amdkfd_rlc_spm_acquire(struct kgd_dev *kgd, + struct amdgpu_vm *vm, u64 gpu_addr, u32 size); +void amdgpu_amdkfd_rlc_spm_release(struct kgd_dev *kgd, struct amdgpu_vm *vm); +void amdgpu_amdkfd_rlc_spm_set_rdptr(struct kgd_dev *kgd, u32 rptr); +void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev); + #if IS_ENABLED(CONFIG_HSA_AMD_SVM) int kgd2kfd_init_zone_device(struct amdgpu_device *adev); #else @@ -429,6 +437,7 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev) #endif /* KGD2KFD callbacks */ +void kgd2kfd_spm_interrupt(struct kfd_dev *kfd); int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger); int kgd2kfd_resume_mm(struct mm_struct *mm); int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c new file mode 100644 index 0000000000000..eeaca9d1e02b9 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -0,0 +1,104 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "amdgpu_object.h" +#include "amdgpu_amdkfd.h" +#include +#include "amdgpu_ids.h" + +void amdgpu_amdkfd_rlc_spm_cntl(struct kgd_dev *kgd, bool cntl) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + spin_lock(&adev->gfx.kiq.ring_lock); + amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); + if (cntl) + adev->gfx.spmfuncs->start(adev); + else + adev->gfx.spmfuncs->stop(adev); + amdgpu_ring_commit(kiq_ring); + spin_unlock(&adev->gfx.kiq.ring_lock); +} + +void amdgpu_amdkfd_rlc_spm_set_rdptr(struct kgd_dev *kgd, u32 rptr) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + spin_lock(&adev->gfx.kiq.ring_lock); + amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); + adev->gfx.spmfuncs->set_rdptr(adev, rptr); + amdgpu_ring_commit(kiq_ring); + spin_unlock(&adev->gfx.kiq.ring_lock); +} + +int amdgpu_amdkfd_rlc_spm_acquire(struct kgd_dev *kgd, struct amdgpu_vm *vm, u64 gpu_addr, u32 size) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + int r; + + if (!adev->gfx.rlc.funcs->update_spm_vmid) + return -EINVAL; + + r = amdgpu_vmid_alloc_reserved(adev, vm, AMDGPU_GFXHUB_0); + if (r) + return r; + + /* init spm vmid with 0x0 */ + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0); + + /* set spm ring registers */ + spin_lock(&adev->gfx.kiq.ring_lock); + amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); + adev->gfx.spmfuncs->set_spm_perfmon_ring_buf(adev, gpu_addr, size); + amdgpu_ring_commit(kiq_ring); + spin_unlock(&adev->gfx.kiq.ring_lock); + return r; +} + +void amdgpu_amdkfd_rlc_spm_release(struct kgd_dev *kgd, struct amdgpu_vm *vm) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + /* stop spm stream and interrupt */ + spin_lock(&adev->gfx.kiq.ring_lock); + amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); + adev->gfx.spmfuncs->stop(adev); + amdgpu_ring_commit(kiq_ring); + spin_unlock(&adev->gfx.kiq.ring_lock); + + amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB_0); + + /* revert spm vmid with 0xf */ + if (adev->gfx.rlc.funcs->update_spm_vmid) + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); +} + +void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev) +{ + if (adev->kfd.dev) + kgd2kfd_spm_interrupt(adev->kfd.dev); +} + diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 08f268dab8f51..ca2b3bd4ee559 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -164,6 +164,15 @@ struct amdgpu_kiq { void *mqd_backup; }; +struct spm_funcs { + void (*start)(struct amdgpu_device *adev); + void (*stop)(struct amdgpu_device *adev); + void (*set_rdptr)(struct amdgpu_device *adev, u32 rptr); + void (*set_spm_perfmon_ring_buf)(struct amdgpu_device *adev, u64 gpu_rptr, u32 size); + /* Packet sizes */ + int set_spm_config_size; +}; + /* * GFX configurations */ @@ -414,6 +423,7 @@ struct amdgpu_gfx { struct amdgpu_mec_bitmap mec_bitmap[AMDGPU_MAX_GC_INSTANCES]; struct amdgpu_kiq kiq[AMDGPU_MAX_GC_INSTANCES]; struct amdgpu_imu imu; + const struct spm_funcs *spmfuncs; bool rs64_enable; /* firmware format */ const struct firmware *me_fw; /* ME firmware */ uint32_t me_fw_version; @@ -457,6 +467,7 @@ struct amdgpu_gfx { struct amdgpu_irq_src priv_inst_irq; struct amdgpu_irq_src bad_op_irq; struct amdgpu_irq_src cp_ecc_error_irq; + struct amdgpu_irq_src spm_irq; struct amdgpu_irq_src sq_irq; struct amdgpu_irq_src rlc_gc_fed_irq; struct sq_work sq_work; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 352bb7f10aef4..266382e7713af 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4872,6 +4872,13 @@ static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block) if (r) return r; + /* SPM */ + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_RLC, + GFX_10_1__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT, + &adev->gfx.spm_irq); + if (r) + return r; + /* EOP Event */ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_EOP_INTERRUPT, @@ -7536,6 +7543,7 @@ static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block) amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.spm_irq, 0); /* WA added for Vangogh asic fixing the SMU suspend failure * It needs to set power gating again during gfxoff control @@ -7789,6 +7797,94 @@ static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); } +static void gfx_v10_0_spm_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t data = 0; + + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, 0); + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); + + + data = RREG32_SOC15(GC, 0, mmRLC_SPM_PERFMON_CNTL); + data |= RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK; + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + STRM_PERFMON_STATE_START_COUNTING); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_INT_CNTL), 1); +} + +static void gfx_v10_0_spm_stop(struct amdgpu_device *adev) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t data = 0; + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, PERFMON_STATE, + CP_PERFMON_STATE_STOP_COUNTING); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); +} + +static void gfx_v10_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), rptr); +} + +static void gfx_v10_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, + u64 gpu_addr, u32 size) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, + mmRLC_SPM_PERFMON_RING_BASE_LO), lower_32_bits(gpu_addr)); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, + 0, mmRLC_SPM_PERFMON_RING_BASE_HI), upper_32_bits(gpu_addr)); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_RING_SIZE), size); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_SEGMENT_THRESHOLD), 0xff); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), 0); +} + +static const struct spm_funcs gfx_v10_0_spm_funcs = { + .start = &gfx_v10_0_spm_start, + .stop = &gfx_v10_0_spm_stop, + .set_rdptr = &gfx_v10_0_spm_set_rdptr, + .set_spm_perfmon_ring_buf = &gfx_v10_0_set_spm_perfmon_ring_buf, + .set_spm_config_size = 30, +}; + +static void gfx_v10_0_set_spm_funcs(struct amdgpu_device *adev) +{ + adev->gfx.spmfuncs = &gfx_v10_0_spm_funcs; +} + static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -7820,6 +7916,7 @@ static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block) adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), AMDGPU_MAX_COMPUTE_RINGS); + gfx_v10_0_set_spm_funcs(adev); gfx_v10_0_set_kiq_pm4_funcs(adev); gfx_v10_0_set_ring_funcs(adev); gfx_v10_0_set_irq_funcs(adev); @@ -7842,6 +7939,10 @@ static int gfx_v10_0_late_init(struct amdgpu_ip_block *ip_block) if (r) return r; + r = amdgpu_irq_get(adev, &adev->gfx.spm_irq, 0); + if (r) + return r; + r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); if (r) return r; @@ -9844,6 +9945,32 @@ static void gfx_v10_0_ring_end_use(struct amdgpu_ring *ring) amdgpu_gfx_enforce_isolation_ring_end_use(ring); } +static int gfx_v10_0_spm_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + WREG32_SOC15(GC, 0, mmRLC_SPM_INT_CNTL, 0); + break; + case AMDGPU_IRQ_STATE_ENABLE: + WREG32_SOC15(GC, 0, mmRLC_SPM_INT_CNTL, 1); + break; + default: + break; + } + return 0; +} + +static int gfx_v10_0_spm_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + amdgpu_amdkfd_rlc_spm_interrupt(adev); + return 0; +} + static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { .name = "gfx_v10_0", .early_init = gfx_v10_0_early_init, @@ -10031,6 +10158,11 @@ static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { .process = gfx_v10_0_kiq_irq, }; +static const struct amdgpu_irq_src_funcs gfx_v10_0_spm_irq_funcs = { + .set = gfx_v10_0_spm_set_interrupt_state, + .process = gfx_v10_0_spm_irq, +}; + static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) { adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; @@ -10039,6 +10171,9 @@ static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; + adev->gfx.spm_irq.num_types = 1; + adev->gfx.spm_irq.funcs = &gfx_v10_0_spm_irq_funcs; + adev->gfx.priv_reg_irq.num_types = 1; adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 367449d8061b0..c558ba8f1500f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -1911,6 +1911,12 @@ static int gfx_v8_0_sw_init(struct amdgpu_ip_block *ip_block) adev->gfx.mec.num_pipe_per_mec = 4; adev->gfx.mec.num_queue_per_pipe = 8; + /* SPM */ + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, + VISLANDS30_IV_SRCID_RLC_STRM_PERF_MONITOR, &adev->gfx.spm_irq); + if (r) + return r; + /* EOP Event */ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq); if (r) @@ -4850,6 +4856,7 @@ static int gfx_v8_0_hw_fini(struct amdgpu_ip_block *ip_block) amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.spm_irq, 0); /* disable KCQ to avoid CPC touch memory not valid anymore */ gfx_v8_0_kcq_disable(adev); @@ -5216,6 +5223,97 @@ static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = { .select_me_pipe_q = &gfx_v8_0_select_me_pipe_q }; +static void gfx_v8_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, + bool wc, uint32_t reg, uint32_t val) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | + WRITE_DATA_DST_SEL(0) | + (wc ? WR_CONFIRM : 0)); + amdgpu_ring_write(ring, reg); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, val); +} + +static void gfx_v8_0_spm_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t data = 0; + + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, 0); + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmGRBM_GFX_INDEX, data); + + + data = RREG32(mmRLC_SPM_PERFMON_CNTL); + data |= RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK; + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_PERFMON_CNTL, data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, + SPM_PERFMON_STATE, CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, + SPM_PERFMON_STATE, STRM_PERFMON_STATE_START_COUNTING); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, data); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_INT_CNTL, 1); +} + +static void gfx_v8_0_spm_stop(struct amdgpu_device *adev) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t data = 0; + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, + PERFMON_STATE, CP_PERFMON_STATE_STOP_COUNTING); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, + SPM_PERFMON_STATE, CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, data); +} + +static void gfx_v8_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_RING_RDPTR, rptr); +} + +static void gfx_v8_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, + u64 gpu_addr, u32 size) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, + mmRLC_SPM_PERFMON_RING_BASE_LO, lower_32_bits(gpu_addr)); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, + mmRLC_SPM_PERFMON_RING_BASE_HI, upper_32_bits(gpu_addr)); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, + mmRLC_SPM_PERFMON_RING_SIZE, size); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, + mmRLC_SPM_SEGMENT_THRESHOLD, 0xff); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, 0); +} + +static const struct spm_funcs gfx_v8_0_spm_funcs = { + .start = &gfx_v8_0_spm_start, + .stop = &gfx_v8_0_spm_stop, + .set_rdptr = &gfx_v8_0_spm_set_rdptr, + .set_spm_perfmon_ring_buf = &gfx_v8_0_set_spm_perfmon_ring_buf, + .set_spm_config_size = 30, +}; + +static void gfx_v8_0_set_spm_funcs(struct amdgpu_device *adev) +{ + adev->gfx.spmfuncs = &gfx_v8_0_spm_funcs; +} + static int gfx_v8_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -5225,6 +5323,7 @@ static int gfx_v8_0_early_init(struct amdgpu_ip_block *ip_block) adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), AMDGPU_MAX_COMPUTE_RINGS); adev->gfx.funcs = &gfx_v8_0_gfx_funcs; + gfx_v8_0_set_spm_funcs(adev); gfx_v8_0_set_ring_funcs(adev); gfx_v8_0_set_irq_funcs(adev); gfx_v8_0_set_gds_init(adev); @@ -5265,6 +5364,10 @@ static int gfx_v8_0_late_init(struct amdgpu_ip_block *ip_block) return r; } + r = amdgpu_irq_get(adev, &adev->gfx.spm_irq, 0); + if (r) + return r; + return 0; } @@ -6756,6 +6859,31 @@ static void gfx_v8_0_emit_mem_sync_compute(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ } +static int gfx_v8_0_spm_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + WREG32(mmRLC_SPM_INT_CNTL, 0); + break; + case AMDGPU_IRQ_STATE_ENABLE: + WREG32(mmRLC_SPM_INT_CNTL, 1); + break; + default: + break; + } + return 0; +} + +static int gfx_v8_0_spm_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + amdgpu_amdkfd_rlc_spm_interrupt(adev); + return 0; +} /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ #define mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT 0x0000007f @@ -6813,7 +6941,6 @@ static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable) gfx_v8_0_emit_wave_limit_cs(ring, i, enable); } - } static const struct amd_ip_funcs gfx_v8_0_ip_funcs = { @@ -6980,11 +7107,19 @@ static const struct amdgpu_irq_src_funcs gfx_v8_0_sq_irq_funcs = { .process = gfx_v8_0_sq_irq, }; +static const struct amdgpu_irq_src_funcs gfx_v8_0_spm_irq_funcs = { + .set = gfx_v8_0_spm_set_interrupt_state, + .process = gfx_v8_0_spm_irq, +}; + static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev) { adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs; + adev->gfx.spm_irq.num_types = 1; + adev->gfx.spm_irq.funcs = &gfx_v8_0_spm_irq_funcs; + adev->gfx.priv_reg_irq.num_types = 1; adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index fe951668f61fd..aa3e258d9afb0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2274,6 +2274,13 @@ static int gfx_v9_0_sw_init(struct amdgpu_ip_block *ip_block) adev->gfx.mec.num_pipe_per_mec = 4; adev->gfx.mec.num_queue_per_pipe = 8; + /* SPM */ + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_RLC, + GFX_9_0__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT, + &adev->gfx.spm_irq); + if (r) + return r; + /* EOP Event */ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); if (r) @@ -4053,6 +4060,7 @@ static int gfx_v9_0_hw_fini(struct amdgpu_ip_block *ip_block) if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.spm_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); @@ -4792,6 +4800,87 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) return r; } +static void gfx_v9_0_spm_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t data = 0; + + data = RREG32_SOC15(GC, 0, mmRLC_SPM_PERFMON_CNTL); + data |= RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK; + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + STRM_PERFMON_STATE_START_COUNTING); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_INT_CNTL), 1); +} + +static void gfx_v9_0_spm_stop(struct amdgpu_device *adev) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t data = 0; + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_STOP_COUNTING); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); +} + +static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), rptr); +} + +static void gfx_v9_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, u64 gpu_addr, u32 size) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, + mmRLC_SPM_PERFMON_RING_BASE_LO), lower_32_bits(gpu_addr)); + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, + mmRLC_SPM_PERFMON_RING_BASE_HI), upper_32_bits(gpu_addr)); + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_RING_SIZE), size); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_SEGMENT_THRESHOLD), 0xff); + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), 0); +} + +static const struct spm_funcs gfx_v9_0_spm_funcs = { + .start = &gfx_v9_0_spm_start, + .stop = &gfx_v9_0_spm_stop, + .set_rdptr = &gfx_v9_0_spm_set_rdptr, + .set_spm_perfmon_ring_buf = &gfx_v9_0_set_spm_perfmon_ring_buf, + .set_spm_config_size = 30, +}; + +static void gfx_v9_0_set_spm_funcs(struct amdgpu_device *adev) +{ + adev->gfx.spmfuncs = &gfx_v9_0_spm_funcs; +} + static int gfx_v9_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -4806,6 +4895,7 @@ static int gfx_v9_0_early_init(struct amdgpu_ip_block *ip_block) adev->gfx.xcc_mask = 1; adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), AMDGPU_MAX_COMPUTE_RINGS); + gfx_v9_0_set_spm_funcs(adev); gfx_v9_0_set_kiq_pm4_funcs(adev); gfx_v9_0_set_ring_funcs(adev); gfx_v9_0_set_irq_funcs(adev); @@ -4861,6 +4951,10 @@ static int gfx_v9_0_late_init(struct amdgpu_ip_block *ip_block) if (r) return r; + r = amdgpu_irq_get(adev, &adev->gfx.spm_irq, 0); + if (r) + return r; + r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); if (r) return r; @@ -7102,6 +7196,32 @@ static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ } +static int gfx_v9_0_spm_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + WREG32(mmRLC_SPM_INT_CNTL, 0); + break; + case AMDGPU_IRQ_STATE_ENABLE: + WREG32(mmRLC_SPM_INT_CNTL, 1); + break; + default: + break; + } + return 0; +} + +static int gfx_v9_0_spm_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + amdgpu_amdkfd_rlc_spm_interrupt(adev); + return 0; +} + static void gfx_v9_0_emit_wave_limit_cs(struct amdgpu_ring *ring, uint32_t pipe, bool enable) { @@ -7643,12 +7763,19 @@ static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = { .process = amdgpu_gfx_cp_ecc_error_irq, }; +static const struct amdgpu_irq_src_funcs gfx_v9_0_spm_irq_funcs = { + .set = gfx_v9_0_spm_set_interrupt_state, + .process = gfx_v9_0_spm_irq, +}; static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) { adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; + adev->gfx.spm_irq.num_types = 1; + adev->gfx.spm_irq.funcs = &gfx_v9_0_spm_irq_funcs; + adev->gfx.priv_reg_irq.num_types = 1; adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 6c776f5dfd481..ee40591c23b31 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -61,6 +61,7 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_peerdirect.o \ $(AMDKFD_PATH)/kfd_ipc.o \ $(AMDKFD_PATH)/kfd_trace.o \ + $(AMDKFD_PATH)/kfd_spm.o \ $(AMDKFD_PATH)/kfd_debug.o ifneq ($(CONFIG_DEBUG_FS),) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 8e936ee89bb8e..d22cca786f176 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1831,6 +1831,12 @@ static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) } #endif +static int kfd_ioctl_rlc_spm(struct file *filep, + struct kfd_process *p, void *data) +{ + return kfd_rlc_spm(p, data); +} + static int criu_checkpoint_process(struct kfd_process *p, uint8_t __user *user_priv_data, uint64_t *priv_offset) @@ -3334,6 +3340,10 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_IPC_EXPORT_HANDLE, kfd_ioctl_ipc_export_handle, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, + kfd_ioctl_rlc_spm, 0), + }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index be2e87f4a5005..1044d3f1d8e45 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -370,6 +370,9 @@ struct kfd_dev { /* Compute Profile ref. count */ atomic_t compute_profile; + /*spm process id */ + unsigned int spm_pasid; + /* * A bitmask to indicate which watch points have been allocated. * bit meaning: @@ -835,6 +838,12 @@ struct kfd_process_device { struct attribute attr_sdma; char sdma_filename[MAX_SYSFS_FILENAME_LEN]; + /* spm data */ + struct kfd_spm_cntr *spm_cntr; + struct mutex spm_mutex; + struct work_struct spm_work; + spinlock_t spm_irq_lock; + /* Eviction activity tracking */ uint64_t last_evict_timestamp; atomic64_t evict_duration_counter; @@ -1608,6 +1617,9 @@ int kfd_send_exception_to_runtime(struct kfd_process *p, uint64_t error_reason); bool kfd_is_locked(struct kfd_dev *kfd); +void kfd_spm_init_process_device(struct kfd_process_device *pdd); +int kfd_rlc_spm(struct kfd_process *p, void __user *data); + /* PeerDirect support */ void kfd_init_peer_direct(void); void kfd_close_peer_direct(void); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c new file mode 100644 index 0000000000000..d9856191ab7eb --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -0,0 +1,462 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "kfd_priv.h" +#include "amdgpu_amdkfd.h" +#include "amdgpu_irq.h" +#include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" +#include "ivsrcid/ivsrcid_vislands30.h" +#include // for use_mm() +#include + +struct user_buf { + uint64_t __user *user_addr; + u32 ubufsize; +}; + +struct kfd_spm_cntr { + struct user_buf ubuf; + struct mutex spm_worker_mutex; + u64 gpu_addr; + u32 ring_size; + u32 ring_mask; + u32 ring_rptr; + u32 size_copied; + u32 has_data_loss; + u32 *cpu_addr; + void *spm_obj; + wait_queue_head_t spm_buf_wq; + bool has_user_buf; + bool is_user_buf_filled; + bool is_spm_started; +}; + +static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) +{ + struct kfd_spm_cntr *spm = pdd->spm_cntr; + uint64_t __user *user_address; + uint64_t *ring_buf; + u32 user_buf_space_left; + int ret = 0; + + if (spm->ubuf.user_addr == NULL) + return -EFAULT; + + user_address = (uint64_t *)((uint64_t)spm->ubuf.user_addr + spm->size_copied); + ring_buf = (uint64_t *)((uint64_t)spm->cpu_addr + spm->ring_rptr); + + if (user_address == NULL) + return -EFAULT; + + user_buf_space_left = spm->ubuf.ubufsize - spm->size_copied; + + if (size_to_copy < user_buf_space_left) { + ret = copy_to_user(user_address, ring_buf, size_to_copy); + if (ret) { + spm->has_data_loss = true; + return -EFAULT; + } + spm->size_copied += size_to_copy; + spm->ring_rptr += size_to_copy; + } else { + ret = copy_to_user(user_address, ring_buf, user_buf_space_left); + if (ret) { + spm->has_data_loss = true; + return -EFAULT; + } + + spm->size_copied = spm->ubuf.ubufsize; + spm->ring_rptr += user_buf_space_left; + WRITE_ONCE(spm->is_user_buf_filled, true); + wake_up(&pdd->spm_cntr->spm_buf_wq); + } + + return ret; +} + +static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) +{ + struct kfd_spm_cntr *spm = pdd->spm_cntr; + u32 size_to_copy; + int ret = 0; + u32 ring_wptr; + + ring_wptr = READ_ONCE(spm->cpu_addr[0]) & spm->ring_mask; + + /* keep SPM ring buffer running */ + if (!spm->has_user_buf || spm->is_user_buf_filled) { + spm->ring_rptr = ring_wptr; + spm->has_data_loss = true; + /* set flag due to there is no flag setup + * when read ring buffer timeout. + */ + if (!spm->is_user_buf_filled) + spm->is_user_buf_filled = true; + goto exit; + } + + if (spm->ring_rptr == ring_wptr) + goto exit; + + if ((spm->ring_rptr >= 0) && (spm->ring_rptr < 0x20)) { + /* + * First 8DW, only use for WritePtr, it is not Counter data + */ + spm->ring_rptr = 0x20; + } + + if (ring_wptr > spm->ring_rptr) { + size_to_copy = ring_wptr - spm->ring_rptr; + ret = kfd_spm_data_copy(pdd, size_to_copy); + } else { + size_to_copy = spm->ring_size - spm->ring_rptr; + ret = kfd_spm_data_copy(pdd, size_to_copy); + + /* correct counter start point */ + if (spm->ring_size == spm->ring_rptr) { + if (ring_wptr == 0) { + /* reset rptr to start point of ring buffer */ + spm->ring_rptr = ring_wptr; + goto exit; + } + spm->ring_rptr = 0x20; + size_to_copy = ring_wptr - spm->ring_rptr; + if (!ret) + ret = kfd_spm_data_copy(pdd, size_to_copy); + } + } + +exit: + amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->kgd, spm->ring_rptr); + return ret; +} + +static void kfd_spm_work(struct work_struct *work) +{ + struct kfd_process_device *pdd = container_of(work, struct kfd_process_device, spm_work); + struct mm_struct *mm = NULL; // referenced + + mm = get_task_mm(pdd->process->lead_thread); + if (mm) { + kthread_use_mm(mm); + { /* attach mm */ + mutex_lock(&pdd->spm_cntr->spm_worker_mutex); + kfd_spm_read_ring_buffer(pdd); + mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); + } /* detach mm */ + kthread_unuse_mm(mm); + /* release the mm structure */ + mmput(mm); + } +} + +void kfd_spm_init_process_device(struct kfd_process_device *pdd) +{ + mutex_init(&pdd->spm_mutex); + pdd->spm_cntr = NULL; +} + +static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) +{ + int ret = 0; + + mutex_lock(&pdd->spm_mutex); + + if (pdd->spm_cntr) { + mutex_unlock(&pdd->spm_mutex); + return -EINVAL; + } + + pdd->spm_cntr = kzalloc(sizeof(struct kfd_spm_cntr), GFP_KERNEL); + if (!pdd->spm_cntr) { + mutex_unlock(&pdd->spm_mutex); + return -ENOMEM; + } + mutex_unlock(&pdd->spm_mutex); + + /* git spm ring buffer 4M */ + pdd->spm_cntr->ring_size = order_base_2(4 * 1024 * 1024/4); + pdd->spm_cntr->ring_size = (1 << pdd->spm_cntr->ring_size) * 4 - 0xff; + pdd->spm_cntr->ring_mask = pdd->spm_cntr->ring_size - 1; + pdd->spm_cntr->has_user_buf = false; + + ret = amdgpu_amdkfd_alloc_gtt_mem(kgd, + pdd->spm_cntr->ring_size, &pdd->spm_cntr->spm_obj, + &pdd->spm_cntr->gpu_addr, (void *)&pdd->spm_cntr->cpu_addr, + false, false); + + if (ret) + goto alloc_gtt_mem_failure; + + ret = amdgpu_amdkfd_rlc_spm_acquire(kgd, pdd->vm, + pdd->spm_cntr->gpu_addr, pdd->spm_cntr->ring_size); + + /* + * By definition, the last 8 DWs of the buffer are not part of the rings + * and are instead part of the Meta data area. + */ + pdd->spm_cntr->ring_size -= 0x20; + + if (ret) + goto acquire_spm_failure; + + mutex_init(&pdd->spm_cntr->spm_worker_mutex); + + init_waitqueue_head(&pdd->spm_cntr->spm_buf_wq); + INIT_WORK(&pdd->spm_work, kfd_spm_work); + + spin_lock_init(&pdd->spm_irq_lock); + + goto out; + +acquire_spm_failure: + amdgpu_amdkfd_free_gtt_mem(kgd, pdd->spm_cntr->spm_obj); + +alloc_gtt_mem_failure: + mutex_lock(&pdd->spm_mutex); + kfree(pdd->spm_cntr); + pdd->spm_cntr = NULL; + mutex_unlock(&pdd->spm_mutex); + +out: + return ret; +} + +static int kfd_release_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) +{ + unsigned long flags; + + mutex_lock(&pdd->spm_mutex); + if (!pdd->spm_cntr) { + mutex_unlock(&pdd->spm_mutex); + return -EINVAL; + } + + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + pdd->spm_cntr->is_spm_started = false; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + + flush_work(&pdd->spm_work); + wake_up_all(&pdd->spm_cntr->spm_buf_wq); + + amdgpu_amdkfd_rlc_spm_release(kgd, pdd->vm); + amdgpu_amdkfd_free_gtt_mem(kgd, pdd->spm_cntr->spm_obj); + + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + kfree(pdd->spm_cntr); + pdd->spm_cntr = NULL; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + + mutex_unlock(&pdd->spm_mutex); + return 0; +} + +static void spm_copy_data_to_usr(struct kfd_ioctl_spm_args *user_spm_data, + struct kfd_process_device *pdd) +{ + mutex_lock(&pdd->spm_cntr->spm_worker_mutex); + user_spm_data->bytes_copied = pdd->spm_cntr->size_copied; + user_spm_data->has_data_loss = pdd->spm_cntr->has_data_loss; + pdd->spm_cntr->has_user_buf = false; + mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); +} + +static void spm_set_dest_info(struct kfd_process_device *pdd, + struct kfd_ioctl_spm_args *user_spm_data) +{ + mutex_lock(&pdd->spm_cntr->spm_worker_mutex); + pdd->spm_cntr->ubuf.user_addr = (uint64_t *)user_spm_data->dest_buf; + pdd->spm_cntr->ubuf.ubufsize = user_spm_data->buf_size; + pdd->spm_cntr->has_data_loss = false; + pdd->spm_cntr->size_copied = 0; + pdd->spm_cntr->is_user_buf_filled = false; + pdd->spm_cntr->has_user_buf = true; + mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); +} + +static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm, + struct kfd_ioctl_spm_args *user_spm_data) +{ + int ret = 0; + + long timeout = msecs_to_jiffies(user_spm_data->timeout); + long start_jiffies = jiffies; + + ret = wait_event_interruptible_timeout(spm->spm_buf_wq, + (READ_ONCE(spm->is_user_buf_filled) == true), + timeout); + + switch (ret) { + case -ERESTARTSYS: + /* Subtract elapsed time from timeout so we wait that much + * less when the call gets restarted. + */ + timeout -= (jiffies - start_jiffies); + if (timeout <= 0) { + ret = -ETIME; + timeout = 0; + pr_debug("[%s] interrupted by signal\n", __func__); + } + break; + + case 0: + default: + timeout = ret; + ret = 0; + break; + } + user_spm_data->timeout = jiffies_to_msecs(timeout); + + return ret; +} + +static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct kgd_dev *kgd, void *data) +{ + struct kfd_ioctl_spm_args *user_spm_data; + struct kfd_spm_cntr *spm; + unsigned long flags; + int ret = 0; + + user_spm_data = (struct kfd_ioctl_spm_args *) data; + + mutex_lock(&pdd->spm_mutex); + spm = pdd->spm_cntr; + + if (spm == NULL) { + mutex_unlock(&pdd->spm_mutex); + return -EINVAL; + } + + if (user_spm_data->timeout && spm->has_user_buf && + !READ_ONCE(spm->is_user_buf_filled)) { + ret = spm_wait_for_fill_awake(spm, user_spm_data); + if (ret == -ETIME) { + /* Copy (partial) data to user buffer after a timeout */ + schedule_work(&pdd->spm_work); + flush_work(&pdd->spm_work); + /* This is not an error */ + ret = 0; + } else if (ret) { + /* handle other errors normally, including -ERESTARTSYS */ + mutex_unlock(&pdd->spm_mutex); + return ret; + } + } else if (!user_spm_data->timeout && spm->has_user_buf) { + /* Copy (partial) data to user buffer */ + schedule_work(&pdd->spm_work); + flush_work(&pdd->spm_work); + } + + if (spm->has_user_buf) { + /* get info about filled space in previous output buffer */ + spm_copy_data_to_usr(user_spm_data, pdd); + } + + if (user_spm_data->dest_buf) { + /* setup new dest buf, start streaming if necessary */ + spm_set_dest_info(pdd, user_spm_data); + + /* Start SPM */ + if (spm->is_spm_started == false) { + amdgpu_amdkfd_rlc_spm_cntl(kgd, 1); + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + spm->is_spm_started = true; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + } else { + /* If SPM was already started, there may already + * be data in the ring-buffer that needs to be read. + */ + schedule_work(&pdd->spm_work); + } + } else { + amdgpu_amdkfd_rlc_spm_cntl(kgd, 0); + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + spm->is_spm_started = false; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + } + + mutex_unlock(&pdd->spm_mutex); + + return ret; +} + +int kfd_rlc_spm(struct kfd_process *p, void *data) +{ + struct kfd_ioctl_spm_args *args = data; + struct kfd_dev *dev; + struct kfd_process_device *pdd; + + dev = kfd_device_by_id(args->gpu_id); + if (!dev) { + pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); + return -EINVAL; + } + + pdd = kfd_get_process_device_data(dev, p); + if (!pdd) + return -EINVAL; + + switch (args->op) { + case KFD_IOCTL_SPM_OP_ACQUIRE: + dev->spm_pasid = p->pasid; + return kfd_acquire_spm(pdd, dev->kgd); + + case KFD_IOCTL_SPM_OP_RELEASE: + return kfd_release_spm(pdd, dev->kgd); + + case KFD_IOCTL_SPM_OP_SET_DEST_BUF: + return kfd_set_dest_buffer(pdd, dev->kgd, data); + + default: + return -EINVAL; + } + + return -EINVAL; +} + +void kgd2kfd_spm_interrupt(struct kfd_dev *dev) +{ + struct kfd_process_device *pdd; + uint16_t pasid = dev->spm_pasid; + + struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); + unsigned long flags; + + if (!p) { + pr_debug("kfd_spm_interrupt p = %p\n", p); + return; /* Presumably process exited. */ + } + + pdd = kfd_get_process_device_data(dev, p); + if (!pdd) + return; + + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + + if (pdd->spm_cntr && pdd->spm_cntr->is_spm_started) + schedule_work(&pdd->spm_work); + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + + kfd_unref_process(p); +} + diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 8ada6ae7dd78c..790bccbd9cb0c 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -591,6 +591,81 @@ struct kfd_ioctl_smi_events_args { __u32 anon_fd; /* from KFD */ }; +/** + * kfd_ioctl_spm_op - SPM ioctl operations + * + * @KFD_IOCTL_SPM_OP_ACQUIRE: acquire exclusive access to SPM + * @KFD_IOCTL_SPM_OP_RELEASE: release exclusive access to SPM + * @KFD_IOCTL_SPM_OP_SET_DEST_BUF: set or unset destination buffer for SPM streaming + */ +enum kfd_ioctl_spm_op { + KFD_IOCTL_SPM_OP_ACQUIRE, + KFD_IOCTL_SPM_OP_RELEASE, + KFD_IOCTL_SPM_OP_SET_DEST_BUF +}; + +/** + * kfd_ioctl_spm_args - Arguments for SPM ioctl + * + * @op[in]: specifies the operation to perform + * @gpu_id[in]: GPU ID of the GPU to profile + * @dst_buf[in]: used for the address of the destination buffer + * in @KFD_IOCTL_SPM_SET_DEST_BUFFER + * @buf_size[in]: size of the destination buffer + * @timeout[in/out]: [in]: timeout in milliseconds, [out]: amount of time left + * `in the timeout window + * @bytes_copied[out]: amount of data that was copied to the previous dest_buf + * @has_data_loss: boolean indicating whether data was lost + * (e.g. due to a ring-buffer overflow) + * + * This ioctl performs different functions depending on the @op parameter. + * + * KFD_IOCTL_SPM_OP_ACQUIRE + * ------------------------ + * + * Acquires exclusive access of SPM on the specified @gpu_id for the calling process. + * This must be called before using KFD_IOCTL_SPM_OP_SET_DEST_BUF. + * + * KFD_IOCTL_SPM_OP_RELEASE + * ------------------------ + * + * Releases exclusive access of SPM on the specified @gpu_id for the calling process, + * which allows another process to acquire it in the future. + * + * KFD_IOCTL_SPM_OP_SET_DEST_BUF + * ----------------------------- + * + * If @dst_buf is NULL, the destination buffer address is unset and copying of counters + * is stopped. + * + * If @dst_buf is not NULL, it specifies the pointer to a new destination buffer. + * @buf_size specifies the size of the buffer. + * + * If @timeout is non-0, the call will wait for up to @timeout ms for the previous + * buffer to be filled. If previous buffer to be filled before timeout, the @timeout + * will be updated value with the time remaining. If the timeout is exceeded, the function + * copies any partial data available into the previous user buffer and returns success. + * The amount of valid data in the previous user buffer is indicated by @bytes_copied. + * + * If @timeout is 0, the function immediately replaces the previous destination buffer + * without waiting for the previous buffer to be filled. That means the previous buffer + * may only be partially filled, and @bytes_copied will indicate how much data has been + * copied to it. + * + * If data was lost, e.g. due to a ring buffer overflow, @has_data_loss will be non-0. + * + * Returns negative error code on failure, 0 on success. + */ +struct kfd_ioctl_spm_args { + __u64 dest_buf; + __u32 buf_size; + __u32 op; + __u32 timeout; + __u32 gpu_id; + __u32 bytes_copied; + __u32 has_data_loss; +}; + /* * SVM event tracing via SMI system management interface * @@ -741,7 +816,6 @@ struct kfd_criu_bo_bucket { /* CRIU IOCTLs - END */ /**************************************************************************************************/ - /* Register offset inside the remapped mmio page */ enum kfd_mmio_remap { @@ -1707,7 +1781,10 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_IPC_EXPORT_HANDLE \ AMDKFD_IOWR(0x81, struct kfd_ioctl_ipc_export_handle_args) +#define AMDKFD_IOC_RLC_SPM \ + AMDKFD_IOWR(0x84, struct kfd_ioctl_spm_args) + #define AMDKFD_COMMAND_START_2 0x80 -#define AMDKFD_COMMAND_END_2 0x84 +#define AMDKFD_COMMAND_END_2 0x85 #endif From 4a2de2a6ea313b00cf92e194f6a28a4df33e2bf0 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Thu, 7 Jan 2021 13:54:26 +0800 Subject: [PATCH 0281/2653] Revert "drm/amd/pm: typo fix (CUSTOM -> COMPUTE)" This reverts commit 11a4d4b89bfd7981aeb765683e1c5f7222f645f5. It breaks one test. Root cause identifying is still on the way. Signed-off-by: Guchun Chen --- drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index d57591509aed1..29090d3dba2ea 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -250,7 +250,7 @@ static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), + WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), }; From 5a96133c1ff751ab8d8d09fd2c7ca202914c4c09 Mon Sep 17 00:00:00 2001 From: Gang Ba Date: Thu, 14 Jan 2021 22:54:39 -0500 Subject: [PATCH 0282/2653] drm/amdkfd: Create indirect links Create GPU<->CPU indirect IO links Signed-off-by: Gang Ba Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index be83f739fc6aa..18e098d043f1c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1415,6 +1415,20 @@ static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev) kfd_set_iolink_non_coherent(peer_dev, link, inbound_link); } } + + /* Create CPU<->GPU indirect links so apply flags setting to all */ + list_for_each_entry(link, &dev->p2p_link_props, list) { + cpu_dev = kfd_topology_device_by_proximity_domain( + link->node_to); + if (cpu_dev && !cpu_dev->gpu) { + list_for_each_entry(cpu_link, + &cpu_dev->p2p_link_props, list) + if (cpu_link->node_to == link->node_from) { + link->flags = flag; + cpu_link->flags = cpu_flag; + } + } + } } static int kfd_build_p2p_node_entry(struct kfd_topology_device *dev, From eec9584d94f45881d51bf3586b852252a9da4f7a Mon Sep 17 00:00:00 2001 From: Philip Cox Date: Tue, 17 Nov 2020 11:05:36 -0500 Subject: [PATCH 0283/2653] drm/amdkfd: Change kfd debugger to use PID. Rework the kfd debugger API to use PID rather than the device id. Debugging actions are now on all devices, rather than a single device. Change-Id: Ie2a18a0299176b6a68c23113da057c7f7746c3a6 Signed-off-by: Philip Cox Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 ------ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 19 ------------------- include/uapi/linux/kfd_ioctl.h | 2 +- 3 files changed, 1 insertion(+), 26 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index d22cca786f176..c9d426f0c7a81 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1520,12 +1520,6 @@ static int kfd_ioctl_alloc_queue_gws(struct file *filep, goto out_unlock; } - pdd = kfd_bind_process_to_device(dev, p); - if (IS_ERR(pdd)) { - retval = -ESRCH; - goto out_unlock; - } - if (!dev->gws) { retval = -ENODEV; goto out_unlock; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 1044d3f1d8e45..5719742b98d1a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -373,15 +373,6 @@ struct kfd_dev { /*spm process id */ unsigned int spm_pasid; - /* - * A bitmask to indicate which watch points have been allocated. - * bit meaning: - * 0: unallocated/available - * 1: allocated/unavailable - */ - uint32_t allocated_debug_watch_points; - spinlock_t watch_points_lock; - struct ida doorbell_ida; unsigned int max_doorbell_slices; @@ -1631,16 +1622,6 @@ int kfd_ipc_init(void); void kfd_inc_compute_active(struct kfd_node *dev); void kfd_dec_compute_active(struct kfd_node *dev); -/* Allocate and free watch point IDs for debugger */ -int kfd_allocate_debug_watch_point(struct kfd_dev *kfd, - uint64_t watch_address, - uint32_t watch_address_mask, - uint32_t *watch_point, - uint32_t watch_mode, - uint32_t debug_vmid); -int kfd_release_debug_watch_points(struct kfd_dev *kfd, - uint32_t watch_point_bit_mask_to_free); - /* Cgroup Support */ /* Check with device cgroup if @kfd device is accessible */ static inline int kfd_devcgroup_check_permission(struct kfd_node *node) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 790bccbd9cb0c..67ca5053e8778 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -251,11 +251,11 @@ struct kfd_ioctl_dbg_wave_control_args { struct kfd_ioctl_dbg_trap_args { __u64 ptr; /* to KFD -- used for pointer arguments: queue arrays */ __u32 pid; /* to KFD */ - __u32 gpu_id; /* to KFD */ __u32 op; /* to KFD */ __u32 data1; /* to KFD */ __u32 data2; /* to KFD */ __u32 data3; /* to KFD */ + __u32 data4; /* to KFD */ }; /* Matching HSA_EVENTTYPE */ From 9b6a8ca78e09e9074ace2f6f0cbde32854dbe414 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Tue, 19 Jan 2021 23:45:47 -0500 Subject: [PATCH 0284/2653] drm/amdkfd: enable exception code reporting to the debugger Report EC_TRAP_HANDLER (debug notifier only at the moment), EC_QUEUE_NEW, EC_QUEUE_DELETE and EC_MEMORY_VIOLATION to the debugger with the new exception code features. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- include/uapi/linux/kfd_ioctl.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 67ca5053e8778..da4f814fe9654 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -249,6 +249,7 @@ struct kfd_ioctl_dbg_wave_control_args { #define KFD_INVALID_FD 0xffffffff struct kfd_ioctl_dbg_trap_args { + __u64 exception_mask; /* to KFD */ __u64 ptr; /* to KFD -- used for pointer arguments: queue arrays */ __u32 pid; /* to KFD */ __u32 op; /* to KFD */ From 649c15ab90d064e43e1dd3340abfb87428ce00b1 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 22 Apr 2020 21:43:26 +0800 Subject: [PATCH 0285/2653] drm/amdkcl: test drm_driver->gem_prime_export() This is a squash of: drm/amdkcl: fix test for drm_gem_prime_export() Reviewed-by: Guchun Chen Signed-off-by: Flora Cui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 10 ++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 5 +++++ .../drm/amd/dkms/m4/drm-drv-gem-prime-export.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 32 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-drv-gem-prime-export.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 22b9b692b9083..2c7f60a845010 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -505,7 +505,12 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = { * Returns: * Shared DMA buffer representing the GEM BO from the given device. */ +#ifdef HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, +#else +struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, + struct drm_gem_object *gobj, +#endif int flags) { struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); @@ -515,7 +520,12 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) return ERR_PTR(-EPERM); +#ifdef HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI buf = drm_gem_prime_export(gobj, flags); +#else + buf = drm_gem_prime_export(dev, gobj, flags); +#endif + #if defined(AMDKCL_AMDGPU_DMABUF_OPS) if (!IS_ERR(buf)) buf->ops = &amdgpu_dmabuf_ops; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h index db75327913c95..f7a7492b68f55 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h @@ -34,7 +34,12 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, struct sg_table *sg); #endif +#ifdef HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, +#else +struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, + struct drm_gem_object *gobj, +#endif int flags); #if defined(AMDKCL_AMDGPU_DMABUF_OPS) struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-drv-gem-prime-export.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-drv-gem-prime-export.m4 new file mode 100644 index 0000000000000..bac95ca04518c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-drv-gem-prime-export.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.2-rc5-870-ge4fa8457b219 +dnl # drm/prime: Align gem_prime_export with obj_funcs.export +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_gem_prime_export(NULL, 0); + ],[ + AC_DEFINE(HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI, 1, + [drm_gem_prime_export() with p,i arg is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cceaf0c361193..268ac6b8672e3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -64,6 +64,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ + AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_MEM_ENCRYPT_ACTIVE From 906e4f63ff98a0c0c9db9f4421af981ab98b70be Mon Sep 17 00:00:00 2001 From: Anatoli Antonovitch Date: Wed, 26 Jun 2019 15:20:19 -0400 Subject: [PATCH 0286/2653] drm/amdkcl: Test whether ttm_bo_vm_fault() wants 2 args v2: Test whether vm_fault->{address/vma} is available v3: fix intree failure due to vmf->vma kcl wrapper v4: refactor test for vm_operations_struct->fault() Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Jack Gui Signed-off-by: Jack Gui Reviewed-by: Jiansong Chen Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 8 +++- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/vm_operations_struct.m4 | 35 +++++++++++++++ drivers/gpu/drm/ttm/ttm_bo_vm.c | 45 ++++++++++++++++--- include/drm/ttm/ttm_bo.h | 16 +++++++ 5 files changed, 99 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index cc97f392c90af..cbd0d109ea883 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -128,9 +128,15 @@ static void kfd_doorbell_close(struct vm_area_struct *vma) mutex_unlock(&pdd->qpd.doorbell_lock); } +#ifdef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG static vm_fault_t kfd_doorbell_vm_fault(struct vm_fault *vmf) { - struct kfd_process_device *pdd = vmf->vma->vm_private_data; + struct vm_area_struct *vma = vmf->vma; +#else +static int kfd_doorbell_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ +#endif + struct kfd_process_device *pdd = vma->vm_private_data; if (!pdd) return VM_FAULT_SIGBUS; diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 268ac6b8672e3..cb1731abd6d52 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -42,6 +42,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMF_INSERT AC_AMDGPU_VMF_INSERT_MIXED_PROT AC_AMDGPU_VMF_INSERT_PFN_PROT + AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU AC_AMDGPU_MM_RELEASE_PAGES diff --git a/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 b/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 new file mode 100644 index 0000000000000..9e01b9fb9f36b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 @@ -0,0 +1,35 @@ +dnl # +dnl # commit v4.10-9602-g11bac8000449 +dnl # mm, fs: reduce fault, page_mkwrite, and pfn_mkwrite to take only vmf +dnl # +AC_DEFUN([AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int (*fault)(struct vm_area_struct *vma, struct vm_fault *vmf) = 0; + struct vm_operations_struct *vm_ops = NULL; + vm_ops->fault(NULL); + ], [ + AC_DEFINE(HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG, 1, + [vm_operations_struct->fault() wants 1 arg]) + AC_DEFINE(HAVE_VM_FAULT_ADDRESS_VMA, 1, + [vm_fault->{address/vam} is available]) + ], [ + dnl # + dnl # commit v4.9-7746-g82b0f8c39a38 + dnl # mm: join struct fault_env and vm_fault + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct vm_fault *ptest = NULL; + ptest->address = 0; + ptest->vma = NULL; + ], [ + AC_DEFINE(HAVE_VM_FAULT_ADDRESS_VMA, 1, + [vm_fault->{address/vam} is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index ba7563e7e5a7c..068dac4f05d8d 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -41,7 +41,8 @@ #include static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, - struct vm_fault *vmf) + struct vm_fault *vmf, + struct vm_area_struct *vma) { long err = 0; @@ -61,7 +62,7 @@ static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, return VM_FAULT_RETRY; drm_gem_object_get(&bo->base); - mmap_read_unlock(vmf->vma->vm_mm); + mmap_read_unlock(vma->vm_mm); (void)dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_KERNEL, true, MAX_SCHEDULE_TIMEOUT); @@ -115,9 +116,17 @@ static unsigned long ttm_bo_io_mem_pfn(struct ttm_buffer_object *bo, * VM_FAULT_RETRY if blocking wait. * VM_FAULT_NOPAGE if blocking wait and retrying was not allowed. */ +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, - struct vm_fault *vmf) + struct vm_fault *vmf, + struct vm_area_struct *vma) { +#else +vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, + struct vm_fault *vmf) +{ + struct vm_area_struct *vma = vmf->vma; +#endif /* * Work around locking order reversal in fault / nopfn * between mmap_lock and bo_reserve: Perform a trylock operation @@ -133,7 +142,7 @@ vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, if (fault_flag_allow_retry_first(vmf->flags)) { if (!(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) { drm_gem_object_get(&bo->base); - mmap_read_unlock(vmf->vma->vm_mm); + mmap_read_unlock(vma->vm_mm); if (!dma_resv_lock_interruptible(amdkcl_ttm_resvp(bo), NULL)) dma_resv_unlock(amdkcl_ttm_resvp(bo)); @@ -180,11 +189,19 @@ EXPORT_SYMBOL(ttm_bo_vm_reserve); * VM_FAULT_OOM on out-of-memory * VM_FAULT_RETRY if retryable wait */ +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG +vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, + struct vm_area_struct *vma, + pgprot_t prot, + pgoff_t num_prefault) +{ +#else vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, pgprot_t prot, pgoff_t num_prefault) { struct vm_area_struct *vma = vmf->vma; +#endif struct ttm_buffer_object *bo = vma->vm_private_data; struct ttm_device *bdev = bo->bdev; unsigned long page_offset; @@ -195,13 +212,17 @@ vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, int err; pgoff_t i; vm_fault_t ret = VM_FAULT_NOPAGE; +#ifndef HAVE_VM_FAULT_ADDRESS_VMA + unsigned long address = (unsigned long)vmf->virtual_address; +#else unsigned long address = vmf->address; +#endif /* * Wait for buffer data in transit, due to a pipelined * move. */ - ret = ttm_bo_vm_fault_idle(bo, vmf); + ret = ttm_bo_vm_fault_idle(bo, vmf, vma); if (unlikely(ret != 0)) return ret; @@ -319,22 +340,36 @@ vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, pgprot_t prot) } EXPORT_SYMBOL(ttm_bo_vm_dummy_page); +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG +vm_fault_t ttm_bo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ +#else vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf) { struct vm_area_struct *vma = vmf->vma; +#endif pgprot_t prot; struct ttm_buffer_object *bo = vma->vm_private_data; struct drm_device *ddev = bo->base.dev; vm_fault_t ret; int idx; +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG + ret = ttm_bo_vm_reserve(bo, vmf, vma); +#else ret = ttm_bo_vm_reserve(bo, vmf); +#endif if (ret) return ret; prot = vma->vm_page_prot; if (drm_dev_enter(ddev, &idx)) { + +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG + ret = ttm_bo_vm_fault_reserved(vmf, vma, prot, TTM_BO_VM_NUM_PREFAULT); +#else ret = ttm_bo_vm_fault_reserved(vmf, prot, TTM_BO_VM_NUM_PREFAULT); +#endif drm_dev_exit(idx); } else { ret = ttm_bo_vm_dummy_page(vmf, prot); diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h index cd5720ef66c21..0a0727af7011f 100644 --- a/include/drm/ttm/ttm_bo.h +++ b/include/drm/ttm/ttm_bo.h @@ -39,6 +39,7 @@ #include "ttm_device.h" #ifndef HAVE_CONFIG_H #define HAVE_DRM_GEM_OBJECT_RESV 1 +#define HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG 1 #endif /* Default number of pre-faulted pages in the TTM fault handler */ @@ -439,12 +440,27 @@ int ttm_bo_evict_first(struct ttm_device *bdev, struct ttm_operation_ctx *ctx); int ttm_bo_access(struct ttm_buffer_object *bo, unsigned long offset, void *buf, int len, int write); + +#if defined(HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG) vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, struct vm_fault *vmf); vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, pgprot_t prot, pgoff_t num_prefault); vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf); +#else +vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, + struct vm_fault *vmf, + struct vm_area_struct *vma); + +vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, + struct vm_area_struct *vma, + pgprot_t prot, + pgoff_t num_prefault); + +vm_fault_t ttm_bo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf); +#endif + void ttm_bo_vm_open(struct vm_area_struct *vma); void ttm_bo_vm_close(struct vm_area_struct *vma); int ttm_bo_vm_access(struct vm_area_struct *vma, unsigned long addr, From 4472901c55bae7dcb2f9959f17941844b3fc8ef4 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 14 Aug 2019 12:58:05 +0800 Subject: [PATCH 0287/2653] drm/amdkcl: Test whether drm_mm_print is available v1: drm/amdkcl: Test whether drm_debug_printer() function is available v2: drm/amdkcl: fix the struct drm_printer error. v3: drm/amdkcl: fix drm_printer related checks v4: drm/amdkcl: accommodate to drmP.h removal for drm-mm-print.m4 Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Slava Grigorev Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Change-Id: I66988af2c3ae0af9782f278edebaaafbccd3fa30 --- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 8 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 4 ++++ drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 | 15 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/drm/ttm/ttm_resource.h | 4 ++++ 6 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index 0760e70402ec1..d72c5a9a85470 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -247,12 +247,20 @@ static bool amdgpu_gtt_mgr_compatible(struct ttm_resource_manager *man, * Dump the table content using printk. */ static void amdgpu_gtt_mgr_debug(struct ttm_resource_manager *man, +#if defined(HAVE_DRM_MM_PRINT) struct drm_printer *printer) +#else + const char *prefix) +#endif { struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man); spin_lock(&mgr->lock); +#if defined(HAVE_DRM_MM_PRINT) drm_mm_print(&mgr->mm, printer); +#else + drm_mm_debug_table(&mgr->mm, prefix); +#endif spin_unlock(&mgr->lock); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 8a0469a8b4c00..2d6f9fcaafa28 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2724,7 +2724,6 @@ int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type) } #if defined(CONFIG_DEBUG_FS) - static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) { struct amdgpu_device *adev = m->private; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 77ce9cf280518..775040320b442 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -911,7 +911,11 @@ static bool amdgpu_vram_mgr_compatible(struct ttm_resource_manager *man, * Dump the table content using printk. */ static void amdgpu_vram_mgr_debug(struct ttm_resource_manager *man, +#if defined(HAVE_DRM_MM_PRINT) struct drm_printer *printer) +#else + const char *prefix) +#endif { struct amdgpu_vram_mgr *mgr = to_vram_mgr(man); struct drm_buddy *mm = &mgr->mm; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 new file mode 100644 index 0000000000000..2d1d63b131ce7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit b5c3714fe8789745521d8351d75049b9c6a0d26b +dnl # drm/mm: Convert to drm_printer +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MM_PRINT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_mm_print(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_MM_PRINT, 1, [drm_mm_print() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cb1731abd6d52..1befd32bc2b9e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -66,6 +66,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT + AC_AMDGPU_DRM_MM_PRINT AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_MEM_ENCRYPT_ACTIVE diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h index b873be9597e2e..a7afc95448be7 100644 --- a/include/drm/ttm/ttm_resource.h +++ b/include/drm/ttm/ttm_resource.h @@ -168,8 +168,12 @@ struct ttm_resource_manager_func { * type manager to aid debugging of out-of-memory conditions. * It may not be called from within atomic context. */ +#if defined(HAVE_DRM_MM_PRINT) void (*debug)(struct ttm_resource_manager *man, struct drm_printer *printer); +#else + void (*debug)(struct ttm_resource_manager *man, const char *prefix); +#endif }; /** From 737ad0cbd85fc314532bfbdedac4ae87422a8a8f Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Mon, 5 Aug 2019 10:10:54 +0800 Subject: [PATCH 0288/2653] drm/amdkcl: Test whether drm_mm_insert_mode is available drm_mm_search_flags was replaced with drm_mm_insert_mode when kernel 4.11 introduced v1: drm/amdkcl: fix missing HAVE_DRM_MM_INSERT_MODE check (v2) v2: clean code v3: drm/amdkcl: accommodate to drmP.h removal for drm-mm-insert-mode.m4 Signed-off-by: Chengming Gui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui Change-Id: I26c8f257f9f86c8c66b8b3ed3ec11bfb217f1507 --- .../gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/ttm/ttm_range_manager.c | 7 +++++++ 3 files changed, 25 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 new file mode 100644 index 0000000000000..633f7925b0aec --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 4e64e5539d152e202ad6eea2b6f65f3ab58d9428 +dnl # Author: Chris Wilson +dnl # Date: Thu Feb 2 21:04:38 2017 +0000 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MM_INSERT_MODE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + enum drm_mm_insert_mode mode = DRM_MM_INSERT_BEST; + ],[ + AC_DEFINE(HAVE_DRM_MM_INSERT_MODE, 1, + [whether drm_mm_insert_mode is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1befd32bc2b9e..e49321200a7c9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -67,6 +67,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT AC_AMDGPU_DRM_MM_PRINT + AC_AMDGPU_DRM_MM_INSERT_MODE AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_MEM_ENCRYPT_ACTIVE diff --git a/drivers/gpu/drm/ttm/ttm_range_manager.c b/drivers/gpu/drm/ttm/ttm_range_manager.c index db854b581d834..7b786bab51c1c 100644 --- a/drivers/gpu/drm/ttm/ttm_range_manager.c +++ b/drivers/gpu/drm/ttm/ttm_range_manager.c @@ -77,9 +77,16 @@ static int ttm_range_man_alloc(struct ttm_resource_manager *man, if (!node) return -ENOMEM; +#ifndef HAVE_DRM_MM_INSERT_MODE + if (place->flags & TTM_PL_FLAG_TOPDOWN) { + sflags = DRM_MM_SEARCH_BELOW; + aflags = DRM_MM_CREATE_TOP; + } +#else mode = DRM_MM_INSERT_BEST; if (place->flags & TTM_PL_FLAG_TOPDOWN) mode = DRM_MM_INSERT_HIGH; +#endif ttm_resource_init(bo, place, &node->base); From c015a0805fd485d8a0f1fdf026b6d770bc385d30 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Tue, 30 Jul 2019 08:58:34 +0800 Subject: [PATCH 0289/2653] drm/amdkcl: add sync obj macros clean amdgpu_cs.c code v1: drm/amdkcl: remove DRIVER_SYNCOBJ_TIMELINE in kms_driver v2: sync with mainline v3: drm/amdkcl: add HAVE_CHUNK_ID_SYNOBJ_IN_OUT in amdgpu_cs_post_dep v4: drm/amd/autoconf: fix CHUNK_ID_SCHEDULED_DEPENDENCIES check error v5: drm/amdkcl: drop kcl_drm_syncobj_find_fence Signed-off-by: Yifan Zhang Signed-off-by: Adam Yang Reviewed-by: Flora Cui Signed-off-by: Flora Cui Signed-off-by: Jack Gui Acked-by: Feifei Xu / --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 11 ++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++++-- .../dkms/m4/chunk-id-scheduled-dependencies.m4 | 16 ++++++++++++++++ .../m4/chunk-id-syncobj-timeline-wait-signal.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 ++ 5 files changed, 51 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/chunk-id-scheduled-dependencies.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/chunk-id-syncobj-timeline-wait-signal.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index f2548e9619955..67a45cfc70ecd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -276,12 +276,15 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p, case AMDGPU_CHUNK_ID_DEPENDENCIES: case AMDGPU_CHUNK_ID_SYNCOBJ_IN: case AMDGPU_CHUNK_ID_SYNCOBJ_OUT: +#if defined(HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES: +#endif +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT: case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL: +#endif case AMDGPU_CHUNK_ID_CP_GFX_SHADOW: break; - default: goto free_partial_kdata; } @@ -593,6 +596,7 @@ static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p, return 0; } +#endif static int amdgpu_cs_p2_shadow(struct amdgpu_cs_parser *p, struct amdgpu_cs_chunk *chunk) @@ -1289,6 +1293,7 @@ static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p) int i; for (i = 0; i < p->num_post_deps; ++i) { +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) if (p->post_deps[i].chain && p->post_deps[i].point) { drm_syncobj_add_point(p->post_deps[i].syncobj, p->post_deps[i].chain, @@ -1298,6 +1303,10 @@ static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p) drm_syncobj_replace_fence(p->post_deps[i].syncobj, p->fence); } +#else + drm_syncobj_replace_fence(p->post_deps[i].syncobj, + p->fence); +#endif } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 67e82a1752c0d..43d880e6f8751 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3082,8 +3082,12 @@ static const struct drm_driver amdgpu_kms_driver = { .driver_features = DRIVER_ATOMIC | DRIVER_GEM | - DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | - DRIVER_SYNCOBJ_TIMELINE, + DRIVER_RENDER | DRIVER_MODESET + | DRIVER_SYNCOBJ +#ifdef HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE + | DRIVER_SYNCOBJ_TIMELINE +#endif /* HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE */ + , .open = amdgpu_driver_open_kms, .postclose = amdgpu_driver_postclose_kms, .ioctls = amdgpu_ioctls_kms, diff --git a/drivers/gpu/drm/amd/dkms/m4/chunk-id-scheduled-dependencies.m4 b/drivers/gpu/drm/amd/dkms/m4/chunk-id-scheduled-dependencies.m4 new file mode 100644 index 0000000000000..c1075f2a16d7f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/chunk-id-scheduled-dependencies.m4 @@ -0,0 +1,16 @@ +dnl # commit 67dd1a36334ffce82bebeb2d633e152aa436d370 +dnl # drm/amdgpu: Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES +AC_DEFUN([AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + #ifndef AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES + #error AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES not #defined + #endif + ], [ + AC_DEFINE(HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES, 1, + [whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/chunk-id-syncobj-timeline-wait-signal.m4 b/drivers/gpu/drm/amd/dkms/m4/chunk-id-syncobj-timeline-wait-signal.m4 new file mode 100644 index 0000000000000..1ae2aee78530f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/chunk-id-syncobj-timeline-wait-signal.m4 @@ -0,0 +1,17 @@ +dnl # commit 2624dd154bcc53ac2de16ecae9746ba867b6ca70 +dnl # drm/amdgpu: add timeline support in amdgpu CS v3 +AC_DEFUN([AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + #if !defined(AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT) ||\ + !defined(AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL) + #error CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL not #defined + #endif + ], [ + AC_DEFINE(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL, 1, + [whether CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL is defined]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e49321200a7c9..a497aff232b48 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -68,6 +68,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT AC_AMDGPU_DRM_MM_PRINT AC_AMDGPU_DRM_MM_INSERT_MODE + AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES + AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_MEM_ENCRYPT_ACTIVE From 4a58c1e6dc82434661b51d771acd5086e5da1213 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 14 Apr 2020 20:31:21 +0800 Subject: [PATCH 0290/2653] drm/amdkcl: test drm_fb_helper_init() Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 400 ++++++++++++++++++ .../gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 | 35 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 436 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c new file mode 100644 index 0000000000000..51c51f477d05c --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -0,0 +1,400 @@ +/* + * Copyright © 2007 David Airlie + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * David Airlie + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "amdgpu.h" +#include "cikd.h" +#include "amdgpu_gem.h" + +#include "amdgpu_display.h" + +/* object hierarchy - + this contains a helper + a amdgpu fb + the helper contains a pointer to amdgpu framebuffer baseclass. +*/ + +static int +amdgpufb_open(struct fb_info *info, int user) +{ + struct drm_fb_helper *fb_helper = info->par; + int ret = pm_runtime_get_sync(fb_helper->dev->dev); + if (ret < 0 && ret != -EACCES) { + pm_runtime_mark_last_busy(fb_helper->dev->dev); + pm_runtime_put_autosuspend(fb_helper->dev->dev); + return ret; + } + return 0; +} + +static int +amdgpufb_release(struct fb_info *info, int user) +{ + struct drm_fb_helper *fb_helper = info->par; + + pm_runtime_mark_last_busy(fb_helper->dev->dev); + pm_runtime_put_autosuspend(fb_helper->dev->dev); + return 0; +} + +static const struct fb_ops amdgpufb_ops = { + .owner = THIS_MODULE, + DRM_FB_HELPER_DEFAULT_OPS, + .fb_open = amdgpufb_open, + .fb_release = amdgpufb_release, + .fb_fillrect = drm_fb_helper_cfb_fillrect, + .fb_copyarea = drm_fb_helper_cfb_copyarea, + .fb_imageblit = drm_fb_helper_cfb_imageblit, +}; + + +int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled) +{ + int aligned = width; + int pitch_mask = 0; + + switch (cpp) { + case 1: + pitch_mask = 255; + break; + case 2: + pitch_mask = 127; + break; + case 3: + case 4: + pitch_mask = 63; + break; + } + + aligned += pitch_mask; + aligned &= ~pitch_mask; + return aligned * cpp; +} + +static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj) +{ + struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); + int ret; + + ret = amdgpu_bo_reserve(abo, true); + if (likely(ret == 0)) { + amdgpu_bo_kunmap(abo); + amdgpu_bo_unpin(abo); + amdgpu_bo_unreserve(abo); + } + drm_gem_object_put(gobj); +} + +static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, + struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object **gobj_p) +{ + const struct drm_format_info *info; + struct amdgpu_device *adev = rfbdev->adev; + struct drm_gem_object *gobj = NULL; + struct amdgpu_bo *abo = NULL; + bool fb_tiled = false; /* useful for testing */ + u32 tiling_flags = 0, domain; + int ret; + int aligned_size, size; + int height = mode_cmd->height; + u32 cpp; + u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_VRAM_CLEARED; + + info = drm_get_format_info(adev_to_drm(adev), mode_cmd); + cpp = info->cpp[0]; + + /* need to align pitch with crtc limits */ + mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, + fb_tiled); + domain = amdgpu_display_supported_domains(adev, flags); + height = ALIGN(mode_cmd->height, 8); + size = mode_cmd->pitches[0] * height; + aligned_size = ALIGN(size, PAGE_SIZE); + ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, flags, + ttm_bo_type_device, NULL, &gobj); + if (ret) { + pr_err("failed to allocate framebuffer (%d)\n", aligned_size); + return -ENOMEM; + } + abo = gem_to_amdgpu_bo(gobj); + + if (fb_tiled) + tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1); + + ret = amdgpu_bo_reserve(abo, false); + if (unlikely(ret != 0)) + goto out_unref; + + if (tiling_flags) { + ret = amdgpu_bo_set_tiling_flags(abo, + tiling_flags); + if (ret) + dev_err(adev->dev, "FB failed to set tiling flags\n"); + } + + ret = amdgpu_bo_pin(abo, domain); + if (ret) { + amdgpu_bo_unreserve(abo); + goto out_unref; + } + + ret = amdgpu_ttm_alloc_gart(&abo->tbo); + if (ret) { + amdgpu_bo_unreserve(abo); + dev_err(adev->dev, "%p bind failed\n", abo); + goto out_unref; + } + + ret = amdgpu_bo_kmap(abo, NULL); + amdgpu_bo_unreserve(abo); + if (ret) { + goto out_unref; + } + + *gobj_p = gobj; + return 0; +out_unref: + amdgpufb_destroy_pinned_object(gobj); + *gobj_p = NULL; + return ret; +} + +static int amdgpufb_create(struct drm_fb_helper *helper, + struct drm_fb_helper_surface_size *sizes) +{ + struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper; + struct amdgpu_device *adev = rfbdev->adev; + struct fb_info *info; + struct drm_framebuffer *fb = NULL; + struct drm_mode_fb_cmd2 mode_cmd; + struct drm_gem_object *gobj = NULL; + struct amdgpu_bo *abo = NULL; + int ret; + + memset(&mode_cmd, 0, sizeof(mode_cmd)); + mode_cmd.width = sizes->surface_width; + mode_cmd.height = sizes->surface_height; + + if (sizes->surface_bpp == 24) + sizes->surface_bpp = 32; + + mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, + sizes->surface_depth); + + ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj); + if (ret) { + DRM_ERROR("failed to create fbcon object %d\n", ret); + return ret; + } + + abo = gem_to_amdgpu_bo(gobj); + + /* okay we have an object now allocate the framebuffer */ + info = drm_fb_helper_alloc_fbi(helper); + if (IS_ERR(info)) { + ret = PTR_ERR(info); + goto out; + } + + ret = amdgpu_display_gem_fb_init(adev_to_drm(adev), &rfbdev->rfb, + &mode_cmd, gobj); + if (ret) { + DRM_ERROR("failed to initialize framebuffer %d\n", ret); + goto out; + } + + fb = &rfbdev->rfb.base; + + /* setup helper */ + rfbdev->helper.fb = fb; + + info->fbops = &amdgpufb_ops; + + info->fix.smem_start = amdgpu_gmc_vram_cpu_pa(adev, abo); + info->fix.smem_len = amdgpu_bo_size(abo); + info->screen_base = amdgpu_bo_kptr(abo); + info->screen_size = amdgpu_bo_size(abo); + + drm_fb_helper_fill_info(info, &rfbdev->helper, sizes); + + /* setup aperture base/size for vesafb takeover */ + info->apertures->ranges[0].base = adev_to_drm(adev)->mode_config.fb_base; + info->apertures->ranges[0].size = adev->gmc.aper_size; + + /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ + + if (info->screen_base == NULL) { + ret = -ENOSPC; + goto out; + } + + DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); + DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base); + DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo)); + DRM_INFO("fb depth is %d\n", fb->format->depth); + DRM_INFO(" pitch is %d\n", fb->pitches[0]); + + vga_switcheroo_client_fb_set(adev->pdev, info); + return 0; + +out: + if (abo) { + + } + if (fb && ret) { + drm_gem_object_put(gobj); + drm_framebuffer_unregister_private(fb); + drm_framebuffer_cleanup(fb); + kfree(fb); + } + return ret; +} + +static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev) +{ + struct amdgpu_framebuffer *rfb = &rfbdev->rfb; + int i; + + drm_fb_helper_unregister_fbi(&rfbdev->helper); + + if (rfb->base.obj[0]) { + for (i = 0; i < rfb->base.format->num_planes; i++) + drm_gem_object_put(rfb->base.obj[0]); + amdgpufb_destroy_pinned_object(rfb->base.obj[0]); + rfb->base.obj[0] = NULL; + drm_framebuffer_unregister_private(&rfb->base); + drm_framebuffer_cleanup(&rfb->base); + } + drm_fb_helper_fini(&rfbdev->helper); + + return 0; +} + +static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = { + .fb_probe = amdgpufb_create, +}; + +int amdgpu_fbdev_init(struct amdgpu_device *adev) +{ + struct amdgpu_fbdev *rfbdev; + int bpp_sel = 32; + int ret; + + /* don't init fbdev on hw without DCE */ + if (!adev->mode_info.mode_config_initialized) + return 0; + + /* don't init fbdev if there are no connectors */ + if (list_empty(&adev_to_drm(adev)->mode_config.connector_list)) + return 0; + + /* select 8 bpp console on low vram cards */ + if (adev->gmc.real_vram_size <= (32*1024*1024)) + bpp_sel = 8; + + rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL); + if (!rfbdev) + return -ENOMEM; + + rfbdev->adev = adev; + adev->mode_info.rfbdev = rfbdev; + + drm_fb_helper_prepare(adev_to_drm(adev), &rfbdev->helper, + &amdgpu_fb_helper_funcs); + +#if defined(HAVE_DRM_FB_HELPER_INIT_2ARGS) + ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper); +#elif defined(HAVE_DRM_FB_HELPER_INIT_3ARGS) + ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper, + AMDGPUFB_CONN_LIMIT); +#else + ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper, + adev->mode_info.num_crtc, AMDGPUFB_CONN_LIMIT); +#endif + + if (ret) { + kfree(rfbdev); + return ret; + } + + /* disable all the possible outputs/crtcs before entering KMS mode */ + if (!amdgpu_device_has_dc_support(adev)) + drm_helper_disable_unused_functions(adev_to_drm(adev)); + + drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); + return 0; +} + +void amdgpu_fbdev_fini(struct amdgpu_device *adev) +{ + if (!adev->mode_info.rfbdev) + return; + + amdgpu_fbdev_destroy(adev_to_drm(adev), adev->mode_info.rfbdev); + kfree(adev->mode_info.rfbdev); + adev->mode_info.rfbdev = NULL; +} + +void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state) +{ + if (adev->mode_info.rfbdev) + drm_fb_helper_set_suspend_unlocked(&adev->mode_info.rfbdev->helper, + state); +} + +int amdgpu_fbdev_total_size(struct amdgpu_device *adev) +{ + struct amdgpu_bo *robj; + int size = 0; + + if (!adev->mode_info.rfbdev) + return 0; + + robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]); + size += amdgpu_bo_size(robj); + return size; +} + +bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) +{ + if (!adev->mode_info.rfbdev) + return false; + if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0])) + return true; + return false; +} diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 new file mode 100644 index 0000000000000..8c0d4b9e932ea --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 @@ -0,0 +1,35 @@ +dnl # +dnl # commit v5.6-rc2-1021-g2dea2d118217 +dnl # drm: Remove unused arg from drm_fb_helper_init +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DRMP_H + #include + #endif + #include + ], [ + drm_fb_helper_init(NULL, NULL); + ], [drm_fb_helper_init], [drivers/gpu/drm/drm_fb_helper.c], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_INIT_2ARGS, 1, + [drm_fb_helper_init() has 2 args]) + ], [ + dnl # + dnl # commit v4.10-rc5-1046-ge4563f6ba717 + dnl # drm: Rely on mode_config data for fb_helper initialization + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DRMP_H + #include + #endif + #include + ], [ + drm_fb_helper_init(NULL, NULL, 0); + ], [drm_fb_helper_init], [drivers/gpu/drm/drm_fb_helper.c], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_INIT_3ARGS, 1, + [drm_fb_helper_init() has 3 args]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a497aff232b48..781f0d97d3157 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -83,6 +83,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT + AC_AMDGPU_DRM_FB_HELPER_INIT AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD From e30cccda40e0261e4c70539c523e32a55a3396a4 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 9 May 2019 17:20:26 -0400 Subject: [PATCH 0291/2653] drm/amdkcl: Test whether format in struct drm_framebuffer is available v1: drm/amdkcl: Test whether drm_framebuffer structure contains format v2: drm/amd/autoconf: test whether struct drm_framebuffer have format v3: drm/amdkcl: fix for HAVE_DRM_FRAMEBUFFER_FORMAT v4: drm/amdkcl: accommodate to drmP.h removal for drm-framebuffer-format.m4 v5: drm/amdkcl: fix pitch setting on leacy kernel (Flora Cui) update pitch register as is done by commit 965ebe3d5d641("drm/amdgpu: Update pitch on page flips without DC as well") Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: chen gong Signed-off-by: Jack Gui Reviewed-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 17 ++++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 17 ++++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 17 ++++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 18 ++++++++++++++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ .../drm/amd/dkms/m4/drm-framebuffer-format.m4 | 23 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 8 files changed, 100 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 51c51f477d05c..7ff70856c88e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -266,7 +266,11 @@ static int amdgpufb_create(struct drm_fb_helper *helper, DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base); DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo)); +#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) + DRM_INFO("fb depth is %d\n", fb->depth); +#else DRM_INFO("fb depth is %d\n", fb->format->depth); +#endif DRM_INFO(" pitch is %d\n", fb->pitches[0]); vga_switcheroo_client_fb_set(adev->pdev, info); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index bf7c22f81cda3..cc6a0530a2c42 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -244,8 +244,13 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev, GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0); WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); /* update pitch */ +#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb->pitches[0] / fb->format->cpp[0]); +#else + WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, + fb->pitches[0] / (fb->bits_per_pixel / 8)); +#endif /* update the primary scanout address */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -1895,7 +1900,11 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); +#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) + switch (target_fb->pixel_format) { +#else switch (target_fb->format->format) { +#endif case DRM_FORMAT_C8: fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); @@ -1979,7 +1988,11 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, break; default: DRM_ERROR("Unsupported screen format %p4cc\n", +#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) &target_fb->format->format); +#else + &target_fb->pixel_format); +#endif return -EINVAL; } @@ -2054,7 +2067,11 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); +#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) + fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); +#else fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; +#endif WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); dce_v10_0_grph_enable(crtc, true); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 47e05783c4a0e..d55b21214ebde 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -268,8 +268,13 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev, GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0); WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); /* update pitch */ +#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb->pitches[0] / fb->format->cpp[0]); +#else + WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, + fb->pitches[0] / (fb->bits_per_pixel / 8)); +#endif /* update the scanout addresses */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -1945,7 +1950,11 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); +#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) + switch (target_fb->pixel_format) { +#else switch (target_fb->format->format) { +#endif case DRM_FORMAT_C8: fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); @@ -2029,7 +2038,11 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, break; default: DRM_ERROR("Unsupported screen format %p4cc\n", +#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) &target_fb->format->format); +#else + &target_fb->pixel_format); +#endif return -EINVAL; } @@ -2104,7 +2117,11 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); +#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) + fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); +#else fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; +#endif WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); dce_v11_0_grph_enable(crtc, true); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 276c025c4c03d..8b7261fe1f5a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -208,8 +208,13 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev, WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); /* update pitch */ +#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb->pitches[0] / fb->format->cpp[0]); +#else + WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, + fb->pitches[0] / (fb->bits_per_pixel / 8)); +#endif /* update the scanout addresses */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -1930,7 +1935,11 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, amdgpu_bo_get_tiling_flags(abo, &tiling_flags); amdgpu_bo_unreserve(abo); +#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) + switch (target_fb->pixel_format) { +#else switch (target_fb->format->format) { +#endif case DRM_FORMAT_C8: fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); @@ -2006,7 +2015,11 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, break; default: DRM_ERROR("Unsupported screen format %p4cc\n", +#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) &target_fb->format->format); +#else + &target_fb->pixel_format); +#endif return -EINVAL; } @@ -2069,7 +2082,11 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); +#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) + fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); +#else fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; +#endif WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); dce_v6_0_grph_enable(crtc, true); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index e62ccf9eb73de..755c53283928d 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -191,9 +191,13 @@ static void dce_v8_0_page_flip(struct amdgpu_device *adev, /* flip at hsync for async, default is vsync */ WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); - /* update pitch */ +#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb->pitches[0] / fb->format->cpp[0]); +#else + WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, + fb->pitches[0] / (fb->bits_per_pixel / 8)); +#endif /* update the primary scanout addresses */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -1842,7 +1846,11 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); +#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) + switch (target_fb->pixel_format) { +#else switch (target_fb->format->format) { +#endif case DRM_FORMAT_C8: fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); @@ -1918,7 +1926,11 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, break; default: DRM_ERROR("Unsupported screen format %p4cc\n", +#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) &target_fb->format->format); +#else + &target_fb->pixel_format); +#endif return -EINVAL; } @@ -1981,7 +1993,11 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); +#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) + fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); +#else fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; +#endif WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); dce_v8_0_grph_enable(crtc, true); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 769d7406481af..b2abb3f2ff474 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11161,7 +11161,11 @@ static bool should_reset_plane(struct drm_atomic_state *state, continue; /* Pixel format changes can require bandwidth updates. */ +#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT + if (old_other_state->fb->pixel_format != new_other_state->fb->pixel_format) +#else if (old_other_state->fb->format != new_other_state->fb->format) +#endif return true; old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 new file mode 100644 index 0000000000000..977ed577e27c8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # commit e14c23c647abfc1fed96a55ba376cd9675a54098 +dnl # drm: Store a pointer to drm_format_info under drm_framebuffer +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_framebuffer *foo = NULL; + foo->format = NULL; + ], [ + AC_DEFINE(HAVE_DRM_FRAMEBUFFER_FORMAT, 1, + [whether struct drm_framebuffer have format]) + ]) + ], [ + AC_DEFINE(HAVE_DRM_FRAMEBUFFER_FORMAT, 1, + [whether struct drm_framebuffer have format]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 781f0d97d3157..a3030fc72c596 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -84,6 +84,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_FB_HELPER_INIT + AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD From 1dae19436e0338675b642cfde2f8488687e08e12 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 11 Dec 2019 17:55:59 +0800 Subject: [PATCH 0292/2653] drm/amdkcl: check drm_get_format_info() is available Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 6 ++++++ drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 20 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 7ff70856c88e1..9db063a9e445c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -121,7 +121,9 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **gobj_p) { +#ifdef HAVE_DRM_GET_FORMAT_INFO const struct drm_format_info *info; +#endif struct amdgpu_device *adev = rfbdev->adev; struct drm_gem_object *gobj = NULL; struct amdgpu_bo *abo = NULL; @@ -135,8 +137,12 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | AMDGPU_GEM_CREATE_VRAM_CLEARED; +#ifdef HAVE_DRM_GET_FORMAT_INFO info = drm_get_format_info(adev_to_drm(adev), mode_cmd); cpp = info->cpp[0]; +#else + cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0); +#endif /* need to align pitch with crtc limits */ mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 new file mode 100644 index 0000000000000..5c797f77620f5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit v4.11-rc1-237-g6a0f9ebfc5e7 +dnl # drm: Add mode_config .get_format_info() hook +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GET_FORMAT_INFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_get_format_info], + [drivers/gpu/drm/drm_fourcc.c], [ + AC_DEFINE(HAVE_DRM_GET_FORMAT_INFO, 1, + [drm_get_format_info() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a3030fc72c596..bf900dc220e7e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -85,6 +85,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_FB_HELPER_INIT AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT + AC_AMDGPU_DRM_GET_FORMAT_INFO AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD From 3eb6118d4d79061bc056b168d734a594eb7848c6 Mon Sep 17 00:00:00 2001 From: changzhu Date: Mon, 13 Aug 2018 17:21:10 +0800 Subject: [PATCH 0293/2653] drm/amdkcl: [4.16] fix drm .last code, .output_poll_changed conflict .last_close and .output_poll_changed helpers are introduced in the same commit v4.14-rc3-576-g304a4f6accac drm_fb_helper_output_poll_changed & drm_fb_helper_lastclose can't be in amdkcl like other nonexistent symbols because there's no way to get fb_helper pointer from drm_device. amdgpu_device is required to get fb_helper pointer in this case. drm_device->fb_helper is introduced in v4.14-rc3-575-g29ad20b22c8f. and the 2 helper are introduced in v4.14-rc3-576-g304a4f6accac. Squash of 9d340fac6ea4 drm/amdkcl: add drm_fb_helper_output_poll_changed & drm_fb_helper_lastclose 686ea5e4ffe8 drm/amdkcl: refactor check for HAVE_DRM_FB_HELPER_LASTCLOSE 9c3af6d1cc70 drm/amdkcl: [4.16] fix drm .last code, .output_poll_changed conflict ae16f355fd44 drm/amdkcl: Test whether drm_fb_helper_lastclose is available 394828020901 drm/amdkcl: fix license for kcl backport part Signed-off-by: Yifan Zhang Signed-off-by: Slava Grigorev Signed-off-by: changzhu Reviewed-by: Rui Teng Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Flora Cui Acked-by: Feifei Xu Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../include/kcl/kcl_amdgpu_drm_fb_helper.h | 39 +++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 786b0e8246e62..c75da3ec0fcb5 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -51,5 +51,6 @@ #include #include #include +#include "kcl/kcl_amdgpu_drm_fb_helper.h" #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h new file mode 100644 index 0000000000000..7b5938a2cd3ce --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006-2009 Red Hat Inc. + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * + * DRM framebuffer helper functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Dave Airlie + * Jesse Barnes + */ +#ifndef AMDGPU_BACKPORT_KCL_AMDGPU_DRM_FB_HELPER_H +#define AMDGPU_BACKPORT_KCL_AMDGPU_DRM_FB_HELPER_H + +#include + +#ifndef HAVE_DRM_FB_HELPER_LASTCLOSE +void drm_fb_helper_lastclose(struct drm_device *dev); +void drm_fb_helper_output_poll_changed(struct drm_device *dev); +#endif +#endif From 14b44a40f482f269895ede41867d8c9023fedbd0 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Wed, 15 Aug 2018 17:21:02 +0800 Subject: [PATCH 0294/2653] drm/amdkcl: fake drm_gem_fb_get_obj & kcl_drm_gem_fb_set_obj drm_gem_fb_get_obj() is introdued in v4.13-rc2-421-g4c3dbb2c312c. same with include/drm/drm_gem_framebuffer_helper.h fake a kcl copy for legacy kernel. Squash of e1357d7a01b8 drm/amdkcl: fake drm_gem_fb_get_obj & kcl_drm_gem_fb_set_obj c5ec212d2f24 drm/amdkcl: [4.14] fix drm_gem_object compile error Reviewed-by: Kevin Wang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Change-Id: I2c087d77e289caabc6f5215f2bd54dc0e33e634e Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 8 ++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 3 +++ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 6 +++--- .../include/kcl/kcl_amdgpu_drm_fb_helper.h | 21 +++++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 +- 9 files changed, 44 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index feaa4c3e163dd..2fcff36b2d322 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -217,13 +217,13 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; /* schedule unpin of the old buffer */ - obj = crtc->primary->fb->obj[0]; + obj = drm_gem_fb_get_obj(crtc->primary->fb, 0); /* take a reference to the old object */ work->old_abo = gem_to_amdgpu_bo(obj); amdgpu_bo_ref(work->old_abo); - obj = fb->obj[0]; + obj = drm_gem_fb_get_obj(fb, 0); new_abo = gem_to_amdgpu_bo(obj); /* pin the new buffer */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 9db063a9e445c..8a71c31f394a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -298,15 +298,17 @@ static int amdgpufb_create(struct drm_fb_helper *helper, static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev) { struct amdgpu_framebuffer *rfb = &rfbdev->rfb; + struct drm_gem_object *obj = NULL; int i; drm_fb_helper_unregister_fbi(&rfbdev->helper); + obj = drm_gem_fb_get_obj(&rfb->base, 0); if (rfb->base.obj[0]) { for (i = 0; i < rfb->base.format->num_planes; i++) drm_gem_object_put(rfb->base.obj[0]); amdgpufb_destroy_pinned_object(rfb->base.obj[0]); - rfb->base.obj[0] = NULL; + kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); drm_framebuffer_unregister_private(&rfb->base); drm_framebuffer_cleanup(&rfb->base); } @@ -395,7 +397,7 @@ int amdgpu_fbdev_total_size(struct amdgpu_device *adev) if (!adev->mode_info.rfbdev) return 0; - robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]); + robj = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&adev->mode_info.rfbdev->rfb.base, 0)); size += amdgpu_bo_size(robj); return size; } @@ -404,7 +406,7 @@ bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) { if (!adev->mode_info.rfbdev) return false; - if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0])) + if (robj == gem_to_amdgpu_bo(drm_gem_fb_get_obj(&adev->mode_info.rfbdev->rfb.base, 0))) return true; return false; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 6da4f946cac00..35b29d5f490ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -298,6 +298,9 @@ struct amdgpu_display_funcs { struct amdgpu_framebuffer { struct drm_framebuffer base; +#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H + struct drm_gem_object *obj; +#endif uint64_t tiling_flags; bool tmz_surface; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index cc6a0530a2c42..90756ea63a83f 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -1879,7 +1879,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, /* If atomic, assume fb object is pinned & idle & fenced and * just update base pointers */ - obj = target_fb->obj[0]; + obj = drm_gem_fb_get_obj(target_fb, 0); abo = gem_to_amdgpu_bo(obj); r = amdgpu_bo_reserve(abo, false); if (unlikely(r != 0)) @@ -2092,7 +2092,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); if (!atomic && fb && fb != crtc->primary->fb) { - abo = gem_to_amdgpu_bo(fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r != 0)) return r; @@ -2578,7 +2578,7 @@ static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) int r; struct amdgpu_bo *abo; - abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(crtc->primary->fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r)) DRM_ERROR("failed to reserve abo before unpin\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index d55b21214ebde..cbdfebdf5dc76 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -1929,7 +1929,7 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, /* If atomic, assume fb object is pinned & idle & fenced and * just update base pointers */ - obj = target_fb->obj[0]; + obj = drm_gem_fb_get_obj(target_fb, 0); abo = gem_to_amdgpu_bo(obj); r = amdgpu_bo_reserve(abo, false); if (unlikely(r != 0)) @@ -2142,7 +2142,7 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); if (!atomic && fb && fb != crtc->primary->fb) { - abo = gem_to_amdgpu_bo(fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r != 0)) return r; @@ -2662,7 +2662,7 @@ static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) int r; struct amdgpu_bo *abo; - abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(crtc->primary->fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r)) DRM_ERROR("failed to reserve abo before unpin\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 8b7261fe1f5a3..63364b6961d2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -1916,7 +1916,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, /* If atomic, assume fb object is pinned & idle & fenced and * just update base pointers */ - obj = target_fb->obj[0]; + obj = drm_gem_fb_get_obj(target_fb, 0); abo = gem_to_amdgpu_bo(obj); r = amdgpu_bo_reserve(abo, false); if (unlikely(r != 0)) @@ -2107,7 +2107,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); if (!atomic && fb && fb != crtc->primary->fb) { - abo = gem_to_amdgpu_bo(fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r != 0)) return r; @@ -2546,7 +2546,7 @@ static void dce_v6_0_crtc_disable(struct drm_crtc *crtc) int r; struct amdgpu_bo *abo; - abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(crtc->primary->fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r)) DRM_ERROR("failed to reserve abo before unpin\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 755c53283928d..352aa749dc678 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -1825,7 +1825,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, /* If atomic, assume fb object is pinned & idle & fenced and * just update base pointers */ - obj = target_fb->obj[0]; + obj = drm_gem_fb_get_obj(target_fb, 0); abo = gem_to_amdgpu_bo(obj); r = amdgpu_bo_reserve(abo, false); if (unlikely(r != 0)) @@ -2018,7 +2018,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); if (!atomic && fb && fb != crtc->primary->fb) { - abo = gem_to_amdgpu_bo(fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r != 0)) return r; @@ -2496,7 +2496,7 @@ static void dce_v8_0_crtc_disable(struct drm_crtc *crtc) int r; struct amdgpu_bo *abo; - abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(crtc->primary->fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r)) DRM_ERROR("failed to reserve abo before unpin\n"); diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h index 7b5938a2cd3ce..7e316b60c45f9 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -31,9 +31,30 @@ #define AMDGPU_BACKPORT_KCL_AMDGPU_DRM_FB_HELPER_H #include +#include +#include "amdgpu.h" #ifndef HAVE_DRM_FB_HELPER_LASTCLOSE void drm_fb_helper_lastclose(struct drm_device *dev); void drm_fb_helper_output_poll_changed(struct drm_device *dev); #endif + +static inline +void kcl_drm_gem_fb_set_obj(struct drm_framebuffer *fb, int index, struct drm_gem_object *obj) +{ +#ifdef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H + if (fb) + fb->obj[index] = obj; +#else + struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); + (void)index; /* for compile un-used warning */ + if (afb) + afb->obj = obj; +#endif +} +#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H +struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, + unsigned int plane); +#endif + #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index b7c6e8d134350..38ae5a14ffb49 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1030,7 +1030,7 @@ static void amdgpu_dm_plane_helper_cleanup_fb(struct drm_plane *plane, if (!old_state->fb) return; - rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); + rbo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(old_state->fb, 0)); r = amdgpu_bo_reserve(rbo, false); if (unlikely(r)) { DRM_ERROR("failed to reserve rbo before unpin\n"); From d499c9e3dec766ed55e9828bd62760427feba1ca Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 15 Jun 2020 15:36:36 +0800 Subject: [PATCH 0295/2653] drm/amdkcl: fake drm_gem_fb_destroy & drm_gem_fb_create_handle the 2 api are introduced in commit v4.13-rc2-421-g4c3dbb2c312c, could leverage test for drm/drm_gem_framebuffer_helper.h Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Change-Id: I55b7e056751e522ef827cadb905468675e342d96 --- .../drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h index 7e316b60c45f9..40a89aea46e78 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -55,6 +55,9 @@ void kcl_drm_gem_fb_set_obj(struct drm_framebuffer *fb, int index, struct drm_ge #ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, unsigned int plane); +void drm_gem_fb_destroy(struct drm_framebuffer *fb); +int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, + unsigned int *handle); #endif #endif From 64bf91e3a23880effc98a560d578ddb6e71791af Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 9 Jul 2024 10:29:27 +0800 Subject: [PATCH 0296/2653] drm/amdkcl: test drm_device->driver_features Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 18 +++++++++++++--- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/struct_drm_device.m4 | 21 +++++++++++++++++++ 3 files changed, 37 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 43d880e6f8751..dbcaeee5ab126 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2429,8 +2429,17 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, kcl_drm_vma_offset_manager_init(ddev->vma_offset_manager); +#ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; +#else + /* warn the user if they mix atomic and non-atomic capable GPUs */ + if ((kms_driver.driver_features & DRIVER_ATOMIC) && !supports_atomic) + DRM_ERROR("Mixing atomic and non-atomic capable GPUs!\n"); + /* support atomic early so the atomic debugfs stuff gets created */ + if (supports_atomic) + kms_driver.driver_features |= DRIVER_ATOMIC; +#endif kcl_pci_configure_extended_tags(pdev); ret = pci_enable_device(pdev); @@ -3080,9 +3089,12 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { static const struct drm_driver amdgpu_kms_driver = { .driver_features = - DRIVER_ATOMIC | - DRIVER_GEM | - DRIVER_RENDER | DRIVER_MODESET + 0 +#ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES + | DRIVER_ATOMIC +#endif /* HAVE_DRM_DEVICE_DRIVER_FEATURES */ + | DRIVER_GEM + | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ #ifdef HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE | DRIVER_SYNCOBJ_TIMELINE diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index bf900dc220e7e..0f6e5d5e03484 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -70,6 +70,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MM_INSERT_MODE AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL + AC_AMDGPU_STRUCT_DRM_DEVICE AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_MEM_ENCRYPT_ACTIVE diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 new file mode 100644 index 0000000000000..73fd46cf9315c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v4.19-rc1-194-g18ace11f87e6 +dnl # drm: Introduce per-device driver_features +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_device *ddev = NULL; + ddev->driver_features = 0; + ],[ + AC_DEFINE(HAVE_DRM_DEVICE_DRIVER_FEATURES, 1, + [dev_device->driver_features is available]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_DEVICE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES + ]) +]) From 31417e6ee05f43e170b37211da603327c12b3905 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Wed, 18 Sep 2019 16:37:51 +0800 Subject: [PATCH 0297/2653] drm/amdkcl: Test whether drm_driver->driver_features available test whether DRIVER_ATOMIC/DRIVER_SYNCOBJ_TIMELINE/DRIVER_IRQ_SHARED are available v1: drm/amdkcl: acommodate drmP.h drop for drm-driver-feature.m4 v2: drm/amdkcl: test DRIVER_PRIME is available Signed-off-by: Adam Yang Signed-off-by: Flora Cui Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 +++ .../gpu/drm/amd/dkms/m4/drm-driver-feature.m4 | 78 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 88 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index dbcaeee5ab126..b65cae593b979 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2429,6 +2429,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, kcl_drm_vma_offset_manager_init(ddev->vma_offset_manager); +#ifdef HAVE_DRM_DRV_DRIVER_ATOMIC #ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; @@ -2439,6 +2440,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, /* support atomic early so the atomic debugfs stuff gets created */ if (supports_atomic) kms_driver.driver_features |= DRIVER_ATOMIC; +#endif #endif kcl_pci_configure_extended_tags(pdev); @@ -3093,6 +3095,13 @@ static const struct drm_driver amdgpu_kms_driver = { #ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES | DRIVER_ATOMIC #endif /* HAVE_DRM_DEVICE_DRIVER_FEATURES */ + | DRIVER_HAVE_IRQ +#ifdef HAVE_DRM_DRV_DRIVER_IRQ_SHARED + | DRIVER_IRQ_SHARED +#endif /* HAVE_DRM_DRV_DRIVER_IRQ_SHARED */ +#ifdef HAVE_DRM_DRV_DRIVER_PRIME + | DRIVER_PRIME +#endif /* HAVE_DRM_DRV_DRIVER_PRIME */ | DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 new file mode 100644 index 0000000000000..3afe53a169b8c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 @@ -0,0 +1,78 @@ +dnl # +dnl # commit 88a48e297b3a3bac6022c03babfb038f1a886cea +dnl # drm: add atomic properties +dnl # commit 0e2a933b02c972919f7478364177eb76cd4ae00d +dnl # drm: Switch DRIVER_ flags to an enum +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int _ = DRIVER_ATOMIC; + ], [ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_ATOMIC, 1, [ + drm_driver_feature DRIVER_ATOMIC is available]) + ]) + ], [ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_ATOMIC, 1, [ + drm_driver_feature DRIVER_ATOMIC is available]) + ]) + ]) + + dnl # + dnl # commit: 060cebb20cdbcd3185d593e7194fa7a738201817 + dnl # drm: introduce a capability flag for syncobj timeline support + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int _ = DRIVER_SYNCOBJ_TIMELINE; + ],[ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE, 1, [ + drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available]) + ]) + ], [ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE, 1, [ + drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available]) + ]) + ]) + + dnl # + dnl # commit: 1ff494813bafa127ecba1160262ba39b2fdde7ba + dnl # drm/irq: Ditch DRIVER_IRQ_SHARED + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int _ = DRIVER_IRQ_SHARED; + ],[ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_IRQ_SHARED, 1, [ + drm_driver_feature DRIVER_IRQ_SHARED is available]) + ]) + ]) + ]) + + dnl # + dnl # commit: v5.2-rc5-867-g0424fdaf883a + dnl # drm/prime: Actually remove DRIVER_PRIME everywhere + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int _ = DRIVER_PRIME; + ],[ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_PRIME, 1, [ + drm_driver_feature DRIVER_PRIME is available]) + ]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0f6e5d5e03484..e488c5030fad9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -71,6 +71,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL AC_AMDGPU_STRUCT_DRM_DEVICE + AC_AMDGPU_DRM_DRIVER_FEATURE AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_MEM_ENCRYPT_ACTIVE From 0639acdfb732a5df0900be91622299175a69ecba Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 22 Apr 2020 21:26:01 +0800 Subject: [PATCH 0298/2653] drm/amdkcl: test drm_device->open_count squash of b6521032d361 drm/amdkcl: fix drm/drm_device.h in m4 578fa0c102a1 drm/amdkcl: add AC_AMDGPU_STRUCT_DRM_DEVICE Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ .../gpu/drm/amd/dkms/m4/struct_drm_device.m4 | 17 +++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 9796415b58e3c..ce28db4ba081d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2243,7 +2243,11 @@ static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) * locking inversion with the driver load path. And the access here is * completely racy anyway. So don't bother with locking for now. */ +#ifdef HAVE_DRM_DEVICE_OPEN_COUNT_INT + return dev->open_count == 0; +#else return atomic_read(&dev->open_count) == 0; +#endif } static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 index 73fd46cf9315c..7016ff6694c88 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 @@ -14,8 +14,25 @@ AC_DEFUN([AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES], [ ]) ]) +dnl # +dnl # commit v5.5-rc2-1419-g7e13ad896484 +dnl # drm: Avoid drm_global_mutex for simple inc/dec of dev->open_count +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEVICE_OPEN_COUNT], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_device *ddev = NULL; + ddev->open_count = 0; + ],[ + AC_DEFINE(HAVE_DRM_DEVICE_OPEN_COUNT_INT, 1, + [drm_device->open_count is int]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_DEVICE], [ AC_KERNEL_DO_BACKGROUND([ AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES + AC_AMDGPU_DRM_DEVICE_OPEN_COUNT ]) ]) From c4eb0868506009abdd7dcdc7c14205064658c21d Mon Sep 17 00:00:00 2001 From: Yintian Tao Date: Mon, 2 Mar 2020 17:09:57 +0800 Subject: [PATCH 0299/2653] drm/amdkcl: get drm_dev reference Before 4.18.0, drm_dev_unplug will confirm dev->open_count to detemine whether to call drm_dev_put(), it will raise the problem below. Therefore, to get drm_dev_reference ensure not release drm_device before amdgpu_driver_unload_kms(). [ 43.055735] ------------[ cut here ]------------ [ 43.055736] Memory manager not clean during takedown. [ 43.055777] WARNING: CPU: 1 PID: 2807 at /build/linux-hwe-9KJ07q/linux-hwe-4.18.0/drivers/gpu/drm/drm_mm.c:913 drm_mm_takedown+0x24/0x30 [drm] [ 43.055778] Modules linked in: amdgpu(OE-) amd_sched(OE) amdttm(OE) amdkcl(OE) amd_iommu_v2 drm_kms_helper drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect sysimgblt snd_hda_codec_generic nfit kvm_intel kvm irqbypass crct10dif_pclmul crc32_pclmul snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm ghash_clmulni_intel snd_seq_midi snd_seq_midi_event pcbc snd_rawmidi snd_seq snd_seq_device aesni_intel snd_timer joydev aes_x86_64 crypto_simd cryptd glue_helper snd soundcore input_leds mac_hid serio_raw qemu_fw_cfg binfmt_misc sch_fq_codel nfsd auth_rpcgss nfs_acl lockd grace sunrpc parport_pc ppdev lp parport ip_tables x_tables autofs4 hid_generic floppy usbhid psmouse hid i2c_piix4 e1000 pata_acpi [ 43.055819] CPU: 1 PID: 2807 Comm: modprobe Tainted: G OE 4.18.0-15-generic #16~18.04.1-Ubuntu [ 43.055820] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.12.0-1 04/01/2014 [ 43.055830] RIP: 0010:drm_mm_takedown+0x24/0x30 [drm] [ 43.055831] Code: 84 00 00 00 00 00 0f 1f 44 00 00 48 8b 47 38 48 83 c7 38 48 39 c7 75 02 f3 c3 55 48 c7 c7 38 33 80 c0 48 89 e5 e8 1c 41 ec d0 <0f> 0b 5d c3 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 55 48 89 e5 41 [ 43.055857] RSP: 0018:ffffae33c1393d28 EFLAGS: 00010286 [ 43.055859] RAX: 0000000000000000 RBX: ffff9651b4a29800 RCX: 0000000000000006 [ 43.055860] RDX: 0000000000000007 RSI: 0000000000000096 RDI: ffff9651bfc964b0 [ 43.055861] RBP: ffffae33c1393d28 R08: 00000000000002a6 R09: 0000000000000004 [ 43.055861] R10: ffffae33c1393d20 R11: 0000000000000001 R12: ffff9651ba6cb000 [ 43.055863] R13: ffff9651b7f40000 R14: ffffffffc0de3a10 R15: ffff9651ba5c6460 [ 43.055864] FS: 00007f1d3c08d540(0000) GS:ffff9651bfc80000(0000) knlGS:0000000000000000 [ 43.055865] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 43.055866] CR2: 00005630a5831640 CR3: 000000012e274004 CR4: 00000000003606e0 [ 43.055870] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 43.055871] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 43.055871] Call Trace: [ 43.055885] drm_vma_offset_manager_destroy+0x1b/0x30 [drm] [ 43.055894] drm_gem_destroy+0x19/0x40 [drm] [ 43.055903] drm_dev_fini+0x7f/0x90 [drm] [ 43.055911] drm_dev_release+0x2b/0x40 [drm] [ 43.055919] drm_dev_unplug+0x64/0x80 [drm] [ 43.055994] amdgpu_pci_remove+0x39/0x70 [amdgpu] [ 43.055998] pci_device_remove+0x3e/0xc0 [ 43.056001] device_release_driver_internal+0x18a/0x260 [ 43.056003] driver_detach+0x3f/0x80 [ 43.056004] bus_remove_driver+0x59/0xd0 [ 43.056006] driver_unregister+0x2c/0x40 [ 43.056008] pci_unregister_driver+0x22/0xa0 [ 43.056087] amdgpu_exit+0x15/0x57c [amdgpu] [ 43.056090] __x64_sys_delete_module+0x146/0x280 [ 43.056094] do_syscall_64+0x5a/0x120 [ 43.056097] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 43.056098] RIP: 0033:0x7f1d3bbb31b7 v2: use < 4.19.0 instead of <= 4.18.0 v3: move the version check into kcl v4: drm_dev_unplug() drop ref change in commit bd53280ef042 ("drm/drv: Fix incorrect resolution of merge conflict") rework kcl wrapper for the ref change Squash of 7109e9b49244 drm/amdkcl: rework kcl wrapper for drm_dev_unplug() e8364b615641 drm/amdkcl: add kcl wrapper for drm_dev_unplug 4e12efdfbcd4 drm/amdkcl: get drm_dev reference Signed-off-by: Yintian Tao Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- .../drm/amd/amdkcl/kcl_drm_atomic_helper.c | 2 +- include/kcl/backport/kcl_drm_drv.h | 52 +++++++++++++++++++ 2 files changed, 53 insertions(+), 1 deletion(-) create mode 100644 include/kcl/backport/kcl_drm_drv.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c index c11911f2dcbc8..4ef77c1846213 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -26,7 +26,7 @@ * Daniel Vetter */ #include -#include +#include #ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, diff --git a/include/kcl/backport/kcl_drm_drv.h b/include/kcl/backport/kcl_drm_drv.h new file mode 100644 index 0000000000000..dcc5c195b2d08 --- /dev/null +++ b/include/kcl/backport/kcl_drm_drv.h @@ -0,0 +1,52 @@ +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * Copyright 2016 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __KCL_BACKPORT_KCL_DRM_DRV_H__ +#define __KCL_BACKPORT_KCL_DRM_DRV_H__ + +/* + * v5.1-rc5-1150-gbd53280ef042 drm/drv: Fix incorrect resolution of merge conflict + * v5.1-rc2-5-g3f04e0a6cfeb drm: Fix drm_release() and device unplug + */ +#if DRM_VERSION_CODE < DRM_VERSION(5, 2, 0) +static inline +void _kcl_drm_dev_unplug(struct drm_device *dev) +{ + unsigned int prev, post; + + drm_dev_get(dev); + + prev = kref_read(&dev->ref); + drm_dev_unplug(dev); + post = kref_read(&dev->ref); + + if (prev == post) + drm_dev_put(dev); +} +#define drm_dev_unplug _kcl_drm_dev_unplug +#endif + +#endif From d5788d2839d88b403ebf5dc1b6781bbe6a81ade1 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 12 Oct 2023 14:38:11 +0800 Subject: [PATCH 0300/2653] drm/amdkcl: add AMDKCL_AMDGPU_DEBUGFS_CLEANUP for debugfs_cleanup. macro AMDKCL_AMDGPU_DEBUGFS_CLEANUP would be more friendly for hybrid branch maintaining. Signed-off-by: Flora Cui Acked-by: Feifei Xu Change-Id: I006ec85bf1e697d4fb5173023f4f4ee9e81bf286 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 19 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h | 5 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++++++ include/kcl/backport/kcl_drm_backport.h | 8 ++++++++ 4 files changed, 38 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 0e6e2e2acf5b5..c7d109ff21264 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -42,6 +42,25 @@ #if defined(CONFIG_DEBUG_FS) +#if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) +void amdgpu_debugfs_cleanup(struct drm_minor *minor) +{ + struct drm_info_node *node, *tmp; + + if (!&minor->debugfs_root) + return; + + mutex_lock(&minor->debugfs_lock); + list_for_each_entry_safe(node, tmp, + &minor->debugfs_list, list) { + debugfs_remove(node->dent); + list_del(&node->list); + kfree(node); + } + mutex_unlock(&minor->debugfs_lock); +} +#endif + /** * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h index e7b3c38e51864..79bfd1d1871ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h @@ -26,6 +26,11 @@ * Debugfs */ +#if defined(CONFIG_DEBUG_FS) +#if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) +void amdgpu_debugfs_cleanup(struct drm_minor *minor); +#endif +#endif int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); int amdgpu_debugfs_init(struct amdgpu_device *adev); void amdgpu_debugfs_fini(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index b65cae593b979..6e659060699c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3111,6 +3111,12 @@ static const struct drm_driver amdgpu_kms_driver = { , .open = amdgpu_driver_open_kms, .postclose = amdgpu_driver_postclose_kms, +#if defined(CONFIG_DEBUG_FS) +#if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) + .debugfs_cleanup = amdgpu_debugfs_cleanup, +#endif +#endif + .irq_handler = amdgpu_irq_handler, .ioctls = amdgpu_ioctls_kms, .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), .dumb_create = amdgpu_mode_dumb_create, diff --git a/include/kcl/backport/kcl_drm_backport.h b/include/kcl/backport/kcl_drm_backport.h index 1450036960b9c..84ca7b867d62d 100644 --- a/include/kcl/backport/kcl_drm_backport.h +++ b/include/kcl/backport/kcl_drm_backport.h @@ -2,6 +2,14 @@ #ifndef AMDKCL_DRM_BACKPORT_H #define AMDKCL_DRM_BACKPORT_H +/* + * commit v4.10-rc3-539-g086f2e5cde74 + * drm: debugfs: Remove all files automatically on cleanup + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 11, 0) +#define AMDKCL_AMDGPU_DEBUGFS_CLEANUP +#endif + #if DRM_VERSION_CODE >= DRM_VERSION(4, 17, 0) #define AMDKCL_AMDGPU_DMABUF_OPS #endif From 224065df4133c3b118619443e116ef7045119873 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Apr 2020 14:42:32 +0800 Subject: [PATCH 0301/2653] drm/amdkcl: for drm_crtc_funcs->get_vblank_timestamp() add vblank macros AC_AMDGPU_GET_SCANOUT_POSITION_IN_DRM_DRIVER AC_AMDGPU_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER AC_AMDGPU_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS it is a squash of: commit 56d1d766045efd0a35ec331be7f176482022ac58 Author: Yifan Zhang Date: Tue Aug 6 13:46:25 2019 +0800 drm/amdkcl: use unsigned pipe v1: drm/amdkcl: drop kcl_amdgpu.c v2: merge unsigned pipe check into get-scanout-position Change-Id: If81006bf54584b6aff68082e0f4be48d1758cd7c Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Adam Yang Signed-off-by: Jack Gui Signed-off-by: Flora Cui commit 5e00d69a73fb4c5c0f888dcdeaca25bd42add60b Author: Slava Grigorev Date: Fri Feb 7 16:13:47 2020 -0500 drm/amdkcl: introduce parallel autoconf tests execution Change-Id: Ifff3054a6cd9403a6a34135bf5fb942f5aa760f8 Signed-off-by: Slava Grigorev drm/amdkcl: Test whether get_scanout_position has flags v1: drm/amd/autoconf: add a missing GET_SCANOUT_POSITION_HAVE_FLAGS v2: drm/amd/autoconf: fix drm_driver->get_scanout_position v3: drm/amdkcl: fix drm_driver->get_vblank_timestamp v4: drm/amd/autoconf: fix kcl_amdgpu_get_vblank_timestamp_kms() v5: drm/amdkcl: fix missing amdgpu_get_vblank_timestamp_kms() v6: drm/amd/autoconf: test drm_calc_vbltimestamp_from_scanoutpos() v7: fix macro for amdgpu_get_vblank_timestamp_kms() v8: drm/amdkcl: fix check for drm_driver->get_vblank_timestamp v9: drm/amdkcl: accommodate to drmP.h removal for drm-calc-vbltimestamp-from-scanoutpos.m4 v10: drm/amdkcl: accommodate to drmP.h removal for get-vblank-timestamp-in-struct-drm-driver.m4 v11: drm/amdkcl: merge use-unsigned-pipe.m4 into get-scanout-position-in-struct-drm-driver.m4 v12: drm/amdkcl: accommodate to drmP.h removal for get-scanout-position-in-struct-drm-driver.m4 Signed-off-by: Yifan Zhang Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Signed-off-by: Jack Gui History-1: v2.6.37-rc3-1-g27641c3f003e int (*get_scanout_position) (struct drm_device *dev, int crtc, int *vpos, int *hpos); v3.12-rc3-485-g8f6fce03ddaf - int *vpos, int *hpos); + int *vpos, int *hpos, ktime_t *stime, + ktime_t *etime); v4.3-rc2-44-g3bb403bf421b - int *vpos, int *hpos, ktime_t *stime, - ktime_t *etime); + int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + ` const struct drm_display_mode *mode); v4.3-rc3-73-g88e72717c2de - int crtc, + unsigned int pipe, v4.11-rc7-1902-g1bf6ad622b9b - int (*get_scanout_position) (struct drm_device *dev, unsigned int pipe, - unsigned int flags, int *vpos, int *hpos, + bool (*get_scanout_position) (struct drm_device *dev, unsigned int pipe, + bool in_vblank_irq, int *vpos, int *hpos, History-2: v2.6.37-rc3-1-g27641c3f003e introduce int (*get_vblank_timestamp) (struct drm_device *dev, int crtc, int *max_error, struct timeval *vblank_time, unsigned flags); v4.3-rc3-73-g88e72717c2de - int (*get_vblank_timestamp) (struct drm_device *dev, int crtc, + int (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe, v4.11-rc7-1899-gd673c02c4bdb - int (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe, + bool (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe, v4.11-rc7-1900-g3fcdcb270936 - unsigned flags); + bool in_vblank_irq); v4.14-rc3-721-g67680d3c0464 - struct timeval *vblank_time, + ktime_t *vblank_time, History-3: v2.6.37-rc3-1-g27641c3f003e int drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev, int crtc, int *max_error, struct timeval *vblank_time, unsigned flags, struct drm_crtc *refcrtc) v3.13-rc8-550-g7da903ef0485 - struct drm_crtc *refcrtc); + const struct drm_crtc *refcrtc, + const struct drm_display_mode *mode); v4.2-rc3-517-gcc1ef118fc09 - int crtc, + unsigned int pipe, v4.3-rc2-43-geba1f35dfe14 - const struct drm_crtc *refcrtc, History-4: v4.11-rc7-1899-gd673c02c4bdb -int drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev, +bool drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev, v4.11-rc7-1900-g3fcdcb270936 - unsigned flags, + bool in_vblank_irq, v4.11-rc7-1902-g1bf6ad622b9b - bool in_vblank_irq, - const struct drm_display_mode *mode) + bool in_vblank_irq) v4.14-rc3-721-g67680d3c0464 - struct timeval *vblank_time, + ktime_t *vblank_time, Signed-off-by: Yifan Zhang Change-Id: I61cb503c47518e6f11769ec4382ba7984c6faa48 Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 58 +++++++++ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 + drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 + drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 + drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 + drivers/gpu/drm/amd/backport/backport.h | 1 + .../drm/amd/backport/include/kcl/kcl_amdgpu.h | 121 ++++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 6 +- .../drm-calc-vbltimestamp-from-scanoutpos.m4 | 58 +++++++++ ...t-scanout-position-in-struct-drm-driver.m4 | 94 ++++++++++++++ ...t-vblank-timestamp-in-struct-drm-driver.m4 | 68 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 28 ++++ 15 files changed, 458 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-calc-vbltimestamp-from-scanoutpos.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/get-scanout-position-in-struct-drm-driver.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/get-vblank-timestamp-in-struct-drm-driver.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index ec61a2c9ec60d..e8544d531e9db 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1653,6 +1653,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon); u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); + int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 6e659060699c7..0ad7c86d9b716 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3115,6 +3115,13 @@ static const struct drm_driver amdgpu_kms_driver = { #if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) .debugfs_cleanup = amdgpu_debugfs_cleanup, #endif +#endif +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + .get_vblank_counter = kcl_amdgpu_get_vblank_counter_kms, + .enable_vblank = kcl_amdgpu_enable_vblank_kms, + .disable_vblank = kcl_amdgpu_disable_vblank_kms, + .get_vblank_timestamp = kcl_amdgpu_get_vblank_timestamp_kms, + .get_scanout_position = kcl_amdgpu_get_crtc_scanout_position, #endif .irq_handler = amdgpu_irq_handler, .ioctls = amdgpu_ioctls_kms, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 2c72c8869f85c..3dc169adad953 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1693,6 +1693,64 @@ void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) amdgpu_irq_put(adev, &adev->crtc_irq, idx); } +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP +#if !defined(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_USE_KTIMER_T_ARG) +/** + * amdgpu_get_vblank_timestamp_kms - get vblank timestamp + * + * @dev: drm dev pointer + * @crtc: crtc to get the timestamp for + * @max_error: max error + * @vblank_time: time value + * @flags: flags passed to the driver + * + * Gets the timestamp on the requested crtc based on the + * scanout position. (all asics). + * Returns postive status flags on success, negative error on failure. + */ +int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, + int *max_error, + struct timeval *vblank_time, + unsigned flags) +{ + struct drm_crtc *crtc; + struct amdgpu_device *adev = drm_to_adev(dev); + + if (pipe >= dev->num_crtcs) { + DRM_ERROR("Invalid crtc %u\n", pipe); + return -EINVAL; + } + + /* Get associated drm_crtc: */ + crtc = &adev->mode_info.crtcs[pipe]->base; + if (!crtc) { + /* This can occur on driver load if some component fails to + * initialize completely and driver is unloaded */ + DRM_ERROR("Uninitialized crtc %d\n", pipe); + return -EINVAL; + } + + /* Helper routine in DRM core does all the work: */ +#if defined(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_DROP_MOD_ARG) + return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, + vblank_time, flags); +#elif defined(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_HAVE_MODE_ARG) + return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, + vblank_time, flags, + &crtc->hwmode); +#elif defined(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_HAVE_CRTC_MODE_ARG) + return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, + vblank_time, flags, + crtc, &crtc->hwmode); +#else + return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, + vblank_time, flags, + crtc); +#endif +} +#endif +#endif + /* * Debugfs info */ diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 90756ea63a83f..fe22503ff4e44 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2506,10 +2506,12 @@ static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v10_0_crtc_destroy, .page_flip_target = amdgpu_display_crtc_page_flip_target, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, .disable_vblank = amdgpu_disable_vblank_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#endif }; static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode) @@ -2701,7 +2703,9 @@ static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = { .prepare = dce_v10_0_crtc_prepare, .commit = dce_v10_0_crtc_commit, .disable = dce_v10_0_crtc_disable, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_scanout_position = amdgpu_crtc_get_scanout_position, +#endif }; static void dce_v10_0_panic_flush(struct drm_plane *plane) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index cbdfebdf5dc76..5fd661e2549c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2590,10 +2590,12 @@ static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v11_0_crtc_destroy, .page_flip_target = amdgpu_display_crtc_page_flip_target, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, .disable_vblank = amdgpu_disable_vblank_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#endif }; static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode) @@ -2814,7 +2816,9 @@ static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = { .prepare = dce_v11_0_crtc_prepare, .commit = dce_v11_0_crtc_commit, .disable = dce_v11_0_crtc_disable, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_scanout_position = amdgpu_crtc_get_scanout_position, +#endif }; static void dce_v11_0_panic_flush(struct drm_plane *plane) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 63364b6961d2c..060259492865a 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2478,10 +2478,12 @@ static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = { .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v6_0_crtc_destroy, .page_flip_target = amdgpu_display_crtc_page_flip_target, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, .disable_vblank = amdgpu_disable_vblank_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#endif }; static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode) @@ -2668,7 +2670,9 @@ static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = { .prepare = dce_v6_0_crtc_prepare, .commit = dce_v6_0_crtc_commit, .disable = dce_v6_0_crtc_disable, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_scanout_position = amdgpu_crtc_get_scanout_position, +#endif }; static void dce_v6_0_panic_flush(struct drm_plane *plane) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 352aa749dc678..d63762aa31060 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2424,10 +2424,12 @@ static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = { .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v8_0_crtc_destroy, .page_flip_target = amdgpu_display_crtc_page_flip_target, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, .disable_vblank = amdgpu_disable_vblank_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#endif }; static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode) @@ -2626,7 +2628,9 @@ static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = { .prepare = dce_v8_0_crtc_prepare, .commit = dce_v8_0_crtc_commit, .disable = dce_v8_0_crtc_disable, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_scanout_position = amdgpu_crtc_get_scanout_position, +#endif }; static void dce_v8_0_panic_flush(struct drm_plane *plane) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index c75da3ec0fcb5..7e5e5fc3d3d02 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -52,5 +52,6 @@ #include #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" +#include "kcl/kcl_amdgpu.h" #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h new file mode 100644 index 0000000000000..9c0291d459b42 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDGPU_BACKPORT_KCL_AMDGPU_H +#define AMDGPU_BACKPORT_KCL_AMDGPU_H + +#include +#include "amdgpu.h" + +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + +#if defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) +static inline u32 kcl_amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int crtc) +#else +static inline u32 kcl_amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc) +#endif +{ + struct drm_crtc *drm_crtc = drm_crtc_from_index(dev, crtc); + + return amdgpu_get_vblank_counter_kms(drm_crtc); +} + +#if defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) +static inline int kcl_amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int crtc) +#else +static inline int kcl_amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc) +#endif +{ + struct drm_crtc *drm_crtc = drm_crtc_from_index(dev, crtc); + + return amdgpu_enable_vblank_kms(drm_crtc); +} + +#if defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) +static inline void kcl_amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int crtc) +#else +static inline void kcl_amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc) +#endif +{ + struct drm_crtc *drm_crtc = drm_crtc_from_index(dev, crtc); + + return amdgpu_disable_vblank_kms(drm_crtc); +} + +#if defined(HAVE_GET_SCANOUT_POSITION_RETURN_BOOL) +static inline bool kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, + bool in_vblank_irq, int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode) +{ + return !!amdgpu_display_get_crtc_scanoutpos(dev, pipe, in_vblank_irq, vpos, hpos, stime, etime, mode); +} +#elif defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) +static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int crtc, + unsigned int flags, int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode) +{ + return amdgpu_display_get_crtc_scanoutpos(dev, crtc, flags, vpos, hpos, stime, etime, mode); +} +#elif defined(HAVE_GET_SCANOUT_POSITION_HAS_DRM_DISPLAY_MODE_ARG) +static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, int crtc, + unsigned int flags, + int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode) +{ + return amdgpu_display_get_crtc_scanoutpos(dev, crtc, flags, vpos, hpos, stime, etime, mode); +} +#elif defined(HAVE_GET_SCANOUT_POSITION_HAS_TIMESTAMP_ARG) +static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, int crtc, + int *vpos, int *hpos, ktime_t *stime, + ktime_t *etime) +{ + return amdgpu_display_get_crtc_scanoutpos(dev, crtc, 0, vpos, hpos, stime, etime, NULL); +} +#else +static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, int crtc, + int *vpos, int *hpos) +{ + return amdgpu_display_get_crtc_scanoutpos(dev, crtc, 0, vpos, hpos, NULL, NULL, NULL); +} +#endif + +#if defined(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_KTIME_T) +static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, + int *max_error, ktime_t *vblank_time, + bool in_vblank_irq) +{ + return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, vblank_time, in_vblank_irq); +} +#elif defined(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_BOOL_IN_VBLANK_IRQ) +static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, + int *max_error, struct timeval *vblank_time, + bool in_vblank_irq) +{ + return !!amdgpu_get_vblank_timestamp_kms(dev, pipe, max_error, vblank_time, in_vblank_irq); +} +#elif defined(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_RETURN_BOOL) +static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, + int *max_error, struct timeval *vblank_time, + unsigned flags) +{ + return !!amdgpu_get_vblank_timestamp_kms(dev, pipe, max_error, vblank_time, flags); +} +#elif defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) +static inline int kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, + int *max_error, struct timeval *vblank_time, + unsigned flags) +{ + return amdgpu_get_vblank_timestamp_kms(dev, pipe, max_error, vblank_time, flags); +} +#else +static inline int kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, + int *max_error, + struct timeval *vblank_time, + unsigned flags) +{ + return amdgpu_get_vblank_timestamp_kms(dev, crtc, max_error, vblank_time, flags); +} +#endif +#endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP */ +#endif /* AMDGPU_BACKPORT_KCL_AMDGPU_H */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 2551823382f8b..492fec079cc70 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -547,10 +547,12 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .set_crc_source = amdgpu_dm_crtc_set_crc_source, .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, - .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_dm_crtc_enable_vblank, .disable_vblank = amdgpu_dm_crtc_disable_vblank, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + .get_vblank_counter = amdgpu_get_vblank_counter_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#endif #if defined(CONFIG_DEBUG_FS) .late_register = amdgpu_dm_crtc_late_register, #endif @@ -676,7 +678,9 @@ static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { .disable = amdgpu_dm_crtc_helper_disable, .atomic_check = amdgpu_dm_crtc_helper_atomic_check, .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_scanout_position = amdgpu_crtc_get_scanout_position, +#endif }; int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-calc-vbltimestamp-from-scanoutpos.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-calc-vbltimestamp-from-scanoutpos.m4 new file mode 100644 index 0000000000000..c69de05235130 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-calc-vbltimestamp-from-scanoutpos.m4 @@ -0,0 +1,58 @@ +dnl # +dnl # commit 67680d3c0464 +dnl # drm: vblank: use ktime_t instead of timeval +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS], [ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, (ktime_t *)NULL, 0); + ], [drm_calc_vbltimestamp_from_scanoutpos], [drivers/gpu/drm/drm_vblank.c], [ + AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_USE_KTIMER_T_ARG, 1, + [drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg]) + ], [ + dnl # + dnl # commit 1bf6ad622b9be + dnl # drm/vblank: drop the mode argument from drm_calc_vbltimestamp_from_scanoutpos + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, (struct timeval *)NULL, 0); + ], [drm_calc_vbltimestamp_from_scanoutpos], [drivers/gpu/drm/drm_vblank.c drivers/gpu/drm/drm_irq.c], [ + AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_DROP_MOD_ARG, 1, + [drm_calc_vbltimestamp_from_scanoutpos() drop mode arg]) + ], [ + dnl # + dnl # commit eba1f35dfe14 + dnl # drm: Move timestamping constants into drm_vblank_crtc + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, NULL, 0, (const struct drm_display_mode *)NULL); + ], [drm_calc_vbltimestamp_from_scanoutpos], [drivers/gpu/drm/drm_irq.c], [ + AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_HAVE_MODE_ARG, 1, + [drm_calc_vbltimestamp_from_scanoutpos() remove crtc arg]) + ], [ + dnl # + dnl # commit 7da903ef0485 + dnl # drm: Pass the display mode to drm_calc_vbltimestamp_from_scanoutpos() + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, NULL, 0, (const struct drm_crtc *)NULL, (const struct drm_display_mode *)NULL); + ], [drm_calc_vbltimestamp_from_scanoutpos], [drivers/gpu/drm/drm_irq.c], [ + AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_HAVE_CRTC_MODE_ARG, 1, + [drm_calc_vbltimestamp_from_scanoutpos() have the crtc & mode arg]) + ]) + ]) + ]) + ]) + ], [ + AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_USE_KTIMER_T_ARG, 1, + [drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-scanout-position-in-struct-drm-driver.m4 b/drivers/gpu/drm/amd/dkms/m4/get-scanout-position-in-struct-drm-driver.m4 new file mode 100644 index 0000000000000..6f0105f6f9890 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/get-scanout-position-in-struct-drm-driver.m4 @@ -0,0 +1,94 @@ +dnl # +dnl # commit v4.11-rc7-1902-g1bf6ad622b9b +dnl # drm/vblank: drop the mode argument from drm_calc_vbltimestamp_from_scanoutpos +dnl # +AC_DEFUN([AC_AMDGPU_GET_SCANOUT_POSITION_IN_DRM_DRIVER], [ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + bool foo(struct drm_device *dev, unsigned int pipe, + bool in_vblank_irq, int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode) + { + return false; + } + ], [ + struct drm_driver *bar = NULL; + bar->get_scanout_position = foo; + ], [ + AC_DEFINE(HAVE_GET_SCANOUT_POSITION_RETURN_BOOL, 1, + [get_scanout_position return bool]) + AC_DEFINE(HAVE_VGA_USE_UNSIGNED_INT_PIPE, 1, + [get_scanout_position use unsigned int pipe]) + ], [ + dnl # + dnl # commit v4.3-rc3-73-g88e72717c2de + dnl # drm/irq: Use unsigned int pipe in public API + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + int foo(struct drm_device *dev, unsigned int pipe, + unsigned int flags, int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode) + { + return 0; + } + ], [ + struct drm_driver *bar = NULL; + bar->get_scanout_position = foo; + ], [ + AC_DEFINE(HAVE_VGA_USE_UNSIGNED_INT_PIPE, 1, + [get_scanout_position use unsigned int pipe]) + ], [ + dnl # + dnl # commit v4.3-rc2-44-g3bb403bf421b + dnl # drm: Stop using linedur_ns and pixeldur_ns for vblank timestamps + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + int foo(struct drm_device *dev, int crtc, + unsigned int flags, + int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode) + { + return 0; + } + ], [ + struct drm_driver *bar = NULL; + bar->get_scanout_position = foo; + ], [ + AC_DEFINE(HAVE_GET_SCANOUT_POSITION_HAS_DRM_DISPLAY_MODE_ARG, 1, + [get_scanout_position has struct drm_display_mode arg]) + ], [ + dnl # + dnl # commit v3.12-rc3-485-g8f6fce03ddaf + dnl # drm: Push latency sensitive bits of vblank scanoutpos timestamping into kms drivers. + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + int foo(struct drm_device *dev, int crtc, + int *vpos, int *hpos, ktime_t *stime, + ktime_t *etime) + { + return 0; + } + ], [ + struct drm_driver *bar = NULL; + bar->get_scanout_position = foo; + ], [ + AC_DEFINE(HAVE_GET_SCANOUT_POSITION_HAS_TIMESTAMP_ARG, 1, + [get_scanout_position has timestamp arg]) + ]) + ]) + ]) + ]) + ], [ + AC_DEFINE(HAVE_GET_SCANOUT_POSITION_RETURN_BOOL, 1, + [get_scanout_position return bool]) + AC_DEFINE(HAVE_VGA_USE_UNSIGNED_INT_PIPE, 1, + [get_scanout_position use unsigned int pipe]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-vblank-timestamp-in-struct-drm-driver.m4 b/drivers/gpu/drm/amd/dkms/m4/get-vblank-timestamp-in-struct-drm-driver.m4 new file mode 100644 index 0000000000000..8037673d5aa39 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/get-vblank-timestamp-in-struct-drm-driver.m4 @@ -0,0 +1,68 @@ +dnl # commit v4.14-rc3-721-g67680d3c0464 +dnl # drm: vblank: use ktime_t instead of timeval +dnl # +AC_DEFUN([AC_AMDGPU_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER], [ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + bool foo(struct drm_device *dev, unsigned int pipe, + int *max_error, + ktime_t *vblank_time, + bool in_vblank_irq) + { + return false; + } + ], [ + struct drm_driver *bar = NULL; + bar->get_vblank_timestamp = foo; + ], [ + AC_DEFINE(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_KTIME_T, 1, + [get_vblank_timestamp has ktime_t arg]) + ], [ + dnl + dnl # commit v4.11-rc7-1900-g3fcdcb270936 + dnl # drm/vblank: Switch to bool in_vblank_irq in get_vblank_timestamp + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + bool foo(struct drm_device *dev, unsigned int pipe, + int *max_error, + struct timeval *vblank_time, + bool in_vblank_irq) + { + return false; + } + ], [ + struct drm_driver *bar = NULL; + bar->get_vblank_timestamp = foo; + ], [ + AC_DEFINE(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_BOOL_IN_VBLANK_IRQ, 1, + [get_vblank_timestamp has bool in_vblank_irq arg]) + ], [ + dnl # + dnl # commit id v4.11-rc7-1899-gd673c02c4bdb + dnl # drm/vblank: Switch drm_driver->get_vblank_timestamp to return a bool + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + bool foo(struct drm_device *dev, unsigned int pipe, + int *max_error, + struct timeval *vblank_time, + unsigned flags) + { + return false; + } + ], [ + struct drm_driver *bar = NULL; + bar->get_vblank_timestamp = foo; + ], [ + AC_DEFINE(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_RETURN_BOOL, 1, + [get_vblank_timestamp return bool]) + ]) + ]) + ]) + ], [ + AC_DEFINE(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_KTIME_T, 1, + [get_vblank_timestamp has ktime_t arg]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e488c5030fad9..6d4e444051a97 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -90,6 +90,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GET_FORMAT_INFO AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 new file mode 100644 index 0000000000000..f70303a508a0e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -0,0 +1,28 @@ +dnl # +dnl # v5.5-rc2-1557-ge3eff4b5d91e drm/amdgpu: Convert to CRTC VBLANK callbacks +dnl # v5.5-rc2-1556-gea702333e567 drm/amdgpu: Convert to struct drm_crtc_helper_funcs.get_scanout_position() +dnl # v5.5-rc2-1555-g7fe3f0d15aac drm: Add get_vblank_timestamp() to struct drm_crtc_funcs +dnl # v5.5-rc2-1554-gf1e2b6371c12 drm: Add get_scanout_position() to struct drm_crtc_helper_funcs +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_crtc_funcs *ptr = NULL; + ptr->get_vblank_timestamp(NULL, NULL, NULL, 0); + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP, + 1, + [struct drm_crtc_funcs->get_vblank_timestamp() is available]) + ],[ + AC_AMDGPU_GET_SCANOUT_POSITION_IN_DRM_DRIVER + AC_AMDGPU_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER + AC_AMDGPU_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP +]) From 72e74803978fb46dc69bc01f0a96bd450a53c5fb Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Mon, 26 Dec 2016 14:26:42 +0800 Subject: [PATCH 0302/2653] drm/amdkcl: test for drm_crtc_funcs->page_flip_target() drm_crtc_funcs->page_flip_target() is introduced in v4.8-rc1-112-gc229bfbbd04a the prototype change is introduced in v4.11-rc3-945-g41292b1fa13a Squash of cf36daa8cd0c drm/amdkcl: missing check with HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET aa624db31f13 drm/amdkcl: test for drm_crtc_funcs->page_flip_target() a2fc1ef061a5 drm/amdkcl: [4.9] fix amdgpu_crtc_page_flip_target() Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Jack Gui Signed-off-by: Jiansong Chen Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 216 ++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 13 ++ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 + drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 + drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 + drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 + .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 35 +++ 8 files changed, 284 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index e8544d531e9db..fafba7213e4bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -482,7 +482,11 @@ struct amdgpu_sa_manager { */ struct amdgpu_flip_work { +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET struct delayed_work flip_work; +#else + struct work_struct flip_work; +#endif struct work_struct unpin_work; struct amdgpu_device *adev; int crtc_id; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 2fcff36b2d322..fb89ae2f9044f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -95,7 +95,11 @@ static void amdgpu_display_flip_callback(struct dma_fence *f, container_of(cb, struct amdgpu_flip_work, cb); dma_fence_put(f); +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET schedule_work(&work->flip_work.work); +#else + schedule_work(&work->flip_work); +#endif } static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, @@ -116,6 +120,89 @@ static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, return false; } +#if !defined(HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET) +static void amdgpu_flip_work_func(struct work_struct *__work) +{ + struct amdgpu_flip_work *work = + container_of(__work, struct amdgpu_flip_work, flip_work); + struct amdgpu_device *adev = work->adev; + struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id]; + + struct drm_crtc *crtc = &amdgpuCrtc->base; + unsigned long flags; + unsigned i, repcnt = 4; + int vpos, hpos, stat, min_udelay = 0; + struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; + + if (amdgpu_display_flip_handle_fence(work, &work->excl)) + return; + + for (i = 0; i < work->shared_count; ++i) + if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) + return; + + /* We borrow the event spin lock for protecting flip_status */ + spin_lock_irqsave(&crtc->dev->event_lock, flags); + + /* If this happens to execute within the "virtually extended" vblank + * interval before the start of the real vblank interval then it needs + * to delay programming the mmio flip until the real vblank is entered. + * This prevents completing a flip too early due to the way we fudge + * our vblank counter and vblank timestamps in order to work around the + * problem that the hw fires vblank interrupts before actual start of + * vblank (when line buffer refilling is done for a frame). It + * complements the fudging logic in amdgpu_display_get_crtc_scanoutpos() for + * timestamping and amdgpu_get_vblank_counter_kms() for vblank counts. + * + * In practice this won't execute very often unless on very fast + * machines because the time window for this to happen is very small. + */ + while (amdgpuCrtc->enabled && --repcnt) { + /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank + * start in hpos, and to the "fudged earlier" vblank start in + * vpos. + */ + stat = amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, + GET_DISTANCE_TO_VBLANKSTART, + &vpos, &hpos, NULL, NULL, + &crtc->hwmode); + + if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != + (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) || + !(vpos >= 0 && hpos <= 0)) + break; + + /* Sleep at least until estimated real start of hw vblank */ + min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); + if (min_udelay > vblank->framedur_ns / 2000) { + /* Don't wait ridiculously long - something is wrong */ + repcnt = 0; + break; + } + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + usleep_range(min_udelay, 2 * min_udelay); + spin_lock_irqsave(&crtc->dev->event_lock, flags); + } + + if (!repcnt) + DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, " + "framedur %d, linedur %d, stat %d, vpos %d, " + "hpos %d\n", work->crtc_id, min_udelay, + vblank->framedur_ns / 1000, + vblank->linedur_ns / 1000, stat, vpos, hpos); + + /* Do the flip (mmio) */ + adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); + + /* Set the flip status */ + amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + + + DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", + amdgpuCrtc->crtc_id, amdgpuCrtc, work); +} +#else static void amdgpu_display_flip_work_func(struct work_struct *__work) { struct delayed_work *delayed_work = @@ -165,6 +252,7 @@ static void amdgpu_display_flip_work_func(struct work_struct *__work) amdgpu_crtc->crtc_id, amdgpu_crtc, work); } +#endif /* * Handle unpin events outside the interrupt handler proper. @@ -188,11 +276,16 @@ static void amdgpu_display_unpin_work_func(struct work_struct *__work) kfree(work); } +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX uint32_t page_flip_flags, uint32_t target, struct drm_modeset_acquire_ctx *ctx) +#else + uint32_t page_flip_flags, uint32_t target) +#endif { struct drm_device *dev = crtc->dev; struct amdgpu_device *adev = drm_to_adev(dev); @@ -307,6 +400,129 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, return r; } +#else +int amdgpu_crtc_page_flip(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + struct drm_pending_vblank_event *event, + uint32_t page_flip_flags) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_framebuffer *old_amdgpu_fb; + struct amdgpu_framebuffer *new_amdgpu_fb; + struct drm_gem_object *obj; + struct amdgpu_flip_work *work; + struct amdgpu_bo *new_abo; + unsigned long flags; + u64 tiling_flags; + u64 base; + int i, r; + + work = kzalloc(sizeof *work, GFP_KERNEL); + if (work == NULL) + return -ENOMEM; + + INIT_WORK(&work->flip_work, amdgpu_flip_work_func); + INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); + + work->event = event; + work->adev = adev; + work->crtc_id = amdgpu_crtc->crtc_id; + work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; + + /* schedule unpin of the old buffer */ + old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); + obj = old_amdgpu_fb->obj; + + /* take a reference to the old object */ + work->old_abo = gem_to_amdgpu_bo(obj); + amdgpu_bo_ref(work->old_abo); + + new_amdgpu_fb = to_amdgpu_framebuffer(fb); + obj = new_amdgpu_fb->obj; + new_abo = gem_to_amdgpu_bo(obj); + + /* pin the new buffer */ + r = amdgpu_bo_reserve(new_abo, false); + if (unlikely(r != 0)) { + DRM_ERROR("failed to reserve new abo buffer before flip\n"); + goto cleanup; + } + + r = amdgpu_bo_pin(new_abo, AMDGPU_GEM_DOMAIN_VRAM); + if (unlikely(r != 0)) { + r = -EINVAL; + DRM_ERROR("failed to pin new abo buffer before flip\n"); + goto unreserve; + } + + r = dma_resv_get_fences_rcu(amdkcl_ttm_resvp(&new_abo->tbo), &work->excl, + &work->shared_count, + &work->shared); + if (unlikely(r != 0)) { + DRM_ERROR("failed to get fences for buffer\n"); + goto unpin; + } + + amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); + amdgpu_bo_unreserve(new_abo); + + work->base = base; + + r = drm_crtc_vblank_get(crtc); + if (r) { + DRM_ERROR("failed to get vblank before flip\n"); + goto pflip_cleanup; + } + + /* we borrow the event spin lock for protecting flip_wrok */ + spin_lock_irqsave(&crtc->dev->event_lock, flags); + if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { + DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + r = -EBUSY; + goto vblank_cleanup; + } + + amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; + amdgpu_crtc->pflip_works = work; + + + DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", + amdgpu_crtc->crtc_id, amdgpu_crtc, work); + /* update crtc fb */ + crtc->primary->fb = fb; + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + amdgpu_flip_work_func(&work->flip_work); + return 0; + +vblank_cleanup: + drm_crtc_vblank_put(crtc); + +pflip_cleanup: + if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { + DRM_ERROR("failed to reserve new abo in error path\n"); + goto cleanup; + } +unpin: + if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) { + DRM_ERROR("failed to unpin new abo in error path\n"); + } +unreserve: + amdgpu_bo_unreserve(new_abo); + +cleanup: + amdgpu_bo_unref(&work->old_abo); + fence_put(work->excl); + for (i = 0; i < work->shared_count; ++i) + fence_put(work->shared[i]); + kfree(work->shared); + kfree(work); + + return r; +} +#endif int amdgpu_display_crtc_set_config(struct drm_mode_set *set, struct drm_modeset_acquire_ctx *ctx) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 35b29d5f490ce..030ae4a832d4e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -706,11 +706,24 @@ void amdgpu_display_print_display_setup(struct drm_device *dev); int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); int amdgpu_display_crtc_set_config(struct drm_mode_set *set, struct drm_modeset_acquire_ctx *ctx); + +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX uint32_t page_flip_flags, uint32_t target, struct drm_modeset_acquire_ctx *ctx); +#else + uint32_t page_flip_flags, uint32_t target); +#endif +#else +int amdgpu_crtc_page_flip(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + struct drm_pending_vblank_event *event, + uint32_t page_flip_flags); +#endif + extern const struct drm_mode_config_funcs amdgpu_mode_funcs; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index fe22503ff4e44..a6e84003b2e89 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2505,7 +2505,11 @@ static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { .gamma_set = dce_v10_0_crtc_gamma_set, .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v10_0_crtc_destroy, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET .page_flip_target = amdgpu_display_crtc_page_flip_target, +#else + .page_flip = amdgpu_crtc_page_flip, +#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 5fd661e2549c6..6f7a1e520651d 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2589,7 +2589,11 @@ static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { .gamma_set = dce_v11_0_crtc_gamma_set, .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v11_0_crtc_destroy, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET .page_flip_target = amdgpu_display_crtc_page_flip_target, +#else + .page_flip = amdgpu_crtc_page_flip, +#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 060259492865a..fe37e31691a4d 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2477,7 +2477,11 @@ static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = { .gamma_set = dce_v6_0_crtc_gamma_set, .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v6_0_crtc_destroy, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET .page_flip_target = amdgpu_display_crtc_page_flip_target, +#else + .page_flip = amdgpu_crtc_page_flip, +#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index d63762aa31060..0b3d50f9cf26d 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2423,7 +2423,11 @@ static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = { .gamma_set = dce_v8_0_crtc_gamma_set, .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v8_0_crtc_destroy, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET .page_flip_target = amdgpu_display_crtc_page_flip_target, +#else + .page_flip = amdgpu_crtc_page_flip, +#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index f70303a508a0e..4cbefbc42c5e8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -23,6 +23,41 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP], [ ]) ]) +dnl # +dnl # v4.11-rc3-945-g41292b1fa13a +dnl # drm: Add acquire ctx parameter to ->page_flip(_target) +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc_funcs *funcs = NULL; + funcs->page_flip_target(NULL, NULL, NULL, 0, 0, NULL); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX, 1, + [drm_crtc_funcs->page_flip_target() wants ctx parameter]) + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET, 1, + [drm_crtc_funcs->page_flip_target() is available]) + ], [ + dnl # + dnl # v4.8-rc1-112-gc229bfbbd04a + dnl # drm: Add page_flip_target CRTC hook v2 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc_funcs *funcs = NULL; + funcs->page_flip_target(NULL, NULL, NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET, 1, + [drm_crtc_funcs->page_flip_target() is available]) + ]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET ]) From 8a0c9386c7853ce1c5395bd80ca1af00636f830c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 16 Jun 2020 13:44:08 +0800 Subject: [PATCH 0303/2653] drm/amdkcl: test for drm_crtc_funcs->set_config() the interface updated in commit v4.11-rc3-950-ga4eff9aa6db8("drm: Add acquire ctx parameter to ->set_config") Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 8 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 ++++ .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 19 +++++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index fb89ae2f9044f..a5c1d160deacf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -524,8 +524,12 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc, } #endif +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX int amdgpu_display_crtc_set_config(struct drm_mode_set *set, struct drm_modeset_acquire_ctx *ctx) +#else +int amdgpu_display_crtc_set_config(struct drm_mode_set *set) +#endif { struct drm_device *dev; struct amdgpu_device *adev; @@ -542,7 +546,11 @@ int amdgpu_display_crtc_set_config(struct drm_mode_set *set, if (ret < 0) goto out; +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX ret = drm_crtc_helper_set_config(set, ctx); +#else + ret = drm_crtc_helper_set_config(set); +#endif list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) if (crtc->enabled) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 030ae4a832d4e..40477c0644f6a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -704,8 +704,12 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, /* amdgpu_display.c */ void amdgpu_display_print_display_setup(struct drm_device *dev); int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX int amdgpu_display_crtc_set_config(struct drm_mode_set *set, struct drm_modeset_acquire_ctx *ctx); +#else +int amdgpu_display_crtc_set_config(struct drm_mode_set *set); +#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 4cbefbc42c5e8..412f1d90ec93d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -23,6 +23,24 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP], [ ]) ]) +dnl # +dnl # v4.11-rc3-950-ga4eff9aa6db8 +dnl # drm: Add acquire ctx parameter to ->set_config +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc_funcs *funcs = NULL; + funcs->set_config(NULL, NULL); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX, 1, + [drm_crtc_funcs->set_config() wants ctx parameter]) + ]) + ]) +]) + dnl # dnl # v4.11-rc3-945-g41292b1fa13a dnl # drm: Add acquire ctx parameter to ->page_flip(_target) @@ -59,5 +77,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET], [ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET ]) From e8a50106caf5cda148d3daf8b369f34c167d25a8 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 17 Jun 2020 10:39:21 +0800 Subject: [PATCH 0304/2653] drm/amdkcl: test drm_kms_helper_is_poll_worker() introduced in v4.15-rc8-13-g25c058ccaf2e Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 7 +++++++ .../amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 21 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 5e375e9c4f5de..677f2abe5fefb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -40,6 +40,13 @@ #include +#ifndef HAVE_DRM_KMS_HELPER_IS_POLL_WORKER +bool inline drm_kms_helper_is_poll_worker(void) +{ + return false; +} +#endif + void amdgpu_connector_hotplug(struct drm_connector *connector) { struct drm_device *dev = connector->dev; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 new file mode 100644 index 0000000000000..dda9b0e2e2c79 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit v4.15-rc8-13-g25c058ccaf2e +dnl # drm: Allow determining if current task is output poll worker +dnl # +AC_DEFUN([AC_AMDGPU_DRM_KMS_HELPER_IS_POLL_WORKER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_kms_helper_is_poll_worker], + [drivers/gpu/drm/drm_probe_helper.c], [ + AC_DEFINE(HAVE_DRM_KMS_HELPER_IS_POLL_WORKER, 1, + [drm_kms_helper_is_poll_worker() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6d4e444051a97..e421253c4bb36 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -91,6 +91,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS + AC_AMDGPU_DRM_KMS_HELPER_IS_POLL_WORKER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 89d2d070f3ee047a26df97d5032a52e512fa1332 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 22 Sep 2020 11:02:03 +0800 Subject: [PATCH 0305/2653] drm/amdkcl: test __drm_atomic_helper_crtc_reset() is available Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e421253c4bb36..45facbdeef08f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -64,6 +64,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME + AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT AC_AMDGPU_DRM_MM_PRINT From b95100a333b3a3307c0865718f73d6ac66d28ac3 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 19 Jun 2020 17:31:03 +0800 Subject: [PATCH 0306/2653] drm/amdkcl: check drm_connector_funcs->detect drm_connector_funcs->detect() is optional since commit v4.9-rc4-949-g949f08862d66 Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- include/kcl/kcl_drm_connector.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index ac6c066aa3376..1da6773c7ee4b 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -26,6 +26,14 @@ #include #include +/* + * commit v4.9-rc4-949-g949f08862d66 + * drm: Make the connector .detect() callback optional + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 10, 0) +#define AMDKCL_AMDGPU_DRM_CONNECTOR_STATUS_DETECT_MANDATORY +#endif + #ifndef HAVE_DRM_CONNECTOR_UPDATE_EDID_PROPERTY #define drm_connector_update_edid_property drm_mode_connector_update_edid_property #endif From 14c7e76fb53cea1cec5ee3f99c1784c87f92715a Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 29 Apr 2020 15:30:15 +0800 Subject: [PATCH 0307/2653] drm/amdkcl: repalce crtc->index with drm_crtc_index Reviewed-by: Feifei Xu Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index a5c1d160deacf..11dee14c279a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1898,7 +1898,7 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, const struct drm_display_mode *mode) { struct drm_device *dev = crtc->dev; - unsigned int pipe = crtc->index; + unsigned int pipe = drm_crtc_index(crtc); return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, stime, etime, mode); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 3dc169adad953..85fc55675951c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1601,7 +1601,7 @@ void amdgpu_driver_release_kms(struct drm_device *dev) u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; - unsigned int pipe = crtc->index; + unsigned int pipe = drm_crtc_index(crtc); struct amdgpu_device *adev = drm_to_adev(dev); int vpos, hpos, stat; u32 count; @@ -1669,7 +1669,7 @@ u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; - unsigned int pipe = crtc->index; + unsigned int pipe = drm_crtc_index(crtc); struct amdgpu_device *adev = drm_to_adev(dev); int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); @@ -1686,7 +1686,7 @@ int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; - unsigned int pipe = crtc->index; + unsigned int pipe = drm_crtc_index(crtc); struct amdgpu_device *adev = drm_to_adev(dev); int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); From 5752d6afd1744d692756453cea14138c4a19f3f7 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 12 Oct 2023 14:41:17 +0800 Subject: [PATCH 0308/2653] drm/amdkcl: test whether drm_driver->release() is available introduced by v4.10-rc5-1045-gf30c92576af4 This patch is caused by 'drm/amdgpu: Embed drm_device into amdgpu_device (v2) Although v5.5-rc2-1531-ge62bf83aa1bb has removed checking on dev->dev_private, some distro with kernel v5.6+ (such as ubuntu20.04-oem) may still access dev->dev_private In case of accessing dev->dev_private in drm code, init dev->dev_private to amdgpu_device. Wrap this initialization with kcl inline function for easy tracking. Squash of 469aa26d1979 drm/amdkcl: fix reture val for faked __devm_drm_dev_alloc() af31a40bf581 drm/amdkcl: rework the faked __devm_drm_dev_alloc 312a6b63c4e9 drm/amdkcl: fake devm_drm_dev_alloc 2ec2a0da80d7 drm/amdkcl: always init drm_device.dev_private 22de9a4cefd6 drm/amdkcl: test whether drm_dev_fini() is available (v2) introduced by v5.5-rc2-1531-ge62bf83aa1bb f9896ea4089f drm/amdkcl: test whether drm checking on dev->dev_private d4300369d400 drm/amdkcl: test whether drm_dev_fini() is available Signed-off-by: Yang Xiong Reviewed-by: Flora Cui Acked-by: Guchun Chen Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Reviewed-by: Shiwu Zhang Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 12 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 24 ++++++++- drivers/gpu/drm/amd/backport/Makefile | 2 +- drivers/gpu/drm/amd/backport/backport.h | 1 + .../drm/amd/backport/include/kcl/kcl_amdgpu.h | 2 + .../backport/include/kcl/kcl_amdgpu_drm_drv.h | 43 ++++++++++++++++ drivers/gpu/drm/amd/backport/kcl_drm_drv.c | 49 +++++++++++++++++++ .../gpu/drm/amd/dkms/m4/drm-driver-release.m4 | 21 ++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 9 files changed, 153 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_drv.h create mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_drv.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index fafba7213e4bf..0a719ce838401 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -962,7 +962,11 @@ enum amdgpu_enforce_isolation_mode { struct amdgpu_device { struct device *dev; struct pci_dev *pdev; +#ifdef HAVE_DRM_DRIVER_RELEASE struct drm_device ddev; +#else + struct drm_device *ddev; +#endif #ifdef CONFIG_DRM_AMD_ACP struct amdgpu_acp acp; @@ -1349,12 +1353,20 @@ static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) { +#ifdef HAVE_DRM_DRIVER_RELEASE return container_of(ddev, struct amdgpu_device, ddev); +#else + return ddev->dev_private; +#endif } static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) { +#ifdef HAVE_DRM_DRIVER_RELEASE return &adev->ddev; +#else + return adev->ddev; +#endif } static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 0ad7c86d9b716..488995f2d25c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2446,7 +2446,11 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, kcl_pci_configure_extended_tags(pdev); ret = pci_enable_device(pdev); if (ret) +#ifndef AMDKCL_DEVM_DRM_DEV_ALLOC return ret; +#else + goto err_free; +#endif pci_set_drvdata(pdev, ddev); @@ -2544,6 +2548,10 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, err_pci: pci_disable_device(pdev); +#ifdef AMDKCL_DEVM_DRM_DEV_ALLOC +err_free: + amdkcl_drm_dev_release(ddev); +#endif return ret; } @@ -2557,7 +2565,6 @@ amdgpu_pci_remove(struct pci_dev *pdev) amdgpu_xcp_dev_unplug(adev); amdgpu_gmc_prepare_nps_mode_change(adev); drm_dev_unplug(dev); - if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { pm_runtime_get_sync(dev->dev); pm_runtime_forbid(dev->dev); @@ -2574,6 +2581,18 @@ amdgpu_pci_remove(struct pci_dev *pdev) pci_wait_for_pending_transaction(pdev); } +#ifdef HAVE_DRM_DRIVER_RELEASE +#ifndef HAVE_DRM_DRM_MANAGED_H +static void amdgpu_driver_release(struct drm_device *ddev) +{ + struct amdgpu_device *adev = drm_to_adev(ddev); + + drm_dev_fini(ddev); + kfree(adev); +} +#endif +#endif + static void amdgpu_pci_shutdown(struct pci_dev *pdev) { @@ -3116,6 +3135,7 @@ static const struct drm_driver amdgpu_kms_driver = { .debugfs_cleanup = amdgpu_debugfs_cleanup, #endif #endif + #ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = kcl_amdgpu_get_vblank_counter_kms, .enable_vblank = kcl_amdgpu_enable_vblank_kms, @@ -3130,7 +3150,9 @@ static const struct drm_driver amdgpu_kms_driver = { .dumb_map_offset = amdgpu_mode_dumb_mmap, DRM_FBDEV_TTM_DRIVER_OPS, .fops = &amdgpu_driver_kms_fops, +#ifdef HAVE_DRM_DRIVER_RELEASE .release = &amdgpu_driver_release_kms, +#endif #ifdef CONFIG_PROC_FS .show_fdinfo = amdgpu_show_fdinfo, #endif diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index 1ad8a02a4b19f..8880468d474a6 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: MIT -BACKPORT_OBJS := +BACKPORT_OBJS := kcl_drm_drv.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7e5e5fc3d3d02..e03d2fe1152ae 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -53,5 +53,6 @@ #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" +#include "kcl/kcl_amdgpu_drm_drv.h" #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h index 9c0291d459b42..5c6fe94ccd030 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -4,6 +4,7 @@ #include #include "amdgpu.h" +#include #ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP @@ -118,4 +119,5 @@ static inline int kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, in } #endif #endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP */ + #endif /* AMDGPU_BACKPORT_KCL_AMDGPU_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_drv.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_drv.h new file mode 100644 index 0000000000000..926e4cd441519 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_drv.h @@ -0,0 +1,43 @@ +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * Copyright 2016 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_DRV_H__ +#define __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_DRV_H__ + +#include + +/* Copied from v5.7-rc1-343-gb0b5849e0cc0 include/drm/drm_drv.h */ +#ifndef devm_drm_dev_alloc +#define AMDKCL_DEVM_DRM_DEV_ALLOC 1 +void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, + size_t size, size_t offset); +#define devm_drm_dev_alloc(parent, driver, type, member) \ + ((type *) __devm_drm_dev_alloc(parent, driver, sizeof(type), \ + offsetof(type, member))) + +void amdkcl_drm_dev_release(struct drm_device *ddev); +#endif + +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_drv.c b/drivers/gpu/drm/amd/backport/kcl_drm_drv.c new file mode 100644 index 0000000000000..d6b18e3a75f73 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_drm_drv.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include +#include "amdgpu.h" + +#ifdef AMDKCL_DEVM_DRM_DEV_ALLOC +/* Copied from v5.7-rc1-343-gb0b5849e0cc0 drivers/gpu/drm/drm_drv.c and modified for KCL */ +void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, + size_t size, size_t offset) +{ + void *container; + struct drm_device *drm; + int ret; + + container = kzalloc(size, GFP_KERNEL); + if (!container) + return ERR_PTR(-ENOMEM); + +#ifdef HAVE_DRM_DRIVER_RELEASE + drm = container + offset; + ret = drm_dev_init(drm, driver, parent); + if (ret) { + drm_dev_put(drm); + return ERR_PTR(ret); + } +#ifdef HAVE_DRM_DRM_MANAGED_H + drmm_add_final_kfree(drm, container); +#endif +#else + drm = drm_dev_alloc(driver, parent); + if (IS_ERR(drm)) + return PTR_ERR(drm); + ((struct amdgpu_device*)container)->ddev = drm; +#endif + drm->dev_private = container; + return container; +} + +void amdkcl_drm_dev_release(struct drm_device *ddev) +{ +#ifndef HAVE_DRM_DRIVER_RELEASE + if (ddev) { + kfree(drm_to_adev(ddev)); + ddev->dev_private = NULL; + } +#endif + drm_dev_put(ddev); +} + +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 new file mode 100644 index 0000000000000..05801784c5188 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v4.10-rc5-1045-gf30c92576af4 +dnl # drm: Provide a driver hook for drm_dev_release() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_RELEASE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRM_DRV_H + #include + #else + #include + #endif + ],[ + struct drm_driver *ddrv = NULL; + ddrv->release = NULL; + ],[ + AC_DEFINE(HAVE_DRM_DRIVER_RELEASE, 1, + [drm_driver->release() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 45facbdeef08f..a76ad4e84223d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -93,6 +93,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_EDID_TO_ELD AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_KMS_HELPER_IS_POLL_WORKER + AC_AMDGPU_DRM_DRIVER_RELEASE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 6cec3ba7283dc348c2b358a032f83c1f63668b50 Mon Sep 17 00:00:00 2001 From: tianci yin Date: Thu, 14 Feb 2019 10:08:11 +0800 Subject: [PATCH 0309/2653] drm/amdkcl: check whether drm_connector_for_each_possible_encoder is available drm_connector_for_each_possible_encoder was introduced by the below commit since 4.19-rc1, add kcl implement for older kernel. "drm: Add drm_connector_for_each_possible_encoder()" for_each_if is introduce from v4.5-rc1 . so it's not available on drm < 4.5 like rhel6.10 . v1: drm/amdkcl: [4.19] kcl for drm_connector_for_each_possible_encoder v2: drm/amdkcl: check whether drm_connector_for_each_possible_encoder is available v3: drm_connector_for_each_possible_encoder Reviewed-by: changzhu Signed-off-by: Tianci Yin Signed-off-by: Chengming Gui Signed-off-by: Flora Cui Signed-off-by: Jack Gui Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 39 +++++++++++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++ ...drm-connector-for-each-possible-encoder.m4 | 20 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 64 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-for-each-possible-encoder.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 677f2abe5fefb..0daeec36c8cbc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -226,10 +226,15 @@ amdgpu_connector_update_scratch_regs(struct drm_connector *connector, struct drm_encoder *encoder; const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; bool connected; + int i; best_encoder = connector_funcs->best_encoder(connector); +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif if ((encoder == best_encoder) && (status == connector_status_connected)) connected = true; else @@ -244,8 +249,13 @@ amdgpu_connector_find_encoder(struct drm_connector *connector, int encoder_type) { struct drm_encoder *encoder; + int i; +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif if (encoder->encoder_type == encoder_type) return encoder; } @@ -330,9 +340,14 @@ static struct drm_encoder * amdgpu_connector_best_single_encoder(struct drm_connector *connector) { struct drm_encoder *encoder; + int i; /* pick the first one */ +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) +#endif return encoder; return NULL; @@ -1118,8 +1133,13 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) /* find analog encoder */ if (amdgpu_connector->dac_load_detect) { struct drm_encoder *encoder; + int i; +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) continue; @@ -1170,8 +1190,13 @@ amdgpu_connector_dvi_encoder(struct drm_connector *connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); struct drm_encoder *encoder; + int i; +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif if (amdgpu_connector->use_digital == true) { if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) return encoder; @@ -1186,7 +1211,11 @@ amdgpu_connector_dvi_encoder(struct drm_connector *connector) /* then check use digitial */ /* pick the first one */ +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) +#endif return encoder; return NULL; @@ -1324,8 +1353,13 @@ u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *conn { struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; + int i; +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif amdgpu_encoder = to_amdgpu_encoder(encoder); switch (amdgpu_encoder->encoder_id) { @@ -1344,9 +1378,14 @@ static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) { struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; + int i; bool found = false; +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif amdgpu_encoder = to_amdgpu_encoder(encoder); if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) found = true; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b2abb3f2ff474..fbc7788c5e5fa 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8060,6 +8060,7 @@ static int to_drm_connector_type(enum signal_type st) static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) { +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS struct drm_encoder *encoder; /* There is only one encoder per connector */ @@ -8067,6 +8068,9 @@ static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector * return encoder; return NULL; +#else + return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]); +#endif } static void amdgpu_dm_get_native_mode(struct drm_connector *connector) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-for-each-possible-encoder.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-for-each-possible-encoder.m4 new file mode 100644 index 0000000000000..0f57128fcf1a1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-for-each-possible-encoder.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit v5.3-rc1-656-g62afb4ad425a +dnl # drm/connector: Allow max possible encoders to attach to a connector +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + struct drm_connector *connector = NULL; + struct drm_encoder *encoder = NULL; + drm_connector_for_each_possible_encoder(connector, encoder) + return 0; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS, 1, + [drm_connector_for_each_possible_encoder() wants 2 arguments]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a76ad4e84223d..20d4f15a2eb7c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -94,6 +94,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_KMS_HELPER_IS_POLL_WORKER AC_AMDGPU_DRM_DRIVER_RELEASE + AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From d64ea306e77e2e46868ea3baddad37ac9c2427a9 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Fri, 20 Sep 2019 16:34:11 +0800 Subject: [PATCH 0310/2653] drm/amdkcl: Test drm_hdmi_avi_infoframe_from_display_mode() interface history v1: f6cdebf80917 Test whether drm_hdmi_avi_infoframe_from_display_mode() wants 2 args Signed-off-by: Adam Yang Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: fix drm_hdmi_avi_infoframe_from_display_mode 1. fix compile waring 2. remove extra "," Signed-off-by: Flora Cui Signed-off-by: Jack Gui Change-Id: I0b32a9991abed7088f72652740aa71604fe40b10 --- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 6 ++++ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 6 ++++ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 6 ++++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 6 ++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++ drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 | 35 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 7 files changed, 66 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index a6e84003b2e89..0794954bc138b 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -1711,7 +1711,13 @@ static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder, dce_v10_0_audio_write_sad_regs(encoder); dce_v10_0_audio_write_latency_fields(encoder, mode); +#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); +#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); +#else + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); +#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ if (err < 0) { DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); return; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 6f7a1e520651d..e8de733871d6f 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -1760,7 +1760,13 @@ static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder, dce_v11_0_audio_write_sad_regs(encoder); dce_v11_0_audio_write_latency_fields(encoder, mode); +#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); +#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); +#else + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); +#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ if (err < 0) { DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); return; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index fe37e31691a4d..d728bedfe9d50 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -1538,7 +1538,13 @@ static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder, ssize_t err; u32 tmp; +#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); +#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); +#else + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); +#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ if (err < 0) { DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); return; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 0b3d50f9cf26d..08b7ec5c3dde8 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -1662,7 +1662,13 @@ static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder, dce_v8_0_audio_write_sad_regs(encoder); dce_v8_0_audio_write_latency_fields(encoder, mode); +#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); +#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); +#else + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); +#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ if (err < 0) { DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); return; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index fbc7788c5e5fa..810a6e4e65dcf 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6376,12 +6376,18 @@ static void fill_stream_properties_from_drm_display_mode( } if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { +#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); if (err < 0) drm_warn_once(connector->dev, "Failed to setup avi infoframe on connector %s: %zd\n", connector->name, err); +#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) + drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, mode_in, false); +#else + drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, mode_in); +#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ timing_out->vic = avi_frame.video_code; err = drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 new file mode 100644 index 0000000000000..02a5a8a2b5875 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 @@ -0,0 +1,35 @@ +dnl # +dnl # 13d0add333afea7b2fef77473232b10dea3627dd +dnl # drm/edid: Pass connector to AVI infoframe functions +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct hdmi_avi_infoframe *frame = NULL; + struct drm_connector *connector = NULL; + const struct drm_display_mode *mode = NULL; + drm_hdmi_avi_infoframe_from_display_mode(frame, connector, mode); + ], [drm_hdmi_avi_infoframe_from_display_mode], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P, 1, + [drm_hdmi_avi_infoframe_from_display_mode() has p,p,p interface]) + ], [ + dnl # + dnl # 10a8512008655d5ce62f8c56323a6b5bd221c920 + dnl # drm: Add HDMI infoframe helpers + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct hdmi_avi_infoframe *frame = NULL; + const struct drm_display_mode *mode = NULL; + bool is_hdmi2_sink = false; + drm_hdmi_avi_infoframe_from_display_mode(frame, mode, is_hdmi2_sink); + ], [drm_hdmi_avi_infoframe_from_display_mode], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B, 1, + [drm_hdmi_avi_infoframe_from_display_mode() has p,p,b interface]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 20d4f15a2eb7c..ed11813a3944d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -92,6 +92,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS + AC_AMDGPU_DRM_EDID AC_AMDGPU_DRM_KMS_HELPER_IS_POLL_WORKER AC_AMDGPU_DRM_DRIVER_RELEASE AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER From 1babf22cf961eebee9f2fd74c5885d36171710e8 Mon Sep 17 00:00:00 2001 From: changzhu Date: Fri, 12 Jul 2019 14:49:19 +0800 Subject: [PATCH 0311/2653] drm/amdkcl: add AC_AMDGPU_DRM_AUDIO_COMPONENT_HEADER it is a squash of: drm/amdkcl: test whether drm/drm_audio_component.h is available [why] drm_audio_component.h is not defined before drm version 4.19.0. So there will be build error when using them before drm version 4.19.0. [How] Use autoconf way to check drm_audio_component_ops, drm_audio_component_audio_ops,drm_audio_component in kernel. If they are not defined,avoid to use them in driver code. This autoconf patch is caused by patch: drm/amd/display: Add drm_audio_component support to amdgpu_dm Change-Id: Ic75928406a042a0e08f5b06cf64543555c62e476 Signed-off-by: changzhu Reviewed-by: Nicholas Kazlauskas Signed-off-by: Jack Gui drm/amdkcl: correct drm_audio_component_header.m4 patten Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: fix check for drm/drm_audio_component.h Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Yifan Zhang Signed-off-by: Ma Jun Change-Id: I7717d2f117361cfa3fa7a0f941e88ac3d99327b8 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 +++++++++++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 ++++ .../amd/dkms/m4/drm-audio-component-header.m4 | 9 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 34 insertions(+) mode change 100644 => 100755 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c mode change 100644 => 100755 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c old mode 100644 new mode 100755 index 810a6e4e65dcf..307b1beaf6c12 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -77,7 +77,10 @@ #include #include #include + +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) #include +#endif #include #include @@ -92,7 +95,9 @@ #include #include #include +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) #include +#endif #include #ifdef CONFIG_DRM_AMD_DC_HDCP #include @@ -1054,6 +1059,7 @@ static void amdgpu_dm_fbc_init(struct drm_connector *connector) } +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, int pipe, bool *enabled, unsigned char *buf, int max_bytes) @@ -1191,6 +1197,7 @@ static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) pin, -1); } } +#endif static int dm_dmub_hw_init(struct amdgpu_device *adev) { @@ -1838,7 +1845,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) mutex_init(&adev->dm.dpia_aux_lock); mutex_init(&adev->dm.dc_lock); + +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) mutex_init(&adev->dm.audio_lock); +#endif if (amdgpu_dm_irq_init(adev)) { drm_err(adev_to_drm(adev), "failed to initialize DM IRQ support.\n"); @@ -2250,7 +2260,9 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) adev->dm.freesync_module = NULL; } +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) mutex_destroy(&adev->dm.audio_lock); +#endif mutex_destroy(&adev->dm.dc_lock); mutex_destroy(&adev->dm.dpia_aux_lock); } @@ -4675,12 +4687,14 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) } #endif +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) r = amdgpu_dm_audio_init(adev); if (r) { dc_state_release(state->context); kfree(state); return r; } +#endif return 0; } @@ -8419,7 +8433,9 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, aconnector->base.stereo_allowed = false; aconnector->base.dpms = DRM_MODE_DPMS_OFF; aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) aconnector->audio_inst = -1; +#endif aconnector->pack_sdp_v1_3 = false; aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); @@ -9687,6 +9703,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, kfree(bundle); } +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) static void amdgpu_dm_commit_audio(struct drm_device *dev, struct drm_atomic_state *state) { @@ -9767,6 +9784,7 @@ static void amdgpu_dm_commit_audio(struct drm_device *dev, amdgpu_dm_audio_eld_notify(adev, inst); } } +#endif /* * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC @@ -10460,8 +10478,10 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) acrtc->wb_enabled = true; } +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) /* Update audio instances for each connector. */ amdgpu_dm_commit_audio(dev, state); +#endif /* restore the backlight level */ for (i = 0; i < dm->num_of_edps; i++) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h old mode 100644 new mode 100755 index 67c3a7a967f2f..241c9e4dd1ec9 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -422,6 +422,7 @@ struct amdgpu_display_manager { */ struct mutex dc_lock; +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) /** * @audio_lock: * @@ -443,6 +444,7 @@ struct amdgpu_display_manager { * successfully, false otherwise. */ bool audio_registered; +#endif /** * @irq_handler_list_low_tab: @@ -770,8 +772,10 @@ struct amdgpu_dm_connector { */ int max_vfreq ; +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) /* Audio instance - protected by audio_lock. */ int audio_inst; +#endif struct mutex hpd_lock; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 new file mode 100644 index 0000000000000..520d72bebcb5c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 @@ -0,0 +1,9 @@ +AC_DEFUN([AC_AMDGPU_DRM_AUDIO_COMPONENT_HEADER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drm_audio_component.h], [ + AC_DEFINE(HAVE_DRM_AUDIO_COMPONENT_HEADER, 1, + [whether drm/drm_audio_component.h is defined]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ed11813a3944d..00ac87837a73c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -48,6 +48,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_SCHED_SET_FIFO_LOW AC_AMDGPU_DMA_FENCE_HEADERS + AC_AMDGPU_DRM_AUDIO_COMPONENT_HEADER AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_SG_TT_INIT AC_AMDGPU_TTM_BUFFER_OBJECT From c3d12281b5345957c5d268e58c2b23f344655197 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 24 Sep 2019 13:30:02 +0800 Subject: [PATCH 0312/2653] drm/amdkcl: Test whether drm_mode_is_420_xxx() is available v2: drm/amdkcl: refactor kcl copy rm_mode_is_420_xxx v3: fix license for kcl drm part Change-Id: I3b71e9df855e8996d76a040ac6b650fdb52702fa Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui Reviewed-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Change-Id: I2797279336841ff551df87ec663ec384b01022ca --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c | 41 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +++-- .../drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 | 17 ++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_modes.h | 39 ++++++++++++++++++ 7 files changed, 106 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 create mode 100644 include/kcl/kcl_drm_modes.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index fafb36606e287..3f301283ce0de 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -10,7 +10,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ - kcl_device_cgroup.o kcl_mn.o kcl_time.o kcl_ftrace.o \ + kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c new file mode 100644 index 0000000000000..bf57f999e4fc2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c @@ -0,0 +1,41 @@ +/* + * Copyright © 1997-2003 by The XFree86 Project, Inc. + * Copyright © 2007 Dave Airlie + * Copyright © 2007-2008 Intel Corporation + * Jesse Barnes + * Copyright 2005-2006 Luc Verhaegen + * Copyright (c) 2001, Andy Ritger aritger@nvidia.com + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ +#include +#include +#include + +#ifndef HAVE_DRM_MODE_IS_420_XXX +amdkcl_dummy_symbol(drm_mode_is_420_only, bool, return false, + const struct drm_display_info *display, const struct drm_display_mode *mode) +amdkcl_dummy_symbol(drm_mode_is_420_also, bool, return false, + const struct drm_display_info *display, const struct drm_display_mode *mode) +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e03d2fe1152ae..b12907b57f7c0 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -44,6 +44,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 307b1beaf6c12..56eebd268e1ac 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6153,6 +6153,11 @@ convert_color_depth_from_display_info(const struct drm_connector *connector, { u8 bpc; + bpc = (uint8_t)connector->display_info.bpc; + /* Assume 8 bpc by default if no bpc is specified. */ + bpc = bpc ? bpc : 8; + +#ifdef HAVE_DRM_MODE_IS_420_XXX if (is_y420) { bpc = 8; @@ -6163,11 +6168,8 @@ convert_color_depth_from_display_info(const struct drm_connector *connector, bpc = 12; else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) bpc = 10; - } else { - bpc = (uint8_t)connector->display_info.bpc; - /* Assume 8 bpc by default if no bpc is specified. */ - bpc = bpc ? bpc : 8; } +#endif if (requested_bpc > 0) { /* diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 new file mode 100644 index 0000000000000..65c9ec9268e1b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 2570fe2586254ff174c2ba5a20dabbde707dbb9b +dnl # drm: add helper functions for YCBCR420 handling +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_IS_420_XXX], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_mode_is_420_only(NULL, NULL); + drm_mode_is_420_also(NULL, NULL); + ], [drm_mode_is_420_only drm_mode_is_420_also],[drivers/gpu/drm/drm_modes.c],[ + AC_DEFINE(HAVE_DRM_MODE_IS_420_XXX, 1, + [drm_mode_is_420_xxx() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 00ac87837a73c..d9d0406b6abc7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -97,6 +97,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_KMS_HELPER_IS_POLL_WORKER AC_AMDGPU_DRM_DRIVER_RELEASE AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER + AC_AMDGPU_DRM_MODE_IS_420_XXX AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_modes.h b/include/kcl/kcl_drm_modes.h new file mode 100644 index 0000000000000..c47d691ca6e7a --- /dev/null +++ b/include/kcl/kcl_drm_modes.h @@ -0,0 +1,39 @@ +/* + * Copyright © 2006 Keith Packard + * Copyright © 2007-2008 Dave Airlie + * Copyright © 2007-2008 Intel Corporation + * Jesse Barnes + * Copyright © 2014 Intel Corporation + * Daniel Vetter + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef KCL_KCL_DRM_MODES_H +#define KCL_KCL_DRM_MODES_H + +#include + +#ifndef HAVE_DRM_MODE_IS_420_XXX +bool drm_mode_is_420_only(const struct drm_display_info *display, + const struct drm_display_mode *mode); +bool drm_mode_is_420_also(const struct drm_display_info *display, + const struct drm_display_mode *mode); +#endif + +#endif From 7864e7a87c9bbef044ff9bd94376a907560d43eb Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 9 May 2019 17:20:26 -0400 Subject: [PATCH 0313/2653] drm/amdkcl: Test whether format in struct drm_framebuffer is available v1: drm/amdkcl: Test whether drm_framebuffer structure contains format v2: drm/amd/autoconf: test whether struct drm_framebuffer have format v3: drm/amdkcl: fix for HAVE_DRM_FRAMEBUFFER_FORMAT v4: drm/amdkcl: accommodate to drmP.h removal for drm-framebuffer-format.m4 It's a squash of drm/amdkcl: fix pitch setting on leacy kernel drm/amdkcl: fix test for drm_framebuffer->format Signed-off-by: Flora Cui Reviewed-by: Yang Xiong drm/amdkcl: [4.11] fix for struct drm_framebuffer format build error v2 Signed-off-by: changzhu Reviewed-by: Nicholas Kazlauskas Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: I03e3c89fa4144a526e917c5fe671a8b60855258a Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: chen gong Signed-off-by: Jack Gui Reviewed-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Flora Cui Signed-off-by: Yang Xiong Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 12 ++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 56eebd268e1ac..2bfc894aa19a9 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5772,7 +5772,11 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, memset(plane_info, 0, sizeof(*plane_info)); +#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT + switch (fb->pixel_format) { +#else switch (fb->format->format) { +#endif case DRM_FORMAT_C8: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; @@ -5824,7 +5828,11 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, default: drm_err(adev_to_drm(adev), "Unsupported screen format %p4cc\n", +#ifdef HAVE_DRM_FRAMEBUFFER_FORMAT &fb->format->format); +#else + &fb->pixel_format); +#endif return -EINVAL; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 38ae5a14ffb49..8ba41973c0963 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -864,7 +864,11 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, plane_size->surface_size.width = fb->width; plane_size->surface_size.height = fb->height; plane_size->surface_pitch = +#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT + fb->pitches[0] / (fb->bits_per_pixel / 8); +#else fb->pitches[0] / fb->format->cpp[0]; +#endif address->type = PLN_ADDR_TYPE_GRAPHICS; address->grph.addr.low_part = lower_32_bits(addr); @@ -878,7 +882,11 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, plane_size->surface_size.width = fb->width; plane_size->surface_size.height = fb->height; plane_size->surface_pitch = +#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT + fb->pitches[0] / (fb->bits_per_pixel / 8); +#else fb->pitches[0] / fb->format->cpp[0]; +#endif plane_size->chroma_size.x = 0; plane_size->chroma_size.y = 0; @@ -887,7 +895,11 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, plane_size->chroma_size.height = fb->height / 2; plane_size->chroma_pitch = +#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT + fb->pitches[1] / (fb->bits_per_pixel / 8)/2; +#else fb->pitches[1] / fb->format->cpp[1]; +#endif address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; address->video_progressive.luma_addr.low_part = diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d9d0406b6abc7..f8984384a9f5d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -88,7 +88,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_FB_HELPER_INIT - AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT AC_AMDGPU_DRM_GET_FORMAT_INFO AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD @@ -98,6 +97,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRIVER_RELEASE AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_AMDGPU_DRM_MODE_IS_420_XXX + AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 00edbebba589b5b002c8ffe9baf5f4f6a51b5562 Mon Sep 17 00:00:00 2001 From: chen gong Date: Mon, 10 Jun 2019 10:52:24 +0800 Subject: [PATCH 0314/2653] drm/amdkcl: Test whether strscpy() is available Change-Id: Ieaf30809e752533ae30b493d7490ceb640476a6a Signed-off-by: chen gong Reviewed-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Ma Jun --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/strscpy.m4 | 17 +++++++++++++++++ 3 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/strscpy.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2bfc894aa19a9..bdc40d90cd008 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6474,9 +6474,15 @@ static void fill_audio_info(struct audio_info *audio_info, cea_revision = drm_connector->display_info.cea_rev; +#if !defined(HAVE_STRSCPY) + strncpy(audio_info->display_name, + edid_caps->display_name, + AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1); +#else strscpy(audio_info->display_name, edid_caps->display_name, AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); +#endif if (cea_revision >= 3) { audio_info->mode_count = edid_caps->audio_mode_count; @@ -8150,7 +8156,11 @@ amdgpu_dm_create_common_mode(struct drm_encoder *encoder, mode->hdisplay = hdisplay; mode->vdisplay = vdisplay; mode->type &= ~DRM_MODE_TYPE_PREFERRED; +#if !defined(HAVE_STRSCPY) + strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN); +#else strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); +#endif return mode; diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f8984384a9f5d..a195dee0dcd92 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -98,6 +98,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT + AC_AMDGPU_STRSCPY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 b/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 new file mode 100644 index 0000000000000..35ace5a7694c7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 30035e45753b708e7d47a98398500ca005e02b86 +dnl # Author: Chris Metcalf +dnl # Date: Wed Apr 29 12:52:04 2015 -0400 +dnl # string: provide strscpy() +dnl # +AC_DEFUN([AC_AMDGPU_STRSCPY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + strscpy(NULL, NULL, 8); + ], [strscpy], [lib/string.c], [ + AC_DEFINE(HAVE_STRSCPY, 1, [strscpy() is available]) + ]) + ]) +]) From b8092d0f38cb2b743bedfc53621a6763fce97965 Mon Sep 17 00:00:00 2001 From: Rui Teng Date: Mon, 23 Sep 2019 19:29:57 +0800 Subject: [PATCH 0315/2653] drm/amdkcl: check whether DEFINE_DEBUGFS_ATTRIBUTE is available DEFINE_DEBUGFS_ATTRIBUTE and debugfs_create_file_unsafe is introduced by kernel 4.7 - commit c64688081490321f2d23a292ef24e60bb321f3f1 - Author: Nicolai Stange - debugfs: add support for self-protecting attribute file fops Change-Id: Ia4c9ddf96d50a5eea76a28c6e8f3a012332f1f69 Signed-off-by: Rui Teng Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: fix compile error if DEFINE_DEBUGFS_ATTRIBUTE not defined Change-Id: I23277d6b9c298fb4325cc54b1ca7379e45b68d99 Signed-off-by: Stanley.Yang --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index f263e1a4537e1..0265e1a891cf9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3087,8 +3087,10 @@ static int force_yuv420_output_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, force_yuv420_output_set, "%llu\n"); +#endif /* * Read Replay state @@ -3350,6 +3352,7 @@ static int dmcub_trace_event_state_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, dmcub_trace_event_state_set, "%llu\n"); @@ -3367,6 +3370,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops, DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops, disallow_edp_enter_psr_get, disallow_edp_enter_psr_set, "%llu\n"); +#endif DEFINE_SHOW_ATTRIBUTE(current_backlight); DEFINE_SHOW_ATTRIBUTE(target_backlight); @@ -3376,7 +3380,9 @@ static const struct { char *name; const struct file_operations *fops; } connector_debugfs_entries[] = { +#ifdef DEFINE_DEBUGFS_ATTRIBUTE {"force_yuv420_output", &force_yuv420_output_fops}, +#endif {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, {"internal_display", &internal_display_fops}, {"odm_combine_segments", &odm_combine_segments_fops} @@ -3529,6 +3535,8 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) dp_debugfs_entries[i].fops); } } + +#ifdef DEFINE_DEBUGFS_ATTRIBUTE if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { debugfs_create_file("replay_capability", 0444, dir, connector, &replay_capability_fops); @@ -3550,6 +3558,7 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector, &disallow_edp_enter_psr_fops); } +#endif for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { debugfs_create_file(connector_debugfs_entries[i].name, @@ -3973,8 +3982,10 @@ static int force_timing_sync_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, force_timing_sync_set, "%llu\n"); +#endif /* @@ -4112,8 +4123,10 @@ static int visual_confirm_get(void *data, u64 *val) } DEFINE_SHOW_ATTRIBUTE(mst_topo); +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, visual_confirm_set, "%llu\n"); +#endif /* @@ -4239,6 +4252,7 @@ void dtn_debugfs_init(struct amdgpu_device *adev) debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, &dp_ignore_cable_id_ops); +#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, &visual_confirm_fops); @@ -4272,4 +4286,5 @@ void dtn_debugfs_init(struct amdgpu_device *adev) if (adev->dm.dc->caps.ips_support) debugfs_create_file_unsafe("amdgpu_dm_ips_status", 0644, root, adev, &ips_status_fops); +#endif } From d905bb8f53c4c3fad689570bf2a811c99a8b88e6 Mon Sep 17 00:00:00 2001 From: chen gong Date: Thu, 16 May 2019 16:29:41 +0800 Subject: [PATCH 0316/2653] drm/amdkcl: check whether for_each_{old/new/oldnew}_{plane/connector/crtc}_in_state is available drm/amdkcl: Test whether for_each_oldnew_plane_in_state() is defined Change-Id: Iff20a648d390ab976a5d98443ee6037b10968561 Signed-off-by: chen gong Reviewed-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: Test whether for_each_oldnew_connector_in_state() is defined Change-Id: I7b2847ca6fc7e847ba9e06bc2e2e9173ef26e8cf Signed-off-by: chen gong Reviewed-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: Test whether for_each_new_crtc_in_state() is defined Change-Id: Iedac8a5691e7bec594db95096259ff260d05b684 Signed-off-by: chen gong Reviewed-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: add protection for for_each_new_crtc_in_state Signed-off-by: Yifan Zhang Reviewed-by: Feifei Xu Signed-off-by: Jack Gui drm/amdkcl: check whether for_each_{old/new/oldnew}_{plane/connector/crtc}_in_state is available drm/amdkcl: test for_each_new_crtc_in_state directly for_each_new_crtc_in_state is a macro which can be tested directly with #ifdef, save a m4 macro Change-Id: I747b753244b1b514ef4a2ad4c1e0cc8bd8fb1314 Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: test for_each_oldnew_plane_in_state directly Change-Id: Ia1a265e35b690ecbf2620a235191c0f269c84fbf Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: test for_each_oldnew_connector_in_state directly Change-Id: I054e2e8db8091d3aa63ebd38c350f2b219edae6c Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: check whether for_each_{old/new/oldnew}_{plane/connector/crtc}_in_state is available Related commit: v4.12~21^2~8^2~134 - commit 581e49fe6b411f407102a7f2377648849e0fa37f - drm/atomic: Add new iterators over all state, v3 v4.17-rc2~1^2~24^2~13 - commit 55de2923847c3318459758931ff175996facce69 - drm/atomic: Add new reverse iterator over all plane state (V2) Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: rework for_each_oldnew_plane_in_state_reverse to fix install failure with ubuntu16.04.5 & phontom Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Flora Cui Change-Id: Ib4bb484bd839ddd20881f0e0d8166e24877124ab Signed-off-by: chen gong --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +-- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 31 +++++++++++++++++++ 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index bdc40d90cd008..ebcfa046a3ce5 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9870,7 +9870,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, } for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, - new_crtc_state, i) { + new_crtc_state, i) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); @@ -11918,9 +11918,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } } + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); - if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->color_mgmt_changed && old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 241c9e4dd1ec9..26efd8de61e6d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -219,6 +219,31 @@ struct amdgpu_dm_backlight_caps { struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; }; +/** + * for_each_oldnew_plane_in_state_reverse - iterate over all planes in an atomic + * update in reverse order + * @__state: &struct drm_atomic_state pointer + * @plane: &struct drm_plane iteration cursor + * @old_plane_state: &struct drm_plane_state iteration cursor for the old state + * @new_plane_state: &struct drm_plane_state iteration cursor for the new state + * @__i: int iteration cursor, for macro-internal use + * + * This iterates over all planes in an atomic update in reverse order, + * tracking both old and new state. This is useful in places where the + * state delta needs to be considered, for example in atomic check functions. + */ +#if !defined(for_each_oldnew_plane_in_state_reverse) && \ + defined(for_each_oldnew_plane_in_state) +#define for_each_oldnew_plane_in_state_reverse(__state, plane, old_plane_state, new_plane_state, __i) \ + for ((__i) = ((__state)->dev->mode_config.num_total_plane - 1); \ + (__i) >= 0; \ + (__i)--) \ + for_each_if ((__state)->planes[__i].ptr && \ + ((plane) = (__state)->planes[__i].ptr, \ + (old_plane_state) = (__state)->planes[__i].old_state,\ + (new_plane_state) = (__state)->planes[__i].new_state, 1)) +#endif + /** * struct dal_allocation - Tracks mapped FB memory for SMU communication * @list: list of dal allocations @@ -233,6 +258,7 @@ struct dal_allocation { u64 gpu_addr; }; + /** * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq * offload work @@ -1062,7 +1088,12 @@ int dm_atomic_get_state(struct drm_atomic_state *state, struct drm_connector * amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, +#ifndef for_each_new_connector_in_state + struct drm_crtc *crtc, + bool from_state_var); +#else struct drm_crtc *crtc); +#endif int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); From 092f0c7fd0106c4abf505ad9e0df1bb4cf68673b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sat, 9 May 2020 17:46:12 +0800 Subject: [PATCH 0317/2653] drm/amdkcl: test struct drm_crtc_funcs->enable_vblank struct drm_crtc_funcs->enable_vblank is introduced in v4.10-rc5-1070-g84e354839b15 It's a squash of drm/amdkcl: drop macro check for dm_enable/disable_vblank Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: [4.12] Fix drm_crtc_funcs - .{enable/disable}_vblank Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Acked-by: Rodrigo Siqueira Signed-off-by: Yang Xiong Change-Id: I23428ae35e3a7898e55608622d2fc9de3237270a Signed-off-by: Ma Jun --- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 ++ .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 492fec079cc70..cba6f4670ee93 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -547,8 +547,10 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .set_crc_source = amdgpu_dm_crtc_set_crc_source, .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK .enable_vblank = amdgpu_dm_crtc_enable_vblank, .disable_vblank = amdgpu_dm_crtc_disable_vblank, +#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 412f1d90ec93d..ba4d038ec86f7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -75,8 +75,27 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET], [ ]) ]) +dnl # +dnl # commit v4.10-rc5-1070-g84e354839b15 +dnl # drm: add vblank hooks to struct drm_crtc_funcs +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc_funcs *crtc_funcs = NULL; + crtc_funcs->enable_vblank(NULL); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK, 1, [ + drm_crtc_funcs->enable_vblank() is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET ]) From 14d45cafdecd767d862a8efebb6b05221f0adc97 Mon Sep 17 00:00:00 2001 From: changzhu Date: Wed, 30 Jan 2019 13:07:27 +0800 Subject: [PATCH 0318/2653] drm/amdkcl: adapt drm_crtc_funcs->set_crc_source change [Why] In drm_crtc.h,drm_crtc_funcs->set_crc_source is defined since DRM_VERSION(4,10,0).It has three parameters until DRM_VERSION(4,20,0).After DRM_VERSION(4,20,0),it has two parameters.The change is as below: From: int (*set_crc_source)(struct drm_crtc *crtc, const char *source, size_t *values_cnt); To: int (*set_crc_source)(struct drm_crtc *crtc, const char *source); In amdgpu_dm.c.we have code: .set_crc_source = amdgpu_dm_crtc_set_crc_source, and amdgpu_dm_crtc_set_crc_source(crtc, "auto"); So we will meet build error when use amdgpu_dm_crtc_set_crc_source because it has three parameters before DRM_VERSION(4,20,0) In drm_crtc.h,drm_crtc_funcs->verify_crc_source is not defined until DRM_VERSION(4,20,0).However,this member is used by patch: drm/crc: Cleanup crtc_crc_open function This patch is needed because we use newly defined function amdgpu_dm_crtc_set_crc_source To fix drm_crtc_funcs->verify_crc_source customer build error,we need to cherry-pick patch: drm/amdgpu_dm/crc: Implement verify_crc_source callback So it will meet build error when use amdgpu_dm_crtc_verify_crc_source before DRM_VERSION(4,20,0) [How] Keep parameter:size_t *values_cnt before DRM_VERSION(4,20,0) to fix .set_crc_source = amdgpu_dm_crtc_set_crc_source, build error. Use amdgpu_dm_crtc_set_crc_source(crtc, "auto", NULL); before DRM_VERSION(4,20,0) to fix amdgpu_dm_crtc_set_crc_source(crtc, "auto"); build error. Avoid using amdgpu_dm_crtc_verify_crc_source before DRM_VERSION(4,20,0) It's a squash of drm/amdkcl: refactor test for drm_crtc_funcs->set_crc_source Signed-off-by: Flora Cui Acked-by: Rodrigo Siqueira drm/amdkcl: [4.20] fix amdgpu_dm_crtc_set_crc_source few arguments error Signed-off-by: changzhu Reviewed-by: Rui Teng Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang drm/amdkcl: add guarding for amdgpu_dm_crtc_handle_crc_irq call Signed-off-by: Jiansong Chen Reviewed-by: Jack Gui Signed-off-by: Yifan Zhang drm/amdkcl: test struct drm_crtc_funcs->get/verify_crtc_source Signed-off-by: Flora Cui Acked-by: Rodrigo Siqueira Change-Id: Ie33bf644377ad146ce486a2f0957f400e4929e3a Signed-off-by: changzhu Reviewed-by: tianci yin Signed-off-by: Jack Gui Signed-off-by: Yang Xiong Signed-off-by: Ma Jun --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 4 ++++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 3 +++ .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 ++ .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 22 +++++++++++++++++++ 5 files changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ebcfa046a3ce5..bc6cbf2473a22 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -664,7 +664,9 @@ static void dm_crtc_high_irq(void *interrupt_params) * Following stuff must happen at start of vblank, for crc * computation and below-the-range btr support in vrr mode. */ +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); +#endif /* BTR updates need to happen before VUPDATE on Vega and above. */ if (adev->family < AMDGPU_FAMILY_AI) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index e20aa74380665..a720908068a9d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -33,6 +33,7 @@ #include "amdgpu_securedisplay.h" #include "amdgpu_dm_psr.h" +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES static const char *const pipe_crc_sources[] = { "none", "crtc", @@ -41,6 +42,7 @@ static const char *const pipe_crc_sources[] = { "dprx dither", "auto", }; +#endif static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source) { @@ -77,6 +79,7 @@ static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src) (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE); } +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, size_t *count) { @@ -493,6 +496,7 @@ amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, *values_cnt = 3; return 0; } +#endif int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, struct dm_crtc_state *dm_crtc_state, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h index 95bdb8699d7fa..23c4afe44522e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h @@ -126,11 +126,14 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, struct dm_crtc_state *dm_crtc_state, enum amdgpu_dm_pipe_crc_source source); int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name); + +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, size_t *values_cnt); const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, size_t *count); +#endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES */ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); #else #define amdgpu_dm_crtc_set_crc_source NULL diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index cba6f4670ee93..69b8baa6db28c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -545,8 +545,10 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state, .atomic_destroy_state = amdgpu_dm_crtc_destroy_state, .set_crc_source = amdgpu_dm_crtc_set_crc_source, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, +#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK .enable_vblank = amdgpu_dm_crtc_enable_vblank, .disable_vblank = amdgpu_dm_crtc_disable_vblank, diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index ba4d038ec86f7..211d8df287f57 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -93,9 +93,31 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK], [ ]) ]) +dnl # +dnl # v5.2-rc5-2034-g8fb843d179a6 drm/amd/display: add functionality to get pipe CRC source. +dnl # v4.18-rc3-759-g3b3b8448ebd1 drm/amdgpu_dm/crc: Implement verify_crc_source callback +dnl # v4.18-rc3-757-g4396551e9cf3 drm: crc: Introduce get_crc_sources callback +dnl # v4.18-rc3-756-gd5cc15a0c66e drm: crc: Introduce verify_crc_source callback +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc_funcs *crtc_funcs = NULL; + crtc_funcs->get_crc_sources(NULL, NULL); + crtc_funcs->verify_crc_source(NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES, 1, [ + drm_crtc_funcs->{get,verify}_crc_sources() is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET ]) From 7958ab82cce6964288c72f66083f77637eba45ae Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Wed, 18 Sep 2019 23:25:40 +0800 Subject: [PATCH 0319/2653] drm/amdkcl: test whether drm_dp_mst_allocate_vcpi() has p,p,i,i interface It's a squash of drm/amdkcl: Test whether drm_dp_mst_{get,put}_port_malloc() is available Signed-off-by: Adam Yang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: I99ef7484b72edf3266bed3cd7cb0cc1db117f05d Signed-off-by: Adam Yang Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yang Xiong --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++ .../drm/amd/dkms/m4/drm-dp-mst-topology.m4 | 55 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 60 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 137f18d41f1b1..39d769bd95c19 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -159,7 +159,9 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector) drm_edid_free(aconnector->drm_edid); drm_connector_cleanup(connector); +#if defined(HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC) drm_dp_mst_put_port_malloc(aconnector->mst_output_port); +#endif /* HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC */ kfree(aconnector); } @@ -675,7 +677,9 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, */ amdgpu_dm_connector_funcs_reset(connector); +#if defined(HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC) drm_dp_mst_get_port_malloc(port); +#endif /* HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC */ return connector; } diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 new file mode 100644 index 0000000000000..5c6393f547854 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 @@ -0,0 +1,55 @@ +dnl # +dnl # commit 1e797f556c616a42f1e039b1ff1d3c58f61b6104 +dnl # drm/dp: Split drm_dp_mst_allocate_vcpi +dnl # +dnl # Note: This autoconf only works with compiler flag -Werror +dnl # The interface types are specified in Hungarian notation +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_mst_allocate_vcpi(NULL, NULL, 1, 1); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I, 1, [ + drm_dp_mst_allocate_vcpi() has p,p,i,i interface]) + ]) + ]) + dnl # + dnl # commit d25689760b747287c6ca03cfe0729da63e0717f4 + dnl # drm/amdgpu/display: Keep malloc ref to MST port + dnl # + dnl # commit ebcc0e6b509108b4a67daa4c55809a05ab7f4b77 + dnl # drm/dp_mst: Introduce new refcounting scheme for mstbs and ports + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_mst_get_port_malloc(NULL); + drm_dp_mst_put_port_malloc(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC, 1, [ + drm_dp_mst_{get,put}_port_malloc() is available]) + ]) + ]) + dnl # + dnl # commit aad0eab4e8dd76d1ba5248f9278633829cbcec38 + dnl # drm/dp_mst: Enable registration of AUX devices for MST ports + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_mst_connector_early_unregister(NULL, NULL); + drm_dp_mst_connector_late_register(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DP_MST_CONNECTOR_EARLY_UNREGISTER, 1, [ + drm_dp_mst_connector_early_unregister() is available]) + AC_DEFINE(HAVE_DP_MST_CONNECTOR_LATE_REGISTER, 1, [ + drm_dp_mst_connector_late_register() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a195dee0dcd92..ff2fe3a1f8016 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -99,6 +99,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT AC_AMDGPU_STRSCPY + AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 065bdb7fdbf836a77b5f3f5d3251d51261747231 Mon Sep 17 00:00:00 2001 From: changzhu Date: Fri, 19 Apr 2019 13:58:42 +0800 Subject: [PATCH 0320/2653] drm/amdkcl: test whether struct drm_dp_mst_topology_cbs has hotplug drm/amdkcl: [5.1] Fix multiple MST daisy chain issues within DM [Why] This patch fixes the following issues: - Null pointer dereference was found with MST monitor attached - MST daisy chain hotplugging doesn't work [How] Until DRM Ver.5.0, we need a MST hotplug function to deal with MST hotplug operations. (this function is not needed since DRV Ver.5.1 rc1). Hence a MST hotplug function is added to avoid hotplug failure. (the old hotplug structure was replaced within DRV Ver.5.1) Signed-off-by: Zhan Liu Reviewed-by: Xiaojie Yuan Reviewed-by: Junwei Zhang drm/amdkcl: fix dm_dp_mst_hotplug custom kernel build error [Why] There is build error when using dm_dp_mst_hotplug to build custom kernel on dkms-5.0 branch [How] Avoid using dm_dp_mst_hotplug when building custom kernel on dkms-5.0 branch. This kcl patch is supplement for kcl patch: drm/amdkcl: [5.1] Fix multiple MST daisy chain issues within DM Change-Id: I827c06eee369f0b5468e8298376f8aea344c5533 Signed-off-by: changzhu Reviewed-by: Zhan Liu drm/amdkcl: test whether struct drm_dp_mst_topology_cbs has hotplug Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 31 ++++++++++++++ .../amd/dkms/m4/drm-dp-mst-topology-cbs.m4 | 42 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 74 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 39d769bd95c19..7a4c80177d296 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -793,8 +793,39 @@ static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT); } +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG) +static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) +{ + struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr); + struct drm_device *dev = master->base.dev; + + drm_kms_helper_hotplug_event(dev); +} +#endif + +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR +static void dm_dp_mst_register_connector(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = dev->dev_private; + + if (adev->mode_info.rfbdev) + drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector); + else + DRM_ERROR("adev->mode_info.rfbdev is NULL\n"); + + drm_connector_register(connector); +} +#endif + static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { .add_connector = dm_dp_add_mst_connector, +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG) + .hotplug = dm_dp_mst_hotplug, +#endif +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR + .register_connector = dm_dp_mst_register_connector +#endif .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready, }; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 new file mode 100644 index 0000000000000..5847b52020f9f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -0,0 +1,42 @@ +dnl # +dnl # commit v4.20-rc4-941-g16bff572cc66 +dnl # drm/dp-mst-helper: Remove hotplug callback +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; + dp_mst_cbs->hotplug(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG, 1, + [struct drm_dp_mst_topology_cbs has hotplug member]) + ]) +]) + + +dnl # +dnl # commit v5.6-rc2-1065-ga5c4dc165957 +dnl # drm/dp_mst: Remove register_connector callback +dnl # +dnl # commit v4.3-rc3-39-gd9515c5ec1a2 +dnl # drm/dp/mst: split connector registration into two parts (v2) +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; + dp_mst_cbs->register_connector(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR, 1, + [struct drm_dp_mst_topology_cbs->register_connector is available]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ff2fe3a1f8016..f7d18acaf3e1e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -100,6 +100,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT AC_AMDGPU_STRSCPY AC_AMDGPU_DRM_DP_MST_TOPOLOGY + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 27a80cbbc067e8409ee23ba8983fa1c79992c04c Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 14 Aug 2019 12:52:25 +0800 Subject: [PATCH 0321/2653] drm/amdkcl: whether struct drm_atomic_state have async_update Change-Id: Ic9a0e4c28255e46fae3af23c0a12d0fbf6fccbf5 Signed-off-by: Yifan Zhang Reviewed-by: Feifei Xu Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index bc6cbf2473a22..ce722938dd1fb 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12152,6 +12152,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } + /* Perform validation of MST topology in the state*/ + ret = drm_dp_mst_atomic_check(state); + if (ret) + goto fail; + if (state->legacy_cursor_update) { /* * This is a fast cursor update coming from the plane update From 4dab4fd7208a0a8f3399135d82b469f919ae2c57 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Fri, 20 Sep 2019 09:27:01 +0800 Subject: [PATCH 0322/2653] drm/amdkcl: Test whether drm_connector_list_iter_begin is available Introduced by kernel v4.11-rc1~83^2~48^2~54 It's a squash of drm/amdkcl: refactor guard for drm_modeset_{lock,unlock}_all Signed-off-by: Flora Cui Acked-by: Rodrigo Siqueira drm/amdkcl: [4.14] fix drm_modeset_lock_all Signed-off-by: Evan Quan Reviewed-by: Junwei Zhang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang drm/amdkcl: rework kcl for amdgpu_pmops_runtime_idle Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: add kcl for amdgpu_pmops_runtime_idle Signed-off-by: Yifan Zhang drm/amdkcl: fix drm_connector_list_iter Signed-off-by: Flora Cui Change-Id: Iacbf79c46b7be3146e0b318c67769e10ff5b73a4 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Yang Xiong --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 10 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 10 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c | 32 +++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 40 ++++++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 40 ++++++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 48 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 40 ++++++++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30 ++++++++++-- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 8 ++++ .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 ++++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 7 +++ .../dkms/m4/drm-connector-list-iter-begin.m4 | 16 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 13 files changed, 286 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-list-iter-begin.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 0daeec36c8cbc..241a619395fe4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -1616,7 +1616,9 @@ amdgpu_connector_add(struct amdgpu_device *adev, { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector; struct amdgpu_connector_atom_dig *amdgpu_dig_connector; struct drm_encoder *encoder; @@ -1631,12 +1633,18 @@ amdgpu_connector_add(struct amdgpu_device *adev, return; /* see if we already added it */ +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->connector_id == connector_id) { amdgpu_connector->devices |= supported_device; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif return; } if (amdgpu_connector->ddc_bus && i2c_bus->valid) { @@ -1651,7 +1659,9 @@ amdgpu_connector_add(struct amdgpu_device *adev, } } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif /* check if it's a dp bridge */ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 11dee14c279a6..4162e50094f5e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -636,13 +636,19 @@ void amdgpu_display_print_display_setup(struct drm_device *dev) struct amdgpu_connector *amdgpu_connector; struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif uint32_t devices; int i = 0; - drm_connector_list_iter_begin(dev, &iter); DRM_INFO("AMDGPU Display Connectors\n"); +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN + drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif amdgpu_connector = to_amdgpu_connector(connector); DRM_INFO("Connector %d:\n", i); DRM_INFO(" %s\n", connector->name); @@ -706,7 +712,9 @@ void amdgpu_display_print_display_setup(struct drm_device *dev) } i++; } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c index 3aaeed2d35620..cd4bf5460252b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c @@ -36,14 +36,20 @@ amdgpu_link_encoder_connector(struct drm_device *dev) { struct amdgpu_device *adev = drm_to_adev(dev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector; struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); /* walk the list and link encoders to connectors */ drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif amdgpu_connector = to_amdgpu_connector(connector); list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { amdgpu_encoder = to_amdgpu_encoder(encoder); @@ -56,7 +62,9 @@ amdgpu_link_encoder_connector(struct drm_device *dev) } } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } void amdgpu_encoder_set_active_device(struct drm_encoder *encoder) @@ -64,10 +72,15 @@ void amdgpu_encoder_set_active_device(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -77,7 +90,9 @@ void amdgpu_encoder_set_active_device(struct drm_encoder *encoder) amdgpu_connector->devices, encoder->encoder_type); } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } struct drm_connector * @@ -86,18 +101,27 @@ amdgpu_get_connector_for_encoder(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct drm_connector *connector, *found = NULL; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { + +#else + drm_for_each_connector(connector, dev) { +#endif amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_encoder->active_device & amdgpu_connector->devices) { found = connector; break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif return found; } @@ -107,18 +131,26 @@ amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct drm_connector *connector, *found = NULL; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_encoder->devices & amdgpu_connector->devices) { found = connector; break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif return found; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 0794954bc138b..694c9a7faa9f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -334,11 +334,17 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -375,7 +381,9 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev) amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } /** @@ -390,11 +398,17 @@ static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -407,7 +421,9 @@ static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev) @@ -1235,7 +1251,9 @@ static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp; int interlace = 0; @@ -1243,14 +1261,20 @@ static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, if (!dig || !dig->afmt || !dig->afmt->pin) return; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1281,7 +1305,9 @@ static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp; u8 *sadb = NULL; @@ -1290,14 +1316,20 @@ static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder if (!dig || !dig->afmt || !dig->afmt->pin) return; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1337,7 +1369,9 @@ static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; struct cea_sad *sads; int i, sad_count; @@ -1360,14 +1394,20 @@ static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) if (!dig || !dig->afmt || !dig->afmt->pin) return; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index e8de733871d6f..cb3bdd0b2c1ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -358,11 +358,17 @@ static void dce_v11_0_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -398,7 +404,9 @@ static void dce_v11_0_hpd_init(struct amdgpu_device *adev) dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } /** @@ -413,11 +421,17 @@ static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -429,7 +443,9 @@ static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev) @@ -1267,7 +1283,9 @@ static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp; int interlace = 0; @@ -1275,14 +1293,20 @@ static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, if (!dig || !dig->afmt || !dig->afmt->pin) return; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1313,7 +1337,9 @@ static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp; u8 *sadb = NULL; @@ -1322,14 +1348,20 @@ static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder if (!dig || !dig->afmt || !dig->afmt->pin) return; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1369,7 +1401,9 @@ static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; struct cea_sad *sads; int i, sad_count; @@ -1392,14 +1426,20 @@ static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) if (!dig || !dig->afmt || !dig->afmt->pin) return; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index d728bedfe9d50..226a3c58fd16d 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -313,11 +313,17 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -344,7 +350,9 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev) dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } /** @@ -359,11 +367,17 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -375,7 +389,9 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev) @@ -1207,19 +1223,27 @@ static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; int interlace = 0; u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1251,20 +1275,28 @@ static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; u8 *sadb = NULL; int sad_count; u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1313,7 +1345,9 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; u32 offset; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; struct cea_sad *sads; int i, sad_count; @@ -1338,14 +1372,20 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) offset = dig->afmt->pin->offset; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1736,7 +1776,9 @@ static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); int bpc = 8; @@ -1744,14 +1786,20 @@ static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, if (!dig || !dig->afmt) return; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 08b7ec5c3dde8..dac59dc0e3695 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -296,11 +296,17 @@ static void dce_v8_0_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -327,7 +333,9 @@ static void dce_v8_0_hpd_init(struct amdgpu_device *adev) dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } /** @@ -342,11 +350,17 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -358,7 +372,9 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev) amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev) @@ -1190,7 +1206,9 @@ static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp = 0, offset; @@ -1199,14 +1217,20 @@ static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder, offset = dig->afmt->pin->offset; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1251,7 +1275,9 @@ static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 offset, tmp; u8 *sadb = NULL; @@ -1262,14 +1288,20 @@ static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) offset = dig->afmt->pin->offset; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1305,7 +1337,9 @@ static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; u32 offset; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; struct cea_sad *sads; int i, sad_count; @@ -1330,14 +1364,20 @@ static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) offset = dig->afmt->pin->offset; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ce722938dd1fb..7ebbf14b3978f 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1069,7 +1069,9 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, struct drm_device *dev = dev_get_drvdata(kdev); struct amdgpu_device *adev = drm_to_adev(dev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter conn_iter; +#endif struct amdgpu_dm_connector *aconnector; int ret = 0; @@ -1077,9 +1079,12 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, mutex_lock(&adev->dm.audio_lock); +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { - +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -1095,7 +1100,9 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, break; } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&conn_iter); +#endif mutex_unlock(&adev->dm.audio_lock); @@ -2628,12 +2635,17 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev) { struct amdgpu_dm_connector *aconnector; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif int ret = 0; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { - +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -2655,7 +2667,9 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev) } } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif return ret; } @@ -2803,12 +2817,17 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend) { struct amdgpu_dm_connector *aconnector; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct drm_dp_mst_topology_mgr *mgr; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { - +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -2838,7 +2857,10 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend) resume_mst_branch_status(mgr); } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif + } static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) @@ -3372,7 +3394,9 @@ static int dm_resume(struct amdgpu_ip_block *ip_block) struct amdgpu_display_manager *dm = &adev->dm; struct amdgpu_dm_connector *aconnector; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); enum dc_connection_type new_connection_type = dc_connection_none; struct dc_state *dc_state; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index a720908068a9d..8ab218a0307d3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -616,10 +616,16 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) dm_is_crc_source_dprx(cur_crc_src))) { struct amdgpu_dm_connector *aconn = NULL; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter conn_iter; +#endif +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(crtc->dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { +#else + drm_for_each_connector(connector, crtc->dev) { +#endif if (!connector->state || connector->state->crtc != crtc) continue; @@ -629,7 +635,9 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) aconn = to_amdgpu_dm_connector(connector); break; } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&conn_iter); +#endif if (!aconn) { DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 0265e1a891cf9..5604bdae86699 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3856,11 +3856,17 @@ static int mst_topo_show(struct seq_file *m, void *unused) struct amdgpu_device *adev = (struct amdgpu_device *)m->private; struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter conn_iter; +#endif struct amdgpu_dm_connector *aconnector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) continue; @@ -3873,7 +3879,9 @@ static int mst_topo_show(struct seq_file *m, void *unused) seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&conn_iter); +#endif return 0; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 7a4c80177d296..72cf080282b54 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -809,11 +809,18 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector) struct drm_device *dev = connector->dev; struct amdgpu_device *adev = dev->dev_private; +#ifndef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN + drm_modeset_lock_all(dev); +#endif if (adev->mode_info.rfbdev) drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector); else DRM_ERROR("adev->mode_info.rfbdev is NULL\n"); +#ifndef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN + drm_modeset_unlock_all(dev); +#endif + drm_connector_register(connector); } #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-list-iter-begin.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-list-iter-begin.m4 new file mode 100644 index 0000000000000..b9b18381ae244 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-list-iter-begin.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 613051dac40da1751ab269572766d3348d45a197 +dnl # drm: locking&new iterators for connector_list +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_LIST_ITER_BEGIN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_connector_list_iter_begin(NULL, NULL); + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN, 1, + [drm_connector_list_iter_begin() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f7d18acaf3e1e..fb8aae09e48ba 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -101,6 +101,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRSCPY AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS + AC_AMDGPU_DRM_CONNECTOR_LIST_ITER_BEGIN AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 02d772caf736c6c8be19bf162a244db70d6c2972 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 16 Jun 2020 10:55:00 +0800 Subject: [PATCH 0323/2653] drm/amdkcl: add test for drm_plane_helper_funcs->atomic_async_check the 2 callbacks are introduced in commit v4.12-rc7-1335-gfef9df8b5945("drm/atomic: initial support for asynchronous plane update") It's a squash of drm/amdkcl: [4.14] add kcl for "add fast path for cursor plane updates" Reviewed-by: Prike Liang Signed-off-by: Tianci Yin Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Change-Id: Iec3f145247132537e016e6895ade88eedbfb0ec2 Signed-off-by: Ma Jun --- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../dkms/m4/struct_drm_plane_helper_funcs.m4 | 18 ++++++++++++++++++ 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 8ba41973c0963..17151a2af8df6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1272,6 +1272,7 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, return -EINVAL; } +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, struct drm_atomic_state *state, bool flip) { @@ -1295,6 +1296,7 @@ static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, return 0; } +#endif int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, struct dc_cursor_position *position) @@ -1455,8 +1457,10 @@ static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { .prepare_fb = amdgpu_dm_plane_helper_prepare_fb, .cleanup_fb = amdgpu_dm_plane_helper_cleanup_fb, .atomic_check = amdgpu_dm_plane_atomic_check, +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK .atomic_async_check = amdgpu_dm_plane_atomic_async_check, .atomic_async_update = amdgpu_dm_plane_atomic_async_update +#endif }; static const struct drm_plane_helper_funcs dm_primary_plane_helper_funcs = { diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fb8aae09e48ba..7e0c53ad66d32 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -102,6 +102,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS AC_AMDGPU_DRM_CONNECTOR_LIST_ITER_BEGIN + AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 new file mode 100644 index 0000000000000..4dd6e4db74ff6 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v4.12-rc7-1335-gfef9df8b5945 +dnl # drm/atomic: initial support for asynchronous plane update +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_plane_helper_funcs *funcs = NULL; + funcs->atomic_async_check(NULL, NULL); + funcs->atomic_async_update(NULL, NULL); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK, 1, + [drm_plane_helper_funcs->atomic_async_check() is available]) + ]) + ]) +]) From b5b9fd7595d652755582e427e5ab2479dca865c1 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Fri, 27 Dec 2019 14:29:23 +0800 Subject: [PATCH 0324/2653] drm/amdkcl: Test whether drm_dp_mst_atomic_check() is available Change-Id: I6d5801df6e80e208e07e3806a031b8672d55e4d1 Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++++ .../drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 26 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7ebbf14b3978f..ef87faf9d4c7b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12176,10 +12176,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } +#if defined(HAVE_STRUCT_NAME_CB_NAME_2ARGS) && defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) /* Perform validation of MST topology in the state*/ ret = drm_dp_mst_atomic_check(state); if (ret) goto fail; +#endif if (state->legacy_cursor_update) { /* @@ -12292,11 +12294,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, * dc_validate_global_state(), or there is a chance * to get stuck in an infinite loop and hang eventually. */ +#ifdef HAVE_DRM_DP_MST_ATOMIC_CHECK ret = drm_dp_mst_atomic_check(state); if (ret) { drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed\n"); goto fail; } +#endif status = dc_validate_global_state(dc, dm_state->context, DC_VALIDATE_MODE_ONLY); if (status != DC_OK) { drm_dbg_atomic(dev, "DC global validation failure: %s (%d)", diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 72cf080282b54..6ed0b2fca7a34 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -873,6 +873,8 @@ int dm_mst_get_pbn_divider(struct dc_link *link) dc_link_get_link_cap(link)) / (8 * 1000 * 54); } +#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) && defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) struct dsc_mst_fairness_params { struct dc_crtc_timing *timing; struct dc_sink *sink; @@ -1795,6 +1797,7 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream, return is_dsc_possible; } #endif +#endif /* HAVE_DRM_DP_MST_ATOMIC_CHECK */ #if defined(CONFIG_DRM_AMD_DC_FP) static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_link_bw) @@ -1980,3 +1983,4 @@ enum dc_status dm_dp_mst_is_port_support_mode( #endif return DC_OK; } +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 new file mode 100644 index 0000000000000..dc4167e33a865 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit eceae147246749c6dbaeefda802b30f804a3c54c +dnl # drm/dp_mst: Start tracking per-port VCPI allocations +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + int ret; + ret = drm_dp_mst_atomic_check(NULL); + ], [drm_dp_mst_atomic_check], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_CHECK, 1, + [drm_dp_mst_atomic_check() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7e0c53ad66d32..0bb054e92ae2b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -103,6 +103,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS AC_AMDGPU_DRM_CONNECTOR_LIST_ITER_BEGIN AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS + AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 7b3c7256f84922090e67cbc28772ddc74d7dd0e8 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Mon, 6 Jan 2020 14:59:32 +0800 Subject: [PATCH 0325/2653] drm/amdkcl: Test whether drm_dp_calc_pbn_mode() wants three arguments v2: drm/amdkcl: Test whether mul_u32_u32 is available v3: drm/amdkcl: move kcl copy for drm_dp_mst_helper into backport part the macros definition should be in backport to warn amdkcl to NOT include it. It is not necessary to wrap a mul_u32_u32() funcion, because function mul_u32_u32() is introdued into kernel before function drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc). Signed-off-by: Stanley.Yang Signed-off-by: Yifan Zhang Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../backport/kcl_drm_dp_mst_helper_backport.h | 14 ++++++++++++++ 3 files changed, 31 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 new file mode 100644 index 0000000000000..d168a591bcd23 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 9a7c0da823fd4e65098bd466a996503cc8309c0e +dnl # drm/dp_mst: Add PBN calculation for DSC modes +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_calc_pbn_mode(0, 0, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS, 1, + [drm_dp_calc_pbn_mode() wants 3args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0bb054e92ae2b..e74cc72e218eb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -62,6 +62,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC + AC_AMDGPU_DRM_DP_CALC_PBN_MODE AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 85fa328d0aa09..183e49a5ba766 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -24,6 +24,20 @@ #include +/* Copied from drivers/gpu/drm/drm_dp_mst_topology.c and modified for KCL */ +#if !defined(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS) +static inline +int _kcl_drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) +{ + if (dsc) + return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006), + 8 * 54 * 1000 * 1000); + + return drm_dp_calc_pbn_mode(clock, bpp); +} +#define drm_dp_calc_pbn_mode _kcl_drm_dp_calc_pbn_mode +#endif + #if defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS) #if !defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS) static inline From ed345e6948c40849dc9cfbc093f181869ced68ec Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 21 Jan 2020 15:22:52 +0800 Subject: [PATCH 0326/2653] drm/amdkcl: refactor test for drm_connector_helper_funcs->atomic_check it is a squash of: commit ae74c678762b314212c82c0afcbc7b06f18f3c15 Author: Slava Grigorev Date: Thu Feb 13 12:43:57 2020 -0500 drm/amdkcl: properly define the root of the build directories Change-Id: I5064df48df8b742be9175b01ba9340378d674103 Signed-off-by: Slava Grigorev Change-Id: I32b0308637042a254d34dc5b1a7d0b01fee0190c Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Yifan Zhang Signed-off-by: Slava Grigorev Signed-off-by: Ma Jun --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +++++++----- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 ++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++++ .../amd/dkms/m4/drm-connector-helper-funcs.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 32 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ef87faf9d4c7b..238c83825f55a 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6651,7 +6651,6 @@ static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) for (i = 0; i < context->stream_count ; i++) { stream = context->streams[i]; - if (!stream) continue; @@ -6722,7 +6721,6 @@ get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, return NULL; } } - highest_refresh = drm_mode_vrefresh(m_pref); /* @@ -7339,7 +7337,6 @@ static void amdgpu_dm_connector_unregister(struct drm_connector *connector) cec_notifier_conn_unregister(amdgpu_dm_connector->notifier); drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); } - static void amdgpu_dm_connector_destroy(struct drm_connector *connector) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); @@ -7373,7 +7370,6 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector) kfree(aconnector->i2c); } kfree(aconnector->dm_dp_aux.aux.name); - kfree(connector); } @@ -7395,8 +7391,10 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) state->underscan_hborder = 0; state->underscan_vborder = 0; state->base.max_requested_bpc = 8; +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) state->vcpi_slots = 0; state->pbn = 0; +#endif if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { if (amdgpu_dm_abm_level <= 0) @@ -7429,8 +7427,10 @@ amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) new_state->underscan_enable = state->underscan_enable; new_state->underscan_hborder = state->underscan_hborder; new_state->underscan_vborder = state->underscan_vborder; +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) new_state->vcpi_slots = state->vcpi_slots; new_state->pbn = state->pbn; +#endif return &new_state->base; } @@ -7921,6 +7921,7 @@ static void dm_encoder_helper_disable(struct drm_encoder *encoder) } +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) { switch (display_color_depth) { @@ -7941,6 +7942,7 @@ int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) } return 0; } +#endif static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, @@ -12176,7 +12178,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } -#if defined(HAVE_STRUCT_NAME_CB_NAME_2ARGS) && defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) && defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) /* Perform validation of MST topology in the state*/ ret = drm_dp_mst_atomic_check(state); if (ret) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 26efd8de61e6d..4d368d957cb02 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -1001,8 +1001,10 @@ struct dm_connector_state { bool freesync_capable; bool update_hdcp; uint8_t abm_level; +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) int vcpi_slots; uint64_t pbn; +#endif }; #define to_dm_connector_state(x)\ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 6ed0b2fca7a34..451186a1f9e62 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -552,6 +552,7 @@ dm_dp_mst_detect(struct drm_connector *connector, return connection_status; } +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) static int dm_dp_mst_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state) { @@ -561,13 +562,16 @@ static int dm_dp_mst_atomic_check(struct drm_connector *connector, return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); } +#endif static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = { .get_modes = dm_dp_mst_get_modes, .mode_valid = amdgpu_dm_connector_mode_valid, .atomic_best_encoder = dm_mst_atomic_best_encoder, .detect_ctx = dm_dp_mst_detect, +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) .atomic_check = dm_dp_mst_atomic_check, +#endif }; static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 new file mode 100644 index 0000000000000..148d0cc472804 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.2-rc2-529-g6f3b62781bbd +dnl # drm: Convert connector_helper_funcs->atomic_check to accept drm_atomic_state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_connector_helper_funcs *p = NULL; + p->atomic_check(NULL, (struct drm_atomic_state*)NULL); + ], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE, 1, + [drm_connector_helper_funcs->atomic_check() wants struct drm_atomic_state arg]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e74cc72e218eb..09403da5cbf04 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -105,6 +105,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_LIST_ITER_BEGIN AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK + AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 92cde58f9e5d52a5f6f789bcb4a0ddf5a836ed91 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Wed, 8 Jan 2020 14:23:18 +0800 Subject: [PATCH 0327/2653] drm/amdkcl: Test whether drm_dp_mst_atomic_enable_dsc() is available Change-Id: If8f9e171797152ab6a10c4bc05b1e8cf014f0d98 Signed-off-by: Stanley.Yang Acked-by: Hawking Zhang Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++++++ .../amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 25 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 238c83825f55a..bb2eec0221f68 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8020,6 +8020,8 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { .atomic_check = dm_encoder_helper_atomic_check }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +#if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, struct dc_state *dc_state, struct dsc_mst_fairness_vars *vars) @@ -8096,6 +8098,8 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, } return 0; } +#endif +#endif static int to_drm_connector_type(enum signal_type st) { @@ -12284,11 +12288,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } #endif +#if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); if (ret) { drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed\n"); goto fail; } +#endif /* * Perform validation of MST topology in the state: @@ -12297,11 +12303,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, * to get stuck in an infinite loop and hang eventually. */ #ifdef HAVE_DRM_DP_MST_ATOMIC_CHECK +#if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) ret = drm_dp_mst_atomic_check(state); if (ret) { drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed\n"); goto fail; } +#endif #endif status = dc_validate_global_state(dc, dm_state->context, DC_VALIDATE_MODE_ONLY); if (status != DC_OK) { diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 new file mode 100644 index 0000000000000..17422c2217f46 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 0529a1d385b9ce6cd7498d180f720eeb3f755980 +dnl # drm/dp_mst: Add DSC enablement helpers to DRM +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_mst_atomic_enable_dsc(NULL, NULL, 0, 0, false); + ], [drm_dp_mst_atomic_enable_dsc], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC, 1, + [drm_dp_mst_atomic_enable_dsc() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 09403da5cbf04..bee36fc161a71 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -105,6 +105,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_LIST_ITER_BEGIN AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK + AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK AC_KERNEL_WAIT From edc0a5f893bd512d0a25055a0621aa8cb1effa8e Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Fri, 12 May 2017 09:35:40 +0800 Subject: [PATCH 0328/2653] drm/amdkcl: [4.11] fix for drm_dp_mst_topology_mgr_init This is a squash of: drm/amdkcl: test drm_dp_mst_topology_mgr_init() the prototype change introduced in v4.10-rc3-517-g7b0a89a6db9a Change-Id: I288af7fc96335e1ae8d1aaf768f4f3f7bb6a8810 Signed-off-by: Evan Quan Reviewed-by: Junwei Zhang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- .../amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 2 files changed, 18 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 new file mode 100644 index 0000000000000..98d2982594b7c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v4.10-rc3-517-g7b0a89a6db9a +dnl # drm/dp: Store drm_device in MST topology manager +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_mst_topology_mgr_init(NULL, (struct drm_device *)NULL, NULL, 0, 0, 0, 0, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT, 1, + [drm_dp_mst_topology_mgr_init() has max_lane_count and max_link_rate]) + + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index bee36fc161a71..bf7790bd270ee 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -107,6 +107,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 9982d82e151b97f75de70b04a3ccd59b92eb087d Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Mon, 25 Nov 2019 13:53:09 +0800 Subject: [PATCH 0329/2653] drm/amdkcl: [4.8] fix drm helper func - .atomic_commit_tail This is a squash of: drm/amdkcl: test drm_mode_config->helper_private Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Change-Id: I6c9491d9985d0054887df89e76d007b202e703b5 Signed-off-by: Chengming Gui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index bb2eec0221f68..cef07cc1612ba 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3635,10 +3635,12 @@ static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { .atomic_commit = drm_atomic_helper_commit, }; +#ifdef HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, }; +#endif static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) { @@ -4669,7 +4671,9 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) adev->mode_info.mode_config_initialized = true; adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; +#ifdef HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; +#endif adev_to_drm(adev)->mode_config.max_width = 16384; adev_to_drm(adev)->mode_config.max_height = 16384; From 1339cb8d0fc40fe978a6f419d8d8af81aab12002 Mon Sep 17 00:00:00 2001 From: tianci yin Date: Mon, 21 Jan 2019 10:45:32 +0800 Subject: [PATCH 0330/2653] drm/amdkcl: [5.0] fix null pointer crash in drm_pick_crtcs It is a squash of: amd/amdkcl: drop AC_AMDGPU_DRM_ATOMIC_HELPER_BEST_ENCODER test [why] drm_pick_crtcs called the best_encoder function pointer directly without NULL checking on rhel6.10, and patch "drm/amdgpu: Remove default best_encoder hook from DC" remove the assignment for .best_encoder, this cause the null crash. [how] bring the assignment code back for these old kernel. Change-Id: I5e687b6c3c83ad3814204c6f7e9a9e8338e18fae Reviewed-by: changzhu Signed-off-by: Tianci Yin Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Ma Jun Signed-off-by: tianci yin --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 31 ++++++++++--------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index cef07cc1612ba..e26d1f873875f 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7907,6 +7907,21 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, return 0; } +static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) +{ +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS + struct drm_encoder *encoder; + + /* There is only one encoder per connector */ + drm_connector_for_each_possible_encoder(connector, encoder) + return encoder; + + return NULL; +#else + return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]); +#endif +} + static const struct drm_connector_helper_funcs amdgpu_dm_connector_helper_funcs = { /* @@ -7918,6 +7933,7 @@ amdgpu_dm_connector_helper_funcs = { .get_modes = get_modes, .mode_valid = amdgpu_dm_connector_mode_valid, .atomic_check = amdgpu_dm_connector_atomic_check, + .best_encoder = amdgpu_dm_connector_to_encoder }; static void dm_encoder_helper_disable(struct drm_encoder *encoder) @@ -8130,21 +8146,6 @@ static int to_drm_connector_type(enum signal_type st) } } -static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) -{ -#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS - struct drm_encoder *encoder; - - /* There is only one encoder per connector */ - drm_connector_for_each_possible_encoder(connector, encoder) - return encoder; - - return NULL; -#else - return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]); -#endif -} - static void amdgpu_dm_get_native_mode(struct drm_connector *connector) { struct drm_encoder *encoder; From b4981322e566551d72c1ddf125a57ba44d8170be Mon Sep 17 00:00:00 2001 From: changzhu Date: Mon, 4 Mar 2019 10:32:16 +0800 Subject: [PATCH 0331/2653] drm/amdkcl: [4.12] fix for Refactor pageflips plane commit This is a squash of: drm/amdkcl: [4.12] fix drm_crtc_state pageflip_flags build error in amdgpu_dm_atomic_commit_tail drm/amdkcl: Test whether drm_crtc_state->async_flip is available drm/amdkcl: [4.12] Reserve flip_flags for display usage drm/amdkcl: add test for drm_crtc_state->pageflip_flags drm/amdkcl: refactor test for pageflip flag in struct drm-crtc-state [Why] In patch:drm/amd/display: Refactor pageflips plane commit Pageflip code is moved from an if statement to after a continue. Because the new code lacks the kcl control,we need to implement it in the new code. [How] Use the old kcl control way in the new code. Change-Id: I82ada88f319ee7c0b9a33f798123ef01e0371b8d Signed-off-by: changzhu Reviewed-by: tianci yin Reviewed-by: Prike Liang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: I8b738edde37ecee67d0aba0dcfaf49d4dd881413 Signed-off-by: changzhu Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: I922e6eefbe5ae01c8a69c4467ea3f22f8398a1e8 Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: Ia7396521f5e11468e83cf2cabac1b6cbbcda21cd Signed-off-by: Le.Ma Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Change-Id: I2f78c678a412ba5945af3d584a525fed5714a6c0 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +++++++++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 5 +++++ drivers/gpu/drm/amd/dkms/m4/drm-crtc-state.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 32 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-crtc-state.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e26d1f873875f..8da1a89e5c0dc 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9551,7 +9551,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, plane->base.id, plane->name); bundle->flip_addrs[planes_count].flip_immediate = +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) crtc->state->async_flip && +#else + (crtc->state->pageflip_flags & + DRM_MODE_PAGE_FLIP_ASYNC) != 0 && +#endif acrtc_state->update_type == UPDATE_TYPE_FAST && get_mem_type(old_plane_state->fb) == get_mem_type(fb); @@ -10499,7 +10504,11 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) } for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) if (new_crtc_state->async_flip) +#else + if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) +#endif wait_for_vblank = false; /* update planes when needed per crtc*/ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 69b8baa6db28c..187ddb4eac99e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -659,7 +659,12 @@ static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, * Only allow async flips for fast updates that don't change the FB * pitch, the DCC state, rotation, etc. */ +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) if (crtc_state->async_flip && +#else + if ((crtc->state->pageflip_flags & + DRM_MODE_PAGE_FLIP_ASYNC) != 0 && +#endif dm_crtc_state->update_type != UPDATE_TYPE_FAST) { drm_dbg_atomic(crtc->dev, "[CRTC:%d:%s] async flips are only supported for fast updates\n", diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-state.m4 new file mode 100644 index 0000000000000..cc6860f55c68e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-state.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.3-rc3-2032-g4d85f45c73a2 +dnl # drm/atomic: Rename crtc_state->pageflip_flags to async_flip +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_STATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc_state *crtc_state = NULL; + crtc_state->async_flip = 0; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP, 1, + [struct drm_crtc_state->async_flip is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index bf7790bd270ee..cbf5f0f365ca2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -107,6 +107,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_KERNEL_WAIT From 16969510ce9f07bc08e99b91dfaf9ac38c5a1b9e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 6 Dec 2019 15:39:25 +0800 Subject: [PATCH 0332/2653] drm/amdkcl: [display] add missing linux/debugfs.h for amdgpu_dm_debugfs.c Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 5604bdae86699..e30d3d0bcec34 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "dc.h" #include "amdgpu.h" From 294c94073d09dca4838267cc54a8aed06fa7ed03 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Mar 2024 16:35:34 +0800 Subject: [PATCH 0333/2653] drm/amdkcl: Test whether drm_dp_mst_detect_port() is available v2: drm/amdkcl: fix drm_dp_mst_detect_port() prototype change v2 Change-Id: I3c263f29db3827f340eb80aecd0d48335f8d53c7 Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Asher Song --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 22 +++++++++++++++++++ .../drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 | 17 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 40 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 451186a1f9e62..c44a380338464 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -143,7 +143,22 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, return result; } +#ifndef HAVE_DRM_DP_MST_DETECT_PORT_PPPP +static enum drm_connector_status +dm_dp_mst_detect(struct drm_connector *connector, bool force) +{ + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); + struct amdgpu_dm_connector *master = aconnector->mst_port; + + enum drm_connector_status status = + drm_dp_mst_detect_port( + connector, + &master->mst_mgr, + aconnector->port); + return status; +} +#endif static void dm_dp_mst_connector_destroy(struct drm_connector *connector) { @@ -230,6 +245,9 @@ amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) } static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { +#ifndef HAVE_DRM_DP_MST_DETECT_PORT_PPPP + .detect = dm_dp_mst_detect, +#endif .fill_modes = drm_helper_probe_single_connector_modes, .destroy = dm_dp_mst_connector_destroy, .reset = amdgpu_dm_connector_funcs_reset, @@ -481,6 +499,7 @@ dm_mst_atomic_best_encoder(struct drm_connector *connector, return &adev->dm.mst_encoders[acrtc->crtc_id].base; } +#ifdef HAVE_DRM_DP_MST_DETECT_PORT_PPPP static int dm_dp_mst_detect(struct drm_connector *connector, struct drm_modeset_acquire_ctx *ctx, bool force) @@ -551,6 +570,7 @@ dm_dp_mst_detect(struct drm_connector *connector, return connection_status; } +#endif #if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) static int dm_dp_mst_atomic_check(struct drm_connector *connector, @@ -568,7 +588,9 @@ static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs .get_modes = dm_dp_mst_get_modes, .mode_valid = amdgpu_dm_connector_mode_valid, .atomic_best_encoder = dm_mst_atomic_best_encoder, +#ifdef HAVE_DRM_DP_MST_DETECT_PORT_PPPP .detect_ctx = dm_dp_mst_detect, +#endif #if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) .atomic_check = dm_dp_mst_atomic_check, #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 new file mode 100644 index 0000000000000..4198140ed6a0e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.4-rc4-752-g3f9b3f02dda5 +dnl # drm/dp_mst: Protect drm_dp_mst_port members with locking +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DETECT_PORT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int ret; + ret = drm_dp_mst_detect_port(NULL, NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_DETECT_PORT_PPPP, 1, + [drm_dp_mst_detect_port() wants p,p,p,p args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cbf5f0f365ca2..f441c90e708a3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -107,6 +107,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DRM_DP_MST_DETECT_PORT AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT From a248aa1ede2cbe2882ffcc0e5d3f22ea1da21dd9 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 6 Dec 2019 16:31:52 +0800 Subject: [PATCH 0334/2653] drm/amdkcl: fix for commit "drm/amd/display: Expose HDR output metadata for supported connectors" Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: I03f5e07550343e269ef5cb7b0dba24249ad20adb --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +++++++++++++++---- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8da1a89e5c0dc..79436428c9119 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6988,7 +6988,6 @@ create_stream_for_sink(struct drm_connector *connector, sink = aconnector->dc_sink; dc_sink_retain(sink); } - stream = dc_create_stream_for_sink(sink); if (stream == NULL) { @@ -7778,6 +7777,7 @@ enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connec return result; } +#ifdef HDMI_DRM_INFOFRAME_SIZE static int fill_hdr_info_packet(const struct drm_connector_state *state, struct dc_info_packet *out) { @@ -7906,7 +7906,7 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, return 0; } - +#endif static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) { #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS @@ -7932,7 +7932,9 @@ amdgpu_dm_connector_helper_funcs = { */ .get_modes = get_modes, .mode_valid = amdgpu_dm_connector_mode_valid, +#ifdef HDMI_DRM_INFOFRAME_SIZE .atomic_check = amdgpu_dm_connector_atomic_check, +#endif .best_encoder = amdgpu_dm_connector_to_encoder }; @@ -8565,6 +8567,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, if (connector_type == DRM_MODE_CONNECTOR_HDMIA || connector_type == DRM_MODE_CONNECTOR_DisplayPort || connector_type == DRM_MODE_CONNECTOR_eDP) { + drm_connector_attach_hdr_output_metadata_property(&aconnector->base); if (!aconnector->mst_root) @@ -10334,9 +10337,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); struct dc_surface_update *dummy_updates; struct dc_stream_update stream_update; - struct dc_info_packet hdr_packet; struct dc_stream_status *status = NULL; - bool abm_changed, hdr_changed, scaling_changed, output_color_space_changed = false; +#ifdef HDMI_DRM_INFOFRAME_SIZE + struct dc_info_packet hdr_packet; + bool hdr_changed; +#endif + bool abm_changed, scaling_changed, output_color_space_changed = false; memset(&stream_update, 0, sizeof(stream_update)); @@ -10363,10 +10369,16 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) abm_changed = dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level; +#ifdef HDMI_DRM_INFOFRAME_SIZE hdr_changed = !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); +#endif - if (!scaling_changed && !abm_changed && !hdr_changed && !output_color_space_changed) + if (!scaling_changed && !abm_changed && !output_color_space_changed +#ifdef HDMI_DRM_INFOFRAME_SIZE + && !hdr_changed +#endif + ) continue; stream_update.stream = dm_new_crtc_state->stream; @@ -10391,10 +10403,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) stream_update.abm_level = &dm_new_crtc_state->abm_level; } +#ifdef HDMI_DRM_INFOFRAME_SIZE if (hdr_changed) { fill_hdr_info_packet(new_con_state, &hdr_packet); stream_update.hdr_static_metadata = &hdr_packet; } +#endif status = dc_stream_get_status(dm_new_crtc_state->stream); @@ -10927,10 +10941,12 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; +#ifdef HDMI_DRM_INFOFRAME_SIZE ret = fill_hdr_info_packet(drm_new_conn_state, &new_stream->hdr_static_metadata); if (ret) goto fail; +#endif /* * If we already removed the old stream from the context From 3e723734995c739412c219dde2ed8d938fe7dc35 Mon Sep 17 00:00:00 2001 From: Jiansong Chen Date: Thu, 19 Dec 2019 14:58:42 +0800 Subject: [PATCH 0335/2653] drm/amdkcl: fix implicit declaration of prepare_flip_isr dm_page_flip is activated for CentOS7.3 kernel(drm version 4.6.5). The funciton will call prepare_flip_isr and its definition is in front of prepare_flip_isr. Change-Id: I084653267001f327adb75f05b9b8f6608af1d9c1 Signed-off-by: Jiansong Chen Reviewed-by: Flora Cui Reviewed-by: Jack Gui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 79436428c9119..24511d1547267 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -244,7 +244,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); - +static void prepare_flip_isr(struct amdgpu_crtc *acrtc); static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); static void handle_hpd_rx_irq(void *param); From f0e0174e8cacadc7bc8a051777e4ac24d99fd422 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Thu, 26 Dec 2019 17:15:39 +0800 Subject: [PATCH 0336/2653] drm/amdkcl: Test whether drm_dp_mst_dsc_aux_for_port is available Change-Id: If098c1c8474741511e7ae338be90c1a382e3f5cc Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 9 +++++++-- .../amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 24 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index c44a380338464..bdfb1efe6f07a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -293,8 +293,9 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 u8 *dsc_branch_dec_caps = NULL; +#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port); - +#endif /* * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs * because it only check the dsc/fec caps of the "port variable" and not the dock @@ -468,6 +469,8 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) amdgpu_dm_update_freesync_caps( connector, aconnector->drm_edid); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) #if defined(CONFIG_DRM_AMD_DC_FP) if (!validate_dsc_caps_on_connector(aconnector)) memset(&aconnector->dc_sink->dsc_caps, @@ -477,6 +480,8 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) if (!retrieve_downstream_port_device(aconnector)) memset(&aconnector->mst_downstream_port_present, 0, sizeof(aconnector->mst_downstream_port_present)); +#endif +#endif } } @@ -900,7 +905,7 @@ int dm_mst_get_pbn_divider(struct dc_link *link) } #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) && defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) +#if defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) struct dsc_mst_fairness_params { struct dc_crtc_timing *timing; struct dc_sink *sink; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 new file mode 100644 index 0000000000000..06d77b61ab828 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit d251c02a2b78245bb32d7909a66b06285f7922a2 +dnl # drm/dp_mst: Add helpers for MST DSC and virtual DPCD aux +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_mst_dsc_aux_for_port(NULL); + ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT, 1, + [drm_dp_mst_dsc_aux_for_port() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f441c90e708a3..b22199f06ac1c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -109,6 +109,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_DETECT_PORT AC_AMDGPU_STRUCT_DRM_CRTC_STATE + AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_KERNEL_WAIT From 8d9373156dfc10443b0ac1eec0ac907a91eeed6a Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Fri, 27 Dec 2019 15:20:06 +0800 Subject: [PATCH 0337/2653] drm/amdkcl: Test whether drm_dp_mst_add_affected_dsc_crtcs() is available Change-Id: Icefa820b7602cfd943cbb4d49caac6fa71083263 Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ .../m4/drm-dp-mst-add-affected-dsc-crtcs.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 22 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 24511d1547267..1869620402d3b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11677,6 +11677,7 @@ static inline struct __drm_planes_state *__get_next_zpos( (old_plane_state) = __i->old_state, \ (new_plane_state) = __i->new_state, 1)) +#if defined(HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS) static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) { struct drm_connector *connector; @@ -11706,6 +11707,7 @@ static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); } +#endif /** * DOC: Cursor Modes - Native vs Overlay @@ -11969,6 +11971,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, new_crtc_state->connectors_changed = true; } +#if defined(HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS) if (dc_resource_is_dsc_encoding_supported(dc)) { for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { @@ -11980,6 +11983,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } } +#endif for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 new file mode 100644 index 0000000000000..1d4564270d065 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 971fb192aaeb4b5086ac3f21d00943a5e1431176 +dnl # drm/dp_mst: Add helper to trigger modeset on affected DSC MST CRTCs +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + int ret; + ret = drm_dp_mst_add_affected_dsc_crtcs(NULL, NULL); + ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS, 1, + [drm_dp_mst_add_affected_dsc_crtcs() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b22199f06ac1c..63862e7be7ba8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -110,6 +110,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_DETECT_PORT AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT + AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_KERNEL_WAIT From 055e04539f0f70f629eb50dd09b8185102b67943 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 21 Jan 2020 15:35:48 +0800 Subject: [PATCH 0338/2653] drm/amdkcl: adapt for drm_connector_helper_funcs->atomic_check() prototype change prototype change is in v5.2-rc2-529-g6f3b62781bbd macro HDMI_DRM_INFOFRAME_SIZE is introduced in v5.1-rc5-1691-g2cdbfd66a829 thus there's no need to check atomic_check() availability. Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Flora Cui Signed-off-by: Yifan Zhang Change-Id: I511b2784fc4d815f3425a58ecc1b64ae8e291444 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1869620402d3b..e40eec04e11a3 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7839,10 +7839,16 @@ static int fill_hdr_info_packet(const struct drm_connector_state *state, static int amdgpu_dm_connector_atomic_check(struct drm_connector *conn, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE struct drm_atomic_state *state) { struct drm_connector_state *new_con_state = drm_atomic_get_new_connector_state(state, conn); +#else + struct drm_connector_state *new_con_state) +{ + struct drm_atomic_state *state = new_con_state->state; +#endif struct drm_connector_state *old_con_state = drm_atomic_get_old_connector_state(state, conn); struct drm_crtc *crtc = new_con_state->crtc; From 9ee52295f19abaa10e17bad221b93923f043a00f Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 4 Mar 2020 15:46:02 +0800 Subject: [PATCH 0339/2653] drm/amdkcl: add HAVE_HDR_SINK_METADATA macro v3 Change-Id: Ifbf6c42b1b46065c6e7836e80bb505e14dfdf76c Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 45 +++++++++++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 ++ .../drm/amd/dkms/m4/drm-hdr-sink-metadata.m4 | 20 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 70 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-hdr-sink-metadata.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e40eec04e11a3..7b83d5f46fba1 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3642,6 +3642,7 @@ static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { }; #endif +#ifdef HAVE_HDR_SINK_METADATA static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) { struct amdgpu_dm_backlight_caps *caps; @@ -3692,6 +3693,7 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) if (min_input_signal_override >= 0) caps->min_input_signal = min_input_signal_override; } +#endif DEFINE_FREE(sink_release, struct dc_sink *, if (_T) dc_sink_release(_T)) @@ -3815,7 +3817,9 @@ void amdgpu_dm_update_connector_after_detect( } amdgpu_dm_update_freesync_caps(connector, aconnector->drm_edid); +#ifdef HAVE_HDR_SINK_METADATA update_connector_ext_caps(aconnector); +#endif } else { hdmi_cec_unset_edid(aconnector); drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); @@ -4732,7 +4736,9 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 #define AMDGPU_DM_MIN_SPREAD ((AMDGPU_DM_DEFAULT_MAX_BACKLIGHT - AMDGPU_DM_DEFAULT_MIN_BACKLIGHT) / 2) +#ifdef HAVE_HDR_SINK_METADATA #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 +#endif static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, int bl_idx) @@ -4765,8 +4771,10 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, caps->caps_valid = true; } #else +#ifdef HAVE_HDR_SINK_METADATA if (caps->aux_support) return; +#endif caps->min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; caps->max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; @@ -4774,6 +4782,7 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, #endif } +#ifdef HAVE_HDR_SINK_METADATA static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, unsigned int *min, unsigned int *max) { @@ -4874,19 +4883,25 @@ static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *cap return DIV_ROUND_CLOSEST_ULL((u64)max * (brightness - min), max - min); } +#endif static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, int bl_idx, u32 user_brightness) { struct amdgpu_dm_backlight_caps *caps; +#ifdef HAVE_HDR_SINK_METADATA struct dc_link *link; u32 brightness; +#else + uint32_t brightness = user_brightness; +#endif bool rc, reallow_idle = false; amdgpu_dm_update_backlight_caps(dm, bl_idx); caps = &dm->backlight_caps[bl_idx]; +#ifdef HAVE_HDR_SINK_METADATA dm->brightness[bl_idx] = user_brightness; /* update scratch register */ if (bl_idx == 0) @@ -4932,6 +4947,30 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, if (rc) dm->actual_brightness[bl_idx] = user_brightness; +#else + /* + * The brightness input is in the range 0-255 + * It needs to be rescaled to be between the + * requested min and max input signal + * + * It also needs to be scaled up by 0x101 to + * match the DC interface which has a range of + * 0 to 0xffff + */ + brightness = + brightness + * 0x101 + * (caps.max_input_signal - caps.min_input_signal) + / AMDGPU_MAX_BL_LEVEL + + caps.min_input_signal * 0x101; + + rc = dc_link_set_backlight_level(dm->backlight_link[bl_idx], brightness, 0); + + if (!rc) + DRM_ERROR("DM: Failed to update backlight on eDP[%d]\n", bl_idx); + if (rc) + dm->actual_brightness[bl_idx] = user_brightness; +#endif } static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) @@ -4960,6 +4999,7 @@ static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, amdgpu_dm_update_backlight_caps(dm, bl_idx); caps = dm->backlight_caps[bl_idx]; +#ifdef HAVE_HDR_SINK_METADATA if (caps.aux_support) { u32 avg, peak; @@ -4967,13 +5007,18 @@ static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, return dm->brightness[bl_idx]; return convert_brightness_to_user(&caps, avg); } +#endif ret = dc_link_get_backlight_level(link); if (ret == DC_ERROR_UNEXPECTED) return dm->brightness[bl_idx]; +#ifdef HAVE_HDR_SINK_METADATA return convert_brightness_to_user(&caps, ret); +#else + return ret; +#endif } static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 4d368d957cb02..83db6da8f1a63 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -171,6 +171,7 @@ struct amdgpu_dm_luminance_data { * Describe the backlight support for ACPI or eDP AUX. */ struct amdgpu_dm_backlight_caps { +#ifdef HAVE_HDR_SINK_METADATA /** * @ext_caps: Keep the data struct with all the information about the * display support for HDR. @@ -185,6 +186,7 @@ struct amdgpu_dm_backlight_caps { * in nits. */ u32 aux_max_input_signal; +#endif /** * @min_input_signal: minimum possible input in range 0-255. */ @@ -200,7 +202,9 @@ struct amdgpu_dm_backlight_caps { /** * @aux_support: Describes if the display supports AUX backlight. */ +#ifdef HAVE_HDR_SINK_METADATA bool aux_support; +#endif /** * @ac_level: the default brightness if booted on AC */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdr-sink-metadata.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdr-sink-metadata.m4 new file mode 100644 index 0000000000000..31c75e5910a4e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-hdr-sink-metadata.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit fbb5d0353c62d10c3699ec844d2d015a762952d7 +dnl # drm: Add HDR source metadata property +dnl # + +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HAVE_HDR_SINK_METADATA], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector *dc = NULL; + struct hdr_sink_metadata *p = NULL; + + p = &dc->hdr_sink_metadata; + ],[ + AC_DEFINE(HAVE_HDR_SINK_METADATA, 1, + [drm_connector_hdr_sink_metadata() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 63862e7be7ba8..5c13dbca1e6ca 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -111,6 +111,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS + AC_AMDGPU_DRM_CONNECTOR_HAVE_HDR_SINK_METADATA AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_KERNEL_WAIT From 63b2b63308e3c52dc0ef5a22b6134bbd29da21da Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Fri, 6 Mar 2020 11:44:27 +0800 Subject: [PATCH 0340/2653] drm/amdkcl: add protection for P010 pixel format Change-Id: Iebdf9ccdb876bba345ae49c06669518101fe35ee Signed-off-by: Yifan Zhang Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 ++ drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c | 2 ++ drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c | 2 ++ 4 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7b83d5f46fba1..9a00706008c73 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5881,9 +5881,11 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, case DRM_FORMAT_NV12: plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; break; +#ifdef DRM_FORMAT_P010 case DRM_FORMAT_P010: plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; break; +#endif case DRM_FORMAT_XRGB16161616F: case DRM_FORMAT_ARGB16161616F: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 17151a2af8df6..84989fc02b349 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -799,8 +799,10 @@ static int amdgpu_dm_plane_get_plane_formats(const struct drm_plane *plane, if (plane_cap && plane_cap->pixel_format_support.nv12) formats[num_formats++] = DRM_FORMAT_NV12; +#ifdef DRM_FORMAT_P010 if (plane_cap && plane_cap->pixel_format_support.p010) formats[num_formats++] = DRM_FORMAT_P010; +#endif if (plane_cap && plane_cap->pixel_format_support.fp16) { formats[num_formats++] = DRM_FORMAT_XRGB16161616F; formats[num_formats++] = DRM_FORMAT_ARGB16161616F; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c index 652c05c354947..59d8c3d28cfb4 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c @@ -514,7 +514,9 @@ static const struct dc_plane_cap plane_cap = { .argb8888 = true, .nv12 = true, .fp16 = true, +#ifdef DRM_FORMAT_P010 .p010 = false +#endif }, .max_upscale_factor = { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 918742a42ded6..a9af721d8e4e1 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -589,7 +589,9 @@ static const struct dc_plane_cap plane_cap = { .argb8888 = true, .nv12 = true, .fp16 = true, +#ifdef DRM_FORMAT_P010 .p010 = true +#endif }, .max_upscale_factor = { From b9034656d7e91e2010d98b8f7bee9a77eaa9bd60 Mon Sep 17 00:00:00 2001 From: Emily Deng Date: Thu, 2 Apr 2020 15:06:51 +0800 Subject: [PATCH 0341/2653] amd/amdkcl: Fix the assert report Signed-off-by: Emily Deng Reviewed-by: Flora Cui Change-Id: If2f264ccc7b2f0e73952fd88b45a23174d22ea61 Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c | 10 ++++------ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 12 ++++++------ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 10 +++++----- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++--- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 2 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +- 10 files changed, 32 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 241a619395fe4..3b162ca7b507d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -1637,7 +1637,7 @@ amdgpu_connector_add(struct amdgpu_device *adev, drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->connector_id == connector_id) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 4162e50094f5e..b22e1f5c2f93b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -647,7 +647,7 @@ void amdgpu_display_print_display_setup(struct drm_device *dev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif amdgpu_connector = to_amdgpu_connector(connector); DRM_INFO("Connector %d:\n", i); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c index cd4bf5460252b..54913ae5148b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c @@ -48,7 +48,7 @@ amdgpu_link_encoder_connector(struct drm_device *dev) /* walk the list and link encoders to connectors */ drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif amdgpu_connector = to_amdgpu_connector(connector); list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { @@ -78,8 +78,7 @@ void amdgpu_encoder_set_active_device(struct drm_encoder *encoder) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -109,9 +108,8 @@ amdgpu_get_connector_for_encoder(struct drm_encoder *encoder) #ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { - #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_encoder->active_device & amdgpu_connector->devices) { @@ -140,7 +138,7 @@ amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_encoder->devices & amdgpu_connector->devices) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 694c9a7faa9f7..889239b441dae 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -343,7 +343,7 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -407,7 +407,7 @@ static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -1265,7 +1265,7 @@ static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); @@ -1320,7 +1320,7 @@ static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); @@ -1398,7 +1398,7 @@ static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index cb3bdd0b2c1ec..73ebc038f0863 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -367,7 +367,7 @@ static void dce_v11_0_hpd_init(struct amdgpu_device *adev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -430,7 +430,7 @@ static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -1297,7 +1297,7 @@ static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); @@ -1352,7 +1352,7 @@ static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); @@ -1430,7 +1430,7 @@ static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 226a3c58fd16d..e1b58fb794549 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -322,7 +322,7 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -376,7 +376,7 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -1234,7 +1234,7 @@ static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder, drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); @@ -1287,7 +1287,7 @@ static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); @@ -1376,7 +1376,7 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); @@ -1790,7 +1790,7 @@ static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index dac59dc0e3695..f0a651f67c026 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -305,7 +305,7 @@ static void dce_v8_0_hpd_init(struct amdgpu_device *adev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -359,7 +359,7 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -1221,7 +1221,7 @@ static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder, drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); @@ -1292,7 +1292,7 @@ static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); @@ -1368,7 +1368,7 @@ static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9a00706008c73..88e8baaf53f31 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1083,7 +1083,7 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -2644,7 +2644,7 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -2826,7 +2826,7 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index 8ab218a0307d3..0289299c273f6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -624,7 +624,7 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) drm_connector_list_iter_begin(crtc->dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { #else - drm_for_each_connector(connector, crtc->dev) { + list_for_each_entry(connector, &(crtc->dev)->mode_config.connector_list, head) { #endif if (!connector->state || connector->state->crtc != crtc) continue; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index e30d3d0bcec34..7dbcb04298c1c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3866,7 +3866,7 @@ static int mst_topo_show(struct seq_file *m, void *unused) drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) continue; From 9e18c513e9dbc44ac468e091cf679c338510248a Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 22 Apr 2020 21:29:31 +0800 Subject: [PATCH 0342/2653] drm/amdkcl: add AC_AMDGPU_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE Change-Id: I66ddaedbb8f853bb9e40f10d96db003d0ccfedab Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ ...drm-hdmi-vendor-infoframe-from-display-mode.m4 | 15 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 20 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-hdmi-vendor-infoframe-from-display-mode.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 88e8baaf53f31..98d79e0e59be9 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6490,12 +6490,16 @@ static void fill_stream_properties_from_drm_display_mode( drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, mode_in); #endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ timing_out->vic = avi_frame.video_code; +#if defined(HAVE_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); if (err < 0) drm_warn_once(connector->dev, "Failed to setup vendor infoframe on connector %s: %zd\n", connector->name, err); +#else + drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, mode_in); +#endif timing_out->hdmi_vic = hv_frame.vic; } diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdmi-vendor-infoframe-from-display-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdmi-vendor-infoframe-from-display-mode.m4 new file mode 100644 index 0000000000000..c9f2c8a635e43 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-hdmi-vendor-infoframe-from-display-mode.m4 @@ -0,0 +1,15 @@ +dnl f1781e9bb2dd2305d8d7ffbede1888ae22119557 +dnl # drm/edid: Allow HDMI infoframe without VIC or S3D +dnl # +AC_DEFUN([AC_AMDGPU_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_hdmi_vendor_infoframe_from_display_mode(NULL, NULL, NULL); + ], [drm_hdmi_vendor_infoframe_from_display_mode], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE_P_P_P, 1, + [drm_hdmi_vendor_infoframe_from_display_mode() has p,p,p interface]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5c13dbca1e6ca..8079736aeeca8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -101,6 +101,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT AC_AMDGPU_STRSCPY AC_AMDGPU_DRM_DP_MST_TOPOLOGY + AC_AMDGPU_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS AC_AMDGPU_DRM_CONNECTOR_LIST_ITER_BEGIN AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS From 06bf2a9efbe1ed8731ab1de9eff951177691ea3c Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Wed, 6 May 2020 15:38:49 +0800 Subject: [PATCH 0343/2653] drm/amdkcl: Test whether drm_dp_send_real_edid_checksum is available introduced by commit: e11f5bd8228fc3760c221f940b9f6365dbf3e7ed drm: Add support for DP 1.4 Compliance edid corruption test Signed-off-by: Chengming Gui Reviewed-by: Flora Cui --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 5 ++++- .../dkms/m4/drm-dp-send-real-edid-checksum.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 21 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index fe100e4c98010..2f51524bbc796 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -994,7 +994,9 @@ enum dc_edid_status dm_helpers_read_local_edid( struct dc_sink *sink) { struct amdgpu_dm_connector *aconnector = link->priv; +#ifdef HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM struct drm_connector *connector = &aconnector->base; +#endif struct i2c_adapter *ddc; int retry = 3; enum dc_edid_status edid_status; @@ -1017,6 +1019,7 @@ enum dc_edid_status dm_helpers_read_local_edid( drm_edid = drm_edid_read_ddc(connector, ddc); drm_edid_connector_update(connector, drm_edid); +#ifdef HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM /* DP Compliance Test 4.2.2.6 */ if (link->aux_mode && connector->edid_corrupt) drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); @@ -1025,6 +1028,7 @@ enum dc_edid_status dm_helpers_read_local_edid( connector->edid_corrupt = false; return EDID_BAD_CHECKSUM; } +#endif if (!drm_edid) return EDID_NO_RESPONSE; @@ -1077,7 +1081,6 @@ enum dc_edid_status dm_helpers_read_local_edid( DP_TEST_RESPONSE, &test_response.raw, sizeof(test_response)); - } return edid_status; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 new file mode 100644 index 0000000000000..c15c7d3d88eb9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit e11f5bd8228fc3760c221f940b9f6365dbf3e7ed +dnl # drm: Add support for DP 1.4 Compliance edid corruption test +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_send_real_edid_checksum(NULL, 0); + ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c], [ + AC_DEFINE(HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM, 1, + [drm_dp_send_real_edid_checksum() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8079736aeeca8..b8dd883be44a3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -64,6 +64,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_CALC_PBN_MODE AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS + AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET From 18c9d2462a86f39be44f11293097d4141f203702 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 7 May 2020 13:59:32 +0800 Subject: [PATCH 0344/2653] drm/amdkcl: Check whether DRM_FORMAT_XRGB16161616F is defined DRM_FORMAT_XRGB16161616F introduced by commit: drm/fourcc: Add 64 bpp half float formats Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Change-Id: I44c6d15e6f91c01377f59520e1d8a360c9796a1a --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 98d79e0e59be9..15e8b03e0d4f0 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5894,6 +5894,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, case DRM_FORMAT_ABGR16161616F: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; break; +#ifdef DRM_FORMAT_XRGB16161616 case DRM_FORMAT_XRGB16161616: case DRM_FORMAT_ARGB16161616: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; @@ -5902,6 +5903,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, case DRM_FORMAT_ABGR16161616: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; break; +#endif default: drm_err(adev_to_drm(adev), "Unsupported screen format %p4cc\n", From 06accb5a1e0f830ee0fea35e59ecdf9869b819b1 Mon Sep 17 00:00:00 2001 From: Yang Xiong Date: Mon, 6 Jul 2020 17:20:41 +0800 Subject: [PATCH 0345/2653] drm/amdkcl: fix build error of drm_atomic_get_new_crtc_state undefined This kcl patch is caused by patch: drm/amd/display: clip plane rects in DM before passing into DC Change-Id: I0932a38c7d28db411b721fcb6303cefed51d8674 Signed-off-by: Yang Xiong Reviewed-by: Flora Cui Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 84989fc02b349..df633e228efc6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1254,9 +1254,9 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, if (!dm_plane_state->dc_state) return 0; - new_crtc_state = - drm_atomic_get_new_crtc_state(state, - new_plane_state->crtc); + new_crtc_state = kcl_drm_atomic_get_new_crtc_state_before_commit( + state, new_plane_state->crtc); + if (!new_crtc_state) return -EINVAL; From 5902e0bdc824a89c9fb78e8ac164dabf3e7059ff Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 21 Mar 2024 11:24:49 +0800 Subject: [PATCH 0346/2653] drm/amdkcl: test whether struct drm_connector_state has hdcp_content_type This patch is caused by 'drm/amdkcl: Enable HDCP Build by default' Signed-off-by: Yang Xiong Reviewed-by: Flora Cui Acked-by: Bhawanpreet Lakha Change-Id: I4c9d082592f89270bcdc292b07cf9bdbfeb9f51b Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 ++++++++++++- .../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 4 ++++ .../m4/drm-connector-state-hdcp-content-type.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 34 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdcp-content-type.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 15e8b03e0d4f0..3a4b66075976e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8633,7 +8633,11 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, drm_connector_attach_vrr_capable_property(&aconnector->base); if (adev->dm.hdcp_workqueue) +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE drm_connector_attach_content_protection_property(&aconnector->base, true); +#else + drm_connector_attach_content_protection_property(&aconnector->base); +#endif } } @@ -8982,6 +8986,7 @@ static bool is_content_protection_different(struct drm_crtc_state *new_crtc_stat new_crtc_state->active_changed, new_crtc_state->connectors_changed); +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE /* hdcp content type change */ if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { @@ -8989,6 +8994,7 @@ static bool is_content_protection_different(struct drm_crtc_state *new_crtc_stat pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); return true; } +#endif /* CP is being re enabled, ignore this */ if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && @@ -10385,7 +10391,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) if (aconnector->dc_link) hdcp_update_display( adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, - new_con_state->hdcp_content_type, enable_encryption); +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE + new_con_state->hdcp_content_type, +#else + DRM_MODE_HDCP_CONTENT_TYPE0, +#endif + enable_encryption); } } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index 4a973c85cb322..4276b99d24a2c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -369,6 +369,7 @@ static void event_property_update(struct work_struct *work) } if (hdcp_work->encryption_status[conn_index] != MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF) { +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE if (conn_state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE0 && hdcp_work->encryption_status[conn_index] <= @@ -383,6 +384,9 @@ static void event_property_update(struct work_struct *work) drm_hdcp_update_content_protection(connector, DRM_MODE_CONTENT_PROTECTION_ENABLED); } +#else + drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_ENABLED); +#endif } else { DRM_DEBUG_DRIVER("[HDCP_DM] DRM_MODE_CONTENT_PROTECTION_DESIRED\n"); drm_hdcp_update_content_protection(connector, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdcp-content-type.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdcp-content-type.m4 new file mode 100644 index 0000000000000..6d852b75d9e05 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdcp-content-type.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.3-rc1-377-g7672dbba85d3 +dnl # drm: Add Content protection type property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *state = NULL; + state->hdcp_content_type = 0; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE, 1, + [struct drm_connector_state has hdcp_content_type member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b8dd883be44a3..3e8922ecb0197 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -115,6 +115,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS AC_AMDGPU_DRM_CONNECTOR_HAVE_HDR_SINK_METADATA AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT + AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 0e7c707eb73e68469a8c978266f5561e31defc75 Mon Sep 17 00:00:00 2001 From: Yang Xiong Date: Fri, 4 Sep 2020 21:45:09 +0800 Subject: [PATCH 0347/2653] drm/amdkcl: drm_device to amdgpu_device by inline-f This patch is caused by the following patche: drm/amdgpu: drm_device to amdgpu_device by inline-f (v2) Change-Id: If95bc03e61ac1f9431be788b7c3ab623e87db5a8 Signed-off-by: Yang Xiong Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index bdfb1efe6f07a..3460759517197 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -838,7 +838,7 @@ static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) static void dm_dp_mst_register_connector(struct drm_connector *connector) { struct drm_device *dev = connector->dev; - struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_device *adev = drm_to_adev(dev); #ifndef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_modeset_lock_all(dev); From 44b0c01023c7b91a4affc426f1a2b99bac2c1632 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 12 May 2020 10:17:25 +0800 Subject: [PATCH 0348/2653] drm/amdkcl: test drm_crtc_funcs->gamma_set the history is: v4.11-rc5-1392-g6d124ff84533 drm: Add acquire ctx to ->gamma_set hook v4.7-rc1-260-g7ea772838782 drm/core: Change declaration for gamma_set. v4.5-rc3-706-g5488dc16fde7 drm: introduce pipe color correction propertie v2.6.35-260-g7203425a943e drm: expand gamma_set v2.6.28-8-gf453ba046074 DRM: add mode setting support It's a squash of drm/amdkcl: drop redundant test for drm_atomic_helper_legacy_gamma_set() Reviewed-by: Yang Xiong Signed-off-by: Flora Cui drm/amdkcl: [4.8] fix for drm_crtc_funcs->gamma_set Signed-off-by: Flora Cui Reviewed-by: Hawking Zhang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang drm/amdkcl: TODO drop dead code in crtc->gamma_set Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Signed-off-by: Flora Cui Acked-by: Rodrigo Siqueira Change-Id: I73df3ae59f010ff4431135aab5bd827af2f958d0 Signed-off-by: Yang Xiong --- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 21 ++++++++ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 21 ++++++++ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 21 ++++++++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 21 ++++++++ .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 48 +++++++++++++++++++ 5 files changed, 132 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 889239b441dae..cd1b543130719 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2528,6 +2528,12 @@ static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) } } +/* + * TODO: drm_fb_helper_setcmap() prev commit v4.12-rc7-1385-g964c60063bff + * ("drm/fb-helper: separate the fb_setcmap helper into atomic and legacy paths") + * don't work as expected. + */ +#if defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS) static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, uint32_t size, struct drm_modeset_acquire_ctx *ctx) @@ -2536,6 +2542,21 @@ static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, return 0; } +#elif defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS) +static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t size) +{ + dce_v10_0_crtc_load_lut(crtc); + + return 0; +} +#else +static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t start, uint32_t size) +{ + dce_v10_0_crtc_load_lut(crtc); +} +#endif static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 73ebc038f0863..0fb757dc31e1e 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2612,6 +2612,12 @@ static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) } } +/* + * TODO: drm_fb_helper_setcmap() prev commit v4.12-rc7-1385-g964c60063bff + * ("drm/fb-helper: separate the fb_setcmap helper into atomic and legacy paths") + * don't work as expected. + */ +#if defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS) static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, uint32_t size, struct drm_modeset_acquire_ctx *ctx) @@ -2620,6 +2626,21 @@ static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, return 0; } +#elif defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS) +static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t size) +{ + dce_v11_0_crtc_load_lut(crtc); + + return 0; +} +#else +static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t start, uint32_t size) +{ + dce_v11_0_crtc_load_lut(crtc); +} +#endif static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index e1b58fb794549..6b3cb2fa26af3 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2508,6 +2508,12 @@ static void dce_v6_0_cursor_reset(struct drm_crtc *crtc) } } +/* + * TODO: drm_fb_helper_setcmap() prev commit v4.12-rc7-1385-g964c60063bff + * ("drm/fb-helper: separate the fb_setcmap helper into atomic and legacy paths") + * don't work as expected. + */ +#if defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS) static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, uint32_t size, struct drm_modeset_acquire_ctx *ctx) @@ -2516,6 +2522,21 @@ static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, return 0; } +#elif defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS) +static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t size) +{ + dce_v6_0_crtc_load_lut(crtc); + + return 0; +} +#else +static void dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t start, uint32_t size) +{ + dce_v6_0_crtc_load_lut(crtc); +} +#endif static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index f0a651f67c026..ff7df7da69f70 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2446,6 +2446,12 @@ static void dce_v8_0_cursor_reset(struct drm_crtc *crtc) } } +/* + * TODO: drm_fb_helper_setcmap() prev commit v4.12-rc7-1385-g964c60063bff + * ("drm/fb-helper: separate the fb_setcmap helper into atomic and legacy paths") + * don't work as expected. + */ +#if defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS) static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, uint32_t size, struct drm_modeset_acquire_ctx *ctx) @@ -2454,6 +2460,21 @@ static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, return 0; } +#elif defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS) +static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t size) +{ + dce_v8_0_crtc_load_lut(crtc); + + return 0; +} +#else +static void dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t start, uint32_t size) +{ + dce_v8_0_crtc_load_lut(crtc); +} +#endif static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 211d8df287f57..ec6c920089ae1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -114,10 +114,58 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES], [ ]) ]) +dnl # +dnl # v4.11-rc5-1392-g6d124ff84533 drm: Add acquire ctx to ->gamma_set hook +dnl # int (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, +dnl # - uint32_t size); +dnl # + uint32_t size, +dnl # + struct drm_modeset_acquire_ctx *ctx); +dnl # v4.7-rc1-260-g7ea772838782 drm/core: Change declaration for gamma_set. +dnl # - void (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, +dnl # - uint32_t start, uint32_t size); +dnl # + int (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, +dnl # + uint32_t size); +dnl # v2.6.35-260-g7203425a943e drm: expand gamma_set +dnl # void (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, +dnl # - uint32_t size); +dnl # + uint32_t start, uint32_t size); +dnl # v2.6.28-8-gf453ba046074 DRM: add mode setting support +dnl # + void (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, +dnl # + uint32_t size); +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc *crtc = NULL; + int ret; + + ret = crtc->funcs->gamma_set(NULL, NULL, NULL, NULL, 0, NULL); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS, 1, + [crtc->funcs->gamma_set() wants 6 args]) + ], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc *crtc = NULL; + int ret; + + ret = crtc->funcs->gamma_set(NULL, NULL, NULL, NULL, 0); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS, 1, + [crtc->funcs->gamma_set() wants 5 args]) + ]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET ]) From 00e4baa97cc30c8bca9229752c54a36822bb6965 Mon Sep 17 00:00:00 2001 From: changzhu Date: Fri, 9 Aug 2019 11:06:58 +0800 Subject: [PATCH 0349/2653] drm/amdkcl: Test whether whether drm_dp_mst_connector_{early_unregister,late_register} are available Rebase 5.3 squash: * 600691173f87 drm/amd/autoconf: Test whether drm_dp_mst_connector_late_register is available * 8baafc6b96b7 drm/amd/autoconf: Test whether whether drm_dp_mst_connector_early_unregister is available Change-Id: I8d5367bf7adf47083cb0c050a9b01b1b5145614f Signed-off-by: Adam Yang Signed-off-by: changzhu Reviewed-by: Leo Li Reviewed-by: Slava Grigorev Signed-off-by: Jack Gui --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 3460759517197..e05d34fa8411a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -180,6 +180,7 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector) kfree(aconnector); } +#if defined(HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER) static int amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) { @@ -198,7 +199,7 @@ amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) return 0; } - +#endif /* HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER */ static inline void amdgpu_dm_mst_reset_mst_connector_setting(struct amdgpu_dm_connector *aconnector) @@ -210,6 +211,7 @@ amdgpu_dm_mst_reset_mst_connector_setting(struct amdgpu_dm_connector *aconnector aconnector->vc_full_pbn = 0; } +#if defined(HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER) static void amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) { @@ -243,6 +245,7 @@ amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) aconnector->mst_status = MST_STATUS_DEFAULT; drm_modeset_unlock(&root->mst_mgr.base.lock); } +#endif /* HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER */ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { #ifndef HAVE_DRM_DP_MST_DETECT_PORT_PPPP @@ -255,8 +258,12 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, .atomic_set_property = amdgpu_dm_connector_atomic_set_property, .atomic_get_property = amdgpu_dm_connector_atomic_get_property, +#if defined(HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER) .late_register = amdgpu_dm_mst_connector_late_register, +#endif /* HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER */ +#if defined(HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER) .early_unregister = amdgpu_dm_mst_connector_early_unregister, +#endif /* HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER */ }; bool needs_dsc_aux_workaround(struct dc_link *link) From 914d8bf6806785e7164f8ce32bb9e8c5eba99bf1 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 12 Oct 2020 15:02:05 +0800 Subject: [PATCH 0350/2653] drm/amdkcl: DCN301 backport for DC This is caused by "Add dcn3.01 support to DC" v5.9-rc2-568-g94e09bdc1c96 v1: enable DCN301 for DKMS build v2: guard the DSC related code under the macro CONFIG_DRM_AMD_DC_DSC_SUPPORT v3: fix the SSE build error for floating operation v4: remove the unnecessary depends for Kconfig Signed-off-by: Shiwu Zhang Reviewed-by: Yang Xiong --- .../display/dc/dio/dcn301/dcn301_dio_link_encoder.c | 2 ++ .../drm/amd/display/dc/hwss/dcn301/dcn301_init.c | 2 ++ .../display/dc/resource/dcn301/dcn301_resource.c | 13 ++++++++++++- 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c index 1b39a6e8a1ac5..100953da7bc48 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c @@ -48,7 +48,9 @@ (enc10->link_regs->index) static const struct link_encoder_funcs dcn301_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc3_hw_init, .setup = dcn10_link_encoder_setup, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c index 8d7ceb7b32b86..a9838babe0fa0 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c @@ -136,7 +136,9 @@ static const struct hwseq_private_funcs dcn301_private_funcs = { .hubp_pg_control = dcn20_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, +#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index 82a205a7c25c0..eeb3794dcd09f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -47,7 +47,9 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" +#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dce/dce_clock_source.h" @@ -489,6 +491,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -507,6 +510,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -648,7 +652,9 @@ static struct resource_caps res_cap_dcn301 = { .num_ddc = 4, .num_vmid = 16, .num_mpc_3dlut = 2, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -1052,10 +1058,12 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1222,6 +1230,7 @@ static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn301_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1236,7 +1245,7 @@ static struct display_stream_compressor *dcn301_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } - +#endif static void dcn301_destroy_resource_pool(struct resource_pool **pool) { @@ -1652,6 +1661,7 @@ static bool dcn301_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn301_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -1660,6 +1670,7 @@ static bool dcn301_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn301_dwbc_create(ctx, &pool->base)) { From 931dbb84d2b309c2c365ef26468f01893ceac2bb Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 19 Oct 2020 14:57:24 +0800 Subject: [PATCH 0351/2653] drm/amdkcl: DCN302 backport for DC This is caused by "Add support for DCN302 (v2)" v5.9-rc2-689-gbe0899b1f9f0 Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- .../drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c | 2 ++ .../drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h | 2 ++ .../gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c | 2 ++ .../amd/display/dc/resource/dcn302/dcn302_resource.c | 12 ++++++++++++ 4 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c index 0a6d58dd8f6da..40fad52521647 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c @@ -156,6 +156,7 @@ void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) { uint32_t power_gate = power_on ? 0 : 1; @@ -221,3 +222,4 @@ void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool po if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } +#endif diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h index 1e5126a0e695d..6317b4a0f363e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h @@ -30,6 +30,8 @@ void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on); void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on); +#endif #endif /* __DC_HWSS_DCN302_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c index 637f9514d37b2..1602be017597a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c @@ -37,5 +37,7 @@ void dcn302_hw_sequencer_construct(struct dc *dc) dc->hwseq->funcs.dpp_pg_control = dcn302_dpp_pg_control; dc->hwseq->funcs.hubp_pg_control = dcn302_hubp_pg_control; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dc->hwseq->funcs.dsc_pg_control = dcn302_dsc_pg_control; +#endif } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c index 3345068a878c1..1d14b741b7daf 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c @@ -40,7 +40,9 @@ #include "dcn30/dcn30_optc.h" #include "dcn30/dcn30_resource.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" +#endif #include "dcn20/dcn20_resource.h" #include "dml/dcn30/dcn30_fpu.h" @@ -128,7 +130,9 @@ static const struct resource_caps res_cap_dcn302 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 5, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -657,6 +661,7 @@ static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int n return &mpc30->base; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = { DSC_REG_LIST_DCN20(id) } @@ -688,6 +693,7 @@ static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ct dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif #define dwbc_regs_dcn3(id)\ [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } @@ -1003,10 +1009,12 @@ static void dcn302_resource_destruct(struct resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { if (pool->dscs[i] != NULL) dcn20_dsc_destroy(&pool->dscs[i]); } +#endif if (pool->mpc != NULL) { kfree(TO_DCN20_MPC(pool->mpc)); @@ -1141,7 +1149,9 @@ static struct resource_funcs dcn302_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -1429,6 +1439,7 @@ static bool dcn302_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { pool->dscs[i] = dcn302_dsc_create(ctx, i); if (pool->dscs[i] == NULL) { @@ -1437,6 +1448,7 @@ static bool dcn302_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn302_dwbc_create(ctx, pool)) { From ee5c90f3a7f76641099f42d1a49d8369fbc581de Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 16 Oct 2020 13:55:40 +0800 Subject: [PATCH 0352/2653] drm/amdkcl: update config checks with _is_kcl_macro_defined Signed-off-by: Flora Cui Reviewed-by: shiwu.zhang --- drivers/gpu/drm/amd/dkms/Makefile | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 25f48546e8d01..26cce7ae2a0cb 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -12,7 +12,7 @@ endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") -ifeq ($(shell grep "HAVE_DMA_RESV_SEQ" $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n"),n) +ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ),n) $(error dma_resv->seq is missing., exit...) endif @@ -156,10 +156,8 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 -ifeq ($(shell grep "HAVE_DRM_DRM_HDCP_H" $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n"),y) export CONFIG_DRM_AMD_DC_HDCP=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP -endif # Trying to enable DCN2/3 with core2 optimizations will result in # older versions of GCC hanging during building/installing. Check From 625f61b8924c6f06e3943b6723e57e2147b2208f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 2 Oct 2020 12:48:30 +0800 Subject: [PATCH 0353/2653] drm/amdkcl: drop test for DRIVER_ATOMIC DRIVER_ATOMIC is introduced in v3.18-1050-g88a48e297b3a Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 -- .../gpu/drm/amd/dkms/m4/drm-driver-feature.m4 | 22 ++----------------- 2 files changed, 2 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 488995f2d25c2..465f87006964d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2429,7 +2429,6 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, kcl_drm_vma_offset_manager_init(ddev->vma_offset_manager); -#ifdef HAVE_DRM_DRV_DRIVER_ATOMIC #ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; @@ -2440,7 +2439,6 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, /* support atomic early so the atomic debugfs stuff gets created */ if (supports_atomic) kms_driver.driver_features |= DRIVER_ATOMIC; -#endif #endif kcl_pci_configure_extended_tags(pdev); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 index 3afe53a169b8c..0970897b2338a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 @@ -1,28 +1,10 @@ dnl # -dnl # commit 88a48e297b3a3bac6022c03babfb038f1a886cea -dnl # drm: add atomic properties dnl # commit 0e2a933b02c972919f7478364177eb76cd4ae00d dnl # drm: Switch DRIVER_ flags to an enum dnl # AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - int _ = DRIVER_ATOMIC; - ], [ - AC_DEFINE(HAVE_DRM_DRV_DRIVER_ATOMIC, 1, [ - drm_driver_feature DRIVER_ATOMIC is available]) - ]) - ], [ - AC_DEFINE(HAVE_DRM_DRV_DRIVER_ATOMIC, 1, [ - drm_driver_feature DRIVER_ATOMIC is available]) - ]) - ]) - dnl # - dnl # commit: 060cebb20cdbcd3185d593e7194fa7a738201817 + dnl # commit: v5.1-rc5-1467-g060cebb20cdb dnl # drm: introduce a capability flag for syncobj timeline support dnl # AC_KERNEL_DO_BACKGROUND([ @@ -42,7 +24,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ ]) dnl # - dnl # commit: 1ff494813bafa127ecba1160262ba39b2fdde7ba + dnl # commit: v5.0-rc1-390-g1ff494813baf dnl # drm/irq: Ditch DRIVER_IRQ_SHARED dnl # AC_KERNEL_DO_BACKGROUND([ From 2400c29e0b6dfddceb722c8ea9c581d7caaa2143 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 3 Nov 2020 15:47:44 +0800 Subject: [PATCH 0354/2653] drm/amdkcl: use the kcl wrapper for get/set gem object This is caused by "Store tiling_flags in the framebuffer" v5.9-rc5-1363-gdd3cc8e45355 Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index b22e1f5c2f93b..6c7e9630cfeec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1406,7 +1406,7 @@ static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb return 0; } - rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); + rbo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&amdgpu_fb->base, 0)); r = amdgpu_bo_reserve(rbo, false); if (unlikely(r)) { From 1cd545d337e7082fec9f882e8dc95b6188add251 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 16 Nov 2020 21:08:17 +0800 Subject: [PATCH 0355/2653] drm/amdkcl: access drm_mm in ttm mem manager by memory type for centos7.3 and 7.4 backport This is caused by "drop priv pointer in memory manager" v5.8-rc2-636-g7ee6c95e05e9 v2: use the static inline function instead Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../amd/backport/include/kcl/kcl_amdgpu_ttm.h | 26 +++++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b12907b57f7c0..802029996d2ac 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -51,6 +51,7 @@ #include #include #include +#include "kcl/kcl_amdgpu_ttm.h" #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h new file mode 100644 index 0000000000000..1c4be1340422f --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDGPU_BACKPORT_KCL_AMDGPU_TTM_H +#define AMDGPU_BACKPORT_KCL_AMDGPU_TTM_H +#include +#include +#include +#include "amdgpu.h" +#include "amdgpu_ttm.h" + +#if !defined(HAVE_DRM_MM_PRINT) +extern struct drm_mm *kcl_ttm_range_res_manager_to_drm_mm(struct ttm_resource_manager *man); + +static inline struct drm_mm *kcl_ttm_get_drm_mm_by_mem_type(struct amdgpu_device *adev, unsigned char ttm_pl) +{ + if (ttm_pl == TTM_PL_TT) { + return &(adev->mman.gtt_mgr.mm); + } else if (ttm_pl == TTM_PL_VRAM) { + return &(adev->mman.vram_mgr.mm); + } else { + struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl); + return kcl_ttm_range_res_manager_to_drm_mm(man); + } +} +#endif + +#endif /* AMDGPU_BACKPORT_KCL_AMDGPU_TTM_H */ From d5933f2a4f05f9a1dfd655dbfbb1c2f62aa65b02 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 24 Nov 2020 16:58:39 +0800 Subject: [PATCH 0356/2653] drm/amdkcl: fake the func of timestamping calculation This is caused by "Always get CRTC updated constant values inside commit tail" v5.9-rc5-1644-gea29955035a6 This is a squash of: drm/amdkcl: call legacy update only for backport This is caused by "Remove the timestamping constant update from drm_atomic_helper_update_legacy_modeset_state()" v5.9-rc5-1595-ge1ad957d45f7 Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- .../drm/amd/amdkcl/kcl_drm_atomic_helper.c | 28 +++++++++++++++++++ ...omic_helper_calc_timestamping_constants.m4 | 13 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_atomic_helper.h | 4 +++ 4 files changed, 46 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c index 4ef77c1846213..3e2cf46b8526c 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -27,6 +27,7 @@ */ #include #include +#include #ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, @@ -59,3 +60,30 @@ __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, } EXPORT_SYMBOL(__drm_atomic_helper_crtc_reset); #endif + +#ifndef HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS +/* + * This implementation is duplicated from v5.9-rc5-1595-ge1ad957d45f7 + * "Extract drm_atomic_helper_calc_timestamping_constants()" + * + */ +void drm_atomic_helper_calc_timestamping_constants(struct drm_atomic_state *state) +{ + struct drm_device *dev = state->dev; + struct drm_crtc_state *new_crtc_state; + struct drm_crtc *crtc; + int i; + +#if !defined(for_each_new_crtc_in_state) + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + new_crtc_state = crtc->state; +#else + for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { +#endif + if (new_crtc_state->enable) + drm_calc_timestamping_constants(crtc, + &new_crtc_state->adjusted_mode); + } +} +EXPORT_SYMBOL(drm_atomic_helper_calc_timestamping_constants); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 new file mode 100644 index 0000000000000..79ab39b5802f3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # v5.9-rc5-1595-ge1ad957d45f7 +dnl # Extract drm_atomic_helper_calc_timestamping_constants() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_atomic_helper_calc_timestamping_constants], + [drivers/gpu/drm/drm_atomic_helper.c], [ + AC_DEFINE(HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS, 1, + [drm_atomic_helper_calc_timestamping_constants() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3e8922ecb0197..478c096290267 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -82,6 +82,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU___PRINT_ARRAY AC_AMDGPU_ACPI_PUT_TABLE + AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS AC_AMDGPU_DRM_DEV_DBG AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM diff --git a/include/kcl/kcl_drm_atomic_helper.h b/include/kcl/kcl_drm_atomic_helper.h index cb5c49c24cb94..208a5e9edf330 100644 --- a/include/kcl/kcl_drm_atomic_helper.h +++ b/include/kcl/kcl_drm_atomic_helper.h @@ -49,4 +49,8 @@ void __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state); #endif +#ifndef HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS +void drm_atomic_helper_calc_timestamping_constants(struct drm_atomic_state *state); +#endif + #endif From ece45c2139c7c9fd91513a884819e0ab76a7aa4f Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 17 Nov 2020 16:48:12 +0800 Subject: [PATCH 0357/2653] drm/amdkcl: disable modifier support for DRM before 5.0 This is caused by "Add formats for DCC with 2/3 planes" and "Expose modifiers" v5.9-rc5-1367-g564b9f4c7cf9 and v5.9-rc5-1368-g86ce3ed796ff This is a squash of: drm/amdkcl: fix license for kcl drm part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling drm/amdkcl: guard the modifier code for backport This is caused by "Store gem objects for planes 1-3" v5.9-rc5-1565-gbf01c77ad320 Signed-off-by: Shiwu Zhang Reviewed-by: Bhawanpreet Lakha drm/amdkcl: update the AMD modifer macros This is caused by "Fix modifier field mask for AMD modifiers", "add table describing AMD modifiers bit layout", "fix AMD modifiers PACKERS field doc" v5.9-rc5-1563-g80363c69ca44, v5.9-rc5-1564-gbac8bece9c55 and v5.9-rc5-1594-g11e500d2892a Signed-off-by: Shiwu Zhang drm/amdkcl: fix the config.h mismatch for autotest and regenerate the config.h Signed-off-by: Shiwu Zhang drm/amdkcl: disable modifier feature if Floating point 64bpp RGB format is not defined This is to avoid warning printing during modprobe on the OS like rhel 7.9 Signed-off-by: Shiwu Zhang Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui Reviewed-by: Bhawanpreet Lakha Signed-off-by: Ma Jun Change-Id: If9ccae068c5b8cf3f475fa8c178b5d3135a9b84a --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 + drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 + .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 10 + .../gpu/drm/amd/dkms/m4/drm_format_info.m4 | 20 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 13 +- include/kcl/kcl_drm_fourcc.h | 217 ++++++++++++++++++ 7 files changed, 263 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 create mode 100644 include/kcl/kcl_drm_fourcc.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 6c7e9630cfeec..7d73806895a04 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -980,6 +980,7 @@ static int convert_tiling_flags_to_modifier_gfx12(struct amdgpu_framebuffer *afb return 0; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) { struct amdgpu_device *adev = drm_to_adev(afb->base.dev); @@ -1173,6 +1174,7 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) afb->base.flags |= DRM_MODE_FB_MODIFIERS; return 0; } +#endif /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */ static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb) @@ -1478,6 +1480,7 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, * This needs to happen before modifier conversion as that might change * the number of planes. */ +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED for (i = 1; i < rfb->base.format->num_planes; ++i) { if (mode_cmd->handles[i] != mode_cmd->handles[0]) { drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n", @@ -1486,12 +1489,14 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, return ret; } } +#endif ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface, &rfb->gfx12_dcc); if (ret) return ret; +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) { drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI, "GFX9+ requires FB check based on format modifier\n"); @@ -1522,6 +1527,7 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, drm_gem_object_get(rfb->base.obj[0]); rfb->base.obj[i] = rfb->base.obj[0]; } +#endif return 0; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 802029996d2ac..08d61f40a3eb4 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -53,6 +53,7 @@ #include #include "kcl/kcl_amdgpu_ttm.h" #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3a4b66075976e..266d344a8af52 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3630,7 +3630,9 @@ const struct amdgpu_ip_block_version dm_ip_block = { static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { .fb_create = amdgpu_display_user_framebuffer_create, +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED .get_format_info = amdgpu_dm_plane_get_format_info, +#endif .atomic_check = amdgpu_dm_atomic_check, .atomic_commit = drm_atomic_helper_commit, }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index df633e228efc6..53ca2c3097580 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -164,10 +164,12 @@ static void amdgpu_dm_plane_add_modifier(uint64_t **mods, uint64_t *size, uint64 *size += 1; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static bool amdgpu_dm_plane_modifier_has_dcc(uint64_t modifier) { return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); } +#endif static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier) { @@ -307,6 +309,7 @@ static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev, return 0; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev, const struct amdgpu_framebuffer *afb, const enum surface_pixel_format format, @@ -357,6 +360,7 @@ static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdg return ret; } +#endif static int amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(struct amdgpu_device *adev, const struct amdgpu_framebuffer *afb, @@ -922,12 +926,14 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, if (ret) return ret; } else if (adev->family >= AMDGPU_FAMILY_AI) { +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED ret = amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(adev, afb, format, rotation, plane_size, tiling_info, dcc, address); if (ret) return ret; +#endif } else { amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags); } @@ -1809,7 +1815,9 @@ static const struct drm_plane_funcs dm_plane_funcs = { .reset = amdgpu_dm_plane_drm_plane_reset, .atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state, .atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state, +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED .format_mod_supported = amdgpu_dm_plane_format_mod_supported, +#endif #ifdef AMD_PRIVATE_COLOR .atomic_set_property = dm_atomic_plane_set_property, .atomic_get_property = dm_atomic_plane_get_property, @@ -1831,9 +1839,11 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, num_formats = amdgpu_dm_plane_get_plane_formats(plane, plane_cap, formats, ARRAY_SIZE(formats)); +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED res = amdgpu_dm_plane_get_plane_modifiers(dm->adev, plane->type, &modifiers); if (res) return res; +#endif if (modifiers == NULL) adev_to_drm(dm->adev)->mode_config.fb_modifiers_not_supported = true; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 new file mode 100644 index 0000000000000..95a45563d402e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # v5.9-rc5-1367-g564b9f4c7cf9 +dnl # drm/amd/display: Add formats for DCC with 2/3 planes +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FORMAT_INFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_format_info format = { + .format = DRM_FORMAT_XRGB16161616F, + .block_w = {0}, + .block_h = {0}, + }; + ], [ + AC_DEFINE(HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED, 1, + [drm_format_info.block_w and rm_format_info.block_h is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 478c096290267..0f2f900a6abc6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -77,12 +77,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_DEVICE AC_AMDGPU_DRM_DRIVER_FEATURE AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET - AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION - AC_AMDGPU_MEM_ENCRYPT_ACTIVE - AC_AMDGPU_JIFFIES64_TO_MSECS - AC_AMDGPU___PRINT_ARRAY - AC_AMDGPU_ACPI_PUT_TABLE - AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS AC_AMDGPU_DRM_DEV_DBG AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM @@ -117,6 +111,13 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_HAVE_HDR_SINK_METADATA AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE + AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION + AC_AMDGPU_MEM_ENCRYPT_ACTIVE + AC_AMDGPU_JIFFIES64_TO_MSECS + AC_AMDGPU___PRINT_ARRAY + AC_AMDGPU_ACPI_PUT_TABLE + AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS + AC_AMDGPU_DRM_FORMAT_INFO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h new file mode 100644 index 0000000000000..25cf40f897b23 --- /dev/null +++ b/include/kcl/kcl_drm_fourcc.h @@ -0,0 +1,217 @@ +/* + * Copyright 2011 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef KCL_KCL_DRM_FOURCC_H +#define KCL_KCL_DRM_FOURCC_H + +#include + +/* Copied from include/uapi/drm/drm_fourcc.h */ +/* + * Linear Layout + * + * Just plain linear layout. Note that this is different from no specifying any + * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), + * which tells the driver to also take driver-internal information into account + * and so might actually result in a tiled framebuffer. + */ +#if !defined(DRM_FORMAT_MOD_VENDOR_NONE) +#define DRM_FORMAT_MOD_VENDOR_NONE 0 +#endif + +#if !defined(DRM_FORMAT_MOD_LINEAR) +#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) +#endif + +#if !defined(DRM_FORMAT_RESERVED) +#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) +#endif +/* + * * Invalid Modifier + * * + * * This modifier can be used as a sentinel to terminate the format modifiers + * * list, or to initialize a variable with an invalid modifier. It might also be + * * used to report an error back to userspace for certain APIs. + * */ +#if !defined(DRM_FORMAT_MOD_INVALID) +#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) +#endif + +/* + * AMD modifiers + * + * Memory layout: + * + * without DCC: + * - main surface + * + * with DCC & without DCC_RETILE: + * - main surface in plane 0 + * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) + * + * with DCC & DCC_RETILE: + * - main surface in plane 0 + * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) + * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) + * + * For multi-plane formats the above surfaces get merged into one plane for + * each format plane, based on the required alignment only. + * + * Bits Parameter Notes + * ----- ------------------------ --------------------------------------------- + * + * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* + * 12:8 TILE Values are AMD_FMT_MOD_TILE__* + * 13 DCC + * 14 DCC_RETILE + * 15 DCC_PIPE_ALIGN + * 16 DCC_INDEPENDENT_64B + * 17 DCC_INDEPENDENT_128B + * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* + * 20 DCC_CONSTANT_ENCODE + * 23:21 PIPE_XOR_BITS Only for some chips + * 26:24 BANK_XOR_BITS Only for some chips + * 29:27 PACKERS Only for some chips + * 32:30 RB Only for some chips + * 35:33 PIPE Only for some chips + * 55:36 - Reserved for future use, must be zero + */ + +#if !defined(AMD_FMT_MOD) +#define AMD_FMT_MOD fourcc_mod_code(AMD, 0) + +#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) + +/* Reserve 0 for GFX8 and older */ +#define AMD_FMT_MOD_TILE_VER_GFX9 1 +#define AMD_FMT_MOD_TILE_VER_GFX10 2 +#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 + +/* + * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical + * version. + */ +#define AMD_FMT_MOD_TILE_GFX9_64K_S 9 + +/* + * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has + * GFX9 as canonical version. + */ +#define AMD_FMT_MOD_TILE_GFX9_64K_D 10 +#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 +#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 +#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 + +#define AMD_FMT_MOD_DCC_BLOCK_64B 0 +#define AMD_FMT_MOD_DCC_BLOCK_128B 1 +#define AMD_FMT_MOD_DCC_BLOCK_256B 2 + +#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 +#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF +#define AMD_FMT_MOD_TILE_SHIFT 8 +#define AMD_FMT_MOD_TILE_MASK 0x1F + +/* Whether DCC compression is enabled. */ +#define AMD_FMT_MOD_DCC_SHIFT 13 +#define AMD_FMT_MOD_DCC_MASK 0x1 + +/* + * Whether to include two DCC surfaces, one which is rb & pipe aligned, and + * one which is not-aligned. + */ +#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 +#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 + +/* Only set if DCC_RETILE = false */ +#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 +#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 + +#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 +#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 +#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 +#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 + +/* + * DCC supports embedding some clear colors directly in the DCC surface. + * However, on older GPUs the rendering HW ignores the embedded clear color + * and prefers the driver provided color. This necessitates doing a fastclear + * eliminate operation before a process transfers control. + * + * If this bit is set that means the fastclear eliminate is not needed for these + * embeddable colors. + */ +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 + +/* + * The below fields are for accounting for per GPU differences. These are only + * relevant for GFX9 and later and if the tile field is *_X/_T. + * + * PIPE_XOR_BITS = always needed + * BANK_XOR_BITS = only for TILE_VER_GFX9 + * PACKERS = only for TILE_VER_GFX10_RBPLUS + * RB = only for TILE_VER_GFX9 & DCC + * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) + */ +#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 +#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 +#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 +#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 +#define AMD_FMT_MOD_PACKERS_SHIFT 27 +#define AMD_FMT_MOD_PACKERS_MASK 0x7 +#define AMD_FMT_MOD_RB_SHIFT 30 +#define AMD_FMT_MOD_RB_MASK 0x7 +#define AMD_FMT_MOD_PIPE_SHIFT 33 +#define AMD_FMT_MOD_PIPE_MASK 0x7 + +#define AMD_FMT_MOD_SET(field, value) \ + ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) +#define AMD_FMT_MOD_GET(field, value) \ + (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) +#define AMD_FMT_MOD_CLEAR(field) \ + (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) +#endif + +/* + * 2 plane YCbCr MSB aligned + * index 0 = Y plane, [15:0] Y:x [10:6] little endian + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian + */ +#ifndef DRM_FORMAT_P010 +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ +#endif +/* + * Floating point 64bpp RGB + * IEEE 754-2008 binary16 half-precision float + * [15:0] sign:exponent:mantissa 1:5:10 + */ +#ifndef DRM_FORMAT_XRGB16161616F +#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ +#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ + +#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ +#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ +#endif + +#endif /* KCL_KCL_DRM_FOURCC_H */ From 7ab75ac219a61957aca167ed3e3629f969b0cdaf Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 15 Dec 2020 17:30:45 +0800 Subject: [PATCH 0358/2653] drm/amdkcl: dummy the amdgpu dm tracepoint for backport This is caused by "Add tracepoint for amdgpu_dm" v5.9-rc5-1254-gb694b19508a3 v2: more autotests to make the new tracepoints valid on the tier1 OS of rhel7.9 and above v3: fix indent and use the autotests already defined before Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- .../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 88 ++++++++++++++++--- .../gpu/drm/amd/dkms/m4/drm-atomic-state.m4 | 18 ++++ .../drm/amd/dkms/m4/drm-connector-state.m4 | 26 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 + include/kcl/backport/kcl_dm_tracepoint.h | 21 +++++ 5 files changed, 143 insertions(+), 12 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-state.m4 create mode 100644 include/kcl/backport/kcl_dm_tracepoint.h diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h index aa56fd6d56c34..045283ad899b4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h @@ -41,6 +41,7 @@ #include "dc/inc/hw/optc.h" #include "dc/inc/core_types.h" +#include DECLARE_EVENT_CLASS(amdgpu_dc_reg_template, TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value), @@ -113,13 +114,19 @@ TRACE_EVENT(amdgpu_dm_connector_atomic_check, __field(uint32_t, crtc_id) __field(uint32_t, best_encoder_id) __field(enum drm_link_status, link_status) +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE __field(bool, self_refresh_aware) +#endif __field(enum hdmi_picture_aspect, picture_aspect_ratio) __field(unsigned int, content_type) +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE __field(unsigned int, hdcp_content_type) +#endif __field(unsigned int, content_protection) __field(unsigned int, scaling_mode) +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE __field(u32, colorspace) +#endif __field(u8, max_requested_bpc) __field(u8, max_bpc) ), @@ -133,28 +140,52 @@ TRACE_EVENT(amdgpu_dm_connector_atomic_check, __entry->best_encoder_id = state->best_encoder ? state->best_encoder->base.id : 0; __entry->link_status = state->link_status; +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE __entry->self_refresh_aware = state->self_refresh_aware; +#endif __entry->picture_aspect_ratio = state->picture_aspect_ratio; __entry->content_type = state->content_type; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE __entry->hdcp_content_type = state->hdcp_content_type; +#endif __entry->content_protection = state->content_protection; __entry->scaling_mode = state->scaling_mode; +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE __entry->colorspace = state->colorspace; +#endif __entry->max_requested_bpc = state->max_requested_bpc; __entry->max_bpc = state->max_bpc; ), TP_printk("conn_id=%u conn_state=%p state=%p commit=%p crtc_id=%u " - "best_encoder_id=%u link_status=%d self_refresh_aware=%d " + "best_encoder_id=%u link_status=%d " +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE + "self_refresh_aware=%d " +#endif "picture_aspect_ratio=%d content_type=%u " - "hdcp_content_type=%u content_protection=%u scaling_mode=%u " - "colorspace=%u max_requested_bpc=%u max_bpc=%u", +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE + "hdcp_content_type=%u " +#endif + "content_protection=%u scaling_mode=%u " +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE + "colorspace=%u " +#endif + "max_requested_bpc=%u max_bpc=%u", __entry->conn_id, __entry->conn_state, __entry->state, __entry->commit, __entry->crtc_id, __entry->best_encoder_id, - __entry->link_status, __entry->self_refresh_aware, + __entry->link_status, +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE + __entry->self_refresh_aware, +#endif __entry->picture_aspect_ratio, __entry->content_type, - __entry->hdcp_content_type, __entry->content_protection, - __entry->scaling_mode, __entry->colorspace, +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE + __entry->hdcp_content_type, +#endif + __entry->content_protection, + __entry->scaling_mode, +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE + __entry->colorspace, +#endif __entry->max_requested_bpc, __entry->max_bpc) ); @@ -176,9 +207,13 @@ TRACE_EVENT(amdgpu_dm_crtc_atomic_check, __field(bool, zpos_changed) __field(bool, color_mgmt_changed) __field(bool, no_vblank) +#ifdef HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP __field(bool, async_flip) +#endif __field(bool, vrr_enabled) +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE __field(bool, self_refresh_active) +#endif __field(u32, plane_mask) __field(u32, connector_mask) __field(u32, encoder_mask) @@ -198,9 +233,13 @@ TRACE_EVENT(amdgpu_dm_crtc_atomic_check, __entry->zpos_changed = state->zpos_changed; __entry->color_mgmt_changed = state->color_mgmt_changed; __entry->no_vblank = state->no_vblank; +#ifdef HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP __entry->async_flip = state->async_flip; +#endif __entry->vrr_enabled = state->vrr_enabled; +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE __entry->self_refresh_active = state->self_refresh_active; +#endif __entry->plane_mask = state->plane_mask; __entry->connector_mask = state->connector_mask; __entry->encoder_mask = state->encoder_mask; @@ -208,16 +247,29 @@ TRACE_EVENT(amdgpu_dm_crtc_atomic_check, TP_printk("crtc_id=%u crtc_state=%p state=%p commit=%p changed(" "planes=%d mode=%d active=%d conn=%d zpos=%d color_mgmt=%d) " - "state(enable=%d active=%d async_flip=%d vrr_enabled=%d " - "self_refresh_active=%d no_vblank=%d) mask(plane=%x conn=%x " + "state(enable=%d active=%d " +#ifdef HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP + "async_flip=%d " +#endif + "vrr_enabled=%d " +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE + "self_refresh_active=%d " +#endif + "no_vblank=%d) mask(plane=%x conn=%x " "enc=%x)", __entry->crtc_id, __entry->crtc_state, __entry->state, __entry->commit, __entry->planes_changed, __entry->mode_changed, __entry->active_changed, __entry->connectors_changed, __entry->zpos_changed, __entry->color_mgmt_changed, __entry->enable, __entry->active, - __entry->async_flip, __entry->vrr_enabled, - __entry->self_refresh_active, __entry->no_vblank, +#ifdef HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP + __entry->async_flip, +#endif + __entry->vrr_enabled, +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE + __entry->self_refresh_active, +#endif + __entry->no_vblank, __entry->plane_mask, __entry->connector_mask, __entry->encoder_mask) ); @@ -323,7 +375,9 @@ TRACE_EVENT(amdgpu_dm_atomic_state_template, __field(bool, allow_modeset) __field(bool, legacy_cursor_update) __field(bool, async_update) +#ifdef HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED __field(bool, duplicated) +#endif __field(int, num_connector) __field(int, num_private_objs) ), @@ -333,16 +387,26 @@ TRACE_EVENT(amdgpu_dm_atomic_state_template, __entry->allow_modeset = state->allow_modeset; __entry->legacy_cursor_update = state->legacy_cursor_update; __entry->async_update = state->async_update; +#ifdef HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED __entry->duplicated = state->duplicated; +#endif __entry->num_connector = state->num_connector; __entry->num_private_objs = state->num_private_objs; ), TP_printk("state=%p allow_modeset=%d legacy_cursor_update=%d " - "async_update=%d duplicated=%d num_connector=%d " + "async_update=%d " +#ifdef HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED + "duplicated=%d " +#endif + "num_connector=%d " "num_private_objs=%d", __entry->state, __entry->allow_modeset, __entry->legacy_cursor_update, - __entry->async_update, __entry->duplicated, __entry->num_connector, + __entry->async_update, +#ifdef HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED + __entry->duplicated, +#endif + __entry->num_connector, __entry->num_private_objs) ); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 new file mode 100644 index 0000000000000..cd7227d5c12eb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v5.0-rc1-415-g022debad063e +dnl # drm/atomic: Add drm_atomic_state->duplicated +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_atomic_state *state = NULL; + state->duplicated = 0; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED, 1, + [struct drm_connector_state->duplicated is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state.m4 new file mode 100644 index 0000000000000..69753da371891 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state.m4 @@ -0,0 +1,26 @@ +dnl # +dnl # v4.20-rc3-425-g1398958cfd8d +dnl # drm: Add vrr_enabled property to drm CRTC +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *state = NULL; + state->colorspace = 0; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE, 1, + [struct drm_connector_state->colorspace is available]) + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *state = NULL; + state->self_refresh_aware = 0; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE, 1, + [struct drm_connector_state->self_refresh_aware is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0f2f900a6abc6..fb0d821b0cd44 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -118,6 +118,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ACPI_PUT_TABLE AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS AC_AMDGPU_DRM_FORMAT_INFO + AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE + AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_dm_tracepoint.h b/include/kcl/backport/kcl_dm_tracepoint.h new file mode 100644 index 0000000000000..7d0e772c51ece --- /dev/null +++ b/include/kcl/backport/kcl_dm_tracepoint.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef KCL_BACKPORT_KCL_DM_TRACEPOINT_H +#define KCL_BACKPORT_KCL_DM_TRACEPOINT_H + +#ifndef DECLARE_EVENT_NOP +#define DECLARE_EVENT_NOP(name, proto, args) \ + static inline void trace_##name(proto) \ + { } \ + static inline bool trace_##name##_enabled(void) \ + { \ + return false; \ + } + +#define TRACE_EVENT_NOP(name, proto, args, struct, assign, print) \ + DECLARE_EVENT_NOP(name, PARAMS(proto), PARAMS(args)) + +#define DEFINE_EVENT_NOP(template, name, proto, args) \ + DECLARE_EVENT_NOP(name, PARAMS(proto), PARAMS(args)) +#endif + +#endif /* KCL_BACKPORT_KCL_DM_TRACEPOINT_H */ From 258872b6e2cb1d9d2f40afb1ddb7bd9e57b6e35e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 8 Jan 2020 17:12:58 +0800 Subject: [PATCH 0359/2653] drm/amdkcl: enable CONFIG_DRM_TTM_DMA_PAGE_POOL Signed-off-by: Flora Cui Reviewed-by: Kevin Wang --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 26cce7ae2a0cb..cfe73b92bcad9 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -141,6 +141,7 @@ LINUXINCLUDE := \ export CONFIG_HSA_AMD=y export CONFIG_DRM_TTM=m +export CONFIG_DRM_TTM_DMA_PAGE_POOL=y export CONFIG_DRM_AMDGPU=m export CONFIG_DRM_SCHED=m export CONFIG_DRM_AMDGPU_CIK=y @@ -150,6 +151,7 @@ export CONFIG_DRM_AMD_DC=y export CONFIG_DRM_AMD_DC_DCN1_0=y subdir-ccflags-y += -DCONFIG_HSA_AMD +subdir-ccflags-y += -DCONFIG_DRM_TTM_DMA_PAGE_POOL subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR From f5c712aa4dccd36108dac83021d5def6d49186ec Mon Sep 17 00:00:00 2001 From: "Le.Ma" Date: Mon, 18 Feb 2019 10:40:35 +0800 Subject: [PATCH 0360/2653] drm/amdkcl: check whether u64_to_user_ptr is available v1: drm/amdkcl: [4.7] kcl for u64_to_user_ptr() v2: drm/amdkcl: drop kcl_u64_to_user_ptr Signed-off-by: Le.Ma Reviewed-by: Junwei Zhang Reviewed-by: Evan Quan Signed-off-by: Flora Cui Acked-by: Feifei Xu / Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_kernel.h | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 include/kcl/kcl_kernel.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 08d61f40a3eb4..a76e1bc850477 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h new file mode 100644 index 0000000000000..e1a0dfe11a386 --- /dev/null +++ b/include/kcl/kcl_kernel.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_KERNEL_H +#define AMDKCL_KERNEL_H + +#include + +/* Copied from include/linux/kernel.h */ +#ifndef u64_to_user_ptr +#define u64_to_user_ptr(x) ( \ +{ \ + typecheck(u64, x); \ + (void __user *)(uintptr_t)x; \ +} \ +) +#endif + +#endif /* AMDKCL_KERNEL_H */ From 5aa91dfd2e09a0279ac0788391ca534bbb44ac51 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Tue, 23 Jan 2018 15:33:23 +0800 Subject: [PATCH 0361/2653] drm/amdkcl: check whether __GFP_RETRY_MAYFAIL is available kernel 4.13: rename __GFP_REPEAT to __GFP_RETRY_MAYFAIL Reviewed-by: Le Ma Reviewed-by: Roger He Signed-Off-by: Kevin Wang Signed-off-by: Jack Gui Signed-off-by: Flora Cui --- drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_kernel.h | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index acec38aa8d159..04bfefdaf001c 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -4,6 +4,7 @@ #include #include +#include #include #include #include diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index e1a0dfe11a386..6624b9a50f79a 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -3,6 +3,7 @@ #define AMDKCL_KERNEL_H #include +#include /* Copied from include/linux/kernel.h */ #ifndef u64_to_user_ptr @@ -14,4 +15,8 @@ ) #endif +#ifndef __GFP_RETRY_MAYFAIL +#define __GFP_RETRY_MAYFAIL __GFP_REPEAT +#endif + #endif /* AMDKCL_KERNEL_H */ From e55267f5b2ce67818160fe12d76e98a2f406945f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 12 Mar 2020 21:00:19 +0800 Subject: [PATCH 0362/2653] drm/amdkcl: add macro ALIGN_DOWN Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Yifan Zhang --- include/kcl/kcl_kernel.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index 6624b9a50f79a..f33fc452d8243 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -19,4 +19,8 @@ #define __GFP_RETRY_MAYFAIL __GFP_REPEAT #endif +#ifndef ALIGN_DOWN +#define ALIGN_DOWN(x, a) __ALIGN_KERNEL((x) - ((a) - 1), (a)) +#endif /* ALIGN_DOWN */ + #endif /* AMDKCL_KERNEL_H */ From 27be3a88df202af3be3465dd736eeca60d27cb8a Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 18 Mar 2020 17:09:57 +0800 Subject: [PATCH 0363/2653] drm/amdkcl: add kcl_compiler_attributes.h Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/scheduler/backport/backport.h | 2 ++ drivers/gpu/drm/ttm/backport/backport.h | 2 ++ include/kcl/kcl_compiler_attributes.h | 13 +++++++++++++ 4 files changed, 18 insertions(+) create mode 100644 include/kcl/kcl_compiler_attributes.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a76e1bc850477..c2baa09d32bc3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 46537c0094114..690cfe2fbe358 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -3,8 +3,10 @@ #define AMDSCHED_BACKPORT_H #include +#include #include #include #include #include + #endif diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 04bfefdaf001c..a5c1c3c403ad7 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -5,10 +5,12 @@ #include #include #include +#include #include #include #include #include #include #include + #endif diff --git a/include/kcl/kcl_compiler_attributes.h b/include/kcl/kcl_compiler_attributes.h new file mode 100644 index 0000000000000..34d035352059c --- /dev/null +++ b/include/kcl/kcl_compiler_attributes.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_COMPILER_ATTRIBUTES_H +#define AMDKCL_COMPILER_ATTRIBUTES_H + +#ifdef HAVE_LINUX_COMPILER_ATTRIBUTES_H +#include +#endif + +#ifndef fallthrough +#define fallthrough do {} while (0) /* fallthrough */ +#endif + +#endif /* AMDKCL_COMPILER_ATTRIBUTES_H */ From f9520c7680de18629b9899f3047929a2969e2ed8 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 10 Sep 2020 13:32:43 +0800 Subject: [PATCH 0364/2653] drm/amdkcl: fake dma_alloc_attrs api for dma_attrs change Signed-off-by: Flora Cui Change-Id: If4dffb0b4f0d2a6d9a7067ab5e15c3d42e31e198 --- drivers/gpu/drm/ttm/ttm_pool.c | 4 ++-- include/kcl/kcl_dma_mapping.h | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c index baf27c70a4193..6c6cc6a43815d 100644 --- a/drivers/gpu/drm/ttm/ttm_pool.c +++ b/drivers/gpu/drm/ttm/ttm_pool.c @@ -162,7 +162,7 @@ static struct page *ttm_pool_alloc_page(struct ttm_pool *pool, gfp_t gfp_flags, if (order) attr |= DMA_ATTR_NO_WARN; - vaddr = dma_alloc_attrs(pool->dev, (1ULL << order) * PAGE_SIZE, + vaddr = kcl_dma_alloc_attrs(pool->dev, (1ULL << order) * PAGE_SIZE, &dma->addr, gfp_flags, attr); if (!vaddr) goto error_free; @@ -210,7 +210,7 @@ static void ttm_pool_free_page(struct ttm_pool *pool, enum ttm_caching caching, dma = (void *)p->private; vaddr = (void *)(dma->vaddr & PAGE_MASK); - dma_free_attrs(pool->dev, (1UL << order) * PAGE_SIZE, vaddr, dma->addr, + kcl_dma_free_attrs(pool->dev, (1UL << order) * PAGE_SIZE, vaddr, dma->addr, attr); kfree(dma); } diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h index 1b7609d8ee876..0d58912e10533 100644 --- a/include/kcl/kcl_dma_mapping.h +++ b/include/kcl/kcl_dma_mapping.h @@ -27,6 +27,38 @@ void _kcl_convert_long_to_dma_attrs(struct dma_attrs *dma_attrs, dma_set_attr(i, dma_attrs); } } + +static inline +void *kcl_dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle, + gfp_t flag, unsigned long attrs) +{ + struct dma_attrs dma_attrs; + + _kcl_convert_long_to_dma_attrs(&dma_attrs, attrs); + return dma_alloc_attrs(dev, size, dma_handle, flag, &dma_attrs); +} + +static inline +void kcl_dma_free_attrs(struct device *dev, size_t size, void *cpu_addr, + dma_addr_t dma_handle, unsigned long attrs) +{ + struct dma_attrs dma_attrs; + + _kcl_convert_long_to_dma_attrs(&dma_attrs, attrs); + dma_free_attrs(dev, size, cpu_addr, dma_handle, &dma_attrs); +} +#else +static inline void *kcl_dma_alloc_attrs(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t flag, + unsigned long attrs) +{ + return dma_alloc_attrs(dev, size, dma_handle, flag, attrs); +} +static inline void kcl_dma_free_attrs(struct device *dev, size_t size, void *cpu_addr, + dma_addr_t dma_handle, unsigned long attrs) +{ + return dma_free_attrs(dev, size, cpu_addr, dma_handle, attrs); +} #endif #ifndef HAVE_DMA_MAP_SGTABLE From 20cd25201747c5dfc7ce587a6f808254416f0498 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 7 Sep 2020 13:36:31 +0800 Subject: [PATCH 0365/2653] drm/amdkcl: test for_each_sgtable_sg() Signed-off-by: Flora Cui --- include/kcl/kcl_dma_mapping.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h index 0d58912e10533..c65a83d51b953 100644 --- a/include/kcl/kcl_dma_mapping.h +++ b/include/kcl/kcl_dma_mapping.h @@ -120,4 +120,13 @@ static inline void dma_unmap_sgtable(struct device *dev, struct sg_table *sgt, } #endif +/* + * v5.8-rc3-2-g68d237056e00 ("scatterlist: protect parameters of the sg_table related macros") + * v5.7-rc5-33-g709d6d73c756 ("scatterlist: add generic wrappers for iterating over sgtable objects") + */ +#ifndef for_each_sgtable_sg +#define for_each_sgtable_sg(sgt, sg, i) \ + for_each_sg((sgt)->sgl, sg, (sgt)->orig_nents, i) +#endif + #endif From 46cb2a1ad18b7a9119d1be7a13bdcf793d127d1e Mon Sep 17 00:00:00 2001 From: Yang Xiong Date: Fri, 10 Jul 2020 16:04:02 +0800 Subject: [PATCH 0366/2653] drm/amdkcl: add kcl copy of epoll event masks macro introduced in v4.11-rc2-2-g7e040726850a This kcl patch is caused by patch: drm/amdkfd: sparse: fix incorrect type in assignment Signed-off-by: Yang Xiong Reviewed-by: Flora Cui Change-Id: I2ab2c440728cfa1a38c1cd8a0e230fb3ee7327ae --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_eventpoll.h | 33 +++++++++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 include/kcl/kcl_eventpoll.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index c2baa09d32bc3..020a1c6516280 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_eventpoll.h b/include/kcl/kcl_eventpoll.h new file mode 100644 index 0000000000000..5f23d49a7e46f --- /dev/null +++ b/include/kcl/kcl_eventpoll.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ +/* + * include/linux/eventpoll.h ( Efficient event polling implementation ) + * Copyright (C) 2001,...,2006 Davide Libenzi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Davide Libenzi + * + */ +#ifndef AMDKCL_EVENTPOLL_H +#define AMDKCL_EVENTPOLL_H + +#include + +/* Copied from include/uapi/linux/eventpoll.h */ +#ifndef EPOLLIN +#define EPOLLIN 0x00000001 +#define EPOLLPRI 0x00000002 +#define EPOLLOUT 0x00000004 +#define EPOLLERR 0x00000008 +#define EPOLLHUP 0x00000010 +#define EPOLLRDNORM 0x00000040 +#define EPOLLRDBAND 0x00000080 +#define EPOLLWRNORM 0x00000100 +#define EPOLLWRBAND 0x00000200 +#define EPOLLMSG 0x00000400 +#define EPOLLRDHUP 0x00002000 +#endif +#endif From 0da74572ccc35193aa5097df45c4d5e34fcd89fc Mon Sep 17 00:00:00 2001 From: tianci yin Date: Mon, 18 Feb 2019 10:59:12 +0800 Subject: [PATCH 0367/2653] drm/amdkcl: Test whether system_highpri_wq is available This is a squash of: drm/amdkcl: [3.16] add system_highpri_wq support Reviewed-by: Prike Liang Signed-off-by: Tianci Yin Signed-off-by: Jack Gui drm/amdkcl: Test whether system_highpri_wq is available system_highpri_wq is exported in kernel 3.6 and declared in kernel 3.15 Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui drm/amd/autoconf: fix system_highpri_wq unexported issue Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: drop test for system_highpri_wq Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_workqueue.h | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 include/kcl/kcl_workqueue.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 020a1c6516280..60e80984d0d19 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_workqueue.h b/include/kcl/kcl_workqueue.h new file mode 100644 index 0000000000000..345bd0f2cc384 --- /dev/null +++ b/include/kcl/kcl_workqueue.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef KCL_LINUX_WORKQUEUE_H +#define KCL_LINUX_WORKQUEUE_H + +#include + +/* + * System-wide workqueues which are always present. + * + * system_highpri_wq is similar to system_wq but for work items which + * require WQ_HIGHPRI. + * + * v3.15-rc1-18-g73e4354444ee workqueue: declare system_highpri_wq + * v3.6-rc1-20-g1aabe902ca36 workqueue: introduce system_highpri_wq + */ +extern struct workqueue_struct *system_highpri_wq; + +#endif From 49bb131ec3b7a9609062c8fa6142921500da77b4 Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Mon, 22 Oct 2018 17:08:04 +0800 Subject: [PATCH 0368/2653] drm/amdkcl: [4.13] Add sysfs node max_link_speed/width, current_link_speed/width For SWDEV-165476 require and implement the feature inquire node. KCL originally implemented as commit 02805f8d0d76 to add sysfs node for max_link_speed, max_link_width, current_link_speed, current_link_width proposed in commit 56c1af4606f0. Since most of the attributes introduced in the commit 56c1af4606f0 are static and only visible within the PCI compile unit, we cannot use autoconf to check if they are defined. In this commit, we use the macro PCI_EXP_LNKCAP_SLS_8_0GB checked-in along with these attributes as a workaround and further check the return value after calling device_create_file() by deliberately ignoring the -EEXIST error code to make sure the error log is not mis-reported. v1: drm/amdkcl: Add sysfs node max_link_speed/width, current_link_speed/width v2: drm/amdkcl: add macros in kcl_pci.h if checked undefinded v3: add macro undefined check for remove BUILD_AS_DKMS macro v4: drm/amdkcl: remove sysfs entry on exit Signed-off-by: Prike Liang Reviewed-by: xinhui pan Reviewed-by: Junwei Zhang Signed-off-by: Adam Yang Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 + drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 122 ++++++++++++++++++++++++ include/kcl/kcl_pci.h | 75 +++++++++++++++ 3 files changed, 199 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 465f87006964d..f18952ecbf327 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2441,6 +2441,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, kms_driver.driver_features |= DRIVER_ATOMIC; #endif + kcl_pci_create_measure_file(pdev); kcl_pci_configure_extended_tags(pdev); ret = pci_enable_device(pdev); if (ret) @@ -2575,6 +2576,7 @@ amdgpu_pci_remove(struct pci_dev *pdev) * Clear the Bus Master Enable bit and then wait on the PCIe Device * StatusTransactions Pending bit. */ + kcl_pci_remove_measure_file(pdev); pci_disable_device(pdev); pci_wait_for_pending_transaction(pdev); } diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index 171f3239eeb3a..13b6180f6b3ed 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -318,3 +318,125 @@ bool _kcl_pci_pr3_present(struct pci_dev *pdev) EXPORT_SYMBOL_GPL(_kcl_pci_pr3_present); #endif #endif /* HAVE_PCI_PR3_PRESENT */ + +#ifdef AMDKCL_CREATE_MEASURE_FILE +static ssize_t max_link_speed_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + + return sprintf(buf, "%s\n", PCIE_SPEED2STR(kcl_pcie_get_speed_cap(pdev))); +} +static DEVICE_ATTR_RO(max_link_speed); + +static ssize_t max_link_width_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + + return sprintf(buf, "%u\n", kcl_pcie_get_width_cap(pdev)); +} +static DEVICE_ATTR_RO(max_link_width); + +static ssize_t current_link_speed_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + u16 linkstat; + int err; + const char *speed; + + err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat); + if (err) + return -EINVAL; + + switch (linkstat & PCI_EXP_LNKSTA_CLS) { + case PCI_EXP_LNKSTA_CLS_16_0GB: + speed = "16 GT/s"; + break; + case PCI_EXP_LNKSTA_CLS_8_0GB: + speed = "8 GT/s"; + break; + case PCI_EXP_LNKSTA_CLS_5_0GB: + speed = "5 GT/s"; + break; + case PCI_EXP_LNKSTA_CLS_2_5GB: + speed = "2.5 GT/s"; + break; + default: + speed = "Unknown speed"; + } + + return sprintf(buf, "%s\n", speed); +} +static DEVICE_ATTR_RO(current_link_speed); + +static ssize_t current_link_width_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + u16 linkstat; + int err; + + err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat); + if (err) + return -EINVAL; + + return sprintf(buf, "%u\n", + (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT); +} +static DEVICE_ATTR_RO(current_link_width); + +static struct attribute *pcie_dev_attrs[] = { + &dev_attr_current_link_speed.attr, + &dev_attr_current_link_width.attr, + &dev_attr_max_link_width.attr, + &dev_attr_max_link_speed.attr, + NULL, +}; + +int _kcl_pci_create_measure_file(struct pci_dev *pdev) +{ + int ret = 0; + + ret = device_create_file(&pdev->dev, &dev_attr_current_link_speed); + if (ret) { + dev_err(&pdev->dev, + "Failed to create current_link_speed sysfs files: %d\n", ret); + return ret; + } + + ret = device_create_file(&pdev->dev, &dev_attr_current_link_width); + if (ret) { + dev_err(&pdev->dev, + "Failed to create current_link_width sysfs files: %d\n", ret); + return ret; + } + + ret = device_create_file(&pdev->dev, &dev_attr_max_link_width); + if (ret) { + dev_err(&pdev->dev, + "Failed to create max_link_width sysfs files: %d\n", ret); + return ret; + } + + ret = device_create_file(&pdev->dev, &dev_attr_max_link_speed); + if (ret) { + dev_err(&pdev->dev, + "Failed to create max_link_speed sysfs files: %d\n", ret); + return ret; + } + + return ret; +} +EXPORT_SYMBOL(_kcl_pci_create_measure_file); + +void _kcl_pci_remove_measure_file(struct pci_dev *pdev) +{ + device_remove_file(&pdev->dev, &dev_attr_current_link_speed); + device_remove_file(&pdev->dev, &dev_attr_current_link_width); + device_remove_file(&pdev->dev, &dev_attr_max_link_width); + device_remove_file(&pdev->dev, &dev_attr_max_link_speed); +} +EXPORT_SYMBOL(_kcl_pci_remove_measure_file); +#endif /* AMDKCL_CREATE_MEASURE_FILE */ diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 4eefafc20be1a..fe3c471def696 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -26,6 +26,58 @@ #include #include +#ifndef PCI_EXP_DEVCAP2_ATOMIC_ROUTE +#define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */ +#endif +#ifndef PCI_EXP_DEVCAP2_ATOMIC_COMP32 +#define PCI_EXP_DEVCAP2_ATOMIC_COMP32 0x00000080 /* 32b AtomicOp completion */ +#endif +#ifndef PCI_EXP_DEVCAP2_ATOMIC_COMP64 +#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* 64b AtomicOp completion*/ +#endif +#ifndef PCI_EXP_DEVCAP2_ATOMIC_COMP128 +#define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp completion*/ +#endif +#ifndef PCI_EXP_DEVCTL2_ATOMIC_REQ +#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */ +#endif +#ifndef PCI_EXP_DEVCTL2_ATOMIC_BLOCK +#define PCI_EXP_DEVCTL2_ATOMIC_BLOCK 0x0040 /* Block AtomicOp on egress */ +#endif + +#ifndef PCIE_SPEED_16_0GT +#define PCIE_SPEED_16_0GT 0x17 +#endif +#ifndef PCI_EXP_LNKCAP2_SLS_16_0GB +#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ +#endif +#ifndef PCI_EXP_LNKCAP_SLS_16_0GB +#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */ +#endif +#ifndef PCI_EXP_LNKSTA_CLS_16_0GB +#define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */ +#endif + +/* PCIe link information */ +#ifndef PCIE_SPEED2STR +#define PCIE_SPEED2STR(speed) \ + ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \ + (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \ + (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \ + (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \ + "Unknown speed") +#endif + +/* PCIe speed to Mb/s reduced by encoding overhead */ +#ifndef PCIE_SPEED2MBS_ENC +#define PCIE_SPEED2MBS_ENC(speed) \ + ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ + (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ + (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ + (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ + 0) +#endif + #if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) extern enum pci_bus_speed (*_kcl_pcie_get_speed_cap)(struct pci_dev *dev); extern enum pcie_link_width (*_kcl_pcie_get_width_cap)(struct pci_dev *dev); @@ -112,4 +164,27 @@ static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } #endif #endif /* HAVE_PCI_PR3_PRESENT */ +#ifndef PCI_EXP_LNKCAP_SLS_8_0GB +#define AMDKCL_CREATE_MEASURE_FILE +#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */ +int _kcl_pci_create_measure_file(struct pci_dev *pdev); +void _kcl_pci_remove_measure_file(struct pci_dev *pdev); +#endif + +static inline int kcl_pci_create_measure_file(struct pci_dev *pdev) +{ +#ifdef AMDKCL_CREATE_MEASURE_FILE + return _kcl_pci_create_measure_file(pdev); +#else + return 0; +#endif +} + +static inline void kcl_pci_remove_measure_file(struct pci_dev *pdev) +{ +#ifdef AMDKCL_CREATE_MEASURE_FILE + _kcl_pci_remove_measure_file(pdev); +#endif +} + #endif /* AMDKCL_PCI_H */ From 0e80d1ac6deeaff3f5f7c13d2420e2385803af3b Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 22 Apr 2020 22:15:29 +0800 Subject: [PATCH 0369/2653] drm/amdkcl: add PCI_EXP macro in kcl Change-Id: I16e3b99df53731bc3f8f836aeb1ac41763443810 Signed-off-by: Yifan Zhang --- include/kcl/kcl_pci.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index fe3c471def696..596f37906499c 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -44,6 +44,25 @@ #ifndef PCI_EXP_DEVCTL2_ATOMIC_BLOCK #define PCI_EXP_DEVCTL2_ATOMIC_BLOCK 0x0040 /* Block AtomicOp on egress */ #endif +#ifndef PCI_EXP_LNKCTL2_ENTER_COMP +#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ +#endif +#ifndef PCI_EXP_LNKCTL2_TX_MARGIN +#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ +#endif + +#ifndef PCI_EXP_LNKCTL2_TLS +#define PCI_EXP_LNKCTL2_TLS 0x000f +#endif +#ifndef PCI_EXP_LNKCTL2_TLS_2_5GT +#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ +#endif +#ifndef PCI_EXP_LNKCTL2_TLS_5_0GT +#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ +#endif +#ifndef PCI_EXP_LNKCTL2_TLS_8_0GT +#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ +#endif #ifndef PCIE_SPEED_16_0GT #define PCIE_SPEED_16_0GT 0x17 From 8f39a7e86c1a48b0894b64adf8627b91702ca1e8 Mon Sep 17 00:00:00 2001 From: tianci yin Date: Fri, 28 Aug 2020 16:25:15 +0800 Subject: [PATCH 0370/2653] drm/amdkcl: add macro for_each_if Signed-off-by: Tianci Yin Signed-off-by: tianci yin --- include/kcl/kcl_drm_crtc.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h index e0eaa2ace66b1..8b8b027aefbf9 100644 --- a/include/kcl/kcl_drm_crtc.h +++ b/include/kcl/kcl_drm_crtc.h @@ -74,6 +74,12 @@ DRM_MODE_ROTATE_270) #endif +/* Copied from include/drm/drm_util.h */ +/* helper for handling conditionals in various for_each macros */ +#ifndef for_each_if +#define for_each_if(condition) if (!(condition)) {} else +#endif + #if !defined(HAVE_DRM_HELPER_FORCE_DISABLE_ALL) int _kcl_drm_helper_force_disable_all(struct drm_device *dev); static inline From 1a53f12c1e15ecfc2dd1d553bf6b73669f2c8d8e Mon Sep 17 00:00:00 2001 From: changzhu Date: Wed, 26 Aug 2020 10:08:03 +0800 Subject: [PATCH 0371/2653] drm/amdkcl: check whether drm_for_each_xxx macros are available This is a squahs of: drm/amdkcl: drop redundant macro Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang This commit is used to fix bug in kcl_drm.h in redhat 7.2 v2: 57e9a478b988 - Clean up KCL macros. v3: drm/amdkcl: remove kcl_drm_for_each_ macro v4: move to kcl_drm_crtc.h Signed-off-by: changzhu Reviewed-by: Amber Lin Signed-off-by: Flora Cui --- include/kcl/kcl_drm_crtc.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h index 8b8b027aefbf9..2f01179d0c2b1 100644 --- a/include/kcl/kcl_drm_crtc.h +++ b/include/kcl/kcl_drm_crtc.h @@ -80,6 +80,21 @@ #define for_each_if(condition) if (!(condition)) {} else #endif +#ifndef drm_for_each_crtc +#define drm_for_each_crtc(crtc, dev) \ + list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) +#endif + +#ifndef drm_for_each_encoder +#define drm_for_each_encoder(encoder, dev) \ + list_for_each_entry(encoder, &(dev)->mode_config.encoder_list, head) +#endif + +#ifndef drm_for_each_fb +#define drm_for_each_fb(fb, dev) \ + list_for_each_entry(fb, &(dev)->mode_config.fb_list, head) +#endif + #if !defined(HAVE_DRM_HELPER_FORCE_DISABLE_ALL) int _kcl_drm_helper_force_disable_all(struct drm_device *dev); static inline @@ -89,4 +104,5 @@ int drm_helper_force_disable_all(struct drm_device *dev) } #endif + #endif From 25a1a655e064082901cfec6b7e4ec3dcd7d03e8f Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Mon, 29 Jul 2019 11:14:34 +0800 Subject: [PATCH 0372/2653] drm/amdkcl: check whether DP_DPRX_FEATURE_ENUMERATION_LIST is available This is a squash of: drm/amdkcl: test DP_TRAINING_PATTERN_SET_PHY_REPEATER1 directly Change-Id: I883c0612c232e08039518f40a794fdb9b148cd16 Signed-off-by: Stanley.Yang Reviewed-by: Rui Teng Signed-off-by: Yifan Zhang drm/amdkcl: test DP_TEST_AUDIO_MODE directory Change-Id: I1b903fc00c3710f88d9db5bd5f72bd60e88d7373 Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang drm/amdkcl: fake macro DP_DSC_SUPPORT Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang drm/amdkcl: move DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED check to kcl_drm_dp_helper.h Signed-off-by: Chengming Gui Reviewed-by: Flora Cui drm/amdkcl: refactor dp related macros Signed-off-by: Flora Cui Reviewed-by: Yang Xiong drm/amdkcl: fake kcl copy of DP_PHY_TEST_PATTERN Signed-off-by: Flora Cui Change-Id: I351a01e5881df067a68f0128ec48aba922e42790 Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui --- include/kcl/kcl_drm_dp_helper.h | 165 ++++++++++++++++++++++++++++++++ 1 file changed, 165 insertions(+) create mode 100644 include/kcl/kcl_drm_dp_helper.h diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h new file mode 100644 index 0000000000000..edb6b4202915b --- /dev/null +++ b/include/kcl/kcl_drm_dp_helper.h @@ -0,0 +1,165 @@ +/* + * Copyright © 2008 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + + +#ifndef _KCL_DRM_DP_HELPER_H_ +#define _KCL_DRM_DP_HELPER_H_ + +#include +#include +#include + +#include +#include +#include +#include + +/* + * v4.13-rc5-840-gc673fe7f0cd5 + * drm/dp: DPCD register defines for link status within ESI field + */ +#ifndef DP_LANE0_1_STATUS_ESI +#define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */ +#define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */ +#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */ +#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */ +#endif + +/* + * v4.13-rc5-1383-gac58fff15516 + * drm/dp-helper: add missing defines needed by AMD display core. + */ +#ifndef DP_ADJUST_REQUEST_POST_CURSOR2 +#define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c + +#define DP_TEST_MISC0 0x232 + +#define DP_TEST_PHY_PATTERN 0x248 +#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 +#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 +#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252 +#define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253 +#define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254 +#define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255 +#define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256 +#define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257 +#define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258 +#define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259 + +#define DP_BRANCH_REVISION_START 0x509 + +#define DP_DP13_DPCD_REV 0x2200 +#define DP_DP13_MAX_LINK_RATE 0x2201 +#endif + + +#if !defined(DP_DPRX_FEATURE_ENUMERATION_LIST) +#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */ +#endif + +#if !defined(DP_TRAINING_PATTERN_SET_PHY_REPEATER1) +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ +#endif + +#if !defined(DP_LANE0_1_STATUS_PHY_REPEATER1) +#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */ +#endif + +#if !defined(DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1) +#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */ +#endif + +#if !defined(DP_TRAINING_LANE0_SET_PHY_REPEATER1) +#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */ +#endif + +#if !defined(DP_PHY_REPEATER_MODE_TRANSPARENT) +#define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */ +#endif + +#if !defined(DP_PHY_REPEATER_MODE) +#define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */ +#endif + +#if !defined(DP_PHY_REPEATER_MODE_NON_TRANSPARENT) +#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */ +#endif + +#if !defined(DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) +#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */ +#endif + +#if !defined(DP_TRAINING_PATTERN_SET_PHY_REPEATER1) +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ +#endif + +#if !defined(DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT) +#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ +#endif + +#if !defined(DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV) +#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */ +#endif + +#if !defined(DP_MAX_LINK_RATE_PHY_REPEATER) +#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */ +#endif + +#if !defined(DP_PHY_REPEATER_CNT) +#define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */ +#endif + +#if !defined(DP_MAX_LANE_COUNT_PHY_REPEATER) +#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ +#endif + +#if !defined(DP_TEST_AUDIO_MODE) +#define DP_TEST_AUDIO_MODE 0x271 +#endif + +#if !defined(DP_TEST_AUDIO_PATTERN_TYPE) +#define DP_TEST_AUDIO_PATTERN_TYPE 0x272 +#endif + +#if !defined(DP_TEST_AUDIO_PERIOD_CH1) +#define DP_TEST_AUDIO_PERIOD_CH1 0x273 +#endif + +#if !defined(DP_DSC_SUPPORT) +#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ +#endif + +/* + * v5.6-1624-g8811d9eb4dfa + * drm/amd/display: Align macro name as per DP spec + */ +#ifdef DP_TEST_PHY_PATTERN +#define DP_PHY_TEST_PATTERN DP_TEST_PHY_PATTERN +#endif + +/* commit fc1424c2ec813080aa1eaa2948070902b1a0e507 + * drm: Correct DP DSC macro typo */ +#ifdef DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED +#define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED +#endif + +#endif /* _KCL_DRM_DP_HELPER_H_ */ From 1058a97fc79ffc59b530283777d1554c5f477343 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Fri, 23 Dec 2016 18:24:00 +0800 Subject: [PATCH 0373/2653] drm/amdkcl: add AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL && AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL dma_fence_get_rcu_safe() history: v4.8-rc8-1410-g4be0542073a3 introduce +static inline struct fence *fence_get_rcu_safe(struct fence * __rcu *fencep) v4.9-rc2-299-gf54d1867005c dma-buf: Rename struct fence to dma_fence v4.14-rc3-486-gf8e0731db4a0 dma-fence: fix dma_fence_get_rcu_safe v2 - if (!fence || !dma_fence_get_rcu(fence)) + if (!fence) return NULL; + if (!dma_fence_get_rcu(fence)) + continue; + v4.14-rc3-601-g5f72db59160c dma-buf/fence: Sparse wants __rcu on the object itself -dma_fence_get_rcu_safe(struct dma_fence * __rcu *fencep) +dma_fence_get_rcu_safe(struct dma_fence __rcu **fencep) v1: drm/amdkcl: [4.8] add fence array support v2: drm/amdkcl: Test whether dma_fence header is available v3: drm/amdkcl: refactor kcl copy dma_fence_is_later() v4: drm/amdkcl: add AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL v5: drm/amdkcl: add AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL v6: drm/amdkcl: refactor check for dma_fence_wait_any_timeout v7: drm/amdkcl: refactor check for fence_default_wait, fence_wait_timeout v8: drm/amdkcl: refactor check for fence_get_rcu_safe v9: drm/amdkcl: include kcl_fence.h for dkms build v10: drm/amdkcl: drop kcl_fence_context_alloc & kcl_fence_init v11: drm/amdkcl: fix kcl_fence_get_rcu_safe() v12: drm/amdkcl: fix kcl_fence_default_wait v13: drm/amdkcl: drop test for linux/dma-fence.h outside of kcl v14: drm/amdkcl: drop test for linux/dma-fence-array.h outside of kcl Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Acked-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 1 + drivers/gpu/drm/scheduler/sched_fence.c | 4 ++++ 3 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c index 1ef758ac5076e..85e560df7f6b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c @@ -184,5 +184,6 @@ static const struct dma_fence_ops amdkfd_fence_ops = { .get_driver_name = amdkfd_fence_get_driver_name, .get_timeline_name = amdkfd_fence_get_timeline_name, .enable_signaling = amdkfd_fence_enable_signaling, + AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = amdkfd_fence_release, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index fd1c72cf69282..16ca58d932da1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -931,6 +931,7 @@ static const struct dma_fence_ops amdgpu_fence_ops = { .get_driver_name = amdgpu_fence_get_driver_name, .get_timeline_name = amdgpu_fence_get_timeline_name, .enable_signaling = amdgpu_fence_enable_signaling, + AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = amdgpu_fence_release, }; diff --git a/drivers/gpu/drm/scheduler/sched_fence.c b/drivers/gpu/drm/scheduler/sched_fence.c index 9391d6f0dc01d..acd4eaab1fd03 100644 --- a/drivers/gpu/drm/scheduler/sched_fence.c +++ b/drivers/gpu/drm/scheduler/sched_fence.c @@ -183,12 +183,16 @@ static void drm_sched_fence_set_deadline_finished(struct dma_fence *f, static const struct dma_fence_ops drm_sched_fence_ops_scheduled = { .get_driver_name = drm_sched_fence_get_driver_name, .get_timeline_name = drm_sched_fence_get_timeline_name, + AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL + AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = drm_sched_fence_release_scheduled, }; static const struct dma_fence_ops drm_sched_fence_ops_finished = { .get_driver_name = drm_sched_fence_get_driver_name, .get_timeline_name = drm_sched_fence_get_timeline_name, + AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL + AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = drm_sched_fence_release_finished, .set_deadline = drm_sched_fence_set_deadline_finished, }; From 8abf82b0d3ed4b44b5b2d614e6be27d669891a99 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 13 Jul 2020 14:39:08 +0800 Subject: [PATCH 0374/2653] drm/amdkcl: dkms support for hmm Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Change-Id: I261b55baa69cc111cde879705b8950573af0d6d3 --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 3 + .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 95 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 111 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 14 + drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 480 +++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 36 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 5 + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 230 ++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 7 +- drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 35 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 15 files changed, 1022 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/hmm.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index abd04072d204a..56c0a7b960b45 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -302,7 +302,7 @@ endif amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o -amdgpu-$(CONFIG_HMM_MIRROR) += amdgpu_hmm.o +amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_hmm.o include $(FULL_AMD_PATH)/pm/Makefile diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 0a719ce838401..5cf24c5b6b4ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1243,7 +1243,9 @@ struct amdgpu_device { enum pp_mp1_state mp1_state; struct amdgpu_doorbell_index doorbell_index; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED struct mutex notifier_lock; +#endif int asic_reset_res; struct work_struct xgmi_reset_work; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index b3be72ed70373..047dfae22515e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -84,6 +84,9 @@ struct kgd_mem { uint32_t invalid; struct amdkfd_process_info *process_info; +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + struct page **user_pages; +#endif struct amdgpu_sync sync; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 895ff89716cb5..e140fca7694eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1074,6 +1074,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, return 0; } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &range); if (ret) { if (ret == -EAGAIN) @@ -1082,6 +1083,29 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, pr_err("%s: Failed to get user pages: %d\n", __func__, ret); goto unregister_out; } +#else + /* If no restore worker is running concurrently, user_pages + * should not be allocated + */ + WARN(mem->user_pages, "Leaking user_pages array"); + + mem->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages, + sizeof(struct page *), + GFP_KERNEL | __GFP_ZERO); + if (!mem->user_pages) { + pr_err("%s: Failed to allocate pages array\n", __func__); + ret = -ENOMEM; + goto unregister_out; + } + + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); + if (ret) { + pr_err("%s: Failed to get user pages: %d\n", __func__, ret); + goto free_out; + } + + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, mem->user_pages); +#endif ret = amdgpu_bo_reserve(bo, true); if (ret) { @@ -1095,7 +1119,15 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, amdgpu_bo_unreserve(bo); release_out: +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); +#else + if (ret) + release_pages(mem->user_pages, bo->tbo.ttm->num_pages); +free_out: + kvfree(mem->user_pages); + mem->user_pages = NULL; +#endif unregister_out: if (ret) amdgpu_hmm_unregister(bo); @@ -1898,6 +1930,17 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( mutex_unlock(&process_info->notifier_lock); } +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + /* Free user pages if necessary */ + if (mem->user_pages) { + pr_debug("%s: Freeing user_pages array\n", __func__); + if (mem->user_pages[0]) + release_pages(mem->user_pages, + mem->bo->tbo.ttm->num_pages); + kvfree(mem->user_pages); + } +#endif + ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx); if (unlikely(ret)) return ret; @@ -2789,6 +2832,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, } } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* Get updated user pages */ ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &mem->range); @@ -2819,9 +2863,35 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, ret = 0; } +#else + if (!mem->user_pages) { + mem->user_pages = + kvmalloc_array(bo->tbo.ttm->num_pages, + sizeof(struct page *), + GFP_KERNEL | __GFP_ZERO); + if (!mem->user_pages) { + pr_err("%s: Failed to allocate pages array\n", + __func__); + return -ENOMEM; + } + } else if (mem->user_pages[0]) { + release_pages(mem->user_pages, bo->tbo.ttm->num_pages); + } + /* Get updated user pages */ + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); + if (ret) { + mem->user_pages[0] = NULL; + pr_info("%s: Failed to get user pages: %d\n", + __func__, ret); + /* Pretend it succeeded. It will fail later + * with a VM fault if the GPU tries to access + * it. Better than hanging indefinitely with + * stalled user mode queues. + */ + } +#endif mutex_lock(&process_info->notifier_lock); - /* Mark the BO as valid unless it was invalidated * again concurrently. */ @@ -2895,6 +2965,7 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) bo = mem->bo; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* Validate the BO if we got user pages */ if (bo->tbo.ttm->pages[0]) { amdgpu_bo_placement_from_domain(bo, mem->domain); @@ -2905,6 +2976,28 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) } } +#else + /* Copy pages array and validate the BO if we got user pages */ + if (mem->user_pages[0]) { + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, + mem->user_pages); + amdgpu_bo_placement_from_domain(bo, mem->domain); + ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); + if (ret) { + pr_err("%s: failed to validate BO\n", __func__); + goto unreserve_out; + } + } + + /* Validate succeeded, now the BO owns the pages, free + * our copy of the pointer array. Put this BO back on + * the userptr_valid_list. If we need to revalidate + * it, we need to start from scratch. + */ + kvfree(mem->user_pages); + mem->user_pages = NULL; +#endif + /* Update mapping. If the BO was not validated * (because we couldn't get user pages), this will * clear the page table entries, which will result in diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h index 555cd6d877c30..204bee0e32562 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h @@ -40,7 +40,11 @@ struct amdgpu_bo_list_entry { uint32_t priority; struct page **user_pages; struct hmm_range *range; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool user_invalidated; +#else + int user_invalidated; +#endif }; struct amdgpu_bo_list { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 67a45cfc70ecd..ff9da699bde2e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -872,6 +872,9 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, struct amdgpu_bo_list_entry *e; struct drm_gem_object *obj; unsigned long index; +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + unsigned tries = 10; +#endif unsigned int i; int r; @@ -894,6 +897,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, mutex_lock(&p->bo_list->bo_list_mutex); + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* Get userptr backing pages. If pages are updated after registered * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do * amdgpu_ttm_backend_bind() to flush and invalidate new pages @@ -953,6 +958,82 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto out_free_user_pages; } } +#else + while (1) { + struct list_head need_pages; + + r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, + &duplicates); + if (unlikely(r != 0)) { + if (r != -ERESTARTSYS) + DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); + goto error_free_pages; + } + + INIT_LIST_HEAD(&need_pages); + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + + if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm, + &e->user_invalidated) && e->user_pages) { + + /* We acquired a page array, but somebody + * invalidated it. Free it and try again + */ + release_pages(e->user_pages, + bo->tbo.ttm->num_pages); + kvfree(e->user_pages); + e->user_pages = NULL; + } + + if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) && + !e->user_pages) { + list_del(&e->tv.head); + list_add(&e->tv.head, &need_pages); + + amdgpu_bo_unreserve(bo); + } + } + + if (list_empty(&need_pages)) + break; + + /* Unreserve everything again. */ + ttm_eu_backoff_reservation(&p->ticket, &p->validated); + + /* We tried too many times, just abort */ + if (!--tries) { + r = -EDEADLK; + DRM_ERROR("deadlock in %s\n", __func__); + goto error_free_pages; + } + + /* Fill the page arrays for all userptrs. */ + list_for_each_entry(e, &need_pages, tv.head) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + + e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages, + sizeof(struct page*), + GFP_KERNEL | __GFP_ZERO); + if (!e->user_pages) { + r = -ENOMEM; + DRM_ERROR("calloc failure in %s\n", __func__); + goto error_free_pages; + } + + r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages); + if (r) { + DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); + kvfree(e->user_pages); + e->user_pages = NULL; + goto error_free_pages; + } + } + + /* And try again. */ + list_splice(&need_pages, &p->validated); + } +#endif amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { struct mm_struct *usermm; @@ -1015,6 +1096,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, p->bo_list->oa_obj); return 0; + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED out_free_user_pages: amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { struct amdgpu_bo *bo = e->bo; @@ -1026,6 +1109,17 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, e->user_pages = NULL; e->range = NULL; } +#else +error_free_pages: + + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + if (!e->user_pages) + continue; + + release_pages(e->user_pages, e->tv.bo->ttm->num_pages); + kvfree(e->user_pages); + } +#endif mutex_unlock(&p->bo_list->bo_list_mutex); return r; } @@ -1345,6 +1439,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, amdgpu_job_set_gang_leader(p->jobs[i], leader); } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* No memory allocation is allowed while holding the notifier lock. * The lock is held until amdgpu_cs_submit is finished and fence is * added to BOs. @@ -1365,6 +1460,18 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, mutex_unlock(&p->adev->notifier_lock); return r; } +#else + /* No memory allocation is allowed while holding the mn lock */ + amdgpu_mn_lock(p->mn); + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + + if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) { + r = -ERESTARTSYS; + goto error_abort; + } + } +#endif p->fence = dma_fence_get(&leader->base.s_fence->finished); drm_exec_for_each_locked_object(&p->exec, index, gobj) { @@ -1408,7 +1515,11 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mutex_unlock(&p->adev->notifier_lock); +#else + amdgpu_mn_unlock(p->mn); +#endif mutex_unlock(&p->bo_list->bo_list_mutex); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index ce28db4ba081d..fa99792eb2be2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4416,7 +4416,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->virt.vf_errors.lock); hash_init(adev->mn_hash); mutex_init(&adev->psp.mutex); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mutex_init(&adev->notifier_lock); +#endif mutex_init(&adev->pm.stable_pstate_ctx_lock); mutex_init(&adev->benchmark_mutex); mutex_init(&adev->gfx.reset_sem_mutex); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index c3d9a1b90afd0..6c61146c7d56b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -632,14 +632,28 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, } r = drm_gem_handle_create(filp, gobj, &handle); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (r) goto user_pages_done; args->handle = handle; +#else + /* drop reference from allocate - handle holds it now */ + drm_gem_object_put(gobj); + if (r) + return r; + + args->handle = handle; + return 0; +#endif user_pages_done: +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); +#else + release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages); +#endif release_object: drm_gem_object_put(gobj); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 3c928bc9d48c0..fa888fbcb17ba 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -51,8 +51,485 @@ #include "amdgpu_amdkfd.h" #include "amdgpu_hmm.h" -#define MAX_WALK_BYTE (2UL << 30) +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED +/** + * struct amdgpu_mn + * + * @adev: amdgpu device pointer + * @mm: process address space + * @mn: MMU notifier structure + * @type: type of MMU notifier + * @work: destruction work item + * @node: hash table node to find structure by adev and mn + * @lock: rw semaphore protecting the notifier nodes + * @objects: interval tree containing amdgpu_mn_nodes + * @read_lock: mutex for recursive locking of @lock + * @recursion: depth of recursion + * + * Data for each amdgpu device and process address space. + */ +struct amdgpu_mn { + /* constant after initialisation */ + struct amdgpu_device *adev; + struct mm_struct *mm; + struct mmu_notifier mn; + enum amdgpu_mn_type type; + + /* only used on destruction */ + struct work_struct work; + + /* protected by adev->mn_lock */ + struct hlist_node node; + + /* objects protected by lock */ + struct rw_semaphore lock; + struct rb_root_cached objects; + struct mutex read_lock; + atomic_t recursion; +}; + +/** + * struct amdgpu_mn_node + * + * @it: interval node defining start-last of the affected address range + * @bos: list of all BOs in the affected address range + * + * Manages all BOs which are affected of a certain range of address space. + */ +struct amdgpu_mn_node { + struct interval_tree_node it; + struct list_head bos; +}; + +/** + * amdgpu_mn_destroy - destroy the MMU notifier + * + * @work: previously sheduled work item + * + * Lazy destroys the notifier from a work item + */ +static void amdgpu_mn_destroy(struct work_struct *work) +{ + struct amdgpu_mn *amn = container_of(work, struct amdgpu_mn, work); + struct amdgpu_device *adev = amn->adev; + struct amdgpu_mn_node *node, *next_node; + struct amdgpu_bo *bo, *next_bo; + + mutex_lock(&adev->mn_lock); + down_write(&amn->lock); + hash_del(&amn->node); + rbtree_postorder_for_each_entry_safe(node, next_node, + &amn->objects.rb_root, it.rb) { + list_for_each_entry_safe(bo, next_bo, &node->bos, mn_list) { + bo->mn = NULL; + list_del_init(&bo->mn_list); + } + kfree(node); + } + up_write(&amn->lock); + mutex_unlock(&adev->mn_lock); + mmu_notifier_unregister_no_release(&amn->mn, amn->mm); + kfree(amn); +} + +/** + * amdgpu_mn_release - callback to notify about mm destruction + * + * @mn: our notifier + * @mm: the mm this callback is about + * + * Shedule a work item to lazy destroy our notifier. + */ +static void amdgpu_mn_release(struct mmu_notifier *mn, + struct mm_struct *mm) +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + + INIT_WORK(&amn->work, amdgpu_mn_destroy); + schedule_work(&amn->work); +} + + +/** + * amdgpu_mn_lock - take the write side lock for this notifier + * + * @mn: our notifier + */ +void amdgpu_mn_lock(struct amdgpu_mn *mn) +{ + if (mn) + down_write(&mn->lock); +} + +/** + * amdgpu_mn_unlock - drop the write side lock for this notifier + * + * @mn: our notifier + */ +void amdgpu_mn_unlock(struct amdgpu_mn *mn) +{ + if (mn) + up_write(&mn->lock); +} + +/** + * amdgpu_mn_read_lock - take the read side lock for this notifier + * + * @amn: our notifier + */ +static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable) +{ + if (blockable) + mutex_lock(&amn->read_lock); + else if (!mutex_trylock(&amn->read_lock)) + return -EAGAIN; + + if (atomic_inc_return(&amn->recursion) == 1) + down_read_non_owner(&amn->lock); + mutex_unlock(&amn->read_lock); + + return 0; +} + +/** + * amdgpu_mn_read_unlock - drop the read side lock for this notifier + * + * @amn: our notifier + */ +static void amdgpu_mn_read_unlock(struct amdgpu_mn *amn) +{ + if (atomic_dec_return(&amn->recursion) == 0) + up_read_non_owner(&amn->lock); +} + +/** + * amdgpu_mn_invalidate_node - unmap all BOs of a node + * + * @node: the node with the BOs to unmap + * @start: start of address range affected + * @end: end of address range affected + * + * Block for operations on BOs to finish and mark pages as accessed and + * potentially dirty. + */ +static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node, + unsigned long start, + unsigned long end) +{ + struct amdgpu_bo *bo; + long r; + + list_for_each_entry(bo, &node->bos, mn_list) { + + if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end)) + continue; + + r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&bo->tbo), + true, false, MAX_SCHEDULE_TIMEOUT); + if (r <= 0) + DRM_ERROR("(%ld) failed to wait for user bo\n", r); + + amdgpu_ttm_tt_mark_user_pages(bo->tbo.ttm); + } +} + +/** + * amdgpu_mn_invalidate_range_start_gfx - callback to notify about mm change + * + * @mn: our notifier + * @range: mmu notifier context + * + * Block for operations on BOs to finish and mark pages as accessed and + * potentially dirty. + */ +static int amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, + const struct mmu_notifier_range *range) +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + struct interval_tree_node *it; + unsigned long end; + + /* notification is exclusive, but interval is inclusive */ + end = range->end - 1; + + /* TODO we should be able to split locking for interval tree and + * amdgpu_mn_invalidate_node + */ + if (amdgpu_mn_read_lock(amn, mmu_notifier_range_blockable(range))) + return -EAGAIN; + + it = interval_tree_iter_first(&amn->objects, range->start, end); + while (it) { + struct amdgpu_mn_node *node; + + if (!mmu_notifier_range_blockable(range)) { + amdgpu_mn_read_unlock(amn); + return -EAGAIN; + } + + node = container_of(it, struct amdgpu_mn_node, it); + it = interval_tree_iter_next(it, range->start, end); + + amdgpu_mn_invalidate_node(node, range->start, end); + } + + return 0; +} + +/** + * amdgpu_mn_invalidate_range_start_hsa - callback to notify about mm change + * + * @mn: our notifier + * @mm: the mm this callback is about + * @start: start of updated range + * @end: end of updated range + * + * We temporarily evict all BOs between start and end. This + * necessitates evicting all user-mode queues of the process. The BOs + * are restorted in amdgpu_mn_invalidate_range_end_hsa. + */ +static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, + const struct mmu_notifier_range *range) +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + struct interval_tree_node *it; + unsigned long end; + + /* notification is exclusive, but interval is inclusive */ + end = range->end - 1; + + if (amdgpu_mn_read_lock(amn, mmu_notifier_range_blockable(range))) + return -EAGAIN; + + it = interval_tree_iter_first(&amn->objects, range->start, end); + while (it) { + struct amdgpu_mn_node *node; + struct amdgpu_bo *bo; + + if (!mmu_notifier_range_blockable(range)) { + amdgpu_mn_read_unlock(amn); + return -EAGAIN; + } + + node = container_of(it, struct amdgpu_mn_node, it); + it = interval_tree_iter_next(it, range->start, end); + + list_for_each_entry(bo, &node->bos, mn_list) { + struct kgd_mem *mem = bo->kfd_bo; + + if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, + range->start, + end)) + amdgpu_amdkfd_evict_userptr(mem, range->mm); + } + } + + return 0; +} + +/** + * amdgpu_mn_invalidate_range_end - callback to notify about mm change + * + * @mn: our notifier + * @mm: the mm this callback is about + * @start: start of updated range + * @end: end of updated range + * + * Release the lock again to allow new command submissions. + */ +static void amdgpu_mn_invalidate_range_end(struct mmu_notifier *mn, + const struct mmu_notifier_range *range) +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + + amdgpu_mn_read_unlock(amn); +} + +static const struct mmu_notifier_ops amdgpu_mn_ops[] = { + [AMDGPU_MN_TYPE_GFX] = { + .release = amdgpu_mn_release, + .invalidate_range_start = amdgpu_mn_invalidate_range_start_gfx, + .invalidate_range_end = amdgpu_mn_invalidate_range_end, + }, + [AMDGPU_MN_TYPE_HSA] = { + .release = amdgpu_mn_release, + .invalidate_range_start = amdgpu_mn_invalidate_range_start_hsa, + .invalidate_range_end = amdgpu_mn_invalidate_range_end, + }, +}; + +/* Low bits of any reasonable mm pointer will be unused due to struct + * alignment. Use these bits to make a unique key from the mm pointer + * and notifier type. + */ +#define AMDGPU_MN_KEY(mm, type) ((unsigned long)(mm) + (type)) + +/** + * amdgpu_mn_get - create notifier context + * + * @adev: amdgpu device pointer + * @type: type of MMU notifier context + * + * Creates a notifier context for current->mm. + */ +struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, + enum amdgpu_mn_type type) +{ + struct mm_struct *mm = current->mm; + struct amdgpu_mn *amn; + unsigned long key = AMDGPU_MN_KEY(mm, type); + int r; + + mutex_lock(&adev->mn_lock); + if (down_write_killable(&mm->mmap_sem)) { + mutex_unlock(&adev->mn_lock); + return ERR_PTR(-EINTR); + } + + hash_for_each_possible(adev->mn_hash, amn, node, key) + if (AMDGPU_MN_KEY(amn->mm, amn->type) == key) + goto release_locks; + + amn = kzalloc(sizeof(*amn), GFP_KERNEL); + if (!amn) { + amn = ERR_PTR(-ENOMEM); + goto release_locks; + } + + amn->adev = adev; + amn->mm = mm; + init_rwsem(&amn->lock); + amn->type = type; + amn->mn.ops = &amdgpu_mn_ops[type]; + amn->objects = RB_ROOT_CACHED; + mutex_init(&amn->read_lock); + atomic_set(&amn->recursion, 0); + + r = __mmu_notifier_register(&amn->mn, mm); + if (r) + goto free_amn; + + hash_add(adev->mn_hash, &amn->node, AMDGPU_MN_KEY(mm, type)); + +release_locks: + up_write(&mm->mmap_sem); + mutex_unlock(&adev->mn_lock); + + return amn; + +free_amn: + up_write(&mm->mmap_sem); + mutex_unlock(&adev->mn_lock); + kfree(amn); + + return ERR_PTR(r); +} + +/** + * amdgpu_mn_register - register a BO for notifier updates + * + * @bo: amdgpu buffer object + * @addr: userptr addr we should monitor + * + * Registers an MMU notifier for the given BO at the specified address. + * Returns 0 on success, -ERRNO if anything goes wrong. + */ +int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) +{ + unsigned long end = addr + amdgpu_bo_size(bo) - 1; + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + enum amdgpu_mn_type type = + bo->kfd_bo ? AMDGPU_MN_TYPE_HSA : AMDGPU_MN_TYPE_GFX; + struct amdgpu_mn *amn; + struct amdgpu_mn_node *node = NULL, *new_node; + struct list_head bos; + struct interval_tree_node *it; + + amn = amdgpu_mn_get(adev, type); + if (IS_ERR(amn)) + return PTR_ERR(amn); + + new_node = kmalloc(sizeof(*new_node), GFP_KERNEL); + if (!new_node) + return -ENOMEM; + + INIT_LIST_HEAD(&bos); + + down_write(&amn->lock); + + while ((it = interval_tree_iter_first(&amn->objects, addr, end))) { + kfree(node); + node = container_of(it, struct amdgpu_mn_node, it); + interval_tree_remove(&node->it, &amn->objects); + addr = min(it->start, addr); + end = max(it->last, end); + list_splice(&node->bos, &bos); + } + + if (!node) + node = new_node; + else + kfree(new_node); + + bo->mn = amn; + + node->it.start = addr; + node->it.last = end; + INIT_LIST_HEAD(&node->bos); + list_splice(&bos, &node->bos); + list_add(&bo->mn_list, &node->bos); + + interval_tree_insert(&node->it, &amn->objects); + + up_write(&amn->lock); + + return 0; +} + +/** + * amdgpu_mn_unregister - unregister a BO for notifier updates + * + * @bo: amdgpu buffer object + * + * Remove any registration of MMU notifier updates from the buffer object. + */ +void amdgpu_mn_unregister(struct amdgpu_bo *bo) +{ + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + struct amdgpu_mn *amn; + struct list_head *head; + + mutex_lock(&adev->mn_lock); + + amn = bo->mn; + if (amn == NULL) { + mutex_unlock(&adev->mn_lock); + return; + } + + down_write(&amn->lock); + + /* save the next list entry for later */ + head = bo->mn_list.next; + + bo->mn = NULL; + list_del_init(&bo->mn_list); + + if (list_empty(head)) { + struct amdgpu_mn_node *node; + + node = container_of(head, struct amdgpu_mn_node, bos); + interval_tree_remove(&node->it, &amn->objects); + kfree(node); + } + + up_write(&amn->lock); + mutex_unlock(&adev->mn_lock); +} + +#else /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ +#define MAX_WALK_BYTE (2UL << 30) /** * amdgpu_hmm_invalidate_gfx - callback to notify about mm change * @@ -255,3 +732,4 @@ bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range) return r; } +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index e2edcd010cccb..7d7a087899125 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -24,6 +24,41 @@ #ifndef __AMDGPU_MN_H__ #define __AMDGPU_MN_H__ +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED +#include +#include +/* + * MMU Notifier + */ +struct amdgpu_mn; + +enum amdgpu_mn_type { + AMDGPU_MN_TYPE_GFX, + AMDGPU_MN_TYPE_HSA, +}; + +#if defined(CONFIG_MMU_NOTIFIER) +void amdgpu_mn_lock(struct amdgpu_mn *mn); +void amdgpu_mn_unlock(struct amdgpu_mn *mn); +struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, + enum amdgpu_mn_type type); +int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); +void amdgpu_mn_unregister(struct amdgpu_bo *bo); +#else /* !CONFIG_MMU_NOTIFIER */ +static inline void amdgpu_mn_lock(struct amdgpu_mn *mn) {} +static inline void amdgpu_mn_unlock(struct amdgpu_mn *mn) {} +static inline struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, + enum amdgpu_mn_type type) +{ + return NULL; +} +static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) +{ + return -ENODEV; +} +static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} +#endif /* CONFIG_MMU_NOTIFIER */ +#else /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ #include #include #include @@ -49,5 +84,6 @@ static inline int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) } static inline void amdgpu_hmm_unregister(struct amdgpu_bo *bo) {} #endif +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 1b8685bf4ff05..b1c1b695f3afc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -112,9 +112,14 @@ struct amdgpu_bo { /* Constant after initialization */ struct amdgpu_bo *parent; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED #ifdef CONFIG_MMU_NOTIFIER struct mmu_interval_notifier notifier; #endif +#else + struct list_head mn_list; +#endif + struct kgd_mem *kfd_bo; /* DGMA imported buffer info */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 2d6f9fcaafa28..1608581792a68 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -32,6 +32,9 @@ #include #include +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED +#include +#endif #include #include #include @@ -712,6 +715,13 @@ uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) /* * TTM backend functions. */ +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED +struct amdgpu_ttm_gup_task_list { + struct list_head list; + struct task_struct *task; +}; +#endif + struct amdgpu_ttm_tt { struct ttm_tt ttm; struct drm_gem_object *gobj; @@ -720,12 +730,19 @@ struct amdgpu_ttm_tt { struct task_struct *usertask; uint32_t userflags; bool bound; +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + spinlock_t guptasklock; + struct list_head guptasks; + atomic_t mmu_invalidations; + uint32_t last_set_pages; +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ int32_t pool_id; }; #define ttm_to_amdgpu_ttm_tt(ptr) container_of(ptr, struct amdgpu_ttm_tt, ttm) #ifdef CONFIG_DRM_AMDGPU_USERPTR +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user * memory and start HMM tracking CPU page table update @@ -813,8 +830,89 @@ bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, return !amdgpu_hmm_range_get_pages_done(range); } -#endif +#else +/* + * amdgpu_ttm_tt_get_user_pages - Pin pages of memory pointed to by a USERPTR + * pointer to memory + * + * Called by amdgpu_gem_userptr_ioctl() and amdgpu_cs_parser_bos(). + * This provides a wrapper around the get_user_pages() call to provide + * device accessible pages that back user memory. + */ +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) +{ + struct ttm_tt *ttm = bo->tbo.ttm; + struct amdgpu_ttm_tt *gtt = (void *)ttm; + struct mm_struct *mm = gtt->usertask->mm; + unsigned int flags = 0; + unsigned pinned = 0; + int r; + + if (!mm) /* Happens during process shutdown */ + return -ESRCH; + + if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) + flags |= FOLL_WRITE; + + down_read(&mm->mmap_sem); + + if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) { + /* + * check that we only use anonymous memory to prevent problems + * with writeback + */ + unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; + struct vm_area_struct *vma; + + vma = find_vma(mm, gtt->userptr); + if (!vma || vma->vm_file || vma->vm_end < end) { + up_read(&mm->mmap_sem); + return -EPERM; + } + } + + /* loop enough times using contiguous pages of memory */ + do { + unsigned num_pages = ttm->num_pages - pinned; + uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; + struct page **p = pages + pinned; + struct amdgpu_ttm_gup_task_list guptask; + + guptask.task = current; + spin_lock(>t->guptasklock); + list_add(&guptask.list, >t->guptasks); + spin_unlock(>t->guptasklock); + + if (mm == current->mm) + r = get_user_pages(userptr, num_pages, flags, p, NULL); + else + r = get_user_pages_remote(mm, userptr, num_pages, + flags, p, NULL, NULL); + + spin_lock(>t->guptasklock); + list_del(&guptask.list); + spin_unlock(>t->guptasklock); + + if (r < 0) + goto release_pages; + + pinned += r; + + } while (pinned < ttm->num_pages); + + up_read(&mm->mmap_sem); + return 0; + +release_pages: + release_pages(pages, pinned); + up_read(&mm->mmap_sem); + return r; +} +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ +#endif /* CONFIG_DRM_AMDGPU_USERPTR */ + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. * @@ -830,6 +928,52 @@ void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) ttm->pages[i] = pages ? pages[i] : NULL; } +#else +/** + * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. + * + * Called by amdgpu_cs_list_validate(). This creates the page list + * that backs user memory and will ultimately be mapped into the device + * address space. + */ +void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + unsigned i; + + gtt->last_set_pages = atomic_read(>t->mmu_invalidations); + for (i = 0; i < ttm->num_pages; ++i) { + if (ttm->pages[i]) + put_page(ttm->pages[i]); + + ttm->pages[i] = pages ? pages[i] : NULL; + } +} + +/** + * amdgpu_ttm_tt_mark_user_page - Mark pages as dirty + * + * Called while unpinning userptr pages + */ +void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + unsigned i; + + for (i = 0; i < ttm->num_pages; ++i) { + struct page *page = ttm->pages[i]; + + if (!page) + continue; + + if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) + set_page_dirty(page); + + mark_page_accessed(page); + } +} +#endif + /* * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages * @@ -889,7 +1033,15 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, /* unmap the pages mapped to the device */ dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED sg_free_table(ttm->sg); +#else + /* mark the pages as dirty */ + amdgpu_ttm_tt_mark_user_pages(ttm); + + sg_free_table(ttm->sg); +#endif } /* @@ -1305,6 +1457,13 @@ int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, gtt->usertask = current->group_leader; get_task_struct(gtt->usertask); +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + spin_lock_init(>t->guptasklock); + INIT_LIST_HEAD(>t->guptasks); + atomic_set(>t->mmu_invalidations, 0); + gtt->last_set_pages = 0; +#endif + return 0; } @@ -1324,6 +1483,7 @@ struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) return gtt->usertask->mm; } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an * address range for the current task. @@ -1363,6 +1523,74 @@ bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) return true; } +#else +/* + * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an + * address range for the current task. + * + */ +bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, + unsigned long end) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + struct amdgpu_ttm_gup_task_list *entry; + unsigned long size; + + if (gtt == NULL || !gtt->userptr) + return false; + + /* Return false if no part of the ttm_tt object lies within + * the range + */ + size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; + if (gtt->userptr > end || gtt->userptr + size <= start) + return false; + + /* Search the lists of tasks that hold this mapping and see + * if current is one of them. If it is return false. + */ + spin_lock(>t->guptasklock); + list_for_each_entry(entry, >t->guptasks, list) { + if (entry->task == current) { + spin_unlock(>t->guptasklock); + return false; + } + } + spin_unlock(>t->guptasklock); + + atomic_inc(>t->mmu_invalidations); + + return true; +} + +/** + * amdgpu_ttm_tt_userptr_invalidated - Has the ttm_tt object been invalidated? + */ +bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, + int *last_invalidated) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + int prev_invalidated = *last_invalidated; + + *last_invalidated = atomic_read(>t->mmu_invalidations); + return prev_invalidated != *last_invalidated; +} + +/** + * amdgpu_ttm_tt_userptr_needs_pages - Have the pages backing this ttm_tt object + * been invalidated since the last time they've been set? + */ +bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + + if (gtt == NULL || !gtt->userptr) + return false; + + return atomic_read(>t->mmu_invalidations) != gtt->last_set_pages; +} +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ + /* * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 188b0c31e51ac..3b07e86e4beca 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -233,9 +233,14 @@ bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, unsigned long end, unsigned long *userptr); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED +bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm); +#else bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, int *last_invalidated); -bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm); +void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm); +bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm); +#endif bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem); uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 new file mode 100644 index 0000000000000..5cda4aed70d25 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -0,0 +1,35 @@ +dnl # +dnl # 93f4e735b6d9 - mm/hmm: remove hmm_range_dma_map and hmm_range_dma_unmap 2019-11-23 19:56:45 -0400 +dnl # d28c2c9a4877 - mm/hmm: make full use of walk_page_range() 2019-11-23 19:56:45 -0400 +dnl # d3eeb1d77c5d - xen/gntdev: use mmu_interval_notifier_insert 2019-11-23 19:56:45 -0400 +dnl # a22dd506400d - mm/hmm: remove hmm_mirror and related 2019-11-23 19:56:45 -0400 +dnl # 81fa1af31b5d - drm/amdgpu: Use mmu_interval_notifier instead of hmm_mirror 2019-11-23 19:56:45 -0400 +dnl # 62914a99dee5 - drm/amdgpu: Use mmu_interval_insert instead of hmm_mirror 2019-11-23 19:56:45 -0400 +dnl # a9ae8731e6e5 - drm/amdgpu: Call find_vma under mmap_sem 2019-11-23 19:56:44 -0400 +dnl # 20fef4ef84bf - nouveau: use mmu_interval_notifier instead of hmm_mirror 2019-11-23 19:56:44 -0400 +dnl # c625c274ee00 - nouveau: use mmu_notifier directly for invalidate_range_start 2019-11-23 19:56:44 -0400 +dnl # 3506ff69c3ec - drm/radeon: use mmu_interval_notifier_insert 2019-11-23 19:56:44 -0400 +dnl # 3889551db212 - RDMA/hfi1: Use mmu_interval_notifier_insert for user_exp_rcv 2019-11-23 19:56:44 -0400 +dnl # f25a546e6529 - RDMA/odp: Use mmu_interval_notifier_insert() 2019-11-23 19:56:44 -0400 +dnl # 107e899874e9 - mm/hmm: define the pre-processor related parts of hmm.h even if disabled 2019-11-23 19:56:44 -0400 +dnl # v5.4-rc5-20-g04ec32fbc2b2 - mm/hmm: allow hmm_range to be used with a mmu_interval_notifier or hmm_mirror 2019-11-23 19:56:44 -0400 +dnl # 99cb252f5e68 - mm/mmu_notifier: add an interval tree notifier 2019-11-23 19:56:44 -0400 +dnl # 56f434f40f05 - mm/mmu_notifier: define the header pre-processor parts even if disabled 2019-11-12 20:18:27 -0400 +dnl # +AC_DEFUN([AC_AMDGPU_HMM], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + #ifdef CONFIG_HMM_MIRROR + struct hmm_range *range = NULL; + range->notifier = NULL; + #else + #error CONFIG_HMM_MIRROR not enabled + #endif + ], [ + AC_DEFINE(HAVE_AMDKCL_HMM_MIRROR_ENABLED, 1, + [hmm support is enabled]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fb0d821b0cd44..03ac52d726852 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -53,6 +53,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TTM_SG_TT_INIT AC_AMDGPU_TTM_BUFFER_OBJECT AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION + AC_AMDGPU_HMM AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED From 860c0fe15bb13d91d755f66ed085516fc1bbf516 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 31 Aug 2020 15:42:28 +0800 Subject: [PATCH 0375/2653] drm/amdkcl: fake hmm_range_fault() protocol changed in v5.6-rc3-21-g6bfef2f91945("mm/hmm: remove HMM_FAULT_SNAPSHOT") Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 16 ++++++++++++++++ include/kcl/backport/kcl_hmm.h | 18 ++++++++++++++++++ 3 files changed, 35 insertions(+) create mode 100644 include/kcl/backport/kcl_hmm.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 60e80984d0d19..2cb3aae626abb 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -37,6 +37,7 @@ #include #include #include +#include #include #ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ #include diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 index 5cda4aed70d25..1e351ff9c3b3f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -1,3 +1,18 @@ +dnl # +dnl # v5.6-rc3-21-g6bfef2f91945 +dnl # mm/hmm: remove HMM_FAULT_SNAPSHOT +dnl # +AC_DEFUN([AC_AMDGPU_HMM_RANGE_FAULT], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + hmm_range_fault(NULL); + ], [ + AC_DEFINE(HAVE_HMM_RANGE_FAULT_1ARG, 1, + [hmm_range_fault() wants 1 arg]) + ]) +]) + dnl # dnl # 93f4e735b6d9 - mm/hmm: remove hmm_range_dma_map and hmm_range_dma_unmap 2019-11-23 19:56:45 -0400 dnl # d28c2c9a4877 - mm/hmm: make full use of walk_page_range() 2019-11-23 19:56:45 -0400 @@ -30,6 +45,7 @@ AC_DEFUN([AC_AMDGPU_HMM], [ ], [ AC_DEFINE(HAVE_AMDKCL_HMM_MIRROR_ENABLED, 1, [hmm support is enabled]) + AC_AMDGPU_HMM_RANGE_FAULT ]) ]) ]) diff --git a/include/kcl/backport/kcl_hmm.h b/include/kcl/backport/kcl_hmm.h new file mode 100644 index 0000000000000..233b0cbda947a --- /dev/null +++ b/include/kcl/backport/kcl_hmm.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_BACKPORT_KCL_HMM_H +#define _KCL_BACKPORT_KCL_HMM_H + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED +#include + +#ifndef HAVE_HMM_RANGE_FAULT_1ARG +static inline +int _kcl_hmm_range_fault(struct hmm_range *range) +{ + return hmm_range_fault(range, 0); +} +#define hmm_range_fault _kcl_hmm_range_fault +#endif /* HAVE_HMM_RANGE_FAULT_1ARG */ + +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ +#endif From 43994a08cf2d19311072ba76a1211a45e6c61181 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 31 Aug 2020 16:06:54 +0800 Subject: [PATCH 0376/2653] drm/amdkcl: test whether hmm remove the customizable pfn format Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 21 +++++++++++++++++++- drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 26 +++++++++++++++++++++---- 2 files changed, 42 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 1608581792a68..0908d020ea0f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -743,6 +743,20 @@ struct amdgpu_ttm_tt { #ifdef CONFIG_DRM_AMDGPU_USERPTR #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT +/* flags used by HMM internal, not related to CPU/GPU PTE flags */ +static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = { + (1 << 0), /* HMM_PFN_VALID */ + (1 << 1), /* HMM_PFN_WRITE */ + 0 /* HMM_PFN_DEVICE_PRIVATE */ +}; + +static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { + 0xfffffffffffffffeUL, /* HMM_PFN_ERROR */ + 0, /* HMM_PFN_NONE */ + 0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */ +}; +#endif /* * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user * memory and start HMM tracking CPU page table update @@ -826,7 +840,12 @@ bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", gtt->userptr, ttm->num_pages); - WARN_ONCE(!range->hmm_pfns, "No user pages to check\n"); +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + WARN_ONCE(!range->pfns, +#else + WARN_ONCE(!range->hmm_pfns, +#endif + "No user pages to check\n"); return !amdgpu_hmm_range_get_pages_done(range); } diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 index 1e351ff9c3b3f..228e66022b959 100644 --- a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -1,15 +1,33 @@ dnl # -dnl # v5.6-rc3-21-g6bfef2f91945 -dnl # mm/hmm: remove HMM_FAULT_SNAPSHOT +dnl # v5.7-rc4-4-g2733ea144dcc mm/hmm: remove the customizable pfn format from hmm_range_fault +dnl # v5.7-rc4-3-g5c8f3c4cf18a mm/hmm: remove HMM_PFN_SPECIAL +dnl # v5.7-rc4-2-g4e2490843d55 drm/amdgpu: remove dead code after hmm_range_fault() +dnl # v5.7-rc4-1-gbe957c886d92 mm/hmm: make hmm_range_fault return 0 or -1 dnl # AC_DEFUN([AC_AMDGPU_HMM_RANGE_FAULT], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - hmm_range_fault(NULL); + enum hmm_pfn_flags flag; + flag = HMM_PFN_REQ_FAULT; ], [ + AC_DEFINE(HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT, 1, + [hmm remove the customizable pfn format]) AC_DEFINE(HAVE_HMM_RANGE_FAULT_1ARG, 1, - [hmm_range_fault() wants 1 arg]) + [hmm_range_fault() wants 1 arg]) + ], [ + dnl # + dnl # v5.6-rc3-21-g6bfef2f91945 + dnl # mm/hmm: remove HMM_FAULT_SNAPSHOT + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + hmm_range_fault(NULL);; + ], [ + AC_DEFINE(HAVE_HMM_RANGE_FAULT_1ARG, 1, + [hmm_range_fault() wants 1 arg]) + ]) ]) ]) From 25530ac5da91881067a535a690a4a5aa90f05179 Mon Sep 17 00:00:00 2001 From: chen gong Date: Fri, 3 May 2019 11:53:41 +0800 Subject: [PATCH 0377/2653] drm/amdkcl: Test whether invalidate_range_start() wants 2 args or 5 args Signed-off-by: chen gong Reviewed-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: fix invalidate_range_end() leverage HAVE_2ARGS_INVALIDATE_RANGE_START for invalidate_range_end() check Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 145 ++++++++++++++++++ .../drm/amd/dkms/m4/invalidate-range-start.m4 | 36 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 182 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/invalidate-range-start.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index fa888fbcb17ba..e75b0846faf94 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -172,6 +172,20 @@ void amdgpu_mn_unlock(struct amdgpu_mn *mn) up_write(&mn->lock); } +#if !defined(HAVE_5ARGS_INVALIDATE_RANGE_START) && !defined(HAVE_2ARGS_INVALIDATE_RANGE_START) +/** + * amdgpu_mn_read_lock - take the read side lock for this notifier + * + * @amn: our notifier + */ +static void amdgpu_mn_read_lock(struct amdgpu_mn *amn) +{ + mutex_lock(&amn->read_lock); + if (atomic_inc_return(&amn->recursion) == 1) + down_read_non_owner(&amn->lock); + mutex_unlock(&amn->read_lock); +} +#else /** * amdgpu_mn_read_lock - take the read side lock for this notifier * @@ -190,6 +204,7 @@ static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable) return 0; } +#endif /** * amdgpu_mn_read_unlock - drop the read side lock for this notifier @@ -233,6 +248,7 @@ static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node, } } +#if defined(HAVE_2ARGS_INVALIDATE_RANGE_START) /** * amdgpu_mn_invalidate_range_start_gfx - callback to notify about mm change * @@ -327,6 +343,129 @@ static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, return 0; } +#else + +/** + * amdgpu_mn_invalidate_range_start_gfx - callback to notify about mm change + * + * @mn: our notifier + * @mm: the mm this callback is about + * @start: start of updated range + * @end: end of updated range + * + * Block for operations on BOs to finish and mark pages as accessed and + * potentially dirty. + */ +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) +static int amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, + struct mm_struct *mm, + unsigned long start, + unsigned long end, + bool blockable) +#else +static void amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, + struct mm_struct *mm, + unsigned long start, + unsigned long end) +#endif +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + struct interval_tree_node *it; + + /* notification is exclusive, but interval is inclusive */ + end -= 1; + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + if (amdgpu_mn_read_lock(amn, blockable)) + return -EAGAIN; +#else + amdgpu_mn_read_lock(amn); +#endif + + it = interval_tree_iter_first(&amn->objects, start, end); + while (it) { + struct amdgpu_mn_node *node; + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + if (!blockable) { + amdgpu_mn_read_unlock(amn); + return -EAGAIN; + } +#endif + + node = container_of(it, struct amdgpu_mn_node, it); + it = interval_tree_iter_next(it, start, end); + + amdgpu_mn_invalidate_node(node, start, end); + } +} + + +/** + * amdgpu_mn_invalidate_range_start_hsa - callback to notify about mm change + * + * @mn: our notifier + * @mm: the mm this callback is about + * @start: start of updated range + * @end: end of updated range + * + * We temporarily evict all BOs between start and end. This + * necessitates evicting all user-mode queues of the process. The BOs + * are restorted in amdgpu_mn_invalidate_range_end_hsa. + */ +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) +static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, + struct mm_struct *mm, + unsigned long start, + unsigned long end, + bool blockable) +#else +static void amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, + struct mm_struct *mm, + unsigned long start, + unsigned long end) +#endif +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + struct interval_tree_node *it; + + /* notification is exclusive, but interval is inclusive */ + end -= 1; + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + if (amdgpu_mn_read_lock(amn, blockable)) + return -EAGAIN; +#else + amdgpu_mn_read_lock(amn); +#endif + + it = interval_tree_iter_first(&amn->objects, start, end); + while (it) { + struct amdgpu_mn_node *node; + struct amdgpu_bo *bo; + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + if (!blockable) { + amdgpu_mn_read_unlock(amn); + return -EAGAIN; + } +#endif + + node = container_of(it, struct amdgpu_mn_node, it); + it = interval_tree_iter_next(it, start, end); + + list_for_each_entry(bo, &node->bos, mn_list) { + struct kgd_mem *mem = bo->kfd_bo; + + if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, + start, end)) + amdgpu_amdkfd_evict_userptr(mem, mm); + } + } +} + +#endif + /** * amdgpu_mn_invalidate_range_end - callback to notify about mm change * @@ -338,7 +477,13 @@ static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, * Release the lock again to allow new command submissions. */ static void amdgpu_mn_invalidate_range_end(struct mmu_notifier *mn, +#ifdef HAVE_2ARGS_INVALIDATE_RANGE_START const struct mmu_notifier_range *range) +#else + struct mm_struct *mm, + unsigned long start, + unsigned long end) +#endif { struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); diff --git a/drivers/gpu/drm/amd/dkms/m4/invalidate-range-start.m4 b/drivers/gpu/drm/amd/dkms/m4/invalidate-range-start.m4 new file mode 100644 index 0000000000000..d9edaefbebdcf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/invalidate-range-start.m4 @@ -0,0 +1,36 @@ +dnl # +dnl # commit 5d6527a784f7a6d247961e046e830de8d71b47d1 +dnl # Author: Jérôme Glisse +dnl # Date: Fri Dec 28 00:38:05 2018 -0800 +dnl # mm/mmu_notifier: use structure for invalidate_range_start/end callback +dnl # Patch series "mmu notifier contextual informations", v2. +dnl # +AC_DEFUN([AC_AMDGPU_INVALIDATE_RANGE_START], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct mmu_notifier_ops *ops = NULL; + ops->invalidate_range_start(NULL, NULL); + ], [ + AC_DEFINE(HAVE_2ARGS_INVALIDATE_RANGE_START, 1, + whether invalidate_range_start() wants 2 args) + ], [ + dnl # + dnl # commit 93065ac753e4443840a057bfef4be71ec766fde9 + dnl # Author: Michal Hocko + dnl # Date: Tue Aug 21 21:52:33 2018 -0700 + dnl # mm, oom: distinguish blockable mode for mmu notifiers + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct mmu_notifier_ops *ops = NULL; + ops->invalidate_range_start(NULL, NULL, 1, 1, 1); + ], [ + AC_DEFINE(HAVE_5ARGS_INVALIDATE_RANGE_START, 1, + whether invalidate_range_start() wants 5 args) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 03ac52d726852..30b3015080a74 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -54,6 +54,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TTM_BUFFER_OBJECT AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION AC_AMDGPU_HMM + AC_AMDGPU_INVALIDATE_RANGE_START AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED From 8327a82ea1dd5bb3ae15070b5e001c74f91fce7c Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Wed, 28 Aug 2019 11:21:44 +0800 Subject: [PATCH 0378/2653] drm/amdkcl: Test whether down_write_killable() is available (v2) down_write_killable() introduced by kernel v4.7-rc1~192^2~3 v2: typo fixed, locking/rwsem.h --> locking/rwsem.c Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 4 ++++ .../gpu/drm/amd/dkms/m4/down-write-killable.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 22 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/down-write-killable.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index e75b0846faf94..9af6fd2c51641 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -526,10 +526,14 @@ struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, int r; mutex_lock(&adev->mn_lock); +#ifndef HAVE_DOWN_WRITE_KILLABLE + down_write(&mm->mmap_sem); +#else if (down_write_killable(&mm->mmap_sem)) { mutex_unlock(&adev->mn_lock); return ERR_PTR(-EINTR); } +#endif hash_for_each_possible(adev->mn_hash, amn, node, key) if (AMDGPU_MN_KEY(amn->mm, amn->type) == key) diff --git a/drivers/gpu/drm/amd/dkms/m4/down-write-killable.m4 b/drivers/gpu/drm/amd/dkms/m4/down-write-killable.m4 new file mode 100644 index 0000000000000..c048731800f48 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/down-write-killable.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 916633a403702549d37ea353e63a68e5b0dc27ad +dnl # locking/rwsem: Provide down_write_killable() +dnl # +AC_DEFUN([AC_AMDGPU_DOWN_WRITE_KILLABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + int ret; + ret = down_write_killable(NULL); + ], [down_write_killable],[kernel/locking/rwsem.c],[ + AC_DEFINE(HAVE_DOWN_WRITE_KILLABLE, 1, + [down_write_killable() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 30b3015080a74..d7b14b013eeba 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -55,6 +55,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION AC_AMDGPU_HMM AC_AMDGPU_INVALIDATE_RANGE_START + AC_AMDGPU_DOWN_WRITE_KILLABLE AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED From 52cd359dbb57e957aa1b1bf88b19e9550b6e05e1 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Thu, 12 Dec 2019 10:04:29 -0500 Subject: [PATCH 0379/2653] drm/amdkcl: add return value for amdgpu_mn_invalidate_range_start_gfx Otherwise it returns random value and generates below kernel warning. The return value is ignored by the calling function, this will just remove the warnings, no function change. v2: add return value for amdgpu_mn_invalidate_range_start_hsa Dec 9 10:08:33 debian-rocm kernel: [ 883.795760] amdgpu_mn_invalidate_range_start_hsa+0x0/0x100 [amdgpu] callback failed with 226470832 in blockable context. Dec 9 10:08:33 debian-rocm kernel: [ 883.805443] amdgpu_mn_invalidate_range_start_hsa+0x0/0x100 [amdgpu] callback failed with 226470832 in blockable context. Change-Id: I2ad1c8703c4d4ec615ccdd5d402dd2ccdf08136b Signed-off-by: Philip Yang Reviewed-by: Eric Huang Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 9af6fd2c51641..41fc2d09d7b0f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -398,6 +398,10 @@ static void amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, amdgpu_mn_invalidate_node(node, start, end); } + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + return 0; +#endif } @@ -462,6 +466,10 @@ static void amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, amdgpu_amdkfd_evict_userptr(mem, mm); } } + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + return 0; +#endif } #endif From 533d9f594dc07cd713846e2b2e4111ae29594d21 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 6 Aug 2019 20:15:47 -0300 Subject: [PATCH 0380/2653] drm/amdkcl: Test whether mmu_notifier_synchronize is available introduced by kernel v5.3-rc1-29-g2c7933f53f6b Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: I0a46e15c16ec5d3e79687a1a33e50069ba956244 --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 +++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 21 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/mmu-notifier-synchronize.m4 | 31 +++++++++++++++++++ 5 files changed, 60 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mmu-notifier-synchronize.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index f18952ecbf327..422d3b3e9dab2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3276,7 +3276,9 @@ static void __exit amdgpu_exit(void) amdgpu_acpi_release(); amdgpu_sync_fini(); amdgpu_userq_fence_slab_fini(); +#ifdef HAVE_MMU_NOTIFIER_SYNCHRONIZE mmu_notifier_synchronize(); +#endif amdgpu_xcp_drv_release(); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 5719742b98d1a..57da7d05ab543 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -961,6 +961,11 @@ struct kfd_process { /* We want to receive a notification when the mm_struct is destroyed */ struct mmu_notifier mmu_notifier; +#ifndef HAVE_MMU_NOTIFIER_SYNCHRONIZE + /* Use for delayed freeing of kfd_process structure */ + struct rcu_head rcu; +#endif + /* * Array of kfd_process_device pointers, * one for each device the process is using. diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index bc8cf2190e44e..2245a5a4d80ae 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1209,6 +1209,7 @@ static void kfd_process_ref_release(struct kref *ref) queue_work(kfd_process_wq, &p->release_work); } +#ifdef HAVE_MMU_NOTIFIER_SYNCHRONIZE static struct mmu_notifier *kfd_process_alloc_notifier(struct mm_struct *mm) { /* This increments p->ref counter if kfd process p exists */ @@ -1221,6 +1222,14 @@ static void kfd_process_free_notifier(struct mmu_notifier *mn) { kfd_unref_process(container_of(mn, struct kfd_process, mmu_notifier)); } +#else +static void kfd_process_destroy_delayed(struct rcu_head *rcu) +{ + struct kfd_process *p = container_of(rcu, struct kfd_process, rcu); + + kfd_unref_process(p); +} +#endif static void kfd_process_notifier_release_internal(struct kfd_process *p) { @@ -1296,8 +1305,10 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn, static const struct mmu_notifier_ops kfd_process_mmu_notifier_ops = { .release = kfd_process_notifier_release, +#ifdef HAVE_MMU_NOTIFIER_SYNCHRONIZE .alloc_notifier = kfd_process_alloc_notifier, .free_notifier = kfd_process_free_notifier, +#endif }; /* @@ -1518,7 +1529,9 @@ void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, static struct kfd_process *create_process(const struct task_struct *thread) { struct kfd_process *process; +#ifdef HAVE_MMU_NOTIFIER_PUT struct mmu_notifier *mn; +#endif int err = -ENOMEM; process = kzalloc(sizeof(*process), GFP_KERNEL); @@ -1569,6 +1582,7 @@ static struct kfd_process *create_process(const struct task_struct *thread) */ kref_get(&process->ref); +#ifdef HAVE_MMU_NOTIFIER_PUT /* MMU notifier registration must be the last call that can fail * because after this point we cannot unwind the process creation. * After this point, mmu_notifier_put will trigger the cleanup by @@ -1580,6 +1594,13 @@ static struct kfd_process *create_process(const struct task_struct *thread) goto err_register_notifier; } BUG_ON(mn != &process->mmu_notifier); +#else + /* Must be last, have to use release destruction after this */ + process->mmu_notifier.ops = &kfd_process_mmu_notifier_ops; + err = mmu_notifier_register(&process->mmu_notifier, process->mm); + if (err) + goto err_register_notifier; +#endif kfd_unref_process(process); get_task_struct(process->lead_thread); diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d7b14b013eeba..91bf4a783ef20 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -44,6 +44,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMF_INSERT_PFN_PROT AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT AC_AMDGPU_MMU_NOTIFIER + AC_AMDGPU_MMU_NOTIFIER_SYNCHRONIZE AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_SCHED_SET_FIFO_LOW diff --git a/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-synchronize.m4 b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-synchronize.m4 new file mode 100644 index 0000000000000..a5e8dcde897ff --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-synchronize.m4 @@ -0,0 +1,31 @@ +dnl # +dnl # commit v5.3-rc1-29-g2c7933f53f6b +dnl # mm/mmu_notifiers: add a get/put scheme for the registration +dnl # +dnl # amdkcl: mmu_notifier_put() & mmu_notifier_synchronize() is +dnl # introduced in the same commit, yet rhel7.7 has different behavior +dnl # +AC_DEFUN([AC_AMDGPU_MMU_NOTIFIER_PUT], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + mmu_notifier_put(NULL); + ],[ + AC_DEFINE(HAVE_MMU_NOTIFIER_PUT, 1, + [mmu_notifier_put() is available]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_MMU_NOTIFIER_SYNCHRONIZE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + mmu_notifier_synchronize(); + ],[ + AC_DEFINE(HAVE_MMU_NOTIFIER_SYNCHRONIZE, 1, + [mmu_notifier_synchronize() is available]) + ]) + AC_AMDGPU_MMU_NOTIFIER_PUT + ]) +]) From 8d4a86aba22d14d1e682ba05a6d70ecf3ab21916 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 6 Dec 2019 22:15:18 +0800 Subject: [PATCH 0381/2653] drm/amdkcl: Test whether mmu_notifier_put is available Change-Id: I6a1119a60093799f5560d72ea00b8bf44bc2b773 Signed-off-by: Flora Cui Signed-off-by: Jack.Gui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 57da7d05ab543..1a38673cdf9ef 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -961,7 +961,7 @@ struct kfd_process { /* We want to receive a notification when the mm_struct is destroyed */ struct mmu_notifier mmu_notifier; -#ifndef HAVE_MMU_NOTIFIER_SYNCHRONIZE +#ifndef HAVE_MMU_NOTIFIER_PUT /* Use for delayed freeing of kfd_process structure */ struct rcu_head rcu; #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 2245a5a4d80ae..132649092161f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1209,7 +1209,7 @@ static void kfd_process_ref_release(struct kref *ref) queue_work(kfd_process_wq, &p->release_work); } -#ifdef HAVE_MMU_NOTIFIER_SYNCHRONIZE +#ifdef HAVE_MMU_NOTIFIER_PUT static struct mmu_notifier *kfd_process_alloc_notifier(struct mm_struct *mm) { /* This increments p->ref counter if kfd process p exists */ @@ -1305,7 +1305,7 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn, static const struct mmu_notifier_ops kfd_process_mmu_notifier_ops = { .release = kfd_process_notifier_release, -#ifdef HAVE_MMU_NOTIFIER_SYNCHRONIZE +#ifdef HAVE_MMU_NOTIFIER_PUT .alloc_notifier = kfd_process_alloc_notifier, .free_notifier = kfd_process_free_notifier, #endif From 6b5d3ba5e83c838c0ec61dead9522c6d8f38a5c7 Mon Sep 17 00:00:00 2001 From: changzhu Date: Sun, 18 Aug 2019 19:17:39 +0800 Subject: [PATCH 0382/2653] drm/amdkcl: Test whether struct rb_root_cached is defined Signed-off-by: changzhu Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: fix the dkms install failure in SLED15.1 use interval_tree_insert to judge rb_root_cached Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 12 ++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 12 ++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 ++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 ++++ .../drm/amd/dkms/m4/interval-tree-insert.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 6 files changed, 51 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/interval-tree-insert.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 41fc2d09d7b0f..78a5f32697202 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -83,7 +83,11 @@ struct amdgpu_mn { /* objects protected by lock */ struct rw_semaphore lock; +#ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED + struct rb_root objects; +#else struct rb_root_cached objects; +#endif struct mutex read_lock; atomic_t recursion; }; @@ -119,7 +123,11 @@ static void amdgpu_mn_destroy(struct work_struct *work) down_write(&amn->lock); hash_del(&amn->node); rbtree_postorder_for_each_entry_safe(node, next_node, +#ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED + &amn->objects, it.rb) { +#else &amn->objects.rb_root, it.rb) { +#endif list_for_each_entry_safe(bo, next_bo, &node->bos, mn_list) { bo->mn = NULL; list_del_init(&bo->mn_list); @@ -558,7 +566,11 @@ struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, init_rwsem(&amn->lock); amn->type = type; amn->mn.ops = &amdgpu_mn_ops[type]; +#ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED + amn->objects = RB_ROOT; +#else amn->objects = RB_ROOT_CACHED; +#endif mutex_init(&amn->read_lock); atomic_set(&amn->recursion, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 72c0b696c389e..baa30ffe158ed 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2560,7 +2560,11 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct amdgpu_bo_vm *root; int r, i; +#ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED + vm->va = RB_ROOT; +#else vm->va = RB_ROOT_CACHED; +#endif for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) vm->reserved_vmid[i] = NULL; INIT_LIST_HEAD(&vm->evicted); @@ -2767,11 +2771,19 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) amdgpu_vm_fini_entities(vm); +#ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED + if (!RB_EMPTY_ROOT(&vm->va)) { +#else if (!RB_EMPTY_ROOT(&vm->va.rb_root)) { +#endif dev_err(adev->dev, "still active bo inside vm\n"); } rbtree_postorder_for_each_entry_safe(mapping, tmp, +#ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED + &vm->va, rb) { +#else &vm->va.rb_root, rb) { +#endif /* Don't remove the mapping here, we don't want to trigger a * rebalance and the tree is about to be destroyed anyway. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 3b4fa3246675f..607e352bc780e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -334,7 +334,11 @@ struct amdgpu_mem_stats { struct amdgpu_vm { /* tree of virtual addresses mapped */ +#ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED + struct rb_root va; +#else struct rb_root_cached va; +#endif /* Lock to prevent eviction while we are updating page tables * use vm_eviction_lock/unlock(vm) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 1a38673cdf9ef..6b478bdaa3e5c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -989,7 +989,11 @@ struct kfd_process { size_t signal_event_count; bool signal_event_limit_reached; +#ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED + struct rb_root bo_interval_tree; +#else struct rb_root_cached bo_interval_tree; +#endif /* Information used for memory eviction */ void *kgd_process_info; diff --git a/drivers/gpu/drm/amd/dkms/m4/interval-tree-insert.m4 b/drivers/gpu/drm/amd/dkms/m4/interval-tree-insert.m4 new file mode 100644 index 0000000000000..52baac13d3460 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/interval-tree-insert.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit f808c13fd3738948e10196496959871130612b61 +dnl # lib/interval_tree: fast overlap detection +dnl # +AC_DEFUN([AC_AMDGPU_INTERVAL_TREE_INSERT_HAVE_RB_ROOT_CACHED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct rb_root_cached *r = NULL; + interval_tree_insert(NULL, r); + ],[ + AC_DEFINE(HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED, 1, + [interval_tree_insert have struct rb_root_cached]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 91bf4a783ef20..f3164aeaacda2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -57,6 +57,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_HMM AC_AMDGPU_INVALIDATE_RANGE_START AC_AMDGPU_DOWN_WRITE_KILLABLE + AC_AMDGPU_INTERVAL_TREE_INSERT_HAVE_RB_ROOT_CACHED AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED From 090acbb5c25fe2f7c35e0c9ed2af084108ab8262 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 1 Sep 2020 11:19:53 +0800 Subject: [PATCH 0383/2653] drm/amdkcl: Test whether get_user_{pages/pages_remote}() wants {5/6,8} args v2: rework get_user_pages() & get_user_pages_remote() test v3: adapt to get_user_pages_remote() prototype change (drop task_struct) Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Reviewed-by: Jack Gui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +- .../drm/amd/dkms/m4/get-user-pages-remote.m4 | 53 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 | 30 +++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 + include/kcl/backport/kcl_mm_backport.h | 45 ++++++++++++++++ 5 files changed, 132 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 0908d020ea0f9..4e94626c3d732 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -906,7 +906,8 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) if (mm == current->mm) r = get_user_pages(userptr, num_pages, flags, p, NULL); else - r = get_user_pages_remote(mm, userptr, num_pages, + r = kcl_get_user_pages_remote(gtt->usertask, + mm, userptr, num_pages, flags, p, NULL, NULL); spin_lock(>t->guptasklock); diff --git a/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 new file mode 100644 index 0000000000000..8f70124da00f0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 @@ -0,0 +1,53 @@ +AC_DEFUN([AC_AMDGPU_GET_USER_PAGES_REMOTE], [ + AC_KERNEL_DO_BACKGROUND([ + dnl # + dnl # v4.5-rc4-71-g1e9877902dc7 + dnl # mm/gup: Introduce get_user_pages_remote() + dnl # + AC_KERNEL_CHECK_SYMBOL_EXPORT([get_user_pages_remote],[mm/gup.c], + [ + dnl # + dnl # v5.8-12463-g64019a2e467a + dnl # mm/gup: remove task_struct pointer for all gup code + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + get_user_pages_remote(NULL, 0, 0, 0, NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT, 1, + [get_user_pages_remote() remove task_struct pointer]) + ], [ + dnl # + dnl # commit v4.9-7744-g5b56d49fc31d + dnl # mm: add locked parameter to get_user_pages_remote() + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_LOCKED, 1, + [get_user_pages_remote() wants locked parameter]) + ], [ + dnl # + dnl # commit v4.8-14096-g9beae1ea8930 + dnl # mm: replace get_user_pages_remote() write/force parameters + dnl # with gup_flags + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL); + ], [ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS, 1, + [get_user_pages_remote() wants gup_flags parameter]) + ],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED, 1, + [get_user_pages_remote() is introduced with initial prototype]) + ]) + ]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 b/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 new file mode 100644 index 0000000000000..7f9931fdf453f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 @@ -0,0 +1,30 @@ +dnl # +dnl # commit v4.8-14095-g768ae309a961 +dnl # mm: replace get_user_pages() write/force parameters with gup_flags +dnl # +AC_DEFUN([AC_AMDGPU_GET_USER_PAGES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages(0, 0, 0, NULL, NULL); + ], [get_user_pages], [mm/gup.c], [ + AC_DEFINE(HAVE_GET_USER_PAGES_GUP_FLAGS, 1, + [get_user_pages() wants gup_flags parameter]) + ], [ + dnl # + dnl # commit v4.6-rc2-1-gc12d2da56d0e + dnl # mm/gup: Remove the macro overload API migration helpers + dnl # from the get_user*() APIs + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages(0, 0, 0, 0, NULL, NULL); + ], [get_user_pages], [mm/gup.c], [ + AC_DEFINE(HAVE_GET_USER_PAGES_6ARGS, 1, + [get_user_pages() wants 6 args]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f3164aeaacda2..d429786636e2f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -58,6 +58,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_INVALIDATE_RANGE_START AC_AMDGPU_DOWN_WRITE_KILLABLE AC_AMDGPU_INTERVAL_TREE_INSERT_HAVE_RB_ROOT_CACHED + AC_AMDGPU_GET_USER_PAGES_REMOTE + AC_AMDGPU_GET_USER_PAGES AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED diff --git a/include/kcl/backport/kcl_mm_backport.h b/include/kcl/backport/kcl_mm_backport.h index 055945c8728ef..3fc317a922a8d 100644 --- a/include/kcl/backport/kcl_mm_backport.h +++ b/include/kcl/backport/kcl_mm_backport.h @@ -5,4 +5,49 @@ #include #include +#ifdef get_user_pages_remote +#undef get_user_pages_remote +#endif +#ifdef get_user_pages +#undef get_user_pages +#endif + +static inline +long kcl_get_user_pages_remote(struct task_struct *tsk, struct mm_struct *mm, + unsigned long start, unsigned long nr_pages, + unsigned int gup_flags, struct page **pages, + struct vm_area_struct **vmas, int *locked) +{ +#if defined(HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT) + return get_user_pages_remote(mm, start, nr_pages, gup_flags, pages, vmas, locked); +#elif defined(HAVE_GET_USER_PAGES_REMOTE_LOCKED) + return get_user_pages_remote(tsk, mm, start, nr_pages, gup_flags, pages, vmas, locked); +#elif defined(HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS) + return get_user_pages_remote(tsk, mm, start, nr_pages, gup_flags, pages, vmas); +#elif defined(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED) + return get_user_pages_remote(tsk, mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), + !!(gup_flags & FOLL_FORCE), pages, vmas); +#else + return get_user_pages(tsk, mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), + !!(gup_flags & FOLL_FORCE), pages, vmas); +#endif +} + +#ifndef HAVE_GET_USER_PAGES_GUP_FLAGS +static inline +long _kcl_get_user_pages(unsigned long start, unsigned long nr_pages, + unsigned int gup_flags, struct page **pages, + struct vm_area_struct **vmas) +{ +#if defined(HAVE_GET_USER_PAGES_6ARGS) + return get_user_pages(start, nr_pages, !!(gup_flags & FOLL_WRITE), + !!(gup_flags & FOLL_FORCE), pages, vmas); +#else + return get_user_pages(current, current->mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), + !!(gup_flags & FOLL_FORCE), pages, vmas); +#endif +} +#define get_user_pages _kcl_get_user_pages +#endif /* HAVE_GET_USER_PAGES_GUP_FLAGS */ + #endif From aa50fe2212a602c437455e1bbdc2aaecd9af974d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sat, 18 Apr 2020 19:46:03 +0800 Subject: [PATCH 0384/2653] drm/amdkcl: workaroud for shared address space with dma bufs Signed-off-by: Flora Cui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 6 +++++- include/kcl/backport/kcl_drm_backport.h | 8 ++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 2c7f60a845010..8e1531e5328e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -526,10 +526,14 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, buf = drm_gem_prime_export(dev, gobj, flags); #endif + if (!IS_ERR(buf)) { +#ifdef AMDKCL_DMA_BUF_SHARE_ADDR_SPACE + buf->file->f_mapping = gobj->dev->anon_inode->i_mapping; +#endif #if defined(AMDKCL_AMDGPU_DMABUF_OPS) - if (!IS_ERR(buf)) buf->ops = &amdgpu_dmabuf_ops; #endif + } return buf; } diff --git a/include/kcl/backport/kcl_drm_backport.h b/include/kcl/backport/kcl_drm_backport.h index 84ca7b867d62d..668fa168e20bd 100644 --- a/include/kcl/backport/kcl_drm_backport.h +++ b/include/kcl/backport/kcl_drm_backport.h @@ -14,4 +14,12 @@ #define AMDKCL_AMDGPU_DMABUF_OPS #endif +/* + * commit v5.4-rc4-1120-gb3fac52c5193 + * drm: share address space for dma bufs + */ +#if DRM_VERSION_CODE < DRM_VERSION(5, 5, 0) +#define AMDKCL_DMA_BUF_SHARE_ADDR_SPACE +#endif + #endif/*AMDKCL_DRM_BACKPORT_H*/ From e0f76f6f92d153070caefd3f0284aa7afb48f73d Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Wed, 18 Sep 2019 16:50:24 +0800 Subject: [PATCH 0385/2653] drm/amdkcl: fix pr_fmt() macro is redefined warning Signed-off-by: Adam Yang Signed-off-by: Yifan Zhang --- drivers/gpu/drm/ttm/ttm_agp_backend.c | 3 +++ drivers/gpu/drm/ttm/ttm_bo.c | 3 +++ drivers/gpu/drm/ttm/ttm_bo_vm.c | 3 +++ drivers/gpu/drm/ttm/ttm_tt.c | 3 +++ 4 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_agp_backend.c b/drivers/gpu/drm/ttm/ttm_agp_backend.c index fca0a1a3c6fd3..dd86a462b2c2a 100644 --- a/drivers/gpu/drm/ttm/ttm_agp_backend.c +++ b/drivers/gpu/drm/ttm/ttm_agp_backend.c @@ -30,6 +30,9 @@ * Keith Packard. */ +#ifdef pr_fmt +#undef pr_fmt +#endif /* pr_fmt */ #define pr_fmt(fmt) "[TTM] " fmt #include diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 63b0733610d86..2221ed3e8b5d4 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -29,6 +29,9 @@ * Authors: Thomas Hellstrom */ +#ifdef pr_fmt +#undef pr_fmt +#endif /* pr_fmt */ #define pr_fmt(fmt) "[TTM] " fmt #include diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 068dac4f05d8d..9dcb96d473771 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -29,6 +29,9 @@ * Authors: Thomas Hellstrom */ +#ifdef pr_fmt +#undef pr_fmt +#endif /* pr_fmt */ #define pr_fmt(fmt) "[TTM] " fmt #include diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 7559139b73d19..dd5aa65e080e3 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -29,6 +29,9 @@ * Authors: Thomas Hellstrom */ +#ifdef pr_fmt +#undef pr_fmt +#endif /* pr_fmt */ #define pr_fmt(fmt) "[TTM] " fmt #include From f072a842a32c7245e17b7db2c228be11fa7af0f2 Mon Sep 17 00:00:00 2001 From: Anatoli Antonovitch Date: Fri, 28 Jun 2019 15:41:36 -0400 Subject: [PATCH 0386/2653] drm/amdkcl: check whether pgprot_decrypted is available Change-Id: I55f9dd3b5b7bf756dd48f74810028c67855bec02 Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui --- drivers/gpu/drm/ttm/ttm_bo_vm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 9dcb96d473771..6f155a908a549 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -259,8 +259,10 @@ vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, return VM_FAULT_SIGBUS; } } else { +#ifdef pgprot_decrypted /* Iomem should not be marked encrypted */ prot = pgprot_decrypted(prot); +#endif } /* From fb3511396af28072fd4966de1196ab9c746b914c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 8 Sep 2020 12:45:50 +0800 Subject: [PATCH 0387/2653] drm/amdkcl: use wait_queue_head_t for backward compatibility Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h index 79bfd1d1871ac..5696dcb7f3be4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h @@ -25,7 +25,6 @@ /* * Debugfs */ - #if defined(CONFIG_DEBUG_FS) #if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) void amdgpu_debugfs_cleanup(struct drm_minor *minor); From 61cef7b25a02ea394857548a97097a689419b1f6 Mon Sep 17 00:00:00 2001 From: Anatoli Antonovitch Date: Mon, 28 Jan 2019 14:16:44 -0500 Subject: [PATCH 0388/2653] drm/amdkcl: Test whether wait_queue_entry_t exists v2: drm/amdkcl: drop kcl_wait.h Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Jiansong Chen Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkfd/kfd_events.c | 12 +++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/sched-list-for-each-entry.m4 | 21 +++++++++++++++++++ 3 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/sched-list-for-each-entry.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index 82905f3e54ddd..766b061d9fd98 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -38,7 +38,11 @@ * Wrapper around wait_queue_entry_t */ struct kfd_event_waiter { +#if defined(HAVE_WAIT_QUEUE_ENTRY) wait_queue_entry_t wait; +#else + wait_queue_t wait; +#endif struct kfd_event *event; /* Event to wait for */ bool activated; /* Becomes true when event is signaled */ bool event_age_enabled; /* set to true when last_event_age is non-zero */ @@ -265,7 +269,11 @@ static void destroy_event(struct kfd_process *p, struct kfd_event *ev) /* Wake up pending waiters. They will return failure */ spin_lock(&ev->lock); +#if !defined(HAVE_WAIT_QUEUE_ENTRY) + list_for_each_entry(waiter, &ev->wq.task_list, wait.task_list) +#else list_for_each_entry(waiter, &ev->wq.head, wait.entry) +#endif WRITE_ONCE(waiter->event, NULL); wake_up_all(&ev->wq); spin_unlock(&ev->lock); @@ -637,7 +645,11 @@ static void set_event(struct kfd_event *ev) WARN_ONCE(1, "event_age wrap back!"); } +#if !defined(HAVE_WAIT_QUEUE_ENTRY) + list_for_each_entry(waiter, &ev->wq.task_list, wait.task_list) +#else list_for_each_entry(waiter, &ev->wq.head, wait.entry) +#endif WRITE_ONCE(waiter->activated, true); wake_up_all(&ev->wq); diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d429786636e2f..e2d7596158067 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -61,6 +61,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_GET_USER_PAGES_REMOTE AC_AMDGPU_GET_USER_PAGES AC_AMDGPU_DMA_BUF + AC_AMDGPU_LIST_FOR_EACH_ENTRY AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED diff --git a/drivers/gpu/drm/amd/dkms/m4/sched-list-for-each-entry.m4 b/drivers/gpu/drm/amd/dkms/m4/sched-list-for-each-entry.m4 new file mode 100644 index 0000000000000..4f993d9da6fa3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/sched-list-for-each-entry.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # 4.13 API change +dnl # commit ac6424b981bce1c4bc55675c6ce11bfe1bbfa64f +dnl # Renamed wait_queue_head::task_list -> wait_queue_head::head +dnl # Renamed wait_queue_entry::task_list -> wait_queue_entry::entry +dnl # +AC_DEFUN([AC_AMDGPU_LIST_FOR_EACH_ENTRY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + wait_queue_entry_t *wq_entry = NULL; + wait_queue_head_t *wq_head = NULL; + + __add_wait_queue(wq_head, wq_entry); + ], [ + AC_DEFINE(HAVE_WAIT_QUEUE_ENTRY, 1, + [wait_queue_entry_t exists]) + ]) + ]) +]) From f465419fa8778290438fe565ecdced22c90fe194 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 13 Apr 2020 06:37:24 +0800 Subject: [PATCH 0389/2653] drm/amdkcl: Test whether struct i2c_lock_operations is defined void (*lock_bus)(struct i2c_adapter *, unsigned int flags); int (*trylock_bus)(struct i2c_adapter *, unsigned int flags); void (*unlock_bus)(struct i2c_adapter *, unsigned int flags); are not defined in struct i2c_adapter until the following patch: commit 8320f495cf441d593f7cd4f30e6b63455be71a2c Author: Peter Rosin Date: Wed May 4 22:15:27 2016 +0200 i2c: allow adapter drivers to override the adapter locking It's not defined until kernel version 4.7.0. So it's hard to support lock_bus,trylock_bus and unlock_bus on redhat 7.7 whose kernel version is 3.10.0. v2: 31fbd646eca3 drm/amdgpu: add lock for i2c bus (andrey.grodzovsky@amd.com) Signed-off-by: changzhu Reviewed-by: Adam Yang Signed-off-by: Jack Gui Signed-off-by: Slava Grigorev Signed-off-by: Andrey Grodzovsky Reviewed-by: Rui Teng --- drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 12 ++++++++++++ .../amd/dkms/m4/i2c-lock-operations-struct.m4 | 19 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 32 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/i2c-lock-operations-struct.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c index dd2d66090d237..2de46087444c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c +++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c @@ -636,17 +636,23 @@ static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) mutex_unlock(&smu_i2c->mutex); } +#if defined(HAVE_I2C_LOCK_OPERATIONS_STRUCT) static const struct i2c_lock_operations smu_v11_0_i2c_i2c_lock_ops = { .lock_bus = lock_bus, .trylock_bus = trylock_bus, .unlock_bus = unlock_bus, }; +#endif static int smu_v11_0_i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msg, int num) { int i, ret; u16 addr, dir; +#if !defined(HAVE_I2C_LOCK_OPERATIONS_STRUCT) + lock_bus(i2c_adap, 0); +#endif + smu_v11_0_i2c_init(i2c_adap); @@ -705,6 +711,10 @@ static int smu_v11_0_i2c_xfer(struct i2c_adapter *i2c_adap, } smu_v11_0_i2c_fini(i2c_adap); + +#if !defined(HAVE_I2C_LOCK_OPERATIONS_STRUCT) + unlock_bus(i2c_adap, 0); +#endif return num; } @@ -736,7 +746,9 @@ int smu_v11_0_i2c_control_init(struct amdgpu_device *adev) control->dev.parent = &adev->pdev->dev; control->algo = &smu_v11_0_i2c_algo; snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0"); +#if defined(HAVE_I2C_LOCK_OPERATIONS_STRUCT) control->lock_ops = &smu_v11_0_i2c_i2c_lock_ops; +#endif control->quirks = &smu_v11_0_i2c_control_quirks; i2c_set_adapdata(control, smu_i2c); diff --git a/drivers/gpu/drm/amd/dkms/m4/i2c-lock-operations-struct.m4 b/drivers/gpu/drm/amd/dkms/m4/i2c-lock-operations-struct.m4 new file mode 100644 index 0000000000000..c8655f6c15d91 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/i2c-lock-operations-struct.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit d1ed7985b9a6b85ea38a330108c51ec83381c01b +dnl # Author: Peter Rosin +dnl # Date: Thu Aug 25 23:07:01 2016 +0200 +dnl # i2c: move locking operations to their own structure +dnl # +AC_DEFUN([AC_AMDGPU_I2C_LOCK_OPERATIONS_STRUCT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct i2c_lock_operations drm_dp_i2c_lock_ops; + drm_dp_i2c_lock_ops.lock_bus = NULL; + ], [ + AC_DEFINE(HAVE_I2C_LOCK_OPERATIONS_STRUCT, 1, + [struct i2c_lock_operations is defined]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e2d7596158067..fa6ec45bc3f66 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -12,6 +12,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TYPE__POLL_T AC_AMDGPU_DMA_MAP_SGTABLE AC_AMDGPU_I2C_NEW_CLIENT_DEVICE + AC_AMDGPU_I2C_LOCK_OPERATIONS_STRUCT AC_AMDGPU_REQUEST_FIRMWARE_DIRECT AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS AC_AMDGPU_DEV_PM_SET_DRIVER_FLAGS From cf8b5e98d7910e3ccea4f2e49bc9a67c3944dbe5 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Mon, 22 Jul 2019 10:13:39 +0800 Subject: [PATCH 0390/2653] drm/amdkcl: Test whether timer_setup() is available test if timer_setup() is defined Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 14 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 | 16 ++++++++++++++++ 3 files changed, 31 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 16ca58d932da1..de549f5a4c31a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -291,6 +291,7 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring) * * Checks for fence activity. */ +#if defined(HAVE_TIMER_SETUP) static void amdgpu_fence_fallback(struct timer_list *t) { struct amdgpu_ring *ring = timer_container_of(ring, t, @@ -301,6 +302,14 @@ static void amdgpu_fence_fallback(struct timer_list *t) "Fence fallback timer expired on ring %s\n", ring->name); } +#else +static void amdgpu_fence_fallback(unsigned long arg) +{ + struct amdgpu_ring *ring = (void *)arg; + + amdgpu_fence_process(ring); +} +#endif /** * amdgpu_fence_wait_empty - wait for all fences to signal @@ -492,7 +501,12 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring) atomic_set(&ring->fence_drv.last_seq, 0); ring->fence_drv.initialized = false; +#if defined(HAVE_TIMER_SETUP) timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0); +#else + setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, + (unsigned long)ring); +#endif ring->fence_drv.num_fences_mask = ring->num_hw_submission * 2 - 1; spin_lock_init(&ring->fence_drv.lock); diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fa6ec45bc3f66..0412e760cb013 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -63,6 +63,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_GET_USER_PAGES AC_AMDGPU_DMA_BUF AC_AMDGPU_LIST_FOR_EACH_ENTRY + AC_AMDGPU_TIMER_SETUP AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED diff --git a/drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 b/drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 new file mode 100644 index 0000000000000..63a4498b7476a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # timer_setup is available +dnl # +dnl # +AC_DEFUN([AC_AMDGPU_TIMER_SETUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + timer_setup(NULL, NULL, 0); + ],[ + AC_DEFINE(HAVE_TIMER_SETUP, 1, + [timer_setup() is available]) + ]) + ]) +]) From c4ae9396f6cdac12b6fd9e625c999c045d33c8e7 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Fri, 9 Aug 2019 14:29:29 +0800 Subject: [PATCH 0391/2653] drm/amdkcl: Test whether amd_iommu_pc_supported is available (v2) amd_iommu_pc_xxx introduced by kernel v3.11-rc1~144^2~20 v2: fix typo and correct header file included Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amd/autoconf: fix missing HAVE_AMD_IOMMU_PC_SUPPORTED Signed-off-by: Flora Cui Reviewed-by: Jack Gui drm/amd/autoconf: fix missing HAVE_AMD_IOMMU_PC_SUPPORTED this break rhel7.6 Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amd/autoconf: check CONFIG_AMD_IOMMU enabled for amd_iommu_pc_* or else the symbols are missing. This is for in-tree build. Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui drm/amdkcl: Fix kfd_iommu dkms install error Issue introduced by commit: 4b38b7a521e3aa401f986483722154b3ba701538 Fix RHEL7.6 with 3.10 kernel kfd_iommu dkms install error some legacy kcl path miss replaced with autoconf macro Signed-off-by: Chengming Gui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 25 +++++++++++++++++-- drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 12 +++++++++ .../drm/amd/dkms/m4/amd-iommu-pc-supported.m4 | 18 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 54 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 18e098d043f1c..52a1f56804ed5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -115,7 +115,9 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) struct kfd_cache_properties *cache; struct kfd_iolink_properties *iolink; struct kfd_iolink_properties *p2plink; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties *perf; +#endif list_del(&dev->list); @@ -147,12 +149,14 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) kfree(p2plink); } +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED while (dev->perf_props.next != &dev->perf_props) { perf = container_of(dev->perf_props.next, struct kfd_perf_properties, list); list_del(&perf->list); kfree(perf); } +#endif kfree(dev); } @@ -189,7 +193,9 @@ struct kfd_topology_device *kfd_create_topology_device( INIT_LIST_HEAD(&dev->cache_props); INIT_LIST_HEAD(&dev->io_link_props); INIT_LIST_HEAD(&dev->p2p_link_props); +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED INIT_LIST_HEAD(&dev->perf_props); +#endif list_add_tail(&dev->list, device_list); @@ -383,6 +389,7 @@ static const struct kobj_type cache_type = { .sysfs_ops = &cache_ops, }; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED /****** Sysfs of Performance Counters ******/ struct kfd_perf_attr { @@ -416,6 +423,7 @@ static struct kfd_perf_attr perf_attr_iommu[] = { KFD_PERF_DESC(counter_ids, 0), }; /****************************************/ +#endif static ssize_t node_show(struct kobject *kobj, struct attribute *attr, char *buffer) @@ -577,7 +585,9 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) struct kfd_iolink_properties *iolink; struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties *perf; +#endif if (dev->kobj_p2plink) { list_for_each_entry(p2plink, &dev->p2p_link_props, list) @@ -643,6 +653,7 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) dev->kobj_mem = NULL; } +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED if (dev->kobj_perf) { list_for_each_entry(perf, &dev->perf_props, list) { kfree(perf->attr_group); @@ -652,6 +663,7 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) kobject_put(dev->kobj_perf); dev->kobj_perf = NULL; } +#endif if (dev->kobj_node) { sysfs_remove_file(dev->kobj_node, &dev->attr_gpuid); @@ -670,10 +682,13 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, struct kfd_iolink_properties *iolink; struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties *perf; - int ret; - uint32_t i, num_attrs; + uint32_t num_attrs; struct attribute **attrs; +#endif + int ret; + uint32_t i; if (WARN_ON(dev->kobj_node)) return -EEXIST; @@ -708,9 +723,11 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, if (!dev->kobj_p2plink) return -ENOMEM; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED dev->kobj_perf = kobject_create_and_add("perf", dev->kobj_node); if (!dev->kobj_perf) return -ENOMEM; +#endif /* * Creating sysfs files for node properties @@ -829,6 +846,7 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, i++; } +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED /* All hardware blocks have the same number of attributes. */ num_attrs = ARRAY_SIZE(perf_attr_iommu); list_for_each_entry(perf, &dev->perf_props, list) { @@ -854,6 +872,7 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, if (ret < 0) return ret; } +#endif return 0; } @@ -1081,8 +1100,10 @@ int kfd_topology_init(void) goto err; } +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED kdev = list_first_entry(&temp_topology_device_list, struct kfd_topology_device, list); +#endif down_write(&topology_lock); kfd_topology_update_device_list(&temp_topology_device_list, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index ab7a3bf1bdefe..b53fdf1f30f19 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -135,12 +135,14 @@ struct kfd_iolink_properties { struct attribute attr; }; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties { struct list_head list; char block_name[16]; uint32_t max_concurrent; struct attribute_group *attr_group; }; +#endif struct kfd_topology_device { struct list_head list; @@ -151,14 +153,18 @@ struct kfd_topology_device { struct list_head cache_props; struct list_head io_link_props; struct list_head p2p_link_props; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct list_head perf_props; +#endif struct kfd_node *gpu; struct kobject *kobj_node; struct kobject *kobj_mem; struct kobject *kobj_cache; struct kobject *kobj_iolink; struct kobject *kobj_p2plink; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kobject *kobj_perf; +#endif struct attribute attr_gpuid; struct attribute attr_name; struct attribute attr_props; @@ -202,4 +208,10 @@ struct kfd_topology_device *kfd_create_topology_device( struct list_head *device_list); void kfd_release_topology_device_list(struct list_head *device_list); +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED +extern bool amd_iommu_pc_supported(void); +extern u8 amd_iommu_pc_get_max_banks(u16 devid); +extern u8 amd_iommu_pc_get_max_counters(u16 devid); +#endif + #endif /* __KFD_TOPOLOGY_H__ */ diff --git a/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 b/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 new file mode 100644 index 0000000000000..27bed9e6beb3b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 30861ddc9cca479a7fc6a5efef4e5c69d6b274f4 +dnl # perf/x86/amd: Add IOMMU Performance Counter resource management +dnl # +AC_DEFUN([AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + #ifndef CONFIG_AMD_IOMMU + #error CONFIG_AMD_IOMMU not enabled + #endif + ], [amd_iommu_pc_supported], [drivers/iommu/amd_iommu_init.c], [ + AC_DEFINE(HAVE_AMD_IOMMU_PC_SUPPORTED, 1, + [amd_iommu_pc_supported() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0412e760cb013..dd18a255c52b9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -64,6 +64,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_BUF AC_AMDGPU_LIST_FOR_EACH_ENTRY AC_AMDGPU_TIMER_SETUP + AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED From e19b52b2852cfb91f175c870a8cb6dac7409bdfb Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 6 Nov 2019 15:53:10 +0800 Subject: [PATCH 0392/2653] drm/amdkcl: fix bridge_pm_usable v2: drm/amdkcl: add AMDKCL_PCIE_BRIDGE_PM_USABLE to be friendly for hybrid branch maintainer Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Flora Cui Acked-by: Feifei Xu Signed-off-by: Jack Gui --- .../gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 17 +++++++++++++++++ include/kcl/backport/kcl_pci_backport.h | 4 ++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c index 3893e6fc2f037..3353c78a258aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c @@ -44,7 +44,9 @@ struct amdgpu_atpx { static struct amdgpu_atpx_priv { bool atpx_detected; +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE bool bridge_pm_usable; +#endif unsigned int quirks; /* handle for device - and atpx */ acpi_handle dhandle; @@ -221,11 +223,18 @@ static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx) atpx->is_hybrid = false; } else { pr_notice("ATPX Hybrid Graphics\n"); +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE /* * Disable legacy PM methods only when pcie port PM is usable, * otherwise the device might fail to power off or power on. */ atpx->functions.power_cntl = !amdgpu_atpx_priv.bridge_pm_usable; +#else + /* + * This is a temporary hack for the kernel doesn't support D3. + */ + atpx->functions.power_cntl = true; +#endif atpx->is_hybrid = true; } } @@ -604,16 +613,20 @@ static bool amdgpu_atpx_detect(void) struct pci_dev *pdev = NULL; bool has_atpx = false; int vga_count = 0; +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE bool d3_supported = false; struct pci_dev *parent_pdev; +#endif while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { vga_count++; has_atpx |= amdgpu_atpx_pci_probe_handle(pdev); +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE parent_pdev = pci_upstream_bridge(pdev); d3_supported |= parent_pdev && parent_pdev->bridge_d3; +#endif amdgpu_atpx_get_quirks(pdev); } @@ -622,8 +635,10 @@ static bool amdgpu_atpx_detect(void) has_atpx |= amdgpu_atpx_pci_probe_handle(pdev); +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE parent_pdev = pci_upstream_bridge(pdev); d3_supported |= parent_pdev && parent_pdev->bridge_d3; +#endif amdgpu_atpx_get_quirks(pdev); } @@ -632,7 +647,9 @@ static bool amdgpu_atpx_detect(void) pr_info("vga_switcheroo: detected switching method %s handle\n", acpi_method_name); amdgpu_atpx_priv.atpx_detected = true; +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE amdgpu_atpx_priv.bridge_pm_usable = d3_supported; +#endif amdgpu_atpx_init(); return true; } diff --git a/include/kcl/backport/kcl_pci_backport.h b/include/kcl/backport/kcl_pci_backport.h index cc2af255e21b5..29bdd6c628b28 100644 --- a/include/kcl/backport/kcl_pci_backport.h +++ b/include/kcl/backport/kcl_pci_backport.h @@ -9,4 +9,8 @@ #if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) #define pcie_get_speed_cap _kcl_pcie_get_speed_cap #endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0) +#define AMDKCL_PCIE_BRIDGE_PM_USABLE +#endif #endif From d7867940b1b2703e0e97a3fa611afdf7dafe2a49 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 6 Nov 2019 10:07:49 +0800 Subject: [PATCH 0393/2653] drm/amdkcl: add AMDKCL_ENABLE_RESIZE_FB_BAR for resize BAR enable This is a squash of: drm/amdkcl: move AMDKCL_ENABLE_RESIZE_FB_BAR to kcl_pci part no actual change. Reviewed-by: Guchun Chen Signed-off-by: Flora Cui drm/amdkcl: rework pci resize dependency. Reviewed-by: Guchun Chen Signed-off-by: Flora Cui drm/amdkcl: move pci resize macro to kcl_pci.h Signed-off-by: Flora Cui Signed-off-by: Flora Cui Acked-by: Feifei Xu --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 +++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ include/kcl/backport/kcl_pci_backport.h | 1 + include/kcl/kcl_pci.h | 10 ++++++++++ 4 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 5cf24c5b6b4ab..1e24e4bc1d889 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1597,7 +1597,14 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, u64 num_vis_bytes); +#ifdef AMDKCL_ENABLE_RESIZE_FB_BAR int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); +#else +static inline int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) +{ + return 0; +} +#endif void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, const u32 *registers, const u32 array_size); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index fa99792eb2be2..366cdec835718 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1657,6 +1657,7 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) spin_unlock_irqrestore(&adev->wb.lock, flags); } +#ifdef AMDKCL_ENABLE_RESIZE_FB_BAR /** * amdgpu_device_resize_fb_bar - try to resize FB BAR * @@ -1754,6 +1755,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) return 0; } +#endif /* * GPU helpers function. diff --git a/include/kcl/backport/kcl_pci_backport.h b/include/kcl/backport/kcl_pci_backport.h index 29bdd6c628b28..21799422a6abd 100644 --- a/include/kcl/backport/kcl_pci_backport.h +++ b/include/kcl/backport/kcl_pci_backport.h @@ -13,4 +13,5 @@ #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0) #define AMDKCL_PCIE_BRIDGE_PM_USABLE #endif + #endif diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 596f37906499c..2fa2ef4a09bdf 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -206,4 +206,14 @@ static inline void kcl_pci_remove_measure_file(struct pci_dev *pdev) #endif } +/* + * v4.18-rc1-3-gb1277a226d8c PCI: Cleanup PCI_REBAR_CTRL_BAR_SHIFT handling + * v4.18-rc1-2-gd3252ace0bc6 PCI: Restore resized BAR state on resume + * v4.14-rc3-3-g8bb705e3e79d PCI: Add pci_resize_resource() for resizing BARs + * v4.14-rc3-2-g276b738deb5b PCI: Add resizable BAR infrastructure + */ +#ifdef PCI_REBAR_CTRL_BAR_SHIFT +#define AMDKCL_ENABLE_RESIZE_FB_BAR +#endif /* PCI_REBAR_CTRL_BAR_SHIFT */ + #endif /* AMDKCL_PCI_H */ From 777f3810080cc95b18629b5bbccc676b29755cf0 Mon Sep 17 00:00:00 2001 From: Yang Xiong Date: Mon, 1 Jun 2020 15:23:39 +0800 Subject: [PATCH 0394/2653] drm/amdkcl: test for RATELIMIT_MSG_ON_RELEASE The macro RATELIMIT_MSG_ON_RELEASE is introduced by the patch: 6b1d174b0c27 ratelimit: extend to print suppressed messages on release. Drop the RATELIMIT_MSG_ON_RELEASE related code if RATELIMIT_MSG_ON_RELEASE is not defined. The only side effect is that some warning messages on ratelimit release will be left over. This kcl patch is caused by patch: drm/amdgpu: added a sysfs interface for thermal throttling related V4 Signed-off-by: Yang Xiong Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 366cdec835718..6605cff1d8683 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4501,7 +4501,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, */ ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1); +#ifdef RATELIMIT_MSG_ON_RELEASE ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE); +#endif /* Registers mapping */ /* TODO: block userspace mapping of io register */ From 5e9b1f23c66ef0cb602884816e43d37a9d072985 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 25 Dec 2019 18:05:04 +0800 Subject: [PATCH 0395/2653] drm/amdkcl: fix dma_addressing_limited() not work correctly It will cause KFDEvictTest failure on ubuntu16.04. Signed-off-by: Flora Cui Reviewed-by: Le Ma Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 15 ++++++++++++++- include/kcl/kcl_dma_mapping.h | 8 ++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 4e94626c3d732..a56592dbbe98e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2390,6 +2390,19 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) { uint64_t gtt_size; int r; + bool need_dma32; + +#ifdef AMDKCL_DMA_ADDRESSING_LIMITED_WORKAROUND + /* + * set DMA mask + need_dma32 flags. + * PCIE - can handle 44-bits. + * IGP - can handle 44-bits + * PCI - dma32 for legacy pci gart + */ + need_dma32 = !!pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(44)); +#else + need_dma32 = dma_addressing_limited(adev->dev); +#endif mutex_init(&adev->mman.gtt_window_lock); @@ -2399,7 +2412,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) adev_to_drm(adev)->anon_inode->i_mapping, adev_to_drm(adev)->vma_offset_manager, adev->need_swiotlb, - dma_addressing_limited(adev->dev)); + need_dma32); if (r) { dev_err(adev->dev, "failed initializing buffer object driver(%d).\n", r); diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h index c65a83d51b953..24d18c3a7bf27 100644 --- a/include/kcl/kcl_dma_mapping.h +++ b/include/kcl/kcl_dma_mapping.h @@ -13,6 +13,14 @@ #define DMA_ATTR_NO_WARN (0UL) #endif +/* +* commit v5.3-rc1-57-g06532750010e +* dma-mapping: use dma_get_mask in dma_addressing_limited + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0) +#define AMDKCL_DMA_ADDRESSING_LIMITED_WORKAROUND +#endif + #ifdef HAVE_LINUX_DMA_ATTRS_H static inline void _kcl_convert_long_to_dma_attrs(struct dma_attrs *dma_attrs, From 40f75d44aa819b67a0e83c05c1d648a90927b763 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 15 Aug 2019 16:11:59 +0800 Subject: [PATCH 0396/2653] drm/amdkcl: check whether DEFINE_SRCU is available (v2) DEFINE_SRCU introduced by kernel v3.8-rc1~173^2^2~4^4~1 v2: replace autoconf test with macro name check Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdkfd/kfd_module.c | 9 +++++++++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 13 +++++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index 5f8093e03d340..ea7aca6d9d874 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -26,6 +26,11 @@ #include "kfd_priv.h" #include "amdgpu_amdkfd.h" +#ifndef DEFINE_SRCU +void kfd_init_processes_srcu(void); +void kfd_cleanup_processes_srcu(void); +#endif + static int kfd_init(void) { int err; @@ -70,6 +75,10 @@ static int kfd_init(void) kfd_debugfs_init(); +#ifndef DEFINE_SRCU + kfd_init_processes_srcu(); +#endif + return 0; err_create_wq: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 132649092161f..8539de7fd1838 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -53,7 +53,20 @@ struct mm_struct; DEFINE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE); DEFINE_MUTEX(kfd_processes_mutex); +#ifndef DEFINE_SRCU +struct srcu_struct kfd_processes_srcu; +void kfd_init_processes_srcu(void) +{ + init_srcu_struct(&kfd_processes_srcu); +} + +void kfd_cleanup_processes_srcu(void) +{ + cleanup_srcu_struct(&kfd_processes_srcu); +} +#else DEFINE_SRCU(kfd_processes_srcu); +#endif /* For process termination handling */ static struct workqueue_struct *kfd_process_wq; From 4b029a4c8ab0f8cbc64872ac5674c6190304e558 Mon Sep 17 00:00:00 2001 From: changzhu Date: Sun, 18 Aug 2019 21:38:39 +0800 Subject: [PATCH 0397/2653] drm/amdkcl: Test whether DW_I2S_QUIRK_16BIT_IDX_OVERRIDE is available [Why] DW_I2S_QUIRK_16BIT_IDX_OVERRIDE is not defined until patch: ASoC: dwc: Added a quirk DW_I2S_QUIRK_16BIT_IDX_OVERRIDE to dwc driver So there will be build when it's not defined. [How] Define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE if it's not defined. Change-Id: I92c4695c24cb7fd7aed80659a53ac57ca8064cef Signed-off-by: changzhu Reviewed-by: Flora Cui Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index 4926996f94da0..ef0dc39650e7b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -87,9 +87,12 @@ #define ACP_TIMEOUT_LOOP 0x000000FF #define ACP_DEVS 4 #define ACP_SRC_ID 162 - static unsigned long acp_machine_id; +#ifndef DW_I2S_QUIRK_16BIT_IDX_OVERRIDE +#define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2) +#endif + enum { ACP_TILE_P1 = 0, ACP_TILE_P2, From f4987fe2e681b33297ae1e9b4e0dd0f98727c90c Mon Sep 17 00:00:00 2001 From: Yang Xiong Date: Tue, 25 Aug 2020 12:24:13 +0800 Subject: [PATCH 0398/2653] drm/amdkcl: test whether down_read_killable is available introduced by v4.14-rc4-65-g76f8507f7a64 This patch is caused by 'drm/amdgpu: change reset lock from mutex to rw_semaphore' v2:change reset_sem to reset_domain->sem, it's caused by "drm/amdgpu: Move reset sem into reset_domain" Signed-off-by: Yang Xiong Reviewed-by: Dennis Li --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++++ drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 | 14 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 19 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index c7d109ff21264..c478823e29e2f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -1954,9 +1954,13 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val) return -ENOMEM; /* Avoid accidently unparking the sched thread during GPU reset */ +#ifdef HAVE_DOWN_READ_KILLABLE r = down_read_killable(&adev->reset_domain->sem); if (r) goto pro_end; +#else + down_read(&adev->reset_domain->sem); +#endif /* stop the scheduler */ drm_sched_wqueue_stop(&ring->sched); diff --git a/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 b/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 new file mode 100644 index 0000000000000..6de71b3c0a40d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 @@ -0,0 +1,14 @@ +#dnl +#dnl commit v4.14-rc4-65-g76f8507f7a64 +#dnl locking/rwsem: Add down_read_killable() +#dnl +AC_DEFUN([AC_AMDGPU_DOWN_READ_KILLABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT( + [down_read_killable], + [kernel/locking/rwsem.c], + [AC_DEFINE(HAVE_DOWN_READ_KILLABLE, 1, + [down_read_killable() is available])] + ) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index dd18a255c52b9..d712ac3b408ad 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -65,6 +65,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LIST_FOR_EACH_ENTRY AC_AMDGPU_TIMER_SETUP AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED + AC_AMDGPU_DOWN_READ_KILLABLE AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED From fcdd40b6c7ba50aa6a54f160e5acbe0c144c31e3 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 15 Oct 2020 14:01:05 +0800 Subject: [PATCH 0399/2653] drm/amdkcl: include kcl_mn with CONFIG_MMU_NOTIFIER enabled Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdkcl/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 3f301283ce0de..798e54671fd8c 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,6 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o +amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o CFLAGS_kcl_fence.o := -I$(src) From dcfc7db016265c97c98654d976fe066f459a8dd4 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 16 Nov 2020 10:56:56 +0800 Subject: [PATCH 0400/2653] drm/amdkcl: rename kcl_connector.c to kcl_drm_connector.c Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/{kcl_connector.c => kcl_drm_connector.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename drivers/gpu/drm/amd/amdkcl/{kcl_connector.c => kcl_drm_connector.c} (100%) diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 798e54671fd8c..52104abef5fe1 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -9,7 +9,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ - kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ + kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c similarity index 100% rename from drivers/gpu/drm/amd/amdkcl/kcl_connector.c rename to drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c From fe48f5b61546248de3c800875f1b3f1b7ceee11a Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Fri, 25 Dec 2020 16:52:50 +0800 Subject: [PATCH 0401/2653] drm/amdkcl: dummy the dp subconnector property This is caused by "utilize subconnector property for DP through atombios" and "utilize subconnector property for DP through DisplayManager" v5.8-rc2-673-g65bf2cf95d3a and v5.8-rc2-673-g65bf2cf95d3a Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- .../gpu/drm/amd/amdkcl/kcl_drm_connector.c | 8 +++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +- .../drm/amd/dkms/m4/drm_dp_subconnector.m4 | 26 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 29 +++++++++++++++++++ 5 files changed, 66 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index ff900e261cb43..a467ebb08a8f3 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -12,3 +12,11 @@ int _kcl_drm_connector_init_with_ddc(struct drm_device *dev, } EXPORT_SYMBOL(_kcl_drm_connector_init_with_ddc); #endif + +#ifndef HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY +amdkcl_dummy_symbol(drm_connector_attach_dp_subconnector_property, void, return, + struct drm_connector *connector) +amdkcl_dummy_symbol(drm_dp_set_subconnector_property, void, return, + struct drm_connector *connector, enum drm_connector_status status, + const u8 *dpcd, const u8 prot_cap[4]) +#endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 266d344a8af52..d482b97c7f1e9 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -213,10 +213,11 @@ static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) if (aconnector->dc_sink) subconnector = get_subconnector_type(link); - +#ifdef HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY drm_object_property_set_value(&connector->base, connector->dev->mode_config.dp_subconnector_property, subconnector); +#endif } /* diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 new file mode 100644 index 0000000000000..a6c7c75f41f9e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 @@ -0,0 +1,26 @@ +dnl # +dnl # v5.8-rc2-671-ge5b92773287c drm: report dp downstream port type as a subconnector property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_SUBCONNECTOR], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_mode_config *mode_config = NULL; + mode_config->dp_subconnector_property = NULL; + ], [ + AC_DEFINE(HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY, 1, + [drm_mode_config->dp_subconnector_property is available]) + ], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum drm_mode_subconnector sub = 0; + ], [ + AC_DEFINE(HAVE_DRM_MODE_SUBCONNECTOR_ENUM, 1, + [enum drm_mode_subconnector is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d712ac3b408ad..b1f693eaec0b4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -132,6 +132,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FORMAT_INFO AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED + AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 1da6773c7ee4b..8eb2f3e647417 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -79,4 +79,33 @@ int drm_connector_init_with_ddc(struct drm_device *dev, } #endif +#ifndef DP_MAX_DOWNSTREAM_PORTS +#define DP_MAX_DOWNSTREAM_PORTS 0x10 +#endif + +#ifndef HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY +void drm_connector_attach_dp_subconnector_property(struct drm_connector *connector); +void drm_dp_set_subconnector_property(struct drm_connector *connector, enum drm_connector_status status, + const u8 *dpcd, const u8 prot_cap[4]); + +#ifdef HAVE_DRM_MODE_SUBCONNECTOR_ENUM +#define DRM_MODE_SUBCONNECTOR_VGA 1 +#define DRM_MODE_SUBCONNECTOR_DisplayPort 10 +#define DRM_MODE_SUBCONNECTOR_HDMIA 11 +#define DRM_MODE_SUBCONNECTOR_Native 15 +#define DRM_MODE_SUBCONNECTOR_Wireless 18 +#else +/* Copied from include/uapi/drm/drm_mode.h */ +/* This is for connectors with multiple signal types. */ +/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ +enum drm_mode_subconnector { + DRM_MODE_SUBCONNECTOR_VGA = 1, /* DP */ + DRM_MODE_SUBCONNECTOR_DisplayPort = 10, /* DP */ + DRM_MODE_SUBCONNECTOR_HDMIA = 11, /* DP */ + DRM_MODE_SUBCONNECTOR_Native = 15, /* DP */ + DRM_MODE_SUBCONNECTOR_Wireless = 18, /* DP */ +}; +#endif /* HAVE_DRM_MODE_SUBCONNECTOR_ENUM */ +#endif /* HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY */ + #endif /* AMDKCL_DRM_CONNECTOR_H */ From f80bdce03b69ff868b9a18f5b18e3de1f4687601 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 9 Mar 2021 11:52:01 +0800 Subject: [PATCH 0402/2653] drm/amdkcl: fake hexint support for module_param Change-Id: Ic6b3fd5e2ca1e6e645c658924cc051b6119297b6 Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 2cb3aae626abb..4cfaaadbf3d8c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -56,9 +56,10 @@ #include #include #include -#include "kcl/kcl_amdgpu_ttm.h" +#include #include #include +#include "kcl/kcl_amdgpu_ttm.h" #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" From ae78ba290284585ab71c3a5b100ba1ab2bf2615a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 3 Feb 2021 11:54:35 +0800 Subject: [PATCH 0403/2653] drm/amdkcl: add kcl/kcl_dma-buf-map.h Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_dma-buf-map.h | 141 ++++++++++++++++++++++++ 3 files changed, 143 insertions(+) create mode 100644 include/kcl/kcl_dma-buf-map.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 4cfaaadbf3d8c..5145ab0dc038a 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index a5c1c3c403ad7..2964bb26cea9e 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_dma-buf-map.h b/include/kcl/kcl_dma-buf-map.h new file mode 100644 index 0000000000000..5bcaad09cabd8 --- /dev/null +++ b/include/kcl/kcl_dma-buf-map.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Pointer to dma-buf-mapped memory, plus helpers. + * Copied from include/kcl/dma-buf-map.h + */ + +#ifndef _KCL_KCL__DMA_BUF_MAP_H__H__ +#define _KCL_KCL__DMA_BUF_MAP_H__H__ + +#include + +#ifndef HAVE_LINUX_DMA_BUF_MAP_H +#include + +/** + * struct dma_buf_map - Pointer to vmap'ed dma-buf memory. + * @vaddr_iomem: The buffer's address if in I/O memory + * @vaddr: The buffer's address if in system memory + * @is_iomem: True if the dma-buf memory is located in I/O + * memory, or false otherwise. + */ +struct dma_buf_map { + union { + void __iomem *vaddr_iomem; + void *vaddr; + }; + bool is_iomem; +}; + +/** + * DMA_BUF_MAP_INIT_VADDR - Initializes struct dma_buf_map to an address in system memory + * @vaddr: A system-memory address + */ +#define DMA_BUF_MAP_INIT_VADDR(vaddr_) \ + { \ + .vaddr = (vaddr_), \ + .is_iomem = false, \ + } + +/** + * dma_buf_map_set_vaddr - Sets a dma-buf mapping structure to an address in system memory + * @map: The dma-buf mapping structure + * @vaddr: A system-memory address + * + * Sets the address and clears the I/O-memory flag. + */ +static inline void dma_buf_map_set_vaddr(struct dma_buf_map *map, void *vaddr) +{ + map->vaddr = vaddr; + map->is_iomem = false; +} + +/** + * dma_buf_map_set_vaddr_iomem - Sets a dma-buf mapping structure to an address in I/O memory + * @map: The dma-buf mapping structure + * @vaddr_iomem: An I/O-memory address + * + * Sets the address and the I/O-memory flag. + */ +static inline void dma_buf_map_set_vaddr_iomem(struct dma_buf_map *map, + void __iomem *vaddr_iomem) +{ + map->vaddr_iomem = vaddr_iomem; + map->is_iomem = true; +} + + +/** + * dma_buf_map_is_equal - Compares two dma-buf mapping structures for equality + * @lhs: The dma-buf mapping structure + * @rhs: A dma-buf mapping structure to compare with + * + * Two dma-buf mapping structures are equal if they both refer to the same type of memory + * and to the same address within that memory. + * + * Returns: + * True is both structures are equal, or false otherwise. + */ +static inline bool dma_buf_map_is_equal(const struct dma_buf_map *lhs, + const struct dma_buf_map *rhs) +{ + if (lhs->is_iomem != rhs->is_iomem) + return false; + else if (lhs->is_iomem) + return lhs->vaddr_iomem == rhs->vaddr_iomem; + else + return lhs->vaddr == rhs->vaddr; +} + +/** + * dma_buf_map_is_null - Tests for a dma-buf mapping to be NULL + * @map: The dma-buf mapping structure + * + * Depending on the state of struct dma_buf_map.is_iomem, tests if the + * mapping is NULL. + * + * Returns: + * True if the mapping is NULL, or false otherwise. + */ +static inline bool dma_buf_map_is_null(const struct dma_buf_map *map) +{ + if (map->is_iomem) + return !map->vaddr_iomem; + return !map->vaddr; +} + +/** + * dma_buf_map_is_set - Tests is the dma-buf mapping has been set + * @map: The dma-buf mapping structure + * + * Depending on the state of struct dma_buf_map.is_iomem, tests if the + * mapping has been set. + * + * Returns: + * True if the mapping is been set, or false otherwise. + */ +static inline bool dma_buf_map_is_set(const struct dma_buf_map *map) +{ + return !dma_buf_map_is_null(map); +} + +/** + * dma_buf_map_clear - Clears a dma-buf mapping structure + * @map: The dma-buf mapping structure + * + * Clears all fields to zero; including struct dma_buf_map.is_iomem. So + * mapping structures that were set to point to I/O memory are reset for + * system memory. Pointers are cleared to NULL. This is the default. + */ +static inline void dma_buf_map_clear(struct dma_buf_map *map) +{ + if (map->is_iomem) { + map->vaddr_iomem = NULL; + map->is_iomem = false; + } else { + map->vaddr = NULL; + } +} +#endif /* HAVE_LINUX_DMA_BUF_MAP_H */ + +#endif From 99d16f418dde964944cd97baddbb8dcbbc42efc6 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 4 Aug 2021 11:05:33 +0800 Subject: [PATCH 0404/2653] drm/amdkcl: Test whether drm_memcpy_from_wc() is available This is caused by 053c57696cb9 "drm/ttm: Use drm_memcpy_from_wc for TTM bo moves" v5.13-rc3-862-g053c57696cb9 Signed-off-by: Leslie Shi --- .../gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 | 16 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/ttm/ttm_bo_util.c | 19 ++++++++++ include/kcl/kcl_dma-buf-map.h | 35 +++++++++++++++++++ 4 files changed, 71 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 new file mode 100644 index 0000000000000..491ada31c112a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit b7e32bef4ae5f9149276203564b7911fac466588 +dnl # drm: Add a prefetching memcpy_from_wc +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MEMCPY_FROM_WC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_memcpy_from_wc(NULL, NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_MEMCPY_FROM_WC, 1, + [drm_memcpy_from_wc() is availablea]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b1f693eaec0b4..56ed70c05b745 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -133,6 +133,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED AC_AMDGPU_DRM_DP_SUBCONNECTOR + AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 96b8667db8ec9..5ebd3ab734aa3 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -117,7 +117,26 @@ void ttm_move_memcpy(bool clear, dst_ops->map_local(dst_iter, &dst_map, i); src_ops->map_local(src_iter, &src_map, i); +#ifdef HAVE_DRM_MEMCPY_FROM_WC drm_memcpy_from_wc(&dst_map, &src_map, PAGE_SIZE); +#else + if (!src_map.is_iomem && !dst_map.is_iomem) { + memcpy(dst_map.vaddr, src_map.vaddr, PAGE_SIZE); + } else if (!src_map.is_iomem) { + dma_buf_map_memcpy_to(&dst_map, src_map.vaddr, + PAGE_SIZE); + } else if (!dst_map.is_iomem) { + memcpy_fromio(dst_map.vaddr, src_map.vaddr_iomem, + PAGE_SIZE); + } else { + int j; + u32 __iomem *src = src_map.vaddr_iomem; + u32 __iomem *dst = dst_map.vaddr_iomem; + + for (j = 0; j < (PAGE_SIZE / sizeof(u32)); ++j) + iowrite32(ioread32(src++), dst++); + } +#endif if (src_ops->unmap_local) src_ops->unmap_local(src_iter, &src_map); diff --git a/include/kcl/kcl_dma-buf-map.h b/include/kcl/kcl_dma-buf-map.h index 5bcaad09cabd8..4ce925f647ec5 100644 --- a/include/kcl/kcl_dma-buf-map.h +++ b/include/kcl/kcl_dma-buf-map.h @@ -136,6 +136,41 @@ static inline void dma_buf_map_clear(struct dma_buf_map *map) map->vaddr = NULL; } } + +/** + * dma_buf_map_memcpy_to - Memcpy into dma-buf mapping + * @dst: The dma-buf mapping structure + * @src: The source buffer + * @len: The number of byte in src + * + * Copies data into a dma-buf mapping. The source buffer is in system + * memory. Depending on the buffer's location, the helper picks the correct + * method of accessing the memory. + */ +static inline void dma_buf_map_memcpy_to(struct dma_buf_map *dst, const void *src, size_t len) +{ + if (dst->is_iomem) + memcpy_toio(dst->vaddr_iomem, src, len); + else + memcpy(dst->vaddr, src, len); +} + +/** + * dma_buf_map_incr - Increments the address stored in a dma-buf mapping + * @map: The dma-buf mapping structure + * @incr: The number of bytes to increment + * + * Increments the address stored in a dma-buf mapping. Depending on the + * buffer's location, the correct value will be updated. + */ +static inline void dma_buf_map_incr(struct dma_buf_map *map, size_t incr) +{ + if (map->is_iomem) + map->vaddr_iomem += incr; + else + map->vaddr += incr; +} + #endif /* HAVE_LINUX_DMA_BUF_MAP_H */ #endif From 8973cff6161dab8b490740e774a50f63dc313a83 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 4 Aug 2021 11:27:39 +0800 Subject: [PATCH 0405/2653] drm/amdkcl: Test whether is_cow_mapping() is available This is caused by f91142c62161 "drm/ttm: nuke VM_MIXEDMAP on BO mappings v3" v5.13-rc3-873-gf91142c62161 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 | 15 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_mm.h | 7 +++++++ 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 b/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 new file mode 100644 index 0000000000000..c0bf84f081f2a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit 97a7e4733b9b221d012ae68fcd3b3251febf6341 +dnl # mm: introduce page_needs_cow_for_dma() for deciding whether cow +dnl # +AC_DEFUN([AC_AMDGPU_IS_COW_MAPPING], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + is_cow_mapping(VM_SHARED); + ], [ + AC_DEFINE(HAVE_IS_COW_MAPPING, 1, [is_cow_mapping() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 56ed70c05b745..91856aa95df75 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -134,6 +134,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_AMDGPU_DRM_MEMCPY_FROM_WC + AC_AMDGPU_IS_COW_MAPPING AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index b4e18dfd764fe..402a28df45f0e 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -54,4 +54,11 @@ static inline unsigned long zone_managed_pages(struct zone *zone) } #endif /* HAVE_ZONE_MANAGED_PAGES */ +#ifndef HAVE_IS_COW_MAPPING +static inline bool is_cow_mapping(vm_flags_t flags) +{ + return (flags & (VM_SHARED | VM_MAYWRITE)) == VM_MAYWRITE; +} +#endif /* HAVE_IS_COW_MAPPING */ + #endif /* AMDKCL_MM_H */ From 1c8bfff4d8f3760e8713b301ade1d9b499e875ca Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 4 Aug 2021 15:13:38 +0800 Subject: [PATCH 0406/2653] drm/amdkcl: Test whether drm_aperture_* is available This is caused by 6848c291a54f "drm/aperture: Convert drivers to aperture interfaces" v5.12-rc3-331-g6848c291a54f Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 139 ++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 | 16 ++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 4 +- .../gpu/drm/amd/dkms/m4/vga_remove_vgacon.m4 | 16 ++ include/kcl/kcl_drm_aperture.h | 25 ++++ 8 files changed, 207 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/vga_remove_vgacon.m4 create mode 100644 include/kcl/kcl_drm_aperture.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 52104abef5fe1..0791290ae716b 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -11,7 +11,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ - kcl_acpi_table.o + kcl_acpi_table.o kcl_drm_aperture.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c new file mode 100644 index 0000000000000..b3fa22920b7f2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: MIT + +#ifndef HAVE_DRM_APERTURE +#include +#include +#include +#include +#include +#include + +struct drm_aperture { + struct drm_device *dev; + resource_size_t base; + resource_size_t size; + struct list_head lh; + void (*detach)(struct drm_device *dev); +}; + +static LIST_HEAD(drm_apertures); +static DEFINE_MUTEX(drm_apertures_lock); + +static bool overlap(resource_size_t base1, resource_size_t end1, + resource_size_t base2, resource_size_t end2) +{ + return (base1 < end2) && (end1 > base2); +} + + +static void drm_aperture_detach_drivers(resource_size_t base, resource_size_t size) +{ + resource_size_t end = base + size; + struct list_head *pos, *n; + + mutex_lock(&drm_apertures_lock); + + list_for_each_safe(pos, n, &drm_apertures) { + struct drm_aperture *ap = + container_of(pos, struct drm_aperture, lh); + struct drm_device *dev = ap->dev; + + if (WARN_ON_ONCE(!dev)) + continue; + + if (!overlap(base, end, ap->base, ap->base + ap->size)) + continue; + + ap->dev = NULL; /* detach from device */ + list_del(&ap->lh); + + ap->detach(dev); + } + + mutex_unlock(&drm_apertures_lock); +} + + +/** + * drm_aperture_remove_conflicting_framebuffers - remove existing framebuffers in the given range + * @base: the aperture's base address in physical memory + * @size: aperture size in bytes + * @primary: also kick vga16fb if present + * @name: requesting driver name + * + * This function removes graphics device drivers which use memory range described by + * @base and @size. + * + * Returns: + * 0 on success, or a negative errno code otherwise + */ +int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size, + bool primary, const char *name) +{ +#if IS_REACHABLE(CONFIG_FB) + struct apertures_struct *a; + int ret; + + a = alloc_apertures(1); + if (!a) + return -ENOMEM; + + a->ranges[0].base = base; + a->ranges[0].size = size; + + ret = remove_conflicting_framebuffers(a, name, primary); + kfree(a); + + if (ret) + return ret; +#endif + + drm_aperture_detach_drivers(base, size); + + return 0; +} +EXPORT_SYMBOL(drm_aperture_remove_conflicting_framebuffers); + +/** + * drm_aperture_remove_conflicting_pci_framebuffers - remove existing framebuffers for PCI devices + * @pdev: PCI device + * @name: requesting driver name + * + * This function removes graphics device drivers using memory range configured + * for any of @pdev's memory bars. The function assumes that PCI device with + * shadowed ROM drives a primary display and so kicks out vga16fb. + * + * Returns: + * 0 on success, or a negative errno code otherwise + */ +int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) +{ + resource_size_t base, size; + int bar, ret = 0; + + for (bar = 0; bar < PCI_STD_NUM_BARS; ++bar) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + base = pci_resource_start(pdev, bar); + size = pci_resource_len(pdev, bar); + drm_aperture_detach_drivers(base, size); + } + + /* + * WARNING: Apparently we must kick fbdev drivers before vgacon, + * otherwise the vga fbdev driver falls over. + */ + +#ifdef HAVE_VGA_REMOVE_VGACON +#if IS_REACHABLE(CONFIG_FB) + ret = remove_conflicting_pci_framebuffers(pdev, name); +#endif + if (ret == 0) + ret = vga_remove_vgacon(pdev); +#endif + + return ret; +} +EXPORT_SYMBOL(drm_aperture_remove_conflicting_pci_framebuffers); + +#endif /* HAVE_DRM_APERTURE */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 5145ab0dc038a..6d1d8f4d0a66e 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -64,5 +64,6 @@ #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" +#include "kcl/kcl_drm_aperture.h" #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 new file mode 100644 index 0000000000000..532e9149653c9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 2916059147ea38f76787d7b38dee883da2e9def2 +dnl # drm/aperture: Add infrastructure for aperture ownership +dnl # +AC_DEFUN([AC_AMDGPU_DRM_APERTURE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_aperture_remove_conflicting_pci_framebuffers(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_APERTURE, 1, + [drm_aperture_remove_* is availablea]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 5db23c22d9fe3..16ebd93fc3ea8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -38,4 +38,10 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm: add managed resources tied to drm_device dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_managed.h]) + + dnl # + dnl # v5.12-rc3-330-g2916059147ea + dnl # drm/aperture: Add infrastructure for aperture ownership + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_aperture.h]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 91856aa95df75..7ffb3afa21990 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -135,7 +135,9 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING - + AC_AMDGPU_VGA_REMOVE_VGACON + AC_AMDGPU_DRM_APERTURE + AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" diff --git a/drivers/gpu/drm/amd/dkms/m4/vga_remove_vgacon.m4 b/drivers/gpu/drm/amd/dkms/m4/vga_remove_vgacon.m4 new file mode 100644 index 0000000000000..f95a903f3143b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vga_remove_vgacon.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.0-rc1-998-gc6b38fbbde91 +dnl # drm: move i915_kick_out_vgacon to vgaarb +dnl # +AC_DEFUN([AC_AMDGPU_VGA_REMOVE_VGACON], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vga_remove_vgacon(NULL); + ], [ + AC_DEFINE(HAVE_VGA_REMOVE_VGACON, 1, + [vga_remove_vgacon() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_drm_aperture.h b/include/kcl/kcl_drm_aperture.h new file mode 100644 index 0000000000000..5c402e251a5d9 --- /dev/null +++ b/include/kcl/kcl_drm_aperture.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef KCL_KCL_DRM_APERTURE_H +#define KCL_KCL_DRM_APERTURE_H + +#ifndef HAVE_DRM_APERTURE + +#include + +/* Copied from uapi/linux/pci_regs.h */ +#ifndef PCI_STD_NUM_BARS +#define PCI_STD_NUM_BARS 6 +#endif + +/* Copied from drm/drm_aperture.h */ +struct drm_device; +struct pci_dev; + +int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size, + bool primary, const char *name); + +int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name); + +#endif /* HAVE_DRM_APERTURE */ + +#endif From 6a05a7dde7eb80d43aba84e0d0c32d955d6fc95a Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 8 Mar 2021 11:52:50 +0800 Subject: [PATCH 0407/2653] drm/amdkcl: fix the warning of struct ttm_bo_devic invisible Signed-off-by: Shiwu Zhang --- include/kcl/backport/kcl_ttm_tt_backport.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/kcl/backport/kcl_ttm_tt_backport.h b/include/kcl/backport/kcl_ttm_tt_backport.h index 64f22b0fb609e..3641f2408b0f3 100644 --- a/include/kcl/backport/kcl_ttm_tt_backport.h +++ b/include/kcl/backport/kcl_ttm_tt_backport.h @@ -2,6 +2,7 @@ #ifndef AMDKCL_BACKPORT_KCL_TTM_TT_BACKPORT_H #define AMDKCL_BACKPORT_KCL_TTM_TT_BACKPORT_H +#include #include #ifndef HAVE_TTM_SG_TT_INIT From 906b25e86bad38cda3923a6905a587513c56e5ba Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 4 Aug 2021 15:43:10 +0800 Subject: [PATCH 0408/2653] drm/amdkcl: Test whether struct pci_driver has field dev_groups This is caused by 35bba8313b95 "drm/amdgpu: Convert driver sysfs attributes to static attributes" v5.13-rc1-237-g35bba8313b95 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 | 16 ++++++++++++++++ 3 files changed, 19 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 422d3b3e9dab2..aeb71b0e2157d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3226,7 +3226,9 @@ static struct pci_driver amdgpu_kms_pci_driver = { .shutdown = amdgpu_pci_shutdown, .driver.pm = &amdgpu_pm_ops, .err_handler = &amdgpu_pci_err_handler, +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS .dev_groups = amdgpu_sysfs_groups, +#endif }; static int __init amdgpu_init(void) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7ffb3afa21990..cec300efc5c45 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -137,6 +137,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON AC_AMDGPU_DRM_APERTURE + AC_AMDGPU_PCI_DRIVER_DEV_GROUPS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 new file mode 100644 index 0000000000000..7a673c73d6b1c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit ded13b9cfd595adb478a1e371d2282048bba1df5 +dnl # PCI: Add support for dev_groups to struct pci_driver +dnl # +AC_DEFUN([AC_AMDGPU_PCI_DRIVER_DEV_GROUPS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct pci_driver pd; + pd.dev_groups = NULL; + ], [], [], [ + AC_DEFINE(HAVE_PCI_DRIVER_DEV_GROUPS, 1, [struct pci_driver has field dev_groups]) + ]) + ]) +]) From 2b38add31d0de7100ca9e6edd5111169e7777e3e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 3 Feb 2021 11:38:10 +0800 Subject: [PATCH 0409/2653] drm/amdkcl: add faked pci_rebar_bytes_to_size() Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/pci_rebar_bytes_to_size.m4 | 16 ++++++++++++++++ include/kcl/kcl_pci.h | 11 +++++++++++ 3 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci_rebar_bytes_to_size.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cec300efc5c45..ad68dc0f0f448 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -33,6 +33,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCIE_BANDWIDTH_AVAILABLE AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS AC_AMDGPU_PCI_DEV_ID + AC_AMDGPU_PCI_REBAR_BYTES_TO_SIZE AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_KTIME_GET_RAW_NS AC_AMDGPU_KTIME_GET_REAL_SECONDS diff --git a/drivers/gpu/drm/amd/dkms/m4/pci_rebar_bytes_to_size.m4 b/drivers/gpu/drm/amd/dkms/m4/pci_rebar_bytes_to_size.m4 new file mode 100644 index 0000000000000..01d066282244a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci_rebar_bytes_to_size.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 192f1bf7559e895d51f81c3976c5892c8b1e0601 +dnl # PCI: Add pci_rebar_bytes_to_size() +dnl # +AC_DEFUN([AC_AMDGPU_PCI_REBAR_BYTES_TO_SIZE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pci_rebar_bytes_to_size(0); + ], [ + AC_DEFINE(HAVE_PCI_REBAR_BYTES_TO_SIZE, 1, + [pci_rebar_bytes_to_size() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 2fa2ef4a09bdf..a75ef23e8bf46 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -214,6 +214,17 @@ static inline void kcl_pci_remove_measure_file(struct pci_dev *pdev) */ #ifdef PCI_REBAR_CTRL_BAR_SHIFT #define AMDKCL_ENABLE_RESIZE_FB_BAR + +/* Copied from 192f1bf7559e895d51f81c3976c5892c8b1e0601 include/linux/pci.h */ +#ifndef HAVE_PCI_REBAR_BYTES_TO_SIZE +static inline int pci_rebar_bytes_to_size(u64 bytes) +{ + bytes = roundup_pow_of_two(bytes); + + /* Return BAR size as defined in the resizable BAR specification */ + return max(ilog2(bytes), 20) - 20; +} +#endif #endif /* PCI_REBAR_CTRL_BAR_SHIFT */ #endif /* AMDKCL_PCI_H */ From 3a46664ce670fd16c857d3c9d82e6d7e3377d9b8 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 3 Feb 2021 11:46:01 +0800 Subject: [PATCH 0410/2653] drm/amdkcl: add faked pci_rebar_get_possible_sizes() Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 51 ++++++++++++++++++++++++++++ include/kcl/kcl_pci.h | 12 +++++++ 2 files changed, 63 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index 13b6180f6b3ed..6cc6a80b921e4 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -440,3 +440,54 @@ void _kcl_pci_remove_measure_file(struct pci_dev *pdev) } EXPORT_SYMBOL(_kcl_pci_remove_measure_file); #endif /* AMDKCL_CREATE_MEASURE_FILE */ + +#ifdef AMDKCL_ENABLE_RESIZE_FB_BAR +/* Copied from drivers/pci/pci.c */ +#ifndef HAVE_PCI_REBAR_BYTES_TO_SIZE +static int _kcl_pci_rebar_find_pos(struct pci_dev *pdev, int bar) +{ + unsigned int pos, nbars, i; + u32 ctrl; + + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); + if (!pos) + return -ENOTSUPP; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> + PCI_REBAR_CTRL_NBAR_SHIFT; + + for (i = 0; i < nbars; i++, pos += 8) { + int bar_idx; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; + if (bar_idx == bar) + return pos; + } + + return -ENOENT; +} + +u32 _kcl_pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) +{ + int pos; + u32 cap; + + pos = _kcl_pci_rebar_find_pos(pdev, bar); + if (pos < 0) + return 0; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); + cap &= PCI_REBAR_CAP_SIZES; + + /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ + if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && + bar == 0 && cap == 0x7000) + cap = 0x3f000; + + return cap >> 4; +} +EXPORT_SYMBOL(_kcl_pci_rebar_get_possible_sizes); +#endif /* HAVE_PCI_REBAR_BYTES_TO_SIZE */ +#endif /* AMDKCL_ENABLE_RESIZE_FB_BAR */ diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index a75ef23e8bf46..7289493f142b2 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -224,7 +224,19 @@ static inline int pci_rebar_bytes_to_size(u64 bytes) /* Return BAR size as defined in the resizable BAR specification */ return max(ilog2(bytes), 20) - 20; } + +/* + * 907830b0fc9e PCI: Add a REBAR size quirk for Sapphire RX 5600 XT Pulse + * 8fbdbb66f8c1 PCI: Export pci_rebar_get_possible_sizes() + */ +u32 _kcl_pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); +static inline +u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) +{ + return _kcl_pci_rebar_get_possible_sizes(pdev, bar); +} #endif + #endif /* PCI_REBAR_CTRL_BAR_SHIFT */ #endif /* AMDKCL_PCI_H */ From 51b7dbe77b3973539e106a3fcd888409dc69eb91 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 8 Mar 2021 14:15:32 +0800 Subject: [PATCH 0411/2653] drm/amdkcl: fake the drm_prime_sg_to_dma_addr_array This is caused by "drm/prime: split array import functions v4" v5.10-rc3-1140-gc67e62790f5c Signed-off-by: Shiwu Zhang --- drivers/block/umem.c | 1130 ++++++++++ drivers/block/umem.h | 132 ++ drivers/block/xsysace.c | 1273 ++++++++++++ drivers/extcon/extcon-arizona.c | 1816 +++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 | 11 + .../gpu/drm/amd/dkms/m4/highmem-internal.m4 | 16 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- include/kcl/kcl_drm_prime.h | 19 + 9 files changed, 4400 insertions(+), 1 deletion(-) create mode 100644 drivers/block/umem.c create mode 100644 drivers/block/umem.h create mode 100644 drivers/block/xsysace.c create mode 100644 drivers/extcon/extcon-arizona.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 create mode 100644 include/kcl/kcl_drm_prime.h diff --git a/drivers/block/umem.c b/drivers/block/umem.c new file mode 100644 index 0000000000000..664280f23bee1 --- /dev/null +++ b/drivers/block/umem.c @@ -0,0 +1,1130 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * mm.c - Micro Memory(tm) PCI memory board block device driver - v2.3 + * + * (C) 2001 San Mehat + * (C) 2001 Johannes Erdfelt + * (C) 2001 NeilBrown + * + * This driver for the Micro Memory PCI Memory Module with Battery Backup + * is Copyright Micro Memory Inc 2001-2002. All rights reserved. + * + * This driver provides a standard block device interface for Micro Memory(tm) + * PCI based RAM boards. + * 10/05/01: Phap Nguyen - Rebuilt the driver + * 10/22/01: Phap Nguyen - v2.1 Added disk partitioning + * 29oct2001:NeilBrown - Use make_request_fn instead of request_fn + * - use stand disk partitioning (so fdisk works). + * 08nov2001:NeilBrown - change driver name from "mm" to "umem" + * - incorporate into main kernel + * 08apr2002:NeilBrown - Move some of interrupt handle to tasklet + * - use spin_lock_bh instead of _irq + * - Never block on make_request. queue + * bh's instead. + * - unregister umem from devfs at mod unload + * - Change version to 2.3 + * 07Nov2001:Phap Nguyen - Select pci read command: 06, 12, 15 (Decimal) + * 07Jan2002: P. Nguyen - Used PCI Memory Write & Invalidate for DMA + * 15May2002:NeilBrown - convert to bio for 2.5 + * 17May2002:NeilBrown - remove init_mem initialisation. Instead detect + * - a sequence of writes that cover the card, and + * - set initialised bit then. + */ + +#undef DEBUG /* #define DEBUG if you want debugging info (pr_debug) */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include /* O_ACCMODE */ +#include /* HDIO_GETGEO */ + +#include "umem.h" + +#include +#include + +#define MM_MAXCARDS 4 +#define MM_RAHEAD 2 /* two sectors */ +#define MM_BLKSIZE 1024 /* 1k blocks */ +#define MM_HARDSECT 512 /* 512-byte hardware sectors */ +#define MM_SHIFT 6 /* max 64 partitions on 4 cards */ + +/* + * Version Information + */ + +#define DRIVER_NAME "umem" +#define DRIVER_VERSION "v2.3" +#define DRIVER_AUTHOR "San Mehat, Johannes Erdfelt, NeilBrown" +#define DRIVER_DESC "Micro Memory(tm) PCI memory board block driver" + +static int debug; +/* #define HW_TRACE(x) writeb(x,cards[0].csr_remap + MEMCTRLSTATUS_MAGIC) */ +#define HW_TRACE(x) + +#define DEBUG_LED_ON_TRANSFER 0x01 +#define DEBUG_BATTERY_POLLING 0x02 + +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Debug bitmask"); + +static int pci_read_cmd = 0x0C; /* Read Multiple */ +module_param(pci_read_cmd, int, 0); +MODULE_PARM_DESC(pci_read_cmd, "PCI read command"); + +static int pci_write_cmd = 0x0F; /* Write and Invalidate */ +module_param(pci_write_cmd, int, 0); +MODULE_PARM_DESC(pci_write_cmd, "PCI write command"); + +static int pci_cmds; + +static int major_nr; + +#include +#include + +struct cardinfo { + struct pci_dev *dev; + + unsigned char __iomem *csr_remap; + unsigned int mm_size; /* size in kbytes */ + + unsigned int init_size; /* initial segment, in sectors, + * that we know to + * have been written + */ + struct bio *bio, *currentbio, **biotail; + struct bvec_iter current_iter; + + struct request_queue *queue; + + struct mm_page { + dma_addr_t page_dma; + struct mm_dma_desc *desc; + int cnt, headcnt; + struct bio *bio, **biotail; + struct bvec_iter iter; + } mm_pages[2]; +#define DESC_PER_PAGE ((PAGE_SIZE*2)/sizeof(struct mm_dma_desc)) + + int Active, Ready; + + struct tasklet_struct tasklet; + unsigned int dma_status; + + struct { + int good; + int warned; + unsigned long last_change; + } battery[2]; + + spinlock_t lock; + int check_batteries; + + int flags; +}; + +static struct cardinfo cards[MM_MAXCARDS]; +static struct timer_list battery_timer; + +static int num_cards; + +static struct gendisk *mm_gendisk[MM_MAXCARDS]; + +static void check_batteries(struct cardinfo *card); + +static int get_userbit(struct cardinfo *card, int bit) +{ + unsigned char led; + + led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL); + return led & bit; +} + +static int set_userbit(struct cardinfo *card, int bit, unsigned char state) +{ + unsigned char led; + + led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL); + if (state) + led |= bit; + else + led &= ~bit; + writeb(led, card->csr_remap + MEMCTRLCMD_LEDCTRL); + + return 0; +} + +/* + * NOTE: For the power LED, use the LED_POWER_* macros since they differ + */ +static void set_led(struct cardinfo *card, int shift, unsigned char state) +{ + unsigned char led; + + led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL); + if (state == LED_FLIP) + led ^= (1<csr_remap + MEMCTRLCMD_LEDCTRL); + +} + +#ifdef MM_DIAG +static void dump_regs(struct cardinfo *card) +{ + unsigned char *p; + int i, i1; + + p = card->csr_remap; + for (i = 0; i < 8; i++) { + printk(KERN_DEBUG "%p ", p); + + for (i1 = 0; i1 < 16; i1++) + printk("%02x ", *p++); + + printk("\n"); + } +} +#endif + +static void dump_dmastat(struct cardinfo *card, unsigned int dmastat) +{ + dev_printk(KERN_DEBUG, &card->dev->dev, "DMAstat - "); + if (dmastat & DMASCR_ANY_ERR) + printk(KERN_CONT "ANY_ERR "); + if (dmastat & DMASCR_MBE_ERR) + printk(KERN_CONT "MBE_ERR "); + if (dmastat & DMASCR_PARITY_ERR_REP) + printk(KERN_CONT "PARITY_ERR_REP "); + if (dmastat & DMASCR_PARITY_ERR_DET) + printk(KERN_CONT "PARITY_ERR_DET "); + if (dmastat & DMASCR_SYSTEM_ERR_SIG) + printk(KERN_CONT "SYSTEM_ERR_SIG "); + if (dmastat & DMASCR_TARGET_ABT) + printk(KERN_CONT "TARGET_ABT "); + if (dmastat & DMASCR_MASTER_ABT) + printk(KERN_CONT "MASTER_ABT "); + if (dmastat & DMASCR_CHAIN_COMPLETE) + printk(KERN_CONT "CHAIN_COMPLETE "); + if (dmastat & DMASCR_DMA_COMPLETE) + printk(KERN_CONT "DMA_COMPLETE "); + printk("\n"); +} + +/* + * Theory of request handling + * + * Each bio is assigned to one mm_dma_desc - which may not be enough FIXME + * We have two pages of mm_dma_desc, holding about 64 descriptors + * each. These are allocated at init time. + * One page is "Ready" and is either full, or can have request added. + * The other page might be "Active", which DMA is happening on it. + * + * Whenever IO on the active page completes, the Ready page is activated + * and the ex-Active page is clean out and made Ready. + * Otherwise the Ready page is only activated when it becomes full. + * + * If a request arrives while both pages a full, it is queued, and b_rdev is + * overloaded to record whether it was a read or a write. + * + * The interrupt handler only polls the device to clear the interrupt. + * The processing of the result is done in a tasklet. + */ + +static void mm_start_io(struct cardinfo *card) +{ + /* we have the lock, we know there is + * no IO active, and we know that card->Active + * is set + */ + struct mm_dma_desc *desc; + struct mm_page *page; + int offset; + + /* make the last descriptor end the chain */ + page = &card->mm_pages[card->Active]; + pr_debug("start_io: %d %d->%d\n", + card->Active, page->headcnt, page->cnt - 1); + desc = &page->desc[page->cnt-1]; + + desc->control_bits |= cpu_to_le32(DMASCR_CHAIN_COMP_EN); + desc->control_bits &= ~cpu_to_le32(DMASCR_CHAIN_EN); + desc->sem_control_bits = desc->control_bits; + + + if (debug & DEBUG_LED_ON_TRANSFER) + set_led(card, LED_REMOVE, LED_ON); + + desc = &page->desc[page->headcnt]; + writel(0, card->csr_remap + DMA_PCI_ADDR); + writel(0, card->csr_remap + DMA_PCI_ADDR + 4); + + writel(0, card->csr_remap + DMA_LOCAL_ADDR); + writel(0, card->csr_remap + DMA_LOCAL_ADDR + 4); + + writel(0, card->csr_remap + DMA_TRANSFER_SIZE); + writel(0, card->csr_remap + DMA_TRANSFER_SIZE + 4); + + writel(0, card->csr_remap + DMA_SEMAPHORE_ADDR); + writel(0, card->csr_remap + DMA_SEMAPHORE_ADDR + 4); + + offset = ((char *)desc) - ((char *)page->desc); + writel(cpu_to_le32((page->page_dma+offset) & 0xffffffff), + card->csr_remap + DMA_DESCRIPTOR_ADDR); + /* Force the value to u64 before shifting otherwise >> 32 is undefined C + * and on some ports will do nothing ! */ + writel(cpu_to_le32(((u64)page->page_dma)>>32), + card->csr_remap + DMA_DESCRIPTOR_ADDR + 4); + + /* Go, go, go */ + writel(cpu_to_le32(DMASCR_GO | DMASCR_CHAIN_EN | pci_cmds), + card->csr_remap + DMA_STATUS_CTRL); +} + +static int add_bio(struct cardinfo *card); + +static void activate(struct cardinfo *card) +{ + /* if No page is Active, and Ready is + * not empty, then switch Ready page + * to active and start IO. + * Then add any bh's that are available to Ready + */ + + do { + while (add_bio(card)) + ; + + if (card->Active == -1 && + card->mm_pages[card->Ready].cnt > 0) { + card->Active = card->Ready; + card->Ready = 1-card->Ready; + mm_start_io(card); + } + + } while (card->Active == -1 && add_bio(card)); +} + +static inline void reset_page(struct mm_page *page) +{ + page->cnt = 0; + page->headcnt = 0; + page->bio = NULL; + page->biotail = &page->bio; +} + +/* + * If there is room on Ready page, take + * one bh off list and add it. + * return 1 if there was room, else 0. + */ +static int add_bio(struct cardinfo *card) +{ + struct mm_page *p; + struct mm_dma_desc *desc; + dma_addr_t dma_handle; + int offset; + struct bio *bio; + struct bio_vec vec; + + bio = card->currentbio; + if (!bio && card->bio) { + card->currentbio = card->bio; + card->current_iter = card->bio->bi_iter; + card->bio = card->bio->bi_next; + if (card->bio == NULL) + card->biotail = &card->bio; + card->currentbio->bi_next = NULL; + return 1; + } + if (!bio) + return 0; + + if (card->mm_pages[card->Ready].cnt >= DESC_PER_PAGE) + return 0; + + vec = bio_iter_iovec(bio, card->current_iter); + + dma_handle = dma_map_page(&card->dev->dev, + vec.bv_page, + vec.bv_offset, + vec.bv_len, + bio_op(bio) == REQ_OP_READ ? + DMA_FROM_DEVICE : DMA_TO_DEVICE); + + p = &card->mm_pages[card->Ready]; + desc = &p->desc[p->cnt]; + p->cnt++; + if (p->bio == NULL) + p->iter = card->current_iter; + if ((p->biotail) != &bio->bi_next) { + *(p->biotail) = bio; + p->biotail = &(bio->bi_next); + bio->bi_next = NULL; + } + + desc->data_dma_handle = dma_handle; + + desc->pci_addr = cpu_to_le64((u64)desc->data_dma_handle); + desc->local_addr = cpu_to_le64(card->current_iter.bi_sector << 9); + desc->transfer_size = cpu_to_le32(vec.bv_len); + offset = (((char *)&desc->sem_control_bits) - ((char *)p->desc)); + desc->sem_addr = cpu_to_le64((u64)(p->page_dma+offset)); + desc->zero1 = desc->zero2 = 0; + offset = (((char *)(desc+1)) - ((char *)p->desc)); + desc->next_desc_addr = cpu_to_le64(p->page_dma+offset); + desc->control_bits = cpu_to_le32(DMASCR_GO|DMASCR_ERR_INT_EN| + DMASCR_PARITY_INT_EN| + DMASCR_CHAIN_EN | + DMASCR_SEM_EN | + pci_cmds); + if (bio_op(bio) == REQ_OP_WRITE) + desc->control_bits |= cpu_to_le32(DMASCR_TRANSFER_READ); + desc->sem_control_bits = desc->control_bits; + + + bio_advance_iter(bio, &card->current_iter, vec.bv_len); + if (!card->current_iter.bi_size) + card->currentbio = NULL; + + return 1; +} + +static void process_page(unsigned long data) +{ + /* check if any of the requests in the page are DMA_COMPLETE, + * and deal with them appropriately. + * If we find a descriptor without DMA_COMPLETE in the semaphore, then + * dma must have hit an error on that descriptor, so use dma_status + * instead and assume that all following descriptors must be re-tried. + */ + struct mm_page *page; + struct bio *return_bio = NULL; + struct cardinfo *card = (struct cardinfo *)data; + unsigned int dma_status = card->dma_status; + + spin_lock(&card->lock); + if (card->Active < 0) + goto out_unlock; + page = &card->mm_pages[card->Active]; + + while (page->headcnt < page->cnt) { + struct bio *bio = page->bio; + struct mm_dma_desc *desc = &page->desc[page->headcnt]; + int control = le32_to_cpu(desc->sem_control_bits); + int last = 0; + struct bio_vec vec; + + if (!(control & DMASCR_DMA_COMPLETE)) { + control = dma_status; + last = 1; + } + + page->headcnt++; + vec = bio_iter_iovec(bio, page->iter); + bio_advance_iter(bio, &page->iter, vec.bv_len); + + if (!page->iter.bi_size) { + page->bio = bio->bi_next; + if (page->bio) + page->iter = page->bio->bi_iter; + } + + dma_unmap_page(&card->dev->dev, desc->data_dma_handle, + vec.bv_len, + (control & DMASCR_TRANSFER_READ) ? + DMA_TO_DEVICE : DMA_FROM_DEVICE); + if (control & DMASCR_HARD_ERROR) { + /* error */ + bio->bi_status = BLK_STS_IOERR; + dev_printk(KERN_WARNING, &card->dev->dev, + "I/O error on sector %d/%d\n", + le32_to_cpu(desc->local_addr)>>9, + le32_to_cpu(desc->transfer_size)); + dump_dmastat(card, control); + } else if (op_is_write(bio_op(bio)) && + le32_to_cpu(desc->local_addr) >> 9 == + card->init_size) { + card->init_size += le32_to_cpu(desc->transfer_size) >> 9; + if (card->init_size >> 1 >= card->mm_size) { + dev_printk(KERN_INFO, &card->dev->dev, + "memory now initialised\n"); + set_userbit(card, MEMORY_INITIALIZED, 1); + } + } + if (bio != page->bio) { + bio->bi_next = return_bio; + return_bio = bio; + } + + if (last) + break; + } + + if (debug & DEBUG_LED_ON_TRANSFER) + set_led(card, LED_REMOVE, LED_OFF); + + if (card->check_batteries) { + card->check_batteries = 0; + check_batteries(card); + } + if (page->headcnt >= page->cnt) { + reset_page(page); + card->Active = -1; + activate(card); + } else { + /* haven't finished with this one yet */ + pr_debug("do some more\n"); + mm_start_io(card); + } + out_unlock: + spin_unlock(&card->lock); + + while (return_bio) { + struct bio *bio = return_bio; + + return_bio = bio->bi_next; + bio->bi_next = NULL; + bio_endio(bio); + } +} + +static void mm_unplug(struct blk_plug_cb *cb, bool from_schedule) +{ + struct cardinfo *card = cb->data; + + spin_lock_irq(&card->lock); + activate(card); + spin_unlock_irq(&card->lock); + kfree(cb); +} + +static int mm_check_plugged(struct cardinfo *card) +{ + return !!blk_check_plugged(mm_unplug, card, sizeof(struct blk_plug_cb)); +} + +static blk_qc_t mm_submit_bio(struct bio *bio) +{ + struct cardinfo *card = bio->bi_bdev->bd_disk->private_data; + + pr_debug("mm_make_request %llu %u\n", + (unsigned long long)bio->bi_iter.bi_sector, + bio->bi_iter.bi_size); + + blk_queue_split(&bio); + + spin_lock_irq(&card->lock); + *card->biotail = bio; + bio->bi_next = NULL; + card->biotail = &bio->bi_next; + if (op_is_sync(bio->bi_opf) || !mm_check_plugged(card)) + activate(card); + spin_unlock_irq(&card->lock); + + return BLK_QC_T_NONE; +} + +static irqreturn_t mm_interrupt(int irq, void *__card) +{ + struct cardinfo *card = (struct cardinfo *) __card; + unsigned int dma_status; + unsigned short cfg_status; + +HW_TRACE(0x30); + + dma_status = le32_to_cpu(readl(card->csr_remap + DMA_STATUS_CTRL)); + + if (!(dma_status & (DMASCR_ERROR_MASK | DMASCR_CHAIN_COMPLETE))) { + /* interrupt wasn't for me ... */ + return IRQ_NONE; + } + + /* clear COMPLETION interrupts */ + if (card->flags & UM_FLAG_NO_BYTE_STATUS) + writel(cpu_to_le32(DMASCR_DMA_COMPLETE|DMASCR_CHAIN_COMPLETE), + card->csr_remap + DMA_STATUS_CTRL); + else + writeb((DMASCR_DMA_COMPLETE|DMASCR_CHAIN_COMPLETE) >> 16, + card->csr_remap + DMA_STATUS_CTRL + 2); + + /* log errors and clear interrupt status */ + if (dma_status & DMASCR_ANY_ERR) { + unsigned int data_log1, data_log2; + unsigned int addr_log1, addr_log2; + unsigned char stat, count, syndrome, check; + + stat = readb(card->csr_remap + MEMCTRLCMD_ERRSTATUS); + + data_log1 = le32_to_cpu(readl(card->csr_remap + + ERROR_DATA_LOG)); + data_log2 = le32_to_cpu(readl(card->csr_remap + + ERROR_DATA_LOG + 4)); + addr_log1 = le32_to_cpu(readl(card->csr_remap + + ERROR_ADDR_LOG)); + addr_log2 = readb(card->csr_remap + ERROR_ADDR_LOG + 4); + + count = readb(card->csr_remap + ERROR_COUNT); + syndrome = readb(card->csr_remap + ERROR_SYNDROME); + check = readb(card->csr_remap + ERROR_CHECK); + + dump_dmastat(card, dma_status); + + if (stat & 0x01) + dev_printk(KERN_ERR, &card->dev->dev, + "Memory access error detected (err count %d)\n", + count); + if (stat & 0x02) + dev_printk(KERN_ERR, &card->dev->dev, + "Multi-bit EDC error\n"); + + dev_printk(KERN_ERR, &card->dev->dev, + "Fault Address 0x%02x%08x, Fault Data 0x%08x%08x\n", + addr_log2, addr_log1, data_log2, data_log1); + dev_printk(KERN_ERR, &card->dev->dev, + "Fault Check 0x%02x, Fault Syndrome 0x%02x\n", + check, syndrome); + + writeb(0, card->csr_remap + ERROR_COUNT); + } + + if (dma_status & DMASCR_PARITY_ERR_REP) { + dev_printk(KERN_ERR, &card->dev->dev, + "PARITY ERROR REPORTED\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + if (dma_status & DMASCR_PARITY_ERR_DET) { + dev_printk(KERN_ERR, &card->dev->dev, + "PARITY ERROR DETECTED\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + if (dma_status & DMASCR_SYSTEM_ERR_SIG) { + dev_printk(KERN_ERR, &card->dev->dev, "SYSTEM ERROR\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + if (dma_status & DMASCR_TARGET_ABT) { + dev_printk(KERN_ERR, &card->dev->dev, "TARGET ABORT\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + if (dma_status & DMASCR_MASTER_ABT) { + dev_printk(KERN_ERR, &card->dev->dev, "MASTER ABORT\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + /* and process the DMA descriptors */ + card->dma_status = dma_status; + tasklet_schedule(&card->tasklet); + +HW_TRACE(0x36); + + return IRQ_HANDLED; +} + +/* + * If both batteries are good, no LED + * If either battery has been warned, solid LED + * If both batteries are bad, flash the LED quickly + * If either battery is bad, flash the LED semi quickly + */ +static void set_fault_to_battery_status(struct cardinfo *card) +{ + if (card->battery[0].good && card->battery[1].good) + set_led(card, LED_FAULT, LED_OFF); + else if (card->battery[0].warned || card->battery[1].warned) + set_led(card, LED_FAULT, LED_ON); + else if (!card->battery[0].good && !card->battery[1].good) + set_led(card, LED_FAULT, LED_FLASH_7_0); + else + set_led(card, LED_FAULT, LED_FLASH_3_5); +} + +static void init_battery_timer(void); + +static int check_battery(struct cardinfo *card, int battery, int status) +{ + if (status != card->battery[battery].good) { + card->battery[battery].good = !card->battery[battery].good; + card->battery[battery].last_change = jiffies; + + if (card->battery[battery].good) { + dev_printk(KERN_ERR, &card->dev->dev, + "Battery %d now good\n", battery + 1); + card->battery[battery].warned = 0; + } else + dev_printk(KERN_ERR, &card->dev->dev, + "Battery %d now FAILED\n", battery + 1); + + return 1; + } else if (!card->battery[battery].good && + !card->battery[battery].warned && + time_after_eq(jiffies, card->battery[battery].last_change + + (HZ * 60 * 60 * 5))) { + dev_printk(KERN_ERR, &card->dev->dev, + "Battery %d still FAILED after 5 hours\n", battery + 1); + card->battery[battery].warned = 1; + + return 1; + } + + return 0; +} + +static void check_batteries(struct cardinfo *card) +{ + /* NOTE: this must *never* be called while the card + * is doing (bus-to-card) DMA, or you will need the + * reset switch + */ + unsigned char status; + int ret1, ret2; + + status = readb(card->csr_remap + MEMCTRLSTATUS_BATTERY); + if (debug & DEBUG_BATTERY_POLLING) + dev_printk(KERN_DEBUG, &card->dev->dev, + "checking battery status, 1 = %s, 2 = %s\n", + (status & BATTERY_1_FAILURE) ? "FAILURE" : "OK", + (status & BATTERY_2_FAILURE) ? "FAILURE" : "OK"); + + ret1 = check_battery(card, 0, !(status & BATTERY_1_FAILURE)); + ret2 = check_battery(card, 1, !(status & BATTERY_2_FAILURE)); + + if (ret1 || ret2) + set_fault_to_battery_status(card); +} + +static void check_all_batteries(struct timer_list *unused) +{ + int i; + + for (i = 0; i < num_cards; i++) + if (!(cards[i].flags & UM_FLAG_NO_BATT)) { + struct cardinfo *card = &cards[i]; + spin_lock_bh(&card->lock); + if (card->Active >= 0) + card->check_batteries = 1; + else + check_batteries(card); + spin_unlock_bh(&card->lock); + } + + init_battery_timer(); +} + +static void init_battery_timer(void) +{ + timer_setup(&battery_timer, check_all_batteries, 0); + battery_timer.expires = jiffies + (HZ * 60); + add_timer(&battery_timer); +} + +static void del_battery_timer(void) +{ + del_timer(&battery_timer); +} + +/* + * Note no locks taken out here. In a worst case scenario, we could drop + * a chunk of system memory. But that should never happen, since validation + * happens at open or mount time, when locks are held. + * + * That's crap, since doing that while some partitions are opened + * or mounted will give you really nasty results. + */ +static int mm_revalidate(struct gendisk *disk) +{ + struct cardinfo *card = disk->private_data; + set_capacity(disk, card->mm_size << 1); + return 0; +} + +static int mm_getgeo(struct block_device *bdev, struct hd_geometry *geo) +{ + struct cardinfo *card = bdev->bd_disk->private_data; + int size = card->mm_size * (1024 / MM_HARDSECT); + + /* + * get geometry: we have to fake one... trim the size to a + * multiple of 2048 (1M): tell we have 32 sectors, 64 heads, + * whatever cylinders. + */ + geo->heads = 64; + geo->sectors = 32; + geo->cylinders = size / (geo->heads * geo->sectors); + return 0; +} + +static const struct block_device_operations mm_fops = { + .owner = THIS_MODULE, + .submit_bio = mm_submit_bio, + .getgeo = mm_getgeo, + .revalidate_disk = mm_revalidate, +}; + +static int mm_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) +{ + int ret; + struct cardinfo *card = &cards[num_cards]; + unsigned char mem_present; + unsigned char batt_status; + unsigned int saved_bar, data; + unsigned long csr_base; + unsigned long csr_len; + int magic_number; + static int printed_version; + + if (!printed_version++) + printk(KERN_INFO DRIVER_VERSION " : " DRIVER_DESC "\n"); + + ret = pci_enable_device(dev); + if (ret) + return ret; + + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF8); + pci_set_master(dev); + + card->dev = dev; + + csr_base = pci_resource_start(dev, 0); + csr_len = pci_resource_len(dev, 0); + if (!csr_base || !csr_len) + return -ENODEV; + + dev_printk(KERN_INFO, &dev->dev, + "Micro Memory(tm) controller found (PCI Mem Module (Battery Backup))\n"); + + if (dma_set_mask(&dev->dev, DMA_BIT_MASK(64)) && + dma_set_mask(&dev->dev, DMA_BIT_MASK(32))) { + dev_printk(KERN_WARNING, &dev->dev, "NO suitable DMA found\n"); + return -ENOMEM; + } + + ret = pci_request_regions(dev, DRIVER_NAME); + if (ret) { + dev_printk(KERN_ERR, &card->dev->dev, + "Unable to request memory region\n"); + goto failed_req_csr; + } + + card->csr_remap = ioremap(csr_base, csr_len); + if (!card->csr_remap) { + dev_printk(KERN_ERR, &card->dev->dev, + "Unable to remap memory region\n"); + ret = -ENOMEM; + + goto failed_remap_csr; + } + + dev_printk(KERN_INFO, &card->dev->dev, + "CSR 0x%08lx -> 0x%p (0x%lx)\n", + csr_base, card->csr_remap, csr_len); + + switch (card->dev->device) { + case 0x5415: + card->flags |= UM_FLAG_NO_BYTE_STATUS | UM_FLAG_NO_BATTREG; + magic_number = 0x59; + break; + + case 0x5425: + card->flags |= UM_FLAG_NO_BYTE_STATUS; + magic_number = 0x5C; + break; + + case 0x6155: + card->flags |= UM_FLAG_NO_BYTE_STATUS | + UM_FLAG_NO_BATTREG | UM_FLAG_NO_BATT; + magic_number = 0x99; + break; + + default: + magic_number = 0x100; + break; + } + + if (readb(card->csr_remap + MEMCTRLSTATUS_MAGIC) != magic_number) { + dev_printk(KERN_ERR, &card->dev->dev, "Magic number invalid\n"); + ret = -ENOMEM; + goto failed_magic; + } + + card->mm_pages[0].desc = dma_alloc_coherent(&card->dev->dev, + PAGE_SIZE * 2, &card->mm_pages[0].page_dma, GFP_KERNEL); + card->mm_pages[1].desc = dma_alloc_coherent(&card->dev->dev, + PAGE_SIZE * 2, &card->mm_pages[1].page_dma, GFP_KERNEL); + if (card->mm_pages[0].desc == NULL || + card->mm_pages[1].desc == NULL) { + dev_printk(KERN_ERR, &card->dev->dev, "alloc failed\n"); + ret = -ENOMEM; + goto failed_alloc; + } + reset_page(&card->mm_pages[0]); + reset_page(&card->mm_pages[1]); + card->Ready = 0; /* page 0 is ready */ + card->Active = -1; /* no page is active */ + card->bio = NULL; + card->biotail = &card->bio; + spin_lock_init(&card->lock); + + card->queue = blk_alloc_queue(NUMA_NO_NODE); + if (!card->queue) { + ret = -ENOMEM; + goto failed_alloc; + } + + tasklet_init(&card->tasklet, process_page, (unsigned long)card); + + card->check_batteries = 0; + + mem_present = readb(card->csr_remap + MEMCTRLSTATUS_MEMORY); + switch (mem_present) { + case MEM_128_MB: + card->mm_size = 1024 * 128; + break; + case MEM_256_MB: + card->mm_size = 1024 * 256; + break; + case MEM_512_MB: + card->mm_size = 1024 * 512; + break; + case MEM_1_GB: + card->mm_size = 1024 * 1024; + break; + case MEM_2_GB: + card->mm_size = 1024 * 2048; + break; + default: + card->mm_size = 0; + break; + } + + /* Clear the LED's we control */ + set_led(card, LED_REMOVE, LED_OFF); + set_led(card, LED_FAULT, LED_OFF); + + batt_status = readb(card->csr_remap + MEMCTRLSTATUS_BATTERY); + + card->battery[0].good = !(batt_status & BATTERY_1_FAILURE); + card->battery[1].good = !(batt_status & BATTERY_2_FAILURE); + card->battery[0].last_change = card->battery[1].last_change = jiffies; + + if (card->flags & UM_FLAG_NO_BATT) + dev_printk(KERN_INFO, &card->dev->dev, + "Size %d KB\n", card->mm_size); + else { + dev_printk(KERN_INFO, &card->dev->dev, + "Size %d KB, Battery 1 %s (%s), Battery 2 %s (%s)\n", + card->mm_size, + batt_status & BATTERY_1_DISABLED ? "Disabled" : "Enabled", + card->battery[0].good ? "OK" : "FAILURE", + batt_status & BATTERY_2_DISABLED ? "Disabled" : "Enabled", + card->battery[1].good ? "OK" : "FAILURE"); + + set_fault_to_battery_status(card); + } + + pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &saved_bar); + data = 0xffffffff; + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, data); + pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &data); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, saved_bar); + data &= 0xfffffff0; + data = ~data; + data += 1; + + if (request_irq(dev->irq, mm_interrupt, IRQF_SHARED, DRIVER_NAME, + card)) { + dev_printk(KERN_ERR, &card->dev->dev, + "Unable to allocate IRQ\n"); + ret = -ENODEV; + goto failed_req_irq; + } + + dev_printk(KERN_INFO, &card->dev->dev, + "Window size %d bytes, IRQ %d\n", data, dev->irq); + + pci_set_drvdata(dev, card); + + if (pci_write_cmd != 0x0F) /* If not Memory Write & Invalidate */ + pci_write_cmd = 0x07; /* then Memory Write command */ + + if (pci_write_cmd & 0x08) { /* use Memory Write and Invalidate */ + unsigned short cfg_command; + pci_read_config_word(dev, PCI_COMMAND, &cfg_command); + cfg_command |= 0x10; /* Memory Write & Invalidate Enable */ + pci_write_config_word(dev, PCI_COMMAND, cfg_command); + } + pci_cmds = (pci_read_cmd << 28) | (pci_write_cmd << 24); + + num_cards++; + + if (!get_userbit(card, MEMORY_INITIALIZED)) { + dev_printk(KERN_INFO, &card->dev->dev, + "memory NOT initialized. Consider over-writing whole device.\n"); + card->init_size = 0; + } else { + dev_printk(KERN_INFO, &card->dev->dev, + "memory already initialized\n"); + card->init_size = card->mm_size; + } + + /* Enable ECC */ + writeb(EDC_STORE_CORRECT, card->csr_remap + MEMCTRLCMD_ERRCTRL); + + return 0; + + failed_req_irq: + failed_alloc: + if (card->mm_pages[0].desc) + dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2, + card->mm_pages[0].desc, + card->mm_pages[0].page_dma); + if (card->mm_pages[1].desc) + dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2, + card->mm_pages[1].desc, + card->mm_pages[1].page_dma); + failed_magic: + iounmap(card->csr_remap); + failed_remap_csr: + pci_release_regions(dev); + failed_req_csr: + + return ret; +} + +static void mm_pci_remove(struct pci_dev *dev) +{ + struct cardinfo *card = pci_get_drvdata(dev); + + tasklet_kill(&card->tasklet); + free_irq(dev->irq, card); + iounmap(card->csr_remap); + + if (card->mm_pages[0].desc) + dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2, + card->mm_pages[0].desc, + card->mm_pages[0].page_dma); + if (card->mm_pages[1].desc) + dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2, + card->mm_pages[1].desc, + card->mm_pages[1].page_dma); + blk_cleanup_queue(card->queue); + + pci_release_regions(dev); + pci_disable_device(dev); +} + +static const struct pci_device_id mm_pci_ids[] = { + {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_5415CN)}, + {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_5425CN)}, + {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_6155)}, + { + .vendor = 0x8086, + .device = 0xB555, + .subvendor = 0x1332, + .subdevice = 0x5460, + .class = 0x050000, + .class_mask = 0, + }, { /* end: all zeroes */ } +}; + +MODULE_DEVICE_TABLE(pci, mm_pci_ids); + +static struct pci_driver mm_pci_driver = { + .name = DRIVER_NAME, + .id_table = mm_pci_ids, + .probe = mm_pci_probe, + .remove = mm_pci_remove, +}; + +static int __init mm_init(void) +{ + int retval, i; + int err; + + retval = pci_register_driver(&mm_pci_driver); + if (retval) + return -ENOMEM; + + err = major_nr = register_blkdev(0, DRIVER_NAME); + if (err < 0) { + pci_unregister_driver(&mm_pci_driver); + return -EIO; + } + + for (i = 0; i < num_cards; i++) { + mm_gendisk[i] = alloc_disk(1 << MM_SHIFT); + if (!mm_gendisk[i]) + goto out; + } + + for (i = 0; i < num_cards; i++) { + struct gendisk *disk = mm_gendisk[i]; + sprintf(disk->disk_name, "umem%c", 'a'+i); + spin_lock_init(&cards[i].lock); + disk->major = major_nr; + disk->first_minor = i << MM_SHIFT; + disk->fops = &mm_fops; + disk->private_data = &cards[i]; + disk->queue = cards[i].queue; + set_capacity(disk, cards[i].mm_size << 1); + add_disk(disk); + } + + init_battery_timer(); + printk(KERN_INFO "MM: desc_per_page = %ld\n", DESC_PER_PAGE); +/* printk("mm_init: Done. 10-19-01 9:00\n"); */ + return 0; + +out: + pci_unregister_driver(&mm_pci_driver); + unregister_blkdev(major_nr, DRIVER_NAME); + while (i--) + put_disk(mm_gendisk[i]); + return -ENOMEM; +} + +static void __exit mm_cleanup(void) +{ + int i; + + del_battery_timer(); + + for (i = 0; i < num_cards ; i++) { + del_gendisk(mm_gendisk[i]); + put_disk(mm_gendisk[i]); + } + + pci_unregister_driver(&mm_pci_driver); + + unregister_blkdev(major_nr, DRIVER_NAME); +} + +module_init(mm_init); +module_exit(mm_cleanup); + +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_LICENSE("GPL"); diff --git a/drivers/block/umem.h b/drivers/block/umem.h new file mode 100644 index 0000000000000..58384978ff054 --- /dev/null +++ b/drivers/block/umem.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file contains defines for the + * Micro Memory MM5415 + * family PCI Memory Module with Battery Backup. + * + * Copyright Micro Memory INC 2001. All rights reserved. + */ + +#ifndef _DRIVERS_BLOCK_MM_H +#define _DRIVERS_BLOCK_MM_H + + +#define IRQ_TIMEOUT (1 * HZ) + +/* CSR register definition */ +#define MEMCTRLSTATUS_MAGIC 0x00 +#define MM_MAGIC_VALUE (unsigned char)0x59 + +#define MEMCTRLSTATUS_BATTERY 0x04 +#define BATTERY_1_DISABLED 0x01 +#define BATTERY_1_FAILURE 0x02 +#define BATTERY_2_DISABLED 0x04 +#define BATTERY_2_FAILURE 0x08 + +#define MEMCTRLSTATUS_MEMORY 0x07 +#define MEM_128_MB 0xfe +#define MEM_256_MB 0xfc +#define MEM_512_MB 0xf8 +#define MEM_1_GB 0xf0 +#define MEM_2_GB 0xe0 + +#define MEMCTRLCMD_LEDCTRL 0x08 +#define LED_REMOVE 2 +#define LED_FAULT 4 +#define LED_POWER 6 +#define LED_FLIP 255 +#define LED_OFF 0x00 +#define LED_ON 0x01 +#define LED_FLASH_3_5 0x02 +#define LED_FLASH_7_0 0x03 +#define LED_POWER_ON 0x00 +#define LED_POWER_OFF 0x01 +#define USER_BIT1 0x01 +#define USER_BIT2 0x02 + +#define MEMORY_INITIALIZED USER_BIT1 + +#define MEMCTRLCMD_ERRCTRL 0x0C +#define EDC_NONE_DEFAULT 0x00 +#define EDC_NONE 0x01 +#define EDC_STORE_READ 0x02 +#define EDC_STORE_CORRECT 0x03 + +#define MEMCTRLCMD_ERRCNT 0x0D +#define MEMCTRLCMD_ERRSTATUS 0x0E + +#define ERROR_DATA_LOG 0x20 +#define ERROR_ADDR_LOG 0x28 +#define ERROR_COUNT 0x3D +#define ERROR_SYNDROME 0x3E +#define ERROR_CHECK 0x3F + +#define DMA_PCI_ADDR 0x40 +#define DMA_LOCAL_ADDR 0x48 +#define DMA_TRANSFER_SIZE 0x50 +#define DMA_DESCRIPTOR_ADDR 0x58 +#define DMA_SEMAPHORE_ADDR 0x60 +#define DMA_STATUS_CTRL 0x68 +#define DMASCR_GO 0x00001 +#define DMASCR_TRANSFER_READ 0x00002 +#define DMASCR_CHAIN_EN 0x00004 +#define DMASCR_SEM_EN 0x00010 +#define DMASCR_DMA_COMP_EN 0x00020 +#define DMASCR_CHAIN_COMP_EN 0x00040 +#define DMASCR_ERR_INT_EN 0x00080 +#define DMASCR_PARITY_INT_EN 0x00100 +#define DMASCR_ANY_ERR 0x00800 +#define DMASCR_MBE_ERR 0x01000 +#define DMASCR_PARITY_ERR_REP 0x02000 +#define DMASCR_PARITY_ERR_DET 0x04000 +#define DMASCR_SYSTEM_ERR_SIG 0x08000 +#define DMASCR_TARGET_ABT 0x10000 +#define DMASCR_MASTER_ABT 0x20000 +#define DMASCR_DMA_COMPLETE 0x40000 +#define DMASCR_CHAIN_COMPLETE 0x80000 + +/* +3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE +READ-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA +TRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE +TO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS +(31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6, +AN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING +DMA READ OPERATIONS. +*/ +#define DMASCR_READ 0x60000000 +#define DMASCR_READLINE 0xE0000000 +#define DMASCR_READMULTI 0xC0000000 + + +#define DMASCR_ERROR_MASK (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR | DMASCR_ANY_ERR) +#define DMASCR_HARD_ERROR (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR) + +#define WINDOWMAP_WINNUM 0x7B + +#define DMA_READ_FROM_HOST 0 +#define DMA_WRITE_TO_HOST 1 + +struct mm_dma_desc { + __le64 pci_addr; + __le64 local_addr; + __le32 transfer_size; + u32 zero1; + __le64 next_desc_addr; + __le64 sem_addr; + __le32 control_bits; + u32 zero2; + + dma_addr_t data_dma_handle; + + /* Copy of the bits */ + __le64 sem_control_bits; +} __attribute__((aligned(8))); + +/* bits for card->flags */ +#define UM_FLAG_DMA_IN_REGS 1 +#define UM_FLAG_NO_BYTE_STATUS 2 +#define UM_FLAG_NO_BATTREG 4 +#define UM_FLAG_NO_BATT 8 +#endif diff --git a/drivers/block/xsysace.c b/drivers/block/xsysace.c new file mode 100644 index 0000000000000..eb8ef65778c35 --- /dev/null +++ b/drivers/block/xsysace.c @@ -0,0 +1,1273 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Xilinx SystemACE device driver + * + * Copyright 2007 Secret Lab Technologies Ltd. + */ + +/* + * The SystemACE chip is designed to configure FPGAs by loading an FPGA + * bitstream from a file on a CF card and squirting it into FPGAs connected + * to the SystemACE JTAG chain. It also has the advantage of providing an + * MPU interface which can be used to control the FPGA configuration process + * and to use the attached CF card for general purpose storage. + * + * This driver is a block device driver for the SystemACE. + * + * Initialization: + * The driver registers itself as a platform_device driver at module + * load time. The platform bus will take care of calling the + * ace_probe() method for all SystemACE instances in the system. Any + * number of SystemACE instances are supported. ace_probe() calls + * ace_setup() which initialized all data structures, reads the CF + * id structure and registers the device. + * + * Processing: + * Just about all of the heavy lifting in this driver is performed by + * a Finite State Machine (FSM). The driver needs to wait on a number + * of events; some raised by interrupts, some which need to be polled + * for. Describing all of the behaviour in a FSM seems to be the + * easiest way to keep the complexity low and make it easy to + * understand what the driver is doing. If the block ops or the + * request function need to interact with the hardware, then they + * simply need to flag the request and kick of FSM processing. + * + * The FSM itself is atomic-safe code which can be run from any + * context. The general process flow is: + * 1. obtain the ace->lock spinlock. + * 2. loop on ace_fsm_dostate() until the ace->fsm_continue flag is + * cleared. + * 3. release the lock. + * + * Individual states do not sleep in any way. If a condition needs to + * be waited for then the state much clear the fsm_continue flag and + * either schedule the FSM to be run again at a later time, or expect + * an interrupt to call the FSM when the desired condition is met. + * + * In normal operation, the FSM is processed at interrupt context + * either when the driver's tasklet is scheduled, or when an irq is + * raised by the hardware. The tasklet can be scheduled at any time. + * The request method in particular schedules the tasklet when a new + * request has been indicated by the block layer. Once started, the + * FSM proceeds as far as it can processing the request until it + * needs on a hardware event. At this point, it must yield execution. + * + * A state has two options when yielding execution: + * 1. ace_fsm_yield() + * - Call if need to poll for event. + * - clears the fsm_continue flag to exit the processing loop + * - reschedules the tasklet to run again as soon as possible + * 2. ace_fsm_yieldirq() + * - Call if an irq is expected from the HW + * - clears the fsm_continue flag to exit the processing loop + * - does not reschedule the tasklet so the FSM will not be processed + * again until an irq is received. + * After calling a yield function, the state must return control back + * to the FSM main loop. + * + * Additionally, the driver maintains a kernel timer which can process + * the FSM. If the FSM gets stalled, typically due to a missed + * interrupt, then the kernel timer will expire and the driver can + * continue where it left off. + * + * To Do: + * - Add FPGA configuration control interface. + * - Request major number from lanana + */ + +#undef DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_OF) +#include +#include +#include +#endif + +MODULE_AUTHOR("Grant Likely "); +MODULE_DESCRIPTION("Xilinx SystemACE device driver"); +MODULE_LICENSE("GPL"); + +/* SystemACE register definitions */ +#define ACE_BUSMODE (0x00) + +#define ACE_STATUS (0x04) +#define ACE_STATUS_CFGLOCK (0x00000001) +#define ACE_STATUS_MPULOCK (0x00000002) +#define ACE_STATUS_CFGERROR (0x00000004) /* config controller error */ +#define ACE_STATUS_CFCERROR (0x00000008) /* CF controller error */ +#define ACE_STATUS_CFDETECT (0x00000010) +#define ACE_STATUS_DATABUFRDY (0x00000020) +#define ACE_STATUS_DATABUFMODE (0x00000040) +#define ACE_STATUS_CFGDONE (0x00000080) +#define ACE_STATUS_RDYFORCFCMD (0x00000100) +#define ACE_STATUS_CFGMODEPIN (0x00000200) +#define ACE_STATUS_CFGADDR_MASK (0x0000e000) +#define ACE_STATUS_CFBSY (0x00020000) +#define ACE_STATUS_CFRDY (0x00040000) +#define ACE_STATUS_CFDWF (0x00080000) +#define ACE_STATUS_CFDSC (0x00100000) +#define ACE_STATUS_CFDRQ (0x00200000) +#define ACE_STATUS_CFCORR (0x00400000) +#define ACE_STATUS_CFERR (0x00800000) + +#define ACE_ERROR (0x08) +#define ACE_CFGLBA (0x0c) +#define ACE_MPULBA (0x10) + +#define ACE_SECCNTCMD (0x14) +#define ACE_SECCNTCMD_RESET (0x0100) +#define ACE_SECCNTCMD_IDENTIFY (0x0200) +#define ACE_SECCNTCMD_READ_DATA (0x0300) +#define ACE_SECCNTCMD_WRITE_DATA (0x0400) +#define ACE_SECCNTCMD_ABORT (0x0600) + +#define ACE_VERSION (0x16) +#define ACE_VERSION_REVISION_MASK (0x00FF) +#define ACE_VERSION_MINOR_MASK (0x0F00) +#define ACE_VERSION_MAJOR_MASK (0xF000) + +#define ACE_CTRL (0x18) +#define ACE_CTRL_FORCELOCKREQ (0x0001) +#define ACE_CTRL_LOCKREQ (0x0002) +#define ACE_CTRL_FORCECFGADDR (0x0004) +#define ACE_CTRL_FORCECFGMODE (0x0008) +#define ACE_CTRL_CFGMODE (0x0010) +#define ACE_CTRL_CFGSTART (0x0020) +#define ACE_CTRL_CFGSEL (0x0040) +#define ACE_CTRL_CFGRESET (0x0080) +#define ACE_CTRL_DATABUFRDYIRQ (0x0100) +#define ACE_CTRL_ERRORIRQ (0x0200) +#define ACE_CTRL_CFGDONEIRQ (0x0400) +#define ACE_CTRL_RESETIRQ (0x0800) +#define ACE_CTRL_CFGPROG (0x1000) +#define ACE_CTRL_CFGADDR_MASK (0xe000) + +#define ACE_FATSTAT (0x1c) + +#define ACE_NUM_MINORS 16 +#define ACE_SECTOR_SIZE (512) +#define ACE_FIFO_SIZE (32) +#define ACE_BUF_PER_SECTOR (ACE_SECTOR_SIZE / ACE_FIFO_SIZE) + +#define ACE_BUS_WIDTH_8 0 +#define ACE_BUS_WIDTH_16 1 + +struct ace_reg_ops; + +struct ace_device { + /* driver state data */ + int id; + int media_change; + int users; + struct list_head list; + + /* finite state machine data */ + struct tasklet_struct fsm_tasklet; + uint fsm_task; /* Current activity (ACE_TASK_*) */ + uint fsm_state; /* Current state (ACE_FSM_STATE_*) */ + uint fsm_continue_flag; /* cleared to exit FSM mainloop */ + uint fsm_iter_num; + struct timer_list stall_timer; + + /* Transfer state/result, use for both id and block request */ + struct request *req; /* request being processed */ + void *data_ptr; /* pointer to I/O buffer */ + int data_count; /* number of buffers remaining */ + int data_result; /* Result of transfer; 0 := success */ + + int id_req_count; /* count of id requests */ + int id_result; + struct completion id_completion; /* used when id req finishes */ + int in_irq; + + /* Details of hardware device */ + resource_size_t physaddr; + void __iomem *baseaddr; + int irq; + int bus_width; /* 0 := 8 bit; 1 := 16 bit */ + struct ace_reg_ops *reg_ops; + int lock_count; + + /* Block device data structures */ + spinlock_t lock; + struct device *dev; + struct request_queue *queue; + struct gendisk *gd; + struct blk_mq_tag_set tag_set; + struct list_head rq_list; + + /* Inserted CF card parameters */ + u16 cf_id[ATA_ID_WORDS]; +}; + +static DEFINE_MUTEX(xsysace_mutex); +static int ace_major; + +/* --------------------------------------------------------------------- + * Low level register access + */ + +struct ace_reg_ops { + u16(*in) (struct ace_device * ace, int reg); + void (*out) (struct ace_device * ace, int reg, u16 val); + void (*datain) (struct ace_device * ace); + void (*dataout) (struct ace_device * ace); +}; + +/* 8 Bit bus width */ +static u16 ace_in_8(struct ace_device *ace, int reg) +{ + void __iomem *r = ace->baseaddr + reg; + return in_8(r) | (in_8(r + 1) << 8); +} + +static void ace_out_8(struct ace_device *ace, int reg, u16 val) +{ + void __iomem *r = ace->baseaddr + reg; + out_8(r, val); + out_8(r + 1, val >> 8); +} + +static void ace_datain_8(struct ace_device *ace) +{ + void __iomem *r = ace->baseaddr + 0x40; + u8 *dst = ace->data_ptr; + int i = ACE_FIFO_SIZE; + while (i--) + *dst++ = in_8(r++); + ace->data_ptr = dst; +} + +static void ace_dataout_8(struct ace_device *ace) +{ + void __iomem *r = ace->baseaddr + 0x40; + u8 *src = ace->data_ptr; + int i = ACE_FIFO_SIZE; + while (i--) + out_8(r++, *src++); + ace->data_ptr = src; +} + +static struct ace_reg_ops ace_reg_8_ops = { + .in = ace_in_8, + .out = ace_out_8, + .datain = ace_datain_8, + .dataout = ace_dataout_8, +}; + +/* 16 bit big endian bus attachment */ +static u16 ace_in_be16(struct ace_device *ace, int reg) +{ + return in_be16(ace->baseaddr + reg); +} + +static void ace_out_be16(struct ace_device *ace, int reg, u16 val) +{ + out_be16(ace->baseaddr + reg, val); +} + +static void ace_datain_be16(struct ace_device *ace) +{ + int i = ACE_FIFO_SIZE / 2; + u16 *dst = ace->data_ptr; + while (i--) + *dst++ = in_le16(ace->baseaddr + 0x40); + ace->data_ptr = dst; +} + +static void ace_dataout_be16(struct ace_device *ace) +{ + int i = ACE_FIFO_SIZE / 2; + u16 *src = ace->data_ptr; + while (i--) + out_le16(ace->baseaddr + 0x40, *src++); + ace->data_ptr = src; +} + +/* 16 bit little endian bus attachment */ +static u16 ace_in_le16(struct ace_device *ace, int reg) +{ + return in_le16(ace->baseaddr + reg); +} + +static void ace_out_le16(struct ace_device *ace, int reg, u16 val) +{ + out_le16(ace->baseaddr + reg, val); +} + +static void ace_datain_le16(struct ace_device *ace) +{ + int i = ACE_FIFO_SIZE / 2; + u16 *dst = ace->data_ptr; + while (i--) + *dst++ = in_be16(ace->baseaddr + 0x40); + ace->data_ptr = dst; +} + +static void ace_dataout_le16(struct ace_device *ace) +{ + int i = ACE_FIFO_SIZE / 2; + u16 *src = ace->data_ptr; + while (i--) + out_be16(ace->baseaddr + 0x40, *src++); + ace->data_ptr = src; +} + +static struct ace_reg_ops ace_reg_be16_ops = { + .in = ace_in_be16, + .out = ace_out_be16, + .datain = ace_datain_be16, + .dataout = ace_dataout_be16, +}; + +static struct ace_reg_ops ace_reg_le16_ops = { + .in = ace_in_le16, + .out = ace_out_le16, + .datain = ace_datain_le16, + .dataout = ace_dataout_le16, +}; + +static inline u16 ace_in(struct ace_device *ace, int reg) +{ + return ace->reg_ops->in(ace, reg); +} + +static inline u32 ace_in32(struct ace_device *ace, int reg) +{ + return ace_in(ace, reg) | (ace_in(ace, reg + 2) << 16); +} + +static inline void ace_out(struct ace_device *ace, int reg, u16 val) +{ + ace->reg_ops->out(ace, reg, val); +} + +static inline void ace_out32(struct ace_device *ace, int reg, u32 val) +{ + ace_out(ace, reg, val); + ace_out(ace, reg + 2, val >> 16); +} + +/* --------------------------------------------------------------------- + * Debug support functions + */ + +#if defined(DEBUG) +static void ace_dump_mem(void *base, int len) +{ + const char *ptr = base; + int i, j; + + for (i = 0; i < len; i += 16) { + printk(KERN_INFO "%.8x:", i); + for (j = 0; j < 16; j++) { + if (!(j % 4)) + printk(" "); + printk("%.2x", ptr[i + j]); + } + printk(" "); + for (j = 0; j < 16; j++) + printk("%c", isprint(ptr[i + j]) ? ptr[i + j] : '.'); + printk("\n"); + } +} +#else +static inline void ace_dump_mem(void *base, int len) +{ +} +#endif + +static void ace_dump_regs(struct ace_device *ace) +{ + dev_info(ace->dev, + " ctrl: %.8x seccnt/cmd: %.4x ver:%.4x\n" + " status:%.8x mpu_lba:%.8x busmode:%4x\n" + " error: %.8x cfg_lba:%.8x fatstat:%.4x\n", + ace_in32(ace, ACE_CTRL), + ace_in(ace, ACE_SECCNTCMD), + ace_in(ace, ACE_VERSION), + ace_in32(ace, ACE_STATUS), + ace_in32(ace, ACE_MPULBA), + ace_in(ace, ACE_BUSMODE), + ace_in32(ace, ACE_ERROR), + ace_in32(ace, ACE_CFGLBA), ace_in(ace, ACE_FATSTAT)); +} + +static void ace_fix_driveid(u16 *id) +{ +#if defined(__BIG_ENDIAN) + int i; + + /* All half words have wrong byte order; swap the bytes */ + for (i = 0; i < ATA_ID_WORDS; i++, id++) + *id = le16_to_cpu(*id); +#endif +} + +/* --------------------------------------------------------------------- + * Finite State Machine (FSM) implementation + */ + +/* FSM tasks; used to direct state transitions */ +#define ACE_TASK_IDLE 0 +#define ACE_TASK_IDENTIFY 1 +#define ACE_TASK_READ 2 +#define ACE_TASK_WRITE 3 +#define ACE_FSM_NUM_TASKS 4 + +/* FSM state definitions */ +#define ACE_FSM_STATE_IDLE 0 +#define ACE_FSM_STATE_REQ_LOCK 1 +#define ACE_FSM_STATE_WAIT_LOCK 2 +#define ACE_FSM_STATE_WAIT_CFREADY 3 +#define ACE_FSM_STATE_IDENTIFY_PREPARE 4 +#define ACE_FSM_STATE_IDENTIFY_TRANSFER 5 +#define ACE_FSM_STATE_IDENTIFY_COMPLETE 6 +#define ACE_FSM_STATE_REQ_PREPARE 7 +#define ACE_FSM_STATE_REQ_TRANSFER 8 +#define ACE_FSM_STATE_REQ_COMPLETE 9 +#define ACE_FSM_STATE_ERROR 10 +#define ACE_FSM_NUM_STATES 11 + +/* Set flag to exit FSM loop and reschedule tasklet */ +static inline void ace_fsm_yieldpoll(struct ace_device *ace) +{ + tasklet_schedule(&ace->fsm_tasklet); + ace->fsm_continue_flag = 0; +} + +static inline void ace_fsm_yield(struct ace_device *ace) +{ + dev_dbg(ace->dev, "%s()\n", __func__); + ace_fsm_yieldpoll(ace); +} + +/* Set flag to exit FSM loop and wait for IRQ to reschedule tasklet */ +static inline void ace_fsm_yieldirq(struct ace_device *ace) +{ + dev_dbg(ace->dev, "ace_fsm_yieldirq()\n"); + + if (ace->irq > 0) + ace->fsm_continue_flag = 0; + else + ace_fsm_yieldpoll(ace); +} + +static bool ace_has_next_request(struct request_queue *q) +{ + struct ace_device *ace = q->queuedata; + + return !list_empty(&ace->rq_list); +} + +/* Get the next read/write request; ending requests that we don't handle */ +static struct request *ace_get_next_request(struct request_queue *q) +{ + struct ace_device *ace = q->queuedata; + struct request *rq; + + rq = list_first_entry_or_null(&ace->rq_list, struct request, queuelist); + if (rq) { + list_del_init(&rq->queuelist); + blk_mq_start_request(rq); + } + + return NULL; +} + +static void ace_fsm_dostate(struct ace_device *ace) +{ + struct request *req; + u32 status; + u16 val; + int count; + +#if defined(DEBUG) + dev_dbg(ace->dev, "fsm_state=%i, id_req_count=%i\n", + ace->fsm_state, ace->id_req_count); +#endif + + /* Verify that there is actually a CF in the slot. If not, then + * bail out back to the idle state and wake up all the waiters */ + status = ace_in32(ace, ACE_STATUS); + if ((status & ACE_STATUS_CFDETECT) == 0) { + ace->fsm_state = ACE_FSM_STATE_IDLE; + ace->media_change = 1; + set_capacity(ace->gd, 0); + dev_info(ace->dev, "No CF in slot\n"); + + /* Drop all in-flight and pending requests */ + if (ace->req) { + blk_mq_end_request(ace->req, BLK_STS_IOERR); + ace->req = NULL; + } + while ((req = ace_get_next_request(ace->queue)) != NULL) + blk_mq_end_request(req, BLK_STS_IOERR); + + /* Drop back to IDLE state and notify waiters */ + ace->fsm_state = ACE_FSM_STATE_IDLE; + ace->id_result = -EIO; + while (ace->id_req_count) { + complete(&ace->id_completion); + ace->id_req_count--; + } + } + + switch (ace->fsm_state) { + case ACE_FSM_STATE_IDLE: + /* See if there is anything to do */ + if (ace->id_req_count || ace_has_next_request(ace->queue)) { + ace->fsm_iter_num++; + ace->fsm_state = ACE_FSM_STATE_REQ_LOCK; + mod_timer(&ace->stall_timer, jiffies + HZ); + if (!timer_pending(&ace->stall_timer)) + add_timer(&ace->stall_timer); + break; + } + del_timer(&ace->stall_timer); + ace->fsm_continue_flag = 0; + break; + + case ACE_FSM_STATE_REQ_LOCK: + if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) { + /* Already have the lock, jump to next state */ + ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY; + break; + } + + /* Request the lock */ + val = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, val | ACE_CTRL_LOCKREQ); + ace->fsm_state = ACE_FSM_STATE_WAIT_LOCK; + break; + + case ACE_FSM_STATE_WAIT_LOCK: + if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) { + /* got the lock; move to next state */ + ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY; + break; + } + + /* wait a bit for the lock */ + ace_fsm_yield(ace); + break; + + case ACE_FSM_STATE_WAIT_CFREADY: + status = ace_in32(ace, ACE_STATUS); + if (!(status & ACE_STATUS_RDYFORCFCMD) || + (status & ACE_STATUS_CFBSY)) { + /* CF card isn't ready; it needs to be polled */ + ace_fsm_yield(ace); + break; + } + + /* Device is ready for command; determine what to do next */ + if (ace->id_req_count) + ace->fsm_state = ACE_FSM_STATE_IDENTIFY_PREPARE; + else + ace->fsm_state = ACE_FSM_STATE_REQ_PREPARE; + break; + + case ACE_FSM_STATE_IDENTIFY_PREPARE: + /* Send identify command */ + ace->fsm_task = ACE_TASK_IDENTIFY; + ace->data_ptr = ace->cf_id; + ace->data_count = ACE_BUF_PER_SECTOR; + ace_out(ace, ACE_SECCNTCMD, ACE_SECCNTCMD_IDENTIFY); + + /* As per datasheet, put config controller in reset */ + val = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET); + + /* irq handler takes over from this point; wait for the + * transfer to complete */ + ace->fsm_state = ACE_FSM_STATE_IDENTIFY_TRANSFER; + ace_fsm_yieldirq(ace); + break; + + case ACE_FSM_STATE_IDENTIFY_TRANSFER: + /* Check that the sysace is ready to receive data */ + status = ace_in32(ace, ACE_STATUS); + if (status & ACE_STATUS_CFBSY) { + dev_dbg(ace->dev, "CFBSY set; t=%i iter=%i dc=%i\n", + ace->fsm_task, ace->fsm_iter_num, + ace->data_count); + ace_fsm_yield(ace); + break; + } + if (!(status & ACE_STATUS_DATABUFRDY)) { + ace_fsm_yield(ace); + break; + } + + /* Transfer the next buffer */ + ace->reg_ops->datain(ace); + ace->data_count--; + + /* If there are still buffers to be transfers; jump out here */ + if (ace->data_count != 0) { + ace_fsm_yieldirq(ace); + break; + } + + /* transfer finished; kick state machine */ + dev_dbg(ace->dev, "identify finished\n"); + ace->fsm_state = ACE_FSM_STATE_IDENTIFY_COMPLETE; + break; + + case ACE_FSM_STATE_IDENTIFY_COMPLETE: + ace_fix_driveid(ace->cf_id); + ace_dump_mem(ace->cf_id, 512); /* Debug: Dump out disk ID */ + + if (ace->data_result) { + /* Error occurred, disable the disk */ + ace->media_change = 1; + set_capacity(ace->gd, 0); + dev_err(ace->dev, "error fetching CF id (%i)\n", + ace->data_result); + } else { + ace->media_change = 0; + + /* Record disk parameters */ + set_capacity(ace->gd, + ata_id_u32(ace->cf_id, ATA_ID_LBA_CAPACITY)); + dev_info(ace->dev, "capacity: %i sectors\n", + ata_id_u32(ace->cf_id, ATA_ID_LBA_CAPACITY)); + } + + /* We're done, drop to IDLE state and notify waiters */ + ace->fsm_state = ACE_FSM_STATE_IDLE; + ace->id_result = ace->data_result; + while (ace->id_req_count) { + complete(&ace->id_completion); + ace->id_req_count--; + } + break; + + case ACE_FSM_STATE_REQ_PREPARE: + req = ace_get_next_request(ace->queue); + if (!req) { + ace->fsm_state = ACE_FSM_STATE_IDLE; + break; + } + + /* Okay, it's a data request, set it up for transfer */ + dev_dbg(ace->dev, + "request: sec=%llx hcnt=%x, ccnt=%x, dir=%i\n", + (unsigned long long)blk_rq_pos(req), + blk_rq_sectors(req), blk_rq_cur_sectors(req), + rq_data_dir(req)); + + ace->req = req; + ace->data_ptr = bio_data(req->bio); + ace->data_count = blk_rq_cur_sectors(req) * ACE_BUF_PER_SECTOR; + ace_out32(ace, ACE_MPULBA, blk_rq_pos(req) & 0x0FFFFFFF); + + count = blk_rq_sectors(req); + if (rq_data_dir(req)) { + /* Kick off write request */ + dev_dbg(ace->dev, "write data\n"); + ace->fsm_task = ACE_TASK_WRITE; + ace_out(ace, ACE_SECCNTCMD, + count | ACE_SECCNTCMD_WRITE_DATA); + } else { + /* Kick off read request */ + dev_dbg(ace->dev, "read data\n"); + ace->fsm_task = ACE_TASK_READ; + ace_out(ace, ACE_SECCNTCMD, + count | ACE_SECCNTCMD_READ_DATA); + } + + /* As per datasheet, put config controller in reset */ + val = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET); + + /* Move to the transfer state. The systemace will raise + * an interrupt once there is something to do + */ + ace->fsm_state = ACE_FSM_STATE_REQ_TRANSFER; + if (ace->fsm_task == ACE_TASK_READ) + ace_fsm_yieldirq(ace); /* wait for data ready */ + break; + + case ACE_FSM_STATE_REQ_TRANSFER: + /* Check that the sysace is ready to receive data */ + status = ace_in32(ace, ACE_STATUS); + if (status & ACE_STATUS_CFBSY) { + dev_dbg(ace->dev, + "CFBSY set; t=%i iter=%i c=%i dc=%i irq=%i\n", + ace->fsm_task, ace->fsm_iter_num, + blk_rq_cur_sectors(ace->req) * 16, + ace->data_count, ace->in_irq); + ace_fsm_yield(ace); /* need to poll CFBSY bit */ + break; + } + if (!(status & ACE_STATUS_DATABUFRDY)) { + dev_dbg(ace->dev, + "DATABUF not set; t=%i iter=%i c=%i dc=%i irq=%i\n", + ace->fsm_task, ace->fsm_iter_num, + blk_rq_cur_sectors(ace->req) * 16, + ace->data_count, ace->in_irq); + ace_fsm_yieldirq(ace); + break; + } + + /* Transfer the next buffer */ + if (ace->fsm_task == ACE_TASK_WRITE) + ace->reg_ops->dataout(ace); + else + ace->reg_ops->datain(ace); + ace->data_count--; + + /* If there are still buffers to be transfers; jump out here */ + if (ace->data_count != 0) { + ace_fsm_yieldirq(ace); + break; + } + + /* bio finished; is there another one? */ + if (blk_update_request(ace->req, BLK_STS_OK, + blk_rq_cur_bytes(ace->req))) { + /* dev_dbg(ace->dev, "next block; h=%u c=%u\n", + * blk_rq_sectors(ace->req), + * blk_rq_cur_sectors(ace->req)); + */ + ace->data_ptr = bio_data(ace->req->bio); + ace->data_count = blk_rq_cur_sectors(ace->req) * 16; + ace_fsm_yieldirq(ace); + break; + } + + ace->fsm_state = ACE_FSM_STATE_REQ_COMPLETE; + break; + + case ACE_FSM_STATE_REQ_COMPLETE: + ace->req = NULL; + + /* Finished request; go to idle state */ + ace->fsm_state = ACE_FSM_STATE_IDLE; + break; + + default: + ace->fsm_state = ACE_FSM_STATE_IDLE; + break; + } +} + +static void ace_fsm_tasklet(unsigned long data) +{ + struct ace_device *ace = (void *)data; + unsigned long flags; + + spin_lock_irqsave(&ace->lock, flags); + + /* Loop over state machine until told to stop */ + ace->fsm_continue_flag = 1; + while (ace->fsm_continue_flag) + ace_fsm_dostate(ace); + + spin_unlock_irqrestore(&ace->lock, flags); +} + +static void ace_stall_timer(struct timer_list *t) +{ + struct ace_device *ace = from_timer(ace, t, stall_timer); + unsigned long flags; + + dev_warn(ace->dev, + "kicking stalled fsm; state=%i task=%i iter=%i dc=%i\n", + ace->fsm_state, ace->fsm_task, ace->fsm_iter_num, + ace->data_count); + spin_lock_irqsave(&ace->lock, flags); + + /* Rearm the stall timer *before* entering FSM (which may then + * delete the timer) */ + mod_timer(&ace->stall_timer, jiffies + HZ); + + /* Loop over state machine until told to stop */ + ace->fsm_continue_flag = 1; + while (ace->fsm_continue_flag) + ace_fsm_dostate(ace); + + spin_unlock_irqrestore(&ace->lock, flags); +} + +/* --------------------------------------------------------------------- + * Interrupt handling routines + */ +static int ace_interrupt_checkstate(struct ace_device *ace) +{ + u32 sreg = ace_in32(ace, ACE_STATUS); + u16 creg = ace_in(ace, ACE_CTRL); + + /* Check for error occurrence */ + if ((sreg & (ACE_STATUS_CFGERROR | ACE_STATUS_CFCERROR)) && + (creg & ACE_CTRL_ERRORIRQ)) { + dev_err(ace->dev, "transfer failure\n"); + ace_dump_regs(ace); + return -EIO; + } + + return 0; +} + +static irqreturn_t ace_interrupt(int irq, void *dev_id) +{ + u16 creg; + struct ace_device *ace = dev_id; + + /* be safe and get the lock */ + spin_lock(&ace->lock); + ace->in_irq = 1; + + /* clear the interrupt */ + creg = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, creg | ACE_CTRL_RESETIRQ); + ace_out(ace, ACE_CTRL, creg); + + /* check for IO failures */ + if (ace_interrupt_checkstate(ace)) + ace->data_result = -EIO; + + if (ace->fsm_task == 0) { + dev_err(ace->dev, + "spurious irq; stat=%.8x ctrl=%.8x cmd=%.4x\n", + ace_in32(ace, ACE_STATUS), ace_in32(ace, ACE_CTRL), + ace_in(ace, ACE_SECCNTCMD)); + dev_err(ace->dev, "fsm_task=%i fsm_state=%i data_count=%i\n", + ace->fsm_task, ace->fsm_state, ace->data_count); + } + + /* Loop over state machine until told to stop */ + ace->fsm_continue_flag = 1; + while (ace->fsm_continue_flag) + ace_fsm_dostate(ace); + + /* done with interrupt; drop the lock */ + ace->in_irq = 0; + spin_unlock(&ace->lock); + + return IRQ_HANDLED; +} + +/* --------------------------------------------------------------------- + * Block ops + */ +static blk_status_t ace_queue_rq(struct blk_mq_hw_ctx *hctx, + const struct blk_mq_queue_data *bd) +{ + struct ace_device *ace = hctx->queue->queuedata; + struct request *req = bd->rq; + + if (blk_rq_is_passthrough(req)) { + blk_mq_start_request(req); + return BLK_STS_IOERR; + } + + spin_lock_irq(&ace->lock); + list_add_tail(&req->queuelist, &ace->rq_list); + spin_unlock_irq(&ace->lock); + + tasklet_schedule(&ace->fsm_tasklet); + return BLK_STS_OK; +} + +static unsigned int ace_check_events(struct gendisk *gd, unsigned int clearing) +{ + struct ace_device *ace = gd->private_data; + dev_dbg(ace->dev, "ace_check_events(): %i\n", ace->media_change); + + return ace->media_change ? DISK_EVENT_MEDIA_CHANGE : 0; +} + +static void ace_media_changed(struct ace_device *ace) +{ + unsigned long flags; + + dev_dbg(ace->dev, "requesting cf id and scheduling tasklet\n"); + + spin_lock_irqsave(&ace->lock, flags); + ace->id_req_count++; + spin_unlock_irqrestore(&ace->lock, flags); + + tasklet_schedule(&ace->fsm_tasklet); + wait_for_completion(&ace->id_completion); + + dev_dbg(ace->dev, "revalidate complete\n"); +} + +static int ace_open(struct block_device *bdev, fmode_t mode) +{ + struct ace_device *ace = bdev->bd_disk->private_data; + unsigned long flags; + + dev_dbg(ace->dev, "ace_open() users=%i\n", ace->users + 1); + + mutex_lock(&xsysace_mutex); + spin_lock_irqsave(&ace->lock, flags); + ace->users++; + spin_unlock_irqrestore(&ace->lock, flags); + + if (bdev_check_media_change(bdev) && ace->media_change) + ace_media_changed(ace); + mutex_unlock(&xsysace_mutex); + + return 0; +} + +static void ace_release(struct gendisk *disk, fmode_t mode) +{ + struct ace_device *ace = disk->private_data; + unsigned long flags; + u16 val; + + dev_dbg(ace->dev, "ace_release() users=%i\n", ace->users - 1); + + mutex_lock(&xsysace_mutex); + spin_lock_irqsave(&ace->lock, flags); + ace->users--; + if (ace->users == 0) { + val = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, val & ~ACE_CTRL_LOCKREQ); + } + spin_unlock_irqrestore(&ace->lock, flags); + mutex_unlock(&xsysace_mutex); +} + +static int ace_getgeo(struct block_device *bdev, struct hd_geometry *geo) +{ + struct ace_device *ace = bdev->bd_disk->private_data; + u16 *cf_id = ace->cf_id; + + dev_dbg(ace->dev, "ace_getgeo()\n"); + + geo->heads = cf_id[ATA_ID_HEADS]; + geo->sectors = cf_id[ATA_ID_SECTORS]; + geo->cylinders = cf_id[ATA_ID_CYLS]; + + return 0; +} + +static const struct block_device_operations ace_fops = { + .owner = THIS_MODULE, + .open = ace_open, + .release = ace_release, + .check_events = ace_check_events, + .getgeo = ace_getgeo, +}; + +static const struct blk_mq_ops ace_mq_ops = { + .queue_rq = ace_queue_rq, +}; + +/* -------------------------------------------------------------------- + * SystemACE device setup/teardown code + */ +static int ace_setup(struct ace_device *ace) +{ + u16 version; + u16 val; + int rc; + + dev_dbg(ace->dev, "ace_setup(ace=0x%p)\n", ace); + dev_dbg(ace->dev, "physaddr=0x%llx irq=%i\n", + (unsigned long long)ace->physaddr, ace->irq); + + spin_lock_init(&ace->lock); + init_completion(&ace->id_completion); + INIT_LIST_HEAD(&ace->rq_list); + + /* + * Map the device + */ + ace->baseaddr = ioremap(ace->physaddr, 0x80); + if (!ace->baseaddr) + goto err_ioremap; + + /* + * Initialize the state machine tasklet and stall timer + */ + tasklet_init(&ace->fsm_tasklet, ace_fsm_tasklet, (unsigned long)ace); + timer_setup(&ace->stall_timer, ace_stall_timer, 0); + + /* + * Initialize the request queue + */ + ace->queue = blk_mq_init_sq_queue(&ace->tag_set, &ace_mq_ops, 2, + BLK_MQ_F_SHOULD_MERGE); + if (IS_ERR(ace->queue)) { + rc = PTR_ERR(ace->queue); + ace->queue = NULL; + goto err_blk_initq; + } + ace->queue->queuedata = ace; + + blk_queue_logical_block_size(ace->queue, 512); + blk_queue_bounce_limit(ace->queue, BLK_BOUNCE_HIGH); + + /* + * Allocate and initialize GD structure + */ + ace->gd = alloc_disk(ACE_NUM_MINORS); + if (!ace->gd) + goto err_alloc_disk; + + ace->gd->major = ace_major; + ace->gd->first_minor = ace->id * ACE_NUM_MINORS; + ace->gd->fops = &ace_fops; + ace->gd->events = DISK_EVENT_MEDIA_CHANGE; + ace->gd->queue = ace->queue; + ace->gd->private_data = ace; + snprintf(ace->gd->disk_name, 32, "xs%c", ace->id + 'a'); + + /* set bus width */ + if (ace->bus_width == ACE_BUS_WIDTH_16) { + /* 0x0101 should work regardless of endianess */ + ace_out_le16(ace, ACE_BUSMODE, 0x0101); + + /* read it back to determine endianess */ + if (ace_in_le16(ace, ACE_BUSMODE) == 0x0001) + ace->reg_ops = &ace_reg_le16_ops; + else + ace->reg_ops = &ace_reg_be16_ops; + } else { + ace_out_8(ace, ACE_BUSMODE, 0x00); + ace->reg_ops = &ace_reg_8_ops; + } + + /* Make sure version register is sane */ + version = ace_in(ace, ACE_VERSION); + if ((version == 0) || (version == 0xFFFF)) + goto err_read; + + /* Put sysace in a sane state by clearing most control reg bits */ + ace_out(ace, ACE_CTRL, ACE_CTRL_FORCECFGMODE | + ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ); + + /* Now we can hook up the irq handler */ + if (ace->irq > 0) { + rc = request_irq(ace->irq, ace_interrupt, 0, "systemace", ace); + if (rc) { + /* Failure - fall back to polled mode */ + dev_err(ace->dev, "request_irq failed\n"); + ace->irq = rc; + } + } + + /* Enable interrupts */ + val = ace_in(ace, ACE_CTRL); + val |= ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ; + ace_out(ace, ACE_CTRL, val); + + /* Print the identification */ + dev_info(ace->dev, "Xilinx SystemACE revision %i.%i.%i\n", + (version >> 12) & 0xf, (version >> 8) & 0x0f, version & 0xff); + dev_dbg(ace->dev, "physaddr 0x%llx, mapped to 0x%p, irq=%i\n", + (unsigned long long) ace->physaddr, ace->baseaddr, ace->irq); + + ace->media_change = 1; + ace_media_changed(ace); + + /* Make the sysace device 'live' */ + add_disk(ace->gd); + + return 0; + +err_read: + /* prevent double queue cleanup */ + ace->gd->queue = NULL; + put_disk(ace->gd); +err_alloc_disk: + blk_cleanup_queue(ace->queue); + blk_mq_free_tag_set(&ace->tag_set); +err_blk_initq: + iounmap(ace->baseaddr); +err_ioremap: + dev_info(ace->dev, "xsysace: error initializing device at 0x%llx\n", + (unsigned long long) ace->physaddr); + return -ENOMEM; +} + +static void ace_teardown(struct ace_device *ace) +{ + if (ace->gd) { + del_gendisk(ace->gd); + put_disk(ace->gd); + } + + if (ace->queue) { + blk_cleanup_queue(ace->queue); + blk_mq_free_tag_set(&ace->tag_set); + } + + tasklet_kill(&ace->fsm_tasklet); + + if (ace->irq > 0) + free_irq(ace->irq, ace); + + iounmap(ace->baseaddr); +} + +static int ace_alloc(struct device *dev, int id, resource_size_t physaddr, + int irq, int bus_width) +{ + struct ace_device *ace; + int rc; + dev_dbg(dev, "ace_alloc(%p)\n", dev); + + /* Allocate and initialize the ace device structure */ + ace = kzalloc(sizeof(struct ace_device), GFP_KERNEL); + if (!ace) { + rc = -ENOMEM; + goto err_alloc; + } + + ace->dev = dev; + ace->id = id; + ace->physaddr = physaddr; + ace->irq = irq; + ace->bus_width = bus_width; + + /* Call the setup code */ + rc = ace_setup(ace); + if (rc) + goto err_setup; + + dev_set_drvdata(dev, ace); + return 0; + +err_setup: + dev_set_drvdata(dev, NULL); + kfree(ace); +err_alloc: + dev_err(dev, "could not initialize device, err=%i\n", rc); + return rc; +} + +static void ace_free(struct device *dev) +{ + struct ace_device *ace = dev_get_drvdata(dev); + dev_dbg(dev, "ace_free(%p)\n", dev); + + if (ace) { + ace_teardown(ace); + dev_set_drvdata(dev, NULL); + kfree(ace); + } +} + +/* --------------------------------------------------------------------- + * Platform Bus Support + */ + +static int ace_probe(struct platform_device *dev) +{ + int bus_width = ACE_BUS_WIDTH_16; /* FIXME: should not be hard coded */ + resource_size_t physaddr; + struct resource *res; + u32 id = dev->id; + int irq; + int i; + + dev_dbg(&dev->dev, "ace_probe(%p)\n", dev); + + /* device id and bus width */ + if (of_property_read_u32(dev->dev.of_node, "port-number", &id)) + id = 0; + if (of_find_property(dev->dev.of_node, "8-bit", NULL)) + bus_width = ACE_BUS_WIDTH_8; + + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + physaddr = res->start; + if (!physaddr) + return -ENODEV; + + irq = platform_get_irq_optional(dev, 0); + + /* Call the bus-independent setup code */ + return ace_alloc(&dev->dev, id, physaddr, irq, bus_width); +} + +/* + * Platform bus remove() method + */ +static int ace_remove(struct platform_device *dev) +{ + ace_free(&dev->dev); + return 0; +} + +#if defined(CONFIG_OF) +/* Match table for of_platform binding */ +static const struct of_device_id ace_of_match[] = { + { .compatible = "xlnx,opb-sysace-1.00.b", }, + { .compatible = "xlnx,opb-sysace-1.00.c", }, + { .compatible = "xlnx,xps-sysace-1.00.a", }, + { .compatible = "xlnx,sysace", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ace_of_match); +#else /* CONFIG_OF */ +#define ace_of_match NULL +#endif /* CONFIG_OF */ + +static struct platform_driver ace_platform_driver = { + .probe = ace_probe, + .remove = ace_remove, + .driver = { + .name = "xsysace", + .of_match_table = ace_of_match, + }, +}; + +/* --------------------------------------------------------------------- + * Module init/exit routines + */ +static int __init ace_init(void) +{ + int rc; + + ace_major = register_blkdev(ace_major, "xsysace"); + if (ace_major <= 0) { + rc = -ENOMEM; + goto err_blk; + } + + rc = platform_driver_register(&ace_platform_driver); + if (rc) + goto err_plat; + + pr_info("Xilinx SystemACE device driver, major=%i\n", ace_major); + return 0; + +err_plat: + unregister_blkdev(ace_major, "xsysace"); +err_blk: + printk(KERN_ERR "xsysace: registration failed; err=%i\n", rc); + return rc; +} +module_init(ace_init); + +static void __exit ace_exit(void) +{ + pr_debug("Unregistering Xilinx SystemACE driver\n"); + platform_driver_unregister(&ace_platform_driver); + unregister_blkdev(ace_major, "xsysace"); +} +module_exit(ace_exit); diff --git a/drivers/extcon/extcon-arizona.c b/drivers/extcon/extcon-arizona.c new file mode 100644 index 0000000000000..aae82db542a5e --- /dev/null +++ b/drivers/extcon/extcon-arizona.c @@ -0,0 +1,1816 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * extcon-arizona.c - Extcon driver Wolfson Arizona devices + * + * Copyright (C) 2012-2014 Wolfson Microelectronics plc + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#define ARIZONA_MAX_MICD_RANGE 8 + +#define ARIZONA_MICD_CLAMP_MODE_JDL 0x4 +#define ARIZONA_MICD_CLAMP_MODE_JDH 0x5 +#define ARIZONA_MICD_CLAMP_MODE_JDL_GP5H 0x9 +#define ARIZONA_MICD_CLAMP_MODE_JDH_GP5H 0xb + +#define ARIZONA_TST_CAP_DEFAULT 0x3 +#define ARIZONA_TST_CAP_CLAMP 0x1 + +#define ARIZONA_HPDET_MAX 10000 + +#define HPDET_DEBOUNCE 500 +#define DEFAULT_MICD_TIMEOUT 2000 + +#define ARIZONA_HPDET_WAIT_COUNT 15 +#define ARIZONA_HPDET_WAIT_DELAY_MS 20 + +#define QUICK_HEADPHONE_MAX_OHM 3 +#define MICROPHONE_MIN_OHM 1257 +#define MICROPHONE_MAX_OHM 30000 + +#define MICD_DBTIME_TWO_READINGS 2 +#define MICD_DBTIME_FOUR_READINGS 4 + +#define MICD_LVL_1_TO_7 (ARIZONA_MICD_LVL_1 | ARIZONA_MICD_LVL_2 | \ + ARIZONA_MICD_LVL_3 | ARIZONA_MICD_LVL_4 | \ + ARIZONA_MICD_LVL_5 | ARIZONA_MICD_LVL_6 | \ + ARIZONA_MICD_LVL_7) + +#define MICD_LVL_0_TO_7 (ARIZONA_MICD_LVL_0 | MICD_LVL_1_TO_7) + +#define MICD_LVL_0_TO_8 (MICD_LVL_0_TO_7 | ARIZONA_MICD_LVL_8) + +struct arizona_extcon_info { + struct device *dev; + struct arizona *arizona; + struct mutex lock; + struct regulator *micvdd; + struct input_dev *input; + + u16 last_jackdet; + + int micd_mode; + const struct arizona_micd_config *micd_modes; + int micd_num_modes; + + const struct arizona_micd_range *micd_ranges; + int num_micd_ranges; + + bool micd_reva; + bool micd_clamp; + + struct delayed_work hpdet_work; + struct delayed_work micd_detect_work; + struct delayed_work micd_timeout_work; + + bool hpdet_active; + bool hpdet_done; + bool hpdet_retried; + + int num_hpdet_res; + unsigned int hpdet_res[3]; + + bool mic; + bool detecting; + int jack_flips; + + int hpdet_ip_version; + + struct extcon_dev *edev; + + struct gpio_desc *micd_pol_gpio; +}; + +static const struct arizona_micd_config micd_default_modes[] = { + { ARIZONA_ACCDET_SRC, 1, 0 }, + { 0, 2, 1 }, +}; + +static const struct arizona_micd_range micd_default_ranges[] = { + { .max = 11, .key = BTN_0 }, + { .max = 28, .key = BTN_1 }, + { .max = 54, .key = BTN_2 }, + { .max = 100, .key = BTN_3 }, + { .max = 186, .key = BTN_4 }, + { .max = 430, .key = BTN_5 }, +}; + +/* The number of levels in arizona_micd_levels valid for button thresholds */ +#define ARIZONA_NUM_MICD_BUTTON_LEVELS 64 + +static const int arizona_micd_levels[] = { + 3, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 34, 36, 39, 41, 44, 46, + 49, 52, 54, 57, 60, 62, 65, 67, 70, 73, 75, 78, 81, 83, 89, 94, 100, + 105, 111, 116, 122, 127, 139, 150, 161, 173, 186, 196, 209, 220, 245, + 270, 295, 321, 348, 375, 402, 430, 489, 550, 614, 681, 752, 903, 1071, + 1257, 30000, +}; + +static const unsigned int arizona_cable[] = { + EXTCON_MECHANICAL, + EXTCON_JACK_MICROPHONE, + EXTCON_JACK_HEADPHONE, + EXTCON_JACK_LINE_OUT, + EXTCON_NONE, +}; + +static void arizona_start_hpdet_acc_id(struct arizona_extcon_info *info); + +static void arizona_extcon_hp_clamp(struct arizona_extcon_info *info, + bool clamp) +{ + struct arizona *arizona = info->arizona; + unsigned int mask = 0, val = 0; + unsigned int cap_sel = 0; + int ret; + + switch (arizona->type) { + case WM8998: + case WM1814: + mask = 0; + break; + case WM5110: + case WM8280: + mask = ARIZONA_HP1L_SHRTO | ARIZONA_HP1L_FLWR | + ARIZONA_HP1L_SHRTI; + if (clamp) { + val = ARIZONA_HP1L_SHRTO; + cap_sel = ARIZONA_TST_CAP_CLAMP; + } else { + val = ARIZONA_HP1L_FLWR | ARIZONA_HP1L_SHRTI; + cap_sel = ARIZONA_TST_CAP_DEFAULT; + } + + ret = regmap_update_bits(arizona->regmap, + ARIZONA_HP_TEST_CTRL_1, + ARIZONA_HP1_TST_CAP_SEL_MASK, + cap_sel); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to set TST_CAP_SEL: %d\n", ret); + break; + default: + mask = ARIZONA_RMV_SHRT_HP1L; + if (clamp) + val = ARIZONA_RMV_SHRT_HP1L; + break; + } + + snd_soc_dapm_mutex_lock(arizona->dapm); + + arizona->hpdet_clamp = clamp; + + /* Keep the HP output stages disabled while doing the clamp */ + if (clamp) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT1L_ENA | + ARIZONA_OUT1R_ENA, 0); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to disable headphone outputs: %d\n", + ret); + } + + if (mask) { + ret = regmap_update_bits(arizona->regmap, ARIZONA_HP_CTRL_1L, + mask, val); + if (ret != 0) + dev_warn(arizona->dev, "Failed to do clamp: %d\n", + ret); + + ret = regmap_update_bits(arizona->regmap, ARIZONA_HP_CTRL_1R, + mask, val); + if (ret != 0) + dev_warn(arizona->dev, "Failed to do clamp: %d\n", + ret); + } + + /* Restore the desired state while not doing the clamp */ + if (!clamp) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT1L_ENA | + ARIZONA_OUT1R_ENA, arizona->hp_ena); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to restore headphone outputs: %d\n", + ret); + } + + snd_soc_dapm_mutex_unlock(arizona->dapm); +} + +static void arizona_extcon_set_mode(struct arizona_extcon_info *info, int mode) +{ + struct arizona *arizona = info->arizona; + + mode %= info->micd_num_modes; + + gpiod_set_value_cansleep(info->micd_pol_gpio, + info->micd_modes[mode].gpio); + + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_BIAS_SRC_MASK, + info->micd_modes[mode].bias << + ARIZONA_MICD_BIAS_SRC_SHIFT); + regmap_update_bits(arizona->regmap, ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_SRC, info->micd_modes[mode].src); + + info->micd_mode = mode; + + dev_dbg(arizona->dev, "Set jack polarity to %d\n", mode); +} + +static const char *arizona_extcon_get_micbias(struct arizona_extcon_info *info) +{ + switch (info->micd_modes[0].bias) { + case 1: + return "MICBIAS1"; + case 2: + return "MICBIAS2"; + case 3: + return "MICBIAS3"; + default: + return "MICVDD"; + } +} + +static void arizona_extcon_pulse_micbias(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + const char *widget = arizona_extcon_get_micbias(info); + struct snd_soc_dapm_context *dapm = arizona->dapm; + struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); + int ret; + + ret = snd_soc_component_force_enable_pin(component, widget); + if (ret != 0) + dev_warn(arizona->dev, "Failed to enable %s: %d\n", + widget, ret); + + snd_soc_dapm_sync(dapm); + + if (!arizona->pdata.micd_force_micbias) { + ret = snd_soc_component_disable_pin(component, widget); + if (ret != 0) + dev_warn(arizona->dev, "Failed to disable %s: %d\n", + widget, ret); + + snd_soc_dapm_sync(dapm); + } +} + +static void arizona_start_mic(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + bool change; + int ret; + unsigned int mode; + + /* Microphone detection can't use idle mode */ + pm_runtime_get(info->dev); + + if (info->detecting) { + ret = regulator_allow_bypass(info->micvdd, false); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to regulate MICVDD: %d\n", + ret); + } + } + + ret = regulator_enable(info->micvdd); + if (ret != 0) { + dev_err(arizona->dev, "Failed to enable MICVDD: %d\n", + ret); + } + + if (info->micd_reva) { + const struct reg_sequence reva[] = { + { 0x80, 0x3 }, + { 0x294, 0x0 }, + { 0x80, 0x0 }, + }; + + regmap_multi_reg_write(arizona->regmap, reva, ARRAY_SIZE(reva)); + } + + if (info->detecting && arizona->pdata.micd_software_compare) + mode = ARIZONA_ACCDET_MODE_ADC; + else + mode = ARIZONA_ACCDET_MODE_MIC; + + regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_MODE_MASK, mode); + + arizona_extcon_pulse_micbias(info); + + ret = regmap_update_bits_check(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, ARIZONA_MICD_ENA, + &change); + if (ret < 0) { + dev_err(arizona->dev, "Failed to enable micd: %d\n", ret); + } else if (!change) { + regulator_disable(info->micvdd); + pm_runtime_put_autosuspend(info->dev); + } +} + +static void arizona_stop_mic(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + const char *widget = arizona_extcon_get_micbias(info); + struct snd_soc_dapm_context *dapm = arizona->dapm; + struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); + bool change = false; + int ret; + + ret = regmap_update_bits_check(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, 0, + &change); + if (ret < 0) + dev_err(arizona->dev, "Failed to disable micd: %d\n", ret); + + ret = snd_soc_component_disable_pin(component, widget); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to disable %s: %d\n", + widget, ret); + + snd_soc_dapm_sync(dapm); + + if (info->micd_reva) { + const struct reg_sequence reva[] = { + { 0x80, 0x3 }, + { 0x294, 0x2 }, + { 0x80, 0x0 }, + }; + + regmap_multi_reg_write(arizona->regmap, reva, ARRAY_SIZE(reva)); + } + + ret = regulator_allow_bypass(info->micvdd, true); + if (ret != 0) { + dev_err(arizona->dev, "Failed to bypass MICVDD: %d\n", + ret); + } + + if (change) { + regulator_disable(info->micvdd); + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); + } +} + +static struct { + unsigned int threshold; + unsigned int factor_a; + unsigned int factor_b; +} arizona_hpdet_b_ranges[] = { + { 100, 5528, 362464 }, + { 169, 11084, 6186851 }, + { 169, 11065, 65460395 }, +}; + +#define ARIZONA_HPDET_B_RANGE_MAX 0x3fb + +static struct { + int min; + int max; +} arizona_hpdet_c_ranges[] = { + { 0, 30 }, + { 8, 100 }, + { 100, 1000 }, + { 1000, 10000 }, +}; + +static int arizona_hpdet_read(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val, range; + int ret; + + ret = regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_2, &val); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read HPDET status: %d\n", + ret); + return ret; + } + + switch (info->hpdet_ip_version) { + case 0: + if (!(val & ARIZONA_HP_DONE)) { + dev_err(arizona->dev, "HPDET did not complete: %x\n", + val); + return -EAGAIN; + } + + val &= ARIZONA_HP_LVL_MASK; + break; + + case 1: + if (!(val & ARIZONA_HP_DONE_B)) { + dev_err(arizona->dev, "HPDET did not complete: %x\n", + val); + return -EAGAIN; + } + + ret = regmap_read(arizona->regmap, ARIZONA_HP_DACVAL, &val); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read HP value: %d\n", + ret); + return -EAGAIN; + } + + regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + &range); + range = (range & ARIZONA_HP_IMPEDANCE_RANGE_MASK) + >> ARIZONA_HP_IMPEDANCE_RANGE_SHIFT; + + if (range < ARRAY_SIZE(arizona_hpdet_b_ranges) - 1 && + (val < arizona_hpdet_b_ranges[range].threshold || + val >= ARIZONA_HPDET_B_RANGE_MAX)) { + range++; + dev_dbg(arizona->dev, "Moving to HPDET range %d\n", + range); + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK, + range << + ARIZONA_HP_IMPEDANCE_RANGE_SHIFT); + return -EAGAIN; + } + + /* If we go out of range report top of range */ + if (val < arizona_hpdet_b_ranges[range].threshold || + val >= ARIZONA_HPDET_B_RANGE_MAX) { + dev_dbg(arizona->dev, "Measurement out of range\n"); + return ARIZONA_HPDET_MAX; + } + + dev_dbg(arizona->dev, "HPDET read %d in range %d\n", + val, range); + + val = arizona_hpdet_b_ranges[range].factor_b + / ((val * 100) - + arizona_hpdet_b_ranges[range].factor_a); + break; + + case 2: + if (!(val & ARIZONA_HP_DONE_B)) { + dev_err(arizona->dev, "HPDET did not complete: %x\n", + val); + return -EAGAIN; + } + + val &= ARIZONA_HP_LVL_B_MASK; + /* Convert to ohms, the value is in 0.5 ohm increments */ + val /= 2; + + regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + &range); + range = (range & ARIZONA_HP_IMPEDANCE_RANGE_MASK) + >> ARIZONA_HP_IMPEDANCE_RANGE_SHIFT; + + /* Skip up a range, or report? */ + if (range < ARRAY_SIZE(arizona_hpdet_c_ranges) - 1 && + (val >= arizona_hpdet_c_ranges[range].max)) { + range++; + dev_dbg(arizona->dev, "Moving to HPDET range %d-%d\n", + arizona_hpdet_c_ranges[range].min, + arizona_hpdet_c_ranges[range].max); + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK, + range << + ARIZONA_HP_IMPEDANCE_RANGE_SHIFT); + return -EAGAIN; + } + + if (range && (val < arizona_hpdet_c_ranges[range].min)) { + dev_dbg(arizona->dev, "Reporting range boundary %d\n", + arizona_hpdet_c_ranges[range].min); + val = arizona_hpdet_c_ranges[range].min; + } + break; + + default: + dev_warn(arizona->dev, "Unknown HPDET IP revision %d\n", + info->hpdet_ip_version); + return -EINVAL; + } + + dev_dbg(arizona->dev, "HP impedance %d ohms\n", val); + return val; +} + +static int arizona_hpdet_do_id(struct arizona_extcon_info *info, int *reading, + bool *mic) +{ + struct arizona *arizona = info->arizona; + int id_gpio = arizona->pdata.hpdet_id_gpio; + + if (!arizona->pdata.hpdet_acc_id) + return 0; + + /* + * If we're using HPDET for accessory identification we need + * to take multiple measurements, step through them in sequence. + */ + info->hpdet_res[info->num_hpdet_res++] = *reading; + + /* Only check the mic directly if we didn't already ID it */ + if (id_gpio && info->num_hpdet_res == 1) { + dev_dbg(arizona->dev, "Measuring mic\n"); + + regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_MODE_MASK | + ARIZONA_ACCDET_SRC, + ARIZONA_ACCDET_MODE_HPR | + info->micd_modes[0].src); + + gpio_set_value_cansleep(id_gpio, 1); + + regmap_update_bits(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_POLL, ARIZONA_HP_POLL); + return -EAGAIN; + } + + /* OK, got both. Now, compare... */ + dev_dbg(arizona->dev, "HPDET measured %d %d\n", + info->hpdet_res[0], info->hpdet_res[1]); + + /* Take the headphone impedance for the main report */ + *reading = info->hpdet_res[0]; + + /* Sometimes we get false readings due to slow insert */ + if (*reading >= ARIZONA_HPDET_MAX && !info->hpdet_retried) { + dev_dbg(arizona->dev, "Retrying high impedance\n"); + info->num_hpdet_res = 0; + info->hpdet_retried = true; + arizona_start_hpdet_acc_id(info); + pm_runtime_put(info->dev); + return -EAGAIN; + } + + /* + * If we measure the mic as high impedance + */ + if (!id_gpio || info->hpdet_res[1] > 50) { + dev_dbg(arizona->dev, "Detected mic\n"); + *mic = true; + info->detecting = true; + } else { + dev_dbg(arizona->dev, "Detected headphone\n"); + } + + /* Make sure everything is reset back to the real polarity */ + regmap_update_bits(arizona->regmap, ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_SRC, info->micd_modes[0].src); + + return 0; +} + +static irqreturn_t arizona_hpdet_irq(int irq, void *data) +{ + struct arizona_extcon_info *info = data; + struct arizona *arizona = info->arizona; + int id_gpio = arizona->pdata.hpdet_id_gpio; + unsigned int report = EXTCON_JACK_HEADPHONE; + int ret, reading; + bool mic = false; + + mutex_lock(&info->lock); + + /* If we got a spurious IRQ for some reason then ignore it */ + if (!info->hpdet_active) { + dev_warn(arizona->dev, "Spurious HPDET IRQ\n"); + mutex_unlock(&info->lock); + return IRQ_NONE; + } + + /* If the cable was removed while measuring ignore the result */ + ret = extcon_get_state(info->edev, EXTCON_MECHANICAL); + if (ret < 0) { + dev_err(arizona->dev, "Failed to check cable state: %d\n", + ret); + goto out; + } else if (!ret) { + dev_dbg(arizona->dev, "Ignoring HPDET for removed cable\n"); + goto done; + } + + ret = arizona_hpdet_read(info); + if (ret == -EAGAIN) + goto out; + else if (ret < 0) + goto done; + reading = ret; + + /* Reset back to starting range */ + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK | ARIZONA_HP_POLL, + 0); + + ret = arizona_hpdet_do_id(info, &reading, &mic); + if (ret == -EAGAIN) + goto out; + else if (ret < 0) + goto done; + + /* Report high impedence cables as line outputs */ + if (reading >= 5000) + report = EXTCON_JACK_LINE_OUT; + else + report = EXTCON_JACK_HEADPHONE; + + ret = extcon_set_state_sync(info->edev, report, true); + if (ret != 0) + dev_err(arizona->dev, "Failed to report HP/line: %d\n", + ret); + +done: + /* Reset back to starting range */ + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK | ARIZONA_HP_POLL, + 0); + + arizona_extcon_hp_clamp(info, false); + + if (id_gpio) + gpio_set_value_cansleep(id_gpio, 0); + + /* If we have a mic then reenable MICDET */ + if (mic || info->mic) + arizona_start_mic(info); + + if (info->hpdet_active) { + pm_runtime_put_autosuspend(info->dev); + info->hpdet_active = false; + } + + info->hpdet_done = true; + +out: + mutex_unlock(&info->lock); + + return IRQ_HANDLED; +} + +static void arizona_identify_headphone(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + int ret; + + if (info->hpdet_done) + return; + + dev_dbg(arizona->dev, "Starting HPDET\n"); + + /* Make sure we keep the device enabled during the measurement */ + pm_runtime_get(info->dev); + + info->hpdet_active = true; + + arizona_stop_mic(info); + + arizona_extcon_hp_clamp(info, true); + + ret = regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_MODE_MASK, + arizona->pdata.hpdet_channel); + if (ret != 0) { + dev_err(arizona->dev, "Failed to set HPDET mode: %d\n", ret); + goto err; + } + + ret = regmap_update_bits(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_POLL, ARIZONA_HP_POLL); + if (ret != 0) { + dev_err(arizona->dev, "Can't start HPDETL measurement: %d\n", + ret); + goto err; + } + + return; + +err: + arizona_extcon_hp_clamp(info, false); + pm_runtime_put_autosuspend(info->dev); + + /* Just report headphone */ + ret = extcon_set_state_sync(info->edev, EXTCON_JACK_HEADPHONE, true); + if (ret != 0) + dev_err(arizona->dev, "Failed to report headphone: %d\n", ret); + + if (info->mic) + arizona_start_mic(info); + + info->hpdet_active = false; +} + +static void arizona_start_hpdet_acc_id(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + int hp_reading = 32; + bool mic; + int ret; + + dev_dbg(arizona->dev, "Starting identification via HPDET\n"); + + /* Make sure we keep the device enabled during the measurement */ + pm_runtime_get_sync(info->dev); + + info->hpdet_active = true; + + arizona_extcon_hp_clamp(info, true); + + ret = regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_SRC | ARIZONA_ACCDET_MODE_MASK, + info->micd_modes[0].src | + arizona->pdata.hpdet_channel); + if (ret != 0) { + dev_err(arizona->dev, "Failed to set HPDET mode: %d\n", ret); + goto err; + } + + if (arizona->pdata.hpdet_acc_id_line) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_POLL, ARIZONA_HP_POLL); + if (ret != 0) { + dev_err(arizona->dev, + "Can't start HPDETL measurement: %d\n", + ret); + goto err; + } + } else { + arizona_hpdet_do_id(info, &hp_reading, &mic); + } + + return; + +err: + /* Just report headphone */ + ret = extcon_set_state_sync(info->edev, EXTCON_JACK_HEADPHONE, true); + if (ret != 0) + dev_err(arizona->dev, "Failed to report headphone: %d\n", ret); + + info->hpdet_active = false; +} + +static void arizona_micd_timeout_work(struct work_struct *work) +{ + struct arizona_extcon_info *info = container_of(work, + struct arizona_extcon_info, + micd_timeout_work.work); + + mutex_lock(&info->lock); + + dev_dbg(info->arizona->dev, "MICD timed out, reporting HP\n"); + + info->detecting = false; + + arizona_identify_headphone(info); + + mutex_unlock(&info->lock); +} + +static int arizona_micd_adc_read(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val; + int ret; + + /* Must disable MICD before we read the ADCVAL */ + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, 0); + + ret = regmap_read(arizona->regmap, ARIZONA_MIC_DETECT_4, &val); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to read MICDET_ADCVAL: %d\n", ret); + return ret; + } + + dev_dbg(arizona->dev, "MICDET_ADCVAL: %x\n", val); + + val &= ARIZONA_MICDET_ADCVAL_MASK; + if (val < ARRAY_SIZE(arizona_micd_levels)) + val = arizona_micd_levels[val]; + else + val = INT_MAX; + + if (val <= QUICK_HEADPHONE_MAX_OHM) + val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_0; + else if (val <= MICROPHONE_MIN_OHM) + val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_1; + else if (val <= MICROPHONE_MAX_OHM) + val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_8; + else + val = ARIZONA_MICD_LVL_8; + + return val; +} + +static int arizona_micd_read(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val = 0; + int ret, i; + + for (i = 0; i < 10 && !(val & MICD_LVL_0_TO_8); i++) { + ret = regmap_read(arizona->regmap, ARIZONA_MIC_DETECT_3, &val); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to read MICDET: %d\n", ret); + return ret; + } + + dev_dbg(arizona->dev, "MICDET: %x\n", val); + + if (!(val & ARIZONA_MICD_VALID)) { + dev_warn(arizona->dev, + "Microphone detection state invalid\n"); + return -EINVAL; + } + } + + if (i == 10 && !(val & MICD_LVL_0_TO_8)) { + dev_err(arizona->dev, "Failed to get valid MICDET value\n"); + return -EINVAL; + } + + return val; +} + +static int arizona_micdet_reading(void *priv) +{ + struct arizona_extcon_info *info = priv; + struct arizona *arizona = info->arizona; + int ret, val; + + if (info->detecting && arizona->pdata.micd_software_compare) + ret = arizona_micd_adc_read(info); + else + ret = arizona_micd_read(info); + if (ret < 0) + return ret; + + val = ret; + + /* Due to jack detect this should never happen */ + if (!(val & ARIZONA_MICD_STS)) { + dev_warn(arizona->dev, "Detected open circuit\n"); + info->mic = false; + info->detecting = false; + arizona_identify_headphone(info); + return 0; + } + + /* If we got a high impedence we should have a headset, report it. */ + if (val & ARIZONA_MICD_LVL_8) { + info->mic = true; + info->detecting = false; + + arizona_identify_headphone(info); + + ret = extcon_set_state_sync(info->edev, + EXTCON_JACK_MICROPHONE, true); + if (ret != 0) + dev_err(arizona->dev, "Headset report failed: %d\n", + ret); + + /* Don't need to regulate for button detection */ + ret = regulator_allow_bypass(info->micvdd, true); + if (ret != 0) { + dev_err(arizona->dev, "Failed to bypass MICVDD: %d\n", + ret); + } + + return 0; + } + + /* If we detected a lower impedence during initial startup + * then we probably have the wrong polarity, flip it. Don't + * do this for the lowest impedences to speed up detection of + * plain headphones. If both polarities report a low + * impedence then give up and report headphones. + */ + if (val & MICD_LVL_1_TO_7) { + if (info->jack_flips >= info->micd_num_modes * 10) { + dev_dbg(arizona->dev, "Detected HP/line\n"); + + info->detecting = false; + + arizona_identify_headphone(info); + } else { + info->micd_mode++; + if (info->micd_mode == info->micd_num_modes) + info->micd_mode = 0; + arizona_extcon_set_mode(info, info->micd_mode); + + info->jack_flips++; + + if (arizona->pdata.micd_software_compare) + regmap_update_bits(arizona->regmap, + ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, + ARIZONA_MICD_ENA); + + queue_delayed_work(system_power_efficient_wq, + &info->micd_timeout_work, + msecs_to_jiffies(arizona->pdata.micd_timeout)); + } + + return 0; + } + + /* + * If we're still detecting and we detect a short then we've + * got a headphone. + */ + dev_dbg(arizona->dev, "Headphone detected\n"); + info->detecting = false; + + arizona_identify_headphone(info); + + return 0; +} + +static int arizona_button_reading(void *priv) +{ + struct arizona_extcon_info *info = priv; + struct arizona *arizona = info->arizona; + int val, key, lvl, i; + + val = arizona_micd_read(info); + if (val < 0) + return val; + + /* + * If we're still detecting and we detect a short then we've + * got a headphone. Otherwise it's a button press. + */ + if (val & MICD_LVL_0_TO_7) { + if (info->mic) { + dev_dbg(arizona->dev, "Mic button detected\n"); + + lvl = val & ARIZONA_MICD_LVL_MASK; + lvl >>= ARIZONA_MICD_LVL_SHIFT; + + for (i = 0; i < info->num_micd_ranges; i++) + input_report_key(info->input, + info->micd_ranges[i].key, 0); + + if (lvl && ffs(lvl) - 1 < info->num_micd_ranges) { + key = info->micd_ranges[ffs(lvl) - 1].key; + input_report_key(info->input, key, 1); + input_sync(info->input); + } else { + dev_err(arizona->dev, "Button out of range\n"); + } + } else { + dev_warn(arizona->dev, "Button with no mic: %x\n", + val); + } + } else { + dev_dbg(arizona->dev, "Mic button released\n"); + for (i = 0; i < info->num_micd_ranges; i++) + input_report_key(info->input, + info->micd_ranges[i].key, 0); + input_sync(info->input); + arizona_extcon_pulse_micbias(info); + } + + return 0; +} + +static void arizona_micd_detect(struct work_struct *work) +{ + struct arizona_extcon_info *info = container_of(work, + struct arizona_extcon_info, + micd_detect_work.work); + struct arizona *arizona = info->arizona; + int ret; + + cancel_delayed_work_sync(&info->micd_timeout_work); + + mutex_lock(&info->lock); + + /* If the cable was removed while measuring ignore the result */ + ret = extcon_get_state(info->edev, EXTCON_MECHANICAL); + if (ret < 0) { + dev_err(arizona->dev, "Failed to check cable state: %d\n", + ret); + mutex_unlock(&info->lock); + return; + } else if (!ret) { + dev_dbg(arizona->dev, "Ignoring MICDET for removed cable\n"); + mutex_unlock(&info->lock); + return; + } + + if (info->detecting) + arizona_micdet_reading(info); + else + arizona_button_reading(info); + + pm_runtime_mark_last_busy(info->dev); + mutex_unlock(&info->lock); +} + +static irqreturn_t arizona_micdet(int irq, void *data) +{ + struct arizona_extcon_info *info = data; + struct arizona *arizona = info->arizona; + int debounce = arizona->pdata.micd_detect_debounce; + + cancel_delayed_work_sync(&info->micd_detect_work); + cancel_delayed_work_sync(&info->micd_timeout_work); + + mutex_lock(&info->lock); + if (!info->detecting) + debounce = 0; + mutex_unlock(&info->lock); + + if (debounce) + queue_delayed_work(system_power_efficient_wq, + &info->micd_detect_work, + msecs_to_jiffies(debounce)); + else + arizona_micd_detect(&info->micd_detect_work.work); + + return IRQ_HANDLED; +} + +static void arizona_hpdet_work(struct work_struct *work) +{ + struct arizona_extcon_info *info = container_of(work, + struct arizona_extcon_info, + hpdet_work.work); + + mutex_lock(&info->lock); + arizona_start_hpdet_acc_id(info); + mutex_unlock(&info->lock); +} + +static int arizona_hpdet_wait(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val; + int i, ret; + + for (i = 0; i < ARIZONA_HPDET_WAIT_COUNT; i++) { + ret = regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_2, + &val); + if (ret) { + dev_err(arizona->dev, + "Failed to read HPDET state: %d\n", ret); + return ret; + } + + switch (info->hpdet_ip_version) { + case 0: + if (val & ARIZONA_HP_DONE) + return 0; + break; + default: + if (val & ARIZONA_HP_DONE_B) + return 0; + break; + } + + msleep(ARIZONA_HPDET_WAIT_DELAY_MS); + } + + dev_warn(arizona->dev, "HPDET did not appear to complete\n"); + + return -ETIMEDOUT; +} + +static irqreturn_t arizona_jackdet(int irq, void *data) +{ + struct arizona_extcon_info *info = data; + struct arizona *arizona = info->arizona; + unsigned int val, present, mask; + bool cancelled_hp, cancelled_mic; + int ret, i; + + cancelled_hp = cancel_delayed_work_sync(&info->hpdet_work); + cancelled_mic = cancel_delayed_work_sync(&info->micd_timeout_work); + + pm_runtime_get_sync(info->dev); + + mutex_lock(&info->lock); + + if (info->micd_clamp) { + mask = ARIZONA_MICD_CLAMP_STS; + present = 0; + } else { + mask = ARIZONA_JD1_STS; + if (arizona->pdata.jd_invert) + present = 0; + else + present = ARIZONA_JD1_STS; + } + + ret = regmap_read(arizona->regmap, ARIZONA_AOD_IRQ_RAW_STATUS, &val); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read jackdet status: %d\n", + ret); + mutex_unlock(&info->lock); + pm_runtime_put_autosuspend(info->dev); + return IRQ_NONE; + } + + val &= mask; + if (val == info->last_jackdet) { + dev_dbg(arizona->dev, "Suppressing duplicate JACKDET\n"); + if (cancelled_hp) + queue_delayed_work(system_power_efficient_wq, + &info->hpdet_work, + msecs_to_jiffies(HPDET_DEBOUNCE)); + + if (cancelled_mic) { + int micd_timeout = arizona->pdata.micd_timeout; + + queue_delayed_work(system_power_efficient_wq, + &info->micd_timeout_work, + msecs_to_jiffies(micd_timeout)); + } + + goto out; + } + info->last_jackdet = val; + + if (info->last_jackdet == present) { + dev_dbg(arizona->dev, "Detected jack\n"); + ret = extcon_set_state_sync(info->edev, + EXTCON_MECHANICAL, true); + + if (ret != 0) + dev_err(arizona->dev, "Mechanical report failed: %d\n", + ret); + + info->detecting = true; + info->mic = false; + info->jack_flips = 0; + + if (!arizona->pdata.hpdet_acc_id) { + arizona_start_mic(info); + } else { + queue_delayed_work(system_power_efficient_wq, + &info->hpdet_work, + msecs_to_jiffies(HPDET_DEBOUNCE)); + } + + if (info->micd_clamp || !arizona->pdata.jd_invert) + regmap_update_bits(arizona->regmap, + ARIZONA_JACK_DETECT_DEBOUNCE, + ARIZONA_MICD_CLAMP_DB | + ARIZONA_JD1_DB, 0); + } else { + dev_dbg(arizona->dev, "Detected jack removal\n"); + + arizona_stop_mic(info); + + info->num_hpdet_res = 0; + for (i = 0; i < ARRAY_SIZE(info->hpdet_res); i++) + info->hpdet_res[i] = 0; + info->mic = false; + info->hpdet_done = false; + info->hpdet_retried = false; + + for (i = 0; i < info->num_micd_ranges; i++) + input_report_key(info->input, + info->micd_ranges[i].key, 0); + input_sync(info->input); + + for (i = 0; i < ARRAY_SIZE(arizona_cable) - 1; i++) { + ret = extcon_set_state_sync(info->edev, + arizona_cable[i], false); + if (ret != 0) + dev_err(arizona->dev, + "Removal report failed: %d\n", ret); + } + + /* + * If the jack was removed during a headphone detection we + * need to wait for the headphone detection to finish, as + * it can not be aborted. We don't want to be able to start + * a new headphone detection from a fresh insert until this + * one is finished. + */ + arizona_hpdet_wait(info); + + regmap_update_bits(arizona->regmap, + ARIZONA_JACK_DETECT_DEBOUNCE, + ARIZONA_MICD_CLAMP_DB | ARIZONA_JD1_DB, + ARIZONA_MICD_CLAMP_DB | ARIZONA_JD1_DB); + } + +out: + /* Clear trig_sts to make sure DCVDD is not forced up */ + regmap_write(arizona->regmap, ARIZONA_AOD_WKUP_AND_TRIG, + ARIZONA_MICD_CLAMP_FALL_TRIG_STS | + ARIZONA_MICD_CLAMP_RISE_TRIG_STS | + ARIZONA_JD1_FALL_TRIG_STS | + ARIZONA_JD1_RISE_TRIG_STS); + + mutex_unlock(&info->lock); + + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); + + return IRQ_HANDLED; +} + +/* Map a level onto a slot in the register bank */ +static void arizona_micd_set_level(struct arizona *arizona, int index, + unsigned int level) +{ + int reg; + unsigned int mask; + + reg = ARIZONA_MIC_DETECT_LEVEL_4 - (index / 2); + + if (!(index % 2)) { + mask = 0x3f00; + level <<= 8; + } else { + mask = 0x3f; + } + + /* Program the level itself */ + regmap_update_bits(arizona->regmap, reg, mask, level); +} + +static int arizona_extcon_get_micd_configs(struct device *dev, + struct arizona *arizona) +{ + const char * const prop = "wlf,micd-configs"; + const int entries_per_config = 3; + struct arizona_micd_config *micd_configs; + int nconfs, ret; + int i, j; + u32 *vals; + + nconfs = device_property_count_u32(arizona->dev, prop); + if (nconfs <= 0) + return 0; + + vals = kcalloc(nconfs, sizeof(u32), GFP_KERNEL); + if (!vals) + return -ENOMEM; + + ret = device_property_read_u32_array(arizona->dev, prop, vals, nconfs); + if (ret < 0) + goto out; + + nconfs /= entries_per_config; + micd_configs = devm_kcalloc(dev, nconfs, sizeof(*micd_configs), + GFP_KERNEL); + if (!micd_configs) { + ret = -ENOMEM; + goto out; + } + + for (i = 0, j = 0; i < nconfs; ++i) { + micd_configs[i].src = vals[j++] ? ARIZONA_ACCDET_SRC : 0; + micd_configs[i].bias = vals[j++]; + micd_configs[i].gpio = vals[j++]; + } + + arizona->pdata.micd_configs = micd_configs; + arizona->pdata.num_micd_configs = nconfs; + +out: + kfree(vals); + return ret; +} + +static int arizona_extcon_device_get_pdata(struct device *dev, + struct arizona *arizona) +{ + struct arizona_pdata *pdata = &arizona->pdata; + unsigned int val = ARIZONA_ACCDET_MODE_HPL; + int ret; + + device_property_read_u32(arizona->dev, "wlf,hpdet-channel", &val); + switch (val) { + case ARIZONA_ACCDET_MODE_HPL: + case ARIZONA_ACCDET_MODE_HPR: + pdata->hpdet_channel = val; + break; + default: + dev_err(arizona->dev, + "Wrong wlf,hpdet-channel DT value %d\n", val); + pdata->hpdet_channel = ARIZONA_ACCDET_MODE_HPL; + } + + device_property_read_u32(arizona->dev, "wlf,micd-detect-debounce", + &pdata->micd_detect_debounce); + + device_property_read_u32(arizona->dev, "wlf,micd-bias-start-time", + &pdata->micd_bias_start_time); + + device_property_read_u32(arizona->dev, "wlf,micd-rate", + &pdata->micd_rate); + + device_property_read_u32(arizona->dev, "wlf,micd-dbtime", + &pdata->micd_dbtime); + + device_property_read_u32(arizona->dev, "wlf,micd-timeout-ms", + &pdata->micd_timeout); + + pdata->micd_force_micbias = device_property_read_bool(arizona->dev, + "wlf,micd-force-micbias"); + + pdata->micd_software_compare = device_property_read_bool(arizona->dev, + "wlf,micd-software-compare"); + + pdata->jd_invert = device_property_read_bool(arizona->dev, + "wlf,jd-invert"); + + device_property_read_u32(arizona->dev, "wlf,gpsw", &pdata->gpsw); + + pdata->jd_gpio5 = device_property_read_bool(arizona->dev, + "wlf,use-jd2"); + pdata->jd_gpio5_nopull = device_property_read_bool(arizona->dev, + "wlf,use-jd2-nopull"); + + ret = arizona_extcon_get_micd_configs(dev, arizona); + if (ret < 0) + dev_err(arizona->dev, "Failed to read micd configs: %d\n", ret); + + return 0; +} + +static int arizona_extcon_probe(struct platform_device *pdev) +{ + struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); + struct arizona_pdata *pdata = &arizona->pdata; + struct arizona_extcon_info *info; + unsigned int val; + unsigned int clamp_mode; + int jack_irq_fall, jack_irq_rise; + int ret, mode, i, j; + + if (!arizona->dapm || !arizona->dapm->card) + return -EPROBE_DEFER; + + info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + if (!dev_get_platdata(arizona->dev)) + arizona_extcon_device_get_pdata(&pdev->dev, arizona); + + info->micvdd = devm_regulator_get(&pdev->dev, "MICVDD"); + if (IS_ERR(info->micvdd)) { + ret = PTR_ERR(info->micvdd); + dev_err(arizona->dev, "Failed to get MICVDD: %d\n", ret); + return ret; + } + + mutex_init(&info->lock); + info->arizona = arizona; + info->dev = &pdev->dev; + info->last_jackdet = ~(ARIZONA_MICD_CLAMP_STS | ARIZONA_JD1_STS); + INIT_DELAYED_WORK(&info->hpdet_work, arizona_hpdet_work); + INIT_DELAYED_WORK(&info->micd_detect_work, arizona_micd_detect); + INIT_DELAYED_WORK(&info->micd_timeout_work, arizona_micd_timeout_work); + platform_set_drvdata(pdev, info); + + switch (arizona->type) { + case WM5102: + switch (arizona->rev) { + case 0: + info->micd_reva = true; + break; + default: + info->micd_clamp = true; + info->hpdet_ip_version = 1; + break; + } + break; + case WM5110: + case WM8280: + switch (arizona->rev) { + case 0 ... 2: + break; + default: + info->micd_clamp = true; + info->hpdet_ip_version = 2; + break; + } + break; + case WM8998: + case WM1814: + info->micd_clamp = true; + info->hpdet_ip_version = 2; + break; + default: + break; + } + + info->edev = devm_extcon_dev_allocate(&pdev->dev, arizona_cable); + if (IS_ERR(info->edev)) { + dev_err(&pdev->dev, "failed to allocate extcon device\n"); + return -ENOMEM; + } + + ret = devm_extcon_dev_register(&pdev->dev, info->edev); + if (ret < 0) { + dev_err(arizona->dev, "extcon_dev_register() failed: %d\n", + ret); + return ret; + } + + info->input = devm_input_allocate_device(&pdev->dev); + if (!info->input) { + dev_err(arizona->dev, "Can't allocate input dev\n"); + ret = -ENOMEM; + return ret; + } + + info->input->name = "Headset"; + info->input->phys = "arizona/extcon"; + + if (!pdata->micd_timeout) + pdata->micd_timeout = DEFAULT_MICD_TIMEOUT; + + if (pdata->num_micd_configs) { + info->micd_modes = pdata->micd_configs; + info->micd_num_modes = pdata->num_micd_configs; + } else { + info->micd_modes = micd_default_modes; + info->micd_num_modes = ARRAY_SIZE(micd_default_modes); + } + + if (arizona->pdata.gpsw > 0) + regmap_update_bits(arizona->regmap, ARIZONA_GP_SWITCH_1, + ARIZONA_SW1_MODE_MASK, arizona->pdata.gpsw); + + if (pdata->micd_pol_gpio > 0) { + if (info->micd_modes[0].gpio) + mode = GPIOF_OUT_INIT_HIGH; + else + mode = GPIOF_OUT_INIT_LOW; + + ret = devm_gpio_request_one(&pdev->dev, pdata->micd_pol_gpio, + mode, "MICD polarity"); + if (ret != 0) { + dev_err(arizona->dev, "Failed to request GPIO%d: %d\n", + pdata->micd_pol_gpio, ret); + return ret; + } + + info->micd_pol_gpio = gpio_to_desc(pdata->micd_pol_gpio); + } else { + if (info->micd_modes[0].gpio) + mode = GPIOD_OUT_HIGH; + else + mode = GPIOD_OUT_LOW; + + /* We can't use devm here because we need to do the get + * against the MFD device, as that is where the of_node + * will reside, but if we devm against that the GPIO + * will not be freed if the extcon driver is unloaded. + */ + info->micd_pol_gpio = gpiod_get_optional(arizona->dev, + "wlf,micd-pol", + GPIOD_OUT_LOW); + if (IS_ERR(info->micd_pol_gpio)) { + ret = PTR_ERR(info->micd_pol_gpio); + dev_err(arizona->dev, + "Failed to get microphone polarity GPIO: %d\n", + ret); + return ret; + } + } + + if (arizona->pdata.hpdet_id_gpio > 0) { + ret = devm_gpio_request_one(&pdev->dev, + arizona->pdata.hpdet_id_gpio, + GPIOF_OUT_INIT_LOW, + "HPDET"); + if (ret != 0) { + dev_err(arizona->dev, "Failed to request GPIO%d: %d\n", + arizona->pdata.hpdet_id_gpio, ret); + goto err_gpio; + } + } + + if (arizona->pdata.micd_bias_start_time) + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_BIAS_STARTTIME_MASK, + arizona->pdata.micd_bias_start_time + << ARIZONA_MICD_BIAS_STARTTIME_SHIFT); + + if (arizona->pdata.micd_rate) + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_RATE_MASK, + arizona->pdata.micd_rate + << ARIZONA_MICD_RATE_SHIFT); + + switch (arizona->pdata.micd_dbtime) { + case MICD_DBTIME_FOUR_READINGS: + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_DBTIME_MASK, + ARIZONA_MICD_DBTIME); + break; + case MICD_DBTIME_TWO_READINGS: + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_DBTIME_MASK, 0); + break; + default: + break; + } + + BUILD_BUG_ON(ARRAY_SIZE(arizona_micd_levels) < + ARIZONA_NUM_MICD_BUTTON_LEVELS); + + if (arizona->pdata.num_micd_ranges) { + info->micd_ranges = pdata->micd_ranges; + info->num_micd_ranges = pdata->num_micd_ranges; + } else { + info->micd_ranges = micd_default_ranges; + info->num_micd_ranges = ARRAY_SIZE(micd_default_ranges); + } + + if (arizona->pdata.num_micd_ranges > ARIZONA_MAX_MICD_RANGE) { + dev_err(arizona->dev, "Too many MICD ranges: %d\n", + arizona->pdata.num_micd_ranges); + } + + if (info->num_micd_ranges > 1) { + for (i = 1; i < info->num_micd_ranges; i++) { + if (info->micd_ranges[i - 1].max > + info->micd_ranges[i].max) { + dev_err(arizona->dev, + "MICD ranges must be sorted\n"); + ret = -EINVAL; + goto err_gpio; + } + } + } + + /* Disable all buttons by default */ + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_2, + ARIZONA_MICD_LVL_SEL_MASK, 0x81); + + /* Set up all the buttons the user specified */ + for (i = 0; i < info->num_micd_ranges; i++) { + for (j = 0; j < ARIZONA_NUM_MICD_BUTTON_LEVELS; j++) + if (arizona_micd_levels[j] >= info->micd_ranges[i].max) + break; + + if (j == ARIZONA_NUM_MICD_BUTTON_LEVELS) { + dev_err(arizona->dev, "Unsupported MICD level %d\n", + info->micd_ranges[i].max); + ret = -EINVAL; + goto err_gpio; + } + + dev_dbg(arizona->dev, "%d ohms for MICD threshold %d\n", + arizona_micd_levels[j], i); + + arizona_micd_set_level(arizona, i, j); + input_set_capability(info->input, EV_KEY, + info->micd_ranges[i].key); + + /* Enable reporting of that range */ + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_2, + 1 << i, 1 << i); + } + + /* Set all the remaining keys to a maximum */ + for (; i < ARIZONA_MAX_MICD_RANGE; i++) + arizona_micd_set_level(arizona, i, 0x3f); + + /* + * If we have a clamp use it, activating in conjunction with + * GPIO5 if that is connected for jack detect operation. + */ + if (info->micd_clamp) { + if (arizona->pdata.jd_gpio5) { + /* Put the GPIO into input mode with optional pull */ + val = 0xc101; + if (arizona->pdata.jd_gpio5_nopull) + val &= ~ARIZONA_GPN_PU; + + regmap_write(arizona->regmap, ARIZONA_GPIO5_CTRL, + val); + + if (arizona->pdata.jd_invert) + clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDH_GP5H; + else + clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDL_GP5H; + } else { + if (arizona->pdata.jd_invert) + clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDH; + else + clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDL; + } + + regmap_update_bits(arizona->regmap, + ARIZONA_MICD_CLAMP_CONTROL, + ARIZONA_MICD_CLAMP_MODE_MASK, clamp_mode); + + regmap_update_bits(arizona->regmap, + ARIZONA_JACK_DETECT_DEBOUNCE, + ARIZONA_MICD_CLAMP_DB, + ARIZONA_MICD_CLAMP_DB); + } + + arizona_extcon_set_mode(info, 0); + + pm_runtime_enable(&pdev->dev); + pm_runtime_idle(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + + if (info->micd_clamp) { + jack_irq_rise = ARIZONA_IRQ_MICD_CLAMP_RISE; + jack_irq_fall = ARIZONA_IRQ_MICD_CLAMP_FALL; + } else { + jack_irq_rise = ARIZONA_IRQ_JD_RISE; + jack_irq_fall = ARIZONA_IRQ_JD_FALL; + } + + ret = arizona_request_irq(arizona, jack_irq_rise, + "JACKDET rise", arizona_jackdet, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get JACKDET rise IRQ: %d\n", + ret); + goto err_pm; + } + + ret = arizona_set_irq_wake(arizona, jack_irq_rise, 1); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to set JD rise IRQ wake: %d\n", + ret); + goto err_rise; + } + + ret = arizona_request_irq(arizona, jack_irq_fall, + "JACKDET fall", arizona_jackdet, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get JD fall IRQ: %d\n", ret); + goto err_rise_wake; + } + + ret = arizona_set_irq_wake(arizona, jack_irq_fall, 1); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to set JD fall IRQ wake: %d\n", + ret); + goto err_fall; + } + + ret = arizona_request_irq(arizona, ARIZONA_IRQ_MICDET, + "MICDET", arizona_micdet, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get MICDET IRQ: %d\n", ret); + goto err_fall_wake; + } + + ret = arizona_request_irq(arizona, ARIZONA_IRQ_HPDET, + "HPDET", arizona_hpdet_irq, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get HPDET IRQ: %d\n", ret); + goto err_micdet; + } + + arizona_clk32k_enable(arizona); + regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_DEBOUNCE, + ARIZONA_JD1_DB, ARIZONA_JD1_DB); + regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE, + ARIZONA_JD1_ENA, ARIZONA_JD1_ENA); + + ret = regulator_allow_bypass(info->micvdd, true); + if (ret != 0) + dev_warn(arizona->dev, "Failed to set MICVDD to bypass: %d\n", + ret); + + ret = input_register_device(info->input); + if (ret) { + dev_err(&pdev->dev, "Can't register input device: %d\n", ret); + goto err_hpdet; + } + + pm_runtime_put(&pdev->dev); + + return 0; + +err_hpdet: + arizona_free_irq(arizona, ARIZONA_IRQ_HPDET, info); +err_micdet: + arizona_free_irq(arizona, ARIZONA_IRQ_MICDET, info); +err_fall_wake: + arizona_set_irq_wake(arizona, jack_irq_fall, 0); +err_fall: + arizona_free_irq(arizona, jack_irq_fall, info); +err_rise_wake: + arizona_set_irq_wake(arizona, jack_irq_rise, 0); +err_rise: + arizona_free_irq(arizona, jack_irq_rise, info); +err_pm: + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); +err_gpio: + gpiod_put(info->micd_pol_gpio); + return ret; +} + +static int arizona_extcon_remove(struct platform_device *pdev) +{ + struct arizona_extcon_info *info = platform_get_drvdata(pdev); + struct arizona *arizona = info->arizona; + int jack_irq_rise, jack_irq_fall; + bool change; + int ret; + + ret = regmap_update_bits_check(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, 0, + &change); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to disable micd on remove: %d\n", + ret); + } else if (change) { + regulator_disable(info->micvdd); + pm_runtime_put(info->dev); + } + + gpiod_put(info->micd_pol_gpio); + + pm_runtime_disable(&pdev->dev); + + regmap_update_bits(arizona->regmap, + ARIZONA_MICD_CLAMP_CONTROL, + ARIZONA_MICD_CLAMP_MODE_MASK, 0); + + if (info->micd_clamp) { + jack_irq_rise = ARIZONA_IRQ_MICD_CLAMP_RISE; + jack_irq_fall = ARIZONA_IRQ_MICD_CLAMP_FALL; + } else { + jack_irq_rise = ARIZONA_IRQ_JD_RISE; + jack_irq_fall = ARIZONA_IRQ_JD_FALL; + } + + arizona_set_irq_wake(arizona, jack_irq_rise, 0); + arizona_set_irq_wake(arizona, jack_irq_fall, 0); + arizona_free_irq(arizona, ARIZONA_IRQ_HPDET, info); + arizona_free_irq(arizona, ARIZONA_IRQ_MICDET, info); + arizona_free_irq(arizona, jack_irq_rise, info); + arizona_free_irq(arizona, jack_irq_fall, info); + cancel_delayed_work_sync(&info->hpdet_work); + regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE, + ARIZONA_JD1_ENA, 0); + arizona_clk32k_disable(arizona); + + return 0; +} + +static struct platform_driver arizona_extcon_driver = { + .driver = { + .name = "arizona-extcon", + }, + .probe = arizona_extcon_probe, + .remove = arizona_extcon_remove, +}; + +module_platform_driver(arizona_extcon_driver); + +MODULE_DESCRIPTION("Arizona Extcon driver"); +MODULE_AUTHOR("Mark Brown "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:extcon-arizona"); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6d1d8f4d0a66e..9d1ea737eebea 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -58,6 +58,7 @@ #include #include #include +#include #include #include #include "kcl/kcl_amdgpu_ttm.h" diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 new file mode 100644 index 0000000000000..4a1160753c960 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 @@ -0,0 +1,11 @@ +dnl # +dnl # commit v5.10-rc3-1140-gc67e62790f5c +dnl # drm/prime: split array import functions v4 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_prime_sg_to_dma_addr_array], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY, 1, [drm_prime_sg_to_dma_addr_array() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 new file mode 100644 index 0000000000000..b2614eabab932 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit f3ba3c710ac5a30cd058615a9eb62d2ad95bb782 +dnl # mm/highmem: Provide kmap_local* +dnl # +AC_DEFUN([AC_AMDGPU_KMAP_LOCAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + pgprot_t prot; + kmap_local_page_prot(NULL, prot); + ], [], [], [ + AC_DEFINE(HAVE_KMAP_LOCAL, 1, [kmap_local_* is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ad68dc0f0f448..f7d256819c259 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -134,12 +134,13 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED AC_AMDGPU_DRM_DP_SUBCONNECTOR + AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON AC_AMDGPU_DRM_APERTURE AC_AMDGPU_PCI_DRIVER_DEV_GROUPS - + AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" diff --git a/include/kcl/kcl_drm_prime.h b/include/kcl/kcl_drm_prime.h new file mode 100644 index 0000000000000..7f02b6c95d10c --- /dev/null +++ b/include/kcl/kcl_drm_prime.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __KCL_DRM_PRIME_H__ +#define __KCL_DRM_PRIME_H__ + +#include +#include +#include + +#ifndef HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY +static inline +int drm_prime_sg_to_dma_addr_array(struct sg_table *sgt, dma_addr_t *addrs, + int max_entries) +{ + return drm_prime_sg_to_page_addr_arrays(sgt, NULL, addrs, max_entries); + +} +#endif +#endif From c3a490567ae9d741f82657ca5d32f829682ee10c Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 3 Feb 2021 18:07:54 +0800 Subject: [PATCH 0412/2653] drm/amdkcl: test drm_prime_pages_to_sg() Test whether drm_prime_pages_to_sg() takes 3 arguments Signed-off-by: Slava Grigorev Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 | 21 ++++++++ .../drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 | 14 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 + include/kcl/backport/kcl_drm_prime.h | 49 +++++++++++++++++++ 5 files changed, 87 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 create mode 100644 include/kcl/backport/kcl_drm_prime.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 9d1ea737eebea..8bf382ab0c388 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -48,6 +48,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 b/drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 new file mode 100644 index 0000000000000..b33ceb61643ce --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit a4574f63edc6f76fb46dcd65d3eb4d5a8e23ba38 +dnl # mm/memremap_pages: convert to 'struct range' +dnl # +AC_DEFUN([AC_AMDGPU_DEV_PAGEMAP_RANGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dev_pagemap *pm = NULL; + pm->range.start = 0; + ], [ + AC_DEFINE(HAVE_DEV_PAGEMAP_RANGE, 1, + [there is 'range' field within dev_pagemap structure]) + ]) + ]) +]) +AC_DEFUN([AC_AMDGPU_DEV_PAGEMAP], [ + AC_AMDGPU_DEV_PAGEMAP_RANGE +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 new file mode 100644 index 0000000000000..5854aa864fd2e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 @@ -0,0 +1,14 @@ +dnl # +dnl # commit 707d561f77b5e2a6f90c9786bee44ee7a8dedc7e +dnl # drm: allow limiting the scatter list size. +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRIME_PAGES_TO_SG], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_prime_pages_to_sg(NULL, NULL, 0); + ], [drm_prime_pages_to_sg], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS, 1, + [drm_prime_pages_to_sg() wants 3 arguments]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f7d256819c259..4bacd14faff32 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -66,6 +66,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LIST_FOR_EACH_ENTRY AC_AMDGPU_TIMER_SETUP AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED + AC_AMDGPU_DEV_PAGEMAP AC_AMDGPU_DOWN_READ_KILLABLE AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED @@ -135,6 +136,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY + AC_AMDGPU_DRM_PRIME_PAGES_TO_SG AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/include/kcl/backport/kcl_drm_prime.h b/include/kcl/backport/kcl_drm_prime.h new file mode 100644 index 0000000000000..1c3895f60823d --- /dev/null +++ b/include/kcl/backport/kcl_drm_prime.h @@ -0,0 +1,49 @@ +/* + * Copyright © 2012 Red Hat + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Dave Airlie + * Rob Clark + * + */ + +// Copied from include/drm/drm_prime.h +#ifndef _KCL_BACKPORT_KCL__DRM_PRIME_H__H_ +#define _KCL_BACKPORT_KCL__DRM_PRIME_H__H_ + +#include + +#ifndef HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS +static inline +struct sg_table *_kcl_drm_prime_pages_to_sg(struct drm_device *dev, + struct page **pages, unsigned int nr_pages) +{ + pr_warn_once("legacy kernel with drm_prime_pages_to_sg() ignore segment size limits, which is buggy\n"); + return drm_prime_pages_to_sg(pages, nr_pages); +} +#define drm_prime_pages_to_sg _kcl_drm_prime_pages_to_sg +#endif + +#endif From 4a609b460679ed4c8b8523e4e7bd5bc960c79798 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 3 Feb 2021 16:33:18 +0800 Subject: [PATCH 0413/2653] drm/amdkcl: test amd_iommu_invalidate_ctx protocol Test whether type of pasid is u32 Reviewed-by: Guchun Chen Signed-off-by: Slava Grigorev Signed-off-by: Flora Cui --- .../drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 2 files changed, 18 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 new file mode 100644 index 0000000000000..ff2bf9c8949ad --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit c7b6bac9c72c5fcbd6e9e12545bd3022c7f21860 +dnl # drm, iommu: Change type of pasid to u32 +dnl # +AC_DEFUN([AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + void (*f)(struct pci_dev *pdev, u32 pasid); + amd_iommu_invalidate_ctx callback = f; + ], [ + AC_DEFINE(HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32, 1, + [amd_iommu_invalidate_ctx take arg type of pasid as u32]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4bacd14faff32..0de9ec0f4abc3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -66,6 +66,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LIST_FOR_EACH_ENTRY AC_AMDGPU_TIMER_SETUP AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED + AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX AC_AMDGPU_DEV_PAGEMAP AC_AMDGPU_DOWN_READ_KILLABLE AC_AMDGPU_DRM_CACHE From 9943df7da0314562ccd1e92cf3ad7dbf22ee6af9 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 8 Mar 2021 20:20:27 +0800 Subject: [PATCH 0414/2653] drm/amdkcl: check the callback prototype of atomic_best_encoder This is caused by "drm: Pass the full state to connectors atomic functions" v5.10-rc3-1075-geca22edb37d2 Signed-off-by: Shiwu Zhang --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 5 ++++ .../amd/dkms/m4/drm-connector-helper-funcs.m4 | 24 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index e05d34fa8411a..9517de7048121 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -501,10 +501,15 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) static struct drm_encoder * dm_mst_atomic_best_encoder(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_BEST_ENCODER_ARG_DRM_ATOMIC_STATE struct drm_atomic_state *state) { struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, connector); +#else + struct drm_connector_state *connector_state) +{ +#endif struct amdgpu_device *adev = drm_to_adev(connector->dev); struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 index 148d0cc472804..c31a4f9b86b56 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 @@ -16,3 +16,27 @@ AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK], [ ]) ]) ]) + +dnl # +dnl # v5.10-rc3-1075-geca22edb37d2 +dnl # drm: Pass the full state to connectors atomic functions +dnl # +AC_DEFUN([AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_ATOMIC_BEST_ENCODER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_connector_helper_funcs *p = NULL; + p->atomic_best_encoder(NULL, (struct drm_atomic_state*)NULL); + ], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_BEST_ENCODER_ARG_DRM_ATOMIC_STATE, 1, + [atomic_best_encoder take 2nd arg type of state as struct drm_atomic_state]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS], [ + AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_ATOMIC_BEST_ENCODER +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0de9ec0f4abc3..56b34a4a20743 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -118,7 +118,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC - AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS AC_AMDGPU_DRM_DP_MST_DETECT_PORT AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT From 9671a3410190bba21f2c97177b2002b67a371f0e Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 8 Mar 2021 20:54:21 +0800 Subject: [PATCH 0415/2653] drm/amdkcl: check the callback prototype of atomic_check in drm_crtc_helper_funcs Signed-off-by: Shiwu Zhang Signed-off-by: Ma Jun Change-Id: Ie6eb721917f480b955f6187de194d4426ae0392b --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 5 +++++ .../drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 187ddb4eac99e..1c01f0e6064a1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -625,10 +625,15 @@ static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, } static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, +#ifdef HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE struct drm_atomic_state *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); +#else + struct drm_crtc_state *crtc_state) +{ +#endif struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct dc *dc = adev->dm.dc; struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 new file mode 100644 index 0000000000000..7f43ce7a2f5e2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.2-rc2-529-g6f3b62781bbd +dnl # drm: Convert connector_helper_funcs->atomic_check to accept drm_atomic_state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_crtc_helper_funcs *p = NULL; + p->atomic_check(NULL, (struct drm_atomic_state*)NULL); + ], [ + AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE, 1, + [drm_crtc_helper_funcs->atomic_check() wants struct drm_atomic_state arg]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 56b34a4a20743..0878133258d18 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -138,6 +138,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY AC_AMDGPU_DRM_PRIME_PAGES_TO_SG + AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON From b5598e71df96637e264c9a939c9cbe10fd6541d2 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Wed, 24 Feb 2021 16:09:01 +0800 Subject: [PATCH 0416/2653] drm/amdkcl: wrapper the code for hmm dkms support and monitor_range related code under DISPLAY_INFO_MONITOR_RANGE This is caused by "remove unused variable from struct amdgpu_bo" and "Add Freesync HDMI support to DM" v5.9-rc5-2435-g3e6c7e19c2a5 and v5.9-rc5-2419-g1556b0c185e3 Signed-off-by: Shiwu Zhang Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 4 ++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index b1c1b695f3afc..ccb818fb115c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -112,6 +112,10 @@ struct amdgpu_bo { /* Constant after initialization */ struct amdgpu_bo *parent; +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + struct amdgpu_mn *mn; +#endif + #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED #ifdef CONFIG_MMU_NOTIFIER struct mmu_interval_notifier notifier; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d482b97c7f1e9..f871069524f4a 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12856,8 +12856,10 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) freesync_capable = true; +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; +#endif } } From a9ace24dd2c600b223dc1fc9551d6b4c44014690 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 22 Feb 2021 18:36:34 +0800 Subject: [PATCH 0417/2653] drm/amdkcl: do not use drm middle layer for dgma debugfs This is a squash of: drm/amdkcl: simplify kcl handling of drm_mm_print() Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui drm/amdkcl: restore prev handling of drm_debug_printer() Signed-off-by: Flora Cui This is caused by "do not use drm middle layer for debugfs" v5.9-rc5-2401-g80453ffefd61 Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui Signed-off-by: Ma Jun Change-Id: Ie651234201ff972b9a49dc77d592bed663a08987 --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 8 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 8 ----- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 4 --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 14 +++++--- drivers/gpu/drm/amd/backport/backport.h | 1 - .../amd/backport/include/kcl/kcl_amdgpu_ttm.h | 26 --------------- .../gpu/drm/amd/dkms/m4/drm-debug-printer.m4 | 16 --------- drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 | 15 --------- drivers/gpu/drm/amd/dkms/m4/drm_print.m4 | 21 ++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- include/drm/ttm/ttm_resource.h | 4 --- include/kcl/kcl_drm_print.h | 33 +++++++++++++------ 13 files changed, 61 insertions(+), 93 deletions(-) delete mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_print.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index c478823e29e2f..49cb35f8cc5bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -1823,12 +1823,14 @@ static int amdgpu_debugfs_vm_info_show(struct seq_file *m, void *unused) DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_test_ib); DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_vm_info); +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_vram_fops, amdgpu_debugfs_evict_vram, NULL, "%lld\n"); DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_gtt_fops, amdgpu_debugfs_evict_gtt, NULL, "%lld\n"); DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_benchmark_fops, NULL, amdgpu_debugfs_benchmark, "%lld\n"); +#endif static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring *ring, struct dma_fence **fences) @@ -2130,16 +2132,18 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) amdgpu_fw_attestation_debugfs_init(adev); amdgpu_psp_debugfs_init(adev); +#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file("amdgpu_evict_vram", 0400, root, adev, &amdgpu_evict_vram_fops); debugfs_create_file("amdgpu_evict_gtt", 0400, root, adev, &amdgpu_evict_gtt_fops); + debugfs_create_file("amdgpu_benchmark", 0200, root, adev, + &amdgpu_benchmark_fops); +#endif debugfs_create_file("amdgpu_test_ib", 0400, root, adev, &amdgpu_debugfs_test_ib_fops); debugfs_create_file("amdgpu_vm_info", 0444, root, adev, &amdgpu_debugfs_vm_info_fops); - debugfs_create_file("amdgpu_benchmark", 0200, root, adev, - &amdgpu_benchmark_fops); adev->debugfs_vbios_blob.data = adev->bios; adev->debugfs_vbios_blob.size = adev->bios_size; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index d72c5a9a85470..0760e70402ec1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -247,20 +247,12 @@ static bool amdgpu_gtt_mgr_compatible(struct ttm_resource_manager *man, * Dump the table content using printk. */ static void amdgpu_gtt_mgr_debug(struct ttm_resource_manager *man, -#if defined(HAVE_DRM_MM_PRINT) struct drm_printer *printer) -#else - const char *prefix) -#endif { struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man); spin_lock(&mgr->lock); -#if defined(HAVE_DRM_MM_PRINT) drm_mm_print(&mgr->mm, printer); -#else - drm_mm_debug_table(&mgr->mm, prefix); -#endif spin_unlock(&mgr->lock); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index a56592dbbe98e..3b3ba3694c168 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -3018,7 +3018,6 @@ DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_dgma_table); DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_dgma_import_table); - /* * amdgpu_ttm_vram_read - Linear read access to VRAM * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 775040320b442..77ce9cf280518 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -911,11 +911,7 @@ static bool amdgpu_vram_mgr_compatible(struct ttm_resource_manager *man, * Dump the table content using printk. */ static void amdgpu_vram_mgr_debug(struct ttm_resource_manager *man, -#if defined(HAVE_DRM_MM_PRINT) struct drm_printer *printer) -#else - const char *prefix) -#endif { struct amdgpu_vram_mgr *mgr = to_vram_mgr(man); struct drm_buddy *mm = &mgr->mm; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 3d690609edb8f..0c47443e0f189 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -38,15 +38,21 @@ void drm_printf(struct drm_printer *p, const char *f, ...) va_end(args); } EXPORT_SYMBOL(drm_printf); + +void __drm_printfn_seq_file(struct drm_printer *p, struct va_format *vaf) +{ + seq_printf(p->arg, "%pV", vaf); +} +EXPORT_SYMBOL(__drm_printfn_seq_file); #endif -#if !defined(HAVE_DRM_DEBUG_PRINTER) +#if !defined(HAVE_DRM_PRINTER_PREFIX) void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf) { -#if !defined(HAVE_DRM_DRM_PRINT_H) - pr_debug("%s %pV", p->prefix, vaf); +#ifndef HAVE_DRM_DRM_PRINT_H + printk(KERN_DEBUG "[" DRM_NAME ":]" "%s %pV", p->prefix, vaf); #else - pr_debug("%s %pV", "no prefix < 4.11", vaf); + printk(KERN_DEBUG "[" DRM_NAME ":]" "%s %pV", "no prefix", vaf); #endif } EXPORT_SYMBOL(__drm_printfn_debug); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 8bf382ab0c388..a26805941e1a0 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -62,7 +62,6 @@ #include #include #include -#include "kcl/kcl_amdgpu_ttm.h" #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h deleted file mode 100644 index 1c4be1340422f..0000000000000 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef AMDGPU_BACKPORT_KCL_AMDGPU_TTM_H -#define AMDGPU_BACKPORT_KCL_AMDGPU_TTM_H -#include -#include -#include -#include "amdgpu.h" -#include "amdgpu_ttm.h" - -#if !defined(HAVE_DRM_MM_PRINT) -extern struct drm_mm *kcl_ttm_range_res_manager_to_drm_mm(struct ttm_resource_manager *man); - -static inline struct drm_mm *kcl_ttm_get_drm_mm_by_mem_type(struct amdgpu_device *adev, unsigned char ttm_pl) -{ - if (ttm_pl == TTM_PL_TT) { - return &(adev->mman.gtt_mgr.mm); - } else if (ttm_pl == TTM_PL_VRAM) { - return &(adev->mman.vram_mgr.mm); - } else { - struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl); - return kcl_ttm_range_res_manager_to_drm_mm(man); - } -} -#endif - -#endif /* AMDGPU_BACKPORT_KCL_AMDGPU_TTM_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 deleted file mode 100644 index 3fdcea368bf1e..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit 3d387d923c18afbacef8f14ccaa2ace2a297df74 -dnl # drm/printer: add debug printer -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DEBUG_PRINTER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - drm_debug_printer(NULL); - ], [ - AC_DEFINE(HAVE_DRM_DEBUG_PRINTER, 1, - [drm_debug_printer() function is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 deleted file mode 100644 index 2d1d63b131ce7..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 +++ /dev/null @@ -1,15 +0,0 @@ -dnl # -dnl # commit b5c3714fe8789745521d8351d75049b9c6a0d26b -dnl # drm/mm: Convert to drm_printer -dnl # -AC_DEFUN([AC_AMDGPU_DRM_MM_PRINT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - drm_mm_print(NULL, NULL); - ], [ - AC_DEFINE(HAVE_DRM_MM_PRINT, 1, [drm_mm_print() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_print.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_print.m4 new file mode 100644 index 0000000000000..3c4a306d53cd3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_print.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # v4.9-rc2-477-gd8187177b0b1 drm: add helper for printing to log or seq_file +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRINTER], [ + AC_KERNEL_DO_BACKGROUND([ + AS_IF([test $HAVE_DRM_DRM_PRINT_H], [ + dnl # + dnl # v4.9-rc8-1738-gb5c3714fe878 drm/mm: Convert to drm_printer + dnl # v4.9-rc8-1737-g3d387d923c18 drm/printer: add debug printer + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_printer *p = NULL; + p->prefix = NULL; + ], [ + AC_DEFINE(HAVE_DRM_PRINTER_PREFIX, 1, [drm_printer->prefix is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0878133258d18..020f38d2bc807 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -85,7 +85,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT - AC_AMDGPU_DRM_MM_PRINT + AC_AMDGPU_DRM_PRINTER AC_AMDGPU_DRM_MM_INSERT_MODE AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL @@ -95,7 +95,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEV_DBG AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM - AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h index a7afc95448be7..b873be9597e2e 100644 --- a/include/drm/ttm/ttm_resource.h +++ b/include/drm/ttm/ttm_resource.h @@ -168,12 +168,8 @@ struct ttm_resource_manager_func { * type manager to aid debugging of out-of-memory conditions. * It may not be called from within atomic context. */ -#if defined(HAVE_DRM_MM_PRINT) void (*debug)(struct ttm_resource_manager *man, struct drm_printer *printer); -#else - void (*debug)(struct ttm_resource_manager *man, const char *prefix); -#endif }; /** diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 3ead0ab2b367f..10ba443b49303 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -29,7 +29,7 @@ #include #if !defined(HAVE_DRM_DRM_PRINT_H) -/* Copied from include/drm/drm_print.h */ +/* Copied from d8187177b0b1 include/drm/drm_print.h */ struct drm_printer { void (*printfn)(struct drm_printer *p, struct va_format *vaf); void *arg; @@ -37,28 +37,41 @@ struct drm_printer { }; void drm_printf(struct drm_printer *p, const char *f, ...); +void __drm_printfn_seq_file(struct drm_printer *p, struct va_format *vaf); +static inline struct drm_printer drm_seq_file_printer(struct seq_file *f) +{ + struct drm_printer p = { + .printfn = __drm_printfn_seq_file, + .arg = f, + }; + return p; +} #endif -/** - * drm_debug_printer - construct a &drm_printer that outputs to pr_debug() - * @prefix: debug output prefix - * - * RETURNS: - * The &drm_printer object - */ -#if !defined(HAVE_DRM_DEBUG_PRINTER) +/* Copied from 3d387d923c18 include/drm/drm_print.h */ +#if !defined(HAVE_DRM_PRINTER_PREFIX) extern void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf); static inline struct drm_printer drm_debug_printer(const char *prefix) { struct drm_printer p = { .printfn = __drm_printfn_debug, -#if !defined(HAVE_DRM_DRM_PRINT_H) +#ifndef HAVE_DRM_DRM_PRINT_H .prefix = prefix #endif }; return p; } + +static inline +void drm_mm_print(const struct drm_mm *mm, struct drm_printer *p) +{ +#ifndef HAVE_DRM_DRM_PRINT_H + drm_mm_debug_table(mm, p->prefix); +#else + drm_mm_debug_table(mm, "no prefix"); +#endif +} #endif #ifndef _DRM_PRINTK From af2728ad44963825fc30365f2c20ebac50d5f74f Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 23 Feb 2021 16:01:29 +0800 Subject: [PATCH 0418/2653] drm/amdkcl: fake the debugfs_create_file_size This is caused by "do not use drm middle layer for debugfs" v5.9-rc5-2401-g80453ffefd61 Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 1 + .../gpu/drm/amd/amdkcl/kcl_debugfs_inode.c | 29 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 | 13 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_debugfs_inode.h | 27 +++++++++++++++++ 6 files changed, 72 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_debugfs_inode.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 create mode 100644 include/kcl/kcl_debugfs_inode.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 0791290ae716b..3a98d624be313 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -15,6 +15,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o +amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_inode.c b/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_inode.c new file mode 100644 index 0000000000000..5d41d1e609712 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_inode.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * inode.c - part of debugfs, a tiny little debug file system + * + * Copyright (C) 2004,2019 Greg Kroah-Hartman + * Copyright (C) 2004 IBM Inc. + * Copyright (C) 2019 Linux Foundation + * + * debugfs is for people to use instead of /proc or /sys. + * See ./Documentation/core-api/kernel-api.rst for more details. + */ + +#include +#include + +/* Copied from fs/debugfs/inode.c */ +#ifndef HAVE_DEBUGFS_CREATE_FILE_SIZE +void debugfs_create_file_size(const char *name, umode_t mode, + struct dentry *parent, void *data, + const struct file_operations *fops, + loff_t file_size) +{ + struct dentry *de = debugfs_create_file(name, mode, parent, data, fops); + + if (de) + d_inode(de)->i_size = file_size; +} +EXPORT_SYMBOL_GPL(debugfs_create_file_size); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a26805941e1a0..2b8a6cea3b4b7 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -62,6 +62,7 @@ #include #include #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 b/drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 new file mode 100644 index 0000000000000..3f4be7129b920 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit: v3.19-rc5-12-ge59b4e9187bd +dnl # debugfs: Provide a file creation function +dnl # that also takes an initial size +AC_DEFUN([AC_AMDGPU_DEBUGFS_CREATE_FILE_SIZE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([debugfs_create_file_size], + [fs/debugfs/inode.c], [ + AC_DEFINE(HAVE_DEBUGFS_CREATE_FILE_SIZE, 1, + [debugfs_create_file_size() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 020f38d2bc807..5433b41409c5a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -138,6 +138,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY AC_AMDGPU_DRM_PRIME_PAGES_TO_SG AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DEBUGFS_CREATE_FILE_SIZE AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/include/kcl/kcl_debugfs_inode.h b/include/kcl/kcl_debugfs_inode.h new file mode 100644 index 0000000000000..a21af633d09d6 --- /dev/null +++ b/include/kcl/kcl_debugfs_inode.h @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * debugfs.h - a tiny little debug file system + * + * Copyright (C) 2004 Greg Kroah-Hartman + * Copyright (C) 2004 IBM Inc. + * + * debugfs is for people to use instead of /proc or /sys. + * See Documentation/filesystems/ for more details. + */ +#include +#include + +#ifndef HAVE_DEBUGFS_CREATE_FILE_SIZE +#ifdef CONFIG_DEBUG_FS +void debugfs_create_file_size(const char *name, umode_t mode, + struct dentry *parent, void *data, + const struct file_operations *fops, + loff_t file_size); +#else +static inline void debugfs_create_file_size(const char *name, umode_t mode, + struct dentry *parent, void *data, + const struct file_operations *fops, + loff_t file_size) +{ } +#endif +#endif From bfab5f0242884b42da4117ce8f1ed893df3e469f Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Thu, 21 Jan 2021 20:25:47 +0800 Subject: [PATCH 0419/2653] drm/amdkcl: check whether drm_display_info have monitor_range This is caused by "Report Freesync to vrr_range debugfs entry in DRM" v5.9-rc5-2241-ga5df71e584c0 squrash: 1aaf7981408b231b5125a59cdd198824af316025 drm/amdkcl: wrap code under macro HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE Signed-off-by: Bob Zhou Signed-off-by: Shiwu Zhang --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- .../gpu/drm/amd/dkms/m4/drm-display-info.m4 | 22 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 25 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f871069524f4a..1ffa0a6e0fd8e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12811,6 +12811,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || sink->sink_signal == SIGNAL_TYPE_EDP)) { +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE if (amdgpu_dm_connector->dc_link && amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) { amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq; @@ -12818,7 +12819,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) freesync_capable = true; } - +#endif parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); if (vsdb_info.replay_mode) { diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 new file mode 100644 index 0000000000000..61eef3b454776 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 @@ -0,0 +1,22 @@ +dnl # +dnl # commit v5.6-rc2-1062-ga1d11d1efe4d +dnl # drm/edid: Add function to parse EDID descriptors for monitor range +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_display_info *info = NULL; + info->monitor_range.min_vfreq=0; + info->monitor_range.max_vfreq=0; + ],[ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE, 1, + [struct drm_display_info has monitor_range member]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO], [ + AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5433b41409c5a..101fed4470836 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -144,6 +144,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VGA_REMOVE_VGACON AC_AMDGPU_DRM_APERTURE AC_AMDGPU_PCI_DRIVER_DEV_GROUPS + AC_AMDGPU_DRM_DISPLAY_INFO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 9589f5095f5043ae2bb17aefa56df2dec595b2f0 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 1 Mar 2021 15:43:59 +0800 Subject: [PATCH 0420/2653] drm/amdkcl: adapt for drm_mm_insert_node prototype change This is caused "drm/amdgpu: reserve backup pages for bad page retirment" v5.9-rc5-2461-g3a5cce0da738 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/backport/kcl_drm_mm_backport.h | 23 ++++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 include/kcl/backport/kcl_drm_mm_backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 2b8a6cea3b4b7..5de75456b50fb 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -63,6 +63,7 @@ #include #include #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/include/kcl/backport/kcl_drm_mm_backport.h b/include/kcl/backport/kcl_drm_mm_backport.h new file mode 100644 index 0000000000000..8c20d53ed7f4f --- /dev/null +++ b/include/kcl/backport/kcl_drm_mm_backport.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_DRM_MM_H +#define AMDKCL_DRM_MM_H + +/** + * interface change in mainline kernel 4.10 + * v4.10-rc5-1060-g4e64e5539d15 drm: Improve drm_mm search (and fix topdown allocation) + * with rbtrees + */ + +#include + +#ifndef HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS +static inline int _kcl_drm_mm_insert_node(struct drm_mm *mm, + struct drm_mm_node *node, + u64 size) +{ + return drm_mm_insert_node(mm, node, size, 0, DRM_MM_SEARCH_DEFAULT); +} +#define drm_mm_insert_node _kcl_drm_mm_insert_node +#endif /* HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS */ + +#endif /* AMDKCL_DRM_MM_H */ From 60e663b5d8e5d11bdc7ec05145aeb94ed5b529b2 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 2 Mar 2021 15:22:04 +0800 Subject: [PATCH 0421/2653] drm/amdkcl: Replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE This is caused by "drm/amdgpu: Replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE" v5.9-rc5-2487-gd7ce9ec795fb Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 49cb35f8cc5bc..a67bd513cb17d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -2045,11 +2045,13 @@ static int amdgpu_debugfs_sclk_set(void *data, u64 val) return ret; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL, amdgpu_debugfs_ib_preempt, "%llu\n"); DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL, amdgpu_debugfs_sclk_set, "%llu\n"); +#endif int amdgpu_debugfs_init(struct amdgpu_device *adev) { @@ -2060,6 +2062,7 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) if (!debugfs_initialized()) return 0; +#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_x32("amdgpu_smu_debug", 0600, root, &adev->pm.smu_debug_mask); @@ -2076,6 +2079,7 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) DRM_ERROR("unable to create amdgpu_set_sclk debugsfs file\n"); return PTR_ERR(ent); } +#endif /* Register debugfs entries for amdgpu_ttm */ amdgpu_ttm_debugfs_init(adev); From 575fb6c06dbecc7f3cd1872bbe35a6f7bf495a10 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 5 Jan 2021 14:45:43 +0800 Subject: [PATCH 0422/2653] drm/amdkcl: add pixel format definitions for backport This is caused by "Check plane scaling against format specific hw plane caps" v5.9-rc5-2058-g9302b36fd9a0 Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui Signed-off-by: Ma Jun Change-Id: I1170bb9d453ab4b4536b1a2cf2cc4a0144a67490 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 8 ++++++-- .../drm/amd/display/dc/resource/dcn10/dcn10_resource.c | 2 -- .../drm/amd/display/dc/resource/dcn21/dcn21_resource.c | 2 -- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 53ca2c3097580..e88301810443e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -803,10 +803,10 @@ static int amdgpu_dm_plane_get_plane_formats(const struct drm_plane *plane, if (plane_cap && plane_cap->pixel_format_support.nv12) formats[num_formats++] = DRM_FORMAT_NV12; -#ifdef DRM_FORMAT_P010 + if (plane_cap && plane_cap->pixel_format_support.p010) formats[num_formats++] = DRM_FORMAT_P010; -#endif + if (plane_cap && plane_cap->pixel_format_support.fp16) { formats[num_formats++] = DRM_FORMAT_XRGB16161616F; formats[num_formats++] = DRM_FORMAT_ARGB16161616F; @@ -1071,7 +1071,11 @@ static void amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_device *dev, /* Caps for all supported planes are the same on DCE and DCN 1 - 3 */ struct dc_plane_cap *plane_cap = &dc->caps.planes[0]; +#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT + switch (fb->pixel_format) { +#else switch (fb->format->format) { +#endif case DRM_FORMAT_P010: case DRM_FORMAT_NV12: case DRM_FORMAT_NV21: diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c index 59d8c3d28cfb4..652c05c354947 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c @@ -514,9 +514,7 @@ static const struct dc_plane_cap plane_cap = { .argb8888 = true, .nv12 = true, .fp16 = true, -#ifdef DRM_FORMAT_P010 .p010 = false -#endif }, .max_upscale_factor = { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index a9af721d8e4e1..918742a42ded6 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -589,9 +589,7 @@ static const struct dc_plane_cap plane_cap = { .argb8888 = true, .nv12 = true, .fp16 = true, -#ifdef DRM_FORMAT_P010 .p010 = true -#endif }, .max_upscale_factor = { From e280e741320c7b8bcd06224b0bb03e338fc8b779 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Fri, 22 Jan 2021 13:04:18 +0800 Subject: [PATCH 0423/2653] drm/amdkcl: fake the PCIe 5.0 speed enum by using macro This is caused by "Add pcie gen5 support in pcie capability" v5.9-rc5-2265-g14769c60e22e Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- include/kcl/kcl_pci.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 7289493f142b2..b93c8b9e91ff0 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -64,9 +64,9 @@ #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ #endif -#ifndef PCIE_SPEED_16_0GT #define PCIE_SPEED_16_0GT 0x17 -#endif +#define PCIE_SPEED_32_0GT 0x18 + #ifndef PCI_EXP_LNKCAP2_SLS_16_0GB #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ #endif From e2843e6bc3f3505765b9d765e2b1bc7715c52970 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 21 Dec 2020 13:50:14 +0800 Subject: [PATCH 0424/2653] drm/amdkcl: test drm_dp_mst_topology_cbs->destroy_connector drm_dp_mst_topology_cbs->destroy_connector() is a must before commit d29333cf5cd7 ("drm/dp_mst: Remove PDT teardown in drm_dp_destroy_port() and refactor"). otherwise kernel NULL pointer dereference jump out. Reviewed-by: Guchun Chen Reviewed-by: Aurabindo Pillai Signed-off-by: Flora Cui --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 37 +++++++++++++++++++ .../amd/dkms/m4/drm-dp-mst-topology-cbs.m4 | 17 +++++++++ 2 files changed, 54 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 9517de7048121..9c1b6331c4912 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -165,11 +165,13 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector) struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR if (aconnector->dc_sink) { dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink); dc_sink_release(aconnector->dc_sink); } +#endif drm_edid_free(aconnector->drm_edid); @@ -836,6 +838,38 @@ static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT); } +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR +static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, + struct drm_connector *connector) +{ + struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr); + struct drm_device *dev = master->base.dev; + struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); + + DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n", + aconnector, connector->base.id, aconnector->mst_port); + + if (aconnector->dc_sink) { + amdgpu_dm_update_freesync_caps(connector, NULL); + dc_link_remove_remote_sink(aconnector->dc_link, + aconnector->dc_sink); + dc_sink_release(aconnector->dc_sink); + aconnector->dc_sink = NULL; + mutex_lock(&mgr->lock); + if (!mgr->mst_state) + aconnector->dc_link->cur_link_settings.lane_count = 0; + mutex_unlock(&mgr->lock); + } + drm_connector_unregister(connector); +#ifdef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS + if (adev->mode_info.rfbdev) + drm_fb_helper_remove_one_connector(&adev->mode_info.rfbdev->helper, connector); +#endif + drm_connector_put(connector); +} +#endif + #if defined(HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG) static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) { @@ -870,6 +904,9 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector) static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { .add_connector = dm_dp_add_mst_connector, +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR + .destroy_connector = dm_dp_destroy_mst_connector, +#endif #if defined(HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG) .hotplug = dm_dp_mst_hotplug, #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 index 5847b52020f9f..f08316600fcbd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -34,9 +34,26 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR], [ ]) ]) +dnl # +dnl # commit v5.6-rc5-1703-g72dc0f515913 +dnl # drm/dp_mst: Remove drm_dp_mst_topology_cbs.destroy_connector +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; + dp_mst_cbs->destroy_connector(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR, 1, + [struct drm_dp_mst_topology_cbs->destroy_connector is available]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS], [ AC_KERNEL_DO_BACKGROUND([ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR ]) ]) From a38c768ead1e2fe455f377d8749eaaa61444933c Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 20 Jan 2021 14:29:34 +0800 Subject: [PATCH 0425/2653] drm/amdkcl: Work around mmu_notifier_put issue on RHEL 8.3 The DRM backport from kernel 5.6 includes some MMU notifier changes that cause problems with the mmu_notifier_put function. The free_notifier never gets called. This leads to a leak of kfd_process structures and their doorbells. Work around this by falling back to the old method of releasing the MMU notifier and destryoing the process structure. Signed-off-by: Felix Kuehling Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- include/kcl/kcl_mn.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_mn.h b/include/kcl/kcl_mn.h index 02e80c3b4e386..f828b5dedec49 100644 --- a/include/kcl/kcl_mn.h +++ b/include/kcl/kcl_mn.h @@ -4,6 +4,12 @@ #include +/* mmu_notifier_put in the RH DRM backport from 5.6 is broken */ +#if DRM_VER == 5 && DRM_PATCH == 6 && \ + LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0) +#undef HAVE_MMU_NOTIFIER_PUT +#endif + /* Copied from v3.16-6588-gb972216e27d1 include/linux/mmu_notifier.h */ #if !defined(HAVE_MMU_NOTIFIER_CALL_SRCU) && \ !defined(HAVE_MMU_NOTIFIER_PUT) From 4aed471973c7b1937150d056917c6dc7d4b9da4a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 3 Feb 2021 16:22:49 +0800 Subject: [PATCH 0426/2653] drm/amdkcl: fake drm_gem_ttm_{vmap,vunmap} Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 14 +++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 16 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 + drivers/gpu/drm/amd/backport/Makefile | 2 +- drivers/gpu/drm/amd/backport/backport.h | 1 + .../include/kcl/kcl_drm_gem_ttm_helper.h | 37 +++++++++++++++++ .../drm/amd/backport/kcl_drm_gem_ttm_helper.c | 40 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 7 ++++ .../drm/amd/dkms/m4/drm_gem_object_funcs.m4 | 28 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/header/drm/drm_gem_ttm_helper.h | 9 +++++ 12 files changed, 158 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h create mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 create mode 100644 include/kcl/header/drm/drm_gem_ttm_helper.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index aeb71b0e2157d..b5ab8c9afad71 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3145,6 +3145,11 @@ static const struct drm_driver amdgpu_kms_driver = { #endif .irq_handler = amdgpu_irq_handler, .ioctls = amdgpu_ioctls_kms, +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + .gem_free_object_unlocked = amdgpu_gem_object_free, + .gem_open_object = amdgpu_gem_object_open, + .gem_close_object = amdgpu_gem_object_close, +#endif .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), .dumb_create = amdgpu_mode_dumb_create, .dumb_map_offset = amdgpu_mode_dumb_mmap, @@ -3157,6 +3162,10 @@ static const struct drm_driver amdgpu_kms_driver = { .show_fdinfo = amdgpu_show_fdinfo, #endif +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + .gem_prime_export = amdgpu_gem_prime_export, +#endif + #if defined(AMDKCL_AMDGPU_DMABUF_OPS) .gem_prime_import = amdgpu_gem_prime_import, #else @@ -3173,6 +3182,11 @@ static const struct drm_driver amdgpu_kms_driver = { .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, #endif +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + .gem_prime_vmap = drm_gem_ttm_vmap, + .gem_prime_vunmap = drm_gem_ttm_vunmap, +#endif + .gem_prime_mmap = drm_gem_prime_mmap, .name = DRIVER_NAME, .desc = DRIVER_DESC, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 6c61146c7d56b..8def53a4e47d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -153,6 +153,9 @@ amdgpu_gem_update_bo_mapping(struct drm_file *filp, drm_syncobj_add_point(syncobj, chain, last_update, point); } +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +void amdgpu_gem_object_free(struct drm_gem_object *gobj) +#else static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) { struct ttm_buffer_object *bo = vmf->vma->vm_private_data; @@ -194,6 +197,7 @@ static const struct vm_operations_struct amdgpu_gem_vm_ops = { }; static void amdgpu_gem_object_free(struct drm_gem_object *gobj) +#endif { struct amdgpu_bo *aobj = gem_to_amdgpu_bo(gobj); struct amdgpu_device *adev = amdgpu_ttm_adev(aobj->tbo.bdev); @@ -302,8 +306,13 @@ void amdgpu_gem_force_release(struct amdgpu_device *adev) * Call from drm_gem_handle_create which appear in both new and open ioctl * case. */ +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int amdgpu_gem_object_open(struct drm_gem_object *obj, + struct drm_file *file_priv) +#else static int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) +#endif { struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); @@ -376,8 +385,13 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj, return r; } +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +void amdgpu_gem_object_close(struct drm_gem_object *obj, + struct drm_file *file_priv) +#else static void amdgpu_gem_object_close(struct drm_gem_object *obj, struct drm_file *file_priv) +#endif { struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); @@ -451,6 +465,7 @@ static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_str return drm_gem_ttm_mmap(obj, vma); } +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { .free = amdgpu_gem_object_free, .open = amdgpu_gem_object_open, @@ -461,6 +476,7 @@ const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { .mmap = amdgpu_gem_object_mmap, .vm_ops = &amdgpu_gem_vm_ops, }; +#endif /* * GEM ioctls. diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h index b51e8f95ee86d..1ddfc7f4f5e3b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h @@ -33,7 +33,9 @@ #define AMDGPU_GEM_DOMAIN_MAX 0x3 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, tbo.base) +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK extern const struct drm_gem_object_funcs amdgpu_gem_object_funcs; +#endif unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 75d25b90f1513..329bd8e2ceafe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -685,7 +685,9 @@ int amdgpu_bo_create(struct amdgpu_device *adev, if (bo == NULL) return -ENOMEM; drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK bo->tbo.base.funcs = &amdgpu_gem_object_funcs; +#endif bo->vm_bo = NULL; bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : bp->domain; diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index 8880468d474a6..115fc89f8204f 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: MIT -BACKPORT_OBJS := kcl_drm_drv.o +BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 5de75456b50fb..c9f88d77262d6 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -67,6 +67,7 @@ #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" +#include "kcl/kcl_drm_gem_ttm_helper.h" #include "kcl/kcl_drm_aperture.h" #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h new file mode 100644 index 0000000000000..10d002f55b191 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copied from include/drm/drm_gem_ttm_helper.h */ + +#ifndef _KCL_KCL_DRM_GEM_TTM_HELPER_H_H +#define _KCL_KCL_DRM_GEM_TTM_HELPER_H_H + +#include + +#ifndef HAVE_DRM_GEM_TTM_VMAP +void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, + void *vaddr); + +void *_kcl_drm_gem_ttm_vmap(struct drm_gem_object *obj); + +static inline +void drm_gem_ttm_vunmap(struct drm_gem_object *gem, + void *vaddr) +{ + _kcl_drm_gem_ttm_vunmap(gem, vaddr); +} + +static inline +void *drm_gem_ttm_vmap(struct drm_gem_object *obj) +{ + return _kcl_drm_gem_ttm_vmap(obj); +} +#endif + +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +void amdgpu_gem_object_free(struct drm_gem_object *obj); +int amdgpu_gem_object_open(struct drm_gem_object *obj, + struct drm_file *file_priv); +void amdgpu_gem_object_close(struct drm_gem_object *obj, + struct drm_file *file_priv); +#endif + +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c new file mode 100644 index 0000000000000..ef1c82463f8e0 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include + +#include +#include +#include +#include +#include +#include + +#ifndef drm_gem_ttm_of_gem +#define drm_gem_ttm_of_gem(gem_obj) \ + container_of(gem_obj, struct ttm_buffer_object, base) +#endif + +#ifndef HAVE_DRM_GEM_TTM_VMAP +void *_kcl_drm_gem_ttm_vmap(struct drm_gem_object *obj) +{ + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(obj); + struct dma_buf_map map; + + ttm_bo_vmap(bo, &map); + return map.vaddr; +} +EXPORT_SYMBOL(_kcl_drm_gem_ttm_vmap); + +void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, + void *vaddr) +{ + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); + struct dma_buf_map map; + + map.vaddr = vaddr; + map.is_iomem = bo->mem.bus.is_iomem; + + ttm_bo_vunmap(bo, &map); +} +EXPORT_SYMBOL(_kcl_drm_gem_ttm_vunmap); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 16ebd93fc3ea8..1f21aec4ff2ee 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -39,6 +39,13 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_managed.h]) + dnl # + dnl # v5.3-rc1-623-gff540b76f14a + dnl # drm/ttm: add drm gem ttm helpers, + dnl # starting with drm_gem_ttm_print_info() + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_gem_ttm_helper.h]) + dnl # dnl # v5.12-rc3-330-g2916059147ea dnl # drm/aperture: Add infrastructure for aperture ownership diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 new file mode 100644 index 0000000000000..353a678db52d7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 @@ -0,0 +1,28 @@ +dnl # +dnl # commit v4.9-rc8-1739-g6d1b81d8e25d +dnl # drm: add crtc helper drm_crtc_from_index() +dnl # commit v5.9-rc5-1077-gd693def4fd1c +dnl # drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_TTM_VMAP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_gem_ttm_vmap], [drivers/gpu/drm/drm_gem_ttm_helper.c], [ + AC_DEFINE(HAVE_DRM_GEM_TTM_VMAP, 1, [drm_gem_ttm_vmap() is available]) + ],[ + AC_KERNEL_TRY_COMPILE([ + struct vm_area_struct; + #ifdef HAVE_DRM_DRMP_H + #include + #else + #include + #endif + ],[ + struct drm_driver *drv = NULL; + drv->gem_open_object = NULL; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK, 1, + [drm_gem_open_object is defined in struct drm_drv]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 101fed4470836..53245abcb13fa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -139,6 +139,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_PRIME_PAGES_TO_SG AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK AC_AMDGPU_DEBUGFS_CREATE_FILE_SIZE + AC_AMDGPU_DRM_GEM_TTM_VMAP AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/include/kcl/header/drm/drm_gem_ttm_helper.h b/include/kcl/header/drm/drm_gem_ttm_helper.h new file mode 100644 index 0000000000000..1f4610148dd07 --- /dev/null +++ b/include/kcl/header/drm/drm_gem_ttm_helper.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_VBLANK_H_H_ +#define _KCL_HEADER_DRM_VBLANK_H_H_ + +#ifdef HAVE_DRM_DRM_DRM_GEM_TTM_HELPER_H +#include_next +#endif + +#endif From 7ca9eafa110342593014c9837c7db215d5a52e0c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 4 Feb 2021 15:18:44 +0800 Subject: [PATCH 0427/2653] drm/amdkcl: refactor test for ktime_get_real_seconds Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- .../drm/amd/dkms/m4/ktime-get-real-seconds.m4 | 42 +++++++------------ 1 file changed, 14 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 index 53fe6c0af4523..6ba2dff0aca08 100644 --- a/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 @@ -1,34 +1,20 @@ -dnl # -dnl # commit dbe7aa622db96b5cd601f59d09c4f00b98b76079 -dnl # timekeeping: Provide y2038 safe accessor to the seconds portion of CLOCK_REALTIME -dnl # -AC_DEFUN([AC_AMDGPU_KTIME_GET_REAL_SECONDS_REAL], [ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - #include - ],[ - ktime_get_real_seconds(); - ],[ktime_get_real_seconds],[kernel/time/timekeeping.c],[ - AC_DEFINE(HAVE_KTIME_GET_REAL_SECONDS, 1, - [ktime_get_real_seconds() is available]) - ]) -]) - AC_DEFUN([AC_AMDGPU_KTIME_GET_REAL_SECONDS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drm_backport.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - ktime_get_real_seconds(); - ], [ - AC_DEFINE(HAVE_KTIME_GET_REAL_SECONDS, 1, - [ktime_get_real_seconds() is available in drm_backport.h]) - ], [ - AC_AMDGPU_KTIME_GET_REAL_SECONDS_REAL - ]) + dnl # + dnl # commit dbe7aa622db96b5cd601f59d09c4f00b98b76079 + dnl # timekeeping: Provide y2038 safe accessor to the seconds portion of CLOCK_REALTIME + dnl # + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRM_BACKPORT_H + #include + #endif + #include + #include + ], [ + ktime_get_real_seconds(); ], [ - AC_AMDGPU_KTIME_GET_REAL_SECONDS_REAL + AC_DEFINE(HAVE_KTIME_GET_REAL_SECONDS, 1, + [ktime_get_real_seconds() is available]) ]) ]) ]) From 2bdd45ee912886c5bf65c963f00897bb6cc3d8a5 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 5 Feb 2021 10:57:32 +0800 Subject: [PATCH 0428/2653] drm/amdkcl: refactor test for drm_driver_feature Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../gpu/drm/amd/dkms/m4/drm-driver-feature.m4 | 59 ++++++++++--------- 1 file changed, 31 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 index 0970897b2338a..d10e0fcde3942 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 @@ -8,16 +8,15 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ dnl # drm: introduce a capability flag for syncobj timeline support dnl # AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - int _ = DRIVER_SYNCOBJ_TIMELINE; - ],[ - AC_DEFINE(HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE, 1, [ - drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available]) - ]) - ], [ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ],[ + int _ = DRIVER_SYNCOBJ_TIMELINE; + ],[ AC_DEFINE(HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE, 1, [ drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available]) ]) @@ -28,15 +27,17 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ dnl # drm/irq: Ditch DRIVER_IRQ_SHARED dnl # AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - int _ = DRIVER_IRQ_SHARED; - ],[ - AC_DEFINE(HAVE_DRM_DRV_DRIVER_IRQ_SHARED, 1, [ - drm_driver_feature DRIVER_IRQ_SHARED is available]) - ]) + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ],[ + int _ = DRIVER_IRQ_SHARED; + ],[ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_IRQ_SHARED, 1, [ + drm_driver_feature DRIVER_IRQ_SHARED is available]) ]) ]) @@ -45,15 +46,17 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ dnl # drm/prime: Actually remove DRIVER_PRIME everywhere dnl # AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - int _ = DRIVER_PRIME; - ],[ - AC_DEFINE(HAVE_DRM_DRV_DRIVER_PRIME, 1, [ - drm_driver_feature DRIVER_PRIME is available]) - ]) + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ],[ + int _ = DRIVER_PRIME; + ],[ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_PRIME, 1, [ + drm_driver_feature DRIVER_PRIME is available]) ]) ]) ]) From ff35f1ab0c7e1a4d79ec32bd0bd49192af8c1608 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 5 Feb 2021 11:20:01 +0800 Subject: [PATCH 0429/2653] drm/amdkcl: refactor test for drm_device Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../gpu/drm/amd/dkms/m4/struct_drm_device.m4 | 26 ++++++++++--------- 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 index 7016ff6694c88..7ea0061caa47e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 @@ -3,14 +3,16 @@ dnl # commit v4.19-rc1-194-g18ace11f87e6 dnl # drm: Introduce per-device driver_features dnl # AC_DEFUN([AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES], [ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - struct drm_device *ddev = NULL; - ddev->driver_features = 0; - ],[ - AC_DEFINE(HAVE_DRM_DEVICE_DRIVER_FEATURES, 1, - [dev_device->driver_features is available]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_device *ddev = NULL; + ddev->driver_features = 0; + ],[ + AC_DEFINE(HAVE_DRM_DEVICE_DRIVER_FEATURES, 1, + [dev_device->driver_features is available]) + ]) ]) ]) @@ -19,6 +21,7 @@ dnl # commit v5.5-rc2-1419-g7e13ad896484 dnl # drm: Avoid drm_global_mutex for simple inc/dec of dev->open_count dnl # AC_DEFUN([AC_AMDGPU_DRM_DEVICE_OPEN_COUNT], [ + AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ #include ],[ @@ -28,11 +31,10 @@ AC_DEFUN([AC_AMDGPU_DRM_DEVICE_OPEN_COUNT], [ AC_DEFINE(HAVE_DRM_DEVICE_OPEN_COUNT_INT, 1, [drm_device->open_count is int]) ]) + ]) ]) AC_DEFUN([AC_AMDGPU_STRUCT_DRM_DEVICE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES - AC_AMDGPU_DRM_DEVICE_OPEN_COUNT - ]) + AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES + AC_AMDGPU_DRM_DEVICE_OPEN_COUNT ]) From db452520bf887741bdaf89908423919aa859feec Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 5 Feb 2021 11:24:09 +0800 Subject: [PATCH 0430/2653] drm/amdkcl: refactor test for drm_framebuffer Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../drm/amd/dkms/m4/drm-framebuffer-format.m4 | 20 +++++++++---------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 index 977ed577e27c8..5a219b26d81bb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 @@ -4,17 +4,15 @@ dnl # drm: Store a pointer to drm_format_info under drm_framebuffer dnl # AC_DEFUN([AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - #include - ], [ - struct drm_framebuffer *foo = NULL; - foo->format = NULL; - ], [ - AC_DEFINE(HAVE_DRM_FRAMEBUFFER_FORMAT, 1, - [whether struct drm_framebuffer have format]) - ]) + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ], [ + struct drm_framebuffer *foo = NULL; + foo->format = NULL; ], [ AC_DEFINE(HAVE_DRM_FRAMEBUFFER_FORMAT, 1, [whether struct drm_framebuffer have format]) From 654e36266ca4c637912e06f860fd8601333e029c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sun, 7 Feb 2021 11:34:46 +0800 Subject: [PATCH 0431/2653] drm/amdkcl: refactor test for drm/drm_audio_component.h Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 ------------------ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 ---- .../amd/dkms/m4/drm-audio-component-header.m4 | 9 --------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 4 files changed, 32 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1ffa0a6e0fd8e..35cfefe72a08d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -78,9 +78,7 @@ #include #include -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) #include -#endif #include #include @@ -95,9 +93,7 @@ #include #include #include -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) #include -#endif #include #ifdef CONFIG_DRM_AMD_DC_HDCP #include @@ -1062,7 +1058,6 @@ static void amdgpu_dm_fbc_init(struct drm_connector *connector) } -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, int pipe, bool *enabled, unsigned char *buf, int max_bytes) @@ -1207,7 +1202,6 @@ static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) pin, -1); } } -#endif static int dm_dmub_hw_init(struct amdgpu_device *adev) { @@ -1856,9 +1850,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) mutex_init(&adev->dm.dpia_aux_lock); mutex_init(&adev->dm.dc_lock); -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) mutex_init(&adev->dm.audio_lock); -#endif if (amdgpu_dm_irq_init(adev)) { drm_err(adev_to_drm(adev), "failed to initialize DM IRQ support.\n"); @@ -2270,9 +2262,7 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) adev->dm.freesync_module = NULL; } -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) mutex_destroy(&adev->dm.audio_lock); -#endif mutex_destroy(&adev->dm.dc_lock); mutex_destroy(&adev->dm.dpia_aux_lock); } @@ -4724,14 +4714,12 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) } #endif -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) r = amdgpu_dm_audio_init(adev); if (r) { dc_state_release(state->context); kfree(state); return r; } -#endif return 0; } @@ -8554,9 +8542,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, aconnector->base.stereo_allowed = false; aconnector->base.dpms = DRM_MODE_DPMS_OFF; aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) aconnector->audio_inst = -1; -#endif aconnector->pack_sdp_v1_3 = false; aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); @@ -9836,7 +9822,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, kfree(bundle); } -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) static void amdgpu_dm_commit_audio(struct drm_device *dev, struct drm_atomic_state *state) { @@ -9917,7 +9902,6 @@ static void amdgpu_dm_commit_audio(struct drm_device *dev, amdgpu_dm_audio_eld_notify(adev, inst); } } -#endif /* * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC @@ -10631,10 +10615,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) acrtc->wb_enabled = true; } -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) /* Update audio instances for each connector. */ amdgpu_dm_commit_audio(dev, state); -#endif /* restore the backlight level */ for (i = 0; i < dm->num_of_edps; i++) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 83db6da8f1a63..6d04b4a2e0de7 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -452,7 +452,6 @@ struct amdgpu_display_manager { */ struct mutex dc_lock; -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) /** * @audio_lock: * @@ -474,7 +473,6 @@ struct amdgpu_display_manager { * successfully, false otherwise. */ bool audio_registered; -#endif /** * @irq_handler_list_low_tab: @@ -802,10 +800,8 @@ struct amdgpu_dm_connector { */ int max_vfreq ; -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) /* Audio instance - protected by audio_lock. */ int audio_inst; -#endif struct mutex hpd_lock; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 deleted file mode 100644 index 520d72bebcb5c..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 +++ /dev/null @@ -1,9 +0,0 @@ -AC_DEFUN([AC_AMDGPU_DRM_AUDIO_COMPONENT_HEADER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drm_audio_component.h], [ - AC_DEFINE(HAVE_DRM_AUDIO_COMPONENT_HEADER, 1, - [whether drm/drm_audio_component.h is defined]) - ]) - ]) -]) - diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 53245abcb13fa..640b321d5f509 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -51,7 +51,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_SCHED_SET_FIFO_LOW AC_AMDGPU_DMA_FENCE_HEADERS - AC_AMDGPU_DRM_AUDIO_COMPONENT_HEADER AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_SG_TT_INIT AC_AMDGPU_TTM_BUFFER_OBJECT From e5375fafb31eff435874d972573d5a84dd1c02af Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sun, 7 Feb 2021 11:41:06 +0800 Subject: [PATCH 0432/2653] drm/amdkcl: refactor test for drm_debug_enabled Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 | 20 +++++++++---------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 index 0baf031bd2e3d..0250d30115d15 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 @@ -3,17 +3,15 @@ dnl # commit v5.3-rc1-708-gf0a8f533adc2 dnl # drm/print: add drm_debug_enabled() dnl # AC_DEFUN([AC_AMDGPU_DRM_DEBUG_ENABLED], [ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drm_print.h], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - drm_debug_enabled(0); - ],[ - AC_DEFINE(HAVE_DRM_DEBUG_ENABLED, - 1, - [drm_debug_enabled() is available]) - ]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_debug_enabled(0); + ],[ + AC_DEFINE(HAVE_DRM_DEBUG_ENABLED, + 1, + [drm_debug_enabled() is available]) ]) ]) ]) From 7bae85dfdecf064665864abbc88f0eff505cc969 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sun, 7 Feb 2021 13:50:01 +0800 Subject: [PATCH 0433/2653] drm/amdkcl: refactor drm-fb-helper-xxx Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../amd/dkms/m4/drm-fb-helper-fill-info.m4 | 18 +++-- ...per-remove-conflicting-pci-framebuffers.m4 | 69 +++++++++---------- .../m4/drm-fb-helper-set-suspend-unlocked.m4 | 18 +++-- 3 files changed, 50 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 index 23832e30bd48e..bf7fcc83d14df 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 @@ -4,16 +4,14 @@ dnl # drm/fb-helper: Fixup fill_info cleanup dnl # AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_FILL_INFO], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - #include - ], [ - drm_fb_helper_fill_info(NULL, NULL, NULL); - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_FILL_INFO, 1, - [drm_fb_helper_fill_info() is available]) - ]) + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ], [ + drm_fb_helper_fill_info(NULL, NULL, NULL); ], [ AC_DEFINE(HAVE_DRM_FB_HELPER_FILL_INFO, 1, [drm_fb_helper_fill_info() is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 index fe519aa4941d2..ec30c7ffa874c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 @@ -4,54 +4,53 @@ dnl # fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers dnl # AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ], [ + drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args]) + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) + ], [ + dnl # + dnl # commit v4.19-rc1-110-g4d18975c78f2 + dnl # Author: Michał Mirosław + dnl # Date: Sat Sep 1 16:08:45 2018 +0200 + dnl # fbdev: add remove_conflicting_pci_framebuffers() + dnl # AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; #include + #endif #include ], [ - drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, NULL); + drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, 0, NULL); ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args]) + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args]) AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) ], [ dnl # - dnl # commit v4.19-rc1-110-g4d18975c78f2 - dnl # Author: Michał Mirosław - dnl # Date: Sat Sep 1 16:08:45 2018 +0200 - dnl # fbdev: add remove_conflicting_pci_framebuffers() + dnl # commit 46eeb2c144956e88197439b5ee5cf221a91b0a81 + dnl # video/fb: Propagate error code from failing to unregister conflicting fb dnl # - AC_KERNEL_TRY_COMPILE([ - #include - #include + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include ], [ - drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, 0, NULL); - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args]) - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) - ], [ - dnl # - dnl # commit 46eeb2c144956e88197439b5ee5cf221a91b0a81 - dnl # video/fb: Propagate error code from failing to unregister conflicting fb - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - int ret = remove_conflicting_framebuffers(NULL, NULL, false); - ], [remove_conflicting_framebuffers], [drivers/video/fbdev/core/fbmem.c], [ - AC_DEFINE(HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT, 1, - [remove_conflicting_framebuffers() returns int]) - ]) + int ret = remove_conflicting_framebuffers(NULL, NULL, false); + ], [remove_conflicting_framebuffers], [drivers/video/fbdev/core/fbmem.c], [ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT, 1, + [remove_conflicting_framebuffers() returns int]) ]) ]) - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args]) - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 index cd00b4a9ac55c..c2502e2f914da 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 @@ -4,16 +4,14 @@ dnl # drm/fb-helper: Add drm_fb_helper_set_suspend_unlocked() dnl # AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - #include - ], [ - drm_fb_helper_set_suspend_unlocked(NULL,0); - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED, 1, - [drm_fb_helper_set_suspend_unlocked() is available]) - ]) + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ], [ + drm_fb_helper_set_suspend_unlocked(NULL,0); ], [ AC_DEFINE(HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED, 1, [drm_fb_helper_set_suspend_unlocked() is available]) From 4bbe5c19988f6df6714f4ed64fe4d81a8df33900 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sun, 7 Feb 2021 17:20:33 +0800 Subject: [PATCH 0434/2653] drm/amdkcl: rework test for drm_calc_vbltimestamp_from_scanoutpos Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 58 ------------ .../drm/amd/backport/include/kcl/kcl_amdgpu.h | 89 ++++++------------ .../drm-calc-vbltimestamp-from-scanoutpos.m4 | 58 ------------ .../drm_calc_vbltimestamp_from_scanoutpos.m4 | 58 ++++++++++++ ...t-scanout-position-in-struct-drm-driver.m4 | 94 ------------------- ...t-vblank-timestamp-in-struct-drm-driver.m4 | 68 -------------- .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 2 - 7 files changed, 87 insertions(+), 340 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-calc-vbltimestamp-from-scanoutpos.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_calc_vbltimestamp_from_scanoutpos.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/get-scanout-position-in-struct-drm-driver.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/get-vblank-timestamp-in-struct-drm-driver.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 85fc55675951c..3289dc90c54e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1693,64 +1693,6 @@ void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) amdgpu_irq_put(adev, &adev->crtc_irq, idx); } -#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP -#if !defined(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_USE_KTIMER_T_ARG) -/** - * amdgpu_get_vblank_timestamp_kms - get vblank timestamp - * - * @dev: drm dev pointer - * @crtc: crtc to get the timestamp for - * @max_error: max error - * @vblank_time: time value - * @flags: flags passed to the driver - * - * Gets the timestamp on the requested crtc based on the - * scanout position. (all asics). - * Returns postive status flags on success, negative error on failure. - */ -int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, - int *max_error, - struct timeval *vblank_time, - unsigned flags) -{ - struct drm_crtc *crtc; - struct amdgpu_device *adev = drm_to_adev(dev); - - if (pipe >= dev->num_crtcs) { - DRM_ERROR("Invalid crtc %u\n", pipe); - return -EINVAL; - } - - /* Get associated drm_crtc: */ - crtc = &adev->mode_info.crtcs[pipe]->base; - if (!crtc) { - /* This can occur on driver load if some component fails to - * initialize completely and driver is unloaded */ - DRM_ERROR("Uninitialized crtc %d\n", pipe); - return -EINVAL; - } - - /* Helper routine in DRM core does all the work: */ -#if defined(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_DROP_MOD_ARG) - return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, - vblank_time, flags); -#elif defined(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_HAVE_MODE_ARG) - return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, - vblank_time, flags, - &crtc->hwmode); -#elif defined(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_HAVE_CRTC_MODE_ARG) - return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, - vblank_time, flags, - crtc, &crtc->hwmode); -#else - return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, - vblank_time, flags, - crtc); -#endif -} -#endif -#endif - /* * Debugfs info */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h index 5c6fe94ccd030..383d7ec209af1 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -7,41 +7,28 @@ #include #ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP - -#if defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) static inline u32 kcl_amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int crtc) -#else -static inline u32 kcl_amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc) -#endif { struct drm_crtc *drm_crtc = drm_crtc_from_index(dev, crtc); return amdgpu_get_vblank_counter_kms(drm_crtc); } -#if defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) static inline int kcl_amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int crtc) -#else -static inline int kcl_amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc) -#endif { struct drm_crtc *drm_crtc = drm_crtc_from_index(dev, crtc); return amdgpu_enable_vblank_kms(drm_crtc); } -#if defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) static inline void kcl_amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int crtc) -#else -static inline void kcl_amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc) -#endif { struct drm_crtc *drm_crtc = drm_crtc_from_index(dev, crtc); return amdgpu_disable_vblank_kms(drm_crtc); } -#if defined(HAVE_GET_SCANOUT_POSITION_RETURN_BOOL) +#if defined(HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL) static inline bool kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, bool in_vblank_irq, int *vpos, int *hpos, ktime_t *stime, ktime_t *etime, @@ -49,75 +36,57 @@ static inline bool kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, { return !!amdgpu_display_get_crtc_scanoutpos(dev, pipe, in_vblank_irq, vpos, hpos, stime, etime, mode); } -#elif defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) -static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int crtc, +#else +static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, unsigned int flags, int *vpos, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode) { - return amdgpu_display_get_crtc_scanoutpos(dev, crtc, flags, vpos, hpos, stime, etime, mode); -} -#elif defined(HAVE_GET_SCANOUT_POSITION_HAS_DRM_DISPLAY_MODE_ARG) -static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, int crtc, - unsigned int flags, - int *vpos, int *hpos, - ktime_t *stime, ktime_t *etime, - const struct drm_display_mode *mode) -{ - return amdgpu_display_get_crtc_scanoutpos(dev, crtc, flags, vpos, hpos, stime, etime, mode); -} -#elif defined(HAVE_GET_SCANOUT_POSITION_HAS_TIMESTAMP_ARG) -static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, int crtc, - int *vpos, int *hpos, ktime_t *stime, - ktime_t *etime) -{ - return amdgpu_display_get_crtc_scanoutpos(dev, crtc, 0, vpos, hpos, stime, etime, NULL); -} -#else -static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, int crtc, - int *vpos, int *hpos) -{ - return amdgpu_display_get_crtc_scanoutpos(dev, crtc, 0, vpos, hpos, NULL, NULL, NULL); + return amdgpu_display_get_crtc_scanoutpos(dev, pipe, flags, vpos, hpos, stime, etime, mode); } #endif -#if defined(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_KTIME_T) +#if defined(HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG) static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, int *max_error, ktime_t *vblank_time, bool in_vblank_irq) { return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, vblank_time, in_vblank_irq); } -#elif defined(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_BOOL_IN_VBLANK_IRQ) +#elif defined(HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_RETURN_BOOL) static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, int *max_error, struct timeval *vblank_time, bool in_vblank_irq) { - return !!amdgpu_get_vblank_timestamp_kms(dev, pipe, max_error, vblank_time, in_vblank_irq); -} -#elif defined(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_RETURN_BOOL) -static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, - int *max_error, struct timeval *vblank_time, - unsigned flags) -{ - return !!amdgpu_get_vblank_timestamp_kms(dev, pipe, max_error, vblank_time, flags); + return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, vblank_time, in_vblank_irq); } -#elif defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) +#else static inline int kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, int *max_error, struct timeval *vblank_time, unsigned flags) { - return amdgpu_get_vblank_timestamp_kms(dev, pipe, max_error, vblank_time, flags); -} -#else -static inline int kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, - int *max_error, - struct timeval *vblank_time, - unsigned flags) -{ - return amdgpu_get_vblank_timestamp_kms(dev, crtc, max_error, vblank_time, flags); + struct drm_crtc *crtc; + struct amdgpu_device *adev = drm_to_adev(dev); + + if (pipe >= dev->num_crtcs) { + DRM_ERROR("Invalid crtc %u\n", pipe); + return -EINVAL; + } + + /* Get associated drm_crtc: */ + crtc = &adev->mode_info.crtcs[pipe]->base; + if (!crtc) { + /* This can occur on driver load if some component fails to + * initialize completely and driver is unloaded */ + DRM_ERROR("Uninitialized crtc %d\n", pipe); + return -EINVAL; + } + + return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, + vblank_time, flags, + &crtc->hwmode); } -#endif +#endif /* HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG */ #endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP */ #endif /* AMDGPU_BACKPORT_KCL_AMDGPU_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-calc-vbltimestamp-from-scanoutpos.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-calc-vbltimestamp-from-scanoutpos.m4 deleted file mode 100644 index c69de05235130..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-calc-vbltimestamp-from-scanoutpos.m4 +++ /dev/null @@ -1,58 +0,0 @@ -dnl # -dnl # commit 67680d3c0464 -dnl # drm: vblank: use ktime_t instead of timeval -dnl # -AC_DEFUN([AC_AMDGPU_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS], [ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, (ktime_t *)NULL, 0); - ], [drm_calc_vbltimestamp_from_scanoutpos], [drivers/gpu/drm/drm_vblank.c], [ - AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_USE_KTIMER_T_ARG, 1, - [drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg]) - ], [ - dnl # - dnl # commit 1bf6ad622b9be - dnl # drm/vblank: drop the mode argument from drm_calc_vbltimestamp_from_scanoutpos - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, (struct timeval *)NULL, 0); - ], [drm_calc_vbltimestamp_from_scanoutpos], [drivers/gpu/drm/drm_vblank.c drivers/gpu/drm/drm_irq.c], [ - AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_DROP_MOD_ARG, 1, - [drm_calc_vbltimestamp_from_scanoutpos() drop mode arg]) - ], [ - dnl # - dnl # commit eba1f35dfe14 - dnl # drm: Move timestamping constants into drm_vblank_crtc - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, NULL, 0, (const struct drm_display_mode *)NULL); - ], [drm_calc_vbltimestamp_from_scanoutpos], [drivers/gpu/drm/drm_irq.c], [ - AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_HAVE_MODE_ARG, 1, - [drm_calc_vbltimestamp_from_scanoutpos() remove crtc arg]) - ], [ - dnl # - dnl # commit 7da903ef0485 - dnl # drm: Pass the display mode to drm_calc_vbltimestamp_from_scanoutpos() - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, NULL, 0, (const struct drm_crtc *)NULL, (const struct drm_display_mode *)NULL); - ], [drm_calc_vbltimestamp_from_scanoutpos], [drivers/gpu/drm/drm_irq.c], [ - AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_HAVE_CRTC_MODE_ARG, 1, - [drm_calc_vbltimestamp_from_scanoutpos() have the crtc & mode arg]) - ]) - ]) - ]) - ]) - ], [ - AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_USE_KTIMER_T_ARG, 1, - [drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_calc_vbltimestamp_from_scanoutpos.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_calc_vbltimestamp_from_scanoutpos.m4 new file mode 100644 index 0000000000000..35e273468a27f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_calc_vbltimestamp_from_scanoutpos.m4 @@ -0,0 +1,58 @@ +dnl # +dnl # commit v4.14-rc3-721-g67680d3c0464 +dnl # drm: vblank: use ktime_t instead of timeval +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #else + #include + #include + #endif + ], [ + struct drm_driver *kms_driver = NULL; + bool (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe, + int *max_error, + ktime_t *vblank_time, + bool in_vblank_irq); + drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, (ktime_t *)NULL, 0); + kms_driver->get_vblank_timestamp = get_vblank_timestamp; + ], [ + AC_DEFINE(HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG, 1, + [drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg]) + AC_DEFINE(HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL, 1, + [drm_driver->get_scanout_position() return bool]) + ], [ + dnl # + dnl # v4.11-rc7-1902-g1bf6ad622b9b drm/vblank: drop the mode argument from drm_calc_vbltimestamp_from_scanoutpos + dnl # v4.11-rc7-1900-g3fcdcb270936 drm/vblank: Switch to bool in_vblank_irq in get_vblank_timestamp + dnl # v4.11-rc7-1899-gd673c02c4bdb drm/vblank: Switch drm_driver->get_vblank_timestamp to return a bool + dnl # + AC_KERNEL_TRY_COMPILE([ + struct vm_area_struct; + #include + ], [ + struct drm_driver *kms_driver = NULL; + bool (*get_scanout_position) (struct drm_device *dev, unsigned int pipe, + bool in_vblank_irq, int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode); + bool (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe, + int *max_error, + struct timeval *vblank_time, + bool in_vblank_irq); + kms_driver->get_scanout_position = get_scanout_position; + kms_driver->get_vblank_timestamp = get_vblank_timestamp; + drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, (struct timeval *)NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL, 1, + [drm_driver->get_scanout_position() return bool]) + AC_DEFINE(HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_RETURN_BOOL, 1, + [drm_driver->get_vblank_timestamp() return bool]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-scanout-position-in-struct-drm-driver.m4 b/drivers/gpu/drm/amd/dkms/m4/get-scanout-position-in-struct-drm-driver.m4 deleted file mode 100644 index 6f0105f6f9890..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/get-scanout-position-in-struct-drm-driver.m4 +++ /dev/null @@ -1,94 +0,0 @@ -dnl # -dnl # commit v4.11-rc7-1902-g1bf6ad622b9b -dnl # drm/vblank: drop the mode argument from drm_calc_vbltimestamp_from_scanoutpos -dnl # -AC_DEFUN([AC_AMDGPU_GET_SCANOUT_POSITION_IN_DRM_DRIVER], [ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - bool foo(struct drm_device *dev, unsigned int pipe, - bool in_vblank_irq, int *vpos, int *hpos, - ktime_t *stime, ktime_t *etime, - const struct drm_display_mode *mode) - { - return false; - } - ], [ - struct drm_driver *bar = NULL; - bar->get_scanout_position = foo; - ], [ - AC_DEFINE(HAVE_GET_SCANOUT_POSITION_RETURN_BOOL, 1, - [get_scanout_position return bool]) - AC_DEFINE(HAVE_VGA_USE_UNSIGNED_INT_PIPE, 1, - [get_scanout_position use unsigned int pipe]) - ], [ - dnl # - dnl # commit v4.3-rc3-73-g88e72717c2de - dnl # drm/irq: Use unsigned int pipe in public API - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - int foo(struct drm_device *dev, unsigned int pipe, - unsigned int flags, int *vpos, int *hpos, - ktime_t *stime, ktime_t *etime, - const struct drm_display_mode *mode) - { - return 0; - } - ], [ - struct drm_driver *bar = NULL; - bar->get_scanout_position = foo; - ], [ - AC_DEFINE(HAVE_VGA_USE_UNSIGNED_INT_PIPE, 1, - [get_scanout_position use unsigned int pipe]) - ], [ - dnl # - dnl # commit v4.3-rc2-44-g3bb403bf421b - dnl # drm: Stop using linedur_ns and pixeldur_ns for vblank timestamps - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - int foo(struct drm_device *dev, int crtc, - unsigned int flags, - int *vpos, int *hpos, - ktime_t *stime, ktime_t *etime, - const struct drm_display_mode *mode) - { - return 0; - } - ], [ - struct drm_driver *bar = NULL; - bar->get_scanout_position = foo; - ], [ - AC_DEFINE(HAVE_GET_SCANOUT_POSITION_HAS_DRM_DISPLAY_MODE_ARG, 1, - [get_scanout_position has struct drm_display_mode arg]) - ], [ - dnl # - dnl # commit v3.12-rc3-485-g8f6fce03ddaf - dnl # drm: Push latency sensitive bits of vblank scanoutpos timestamping into kms drivers. - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - int foo(struct drm_device *dev, int crtc, - int *vpos, int *hpos, ktime_t *stime, - ktime_t *etime) - { - return 0; - } - ], [ - struct drm_driver *bar = NULL; - bar->get_scanout_position = foo; - ], [ - AC_DEFINE(HAVE_GET_SCANOUT_POSITION_HAS_TIMESTAMP_ARG, 1, - [get_scanout_position has timestamp arg]) - ]) - ]) - ]) - ]) - ], [ - AC_DEFINE(HAVE_GET_SCANOUT_POSITION_RETURN_BOOL, 1, - [get_scanout_position return bool]) - AC_DEFINE(HAVE_VGA_USE_UNSIGNED_INT_PIPE, 1, - [get_scanout_position use unsigned int pipe]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-vblank-timestamp-in-struct-drm-driver.m4 b/drivers/gpu/drm/amd/dkms/m4/get-vblank-timestamp-in-struct-drm-driver.m4 deleted file mode 100644 index 8037673d5aa39..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/get-vblank-timestamp-in-struct-drm-driver.m4 +++ /dev/null @@ -1,68 +0,0 @@ -dnl # commit v4.14-rc3-721-g67680d3c0464 -dnl # drm: vblank: use ktime_t instead of timeval -dnl # -AC_DEFUN([AC_AMDGPU_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER], [ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - bool foo(struct drm_device *dev, unsigned int pipe, - int *max_error, - ktime_t *vblank_time, - bool in_vblank_irq) - { - return false; - } - ], [ - struct drm_driver *bar = NULL; - bar->get_vblank_timestamp = foo; - ], [ - AC_DEFINE(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_KTIME_T, 1, - [get_vblank_timestamp has ktime_t arg]) - ], [ - dnl - dnl # commit v4.11-rc7-1900-g3fcdcb270936 - dnl # drm/vblank: Switch to bool in_vblank_irq in get_vblank_timestamp - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - bool foo(struct drm_device *dev, unsigned int pipe, - int *max_error, - struct timeval *vblank_time, - bool in_vblank_irq) - { - return false; - } - ], [ - struct drm_driver *bar = NULL; - bar->get_vblank_timestamp = foo; - ], [ - AC_DEFINE(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_BOOL_IN_VBLANK_IRQ, 1, - [get_vblank_timestamp has bool in_vblank_irq arg]) - ], [ - dnl # - dnl # commit id v4.11-rc7-1899-gd673c02c4bdb - dnl # drm/vblank: Switch drm_driver->get_vblank_timestamp to return a bool - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - bool foo(struct drm_device *dev, unsigned int pipe, - int *max_error, - struct timeval *vblank_time, - unsigned flags) - { - return false; - } - ], [ - struct drm_driver *bar = NULL; - bar->get_vblank_timestamp = foo; - ], [ - AC_DEFINE(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_RETURN_BOOL, 1, - [get_vblank_timestamp return bool]) - ]) - ]) - ]) - ], [ - AC_DEFINE(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_KTIME_T, 1, - [get_vblank_timestamp has ktime_t arg]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index ec6c920089ae1..2820aaa74c3b0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -16,8 +16,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP], [ 1, [struct drm_crtc_funcs->get_vblank_timestamp() is available]) ],[ - AC_AMDGPU_GET_SCANOUT_POSITION_IN_DRM_DRIVER - AC_AMDGPU_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER AC_AMDGPU_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS ]) ]) From 33c82cad5cb2ec5aba143e0129bafce52a36fb1c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 19 Feb 2021 14:21:21 +0800 Subject: [PATCH 0435/2653] drm/amdkcl: simplify test for drm_connector_xxx the prototype change is introduced in a series of patch. no need to test for each api. Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- .../amd/dkms/m4/drm-connector-attach-encoder.m4 | 16 ---------------- .../dkms/m4/drm-connector-set-path-property.m4 | 16 ---------------- .../m4/drm-connector-update-edid-property.m4 | 16 ---------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 --- include/kcl/kcl_drm_connector.h | 12 ------------ 5 files changed, 63 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 deleted file mode 100644 index 9b4bd0e561b64..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit cde4c44d8769c1be16074c097592c46c7d64092b -dnl # drm: drop _mode_ from drm_mode_connector_attach_encode -dnl # -AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ],[ - drm_connector_attach_encoder(NULL, NULL); - ],[drm_connector_attach_encoder],[drivers/gpu/drm/drm_connector.c],[ - AC_DEFINE(HAVE_DRM_CONNECTOR_ATTACH_ENCODER, 1, - [drm_connector_attach_encoder() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 deleted file mode 100644 index f872d0db19a2e..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit 97e14fbeb53fe060c5f6a7a07e37fd24c087ed0c -dnl # drm: drop _mode_ from remaining connector functions -dnl # -AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ],[ - drm_connector_set_path_property(NULL, NULL); - ],[drm_connector_set_path_property],[drivers/gpu/drm/drm_connector.c],[ - AC_DEFINE(HAVE_DRM_CONNECTOR_SET_PATH_PROPERTY, 1, - [drm_connector_set_path_property() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 deleted file mode 100644 index eade2ed63d298..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit c555f02371c338b06752577aebf738dbdb6907bd -dnl # drm: drop _mode_ from update_edit_property() -dnl # -AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ],[ - drm_connector_update_edid_property(NULL, NULL); - ],[drm_connector_update_edid_property],[drivers/gpu/drm/drm_connector.c],[ - AC_DEFINE(HAVE_DRM_CONNECTOR_UPDATE_EDID_PROPERTY, 1, - [drm_connector_update_edid_property() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 640b321d5f509..a165f396ac171 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -72,9 +72,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS - AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY - AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER - AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_CALC_PBN_MODE AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 8eb2f3e647417..9074a56cce9fd 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -34,18 +34,6 @@ #define AMDKCL_AMDGPU_DRM_CONNECTOR_STATUS_DETECT_MANDATORY #endif -#ifndef HAVE_DRM_CONNECTOR_UPDATE_EDID_PROPERTY -#define drm_connector_update_edid_property drm_mode_connector_update_edid_property -#endif - -#ifndef HAVE_DRM_CONNECTOR_ATTACH_ENCODER -#define drm_connector_attach_encoder drm_mode_connector_attach_encoder -#endif - -#ifndef HAVE_DRM_CONNECTOR_SET_PATH_PROPERTY -#define drm_connector_set_path_property drm_mode_connector_set_path_property -#endif - /** * drm_connector_for_each_possible_encoder - iterate connector's possible encoders * @connector: &struct drm_connector pointer From 7f721d6ffdefad163d9e24737f3f57598db7f389 Mon Sep 17 00:00:00 2001 From: xinhui pan Date: Wed, 18 Mar 2020 16:50:45 +0800 Subject: [PATCH 0436/2653] drm/amdgpu: fix OOM panic and deadlock In mmu release, we schedule a work to free amn. however there is race between exit_mmap and oom_reap_task_mm. exit_mmap -> mmu_notifier_release oom_reap_task_mm -> __oom_reap_task_mm -> mmu_notifier_invalidate_range_start_nonblock So the amn might have been freed. sync rcu in destroy to wait for ongoing range invalidate. calltrace: [ 4407.908455] BUG: kernel NULL pointer dereference, address: 0000000000000050 [ 4407.915591] #PF: supervisor read access in kernel mode [ 4407.920827] #PF: error_code(0x0000) - not-present page [ 4407.926079] PGD 0 P4D 0 [ 4407.928662] Oops: 0000 [#1] SMP PTI [ 4407.932216] CPU: 3 PID: 55 Comm: oom_reaper Tainted: G W O 5.4.0-rc7+ #1 [ 4407.940206] Hardware name: System manufacturer System Product Name/Z170-A, BIOS 1702 01/28/2016 [ 4407.949080] RIP: 0010:mark_lock+0xc9/0x540 [ 4407.953282] Code: 31 c0 eb 12 48 8d 14 80 48 8d 04 50 48 c1 e0 04 48 05 00 dd 01 9c 41 bc 01 00 00 00 89 d9 41 bf 01 00 00 00 41 d3 e4 4d 63 e4 <4c> 85 60 50 0f 85 50 ff ff ff e8 18 bb ff ff 85 c0 0f 84 40 ff ff [ 4407.972385] RSP: 0018:ffffab4440253ab0 EFLAGS: 00010006 [ 4407.977723] RAX: 0000000000000000 RBX: 0000000000000008 RCX: 0000000000000008 [ 4407.984977] RDX: ffff9df1d9fd8040 RSI: 0000000000000001 RDI: ffffffff9a318d0a [ 4407.992222] RBP: ffffab4440253af0 R08: 0000000000000000 R09: 000000000003b540 [ 4407.999493] R10: 0000000000000000 R11: 0000000000000037 R12: 0000000000000100 [ 4408.006774] R13: ffff9df1d9fd8040 R14: ffff9df1d9fd8c88 R15: 0000000000000001 [ 4408.014062] FS: 0000000000000000(0000) GS:ffff9df1de180000(0000) knlGS:0000000000000000 [ 4408.022295] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 4408.028154] CR2: 0000000000000050 CR3: 0000000393410001 CR4: 00000000003606e0 [ 4408.035427] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 4408.042689] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 4408.049968] Call Trace: [ 4408.052467] __lock_acquire+0x261/0x1600 [ 4408.056486] ? __lock_acquire+0x43a/0x1600 [ 4408.060628] ? __lock_acquire+0x43a/0x1600 [ 4408.064816] lock_acquire+0xb8/0x1c0 [ 4408.068482] ? rwsem_down_read_slowpath+0x1e8/0x5f0 [ 4408.073509] _raw_spin_lock_irq+0x3b/0x50 [ 4408.077624] ? rwsem_down_read_slowpath+0x1e8/0x5f0 [ 4408.082582] rwsem_down_read_slowpath+0x1e8/0x5f0 [ 4408.087401] ? finish_task_switch+0x63/0x230 [ 4408.091759] ? __schedule+0x2b3/0x860 [ 4408.095487] down_read_non_owner+0x86/0x160 [ 4408.099767] ? down_read_non_owner+0x86/0x160 [ 4408.104295] amdgpu_mn_read_lock+0x9f/0xb0 [amdgpu] [ 4408.109364] amdgpu_mn_invalidate_range_start_gfx+0x3f/0x1e0 [amdgpu] [ 4408.115941] __mmu_notifier_invalidate_range_start+0x9e/0x190 [ 4408.121816] ? __oom_reap_task_mm+0x6d/0x220 [ 4408.126166] __oom_reap_task_mm+0x1b5/0x220 [ 4408.130450] oom_reaper+0x4d0/0x650 [ 4408.133991] ? __kthread_parkme+0x2f/0x90 [ 4408.138083] ? finish_wait+0x90/0x90 [ 4408.141715] kthread+0x12c/0x150 [ 4408.145043] ? __oom_reap_task_mm+0x220/0x220 [ 4408.149461] ? kthread_park+0x90/0x90 [ 4408.153208] ret_from_fork+0x3a/0x50 There is another deadlock. calltrace: [ 1635.072660] BUG: sleeping function called from invalid context at ../kernel/locking/rwsem.c:1621 [ 1635.081870] in_atomic(): 0, irqs_disabled(): 0, non_block: 1, pid: 55, name: oom_reaper [ 1635.090106] 4 locks held by oom_reaper/55: [ 1635.091485] init_user_pages: Failed to get user pages: -512 [ 1635.094302] #0: ffff9ca48e94b5d8 (&mm->mmap_sem#2){++++}, at: oom_reaper+0xa4/0x650 [ 1635.108116] #1: ffffffff82750fc0 (mmu_notifier_invalidate_range_start){+.+.}, at: __oom_reap_task_mm+0x6d/0x220 [ 1635.118558] #2: ffffffff827637f0 (srcu){....}, at: __mmu_notifier_invalidate_range_start+0x5/0x190 [ 1635.127879] #3: ffff9ca4f7c605f0 (&amn->read_lock){+.+.}, at: amdgpu_mn_read_lock+0x75/0xb0 [amdgpu] [ 1635.137614] CPU: 3 PID: 55 Comm: oom_reaper Tainted: G W O 5.4.0-rc7+ #1 [ 1635.145787] Hardware name: System manufacturer System Product Name/Z170-A, BIOS 1702 01/28/2016 [ 1635.154744] Call Trace: [ 1635.157264] dump_stack+0x98/0xd5 [ 1635.160688] ___might_sleep+0x175/0x260 [ 1635.164675] __might_sleep+0x4a/0x80 [ 1635.168340] down_read_non_owner+0x20/0x160 [ 1635.172748] amdgpu_mn_read_lock+0x9f/0xb0 [amdgpu] [ 1635.177884] amdgpu_mn_invalidate_range_start_hsa+0x3f/0x180 [amdgpu] [ 1635.184477] __mmu_notifier_invalidate_range_start+0x9e/0x190 [ 1635.190337] ? __oom_reap_task_mm+0x6d/0x220 [ 1635.194725] __oom_reap_task_mm+0x1b5/0x220 [ 1635.199069] oom_reaper+0x4d0/0x650 [ 1635.202611] ? __kthread_parkme+0x2f/0x90 [ 1635.206740] ? finish_wait+0x90/0x90 [ 1635.210425] kthread+0x12c/0x150 [ 1635.213714] ? __oom_reap_task_mm+0x220/0x220 [ 1635.218215] ? kthread_park+0x90/0x90 [ 1635.221976] ret_from_fork+0x3a/0x50 [ 1815.108088] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 1815.116065] kworker/1:1 D 0 9357 2 0x80004000 [ 1815.121873] Workqueue: events amdgpu_mn_destroy [amdgpu] [ 1815.127264] Call Trace: [ 1815.129765] __schedule+0x2ab/0x860 [ 1815.133299] ? rwsem_down_write_slowpath+0x329/0x660 [ 1815.138382] schedule+0x3a/0xc0 [ 1815.141613] rwsem_down_write_slowpath+0x32e/0x660 [ 1815.146523] down_write+0x74/0x80 [ 1815.149921] ? down_write+0x40/0x80 [ 1815.153490] ? down_write+0x74/0x80 [ 1815.157285] amdgpu_mn_destroy+0x6e/0x240 [amdgpu] [ 1815.162176] process_one_work+0x231/0x5c0 [ 1815.166313] worker_thread+0x3f/0x3b0 [ 1815.170100] ? __kthread_parkme+0x61/0x90 [ 1815.174204] kthread+0x12c/0x150 [ 1815.177573] ? process_one_work+0x5c0/0x5c0 [ 1815.181857] ? kthread_park+0x90/0x90 [ 1815.185591] ret_from_fork+0x3a/0x50 oom killer want to invalidate range in nonblock context. But the amdgpu_mn_read_lock might sleep, and casue deadlock then. Reviewed-by: Flora Cui Signed-off-by: xinhui pan Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 63 ++++++++++++++----------- 1 file changed, 35 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 78a5f32697202..6621f0447d559 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -90,6 +90,9 @@ struct amdgpu_mn { #endif struct mutex read_lock; atomic_t recursion; +#if !defined(HAVE_MMU_NOTIFIER_PUT) + struct rcu_head rcu; +#endif }; /** @@ -105,6 +108,18 @@ struct amdgpu_mn_node { struct list_head bos; }; +#ifdef HAVE_MMU_NOTIFIER_PUT +static void amdgpu_mn_free(struct mmu_notifier *mn) +{ + kfree(container_of(mn, struct amdgpu_mn, mn)); +} +#else +static void amdgpu_mn_free(struct rcu_head *rcu) +{ + kfree(container_of(rcu, struct amdgpu_mn, rcu)); +} +#endif + /** * amdgpu_mn_destroy - destroy the MMU notifier * @@ -136,8 +151,12 @@ static void amdgpu_mn_destroy(struct work_struct *work) } up_write(&amn->lock); mutex_unlock(&adev->mn_lock); +#ifdef HAVE_MMU_NOTIFIER_PUT + mmu_notifier_put(&amn->mn); +#else mmu_notifier_unregister_no_release(&amn->mn, amn->mm); - kfree(amn); + mmu_notifier_call_srcu(&amn->rcu, amdgpu_mn_free); +#endif } /** @@ -188,6 +207,9 @@ void amdgpu_mn_unlock(struct amdgpu_mn *mn) */ static void amdgpu_mn_read_lock(struct amdgpu_mn *amn) { + /* FIXME: Need figure out one way to detect + * if we are in oom reaper context. + */ mutex_lock(&amn->read_lock); if (atomic_inc_return(&amn->recursion) == 1) down_read_non_owner(&amn->lock); @@ -201,11 +223,14 @@ static void amdgpu_mn_read_lock(struct amdgpu_mn *amn) */ static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable) { - if (blockable) - mutex_lock(&amn->read_lock); - else if (!mutex_trylock(&amn->read_lock)) + /* Non blockable occurs only in oom reaper context. + * In this case, process is going to be killed anyway. + * Let oom reaper fail at this stage. + */ + if (!blockable) return -EAGAIN; + mutex_lock(&amn->read_lock); if (atomic_inc_return(&amn->recursion) == 1) down_read_non_owner(&amn->lock); mutex_unlock(&amn->read_lock); @@ -286,11 +311,6 @@ static int amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, while (it) { struct amdgpu_mn_node *node; - if (!mmu_notifier_range_blockable(range)) { - amdgpu_mn_read_unlock(amn); - return -EAGAIN; - } - node = container_of(it, struct amdgpu_mn_node, it); it = interval_tree_iter_next(it, range->start, end); @@ -330,11 +350,6 @@ static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, struct amdgpu_mn_node *node; struct amdgpu_bo *bo; - if (!mmu_notifier_range_blockable(range)) { - amdgpu_mn_read_unlock(amn); - return -EAGAIN; - } - node = container_of(it, struct amdgpu_mn_node, it); it = interval_tree_iter_next(it, range->start, end); @@ -394,13 +409,6 @@ static void amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, while (it) { struct amdgpu_mn_node *node; -#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) - if (!blockable) { - amdgpu_mn_read_unlock(amn); - return -EAGAIN; - } -#endif - node = container_of(it, struct amdgpu_mn_node, it); it = interval_tree_iter_next(it, start, end); @@ -456,13 +464,6 @@ static void amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, struct amdgpu_mn_node *node; struct amdgpu_bo *bo; -#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) - if (!blockable) { - amdgpu_mn_read_unlock(amn); - return -EAGAIN; - } -#endif - node = container_of(it, struct amdgpu_mn_node, it); it = interval_tree_iter_next(it, start, end); @@ -508,11 +509,17 @@ static void amdgpu_mn_invalidate_range_end(struct mmu_notifier *mn, static const struct mmu_notifier_ops amdgpu_mn_ops[] = { [AMDGPU_MN_TYPE_GFX] = { +#ifdef HAVE_MMU_NOTIFIER_PUT + .free_notifier = amdgpu_mn_free, +#endif .release = amdgpu_mn_release, .invalidate_range_start = amdgpu_mn_invalidate_range_start_gfx, .invalidate_range_end = amdgpu_mn_invalidate_range_end, }, [AMDGPU_MN_TYPE_HSA] = { +#ifdef HAVE_MMU_NOTIFIER_PUT + .free_notifier = amdgpu_mn_free, +#endif .release = amdgpu_mn_release, .invalidate_range_start = amdgpu_mn_invalidate_range_start_hsa, .invalidate_range_end = amdgpu_mn_invalidate_range_end, From a19df9ae44619dcc04a34c959770a49ad6fb469e Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Tue, 15 Sep 2020 17:25:54 -0400 Subject: [PATCH 0437/2653] drm/amdgpu: prevent double release ttm->pages If ttm_bo_validate failed, pages are released, but ttm->pages is not cleared, this causes below backtrace. This issue happens on DELL machine with Ubuntu 18.04 kernel 4.15. put pages and set ttm->pages to NULL if ttm_bo_validate failed under memory pressure. [ 5400.077763] 0000:23:00.0: IOMMU mapping error in map_sg (io-pages: 32981732) [ 5400.097080] [drm:amdgpu_ttm_backend_bind [amdgpu]] *ERROR* failed to pin userptr [ 5400.097104] amdgpu: init_user_pages: failed to validate BO [ 5400.285482] BUG: Bad page state in process kfdtest pfn:1f6eac9 [ 5400.285533] page:ffffe07f7dbab240 count:0 mapcount:1 mapping:0000000000000000 index:0x1 [ 5400.285578] flags: 0x17ffffc0000000() [ 5400.285602] raw: 0017ffffc0000000 0000000000000000 0000000000000001 0000000000000000 [ 5400.285643] raw: dead000000000100 dead000000000200 0000000000000000 0000000000000000 [ 5400.285684] page dumped because: nonzero mapcount [ 5400.285710] Modules linked in: xt_conntrack ipt_MASQUERADE 4.15.0-117-generic #118-Ubuntu [ 5400.285779] Hardware name: Dell Inc. PowerEdge R7525/0PYVT1, BIOS 1.5.4 07/09/2020 [ 5400.285780] Call Trace: [ 5400.285793] dump_stack+0x6d/0x8e [ 5400.285798] bad_page+0xcb/0x120 [ 5400.285801] free_pages_check_bad+0x5f/0x70 [ 5400.285803] free_pcppages_bulk+0x44a/0x4e0 [ 5400.285808] ? mem_cgroup_uncharge+0x64/0x70 [ 5400.285810] free_unref_page_commit+0xb1/0xf0 [ 5400.285813] free_unref_page+0x59/0x70 [ 5400.285815] __put_page+0x40/0x80 [ 5400.285906] amdgpu_ttm_tt_set_user_pages+0x64/0xc0 [amdgpu] [ 5400.285983] amdgpu_ttm_tt_unpopulate+0x55/0x80 [amdgpu] [ 5400.285988] ttm_tt_unpopulate.part.10+0x53/0x60 [amdttm] [ 5400.285992] ttm_tt_destroy.part.11+0x4f/0x60 [amdttm] [ 5400.285996] ttm_tt_destroy+0x13/0x20 [amdttm] [ 5400.286000] ttm_bo_cleanup_memtype_use+0x36/0x80 [amdttm] [ 5400.286004] ttm_bo_release+0x1c9/0x360 [amdttm] [ 5400.286008] amdttm_bo_put+0x24/0x30 [amdttm] [ 5400.286083] amdgpu_bo_unref+0x1e/0x30 [amdgpu] [ 5400.286192] amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu+0x9ca/0xb10 [amdgpu] [ 5400.286293] kfd_ioctl_alloc_memory_of_gpu+0xef/0x2c0 [amdgpu] Change-Id: Ide1cac32300e4195257a4faf125f4d85e1fc3d64 Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling Reviewed-by: Oak Zeng --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index e140fca7694eb..7ddc5f2fb768f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1123,7 +1123,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); #else if (ret) - release_pages(mem->user_pages, bo->tbo.ttm->num_pages); + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, NULL); free_out: kvfree(mem->user_pages); mem->user_pages = NULL; From ad5851576d0b0d25c79b6ad3155c402cd4126f6a Mon Sep 17 00:00:00 2001 From: xinhui pan Date: Wed, 4 Nov 2020 11:43:39 +0800 Subject: [PATCH 0438/2653] drm/amdkcl: define __GFP_RETRY_MAYFAIL as __GFP_NORETRY In old kernel, __GFP_NORETRY would not invoke OOM killer. TTM prefers that usage when TTM_PAGE_FLAG_NO_RETRY is set. Signed-off-by: xinhui pan Reviewed-by: Kevin Wang --- include/kcl/kcl_kernel.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index f33fc452d8243..f93febef548d8 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -16,7 +16,7 @@ #endif #ifndef __GFP_RETRY_MAYFAIL -#define __GFP_RETRY_MAYFAIL __GFP_REPEAT +#define __GFP_RETRY_MAYFAIL __GFP_NORETRY #endif #ifndef ALIGN_DOWN From bbaf53f280a809978fef0462c567f802fe24cffa Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 15 Mar 2021 13:28:34 +0800 Subject: [PATCH 0439/2653] drm/amdkcl: fake the fs_reclaim_acquire{release} Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c | 143 ++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/dkms/m4/fs_reclaim_acquire.m4 | 15 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_sched_mm.h | 35 +++++ 7 files changed, 197 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/fs_reclaim_acquire.m4 create mode 100644 include/kcl/kcl_sched_mm.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 3a98d624be313..4ea595282d7d1 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -11,7 +11,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ - kcl_acpi_table.o kcl_drm_aperture.o + kcl_acpi_table.o kcl_page_alloc.o kcl_drm_aperture.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c b/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c new file mode 100644 index 0000000000000..d56b220384800 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/mm/page_alloc.c + * + * Manages the free list, the system allocates free pages here. + * Note that kmalloc() lives in slab.c + * + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * Swap reorganised 29.12.95, Stephen Tweedie + * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999 + * Reshaped it to be a zoned allocator, Ingo Molnar, Red Hat, 1999 + * Discontiguous memory support, Kanoj Sarcar, SGI, Nov 1999 + * Zone balancing, Kanoj Sarcar, SGI, Jan 2000 + * Per cpu hot/cold page lists, bulk allocation, Martin J. Bligh, Sept 2002 + * (lots of bits borrowed from Ingo Molnar & Andrew Morton) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include +#include +#include +#include + +#include +#include +#include +//#include "internal.h" +//#include "shuffle.h" +//#include "page_reporting.h" + +/* Copied from mm/page_allo.c */ +#ifndef HAVE_FS_RECLAIM_ACQUIRE +#ifdef CONFIG_LOCKDEP +static struct lockdep_map __fs_reclaim_map = + STATIC_LOCKDEP_MAP_INIT("fs_reclaim", &__fs_reclaim_map); + +static bool __need_reclaim(gfp_t gfp_mask) +{ + /* no reclaim without waiting on it */ + if (!(gfp_mask & __GFP_DIRECT_RECLAIM)) + return false; + + /* this guy won't enter reclaim */ + if (current->flags & PF_MEMALLOC) + return false; + + if (gfp_mask & __GFP_NOLOCKDEP) + return false; + + return true; +} + +void __fs_reclaim_acquire(void) +{ + lock_map_acquire(&__fs_reclaim_map); +} + +void __fs_reclaim_release(void) +{ + lock_map_release(&__fs_reclaim_map); +} + +void _kcl_fs_reclaim_acquire(gfp_t gfp_mask) +{ + gfp_mask = current_gfp_context(gfp_mask); + + if (__need_reclaim(gfp_mask)) { + if (gfp_mask & __GFP_FS) + __fs_reclaim_acquire(); + +#ifdef CONFIG_MMU_NOTIFIER + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); + lock_map_release(&__mmu_notifier_invalidate_range_start_map); +#endif + + } +} +EXPORT_SYMBOL_GPL(_kcl_fs_reclaim_acquire); + +void _kcl_fs_reclaim_release(gfp_t gfp_mask) +{ + gfp_mask = current_gfp_context(gfp_mask); + + if (__need_reclaim(gfp_mask)) { + if (gfp_mask & __GFP_FS) + __fs_reclaim_release(); + } +} +EXPORT_SYMBOL_GPL(_kcl_fs_reclaim_release); +#endif +#endif /* HAVE_FS_RECLAIM_ACQUIRE */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index c9f88d77262d6..b9e45108b818c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -64,6 +64,7 @@ #include #include #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/drivers/gpu/drm/amd/dkms/m4/fs_reclaim_acquire.m4 b/drivers/gpu/drm/amd/dkms/m4/fs_reclaim_acquire.m4 new file mode 100644 index 0000000000000..be2f5c9928ae2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/fs_reclaim_acquire.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # v4.13-rc4-164-gd92a8cfcb37e +dnl # locking/lockdep: Rework FS_RECLAIM annotation +dnl # +AC_DEFUN([AC_AMDGPU_FS_RECLAIM_ACQUIRE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + fs_reclaim_acquire(0); + ],[ + AC_DEFINE(HAVE_FS_RECLAIM_ACQUIRE, 1, [fs_reclaim_acquire() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a165f396ac171..9969421ffbe14 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -136,6 +136,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK AC_AMDGPU_DEBUGFS_CREATE_FILE_SIZE AC_AMDGPU_DRM_GEM_TTM_VMAP + AC_AMDGPU_FS_RECLAIM_ACQUIRE AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 2964bb26cea9e..aa26d4d279a22 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -13,5 +13,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_sched_mm.h b/include/kcl/kcl_sched_mm.h new file mode 100644 index 0000000000000..3458dc2617c6a --- /dev/null +++ b/include/kcl/kcl_sched_mm.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_SCHED_MM_H +#define _KCL_KCL_SCHED_MM_H + +#include +#include +#include +#include +#include +#include + +#ifndef SHRINK_EMPTY +#define SHRINK_EMPTY (~0UL - 1) +#define SHRINK_STOP (~0UL) +#endif + +#ifndef HAVE_FS_RECLAIM_ACQUIRE +#ifdef CONFIG_LOCKDEP +extern void __fs_reclaim_acquire(void); +extern void __fs_reclaim_release(void); +static inline void fs_reclaim_acquire(gfp_t gfp_mask) { + return _kcl_fs_reclaim_acquire(gfp_mask); +} +static inline void fs_reclaim_release(gfp_t gfp_mask) { + return _kcl_fs_reclaim_release(gfp_mask); +} +#else +static inline void __fs_reclaim_acquire(void) { } +static inline void __fs_reclaim_release(void) { } +static inline void fs_reclaim_acquire(gfp_t gfp_mask) { } +static inline void fs_reclaim_release(gfp_t gfp_mask) { } +#endif +#endif + +#endif From a6c667215ade4aa9239b2c6a9c9c62b8381791a2 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 15 Mar 2021 15:23:24 +0800 Subject: [PATCH 0440/2653] drm/amdkcl: fake memalloc_noreclaim_save() Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/memalloc_noreclaim_save.m4 | 16 ++++++++++++++++ include/kcl/kcl_sched_mm.h | 18 ++++++++++++++++-- 3 files changed, 33 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/memalloc_noreclaim_save.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9969421ffbe14..a370c9600c8d1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -137,6 +137,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DEBUGFS_CREATE_FILE_SIZE AC_AMDGPU_DRM_GEM_TTM_VMAP AC_AMDGPU_FS_RECLAIM_ACQUIRE + AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/memalloc_noreclaim_save.m4 b/drivers/gpu/drm/amd/dkms/m4/memalloc_noreclaim_save.m4 new file mode 100644 index 0000000000000..f9d0ba9a842cf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/memalloc_noreclaim_save.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 4e544bac8267f65a0bf06aed1bde9964da4812ed +dnl # PCI: Add pci_dev_id() helper +dnl # +AC_DEFUN([AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + memalloc_noreclaim_save(); + ], [ + AC_DEFINE(HAVE_MEMALLOC_NORECLAIM_SAVE, 1, + [memalloc_noreclaim_save() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_sched_mm.h b/include/kcl/kcl_sched_mm.h index 3458dc2617c6a..be8915e298c62 100644 --- a/include/kcl/kcl_sched_mm.h +++ b/include/kcl/kcl_sched_mm.h @@ -29,7 +29,21 @@ static inline void __fs_reclaim_acquire(void) { } static inline void __fs_reclaim_release(void) { } static inline void fs_reclaim_acquire(gfp_t gfp_mask) { } static inline void fs_reclaim_release(gfp_t gfp_mask) { } -#endif -#endif +#endif /* CONFIG_LOCKDEP */ +#endif /* HAVE_FS_RECLAIM_ACQUIRE */ + +#ifndef HAVE_MEMALLOC_NORECLAIM_SAVE +static inline unsigned int memalloc_noreclaim_save(void) +{ + unsigned int flags = current->flags & PF_MEMALLOC; + current->flags |= PF_MEMALLOC; + return flags; +} + +static inline void memalloc_noreclaim_restore(unsigned int flags) +{ + current->flags = (current->flags & ~PF_MEMALLOC) | flags; +} +#endif /* HAVE_MEMALLOC_NORECLAIM_SAVE */ #endif From f2c8735f70fc849e86f9898ea9f664d8937e43eb Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 15 Mar 2021 20:10:01 +0800 Subject: [PATCH 0441/2653] drm/amdkcl: fake the macro of __GFP_KSWAPD_RECLAIM Signed-off-by: Shiwu Zhang --- include/kcl/kcl_kernel.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index f93febef548d8..ef5bdee50ee36 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -23,4 +23,9 @@ #define ALIGN_DOWN(x, a) __ALIGN_KERNEL((x) - ((a) - 1), (a)) #endif /* ALIGN_DOWN */ +#ifndef ___GFP_KSWAPD_RECLAIM +#define ___GFP_KSWAPD_RECLAIM 0x00u +#define __GFP_KSWAPD_RECLAIM ((__force gfp_t)___GFP_KSWAPD_RECLAIM) /* kswapd can wake */ +#endif /* ___GFP_KSWAPD_RECLAIM */ + #endif /* AMDKCL_KERNEL_H */ From 9833ed79c43e9d7fb33ea687a852f42c2ed734ca Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Wed, 17 Mar 2021 17:36:05 +0800 Subject: [PATCH 0442/2653] drm/amdkcl: init the ddev->pdev for legacy os This is caused by "Upcast struct drm_device.dev to struct pci_device; replace pdev" v5.11-rc2-514-g36b73b051c41 Otherwise, NULL pointer dereference will be reported for drm_pci_set_busid: [ 55.850413] BUG: kernel NULL pointer dereference, address: 0000000000000038 [ 55.850456] #PF: supervisor read access in kernel mode [ 55.850482] #PF: error_code(0x0000) - not-present page [ 55.850507] PGD 0 P4D 0 [ 55.850524] Oops: 0000 [#1] SMP NOPTI [ 55.850545] CPU: 7 PID: 1687 Comm: Xorg Tainted: G OE 5.8.0-45-generic #51~20.04.1-Ubuntu [ 55.850587] Hardware name: System manufacturer System Product Name/PRIME Z390-A, BIOS 1201 07/29/2019 [ 55.850655] RIP: 0010:drm_pci_set_busid+0x16/0x80 [drm] [ 55.850681] Code: 8b 85 80 01 00 00 eb 86 c3 66 2e 0f 1f 84 00 00 00 00 00 90 0f 1f 44 00 00 55 31 d2 48 89 e5 53 48 8b 87 88 01 00 00 48 89 f3 <44> 8b 40 38 48 8b 40 10 45 89 c1 41 c1 e8 03 0f b6 88 e0 00 00 00 [ 55.850762] RSP: 0018:ffffb768c0fabd20 EFLAGS: 00010246 [ 55.850788] RAX: 0000000000000000 RBX: ffffa0745070a840 RCX: 0000000000000002 [ 55.850820] RDX: 0000000000000000 RSI: ffffa0745070a840 RDI: ffffa0742dbe0010 [ 55.850853] RBP: ffffb768c0fabd28 R08: 0000000000000000 R09: ffffffffc046e5d9 [ 55.850886] R10: 0000000000000000 R11: 0000000000000000 R12: ffffa0742dbe0010 [ 55.850918] R13: ffffa0742d2abe00 R14: ffffa0742dbe00b8 R15: ffffa0745070a840 [ 55.850952] FS: 00007f6673a15a40(0000) GS:ffffa0745ddc0000(0000) knlGS:0000000000000000 [ 55.850989] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 55.851016] CR2: 0000000000000038 CR3: 00000004506da006 CR4: 00000000003606e0 [ 55.851049] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 55.851082] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 55.851114] Call Trace: [ 55.851149] drm_setversion+0x14e/0x190 [drm] [ 55.851188] ? drm_ioctl_permit+0x80/0x80 [drm] [ 55.851227] drm_ioctl_kernel+0xae/0xf0 [drm] [ 55.851266] drm_ioctl+0x234/0x3d0 [drm] [ 55.851302] ? drm_ioctl_permit+0x80/0x80 [drm] [ 55.851449] amdgpu_drm_ioctl+0x4e/0x80 [amdgpu] [ 55.851478] ksys_ioctl+0x9d/0xd0 [ 55.851496] __x64_sys_ioctl+0x1a/0x20 [ 55.851519] do_syscall_64+0x49/0xc0 [ 55.851539] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 55.851565] RIP: 0033:0x7f6673d7550b Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index b5ab8c9afad71..cc03067c1f9ca 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2451,6 +2451,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, goto err_free; #endif + ddev->pdev = pdev; pci_set_drvdata(pdev, ddev); amdgpu_init_debug_options(adev); From 1baab770e959b36be0aa7486804f47d2ccee549c Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 11 Mar 2021 13:11:31 +0800 Subject: [PATCH 0443/2653] drm/amdkcl: add BIT_PER_TYPE macro This patch is caused by 'drm/amdkfd: Fix UBSAN shift-out-of-bounds warning' v5.11-2606-g9f3ada6b3e86 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_bitops.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/kcl/kcl_bitops.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b9e45108b818c..d6fc929d16b12 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -63,6 +63,7 @@ #include #include #include +#include #include #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" diff --git a/include/kcl/kcl_bitops.h b/include/kcl/kcl_bitops.h new file mode 100644 index 0000000000000..f022f59a6a772 --- /dev/null +++ b/include/kcl/kcl_bitops.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_BITOPS_BACKPORT_H +#define AMDKCL_BITOPS_BACKPORT_H + +#include +/* Copied froma include/linux/bitops.h */ +#ifndef BITS_PER_TYPE +#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) +#endif + +#endif From 2cdc601f6470bcfcb6e4637c6cea94b9928c62f8 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 11 Mar 2021 16:14:09 +0800 Subject: [PATCH 0444/2653] drm/amdkcl: change drm_framebuffer field access code to kcl_drm_gem_fb_set_obj This patch is caused by 'drm/amdgpu: Verify bo size can fit framebuffer size on init.' v5.11-2639-g9e429bf5aabb Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 28 +++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 7d73806895a04..c697d32d1e234 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1427,6 +1427,30 @@ static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb return r; } +int amdgpu_display_gem_fb_init(struct drm_device *dev, + struct amdgpu_framebuffer *rfb, + const struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object *obj) +{ + int ret; + kcl_drm_gem_fb_set_obj(&rfb->base, 0, obj); + drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); + + ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); + if (ret) + goto err; + + ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); + if (ret) + goto err; + + return 0; +err: + drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret); + kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); + return ret; +} + static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, struct amdgpu_framebuffer *rfb, struct drm_file *file_priv, @@ -1435,7 +1459,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, { int ret; - rfb->base.obj[0] = obj; + kcl_drm_gem_fb_set_obj(&rfb->base, 0, obj); drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); /* Verify that the modifier is supported. */ if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, @@ -1464,7 +1488,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, return 0; err: drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret); - rfb->base.obj[0] = NULL; + kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); return ret; } From 3c344ef6b2032cb131d8c4dd7e739bb7fd294b5f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 15 Mar 2021 16:58:47 +0800 Subject: [PATCH 0445/2653] drm/amdkcl: fake drm_err macro This patch is caused by 'drm/amdgpu: Verify bo size can fit framebuffer size on init.' v5.11-2639-g9e429bf5aabb Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 19 +++++++++++++++++++ include/kcl/kcl_drm_print.h | 20 ++++++++++++++++---- 2 files changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 0c47443e0f189..b5d9e1a9113a3 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -83,3 +83,22 @@ void drm_dev_dbg(const struct device *dev, int category, } EXPORT_SYMBOL(drm_dev_dbg); #endif + +#if !defined(HAVE_DRM_ERR_MACRO) +void kcl_drm_err(const char *format, ...) +{ + struct va_format vaf; + va_list args; + + va_start(args, format); + vaf.fmt = format; + vaf.va = &args; + + printk(KERN_ERR "[" DRM_NAME ":%ps] *ERROR* %pV", + __builtin_return_address(0), &vaf); + + va_end(args); +} +EXPORT_SYMBOL(kcl_drm_err); + +#endif diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 10ba443b49303..c51497dc79f3e 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -27,6 +27,7 @@ #include #include +#include #if !defined(HAVE_DRM_DRM_PRINT_H) /* Copied from d8187177b0b1 include/drm/drm_print.h */ @@ -102,10 +103,20 @@ void drm_mm_print(const struct drm_mm *mm, struct drm_printer *p) _DRM_PRINTK(_once, NOTICE, fmt, ##__VA_ARGS__) #endif -#ifndef DRM_ERROR -#define DRM_ERROR(fmt, ...) \ - drm_printk(KERN_ERR, DRM_UT_NONE, fmt, ##__VA_ARGS__) -#endif +#ifndef drm_err +#define drm_err(drm, fmt, ...) \ + dev_err((drm)->dev, "[drm] " fmt, ##__VA_ARGS__) + +__printf(1, 2) +void kcl_drm_err(const char *format, ...); + +#undef DRM_ERROR +#define DRM_ERROR(fmt, ...) \ + kcl_drm_err(fmt, ##__VA_ARGS__) + +#else +#define HAVE_DRM_ERR_MACRO +#endif /* drm_err */ #if !defined(DRM_DEV_DEBUG) #define DRM_DEV_DEBUG(dev, fmt, ...) \ @@ -142,4 +153,5 @@ static inline bool drm_debug_enabled(unsigned int category) return unlikely(drm_debug & category); } #endif /* HAVE_DRM_DEBUG_ENABLED */ + #endif From 204c0861682662054a0ec9f8fd4265318475f3c2 Mon Sep 17 00:00:00 2001 From: charles sun Date: Sun, 14 Mar 2021 19:19:10 +0800 Subject: [PATCH 0446/2653] the dcn301_calculate_wm_and_dl() calculation exposed a issue - switch to dcn30 version for now. still need to follow up with dcn301 watermark updates version. Signed-off-by: Charles Sun Reviewed-by: Nikola Cornij Acked-by: Charles Sun --- .../gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index eeb3794dcd09f..dd77e91df3493 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -1395,7 +1395,7 @@ static struct resource_funcs dcn301_res_pool_funcs = { .link_enc_create = dcn301_link_encoder_create, .panel_cntl_create = dcn301_panel_cntl_create, .validate_bandwidth = dcn30_validate_bandwidth, - .calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg, + .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, From aac295bd10f840a6f6572a30757280a8d2561d1d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 17 Mar 2021 15:07:31 +0800 Subject: [PATCH 0447/2653] drm/amdkcl: cleanup HAVE_DRM_MM_INSERT_MODE Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/ttm/backport/backport.h | 1 + drivers/gpu/drm/ttm/ttm_range_manager.c | 7 --- include/kcl/backport/kcl_drm_mm_backport.h | 6 +- include/kcl/kcl_drm_mm.h | 68 ++++++++++++++++++++++ 4 files changed, 74 insertions(+), 8 deletions(-) create mode 100644 include/kcl/kcl_drm_mm.h diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index aa26d4d279a22..6d784a77a1906 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/ttm/ttm_range_manager.c b/drivers/gpu/drm/ttm/ttm_range_manager.c index 7b786bab51c1c..db854b581d834 100644 --- a/drivers/gpu/drm/ttm/ttm_range_manager.c +++ b/drivers/gpu/drm/ttm/ttm_range_manager.c @@ -77,16 +77,9 @@ static int ttm_range_man_alloc(struct ttm_resource_manager *man, if (!node) return -ENOMEM; -#ifndef HAVE_DRM_MM_INSERT_MODE - if (place->flags & TTM_PL_FLAG_TOPDOWN) { - sflags = DRM_MM_SEARCH_BELOW; - aflags = DRM_MM_CREATE_TOP; - } -#else mode = DRM_MM_INSERT_BEST; if (place->flags & TTM_PL_FLAG_TOPDOWN) mode = DRM_MM_INSERT_HIGH; -#endif ttm_resource_init(bo, place, &node->base); diff --git a/include/kcl/backport/kcl_drm_mm_backport.h b/include/kcl/backport/kcl_drm_mm_backport.h index 8c20d53ed7f4f..1a2614d47ab59 100644 --- a/include/kcl/backport/kcl_drm_mm_backport.h +++ b/include/kcl/backport/kcl_drm_mm_backport.h @@ -8,7 +8,7 @@ * with rbtrees */ -#include +#include #ifndef HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS static inline int _kcl_drm_mm_insert_node(struct drm_mm *mm, @@ -20,4 +20,8 @@ static inline int _kcl_drm_mm_insert_node(struct drm_mm *mm, #define drm_mm_insert_node _kcl_drm_mm_insert_node #endif /* HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS */ +#ifndef HAVE_DRM_MM_INSERT_MODE +#define drm_mm_insert_node_in_range _kcl_drm_mm_insert_node_in_range +#endif + #endif /* AMDKCL_DRM_MM_H */ diff --git a/include/kcl/kcl_drm_mm.h b/include/kcl/kcl_drm_mm.h new file mode 100644 index 0000000000000..5387e6c05bc65 --- /dev/null +++ b/include/kcl/kcl_drm_mm.h @@ -0,0 +1,68 @@ +/************************************************************************** + * + * Copyright 2006-2008 Tungsten Graphics, Inc., Cedar Park, TX. USA. + * Copyright 2016 Intel Corporation + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * + **************************************************************************/ +/* + * Authors: + * Thomas Hellstrom + */ +#ifndef _KCL_KCL_DRM_MM_H_H_ +#define _KCL_KCL_DRM_MM_H_H_ +#include + +#ifndef HAVE_DRM_MM_INSERT_MODE +/* Copied from 4e64e5539d15 include/drm/drm_mm.h */ +enum drm_mm_insert_mode { + DRM_MM_INSERT_BEST = 0, + DRM_MM_INSERT_LOW, + DRM_MM_INSERT_HIGH, + DRM_MM_INSERT_EVICT, +}; + +static inline +int _kcl_drm_mm_insert_node_in_range(struct drm_mm * const mm, + struct drm_mm_node * const node, + u64 size, u64 alignment, + unsigned long color, + u64 range_start, u64 range_end, + enum drm_mm_insert_mode mode) +{ + enum drm_mm_search_flags sflags = DRM_MM_SEARCH_BEST; + enum drm_mm_allocator_flags aflags = DRM_MM_CREATE_DEFAULT; + + if (mode == DRM_MM_INSERT_HIGH) { + sflags = DRM_MM_SEARCH_BELOW; + aflags = DRM_MM_CREATE_TOP; + } + + return drm_mm_insert_node_in_range_generic(mm, node, size, + alignment, color, range_start, range_end, + sflags, aflags); +} +#endif /* HAVE_DRM_MM_INSERT_MODE */ + +#endif From 30125654d9dedc39ac09c52b67a9101461f3f9bc Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Thu, 25 Mar 2021 16:03:17 +0800 Subject: [PATCH 0448/2653] drm/amdkcl: add Centos7.3, 7.4 and 7.6 phantom support clear the compiling errors like lacking header files Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 5 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 4 ++++ drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c | 1 - drivers/gpu/drm/amd/backport/backport.h | 2 +- drivers/gpu/drm/ttm/backport/backport.h | 1 + drivers/gpu/drm/ttm/ttm_tt.c | 4 ++++ include/kcl/backport/kcl_drm_prime.h | 4 ++++ include/kcl/backport/kcl_ttm_tt_backport.h | 12 ------------ include/kcl/kcl_drm_hdcp.h | 7 +++++++ include/kcl/kcl_sched_mm.h | 1 - 11 files changed, 27 insertions(+), 22 deletions(-) delete mode 100644 include/kcl/backport/kcl_ttm_tt_backport.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index c697d32d1e234..7fd927cadca3b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -506,9 +506,8 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc, goto cleanup; } unpin: - if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) { - DRM_ERROR("failed to unpin new abo in error path\n"); - } + amdgpu_bo_unpin(new_abo); + unreserve: amdgpu_bo_unreserve(new_abo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index cc03067c1f9ca..7a992fc12e4f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2238,7 +2238,7 @@ static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { {0x67FF, 0xF7, CHIP_POLARIS10}, }; -static const struct drm_driver amdgpu_kms_driver; +static struct drm_driver amdgpu_kms_driver; static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) { @@ -2434,11 +2434,11 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, ddev->driver_features &= ~DRIVER_ATOMIC; #else /* warn the user if they mix atomic and non-atomic capable GPUs */ - if ((kms_driver.driver_features & DRIVER_ATOMIC) && !supports_atomic) + if ((amdgpu_kms_driver.driver_features & DRIVER_ATOMIC) && !supports_atomic) DRM_ERROR("Mixing atomic and non-atomic capable GPUs!\n"); /* support atomic early so the atomic debugfs stuff gets created */ if (supports_atomic) - kms_driver.driver_features |= DRIVER_ATOMIC; + amdgpu_kms_driver.driver_features |= DRIVER_ATOMIC; #endif kcl_pci_create_measure_file(pdev); @@ -3109,7 +3109,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW) }; -static const struct drm_driver amdgpu_kms_driver = { +static struct drm_driver amdgpu_kms_driver = { .driver_features = 0 #ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 13f0cdeb59c46..a5225e6f41cf1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -64,7 +64,11 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev) adev->mode_info.num_crtc = 1; adev->enable_virtual_display = true; } +#ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES ddev->driver_features &= ~DRIVER_ATOMIC; +#else + ddev->driver->driver_features &= ~DRIVER_ATOMIC; +#endif adev->cg_flags = 0; adev->pg_flags = 0; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c b/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c index d56b220384800..4b6735959d945 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c @@ -62,7 +62,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index d6fc929d16b12..15f2db83d31cd 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -36,7 +37,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 6d784a77a1906..f8fb0af23aa40 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -15,5 +15,6 @@ #include #include #include +#include #endif diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index dd5aa65e080e3..8772617d3f25f 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -214,10 +214,14 @@ int ttm_sg_tt_init(struct ttm_tt *ttm, struct ttm_buffer_object *bo, ttm_tt_init_fields(ttm, bo, page_flags, caching, 0); +#ifndef HAVE_TTM_SG_TT_INIT + ret = ttm_dma_tt_alloc_page_directory(ttm); +#else if (page_flags & TTM_TT_FLAG_EXTERNAL) ret = ttm_sg_tt_alloc_page_directory(ttm); else ret = ttm_dma_tt_alloc_page_directory(ttm); +#endif if (ret) { pr_err("Failed allocating page table\n"); return -ENOMEM; diff --git a/include/kcl/backport/kcl_drm_prime.h b/include/kcl/backport/kcl_drm_prime.h index 1c3895f60823d..33187c1891d71 100644 --- a/include/kcl/backport/kcl_drm_prime.h +++ b/include/kcl/backport/kcl_drm_prime.h @@ -33,7 +33,11 @@ #ifndef _KCL_BACKPORT_KCL__DRM_PRIME_H__H_ #define _KCL_BACKPORT_KCL__DRM_PRIME_H__H_ +#ifdef HAVE_DRM_DRMP_H +#include +#else #include +#endif #ifndef HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS static inline diff --git a/include/kcl/backport/kcl_ttm_tt_backport.h b/include/kcl/backport/kcl_ttm_tt_backport.h deleted file mode 100644 index 3641f2408b0f3..0000000000000 --- a/include/kcl/backport/kcl_ttm_tt_backport.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef AMDKCL_BACKPORT_KCL_TTM_TT_BACKPORT_H -#define AMDKCL_BACKPORT_KCL_TTM_TT_BACKPORT_H - -#include -#include - -#ifndef HAVE_TTM_SG_TT_INIT -#define amdttm_sg_tt_init ttm_dma_tt_init -#endif - -#endif diff --git a/include/kcl/kcl_drm_hdcp.h b/include/kcl/kcl_drm_hdcp.h index ba77fb5c0973a..b3f6318e1f652 100644 --- a/include/kcl/kcl_drm_hdcp.h +++ b/include/kcl/kcl_drm_hdcp.h @@ -45,6 +45,13 @@ #define HDCP_STREAM_TYPE0 0x00 #define HDCP_STREAM_TYPE1 0x01 +/* introduced in v4.15-rc4-1351-g495eb7f877ab + * drm: Add some HDCP related #defines + */ +#ifndef DRM_HDCP_KSV_LEN +#define DRM_HDCP_KSV_LEN 5 +#endif + /* HDCP2.2 Msg IDs */ #define HDCP_2_2_NULL_MSG 1 #define HDCP_2_2_AKE_INIT 2 diff --git a/include/kcl/kcl_sched_mm.h b/include/kcl/kcl_sched_mm.h index be8915e298c62..31e59278e4b5d 100644 --- a/include/kcl/kcl_sched_mm.h +++ b/include/kcl/kcl_sched_mm.h @@ -7,7 +7,6 @@ #include #include #include -#include #ifndef SHRINK_EMPTY #define SHRINK_EMPTY (~0UL - 1) From e606f00f04e802d5097eb8c13aa5c417c3c3b62a Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 22 Mar 2021 17:08:28 +0800 Subject: [PATCH 0449/2653] drm/amdkcl: update the config.h Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/dkms/config/config.h | 829 +++++++++++++++++++++++ 1 file changed, 829 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5c604c53ed971..1159d273a7753 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1,18 +1,317 @@ /* config/config.h. Generated from config.h.in by configure. */ /* config/config.h.in. Generated from configure.ac by autoheader. */ +/* whether invalidate_range_start() wants 2 args */ +#define HAVE_2ARGS_INVALIDATE_RANGE_START 1 + +/* whether invalidate_range_start() wants 5 args */ +/* #undef HAVE_5ARGS_INVALIDATE_RANGE_START */ + +/* whether access_ok(x, x) is available */ +#define HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS 1 + +/* acpi_put_table() is available */ +/* #undef HAVE_ACPI_PUT_TABLE */ + +/* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ +#define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 + /* *FLAGS_.o support to take the path relative to $(obj) */ #define HAVE_AMDKCL_FLAGS_TAKE_PATH 1 +/* hmm support is enabled */ +#define HAVE_AMDKCL_HMM_MIRROR_ENABLED 1 + +/* amd_iommu_invalidate_ctx take arg type of pasid as u32 */ +#define HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 1 + +/* amd_iommu_pc_supported() is available */ +/* #undef HAVE_AMD_IOMMU_PC_SUPPORTED */ + +/* arch_io_{reserve/free}_memtype_wc() are available */ +#define HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC 1 + /* Define to 1 if you have the header file. */ #define HAVE_ASM_FPU_API_H 1 /* Define to 1 if you have the header file. */ #define HAVE_ASM_SET_MEMORY_H 1 +/* backlight_device_set_brightness() is available */ +#define HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS 1 + +/* whether CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL is defined */ +#define HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL 1 + +/* whether CHUNK_ID_SYNOBJ_IN_OUT is defined */ +#define HAVE_CHUNK_ID_SYNOBJ_IN_OUT 1 + +/* compat_ptr_ioctl() is available */ +#define HAVE_COMPAT_PTR_IOCTL 1 + +/* debugfs_create_file_size() is available */ +#define HAVE_DEBUGFS_CREATE_FILE_SIZE 1 + +/* devcgroup_check_permission() is available */ +#define HAVE_DEVCGROUP_CHECK_PERMISSION 1 + +/* devm_memremap_pages() wants struct dev_pagemap */ +#define HAVE_DEVM_MEMREMAP_PAGES_DEV_PAGEMAP 1 + +/* devm_memremap_pages() wants p,p,p,p interface */ +/* #undef HAVE_DEVM_MEMREMAP_PAGES_P_P_P_P */ + +/* there is 'range' field within dev_pagemap structure */ +#define HAVE_DEV_PAGEMAP_RANGE 1 + +/* dev_pm_set_driver_flags() is available */ +#define HAVE_DEV_PM_SET_DRIVER_FLAGS 1 + +/* dma_buf dynamic_mapping is available */ +/* #undef HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING */ + +/* whether dma_fence_get_stub exits */ +#define HAVE_DMA_FENCE_GET_STUB 1 + +/* dma_fence_set_error() is available */ +#define HAVE_DMA_FENCE_SET_ERROR 1 + +/* dma_map_resource() is enabled */ +#define HAVE_DMA_MAP_RESOURCE 1 + +/* dma_map_sgtable() is enabled */ +#define HAVE_DMA_MAP_SGTABLE 1 + +/* dma_resv->seq is available */ +#define HAVE_DMA_RESV_SEQ 1 + +/* dma_resv->seq is seqcount_ww_mutex_t */ +#define HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T 1 + +/* down_read_killable() is available */ +#define HAVE_DOWN_READ_KILLABLE 1 + +/* down_write_killable() is available */ +#define HAVE_DOWN_WRITE_KILLABLE 1 + +/* drm_dp_mst_connector_early_unregister() is available */ +#define HAVE_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 + +/* drm_dp_mst_connector_late_register() is available */ +#define HAVE_DP_MST_CONNECTOR_LATE_REGISTER 1 + +/* drm_accurate_vblank_count() is available */ +/* #undef HAVE_DRM_ACCURATE_VBLANK_COUNT */ + +/* DRM_AMDGPU_FENCE_TO_HANDLE is defined */ +#define HAVE_DRM_AMDGPU_FENCE_TO_HANDLE 1 + /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_AMDGPU_PCIID_H */ +/* drm_atomic_get_old_crtc_state() and drm_atomic_get_new_crtc_state() are + available */ +#define HAVE_DRM_ATOMIC_GET_CRTC_STATE 1 + +/* drm_atomic_get_new_plane_state() is available */ +#define HAVE_DRM_ATOMIC_GET_NEW_PLANE_STATE 1 + +/* drm_atomic_helper_calc_timestamping_constants() is available */ +#define HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS 1 + +/* drm_atomic_helper_check_plane_state() is available */ +#define HAVE_DRM_ATOMIC_HELPER_CHECK_PLANE_STATE 1 + +/* drm_atomic_helper_shutdown() is available */ +#define HAVE_DRM_ATOMIC_HELPER_SHUTDOWN 1 + +/* drm_atomic_helper_wait_for_flip_done() is available */ +#define HAVE_DRM_ATOMIC_HELPER_WAIT_FOR_FLIP_DONE 1 + +/* {drm_atomic_helper_crtc_set_property, drm_atomic_helper_plane_set_property, + drm_atomic_helper_connector_set_property, drm_atomic_helper_connector_dpms} + is available */ +/* #undef HAVE_DRM_ATOMIC_HELPER_XXX_SET_PROPERTY */ + +/* drm_atomic_nonblocking_commit() is available */ +#define HAVE_DRM_ATOMIC_NONBLOCKING_COMMIT 1 + +/* drm_atomic_plane_disabling() wants drm_plane_state * arg */ +#define HAVE_DRM_ATOMIC_PLANE_DISABLING_DRM_PLANE_STATE 1 + +/* drm_atomic_private_obj_init() is available */ +#define HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT 1 + +/* drm_atomic_private_obj_init() has p,p,p,p interface */ +#define HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT_P_P_P_P 1 + +/* whether struct drm_atomic_state have async_update */ +#define HAVE_DRM_ATOMIC_STATE_ASYNC_UPDATE 1 + +/* drm_atomic_state_put() is available */ +#define HAVE_DRM_ATOMIC_STATE_PUT 1 + +/* drm_color_lut_size() is available */ +#define HAVE_DRM_COLOR_LUT_SIZE 1 + +/* drm_connector_for_each_possible_encoder() wants 2 arguments */ +#define HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS 1 + +/* struct drm_connector_funcs has register members */ +#define HAVE_DRM_CONNECTOR_FUNCS_REGISTER 1 + +/* atomic_best_encoder take 2nd arg type of state as struct drm_atomic_state + */ +#define HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_BEST_ENCODER_ARG_DRM_ATOMIC_STATE 1 + +/* drm_connector_helper_funcs->atomic_check() wants struct drm_atomic_state + arg */ +#define HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE 1 + +/* drm_connector_init_with_ddc() is available */ +#define HAVE_DRM_CONNECTOR_INIT_WITH_DDC 1 + +/* drm_connector_list_iter_begin() is available */ +#define HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN 1 + +/* connector property "max bpc" is available */ +#define HAVE_DRM_CONNECTOR_PROPERTY_MAX_BPC 1 + +/* drm_connector_put() is available */ +#define HAVE_DRM_CONNECTOR_PUT 1 + +/* connector reference counting is available */ +#define HAVE_DRM_CONNECTOR_REFERENCE_COUNTING_SUPPORTED 1 + +/* struct drm_connector_state has hdcp_content_type member */ +#define HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE 1 + +/* drm_connector_unreference() is available */ +/* #undef HAVE_DRM_CONNECTOR_UNREFERENCE */ + +/* drm_connector_xxx() drop _mode_ */ +#define HAVE_DRM_CONNECTOR_XXX_DROP_MODE 1 + +/* ddrm_atomic_stat has __drm_crtcs_state */ +/* #undef HAVE_DRM_CRTCS_STATE_MEMBER */ + +/* drm_crtc_accurate_vblank_count() is available */ +#define HAVE_DRM_CRTC_ACCURATE_VBLANK_COUNT 1 + +/* drm_crtc_enable_color_mgmt() is available */ +#define HAVE_DRM_CRTC_ENABLE_COLOR_MGMT 1 + +/* drm_crtc_from_index() is available */ +#define HAVE_DRM_CRTC_FROM_INDEX 1 + +/* drm_crtc_helper_funcs->atomic_check() wants struct drm_atomic_state arg */ +#define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE 1 + +/* drm_crtc_init_with_planes() wants name */ +#define HAVE_DRM_CRTC_INIT_WITH_PLANES_VALID_WITH_NAME 1 + +/* drm_debug_enabled() is available */ +#define HAVE_DRM_DEBUG_ENABLED 1 + +/* dev_device->driver_features is available */ +#define HAVE_DRM_DEVICE_DRIVER_FEATURES 1 + +/* drm_device->filelist_mutex is available */ +#define HAVE_DRM_DEVICE_FILELIST_MUTEX 1 + +/* drm_device->open_count is int */ +/* #undef HAVE_DRM_DEVICE_OPEN_COUNT_INT */ + +/* drm_dev_dbg() is available */ +#define HAVE_DRM_DEV_DBG 1 + +/* drm_dev_put() is available */ +#define HAVE_DRM_DEV_PUT 1 + +/* drm_dev_unplug() is available */ +#define HAVE_DRM_DEV_UNPLUG 1 + +/* display_info->hdmi.scdc.scrambling are available */ +#define HAVE_DRM_DISPLAY_INFO_HDMI_SCDC_SCRAMBLING 1 + +/* display_info->max_tmds_clock is available */ +#define HAVE_DRM_DISPLAY_INFO_MAX_TMDS_CLOCK 1 + +/* struct drm_display_info has monitor_range member */ +#define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 + +/* drm_dp_atomic_find_vcpi_slots() is available */ +#define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 + +/* drm_dp_atomic_find_vcpi_slots() wants 5args */ +#define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS 1 + +/* drm_dp_calc_pbn_mode() wants 3args */ +#define HAVE_DRM_DP_CALC_PBN_MODE_3ARGS 1 + +/* drm_dp_cec* correlation functions are available */ +#define HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS 1 + +/* drm_dp_cec_register_connector() wants p,p interface */ +#define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 + +/* drm_dp_mst_add_affected_dsc_crtcs() is available */ +#define HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS 1 + +/* drm_dp_mst_allocate_vcpi() has p,p,i,i interface */ +#define HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I 1 + +/* drm_dp_mst_atomic_check() is available */ +#define HAVE_DRM_DP_MST_ATOMIC_CHECK 1 + +/* drm_dp_mst_atomic_enable_dsc() is available */ +#define HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC 1 + +/* drm_dp_mst_detect_port() wants p,p,p,p args */ +#define HAVE_DRM_DP_MST_DETECT_PORT_PPPP 1 + +/* drm_dp_mst_dsc_aux_for_port() is available */ +#define HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT 1 + +/* drm_dp_mst_{get,put}_port_malloc() is available */ +#define HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC 1 + +/* struct drm_dp_mst_topology_cbs->destroy_connector is available */ +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR */ + +/* struct drm_dp_mst_topology_cbs has hotplug member */ +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG */ + +/* struct drm_dp_mst_topology_cbs->register_connector is available */ +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR */ + +/* drm_dp_mst_topology_mgr_init() wants drm_device arg */ +#define HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_DRM_DEV 1 + +/* drm_dp_mst_topology_mgr_resume() wants 2 args */ +#define HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS 1 + +/* drm_dp_send_real_edid_checksum() is available */ +#define HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM 1 + +/* drm_dp_start_crc() is available */ +#define HAVE_DRM_DP_START_CRC 1 + +/* drm_driver->gem_prime_res_obj() is available */ +/* #undef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ */ + +/* drm_driver->get_scanout_position() return bool */ +/* #undef HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL */ + +/* drm_driver->get_vblank_timestamp() return bool */ +/* #undef HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_RETURN_BOOL */ + +/* drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg */ +/* #undef HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG */ + +/* drm_driver->release() is available */ +#define HAVE_DRM_DRIVER_RELEASE 1 + /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRMP_H */ @@ -50,6 +349,9 @@ */ #define HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_GEM_TTM_HELPER_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_HDCP_H 1 @@ -77,12 +379,290 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_VBLANK_H 1 +/* drm_driver_feature DRIVER_IRQ_SHARED is available */ +/* #undef HAVE_DRM_DRV_DRIVER_IRQ_SHARED */ + +/* drm_driver_feature DRIVER_PRIME is available */ +/* #undef HAVE_DRM_DRV_DRIVER_PRIME */ + +/* drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available */ +#define HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE 1 + +/* drm_gem_prime_export() with p,i arg is available */ +#define HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI 1 + +/* drm_edid_to_eld() are available */ +/* #undef HAVE_DRM_EDID_TO_ELD */ + +/* drm_encoder_find() wants file_priv */ +#define HAVE_DRM_ENCODER_FIND_VALID_WITH_FILE 1 + +/* drm_fb_helper_single_add_all_connectors() && + drm_fb_helper_remove_one_connector() are symbol */ +/* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ + +/* drm_fb_helper_fill_info() is available */ +#define HAVE_DRM_FB_HELPER_FILL_INFO 1 + +/* drm_fb_helper_init() has 2 args */ +#define HAVE_DRM_FB_HELPER_INIT_2ARGS 1 + +/* drm_fb_helper_init() has 3 args */ +/* #undef HAVE_DRM_FB_HELPER_INIT_3ARGS */ + +/* whether drm_fb_helper_lastclose() is available */ +#define HAVE_DRM_FB_HELPER_LASTCLOSE 1 + +/* drm_fb_helper_remove_conflicting_pci_framebuffers() is available */ +#define HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS 1 + +/* drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args */ +/* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP */ + +/* drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args */ +#define HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP 1 + +/* drm_fb_helper_set_suspend_unlocked() is available */ +#define HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED 1 + +/* drm_format_info.block_w and rm_format_info.block_h is available */ +#define HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED 1 + +/* whether struct drm_framebuffer have format */ +#define HAVE_DRM_FRAMEBUFFER_FORMAT 1 + +/* drm_gem_map_attach() wants 2 arguments */ +/* #undef HAVE_DRM_GEM_MAP_ATTACH_2ARGS */ + +/* drm_gem_object_lookup() wants 2 args */ +#define HAVE_DRM_GEM_OBJECT_LOOKUP_2ARGS 1 + +/* drm_gem_object_put_locked() is available */ +#define HAVE_DRM_GEM_OBJECT_PUT_LOCKED 1 + +/* drm_gem_object_put_unlocked() is available */ +/* #undef HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED */ + +/* ttm_buffer_object->base is available */ +#define HAVE_DRM_GEM_OBJECT_RESV 1 + +/* drm_gem_ttm_vmap() is available */ +#define HAVE_DRM_GEM_TTM_VMAP 1 + +/* drm_get_format_info() is available */ +#define HAVE_DRM_GET_FORMAT_INFO 1 + +/* drm_get_format_name() has i,p interface */ +#define HAVE_DRM_GET_FORMAT_NAME_I_P 1 + +/* drm_hdcp_update_content_protection is available */ +#define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 + +/* drm_hdmi_avi_infoframe_from_display_mode() has p,p,b interface */ +/* #undef HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B */ + +/* drm_hdmi_avi_infoframe_from_display_mode() has p,p,p interface */ +#define HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P 1 + +/* drm_hdmi_vendor_infoframe_from_display_mode() has p,p,p interface */ +#define HAVE_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE_P_P_P 1 + +/* drm_helper_force_disable_all() is available */ +#define HAVE_DRM_HELPER_FORCE_DISABLE_ALL 1 + +/* drm_helper_mode_fill_fb_struct() wants dev arg */ +#define HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV 1 + +/* drm_is_current_master() is available */ +#define HAVE_DRM_IS_CURRENT_MASTER 1 + +/* drm_kms_helper_is_poll_worker() is available */ +#define HAVE_DRM_KMS_HELPER_IS_POLL_WORKER 1 + +/* whether drm_mm_insert_mode is available */ +#define HAVE_DRM_MM_INSERT_MODE 1 + +/* drm_mm_insert_node has three parameters */ +#define HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS 1 + +/* drm_mode_config->dp_subconnector_property is available */ +#define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 + +/* drm_mode_config_funcs->atomic_state_alloc() is available */ +#define HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC 1 + +/* drm_mode_config->helper_private is available */ +#define HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE 1 + +/* drm_mode_get_hv_timing is available */ +#define HAVE_DRM_MODE_GET_HV_TIMING 1 + +/* drm_mode_is_420_xxx() is available */ +#define HAVE_DRM_MODE_IS_420_XXX 1 + +/* enum drm_mode_subconnector is available */ +/* #undef HAVE_DRM_MODE_SUBCONNECTOR_ENUM */ + +/* drm_need_swiotlb() is availablea */ +#define HAVE_DRM_NEED_SWIOTLB 1 + +/* drm atomic nonblocking commit support is available */ +#define HAVE_DRM_NONBLOCKING_COMMIT_SUPPORT 1 + +/* drm_plane_helper_check_state is available */ +/* #undef HAVE_DRM_PLANE_HELPER_CHECK_STATE */ + +/* drm_plane_mask is available */ +#define HAVE_DRM_PLANE_MASK 1 + +/* drm_plane_create_alpha_property, drm_plane_create_blend_mode_property are + available */ +#define HAVE_DRM_PLANE_PROPERTY_ALPHA_BLEND_MODE 1 + +/* drm_plane_create_color_properties is available */ +#define HAVE_DRM_PLANE_PROPERTY_COLOR_ENCODING_RANGE 1 + +/* drm_plane_create_rotation_property is available */ +#define HAVE_DRM_PLANE_PROPERTY_ROTATION 1 + +/* drm_prime_pages_to_sg() wants 3 arguments */ +#define HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS 1 + +/* drm_prime_sg_to_dma_addr_array() is available */ +#define HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY 1 + +/* drm_printer->prefix is available */ +#define HAVE_DRM_PRINTER_PREFIX 1 + +/* drm_syncobj_fence_get() is available */ +/* #undef HAVE_DRM_SYNCOBJ_FENCE_GET */ + +/* drm_syncobj_find_fence() is available */ +#define HAVE_DRM_SYNCOBJ_FIND_FENCE 1 + +/* whether drm_syncobj_find_fence() wants 3 args */ +/* #undef HAVE_DRM_SYNCOBJ_FIND_FENCE_3ARGS */ + +/* whether drm_syncobj_find_fence() wants 4 args */ +/* #undef HAVE_DRM_SYNCOBJ_FIND_FENCE_4ARGS */ + +/* whether drm_syncobj_find_fence() wants 5 args */ +#define HAVE_DRM_SYNCOBJ_FIND_FENCE_5ARGS 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 +/* drm_universal_plane_init() wants 7 args */ +/* #undef HAVE_DRM_UNIVERSAL_PLANE_INIT_7ARGS */ + +/* drm_universal_plane_init() wants 8 args */ +/* #undef HAVE_DRM_UNIVERSAL_PLANE_INIT_8ARGS */ + +/* drm_universal_plane_init() wants 9 args */ +#define HAVE_DRM_UNIVERSAL_PLANE_INIT_9ARGS 1 + +/* drm_vma_node_verify_access() 2nd argument is drm_file */ +#define HAVE_DRM_VMA_NODE_VERIFY_ACCESS_HAS_DRM_FILE 1 + +/* Variable refresh rate(vrr) is supported */ +#define HAVE_DRM_VRR_SUPPORTED 1 + +/* fault_flag_allow_retry_first() is available */ +#define HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST 1 + +/* drm_mode_object->free_cb is available */ +/* #undef HAVE_FREE_CB_IN_STRUCT_DRM_MODE_OBJECT */ + +/* fs_reclaim_acquire() is available */ +#define HAVE_FS_RECLAIM_ACQUIRE 1 + +/* drm_driver->gem_free_object_unlocked() is available */ +/* #undef HAVE_GEM_FREE_OBJECT_UNLOCKED_IN_DRM_DRIVER */ + +/* get_user_pages() wants 6 args */ +/* #undef HAVE_GET_USER_PAGES_6ARGS */ + +/* get_user_pages() wants gup_flags parameter */ +#define HAVE_GET_USER_PAGES_GUP_FLAGS 1 + +/* get_user_pages_remote() wants gup_flags parameter */ +/* #undef HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS */ + +/* get_user_pages_remote() is introduced with initial prototype */ +/* #undef HAVE_GET_USER_PAGES_REMOTE_INTRODUCED */ + +/* get_user_pages_remote() wants locked parameter */ +/* #undef HAVE_GET_USER_PAGES_REMOTE_LOCKED */ + +/* get_user_pages_remote() remove task_struct pointer */ +#define HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT 1 + +/* drm_connector_hdr_sink_metadata() is available */ +#define HAVE_HDR_SINK_METADATA 1 + +/* hmm remove the customizable pfn format */ +#define HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT 1 + +/* hmm_range_fault() wants 1 arg */ +#define HAVE_HMM_RANGE_FAULT_1ARG 1 + +/* struct i2c_lock_operations is defined */ +#define HAVE_I2C_LOCK_OPERATIONS_STRUCT 1 + +/* i2c_new_client_device() is enabled */ +#define HAVE_I2C_NEW_CLIENT_DEVICE 1 + +/* idr_remove return void pointer */ +#define HAVE_IDR_REMOVE_RETURN_VOID_POINTER 1 + +/* in_compat_syscall is defined */ +#define HAVE_IN_COMPAT_SYSCALL 1 + +/* jiffies64_to_msecs() is available */ +#define HAVE_JIFFIES64_TO_MSECS 1 + /* kallsyms_lookup_name is available */ /* #undef HAVE_KALLSYMS_LOOKUP_NAME */ +/* kref_read() function is available */ +#define HAVE_KREF_READ 1 + +/* ksys_sync_helper() is available */ +#define HAVE_KSYS_SYNC_HELPER 1 + +/* kthread_{park/unpark/parkme/should_park}() is available */ +#define HAVE_KTHREAD_PARK_XX 1 + +/* kthread_{use,unuse}_mm() is available */ +#define HAVE_KTHREAD_USE_MM 1 + +/* ktime_get_boottime_ns() is available */ +#define HAVE_KTIME_GET_BOOTTIME_NS 1 + +/* ktime_get_mono_fast_ns is available */ +#define HAVE_KTIME_GET_MONO_FAST_NS 1 + +/* ktime_get_ns is available */ +#define HAVE_KTIME_GET_NS 1 + +/* ktime_get_raw_ns is available */ +#define HAVE_KTIME_GET_RAW_NS 1 + +/* ktime_get_real_seconds() is available */ +#define HAVE_KTIME_GET_REAL_SECONDS 1 + +/* kvcalloc() is available */ +#define HAVE_KVCALLOC 1 + +/* kvfree() is available */ +#define HAVE_KVFREE 1 + +/* kvmalloc_array() is available */ +#define HAVE_KVMALLOC_ARRAY 1 + +/* kv[mz]alloc() are available */ +#define HAVE_KVZALLOC_KVMALLOC 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_BITS_H 1 @@ -92,12 +672,18 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_LINUX_DMA_ATTRS_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_BUF_MAP_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_FENCE_H 1 /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_RESV_H 1 +/* Define to 1 if you have the header file. */ +/* #undef HAVE_LINUX_FENCE_ARRAY_H */ + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_IO_64_NONATOMIC_LO_HI_H 1 @@ -125,9 +711,252 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_SCHED_TASK_H 1 +/* list_bulk_move_tail() is available */ +#define HAVE_LIST_BULK_MOVE_TAIL 1 + +/* list_is_first() is available */ +#define HAVE_LIST_IS_FIRST 1 + +/* list_rotate_to_front() is available */ +#define HAVE_LIST_ROTATE_TO_FRONT 1 + +/* memalloc_nofs_{save,restore}() are available */ +#define HAVE_MEMALLOC_NOFS_SAVE 1 + +/* memalloc_noreclaim_save() is available */ +#define HAVE_MEMALLOC_NORECLAIM_SAVE 1 + +/* mem_encrypt_active() is available */ +#define HAVE_MEM_ENCRYPT_ACTIVE 1 + +/* mmgrab() is available */ +#define HAVE_MMGRAB 1 + +/* mmu_notifier_call_srcu() is available */ +/* #undef HAVE_MMU_NOTIFIER_CALL_SRCU */ + +/* mmu_notifier_put() is available */ +#define HAVE_MMU_NOTIFIER_PUT 1 + +/* mmu_notifier_range_blockable() is available */ +#define HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE 1 + +/* mmu_notifier_synchronize() is available */ +#define HAVE_MMU_NOTIFIER_SYNCHRONIZE 1 + +/* mm_access() is available */ +#define HAVE_MM_ACCESS 1 + +/* release_pages() wants 2 args */ +#define HAVE_MM_RELEASE_PAGES_2ARGS 1 + +/* num_u32_u32 is available */ +#define HAVE_MUL_U32_U32 1 + +/* pcie_bandwidth_available() is available */ +#define HAVE_PCIE_BANDWIDTH_AVAILABLE 1 + +/* pci_enable_atomic_ops_to_root() exist */ +#define HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT 1 + +/* pcie_get_speed_cap() and pcie_get_width_cap() exist */ +#define HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP 1 + +/* PCI driver handles extended tags */ +#define HAVE_PCI_CONFIGURE_EXTENDED_TAGS 1 + +/* pci_dev_id() is available */ +#define HAVE_PCI_DEV_ID 1 + +/* pci_is_thunderbolt_attached() is available */ +#define HAVE_PCI_IS_THUNDERBOLD_ATTACHED 1 + +/* pci_pr3_present() is available */ +#define HAVE_PCI_PR3_PRESENT 1 + +/* pci_rebar_bytes_to_size() is available */ +#define HAVE_PCI_REBAR_BYTES_TO_SIZE 1 + +/* pci_upstream_bridge() is available */ +#define HAVE_PCI_UPSTREAM_BRIDGE 1 + +/* perf_event_update_userpage() is exported */ +#define HAVE_PERF_EVENT_UPDATE_USERPAGE 1 + +/* pfn_t is defined */ +#define HAVE_PFN_T 1 + +/* vm_insert_mixed() wants pfn_t arg */ +/* #undef HAVE_PFN_T_VM_INSERT_MIXED */ + +/* pm_genpd_remove_device() wants 2 arguments */ +/* #undef HAVE_PM_GENPD_REMOVE_DEVICE_2ARGS */ + +/* remove_conflicting_framebuffers() returns int */ +/* #undef HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT */ + +/* request_firmware_direct() is available */ +#define HAVE_REQUEST_FIRMWARE_DIRECT 1 + +/* reservation_object->staged is available */ +/* #undef HAVE_RESERVATION_OBJECT_STAGED */ + +/* sched_set_fifo_low() is available */ +#define HAVE_SCHED_SET_FIFO_LOW 1 + +/* seq_hex_dump() is available */ +#define HAVE_SEQ_HEX_DUMP 1 + +/* drm_driver->set_busid is available */ +/* #undef HAVE_SET_BUSID_IN_STRUCT_DRM_DRIVER */ + +/* whether si_mem_available() is available */ +#define HAVE_SI_MEM_AVAILABLE 1 + +/* strscpy() is available */ +#define HAVE_STRSCPY 1 + +/* struct dma_buf_ops->allow_peer2peer is available */ +/* #undef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER */ + +/* struct dma_buf_ops->pin() is available */ +#define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 + +/* struct drm_connector_state->duplicated is available */ +#define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 + +/* struct drm_connector_state->colorspace is available */ +#define HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE 1 + +/* struct drm_connector_state->self_refresh_aware is available */ +#define HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE 1 + +/* drm_connector->ycbcr_420_allowed is available */ +#define HAVE_STRUCT_DRM_CONNECTOR_YCBCR_420_ALLOWED 1 + +/* drm_crtc_funcs->enable_vblank() is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK 1 + +/* crtc->funcs->gamma_set() wants 5 args */ +/* #undef HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS */ + +/* crtc->funcs->gamma_set() wants 6 args */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS 1 + +/* struct drm_crtc_funcs->get_vblank_timestamp() is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP 1 + +/* drm_crtc_funcs->{get,verify}_crc_sources() is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES 1 + +/* drm_crtc_funcs->page_flip_target() is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET 1 + +/* drm_crtc_funcs->page_flip_target() wants ctx parameter */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX 1 + +/* drm_crtc_funcs->set_config() wants ctx parameter */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX 1 + +/* crtc->funcs->set_crc_source() is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CRC_SOURCE 1 + +/* crtc->funcs->set_crc_source() wants 2 args */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CRC_SOURCE_2ARGS 1 + +/* struct drm_crtc_state->async_flip is available */ +#define HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP 1 + +/* struct drm_crtc_state has flag for flip */ +#define HAVE_STRUCT_DRM_CRTC_STATE_FLIP_FLAG 1 + +/* struct drm_crtc_state->pageflip_flags is available */ +/* #undef HAVE_STRUCT_DRM_CRTC_STATE_PAGEFLIP_FLAGS */ + +/* drm_gem_open_object is defined in struct drm_drv */ +/* #undef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ + +/* drm_pending_vblank_event->sequence is available */ +#define HAVE_STRUCT_DRM_PENDING_VBLANK_EVENT_SEQUENCE 1 + +/* drm_plane_helper_funcs->atomic_async_check() is available */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK 1 + +/* drm_plane_helper_funcs->prepare_fb() wants const p arg */ +/* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_CONST */ + +/* drm_plane_helper_funcs->prepare_fb() wants p,p arg */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_PP 1 + +/* zone->managed_pages is available */ +/* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ + +/* timer_setup() is available */ +#define HAVE_TIMER_SETUP 1 + +/* interval_tree_insert have struct rb_root_cached */ +#define HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED 1 + +/* ttm_sg_tt_init() is available */ +#define HAVE_TTM_SG_TT_INIT 1 + +/* __poll_t is available */ +#define HAVE_TYPE__POLL_T 1 + /* Define to 1 if you have the header file. */ #define HAVE_UAPI_LINUX_SCHED_TYPES_H 1 +/* vga_switcheroo_set_dynamic_switch() exist */ +/* #undef HAVE_VGA_SWITCHEROO_SET_DYNAMIC_SWITCH */ + +/* vmf_insert_*() are available */ +#define HAVE_VMF_INSERT 1 + +/* vmf_insert_mixed_prot() is available */ +#define HAVE_VMF_INSERT_MIXED_PROT 1 + +/* vmf_insert_pfn_{pmd,pud}() wants 3 args */ +/* #undef HAVE_VMF_INSERT_PFN_PMD_3ARGS */ + +/* vmf_insert_pfn_{pmd,pud}_prot() is available */ +#define HAVE_VMF_INSERT_PFN_PMD_PROT 1 + +/* vmf_insert_pfn_prot() is available */ +#define HAVE_VMF_INSERT_PFN_PROT 1 + +/* vmf_insert_pfn_pud() is available */ +/* #undef HAVE_VMF_INSERT_PFN_PUD */ + +/* vm_fault->{address/vam} is available */ +#define HAVE_VM_FAULT_ADDRESS_VMA 1 + +/* vm_insert_pfn_prot() is available */ +/* #undef HAVE_VM_INSERT_PFN_PROT */ + +/* vm_operations_struct->fault() wants 1 arg */ +#define HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG 1 + +/* wait_queue_entry_t exists */ +#define HAVE_WAIT_QUEUE_ENTRY 1 + +/* zone_managed_pages() is available */ +#define HAVE_ZONE_MANAGED_PAGES 1 + +/* __drm_atomic_helper_connector_destroy_state() wants 1 arg */ +#define HAVE___DRM_ATOMIC_HELPER_CONNECTOR_DESTROY_STATE_P 1 + +/* __drm_atomic_helper_crtc_destroy_state() wants 1 arg */ +#define HAVE___DRM_ATOMIC_HELPER_CRTC_DESTROY_STATE_P 1 + +/* __drm_atomic_helper_crtc_reset() is available */ +#define HAVE___DRM_ATOMIC_HELPER_CRTC_RESET 1 + +/* __kthread_should_park() is available */ +#define HAVE___KTHREAD_SHOULD_PARK 1 + +/* __print_array is available */ +#define HAVE___PRINT_ARRAY 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" From 0403355f8eb947ce5900645865be6f257f7eb15d Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Wed, 24 Mar 2021 17:30:18 +0800 Subject: [PATCH 0450/2653] drm/amdkcl: re-generate the config.h Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/dkms/config/config.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1159d273a7753..deeb11aad8f2a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -11,7 +11,7 @@ #define HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS 1 /* acpi_put_table() is available */ -/* #undef HAVE_ACPI_PUT_TABLE */ +#define HAVE_ACPI_PUT_TABLE 1 /* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ #define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 @@ -26,7 +26,7 @@ #define HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 1 /* amd_iommu_pc_supported() is available */ -/* #undef HAVE_AMD_IOMMU_PC_SUPPORTED */ +#define HAVE_AMD_IOMMU_PC_SUPPORTED 1 /* arch_io_{reserve/free}_memtype_wc() are available */ #define HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC 1 @@ -449,6 +449,9 @@ /* drm_gem_ttm_vmap() is available */ #define HAVE_DRM_GEM_TTM_VMAP 1 +/* drm_gen_fb_init_with_funcs() is available */ +#define HAVE_DRM_GEN_FB_INIT_WITH_FUNCS 1 + /* drm_get_format_info() is available */ #define HAVE_DRM_GET_FORMAT_INFO 1 From ad59b6a52b81d630bb80984723303e44e32b1185 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 21 Jan 2021 15:02:48 +0800 Subject: [PATCH 0451/2653] drm/amdkcl: rework dma-fence header file handling Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- include/kcl/header/linux/dma-fence-array.h | 11 +++++++++++ include/kcl/header/linux/dma-fence.h | 11 +++++++++++ include/kcl/kcl_fence.h | 7 +------ include/kcl/kcl_fence_array.h | 6 +++--- 4 files changed, 26 insertions(+), 9 deletions(-) create mode 100644 include/kcl/header/linux/dma-fence-array.h create mode 100644 include/kcl/header/linux/dma-fence.h diff --git a/include/kcl/header/linux/dma-fence-array.h b/include/kcl/header/linux/dma-fence-array.h new file mode 100644 index 0000000000000..49bb1fcd2a798 --- /dev/null +++ b/include/kcl/header/linux/dma-fence-array.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__LINUX_DMA_FENCE_ARRAY_H_H_ +#define _KCL_HEADER__LINUX_DMA_FENCE_ARRAY_H_H_ + +#if defined(HAVE_LINUX_DMA_FENCE_H) +#include_next +#elif defined(HAVE_LINUX_FENCE_ARRAY_H) +#include +#endif + +#endif diff --git a/include/kcl/header/linux/dma-fence.h b/include/kcl/header/linux/dma-fence.h new file mode 100644 index 0000000000000..d4bb6177302a3 --- /dev/null +++ b/include/kcl/header/linux/dma-fence.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__LINUX_DMA_FENCE_H_H_ +#define _KCL_HEADER__LINUX_DMA_FENCE_H_H_ + +#if defined(HAVE_LINUX_DMA_FENCE_H) +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index 7a869acf02b93..947efbf7e38aa 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -14,13 +14,8 @@ #include #include -#if !defined(HAVE_LINUX_DMA_FENCE_H) -#include -#include -#else #include -#include -#endif +#include #if !defined(HAVE_LINUX_DMA_FENCE_H) #define dma_fence_cb fence_cb diff --git a/include/kcl/kcl_fence_array.h b/include/kcl/kcl_fence_array.h index 8bce1cf8ff00c..1e8f37c5864d3 100644 --- a/include/kcl/kcl_fence_array.h +++ b/include/kcl/kcl_fence_array.h @@ -23,10 +23,10 @@ #ifndef AMDKCL_FENCE_ARRAY_H #define AMDKCL_FENCE_ARRAY_H +#include + #if !defined(HAVE_LINUX_DMA_FENCE_H) -#if defined(HAVE_LINUX_FENCE_ARRAY_H) -#include -#else +#if !defined(HAVE_LINUX_FENCE_ARRAY_H) #include /** From 9b2b7d5809dc190666b67fc87cbaa8a5df64b643 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 29 Mar 2021 20:24:42 +0800 Subject: [PATCH 0452/2653] drm/amdkcl: fix the autotest of drm_gem_ttm_helper.h Signed-off-by: Shiwu Zhang --- include/kcl/header/drm/drm_gem_ttm_helper.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/kcl/header/drm/drm_gem_ttm_helper.h b/include/kcl/header/drm/drm_gem_ttm_helper.h index 1f4610148dd07..5612902e4958d 100644 --- a/include/kcl/header/drm/drm_gem_ttm_helper.h +++ b/include/kcl/header/drm/drm_gem_ttm_helper.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER_DRM_VBLANK_H_H_ -#define _KCL_HEADER_DRM_VBLANK_H_H_ +#ifndef _KCL_HEADER_DRM_GEM_TTM_HELPER_H_H_ +#define _KCL_HEADER_DRM_GEM_TTM_HELPER_H_H_ -#ifdef HAVE_DRM_DRM_DRM_GEM_TTM_HELPER_H +#ifdef HAVE_DRM_DRM_GEM_TTM_HELPER_H #include_next #endif From 3104f2390412c2e1d939d8570f75c6798aed4f43 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 16:46:45 +0800 Subject: [PATCH 0453/2653] drm/amdkcl: clear up the license left out during rebase Signed-off-by: Shiwu Zhang Signed-off-by: Asher Song --- .../drm/amd/amdkcl/kcl_drm_atomic_helper.c | 2 + .../gpu/drm/amd/amdkcl/kcl_drm_connector.c | 22 +++++++++- drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c | 31 +++++++++++++- drivers/gpu/drm/amd/amdkcl/kcl_memory.c | 32 ++++++++++++++- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 3 ++ drivers/gpu/drm/amd/backport/Makefile | 3 +- drivers/gpu/drm/amd/backport/backport.h | 1 + .../include/kcl/kcl_amdgpu_drm_fb_helper.h | 21 ---------- .../kcl_amdgpu_drm_gem_framebuffer_helper.h | 30 ++++++++++++++ drivers/gpu/drm/amd/backport/kcl_drm_drv.c | 28 ++++++++++++- .../backport/kcl_drm_gem_framebuffer_helper.c | 40 +++++++++++++++++++ .../backport/kcl_drm_atomic_helper_backport.h | 28 ++++++++++++- include/kcl/backport/kcl_drm_encoder.h | 1 + .../backport/kcl_drm_vma_manager_backport.h | 1 + include/kcl/backport/kcl_hmm.h | 9 ++++- include/kcl/backport/kcl_pci_backport.h | 2 +- include/kcl/kcl_device.h | 7 +++- include/kcl/kcl_dma_mapping.h | 1 + include/kcl/kcl_drm_fb.h | 1 + include/kcl/kcl_kernel.h | 1 + include/kcl/kcl_kthread.h | 1 + include/kcl/kcl_mm.h | 1 + include/kcl/kcl_pci.h | 2 + include/kcl/kcl_preempt.h | 2 +- include/kcl/kcl_rcupdate.h | 19 ++++++++- include/kcl/kcl_task_barrier.h | 24 ++++++++++- include/kcl/kcl_version.h | 2 +- 27 files changed, 281 insertions(+), 34 deletions(-) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h create mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c index 3e2cf46b8526c..58beb9fcedf38 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -30,6 +30,7 @@ #include #ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET +/* Copied from drivers/gpu/drm/drm_atomic_state_helper.c and modified for KCL */ void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, struct drm_plane_state *state) { @@ -49,6 +50,7 @@ EXPORT_SYMBOL(_kcl__drm_atomic_helper_plane_reset); #endif #ifndef HAVE___DRM_ATOMIC_HELPER_CRTC_RESET +/* Copied from drivers/gpu/drm/drm_atomic_state_helper.c */ void __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index a467ebb08a8f3..ebcb2ae541c33 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -1,4 +1,24 @@ -/* SPDX-License-Identifier: MIT */ +/* + * Copyright (c) 2016 Intel Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ #include #ifndef HAVE_DRM_CONNECTOR_INIT_WITH_DDC diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c index 900629e0dc0ed..139e955f225eb 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -1,4 +1,32 @@ -/* SPDX-License-Identifier: MIT */ +/* + * Copyright (c) 2006-2009 Red Hat Inc. + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * + * DRM framebuffer helper functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Dave Airlie + * Jesse Barnes + */ #include #include #include @@ -32,6 +60,7 @@ EXPORT_SYMBOL(drm_fb_helper_fill_info); #ifndef HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED /** + * Copied from drivers/gpu/drm/drm_fb_helper.c and modified for KCL. * _kcl_drm_fb_helper_set_suspend_stub - wrapper around fb_set_suspend * @fb_helper: driver-allocated fbdev helper * @state: desired state, zero to resume, non-zero to suspend diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c index 9d5358ca93b48..f5d947730e628 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c @@ -1,6 +1,36 @@ -/* SPDX-License-Identifier: MIT */ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/************************************************************************** + * + * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ +/* + * Authors: Thomas Hellstrom + */ #include +/* Copied from drivers/gpu/drm/ttm/ttm_bo_vm.c and modified for KCL */ #ifndef HAVE_VMF_INSERT_MIXED_PROT vm_fault_t _kcl_vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, pfn_t pfn, pgprot_t pgprot) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index 6cc6a80b921e4..42ca0b4a36945 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -22,6 +22,7 @@ #include #if !defined(HAVE_PCIE_BANDWIDTH_AVAILABLE) +/* Copied from drivers/pci/probe.c and modified for KCL */ const unsigned char *_kcl_pcie_link_speed; const unsigned char _kcl_pcie_link_speed_stub[] = { @@ -43,6 +44,7 @@ const unsigned char _kcl_pcie_link_speed_stub[] = { PCI_SPEED_UNKNOWN /* F */ }; +/* Copied from drivers/pci/pci.c */ /** * pcie_bandwidth_available - determine minimum link settings of a PCIe * device and its bandwidth limitation @@ -320,6 +322,7 @@ EXPORT_SYMBOL_GPL(_kcl_pci_pr3_present); #endif /* HAVE_PCI_PR3_PRESENT */ #ifdef AMDKCL_CREATE_MEASURE_FILE +/* Copied from drivers/pci/pci-sysfs.c */ static ssize_t max_link_speed_show(struct device *dev, struct device_attribute *attr, char *buf) { diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index 115fc89f8204f..ba3805d29cbc3 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: MIT -BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o +BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ + kcl_drm_gem_framebuffer_helper.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 15f2db83d31cd..7c48927ff0bd7 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -67,6 +67,7 @@ #include #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" +#include "kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" #include "kcl/kcl_drm_gem_ttm_helper.h" diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h index 40a89aea46e78..b67bfda700d77 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -39,25 +39,4 @@ void drm_fb_helper_lastclose(struct drm_device *dev); void drm_fb_helper_output_poll_changed(struct drm_device *dev); #endif -static inline -void kcl_drm_gem_fb_set_obj(struct drm_framebuffer *fb, int index, struct drm_gem_object *obj) -{ -#ifdef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H - if (fb) - fb->obj[index] = obj; -#else - struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); - (void)index; /* for compile un-used warning */ - if (afb) - afb->obj = obj; -#endif -} -#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H -struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, - unsigned int plane); -void drm_gem_fb_destroy(struct drm_framebuffer *fb); -int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, - unsigned int *handle); -#endif - #endif diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h new file mode 100644 index 0000000000000..bbd3326b824bf --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h @@ -0,0 +1,30 @@ +#ifndef __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_FRAMEBUFFER_HELPER_H__ +#define __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_FRAMEBUFFER_HELPER_H__ + +#include +#include "amdgpu.h" + +static inline +void kcl_drm_gem_fb_set_obj(struct drm_framebuffer *fb, int index, struct drm_gem_object *obj) +{ +#ifdef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H + if (fb) + fb->obj[index] = obj; +#else + struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); + (void)index; /* for compile un-used warning */ + if (afb) + afb->obj = obj; +#endif +} + +#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H +/* Copied from include/drm/drm_gem_framebuffer_helper.h */ +struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, + unsigned int plane); +void drm_gem_fb_destroy(struct drm_framebuffer *fb); +int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, + unsigned int *handle); +#endif + +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_drv.c b/drivers/gpu/drm/amd/backport/kcl_drm_drv.c index d6b18e3a75f73..9783e852192a5 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_drv.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_drv.c @@ -1,4 +1,30 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org + * + * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Author Rickard E. (Rik) Faith + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include #include "amdgpu.h" diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c new file mode 100644 index 0000000000000..1f68cf8bbe2b3 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * drm gem framebuffer helper functions + * + * Copyright (C) 2017 Noralf Trønnes + */ + +#include + +/* Copied from drivers/gpu/drm/drm_gem_framebuffer_helper.c and modified for KCL */ +#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H +struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, + unsigned int plane) +{ + struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); + (void)plane; /* for compile un-used warning */ + if (afb) + return afb->obj; + else + return NULL; +} + +void drm_gem_fb_destroy(struct drm_framebuffer *fb) +{ + struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); + + drm_gem_object_put(amdgpu_fb->obj); + + drm_framebuffer_cleanup(fb); + kfree(fb); +} + +int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, + unsigned int *handle) +{ + struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); + + return drm_gem_handle_create(file, amdgpu_fb->obj, handle); +} +#endif diff --git a/include/kcl/backport/kcl_drm_atomic_helper_backport.h b/include/kcl/backport/kcl_drm_atomic_helper_backport.h index 1edfc203e12ce..eaa2464b77353 100644 --- a/include/kcl/backport/kcl_drm_atomic_helper_backport.h +++ b/include/kcl/backport/kcl_drm_atomic_helper_backport.h @@ -1,4 +1,30 @@ -/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2014 Red Hat + * Copyright (C) 2014 Intel Corp. + * Copyright (C) 2018 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + * Daniel Vetter + */ #ifndef AMDKCL_DRM_ATOMIC_HELPER_BACKPORT_H #define AMDKCL_DRM_ATOMIC_HELPER_BACKPORT_H diff --git a/include/kcl/backport/kcl_drm_encoder.h b/include/kcl/backport/kcl_drm_encoder.h index 07e3a75541b80..0efc8f747defd 100644 --- a/include/kcl/backport/kcl_drm_encoder.h +++ b/include/kcl/backport/kcl_drm_encoder.h @@ -37,6 +37,7 @@ #include #include +/* Copied from drivers/gpu/drm/drm_edid.c and modified for KCL */ #if defined(HAVE_DRM_EDID_TO_ELD) static inline int _kcl_drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) diff --git a/include/kcl/backport/kcl_drm_vma_manager_backport.h b/include/kcl/backport/kcl_drm_vma_manager_backport.h index 0a7e1bf34bd82..9893688f6fac2 100644 --- a/include/kcl/backport/kcl_drm_vma_manager_backport.h +++ b/include/kcl/backport/kcl_drm_vma_manager_backport.h @@ -29,6 +29,7 @@ #include #include +/* Copied from include/drm/drm_vma_manager.h */ #if (BITS_PER_LONG == 64) #ifdef DRM_FILE_PAGE_OFFSET_START #undef DRM_FILE_PAGE_OFFSET_START diff --git a/include/kcl/backport/kcl_hmm.h b/include/kcl/backport/kcl_hmm.h index 233b0cbda947a..7dad7453aaa89 100644 --- a/include/kcl/backport/kcl_hmm.h +++ b/include/kcl/backport/kcl_hmm.h @@ -1,4 +1,11 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2013 Red Hat Inc. + * + * Authors: Jérôme Glisse + * + * See Documentation/vm/hmm.rst for reasons and overview of what HMM is. + */ #ifndef _KCL_BACKPORT_KCL_HMM_H #define _KCL_BACKPORT_KCL_HMM_H diff --git a/include/kcl/backport/kcl_pci_backport.h b/include/kcl/backport/kcl_pci_backport.h index 21799422a6abd..2cf66ef4aa69f 100644 --- a/include/kcl/backport/kcl_pci_backport.h +++ b/include/kcl/backport/kcl_pci_backport.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef AMDKCL_PCI_BACKPORT_H #define AMDKCL_PCI_BACKPORT_H diff --git a/include/kcl/kcl_device.h b/include/kcl/kcl_device.h index 078622c69af21..a4d0dfbb334bc 100644 --- a/include/kcl/kcl_device.h +++ b/include/kcl/kcl_device.h @@ -1,10 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0 */ +/* + * Definitions for the NVM Express interface + * Copyright (c) 2011-2014, Intel Corporation. + */ #ifndef AMDKCL_DEVICE_H #define AMDKCL_DEVICE_H #include #include +/* Copied from include/linux/dev_printk.h */ #if !defined(dev_err_once) #ifdef CONFIG_PRINTK #define dev_level_once(dev_level, dev, fmt, ...) \ @@ -51,7 +56,7 @@ do { \ #define DPM_FLAG_SMART_PREPARE BIT(1) static inline void dev_pm_set_driver_flags(struct device *dev, u32 flags) { - printk_once(KERN_WARNING "%s is not available\n", __func__); + pr_warn_once("%s is not available\n", __func__); } #endif diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h index 24d18c3a7bf27..ba248dc82f298 100644 --- a/include/kcl/kcl_dma_mapping.h +++ b/include/kcl/kcl_dma_mapping.h @@ -131,6 +131,7 @@ static inline void dma_unmap_sgtable(struct device *dev, struct sg_table *sgt, /* * v5.8-rc3-2-g68d237056e00 ("scatterlist: protect parameters of the sg_table related macros") * v5.7-rc5-33-g709d6d73c756 ("scatterlist: add generic wrappers for iterating over sgtable objects") + * Copied from include/linux/scatterlist.h */ #ifndef for_each_sgtable_sg #define for_each_sgtable_sg(sgt, sg, i) \ diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 3a0d30273cf7a..2b90f5bcd8682 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -35,6 +35,7 @@ #include #include +/* Copied from include/drm/drm_fb_helper.h */ /* * Don't add fb_debug_* since the legacy drm_fb_helper_debug_* has segfault * history: diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index ef5bdee50ee36..d055fad138c19 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -16,6 +16,7 @@ #endif #ifndef __GFP_RETRY_MAYFAIL +/* Copied from include/linux/gfp.h and modified for KCL */ #define __GFP_RETRY_MAYFAIL __GFP_NORETRY #endif diff --git a/include/kcl/kcl_kthread.h b/include/kcl/kcl_kthread.h index 90893fd2590b1..f9cca65e1ea6c 100644 --- a/include/kcl/kcl_kthread.h +++ b/include/kcl/kcl_kthread.h @@ -17,6 +17,7 @@ extern int (*_kcl_kthread_park)(struct task_struct *k); extern bool (*_kcl_kthread_should_park)(void); #endif +/* Copied from v5.7-13665-g9bf5b9eb232b kernel/kthread.c */ #ifndef HAVE_KTHREAD_USE_MM static inline void kthread_use_mm(struct mm_struct *mm) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 402a28df45f0e..be023c0b95edd 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -42,6 +42,7 @@ static inline void memalloc_nofs_restore(unsigned int flags) #endif #if !defined(HAVE_ZONE_MANAGED_PAGES) +/* Copied from v4.20-6505-g9705bea5f833 include/linux/mmzone.h and modified for KCL */ static inline unsigned long zone_managed_pages(struct zone *zone) { #if defined(HAVE_STRUCT_ZONE_MANAGED_PAGES) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index b93c8b9e91ff0..f10e5e5c84106 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -129,6 +129,7 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) } #endif +/* Copied from v3.12-rc2-29-gc6bde215acfd include/linux/pci.h */ #if !defined(HAVE_PCI_UPSTREAM_BRIDGE) static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) { @@ -164,6 +165,7 @@ static inline void kcl_pci_configure_extended_tags(struct pci_dev *dev) #endif } +/* Copied from v5.1-rc1-5-g4e544bac8267 include/linux/pci.h */ #if !defined(HAVE_PCI_DEV_ID) static inline u16 pci_dev_id(struct pci_dev *dev) { diff --git a/include/kcl/kcl_preempt.h b/include/kcl/kcl_preempt.h index d76961463a6e3..1e59cbca1bf73 100644 --- a/include/kcl/kcl_preempt.h +++ b/include/kcl/kcl_preempt.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef AMDKCL_PREEMPT_H #define AMDKCL_PREEMPT_H #include diff --git a/include/kcl/kcl_rcupdate.h b/include/kcl/kcl_rcupdate.h index ec31bae327ead..da63bf6d4f9e0 100644 --- a/include/kcl/kcl_rcupdate.h +++ b/include/kcl/kcl_rcupdate.h @@ -1,4 +1,21 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Read-Copy Update mechanism for mutual exclusion + * + * Copyright IBM Corporation, 2001 + * + * Author: Dipankar Sarma + * + * Based on the original work by Paul McKenney + * and inputs from Rusty Russell, Andrea Arcangeli and Andi Kleen. + * Papers: + * http://www.rdrop.com/users/paulmck/paper/rclockpdcsproof.pdf + * http://lse.sourceforge.net/locking/rclock_OLS.2001.05.01c.sc.pdf (OLS2001) + * + * For detailed explanation of Read-Copy Update mechanism see - + * http://lse.sourceforge.net/locking/rcupdate.html + * + */ #ifndef AMDKCL_RCUPDATE_H #define AMDKCL_RCUPDATE_H diff --git a/include/kcl/kcl_task_barrier.h b/include/kcl/kcl_task_barrier.h index 341fe8e02a9d9..315bff4402dbc 100644 --- a/include/kcl/kcl_task_barrier.h +++ b/include/kcl/kcl_task_barrier.h @@ -1,10 +1,32 @@ -/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ #ifndef AMDKCL_DRM_TASK_BARRIER_H #define AMDKCL_DRM_TASK_BARRIER_H #ifdef HAVE_DRM_TASK_BARRIER_H #include #else +/* Copied from include/drm/task_barrier.h */ /* * Reusable 2 PHASE task barrier (randevouz point) implementation for N tasks. * Based on the Little book of sempahores - https://greenteapress.com/wp/semaphores/ diff --git a/include/kcl/kcl_version.h b/include/kcl/kcl_version.h index 4a470ef6dbbc7..59a859a26a540 100644 --- a/include/kcl/kcl_version.h +++ b/include/kcl/kcl_version.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef AMDKCL_VERSION_H #define AMDKCL_VERSION_H From 6d01eef1e1605af5c5cfc96fda36f1b80d908446 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 22 Mar 2021 14:32:02 +0800 Subject: [PATCH 0454/2653] drm/amdkcl: test whether pm_suspend_via_firmware is available This patch is caused by following commit 'drm/amdgpu: add a dev_pm_ops prepare callback (v2)' v5.11-2759-ga2839ac3fd80 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/pm-suspend-via-firmware.m4 | 17 +++++++++++++++++ include/kcl/kcl_suspend.h | 5 +++++ 4 files changed, 26 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pm-suspend-via-firmware.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index deeb11aad8f2a..9be686177182d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -795,6 +795,9 @@ /* pm_genpd_remove_device() wants 2 arguments */ /* #undef HAVE_PM_GENPD_REMOVE_DEVICE_2ARGS */ +/* pm_suspend_via_firmware() is available */ +#define HAVE_PM_SUSPEND_VIA_FIRMWARE 1 + /* remove_conflicting_framebuffers() returns int */ /* #undef HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a370c9600c8d1..9916006d72aa7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -138,6 +138,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_TTM_VMAP AC_AMDGPU_FS_RECLAIM_ACQUIRE AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE + AC_AMDGPU_PM_SUSPEND_VIA_FIRMWARE AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/pm-suspend-via-firmware.m4 b/drivers/gpu/drm/amd/dkms/m4/pm-suspend-via-firmware.m4 new file mode 100644 index 0000000000000..d5bcda40a4d71 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm-suspend-via-firmware.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v4.3-rc5-6-gef25ba047601 +dnl # PM / sleep: Add flags to indicate platform firmware involvement +dnl # +AC_DEFUN([AC_AMDGPU_PM_SUSPEND_VIA_FIRMWARE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + pm_suspend_via_firmware(); + ],[ + AC_DEFINE(HAVE_PM_SUSPEND_VIA_FIRMWARE, + 1, + [pm_suspend_via_firmware() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_suspend.h b/include/kcl/kcl_suspend.h index 37a3cab923aa5..fb2c02994f763 100644 --- a/include/kcl/kcl_suspend.h +++ b/include/kcl/kcl_suspend.h @@ -14,4 +14,9 @@ static inline void ksys_sync_helper(void) static inline void ksys_sync_helper(void) {} #endif /* CONFIG_PM_SLEEP */ #endif /* HAVE_KSYS_SYNC_HELPER */ + +#ifndef HAVE_PM_SUSPEND_VIA_FIRMWARE +static inline bool pm_suspend_via_firmware(void) { return false; } +#endif /* HAVE_PM_SUSPEND_VIA_FIRMWARE */ + #endif /* AMDKCL_SUSPEND_H */ From 2c44ada431dd008b96f67963d9979919469c2ec4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 22 Mar 2021 14:47:46 +0800 Subject: [PATCH 0455/2653] drm/amdkcl: add DPM_FLAG_SMART_SUSPEND and DPM_FLAG_MAY_SKIP_RESUME macro This patch is caused by following commit 'drm/amdgpu: enable DPM_FLAG_MAY_SKIP_RESUME and DPM_FLAG_SMART_SUSPEND flags (v2)' v5.11-2760-g3d6ae23c0594 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- include/kcl/kcl_pm.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/kcl/kcl_pm.h b/include/kcl/kcl_pm.h index 157fc65f14708..37c761718589e 100644 --- a/include/kcl/kcl_pm.h +++ b/include/kcl/kcl_pm.h @@ -7,6 +7,7 @@ #ifndef KCL_KCL_PM_H #define KCL_KCL_PM_H +#include #include /* @@ -17,4 +18,21 @@ #define DPM_FLAG_NO_DIRECT_COMPLETE DPM_FLAG_NEVER_SKIP #endif + +/* + * v4.15-rc1-1-g0d4b54c6fee8 + * PM / core: Add LEAVE_SUSPENDED driver flag + */ +#ifndef DPM_FLAG_SMART_SUSPEND +#define DPM_FLAG_SMART_SUSPEND BIT(2) +#endif + +/* + * v5.7-rc2-8-g2a3f34750b8b + * PM: sleep: core: Rename DPM_FLAG_LEAVE_SUSPENDED + */ +#ifndef DPM_FLAG_MAY_SKIP_RESUME +#define DPM_FLAG_MAY_SKIP_RESUME BIT(3) +#endif + #endif From 0728afb10f201a04dd7d0b57e0ce23dfd9626a8c Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 22 Mar 2021 15:28:30 +0800 Subject: [PATCH 0456/2653] drm/amdkcl: adapt code using list_for_each_entry for legacy os This patch is caused by following commit 'drm/amdgpu: clean up non-DC suspend/resume handling' v5.11-2764-ga7c22df2fd07 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 7fd927cadca3b..89b7a31f78cc5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1961,18 +1961,28 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) struct drm_device *dev = adev_to_drm(adev); struct drm_crtc *crtc; struct drm_connector *connector; + +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif int r; drm_kms_helper_poll_disable(dev); /* turn off display hw */ drm_modeset_lock_all(dev); +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) +#else + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) +#endif drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); + +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif drm_modeset_unlock_all(dev); /* unpin the front buffers and cursors */ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { @@ -2009,7 +2019,9 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct drm_crtc *crtc; int r; @@ -2037,12 +2049,18 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev) /* turn on display hw */ drm_modeset_lock_all(dev); +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) +#else + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) +#endif drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif drm_modeset_unlock_all(dev); drm_kms_helper_poll_enable(dev); From 4fcc06344d12e1329c0f91a7053c71a866803ae3 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 23 Mar 2021 15:41:51 +0800 Subject: [PATCH 0457/2653] drm/amdkcl: adapt code using drm_gem_fb_get_obj for legacy os This patch is caused by following commit 'drm/amdgpu: clean up non-DC suspend/resume handling' v5.11-2764-ga7c22df2fd07 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 89b7a31f78cc5..b696bc0c25edf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -2000,10 +2000,10 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) } } - if (!fb || !fb->obj[0]) + if (!fb || !drm_gem_fb_get_obj(fb, 0)) continue; - robj = gem_to_amdgpu_bo(fb->obj[0]); + robj = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); if (!amdgpu_display_robj_is_fb(adev, robj)) { r = amdgpu_bo_reserve(robj, true); if (r == 0) { From a422df9ce29942c77f32bee803cbdab40a930918 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Tue, 8 Sep 2020 17:25:51 +0800 Subject: [PATCH 0458/2653] drm/amdkfd: add debug support for aldebaran The following commits have been squashed/touched up from npi and will go into dkms-staging: 'commit 156affb5f5d7 ("drm/amdkfd: update per-vmid registers for debug attach/detach")' 'commit 656b84994342 ("drm/amdgpu: fix lock scheme on aldebaran debug functions")' 'commit a376539fcd40 ("drm/amdkfd: add precise memory operations enable for aldebaran")' 'commit 32548be937a8 ("drm/amdgpu: unify debug setting fixes in aldebaran")' 'commit fc209adaf7ce ("drm/amdgpu: add new address watch functions to aldebaran")' The following has been omitted: References to anything emulation related Experimental host trap commands Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c index 7e9f7a280c1b9..c55bc29a2c77c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c @@ -26,6 +26,7 @@ #include "amdgpu_amdkfd_aldebaran.h" #include "gc/gc_9_4_2_offset.h" #include "gc/gc_9_4_2_sh_mask.h" +#include "soc15.h" #include /* From f2805b30735717c2abe4a952707a857979949ac6 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 31 Mar 2021 11:03:09 +0800 Subject: [PATCH 0459/2653] drm/amdkcl: fake the sysfs_emit This is caused by "Convert sysfs sprintf/snprintf family to sysfs_emit" v5.11-2844-g5f7dd9b5c2d3 Signed-off-by: Leslie Shi Reviewed by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 1 + drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c | 32 +++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 | 13 +++++++++ include/kcl/kcl_sysfs_emit.h | 25 ++++++++++++++++ 7 files changed, 76 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 create mode 100644 include/kcl/kcl_sysfs_emit.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 4ea595282d7d1..a22c482f8b7b5 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -16,6 +16,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o +amdkcl-$(CONFIG_SYSFS) += kcl_sysfs_emit.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c b/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c new file mode 100644 index 0000000000000..798745cbfff91 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * fs/sysfs/file.c - sysfs regular (text) file implementation + * + * Copyright (c) 2001-3 Patrick Mochel + * Copyright (c) 2007 SUSE Linux Products GmbH + * Copyright (c) 2007 Tejun Heo + * + * Please see Documentation/filesystems/sysfs.rst for more information. + */ +#include +#include + +/* Copied from fs/sysfs/file.c */ +#ifndef HAVE_SYSFS_EMIT +int sysfs_emit(char *buf, const char *fmt, ...) +{ + va_list args; + int len; + + if (WARN(!buf || offset_in_page(buf), + "invalid sysfs_emit: buf:%p\n", buf)) + return 0; + + va_start(args, fmt); + len = vscnprintf(buf, PAGE_SIZE, fmt, args); + va_end(args); + + return len; +} +EXPORT_SYMBOL_GPL(sysfs_emit); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7c48927ff0bd7..2e0f765e1c88d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -63,6 +63,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9be686177182d..416b9a4042b0e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -897,6 +897,9 @@ /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ +/* sysfs_emit() is available */ +#define HAVE_SYSFS_EMIT 1 + /* timer_setup() is available */ #define HAVE_TIMER_SETUP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9916006d72aa7..bca36e9a5e05a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -139,6 +139,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_FS_RECLAIM_ACQUIRE AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE AC_AMDGPU_PM_SUSPEND_VIA_FIRMWARE + AC_AMDGPU_SYSFS_EMIT AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 new file mode 100644 index 0000000000000..e9f403134af83 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit: v5.9-rc5-23-g2efc459d06f1 +dnl # sysfs: Add sysfs_emit and sysfs_emit_at +dnl # to format sysfs output +AC_DEFUN([AC_AMDGPU_SYSFS_EMIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([sysfs_emit], + [fs/sysfs/file.c], [ + AC_DEFINE(HAVE_SYSFS_EMIT, 1, + [sysfs_emit() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_sysfs_emit.h b/include/kcl/kcl_sysfs_emit.h new file mode 100644 index 0000000000000..ab87e74f817ff --- /dev/null +++ b/include/kcl/kcl_sysfs_emit.h @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * sysfs.h - definitions for the device driver filesystem + * + * Copyright (c) 2001,2002 Patrick Mochel + * Copyright (c) 2004 Silicon Graphics, Inc. + * Copyright (c) 2007 SUSE Linux Products GmbH + * Copyright (c) 2007 Tejun Heo + * + * Please see Documentation/filesystems/sysfs.rst for more information. + */ +#include + +#ifndef HAVE_SYSFS_EMIT +#ifdef CONFIG_SYSFS +__printf(2, 3) +int sysfs_emit(char *buf, const char *fmt, ...); +#else +__printf(2, 3) +static inline int sysfs_emit(char *buf, const char *fmt, ...) +{ + return 0; +} +#endif +#endif From 713e5a7f1e3862ac1fc022b42ebd4c6d80099c5a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 5 Aug 2021 10:40:27 +0800 Subject: [PATCH 0460/2653] drm/amdkcl: Test whether io_mapping_unmap_local() is available This is caused by 3bf3710e3718 "drm/ttm: Add a generic TTM memcpy move for page-based iomem" v5.13-rc3-860-g3bf3710e3718 Signed-off-by: Leslie Shi --- .../amd/dkms/m4/io-mapping-map-local-wc.m4 | 15 +++++++++++ .../drm/amd/dkms/m4/io-mapping-unmap-local.m4 | 15 +++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 ++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_io-mapping.h | 26 +++++++++++++++++++ 5 files changed, 59 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/io-mapping-map-local-wc.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/io-mapping-unmap-local.m4 create mode 100644 include/kcl/kcl_io-mapping.h diff --git a/drivers/gpu/drm/amd/dkms/m4/io-mapping-map-local-wc.m4 b/drivers/gpu/drm/amd/dkms/m4/io-mapping-map-local-wc.m4 new file mode 100644 index 0000000000000..72ba661169b58 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/io-mapping-map-local-wc.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit e66f6e095486f0210fcf3c5eb3ecf13fa348be4c +dnl # io-mapping: Provide iomap_local variant +dnl # +AC_DEFUN([AC_AMDGPU_IO_MAPPING_MAP_LOCAL_WC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + io_mapping_map_local_wc(NULL, 0); + ], [ + AC_DEFINE(HAVE_IO_MAPPING_MAP_LOCAL_WC, 1, [io_mapping_map_local_wc() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/io-mapping-unmap-local.m4 b/drivers/gpu/drm/amd/dkms/m4/io-mapping-unmap-local.m4 new file mode 100644 index 0000000000000..282b77e11e1c5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/io-mapping-unmap-local.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit e66f6e095486f0210fcf3c5eb3ecf13fa348be4c +dnl # io-mapping: Provide iomap_local variant +dnl # +AC_DEFUN([AC_AMDGPU_IO_MAPPING_UNMAP_LOCAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + io_mapping_unmap_local(NULL); + ], [ + AC_DEFINE(HAVE_IO_MAPPING_UNMAP_LOCAL, 1, [io_mapping_unmap_local() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index bca36e9a5e05a..b78fcc8bc51cd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -146,6 +146,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_APERTURE AC_AMDGPU_PCI_DRIVER_DEV_GROUPS AC_AMDGPU_DRM_DISPLAY_INFO + AC_AMDGPU_IO_MAPPING_UNMAP_LOCAL + AC_AMDGPU_IO_MAPPING_MAP_LOCAL_WC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index f8fb0af23aa40..603819a994f54 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -16,5 +16,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_io-mapping.h b/include/kcl/kcl_io-mapping.h new file mode 100644 index 0000000000000..6551e94cf3551 --- /dev/null +++ b/include/kcl/kcl_io-mapping.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright © 2008 Keith Packard + */ + +#ifndef KCL_KCL_IO_MAPPING_H +#define KCL_KCL_IO_MAPPING_H + +#include + +#ifndef HAVE_IO_MAPPING_UNMAP_LOCAL +static inline void io_mapping_unmap_local(void __iomem *vaddr) +{ + io_mapping_unmap(vaddr); +} +#endif + +#ifndef HAVE_IO_MAPPING_MAP_LOCAL_WC +static inline void __iomem * +io_mapping_map_local_wc(struct io_mapping *mapping, unsigned long offset) +{ + return io_mapping_map_wc(mapping, offset, PAGE_SIZE); +} +#endif + +#endif /* KCL_KCL_IO_MAPPING_H */ From 97ee8d26402e9583025c473c5d699e3687842421 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 5 Aug 2021 14:01:12 +0800 Subject: [PATCH 0461/2653] drm/amdkcl: Test whether kmap_local_* is available This is caused by 3bf3710e3718 "drm/ttm: Add a generic TTM memcpy move for page-based iomem" v5.13-rc3-860-g3bf3710e3718 Signed-off-by: Leslie Shi --- .../gpu/drm/amd/dkms/m4/highmem-internal.m4 | 6 +-- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_highmem-internal.h | 41 +++++++++++++++++++ 4 files changed, 46 insertions(+), 3 deletions(-) create mode 100644 include/kcl/kcl_highmem-internal.h diff --git a/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 index b2614eabab932..326a3fc8e64c4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 @@ -4,12 +4,12 @@ dnl # mm/highmem: Provide kmap_local* dnl # AC_DEFUN([AC_AMDGPU_KMAP_LOCAL], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include + AC_KERNEL_TRY_COMPILE([ + #include ], [ pgprot_t prot; kmap_local_page_prot(NULL, prot); - ], [], [], [ + ], [ AC_DEFINE(HAVE_KMAP_LOCAL, 1, [kmap_local_* is available]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b78fcc8bc51cd..f7c85100cd43b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -148,6 +148,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DISPLAY_INFO AC_AMDGPU_IO_MAPPING_UNMAP_LOCAL AC_AMDGPU_IO_MAPPING_MAP_LOCAL_WC + AC_AMDGPU_KMAP_LOCAL AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 603819a994f54..e6763a9dfb224 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -17,5 +17,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_highmem-internal.h b/include/kcl/kcl_highmem-internal.h new file mode 100644 index 0000000000000..7304f188d7c2d --- /dev/null +++ b/include/kcl/kcl_highmem-internal.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef KCL_KCL_HIGHMEM_INTERNAL_H +#define KCL_KCL_HIGHMEM_INTERNAL_H + +#include +#include + +#ifndef HAVE_KMAP_LOCAL + +static inline void *kmap_local_page(struct page *page) +{ + return page_address(page); +} + +static inline void *kmap_local_page_prot(struct page *page, pgprot_t prot) +{ + return kmap_local_page(page); +} + +#endif + +#ifndef kunmap_local + +static inline void __kunmap_local(void *addr) +{ +#ifdef ARCH_HAS_FLUSH_ON_KUNMAP + kunmap_flush_on_unmap(addr); +#endif +} + +#define kunmap_local(__addr) \ +do { \ + BUILD_BUG_ON(__same_type((__addr), struct page *)); \ + __kunmap_local(__addr); \ +} while (0) +#endif /* kunmap_local */ + + + +#endif From a90712368aee7a5c5ab52314082e1506bc652a27 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 5 Aug 2021 16:01:03 +0800 Subject: [PATCH 0462/2653] drm/amdkcl: fix build error of amdkcl_ttm_resvp Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 8e1531e5328e1..bd3766490cf1d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -745,7 +745,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { struct amdgpu_vm *vm = bo_base->vm; - struct dma_resv *resv = amdkcl_ttm_resvp(&vm->root.base.bo->tbo); + struct dma_resv *resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); if (ticket) { /* When we get an error here it means that somebody diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index baa30ffe158ed..db141728911fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1511,7 +1511,7 @@ static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, */ static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) { - struct dma_resv *resv = vm->root.bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); struct dma_resv_iter cursor; struct dma_fence *fence; From 80a9fd6b931bc4fc39e980d745f3d7cfb34083d0 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 6 Aug 2021 10:25:47 +0800 Subject: [PATCH 0463/2653] drm/amdkcl: Test whether struct drm_dp_aux has member drm_dev This is caused by 6cba3fe43341 "drm/dp: Add backpointer to drm_device in drm_dp_aux" v5.12-rc7-1495-g6cba3fe43341 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 3 +++ .../gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 21 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index 492813ab1b541..9370fb91ca909 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -189,7 +189,10 @@ void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector) { amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd; amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer; + +#ifdef HAVE_DRM_DP_AUX_DRM_DEV amdgpu_connector->ddc_bus->aux.drm_dev = amdgpu_connector->base.dev; +#endif drm_dp_aux_init(&amdgpu_connector->ddc_bus->aux); amdgpu_connector->ddc_bus->has_aux = true; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 new file mode 100644 index 0000000000000..d851ad71eab97 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.12-rc7-1495-g6cba3fe43341 +dnl # drm/dp: Add backpointer to drm_device in drm_dp_aux +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_AUX_DRM_DEV], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct drm_dp_aux dda; + dda.drm_dev = NULL; + ], [],[],[ + AC_DEFINE(HAVE_DRM_DP_AUX_DRM_DEV, 1, + [struct drm_dp_aux has member named 'drm_dev']) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f7c85100cd43b..6585513a5b491 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -149,6 +149,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IO_MAPPING_UNMAP_LOCAL AC_AMDGPU_IO_MAPPING_MAP_LOCAL_WC AC_AMDGPU_KMAP_LOCAL + AC_AMDGPU_DRM_DP_AUX_DRM_DEV AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From f127a3efb5a8dfbe43baadb5cc4b7707b9a2a2f4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 6 Aug 2021 10:39:04 +0800 Subject: [PATCH 0464/2653] drm/amdkcl: Test whether drm_dp_link_train_clock_recovery_delay() has 2 args This is caused by 9e9866664456 "drm/dp: Pass drm_dp_aux to drm_dp_link_train_clock_recovery_delay()" v5.12-rc7-1497-g9e9866664456 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 4 ++++ .../drm-dp-link-train-clock-recovery-delay.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index 9370fb91ca909..2d9cffe6c4e52 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -616,7 +616,11 @@ amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_i dp_info->tries = 0; voltage = 0xff; while (1) { +#ifdef HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd); +#else + drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); +#endif if (drm_dp_dpcd_read_link_status(dp_info->aux, dp_info->link_status) < 0) { diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 new file mode 100644 index 0000000000000..4d8e0f733eb7e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.12-rc7-1497-g9e9866664456 +dnl # drm/dp: Pass drm_dp_aux to drm_dp_link_train_clock_recovery_delay() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct drm_dp_aux *aux = NULL; + const u8 dpcd[DP_RECEIVER_CAP_SIZE]; + drm_dp_link_train_clock_recovery_delay(aux, dpcd); + ], [drm_dp_link_train_clock_recovery_delay],[drm/drm_dp_helper.c],[ + AC_DEFINE(HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS, 1, + [drm_dp_link_train_clock_recovery_delay() has 2 args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6585513a5b491..6c90a1d35646e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -150,6 +150,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IO_MAPPING_MAP_LOCAL_WC AC_AMDGPU_KMAP_LOCAL AC_AMDGPU_DRM_DP_AUX_DRM_DEV + AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From a39157f91cad36aba822c391353399eb17415250 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 6 Aug 2021 13:27:27 +0800 Subject: [PATCH 0465/2653] drm/amdkcl: Test whether drm_dp_link_train_channel_eq_delay() has 2 args This is caused by 0c4fada608c1 "drm/dp: Pass drm_dp_aux to drm_dp*_link_train_channel_eq_delay()" v5.12-rc7-1498-g0c4fada608c1 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 4 ++++ .../m4/drm-dp-link-train-channel-eq-delay.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index 2d9cffe6c4e52..b81674da7ed76 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -685,7 +685,11 @@ amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_i dp_info->tries = 0; channel_eq = false; while (1) { +#ifdef HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); +#else + drm_dp_link_train_channel_eq_delay(dp_info->dpcd); +#endif if (drm_dp_dpcd_read_link_status(dp_info->aux, dp_info->link_status) < 0) { diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 new file mode 100644 index 0000000000000..664b63498814e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.12-rc7-1498-g0c4fada608c1 +dnl # drm/dp: Pass drm_dp_aux to drm_dp*_link_train_channel_eq_delay() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct drm_dp_aux *aux = NULL; + const u8 dpcd[DP_RECEIVER_CAP_SIZE]; + drm_dp_link_train_channel_eq_delay(aux, dpcd); + ], [drm_dp_link_train_channel_eq_delay],[drm/drm_dp_helper.c],[ + AC_DEFINE(HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS, 1, + [drm_dp_link_train_channel_eq_delay() has 2 args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6c90a1d35646e..95ba8616377b0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -151,6 +151,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KMAP_LOCAL AC_AMDGPU_DRM_DP_AUX_DRM_DEV AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY + AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 62a0efc3185767cc1ecbbcba4b891b3ec604402a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 31 Mar 2021 15:17:23 +0800 Subject: [PATCH 0466/2653] drm/amdkcl: access drm_plane index field using drm_plane_index This is caused by "drm/amd/display: Use appropriate DRM_DEBUG_... level" v5.11-2836-g27f1f74cc17e Signed-off-by: Leslie Shi Reviewed by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 35cfefe72a08d..2c89b5e9182d7 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9556,7 +9556,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, afb->tmz_surface); drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", - new_plane_state->plane->index, + drm_plane_index(new_plane_state->plane), bundle->plane_infos[planes_count].dcc.enable); bundle->surface_updates[planes_count].plane_info = From 0f9db55a66f344f93b76791c3897004a8f9502c8 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 1 Apr 2021 16:59:38 +0800 Subject: [PATCH 0467/2653] drm/amdkcl: wrap the code under HAVE_KTIME_IS_UNION This is caused by "drm/amd/display: Add refresh rate trace" v5.11-2869-g3b8fa2a4ed4c Signed-off-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/ktime-is-union.m4 | 17 +++++++++++++++++ 5 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ktime-is-union.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2c89b5e9182d7..cfcc49717ddbc 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -540,9 +540,11 @@ static void dm_vupdate_high_irq(void *interrupt_params) struct common_irq_params *irq_params = interrupt_params; struct amdgpu_device *adev = irq_params->adev; struct amdgpu_crtc *acrtc; +#ifndef HAVE_KTIME_IS_UNION struct drm_device *drm_dev; struct drm_vblank_crtc *vblank; ktime_t frame_duration_ns, previous_timestamp; +#endif unsigned long flags; int vrr_active; @@ -550,6 +552,7 @@ static void dm_vupdate_high_irq(void *interrupt_params) if (acrtc) { vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); +#ifndef HAVE_KTIME_IS_UNION drm_dev = acrtc->base.dev; vblank = drm_crtc_vblank_crtc(&acrtc->base); previous_timestamp = atomic64_read(&irq_params->previous_timestamp); @@ -561,6 +564,7 @@ static void dm_vupdate_high_irq(void *interrupt_params) ktime_divns(NSEC_PER_SEC, frame_duration_ns)); atomic64_set(&irq_params->previous_timestamp, vblank->time); } +#endif drm_dbg_vbl(drm_dev, "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h index 045283ad899b4..cf168868a0f16 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h @@ -685,6 +685,7 @@ TRACE_EVENT(amdgpu_dmub_trace_high_irq, __entry->param0, __entry->param1) ); +#ifndef HAVE_KTIME_IS_UNION TRACE_EVENT(amdgpu_refresh_rate_track, TP_PROTO(int crtc_index, ktime_t refresh_rate_ns, uint32_t refresh_rate_hz), TP_ARGS(crtc_index, refresh_rate_ns, refresh_rate_hz), @@ -703,6 +704,7 @@ TRACE_EVENT(amdgpu_refresh_rate_track, __entry->refresh_rate_hz, __entry->refresh_rate_ns) ); +#endif TRACE_EVENT(dcn_fpu, TP_PROTO(bool begin, const char *function, const int line, const int recursion_depth), diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 416b9a4042b0e..c4c39ba20b734 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -654,6 +654,9 @@ /* ktime_get_real_seconds() is available */ #define HAVE_KTIME_GET_REAL_SECONDS 1 +/* ktime_t is union */ +/* #undef HAVE_KTIME_IS_UNION */ + /* kvcalloc() is available */ #define HAVE_KVCALLOC 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 95ba8616377b0..264822df9882d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -140,6 +140,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE AC_AMDGPU_PM_SUSPEND_VIA_FIRMWARE AC_AMDGPU_SYSFS_EMIT + AC_AMDGPU_KTIME_IS_UNION AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-is-union.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-is-union.m4 new file mode 100644 index 0000000000000..0bd3f631e535f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ktime-is-union.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v4.18-rc1-35-ga8802d97e733 +dnl # ktime: Get rid of the union +dnl # +AC_DEFUN([AC_AMDGPU_KTIME_IS_UNION], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_t t; + t.tv64 = 0; + ], [ + AC_DEFINE(HAVE_KTIME_IS_UNION, 1, + [ktime_t is union]) + ]) + ]) +]) From f6c2dc3b54781c40f207f686fc9ba84fce9bd8f1 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 6 Apr 2021 16:26:22 +0800 Subject: [PATCH 0468/2653] drm/amdkcl: access resv field using amdkcl_ttm_resvp This is caused by "drm/amdgpu: reserve fence slot to update page table" v5.11-2904-gf63da9ae7584 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index db141728911fa..ce400d3bb70bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2999,7 +2999,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, value = 0; } - r = dma_resv_reserve_fences(root->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&root->tbo), 1); if (r) { pr_debug("failed %d to reserve fence slot\n", r); goto error_unlock; From 3785ae59f925ddc9630e2f249699144b1fdd1ced Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 7 Apr 2021 14:56:34 +0800 Subject: [PATCH 0469/2653] drm/amdkcl: wrap the code under DEFINE_DEBUGFS_ATTRIBUTE This is caused by "drm/amd/display: Add MST capability to trigger_hotplug interface" v5.11-2937-gd39b43894f55 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 7dbcb04298c1c..492980f205507 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3887,6 +3887,7 @@ static int mst_topo_show(struct seq_file *m, void *unused) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE /* * Sets trigger hpd for MST topologies. * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. @@ -3960,7 +3961,7 @@ static int trigger_hpd_mst_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, trigger_hpd_mst_set, "%llu\n"); - +#endif /* * Sets the force_timing_sync debug option from the given string. From ea3061d76c71f43529ef0f1fd0edf6c907b7b92d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 7 Apr 2021 16:15:49 +0800 Subject: [PATCH 0470/2653] drm/amdkcl: wrap the code under DEFINE_DEBUGFS_ATTRIBUTE This is caused by "drm/amd/display: Add debugfs entry for LTTPR register status" v5.11-2928-g4721d0678f7c Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Change-Id: I84809cf9dabb0b697c76bb8bd24e9e043e532b65 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 492980f205507..be7af57598a4f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -571,6 +571,7 @@ static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, return result; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE static int dp_lttpr_status_show(struct seq_file *m, void *unused) { struct drm_connector *connector = m->private; @@ -605,6 +606,7 @@ static int dp_lttpr_status_show(struct seq_file *m, void *unused) seq_puts(m, "\n"); return 0; } +#endif static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, size_t size, loff_t *pos) @@ -2915,7 +2917,9 @@ static ssize_t hdmi_cec_state_write(struct file *f, const char __user *buf, DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); +#endif DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); DEFINE_SHOW_ATTRIBUTE(internal_display); DEFINE_SHOW_ATTRIBUTE(odm_combine_segments); @@ -3035,7 +3039,9 @@ static const struct { } dp_debugfs_entries[] = { {"link_settings", &dp_link_settings_debugfs_fops}, {"phy_settings", &dp_phy_settings_debugfs_fop}, +#ifdef DEFINE_DEBUGFS_ATTRIBUTE {"lttpr_status", &dp_lttpr_status_fops}, +#endif {"test_pattern", &dp_phy_test_pattern_fops}, {"hdcp_sink_capability", &hdcp_sink_capability_fops}, {"sdp_message", &sdp_message_fops}, From 25318072e79c5f1324faed047f1909984ff9e98b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 9 Apr 2021 11:01:14 +0800 Subject: [PATCH 0471/2653] drm/amdkcl: fix pytorch test memory page fault Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index ce400d3bb70bf..27f928b8fd010 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1264,6 +1264,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, uint64_t flags; bool uncached; int r; + struct amdgpu_device *bo_adev; amdgpu_sync_create(&sync); if (clear) { @@ -1313,8 +1314,6 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, } if (bo) { - struct amdgpu_device *bo_adev; - flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); if (amdgpu_bo_encrypted(bo)) @@ -1357,6 +1356,18 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, amdgpu_gmc_get_vm_pte(adev, vm, bo, mapping->flags, &update_flags); + if (adev != bo_adev && + !(update_flags & AMDGPU_PTE_SYSTEM) && + !mapping->bo_va->is_xgmi) { + if (amdgpu_device_is_peer_accessible(bo_adev, adev)) { + update_flags |= AMDGPU_PTE_SYSTEM; + vram_base = bo_adev->gmc.aper_base; + } else { + DRM_DEBUG_DRIVER("Failed to map the VRAM for peer device access.\n"); + return -EINVAL; + } + } + trace_amdgpu_vm_bo_update(mapping); r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb, From 45e2c6aab989423dc73afeb158bebc97f4f519cd Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 13 Apr 2021 13:10:01 +0800 Subject: [PATCH 0472/2653] drm/amdkcl: wrap the code under DEFINE_DEBUGFS_ATTRIBUTE This is caused by "drm/amd/display: Add debugfs to repress HPD and HPR_RX IRQs" v5.11-2975-g14bc8d04dd21 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index be7af57598a4f..ee87ae3ee26f2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -4004,6 +4004,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, #endif +#ifdef DEFINE_DEBUGFS_ATTRIBUTE /* * Disables all HPD and HPD RX interrupt handling in the * driver when set to 1. Default is 0. @@ -4033,6 +4034,7 @@ static int disable_hpd_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, disable_hpd_set, "%llu\n"); +#endif /* * Prints hardware capabilities. These are used for IGT testing. From 99d5ce3d0ff529eb9eca917f76733ffc2c622892 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Thu, 15 Apr 2021 14:03:09 +0800 Subject: [PATCH 0473/2653] drm/amdgpu: use ratelimited print in sdma4 interrupt dev_*_ratelimited printing will avoid dmesg flush. Signed-off-by: Feifei Xu Acked-by: Kent Russell --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 919de02efb0ef..64d7093c5feb0 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -2171,7 +2171,7 @@ static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev, instance = sdma_v4_0_irq_id_to_seq(entry->client_id); if (instance < 0 || instance >= adev->sdma.num_instances) { - dev_err(adev->dev, "sdma instance invalid %d\n", instance); + dev_err_ratelimited(adev->dev, "sdma instance invalid %d\n", instance); return -EINVAL; } From 24fbd9d7b7e0cc6c90fb197c605a65f2b5685dd4 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Tue, 20 Apr 2021 15:53:54 +0800 Subject: [PATCH 0474/2653] drm/amd/amdgpu: Add missing bo size setting for bo_create MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add missing bp.bo_ptr_size setting in amdgpu_gem_prime_import_sg_table Signed-off-by: Chengming Gui Reviewed-by: Christian König Reviewed-by: Guchun Chen Change-Id: Ibe8ed71e797c12587684b2604c76e513adf98803 --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index bd3766490cf1d..30b891c50e310 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -603,6 +603,7 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, bp.flags = 0; bp.type = ttm_bo_type_sg; bp.resv = resv; + bp.bo_ptr_size = sizeof(struct amdgpu_bo); dma_resv_lock(resv, NULL); ret = amdgpu_bo_create(adev, &bp, &bo); if (ret) From cf7828f55f40da530f0a6f170b17b8e65256b0e9 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 16 Apr 2021 15:53:12 +0800 Subject: [PATCH 0475/2653] drm/amdkcl: replace vm parameter with drm_priv This is caused by "drm/amdkfd: Use drm_priv to pass VM from KFD to amdgpu" v5.11-3019-g9be47f808bf7 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index d52e0f38eef1c..88ab20909ce39 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -135,7 +135,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, } r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf, ipc_obj, - va_addr, pdd->vm, + va_addr, pdd->drm_priv, (struct kgd_mem **)&mem, &size, mmap_offset); if (r) @@ -248,7 +248,7 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, } mem = (struct kgd_mem *)kfd_bo->mem; - r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->kgd, pdd->vm, mem, + r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->kgd, pdd->drm_priv, mem, &ipc_obj); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index d9856191ab7eb..ceabdb3680a64 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -208,7 +208,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) if (ret) goto alloc_gtt_mem_failure; - ret = amdgpu_amdkfd_rlc_spm_acquire(kgd, pdd->vm, + ret = amdgpu_amdkfd_rlc_spm_acquire(kgd, pdd->drm_priv, pdd->spm_cntr->gpu_addr, pdd->spm_cntr->ring_size); /* @@ -259,7 +259,7 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) flush_work(&pdd->spm_work); wake_up_all(&pdd->spm_cntr->spm_buf_wq); - amdgpu_amdkfd_rlc_spm_release(kgd, pdd->vm); + amdgpu_amdkfd_rlc_spm_release(kgd, pdd->drm_priv); amdgpu_amdkfd_free_gtt_mem(kgd, pdd->spm_cntr->spm_obj); spin_lock_irqsave(&pdd->spm_irq_lock, flags); From b58fed304fb47fc31b06ea455af3badbaf5a0864 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 24 Feb 2020 21:17:30 -0500 Subject: [PATCH 0476/2653] drm/amdkcl: move kcl part for hmm into amdgpu_mn Signed-off-by: Flora Cui Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 49 +++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 6621f0447d559..62856f6e3d949 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -818,6 +818,21 @@ void amdgpu_hmm_unregister(struct amdgpu_bo *bo) bo->notifier.mm = NULL; } +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT +/* flags used by HMM internal, not related to CPU/GPU PTE flags */ +static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = { + (1 << 0), /* HMM_PFN_VALID */ + (1 << 1), /* HMM_PFN_WRITE */ + 0 /* HMM_PFN_DEVICE_PRIVATE */ +}; + +static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { + 0xfffffffffffffffeUL, /* HMM_PFN_ERROR */ + 0, /* HMM_PFN_NONE */ + 0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */ +}; +#endif + int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, void *owner, struct page **pages, @@ -841,10 +856,20 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, } hmm_range->notifier = notifier; +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + hmm_range->flags = hmm_range_flags; + hmm_range->values = hmm_range_values; + hmm_range->pfn_shift = PAGE_SHIFT; + hmm_range->default_flags = hmm_range_flags[HMM_PFN_VALID]; + if (!readonly) + hmm_range->default_flags |= hmm_range->flags[HMM_PFN_WRITE]; + hmm_range->pfns = (uint64_t *)pfns; +#else hmm_range->default_flags = HMM_PFN_REQ_FAULT; if (!readonly) hmm_range->default_flags |= HMM_PFN_REQ_WRITE; hmm_range->hmm_pfns = pfns; +#endif hmm_range->start = start; end = start + npages * PAGE_SIZE; hmm_range->dev_private_owner = owner; @@ -860,8 +885,16 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, retry: hmm_range->notifier_seq = mmu_interval_read_begin(notifier); r = hmm_range_fault(hmm_range); +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + if (unlikely(r <= 0)) { +#else if (unlikely(r)) { +#endif +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + if ((r == 0 || r == -EBUSY) && !time_after(jiffies, timeout)) +#else if (r == -EBUSY && !time_after(jiffies, timeout)) +#endif goto retry; goto out_free_pfns; } @@ -881,7 +914,19 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, * the notifier_lock, and mmu_interval_read_retry() must be done first. */ for (i = 0; pages && i < npages; i++) +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + pages[i] = hmm_device_entry_to_page(hmm_range, hmm_range->pfns[i]); + if (unlikely(!pages[i])) { + pr_err("Page fault failed for pfn[%lu] = 0x%llx\n", + i, hmm_range->pfns[i]); + r = -ENOMEM; + + goto out_free_pfns; + } + +#else pages[i] = hmm_pfn_to_page(pfns[i]); +#endif *phmm_range = hmm_range; @@ -903,7 +948,11 @@ bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range) r = mmu_interval_read_retry(hmm_range->notifier, hmm_range->notifier_seq); +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + kvfree(hmm_range->pfns); +#else kvfree(hmm_range->hmm_pfns); +#endif kfree(hmm_range); return r; From 429f2de6123126316439f61ea48ea6971f13d566 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 6 Apr 2021 11:42:37 +0800 Subject: [PATCH 0477/2653] drm/amdkcl: adapt to dev_pagemap->range update Signed-off-by: Flora Cui Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 27 ++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 79251f22b7022..d31f56e92033d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -206,7 +206,11 @@ svm_migrate_copy_done(struct amdgpu_device *adev, struct dma_fence *mfence) unsigned long svm_migrate_addr_to_pfn(struct amdgpu_device *adev, unsigned long addr) { +#ifdef HAVE_DEV_PAGEMAP_RANGE return (addr + adev->kfd.pgmap.range.start) >> PAGE_SHIFT; +#else + return (addr + adev->kfd.dev->pgmap.res.start) >> PAGE_SHIFT; +#endif } static void @@ -236,7 +240,12 @@ svm_migrate_addr(struct amdgpu_device *adev, struct page *page) unsigned long addr; addr = page_to_pfn(page) << PAGE_SHIFT; +#ifdef HAVE_DEV_PAGEMAP_RANGE return (addr - adev->kfd.pgmap.range.start); +#else + return (addr - adev->kfd.dev->pgmap.res.start); +#endif + } static struct page * @@ -1037,20 +1046,34 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev) * should remove reserved size */ size = ALIGN(adev->gmc.real_vram_size, 2ULL << 20); +#ifdef HAVE_DEVICE_COHERENT if (adev->gmc.xgmi.connected_to_cpu) { +#ifdef HAVE_DEV_PAGEMAP_RANGE + pgmap->nr_range = 1; pgmap->range.start = adev->gmc.aper_base; pgmap->range.end = adev->gmc.aper_base + adev->gmc.aper_size - 1; +#else + pgmap->res.start = adev->gmc.aper_base; + pgmap->res.end = adev->gmc.aper_base + adev->gmc.aper_size - 1; +#endif pgmap->type = MEMORY_DEVICE_COHERENT; - } else { + } else +#endif + { res = devm_request_free_mem_region(adev->dev, &iomem_resource, size); if (IS_ERR(res)) return PTR_ERR(res); +#ifdef HAVE_DEV_PAGEMAP_RANGE + pgmap->nr_range = 1; pgmap->range.start = res->start; pgmap->range.end = res->end; +#else + pgmap->res.start = res->start; + pgmap->res.end = res->end; +#endif pgmap->type = MEMORY_DEVICE_PRIVATE; } - pgmap->nr_range = 1; pgmap->ops = &svm_migrate_pgmap_ops; pgmap->owner = SVM_ADEV_PGMAP_OWNER(adev); pgmap->flags = 0; From 6ee86d97693a35099dd052793f2d0b2272ffa0ff Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 6 Apr 2021 11:46:35 +0800 Subject: [PATCH 0478/2653] drm/amdkcl: enable HSA_AMD_SVM in dkms package Signed-off-by: Flora Cui Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 5 +++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/svm.m4 | 21 +++++++++++++++++++++ 4 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/svm.m4 diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index cfe73b92bcad9..4fc3b8e5ba5a4 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -158,6 +158,11 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 +ifeq ($(call _is_kcl_macro_defined,HAVE_HSA_AMD_SVM_ENABLED),y) +export CONFIG_HSA_AMD_SVM=y +subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM +endif + export CONFIG_DRM_AMD_DC_HDCP=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c4c39ba20b734..703e254dacb0e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -609,6 +609,9 @@ /* hmm_range_fault() wants 1 arg */ #define HAVE_HMM_RANGE_FAULT_1ARG 1 +/* dev_pagemap->owner is available */ +#define HAVE_HSA_AMD_SVM_ENABLED 1 + /* struct i2c_lock_operations is defined */ #define HAVE_I2C_LOCK_OPERATIONS_STRUCT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 264822df9882d..479bc3938e10a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -67,6 +67,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX AC_AMDGPU_DEV_PAGEMAP + AC_AMDGPU_HSA_AMD_SVM AC_AMDGPU_DOWN_READ_KILLABLE AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED diff --git a/drivers/gpu/drm/amd/dkms/m4/svm.m4 b/drivers/gpu/drm/amd/dkms/m4/svm.m4 new file mode 100644 index 0000000000000..ef2c930e21391 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/svm.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # v5.6-rc3-15-g800bb1c8dc80 mm: handle multiple owners of device private pages in migrate_vma +dnl # v5.6-rc3-14-gf894ddd5ff01 memremap: add an owner field to struct dev_pagemap +dnl # +AC_DEFUN([AC_AMDGPU_HSA_AMD_SVM], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #if !IS_ENABLED(CONFIG_DEVICE_PRIVATE) + #error "DEVICE_PRIVATE is a must for svm support" + #endif + ], [ + struct dev_pagemap *pm = NULL; + pm->owner = NULL; + ], [ + AC_DEFINE(HAVE_HSA_AMD_SVM_ENABLED, 1, + [dev_pagemap->owner is available]) + ]) + ]) +]) + From 53313e4ef2846f17baf21e5b394d3ed404561329 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 6 Apr 2021 14:10:59 +0800 Subject: [PATCH 0479/2653] drm/amdkcl: test for migrate_vma->pgmap_owner kernel 5.8 doesnot have migrate_vma.pgmap_owner, it uses migrate_vma.src_owner=NULL for system memory and migrate_vma.src_ovner=adev for device memory. Kernel 5.9 and 5.11 add migrate_vma.pgmap_owner, and migrate_vma.flags to distinguish system memory or device memory. Signed-off-by: Flora Cui Signed-off-by: Philip Yang Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 9 +++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/svm.m4 | 17 +++++++++++++++++ 3 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index d31f56e92033d..0585e227c97bb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -413,8 +413,12 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange, migrate.vma = vma; migrate.start = start; migrate.end = end; +#ifdef HAVE_MIGRATE_VMA_PGMAP_OWNER migrate.flags = MIGRATE_VMA_SELECT_SYSTEM; migrate.pgmap_owner = SVM_ADEV_PGMAP_OWNER(adev); +#else + migrate.src_owner = NULL; +#endif buf = kvcalloc(npages, 2 * sizeof(*migrate.src) + sizeof(uint64_t) + sizeof(dma_addr_t), @@ -712,11 +716,15 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, migrate.vma = vma; migrate.start = start; migrate.end = end; +#ifdef HAVE_MIGRATE_VMA_PGMAP_OWNER migrate.pgmap_owner = SVM_ADEV_PGMAP_OWNER(adev); if (adev->gmc.xgmi.connected_to_cpu) migrate.flags = MIGRATE_VMA_SELECT_DEVICE_COHERENT; else migrate.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE; +#else + migrate.src_owner = SVM_ADEV_PGMAP_OWNER(adev); +#endif buf = kvcalloc(npages, 2 * sizeof(*migrate.src) + sizeof(uint64_t) + sizeof(dma_addr_t), @@ -1077,6 +1085,7 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev) pgmap->ops = &svm_migrate_pgmap_ops; pgmap->owner = SVM_ADEV_PGMAP_OWNER(adev); pgmap->flags = 0; + /* Device manager releases device-specific resources, memory region and * pgmap when driver disconnects from device. */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 703e254dacb0e..50c03bd2ddcbd 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -738,6 +738,9 @@ /* mem_encrypt_active() is available */ #define HAVE_MEM_ENCRYPT_ACTIVE 1 +/* migrate_vma->pgmap_owner is available */ +#define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 + /* mmgrab() is available */ #define HAVE_MMGRAB 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/svm.m4 b/drivers/gpu/drm/amd/dkms/m4/svm.m4 index ef2c930e21391..0deabfae97260 100644 --- a/drivers/gpu/drm/amd/dkms/m4/svm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/svm.m4 @@ -1,3 +1,18 @@ +dnl # +dnl # v5.8-rc4-7-g5143192cd410 mm/migrate: add a flags parameter to migrate_vma +dnl # +AC_DEFUN([AC_AMDGPU_MIGRATE_VMA_PGMAP_OWNER], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct migrate_vma *migrate = NULL; + migrate->pgmap_owner = NULL; + ], [ + AC_DEFINE(HAVE_MIGRATE_VMA_PGMAP_OWNER, 1, + [migrate_vma->pgmap_owner is available]) + ]) +]) + dnl # dnl # v5.6-rc3-15-g800bb1c8dc80 mm: handle multiple owners of device private pages in migrate_vma dnl # v5.6-rc3-14-gf894ddd5ff01 memremap: add an owner field to struct dev_pagemap @@ -15,6 +30,8 @@ AC_DEFUN([AC_AMDGPU_HSA_AMD_SVM], [ ], [ AC_DEFINE(HAVE_HSA_AMD_SVM_ENABLED, 1, [dev_pagemap->owner is available]) + + AC_AMDGPU_MIGRATE_VMA_PGMAP_OWNER ]) ]) ]) From 081503c845561dc6f15fef0eeb6521a441e886f1 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 19 Apr 2021 13:12:39 +0800 Subject: [PATCH 0480/2653] drm/amdkcl: direct include memremap.h for legacy os This is caused by "drm/amdkfd: register HMM device private zone" v5.11-3037-g2f833caf32eb Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 6b478bdaa3e5c..b2d2439da722c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -47,6 +47,7 @@ #include #include #include +#include #include "amdgpu_amdkfd.h" #include "amd_shared.h" From 00d04a6d5acbbf8c87508e562037be5d81c0f590 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 19 Apr 2021 13:52:15 +0800 Subject: [PATCH 0481/2653] drm/amdkcl: wrap the code under HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED This is caused by "drm/amdkfd: register svm range" v5.11-3025-gcdc3d25724fd Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index b2d2439da722c..39d7df89930c1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -909,7 +909,9 @@ struct kfd_process_device { struct svm_range_list { struct mutex lock; +#ifdef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED struct rb_root_cached objects; +#endif struct list_head list; struct work_struct deferred_list_work; struct list_head deferred_range_list; From ced3b59346f784735dfbb3bc37e562356c7f82a2 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 20 Apr 2021 10:21:04 +0800 Subject: [PATCH 0482/2653] drm/amdkcl: fix autoconf test for svm config Signed-off-by: Flora Cui Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/svm.m4 | 30 +++++++++++++-------------- 3 files changed, 16 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 index 228e66022b959..5137132996950 100644 --- a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -15,6 +15,8 @@ AC_DEFUN([AC_AMDGPU_HMM_RANGE_FAULT], [ [hmm remove the customizable pfn format]) AC_DEFINE(HAVE_HMM_RANGE_FAULT_1ARG, 1, [hmm_range_fault() wants 1 arg]) + + AC_AMDGPU_HSA_AMD_SVM ], [ dnl # dnl # v5.6-rc3-21-g6bfef2f91945 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 479bc3938e10a..264822df9882d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -67,7 +67,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX AC_AMDGPU_DEV_PAGEMAP - AC_AMDGPU_HSA_AMD_SVM AC_AMDGPU_DOWN_READ_KILLABLE AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED diff --git a/drivers/gpu/drm/amd/dkms/m4/svm.m4 b/drivers/gpu/drm/amd/dkms/m4/svm.m4 index 0deabfae97260..dbcd257ba1662 100644 --- a/drivers/gpu/drm/amd/dkms/m4/svm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/svm.m4 @@ -18,21 +18,19 @@ dnl # v5.6-rc3-15-g800bb1c8dc80 mm: handle multiple owners of device private pag dnl # v5.6-rc3-14-gf894ddd5ff01 memremap: add an owner field to struct dev_pagemap dnl # AC_DEFUN([AC_AMDGPU_HSA_AMD_SVM], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - #if !IS_ENABLED(CONFIG_DEVICE_PRIVATE) - #error "DEVICE_PRIVATE is a must for svm support" - #endif - ], [ - struct dev_pagemap *pm = NULL; - pm->owner = NULL; - ], [ - AC_DEFINE(HAVE_HSA_AMD_SVM_ENABLED, 1, - [dev_pagemap->owner is available]) - - AC_AMDGPU_MIGRATE_VMA_PGMAP_OWNER - ]) - ]) + AC_KERNEL_TRY_COMPILE([ + #include + #if !IS_ENABLED(CONFIG_DEVICE_PRIVATE) + #error "DEVICE_PRIVATE is a must for svm support" + #endif + ], [ + struct dev_pagemap *pm = NULL; + pm->owner = NULL; + ], [ + AC_DEFINE(HAVE_HSA_AMD_SVM_ENABLED, 1, + [dev_pagemap->owner is available]) + + AC_AMDGPU_MIGRATE_VMA_PGMAP_OWNER + ]) ]) From c222ac49c028ed1ef73154be6799596ad2cab651 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 14 Apr 2021 12:19:39 -0500 Subject: [PATCH 0483/2653] drm/amdgpu: Use VRAM Mgr api's to export SG Tables Use api's exported by VRAM Mgr (amdgpu_vram_mgr.c) to build and export SG Tables for access by peer PCIe devices. These api's allow a VRAM buffer object to be partitioned into multiple non-overlapping segments. For example one could partition a VRAM buffer into two segments, one serving as SRC buffer while the other serves as DST buffer. Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 7ddc5f2fb768f..d276281d3bcaf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2497,6 +2497,7 @@ int amdgpu_amdkfd_gpuvm_get_sg_table(struct kgd_dev *kgd, * Walk down system memory pointed by BO while * Updating Scatterlist nodes with system memory info */ + sg = kmalloc(sizeof(*sg), GFP_KERNEL); if (!sg) { ret = -ENOMEM; From b9371a06805d67de6c7aeb3b9edd75a9049d47d9 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 21 Apr 2021 13:19:15 +0800 Subject: [PATCH 0484/2653] drm/amdkcl: fix missing {} in amdgpu_hmm_range_get_pages Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 62856f6e3d949..9a68c36d7df98 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -913,7 +913,7 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, * hmm_range_fault() fails. FIXME: The pages cannot be touched outside * the notifier_lock, and mmu_interval_read_retry() must be done first. */ - for (i = 0; pages && i < npages; i++) + for (i = 0; pages && i < npages; i++) { #ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT pages[i] = hmm_device_entry_to_page(hmm_range, hmm_range->pfns[i]); if (unlikely(!pages[i])) { @@ -927,6 +927,7 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, #else pages[i] = hmm_pfn_to_page(pfns[i]); #endif + } *phmm_range = hmm_range; From baaeec2f89b143690aaa6453fd65c9894bbc3307 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 21 Apr 2021 10:57:09 +0800 Subject: [PATCH 0485/2653] drm/amdkcl: wrap the code under HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE This is caused by "drm/amd/display: update hdcp display using correct CP type." v5.11-3068-g2b39a66dfe7b Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Signed-off-by: Ma Jun Change-Id: I8c6650ceb98679c6e708d7b8d8380634a279fb99 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index 4276b99d24a2c..279f1226c3c64 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -579,6 +579,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) link->adjust.hdcp1.disable = 0; hdcp_w->encryption_status[display->index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP %d, type %d\n", aconnector->base.index, (!!aconnector->base.state) ? aconnector->base.state->content_protection : -1, @@ -593,6 +594,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) drm_connector_put(&hdcp_w->aconnector[conn_index]->base); hdcp_w->aconnector[conn_index] = aconnector; process_output(hdcp_w); +#endif } /** From 7e994fbe84d618180c2a4dd231100af0fff6428f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Sun, 25 Apr 2021 11:10:48 +0800 Subject: [PATCH 0486/2653] drm/amdkcl: adapt code to access format field of struct drm_framebuffer This is caused by "drm/amd/display: Reject non-zero src_y and src_x for video planes" v5.11-3116-g7af71c0752f0 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Signed-off-by: Ma Jun Change-Id: Ic7b7718302c27d2bf2193760407933401c923f48 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 9 +++++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index cfcc49717ddbc..76441abb585b0 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5928,7 +5928,6 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, break; } - plane_info->visible = true; plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index e88301810443e..629282825bf8d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1188,8 +1188,13 @@ int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, */ if (((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) && - (state->fb && state->fb->format->format == DRM_FORMAT_NV12 && - (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0))) + (state->fb && +#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT + state->fb->pixel_format == DRM_FORMAT_NV12 && +#else + state->fb->format->format == DRM_FORMAT_NV12 && +#endif + (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0))) return -EINVAL; scaling_info->src_rect.width = state->src_w >> 16; From fdd8cf95cea55dffe2fba8b99883c2f184b5d8b0 Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Wed, 21 Apr 2021 13:34:01 -0400 Subject: [PATCH 0487/2653] drm/amdkcl: test for is_smca_umc_v2 symbol Test if is_smca_umc_v2 symbol is available or not. This symbol is needed for page retirement handling on Aldebaran. Signed-off-by: Mukul Joshi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 2 files changed, 14 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 b/drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 new file mode 100644 index 0000000000000..28eda1decdae2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # +dnl # is_smca_umc_v2() +dnl # +AC_DEFUN([AC_AMDGPU_CHECK_SMCA_UMC_V2], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([is_smca_umc_v2], + [arch/x86/kernel/cpu/mce/amd.c], [ + AC_DEFINE(HAVE_SMCA_UMC_V2, 1, + [is_smca_umc_v2() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 264822df9882d..3e82c5e341fb8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -141,6 +141,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PM_SUSPEND_VIA_FIRMWARE AC_AMDGPU_SYSFS_EMIT AC_AMDGPU_KTIME_IS_UNION + AC_AMDGPU_CHECK_SMCA_UMC_V2 AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON From a2b822d66e604cd1a7c375e8234418d1c913ab31 Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Wed, 21 Apr 2021 13:37:06 -0400 Subject: [PATCH 0488/2653] drm/amdgpu: Register bad page handler for Aldebaran On Aldebaran, GPU driver will handle bad page retirement even though UMC is host managed. As a result, register a bad page retirement handler on the mce notifier chain to retire bad pages on Aldebaran. Signed-off-by: Mukul Joshi Reviewed-By: John Clements Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 1e31ef5592f22..a9522b845249f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -131,6 +131,16 @@ const char *get_ras_block_str(struct ras_common_if *ras_block) #define BYPASS_ALLOCATED_ADDRESS 0x0 #define BYPASS_INITIALIZATION_ADDRESS 0x1 +#ifdef HAVE_SMCA_UMC_V2 +#define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF) +#define GET_UMC_INST_NIBBLE(m) (((m) >> 20) & 0xF) +#define GET_CHAN_INDEX_NIBBLE(m) (((m) >> 12) & 0xF) +#define GPU_ID_OFFSET 8 + +static bool notifier_registered = false; +static void amdgpu_register_bad_pages_mca_notifier(void); +#endif + enum amdgpu_ras_retire_page_reservation { AMDGPU_RAS_RETIRE_PAGE_RESERVED, AMDGPU_RAS_RETIRE_PAGE_PENDING, @@ -3675,10 +3685,13 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info) INIT_DELAYED_WORK(&con->page_retirement_dwork, amdgpu_ras_do_page_retirement); amdgpu_ras_ecc_log_init(&con->umc_ecc_log); #ifdef CONFIG_X86_MCE_AMD +#ifdef HAVE_SMCA_UMC_V2 if ((adev->asic_type == CHIP_ALDEBARAN) && (adev->gmc.xgmi.connected_to_cpu)) amdgpu_register_bad_pages_mca_notifier(adev); #endif +#endif + return 0; free: @@ -4671,6 +4684,7 @@ void amdgpu_release_ras_context(struct amdgpu_device *adev) } #ifdef CONFIG_X86_MCE_AMD +#ifdef HAVE_SMCA_UMC_V2 static struct amdgpu_device *find_adev(uint32_t node_id) { int i; @@ -4771,6 +4785,7 @@ static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev) } } #endif +#endif struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev) { From 7d94390f5ee8ff0e7b286fe4664c63724d161862 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 27 Apr 2021 11:06:29 +0800 Subject: [PATCH 0489/2653] drm/amdkcl: update config.h Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 50c03bd2ddcbd..81c902cba8bce 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -828,6 +828,9 @@ /* whether si_mem_available() is available */ #define HAVE_SI_MEM_AVAILABLE 1 +/* is_smca_umc_v2() is available */ +/* #undef HAVE_SMCA_UMC_V2 */ + /* strscpy() is available */ #define HAVE_STRSCPY 1 From 060bff4505ce23271352819b67885fe5e9dc387b Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Thu, 29 Apr 2021 16:58:17 +0800 Subject: [PATCH 0490/2653] drm/amdkcl: fix sg to page arrays callback for legacy OS To call the legacy drm_prime_sg_to_page_addr_arrays, the 2nd parameter should be page array instead of NULL pointer Otherwise, the page fault will be triggered Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- include/kcl/kcl_drm_prime.h | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/include/kcl/kcl_drm_prime.h b/include/kcl/kcl_drm_prime.h index 7f02b6c95d10c..8f207f1f44b91 100644 --- a/include/kcl/kcl_drm_prime.h +++ b/include/kcl/kcl_drm_prime.h @@ -12,8 +12,19 @@ static inline int drm_prime_sg_to_dma_addr_array(struct sg_table *sgt, dma_addr_t *addrs, int max_entries) { +#ifdef HAVE_TTM_SG_TT_INIT return drm_prime_sg_to_page_addr_arrays(sgt, NULL, addrs, max_entries); - -} +#else + /* + * the page array stands right next to dma address array, + * so get the page array pointer directly by max_entries offset + * refer to ttm_sg_tt_init() for initial array allocation and + * c67e62790f5c drm/prime: split array import functions v4 for + * the change to drm_prime_sg_to_page_addr_arrays() + */ + struct page **pages = (void*)addrs - max_entries; + return drm_prime_sg_to_page_addr_arrays(sgt, pages, addrs, max_entries); #endif +} +#endif /* HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY */ #endif From a8a59d670b69170f64ae7a2149cbcc79728c88e5 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 30 Apr 2021 14:56:46 +0800 Subject: [PATCH 0491/2653] drm/amdkcl: fake hmm_pfn_to_page() Suggested-by: Felix Kuehling Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 17 +++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 14 -------------- 3 files changed, 21 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 9a68c36d7df98..1fada0f022dc0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -820,13 +820,13 @@ void amdgpu_hmm_unregister(struct amdgpu_bo *bo) #ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT /* flags used by HMM internal, not related to CPU/GPU PTE flags */ -static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = { +const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = { (1 << 0), /* HMM_PFN_VALID */ (1 << 1), /* HMM_PFN_WRITE */ 0 /* HMM_PFN_DEVICE_PRIVATE */ }; -static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { +const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { 0xfffffffffffffffeUL, /* HMM_PFN_ERROR */ 0, /* HMM_PFN_NONE */ 0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */ @@ -915,15 +915,14 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, */ for (i = 0; pages && i < npages; i++) { #ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT - pages[i] = hmm_device_entry_to_page(hmm_range, hmm_range->pfns[i]); + pages[i] = hmm_device_entry_to_page(hmm_range, pfns[i]); if (unlikely(!pages[i])) { pr_err("Page fault failed for pfn[%lu] = 0x%llx\n", - i, hmm_range->pfns[i]); + i, pfns[i]); r = -ENOMEM; goto out_free_pfns; } - #else pages[i] = hmm_pfn_to_page(pfns[i]); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index 7d7a087899125..b70e93444fabb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -66,6 +66,23 @@ static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} #include #include +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT +/* flags used by HMM internal, not related to CPU/GPU PTE flags */ +extern const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX]; +extern const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX]; + +static inline struct page *hmm_pfn_to_page(unsigned long hmm_pfn) +{ + struct hmm_range hmm_range = { + .flags = hmm_range_flags, + .values = hmm_range_values, + .pfn_shift = PAGE_SHIFT, + }; + + return hmm_device_entry_to_page(&hmm_range, hmm_pfn); +} +#endif + int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, void *owner, struct page **pages, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 3b3ba3694c168..81bc61c4ca450 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -743,20 +743,6 @@ struct amdgpu_ttm_tt { #ifdef CONFIG_DRM_AMDGPU_USERPTR #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED -#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT -/* flags used by HMM internal, not related to CPU/GPU PTE flags */ -static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = { - (1 << 0), /* HMM_PFN_VALID */ - (1 << 1), /* HMM_PFN_WRITE */ - 0 /* HMM_PFN_DEVICE_PRIVATE */ -}; - -static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { - 0xfffffffffffffffeUL, /* HMM_PFN_ERROR */ - 0, /* HMM_PFN_NONE */ - 0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */ -}; -#endif /* * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user * memory and start HMM tracking CPU page table update From f63bfc3115fa8abbcc4c427e0b4d721c2c776b73 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 30 Apr 2021 13:58:54 +0800 Subject: [PATCH 0492/2653] drm/amdkcl: rework svm enabled dependency Signed-off-by: Flora Cui Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 6 ++++-- drivers/gpu/drm/amd/dkms/Makefile | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 6 +++--- drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 3 +-- drivers/gpu/drm/amd/dkms/m4/svm.m4 | 2 +- 5 files changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 0585e227c97bb..d4f840c5aec88 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -416,7 +416,7 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange, #ifdef HAVE_MIGRATE_VMA_PGMAP_OWNER migrate.flags = MIGRATE_VMA_SELECT_SYSTEM; migrate.pgmap_owner = SVM_ADEV_PGMAP_OWNER(adev); -#else +#elif defined(HAVE_DEV_PAGEMAP_OWNER) migrate.src_owner = NULL; #endif @@ -722,7 +722,7 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, migrate.flags = MIGRATE_VMA_SELECT_DEVICE_COHERENT; else migrate.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE; -#else +#elif defined(HAVE_DEV_PAGEMAP_OWNER) migrate.src_owner = SVM_ADEV_PGMAP_OWNER(adev); #endif @@ -1083,7 +1083,9 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev) } pgmap->ops = &svm_migrate_pgmap_ops; +#ifdef HAVE_DEV_PAGEMAP_OWNER pgmap->owner = SVM_ADEV_PGMAP_OWNER(adev); +#endif pgmap->flags = 0; /* Device manager releases device-specific resources, memory region and diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 4fc3b8e5ba5a4..b1eecc92ebfb3 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -158,7 +158,7 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 -ifeq ($(call _is_kcl_macro_defined,HAVE_HSA_AMD_SVM_ENABLED),y) +ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) export CONFIG_HSA_AMD_SVM=y subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 81c902cba8bce..69b0de5a9f633 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -61,6 +61,9 @@ /* devm_memremap_pages() wants p,p,p,p interface */ /* #undef HAVE_DEVM_MEMREMAP_PAGES_P_P_P_P */ +/* dev_pagemap->owner is available */ +#define HAVE_DEV_PAGEMAP_OWNER 1 + /* there is 'range' field within dev_pagemap structure */ #define HAVE_DEV_PAGEMAP_RANGE 1 @@ -609,9 +612,6 @@ /* hmm_range_fault() wants 1 arg */ #define HAVE_HMM_RANGE_FAULT_1ARG 1 -/* dev_pagemap->owner is available */ -#define HAVE_HSA_AMD_SVM_ENABLED 1 - /* struct i2c_lock_operations is defined */ #define HAVE_I2C_LOCK_OPERATIONS_STRUCT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 index 5137132996950..c175fd6289702 100644 --- a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -15,8 +15,6 @@ AC_DEFUN([AC_AMDGPU_HMM_RANGE_FAULT], [ [hmm remove the customizable pfn format]) AC_DEFINE(HAVE_HMM_RANGE_FAULT_1ARG, 1, [hmm_range_fault() wants 1 arg]) - - AC_AMDGPU_HSA_AMD_SVM ], [ dnl # dnl # v5.6-rc3-21-g6bfef2f91945 @@ -66,6 +64,7 @@ AC_DEFUN([AC_AMDGPU_HMM], [ AC_DEFINE(HAVE_AMDKCL_HMM_MIRROR_ENABLED, 1, [hmm support is enabled]) AC_AMDGPU_HMM_RANGE_FAULT + AC_AMDGPU_HSA_AMD_SVM ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/svm.m4 b/drivers/gpu/drm/amd/dkms/m4/svm.m4 index dbcd257ba1662..17657770988f5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/svm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/svm.m4 @@ -27,7 +27,7 @@ AC_DEFUN([AC_AMDGPU_HSA_AMD_SVM], [ struct dev_pagemap *pm = NULL; pm->owner = NULL; ], [ - AC_DEFINE(HAVE_HSA_AMD_SVM_ENABLED, 1, + AC_DEFINE(HAVE_DEV_PAGEMAP_OWNER, 1, [dev_pagemap->owner is available]) AC_AMDGPU_MIGRATE_VMA_PGMAP_OWNER From 62c4c1133d7f9da4c0104dd3a916f79ddaecc2bb Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 7 May 2021 13:59:37 +0800 Subject: [PATCH 0493/2653] drm/amdkcl: wrap the code under HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED This is caused by "drm/amdgpu: Use device specific BO size & stride check." v5.11-3225-gdf0c606a6ced Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index b696bc0c25edf..bb85b41a27078 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1196,6 +1196,7 @@ static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb) } } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static void get_block_dimensions(unsigned int block_log2, unsigned int cpp, unsigned int *width, unsigned int *height) { @@ -1278,17 +1279,16 @@ static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane (uint64_t)rfb->base.pitches[plane] / block_pitch * block_size * DIV_ROUND_UP(height, block_height); - if (rfb->base.obj[0]->size < size) { + if (drm_gem_fb_get_obj(&rfb->base, 0)->size < size) { drm_dbg_kms(rfb->base.dev, "BO size 0x%zx is less than 0x%llx required for plane %d\n", - rfb->base.obj[0]->size, size, plane); + drm_gem_fb_get_obj(&rfb->base, 0)->size, size, plane); return -EINVAL; } return 0; } - static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) { const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format); @@ -1392,6 +1392,7 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) return 0; } +#endif static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, uint64_t *tiling_flags, bool *tmz_surface, @@ -1460,6 +1461,8 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, kcl_drm_gem_fb_set_obj(&rfb->base, 0, obj); drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); + +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED /* Verify that the modifier is supported. */ if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, mode_cmd->modifier[0])) { @@ -1470,6 +1473,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, ret = -EINVAL; goto err; } +#endif ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); if (ret) @@ -1580,13 +1584,17 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags); if (drm_gem_is_imported(obj) && !(domains & AMDGPU_GEM_DOMAIN_GTT)) { drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n"); +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED drm_gem_object_put(obj); +#endif return ERR_PTR(-EINVAL); } amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); if (amdgpu_fb == NULL) { +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED drm_gem_object_put(obj); +#endif return ERR_PTR(-ENOMEM); } @@ -1594,11 +1602,16 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, mode_cmd, obj); if (ret) { kfree(amdgpu_fb); +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED drm_gem_object_put(obj); +#endif return ERR_PTR(ret); } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED drm_gem_object_put(obj); +#endif + return &amdgpu_fb->base; } From f0f00f773cdf072ed06aeed80a3a8a8ac4e10efc Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Fri, 7 May 2021 18:07:00 +0800 Subject: [PATCH 0494/2653] drm/amdkcl: export the symbol of pxm_to_node This is caused by "add ACPI SRAT parsing for topology" v2: dummy pxm_to_node() in case the symbol cannot be found by kallsyms_lookup_name() Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_numa.c | 20 ++++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 ++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 | 13 +++++++++++++ include/kcl/backport/kcl_numa_backport.h | 10 ++++++++++ 8 files changed, 51 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_numa.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 create mode 100644 include/kcl/backport/kcl_numa_backport.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index a22c482f8b7b5..f95c0c73adb27 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -11,7 +11,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ - kcl_acpi_table.o kcl_page_alloc.o kcl_drm_aperture.o + kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_numa.c b/drivers/gpu/drm/amd/amdkcl/kcl_numa.c new file mode 100644 index 0000000000000..92605529089d1 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_numa.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include + +#ifndef HAVE_PXM_TO_NODE +int (*_kcl_pxm_to_node)(int pxm); +EXPORT_SYMBOL(_kcl_pxm_to_node); + +/* Copied from include/acpi/acpi_numa.h */ +static int __kcl_pxm_to_node_stub(int pxm) +{ + return 0; +} +#endif + +void amdkcl_numa_init(void) +{ +#ifndef HAVE_PXM_TO_NODE + _kcl_pxm_to_node = amdkcl_fp_setup("pxm_to_node", __kcl_pxm_to_node_stub); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index aa767fa0aa014..feb2d6548f323 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -13,6 +13,7 @@ extern void amdkcl_perf_event_init(void); extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); extern void amdkcl_sched_init(void); +extern void amdkcl_numa_init(void); int __init amdkcl_init(void) { @@ -27,6 +28,7 @@ int __init amdkcl_init(void) amdkcl_pci_init(); amdkcl_suspend_init(); amdkcl_sched_init(); + amdkcl_numa_init(); return 0; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 2e0f765e1c88d..9e7bee1e97075 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -67,6 +67,7 @@ #include #include #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h" #include "kcl/kcl_amdgpu.h" diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 69b0de5a9f633..5f53c6094f4c6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -807,6 +807,9 @@ /* pm_suspend_via_firmware() is available */ #define HAVE_PM_SUSPEND_VIA_FIRMWARE 1 +/* pxm_to_node() is available */ +#define HAVE_PXM_TO_NODE 1 + /* remove_conflicting_framebuffers() returns int */ /* #undef HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3e82c5e341fb8..345bb2d2433cb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -142,6 +142,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SYSFS_EMIT AC_AMDGPU_KTIME_IS_UNION AC_AMDGPU_CHECK_SMCA_UMC_V2 + AC_AMDGPU_PXM_TO_NODE AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 b/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 new file mode 100644 index 0000000000000..35651096f8e2a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # v5.7-20-gf2af6d3978d7 +dnl # virtio-mem: Allow to specify an ACPI PXM as nid +dnl # +AC_DEFUN([AC_AMDGPU_PXM_TO_NODE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([pxm_to_node], + [drivers/acpi/numa/srat.c], [ + AC_DEFINE(HAVE_PXM_TO_NODE, 1, + [pxm_to_node() is available]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_numa_backport.h b/include/kcl/backport/kcl_numa_backport.h new file mode 100644 index 0000000000000..ef190c784cdbf --- /dev/null +++ b/include/kcl/backport/kcl_numa_backport.h @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#ifndef AMDKCL_NUMA_BACKPORT_H +#define AMDKCL_NUMA_BACKPORT_H + +#if !defined(HAVE_PXM_TO_NODE) +extern int _kcl_pxm_to_node(int pxm); +#define pxm_to_node _kcl_pxm_to_node +#endif + +#endif From 2d5155aee46be70dc209ccf11536c1b8bbf7543e Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Sat, 8 May 2021 11:48:26 +0800 Subject: [PATCH 0495/2653] drm/amdkcl: wrap the code of GENERIC_AFFINITY processing Disable the GENERIC_AFFINITY related code for legacy OS where ACPI 6.x is NOT supported. This is caused by "add ACPI SRAT parsing for topology" Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/acpi_srat.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 22 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/acpi_srat.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index 87494915f4fba..17ddfe4092020 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -2068,6 +2068,7 @@ static void kfd_find_numa_node_in_srat(struct kfd_node *kdev) if (pxm > max_pxm) max_pxm = pxm; break; +#ifdef HAVE_ACPI_SRAT_GENERIC_AFFINITY case ACPI_SRAT_TYPE_GENERIC_AFFINITY: gpu = (struct acpi_srat_generic_affinity *)sub_header; bdf = *((u16 *)(&gpu->device_handle[0])) << 16 | @@ -2077,6 +2078,7 @@ static void kfd_find_numa_node_in_srat(struct kfd_node *kdev) numa_node = pxm_to_node(gpu->proximity_domain); } break; +#endif default: break; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5f53c6094f4c6..d48a7edc72c7d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -13,6 +13,9 @@ /* acpi_put_table() is available */ #define HAVE_ACPI_PUT_TABLE 1 +/* struct acpi_srat_generic_affinity is available */ +#define HAVE_ACPI_SRAT_GENERIC_AFFINITY 1 + /* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ #define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi_srat.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi_srat.m4 new file mode 100644 index 0000000000000..16493b5e8d995 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/acpi_srat.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit aa475a59fff172ec858093fbc8471c0993081481 +dnl # ACPICA: ACPI 6.3: SRAT: add Generic Affinity Structure subtable +dnl # +AC_DEFUN([AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct acpi_srat_generic_affinity *p = NULL; + p->reserved = 0; + ], [ + AC_DEFINE(HAVE_ACPI_SRAT_GENERIC_AFFINITY, 1, [struct acpi_srat_generic_affinity is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 345bb2d2433cb..f1e4bc1791f84 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -143,6 +143,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTIME_IS_UNION AC_AMDGPU_CHECK_SMCA_UMC_V2 AC_AMDGPU_PXM_TO_NODE + AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON From 6fb496cbe8af9e1e9fff4dbbc3a7ba7ca9673f80 Mon Sep 17 00:00:00 2001 From: Matt Ezell Date: Wed, 12 May 2021 12:38:14 -0400 Subject: [PATCH 0496/2653] drm/amdkfd: Unlock mutex in error path of kfd_ioctl_alloc_memory_of_gpu Signed-off-by: Matt Ezell Reviewed-by: Felix Kuehling Signed-off-by: Felix Kuehling Reviewed-by: Kent Russell --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index c9d426f0c7a81..622865a15b971 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1137,7 +1137,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, err = follow_pfn(vma, args->mmap_offset, &pfn); if (err) { pr_debug("Failed to get PFN: %ld\n", err); - return err; + goto err_unlock; } flags |= KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL; flags &= ~KFD_IOC_ALLOC_MEM_FLAGS_USERPTR; @@ -1146,7 +1146,8 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, if (offset & (PAGE_SIZE - 1)) { pr_debug("Unaligned userptr address:%llx\n", offset); - return -EINVAL; + err = -EINVAL; + goto err_unlock; } cpuva = offset; } From 3c05a5ae69b8f4114ad0bc9d2af9c302875349db Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Mon, 17 May 2021 13:07:54 +0800 Subject: [PATCH 0497/2653] drm/amdgpu: disable GFX RAS on A + A platform this is a regression introduced by 0c15d459a359ff3e02e0556248fc0af17e11b178 GFX RAS should be disabled by default on A + A platform Signed-off-by: Hawking Zhang Reviewed-by: Dennis Li --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index a9522b845249f..2dd2ea658bec3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3923,9 +3923,8 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) } else { /* driver only manages a few IP blocks RAS feature * when GPU is connected cpu through XGMI */ - adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX | - 1 << AMDGPU_RAS_BLOCK__SDMA | - 1 << AMDGPU_RAS_BLOCK__MMHUB); + adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__SDMA | + 1 << AMDGPU_RAS_BLOCK__MMHUB); } /* apply asic specific settings (vega20 only for now) */ From 8554734b4ff40e769b2161e57b492ac893882db0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 12 Oct 2023 10:18:24 +0800 Subject: [PATCH 0498/2653] drm/amdkcl: fix IGT gamma test failure [why] Patch "drm: automatic legacy gamma support" removes the assignment of amdgpu_dm_crtc_funcs.gamma_set, it's ok on new kernel that drm core handled the gamma setting, but on old kernel, it results drm_mode_gamma_set_ioctl() exit with ENOSYS, then the IGT gamma test failed. [how] Bring the assignment code back to fix the failure. Change-Id: Iebdf4752e5a06fa551df18810e3da1ba52c9fba0 Reviewed-by: Flora Cui Signed-off-by: Tianci.Yin Signed-off-by: Ma Jun Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 3 +++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 13 +++++++++++++ 3 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 1c01f0e6064a1..633d6192bdac2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -540,6 +540,9 @@ amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc, static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .reset = amdgpu_dm_crtc_reset_state, .destroy = amdgpu_dm_crtc_destroy, +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL + .gamma_set = drm_atomic_helper_legacy_gamma_set, +#endif .set_config = drm_atomic_helper_set_config, .page_flip = drm_atomic_helper_page_flip, .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d48a7edc72c7d..848d2f2e56b40 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -128,6 +128,9 @@ /* drm_atomic_helper_check_plane_state() is available */ #define HAVE_DRM_ATOMIC_HELPER_CHECK_PLANE_STATE 1 +/* HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL 1 + /* drm_atomic_helper_shutdown() is available */ #define HAVE_DRM_ATOMIC_HELPER_SHUTDOWN 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 2820aaa74c3b0..e92c34e468d65 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -159,6 +159,18 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET], [ ]) ]) +dnl # +dnl # v5.10-1961-g6ca2ab8086af drm: automatic legacy gamma support +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL], [ + AC_KERNEL_CHECK_SYMBOL_EXPORT( + [drm_atomic_helper_legacy_gamma_set], [drivers/gpu/drm/drm_atomic_helper.c], [], + [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL, 1, + [HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK @@ -166,4 +178,5 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL ]) From 6969a33d0146f780e0f652277048db0642d5f094 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 18 May 2021 17:14:05 +0800 Subject: [PATCH 0499/2653] drm/amdkcl: fix the calculation of pages array based on dma array Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- include/kcl/kcl_drm_prime.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_drm_prime.h b/include/kcl/kcl_drm_prime.h index 8f207f1f44b91..2c5e972520576 100644 --- a/include/kcl/kcl_drm_prime.h +++ b/include/kcl/kcl_drm_prime.h @@ -22,7 +22,7 @@ int drm_prime_sg_to_dma_addr_array(struct sg_table *sgt, dma_addr_t *addrs, * c67e62790f5c drm/prime: split array import functions v4 for * the change to drm_prime_sg_to_page_addr_arrays() */ - struct page **pages = (void*)addrs - max_entries; + struct page **pages = (void*)((unsigned long)addrs - max_entries*sizeof(dma_addr_t)); return drm_prime_sg_to_page_addr_arrays(sgt, pages, addrs, max_entries); #endif } From 8afc2f7a09db123b6e983a16eb0a88225bf38cd6 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 May 2021 13:25:00 +0800 Subject: [PATCH 0500/2653] drm/amdkcl: wrap the code under CONFIG_DRM_AMD_DC_DSC_SUPPORT This is caused by "drm/amd/display: Initial DC support for Beige Goby" v5.11-3391-g54f910c6372e Signed-off-by: Leslie Shi --- .../amd/display/dc/resource/dcn303/dcn303_resource.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c index 3479e1eab4cd7..48218ab297e6f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c @@ -126,7 +126,9 @@ static const struct resource_caps res_cap_dcn303 = { .num_ddc = 2, .num_vmid = 16, .num_mpc_3dlut = 1, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 2, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -622,6 +624,7 @@ static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int n return &mpc30->base; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = { DSC_REG_LIST_DCN20(id) } @@ -650,6 +653,7 @@ static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ct dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif #define dwbc_regs_dcn3(id)\ [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } @@ -948,10 +952,12 @@ static void dcn303_resource_destruct(struct resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { if (pool->dscs[i] != NULL) dcn20_dsc_destroy(&pool->dscs[i]); } +#endif if (pool->mpc != NULL) { kfree(TO_DCN20_MPC(pool->mpc)); @@ -1086,7 +1092,9 @@ static struct resource_funcs dcn303_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -1362,6 +1370,7 @@ static bool dcn303_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { pool->dscs[i] = dcn303_dsc_create(ctx, i); if (pool->dscs[i] == NULL) { @@ -1370,6 +1379,7 @@ static bool dcn303_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn303_dwbc_create(ctx, pool)) { From 77af1b74b4bb4d316a6ebb1ca52d511c1fddef5b Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Wed, 19 May 2021 09:29:00 -0400 Subject: [PATCH 0501/2653] drm/amdkfd: complete indirect peer no-atomics support checks When setting no-atomics flags for a target GPU, the target should self check atomic support over root and check the source GPU's atomic endpoint support to complete the flag check and set. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 35 ++++++++++++++++------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 52a1f56804ed5..6b47832ef150a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1277,7 +1277,16 @@ static void kfd_set_iolink_no_atomics(struct kfd_topology_device *dev, if (link->iolink_type == CRAT_IOLINK_TYPE_XGMI) return; - /* check pcie support to set cpu(dev) flags for target_gpu_dev link. */ + /* checkout source dev has atomics support on root. */ + if (dev->gpu && (!dev->gpu->pci_atomic_requested || + dev->gpu->device_info->asic_family == + CHIP_HAWAII)) { + link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT | + CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT; + return; + } + + /* check target_gpu_dev is atomics capable. */ if (target_gpu_dev) { uint32_t cap; @@ -1437,17 +1446,23 @@ static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev) } } - /* Create CPU<->GPU indirect links so apply flags setting to all */ + /* Create indirect links so apply flags setting to all */ list_for_each_entry(link, &dev->p2p_link_props, list) { - cpu_dev = kfd_topology_device_by_proximity_domain( + link->flags = CRAT_IOLINK_FLAGS_ENABLED; + kfd_set_iolink_no_atomics(dev, NULL, link); + peer_dev = kfd_topology_device_by_proximity_domain( link->node_to); - if (cpu_dev && !cpu_dev->gpu) { - list_for_each_entry(cpu_link, - &cpu_dev->p2p_link_props, list) - if (cpu_link->node_to == link->node_from) { - link->flags = flag; - cpu_link->flags = cpu_flag; - } + + if (!peer_dev) + continue; + + list_for_each_entry(inbound_link, &peer_dev->p2p_link_props, + list) { + if (inbound_link->node_to != link->node_from) + continue; + + inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED; + kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link); } } } From 8b94f347c7d2ed6c9810cf7d4d9c4d90ac686f47 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 May 2021 15:53:33 +0800 Subject: [PATCH 0502/2653] drm/amdkcl: adapt code for legacy os This is caused by following commits: d9e1c5963c97 drm/amd/amdgpu: fix refcount leak 9faf262c32d3 drm/amdgpu: Add DMA mapping of GTT BOs ac89ed0789f8 drm/amdgpu: Move kfd_mem_attach outside reservation Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 8 +++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index d276281d3bcaf..7714f774b53b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -819,6 +819,7 @@ static int kfd_mem_export_dmabuf(struct kgd_mem *mem) return 0; } +#ifdef AMDKCL_AMDGPU_DMABUF_OPS static int kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, struct amdgpu_bo **bo) @@ -839,6 +840,7 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, return 0; } +#endif /* kfd_mem_attach - Add a BO to a VM * @@ -929,6 +931,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, ret = create_dmamap_sg_bo(adev, mem, &bo[i]); if (ret) goto unwind; +#ifdef AMDKCL_AMDGPU_DMABUF_OPS /* Enable acces to GTT and VRAM BOs of peer devices */ } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT || mem->domain == AMDGPU_GEM_DOMAIN_VRAM) { @@ -937,6 +940,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, if (ret) goto unwind; pr_debug("Employ DMABUF mechanism to enable peer GPU access\n"); +#endif } else { WARN_ONCE(true, "Handling invalid ATTACH request"); ret = -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 8a71c31f394a4..2367c391e6f33 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -304,10 +304,12 @@ static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfb drm_fb_helper_unregister_fbi(&rfbdev->helper); obj = drm_gem_fb_get_obj(&rfb->base, 0); - if (rfb->base.obj[0]) { + if (obj) { +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED for (i = 0; i < rfb->base.format->num_planes; i++) - drm_gem_object_put(rfb->base.obj[0]); - amdgpufb_destroy_pinned_object(rfb->base.obj[0]); + drm_gem_object_put(obj); +#endif + amdgpufb_destroy_pinned_object(obj); kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); drm_framebuffer_unregister_private(&rfb->base); drm_framebuffer_cleanup(&rfb->base); From 1e41b4c5979afb3fc88ff49bdca0f2585d2a047c Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Fri, 21 May 2021 16:14:38 +0800 Subject: [PATCH 0503/2653] drm/amdgpu: allow force enable gfx ras on A + A platform This is temporary solution to allow enable gfx ras on A + A platform by setting kernel module parameter ras_mask to 0xe. It should be removed when gfx ras is enabled by default on A + A platform Signed-off-by: Hawking Zhang Reviewed-by: John Clements Reviewed-by: Dennis Li --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 2dd2ea658bec3..661dc33d8c59b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3925,6 +3925,12 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) * when GPU is connected cpu through XGMI */ adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__SDMA | 1 << AMDGPU_RAS_BLOCK__MMHUB); + /* This is temporary workaround to leverage ras_mask + * to allow nable GFX RAS manually. Should be removed later + */ + if (amdgpu_ras_enable && + (amdgpu_ras_mask == 0xe)) + adev->ras_hw_enabled |= 1 << AMDGPU_RAS_BLOCK__GFX; } /* apply asic specific settings (vega20 only for now) */ From 3a9a46a3b6a30f540168f090c68b71772952aa78 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 26 May 2021 14:59:49 +0800 Subject: [PATCH 0504/2653] drm/amdkcl: wrap code under macro for legacy os This is caused by "drm/amdgpu: Move dmabuf attach/detach to backend_(un)bind" v5.11-3411-g6c6210ae18ba Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen drm/amdkcl: fix a define typo Signed-off-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 81bc61c4ca450..a305fab51a043 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1135,6 +1135,8 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, return r; } } else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) { +#if defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) || \ + defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) if (!ttm->sg) { struct dma_buf_attachment *attach; struct sg_table *sgt; @@ -1146,6 +1148,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, ttm->sg = sgt; } +#endif drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, ttm->num_pages); @@ -1258,11 +1261,14 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, if (gtt->userptr) { amdgpu_ttm_tt_unpin_userptr(bdev, ttm); } else if (ttm->sg && drm_gem_is_imported(gtt->gobj)) { +#if defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) || \ + defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) struct dma_buf_attachment *attach; attach = gtt->gobj->import_attach; dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); ttm->sg = NULL; +#endif } if (!gtt->bound) From c26a470c50df157084d74f22bc3d64fc76a789d4 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Tue, 8 Dec 2020 11:43:29 -0500 Subject: [PATCH 0505/2653] drm/amdgpu: fix mmu notifier release callback race exit_mmap calls MMU notifier release callback first, which schedule kfd_process_wq_release work and amdgpu_mn_destroy work, then calls unmap_vmas to unmap userptr, which calls amdgpu_mn_invalidate_range_start_hsa. kfd_process_wq_release work calls free_outstanding_kfd_bos -> amdgpu_mn_unregister to remove bo from amn->objects. amdgpu_mn_destroy work free bo nodes from amn->objects. amdgpu_mn_invalidate_range_start_hsa scans amn->objects tree to find bo. amdgpu_mn_destroy free bo nodes on the interval tree, but not free the tree. amdgpu_mn_invalidate_range_start_hsa scan the amn->objects to lookup bo node, this causes kernel BUG or NULL pointer access because bo node maybe freed. Fix: Set amn->objects tree to NULL, and remove amn from MMU notifier in amdgpu_mn_destroy before releasing adev->mn_lock. Kernel BUG backtrace: [849938.299554] BUG: unable to handle kernel paging request at [849938.314382] Call Trace: [849938.315637] amdgpu_mn_invalidate_range_start_hsa+0x55/0xc0 [amdgpu] [849938.316778] __mmu_notifier_invalidate_range_start+0x52/0x80 [849938.317627] try_to_unmap_one+0x101/0xa70 [849938.318545] ? entry_SYSCALL_64_after_hwframe+0xb9/0xca [849938.319590] ? __switch_to_asm+0x41/0x70 [849938.320434] ? __switch_to_asm+0x35/0x70 [849938.321525] ? __switch_to_asm+0x41/0x70 [849938.322676] rmap_walk_file+0xf7/0x260 [849938.323822] try_to_munlock+0x4d/0x70 [849938.324939] ? page_remove_rmap+0x350/0x350 [849938.326031] ? anon_vma_ctor+0x40/0x40 [849938.327089] ? page_get_anon_vma+0x80/0x80 [849938.328143] __munlock_isolated_page+0x26/0x60 [849938.329217] munlock_vma_page+0xff/0x110 [849938.330289] munlock_vma_pages_range+0x8d/0x3d0 [849938.331381] ? enqueue_entity+0x108/0x640 [849938.332466] ? select_idle_sibling+0x22/0x430 [849938.333560] ? enqueue_task_fair+0x7d/0x460 [849938.334671] exit_mmap+0x132/0x190 [849938.335750] ? __delayacct_add_tsk+0x183/0x1b0 [849938.336794] ? kmem_cache_free+0x18c/0x1b0 [849938.337816] mmput+0x54/0x130 [849938.338823] do_exit+0x353/0xb40 [849938.339821] do_group_exit+0x3a/0xa0 [849938.340814] get_signal+0x147/0x850 [849938.341825] do_signal+0x36/0x660 [849938.342835] ? ktime_get_ts64+0x40/0xe0 [849938.343839] exit_to_usermode_loop+0x89/0xf0 [849938.344605] do_syscall_64+0x198/0x1a0 BUG: SWDEV-262212 Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 1fada0f022dc0..d8ca2619f97cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -149,14 +149,23 @@ static void amdgpu_mn_destroy(struct work_struct *work) } kfree(node); } + +#ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED + amn->objects = RB_ROOT; +#else + amn->objects = RB_ROOT_CACHED; +#endif + up_write(&amn->lock); - mutex_unlock(&adev->mn_lock); + #ifdef HAVE_MMU_NOTIFIER_PUT mmu_notifier_put(&amn->mn); #else mmu_notifier_unregister_no_release(&amn->mn, amn->mm); mmu_notifier_call_srcu(&amn->rcu, amdgpu_mn_free); #endif + + mutex_unlock(&adev->mn_lock); } /** From 2deb4415dfbbe5be57a414206b170f151ce76ee1 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Sun, 30 May 2021 22:52:03 -0400 Subject: [PATCH 0506/2653] drm/amdgpu: unregister MMU notifier in release callback Schedule work to unregister MMU notifier in MMU release callback, if the work remove MMU notifier between invalidate_range_start and invalidate_range_end, amdgpu_mn_invalidate_range_end will not be called because the notifier is gone. This causes amn->lock is not unlocked, then amdgpu_mn_unregister hold adev->mn_lock, wait for amn->lock forever, and new process amdgpu_mn_register wait for adev->mn_lock, it is deadklock. Fix: Unregister MMU notifier in MMU notifier release callback, remove amn->work, it is not needed anymore. As a result, exit_mmap unmap outstanding userptr will not cause unnecessary queue evction and restore because MMU notifier is already removed before unmap userptr. BUG: SWDEV-262212 Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index d8ca2619f97cb..128f079102013 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -75,9 +75,6 @@ struct amdgpu_mn { struct mmu_notifier mn; enum amdgpu_mn_type type; - /* only used on destruction */ - struct work_struct work; - /* protected by adev->mn_lock */ struct hlist_node node; @@ -123,13 +120,12 @@ static void amdgpu_mn_free(struct rcu_head *rcu) /** * amdgpu_mn_destroy - destroy the MMU notifier * - * @work: previously sheduled work item + * @amn: our notifier * - * Lazy destroys the notifier from a work item + * Destroy the notifier */ -static void amdgpu_mn_destroy(struct work_struct *work) +static void amdgpu_mn_destroy(struct amdgpu_mn *amn) { - struct amdgpu_mn *amn = container_of(work, struct amdgpu_mn, work); struct amdgpu_device *adev = amn->adev; struct amdgpu_mn_node *node, *next_node; struct amdgpu_bo *bo, *next_bo; @@ -174,15 +170,14 @@ static void amdgpu_mn_destroy(struct work_struct *work) * @mn: our notifier * @mm: the mm this callback is about * - * Shedule a work item to lazy destroy our notifier. + * Destroy our notifier. */ static void amdgpu_mn_release(struct mmu_notifier *mn, struct mm_struct *mm) { struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); - INIT_WORK(&amn->work, amdgpu_mn_destroy); - schedule_work(&amn->work); + amdgpu_mn_destroy(amn); } From 831cf0857c88dfd7423363e7464438150ab1d825 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 2 Jun 2021 10:13:34 +0800 Subject: [PATCH 0507/2653] drm/amdkcl: define macro DRM_FORMAT_{XRGB/XBGR/ARGB/ABGR}16161616 for legacy os This is caused by bcd05bd9251f "drm/amd/display: Enable support for 16 bpc fixed-point framebuffers." Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_drm_fourcc.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h index 25cf40f897b23..d40688cb6422d 100644 --- a/include/kcl/kcl_drm_fourcc.h +++ b/include/kcl/kcl_drm_fourcc.h @@ -214,4 +214,17 @@ #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ #endif + +/* 64 bpp RGB */ +#ifndef DRM_FORMAT_XRGB16161616 +/* Copied from v5.11-3544-ga2fe23ecdbb7 */ +#define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ +#define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ +#endif + +#ifndef DRM_FORMAT_ARGB16161616 +#define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ +#define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ +#endif + #endif /* KCL_KCL_DRM_FOURCC_H */ From b616afa16e2b882b2b0f3c87b04b20a60f17ae28 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 2 Jun 2021 15:54:34 +0800 Subject: [PATCH 0508/2653] drm/amdkcl: add macro drm_dbg_atomic This is caused by 216502b1e930 "amd/display: convert DRM_DEBUG_ATOMIC to drm_dbg_atomic" v5.11-3568-g216502b1e930 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_drm_print.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index c51497dc79f3e..c2dac790ba1c8 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -141,6 +141,11 @@ void kcl_drm_err(const char *format, ...); void drm_dev_dbg(const struct device *dev, int category, const char *format, ...); #endif +#if !defined(drm_dbg_atomic) +#define drm_dbg_atomic(drm, fmt, ...) \ + drm_dev_dbg((drm)->dev, DRM_UT_ATOMIC, fmt, ##__VA_ARGS__) +#endif + #if !defined(drm_dbg_kms) #define drm_dbg_kms(drm, fmt, ...) \ drm_dev_dbg((drm)->dev, 0x04, fmt, ##__VA_ARGS__) From 834a2ebebf67eb707d01c08a689666f4e528b353 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Fri, 4 Jun 2021 17:17:18 +0800 Subject: [PATCH 0509/2653] drm/amdkcl: fix the _kcl_pxm_to_node func declaration As _kcl_pxm_to_node is defined as func pointer the same for the declaration format. Otherwise the page fault will happen since the address of the pointer var itself is used for calling the func. [ 284.537683] kernel tried to execute NX-protected page - exploit attempt? (uid: 0) Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- include/kcl/backport/kcl_numa_backport.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/backport/kcl_numa_backport.h b/include/kcl/backport/kcl_numa_backport.h index ef190c784cdbf..99251097a9e76 100644 --- a/include/kcl/backport/kcl_numa_backport.h +++ b/include/kcl/backport/kcl_numa_backport.h @@ -3,7 +3,7 @@ #define AMDKCL_NUMA_BACKPORT_H #if !defined(HAVE_PXM_TO_NODE) -extern int _kcl_pxm_to_node(int pxm); +extern int (*_kcl_pxm_to_node)(int pxm); #define pxm_to_node _kcl_pxm_to_node #endif From 5056b432ccc0bb051ff2235ca015e47a1e4e1f09 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Fri, 4 Jun 2021 12:51:31 -0500 Subject: [PATCH 0510/2653] drm/amdgpu: Access peer GPU VRAM BO's as DMABUF objects Current design enabling access to peer GPU's VRAM BO requires that system run with IOMMU disabled. Enabling the use of DMABUF objects relaxes this constraint i.e. access is not affected by IOMMU being ON or OFF. However, the use of DMABUF objects requires config option DMABUF_MOVE_NOTIFY to be enabled. When this config option is not SET access requests are valid only if IOMMU is OFF. Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 7714f774b53b5..8a6ddb6968a95 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -842,6 +842,38 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, } #endif +/** + * @kfd_mem_attach_vram_bo: Acquires the handle of a VRAM BO that could + * be used to enable a peer GPU access it + * + * Implementation determines if access to VRAM BO would employ DMABUF + * or Shared BO mechanism. Employ DMABUF mechanism if kernel has config + * option DMABUF_MOVE_NOTIFY enabled. Employ Shared BO mechanism if above + * config option is not set. It is important to note that a Shared BO + * cannot be used to enable peer acces if system has IOMMU enabled + * + * @TODO: ADD Check to ensure IOMMU is not enabled. Should this check + * be somewhere as this is information could be useful in other places + */ +static int kfd_mem_attach_vram_bo(struct amdgpu_device *adev, + struct kgd_mem *mem, struct amdgpu_bo **bo, + struct kfd_mem_attachment *attachment) +{ + int ret = 0; + +#ifdef CONFIG_DMABUF_MOVE_NOTIFY + attachment->type = KFD_MEM_ATT_DMABUF; + ret = kfd_mem_attach_dmabuf(adev, mem, bo); + pr_debug("Employ DMABUF mechanim to enable peer GPU access\n"); +#else + *bo = mem->bo; + attachment->type = KFD_MEM_ATT_SHARED; + drm_gem_object_get(&(*bo)->tbo.base); + pr_debug("Employ Shared BO mechanim to enable peer GPU access\n"); +#endif + return ret; +} + /* kfd_mem_attach - Add a BO to a VM * * Everything that needs to bo done only once when a BO is first added @@ -941,6 +973,13 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, goto unwind; pr_debug("Employ DMABUF mechanism to enable peer GPU access\n"); #endif + /* Enable peer acces to VRAM BO's */ + } else if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM && + mem->bo->tbo.type == ttm_bo_type_device) { + ret = kfd_mem_attach_vram_bo(adev, mem, + &bo[i], attachment[i]); + if (ret) + goto unwind; } else { WARN_ONCE(true, "Handling invalid ATTACH request"); ret = -EINVAL; From 3986f4465c24e25229f880fe3d90fcc14cf02be1 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 8 Jun 2021 12:13:06 -0400 Subject: [PATCH 0511/2653] drm/amdkcl: get list of supported ASIC The patch ensures that DKMS build succeeds against kernels that don't support all chips defined in amdgpu_pciid.h Change-Id: Id00ed13b2d8210965bd9de6759da1f1e776a3d4f Signed-off-by: Slava Grigorev Reviewed-by: Tim Writer Reviewed-by: Slava Abramov --- .../drm/amd/dkms/config/config-amd-chips.h | 3 ++ drivers/gpu/drm/amd/dkms/config/config.h | 2 ++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 5 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 29 +++++++++++++++++++ 4 files changed, 39 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/config/config-amd-chips.h diff --git a/drivers/gpu/drm/amd/dkms/config/config-amd-chips.h b/drivers/gpu/drm/amd/dkms/config/config-amd-chips.h new file mode 100644 index 0000000000000..9ff8bd1cb6a04 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/config/config-amd-chips.h @@ -0,0 +1,3 @@ +/* + * This file is managed by DKMS build. Do not edit. + */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 848d2f2e56b40..020d10ba36675 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1004,3 +1004,5 @@ /* Define to the version of this package. */ #define PACKAGE_VERSION "19.40" + +#include "config-amd-chips.h" diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 1f21aec4ff2ee..5c9cf41e67120 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -46,6 +46,11 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_gem_ttm_helper.h]) + dnl # + dnl # Required by AC_KERNEL_SUPPORTED_AMD_CHIPS macro + dnl # + AC_KERNEL_CHECK_HEADERS([drm/amd_asic_type.h]) + dnl # dnl # v5.12-rc3-330-g2916059147ea dnl # drm/aperture: Add infrastructure for aperture ownership diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f1e4bc1791f84..9133ac7947216 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -7,6 +7,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_HEADERS AC_AMDGPU_DRM_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME + AC_KERNEL_SUPPORTED_AMD_CHIPS AC_AMDGPU_IDR_REMOVE AC_AMDGPU_KREF_READ AC_AMDGPU_TYPE__POLL_T @@ -163,6 +164,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ ]) AC_SUBST(KERNEL_MAKE) + AH_BOTTOM([#include "config-amd-chips.h"]) ]) dnl # @@ -565,3 +567,30 @@ AC_DEFUN([AC_KERNEL_WAIT], [ AC_MSG_RESULT([failed]) ]) ]) + +dnl # +dnl # AC_KERNEL_SUPPORTED_AMD_CHIPS +dnl # get list of graphics chips supported by the amdgpu kernel driver +dnl # +AC_DEFUN([AC_KERNEL_SUPPORTED_AMD_CHIPS], [ + AC_MSG_CHECKING([for supported chips]) + AS_IF([test $HAVE_DRM_AMD_ASIC_TYPE_H], [ + chips=$(awk 'BEGIN {enum = 0} { + if ($[0] ~ "^enum amd_asic_type") + enum = 1; + if (enum && $[1] ~ "CHIP_") { + gsub(",", ""); + if ($[1] == "CHIP_LAST") + exit; + print $[1]; + } + }' $LINUX/include/drm/amd_asic_type.h) + + for i in $chips; do + $as_echo "#define HAVE_$i" >>config/config-amd-chips.h + done + AC_MSG_RESULT([done]) + ], [ + AC_MSG_RESULT([failed]) + ]) +]) From 709819a0e5e37f8ce7a48cc76c44420988a6be43 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 9 Jun 2021 12:42:06 +0800 Subject: [PATCH 0512/2653] drm/amdkcl: wrap the coder under HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE This is caused by 4238367e9de8 "drm/amd/display: force CP to DESIRED when removing display" v5.11-3747-g084150ff1151 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index 279f1226c3c64..e4aa129d14b8d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -262,9 +262,11 @@ static void hdcp_remove_display(struct hdcp_workqueue *hdcp_work, if (conn_state && conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP 2 -> 1, type %u, DPMS %u\n", aconnector->base.index, conn_state->hdcp_content_type, aconnector->base.dpms); +#endif } mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output); From a7509e9c05300175bacac06a46e340aa00f5682b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 10 Jun 2021 15:30:18 +0800 Subject: [PATCH 0513/2653] drm/amdkcl: disable support for 16 bpc fixed-point framebuffers in legacy os This is caused by 0c53c5194ddf "drm/amd/display: Enable support for 16 bpc fixed-point framebuffers." v5.11-3548-g0c53c5194ddf Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Signed-off-by: Ma Jun Change-Id: I20f72b0bd90888520cb4e47453b94ffb1a75c157 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 ++ include/kcl/kcl_drm_fourcc.h | 13 ------------- 2 files changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 629282825bf8d..c9e2173e18967 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -54,10 +54,12 @@ static const uint32_t rgb_formats[] = { DRM_FORMAT_XBGR2101010, DRM_FORMAT_ARGB2101010, DRM_FORMAT_ABGR2101010, +#ifdef DRM_FORMAT_XRGB16161616 DRM_FORMAT_XRGB16161616, DRM_FORMAT_XBGR16161616, DRM_FORMAT_ARGB16161616, DRM_FORMAT_ABGR16161616, +#endif DRM_FORMAT_XBGR8888, DRM_FORMAT_ABGR8888, DRM_FORMAT_RGB565, diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h index d40688cb6422d..25cf40f897b23 100644 --- a/include/kcl/kcl_drm_fourcc.h +++ b/include/kcl/kcl_drm_fourcc.h @@ -214,17 +214,4 @@ #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ #endif - -/* 64 bpp RGB */ -#ifndef DRM_FORMAT_XRGB16161616 -/* Copied from v5.11-3544-ga2fe23ecdbb7 */ -#define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ -#define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ -#endif - -#ifndef DRM_FORMAT_ARGB16161616 -#define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ -#define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ -#endif - #endif /* KCL_KCL_DRM_FOURCC_H */ From 16e27fd7e57e758f8900373ed49babaa69d315f8 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 15 Jun 2021 13:45:38 +0800 Subject: [PATCH 0514/2653] drm/amdkcl: add DP_* macro for legacy os This is caused by f50245219f8c "drm/amd/display: Partition DPCD address space and break up transactions" v5.11-3817-gf50245219f8c Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_drm_dp_helper.h | 53 ++++++++++++++++++++++++++++++--- 1 file changed, 49 insertions(+), 4 deletions(-) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index edb6b4202915b..7fb0da12e569b 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -108,10 +108,6 @@ #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */ #endif -#if !defined(DP_TRAINING_PATTERN_SET_PHY_REPEATER1) -#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ -#endif - #if !defined(DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT) #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ #endif @@ -162,4 +158,53 @@ #define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED #endif +/* v5.9-rc4-979-g9782f52ab5d6 + * drm/dp: Add LTTPR helpers + */ +#ifndef DP_TRAINING_PATTERN_SET_PHY_REPEATER + +enum drm_dp_phy { + DP_PHY_DPRX, + + DP_PHY_LTTPR1, + DP_PHY_LTTPR2, + DP_PHY_LTTPR3, + DP_PHY_LTTPR4, + DP_PHY_LTTPR5, + DP_PHY_LTTPR6, + DP_PHY_LTTPR7, + DP_PHY_LTTPR8, + + DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8, +}; + +#define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i)) +#define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */ +#define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */ +#define DP_LTTPR_BASE(dp_phy) \ + (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \ + ((dp_phy) - DP_PHY_LTTPR1)) +#define DP_LTTPR_REG(dp_phy, lttpr1_reg) \ + (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg)) +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \ + DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1) +#endif + +#ifndef DP_FEC_STATUS_PHY_REPEATER + +#define __DP_FEC1_BASE 0xf0290 /* 1.4 */ +#define __DP_FEC2_BASE 0xf0298 /* 1.4 */ +#define DP_FEC_BASE(dp_phy) \ + (__DP_FEC1_BASE + ((__DP_FEC2_BASE - __DP_FEC1_BASE) * \ + ((dp_phy) - DP_PHY_LTTPR1))) +#define DP_FEC_REG(dp_phy, fec1_reg) \ + (DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg) +#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */ +#define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \ + DP_FEC_REG(dp_phy, DP_FEC_STATUS_PHY_REPEATER1) +#define DP_LTTPR_MAX_ADD 0xf02ff /* 1.4 */ +#define DP_DPCD_MAX_ADD 0xfffff /* 1.4 */ + +#endif + #endif /* _KCL_DRM_DP_HELPER_H_ */ From a485bfa695d041caa7f7fc2e7b85f4f5123aef31 Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Thu, 17 Jun 2021 10:15:18 -0400 Subject: [PATCH 0515/2653] drm/amdkfd: Set p2plink non-coherent in topology Fix non-coherent bit of p2plink properties flag which always is 0. Signed-off-by: Eric Huang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 6b47832ef150a..1b94b813f18bc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1463,6 +1463,7 @@ static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev) inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED; kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link); + kfd_set_iolink_non_coherent(peer_dev, link, inbound_link); } } } From 4603267faf4396a595959b3c9245d3c117148881 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 18 Jun 2021 14:02:34 +0800 Subject: [PATCH 0516/2653] drm/amdkcl: fix kgd2kfd_resume() prototype in dkms branch Signed-off-by: Flora Cui Reported-by: chen gong Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 047dfae22515e..f65d82b8fa161 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -501,7 +501,7 @@ static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) { } -static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc) +static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm, bool sync) { return 0; } From e350b6bf6ebed2663aa41851ae854f3b507d94bc Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 18 Jun 2021 13:14:46 +0800 Subject: [PATCH 0517/2653] drm/amdkcl: fake the sysfs_emit_at This is caused by d0d2e18213f7 "amdgpu/pm: replaced snprintf usage in amdgpu_pm.c with sysfs_emit" v5.11-3838-gd0d2e18213f7 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c | 29 +++++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 2 +- drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 | 9 ++++--- include/kcl/kcl_sysfs_emit.h | 10 +++++++ 4 files changed, 46 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c b/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c index 798745cbfff91..0b23918cc8486 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c @@ -29,4 +29,33 @@ int sysfs_emit(char *buf, const char *fmt, ...) return len; } EXPORT_SYMBOL_GPL(sysfs_emit); + +/** + * sysfs_emit_at - scnprintf equivalent, aware of PAGE_SIZE buffer. + * @buf: start of PAGE_SIZE buffer. + * @at: offset in @buf to start write in bytes + * @at must be >= 0 && < PAGE_SIZE + * @fmt: format + * @...: optional arguments to @fmt + * + * + * Returns number of characters written starting at &@buf[@at]. + */ +int sysfs_emit_at(char *buf, int at, const char *fmt, ...) +{ + va_list args; + int len; + + if (WARN(!buf || offset_in_page(buf) || at < 0 || at >= PAGE_SIZE, + "invalid sysfs_emit_at: buf:%p at:%d\n", buf, at)) + return 0; + + va_start(args, fmt); + len = vscnprintf(buf + at, PAGE_SIZE - at, fmt, args); + va_end(args); + + return len; +} +EXPORT_SYMBOL_GPL(sysfs_emit_at); + #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 020d10ba36675..92e367643dc75 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -918,7 +918,7 @@ /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ -/* sysfs_emit() is available */ +/* sysfs_emit() and sysfs_emit_at are available */ #define HAVE_SYSFS_EMIT 1 /* timer_setup() is available */ diff --git a/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 index e9f403134af83..c1dc1717cc324 100644 --- a/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 @@ -1,13 +1,16 @@ dnl # dnl # commit: v5.9-rc5-23-g2efc459d06f1 -dnl # sysfs: Add sysfs_emit and sysfs_emit_at +dnl # sysfs: Add sysfs_emit and sysfs_emit_at dnl # to format sysfs output AC_DEFUN([AC_AMDGPU_SYSFS_EMIT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([sysfs_emit], + AC_KERNEL_CHECK_SYMBOL_EXPORT([sysfs_emit sysfs_emit_at], [fs/sysfs/file.c], [ AC_DEFINE(HAVE_SYSFS_EMIT, 1, - [sysfs_emit() is available]) + [sysfs_emit() and sysfs_emit_at() are available]) ]) ]) ]) + + +) diff --git a/include/kcl/kcl_sysfs_emit.h b/include/kcl/kcl_sysfs_emit.h index ab87e74f817ff..381265a29b7e1 100644 --- a/include/kcl/kcl_sysfs_emit.h +++ b/include/kcl/kcl_sysfs_emit.h @@ -15,11 +15,21 @@ #ifdef CONFIG_SYSFS __printf(2, 3) int sysfs_emit(char *buf, const char *fmt, ...); + +__printf(3, 4) +int sysfs_emit_at(char *buf, int at, const char *fmt, ...); + #else __printf(2, 3) static inline int sysfs_emit(char *buf, const char *fmt, ...) { return 0; } + +__printf(3, 4) +static inline int sysfs_emit_at(char *buf, int at, const char *fmt, ...) +{ + return 0; +} #endif #endif From 9b3961682977172ae2226e31d331e506bf035376 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 21 Jun 2021 14:38:26 +0800 Subject: [PATCH 0518/2653] drm/amdkcl: update test for ttm_sg_tt_init for kernel with CONFIG_DRM_TTM disabled Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 b/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 index 9bfcadc878e3c..5cbf835eaf401 100644 --- a/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 @@ -1,10 +1,10 @@ dnl # -dnl # v4.16-rc1-1232-g75a57669cbc8 -dnl # drm/ttm: add ttm_sg_tt_init +dnl # v4.16-rc1-1232-g75a57669cbc8 drm/ttm: add ttm_sg_tt_init +dnl # v4.16-rc1-409-g186ca446aea1 drm/prime: make the pages array optional for drm_prime_sg_to_page_addr_arrays dnl # AC_DEFUN([AC_AMDGPU_TTM_SG_TT_INIT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([ttm_sg_tt_init], [drivers/gpu/drm/ttm/ttm_tt.c], [ + AS_IF([grep -q ttm_sg_tt_init $LINUX/include/drm/ttm/ttm_tt.h > /dev/null 2>&1], [ AC_DEFINE(HAVE_TTM_SG_TT_INIT, 1, [ttm_sg_tt_init() is available]) ]) ]) From 4764835c60a599e7ca891a87121ee29464a3ae5b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 25 Jun 2021 13:00:25 +0800 Subject: [PATCH 0519/2653] drm/amdkcl: fix for kernel_write() prototype change Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_fs_read_write.c | 27 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/kernel_write.m4 | 16 +++++++++++ include/kcl/backport/kcl_fs.h | 12 +++++++++ include/kcl/kcl_fs.h | 6 +++++ 8 files changed, 67 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/kernel_write.m4 create mode 100644 include/kcl/backport/kcl_fs.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index f95c0c73adb27..662dbafdd44d2 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -11,7 +11,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ - kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o + kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c b/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c new file mode 100644 index 0000000000000..e45c10eabc006 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c @@ -0,0 +1,27 @@ +/* + * linux/fs/read_write.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ +#include +#include + +/* Copied from v4.13-rc7-6-ge13ec939e96b:fs/read_write.c */ +#ifndef HAVE_KERNEL_WRITE_PPOS +ssize_t _kcl_kernel_write(struct file *file, const void *buf, size_t count, + loff_t *pos) +{ + mm_segment_t old_fs; + ssize_t res; + + old_fs = get_fs(); + set_fs(get_ds()); + /* The cast to a user pointer is valid due to the set_fs() */ + res = vfs_write(file, (__force const char __user *)buf, count, pos); + set_fs(old_fs); + + return res; +} +EXPORT_SYMBOL(_kcl_kernel_write); +#endif + diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 9e7bee1e97075..810a40bc1d1d6 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 92e367643dc75..ff3331748b748 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -636,6 +636,9 @@ /* kallsyms_lookup_name is available */ /* #undef HAVE_KALLSYMS_LOOKUP_NAME */ +/* kernel_write() take arg type of position as pointer */ +#define HAVE_KERNEL_WRITE_PPOS 1 + /* kref_read() function is available */ #define HAVE_KREF_READ 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9133ac7947216..312b2f4766c04 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -145,6 +145,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CHECK_SMCA_UMC_V2 AC_AMDGPU_PXM_TO_NODE AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY + AC_AMDGPU_KERNEL_WRITE AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_write.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_write.m4 new file mode 100644 index 0000000000000..3fdd8e902d61e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_write.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v4.13-rc7-6-ge13ec939e96b +dnl # fs: fix kernel_write prototype +dnl # +AC_DEFUN([AC_AMDGPU_KERNEL_WRITE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + kernel_write(NULL, NULL, 0, NULL); + ], [ + AC_DEFINE(HAVE_KERNEL_WRITE_PPOS, 1, + [kernel_write() take arg type of position as pointer]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_fs.h b/include/kcl/backport/kcl_fs.h new file mode 100644 index 0000000000000..200c92cd0f82f --- /dev/null +++ b/include/kcl/backport/kcl_fs.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_BACKPORT_KCL_FS_H +#define _KCL_BACKPORT_KCL_FS_H + +#include +#include + +#ifndef HAVE_KERNEL_WRITE_PPOS +#define kernel_write _kcl_kernel_write +#endif + +#endif diff --git a/include/kcl/kcl_fs.h b/include/kcl/kcl_fs.h index 4a4c208d833e0..633a6edfd8f17 100644 --- a/include/kcl/kcl_fs.h +++ b/include/kcl/kcl_fs.h @@ -19,4 +19,10 @@ static inline long compat_ptr_ioctl(struct file *file, unsigned int cmd, #define compat_ptr_ioctl NULL #endif /* CONFIG_COMPAT */ #endif /* HAVE_COMPAT_PTR_IOCTL */ + +#ifndef HAVE_KERNEL_WRITE_PPOS +ssize_t _kcl_kernel_write(struct file *file, const void *buf, size_t count, + loff_t *pos); +#endif + #endif From b893883d6c4fd4d6c06855a059e521877c2ed051 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 6 Jul 2021 15:33:05 +0800 Subject: [PATCH 0520/2653] drm/amdkcl: not use xarray for storing pasid in legacy os This is caused by 9538d0fc5286 "drm/amdgpu: use xarray for storing pasid in vm" v5.11-3985-g9538d0fc5286 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 45 +++++++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 5 +++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/xarray.m4 | 17 +++++++++ 5 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/xarray.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 27f928b8fd010..d2369164ee3c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -141,8 +141,9 @@ struct amdgpu_vm_tlb_seq_struct { int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid) { - int r; + int r = 0; +#ifdef HAVE_STRUCT_XARRAY if (vm->pasid == pasid) return 0; @@ -162,7 +163,21 @@ int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, vm->pasid = pasid; } +#else + unsigned long flags; + spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); + if (pasid) { + r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, + GFP_ATOMIC); + } else if (vm->pasid) { + idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); + } + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); + if (r < 0) + return r; + vm->pasid = pasid; +#endif return 0; } @@ -2871,7 +2886,12 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev) adev->vm_manager.vm_update_mode = 0; #endif +#ifdef HAVE_STRUCT_XARRAY xa_init_flags(&adev->vm_manager.pasids, XA_FLAGS_LOCK_IRQ); +#else + idr_init(&adev->vm_manager.pasid_idr); + spin_lock_init(&adev->vm_manager.pasid_lock); +#endif } /** @@ -2883,8 +2903,13 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev) */ void amdgpu_vm_manager_fini(struct amdgpu_device *adev) { +#ifdef HAVE_STRUCT_XARRAY WARN_ON(!xa_empty(&adev->vm_manager.pasids)); xa_destroy(&adev->vm_manager.pasids); +#else + WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr)); + idr_destroy(&adev->vm_manager.pasid_idr); +#endif amdgpu_vmid_mgr_fini(adev); } @@ -2956,15 +2981,24 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, struct amdgpu_vm *vm; int r; +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, irqflags); vm = xa_load(&adev->vm_manager.pasids, pasid); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags); + vm = idr_find(&adev->vm_manager.pasid_idr, pasid); +#endif if (vm) { root = amdgpu_bo_ref(vm->root.bo); is_compute_context = vm->is_compute_context; } else { root = NULL; } +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags); +#else + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags); +#endif if (!root) return false; @@ -2982,11 +3016,20 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, goto error_unref; /* Double check that the VM still exists */ +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, irqflags); vm = xa_load(&adev->vm_manager.pasids, pasid); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags); + vm = idr_find(&adev->vm_manager.pasid_idr, pasid); +#endif if (vm && vm->root.bo != root) vm = NULL; +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags); +#else + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags); +#endif if (!vm) goto error_unlock; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 607e352bc780e..0298898579863 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -469,7 +469,12 @@ struct amdgpu_vm_manager { /* PASID to VM mapping, will be used in interrupt context to * look up VM of a page fault */ +#ifdef HAVE_STRUCT_XARRAY struct xarray pasids; +#else + struct idr pasid_idr; + spinlock_t pasid_lock; +#endif /* Global registration of recent page fault information */ struct amdgpu_vm_fault_info fault_info; }; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ff3331748b748..bce21674fb244 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -918,6 +918,9 @@ /* drm_plane_helper_funcs->prepare_fb() wants p,p arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_PP 1 +/* struct xarray is available */ +#define HAVE_STRUCT_XARRAY 1 + /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 312b2f4766c04..744d7c5eedfa6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -146,6 +146,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PXM_TO_NODE AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY AC_AMDGPU_KERNEL_WRITE + AC_AMDGPU_STRUCT_XARRAY AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/xarray.m4 b/drivers/gpu/drm/amd/dkms/m4/xarray.m4 new file mode 100644 index 0000000000000..bfe64c548f1c1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/xarray.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v4.19-rc5-244-gf8d5d0cc145c +dnl # xarray: Add definition of struct xarray +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_XARRAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct xarray x; + xa_init(&x); + ], [ + AC_DEFINE(HAVE_STRUCT_XARRAY, 1, + [struct xarray is available]) + ]) + ]) +]) From 53cbbde11a02f16800c28df901de2a73dc7d6676 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 6 Jul 2021 15:44:07 +0800 Subject: [PATCH 0521/2653] drm/amdkcl: add I2C_AQ_NO_ZERO_LEN macro This is caused by b79271766c50 "drm/amdgpu: The I2C IP doesn't support 0 writes/reads" v5.11-3990-gb79271766c50 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_i2c.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/kcl/kcl_i2c.h b/include/kcl/kcl_i2c.h index 66b3195eff49d..2e7f36acdeadc 100644 --- a/include/kcl/kcl_i2c.h +++ b/include/kcl/kcl_i2c.h @@ -23,4 +23,11 @@ i2c_new_client_device(struct i2c_adapter *adap, struct i2c_board_info const *inf } #endif +#ifndef I2C_AQ_NO_ZERO_LEN +#define I2C_AQ_NO_ZERO_LEN_READ BIT(5) +#define I2C_AQ_NO_ZERO_LEN_WRITE BIT(6) +#define I2C_AQ_NO_ZERO_LEN (I2C_AQ_NO_ZERO_LEN_READ | I2C_AQ_NO_ZERO_LEN_WRITE) +#endif + + #endif From 638937c4e433efcf5024a1e3d1323fdc41652637 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 25 Jun 2021 16:50:03 +0800 Subject: [PATCH 0522/2653] drm/amdkcl: wrap the coder under CONFIG_DRM_AMD_DC_DSC_SUPPORT This is caused by b37360fb390e "drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN" v5.11-3882-gb37360fb390e Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- .../display/dc/dio/dcn31/dcn31_dio_link_encoder.c | 2 ++ .../gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 5 ++++- .../gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c | 2 ++ .../gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c | 2 ++ .../amd/display/dc/resource/dcn31/dcn31_resource.c | 12 ++++++++++++ 5 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c index 9a92f73d5b7fe..127760c096d56 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c @@ -247,7 +247,9 @@ void enc31_hw_init(struct link_encoder *enc) } static const struct link_encoder_funcs dcn31_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc31_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index 8ba934b83957b..a3bdaca7d3e5b 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -278,6 +278,7 @@ void dcn31_init_hw(struct dc *dc) dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn31_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -340,6 +341,7 @@ void dcn31_dsc_pg_control( } } +#endif void dcn31_enable_power_gating_plane( @@ -536,10 +538,11 @@ static void dcn31_reset_back_end_for_pipe( dc->hwseq->wa_state.skip_blank_stream = true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT pipe_ctx->stream_res.tg->funcs->set_dsc_config( pipe_ctx->stream_res.tg, OPTC_DSC_DISABLED, 0, 0); - +#endif pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c index 556f4fe57eda7..060e3db29052b 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c @@ -139,7 +139,9 @@ static const struct hwseq_private_funcs dcn31_private_funcs = { .hubp_pg_control = dcn31_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn31_dsc_pg_control, +#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c index 4f1830ba619f0..1b7d2879b084d 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c @@ -359,7 +359,9 @@ static const struct timing_generator_funcs dcn31_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, +#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .set_odm_bypass = optc3_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c index ca17e5d8fdc2a..60df1c2308402 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c @@ -563,6 +563,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -581,6 +582,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -824,7 +826,9 @@ static const struct resource_caps res_cap_dcn31 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -1382,10 +1386,12 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1560,6 +1566,7 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1574,6 +1581,7 @@ static struct display_stream_compressor *dcn31_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif static void dcn31_destroy_resource_pool(struct resource_pool **pool) { @@ -1839,7 +1847,9 @@ static struct resource_funcs dcn31_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn31_set_mcif_arb_params, @@ -2140,6 +2150,7 @@ static bool dcn31_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn31_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2148,6 +2159,7 @@ static bool dcn31_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { From a956163e91755d3306e479d00804c22adbf2f757 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 15 Jul 2021 10:11:26 -0400 Subject: [PATCH 0523/2653] drm/amdkcl: fix get list of supported ASIC Use amd_asic_type.h header in DKMS tree instead of system kernel tree to search for supported ASIC. Change-Id: Ie20e9670cecdea28616c325d983f99fb0155b616 Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 744d7c5eedfa6..7346d103d2cd7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -586,7 +586,7 @@ AC_DEFUN([AC_KERNEL_SUPPORTED_AMD_CHIPS], [ exit; print $[1]; } - }' $LINUX/include/drm/amd_asic_type.h) + }' ../../include/drm/amd_asic_type.h) for i in $chips; do $as_echo "#define HAVE_$i" >>config/config-amd-chips.h From a3d0952df2eb32e7638e23a34ee08a00bd5ecac8 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Mon, 17 May 2021 19:48:51 -0400 Subject: [PATCH 0524/2653] drm/amdkfd: synchronize runtime enable with the debugger If the debugger is attached, raise an EC_PROCESS_RUNTIME_ENABLE/DISABLE event on runtime enable/disable and block until the debugger sends the process event to unblock. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 39d7df89930c1..a68f348d0cfc0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -39,6 +39,7 @@ #include #include #include +#include /* amdkcl: this header file is included in kcl_device_cgroup.h #include */ #include From 256e32b0f26ab2e68a0b5d454bb78c94a33c1af9 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 28 Jun 2021 12:16:21 +0800 Subject: [PATCH 0525/2653] drm/amdkcl: Fix compile warning by include header file Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_ftrace.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/kcl/kcl_ftrace.h b/include/kcl/kcl_ftrace.h index de98a0a5f345e..ae106eff452b0 100644 --- a/include/kcl/kcl_ftrace.h +++ b/include/kcl/kcl_ftrace.h @@ -2,6 +2,7 @@ #ifndef AMDKCL_FTRACE_H #define AMDKCL_FTRACE_H +#include /* Copied from v3.19-rc1-6-g6ea22486ba46 include/trace/ftrace.h */ #if !defined(HAVE___PRINT_ARRAY) extern const char * ftrace_print_array_seq(struct trace_seq *p, const void *buf, int count, From 007d7744237785b905681e60c86bce7bbe73f480 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 28 Jun 2021 12:28:49 +0800 Subject: [PATCH 0526/2653] drm/amdkcl: Add const cast to adapt function prototype and Fix compile warning Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_drm_print.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index c2dac790ba1c8..6dea17070b5de 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -68,9 +68,9 @@ static inline void drm_mm_print(const struct drm_mm *mm, struct drm_printer *p) { #ifndef HAVE_DRM_DRM_PRINT_H - drm_mm_debug_table(mm, p->prefix); + drm_mm_debug_table((struct drm_mm *)mm, p->prefix); #else - drm_mm_debug_table(mm, "no prefix"); + drm_mm_debug_table((struct drm_mm *)mm, "no prefix"); #endif } #endif From 97fd4a2a36a916fc5dc330b76b6095c9785cc9af Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 28 Jun 2021 13:47:37 +0800 Subject: [PATCH 0527/2653] amd/drmkcl: Fix redefined dma_fence_default_wait macro Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/backport/kcl_fence_backport.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/backport/kcl_fence_backport.h b/include/kcl/backport/kcl_fence_backport.h index 022951286bb7d..7e3e1ab42138b 100644 --- a/include/kcl/backport/kcl_fence_backport.h +++ b/include/kcl/backport/kcl_fence_backport.h @@ -19,6 +19,11 @@ * dma-buf/fence: revert "don't wait when specified timeout is zero" (v2) */ #ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT + +#ifdef dma_fence_default_wait +#undef dma_fence_default_wait +#endif + #define dma_fence_default_wait _kcl_fence_default_wait #define dma_fence_wait_timeout _kcl_fence_wait_timeout #endif From 1e1409f2e24b19ec2c92d877532ce2ae2d4cfdb0 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 28 Jun 2021 13:47:19 +0800 Subject: [PATCH 0528/2653] drm/amdkcl: Remove unused local variable Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c index 58beb9fcedf38..c0f145df309d3 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -71,15 +71,15 @@ EXPORT_SYMBOL(__drm_atomic_helper_crtc_reset); */ void drm_atomic_helper_calc_timestamping_constants(struct drm_atomic_state *state) { - struct drm_device *dev = state->dev; struct drm_crtc_state *new_crtc_state; struct drm_crtc *crtc; - int i; #if !defined(for_each_new_crtc_in_state) + struct drm_device *dev = state->dev; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { new_crtc_state = crtc->state; #else + int i; for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { #endif if (new_crtc_state->enable) From 1d308d023237fe8479578ccab0fd81abc32eb1e2 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 28 Jun 2021 16:02:19 +0800 Subject: [PATCH 0529/2653] drm/amdkcl: wrap function dma_fence_test_signaled_any under the macro Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index ed889c91b8dd4..1376705d31822 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -26,6 +26,7 @@ #include "kcl_fence_trace.h" /* Copied from drivers/dma-buf/dma-fence.c */ +#if defined(AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT) || defined(AMDKCL_FENCE_WAIT_ANY_TIMEOUT) static bool dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count, uint32_t *idx) @@ -42,6 +43,7 @@ dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count, } return false; } +#endif struct default_wait_cb { struct dma_fence_cb base; From 68ff82583e6bd28cee872c72b4dee5bbacf2cb09 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Tue, 20 Jul 2021 22:10:49 -0400 Subject: [PATCH 0530/2653] drm/amdkfd: IPC export and import memory alloc flags Support query pointer info memory alloc flags, ex CoarseGrain, for shared memory by IPC. App pass memory alloc flags to export handle ioctl, to save memory alloc flags to ipc object, import handle ioctl get ipc object and pass memory alloc flags back to app which could be different process. Keep import export handle ioctl interface, rename unused _u32 pad field to flags. Signed-off-by: Philip Yang Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 +++-- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 +++-- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 12 ++++++++---- drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 9 ++++++--- include/uapi/linux/kfd_ioctl.h | 6 +++--- 6 files changed, 25 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index f65d82b8fa161..051bfa1a98f26 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -362,7 +362,8 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, struct dma_buf **dmabuf); int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, struct kgd_mem *mem, - struct kfd_ipc_obj **ipc_obj); + struct kfd_ipc_obj **ipc_obj, + uint32_t flags); void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev); int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 8a6ddb6968a95..5db1cd45a2e62 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2737,7 +2737,8 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, struct kgd_mem *mem, - struct kfd_ipc_obj **ipc_obj) + struct kfd_ipc_obj **ipc_obj, + uint32_t flags) { struct amdgpu_device *adev = NULL; struct dma_buf *dmabuf; @@ -2760,7 +2761,7 @@ int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, goto unlock_out; } - r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj); + r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj, flags); if (r) dma_buf_put(dmabuf); else diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 622865a15b971..7800651c7c5aa 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1664,7 +1664,8 @@ static int kfd_ioctl_ipc_export_handle(struct file *filep, if (!dev) return -EINVAL; - r = kfd_ipc_export_as_handle(dev, p, args->handle, args->share_handle); + r = kfd_ipc_export_as_handle(dev, p, args->handle, args->share_handle, + args->flags); if (r) pr_err("Failed to export IPC handle\n"); @@ -1685,7 +1686,7 @@ static int kfd_ioctl_ipc_import_handle(struct file *filep, r = kfd_ipc_import_handle(dev, p, args->gpu_id, args->share_handle, args->va_addr, &args->handle, - &args->mmap_offset); + &args->mmap_offset, &args->flags); if (r) pr_err("Failed to import IPC handle\n"); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index 88ab20909ce39..b5d89265d3c2d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -41,7 +41,8 @@ static struct kfd_ipc_handles { */ #define HANDLE_TO_KEY(sh) ((*(uint64_t *)sh) & KFD_IPC_HASH_TABLE_SIZE_MASK) -int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj) +int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, + uint32_t flags) { struct kfd_ipc_obj *obj; @@ -59,6 +60,7 @@ int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj) kref_init(&obj->ref); obj->dmabuf = dmabuf; get_random_bytes(obj->share_handle, sizeof(obj->share_handle)); + obj->flags = flags; mutex_lock(&kfd_ipc_handles.lock); hlist_add_head(&obj->node, @@ -182,7 +184,7 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *dev, int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset) + uint64_t *mmap_offset, uint32_t *pflags) { int r; struct kfd_ipc_obj *entry, *found = NULL; @@ -212,6 +214,7 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, if (r) goto error_unref; + *pflags = found->flags; return r; error_unref: @@ -220,7 +223,8 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, } int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, - uint64_t handle, uint32_t *ipc_handle) + uint64_t handle, uint32_t *ipc_handle, + uint32_t flags) { struct kfd_process_device *pdd = NULL; struct kfd_ipc_obj *ipc_obj; @@ -249,7 +253,7 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, mem = (struct kgd_mem *)kfd_bo->mem; r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->kgd, pdd->drm_priv, mem, - &ipc_obj); + &ipc_obj, flags); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h index 72fe8e4af2e5c..7915b8cad13db 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -36,20 +36,23 @@ struct kfd_ipc_obj { struct kref ref; struct dma_buf *dmabuf; uint32_t share_handle[4]; + uint32_t flags; }; int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset); + uint64_t *mmap_offset, uint32_t *pflags); int kfd_ipc_import_dmabuf(struct kfd_dev *kfd, struct kfd_process *p, uint32_t gpu_id, int dmabuf_fd, uint64_t va_addr, uint64_t *handle, uint64_t *mmap_offset); int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, - uint64_t handle, uint32_t *ipc_handle); + uint64_t handle, uint32_t *ipc_handle, + uint32_t flags); -int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj); +int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, + uint32_t flags); void kfd_ipc_obj_put(struct kfd_ipc_obj **obj); #endif /* KFD_IPC_H_ */ diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index da4f814fe9654..bcda022281f26 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -828,16 +828,16 @@ struct kfd_ioctl_ipc_export_handle_args { __u64 handle; /* to KFD */ __u32 share_handle[4]; /* from KFD */ __u32 gpu_id; /* to KFD */ - __u32 pad; + __u32 flags; /* to KFD */ }; struct kfd_ioctl_ipc_import_handle_args { __u64 handle; /* from KFD */ __u64 va_addr; /* to KFD */ - __u64 mmap_offset; /* from KFD */ + __u64 mmap_offset; /* from KFD */ __u32 share_handle[4]; /* to KFD */ __u32 gpu_id; /* to KFD */ - __u32 pad; + __u32 flags; /* from KFD */ }; /* Guarantee host access to memory */ From c76eb58dae5e3bd424b52cfec8005a5ea06aa1d5 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 10 Aug 2021 14:14:34 +0800 Subject: [PATCH 0531/2653] drm/amdkcl: Test whether struct dev_pagemap has member range This is caused by 1d5dbfe6c06a "drm/amdkfd: classify and map mixed svm range pages in GPU" v5.13-rc7-1639-g1d5dbfe6c06a Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index e23b5a0f31f2b..794e27a83ea24 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -184,7 +184,11 @@ svm_range_dma_map_dev(struct amdgpu_device *adev, struct svm_range *prange, addr[i] = (hmm_pfns[i] << PAGE_SHIFT) + bo_adev->vm_manager.vram_base_offset - +#ifdef HAVE_DEV_PAGEMAP_RANGE bo_adev->kfd.pgmap.range.start; +#else + bo_adev->kfd.dev->pgmap.res.start; +#endif addr[i] |= SVM_RANGE_VRAM_DOMAIN; pr_debug_ratelimited("vram address: 0x%llx\n", addr[i]); continue; From a2c9d73229a43328947a1f8652dd544b2749f878 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 10 Aug 2021 14:44:49 +0800 Subject: [PATCH 0532/2653] drm/amdkcl: wrap the code under macro HAVE_DRM_DP_AUX_DRM_DEV This is caused by 6cba3fe43341 "drm/dp: Add backpointer to drm_device in drm_dp_aux" v5.12-rc7-1495-g6cba3fe43341 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 9c1b6331c4912..ebf0f5d41c9cc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -926,7 +926,9 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d", link_index); aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer; +#ifdef HAVE_DRM_DP_AUX_DRM_DEV aconnector->dm_dp_aux.aux.drm_dev = dm->ddev; +#endif aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc; drm_dp_aux_init(&aconnector->dm_dp_aux.aux); From b8db3c07a926d7430244910b12723671c0c87fc4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 10 Aug 2021 15:35:04 +0800 Subject: [PATCH 0533/2653] =?UTF-8?q?drm/amdkcl:=20Test=20whether=20drm=5F?= =?UTF-8?q?connector=5Fatomic=5Fhdr=5Fmetadata=5Fequal=EF=BC=88=EF=BC=89?= =?UTF-8?q?=20is=20available?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is caused by 72921cdf8ac2 "drm/connector: Add helper to compare HDR metadata" v5.12-rc7-1582-g72921cdf8ac2 Signed-off-by: Leslie Shi --- .../gpu/drm/amd/amdkcl/kcl_drm_connector.c | 23 +++++++++++++++++++ ...drm-connector-atomic-hdr-metadata-equal.m4 | 16 +++++++++++++ ...drm-connector-state-hdr-output-metadata.m4 | 17 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 5 ++++ include/kcl/kcl_drm_connector.h | 5 ++++ 5 files changed, 66 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdr-output-metadata.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index ebcb2ae541c33..f8bb8819388e6 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -40,3 +40,26 @@ amdkcl_dummy_symbol(drm_dp_set_subconnector_property, void, return, struct drm_connector *connector, enum drm_connector_status status, const u8 *dpcd, const u8 prot_cap[4]) #endif + +#ifndef HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL + +bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_state, + struct drm_connector_state *new_state) +{ +#ifdef HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA + struct drm_property_blob *old_blob = old_state->hdr_output_metadata; + struct drm_property_blob *new_blob = new_state->hdr_output_metadata; + + if (!old_blob || !new_blob) + return old_blob == new_blob; + + if (old_blob->length != new_blob->length) + return false; + + return !memcmp(old_blob->data, new_blob->data, old_blob->length); +#else + return false; +#endif +} +EXPORT_SYMBOL(drm_connector_atomic_hdr_metadata_equal); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 new file mode 100644 index 0000000000000..7ae2c3fd78efd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.12-rc7-1582-g72921cdf8ac2 +dnl # drm/connector: Add helper to compare HDR metadata +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_connector_atomic_hdr_metadata_equal(NULL, NULL); + ], [drm_connector_atomic_hdr_metadata_equal], [drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL, 1, + [drm_connector_atomic_hdr_metadata_equal() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdr-output-metadata.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdr-output-metadata.m4 new file mode 100644 index 0000000000000..d79d5c876e35b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdr-output-metadata.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.1-rc5-1688-gfbb5d0353c62 +dnl # drm: Add HDR source metadata property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *state = NULL; + state->hdr_output_metadata = NULL; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA, 1, + [struct drm_connector_state has hdr_output_metadata member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7346d103d2cd7..411a68f7db3c8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -159,6 +159,11 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_AUX_DRM_DEV AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY + AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL + AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY + AC_AMDGPU_DMA_BUF_UNPIN + AC_AMDGPU_STRUCT_DMA_BUF_OPS_UNPIN + AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 9074a56cce9fd..cc7d8fbfe6386 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -96,4 +96,9 @@ enum drm_mode_subconnector { #endif /* HAVE_DRM_MODE_SUBCONNECTOR_ENUM */ #endif /* HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY */ +#ifndef HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL +bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_state, + struct drm_connector_state *new_state); +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From 9aae2abc3b49a5be6ec4af091175ba0bd46eaf87 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 10 Aug 2021 16:05:02 +0800 Subject: [PATCH 0534/2653] =?UTF-8?q?drm/amdkcl:=20Test=20whether=20drm=5F?= =?UTF-8?q?connector=5Fattach=5Fhdr=5Foutput=5Fmetadata=5Fproperty?= =?UTF-8?q?=EF=BC=88=EF=BC=89=20is=20available?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is caused by e057b52c1d90 "drm/connector: Create a helper to attach the hdr_output_metadata property" v5.12-rc7-1581-ge057b52c1d90 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c | 15 +++++++++++++++ ...nector-attach-hdr-output-metadata-property.m4 | 16 ++++++++++++++++ include/kcl/kcl_drm_connector.h | 4 ++++ 3 files changed, 35 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index f8bb8819388e6..79c907264d709 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -63,3 +63,18 @@ bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_sta } EXPORT_SYMBOL(drm_connector_atomic_hdr_metadata_equal); #endif + +#if !defined(HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY) +int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *connector) +{ +#ifdef HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY + struct drm_device *dev = connector->dev; + struct drm_property *prop = dev->mode_config.hdr_output_metadata_property; + + drm_object_attach_property(&connector->base, prop, 0); +#endif + + return 0; +} +EXPORT_SYMBOL(drm_connector_attach_hdr_output_metadata_property); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 new file mode 100644 index 0000000000000..fccf8755fc7fe --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.12-rc7-1581-ge057b52c1d90 +dnl # drm/connector: Create a helper to attach the hdr_output_metadata property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_connector_attach_hdr_output_metadata_property(NULL); + ], [drm_connector_attach_hdr_output_metadata_property], [drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY, 1, + [drm_connector_attach_hdr_output_metadata_property() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index cc7d8fbfe6386..f50f00e2f17fb 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -101,4 +101,8 @@ bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_sta struct drm_connector_state *new_state); #endif +#if !defined(HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY) +int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *connector); +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From 35635566f5fc3437dc475dc634106c1e50499260 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 10 Aug 2021 16:57:47 +0800 Subject: [PATCH 0535/2653] drm/amdkcl: Test whether drm_plane_helper_funcs.atomic_check second param is struct drm_atomic_state* This is caused by 5ddb0bd4ddc3 "drm/atomic: Pass the full state to planes async atomic check and update" v5.11-rc2-698-g5ddb0bd4ddc3 Signed-off-by: Leslie Shi Signed-off-by: Ma Jun Change-Id: Ib363f19e14009df6191f30959f76fe17ce68a5ca --- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 33 ++++++++++++++++--- .../dkms/m4/struct_drm_plane_helper_funcs.m4 | 20 +++++++++++ 2 files changed, 49 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index c9e2173e18967..1929ad52d04e4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1253,10 +1253,18 @@ int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, } static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + struct drm_atomic_state *state) +#else + struct drm_plane_state *state) +#endif { +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); +#else + struct drm_plane_state *new_plane_state = state; +#endif struct amdgpu_device *adev = drm_to_adev(plane->dev); struct dc *dc = adev->dm.dc; struct dm_plane_state *dm_plane_state; @@ -1271,8 +1279,12 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, if (!dm_plane_state->dc_state) return 0; - new_crtc_state = kcl_drm_atomic_get_new_crtc_state_before_commit( - state, new_plane_state->crtc); + new_crtc_state = +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); +#else + drm_atomic_get_new_crtc_state(state->state, state->crtc); +#endif if (!new_crtc_state) return -EINVAL; @@ -1293,7 +1305,11 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, #ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS struct drm_atomic_state *state, bool flip) +#else + struct drm_plane_state *state, bool flip) +#endif { struct drm_crtc_state *new_crtc_state; struct drm_plane_state *new_plane_state; @@ -1435,12 +1451,21 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane, } static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane, - struct drm_atomic_state *state) +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + struct drm_atomic_state *state) +#else + struct drm_plane_state *new_state) +#endif { +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); +#else + struct drm_plane_state *old_state = + drm_atomic_get_old_plane_state(new_state->state, plane); +#endif trace_amdgpu_dm_atomic_update_cursor(new_state); diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 index 4dd6e4db74ff6..68b8e02668cae 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 @@ -16,3 +16,23 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS], [ ]) ]) ]) + +dnl # commit v5.11-rc2-701-g7c11b99a8e58 +dnl # drm/atomic: Pass the full state to planes atomic_check +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_plane_helper_funcs *funcs = NULL; + funcs->atomic_check((struct drm_crtc *)NULL, (struct drm_atomic_state *)NULL); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS, 1, + [drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS], [ + AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS +]) From ec9ce77fe6dde75278a44af2c69395a341880aaf Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 10 Aug 2021 17:15:56 +0800 Subject: [PATCH 0536/2653] drm/amdkcl: fix build error for renamed struct field Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c index ef1c82463f8e0..5acf8485888f7 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -32,7 +32,7 @@ void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, struct dma_buf_map map; map.vaddr = vaddr; - map.is_iomem = bo->mem.bus.is_iomem; + map.is_iomem = bo->resource->bus.is_iomem; ttm_bo_vunmap(bo, &map); } From dba9c3c570fcb1f261cf4ce01e229eab921b0c2f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 13 Aug 2021 16:26:58 +0800 Subject: [PATCH 0537/2653] drm/amdkcl: access resv field using amdkcl_ttm_resvp Signed-off-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_bo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 2221ed3e8b5d4..5853d814ef26b 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -427,7 +427,7 @@ bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, struct ttm_resource *res = bo->resource; struct ttm_device *bdev = bo->bdev; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (bo->resource->mem_type == TTM_PL_SYSTEM) return true; From 71738ab65ffa47cd324e9ab510884359d5539c40 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 18 Aug 2021 10:51:54 +0800 Subject: [PATCH 0538/2653] drm/amdkcl: DROPME rework config.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 69 ++++++++++++++++++++---- 1 file changed, 59 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index bce21674fb244..b8d0184b66fa5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -11,7 +11,7 @@ #define HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS 1 /* acpi_put_table() is available */ -#define HAVE_ACPI_PUT_TABLE 1 +/* #undef HAVE_ACPI_PUT_TABLE */ /* struct acpi_srat_generic_affinity is available */ #define HAVE_ACPI_SRAT_GENERIC_AFFINITY 1 @@ -29,7 +29,7 @@ #define HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 1 /* amd_iommu_pc_supported() is available */ -#define HAVE_AMD_IOMMU_PC_SUPPORTED 1 +/* #undef HAVE_AMD_IOMMU_PC_SUPPORTED */ /* arch_io_{reserve/free}_memtype_wc() are available */ #define HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC 1 @@ -115,6 +115,12 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_AMDGPU_PCIID_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_AMD_ASIC_TYPE_H 1 + +/* drm_aperture_remove_* is availablea */ +#define HAVE_DRM_APERTURE 1 + /* drm_atomic_get_old_crtc_state() and drm_atomic_get_new_crtc_state() are available */ #define HAVE_DRM_ATOMIC_GET_CRTC_STATE 1 @@ -128,9 +134,6 @@ /* drm_atomic_helper_check_plane_state() is available */ #define HAVE_DRM_ATOMIC_HELPER_CHECK_PLANE_STATE 1 -/* HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL 1 - /* drm_atomic_helper_shutdown() is available */ #define HAVE_DRM_ATOMIC_HELPER_SHUTDOWN 1 @@ -163,6 +166,12 @@ /* drm_color_lut_size() is available */ #define HAVE_DRM_COLOR_LUT_SIZE 1 +/* drm_connector_atomic_hdr_metadata_equal() is available */ +/* #undef HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL */ + +/* drm_connector_attach_hdr_output_metadata_property() is available */ +/* #undef HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY */ + /* drm_connector_for_each_possible_encoder() wants 2 arguments */ #define HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS 1 @@ -255,6 +264,9 @@ /* drm_dp_atomic_find_vcpi_slots() wants 5args */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS 1 +/* struct drm_dp_aux has member named 'drm_dev' */ +#define HAVE_DRM_DP_AUX_DRM_DEV 1 + /* drm_dp_calc_pbn_mode() wants 3args */ #define HAVE_DRM_DP_CALC_PBN_MODE_3ARGS 1 @@ -264,6 +276,12 @@ /* drm_dp_cec_register_connector() wants p,p interface */ #define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 +/* drm_dp_link_train_channel_eq_delay() has 2 args */ +/* #undef HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS */ + +/* drm_dp_link_train_clock_recovery_delay() has 2 args */ +/* #undef HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS */ + /* drm_dp_mst_add_affected_dsc_crtcs() is available */ #define HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS 1 @@ -324,6 +342,9 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRMP_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_APERTURE_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_ATOMIC_UAPI_H 1 @@ -423,13 +444,13 @@ #define HAVE_DRM_FB_HELPER_LASTCLOSE 1 /* drm_fb_helper_remove_conflicting_pci_framebuffers() is available */ -#define HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS 1 +/* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ /* drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args */ /* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP */ /* drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args */ -#define HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP 1 +/* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ /* drm_fb_helper_set_suspend_unlocked() is available */ #define HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED 1 @@ -455,6 +476,9 @@ /* ttm_buffer_object->base is available */ #define HAVE_DRM_GEM_OBJECT_RESV 1 +/* drm_gem_prime_mmap() is available */ +/* #undef HAVE_DRM_GEM_PRIME_MMAP */ + /* drm_gem_ttm_vmap() is available */ #define HAVE_DRM_GEM_TTM_VMAP 1 @@ -465,7 +489,7 @@ #define HAVE_DRM_GET_FORMAT_INFO 1 /* drm_get_format_name() has i,p interface */ -#define HAVE_DRM_GET_FORMAT_NAME_I_P 1 +/* #undef HAVE_DRM_GET_FORMAT_NAME_I_P */ /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 @@ -491,6 +515,9 @@ /* drm_kms_helper_is_poll_worker() is available */ #define HAVE_DRM_KMS_HELPER_IS_POLL_WORKER 1 +/* drm_memcpy_from_wc() is availablea */ +#define HAVE_DRM_MEMCPY_FROM_WC 1 + /* whether drm_mm_insert_mode is available */ #define HAVE_DRM_MM_INSERT_MODE 1 @@ -630,6 +657,15 @@ /* in_compat_syscall is defined */ #define HAVE_IN_COMPAT_SYSCALL 1 +/* io_mapping_map_local_wc() is available */ +#define HAVE_IO_MAPPING_MAP_LOCAL_WC 1 + +/* io_mapping_unmap_local() is available */ +#define HAVE_IO_MAPPING_UNMAP_LOCAL 1 + +/* is_cow_mapping() is available */ +#define HAVE_IS_COW_MAPPING 1 + /* jiffies64_to_msecs() is available */ #define HAVE_JIFFIES64_TO_MSECS 1 @@ -639,6 +675,9 @@ /* kernel_write() take arg type of position as pointer */ #define HAVE_KERNEL_WRITE_PPOS 1 +/* kmap_local_page_prot() is available */ +#define HAVE_KMAP_LOCAL_PAGE_PROT 1 + /* kref_read() function is available */ #define HAVE_KREF_READ 1 @@ -789,6 +828,9 @@ /* pci_dev_id() is available */ #define HAVE_PCI_DEV_ID 1 +/* struct pci_driver has field dev_groups */ +#define HAVE_PCI_DRIVER_DEV_GROUPS 1 + /* pci_is_thunderbolt_attached() is available */ #define HAVE_PCI_IS_THUNDERBOLD_ATTACHED 1 @@ -820,7 +862,7 @@ #define HAVE_PXM_TO_NODE 1 /* remove_conflicting_framebuffers() returns int */ -/* #undef HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT */ +#define HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT 1 /* request_firmware_direct() is available */ #define HAVE_REQUEST_FIRMWARE_DIRECT 1 @@ -873,6 +915,9 @@ /* crtc->funcs->gamma_set() wants 6 args */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS 1 +/* HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL 1 + /* struct drm_crtc_funcs->get_vblank_timestamp() is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP 1 @@ -912,6 +957,10 @@ /* drm_plane_helper_funcs->atomic_async_check() is available */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK 1 +/* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state + arg */ +/* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS */ + /* drm_plane_helper_funcs->prepare_fb() wants const p arg */ /* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_CONST */ @@ -924,7 +973,7 @@ /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ -/* sysfs_emit() and sysfs_emit_at are available */ +/* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 /* timer_setup() is available */ From 7195fab47f05a4b64aa2dfd94e84b826b96037ec Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 20 Aug 2021 17:45:09 +0800 Subject: [PATCH 0539/2653] drm/amdkcl: fake drm_gem_mmap for drm_gem_prime_mmap for legacy ps This is caused by following commits: 71df0368e9b6 drm/amdgpu: Implement mmap as GEM object function 47d35c1c40d5 drm: Set vm_ops to GEM object's values during mmap Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 48 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 6 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 84 ++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 4 + drivers/gpu/drm/amd/backport/Makefile | 2 +- drivers/gpu/drm/amd/backport/backport.h | 1 + .../backport/include/kcl/kcl_amdgpu_drm_gem.h | 49 ++++++ drivers/gpu/drm/amd/backport/kcl_drm_gem.c | 149 ++++++++++++++++++ drivers/gpu/drm/ttm/ttm_bo_vm.c | 77 +++++++++ include/drm/ttm/ttm_bo.h | 14 ++ include/drm/ttm/ttm_device.h | 18 +++ 12 files changed, 454 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem.h create mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_gem.c diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 30b891c50e310..1364f566c8b66 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -43,6 +43,54 @@ #include #include +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +/** + * amdgpu_gem_prime_mmap - &drm_driver.gem_prime_mmap implementation + * @obj: GEM BO + * @vma: Virtual memory area + * + * Sets up a userspace mapping of the BO's memory in the given + * virtual memory area. + * + * Returns: + * 0 on success or a negative error code on failure. + */ +int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, + struct vm_area_struct *vma) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + unsigned asize = amdgpu_bo_size(bo); + int ret; + + if (!vma->vm_file) + return -ENODEV; + + if (adev == NULL) + return -ENODEV; + + /* Check for valid size. */ + if (asize < vma->vm_end - vma->vm_start) + return -EINVAL; + + if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) || + (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { + return -EPERM; + } + vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT; + + /* prime mmap does not need to check access, so allow here */ + ret = drm_vma_node_allow(&obj->vma_node, vma->vm_file->private_data); + if (ret) + return ret; + + ret = ttm_bo_mmap(vma->vm_file, vma, &adev->mman.bdev); + drm_vma_node_revoke(&obj->vma_node, vma->vm_file->private_data); + + return ret; +} +#endif + #if defined(AMDKCL_AMDGPU_DMABUF_OPS) static int __dma_resv_make_exclusive(struct dma_resv *obj) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h index f7a7492b68f55..dbc9384febd43 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h @@ -54,6 +54,12 @@ bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev, struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); #endif +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, + struct vm_area_struct *vma); +#endif + + extern const struct dma_buf_ops amdgpu_dmabuf_ops; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 7a992fc12e4f7..730a51c2bce03 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3057,7 +3057,7 @@ static const struct file_operations amdgpu_driver_kms_fops = { .flush = amdgpu_flush, .release = amdgpu_drm_release, .unlocked_ioctl = amdgpu_drm_ioctl, - .mmap = drm_gem_mmap, + .mmap = amdkcl_drm_gem_mmap, .poll = drm_poll, .read = drm_read, #ifdef CONFIG_COMPAT @@ -3188,7 +3188,8 @@ static struct drm_driver amdgpu_kms_driver = { .gem_prime_vunmap = drm_gem_ttm_vunmap, #endif - .gem_prime_mmap = drm_gem_prime_mmap, + .gem_prime_mmap = amdkcl_drm_gem_prime_mmap, + .name = DRIVER_NAME, .desc = DRIVER_DESC, .major = KMS_DRIVER_MAJOR, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index a305fab51a043..e23a69c64bb0c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -171,6 +171,27 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, *placement = abo->placement; } +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +/** + * amdgpu_verify_access - Verify access for a mmap call + * + * @bo: The buffer object to map + * @filp: The file pointer from the process performing the mmap + * + * This is called by ttm_bo_mmap() to verify whether a process + * has the right to mmap a BO to their process space. + */ +static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) +{ + struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); + + if (amdgpu_ttm_tt_get_usermm(bo->ttm)) + return -EPERM; + return drm_vma_node_verify_access(&abo->tbo.base.vma_node, + filp->private_data); +} +#endif + /** * amdgpu_ttm_map_buffer - Map memory into the GART windows * @bo: buffer object to map @@ -1885,6 +1906,9 @@ static struct ttm_device_funcs amdgpu_bo_driver = { .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, .evict_flags = &amdgpu_evict_flags, .move = &amdgpu_bo_move, +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + .verify_access = &amdgpu_verify_access, +#endif .delete_mem_notify = &amdgpu_bo_delete_mem_notify, .release_notify = &amdgpu_bo_release_notify, .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, @@ -2739,6 +2763,66 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, DMA_RESV_USAGE_BOOKKEEP); } +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG +static vm_fault_t amdgpu_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ + struct ttm_buffer_object *bo = vma->vm_private_data; +#else +static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf) +{ + struct ttm_buffer_object *bo = vmf->vma->vm_private_data; +#endif + vm_fault_t ret; + +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG + ret = ttm_bo_vm_reserve(bo, vmf, vma); +#else + ret = ttm_bo_vm_reserve(bo, vmf); +#endif + if (ret) + return ret; + + ret = amdgpu_bo_fault_reserve_notify(bo); + if (ret) + goto unlock; + +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG + ret = ttm_bo_vm_fault_reserved(vmf, vma, vma->vm_page_prot, TTM_BO_VM_NUM_PREFAULT); +#else + ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, + TTM_BO_VM_NUM_PREFAULT); +#endif + if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) + return ret; + +unlock: + dma_resv_unlock(amdkcl_ttm_resvp(bo)); + return ret; +} + +static struct vm_operations_struct amdgpu_ttm_vm_ops = { + .fault = amdgpu_ttm_fault, + .open = ttm_bo_vm_open, + .close = ttm_bo_vm_close, + .access = ttm_bo_vm_access +}; + +int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) +{ + struct drm_file *file_priv = filp->private_data; + struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev); + int r; + + r = ttm_bo_mmap(filp, vma, &adev->mman.bdev); + if (unlikely(r != 0)) + return r; + + vma->vm_ops = &amdgpu_ttm_vm_ops; + return 0; +} +#endif /* HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ + int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, uint64_t dst_offset, uint32_t byte_count, struct dma_resv *resv, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 3b07e86e4beca..747c9669069a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -195,6 +195,10 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, struct dma_fence **fence, bool delayed); +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); +#endif + int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index ba3805d29cbc3..fa78abd428129 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: MIT BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ - kcl_drm_gem_framebuffer_helper.o + kcl_drm_gem_framebuffer_helper.o kcl_drm_gem.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 810a40bc1d1d6..e10a0d22ed94b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -72,6 +72,7 @@ #include "kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" +#include "kcl/kcl_amdgpu_drm_gem.h" #include "kcl/kcl_drm_gem_ttm_helper.h" #include "kcl/kcl_drm_aperture.h" diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem.h new file mode 100644 index 0000000000000..9ad60a7646fa0 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem.h @@ -0,0 +1,49 @@ +/* + * GEM Graphics Execution Manager Driver Interfaces + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * All rights reserved. + * Copyright © 2014 Intel Corporation + * Daniel Vetter + * + * Author: Rickard E. (Rik) Faith + * Author: Gareth Hughes + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_H__ +#define __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_H__ + +int _kcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma); + +static inline int amdkcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { + return _kcl_drm_gem_mmap(filp, vma); +} + + +int _kcl_drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); + +static inline int amdkcl_drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { + return _kcl_drm_gem_prime_mmap(obj, vma); +} + +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c new file mode 100644 index 0000000000000..328395cbd0125 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c @@ -0,0 +1,149 @@ +/* + * Copyright © 2008 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include +#include "amdgpu_ttm.h" +#include "amdgpu_dma_buf.h" + +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int _kcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { + return amdgpu_mmap(filp, vma); +} + +int _kcl_drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { + return amdgpu_gem_prime_mmap(obj, vma); +} + +#else +static int _kcl_drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, + struct vm_area_struct *vma) +{ + int ret; + + /* Check for valid size. */ + if (obj_size < vma->vm_end - vma->vm_start) + return -EINVAL; + + /* Take a ref for this mapping of the object, so that the fault + * handler can dereference the mmap offset's pointer to the object. + * This reference is cleaned up by the corresponding vm_close + * (which should happen whether the vma was created by this call, or + * by a vm_open due to mremap or partial unmap or whatever). + */ + drm_gem_object_get(obj); + + vma->vm_private_data = obj; + vma->vm_ops = obj->funcs->vm_ops; + + if (obj->funcs->mmap) { + ret = obj->funcs->mmap(obj, vma); + if (ret) + goto err_drm_gem_object_put; + WARN_ON(!(vma->vm_flags & VM_DONTEXPAND)); + } else { + if (!vma->vm_ops) { + ret = -EINVAL; + goto err_drm_gem_object_put; + } + + vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP; + vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); + vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); + } + + return 0; + +err_drm_gem_object_put: + drm_gem_object_put(obj); + return ret; +} + +int _kcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { + struct drm_file *priv = filp->private_data; + struct drm_device *dev = priv->minor->dev; + struct drm_gem_object *obj = NULL; + struct drm_vma_offset_node *node; + int ret; + + if (drm_dev_is_unplugged(dev)) + return -ENODEV; + + drm_vma_offset_lock_lookup(dev->vma_offset_manager); + node = drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager, + vma->vm_pgoff, + vma_pages(vma)); + if (likely(node)) { + obj = container_of(node, struct drm_gem_object, vma_node); + /* + * When the object is being freed, after it hits 0-refcnt it + * proceeds to tear down the object. In the process it will + * attempt to remove the VMA offset and so acquire this + * mgr->vm_lock. Therefore if we find an object with a 0-refcnt + * that matches our range, we know it is in the process of being + * destroyed and will be freed as soon as we release the lock - + * so we have to check for the 0-refcnted object and treat it as + * invalid. + */ + if (!kref_get_unless_zero(&obj->refcount)) + obj = NULL; + } + drm_vma_offset_unlock_lookup(dev->vma_offset_manager); + + if (!obj) + return -EINVAL; + + if (!drm_vma_node_is_allowed(node, priv)) { + drm_gem_object_put(obj); + return -EACCES; + } + + if (node->readonly) { + if (vma->vm_flags & VM_WRITE) { + drm_gem_object_put(obj); + return -EINVAL; + } + + vma->vm_flags &= ~VM_MAYWRITE; + } + + ret = _kcl_drm_gem_mmap_obj(obj, drm_vma_node_size(node) << PAGE_SHIFT, + vma); + + drm_gem_object_put(obj); + + return ret; + +} + +int _kcl_drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { + if (obj->funcs && obj->funcs->mmap) { + vma->vm_ops = obj->funcs->vm_ops; + } + return drm_gem_prime_mmap(obj, vma); +} + +#endif diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 6f155a908a549..83a536863c682 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -513,6 +513,83 @@ static const struct vm_operations_struct ttm_bo_vm_ops = { .access = ttm_bo_vm_access, }; +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +static struct ttm_buffer_object *ttm_bo_vm_lookup(struct ttm_device *bdev, + unsigned long offset, + unsigned long pages) +{ + struct drm_vma_offset_node *node; + struct ttm_buffer_object *bo = NULL; + + drm_vma_offset_lock_lookup(bdev->vma_manager); + + node = drm_vma_offset_lookup_locked(bdev->vma_manager, offset, pages); + if (likely(node)) { + bo = container_of(node, struct ttm_buffer_object, + base.vma_node); + bo = ttm_bo_get_unless_zero(bo); + } + + drm_vma_offset_unlock_lookup(bdev->vma_manager); + + if (!bo) + pr_err("Could not find buffer object to map\n"); + + return bo; +} + +static void ttm_bo_mmap_vma_setup(struct ttm_buffer_object *bo, struct vm_area_struct *vma) +{ + vma->vm_ops = &ttm_bo_vm_ops; + + /* + * Note: We're transferring the bo reference to + * vma->vm_private_data here. + */ + + vma->vm_private_data = bo; + + /* + * We'd like to use VM_PFNMAP on shared mappings, where + * (vma->vm_flags & VM_SHARED) != 0, for performance reasons, + * but for some reason VM_PFNMAP + x86 PAT + write-combine is very + * bad for performance. Until that has been sorted out, use + * VM_MIXEDMAP on all mappings. See freedesktop.org bug #75719 + */ + vma->vm_flags |= VM_PFNMAP; + vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP; +} + +int ttm_bo_mmap(struct file *filp, struct vm_area_struct *vma, + struct ttm_device *bdev) +{ + struct ttm_buffer_object *bo; + int ret; + + if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET_START)) + return -EINVAL; + + bo = ttm_bo_vm_lookup(bdev, vma->vm_pgoff, vma_pages(vma)); + if (unlikely(!bo)) + return -EINVAL; + + if (unlikely(!bo->bdev->funcs->verify_access)) { + ret = -EPERM; + goto out_unref; + } + ret = bo->bdev->funcs->verify_access(bo, filp); + if (unlikely(ret != 0)) + goto out_unref; + + ttm_bo_mmap_vma_setup(bo, vma); + return 0; +out_unref: + ttm_bo_put(bo); + return ret; +} +EXPORT_SYMBOL(ttm_bo_mmap); +#endif /* HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ + /** * ttm_bo_mmap_obj - mmap memory backed by a ttm buffer object. * diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h index 0a0727af7011f..3e67b442400e3 100644 --- a/include/drm/ttm/ttm_bo.h +++ b/include/drm/ttm/ttm_bo.h @@ -430,6 +430,20 @@ void *ttm_bo_kmap_try_from_panic(struct ttm_buffer_object *bo, unsigned long pag int ttm_bo_vmap(struct ttm_buffer_object *bo, struct iosys_map *map); void ttm_bo_vunmap(struct ttm_buffer_object *bo, struct iosys_map *map); int ttm_bo_mmap_obj(struct vm_area_struct *vma, struct ttm_buffer_object *bo); + +/** + * ttm_bo_mmap - mmap out of the ttm device address space. + * + * @filp: filp as input from the mmap method. + * @vma: vma as input from the mmap method. + * @bdev: Pointer to the ttm_device with the address space manager. + * + * This function is intended to be called by the device mmap method. + * if the device address space is to be backed by the bo manager. + */ +int ttm_bo_mmap(struct file *filp, struct vm_area_struct *vma, + struct ttm_device *bdev); + s64 ttm_bo_swapout(struct ttm_device *bdev, struct ttm_operation_ctx *ctx, struct ttm_resource_manager *man, gfp_t gfp_flags, s64 target); diff --git a/include/drm/ttm/ttm_device.h b/include/drm/ttm/ttm_device.h index 592b5f8028599..2f59de87d5a8c 100644 --- a/include/drm/ttm/ttm_device.h +++ b/include/drm/ttm/ttm_device.h @@ -151,6 +151,24 @@ struct ttm_device_funcs { struct ttm_resource *new_mem, struct ttm_place *hop); +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + /** + * struct ttm_bo_driver_member verify_access + * + * @bo: Pointer to a buffer object. + * @filp: Pointer to a struct file trying to access the object. + * + * Called from the map / write / read methods to verify that the + * caller is permitted to access the buffer object. + * This member may be set to NULL, which will refuse this kind of + * access for all buffer objects. + * This function should return 0 if access is granted, -EPERM otherwise. + */ + int (*verify_access)(struct ttm_buffer_object *bo, + struct file *filp); +#endif + + /** * Hook to notify driver about a resource delete. */ From b7ab7a89721e167e18866b5044f79191a3caf218 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 23 Aug 2021 10:22:00 +0800 Subject: [PATCH 0540/2653] drm/amdkcl: wrap the code under macro drmm_add_action_or_reset This is caused by 267d51d77fda "drm/amdgpu: Implement mmap as GEM object function" v5.13-rc1-231-g267d51d77fda Signed-off-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_bo_vm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 83a536863c682..b7d8aa9bfb4e1 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -331,8 +331,10 @@ vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, pgprot_t prot) return VM_FAULT_OOM; /* Set the page to be freed using drmm release action */ +#ifdef drmm_add_action_or_reset if (drmm_add_action_or_reset(ddev, ttm_bo_release_dummy_page, page)) return VM_FAULT_OOM; +#endif pfn = page_to_pfn(page); From 5897c6540bdcef81b1ae634d97e33bb186d99fd1 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 23 Aug 2021 11:06:02 +0800 Subject: [PATCH 0541/2653] drm/amdkcl: Test whether dma_buf_unpin() is available This is caused by a448cb003edc "drm/amdgpu: implement amdgpu_gem_prime_move_notify v2" v5.6-rc2-339-ga448cb003edc Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 | 34 ++++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 329bd8e2ceafe..cdf26f4df7fce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1049,8 +1049,10 @@ void amdgpu_bo_unpin(struct amdgpu_bo *bo) if (bo->tbo.pin_count) return; +#ifdef HAVE_DMA_BUF_UNPIN if (drm_gem_is_imported(&bo->tbo.base)) dma_buf_unpin(bo->tbo.base.import_attach); +#endif if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 new file mode 100644 index 0000000000000..4c07a856211f9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 @@ -0,0 +1,34 @@ +dnl # +dnl # v5.6-rc2-335-gbb42df4662a4 +dnl # dma-buf: add dynamic DMA-buf handling v15 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_BUF_UNPIN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + dma_buf_unpin(NULL); + ],[ + AC_DEFINE(HAVE_DMA_BUF_UNPIN, 1, + [dma_buf_unpin() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DMA_BUF_OPS_UNPIN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct dma_buf_ops *ptr = NULL; + ptr->unpin(NULL); + ],[ + AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_UNPIN, 1, + [struct dma_buf_ops->unpin() is available]) + ]) + ]) +]) + + + + From 700f92ecdbfd3f198e54ef99da08b74697a5dc45 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 23 Aug 2021 12:46:55 +0800 Subject: [PATCH 0542/2653] drm/amdkcl: Test whether linux/pgtable.h is available This is caused by 3bf3710e3718 "drm/ttm: Add a generic TTM memcpy move for page-based iomem" v5.13-rc3-860-g3bf3710e3718 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ drivers/gpu/drm/ttm/ttm_module.c | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 5c9cf41e67120..05687ebbd1ec7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -56,4 +56,10 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/aperture: Add infrastructure for aperture ownership dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_aperture.h]) + + dnl # + dnl # v5.7-13141-gca5999fde0a1 + dnl # mm: introduce include/linux/pgtable.h + dnl # + AC_KERNEL_CHECK_HEADERS([linux/pgtable.h]) ]) diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c index b3fffe7b5062a..7e8366ece9d6d 100644 --- a/drivers/gpu/drm/ttm/ttm_module.c +++ b/drivers/gpu/drm/ttm/ttm_module.c @@ -31,7 +31,9 @@ */ #include #include +#ifdef HAVE_LINUX_PGTABLE_H #include +#endif #include #include #include From ea52da3a19362ea314601f6acc15e33989e9c4a2 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 23 Aug 2021 14:20:05 +0800 Subject: [PATCH 0543/2653] drm/amdkcl: wrap the code under macro HAVE_DRM_DRIVER_RELEASE This is caused by 07775fc13878 "drm/amdgpu: Unmap all MMIO mappings" v5.13-rc1-246-g07775fc13878 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 6605cff1d8683..ee4a434a339fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4859,7 +4859,11 @@ static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev) { /* Clear all CPU mappings pointing to this device */ +#ifdef HAVE_DRM_DRIVER_RELEASE unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1); +#else + unmap_mapping_range(adev->ddev->anon_inode->i_mapping, 0, 0, 1); +#endif /* Unmap all mapped bars - Doorbell, registers and VRAM */ amdgpu_doorbell_fini(adev); From 17244b20172b8129573d851ba26f5e53d825b59a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 23 Aug 2021 14:23:20 +0800 Subject: [PATCH 0544/2653] drm/amdkcl: wrap the code under macro HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 8def53a4e47d1..c77bccb33470b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -444,6 +444,7 @@ static void amdgpu_gem_object_close(struct drm_gem_object *obj, drm_exec_fini(&exec); } +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); @@ -464,6 +465,7 @@ static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_str return drm_gem_ttm_mmap(obj, vma); } +#endif #ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { From b3445311e01d93956048dbad1cfec45814394c91 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 24 Aug 2021 11:02:08 +0800 Subject: [PATCH 0545/2653] drm/amdkcl: adapt code for remove_conflicting_pci_framebuffers with argument numbers Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 6 +++ drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 40 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../m4/remove-conflicting-pci-framebuffers.m4 | 26 ++++++++++++ include/kcl/kcl_drm_fb.h | 14 +++++++ 5 files changed, 87 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c index b3fa22920b7f2..99c29f3b4c803 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -126,7 +126,13 @@ int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const #ifdef HAVE_VGA_REMOVE_VGACON #if IS_REACHABLE(CONFIG_FB) + +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG ret = remove_conflicting_pci_framebuffers(pdev, name); +#else + ret = remove_conflicting_pci_framebuffers(pdev, 0, name); +#endif + #endif if (ret == 0) ret = vga_remove_vgacon(pdev); diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c index 11a2fe7ab066e..18f2a20d821da 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -15,6 +15,44 @@ /* Copied from drivers/video/fbdev/core/fbmem.c and modified for KCL */ #if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) + +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG +int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) +{ + struct apertures_struct *ap; + bool primary = false; + int err, idx, bar; + + for (idx = 0, bar = 0; bar < PCI_STD_NUM_BARS; bar++) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + idx++; + } + + ap = alloc_apertures(idx); + if (!ap) + return -ENOMEM; + + for (idx = 0, bar = 0; bar < PCI_STD_NUM_BARS; bar++) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + ap->ranges[idx].base = pci_resource_start(pdev, bar); + ap->ranges[idx].size = pci_resource_len(pdev, bar); + pci_dbg(pdev, "%s: bar %d: 0x%lx -> 0x%lx\n", __func__, bar, + (unsigned long)pci_resource_start(pdev, bar), + (unsigned long)pci_resource_end(pdev, bar)); + idx++; + } + +#ifdef CONFIG_X86 + primary = pdev->resource[PCI_ROM_RESOURCE].flags & + IORESOURCE_ROM_SHADOW; +#endif + err = remove_conflicting_framebuffers(ap, name, primary); + kfree(ap); + return err; +} +#else /* HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG */ int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const char *name) { struct apertures_struct *ap; @@ -39,5 +77,7 @@ int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const kfree(ap); return err; } +#endif /* HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG */ + EXPORT_SYMBOL(remove_conflicting_pci_framebuffers); #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 411a68f7db3c8..14f5a1c25c6c2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -164,6 +164,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_BUF_UNPIN AC_AMDGPU_STRUCT_DMA_BUF_OPS_UNPIN AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA + AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 new file mode 100644 index 0000000000000..06241044fe4d4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 @@ -0,0 +1,26 @@ +dnl # +dnl # v5.3-rc1-540-g0a8459693238 +dnl # fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers +dnl # +AC_DEFUN([AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + remove_conflicting_pci_framebuffers(NULL, NULL); + ],[ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG, 1, + [remove_conflicting_pci_framebuffers() is available and doesn't have res_id arg]) + ],[ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + remove_conflicting_pci_framebuffers(NULL, 0, NULL); + ], [ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_WITH_RES_ID_ARG, 1, + [remove_conflicting_pci_framebuffers() is available and has res_id arg]) + ]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 2b90f5bcd8682..2e66b7b2aa2fa 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -77,14 +77,24 @@ __and(IS_MODULE(option), __is_defined(MODULE))) #endif /*IS_REACHABLE*/ +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG +extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const char *name); +#else extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const char *name); +#endif + static inline int _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) { #if IS_REACHABLE(CONFIG_FB) +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG + return remove_conflicting_pci_framebuffers(pdev, name); +#else return remove_conflicting_pci_framebuffers(pdev, 0, name); +#endif #else return 0; #endif @@ -94,7 +104,11 @@ static inline int _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) { +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_WITH_RES_ID_ARG return drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, name); +#else + return drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, name); +#endif } #endif /* HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ From ec7dcf3d5e411fd18fa8649d3baafdefcad7b75d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 24 Aug 2021 13:22:55 +0800 Subject: [PATCH 0546/2653] drm/amdkcl: fake drm_dev_{enter, exit, is_unplugged} for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c | 73 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 | 19 +++++ .../drm/amd/dkms/m4/drm-dev-is-unplugged.m4 | 21 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_drm_drv.h | 66 +++++++++++++++++ 8 files changed, 185 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 create mode 100644 include/kcl/kcl_drm_drv.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 662dbafdd44d2..a26c5110afa79 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -11,7 +11,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ - kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o + kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ + kcl_drm_drv.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c new file mode 100644 index 0000000000000..8014069a7c654 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c @@ -0,0 +1,73 @@ +/* + * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org + * + * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Author Rickard E. (Rik) Faith + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef HAVE_DRM_DEV_ENTER +#include +#include + +DEFINE_STATIC_SRCU(drm_unplug_srcu); + +/** + * drm_dev_enter - Enter device critical section + * @dev: DRM device + * @idx: Pointer to index that will be passed to the matching drm_dev_exit() + * + * This function marks and protects the beginning of a section that should not + * be entered after the device has been unplugged. The section end is marked + * with drm_dev_exit(). Calls to this function can be nested. + * + * Returns: + * True if it is OK to enter the section, false otherwise. + */ +bool drm_dev_enter(struct drm_device *dev, int *idx) +{ + *idx = srcu_read_lock(&drm_unplug_srcu); + + if (atomic_read(&dev->unplugged)) { + srcu_read_unlock(&drm_unplug_srcu, *idx); + return false; + } + + return true; +} +EXPORT_SYMBOL(drm_dev_enter); + +/** + * drm_dev_exit - Exit device critical section + * @idx: index returned from drm_dev_enter() + * + * This function marks the end of a section that should not be entered after + * the device has been unplugged. + */ +void drm_dev_exit(int idx) +{ + srcu_read_unlock(&drm_unplug_srcu, idx); +} +EXPORT_SYMBOL(drm_dev_exit); + +#endif /* HAVE_DRM_DEV_ENTER */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e10a0d22ed94b..b2b923f962a40 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -51,6 +51,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 new file mode 100644 index 0000000000000..4ac5579c0f5c2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit bee330f3d67273a68dcb99f59480d59553c008b2 +dnl # drm: Use srcu to protect drm_device.unplugged +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEV_ENTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DRMP_H + #include + #else + #include + #endif + ], [ + drm_dev_enter(NULL, NULL); + ], [drm_dev_enter], [drivers/gpu/drm/drm_drv.c], [ + AC_DEFINE(HAVE_DRM_DEV_ENTER, 1, [drm_dev_enter() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 new file mode 100644 index 0000000000000..4a05d157649e4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit bee330f3d67273a68dcb99f59480d59553c008b2 +dnl # drm: Use srcu to protect drm_device.unplugged +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEV_IS_UNPLUGGED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + #include + #endif + #ifdef HAVE_DRM_DRM_DRV_H + #include + #endif + ], [ + drm_dev_is_unplugged(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DEV_IS_UNPLUGGED, 1, + [drm_dev_is_unplugged() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 14f5a1c25c6c2..926512d22c49f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -165,6 +165,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DMA_BUF_OPS_UNPIN AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS + AC_AMDGPU_DRM_DEV_ENTER + AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index e6763a9dfb224..97ee04f8c9330 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_drm_drv.h b/include/kcl/kcl_drm_drv.h new file mode 100644 index 0000000000000..b4e923bfa1465 --- /dev/null +++ b/include/kcl/kcl_drm_drv.h @@ -0,0 +1,66 @@ +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * Copyright 2016 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __KCL_KCL_DRM_DRV_H__ +#define __KCL_KCL_DRM_DRV_H__ + +#include +#include + +#ifndef HAVE_DRM_DEV_ENTER +/* Copied from include/drm/drm_drv.h*/ + +bool drm_dev_enter(struct drm_device *dev, int *idx); +void drm_dev_exit(int idx); + +#ifndef HAVE_DRM_DEV_IS_UNPLUGGED +/** + * drm_dev_is_unplugged - is a DRM device unplugged + * @dev: DRM device + * + * This function can be called to check whether a hotpluggable is unplugged. + * Unplugging itself is singalled through drm_dev_unplug(). If a device is + * unplugged, these two functions guarantee that any store before calling + * drm_dev_unplug() is visible to callers of this function after it completes + * + * WARNING: This function fundamentally races against drm_dev_unplug(). It is + * recommended that drivers instead use the underlying drm_dev_enter() and + * drm_dev_exit() function pairs. + */ +static inline bool drm_dev_is_unplugged(struct drm_device *dev) +{ + int idx; + + if (drm_dev_enter(dev, &idx)) { + drm_dev_exit(idx); + return false; + } + + return true; +} +#endif /* HAVE_DRM_DEV_IS_UNPLUGGED */ +#endif /* HAVE_DRM_DEV_ENTER */ + +#endif From 700eec19837bfc2a0bacc46a3522c871aa1dd625 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 24 Aug 2021 13:52:05 +0800 Subject: [PATCH 0547/2653] drm/amdkcl: replace dma_resv_get_list with dma_resv_shared_list Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_reservation.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c index 5bb5b8b68e64e..bad215a62e54d 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c @@ -164,7 +164,7 @@ void _kcl_dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fenc { struct dma_resv_list *old, *fobj = obj->staged; - old = dma_resv_get_list(obj); + old = dma_resv_shared_list(obj); obj->staged = NULL; if (!fobj) From 42d7d8a5507ff107c9c795cdf0b27c384a435747 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 24 Aug 2021 17:29:29 +0800 Subject: [PATCH 0548/2653] drm/amdkcl: REWORKME: config.h Signed-off-by: Leslie Shi Change-Id: Id383189a33e53194d9b6f98879bf1e95a6987243 --- drivers/gpu/drm/amd/dkms/config/config.h | 41 +++++++++++++++++++----- 1 file changed, 33 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b8d0184b66fa5..c517b7649bd82 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -76,6 +76,9 @@ /* dma_buf dynamic_mapping is available */ /* #undef HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING */ +/* dma_buf_unpin() is available */ +#define HAVE_DMA_BUF_UNPIN 1 + /* whether dma_fence_get_stub exits */ #define HAVE_DMA_FENCE_GET_STUB 1 @@ -204,6 +207,9 @@ /* struct drm_connector_state has hdcp_content_type member */ #define HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE 1 +/* struct drm_connector_state has hdr_output_metadata member */ +#define HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA 1 + /* drm_connector_unreference() is available */ /* #undef HAVE_DRM_CONNECTOR_UNREFERENCE */ @@ -243,6 +249,12 @@ /* drm_dev_dbg() is available */ #define HAVE_DRM_DEV_DBG 1 +/* drm_dev_enter() is available */ +#define HAVE_DRM_DEV_ENTER 1 + +/* drm_dev_is_unplugged() is availablea */ +#define HAVE_DRM_DEV_IS_UNPLUGGED 1 + /* drm_dev_put() is available */ #define HAVE_DRM_DEV_PUT 1 @@ -277,10 +289,10 @@ #define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 /* drm_dp_link_train_channel_eq_delay() has 2 args */ -/* #undef HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS */ +#define HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS 1 /* drm_dp_link_train_clock_recovery_delay() has 2 args */ -/* #undef HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS */ +#define HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS 1 /* drm_dp_mst_add_affected_dsc_crtcs() is available */ #define HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS 1 @@ -476,9 +488,6 @@ /* ttm_buffer_object->base is available */ #define HAVE_DRM_GEM_OBJECT_RESV 1 -/* drm_gem_prime_mmap() is available */ -/* #undef HAVE_DRM_GEM_PRIME_MMAP */ - /* drm_gem_ttm_vmap() is available */ #define HAVE_DRM_GEM_TTM_VMAP 1 @@ -675,8 +684,8 @@ /* kernel_write() take arg type of position as pointer */ #define HAVE_KERNEL_WRITE_PPOS 1 -/* kmap_local_page_prot() is available */ -#define HAVE_KMAP_LOCAL_PAGE_PROT 1 +/* kmap_local_* is available */ +#define HAVE_KMAP_LOCAL 1 /* kref_read() function is available */ #define HAVE_KREF_READ 1 @@ -759,6 +768,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PCI_P2PDMA_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_PGTABLE_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_SCHED_MM_H 1 @@ -864,6 +876,13 @@ /* remove_conflicting_framebuffers() returns int */ #define HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT 1 +/* remove_conflicting_pci_framebuffers() is available and doesn't have res_id + arg */ +#define HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG 1 + +/* remove_conflicting_pci_framebuffers() is available and has res_id arg */ +/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_WITH_RES_ID_ARG */ + /* request_firmware_direct() is available */ #define HAVE_REQUEST_FIRMWARE_DIRECT 1 @@ -894,6 +913,9 @@ /* struct dma_buf_ops->pin() is available */ #define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 +/* struct dma_buf_ops->unpin() is available */ +#define HAVE_STRUCT_DMA_BUF_OPS_UNPIN 1 + /* struct drm_connector_state->duplicated is available */ #define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 @@ -959,7 +981,7 @@ /* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg */ -/* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 /* drm_plane_helper_funcs->prepare_fb() wants const p arg */ /* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_CONST */ @@ -991,6 +1013,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_UAPI_LINUX_SCHED_TYPES_H 1 +/* vga_remove_vgacon() is available */ +#define HAVE_VGA_REMOVE_VGACON 1 + /* vga_switcheroo_set_dynamic_switch() exist */ /* #undef HAVE_VGA_SWITCHEROO_SET_DYNAMIC_SWITCH */ From 2c4e938e5a7b14eb7ed00a29ebdf7e889480a3bf Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 25 Aug 2021 10:25:27 +0800 Subject: [PATCH 0549/2653] drm/amdkcl: Test whether struct drm_device has pdev member This is caused by 5c0cd6459c5a "drm/amdkcl: init the ddev->pdev for legacy os" v5.13-2411-g5c0cd6459c5a Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm-device-pdev.m4 | 19 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 25 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 730a51c2bce03..62aded3e42513 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2451,7 +2451,9 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, goto err_free; #endif +#ifdef HAVE_DRM_DEVICE_PDEV ddev->pdev = pdev; +#endif pci_set_drvdata(pdev, ddev); amdgpu_init_debug_options(adev); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c517b7649bd82..d5ac7494a44ac 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -246,6 +246,9 @@ /* drm_device->open_count is int */ /* #undef HAVE_DRM_DEVICE_OPEN_COUNT_INT */ +/* struct drm_device has pdev member */ +/* #undef HAVE_DRM_DEVICE_PDEV */ + /* drm_dev_dbg() is available */ #define HAVE_DRM_DEV_DBG 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 new file mode 100644 index 0000000000000..25f5b1ca72eca --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit b347e04452ff6382ace8fba9c81f5bcb63be17a6 +dnl # drm: Remove pdev field from struct drm_device +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEVICE_PDEV], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + #include + #endif + #include + ], [ + struct drm_device *pdd = NULL; + pdd->pdev = NULL; + ], [ + AC_DEFINE(HAVE_DRM_DEVICE_PDEV, 1, [struct drm_device has pdev member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 926512d22c49f..f3750fc17ae1a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -167,6 +167,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_DEV_ENTER AC_AMDGPU_DRM_DEV_IS_UNPLUGGED + AC_AMDGPU_DRM_DEVICE_PDEV AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 6c77bdc5d62ed419679b77a7da61a720be8c438f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 25 Aug 2021 10:43:19 +0800 Subject: [PATCH 0550/2653] drm/amdkcl: call dma_resv_init for legacy os This is caused by d02117f8efaa "drm/ttm: remove special handling for non GEM drivers" v5.12-rc3-374-gd02117f8efaa Signed-off-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_bo.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 5853d814ef26b..0c98436e7cfbb 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -948,6 +948,11 @@ int ttm_bo_init_reserved(struct ttm_device *bdev, struct ttm_buffer_object *bo, amdkcl_ttm_resvp(bo) = resv; else amdkcl_ttm_resvp(bo) = &amdkcl_ttm_resv(bo); + +#ifndef HAVE_DRM_GEM_OBJECT_RESV + dma_resv_init(&amdkcl_ttm_resv(bo)); +#endif + atomic_inc(&ttm_glob.bo_count); /* From dd9778f3cbf4d8ccd4844183e0128bb9935a0ed7 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 25 Aug 2021 14:05:33 +0800 Subject: [PATCH 0551/2653] drm/amdkcl: wrap the code under macro PCI_IRQ_MSI Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 8112ffc85995e..8cf71e0994592 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -333,7 +333,11 @@ void amdgpu_irq_fini_hw(struct amdgpu_device *adev) free_irq(adev->irq.irq, adev_to_drm(adev)); adev->irq.installed = false; if (adev->irq.msi_enabled) +#ifdef PCI_IRQ_MSI pci_free_irq_vectors(adev->pdev); +#else + pci_disable_msi(adev->pdev); +#endif } amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); From e43480bf80c5d8d6cc1d72143fae3678fc46c282 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 25 Aug 2021 14:08:04 +0800 Subject: [PATCH 0552/2653] drm/amdkcl: drop dma_resv rcu postfix This is caused by d3fae3b3daac "dma-buf: drop the _rcu postfix on function names v3" v5.13-rc3-854-gd3fae3b3daac Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index bb85b41a27078..6e7404787251c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -457,7 +457,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc, goto unreserve; } - r = dma_resv_get_fences_rcu(amdkcl_ttm_resvp(&new_abo->tbo), &work->excl, + r = dma_resv_get_fences(amdkcl_ttm_resvp(&new_abo->tbo), &work->excl, &work->shared_count, &work->shared); if (unlikely(r != 0)) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 1364f566c8b66..1b2c930244399 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -899,7 +899,7 @@ int amdgpu_gem_prime_pin(struct drm_gem_object *obj) * Wait for all shared fences to complete before we switch to future * use of exclusive fence on this prime shared bo. */ - ret = dma_resv_wait_timeout_rcu(bo->tbo.resv, true, false, + ret = dma_resv_wait_timeout(bo->tbo.resv, true, false, MAX_SCHEDULE_TIMEOUT); if (unlikely(ret < 0)) { DRM_DEBUG_PRIME("Fence wait failed: %li\n", ret); From 6024d1416373bed552614984b9b8aa38d7fd8fe8 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 25 Aug 2021 15:14:25 +0800 Subject: [PATCH 0553/2653] drm/amdkcl: add vma parameter for ttm_bo_vm_dummy_page() to adapt legacy os This is caused by 267d51d77fda "drm/ttm: Remap all page faults to per process dummy page." v5.13-rc1-231-g267d51d77fda Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 15 +++++++++++---- drivers/gpu/drm/ttm/ttm_bo_vm.c | 9 +++++++++ 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index c77bccb33470b..e584069220fe9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -156,9 +156,16 @@ amdgpu_gem_update_bo_mapping(struct drm_file *filp, #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK void amdgpu_gem_object_free(struct drm_gem_object *gobj) #else + +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG +static vm_fault_t amdgpu_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ +#else static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) { - struct ttm_buffer_object *bo = vmf->vma->vm_private_data; + struct vm_area_struct *vma = vmf->vma; +#endif + struct ttm_buffer_object *bo = vma->vm_private_data; struct drm_device *ddev = bo->base.dev; vm_fault_t ret; int idx; @@ -174,12 +181,12 @@ static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) goto unlock; } - ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, - TTM_BO_VM_NUM_PREFAULT); + ret = ttm_bo_vm_fault_reserved(vmf, vma->vm_page_prot, + TTM_BO_VM_NUM_PREFAULT); drm_dev_exit(idx); } else { - ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot); + ret = ttm_bo_vm_dummy_page(vmf, vma->vm_page_prot); } if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) return ret; diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index b7d8aa9bfb4e1..52b0ec32ba6f2 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -315,9 +315,14 @@ static void ttm_bo_release_dummy_page(struct drm_device *dev, void *res) __free_page(dummy_page); } +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG +vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, struct vm_area_struct *vma, pgprot_t prot) +{ +#else vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, pgprot_t prot) { struct vm_area_struct *vma = vmf->vma; +#endif struct ttm_buffer_object *bo = vma->vm_private_data; struct drm_device *ddev = bo->base.dev; vm_fault_t ret = VM_FAULT_NOPAGE; @@ -379,7 +384,11 @@ vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf) #endif drm_dev_exit(idx); } else { +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG + ret = ttm_bo_vm_dummy_page(vmf, vma, prot); +#else ret = ttm_bo_vm_dummy_page(vmf, prot); +#endif } if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) return ret; From 458b7e62ee4f57fdc32f0261b82386c01b07e24e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 31 Aug 2021 11:52:31 +0800 Subject: [PATCH 0554/2653] drm/amdkcl: fake drm_gem_ttm_mmap function Signed-off-by: Leslie Shi --- .../include/kcl/kcl_drm_gem_ttm_helper.h | 10 +++++++++ .../drm/amd/backport/kcl_drm_gem_ttm_helper.c | 22 +++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h index 10d002f55b191..e9d8d3fd9d9d8 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h @@ -34,4 +34,14 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, struct drm_file *file_priv); #endif +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int _kcl_drm_gem_ttm_mmap(struct drm_gem_object *gem, + struct vm_area_struct *vma); +static inline +int drm_gem_ttm_mmap(struct drm_gem_object *gem, + struct vm_area_struct *vma) { + return _kcl_drm_gem_ttm_mmap(gem, vma); +} +#endif + #endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c index 5acf8485888f7..b5fb22fa5a50a 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -38,3 +38,25 @@ void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, } EXPORT_SYMBOL(_kcl_drm_gem_ttm_vunmap); #endif + +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int _kcl_drm_gem_ttm_mmap(struct drm_gem_object *gem, + struct vm_area_struct *vma) { + + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); + int ret; + + ret = ttm_bo_mmap_obj(vma, bo); + if (ret < 0) + return ret; + + /* + * ttm has its own object refcounting, so drop gem reference + * to avoid double accounting counting. + */ + drm_gem_object_put(gem); + + return 0; +} +EXPORT_SYMBOL(_kcl_drm_gem_ttm_mmap); +#endif From 6c9b8c7a5da151e124028d5239d638a9c0686755 Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Tue, 3 Aug 2021 14:44:31 -0400 Subject: [PATCH 0555/2653] drm/amdkfd: add parameter force in kfd_process_evict_queues It is to differenciate case scenario for proper behavior when calling evict queues, such as GPU reset doesn't need to roll back restoring partial evicted queues. Signed-off-by: Eric Huang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 8 ++++---- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 12 ++++++------ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 18 ++++++++++-------- 6 files changed, 26 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index a274a937d8bab..1ece28c83485e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -252,7 +252,7 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc) { if (adev->kfd.dev) - kgd2kfd_suspend(adev->kfd.dev, suspend_proc); + kgd2kfd_suspend(adev->kfd.dev, suspend_proc, true); } int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc) @@ -268,7 +268,7 @@ int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc) void amdgpu_amdkfd_suspend_process(struct amdgpu_device *adev) { if (adev->kfd.dev) - kgd2kfd_suspend_process(adev->kfd.dev); + kgd2kfd_suspend_process(adev->kfd.dev, true); } int amdgpu_amdkfd_resume_process(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 051bfa1a98f26..804b36d384826 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -453,9 +453,9 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf); bool kgd2kfd_device_init(struct kfd_dev *kfd, const struct kgd2kfd_shared_resources *gpu_resources); void kgd2kfd_device_exit(struct kfd_dev *kfd); -void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc); +void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc, bool force); int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc); -void kgd2kfd_suspend_process(struct kfd_dev *kfd); +void kgd2kfd_suspend_process(struct kfd_dev *kfd, bool force); int kgd2kfd_resume_process(struct kfd_dev *kfd); int kgd2kfd_pre_reset(struct kfd_dev *kfd, struct amdgpu_reset_context *reset_context); @@ -498,7 +498,7 @@ static inline void kgd2kfd_device_exit(struct kfd_dev *kfd) { } -static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) +static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc, bool force) { } @@ -507,7 +507,7 @@ static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm, bool sync) return 0; } -static inline void kgd2kfd_suspend_process(struct kfd_dev *kfd) +static inline void kgd2kfd_suspend_process(struct kfd_dev *kfd, bool force) { } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 7800651c7c5aa..f87c793860d4d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2670,7 +2670,7 @@ static int criu_restore(struct file *filep, * Set the process to evicted state to avoid running any new queues before all the memory * mappings are ready. */ - ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_RESTORE); + ret = kfd_process_evict_queues(p, false, KFD_QUEUE_EVICTION_CRIU_RESTORE); if (ret) goto exit_unlock; @@ -2789,7 +2789,7 @@ static int criu_process_info(struct file *filep, goto err_unlock; } - ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT); + ret = kfd_process_evict_queues(p, false, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT); if (ret) goto err_unlock; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 65da9b382c32b..6063d6b33805d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -980,7 +980,7 @@ int kgd2kfd_pre_reset(struct kfd_dev *kfd, kfd_smi_event_update_gpu_reset(node, false, reset_context); } - kgd2kfd_suspend(kfd, true); + kgd2kfd_suspend(kfd, true, true); for (i = 0; i < kfd->num_nodes; i++) kfd_signal_reset_event(kfd->nodes[i]); @@ -1048,7 +1048,7 @@ bool kfd_is_locked(struct kfd_dev *kfd) return false; } -void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) +void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc, bool force) { struct kfd_node *node; int i; @@ -1057,7 +1057,7 @@ void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) return; if (suspend_proc) - kgd2kfd_suspend_process(kfd); + kgd2kfd_suspend_process(kfd, force); for (i = 0; i < kfd->num_nodes; i++) { node = kfd->nodes[i]; @@ -1084,7 +1084,7 @@ int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc) return ret; } -void kgd2kfd_suspend_process(struct kfd_dev *kfd) +void kgd2kfd_suspend_process(struct kfd_dev *kfd, bool force) { if (!kfd->init_complete) return; @@ -1092,7 +1092,7 @@ void kgd2kfd_suspend_process(struct kfd_dev *kfd) mutex_lock(&kfd_processes_mutex); /* For first KFD device suspend all the KFD processes */ if (++kfd_locked == 1) - kfd_suspend_all_processes(); + kfd_suspend_all_processes(force); mutex_unlock(&kfd_processes_mutex); } @@ -1173,7 +1173,7 @@ int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) return -ESRCH; WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); - r = kfd_process_evict_queues(p, trigger); + r = kfd_process_evict_queues(p, true, trigger); kfd_unref_process(p); return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index a68f348d0cfc0..2b9697ad0b077 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1121,9 +1121,9 @@ static inline struct kfd_process_device *kfd_process_device_from_gpuidx( } void kfd_unref_process(struct kfd_process *p); -int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger); +int kfd_process_evict_queues(struct kfd_process *p, bool force, uint32_t trigger); int kfd_process_restore_queues(struct kfd_process *p); -void kfd_suspend_all_processes(void); +void kfd_suspend_all_processes(bool force); int kfd_resume_all_processes(void); struct kfd_process_device *kfd_process_device_data_by_id(struct kfd_process *process, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 8539de7fd1838..95f0d3e9af690 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1997,9 +1997,9 @@ struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm) * Eviction is reference-counted per process-device. This means multiple * evictions from different sources can be nested safely. */ -int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger) +int kfd_process_evict_queues(struct kfd_process *p, bool force, uint32_t trigger) { - int r = 0; + int r = 0, r_tmp = 0; int i; unsigned int n_evicted = 0; @@ -2010,15 +2010,17 @@ int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger) kfd_smi_event_queue_eviction(pdd->dev, p->lead_thread->pid, trigger); - r = pdd->dev->dqm->ops.evict_process_queues(pdd->dev->dqm, + r_tmp = pdd->dev->dqm->ops.evict_process_queues(pdd->dev->dqm, &pdd->qpd); /* evict return -EIO if HWS is hang or asic is resetting, in this case * we would like to set all the queues to be in evicted state to prevent * them been add back since they actually not be saved right now. */ - if (r && r != -EIO) { + if (r_tmp && r_tmp != -EIO) { dev_err(dev, "Failed to evict process queues\n"); - goto fail; + r = r_tmp; + if (!force) + goto fail; } n_evicted++; @@ -2222,7 +2224,7 @@ static void evict_process_worker(struct work_struct *work) p->last_evict_timestamp = get_jiffies_64(); pr_debug("Started evicting process pid %d\n", p->lead_thread->pid); - ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_TTM); + ret = kfd_process_evict_queues(p, false, KFD_QUEUE_EVICTION_TRIGGER_TTM); if (!ret) { /* If another thread already signaled the eviction fence, * they are responsible stopping the queues and scheduling @@ -2305,7 +2307,7 @@ static void restore_process_worker(struct work_struct *work) } } -void kfd_suspend_all_processes(void) +void kfd_suspend_all_processes(bool force) { struct kfd_process *p; unsigned int temp; @@ -2313,7 +2315,7 @@ void kfd_suspend_all_processes(void) WARN(debug_evictions, "Evicting all processes"); hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) { - if (kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_SUSPEND)) + if (kfd_process_evict_queues(p, force, KFD_QUEUE_EVICTION_TRIGGER_SUSPEND)) pr_err("Failed to suspend process pid %d\n", p->lead_thread->pid); signal_eviction_fence(p); } From 3e659368c6feb60b8d3256062242afff91da48eb Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Tue, 3 Aug 2021 16:10:43 -0400 Subject: [PATCH 0556/2653] drm/amdgpu: Fix bad page address calculation on Aldebaran Fix normalized address to physical address calculation during page retirement, by using the channel index table instead of channel instance. While at it, do general cleanup, use macros instead of function to fetch UMC instance and channel instance from MCA registers. Signed-off-by: Mukul Joshi Reviewed-by: John Clements --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 661dc33d8c59b..405db4ba15334 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -132,11 +132,6 @@ const char *get_ras_block_str(struct ras_common_if *ras_block) #define BYPASS_INITIALIZATION_ADDRESS 0x1 #ifdef HAVE_SMCA_UMC_V2 -#define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF) -#define GET_UMC_INST_NIBBLE(m) (((m) >> 20) & 0xF) -#define GET_CHAN_INDEX_NIBBLE(m) (((m) >> 12) & 0xF) -#define GPU_ID_OFFSET 8 - static bool notifier_registered = false; static void amdgpu_register_bad_pages_mca_notifier(void); #endif From 647ae90849c36ba044a0cecd19263f984bc34a2b Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 4 Aug 2021 16:38:11 -0500 Subject: [PATCH 0557/2653] drm/amdkcl: Fix the macro for HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER The code body that is used to determine if compile time macro HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER should be enabled or not is incorrect. It references the wrong structure. The correct struct to reference is dma_buf_attach_ops not dma_buf_ops Signed-off-by: Ramesh Errabolu Reviewed-by: Flora Cui Change-Id: I735de6e7aa30ee86159b67846fa5b4de056375a8 --- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d5ac7494a44ac..7594060ba31a2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -911,7 +911,7 @@ #define HAVE_STRSCPY 1 /* struct dma_buf_ops->allow_peer2peer is available */ -/* #undef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER */ +#define HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER 1 /* struct dma_buf_ops->pin() is available */ #define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 index 3f408896f437b..e402bf57f2ec6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -7,12 +7,12 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ AC_KERNEL_TRY_COMPILE([ #include ],[ - struct dma_buf_ops *ptr = NULL; + struct dma_buf_attach_ops *ptr = NULL; ptr->allow_peer2peer = false; ],[ AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER, 1, - [struct dma_buf_ops->allow_peer2peer is available]) + [struct dma_buf_attach_ops->allow_peer2peer is available]) ],[ dnl # dnl # 4981cdb063e3 dma-buf: make move_notify mandatory if importer_ops are provided From fe9f52434d41bb360ff2f02e1a6e0f111960401d Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Thu, 12 Aug 2021 12:17:30 -0400 Subject: [PATCH 0558/2653] drm/amdkcl: Add XEC macro v2 v2: Change header from kcl_xec.h to kcl_mce.h Signed-off-by: Kent Russell Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_mce.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/kcl/kcl_mce.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b2b923f962a40..b9f8ad0f5d7f2 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -75,6 +75,7 @@ #include "kcl/kcl_amdgpu_drm_drv.h" #include "kcl/kcl_amdgpu_drm_gem.h" #include "kcl/kcl_drm_gem_ttm_helper.h" +#include "kcl/kcl_mce.h" #include "kcl/kcl_drm_aperture.h" #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_mce.h b/include/kcl/kcl_mce.h new file mode 100644 index 0000000000000..037fb0c1b3e37 --- /dev/null +++ b/include/kcl/kcl_mce.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_MCE_H +#define AMDKCL_MCE_H + +#include +/* Copied from asm/mce.h */ +#ifndef XEC +#define XEC(x, mask) (((x) >> 16) & mask) +#endif + +#endif From 7b3e88d9693ea5e86e09c97645619f1d0830d301 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Thu, 12 Aug 2021 20:09:20 -0500 Subject: [PATCH 0559/2653] Use DMABUF for remote VRAM BOs only if CONFIG_PCI_P2PDMA is SET Without CONFIG_PCI_P2PDMA, pci_p2pdma_distance_many will always fail. This will cause DMABUF implementation to migrate VRAM BOs to GTT domain. Therefore, use DMABuf for remote VRAM mappings only if CONFIG_PCI_P2PDMA is enabled. Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 5db1cd45a2e62..a24218062173a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -861,7 +861,7 @@ static int kfd_mem_attach_vram_bo(struct amdgpu_device *adev, { int ret = 0; -#ifdef CONFIG_DMABUF_MOVE_NOTIFY +#if defined(CONFIG_DMABUF_MOVE_NOTIFY) && defined(CONFIG_PCI_P2PDMA) attachment->type = KFD_MEM_ATT_DMABUF; ret = kfd_mem_attach_dmabuf(adev, mem, bo); pr_debug("Employ DMABUF mechanim to enable peer GPU access\n"); From 41b43297e3d1a4940187d27502be4098e4535554 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 16 Aug 2021 17:04:36 +0800 Subject: [PATCH 0560/2653] drm/amdkcl: add DMA_FENCE_FLAG_USER_BITS macro This is caused by de7515d43659f852590645a688f8d493e4a18141 "drm/amd/amdgpu embed hw_fence into amdgpu_job" v5.13-2021-gde7515d43659 Signed-off-by: Asher Song Reviewed-by: Flora Cui --- include/kcl/kcl_fence.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index 947efbf7e38aa..88a2d1a425ec2 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -27,6 +27,7 @@ #define DMA_FENCE_TRACE FENCE_TRACE #define DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT FENCE_FLAG_ENABLE_SIGNAL_BIT #define DMA_FENCE_FLAG_SIGNALED_BIT FENCE_FLAG_SIGNALED_BIT +#define DMA_FENCE_FLAG_USER_BITS FENCE_FLAG_USER_BITS #define dma_fence_wait fence_wait #define dma_fence_get fence_get #define dma_fence_put fence_put From 1f6f4a48d45d317210bb050b9c40a0facbaa0f6f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 30 Aug 2021 14:29:55 +0800 Subject: [PATCH 0561/2653] drm/amdkcl: wrap code under the macro HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN It is caused by 00be4268d32c495798878c1b971a2e2fd18cf0d4 "drm/amd/display: Support for DMUB HPD interrupt handling" v5.13-2097-g00be4268d32c Signed-off-by: Asher Song Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 76441abb585b0..6bdc6a5e41041 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -789,7 +789,9 @@ static void dmub_hpd_callback(struct amdgpu_device *adev, struct amdgpu_dm_connector *aconnector; struct amdgpu_dm_connector *hpd_aconnector = NULL; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct dc_link *link; u8 link_index = 0; struct drm_device *dev; @@ -816,9 +818,12 @@ static void dmub_hpd_callback(struct amdgpu_device *adev, link_index = notify->link_index; link = adev->dm.dc->links[link_index]; dev = adev->dm.ddev; - +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { +#endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -837,7 +842,10 @@ static void dmub_hpd_callback(struct amdgpu_device *adev, break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif + drm_modeset_unlock(&dev->mode_config.connection_mutex); if (hpd_aconnector) { if (notify->type == DMUB_NOTIFICATION_HPD) { From dc51d6a1c52aa17ee0de26bb15686cf0187bb68d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 1 Sep 2021 18:52:10 +0800 Subject: [PATCH 0562/2653] drm/amdkcl: add macro INTEL_FAM6_ROCKETLAKE It's caused by 857d1b24aa8d97a7e1cb50ed3b02773a159a8c4d "drm/amdgpu: Disable PCIE_DPM on Intel RKL Platform" v5.13-2160-g857d1b24aa8d Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_intel_family.h | 12 ++++++++++++ 2 files changed, 13 insertions(+) create mode 100644 include/kcl/kcl_intel_family.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b9f8ad0f5d7f2..db2ccf68b324d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -77,5 +77,6 @@ #include "kcl/kcl_drm_gem_ttm_helper.h" #include "kcl/kcl_mce.h" #include "kcl/kcl_drm_aperture.h" +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_intel_family.h b/include/kcl/kcl_intel_family.h new file mode 100644 index 0000000000000..20781af676d6b --- /dev/null +++ b/include/kcl/kcl_intel_family.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_INTEL_FAMILY_H +#define AMDKCL_INTEL_FAMILY_H + +#include +/* Copied froma asm/intel-family.h*/ +#ifndef INTEL_FAM6_ROCKETLAKE +#define INTEL_FAM6_ROCKETLAKE 0xA7 +#endif + +#endif + From c5b918cc8ac27af01e5e1b8fc7ea7031985c7eb9 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 10 Sep 2021 10:50:25 +0800 Subject: [PATCH 0563/2653] drm/amdkcl: Avoid array out of bounds This is caused by bb892cd603b7 "drm/amdgpu: [hybrid] add direct gma(dgma) support" v5.13-2077-gbb892cd603b7 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index e23a69c64bb0c..ae9664066e75b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2137,6 +2137,7 @@ static int amdgpu_dgma_import_mgr_init(struct amdgpu_device *adev, uint64_t p_si spin_lock_init(&mgr->lock); atomic64_set(&mgr->available, p_size); + BUG_ON(AMDGPU_PL_DGMA_IMPORT >= TTM_NUM_MEM_TYPES); ttm_set_driver_manager(&adev->mman.bdev, AMDGPU_PL_DGMA_IMPORT, man); ttm_resource_manager_set_used(man, true); return 0; From 4ab82e100aa64593af5fcd5ffe241c647666b8e0 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 14 Sep 2021 10:20:43 +0800 Subject: [PATCH 0564/2653] drm/amdkcl: retain explicit creation and destruction of sysfs attributes for legacy os It's caused by 35bba8313b95a5cd074fc910a9c2670b4a1b105d "drm/amdgpu: Convert driver sysfs attributes to static attributes" v5.13-rc1-237-g35bba8313b95 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Change-Id: Id4d05534e1329859546cc642d0ee1536e47114b0 --- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 16 +++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 23 ++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 18 +++++++++++++++ .../drm/amd/dkms/m4/pci-driver-dev-groups.m4 | 8 +++---- 5 files changed, 62 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index e476e45b996a2..12f52c42da34c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -1819,6 +1819,7 @@ static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev, static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version, NULL); +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static struct attribute *amdgpu_vbios_version_attrs[] = { &dev_attr_vbios_version.attr, NULL @@ -1827,6 +1828,7 @@ static struct attribute *amdgpu_vbios_version_attrs[] = { const struct attribute_group amdgpu_vbios_version_attr_group = { .attrs = amdgpu_vbios_version_attrs }; +#endif int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev) { @@ -1856,6 +1858,9 @@ void amdgpu_atombios_fini(struct amdgpu_device *adev) adev->mode_info.atom_context = NULL; kfree(adev->mode_info.atom_card_info); adev->mode_info.atom_card_info = NULL; +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + device_remove_file(adev->dev, &dev_attr_vbios_version); +#endif } /** @@ -1872,6 +1877,9 @@ int amdgpu_atombios_init(struct amdgpu_device *adev) { struct card_info *atom_card_info = kzalloc(sizeof(struct card_info), GFP_KERNEL); +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + int ret; +#endif if (!atom_card_info) return -ENOMEM; @@ -1903,6 +1911,14 @@ int amdgpu_atombios_init(struct amdgpu_device *adev) amdgpu_atombios_allocate_fb_scratch(adev); } +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + ret = device_create_file(adev->dev, &dev_attr_vbios_version); + if (ret) { + DRM_ERROR("Failed to create device file for VBIOS version\n"); + return ret; + } +#endif + return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 62aded3e42513..632bb589c1d07 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3229,12 +3229,14 @@ static struct pci_error_handlers amdgpu_pci_err_handler = { .resume = amdgpu_pci_resume, }; +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static const struct attribute_group *amdgpu_sysfs_groups[] = { &amdgpu_vram_mgr_attr_group, &amdgpu_gtt_mgr_attr_group, &amdgpu_flash_attr_group, NULL, }; +#endif static struct pci_driver amdgpu_kms_pci_driver = { .name = DRIVER_NAME, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index 0760e70402ec1..071241ccfb646 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -76,6 +76,7 @@ static DEVICE_ATTR(mem_info_gtt_total, S_IRUGO, static DEVICE_ATTR(mem_info_gtt_used, S_IRUGO, amdgpu_mem_info_gtt_used_show, NULL); +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static struct attribute *amdgpu_gtt_mgr_attributes[] = { &dev_attr_mem_info_gtt_total.attr, &dev_attr_mem_info_gtt_used.attr, @@ -85,6 +86,7 @@ static struct attribute *amdgpu_gtt_mgr_attributes[] = { const struct attribute_group amdgpu_gtt_mgr_attr_group = { .attrs = amdgpu_gtt_mgr_attributes }; +#endif /** * amdgpu_gtt_mgr_has_gart_addr - Check if mem has address space @@ -277,6 +279,9 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size) struct amdgpu_gtt_mgr *mgr = &adev->mman.gtt_mgr; struct ttm_resource_manager *man = &mgr->manager; uint64_t start, size; +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + int ret; +#endif man->use_tt = true; man->func = &amdgpu_gtt_mgr_func; @@ -288,6 +293,19 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size) drm_mm_init(&mgr->mm, start, size); spin_lock_init(&mgr->lock); +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + ret = device_create_file(adev->dev, &dev_attr_mem_info_gtt_total); + if (ret) { + DRM_ERROR("Failed to create device file mem_info_gtt_total\n"); + return ret; + } + ret = device_create_file(adev->dev, &dev_attr_mem_info_gtt_used); + if (ret) { + DRM_ERROR("Failed to create device file mem_info_gtt_used\n"); + return ret; + } +#endif + ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, &mgr->manager); ttm_resource_manager_set_used(man, true); return 0; @@ -316,7 +334,10 @@ void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev) spin_lock(&mgr->lock); drm_mm_takedown(&mgr->mm); spin_unlock(&mgr->lock); - +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + device_remove_file(adev->dev, &dev_attr_mem_info_gtt_total); + device_remove_file(adev->dev, &dev_attr_mem_info_gtt_used); +#endif ttm_resource_manager_cleanup(man); ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, NULL); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 77ce9cf280518..95a63a7c18154 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -214,7 +214,11 @@ static DEVICE_ATTR(mem_info_vis_vram_used, S_IRUGO, static DEVICE_ATTR(mem_info_vram_vendor, S_IRUGO, amdgpu_mem_info_vram_vendor, NULL); +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static struct attribute *amdgpu_vram_mgr_attributes[] = { +#else +static const struct attribute *amdgpu_vram_mgr_attributes[] = { +#endif &dev_attr_mem_info_vram_total.attr, &dev_attr_mem_info_vis_vram_total.attr, &dev_attr_mem_info_vram_used.attr, @@ -223,6 +227,7 @@ static struct attribute *amdgpu_vram_mgr_attributes[] = { NULL }; +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static umode_t amdgpu_vram_attrs_is_visible(struct kobject *kobj, struct attribute *attr, int i) { @@ -241,6 +246,7 @@ const struct attribute_group amdgpu_vram_mgr_attr_group = { .attrs = amdgpu_vram_mgr_attributes, .is_visible = amdgpu_vram_attrs_is_visible }; +#endif /** * amdgpu_vram_mgr_vis_size - Calculate visible block size @@ -961,6 +967,9 @@ int amdgpu_vram_mgr_init(struct amdgpu_device *adev) struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; struct ttm_resource_manager *man = &mgr->manager; int err; +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + int ret; +#endif man->cg = drmm_cgroup_register_region(adev_to_drm(adev), "vram", adev->gmc.real_vram_size); if (IS_ERR(man->cg)) @@ -973,6 +982,12 @@ int amdgpu_vram_mgr_init(struct amdgpu_device *adev) INIT_LIST_HEAD(&mgr->reserved_pages); INIT_LIST_HEAD(&mgr->allocated_vres_list); mgr->default_page_size = PAGE_SIZE; +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + /* Add the two VRAM-related sysfs files */ + ret = sysfs_create_files(&adev->dev->kobj, amdgpu_vram_mgr_attributes); + if (ret) + DRM_ERROR("Failed to register sysfs\n"); +#endif if (!adev->gmc.is_app_apu) { man->func = &amdgpu_vram_mgr_func; @@ -1023,6 +1038,9 @@ void amdgpu_vram_mgr_fini(struct amdgpu_device *adev) drm_buddy_fini(&mgr->mm); mutex_unlock(&mgr->lock); +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + sysfs_remove_files(&adev->dev->kobj, amdgpu_vram_mgr_attributes); +#endif ttm_resource_manager_cleanup(man); ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_VRAM, NULL); } diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 index 7a673c73d6b1c..dfb7bd92cade1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 @@ -4,12 +4,12 @@ dnl # PCI: Add support for dev_groups to struct pci_driver dnl # AC_DEFUN([AC_AMDGPU_PCI_DRIVER_DEV_GROUPS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ + AC_KERNEL_TRY_COMPILE([ #include ], [ - struct pci_driver pd; - pd.dev_groups = NULL; - ], [], [], [ + struct pci_driver *pd = NULL; + pd->dev_groups = NULL; + ], [ AC_DEFINE(HAVE_PCI_DRIVER_DEV_GROUPS, 1, [struct pci_driver has field dev_groups]) ]) ]) From 6eb9ceea2b1a83f8e50300b2ebd57d0fd6cf7f08 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Sep 2021 10:22:22 +0800 Subject: [PATCH 0565/2653] drm/amdkcl: update config.h Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7594060ba31a2..0fa6ca4093282 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -11,7 +11,7 @@ #define HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS 1 /* acpi_put_table() is available */ -/* #undef HAVE_ACPI_PUT_TABLE */ +#define HAVE_ACPI_PUT_TABLE 1 /* struct acpi_srat_generic_affinity is available */ #define HAVE_ACPI_SRAT_GENERIC_AFFINITY 1 @@ -29,7 +29,7 @@ #define HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 1 /* amd_iommu_pc_supported() is available */ -/* #undef HAVE_AMD_IOMMU_PC_SUPPORTED */ +#define HAVE_AMD_IOMMU_PC_SUPPORTED 1 /* arch_io_{reserve/free}_memtype_wc() are available */ #define HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC 1 @@ -65,7 +65,7 @@ /* #undef HAVE_DEVM_MEMREMAP_PAGES_P_P_P_P */ /* dev_pagemap->owner is available */ -#define HAVE_DEV_PAGEMAP_OWNER 1 +/* #undef HAVE_DEV_PAGEMAP_OWNER */ /* there is 'range' field within dev_pagemap structure */ #define HAVE_DEV_PAGEMAP_RANGE 1 @@ -170,10 +170,10 @@ #define HAVE_DRM_COLOR_LUT_SIZE 1 /* drm_connector_atomic_hdr_metadata_equal() is available */ -/* #undef HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL */ +#define HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL 1 /* drm_connector_attach_hdr_output_metadata_property() is available */ -/* #undef HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY */ +#define HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY 1 /* drm_connector_for_each_possible_encoder() wants 2 arguments */ #define HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS 1 @@ -255,7 +255,7 @@ /* drm_dev_enter() is available */ #define HAVE_DRM_DEV_ENTER 1 -/* drm_dev_is_unplugged() is availablea */ +/* drm_dev_is_unplugged() is available */ #define HAVE_DRM_DEV_IS_UNPLUGGED 1 /* drm_dev_put() is available */ @@ -672,6 +672,9 @@ /* io_mapping_map_local_wc() is available */ #define HAVE_IO_MAPPING_MAP_LOCAL_WC 1 +/* io_mapping_map_wc() has size argument */ +#define HAVE_IO_MAPPING_MAP_WC_HAS_SIZE_ARG 1 + /* io_mapping_unmap_local() is available */ #define HAVE_IO_MAPPING_UNMAP_LOCAL 1 @@ -802,7 +805,7 @@ #define HAVE_MEM_ENCRYPT_ACTIVE 1 /* migrate_vma->pgmap_owner is available */ -#define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 +/* #undef HAVE_MIGRATE_VMA_PGMAP_OWNER */ /* mmgrab() is available */ #define HAVE_MMGRAB 1 @@ -984,7 +987,7 @@ /* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg */ -#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 +/* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS */ /* drm_plane_helper_funcs->prepare_fb() wants const p arg */ /* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_CONST */ @@ -1052,6 +1055,9 @@ /* wait_queue_entry_t exists */ #define HAVE_WAIT_QUEUE_ENTRY 1 +/* is_device_page is available */ +/* #undef HAVE_ZONE_DEVICE_PUBLIC */ + /* zone_managed_pages() is available */ #define HAVE_ZONE_MANAGED_PAGES 1 From 523110197535d8c3282d3a4b21a8c96865db8c36 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Sep 2021 10:20:41 +0800 Subject: [PATCH 0566/2653] drm/amdkcl: fix test for is_cow_mapping Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 b/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 index c0bf84f081f2a..116779b2674f0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 @@ -1,10 +1,10 @@ dnl # -dnl # commit 97a7e4733b9b221d012ae68fcd3b3251febf6341 +dnl # commit v5.12-rc2-346-g97a7e4733b9b dnl # mm: introduce page_needs_cow_for_dma() for deciding whether cow dnl # AC_DEFUN([AC_AMDGPU_IS_COW_MAPPING], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ + AC_KERNEL_TRY_COMPILE([ #include ], [ is_cow_mapping(VM_SHARED); From 584e3ef52bb54fbd00fd2e2824aecd4e06d79a75 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Sep 2021 15:59:24 +0800 Subject: [PATCH 0567/2653] drm/amdkcl: fix test for drm_plane_helper_funcs->atomic_check() Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0fa6ca4093282..52bb9db3ef526 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -987,7 +987,7 @@ /* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg */ -/* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 /* drm_plane_helper_funcs->prepare_fb() wants const p arg */ /* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_CONST */ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 index 68b8e02668cae..59fe64ed86c35 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 @@ -25,7 +25,7 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_ #include ], [ struct drm_plane_helper_funcs *funcs = NULL; - funcs->atomic_check((struct drm_crtc *)NULL, (struct drm_atomic_state *)NULL); + funcs->atomic_check(NULL, (struct drm_atomic_state *)NULL); ], [ AC_DEFINE(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS, 1, [drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg]) From 26263a8e4ef267d210da03c7a30eb64e606b4bd9 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Sep 2021 15:38:20 +0800 Subject: [PATCH 0568/2653] drm/amdkcl: fix test for amd_iommu_pc_xxx Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 6 ----- drivers/gpu/drm/amd/dkms/config/config.h | 6 +++++ .../drm/amd/dkms/m4/amd-iommu-pc-supported.m4 | 27 +++++++++++++++++-- 3 files changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index b53fdf1f30f19..e4f9d839be01e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -208,10 +208,4 @@ struct kfd_topology_device *kfd_create_topology_device( struct list_head *device_list); void kfd_release_topology_device_list(struct list_head *device_list); -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED -extern bool amd_iommu_pc_supported(void); -extern u8 amd_iommu_pc_get_max_banks(u16 devid); -extern u8 amd_iommu_pc_get_max_counters(u16 devid); -#endif - #endif /* __KFD_TOPOLOGY_H__ */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 52bb9db3ef526..b7b1007ab10e5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -28,6 +28,12 @@ /* amd_iommu_invalidate_ctx take arg type of pasid as u32 */ #define HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 1 +/* amd_iommu_pc_get_max_banks() declared */ +#define HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED 1 + +/* amd_iommu_pc_get_max_banks() arg is unsigned int */ +/* #undef HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_UINT */ + /* amd_iommu_pc_supported() is available */ #define HAVE_AMD_IOMMU_PC_SUPPORTED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 b/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 index 27bed9e6beb3b..67cbbec8cac3e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 @@ -1,5 +1,27 @@ dnl # -dnl # commit 30861ddc9cca479a7fc6a5efef4e5c69d6b274f4 +dnl # v5.12-rc3-5-gfc1b6620501f iommu/amd: Move a few prototypes to include/linux/amd-iommu.h +dnl # v5.12-rc3-4-gb29a1fc7595a iommu/amd: Remove a few unused exports +dnl # v4.11-rc4-171-gf5863a00e73c x86/events/amd/iommu.c: Modify functions to query max banks and counters +dnl # +AC_DEFUN([AC_AMDGPU_AMD_IOMMU_PC_GET_MAX_BANKS], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + amd_iommu_pc_get_max_banks(0); + ], [ + AC_DEFINE(HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED, 1, + [amd_iommu_pc_get_max_banks() declared]) + ], [ + AC_KERNEL_CHECK_SYMBOL_EXPORT([get_amd_iommu], + [drivers/iommu/amd/init.c], [ + AC_DEFINE(HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_UINT, 1, + [amd_iommu_pc_get_max_banks() arg is unsigned int]) + ]) + ]) +]) + +dnl # +dnl # commit v3.10-rc3-89-g30861ddc9cca dnl # perf/x86/amd: Add IOMMU Performance Counter resource management dnl # AC_DEFUN([AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED], [ @@ -10,9 +32,10 @@ AC_DEFUN([AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED], [ #ifndef CONFIG_AMD_IOMMU #error CONFIG_AMD_IOMMU not enabled #endif - ], [amd_iommu_pc_supported], [drivers/iommu/amd_iommu_init.c], [ + ], [amd_iommu_pc_supported], [drivers/iommu/amd/init.c], [ AC_DEFINE(HAVE_AMD_IOMMU_PC_SUPPORTED, 1, [amd_iommu_pc_supported() is available]) + AC_AMDGPU_AMD_IOMMU_PC_GET_MAX_BANKS ]) ]) ]) From b78afa6b91a2e6ca2aac584cca18c4061d3c515b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 10 Sep 2021 11:44:49 +0800 Subject: [PATCH 0569/2653] drm/amdkcl: fake a dummy mmput_async v2: fix the missing ; HAVE_MMPUT_ASYNC must be defined for monolithic build Signed-off-by: Flora Cui Reviewed-and-tested-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 | 12 ++++++++++++ include/kcl/backport/kcl_mm_backport.h | 4 ++++ include/kcl/kcl_mm.h | 4 ++++ 6 files changed, 37 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index e60ac00cba573..9d7534002b7e1 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -6,6 +6,19 @@ */ #include +#ifndef HAVE_MMPUT_ASYNC +void (*_kcl_mmput_async)(struct mm_struct *mm); +EXPORT_SYMBOL(_kcl_mmput_async); + +void __kcl_mmput_async(struct mm_struct *mm) +{ + pr_warn_once("This kernel version not support API: mmput_async !\n"); +} +#endif + void amdkcl_mm_init(void) { +#ifndef HAVE_MMPUT_ASYNC + _kcl_mmput_async = amdkcl_fp_setup("mmput_async", __kcl_mmput_async); +#endif } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b7b1007ab10e5..3bf2610fde6a4 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -816,6 +816,9 @@ /* mmgrab() is available */ #define HAVE_MMGRAB 1 +/* mmput_async() is available */ +#define HAVE_MMPUT_ASYNC 1 + /* mmu_notifier_call_srcu() is available */ /* #undef HAVE_MMU_NOTIFIER_CALL_SRCU */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f3750fc17ae1a..04908532f1dc6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -147,6 +147,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY AC_AMDGPU_KERNEL_WRITE AC_AMDGPU_STRUCT_XARRAY + AC_AMDGPU_MMPUT_ASYNC AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 b/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 new file mode 100644 index 0000000000000..2c8863597781f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 @@ -0,0 +1,12 @@ +dnl # +dnl # v4.14-rc3-117-ga1b2289cef92 android: binder: drop lru lock in isolate callback +dnl # v4.13-4372-g212925802454 mm: oom: let oom_reap_task and exit_mmap run concurrently +dnl # v4.6-6601-gec8d7c14ea14 mm, oom_reaper: do not mmput synchronously from the oom reaper context +dnl # +AC_DEFUN([AC_AMDGPU_MMPUT_ASYNC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([mmput_async], [kernel/fork.c], [ + AC_DEFINE(HAVE_MMPUT_ASYNC, 1, [mmput_async() is available]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_mm_backport.h b/include/kcl/backport/kcl_mm_backport.h index 3fc317a922a8d..48312d64e5869 100644 --- a/include/kcl/backport/kcl_mm_backport.h +++ b/include/kcl/backport/kcl_mm_backport.h @@ -5,6 +5,10 @@ #include #include +#ifndef HAVE_MMPUT_ASYNC +#define mmput_async _kcl_mmput_async +#endif + #ifdef get_user_pages_remote #undef get_user_pages_remote #endif diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index be023c0b95edd..57b2ee1fcb846 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -22,6 +22,10 @@ #define untagged_addr(addr) (addr) #endif +#ifndef HAVE_MMPUT_ASYNC +extern void (*_kcl_mmput_async)(struct mm_struct *mm); +#endif + #ifndef HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST static inline bool fault_flag_allow_retry_first(unsigned int flags) { From ad9fecb3dab09dc16dfb4cc25469aa3f07c0c60f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 22 Sep 2021 15:54:28 +0800 Subject: [PATCH 0570/2653] drm/amdkcl: wrap code under macro HAVE_DOWN_WRITE_KILLABLE It's caused by 3e563486be3ca0c716f6ac1b888eef59626d72fe "drm/amdgpu: Fix a race of IB test" v5.13-2444-g3e563486be3c Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index a67bd513cb17d..e919ab95ace30 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -1689,9 +1689,13 @@ static int amdgpu_debugfs_test_ib_show(struct seq_file *m, void *unused) } /* Avoid accidently unparking the sched thread during GPU reset */ +#ifndef HAVE_DOWN_WRITE_KILLABLE + down_write(&adev->reset_domain->sem); +#else r = down_write_killable(&adev->reset_domain->sem); if (r) return r; +#endif /* hold on the scheduler */ for (i = 0; i < AMDGPU_MAX_RINGS; i++) { From 0bc88baa7ee68b51bdcb8933801a43ad4783a763 Mon Sep 17 00:00:00 2001 From: Jingwen Chen Date: Tue, 7 Sep 2021 11:12:06 +0800 Subject: [PATCH 0571/2653] drm/amd/amdgpu: use ordered workqueue for tdr in SRIOV [Why] When two job timedout happens during a very close time, the job bailing will happen. As drm scheduler will delete the bad job from pending list when entering the tdr and add it back when calling drm_sched_stop during tdr handling, the bailing job will be deleted from pending list but it will directly return before calling drm_sched_stop as the first job has already sets the in_gpu_reset. So this bailing job will not be added back ever. And this can lead to this job never be finished. [How] 1. Use an ordered_workqueue as the timeout_wq for all tdr. As there will only be one tdr work at the same time, the bailing will never happen. 2. Use mdelay in sriov flr work to make sure the polling flr won't exceeds the default ring timeout. v2: Add detailed description. Use gpu_recovery=2 for SRIOV v3: split recovery mode and mdelay into seperate patch Based on: https://patchwork.freedesktop.org/patch/msgid/20210630062751.2832545-3-boris.brezillon@collabora.com Signed-off-by: Jingwen Chen Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 1e24e4bc1d889..e8cf2951708f1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1104,6 +1104,7 @@ struct amdgpu_device { bool ib_pool_ready; struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; + struct workqueue_struct *timeout_wq; /* interrupts */ struct amdgpu_irq irq; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index ee4a434a339fa..5f07e4db9081e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4704,6 +4704,12 @@ int amdgpu_device_init(struct amdgpu_device *adev, /* init the mode config */ drm_mode_config_init(adev_to_drm(adev)); + if (amdgpu_sriov_vf(adev)) { + adev->timeout_wq = alloc_ordered_workqueue("amdgpu_ring_timeout_wq", 0); + if (!adev->timeout_wq) + dev_warn(adev->dev, "alloc_ordered_workqueue failed\n"); + } + r = amdgpu_device_ip_init(adev); if (r) { dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); From 0a6016dd7edc3f961ed5c54ad410a7206e9ca0f1 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 16:48:10 +0800 Subject: [PATCH 0572/2653] drm/amdkcl: Resolve target kernel 4.14 amdgpu_dm build issue invalid operands to binary - (have 'struct timeval' and 'ktime_t' {aka long long int}') frame_duration = vblank->time - previous_timestamp; incompatible type for argument 2 of 'atomic64_set' atomic64_set(irq_params->previous_timestamp, vblank->time) v2: create separated KCL macro for vblank field time of type ktime_t or timeval v3: fix typo in new m4 configuration v4: use initialized variable in m4 configuration file Signed-off-by: Nikola Prica Reviewed-by: Flora Cui Signed-off-by: Ma Jun Change-Id: I539392044b24600278315f09323974dc0ef36ba7 Signed-off-by: Asher Song --- .../gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h | 11 +++++++++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ++++++++++-- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../dkms/m4/drm_vblank_use_ktime_t_time_field.m4 | 15 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 40 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h index 383d7ec209af1..825228898e963 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -89,4 +89,15 @@ static inline int kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, un #endif /* HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG */ #endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP */ +#if defined(HAVE_DRM_VBLANK_USE_KTIME_T) +static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) { + return vblank->time; +} +#else +static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) { + return timeval_to_ns(&vblank->time); +} +#endif /* HAVE_DRM_VBLANK_USE_KTIME_T */ + + #endif /* AMDGPU_BACKPORT_KCL_AMDGPU_H */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6bdc6a5e41041..480fb03a00a7c 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -535,6 +535,13 @@ static void dm_pflip_high_irq(void *interrupt_params) amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e); } +#ifndef HAVE_KTIME_IS_UNION +static inline ktime_t get_drm_vblank_crtc_time(struct drm_vblank_crtc *vblank) +{ + return kcl_amdgpu_get_vblank_time_ns(vblank); +} +#endif + static void dm_vupdate_high_irq(void *interrupt_params) { struct common_irq_params *irq_params = interrupt_params; @@ -556,13 +563,14 @@ static void dm_vupdate_high_irq(void *interrupt_params) drm_dev = acrtc->base.dev; vblank = drm_crtc_vblank_crtc(&acrtc->base); previous_timestamp = atomic64_read(&irq_params->previous_timestamp); - frame_duration_ns = vblank->time - previous_timestamp; + frame_duration_ns = get_drm_vblank_crtc_time(vblank) - previous_timestamp; if (frame_duration_ns > 0) { trace_amdgpu_refresh_rate_track(acrtc->base.index, frame_duration_ns, ktime_divns(NSEC_PER_SEC, frame_duration_ns)); - atomic64_set(&irq_params->previous_timestamp, vblank->time); + atomic64_set(&irq_params->previous_timestamp, + get_drm_vblank_crtc_time(vblank)); } #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3bf2610fde6a4..5dffaca76c2a7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -357,6 +357,9 @@ /* drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg */ /* #undef HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG */ +/* drm_vblank struct use ktime_t for time field */ +#define HAVE_DRM_VBLANK_USE_KTIME_T 1 + /* drm_driver->release() is available */ #define HAVE_DRM_DRIVER_RELEASE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 new file mode 100644 index 0000000000000..1107aa2219eca --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit v4.14-rc3-721-g67680d3c0464 dnl # drm: vblank: use ktime_t instead of timeval +AC_DEFUN([AC_AMDGPU_DRM_VBLANK_USE_KTIME_T], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_vblank_crtc *vblank = NULL; + vblank->time = 0; + ], [ + AC_DEFINE(HAVE_DRM_VBLANK_USE_KTIME_T, 1, + [drm_vblank->time uses ktime_t type]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 04908532f1dc6..083ae751b5c8c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -169,6 +169,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEV_ENTER AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_AMDGPU_DRM_DEVICE_PDEV + AC_AMDGPU_DRM_VBLANK_USE_KTIME_T AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 8a79bcb47121bc4ab51b60e4a42495c128312fbc Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Sat, 9 Oct 2021 15:21:18 +0800 Subject: [PATCH 0573/2653] drm/amdkcl: adapt code of ktime_t api for legacy os Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h | 4 +++- .../drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 | 9 +++++++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h index 825228898e963..fc2eecd49d62b 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -95,7 +95,9 @@ static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vbla } #else static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) { - return timeval_to_ns(&vblank->time); + struct timeval tv; + drm_crtc_vblank_count_and_time(vblank, &tv); + return timeval_to_ktime(tv); } #endif /* HAVE_DRM_VBLANK_USE_KTIME_T */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 index 1107aa2219eca..b846cb2f57a41 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 @@ -1,12 +1,17 @@ dnl # -dnl # commit v4.14-rc3-721-g67680d3c0464 dnl # drm: vblank: use ktime_t instead of timeval +dnl # commit v4.14-rc3-721-g67680d3c0464 dnl # drm: vblank: use ktime_t instead of timeval AC_DEFUN([AC_AMDGPU_DRM_VBLANK_USE_KTIME_T], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + #include + #else #include + #endif + #include ], [ struct drm_vblank_crtc *vblank = NULL; - vblank->time = 0; + vblank->time = ns_to_ktime(0); ], [ AC_DEFINE(HAVE_DRM_VBLANK_USE_KTIME_T, 1, [drm_vblank->time uses ktime_t type]) From 3fce561575984d0ec99da2a512683c8b5412546f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 11 Oct 2021 14:50:16 +0800 Subject: [PATCH 0574/2653] drm/amdkcl: fix dependency for HSA_AMD_SVM Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index b1eecc92ebfb3..ef8bfe38400f5 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -159,9 +159,11 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) +ifdef CONFIG_DEVICE_PRIVATE export CONFIG_HSA_AMD_SVM=y subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM endif +endif export CONFIG_DRM_AMD_DC_HDCP=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP From 49703d2ed96382ddd0ba48bd44881f5a1dfb0e34 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 11 Oct 2021 14:49:42 +0800 Subject: [PATCH 0575/2653] drm/amdkcl: fix mmu_notifier_range_blockable on rhel8.5 Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- include/kcl/kcl_mmu_notifier.h | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/include/kcl/kcl_mmu_notifier.h b/include/kcl/kcl_mmu_notifier.h index 1af9433bdbfe5..eb18197778b02 100644 --- a/include/kcl/kcl_mmu_notifier.h +++ b/include/kcl/kcl_mmu_notifier.h @@ -4,16 +4,25 @@ #include -#if !defined(HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE) && \ - defined(HAVE_2ARGS_INVALIDATE_RANGE_START) +#if !defined(HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE) /* Copied from v5.1-10225-g4a83bfe916f3 include/linux/mmu_notifier.h */ -#ifdef CONFIG_MMU_NOTIFIER +#if defined(CONFIG_MMU_NOTIFIER) && \ + defined(HAVE_2ARGS_INVALIDATE_RANGE_START) static inline bool mmu_notifier_range_blockable(const struct mmu_notifier_range *range) { +/* + * It's for rhel8.5 which has the latest struct mmu_notifier_range + * and no mmu_notifier_range_blockable + */ +#ifdef MMU_NOTIFIER_RANGE_BLOCKABLE + return (range->flags & MMU_NOTIFIER_RANGE_BLOCKABLE); +#else return range->blockable; +#endif } #else +struct mmu_notifier_range; static inline bool mmu_notifier_range_blockable(const struct mmu_notifier_range *range) { From 9bd40261a612b0ba8bcd1e6840f59c5c526ce27f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 11 Oct 2021 19:12:08 +0800 Subject: [PATCH 0576/2653] drm/amdkcl: fake drm_connector_set_panel_orientation_with_quirk() It's caused by 01265b703af5e7cd99545319bc88aba22ab7b95f "amd/display: enable panel orientation quirks" v5.13-2450-g01265b703af5 Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c | 11 +++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ ...connector-set-panel-orientation-with-quirk.m4 | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 16 ++++++++++++++++ 5 files changed, 44 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index 79c907264d709..a4a4e8d2e9acf 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -78,3 +78,14 @@ int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *conn } EXPORT_SYMBOL(drm_connector_attach_hdr_output_metadata_property); #endif + +#if !defined(HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK) +int _kcl_drm_connector_set_panel_orientation_with_quirk( + struct drm_connector *connector, + enum drm_panel_orientation panel_orientation, + int width, int height) +{ + return drm_connector_init_panel_orientation_property(connector, width, height); +} +EXPORT_SYMBOL(_kcl_drm_connector_set_panel_orientation_with_quirk); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5dffaca76c2a7..3beb7d29369a3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -210,6 +210,9 @@ /* connector reference counting is available */ #define HAVE_DRM_CONNECTOR_REFERENCE_COUNTING_SUPPORTED 1 +/* drm_connector_set_panel_orientation_with_quirk() is available */ +#define HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK 1 + /* struct drm_connector_state has hdcp_content_type member */ #define HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 new file mode 100644 index 0000000000000..463767cb7e3a6 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit v5.5-rc2-1360-g69654c632d80 +dnl # drm/connector: Split out orientation quirk detection (v2) +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_connector_set_panel_orientation_with_quirk], + [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK, 1, + [drm_connector_set_panel_orientation_with_quirk() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 083ae751b5c8c..2b2bf36f9a7a7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -170,6 +170,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_VBLANK_USE_KTIME_T + AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index f50f00e2f17fb..d77022ef022ac 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -105,4 +105,20 @@ bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_sta int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *connector); #endif +#ifndef HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK +int _kcl_drm_connector_set_panel_orientation_with_quirk( + struct drm_connector *connector, + enum drm_panel_orientation panel_orientation, + int width, int height); + +static inline +int drm_connector_set_panel_orientation_with_quirk( + struct drm_connector *connector, + enum drm_panel_orientation panel_orientation, + int width, int height) +{ + return _kcl_drm_connector_set_panel_orientation_with_quirk(connector, panel_orientation, width, height); +} +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From cbe3b82c5c192927f3f5ead7774d173e41695123 Mon Sep 17 00:00:00 2001 From: Marko Zekovic Date: Mon, 11 Oct 2021 15:03:35 +0200 Subject: [PATCH 0577/2653] drm/amdkcl: fix issue with dirver unloading Fix issue with driver unloading on kernel 5.4. Backported from 5.11 version of driver. Signed-off-by: Marko Zekovic Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 632bb589c1d07..1d139b093daa8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2582,6 +2582,9 @@ amdgpu_pci_remove(struct pci_dev *pdev) kcl_pci_remove_measure_file(pdev); pci_disable_device(pdev); pci_wait_for_pending_transaction(pdev); +#ifdef AMDKCL_DEVM_DRM_DEV_ALLOC + amdkcl_drm_dev_release(dev); +#endif } #ifdef HAVE_DRM_DRIVER_RELEASE From ce876d3101124b631c737ee362bff2dfa318c094 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 15 Oct 2021 16:13:34 +0800 Subject: [PATCH 0578/2653] drm/amdkcl: add arguments of function amdgpu_ttm_tt_affect_userptr() It's caused by 2d3ad5529663465fd1443f9cf8230ec2bba2cd77 "drm/amdkfd: unregistered svm range not overlap with TTM range" v5.13-2731-g2d3ad5529663 Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 9 ++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 5 ++++- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 128f079102013..43bb1ec468fe8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -270,10 +270,11 @@ static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node, { struct amdgpu_bo *bo; long r; + unsigned long userptr; list_for_each_entry(bo, &node->bos, mn_list) { - if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end)) + if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end, &userptr)) continue; r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&bo->tbo), @@ -342,6 +343,7 @@ static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); struct interval_tree_node *it; unsigned long end; + unsigned long userptr; /* notification is exclusive, but interval is inclusive */ end = range->end - 1; @@ -362,7 +364,7 @@ static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, range->start, - end)) + end, &userptr)) amdgpu_amdkfd_evict_userptr(mem, range->mm); } } @@ -452,6 +454,7 @@ static void amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, { struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); struct interval_tree_node *it; + unsigned long userptr; /* notification is exclusive, but interval is inclusive */ end -= 1; @@ -475,7 +478,7 @@ static void amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, struct kgd_mem *mem = bo->kfd_bo; if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, - start, end)) + start, end, &userptr)) amdgpu_amdkfd_evict_userptr(mem, mm); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index ae9664066e75b..dc3a4a4451e90 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1563,7 +1563,7 @@ bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) * */ bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, - unsigned long end) + unsigned long end, unsigned long *userptr) { struct amdgpu_ttm_tt *gtt = (void *)ttm; struct amdgpu_ttm_gup_task_list *entry; @@ -1593,6 +1593,9 @@ bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, atomic_inc(>t->mmu_invalidations); + if (userptr) + *userptr = gtt->userptr; + return true; } From 9cac59c978f020f21aab05f7603486c256620350 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Oct 2021 16:11:29 +0800 Subject: [PATCH 0579/2653] drm/amdkcl: fake a get_mm_exe_file get_mm_exe_file is not export in legacy kernel. It's caused by 0d4da915c7098eca2aa6f559f42e33b5e9c7c5e8 "amd/display: only require overlay plane to cover whole CRTC on ChromeOS" v5.13-2703-g0d4da915c709 Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 10 ++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 | 10 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_mm_backport.h | 4 ++++ include/kcl/kcl_mm.h | 4 ++++ 6 files changed, 32 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index 9d7534002b7e1..65ae09624622f 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -16,9 +16,19 @@ void __kcl_mmput_async(struct mm_struct *mm) } #endif + +#ifndef HAVE_GET_MM_EXE_FILE +struct file *(*_kcl_get_mm_exe_file)(struct mm_struct *mm); +EXPORT_SYMBOL(_kcl_get_mm_exe_file); +#endif + void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC _kcl_mmput_async = amdkcl_fp_setup("mmput_async", __kcl_mmput_async); #endif + +#ifndef HAVE_GET_MM_EXE_FILE + _kcl_get_mm_exe_file = amdkcl_fp_setup("get_mm_exe_file", NULL); +#endif } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3beb7d29369a3..4a844b33546e1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -642,6 +642,9 @@ /* drm_driver->gem_free_object_unlocked() is available */ /* #undef HAVE_GEM_FREE_OBJECT_UNLOCKED_IN_DRM_DRIVER */ +/* get_mm_exe_file() is available */ +#define HAVE_GET_MM_EXE_FILE 1 + /* get_user_pages() wants 6 args */ /* #undef HAVE_GET_USER_PAGES_6ARGS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 b/drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 new file mode 100644 index 0000000000000..9c024190e405d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 @@ -0,0 +1,10 @@ +dnl # +dnl # v2.6.39-6856-g3864601387cf mm: extract exe_file handling from procfs +dnl # +AC_DEFUN([AC_AMDGPU_GET_MM_EXE_FILE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([get_mm_exe_file], [kernel/fork.c], [ + AC_DEFINE(HAVE_GET_MM_EXE_FILE, 1, [get_mm_exe_file() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2b2bf36f9a7a7..027b7fa52e23a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -171,6 +171,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_VBLANK_USE_KTIME_T AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK + AC_AMDGPU_GET_MM_EXE_FILE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_mm_backport.h b/include/kcl/backport/kcl_mm_backport.h index 48312d64e5869..131403b50a6b4 100644 --- a/include/kcl/backport/kcl_mm_backport.h +++ b/include/kcl/backport/kcl_mm_backport.h @@ -9,6 +9,10 @@ #define mmput_async _kcl_mmput_async #endif +#ifndef HAVE_GET_MM_EXE_FILE +#define get_mm_exe_file _kcl_get_mm_exe_file +#endif + #ifdef get_user_pages_remote #undef get_user_pages_remote #endif diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 57b2ee1fcb846..4f33936bf7dd9 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -26,6 +26,10 @@ extern void (*_kcl_mmput_async)(struct mm_struct *mm); #endif +#ifndef HAVE_GET_MM_EXE_FILE +extern struct file *(*_kcl_get_mm_exe_file)(struct mm_struct *mm); +#endif + #ifndef HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST static inline bool fault_flag_allow_retry_first(unsigned int flags) { From a706842d6b6b94fd18d2535207de98f0e9db1736 Mon Sep 17 00:00:00 2001 From: Amber Lin Date: Fri, 22 Oct 2021 12:08:37 -0400 Subject: [PATCH 0580/2653] drm/amdkcl: Set PAGEMAP_OWNER for in-tree build PAGEMAP_OWNER should be defined in config.h for in-tree build on 5.13 kernel. This fixes "failed to register HMM device memory" error when loading amdgpu driver where a 5.13 monolithic kernel is used. Signed-off-by: Amber Lin Reviewed-by: Philip Yang Change-Id: I5a09a4ec30649c202096fa1f95248ad802e9fdd7 --- drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4a844b33546e1..36f268b2239c8 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -71,7 +71,7 @@ /* #undef HAVE_DEVM_MEMREMAP_PAGES_P_P_P_P */ /* dev_pagemap->owner is available */ -/* #undef HAVE_DEV_PAGEMAP_OWNER */ +#define HAVE_DEV_PAGEMAP_OWNER 1 /* there is 'range' field within dev_pagemap structure */ #define HAVE_DEV_PAGEMAP_RANGE 1 @@ -820,7 +820,7 @@ #define HAVE_MEM_ENCRYPT_ACTIVE 1 /* migrate_vma->pgmap_owner is available */ -/* #undef HAVE_MIGRATE_VMA_PGMAP_OWNER */ +#define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 /* mmgrab() is available */ #define HAVE_MMGRAB 1 From 3450556817bb2e5a9839c1f124f0675917a8ef59 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 28 Oct 2021 17:00:24 +0800 Subject: [PATCH 0581/2653] drm/amdkcl: add forward declaration of task_struct v5.12-rc3-304-gf7b21a0e4117 fixes a build error when linux/fb.h is used outside of the kernel tree. This patch adds forward declaration of task_struct to adapt legacy os. Reviewed-by: Flora Cui --- .../m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 | 1 + .../gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 index ec30c7ffa874c..ee6e915098f5c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 @@ -43,6 +43,7 @@ AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ dnl # video/fb: Propagate error code from failing to unregister conflicting fb dnl # AC_KERNEL_TRY_COMPILE_SYMBOL([ + struct task_struct; #include ], [ int ret = remove_conflicting_framebuffers(NULL, NULL, false); diff --git a/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 index 06241044fe4d4..bde011042303f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 @@ -5,6 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + struct task_struct; #include ],[ remove_conflicting_pci_framebuffers(NULL, NULL); @@ -13,6 +14,7 @@ AC_DEFUN([AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ [remove_conflicting_pci_framebuffers() is available and doesn't have res_id arg]) ],[ AC_KERNEL_TRY_COMPILE([ + struct task_struct; #include ], [ remove_conflicting_pci_framebuffers(NULL, 0, NULL); From 6903e91bd2ebda8a67a6489bdd0991478c839cdc Mon Sep 17 00:00:00 2001 From: Jingwen Chen Date: Fri, 29 Oct 2021 18:04:05 +0800 Subject: [PATCH 0582/2653] drm/amdkcl: fix minor index not removed after unload driver [Why] In kernel 5.4, current driver will not remove minor->index from drm_minors_idr during unload driver. Which will lead to minor index increase after reload amdgpu. [How] As there's no drm_managed.h to call drm_minor_alloc_release when release dev, add drm_dev_fini to amdgpu_driver_release_kms Signed-off-by: Jingwen Chen Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 3289dc90c54e0..5d36cfff399dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1585,6 +1585,10 @@ void amdgpu_driver_release_kms(struct drm_device *dev) amdgpu_device_fini_sw(adev); pci_set_drvdata(adev->pdev, NULL); +#ifndef HAVE_DRM_DRM_MANAGED_H + drm_dev_fini(dev); + kfree(adev); +#endif } /* From f36344a1d70cb5e25a8c8fb29115c48be2e7f724 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 2 Nov 2021 10:07:22 +0800 Subject: [PATCH 0583/2653] drm/amdkcl: Fix DKMS makefile include path filter As of Ubuntu 20.04.4, the given paths from LINUXINCLUDE variable would be filtered incorrectly as each token is considered a word and done independently. This would lead to the case where two '-include' switches would appear in sequence causing later switches to be parsed incorrectly. When the kconfig file is filtered out, it should be filtered out together with the preceding '-include', so adding quotes fixes this. v1: add quotes to filter out the specific string v2: handle the extra space with "-I " Signed-off-by: George Cave Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index ef8bfe38400f5..b9f423b84ddaf 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -124,9 +124,10 @@ endif export OS_NAME OS_VERSION +_KCL_LINUXINCLUDE=$(subst -I ,-I,$(strip $(LINUXINCLUDE))) LINUX_SRCTREE_INCLUDE := \ - $(filter-out -I%/uapi -include %/kconfig.h,$(LINUXINCLUDE)) -USER_INCLUDE := $(filter-out $(LINUX_SRCTREE_INCLUDE), $(LINUXINCLUDE)) + $(filter-out -I%/uapi "-include %/kconfig.h",$(_KCL_LINUXINCLUDE)) +USER_INCLUDE := $(filter-out $(LINUX_SRCTREE_INCLUDE), $(_KCL_LINUXINCLUDE)) LINUXINCLUDE := \ -I$(src)/include \ From da6625697ceb10e14d6f3cb8a35ec5a094ce7abd Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 3 Nov 2021 11:54:40 +0800 Subject: [PATCH 0584/2653] drm/amdkcl: fake drm_simple_encoder_init It's caused by ba5317109d0ce7809831abfcea9b8157464b263f "drm/amdgpu: create amdgpu_vkms (v4)" v5.13-1946-gba5317109d0c Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../amd/amdkcl/kcl_drm_simple_kms_helper.c | 24 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm_simple_kms_helper.m4 | 12 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_simple_kms_helper.h | 22 +++++++++++++++++ 7 files changed, 64 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_simple_kms_helper.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 create mode 100644 include/kcl/kcl_drm_simple_kms_helper.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index a26c5110afa79..ef7887752b276 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,7 +12,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ - kcl_drm_drv.o + kcl_drm_drv.o kcl_drm_simple_kms_helper.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_simple_kms_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_simple_kms_helper.c new file mode 100644 index 0000000000000..7a44428ce88e2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_simple_kms_helper.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 Noralf Trønnes + */ + +#include + +/* Copied from drivers/gpu/drm/drm_simple_kms_helper.c and modified for KCL */ +#ifndef HAVE_DRM_SIMPLE_ENCODER_INIT +static const struct drm_encoder_funcs drm_simple_encoder_funcs_cleanup = { + .destroy = drm_encoder_cleanup, +}; + +int _kcl_drm_simple_encoder_init(struct drm_device *dev, + struct drm_encoder *encoder, + int encoder_type) +{ + return drm_encoder_init(dev, encoder, + &drm_simple_encoder_funcs_cleanup, + encoder_type, NULL); +} +EXPORT_SYMBOL(_kcl_drm_simple_encoder_init); + +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index db2ccf68b324d..e2a1e3e409bde 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -78,5 +78,6 @@ #include "kcl/kcl_mce.h" #include "kcl/kcl_drm_aperture.h" #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 36f268b2239c8..47a227eaee844 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -597,6 +597,9 @@ /* drm_printer->prefix is available */ #define HAVE_DRM_PRINTER_PREFIX 1 +/* drm_simple_encoder is available */ +#define HAVE_DRM_SIMPLE_ENCODER_INIT 1 + /* drm_syncobj_fence_get() is available */ /* #undef HAVE_DRM_SYNCOBJ_FENCE_GET */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 new file mode 100644 index 0000000000000..0ffcd218e5a99 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 @@ -0,0 +1,12 @@ +dnl # +dnl # v5.6-rc2-359-g63170ac6f2e8 +dnl # drm/simple-kms: Add drm_simple_encoder_{init,create}() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT], [ + AC_KERNEL_CHECK_SYMBOL_EXPORT( + [drm_simple_encoder_init], + [drivers/gpu/drm/drm_simple_kms_helper.c],[ + AC_DEFINE(HAVE_DRM_SIMPLE_ENCODER_INIT, 1, + [drm_simple_encoder is available]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 027b7fa52e23a..4566ed1fb6a5e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -172,6 +172,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_VBLANK_USE_KTIME_T AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_GET_MM_EXE_FILE + AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_simple_kms_helper.h b/include/kcl/kcl_drm_simple_kms_helper.h new file mode 100644 index 0000000000000..51a6699486da0 --- /dev/null +++ b/include/kcl/kcl_drm_simple_kms_helper.h @@ -0,0 +1,22 @@ +/*SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (C) 2016 Noralf Trønnes + */ + +#include +#include +#include +#include + +#ifndef HAVE_DRM_SIMPLE_ENCODER_INIT +extern int _kcl_drm_simple_encoder_init(struct drm_device *dev, + struct drm_encoder *encoder, + int encoder_type); +static inline +int drm_simple_encoder_init(struct drm_device *dev, + struct drm_encoder *encoder, + int encoder_type) +{ + return _kcl_drm_simple_encoder_init(dev,encoder,encoder_type); +} +#endif From 5a408f1cfaa08c8e36d9d79b17b427893fe4a5f6 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 2 Nov 2021 12:27:34 +0800 Subject: [PATCH 0585/2653] drm/amdkcl: convert ktime_t to adapt legacy os It's caused by ba5317109d0ce7809831abfcea9b8157464b263f "drm/amdgpu: create amdgpu_vkms (v4)" v5.13-1946-gba5317109d0c Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 155bb9891a175..f8fede065406e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -101,9 +101,8 @@ static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc, *vblank_time = READ_ONCE(amdgpu_crtc->vblank_timer.node.expires); - if (WARN_ON(*vblank_time == vblank->time)) + if (WARN_ON(ktime_to_us(*vblank_time) == ktime_to_us(vblank->time))) return true; - /* * To prevent races we roll the hrtimer forward before we do any * interrupt processing - this is how real hw works (the interrupt is @@ -111,8 +110,8 @@ static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc, * the vblank core expects. Therefore we need to always correct the * timestampe by one frame. */ - *vblank_time -= output->period_ns; + *vblank_time = ktime_sub(*vblank_time, output->period_ns); return true; } From 31741746a7a2f92e4a3d43e6cc58255491a558b8 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 20 Aug 2021 18:58:21 +0800 Subject: [PATCH 0586/2653] drm/amdkcl: wrap the code under macro HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP It's caused by ba5317109d0ce7809831abfcea9b8157464b263f "drm/amdgpu: create amdgpu_vkms (v4)" v5.13-1946-gba5317109d0c Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index f8fede065406e..bf19b322724b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -122,9 +122,11 @@ static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = { .reset = drm_atomic_helper_crtc_reset, .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .enable_vblank = amdgpu_vkms_enable_vblank, .disable_vblank = amdgpu_vkms_disable_vblank, .get_vblank_timestamp = amdgpu_vkms_get_vblank_timestamp, +#endif }; static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc, From 8de9a4f7555d95526332b2e4ceb73c93bacfa272 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 3 Nov 2021 12:48:17 +0800 Subject: [PATCH 0587/2653] drm/amdkcl: test atomic_enable function in drm_crtc_helper_funcs and its argument type It's caused by ba5317109d0ce7809831abfcea9b8157464b263f "drm/amdgpu: create amdgpu_vkms (v4)" v5.13-1946-gba5317109d0c Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 26 ++++++++-- drivers/gpu/drm/amd/dkms/config/config.h | 10 +++- .../drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 | 52 +++++++++++++++++-- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 4 files changed, 81 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index bf19b322724b1..9eea96f741afc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -129,20 +129,34 @@ static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = { #endif }; -static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) +static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc +#if defined(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE) + , struct drm_atomic_state *state) +#elif defined(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE) + , struct drm_crtc_state *state) +#else + ) +#endif { drm_crtc_vblank_on(crtc); } static void amdgpu_vkms_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) +#if defined(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE) + struct drm_atomic_state *state) +#else + struct drm_crtc_state *state) +#endif { drm_crtc_vblank_off(crtc); } static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) +#if defined(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + struct drm_atomic_state *state) +#else + struct drm_crtc_state *state) +#endif { unsigned long flags; if (crtc->state->event) { @@ -161,7 +175,11 @@ static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = { .atomic_flush = amdgpu_vkms_crtc_atomic_flush, +#if defined(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE) .atomic_enable = amdgpu_vkms_crtc_atomic_enable, +#else + .enable = amdgpu_vkms_crtc_atomic_enable, +#endif .atomic_disable = amdgpu_vkms_crtc_atomic_disable, }; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 47a227eaee844..d2e0712acf4f3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -237,9 +237,17 @@ /* drm_crtc_from_index() is available */ #define HAVE_DRM_CRTC_FROM_INDEX 1 -/* drm_crtc_helper_funcs->atomic_check() wants struct drm_atomic_state arg */ +/* drm_crtc_helper_funcs->atomic_check()/atomic_flush()/atomic_begin() wants + struct drm_atomic_state arg */ #define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE 1 +/* drm_crtc_helper_funcs->atomic_enable()/atomic_disable() wants struct + drm_atomic_state arg */ +#define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE 1 + +/* have drm_crtc_helper_funcs->atomic_enable() */ +#define HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE 1 + /* drm_crtc_init_with_planes() wants name */ #define HAVE_DRM_CRTC_INIT_WITH_PLANES_VALID_WITH_NAME 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 index 7f43ce7a2f5e2..ea944aff250c5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 @@ -1,6 +1,9 @@ dnl # -dnl # commit v5.2-rc2-529-g6f3b62781bbd -dnl # drm: Convert connector_helper_funcs->atomic_check to accept drm_atomic_state +dnl # v5.10-rc2-260-g29b77ad7b9ca +dnl # drm/atomic: Pass the full state to CRTC atomic_check +dnl +dnl # v5.10-rc2-261-gf6ebe9f9c923 +dnl # drm/atomic: Pass the full state to CRTC atomic begin and flush dnl # AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK], [ AC_KERNEL_DO_BACKGROUND([ @@ -12,7 +15,50 @@ AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK], [ p->atomic_check(NULL, (struct drm_atomic_state*)NULL); ], [ AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE, 1, - [drm_crtc_helper_funcs->atomic_check() wants struct drm_atomic_state arg]) + [drm_crtc_helper_funcs->atomic_check()/atomic_flush()/atomic_begin() wants struct drm_atomic_state arg]) ]) ]) ]) + +dnl # +dnl # v5.9-rc5-1161-g351f950db4ab +dnl # drm/atomic: Pass the full state to CRTC atomic enable/disable +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_crtc_helper_funcs *p = NULL; + p->atomic_enable(NULL, (struct drm_atomic_state*)NULL); + ], [ + AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE, 1, + [drm_crtc_helper_funcs->atomic_enable()/atomic_disable() wants struct drm_atomic_state arg]) + AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE, 1, + [have drm_crtc_helper_funcs->atomic_enable()]) + + ],[ + dnl # + dnl # v4.12-rc7-1332-g0b20a0f8c3cb + dnl # drm: Add old state pointer to CRTC .enable() helper function + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_crtc_helper_funcs *p = NULL; + p->atomic_enable(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE, 1, + [have drm_crtc_helper_funcs->atomic_enable()]) + ]) + + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS], [ + AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4566ed1fb6a5e..b771c7b4dc89e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -134,7 +134,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY AC_AMDGPU_DRM_PRIME_PAGES_TO_SG - AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DRM_CRTC_HELPER_FUNCS AC_AMDGPU_DEBUGFS_CREATE_FILE_SIZE AC_AMDGPU_DRM_GEM_TTM_VMAP AC_AMDGPU_FS_RECLAIM_ACQUIRE From 04d033811b6f1a22b081a51a8ab115104583c6d4 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 4 Nov 2021 11:28:49 +0800 Subject: [PATCH 0588/2653] drm/amdkcl: fake drm_mode_config_helper_suspend/resume() It's caused by 16dcf291698ca37e89c481ae622cd5dc50afa6f4 "drm/amdgpu: replace dce_virtual with amdgpu_vkms (v3)" v5.13-1948-g16dcf291698c Signed-off-by: Flora Cui Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 3 + drivers/gpu/drm/amd/backport/Makefile | 3 +- drivers/gpu/drm/amd/backport/backport.h | 1 + .../kcl/kcl_amdgpu_drm_modeset_helper.h | 31 +++++++ .../drm/amd/backport/kcl_drm_modeset_helper.c | 89 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../dkms/m4/drm_mode_config_helper_suspend.m4 | 13 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 8 files changed, 143 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_modeset_helper.h create mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_modeset_helper.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_config_helper_suspend.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 40477c0644f6a..1d573c9bbf909 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -345,6 +345,9 @@ struct amdgpu_mode_info { int disp_priority; const struct amdgpu_display_funcs *funcs; const enum drm_plane_type *plane_type; +#ifndef HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND + struct drm_atomic_state *suspend_state; +#endif /* Driver-private color mgmt props */ diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index fa78abd428129..cba90812f73b2 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: MIT BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ - kcl_drm_gem_framebuffer_helper.o kcl_drm_gem.o + kcl_drm_gem_framebuffer_helper.o kcl_drm_gem.o \ + kcl_drm_modeset_helper.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e2a1e3e409bde..4ede69680225a 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -75,6 +75,7 @@ #include "kcl/kcl_amdgpu_drm_drv.h" #include "kcl/kcl_amdgpu_drm_gem.h" #include "kcl/kcl_drm_gem_ttm_helper.h" +#include "kcl/kcl_amdgpu_drm_modeset_helper.h" #include "kcl/kcl_mce.h" #include "kcl/kcl_drm_aperture.h" #include diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_modeset_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_modeset_helper.h new file mode 100644 index 0000000000000..611d801aa6c33 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_modeset_helper.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#ifndef AMDGPU_BACKPORT_KCL_AMDGPU_DRM_MODESET_HELPER_H +#define AMDGPU_BACKPORT_KCL_AMDGPU_DRM_MODESET_HELPER_H + +#ifndef HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND +int drm_mode_config_helper_suspend(struct drm_device *dev); +int drm_mode_config_helper_resume(struct drm_device *dev); +#endif + +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_modeset_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_modeset_helper.c new file mode 100644 index 0000000000000..e6015f0a7efce --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_drm_modeset_helper.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#include +#include "amdgpu.h" + +/* Copied from drivers/gpu/drm/drm_modeset_helper.c and modified for KCL */ +#ifndef HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND +int drm_mode_config_helper_suspend(struct drm_device *dev) +{ + struct drm_atomic_state *state; + struct amdgpu_device *adev; + struct amdgpu_fbdev *afbdev; + struct drm_fb_helper *fb_helper; + + if (!dev) + return 0; + + adev = drm_to_adev(dev); + afbdev = adev->mode_info.rfbdev; + if (!afbdev) + return 0; + + fb_helper = &afbdev->helper; + + drm_kms_helper_poll_disable(dev); + drm_fb_helper_set_suspend_unlocked(fb_helper, 1); + state = drm_atomic_helper_suspend(dev); + if (IS_ERR(state)) { + drm_fb_helper_set_suspend_unlocked(fb_helper, 0); + drm_kms_helper_poll_enable(dev); + return PTR_ERR(state); + } + + adev->mode_info.suspend_state = state; + + return 0; +} + +int drm_mode_config_helper_resume(struct drm_device *dev) +{ + int ret; + struct amdgpu_device *adev; + struct amdgpu_fbdev *afbdev; + struct drm_fb_helper *fb_helper; + + if (!dev) + return 0; + + adev = drm_to_adev(dev); + afbdev = adev->mode_info.rfbdev; + if (!afbdev) + return 0; + + fb_helper = &afbdev->helper; + + if (WARN_ON(!adev->mode_info.suspend_state)) + return -EINVAL; + + ret = drm_atomic_helper_resume(dev, adev->mode_info.suspend_state); + if (ret) + DRM_ERROR("Failed to resume (%d)\n", ret); + adev->mode_info.suspend_state = NULL; + + drm_fb_helper_set_suspend_unlocked(fb_helper, 0); + drm_kms_helper_poll_enable(dev); + + return ret; +} +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d2e0712acf4f3..087e718c16ab9 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -565,6 +565,9 @@ /* drm_mode_config->helper_private is available */ #define HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE 1 +/* drm_mode_config_helper_{suspend/resume}() is available */ +#define HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND 1 + /* drm_mode_get_hv_timing is available */ #define HAVE_DRM_MODE_GET_HV_TIMING 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_helper_suspend.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_helper_suspend.m4 new file mode 100644 index 0000000000000..8d30e1afba578 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_helper_suspend.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # v4.14-rc7-1626-gca038cfb5cfa +dnl # drm/modeset-helper: Add simple modeset suspend/resume helpers +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG_HELPER_SUSPEND], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_mode_config_helper_suspend drm_mode_config_helper_resume], + [drivers/gpu/drm/drm_modeset_helper.c],[ + AC_DEFINE(HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND, 1, + [drm_mode_config_helper_{suspend/resume}() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b771c7b4dc89e..4808f6040db6a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -173,6 +173,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_GET_MM_EXE_FILE AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT + AC_AMDGPU_DRM_MODE_CONFIG_HELPER_SUSPEND AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From d714151831efe894b10bfbfea0fefb410187f6bc Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 2 Nov 2021 21:41:40 +0800 Subject: [PATCH 0589/2653] drm/amdkcl: wrap code under macro AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS It's caused by ba5317109d0ce7809831abfcea9b8157464b263f "drm/amdgpu: create amdgpu_vkms (v4)" v5.13-1946-gba5317109d0c Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 9eea96f741afc..317a8faacb1e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -280,16 +280,26 @@ static const struct drm_plane_funcs amdgpu_vkms_plane_funcs = { }; static void amdgpu_vkms_plane_atomic_update(struct drm_plane *plane, +#if defined(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS) struct drm_atomic_state *old_state) +#else + struct drm_plane_state *old_state) +#endif { return; } static int amdgpu_vkms_plane_atomic_check(struct drm_plane *plane, +#if defined(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS) struct drm_atomic_state *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); +#else + struct drm_plane_state *new_plane_state) +{ + struct drm_atomic_state *state = new_plane_state->state; +#endif struct drm_crtc_state *crtc_state; int ret; @@ -298,6 +308,7 @@ static int amdgpu_vkms_plane_atomic_check(struct drm_plane *plane, crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc); + if (IS_ERR(crtc_state)) return PTR_ERR(crtc_state); From f1d196c9089f6c30446ff054dbfce64e15f5e293 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Sat, 6 Nov 2021 20:01:37 +0800 Subject: [PATCH 0590/2653] drm/amdkcl: update sources file to include kfd_sysfs.h Fix: 1aefe844453b("drm/amdkfd: Add sysfs bitfields and enums to uAPI") Signed-off-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/sources | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources index a1b74441203de..da9e9612a23fb 100644 --- a/drivers/gpu/drm/amd/dkms/sources +++ b/drivers/gpu/drm/amd/dkms/sources @@ -28,3 +28,4 @@ include/drm/amd_rdma.h include/drm/ drivers/dma-buf/dma-resv.c amd/amdkcl/dma-buf/ include/linux/dma-resv.h include/linux/ include/kcl/reservation.h include/linux/ +include/uapi/linux/kfd_sysfs.h include/uapi/linux/ From 3861c52f6f97ad6cc81d8628053627647b0b1277 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Mon, 8 Nov 2021 14:58:25 +0800 Subject: [PATCH 0591/2653] drm/amdkcl: guard amdgpu_driver_release_kms by HAVE_DRM_DRIVER_RELEASE Fix: 1776040c6227("drm/amd/amdkcl: fix minor index not removed after unload driver") Signed-off-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 5d36cfff399dd..4c412c3baa3ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1578,7 +1578,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, pm_runtime_put_autosuspend(dev->dev); } - +#ifdef HAVE_DRM_DRIVER_RELEASE void amdgpu_driver_release_kms(struct drm_device *dev) { struct amdgpu_device *adev = drm_to_adev(dev); @@ -1590,6 +1590,7 @@ void amdgpu_driver_release_kms(struct drm_device *dev) kfree(adev); #endif } +#endif /* * VBlank related functions. From 2e942a1dd088bd6bade43b60d51ff52b9e57d2fd Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 8 Nov 2021 10:55:23 +0800 Subject: [PATCH 0592/2653] drm/amdkcl: drop drmP.h in kcl_drm_simple_encoder_init.h Fix a intree build error caused by 925fd65464c80f28ed1bea7357c7389acbb618ea "drm/amdkcl: fake drm_simple_encoder_init" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- include/kcl/kcl_drm_simple_kms_helper.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_drm_simple_kms_helper.h b/include/kcl/kcl_drm_simple_kms_helper.h index 51a6699486da0..f6a5ac0c15d00 100644 --- a/include/kcl/kcl_drm_simple_kms_helper.h +++ b/include/kcl/kcl_drm_simple_kms_helper.h @@ -4,7 +4,7 @@ */ #include -#include +#include #include #include From a5ee1eea2cb6208d3d613dc9cfca498811dd909a Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 1 Nov 2021 20:18:06 +0800 Subject: [PATCH 0593/2653] drm/amdkcl: assign dpms for amdgpu_vkms_crtc_helper_funcs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In drm_helper_disable_unused_functions(), when !crtc->enable is false, a NULL pointer crtc_funcs->dpms may occur. To avoid this, assign dpms for amdgpu_vkms_crtc_helper_funcs. Call Trace: __drm_helper_disable_unused_functions+0xac/0xe0 [drm_kms_helper] drm_helper_disable_unused_functions+0x38/0x60 [drm_kms_helper] amdgpu_fbdev_init+0xf6/0x100 [amdgpu] amdgpu_device_init+0x13d4/0x1f10 [amdgpu] Fixes: ba5317109d0ce ("drm/amdgpu: create amdgpu_vkms (v4)") Ackded-by：Guchun Chen Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 317a8faacb1e8..b66b4ad3769dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -173,7 +173,33 @@ static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, } } +static void amdgpu_vkms_crtc_dpms(struct drm_crtc *crtc, int mode) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + unsigned type; + + switch (mode) { + case DRM_MODE_DPMS_ON: + amdgpu_crtc->enabled = true; + /* Make sure VBLANK interrupts are still enabled */ + type = amdgpu_display_crtc_idx_to_irq_type(adev, + amdgpu_crtc->crtc_id); + amdgpu_irq_update(adev, &adev->crtc_irq, type); + drm_crtc_vblank_on(crtc); + break; + case DRM_MODE_DPMS_STANDBY: + case DRM_MODE_DPMS_SUSPEND: + case DRM_MODE_DPMS_OFF: + drm_crtc_vblank_off(crtc); + amdgpu_crtc->enabled = false; + break; + } +} + static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = { + .dpms = amdgpu_vkms_crtc_dpms, .atomic_flush = amdgpu_vkms_crtc_atomic_flush, #if defined(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE) .atomic_enable = amdgpu_vkms_crtc_atomic_enable, From 8faeb32bc0cab1b16496ccd7a6b11778123f4e9b Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Tue, 26 Oct 2021 17:35:34 -0500 Subject: [PATCH 0594/2653] drm/amdkfd: Pin MMIO/DOORBELL BO's in GTT domain MMIO/DOORBELL BOs encode control data and should be pinned in GTT domain before enabling PCIe connected peer devices in accessing it Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 23 ++++++++++++++++++- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 17 ++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 3 ++- 3 files changed, 41 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 804b36d384826..d24f26ae086e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -336,7 +336,28 @@ struct amdgpu_bo *amdgpu_amdkfd_gpuvm_get_bo_ref(struct kgd_mem *mem, uint32_t *flags); void amdgpu_amdkfd_gpuvm_put_bo_ref(struct amdgpu_bo *bo); -int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo); +/** + * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria + * @bo: Handle of buffer object being pinned + * @domain: Domain into which BO should be pinned + * + * - USERPTR BOs are UNPINNABLE and will return error + * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their + * PIN count incremented. It is valid to PIN a BO multiple times + * + * Return: ZERO if successful in pinning, Non-Zero in case of error. + * Will return -EINVAL if input BO parameter is a USERPTR type. + */ +int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain); + +/** + * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria + * @bo: Handle of buffer object being unpinned + * + * - Is a illegal request for USERPTR BOs and is ignored + * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their + * PIN count decremented. Calls to UNPIN must balance calls to PIN + */ void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo); int amdgpu_amdkfd_gpuvm_get_sg_table(struct kgd_dev *kgd, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index a24218062173a..0d10534671ebb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1896,6 +1896,23 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( if (offset) *offset = amdgpu_bo_mmap_offset(bo); + if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | + KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { + ret = amdgpu_amdkfd_bo_validate(bo, AMDGPU_GEM_DOMAIN_GTT, false); + if (ret) { + pr_err("Validating MMIO/DOORBELL BO during ALLOC FAILED\n"); + goto err_node_allow; + } + + ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT); + if (ret) { + pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n"); + goto err_node_allow; + } + bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; + bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; + } + return 0; allocate_init_user_pages_failed: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index 27fe96b788de6..f8c89ba5ff86b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -261,7 +261,8 @@ static int amd_get_pages(unsigned long addr, size_t size, int write, int force, return -EINVAL; } - ret = amdgpu_amdkfd_gpuvm_pin_bo(mem_context->bo); + ret = amdgpu_amdkfd_gpuvm_pin_bo(mem_context->bo, + mem_context->bo->kfd_bo->domain); if (ret) { pr_err("Pinning of buffer failed.\n"); return ret; From 7bda1dbede2e953d4faa75fb48b23ed47ca3a20d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 9 Nov 2021 17:49:38 +0800 Subject: [PATCH 0595/2653] drm/amdkcl: nuke dpms callback Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 22 +--------------------- 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index b66b4ad3769dc..0edd81db831de 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -175,27 +175,7 @@ static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, static void amdgpu_vkms_crtc_dpms(struct drm_crtc *crtc, int mode) { - struct drm_device *dev = crtc->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - unsigned type; - - switch (mode) { - case DRM_MODE_DPMS_ON: - amdgpu_crtc->enabled = true; - /* Make sure VBLANK interrupts are still enabled */ - type = amdgpu_display_crtc_idx_to_irq_type(adev, - amdgpu_crtc->crtc_id); - amdgpu_irq_update(adev, &adev->crtc_irq, type); - drm_crtc_vblank_on(crtc); - break; - case DRM_MODE_DPMS_STANDBY: - case DRM_MODE_DPMS_SUSPEND: - case DRM_MODE_DPMS_OFF: - drm_crtc_vblank_off(crtc); - amdgpu_crtc->enabled = false; - break; - } + return; } static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = { From f0db330089aebf127847eadf1b5b08824a753d7d Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 10 Nov 2021 15:04:58 -0600 Subject: [PATCH 0596/2653] drm/amdgpu: Fix error handling path while allocating MMIO/DOORBELL BOs MMIO/DOORBELL BOs are pinned as part allocation procedure. The patch fixes a bug in error handling part of pinning MMIO/DOORBELL BO Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8 +------- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index d24f26ae086e1..10935711ae95e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -346,7 +346,6 @@ void amdgpu_amdkfd_gpuvm_put_bo_ref(struct amdgpu_bo *bo); * PIN count incremented. It is valid to PIN a BO multiple times * * Return: ZERO if successful in pinning, Non-Zero in case of error. - * Will return -EINVAL if input BO parameter is a USERPTR type. */ int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 0d10534671ebb..189e612ea6a02 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1898,16 +1898,10 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { - ret = amdgpu_amdkfd_bo_validate(bo, AMDGPU_GEM_DOMAIN_GTT, false); - if (ret) { - pr_err("Validating MMIO/DOORBELL BO during ALLOC FAILED\n"); - goto err_node_allow; - } - ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT); if (ret) { pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n"); - goto err_node_allow; + goto err_pin_bo; } bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; From 7930d0909d23c71918b5fcca5bb4db8e25412758 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 11 Nov 2021 14:09:46 +0800 Subject: [PATCH 0597/2653] drm/amdkcl: check whether drm_fbdev_generic_setup() is available It's caused by 844612e1149d0cd6fd2346018c91f5744b2615f5 "drm/amdgpu: use generic fb helpers instead of setting up AMD own's." v5.13-2445-g844612e1149d Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 20 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 087e718c16ab9..4ec060c7b20cf 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -462,6 +462,9 @@ /* drm_encoder_find() wants file_priv */ #define HAVE_DRM_ENCODER_FIND_VALID_WITH_FILE 1 +/* drm_fbdev_generic_setup() is available */ +#define HAVE_DRM_FBDEV_GENERIC_SETUP 1 + /* drm_fb_helper_single_add_all_connectors() && drm_fb_helper_remove_one_connector() are symbol */ /* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 new file mode 100644 index 0000000000000..cfd16b033ccbf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v4.18-rc3-614-g9060d7f49376 +dnl # drm/fb-helper: Finish the generic fbdev emulation +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_fbdev_generic_setup(NULL, 0); + ], [drm_fbdev_generic_setup], [drivers/gpu/drm/drm_fb_helper.c],[ + AC_DEFINE(HAVE_DRM_FBDEV_GENERIC_SETUP, 1, + [drm_fbdev_generic_setup() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4808f6040db6a..027e22b36012d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -174,6 +174,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_GET_MM_EXE_FILE AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT AC_AMDGPU_DRM_MODE_CONFIG_HELPER_SUSPEND + AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 631e932adc733cdf7662beb297f144f1207456d3 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 11 Nov 2021 15:07:23 +0800 Subject: [PATCH 0598/2653] drm/amdkcl: check whether struct drm_device has fb_helper member It's caused by 844612e1149d0cd6fd2346018c91f5744b2615f5 "drm/amdgpu: use generic fb helpers instead of setting up AMD own's." v5.13-2445-g844612e1149d Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 3 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 29 +++++++++++++++++++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 5 +++- drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../drm/amd/dkms/m4/drm-device-fb-helper.m4 | 21 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 7 files changed, 62 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 56c0a7b960b45..dda726c04b7b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -50,7 +50,7 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \ amdgpu_atombios.o atombios_crtc.o amdgpu_connectors.o \ atom.o amdgpu_fence.o amdgpu_ttm.o amdgpu_object.o amdgpu_gart.o \ amdgpu_encoders.o amdgpu_display.o amdgpu_i2c.o \ - amdgpu_gem.o amdgpu_ring.o \ + amdgpu_fb.o amdgpu_gem.o amdgpu_ring.o \ amdgpu_cs.o amdgpu_bios.o amdgpu_benchmark.o \ atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \ atombios_encoders.o amdgpu_sa.o atombios_i2c.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 2367c391e6f33..7fbd2b4f964b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -24,6 +24,8 @@ * David Airlie */ +#ifndef HAVE_DRM_DEVICE_FB_HELPER + #include #include #include @@ -412,3 +414,4 @@ bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) return true; return false; } +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 1d573c9bbf909..cac467bd718c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -231,6 +231,11 @@ struct amdgpu_i2c_chan { struct mutex mutex; }; + +#ifndef HAVE_DRM_DEVICE_FB_HELPER +struct amdgpu_fbdev; +#endif + struct amdgpu_afmt { bool enabled; int offset; @@ -310,6 +315,15 @@ struct amdgpu_framebuffer { uint64_t address; }; +#ifndef HAVE_DRM_DEVICE_FB_HELPER +struct amdgpu_fbdev { + struct drm_fb_helper helper; + struct amdgpu_framebuffer rfb; + struct list_head fbdev_list; + struct amdgpu_device *adev; +}; +#endif + struct amdgpu_mode_info { struct atom_context *atom_context; struct card_info *atom_card_info; @@ -332,6 +346,10 @@ struct amdgpu_mode_info { /* hardcoded DFP edid from BIOS */ const struct drm_edid *bios_hardcoded_edid; +#ifndef HAVE_DRM_DEVICE_FB_HELPER + /* pointer to fbdev info structure */ + struct amdgpu_fbdev *rfbdev; +#endif /* firmware flags */ u32 firmware_flags; /* pointer to backlight encoder */ @@ -704,6 +722,17 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode); +#ifndef HAVE_DRM_DEVICE_FB_HELPER +/* fbdev layer */ +int amdgpu_fbdev_init(struct amdgpu_device *adev); +void amdgpu_fbdev_fini(struct amdgpu_device *adev); +void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); +int amdgpu_fbdev_total_size(struct amdgpu_device *adev); +bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); + +int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); +#endif + /* amdgpu_display.c */ void amdgpu_display_print_display_setup(struct drm_device *dev); int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index ebf0f5d41c9cc..3349e6d8a98a1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -862,7 +862,7 @@ static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, mutex_unlock(&mgr->lock); } drm_connector_unregister(connector); -#ifdef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS +#if defined(HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS) && !defined(HAVE_DRM_DEVICE_FB_HELPER) if (adev->mode_info.rfbdev) drm_fb_helper_remove_one_connector(&adev->mode_info.rfbdev->helper, connector); #endif @@ -889,10 +889,13 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector) #ifndef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_modeset_lock_all(dev); #endif + +#ifndef HAVE_DRM_DEVICE_FB_HELPER if (adev->mode_info.rfbdev) drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector); else DRM_ERROR("adev->mode_info.rfbdev is NULL\n"); +#endif #ifndef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_modeset_unlock_all(dev); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4ec060c7b20cf..32b8940f5385e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -257,6 +257,9 @@ /* dev_device->driver_features is available */ #define HAVE_DRM_DEVICE_DRIVER_FEATURES 1 +/* struct drm_device has fb_helper member */ +#define HAVE_DRM_DEVICE_FB_HELPER 1 + /* drm_device->filelist_mutex is available */ #define HAVE_DRM_DEVICE_FILELIST_MUTEX 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 new file mode 100644 index 0000000000000..b5e24caf0a842 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v4.14-rc3-575-g29ad20b22c8f +dnl # drm: Add drm_device->fb_helper pointer +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEVICE_FB_HELPER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + #include + #endif + #ifdef HAVE_DRM_DRM_DEVICE_H + #include + #endif + ], [ + struct drm_device *pdd = NULL; + pdd->fb_helper = NULL; + ], [ + AC_DEFINE(HAVE_DRM_DEVICE_FB_HELPER, 1, [struct drm_device has fb_helper member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 027e22b36012d..8a6ac6cd7885b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -175,6 +175,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT AC_AMDGPU_DRM_MODE_CONFIG_HELPER_SUSPEND AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP + AC_AMDGPU_DRM_DEVICE_FB_HELPER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 9b8704ad92f4106403048b033ef9ced0488068b5 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Fri, 12 Nov 2021 12:40:38 -0500 Subject: [PATCH 0599/2653] drm/amdkfd: remove unused variable in alloc gpuvm Unused "int mem_type" got removed in drm-next during alloc gpuvm update but not in dkms staging for whatever reason. Remove it to silence the usused variable warning during compile. Signed-off-by: Jonathan Kim Reviewed-by: Kevin Wang --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 95f0d3e9af690..d4cc101062152 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -756,7 +756,6 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, { struct kfd_node *kdev = pdd->dev; int err; - unsigned int mem_type; err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, gpu_va, size, pdd->drm_priv, mem, NULL, From faa814b1eff23503be15c524fd406c80e11e6a6a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 15 Nov 2021 17:38:07 +0800 Subject: [PATCH 0600/2653] drm/amdgpu: fix amdgpu_vkms support otherwise adev->mode_info.crtcs[] & adev->mode_info.funcs are NULL and would trigger NULL pointer error Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 67 ++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 0edd81db831de..b8abf993cfe91 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -523,6 +523,73 @@ static int amdgpu_vkms_output_init(struct drm_device *dev, struct return ret; } +static u32 amdgpu_vkms_vblank_get_counter(struct amdgpu_device *adev, int crtc) +{ + return 0; +} + +static void amdgpu_vkms_page_flip(struct amdgpu_device *adev, + int crtc_id, u64 crtc_base, bool async) +{ + return; +} + +static int amdgpu_vkms_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, + u32 *vbl, u32 *position) +{ + *vbl = 0; + *position = 0; + + return -EINVAL; +} + +static bool amdgpu_vkms_hpd_sense(struct amdgpu_device *adev, + enum amdgpu_hpd_id hpd) +{ + return true; +} + +static void amdgpu_vkms_hpd_set_polarity(struct amdgpu_device *adev, + enum amdgpu_hpd_id hpd) +{ + return; +} + +static u32 amdgpu_vkms_hpd_get_gpio_reg(struct amdgpu_device *adev) +{ + return 0; +} + +static void amdgpu_vkms_bandwidth_update(struct amdgpu_device *adev) +{ + return; +} + +static const struct amdgpu_display_funcs amdgpu_vkms_display_funcs = { + .bandwidth_update = &amdgpu_vkms_bandwidth_update, + .vblank_get_counter = &amdgpu_vkms_vblank_get_counter, + .backlight_set_level = NULL, + .backlight_get_level = NULL, + .hpd_sense = &amdgpu_vkms_hpd_sense, + .hpd_set_polarity = &amdgpu_vkms_hpd_set_polarity, + .hpd_get_gpio_reg = &amdgpu_vkms_hpd_get_gpio_reg, + .page_flip = &amdgpu_vkms_page_flip, + .page_flip_get_scanoutpos = &amdgpu_vkms_crtc_get_scanoutpos, + .add_encoder = NULL, + .add_connector = NULL, +}; + +static int amdgpu_vkms_early_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + adev->mode_info.funcs = &amdgpu_vkms_display_funcs; + + adev->mode_info.num_hpd = 1; + adev->mode_info.num_dig = 1; + return 0; +} + const struct drm_mode_config_funcs amdgpu_vkms_mode_funcs = { .fb_create = amdgpu_display_user_framebuffer_create, .atomic_check = drm_atomic_helper_check, From 58a5f0354a1a1ab5ef10725c64d03a45ba87d178 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 11 Nov 2021 15:55:39 +0800 Subject: [PATCH 0601/2653] drm/amdkcl: check whether drm_dp_update_payload_part1() has start_slot argument It's caused by cf95d5c0c94100fd76bb590657ceb94db4097c42 "drm: Update MST First Link Slot Information Based on Encoding Format" v5.13-2803-gcf95d5c0c941 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ ...drm-up-update-payload-part1-start-slot-arg.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 20 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 32b8940f5385e..6209ae0f757a7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -359,6 +359,9 @@ /* drm_dp_start_crc() is available */ #define HAVE_DRM_DP_START_CRC 1 +/* drm_dp_update_payload_part1() function has start_slot argument */ +#define HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG 1 + /* drm_driver->gem_prime_res_obj() is available */ /* #undef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 new file mode 100644 index 0000000000000..1b341003bb985 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.13-2803-gcf95d5c0c941 +dnl # drm: Update MST First Link Slot Information Based on Encoding Format +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_update_payload_part1(NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG, 1, + [drm_dp_update_payload_part1() function has start_slot argument]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8a6ac6cd7885b..ee0cd4fd2f658 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -176,6 +176,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MODE_CONFIG_HELPER_SUSPEND AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP AC_AMDGPU_DRM_DEVICE_FB_HELPER + AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 15d8234eaec4d4a0f7c67526ccdb17e2f85dedfc Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 15 Nov 2021 13:03:51 +0800 Subject: [PATCH 0602/2653] drm/amdkcl: test whether struct drm_dp_mst_topology_state has member total_avail_slots It's caused by cf95d5c0c94100fd76bb590657ceb94db4097c42 "drm: Update MST First Link Slot Information Based on Encoding Format" v5.13-2803-gcf95d5c0c941 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-dp-mst-topology-state.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 480fb03a00a7c..17b52812a429b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12339,6 +12339,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS /* set the slot info for each mst_state based on the link encoding format */ for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { struct amdgpu_dm_connector *aconnector; @@ -12358,7 +12359,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } drm_connector_list_iter_end(&iter); } - +#endif /** * Streams and planes are reset when there are changes that affect * bandwidth. Anything that affects bandwidth needs to go through diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6209ae0f757a7..c448f4fcde788 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -353,6 +353,9 @@ /* drm_dp_mst_topology_mgr_resume() wants 2 args */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS 1 +/* struct drm_dp_mst_topology_state has member total_avail_slots */ +#define HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS 1 + /* drm_dp_send_real_edid_checksum() is available */ #define HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 new file mode 100644 index 0000000000000..bd46fb9e30abb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v4.11-rc7-1869-g3f3353b7e121 +dnl # drm/dp: Introduce MST topology state to track available link bandwidth +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_state * mst_state = NULL; + mst_state->total_avail_slots = 0; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS, 1, + [struct drm_dp_mst_topology_state has member total_avail_slots]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ee0cd4fd2f658..5952e31fb027d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -177,6 +177,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP AC_AMDGPU_DRM_DEVICE_FB_HELPER AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 3478d0e64e2f39df56eb34e7db868c37857be0dc Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 12 Nov 2021 11:22:38 -0500 Subject: [PATCH 0603/2653] drm/amdkcl: use autoconf to tarck amdgpu version Change-Id: Idef567dd18760272fbc5e4b7fda76d35f47062d0 Signed-off-by: Slava Grigorev Reviewed-by: Jeremy Newton Reviewed-by: Rui Teng --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 - drivers/gpu/drm/amd/dkms/configure.ac | 2 +- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 1d139b093daa8..15ba1c8d69345 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -131,7 +131,6 @@ #define KMS_DRIVER_MINOR 64 #define KMS_DRIVER_PATCHLEVEL 0 -#define AMDGPU_VERSION "19.10.9.418" /* * amdgpu.debug module options. Are all disabled by default */ diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index b367e452d4cbb..71855ccd6e523 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 19.40) +AC_INIT(amdgpu-dkms, 5.13.5) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5952e31fb027d..52a97889a6ede 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -186,6 +186,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_SUBST(KERNEL_MAKE) AH_BOTTOM([#include "config-amd-chips.h"]) + AH_BOTTOM([#define AMDGPU_VERSION PACKAGE_VERSION]) ]) dnl # From 159a47204742002495b3a7eec9ddd65d6ba2480a Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 18 Nov 2021 09:59:29 -0500 Subject: [PATCH 0604/2653] Version strings in DKMS config.h Correct version strings in config.h and add AMDGPU_VERSION macro to fix in-tree kernel build. Other diffs observed in the file after regeneration are pointing to problematic tests that may affect DKMS functionality. They have to be re-visited and fixed. The list of suspicious test results is: HAVE_ACPI_PUT_TABLE HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS Change-Id: I5afb975182c029d047f71356098514196b719aee Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/config/config.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c448f4fcde788..a7cc3bf23c054 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1127,7 +1127,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 19.40" +#define PACKAGE_STRING "amdgpu-dkms 5.13.6" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1136,6 +1136,8 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "19.40" +#define PACKAGE_VERSION "5.13.6" #include "config-amd-chips.h" + +#define AMDGPU_VERSION PACKAGE_VERSION From 2255459067add937e369c6e616ae9536cd7d5ff9 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 18 Nov 2021 16:17:34 +0800 Subject: [PATCH 0605/2653] drm/amdkcl: guard CONFIG_X86 for x86 related stuff Signed-off-by: Flora Cui Tested-by: Emily.Deng Reviewed-by: Leslie Shi --- include/kcl/kcl_intel_family.h | 4 +++- include/kcl/kcl_mce.h | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/include/kcl/kcl_intel_family.h b/include/kcl/kcl_intel_family.h index 20781af676d6b..a4d7693bf0b0b 100644 --- a/include/kcl/kcl_intel_family.h +++ b/include/kcl/kcl_intel_family.h @@ -2,11 +2,13 @@ #ifndef AMDKCL_INTEL_FAMILY_H #define AMDKCL_INTEL_FAMILY_H +#ifdef CONFIG_X86 + #include /* Copied froma asm/intel-family.h*/ #ifndef INTEL_FAM6_ROCKETLAKE #define INTEL_FAM6_ROCKETLAKE 0xA7 #endif +#endif /* CONFIG_X86 */ #endif - diff --git a/include/kcl/kcl_mce.h b/include/kcl/kcl_mce.h index 037fb0c1b3e37..5418ec9351e36 100644 --- a/include/kcl/kcl_mce.h +++ b/include/kcl/kcl_mce.h @@ -2,10 +2,14 @@ #ifndef AMDKCL_MCE_H #define AMDKCL_MCE_H +#ifdef CONFIG_X86 + #include + /* Copied from asm/mce.h */ #ifndef XEC #define XEC(x, mask) (((x) >> 16) & mask) #endif +#endif /* CONFIG_X86 */ #endif From 397ea42b777294651325eec54e72ea6ef7f5a64f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 18 Nov 2021 16:18:34 +0800 Subject: [PATCH 0606/2653] drm/amdkcl: misc fix for autoconf test Signed-off-by: Flora Cui Tested-by: Emily.Deng Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/access-ok.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 b/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 index 066bd767ddf78..70a1ec664ef7f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 @@ -9,7 +9,7 @@ AC_DEFUN([AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS], [ AC_KERNEL_TRY_COMPILE([ #include ],[ - access_ok(1, 1); + access_ok(0, 0); ],[ AC_DEFINE(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS, 1, [whether access_ok(x, x) is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 b/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 index ad484a873022a..5b80d8cf1223a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 @@ -5,6 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_MEM_ENCRYPT_ACTIVE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #include #include ], [ mem_encrypt_active(); From 548c1b8a9c2a5a0c14e550180a90ad9efa5b3102 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 22 Jan 2024 16:05:41 +0800 Subject: [PATCH 0607/2653] drm/amdkcl: fix vkms hrtimer settings Signed-off-by: Flora Cui Reviewed-by: Guchun Chen Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 62 +++++++++++++++++++++--- include/kcl/backport/kcl_drm_backport.h | 8 +++ 2 files changed, 63 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index b8abf993cfe91..b30f83aa53f00 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -47,6 +47,7 @@ static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer) { struct amdgpu_crtc *amdgpu_crtc = container_of(timer, struct amdgpu_crtc, vblank_timer); struct drm_crtc *crtc = &amdgpu_crtc->base; + struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc); u64 ret_overrun; bool ret; @@ -100,7 +101,6 @@ static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc, } *vblank_time = READ_ONCE(amdgpu_crtc->vblank_timer.node.expires); - if (WARN_ON(ktime_to_us(*vblank_time) == ktime_to_us(vblank->time))) return true; /* @@ -173,13 +173,8 @@ static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, } } -static void amdgpu_vkms_crtc_dpms(struct drm_crtc *crtc, int mode) -{ - return; -} static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = { - .dpms = amdgpu_vkms_crtc_dpms, .atomic_flush = amdgpu_vkms_crtc_atomic_flush, #if defined(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE) .atomic_enable = amdgpu_vkms_crtc_atomic_enable, @@ -219,12 +214,33 @@ static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, return ret; } +#ifdef AMDKCL_DRM_CONNECTOR_FUNCS_DPMS_MANDATORY +static int +amdgpu_vkms_connector_dpms(struct drm_connector *connector, int mode) +{ + return 0; +} + + +static int +amdgpu_vkms_connector_set_property(struct drm_connector *connector, + struct drm_property *property, + uint64_t val) +{ + return 0; +} +#endif + static const struct drm_connector_funcs amdgpu_vkms_connector_funcs = { .fill_modes = drm_helper_probe_single_connector_modes, .destroy = drm_connector_cleanup, .reset = drm_atomic_helper_connector_reset, .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +#ifdef AMDKCL_DRM_CONNECTOR_FUNCS_DPMS_MANDATORY + .set_property = amdgpu_vkms_connector_set_property, + .dpms = amdgpu_vkms_connector_dpms, +#endif }; static int amdgpu_vkms_conn_get_modes(struct drm_connector *connector) @@ -523,6 +539,7 @@ static int amdgpu_vkms_output_init(struct drm_device *dev, struct return ret; } +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP static u32 amdgpu_vkms_vblank_get_counter(struct amdgpu_device *adev, int crtc) { return 0; @@ -579,16 +596,47 @@ static const struct amdgpu_display_funcs amdgpu_vkms_display_funcs = { .add_connector = NULL, }; +static int amdgpu_vkms_set_crtc_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + if (type > AMDGPU_CRTC_IRQ_VBLANK6) + return -EINVAL; + + if (type >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[type]) { + DRM_DEBUG("invalid crtc %d\n", type); + return -EINVAL; + } + + adev->mode_info.crtcs[type]->vsync_timer_enabled = state; + + if (state == AMDGPU_IRQ_STATE_ENABLE) + amdgpu_vkms_enable_vblank(&adev->mode_info.crtcs[type]->base); + else + amdgpu_vkms_disable_vblank(&adev->mode_info.crtcs[type]->base); + + return 0; +} + +static const struct amdgpu_irq_src_funcs amdgpu_vkms_crtc_irq_funcs = { + .set = amdgpu_vkms_set_crtc_irq_state, + .process = NULL, +}; + static int amdgpu_vkms_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - adev->mode_info.funcs = &amdgpu_vkms_display_funcs; + adev->crtc_irq.num_types = adev->mode_info.num_crtc; + adev->crtc_irq.funcs = &amdgpu_vkms_crtc_irq_funcs; + adev->mode_info.funcs = &amdgpu_vkms_display_funcs; adev->mode_info.num_hpd = 1; adev->mode_info.num_dig = 1; return 0; } +#endif const struct drm_mode_config_funcs amdgpu_vkms_mode_funcs = { .fb_create = amdgpu_display_user_framebuffer_create, diff --git a/include/kcl/backport/kcl_drm_backport.h b/include/kcl/backport/kcl_drm_backport.h index 668fa168e20bd..c17c10af84c09 100644 --- a/include/kcl/backport/kcl_drm_backport.h +++ b/include/kcl/backport/kcl_drm_backport.h @@ -22,4 +22,12 @@ #define AMDKCL_DMA_BUF_SHARE_ADDR_SPACE #endif +/* + * commit v4.13-rc2-365-g144a7999d633 + * drm: Handle properties in the core for atomic drivers + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 14, 0) +#define AMDKCL_DRM_CONNECTOR_FUNCS_DPMS_MANDATORY +#endif + #endif/*AMDKCL_DRM_BACKPORT_H*/ From 3ada42a68f2aab0514ee3155ebcf45328abb9eef Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 18 Nov 2021 16:25:45 +0800 Subject: [PATCH 0608/2653] drm/amdkcl: update related flags for atomic unsupported case Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 15ba1c8d69345..b18e93593329b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2349,8 +2349,10 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, return -ENODEV; } - if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) - amdgpu_aspm = 0; + if (flags == 0) { + DRM_INFO("Unsupported asic. Remove me when IP discovery init is in place.\n"); + return -ENODEV; + } if (amdgpu_virtual_display || amdgpu_device_asic_has_dc_support(pdev, flags & AMD_ASIC_MASK)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 7fbd2b4f964b9..6f1dd87d31ee9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -369,7 +369,7 @@ int amdgpu_fbdev_init(struct amdgpu_device *adev) } /* disable all the possible outputs/crtcs before entering KMS mode */ - if (!amdgpu_device_has_dc_support(adev)) + if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev))) drm_helper_disable_unused_functions(adev_to_drm(adev)); drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); From 5bb838f19beb4d719f4ca8a5a4bcf52bd1d1fbc8 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 19 Nov 2021 10:34:32 +0800 Subject: [PATCH 0609/2653] drm/amdkcl: add strict restriction when calling drm_fbdev_generic_setup It's caused by 844612e1149d0cd6fd2346018c91f5744b2615f5 "drm/amdgpu: use generic fb helpers instead of setting up AMD own's." v5.13-2445-g844612e1149d Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 13 +++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 7 +++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 8 ++++---- include/kcl/backport/kcl_drm_fb.h | 6 ++++++ 6 files changed, 37 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 5f07e4db9081e..3bb95f5daa055 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4738,6 +4738,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, /* Get a log2 for easy divisions. */ adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); +#ifndef AMDKCL_DRM_FBDEV_GENERIC + amdgpu_fbdev_init(adev); +#endif /* * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost. * Otherwise the mgpu fan boost feature will be skipped due to the @@ -4934,6 +4937,9 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) amdgpu_reg_state_sysfs_fini(adev); amdgpu_xcp_sysfs_fini(adev); +#ifndef AMDKCL_DRM_FBDEV_GENERIC + amdgpu_fbdev_fini(adev); +#endif /* disable ras feature must before hw fini */ amdgpu_ras_pre_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 6e7404787251c..85b171befd2ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1954,6 +1954,7 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, stime, etime, mode); } +#ifdef AMDKCL_DRM_FBDEV_GENERIC static bool amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) { @@ -1968,6 +1969,7 @@ amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) return true; } +#endif int amdgpu_display_suspend_helper(struct amdgpu_device *adev) { @@ -2017,6 +2019,16 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) continue; robj = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); +#ifndef AMDKCL_DRM_FBDEV_GENERIC + /* don't unpin kernel fb objects */ + if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { + r = amdgpu_bo_reserve(robj, true); + if (r == 0) { + amdgpu_bo_unpin(robj); + amdgpu_bo_unreserve(robj); + } + } +#else if (!amdgpu_display_robj_is_fb(adev, robj)) { r = amdgpu_bo_reserve(robj, true); if (r == 0) { @@ -2024,6 +2036,7 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) amdgpu_bo_unreserve(robj); } } +#endif } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 6f1dd87d31ee9..60bf213b8c85d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -24,7 +24,7 @@ * David Airlie */ -#ifndef HAVE_DRM_DEVICE_FB_HELPER +#ifndef AMDKCL_DRM_FBDEV_GENERIC #include #include diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index e584069220fe9..31f393fd2d2c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -1165,6 +1165,7 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, return r; } +#ifdef AMDKCL_DRM_FBDEV_GENERIC static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, int width, int cpp, @@ -1190,6 +1191,7 @@ static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, aligned &= ~pitch_mask; return aligned * cpp; } +#endif int amdgpu_mode_dumb_create(struct drm_file *file_priv, struct drm_device *dev, @@ -1213,8 +1215,13 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv, if (adev->mman.buffer_funcs_enabled) flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; +#ifdef AMDKCL_DRM_FBDEV_GENERIC args->pitch = amdgpu_gem_align_pitch(adev, args->width, DIV_ROUND_UP(args->bpp, 8), 0); +#else + args->pitch = amdgpu_align_pitch(adev, args->width, + DIV_ROUND_UP(args->bpp, 8), 0); +#endif args->size = (u64)args->pitch * args->height; args->size = ALIGN(args->size, PAGE_SIZE); domain = amdgpu_bo_get_preferred_domain(adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index cac467bd718c0..53e0463bfc07a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -232,7 +232,7 @@ struct amdgpu_i2c_chan { }; -#ifndef HAVE_DRM_DEVICE_FB_HELPER +#ifndef AMDKCL_DRM_FBDEV_GENERIC struct amdgpu_fbdev; #endif @@ -315,7 +315,7 @@ struct amdgpu_framebuffer { uint64_t address; }; -#ifndef HAVE_DRM_DEVICE_FB_HELPER +#ifndef AMDKCL_DRM_FBDEV_GENERIC struct amdgpu_fbdev { struct drm_fb_helper helper; struct amdgpu_framebuffer rfb; @@ -346,7 +346,7 @@ struct amdgpu_mode_info { /* hardcoded DFP edid from BIOS */ const struct drm_edid *bios_hardcoded_edid; -#ifndef HAVE_DRM_DEVICE_FB_HELPER +#ifndef AMDKCL_DRM_FBDEV_GENERIC /* pointer to fbdev info structure */ struct amdgpu_fbdev *rfbdev; #endif @@ -722,7 +722,7 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode); -#ifndef HAVE_DRM_DEVICE_FB_HELPER +#ifndef AMDKCL_DRM_FBDEV_GENERIC /* fbdev layer */ int amdgpu_fbdev_init(struct amdgpu_device *adev); void amdgpu_fbdev_fini(struct amdgpu_device *adev); diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index fd7f828ca96fd..2d165e481704b 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -42,4 +42,10 @@ void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, #define drm_helper_mode_fill_fb_struct _kcl_drm_helper_mode_fill_fb_struct #endif +#if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) && \ + defined(HAVE_DRM_DEVICE_FB_HELPER) && \ + DRM_VERSION_CODE >= DRM_VERSION(5, 13, 0) +#define AMDKCL_DRM_FBDEV_GENERIC +#endif + #endif From adab3a2ce9659a381705328f0b9470f5b0ffda45 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 15 Nov 2021 14:52:04 +0800 Subject: [PATCH 0610/2653] drm/amdkfd: replace kgd_dev with amdgpu_device Modified definitions: - amdgpu_amdkfd_copy_mem_to_mem - amdgpu_amdkfd_send_close_event_drain_irq - amdgpu_amdkfd_gfx_off_ctrl - amdgpu_amdkfd_gpuvm_get_sg_table - amdgpu_amdkfd_gpuvm_export_ipc_obj - amdgpu_amdkfd_debug_mem_fence - amdgpu_amdkfd_rlc_spm_cntl - amdgpu_amdkfd_rlc_spm_acquire - amdgpu_amdkfd_rlc_spm_release - amdgpu_amdkfd_rlc_spm_set_rdptr - kgd_aldebaran_enable_debug_trap - kgd_aldebaran_disable_debug_trap - kgd_aldebaran_set_wave_launch_trap_override - kgd_aldebaran_set_wave_launch_mode - kgd_aldebaran_set_precise_mem_ops - kgd_gfx_v10_enable_debug_trap - kgd_gfx_v10_disable_debug_trap - kgd_gfx_v10_set_wave_launch_trap_override - kgd_gfx_v10_set_wave_launch_mode - kgd_gfx_v10_set_address_watch - kgd_gfx_v10_clear_address_watch - kgd_gfx_v10_set_precise_mem_ops - kgd_gfx_v10_get_iq_wait_times - kgd_gfx_v10_build_grace_period_packet_info - kgd_gfx_v9_enable_debug_trap - kgd_gfx_v9_disable_debug_trap - kgd_gfx_v9_set_wave_launch_trap_override - kgd_gfx_v9_set_wave_launch_mode - kgd_gfx_v9_set_address_watch - kgd_gfx_v9_clear_address_watch - kgd_gfx_v9_set_precise_mem_ops - kgd_gfx_v9_get_iq_wait_times - kgd_gfx_v9_build_grace_period_packet_info Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 15 +++++----- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 9 ++---- .../drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 12 +++----- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 6 ++-- drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 28 +++++++++---------- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 +- 8 files changed, 34 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 10935711ae95e..996685cf00dc4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -359,7 +359,7 @@ int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain); */ void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo); -int amdgpu_amdkfd_gpuvm_get_sg_table(struct kgd_dev *kgd, +int amdgpu_amdkfd_gpuvm_get_sg_table(struct amdgpu_device *adev, struct amdgpu_bo *bo, uint32_t flags, uint64_t offset, uint64_t size, struct device *dma_dev, enum dma_data_direction dir, @@ -368,7 +368,7 @@ void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, struct device *dma_dev, enum dma_data_direction dir, struct sg_table *sg); -int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, +int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev, struct dma_buf *dmabuf, struct kfd_ipc_obj *ipc_obj, uint64_t va, void *drm_priv, @@ -380,7 +380,7 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, uint64_t *mmap_offset); int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, struct dma_buf **dmabuf); -int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, +int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, struct kgd_mem *mem, struct kfd_ipc_obj **ipc_obj, uint32_t flags); @@ -442,12 +442,11 @@ void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) } #endif -void amdgpu_amdkfd_rlc_spm_cntl(struct kgd_dev *kgd, bool cntl); -int amdgpu_amdkfd_rlc_spm(struct kgd_dev *kgd, void *args); -int amdgpu_amdkfd_rlc_spm_acquire(struct kgd_dev *kgd, +void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, bool cntl); +int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm *vm, u64 gpu_addr, u32 size); -void amdgpu_amdkfd_rlc_spm_release(struct kgd_dev *kgd, struct amdgpu_vm *vm); -void amdgpu_amdkfd_rlc_spm_set_rdptr(struct kgd_dev *kgd, u32 rptr); +void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm *vm); +void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr); void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev); #if IS_ENABLED(CONFIG_HSA_AMD_SVM) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 189e612ea6a02..437dd6bd28e62 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2496,13 +2496,12 @@ static int get_sg_table_of_mmio_or_doorbel_bo(struct amdgpu_bo *bo, return 0; } -int amdgpu_amdkfd_gpuvm_get_sg_table(struct kgd_dev *kgd, +int amdgpu_amdkfd_gpuvm_get_sg_table(struct amdgpu_device *adev, struct amdgpu_bo *bo, uint32_t flags, uint64_t offset, uint64_t size, struct device *dma_dev, enum dma_data_direction dir, struct sg_table **ret_sg) { - struct amdgpu_device *adev = get_amdgpu_device(kgd); struct sg_table *sg = NULL; struct scatterlist *s; struct page **pages; @@ -2746,19 +2745,17 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, return ret; } -int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, +int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, struct kgd_mem *mem, struct kfd_ipc_obj **ipc_obj, uint32_t flags) { - struct amdgpu_device *adev = NULL; struct dma_buf *dmabuf; int r = 0; - if (!kgd || !vm || !mem) + if (!adev || !vm || !mem) return -EINVAL; - adev = get_amdgpu_device(kgd); mutex_lock(&mem->lock); if (mem->ipc_obj) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index eeaca9d1e02b9..1dd189536c764 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -25,9 +25,8 @@ #include #include "amdgpu_ids.h" -void amdgpu_amdkfd_rlc_spm_cntl(struct kgd_dev *kgd, bool cntl) +void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, bool cntl) { - struct amdgpu_device *adev = (struct amdgpu_device *)kgd; struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; spin_lock(&adev->gfx.kiq.ring_lock); @@ -40,9 +39,8 @@ void amdgpu_amdkfd_rlc_spm_cntl(struct kgd_dev *kgd, bool cntl) spin_unlock(&adev->gfx.kiq.ring_lock); } -void amdgpu_amdkfd_rlc_spm_set_rdptr(struct kgd_dev *kgd, u32 rptr) +void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) { - struct amdgpu_device *adev = (struct amdgpu_device *)kgd; struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; spin_lock(&adev->gfx.kiq.ring_lock); @@ -52,9 +50,8 @@ void amdgpu_amdkfd_rlc_spm_set_rdptr(struct kgd_dev *kgd, u32 rptr) spin_unlock(&adev->gfx.kiq.ring_lock); } -int amdgpu_amdkfd_rlc_spm_acquire(struct kgd_dev *kgd, struct amdgpu_vm *vm, u64 gpu_addr, u32 size) +int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm *vm, u64 gpu_addr, u32 size) { - struct amdgpu_device *adev = (struct amdgpu_device *)kgd; struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; int r; @@ -77,9 +74,8 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct kgd_dev *kgd, struct amdgpu_vm *vm, u64 return r; } -void amdgpu_amdkfd_rlc_spm_release(struct kgd_dev *kgd, struct amdgpu_vm *vm) +void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm *vm) { - struct amdgpu_device *adev = (struct amdgpu_device *)kgd; struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; /* stop spm stream and interrupt */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index b5d89265d3c2d..b7208b22ad883 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -136,7 +136,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, goto err_unlock; } - r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf, ipc_obj, + r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->adev, dmabuf, ipc_obj, va_addr, pdd->drm_priv, (struct kgd_mem **)&mem, &size, mmap_offset); @@ -157,7 +157,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, return 0; err_free: - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem, NULL); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem, pdd->drm_priv, NULL); err_unlock: mutex_unlock(&p->mutex); return r; @@ -252,7 +252,7 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, } mem = (struct kgd_mem *)kfd_bo->mem; - r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->kgd, pdd->drm_priv, mem, + r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->adev, pdd->drm_priv, mem, &ipc_obj, flags); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index f8c89ba5ff86b..09cf783e460d3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -320,7 +320,7 @@ static int amd_dma_map(struct sg_table *sg_head, void *client_context, /* Build sg_table for buffer being exported, including DMA mapping */ ret = amdgpu_amdkfd_gpuvm_get_sg_table( - mem_context->dev->kgd, mem_context->bo, mem_context->flags, + mem_context->dev->adev, mem_context->bo, mem_context->flags, mem_context->offset, mem_context->size, dma_device, DMA_BIDIRECTIONAL, &sg_table_tmp); if (ret) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index d4cc101062152..978236c4689c4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1016,7 +1016,7 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) if (!peer_pdd->drm_priv) continue; amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( - peer_pdd->dev->kgd, buf_obj->mem, peer_pdd->drm_priv); + peer_pdd->dev->adev, buf_obj->mem, peer_pdd->drm_priv); } run_rdma_free_callback(buf_obj); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index ceabdb3680a64..b1fc5ace4015d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -147,7 +147,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) } exit: - amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->kgd, spm->ring_rptr); + amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->adev, spm->ring_rptr); return ret; } @@ -176,7 +176,7 @@ void kfd_spm_init_process_device(struct kfd_process_device *pdd) pdd->spm_cntr = NULL; } -static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) +static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) { int ret = 0; @@ -200,7 +200,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) pdd->spm_cntr->ring_mask = pdd->spm_cntr->ring_size - 1; pdd->spm_cntr->has_user_buf = false; - ret = amdgpu_amdkfd_alloc_gtt_mem(kgd, + ret = amdgpu_amdkfd_alloc_gtt_mem(adev, pdd->spm_cntr->ring_size, &pdd->spm_cntr->spm_obj, &pdd->spm_cntr->gpu_addr, (void *)&pdd->spm_cntr->cpu_addr, false, false); @@ -208,7 +208,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) if (ret) goto alloc_gtt_mem_failure; - ret = amdgpu_amdkfd_rlc_spm_acquire(kgd, pdd->drm_priv, + ret = amdgpu_amdkfd_rlc_spm_acquire(adev, pdd->drm_priv, pdd->spm_cntr->gpu_addr, pdd->spm_cntr->ring_size); /* @@ -230,7 +230,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) goto out; acquire_spm_failure: - amdgpu_amdkfd_free_gtt_mem(kgd, pdd->spm_cntr->spm_obj); + amdgpu_amdkfd_free_gtt_mem(adev, pdd->spm_cntr->spm_obj); alloc_gtt_mem_failure: mutex_lock(&pdd->spm_mutex); @@ -242,7 +242,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) return ret; } -static int kfd_release_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) +static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) { unsigned long flags; @@ -259,8 +259,8 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) flush_work(&pdd->spm_work); wake_up_all(&pdd->spm_cntr->spm_buf_wq); - amdgpu_amdkfd_rlc_spm_release(kgd, pdd->drm_priv); - amdgpu_amdkfd_free_gtt_mem(kgd, pdd->spm_cntr->spm_obj); + amdgpu_amdkfd_rlc_spm_release(adev, pdd->drm_priv); + amdgpu_amdkfd_free_gtt_mem(adev, pdd->spm_cntr->spm_obj); spin_lock_irqsave(&pdd->spm_irq_lock, flags); kfree(pdd->spm_cntr); @@ -330,7 +330,7 @@ static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm, return ret; } -static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct kgd_dev *kgd, void *data) +static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_device *adev, void *data) { struct kfd_ioctl_spm_args *user_spm_data; struct kfd_spm_cntr *spm; @@ -378,7 +378,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct kgd_dev *k /* Start SPM */ if (spm->is_spm_started == false) { - amdgpu_amdkfd_rlc_spm_cntl(kgd, 1); + amdgpu_amdkfd_rlc_spm_cntl(adev, 1); spin_lock_irqsave(&pdd->spm_irq_lock, flags); spm->is_spm_started = true; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); @@ -389,7 +389,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct kgd_dev *k schedule_work(&pdd->spm_work); } } else { - amdgpu_amdkfd_rlc_spm_cntl(kgd, 0); + amdgpu_amdkfd_rlc_spm_cntl(adev, 0); spin_lock_irqsave(&pdd->spm_irq_lock, flags); spm->is_spm_started = false; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); @@ -419,13 +419,13 @@ int kfd_rlc_spm(struct kfd_process *p, void *data) switch (args->op) { case KFD_IOCTL_SPM_OP_ACQUIRE: dev->spm_pasid = p->pasid; - return kfd_acquire_spm(pdd, dev->kgd); + return kfd_acquire_spm(pdd, dev->adev); case KFD_IOCTL_SPM_OP_RELEASE: - return kfd_release_spm(pdd, dev->kgd); + return kfd_release_spm(pdd, dev->adev); case KFD_IOCTL_SPM_OP_SET_DEST_BUF: - return kfd_set_dest_buffer(pdd, dev->kgd, data); + return kfd_set_dest_buffer(pdd, dev->adev, data); default: return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 1b94b813f18bc..310a75f5f921e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -314,7 +314,7 @@ static ssize_t mem_show(struct kobject *kobj, struct attribute *attr, if (mem->gpu) { if (kfd_devcgroup_check_permission(mem->gpu)) return -EPERM; - used_mem = amdgpu_amdkfd_get_vram_usage(mem->gpu->kgd); + used_mem = amdgpu_amdkfd_get_vram_usage(mem->gpu->adev); return sysfs_show_64bit_val(buffer, offs, used_mem); } /* TODO: Report APU/CPU-allocated memory; For now return 0 */ From 91226f117a05a3fe547e6ae4db4dbe2876a7483b Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Thu, 25 Nov 2021 22:25:12 +0800 Subject: [PATCH 0611/2653] drm/amdgpu: correct RLC_SPM_INT_CNTL register address should count on gc base address Signed-off-by: Hawking Zhang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index aa3e258d9afb0..eb6d5b4278b94 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -7203,10 +7203,10 @@ static int gfx_v9_0_spm_set_interrupt_state(struct amdgpu_device *adev, { switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - WREG32(mmRLC_SPM_INT_CNTL, 0); + WREG32_SOC15(GC, 0, mmRLC_SPM_INT_CNTL, 0); break; case AMDGPU_IRQ_STATE_ENABLE: - WREG32(mmRLC_SPM_INT_CNTL, 1); + WREG32_SOC15(GC, 0, mmRLC_SPM_INT_CNTL, 1); break; default: break; From cb40a94ced047f698ddc5f7d0ceced6924520e73 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 17 Nov 2021 19:44:55 -0500 Subject: [PATCH 0612/2653] drm/amdkfd: Fix amdgpu_read_lock lockdep errors The amdgpu_read_lock must be taken inside the p->mutex to avoid circular lock dependencies between these two locks. Move locking from IPC and dmabuf import ioctls into kfd_import_dmabuf_create_kfd_bo to satisfy this constraint. Signed-off-by: Felix Kuehling Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index b7208b22ad883..c1f5f7dc6c5d7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -129,11 +129,14 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, return -EINVAL; mutex_lock(&p->mutex); + r = amdgpu_read_lock(dev->ddev, true); + if (r) + goto err_unlock; pdd = kfd_bind_process_to_device(dev, p); if (IS_ERR(pdd)) { r = PTR_ERR(pdd); - goto err_unlock; + goto err_read_unlock; } r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->adev, dmabuf, ipc_obj, @@ -141,7 +144,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, (struct kgd_mem **)&mem, &size, mmap_offset); if (r) - goto err_unlock; + goto err_read_unlock; idr_handle = kfd_process_device_create_obj_handle(pdd, mem, va_addr, size, 0, 0); @@ -150,6 +153,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, goto err_free; } + amdgpu_read_unlock(dev->ddev); mutex_unlock(&p->mutex); *handle = MAKE_HANDLE(gpu_id, idr_handle); @@ -158,6 +162,8 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, err_free: amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem, pdd->drm_priv, NULL); +err_read_unlock: + amdgpu_read_unlock(dev->ddev); err_unlock: mutex_unlock(&p->mutex); return r; From 0f0c31f91c9c943d3b4fca38d7dc659b1b6a5466 Mon Sep 17 00:00:00 2001 From: Emily Deng Date: Tue, 30 Nov 2021 11:58:39 +0800 Subject: [PATCH 0613/2653] amd/amdgpu: Fix build issue on arm platform On arm platform, couldn't support float build. And for container it doesn't need dcn. So directly remove dcn parts. Signed-off-by: Emily Deng Reviewed-by: Flora Cui Change-Id: Ic01a003271a9481c4e04fb1eb15fbc1162d6ccc6 --- drivers/gpu/drm/amd/dkms/Makefile | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index b9f423b84ddaf..340258b04f0aa 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -149,7 +149,9 @@ export CONFIG_DRM_AMDGPU_CIK=y export CONFIG_DRM_AMDGPU_SI=y export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y +ifndef CONFIG_ARM64 export CONFIG_DRM_AMD_DC_DCN1_0=y +endif subdir-ccflags-y += -DCONFIG_HSA_AMD subdir-ccflags-y += -DCONFIG_DRM_TTM_DMA_PAGE_POOL @@ -157,7 +159,9 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC +ifndef CONFIG_ARM64 subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 +endif ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) ifdef CONFIG_DEVICE_PRIVATE @@ -173,11 +177,13 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP # older versions of GCC hanging during building/installing. Check # if the compiler is using core2 optimizations and only build DCN2/3 # if core2 isn't in the compiler flags +ifndef CONFIG_ARM64 ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) export CONFIG_DRM_AMD_DC_DCN2_x=y export CONFIG_DRM_AMD_DC_DCN3_x=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN2_x subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN3_x endif +endif obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ From 8adff909b8bdfdce4281006b252b390cc8a552da Mon Sep 17 00:00:00 2001 From: Jiange Zhao Date: Thu, 29 Jul 2021 13:36:19 +0800 Subject: [PATCH 0614/2653] amd/amdkcl - Make dkms package compile and run on arm64 4.19 kernel Resolve the compile error about access ok Signed-off-by: Jiange Zhao Signed-off-by: Emily Deng Reviewed-by: Flora Cui Change-Id: I703025483dd8e5fb30f5004162c3de19fe04b12c --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 12 ++++++------ drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 2 +- include/kcl/backport/kcl_uaccess_backport.h | 10 +++++----- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index f87c793860d4d..fe76ffb6da6bc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -203,7 +203,7 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, } if ((args->ring_base_address) && - (!access_ok((const void __user *) args->ring_base_address, + (!kcl_access_ok((const void __user *) args->ring_base_address, sizeof(uint64_t)))) { pr_err("Can't access ring base address\n"); return -EFAULT; @@ -219,27 +219,27 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, pr_debug("Size lower. clamped to KFD_MIN_QUEUE_RING_SIZE"); } - if (!access_ok((const void __user *) args->read_pointer_address, + if (!kcl_access_ok((const void __user *) args->read_pointer_address, sizeof(uint32_t))) { pr_err("Can't access read pointer\n"); return -EFAULT; } - if (!access_ok((const void __user *) args->write_pointer_address, + if (!kcl_access_ok((const void __user *) args->write_pointer_address, sizeof(uint32_t))) { pr_err("Can't access write pointer\n"); return -EFAULT; } if (args->eop_buffer_address && - !access_ok((const void __user *) args->eop_buffer_address, + !kcl_access_ok((const void __user *) args->eop_buffer_address, sizeof(uint32_t))) { pr_debug("Can't access eop buffer"); return -EFAULT; } if (args->ctx_save_restore_address && - !access_ok((const void __user *) args->ctx_save_restore_address, + !kcl_access_ok((const void __user *) args->ctx_save_restore_address, sizeof(uint32_t))) { pr_debug("Can't access ctx save restore buffer"); return -EFAULT; @@ -457,7 +457,7 @@ static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, } if ((args->ring_base_address) && - (!access_ok((const void __user *) args->ring_base_address, + (!kcl_access_ok((const void __user *) args->ring_base_address, sizeof(uint64_t)))) { pr_err("Can't access ring base address\n"); return -EFAULT; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c index a499449fcb068..3058f04393705 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c @@ -129,7 +129,7 @@ static ssize_t kfd_smi_ev_write(struct file *filep, const char __user *user, struct kfd_smi_client *client = filep->private_data; uint64_t events; - if (!access_ok(user, size) || size < sizeof(events)) + if (!kcl_access_ok(user, size) || size < sizeof(events)) return -EFAULT; if (copy_from_user(&events, user, sizeof(events))) return -EFAULT; diff --git a/include/kcl/backport/kcl_uaccess_backport.h b/include/kcl/backport/kcl_uaccess_backport.h index c7466949cad39..5e358c64a8fce 100644 --- a/include/kcl/backport/kcl_uaccess_backport.h +++ b/include/kcl/backport/kcl_uaccess_backport.h @@ -3,12 +3,12 @@ #define AMDKCL_UACCESS_BACKPORT_H #include -#if !defined(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS) -static inline int _kcl_access_ok(unsigned long addr, unsigned long size) +static inline int kcl_access_ok(unsigned long addr, unsigned long size) { +#if !defined(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS) return access_ok(VERIFY_WRITE, (addr), (size)); -} -#undef access_ok -#define access_ok _kcl_access_ok +#else + return access_ok((addr), (size)); #endif +} #endif From 902db5556ad747f458e56093c0672b48033ec5ea Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Fri, 12 Nov 2021 15:39:32 -0600 Subject: [PATCH 0615/2653] drm/amdgpu: Fix config macro HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER Logic determining status of HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER is incorrect. Code body should reference struct dma_buf_attach_ops. Rename macro as HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER Signed-off-by: Ramesh Errabolu Acked-by: Felix Kuehling Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 6 +++--- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 2 +- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 1b2c930244399..e1ed5a7104d8f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -271,7 +271,7 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); -#ifdef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER +#ifdef HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER if (!amdgpu_dmabuf_is_xgmi_accessible(attach_adev, bo) && pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0) attach->peer2peer = false; @@ -387,7 +387,7 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, struct ttm_operation_ctx ctx = { false, false }; unsigned int domains = AMDGPU_GEM_DOMAIN_GTT; -#ifdef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER +#ifdef HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM && attach->peer2peer) { bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; @@ -830,7 +830,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) } static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = { -#ifdef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER +#ifdef HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER .allow_peer2peer = true, #endif .move_notify = amdgpu_dma_buf_move_notify diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a7cc3bf23c054..a7bca453c6b00 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -960,6 +960,9 @@ /* struct dma_buf_ops->allow_peer2peer is available */ #define HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER 1 +/* struct dma_buf_attach_ops->allow_peer2peer is available */ +#define HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER 1 + /* struct dma_buf_ops->pin() is available */ #define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 index e402bf57f2ec6..5f773c28a1b9e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -10,7 +10,7 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ struct dma_buf_attach_ops *ptr = NULL; ptr->allow_peer2peer = false; ],[ - AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER, + AC_DEFINE(HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER, 1, [struct dma_buf_attach_ops->allow_peer2peer is available]) ],[ From 615b96d23e2033fae4abf36765bc2aa75ae295ef Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 3 Dec 2021 11:11:58 +0800 Subject: [PATCH 0616/2653] drm/amdkcl: fix dma-buf related check Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 6 ++---- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +-- drivers/gpu/drm/amd/dkms/config/config.h | 5 ++++- drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 9 ++++++++- 4 files changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index e1ed5a7104d8f..f3e6465bec2e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -134,8 +134,7 @@ __dma_resv_make_exclusive(struct dma_resv *obj) return -ENOMEM; } -#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ - !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +#if defined(HAVE_DMA_BUF_OPS_LEGACY) /** * amdgpu_dma_buf_map_attach - &dma_buf_ops.attach implementation * @dma_buf: Shared DMA buffer @@ -517,8 +516,7 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf, } const struct dma_buf_ops amdgpu_dmabuf_ops = { -#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ - !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +#if defined(HAVE_DMA_BUF_OPS_LEGACY) .attach = amdgpu_dma_buf_map_attach, .detach = amdgpu_dma_buf_map_detach, .map_dma_buf = drm_gem_map_dma_buf, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index b18e93593329b..fa8360f5bb14e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3183,8 +3183,7 @@ static struct drm_driver amdgpu_kms_driver = { #ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ .gem_prime_res_obj = amdgpu_gem_prime_res_obj, #endif -#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ - !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +#if defined(HAVE_DMA_BUF_OPS_LEGACY) .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a7bca453c6b00..7c15f6c11260b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -79,9 +79,12 @@ /* dev_pm_set_driver_flags() is available */ #define HAVE_DEV_PM_SET_DRIVER_FLAGS 1 -/* dma_buf dynamic_mapping is available */ +/* dma_buf->dynamic_mapping is available */ /* #undef HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING */ +/* dma_buf->dynamic_mapping is not available */ +/* #undef HAVE_DMA_BUF_OPS_LEGACY */ + /* dma_buf_unpin() is available */ #define HAVE_DMA_BUF_UNPIN 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 index 5f773c28a1b9e..d4f139e428849 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -13,6 +13,10 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ AC_DEFINE(HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER, 1, [struct dma_buf_attach_ops->allow_peer2peer is available]) + + AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_PIN, + 1, + [struct dma_buf_ops->pin() is available]) ],[ dnl # dnl # 4981cdb063e3 dma-buf: make move_notify mandatory if importer_ops are provided @@ -44,8 +48,11 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ dma_buf_ops->dynamic_mapping = true; ],[ AC_DEFINE(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING, 1, - [dma_buf dynamic_mapping is available]) + [dma_buf->dynamic_mapping is available]) ],[ + AC_DEFINE(HAVE_DMA_BUF_OPS_LEGACY, 1, + [dma_buf->dynamic_mapping is not available]) + AC_AMDGPU_DRM_GEM_MAP_ATTACH ]) ]) From 1112e2e8765d35b5a8c74314c0e2157c0f5494e2 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 3 Dec 2021 11:23:06 +0800 Subject: [PATCH 0617/2653] drm/amdkcl: drop test for dma_buf_unpin It's the same with test for dma_buf_pin Signed-off-by: Flora Cui Reviewed-by: Yuan Perry --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 6 ---- drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 | 34 -------------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 -- 4 files changed, 1 insertion(+), 43 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index cdf26f4df7fce..d799d4e4a4d06 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1049,7 +1049,7 @@ void amdgpu_bo_unpin(struct amdgpu_bo *bo) if (bo->tbo.pin_count) return; -#ifdef HAVE_DMA_BUF_UNPIN +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN if (drm_gem_is_imported(&bo->tbo.base)) dma_buf_unpin(bo->tbo.base.import_attach); #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7c15f6c11260b..712202125631d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -85,9 +85,6 @@ /* dma_buf->dynamic_mapping is not available */ /* #undef HAVE_DMA_BUF_OPS_LEGACY */ -/* dma_buf_unpin() is available */ -#define HAVE_DMA_BUF_UNPIN 1 - /* whether dma_fence_get_stub exits */ #define HAVE_DMA_FENCE_GET_STUB 1 @@ -969,9 +966,6 @@ /* struct dma_buf_ops->pin() is available */ #define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 -/* struct dma_buf_ops->unpin() is available */ -#define HAVE_STRUCT_DMA_BUF_OPS_UNPIN 1 - /* struct drm_connector_state->duplicated is available */ #define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 deleted file mode 100644 index 4c07a856211f9..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 +++ /dev/null @@ -1,34 +0,0 @@ -dnl # -dnl # v5.6-rc2-335-gbb42df4662a4 -dnl # dma-buf: add dynamic DMA-buf handling v15 -dnl # -AC_DEFUN([AC_AMDGPU_DMA_BUF_UNPIN], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - dma_buf_unpin(NULL); - ],[ - AC_DEFINE(HAVE_DMA_BUF_UNPIN, 1, - [dma_buf_unpin() is available]) - ]) - ]) -]) - -AC_DEFUN([AC_AMDGPU_STRUCT_DMA_BUF_OPS_UNPIN], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - struct dma_buf_ops *ptr = NULL; - ptr->unpin(NULL); - ],[ - AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_UNPIN, 1, - [struct dma_buf_ops->unpin() is available]) - ]) - ]) -]) - - - - diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 52a97889a6ede..2e50038ded496 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -162,8 +162,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY - AC_AMDGPU_DMA_BUF_UNPIN - AC_AMDGPU_STRUCT_DMA_BUF_OPS_UNPIN AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_DEV_ENTER From ccac449be7d95da0099447bec161c708fc04d0a0 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 6 Dec 2021 04:02:25 -0500 Subject: [PATCH 0618/2653] drm/amdkfd: fix build error by replacing asic_name with asic type The patch will fix the build error which was caused by below commit: f31e07ea10f1 amdkfd: replace asic_family with asic_type v5.13-2961-gf31e07ea10f1 Signed-off-by: Perry Yuan Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 8 ++++---- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 6063d6b33805d..e4a2da0d814dd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -593,12 +593,12 @@ static int kfd_gws_init(struct kfd_node *node) node->adev->gds.gws_size, &node->gws); } - if ((kfd->device_info->asic_family == CHIP_VEGA10 + if ((kfd->adev->asic_type == CHIP_VEGA10 && kfd->mec2_fw_version < 0x81b6) - || (kfd->device_info->asic_family >= CHIP_VEGA12 - && kfd->device_info->asic_family <= CHIP_RAVEN + || (kfd->adev->asic_type >= CHIP_VEGA12 + && kfd->adev->asic_type <= CHIP_RAVEN && kfd->mec2_fw_version < 0x1b6) - || (kfd->device_info->asic_family == CHIP_ARCTURUS + || (kfd->adev->asic_type == CHIP_ARCTURUS && kfd->mec2_fw_version < 0x30)) kfd->gws_debug_workaround = true; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 310a75f5f921e..949ef727df8f5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1279,7 +1279,7 @@ static void kfd_set_iolink_no_atomics(struct kfd_topology_device *dev, /* checkout source dev has atomics support on root. */ if (dev->gpu && (!dev->gpu->pci_atomic_requested || - dev->gpu->device_info->asic_family == + dev->gpu->adev->asic_type == CHIP_HAWAII)) { link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT | CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT; From 7c141242d87013e7c7c318d16e37c188e0897b64 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 7 Dec 2021 21:28:21 -0500 Subject: [PATCH 0619/2653] drm/amdkfd: fix coding style problem The patch fix the code format for the below patch. b751ff5666 drm/amdkfd: fix build error by replacing asic_name with asic type Signed-off-by: Perry Yuan Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 949ef727df8f5..3696065e84c0d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1279,8 +1279,7 @@ static void kfd_set_iolink_no_atomics(struct kfd_topology_device *dev, /* checkout source dev has atomics support on root. */ if (dev->gpu && (!dev->gpu->pci_atomic_requested || - dev->gpu->adev->asic_type == - CHIP_HAWAII)) { + dev->gpu->adev->asic_type == CHIP_HAWAII)) { link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT | CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT; return; From 423a8433f5fc1b280e44fab7711985746a48d7be Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Wed, 8 Dec 2021 04:56:12 -0500 Subject: [PATCH 0620/2653] drm/amdkcl: fix build error by adding drm_display_info.is_hdmi check The build failure caused by below commit, the patch will check if the is_hdmi is available on the current kernel. dfbe9bf067 drm/amdgpu: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi v5.13-3121-gdfbe9bf067a2 Signed-off-by: Perry Yuan Reviewed-by: Flora Cui --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 24 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c | 8 +++++++ .../gpu/drm/amd/amdgpu/atombios_encoders.c | 12 ++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 5 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../m4/drm-connector-display-info-hdmi.m4 | 18 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 8 files changed, 75 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-display-info-hdmi.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 3b162ca7b507d..a59092dcadc14 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -116,7 +116,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) case DRM_MODE_CONNECTOR_DVII: case DRM_MODE_CONNECTOR_HDMIB: if (amdgpu_connector->use_digital) { +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif if (connector->display_info.bpc) bpc = connector->display_info.bpc; } @@ -124,7 +128,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) break; case DRM_MODE_CONNECTOR_DVID: case DRM_MODE_CONNECTOR_HDMIA: +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif if (connector->display_info.bpc) bpc = connector->display_info.bpc; } @@ -133,7 +141,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) dig_connector = amdgpu_connector->con_priv; if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) connector->display_info.is_hdmi) { +#else + drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif if (connector->display_info.bpc) bpc = connector->display_info.bpc; } @@ -157,7 +169,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) break; } +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif /* * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at @@ -1245,7 +1261,11 @@ static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { return MODE_OK; +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) } else if (connector->display_info.is_hdmi) { +#else + } else if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif /* HDMI 1.3+ supports max clock of 340 Mhz */ if (mode->clock > 340000) return MODE_CLOCK_HIGH; @@ -1548,7 +1568,11 @@ static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { return amdgpu_atombios_dp_mode_valid_helper(connector, mode); } else { +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif /* HDMI 1.3+ supports max clock of 340 Mhz */ if (mode->clock > 340000) return MODE_CLOCK_HIGH; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 85b171befd2ac..6fc1cfef92962 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1750,7 +1750,11 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) connector && connector->display_info.is_hdmi && +#else + drm_detect_hdmi_monitor(to_amdgpu_connector(connector)->edid) && +#endif amdgpu_display_is_hdtv_mode(mode)))) { if (amdgpu_encoder->underscan_hborder != 0) amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c index 54913ae5148b6..ccd095286b0b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c @@ -252,7 +252,11 @@ bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, case DRM_MODE_CONNECTOR_HDMIB: if (amdgpu_connector->use_digital) { /* HDMI 1.3 supports up to 340 Mhz over single link */ +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif if (pixel_clock > 340000) return true; else @@ -274,7 +278,11 @@ bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, return false; else { /* HDMI 1.3 supports up to 340 Mhz over single link */ +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif if (pixel_clock > 340000) return true; else diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index a51f3414b65dd..99bc6a0066e20 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -466,7 +466,11 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) if (amdgpu_connector->use_digital && (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE)) return ATOM_ENCODER_MODE_HDMI; +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) else if (connector->display_info.is_hdmi && +#else + else if (drm_detect_hdmi_monitor(amdgpu_connector->edid) && +#endif (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO)) return ATOM_ENCODER_MODE_HDMI; else if (amdgpu_connector->use_digital) @@ -485,7 +489,11 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) if (amdgpu_audio != 0) { if (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE) return ATOM_ENCODER_MODE_HDMI; +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) else if (connector->display_info.is_hdmi && +#else + else if (drm_detect_hdmi_monitor(amdgpu_connector->edid) && +#endif (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO)) return ATOM_ENCODER_MODE_HDMI; else @@ -503,7 +511,11 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) } else if (amdgpu_audio != 0) { if (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE) return ATOM_ENCODER_MODE_HDMI; +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) else if (connector->display_info.is_hdmi && +#else + else if (drm_detect_hdmi_monitor(amdgpu_connector->edid) && +#endif (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO)) return ATOM_ENCODER_MODE_HDMI; else diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 2f51524bbc796..be17caad18ca1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -135,7 +135,12 @@ enum dc_edid_status dm_helpers_parse_edid_caps( edid_caps->display_name, AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) edid_caps->edid_hdmi = connector->display_info.is_hdmi; +#else + edid_caps->edid_hdmi = drm_detect_hdmi_monitor( + (struct edid *) edid->raw_edid); +#endif apply_edid_quirks(dev, edid_buf, edid_caps); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 712202125631d..3543aa7d3a959 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -293,6 +293,9 @@ /* struct drm_display_info has monitor_range member */ #define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 +/* display_info->is_hdmi is available */ +#define HAVE_DRM_DISPLAY_INFO_IS_HDMI 1 + /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-display-info-hdmi.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-display-info-hdmi.m4 new file mode 100644 index 0000000000000..7c3454c843d50 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-display-info-hdmi.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # dfbe9bf0 introduce this change +dnl # drm/amdgpu: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi +dnl # v5.13-3121-gdfbe9bf067a2 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_display_info *display_info = NULL; + display_info->is_hdmi = 0; + ], [ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_IS_HDMI, 1, + [display_info->is_hdmi is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2e50038ded496..be4b0e4be0faf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -176,6 +176,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEVICE_FB_HELPER AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS + AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 0483322af4947e941574905a17da337738b23c88 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Wed, 8 Dec 2021 10:45:57 -0500 Subject: [PATCH 0621/2653] drm/amdkcl: fix build error of debugfs entry dp_set_mst_en_for_sst_ops wrap the dp_set_mst_en_for_sst_ops debug entry code, the build error was caused by below commit : ad9601f002 drm/amd/display: Add Debugfs Entry to Force in SST Sequence v5.13-3122-gad9601f00296 Signed-off-by: Perry Yuan Reviewed-by: Shi, Leslie --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index ee87ae3ee26f2..70bdf6164986a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -4087,9 +4087,10 @@ static int dp_force_sst_get(void *data, u64 *val) return 0; } + +#if defined(DEFINE_DEBUGFS_ATTRIBUTE) DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, dp_force_sst_set, "%llu\n"); - /* * Force DP2 sequence without VESA certified cable. * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id @@ -4113,6 +4114,7 @@ static int dp_ignore_cable_id_get(void *data, u64 *val) } DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get, dp_ignore_cable_id_set, "%llu\n"); +#endif /* * Sets the DC visual confirm debug option from the given string. @@ -4265,12 +4267,12 @@ void dtn_debugfs_init(struct amdgpu_device *adev) adev, &capabilities_fops); debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, &dtn_log_fops); + +#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, &dp_set_mst_en_for_sst_ops); debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, &dp_ignore_cable_id_ops); - -#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, &visual_confirm_fops); From 1060306e67a2e296abb79a34d74da2e2ca46269d Mon Sep 17 00:00:00 2001 From: Xiaogang Chen Date: Mon, 13 Dec 2021 16:28:57 -0600 Subject: [PATCH 0622/2653] drm/amdkfd: explicitly create/destroy queue attributes under /sys When application is about finish it destroys queues it has created by an ioctl. Driver deletes queue entry(/sys/class/kfd/kfd/proc/pid/queues/queueid/) which is directory including this queue all attributes. Low level kernel code deletes all attributes under this directory. The lock from kernel is on queue entry, not its attributes. At meantime another user space application can read the attributes. There is possibility that the application can hold/read the attributes while kernel is deleting the queue entry, cause the application have invalid memory access, then killed by kernel. Driver changes: explicitly create/destroy each attribute for each queue, let kernel put lock on each attribute too. Signed-off-by: Xiaogang Chen Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 +++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 10 ++++++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 2b9697ad0b077..162412041d6f0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -641,6 +641,9 @@ struct queue { /* procfs */ struct kobject kobj; + struct attribute attr_guid; + struct attribute attr_size; + struct attribute attr_type; void *gang_ctx_bo; uint64_t gang_ctx_gpu_addr; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 978236c4689c4..cfef0f7e30a6a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -88,6 +88,8 @@ static void evict_process_worker(struct work_struct *work); static void restore_process_worker(struct work_struct *work); static void kfd_process_device_destroy_cwsr_dgpu(struct kfd_process_device *pdd); +static void kfd_sysfs_create_file(struct kobject *kobj, struct attribute *attr, + char *name); struct kfd_procfs_tree { struct kobject *kobj; @@ -553,6 +555,10 @@ int kfd_procfs_add_queue(struct queue *q) return ret; } + kfd_sysfs_create_file(&q->kobj, &q->attr_guid, "guid"); + kfd_sysfs_create_file(&q->kobj, &q->attr_size, "size"); + kfd_sysfs_create_file(&q->kobj, &q->attr_type, "type"); + return 0; } @@ -697,6 +703,10 @@ void kfd_procfs_del_queue(struct queue *q) if (!q) return; + sysfs_remove_file(&q->kobj, &q->attr_guid); + sysfs_remove_file(&q->kobj, &q->attr_size); + sysfs_remove_file(&q->kobj, &q->attr_type); + kobject_del(&q->kobj); kobject_put(&q->kobj); } From 2b8ba68375a179b1a251c6a19675a12cc97ba646 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 13 Dec 2021 03:34:27 -0500 Subject: [PATCH 0623/2653] drm/amdkcl: define macro of HDMI FRL feature for legacy os * Add some micro definition missing when building on ubuntu 5.8 kernel version * wrap DSC code with DSC support micro 8808f3ffb14 drm/amd/display: Add DP-HDMI FRL PCON Support in DC v5.13-3064-g8808f3ffb14d Signed-off-by: Perry Yuan Reviewed-by: Leslie Shi --- include/kcl/kcl_drm_dp_helper.h | 54 +++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 7fb0da12e569b..d92383908edc8 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -207,4 +207,58 @@ enum drm_dp_phy { #endif +/* + * v5.10-rc2-482-gce32a6239de6 + * drm/dp_helper: Add Helpers for FRL Link Training support for DP-HDMI2.1 PCON + */ +#ifndef DP_PCON_HDMI_POST_FRL_STATUS + +/* PCON CONFIGURE-1 FRL FOR HDMI SINK */ +#define DP_PCON_HDMI_LINK_CONFIG_1 0x305A +# define DP_PCON_ENABLE_MAX_FRL_BW (7 << 0) +# define DP_PCON_ENABLE_MAX_BW_0GBPS 0 +# define DP_PCON_ENABLE_MAX_BW_9GBPS 1 +# define DP_PCON_ENABLE_MAX_BW_18GBPS 2 +# define DP_PCON_ENABLE_MAX_BW_24GBPS 3 +# define DP_PCON_ENABLE_MAX_BW_32GBPS 4 +# define DP_PCON_ENABLE_MAX_BW_40GBPS 5 +# define DP_PCON_ENABLE_MAX_BW_48GBPS 6 +# define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3) +# define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4) +# define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4) +# define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5) +# define DP_PCON_ENABLE_HPD_READY (1 << 6) +# define DP_PCON_ENABLE_HDMI_LINK (1 << 7) + +/* PCON CONFIGURE-2 FRL FOR HDMI SINK */ +#define DP_PCON_HDMI_LINK_CONFIG_2 0x305B +# define DP_PCON_MAX_LINK_BW_MASK (0x3F << 0) +# define DP_PCON_FRL_BW_MASK_9GBPS (1 << 0) +# define DP_PCON_FRL_BW_MASK_18GBPS (1 << 1) +# define DP_PCON_FRL_BW_MASK_24GBPS (1 << 2) +# define DP_PCON_FRL_BW_MASK_32GBPS (1 << 3) +# define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4) +# define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5) +# define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6) +# define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6) + +/* PCON HDMI LINK STATUS */ +#define DP_PCON_HDMI_TX_LINK_STATUS 0x303B +# define DP_PCON_HDMI_TX_LINK_ACTIVE (1 << 0) +# define DP_PCON_FRL_READY (1 << 1) + +/* PCON HDMI POST FRL STATUS */ +#define DP_PCON_HDMI_POST_FRL_STATUS 0x3036 +# define DP_PCON_HDMI_LINK_MODE (1 << 0) +# define DP_PCON_HDMI_MODE_TMDS 0 +# define DP_PCON_HDMI_MODE_FRL 1 +# define DP_PCON_HDMI_FRL_TRAINED_BW (0x3F << 1) +# define DP_PCON_FRL_TRAINED_BW_9GBPS (1 << 1) +# define DP_PCON_FRL_TRAINED_BW_18GBPS (1 << 2) +# define DP_PCON_FRL_TRAINED_BW_24GBPS (1 << 3) +# define DP_PCON_FRL_TRAINED_BW_32GBPS (1 << 4) +# define DP_PCON_FRL_TRAINED_BW_40GBPS (1 << 5) +# define DP_PCON_FRL_TRAINED_BW_48GBPS (1 << 6) +#endif + #endif /* _KCL_DRM_DP_HELPER_H_ */ From 44c1a62c770bf3d3ffce1aca63e8743024f7fe90 Mon Sep 17 00:00:00 2001 From: Fangzhi Zuo Date: Fri, 10 Dec 2021 21:31:38 -0500 Subject: [PATCH 0624/2653] drm/amd/display: Fix Compile Error for DCE Guard the new debugfs entry to DCN only Follow-up fix for: drm/amd/display: Add Debugfs Entry to Force in SST Sequence Signed-off-by: Fangzhi Zuo Reviewed-by: Nicholas Choi Acked-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 70bdf6164986a..db4760745614c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -4091,6 +4091,7 @@ static int dp_force_sst_get(void *data, u64 *val) #if defined(DEFINE_DEBUGFS_ATTRIBUTE) DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, dp_force_sst_set, "%llu\n"); + /* * Force DP2 sequence without VESA certified cable. * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id From dac403f2676d5423daf4a265aad6eb2b95ba77f9 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 14 Dec 2021 00:22:48 -0500 Subject: [PATCH 0625/2653] drm/amdkcl: add definition of DP_DPCD_REV_XX to kcl_drm_dp_helper The patch add some missing micro definition of DP_DPCD_REV_XX to drm kcl header kcl_drm_dp_helper.h to resolve some dependency case. original commit: 0597017cd1 drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper v4.16-rc7-1860-g0597017cd18d Signed-off-by: Perry Yuan Reviewed-by: Leslie Shi --- include/kcl/kcl_drm_dp_helper.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index d92383908edc8..ec52d89063426 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -260,5 +260,20 @@ enum drm_dp_phy { # define DP_PCON_FRL_TRAINED_BW_40GBPS (1 << 5) # define DP_PCON_FRL_TRAINED_BW_48GBPS (1 << 6) #endif +/* + * v4.16-rc7-1860-g0597017cd18d + * drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper + */ + +/* DPCD Field Address Mapping */ + +/* Receiver Capability */ +#ifndef DP_DPCD_REV_14 +# define DP_DPCD_REV_10 0x10 +# define DP_DPCD_REV_11 0x11 +# define DP_DPCD_REV_12 0x12 +# define DP_DPCD_REV_13 0x13 +# define DP_DPCD_REV_14 0x14 +#endif #endif /* _KCL_DRM_DP_HELPER_H_ */ From 69ad1f2025b281351da9a14d5ce1ee46ce75f523 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Wed, 15 Dec 2021 03:25:57 -0500 Subject: [PATCH 0626/2653] drm/amdkcl: fake bitmap_alloc(), bitmap_zalloc() and bitmap_free() This patch will fix the below patch building dependency issue on some old kernels version. 1a48fbd4 drm/amdkfd: Use bitmap_zalloc() when applicable v5.13-3049-g1a48fbd4ce19 Signed-off-by: Perry Yuan Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c | 48 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../drm/amd/dkms/m4/drm-bitmap-functions.m4 | 12 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_bitmap.h | 42 ++++++++++++++++ 7 files changed, 108 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 create mode 100644 include/kcl/kcl_bitmap.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index ef7887752b276..5352465a012f4 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,7 +12,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ - kcl_drm_drv.o kcl_drm_simple_kms_helper.o + kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c b/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c new file mode 100644 index 0000000000000..106a0960013d2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c @@ -0,0 +1,48 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef HAVE_BITMAP_FUNCS + +#include +#include +#include +#include + +unsigned long *bitmap_alloc(unsigned int nbits, gfp_t flags) +{ + return kmalloc_array(BITS_TO_LONGS(nbits), sizeof(unsigned long), + flags); +} +EXPORT_SYMBOL(bitmap_alloc); + +unsigned long *bitmap_zalloc(unsigned int nbits, gfp_t flags) +{ + return bitmap_alloc(nbits, flags | __GFP_ZERO); +} +EXPORT_SYMBOL(bitmap_zalloc); + +void bitmap_free(const unsigned long *bitmap) +{ + kfree(bitmap); +} +EXPORT_SYMBOL(bitmap_free); +#endif /* HAVE_BITMAP_FUNCS */ + diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 4ede69680225a..c26be24e7c01b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -80,5 +80,6 @@ #include "kcl/kcl_drm_aperture.h" #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3543aa7d3a959..6db9845cfabed 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1108,6 +1108,9 @@ /* zone_managed_pages() is available */ #define HAVE_ZONE_MANAGED_PAGES 1 +/* bitmap_free() is available */ +#define HAVE_BITMAP_FUNCS 1 + /* __drm_atomic_helper_connector_destroy_state() wants 1 arg */ #define HAVE___DRM_ATOMIC_HELPER_CONNECTOR_DESTROY_STATE_P 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 new file mode 100644 index 0000000000000..542826aa5e405 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 @@ -0,0 +1,12 @@ +dnl # +dnl # commit c42b65e363ce introduce this change +dnl # v4.17-3-gc42b65e363ce +dnl # bitmap: Add bitmap_alloc(), bitmap_zalloc() and bitmap_free() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_BITMAP_FUNCS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([bitmap_free], [linux/bitmap.h], [ + AC_DEFINE(HAVE_BITMAP_FUNCS, 1, [bitmap_free() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index be4b0e4be0faf..c3d8d75ebc40c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -177,6 +177,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI + AC_AMDGPU_DRM_BITMAP_FUNCS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_bitmap.h b/include/kcl/kcl_bitmap.h new file mode 100644 index 0000000000000..5eb728c542ef3 --- /dev/null +++ b/include/kcl/kcl_bitmap.h @@ -0,0 +1,42 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef KCL_BITMAP_H +#define KCL_BITMAP_H + +#ifndef HAVE_BITMAP_FUNCS +/* Copied from include/linux/bitmap.h*/ + +/* + * v4.17-3-gc42b65e363ce + * bitmap: Add bitmap_alloc(), bitmap_zalloc() and bitmap_free() + */ + +/* + * Allocation and deallocation of bitmap. + * Provided in lib/bitmap.c to avoid circular dependency. + */ +unsigned long *bitmap_alloc(unsigned int nbits, gfp_t flags); +unsigned long *bitmap_zalloc(unsigned int nbits, gfp_t flags); +void bitmap_free(const unsigned long *bitmap); +#endif /* HAVE_BITMAP_FUNCS */ + +#endif /* KCL_BITMAP_H */ From cdb41b7c04df6070bf74baa360dc5d0e6abcda88 Mon Sep 17 00:00:00 2001 From: Jeremy Newton Date: Fri, 17 Dec 2021 10:42:35 -0500 Subject: [PATCH 0627/2653] drm/amdkcl: Remove REMAKE_INITRD from dkms This is deprecated and causes issues during installation of the amdgpu-dkms package on RHEL. For manual testing, please use dracut manually to regenerate initrd. Fixes SWDEV-315476 SWDEV-314875 Signed-off-by: Jeremy Newton Change-Id: If2ab6bf7d00aa2689ffe543134e1291b0b95f5da --- drivers/gpu/drm/amd/dkms/dkms.conf | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 7a6075f32cb5a..146f1b4db6148 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -1,7 +1,6 @@ PACKAGE_NAME="amdgpu" PACKAGE_VERSION="1.0" AUTOINSTALL="yes" -REMAKE_INITRD="yes" PRE_BUILD="amd/dkms/pre-build.sh $kernelver" # not work with RHEL DKMS From e5d06a2f8626544f3196263c48fea16c6cdd10b4 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 20 Dec 2021 22:44:06 -0500 Subject: [PATCH 0628/2653] drm/amdkcl: wrap drm_edid_get_monitor_name with macro HAVE_DRM_EDID_GET_MONITOR_NAME This patch will check if the drm_edid_get_monitor_name exist in the some old kernel to avoid build dependency failure. b5f640ae7a0 drm/amdgpu: use drm_edid_get_monitor_name() instead of duplicating the code v5.13-3120-gb5f640ae7a0a Signed-off-by: Perry Yuan Reviewed-by: Leslie Shi --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 21 ++++++++++++++++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-edid-get-monitor-name.m4 | 17 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 41 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index be17caad18ca1..9667312bb9513 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -114,6 +114,9 @@ enum dc_edid_status dm_helpers_parse_edid_caps( int sadb_count = -1; int i = 0; uint8_t *sadb = NULL; +#if !defined(HAVE_DRM_EDID_GET_MONITOR_NAME) + int j = 0; +#endif enum dc_edid_status result = EDID_OK; @@ -130,10 +133,26 @@ enum dc_edid_status dm_helpers_parse_edid_caps( edid_caps->serial_number = edid_buf->serial; edid_caps->manufacture_week = edid_buf->mfg_week; edid_caps->manufacture_year = edid_buf->mfg_year; - +#if defined(HAVE_DRM_EDID_GET_MONITOR_NAME) drm_edid_get_monitor_name(edid_buf, edid_caps->display_name, AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); +#else + /* One of the four detailed_timings stores the monitor name. It's + * stored in an array of length 13. */ + for (i = 0; i < 4; i++) { + if (edid_buf->detailed_timings[i].data.other_data.type == 0xfc) { + while (j < 13 && edid_buf->detailed_timings[i].data.other_data.data.str.str[j]) { + if (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] == '\n') + break; + + edid_caps->display_name[j] = + edid_buf->detailed_timings[i].data.other_data.data.str.str[j]; + j++; + } + } + } +#endif #if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) edid_caps->edid_hdmi = connector->display_info.is_hdmi; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6db9845cfabed..e03b550b5ae49 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1111,6 +1111,9 @@ /* bitmap_free() is available */ #define HAVE_BITMAP_FUNCS 1 +/* drm_edid_get_monitor_name is available*/ +#define HAVE_DRM_EDID_GET_MONITOR_NAME 1 + /* __drm_atomic_helper_connector_destroy_state() wants 1 arg */ #define HAVE___DRM_ATOMIC_HELPER_CONNECTOR_DESTROY_STATE_P 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 new file mode 100644 index 0000000000000..c5de63f48eb91 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v4.6-rc2-221-g59f7c0fa325e +dnl # drm/edid: Add drm_edid_get_monitor_name() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_GET_MONITOR_NAME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_edid_get_monitor_name(NULL, NULL, NULL); + ], [drm_edid_get_monitor_name], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_EDID_GET_MONITOR_NAME, 1, + [drm_edid_get_monitor_name() are available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c3d8d75ebc40c..7ac5457623661 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -178,6 +178,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI AC_AMDGPU_DRM_BITMAP_FUNCS + AC_AMDGPU_DRM_EDID_GET_MONITOR_NAME AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 96198b9c7a9ce2bd2853d0a3ab13d37ec50e2a3c Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 27 Dec 2021 21:50:08 -0500 Subject: [PATCH 0629/2653] drm/amddkms: remove the duplicated amdgpu_amdkfd_gpuvm_pin_bo call The patch fix the amdgpu bo released twice kernel warning [ 604.329614] Workqueue: kfd_process_wq kfd_process_wq_release [amdgpu] [ 604.329752] RIP: 0010:ttm_bo_release+0x2f6/0x320 [amdttm] [ 604.329757] Code: e8 2f 68 e8 d4 e9 9e fd ff ff 48 8b 7b 94 b9 4c 1d 00 00 31 d2 be 01 00 00 00 e8 65 23 36 00 48 8b 7b e4 eb 9d 4c 89 e7 eb 98 <0f> 0b e9 2e fd ff ff e8 6e 60 e8 d4 e9 ed fe ff ff be 03 00 00 00 [ 604.329758] RSP: 0018:ffffaebec0c8fc40 EFLAGS: 00010202 [ 604.329759] RAX: 0000000000000001 RBX: ffff971f8716adbc RCX: 0000000080400039 [ 604.329760] RDX: 0000000000000001 RSI: 0000000080400039 RDI: ffff971f8716adbc [ 604.329761] RBP: ffffaebec0c8fc68 R08: ffff971f8716adbc R09: ffffffffc053b900 [ 604.329762] R10: ffff971fee794540 R11: 0000000000000001 R12: ffff971f93c65368 [ 604.329762] R13: ffff971f8db13038 R14: ffff971f8716ac58 R15: dead000000000100 [ 604.329763] FS: 0000000000000000(0000) GS:ffff97268edc0000(0000) knlGS:0000000000000000 [ 604.329764] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 604.329765] CR2: 0000000620cdc258 CR3: 000000051c610005 CR4: 00000000003706e0 [ 604.329766] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 604.329767] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 604.329767] Call Trace: [ 604.329769] amdttm_bo_put+0x30/0x50 [amdttm] [ 604.329772] amdgpu_bo_unref+0x1e/0x30 [amdgpu] [ 604.329856] amdgpu_gem_object_free+0x8c/0x160 [amdgpu] [ 604.329939] drm_gem_object_free+0x1d/0x30 [drm] [ 604.329956] amdgpu_amdkfd_gpuvm_free_memory_of_gpu+0x35e/0x3b0 [amdgpu] [ 604.330071] ? preempt_schedule_common+0x18/0x30 [ 604.330074] kfd_process_device_free_bos+0xda/0x120 [amdgpu] [ 604.330183] kfd_process_wq_release+0x2a4/0x360 [amdgpu] [ 604.330289] process_one_work+0x220/0x3c0 [ 604.330291] worker_thread+0x4d/0x3f0 [ 604.330292] ? process_one_work+0x3c0/0x3c0 [ 604.330293] kthread+0x12b/0x150 [ 604.330295] ? set_kthread_struct+0x40/0x40 [ 604.330297] ret_from_fork+0x22/0x30 [ 604.330300] ---[ end trace acd84dcb8e491ccb ]--- It was caused by below commit deffdd3f09 drm/amdgpu: Pin MMIO/DOORBELL BO's in GTT domain v5.13-2965-gdeffdd3f0971 Signed-off-by: Perry Yuan Reviewed-by: Guchun Chen Change-Id: Ica29a250dae065f9999803d94f858f8dda6840aa --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 437dd6bd28e62..6f36cd02705d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1896,17 +1896,6 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( if (offset) *offset = amdgpu_bo_mmap_offset(bo); - if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | - KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { - ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT); - if (ret) { - pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n"); - goto err_pin_bo; - } - bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; - bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; - } - return 0; allocate_init_user_pages_failed: From b4ed0b6350ff6dec02d223212a7c2dc6d5435873 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 28 Dec 2021 12:26:09 +0800 Subject: [PATCH 0630/2653] drm/amdkcl: refactor code for drm_aperture.h Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 5 +++-- drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 | 16 ---------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/header/drm/drm_aperture.h | 9 +++++++++ include/kcl/kcl_drm_aperture.h | 4 ++-- 5 files changed, 14 insertions(+), 21 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 create mode 100644 include/kcl/header/drm/drm_aperture.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c index 99c29f3b4c803..f91a4d60ffd11 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: MIT -#ifndef HAVE_DRM_APERTURE +#ifndef HAVE_DRM_APERTURE_H + #include #include #include @@ -142,4 +143,4 @@ int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const } EXPORT_SYMBOL(drm_aperture_remove_conflicting_pci_framebuffers); -#endif /* HAVE_DRM_APERTURE */ +#endif /* HAVE_DRM_APERTURE_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 deleted file mode 100644 index 532e9149653c9..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit 2916059147ea38f76787d7b38dee883da2e9def2 -dnl # drm/aperture: Add infrastructure for aperture ownership -dnl # -AC_DEFUN([AC_AMDGPU_DRM_APERTURE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - drm_aperture_remove_conflicting_pci_framebuffers(NULL, NULL); - ], [ - AC_DEFINE(HAVE_DRM_APERTURE, 1, - [drm_aperture_remove_* is availablea]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7ac5457623661..111eaab3e8ad2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -151,7 +151,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON - AC_AMDGPU_DRM_APERTURE AC_AMDGPU_PCI_DRIVER_DEV_GROUPS AC_AMDGPU_DRM_DISPLAY_INFO AC_AMDGPU_IO_MAPPING_UNMAP_LOCAL diff --git a/include/kcl/header/drm/drm_aperture.h b/include/kcl/header/drm/drm_aperture.h new file mode 100644 index 0000000000000..9197d9538fc69 --- /dev/null +++ b/include/kcl/header/drm/drm_aperture.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_APERTURE_H_H_ +#define _KCL_HEADER_DRM_APERTURE_H_H_ + +#if defined(HAVE_DRM_DRM_APERTURE_H) +#include_next +#endif + +#endif diff --git a/include/kcl/kcl_drm_aperture.h b/include/kcl/kcl_drm_aperture.h index 5c402e251a5d9..e1af88ce1ba85 100644 --- a/include/kcl/kcl_drm_aperture.h +++ b/include/kcl/kcl_drm_aperture.h @@ -2,7 +2,7 @@ #ifndef KCL_KCL_DRM_APERTURE_H #define KCL_KCL_DRM_APERTURE_H -#ifndef HAVE_DRM_APERTURE +#ifndef HAVE_DRM_DRM_APERTURE_H #include @@ -20,6 +20,6 @@ int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_ int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name); -#endif /* HAVE_DRM_APERTURE */ +#endif /* HAVE_DRM_DRM_APERTURE_H */ #endif From be974087413030a56c9a5246960d327853a09a3c Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 28 Dec 2021 22:54:31 -0500 Subject: [PATCH 0631/2653] drm/amdkcl: rename the bitmap function prefix for definition conflicts The patch will fix the bitmap_free and some other new bitmap_xx function on the some old version kernel, including ubuntu 18.04 4.15.0-72-generic kernel, the patch rename the bitmap function with kcl_ as prefix to resolve the name space conflict issue. the new patch is based on below commit and improve it. 99eae3189d5f drm/amdkcl: fake bitmap_alloc(), bitmap_zalloc() and bitmap_free() Signed-off-by: Perry Yuan Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c | 14 +++++++------- .../drm/amd/amdkfd/kfd_process_queue_manager.c | 9 +++++++++ .../drm/amd/dkms/m4/drm-bitmap-functions.m4 | 18 +++++++++++++----- include/kcl/kcl_bitmap.h | 6 +++--- 4 files changed, 32 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c b/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c index 106a0960013d2..946b29d66408b 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c @@ -26,23 +26,23 @@ #include #include -unsigned long *bitmap_alloc(unsigned int nbits, gfp_t flags) +unsigned long *kcl_bitmap_alloc(unsigned int nbits, gfp_t flags) { return kmalloc_array(BITS_TO_LONGS(nbits), sizeof(unsigned long), flags); } -EXPORT_SYMBOL(bitmap_alloc); +EXPORT_SYMBOL(kcl_bitmap_alloc); -unsigned long *bitmap_zalloc(unsigned int nbits, gfp_t flags) +unsigned long *kcl_bitmap_zalloc(unsigned int nbits, gfp_t flags) { - return bitmap_alloc(nbits, flags | __GFP_ZERO); + return kcl_bitmap_alloc(nbits, flags | __GFP_ZERO); } -EXPORT_SYMBOL(bitmap_zalloc); +EXPORT_SYMBOL(kcl_bitmap_zalloc); -void bitmap_free(const unsigned long *bitmap) +void kcl_bitmap_free(const unsigned long *bitmap) { kfree(bitmap); } -EXPORT_SYMBOL(bitmap_free); +EXPORT_SYMBOL(kcl_bitmap_free); #endif /* HAVE_BITMAP_FUNCS */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index c58fe0e4bbcdc..6737e35655a4d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -175,8 +175,13 @@ void kfd_process_dequeue_from_all_devices(struct kfd_process *p) int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p) { INIT_LIST_HEAD(&pqm->queues); +#if defined(HAVE_BITMAP_FUNCS) pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, GFP_KERNEL); +#else + pqm->queue_slot_bitmap = kcl_bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, + GFP_KERNEL); +#endif if (!pqm->queue_slot_bitmap) return -ENOMEM; pqm->process = p; @@ -237,7 +242,11 @@ void pqm_uninit(struct process_queue_manager *pqm) kfree(pqn); } +#if defined(HAVE_BITMAP_FUNCS) bitmap_free(pqm->queue_slot_bitmap); +#else + kcl_bitmap_free(pqm->queue_slot_bitmap); +#endif pqm->queue_slot_bitmap = NULL; } diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 index 542826aa5e405..b91abf96c4598 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 @@ -4,9 +4,17 @@ dnl # v4.17-3-gc42b65e363ce dnl # bitmap: Add bitmap_alloc(), bitmap_zalloc() and bitmap_free() dnl # AC_DEFUN([AC_AMDGPU_DRM_BITMAP_FUNCS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([bitmap_free], [linux/bitmap.h], [ - AC_DEFINE(HAVE_BITMAP_FUNCS, 1, [bitmap_free() is available]) - ]) - ]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + bitmap_free(NULL); + bitmap_alloc(NULL); + bitmap_zalloc(NULL); + ],[ + AC_DEFINE(HAVE_BITMAP_FUNCS, + 1, + [bitmap_free(),bitmap_alloc(),bitmap_zalloc is available]) + ]) + ]) ]) diff --git a/include/kcl/kcl_bitmap.h b/include/kcl/kcl_bitmap.h index 5eb728c542ef3..f65fa8fbcc56d 100644 --- a/include/kcl/kcl_bitmap.h +++ b/include/kcl/kcl_bitmap.h @@ -34,9 +34,9 @@ * Allocation and deallocation of bitmap. * Provided in lib/bitmap.c to avoid circular dependency. */ -unsigned long *bitmap_alloc(unsigned int nbits, gfp_t flags); -unsigned long *bitmap_zalloc(unsigned int nbits, gfp_t flags); -void bitmap_free(const unsigned long *bitmap); +unsigned long *kcl_bitmap_alloc(unsigned int nbits, gfp_t flags); +unsigned long *kcl_bitmap_zalloc(unsigned int nbits, gfp_t flags); +void kcl_bitmap_free(const unsigned long *bitmap); #endif /* HAVE_BITMAP_FUNCS */ #endif /* KCL_BITMAP_H */ From 468e397d271de0974e6e08dad9162f7d52b3339b Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Sun, 26 Dec 2021 21:21:31 -0500 Subject: [PATCH 0632/2653] drm/amdkcl: add wait callback to the amdgpu_job_fence_ops the patch fix the kernel hang issue which was caused by below commit. 8daddbf88a414b33be drm/amdgpu: introduce new amdgpu_fence object to indicate the job embedded fence v5.13-3204-g8daddbf88a41 Signed-off-by: Perry Yuan Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index de549f5a4c31a..ec0f26fed010a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -953,6 +953,7 @@ static const struct dma_fence_ops amdgpu_job_fence_ops = { .get_driver_name = amdgpu_fence_get_driver_name, .get_timeline_name = amdgpu_job_fence_get_timeline_name, .enable_signaling = amdgpu_job_fence_enable_signaling, + AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = amdgpu_job_fence_release, }; From 5b5f9de0462566f7f12a6fe9c3a087ef6593e28c Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Wed, 5 Jan 2022 13:33:44 -0500 Subject: [PATCH 0633/2653] drm/amdgpu: Re-enable GFX RAS by default This was disabled due to issues on A+A but these have been addressed. Re-enable GFX RAS by default and remove the requirement on ras_mask=0xe Signed-off-by: Kent Russell Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 405db4ba15334..fd29658eee798 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3918,14 +3918,9 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) } else { /* driver only manages a few IP blocks RAS feature * when GPU is connected cpu through XGMI */ - adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__SDMA | - 1 << AMDGPU_RAS_BLOCK__MMHUB); - /* This is temporary workaround to leverage ras_mask - * to allow nable GFX RAS manually. Should be removed later - */ - if (amdgpu_ras_enable && - (amdgpu_ras_mask == 0xe)) - adev->ras_hw_enabled |= 1 << AMDGPU_RAS_BLOCK__GFX; + adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX | + 1 << AMDGPU_RAS_BLOCK__SDMA | + 1 << AMDGPU_RAS_BLOCK__MMHUB); } /* apply asic specific settings (vega20 only for now) */ From 8dcc0beaa61d0829955ddc5e812e6d7c1ae00202 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Mon, 20 Dec 2021 16:06:19 -0500 Subject: [PATCH 0634/2653] drm/amdkfd: switch debugger asic type checks to ip version checks The rest of the driver now uses IP version checks so have the debugger code do the same. Signed-off-by: Jonathan Kim Reviewed-by: Graham Sider --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index e4a2da0d814dd..b4a5593cf342a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -593,12 +593,14 @@ static int kfd_gws_init(struct kfd_node *node) node->adev->gds.gws_size, &node->gws); } - if ((kfd->adev->asic_type == CHIP_VEGA10 - && kfd->mec2_fw_version < 0x81b6) - || (kfd->adev->asic_type >= CHIP_VEGA12 - && kfd->adev->asic_type <= CHIP_RAVEN - && kfd->mec2_fw_version < 0x1b6) - || (kfd->adev->asic_type == CHIP_ARCTURUS + if ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 0, 1) + && kfd->mec2_fw_version < 0x81b6) || + (KFD_GC_VERSION(kfd) >= IP_VERSION(9, 1, 0) + && KFD_GC_VERSION(kfd) <= IP_VERSION(9, 2, 2) + && kfd->mec2_fw_version < 0x1b6) || + (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 0) + && kfd->mec2_fw_version < 0x1b6) || + (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1) && kfd->mec2_fw_version < 0x30)) kfd->gws_debug_workaround = true; From 1899b810b26848f31e056cd7759b1ba7575371c1 Mon Sep 17 00:00:00 2001 From: Alex Sierra Date: Wed, 5 Jan 2022 20:54:22 -0600 Subject: [PATCH 0635/2653] drm/amdkcl: test for full HMM support in kernel Make sure HMM is fully supported in the current kernel version. Some Kernels that were HMM back ported, have missing implementation. Ex. RHEL 8.5 with Kernel 4.18. Signed-off-by: Alex Sierra Suggested-by: Flora Cui Acked-by: Felix Kuehling Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 index c175fd6289702..72147cbe68a28 100644 --- a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -32,6 +32,7 @@ AC_DEFUN([AC_AMDGPU_HMM_RANGE_FAULT], [ ]) dnl # +dnl # v5.1-10231-gbf198b2b34bf: mm/mmu_notifier: pass down vma and reasons why mmu notifier is happening dnl # 93f4e735b6d9 - mm/hmm: remove hmm_range_dma_map and hmm_range_dma_unmap 2019-11-23 19:56:45 -0400 dnl # d28c2c9a4877 - mm/hmm: make full use of walk_page_range() 2019-11-23 19:56:45 -0400 dnl # d3eeb1d77c5d - xen/gntdev: use mmu_interval_notifier_insert 2019-11-23 19:56:45 -0400 @@ -53,10 +54,14 @@ AC_DEFUN([AC_AMDGPU_HMM], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ #include + #include ], [ #ifdef CONFIG_HMM_MIRROR struct hmm_range *range = NULL; + struct mmu_notifier_range *mmu_range = NULL; + range->notifier = NULL; + mmu_range->vma = NULL; #else #error CONFIG_HMM_MIRROR not enabled #endif From e9f4e81328a695638a18950e9aad2c4ead8dfd3e Mon Sep 17 00:00:00 2001 From: majun Date: Wed, 12 Jan 2022 14:16:44 +0800 Subject: [PATCH 0636/2653] amd/amdkcl: Fix the compile error caused by struct kobj_type The patch (drm/amdgpu: use default_groups in kobj_type) introduced a new member "default_groups" in struct kobj_type. To fix the compile errors cuased by this patch, a new kcl macro is added. Reviewed-by: Guchun Chen Signed-off-by: majun Change-Id: If536c7cddfafd17be652a7f15cb68f2e7b4a80d4 --- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 6 ++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/struct_kobj_type.m4 | 19 +++++++++++++++++++ 4 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_kobj_type.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index 1ede308a7c677..95f3611d743b7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -396,7 +396,9 @@ static struct attribute *amdgpu_xgmi_hive_attrs[] = { &amdgpu_xgmi_hive_id, NULL }; +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(amdgpu_xgmi_hive); +#endif static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj, struct attribute *attr, char *buf) @@ -429,7 +431,11 @@ static const struct sysfs_ops amdgpu_xgmi_hive_ops = { static const struct kobj_type amdgpu_xgmi_hive_type = { .release = amdgpu_xgmi_hive_release, .sysfs_ops = &amdgpu_xgmi_hive_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = amdgpu_xgmi_hive_groups, +#else + .default_attrs = amdgpu_xgmi_hive_attrs, +#endif }; static ssize_t amdgpu_xgmi_show_device_id(struct device *dev, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e03b550b5ae49..ab745ced8746c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1129,6 +1129,9 @@ /* __print_array is available */ #define HAVE___PRINT_ARRAY 1 +/* kobj_type->default_groups is available */ +#define HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 111eaab3e8ad2..f83019d5db1e2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -178,6 +178,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI AC_AMDGPU_DRM_BITMAP_FUNCS AC_AMDGPU_DRM_EDID_GET_MONITOR_NAME + AC_AMDGPU_STRUCT_KOBJ_TYPE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_kobj_type.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_kobj_type.m4 new file mode 100644 index 0000000000000..a698f80362f2c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_kobj_type.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit aa30f47cf666111f6bbfd15f290a27e8a7b9d854 +dnl # kobject: Add support for default attribute groups to kobj_type +dnl # + +AC_DEFUN([AC_AMDGPU_STRUCT_KOBJ_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct kobj_type *k_type = NULL; + k_type->default_groups = NULL; + ],[ + AC_DEFINE(HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE, 1, + [kobj_type->default_groups is available]) + ],[ + ]) + ]) +]) From 1afe79fea9554efb34f810c93167b0d1d61a7b44 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 11 Jan 2022 13:35:09 +0800 Subject: [PATCH 0637/2653] drm/amdkcl: cleanup kcl_bitmap_xxx rename to bitmap_xxx to avoid changes in amdgpu part Reviewed-by: Ma Jun Signed-off-by: Flora Cui Change-Id: I3401f1758f146521f7115a14880f779811e3bb4f --- .../amd/amdkfd/kfd_process_queue_manager.c | 4 +-- drivers/gpu/drm/amd/backport/backport.h | 2 +- include/kcl/backport/kcl_bitmap.h | 34 +++++++++++++++++++ 3 files changed, 37 insertions(+), 3 deletions(-) create mode 100644 include/kcl/backport/kcl_bitmap.h diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 6737e35655a4d..10e91898146ca 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -179,7 +179,7 @@ int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p) pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, GFP_KERNEL); #else - pqm->queue_slot_bitmap = kcl_bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, + pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, GFP_KERNEL); #endif if (!pqm->queue_slot_bitmap) @@ -245,7 +245,7 @@ void pqm_uninit(struct process_queue_manager *pqm) #if defined(HAVE_BITMAP_FUNCS) bitmap_free(pqm->queue_slot_bitmap); #else - kcl_bitmap_free(pqm->queue_slot_bitmap); + bitmap_free(pqm->queue_slot_bitmap); #endif pqm->queue_slot_bitmap = NULL; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index c26be24e7c01b..0bb5673cc401e 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -80,6 +80,6 @@ #include "kcl/kcl_drm_aperture.h" #include #include -#include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/backport/kcl_bitmap.h b/include/kcl/backport/kcl_bitmap.h new file mode 100644 index 0000000000000..5871f13aff831 --- /dev/null +++ b/include/kcl/backport/kcl_bitmap.h @@ -0,0 +1,34 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __KCL_BACKPORT_KCL_BITMAP_H_ +#define __KCL_BACKPORT_KCL_BITMAP_H_ + +#include +#include + +#ifndef HAVE_BITMAP_FUNCS +#define bitmap_alloc kcl_bitmap_alloc +#define bitmap_zalloc kcl_bitmap_zalloc +#define bitmap_free kcl_bitmap_free +#endif /* HAVE_BITMAP_FUNCS */ + +#endif /* KCL_BITMAP_H */ From ccd17be4d10ac0155fe2d1bf1bc2daec2a7d6039 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Tue, 18 Jan 2022 02:06:39 -0500 Subject: [PATCH 0638/2653] drm/amdkcl: Fix for CAP_CHECKPOINT_RESTORE not defined Fix for CAP_CHECKPOINT_RESTORE not defined on kernels before 5.9 Reviewed-by: Flora Cui Reviewed-by: Felix Kuehling Signed-off-by: David Yat Sin --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_capability.h | 31 +++++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 include/kcl/kcl_capability.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 0bb5673cc401e..7f1ec2c474a53 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -81,5 +81,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_capability.h b/include/kcl/kcl_capability.h new file mode 100644 index 0000000000000..2cc984db5ac19 --- /dev/null +++ b/include/kcl/kcl_capability.h @@ -0,0 +1,31 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _KCL_KCL_CAPABILITY_H +#define _KCL_KCL_CAPABILITY_H + +#include + +#ifndef CAP_CHECKPOINT_RESTORE +#define CAP_CHECKPOINT_RESTORE CAP_SYS_ADMIN +#endif + +#endif From c90c71a4b45e7eb8023f9d4ac80cc11680476f68 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Tue, 18 Jan 2022 02:06:40 -0500 Subject: [PATCH 0639/2653] drm/amdkcl: fix for close_fd not defined Use ksys_close instead of close_fd on older kernels Reviewed-by: Flora Cui Reviewed-by: Felix Kuehling (rajneesh: removed new line EOF warning) Signed-off-by: Rajneesh Bhardwaj Signed-off-by: David Yat Sin --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 | 15 +++++++++++++++ include/kcl/kcl_fdtable.h | 10 ++++++++++ 5 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 create mode 100644 include/kcl/kcl_fdtable.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7f1ec2c474a53..c712af60c7345 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -82,5 +82,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ab745ced8746c..54d03fda804e6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1132,6 +1132,9 @@ /* kobj_type->default_groups is available */ #define HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE 1 +/* close_fd() is available */ +#define HAVE_KERNEL_CLOSE_FD 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f83019d5db1e2..f9887daf39d7c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -179,6 +179,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_BITMAP_FUNCS AC_AMDGPU_DRM_EDID_GET_MONITOR_NAME AC_AMDGPU_STRUCT_KOBJ_TYPE + AC_AMDGPU_CLOSE_FD AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 b/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 new file mode 100644 index 0000000000000..59eb3c9632fdc --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit 8760c909f54a82aaa6e76da19afe798a0c77c3c3 +dnl # file: Rename __close_fd to close_fd and remove the files parameter +dnl # +AC_DEFUN([AC_AMDGPU_CLOSE_FD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + close_fd(0); + ], [ + AC_DEFINE(HAVE_KERNEL_CLOSE_FD, 1, [close_fd() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_fdtable.h b/include/kcl/kcl_fdtable.h new file mode 100644 index 0000000000000..0a4b97605e146 --- /dev/null +++ b/include/kcl/kcl_fdtable.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_FDTABLE_H +#define _KCL_FDTABLE_H + +#ifndef HAVE_KERNEL_CLOSE_FD +#include +#define close_fd ksys_close +#endif + +#endif From affef40a5f22e0142f8daf260e7e90335bde788b Mon Sep 17 00:00:00 2001 From: majun Date: Wed, 19 Jan 2022 19:28:44 +0800 Subject: [PATCH 0640/2653] amd/amdkcl: Fix the compile bug of ksys_close missing Fix the bug caused by ksys_close missing in some kernels. Reviewed-by: Flora Cui Signed-off-by: majun Change-Id: Ibc94fdac9392b642f1f748c1dacff076f524a8ce --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 | 12 ++++++++++++ include/kcl/kcl_fdtable.h | 4 ++++ 3 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 54d03fda804e6..6527a353d3005 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1135,6 +1135,9 @@ /* close_fd() is available */ #define HAVE_KERNEL_CLOSE_FD 1 +/* ksys_close() is available */ +#define HAVE_KSYS_CLOSE_FD 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" diff --git a/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 b/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 index 59eb3c9632fdc..82b1e366bd09a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 @@ -10,6 +10,18 @@ AC_DEFUN([AC_AMDGPU_CLOSE_FD], [ close_fd(0); ], [ AC_DEFINE(HAVE_KERNEL_CLOSE_FD, 1, [close_fd() is available]) + ], [ + dnl # + dnl # commit 16a78543a1d3537645de737934b9387c42bfb53b + dnl # drm/amdkcl: fix for close_fd not defined + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ksys_close(0); + ], [ + AC_DEFINE(HAVE_KSYS_CLOSE_FD, 1, [ksys_fd() is available]) + ]) ]) ]) ]) diff --git a/include/kcl/kcl_fdtable.h b/include/kcl/kcl_fdtable.h index 0a4b97605e146..f6829418719c5 100644 --- a/include/kcl/kcl_fdtable.h +++ b/include/kcl/kcl_fdtable.h @@ -4,7 +4,11 @@ #ifndef HAVE_KERNEL_CLOSE_FD #include +#ifdef HAVE_KSYS_CLOSE_FD #define close_fd ksys_close +#else +#define close_fd sys_close +#endif #endif #endif From 690d914f2754f2e5de8c6eca0231fdcce7368767 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Wed, 19 Jan 2022 10:34:09 -0500 Subject: [PATCH 0641/2653] drm/amdkfd: Fix ipc_import_handle to use user_gpu_id Change kfd_ioctl_ipc_import_handle to use user_gpu_id. When a process is checkpointed and restored using CRIU on a different server, pdd->dev->id could be different on the restored server. So we use pdd->user_gpu_id as it remains the same throughout the life of kfd_process. Reviewed-by: Rajneesh Bhardwaj Signed-off-by: David Yat Sin --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index fe76ffb6da6bc..a9387f1af52ed 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1677,14 +1677,16 @@ static int kfd_ioctl_ipc_import_handle(struct file *filep, void *data) { struct kfd_ioctl_ipc_import_handle_args *args = data; - struct kfd_dev *dev = NULL; + struct kfd_process_device *pdd; int r; - dev = kfd_device_by_id(args->gpu_id); - if (!dev) + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + mutex_unlock(&p->mutex); + if (!pdd) return -EINVAL; - r = kfd_ipc_import_handle(dev, p, args->gpu_id, args->share_handle, + r = kfd_ipc_import_handle(pdd->dev, p, args->gpu_id, args->share_handle, args->va_addr, &args->handle, &args->mmap_offset, &args->flags); if (r) From 21090cb48559c40c613432e91c6bfb58d3186cb8 Mon Sep 17 00:00:00 2001 From: majun Date: Thu, 13 Jan 2022 14:33:45 +0800 Subject: [PATCH 0642/2653] amd/amdkcl: Fix the compile error caused by missing fucntions in fbdev Because the patch (drm/amdgpu: disable runpm if we are the primary adapter) introduced a new function is_firmware_frambuffer which implemented in drivers/video/fbdev. To avoid the dkms compile error, a new KCL function is added here. v5: - Print the function name in warning message. v4: - Remove the change point in kms v3:(based on Alex's suggestion) - Return false defaultly in is_firmware_framebuffer() - Check the amdgpu_runtime_pm for runpm setup v2: - Fix the typo - Remove the for-each-registered-fb.m4 - Remove the function prefix kcl - Checking the symbol instead of compiling. Signed-off-by: majun Change-Id: I8144b216df9318c95f8083ec3b1e86e00dbdb414 --- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 9 +++++++++ .../gpu/drm/amd/dkms/m4/is-firmware-framebuffer.m4 | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_fb.h | 5 +++++ 4 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/is-firmware-framebuffer.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c index 18f2a20d821da..a4f4f80696c19 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -81,3 +81,12 @@ int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const EXPORT_SYMBOL(remove_conflicting_pci_framebuffers); #endif + +#ifndef HAVE_IS_FIRMWARE_FRAMEBUFFER +bool is_firmware_framebuffer(struct apertures_struct *a) +{ + pr_warn_once("%s:enable the runtime pm\n", __func__); + return false; +} +EXPORT_SYMBOL(is_firmware_framebuffer); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/is-firmware-framebuffer.m4 b/drivers/gpu/drm/amd/dkms/m4/is-firmware-framebuffer.m4 new file mode 100644 index 0000000000000..44d0db303a161 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/is-firmware-framebuffer.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit a99952170b19db855b7b45fba8e263ddc5205a0c +dnl # drm/amdgpu: disable runpm if we are the primary adapter +dnl # + +AC_DEFUN([AC_AMDGPU_IS_FIRMWARE_FRAMEBUFFER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([is_firmware_framebuffer], [include/linux/fb.h], [ + AC_DEFINE(HAVE_IS_FIRMWARE_FRAMEBUFFER, 1, [is_firmware_framebuffer() is available]) + ],[ + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f9887daf39d7c..83683d0531ebd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -180,6 +180,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_EDID_GET_MONITOR_NAME AC_AMDGPU_STRUCT_KOBJ_TYPE AC_AMDGPU_CLOSE_FD + AC_AMDGPU_IS_FIRMWARE_FRAMEBUFFER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 2e66b7b2aa2fa..56361a8b43ebd 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -128,4 +128,9 @@ void drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, _kcl_drm_fb_helper_set_suspend_unlocked(fb_helper, suspend); } #endif + +#ifndef HAVE_IS_FIRMWARE_FRAMEBUFFER +extern bool is_firmware_framebuffer(struct apertures_struct *a); +#endif + #endif From 942491751892da4abd6270e9e4181e26c62a2f44 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Thu, 20 Jan 2022 14:59:05 +0800 Subject: [PATCH 0643/2653] drm/amdkcl: defer to enable generic FB setup by drm version >=5.15 This is workaround, and will be dropped when rooting cause it. Below are the collected failures from drm_fb_helper_damage_work on different kernels. In 5.13.0-27-generic kernel: amdgpu 0000:03:00.0: Damage blitter failed: ret=-22 In 5.13.0-22-generic: BUG: unable to handle page fault for address: 0000000100000008 Signed-off-by: Guchun Chen Reviewed-by: Leslie Shi --- include/kcl/backport/kcl_drm_fb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index 2d165e481704b..87df9c35328f4 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -44,7 +44,7 @@ void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, #if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) && \ defined(HAVE_DRM_DEVICE_FB_HELPER) && \ - DRM_VERSION_CODE >= DRM_VERSION(5, 13, 0) + DRM_VERSION_CODE >= DRM_VERSION(5, 15, 0) #define AMDKCL_DRM_FBDEV_GENERIC #endif From 8e4c4077bd24e525590c09b724298f5428d020c6 Mon Sep 17 00:00:00 2001 From: Nikola Prica Date: Tue, 18 Jan 2022 20:31:16 +0100 Subject: [PATCH 0644/2653] amd/amdkcl: fix ddrv->release check for legacy kernels Fix following error that is detected on Centos 3.10 kernel drm_drv.h:500:12: error: 'struct vm_area_struct' declared inside parameter list Signed-off-by: Nikola Prica Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 index 05801784c5188..8d844a5d7124c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 @@ -5,6 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DRIVER_RELEASE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + struct vm_area_struct; #ifdef HAVE_DRM_DRM_DRV_H #include #else From 837e39fbc87a1d259437bb937c663db0d8bc0b94 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 16:49:29 +0800 Subject: [PATCH 0645/2653] drm/amdkcl: Resolve build issue with kcl_amdgpu_get_vblank_time_ns Fix incompatible pointer type passed as argument 1 of 'drm_crtc_vblank_count_and_time'. Access time field of drm_vblank_crtc structure depending on the field type, defined by HAVE_DRM_VBLANK_USE_KTIME_T or HAVE_DRM_VBLANK_CRTC_HAS_ARRAY_TIME_FIELD. v2: merge tests for drm_vblank_crtc->time, drop checking if drm_vblank_struct exists and fix test for checking if time is array based on test on centos7.3 v3: switch HAVE_DRM_VBLANK_USE_KTIME_T to be tested first and unset HAVE_DRM_VBLANK_CRTC_HAS_ARRAY_TIME_FIELD Signed-off-by: Danijel Slivka Reviewed-by: Flora Cui Signed-off-by: Asher Song --- .../drm/amd/backport/include/kcl/kcl_amdgpu.h | 12 ++--------- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../m4/drm_vblank_use_ktime_t_time_field.m4 | 20 ------------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 4 files changed, 5 insertions(+), 31 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h index fc2eecd49d62b..9b26a06085c84 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -89,17 +89,9 @@ static inline int kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, un #endif /* HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG */ #endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP */ -#if defined(HAVE_DRM_VBLANK_USE_KTIME_T) -static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) { +static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) +{ return vblank->time; } -#else -static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) { - struct timeval tv; - drm_crtc_vblank_count_and_time(vblank, &tv); - return timeval_to_ktime(tv); -} -#endif /* HAVE_DRM_VBLANK_USE_KTIME_T */ - #endif /* AMDGPU_BACKPORT_KCL_AMDGPU_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6527a353d3005..a81d3ace44f4a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -383,6 +383,9 @@ /* drm_vblank struct use ktime_t for time field */ #define HAVE_DRM_VBLANK_USE_KTIME_T 1 +/* drm_vblank->time is array */ +/* #undef HAVE_DRM_VBLANK_CRTC_HAS_ARRAY_TIME_FIELD */ + /* drm_driver->release() is available */ #define HAVE_DRM_DRIVER_RELEASE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 deleted file mode 100644 index b846cb2f57a41..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 +++ /dev/null @@ -1,20 +0,0 @@ -dnl # -dnl # commit v4.14-rc3-721-g67680d3c0464 dnl # drm: vblank: use ktime_t instead of timeval -AC_DEFUN([AC_AMDGPU_DRM_VBLANK_USE_KTIME_T], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - #include - #else - #include - #endif - #include - ], [ - struct drm_vblank_crtc *vblank = NULL; - vblank->time = ns_to_ktime(0); - ], [ - AC_DEFINE(HAVE_DRM_VBLANK_USE_KTIME_T, 1, - [drm_vblank->time uses ktime_t type]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 83683d0531ebd..5acad22846c3e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -166,7 +166,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEV_ENTER AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_AMDGPU_DRM_DEVICE_PDEV - AC_AMDGPU_DRM_VBLANK_USE_KTIME_T AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_GET_MM_EXE_FILE AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT From a450c1e0e473a3cde53ee06c1359e64c2952f1cd Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 27 Jan 2022 19:38:00 +0800 Subject: [PATCH 0646/2653] drm/amdkcl: fix macro name error Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c index f91a4d60ffd11..c81b1cadf0099 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT -#ifndef HAVE_DRM_APERTURE_H +#ifndef HAVE_DRM_DRM_APERTURE_H #include #include From 37543dec7bd8fae77bf7a8a427ce4e6849943f81 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 27 Jan 2022 19:42:09 +0800 Subject: [PATCH 0647/2653] drm/amdkcl: no need to export remove_conflicting_pci_framebuffers it's not used by amdgpu Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c index a4f4f80696c19..742edcc32b042 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -79,7 +79,6 @@ int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const } #endif /* HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG */ -EXPORT_SYMBOL(remove_conflicting_pci_framebuffers); #endif #ifndef HAVE_IS_FIRMWARE_FRAMEBUFFER From 86a783161850580ca360f7c5985137fda95c5c56 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 21 Jan 2022 16:00:32 +0800 Subject: [PATCH 0648/2653] drm/amdkcl: fix test for bitmap_xxx api Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 index b91abf96c4598..c5a71aac5af1e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 @@ -9,8 +9,8 @@ AC_DEFUN([AC_AMDGPU_DRM_BITMAP_FUNCS], [ #include ],[ bitmap_free(NULL); - bitmap_alloc(NULL); - bitmap_zalloc(NULL); + bitmap_alloc(0, 0); + bitmap_zalloc(0, 0); ],[ AC_DEFINE(HAVE_BITMAP_FUNCS, 1, From 735f61bdfd2c63714b3e16e1ba029fe42c4b22a5 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 21 Jan 2022 14:01:56 +0800 Subject: [PATCH 0649/2653] drm/amdkcl: include drm_ttm_helper.ko into dkms package Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/files | 2 +- drivers/gpu/drm/amd/dkms/Makefile | 8 ++++++++ drivers/gpu/drm/amd/dkms/dkms.conf | 4 ++++ drivers/gpu/drm/amd/dkms/sources | 2 ++ 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/files b/drivers/gpu/drm/amd/amdkcl/files index a5a39207c730e..6cc9587ebc525 100644 --- a/drivers/gpu/drm/amd/amdkcl/files +++ b/drivers/gpu/drm/amd/amdkcl/files @@ -1 +1 @@ -FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c" +FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c drm_gem_ttm_helper.c" diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 340258b04f0aa..e7b791c8195f0 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -186,4 +186,12 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN3_x endif endif +export CONFIG_DRM_TTM_HELPER=m +subdir-ccflags-y += -DCONFIG_DRM_TTM_HELPER +CFLAGS_drm_gem_ttm_helper.o += -include $(src)/ttm/backport/backport.h \ + -include $(src)/include/kcl/backport/kcl_drm_gem.h \ + -DHAVE_CONFIG_H +amddrm_ttm_helper-y := drm_gem_ttm_helper.o +obj-$(CONFIG_DRM_TTM_HELPER) += amddrm_ttm_helper.o + obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 146f1b4db6148..bd79232132f60 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -22,6 +22,10 @@ BUILT_MODULE_NAME[3]="amd-sched" BUILT_MODULE_LOCATION[3]="scheduler" DEST_MODULE_LOCATION[3]="/kernel/drivers/gpu/drm/scheduler" +BUILT_MODULE_NAME[4]="amddrm_ttm_helper" +BUILT_MODULE_LOCATION[4]="." +DEST_MODULE_LOCATION[4]="/kernel/drivers/gpu/drm" + # Find out how many CPU cores can be use if we pass appropriate -j option to make. # DKMS could use all cores on multicore systems to build the kernel module. num_cpu_cores() diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources index da9e9612a23fb..60563cf6abf8e 100644 --- a/drivers/gpu/drm/amd/dkms/sources +++ b/drivers/gpu/drm/amd/dkms/sources @@ -29,3 +29,5 @@ drivers/dma-buf/dma-resv.c amd/amdkcl/dma-buf/ include/linux/dma-resv.h include/linux/ include/kcl/reservation.h include/linux/ include/uapi/linux/kfd_sysfs.h include/uapi/linux/ +drivers/gpu/drm/drm_gem_ttm_helper.c . +include/drm/drm_gem_ttm_helper.h include/drm/ From 4be75c4b46c08a87f3ecab1c1bff4e9170202989 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 25 Jan 2022 10:24:15 +0800 Subject: [PATCH 0650/2653] drm/amdkcl: add kcl copy of drm_printf_indent Signed-off-by: Flora Cui --- include/kcl/kcl_drm_print.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 6dea17070b5de..3c4e6b62a6e15 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -159,4 +159,10 @@ static inline bool drm_debug_enabled(unsigned int category) } #endif /* HAVE_DRM_DEBUG_ENABLED */ +/* Copied from v4.14-rc3-610-gbf6234a294c5 include/drm/drm_print.h */ +#ifndef drm_printf_indent +#define drm_printf_indent(printer, indent, fmt, ...) \ + drm_printf((printer), "%.*s" fmt, (indent), "\t\t\t\t\tX", ##__VA_ARGS__) +#endif + #endif From 4c6c6d427dabf11909cfe50b324df9fe230947cf Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 25 Jan 2022 11:44:18 +0800 Subject: [PATCH 0651/2653] drm/amdkcl: add kcl copy drm_print_bits Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 25 +++++++++ drivers/gpu/drm/amd/backport/backport.h | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 6 +++ drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 | 26 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/scheduler/backport/backport.h | 2 +- drivers/gpu/drm/ttm/backport/backport.h | 2 +- include/kcl/backport/kcl_drm_print.h | 51 +++++++++++++++++++ include/kcl/kcl_drm_print.h | 5 ++ 9 files changed, 117 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 create mode 100644 include/kcl/backport/kcl_drm_print.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index b5d9e1a9113a3..907a902c5f204 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -23,6 +23,7 @@ * Rob Clark */ #include +#include #include #if !defined(HAVE_DRM_DRM_PRINT_H) @@ -102,3 +103,27 @@ void kcl_drm_err(const char *format, ...) EXPORT_SYMBOL(kcl_drm_err); #endif + +#ifndef HAVE_DRM_PRINT_BITS +/* Copied from v5.3-rc1-684-g141f6357f45c drivers/gpu/drm/drm_print.c */ +void drm_print_bits(struct drm_printer *p, unsigned long value, + const char * const bits[], unsigned int nbits) +{ + bool first = true; + unsigned int i; + + if (WARN_ON_ONCE(nbits > BITS_PER_TYPE(value))) + nbits = BITS_PER_TYPE(value); + + for_each_set_bit(i, &value, nbits) { + if (WARN_ON_ONCE(!bits[i])) + continue; + drm_printf(p, "%s%s", first ? "" : ",", + bits[i]); + first = false; + } + if (first) + drm_printf(p, "(none)"); +} +EXPORT_SYMBOL(drm_print_bits); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index c712af60c7345..9cad31b0f38d7 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -45,7 +45,7 @@ #endif #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a81d3ace44f4a..562d9d6485769 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -626,6 +626,12 @@ /* drm_printer->prefix is available */ #define HAVE_DRM_PRINTER_PREFIX 1 +/* drm_print_bits() is available */ +#define HAVE_DRM_PRINT_BITS 1 + +/* drm_print_bits() has 4 args */ +#define HAVE_DRM_PRINT_BITS_4ARGS 1 + /* drm_simple_encoder is available */ #define HAVE_DRM_SIMPLE_ENCODER_INIT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 new file mode 100644 index 0000000000000..62209f24b90e0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 @@ -0,0 +1,26 @@ +dnl # +dnl # v5.3-rc1-684-g141f6357f45c +dnl # drm: tweak drm_print_bits() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRINT_BITS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_print_bits(NULL, 0, NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_PRINT_BITS_4ARGS, 1, + [drm_print_bits() has 4 args]) + AC_DEFINE(HAVE_DRM_PRINT_BITS, 1, + [drm_print_bits() is available]) + ], [ + dnl # v5.3-rc1-622-g2dc5d44ccc5e + dnl # drm: add drm_print_bits + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_print_bits], + [drivers/gpu/drm/drm_print.c], [ + AC_DEFINE(HAVE_DRM_PRINT_BITS, 1, + [drm_print_bits() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5acad22846c3e..c1db9dda5b3fa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -83,6 +83,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT AC_AMDGPU_DRM_PRINTER + AC_AMDGPU_DRM_PRINT_BITS AC_AMDGPU_DRM_MM_INSERT_MODE AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 690cfe2fbe358..25460de490b35 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include #endif diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 97ee04f8c9330..21badd8cad2e9 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/include/kcl/backport/kcl_drm_print.h b/include/kcl/backport/kcl_drm_print.h new file mode 100644 index 0000000000000..379308c2563d4 --- /dev/null +++ b/include/kcl/backport/kcl_drm_print.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2016 Red Hat + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + */ + + +// Copied from include/drm/drm_print.h +#ifndef _KCL_BACKPORT_KCL__DRM_PRINT_H__H_ +#define _KCL_BACKPORT_KCL__DRM_PRINT_H__H_ + +#include +#include + +#if !defined(HAVE_DRM_PRINT_BITS_4ARGS) && \ + defined(HAVE_DRM_PRINT_BITS) +static inline +void _kcl_drm_print_bits(struct drm_printer *p, unsigned long value, + const char * const bits[], unsigned int nbits) +{ + unsigned int from, to; + + from = ffs(value); + to = fls(value); + WARN_ON_ONCE(to > nbits); + + drm_print_bits(p, value, bits, from, nbits); +} +#define drm_print_bits _kcl_drm_print_bits +#endif + +#endif diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 3c4e6b62a6e15..d92e4744fea4b 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -165,4 +165,9 @@ static inline bool drm_debug_enabled(unsigned int category) drm_printf((printer), "%.*s" fmt, (indent), "\t\t\t\t\tX", ##__VA_ARGS__) #endif +#ifndef HAVE_DRM_PRINT_BITS +void drm_print_bits(struct drm_printer *p, unsigned long value, + const char * const bits[], unsigned int nbits); +#endif + #endif From 6e3f5b55cc32f77edb2d607ca3f93d00266f16bf Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 26 Jan 2022 17:04:10 +0800 Subject: [PATCH 0652/2653] drm/amdkcl: rework kcl stuff for drm_ttm_helper.ko Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 5 +++ .../include/kcl/kcl_drm_gem_ttm_helper.h | 33 +++---------------- .../drm/amd/backport/kcl_drm_gem_ttm_helper.c | 30 ++--------------- drivers/gpu/drm/amd/dkms/config/config.h | 9 ++--- .../amd/dkms/m4/drm-driver-gem-open-object.m4 | 33 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 7 ---- .../drm/amd/dkms/m4/drm_gem_object_funcs.m4 | 28 ---------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- include/kcl/header/drm/drm_gem_ttm_helper.h | 9 ----- 10 files changed, 51 insertions(+), 109 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 delete mode 100644 include/kcl/header/drm/drm_gem_ttm_helper.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index fa8360f5bb14e..d2a46d1504e77 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3189,8 +3189,8 @@ static struct drm_driver amdgpu_kms_driver = { #endif #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK - .gem_prime_vmap = drm_gem_ttm_vmap, - .gem_prime_vunmap = drm_gem_ttm_vunmap, + .gem_prime_vmap = amdgpu_gem_prime_vmap, + .gem_prime_vunmap = amdgpu_gem_prime_vunmap, #endif .gem_prime_mmap = amdkcl_drm_gem_prime_mmap, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 31f393fd2d2c2..301a3f319a5b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -480,8 +480,13 @@ const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { .open = amdgpu_gem_object_open, .close = amdgpu_gem_object_close, .export = amdgpu_gem_prime_export, +#ifdef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS .vmap = drm_gem_ttm_vmap, .vunmap = drm_gem_ttm_vunmap, +#else + .vmap = amdgpu_gem_prime_vmap, + .vunmap = amdgpu_gem_prime_vunmap, +#endif .mmap = amdgpu_gem_object_mmap, .vm_ops = &amdgpu_gem_vm_ops, }; diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h index e9d8d3fd9d9d8..ae25af4cbc8c5 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h @@ -1,29 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -/* Copied from include/drm/drm_gem_ttm_helper.h */ - #ifndef _KCL_KCL_DRM_GEM_TTM_HELPER_H_H #define _KCL_KCL_DRM_GEM_TTM_HELPER_H_H #include +#include -#ifndef HAVE_DRM_GEM_TTM_VMAP -void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, +#ifndef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS +void amdgpu_gem_prime_vunmap(struct drm_gem_object *gem, void *vaddr); - -void *_kcl_drm_gem_ttm_vmap(struct drm_gem_object *obj); - -static inline -void drm_gem_ttm_vunmap(struct drm_gem_object *gem, - void *vaddr) -{ - _kcl_drm_gem_ttm_vunmap(gem, vaddr); -} - -static inline -void *drm_gem_ttm_vmap(struct drm_gem_object *obj) -{ - return _kcl_drm_gem_ttm_vmap(obj); -} +void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); #endif #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK @@ -34,14 +19,4 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, struct drm_file *file_priv); #endif -#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK -int _kcl_drm_gem_ttm_mmap(struct drm_gem_object *gem, - struct vm_area_struct *vma); -static inline -int drm_gem_ttm_mmap(struct drm_gem_object *gem, - struct vm_area_struct *vma) { - return _kcl_drm_gem_ttm_mmap(gem, vma); -} -#endif - #endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c index b5fb22fa5a50a..2cef03209d156 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -14,8 +14,8 @@ container_of(gem_obj, struct ttm_buffer_object, base) #endif -#ifndef HAVE_DRM_GEM_TTM_VMAP -void *_kcl_drm_gem_ttm_vmap(struct drm_gem_object *obj) +#ifndef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS +void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj) { struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(obj); struct dma_buf_map map; @@ -23,9 +23,8 @@ void *_kcl_drm_gem_ttm_vmap(struct drm_gem_object *obj) ttm_bo_vmap(bo, &map); return map.vaddr; } -EXPORT_SYMBOL(_kcl_drm_gem_ttm_vmap); -void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, +void amdgpu_gem_prime_vunmap(struct drm_gem_object *gem, void *vaddr) { struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); @@ -36,27 +35,4 @@ void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, ttm_bo_vunmap(bo, &map); } -EXPORT_SYMBOL(_kcl_drm_gem_ttm_vunmap); -#endif - -#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK -int _kcl_drm_gem_ttm_mmap(struct drm_gem_object *gem, - struct vm_area_struct *vma) { - - struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); - int ret; - - ret = ttm_bo_mmap_obj(vma, bo); - if (ret < 0) - return ret; - - /* - * ttm has its own object refcounting, so drop gem reference - * to avoid double accounting counting. - */ - drm_gem_object_put(gem); - - return 0; -} -EXPORT_SYMBOL(_kcl_drm_gem_ttm_mmap); #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 562d9d6485769..ea50bc19e2532 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -429,9 +429,6 @@ */ #define HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_GEM_TTM_HELPER_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_HDCP_H 1 @@ -517,6 +514,9 @@ /* drm_gem_map_attach() wants 2 arguments */ /* #undef HAVE_DRM_GEM_MAP_ATTACH_2ARGS */ +/* drm_gem_object_funcs->vmap() has 2 args */ +#define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS 1 + /* drm_gem_object_lookup() wants 2 args */ #define HAVE_DRM_GEM_OBJECT_LOOKUP_2ARGS 1 @@ -529,9 +529,6 @@ /* ttm_buffer_object->base is available */ #define HAVE_DRM_GEM_OBJECT_RESV 1 -/* drm_gem_ttm_vmap() is available */ -#define HAVE_DRM_GEM_TTM_VMAP 1 - /* drm_gen_fb_init_with_funcs() is available */ #define HAVE_DRM_GEN_FB_INIT_WITH_FUNCS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 new file mode 100644 index 0000000000000..cb583a5e9dafd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 @@ -0,0 +1,33 @@ +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_OPEN_OBJECT], [ + AC_KERNEL_DO_BACKGROUND([ + dnl # + dnl # commit v5.10-rc2-329-g49a3f51dfeee + dnl # drm/gem: Use struct dma_buf_map in GEM vmap ops and convert GEM backends + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_gem_object_funcs *funcs = NULL; + funcs->vmap(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS, 1, [drm_gem_object_funcs->vmap() has 2 args]) + ],[ + dnl # commit v5.9-rc5-1077-gd693def4fd1c + dnl # drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver + AC_KERNEL_TRY_COMPILE([ + struct vm_area_struct; + #ifdef HAVE_DRM_DRMP_H + #include + #else + #include + #endif + ],[ + struct drm_driver *drv = NULL; + drv->gem_open_object = NULL; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK, 1, + [drm_gem_open_object is defined in struct drm_drv]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 05687ebbd1ec7..b3b69a3e8dea7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -39,13 +39,6 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_managed.h]) - dnl # - dnl # v5.3-rc1-623-gff540b76f14a - dnl # drm/ttm: add drm gem ttm helpers, - dnl # starting with drm_gem_ttm_print_info() - dnl # - AC_KERNEL_CHECK_HEADERS([drm/drm_gem_ttm_helper.h]) - dnl # dnl # Required by AC_KERNEL_SUPPORTED_AMD_CHIPS macro dnl # diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 deleted file mode 100644 index 353a678db52d7..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 +++ /dev/null @@ -1,28 +0,0 @@ -dnl # -dnl # commit v4.9-rc8-1739-g6d1b81d8e25d -dnl # drm: add crtc helper drm_crtc_from_index() -dnl # commit v5.9-rc5-1077-gd693def4fd1c -dnl # drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver -dnl # -AC_DEFUN([AC_AMDGPU_DRM_GEM_TTM_VMAP], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_gem_ttm_vmap], [drivers/gpu/drm/drm_gem_ttm_helper.c], [ - AC_DEFINE(HAVE_DRM_GEM_TTM_VMAP, 1, [drm_gem_ttm_vmap() is available]) - ],[ - AC_KERNEL_TRY_COMPILE([ - struct vm_area_struct; - #ifdef HAVE_DRM_DRMP_H - #include - #else - #include - #endif - ],[ - struct drm_driver *drv = NULL; - drv->gem_open_object = NULL; - ],[ - AC_DEFINE(HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK, 1, - [drm_gem_open_object is defined in struct drm_drv]) - ]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c1db9dda5b3fa..740c4bc580ca5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -137,7 +137,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_PRIME_PAGES_TO_SG AC_AMDGPU_DRM_CRTC_HELPER_FUNCS AC_AMDGPU_DEBUGFS_CREATE_FILE_SIZE - AC_AMDGPU_DRM_GEM_TTM_VMAP + AC_AMDGPU_DRM_DRIVER_GEM_OPEN_OBJECT AC_AMDGPU_FS_RECLAIM_ACQUIRE AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE AC_AMDGPU_PM_SUSPEND_VIA_FIRMWARE diff --git a/include/kcl/header/drm/drm_gem_ttm_helper.h b/include/kcl/header/drm/drm_gem_ttm_helper.h deleted file mode 100644 index 5612902e4958d..0000000000000 --- a/include/kcl/header/drm/drm_gem_ttm_helper.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER_DRM_GEM_TTM_HELPER_H_H_ -#define _KCL_HEADER_DRM_GEM_TTM_HELPER_H_H_ - -#ifdef HAVE_DRM_DRM_GEM_TTM_HELPER_H -#include_next -#endif - -#endif From 65a0e2f449f39162e9d6d89e6c8c994095dddbbe Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 21 Jan 2022 15:29:52 +0800 Subject: [PATCH 0653/2653] drm/amdkcl: drop trict restriction for drm_fbdev_generic_setup Signed-off-by: Flora Cui --- include/kcl/backport/kcl_drm_fb.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index 87df9c35328f4..662d312577d93 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -43,8 +43,7 @@ void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, #endif #if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) && \ - defined(HAVE_DRM_DEVICE_FB_HELPER) && \ - DRM_VERSION_CODE >= DRM_VERSION(5, 15, 0) + defined(HAVE_DRM_DEVICE_FB_HELPER) #define AMDKCL_DRM_FBDEV_GENERIC #endif From b91d2c07f6d67af2bd58303fb2db4aee52241522 Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Mon, 31 Jan 2022 22:10:31 -0500 Subject: [PATCH 0654/2653] drm/amdkfd: CRIU Update attributes during resume KFD_IOCTL_SVM_ATTR_CLR_FLAGS is not available for querying via get_attr interface but we must clear the flags during restore as there might be some default flags set when the prange is created. Also fix for invalid PREFETCH atribute values saved during checkpoint by replacing them with another dummy KFD_IOCTL_SVM_ATTR_SET_FLAGS attribute. Change-Id: Ibbe573ac5d7cffee80e08668d829b46f6b6aa688 Reviewed-by: Felix Kuehling Signed-off-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 794e27a83ea24..6fd292005efd1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -3999,6 +3999,24 @@ int kfd_criu_resume_svm(struct kfd_process *p) set_attr[num_attrs].type = KFD_IOCTL_SVM_ATTR_CLR_FLAGS; set_attr[num_attrs].value = ~set_flags; + /* CLR_FLAGS is not available via get_attr during checkpoint but + * it needs to be inserted before restoring the ranges so + * allocate extra space for it before calling set_attr + */ + set_attr_size = sizeof(struct kfd_ioctl_svm_attribute) * + (num_attrs + 1); + set_attr = krealloc(set_attr, set_attr_size, + GFP_KERNEL); + if (!set_attr) { + ret = -ENOMEM; + goto exit; + } + + memcpy(set_attr, criu_svm_md->data.attrs, num_attrs * + sizeof(struct kfd_ioctl_svm_attribute)); + set_attr[num_attrs].type = KFD_IOCTL_SVM_ATTR_CLR_FLAGS; + set_attr[num_attrs].value = ~set_flags; + ret = svm_range_set_attr(p, mm, criu_svm_md->data.start_addr, criu_svm_md->data.size, num_attrs + 1, set_attr); From 3e5a1ab918ce439fb5af66ac0b4e6eb459be9378 Mon Sep 17 00:00:00 2001 From: majun Date: Fri, 28 Jan 2022 11:53:21 +0800 Subject: [PATCH 0655/2653] drm/amdkcl: Check if pm_suspend_target_state is defined Fixed the compile error caused by pm_suspend_target_state which is not defined in some legacy kernel versions. v3: - Fix the wrong return value v2: - Modify the patch subject - Fix the return value for APU Signed-off-by: majun Change-Id: Idc26e7045132b61130d9cc9e555729c85ae238b6 --- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 8 ++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/pm_suspend_target_state.m4 | 17 +++++++++++++++++ 3 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pm_suspend_target_state.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index 6c62e27b98002..b108c23873ef0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -1488,8 +1488,12 @@ void amdgpu_acpi_release(void) */ bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { +#ifdef HAVE_PM_SUSPEND_TARGET_STATE return !(adev->flags & AMD_IS_APU) || (pm_suspend_target_state == PM_SUSPEND_MEM); +#else + return true; +#endif } /** @@ -1501,9 +1505,13 @@ bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) */ bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { +#ifdef HAVE_PM_SUSPEND_TARGET_STATE if (!(adev->flags & AMD_IS_APU) || (pm_suspend_target_state != PM_SUSPEND_TO_IDLE)) return false; +#else + return false; +#endif if (adev->asic_type < CHIP_RAVEN) return false; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ea50bc19e2532..7849687698bd9 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1144,6 +1144,9 @@ /* ksys_close() is available */ #define HAVE_KSYS_CLOSE_FD 1 +/* pm_suspend_target_state is available */ +#define HAVE_PM_SUSPEND_TARGET_STATE 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_suspend_target_state.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_suspend_target_state.m4 new file mode 100644 index 0000000000000..7f4394902241d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm_suspend_target_state.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit edf3ad32f18b0ea7d27ea9420f3bb9b2c850b48b +dnl # drm/amd: Warn users about potential s0ix problems +dnl # +AC_DEFUN([AC_AMDGPU_PM_SUSPEND_TARGET_STATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + pm_suspend_target_state = PM_SUSPEND_TO_IDLE; + ],[ + AC_DEFINE(HAVE_PM_SUSPEND_TARGET_STATE, + 1, + [pm_suspend_target_state is available]) + ]) + ]) +]) From 1e2e16558b9f5c3f734584a2e404df97b18336b5 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 6 Jan 2022 10:45:13 +0800 Subject: [PATCH 0656/2653] drm/amdkcl: update config.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7849687698bd9..a589a6f1f9f80 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -49,6 +49,9 @@ /* backlight_device_set_brightness() is available */ #define HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS 1 +/* bitmap_free() is available */ +#define HAVE_BITMAP_FUNCS 1 + /* whether CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL is defined */ #define HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL 1 @@ -287,15 +290,15 @@ /* display_info->hdmi.scdc.scrambling are available */ #define HAVE_DRM_DISPLAY_INFO_HDMI_SCDC_SCRAMBLING 1 +/* display_info->is_hdmi is available */ +#define HAVE_DRM_DISPLAY_INFO_IS_HDMI 1 + /* display_info->max_tmds_clock is available */ #define HAVE_DRM_DISPLAY_INFO_MAX_TMDS_CLOCK 1 /* struct drm_display_info has monitor_range member */ #define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 -/* display_info->is_hdmi is available */ -#define HAVE_DRM_DISPLAY_INFO_IS_HDMI 1 - /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 @@ -436,7 +439,7 @@ #define HAVE_DRM_DRM_IOCTL_H 1 /* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_IRQ_H 1 +/* #undef HAVE_DRM_DRM_IRQ_H */ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_MANAGED_H 1 @@ -659,6 +662,9 @@ /* drm_universal_plane_init() wants 9 args */ #define HAVE_DRM_UNIVERSAL_PLANE_INIT_9ARGS 1 +/* drm_vblank->time uses ktime_t type */ +#define HAVE_DRM_VBLANK_USE_KTIME_T 1 + /* drm_vma_node_verify_access() 2nd argument is drm_file */ #define HAVE_DRM_VMA_NODE_VERIFY_ACCESS_HAS_DRM_FILE 1 @@ -1154,7 +1160,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 5.13.6" +#define PACKAGE_STRING "amdgpu-dkms 5.13.5" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1163,7 +1169,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "5.13.6" +#define PACKAGE_VERSION "5.13.5" #include "config-amd-chips.h" From 88bd1eeae378078aed6339cbffcf9dfc727212c5 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 6 Jan 2022 12:39:56 +0800 Subject: [PATCH 0657/2653] drm/amdkcl: wrap the code under macro CONFIG_DRM_LEGACY The following patch hides the DRM midlayer behind CONFIG_DRM_LEGACY c1736b9008cb "drm: IRQ midlayer is now legacy" Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 5 ++++- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 3 +++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index d2a46d1504e77..a92a70075f879 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3150,7 +3150,9 @@ static struct drm_driver amdgpu_kms_driver = { .get_vblank_timestamp = kcl_amdgpu_get_vblank_timestamp_kms, .get_scanout_position = kcl_amdgpu_get_crtc_scanout_position, #endif +#ifdef CONFIG_DRM_LEGACY .irq_handler = amdgpu_irq_handler, +#endif .ioctls = amdgpu_ioctls_kms, #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK .gem_free_object_unlocked = amdgpu_gem_object_free, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 8cf71e0994592..00751d2e547be 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -162,7 +162,10 @@ void amdgpu_irq_disable_all(struct amdgpu_device *adev) * Returns: * result of handling the IRQ, as defined by &irqreturn_t */ -static irqreturn_t amdgpu_irq_handler(int irq, void *arg) +#ifndef CONFIG_DRM_LEGACY +static +#endif +irqreturn_t amdgpu_irq_handler(int irq, void *arg) { struct drm_device *dev = (struct drm_device *) arg; struct amdgpu_device *adev = drm_to_adev(dev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h index 9f0417456abda..f52bd7e6d9882 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h @@ -121,6 +121,9 @@ enum interrupt_node_id_per_aid { extern const int node_id_to_phys_map[NODEID_MAX]; void amdgpu_irq_disable_all(struct amdgpu_device *adev); +#ifdef CONFIG_DRM_LEGACY +irqreturn_t amdgpu_irq_handler(int irq, void *arg); +#endif int amdgpu_irq_init(struct amdgpu_device *adev); void amdgpu_irq_fini_sw(struct amdgpu_device *adev); From 084e8d18589bc391e3fa51e3fafb0bf6e22dbb5c Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 14 Jan 2022 16:03:54 +0800 Subject: [PATCH 0658/2653] drm/amdkcl: test whether struct drm_vma_offset_node has member readonly This is cause by f425821b946847282708121600fffc20344183a0 "drm/vma: Add a driver_private member to vma_node." v5.13-rc3-1382-gf425821b9468 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/kcl_drm_gem.c | 2 ++ .../m4/drm-vma-offset-node-readonly-field.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 19 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-vma-offset-node-readonly-field.m4 diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c index 328395cbd0125..359099cb8af9e 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c @@ -121,6 +121,7 @@ int _kcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { return -EACCES; } +#ifdef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD if (node->readonly) { if (vma->vm_flags & VM_WRITE) { drm_gem_object_put(obj); @@ -129,6 +130,7 @@ int _kcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { vma->vm_flags &= ~VM_MAYWRITE; } +#endif ret = _kcl_drm_gem_mmap_obj(obj, drm_vma_node_size(node) << PAGE_SHIFT, vma); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-vma-offset-node-readonly-field.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-vma-offset-node-readonly-field.m4 new file mode 100644 index 0000000000000..06ca73cc0fe91 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-vma-offset-node-readonly-field.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.13-rc3-1382-gf425821b9468 +dnl # drm/vma: Add a driver_private member to vma_node. +dnl # +AC_DEFUN([AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_vma_offset_node *node = NULL; + node->readonly = false; + ], [ + AC_DEFINE(HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD, 1, [struct drm_vma_offset_node has readonly field]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 740c4bc580ca5..082e31c2a8cf0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -181,6 +181,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_KOBJ_TYPE AC_AMDGPU_CLOSE_FD AC_AMDGPU_IS_FIRMWARE_FRAMEBUFFER + AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From a05a84a27c8c0c9b7a045fc59242045e900e78e6 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 10:34:10 +0800 Subject: [PATCH 0659/2653] drm/amdkcl: Test whether ww_mutex_trylock() has context argument Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 | 16 ++++++++++ include/kcl/backport/kcl_ww_mutex.h | 29 +++++++++++++++++++ include/kcl/kcl_dma-resv.h | 1 + 5 files changed, 50 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 create mode 100644 include/kcl/backport/kcl_ww_mutex.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a589a6f1f9f80..1e737875cb974 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1114,6 +1114,9 @@ /* wait_queue_entry_t exists */ #define HAVE_WAIT_QUEUE_ENTRY 1 +/* ww_mutex_trylock() has context arg */ +#define HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG 1 + /* is_device_page is available */ /* #undef HAVE_ZONE_DEVICE_PUBLIC */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 082e31c2a8cf0..a1fb4653dc70f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -182,6 +182,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CLOSE_FD AC_AMDGPU_IS_FIRMWARE_FRAMEBUFFER AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD + AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 b/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 new file mode 100644 index 0000000000000..e3018a1b798e0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.15-rc1-1-g12235da8c80a +dnl # kernel/locking: Add context to ww_mutex_trylock() +dnl # +AC_DEFUN([AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int r = ww_mutex_trylock(NULL, NULL); + ], [ + AC_DEFINE(HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG, 1, + [ww_mutex_trylock() has context arg]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_ww_mutex.h b/include/kcl/backport/kcl_ww_mutex.h new file mode 100644 index 0000000000000..101a5b8aacafa --- /dev/null +++ b/include/kcl/backport/kcl_ww_mutex.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Wound/Wait Mutexes: blocking mutual exclusion locks with deadlock avoidance + * + * Original mutex implementation started by Ingo Molnar: + * + * Copyright (C) 2004, 2005, 2006 Red Hat, Inc., Ingo Molnar + * + * Wait/Die implementation: + * Copyright (C) 2013 Canonical Ltd. + * Choice of algorithm: + * Copyright (C) 2018 WMWare Inc. + * + * This file contains the main data structure and API definitions. + */ +#ifndef __KCL_BACKPORT_KCL_WW_MUTEX_H__ +#define __KCL_BACKPORT_KCL_WW_MUTEX_H__ + +#include + +#ifndef HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG +static inline int _kcl_ww_mutex_trylock(struct ww_mutex *lock) +{ + return ww_mutex_trylock(lock); +} +#define ww_mutex_trylock(MUTEX, CTX) _kcl_ww_mutex_trylock(MUTEX) +#endif + +#endif diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 680f1fe9c1757..0d0ccbbb5d043 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -48,6 +48,7 @@ #include #include +#include #include struct dma_resv_list; From 2c1e80e2edfe77bed5e6250490c66ef18afc3939 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 12:03:59 +0800 Subject: [PATCH 0660/2653] drm/amdkcl: Test whether drm_aperture_remove_conflicting_pci_framebuffers() has drm_driver argument Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 9 +++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 4 ++++ ...ture-remove-conflicting-pci-framebuffers.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 32 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c index c81b1cadf0099..c597046dee062 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -107,7 +107,12 @@ EXPORT_SYMBOL(drm_aperture_remove_conflicting_framebuffers); * Returns: * 0 on success, or a negative errno code otherwise */ +#ifdef HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG +int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const struct drm_driver *req_driver) +#else int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) +#endif { resource_size_t base, size; int bar, ret = 0; @@ -128,11 +133,15 @@ int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const #ifdef HAVE_VGA_REMOVE_VGACON #if IS_REACHABLE(CONFIG_FB) +#ifdef HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG + ret = remove_conflicting_pci_framebuffers(pdev, req_driver->name); +#else #ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG ret = remove_conflicting_pci_framebuffers(pdev, name); #else ret = remove_conflicting_pci_framebuffers(pdev, 0, name); #endif +#endif /* HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG */ #endif if (ret == 0) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1e737875cb974..f13f6a45e35d8 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -133,6 +133,10 @@ /* drm_aperture_remove_* is availablea */ #define HAVE_DRM_APERTURE 1 +/* drm_aperture_remove_conflicting_pci_framebuffers() second arg is + drm_driver* */ +#define HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG 1 + /* drm_atomic_get_old_crtc_state() and drm_atomic_get_new_crtc_state() are available */ #define HAVE_DRM_ATOMIC_GET_CRTC_STATE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 new file mode 100644 index 0000000000000..50cfd872b53b3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.13-rc3-1543-g97c9bfe3f660 +dnl # drm/aperture: Pass DRM driver structure instead of driver name +dnl # +AC_DEFUN([AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + struct drm_driver; + ], [ + const struct drm_driver *drv = NULL; + drm_aperture_remove_conflicting_pci_framebuffers(NULL, drv); + ], [ + AC_DEFINE(HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG, 1, + [drm_aperture_remove_conflicting_pci_framebuffers() second arg is drm_driver*]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a1fb4653dc70f..6208139437216 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -183,6 +183,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IS_FIRMWARE_FRAMEBUFFER AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG + AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From d04afc2d24ee97c5c3c02f2584ec484e4c91ad5a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 12:41:56 +0800 Subject: [PATCH 0661/2653] drm/amdkcl: Test whether synchronize_shrinkers() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c | 31 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/synchronize-shrinkers.m4 | 13 ++++++++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_shrinker.h | 10 ++++++ 7 files changed, 60 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 create mode 100644 include/kcl/kcl_shrinker.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 5352465a012f4..dab6bdb4b03ea 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,7 +12,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ - kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o + kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c b/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c new file mode 100644 index 0000000000000..fb57e87ff981b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * Swap reorganised 29.12.95, Stephen Tweedie. + * kswapd added: 7.1.96 sct + * Removed kswapd_ctl limits, and swap out as many pages as needed + * to bring the system back to freepages.high: 2.4.97, Rik van Riel. + * Zone aware kswapd started 02/00, Kanoj Sarcar (kanoj@sgi.com). + * Multiqueue VM started 5.8.00, Rik van Riel. + */ +#include + +#ifndef HAVE_SYNCHRONIZE_SHRINKERS +static DECLARE_RWSEM(shrinker_rwsem); + +/** + * synchronize_shrinkers - Wait for all running shrinkers to complete. + * + * This is equivalent to calling unregister_shrink() and register_shrinker(), + * but atomically and with less overhead. This is useful to guarantee that all + * shrinker invocations have seen an update, before freeing memory, similar to + * rcu. + */ +void synchronize_shrinkers(void) +{ + down_write(&shrinker_rwsem); + up_write(&shrinker_rwsem); +} +EXPORT_SYMBOL(synchronize_shrinkers); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f13f6a45e35d8..a7bd3f8fbc6db 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1064,6 +1064,9 @@ /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ +/* synchronize_shrinkers() is available */ +#define HAVE_SYNCHRONIZE_SHRINKERS 1 + /* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6208139437216..67254d127c1d9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -184,6 +184,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG + AC_AMDGPU_SYNCHRONIZE_SHRINKERS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 new file mode 100644 index 0000000000000..3abf21e7f2b67 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # v5.14-rc3-760-g880121be1179 +dnl # mm/vmscan: add sync_shrinkers function v3 +dnl # +AC_DEFUN([AC_AMDGPU_SYNCHRONIZE_SHRINKERS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([synchronize_shrinkers], + [mm/vmscan.c], [ + AC_DEFINE(HAVE_SYNCHRONIZE_SHRINKERS, 1, + [synchronize_shrinkers() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 21badd8cad2e9..cc5ba307b7e10 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -19,5 +19,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_shrinker.h b/include/kcl/kcl_shrinker.h new file mode 100644 index 0000000000000..d8704a749d2dd --- /dev/null +++ b/include/kcl/kcl_shrinker.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef AMDKCL_SHRINKER_H +#define AMDKCL_SHRINKER_H + +#ifndef HAVE_SYNCHRONIZE_SHRINKERS +extern void synchronize_shrinkers(void); +#endif + +#endif From 93a54db33a7466944e8348bd4374fae109edebb8 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 13:00:54 +0800 Subject: [PATCH 0662/2653] drm/amdkcl: Test whether krealloc_array() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 | 18 +++++++++ include/kcl/backport/kcl_fence_backport.h | 1 + include/kcl/kcl_slab.h | 37 +++++++++++++++++++ 5 files changed, 60 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 create mode 100644 include/kcl/kcl_slab.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a7bd3f8fbc6db..085a46d6325b2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -753,6 +753,9 @@ /* kmap_local_* is available */ #define HAVE_KMAP_LOCAL 1 +/* krealloc_array() is available */ +#define HAVE_KREALLOC_ARRAY 1 + /* kref_read() function is available */ #define HAVE_KREF_READ 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 67254d127c1d9..bc15ff7200126 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -185,6 +185,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG AC_AMDGPU_SYNCHRONIZE_SHRINKERS + AC_AMDGPU_KREALLOC_ARRAY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 b/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 new file mode 100644 index 0000000000000..f9f0fa0a1862f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v5.10-13-gf0dbd2bd1c22 +dnl # mm: slab: provide krealloc_array() +dnl # +AC_DEFUN([AC_AMDGPU_KREALLOC_ARRAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + void *p = krealloc_array(NULL, 0, 0, GFP_KERNEL); + (void)p; + ], [ + AC_DEFINE(HAVE_KREALLOC_ARRAY, 1, + [krealloc_array() is available]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_fence_backport.h b/include/kcl/backport/kcl_fence_backport.h index 7e3e1ab42138b..a29c3293c6c88 100644 --- a/include/kcl/backport/kcl_fence_backport.h +++ b/include/kcl/backport/kcl_fence_backport.h @@ -2,6 +2,7 @@ #ifndef AMDKCL_FENCE_BACKPORT_H #define AMDKCL_FENCE_BACKPORT_H #include +#include /* * commit v4.18-rc2-533-g418cc6ca0607 diff --git a/include/kcl/kcl_slab.h b/include/kcl/kcl_slab.h new file mode 100644 index 0000000000000..e095f8a46088e --- /dev/null +++ b/include/kcl/kcl_slab.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Written by Mark Hemment, 1996 (markhe@nextd.demon.co.uk). + * + * (C) SGI 2006, Christoph Lameter + * Cleaned up and restructured to ease the addition of alternative + * implementations of SLAB allocators. + * (C) Linux Foundation 2008-2013 + * Unified interface for all slab allocators + */ +#ifndef AMDKCL_SLAB_H +#define AMDKCL_SLAB_H + +#include +#include + +#ifndef HAVE_KREALLOC_ARRAY +/** + * krealloc_array - reallocate memory for an array. + * @p: pointer to the memory chunk to reallocate + * @new_n: new number of elements to alloc + * @new_size: new size of a single member of the array + * @flags: the type of memory to allocate (see kmalloc) + */ +static __must_check inline void * +krealloc_array(void *p, size_t new_n, size_t new_size, gfp_t flags) +{ + size_t bytes; + + if (unlikely(check_mul_overflow(new_n, new_size, &bytes))) + return NULL; + + return krealloc(p, bytes, flags); +} +#endif + +#endif From fb916584e5aa91dc746524f88fa146bb274c4e69 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 13:27:47 +0800 Subject: [PATCH 0663/2653] drm/amdkcl: Test whether vga_client_register() don't pass cookie argument Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 17 ++++++++++++++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/vga-client-register.m4 | 18 ++++++++++++++++++ 4 files changed, 38 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/vga-client-register.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 3bb95f5daa055..2359ea4e179b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1948,11 +1948,18 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev) * Enable/disable vga decode (all asics). * Returns VGA resource flags. */ +#ifdef HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev, bool state) +#else +static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state) +#endif { +#ifdef HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev)); - +#else + struct amdgpu_device *adev = cookie; +#endif amdgpu_asic_set_vga_state(adev, state); if (state) return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | @@ -4817,7 +4824,11 @@ int amdgpu_device_init(struct amdgpu_device *adev, * ignore it */ if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) +#ifdef HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE vga_client_register(adev->pdev, amdgpu_device_vga_set_decode); +#else + vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode); +#endif px = amdgpu_device_supports_px(adev); @@ -5002,7 +5013,11 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev) vga_switcheroo_fini_domain_pm_ops(adev->dev); if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) +#ifdef HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE vga_client_unregister(adev->pdev); +#else + vga_client_register(adev->pdev, NULL, NULL, NULL); +#endif if (drm_dev_enter(adev_to_drm(adev), &idx)) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 085a46d6325b2..2343d06843b57 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1088,6 +1088,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_UAPI_LINUX_SCHED_TYPES_H 1 +/* vga_client_register() don't pass a cookie */ +#define HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE 1 + /* vga_remove_vgacon() is available */ #define HAVE_VGA_REMOVE_VGACON 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index bc15ff7200126..9f7ef276af03b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -186,6 +186,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG AC_AMDGPU_SYNCHRONIZE_SHRINKERS AC_AMDGPU_KREALLOC_ARRAY + AC_AMDGPU_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/vga-client-register.m4 b/drivers/gpu/drm/amd/dkms/m4/vga-client-register.m4 new file mode 100644 index 0000000000000..603da40bd05db --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vga-client-register.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v5.13-rc3-1630-gbf44e8cecc03 +dnl # vgaarb: don't pass a cookie to vga_client_register +dnl # +AC_DEFUN([AC_AMDGPU_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + struct pci_dev; + ], [ + unsigned int (*callback)(struct pci_dev *, bool) = NULL; + vga_client_register(NULL, callback); + ], [ + AC_DEFINE(HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE, 1, + [vga_client_register() don't pass a cookie]) + ]) + ]) +]) From 9f971f8d5e863395b3cc2ddfe97814da487d9eca Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 16:51:31 +0800 Subject: [PATCH 0664/2653] drm/amdkcl: Test whether vma_lookup() is available Signed-off-by: Leslie Shi Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 | 16 ++++++++++++++++ include/kcl/kcl_mm.h | 20 ++++++++++++++++++++ 4 files changed, 40 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2343d06843b57..ec9c4c948950c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1097,6 +1097,9 @@ /* vga_switcheroo_set_dynamic_switch() exist */ /* #undef HAVE_VGA_SWITCHEROO_SET_DYNAMIC_SWITCH */ +/* vma_lookup() is available */ +#define HAVE_VMA_LOOKUP 1 + /* vmf_insert_*() are available */ #define HAVE_VMF_INSERT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9f7ef276af03b..36e26eb7c1b87 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -187,6 +187,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SYNCHRONIZE_SHRINKERS AC_AMDGPU_KREALLOC_ARRAY AC_AMDGPU_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE + AC_AMDGPU_VMA_LOOKUP AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 new file mode 100644 index 0000000000000..1eb0129ff303c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.13-105-gce6d42f2e4a2 +dnl # mm: add vma_lookup(), update find_vma_intersection() comments +dnl # +AC_DEFUN([AC_AMDGPU_VMA_LOOKUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vma_lookup(NULL, 0); + ], [ + AC_DEFINE(HAVE_VMA_LOOKUP, 1, + [vma_lookup() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 4f33936bf7dd9..6a9f864111c47 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -70,4 +70,24 @@ static inline bool is_cow_mapping(vm_flags_t flags) } #endif /* HAVE_IS_COW_MAPPING */ +#ifndef HAVE_VMA_LOOKUP +/** + * vma_lookup() - Find a VMA at a specific address + * @mm: The process address space. + * @addr: The user address. + * + * Return: The vm_area_struct at the given address, %NULL otherwise. + */ +static inline +struct vm_area_struct *vma_lookup(struct mm_struct *mm, unsigned long addr) +{ + struct vm_area_struct *vma = find_vma(mm, addr); + + if (vma && addr < vma->vm_start) + vma = NULL; + + return vma; +} +#endif /* HAVE_VMA_LOOKUP */ + #endif /* AMDKCL_MM_H */ From 8259aadacf50bbbbe268ab920c7140add9fd7157 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 14:24:31 +0800 Subject: [PATCH 0665/2653] drm/amdkcl: Test whether generic_handle_domain_irq() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/generic_handle_domain_irq.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +++ 4 files changed, 26 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 00751d2e547be..2e0c6b43e2799 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -477,7 +477,11 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev, } else if (((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) || (client_id == SOC15_IH_CLIENTID_ISP)) && adev->irq.virq[src_id]) { +#ifdef HAVE_GENERIC_HANDLE_DOMAIN_IRQ generic_handle_domain_irq(adev->irq.domain, src_id); +#else + generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id)); +#endif } else if (!adev->irq.client[client_id].sources) { dev_dbg(adev->dev, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ec9c4c948950c..566f38b03388b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -687,6 +687,9 @@ /* drm_driver->gem_free_object_unlocked() is available */ /* #undef HAVE_GEM_FREE_OBJECT_UNLOCKED_IN_DRM_DRIVER */ +/* generic_handle_domain_irq() is available */ +#define HAVE_GENERIC_HANDLE_DOMAIN_IRQ 1 + /* get_mm_exe_file() is available */ #define HAVE_GET_MM_EXE_FILE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 b/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 new file mode 100644 index 0000000000000..d02f0f7f60014 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.13-rc4-24-g8240ef50d486 +dnl # genirq: Add generic_handle_domain_irq() helper +dnl # +AC_DEFUN([AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + generic_handle_domain_irq(NULL, 0); + ], [ + AC_DEFINE(HAVE_GENERIC_HANDLE_DOMAIN_IRQ, 1, + [generic_handle_domain_irq() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 36e26eb7c1b87..4ea3c8e96b723 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -188,6 +188,9 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KREALLOC_ARRAY AC_AMDGPU_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE AC_AMDGPU_VMA_LOOKUP + AC_AMDGPU_DMA_FENCE_CHAIN_ALLOC + AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT + AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From acfff755a559ab337f568ce00ae47eea95606d55 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 15:17:19 +0800 Subject: [PATCH 0666/2653] drm/amdkcl: Test whether linux/stdarg.h is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/display/dc/dc_helper.c | 2 -- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 ++++++ include/kcl/header/linux/stdarg.h | 11 +++++++++++ 4 files changed, 20 insertions(+), 2 deletions(-) create mode 100644 include/kcl/header/linux/stdarg.h diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index 51e41aed7316c..d36c71bfd8279 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -28,8 +28,6 @@ */ #include -#include - #include "dm_services.h" #include "dc.h" diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 566f38b03388b..82b09d7fdc090 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -852,6 +852,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_SCHED_TASK_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_STDARG_H 1 + /* list_bulk_move_tail() is available */ #define HAVE_LIST_BULK_MOVE_TAIL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 38b46427e3689..9e7deb65f6a95 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -72,4 +72,10 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # dma-buf: Add struct dma-buf-map for storing struct dma_buf.vaddr_ptr dnl # AC_KERNEL_CHECK_HEADERS([linux/dma-buf-map.h]) + + dnl # + dnl # v5.14-rc5-11-gc0891ac15f04 + dnl # isystem: ship and use stdarg.h + dnl # + AC_KERNEL_CHECK_HEADERS([linux/stdarg.h]) ]) diff --git a/include/kcl/header/linux/stdarg.h b/include/kcl/header/linux/stdarg.h new file mode 100644 index 0000000000000..c7564aec2d86d --- /dev/null +++ b/include/kcl/header/linux/stdarg.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_STDARG_H_H +#define _KCL_HEADER_LINUX_STDARG_H_H + +#if defined(HAVE_LINUX_STDARG_H) +#include_next +#else +#include +#endif + +#endif From de412e8491cadb554ccfc19e387479ee54d388f2 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Jan 2022 12:41:13 +0800 Subject: [PATCH 0667/2653] drm/amdkcl: access resv field using amdkcl_ttm_resv Signed-off-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 5ebd3ab734aa3..5ffb3c7b662df 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -226,7 +226,7 @@ static void ttm_transfered_destroy(struct ttm_buffer_object *bo) struct ttm_transfer_obj *fbo; fbo = container_of(bo, struct ttm_transfer_obj, base); - dma_resv_fini(&fbo->base.base._resv); + dma_resv_fini(&amdkcl_ttm_resv(&fbo->base)); ttm_bo_put(fbo->bo); kfree(fbo); } From 092c967505a2589a43194a7dd06e09c9383ac62b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Jan 2022 13:18:16 +0800 Subject: [PATCH 0668/2653] drm/amdkcl: add rcu_replace_pointer macro for legacy os Signed-off-by: Leslie Shi --- include/kcl/kcl_rcupdate.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/include/kcl/kcl_rcupdate.h b/include/kcl/kcl_rcupdate.h index da63bf6d4f9e0..d2b09177e7c56 100644 --- a/include/kcl/kcl_rcupdate.h +++ b/include/kcl/kcl_rcupdate.h @@ -26,4 +26,26 @@ #define rcu_pointer_handoff(p) (p) #endif +#ifndef rcu_replace_pointer +#if defined(rcu_dereference_protected) && defined(rcu_assign_pointer) +/** + * rcu_replace_pointer() - replace an RCU pointer, returning its old value + * @rcu_ptr: RCU pointer, whose old value is returned + * @ptr: regular pointer + * @c: the lockdep conditions under which the dereference will take place + * + * Perform a replacement, where @rcu_ptr is an RCU-annotated + * pointer and @c is the lockdep argument that is passed to the + * rcu_dereference_protected() call used to read that pointer. The old + * value of @rcu_ptr is returned, and @rcu_ptr is set to @ptr. + */ +#define rcu_replace_pointer(rcu_ptr, ptr, c) \ +({ \ + typeof(ptr) __tmp = rcu_dereference_protected((rcu_ptr), (c)); \ + rcu_assign_pointer((rcu_ptr), (ptr)); \ + __tmp; \ +}) +#endif +#endif + #endif /* AMDKCL_RCUPDATE_H */ From d355584cfeb28889d7a9ebafdb2daacf225a7da8 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 14:05:53 +0800 Subject: [PATCH 0669/2653] drm/amdkcl: Test whether dma_fence_chain is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c | 262 ++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 2 + drivers/gpu/drm/amd/dkms/config/config.h | 6 + .../gpu/drm/amd/dkms/m4/dma-fence-chain.m4 | 34 +++ include/kcl/kcl_dma_fence_chain.h | 123 ++++++++ include/kcl/kcl_fence.h | 2 + 7 files changed, 430 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 create mode 100644 include/kcl/kcl_dma_fence_chain.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index dab6bdb4b03ea..d18e0cbe51c9a 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,7 +12,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ - kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o + kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c new file mode 100644 index 0000000000000..d396b7439a8d1 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * fence-chain: chain fences together in a timeline + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * Authors: + * Christian König + */ + +#if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) + +#include +#include + +static bool dma_fence_chain_enable_signaling(struct dma_fence *fence); + +/** + * dma_fence_chain_get_prev - use RCU to get a reference to the previous fence + * @chain: chain node to get the previous node from + * + * Use dma_fence_get_rcu_safe to get a reference to the previous fence of the + * chain node. + */ +static struct dma_fence *dma_fence_chain_get_prev(struct dma_fence_chain *chain) +{ + struct dma_fence *prev; + + rcu_read_lock(); + prev = dma_fence_get_rcu_safe(&chain->prev); + rcu_read_unlock(); + return prev; +} + +/** + * dma_fence_chain_walk - chain walking function + * @fence: current chain node + * + * Walk the chain to the next node. Returns the next fence or NULL if we are at + * the end of the chain. Garbage collects chain nodes which are already + * signaled. + */ +struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence) +{ + struct dma_fence_chain *chain, *prev_chain; + struct dma_fence *prev, *replacement, *tmp; + + chain = to_dma_fence_chain(fence); + if (!chain) { + dma_fence_put(fence); + return NULL; + } + + while ((prev = dma_fence_chain_get_prev(chain))) { + + prev_chain = to_dma_fence_chain(prev); + if (prev_chain) { + if (!dma_fence_is_signaled(prev_chain->fence)) + break; + + replacement = dma_fence_chain_get_prev(prev_chain); + } else { + if (!dma_fence_is_signaled(prev)) + break; + + replacement = NULL; + } + + tmp = cmpxchg((struct dma_fence __force **)&chain->prev, + prev, replacement); + if (tmp == prev) + dma_fence_put(tmp); + else + dma_fence_put(replacement); + dma_fence_put(prev); + } + + dma_fence_put(fence); + return prev; +} +EXPORT_SYMBOL(dma_fence_chain_walk); + +/** + * dma_fence_chain_find_seqno - find fence chain node by seqno + * @pfence: pointer to the chain node where to start + * @seqno: the sequence number to search for + * + * Advance the fence pointer to the chain node which will signal this sequence + * number. If no sequence number is provided then this is a no-op. + * + * Returns EINVAL if the fence is not a chain node or the sequence number has + * not yet advanced far enough. + */ +int dma_fence_chain_find_seqno(struct dma_fence **pfence, uint64_t seqno) +{ + struct dma_fence_chain *chain; + + if (!seqno) + return 0; + + chain = to_dma_fence_chain(*pfence); + if (!chain || chain->base.seqno < seqno) + return -EINVAL; + + dma_fence_chain_for_each(*pfence, &chain->base) { + if ((*pfence)->context != chain->base.context || + to_dma_fence_chain(*pfence)->prev_seqno < seqno) + break; + } + dma_fence_put(&chain->base); + + return 0; +} +EXPORT_SYMBOL(dma_fence_chain_find_seqno); + +static const char *dma_fence_chain_get_driver_name(struct dma_fence *fence) +{ + return "dma_fence_chain"; +} + +static const char *dma_fence_chain_get_timeline_name(struct dma_fence *fence) +{ + return "unbound"; +} + +static void dma_fence_chain_irq_work(struct irq_work *work) +{ + struct dma_fence_chain *chain; + + chain = container_of(work, typeof(*chain), work); + + /* Try to rearm the callback */ + if (!dma_fence_chain_enable_signaling(&chain->base)) + /* Ok, we are done. No more unsignaled fences left */ + dma_fence_signal(&chain->base); + dma_fence_put(&chain->base); +} + +static void dma_fence_chain_cb(struct dma_fence *f, struct dma_fence_cb *cb) +{ + struct dma_fence_chain *chain; + + chain = container_of(cb, typeof(*chain), cb); + init_irq_work(&chain->work, dma_fence_chain_irq_work); + irq_work_queue(&chain->work); + dma_fence_put(f); +} + +static bool dma_fence_chain_enable_signaling(struct dma_fence *fence) +{ + struct dma_fence_chain *head = to_dma_fence_chain(fence); + + dma_fence_get(&head->base); + dma_fence_chain_for_each(fence, &head->base) { + struct dma_fence_chain *chain = to_dma_fence_chain(fence); + struct dma_fence *f = chain ? chain->fence : fence; + + dma_fence_get(f); + if (!dma_fence_add_callback(f, &head->cb, dma_fence_chain_cb)) { + dma_fence_put(fence); + return true; + } + dma_fence_put(f); + } + dma_fence_put(&head->base); + return false; +} + +static bool dma_fence_chain_signaled(struct dma_fence *fence) +{ + dma_fence_chain_for_each(fence, fence) { + struct dma_fence_chain *chain = to_dma_fence_chain(fence); + struct dma_fence *f = chain ? chain->fence : fence; + + if (!dma_fence_is_signaled(f)) { + dma_fence_put(fence); + return false; + } + } + + return true; +} + +static void dma_fence_chain_release(struct dma_fence *fence) +{ + struct dma_fence_chain *chain = to_dma_fence_chain(fence); + struct dma_fence *prev; + + /* Manually unlink the chain as much as possible to avoid recursion + * and potential stack overflow. + */ + while ((prev = rcu_dereference_protected(chain->prev, true))) { + struct dma_fence_chain *prev_chain; + + if (kref_read(&prev->refcount) > 1) + break; + + prev_chain = to_dma_fence_chain(prev); + if (!prev_chain) + break; + + /* No need for atomic operations since we hold the last + * reference to prev_chain. + */ + chain->prev = prev_chain->prev; + RCU_INIT_POINTER(prev_chain->prev, NULL); + dma_fence_put(prev); + } + dma_fence_put(prev); + + dma_fence_put(chain->fence); + dma_fence_free(fence); +} + +const struct dma_fence_ops dma_fence_chain_ops = { + .use_64bit_seqno = true, + .get_driver_name = dma_fence_chain_get_driver_name, + .get_timeline_name = dma_fence_chain_get_timeline_name, + .enable_signaling = dma_fence_chain_enable_signaling, + .signaled = dma_fence_chain_signaled, + .release = dma_fence_chain_release, +}; +EXPORT_SYMBOL(dma_fence_chain_ops); + +/** + * dma_fence_chain_init - initialize a fence chain + * @chain: the chain node to initialize + * @prev: the previous fence + * @fence: the current fence + * @seqno: the sequence number to use for the fence chain + * + * Initialize a new chain node and either start a new chain or add the node to + * the existing chain of the previous fence. + */ +void dma_fence_chain_init(struct dma_fence_chain *chain, + struct dma_fence *prev, + struct dma_fence *fence, + uint64_t seqno) +{ + struct dma_fence_chain *prev_chain = to_dma_fence_chain(prev); + uint64_t context; + + spin_lock_init(&chain->lock); + rcu_assign_pointer(chain->prev, prev); + chain->fence = fence; + chain->prev_seqno = 0; + + /* Try to reuse the context of the previous chain node. */ + if (prev_chain && __dma_fence_is_later(seqno, prev->seqno, prev->ops)) { + context = prev->context; + chain->prev_seqno = prev->seqno; + } else { + context = dma_fence_context_alloc(1); + /* Make sure that we always have a valid sequence number. */ + if (prev_chain) + seqno = max(prev->seqno, seqno); + } + + dma_fence_init(&chain->base, &dma_fence_chain_ops, + &chain->lock, context, seqno); +} +EXPORT_SYMBOL(dma_fence_chain_init); +#endif /* HAVE_STRUCT_DMA_FENCE_CHAIN */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 9cad31b0f38d7..a2ab4cd5687fb 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -83,5 +83,7 @@ #include #include #include +#include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 82b09d7fdc090..b2c35e119e36e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -88,6 +88,9 @@ /* dma_buf->dynamic_mapping is not available */ /* #undef HAVE_DMA_BUF_OPS_LEGACY */ +/* dma_fence_chain_alloc() is available */ +#define HAVE_DMA_FENCE_CHAIN_ALLOC 1 + /* whether dma_fence_get_stub exits */ #define HAVE_DMA_FENCE_GET_STUB 1 @@ -994,6 +997,9 @@ /* struct dma_buf_ops->pin() is available */ #define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 +/* struct dma_fence_chain is available */ +#define HAVE_STRUCT_DMA_FENCE_CHAIN 1 + /* struct drm_connector_state->duplicated is available */ #define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 new file mode 100644 index 0000000000000..34231d5d2028d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 @@ -0,0 +1,34 @@ +dnl # +dnl # v5.13-rc3-1424-g440d0f12b52a +dnl # dma-buf: add dma_fence_chain_alloc/free v3 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_ALLOC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_chain_alloc(); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_CHAIN_ALLOC, 1, + [dma_fence_chain_alloc() is available]) + ]) + ]) +]) + +dnl # +dnl # v5.0-1331-g7bf60c52e093 +dnl # dma-buf: add new dma_fence_chain container v7 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_fence_chain *chain = NULL; + ], [ + AC_DEFINE(HAVE_STRUCT_DMA_FENCE_CHAIN, 1, + [struct dma_fence_chain is available]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_dma_fence_chain.h b/include/kcl/kcl_dma_fence_chain.h new file mode 100644 index 0000000000000..4cde69227a3f1 --- /dev/null +++ b/include/kcl/kcl_dma_fence_chain.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * fence-chain: chain fences together in a timeline + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * Authors: + * Christian König + */ +#ifndef AMDKCL_DMA_FENCE_CHAIN_H +#define AMDKCL_DMA_FENCE_CHAIN_H + + +#if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) +#ifdef HAVE_LINUX_DMA_FENCE_H +#include +#else +#include +#endif +#include +#include + +/** + * struct dma_fence_chain - fence to represent an node of a fence chain + * @base: fence base class + * @prev: previous fence of the chain + * @prev_seqno: original previous seqno before garbage collection + * @fence: encapsulated fence + * @lock: spinlock for fence handling + */ +struct dma_fence_chain { + struct dma_fence base; + struct dma_fence __rcu *prev; + u64 prev_seqno; + struct dma_fence *fence; + union { + /** + * @cb: callback for signaling + * + * This is used to add the callback for signaling the + * complection of the fence chain. Never used at the same time + * as the irq work. + */ + struct dma_fence_cb cb; + + /** + * @work: irq work item for signaling + * + * Irq work structure to allow us to add the callback without + * running into lock inversion. Never used at the same time as + * the callback. + */ + struct irq_work work; + }; + spinlock_t lock; +}; + +extern const struct dma_fence_ops dma_fence_chain_ops; + +/** + * to_dma_fence_chain - cast a fence to a dma_fence_chain + * @fence: fence to cast to a dma_fence_array + * + * Returns NULL if the fence is not a dma_fence_chain, + * or the dma_fence_chain otherwise. + */ +static inline struct dma_fence_chain * +to_dma_fence_chain(struct dma_fence *fence) +{ + if (!fence || fence->ops != &dma_fence_chain_ops) + return NULL; + + return container_of(fence, struct dma_fence_chain, base); +} + +/** + * dma_fence_chain_for_each - iterate over all fences in chain + * @iter: current fence + * @head: starting point + * + * Iterate over all fences in the chain. We keep a reference to the current + * fence while inside the loop which must be dropped when breaking out. + */ +#define dma_fence_chain_for_each(iter, head) \ + for (iter = dma_fence_get(head); iter; \ + iter = dma_fence_chain_walk(iter)) + +struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence); +int dma_fence_chain_find_seqno(struct dma_fence **pfence, uint64_t seqno); +void dma_fence_chain_init(struct dma_fence_chain *chain, + struct dma_fence *prev, + struct dma_fence *fence, + uint64_t seqno); + +#endif /* HAVE_STRUCT_DMA_FENCE_CHAIN */ + +#if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) || !defined(HAVE_DMA_FENCE_CHAIN_ALLOC) +/** + * dma_fence_chain_alloc + * + * Returns a new struct dma_fence_chain object or NULL on failure. + */ +static inline struct dma_fence_chain *dma_fence_chain_alloc(void) +{ + return kmalloc(sizeof(struct dma_fence_chain), GFP_KERNEL); +}; + +/** + * dma_fence_chain_free + * @chain: chain node to free + * + * Frees up an allocated but not used struct dma_fence_chain object. This + * doesn't need an RCU grace period since the fence was never initialized nor + * published. After dma_fence_chain_init() has been called the fence must be + * released by calling dma_fence_put(), and not through this function. + */ +static inline void dma_fence_chain_free(struct dma_fence_chain *chain) +{ + kfree(chain); +}; + +#endif + +#endif diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index 88a2d1a425ec2..ec9f6c83ab8da 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -40,6 +40,8 @@ #define dma_fence_remove_callback fence_remove_callback #define dma_fence_enable_sw_signaling fence_enable_sw_signaling #define dma_fence_default_wait fence_default_wait +#define dma_fence_free fence_free +#define dma_fence_get_rcu_safe fence_get_rcu #define dma_fence_set_error fence_set_error #endif From 56da87a1392e30a8bee7c32bb9d46444e46b98a3 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Jan 2022 13:35:38 +0800 Subject: [PATCH 0670/2653] drm/amdkcl: Test whether struct dma_fence_ops has use_64bit_seqno field Signed-off-by: Leslie Shi --- .../gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c | 6 ++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c index d396b7439a8d1..8ee9e8bf76779 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c @@ -212,7 +212,9 @@ static void dma_fence_chain_release(struct dma_fence *fence) } const struct dma_fence_ops dma_fence_chain_ops = { +#ifdef HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO .use_64bit_seqno = true, +#endif .get_driver_name = dma_fence_chain_get_driver_name, .get_timeline_name = dma_fence_chain_get_timeline_name, .enable_signaling = dma_fence_chain_enable_signaling, @@ -245,7 +247,11 @@ void dma_fence_chain_init(struct dma_fence_chain *chain, chain->prev_seqno = 0; /* Try to reuse the context of the previous chain node. */ +#ifdef HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO if (prev_chain && __dma_fence_is_later(seqno, prev->seqno, prev->ops)) { +#else + if (prev_chain && __dma_fence_is_later(seqno, prev->seqno)) { +#endif context = prev->context; chain->prev_seqno = prev->seqno; } else { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b2c35e119e36e..5b2d06af70f69 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -94,6 +94,9 @@ /* whether dma_fence_get_stub exits */ #define HAVE_DMA_FENCE_GET_STUB 1 +/* struct dma_fence_ops has use_64bit_seqno field */ +#define HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO 1 + /* dma_fence_set_error() is available */ #define HAVE_DMA_FENCE_SET_ERROR 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 new file mode 100644 index 0000000000000..c10c92dfb503e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.1-rc2-1115-g5e498abf1485 +dnl # dma-buf: explicitely note that dma-fence-chains use 64bit seqno +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_fence_ops *ops = NULL; + ops->use_64bit_seqno = false; + ], [ + AC_DEFINE(HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO, 1, + [struct dma_fence_ops has use_64bit_seqno field]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4ea3c8e96b723..06bbbf0401bce 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -190,6 +190,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMA_LOOKUP AC_AMDGPU_DMA_FENCE_CHAIN_ALLOC AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT + AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ AC_KERNEL_WAIT From 016af8e42f84ffcdf21e734207ffcd498c6e8b4c Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Jan 2022 14:04:37 +0800 Subject: [PATCH 0671/2653] drm/amdkcl: Test whether linux/dma-fence-chain.h is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 2 -- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 ++++++ include/kcl/header/linux/dma-fence-chain.h | 9 +++++++++ 4 files changed, 18 insertions(+), 2 deletions(-) create mode 100644 include/kcl/header/linux/dma-fence-chain.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index d6ae9974c952e..8858dd9ffb021 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -29,8 +29,6 @@ * Christian König */ -#include - #include "amdgpu.h" #include "amdgpu_trace.h" #include "amdgpu_amdkfd.h" diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5b2d06af70f69..224ce75be2c1c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -819,6 +819,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_BUF_MAP_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_FENCE_CHAIN_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_FENCE_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 9e7deb65f6a95..456e16dba8935 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -78,4 +78,10 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # isystem: ship and use stdarg.h dnl # AC_KERNEL_CHECK_HEADERS([linux/stdarg.h]) + + dnl # + dnl # v5.0-1331-g7bf60c52e093 + dnl # dma-buf: add new dma_fence_chain container v7 + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-fence-chain.h]) ]) diff --git a/include/kcl/header/linux/dma-fence-chain.h b/include/kcl/header/linux/dma-fence-chain.h new file mode 100644 index 0000000000000..ff429da204f75 --- /dev/null +++ b/include/kcl/header/linux/dma-fence-chain.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__LINUX_DMA_FENCE_CHAIN_H_H_ +#define _KCL_HEADER__LINUX_DMA_FENCE_CHAIN_H_H_ + +#if defined(HAVE_LINUX_DMA_FENCE_CHAIN_H) +#include_next +#endif + +#endif From d98adbbe91b157d49cc820cf1b6562be3bef2a2a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Jan 2022 14:44:13 +0800 Subject: [PATCH 0672/2653] drm/amdkcl: wrap the code under macro HAVE_DRM_GEM_OBJECT_RESV Signed-off-by: Leslie Shi --- drivers/gpu/drm/scheduler/sched_main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c index 81ad40d9582bc..aa37d145e2dc7 100644 --- a/drivers/gpu/drm/scheduler/sched_main.c +++ b/drivers/gpu/drm/scheduler/sched_main.c @@ -956,6 +956,7 @@ int drm_sched_job_add_resv_dependencies(struct drm_sched_job *job, } EXPORT_SYMBOL(drm_sched_job_add_resv_dependencies); +#ifdef HAVE_DRM_GEM_OBJECT_RESV /** * drm_sched_job_add_implicit_dependencies - adds implicit dependencies as job * dependencies @@ -979,6 +980,7 @@ int drm_sched_job_add_implicit_dependencies(struct drm_sched_job *job, dma_resv_usage_rw(write)); } EXPORT_SYMBOL(drm_sched_job_add_implicit_dependencies); +#endif /** * drm_sched_job_has_dependency - check whether fence is the job's dependency From e616f7f8f5aee04b4ecfc10b85d70a7df8f50a4f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Jan 2022 16:36:08 +0800 Subject: [PATCH 0673/2653] drm/amdkcl: wrap the code under HAVE_STRUCT_XARRAY for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/scheduler/sched_entity.c | 7 +++++++ drivers/gpu/drm/scheduler/sched_main.c | 10 ++++++++-- include/drm/gpu_scheduler.h | 5 +++++ include/kcl/header/linux/xarray.h | 9 +++++++++ 4 files changed, 29 insertions(+), 2 deletions(-) create mode 100644 include/kcl/header/linux/xarray.h diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c index 8867b95ab089c..03fe677a4f129 100644 --- a/drivers/gpu/drm/scheduler/sched_entity.c +++ b/drivers/gpu/drm/scheduler/sched_entity.c @@ -453,6 +453,9 @@ drm_sched_job_dependency(struct drm_sched_job *job, struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity) { +#ifndef HAVE_STRUCT_XARRAY + struct drm_gpu_scheduler *sched = entity->rq->sched; +#endif struct drm_sched_job *sched_job; sched_job = drm_sched_entity_queue_peek(entity); @@ -460,7 +463,11 @@ struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity) return NULL; while ((entity->dependency = +#ifdef HAVE_STRUCT_XARRAY drm_sched_job_dependency(sched_job, entity))) { +#else + sched->ops->dependency(sched_job, entity))) { +#endif if (drm_sched_entity_add_dependency_cb(entity)) { trace_drm_sched_job_unschedulable(sched_job, entity->dependency); return NULL; diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c index aa37d145e2dc7..4a990cdd6a434 100644 --- a/drivers/gpu/drm/scheduler/sched_main.c +++ b/drivers/gpu/drm/scheduler/sched_main.c @@ -807,8 +807,9 @@ int drm_sched_job_init(struct drm_sched_job *job, return -ENOMEM; INIT_LIST_HEAD(&job->list); - +#ifdef HAVE_STRUCT_XARRAY xa_init_flags(&job->dependencies, XA_FLAGS_ALLOC); +#endif return 0; } @@ -847,6 +848,7 @@ void drm_sched_job_arm(struct drm_sched_job *job) } EXPORT_SYMBOL(drm_sched_job_arm); +#ifdef HAVE_STRUCT_XARRAY /** * drm_sched_job_add_dependency - adds the fence as a job dependency * @job: scheduler job to add the dependencies to @@ -1004,6 +1006,7 @@ bool drm_sched_job_has_dependency(struct drm_sched_job *job, return false; } EXPORT_SYMBOL(drm_sched_job_has_dependency); +#endif /* HAVE_STRUCR_XARRAY */ /** * drm_sched_job_cleanup - clean up scheduler job resources @@ -1023,8 +1026,10 @@ EXPORT_SYMBOL(drm_sched_job_has_dependency); */ void drm_sched_job_cleanup(struct drm_sched_job *job) { +#ifdef HAVE_STRUCT_XARRAY struct dma_fence *fence; unsigned long index; +#endif if (kref_read(&job->s_fence->finished.refcount)) { /* The job has been processed by the scheduler, i.e., @@ -1041,11 +1046,12 @@ void drm_sched_job_cleanup(struct drm_sched_job *job) job->s_fence = NULL; +#ifdef HAVE_STRUCT_XARRAY xa_for_each(&job->dependencies, index, fence) { dma_fence_put(fence); } xa_destroy(&job->dependencies); - +#endif } EXPORT_SYMBOL(drm_sched_job_cleanup); diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h index e62a7214e0521..daba51a67ad4c 100644 --- a/include/drm/gpu_scheduler.h +++ b/include/drm/gpu_scheduler.h @@ -359,8 +359,10 @@ struct drm_sched_job { enum drm_sched_priority s_priority; u32 credits; +#ifdef HAVE_STRUCT_XARRAY /** @last_dependency: tracks @dependencies as they signal */ unsigned int last_dependency; +#endif atomic_t karma; struct spsc_node queue_node; @@ -384,7 +386,9 @@ struct drm_sched_job { * drm_sched_job_add_dependency() and * drm_sched_job_add_implicit_dependencies(). */ +#ifdef HAVE_STRUCT_XARRAY struct xarray dependencies; +#endif }; /** @@ -637,6 +641,7 @@ int drm_sched_job_init(struct drm_sched_job *job, u64 drm_client_id); void drm_sched_job_arm(struct drm_sched_job *job); void drm_sched_entity_push_job(struct drm_sched_job *sched_job); + int drm_sched_job_add_dependency(struct drm_sched_job *job, struct dma_fence *fence); int drm_sched_job_add_syncobj_dependency(struct drm_sched_job *job, diff --git a/include/kcl/header/linux/xarray.h b/include/kcl/header/linux/xarray.h new file mode 100644 index 0000000000000..3df793f177365 --- /dev/null +++ b/include/kcl/header/linux/xarray.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _KCL_HEADER_LINUX_XARRAY_H_H +#define _KCL_HEADER_LINUX_XARRAY_H_H + +#ifdef HAVE_STRUCT_XARRAY +#include_next +#endif + +#endif From f4c8e303520f0369ab01a27dffb9acde3c27f382 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 19 Jan 2022 11:58:32 +0800 Subject: [PATCH 0674/2653] drm/amdkcl: add macro DP_PSR2_SU_X_GRANULARITY for legacy os Signed-off-by: Leslie Shi --- include/kcl/kcl_drm_dp_helper.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index ec52d89063426..10b162b5c4693 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -276,4 +276,16 @@ enum drm_dp_phy { # define DP_DPCD_REV_14 0x14 #endif +/* + * v4.20-rc3-897-g71b15621f097 + * drm: Add the PSR SU granularity registers offsets + */ +#ifndef DP_PSR2_SU_X_GRANULARITY +#define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */ +#endif +#ifndef DP_PSR2_SU_Y_GRANULARITY +#define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */ +#endif + + #endif /* _KCL_DRM_DP_HELPER_H_ */ From 30c46b769a767528baf44243f63e76da49a17d86 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 19 Jan 2022 15:35:09 +0800 Subject: [PATCH 0675/2653] drm/amdkcl: include kcl_kref.h for drm scheduler code Signed-off-by: Leslie Shi --- drivers/gpu/drm/scheduler/backport/backport.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 25460de490b35..3327879e06a15 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -8,5 +8,6 @@ #include #include #include +#include #endif From 07536efc2530b9ffe80a06be1933776369ffcd71 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 19 Jan 2022 15:59:05 +0800 Subject: [PATCH 0676/2653] drm/amdkcl: test whether __dma_fence_is_later() is available Signed-off-by: Leslie Shi --- .../gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 8 ++--- .../gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 | 30 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_fence.h | 35 +++++++++++++++++++ 5 files changed, 71 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c index 8ee9e8bf76779..d19d8b3733657 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c @@ -10,6 +10,7 @@ #if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) #include +#include #include static bool dma_fence_chain_enable_signaling(struct dma_fence *fence); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 224ce75be2c1c..fe769beac3a15 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1157,11 +1157,11 @@ /* zone_managed_pages() is available */ #define HAVE_ZONE_MANAGED_PAGES 1 -/* bitmap_free() is available */ -#define HAVE_BITMAP_FUNCS 1 +/* __dma_fence_is_later() is available and has 2 args */ +/* #undef HAVE__DMA_FENCE_IS_LATER_2ARGS */ -/* drm_edid_get_monitor_name is available*/ -#define HAVE_DRM_EDID_GET_MONITOR_NAME 1 +/* __dma_fence_is_later() is available and has ops arg */ +#define HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG 1 /* __drm_atomic_helper_connector_destroy_state() wants 1 arg */ #define HAVE___DRM_ATOMIC_HELPER_CONNECTOR_DESTROY_STATE_P 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 new file mode 100644 index 0000000000000..bbc3eb8117f9c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 @@ -0,0 +1,30 @@ +dnl # +dnl # v5.1-rc2-1115-g5e498abf1485 +dnl # dma-buf: explicitely note that dma-fence-chains use 64bit seqno +dnl # +AC_DEFUN([AC_AMDGPU__DMA_FENCE_IS_LATER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + const struct dma_fence_ops *ops = NULL; + __dma_fence_is_later(0, 0, ops); + ], [ + AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG, 1, + [__dma_fence_is_later() is available and has ops arg]) + ], [ + dnl # + dnl # v4.20-rc4-931-gb312d8ca3a7c + dnl # dma-buf: make fence sequence numbers 64 bit v2 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + __dma_fence_is_later(0, 0); + ], [ + AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_2ARGS, 1, + [__dma_fence_is_later() is available and has 2 args]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 06bbbf0401bce..014078d2952af 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -192,6 +192,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ + AC_AMDGPU__DMA_FENCE_IS_LATER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index ec9f6c83ab8da..addd6733ff680 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -46,6 +46,41 @@ #define dma_fence_set_error fence_set_error #endif +#if !defined(HAVE__DMA_FENCE_IS_LATER_2ARGS) + +#if !defined(HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO) +static inline bool __dma_fence_is_later(u64 f1, u64 f2) +{ + + /* This is for backward compatibility with drivers which can only handle + * 32bit sequence numbers. Use a 64bit compare when any of the higher + * bits are none zero, otherwise use a 32bit compare with wrap around + * handling. + */ + if (upper_32_bits(f1) || upper_32_bits(f2)) + return f1 > f2; + + return (int)(lower_32_bits(f1) - lower_32_bits(f2)) > 0; +} + +#elif !defined(HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG) && \ + defined(HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO) +static inline bool __dma_fence_is_later(u64 f1, u64 f2, + const struct dma_fence_ops *ops) +{ + /* This is for backward compatibility with drivers which can only handle + * 32bit sequence numbers. Use a 64bit compare when the driver says to + * do so. + */ + if (ops->use_64bit_seqno) + return f1 > f2; + + return (int)(lower_32_bits(f1) - lower_32_bits(f2)) > 0; +} + +#endif +#endif /* HAVE__DMA_FENCE_IS_LATER_2ARGS */ + /* commit v4.5-rc3-715-gb47bcb93bbf2 * fall back to HAVE_LINUX_DMA_FENCE_H check directly * as it's hard to detect the implementation in kernel From cc886c78f08d45ba425cefde8315e1cbe11aa18b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 19 Jan 2022 16:31:28 +0800 Subject: [PATCH 0677/2653] drm/amdkcl: test whether pci_irq_vector() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 | 16 ++++++++++++++++ include/kcl/kcl_pci.h | 9 +++++++++ 5 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a2ab4cd5687fb..0fc8065196bae 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -85,5 +85,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index fe769beac3a15..e99886fd8dc15 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -930,6 +930,9 @@ /* struct pci_driver has field dev_groups */ #define HAVE_PCI_DRIVER_DEV_GROUPS 1 +/* pci_irq_vector() is available */ +#define HAVE_PCI_IRQ_VECTOR 1 + /* pci_is_thunderbolt_attached() is available */ #define HAVE_PCI_IS_THUNDERBOLD_ATTACHED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 014078d2952af..be35bb2d51312 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -193,6 +193,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ AC_AMDGPU__DMA_FENCE_IS_LATER + AC_AMDGPU_PCI_IRQ_VECTOR AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 new file mode 100644 index 0000000000000..5567ed9920070 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v4.7-rc6-10-gaff171641d18 +dnl # PCI: Provide sensible IRQ vector alloc/free routines +dnl # +AC_DEFUN([AC_AMDGPU_PCI_IRQ_VECTOR], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pci_irq_vector(NULL, 0); + ], [ + AC_DEFINE(HAVE_PCI_IRQ_VECTOR, 1, + [pci_irq_vector() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index f10e5e5c84106..cf46e2db8d19b 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -241,4 +241,13 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) #endif /* PCI_REBAR_CTRL_BAR_SHIFT */ +#if !defined(HAVE_PCI_IRQ_VECTOR) +static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) +{ + if (WARN_ON_ONCE(nr > 0)) + return -EINVAL; + return dev->irq; +} +#endif /* HAVE_PCI_IRQ_VECTOR */ + #endif /* AMDKCL_PCI_H */ From dd20d4823077259b674475579f1d2e65171ff104 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 20 Jan 2022 10:43:24 +0800 Subject: [PATCH 0678/2653] drm/amdkcl: add macro DP_PSR2_SU_GRANULARITY_REQUIRED Signed-off-by: Leslie Shi --- include/kcl/kcl_drm_dp_helper.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 10b162b5c4693..f32ad22d172db 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -287,5 +287,15 @@ enum drm_dp_phy { #define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */ #endif +/* + * v4.10-rc3-483-gd0ce90629120 + * drm : adds Y-coordinate and Colorimetry Format + */ +#ifndef DP_PSR2_SU_Y_COORDINATE_REQUIRED +# define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */ +# define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ +#endif + + #endif /* _KCL_DRM_DP_HELPER_H_ */ From 6a8f880fb6ee7aba5648a30360899de6bdfb0866 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 20 Jan 2022 15:53:46 +0800 Subject: [PATCH 0679/2653] drm/amdkcl: test whether linux/xarray.h is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 7 +++++++ include/kcl/header/linux/xarray.h | 2 +- 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e99886fd8dc15..8404a1f3d9a83 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -864,6 +864,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_STDARG_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_XARRAY_H 1 + /* list_bulk_move_tail() is available */ #define HAVE_LIST_BULK_MOVE_TAIL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 456e16dba8935..8f7a4ca59147b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -84,4 +84,11 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # dma-buf: add new dma_fence_chain container v7 dnl # AC_KERNEL_CHECK_HEADERS([linux/dma-fence-chain.h]) + + + dnl # + dnl # v4.16-11455-gf6bb2a2c0b81 + dnl # xarray: add the xa_lock to the radix_tree_root + dnl # + AC_KERNEL_CHECK_HEADERS([linux/xarray.h]) ]) diff --git a/include/kcl/header/linux/xarray.h b/include/kcl/header/linux/xarray.h index 3df793f177365..80d73c2ed9065 100644 --- a/include/kcl/header/linux/xarray.h +++ b/include/kcl/header/linux/xarray.h @@ -2,7 +2,7 @@ #ifndef _KCL_HEADER_LINUX_XARRAY_H_H #define _KCL_HEADER_LINUX_XARRAY_H_H -#ifdef HAVE_STRUCT_XARRAY +#ifdef HAVE_LINUX_XARRAY_H #include_next #endif From 8007f4de387e6c611322ba768c2721744ee81c40 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 20 Dec 2021 22:44:06 -0500 Subject: [PATCH 0680/2653] drm/amdkcl: wrap drm_edid_get_monitor_name with macro HAVE_DRM_EDID_GET_MONITOR_NAME This patch will check if the drm_edid_get_monitor_name exist in the some old kernel to avoid build dependency failure. b5f640ae7a0 drm/amdgpu: use drm_edid_get_monitor_name() instead of duplicating the code v5.13-3120-gb5f640ae7a0a Signed-off-by: Perry Yuan Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8404a1f3d9a83..ea447693c38fd 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1169,6 +1169,9 @@ /* __dma_fence_is_later() is available and has ops arg */ #define HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG 1 +/* drm_edid_get_monitor_name is available*/ +#define HAVE_DRM_EDID_GET_MONITOR_NAME 1 + /* __drm_atomic_helper_connector_destroy_state() wants 1 arg */ #define HAVE___DRM_ATOMIC_HELPER_CONNECTOR_DESTROY_STATE_P 1 From 0acfb2c68f7372ec2f51dd13f57379ea5e138915 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 10 Feb 2022 11:01:46 +0800 Subject: [PATCH 0681/2653] drm/amdkcl: Test whether linux/container_of.h is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 7 ++++++- include/kcl/header/linux/container_of.h | 10 ++++++++++ 3 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 include/kcl/header/linux/container_of.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ea447693c38fd..7c7a43b69cb6d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -813,6 +813,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_COMPILER_ATTRIBUTES_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_CONTAINER_OF_H 1 + /* Define to 1 if you have the header file. */ /* #undef HAVE_LINUX_DMA_ATTRS_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 8f7a4ca59147b..0ea53ea27426d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -85,10 +85,15 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([linux/dma-fence-chain.h]) - dnl # dnl # v4.16-11455-gf6bb2a2c0b81 dnl # xarray: add the xa_lock to the radix_tree_root dnl # AC_KERNEL_CHECK_HEADERS([linux/xarray.h]) + + dnl # + dnl # v5.15-272-gd2a8ebbf8192 + dnl # kernel.h: split out container_of() and typeof_member() macros + dnl # + AC_KERNEL_CHECK_HEADERS([linux/container_of.h]) ]) diff --git a/include/kcl/header/linux/container_of.h b/include/kcl/header/linux/container_of.h new file mode 100644 index 0000000000000..cf1f8a85f216f --- /dev/null +++ b/include/kcl/header/linux/container_of.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_CONTAINER_OF_H_H +#define _KCL_HEADER_LINUX_CONTAINER_OF_H_H + +#if defined(HAVE_LINUX_CONTAINER_OF_H) +#include_next +#endif + +#endif + From d20b279bcaa89877944f94f012cd81acc80ec1b4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 10 Feb 2022 11:13:51 +0800 Subject: [PATCH 0682/2653] drm/amdkcl: Test whether linux/cc_platform.h is available It's caused by v6.7-rc3-802-g71ce046327cf drm/ttm: Make sure the mapped tt pages are decrypted when needed Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 + drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 ++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/header/linux/cc_platform.h | 10 +++ include/kcl/kcl_cc_platform.h | 66 ++++++++++++++++++++ 6 files changed, 87 insertions(+) create mode 100644 include/kcl/header/linux/cc_platform.h create mode 100644 include/kcl/kcl_cc_platform.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 0fc8065196bae..7e6a3520aa453 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -86,5 +86,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7c7a43b69cb6d..f4d2c57119971 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -810,6 +810,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_BITS_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_CC_PLATFORM_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_COMPILER_ATTRIBUTES_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 0ea53ea27426d..7b2aa10060569 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -96,4 +96,10 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # kernel.h: split out container_of() and typeof_member() macros dnl # AC_KERNEL_CHECK_HEADERS([linux/container_of.h]) + + dnl # + dnl # v5.15-rc4-2-g46b49b12f3fc + dnl # arch/cc: Introduce a function to check for confidential computing features + dnl # + AC_KERNEL_CHECK_HEADERS([linux/cc_platform.h]) ]) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index cc5ba307b7e10..1e6024331b9f1 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -20,5 +20,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/header/linux/cc_platform.h b/include/kcl/header/linux/cc_platform.h new file mode 100644 index 0000000000000..cea7cc0c28876 --- /dev/null +++ b/include/kcl/header/linux/cc_platform.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_CC_PLATFORM_H_H +#define _KCL_HEADER_LINUX_CC_PLATFORM_H_H + +#if defined(HAVE_LINUX_CC_PLATFORM_H) +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_cc_platform.h b/include/kcl/kcl_cc_platform.h new file mode 100644 index 0000000000000..8a2d455442e4f --- /dev/null +++ b/include/kcl/kcl_cc_platform.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Confidential Computing Platform Capability checks + * + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Author: Tom Lendacky + */ +#ifndef AMDKCL_CC_PLATFORM_H +#define AMDKCL_CC_PLATFORM_H + +#ifndef HAVE_LINUX_CC_PLATFORM_H +/** + * enum cc_attr - Confidential computing attributes + * + * These attributes represent confidential computing features that are + * currently active. + */ +enum cc_attr { + /** + * @CC_ATTR_MEM_ENCRYPT: Memory encryption is active + * + * The platform/OS is running with active memory encryption. This + * includes running either as a bare-metal system or a hypervisor + * and actively using memory encryption or as a guest/virtual machine + * and actively using memory encryption. + * + * Examples include SME, SEV and SEV-ES. + */ + CC_ATTR_MEM_ENCRYPT, + + /** + * @CC_ATTR_HOST_MEM_ENCRYPT: Host memory encryption is active + * + * The platform/OS is running as a bare-metal system or a hypervisor + * and actively using memory encryption. + * + * Examples include SME. + */ + CC_ATTR_HOST_MEM_ENCRYPT, + + /** + * @CC_ATTR_GUEST_MEM_ENCRYPT: Guest memory encryption is active + * + * The platform/OS is running as a guest/virtual machine and actively + * using memory encryption. + * + * Examples include SEV and SEV-ES. + */ + CC_ATTR_GUEST_MEM_ENCRYPT, + + /** + * @CC_ATTR_GUEST_STATE_ENCRYPT: Guest state encryption is active + * + * The platform/OS is running as a guest/virtual machine and actively + * using memory encryption and register state encryption. + * + * Examples include SEV-ES. + */ + CC_ATTR_GUEST_STATE_ENCRYPT, +}; + +static inline bool cc_platform_has(enum cc_attr attr) { return false; } + +#endif /* HAVE_LINUX_CC_PLATFORM_H */ +#endif From 0dcdec40a73baef420781399679911e33a2548d0 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 10 Feb 2022 13:22:14 +0800 Subject: [PATCH 0683/2653] drm/amdkcl: Test whether drm_firmware_drivers_only() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 ++- .../gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c | 25 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm_firmware_drivers_only.m4 | 16 ++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_drv.h | 4 +++ 6 files changed, 51 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index d18e0cbe51c9a..d268f4a39a272 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,7 +12,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ - kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o + kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ + kcl_drm_nomodeset.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c new file mode 100644 index 0000000000000..c60ce331ebb3a --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +#ifndef HAVE_DRM_FIRMWARE_DRIVERS_ONLY + +static bool drm_nomodeset; + +bool drm_firmware_drivers_only(void) +{ + return drm_nomodeset; +} +EXPORT_SYMBOL(drm_firmware_drivers_only); + +static int __init disable_modeset(char *str) +{ + drm_nomodeset = true; + + pr_warn("Booted with the nomodeset parameter. Only the system framebuffer will be available\n"); + + return 1; +} + +/* Disable kernel modesetting */ +__setup("nomodeset", disable_modeset); + +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f4d2c57119971..a48a321e53f5e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -518,6 +518,9 @@ /* drm_fb_helper_set_suspend_unlocked() is available */ #define HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED 1 +/* drm_firmware_drivers_only() is available */ +#define HAVE_DRM_FIRMWARE_DRIVERS_ONLY 1 + /* drm_format_info.block_w and rm_format_info.block_h is available */ #define HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 new file mode 100644 index 0000000000000..b390e877bece7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.16-rc1-268-g6a2d2ddf2c34 +dnl # drm: Move nomodeset kernel parameter to the DRM subsystem +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_firmware_drivers_only(); + ], [ + AC_DEFINE(HAVE_DRM_FIRMWARE_DRIVERS_ONLY, 1, + [drm_firmware_drivers_only() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index be35bb2d51312..e6b2f44cf8817 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -194,6 +194,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ AC_AMDGPU__DMA_FENCE_IS_LATER AC_AMDGPU_PCI_IRQ_VECTOR + AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_drv.h b/include/kcl/kcl_drm_drv.h index b4e923bfa1465..0360a07613727 100644 --- a/include/kcl/kcl_drm_drv.h +++ b/include/kcl/kcl_drm_drv.h @@ -63,4 +63,8 @@ static inline bool drm_dev_is_unplugged(struct drm_device *dev) #endif /* HAVE_DRM_DEV_IS_UNPLUGGED */ #endif /* HAVE_DRM_DEV_ENTER */ +#ifndef HAVE_DRM_FIRMWARE_DRIVERS_ONLY +extern bool drm_firmware_drivers_only(void); +#endif /* HAVE_DRM_FIRMWARE_DRIVERS_ONLY */ + #endif From cfd73a899b20eb671d54008e92c41c9d095010c2 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 10 Feb 2022 14:00:35 +0800 Subject: [PATCH 0684/2653] drm/amdkcl: Test whether dma_resv_describe() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/dma-fence-describe.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_fence.h | 4 ++++ 5 files changed, 43 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-describe.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index 1376705d31822..1969d6e0f289c 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -244,3 +244,21 @@ void amdkcl_fence_init(void) _kcl_fence_default_wait_cb = amdkcl_fp_setup("fence_default_wait_cb", NULL); #endif } + +#if !defined(HAVE_DMA_FENCE_DESCRIBE) +/** + * dma_fence_describe - Dump fence describtion into seq_file + * @fence: the 6fence to describe + * @seq: the seq_file to put the textual description into + * + * Dump a textual description of the fence and it's state into the seq_file. + */ +void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq) +{ + seq_printf(seq, "%s %s seq %llu %ssignalled\n", + fence->ops->get_driver_name(fence), + fence->ops->get_timeline_name(fence), fence->seqno, + dma_fence_is_signaled(fence) ? "" : "un"); +} +EXPORT_SYMBOL(dma_fence_describe); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a48a321e53f5e..7b584a3c027d1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -91,6 +91,9 @@ /* dma_fence_chain_alloc() is available */ #define HAVE_DMA_FENCE_CHAIN_ALLOC 1 +/* dma_fence_describe() is available */ +#define HAVE_DMA_FENCE_DESCRIBE 1 + /* whether dma_fence_get_stub exits */ #define HAVE_DMA_FENCE_GET_STUB 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-describe.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-describe.m4 new file mode 100644 index 0000000000000..e82d65e149645 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-describe.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.15-rc2-1312-ga25efb3863d0 +dnl # dma-buf: add dma_fence_describe and dma_resv_describe v2 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_DESCRIBE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_describe(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_DESCRIBE, 1, + [dma_fence_describe() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e6b2f44cf8817..028caba358a14 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -195,6 +195,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU__DMA_FENCE_IS_LATER AC_AMDGPU_PCI_IRQ_VECTOR AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY + AC_AMDGPU_DMA_FENCE_DESCRIBE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index addd6733ff680..e8adf7bef1c57 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -186,4 +186,8 @@ bool _kcl_fence_enable_signaling(struct dma_fence *f); #define AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL #endif +#if !defined(HAVE_DMA_FENCE_DESCRIBE) +void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq); +#endif + #endif /* AMDKCL_FENCE_H */ From b4f71e07f58ed94eb033ec2e3393f940f8eaf14b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 13 Jan 2022 12:39:35 +0800 Subject: [PATCH 0685/2653] drm/amdgpu: remove code access prime_shared_count field of struct amdgpu_bo commit "drm/amdgpu: rework dma_resv handling v3" removes the `prime_shared_count` field of struct amdgpu_bo Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 32 --------------------- 1 file changed, 32 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index f3e6465bec2e9..620b64b57b134 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -190,8 +190,6 @@ static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf, if (r) goto error_unreserve; - if (attach->dev->driver != adev->dev->driver) - bo->prime_shared_count++; error_unreserve: amdgpu_bo_unreserve(bo); @@ -223,8 +221,6 @@ static void amdgpu_dma_buf_map_detach(struct dma_buf *dma_buf, goto error; amdgpu_bo_unpin(bo); - if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count) - bo->prime_shared_count--; amdgpu_bo_unreserve(bo); error: @@ -276,25 +272,6 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, attach->peer2peer = false; #endif - r = amdgpu_bo_reserve(bo, false); - if (unlikely(r != 0)) - goto out; - - /* - * We only create shared fences for internal use, but importers - * of the dmabuf rely on exclusive fences for implicitly - * tracking write hazards. As any of the current fences may - * correspond to a write, we need to convert all existing - * fences on the reservation object into a single exclusive - * fence. - */ - r = __dma_resv_make_exclusive(amdkcl_ttm_resvp(&bo->tbo)); - if (r) - goto out; - - bo->prime_shared_count++; - amdgpu_bo_unreserve(bo); - amdgpu_vm_bo_update_shared(bo); return 0; @@ -659,11 +636,6 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, bo->tbo.ttm->sg = sg; bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; -#if defined(AMDKCL_AMDGPU_DMABUF_OPS) - if (attach->dmabuf->ops != &amdgpu_dmabuf_ops) -#endif - bo->prime_shared_count = 1; - dma_resv_unlock(resv); return &bo->tbo.base; @@ -907,8 +879,6 @@ int amdgpu_gem_prime_pin(struct drm_gem_object *obj) /* pin buffer into GTT */ ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); - if (likely(ret == 0)) - bo->prime_shared_count++; amdgpu_bo_unreserve(bo); return ret; @@ -924,8 +894,6 @@ void amdgpu_gem_prime_unpin(struct drm_gem_object *obj) return; amdgpu_bo_unpin(bo); - if (bo->prime_shared_count) - bo->prime_shared_count--; amdgpu_bo_unreserve(bo); } #endif From 8d9d6a28e293908779e5968ec0a03a28ce0da2e6 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 15 Feb 2022 13:11:56 +0800 Subject: [PATCH 0686/2653] drm/amdkcl: Test whether drm_sysfs_connector_hotplug_event() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c | 44 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../m4/drm-sysfs-connector-hotplug-event.m4 | 16 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_sysfs.h | 10 +++++ 7 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-sysfs-connector-hotplug-event.m4 create mode 100644 include/kcl/kcl_drm_sysfs.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index d268f4a39a272..30e4532c21b24 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_drm_nomodeset.o + kcl_drm_nomodeset.o kcl_drm_sysfs.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c new file mode 100644 index 0000000000000..5be759d09043b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/* + * drm_sysfs.c - Modifications to drm_sysfs_class.c to support + * extra sysfs attribute from DRM. Normal drm_sysfs_class + * does not allow adding attributes. + * + * Copyright (c) 2004 Jon Smirl + * Copyright (c) 2003-2004 Greg Kroah-Hartman + * Copyright (c) 2003-2004 IBM Corp. + */ +#include +#include +#include +#include +#include + +#ifndef HAVE_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT +/** + * drm_sysfs_connector_hotplug_event - generate a DRM uevent for any connector + * change + * @connector: connector which has changed + * + * Send a uevent for the DRM connector specified by @connector. This will send + * a uevent with the properties HOTPLUG=1 and CONNECTOR. + */ +void drm_sysfs_connector_hotplug_event(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + char hotplug_str[] = "HOTPLUG=1", conn_id[21]; + char *envp[] = { hotplug_str, conn_id, NULL }; + + snprintf(conn_id, sizeof(conn_id), + "CONNECTOR=%u", connector->base.id); + + drm_dbg_kms(connector->dev, + "[CONNECTOR:%d:%s] generating connector hotplug event\n", + connector->base.id, connector->name); + + kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, envp); +} +EXPORT_SYMBOL(drm_sysfs_connector_hotplug_event); + +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7e6a3520aa453..b8a8cb558937b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -87,5 +87,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7b584a3c027d1..b12a79b7f0b08 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -666,6 +666,9 @@ /* whether drm_syncobj_find_fence() wants 5 args */ #define HAVE_DRM_SYNCOBJ_FIND_FENCE_5ARGS 1 +/* drm_sysfs_connector_hotplug_event() function is available */ +#define HAVE_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-sysfs-connector-hotplug-event.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-sysfs-connector-hotplug-event.m4 new file mode 100644 index 0000000000000..3db7dabaf0b15 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-sysfs-connector-hotplug-event.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.15-rc2-1273-g0d6a8c5e9683 +dnl # drm/sysfs: introduce drm_sysfs_connector_hotplug_event +dnl # +AC_DEFUN([AC_AMDGPU_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_sysfs_connector_hotplug_event(NULL); + ], [ + AC_DEFINE(HAVE_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT, 1, + [drm_sysfs_connector_hotplug_event() function is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 028caba358a14..54460ac69c964 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -196,6 +196,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_IRQ_VECTOR AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY AC_AMDGPU_DMA_FENCE_DESCRIBE + AC_AMDGPU_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_sysfs.h b/include/kcl/kcl_drm_sysfs.h new file mode 100644 index 0000000000000..aaa27638d4659 --- /dev/null +++ b/include/kcl/kcl_drm_sysfs.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_DRM_SYSFS_H +#define AMDKCL_DRM_SYSFS_H + +struct drm_connector; +#ifndef HAVE_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT +void drm_sysfs_connector_hotplug_event(struct drm_connector *connector); +#endif + +#endif From de27e0c8862b2226b3df2cb6e1778eaf8328e135 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 15 Feb 2022 13:50:54 +0800 Subject: [PATCH 0687/2653] drm/amdkcl: Test whether drm_kms_helper_connector_hotplug_event() is available This is cause by fc320a6f64044f12128519ca98404b641340d136 "amdgpu: use drm_kms_helper_connector_hotplug_event" v5.15-rc2-1276-gfc320a6f6404 Signed-off-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 16 ++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 ++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-kms-helper-hotplug-event.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 44 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-kms-helper-hotplug-event.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 17b52812a429b..a14929b953c49 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3891,7 +3891,11 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) drm_modeset_unlock_all(dev); if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(dev); +#endif } else { scoped_guard(mutex, &adev->dm.dc_lock) { dc_exit_ips_for_hw_access(dc); @@ -3907,7 +3911,11 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) drm_modeset_unlock_all(dev); if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(dev); +#endif } } } @@ -4040,7 +4048,11 @@ static void handle_hpd_rx_irq(void *param) dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(dev); +#endif } else { bool ret = false; @@ -4059,7 +4071,11 @@ static void handle_hpd_rx_irq(void *param) dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(dev); +#endif } } } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index db4760745614c..1a1f37b3517e8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -1503,7 +1503,11 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(dev); +#endif } else if (param[0] == 0) { if (!aconnector->dc_link) goto unlock; @@ -1529,7 +1533,11 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(dev); +#endif } unlock: diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b12a79b7f0b08..d3bc537e20173 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -578,6 +578,9 @@ /* drm_is_current_master() is available */ #define HAVE_DRM_IS_CURRENT_MASTER 1 +/* drm_kms_helper_connector_hotplug_event() function is available */ +#define HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT 1 + /* drm_kms_helper_is_poll_worker() is available */ #define HAVE_DRM_KMS_HELPER_IS_POLL_WORKER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-kms-helper-hotplug-event.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-kms-helper-hotplug-event.m4 new file mode 100644 index 0000000000000..2bb2ec7fade6e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-kms-helper-hotplug-event.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.15-rc2-1274-g710074bb8ab0 +dnl # drm/probe-helper: add drm_kms_helper_connector_hotplug_event +dnl # +AC_DEFUN([AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_kms_helper_connector_hotplug_event(NULL); + ], [ + AC_DEFINE(HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT, 1, + [drm_kms_helper_connector_hotplug_event() function is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 54460ac69c964..0f5dd0b6fb884 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -197,6 +197,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY AC_AMDGPU_DMA_FENCE_DESCRIBE AC_AMDGPU_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT + AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From c703e2d16d60da4b491ff69d83b4395ad7d4cbdc Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 17 Feb 2022 10:50:25 +0800 Subject: [PATCH 0688/2653] drm/amdkcl: fake macro MODULE_IMPORT_NS for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_module.h | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 include/kcl/kcl_module.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b8a8cb558937b..b7a34ffd5527f 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -88,5 +88,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_module.h b/include/kcl/kcl_module.h new file mode 100644 index 0000000000000..2265f3bed4091 --- /dev/null +++ b/include/kcl/kcl_module.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Dynamic loading of modules into the kernel. + * + * Rewritten by Richard Henderson Dec 1996 + * Rewritten again by Rusty Russell, 2002 + */ +#ifndef _KCL_KCL_LINUX_MODULE_H_H +#define _KCL_KCL_LINUX_MODULE_H_H + +#include + +/* Copied from v5.3-11739-g3e4d890a26d5 include/linux/module.h */ +#ifndef MODULE_IMPORT_NS +#define MODULE_IMPORT_NS(ns) MODULE_INFO(import_ns, #ns) +#endif + +#endif From de030ebf75d71fb8248c04694a914760e8094366 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 17 Feb 2022 11:08:18 +0800 Subject: [PATCH 0689/2653] drm/amdkcl: wrap the code under HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE for legacy os This is caused by 5fea167ec0a13 "drm/amdkfd: use default_groups in kobj_type" v5.16-rc5-1299-g5fea167ec0a1 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 12 ++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 6 ++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 81b3443c8d7f4..f2f18fb422c3b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -873,7 +873,9 @@ static struct ip_hw_instance_attr ip_hw_attr[] = { }; static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(ip_hw_instance); +#endif #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) @@ -905,7 +907,11 @@ static void ip_hw_instance_release(struct kobject *kobj) static const struct kobj_type ip_hw_instance_ktype = { .release = ip_hw_instance_release, .sysfs_ops = &ip_hw_instance_sysfs_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = ip_hw_instance_groups, +#else + .default_attrs = ip_hw_instance_attrs, +#endif }; /* -------------------------------------------------- */ @@ -954,7 +960,9 @@ static struct attribute *ip_die_entry_attrs[] = { &num_ips_attr.attr, NULL, }; +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ +#endif #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) @@ -987,7 +995,11 @@ static const struct sysfs_ops ip_die_entry_sysfs_ops = { static const struct kobj_type ip_die_entry_ktype = { .release = ip_die_entry_release, .sysfs_ops = &ip_die_entry_sysfs_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = ip_die_entry_groups, +#else + .default_attrs = ip_die_entry_attrs, +#endif }; static const struct kobj_type die_kobj_ktype = { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index cfef0f7e30a6a..78788f0150b00 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -505,7 +505,9 @@ static struct attribute *procfs_queue_attrs[] = { &attr_queue_gpuid, NULL }; +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(procfs_queue); +#endif static const struct sysfs_ops procfs_queue_ops = { .show = kfd_procfs_queue_show, @@ -513,7 +515,11 @@ static const struct sysfs_ops procfs_queue_ops = { static const struct kobj_type procfs_queue_type = { .sysfs_ops = &procfs_queue_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = procfs_queue_groups, +#else + .default_attrs = procfs_queue_attrs, +#endif }; static const struct sysfs_ops procfs_stats_ops = { From cd51f339554fc221aca35dcc6b54875380c3c8cd Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 21 Feb 2022 15:08:07 +0800 Subject: [PATCH 0690/2653] drm/amdkcl: access resv field using amdkcl_ttm_resvp Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index dc3a4a4451e90..254987e8bf16f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1727,7 +1727,7 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, * If true, then return false as any KFD process needs all its BOs to * be resident to run successfully */ - dma_resv_for_each_fence(&resv_cursor, bo->base.resv, + dma_resv_for_each_fence(&resv_cursor, amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP, f) { if (amdkfd_fence_check_mm(f, current->mm) && !(place->flags & TTM_PL_FLAG_CONTIGUOUS)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index d2369164ee3c9..17b9401da68ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -462,7 +462,7 @@ void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, if (!amdgpu_vm_is_bo_always_valid(vm, bo)) return; - dma_resv_assert_held(vm->root.bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&vm->root.bo->tbo)); ttm_bo_set_bulk_move(&bo->tbo, &vm->lru_bulk_move); if (bo->tbo.type == ttm_bo_type_kernel && bo->parent) @@ -1770,7 +1770,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, if (!bo) return bo_va; - dma_resv_assert_held(bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&bo->tbo)); if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) { bo_va->is_xgmi = true; /* Power up XGMI if it can be potentially used */ @@ -2196,10 +2196,10 @@ void amdgpu_vm_bo_del(struct amdgpu_device *adev, struct amdgpu_vm *vm = bo_va->base.vm; struct amdgpu_vm_bo_base **base; - dma_resv_assert_held(vm->root.bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&vm->root.bo->tbo)); if (bo) { - dma_resv_assert_held(bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&bo->tbo)); if (amdgpu_vm_is_bo_always_valid(vm, bo)) ttm_bo_set_bulk_move(&bo->tbo, NULL); From d99b34f5dfa122fe913479337100687248b2ea7e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 21 Feb 2022 10:44:56 +0800 Subject: [PATCH 0691/2653] drm/amdkcl: replace with for_each_crtc_in_state for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a14929b953c49..863313910dadc 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12253,7 +12253,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; } +#if !defined(for_each_new_crtc_in_state) + for_each_crtc_in_state(state, crtc, new_crtc_state, i) { +#else for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { +#endif dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); if (dm_new_crtc_state->mpo_requested) drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc); From 1cdb80a104a430b48a880f1bd7313ef0f13aafee Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 21 Feb 2022 12:51:08 +0800 Subject: [PATCH 0692/2653] drm/amdgpu: remove code accessing excl field This is caused by fa78e367a249 "drm/amdgpu: stop getting excl fence separately" v5.15-rc2-1366-gfa78e367a249 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 6fc1cfef92962..62e56dafbb6f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -134,8 +134,6 @@ static void amdgpu_flip_work_func(struct work_struct *__work) int vpos, hpos, stat, min_udelay = 0; struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; - if (amdgpu_display_flip_handle_fence(work, &work->excl)) - return; for (i = 0; i < work->shared_count; ++i) if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) @@ -457,7 +455,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc, goto unreserve; } - r = dma_resv_get_fences(amdkcl_ttm_resvp(&new_abo->tbo), &work->excl, + r = dma_resv_get_fences(amdkcl_ttm_resvp(&new_abo->tbo), NULL, &work->shared_count, &work->shared); if (unlikely(r != 0)) { @@ -513,7 +511,6 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc, cleanup: amdgpu_bo_unref(&work->old_abo); - fence_put(work->excl); for (i = 0; i < work->shared_count; ++i) fence_put(work->shared[i]); kfree(work->shared); From 0809a63fd5136e3148e6a50acbc7c5abc1892a04 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 22 Feb 2022 17:16:40 +0800 Subject: [PATCH 0693/2653] drm/amdkcl: Test whether pcie_aspm_enabled() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/pcie-aspm-enabled.m4 | 16 ++++++++++++++++ 4 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pcie-aspm-enabled.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2359ea4e179b2..f2b2dad809c26 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1935,7 +1935,11 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev) return false; if (amdgpu_device_aspm_support_quirk(adev)) return false; +#ifdef HAVE_PCIE_ASPM_ENABLED return pcie_aspm_enabled(adev->pdev); +#else + return false; +#endif } /* if we get transitioned to only one device, take VGA back */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d3bc537e20173..f3023dbd85820 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -933,6 +933,9 @@ /* num_u32_u32 is available */ #define HAVE_MUL_U32_U32 1 +/* pcie_aspm_enabled() is available */ +#define HAVE_PCIE_ASPM_ENABLED 1 + /* pcie_bandwidth_available() is available */ #define HAVE_PCIE_BANDWIDTH_AVAILABLE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0f5dd0b6fb884..5cb4da134666d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -198,6 +198,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_DESCRIBE AC_AMDGPU_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT + AC_AMDGPU_PCIE_ASPM_ENABLED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/pcie-aspm-enabled.m4 b/drivers/gpu/drm/amd/dkms/m4/pcie-aspm-enabled.m4 new file mode 100644 index 0000000000000..32927a35d28f5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pcie-aspm-enabled.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.3-rc4-1-gaccd2dd72c8f +dnl # PCI/ASPM: Add pcie_aspm_enabled() +dnl # +AC_DEFUN([AC_AMDGPU_PCIE_ASPM_ENABLED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pcie_aspm_enabled(NULL); + ], [ + AC_DEFINE(HAVE_PCIE_ASPM_ENABLED, 1, + [pcie_aspm_enabled() is available]) + ]) + ]) +]) From b07bcf8a6beaefae2df64b4d295da55e8a3cf535 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 21 Feb 2022 16:24:22 +0800 Subject: [PATCH 0694/2653] drm/amdkcl: Implement drm_WARN_ONCE for older versions of kernel Implement drm_WARN_ONCE function for older versions of kernel Otherwise,there are compile errors. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I4c85aa289dad6577bf04e7d1a5069af833b7a641 --- include/kcl/kcl_drm_print.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index d92e4744fea4b..a7ef405b97cdc 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -93,6 +93,13 @@ void drm_mm_print(const struct drm_mm *mm, struct drm_printer *p) _DRM_PRINTK(_once, WARNING, fmt, ##__VA_ARGS__) #endif +#ifndef drm_WARN_ONCE +#define drm_WARN_ONCE(drm, condition, format, arg...) \ + WARN_ONCE(condition, "%s %s: " format, \ + dev_driver_string((drm)->dev), \ + dev_name((drm)->dev), ## arg) +#endif + #ifndef DRM_NOTE #define DRM_NOTE(fmt, ...) \ _DRM_PRINTK(, NOTICE, fmt, ##__VA_ARGS__) From feb9df389de24818c1a1c839a8b5c8dbd548047a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 23 Feb 2022 10:15:32 +0800 Subject: [PATCH 0695/2653] drm/amdkcl: Test whether linux/processor.h is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 ++++++ include/kcl/header/linux/processor.h | 10 ++++++++++ 3 files changed, 19 insertions(+) create mode 100644 include/kcl/header/linux/processor.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f3023dbd85820..4d5862b92bb59 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -870,6 +870,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PGTABLE_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_PROCESSOR_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_SCHED_MM_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 7b2aa10060569..203f810772d52 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -102,4 +102,10 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # arch/cc: Introduce a function to check for confidential computing features dnl # AC_KERNEL_CHECK_HEADERS([linux/cc_platform.h]) + + dnl # + dnl # v4.12-rc3-120-gfd851a3cdc19 + dnl # spin loop primitives for busy waiting + dnl # + AC_KERNEL_CHECK_HEADERS([linux/processor.h]) ]) diff --git a/include/kcl/header/linux/processor.h b/include/kcl/header/linux/processor.h new file mode 100644 index 0000000000000..873ab8368cb12 --- /dev/null +++ b/include/kcl/header/linux/processor.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_PROCESSOR_H_H +#define _KCL_HEADER_LINUX_PROCESSOR_H_H + +#if defined(HAVE_LINUX_PROCESSOR_H) +#include_next +#endif + +#endif + From d3e3ccc1e93dcfc16b77436201dd63c73829d551 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 11 Feb 2022 11:01:14 +0800 Subject: [PATCH 0696/2653] drm/amdkfd: add removed amdgpu_amdkfd_get_vram_usage() function This is removed by v5.16-rc5-1294-gffb378fb3069 "drm/amdkfd: remove unused function" Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 1ece28c83485e..e335cafca639a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -580,6 +580,12 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, return r; } +uint64_t amdgpu_amdkfd_get_vram_usage(struct amdgpu_device *adev) +{ + + return amdgpu_vram_mgr_usage(&adev->mman.vram_mgr); +} + int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min) { int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) : diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 996685cf00dc4..aea41b8397420 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -260,6 +260,7 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, uint64_t *bo_size, void *metadata_buffer, size_t buffer_size, uint32_t *metadata_size, uint32_t *flags, int8_t *xcp_id); +uint64_t amdgpu_amdkfd_get_vram_usage(struct amdgpu_device *adev); int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min); int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, uint32_t *payload); From 79284eb1139a2ba7b652f3ef83e19bc0fdcf33fe Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 9 Feb 2022 17:07:22 -0600 Subject: [PATCH 0697/2653] drm/amdkfd: Protect BO during acquisition of its IPC handle Ensure the process of acquiring IPC handle of a BO is safe i.e. BO is not exposed from being destroyed. This is done by serializing user accesses to BO's of a process Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index c1f5f7dc6c5d7..1e3d9af012651 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -241,30 +241,33 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, if (!dev || !ipc_handle) return -EINVAL; + /* Protect kgd_mem object from being deleted by another thread */ mutex_lock(&p->mutex); pdd = kfd_bind_process_to_device(dev, p); if (IS_ERR(pdd)) { - mutex_unlock(&p->mutex); pr_err("Failed to get pdd\n"); - return PTR_ERR(pdd); + r = PTR_ERR(pdd); + goto unlock; } kfd_bo = kfd_process_device_find_bo(pdd, GET_IDR_HANDLE(handle)); - mutex_unlock(&p->mutex); if (!kfd_bo) { pr_err("Failed to get bo"); - return -EINVAL; + r = -EINVAL; + goto unlock; } mem = (struct kgd_mem *)kfd_bo->mem; r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->adev, pdd->drm_priv, mem, &ipc_obj, flags); if (r) - return r; + goto unlock; memcpy(ipc_handle, ipc_obj->share_handle, sizeof(ipc_obj->share_handle)); +unlock: + mutex_unlock(&p->mutex); return r; } From f9c1ad2669a16f5cf2ef773a2ce1903873f013b7 Mon Sep 17 00:00:00 2001 From: Rui Teng Date: Mon, 28 Feb 2022 16:08:43 +0800 Subject: [PATCH 0698/2653] drm/amdkcl: Bump AMDGPU version to 5.16.0 Signed-off-by: Rui Teng Change-Id: I708952a593cbd3205227c065e98f4fee4add4a01 --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 71855ccd6e523..3feca735c2140 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 5.13.5) +AC_INIT(amdgpu-dkms, 5.16.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 642183d098fe7d71b0a00a163f0c7b9785995396 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 7 Feb 2022 16:34:52 +0800 Subject: [PATCH 0699/2653] drm/amdkcl: rework drm_aperture_remove_conflicting_pci_framebuffers() Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 153 ++---------------- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 70 +++----- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h | 38 +++++ drivers/gpu/drm/amd/dkms/config/config.h | 22 +-- ...per-remove-conflicting-pci-framebuffers.m4 | 57 ------- ...ure_remove_conflicting_pci_framebuffers.m4 | 38 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- .../m4/remove-conflicting-pci-framebuffers.m4 | 28 ---- include/kcl/backport/kcl_drm_fb.h | 4 - include/kcl/kcl_drm_aperture.h | 8 - include/kcl/kcl_drm_fb.h | 57 ------- 11 files changed, 118 insertions(+), 360 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c index c597046dee062..91f2508079ff1 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -3,153 +3,28 @@ #ifndef HAVE_DRM_DRM_APERTURE_H #include -#include #include -#include -#include -#include - -struct drm_aperture { - struct drm_device *dev; - resource_size_t base; - resource_size_t size; - struct list_head lh; - void (*detach)(struct drm_device *dev); -}; - -static LIST_HEAD(drm_apertures); -static DEFINE_MUTEX(drm_apertures_lock); - -static bool overlap(resource_size_t base1, resource_size_t end1, - resource_size_t base2, resource_size_t end2) -{ - return (base1 < end2) && (end1 > base2); -} - - -static void drm_aperture_detach_drivers(resource_size_t base, resource_size_t size) -{ - resource_size_t end = base + size; - struct list_head *pos, *n; - - mutex_lock(&drm_apertures_lock); - list_for_each_safe(pos, n, &drm_apertures) { - struct drm_aperture *ap = - container_of(pos, struct drm_aperture, lh); - struct drm_device *dev = ap->dev; - - if (WARN_ON_ONCE(!dev)) - continue; - - if (!overlap(base, end, ap->base, ap->base + ap->size)) - continue; - - ap->dev = NULL; /* detach from device */ - list_del(&ap->lh); - - ap->detach(dev); - } - - mutex_unlock(&drm_apertures_lock); -} - - -/** - * drm_aperture_remove_conflicting_framebuffers - remove existing framebuffers in the given range - * @base: the aperture's base address in physical memory - * @size: aperture size in bytes - * @primary: also kick vga16fb if present - * @name: requesting driver name - * - * This function removes graphics device drivers which use memory range described by - * @base and @size. - * - * Returns: - * 0 on success, or a negative errno code otherwise - */ -int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size, - bool primary, const char *name) -{ -#if IS_REACHABLE(CONFIG_FB) - struct apertures_struct *a; - int ret; - - a = alloc_apertures(1); - if (!a) - return -ENOMEM; - - a->ranges[0].base = base; - a->ranges[0].size = size; - - ret = remove_conflicting_framebuffers(a, name, primary); - kfree(a); - - if (ret) - return ret; -#endif - - drm_aperture_detach_drivers(base, size); - - return 0; -} -EXPORT_SYMBOL(drm_aperture_remove_conflicting_framebuffers); +#include +#include +#include "kcl_fbmem.h" -/** - * drm_aperture_remove_conflicting_pci_framebuffers - remove existing framebuffers for PCI devices - * @pdev: PCI device - * @name: requesting driver name - * - * This function removes graphics device drivers using memory range configured - * for any of @pdev's memory bars. The function assumes that PCI device with - * shadowed ROM drives a primary display and so kicks out vga16fb. - * - * Returns: - * 0 on success, or a negative errno code otherwise - */ -#ifdef HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG -int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, - const struct drm_driver *req_driver) -#else int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) -#endif { - resource_size_t base, size; - int bar, ret = 0; + int ret = 0; - for (bar = 0; bar < PCI_STD_NUM_BARS; ++bar) { - if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) - continue; - base = pci_resource_start(pdev, bar); - size = pci_resource_len(pdev, bar); - drm_aperture_detach_drivers(base, size); - } - - /* - * WARNING: Apparently we must kick fbdev drivers before vgacon, - * otherwise the vga fbdev driver falls over. - */ - -#ifdef HAVE_VGA_REMOVE_VGACON + /* + * WARNING: Apparently we must kick fbdev drivers before vgacon, + * otherwise the vga fbdev driver falls over. + */ #if IS_REACHABLE(CONFIG_FB) - -#ifdef HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG - ret = remove_conflicting_pci_framebuffers(pdev, req_driver->name); -#else -#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG - ret = remove_conflicting_pci_framebuffers(pdev, name); -#else - ret = remove_conflicting_pci_framebuffers(pdev, 0, name); + ret = _kcl_remove_conflicting_pci_framebuffers(pdev, name); #endif -#endif /* HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG */ - -#endif - if (ret == 0) - ret = vga_remove_vgacon(pdev); +#ifdef HAVE_VGA_REMOVE_VGACON + if (ret == 0) + ret = vga_remove_vgacon(pdev); #endif - - return ret; + return ret; } EXPORT_SYMBOL(drm_aperture_remove_conflicting_pci_framebuffers); - -#endif /* HAVE_DRM_APERTURE_H */ +#endif /* HAVE_DRM_DRM_APERTURE_H */ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c index 742edcc32b042..eae1bf4134541 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -14,71 +14,43 @@ #include /* Copied from drivers/video/fbdev/core/fbmem.c and modified for KCL */ -#if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) - -#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG +#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) -{ - struct apertures_struct *ap; - bool primary = false; - int err, idx, bar; - - for (idx = 0, bar = 0; bar < PCI_STD_NUM_BARS; bar++) { - if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) - continue; - idx++; - } - - ap = alloc_apertures(idx); - if (!ap) - return -ENOMEM; - - for (idx = 0, bar = 0; bar < PCI_STD_NUM_BARS; bar++) { - if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) - continue; - ap->ranges[idx].base = pci_resource_start(pdev, bar); - ap->ranges[idx].size = pci_resource_len(pdev, bar); - pci_dbg(pdev, "%s: bar %d: 0x%lx -> 0x%lx\n", __func__, bar, - (unsigned long)pci_resource_start(pdev, bar), - (unsigned long)pci_resource_end(pdev, bar)); - idx++; - } - -#ifdef CONFIG_X86 - primary = pdev->resource[PCI_ROM_RESOURCE].flags & - IORESOURCE_ROM_SHADOW; -#endif - err = remove_conflicting_framebuffers(ap, name, primary); - kfree(ap); - return err; -} -#else /* HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG */ -int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const char *name) { struct apertures_struct *ap; bool primary = false; - int err = 0; + int err, idx, bar; + + for (idx = 0, bar = 0; bar < PCI_ROM_RESOURCE; bar++) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + idx++; + } - ap = alloc_apertures(1); + ap = alloc_apertures(idx); if (!ap) return -ENOMEM; - ap->ranges[0].base = pci_resource_start(pdev, res_id); - ap->ranges[0].size = pci_resource_len(pdev, res_id); + for (idx = 0, bar = 0; bar < PCI_ROM_RESOURCE; bar++) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + ap->ranges[idx].base = pci_resource_start(pdev, bar); + ap->ranges[idx].size = pci_resource_len(pdev, bar); + dev_dbg(&pdev->dev, "%s: bar %d: 0x%lx -> 0x%lx\n", __func__, bar, + (unsigned long)pci_resource_start(pdev, bar), + (unsigned long)pci_resource_end(pdev, bar)); + idx++; + } + #ifdef CONFIG_X86 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; #endif -#ifdef HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT err = remove_conflicting_framebuffers(ap, name, primary); -#else - remove_conflicting_framebuffers(ap, name, primary); -#endif kfree(ap); return err; } -#endif /* HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG */ - +EXPORT_SYMBOL(remove_conflicting_pci_framebuffers); #endif #ifndef HAVE_IS_FIRMWARE_FRAMEBUFFER diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h new file mode 100644 index 0000000000000..de4bdea92fa7f --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _AMDKCL_KCL_FBMEM_H_ +#define _AMDKCL_KCL_FBMEM_H_ + +#include +#include + +/* Copied from include/linux/fb.h */ +#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) +extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const char *name); +#endif +static inline +int _kcl_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const char *name) +{ +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP + /** + * v5.1-rc3-20-gb0e999c95581 fbdev: list all pci memory bars as conflicting apertures + * handle bar 0 directly. + * as remove_conflicting_pci_framebuffers() for bar 2/5 fails on rhel7.9 + int bar, err; + + for (bar = 0; bar < PCI_ROM_RESOURCE; bar++) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + err = remove_conflicting_pci_framebuffers(pdev, bar, name); + if (err) + return err; + } + */ + pr_warn_once("remove conflicting pci framebuffers on bar 0\n"); + return remove_conflicting_pci_framebuffers(pdev, 0, name); +#else + return remove_conflicting_pci_framebuffers(pdev, name); +#endif +} +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4d5862b92bb59..c9d73d317b8d2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -509,15 +509,6 @@ /* whether drm_fb_helper_lastclose() is available */ #define HAVE_DRM_FB_HELPER_LASTCLOSE 1 -/* drm_fb_helper_remove_conflicting_pci_framebuffers() is available */ -/* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ - -/* drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args */ -/* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP */ - -/* drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args */ -/* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ - /* drm_fb_helper_set_suspend_unlocked() is available */ #define HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED 1 @@ -990,15 +981,14 @@ /* pxm_to_node() is available */ #define HAVE_PXM_TO_NODE 1 -/* remove_conflicting_framebuffers() returns int */ -#define HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT 1 +/* remove_conflicting_pci_framebuffers() is available */ +/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ -/* remove_conflicting_pci_framebuffers() is available and doesn't have res_id - arg */ -#define HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG 1 +/* remove_conflicting_pci_framebuffers() wants p,i,p args */ +/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP */ -/* remove_conflicting_pci_framebuffers() is available and has res_id arg */ -/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_WITH_RES_ID_ARG */ +/* remove_conflicting_pci_framebuffers() wants p,p args */ +/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ /* request_firmware_direct() is available */ #define HAVE_REQUEST_FIRMWARE_DIRECT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 deleted file mode 100644 index ee6e915098f5c..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 +++ /dev/null @@ -1,57 +0,0 @@ -dnl # -dnl # commit v5.3-rc1-541-g35616a4aa919 -dnl # fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers -dnl # -AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; - #include - #endif - #include - ], [ - drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, NULL); - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args]) - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) - ], [ - dnl # - dnl # commit v4.19-rc1-110-g4d18975c78f2 - dnl # Author: Michał Mirosław - dnl # Date: Sat Sep 1 16:08:45 2018 +0200 - dnl # fbdev: add remove_conflicting_pci_framebuffers() - dnl # - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; - #include - #endif - #include - ], [ - drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, 0, NULL); - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args]) - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) - ], [ - dnl # - dnl # commit 46eeb2c144956e88197439b5ee5cf221a91b0a81 - dnl # video/fb: Propagate error code from failing to unregister conflicting fb - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - struct task_struct; - #include - ], [ - int ret = remove_conflicting_framebuffers(NULL, NULL, false); - ], [remove_conflicting_framebuffers], [drivers/video/fbdev/core/fbmem.c], [ - AC_DEFINE(HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT, 1, - [remove_conflicting_framebuffers() returns int]) - ]) - ]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 new file mode 100644 index 0000000000000..50e28229344bf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 @@ -0,0 +1,38 @@ +dnl # +dnl # v5.12-rc3-332-g603dc7ed917f drm/aperture: Inline fbdev conflict helpers into aperture helpers +dnl # v5.12-rc3-330-g2916059147ea drm/aperture: Add infrastructure for aperture ownership +dnl # +AC_DEFUN([AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ + AC_KERNEL_DO_BACKGROUND([ + AS_IF([test x$HAVE_DRM_DRM_APERTURE_H = x ], [ + dnl # + dnl # v5.3-rc1-540-g0a8459693238 fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + remove_conflicting_pci_framebuffers(NULL, NULL); + ], [ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, + [remove_conflicting_pci_framebuffers() wants p,p args]) + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, + [remove_conflicting_pci_framebuffers() is available]) + ], [ + dnl # + dnl # v4.19-rc1-110-g4d18975c78f2 fbdev: add remove_conflicting_pci_framebuffers() + dnl # + AC_KERNEL_TRY_COMPILE([ + struct task_struct; + #include + ], [ + remove_conflicting_pci_framebuffers(NULL, 0, NULL); + ], [ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP, 1, + [remove_conflicting_pci_framebuffers() wants p,i,p args]) + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, + [remove_conflicting_pci_framebuffers() is available]) + ]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5cb4da134666d..c24918aa4db15 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -72,7 +72,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED - AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS + AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_CALC_PBN_MODE AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS @@ -163,7 +163,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA - AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_DEV_ENTER AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_AMDGPU_DRM_DEVICE_PDEV diff --git a/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 deleted file mode 100644 index bde011042303f..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 +++ /dev/null @@ -1,28 +0,0 @@ -dnl # -dnl # v5.3-rc1-540-g0a8459693238 -dnl # fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers -dnl # -AC_DEFUN([AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - struct task_struct; - #include - ],[ - remove_conflicting_pci_framebuffers(NULL, NULL); - ],[ - AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG, 1, - [remove_conflicting_pci_framebuffers() is available and doesn't have res_id arg]) - ],[ - AC_KERNEL_TRY_COMPILE([ - struct task_struct; - #include - ], [ - remove_conflicting_pci_framebuffers(NULL, 0, NULL); - ], [ - AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_WITH_RES_ID_ARG, 1, - [remove_conflicting_pci_framebuffers() is available and has res_id arg]) - ]) - ]) - ]) -]) - diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index 662d312577d93..f1d242ac9d61f 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -25,10 +25,6 @@ #include #include -#if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP) -#define drm_fb_helper_remove_conflicting_pci_framebuffers _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers -#endif - #ifndef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV static inline void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, diff --git a/include/kcl/kcl_drm_aperture.h b/include/kcl/kcl_drm_aperture.h index e1af88ce1ba85..d4ca18d5c1792 100644 --- a/include/kcl/kcl_drm_aperture.h +++ b/include/kcl/kcl_drm_aperture.h @@ -6,18 +6,10 @@ #include -/* Copied from uapi/linux/pci_regs.h */ -#ifndef PCI_STD_NUM_BARS -#define PCI_STD_NUM_BARS 6 -#endif - /* Copied from drm/drm_aperture.h */ struct drm_device; struct pci_dev; -int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size, - bool primary, const char *name); - int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name); #endif /* HAVE_DRM_DRM_APERTURE_H */ diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 56361a8b43ebd..392638c78018c 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -55,63 +55,6 @@ .fb_pan_display = drm_fb_helper_pan_display #endif -#if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) -#if !defined(IS_REACHABLE) -/* Copied from include/linux/kconfig.h */ -#define __ARG_PLACEHOLDER_1 0, -#define __take_second_arg(__ignored, val, ...) val - -/* - * The use of "&&" / "||" is limited in certain expressions. - * The followings enable to calculate "and" / "or" with macro expansion only. - */ -#define __and(x, y) ___and(x, y) -#define ___and(x, y) ____and(__ARG_PLACEHOLDER_##x, y) -#define ____and(arg1_or_junk, y) __take_second_arg(arg1_or_junk y, 0) - -#define __or(x, y) ___or(x, y) -#define ___or(x, y) ____or(__ARG_PLACEHOLDER_##x, y) -#define ____or(arg1_or_junk, y) __take_second_arg(arg1_or_junk 1, y) - -#define IS_REACHABLE(option) __or(IS_BUILTIN(option), \ - __and(IS_MODULE(option), __is_defined(MODULE))) -#endif /*IS_REACHABLE*/ - -#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG -extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, - const char *name); -#else -extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, - const char *name); -#endif - -static inline int -_kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, - const char *name) -{ -#if IS_REACHABLE(CONFIG_FB) -#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG - return remove_conflicting_pci_framebuffers(pdev, name); -#else - return remove_conflicting_pci_framebuffers(pdev, 0, name); -#endif -#else - return 0; -#endif -} -#elif !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP) -static inline int -_kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, - const char *name) -{ -#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_WITH_RES_ID_ARG - return drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, name); -#else - return drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, name); -#endif -} -#endif /* HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ - #ifndef HAVE_DRM_FB_HELPER_FILL_INFO void drm_fb_helper_fill_info(struct fb_info *info, struct drm_fb_helper *fb_helper, From 24f57deaa132cf044d8264282d9b9e042616b0fc Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 22 Feb 2022 19:24:56 +0800 Subject: [PATCH 0700/2653] drm/amdkcl: fix kcl implementation for remove_conflicting_pci_framebuffers Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 3 ++- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c index eae1bf4134541..ce1cdaad500a0 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -14,7 +14,8 @@ #include /* Copied from drivers/video/fbdev/core/fbmem.c and modified for KCL */ -#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) +#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) && \ + !defined(HAVE_DRM_DRM_APERTURE_H) int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) { struct apertures_struct *ap; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h index de4bdea92fa7f..b734ca7c3d36a 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h @@ -6,7 +6,8 @@ #include /* Copied from include/linux/fb.h */ -#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) +#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) && \ + !defined(HAVE_DRM_DRM_APERTURE_H) extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name); #endif From 9d21b2ef222bccf66901c3479105e4d05e3f4ea2 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Feb 2022 18:44:26 +0800 Subject: [PATCH 0701/2653] drm/amdkcl: Add the PSR related macro definition Add DP_PSR2_SU_Y_GRANULARITY definition for older versions of kernel Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I3badfeb16886544c2548597e2f1eb085e58e7c5d --- include/kcl/kcl_drm_dp_helper.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index f32ad22d172db..60b18feee18f4 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -296,6 +296,4 @@ enum drm_dp_phy { # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ #endif - - #endif /* _KCL_DRM_DP_HELPER_H_ */ From 5af38e4745bb5a38e1de6e2579d4a834917248a7 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 2 Mar 2022 14:59:11 +0800 Subject: [PATCH 0702/2653] drm/amdkcl: drm/amd/display: Use adjusted DCN301 watermarks the patch was not applied completely in the rebase. Original patch is 808643ea56a2 - drm/amd/display: Use adjusted DCN301 watermarks Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- .../gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index dd77e91df3493..eeb3794dcd09f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -1395,7 +1395,7 @@ static struct resource_funcs dcn301_res_pool_funcs = { .link_enc_create = dcn301_link_encoder_create, .panel_cntl_create = dcn301_panel_cntl_create, .validate_bandwidth = dcn30_validate_bandwidth, - .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, + .calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg, .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, From f917cbf4258b8625611138191177156a7c38f59d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 2 Mar 2022 15:55:07 +0800 Subject: [PATCH 0703/2653] drm/amdkcl: undef REG_SET/REG_GET in display part fix warning for REG_SET/REG_GET redefined in display/dmub part Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h index 123d1704670ee..b314e60714ee2 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h @@ -28,6 +28,14 @@ #include "../inc/dmub_cmd.h" +#ifdef REG_SET +#undef REG_SET +#endif + +#ifdef REG_GET +#undef REG_GET +#endif + struct dmub_srv; /* Register offset and field lookup. */ From 07edd22b486f979085a08c41c1d9308ce4a685ea Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 2 Mar 2022 13:55:12 +0800 Subject: [PATCH 0704/2653] drm/amdkcl: move __dma_resv_make_exclusive near to its caller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix warning: ‘__dma_resv_make_exclusive’ defined but not used [-Wunused-function] Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 620b64b57b134..4baa8ccd74e2f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -92,6 +92,7 @@ int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, #endif #if defined(AMDKCL_AMDGPU_DMABUF_OPS) +#if defined(HAVE_DMA_BUF_OPS_LEGACY) static int __dma_resv_make_exclusive(struct dma_resv *obj) { @@ -134,7 +135,6 @@ __dma_resv_make_exclusive(struct dma_resv *obj) return -ENOMEM; } -#if defined(HAVE_DMA_BUF_OPS_LEGACY) /** * amdgpu_dma_buf_map_attach - &dma_buf_ops.attach implementation * @dma_buf: Shared DMA buffer From 2a1f746f95dc167ba45d2687f9f4fb4d042da334 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 2 Mar 2022 14:19:08 +0800 Subject: [PATCH 0705/2653] drm/amdkcl: fix warning in amdgpu_ras.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:133:13: warning: ‘amdgpu_register_bad_pages_mca_notifier’ declared ‘static’ but never defined [-Wunused-function] 133 | static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:138:38: warning: ‘mce_adev_list’ defined but not used [-Wunused-variable] 138 | static struct mce_notifier_adev_list mce_adev_list; | ^~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:44:13: warning: ‘notifier_registered’ defined but not used [-Wunused-variable] 44 | static bool notifier_registered; | ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index fd29658eee798..f2d7a253fd038 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -45,8 +45,10 @@ #ifdef CONFIG_X86_MCE_AMD #include +#ifdef HAVE_SMCA_UMC_V2 static bool notifier_registered; #endif +#endif static const char *RAS_FS_NAME = "ras"; const char *ras_error_string[] = { @@ -131,11 +133,6 @@ const char *get_ras_block_str(struct ras_common_if *ras_block) #define BYPASS_ALLOCATED_ADDRESS 0x0 #define BYPASS_INITIALIZATION_ADDRESS 0x1 -#ifdef HAVE_SMCA_UMC_V2 -static bool notifier_registered = false; -static void amdgpu_register_bad_pages_mca_notifier(void); -#endif - enum amdgpu_ras_retire_page_reservation { AMDGPU_RAS_RETIRE_PAGE_RESERVED, AMDGPU_RAS_RETIRE_PAGE_PENDING, @@ -153,6 +150,7 @@ static void amdgpu_ras_critical_region_init(struct amdgpu_device *adev); static void amdgpu_ras_critical_region_fini(struct amdgpu_device *adev); #ifdef CONFIG_X86_MCE_AMD +#ifdef HAVE_SMCA_UMC_V2 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev); struct mce_notifier_adev_list { struct amdgpu_device *devs[MAX_GPU_INSTANCE]; @@ -160,6 +158,7 @@ struct mce_notifier_adev_list { }; static struct mce_notifier_adev_list mce_adev_list; #endif +#endif void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) { From cab82c7c149918fbce01979b65cbd14649d99651 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 2 Mar 2022 14:24:50 +0800 Subject: [PATCH 0706/2653] drm/amdkcl: drop unused var in amdgpu_vkms_vblank_simulate MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c: In function ‘amdgpu_vkms_vblank_simulate’: drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c:48:24: warning: unused variable ‘adev’ [-Wunused-variable] 48 | struct amdgpu_device *adev = drm_to_adev(crtc->dev); | ^~~~ Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index b30f83aa53f00..317bb51569188 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -47,7 +47,6 @@ static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer) { struct amdgpu_crtc *amdgpu_crtc = container_of(timer, struct amdgpu_crtc, vblank_timer); struct drm_crtc *crtc = &amdgpu_crtc->base; - struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc); u64 ret_overrun; bool ret; From ea3ad97e707be555c5867a64989f68235c7540bf Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 2 Mar 2022 15:53:44 +0800 Subject: [PATCH 0707/2653] drm/amdkcl: fix warning in amdgpu_display_get_fb_info MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:1153:44: warning: passing argument 1 of ‘drm_gem_fb_get_obj’ discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] 1153 | rbo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&amdgpu_fb->base, 0)); Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 62e56dafbb6f9..8406fbbd364bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1405,7 +1405,7 @@ static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb return 0; } - rbo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&amdgpu_fb->base, 0)); + rbo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&((struct amdgpu_framebuffer *)amdgpu_fb)->base, 0)); r = amdgpu_bo_reserve(rbo, false); if (unlikely(r)) { From ff9476b890485f90cc8563843ce25dfce883c92c Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 1 Mar 2022 16:24:54 -0500 Subject: [PATCH 0708/2653] drm/amdkfd: Fixup rebase errors in CRIU code Signed-off-by: Felix Kuehling Acked-by: Guchun Chen Reviewed-and-tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 14 +++++++------- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 9 +++++++-- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 18 ------------------ 5 files changed, 17 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index a9387f1af52ed..9a314f930e784 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1187,7 +1187,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); idr_handle = kfd_process_device_create_obj_handle(pdd, mem, - args->va_addr, args->size, cpuva, mem_type); + args->va_addr, args->size, cpuva, mem_type, -1); if (idr_handle < 0) { err = -EFAULT; goto err_free; @@ -1927,11 +1927,11 @@ static uint32_t get_process_num_bos(struct kfd_process *p) /* Run over all PDDs of the process */ for (i = 0; i < p->n_pdds; i++) { struct kfd_process_device *pdd = p->pdds[i]; - void *mem; + struct kfd_bo *buf_obj; int id; - idr_for_each_entry(&pdd->alloc_idr, mem, id) { - struct kgd_mem *kgd_mem = (struct kgd_mem *)mem; + idr_for_each_entry(&pdd->alloc_idr, buf_obj, id) { + struct kgd_mem *kgd_mem = (struct kgd_mem *)buf_obj->mem; if (!kgd_mem->va || kgd_mem->va > pdd->gpuvm_base) num_of_bos++; @@ -1997,7 +1997,7 @@ static int criu_checkpoint_bos(struct kfd_process *p, struct kfd_criu_bo_priv_data *bo_privs; struct file **files = NULL; int ret = 0, pdd_index, bo_index = 0, id; - void *mem; + struct kfd_bo *buf_obj; bo_buckets = kvzalloc(num_bos * sizeof(*bo_buckets), GFP_KERNEL); if (!bo_buckets) @@ -2020,12 +2020,12 @@ static int criu_checkpoint_bos(struct kfd_process *p, struct amdgpu_bo *dumper_bo; struct kgd_mem *kgd_mem; - idr_for_each_entry(&pdd->alloc_idr, mem, id) { + idr_for_each_entry(&pdd->alloc_idr, buf_obj, id) { struct kfd_criu_bo_bucket *bo_bucket; struct kfd_criu_bo_priv_data *bo_priv; int i, dev_idx = 0; - kgd_mem = (struct kgd_mem *)mem; + kgd_mem = (struct kgd_mem *)buf_obj->mem; dumper_bo = kgd_mem->bo; /* Skip checkpointing BOs that are used for Trap handler diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index 1e3d9af012651..e0a41feb7966f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -147,7 +147,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, goto err_read_unlock; idr_handle = kfd_process_device_create_obj_handle(pdd, mem, - va_addr, size, 0, 0); + va_addr, size, 0, 0, -1); if (idr_handle < 0) { r = -EFAULT; goto err_free; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 162412041d6f0..5d963fd601f44 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1152,7 +1152,8 @@ int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process, int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, void *mem, uint64_t start, uint64_t length, uint64_t cpuva, - unsigned int mem_type); + unsigned int mem_type, + int preferred_id); void *kfd_process_device_translate_handle(struct kfd_process_device *p, int handle); struct kfd_bo *kfd_process_device_find_bo(struct kfd_process_device *pdd, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 78788f0150b00..4d1caad455a8e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1844,7 +1844,8 @@ struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev, int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, void *mem, uint64_t start, uint64_t length, uint64_t cpuva, - unsigned int mem_type) + unsigned int mem_type, + int preferred_id) { int handle; struct kfd_bo *buf_obj; @@ -1866,7 +1867,11 @@ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, buf_obj->cpuva = cpuva; buf_obj->mem_type = mem_type; - handle = idr_alloc(&pdd->alloc_idr, buf_obj, 0, 0, GFP_KERNEL); + if (preferred_id < 0) + handle = idr_alloc(&pdd->alloc_idr, buf_obj, 0, 0, GFP_KERNEL); + else + handle = idr_alloc(&pdd->alloc_idr, buf_obj, preferred_id, + preferred_id + 1, GFP_KERNEL); if (handle < 0) kfree(buf_obj); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 6fd292005efd1..794e27a83ea24 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -3999,24 +3999,6 @@ int kfd_criu_resume_svm(struct kfd_process *p) set_attr[num_attrs].type = KFD_IOCTL_SVM_ATTR_CLR_FLAGS; set_attr[num_attrs].value = ~set_flags; - /* CLR_FLAGS is not available via get_attr during checkpoint but - * it needs to be inserted before restoring the ranges so - * allocate extra space for it before calling set_attr - */ - set_attr_size = sizeof(struct kfd_ioctl_svm_attribute) * - (num_attrs + 1); - set_attr = krealloc(set_attr, set_attr_size, - GFP_KERNEL); - if (!set_attr) { - ret = -ENOMEM; - goto exit; - } - - memcpy(set_attr, criu_svm_md->data.attrs, num_attrs * - sizeof(struct kfd_ioctl_svm_attribute)); - set_attr[num_attrs].type = KFD_IOCTL_SVM_ATTR_CLR_FLAGS; - set_attr[num_attrs].value = ~set_flags; - ret = svm_range_set_attr(p, mm, criu_svm_md->data.start_addr, criu_svm_md->data.size, num_attrs + 1, set_attr); From 8f98abb878484aeac90874a90440938e09dc89a6 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 1 Mar 2022 16:47:00 -0500 Subject: [PATCH 0709/2653] drm/amdkcl: Add support for kernels with MIGRATE_PFN_LOCKED MIGRATE_PFN_LOCKED was removed in commit ab09243aa95a ("mm/migrate.c: remove MIGRATE_PFN_LOCKED"). This patch restores compatibility with older kernels that still require this bit. Signed-off-by: Felix Kuehling Reviewed-by: Philip Yang Acked-by: Guchun Chen --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 ++ drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/backport/kcl_migrate.h | 14 ++++++++++++++ 3 files changed, 17 insertions(+) create mode 100644 include/kcl/backport/kcl_migrate.h diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index d4f840c5aec88..ec82b529fbd36 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -313,6 +313,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, migrate->dst[i] = svm_migrate_addr_to_pfn(adev, dst[i]); svm_migrate_get_vram_page(prange, migrate->dst[i]); migrate->dst[i] = migrate_pfn(migrate->dst[i]); + migrate->dst[i] |= MIGRATE_PFN_LOCKED; mpages++; } spage = migrate_pfn_to_page(migrate->src[i]); @@ -659,6 +660,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, dst[i] >> PAGE_SHIFT, page_to_pfn(dpage)); migrate->dst[i] = migrate_pfn(page_to_pfn(dpage)); + migrate->dst[i] |= MIGRATE_PFN_LOCKED; j++; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b7a34ffd5527f..1375da8d63065 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -39,6 +39,7 @@ #include #include #include +#include #include #ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ #include diff --git a/include/kcl/backport/kcl_migrate.h b/include/kcl/backport/kcl_migrate.h new file mode 100644 index 0000000000000..55a817d8cf2aa --- /dev/null +++ b/include/kcl/backport/kcl_migrate.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_BACKPORT_KCL_MIGRATE_H +#define _KCL_BACKPORT_KCL_MIGRATE_H + +#include + +/* Compatibility with kernels before ab09243aa95a ("mm/migrate.c: remove + * MIGRATE_PFN_LOCKED") + */ +#ifndef MIGRATE_PFN_LOCKED +#define MIGRATE_PFN_LOCKED 0 +#endif + +#endif From 21e1204e32a686df50dd45b4cd424d833faf7508 Mon Sep 17 00:00:00 2001 From: Xiaogang Chen Date: Mon, 13 Dec 2021 16:28:57 -0600 Subject: [PATCH 0710/2653] drm/amdkfd: explicitly create/destroy queue attributes under /sys This patch was not applied completely in the rebase. Original patch description follows. When application is about finish it destroys queues it has created by an ioctl. Driver deletes queue entry(/sys/class/kfd/kfd/proc/pid/queues/queueid/) which is directory including this queue all attributes. Low level kernel code deletes all attributes under this directory. The lock from kernel is on queue entry, not its attributes. At meantime another user space application can read the attributes. There is possibility that the application can hold/read the attributes while kernel is deleting the queue entry, cause the application have invalid memory access, then killed by kernel. Driver changes: explicitly create/destroy each attribute for each queue, let kernel put lock on each attribute too. Signed-off-by: Xiaogang Chen Reviewed-by: Felix Kuehling Acked-by: Guchun Chen Reviewed-by: Xiaogang.Chen --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 30 ------------------------ 1 file changed, 30 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 4d1caad455a8e..474ee5699f768 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -484,42 +484,12 @@ static ssize_t kfd_sysfs_counters_show(struct kobject *kobj, return 0; } -static struct attribute attr_queue_size = { - .name = "size", - .mode = KFD_SYSFS_FILE_MODE -}; - -static struct attribute attr_queue_type = { - .name = "type", - .mode = KFD_SYSFS_FILE_MODE -}; - -static struct attribute attr_queue_gpuid = { - .name = "gpuid", - .mode = KFD_SYSFS_FILE_MODE -}; - -static struct attribute *procfs_queue_attrs[] = { - &attr_queue_size, - &attr_queue_type, - &attr_queue_gpuid, - NULL -}; -#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE -ATTRIBUTE_GROUPS(procfs_queue); -#endif - static const struct sysfs_ops procfs_queue_ops = { .show = kfd_procfs_queue_show, }; static const struct kobj_type procfs_queue_type = { .sysfs_ops = &procfs_queue_ops, -#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE - .default_groups = procfs_queue_groups, -#else - .default_attrs = procfs_queue_attrs, -#endif }; static const struct sysfs_ops procfs_stats_ops = { From a8677e3fe91a9f003780936667cb2e6b62f99038 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Fri, 4 Mar 2022 19:11:53 -0500 Subject: [PATCH 0711/2653] drm/amdkfd: Hold mmap_read_lock for find_vma find_vma throws a warning if them mmap_read_lock is not held. Hold the lock as long as the vma returned by the call is needed. Once the lock is dropped, the VMA can become invalid. Signed-off-by: Felix Kuehling Reviewed-and-tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 9a314f930e784..ea1557eda18fc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1129,12 +1129,14 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, * space will be oblivious of this and will use this doorbell * BO as a regular userptr BO */ + mmap_read_lock(current->mm); vma = find_vma(current->mm, args->mmap_offset); if (vma && args->mmap_offset >= vma->vm_start && (vma->vm_flags & VM_IO)) { unsigned long pfn; err = follow_pfn(vma, args->mmap_offset, &pfn); + mmap_read_unlock(current->mm); if (err) { pr_debug("Failed to get PFN: %ld\n", err); goto err_unlock; @@ -1143,6 +1145,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, flags &= ~KFD_IOC_ALLOC_MEM_FLAGS_USERPTR; offset = (pfn << PAGE_SHIFT); } else { + mmap_read_unlock(current->mm); if (offset & (PAGE_SIZE - 1)) { pr_debug("Unaligned userptr address:%llx\n", offset); From a5cbd1124804b5e6026efb3f3da2ffdb203dae64 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 7 Mar 2022 12:03:23 +0800 Subject: [PATCH 0712/2653] drm/amdkcl: fix warning for unused variable in amdgpu_connector.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_update_scratch_regs’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:252:6: warning: unused variable ‘i’ [-Wunused-variable] 252 | int i; | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_find_encoder’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:275:6: warning: unused variable ‘i’ [-Wunused-variable] 275 | int i; | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_best_single_encoder’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:393:6: warning: unused variable ‘i’ [-Wunused-variable] 393 | int i; | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_dvi_detect’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1148:7: warning: unused variable ‘i’ [-Wunused-variable] 1148 | int i; | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_dvi_encoder’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1204:6: warning: unused variable ‘i’ [-Wunused-variable] 1204 | int i; | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_encoder_get_dp_bridge_encoder_id’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1372:6: warning: unused variable ‘i’ [-Wunused-variable] 1372 | int i; | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_encoder_is_hbr2’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1397:6: warning: unused variable ‘i’ [-Wunused-variable] 1397 | int i; | ^ Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index a59092dcadc14..be15a320c065c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -242,7 +242,9 @@ amdgpu_connector_update_scratch_regs(struct drm_connector *connector, struct drm_encoder *encoder; const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; bool connected; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif best_encoder = connector_funcs->best_encoder(connector); @@ -265,7 +267,9 @@ amdgpu_connector_find_encoder(struct drm_connector *connector, int encoder_type) { struct drm_encoder *encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { @@ -356,7 +360,9 @@ static struct drm_encoder * amdgpu_connector_best_single_encoder(struct drm_connector *connector) { struct drm_encoder *encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif /* pick the first one */ #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS @@ -1149,7 +1155,9 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) /* find analog encoder */ if (amdgpu_connector->dac_load_detect) { struct drm_encoder *encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { @@ -1206,7 +1214,9 @@ amdgpu_connector_dvi_encoder(struct drm_connector *connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); struct drm_encoder *encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { @@ -1373,7 +1383,9 @@ u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *conn { struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { @@ -1398,7 +1410,9 @@ static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) { struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif bool found = false; #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS From 0a1dc5d9416b37ae841e6f047e6e5640740b4daa Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Thu, 3 Mar 2022 14:48:19 -0500 Subject: [PATCH 0713/2653] drm/amdkfd: CRIU Add support for IPC handles Add support for checkpointing/restoring BOs with IPC handles. Reviewed-by: Felix Kuehling Signed-off-by: David Yat Sin --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 4 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 110 +++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 103 +++++++++++----- drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 4 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 + 6 files changed, 191 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index aea41b8397420..bbeac961f7381 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -384,7 +384,9 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, struct kgd_mem *mem, struct kfd_ipc_obj **ipc_obj, - uint32_t flags); + uint32_t flags, + uint32_t *restore_handle); + void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev); int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 6f36cd02705d8..8b773e64d8cc2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2737,7 +2737,8 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, struct kgd_mem *mem, struct kfd_ipc_obj **ipc_obj, - uint32_t flags) + uint32_t flags, + uint32_t *restore_handle) { struct dma_buf *dmabuf; int r = 0; @@ -2758,7 +2759,7 @@ int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, goto unlock_out; } - r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj, flags); + r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj, flags, restore_handle); if (r) dma_buf_put(dmabuf); else diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index ea1557eda18fc..6325c378ba469 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1691,7 +1691,7 @@ static int kfd_ioctl_ipc_import_handle(struct file *filep, r = kfd_ipc_import_handle(pdd->dev, p, args->gpu_id, args->share_handle, args->va_addr, &args->handle, - &args->mmap_offset, &args->flags); + &args->mmap_offset, &args->flags, false); if (r) pr_err("Failed to import IPC handle\n"); @@ -2082,8 +2082,18 @@ static int criu_checkpoint_bos(struct kfd_process *p, bo_priv->mapped_gpuids[dev_idx++] = p->pdds[i]->user_gpu_id; } - pr_debug("bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n" + if (kgd_mem->ipc_obj) { + bo_priv->ipc_flags = kgd_mem->ipc_obj->flags; + bo_priv->is_imported = kgd_mem->is_imported; + + memcpy(bo_priv->ipc_share_handle, + kgd_mem->ipc_obj->share_handle, + sizeof(kgd_mem->ipc_obj->share_handle)); + } + + pr_debug("[%d]bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx" "gpu_id = 0x%x alloc_flags = 0x%x idr_handle = 0x%x", + bo_index, bo_bucket->size, bo_bucket->addr, bo_bucket->offset, @@ -2391,6 +2401,93 @@ static int criu_restore_devices(struct kfd_process *p, return ret; } +static int criu_restore_memory_of_gpu_ipc(struct kfd_process_device *pdd, + struct kfd_criu_bo_bucket *bo_bucket, + struct kfd_criu_bo_priv_data *bo_priv, + struct kgd_mem **kgd_mem) +{ + uint64_t alloc_handle = MAKE_HANDLE(pdd->user_gpu_id, bo_priv->idr_handle); + struct kfd_dev *dev = pdd->dev; + struct kfd_bo *kfd_bo; + int ret, idr_handle; + uint64_t offset; + + ret = kfd_ipc_import_handle(dev, pdd->process, pdd->user_gpu_id, bo_priv->ipc_share_handle, + bo_bucket->addr, &alloc_handle, &offset, NULL, true); + if (ret) { + unsigned int mem_type; + + if (ret != -EINVAL) { + pr_err("Failed to import IPC handle ret:%d\n", ret); + return ret; + } + + /* kfd_ipc_import_handle returns -EINVAL if the ipc share_handle does not exist. + * In that case create a new BO and create a new ipc share_handle by calling + * amdgpu_amdkfd_gpuvm_export_ipc_obj. + */ + ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(dev->adev, bo_bucket->addr, + bo_bucket->size, pdd->drm_priv, + NULL, kgd_mem, &offset, + bo_bucket->alloc_flags, true); + if (ret) { + pr_err("Could not create the BO\n"); + return ret; + } + + pr_debug("New IPC BO created: size:0x%llx addr:0x%llx offset:0x%llx\n", + bo_bucket->size, bo_bucket->addr, offset); + + mem_type = bo_bucket->alloc_flags & + (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT); + + idr_handle = kfd_process_device_create_obj_handle(pdd, *kgd_mem, bo_bucket->addr, + bo_bucket->size, 0, mem_type, + bo_priv->idr_handle); + if (idr_handle < 0) { + pr_err("Could not allocate idr\n"); + + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, *kgd_mem, pdd->drm_priv, + NULL); + return -ENOMEM; + } + + ret = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->adev, pdd->drm_priv, *kgd_mem, + &(*kgd_mem)->ipc_obj, bo_priv->ipc_flags, + bo_priv->ipc_share_handle); + if (ret == -EINVAL) { + /* This is a race condition. The other process that owns this same IPC + * handle created the handle before this process. Delete BO and re-use + * import IPC handle created by the other process. + */ + ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, *kgd_mem, + pdd->drm_priv, NULL); + if (ret) + return ret; + + kfd_process_device_remove_obj_handle(pdd, idr_handle); + + ret = kfd_ipc_import_handle(dev, pdd->process, pdd->user_gpu_id, + bo_priv->ipc_share_handle, + bo_bucket->addr, &alloc_handle, + &offset, NULL, true); + if (ret) + return ret; + } + } + + kfd_bo = kfd_process_device_find_bo(pdd, bo_priv->idr_handle); + *kgd_mem = kfd_bo->mem; + (*kgd_mem)->is_imported = bo_priv->is_imported; + + bo_bucket->restored_offset = offset; + if ((bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) && !bo_priv->is_imported) + /* Update the VRAM usage count */ + WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + bo_bucket->size); + + return 0; +} + static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, struct kfd_criu_bo_bucket *bo_bucket, struct kfd_criu_bo_priv_data *bo_priv, @@ -2465,11 +2562,14 @@ static int criu_restore_bo(struct kfd_process *p, struct kfd_criu_bo_priv_data *bo_priv, struct file **file) { + const uint32_t zero_handle[4] = { 0, 0, 0, 0 }; struct kfd_process_device *pdd; struct kgd_mem *kgd_mem; int ret; int j; + BUILD_BUG_ON(sizeof_field(struct kfd_ipc_obj, share_handle) != sizeof(zero_handle)); + pr_debug("Restoring BO size:0x%llx addr:0x%llx gpu_id:0x%x flags:0x%x idr_handle:0x%x\n", bo_bucket->size, bo_bucket->addr, bo_bucket->gpu_id, bo_bucket->alloc_flags, bo_priv->idr_handle); @@ -2480,7 +2580,11 @@ static int criu_restore_bo(struct kfd_process *p, return -ENODEV; } - ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem); + if (memcmp(bo_priv->ipc_share_handle, zero_handle, sizeof(zero_handle))) + ret = criu_restore_memory_of_gpu_ipc(pdd, bo_bucket, bo_priv, &kgd_mem); + else + ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem); + if (ret) return ret; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index e0a41feb7966f..6021077f7199b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -42,7 +42,7 @@ static struct kfd_ipc_handles { #define HANDLE_TO_KEY(sh) ((*(uint64_t *)sh) & KFD_IPC_HASH_TABLE_SIZE_MASK) int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, - uint32_t flags) + uint32_t flags, uint32_t *restore_handle) { struct kfd_ipc_obj *obj; @@ -50,6 +50,30 @@ int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, if (!obj) return -ENOMEM; + if (restore_handle) + memcpy(obj->share_handle, restore_handle, sizeof(obj->share_handle)); + else + get_random_bytes(obj->share_handle, sizeof(obj->share_handle)); + + mutex_lock(&kfd_ipc_handles.lock); + if (restore_handle) { + struct kfd_ipc_obj *entry; + + /* When doing CRIU restore, we may have a race condition where two processes try + * to insert handles with the same key. Make sure this key does not already exist + */ + hlist_for_each_entry(entry, + &kfd_ipc_handles.handles[HANDLE_TO_KEY(obj->share_handle)], node) { + if (!memcmp(entry->share_handle, + obj->share_handle, + sizeof(entry->share_handle))) { + mutex_unlock(&kfd_ipc_handles.lock); + kfree(obj); + return -EINVAL; + } + } + } + /* The initial ref belongs to the allocator process. * The IPC object store itself does not hold a ref since * there is no specific moment in time where that ref should @@ -59,12 +83,9 @@ int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, */ kref_init(&obj->ref); obj->dmabuf = dmabuf; - get_random_bytes(obj->share_handle, sizeof(obj->share_handle)); obj->flags = flags; - mutex_lock(&kfd_ipc_handles.lock); - hlist_add_head(&obj->node, - &kfd_ipc_handles.handles[HANDLE_TO_KEY(obj->share_handle)]); + hlist_add_head(&obj->node, &kfd_ipc_handles.handles[HANDLE_TO_KEY(obj->share_handle)]); mutex_unlock(&kfd_ipc_handles.lock); if (ipc_obj) @@ -114,10 +135,10 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, uint32_t gpu_id, struct dma_buf *dmabuf, struct kfd_ipc_obj *ipc_obj, uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset) + uint64_t *mmap_offset, bool restore) { int r; - void *mem; + struct kgd_mem *mem; uint64_t size; int idr_handle; struct kfd_process_device *pdd = NULL; @@ -128,44 +149,34 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, if (!dev) return -EINVAL; - mutex_lock(&p->mutex); - r = amdgpu_read_lock(dev->ddev, true); - if (r) - goto err_unlock; + if (restore) + idr_handle = GET_IDR_HANDLE(*handle); + else + idr_handle = -1; pdd = kfd_bind_process_to_device(dev, p); - if (IS_ERR(pdd)) { - r = PTR_ERR(pdd); - goto err_read_unlock; - } + if (IS_ERR(pdd)) + return PTR_ERR(pdd); r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->adev, dmabuf, ipc_obj, - va_addr, pdd->drm_priv, - (struct kgd_mem **)&mem, &size, - mmap_offset); + va_addr, pdd->drm_priv, + &mem, &size, mmap_offset); if (r) - goto err_read_unlock; + return r; idr_handle = kfd_process_device_create_obj_handle(pdd, mem, - va_addr, size, 0, 0, -1); + va_addr, size, 0, 0, idr_handle); if (idr_handle < 0) { r = -EFAULT; goto err_free; } - amdgpu_read_unlock(dev->ddev); - mutex_unlock(&p->mutex); - *handle = MAKE_HANDLE(gpu_id, idr_handle); return 0; err_free: amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem, pdd->drm_priv, NULL); -err_read_unlock: - amdgpu_read_unlock(dev->ddev); -err_unlock: - mutex_unlock(&p->mutex); return r; } @@ -181,8 +192,19 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *dev, if (!dmabuf) return -EINVAL; + mutex_lock(&p->mutex); + r = amdgpu_read_lock(dev->ddev, true); + if (r) + goto err_unlock; + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, dmabuf, NULL, - va_addr, handle, mmap_offset); + va_addr, handle, mmap_offset, false); + + amdgpu_read_unlock(dev->ddev); + +err_unlock: + mutex_unlock(&p->mutex); + dma_buf_put(dmabuf); return r; } @@ -190,7 +212,7 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *dev, int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset, uint32_t *pflags) + uint64_t *mmap_offset, uint32_t *pflags, bool restore) { int r; struct kfd_ipc_obj *entry, *found = NULL; @@ -214,15 +236,32 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, pr_debug("Found ipc_dma_buf: %p\n", found->dmabuf); + if (!restore) { + mutex_lock(&p->mutex); + r = amdgpu_read_lock(dev->ddev, true); + if (r) + goto err_unlock; + } + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, found->dmabuf, found, - va_addr, handle, mmap_offset); + va_addr, handle, mmap_offset, + restore); + if (!restore) { + amdgpu_read_unlock(dev->ddev); + mutex_unlock(&p->mutex); + } if (r) goto error_unref; - *pflags = found->flags; + if (pflags) + *pflags = found->flags; + return r; +err_unlock: + mutex_unlock(&p->mutex); + error_unref: kfd_ipc_obj_put(&found); return r; @@ -260,7 +299,7 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, mem = (struct kgd_mem *)kfd_bo->mem; r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->adev, pdd->drm_priv, mem, - &ipc_obj, flags); + &ipc_obj, flags, NULL); if (r) goto unlock; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h index 7915b8cad13db..be0bf2b388194 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -42,7 +42,7 @@ struct kfd_ipc_obj { int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset, uint32_t *pflags); + uint64_t *mmap_offset, uint32_t *pflags, bool restore); int kfd_ipc_import_dmabuf(struct kfd_dev *kfd, struct kfd_process *p, uint32_t gpu_id, int dmabuf_fd, uint64_t va_addr, uint64_t *handle, @@ -52,7 +52,7 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, uint32_t flags); int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, - uint32_t flags); + uint32_t flags, uint32_t *restore_handle); void kfd_ipc_obj_put(struct kfd_ipc_obj **obj); #endif /* KFD_IPC_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 5d963fd601f44..176992c4b377d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1307,6 +1307,11 @@ struct kfd_criu_bo_priv_data { uint64_t user_addr; uint32_t idr_handle; uint32_t mapped_gpuids[MAX_GPU_INSTANCE]; + + /* IPC related variables */ + uint32_t is_imported; + uint32_t ipc_flags; + uint32_t ipc_share_handle[4]; }; /* From 2c816fc85391cb55e8d2d40c5a0bfacd5d2edf61 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 9 Mar 2022 15:54:38 +0800 Subject: [PATCH 0714/2653] drm/amdkcl: Add the sizeof_field() macro definition Add the sizeof_field() macro definiton for older versions of kernel Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I94d722db8c9fbfed92f07a3bd926e4fdaa7a8de3 --- drivers/gpu/drm/amd/backport/backport.h | 2 +- include/kcl/kcl_stddef.h | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 include/kcl/kcl_stddef.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1375da8d63065..7a3191d02da5d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -90,5 +90,5 @@ #include #include #include - +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_stddef.h b/include/kcl/kcl_stddef.h new file mode 100644 index 0000000000000..dc455e1423ab1 --- /dev/null +++ b/include/kcl/kcl_stddef.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_STDDEF_H_ +#define _KCL_KCL_STDDEF_H_ + +#include +#ifndef sizeof_field +/** + * sizeof_field() - Report the size of a struct field in bytes + * + * @TYPE: The structure containing the field of interest + * @MEMBER: The field to return the size of + */ +#define sizeof_field(TYPE, MEMBER) sizeof((((TYPE *)0)->MEMBER)) +#endif + +#endif From 038e5caf57f923a32a24475a4fe9f99272a3d422 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Thu, 10 Mar 2022 12:34:39 -0500 Subject: [PATCH 0715/2653] drm/amdkfd: Fix incorrect identation and compile warning Fix incorrect indentation and compile warning Signed-off-by: David Yat Sin Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 6325c378ba469..59c3fbe03bc14 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1235,7 +1235,6 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, struct kfd_ioctl_free_memory_of_gpu_args *args = data; struct kfd_process_device *pdd; struct kfd_bo *buf_obj; - struct kfd_dev *dev; int ret; uint64_t size = 0; From 1dcfb1cc923dc0f2a9f621b326f5f805e88cdf1f Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Mon, 14 Mar 2022 14:41:36 -0400 Subject: [PATCH 0716/2653] drm/amdkfd: fix a bug on creating gpuid sysfs entry Correct guid to gpuid to make kfd_procfs_queue_show() return a valid value. Signed-off-by: Eric Huang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 176992c4b377d..cab6a7cadfbf0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -641,7 +641,7 @@ struct queue { /* procfs */ struct kobject kobj; - struct attribute attr_guid; + struct attribute attr_gpuid; struct attribute attr_size; struct attribute attr_type; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 474ee5699f768..9a62aff0c2eeb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -531,7 +531,7 @@ int kfd_procfs_add_queue(struct queue *q) return ret; } - kfd_sysfs_create_file(&q->kobj, &q->attr_guid, "guid"); + kfd_sysfs_create_file(&q->kobj, &q->attr_gpuid, "gpuid"); kfd_sysfs_create_file(&q->kobj, &q->attr_size, "size"); kfd_sysfs_create_file(&q->kobj, &q->attr_type, "type"); @@ -679,7 +679,7 @@ void kfd_procfs_del_queue(struct queue *q) if (!q) return; - sysfs_remove_file(&q->kobj, &q->attr_guid); + sysfs_remove_file(&q->kobj, &q->attr_gpuid); sysfs_remove_file(&q->kobj, &q->attr_size); sysfs_remove_file(&q->kobj, &q->attr_type); From e04df481942ce94233ffd3f7b3493a7a05b9d6ca Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 14 Mar 2022 11:44:14 +0800 Subject: [PATCH 0717/2653] drm/amdkcl: fix test for drm_gem_object_put Signed-off-by: Flora Cui Reviewed-by: Rui Teng --- drivers/gpu/drm/amd/dkms/config/config.h | 8 ++--- .../gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 | 29 ++++++++----------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- include/kcl/backport/kcl_drm_gem.h | 4 +-- include/kcl/kcl_drm_gem.h | 8 ++--- 5 files changed, 23 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c9d73d317b8d2..47a86bc31cee8 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -530,11 +530,11 @@ /* drm_gem_object_lookup() wants 2 args */ #define HAVE_DRM_GEM_OBJECT_LOOKUP_2ARGS 1 -/* drm_gem_object_put_locked() is available */ -#define HAVE_DRM_GEM_OBJECT_PUT_LOCKED 1 +/* drm_gem_object_put() is available */ +#define HAVE_DRM_GEM_OBJECT_PUT 1 -/* drm_gem_object_put_unlocked() is available */ -/* #undef HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED */ +/* drm_gem_object_put() is exported */ +/* #undef HAVE_DRM_GEM_OBJECT_PUT_SYMBOL */ /* ttm_buffer_object->base is available */ #define HAVE_DRM_GEM_OBJECT_RESV 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 index f73dc8440b756..c4d2a03ec81c0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 @@ -3,25 +3,20 @@ dnl # v5.7-rc1-518-gab15d56e27be drm: remove transient drm_gem_object_put_unlock dnl # v5.7-rc1-491-geecd7fd8bf58 drm/gem: add _locked suffix to drm_gem_object_put dnl # v5.7-rc1-490-gb5d250744ccc drm/gem: fold drm_gem_object_put_unlocked and __drm_gem_object_put() dnl # -AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED], [ +AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_PUT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT( - [drm_gem_object_put_locked], [drivers/gpu/drm/drm_gem.c], - [ - AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_LOCKED, 1, - [drm_gem_object_put_locked() is available]) + AC_KERNEL_TRY_COMPILE([ + #include ], [ - dnl # - dnl # commit v4.10-rc8-1302-ge6b62714e87c - dnl # drm: Introduce drm_gem_object_{get,put}() - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_gem_object_put_unlocked(NULL); - ], [drm_gem_object_put_unlocked], [drivers/gpu/drm/drm_gem.c], [ - AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED, 1, - [drm_gem_object_put_unlocked() is available]) + drm_gem_object_put(NULL); + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT, 1, + [drm_gem_object_put() is available]) + + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_gem_object_put], + [drivers/gpu/drm/drm_gem.c], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_SYMBOL, 1, + [drm_gem_object_put() is exported]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c24918aa4db15..5141bcfedeba8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -71,7 +71,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DOWN_READ_KILLABLE AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED - AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED + AC_AMDGPU_DRM_GEM_OBJECT_PUT AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_CALC_PBN_MODE diff --git a/include/kcl/backport/kcl_drm_gem.h b/include/kcl/backport/kcl_drm_gem.h index 373e3719b4c57..6f04e71ca35fd 100644 --- a/include/kcl/backport/kcl_drm_gem.h +++ b/include/kcl/backport/kcl_drm_gem.h @@ -36,8 +36,8 @@ #include -#if !defined(HAVE_DRM_GEM_OBJECT_PUT_LOCKED) -#if defined(HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED) +#if defined(HAVE_DRM_GEM_OBJECT_PUT) +#if defined(HAVE_DRM_GEM_OBJECT_PUT_SYMBOL) #define drm_gem_object_put _kcl_drm_gem_object_put #endif #endif diff --git a/include/kcl/kcl_drm_gem.h b/include/kcl/kcl_drm_gem.h index a0f90deb18b06..cded9b424aa89 100644 --- a/include/kcl/kcl_drm_gem.h +++ b/include/kcl/kcl_drm_gem.h @@ -35,13 +35,14 @@ #define __KCL_KCL_DRM_GEM_H__ #include -#if !defined(HAVE_DRM_GEM_OBJECT_PUT_LOCKED) -#if defined(HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED) +#if defined(HAVE_DRM_GEM_OBJECT_PUT) +#if defined(HAVE_DRM_GEM_OBJECT_PUT_SYMBOL) static inline void _kcl_drm_gem_object_put(struct drm_gem_object *obj) { return drm_gem_object_put_unlocked(obj); } +#endif #else static inline void drm_gem_object_put(struct drm_gem_object *obj) @@ -54,7 +55,6 @@ drm_gem_object_get(struct drm_gem_object *obj) { kref_get(&obj->refcount); } -#endif -#endif /* HAVE_DRM_GEM_OBJECT_PUT_LOCKED */ +#endif /* HAVE_DRM_GEM_OBJECT_PUT */ #endif From f9751c18eb700c64a93a5734a81afd73576bdfa9 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 15 Mar 2022 16:17:42 +0800 Subject: [PATCH 0718/2653] drm/amdkcl: fix CC CFLAGS check Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 4 +-- .../drm/amd/dkms/m4/kernel_single_target.m4 | 25 ++++++++----------- 2 files changed, 13 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5141bcfedeba8..bca2a8c59ceeb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -457,7 +457,7 @@ AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) m4_ifvaln([$5], [AC_KERNEL_CONFTEST_H([$5])], [AC_KERNEL_CONFTEST_H([])]) AS_IF( - [AC_TRY_COMMAND($CC $CFLAGS -o conftest.o conftest.c) >/dev/null && AC_TRY_COMMAND([$2])], + [AC_TRY_COMMAND(eval $CC $CFLAGS) > /dev/null && AC_TRY_COMMAND([$2])], [$3], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$4],[$4])] ) @@ -472,7 +472,7 @@ dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], [AC_KERNEL_COMPILE_IFELSE( [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], - [test -s conftest.o], + [test -s conftest.o || test -s .tmp_conftest.o], [$3], [$4]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index b4af835c8928f..7fd86cef1e099 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -3,28 +3,25 @@ dnl # extract cc, cflags, cppflags dnl # AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ AS_IF([test -s .conftest.o.cmd], [ - _base_cflags="-DKBUILD_BASENAME='\"conftest\"' -DKBUILD_MODNAME='\"conftest\"'" - _base_dir=$(basename $PWD) _conftest_cmd=$(head -1 .conftest.o.cmd) CC=$(echo $_conftest_cmd | awk -F ' ' '{print $[3]}') + CFLAGS=$(echo $_conftest_cmd | \ - sed -e 's| -|\n&|g' | \ - sed -e "s|\./|${LINUX_OBJ}/|" \ - -e "s|-I\([[[a-z]]]*\)|-I${LINUX_OBJ}/\1|" \ - -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|" \ - -e '/conftest/d' \ - -e '/KBUILD_/d' \ - -e "/$_base_dir/d" | \ - xargs) + cut -d ' ' -f 4- | \ + sed -e "s|\./|${LINUX_OBJ}/|g" \ + -e "s|-I\([[[a-z]]]*\)|-I${LINUX_OBJ}/\1|g" \ + -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|g" \ + -e "s|$PWD|\${PWD}|g") + CPPFLAGS=$(echo $CFLAGS | \ + cut -d ';' -f 1 | \ sed 's| -|\n&|g' | \ - sed -n '/-I/p; /-include/p; /-isystem/p; /-D/p' | \ + sed -n -e '/conftest/d' \ + -e '/KBUILD/d' \ + -e '/-I/p; /-include/p; /-isystem/p; /-D/p' | \ xargs) - CFLAGS="$CFLAGS $_base_cflags" - CPPFLAGS="$CPPFLAGS $_base_cflags" - AC_SUBST(CC) AC_SUBST(CFLAGS) AC_SUBST(CPPFLAGS) From 6cb1a6b4721bb53fc41a3be84390e73474646ede Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 15 Mar 2022 16:50:44 +0800 Subject: [PATCH 0719/2653] drm/amdkcl: drop test for mem_encrypt_active not needed anymore Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 | 17 ------------ include/kcl/kcl_dma_mapping.h | 1 - include/kcl/kcl_mem_encrypt.h | 26 ------------------- 5 files changed, 48 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 delete mode 100644 include/kcl/kcl_mem_encrypt.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 47a86bc31cee8..b51ad53a9fbf5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -894,9 +894,6 @@ /* memalloc_noreclaim_save() is available */ #define HAVE_MEMALLOC_NORECLAIM_SAVE 1 -/* mem_encrypt_active() is available */ -#define HAVE_MEM_ENCRYPT_ACTIVE 1 - /* migrate_vma->pgmap_owner is available */ #define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index bca2a8c59ceeb..d5285f3b36d40 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -124,7 +124,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION - AC_AMDGPU_MEM_ENCRYPT_ACTIVE AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU___PRINT_ARRAY AC_AMDGPU_ACPI_PUT_TABLE diff --git a/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 b/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 deleted file mode 100644 index 5b80d8cf1223a..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 +++ /dev/null @@ -1,17 +0,0 @@ -dnl # -dnl # commit v4.14-rc8-89-gd8aa7eea78a1 -dnl # x86/mm: Add Secure Encrypted Virtualization (SEV) support -dnl # -AC_DEFUN([AC_AMDGPU_MEM_ENCRYPT_ACTIVE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - #include - ], [ - mem_encrypt_active(); - ], [ - AC_DEFINE(HAVE_MEM_ENCRYPT_ACTIVE, 1, - [mem_encrypt_active() is available]) - ]) - ]) -]) diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h index ba248dc82f298..81d15205ec77e 100644 --- a/include/kcl/kcl_dma_mapping.h +++ b/include/kcl/kcl_dma_mapping.h @@ -3,7 +3,6 @@ #define AMDKCL_DMA_MAPPING_H #include -#include /* * commit v4.8-11962-ga9a62c938441 diff --git a/include/kcl/kcl_mem_encrypt.h b/include/kcl/kcl_mem_encrypt.h deleted file mode 100644 index 60d24e198587e..0000000000000 --- a/include/kcl/kcl_mem_encrypt.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * AMD Memory Encryption Support - * - * Copyright (C) 2016 Advanced Micro Devices, Inc. - * - * Author: Tom Lendacky - */ -#ifndef KCL_KCL_MEM_ENCRYPT_H -#define KCL_KCL_MEM_ENCRYPT_H - -#ifdef HAVE_LINUX_MEM_ENCRYPT_H -#include -#ifndef HAVE_MEM_ENCRYPT_ACTIVE -static inline bool mem_encrypt_active(void) -{ - return sme_me_mask; -} -#endif -#else -static inline bool mem_encrypt_active(void) -{ - return false; -} -#endif -#endif From c96f9f94a08d3c49cb6b55d5bede4604efdcf007 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 15 Mar 2022 17:40:57 +0800 Subject: [PATCH 0720/2653] drm/amdkcl: drop test for drm_sysfs_connector_hotplug_event not needed anymore Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c | 44 ------------------- drivers/gpu/drm/amd/backport/backport.h | 1 - drivers/gpu/drm/amd/dkms/config/config.h | 3 -- .../m4/drm-sysfs-connector-hotplug-event.m4 | 16 ------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/kcl_drm_sysfs.h | 10 ----- 7 files changed, 1 insertion(+), 76 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-sysfs-connector-hotplug-event.m4 delete mode 100644 include/kcl/kcl_drm_sysfs.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 30e4532c21b24..d268f4a39a272 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_drm_nomodeset.o kcl_drm_sysfs.o + kcl_drm_nomodeset.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c deleted file mode 100644 index 5be759d09043b..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/* - * drm_sysfs.c - Modifications to drm_sysfs_class.c to support - * extra sysfs attribute from DRM. Normal drm_sysfs_class - * does not allow adding attributes. - * - * Copyright (c) 2004 Jon Smirl - * Copyright (c) 2003-2004 Greg Kroah-Hartman - * Copyright (c) 2003-2004 IBM Corp. - */ -#include -#include -#include -#include -#include - -#ifndef HAVE_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT -/** - * drm_sysfs_connector_hotplug_event - generate a DRM uevent for any connector - * change - * @connector: connector which has changed - * - * Send a uevent for the DRM connector specified by @connector. This will send - * a uevent with the properties HOTPLUG=1 and CONNECTOR. - */ -void drm_sysfs_connector_hotplug_event(struct drm_connector *connector) -{ - struct drm_device *dev = connector->dev; - char hotplug_str[] = "HOTPLUG=1", conn_id[21]; - char *envp[] = { hotplug_str, conn_id, NULL }; - - snprintf(conn_id, sizeof(conn_id), - "CONNECTOR=%u", connector->base.id); - - drm_dbg_kms(connector->dev, - "[CONNECTOR:%d:%s] generating connector hotplug event\n", - connector->base.id, connector->name); - - kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, envp); -} -EXPORT_SYMBOL(drm_sysfs_connector_hotplug_event); - -#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7a3191d02da5d..1887b9a0952fd 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -88,7 +88,6 @@ #include #include #include -#include #include #include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b51ad53a9fbf5..ac3bca351e4c3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -660,9 +660,6 @@ /* whether drm_syncobj_find_fence() wants 5 args */ #define HAVE_DRM_SYNCOBJ_FIND_FENCE_5ARGS 1 -/* drm_sysfs_connector_hotplug_event() function is available */ -#define HAVE_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-sysfs-connector-hotplug-event.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-sysfs-connector-hotplug-event.m4 deleted file mode 100644 index 3db7dabaf0b15..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-sysfs-connector-hotplug-event.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit v5.15-rc2-1273-g0d6a8c5e9683 -dnl # drm/sysfs: introduce drm_sysfs_connector_hotplug_event -dnl # -AC_DEFUN([AC_AMDGPU_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - drm_sysfs_connector_hotplug_event(NULL); - ], [ - AC_DEFINE(HAVE_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT, 1, - [drm_sysfs_connector_hotplug_event() function is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d5285f3b36d40..b87741ec01933 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -194,7 +194,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_IRQ_VECTOR AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY AC_AMDGPU_DMA_FENCE_DESCRIBE - AC_AMDGPU_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT AC_AMDGPU_PCIE_ASPM_ENABLED diff --git a/include/kcl/kcl_drm_sysfs.h b/include/kcl/kcl_drm_sysfs.h deleted file mode 100644 index aaa27638d4659..0000000000000 --- a/include/kcl/kcl_drm_sysfs.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef AMDKCL_DRM_SYSFS_H -#define AMDKCL_DRM_SYSFS_H - -struct drm_connector; -#ifndef HAVE_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT -void drm_sysfs_connector_hotplug_event(struct drm_connector *connector); -#endif - -#endif From 8e7ebe7709300fe875275594b48942fdfcf3245b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 16 Mar 2022 10:25:00 +0800 Subject: [PATCH 0721/2653] drm/amdkcl: drop kcl part of get_mm_exe_file not needed any more Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 10 ---------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 | 10 ---------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/backport/kcl_mm_backport.h | 4 ---- include/kcl/kcl_mm.h | 4 ---- 6 files changed, 32 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index 65ae09624622f..9d7534002b7e1 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -16,19 +16,9 @@ void __kcl_mmput_async(struct mm_struct *mm) } #endif - -#ifndef HAVE_GET_MM_EXE_FILE -struct file *(*_kcl_get_mm_exe_file)(struct mm_struct *mm); -EXPORT_SYMBOL(_kcl_get_mm_exe_file); -#endif - void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC _kcl_mmput_async = amdkcl_fp_setup("mmput_async", __kcl_mmput_async); #endif - -#ifndef HAVE_GET_MM_EXE_FILE - _kcl_get_mm_exe_file = amdkcl_fp_setup("get_mm_exe_file", NULL); -#endif } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ac3bca351e4c3..77555469a3de5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -696,9 +696,6 @@ /* generic_handle_domain_irq() is available */ #define HAVE_GENERIC_HANDLE_DOMAIN_IRQ 1 -/* get_mm_exe_file() is available */ -#define HAVE_GET_MM_EXE_FILE 1 - /* get_user_pages() wants 6 args */ /* #undef HAVE_GET_USER_PAGES_6ARGS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 b/drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 deleted file mode 100644 index 9c024190e405d..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 +++ /dev/null @@ -1,10 +0,0 @@ -dnl # -dnl # v2.6.39-6856-g3864601387cf mm: extract exe_file handling from procfs -dnl # -AC_DEFUN([AC_AMDGPU_GET_MM_EXE_FILE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([get_mm_exe_file], [kernel/fork.c], [ - AC_DEFINE(HAVE_GET_MM_EXE_FILE, 1, [get_mm_exe_file() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b87741ec01933..219766435eae6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -166,7 +166,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK - AC_AMDGPU_GET_MM_EXE_FILE AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT AC_AMDGPU_DRM_MODE_CONFIG_HELPER_SUSPEND AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP diff --git a/include/kcl/backport/kcl_mm_backport.h b/include/kcl/backport/kcl_mm_backport.h index 131403b50a6b4..48312d64e5869 100644 --- a/include/kcl/backport/kcl_mm_backport.h +++ b/include/kcl/backport/kcl_mm_backport.h @@ -9,10 +9,6 @@ #define mmput_async _kcl_mmput_async #endif -#ifndef HAVE_GET_MM_EXE_FILE -#define get_mm_exe_file _kcl_get_mm_exe_file -#endif - #ifdef get_user_pages_remote #undef get_user_pages_remote #endif diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 6a9f864111c47..a3fb87d51aa61 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -26,10 +26,6 @@ extern void (*_kcl_mmput_async)(struct mm_struct *mm); #endif -#ifndef HAVE_GET_MM_EXE_FILE -extern struct file *(*_kcl_get_mm_exe_file)(struct mm_struct *mm); -#endif - #ifndef HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST static inline bool fault_flag_allow_retry_first(unsigned int flags) { From 07579331ab9d6741448e89eeae0a74d9f3c41bb3 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 15 Mar 2022 16:28:03 +0800 Subject: [PATCH 0722/2653] drm/amdkcl: add missing AC_AMDGPU_PM_SUSPEND_TARGET_STATE Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 219766435eae6..aedd212e7be57 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -195,6 +195,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_DESCRIBE AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT AC_AMDGPU_PCIE_ASPM_ENABLED + AC_AMDGPU_PM_SUSPEND_TARGET_STATE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From f35ff936d6a2d47e70f24546158704024ff8c014 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 17 Mar 2022 13:15:35 +0800 Subject: [PATCH 0723/2653] drm/amdkcl: Test whether smca_get_bank_type() is exported v2: add CONFIG_X86_MCE_AMD guard v3: remove CONFIG_X86 guard v4: improve test for struct smca_bank and kcl implementation of smca_get_bank_type() Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c | 42 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 6 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 | 27 ++++++++++++ include/kcl/kcl_mce.h | 13 +++++- 7 files changed, 89 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index d268f4a39a272..4f4e70f2280c1 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_drm_nomodeset.o + kcl_drm_nomodeset.o kcl_mce_amd.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c new file mode 100644 index 0000000000000..30e62d94fbead --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * (c) 2005-2016 Advanced Micro Devices, Inc. + * + * Written by Jacob Shin - AMD, Inc. + * Maintained by: Borislav Petkov + * + * All MC4_MISCi registers are shared between cores on a node. + */ + + +#ifdef CONFIG_X86_MCE_AMD +#include + +#ifndef HAVE_SMCA_GET_BANK_TYPE + +/* Copied from v5.15-rc2-452-gf38ce910d8df:arch/x86/kernel/cpu/mce/amd.c and modified for KCL */ +#ifdef HAVE_SMCA_BANK_STRUCT +enum smca_bank_types smca_get_bank_type(unsigned int bank) +{ + struct smca_bank *b; + + if (bank >= MAX_NR_BANKS) + return N_SMCA_BANK_TYPES; + + b = &smca_banks[bank]; + if (!b->hwid) + return N_SMCA_BANK_TYPES; + + return b->hwid->bank_type; +} +#else +int smca_get_bank_type(unsigned int bank) +{ + pr_warn_once("smca_get_bank_type is not supported\n"); + return 0; +} +#endif /* HAVE_SMCA_BANK_STRUCT */ +EXPORT_SYMBOL_GPL(smca_get_bank_type); +#endif /* HAVE_SMCA_GET_BANK_TYPE */ + +#endif /* CONFIG_X86_MCE_AMD */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1887b9a0952fd..5498d12b697f2 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -90,4 +90,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 77555469a3de5..34277bb23679b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -999,6 +999,9 @@ /* whether si_mem_available() is available */ #define HAVE_SI_MEM_AVAILABLE 1 +/* smca_get_bank_type() is available */ +#define HAVE_SMCA_GET_BANK_TYPE 1 + /* is_smca_umc_v2() is available */ /* #undef HAVE_SMCA_UMC_V2 */ @@ -1090,6 +1093,9 @@ /* drm_plane_helper_funcs->prepare_fb() wants p,p arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_PP 1 +/* struct smca_bank is available */ +/* #undef HAVE_STRUCT_SMCA_BANK */ + /* struct xarray is available */ #define HAVE_STRUCT_XARRAY 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index aedd212e7be57..60b544a432488 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -196,6 +196,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT AC_AMDGPU_PCIE_ASPM_ENABLED AC_AMDGPU_PM_SUSPEND_TARGET_STATE + AC_AMDGPU_SMCA_GET_BANK_TYPE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 b/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 new file mode 100644 index 0000000000000..2ed1eef7d5149 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 @@ -0,0 +1,27 @@ +dnl # +dnl # +dnl # v5.15-rc2-452-gf38ce910d8df x86/MCE/AMD: Export smca_get_bank_type symbol +dnl # +AC_DEFUN([AC_AMDGPU_SMCA_GET_BANK_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([smca_get_bank_type], + [arch/x86/kernel/cpu/mce/amd.c], [ + AC_DEFINE(HAVE_SMCA_GET_BANK_TYPE, 1, + [smca_get_bank_type() is available]) + ], [ + dnl # + dnl # + dnl # v4.9-rc4-4-g79349f529ab1 x86/RAS: Simplify SMCA bank descriptor struct + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct smca_bank *b = NULL; + b->id = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_SMCA_BANK, 1, + [struct smca_bank is available]) + ]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mce.h b/include/kcl/kcl_mce.h index 5418ec9351e36..fee8c17c7d8fc 100644 --- a/include/kcl/kcl_mce.h +++ b/include/kcl/kcl_mce.h @@ -2,7 +2,7 @@ #ifndef AMDKCL_MCE_H #define AMDKCL_MCE_H -#ifdef CONFIG_X86 +#ifdef CONFIG_X86_MCE_AMD #include @@ -11,5 +11,14 @@ #define XEC(x, mask) (((x) >> 16) & mask) #endif -#endif /* CONFIG_X86 */ + +#if !defined(HAVE_SMCA_GET_BANK_TYPE) && defined(HAVE_SMCA_BANK_STRUCT) +enum smca_bank_types smca_get_bank_type(unsigned int bank); +#endif + +#ifndef HAVE_MCE_PRIO_UC +#define MCE_PRIO_UC MCE_PRIO_SRAO +#endif + +#endif /* CONFIG_X86_MCE_AMD */ #endif From 3ee5e75476e6057f07607c4e82d05476150a5347 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 17 Mar 2022 14:56:32 +0800 Subject: [PATCH 0724/2653] drm/amdkcl: Test whether enum MCE_PRIO_UC is available v2: define MCE_PRIO_UC macro if HAVE_MCE_PRIO_UC is not defined Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 | 15 +++++++++++++++ 3 files changed, 19 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 34277bb23679b..c68804bb5cd39 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -882,6 +882,9 @@ /* list_rotate_to_front() is available */ #define HAVE_LIST_ROTATE_TO_FRONT 1 +/* enum MCE_PRIO_UC is available */ +#define HAVE_MCE_PRIO_UC 1 + /* memalloc_nofs_{save,restore}() are available */ #define HAVE_MEMALLOC_NOFS_SAVE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 60b544a432488..fabf0b307cb97 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -197,6 +197,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCIE_ASPM_ENABLED AC_AMDGPU_PM_SUSPEND_TARGET_STATE AC_AMDGPU_SMCA_GET_BANK_TYPE + AC_AMDGPU_MCE_PRIO_UC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 new file mode 100644 index 0000000000000..ac2a78006ea2e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # +dnl # v5.5-rc2-5-g8438b84ab42d x86/mce: Take action on UCNA/Deferred errors again +dnl # +AC_DEFUN([AC_AMDGPU_MCE_PRIO_UC], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum mce_notifier_prios pri; + pri = MCE_PRIO_UC; + ], [ + AC_DEFINE(HAVE_MCE_PRIO_UC, 1, + [enum MCE_PRIO_UC is available]) + ]) +]) From bddf5ccb52f0aa301eed23b0c8e81cc70ff573eb Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 15 Mar 2022 16:28:28 +0800 Subject: [PATCH 0725/2653] drm/amdkcl: fix test for generic_handle_domain_irq Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 b/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 index d02f0f7f60014..01d095dd14cb8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 @@ -5,7 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #include + #include ], [ generic_handle_domain_irq(NULL, 0); ], [ From 90ff0f683cbbea37f6245bde1bca88ddf234f9c2 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 15 Mar 2022 17:58:08 +0800 Subject: [PATCH 0726/2653] drm/amdkcl: fix test for drm_edid_get_monitor_name Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 index c5de63f48eb91..4a6a10c962f4c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 @@ -7,7 +7,7 @@ AC_DEFUN([AC_AMDGPU_DRM_EDID_GET_MONITOR_NAME], [ AC_KERNEL_TRY_COMPILE_SYMBOL([ #include ], [ - drm_edid_get_monitor_name(NULL, NULL, NULL); + drm_edid_get_monitor_name(NULL, NULL, 0); ], [drm_edid_get_monitor_name], [drivers/gpu/drm/drm_edid.c], [ AC_DEFINE(HAVE_DRM_EDID_GET_MONITOR_NAME, 1, [drm_edid_get_monitor_name() are available]) From 54b09f2f775f887dc1bb29de44eae4fead55b060 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 28 Mar 2022 09:52:24 +0800 Subject: [PATCH 0727/2653] drm/amdkcl: Add drm_dbg_* related definition Add the drm_dbg_state, drm_dbg_vbl and related macro definition for older versions of kernel. Reviewed-by: Flora Cui Signed-off-by: Ma Jun Change-Id: Ia5766e1b9d51b2ceedd1f42b1866a6c836c729d6 --- include/kcl/kcl_drm_print.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index a7ef405b97cdc..f4a7ee6d44a16 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -125,6 +125,14 @@ void kcl_drm_err(const char *format, ...); #define HAVE_DRM_ERR_MACRO #endif /* drm_err */ +#if !defined(DRM_UT_STATE) +#define DRM_UT_STATE 0x40 +#endif + +#if !defined(DRM_UT_VBL) +#define DRM_UT_VBL 0x20 +#endif + #if !defined(DRM_DEV_DEBUG) #define DRM_DEV_DEBUG(dev, fmt, ...) \ DRM_DEBUG(fmt, ##__VA_ARGS__) @@ -136,7 +144,6 @@ void kcl_drm_err(const char *format, ...); #endif #ifndef DRM_DEBUG_VBL -#define DRM_UT_VBL 0x20 #define DRM_DEBUG_VBL(fmt, args...) \ do { \ if (unlikely(drm_debug & DRM_UT_VBL)) \ @@ -153,6 +160,16 @@ void drm_dev_dbg(const struct device *dev, int category, const char *format, ... drm_dev_dbg((drm)->dev, DRM_UT_ATOMIC, fmt, ##__VA_ARGS__) #endif +#if !defined(drm_dbg_state) +#define drm_dbg_state(drm, fmt, ...) \ + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_STATE, fmt, ##__VA_ARGS__) +#endif + +#if !defined(drm_dbg_vbl) +#define drm_dbg_vbl(drm, fmt, ...) \ + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_VBL, fmt, ##__VA_ARGS__) +#endif + #if !defined(drm_dbg_kms) #define drm_dbg_kms(drm, fmt, ...) \ drm_dev_dbg((drm)->dev, 0x04, fmt, ##__VA_ARGS__) From 7eec202065e5a1289d5156f68a16b2c004955ecb Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 31 Mar 2022 18:11:19 +0800 Subject: [PATCH 0728/2653] drm/amdkcl: rework kcl implementation drm_firmware_drivers_only() Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c | 25 ------------------- .../amd/dkms/m4/drm_firmware_drivers_only.m4 | 12 ++++----- include/kcl/backport/kcl_drm_drv.h | 6 +++++ 4 files changed, 13 insertions(+), 32 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 4f4e70f2280c1..97214f65dfbe2 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_drm_nomodeset.o kcl_mce_amd.o + kcl_mce_amd.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c deleted file mode 100644 index c60ce331ebb3a..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#ifndef HAVE_DRM_FIRMWARE_DRIVERS_ONLY - -static bool drm_nomodeset; - -bool drm_firmware_drivers_only(void) -{ - return drm_nomodeset; -} -EXPORT_SYMBOL(drm_firmware_drivers_only); - -static int __init disable_modeset(char *str) -{ - drm_nomodeset = true; - - pr_warn("Booted with the nomodeset parameter. Only the system framebuffer will be available\n"); - - return 1; -} - -/* Disable kernel modesetting */ -__setup("nomodeset", disable_modeset); - -#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 index b390e877bece7..3d95cd4406fe2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 @@ -3,14 +3,14 @@ dnl # v5.16-rc1-268-g6a2d2ddf2c34 dnl # drm: Move nomodeset kernel parameter to the DRM subsystem dnl # AC_DEFUN([AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ #include ], [ drm_firmware_drivers_only(); ], [ - AC_DEFINE(HAVE_DRM_FIRMWARE_DRIVERS_ONLY, 1, - [drm_firmware_drivers_only() is available]) - ]) - ]) + AC_DEFINE(HAVE_DRM_FIRMWARE_DRIVERS_ONLY, 1, + [drm_firmware_drivers_only() is available]) + ]) + ]) ]) diff --git a/include/kcl/backport/kcl_drm_drv.h b/include/kcl/backport/kcl_drm_drv.h index dcc5c195b2d08..2fd32a57bb5d5 100644 --- a/include/kcl/backport/kcl_drm_drv.h +++ b/include/kcl/backport/kcl_drm_drv.h @@ -27,6 +27,7 @@ #ifndef __KCL_BACKPORT_KCL_DRM_DRV_H__ #define __KCL_BACKPORT_KCL_DRM_DRV_H__ +#include /* * v5.1-rc5-1150-gbd53280ef042 drm/drv: Fix incorrect resolution of merge conflict * v5.1-rc2-5-g3f04e0a6cfeb drm: Fix drm_release() and device unplug @@ -49,4 +50,9 @@ void _kcl_drm_dev_unplug(struct drm_device *dev) #define drm_dev_unplug _kcl_drm_dev_unplug #endif + +#ifndef HAVE_DRM_FIRMWARE_DRIVERS_ONLY +#define drm_firmware_drivers_only vgacon_text_force +#endif /* HAVE_DRM_FIRMWARE_DRIVERS_ONLY */ + #endif From 3eddf7fb5ebd8484d23195c7ae0c0737700d7489 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 6 Apr 2022 13:18:51 +0800 Subject: [PATCH 0729/2653] drm/amdkcl: fix kcl of smca_get_bank_type() Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_mce.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/include/kcl/kcl_mce.h b/include/kcl/kcl_mce.h index fee8c17c7d8fc..80625b60944b7 100644 --- a/include/kcl/kcl_mce.h +++ b/include/kcl/kcl_mce.h @@ -11,9 +11,12 @@ #define XEC(x, mask) (((x) >> 16) & mask) #endif - -#if !defined(HAVE_SMCA_GET_BANK_TYPE) && defined(HAVE_SMCA_BANK_STRUCT) +#if !defined(HAVE_SMCA_GET_BANK_TYPE) +#ifdef HAVE_SMCA_BANK_STRUCT enum smca_bank_types smca_get_bank_type(unsigned int bank); +#else +int smca_get_bank_type(unsigned int bank); +#endif #endif #ifndef HAVE_MCE_PRIO_UC From 42d9657cbed290de5f0cf08a4e55abfa52904de4 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 8 Apr 2022 10:33:53 +0800 Subject: [PATCH 0730/2653] drm/amdkcl: Check if x86_hypervisor_type is defined Check and define x86_hypervisor_type for older versions of kernel Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I1428dcf4c10a7ceaa6b42815370589fdeba8595a --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/x86_hypervisor_type.m4 | 19 +++++++++++++++++ include/kcl/kcl_hypervisor.h | 21 +++++++++++++++++++ 5 files changed, 45 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/x86_hypervisor_type.m4 create mode 100644 include/kcl/kcl_hypervisor.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 5498d12b697f2..3428419009f27 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -91,4 +91,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c68804bb5cd39..55a59e5b5011c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1213,6 +1213,9 @@ /* pm_suspend_target_state is available */ #define HAVE_PM_SUSPEND_TARGET_STATE 1 +/* enum x86_hypervisor_type is available */ +#define HAVE_X86_HYPERVISOR_TYPE 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fabf0b307cb97..d2d023279dd31 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -198,6 +198,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PM_SUSPEND_TARGET_STATE AC_AMDGPU_SMCA_GET_BANK_TYPE AC_AMDGPU_MCE_PRIO_UC + AC_AMDGPU_X86_HYPERVISOR_TYPE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/x86_hypervisor_type.m4 b/drivers/gpu/drm/amd/dkms/m4/x86_hypervisor_type.m4 new file mode 100644 index 0000000000000..677a6050d5745 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/x86_hypervisor_type.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit: 03b2a320b19f1424e9ac9c21696be9c60b6d0d93 +dnl # x86/virt: Add enum for hypervisors to replace x86_hyper +dnl # +AC_DEFUN([AC_AMDGPU_X86_HYPERVISOR_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + enum x86_hypervisor_type test; + test = X86_HYPER_NATIVE; + ], [ + AC_DEFINE(HAVE_X86_HYPERVISOR_TYPE, 1, + [enum x86_hypervisor_type is available]) + ], [ + ]) + ]) +]) \ No newline at end of file diff --git a/include/kcl/kcl_hypervisor.h b/include/kcl/kcl_hypervisor.h new file mode 100644 index 0000000000000..270d6ddb53d44 --- /dev/null +++ b/include/kcl/kcl_hypervisor.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_HYPERVISOR_H +#define AMDKCL_HYPERVISOR_H + +#include + +#ifdef CONFIG_X86 +#if !defined(HAVE_X86_HYPERVISOR_TYPE) +enum x86_hypervisor_type { + X86_HYPER_NATIVE = 0, + X86_HYPER_VMWARE, + X86_HYPER_MS_HYPERV, + X86_HYPER_XEN_PV, + X86_HYPER_XEN_HVM, + X86_HYPER_KVM, + X86_HYPER_JAILHOUSE, + X86_HYPER_ACRN, +}; +#endif +#endif +#endif From 614c689ed52590b713ae35bbac03fdf4dc134779 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 8 Apr 2022 14:08:51 +0800 Subject: [PATCH 0731/2653] drm/amdkcl: Implement the hypervisor_is_type function Implement the hypervisor_is_type() function for older versions of kernel. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: Ib1dc33d7d6e02037e756c602bc21200e6941827c --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/hypervisor_is_type.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_hypervisor.h | 10 +++++++++- 4 files changed, 31 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/hypervisor_is_type.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 55a59e5b5011c..8f3e304cf8e52 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1216,6 +1216,9 @@ /* enum x86_hypervisor_type is available */ #define HAVE_X86_HYPERVISOR_TYPE 1 +/* hypervisor_is_type() is available */ +#define HAVE_HYPERVISOR_IS_TYPE 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" diff --git a/drivers/gpu/drm/amd/dkms/m4/hypervisor_is_type.m4 b/drivers/gpu/drm/amd/dkms/m4/hypervisor_is_type.m4 new file mode 100644 index 0000000000000..2d2702416ffd7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/hypervisor_is_type.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit: 79cc74155218316b9a5d28577c7077b2adba8e58 +dnl # x86/paravirt: Provide a way to check for hypervisors +dnl # +AC_DEFUN([AC_AMDGPU_HYPERVISOR_IS_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + hypervisor_is_type(X86_HYPER_NATIVE); + ], [ + AC_DEFINE(HAVE_HYPERVISOR_IS_TYPE, 1, + [hypervisor_is_type() is available]) + ], [ + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d2d023279dd31..a254af9171642 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -199,6 +199,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SMCA_GET_BANK_TYPE AC_AMDGPU_MCE_PRIO_UC AC_AMDGPU_X86_HYPERVISOR_TYPE + AC_AMDGPU_HYPERVISOR_IS_TYPE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_hypervisor.h b/include/kcl/kcl_hypervisor.h index 270d6ddb53d44..60521c70b9ba5 100644 --- a/include/kcl/kcl_hypervisor.h +++ b/include/kcl/kcl_hypervisor.h @@ -17,5 +17,13 @@ enum x86_hypervisor_type { X86_HYPER_ACRN, }; #endif + +#ifndef HAVE_HYPERVISOR_IS_TYPE +static inline bool hypervisor_is_type(enum x86_hypervisor_type type) +{ + return false; +} #endif -#endif + +#endif /* CONFIG_X86 */ +#endif /* AMDKCL_HYPERVISOR_H */ From 22f71c381c4926462fb9c23bb885acdf5e918304 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 12 Apr 2022 10:34:35 +0800 Subject: [PATCH 0732/2653] drm/amdkcl: Add support for ullong type module parameter Add support for ullong type module parameter in older versions of kernel. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: Ief04a76fb56a00632df15041df612d0e3256e5c4 --- drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c | 4 ++++ include/kcl/kcl_moduleparam.h | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c b/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c index d350a6bd07769..10fe1c5d9d9c4 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c @@ -27,3 +27,7 @@ #ifdef _kcl_param_check_hexint STANDARD_PARAM_DEF(hexint, unsigned int, "%#08x", kstrtouint); #endif + +#ifdef _kcl_param_check_ullong +STANDARD_PARAM_DEF(ullong, unsigned long long, "%llu", kstrtoull); +#endif \ No newline at end of file diff --git a/include/kcl/kcl_moduleparam.h b/include/kcl/kcl_moduleparam.h index 427abe45ea8af..e579efe182bbd 100644 --- a/include/kcl/kcl_moduleparam.h +++ b/include/kcl/kcl_moduleparam.h @@ -14,4 +14,12 @@ extern int param_get_hexint(char *buffer, const struct kernel_param *kp); #define param_check_hexint(name, p) param_check_uint(name, p) #endif /* param_check_hexint */ +#ifndef param_check_ullong +#define _kcl_param_check_ullong +extern const struct kernel_param_ops param_ops_ullong; +extern int param_set_ullong(const char *val, const struct kernel_param *kp); +extern int param_get_ullong(char *buffer, const struct kernel_param *kp); +#define param_check_ullong(name, p) __param_check(name, p, unsigned long long) +#endif /* param_check_ullong */ + #endif From 3e17b131f90d533bffe666bb5f2cb77ca1679e9b Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 12 Apr 2022 20:01:00 +0800 Subject: [PATCH 0733/2653] drm/amdkcl: Add PSR2 related macro Add PSR2 related macro definition for older versions of kernle. Signed-off-by: Ma Jun Change-Id: Id2d7ed0934faaaa2e91678426ea396cb99cbc54e --- include/kcl/kcl_drm_dp_helper.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 60b18feee18f4..74163ac1e0e2a 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -287,6 +287,20 @@ enum drm_dp_phy { #define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */ #endif +/* + * drm: Add PSR version 3 macro + */ +#ifndef DP_PSR2_WITH_Y_COORD_IS_SUPPORTED +# define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */ +#endif + +/* + * drm: add PSR2 support and capability definition as per eDP 1.5 + */ +#ifndef DP_PSR2_WITH_Y_COORD_ET_SUPPORTED +# define DP_PSR2_WITH_Y_COORD_ET_SUPPORTED 4 /* eDP 1.5, adopted eDP 1.4b SCR */ +#endif + /* * v4.10-rc3-483-gd0ce90629120 * drm : adds Y-coordinate and Colorimetry Format From 49113c1cfb713c9e4c533e3156d434fa4e082a94 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 19 Apr 2022 17:40:47 +0800 Subject: [PATCH 0734/2653] drm/amdkcl: add task_struct forward declaration Signed-off-by: Leslie Shi --- .../dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 index 50e28229344bf..87f2f1c951581 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 @@ -9,6 +9,7 @@ AC_DEFUN([AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ dnl # v5.3-rc1-540-g0a8459693238 fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers dnl # AC_KERNEL_TRY_COMPILE([ + struct task_struct; #include ], [ remove_conflicting_pci_framebuffers(NULL, NULL); From 5271dd81214567cd35a3481c841087b1065b7e2e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Sat, 7 May 2022 15:53:28 +0800 Subject: [PATCH 0735/2653] drm/amdkcl:Add the INTEL_FAM6_ALDERLAKE definition Add the INTEL_FAM6_ALDERLAKE definition for older verisons of kernel. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I3e88fe0aa0f6b7be48bcd23be5b5dc63edf7274e --- include/kcl/kcl_intel_family.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_intel_family.h b/include/kcl/kcl_intel_family.h index a4d7693bf0b0b..90793a772861b 100644 --- a/include/kcl/kcl_intel_family.h +++ b/include/kcl/kcl_intel_family.h @@ -10,5 +10,9 @@ #define INTEL_FAM6_ROCKETLAKE 0xA7 #endif +#ifndef INTEL_FAM6_ALDERLAKE +#define INTEL_FAM6_ALDERLAKE 0x97 /* Golden Cove / Gracemont */ +#endif + #endif /* CONFIG_X86 */ #endif From b05647c3850946a5d2f6073988d0b638e879e07a Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Sat, 7 May 2022 16:17:00 +0800 Subject: [PATCH 0736/2653] drm/amdkcl:Add DRM_DEV_INFO macro definition Add DRM_DEV_INFO macro definition for older versions of kernel. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I0337286e68f45420232e652f3c42cf0cb340260e --- include/kcl/kcl_drm_print.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index f4a7ee6d44a16..bba9e048cf699 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -143,6 +143,12 @@ void kcl_drm_err(const char *format, ...); DRM_ERROR(fmt, ##__VA_ARGS__) #endif +#ifndef DRM_DEV_INFO +/* NOTE: this is deprecated in favor of drm_info() or dev_info(). */ +#define DRM_DEV_INFO(dev, fmt, ...) \ + DRM_INFO(fmt, ##__VA_ARGS__) +#endif + #ifndef DRM_DEBUG_VBL #define DRM_DEBUG_VBL(fmt, args...) \ do { \ From c1eab6b08a7957496a277698d74152766510078c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 16 May 2022 12:04:45 +0800 Subject: [PATCH 0737/2653] drm/amdkcl: fix access_ok prototype MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix warning drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_smi_events.c: In function ‘kfd_smi_ev_write’: drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_smi_events.c:128:21: warning: passing argument 1 of ‘kcl_access_ok’ makes integer from pointer without a cast [-Wint-conversion] Signed-off-by: Flora Cui Reviewed-by: Guchun Chen Reviewed-by: Leslie Shi --- include/kcl/backport/kcl_uaccess_backport.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/backport/kcl_uaccess_backport.h b/include/kcl/backport/kcl_uaccess_backport.h index 5e358c64a8fce..e781a42201f49 100644 --- a/include/kcl/backport/kcl_uaccess_backport.h +++ b/include/kcl/backport/kcl_uaccess_backport.h @@ -3,7 +3,7 @@ #define AMDKCL_UACCESS_BACKPORT_H #include -static inline int kcl_access_ok(unsigned long addr, unsigned long size) +static inline int kcl_access_ok(const void __user *addr, unsigned long size) { #if !defined(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS) return access_ok(VERIFY_WRITE, (addr), (size)); From dff55b14f1bbbcd77175e8757d35006d33cf5a31 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 11 May 2022 10:39:14 +0800 Subject: [PATCH 0738/2653] drm/amdkcl: Add the DP_PHY_REPEATER_128B132B_RATES definition Add the macro definiton of DP_PHY_REPEATER_128B132B_RATES for older versions of kernel. Signed-off-by: Ma Jun Reviewed-by: Leslie Shi Change-Id: If48731e99796af81c36599f26d6497ab11f7aa18 --- include/kcl/kcl_drm_dp_helper.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 74163ac1e0e2a..e379e156b74d9 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -158,6 +158,11 @@ #define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED #endif +#ifndef DP_PHY_REPEATER_128B132B_RATES +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */ +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */ +#endif + /* v5.9-rc4-979-g9782f52ab5d6 * drm/dp: Add LTTPR helpers */ From 18aeef8b7836e357be1f35dab92ae14a8dbf65ea Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 13 Apr 2022 13:14:29 -0500 Subject: [PATCH 0739/2653] drm/amdgpu: Access MMIO/DOORBELL BO's of peer devices when IOMMU is ON Current design does not allow a GPU to access MMIO/DOORBELL memory of a peer device when IOMMU is turned ON. Changes made by this patch relax this constraint i.e. it allows GPU's to access MMIO/DOORBELL memory of peer devices without regard to IOMMU being ON or OFF. Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 42 +++++++++++-------- 1 file changed, 24 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 8b773e64d8cc2..4f64507f62c27 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -980,10 +980,24 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, &bo[i], attachment[i]); if (ret) goto unwind; + + /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */ + } else if ((mem->bo->tbo.type == ttm_bo_type_sg) && + ((mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) || + (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { + attachment[i]->type = KFD_MEM_ATT_SG; + ret = create_dmamap_sg_bo(adev, mem, &bo[i]); + if (ret) + goto unwind; } else { +#ifdef AMDKCL_AMDGPU_DMABUF_OPS WARN_ONCE(true, "Handling invalid ATTACH request"); ret = -EINVAL; goto unwind; +#endif + attachment[i]->type = KFD_MEM_ATT_SHARED; + bo[i] = mem->bo; + drm_gem_object_get(&bo[i]->tbo.base); } /* Add BO to VM internal data structures */ @@ -2425,35 +2439,27 @@ void amdgpu_amdkfd_gpuvm_put_bo_ref(struct amdgpu_bo *bo) /** * @get_sg_table_of_mmio_or_doorbel_bo - Builds and returns an instance - * of scatter gather table (sg_table) for BO's that represent MMIO or - * DOORBELL memory. An example of this is the MMIO BO that is used to - * surface HDP registers. + * of scatter gather table (sg_table) for a MMIO/DOORBELL BO. An example + * of this is the MMIO BO that's used to surface HDP registers. * - * @note: Per current design and implementation MMIO or DOORBELL BO's - * use only one scatterlist node in their sg_table. This is because - * the size of backing memory is relatively small (e.g. 4096 bytes - * for MMIO BO surfacing HDP registers). Implementation of this method - * relies on this design choice. + * @note: This method will only work as long as the address encapsulated + * by MMIO/DOORBELL BO is not a DMA mapped address * * The method does the following: * Acquire address to use in building scatterlist nodes * Acquire size of memory to use in building scatterlist nodes - * Invoke DMA Map service to obtain DMA'able address + * Invoke DMA Map service to obtain DMA mapped address * Access sg_table construction service with above parameters * Return the handle of scatter gather table * - * @adev: GPU device whose MMIO address needs to be exported - * @bo: Buffer object representing MMIO/DOORBELL memory e.g. HDP registers - * @dma_dev: Handle of peer PCIe device that wishes to access BO's memory + * @adev: GPU device whose MMIO/DOORBELL BO is being exported + * @bo: Handle of MMIO/DOORBELL BO e.g. HDP registers + * @dma_dev: Handle of peer PCIe device that wishes to access * @dir: Direction of data movement from peer PCIe devices perspective * * @sgt: Output parameter that is built and returned * * Return: zero if successful, non-zero otherwise - * - * @FIXME: This will only work as long as bo->tbo.sg->sgl->dma_address - * is not a DMA address but a physical BAR address. This will be reworked - * later when we add DMA mapping support for doorbell and MMIO BOs */ static int get_sg_table_of_mmio_or_doorbel_bo(struct amdgpu_bo *bo, struct device *dma_dev, enum dma_data_direction dir, @@ -2481,8 +2487,8 @@ static int get_sg_table_of_mmio_or_doorbel_bo(struct amdgpu_bo *bo, /* Update output parameter with a new sg_table */ pr_debug("MMIO/Doorbell BO size: %d\n", size); pr_debug("MMIO/Doorbell's DMA Address: %llx\n", dma_addr); - *sgt = create_doorbell_sg(dma_addr, size); - return 0; + *sgt = create_sg_table(dma_addr, size); + return (*sgt) ? 0 : -ENOMEM; } int amdgpu_amdkfd_gpuvm_get_sg_table(struct amdgpu_device *adev, From 14feae2155f3fc46bd9777ae589bc3d6c10fbbdc Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 2 Jun 2022 09:16:22 +0800 Subject: [PATCH 0740/2653] drm/amdkcl: Add macro definition for some new plane formats Add macro definition for some new plane formats Signed-off-by: Ma Jun Reviewed-by: Flora Cui Reviewed-by: Guchun Chen Change-Id: I290eefb6c39114a4790fde869429539957578e32 --- include/kcl/kcl_drm_fourcc.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h index 25cf40f897b23..959f64bb803a6 100644 --- a/include/kcl/kcl_drm_fourcc.h +++ b/include/kcl/kcl_drm_fourcc.h @@ -96,6 +96,14 @@ * 55:36 - Reserved for future use, must be zero */ +#ifndef AMD_FMT_MOD_TILE_VER_GFX11 +#define AMD_FMT_MOD_TILE_VER_GFX11 4 +#endif + +#ifndef AMD_FMT_MOD_TILE_GFX11_256K_R_X +#define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31 +#endif + #if !defined(AMD_FMT_MOD) #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) From bc02477849682bee89cf7e8093a8e8b36884432f Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 9 Jun 2022 14:57:42 +0800 Subject: [PATCH 0741/2653] drm/amdkcl: Check if ltr_path is defined Check if ltr_path is defined in struct pci_dev Signed-off-by: Ma Jun Reviewed-by: Guchun Chen Change-Id: I55201dca99824b144f6272198f68dedc46f114ce --- drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 | 18 ++++++++++++++++++ 4 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c index f89e5f40e1a54..9a8f93a288ac6 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c @@ -374,9 +374,11 @@ static void nbio_v4_3_program_ltr(struct amdgpu_device *adev) WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2, data); def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); +#ifdef HAVE_PCI_DEV_LTR_PATH if (adev->pdev->ltr_path) data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; else +#endif data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; if (def != data) WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8f3e304cf8e52..b33a9460cce97 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -882,6 +882,9 @@ /* list_rotate_to_front() is available */ #define HAVE_LIST_ROTATE_TO_FRONT 1 +/* strurct pci_dev->ltr_path is available */ +#define HAVE_PCI_DEV_LTR_PATH 1 + /* enum MCE_PRIO_UC is available */ #define HAVE_MCE_PRIO_UC 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a254af9171642..7c31c8309db35 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -200,6 +200,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MCE_PRIO_UC AC_AMDGPU_X86_HYPERVISOR_TYPE AC_AMDGPU_HYPERVISOR_IS_TYPE + AC_AMDGPU_PCI_DEV_LTR_PATH AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 b/drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 new file mode 100644 index 0000000000000..a629dac5f4aad --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit c46fd358070f22ba68d6e74c22016a33b914c20a +dnl # PCI/ASPM: Enable Latency Tolerance Reporting when supported +dnl # +dnl # +AC_DEFUN([AC_AMDGPU_PCI_DEV_LTR_PATH], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct pci_dev *dev; + dev->ltr_path = 0; + ], [ + AC_DEFINE(HAVE_PCI_DEV_LTR_PATH, 1, + [strurct pci_dev->ltr_path is available]) + ]) + ]) +]) From 1c2d688dda830e671ac10838e85e5d60cdeeeea3 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Fri, 10 Jun 2022 20:43:25 +0800 Subject: [PATCH 0742/2653] drm/amdkcl: Check if display_info->edid_hdmi_rgb444_dc_modes is defined Check if display_info->edid_hdmi_rgb444_dc_modes is defined introduced in v4.9-rc1-522171951761153172c75b94ae1f4bc9ab631745 Signed-off-by: Yifan Zhang Signed-off-by: Ma Jun Change-Id: Ic2659a288fae2af696cf2c3d20c3e97491341c5f --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm-display-info.m4 | 20 +++++++++++++++++++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index be15a320c065c..8d3f165f4686d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -199,7 +199,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { +#ifndef HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES + if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && +#else if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) && +#endif (mode_clock * 5/4 <= max_tmds_clock)) bpc = 10; else diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b33a9460cce97..52fed73a65292 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -300,6 +300,9 @@ /* drm_dev_unplug() is available */ #define HAVE_DRM_DEV_UNPLUG 1 +/* display_info->edid_hdmi_rgb444_dc_modes is available */ +#define HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES 1 + /* display_info->hdmi.scdc.scrambling are available */ #define HAVE_DRM_DISPLAY_INFO_HDMI_SCDC_SCRAMBLING 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 index 61eef3b454776..6e726111f8c16 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 @@ -1,3 +1,22 @@ +dnl # +dnl # commit v4.9-rc1-522171951761153172c75b94ae1f4bc9ab631745 +dnl # drm: Extract drm_connector.[hc] +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_display_info *display_info = NULL; + display_info->edid_hdmi_rgb444_dc_modes = 0; + ], [ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES, 1, + [display_info->edid_hdmi_rgb444_dc_modes is available]) + ]) + ]) +]) + + dnl # dnl # commit v5.6-rc2-1062-ga1d11d1efe4d dnl # drm/edid: Add function to parse EDID descriptors for monitor range @@ -18,5 +37,6 @@ AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE], [ ]) AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO], [ + AC_AMDGPU_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE ]) From 00c89819ab068dc2dd829f9975f77101911f7c83 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Sun, 12 Jun 2022 16:58:46 +0800 Subject: [PATCH 0743/2653] drm/amdkcl: Check if cancel_work is defined Check and add cancel_work() function Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I002962a0476e253cbad2f4f414965c95b96b2d78 --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c | 41 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 | 17 ++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_workqueue_backport.h | 13 ++++++ 8 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 create mode 100644 include/kcl/backport/kcl_workqueue_backport.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 97214f65dfbe2..d0ccd6f534348 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_mce_amd.o + kcl_mce_amd.o kcl_workqueue.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c b/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c new file mode 100644 index 0000000000000..461066e047ac3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c @@ -0,0 +1,41 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#ifndef HAVE_CANCEL_WORK +bool (*_kcl_cancel_work)(struct work_struct *work); +EXPORT_SYMBOL(_kcl_cancel_work); + +bool _kcl_cancel_work_stub(struct work_struct *work) +{ + pr_warn_once("cancel_work function is not supported\n"); + return false; +} +#endif + +void amdkcl_workqueue_init(void) +{ +#ifndef HAVE_CANCEL_WORK + _kcl_cancel_work = amdkcl_fp_setup("cancel_work", _kcl_cancel_work_stub); +#endif /* HAVE_CANCEL_WORK */ +} + diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index feb2d6548f323..bd158234c6db0 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -14,6 +14,7 @@ extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); extern void amdkcl_sched_init(void); extern void amdkcl_numa_init(void); +extern void amdkcl_workqueue_init(void); int __init amdkcl_init(void) { @@ -29,6 +30,7 @@ int __init amdkcl_init(void) amdkcl_suspend_init(); amdkcl_sched_init(); amdkcl_numa_init(); + amdkcl_workqueue_init(); return 0; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 3428419009f27..3de3c768a6147 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -92,4 +92,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 52fed73a65292..545032a26c018 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -52,6 +52,9 @@ /* bitmap_free() is available */ #define HAVE_BITMAP_FUNCS 1 +/* cancel_work() is available */ +#define HAVE_CANCEL_WORK 1 + /* whether CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL is defined */ #define HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 new file mode 100644 index 0000000000000..b0cabe1643a14 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit id:c46fd358070f22ba68d6e74c22016a33b914c20a +dnl # PCI/ASPM: Enable Latency Tolerance Reporting when supported +dnl # +dnl # +AC_DEFUN([AC_AMDGPU_CANCEL_WORK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + cancel_work(NULL); + ], [ + AC_DEFINE(HAVE_CANCEL_WORK, 1, + [cancel_work() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7c31c8309db35..9abc1dd6f4d35 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -201,6 +201,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_X86_HYPERVISOR_TYPE AC_AMDGPU_HYPERVISOR_IS_TYPE AC_AMDGPU_PCI_DEV_LTR_PATH + AC_AMDGPU_CANCEL_WORK AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_workqueue_backport.h b/include/kcl/backport/kcl_workqueue_backport.h new file mode 100644 index 0000000000000..3e6adabc0f08c --- /dev/null +++ b/include/kcl/backport/kcl_workqueue_backport.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef KCL_LINUX_WORKQUEUE_BACKPORT_H +#define KCL_LINUX_WORKQUEUE_BACKPORT_H + +#include + +#ifndef HAVE_CANCEL_WORK +extern bool (*_kcl_cancel_work)(struct work_struct *work); +#define cancel_work _kcl_cancel_work +#endif + +#endif /* KCL_LINUX_WORKQUEUE_BACKPORT_H */ From d8bf2feef87a1b5a31cb02cb8b1dc690f3096f8a Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 8 Jun 2022 10:13:16 -0500 Subject: [PATCH 0744/2653] drm/amdgpu: Reduce P2P code divergence in DRM vs DKMS branches Cleans up the DKMS-version of P2P to reduce differences from the upstream implementation (DRM-version) without breaking the P2P functionality supported on the DKMS branch. Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling Change-Id: I6de18c791a6def548024d03526de695b6032adff --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 16 +++------------- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + 3 files changed, 5 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index e8cf2951708f1..f286bb85ee00e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -232,6 +232,7 @@ extern int amdgpu_noretry; extern int amdgpu_force_asic_type; extern int amdgpu_smartshift_bias; extern int amdgpu_use_xgmi_p2p; +extern bool pcie_p2p; extern int amdgpu_mtype_local; extern int amdgpu_enforce_isolation; #ifdef CONFIG_HSA_AMD diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 4f64507f62c27..7a71012b9654d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -848,7 +848,7 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, * * Implementation determines if access to VRAM BO would employ DMABUF * or Shared BO mechanism. Employ DMABUF mechanism if kernel has config - * option DMABUF_MOVE_NOTIFY enabled. Employ Shared BO mechanism if above + * option HSA_AMD_P2P enabled. Employ Shared BO mechanism if above * config option is not set. It is important to note that a Shared BO * cannot be used to enable peer acces if system has IOMMU enabled * @@ -861,7 +861,7 @@ static int kfd_mem_attach_vram_bo(struct amdgpu_device *adev, { int ret = 0; -#if defined(CONFIG_DMABUF_MOVE_NOTIFY) && defined(CONFIG_PCI_P2PDMA) +#ifdef CONFIG_HSA_AMD_P2P attachment->type = KFD_MEM_ATT_DMABUF; ret = kfd_mem_attach_dmabuf(adev, mem, bo); pr_debug("Employ DMABUF mechanim to enable peer GPU access\n"); @@ -974,21 +974,11 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, pr_debug("Employ DMABUF mechanism to enable peer GPU access\n"); #endif /* Enable peer acces to VRAM BO's */ - } else if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM && - mem->bo->tbo.type == ttm_bo_type_device) { + } else if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM) { ret = kfd_mem_attach_vram_bo(adev, mem, &bo[i], attachment[i]); if (ret) goto unwind; - - /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */ - } else if ((mem->bo->tbo.type == ttm_bo_type_sg) && - ((mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) || - (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { - attachment[i]->type = KFD_MEM_ATT_SG; - ret = create_dmamap_sg_bo(adev, mem, &bo[i]); - if (ret) - goto unwind; } else { #ifdef AMDKCL_AMDGPU_DMABUF_OPS WARN_ONCE(true, "Handling invalid ATTACH request"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index f2b2dad809c26..1804a1927c825 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include From 30a39f9fa3810aa972454d91c92a1002c66d0c8d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 17 Jun 2022 16:02:27 +0800 Subject: [PATCH 0745/2653] drm/amdkcl: Fix 64 bit wraparound resulting in illegal drm mode [Why] For m = drm_display_mode{.clock = 533250, .htotal = 4000, .vtotal = 2222}, common_rates[i] = 60000, the result of target_vtotal is 2221. This cause wraparound of variable target_vtotal_diff. [How] Skip the loop if target_vtotal less than m->vtotal Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 863313910dadc..2927a6000869b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8476,6 +8476,10 @@ static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) num = (unsigned long long)m->clock * 1000 * 1000; den = common_rates[i] * (unsigned long long)m->htotal; target_vtotal = div_u64(num, den); + + if (target_vtotal < m->vtotal) + continue; + target_vtotal_diff = target_vtotal - m->vtotal; /* Check for illegal modes */ From 5dac330a533510172b7bdbcfcd298209c6fb9fa4 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 24 Jun 2022 09:02:20 +0800 Subject: [PATCH 0746/2653] drm/amdkcl: Change the temp build dir name Changing the build-XXXXXXXX to build.XXXXXXXX to fix the CFLAGS parse error in case of using build-Ixxx as temp dir name. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I92ef6e3aaafae103b48d12786f3eac15b6bab708 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9abc1dd6f4d35..de186e596e0e6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -423,7 +423,7 @@ dnl # AC_KERNEL_TMP_BUILD_DIR dnl # $1: contents to be executed in a temporary directory dnl # AC_DEFUN([AC_KERNEL_TMP_BUILD_DIR], [ - build_dir=$(mktemp -d -t build-XXXXXXXX -p $build_dir_root) + build_dir=$(mktemp -d -t build_XXXXXXXX -p $build_dir_root) cd $build_dir $1 AS_IF([test -s confdefs.h], [ From 5c4800b735cf74b1befd4327a56ab4a29c862c82 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 21 Jun 2022 13:43:48 +0800 Subject: [PATCH 0747/2653] drm/amdkcl: add kcl/kcl_iosys-map.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 5 +- drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 + drivers/gpu/drm/ttm/backport/backport.h | 1 + drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- include/kcl/header/linux/iosys-map.h | 9 + include/kcl/kcl_dma-buf-map.h | 2 + include/kcl/kcl_iosys-map.h | 179 +++++++++++++++++++ 8 files changed, 203 insertions(+), 2 deletions(-) create mode 100644 include/kcl/header/linux/iosys-map.h create mode 100644 include/kcl/kcl_iosys-map.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 3de3c768a6147..1846a72101907 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 545032a26c018..7f7bc35b2d0d0 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -826,7 +826,7 @@ /* #undef HAVE_LINUX_DMA_ATTRS_H */ /* Define to 1 if you have the header file. */ -#define HAVE_LINUX_DMA_BUF_MAP_H 1 +/* #undef HAVE_LINUX_DMA_BUF_MAP_H */ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_FENCE_CHAIN_H 1 @@ -840,6 +840,9 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_LINUX_FENCE_ARRAY_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_IOSYS_MAP_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_IO_64_NONATOMIC_LO_HI_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 203f810772d52..b6024239ef2f5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -73,6 +73,12 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([linux/dma-buf-map.h]) + dnl # + dnl # 7938f4218168 + dnl # dma-buf: dma-buf-map: Rename to iosys-map + dnl # + AC_KERNEL_CHECK_HEADERS([linux/iosys-map.h]) + dnl # dnl # v5.14-rc5-11-gc0891ac15f04 dnl # isystem: ship and use stdarg.h diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 1e6024331b9f1..23eea49ccf6ae 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 5ffb3c7b662df..63c470af0e18d 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -123,7 +123,7 @@ void ttm_move_memcpy(bool clear, if (!src_map.is_iomem && !dst_map.is_iomem) { memcpy(dst_map.vaddr, src_map.vaddr, PAGE_SIZE); } else if (!src_map.is_iomem) { - dma_buf_map_memcpy_to(&dst_map, src_map.vaddr, + iosys_map_memcpy_to(&dst_map, 0, src_map.vaddr, PAGE_SIZE); } else if (!dst_map.is_iomem) { memcpy_fromio(dst_map.vaddr, src_map.vaddr_iomem, diff --git a/include/kcl/header/linux/iosys-map.h b/include/kcl/header/linux/iosys-map.h new file mode 100644 index 0000000000000..a96b1547378c6 --- /dev/null +++ b/include/kcl/header/linux/iosys-map.h @@ -0,0 +1,9 @@ +#ifndef _KCL_HEADER___IOSYS_MAP_H___H_ +#define _KCL_HEADER___IOSYS_MAP_H___H_ + +#ifdef HAVE_LINUX_IOSYS_MAP_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_dma-buf-map.h b/include/kcl/kcl_dma-buf-map.h index 4ce925f647ec5..c3112da74c090 100644 --- a/include/kcl/kcl_dma-buf-map.h +++ b/include/kcl/kcl_dma-buf-map.h @@ -7,7 +7,9 @@ #ifndef _KCL_KCL__DMA_BUF_MAP_H__H__ #define _KCL_KCL__DMA_BUF_MAP_H__H__ +#ifndef HAVE_LINUX_IOSYS_MAP_H #include +#endif #ifndef HAVE_LINUX_DMA_BUF_MAP_H #include diff --git a/include/kcl/kcl_iosys-map.h b/include/kcl/kcl_iosys-map.h new file mode 100644 index 0000000000000..d35ce3a8f5c58 --- /dev/null +++ b/include/kcl/kcl_iosys-map.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Pointer abstraction for IO/system memory + * Copied from include/kcl/iosys-map.h + */ + +#ifndef _KCL_KCL__IOSYS_MAP_H__H__ +#define _KCL_KCL__IOSYS_MAP_H__H__ + +#include + +#ifndef HAVE_LINUX_IOSYS_MAP_H +#include +#include + +/** + * struct iosys_map - Pointer to IO/system memory + * @vaddr_iomem: The buffer's address if in I/O memory + * @vaddr: The buffer's address if in system memory + * @is_iomem: True if the buffer is located in I/O memory, or false + * otherwise. + */ +struct iosys_map { + union { + void __iomem *vaddr_iomem; + void *vaddr; + }; + bool is_iomem; +}; + +/** + * IOSYS_MAP_INIT_VADDR - Initializes struct iosys_map to an address in system memory + * @vaddr_: A system-memory address + */ +#define IOSYS_MAP_INIT_VADDR(vaddr_) \ + { \ + .vaddr = (vaddr_), \ + .is_iomem = false, \ + } + + +/** + * iosys_map_set_vaddr - Sets a iosys mapping structure to an address in system memory + * @map: The iosys_map structure + * @vaddr: A system-memory address + * + * Sets the address and clears the I/O-memory flag. + */ +static inline void iosys_map_set_vaddr(struct iosys_map *map, void *vaddr) +{ + map->vaddr = vaddr; + map->is_iomem = false; +} + +/** + * iosys_map_set_vaddr_iomem - Sets a iosys mapping structure to an address in I/O memory + * @map: The iosys_map structure + * @vaddr_iomem: An I/O-memory address + * + * Sets the address and the I/O-memory flag. + */ +static inline void iosys_map_set_vaddr_iomem(struct iosys_map *map, + void __iomem *vaddr_iomem) +{ + map->vaddr_iomem = vaddr_iomem; + map->is_iomem = true; +} + +/** + * iosys_map_is_equal - Compares two iosys mapping structures for equality + * @lhs: The iosys_map structure + * @rhs: A iosys_map structure to compare with + * + * Two iosys mapping structures are equal if they both refer to the same type of memory + * and to the same address within that memory. + * + * Returns: + * True is both structures are equal, or false otherwise. + */ +static inline bool iosys_map_is_equal(const struct iosys_map *lhs, + const struct iosys_map *rhs) +{ + if (lhs->is_iomem != rhs->is_iomem) + return false; + else if (lhs->is_iomem) + return lhs->vaddr_iomem == rhs->vaddr_iomem; + else + return lhs->vaddr == rhs->vaddr; +} + +/** + * iosys_map_is_null - Tests for a iosys mapping to be NULL + * @map: The iosys_map structure + * + * Depending on the state of struct iosys_map.is_iomem, tests if the + * mapping is NULL. + * + * Returns: + * True if the mapping is NULL, or false otherwise. + */ +static inline bool iosys_map_is_null(const struct iosys_map *map) +{ + if (map->is_iomem) + return !map->vaddr_iomem; + return !map->vaddr; +} + +/** + * iosys_map_is_set - Tests if the iosys mapping has been set + * @map: The iosys_map structure + * + * Depending on the state of struct iosys_map.is_iomem, tests if the + * mapping has been set. + * + * Returns: + * True if the mapping is been set, or false otherwise. + */ +static inline bool iosys_map_is_set(const struct iosys_map *map) +{ + return !iosys_map_is_null(map); +} + +/** + * iosys_map_clear - Clears a iosys mapping structure + * @map: The iosys_map structure + * + * Clears all fields to zero, including struct iosys_map.is_iomem, so + * mapping structures that were set to point to I/O memory are reset for + * system memory. Pointers are cleared to NULL. This is the default. + */ +static inline void iosys_map_clear(struct iosys_map *map) +{ + if (map->is_iomem) { + map->vaddr_iomem = NULL; + map->is_iomem = false; + } else { + map->vaddr = NULL; + } +} + +/** + * iosys_map_memcpy_to - Memcpy into offset of iosys_map + * @dst: The iosys_map structure + * @dst_offset: The offset from which to copy + * @src: The source buffer + * @len: The number of byte in src + * + * Copies data into a iosys_map with an offset. The source buffer is in + * system memory. Depending on the buffer's location, the helper picks the + * correct method of accessing the memory. + */ +static inline void iosys_map_memcpy_to(struct iosys_map *dst, size_t dst_offset, + const void *src, size_t len) +{ + if (dst->is_iomem) + memcpy_toio(dst->vaddr_iomem + dst_offset, src, len); + else + memcpy(dst->vaddr + dst_offset, src, len); +} + +/** + * iosys_map_incr - Increments the address stored in a iosys mapping + * @map: The iosys_map structure + * @incr: The number of bytes to increment + * + * Increments the address stored in a iosys mapping. Depending on the + * buffer's location, the correct value will be updated. + */ +static inline void iosys_map_incr(struct iosys_map *map, size_t incr) +{ + if (map->is_iomem) + map->vaddr_iomem += incr; + else + map->vaddr += incr; +} + +#endif /* HAVE_LINUX_IOSYS_MAP_H */ + +#endif From 97b339b408fb22882cdae98d5565f5d1caa0efd9 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 21 Jun 2022 14:01:45 +0800 Subject: [PATCH 0748/2653] drm/amdkcl: test for drm/dp/drm_dp_helper.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 | 4 ++++ .../drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 | 8 ++++++++ .../amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 | 4 ++++ .../dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 | 4 ++++ .../drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 | 4 ++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ include/kcl/backport/kcl_drm_dp_helper_backport.h | 1 - include/kcl/header/drm/dp/drm_dp_helper.h | 9 +++++++++ include/kcl/kcl_drm_dp_cec.h | 4 ++++ include/kcl/kcl_drm_dp_helper.h | 4 ++++ 11 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 include/kcl/header/drm/dp/drm_dp_helper.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7f7bc35b2d0d0..766f8c57ce815 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -336,6 +336,9 @@ /* drm_dp_cec_register_connector() wants p,p interface */ #define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DP_DRM_DP_HELPER_H 1 + /* drm_dp_link_train_channel_eq_delay() has 2 args */ #define HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 index d851ad71eab97..49994828e0873 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_AUX_DRM_DEV], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_aux dda; dda.drm_dev = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 index 52f51298caf4d..141e3a6ff65d0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #include + #else #include + #endif ], [ drm_dp_cec_register_connector(NULL, NULL); ], [ @@ -15,7 +19,11 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ [drm_dp_cec* correlation functions are available]) ], [ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #include + #else #include + #endif ], [ drm_dp_cec_irq(NULL); drm_dp_cec_register_connector(NULL, NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 index 664b63498814e..e6713844783e2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 index 4d8e0f733eb7e..af98096981e77 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 index c15c7d3d88eb9..f49bd33a93a19 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #include + #else #include + #endif ], [ drm_dp_send_real_edid_checksum(NULL, 0); ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index b3b69a3e8dea7..da4ac4556d9b7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -50,6 +50,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_aperture.h]) + dnl # + dnl # v5.16-rc5-872-g5b529e8d9c38 + dnl # drm/dp: Move public DisplayPort headers into dp/ + dnl # + AC_KERNEL_CHECK_HEADERS([drm/dp/drm_dp_helper.h]) + dnl # dnl # v5.7-13141-gca5999fde0a1 dnl # mm: introduce include/linux/pgtable.h diff --git a/include/kcl/backport/kcl_drm_dp_helper_backport.h b/include/kcl/backport/kcl_drm_dp_helper_backport.h index 8a932361c9e0e..4c541b78127d7 100644 --- a/include/kcl/backport/kcl_drm_dp_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_helper_backport.h @@ -3,7 +3,6 @@ #define _KCL_DRM_DP_HELPER_BACKPORT_H_ #include -#include /* * commit v4.19-rc1-100-g5ce70c799ac2 diff --git a/include/kcl/header/drm/dp/drm_dp_helper.h b/include/kcl/header/drm/dp/drm_dp_helper.h new file mode 100644 index 0000000000000..9aac78ed61294 --- /dev/null +++ b/include/kcl/header/drm/dp/drm_dp_helper.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DP_DRM_DP_HELPER_H_H_ +#define _KCL_HEADER_DP_DRM_DP_HELPER_H_H_ + +#ifdef HAVE_DRM_DP_DRM_DP_HELPER_H +#include_next +#endif + +#endif diff --git a/include/kcl/kcl_drm_dp_cec.h b/include/kcl/kcl_drm_dp_cec.h index 984b5d320f4fa..b810aae53f69a 100644 --- a/include/kcl/kcl_drm_dp_cec.h +++ b/include/kcl/kcl_drm_dp_cec.h @@ -8,7 +8,11 @@ #ifndef __KCL_KCL_DRM_DP_CEC_H__ #define __KCL_KCL_DRM_DP_CEC_H__ +#ifdef HAVE_DRM_DP_DRM_DP_HELPER_H +#include +#else #include +#endif /* * commit v4.19-rc1-100-g5ce70c799ac2 diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index e379e156b74d9..6168671062032 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -30,7 +30,11 @@ #include #include +#ifdef HAVE_DRM_DP_DRM_DP_HELPER_H +#include +#else #include +#endif #include /* From 7cc853c38a57735ed560d55937a26c035889afe4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 21 Jun 2022 14:06:15 +0800 Subject: [PATCH 0749/2653] drm/amdkcl: test for drm/dp/drm_dp_mst_helper.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 | 8 ++++++++ drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 | 6 +++++- .../amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 | 4 ++++ .../gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 | 4 ++++ .../drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 | 4 ++++ .../gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 | 4 ++++ .../drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 | 4 ++++ .../gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 | 12 ++++++++++++ .../amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 | 4 ++++ .../gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 | 4 ++++ drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 | 12 ++++++++++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ .../m4/drm-up-update-payload-part1-start-slot-arg.m4 | 4 ++++ .../drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 | 4 ++++ .../kcl/backport/kcl_drm_dp_mst_helper_backport.h | 4 ++++ include/kcl/header/drm/dp/drm_dp_mst_helper.h | 9 +++++++++ 17 files changed, 95 insertions(+), 1 deletion(-) create mode 100644 include/kcl/header/drm/dp/drm_dp_mst_helper.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 766f8c57ce815..d515cbafacc5c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -339,6 +339,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DP_DRM_DP_HELPER_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DP_DRM_DP_MST_HELPER_H 1 + /* drm_dp_link_train_channel_eq_delay() has 2 args */ #define HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 index 448c9066f274a..65b49ae69f164 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ int retval; retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0); @@ -18,7 +22,11 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ dnl # drm/dp_mst: Manually overwrite PBN divider for calculating timeslots dnl # AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ int retval; retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0, 0); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 index d168a591bcd23..8dc9ef9c8dd48 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #include + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else + #include + #endif ], [ drm_dp_calc_pbn_mode(0, 0, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 index 1d4564270d065..1f637c137dad1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ int ret; ret = drm_dp_mst_add_affected_dsc_crtcs(NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 index dc4167e33a865..df6b3450485e0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ int ret; ret = drm_dp_mst_atomic_check(NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 index 17422c2217f46..65d24257c4d25 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_mst_atomic_enable_dsc(NULL, NULL, 0, 0, false); ], [drm_dp_mst_atomic_enable_dsc], [drivers/gpu/drm/drm_dp_mst_topology.c], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 index 4198140ed6a0e..913f4586acf6c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DETECT_PORT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ int ret; ret = drm_dp_mst_detect_port(NULL, NULL, NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 index 06d77b61ab828..4c48b47b4c9bf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_mst_dsc_aux_for_port(NULL); ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 index f08316600fcbd..5540428fc8b49 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -4,7 +4,11 @@ dnl # drm/dp-mst-helper: Remove hotplug callback dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG], [ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->hotplug(NULL); @@ -24,7 +28,11 @@ dnl # drm/dp/mst: split connector registration into two parts (v2) dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR], [ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->register_connector(NULL); @@ -40,7 +48,11 @@ dnl # drm/dp_mst: Remove drm_dp_mst_topology_cbs.destroy_connector dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR], [ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->destroy_connector(NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 index 3c491e182062e..039132d5081d7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ int ret; ret = drm_dp_mst_topology_mgr_resume(NULL, 0); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index bd46fb9e30abb..720e605f38d4f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_mst_topology_state * mst_state = NULL; mst_state->total_avail_slots = 0; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 index 5c6393f547854..5065a8ab6d0d6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 @@ -8,7 +8,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_mst_allocate_vcpi(NULL, NULL, 1, 1); ], [ @@ -25,7 +29,11 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_mst_get_port_malloc(NULL); drm_dp_mst_put_port_malloc(NULL); @@ -40,7 +48,11 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_mst_connector_early_unregister(NULL, NULL); drm_dp_mst_connector_late_register(NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index da4ac4556d9b7..db107edff41aa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -56,6 +56,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/dp/drm_dp_helper.h]) + dnl # + dnl # v5.16-rc5-872-g5b529e8d9c38 + dnl # drm/dp: Move public DisplayPort headers into dp/ + dnl # + AC_KERNEL_CHECK_HEADERS([drm/dp/drm_dp_mst_helper.h]) + dnl # dnl # v5.7-13141-gca5999fde0a1 dnl # mm: introduce include/linux/pgtable.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 index 1b341003bb985..0c25016be1da4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_update_payload_part1(NULL, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 index 98d2982594b7c..ca29f48cb467a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_mst_topology_mgr_init(NULL, (struct drm_device *)NULL, NULL, 0, 0, 0, 0, 0); ], [ diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 183e49a5ba766..2412859be272a 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -22,7 +22,11 @@ #ifndef _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ #define _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ +#ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H +#include +#else #include +#endif /* Copied from drivers/gpu/drm/drm_dp_mst_topology.c and modified for KCL */ #if !defined(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS) diff --git a/include/kcl/header/drm/dp/drm_dp_mst_helper.h b/include/kcl/header/drm/dp/drm_dp_mst_helper.h new file mode 100644 index 0000000000000..116be51b87c2c --- /dev/null +++ b/include/kcl/header/drm/dp/drm_dp_mst_helper.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DP_DRM_DP_MST_HELPER_H_H_ +#define _KCL_HEADER_DP_DRM_DP_MST_HELPER_H_H_ + +#ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H +#include_next +#endif + +#endif From 389fd9385ef077a40b916928b543cb88652e147e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 21 Jun 2022 16:28:32 +0800 Subject: [PATCH 0750/2653] drm/amdkcl: Test whether dma_fence_is_container() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../drm/amd/dkms/m4/dma-fence-is-container.m4 | 15 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma-resv.h | 1 + include/kcl/kcl_dma_fence.h | 46 +++++++++++++++++++ include/kcl/kcl_dma_fence_chain.h | 3 ++ include/kcl/kcl_fence_array.h | 11 +++++ 7 files changed, 80 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-is-container.m4 create mode 100644 include/kcl/kcl_dma_fence.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d515cbafacc5c..2909f87ad0340 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -100,6 +100,9 @@ /* whether dma_fence_get_stub exits */ #define HAVE_DMA_FENCE_GET_STUB 1 +/* dma_fence_is_container() is available */ +#define HAVE_DMA_FENCE_IS_CONTAINER 1 + /* struct dma_fence_ops has use_64bit_seqno field */ #define HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-container.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-container.m4 new file mode 100644 index 0000000000000..7c07948aa5205 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-container.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit v5.17-rc2-229-g976b6d97c623 +dnl # dma-buf: consolidate dma_fence subclass checking +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_IS_CONTAINER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_is_container(NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_IS_CONTAINER, 1, [dma_fence_is_container() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index de186e596e0e6..19fd30226e048 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -202,6 +202,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_HYPERVISOR_IS_TYPE AC_AMDGPU_PCI_DEV_LTR_PATH AC_AMDGPU_CANCEL_WORK + AC_AMDGPU_DMA_FENCE_IS_CONTAINER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 0d0ccbbb5d043..0c4850cd6bf95 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -50,6 +50,7 @@ #include #include #include +#include struct dma_resv_list; diff --git a/include/kcl/kcl_dma_fence.h b/include/kcl/kcl_dma_fence.h new file mode 100644 index 0000000000000..cbf594a40d4de --- /dev/null +++ b/include/kcl/kcl_dma_fence.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Fence mechanism for dma-buf to allow for asynchronous dma access + * + * Copyright (C) 2012 Canonical Ltd + * Copyright (C) 2012 Texas Instruments + * + * Authors: + * Rob Clark + * Maarten Lankhorst + */ + +#ifndef AMDKCL_DMA_FENCE_H +#define AMDKCL_DMA_FENCE_H + +#ifndef HAVE_DMA_FENCE_IS_CONTAINER +#include +#include + +/** + * dma_fence_is_chain - check if a fence is from the chain subclass + * @fence: the fence to test + * + * Return true if it is a dma_fence_chain and false otherwise. + */ +static inline bool dma_fence_is_chain(struct dma_fence *fence) +{ + return fence->ops == &dma_fence_chain_ops; +} + +/** + * dma_fence_is_container - check if a fence is a container for other fences + * @fence: the fence to test + * + * Return true if this fence is a container for other fences, false otherwise. + * This is important since we can't build up large fence structure or otherwise + * we run into recursion during operation on those fences. + */ +static inline bool dma_fence_is_container(struct dma_fence *fence) +{ + return dma_fence_is_array(fence) || dma_fence_is_chain(fence); +} + +#endif /* HAVE_DMA_FENCE_IS_CONTAINER */ + +#endif diff --git a/include/kcl/kcl_dma_fence_chain.h b/include/kcl/kcl_dma_fence_chain.h index 4cde69227a3f1..eafcd818c1da3 100644 --- a/include/kcl/kcl_dma_fence_chain.h +++ b/include/kcl/kcl_dma_fence_chain.h @@ -9,6 +9,9 @@ #ifndef AMDKCL_DMA_FENCE_CHAIN_H #define AMDKCL_DMA_FENCE_CHAIN_H +#ifdef HAVE_LINUX_DMA_FENCE_CHAIN_H +#include +#endif #if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) #ifdef HAVE_LINUX_DMA_FENCE_H diff --git a/include/kcl/kcl_fence_array.h b/include/kcl/kcl_fence_array.h index 1e8f37c5864d3..060edd1567fda 100644 --- a/include/kcl/kcl_fence_array.h +++ b/include/kcl/kcl_fence_array.h @@ -76,6 +76,17 @@ static inline struct fence_array *to_fence_array(struct fence *fence) struct fence_array *fence_array_create(int num_fences, struct fence **fences, u64 context, unsigned seqno, bool signal_on_any); +/** + * dma_fence_is_array - check if a fence is from the array subclass + * @fence: the fence to test + * + * Return true if it is a dma_fence_array and false otherwise. + */ +static inline bool dma_fence_is_array(struct dma_fence *fence) +{ + return false; +} + #endif #endif From f4cf8803123fc95f531230da4a7f04ba5c668e97 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 21 Jun 2022 16:57:30 +0800 Subject: [PATCH 0751/2653] drm/amdkcl: Test whether str_yes_no() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 | 16 ++++++++++++ include/kcl/kcl_string_helpers.h | 30 +++++++++++++++++++++++ 5 files changed, 52 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 create mode 100644 include/kcl/kcl_string_helpers.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1846a72101907..42072db6869d3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -94,4 +94,6 @@ #include #include #include +#include + #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2909f87ad0340..d48ab5b611781 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1126,6 +1126,9 @@ /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ +/* str_yes_no() is defined */ +#define HAVE_STR_YES_NO 1 + /* synchronize_shrinkers() is available */ #define HAVE_SYNCHRONIZE_SHRINKERS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 19fd30226e048..09999fab9e0a0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -203,6 +203,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_DEV_LTR_PATH AC_AMDGPU_CANCEL_WORK AC_AMDGPU_DMA_FENCE_IS_CONTAINER + AC_AMDGPU_STR_YES_NO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 b/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 new file mode 100644 index 0000000000000..9ca6f08ae00e7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit ea4692c75e1c63926e4fb0728f5775ef0d733888 +dnl # lib/string_helpers: Consolidate string helpers implementation +dnl # +AC_DEFUN([AC_AMDGPU_STR_YES_NO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + const char *str = str_yes_no(true); + ], [ + AC_DEFINE(HAVE_STR_YES_NO, 1, + [str_yes_no() is defined]) + ]) + ]) +]) diff --git a/include/kcl/kcl_string_helpers.h b/include/kcl/kcl_string_helpers.h new file mode 100644 index 0000000000000..ceac153f44bfd --- /dev/null +++ b/include/kcl/kcl_string_helpers.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_STRING_HELPERS_H +#define AMDKCL_STRING_HELPERS_H + + +/* Copied from v5.17-rc2-224-gea4692c75e1c linux/string_helpers.h */ + +#ifndef HAVE_STR_YES_NO +static inline const char *str_yes_no(bool v) +{ + return v ? "yes" : "no"; +} + +static inline const char *str_on_off(bool v) +{ + return v ? "on" : "off"; +} + +static inline const char *str_enable_disable(bool v) +{ + return v ? "enable" : "disable"; +} + +static inline const char *str_enabled_disabled(bool v) +{ + return v ? "enabled" : "disabled"; +} + +#endif /* HAVE_STR_YES_NO */ +#endif From f007ac638659c2bd9476a2aef6b4ba9f4f6dc713 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 21 Mar 2024 11:27:12 +0800 Subject: [PATCH 0752/2653] drm/amdkcl: Test whether struct drm_mode_config has member fb_modifiers_not_supported Signed-off-by: Leslie Shi Signed-off-by: Ma Jun Change-Id: I37f2cbc1e506f97d09a4850d0b92dabcf4121a88 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 12 ++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 ++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 10 files changed, 44 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 8406fbbd364bc..cd5edab6b135e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1293,7 +1293,11 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) int ret; unsigned int i, block_width, block_height, block_size_log2; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED if (rfb->base.dev->mode_config.fb_modifiers_not_supported) +#else + if (!rfb->base.dev->mode_config.allow_fb_modifiers) +#endif return 0; for (i = 0; i < format_info->num_planes; ++i) { @@ -1521,7 +1525,11 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, return ret; #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) { +#else + if (!dev->mode_config.allow_fb_modifiers && !adev->enable_virtual_display) { +#endif drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI, "GFX9+ requires FB check based on format modifier\n"); ret = check_tiling_flags_gfx6(rfb); @@ -1529,7 +1537,11 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, return ret; } +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED if (!dev->mode_config.fb_modifiers_not_supported && +#else + if (dev->mode_config.allow_fb_modifiers && +#endif !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) { if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ret = convert_tiling_flags_to_modifier_gfx12(rfb); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index cd1b543130719..278ea8f596d83 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2916,7 +2916,9 @@ static int dce_v10_0_sw_init(struct amdgpu_ip_block *ip_block) adev_to_drm(adev)->mode_config.preferred_depth = 24; adev_to_drm(adev)->mode_config.prefer_shadow = 1; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; +#endif r = amdgpu_display_modeset_create_props(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 0fb757dc31e1e..c9867a927c8ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -3042,7 +3042,9 @@ static int dce_v11_0_sw_init(struct amdgpu_ip_block *ip_block) adev_to_drm(adev)->mode_config.preferred_depth = 24; adev_to_drm(adev)->mode_config.prefer_shadow = 1; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; +#endif r = amdgpu_display_modeset_create_props(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 6b3cb2fa26af3..11643f7194683 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2873,7 +2873,9 @@ static int dce_v6_0_sw_init(struct amdgpu_ip_block *ip_block) adev_to_drm(adev)->mode_config.max_height = 16384; adev_to_drm(adev)->mode_config.preferred_depth = 24; adev_to_drm(adev)->mode_config.prefer_shadow = 1; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; +#endif r = amdgpu_display_modeset_create_props(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index ff7df7da69f70..255ca61e82990 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2833,7 +2833,9 @@ static int dce_v8_0_sw_init(struct amdgpu_ip_block *ip_block) else adev_to_drm(adev)->mode_config.prefer_shadow = 1; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; +#endif r = amdgpu_display_modeset_create_props(adev); if (r) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2927a6000869b..d2a2a8c9bea0c 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8050,7 +8050,6 @@ int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) return 0; } #endif - static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 1929ad52d04e4..58166f2fed938 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1881,8 +1881,10 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, return res; #endif +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED if (modifiers == NULL) adev_to_drm(dm->adev)->mode_config.fb_modifiers_not_supported = true; +#endif res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs, &dm_plane_funcs, formats, num_formats, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d48ab5b611781..b16a47d3e74e1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -602,6 +602,9 @@ /* drm_mode_config->dp_subconnector_property is available */ #define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 +/* drm_mode_config->fb_modifiers_not_supported is available */ +#define HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED 1 + /* drm_mode_config_funcs->atomic_state_alloc() is available */ #define HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 new file mode 100644 index 0000000000000..add5633e0f26f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 @@ -0,0 +1,18 @@ +AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_mode_config *mode_config = NULL; + mode_config->fb_modifiers_not_supported = true; + ], [ + AC_DEFINE(HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED, 1, + [drm_mode_config->fb_modifiers_not_supported is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG], [ + AC_AMDGPU_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 09999fab9e0a0..173bb79f98406 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -122,6 +122,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS AC_AMDGPU_DRM_CONNECTOR_HAVE_HDR_SINK_METADATA AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT + AC_AMDGPU_DRM_MODE_CONFIG AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_JIFFIES64_TO_MSECS From 71953a56bf5e52d506f2cb6f66202ebd7c10d591 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 22 Jun 2022 13:12:12 +0800 Subject: [PATCH 0753/2653] drm/amdkcl: Test whether dma_fence_chain_contained is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma_fence_chain.h | 17 +++++++++++++++++ 4 files changed, 38 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b16a47d3e74e1..6c4aedb8cfc8b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1047,6 +1047,9 @@ /* struct dma_fence_chain is available */ #define HAVE_STRUCT_DMA_FENCE_CHAIN 1 +/* dma_fence_chain_contained() is available */ +#define HAVE_DMA_FENCE_CHAIN_CONTAINED 1 + /* struct drm_connector_state->duplicated is available */ #define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 index 34231d5d2028d..7867a6283d95f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 @@ -32,3 +32,20 @@ AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT], [ ]) ]) +dnl # +dnl # v5.17-rc2-233-g18f5fad275ef +dnl # dma-buf: add dma_fence_chain_contained helper +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_chain_contained(NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_CHAIN_CONTAINED, 1, + [dma_fence_chain_contained() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 173bb79f98406..f620c3aaf4864 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -205,6 +205,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CANCEL_WORK AC_AMDGPU_DMA_FENCE_IS_CONTAINER AC_AMDGPU_STR_YES_NO + AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_dma_fence_chain.h b/include/kcl/kcl_dma_fence_chain.h index eafcd818c1da3..b7b66a3b93c90 100644 --- a/include/kcl/kcl_dma_fence_chain.h +++ b/include/kcl/kcl_dma_fence_chain.h @@ -123,4 +123,21 @@ static inline void dma_fence_chain_free(struct dma_fence_chain *chain) #endif +#ifndef HAVE_DMA_FENCE_CHAIN_CONTAINED +/** + * dma_fence_chain_contained - return the contained fence + * @fence: the fence to test + * + * If the fence is a dma_fence_chain the function returns the fence contained + * inside the chain object, otherwise it returns the fence itself. + */ +static inline struct dma_fence * +dma_fence_chain_contained(struct dma_fence *fence) +{ + struct dma_fence_chain *chain = to_dma_fence_chain(fence); + + return chain ? chain->fence : fence; +} +#endif /* HAVE_DMA_FENCE_CHAIN_CONTAINED */ + #endif From 68ecaa7bf2e003806672a8d4abe8add647cffda2 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 23 Jun 2022 14:59:24 +0800 Subject: [PATCH 0754/2653] drm/amdkcl: add DRM_COLOR_FORMAT_YCRCB enums This is caused by c03d0b52ff71 "drm/connector: Fix typo in output format" v5.16-rc5-909-gc03d0b52ff71 Signed-off-by: Leslie Shi --- include/kcl/kcl_drm_connector.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index d77022ef022ac..96e58541b57a4 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -121,4 +121,16 @@ int drm_connector_set_panel_orientation_with_quirk( } #endif +#ifndef DRM_COLOR_FORMAT_YCBCR444 +#define DRM_COLOR_FORMAT_YCBCR444 (1<<1) +#endif + +#ifndef DRM_COLOR_FORMAT_YCBCR422 +#define DRM_COLOR_FORMAT_YCBCR422 (1<<2) +#endif + +#ifndef DRM_COLOR_FORMAT_YCBCR420 +#define DRM_COLOR_FORMAT_YCBCR420 (1<<3) +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From ab0ed054e4479f5faf5f6af98ccc6d06f0562558 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Mar 2024 12:24:06 +0800 Subject: [PATCH 0755/2653] drm/amdkcl: wrap code under macro CONFIG_DRM_AMD_DC_DSC_SUPPORT Signed-off-by: Leslie Shi Signed-off-by: Ma Jun Change-Id: I319776ac36ade90de99d03e520d6426efd7c31c4 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++-- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 9 ++++- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 4 +++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 6 ++-- drivers/gpu/drm/amd/display/dc/core/dc.c | 13 +++++++ .../gpu/drm/amd/display/dc/core/dc_resource.c | 6 ++++ .../gpu/drm/amd/display/dc/core/dc_stream.c | 4 +++ drivers/gpu/drm/amd/display/dc/dc.h | 4 +++ drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 ++ drivers/gpu/drm/amd/display/dc/dc_types.h | 2 ++ drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 5 ++- .../display/dc/dcn201/dcn201_link_encoder.c | 2 ++ .../amd/display/dc/dcn21/dcn21_link_encoder.c | 2 ++ .../display/dc/dio/dcn20/dcn20_link_encoder.c | 8 ++++- .../display/dc/dio/dcn20/dcn20_link_encoder.h | 2 ++ .../dc/dio/dcn20/dcn20_stream_encoder.c | 7 +++- .../dc/dio/dcn30/dcn30_dio_link_encoder.c | 2 ++ .../dc/dio/dcn30/dcn30_dio_stream_encoder.c | 4 +++ .../dc/dio/dcn31/dcn31_dio_link_encoder.c | 4 +++ .../dc/dio/dcn314/dcn314_dio_stream_encoder.c | 4 +++ .../dc/dio/dcn32/dcn32_dio_link_encoder.c | 2 ++ .../dc/dio/dcn32/dcn32_dio_stream_encoder.c | 3 ++ .../dc/dio/dcn321/dcn321_dio_link_encoder.c | 2 ++ .../amd/display/dc/dml/display_mode_enums.h | 2 ++ .../drm/amd/display/dc/dml/dsc/rc_calc_fpu.c | 3 +- .../drm/amd/display/dc/dml/dsc/rc_calc_fpu.h | 2 ++ drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 2 ++ .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 2 ++ .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h | 3 +- drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 2 ++ .../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 3 +- .../hpo/dcn31/dcn31_hpo_dp_stream_encoder.c | 2 ++ .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 4 +++ .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 8 +++++ .../amd/display/dc/hwss/dcn20/dcn20_hwseq.h | 2 ++ .../amd/display/dc/hwss/dcn20/dcn20_init.c | 4 +++ .../amd/display/dc/hwss/dcn21/dcn21_init.c | 2 ++ .../amd/display/dc/hwss/dcn30/dcn30_init.c | 2 ++ .../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 2 ++ .../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 4 +++ .../amd/display/dc/hwss/dcn314/dcn314_init.c | 2 ++ .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 3 +- .../gpu/drm/amd/display/dc/inc/core_types.h | 5 ++- .../drm/amd/display/dc/inc/hw/link_encoder.h | 4 +++ .../amd/display/dc/inc/hw/timing_generator.h | 2 ++ .../dc/link/protocols/link_dp_training_dpia.c | 2 ++ .../amd/display/dc/optc/dcn20/dcn20_optc.c | 9 +++++ .../amd/display/dc/optc/dcn20/dcn20_optc.h | 2 ++ .../amd/display/dc/optc/dcn201/dcn201_optc.c | 2 ++ .../amd/display/dc/optc/dcn30/dcn30_optc.c | 4 +++ .../amd/display/dc/optc/dcn30/dcn30_optc.h | 2 ++ .../amd/display/dc/optc/dcn314/dcn314_optc.c | 2 ++ .../amd/display/dc/optc/dcn32/dcn32_optc.c | 2 ++ .../dc/resource/dcn20/dcn20_resource.c | 36 +++++++++++++++---- .../dc/resource/dcn20/dcn20_resource.h | 2 ++ .../dc/resource/dcn201/dcn201_resource.c | 2 ++ .../dc/resource/dcn21/dcn21_resource.c | 15 +++++++- .../dc/resource/dcn30/dcn30_resource.c | 22 ++++++++++++ .../dc/resource/dcn301/dcn301_resource.c | 2 ++ .../dc/resource/dcn314/dcn314_resource.c | 10 ++++++ .../dc/resource/dcn315/dcn315_resource.c | 14 ++++++++ .../dc/resource/dcn316/dcn316_resource.c | 15 ++++++++ .../dc/resource/dcn32/dcn32_resource.c | 10 ++++++ .../resource/dcn32/dcn32_resource_helpers.c | 2 ++ .../dc/virtual/virtual_stream_encoder.c | 8 +++++ 65 files changed, 311 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d2a2a8c9bea0c..b75a3aa0848a5 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7154,7 +7154,6 @@ create_stream_for_sink(struct drm_connector *connector, if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); #endif - update_stream_scaling_settings(&mode, dm_state, stream); fill_audio_info( @@ -12031,10 +12030,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, bool lock_and_validation_needed = false; bool is_top_most_overlay = true; struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct drm_dp_mst_topology_mgr *mgr; struct drm_dp_mst_topology_state *mst_state; struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; - +#endif trace_amdgpu_dm_atomic_check_begin(state); ret = drm_atomic_helper_check_modeset(dev, state); @@ -12362,6 +12362,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS /* set the slot info for each mst_state based on the link encoding format */ for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { @@ -12382,6 +12383,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } drm_connector_list_iter_end(&iter); } +#endif #endif /** * Streams and planes are reset when there are changes that affect diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 1a1f37b3517e8..776c12442de41 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -1361,6 +1361,7 @@ static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *b * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support * */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static int dp_dsc_fec_support_show(struct seq_file *m, void *data) { struct drm_connector *connector = m->private; @@ -1416,6 +1417,7 @@ static int dp_dsc_fec_support_show(struct seq_file *m, void *data) return ret; } +#endif /* function: Trigger virtual HPD redetection on connector * @@ -1561,6 +1563,7 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, * 1 - means that DSC is currently enabled * 0 - means that DSC is disabled */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { @@ -2531,7 +2534,7 @@ static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, kfree(rd_buf); return result; } - +#endif /* * function description: Read max_requested_bpc property from the connector @@ -2938,6 +2941,7 @@ DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); DEFINE_SHOW_ATTRIBUTE(is_dpia_link); DEFINE_SHOW_STORE_ATTRIBUTE(hdmi_cec_state); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static const struct file_operations dp_dsc_clock_en_debugfs_fops = { .owner = THIS_MODULE, .read = dp_dsc_clock_en_read, @@ -2989,6 +2993,7 @@ static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { .read = dp_dsc_slice_bpg_offset_read, .llseek = default_llseek }; +#endif static const struct file_operations trigger_hotplug_debugfs_fops = { .owner = THIS_MODULE, @@ -3062,6 +3067,8 @@ static const struct { {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, +#endif + {"max_bpc", &dp_max_bpc_debugfs_fops}, {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, {"is_mst_connector", &dp_is_mst_connector_fops}, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 9667312bb9513..bb8037a626413 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -668,6 +668,7 @@ bool dm_helpers_execute_fused_io( return amdgpu_dm_execute_fused_io(dev, link, commands, count, timeout_us); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, bool is_write_cmd, unsigned char cmd, @@ -845,7 +846,9 @@ static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( return ret; } +#endif +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool dm_helpers_dp_write_dsc_enable( struct dc_context *ctx, const struct dc_stream_state *stream, @@ -928,6 +931,7 @@ bool dm_helpers_dp_write_dsc_enable( return ret; } +#endif bool dm_helpers_dp_write_hblank_reduction(struct dc_context *ctx, const struct dc_stream_state *stream) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 3349e6d8a98a1..e0fd4f4b6b64c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -268,6 +268,8 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { #endif /* HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER */ }; +#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) +#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) bool needs_dsc_aux_workaround(struct dc_link *link) { if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && @@ -302,9 +304,7 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 u8 *dsc_branch_dec_caps = NULL; -#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port); -#endif /* * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs * because it only check the dsc/fec caps of the "port variable" and not the dock @@ -359,6 +359,8 @@ static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnect return true; } +#endif +#endif static int dm_dp_mst_get_modes(struct drm_connector *connector) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index cf3893a2f8ce3..f058319219365 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -66,7 +66,9 @@ #include "dc_dmub_srv.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dsc.h" +#endif #include "vm_helper.h" @@ -719,7 +721,9 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, param.windowb_y_end = crc_window->windowb_y_end; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0; +#endif param.odm_mode = pipe->next_odm_pipe ? 1:0; /* Default to the union of both windows */ @@ -2953,8 +2957,10 @@ static enum surface_update_type check_update_surfaces_for_stream( if (stream_update->wb_update) su_flags->bits.wb_update = 1; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (stream_update->dsc_config) su_flags->bits.dsc_changed = 1; +#endif if (stream_update->mst_bw_update) su_flags->bits.mst_bw = 1; @@ -3207,7 +3213,9 @@ static void copy_stream_update_to_stream(struct dc *dc, struct dc_stream_state *stream, struct dc_stream_update *update) { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_context *dc_ctx = dc->ctx; +#endif if (update == NULL || stream == NULL) return; @@ -3308,6 +3316,8 @@ static void copy_stream_update_to_stream(struct dc *dc, stream->writeback_info[i] = update->wb_update->writeback_info[i]; } + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (update->dsc_config) { struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg; uint32_t old_dsc_enabled = stream->timing.flags.DSC; @@ -3333,6 +3343,7 @@ static void copy_stream_update_to_stream(struct dc *dc, update->dsc_config = NULL; } } +#endif if (update->scaler_sharpener_update) stream->scaler_sharpener_update = *update->scaler_sharpener_update; if (update->sharpening_required) @@ -3634,8 +3645,10 @@ static void commit_planes_do_stream_update(struct dc *dc, if (update_type == UPDATE_TYPE_FAST) continue; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (stream_update->dsc_config) dc->link_srv->update_dsc_config(pipe_ctx); +#endif if (stream_update->mst_bw_update) { if (stream_update->mst_bw_update->is_increase) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 4d6181e7c612b..54ae2faaa94e6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -3983,7 +3983,11 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc) if (dc->res_pool == NULL) return false; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT return dc->res_pool->res_cap->num_dsc > 0; +#else + return 0; +#endif } static bool planes_changed_for_existing_stream(struct dc_state *context, @@ -4904,8 +4908,10 @@ bool pipe_need_reprogram( false == pipe_ctx_old->stream->dpms_off) return true; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc) return true; +#endif if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc) return true; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 4d6bc9fd4faa8..73c02d581133a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -111,6 +111,7 @@ bool dc_stream_construct(struct dc_stream_state *stream, /* EDID CAP translation for HDMI 2.0 */ stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); stream->timing.dsc_cfg.num_slices_h = 0; stream->timing.dsc_cfg.num_slices_v = 0; @@ -119,6 +120,7 @@ bool dc_stream_construct(struct dc_stream_state *stream, stream->timing.dsc_cfg.linebuf_depth = 9; stream->timing.dsc_cfg.version_minor = 2; stream->timing.dsc_cfg.ycbcr422_simple = 0; +#endif update_stream_signal(stream, dc_sink_data); @@ -789,6 +791,7 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc, return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, struct dc_state *state, struct dc_stream_state *stream) @@ -799,6 +802,7 @@ enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, return DC_NO_DSC_RESOURCE; } } +#endif struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5653c1673aece..314de71706b33 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -963,6 +963,7 @@ struct dc_debug_options { bool disable_dfs_bypass; bool disable_dpp_power_gate; bool disable_hubp_power_gate; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool disable_dsc_power_gate; bool disable_optc_power_gate; bool disable_hpo_power_gate; @@ -971,6 +972,7 @@ struct dc_debug_options { bool disable_dio_power_gate; int dsc_min_slice_height_override; int dsc_bpp_increment_div; +#endif bool disable_pplib_wm_range; enum wm_report_mode pplib_wm_report_mode; unsigned int min_disp_clk_khz; @@ -2473,6 +2475,7 @@ struct dc_container_id { }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_sink_dsc_caps { // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), // 'false' if they are sink's DSC caps @@ -2482,6 +2485,7 @@ struct dc_sink_dsc_caps { bool is_dsc_passthrough_supported; struct dsc_dec_dpcd_caps dsc_dec_caps; }; +#endif struct dc_sink_hblank_expansion_caps { // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 5fc6fea211de3..1034e0fed5932 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -445,9 +445,11 @@ bool dc_stream_remove_writeback(struct dc *dc, struct dc_stream_state *stream, uint32_t dwb_pipe_inst); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, struct dc_state *state, struct dc_stream_state *stream); +#endif bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream); diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 2e2dea21b3321..e68d25be0f779 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -542,7 +542,9 @@ enum dc_infoframe_type { DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DC_DP_INFOFRAME_TYPE_PPS = 0x10, +#endif }; struct dc_info_packet { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index ff3b8244ba3d0..9839dd8468554 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -379,8 +379,9 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us; copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; copy_settings_data->panel_inst = panel_inst; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1); - +#endif /** * WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update) * Note that PSRSU+DSC is still under development. @@ -393,6 +394,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (((link->dpcd_caps.fec_cap.bits.FEC_CAPABLE && !link->dc->debug.disable_fec) && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && @@ -405,6 +407,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, sizeof(DP_SINK_DEVICE_STR_ID_2)))) copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 1; else +#endif copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 0; if (link->psr_settings.psr_version == DC_PSR_VERSION_1 && diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c index 8d31fa131cd60..789d6800ff08c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c @@ -77,7 +77,9 @@ static bool dcn201_link_encoder_is_in_alt_mode(struct link_encoder *enc) } static const struct link_encoder_funcs dcn201_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c index eb9abb9f96986..24fedaf5df408 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c @@ -298,7 +298,9 @@ static void dcn21_link_encoder_disable_output(struct link_encoder *enc, static const struct link_encoder_funcs dcn21_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c index 51a57dae18114..d1518602a1702 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c @@ -173,8 +173,10 @@ static struct mpll_cfg dcn2_mpll_cfg[] = { void enc2_fec_set_enable(struct link_encoder *enc, bool enable) { struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DC_LOG_DSC("%s FEC at link encoder inst %d", enable ? "Enabling" : "Disabling", enc->id.enum_id); +#endif REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable); } @@ -194,7 +196,8 @@ bool enc2_fec_is_active(struct link_encoder *enc) return (active != 0); } - + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* this function reads dsc related register fields to be logged later in dcn10_log_hw_state * into a dcn_dsc_state struct. */ @@ -207,6 +210,7 @@ void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s) REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete); } +#endif static bool update_cfg_data( struct dcn10_link_encoder *enc10, @@ -356,7 +360,9 @@ void enc2_hw_init(struct link_encoder *enc) } static const struct link_encoder_funcs dcn20_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h index 762c579fcb44d..39a5f6882cf95 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h @@ -342,7 +342,9 @@ void enc2_fec_set_ready(struct link_encoder *enc, bool ready); bool enc2_fec_is_active(struct link_encoder *enc); void enc2_hw_init(struct link_encoder *enc); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s); +#endif void dcn20_link_encoder_enable_dp_output( struct link_encoder *enc, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c index 0b47aeb60e795..2fa2816e28aa0 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c @@ -207,7 +207,7 @@ static void enc2_stream_encoder_stop_hdmi_info_packets( HDMI_GENERIC7_LINE, 0); } - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Update GSP7 SDP 128 byte long */ static void enc2_update_gsp7_128_info_packet( struct dcn10_stream_encoder *enc1, @@ -365,6 +365,7 @@ static void enc2_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } +#endif /* Set Dynamic Metadata-configuration. * enable_dme: TRUE: enables Dynamic Metadata Enfine, FALSE: disables DME @@ -460,8 +461,10 @@ static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing) { bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 && !timing->dsc_cfg.ycbcr422_simple); +#endif return two_pix; } @@ -632,9 +635,11 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc2_read_state, .dp_set_dsc_config = enc2_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet, +#endif .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, .get_fifo_cal_average_level = enc2_get_fifo_cal_average_level, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c index b8e31b5ea1140..504b70931b701 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c @@ -56,7 +56,9 @@ bool dcn30_link_encoder_validate_output_with_stream( } static const struct link_encoder_funcs dcn30_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc3_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c index e93be7b6d9b03..106e963256c44 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c @@ -295,6 +295,7 @@ void enc3_stream_encoder_stop_hdmi_info_packets( HDMI_GENERIC14_LINE, 0); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: Bytes per pixel in u3.28 format @@ -401,6 +402,7 @@ static void enc3_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } +#endif void enc3_stream_encoder_update_dp_info_packets_sdp_line_num( struct stream_encoder *enc, @@ -865,9 +867,11 @@ static const struct stream_encoder_funcs dcn30_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc3_read_state, .dp_set_dsc_config = enc3_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, +#endif .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c index 127760c096d56..5abed61b96860 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c @@ -484,7 +484,9 @@ void dcn31_link_encoder_enable_dp_output( if (link) { dpia_control.dpia_id = link->ddc_hw_inst; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dpia_control.fec_rdy = link->dc->link_srv->dp_should_enable_fec(link); +#endif } else { DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__); BREAK_TO_DEBUGGER(); @@ -531,7 +533,9 @@ void dcn31_link_encoder_enable_dp_mst_output( if (link) { dpia_control.dpia_id = link->ddc_hw_inst; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dpia_control.fec_rdy = link->dc->link_srv->dp_should_enable_fec(link); +#endif } else { DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__); BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c index ae81451a3a725..6bb66e4d37e02 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c @@ -384,6 +384,7 @@ void enc314_stream_encoder_dp_unblank( link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32 @@ -418,6 +419,7 @@ void enc314_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } +#endif void enc314_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container) { @@ -469,9 +471,11 @@ static const struct stream_encoder_funcs dcn314_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc314_read_state, .dp_set_dsc_config = enc314_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, +#endif .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c index 06907e8a4eda1..cfcd48a67c760 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c @@ -195,7 +195,9 @@ void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc, static const struct link_encoder_funcs dcn32_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc32_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c index 1a9bb614c41e0..173225fcdb6b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c @@ -346,6 +346,7 @@ void enc32_stream_encoder_dp_unblank( link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32 @@ -380,6 +381,7 @@ static void enc32_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } +#endif static void enc32_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container) { @@ -458,6 +460,7 @@ static const struct stream_encoder_funcs dcn32_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc32_read_state, .dp_set_dsc_config = enc32_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c index 2ed382a8e79c6..b555264990f6b 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c @@ -60,7 +60,9 @@ dm_write_reg(CTX, AUX_REG(reg_name), val) static const struct link_encoder_funcs dcn321_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc32_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h index d5831a34f5a19..8975cd1529fa3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h @@ -174,7 +174,9 @@ enum dm_validation_status { DML_FAIL_DIO_SUPPORT, DML_FAIL_NOT_ENOUGH_DSC, DML_FAIL_DSC_CLK_REQUIRED, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DML_FAIL_DSC_VALIDATION_FAILURE, +#endif DML_FAIL_URGENT_LATENCY, DML_FAIL_REORDERING_BUFFER, DML_FAIL_DISPCLK_DPPCLK, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c index ef75eb7d5adc3..e14e11ccf7d08 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c @@ -23,6 +23,7 @@ * */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "rc_calc_fpu.h" #include "qp_tables.h" @@ -257,4 +258,4 @@ void _do_calc_rc_params(struct rc_params *rc, rc->rc_buf_thresh[12] = 8000; rc->rc_buf_thresh[13] = 8064; } - +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h index d7cd8cc247583..0b70eb9bcc6b9 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h +++ b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h @@ -23,6 +23,7 @@ * */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifndef __RC_CALC_FPU_H__ #define __RC_CALC_FPU_H__ @@ -88,3 +89,4 @@ void _do_calc_rc_params(struct rc_params *rc, int minor_version); #endif +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 1f53a9f0c0ac3..1c8711a4b88e9 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -22,6 +22,7 @@ * Author: AMD */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include #include #include "dc_hw_types.h" @@ -1452,3 +1453,4 @@ void dc_dsc_get_default_config_option(const struct dc *dc, struct dc_dsc_config_ options->slice_height_granularity = 1; options->force_dsc_when_not_needed = false; } +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c index bd1b9aef6d5c8..427cd2301372d 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c @@ -23,6 +23,7 @@ * */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include #include "reg_helper.h" @@ -765,3 +766,4 @@ static void dsc_write_to_registers(struct display_stream_compressor *dsc, const RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); } +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h index a9c04fc95bd11..582c8deb5c47a 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h @@ -21,6 +21,7 @@ * Authors: AMD * */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifndef __DCN20_DSC_H__ #define __DCN20_DSC_H__ @@ -615,4 +616,4 @@ void dsc2_disconnect(struct display_stream_compressor *dsc); void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc); #endif - +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c index 64cee8c80110c..d61b6430a6409 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c @@ -1,3 +1,4 @@ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* * Copyright 2017 Advanced Micro Devices, Inc. @@ -62,3 +63,4 @@ void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps) DC_FP_END(); #endif } +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c index 59864130cf83b..b01295c412b1d 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c @@ -1,3 +1,4 @@ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* * Copyright 2012-17 Advanced Micro Devices, Inc. * @@ -119,4 +120,4 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, dsc_params->rc_buffer_model_size = dsc_cfg.rc_bits; return ret; } - +#endif diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c index 759b453385c46..7b181d4f959b2 100644 --- a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c @@ -564,7 +564,9 @@ static void dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet( /* Load PPS into infoframe (SDP) registers */ pps_sdp.valid = true; pps_sdp.hb0 = 0; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS; +#endif pps_sdp.hb2 = 127; pps_sdp.hb3 = 0; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 39910f73ecd06..04ce194010ef9 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -49,7 +49,9 @@ #include "clk_mgr.h" #include "link_hwss.h" #include "dpcd_defs.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dsc.h" +#endif #include "dce/dmub_psr.h" #include "dc_dmub_srv.h" #include "dce/dmub_hw_lock_mgr.h" @@ -644,6 +646,7 @@ void dcn10_log_hw_state(struct dc *dc, } DTN_INFO("\n"); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT // dcn_dsc_state struct field bytes_per_pixel was renamed to bits_per_pixel // TODO: Update golden log header to reflect this name change DTN_INFO("DSC: CLOCK_EN SLICE_WIDTH Bytes_pp\n"); @@ -700,6 +703,7 @@ void dcn10_log_hw_state(struct dc *dc, } } DTN_INFO("\n"); +#endif DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n" "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n", diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 7d24fa1517bf1..55dd8f52e40e3 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -32,7 +32,9 @@ #include "dcn20/dcn20_resource.h" #include "dcn20_hwseq.h" #include "dce/dce_hwseq.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" +#endif #include "dcn20/dcn20_optc.h" #include "abm.h" #include "clk_mgr.h" @@ -471,6 +473,7 @@ void dcn20_init_blank( hws->funcs.wait_for_blank_complete(opp); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn20_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -547,6 +550,7 @@ void dcn20_dsc_pg_control( if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } +#endif void dcn20_dpp_pg_control( struct dce_hwseq *hws, @@ -2604,6 +2608,7 @@ bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dce_hwseq *hws = dc->hwseq; if (pipe_ctx->stream_res.dsc) { @@ -2615,10 +2620,12 @@ void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) odm_pipe = odm_pipe->next_odm_pipe; } } +#endif } void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dce_hwseq *hws = dc->hwseq; if (pipe_ctx->stream_res.dsc) { @@ -2630,6 +2637,7 @@ void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) odm_pipe = odm_pipe->next_odm_pipe; } } +#endif } void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h index 9d1ad3b29ca52..1424a0f2c09d8 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h @@ -130,10 +130,12 @@ void dcn20_init_vm_ctx( void dcn20_set_flip_control_gsl( struct pipe_ctx *pipe_ctx, bool flip_immediate); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn20_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on); +#endif void dcn20_fpga_init_hw(struct dc *dc); bool dcn20_wait_for_blank_complete( struct output_pixel_processor *opp); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c index ad253c586ea1a..8ad1455284fc9 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c @@ -129,7 +129,11 @@ static const struct hwseq_private_funcs dcn20_private_funcs = { .dpp_pg_control = dcn20_dpp_pg_control, .hubp_pg_control = dcn20_hubp_pg_control, .update_odm = dcn20_update_odm, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, +#else + .dsc_pg_control = NULL, +#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c index c7701a8b574aa..46b06ea163ced 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c @@ -132,7 +132,9 @@ static const struct hwseq_private_funcs dcn21_private_funcs = { .dpp_pg_control = dcn20_dpp_pg_control, .hubp_pg_control = dcn20_hubp_pg_control, .update_odm = dcn20_update_odm, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, +#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c index 2ac5d54d16269..2d92ff4ababb8 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c @@ -138,7 +138,9 @@ static const struct hwseq_private_funcs dcn30_private_funcs = { .hubp_pg_control = dcn20_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, +#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index a3bdaca7d3e5b..5f148e79319ab 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -365,8 +365,10 @@ void dcn31_enable_power_gating_plane( REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); force_on = true; /* disable power gating */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) force_on = false; +#endif /* DCS0/1/2/3/4/5 */ REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c index e68f21fd5f0fb..677499078988e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c @@ -221,6 +221,7 @@ void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn314_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -291,6 +292,7 @@ void dcn314_dsc_pg_control( } } +#endif void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) { @@ -311,8 +313,10 @@ void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); force_on = true; /* disable power gating */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) force_on = false; +#endif /* DCS0/1/2/3/4 */ REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c index f5112742edf9b..6544d15917a49 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c @@ -143,7 +143,9 @@ static const struct hwseq_private_funcs dcn314_private_funcs = { .hubp_pg_control = dcn31_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn314_update_odm, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn314_dsc_pg_control, +#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index 416b1dca3dac9..636da9084b02c 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -66,6 +66,7 @@ #define FN(reg_name, field_name) \ hws->shifts->field_name, hws->masks->field_name +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn32_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -128,7 +129,7 @@ void dcn32_dsc_pg_control( if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } - +#endif void dcn32_enable_power_gating_plane( struct dce_hwseq *hws, diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 4387de044469b..725079acc10c6 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -200,10 +200,11 @@ struct resource_funcs { const struct resource_pool *pool, struct dc_3dlut **lut, struct dc_transfer_func **shaper); - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status (*add_dsc_to_stream_resource)( struct dc *dc, struct dc_state *state, struct dc_stream_state *stream); +#endif void (*add_phantom_pipes)( struct dc *dc, @@ -264,7 +265,9 @@ struct resource_pool { unsigned int gsl_2:1; } gsl_groups; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct display_stream_compressor *dscs[MAX_PIPES]; +#endif unsigned int pipe_count; unsigned int underlay_pipe_index; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 08c16ba52a51f..42bc4a0bdf823 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -89,6 +89,7 @@ struct link_encoder { bool usbc_combo_phy; }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct link_enc_state { uint32_t dphy_fec_en; @@ -97,6 +98,7 @@ struct link_enc_state { uint32_t dp_link_training_complete; }; +#endif enum encoder_type_select { ENCODER_TYPE_DIG = 0, @@ -105,8 +107,10 @@ enum encoder_type_select { }; struct link_encoder_funcs { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void (*read_state)( struct link_encoder *enc, struct link_enc_state *s); +#endif bool (*validate_output_with_stream)( struct link_encoder *enc, const struct dc_stream_state *stream); void (*hw_init)(struct link_encoder *enc); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 267ace4eef8a3..64cd9d345a359 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -136,7 +136,9 @@ struct crc_params { enum crc_selection selection; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT uint8_t dsc_mode; +#endif uint8_t odm_mode; bool continuous_mode; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c index 603537ffd1284..04fdc70ae6da3 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c @@ -101,7 +101,9 @@ static enum link_training_result dpia_configure_link( struct link_training_settings *lt_settings) { enum dc_status status; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool fec_enable; +#endif DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) configuring\n - LTTPR mode(%d)\n", __func__, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c index e7a90a437fffb..d3d3fadce5dab 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c @@ -124,6 +124,7 @@ void optc2_set_gsl_source_select( } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: Bytes per pixel in u3.28 format @@ -145,6 +146,7 @@ void optc2_set_dsc_config(struct timing_generator *optc, REG_UPDATE(OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, dsc_slice_width); } +#endif /* Get DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format @@ -487,9 +489,14 @@ bool optc2_configure_crc(struct timing_generator *optc, { struct optc *optc1 = DCN10TG_FROM_TG(optc); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT REG_SET_2(OTG_CRC_CNTL2, 0, OTG_CRC_DSC_MODE, params->dsc_mode, OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode); +#else + REG_SET(OTG_CRC_CNTL2, 0, + OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode); +#endif return optc1_configure_crc(optc, params); } @@ -548,7 +555,9 @@ static const struct timing_generator_funcs dcn20_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc2_set_dsc_config, +#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = optc2_set_dwb_source, .set_odm_bypass = optc2_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h index 928e110b95fb5..09f16dc1c5048 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h @@ -98,10 +98,12 @@ void optc2_set_gsl_source_select(struct timing_generator *optc, int group_idx, uint32_t gsl_ready_signal); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void optc2_set_dsc_config(struct timing_generator *optc, enum optc_dsc_mode dsc_mode, uint32_t dsc_bytes_per_pixel, uint32_t dsc_slice_width); +#endif void optc2_get_dsc_status(struct timing_generator *optc, uint32_t *dsc_mode); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c index 772a8bfb949c1..fcc5d6138e5a6 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c @@ -172,7 +172,9 @@ static const struct timing_generator_funcs dcn201_tg_funcs = { .clear_optc_underflow = optc1_clear_optc_underflow, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc2_set_dsc_config, +#endif .set_dwb_source = NULL, .get_optc_source = optc201_get_optc_source, .set_vtg_params = optc1_set_vtg_params, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c index ee4665aa49e9f..ddf112c87267d 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c @@ -176,6 +176,7 @@ void optc3_set_vtotal_change_limit(struct timing_generator *optc, } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: Bytes per pixel in u3.28 format @@ -191,6 +192,7 @@ void optc3_set_dsc_config(struct timing_generator *optc, optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel, dsc_slice_width); REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0); } +#endif void optc3_set_odm_bypass(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing) @@ -400,7 +402,9 @@ static const struct timing_generator_funcs dcn30_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, +#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .set_odm_bypass = optc3_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h index e2303f9eaf13b..f3ca2df9a3a00 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h @@ -348,10 +348,12 @@ void optc3_program_blank_color(struct timing_generator *optc, void optc3_set_vtotal_change_limit(struct timing_generator *optc, uint32_t limit); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void optc3_set_dsc_config(struct timing_generator *optc, enum optc_dsc_mode dsc_mode, uint32_t dsc_bytes_per_pixel, uint32_t dsc_slice_width); +#endif void optc3_set_timing_db_mode(struct timing_generator *optc, bool enable); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c index 4a2caca372556..32debad43c8c1 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c @@ -237,7 +237,9 @@ static const struct timing_generator_funcs dcn314_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc1_configure_crc, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, +#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .get_optc_source = optc2_get_optc_source, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index b2b226bcd871c..94896379ded9a 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -342,7 +342,9 @@ static const struct timing_generator_funcs dcn32_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc1_configure_crc, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, +#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .set_odm_bypass = optc32_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index f9cbdad3ef370..8b14bc26e984e 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -618,6 +618,7 @@ static int map_transmitter_id_to_phy_instance( } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -639,6 +640,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dccg_registers dccg_regs = { DCCG_REG_LIST_DCN2() @@ -662,7 +664,9 @@ static const struct resource_caps res_cap_nv10 = { .num_dwb = 1, .num_ddc = 6, .num_vmid = 16, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 6, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -700,7 +704,9 @@ static const struct resource_caps res_cap_nv14 = { .num_dwb = 1, .num_ddc = 5, .num_vmid = 16, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 5, +#endif }; static const struct dc_debug_options debug_defaults_drv = { @@ -1056,7 +1062,7 @@ void dcn20_clock_source_destroy(struct clock_source **clk_src) *clk_src = NULL; } - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct display_stream_compressor *dcn20_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1077,7 +1083,7 @@ void dcn20_dsc_destroy(struct display_stream_compressor **dsc) kfree(container_of(*dsc, struct dcn20_dsc, base)); *dsc = NULL; } - +#endif static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) { @@ -1090,10 +1096,12 @@ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1321,7 +1329,7 @@ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state return status; } - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn20_acquire_dsc(const struct dc *dc, struct resource_context *res_ctx, struct display_stream_compressor **dsc, @@ -1371,8 +1379,6 @@ void dcn20_release_dsc(struct resource_context *res_ctx, } } - - enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream) @@ -1428,7 +1434,7 @@ static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, else return DC_OK; } - +#endif enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { @@ -1439,9 +1445,11 @@ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, if (result == DC_OK) result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Get a DSC if required and available */ if (result == DC_OK && dc_stream->timing.flags.DSC) result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream); +#endif if (result == DC_OK) result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream); @@ -1454,7 +1462,9 @@ enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ { enum dc_status result = DC_OK; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream); +#endif return result; } @@ -1493,7 +1503,9 @@ bool dcn20_split_stream_for_odm( next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT next_odm_pipe->stream_res.dsc = NULL; +#endif if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe; @@ -1520,12 +1532,14 @@ bool dcn20_split_stream_for_odm( next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; else next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) { dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx); ASSERT(next_odm_pipe->stream_res.dsc); if (next_odm_pipe->stream_res.dsc == NULL) return false; } +#endif return true; } @@ -1549,7 +1563,9 @@ void dcn20_split_stream_for_mpc( secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT secondary_pipe->stream_res.dsc = NULL; +#endif if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { ASSERT(!secondary_pipe->bottom_pipe); secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; @@ -1640,6 +1656,7 @@ void dcn20_set_mcif_arb_params( } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) { int i; @@ -1674,6 +1691,7 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) } return true; } +#endif struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, struct resource_context *res_ctx, @@ -1777,8 +1795,10 @@ void dcn20_merge_pipes_for_validate( odm_pipe->bottom_pipe = NULL; odm_pipe->prev_odm_pipe = NULL; odm_pipe->next_odm_pipe = NULL; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (odm_pipe->stream_res.dsc) dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); +#endif /* Clear plane_res and stream_res */ memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res)); @@ -2224,7 +2244,9 @@ static const struct resource_funcs dcn20_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn20_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, @@ -2692,6 +2714,7 @@ static bool dcn20_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn20_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2700,6 +2723,7 @@ static bool dcn20_resource_construct( goto create_fail; } } +#endif if (!dcn20_dwbc_create(ctx, &pool->base)) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h index e997d35a8b86e..072bfaa3185c8 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h @@ -132,7 +132,9 @@ int dcn20_validate_apply_pipe_split_flags( void dcn20_release_dsc(struct resource_context *res_ctx, const struct resource_pool *pool, struct display_stream_compressor **dsc); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx); +#endif void dcn20_split_stream_for_mpc( struct resource_context *res_ctx, const struct resource_pool *pool, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c index e4a1338d21e01..d9aac402615f5 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c @@ -1072,7 +1072,9 @@ static struct resource_funcs dcn201_res_pool_funcs = { .validate_bandwidth = dcn20_validate_bandwidth, .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, .add_stream_to_ctx = dcn20_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = NULL, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .acquire_free_pipe_as_secondary_dpp_pipe = dcn201_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 918742a42ded6..584e7e429fb97 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -362,6 +362,7 @@ static const struct dcn20_vmid_mask vmid_masks = { DCN20_VMID_MASK_SH_LIST(_MASK) }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -383,6 +384,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif #define ipp_regs(id)\ [id] = {\ @@ -578,7 +580,9 @@ static const struct resource_caps res_cap_rn = { .num_dwb = 1, .num_ddc = 5, .num_vmid = 16, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -661,10 +665,12 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -899,12 +905,14 @@ bool dcn21_fast_validate_bw(struct dc *dc, ASSERT(0); } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Actual dsc count per stream dsc validation*/ if (!dcn20_validate_dsc(dc, context)) { context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; goto validate_fail; } +#endif *vlevel_out = vlevel; @@ -1085,7 +1093,7 @@ static void read_dce_straps( } - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx, uint32_t inst) { @@ -1100,6 +1108,7 @@ static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) { @@ -1368,7 +1377,9 @@ static const struct resource_funcs dcn21_res_pool_funcs = { .validate_bandwidth = dcn21_validate_bandwidth, .populate_dml_pipes = dcn21_populate_dml_pipes_from_context, .add_stream_to_ctx = dcn20_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, @@ -1653,6 +1664,7 @@ static bool dcn21_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn21_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -1661,6 +1673,7 @@ static bool dcn21_resource_construct( goto create_fail; } } +#endif if (!dcn20_dwbc_create(ctx, &pool->base)) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c index 895349d9ca07c..112e0ab4b226c 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c @@ -46,7 +46,9 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" +#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" @@ -511,6 +513,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { DSC_REG_LIST_DCN20(id)\ } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static const struct dcn20_dsc_registers dsc_regs[] = { dsc_regsDCN20(0), dsc_regsDCN20(1), @@ -527,6 +530,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -677,7 +681,9 @@ static const struct resource_caps res_cap_dcn3 = { .num_ddc = 6, .num_vmid = 16, .num_mpc_3dlut = 3, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 6, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -1081,10 +1087,12 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1262,6 +1270,7 @@ static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn30_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1276,6 +1285,7 @@ static struct display_stream_compressor *dcn30_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { @@ -1536,7 +1546,9 @@ static bool dcn30_split_stream_for_mpc_or_odm( sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT sec_pipe->stream_res.dsc = NULL; +#endif if (odm) { if (pri_pipe->next_odm_pipe) { ASSERT(pri_pipe->next_odm_pipe != sec_pipe); @@ -1558,12 +1570,14 @@ static bool dcn30_split_stream_for_mpc_or_odm( sec_pipe->stream_res.opp = pool->opps[pipe_idx]; else sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (sec_pipe->stream->timing.flags.DSC == 1) { dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); ASSERT(sec_pipe->stream_res.dsc); if (sec_pipe->stream_res.dsc == NULL) return false; } +#endif } else { if (pri_pipe->bottom_pipe) { ASSERT(pri_pipe->bottom_pipe != sec_pipe); @@ -1738,8 +1752,10 @@ noinline bool dcn30_internal_validate_bw( pipe->stream = NULL; pipe->top_pipe = NULL; pipe->prev_odm_pipe = NULL; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe->stream_res.dsc) dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); +#endif memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); repopulate_pipes = true; @@ -1858,11 +1874,13 @@ noinline bool dcn30_internal_validate_bw( } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Actual dsc count per stream dsc validation*/ if (!dcn20_validate_dsc(dc, context)) { vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; goto validate_fail; } +#endif if (repopulate_pipes) pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); @@ -2239,7 +2257,9 @@ static const struct resource_funcs dcn30_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -2532,6 +2552,7 @@ static bool dcn30_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn30_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2540,6 +2561,7 @@ static bool dcn30_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn30_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index eeb3794dcd09f..6c0c8b6cb45aa 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -1401,7 +1401,9 @@ static struct resource_funcs dcn301_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c index 663c49cce4aa3..f45f682fc21a5 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c @@ -574,6 +574,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { DSC_REG_LIST_DCN20(id)\ } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static const struct dcn20_dsc_registers dsc_regs[] = { dsc_regsDCN314(0), dsc_regsDCN314(1), @@ -588,6 +589,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -1440,10 +1442,12 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1617,6 +1621,7 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn314_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1631,6 +1636,7 @@ static struct display_stream_compressor *dcn314_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif static void dcn314_destroy_resource_pool(struct resource_pool **pool) { @@ -1768,7 +1774,9 @@ static struct resource_funcs dcn314_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -2063,6 +2071,7 @@ static bool dcn314_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn314_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2071,6 +2080,7 @@ static bool dcn314_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index 82cc78c291d82..44a02ea5f72d8 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -49,7 +49,9 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" +#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" @@ -566,6 +568,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -584,6 +587,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -823,7 +827,9 @@ static const struct resource_caps res_cap_dcn31 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -1382,10 +1388,12 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1560,6 +1568,7 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1574,6 +1583,7 @@ static struct display_stream_compressor *dcn31_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif static void dcn315_destroy_resource_pool(struct resource_pool **pool) { @@ -1832,7 +1842,9 @@ static struct resource_funcs dcn315_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn31_set_mcif_arb_params, @@ -2088,6 +2100,7 @@ static bool dcn315_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn31_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2096,6 +2109,7 @@ static bool dcn315_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c index 636110e48d01b..e35af428f0853 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c @@ -49,7 +49,9 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" +#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" @@ -557,6 +559,8 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -575,6 +579,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -818,7 +823,9 @@ static const struct resource_caps res_cap_dcn31 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -1378,10 +1385,12 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1553,6 +1562,7 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1567,6 +1577,7 @@ static struct display_stream_compressor *dcn31_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif static void dcn316_destroy_resource_pool(struct resource_pool **pool) { @@ -1709,7 +1720,9 @@ static struct resource_funcs dcn316_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn31_set_mcif_arb_params, @@ -1956,6 +1969,7 @@ static bool dcn316_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn31_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -1964,6 +1978,7 @@ static bool dcn316_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index 9917b366f00c6..f36507b166f7a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -438,6 +438,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { #define dsc_regsDCN20_init(id)\ DSC_REG_LIST_DCN20_RI(id) +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct dcn20_dsc_registers dsc_regs[4]; static const struct dcn20_dsc_shift dsc_shift = { @@ -447,6 +448,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static struct dcn30_mpc_registers mpc_regs; @@ -1387,10 +1389,12 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1558,6 +1562,7 @@ static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn32_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1582,6 +1587,7 @@ static struct display_stream_compressor *dcn32_dsc_create( return &dsc->base; } +#endif static void dcn32_destroy_resource_pool(struct resource_pool **pool) { @@ -2098,7 +2104,9 @@ static struct resource_funcs dcn32_res_pool_funcs = { .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -2444,6 +2452,7 @@ static bool dcn32_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* DSCs */ for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn32_dsc_create(ctx, i); @@ -2453,6 +2462,7 @@ static bool dcn32_resource_construct( goto create_fail; } } +#endif /* DWB */ if (!dcn32_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c index f5a4e97c40ced..eb78191838c7c 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c @@ -128,8 +128,10 @@ void dcn32_merge_pipes_for_subvp(struct dc *dc, pipe->stream = NULL; pipe->top_pipe = NULL; pipe->prev_odm_pipe = NULL; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe->stream_res.dsc) dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); +#endif memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c index 6ffc74fc9dcd8..6f138e445421b 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c @@ -88,10 +88,12 @@ static void virtual_stream_encoder_reset_hdmi_stream_attribute( struct stream_encoder *enc) {} +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static void virtual_enc_dp_set_odm_combine( struct stream_encoder *enc, bool odm_combine) {} +#endif static void virtual_dig_connect_to_otg( struct stream_encoder *enc, @@ -104,16 +106,20 @@ static void virtual_setup_stereo_sync( bool enable) {} +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static void virtual_stream_encoder_set_dsc_pps_info_packet( struct stream_encoder *enc, bool enable, uint8_t *dsc_packed_pps, bool immediate_update) {} +#endif static const struct stream_encoder_funcs virtual_str_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dp_set_odm_combine = virtual_enc_dp_set_odm_combine, +#endif .dp_set_stream_attribute = virtual_stream_encoder_dp_set_stream_attribute, .hdmi_set_stream_attribute = @@ -142,7 +148,9 @@ static const struct stream_encoder_funcs virtual_str_enc_funcs = { .hdmi_reset_stream_attribute = virtual_stream_encoder_reset_hdmi_stream_attribute, .dig_connect_to_otg = virtual_dig_connect_to_otg, .setup_stereo_sync = virtual_setup_stereo_sync, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dp_set_dsc_pps_info_packet = virtual_stream_encoder_set_dsc_pps_info_packet, +#endif }; bool virtual_stream_encoder_construct( From bbc0b98a101c4dc37c10dd9ddb48982f0e4fe4ad Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 28 Jun 2022 11:16:02 +0800 Subject: [PATCH 0756/2653] drm/amdkfd: remove redundant sg_table* argument This is caused by dropping of patch v5.16-1998-g1d11a577d7f0 "drm/amdkfd: Add CMA API" Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 59c3fbe03bc14..34f4bac7ac42e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2427,7 +2427,7 @@ static int criu_restore_memory_of_gpu_ipc(struct kfd_process_device *pdd, */ ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(dev->adev, bo_bucket->addr, bo_bucket->size, pdd->drm_priv, - NULL, kgd_mem, &offset, + kgd_mem, &offset, bo_bucket->alloc_flags, true); if (ret) { pr_err("Could not create the BO\n"); From daafa318d937f533d2e49ae8df67ad8550886d7e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 7 Mar 2022 16:42:59 +0800 Subject: [PATCH 0757/2653] Revert "drm/amdkfd: add reset lock protection for kfd entry functions" This reverts commit f09bc5e4580c1aa0c2d7eb43b762f58dbd239423. Signed-off-by: Ma Jun Change-Id: I7e7c136bb9831224bb0fc749f2f109b6f9e8d976 --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 14 -------------- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 1 - 3 files changed, 2 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 34f4bac7ac42e..23676dd952090 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1260,7 +1260,7 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, GET_IDR_HANDLE(args->handle)); if (!buf_obj) { ret = -EINVAL; - goto err_unlock; + goto err_pdd; } ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, @@ -1364,6 +1364,7 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), ((struct kgd_mem *)mem)->domain); + goto map_memory_to_gpu_failed; } args->n_success = i+1; @@ -1492,7 +1493,6 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, mutex_unlock(&p->mutex); kfree(devices_arr); - return 0; bind_process_to_device_failed: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index 6021077f7199b..9cb5155809752 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -193,18 +193,11 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *dev, return -EINVAL; mutex_lock(&p->mutex); - r = amdgpu_read_lock(dev->ddev, true); - if (r) - goto err_unlock; r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, dmabuf, NULL, va_addr, handle, mmap_offset, false); - amdgpu_read_unlock(dev->ddev); - -err_unlock: mutex_unlock(&p->mutex); - dma_buf_put(dmabuf); return r; } @@ -238,9 +231,6 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, if (!restore) { mutex_lock(&p->mutex); - r = amdgpu_read_lock(dev->ddev, true); - if (r) - goto err_unlock; } r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, @@ -248,7 +238,6 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, va_addr, handle, mmap_offset, restore); if (!restore) { - amdgpu_read_unlock(dev->ddev); mutex_unlock(&p->mutex); } if (r) @@ -259,9 +248,6 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, return r; -err_unlock: - mutex_unlock(&p->mutex); - error_unref: kfd_ipc_obj_put(&found); return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 9a62aff0c2eeb..e219d556e2ad1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1005,7 +1005,6 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) peer_pdd->dev->adev, buf_obj->mem, peer_pdd->drm_priv); } - run_rdma_free_callback(buf_obj); amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, buf_obj->mem, pdd->drm_priv, NULL); kfd_process_device_remove_obj_handle(pdd, id); From e2d509601fcacfbb4d70af0cd970411a576d82a1 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 28 Jun 2022 17:38:36 +0800 Subject: [PATCH 0758/2653] drm/amdkcl: fake drm_gem_ttm_vmap which the type of second arg is dma_buf_map pointer Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 5 ++- .../include/kcl/kcl_drm_gem_ttm_helper.h | 20 +++++++++- .../drm/amd/backport/kcl_drm_gem_ttm_helper.c | 38 ++++++++++++++++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../amd/dkms/m4/drm-driver-gem-open-object.m4 | 21 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 6 files changed, 84 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 301a3f319a5b1..0485684c76117 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -480,9 +480,12 @@ const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { .open = amdgpu_gem_object_open, .close = amdgpu_gem_object_close, .export = amdgpu_gem_prime_export, -#ifdef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS +#ifdef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG .vmap = drm_gem_ttm_vmap, .vunmap = drm_gem_ttm_vunmap, +#elif defined(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS) + .vmap = amdgpu_drm_gem_ttm_vmap, + .vunmap = amdgpu_drm_gem_ttm_vunmap, #else .vmap = amdgpu_gem_prime_vmap, .vunmap = amdgpu_gem_prime_vunmap, diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h index ae25af4cbc8c5..aa89982b0c2c7 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h @@ -5,10 +5,28 @@ #include #include -#ifndef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS +#if !defined(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS) void amdgpu_gem_prime_vunmap(struct drm_gem_object *gem, void *vaddr); void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); +#elif !defined(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG) +int _kcl_drm_gem_ttm_vmap(struct drm_gem_object *gem, + struct dma_buf_map *map); +void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, + struct dma_buf_map *map); +static inline +void amdgpu_drm_gem_ttm_vunmap(struct drm_gem_object *gem, + struct dma_buf_map *map) +{ + _kcl_drm_gem_ttm_vunmap(gem, map); +} + +static inline +int amdgpu_drm_gem_ttm_vmap(struct drm_gem_object *obj, + struct dma_buf_map *map) +{ + return _kcl_drm_gem_ttm_vmap(obj, map); +} #endif #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c index 2cef03209d156..04b308171928f 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #ifndef drm_gem_ttm_of_gem @@ -18,7 +19,7 @@ void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj) { struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(obj); - struct dma_buf_map map; + struct iosys_map map; ttm_bo_vmap(bo, &map); return map.vaddr; @@ -28,11 +29,44 @@ void amdgpu_gem_prime_vunmap(struct drm_gem_object *gem, void *vaddr) { struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); - struct dma_buf_map map; + struct iosys_map map; map.vaddr = vaddr; map.is_iomem = bo->resource->bus.is_iomem; ttm_bo_vunmap(bo, &map); } +#elif !defined(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG) + +int _kcl_drm_gem_ttm_vmap(struct drm_gem_object *gem, + struct dma_buf_map *map) +{ + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); + struct iosys_map iosys_map; + int r; + + iosys_map.vaddr = map->vaddr; + iosys_map.is_iomem = map->is_iomem; + + r = ttm_bo_vmap(bo, &iosys_map); + + map->vaddr = iosys_map.vaddr; + map->is_iomem = iosys_map.is_iomem; + return r; +} + +void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, + struct dma_buf_map *map) +{ + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); + struct iosys_map iosys_map; + + iosys_map.vaddr = map->vaddr; + iosys_map.is_iomem = map->is_iomem; + + ttm_bo_vunmap(bo, &iosys_map); + + map->vaddr = iosys_map.vaddr; + map->is_iomem = iosys_map.is_iomem; +} #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6c4aedb8cfc8b..23612516b3ad7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -542,6 +542,9 @@ /* drm_gem_object_funcs->vmap() has 2 args */ #define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS 1 +/* drm_gem_object_funcs.vmap hsa iosys_map arg */ +#define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG 1 + /* drm_gem_object_lookup() wants 2 args */ #define HAVE_DRM_GEM_OBJECT_LOOKUP_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 index cb583a5e9dafd..6631ba066edcf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 @@ -31,3 +31,24 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_OPEN_OBJECT], [ ]) ]) ]) + + +dnl # +dnl # commit v5.17-rc2-157-g7938f4218168 +dnl # dma-buf-map: Rename to iosys-map +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_gem_object_funcs *funcs = NULL; + struct iosys_map *map = NULL; + funcs->vmap(NULL, map); + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG, 1, + [drm_gem_object_funcs.vmap hsa iosys_map arg]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f620c3aaf4864..7b3a26efd9324 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -206,6 +206,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_IS_CONTAINER AC_AMDGPU_STR_YES_NO AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED + AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 0c531d6e6e1de559ea9cfebb39e86cac32e22074 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 29 Jun 2022 14:11:03 +0800 Subject: [PATCH 0759/2653] drm/amdkcl: Test whether drm_memcpy_from_wc argument type is struct iosys_map Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 5 ++++- .../gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 | 17 ++++++++++++++--- drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- 3 files changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 23612516b3ad7..812ed631934a4 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -594,7 +594,10 @@ #define HAVE_DRM_KMS_HELPER_IS_POLL_WORKER 1 /* drm_memcpy_from_wc() is availablea */ -#define HAVE_DRM_MEMCPY_FROM_WC 1 +/* #undef HAVE_DRM_MEMCPY_FROM_WC */ + +/* drm_memcpy_from_wc() is availablea and has struct iosys_map* arg */ +#define HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG 1 /* whether drm_mm_insert_mode is available */ #define HAVE_DRM_MM_INSERT_MODE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 index 491ada31c112a..8ab4aaf2521dc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 @@ -6,11 +6,22 @@ AC_DEFUN([AC_AMDGPU_DRM_MEMCPY_FROM_WC], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ #include + #include ], [ - drm_memcpy_from_wc(NULL, NULL, 0); + struct iosys_map *dst = NULL, *src = NULL; + drm_memcpy_from_wc(dst, src, 0); ], [ - AC_DEFINE(HAVE_DRM_MEMCPY_FROM_WC, 1, - [drm_memcpy_from_wc() is availablea]) + AC_DEFINE(HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG, 1, + [drm_memcpy_from_wc() is availablea and has struct iosys_map* arg]) + ], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_memcpy_from_wc(NULL, NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_MEMCPY_FROM_WC, 1, + [drm_memcpy_from_wc() is availablea]) + ]) ]) ]) ]) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 63c470af0e18d..490f415cd8db0 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -117,7 +117,7 @@ void ttm_move_memcpy(bool clear, dst_ops->map_local(dst_iter, &dst_map, i); src_ops->map_local(src_iter, &src_map, i); -#ifdef HAVE_DRM_MEMCPY_FROM_WC +#ifdef HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG drm_memcpy_from_wc(&dst_map, &src_map, PAGE_SIZE); #else if (!src_map.is_iomem && !dst_map.is_iomem) { From e0d5e544283cac219b71976bb713c55a56fce4ab Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 4 Jul 2022 13:54:52 +0800 Subject: [PATCH 0760/2653] drm/amdkfd: using TTM provided vram usage function Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index e335cafca639a..510e836ddd36d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -583,7 +583,7 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, uint64_t amdgpu_amdkfd_get_vram_usage(struct amdgpu_device *adev) { - return amdgpu_vram_mgr_usage(&adev->mman.vram_mgr); + return ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); } int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min) From 6fb786d6779a0db3a38fc4388f918d903ce77562 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 4 Jul 2022 17:33:14 +0800 Subject: [PATCH 0761/2653] drm/amdkcl: wrap the code under HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index a92a70075f879..3921030fa1b0f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2765,7 +2765,9 @@ static int amdgpu_runtime_idle_check_display(struct device *dev) if (adev->mode_info.num_crtc) { struct drm_connector *list_connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif int ret = 0; if (amdgpu_runtime_pm != -2) { @@ -2775,14 +2777,20 @@ static int amdgpu_runtime_idle_check_display(struct device *dev) * the GPU was in suspend. Remove this once that is fixed. */ mutex_lock(&drm_dev->mode_config.mutex); +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(drm_dev, &iter); drm_for_each_connector_iter(list_connector, &iter) { +#else + list_for_each_entry(list_connector, &(drm_dev)->mode_config.connector_list, head) { +#endif if (list_connector->status == connector_status_connected) { ret = -EBUSY; break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif mutex_unlock(&drm_dev->mode_config.mutex); if (ret) @@ -2804,15 +2812,21 @@ static int amdgpu_runtime_idle_check_display(struct device *dev) mutex_lock(&drm_dev->mode_config.mutex); drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(drm_dev, &iter); drm_for_each_connector_iter(list_connector, &iter) { +#else + list_for_each_entry(list_connector, &(drm_dev)->mode_config.connector_list, head) { +#endif if (list_connector->dpms == DRM_MODE_DPMS_ON) { ret = -EBUSY; break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); mutex_unlock(&drm_dev->mode_config.mutex); From 1bb7a42ecf7c971f6151df0f7aa154da9ed5db91 Mon Sep 17 00:00:00 2001 From: Alex Sierra Date: Fri, 20 Aug 2021 12:53:14 -0500 Subject: [PATCH 0762/2653] drm/amdkfd: ref count init for device pages Ref counter from device pages is init to zero during memmap init zone. The first time a new device page is allocated to migrate data into it, its ref counter needs to be initialized to one. Signed-off-by: Alex Sierra Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index ec82b529fbd36..9946bab27a712 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -221,7 +221,13 @@ svm_migrate_get_vram_page(struct svm_range *prange, unsigned long pfn) page = pfn_to_page(pfn); svm_range_bo_ref(prange->svm_bo); page->zone_device_data = prange->svm_bo; - zone_device_page_init(page); +#ifdef HAVE_ZONE_DEVICE_PUBLIC + VM_BUG_ON_PAGE(page_ref_count(page), page); + init_page_count(page); +#else + get_page(page); +#endif + lock_page(page); } static void From 377443ecfa3cd647a3bb202772f702f153254f53 Mon Sep 17 00:00:00 2001 From: George Cave Date: Tue, 5 Jul 2022 17:56:04 -0400 Subject: [PATCH 0763/2653] drm/amdkcl: Add directory to included header path As of RedHat 9.1, building the DKMS module fails due to it being unable to find a stdarg.h header. This file is available in a directory that is not included via the compiler, but can be by adding the subdirectory it resides in at the include point. Signed-off-by: George Cave Reviewed-by: Flora Cui flora.cui@amd.com --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 907a902c5f204..9e0c95502367c 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -24,7 +24,7 @@ */ #include #include -#include +#include #if !defined(HAVE_DRM_DRM_PRINT_H) void drm_printf(struct drm_printer *p, const char *f, ...) From b9b7ad99188adfad42fac132a39b0ca38c2b0531 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 02:10:31 -0400 Subject: [PATCH 0764/2653] drm/amdkfd: Add CMA API This is similar to Cross Memory Attach, except that it uses SDMA to copy data between processes, and can access GPU memory that's not CPU accessible. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 7 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 86 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 841 +++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 32 + drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +- include/uapi/linux/kfd_ioctl.h | 35 + 6 files changed, 998 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index bbeac961f7381..fd2bf0257f499 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -176,6 +176,11 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle); bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev); +int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, + uint64_t src_offset, struct kgd_mem *dst_mem, + uint64_t dest_offset, uint64_t size, struct dma_fence **f, + uint64_t *actual_size); + bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev, @@ -310,7 +315,7 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, uint8_t xcp_id); int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( struct amdgpu_device *adev, uint64_t va, uint64_t size, - void *drm_priv, struct kgd_mem **mem, + void *drm_priv, struct sg_table *sg, struct kgd_mem **mem, uint64_t *offset, uint32_t flags, bool criu_resume); int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 7a71012b9654d..945bbe20561cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1739,13 +1739,12 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( struct amdgpu_device *adev, uint64_t va, uint64_t size, - void *drm_priv, struct kgd_mem **mem, + void *drm_priv, struct sg_table *sg, struct kgd_mem **mem, uint64_t *offset, uint32_t flags, bool criu_resume) { struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm); enum ttm_bo_type bo_type = ttm_bo_type_device; - struct sg_table *sg = NULL; uint64_t user_addr = 0; struct amdgpu_bo *bo; struct drm_gem_object *gobj = NULL; @@ -1808,6 +1807,10 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED) alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED; + if (sg) { + alloc_domain = AMDGPU_GEM_DOMAIN_CPU; + bo_type = ttm_bo_type_sg; + } *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL); if (!*mem) { ret = -ENOMEM; @@ -3522,6 +3525,85 @@ int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem) return 0; } +int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, + uint64_t src_offset, struct kgd_mem *dst_mem, + uint64_t dst_offset, uint64_t size, + struct dma_fence **f, uint64_t *actual_size) +{ + struct amdgpu_device *adev = NULL; + struct amdgpu_copy_mem src, dst; + struct ww_acquire_ctx ticket; + struct list_head list, duplicates; + struct ttm_validate_buffer resv_list[2]; + struct dma_fence *fence = NULL; + int i, r; + + if (!kgd || !src_mem || !dst_mem || !actual_size) + return -EINVAL; + + *actual_size = 0; + + adev = get_amdgpu_device(kgd); + INIT_LIST_HEAD(&list); + INIT_LIST_HEAD(&duplicates); + + src.bo = &src_mem->bo->tbo; + dst.bo = &dst_mem->bo->tbo; + src.mem = &src.bo->mem; + dst.mem = &dst.bo->mem; + src.offset = src_offset; + dst.offset = dst_offset; + + resv_list[0].bo = src.bo; + resv_list[1].bo = dst.bo; + + for (i = 0; i < 2; i++) { + resv_list[i].num_shared = 1; + list_add_tail(&resv_list[i].head, &list); + } + + r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); + if (r) { + pr_err("Copy buffer failed. Unable to reserve bo (%d)\n", r); + return r; + } + + /* The process to which the Source and Dest BOs belong to could be + * evicted and the BOs invalidated. So validate BOs before use + */ + r = amdgpu_amdkfd_bo_validate(src_mem->bo, src_mem->domain, false); + if (r) { + pr_err("CMA fail: SRC BO validate failed %d\n", r); + goto validate_fail; + } + + + r = amdgpu_amdkfd_bo_validate(dst_mem->bo, dst_mem->domain, false); + if (r) { + pr_err("CMA fail: DST BO validate failed %d\n", r); + goto validate_fail; + } + + + r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, size, false, NULL, + &fence); + if (r) + pr_err("Copy buffer failed %d\n", r); + else + *actual_size = size; + if (fence) { + amdgpu_bo_fence(src_mem->bo, fence, true); + amdgpu_bo_fence(dst_mem->bo, fence, true); + } + if (f) + *f = dma_fence_get(fence); + dma_fence_put(fence); + +validate_fail: + ttm_eu_backoff_reservation(&ticket, &list); + return r; +} + /* Returns GPU-specific tiling mode information */ int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 23676dd952090..a4538aacf7aab 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1178,7 +1178,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( dev->adev, args->va_addr, args->size, - pdd->drm_priv, (struct kgd_mem **) &mem, &offset, + pdd->drm_priv, NULL, (struct kgd_mem **) &mem, &offset, flags, false); if (err) @@ -1697,6 +1697,843 @@ static int kfd_ioctl_ipc_import_handle(struct file *filep, return r; } +/* Maximum number of entries for process pages array which lives on stack */ +#define MAX_PP_STACK_COUNT 16 +/* Maximum number of pages kmalloc'd to hold struct page's during copy */ +#define MAX_KMALLOC_PAGES (PAGE_SIZE * 2) +#define MAX_PP_KMALLOC_COUNT (MAX_KMALLOC_PAGES/sizeof(struct page *)) + +static void kfd_put_sg_table(struct sg_table *sg) +{ + unsigned int i; + struct scatterlist *s; + + for_each_sg(sg->sgl, s, sg->nents, i) + put_page(sg_page(s)); +} + + +/* Create a sg table for the given userptr BO by pinning its system pages + * @bo: userptr BO + * @offset: Offset into BO + * @mm/@task: mm_struct & task_struct of the process that holds the BO + * @size: in/out: desired size / actual size which could be smaller + * @sg_size: out: Size of sg table. This is ALIGN_UP(@size) + * @ret_sg: out sg table + */ +static int kfd_create_sg_table_from_userptr_bo(struct kfd_bo *bo, + int64_t offset, int cma_write, + struct mm_struct *mm, + struct task_struct *task, + uint64_t *size, + uint64_t *sg_size, + struct sg_table **ret_sg) +{ + int ret, locked = 1; + struct sg_table *sg = NULL; + unsigned int i, offset_in_page, flags = 0; + unsigned long nents, n; + unsigned long pa = (bo->cpuva + offset) & PAGE_MASK; + unsigned int cur_page = 0; + struct scatterlist *s; + uint64_t sz = *size; + struct page **process_pages; + + *sg_size = 0; + sg = kmalloc(sizeof(*sg), GFP_KERNEL); + if (!sg) + return -ENOMEM; + + offset_in_page = offset & (PAGE_SIZE - 1); + nents = (sz + offset_in_page + PAGE_SIZE - 1) / PAGE_SIZE; + + ret = sg_alloc_table(sg, nents, GFP_KERNEL); + if (unlikely(ret)) { + ret = -ENOMEM; + goto sg_alloc_fail; + } + process_pages = kmalloc_array(nents, sizeof(struct pages *), + GFP_KERNEL); + if (!process_pages) { + ret = -ENOMEM; + goto page_alloc_fail; + } + + if (cma_write) + flags = FOLL_WRITE; + locked = 1; + mmap_read_lock(mm); + n = get_user_pages_remote(mm, pa, nents, flags, process_pages, + NULL, &locked); + if (locked) + mmap_read_unlock(mm); + if (n <= 0) { + pr_err("CMA: Invalid virtual address 0x%lx\n", pa); + ret = -EFAULT; + goto get_user_fail; + } + if (n != nents) { + /* Pages pinned < requested. Set the size accordingly */ + *size = (n * PAGE_SIZE) - offset_in_page; + pr_debug("Requested %lx but pinned %lx\n", nents, n); + } + + sz = 0; + for_each_sg(sg->sgl, s, n, i) { + sg_set_page(s, process_pages[cur_page], PAGE_SIZE, + offset_in_page); + sg_dma_address(s) = page_to_phys(process_pages[cur_page]); + offset_in_page = 0; + cur_page++; + sz += PAGE_SIZE; + } + *ret_sg = sg; + *sg_size = sz; + + kfree(process_pages); + return 0; + +get_user_fail: + kfree(process_pages); +page_alloc_fail: + sg_free_table(sg); +sg_alloc_fail: + kfree(sg); + return ret; +} + +static void kfd_free_cma_bos(struct cma_iter *ci) +{ + struct cma_system_bo *cma_bo, *tmp; + + list_for_each_entry_safe(cma_bo, tmp, &ci->cma_list, list) { + struct kfd_dev *dev = cma_bo->dev; + + /* sg table is deleted by free_memory_of_gpu */ + if (cma_bo->sg) + kfd_put_sg_table(cma_bo->sg); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, cma_bo->mem, NULL); + list_del(&cma_bo->list); + kfree(cma_bo); + } +} + +/* 1 second timeout */ +#define CMA_WAIT_TIMEOUT msecs_to_jiffies(1000) + +static int kfd_cma_fence_wait(struct dma_fence *f) +{ + int ret; + + ret = dma_fence_wait_timeout(f, false, CMA_WAIT_TIMEOUT); + if (likely(ret > 0)) + return 0; + if (!ret) + ret = -ETIME; + return ret; +} + +/* Put previous (old) fence @pf but it waits for @pf to signal if the context + * of the current fence @cf is different. + */ +static int kfd_fence_put_wait_if_diff_context(struct dma_fence *cf, + struct dma_fence *pf) +{ + int ret = 0; + + if (pf && cf && cf->context != pf->context) + ret = kfd_cma_fence_wait(pf); + dma_fence_put(pf); + return ret; +} + +#define MAX_SYSTEM_BO_SIZE (512*PAGE_SIZE) + +/* Create an equivalent system BO for the given @bo. If @bo is a userptr then + * create a new system BO by pinning underlying system pages of the given + * userptr BO. If @bo is in Local Memory then create an empty system BO and + * then copy @bo into this new BO. + * @bo: Userptr BO or Local Memory BO + * @offset: Offset into bo + * @size: in/out: The size of the new BO could be less than requested if all + * the pages couldn't be pinned or size > MAX_SYSTEM_BO_SIZE. This would + * be reflected in @size + * @mm/@task: mm/task to which @bo belongs to + * @cma_bo: out: new system BO + */ +static int kfd_create_cma_system_bo(struct kfd_dev *kdev, struct kfd_bo *bo, + uint64_t *size, uint64_t offset, + int cma_write, struct kfd_process *p, + struct mm_struct *mm, + struct task_struct *task, + struct cma_system_bo **cma_bo) +{ + int ret; + struct kfd_process_device *pdd = NULL; + struct cma_system_bo *cbo; + uint64_t bo_size = 0; + struct dma_fence *f; + + uint32_t flags = KFD_IOC_ALLOC_MEM_FLAGS_GTT | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | + KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE; + + *cma_bo = NULL; + cbo = kzalloc(sizeof(**cma_bo), GFP_KERNEL); + if (!cbo) + return -ENOMEM; + + INIT_LIST_HEAD(&cbo->list); + if (bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) + bo_size = min_t(uint64_t, *size, MAX_SYSTEM_BO_SIZE); + else if (bo->cpuva) { + ret = kfd_create_sg_table_from_userptr_bo(bo, offset, + cma_write, mm, task, + size, &bo_size, + &cbo->sg); + if (ret) { + pr_err("CMA: BO create with sg failed %d\n", ret); + goto sg_fail; + } + } else { + WARN_ON(1); + ret = -EINVAL; + goto sg_fail; + } + mutex_lock(&p->mutex); + pdd = kfd_get_process_device_data(kdev, p); + if (!pdd) { + mutex_unlock(&p->mutex); + pr_err("Process device data doesn't exist\n"); + ret = -EINVAL; + goto pdd_fail; + } + + ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, bo_size, + pdd->drm_priv, cbo->sg, + &cbo->mem, NULL, flags); + mutex_unlock(&p->mutex); + if (ret) { + pr_err("Failed to create shadow system BO %d\n", ret); + goto pdd_fail; + } + + if (bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { + ret = amdgpu_amdkfd_copy_mem_to_mem(kdev->kgd, bo->mem, + offset, cbo->mem, 0, + bo_size, &f, size); + if (ret) { + pr_err("CMA: Intermediate copy failed %d\n", ret); + goto copy_fail; + } + + /* Wait for the copy to finish as subsequent copy will be done + * by different device + */ + ret = kfd_cma_fence_wait(f); + dma_fence_put(f); + if (ret) { + pr_err("CMA: Intermediate copy timed out %d\n", ret); + goto copy_fail; + } + } + + cbo->dev = kdev; + *cma_bo = cbo; + + return ret; + +copy_fail: + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(kdev->kgd, bo->mem, NULL); +pdd_fail: + if (cbo->sg) { + kfd_put_sg_table(cbo->sg); + sg_free_table(cbo->sg); + kfree(cbo->sg); + } +sg_fail: + kfree(cbo); + return ret; +} + +/* Update cma_iter.cur_bo with KFD BO that is assocaited with + * cma_iter.array.va_addr + */ +static int kfd_cma_iter_update_bo(struct cma_iter *ci) +{ + struct kfd_memory_range *arr = ci->array; + uint64_t va_end = arr->va_addr + arr->size - 1; + + mutex_lock(&ci->p->mutex); + ci->cur_bo = kfd_process_find_bo_from_interval(ci->p, arr->va_addr, + va_end); + mutex_unlock(&ci->p->mutex); + + if (!ci->cur_bo || va_end > ci->cur_bo->it.last) { + pr_err("CMA failed. Range out of bounds\n"); + return -EFAULT; + } + return 0; +} + +/* Advance iter by @size bytes. */ +static int kfd_cma_iter_advance(struct cma_iter *ci, unsigned long size) +{ + int ret = 0; + + ci->offset += size; + if (WARN_ON(size > ci->total || ci->offset > ci->array->size)) + return -EFAULT; + ci->total -= size; + /* If current range is copied, move to next range if available. */ + if (ci->offset == ci->array->size) { + + /* End of all ranges */ + if (!(--ci->nr_segs)) + return 0; + + ci->array++; + ci->offset = 0; + ret = kfd_cma_iter_update_bo(ci); + if (ret) + return ret; + } + ci->bo_offset = (ci->array->va_addr + ci->offset) - + ci->cur_bo->it.start; + return ret; +} + +static int kfd_cma_iter_init(struct kfd_memory_range *arr, unsigned long segs, + struct kfd_process *p, struct mm_struct *mm, + struct task_struct *task, struct cma_iter *ci) +{ + int ret; + int nr; + + if (!arr || !segs) + return -EINVAL; + + memset(ci, 0, sizeof(*ci)); + INIT_LIST_HEAD(&ci->cma_list); + ci->array = arr; + ci->nr_segs = segs; + ci->p = p; + ci->offset = 0; + ci->mm = mm; + ci->task = task; + for (nr = 0; nr < segs; nr++) + ci->total += arr[nr].size; + + /* Valid but size is 0. So copied will also be 0 */ + if (!ci->total) + return 0; + + ret = kfd_cma_iter_update_bo(ci); + if (!ret) + ci->bo_offset = arr->va_addr - ci->cur_bo->it.start; + return ret; +} + +static bool kfd_cma_iter_end(struct cma_iter *ci) +{ + if (!(ci->nr_segs) || !(ci->total)) + return true; + return false; +} + +/* Copies @size bytes from si->cur_bo to di->cur_bo BO. The function assumes + * both source and dest. BOs are userptr BOs. Both BOs can either belong to + * current process or one of the BOs can belong to a differnt + * process. @Returns 0 on success, -ve on failure + * + * @si: Source iter + * @di: Dest. iter + * @cma_write: Indicates if it is write to remote or read from remote + * @size: amount of bytes to be copied + * @copied: Return number of bytes actually copied. + */ +static int kfd_copy_userptr_bos(struct cma_iter *si, struct cma_iter *di, + bool cma_write, uint64_t size, + uint64_t *copied) +{ + int i, ret = 0, locked; + unsigned int nents, nl; + unsigned int offset_in_page; + struct page *pp_stack[MAX_PP_STACK_COUNT]; + struct page **process_pages = pp_stack; + unsigned long rva, lva = 0, flags = 0; + uint64_t copy_size, to_copy = size; + struct cma_iter *li, *ri; + + if (cma_write) { + ri = di; + li = si; + flags |= FOLL_WRITE; + } else { + li = di; + ri = si; + } + /* rva: remote virtual address. Page aligned to start page. + * rva + offset_in_page: Points to remote start address + * lva: local virtual address. Points to the start address. + * nents: computes number of remote pages to request + */ + offset_in_page = ri->bo_offset & (PAGE_SIZE - 1); + rva = (ri->cur_bo->cpuva + ri->bo_offset) & PAGE_MASK; + lva = li->cur_bo->cpuva + li->bo_offset; + + nents = (size + offset_in_page + PAGE_SIZE - 1) / PAGE_SIZE; + + copy_size = min_t(uint64_t, size, PAGE_SIZE - offset_in_page); + *copied = 0; + + if (nents > MAX_PP_STACK_COUNT) { + /* For reliability kmalloc only 2 pages worth */ + process_pages = kmalloc(min_t(size_t, MAX_KMALLOC_PAGES, + sizeof(struct pages *)*nents), + GFP_KERNEL); + + if (!process_pages) + return -ENOMEM; + } + + while (nents && to_copy) { + nl = min_t(unsigned int, MAX_PP_KMALLOC_COUNT, nents); + locked = 1; + mmap_read_lock(ri->mm); + nl = get_user_pages_remote(ri->mm, rva, nl, + flags, process_pages, NULL, + &locked); + if (locked) + mmap_read_unlock(ri->mm); + if (nl <= 0) { + pr_err("CMA: Invalid virtual address 0x%lx\n", rva); + ret = -EFAULT; + break; + } + + for (i = 0; i < nl; i++) { + unsigned int n; + void *kaddr = kmap(process_pages[i]); + + if (cma_write) { + n = copy_from_user(kaddr+offset_in_page, + (void *)lva, copy_size); + set_page_dirty(process_pages[i]); + } else { + n = copy_to_user((void *)lva, + kaddr+offset_in_page, + copy_size); + } + kunmap(kaddr); + if (n) { + ret = -EFAULT; + break; + } + to_copy -= copy_size; + if (!to_copy) + break; + lva += copy_size; + rva += (copy_size + offset_in_page); + WARN_ONCE(rva & (PAGE_SIZE - 1), + "CMA: Error in remote VA computation"); + offset_in_page = 0; + copy_size = min_t(uint64_t, to_copy, PAGE_SIZE); + } + + for (i = 0; i < nl; i++) + put_page(process_pages[i]); + + if (ret) + break; + nents -= nl; + } + + if (process_pages != pp_stack) + kfree(process_pages); + + *copied = (size - to_copy); + return ret; + +} + +static int kfd_create_kgd_mem(struct kfd_dev *kdev, uint64_t size, + struct kfd_process *p, struct kgd_mem **mem) +{ + int ret; + struct kfd_process_device *pdd = NULL; + uint32_t flags = KFD_IOC_ALLOC_MEM_FLAGS_GTT | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | + KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE; + + if (!mem || !size || !p || !kdev) + return -EINVAL; + + *mem = NULL; + + mutex_lock(&p->mutex); + pdd = kfd_get_process_device_data(kdev, p); + if (!pdd) { + mutex_unlock(&p->mutex); + pr_err("Process device data doesn't exist\n"); + return -EINVAL; + } + + ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, size, + pdd->drm_priv, NULL, + mem, NULL, flags); + mutex_unlock(&p->mutex); + if (ret) { + pr_err("Failed to create shadow system BO %d\n", ret); + return -EINVAL; + } + + return 0; +} + +static int kfd_destroy_kgd_mem(struct kgd_mem *mem) +{ + if (!mem) + return -EINVAL; + + /* param adev is not used*/ + return amdgpu_amdkfd_gpuvm_free_memory_of_gpu(NULL, mem, NULL); +} + +/* Copies @size bytes from si->cur_bo to di->cur_bo starting at their + * respective offset. + * @si: Source iter + * @di: Dest. iter + * @cma_write: Indicates if it is write to remote or read from remote + * @size: amount of bytes to be copied + * @f: Return the last fence if any + * @copied: Return number of bytes actually copied. + */ +static int kfd_copy_bos(struct cma_iter *si, struct cma_iter *di, + int cma_write, uint64_t size, + struct dma_fence **f, uint64_t *copied, + struct kgd_mem **tmp_mem) +{ + int err = 0; + struct kfd_bo *dst_bo = di->cur_bo, *src_bo = si->cur_bo; + uint64_t src_offset = si->bo_offset, dst_offset = di->bo_offset; + struct kgd_mem *src_mem = src_bo->mem, *dst_mem = dst_bo->mem; + struct kfd_dev *dev = dst_bo->dev; + int d2d = 0; + + *copied = 0; + if (f) + *f = NULL; + if (src_bo->cpuva && dst_bo->cpuva) + return kfd_copy_userptr_bos(si, di, cma_write, size, copied); + + /* If either source or dest. is userptr, create a shadow system BO + * by using the underlying userptr BO pages. Then use this shadow + * BO for copy. src_offset & dst_offset are adjusted because the new BO + * is only created for the window (offset, size) requested. + * The shadow BO is created on the other device. This means if the + * other BO is a device memory, the copy will be using that device. + * The BOs are stored in cma_list for deferred cleanup. This minimizes + * fence waiting just to the last fence. + */ + if (src_bo->cpuva) { + dev = dst_bo->dev; + err = kfd_create_cma_system_bo(dev, src_bo, &size, + si->bo_offset, cma_write, + si->p, si->mm, si->task, + &si->cma_bo); + src_mem = si->cma_bo->mem; + src_offset = si->bo_offset & (PAGE_SIZE - 1); + list_add_tail(&si->cma_bo->list, &si->cma_list); + } else if (dst_bo->cpuva) { + dev = src_bo->dev; + err = kfd_create_cma_system_bo(dev, dst_bo, &size, + di->bo_offset, cma_write, + di->p, di->mm, di->task, + &di->cma_bo); + dst_mem = di->cma_bo->mem; + dst_offset = di->bo_offset & (PAGE_SIZE - 1); + list_add_tail(&di->cma_bo->list, &di->cma_list); + } else if (src_bo->dev->kgd != dst_bo->dev->kgd) { + /* This indicates that atleast on of the BO is in local mem. + * If both are in local mem of different devices then create an + * intermediate System BO and do a double copy + * [VRAM]--gpu1-->[System BO]--gpu2-->[VRAM]. + * If only one BO is in VRAM then use that GPU to do the copy + */ + if (src_bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM && + dst_bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { + dev = dst_bo->dev; + size = min_t(uint64_t, size, MAX_SYSTEM_BO_SIZE); + d2d = 1; + + if (*tmp_mem == NULL) { + if (kfd_create_kgd_mem(src_bo->dev, + MAX_SYSTEM_BO_SIZE, + si->p, + tmp_mem)) + return -EINVAL; + } + + if (amdgpu_amdkfd_copy_mem_to_mem(src_bo->dev->kgd, + src_bo->mem, si->bo_offset, + *tmp_mem, 0, + size, f, &size)) + /* tmp_mem will be freed in caller.*/ + return -EINVAL; + + kfd_cma_fence_wait(*f); + dma_fence_put(*f); + + src_mem = *tmp_mem; + src_offset = 0; + } else if (src_bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) + dev = src_bo->dev; + /* else already set to dst_bo->dev */ + } + + if (err) { + pr_err("Failed to create system BO %d", err); + return -EINVAL; + } + + err = amdgpu_amdkfd_copy_mem_to_mem(dev->kgd, src_mem, src_offset, + dst_mem, dst_offset, size, f, + copied); + /* The tmp_bo allocates additional memory. So it is better to wait and + * delete. Also since multiple GPUs are involved the copies are + * currently not pipelined. + */ + if (*tmp_mem && d2d) { + if (!err) { + kfd_cma_fence_wait(*f); + dma_fence_put(*f); + *f = NULL; + } + } + return err; +} + +/* Copy single range from source iterator @si to destination iterator @di. + * @si will move to next range and @di will move by bytes copied. + * @return : 0 for success or -ve for failure + * @f: The last fence if any + * @copied: out: number of bytes copied + */ +static int kfd_copy_single_range(struct cma_iter *si, struct cma_iter *di, + bool cma_write, struct dma_fence **f, + uint64_t *copied, struct kgd_mem **tmp_mem) +{ + int err = 0; + uint64_t copy_size, n; + uint64_t size = si->array->size; + struct kfd_bo *src_bo = si->cur_bo; + struct dma_fence *lfence = NULL; + + if (!src_bo || !di || !copied) + return -EINVAL; + *copied = 0; + if (f) + *f = NULL; + + while (size && !kfd_cma_iter_end(di)) { + struct dma_fence *fence = NULL; + + copy_size = min(size, (di->array->size - di->offset)); + + err = kfd_copy_bos(si, di, cma_write, copy_size, + &fence, &n, tmp_mem); + if (err) { + pr_err("CMA %d failed\n", err); + break; + } + + if (fence) { + err = kfd_fence_put_wait_if_diff_context(fence, + lfence); + lfence = fence; + if (err) + break; + } + + size -= n; + *copied += n; + err = kfd_cma_iter_advance(si, n); + if (err) + break; + err = kfd_cma_iter_advance(di, n); + if (err) + break; + } + + if (f) + *f = dma_fence_get(lfence); + dma_fence_put(lfence); + + return err; +} + +static int kfd_ioctl_cross_memory_copy(struct file *filep, + struct kfd_process *local_p, void *data) +{ + struct kfd_ioctl_cross_memory_copy_args *args = data; + struct kfd_memory_range *src_array, *dst_array; + struct kfd_process *remote_p; + struct task_struct *remote_task; + struct mm_struct *remote_mm; + struct pid *remote_pid; + struct dma_fence *lfence = NULL; + uint64_t copied = 0, total_copied = 0; + struct cma_iter di, si; + const char *cma_op; + int err = 0; + struct kgd_mem *tmp_mem = NULL; + + /* Check parameters */ + if (args->src_mem_range_array == 0 || args->dst_mem_range_array == 0 || + args->src_mem_array_size == 0 || args->dst_mem_array_size == 0) + return -EINVAL; + args->bytes_copied = 0; + + /* Allocate space for source and destination arrays */ + src_array = kmalloc_array((args->src_mem_array_size + + args->dst_mem_array_size), + sizeof(struct kfd_memory_range), + GFP_KERNEL); + if (!src_array) + return -ENOMEM; + dst_array = &src_array[args->src_mem_array_size]; + + if (copy_from_user(src_array, (void __user *)args->src_mem_range_array, + args->src_mem_array_size * + sizeof(struct kfd_memory_range))) { + err = -EFAULT; + goto copy_from_user_fail; + } + if (copy_from_user(dst_array, (void __user *)args->dst_mem_range_array, + args->dst_mem_array_size * + sizeof(struct kfd_memory_range))) { + err = -EFAULT; + goto copy_from_user_fail; + } + + /* Get remote process */ + remote_pid = find_get_pid(args->pid); + if (!remote_pid) { + pr_err("Cross mem copy failed. Invalid PID %d\n", args->pid); + err = -ESRCH; + goto copy_from_user_fail; + } + + remote_task = get_pid_task(remote_pid, PIDTYPE_PID); + if (!remote_pid) { + pr_err("Cross mem copy failed. Invalid PID or task died %d\n", + args->pid); + err = -ESRCH; + goto get_pid_task_fail; + } + + /* Check access permission */ + remote_mm = mm_access(remote_task, PTRACE_MODE_ATTACH_REALCREDS); + if (!remote_mm || IS_ERR(remote_mm)) { + err = IS_ERR(remote_mm) ? PTR_ERR(remote_mm) : -ESRCH; + if (err == -EACCES) { + pr_err("Cross mem copy failed. Permission error\n"); + err = -EPERM; + } else + pr_err("Cross mem copy failed. Invalid task %d\n", + err); + goto mm_access_fail; + } + + remote_p = kfd_get_process(remote_task); + if (IS_ERR(remote_p)) { + pr_err("Cross mem copy failed. Invalid kfd process %d\n", + args->pid); + err = -EINVAL; + goto kfd_process_fail; + } + /* Initialise cma_iter si & @di with source & destination range. */ + if (KFD_IS_CROSS_MEMORY_WRITE(args->flags)) { + cma_op = "WRITE"; + pr_debug("CMA WRITE: local -> remote\n"); + err = kfd_cma_iter_init(dst_array, args->dst_mem_array_size, + remote_p, remote_mm, remote_task, &di); + if (err) + goto kfd_process_fail; + err = kfd_cma_iter_init(src_array, args->src_mem_array_size, + local_p, current->mm, current, &si); + if (err) + goto kfd_process_fail; + } else { + cma_op = "READ"; + pr_debug("CMA READ: remote -> local\n"); + + err = kfd_cma_iter_init(dst_array, args->dst_mem_array_size, + local_p, current->mm, current, &di); + if (err) + goto kfd_process_fail; + err = kfd_cma_iter_init(src_array, args->src_mem_array_size, + remote_p, remote_mm, remote_task, &si); + if (err) + goto kfd_process_fail; + } + + /* Copy one si range at a time into di. After each call to + * kfd_copy_single_range() si will move to next range. di will be + * incremented by bytes copied + */ + while (!kfd_cma_iter_end(&si) && !kfd_cma_iter_end(&di)) { + struct dma_fence *fence = NULL; + + err = kfd_copy_single_range(&si, &di, + KFD_IS_CROSS_MEMORY_WRITE(args->flags), + &fence, &copied, &tmp_mem); + total_copied += copied; + + if (err) + break; + + /* Release old fence if a later fence is created. If no + * new fence is created, then keep the preivous fence + */ + if (fence) { + err = kfd_fence_put_wait_if_diff_context(fence, + lfence); + lfence = fence; + if (err) + break; + } + } + + /* Wait for the last fence irrespective of error condition */ + if (lfence) { + err = kfd_cma_fence_wait(lfence); + dma_fence_put(lfence); + if (err) + pr_err("CMA %s failed. BO timed out\n", cma_op); + } + + if (tmp_mem) + kfd_destroy_kgd_mem(tmp_mem); + + kfd_free_cma_bos(&si); + kfd_free_cma_bos(&di); + +kfd_process_fail: + mmput(remote_mm); +mm_access_fail: + put_task_struct(remote_task); +get_pid_task_fail: + put_pid(remote_pid); +copy_from_user_fail: + kfree(src_array); + + /* An error could happen after partial copy. In that case this will + * reflect partial amount of bytes copied + */ + args->bytes_copied = total_copied; + return err; +} + static int kfd_ioctl_export_dmabuf(struct file *filep, struct kfd_process *p, void *data) { @@ -3448,6 +4285,8 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, kfd_ioctl_rlc_spm, 0), + AMDKFD_IOCTL_DEF(AMDKFD_IOC_CROSS_MEMORY_COPY, + kfd_ioctl_cross_memory_copy, 0), }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index cab6a7cadfbf0..4498725592c2b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -406,6 +406,38 @@ struct kfd_bo { unsigned int mem_type; }; +struct cma_system_bo { + struct kgd_mem *mem; + struct sg_table *sg; + struct kfd_dev *dev; + struct list_head list; +}; + +/* Similar to iov_iter */ +struct cma_iter { + /* points to current entry of range array */ + struct kfd_memory_range *array; + /* total number of entries in the initial array */ + unsigned long nr_segs; + /* total amount of data pointed by kfd array*/ + unsigned long total; + /* offset into the entry pointed by cma_iter.array */ + unsigned long offset; + struct kfd_process *p; + struct mm_struct *mm; + struct task_struct *task; + /* current kfd_bo associated with cma_iter.array.va_addr */ + struct kfd_bo *cur_bo; + /* offset w.r.t cur_bo */ + unsigned long bo_offset; + /* If cur_bo is a userptr BO, then a shadow system BO is created + * using its underlying pages. cma_bo holds this BO. cma_list is a + * list cma_bos created in one session + */ + struct cma_system_bo *cma_bo; + struct list_head cma_list; +}; + enum kfd_mempool { KFD_MEMPOOL_SYSTEM_CACHEABLE = 1, KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index e219d556e2ad1..cff1cb83a10c7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -744,7 +744,7 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, int err; err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, gpu_va, size, - pdd->drm_priv, mem, NULL, + pdd->drm_priv, NULL, &mem, NULL, flags, false); if (err) goto err_alloc_mem; diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index bcda022281f26..0712a6aed43b5 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -840,6 +840,37 @@ struct kfd_ioctl_ipc_import_handle_args { __u32 flags; /* from KFD */ }; +struct kfd_memory_range { + __u64 va_addr; + __u64 size; +}; + +/* flags definitions + * BIT0: 0: read operation, 1: write operation. + * This also identifies if the src or dst array belongs to remote process + */ +#define KFD_CROSS_MEMORY_RW_BIT (1 << 0) +#define KFD_SET_CROSS_MEMORY_READ(flags) (flags &= ~KFD_CROSS_MEMORY_RW_BIT) +#define KFD_SET_CROSS_MEMORY_WRITE(flags) (flags |= KFD_CROSS_MEMORY_RW_BIT) +#define KFD_IS_CROSS_MEMORY_WRITE(flags) (flags & KFD_CROSS_MEMORY_RW_BIT) + +struct kfd_ioctl_cross_memory_copy_args { + /* to KFD: Process ID of the remote process */ + __u32 pid; + /* to KFD: See above definition */ + __u32 flags; + /* to KFD: Source GPU VM range */ + __u64 src_mem_range_array; + /* to KFD: Size of above array */ + __u64 src_mem_array_size; + /* to KFD: Destination GPU VM range */ + __u64 dst_mem_range_array; + /* to KFD: Size of above array */ + __u64 dst_mem_array_size; + /* from KFD: Total amount of bytes copied */ + __u64 bytes_copied; +}; + /* Guarantee host access to memory */ #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 /* Fine grained coherency between all devices with access */ @@ -1785,7 +1816,11 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_RLC_SPM \ AMDKFD_IOWR(0x84, struct kfd_ioctl_spm_args) +#define AMDKFD_IOC_CROSS_MEMORY_COPY \ + AMDKFD_IOWR(0x83, struct kfd_ioctl_cross_memory_copy_args) + #define AMDKFD_COMMAND_START_2 0x80 #define AMDKFD_COMMAND_END_2 0x85 + #endif From 41bf47ff1465e65824242fd210c14e67c405417e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 7 Jul 2022 14:08:06 +0800 Subject: [PATCH 0765/2653] drm/amdkcl: fix build error Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 10 ++-- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 50 +++++++++++++------ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +- 4 files changed, 41 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index fd2bf0257f499..1d74969ef2afe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -176,7 +176,7 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle); bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev); -int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, +int amdgpu_amdkfd_copy_mem_to_mem(struct amdgpu_device *adev, struct kgd_mem *src_mem, uint64_t src_offset, struct kgd_mem *dst_mem, uint64_t dest_offset, uint64_t size, struct dma_fence **f, uint64_t *actual_size); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 945bbe20561cc..1b88c90188a7d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -3525,12 +3525,11 @@ int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem) return 0; } -int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, +int amdgpu_amdkfd_copy_mem_to_mem(struct amdgpu_device *adev, struct kgd_mem *src_mem, uint64_t src_offset, struct kgd_mem *dst_mem, uint64_t dst_offset, uint64_t size, struct dma_fence **f, uint64_t *actual_size) { - struct amdgpu_device *adev = NULL; struct amdgpu_copy_mem src, dst; struct ww_acquire_ctx ticket; struct list_head list, duplicates; @@ -3538,19 +3537,18 @@ int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, struct dma_fence *fence = NULL; int i, r; - if (!kgd || !src_mem || !dst_mem || !actual_size) + if (!adev|| !src_mem || !dst_mem || !actual_size) return -EINVAL; *actual_size = 0; - adev = get_amdgpu_device(kgd); INIT_LIST_HEAD(&list); INIT_LIST_HEAD(&duplicates); src.bo = &src_mem->bo->tbo; dst.bo = &dst_mem->bo->tbo; - src.mem = &src.bo->mem; - dst.mem = &dst.bo->mem; + src.mem = src.bo->resource; + dst.mem = dst.bo->resource; src.offset = src_offset; dst.offset = dst_offset; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index a4538aacf7aab..04273eb7603c5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1763,7 +1763,7 @@ static int kfd_create_sg_table_from_userptr_bo(struct kfd_bo *bo, flags = FOLL_WRITE; locked = 1; mmap_read_lock(mm); - n = get_user_pages_remote(mm, pa, nents, flags, process_pages, + n = kcl_get_user_pages_remote(task, mm, pa, nents, flags, process_pages, NULL, &locked); if (locked) mmap_read_unlock(mm); @@ -1808,11 +1808,13 @@ static void kfd_free_cma_bos(struct cma_iter *ci) list_for_each_entry_safe(cma_bo, tmp, &ci->cma_list, list) { struct kfd_dev *dev = cma_bo->dev; + struct kfd_process_device *pdd; /* sg table is deleted by free_memory_of_gpu */ if (cma_bo->sg) kfd_put_sg_table(cma_bo->sg); - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, cma_bo->mem, NULL); + pdd = kfd_get_process_device_data(dev, ci->p); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, cma_bo->mem, pdd->drm_priv, NULL); list_del(&cma_bo->list); kfree(cma_bo); } @@ -1908,9 +1910,10 @@ static int kfd_create_cma_system_bo(struct kfd_dev *kdev, struct kfd_bo *bo, goto pdd_fail; } - ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, bo_size, + ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, 0ULL, bo_size, pdd->drm_priv, cbo->sg, - &cbo->mem, NULL, flags); + &cbo->mem, NULL, flags, + false); mutex_unlock(&p->mutex); if (ret) { pr_err("Failed to create shadow system BO %d\n", ret); @@ -1918,7 +1921,7 @@ static int kfd_create_cma_system_bo(struct kfd_dev *kdev, struct kfd_bo *bo, } if (bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { - ret = amdgpu_amdkfd_copy_mem_to_mem(kdev->kgd, bo->mem, + ret = amdgpu_amdkfd_copy_mem_to_mem(kdev->adev, bo->mem, offset, cbo->mem, 0, bo_size, &f, size); if (ret) { @@ -1943,7 +1946,7 @@ static int kfd_create_cma_system_bo(struct kfd_dev *kdev, struct kfd_bo *bo, return ret; copy_fail: - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(kdev->kgd, bo->mem, NULL); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(kdev->adev, bo->mem, pdd->drm_priv, NULL); pdd_fail: if (cbo->sg) { kfd_put_sg_table(cbo->sg); @@ -2100,7 +2103,7 @@ static int kfd_copy_userptr_bos(struct cma_iter *si, struct cma_iter *di, nl = min_t(unsigned int, MAX_PP_KMALLOC_COUNT, nents); locked = 1; mmap_read_lock(ri->mm); - nl = get_user_pages_remote(ri->mm, rva, nl, + nl = kcl_get_user_pages_remote(ri->task, ri->mm, rva, nl, flags, process_pages, NULL, &locked); if (locked) @@ -2177,9 +2180,9 @@ static int kfd_create_kgd_mem(struct kfd_dev *kdev, uint64_t size, return -EINVAL; } - ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, size, + ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, 0ULL, size, pdd->drm_priv, NULL, - mem, NULL, flags); + mem, NULL, flags, false); mutex_unlock(&p->mutex); if (ret) { pr_err("Failed to create shadow system BO %d\n", ret); @@ -2191,11 +2194,28 @@ static int kfd_create_kgd_mem(struct kfd_dev *kdev, uint64_t size, static int kfd_destroy_kgd_mem(struct kgd_mem *mem) { + struct amdgpu_device *adev; + struct task_struct *task; + struct kfd_process *p; + struct kfd_process_device *pdd; + uint32_t gpu_id, gpu_idx; + int r; + if (!mem) return -EINVAL; + adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); + task = get_pid_task(mem->process_info->pid, PIDTYPE_PID); + p = kfd_get_process(task); + r = kfd_process_gpuid_from_adev(p, adev, &gpu_id, &gpu_idx); + if (r < 0) { + pr_warn("no gpu id found, mem maybe leaking\n"); + return -EINVAL; + } + pdd = kfd_process_device_from_gpuidx(p, gpu_idx); + /* param adev is not used*/ - return amdgpu_amdkfd_gpuvm_free_memory_of_gpu(NULL, mem, NULL); + return amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, mem, pdd->drm_priv, NULL); } /* Copies @size bytes from si->cur_bo to di->cur_bo starting at their @@ -2252,7 +2272,7 @@ static int kfd_copy_bos(struct cma_iter *si, struct cma_iter *di, dst_mem = di->cma_bo->mem; dst_offset = di->bo_offset & (PAGE_SIZE - 1); list_add_tail(&di->cma_bo->list, &di->cma_list); - } else if (src_bo->dev->kgd != dst_bo->dev->kgd) { + } else if (src_bo->dev->adev != dst_bo->dev->adev) { /* This indicates that atleast on of the BO is in local mem. * If both are in local mem of different devices then create an * intermediate System BO and do a double copy @@ -2273,7 +2293,7 @@ static int kfd_copy_bos(struct cma_iter *si, struct cma_iter *di, return -EINVAL; } - if (amdgpu_amdkfd_copy_mem_to_mem(src_bo->dev->kgd, + if (amdgpu_amdkfd_copy_mem_to_mem(src_bo->dev->adev, src_bo->mem, si->bo_offset, *tmp_mem, 0, size, f, &size)) @@ -2295,7 +2315,7 @@ static int kfd_copy_bos(struct cma_iter *si, struct cma_iter *di, return -EINVAL; } - err = amdgpu_amdkfd_copy_mem_to_mem(dev->kgd, src_mem, src_offset, + err = amdgpu_amdkfd_copy_mem_to_mem(dev->adev, src_mem, src_offset, dst_mem, dst_offset, size, f, copied); /* The tmp_bo allocates additional memory. So it is better to wait and @@ -3264,7 +3284,7 @@ static int criu_restore_memory_of_gpu_ipc(struct kfd_process_device *pdd, */ ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(dev->adev, bo_bucket->addr, bo_bucket->size, pdd->drm_priv, - kgd_mem, &offset, + NULL, kgd_mem, &offset, bo_bucket->alloc_flags, true); if (ret) { pr_err("Could not create the BO\n"); @@ -3358,7 +3378,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, } /* Create the BO */ ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(pdd->dev->adev, bo_bucket->addr, - bo_bucket->size, pdd->drm_priv, kgd_mem, + bo_bucket->size, pdd->drm_priv, NULL, kgd_mem, &offset, bo_bucket->alloc_flags, criu_resume); if (ret) { pr_err("Could not create the BO\n"); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index cff1cb83a10c7..ad0b2abfe7e18 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -744,7 +744,7 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, int err; err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, gpu_va, size, - pdd->drm_priv, NULL, &mem, NULL, + pdd->drm_priv, NULL, mem, NULL, flags, false); if (err) goto err_alloc_mem; From 5b84ce3b0aed83417a230962eebe6124dd313e4f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 12 Jul 2022 16:30:02 +0800 Subject: [PATCH 0766/2653] drm/amdkcl: test for drm/display/drm_dp_helper.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 5 ++++- drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 | 6 ++++-- .../dkms/m4/drm-dp-cec-correlation-functions.m4 | 8 ++++++-- .../dkms/m4/drm-dp-link-train-channel-eq-delay.m4 | 6 ++++-- .../m4/drm-dp-link-train-clock-recovery-delay.m4 | 4 +++- .../amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 | 6 ++++-- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ include/kcl/header/drm/display/drm_dp_helper.h | 14 ++++++++++++++ include/kcl/kcl_drm_dp_cec.h | 4 +++- include/kcl/kcl_drm_dp_helper.h | 4 +++- 10 files changed, 51 insertions(+), 12 deletions(-) create mode 100644 include/kcl/header/drm/display/drm_dp_helper.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 812ed631934a4..1317935af57ad 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -306,6 +306,9 @@ /* drm_dev_unplug() is available */ #define HAVE_DRM_DEV_UNPLUG 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DP_HELPER_H 1 + /* display_info->edid_hdmi_rgb444_dc_modes is available */ #define HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES 1 @@ -340,7 +343,7 @@ #define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 /* Define to 1 if you have the header file. */ -#define HAVE_DRM_DP_DRM_DP_HELPER_H 1 +/* #undef HAVE_DRM_DP_DRM_DP_HELPER_H */ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DP_DRM_DP_MST_HELPER_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 index 49994828e0873..a20efecd2b022 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 @@ -5,11 +5,13 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_AUX_DRM_DEV], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include - #endif + #endif ], [ struct drm_dp_aux dda; dda.drm_dev = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 index 141e3a6ff65d0..30cf21b106f4b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include @@ -19,7 +21,9 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ [drm_dp_cec* correlation functions are available]) ], [ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 index e6713844783e2..5dc461c4db3df 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 @@ -5,11 +5,13 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include - #endif + #endif ], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 index af98096981e77..4d0c1a7e21313 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 index f49bd33a93a19..27b63066be2dc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 @@ -5,11 +5,13 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include - #endif + #endif ], [ drm_dp_send_real_edid_checksum(NULL, 0); ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index db107edff41aa..b4a3e320a016d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -62,6 +62,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/dp/drm_dp_mst_helper.h]) + dnl # + dnl # v5.18-rc2-594-gda68386d9edb + dnl # drm: Rename dp/ to display/ + dnl # + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dp_helper.h]) + dnl # dnl # v5.7-13141-gca5999fde0a1 dnl # mm: introduce include/linux/pgtable.h diff --git a/include/kcl/header/drm/display/drm_dp_helper.h b/include/kcl/header/drm/display/drm_dp_helper.h new file mode 100644 index 0000000000000..83269a83e90ba --- /dev/null +++ b/include/kcl/header/drm/display/drm_dp_helper.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DP_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DP_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) +#include_next +#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) +#include_next +#else +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_drm_dp_cec.h b/include/kcl/kcl_drm_dp_cec.h index b810aae53f69a..e76e90cc0fe59 100644 --- a/include/kcl/kcl_drm_dp_cec.h +++ b/include/kcl/kcl_drm_dp_cec.h @@ -8,7 +8,9 @@ #ifndef __KCL_KCL_DRM_DP_CEC_H__ #define __KCL_KCL_DRM_DP_CEC_H__ -#ifdef HAVE_DRM_DP_DRM_DP_HELPER_H +#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 6168671062032..2d6d15d2bedb8 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -30,7 +30,9 @@ #include #include -#ifdef HAVE_DRM_DP_DRM_DP_HELPER_H +#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include From 604b6e15117ea92eed6b10afe842e58dcaa7ff8f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 12 Jul 2022 16:34:47 +0800 Subject: [PATCH 0767/2653] drm/amdkcl: test for drm/display/drm_dp_mst_helper.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 5 ++++- .../amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 | 8 ++++++-- .../gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 | 12 +++++++----- .../dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 | 4 +++- .../gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 | 4 +++- .../amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 | 4 +++- .../gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 | 4 +++- .../drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 | 4 +++- .../gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 | 12 +++++++++--- .../amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 | 4 +++- .../drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 | 4 +++- drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 | 12 +++++++++--- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ .../drm-up-update-payload-part1-start-slot-arg.m4 | 4 +++- .../amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 | 4 +++- .../kcl/backport/kcl_drm_dp_mst_helper_backport.h | 4 +++- include/kcl/header/drm/display/drm_dp_mst_helper.h | 14 ++++++++++++++ 17 files changed, 85 insertions(+), 24 deletions(-) create mode 100644 include/kcl/header/drm/display/drm_dp_mst_helper.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1317935af57ad..df734680faa29 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -309,6 +309,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DISPLAY_DRM_DP_HELPER_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H 1 + /* display_info->edid_hdmi_rgb444_dc_modes is available */ #define HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES 1 @@ -346,7 +349,7 @@ /* #undef HAVE_DRM_DP_DRM_DP_HELPER_H */ /* Define to 1 if you have the header file. */ -#define HAVE_DRM_DP_DRM_DP_MST_HELPER_H 1 +/* #undef HAVE_DRM_DP_DRM_DP_MST_HELPER_H */ /* drm_dp_link_train_channel_eq_delay() has 2 args */ #define HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 index 65b49ae69f164..10cfe8e436f12 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include @@ -22,7 +24,9 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ dnl # drm/dp_mst: Manually overwrite PBN divider for calculating timeslots dnl # AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 index 8dc9ef9c8dd48..eabc0261dd0be 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 @@ -5,11 +5,13 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H - #include - #else - #include - #endif + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif ], [ drm_dp_calc_pbn_mode(0, 0, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 index 1f637c137dad1..42d7b5595403a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 index df6b3450485e0..318f729096712 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 index 65d24257c4d25..806158f1562a8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 index 913f4586acf6c..7c01c0479075e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DETECT_PORT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 index 4c48b47b4c9bf..522d9e0e4b565 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 index 5540428fc8b49..683d563cfc7bb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -4,7 +4,9 @@ dnl # drm/dp-mst-helper: Remove hotplug callback dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG], [ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include @@ -28,7 +30,9 @@ dnl # drm/dp/mst: split connector registration into two parts (v2) dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR], [ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include @@ -48,7 +52,9 @@ dnl # drm/dp_mst: Remove drm_dp_mst_topology_cbs.destroy_connector dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR], [ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 index 039132d5081d7..961c150fe148e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index 720e605f38d4f..646dc3b137f68 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 index 5065a8ab6d0d6..611bd25368735 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 @@ -8,7 +8,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include @@ -29,7 +31,9 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include @@ -48,7 +52,9 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index b4a3e320a016d..ccdc2e200d0a0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -68,6 +68,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/display/drm_dp_helper.h]) + dnl # + dnl # v5.18-rc2-594-gda68386d9edb + dnl # drm: Rename dp/ to display/ + dnl # + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dp_mst_helper.h]) + dnl # dnl # v5.7-13141-gca5999fde0a1 dnl # mm: introduce include/linux/pgtable.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 index 0c25016be1da4..7839b7b00baee 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 index ca29f48cb467a..66d1beb0b8a34 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 2412859be272a..5623abd34416b 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -22,7 +22,9 @@ #ifndef _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ #define _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ -#ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H +#if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/include/kcl/header/drm/display/drm_dp_mst_helper.h b/include/kcl/header/drm/display/drm_dp_mst_helper.h new file mode 100644 index 0000000000000..35221a4f00645 --- /dev/null +++ b/include/kcl/header/drm/display/drm_dp_mst_helper.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DP_MST_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DP_MST_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) +#include_next +#elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) +#include_next +#else +#include_next +#endif + +#endif + From e678b0fcd5212832153110bdb4384b2bba40a96a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 13 Jul 2022 15:06:51 +0800 Subject: [PATCH 0768/2653] drm/amdkcl: test for drm_* headers moved into drm/display directory Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 15 +++++++++++++++ .../dkms/m4/drm-hdcp-update-content-protection.m4 | 4 ++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ include/kcl/header/drm/display/drm_dsc.h | 12 ++++++++++++ include/kcl/header/drm/display/drm_dsc_helper.h | 10 ++++++++++ include/kcl/header/drm/display/drm_hdcp.h | 11 +++++++++++ include/kcl/header/drm/display/drm_hdcp_helper.h | 10 ++++++++++ include/kcl/header/drm/display/drm_hdmi_helper.h | 10 ++++++++++ include/kcl/kcl_drm_hdcp.h | 2 +- 9 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 include/kcl/header/drm/display/drm_dsc.h create mode 100644 include/kcl/header/drm/display/drm_dsc_helper.h create mode 100644 include/kcl/header/drm/display/drm_hdcp.h create mode 100644 include/kcl/header/drm/display/drm_hdcp_helper.h create mode 100644 include/kcl/header/drm/display/drm_hdmi_helper.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index df734680faa29..3432ffad2b246 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -312,6 +312,21 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DSC_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_HDCP_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_HDCP_HELPER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_HDMI_HELPER_H 1 + /* display_info->edid_hdmi_rgb444_dc_modes is available */ #define HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 index 5b8c871002830..f91f55f90ced8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H + #include + #else #include + #endif ], [ drm_hdcp_update_content_protection(NULL, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index ccdc2e200d0a0..17fb837a138c4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -74,6 +74,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/display/drm_dp_mst_helper.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dsc.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dsc_helper.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdmi_helper.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdcp_helper.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdcp.h]) + dnl # dnl # v5.7-13141-gca5999fde0a1 dnl # mm: introduce include/linux/pgtable.h diff --git a/include/kcl/header/drm/display/drm_dsc.h b/include/kcl/header/drm/display/drm_dsc.h new file mode 100644 index 0000000000000..7b4f143d14323 --- /dev/null +++ b/include/kcl/header/drm/display/drm_dsc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DSC_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DSC_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DSC_H) +#include_next +#else +#include +#endif + +#endif + diff --git a/include/kcl/header/drm/display/drm_dsc_helper.h b/include/kcl/header/drm/display/drm_dsc_helper.h new file mode 100644 index 0000000000000..162730616ccb2 --- /dev/null +++ b/include/kcl/header/drm/display/drm_dsc_helper.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DSC_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DSC_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) +#include_next +#endif + +#endif + diff --git a/include/kcl/header/drm/display/drm_hdcp.h b/include/kcl/header/drm/display/drm_hdcp.h new file mode 100644 index 0000000000000..a3c3aad2a794d --- /dev/null +++ b/include/kcl/header/drm/display/drm_hdcp.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_DISPLAY_HDCP_H_INCLUDED_H_ +#define _KCL_HEADER_DRM_DISPLAY_HDCP_H_INCLUDED_H_ + +#ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/header/drm/display/drm_hdcp_helper.h b/include/kcl/header/drm/display/drm_hdcp_helper.h new file mode 100644 index 0000000000000..047decb7fc695 --- /dev/null +++ b/include/kcl/header/drm/display/drm_hdcp_helper.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_HDCP_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_HDCP_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_HDCP_HELPER_H) +#include_next +#endif + +#endif + diff --git a/include/kcl/header/drm/display/drm_hdmi_helper.h b/include/kcl/header/drm/display/drm_hdmi_helper.h new file mode 100644 index 0000000000000..da7492d32e946 --- /dev/null +++ b/include/kcl/header/drm/display/drm_hdmi_helper.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_HDMI_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_HDMI_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_HDMI_HELPER_H) +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_drm_hdcp.h b/include/kcl/kcl_drm_hdcp.h index b3f6318e1f652..76c7823fe6f88 100644 --- a/include/kcl/kcl_drm_hdcp.h +++ b/include/kcl/kcl_drm_hdcp.h @@ -9,7 +9,7 @@ #define AMDKCL_DRM_HDCP_H #ifdef CONFIG_DRM_AMD_DC_HDCP -#include +#include #include /* changed in v4.16-rc7-1717-gb8e47d87be65 From 8fadd3c627db446cdfcc1cd6184ae58683b7339e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 19 Jul 2022 18:12:49 +0800 Subject: [PATCH 0769/2653] drm/amdkcl: fix build error by adding missing arguments Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 10e91898146ca..701bc5194f0f6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -278,7 +278,7 @@ static int init_user_queue(struct process_queue_manager *pqm, &(*q)->gang_ctx_bo, &(*q)->gang_ctx_gpu_addr, &(*q)->gang_ctx_cpu_ptr, - false); + false, true); if (retval) { pr_err("failed to allocate gang context bo\n"); goto cleanup; From bc82156fd9e049b18c5a6dce745400ee8835d803 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 14:05:13 +0800 Subject: [PATCH 0770/2653] drm/amdkcl: fix build error of amdkcl_ttm_resvp Signed-off-by: Leslie Shi Signed-off-by: Ma Jun Change-Id: Ifbb5c079dfa13b34b5ae0d893ec243165da74ce8 --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 2 +- drivers/gpu/drm/ttm/ttm_bo.c | 8 ++++---- drivers/gpu/drm/ttm/ttm_bo_vm.c | 4 ++-- drivers/gpu/drm/ttm/ttm_resource.c | 4 ++-- 10 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 1b88c90188a7d..9458f728e9cc7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -3304,7 +3304,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu * goto validate_map_fail; } } - dma_resv_for_each_fence(&cursor, bo->tbo.base.resv, + dma_resv_for_each_fence(&cursor, amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL, fence) { ret = amdgpu_sync_fence(&sync_obj, fence, GFP_KERNEL); if (ret) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 0485684c76117..2b7cb217472b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -192,7 +192,7 @@ static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) return ret; unlock: - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index d799d4e4a4d06..c7289071dadfa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -744,7 +744,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev, if (unlikely(r)) goto fail_unreserve; - dma_resv_add_fence(bo->tbo.base.resv, fence, + dma_resv_add_fence(amdkcl_ttm_resvp(&bo->tbo), fence, DMA_RESV_USAGE_KERNEL); dma_fence_put(fence); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 317bb51569188..68dbaff20329c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -378,7 +378,7 @@ static int amdgpu_vkms_prepare_fb(struct drm_plane *plane, return r; } - r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&rbo->tbo), 1); if (r) { dev_err(adev->dev, "allocating fence slot failed (%d)\n", r); goto error_unlock; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c index 0c1ef5850a5eb..1e79d31544a98 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c @@ -75,7 +75,7 @@ static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p, uint64_t value; long r; - r = dma_resv_wait_timeout(vmbo->bo.tbo.base.resv, DMA_RESV_USAGE_KERNEL, + r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&vmbo->bo.tbo), DMA_RESV_USAGE_KERNEL, true, MAX_SCHEDULE_TIMEOUT); if (r < 0) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c index 30022123b0bf6..10f31d6bd6a46 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c @@ -471,7 +471,7 @@ int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, bp.xcp_id_plus1 = xcp_id + 1; if (vm->root.bo) - bp.resv = vm->root.bo->tbo.base.resv; + bp.resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); return amdgpu_bo_create_vm(adev, &bp, vmbo); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 794e27a83ea24..744e0b8df16b7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -631,7 +631,7 @@ svm_range_vram_node_new(struct kfd_node *node, struct svm_range *prange, } } - r = dma_resv_reserve_fences(bo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&bo->tbo), 1); if (r) { pr_debug("failed %d to reserve bo\n", r); amdgpu_bo_unreserve(bo); diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 0c98436e7cfbb..ba7b5b054faf3 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -151,7 +151,7 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo, } } - ret = dma_resv_reserve_fences(bo->base.resv, 1); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(bo), 1); if (ret) goto out_err; @@ -627,7 +627,7 @@ static int ttm_bo_evict_alloc(struct ttm_device *bdev, */ void ttm_bo_pin(struct ttm_buffer_object *bo) { - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); WARN_ON_ONCE(!kref_read(&bo->kref)); spin_lock(&bo->bdev->lru_lock); if (bo->resource) @@ -646,7 +646,7 @@ EXPORT_SYMBOL(ttm_bo_pin); */ void ttm_bo_unpin(struct ttm_buffer_object *bo) { - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); WARN_ON_ONCE(!kref_read(&bo->kref)); if (WARN_ON_ONCE(!bo->pin_count)) return; @@ -686,7 +686,7 @@ static int ttm_bo_add_move_fence(struct ttm_buffer_object *bo, dma_resv_add_fence(amdkcl_ttm_resvp(bo), fence, DMA_RESV_USAGE_KERNEL); - ret = dma_resv_reserve_fences(bo->base.resv, 1); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(bo), 1); dma_fence_put(fence); return ret; } diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 52b0ec32ba6f2..18e898018c266 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -52,7 +52,7 @@ static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, /* * Quick non-stalling check for idle. */ - if (dma_resv_test_signaled(bo->base.resv, DMA_RESV_USAGE_KERNEL)) + if (dma_resv_test_signaled(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_KERNEL)) return 0; /* @@ -77,7 +77,7 @@ static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, /* * Ordinary wait. */ - err = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_KERNEL, true, + err = dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_KERNEL, true, MAX_SCHEDULE_TIMEOUT); if (unlikely(err < 0)) { return (err != -ERESTARTSYS) ? VM_FAULT_SIGBUS : diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c index e2c82ad07eb44..8733aa0092367 100644 --- a/drivers/gpu/drm/ttm/ttm_resource.c +++ b/drivers/gpu/drm/ttm/ttm_resource.c @@ -167,8 +167,8 @@ void ttm_lru_bulk_move_tail(struct ttm_lru_bulk_move *bulk) continue; lockdep_assert_held(&pos->first->bo->bdev->lru_lock); - dma_resv_assert_held(pos->first->bo->base.resv); - dma_resv_assert_held(pos->last->bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(pos->first->bo)); + dma_resv_assert_held(amdkcl_ttm_resvp(pos->last->bo)); man = ttm_manager_type(pos->first->bo->bdev, i); list_bulk_move_tail(&man->lru[j], &pos->first->lru.link, From d0b71cf30c16b14cac325b5710db44dffff2d638 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 14:13:33 +0800 Subject: [PATCH 0771/2653] drm/amdkcl: wrap the code under HAVE_KTIME_IS_UNION for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c index 91d638098889d..ff1e1d8a3a2ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c @@ -114,8 +114,13 @@ void amdgpu_show_fdinfo(struct drm_printer *p, struct drm_file *file) stats[TTM_PL_TT].drm.private) / 1024UL); for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { +#ifdef HAVE_KTIME_IS_UNION + if (!usage[hw_ip].tv64) + continue; +#else if (!usage[hw_ip]) continue; +#endif drm_printf(p, "drm-engine-%s:\t%lld ns\n", amdgpu_ip_name[hw_ip], ktime_to_ns(usage[hw_ip])); From e7b722d9b0b435a78e9e0af2b2aed72e84dd59a7 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 14:31:08 +0800 Subject: [PATCH 0772/2653] drm/amdkcl: fix compile error if DEFINE_DEBUGFS_ATTRIBUTE not defined Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 776c12442de41..a794496df7b08 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -4162,7 +4162,6 @@ DEFINE_SHOW_ATTRIBUTE(mst_topo); #ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, visual_confirm_set, "%llu\n"); -#endif /* @@ -4197,6 +4196,7 @@ static int skip_detection_link_training_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops, skip_detection_link_training_get, skip_detection_link_training_set, "%llu\n"); +#endif /* * Dumps the DCC_EN bit for each pipe. From 0be20798ac6361de7d7acbb16d59f480ddff424c Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 14:46:50 +0800 Subject: [PATCH 0773/2653] drm/amdkcl: include linux/debugfs.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_resource.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c index 8733aa0092367..185d23323db70 100644 --- a/drivers/gpu/drm/ttm/ttm_resource.c +++ b/drivers/gpu/drm/ttm/ttm_resource.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include From 2f512faae9e8f88c902761d095f1d08c67c309d3 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 15:11:01 +0800 Subject: [PATCH 0774/2653] drm/amdkcl: adjust vblank_lock position of struct amdgpu_display_manager Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 6d04b4a2e0de7..5a3d99c944f10 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -474,6 +474,13 @@ struct amdgpu_display_manager { */ bool audio_registered; + /** + * @vblank_lock: + * + * Guards access to deferred vblank work state. + */ + spinlock_t vblank_lock; + /** * @irq_handler_list_low_tab: * From a980e4d0f7ac35e05a71fec27591bdb3a74602c6 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 13 Jul 2022 16:09:52 +0800 Subject: [PATCH 0775/2653] drm/amdkcl: fake dma_resv api using legacy structure Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 841 ++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 7 +- drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 20 + drivers/gpu/drm/amd/dkms/pre-build.sh | 8 +- include/kcl/kcl_dma-resv.h | 151 ++++ 5 files changed, 1024 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c new file mode 100644 index 0000000000000..e3525a0973f71 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -0,0 +1,841 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2012-2014 Canonical Ltd (Maarten Lankhorst) + * + * Based on bo.c which bears the following copyright notice, + * but is dual licensed: + * + * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ +/* + * Authors: Thomas Hellstrom + */ +#include +#include +#include +#include +#include +#include +#include + +/* Copied from drivers/dma-buf/dma-resv.c */ +#ifndef HAVE_DMA_RESV_FENCES + +/** + * DOC: Reservation Object Overview + * + * The reservation object provides a mechanism to manage a container of + * dma_fence object associated with a resource. A reservation object + * can have any number of fences attaches to it. Each fence carries an usage + * parameter determining how the operation represented by the fence is using the + * resource. The RCU mechanism is used to protect read access to fences from + * locked write-side updates. + * + * See struct dma_resv for more details. + */ + +extern struct ww_class reservation_ww_class; + +/** + * dma_resv_list_alloc - allocate fence list + * @shared_max: number of fences we need space for + * + * Allocate a new dma_resv_list and make sure to correctly initialize + * shared_max. + */ +static struct dma_resv_list *dma_resv_list_alloc(unsigned int shared_max) +{ + struct dma_resv_list *list; + + list = kmalloc(struct_size(list, shared, shared_max), GFP_KERNEL); + if (!list) + return NULL; + + list->shared_max = (ksize(list) - offsetof(typeof(*list), shared)) / + sizeof(*list->shared); + + return list; +} + +/** + * dma_resv_list_free - free fence list + * @list: list to free + * + * Free a dma_resv_list and make sure to drop all references. + */ +static void dma_resv_list_free(struct dma_resv_list *list) +{ + unsigned int i; + + if (!list) + return; + + for (i = 0; i < list->shared_count; ++i) + dma_fence_put(rcu_dereference_protected(list->shared[i], true)); + + kfree_rcu(list, rcu); +} + +/** + * dma_resv_init - initialize a reservation object + * @obj: the reservation object + */ +void dma_resv_init(struct dma_resv *obj) +{ + ww_mutex_init(&obj->lock, &reservation_ww_class); + seqcount_ww_mutex_init(&obj->seq, &obj->lock); + + RCU_INIT_POINTER(obj->fence, NULL); + RCU_INIT_POINTER(obj->fence_excl, NULL); +} +EXPORT_SYMBOL(dma_resv_init); + +/** + * dma_resv_fini - destroys a reservation object + * @obj: the reservation object + */ +void dma_resv_fini(struct dma_resv *obj) +{ + struct dma_resv_list *fobj; + struct dma_fence *excl; + + /* + * This object should be dead and all references must have + * been released to it, so no need to be protected with rcu. + */ + excl = rcu_dereference_protected(obj->fence_excl, 1); + if (excl) + dma_fence_put(excl); + + fobj = rcu_dereference_protected(obj->fence, 1); + dma_resv_list_free(fobj); + ww_mutex_destroy(&obj->lock); +} +EXPORT_SYMBOL(dma_resv_fini); + +/** + * dma_resv_reserve_fences - Reserve space to add shared fences to + * a dma_resv. + * @obj: reservation object + * @num_fences: number of fences we want to add + * + * Should be called before dma_resv_add_shared_fence(). Must + * be called with @obj locked through dma_resv_lock(). + * + * Note that the preallocated slots need to be re-reserved if @obj is unlocked + * at any time before calling dma_resv_add_shared_fence(). This is validated + * when CONFIG_DEBUG_MUTEXES is enabled. + * + * RETURNS + * Zero for success, or -errno + */ +int dma_resv_reserve_fences(struct dma_resv *obj, unsigned int num_fences) +{ + struct dma_resv_list *old, *new; + unsigned int i, j, k, max; + + dma_resv_assert_held(obj); + + old = dma_resv_shared_list(obj); + if (old && old->shared_max) { + if ((old->shared_count + num_fences) <= old->shared_max) + return 0; + max = max(old->shared_count + num_fences, old->shared_max * 2); + } else { + max = max(4ul, roundup_pow_of_two(num_fences)); + } + + new = dma_resv_list_alloc(max); + if (!new) + return -ENOMEM; + + /* + * no need to bump fence refcounts, rcu_read access + * requires the use of kref_get_unless_zero, and the + * references from the old struct are carried over to + * the new. + */ + for (i = 0, j = 0, k = max; i < (old ? old->shared_count : 0); ++i) { + struct dma_fence *fence; + + fence = rcu_dereference_protected(old->shared[i], + dma_resv_held(obj)); + if (dma_fence_is_signaled(fence)) + RCU_INIT_POINTER(new->shared[--k], fence); + else + RCU_INIT_POINTER(new->shared[j++], fence); + } + new->shared_count = j; + + /* + * We are not changing the effective set of fences here so can + * merely update the pointer to the new array; both existing + * readers and new readers will see exactly the same set of + * active (unsignaled) shared fences. Individual fences and the + * old array are protected by RCU and so will not vanish under + * the gaze of the rcu_read_lock() readers. + */ + rcu_assign_pointer(obj->fence, new); + + if (!old) + return 0; + + /* Drop the references to the signaled fences */ + for (i = k; i < max; ++i) { + struct dma_fence *fence; + + fence = rcu_dereference_protected(new->shared[i], + dma_resv_held(obj)); + dma_fence_put(fence); + } + kfree_rcu(old, rcu); + + return 0; +} +EXPORT_SYMBOL(dma_resv_reserve_fences); + +#ifdef CONFIG_DEBUG_MUTEXES +/** + * dma_resv_reset_max_fences - reset shared fences for debugging + * @obj: the dma_resv object to reset + * + * Reset the number of pre-reserved shared slots to test that drivers do + * correct slot allocation using dma_resv_reserve_fences(). See also + * &dma_resv_list.shared_max. + */ +void dma_resv_reset_max_fences(struct dma_resv *obj) +{ + struct dma_resv_list *fences = dma_resv_shared_list(obj); + + dma_resv_assert_held(obj); + + /* Test shared fence slot reservation */ + if (fences) + fences->shared_max = fences->shared_count; +} +EXPORT_SYMBOL(dma_resv_reset_max_fences); +#endif + +/** + * dma_resv_add_shared_fence - Add a fence to a shared slot + * @obj: the reservation object + * @fence: the shared fence to add + * + * Add a fence to a shared slot, @obj must be locked with dma_resv_lock(), and + * dma_resv_reserve_fences() has been called. + * + * See also &dma_resv.fence for a discussion of the semantics. + */ +static void dma_resv_add_shared_fence(struct dma_resv *obj, + struct dma_fence *fence) +{ + struct dma_resv_list *fobj; + struct dma_fence *old; + unsigned int i, count; + + dma_fence_get(fence); + + dma_resv_assert_held(obj); + + /* Drivers should not add containers here, instead add each fence + * individually. + */ + WARN_ON(dma_fence_is_container(fence)); + + fobj = dma_resv_shared_list(obj); + count = fobj->shared_count; + + write_seqcount_begin(&obj->seq); + + for (i = 0; i < count; ++i) { + + old = rcu_dereference_protected(fobj->shared[i], + dma_resv_held(obj)); + if (old->context == fence->context || + dma_fence_is_signaled(old)) + goto replace; + } + + BUG_ON(fobj->shared_count >= fobj->shared_max); + old = NULL; + count++; + +replace: + RCU_INIT_POINTER(fobj->shared[i], fence); + /* pointer update must be visible before we extend the shared_count */ + smp_store_mb(fobj->shared_count, count); + + write_seqcount_end(&obj->seq); + dma_fence_put(old); +} + +/** + * dma_resv_replace_fences - replace fences in the dma_resv obj + * @obj: the reservation object + * @context: the context of the fences to replace + * @replacement: the new fence to use instead + * @usage: how the new fence is used, see enum dma_resv_usage + * + * Replace fences with a specified context with a new fence. Only valid if the + * operation represented by the original fence has no longer access to the + * resources represented by the dma_resv object when the new fence completes. + * + * And example for using this is replacing a preemption fence with a page table + * update fence which makes the resource inaccessible. + */ +void dma_resv_replace_fences(struct dma_resv *obj, uint64_t context, + struct dma_fence *replacement, + enum dma_resv_usage usage) +{ + struct dma_resv_list *list; + struct dma_fence *old; + unsigned int i; + + /* Only readers supported for now */ + WARN_ON(usage != DMA_RESV_USAGE_READ); + + dma_resv_assert_held(obj); + + write_seqcount_begin(&obj->seq); + + old = dma_resv_excl_fence(obj); + if (old->context == context) { + RCU_INIT_POINTER(obj->fence_excl, dma_fence_get(replacement)); + dma_fence_put(old); + } + + list = dma_resv_shared_list(obj); + for (i = 0; list && i < list->shared_count; ++i) { + old = rcu_dereference_protected(list->shared[i], + dma_resv_held(obj)); + if (old->context != context) + continue; + + rcu_assign_pointer(list->shared[i], dma_fence_get(replacement)); + dma_fence_put(old); + } + + write_seqcount_end(&obj->seq); +} +EXPORT_SYMBOL(dma_resv_replace_fences); + +/** + * dma_resv_add_excl_fence - Add an exclusive fence. + * @obj: the reservation object + * @fence: the exclusive fence to add + * + * Add a fence to the exclusive slot. @obj must be locked with dma_resv_lock(). + * See also &dma_resv.fence_excl for a discussion of the semantics. + */ +static void dma_resv_add_excl_fence(struct dma_resv *obj, + struct dma_fence *fence) +{ + struct dma_fence *old_fence = dma_resv_excl_fence(obj); + + dma_resv_assert_held(obj); + + dma_fence_get(fence); + + write_seqcount_begin(&obj->seq); + /* write_seqcount_begin provides the necessary memory barrier */ + RCU_INIT_POINTER(obj->fence_excl, fence); + write_seqcount_end(&obj->seq); + + dma_fence_put(old_fence); +} + +/** + * dma_resv_add_fence - Add a fence to the dma_resv obj + * @obj: the reservation object + * @fence: the fence to add + * @usage: how the fence is used, see enum dma_resv_usage + * + * Add a fence to a slot, @obj must be locked with dma_resv_lock(), and + * dma_resv_reserve_fences() has been called. + * + * See also &dma_resv.fence for a discussion of the semantics. + */ +void dma_resv_add_fence(struct dma_resv *obj, struct dma_fence *fence, + enum dma_resv_usage usage) +{ + if (usage == DMA_RESV_USAGE_WRITE) + dma_resv_add_excl_fence(obj, fence); + else + dma_resv_add_shared_fence(obj, fence); +} +EXPORT_SYMBOL(dma_resv_add_fence); + +/* Restart the iterator by initializing all the necessary fields, but not the + * relation to the dma_resv object. */ +static void dma_resv_iter_restart_unlocked(struct dma_resv_iter *cursor) +{ + cursor->seq = read_seqcount_begin(&cursor->obj->seq); + cursor->index = -1; + cursor->shared_count = 0; + if (cursor->usage >= DMA_RESV_USAGE_READ) { + cursor->fences = dma_resv_shared_list(cursor->obj); + if (cursor->fences) + cursor->shared_count = cursor->fences->shared_count; + } else { + cursor->fences = NULL; + } + cursor->is_restarted = true; +} + +/* Walk to the next not signaled fence and grab a reference to it */ +static void dma_resv_iter_walk_unlocked(struct dma_resv_iter *cursor) +{ + struct dma_resv *obj = cursor->obj; + + do { + /* Drop the reference from the previous round */ + dma_fence_put(cursor->fence); + + if (cursor->index == -1) { + cursor->fence = dma_resv_excl_fence(obj); + cursor->index++; + if (!cursor->fence) + continue; + + } else if (!cursor->fences || + cursor->index >= cursor->shared_count) { + cursor->fence = NULL; + break; + + } else { + struct dma_resv_list *fences = cursor->fences; + unsigned int idx = cursor->index++; + + cursor->fence = rcu_dereference(fences->shared[idx]); + } + cursor->fence = dma_fence_get_rcu(cursor->fence); + if (!cursor->fence || !dma_fence_is_signaled(cursor->fence)) + break; + } while (true); +} + +/** + * dma_resv_iter_first_unlocked - first fence in an unlocked dma_resv obj. + * @cursor: the cursor with the current position + * + * Subsequent fences are iterated with dma_resv_iter_next_unlocked(). + * + * Beware that the iterator can be restarted. Code which accumulates statistics + * or similar needs to check for this with dma_resv_iter_is_restarted(). For + * this reason prefer the locked dma_resv_iter_first() whenver possible. + * + * Returns the first fence from an unlocked dma_resv obj. + */ +struct dma_fence *dma_resv_iter_first_unlocked(struct dma_resv_iter *cursor) +{ + rcu_read_lock(); + do { + dma_resv_iter_restart_unlocked(cursor); + dma_resv_iter_walk_unlocked(cursor); + } while (read_seqcount_retry(&cursor->obj->seq, cursor->seq)); + rcu_read_unlock(); + + return cursor->fence; +} +EXPORT_SYMBOL(dma_resv_iter_first_unlocked); + +/** + * dma_resv_iter_next_unlocked - next fence in an unlocked dma_resv obj. + * @cursor: the cursor with the current position + * + * Beware that the iterator can be restarted. Code which accumulates statistics + * or similar needs to check for this with dma_resv_iter_is_restarted(). For + * this reason prefer the locked dma_resv_iter_next() whenver possible. + * + * Returns the next fence from an unlocked dma_resv obj. + */ +struct dma_fence *dma_resv_iter_next_unlocked(struct dma_resv_iter *cursor) +{ + bool restart; + + rcu_read_lock(); + cursor->is_restarted = false; + restart = read_seqcount_retry(&cursor->obj->seq, cursor->seq); + do { + if (restart) + dma_resv_iter_restart_unlocked(cursor); + dma_resv_iter_walk_unlocked(cursor); + restart = true; + } while (read_seqcount_retry(&cursor->obj->seq, cursor->seq)); + rcu_read_unlock(); + + return cursor->fence; +} +EXPORT_SYMBOL(dma_resv_iter_next_unlocked); + +/** + * dma_resv_iter_first - first fence from a locked dma_resv object + * @cursor: cursor to record the current position + * + * Subsequent fences are iterated with dma_resv_iter_next_unlocked(). + * + * Return the first fence in the dma_resv object while holding the + * &dma_resv.lock. + */ +struct dma_fence *dma_resv_iter_first(struct dma_resv_iter *cursor) +{ + struct dma_fence *fence; + + dma_resv_assert_held(cursor->obj); + + cursor->index = 0; + if (cursor->usage >= DMA_RESV_USAGE_READ) + cursor->fences = dma_resv_shared_list(cursor->obj); + else + cursor->fences = NULL; + + fence = dma_resv_excl_fence(cursor->obj); + if (!fence) + fence = dma_resv_iter_next(cursor); + + cursor->is_restarted = true; + return fence; +} +EXPORT_SYMBOL_GPL(dma_resv_iter_first); + +/** + * dma_resv_iter_next - next fence from a locked dma_resv object + * @cursor: cursor to record the current position + * + * Return the next fences from the dma_resv object while holding the + * &dma_resv.lock. + */ +struct dma_fence *dma_resv_iter_next(struct dma_resv_iter *cursor) +{ + unsigned int idx; + + dma_resv_assert_held(cursor->obj); + + cursor->is_restarted = false; + if (!cursor->fences || cursor->index >= cursor->fences->shared_count) + return NULL; + + idx = cursor->index++; + return rcu_dereference_protected(cursor->fences->shared[idx], + dma_resv_held(cursor->obj)); +} +EXPORT_SYMBOL_GPL(dma_resv_iter_next); + +/** + * dma_resv_copy_fences - Copy all fences from src to dst. + * @dst: the destination reservation object + * @src: the source reservation object + * + * Copy all fences from src to dst. dst-lock must be held. + */ +int dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src) +{ + struct dma_resv_iter cursor; + struct dma_resv_list *list; + struct dma_fence *f, *excl; + + dma_resv_assert_held(dst); + + list = NULL; + excl = NULL; + + dma_resv_iter_begin(&cursor, src, DMA_RESV_USAGE_READ); + dma_resv_for_each_fence_unlocked(&cursor, f) { + + if (dma_resv_iter_is_restarted(&cursor)) { + dma_resv_list_free(list); + dma_fence_put(excl); + + if (cursor.shared_count) { + list = dma_resv_list_alloc(cursor.shared_count); + if (!list) { + dma_resv_iter_end(&cursor); + return -ENOMEM; + } + + list->shared_count = 0; + + } else { + list = NULL; + } + excl = NULL; + } + + dma_fence_get(f); + if (dma_resv_iter_usage(&cursor) == DMA_RESV_USAGE_WRITE) + excl = f; + else + RCU_INIT_POINTER(list->shared[list->shared_count++], f); + } + dma_resv_iter_end(&cursor); + + write_seqcount_begin(&dst->seq); + excl = rcu_replace_pointer(dst->fence_excl, excl, dma_resv_held(dst)); + list = rcu_replace_pointer(dst->fence, list, dma_resv_held(dst)); + write_seqcount_end(&dst->seq); + + dma_resv_list_free(list); + dma_fence_put(excl); + + return 0; +} +EXPORT_SYMBOL(dma_resv_copy_fences); + +/** + * dma_resv_get_fences - Get an object's shared and exclusive + * fences without update side lock held + * @obj: the reservation object + * @usage: controls which fences to include, see enum dma_resv_usage. + * @num_fences: the number of fences returned + * @fences: the array of fence ptrs returned (array is krealloc'd to the + * required size, and must be freed by caller) + * + * Retrieve all fences from the reservation object. + * Returns either zero or -ENOMEM. + */ +int dma_resv_get_fences(struct dma_resv *obj, enum dma_resv_usage usage, + unsigned int *num_fences, struct dma_fence ***fences) +{ + struct dma_resv_iter cursor; + struct dma_fence *fence; + + *num_fences = 0; + *fences = NULL; + + dma_resv_iter_begin(&cursor, obj, usage); + dma_resv_for_each_fence_unlocked(&cursor, fence) { + + if (dma_resv_iter_is_restarted(&cursor)) { + unsigned int count; + + while (*num_fences) + dma_fence_put((*fences)[--(*num_fences)]); + + count = cursor.shared_count + 1; + + /* Eventually re-allocate the array */ + *fences = krealloc_array(*fences, count, + sizeof(void *), + GFP_KERNEL); + if (count && !*fences) { + dma_resv_iter_end(&cursor); + return -ENOMEM; + } + } + + (*fences)[(*num_fences)++] = dma_fence_get(fence); + } + dma_resv_iter_end(&cursor); + + return 0; +} +EXPORT_SYMBOL_GPL(dma_resv_get_fences); + +/** + * dma_resv_get_singleton - Get a single fence for all the fences + * @obj: the reservation object + * @usage: controls which fences to include, see enum dma_resv_usage. + * @fence: the resulting fence + * + * Get a single fence representing all the fences inside the resv object. + * Returns either 0 for success or -ENOMEM. + * + * Warning: This can't be used like this when adding the fence back to the resv + * object since that can lead to stack corruption when finalizing the + * dma_fence_array. + * + * Returns 0 on success and negative error values on failure. + */ +int dma_resv_get_singleton(struct dma_resv *obj, enum dma_resv_usage usage, + struct dma_fence **fence) +{ + struct dma_fence_array *array; + struct dma_fence **fences; + unsigned count; + int r; + + r = dma_resv_get_fences(obj, usage, &count, &fences); + if (r) + return r; + + if (count == 0) { + *fence = NULL; + return 0; + } + + if (count == 1) { + *fence = fences[0]; + kfree(fences); + return 0; + } + + array = dma_fence_array_create(count, fences, + dma_fence_context_alloc(1), + 1, false); + if (!array) { + while (count--) + dma_fence_put(fences[count]); + kfree(fences); + return -ENOMEM; + } + + *fence = &array->base; + return 0; +} +EXPORT_SYMBOL_GPL(dma_resv_get_singleton); + +/** + * dma_resv_wait_timeout - Wait on reservation's objects + * shared and/or exclusive fences. + * @obj: the reservation object + * @usage: controls which fences to include, see enum dma_resv_usage. + * @intr: if true, do interruptible wait + * @timeout: timeout value in jiffies or zero to return immediately + * + * Callers are not required to hold specific locks, but maybe hold + * dma_resv_lock() already + * RETURNS + * Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or + * greater than zer on success. + */ +long dma_resv_wait_timeout(struct dma_resv *obj, enum dma_resv_usage usage, + bool intr, unsigned long timeout) +{ + long ret = timeout ? timeout : 1; + struct dma_resv_iter cursor; + struct dma_fence *fence; + + dma_resv_iter_begin(&cursor, obj, usage); + dma_resv_for_each_fence_unlocked(&cursor, fence) { + + ret = dma_fence_wait_timeout(fence, intr, ret); + if (ret <= 0) { + dma_resv_iter_end(&cursor); + return ret; + } + } + dma_resv_iter_end(&cursor); + + return ret; +} +EXPORT_SYMBOL_GPL(dma_resv_wait_timeout); + +/** + * dma_resv_test_signaled - Test if a reservation object's fences have been + * signaled. + * @obj: the reservation object + * @usage: controls which fences to include, see enum dma_resv_usage. + * + * Callers are not required to hold specific locks, but maybe hold + * dma_resv_lock() already. + * + * RETURNS + * + * True if all fences signaled, else false. + */ +bool dma_resv_test_signaled(struct dma_resv *obj, enum dma_resv_usage usage) +{ + struct dma_resv_iter cursor; + struct dma_fence *fence; + + dma_resv_iter_begin(&cursor, obj, usage); + dma_resv_for_each_fence_unlocked(&cursor, fence) { + dma_resv_iter_end(&cursor); + return false; + } + dma_resv_iter_end(&cursor); + return true; +} +EXPORT_SYMBOL_GPL(dma_resv_test_signaled); + +/** + * dma_resv_describe - Dump description of the resv object into seq_file + * @obj: the reservation object + * @seq: the seq_file to dump the description into + * + * Dump a textual description of the fences inside an dma_resv object into the + * seq_file. + */ +void dma_resv_describe(struct dma_resv *obj, struct seq_file *seq) +{ + static const char *usage[] = { "write", "read" }; + struct dma_resv_iter cursor; + struct dma_fence *fence; + + dma_resv_for_each_fence(&cursor, obj, DMA_RESV_USAGE_READ, fence) { + seq_printf(seq, "\t%s fence:", + usage[dma_resv_iter_usage(&cursor)]); + dma_fence_describe(fence, seq); + } +} +EXPORT_SYMBOL_GPL(dma_resv_describe); + +#if IS_ENABLED(CONFIG_LOCKDEP) +static int __init dma_resv_lockdep(void) +{ + struct mm_struct *mm = mm_alloc(); + struct ww_acquire_ctx ctx; + struct dma_resv obj; + struct address_space mapping; + int ret; + + if (!mm) + return -ENOMEM; + + dma_resv_init(&obj); + address_space_init_once(&mapping); + + mmap_read_lock(mm); + ww_acquire_init(&ctx, &reservation_ww_class); + ret = dma_resv_lock(&obj, &ctx); + if (ret == -EDEADLK) + dma_resv_lock_slow(&obj, &ctx); + fs_reclaim_acquire(GFP_KERNEL); + /* for unmap_mapping_range on trylocked buffer objects in shrinkers */ + i_mmap_lock_write(&mapping); + i_mmap_unlock_write(&mapping); +#ifdef CONFIG_MMU_NOTIFIER + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); + __dma_fence_might_wait(); + lock_map_release(&__mmu_notifier_invalidate_range_start_map); +#else + __dma_fence_might_wait(); +#endif + fs_reclaim_release(GFP_KERNEL); + ww_mutex_unlock(&obj.lock); + ww_acquire_fini(&ctx); + mmap_read_unlock(mm); + + mmput(mm); + + return 0; +} +subsys_initcall(dma_resv_lockdep); +#endif + + + + +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3432ffad2b246..11c8c58681418 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -115,11 +115,14 @@ /* dma_map_sgtable() is enabled */ #define HAVE_DMA_MAP_SGTABLE 1 +/* dma_resv->fences is available */ +#define HAVE_DMA_RESV_FENCES 1 + /* dma_resv->seq is available */ -#define HAVE_DMA_RESV_SEQ 1 +/* #undef HAVE_DMA_RESV_SEQ */ /* dma_resv->seq is seqcount_ww_mutex_t */ -#define HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T 1 +/* #undef HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T */ /* down_read_killable() is available */ #define HAVE_DOWN_READ_KILLABLE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index 1ede56611c58d..9d11fb99c397a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -41,6 +41,25 @@ AC_DEFUN([AC_AMDGPU_DMA_RESV_SEQ], [ ]) ]) +dnl # +dnl # v5.18-rc1-237-g047a1b877ed4 +dnl # dma-buf & drm/amdgpu: remove dma_resv workaround +dnl # +AC_DEFUN([AC_AMDGPU_DMA_RESV_FENCES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_resv *resv = NULL; + resv->fences = NULL; + ], [ + AC_DEFINE(HAVE_DMA_RESV_FENCES, 1, + [dma_resv->fences is available]) + ]) + ]) +]) + + dnl # dnl # v4.19-rc6-1514-g27836b641c1b dnl # dma-buf: remove shared fence staging in reservation object @@ -63,5 +82,6 @@ AC_DEFUN([AC_AMDGPU_RESERVATION_OBJECT_STAGED], [ AC_DEFUN([AC_AMDGPU_DMA_RESV], [ AC_AMDGPU_DMA_RESV_SEQ + AC_AMDGPU_DMA_RESV_FENCES AC_AMDGPU_RESERVATION_OBJECT_STAGED ]) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 7d481851f944d..81a0d5da5c8bd 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -41,7 +41,9 @@ done sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ -e '/dma_resv_lockdep/,/subsys_initcall/d' $KCL/dma-buf/dma-resv.c sed -i -e '/extern struct ww_class reservation_ww_class/i #include ' \ - -e '/struct dma_resv {/, /}/d' $INC/linux/dma-resv.h + -e '/struct dma_resv {/, /}/d' $INC/linux/dma-resv.h \ + -e '/struct dma_resv_iter {/, /}/d' $INC/linux/dma-resv.h \ + -e '/enum dma_resv_usage {/, /}/d' $INC/linux/dma-resv.h # add amd prefix to exported symbols for file in $FILES; do @@ -71,3 +73,7 @@ if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then sed -i 's|$(AMDDALPATH)/.*/\(.*\.o\)|\1|' $file done fi + +if ! grep -q 'define HAVE_DMA_RESV_FENCES' $SRC/config/config.h; then + sed -i 's|dma-buf/dma-resv.o|kcl_dma-resv.o|' amd/amdkcl/Makefile +fi diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 0c4850cd6bf95..39a4e3b5e67f1 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -54,6 +54,125 @@ struct dma_resv_list; +enum dma_resv_usage { + /** + * @DMA_RESV_USAGE_KERNEL: For in kernel memory management only. + * + * This should only be used for things like copying or clearing memory + * with a DMA hardware engine for the purpose of kernel memory + * management. + * + * Drivers *always* must wait for those fences before accessing the + * resource protected by the dma_resv object. The only exception for + * that is when the resource is known to be locked down in place by + * pinning it previously. + */ + DMA_RESV_USAGE_KERNEL, + + /** + * @DMA_RESV_USAGE_WRITE: Implicit write synchronization. + * + * This should only be used for userspace command submissions which add + * an implicit write dependency. + */ + DMA_RESV_USAGE_WRITE, + + /** + * @DMA_RESV_USAGE_READ: Implicit read synchronization. + * + * This should only be used for userspace command submissions which add + * an implicit read dependency. + */ + DMA_RESV_USAGE_READ, + + /** + * @DMA_RESV_USAGE_BOOKKEEP: No implicit sync. + * + * This should be used by submissions which don't want to participate in + * implicit synchronization. + * + * The most common case are preemption fences as well as page table + * updates and their TLB flushes. + */ + DMA_RESV_USAGE_BOOKKEEP +}; + +#if defined(HAVE_DMA_RESV_FENCES) +struct dma_resv { + struct ww_mutex lock; + struct dma_resv_list __rcu *fences; +}; + +struct dma_resv_iter { + /** @obj: The dma_resv object we iterate over */ + struct dma_resv *obj; + + /** @usage: Return fences with this usage or lower. */ + enum dma_resv_usage usage; + + /** @fence: the currently handled fence */ + struct dma_fence *fence; + + /** @fence_usage: the usage of the current fence */ + enum dma_resv_usage fence_usage; + + /** @index: index into the shared fences */ + unsigned int index; + + /** @fences: the shared fences; private, *MUST* not dereference */ + struct dma_resv_list *fences; + + /** @num_fences: number of fences */ + unsigned int num_fences; + + /** @is_restarted: true if this is the first returned fence */ + bool is_restarted; +}; + +#else + +/** + * struct dma_resv_list - a list of shared fences + * @rcu: for internal use + * @shared_count: table of shared fences + * @shared_max: for growing shared fence table + * @shared: shared fence table + */ +struct dma_resv_list { + struct rcu_head rcu; + u32 shared_count, shared_max; + struct dma_fence __rcu *shared[]; +}; + +struct dma_resv_iter { + /** @obj: The dma_resv object we iterate over */ + struct dma_resv *obj; + + /** @usage: Return fences with this usage or lower. */ + enum dma_resv_usage usage; + + /** @fence: the currently handled fence */ + struct dma_fence *fence; + + /** @fence_usage: the usage of the current fence */ + enum dma_resv_usage fence_usage; + + /** @seq: sequence number to check for modifications */ + unsigned int seq; + + /** @index: index into the shared fences */ + unsigned int index; + + /** @fences: the shared fences; private, *MUST* not dereference */ + struct dma_resv_list *fences; + + /** @shared_count: number of shared fences */ + unsigned int shared_count; + + /** @is_restarted: true if this is the first returned fence */ + bool is_restarted; +}; + #if defined(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T) struct dma_resv { struct ww_mutex lock; @@ -81,6 +200,38 @@ struct dma_resv { }; #endif +/** + * dma_resv_excl_fence - return the object's exclusive fence + * @obj: the reservation object + * + * Returns the exclusive fence (if any). Caller must either hold the objects + * through dma_resv_lock() or the RCU read side lock through rcu_read_lock(), + * or one of the variants of each + * + * RETURNS + * The exclusive fence or NULL + */ +static inline struct dma_fence * +dma_resv_excl_fence(struct dma_resv *obj) +{ + return rcu_dereference_check(obj->fence_excl, lockdep_is_held(&(obj)->lock.base)); +} + +/** + * dma_resv_shared_list - get the reservation object's shared fence list + * @obj: the reservation object + * + * Returns the shared fence list. Caller must either hold the objects + * through dma_resv_lock() or the RCU read side lock through rcu_read_lock(), + * or one of the variants of each + */ +static inline struct dma_resv_list *dma_resv_shared_list(struct dma_resv *obj) +{ + return rcu_dereference_check(obj->fence, lockdep_is_held(&(obj)->lock.base)); +} + +#endif /* !defined(HAVE_DMA_RESV_FENCES) */ + #if !defined(smp_store_mb) #define smp_store_mb set_mb #endif From 6e9f4285fc5fb4ee9d081461d029c2a30c1b2ba4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 10:30:52 +0800 Subject: [PATCH 0776/2653] drm/amdkcl: replace dma_resv_add_excl_fence with dma_resv_add_fence Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 4baa8ccd74e2f..e86813cf37651 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -103,14 +103,14 @@ __dma_resv_make_exclusive(struct dma_resv *obj) if (!dma_resv_shared_list(obj)) /* no shared fences to convert */ return 0; - r = dma_resv_get_fences(obj, NULL, &count, &fences); + r = dma_resv_get_fences(obj, DMA_RESV_USAGE_READ, &count, &fences); if (r) return r; if (count == 0) { /* Now that was unexpected. */ } else if (count == 1) { - dma_resv_add_excl_fence(obj, fences[0]); + dma_resv_add_fence(obj, fences[0], DMA_RESV_USAGE_WRITE); dma_fence_put(fences[0]); kfree(fences); } else { @@ -122,7 +122,7 @@ __dma_resv_make_exclusive(struct dma_resv *obj) if (!array) goto err_fences_put; - dma_resv_add_excl_fence(obj, &array->base); + dma_resv_add_fence(obj, &array->base, DMA_RESV_USAGE_WRITE); dma_fence_put(&array->base); } From 2d84abd43e6aea1a763a9cbe3dec702ebabe0b53 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 12:58:52 +0800 Subject: [PATCH 0777/2653] drm/amdkcl: use DMA_RESV_USAGE_KERNEL as DMA_REV_USAGE_WRITE for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index e3525a0973f71..5cd7528f0c2a7 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -380,7 +380,7 @@ static void dma_resv_add_excl_fence(struct dma_resv *obj, void dma_resv_add_fence(struct dma_resv *obj, struct dma_fence *fence, enum dma_resv_usage usage) { - if (usage == DMA_RESV_USAGE_WRITE) + if (usage == DMA_RESV_USAGE_WRITE || usage == DMA_RESV_USAGE_KERNEL) dma_resv_add_excl_fence(obj, fence); else dma_resv_add_shared_fence(obj, fence); From 12b481789883a3aa520c695a0c75a37b59e4d1cc Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 13:00:56 +0800 Subject: [PATCH 0778/2653] drm/amdkcl: fix NULL pointer check Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index 5cd7528f0c2a7..db40a6e5f035a 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -321,7 +321,7 @@ void dma_resv_replace_fences(struct dma_resv *obj, uint64_t context, write_seqcount_begin(&obj->seq); old = dma_resv_excl_fence(obj); - if (old->context == context) { + if (old && old->context == context) { RCU_INIT_POINTER(obj->fence_excl, dma_fence_get(replacement)); dma_fence_put(old); } From 89a06c03866fede890c8aec6e426638166a5e937 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 15:50:43 +0800 Subject: [PATCH 0779/2653] drm/amdkcl: replace arg with DMA_RESV_USAGE_WRITE Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index cd5edab6b135e..7c506441f74f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -455,7 +455,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc, goto unreserve; } - r = dma_resv_get_fences(amdkcl_ttm_resvp(&new_abo->tbo), NULL, + r = dma_resv_get_fences(amdkcl_ttm_resvp(&new_abo->tbo), DMA_RESV_USAGE_WRITE, &work->shared_count, &work->shared); if (unlikely(r != 0)) { From 0c2457e2e81e5f9292fb2cdd544dfb80ec94a7cf Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 22:33:58 +0800 Subject: [PATCH 0780/2653] drm/amdkcl: remove useless header Signed-off-by: Leslie Shi Signed-off-by: Ma Jun Change-Id: Ic20beeebc180c41f7b6f0a7510c3f03aa4370985 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b75a3aa0848a5..2b0043316836e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -95,9 +95,6 @@ #include #include #include -#ifdef CONFIG_DRM_AMD_DC_HDCP -#include -#endif #include #include From f596bacdc92e554fa71cff80925e7ca34ad86a60 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 25 Jul 2022 10:21:47 +0800 Subject: [PATCH 0781/2653] drm/amdkcl: drop DRM_AMD_DC_DCN{1_0/2_x/3_x} Signed-off-by: Leslie Shi Change-Id: I6e3f9d20a8573901fabcc13538abc988936d803e Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/dkms/Makefile | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index e7b791c8195f0..1fc960e3cae03 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -149,9 +149,6 @@ export CONFIG_DRM_AMDGPU_CIK=y export CONFIG_DRM_AMDGPU_SI=y export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y -ifndef CONFIG_ARM64 -export CONFIG_DRM_AMD_DC_DCN1_0=y -endif subdir-ccflags-y += -DCONFIG_HSA_AMD subdir-ccflags-y += -DCONFIG_DRM_TTM_DMA_PAGE_POOL @@ -159,9 +156,6 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC -ifndef CONFIG_ARM64 -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 -endif ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) ifdef CONFIG_DEVICE_PRIVATE @@ -179,10 +173,8 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP # if core2 isn't in the compiler flags ifndef CONFIG_ARM64 ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) -export CONFIG_DRM_AMD_DC_DCN2_x=y -export CONFIG_DRM_AMD_DC_DCN3_x=y -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN2_x -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN3_x +export CONFIG_DRM_AMD_DC_DCN=y +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN endif endif From 31ce1a4e49ec85e9fed34f7da52f216d7d189763 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 27 Jul 2022 18:56:58 +0800 Subject: [PATCH 0782/2653] drm/amdkcl: Test if drm_private_obj is defined Test if drm_private_obj is defined in struct drm_dp_mst_topology_mrg Signed-off-by: Ma Jun Reviewed-by: Leslie Shi Change-Id: I9daeac36f316b5183cd732aa13a7283be43ea097 --- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 +++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm_dp_mst_topology_mgr.m4 | 26 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 36 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index a794496df7b08..c8846afc46042 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -2772,6 +2772,7 @@ static int target_backlight_show(struct seq_file *m, void *unused) * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector * */ +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE static int dp_is_mst_connector_show(struct seq_file *m, void *unused) { struct drm_connector *connector = m->private; @@ -2808,6 +2809,7 @@ static int dp_is_mst_connector_show(struct seq_file *m, void *unused) return 0; } +#endif /* * function description: Read out the mst progress status @@ -2936,7 +2938,9 @@ DEFINE_SHOW_ATTRIBUTE(internal_display); DEFINE_SHOW_ATTRIBUTE(odm_combine_segments); DEFINE_SHOW_ATTRIBUTE(replay_capability); DEFINE_SHOW_ATTRIBUTE(psr_capability); +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector); +#endif DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); DEFINE_SHOW_ATTRIBUTE(is_dpia_link); DEFINE_SHOW_STORE_ATTRIBUTE(hdmi_cec_state); @@ -3071,7 +3075,9 @@ static const struct { {"max_bpc", &dp_max_bpc_debugfs_fops}, {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE {"is_mst_connector", &dp_is_mst_connector_fops}, +#endif {"mst_progress_status", &dp_mst_progress_status_fops}, {"is_dpia_link", &is_dpia_link_fops}, {"mst_link_settings", &dp_mst_link_settings_debugfs_fops} diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 11c8c58681418..c3e1e5c202995 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -405,6 +405,9 @@ /* struct drm_dp_mst_topology_cbs->register_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR */ +/* struct drm_dp_mst_topology_mgr.base is available */ +#define HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE 1 + /* drm_dp_mst_topology_mgr_init() wants drm_device arg */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_DRM_DEV 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 new file mode 100644 index 0000000000000..06cdbe40de8cf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 @@ -0,0 +1,26 @@ +dnl # +dnl # commit v4.14-rc1-a4370c7774 +dnl # drm/atomic: Make private objs proper objects +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + #include + ], [ + struct drm_dp_mst_topology_mgr *mst_mgr = 0; + int i = 0; + if ((&mst_mgr->base) && (&mst_mgr->base.lock)) + i++; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE, 1, + [struct drm_dp_mst_topology_mgr.base is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7b3a26efd9324..03952ad6e65b6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -207,6 +207,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STR_YES_NO AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 45fac31ab9a6ee66b79262d50af0d9872b653b19 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 29 Jul 2022 13:54:21 +0800 Subject: [PATCH 0783/2653] drm/amdkcl: refactor kcl implementation for drm/display header change Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- include/kcl/backport/kcl_drm_dp_mst_helper_backport.h | 6 ------ include/kcl/header/drm/display/drm_dp_helper.h | 4 ++-- include/kcl/header/drm/display/drm_dp_mst_helper.h | 4 ++-- include/kcl/header/drm/dp/drm_dp_helper.h | 9 --------- include/kcl/header/drm/dp/drm_dp_mst_helper.h | 9 --------- include/kcl/kcl_drm_dp_cec.h | 6 ------ include/kcl/kcl_drm_dp_helper.h | 6 ------ 7 files changed, 4 insertions(+), 40 deletions(-) delete mode 100644 include/kcl/header/drm/dp/drm_dp_helper.h delete mode 100644 include/kcl/header/drm/dp/drm_dp_mst_helper.h diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 5623abd34416b..9be8ef18696a1 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -22,13 +22,7 @@ #ifndef _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ #define _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ -#if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) #include -#elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) -#include -#else -#include -#endif /* Copied from drivers/gpu/drm/drm_dp_mst_topology.c and modified for KCL */ #if !defined(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS) diff --git a/include/kcl/header/drm/display/drm_dp_helper.h b/include/kcl/header/drm/display/drm_dp_helper.h index 83269a83e90ba..3435bd45d5669 100644 --- a/include/kcl/header/drm/display/drm_dp_helper.h +++ b/include/kcl/header/drm/display/drm_dp_helper.h @@ -5,9 +5,9 @@ #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) #include_next #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) -#include_next +#include #else -#include_next +#include #endif #endif diff --git a/include/kcl/header/drm/display/drm_dp_mst_helper.h b/include/kcl/header/drm/display/drm_dp_mst_helper.h index 35221a4f00645..c667873640a00 100644 --- a/include/kcl/header/drm/display/drm_dp_mst_helper.h +++ b/include/kcl/header/drm/display/drm_dp_mst_helper.h @@ -5,9 +5,9 @@ #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) #include_next #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) -#include_next +#include #else -#include_next +#include #endif #endif diff --git a/include/kcl/header/drm/dp/drm_dp_helper.h b/include/kcl/header/drm/dp/drm_dp_helper.h deleted file mode 100644 index 9aac78ed61294..0000000000000 --- a/include/kcl/header/drm/dp/drm_dp_helper.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER_DP_DRM_DP_HELPER_H_H_ -#define _KCL_HEADER_DP_DRM_DP_HELPER_H_H_ - -#ifdef HAVE_DRM_DP_DRM_DP_HELPER_H -#include_next -#endif - -#endif diff --git a/include/kcl/header/drm/dp/drm_dp_mst_helper.h b/include/kcl/header/drm/dp/drm_dp_mst_helper.h deleted file mode 100644 index 116be51b87c2c..0000000000000 --- a/include/kcl/header/drm/dp/drm_dp_mst_helper.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER_DP_DRM_DP_MST_HELPER_H_H_ -#define _KCL_HEADER_DP_DRM_DP_MST_HELPER_H_H_ - -#ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H -#include_next -#endif - -#endif diff --git a/include/kcl/kcl_drm_dp_cec.h b/include/kcl/kcl_drm_dp_cec.h index e76e90cc0fe59..58549a2e15bf1 100644 --- a/include/kcl/kcl_drm_dp_cec.h +++ b/include/kcl/kcl_drm_dp_cec.h @@ -8,13 +8,7 @@ #ifndef __KCL_KCL_DRM_DP_CEC_H__ #define __KCL_KCL_DRM_DP_CEC_H__ -#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) #include -#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) -#include -#else -#include -#endif /* * commit v4.19-rc1-100-g5ce70c799ac2 diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 2d6d15d2bedb8..43ddfa2ed899d 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -30,13 +30,7 @@ #include #include -#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) #include -#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) -#include -#else -#include -#endif #include /* From 5f59475e485bb28f2943d8672b30b859ed2d09e6 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 3 Aug 2022 10:29:12 +0800 Subject: [PATCH 0784/2653] drm/amdkcl: enable CONFIG_HSA_AMD_P2P Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 1fc960e3cae03..a00c632cc588f 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -167,6 +167,11 @@ endif export CONFIG_DRM_AMD_DC_HDCP=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP +ifeq ($(call _is_kcl_macro_defined,HAVE_LINUX_PCI_P2PDMA_H),y) +export CONFIG_HSA_AMD_P2P=y +subdir-ccflags-y += -DCONFIG_HSA_AMD_P2P +endif + # Trying to enable DCN2/3 with core2 optimizations will result in # older versions of GCC hanging during building/installing. Check # if the compiler is using core2 optimizations and only build DCN2/3 From 02ea26b47f02f557451a3dbee2fe76a8daff22b6 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 13 Jul 2022 09:54:49 -0400 Subject: [PATCH 0785/2653] drm/amdkcl: test for available memory Do not kick off new background compiling processes if amount of available system memory less than 20%. It prevents from killing the driver installation on the systems with small amount of memory. SWDEV-336154 Change-Id: Idaf71093526ce2a4a734c5c168a239c927d543b3 Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Reviewed-by: Slava Abramov --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 03952ad6e65b6..58fb6d56bfb77 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -594,6 +594,22 @@ AC_DEFUN([AC_KERNEL_CHECK_HEADERS], [ AC_CHECK_HEADERS([$1],[AS_TR_CPP([HAVE_$1])=1],,[-]) ]) +dnl # +dnl # AC_KERNEL_FREE_MEM +dnl # return true if available memory >20% +dnl # +AC_DEFUN([AC_KERNEL_FREE_MEM], [ + free_mem=$(free -t | awk '/^Total:/ { + printf("%d\n", $[4] / $[2] * 100) + }') + + AS_IF([[[ $free_mem -gt 20 ]]], [ + $1 + ], [ + $2 + ]) +]) + dnl # dnl # AC_KERNEL_DO_BACKGROUND dnl # $1: contents to be executed @@ -602,6 +618,17 @@ AC_DEFUN([AC_KERNEL_DO_BACKGROUND], [ do_background() { AC_KERNEL_TMP_BUILD_DIR([$1]) } + + while : + do + AC_KERNEL_FREE_MEM([rc=0], [rc=1]) + if test $rc -ne 0; then : + sleep 1 + else : + break + fi + done + do_background & procs="$! $procs" ]) From 9ee57d9f5b5364bff403cd5c125646fb50dfa33c Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 10 Aug 2022 11:40:18 +0800 Subject: [PATCH 0786/2653] Revert "drm/amdkcl: fix build error" This reverts commit b57ae4cfbeb096d6f01809599c6194b79c4620a5. --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 10 ++-- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 50 ++++++------------- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +- 4 files changed, 23 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 1d74969ef2afe..fd2bf0257f499 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -176,7 +176,7 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle); bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev); -int amdgpu_amdkfd_copy_mem_to_mem(struct amdgpu_device *adev, struct kgd_mem *src_mem, +int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, uint64_t src_offset, struct kgd_mem *dst_mem, uint64_t dest_offset, uint64_t size, struct dma_fence **f, uint64_t *actual_size); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 9458f728e9cc7..4d9accc938a65 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -3525,11 +3525,12 @@ int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem) return 0; } -int amdgpu_amdkfd_copy_mem_to_mem(struct amdgpu_device *adev, struct kgd_mem *src_mem, +int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, uint64_t src_offset, struct kgd_mem *dst_mem, uint64_t dst_offset, uint64_t size, struct dma_fence **f, uint64_t *actual_size) { + struct amdgpu_device *adev = NULL; struct amdgpu_copy_mem src, dst; struct ww_acquire_ctx ticket; struct list_head list, duplicates; @@ -3537,18 +3538,19 @@ int amdgpu_amdkfd_copy_mem_to_mem(struct amdgpu_device *adev, struct kgd_mem *sr struct dma_fence *fence = NULL; int i, r; - if (!adev|| !src_mem || !dst_mem || !actual_size) + if (!kgd || !src_mem || !dst_mem || !actual_size) return -EINVAL; *actual_size = 0; + adev = get_amdgpu_device(kgd); INIT_LIST_HEAD(&list); INIT_LIST_HEAD(&duplicates); src.bo = &src_mem->bo->tbo; dst.bo = &dst_mem->bo->tbo; - src.mem = src.bo->resource; - dst.mem = dst.bo->resource; + src.mem = &src.bo->mem; + dst.mem = &dst.bo->mem; src.offset = src_offset; dst.offset = dst_offset; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 04273eb7603c5..a4538aacf7aab 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1763,7 +1763,7 @@ static int kfd_create_sg_table_from_userptr_bo(struct kfd_bo *bo, flags = FOLL_WRITE; locked = 1; mmap_read_lock(mm); - n = kcl_get_user_pages_remote(task, mm, pa, nents, flags, process_pages, + n = get_user_pages_remote(mm, pa, nents, flags, process_pages, NULL, &locked); if (locked) mmap_read_unlock(mm); @@ -1808,13 +1808,11 @@ static void kfd_free_cma_bos(struct cma_iter *ci) list_for_each_entry_safe(cma_bo, tmp, &ci->cma_list, list) { struct kfd_dev *dev = cma_bo->dev; - struct kfd_process_device *pdd; /* sg table is deleted by free_memory_of_gpu */ if (cma_bo->sg) kfd_put_sg_table(cma_bo->sg); - pdd = kfd_get_process_device_data(dev, ci->p); - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, cma_bo->mem, pdd->drm_priv, NULL); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, cma_bo->mem, NULL); list_del(&cma_bo->list); kfree(cma_bo); } @@ -1910,10 +1908,9 @@ static int kfd_create_cma_system_bo(struct kfd_dev *kdev, struct kfd_bo *bo, goto pdd_fail; } - ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, 0ULL, bo_size, + ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, bo_size, pdd->drm_priv, cbo->sg, - &cbo->mem, NULL, flags, - false); + &cbo->mem, NULL, flags); mutex_unlock(&p->mutex); if (ret) { pr_err("Failed to create shadow system BO %d\n", ret); @@ -1921,7 +1918,7 @@ static int kfd_create_cma_system_bo(struct kfd_dev *kdev, struct kfd_bo *bo, } if (bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { - ret = amdgpu_amdkfd_copy_mem_to_mem(kdev->adev, bo->mem, + ret = amdgpu_amdkfd_copy_mem_to_mem(kdev->kgd, bo->mem, offset, cbo->mem, 0, bo_size, &f, size); if (ret) { @@ -1946,7 +1943,7 @@ static int kfd_create_cma_system_bo(struct kfd_dev *kdev, struct kfd_bo *bo, return ret; copy_fail: - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(kdev->adev, bo->mem, pdd->drm_priv, NULL); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(kdev->kgd, bo->mem, NULL); pdd_fail: if (cbo->sg) { kfd_put_sg_table(cbo->sg); @@ -2103,7 +2100,7 @@ static int kfd_copy_userptr_bos(struct cma_iter *si, struct cma_iter *di, nl = min_t(unsigned int, MAX_PP_KMALLOC_COUNT, nents); locked = 1; mmap_read_lock(ri->mm); - nl = kcl_get_user_pages_remote(ri->task, ri->mm, rva, nl, + nl = get_user_pages_remote(ri->mm, rva, nl, flags, process_pages, NULL, &locked); if (locked) @@ -2180,9 +2177,9 @@ static int kfd_create_kgd_mem(struct kfd_dev *kdev, uint64_t size, return -EINVAL; } - ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, 0ULL, size, + ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, size, pdd->drm_priv, NULL, - mem, NULL, flags, false); + mem, NULL, flags); mutex_unlock(&p->mutex); if (ret) { pr_err("Failed to create shadow system BO %d\n", ret); @@ -2194,28 +2191,11 @@ static int kfd_create_kgd_mem(struct kfd_dev *kdev, uint64_t size, static int kfd_destroy_kgd_mem(struct kgd_mem *mem) { - struct amdgpu_device *adev; - struct task_struct *task; - struct kfd_process *p; - struct kfd_process_device *pdd; - uint32_t gpu_id, gpu_idx; - int r; - if (!mem) return -EINVAL; - adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); - task = get_pid_task(mem->process_info->pid, PIDTYPE_PID); - p = kfd_get_process(task); - r = kfd_process_gpuid_from_adev(p, adev, &gpu_id, &gpu_idx); - if (r < 0) { - pr_warn("no gpu id found, mem maybe leaking\n"); - return -EINVAL; - } - pdd = kfd_process_device_from_gpuidx(p, gpu_idx); - /* param adev is not used*/ - return amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, mem, pdd->drm_priv, NULL); + return amdgpu_amdkfd_gpuvm_free_memory_of_gpu(NULL, mem, NULL); } /* Copies @size bytes from si->cur_bo to di->cur_bo starting at their @@ -2272,7 +2252,7 @@ static int kfd_copy_bos(struct cma_iter *si, struct cma_iter *di, dst_mem = di->cma_bo->mem; dst_offset = di->bo_offset & (PAGE_SIZE - 1); list_add_tail(&di->cma_bo->list, &di->cma_list); - } else if (src_bo->dev->adev != dst_bo->dev->adev) { + } else if (src_bo->dev->kgd != dst_bo->dev->kgd) { /* This indicates that atleast on of the BO is in local mem. * If both are in local mem of different devices then create an * intermediate System BO and do a double copy @@ -2293,7 +2273,7 @@ static int kfd_copy_bos(struct cma_iter *si, struct cma_iter *di, return -EINVAL; } - if (amdgpu_amdkfd_copy_mem_to_mem(src_bo->dev->adev, + if (amdgpu_amdkfd_copy_mem_to_mem(src_bo->dev->kgd, src_bo->mem, si->bo_offset, *tmp_mem, 0, size, f, &size)) @@ -2315,7 +2295,7 @@ static int kfd_copy_bos(struct cma_iter *si, struct cma_iter *di, return -EINVAL; } - err = amdgpu_amdkfd_copy_mem_to_mem(dev->adev, src_mem, src_offset, + err = amdgpu_amdkfd_copy_mem_to_mem(dev->kgd, src_mem, src_offset, dst_mem, dst_offset, size, f, copied); /* The tmp_bo allocates additional memory. So it is better to wait and @@ -3284,7 +3264,7 @@ static int criu_restore_memory_of_gpu_ipc(struct kfd_process_device *pdd, */ ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(dev->adev, bo_bucket->addr, bo_bucket->size, pdd->drm_priv, - NULL, kgd_mem, &offset, + kgd_mem, &offset, bo_bucket->alloc_flags, true); if (ret) { pr_err("Could not create the BO\n"); @@ -3378,7 +3358,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, } /* Create the BO */ ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(pdd->dev->adev, bo_bucket->addr, - bo_bucket->size, pdd->drm_priv, NULL, kgd_mem, + bo_bucket->size, pdd->drm_priv, kgd_mem, &offset, bo_bucket->alloc_flags, criu_resume); if (ret) { pr_err("Could not create the BO\n"); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index ad0b2abfe7e18..cff1cb83a10c7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -744,7 +744,7 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, int err; err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, gpu_va, size, - pdd->drm_priv, NULL, mem, NULL, + pdd->drm_priv, NULL, &mem, NULL, flags, false); if (err) goto err_alloc_mem; From d3b662acbdc53df59a7f04ee9db46c023335dadd Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 10 Aug 2022 11:47:47 +0800 Subject: [PATCH 0787/2653] Revert "drm/amdkfd: Add CMA API" This reverts commit 4397c7e24bdd5a65ab131266c1acbe6078235e74. CMA is not supported anymore. So revert this patch Signed-off-by: Ma Jun Change-Id: I341df8470a1666cdd37e1c167dad139aafb4dc08 --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 7 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 86 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 842 +----------------- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 32 - drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +- include/uapi/linux/kfd_ioctl.h | 35 - 6 files changed, 5 insertions(+), 999 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index fd2bf0257f499..bbeac961f7381 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -176,11 +176,6 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle); bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev); -int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, - uint64_t src_offset, struct kgd_mem *dst_mem, - uint64_t dest_offset, uint64_t size, struct dma_fence **f, - uint64_t *actual_size); - bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev, @@ -315,7 +310,7 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, uint8_t xcp_id); int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( struct amdgpu_device *adev, uint64_t va, uint64_t size, - void *drm_priv, struct sg_table *sg, struct kgd_mem **mem, + void *drm_priv, struct kgd_mem **mem, uint64_t *offset, uint32_t flags, bool criu_resume); int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 4d9accc938a65..98390bf602b18 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1739,12 +1739,13 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( struct amdgpu_device *adev, uint64_t va, uint64_t size, - void *drm_priv, struct sg_table *sg, struct kgd_mem **mem, + void *drm_priv, struct kgd_mem **mem, uint64_t *offset, uint32_t flags, bool criu_resume) { struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm); enum ttm_bo_type bo_type = ttm_bo_type_device; + struct sg_table *sg = NULL; uint64_t user_addr = 0; struct amdgpu_bo *bo; struct drm_gem_object *gobj = NULL; @@ -1807,10 +1808,6 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED) alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED; - if (sg) { - alloc_domain = AMDGPU_GEM_DOMAIN_CPU; - bo_type = ttm_bo_type_sg; - } *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL); if (!*mem) { ret = -ENOMEM; @@ -3525,85 +3522,6 @@ int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem) return 0; } -int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, - uint64_t src_offset, struct kgd_mem *dst_mem, - uint64_t dst_offset, uint64_t size, - struct dma_fence **f, uint64_t *actual_size) -{ - struct amdgpu_device *adev = NULL; - struct amdgpu_copy_mem src, dst; - struct ww_acquire_ctx ticket; - struct list_head list, duplicates; - struct ttm_validate_buffer resv_list[2]; - struct dma_fence *fence = NULL; - int i, r; - - if (!kgd || !src_mem || !dst_mem || !actual_size) - return -EINVAL; - - *actual_size = 0; - - adev = get_amdgpu_device(kgd); - INIT_LIST_HEAD(&list); - INIT_LIST_HEAD(&duplicates); - - src.bo = &src_mem->bo->tbo; - dst.bo = &dst_mem->bo->tbo; - src.mem = &src.bo->mem; - dst.mem = &dst.bo->mem; - src.offset = src_offset; - dst.offset = dst_offset; - - resv_list[0].bo = src.bo; - resv_list[1].bo = dst.bo; - - for (i = 0; i < 2; i++) { - resv_list[i].num_shared = 1; - list_add_tail(&resv_list[i].head, &list); - } - - r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); - if (r) { - pr_err("Copy buffer failed. Unable to reserve bo (%d)\n", r); - return r; - } - - /* The process to which the Source and Dest BOs belong to could be - * evicted and the BOs invalidated. So validate BOs before use - */ - r = amdgpu_amdkfd_bo_validate(src_mem->bo, src_mem->domain, false); - if (r) { - pr_err("CMA fail: SRC BO validate failed %d\n", r); - goto validate_fail; - } - - - r = amdgpu_amdkfd_bo_validate(dst_mem->bo, dst_mem->domain, false); - if (r) { - pr_err("CMA fail: DST BO validate failed %d\n", r); - goto validate_fail; - } - - - r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, size, false, NULL, - &fence); - if (r) - pr_err("Copy buffer failed %d\n", r); - else - *actual_size = size; - if (fence) { - amdgpu_bo_fence(src_mem->bo, fence, true); - amdgpu_bo_fence(dst_mem->bo, fence, true); - } - if (f) - *f = dma_fence_get(fence); - dma_fence_put(fence); - -validate_fail: - ttm_eu_backoff_reservation(&ticket, &list); - return r; -} - /* Returns GPU-specific tiling mode information */ int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index a4538aacf7aab..c993657ebc806 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1178,7 +1178,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( dev->adev, args->va_addr, args->size, - pdd->drm_priv, NULL, (struct kgd_mem **) &mem, &offset, + pdd->drm_priv, (struct kgd_mem **) &mem, &offset, flags, false); if (err) @@ -1697,843 +1697,6 @@ static int kfd_ioctl_ipc_import_handle(struct file *filep, return r; } -/* Maximum number of entries for process pages array which lives on stack */ -#define MAX_PP_STACK_COUNT 16 -/* Maximum number of pages kmalloc'd to hold struct page's during copy */ -#define MAX_KMALLOC_PAGES (PAGE_SIZE * 2) -#define MAX_PP_KMALLOC_COUNT (MAX_KMALLOC_PAGES/sizeof(struct page *)) - -static void kfd_put_sg_table(struct sg_table *sg) -{ - unsigned int i; - struct scatterlist *s; - - for_each_sg(sg->sgl, s, sg->nents, i) - put_page(sg_page(s)); -} - - -/* Create a sg table for the given userptr BO by pinning its system pages - * @bo: userptr BO - * @offset: Offset into BO - * @mm/@task: mm_struct & task_struct of the process that holds the BO - * @size: in/out: desired size / actual size which could be smaller - * @sg_size: out: Size of sg table. This is ALIGN_UP(@size) - * @ret_sg: out sg table - */ -static int kfd_create_sg_table_from_userptr_bo(struct kfd_bo *bo, - int64_t offset, int cma_write, - struct mm_struct *mm, - struct task_struct *task, - uint64_t *size, - uint64_t *sg_size, - struct sg_table **ret_sg) -{ - int ret, locked = 1; - struct sg_table *sg = NULL; - unsigned int i, offset_in_page, flags = 0; - unsigned long nents, n; - unsigned long pa = (bo->cpuva + offset) & PAGE_MASK; - unsigned int cur_page = 0; - struct scatterlist *s; - uint64_t sz = *size; - struct page **process_pages; - - *sg_size = 0; - sg = kmalloc(sizeof(*sg), GFP_KERNEL); - if (!sg) - return -ENOMEM; - - offset_in_page = offset & (PAGE_SIZE - 1); - nents = (sz + offset_in_page + PAGE_SIZE - 1) / PAGE_SIZE; - - ret = sg_alloc_table(sg, nents, GFP_KERNEL); - if (unlikely(ret)) { - ret = -ENOMEM; - goto sg_alloc_fail; - } - process_pages = kmalloc_array(nents, sizeof(struct pages *), - GFP_KERNEL); - if (!process_pages) { - ret = -ENOMEM; - goto page_alloc_fail; - } - - if (cma_write) - flags = FOLL_WRITE; - locked = 1; - mmap_read_lock(mm); - n = get_user_pages_remote(mm, pa, nents, flags, process_pages, - NULL, &locked); - if (locked) - mmap_read_unlock(mm); - if (n <= 0) { - pr_err("CMA: Invalid virtual address 0x%lx\n", pa); - ret = -EFAULT; - goto get_user_fail; - } - if (n != nents) { - /* Pages pinned < requested. Set the size accordingly */ - *size = (n * PAGE_SIZE) - offset_in_page; - pr_debug("Requested %lx but pinned %lx\n", nents, n); - } - - sz = 0; - for_each_sg(sg->sgl, s, n, i) { - sg_set_page(s, process_pages[cur_page], PAGE_SIZE, - offset_in_page); - sg_dma_address(s) = page_to_phys(process_pages[cur_page]); - offset_in_page = 0; - cur_page++; - sz += PAGE_SIZE; - } - *ret_sg = sg; - *sg_size = sz; - - kfree(process_pages); - return 0; - -get_user_fail: - kfree(process_pages); -page_alloc_fail: - sg_free_table(sg); -sg_alloc_fail: - kfree(sg); - return ret; -} - -static void kfd_free_cma_bos(struct cma_iter *ci) -{ - struct cma_system_bo *cma_bo, *tmp; - - list_for_each_entry_safe(cma_bo, tmp, &ci->cma_list, list) { - struct kfd_dev *dev = cma_bo->dev; - - /* sg table is deleted by free_memory_of_gpu */ - if (cma_bo->sg) - kfd_put_sg_table(cma_bo->sg); - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, cma_bo->mem, NULL); - list_del(&cma_bo->list); - kfree(cma_bo); - } -} - -/* 1 second timeout */ -#define CMA_WAIT_TIMEOUT msecs_to_jiffies(1000) - -static int kfd_cma_fence_wait(struct dma_fence *f) -{ - int ret; - - ret = dma_fence_wait_timeout(f, false, CMA_WAIT_TIMEOUT); - if (likely(ret > 0)) - return 0; - if (!ret) - ret = -ETIME; - return ret; -} - -/* Put previous (old) fence @pf but it waits for @pf to signal if the context - * of the current fence @cf is different. - */ -static int kfd_fence_put_wait_if_diff_context(struct dma_fence *cf, - struct dma_fence *pf) -{ - int ret = 0; - - if (pf && cf && cf->context != pf->context) - ret = kfd_cma_fence_wait(pf); - dma_fence_put(pf); - return ret; -} - -#define MAX_SYSTEM_BO_SIZE (512*PAGE_SIZE) - -/* Create an equivalent system BO for the given @bo. If @bo is a userptr then - * create a new system BO by pinning underlying system pages of the given - * userptr BO. If @bo is in Local Memory then create an empty system BO and - * then copy @bo into this new BO. - * @bo: Userptr BO or Local Memory BO - * @offset: Offset into bo - * @size: in/out: The size of the new BO could be less than requested if all - * the pages couldn't be pinned or size > MAX_SYSTEM_BO_SIZE. This would - * be reflected in @size - * @mm/@task: mm/task to which @bo belongs to - * @cma_bo: out: new system BO - */ -static int kfd_create_cma_system_bo(struct kfd_dev *kdev, struct kfd_bo *bo, - uint64_t *size, uint64_t offset, - int cma_write, struct kfd_process *p, - struct mm_struct *mm, - struct task_struct *task, - struct cma_system_bo **cma_bo) -{ - int ret; - struct kfd_process_device *pdd = NULL; - struct cma_system_bo *cbo; - uint64_t bo_size = 0; - struct dma_fence *f; - - uint32_t flags = KFD_IOC_ALLOC_MEM_FLAGS_GTT | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | - KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE; - - *cma_bo = NULL; - cbo = kzalloc(sizeof(**cma_bo), GFP_KERNEL); - if (!cbo) - return -ENOMEM; - - INIT_LIST_HEAD(&cbo->list); - if (bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) - bo_size = min_t(uint64_t, *size, MAX_SYSTEM_BO_SIZE); - else if (bo->cpuva) { - ret = kfd_create_sg_table_from_userptr_bo(bo, offset, - cma_write, mm, task, - size, &bo_size, - &cbo->sg); - if (ret) { - pr_err("CMA: BO create with sg failed %d\n", ret); - goto sg_fail; - } - } else { - WARN_ON(1); - ret = -EINVAL; - goto sg_fail; - } - mutex_lock(&p->mutex); - pdd = kfd_get_process_device_data(kdev, p); - if (!pdd) { - mutex_unlock(&p->mutex); - pr_err("Process device data doesn't exist\n"); - ret = -EINVAL; - goto pdd_fail; - } - - ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, bo_size, - pdd->drm_priv, cbo->sg, - &cbo->mem, NULL, flags); - mutex_unlock(&p->mutex); - if (ret) { - pr_err("Failed to create shadow system BO %d\n", ret); - goto pdd_fail; - } - - if (bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { - ret = amdgpu_amdkfd_copy_mem_to_mem(kdev->kgd, bo->mem, - offset, cbo->mem, 0, - bo_size, &f, size); - if (ret) { - pr_err("CMA: Intermediate copy failed %d\n", ret); - goto copy_fail; - } - - /* Wait for the copy to finish as subsequent copy will be done - * by different device - */ - ret = kfd_cma_fence_wait(f); - dma_fence_put(f); - if (ret) { - pr_err("CMA: Intermediate copy timed out %d\n", ret); - goto copy_fail; - } - } - - cbo->dev = kdev; - *cma_bo = cbo; - - return ret; - -copy_fail: - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(kdev->kgd, bo->mem, NULL); -pdd_fail: - if (cbo->sg) { - kfd_put_sg_table(cbo->sg); - sg_free_table(cbo->sg); - kfree(cbo->sg); - } -sg_fail: - kfree(cbo); - return ret; -} - -/* Update cma_iter.cur_bo with KFD BO that is assocaited with - * cma_iter.array.va_addr - */ -static int kfd_cma_iter_update_bo(struct cma_iter *ci) -{ - struct kfd_memory_range *arr = ci->array; - uint64_t va_end = arr->va_addr + arr->size - 1; - - mutex_lock(&ci->p->mutex); - ci->cur_bo = kfd_process_find_bo_from_interval(ci->p, arr->va_addr, - va_end); - mutex_unlock(&ci->p->mutex); - - if (!ci->cur_bo || va_end > ci->cur_bo->it.last) { - pr_err("CMA failed. Range out of bounds\n"); - return -EFAULT; - } - return 0; -} - -/* Advance iter by @size bytes. */ -static int kfd_cma_iter_advance(struct cma_iter *ci, unsigned long size) -{ - int ret = 0; - - ci->offset += size; - if (WARN_ON(size > ci->total || ci->offset > ci->array->size)) - return -EFAULT; - ci->total -= size; - /* If current range is copied, move to next range if available. */ - if (ci->offset == ci->array->size) { - - /* End of all ranges */ - if (!(--ci->nr_segs)) - return 0; - - ci->array++; - ci->offset = 0; - ret = kfd_cma_iter_update_bo(ci); - if (ret) - return ret; - } - ci->bo_offset = (ci->array->va_addr + ci->offset) - - ci->cur_bo->it.start; - return ret; -} - -static int kfd_cma_iter_init(struct kfd_memory_range *arr, unsigned long segs, - struct kfd_process *p, struct mm_struct *mm, - struct task_struct *task, struct cma_iter *ci) -{ - int ret; - int nr; - - if (!arr || !segs) - return -EINVAL; - - memset(ci, 0, sizeof(*ci)); - INIT_LIST_HEAD(&ci->cma_list); - ci->array = arr; - ci->nr_segs = segs; - ci->p = p; - ci->offset = 0; - ci->mm = mm; - ci->task = task; - for (nr = 0; nr < segs; nr++) - ci->total += arr[nr].size; - - /* Valid but size is 0. So copied will also be 0 */ - if (!ci->total) - return 0; - - ret = kfd_cma_iter_update_bo(ci); - if (!ret) - ci->bo_offset = arr->va_addr - ci->cur_bo->it.start; - return ret; -} - -static bool kfd_cma_iter_end(struct cma_iter *ci) -{ - if (!(ci->nr_segs) || !(ci->total)) - return true; - return false; -} - -/* Copies @size bytes from si->cur_bo to di->cur_bo BO. The function assumes - * both source and dest. BOs are userptr BOs. Both BOs can either belong to - * current process or one of the BOs can belong to a differnt - * process. @Returns 0 on success, -ve on failure - * - * @si: Source iter - * @di: Dest. iter - * @cma_write: Indicates if it is write to remote or read from remote - * @size: amount of bytes to be copied - * @copied: Return number of bytes actually copied. - */ -static int kfd_copy_userptr_bos(struct cma_iter *si, struct cma_iter *di, - bool cma_write, uint64_t size, - uint64_t *copied) -{ - int i, ret = 0, locked; - unsigned int nents, nl; - unsigned int offset_in_page; - struct page *pp_stack[MAX_PP_STACK_COUNT]; - struct page **process_pages = pp_stack; - unsigned long rva, lva = 0, flags = 0; - uint64_t copy_size, to_copy = size; - struct cma_iter *li, *ri; - - if (cma_write) { - ri = di; - li = si; - flags |= FOLL_WRITE; - } else { - li = di; - ri = si; - } - /* rva: remote virtual address. Page aligned to start page. - * rva + offset_in_page: Points to remote start address - * lva: local virtual address. Points to the start address. - * nents: computes number of remote pages to request - */ - offset_in_page = ri->bo_offset & (PAGE_SIZE - 1); - rva = (ri->cur_bo->cpuva + ri->bo_offset) & PAGE_MASK; - lva = li->cur_bo->cpuva + li->bo_offset; - - nents = (size + offset_in_page + PAGE_SIZE - 1) / PAGE_SIZE; - - copy_size = min_t(uint64_t, size, PAGE_SIZE - offset_in_page); - *copied = 0; - - if (nents > MAX_PP_STACK_COUNT) { - /* For reliability kmalloc only 2 pages worth */ - process_pages = kmalloc(min_t(size_t, MAX_KMALLOC_PAGES, - sizeof(struct pages *)*nents), - GFP_KERNEL); - - if (!process_pages) - return -ENOMEM; - } - - while (nents && to_copy) { - nl = min_t(unsigned int, MAX_PP_KMALLOC_COUNT, nents); - locked = 1; - mmap_read_lock(ri->mm); - nl = get_user_pages_remote(ri->mm, rva, nl, - flags, process_pages, NULL, - &locked); - if (locked) - mmap_read_unlock(ri->mm); - if (nl <= 0) { - pr_err("CMA: Invalid virtual address 0x%lx\n", rva); - ret = -EFAULT; - break; - } - - for (i = 0; i < nl; i++) { - unsigned int n; - void *kaddr = kmap(process_pages[i]); - - if (cma_write) { - n = copy_from_user(kaddr+offset_in_page, - (void *)lva, copy_size); - set_page_dirty(process_pages[i]); - } else { - n = copy_to_user((void *)lva, - kaddr+offset_in_page, - copy_size); - } - kunmap(kaddr); - if (n) { - ret = -EFAULT; - break; - } - to_copy -= copy_size; - if (!to_copy) - break; - lva += copy_size; - rva += (copy_size + offset_in_page); - WARN_ONCE(rva & (PAGE_SIZE - 1), - "CMA: Error in remote VA computation"); - offset_in_page = 0; - copy_size = min_t(uint64_t, to_copy, PAGE_SIZE); - } - - for (i = 0; i < nl; i++) - put_page(process_pages[i]); - - if (ret) - break; - nents -= nl; - } - - if (process_pages != pp_stack) - kfree(process_pages); - - *copied = (size - to_copy); - return ret; - -} - -static int kfd_create_kgd_mem(struct kfd_dev *kdev, uint64_t size, - struct kfd_process *p, struct kgd_mem **mem) -{ - int ret; - struct kfd_process_device *pdd = NULL; - uint32_t flags = KFD_IOC_ALLOC_MEM_FLAGS_GTT | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | - KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE; - - if (!mem || !size || !p || !kdev) - return -EINVAL; - - *mem = NULL; - - mutex_lock(&p->mutex); - pdd = kfd_get_process_device_data(kdev, p); - if (!pdd) { - mutex_unlock(&p->mutex); - pr_err("Process device data doesn't exist\n"); - return -EINVAL; - } - - ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, size, - pdd->drm_priv, NULL, - mem, NULL, flags); - mutex_unlock(&p->mutex); - if (ret) { - pr_err("Failed to create shadow system BO %d\n", ret); - return -EINVAL; - } - - return 0; -} - -static int kfd_destroy_kgd_mem(struct kgd_mem *mem) -{ - if (!mem) - return -EINVAL; - - /* param adev is not used*/ - return amdgpu_amdkfd_gpuvm_free_memory_of_gpu(NULL, mem, NULL); -} - -/* Copies @size bytes from si->cur_bo to di->cur_bo starting at their - * respective offset. - * @si: Source iter - * @di: Dest. iter - * @cma_write: Indicates if it is write to remote or read from remote - * @size: amount of bytes to be copied - * @f: Return the last fence if any - * @copied: Return number of bytes actually copied. - */ -static int kfd_copy_bos(struct cma_iter *si, struct cma_iter *di, - int cma_write, uint64_t size, - struct dma_fence **f, uint64_t *copied, - struct kgd_mem **tmp_mem) -{ - int err = 0; - struct kfd_bo *dst_bo = di->cur_bo, *src_bo = si->cur_bo; - uint64_t src_offset = si->bo_offset, dst_offset = di->bo_offset; - struct kgd_mem *src_mem = src_bo->mem, *dst_mem = dst_bo->mem; - struct kfd_dev *dev = dst_bo->dev; - int d2d = 0; - - *copied = 0; - if (f) - *f = NULL; - if (src_bo->cpuva && dst_bo->cpuva) - return kfd_copy_userptr_bos(si, di, cma_write, size, copied); - - /* If either source or dest. is userptr, create a shadow system BO - * by using the underlying userptr BO pages. Then use this shadow - * BO for copy. src_offset & dst_offset are adjusted because the new BO - * is only created for the window (offset, size) requested. - * The shadow BO is created on the other device. This means if the - * other BO is a device memory, the copy will be using that device. - * The BOs are stored in cma_list for deferred cleanup. This minimizes - * fence waiting just to the last fence. - */ - if (src_bo->cpuva) { - dev = dst_bo->dev; - err = kfd_create_cma_system_bo(dev, src_bo, &size, - si->bo_offset, cma_write, - si->p, si->mm, si->task, - &si->cma_bo); - src_mem = si->cma_bo->mem; - src_offset = si->bo_offset & (PAGE_SIZE - 1); - list_add_tail(&si->cma_bo->list, &si->cma_list); - } else if (dst_bo->cpuva) { - dev = src_bo->dev; - err = kfd_create_cma_system_bo(dev, dst_bo, &size, - di->bo_offset, cma_write, - di->p, di->mm, di->task, - &di->cma_bo); - dst_mem = di->cma_bo->mem; - dst_offset = di->bo_offset & (PAGE_SIZE - 1); - list_add_tail(&di->cma_bo->list, &di->cma_list); - } else if (src_bo->dev->kgd != dst_bo->dev->kgd) { - /* This indicates that atleast on of the BO is in local mem. - * If both are in local mem of different devices then create an - * intermediate System BO and do a double copy - * [VRAM]--gpu1-->[System BO]--gpu2-->[VRAM]. - * If only one BO is in VRAM then use that GPU to do the copy - */ - if (src_bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM && - dst_bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { - dev = dst_bo->dev; - size = min_t(uint64_t, size, MAX_SYSTEM_BO_SIZE); - d2d = 1; - - if (*tmp_mem == NULL) { - if (kfd_create_kgd_mem(src_bo->dev, - MAX_SYSTEM_BO_SIZE, - si->p, - tmp_mem)) - return -EINVAL; - } - - if (amdgpu_amdkfd_copy_mem_to_mem(src_bo->dev->kgd, - src_bo->mem, si->bo_offset, - *tmp_mem, 0, - size, f, &size)) - /* tmp_mem will be freed in caller.*/ - return -EINVAL; - - kfd_cma_fence_wait(*f); - dma_fence_put(*f); - - src_mem = *tmp_mem; - src_offset = 0; - } else if (src_bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) - dev = src_bo->dev; - /* else already set to dst_bo->dev */ - } - - if (err) { - pr_err("Failed to create system BO %d", err); - return -EINVAL; - } - - err = amdgpu_amdkfd_copy_mem_to_mem(dev->kgd, src_mem, src_offset, - dst_mem, dst_offset, size, f, - copied); - /* The tmp_bo allocates additional memory. So it is better to wait and - * delete. Also since multiple GPUs are involved the copies are - * currently not pipelined. - */ - if (*tmp_mem && d2d) { - if (!err) { - kfd_cma_fence_wait(*f); - dma_fence_put(*f); - *f = NULL; - } - } - return err; -} - -/* Copy single range from source iterator @si to destination iterator @di. - * @si will move to next range and @di will move by bytes copied. - * @return : 0 for success or -ve for failure - * @f: The last fence if any - * @copied: out: number of bytes copied - */ -static int kfd_copy_single_range(struct cma_iter *si, struct cma_iter *di, - bool cma_write, struct dma_fence **f, - uint64_t *copied, struct kgd_mem **tmp_mem) -{ - int err = 0; - uint64_t copy_size, n; - uint64_t size = si->array->size; - struct kfd_bo *src_bo = si->cur_bo; - struct dma_fence *lfence = NULL; - - if (!src_bo || !di || !copied) - return -EINVAL; - *copied = 0; - if (f) - *f = NULL; - - while (size && !kfd_cma_iter_end(di)) { - struct dma_fence *fence = NULL; - - copy_size = min(size, (di->array->size - di->offset)); - - err = kfd_copy_bos(si, di, cma_write, copy_size, - &fence, &n, tmp_mem); - if (err) { - pr_err("CMA %d failed\n", err); - break; - } - - if (fence) { - err = kfd_fence_put_wait_if_diff_context(fence, - lfence); - lfence = fence; - if (err) - break; - } - - size -= n; - *copied += n; - err = kfd_cma_iter_advance(si, n); - if (err) - break; - err = kfd_cma_iter_advance(di, n); - if (err) - break; - } - - if (f) - *f = dma_fence_get(lfence); - dma_fence_put(lfence); - - return err; -} - -static int kfd_ioctl_cross_memory_copy(struct file *filep, - struct kfd_process *local_p, void *data) -{ - struct kfd_ioctl_cross_memory_copy_args *args = data; - struct kfd_memory_range *src_array, *dst_array; - struct kfd_process *remote_p; - struct task_struct *remote_task; - struct mm_struct *remote_mm; - struct pid *remote_pid; - struct dma_fence *lfence = NULL; - uint64_t copied = 0, total_copied = 0; - struct cma_iter di, si; - const char *cma_op; - int err = 0; - struct kgd_mem *tmp_mem = NULL; - - /* Check parameters */ - if (args->src_mem_range_array == 0 || args->dst_mem_range_array == 0 || - args->src_mem_array_size == 0 || args->dst_mem_array_size == 0) - return -EINVAL; - args->bytes_copied = 0; - - /* Allocate space for source and destination arrays */ - src_array = kmalloc_array((args->src_mem_array_size + - args->dst_mem_array_size), - sizeof(struct kfd_memory_range), - GFP_KERNEL); - if (!src_array) - return -ENOMEM; - dst_array = &src_array[args->src_mem_array_size]; - - if (copy_from_user(src_array, (void __user *)args->src_mem_range_array, - args->src_mem_array_size * - sizeof(struct kfd_memory_range))) { - err = -EFAULT; - goto copy_from_user_fail; - } - if (copy_from_user(dst_array, (void __user *)args->dst_mem_range_array, - args->dst_mem_array_size * - sizeof(struct kfd_memory_range))) { - err = -EFAULT; - goto copy_from_user_fail; - } - - /* Get remote process */ - remote_pid = find_get_pid(args->pid); - if (!remote_pid) { - pr_err("Cross mem copy failed. Invalid PID %d\n", args->pid); - err = -ESRCH; - goto copy_from_user_fail; - } - - remote_task = get_pid_task(remote_pid, PIDTYPE_PID); - if (!remote_pid) { - pr_err("Cross mem copy failed. Invalid PID or task died %d\n", - args->pid); - err = -ESRCH; - goto get_pid_task_fail; - } - - /* Check access permission */ - remote_mm = mm_access(remote_task, PTRACE_MODE_ATTACH_REALCREDS); - if (!remote_mm || IS_ERR(remote_mm)) { - err = IS_ERR(remote_mm) ? PTR_ERR(remote_mm) : -ESRCH; - if (err == -EACCES) { - pr_err("Cross mem copy failed. Permission error\n"); - err = -EPERM; - } else - pr_err("Cross mem copy failed. Invalid task %d\n", - err); - goto mm_access_fail; - } - - remote_p = kfd_get_process(remote_task); - if (IS_ERR(remote_p)) { - pr_err("Cross mem copy failed. Invalid kfd process %d\n", - args->pid); - err = -EINVAL; - goto kfd_process_fail; - } - /* Initialise cma_iter si & @di with source & destination range. */ - if (KFD_IS_CROSS_MEMORY_WRITE(args->flags)) { - cma_op = "WRITE"; - pr_debug("CMA WRITE: local -> remote\n"); - err = kfd_cma_iter_init(dst_array, args->dst_mem_array_size, - remote_p, remote_mm, remote_task, &di); - if (err) - goto kfd_process_fail; - err = kfd_cma_iter_init(src_array, args->src_mem_array_size, - local_p, current->mm, current, &si); - if (err) - goto kfd_process_fail; - } else { - cma_op = "READ"; - pr_debug("CMA READ: remote -> local\n"); - - err = kfd_cma_iter_init(dst_array, args->dst_mem_array_size, - local_p, current->mm, current, &di); - if (err) - goto kfd_process_fail; - err = kfd_cma_iter_init(src_array, args->src_mem_array_size, - remote_p, remote_mm, remote_task, &si); - if (err) - goto kfd_process_fail; - } - - /* Copy one si range at a time into di. After each call to - * kfd_copy_single_range() si will move to next range. di will be - * incremented by bytes copied - */ - while (!kfd_cma_iter_end(&si) && !kfd_cma_iter_end(&di)) { - struct dma_fence *fence = NULL; - - err = kfd_copy_single_range(&si, &di, - KFD_IS_CROSS_MEMORY_WRITE(args->flags), - &fence, &copied, &tmp_mem); - total_copied += copied; - - if (err) - break; - - /* Release old fence if a later fence is created. If no - * new fence is created, then keep the preivous fence - */ - if (fence) { - err = kfd_fence_put_wait_if_diff_context(fence, - lfence); - lfence = fence; - if (err) - break; - } - } - - /* Wait for the last fence irrespective of error condition */ - if (lfence) { - err = kfd_cma_fence_wait(lfence); - dma_fence_put(lfence); - if (err) - pr_err("CMA %s failed. BO timed out\n", cma_op); - } - - if (tmp_mem) - kfd_destroy_kgd_mem(tmp_mem); - - kfd_free_cma_bos(&si); - kfd_free_cma_bos(&di); - -kfd_process_fail: - mmput(remote_mm); -mm_access_fail: - put_task_struct(remote_task); -get_pid_task_fail: - put_pid(remote_pid); -copy_from_user_fail: - kfree(src_array); - - /* An error could happen after partial copy. In that case this will - * reflect partial amount of bytes copied - */ - args->bytes_copied = total_copied; - return err; -} - static int kfd_ioctl_export_dmabuf(struct file *filep, struct kfd_process *p, void *data) { @@ -4284,9 +3447,6 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, kfd_ioctl_rlc_spm, 0), - - AMDKFD_IOCTL_DEF(AMDKFD_IOC_CROSS_MEMORY_COPY, - kfd_ioctl_cross_memory_copy, 0), }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 4498725592c2b..cab6a7cadfbf0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -406,38 +406,6 @@ struct kfd_bo { unsigned int mem_type; }; -struct cma_system_bo { - struct kgd_mem *mem; - struct sg_table *sg; - struct kfd_dev *dev; - struct list_head list; -}; - -/* Similar to iov_iter */ -struct cma_iter { - /* points to current entry of range array */ - struct kfd_memory_range *array; - /* total number of entries in the initial array */ - unsigned long nr_segs; - /* total amount of data pointed by kfd array*/ - unsigned long total; - /* offset into the entry pointed by cma_iter.array */ - unsigned long offset; - struct kfd_process *p; - struct mm_struct *mm; - struct task_struct *task; - /* current kfd_bo associated with cma_iter.array.va_addr */ - struct kfd_bo *cur_bo; - /* offset w.r.t cur_bo */ - unsigned long bo_offset; - /* If cur_bo is a userptr BO, then a shadow system BO is created - * using its underlying pages. cma_bo holds this BO. cma_list is a - * list cma_bos created in one session - */ - struct cma_system_bo *cma_bo; - struct list_head cma_list; -}; - enum kfd_mempool { KFD_MEMPOOL_SYSTEM_CACHEABLE = 1, KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index cff1cb83a10c7..e219d556e2ad1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -744,7 +744,7 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, int err; err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, gpu_va, size, - pdd->drm_priv, NULL, &mem, NULL, + pdd->drm_priv, mem, NULL, flags, false); if (err) goto err_alloc_mem; diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 0712a6aed43b5..bcda022281f26 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -840,37 +840,6 @@ struct kfd_ioctl_ipc_import_handle_args { __u32 flags; /* from KFD */ }; -struct kfd_memory_range { - __u64 va_addr; - __u64 size; -}; - -/* flags definitions - * BIT0: 0: read operation, 1: write operation. - * This also identifies if the src or dst array belongs to remote process - */ -#define KFD_CROSS_MEMORY_RW_BIT (1 << 0) -#define KFD_SET_CROSS_MEMORY_READ(flags) (flags &= ~KFD_CROSS_MEMORY_RW_BIT) -#define KFD_SET_CROSS_MEMORY_WRITE(flags) (flags |= KFD_CROSS_MEMORY_RW_BIT) -#define KFD_IS_CROSS_MEMORY_WRITE(flags) (flags & KFD_CROSS_MEMORY_RW_BIT) - -struct kfd_ioctl_cross_memory_copy_args { - /* to KFD: Process ID of the remote process */ - __u32 pid; - /* to KFD: See above definition */ - __u32 flags; - /* to KFD: Source GPU VM range */ - __u64 src_mem_range_array; - /* to KFD: Size of above array */ - __u64 src_mem_array_size; - /* to KFD: Destination GPU VM range */ - __u64 dst_mem_range_array; - /* to KFD: Size of above array */ - __u64 dst_mem_array_size; - /* from KFD: Total amount of bytes copied */ - __u64 bytes_copied; -}; - /* Guarantee host access to memory */ #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 /* Fine grained coherency between all devices with access */ @@ -1816,11 +1785,7 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_RLC_SPM \ AMDKFD_IOWR(0x84, struct kfd_ioctl_spm_args) -#define AMDKFD_IOC_CROSS_MEMORY_COPY \ - AMDKFD_IOWR(0x83, struct kfd_ioctl_cross_memory_copy_args) - #define AMDKFD_COMMAND_START_2 0x80 #define AMDKFD_COMMAND_END_2 0x85 - #endif From a30d7243bc021d8f5afd0224ca24015801597a0d Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Fri, 5 Aug 2022 17:10:44 +0800 Subject: [PATCH 0788/2653] drm/amdgpu: relax the check in amdgpu_device_is_peer_accessible To support p2p feature on old kernels without defining CONFIG_PCI_P2PDMA, amdgpu_device_is_peer_accessible needs to return true in such scenario. So relax the requirement from upstream. Suggested-by: Ramesh Errabolu Suggested-by: Felix Kuehling Signed-off-by: Leslie Shi Signed-off-by: Guchun Chen Reviewed-by: Ramesh Errabolu --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 1804a1927c825..e09b0d1725cb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6855,17 +6855,20 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, struct amdgpu_device *peer_adev) { -#ifdef CONFIG_HSA_AMD_P2P - bool p2p_access = + bool p2p_access = true; + bool p2p_addressable = false; + bool is_large_bar = adev->gmc.visible_vram_size && + adev->gmc.real_vram_size == adev->gmc.visible_vram_size; + +#ifdef CONFIG_PCI_P2PDMA + p2p_access = !adev->gmc.xgmi.connected_to_cpu && !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0); if (!p2p_access) dev_info(adev->dev, "PCIe P2P access from peer device %s is not supported by the chipset\n", pci_name(peer_adev->pdev)); - - bool is_large_bar = adev->gmc.visible_vram_size && - adev->gmc.real_vram_size == adev->gmc.visible_vram_size; - bool p2p_addressable = amdgpu_device_check_iommu_remap(peer_adev); + p2p_addressable = amdgpu_device_check_iommu_remap(peer_adev); +#endif if (!p2p_addressable) { uint64_t address_mask = peer_adev->dev->dma_mask ? @@ -6877,9 +6880,6 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, aper_limit & address_mask); } return pcie_p2p && is_large_bar && p2p_access && p2p_addressable; -#else - return false; -#endif } int amdgpu_device_baco_enter(struct amdgpu_device *adev) From 1156c31414810eb2ee2cb8c0401308595447b549 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Mon, 8 Aug 2022 10:06:03 +0800 Subject: [PATCH 0789/2653] drm/amdgpu: drop compiler guard for pcie_p2p CONFIG_HSA_AMD_P2P is not needed as a build option for pcie_p2p, as p2p feature needs to be always supported on dkms branch, otherwise, intree build fails once CONFIG_HSA_AMD_P2P is not defined. Also drop redundant extern of pcie_p2p in amdgpu.h. Fixes: af428201b20e("drm/amdgpu: relax the check in amdgpu_device_is_peer_accessible") Signed-off-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 -- 2 files changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index f286bb85ee00e..7519251a91a76 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -247,9 +247,6 @@ static const bool __maybe_unused debug_evictions; /* = false */ static const bool __maybe_unused no_system_mem_limit; static const int __maybe_unused halt_if_hws_hang; #endif -#ifdef CONFIG_HSA_AMD_P2P -extern bool pcie_p2p; -#endif extern int amdgpu_tmz; extern int amdgpu_reset_method; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 3921030fa1b0f..36e5243190a28 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -892,11 +892,9 @@ module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444); * DOC: pcie_p2p (bool) * Enable PCIe P2P (requires large-BAR). Default value: true (on) */ -#ifdef CONFIG_HSA_AMD_P2P bool pcie_p2p = true; module_param(pcie_p2p, bool, 0444); MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); -#endif /** * DOC: dcfeaturemask (uint) From de95d197fb93c63f1df308eda3846dc06b6596eb Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 8 Aug 2022 10:49:08 +0800 Subject: [PATCH 0790/2653] drm/amdgpu: enable CONFIG_HSA_AMD_P2P when PCI_P2PDMA and DMABUF_MOVENOTIFY are set Suggested-by: Felix Kuehling Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/Makefile | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index a00c632cc588f..ff7758499d54d 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -167,9 +167,11 @@ endif export CONFIG_DRM_AMD_DC_HDCP=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP -ifeq ($(call _is_kcl_macro_defined,HAVE_LINUX_PCI_P2PDMA_H),y) -export CONFIG_HSA_AMD_P2P=y -subdir-ccflags-y += -DCONFIG_HSA_AMD_P2P +ifeq (y,$(CONFIG_PCI_P2PDMA)) + ifeq (y,$(CONFIG_DMABUF_MOVENOTIFY)) + export CONFIG_HSA_AMD_P2P=y + subdir-ccflags-y += -DCONFIG_HSA_AMD_P2P + endif endif # Trying to enable DCN2/3 with core2 optimizations will result in From 02fa4454dc40db1391cf5c46ba7b584bcfd6c5c7 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 8 Aug 2022 17:38:51 -0400 Subject: [PATCH 0791/2653] drm/amdkfd: Fix VRAM attachment Use kfd_mem_attach_vram_bo instead of kfd_mem_attach_dmabuf. Signed-off-by: Felix Kuehling Reviewed-by: Ramesh Errabolu --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 98390bf602b18..8bccb19d475a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -964,9 +964,8 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, if (ret) goto unwind; #ifdef AMDKCL_AMDGPU_DMABUF_OPS - /* Enable acces to GTT and VRAM BOs of peer devices */ - } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT || - mem->domain == AMDGPU_GEM_DOMAIN_VRAM) { + /* Enable acces to GTT BOs of peer devices */ + } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT) { attachment[i]->type = KFD_MEM_ATT_DMABUF; ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]); if (ret) From c2bf62de57d5b86d02e0ab215310606b75b6ce6d Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 8 Aug 2022 19:51:45 -0400 Subject: [PATCH 0792/2653] drm/amdkfd: Fix DEVICE_PRIVATE page leak on 5.18 commit 27674ef6c73f ("mm: remove the extra ZONE_DEVICE struct page refcount") removed an extra reference count for ZONE_DEVICE pages. This requires a corresponding driver change (which was part of that patch). For DKMS builds, conditionally get a page reference only on old kernels without this patch. CONFIG_DEV_PAGEMAP_OPS is a suitable indicator, because this option was removed by the patch, and was previously selected by CONFIG_DEVICE_PRIVATE. Signed-off-by: Felix Kuehling Reviewed-by: Alex Sierra --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 9946bab27a712..cd98c44accd34 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -225,7 +225,9 @@ svm_migrate_get_vram_page(struct svm_range *prange, unsigned long pfn) VM_BUG_ON_PAGE(page_ref_count(page), page); init_page_count(page); #else +#if IS_ENABLED(CONFIG_DEV_PAGEMAP_OPS) get_page(page); +#endif #endif lock_page(page); } From 8a1d03688bcceb123aee6e38a28b44db5b9adaa1 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 9 Aug 2022 17:10:52 -0400 Subject: [PATCH 0793/2653] drm/amdkfd: Remove useless #ifdefs Both branches are exactly the same, so the #ifdefs are no longer needed. Fixes: 90fbc2dc692e ("drm/amdkcl: cleanup kcl_bitmap_xxx") CC: Flora Cui Signed-off-by: Felix Kuehling Reviewed-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 701bc5194f0f6..81b4f9c82b51a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -175,13 +175,8 @@ void kfd_process_dequeue_from_all_devices(struct kfd_process *p) int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p) { INIT_LIST_HEAD(&pqm->queues); -#if defined(HAVE_BITMAP_FUNCS) pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, GFP_KERNEL); -#else - pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, - GFP_KERNEL); -#endif if (!pqm->queue_slot_bitmap) return -ENOMEM; pqm->process = p; @@ -242,11 +237,7 @@ void pqm_uninit(struct process_queue_manager *pqm) kfree(pqn); } -#if defined(HAVE_BITMAP_FUNCS) bitmap_free(pqm->queue_slot_bitmap); -#else - bitmap_free(pqm->queue_slot_bitmap); -#endif pqm->queue_slot_bitmap = NULL; } From d04b4bcb0c2231446ea6b933ef5acbfc3b47f38a Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 8 Aug 2022 20:16:39 -0400 Subject: [PATCH 0794/2653] drm/amd/dkms: Bump package version to 5.18.0 DKMS packages built from staging should have verion 5.18, not 5.16. Signed-off-by: Felix Kuehling Reviewed-by: Hawking Zhang Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 3feca735c2140..eada36c6a9f53 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 5.16.0) +AC_INIT(amdgpu-dkms, 5.18.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 2e4cfc6a3adb9c0504e0dde22b21c5f7a94211e8 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 17 Aug 2022 17:02:02 +0800 Subject: [PATCH 0795/2653] drm/amdkcl: Bump dkms package version to 5.19.0 Bump dkms package version to 5.19.0 Signed-off-by: Ma Jun Change-Id: Ia94eea0c5d92a3e9673e069223f86f4811c7a6ee --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index eada36c6a9f53..fb89f280535c4 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 5.18.0) +AC_INIT(amdgpu-dkms, 5.19.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From fb0467d08ba4932480445d9be844bc0fee6d08ff Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 6 Jul 2022 09:56:55 +0800 Subject: [PATCH 0796/2653] drm/amdkcl: Fix the CFLAGS_xx process script Only remove the AMDDALPATH with prefix CFLAGS_ Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I9be3fe482ccb1da0226572e2726c025d5487205c --- drivers/gpu/drm/amd/dkms/pre-build.sh | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 81a0d5da5c8bd..07df3f07ea532 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -67,10 +67,11 @@ done export KERNELVER (cd $SRC && ./configure) -# rename CFLAGS_target.o to CFLAGS_target.o +# rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o +# for kernel version < 5.3 if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then for file in $(grep -rl 'CFLAGS_' amd/display/); do - sed -i 's|$(AMDDALPATH)/.*/\(.*\.o\)|\1|' $file + sed -i 's|\(CFLAGS_[A-Z_]*\)$(AMDDALPATH)/.*/\(.*\.o\)|\1\2|' $file done fi From 30b81de6e8f7c9ea1996100468fcff45855cf663 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 8 Jul 2022 14:09:09 +0800 Subject: [PATCH 0797/2653] drm/amdkcl: Fix the bug when get gcc version Fix the bug when get gcc version Signed-off-by: Ma Jun Reviewed-by: Flora Cui Reviewed-by: Guchun Chen Change-Id: If49e6bb007c382cdd1e35e0597a4d9e77287f099 --- drivers/gpu/drm/amd/dkms/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index ff7758499d54d..64171883b4bb2 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -19,7 +19,7 @@ endif ifdef CONFIG_CC_IS_GCC GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) -GCCPAT=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) +GCCPAT=$(shell echo __GNUC_PATCHLEVEL__ | $(CC) -E -x c - | tail -n 1) # CONFIG_GCC_VERSION returns x.xx.xx as the version format GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) From 464692aa52a15a38cbac8256ebb619e112f5053f Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 8 Jul 2022 10:46:54 +0800 Subject: [PATCH 0798/2653] drm/amdkcl: Export gcc related config Check and export CONFIG_CC_IS_GCC and CONFIG_GCC_VERSION for the kernels which has no these config. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: Id2f5da8b515a11bde8e40b8cc4a694b0b249ab47 --- drivers/gpu/drm/amd/dkms/Makefile | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 64171883b4bb2..6178008b48339 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -16,16 +16,22 @@ ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ),n) $(error dma_resv->seq is missing., exit...) endif -ifdef CONFIG_CC_IS_GCC +ifeq ($(CC), gcc) GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) GCCPAT=$(shell echo __GNUC_PATCHLEVEL__ | $(CC) -E -x c - | tail -n 1) # CONFIG_GCC_VERSION returns x.xx.xx as the version format GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) +ifdef CONFIG_CC_IS_GCC ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) $(warning "Local GCC version $(GCCSTR) does not match kernel compiler GCC version $(CONFIG_GCC_VERSION)") $(warning "This may cause unexpected and hard-to-isolate compiler-related issues") endif +else +export CONFIG_CC_IS_GCC=y +export CONFIG_GCC_VERSION=$(GCCSTR) +$(warning "CONFIG_CC_IS_GCC is not defined. Let's export it with version $(CONFIG_GCC_VERSION)") +endif endif DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) From db162c7c92f735ca428548522b0ac372a32adea0 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 16 Aug 2022 16:50:39 +0800 Subject: [PATCH 0799/2653] drm/amdkcl: fix ttm debugfs dir name Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c index c3e2fcbdd2cc6..5b340c2dc9c8d 100644 --- a/drivers/gpu/drm/ttm/ttm_device.c +++ b/drivers/gpu/drm/ttm/ttm_device.c @@ -79,7 +79,7 @@ static int ttm_global_init(void) si_meminfo(&si); - ttm_debugfs_root = debugfs_create_dir("ttm", NULL); + ttm_debugfs_root = debugfs_create_dir(TTM_NAME, NULL); if (IS_ERR(ttm_debugfs_root)) { ttm_debugfs_root = NULL; } From 030634314a55152e9e6803c2581d61b058c9a5bf Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 15 Aug 2022 22:07:12 +0800 Subject: [PATCH 0800/2653] drm/amdkcl: fake macro for_each_cpu_wrap and function cpumask_next_wrap It's caused by 78231f639e2eec3f14de8bb8309f459413ca86b4 drm/amdkfd: Try to schedule bottom half on same core Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c | 38 +++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_cpumask.h | 43 ++++++++++++++++++++++++ 4 files changed, 83 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c create mode 100644 include/kcl/kcl_cpumask.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index d0ccd6f534348..e9d5160622e08 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_mce_amd.o kcl_workqueue.o + kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c b/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c new file mode 100644 index 0000000000000..fe36b386ff52b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#ifndef for_each_cpu_wrap +/* copied from lib/cpumask.c +/** + * cpumask_next_wrap - helper to implement for_each_cpu_wrap + * @n: the cpu prior to the place to search + * @mask: the cpumask pointer + * @start: the start point of the iteration + * @wrap: assume @n crossing @start terminates the iteration + * + * Returns >= nr_cpu_ids on completion + * + * Note: the @wrap argument is required for the start condition when + * we cannot assume @start is set in @mask. + */ +int _kcl_cpumask_next_wrap(int n, const struct cpumask *mask, int start, bool wrap) +{ + int next; + +again: + next = cpumask_next(n, mask); + + if (wrap && n < start && next >= start) { + return nr_cpumask_bits; + + } else if (next >= nr_cpumask_bits) { + wrap = true; + n = -1; + goto again; + } + + return next; +} +EXPORT_SYMBOL(_kcl_cpumask_next_wrap); +#endif + diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 42072db6869d3..251fee9e35fca 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -95,5 +95,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_cpumask.h b/include/kcl/kcl_cpumask.h new file mode 100644 index 0000000000000..aee779d6ec5f2 --- /dev/null +++ b/include/kcl/kcl_cpumask.h @@ -0,0 +1,43 @@ +/*SPDX-License-Identifier: GPL-2.0*/ + +#include +#include +#include +#include +#include + +#ifndef for_each_cpu_wrap + +extern int _kcl_cpumask_next_wrap(int n, const struct cpumask *mask, + int start, bool wrap); + +static inline +int cpumask_next_wrap(int n, const struct cpumask *mask, + int start, bool wrap) +{ +return _kcl_cpumask_next_wrap(n, mask, start, wrap); +} + +/* Copied from include/linux/cpumask.h */ +#if NR_CPUS == 1 +#define for_each_cpu_wrap(cpu, mask, start) \ + for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask, (void)(start)) +#else +/** + * for_each_cpu_wrap - iterate over every cpu in a mask, starting at a specified location + * @cpu: the (optionally unsigned) integer iterator + * @mask: the cpumask pointer + * @start: the start location + * + * The implementation does not assume any bit in @mask is set (including @start). + * + * After the loop, cpu is >= nr_cpu_ids. + */ +#define for_each_cpu_wrap(cpu, mask, start) \ + for ((cpu) = cpumask_next_wrap((start)-1, (mask), (start), false); \ + (cpu) < nr_cpumask_bits; \ + (cpu) = cpumask_next_wrap((cpu), (mask), (start), true)) + +#endif +#endif + From bb4e6e4fc4134e494884cdb6720bd6ad09b1917e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 18 Aug 2022 16:42:51 +0800 Subject: [PATCH 0801/2653] drm/amdkcl: Optimize the make command of dkms The parameter -j${num_cpu_cores} will be added by dkms, so remove this param here. Signed-off-by: Ma Jun Reviewed-by: Guchun Chen Reviewed-by: Flora Cui Change-Id: I4346afa99a0a06126bb21873e5c9d0c9c5059131 --- drivers/gpu/drm/amd/dkms/dkms.conf | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index bd79232132f60..a4fde02caa219 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -26,18 +26,7 @@ BUILT_MODULE_NAME[4]="amddrm_ttm_helper" BUILT_MODULE_LOCATION[4]="." DEST_MODULE_LOCATION[4]="/kernel/drivers/gpu/drm" -# Find out how many CPU cores can be use if we pass appropriate -j option to make. -# DKMS could use all cores on multicore systems to build the kernel module. -num_cpu_cores() -{ - if [ -x /usr/bin/nproc ]; then - nproc - else - echo "1" - fi -} - -MAKE[0]="make -j$(num_cpu_cores) TTM_NAME=${BUILT_MODULE_NAME[1]} \ +MAKE[0]="make TTM_NAME=${BUILT_MODULE_NAME[1]} \ SCHED_NAME=${BUILT_MODULE_NAME[3]} \ -C $kernel_source_dir \ M=$dkms_tree/$module/$module_version/build" From 9b2face8da4da4a485903c41788cfc383e33fc93 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 23 Aug 2022 17:01:32 +0800 Subject: [PATCH 0802/2653] drm/amdkcl: Fix the compile error of drm_for_each_fb Fix the redefintion error of drm_for_each_fb. Because the drm_framebuffer.h is not include in drm_crtc.h anymore. Signed-off-by: Ma Jun Change-Id: Ie68880609d4ceba4aaddbf074b2682d0fc0ee577 --- include/kcl/kcl_drm_crtc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h index 2f01179d0c2b1..3911fa0faaa04 100644 --- a/include/kcl/kcl_drm_crtc.h +++ b/include/kcl/kcl_drm_crtc.h @@ -48,9 +48,9 @@ #ifndef KCL_KCL_DRM_CRTC_H #define KCL_KCL_DRM_CRTC_H -#include #include #include +#include /* Copied from include/drm/drm_mode.h */ #ifndef DRM_MODE_ROTATE_0 From 9b14bb204679cce49aefdf2bd6a9fc03fccc0448 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 14 Jul 2022 16:40:51 +0800 Subject: [PATCH 0803/2653] drm/amdkcl: fix redefined pr_fmt warning Signed-off-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_device.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c index 5b340c2dc9c8d..f49a262462297 100644 --- a/drivers/gpu/drm/ttm/ttm_device.c +++ b/drivers/gpu/drm/ttm/ttm_device.c @@ -25,8 +25,6 @@ * Authors: Christian König */ -#define pr_fmt(fmt) "[TTM DEVICE] " fmt - #include #include #include @@ -39,6 +37,11 @@ #include "ttm_module.h" #include "ttm_bo_internal.h" +#ifdef pr_fmt +#undef pr_fmt +#endif +#define pr_fmt(fmt) "[TTM DEVICE] " fmt + /* * ttm_global_mutex - protecting the global state */ From d9ace2ec0afea98adffcf54a87cd5739af4c84ec Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Fri, 19 Aug 2022 21:40:12 -0400 Subject: [PATCH 0804/2653] drm/amdkfd: Fix the criu restore regression The logic to create the IDR handles was broken, this fixes the issue seen during criu restore. Signed-off-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index c993657ebc806..2f10befe048ca 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2495,6 +2495,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, int idr_handle; int ret; const bool criu_resume = true; + unsigned int mem_type = 0; u64 offset; if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { @@ -2531,13 +2532,22 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, bo_bucket->size, bo_bucket->addr, offset); /* Restore previous IDR handle */ - pr_debug("Restoring old IDR handle for the BO"); - idr_handle = idr_alloc(&pdd->alloc_idr, *kgd_mem, bo_priv->idr_handle, - bo_priv->idr_handle + 1, GFP_KERNEL); + mem_type = bo_bucket->alloc_flags & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | + KFD_IOC_ALLOC_MEM_FLAGS_GTT | + KFD_IOC_ALLOC_MEM_FLAGS_USERPTR | + KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | + KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); + + idr_handle = kfd_process_device_create_obj_handle(pdd, *kgd_mem, + bo_bucket->addr, + bo_bucket->size, + 0, mem_type, + bo_priv->idr_handle); if (idr_handle < 0) { pr_err("Could not allocate idr\n"); - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, pdd->drm_priv, + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, + pdd->drm_priv, NULL); return -ENOMEM; } From 14e59f0c66f02ef07c1895d8103d3af86da5b8c9 Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Mon, 22 Aug 2022 12:17:43 -0400 Subject: [PATCH 0805/2653] drm/amdkfd: Fix some coding indentation Recently introduced patch to fix a criu regression due to a rebase, had some off indentation and extra newline. Fix that to stay close to the upstream version. Reviewed-by: Felix Kuehling Signed-off-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 2f10befe048ca..9fd864a25f88c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2536,7 +2536,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, KFD_IOC_ALLOC_MEM_FLAGS_GTT | KFD_IOC_ALLOC_MEM_FLAGS_USERPTR | KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | - KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); + KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); idr_handle = kfd_process_device_create_obj_handle(pdd, *kgd_mem, bo_bucket->addr, @@ -2546,8 +2546,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, if (idr_handle < 0) { pr_err("Could not allocate idr\n"); - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, - pdd->drm_priv, + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, pdd->drm_priv, NULL); return -ENOMEM; } From b405de007e1f0ae351e49f61fb03f60e6e9fb8c9 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 29 Jul 2022 16:20:27 +0800 Subject: [PATCH 0806/2653] drm/amdkcl: enable DRM_AMD_DC_DSC_SUPPORT by default v2: remove redundant check Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 6178008b48339..3b41a6d897f59 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -191,6 +191,9 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN endif endif +export CONFIG_DRM_AMD_DC_DSC_SUPPORT=y +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DSC_SUPPORT + export CONFIG_DRM_TTM_HELPER=m subdir-ccflags-y += -DCONFIG_DRM_TTM_HELPER CFLAGS_drm_gem_ttm_helper.o += -include $(src)/ttm/backport/backport.h \ From 67af66effce12c75df57e46ca06e2a8462e353c6 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 27 Jul 2022 10:54:21 +0800 Subject: [PATCH 0807/2653] drm/amdkcl: fake macro in drm/display/dsc_dp.h for legacy os v2: also include drm_dp_helper.h when drm_dp.h not exist v3: drop kcl_drm_dp.h and add some missing macros in kcl_drm_dp_helper.h for legacy os Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 1 + include/kcl/header/drm/display/drm_dp.h | 16 ++++++++++++++++ include/kcl/kcl_drm_dp_helper.h | 11 +++++++++++ 4 files changed, 31 insertions(+) create mode 100644 include/kcl/header/drm/display/drm_dp.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c3e1e5c202995..af7b76eb527ec 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -309,6 +309,9 @@ /* drm_dev_unplug() is available */ #define HAVE_DRM_DEV_UNPLUG 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DP_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DISPLAY_DRM_DP_HELPER_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 17fb837a138c4..b9977c77c0f81 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -79,6 +79,7 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdmi_helper.h]) AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdcp_helper.h]) AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdcp.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dp.h]) dnl # dnl # v5.7-13141-gca5999fde0a1 diff --git a/include/kcl/header/drm/display/drm_dp.h b/include/kcl/header/drm/display/drm_dp.h new file mode 100644 index 0000000000000..fc1cc1a4bac8e --- /dev/null +++ b/include/kcl/header/drm/display/drm_dp.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DP_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DP_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DP_H) +#include_next +#elif defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) +#include +#else +#include +#endif + +#endif + diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 43ddfa2ed899d..cecb273e97d8a 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -158,6 +158,17 @@ #define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED #endif +#ifndef DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED +# define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0 +# define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */ +#endif + +#ifndef DP_UHBR10 +# define DP_UHBR10 (1 << 0) +# define DP_UHBR20 (1 << 1) +# define DP_UHBR13_5 (1 << 2) +#endif + #ifndef DP_PHY_REPEATER_128B132B_RATES /* See DP_128B132B_SUPPORTED_LINK_RATES for values */ #define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */ From 45de5d3e71a6395b61a3bf64f712bdd2a124c392 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 27 Jul 2022 12:31:33 +0800 Subject: [PATCH 0808/2653] drm/amdkcl: define macro DRM_MODESET_ACQUIRE_INTERRUPTIBLE for legacy os v2: include Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_drm_modeset_lock.h | 12 ++++++++++++ 2 files changed, 13 insertions(+) create mode 100644 include/kcl/kcl_drm_modeset_lock.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 251fee9e35fca..8a8becd2a3d6f 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -96,5 +96,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_drm_modeset_lock.h b/include/kcl/kcl_drm_modeset_lock.h new file mode 100644 index 0000000000000..009e4af7a4c00 --- /dev/null +++ b/include/kcl/kcl_drm_modeset_lock.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_DRM_MODESET_LOCK_H_H_ +#define _KCL_KCL_DRM_MODESET_LOCK_H_H_ + +#include /* stackdepot.h is not self-contained */ +#include + +#ifndef DRM_MODESET_ACQUIRE_INTERRUPTIBLE +#define DRM_MODESET_ACQUIRE_INTERRUPTIBLE BIT(0) +#endif + +#endif From 0fcb5b683163bd5209bb912dd886a80dc01904fa Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 27 Jul 2022 14:42:09 +0800 Subject: [PATCH 0809/2653] drm/amdkcl: Test whether struct drm_dsc_config has member simple_422 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 4 ++++ drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 5 +++++ .../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 | 21 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 6 files changed, 36 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c index 427cd2301372d..72bb616c00405 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c @@ -290,7 +290,9 @@ void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *p DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth); DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable); DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb); +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 DC_LOG_DSC("\tsimple_422 %d", pps->simple_422); +#endif DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable); DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16); DC_LOG_DSC("\tpic_height %d", pps->pic_height); @@ -427,7 +429,9 @@ bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0; dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422); dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420); +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422); +#endif calc_rc_params(&rc, &dsc_reg_vals->pps); diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c index d61b6430a6409..1699a57ab7cb1 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c @@ -48,9 +48,14 @@ void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps) int slice_width = pps->slice_width; int slice_height = pps->slice_height; +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 mode = pps->convert_rgb ? CM_RGB : (pps->simple_422 ? CM_444 : (pps->native_422 ? CM_422 : pps->native_420 ? CM_420 : CM_444)); +#else + mode = pps->convert_rgb ? CM_RGB : (pps->native_422 ? CM_422 : + pps->native_420 ? CM_420 : CM_444); +#endif bpc = (pps->bits_per_component == 8) ? BPC_8 : (pps->bits_per_component == 10) ? BPC_10 : BPC_12; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c index b01295c412b1d..13fc27926468f 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c @@ -34,7 +34,9 @@ static void copy_pps_fields(struct drm_dsc_config *to, const struct drm_dsc_conf to->convert_rgb = from->convert_rgb; to->slice_width = from->slice_width; to->slice_height = from->slice_height; +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 to->simple_422 = from->simple_422; +#endif to->native_422 = from->native_422; to->native_420 = from->native_420; to->pic_width = from->pic_width; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index af7b76eb527ec..ee927932f1f36 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1249,6 +1249,9 @@ /* __dma_fence_is_later() is available and has ops arg */ #define HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG 1 +/* struct drm_dsc_config has member simple_422 */ +#define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 + /* drm_edid_get_monitor_name is available*/ #define HAVE_DRM_EDID_GET_MONITOR_NAME 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 new file mode 100644 index 0000000000000..c5c3c2c4418bb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v4.20-rc3-804-g19fd5adbb595 +dnl # drm/dsc: Define VESA Display Stream Compression Capabilities +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DSC_H) + #include + #else + #include + #endif + ], [ + struct drm_dsc_config *conf = NULL; + conf->simple_422 = true; + ], [ + AC_DEFINE(HAVE_DRM_DSC_CONFIG_SIMPLE_422, 1, + [struct drm_dsc_config has member simple_422]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 58fb6d56bfb77..9383aa8383200 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -208,6 +208,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE + AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From ce323555b8f84910570e7c1f1928d3187c88fd74 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 27 Jul 2022 17:06:15 +0800 Subject: [PATCH 0810/2653] drm/amdkcl: Test whether drm_dsc_pps_payload_pack() is available Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c | 203 ++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../amd/dkms/m4/drm_dsc_pps_payload_pack.m4 | 20 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_dsc_helper.h | 18 ++ 7 files changed, 247 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 create mode 100644 include/kcl/kcl_drm_dsc_helper.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index e9d5160622e08..8e3650b52cfc0 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o + kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c new file mode 100644 index 0000000000000..d54ef86bceaf4 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c @@ -0,0 +1,203 @@ +/** + * drm_dsc_pps_payload_pack() - Populates the DSC PPS + * + * @pps_payload: + * Bitwise struct for DSC Picture Parameter Set. This is defined + * by &struct drm_dsc_picture_parameter_set + * @dsc_cfg: + * DSC Configuration data filled by driver as defined by + * &struct drm_dsc_config + * + * DSC source device sends a picture parameter set (PPS) containing the + * information required by the sink to decode the compressed frame. Driver + * populates the DSC PPS struct using the DSC configuration parameters in + * the order expected by the DSC Display Sink device. For the DSC, the sink + * device expects the PPS payload in big endian format for fields + * that span more than 1 byte. + */ + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +#include +#include + +#ifndef HAVE_DRM_DSC_PPS_PAYLOAD_PACK +void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, + const struct drm_dsc_config *dsc_cfg) +{ + int i; + + /* Protect against someone accidentally changing struct size */ + BUILD_BUG_ON(sizeof(*pps_payload) != + DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1); + + memset(pps_payload, 0, sizeof(*pps_payload)); + + /* PPS 0 */ + pps_payload->dsc_version = + dsc_cfg->dsc_version_minor | + dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; + + /* PPS 1, 2 is 0 */ + + /* PPS 3 */ + pps_payload->pps_3 = + dsc_cfg->line_buf_depth | + dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT; + + /* PPS 4 */ + pps_payload->pps_4 = + ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> + DSC_PPS_MSB_SHIFT) | + dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 + dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT | +#endif + dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | + dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; + + /* PPS 5 */ + pps_payload->bits_per_pixel_low = + (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK); + + /* + * The DSC panel expects the PPS packet to have big endian format + * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert + * to big endian format. If format is little endian, it will swap + * bytes to convert to Big endian else keep it unchanged. + */ + + /* PPS 6, 7 */ + pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height); + + /* PPS 8, 9 */ + pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width); + + /* PPS 10, 11 */ + pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height); + + /* PPS 12, 13 */ + pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width); + + /* PPS 14, 15 */ + pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size); + + /* PPS 16 */ + pps_payload->initial_xmit_delay_high = + ((dsc_cfg->initial_xmit_delay & + DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >> + DSC_PPS_MSB_SHIFT); + + /* PPS 17 */ + pps_payload->initial_xmit_delay_low = + (dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK); + + /* PPS 18, 19 */ + pps_payload->initial_dec_delay = + cpu_to_be16(dsc_cfg->initial_dec_delay); + + /* PPS 20 is 0 */ + + /* PPS 21 */ + pps_payload->initial_scale_value = + dsc_cfg->initial_scale_value; + + /* PPS 22, 23 */ + pps_payload->scale_increment_interval = + cpu_to_be16(dsc_cfg->scale_increment_interval); + + /* PPS 24 */ + pps_payload->scale_decrement_interval_high = + ((dsc_cfg->scale_decrement_interval & + DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >> + DSC_PPS_MSB_SHIFT); + + /* PPS 25 */ + pps_payload->scale_decrement_interval_low = + (dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK); + + /* PPS 26[7:0], PPS 27[7:5] RESERVED */ + + /* PPS 27 */ + pps_payload->first_line_bpg_offset = + dsc_cfg->first_line_bpg_offset; + + /* PPS 28, 29 */ + pps_payload->nfl_bpg_offset = + cpu_to_be16(dsc_cfg->nfl_bpg_offset); + + /* PPS 30, 31 */ + pps_payload->slice_bpg_offset = + cpu_to_be16(dsc_cfg->slice_bpg_offset); + + /* PPS 32, 33 */ + pps_payload->initial_offset = + cpu_to_be16(dsc_cfg->initial_offset); + + /* PPS 34, 35 */ + pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset); + + /* PPS 36 */ + pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp; + + /* PPS 37 */ + pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp; + + /* PPS 38, 39 */ + pps_payload->rc_model_size = cpu_to_be16(dsc_cfg->rc_model_size); + + /* PPS 40 */ + pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST; + + /* PPS 41 */ + pps_payload->rc_quant_incr_limit0 = + dsc_cfg->rc_quant_incr_limit0; + + /* PPS 42 */ + pps_payload->rc_quant_incr_limit1 = + dsc_cfg->rc_quant_incr_limit1; + + /* PPS 43 */ + pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST | + DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT; + + /* PPS 44 - 57 */ + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) + pps_payload->rc_buf_thresh[i] = + dsc_cfg->rc_buf_thresh[i]; + + /* PPS 58 - 87 */ + /* + * For DSC sink programming the RC Range parameter fields + * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0] + */ + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { + pps_payload->rc_range_parameters[i] = + cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp << + DSC_PPS_RC_RANGE_MINQP_SHIFT) | + (dsc_cfg->rc_range_params[i].range_max_qp << + DSC_PPS_RC_RANGE_MAXQP_SHIFT) | + (dsc_cfg->rc_range_params[i].range_bpg_offset)); + } + + /* PPS 88 */ + pps_payload->native_422_420 = dsc_cfg->native_422 | + dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT; + + /* PPS 89 */ + pps_payload->second_line_bpg_offset = + dsc_cfg->second_line_bpg_offset; + + /* PPS 90, 91 */ + pps_payload->nsl_bpg_offset = + cpu_to_be16(dsc_cfg->nsl_bpg_offset); + + /* PPS 92, 93 */ + pps_payload->second_line_offset_adj = + cpu_to_be16(dsc_cfg->second_line_offset_adj); + + /* PPS 94 - 127 are O */ +} +EXPORT_SYMBOL(drm_dsc_pps_payload_pack); +#endif /* HAVE_DRM_DSC_PPS_PAYLOAD_PACK */ + +#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 8a8becd2a3d6f..e9b12c3982507 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -97,5 +97,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ee927932f1f36..11b55ef32140a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1252,6 +1252,9 @@ /* struct drm_dsc_config has member simple_422 */ #define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 +/* drm_dsc_pps_payload_pack() is available */ +#define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 + /* drm_edid_get_monitor_name is available*/ #define HAVE_DRM_EDID_GET_MONITOR_NAME 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 new file mode 100644 index 0000000000000..624e489e45e3a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit v5.18-rc2-597-g2a64b147350f +dnl # drm/display: Move DSC header and helpers into display-helper module +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) + #include + #else + #include + #endif + ], [ + drm_dsc_pps_payload_pack(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DSC_PPS_PAYLOAD_PACK, 1, + [drm_dsc_pps_payload_pack() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9383aa8383200..b44f42fa2fa90 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -209,6 +209,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 + AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_dsc_helper.h b/include/kcl/kcl_drm_dsc_helper.h new file mode 100644 index 0000000000000..d7b02f62b5ed1 --- /dev/null +++ b/include/kcl/kcl_drm_dsc_helper.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: MIT */ + +#ifndef _KCL_KCL_DRM_DSC_HELPER_H +#define _KCL_KCL_DRM_DSC_HELPER_H + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + +#include +#include + +#ifndef HAVE_DRM_DSC_PPS_PAYLOAD_PACK +void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, + const struct drm_dsc_config *dsc_cfg); +#endif + +#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ +#endif /* _KCL_KCL_DRM_DSC_HELPER_H */ + From 2310b53ca4e56a55b77f20ce7a7a630e8c4aef00 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 28 Jul 2022 11:09:19 +0800 Subject: [PATCH 0811/2653] drm/amdkcl: Test whether drm_dsc_compute_rc_parameters() is available Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- .../gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c | 134 +++++++++++++++++- drivers/gpu/drm/amd/dkms/config/config.h | 6 + .../dkms/m4/drm_dsc_compute_rc_parameters.m4 | 20 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_dsc_helper.h | 4 + 5 files changed, 164 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c index d54ef86bceaf4..f5546b4049608 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c @@ -15,9 +15,11 @@ * device expects the PPS payload in big endian format for fields * that span more than 1 byte. */ - #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + +#include #include +#include #include #ifndef HAVE_DRM_DSC_PPS_PAYLOAD_PACK @@ -200,4 +202,134 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, EXPORT_SYMBOL(drm_dsc_pps_payload_pack); #endif /* HAVE_DRM_DSC_PPS_PAYLOAD_PACK */ +#ifndef HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) +{ + unsigned long groups_per_line = 0; + unsigned long groups_total = 0; + unsigned long num_extra_mux_bits = 0; + unsigned long slice_bits = 0; + unsigned long hrd_delay = 0; + unsigned long final_scale = 0; + unsigned long rbs_min = 0; + + if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { + /* Number of groups used to code each line of a slice */ + groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2, + DSC_RC_PIXELS_PER_GROUP); + + /* chunksize in Bytes */ + vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * + vdsc_cfg->bits_per_pixel, + (8 * 16)); + } else { + /* Number of groups used to code each line of a slice */ + groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, + DSC_RC_PIXELS_PER_GROUP); + + /* chunksize in Bytes */ + vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * + vdsc_cfg->bits_per_pixel, + (8 * 16)); + } + + if (vdsc_cfg->convert_rgb) + num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + - 2); + else if (vdsc_cfg->native_422) + num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + + 3 * (4 * vdsc_cfg->bits_per_component) - 2; + else + num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + + 2 * (4 * vdsc_cfg->bits_per_component) - 2; + /* Number of bits in one Slice */ + slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; + + while ((num_extra_mux_bits > 0) && + ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size)) + num_extra_mux_bits--; + + if (groups_per_line < vdsc_cfg->initial_scale_value - 8) + vdsc_cfg->initial_scale_value = groups_per_line + 8; + + /* scale_decrement_interval calculation according to DSC spec 1.11 */ + if (vdsc_cfg->initial_scale_value > 8) + vdsc_cfg->scale_decrement_interval = groups_per_line / + (vdsc_cfg->initial_scale_value - 8); + else + vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX; + + vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - + (vdsc_cfg->initial_xmit_delay * + vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; + + if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { + DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n"); + return -ERANGE; + } + + final_scale = (vdsc_cfg->rc_model_size * 8) / + (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); + if (vdsc_cfg->slice_height > 1) + /* + * NflBpgOffset is 16 bit value with 11 fractional bits + * hence we multiply by 2^11 for preserving the + * fractional part + */ + vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), + (vdsc_cfg->slice_height - 1)); + else + vdsc_cfg->nfl_bpg_offset = 0; + + /* Number of groups used to code the entire slice */ + groups_total = groups_per_line * vdsc_cfg->slice_height; + + /* slice_bpg_offset is 16 bit value with 11 fractional bits */ + vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - + vdsc_cfg->initial_offset + + num_extra_mux_bits) << 11), + groups_total); + + if (final_scale > 9) { + /* + * ScaleIncrementInterval = + * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125)) + * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value, + * we need divide by 2^11 from pstDscCfg values + */ + vdsc_cfg->scale_increment_interval = + (vdsc_cfg->final_offset * (1 << 11)) / + ((vdsc_cfg->nfl_bpg_offset + + vdsc_cfg->slice_bpg_offset) * + (final_scale - 9)); + } else { + /* + * If finalScaleValue is less than or equal to 9, a value of 0 should + * be used to disable the scale increment at the end of the slice + */ + vdsc_cfg->scale_increment_interval = 0; + } + + /* + * DSC spec mentions that bits_per_pixel specifies the target + * bits/pixel (bpp) rate that is used by the encoder, + * in steps of 1/16 of a bit per pixel + */ + rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + + DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * + vdsc_cfg->bits_per_pixel, 16) + + groups_per_line * vdsc_cfg->first_line_bpg_offset; + + hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); + vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; + vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; + + return 0; +} +EXPORT_SYMBOL(drm_dsc_compute_rc_parameters); +#endif /* HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS */ + #endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 11b55ef32140a..4d4822ada9873 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -529,6 +529,12 @@ /* drm_gem_prime_export() with p,i arg is available */ #define HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI 1 +/* drm_drv_uses_atomic_modeset() is available */ +#define HAVE_DRM_DRV_USES_ATOMIC_MODESET 1 + +/* drm_dsc_compute_rc_parameters() is available */ +#define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 + /* drm_edid_to_eld() are available */ /* #undef HAVE_DRM_EDID_TO_ELD */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 new file mode 100644 index 0000000000000..57d179067d66b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit v5.18-rc2-597-g2a64b147350f +dnl # drm/display: Move DSC header and helpers into display-helper module +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) + #include + #else + #include + #endif + ], [ + drm_dsc_compute_rc_parameters(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS, 1, + [drm_dsc_compute_rc_parameters() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b44f42fa2fa90..9554606a9f9f5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -210,6 +210,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK + AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_dsc_helper.h b/include/kcl/kcl_drm_dsc_helper.h index d7b02f62b5ed1..207bc76eb1195 100644 --- a/include/kcl/kcl_drm_dsc_helper.h +++ b/include/kcl/kcl_drm_dsc_helper.h @@ -13,6 +13,10 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, const struct drm_dsc_config *dsc_cfg); #endif +#ifndef HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); +#endif + #endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ #endif /* _KCL_KCL_DRM_DSC_HELPER_H */ From 64088f3e784e907b376017360ccad1c607829e65 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 28 Jul 2022 13:00:10 +0800 Subject: [PATCH 0812/2653] drm/amdkcl: adjust macro to fix build error Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2b0043316836e..8ef6ec97c09fb 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12408,6 +12408,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; } +#ifdef HAVE_DRM_DP_MST_ATOMIC_CHECK #if defined(CONFIG_DRM_AMD_DC_FP) if (dc_resource_is_dsc_encoding_supported(dc)) { ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); @@ -12418,6 +12419,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } #endif +#endif #if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index e0fd4f4b6b64c..044739fddd054 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -269,7 +269,6 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { }; #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) -#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) bool needs_dsc_aux_workaround(struct dc_link *link) { if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && @@ -296,6 +295,7 @@ static bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_m return false; } +#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector) { struct dc_sink *dc_sink = aconnector->dc_sink; From 5225b077a1cc5387aab5292604ed8b9d599de7bb Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 28 Jul 2022 13:00:43 +0800 Subject: [PATCH 0813/2653] drm/amdkcl: remove useless macro wrapper Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Change-Id: Id09116daf768f3e17026e6db0826dbfb7bc179ee --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8ef6ec97c09fb..26550d5c60e2c 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8024,7 +8024,6 @@ static void dm_encoder_helper_disable(struct drm_encoder *encoder) } -#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) { switch (display_color_depth) { @@ -8045,7 +8044,7 @@ int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) } return 0; } -#endif + static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) From 28c4a0f51771cd9ea4058d1ba3ba78e2dd73c146 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 28 Jul 2022 13:54:31 +0800 Subject: [PATCH 0814/2653] drm/amdkcl: fix unused variable warning Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 26550d5c60e2c..55fbfcaf53799 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12027,7 +12027,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, bool is_top_most_overlay = true; struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS struct drm_dp_mst_topology_mgr *mgr; +#endif struct drm_dp_mst_topology_state *mst_state; struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; #endif From c724feaf4a4e76e28a59763d8dadc1890694df4e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 24 Aug 2022 11:35:44 +0800 Subject: [PATCH 0815/2653] drm/amdkcl: Check if drm_buddy.h is exist Signed-off-by: Ma Jun Change-Id: I0981cffaa5da7fcd75273e8adc09051bb966037e --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4d4822ada9873..c90e5e61b257e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -511,6 +511,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_BUDDY_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_UTIL_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index b9977c77c0f81..055736d17b86a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -86,4 +86,10 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # mm: introduce include/linux/pgtable.h dnl # AC_KERNEL_CHECK_HEADERS([linux/pgtable.h]) + + dnl # + dnl # v5.19-rc1- c9cad937c0 + dnl # drm/amdgpu: add drm buddy support to amdgpu + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_buddy.h]) ]) From c78d13b37da7fe16b0f7bba0a142384c58cf309e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 24 Aug 2022 16:01:56 +0800 Subject: [PATCH 0816/2653] drm/amdkcl: Add the drm buddy support for legacy os Signed-off-by: Ma Jun Change-Id: Ide9f05c3cdb024ba06fb70c12f72eb105af23118 --- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h | 1 - drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c | 783 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 11 + drivers/gpu/drm/amd/backport/backport.h | 2 +- include/kcl/header/drm/drm_buddy.h | 11 + include/kcl/kcl_drm_buddy.h | 161 ++++ 7 files changed, 968 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c create mode 100644 include/kcl/header/drm/drm_buddy.h create mode 100644 include/kcl/kcl_drm_buddy.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h index 5f5fd9a911c26..1613841246b2e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h @@ -25,7 +25,6 @@ #define __AMDGPU_VRAM_MGR_H__ #include - struct amdgpu_vram_mgr { struct ttm_resource_manager manager; struct drm_buddy mm; diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 8e3650b52cfc0..0104acd2fd133 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o + kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_drm_buddy.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c new file mode 100644 index 0000000000000..b8e89facbadd0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c @@ -0,0 +1,783 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2021 Intel Corporation + */ + +#include +#ifndef HAVE_DRM_DRM_BUDDY_H + +#include + +static struct kmem_cache *slab_blocks; + +static struct drm_buddy_block *drm_block_alloc(struct drm_buddy *mm, + struct drm_buddy_block *parent, + unsigned int order, + u64 offset) +{ + struct drm_buddy_block *block; + + BUG_ON(order > DRM_BUDDY_MAX_ORDER); + + block = kmem_cache_zalloc(slab_blocks, GFP_KERNEL); + if (!block) + return NULL; + + block->header = offset; + block->header |= order; + block->parent = parent; + + BUG_ON(block->header & DRM_BUDDY_HEADER_UNUSED); + return block; +} + +static void drm_block_free(struct drm_buddy *mm, + struct drm_buddy_block *block) +{ + kmem_cache_free(slab_blocks, block); +} + +static void mark_allocated(struct drm_buddy_block *block) +{ + block->header &= ~DRM_BUDDY_HEADER_STATE; + block->header |= DRM_BUDDY_ALLOCATED; + + list_del(&block->link); +} + +static void mark_free(struct drm_buddy *mm, + struct drm_buddy_block *block) +{ + block->header &= ~DRM_BUDDY_HEADER_STATE; + block->header |= DRM_BUDDY_FREE; + + list_add(&block->link, + &mm->free_list[drm_buddy_block_order(block)]); +} + +static void mark_split(struct drm_buddy_block *block) +{ + block->header &= ~DRM_BUDDY_HEADER_STATE; + block->header |= DRM_BUDDY_SPLIT; + + list_del(&block->link); +} + +/** + * drm_buddy_init - init memory manager + * + * @mm: DRM buddy manager to initialize + * @size: size in bytes to manage + * @chunk_size: minimum page size in bytes for our allocations + * + * Initializes the memory manager and its resources. + * + * Returns: + * 0 on success, error code on failure. + */ +int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) +{ + unsigned int i; + u64 offset; + + if (size < chunk_size) + return -EINVAL; + + if (chunk_size < PAGE_SIZE) + return -EINVAL; + + if (!is_power_of_2(chunk_size)) + return -EINVAL; + + size = round_down(size, chunk_size); + + mm->size = size; + mm->avail = size; + mm->chunk_size = chunk_size; + mm->max_order = ilog2(size) - ilog2(chunk_size); + + BUG_ON(mm->max_order > DRM_BUDDY_MAX_ORDER); + + mm->free_list = kmalloc_array(mm->max_order + 1, + sizeof(struct list_head), + GFP_KERNEL); + if (!mm->free_list) + return -ENOMEM; + + for (i = 0; i <= mm->max_order; ++i) + INIT_LIST_HEAD(&mm->free_list[i]); + + mm->n_roots = hweight64(size); + + mm->roots = kmalloc_array(mm->n_roots, + sizeof(struct drm_buddy_block *), + GFP_KERNEL); + if (!mm->roots) + goto out_free_list; + + offset = 0; + i = 0; + + /* + * Split into power-of-two blocks, in case we are given a size that is + * not itself a power-of-two. + */ + do { + struct drm_buddy_block *root; + unsigned int order; + u64 root_size; + + root_size = rounddown_pow_of_two(size); + order = ilog2(root_size) - ilog2(chunk_size); + + root = drm_block_alloc(mm, NULL, order, offset); + if (!root) + goto out_free_roots; + + mark_free(mm, root); + + BUG_ON(i > mm->max_order); + BUG_ON(drm_buddy_block_size(mm, root) < chunk_size); + + mm->roots[i] = root; + + offset += root_size; + size -= root_size; + i++; + } while (size); + + return 0; + +out_free_roots: + while (i--) + drm_block_free(mm, mm->roots[i]); + kfree(mm->roots); +out_free_list: + kfree(mm->free_list); + return -ENOMEM; +} +EXPORT_SYMBOL(drm_buddy_init); + +/** + * drm_buddy_fini - tear down the memory manager + * + * @mm: DRM buddy manager to free + * + * Cleanup memory manager resources and the freelist + */ +void drm_buddy_fini(struct drm_buddy *mm) +{ + int i; + + for (i = 0; i < mm->n_roots; ++i) { + WARN_ON(!drm_buddy_block_is_free(mm->roots[i])); + drm_block_free(mm, mm->roots[i]); + } + + WARN_ON(mm->avail != mm->size); + + kfree(mm->roots); + kfree(mm->free_list); +} +EXPORT_SYMBOL(drm_buddy_fini); + +static int split_block(struct drm_buddy *mm, + struct drm_buddy_block *block) +{ + unsigned int block_order = drm_buddy_block_order(block) - 1; + u64 offset = drm_buddy_block_offset(block); + + BUG_ON(!drm_buddy_block_is_free(block)); + BUG_ON(!drm_buddy_block_order(block)); + + block->left = drm_block_alloc(mm, block, block_order, offset); + if (!block->left) + return -ENOMEM; + + block->right = drm_block_alloc(mm, block, block_order, + offset + (mm->chunk_size << block_order)); + if (!block->right) { + drm_block_free(mm, block->left); + return -ENOMEM; + } + + mark_free(mm, block->left); + mark_free(mm, block->right); + + mark_split(block); + + return 0; +} + +static struct drm_buddy_block * +__get_buddy(struct drm_buddy_block *block) +{ + struct drm_buddy_block *parent; + + parent = block->parent; + if (!parent) + return NULL; + + if (parent->left == block) + return parent->right; + + return parent->left; +} + +/** + * drm_get_buddy - get buddy address + * + * @block: DRM buddy block + * + * Returns the corresponding buddy block for @block, or NULL + * if this is a root block and can't be merged further. + * Requires some kind of locking to protect against + * any concurrent allocate and free operations. + */ +struct drm_buddy_block * +drm_get_buddy(struct drm_buddy_block *block) +{ + return __get_buddy(block); +} +EXPORT_SYMBOL(drm_get_buddy); + +static void __drm_buddy_free(struct drm_buddy *mm, + struct drm_buddy_block *block) +{ + struct drm_buddy_block *parent; + + while ((parent = block->parent)) { + struct drm_buddy_block *buddy; + + buddy = __get_buddy(block); + + if (!drm_buddy_block_is_free(buddy)) + break; + + list_del(&buddy->link); + + drm_block_free(mm, block); + drm_block_free(mm, buddy); + + block = parent; + } + + mark_free(mm, block); +} + +/** + * drm_buddy_free_block - free a block + * + * @mm: DRM buddy manager + * @block: block to be freed + */ +void drm_buddy_free_block(struct drm_buddy *mm, + struct drm_buddy_block *block) +{ + BUG_ON(!drm_buddy_block_is_allocated(block)); + mm->avail += drm_buddy_block_size(mm, block); + __drm_buddy_free(mm, block); +} +EXPORT_SYMBOL(drm_buddy_free_block); + +/** + * drm_buddy_free_list - free blocks + * + * @mm: DRM buddy manager + * @objects: input list head to free blocks + */ +void drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects) +{ + struct drm_buddy_block *block, *on; + + list_for_each_entry_safe(block, on, objects, link) { + drm_buddy_free_block(mm, block); + cond_resched(); + } + INIT_LIST_HEAD(objects); +} +EXPORT_SYMBOL(drm_buddy_free_list); + +static inline bool overlaps(u64 s1, u64 e1, u64 s2, u64 e2) +{ + return s1 <= e2 && e1 >= s2; +} + +static inline bool contains(u64 s1, u64 e1, u64 s2, u64 e2) +{ + return s1 <= s2 && e1 >= e2; +} + +static struct drm_buddy_block * +alloc_range_bias(struct drm_buddy *mm, + u64 start, u64 end, + unsigned int order) +{ + struct drm_buddy_block *block; + struct drm_buddy_block *buddy; + LIST_HEAD(dfs); + int err; + int i; + + end = end - 1; + + for (i = 0; i < mm->n_roots; ++i) + list_add_tail(&mm->roots[i]->tmp_link, &dfs); + + do { + u64 block_start; + u64 block_end; + + block = list_first_entry_or_null(&dfs, + struct drm_buddy_block, + tmp_link); + if (!block) + break; + + list_del(&block->tmp_link); + + if (drm_buddy_block_order(block) < order) + continue; + + block_start = drm_buddy_block_offset(block); + block_end = block_start + drm_buddy_block_size(mm, block) - 1; + + if (!overlaps(start, end, block_start, block_end)) + continue; + + if (drm_buddy_block_is_allocated(block)) + continue; + + if (contains(start, end, block_start, block_end) && + order == drm_buddy_block_order(block)) { + /* + * Find the free block within the range. + */ + if (drm_buddy_block_is_free(block)) + return block; + + continue; + } + + if (!drm_buddy_block_is_split(block)) { + err = split_block(mm, block); + if (unlikely(err)) + goto err_undo; + } + + list_add(&block->right->tmp_link, &dfs); + list_add(&block->left->tmp_link, &dfs); + } while (1); + + return ERR_PTR(-ENOSPC); + +err_undo: + /* + * We really don't want to leave around a bunch of split blocks, since + * bigger is better, so make sure we merge everything back before we + * free the allocated blocks. + */ + buddy = __get_buddy(block); + if (buddy && + (drm_buddy_block_is_free(block) && + drm_buddy_block_is_free(buddy))) + __drm_buddy_free(mm, block); + return ERR_PTR(err); +} + +static struct drm_buddy_block * +get_maxblock(struct list_head *head) +{ + struct drm_buddy_block *max_block = NULL, *node; + + max_block = list_first_entry_or_null(head, + struct drm_buddy_block, + link); + if (!max_block) + return NULL; + + list_for_each_entry(node, head, link) { + if (drm_buddy_block_offset(node) > + drm_buddy_block_offset(max_block)) + max_block = node; + } + + return max_block; +} + +static struct drm_buddy_block * +alloc_from_freelist(struct drm_buddy *mm, + unsigned int order, + unsigned long flags) +{ + struct drm_buddy_block *block = NULL; + unsigned int i; + int err; + + for (i = order; i <= mm->max_order; ++i) { + if (flags & DRM_BUDDY_TOPDOWN_ALLOCATION) { + block = get_maxblock(&mm->free_list[i]); + if (block) + break; + } else { + block = list_first_entry_or_null(&mm->free_list[i], + struct drm_buddy_block, + link); + if (block) + break; + } + } + + if (!block) + return ERR_PTR(-ENOSPC); + + BUG_ON(!drm_buddy_block_is_free(block)); + + while (i != order) { + err = split_block(mm, block); + if (unlikely(err)) + goto err_undo; + + block = block->right; + i--; + } + return block; + +err_undo: + if (i != order) + __drm_buddy_free(mm, block); + return ERR_PTR(err); +} + +static int __alloc_range(struct drm_buddy *mm, + struct list_head *dfs, + u64 start, u64 size, + struct list_head *blocks) +{ + struct drm_buddy_block *block; + struct drm_buddy_block *buddy; + LIST_HEAD(allocated); + u64 end; + int err; + + end = start + size - 1; + + do { + u64 block_start; + u64 block_end; + + block = list_first_entry_or_null(dfs, + struct drm_buddy_block, + tmp_link); + if (!block) + break; + + list_del(&block->tmp_link); + + block_start = drm_buddy_block_offset(block); + block_end = block_start + drm_buddy_block_size(mm, block) - 1; + + if (!overlaps(start, end, block_start, block_end)) + continue; + + if (drm_buddy_block_is_allocated(block)) { + err = -ENOSPC; + goto err_free; + } + + if (contains(start, end, block_start, block_end)) { + if (!drm_buddy_block_is_free(block)) { + err = -ENOSPC; + goto err_free; + } + + mark_allocated(block); + mm->avail -= drm_buddy_block_size(mm, block); + list_add_tail(&block->link, &allocated); + continue; + } + + if (!drm_buddy_block_is_split(block)) { + err = split_block(mm, block); + if (unlikely(err)) + goto err_undo; + } + + list_add(&block->right->tmp_link, dfs); + list_add(&block->left->tmp_link, dfs); + } while (1); + + list_splice_tail(&allocated, blocks); + return 0; + +err_undo: + /* + * We really don't want to leave around a bunch of split blocks, since + * bigger is better, so make sure we merge everything back before we + * free the allocated blocks. + */ + buddy = __get_buddy(block); + if (buddy && + (drm_buddy_block_is_free(block) && + drm_buddy_block_is_free(buddy))) + __drm_buddy_free(mm, block); + +err_free: + drm_buddy_free_list(mm, &allocated); + return err; +} + +static int __drm_buddy_alloc_range(struct drm_buddy *mm, + u64 start, + u64 size, + struct list_head *blocks) +{ + LIST_HEAD(dfs); + int i; + + for (i = 0; i < mm->n_roots; ++i) + list_add_tail(&mm->roots[i]->tmp_link, &dfs); + + return __alloc_range(mm, &dfs, start, size, blocks); +} + +/** + * drm_buddy_block_trim - free unused pages + * + * @mm: DRM buddy manager + * @new_size: original size requested + * @blocks: Input and output list of allocated blocks. + * MUST contain single block as input to be trimmed. + * On success will contain the newly allocated blocks + * making up the @new_size. Blocks always appear in + * ascending order + * + * For contiguous allocation, we round up the size to the nearest + * power of two value, drivers consume *actual* size, so remaining + * portions are unused and can be optionally freed with this function + * + * Returns: + * 0 on success, error code on failure. + */ +int drm_buddy_block_trim(struct drm_buddy *mm, + u64 new_size, + struct list_head *blocks) +{ + struct drm_buddy_block *parent; + struct drm_buddy_block *block; + LIST_HEAD(dfs); + u64 new_start; + int err; + + if (!list_is_singular(blocks)) + return -EINVAL; + + block = list_first_entry(blocks, + struct drm_buddy_block, + link); + + if (WARN_ON(!drm_buddy_block_is_allocated(block))) + return -EINVAL; + + if (new_size > drm_buddy_block_size(mm, block)) + return -EINVAL; + + if (!new_size || !IS_ALIGNED(new_size, mm->chunk_size)) + return -EINVAL; + + if (new_size == drm_buddy_block_size(mm, block)) + return 0; + + list_del(&block->link); + mark_free(mm, block); + mm->avail += drm_buddy_block_size(mm, block); + + /* Prevent recursively freeing this node */ + parent = block->parent; + block->parent = NULL; + + new_start = drm_buddy_block_offset(block); + list_add(&block->tmp_link, &dfs); + err = __alloc_range(mm, &dfs, new_start, new_size, blocks); + if (err) { + mark_allocated(block); + mm->avail -= drm_buddy_block_size(mm, block); + list_add(&block->link, blocks); + } + + block->parent = parent; + return err; +} +EXPORT_SYMBOL(drm_buddy_block_trim); + +/** + * drm_buddy_alloc_blocks - allocate power-of-two blocks + * + * @mm: DRM buddy manager to allocate from + * @start: start of the allowed range for this block + * @end: end of the allowed range for this block + * @size: size of the allocation + * @min_page_size: alignment of the allocation + * @blocks: output list head to add allocated blocks + * @flags: DRM_BUDDY_*_ALLOCATION flags + * + * alloc_range_bias() called on range limitations, which traverses + * the tree and returns the desired block. + * + * alloc_from_freelist() called when *no* range restrictions + * are enforced, which picks the block from the freelist. + * + * Returns: + * 0 on success, error code on failure. + */ +int drm_buddy_alloc_blocks(struct drm_buddy *mm, + u64 start, u64 end, u64 size, + u64 min_page_size, + struct list_head *blocks, + unsigned long flags) +{ + struct drm_buddy_block *block = NULL; + unsigned int min_order, order; + unsigned long pages; + LIST_HEAD(allocated); + int err; + + if (size < mm->chunk_size) + return -EINVAL; + + if (min_page_size < mm->chunk_size) + return -EINVAL; + + if (!is_power_of_2(min_page_size)) + return -EINVAL; + + if (!IS_ALIGNED(start | end | size, mm->chunk_size)) + return -EINVAL; + + if (end > mm->size) + return -EINVAL; + + if (range_overflows(start, size, mm->size)) + return -EINVAL; + + /* Actual range allocation */ + if (start + size == end) + return __drm_buddy_alloc_range(mm, start, size, blocks); + + if (!IS_ALIGNED(size, min_page_size)) + return -EINVAL; + + pages = size >> ilog2(mm->chunk_size); + order = fls(pages) - 1; + min_order = ilog2(min_page_size) - ilog2(mm->chunk_size); + + do { + order = min(order, (unsigned int)fls(pages) - 1); + BUG_ON(order > mm->max_order); + BUG_ON(order < min_order); + + do { + if (flags & DRM_BUDDY_RANGE_ALLOCATION) + /* Allocate traversing within the range */ + block = alloc_range_bias(mm, start, end, order); + else + /* Allocate from freelist */ + block = alloc_from_freelist(mm, order, flags); + + if (!IS_ERR(block)) + break; + + if (order-- == min_order) { + err = -ENOSPC; + goto err_free; + } + } while (1); + + mark_allocated(block); + mm->avail -= drm_buddy_block_size(mm, block); + //kmemleak_update_trace(block); + list_add_tail(&block->link, &allocated); + + pages -= BIT(order); + + if (!pages) + break; + } while (1); + + list_splice_tail(&allocated, blocks); + return 0; + +err_free: + drm_buddy_free_list(mm, &allocated); + return err; +} +EXPORT_SYMBOL(drm_buddy_alloc_blocks); + +/** + * drm_buddy_block_print - print block information + * + * @mm: DRM buddy manager + * @block: DRM buddy block + * @p: DRM printer to use + */ +void drm_buddy_block_print(struct drm_buddy *mm, + struct drm_buddy_block *block, + struct drm_printer *p) +{ + u64 start = drm_buddy_block_offset(block); + u64 size = drm_buddy_block_size(mm, block); + + drm_printf(p, "%#018llx-%#018llx: %llu\n", start, start + size, size); +} +EXPORT_SYMBOL(drm_buddy_block_print); + +/** + * drm_buddy_print - print allocator state + * + * @mm: DRM buddy manager + * @p: DRM printer to use + */ +void drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p) +{ + int order; + + drm_printf(p, "chunk_size: %lluKiB, total: %lluMiB, free: %lluMiB\n", + mm->chunk_size >> 10, mm->size >> 20, mm->avail >> 20); + + for (order = mm->max_order; order >= 0; order--) { + struct drm_buddy_block *block; + u64 count = 0, free; + + list_for_each_entry(block, &mm->free_list[order], link) { + BUG_ON(!drm_buddy_block_is_free(block)); + count++; + } + + drm_printf(p, "order-%d ", order); + + free = count * (mm->chunk_size << order); + if (free < SZ_1M) + drm_printf(p, "free: %lluKiB", free >> 10); + else + drm_printf(p, "free: %lluMiB", free >> 20); + + drm_printf(p, ", pages: %llu\n", count); + } +} +EXPORT_SYMBOL(drm_buddy_print); + +void amdkcl_drm_buddy_module_exit(void) +{ + kmem_cache_destroy(slab_blocks); +} + +int amdkcl_drm_buddy_module_init(void) +{ + slab_blocks = KMEM_CACHE(drm_buddy_block, 0); + if (!slab_blocks) + return -ENOMEM; + + return 0; +} + +#endif /* HAVE_DRM_DRM_BUDDY_H */ \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index bd158234c6db0..a98196918c9f9 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -16,6 +16,11 @@ extern void amdkcl_sched_init(void); extern void amdkcl_numa_init(void); extern void amdkcl_workqueue_init(void); +#ifndef HAVE_DRM_DRM_BUDDY_H +extern int amdkcl_drm_buddy_module_init(void); +extern void amdkcl_drm_buddy_module_exit(void); +#endif + int __init amdkcl_init(void) { amdkcl_symbol_init(); @@ -31,6 +36,9 @@ int __init amdkcl_init(void) amdkcl_sched_init(); amdkcl_numa_init(); amdkcl_workqueue_init(); +#ifndef HAVE_DRM_DRM_BUDDY_H + amdkcl_drm_buddy_module_init(); +#endif return 0; } @@ -38,6 +46,9 @@ module_init(amdkcl_init); void __exit amdkcl_exit(void) { +#ifndef HAVE_DRM_DRM_BUDDY_H + amdkcl_drm_buddy_module_exit(); +#endif } module_exit(amdkcl_exit); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e9b12c3982507..fe458b9b1f4cc 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -98,5 +98,5 @@ #include #include #include - +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/header/drm/drm_buddy.h b/include/kcl/header/drm/drm_buddy.h new file mode 100644 index 0000000000000..37aa64b07a8e6 --- /dev/null +++ b/include/kcl/header/drm/drm_buddy.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_BUDDY_H_H_ +#define _KCL_HEADER_DRM_BUDDY_H_H_ + +#ifdef HAVE_DRM_DRM_BUDDY_H +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/kcl_drm_buddy.h b/include/kcl/kcl_drm_buddy.h new file mode 100644 index 0000000000000..5f13318751887 --- /dev/null +++ b/include/kcl/kcl_drm_buddy.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2021 Intel Corporation + */ +#ifndef __KCL_KCL_DRM_BUDDY_H__ +#define __KCL_KCL_DRM_BUDDY_H__ + +#ifdef HAVE_DRM_DRM_BUDDY_H +#include +#else +#include +#include +#include +#include +#include + +#define range_overflows(start, size, max) ({ \ + typeof(start) start__ = (start); \ + typeof(size) size__ = (size); \ + typeof(max) max__ = (max); \ + (void)(&start__ == &size__); \ + (void)(&start__ == &max__); \ + start__ >= max__ || size__ > max__ - start__; \ +}) + +#define DRM_BUDDY_RANGE_ALLOCATION (1 << 0) +#define DRM_BUDDY_TOPDOWN_ALLOCATION (1 << 1) + +struct drm_buddy_block { +#define DRM_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12) +#define DRM_BUDDY_HEADER_STATE GENMASK_ULL(11, 10) +#define DRM_BUDDY_ALLOCATED (1 << 10) +#define DRM_BUDDY_FREE (2 << 10) +#define DRM_BUDDY_SPLIT (3 << 10) +/* Free to be used, if needed in the future */ +#define DRM_BUDDY_HEADER_UNUSED GENMASK_ULL(9, 6) +#define DRM_BUDDY_HEADER_ORDER GENMASK_ULL(5, 0) + u64 header; + + struct drm_buddy_block *left; + struct drm_buddy_block *right; + struct drm_buddy_block *parent; + + void *private; /* owned by creator */ + + /* + * While the block is allocated by the user through drm_buddy_alloc*, + * the user has ownership of the link, for example to maintain within + * a list, if so desired. As soon as the block is freed with + * drm_buddy_free* ownership is given back to the mm. + */ + struct list_head link; + struct list_head tmp_link; +}; + +/* Order-zero must be at least PAGE_SIZE */ +#define DRM_BUDDY_MAX_ORDER (63 - PAGE_SHIFT) + +/* + * Binary Buddy System. + * + * Locking should be handled by the user, a simple mutex around + * drm_buddy_alloc* and drm_buddy_free* should suffice. + */ +struct drm_buddy { + /* Maintain a free list for each order. */ + struct list_head *free_list; + + /* + * Maintain explicit binary tree(s) to track the allocation of the + * address space. This gives us a simple way of finding a buddy block + * and performing the potentially recursive merge step when freeing a + * block. Nodes are either allocated or free, in which case they will + * also exist on the respective free list. + */ + struct drm_buddy_block **roots; + + /* + * Anything from here is public, and remains static for the lifetime of + * the mm. Everything above is considered do-not-touch. + */ + unsigned int n_roots; + unsigned int max_order; + + /* Must be at least PAGE_SIZE */ + u64 chunk_size; + u64 size; + u64 avail; +}; + +static inline u64 +drm_buddy_block_offset(struct drm_buddy_block *block) +{ + return block->header & DRM_BUDDY_HEADER_OFFSET; +} + +static inline unsigned int +drm_buddy_block_order(struct drm_buddy_block *block) +{ + return block->header & DRM_BUDDY_HEADER_ORDER; +} + +static inline unsigned int +drm_buddy_block_state(struct drm_buddy_block *block) +{ + return block->header & DRM_BUDDY_HEADER_STATE; +} + +static inline bool +drm_buddy_block_is_allocated(struct drm_buddy_block *block) +{ + return drm_buddy_block_state(block) == DRM_BUDDY_ALLOCATED; +} + +static inline bool +drm_buddy_block_is_free(struct drm_buddy_block *block) +{ + return drm_buddy_block_state(block) == DRM_BUDDY_FREE; +} + +static inline bool +drm_buddy_block_is_split(struct drm_buddy_block *block) +{ + return drm_buddy_block_state(block) == DRM_BUDDY_SPLIT; +} + +static inline u64 +drm_buddy_block_size(struct drm_buddy *mm, + struct drm_buddy_block *block) +{ + return mm->chunk_size << drm_buddy_block_order(block); +} + +int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size); + +void drm_buddy_fini(struct drm_buddy *mm); + +struct drm_buddy_block * +drm_get_buddy(struct drm_buddy_block *block); + +int drm_buddy_alloc_blocks(struct drm_buddy *mm, + u64 start, u64 end, u64 size, + u64 min_page_size, + struct list_head *blocks, + unsigned long flags); + +int drm_buddy_block_trim(struct drm_buddy *mm, + u64 new_size, + struct list_head *blocks); + +void drm_buddy_free_block(struct drm_buddy *mm, struct drm_buddy_block *block); + +void drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects); + +void drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p); +void drm_buddy_block_print(struct drm_buddy *mm, + struct drm_buddy_block *block, + struct drm_printer *p); + +#endif /* HAVE_DRM_DRM_BUDDY_H */ +#endif /* __KCL_KCL_DRM_BUDDY_H__ */ From e337cb944ff5700bfe525da3bd043e129fcc5f31 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 25 Aug 2022 09:43:28 +0800 Subject: [PATCH 0817/2653] drm/amdkcl: Remove the redundant reference of header file Signed-off-by: Ma Jun Change-Id: I257d7940e5770ce5399d72039ab47328cc3b105b --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 55fbfcaf53799..3e61ada6364da 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -94,7 +94,6 @@ #include #include #include -#include #include #include From b2aeac61e1d64140cc57f4a7092fa289fe37ec3d Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 25 Aug 2022 10:04:40 +0800 Subject: [PATCH 0818/2653] drm/amdkcl: Test if drm_gem_plane_helper_prepare_fb() is defined Signed-off-by: Ma Jun Change-Id: Ie8eee916043ff4e7a52a256f548d6b89782259bc --- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 4 ++++ .../dkms/m4/drm_gem_plane_helper_prepare_fb.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/header/drm/drm_gem_atomic_helper.h | 9 +++++++++ 5 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_gem_plane_helper_prepare_fb.m4 create mode 100644 include/kcl/header/drm/drm_gem_atomic_helper.h diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 58166f2fed938..eff18cae894bd 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -999,9 +999,11 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane, goto error_unpin; } +#ifdef HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB r = drm_gem_plane_helper_prepare_fb(plane, new_state); if (unlikely(r != 0)) goto error_unpin; +#endif amdgpu_bo_unreserve(rbo); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c90e5e61b257e..1ac18b80aa28f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -575,6 +575,10 @@ /* whether struct drm_framebuffer have format */ #define HAVE_DRM_FRAMEBUFFER_FORMAT 1 + + /* drm_gem_plane_helper_prepare_fb() is available */ + #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 + /* drm_gem_map_attach() wants 2 arguments */ /* #undef HAVE_DRM_GEM_MAP_ATTACH_2ARGS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_gem_plane_helper_prepare_fb.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_gem_plane_helper_prepare_fb.m4 new file mode 100644 index 0000000000000..e0311f6ebd145 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_gem_plane_helper_prepare_fb.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 96d4f267e40f9509e8a66e2b39e8b95655617693 +dnl # Author: Linus Torvalds +dnl # Date: Thu Jan 3 18:57:57 2019 -0800 +dnl # Remove 'type' argument from access_ok() function +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_gem_plane_helper_prepare_fb(NULL, NULL); + ],[ + AC_DEFINE(HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB, 1, + [drm_gem_plane_helper_prepare_fb() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9554606a9f9f5..06df0c626d699 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -211,6 +211,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS + AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/header/drm/drm_gem_atomic_helper.h b/include/kcl/header/drm/drm_gem_atomic_helper.h new file mode 100644 index 0000000000000..ba17f457edc4f --- /dev/null +++ b/include/kcl/header/drm/drm_gem_atomic_helper.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_GEM_ATOMIC_HELPER_PREPARE_H_H_ +#define _KCL_HEADER_DRM_GEM_ATOMIC_HELPER_PREPARE_H_H_ + +#if defined(HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB) +#include_next +#endif + +#endif From eaee41b5871a8a45194362b7963e8041b551a5ca Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 19 Jul 2022 21:00:28 -0400 Subject: [PATCH 0819/2653] drm/amdkfd: Add placeholder for deprecated CMA ioctl Implement a dummy ioctl to avoid undefined behaviour. Signed-off-by: Felix Kuehling Change-Id: I0cd535d891c64022d72aa4dc1b724944f558a219 --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 10 ++++++++++ include/uapi/linux/kfd_ioctl.h | 21 +++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 9fd864a25f88c..7fa4441667eca 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1749,6 +1749,13 @@ static int kfd_ioctl_export_dmabuf(struct file *filep, return ret; } +/* Place holder for deprecated CMA API */ +static int kfd_ioctl_cross_memory_copy_deprecated(struct file *filep, + struct kfd_process *local_p, void *data) { + dev_dbg(kfd_device, "AMDKFD_IOC_CROSS_MEMORY_COPY is deprecated.\n"); + return -EINVAL; +} + /* Handle requests for watching SMI events */ static int kfd_ioctl_smi_events(struct file *filep, struct kfd_process *p, void *data) @@ -3456,6 +3463,9 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, kfd_ioctl_rlc_spm, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_CROSS_MEMORY_COPY_DEPRECATED, + kfd_ioctl_cross_memory_copy_deprecated, 0), }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index bcda022281f26..03178b1cd3206 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -840,6 +840,23 @@ struct kfd_ioctl_ipc_import_handle_args { __u32 flags; /* from KFD */ }; +struct kfd_ioctl_cross_memory_copy_deprecated_args { + /* to KFD: Process ID of the remote process */ + __u32 pid; + /* to KFD: See above definition */ + __u32 flags; + /* to KFD: Source GPU VM range */ + __u64 src_mem_range_array; + /* to KFD: Size of above array */ + __u64 src_mem_array_size; + /* to KFD: Destination GPU VM range */ + __u64 dst_mem_range_array; + /* to KFD: Size of above array */ + __u64 dst_mem_array_size; + /* from KFD: Total amount of bytes copied */ + __u64 bytes_copied; +}; + /* Guarantee host access to memory */ #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 /* Fine grained coherency between all devices with access */ @@ -1782,6 +1799,10 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_IPC_EXPORT_HANDLE \ AMDKFD_IOWR(0x81, struct kfd_ioctl_ipc_export_handle_args) + +#define AMDKFD_IOC_CROSS_MEMORY_COPY_DEPRECATED \ + AMDKFD_IOWR(0x83, struct kfd_ioctl_cross_memory_copy_deprecated_args) + #define AMDKFD_IOC_RLC_SPM \ AMDKFD_IOWR(0x84, struct kfd_ioctl_spm_args) From 503a71e7e4cda896962983d7cccf205dbb3f3724 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 25 Aug 2022 13:30:33 +0800 Subject: [PATCH 0820/2653] drm/amdkcl: Wrap the code with macro HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED Mainly fix the build error on legacy os by wrapping the code with macro HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED Signed-off-by: Ma Jun Change-Id: I3f0a1c1e86f82153930eefde88ad3e7d904308e2 --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 3 ++- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 7c506441f74f8..a0314cb301deb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -808,6 +808,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, return domain; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static const struct drm_format_info dcc_formats[] = { { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, @@ -900,7 +901,7 @@ amdgpu_lookup_format_info(u32 format, uint64_t modifier) /* returning NULL will cause the default format structs to be used. */ return NULL; } - +#endif /* * Tries to extract the renderable DCC offset from the opaque metadata attached diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index eff18cae894bd..2cd4ee30dc92f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -94,10 +94,12 @@ enum dm_micro_swizzle { MICRO_SWIZZLE_R = 3 }; +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd) { return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]); } +#endif void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, bool *per_pixel_alpha, bool *pre_multiplied_alpha, @@ -1579,6 +1581,7 @@ static struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct return &dm_plane_state->base; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane, uint32_t format, uint64_t modifier) @@ -1640,6 +1643,7 @@ static bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane, return true; } +#endif static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane, struct drm_plane_state *state) From 7b926f78649d3bbd7a8ec47d12e36416f01b0fb5 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 25 Aug 2022 14:29:07 +0800 Subject: [PATCH 0821/2653] drm/amdkcl: Wrap the code with kcl macro Wrap the code with macro HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE to avoid build error on legacy os. Signed-off-by: Ma Jun Change-Id: I761a11a9a270c08295807bb7f3a0bc340e82e416 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3e61ada6364da..f44c3d1dfb98c 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8048,6 +8048,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) struct drm_atomic_state *state = crtc_state->state; struct drm_connector *connector = conn_state->connector; struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); @@ -8112,6 +8113,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); return dm_new_connector_state->vcpi_slots; } +#endif return 0; } From 1f6060b3cbf4b8a7729816789854ad2225a7d1ae Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 25 Aug 2022 13:46:45 +0800 Subject: [PATCH 0822/2653] drm/amdkcl: Fix the error caused by drm_gem_object->resv Use the amdkcl_ttm_resvp(bo) instead of drm_gem_object->resv Signed-off-by: Ma Jun Change-Id: Iada5d30f196ef81d4ea5148db6d1df84c96d9f90 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 2cd4ee30dc92f..ee748e193b5bb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -976,7 +976,7 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane, return r; } - r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&rbo->tbo), 1); if (r) { drm_err(adev_to_drm(adev), "reserving fence slot failed (%d)\n", r); goto error_unlock; From 716da198e202a7beb729d0ac3ea482cc82853dcc Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 25 Aug 2022 13:44:44 +0800 Subject: [PATCH 0823/2653] drm/amdkcl: Implement the bitmap_to_arr32() Implement the bitmap_to_arr32() for legacy os Signed-off-by: Ma Jun Change-Id: I9802dd45c5ce57a7bd4c83ea12e0c7ad689a83a6 --- drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c | 29 ++++++++++++++++++- drivers/gpu/drm/amd/dkms/config/config.h | 4 ++- .../gpu/drm/amd/dkms/m4/bitmap_to_arr32.m4 | 16 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_bitmap.h | 4 +++ include/kcl/kcl_bitmap.h | 12 ++++++++ 6 files changed, 64 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/bitmap_to_arr32.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c b/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c index 946b29d66408b..2b0c29936bc96 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c @@ -19,9 +19,10 @@ * DEALINGS IN THE SOFTWARE. */ +#include + #ifndef HAVE_BITMAP_FUNCS -#include #include #include #include @@ -46,3 +47,29 @@ void kcl_bitmap_free(const unsigned long *bitmap) EXPORT_SYMBOL(kcl_bitmap_free); #endif /* HAVE_BITMAP_FUNCS */ +#ifndef HAVE_BITMAP_TO_ARR32 +#if BITS_PER_LONG == 64 +/** + * kcl_bitmap_to_arr32 - copy the contents of bitmap to a u32 array of bits + * @buf: array of u32 (in host byte order), the dest bitmap + * @bitmap: array of unsigned longs, the source bitmap + * @nbits: number of bits in @bitmap + */ +void kcl_bitmap_to_arr32(u32 *buf, const unsigned long *bitmap, unsigned int nbits) +{ + unsigned int i, halfwords; + + halfwords = DIV_ROUND_UP(nbits, 32); + for (i = 0; i < halfwords; i++) { + buf[i] = (u32) (bitmap[i/2] & UINT_MAX); + if (++i < halfwords) + buf[i] = (u32) (bitmap[i/2] >> 32); + } + + /* Clear tail bits in last element of array beyond nbits. */ + if (nbits % BITS_PER_LONG) + buf[halfwords - 1] &= (u32) (UINT_MAX >> ((-nbits) & 31)); +} +EXPORT_SYMBOL(kcl_bitmap_to_arr32); +#endif +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1ac18b80aa28f..a900814a484b0 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -52,6 +52,9 @@ /* bitmap_free() is available */ #define HAVE_BITMAP_FUNCS 1 +/* bitmap_to_arr32() is available */ +#define HAVE_BITMAP_TO_ARR32 1 + /* cancel_work() is available */ #define HAVE_CANCEL_WORK 1 @@ -575,7 +578,6 @@ /* whether struct drm_framebuffer have format */ #define HAVE_DRM_FRAMEBUFFER_FORMAT 1 - /* drm_gem_plane_helper_prepare_fb() is available */ #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/bitmap_to_arr32.m4 b/drivers/gpu/drm/amd/dkms/m4/bitmap_to_arr32.m4 new file mode 100644 index 0000000000000..3c981e3fa9518 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/bitmap_to_arr32.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.19-rc1-22-525d6515604e +dnl # drm/amd/pm: use bitmap_{from,to}_arr32 where appropriate +dnl # +AC_DEFUN([AC_AMDGPU_BITMAP_TO_ARR32], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + bitmap_to_arr32(NULL, NULL, 0); + ],[ + AC_DEFINE(HAVE_BITMAP_TO_ARR32, 1, + [bitmap_to_arr32() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 06df0c626d699..6174c4e49c81a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -212,6 +212,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB + AC_AMDGPU_BITMAP_TO_ARR32 AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_bitmap.h b/include/kcl/backport/kcl_bitmap.h index 5871f13aff831..1382530929001 100644 --- a/include/kcl/backport/kcl_bitmap.h +++ b/include/kcl/backport/kcl_bitmap.h @@ -31,4 +31,8 @@ #define bitmap_free kcl_bitmap_free #endif /* HAVE_BITMAP_FUNCS */ +#ifndef HAVE_BITMAP_TO_ARR32 +#define bitmap_to_arr32 kcl_bitmap_to_arr32 +#endif /* HAVE_BITMAP_TO_ARR32 */ + #endif /* KCL_BITMAP_H */ diff --git a/include/kcl/kcl_bitmap.h b/include/kcl/kcl_bitmap.h index f65fa8fbcc56d..f2c0863b7b7d8 100644 --- a/include/kcl/kcl_bitmap.h +++ b/include/kcl/kcl_bitmap.h @@ -39,4 +39,16 @@ unsigned long *kcl_bitmap_zalloc(unsigned int nbits, gfp_t flags); void kcl_bitmap_free(const unsigned long *bitmap); #endif /* HAVE_BITMAP_FUNCS */ +/* copy form bitmap.h */ +#ifndef HAVE_BITMAP_TO_ARR32 +#if BITS_PER_LONG == 64 +void kcl_bitmap_to_arr32(u32 *buf, const unsigned long *bitmap, + unsigned int nbits); +#else +#define kcl_bitmap_to_arr32(buf, bitmap, nbits) \ + bitmap_copy_clear_tail((unsigned long *) (buf), \ + (const unsigned long *) (bitmap), (nbits)) +#endif +#endif /* HAVE_BITMAP_TO_ARR32 */ + #endif /* KCL_BITMAP_H */ From 29101ec0d2979991a44587d0dfd9f48cffe064c8 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 24 Aug 2022 13:37:09 +0800 Subject: [PATCH 0824/2653] drm/amdkcl: Fix missing execl fence copy in dma_resv_copy_fences() add back dma_resv_iter_is_exclusive() to test current fence is excl fence Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 2 +- include/kcl/kcl_dma-resv.h | 11 +++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index db40a6e5f035a..e6c4b9ef220d1 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -584,7 +584,7 @@ int dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src) } dma_fence_get(f); - if (dma_resv_iter_usage(&cursor) == DMA_RESV_USAGE_WRITE) + if (dma_resv_iter_is_exclusive(&cursor)) excl = f; else RCU_INIT_POINTER(list->shared[list->shared_count++], f); diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 39a4e3b5e67f1..4fe1fe0afac9d 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -230,6 +230,17 @@ static inline struct dma_resv_list *dma_resv_shared_list(struct dma_resv *obj) return rcu_dereference_check(obj->fence, lockdep_is_held(&(obj)->lock.base)); } +/** + * dma_resv_iter_is_exclusive - test if the current fence is the exclusive one + * @cursor: the cursor of the current position + * + * Returns true if the currently returned fence is the exclusive one. + */ +static inline bool dma_resv_iter_is_exclusive(struct dma_resv_iter *cursor) +{ + return cursor->index == 0; +} + #endif /* !defined(HAVE_DMA_RESV_FENCES) */ #if !defined(smp_store_mb) From 317add18560679bc5495092704480b862253af31 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 26 Aug 2022 15:05:52 +0800 Subject: [PATCH 0825/2653] drm/amdkcl: Check if dma_resv->seq is available Check if dma_resv->seq is available for kernel version >= 5.18.0 Signed-off-by: Ma Jun Change-Id: I17151eddb9bf97500d8abd28320505f4026b2291 --- drivers/gpu/drm/amd/dkms/Makefile | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 17 +++++++++++++++++ 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 3b41a6d897f59..4755cde423517 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -12,7 +12,7 @@ endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") -ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ),n) +ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) $(error dma_resv->seq is missing., exit...) endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a900814a484b0..18c1a1cb412a5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -127,6 +127,9 @@ /* dma_resv->seq is seqcount_ww_mutex_t */ /* #undef HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T */ +/* bug for missing dma_resv->seq */ +/* #undef HAVE_DMA_RESV_SEQ_BUG */ + /* down_read_killable() is available */ #define HAVE_DOWN_READ_KILLABLE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index 9d11fb99c397a..93c6dbc25ae22 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -36,6 +36,23 @@ AC_DEFUN([AC_AMDGPU_DMA_RESV_SEQ], [ ], [ AC_DEFINE(HAVE_DMA_RESV_SEQ, 1, [dma_resv->seq is available]) + ],[ + dnl # + dnl # dma_resv->seq is dropped since kernle 5.18.0 + dnl # So trigger the bug only for the kernel_version < 5.18.0 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 18, 0) + int this_is_bug = 0; + #else + this_is_not_bug(); + #endif + ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQ_BUG, 1, + [bug for missing dma_resv->seq]) + ]) ]) ]) ]) From 81baab0cb38715eed9d5c5d6723d152405c43b79 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 16 Aug 2022 17:05:25 +0800 Subject: [PATCH 0826/2653] drm/amdkcl: add buffer cache as available memory [Why] For system cache large amount of file buffer, free memory occupancy calculated from patch "f32b51764601 drm/amdkcl: test for available memory" will smaller than 20% and will hang the dkms install process. [How] consider buffer cache also as available memory Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6174c4e49c81a..cc0349c98735e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -604,8 +604,8 @@ dnl # AC_KERNEL_FREE_MEM dnl # return true if available memory >20% dnl # AC_DEFUN([AC_KERNEL_FREE_MEM], [ - free_mem=$(free -t | awk '/^Total:/ { - printf("%d\n", $[4] / $[2] * 100) + free_mem=$(free -t | awk '/^Mem:/ { BUF_MEM=$[6]} /^Total:/ { TOTAL_MEM=$[2];FREE_MEM=$[4] } END { + printf("%d\n", (BUF_MEM + FREE_MEM) / TOTAL_MEM * 100) }') AS_IF([[[ $free_mem -gt 20 ]]], [ From 5255fb92af5b28a140b6526097b4aee78b214116 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Wed, 24 Aug 2022 22:09:58 +0800 Subject: [PATCH 0827/2653] drm/amdgpu: create p2p links unconditionally in dkms P2P needs to be enabled on old kernels without setting CONFIG_HSA_AMD_P2P, so p2p links needs to be created unconditionally. This also releases build option from upstream. Suggested-by: Ramesh Errabolu Signed-off-by: Guchun Chen Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 3696065e84c0d..2d561e679770c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1576,7 +1576,6 @@ static int kfd_create_indirect_link_prop(struct kfd_topology_device *kdev, int g return ret; } -#if defined(CONFIG_HSA_AMD_P2P) static int kfd_add_peer_prop(struct kfd_topology_device *kdev, struct kfd_topology_device *peer, int from, int to) { @@ -1644,16 +1643,12 @@ static int kfd_add_peer_prop(struct kfd_topology_device *kdev, return ret; } -#endif static int kfd_dev_create_p2p_links(void) { struct kfd_topology_device *dev; struct kfd_topology_device *new_dev; -#if defined(CONFIG_HSA_AMD_P2P) - uint32_t i; -#endif - uint32_t k; + uint32_t i, k; int ret = 0; k = 0; @@ -1674,7 +1669,6 @@ static int kfd_dev_create_p2p_links(void) goto out; /* create p2p links */ -#if defined(CONFIG_HSA_AMD_P2P) i = 0; list_for_each_entry(dev, &topology_device_list, list) { if (dev == new_dev) @@ -1695,7 +1689,6 @@ static int kfd_dev_create_p2p_links(void) next: i++; } -#endif out: return ret; From 847e55b47c56ccad060f30a89ba392530b6c13fe Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 26 Aug 2022 17:10:21 +0800 Subject: [PATCH 0828/2653] drm/amdkcl: Test whether smca_get_bank_type() has two arguments It's caused by 91f75eb481cfaee5c4ed8fb5214bf2fbfa04bd7b "x86/MCE/AMD, EDAC/mce_amd: Support non-uniform MCA bank type enumeration" Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c | 29 +++++++++-- drivers/gpu/drm/amd/dkms/config/config.h | 7 ++- .../gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 | 52 +++++++++++++------ include/kcl/kcl_mce.h | 8 ++- 5 files changed, 70 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index f2d7a253fd038..0f06793e7ec05 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -4714,7 +4714,7 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, * and error occurred in DramECC (Extended error code = 0) then only * process the error, else bail out. */ - if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && + if (!m || !((kcl_smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && (XEC(m->status, 0x3f) == 0x0))) return NOTIFY_DONE; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c index 30e62d94fbead..bd90d447713f5 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c @@ -12,10 +12,19 @@ #ifdef CONFIG_X86_MCE_AMD #include -#ifndef HAVE_SMCA_GET_BANK_TYPE +#if defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) +enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) +{ + return smca_get_bank_type(cpu, bank); +} +#elif defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) +enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) +{ + return smca_get_bank_type(bank); +} /* Copied from v5.15-rc2-452-gf38ce910d8df:arch/x86/kernel/cpu/mce/amd.c and modified for KCL */ -#ifdef HAVE_SMCA_BANK_STRUCT +#elif defined(HAVE_STRUCT_SMCA_BANK) enum smca_bank_types smca_get_bank_type(unsigned int bank) { struct smca_bank *b; @@ -29,14 +38,24 @@ enum smca_bank_types smca_get_bank_type(unsigned int bank) return b->hwid->bank_type; } +enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) +{ + return smca_get_bank_type(bank); +} + #else int smca_get_bank_type(unsigned int bank) { pr_warn_once("smca_get_bank_type is not supported\n"); return 0; } -#endif /* HAVE_SMCA_BANK_STRUCT */ -EXPORT_SYMBOL_GPL(smca_get_bank_type); -#endif /* HAVE_SMCA_GET_BANK_TYPE */ + +int kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) +{ + return smca_get_bank_type(bank); +} + +#endif +EXPORT_SYMBOL_GPL(kcl_smca_get_bank_type); #endif /* CONFIG_X86_MCE_AMD */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 18c1a1cb412a5..b0162ceea2d3e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1080,8 +1080,11 @@ /* whether si_mem_available() is available */ #define HAVE_SI_MEM_AVAILABLE 1 -/* smca_get_bank_type() is available */ -#define HAVE_SMCA_GET_BANK_TYPE 1 +/* smca_get_bank_type(x) is available */ +/* #undef HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT */ + +/* whether smca_get_bank_type(x, x) is available */ +#define HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS 1 /* is_smca_umc_v2() is available */ /* #undef HAVE_SMCA_UMC_V2 */ diff --git a/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 b/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 index 2ed1eef7d5149..4dbfe78524f84 100644 --- a/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 @@ -1,27 +1,49 @@ dnl # -dnl # -dnl # v5.15-rc2-452-gf38ce910d8df x86/MCE/AMD: Export smca_get_bank_type symbol +dnl # v5.16-rc1-22-g91f75eb481cf x86/MCE/AMD, EDAC/mce_amd: Support non-uniform MCA bank type enumeration dnl # AC_DEFUN([AC_AMDGPU_SMCA_GET_BANK_TYPE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([smca_get_bank_type], - [arch/x86/kernel/cpu/mce/amd.c], [ - AC_DEFINE(HAVE_SMCA_GET_BANK_TYPE, 1, - [smca_get_bank_type() is available]) - ], [ - dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + unsigned int a = 0, b = 0; + enum smca_bank_types bank_type; + bank_type = smca_get_bank_type(a, b); + ],[ + AC_DEFINE(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS, 1, + [whether smca_get_bank_type(x, x) is available]) + ],[ dnl # - dnl # v4.9-rc4-4-g79349f529ab1 x86/RAS: Simplify SMCA bank descriptor struct + dnl # v5.15-rc2-452-gf38ce910d8df x86/MCE/AMD: Export smca_get_bank_type symbol dnl # AC_KERNEL_TRY_COMPILE([ + #include #include - ], [ - struct smca_bank *b = NULL; - b->id = 0; - ], [ - AC_DEFINE(HAVE_STRUCT_SMCA_BANK, 1, - [struct smca_bank is available]) + ],[ + unsigned int a = 0; + enum smca_bank_types bank_type; + bank_type = smca_get_bank_type(a); + ],[ + AC_DEFINE(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT, 1, + [smca_get_bank_type(x) is available]) + ],[ + dnl # + dnl # v4.9-rc4-4-g79349f529ab1 x86/RAS: Simplify SMCA bank descriptor struct + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + struct smca_bank *b = NULL; + b->id = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_SMCA_BANK, 1, + [struct smca_bank is available]) + ]) + ]) ]) + ]) ]) diff --git a/include/kcl/kcl_mce.h b/include/kcl/kcl_mce.h index 80625b60944b7..fd6098c99a240 100644 --- a/include/kcl/kcl_mce.h +++ b/include/kcl/kcl_mce.h @@ -11,12 +11,10 @@ #define XEC(x, mask) (((x) >> 16) & mask) #endif -#if !defined(HAVE_SMCA_GET_BANK_TYPE) -#ifdef HAVE_SMCA_BANK_STRUCT -enum smca_bank_types smca_get_bank_type(unsigned int bank); +#if defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) || defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) || defined(HAVE_STRUCT_SMCA_BANK) +enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank); #else -int smca_get_bank_type(unsigned int bank); -#endif +int kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank); #endif #ifndef HAVE_MCE_PRIO_UC From 2f1e51b0d3f62e6e18103f5edef13edbd96351b5 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 8 Sep 2022 12:37:59 -0400 Subject: [PATCH 0829/2653] drm/amdkcl: limit number of tests to number of CPU Limit the number of tests to be executed in parallel to the number of processors available in the system. Checking for available memory may cause a hang in the infinite loop on the system with small amount of the system memory. Change-Id: Ia7cc2e56d068c642975026c2e1b577128970c563 Signed-off-by: Slava Grigorev Reviewed-by: Jeremy Newton Reviewed-by: Slava Abramov --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 32 ++++++++------------------- 1 file changed, 9 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cc0349c98735e..a5d8b02d9f9ce 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -599,22 +599,6 @@ AC_DEFUN([AC_KERNEL_CHECK_HEADERS], [ AC_CHECK_HEADERS([$1],[AS_TR_CPP([HAVE_$1])=1],,[-]) ]) -dnl # -dnl # AC_KERNEL_FREE_MEM -dnl # return true if available memory >20% -dnl # -AC_DEFUN([AC_KERNEL_FREE_MEM], [ - free_mem=$(free -t | awk '/^Mem:/ { BUF_MEM=$[6]} /^Total:/ { TOTAL_MEM=$[2];FREE_MEM=$[4] } END { - printf("%d\n", (BUF_MEM + FREE_MEM) / TOTAL_MEM * 100) - }') - - AS_IF([[[ $free_mem -gt 20 ]]], [ - $1 - ], [ - $2 - ]) -]) - dnl # dnl # AC_KERNEL_DO_BACKGROUND dnl # $1: contents to be executed @@ -624,14 +608,16 @@ AC_DEFUN([AC_KERNEL_DO_BACKGROUND], [ AC_KERNEL_TMP_BUILD_DIR([$1]) } - while : + AC_CHECK_PROG(NPROC, nproc, yes) + AS_IF([test x"$NPROC" != x"yes"], [ + ncpu=1 + ], [ + ncpu=$(nproc) + ]) + + while [[ $(jobs | wc -l) -gt $ncpu ]] do - AC_KERNEL_FREE_MEM([rc=0], [rc=1]) - if test $rc -ne 0; then : - sleep 1 - else : - break - fi + sleep 0.1 done do_background & From c22afdb9ae7a0b3dcdcc6dfe7b84e22f154ff5d4 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 9 Sep 2022 15:12:04 +0800 Subject: [PATCH 0830/2653] drm/amdkcl: wrap code under macro HAVE_PCI_DEV_LTR_PATH It's caused by 9000fc3a77dbb05224a0053a85a0d515b4069286 "drm/amdgpu: Don't enable LTR if not supported" There is no member ltr_path in struc pci_dev in old kernels. So wrap the code under macro HAVE_PCI_DEV_LTR Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 3 ++- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 3 ++- drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 2 ++ 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c index 04041b398781b..bb1a1375eef0f 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c @@ -460,9 +460,10 @@ static void nbio_v2_3_program_aspm(struct amdgpu_device *adev) /* Don't bother about LTR if LTR is not enabled * in the path */ +#ifdef HAVE_PCI_DEV_LTR_PATH if (adev->pdev->ltr_path) nbio_v2_3_program_ltr(adev); - +#endif def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3); data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c index e911368c1aeb5..522dbe8a92d6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c @@ -361,9 +361,10 @@ static void nbio_v6_1_program_aspm(struct amdgpu_device *adev) /* Don't bother about LTR if LTR is not enabled * in the path */ +#ifdef HAVE_PCI_DEV_LTR_PATH if (adev->pdev->ltr_path) nbio_v6_1_program_ltr(adev); - +#endif def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c index d5002ff931d84..dceacf3f0d512 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c @@ -759,8 +759,10 @@ static void nbio_v7_4_program_aspm(struct amdgpu_device *adev) /* Don't bother about LTR if LTR is not enabled * in the path */ +#ifdef HAVE_PCI_DEV_LTR_PATH if (adev->pdev->ltr_path) nbio_v7_4_program_ltr(adev); +#endif def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; From a8d251a36a142f383fc3d036d83cadce821e8527 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 14 Sep 2022 12:24:25 +0800 Subject: [PATCH 0831/2653] drm/amdkcl: wrap code under macro HAVE_CHUNK_ID_SYNOBJ_IN_OUT and HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL It's caused by 253c2b45dfa82a18530076bb743f67355948550c "drm/amdgpu: cleanup CS init/fini and pass1" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index ff9da699bde2e..6f5e0ceee861e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1532,11 +1532,15 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser) amdgpu_sync_free(&parser->sync); drm_exec_fini(&parser->exec); +#if defined(HAVE_CHUNK_ID_SYNOBJ_IN_OUT) for (i = 0; i < parser->num_post_deps; i++) { drm_syncobj_put(parser->post_deps[i].syncobj); +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) kfree(parser->post_deps[i].chain); +#endif } kfree(parser->post_deps); +#endif dma_fence_put(parser->fence); From a538cae67286af5740f95c3696ec342fb9f17f01 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 14 Sep 2022 15:35:09 +0800 Subject: [PATCH 0832/2653] drm/amdkcl: wrap code under macro HAVE_CHUNK_ID_SYNOBJ_IN_OUT, HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL, HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES It's caused by d8ede49db6249fb8d274dde7475e7b33d2ab126c "drm/amdgpu: reorder CS code" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 6f5e0ceee861e..18135a090adf5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -462,7 +462,6 @@ static int amdgpu_cs_p2_dependencies(struct amdgpu_cs_parser *p, } return 0; } - static int amdgpu_syncobj_lookup_and_add(struct amdgpu_cs_parser *p, uint32_t handle, u64 point, u64 flags) @@ -546,7 +545,9 @@ static int amdgpu_cs_p2_syncobj_out(struct amdgpu_cs_parser *p, drm_syncobj_find(p->filp, deps[i].handle); if (!p->post_deps[i].syncobj) return -EINVAL; +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) p->post_deps[i].chain = NULL; +#endif p->post_deps[i].point = 0; p->num_post_deps++; } @@ -576,14 +577,14 @@ static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p, for (i = 0; i < num_deps; ++i) { struct amdgpu_cs_post_dep *dep = &p->post_deps[i]; - +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) dep->chain = NULL; if (syncobj_deps[i].point) { dep->chain = dma_fence_chain_alloc(); if (!dep->chain) return -ENOMEM; } - +#endif dep->syncobj = drm_syncobj_find(p->filp, syncobj_deps[i].handle); if (!dep->syncobj) { @@ -596,7 +597,6 @@ static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p, return 0; } -#endif static int amdgpu_cs_p2_shadow(struct amdgpu_cs_parser *p, struct amdgpu_cs_chunk *chunk) @@ -635,7 +635,9 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) return r; break; case AMDGPU_CHUNK_ID_DEPENDENCIES: +#if defined(HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES: +#endif r = amdgpu_cs_p2_dependencies(p, chunk); if (r) return r; @@ -650,6 +652,7 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) if (r) return r; break; +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT: r = amdgpu_cs_p2_syncobj_timeline_wait(p, chunk); if (r) @@ -660,6 +663,7 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) if (r) return r; break; +#endif case AMDGPU_CHUNK_ID_CP_GFX_SHADOW: r = amdgpu_cs_p2_shadow(p, chunk); if (r) @@ -1532,7 +1536,6 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser) amdgpu_sync_free(&parser->sync); drm_exec_fini(&parser->exec); -#if defined(HAVE_CHUNK_ID_SYNOBJ_IN_OUT) for (i = 0; i < parser->num_post_deps; i++) { drm_syncobj_put(parser->post_deps[i].syncobj); #if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) @@ -1540,7 +1543,6 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser) #endif } kfree(parser->post_deps); -#endif dma_fence_put(parser->fence); From ac9624af3b688d4047195f0644b4df374a564864 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 14 Sep 2022 17:27:20 +0800 Subject: [PATCH 0833/2653] drm/amdkcl: test whether drm_gem_object->resv is available It's caused by 708a6179d00f1d6cc060afcf7b5b6dc4e75d3ed6 "drm/amdgpu: use DMA_RESV_USAGE_BOOKKEEP v2" dd37405b55736ee33410ad653b8c2c9a2b2700c9 "drm/amdgpu: reorder CS code" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8 ++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 8bccb19d475a1..ce5d8e644fc65 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1495,7 +1495,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(&vm->root.bo->tbo), 1); if (ret) goto reserve_shared_fail; - dma_resv_add_fence(vm->root.bo->tbo.base.resv, + dma_resv_add_fence(amdkcl_ttm_resvp(&vm->root.bo->tbo), &vm->process_info->eviction_fence->base, DMA_RESV_USAGE_BOOKKEEP); amdgpu_bo_unreserve(vm->root.bo); @@ -3407,7 +3407,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu * if (mem->bo->tbo.pin_count) continue; - dma_resv_add_fence(mem->bo->tbo.base.resv, + dma_resv_add_fence(amdkcl_ttm_resvp(&mem->bo->tbo), &process_info->eviction_fence->base, DMA_RESV_USAGE_BOOKKEEP); } @@ -3416,7 +3416,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu * vm_list_node) { struct amdgpu_bo *bo = peer_vm->root.bo; - dma_resv_add_fence(bo->tbo.base.resv, + dma_resv_add_fence(amdkcl_ttm_resvp(&bo->tbo), &process_info->eviction_fence->base, DMA_RESV_USAGE_BOOKKEEP); } @@ -3471,7 +3471,7 @@ int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(&gws_bo->tbo), 1); if (ret) goto reserve_shared_fail; - dma_resv_add_fence(gws_bo->tbo.base.resv, + dma_resv_add_fence(amdkcl_ttm_resvp(&gws_bo->tbo), &process_info->eviction_fence->base, DMA_RESV_USAGE_BOOKKEEP); amdgpu_bo_unreserve(gws_bo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index 46d9fb433ab2a..cbeb732f85d1d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -127,7 +127,7 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p, swap(p->vm->last_unlocked, tmp); dma_fence_put(tmp); } else { - dma_resv_add_fence(p->vm->root.bo->tbo.base.resv, f, + dma_resv_add_fence(amdkcl_ttm_resvp(&p->vm->root.bo->tbo), f, DMA_RESV_USAGE_BOOKKEEP); } From 904110a8978d2dad62bcd73e3203bfa85eba2400 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 20 Sep 2022 15:17:48 +0800 Subject: [PATCH 0834/2653] drm/amdkcl: regard DMA_RESV_USAGE_BOOKKEEP usage as read fence for legacy os For legacy os, the new usage DMA_RESV_USAGE_BOOKKEEP is regarded same as DMA_RESV_USAGE_READ Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index e6c4b9ef220d1..1477c6349dad7 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -314,7 +314,7 @@ void dma_resv_replace_fences(struct dma_resv *obj, uint64_t context, unsigned int i; /* Only readers supported for now */ - WARN_ON(usage != DMA_RESV_USAGE_READ); + WARN_ON(usage != DMA_RESV_USAGE_READ && usage != DMA_RESV_USAGE_BOOKKEEP); dma_resv_assert_held(obj); From 17095f8eff15895e46f85e1420419106187b669a Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 31 Aug 2022 17:25:12 +0800 Subject: [PATCH 0835/2653] drm/amdkcl: Update the config.h Update the version related macro in config.h Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I580539022bb383bcc54bf12a853cf690ec190318 --- drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b0162ceea2d3e..92dfec9ea8711 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1319,7 +1319,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 5.13.5" +#define PACKAGE_STRING "amdgpu-dkms 5.19.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1328,7 +1328,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "5.13.5" +#define PACKAGE_VERSION "5.19.0" #include "config-amd-chips.h" From d7cdc567b9cac34d10bce280366ea159fcf50284 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 15 Sep 2022 14:20:19 +0800 Subject: [PATCH 0836/2653] drm/amdkcl: test whether drm_gem_object->resv is available It's caused by e406606fb782b811b6bfb6f51b5fc9e0c8f5d1bf "drm/amdgpu: SDMA update use unlocked iterator" Signed-off-by: Asher Song Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index cbeb732f85d1d..3ca6cf8297d2e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -228,7 +228,7 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, int r; /* Wait for PD/PT moves to be completed */ - dma_resv_iter_begin(&cursor, bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL); + dma_resv_iter_begin(&cursor, amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL); dma_resv_for_each_fence_unlocked(&cursor, fence) { dma_fence_get(fence); r = drm_sched_job_add_dependency(&p->job->base, fence); From d1356cd476cb9e7d9a3043a1eed139954cf8df4b Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 7 Sep 2022 14:16:27 +0800 Subject: [PATCH 0837/2653] drm/amdkcl: Optimize cancel_work() test Search the __cancel_work() instead of cancel_work() to optimize the cancel_work() test. Suggested-by: Flora Cui Signed-off-by: Ma Jun Reviewed-by: Guchun Chen Reviewed-by: Flora Cui Change-Id: I595e947b5c98bc601b7e173fbd2ceed4ccd9f7f8 --- drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c | 13 +++++++++---- include/kcl/backport/kcl_workqueue_backport.h | 4 ++-- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c b/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c index 461066e047ac3..7c9b248df0e27 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c @@ -22,20 +22,25 @@ #include #ifndef HAVE_CANCEL_WORK -bool (*_kcl_cancel_work)(struct work_struct *work); -EXPORT_SYMBOL(_kcl_cancel_work); +static bool (*_kcl_cancel_work)(struct work_struct *work, bool is_dwork); -bool _kcl_cancel_work_stub(struct work_struct *work) +bool _kcl_cancel_work_stub(struct work_struct *work, bool is_dwork) { pr_warn_once("cancel_work function is not supported\n"); return false; } + +bool kcl_cancel_work(struct work_struct *work) +{ + return _kcl_cancel_work(work, false); +} +EXPORT_SYMBOL(kcl_cancel_work); #endif void amdkcl_workqueue_init(void) { #ifndef HAVE_CANCEL_WORK - _kcl_cancel_work = amdkcl_fp_setup("cancel_work", _kcl_cancel_work_stub); + _kcl_cancel_work = amdkcl_fp_setup("__cancel_work", _kcl_cancel_work_stub); #endif /* HAVE_CANCEL_WORK */ } diff --git a/include/kcl/backport/kcl_workqueue_backport.h b/include/kcl/backport/kcl_workqueue_backport.h index 3e6adabc0f08c..ac9ffbddd468c 100644 --- a/include/kcl/backport/kcl_workqueue_backport.h +++ b/include/kcl/backport/kcl_workqueue_backport.h @@ -6,8 +6,8 @@ #include #ifndef HAVE_CANCEL_WORK -extern bool (*_kcl_cancel_work)(struct work_struct *work); -#define cancel_work _kcl_cancel_work +extern bool kcl_cancel_work(struct work_struct *work); +#define cancel_work kcl_cancel_work #endif #endif /* KCL_LINUX_WORKQUEUE_BACKPORT_H */ From 4b80f1ff40ee060ee1423f638de2af8baf03f358 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 7 Sep 2022 20:57:09 +0800 Subject: [PATCH 0838/2653] drm/amdkcl: Modify the kcl drm buddy functions name Signed-off-by: Ma Jun Change-Id: Ia336a4c20279382d5f931edae10114c57fa756e3 --- drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c | 36 +++++++++++----------- include/kcl/kcl_drm_buddy.h | 27 ++++++++++------ 2 files changed, 36 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c index b8e89facbadd0..0d18f0d43b68d 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c @@ -75,7 +75,7 @@ static void mark_split(struct drm_buddy_block *block) * Returns: * 0 on success, error code on failure. */ -int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) +int kcl_drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) { unsigned int i; u64 offset; @@ -156,7 +156,7 @@ int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) kfree(mm->free_list); return -ENOMEM; } -EXPORT_SYMBOL(drm_buddy_init); +EXPORT_SYMBOL(kcl_drm_buddy_init); /** * drm_buddy_fini - tear down the memory manager @@ -165,7 +165,7 @@ EXPORT_SYMBOL(drm_buddy_init); * * Cleanup memory manager resources and the freelist */ -void drm_buddy_fini(struct drm_buddy *mm) +void kcl_drm_buddy_fini(struct drm_buddy *mm) { int i; @@ -179,7 +179,7 @@ void drm_buddy_fini(struct drm_buddy *mm) kfree(mm->roots); kfree(mm->free_list); } -EXPORT_SYMBOL(drm_buddy_fini); +EXPORT_SYMBOL(kcl_drm_buddy_fini); static int split_block(struct drm_buddy *mm, struct drm_buddy_block *block) @@ -235,11 +235,11 @@ __get_buddy(struct drm_buddy_block *block) * any concurrent allocate and free operations. */ struct drm_buddy_block * -drm_get_buddy(struct drm_buddy_block *block) +kcl_drm_get_buddy(struct drm_buddy_block *block) { return __get_buddy(block); } -EXPORT_SYMBOL(drm_get_buddy); +EXPORT_SYMBOL(kcl_drm_get_buddy); static void __drm_buddy_free(struct drm_buddy *mm, struct drm_buddy_block *block) @@ -271,14 +271,14 @@ static void __drm_buddy_free(struct drm_buddy *mm, * @mm: DRM buddy manager * @block: block to be freed */ -void drm_buddy_free_block(struct drm_buddy *mm, +void kcl_drm_buddy_free_block(struct drm_buddy *mm, struct drm_buddy_block *block) { BUG_ON(!drm_buddy_block_is_allocated(block)); mm->avail += drm_buddy_block_size(mm, block); __drm_buddy_free(mm, block); } -EXPORT_SYMBOL(drm_buddy_free_block); +EXPORT_SYMBOL(kcl_drm_buddy_free_block); /** * drm_buddy_free_list - free blocks @@ -286,7 +286,7 @@ EXPORT_SYMBOL(drm_buddy_free_block); * @mm: DRM buddy manager * @objects: input list head to free blocks */ -void drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects) +void kcl_drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects) { struct drm_buddy_block *block, *on; @@ -296,7 +296,7 @@ void drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects) } INIT_LIST_HEAD(objects); } -EXPORT_SYMBOL(drm_buddy_free_list); +EXPORT_SYMBOL(kcl_drm_buddy_free_list); static inline bool overlaps(u64 s1, u64 e1, u64 s2, u64 e2) { @@ -559,7 +559,7 @@ static int __drm_buddy_alloc_range(struct drm_buddy *mm, * Returns: * 0 on success, error code on failure. */ -int drm_buddy_block_trim(struct drm_buddy *mm, +int kcl_drm_buddy_block_trim(struct drm_buddy *mm, u64 new_size, struct list_head *blocks) { @@ -608,7 +608,7 @@ int drm_buddy_block_trim(struct drm_buddy *mm, block->parent = parent; return err; } -EXPORT_SYMBOL(drm_buddy_block_trim); +EXPORT_SYMBOL(kcl_drm_buddy_block_trim); /** * drm_buddy_alloc_blocks - allocate power-of-two blocks @@ -630,7 +630,7 @@ EXPORT_SYMBOL(drm_buddy_block_trim); * Returns: * 0 on success, error code on failure. */ -int drm_buddy_alloc_blocks(struct drm_buddy *mm, +int kcl_drm_buddy_alloc_blocks(struct drm_buddy *mm, u64 start, u64 end, u64 size, u64 min_page_size, struct list_head *blocks, @@ -711,7 +711,7 @@ int drm_buddy_alloc_blocks(struct drm_buddy *mm, drm_buddy_free_list(mm, &allocated); return err; } -EXPORT_SYMBOL(drm_buddy_alloc_blocks); +EXPORT_SYMBOL(kcl_drm_buddy_alloc_blocks); /** * drm_buddy_block_print - print block information @@ -720,7 +720,7 @@ EXPORT_SYMBOL(drm_buddy_alloc_blocks); * @block: DRM buddy block * @p: DRM printer to use */ -void drm_buddy_block_print(struct drm_buddy *mm, +void kcl_drm_buddy_block_print(struct drm_buddy *mm, struct drm_buddy_block *block, struct drm_printer *p) { @@ -729,7 +729,7 @@ void drm_buddy_block_print(struct drm_buddy *mm, drm_printf(p, "%#018llx-%#018llx: %llu\n", start, start + size, size); } -EXPORT_SYMBOL(drm_buddy_block_print); +EXPORT_SYMBOL(kcl_drm_buddy_block_print); /** * drm_buddy_print - print allocator state @@ -737,7 +737,7 @@ EXPORT_SYMBOL(drm_buddy_block_print); * @mm: DRM buddy manager * @p: DRM printer to use */ -void drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p) +void kcl_drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p) { int order; @@ -764,7 +764,7 @@ void drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p) drm_printf(p, ", pages: %llu\n", count); } } -EXPORT_SYMBOL(drm_buddy_print); +EXPORT_SYMBOL(kcl_drm_buddy_print); void amdkcl_drm_buddy_module_exit(void) { diff --git a/include/kcl/kcl_drm_buddy.h b/include/kcl/kcl_drm_buddy.h index 5f13318751887..b87f9743342ea 100644 --- a/include/kcl/kcl_drm_buddy.h +++ b/include/kcl/kcl_drm_buddy.h @@ -131,31 +131,40 @@ drm_buddy_block_size(struct drm_buddy *mm, return mm->chunk_size << drm_buddy_block_order(block); } -int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size); +int kcl_drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size); -void drm_buddy_fini(struct drm_buddy *mm); +void kcl_drm_buddy_fini(struct drm_buddy *mm); struct drm_buddy_block * -drm_get_buddy(struct drm_buddy_block *block); +kcl_drm_get_buddy(struct drm_buddy_block *block); -int drm_buddy_alloc_blocks(struct drm_buddy *mm, +int kcl_drm_buddy_alloc_blocks(struct drm_buddy *mm, u64 start, u64 end, u64 size, u64 min_page_size, struct list_head *blocks, unsigned long flags); -int drm_buddy_block_trim(struct drm_buddy *mm, +int kcl_drm_buddy_block_trim(struct drm_buddy *mm, u64 new_size, struct list_head *blocks); -void drm_buddy_free_block(struct drm_buddy *mm, struct drm_buddy_block *block); +void kcl_drm_buddy_free_block(struct drm_buddy *mm, struct drm_buddy_block *block); -void drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects); +void kcl_drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects); -void drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p); -void drm_buddy_block_print(struct drm_buddy *mm, +void kcl_drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p); +void kcl_drm_buddy_block_print(struct drm_buddy *mm, struct drm_buddy_block *block, struct drm_printer *p); +#define drm_buddy_print kcl_drm_buddy_print +#define drm_buddy_block_print kcl_drm_buddy_block_print +#define drm_buddy_alloc_blocks kcl_drm_buddy_alloc_blocks +#define drm_buddy_block_trim kcl_drm_buddy_block_trim +#define drm_buddy_free_list kcl_drm_buddy_free_list +#define drm_buddy_free_block kcl_drm_buddy_free_block +#define drm_get_buddy kcl_drm_get_buddy +#define drm_buddy_fini kcl_drm_buddy_fini +#define drm_buddy_init kcl_drm_buddy_init #endif /* HAVE_DRM_DRM_BUDDY_H */ #endif /* __KCL_KCL_DRM_BUDDY_H__ */ From c042fdffe8672e843b93be3eaa0098b3985a7e7e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 16 Sep 2022 11:05:12 +0800 Subject: [PATCH 0839/2653] drm/amdkcl: fix the compile error caused by drm_printf() Fix the compile error caused by drm_printf() Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: If3417d24b8a808de1d4b3ac83d0cd7c92d18e1b1 --- include/kcl/kcl_drm_buddy.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/kcl/kcl_drm_buddy.h b/include/kcl/kcl_drm_buddy.h index b87f9743342ea..4db95edb25369 100644 --- a/include/kcl/kcl_drm_buddy.h +++ b/include/kcl/kcl_drm_buddy.h @@ -13,6 +13,7 @@ #include #include #include +#include #define range_overflows(start, size, max) ({ \ typeof(start) start__ = (start); \ From adc17a164e6f59ba3be0417ed697341f120ae9fc Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 16 Sep 2022 22:11:46 +0800 Subject: [PATCH 0840/2653] drm/amdkcl: Check if drm_crtc_funcs->late_register() is defined Check if drm_crtc_funcs->late_register() is defined Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: Ie53ef60820cefd381976ac3b9922fda8660100f3 --- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 19 +++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 633d6192bdac2..8bb58a8a860fb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -464,6 +464,7 @@ static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc) } #ifdef CONFIG_DEBUG_FS +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) { crtc_debugfs_init(crtc); @@ -471,6 +472,7 @@ static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) return 0; } #endif +#endif #ifdef AMD_PRIVATE_COLOR /** @@ -561,8 +563,10 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, #endif #if defined(CONFIG_DEBUG_FS) +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER .late_register = amdgpu_dm_crtc_late_register, #endif +#endif #ifdef AMD_PRIVATE_COLOR .atomic_set_property = amdgpu_dm_atomic_crtc_set_property, .atomic_get_property = amdgpu_dm_atomic_crtc_get_property, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 92dfec9ea8711..d0479ad29347d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1146,6 +1146,9 @@ /* drm_crtc_funcs->set_config() wants ctx parameter */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX 1 +/* drm_crtc_funcs->late_register() is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER 1 + /* crtc->funcs->set_crc_source() is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CRC_SOURCE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index e92c34e468d65..41d85b15ac85f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -171,6 +171,24 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL], [ ]) ]) +dnl # +dnl # commit v4.8-rc1~62-79190ea26 +dnl # drm: Add callbacks for late registering +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc_funcs *crtc_funcs = NULL; + crtc_funcs->late_register(NULL); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER, 1, [ + drm_crtc_funcs->late_register() is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK @@ -179,4 +197,5 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER ]) From 4c8a490204c11db4f4cfc5eeea4420bd0a43e142 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 16 Sep 2022 22:44:57 +0800 Subject: [PATCH 0841/2653] drm/amdkcl: Check if drm_crtc->debugfs_entry is defined Check if drm_crtc->debugfs_entry is defined Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I407e6fdc0bf040dfb619f7718b0d077179fbe510 --- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 | 21 +++++++++++++++++++ 4 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index c8846afc46042..7f0c4458b85ea 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3811,10 +3811,12 @@ void crtc_debugfs_init(struct drm_crtc *crtc) &crc_win_update_fops); dput(dir); #endif +#ifdef HAVE_STRUCT_DRM_CRTC_DEBUGFS_ENTRY debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry, crtc, &amdgpu_current_bpc_fops); debugfs_create_file("amdgpu_current_colorspace", 0644, crtc->debugfs_entry, crtc, &amdgpu_current_colorspace_fops); +#endif } /* diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d0479ad29347d..ff03bc13a416b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1161,6 +1161,9 @@ /* struct drm_crtc_state has flag for flip */ #define HAVE_STRUCT_DRM_CRTC_STATE_FLIP_FLAG 1 +/* drm_crtc->debugfs_entry is available */ +#define HAVE_STRUCT_DRM_CRTC_DEBUGFS_ENTRY 1 + /* struct drm_crtc_state->pageflip_flags is available */ /* #undef HAVE_STRUCT_DRM_CRTC_STATE_PAGEFLIP_FLAGS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a5d8b02d9f9ce..59adba5e6e1b9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -213,6 +213,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB AC_AMDGPU_BITMAP_TO_ARR32 + AC_AMDGPU_STRUCT_DRM_CRTC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 new file mode 100644 index 0000000000000..5c02ff4595856 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v4.10-rc1~154-9edbf1fa6 +dnl # drm: Add API for capturing frame CRCs +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_DEBUGFS_ENTRY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc *test = NULL; + test->debugfs_entry = NULL; + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_DEBUGFS_ENTRY, 1, [ + drm_crtc->debugfs_entry is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC], [ + AC_AMDGPU_STRUCT_DRM_CRTC_DEBUGFS_ENTRY +]) From 37928dd3a771b51bbdf4347e5d1333b5ca889bb9 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 22 Sep 2022 14:58:47 +0800 Subject: [PATCH 0842/2653] drm/amdkcl: Remove redundant whitespace Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I107ee795d50908d08587d25a215012fd6403049f --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 60bf213b8c85d..65bf30a84fdd3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -279,7 +279,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper, #else DRM_INFO("fb depth is %d\n", fb->format->depth); #endif - DRM_INFO(" pitch is %d\n", fb->pitches[0]); + DRM_INFO("pitch is %d\n", fb->pitches[0]); vga_switcheroo_client_fb_set(adev->pdev, info); return 0; From ee5e644eead65b6f21061c9ca41a49f6d736551e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 22 Sep 2022 15:48:21 +0800 Subject: [PATCH 0843/2653] drm/amdgpu: [hybrid] revise semaphore object support Due to struct amdgpu_cs_parser change, revise semaphore object support. It's caused by "e89b45235fe6edd94595a3c437beaef0dbf762ca" drm/amdgpu: add gang submit frontend v6 Signed-off-by: Asher Song Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 18135a090adf5..2545699a35fb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -672,7 +672,12 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) } } - return amdgpu_sem_add_cs(p->ctx, p->entity, &p->job->sync); + for (i = 0; i < p->gang_size; ++i) { + r = amdgpu_sem_add_cs(p->ctx, p->entities[i], &p->jobs[i]->sync); + if (r) + return r; + } + return 0; } /* Convert microseconds to bytes. */ From 680e018d8b2170e7aa7cc5dd89d85b79a4efd135 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 26 Sep 2022 15:44:12 +0800 Subject: [PATCH 0844/2653] drm/amdkcl: wrap code under macro CONFIG_DRM_AMD_DC_DSC_SUPPORT It's caused by ac2e8b34b24ac3966df28d289fc2c03825bc8f1f drm/amd/display: Fix various dynamic ODM transitions on DCN32 Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 2 ++ drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h | 2 ++ drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index 636da9084b02c..b60e3e6787670 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -1509,6 +1509,7 @@ bool dcn32_dsc_pg_status( return pwr_status == 0; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn32_update_dsc_pg(struct dc *dc, struct dc_state *context, bool safe_to_disable) @@ -1531,6 +1532,7 @@ void dcn32_update_dsc_pg(struct dc *dc, } } } +#endif void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context) { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h index 0303a59536737..644d141cd01e7 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h @@ -107,9 +107,11 @@ bool dcn32_dsc_pg_status( struct dce_hwseq *hws, unsigned int dsc_inst); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn32_update_dsc_pg(struct dc *dc, struct dc_state *context, bool safe_to_disable); +#endif void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c index b971356d30b18..14d700deaac31 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c @@ -115,7 +115,9 @@ static const struct hw_sequencer_funcs dcn32_funcs = { .update_visual_confirm_color = dcn10_update_visual_confirm_color, .subvp_pipe_control_lock_fast = dcn32_subvp_pipe_control_lock_fast, .update_phantom_vp_position = dcn32_update_phantom_vp_position, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .update_dsc_pg = dcn32_update_dsc_pg, +#endif .apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom, .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless, .calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider, From 4652c8405a0bce76d6f6f29f6dc28ad7d70f6636 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 27 Sep 2022 13:43:38 +0800 Subject: [PATCH 0845/2653] drm/amdkcl: Test whether linux/dma-map-ops.h exist Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 ++++++ include/kcl/header/linux/dma-map-ops.h | 11 +++++++++++ 3 files changed, 20 insertions(+) create mode 100644 include/kcl/header/linux/dma-map-ops.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ff03bc13a416b..28f62454fb160 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -900,6 +900,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_FENCE_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_MAP_OPS_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_RESV_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index b6024239ef2f5..0b21b17421ef2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -114,4 +114,10 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # spin loop primitives for busy waiting dnl # AC_KERNEL_CHECK_HEADERS([linux/processor.h]) + + dnl # + dnl # v5.9-rc6-311-g0a0f0d8be76d + dnl # dma-mapping: split + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-map-ops.h]) ]) diff --git a/include/kcl/header/linux/dma-map-ops.h b/include/kcl/header/linux/dma-map-ops.h new file mode 100644 index 0000000000000..0bda5e05b7eb1 --- /dev/null +++ b/include/kcl/header/linux/dma-map-ops.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__LINUX_DMA_MAP_OPS_H_H_ +#define _KCL_HEADER__LINUX_DMA_MAP_OPS_H_H_ + +#if defined(HAVE_LINUX_DMA_MAP_OPS_H) +#include_next +#else +#include +#endif + +#endif From 028164da1e10cf54df28634fad4cbeadfc1655e3 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 22 Sep 2022 14:24:55 +0800 Subject: [PATCH 0846/2653] drm/amdkcl: avoid DMA mapping of DOORBELL/MMIO bos for legacy os map_resource ops not provided On AMD platform for legacy os(e.g., ubuntu with kernel version <= 5.4), PCI device cannot access a peer device's BAR resource when a hardware IOMMU is enabled as the map_resource DMA op is not provided. This is fixed by commit "be62dbf554c5 iommu/amd: Convert AMD iommu driver to the dma-iommu api". This patch avoid DMA mapping of DOORBELL/MMIO bos for legacy os that dma map_resource ops is not provided. v2: remove kcl kernel version check v3: include linux/dma-map-ops.h Signed-off-by: Leslie Shi Reviewed-by: Felix Kuehling Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 15 +++++++++++---- include/kcl/kcl_dma_mapping.h | 6 ++++++ 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index ce5d8e644fc65..fce82223feef5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -959,10 +959,17 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL || mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP), "Handing invalid SG BO in ATTACH request"); - attachment[i]->type = KFD_MEM_ATT_SG; - ret = create_dmamap_sg_bo(adev, mem, &bo[i]); - if (ret) - goto unwind; + + if (kcl_has_dma_map_resource_ops(adev->dev)) { + attachment[i]->type = KFD_MEM_ATT_SG; + ret = create_dmamap_sg_bo(adev, mem, &bo[i]); + if (ret) + goto unwind; + } else { + attachment[i]->type = KFD_MEM_ATT_SHARED; + bo[i] = mem->bo; + drm_gem_object_get(&bo[i]->tbo.base); + } #ifdef AMDKCL_AMDGPU_DMABUF_OPS /* Enable acces to GTT BOs of peer devices */ } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT) { diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h index 81d15205ec77e..c433caeca3d98 100644 --- a/include/kcl/kcl_dma_mapping.h +++ b/include/kcl/kcl_dma_mapping.h @@ -3,6 +3,7 @@ #define AMDKCL_DMA_MAPPING_H #include +#include /* * commit v4.8-11962-ga9a62c938441 @@ -127,6 +128,11 @@ static inline void dma_unmap_sgtable(struct device *dev, struct sg_table *sgt, } #endif +static inline bool kcl_has_dma_map_resource_ops(struct device *dev) +{ + const struct dma_map_ops *ops = get_dma_ops(dev); + return ops == NULL || ops->map_resource != NULL; +} /* * v5.8-rc3-2-g68d237056e00 ("scatterlist: protect parameters of the sg_table related macros") * v5.7-rc5-33-g709d6d73c756 ("scatterlist: add generic wrappers for iterating over sgtable objects") From 6ef204d37fa88fc54ada4a0c73751127f4b95190 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Fri, 30 Sep 2022 17:32:20 -0500 Subject: [PATCH 0847/2653] drm/amdgpu: Query P2PDMA distance only if CONFIG_HSA_AMD_P2P is defined CONFIG_HSA_AMD_P2P indicates the requirements that are needed for P2P DMA Mappings. It is important to note that enabling CONFIG_HSA_AMD_P2P is a necessary but insufficient condition. It is possible to encounter runtime errors - e.g. CPU's do not support Inter-CPU transport of PCIe transaction packets i.e. P2PDMA distance API may return error Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index e09b0d1725cb4..9ebaeaed3b3a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6851,6 +6851,12 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) * Return true if @peer_adev can access (DMA) @adev through the PCIe * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of * @peer_adev. + * + * @note: CONFIG_HSA_AMD_P2P indicates support for P2P DMA mappings. Query + * P2PDMA distance only if the kernel has all the prerequisites for P2P DMA + * support. Otherwise fall back to the less reliable legacy P2P support to + * avoid regressions. + * */ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, struct amdgpu_device *peer_adev) @@ -6860,7 +6866,7 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, bool is_large_bar = adev->gmc.visible_vram_size && adev->gmc.real_vram_size == adev->gmc.visible_vram_size; -#ifdef CONFIG_PCI_P2PDMA +#ifdef CONFIG_HSA_AMD_P2P p2p_access = !adev->gmc.xgmi.connected_to_cpu && !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0); From 66058bb0072b163f6232e45cff5618b51dbe63ca Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 11 Oct 2022 10:24:53 +0800 Subject: [PATCH 0848/2653] drm/amdkcl: wrap code under macro CONFIG_DRM_AMD_DC_DSC_SUPPORT and HAVE_DRM_DP_MST_ATOMIC_CHECK It's caused by a7bfbdb0578e89ae380eeffdb2949bd0162e1cb1 "drm/amd/display: Validate DSC After Enable All New CRTCs" 64fbeb725d23878bea621dfddbd3c64a4b0868fe "drm/amd/display: Add a helper to map ODM/MPC/Multi-Plane resources" Signed-off-by: Asher Song Reviewed-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f44c3d1dfb98c..1d91854417eaa 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12240,12 +12240,14 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } +#if defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) #if defined(CONFIG_DRM_AMD_DC_FP) if (dc_resource_is_dsc_encoding_supported(dc)) { ret = pre_validate_dsc(state, &dm_state, vars); if (ret != 0) goto fail; } +#endif #endif /* Run this here since we want to validate the streams we created */ From 1d3c1079eba9dc7949d49279c95a8c1f70e7f34f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 12 Oct 2022 16:29:57 +0800 Subject: [PATCH 0849/2653] drm/amdgpu: [hybrid] fix dgma Signed-off-by: Flora Cui Tested-by: Andy Dong Reviewed-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 176 +----------------------- 2 files changed, 10 insertions(+), 172 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 4c412c3baa3ea..9225c63bb41de 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1145,6 +1145,12 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) memset(&cap, 0, sizeof(cap)); if (amdgpu_no_evict) cap.flag |= AMDGPU_CAPABILITY_PIN_MEM_FLAG; + + if (amdgpu_direct_gma_size) { + cap.flag |= AMDGPU_CAPABILITY_DIRECT_GMA_FLAG; + cap.direct_gma_size = amdgpu_direct_gma_size; + } + return copy_to_user(out, &cap, min((size_t)size, sizeof(cap))) ? -EFAULT : 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 254987e8bf16f..5f99bc12642e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -68,11 +68,6 @@ MODULE_IMPORT_NS("DMA_BUF"); #define AMDGPU_TTM_VRAM_MAX_DW_READ ((size_t)128) -struct amdgpu_dgma_node { - struct ttm_buffer_object *tbo; - struct ttm_range_mgr_node base; -}; - static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, struct ttm_tt *ttm, struct ttm_resource *bo_mem); @@ -670,11 +665,9 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, break; case AMDGPU_PL_DGMA_IMPORT: { - struct amdgpu_dgma_node *node; struct amdgpu_bo *abo; - node = container_of(mem, struct amdgpu_dgma_node, base.base); - abo = ttm_to_amdgpu_bo(node->tbo); + abo = ttm_to_amdgpu_bo(mem->bo); mem->bus.addr = abo->dgma_addr; mem->bus.offset = abo->dgma_import_base; mem->bus.is_iomem = true; @@ -2114,168 +2107,6 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) return 0; } -static inline struct amdgpu_dgma_import_mgr *to_dgma_import_mgr(struct ttm_resource_manager *man) -{ - return container_of(man, struct amdgpu_dgma_import_mgr, manager); -} - -static const struct ttm_resource_manager_func amdgpu_dgma_import_mgr_func; -/** - * amdgpu_dgma_import_mgr_init - init DGMA_import manager and DRM MM - * - * @adev: amdgpu_device pointer - * @dgma_size: maximum size of DGMA - * - * Allocate and initialize the DGMA manager. - */ -static int amdgpu_dgma_import_mgr_init(struct amdgpu_device *adev, uint64_t p_size) -{ - struct amdgpu_dgma_import_mgr *mgr = &adev->mman.dgma_import_mgr; - struct ttm_resource_manager *man = &mgr->manager; - - man->func = &amdgpu_dgma_import_mgr_func; - - ttm_resource_manager_init(man, &adev->mman.bdev, p_size); - drm_mm_init(&mgr->mm, 0, p_size); - spin_lock_init(&mgr->lock); - atomic64_set(&mgr->available, p_size); - - BUG_ON(AMDGPU_PL_DGMA_IMPORT >= TTM_NUM_MEM_TYPES); - ttm_set_driver_manager(&adev->mman.bdev, AMDGPU_PL_DGMA_IMPORT, man); - ttm_resource_manager_set_used(man, true); - return 0; -} - -/** - * amdgpu_dgma_import_mgr_fini - free and destroy DGMA import manager - * - * @adev: amdgpu_device pointer - * - * Destroy and free the DGMA import manager, returns -EBUSY if ranges are still - * allocated inside it. - */ -static void amdgpu_dgma_import_mgr_fini(struct amdgpu_device *adev) -{ - struct amdgpu_dgma_import_mgr *mgr = &adev->mman.dgma_import_mgr; - struct ttm_resource_manager *man = &mgr->manager; - int ret; - - ttm_resource_manager_set_used(man, false); - - ret = ttm_resource_manager_evict_all(&adev->mman.bdev, man); - if (ret) - return; - - spin_lock(&mgr->lock); - drm_mm_takedown(&mgr->mm); - spin_unlock(&mgr->lock); - ttm_resource_manager_cleanup(man); - ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, NULL); -} - -/** - * amdgpu_dgma_import_mgr_new - allocate a new node - * - * @man: TTM memory type manager - * @tbo: TTM BO we need this range for - * @place: placement flags and restrictions - * @mem: the resulting mem object - */ -static int amdgpu_dgma_import_mgr_new(struct ttm_resource_manager *man, - struct ttm_buffer_object *tbo, - const struct ttm_place *place, - struct ttm_resource **res) -{ - struct amdgpu_dgma_import_mgr *mgr = to_dgma_import_mgr(man); - uint32_t num_pages = PFN_UP(tbo->base.size); - struct amdgpu_dgma_node *node; - unsigned long lpfn; - int r; - - spin_lock(&mgr->lock); - if (atomic64_read(&mgr->available) < num_pages) { - spin_unlock(&mgr->lock); - return -ENOSPC; - } - atomic64_sub(num_pages, &mgr->available); - spin_unlock(&mgr->lock); - - lpfn = place->lpfn; - if (!lpfn) - lpfn = man->size; - - node = kzalloc(struct_size(node, base.mm_nodes, 1), GFP_KERNEL); - if (!node) { - r = -ENOMEM; - goto err_out; - } - - node->tbo = tbo; - ttm_resource_init(tbo, place, &node->base.base); - - spin_lock(&mgr->lock); - r = drm_mm_insert_node_in_range(&mgr->mm, &node->base.mm_nodes[0], num_pages, - tbo->page_alignment, 0, place->fpfn, - lpfn, DRM_MM_INSERT_BEST); - spin_unlock(&mgr->lock); - - if (unlikely(r)) - goto err_free; - - *res = &node->base.base; - (*res)->start = node->base.mm_nodes[0].start; - - return 0; - -err_free: - kfree(node); - -err_out: - atomic64_add(num_pages, &mgr->available); - - return r; -} - -/** - * amdgpu_dgma_import_mgr_del - free ranges - * - * @man: TTM memory type manager - * @mem: TTM memory object - * - * Free the allocated node. - */ -static void amdgpu_dgma_import_mgr_del(struct ttm_resource_manager *man, - struct ttm_resource *mem) -{ - struct amdgpu_dgma_import_mgr *mgr = to_dgma_import_mgr(man); - struct amdgpu_dgma_node *node = container_of(mem, struct amdgpu_dgma_node, base.base); - - if (node) { - spin_lock(&mgr->lock); - drm_mm_remove_node(&node->base.mm_nodes[0]); - spin_unlock(&mgr->lock); - kfree(node); - } - - atomic64_add(mem->num_pages, &mgr->available); -} - -static void amdgpu_dgma_import_mgr_debug(struct ttm_resource_manager *man, - struct drm_printer *printer) -{ - struct amdgpu_dgma_import_mgr *rman = to_dgma_import_mgr(man); - - spin_lock(&rman->lock); - drm_mm_print(&rman->mm, printer); - spin_unlock(&rman->lock); -} - -static const struct ttm_resource_manager_func amdgpu_dgma_import_mgr_func = { - .alloc = amdgpu_dgma_import_mgr_new, - .free = amdgpu_dgma_import_mgr_del, - .debug = amdgpu_dgma_import_mgr_debug -}; - static int amdgpu_direct_gma_init(struct amdgpu_device *adev) { struct amdgpu_bo *abo; @@ -2321,7 +2152,8 @@ static int amdgpu_direct_gma_init(struct amdgpu_device *adev) if (unlikely(r)) goto error_put_node; - r = amdgpu_dgma_import_mgr_init(adev, size >> PAGE_SHIFT); + r = ttm_range_man_init(&adev->mman.bdev, AMDGPU_PL_DGMA_IMPORT, + false, size >> PAGE_SHIFT); if (unlikely(r)) goto error_release_mm; @@ -2350,8 +2182,8 @@ static void amdgpu_direct_gma_fini(struct amdgpu_device *adev) if (amdgpu_direct_gma_size == 0) return; + ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DGMA_IMPORT); ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DGMA); - amdgpu_dgma_import_mgr_fini(adev); r = amdgpu_bo_reserve(adev->direct_gma.dgma_bo, false); if (r == 0) { From 9f716992bb5ac150ffd97f3c96e9dee823635968 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Oct 2022 16:25:34 +0800 Subject: [PATCH 0850/2653] drm/amdkcl: fix uninitialized bo_dev variable When bo is NULL pointer, the bo_dev variable will be used uninitialized. This is caused by 292718775885 "drm/amdkcl: fix pytorch test memory page fault" v5.18-2828-g292718775885 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 17b9401da68ff..faf409e8d13a2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1279,7 +1279,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, uint64_t flags; bool uncached; int r; - struct amdgpu_device *bo_adev; + struct amdgpu_device *bo_adev = adev; amdgpu_sync_create(&sync); if (clear) { From 80920ba7637e5a1b8578b12aa7690ff7bc6e60ea Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 31 Oct 2022 19:27:32 +0800 Subject: [PATCH 0851/2653] drm/amdkcl: test register_shrinker whether has two arguments Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/register_shrinker.m4 | 19 +++++++++++++++++++ include/kcl/kcl_shrinker.h | 10 ++++++++++ 4 files changed, 33 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 28f62454fb160..4130071863f9f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1056,6 +1056,9 @@ /* pxm_to_node() is available */ #define HAVE_PXM_TO_NODE 1 +/* whether register_shrinker(x, x) is available */ +#define HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS 1 + /* remove_conflicting_pci_framebuffers() is available */ /* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 59adba5e6e1b9..80c184db14578 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -214,6 +214,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB AC_AMDGPU_BITMAP_TO_ARR32 AC_AMDGPU_STRUCT_DRM_CRTC + AC_AMDGPU_REGISTER_SHRINKER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 b/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 new file mode 100644 index 0000000000000..903f100bf18bd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v5.16-rc1-22-g91f75eb481cf x86/MCE/AMD, EDAC/mce_amd: Support non-uniform MCA bank type enumeration +dnl # +AC_DEFUN([AC_AMDGPU_REGISTER_SHRINKER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + #include + ],[ + struct shrinker *a = NULL; + const char *b = NULL; + register_shrinker(a, b); + ],[ + AC_DEFINE(HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS, 1, + [whether register_shrinker(x, x) is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_shrinker.h b/include/kcl/kcl_shrinker.h index d8704a749d2dd..c237de4b867cf 100644 --- a/include/kcl/kcl_shrinker.h +++ b/include/kcl/kcl_shrinker.h @@ -7,4 +7,14 @@ extern void synchronize_shrinkers(void); #endif +static inline int __printf(2, 3) kcl_register_shrinker(struct shrinker *shrinker, + const char *fmt, ...) +{ +#if defined(HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS) + return register_shrinker(shrinker, fmt); +#else + return register_shrinker(shrinker); +#endif +} + #endif From d0efadb354ad3421480dff44de7fb1459f95aea1 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 12 Aug 2022 16:10:19 +0800 Subject: [PATCH 0852/2653] drm/amdkcl: test whether struct drm_dp_mst_port has member passthrough_aux It's caused by 0087990a9f572c6dd9533c973fe1072458f54b7a "drm/amd/display: consider DSC pass-through during mode validation" 99d08a5d1ad7fb76b33aabae46cd88bc7e6e6df4 "drm/amd/display: implement DSC pass-through support" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 16 ++++++++++--- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 | 23 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 41 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index bb8037a626413..dcedd159c160e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -854,16 +854,20 @@ bool dm_helpers_dp_write_dsc_enable( const struct dc_stream_state *stream, bool enable) { + struct amdgpu_dm_connector *aconnector = + (struct amdgpu_dm_connector *)stream->dm_stream_context; + struct drm_device *dev = aconnector->base.dev; +#if defined(HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX) static const uint8_t DSC_DISABLE; static const uint8_t DSC_DECODING = 0x01; static const uint8_t DSC_PASSTHROUGH = 0x02; - struct amdgpu_dm_connector *aconnector = - (struct amdgpu_dm_connector *)stream->dm_stream_context; - struct drm_device *dev = aconnector->base.dev; struct drm_dp_mst_port *port; uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE; uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE; +#else + uint8_t enable_dsc = enable ? 1 : 0; +#endif uint8_t ret = 0; if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { @@ -876,6 +880,7 @@ bool dm_helpers_dp_write_dsc_enable( return write_dsc_enable_synaptics_non_virtual_dpcd_mst( aconnector->dsc_aux, stream, enable_dsc); +#if defined(HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX) port = aconnector->mst_output_port; if (enable) { @@ -913,6 +918,11 @@ bool dm_helpers_dp_write_dsc_enable( ret); } } +#else + ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1); + DC_LOG_DC("Send DSC %s to MST RX\n", enable_dsc ? "enable" : "disable"); +#endif + } if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 044739fddd054..9137af6ccd9cd 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -2067,6 +2067,7 @@ enum dc_status dm_dp_mst_is_port_support_mode( DRM_DEBUG_DRIVER("MST_DSC require dsc but can't find common dsc config\n"); return DC_FAIL_BANDWIDTH_VALIDATE; } + #endif return DC_OK; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4130071863f9f..bb79f8bc7a5bb 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -405,6 +405,9 @@ /* drm_dp_mst_{get,put}_port_malloc() is available */ #define HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC 1 +/* struct drm_dp_mst_port has passthrough_aux member */ +/* #undef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX */ + /* struct drm_dp_mst_topology_cbs->destroy_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 new file mode 100644 index 0000000000000..a1f26ca53e149 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # commit v5.18-2579-g3af4b1f1d6e7 +dnl # "drm/dp_mst: add passthrough_aux to struct drm_dp_mst_port" +dnl +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ], [ + struct drm_dp_mst_port *dp_mst_port = NULL; + dp_mst_port->passthrough_aux = NULL; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX, 1, + [struct drm_dp_mst_port has passthrough_aux member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 80c184db14578..fbfc386f3922f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -215,6 +215,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_BITMAP_TO_ARR32 AC_AMDGPU_STRUCT_DRM_CRTC AC_AMDGPU_REGISTER_SHRINKER + AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 6b2d583699ac289be696a6eb0e2f9985aea23801 Mon Sep 17 00:00:00 2001 From: Bob zhou Date: Fri, 28 Oct 2022 16:36:06 +0800 Subject: [PATCH 0853/2653] drm/amdkcl: test whether display_info->max_dsc_bpp is available It's caused by cb4f0334768bb60ff144dd8ec1cd212dc09dcf6d "Revert "drm/amd/display: Limit max DSC target bpp for specific monitors"" affba10c1048d56a146cbb6b4ae13d0bf644a7b5 "drm/amd/display: use max_dsc_bpp in amdgpu_dm" Signed-off-by: Bob zhou Reviewed-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++++ .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 39 +++++++++++++++++++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../gpu/drm/amd/dkms/m4/drm-display-info.m4 | 19 +++++++++ 5 files changed, 72 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1d91854417eaa..52f738e893c85 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6940,8 +6940,15 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, struct dc *dc = sink->ctx->dc; u32 max_supported_bw_in_kbps, timing_bw_in_kbps; u32 dsc_max_supported_bw_in_kbps; +#ifdef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP u32 max_dsc_target_bpp_limit_override = drm_connector->display_info.max_dsc_bpp; +#else + u32 max_dsc_target_bpp_limit_override = 0; + if (stream->link && stream->link->local_sink) + max_dsc_target_bpp_limit_override = + stream->link->local_sink->edid_caps.panel_patch.max_dsc_target_bpp_limit; +#endif struct dc_dsc_config_options dsc_options = {0}; dc_dsc_get_default_config_option(dc, &dsc_options); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index dcedd159c160e..8c3af1ebaf024 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -49,6 +49,41 @@ #include "ddc_service_types.h" #include "clk_mgr.h" +#ifndef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP +struct monitor_patch_info { + unsigned int manufacturer_id; + unsigned int product_id; + void (*patch_func)(struct dc_edid_caps *edid_caps, unsigned int param); + unsigned int patch_param; +}; +static void set_max_dsc_bpp_limit(struct dc_edid_caps *edid_caps, unsigned int param); + +static const struct monitor_patch_info monitor_patch_table[] = { +{0x6D1E, 0x5BBF, set_max_dsc_bpp_limit, 15}, +{0x6D1E, 0x5B9A, set_max_dsc_bpp_limit, 15}, +}; + +static void set_max_dsc_bpp_limit(struct dc_edid_caps *edid_caps, unsigned int param) +{ + if (edid_caps) + edid_caps->panel_patch.max_dsc_target_bpp_limit = param; +} + +static int amdgpu_dm_patch_edid_caps(struct dc_edid_caps *edid_caps) +{ + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(monitor_patch_table); i++) + if ((edid_caps->manufacturer_id == monitor_patch_table[i].manufacturer_id) + && (edid_caps->product_id == monitor_patch_table[i].product_id)) { + monitor_patch_table[i].patch_func(edid_caps, monitor_patch_table[i].patch_param); + ret++; + } + + return ret; +} +#endif + static u32 edid_extract_panel_id(struct edid *edid) { return (u32)edid->mfg_id[0] << 24 | @@ -192,6 +227,10 @@ enum dc_edid_status dm_helpers_parse_edid_caps( kfree(sads); kfree(sadb); +#ifndef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP + amdgpu_dm_patch_edid_caps(edid_caps); +#endif + return result; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 9137af6ccd9cd..cc7a478d3dc7f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1064,7 +1064,11 @@ static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn) struct dc_dsc_config_options dsc_options = {0}; dc_dsc_get_default_config_option(param.sink->ctx->dc, &dsc_options); +#ifdef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16; +#else + dsc_options.max_target_bpp_limit_override_x16 = param.sink->edid_caps.panel_patch.max_dsc_target_bpp_limit * 16; +#endif kbps = div_u64((u64)pbn * 994 * 8 * 54, 64); dc_dsc_compute_config( diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index bb79f8bc7a5bb..267e5b2e7e13a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -354,6 +354,9 @@ /* struct drm_display_info has monitor_range member */ #define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 +/* display_info->max_dsc_bpp is available */ +/* #undef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP */ + /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 index 6e726111f8c16..e498f3bc94867 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 @@ -36,7 +36,26 @@ AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE], [ ]) ]) +dnl # +dnl # commit v5.18-3347-g721ed0ae5acf +dnl # drm/edid: add a quirk for two LG monitors to get them to work on 10bpc +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_MAX_DSC_BPP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_display_info *display_info = NULL; + display_info->max_dsc_bpp=0; + ],[ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP, 1, + [display_info->max_dsc_bpp is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO], [ AC_AMDGPU_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE + AC_AMDGPU_DRM_DISPLAY_INFO_MAX_DSC_BPP ]) From 49d2cc39315f33db3dc20788495c7ca6d1b77bb1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 13 Jun 2024 13:46:45 +0800 Subject: [PATCH 0854/2653] drm/amdkcl: wrap code under macro HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP It's caused by 13ba1f22181d90f4d62f9103351581b94d2442b2 "drm/amd/display: Refactor function dm_dp_mst_is_port_support_mode()" Signed-off-by: Bob Zhou Reviewed-by: Asher Song Reviewed-by: Wayne Lin --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index cc7a478d3dc7f..5034e52f5fa17 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1948,6 +1948,7 @@ enum dc_status dm_dp_mst_is_port_support_mode( { #if defined(CONFIG_DRM_AMD_DC_FP) int branch_max_throughput_mps = 0; +#if defined(HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX) && defined(HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP) struct dc_link_settings cur_link_settings; uint32_t end_to_end_bw_in_kbps = 0; uint32_t root_link_bw_in_kbps = 0; @@ -2071,7 +2072,41 @@ enum dc_status dm_dp_mst_is_port_support_mode( DRM_DEBUG_DRIVER("MST_DSC require dsc but can't find common dsc config\n"); return DC_FAIL_BANDWIDTH_VALIDATE; } +#else + int pbn; + /* Check if mode could be supported within max slot + * number of current mst link and full_pbn of mst links. + */ + int pbn_div, slot_num, max_slot_num; + enum dc_link_encoding_format link_encoding; + uint32_t stream_kbps = dc_bandwidth_in_kbps_from_timing( + &stream->timing, + dc_link_get_highest_encoding_format(stream->link)); + + pbn = kbps_to_peak_pbn(stream_kbps); + pbn_div = dm_mst_get_pbn_divider(stream->link); + slot_num = DIV_ROUND_UP(pbn, pbn_div); + + link_encoding = dc_link_get_highest_encoding_format(stream->link); + if (link_encoding == DC_LINK_ENCODING_DP_8b_10b) + max_slot_num = 63; + else if (link_encoding == DC_LINK_ENCODING_DP_128b_132b) + max_slot_num = 64; + else { + DRM_DEBUG_DRIVER("Invalid link encoding format\n"); + return DC_FAIL_BANDWIDTH_VALIDATE; + } + if (slot_num > max_slot_num || +#ifdef HAVE_DRM_DP_MST_PORT_FULL_PBN + pbn > aconnector->mst_output_port->full_pbn) { +#else + pbn > aconnector->mst_output_port->available_pbn) { +#endif + DRM_DEBUG_DRIVER("Mode can not be supported within mst links!"); + return DC_FAIL_BANDWIDTH_VALIDATE; + } +#endif #endif return DC_OK; } From 855f009bd0897970dec20debda7e15a2da0ce820 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 27 Jul 2022 10:34:23 +0800 Subject: [PATCH 0855/2653] drm/amdkcl: Test whether struct drm_dp_mst_port has full_pbn member Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 | 23 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 267e5b2e7e13a..6b05c9524ab2e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -411,6 +411,9 @@ /* struct drm_dp_mst_port has passthrough_aux member */ /* #undef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX */ +/* drm_dp_mst_port struct has full_pbn member */ +#define HAVE_DRM_DP_MST_PORT_FULL_PBN 1 + /* struct drm_dp_mst_topology_cbs->destroy_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 new file mode 100644 index 0000000000000..dc2ce8bd06835 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # commit v5.6-rc5-4-gfcf463807596 +dnl # drm/dp_mst: Use full_pbn instead of available_pbn for bandwidth checks +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ], [ + struct drm_dp_mst_port *mst_port = NULL; + mst_port->full_pbn = 0; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_PORT_FULL_PBN, 1, + [drm_dp_mst_port struct has full_pbn member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fbfc386f3922f..491bcc3ac19b3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -216,6 +216,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CRTC AC_AMDGPU_REGISTER_SHRINKER AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX + AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From fc0f33c004b801225efb357ef3f2f8ebd956c961 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 7 Nov 2022 17:50:22 +0800 Subject: [PATCH 0856/2653] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 5034e52f5fa17..008f410cf6f57 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1859,6 +1859,7 @@ int pre_validate_dsc(struct drm_atomic_state *state, return ret; } +#ifdef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX static uint32_t kbps_from_pbn(unsigned int pbn) { uint64_t kbps = (uint64_t)pbn; @@ -1889,6 +1890,7 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream, } #endif #endif /* HAVE_DRM_DP_MST_ATOMIC_CHECK */ +#endif #if defined(CONFIG_DRM_AMD_DC_FP) static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_link_bw) From 97cb86b6d1b834bf813204ebf7dad54ed7a4f91c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 20 Oct 2022 14:06:45 +0800 Subject: [PATCH 0857/2653] drm/amdkcl: fake kmap_local_* It's caused by f7e8a8be4361c6cba23fd5df693a830e8351402c "drm/amd/amdgpu: Replace kmap() with kmap_local_page()" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index fe458b9b1f4cc..475cc32dcc47c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -99,4 +99,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ From d5a4f81375286dc5d2ce676861c15ff40fa99730 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 26 Oct 2022 14:31:13 +0800 Subject: [PATCH 0858/2653] drm/amdkcl: wrap code under macro HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED It's caused by 7a462295e26244d5d21d101b9d8b33cd327e95f1 "drm/amdgpu: set fb_modifiers_not_supported in vkms" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 68dbaff20329c..a1b159275b88f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -663,7 +663,9 @@ static int amdgpu_vkms_sw_init(struct amdgpu_ip_block *ip_block) adev_to_drm(adev)->mode_config.preferred_depth = 24; adev_to_drm(adev)->mode_config.prefer_shadow = 1; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; +#endif r = amdgpu_display_modeset_create_props(adev); if (r) From 08856fb1d8274d372a09cdd6650e4b3a9ec69712 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 26 Oct 2022 15:31:13 +0800 Subject: [PATCH 0859/2653] drm/amdkcl: Modify CONFIG_DRM_AMD_DC_DSC_SUPPORT enable condition According to the Kconfig file, the CONFIG_DRM_AMD_DC_DSC_SUPPORT is selected by CONFIG_DRM_AMD_DC_DCN. So, we should enable them together. Or else, there maybe are compile errors on phantoms or the arm64 platform Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: Ia2e3f15195cf01f7521a8c0c50553484c155e842 --- drivers/gpu/drm/amd/dkms/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 4755cde423517..f7fa3166cdb33 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -188,11 +188,11 @@ ifndef CONFIG_ARM64 ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) export CONFIG_DRM_AMD_DC_DCN=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN -endif -endif export CONFIG_DRM_AMD_DC_DSC_SUPPORT=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DSC_SUPPORT +endif +endif export CONFIG_DRM_TTM_HELPER=m subdir-ccflags-y += -DCONFIG_DRM_TTM_HELPER From 9698e1e29f2f07eae7cb6f060ac88fd7436ce246 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 26 Oct 2022 12:27:04 +0800 Subject: [PATCH 0860/2653] drm/amdkcl: join multiple exclusive fences instead of overwriting old fence If old exclusive fence is not signaled, use dma_fence_chain to join old and new fence together. Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index 1477c6349dad7..67f67bcd4e2b4 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -34,6 +34,7 @@ */ #include #include +#include #include #include #include @@ -353,9 +354,21 @@ static void dma_resv_add_excl_fence(struct dma_resv *obj, struct dma_fence *fence) { struct dma_fence *old_fence = dma_resv_excl_fence(obj); + struct dma_fence_chain *chain; dma_resv_assert_held(obj); + if (old_fence && !dma_fence_is_signaled(old_fence)) { + + chain = dma_fence_chain_alloc(); + if (unlikely(!chain)) + pr_err("dma_resv_add_excl_fence OOM\n"); + else { + dma_fence_chain_init(chain, dma_fence_get(old_fence), dma_fence_get(fence), 1); + fence = &chain->base; + } + } + dma_fence_get(fence); write_seqcount_begin(&obj->seq); From fb9d221ff1841d868bc61bddd75557004c36f43e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 27 Oct 2022 17:14:12 +0800 Subject: [PATCH 0861/2653] drm/amdkcl: Add drm buddy Add drm_buddy.c as a new module Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I945c93d973c6bb9e6a401acce79789c80b58a2da --- drivers/gpu/drm/amd/amdkcl/files | 2 +- drivers/gpu/drm/amd/dkms/Makefile | 6 ++++++ drivers/gpu/drm/amd/dkms/dkms.conf | 4 ++++ drivers/gpu/drm/amd/dkms/sources | 2 ++ 4 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/files b/drivers/gpu/drm/amd/amdkcl/files index 6cc9587ebc525..20534a90dbb86 100644 --- a/drivers/gpu/drm/amd/amdkcl/files +++ b/drivers/gpu/drm/amd/amdkcl/files @@ -1 +1 @@ -FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c drm_gem_ttm_helper.c" +FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c drm_gem_ttm_helper.c drm_buddy.c" diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index f7fa3166cdb33..eec0d7868d7c2 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -202,4 +202,10 @@ CFLAGS_drm_gem_ttm_helper.o += -include $(src)/ttm/backport/backport.h \ amddrm_ttm_helper-y := drm_gem_ttm_helper.o obj-$(CONFIG_DRM_TTM_HELPER) += amddrm_ttm_helper.o +export CONFIG_DRM_BUDDY=m +subdir-ccflags-y += -DCONFIG_DRM_BUDDY +CFLAGS_drm_buddy.o += -DHAVE_CONFIG_H +amddrm_buddy-y := drm_buddy.o +obj-$(CONFIG_DRM_BUDDY) += amddrm_buddy.o + obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index a4fde02caa219..caa34f979ef96 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -26,6 +26,10 @@ BUILT_MODULE_NAME[4]="amddrm_ttm_helper" BUILT_MODULE_LOCATION[4]="." DEST_MODULE_LOCATION[4]="/kernel/drivers/gpu/drm" +BUILT_MODULE_NAME[5]="amddrm_buddy" +BUILT_MODULE_LOCATION[5]="." +DEST_MODULE_LOCATION[5]="/kernel/drivers/gpu/drm" + MAKE[0]="make TTM_NAME=${BUILT_MODULE_NAME[1]} \ SCHED_NAME=${BUILT_MODULE_NAME[3]} \ -C $kernel_source_dir \ diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources index 60563cf6abf8e..373b38d0d2325 100644 --- a/drivers/gpu/drm/amd/dkms/sources +++ b/drivers/gpu/drm/amd/dkms/sources @@ -31,3 +31,5 @@ include/kcl/reservation.h include/linux/ include/uapi/linux/kfd_sysfs.h include/uapi/linux/ drivers/gpu/drm/drm_gem_ttm_helper.c . include/drm/drm_gem_ttm_helper.h include/drm/ +drivers/gpu/drm/drm_buddy.c . +include/drm/drm_buddy.h include/drm/ From 06dce89988dea27fd6efe4a83cc73f231881e361 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 28 Oct 2022 15:10:18 +0800 Subject: [PATCH 0862/2653] drm/amdkcl:Remove kcl_drm_buddy related file Because the drm_buddy is added as a module, these files can be removed now Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: Idead98ab257bcdc689de6257a9aea88a0ddbdb02 --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c | 783 --------------------- drivers/gpu/drm/amd/amdkcl/main.c | 12 +- drivers/gpu/drm/amd/backport/backport.h | 1 - include/kcl/header/drm/drm_buddy.h | 11 - include/kcl/kcl_drm_buddy.h | 171 ----- 6 files changed, 2 insertions(+), 978 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c delete mode 100644 include/kcl/header/drm/drm_buddy.h delete mode 100644 include/kcl/kcl_drm_buddy.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 0104acd2fd133..8e3650b52cfc0 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_drm_buddy.o + kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c deleted file mode 100644 index 0d18f0d43b68d..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c +++ /dev/null @@ -1,783 +0,0 @@ -// SPDX-License-Identifier: MIT -/* - * Copyright © 2021 Intel Corporation - */ - -#include -#ifndef HAVE_DRM_DRM_BUDDY_H - -#include - -static struct kmem_cache *slab_blocks; - -static struct drm_buddy_block *drm_block_alloc(struct drm_buddy *mm, - struct drm_buddy_block *parent, - unsigned int order, - u64 offset) -{ - struct drm_buddy_block *block; - - BUG_ON(order > DRM_BUDDY_MAX_ORDER); - - block = kmem_cache_zalloc(slab_blocks, GFP_KERNEL); - if (!block) - return NULL; - - block->header = offset; - block->header |= order; - block->parent = parent; - - BUG_ON(block->header & DRM_BUDDY_HEADER_UNUSED); - return block; -} - -static void drm_block_free(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - kmem_cache_free(slab_blocks, block); -} - -static void mark_allocated(struct drm_buddy_block *block) -{ - block->header &= ~DRM_BUDDY_HEADER_STATE; - block->header |= DRM_BUDDY_ALLOCATED; - - list_del(&block->link); -} - -static void mark_free(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - block->header &= ~DRM_BUDDY_HEADER_STATE; - block->header |= DRM_BUDDY_FREE; - - list_add(&block->link, - &mm->free_list[drm_buddy_block_order(block)]); -} - -static void mark_split(struct drm_buddy_block *block) -{ - block->header &= ~DRM_BUDDY_HEADER_STATE; - block->header |= DRM_BUDDY_SPLIT; - - list_del(&block->link); -} - -/** - * drm_buddy_init - init memory manager - * - * @mm: DRM buddy manager to initialize - * @size: size in bytes to manage - * @chunk_size: minimum page size in bytes for our allocations - * - * Initializes the memory manager and its resources. - * - * Returns: - * 0 on success, error code on failure. - */ -int kcl_drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) -{ - unsigned int i; - u64 offset; - - if (size < chunk_size) - return -EINVAL; - - if (chunk_size < PAGE_SIZE) - return -EINVAL; - - if (!is_power_of_2(chunk_size)) - return -EINVAL; - - size = round_down(size, chunk_size); - - mm->size = size; - mm->avail = size; - mm->chunk_size = chunk_size; - mm->max_order = ilog2(size) - ilog2(chunk_size); - - BUG_ON(mm->max_order > DRM_BUDDY_MAX_ORDER); - - mm->free_list = kmalloc_array(mm->max_order + 1, - sizeof(struct list_head), - GFP_KERNEL); - if (!mm->free_list) - return -ENOMEM; - - for (i = 0; i <= mm->max_order; ++i) - INIT_LIST_HEAD(&mm->free_list[i]); - - mm->n_roots = hweight64(size); - - mm->roots = kmalloc_array(mm->n_roots, - sizeof(struct drm_buddy_block *), - GFP_KERNEL); - if (!mm->roots) - goto out_free_list; - - offset = 0; - i = 0; - - /* - * Split into power-of-two blocks, in case we are given a size that is - * not itself a power-of-two. - */ - do { - struct drm_buddy_block *root; - unsigned int order; - u64 root_size; - - root_size = rounddown_pow_of_two(size); - order = ilog2(root_size) - ilog2(chunk_size); - - root = drm_block_alloc(mm, NULL, order, offset); - if (!root) - goto out_free_roots; - - mark_free(mm, root); - - BUG_ON(i > mm->max_order); - BUG_ON(drm_buddy_block_size(mm, root) < chunk_size); - - mm->roots[i] = root; - - offset += root_size; - size -= root_size; - i++; - } while (size); - - return 0; - -out_free_roots: - while (i--) - drm_block_free(mm, mm->roots[i]); - kfree(mm->roots); -out_free_list: - kfree(mm->free_list); - return -ENOMEM; -} -EXPORT_SYMBOL(kcl_drm_buddy_init); - -/** - * drm_buddy_fini - tear down the memory manager - * - * @mm: DRM buddy manager to free - * - * Cleanup memory manager resources and the freelist - */ -void kcl_drm_buddy_fini(struct drm_buddy *mm) -{ - int i; - - for (i = 0; i < mm->n_roots; ++i) { - WARN_ON(!drm_buddy_block_is_free(mm->roots[i])); - drm_block_free(mm, mm->roots[i]); - } - - WARN_ON(mm->avail != mm->size); - - kfree(mm->roots); - kfree(mm->free_list); -} -EXPORT_SYMBOL(kcl_drm_buddy_fini); - -static int split_block(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - unsigned int block_order = drm_buddy_block_order(block) - 1; - u64 offset = drm_buddy_block_offset(block); - - BUG_ON(!drm_buddy_block_is_free(block)); - BUG_ON(!drm_buddy_block_order(block)); - - block->left = drm_block_alloc(mm, block, block_order, offset); - if (!block->left) - return -ENOMEM; - - block->right = drm_block_alloc(mm, block, block_order, - offset + (mm->chunk_size << block_order)); - if (!block->right) { - drm_block_free(mm, block->left); - return -ENOMEM; - } - - mark_free(mm, block->left); - mark_free(mm, block->right); - - mark_split(block); - - return 0; -} - -static struct drm_buddy_block * -__get_buddy(struct drm_buddy_block *block) -{ - struct drm_buddy_block *parent; - - parent = block->parent; - if (!parent) - return NULL; - - if (parent->left == block) - return parent->right; - - return parent->left; -} - -/** - * drm_get_buddy - get buddy address - * - * @block: DRM buddy block - * - * Returns the corresponding buddy block for @block, or NULL - * if this is a root block and can't be merged further. - * Requires some kind of locking to protect against - * any concurrent allocate and free operations. - */ -struct drm_buddy_block * -kcl_drm_get_buddy(struct drm_buddy_block *block) -{ - return __get_buddy(block); -} -EXPORT_SYMBOL(kcl_drm_get_buddy); - -static void __drm_buddy_free(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - struct drm_buddy_block *parent; - - while ((parent = block->parent)) { - struct drm_buddy_block *buddy; - - buddy = __get_buddy(block); - - if (!drm_buddy_block_is_free(buddy)) - break; - - list_del(&buddy->link); - - drm_block_free(mm, block); - drm_block_free(mm, buddy); - - block = parent; - } - - mark_free(mm, block); -} - -/** - * drm_buddy_free_block - free a block - * - * @mm: DRM buddy manager - * @block: block to be freed - */ -void kcl_drm_buddy_free_block(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - BUG_ON(!drm_buddy_block_is_allocated(block)); - mm->avail += drm_buddy_block_size(mm, block); - __drm_buddy_free(mm, block); -} -EXPORT_SYMBOL(kcl_drm_buddy_free_block); - -/** - * drm_buddy_free_list - free blocks - * - * @mm: DRM buddy manager - * @objects: input list head to free blocks - */ -void kcl_drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects) -{ - struct drm_buddy_block *block, *on; - - list_for_each_entry_safe(block, on, objects, link) { - drm_buddy_free_block(mm, block); - cond_resched(); - } - INIT_LIST_HEAD(objects); -} -EXPORT_SYMBOL(kcl_drm_buddy_free_list); - -static inline bool overlaps(u64 s1, u64 e1, u64 s2, u64 e2) -{ - return s1 <= e2 && e1 >= s2; -} - -static inline bool contains(u64 s1, u64 e1, u64 s2, u64 e2) -{ - return s1 <= s2 && e1 >= e2; -} - -static struct drm_buddy_block * -alloc_range_bias(struct drm_buddy *mm, - u64 start, u64 end, - unsigned int order) -{ - struct drm_buddy_block *block; - struct drm_buddy_block *buddy; - LIST_HEAD(dfs); - int err; - int i; - - end = end - 1; - - for (i = 0; i < mm->n_roots; ++i) - list_add_tail(&mm->roots[i]->tmp_link, &dfs); - - do { - u64 block_start; - u64 block_end; - - block = list_first_entry_or_null(&dfs, - struct drm_buddy_block, - tmp_link); - if (!block) - break; - - list_del(&block->tmp_link); - - if (drm_buddy_block_order(block) < order) - continue; - - block_start = drm_buddy_block_offset(block); - block_end = block_start + drm_buddy_block_size(mm, block) - 1; - - if (!overlaps(start, end, block_start, block_end)) - continue; - - if (drm_buddy_block_is_allocated(block)) - continue; - - if (contains(start, end, block_start, block_end) && - order == drm_buddy_block_order(block)) { - /* - * Find the free block within the range. - */ - if (drm_buddy_block_is_free(block)) - return block; - - continue; - } - - if (!drm_buddy_block_is_split(block)) { - err = split_block(mm, block); - if (unlikely(err)) - goto err_undo; - } - - list_add(&block->right->tmp_link, &dfs); - list_add(&block->left->tmp_link, &dfs); - } while (1); - - return ERR_PTR(-ENOSPC); - -err_undo: - /* - * We really don't want to leave around a bunch of split blocks, since - * bigger is better, so make sure we merge everything back before we - * free the allocated blocks. - */ - buddy = __get_buddy(block); - if (buddy && - (drm_buddy_block_is_free(block) && - drm_buddy_block_is_free(buddy))) - __drm_buddy_free(mm, block); - return ERR_PTR(err); -} - -static struct drm_buddy_block * -get_maxblock(struct list_head *head) -{ - struct drm_buddy_block *max_block = NULL, *node; - - max_block = list_first_entry_or_null(head, - struct drm_buddy_block, - link); - if (!max_block) - return NULL; - - list_for_each_entry(node, head, link) { - if (drm_buddy_block_offset(node) > - drm_buddy_block_offset(max_block)) - max_block = node; - } - - return max_block; -} - -static struct drm_buddy_block * -alloc_from_freelist(struct drm_buddy *mm, - unsigned int order, - unsigned long flags) -{ - struct drm_buddy_block *block = NULL; - unsigned int i; - int err; - - for (i = order; i <= mm->max_order; ++i) { - if (flags & DRM_BUDDY_TOPDOWN_ALLOCATION) { - block = get_maxblock(&mm->free_list[i]); - if (block) - break; - } else { - block = list_first_entry_or_null(&mm->free_list[i], - struct drm_buddy_block, - link); - if (block) - break; - } - } - - if (!block) - return ERR_PTR(-ENOSPC); - - BUG_ON(!drm_buddy_block_is_free(block)); - - while (i != order) { - err = split_block(mm, block); - if (unlikely(err)) - goto err_undo; - - block = block->right; - i--; - } - return block; - -err_undo: - if (i != order) - __drm_buddy_free(mm, block); - return ERR_PTR(err); -} - -static int __alloc_range(struct drm_buddy *mm, - struct list_head *dfs, - u64 start, u64 size, - struct list_head *blocks) -{ - struct drm_buddy_block *block; - struct drm_buddy_block *buddy; - LIST_HEAD(allocated); - u64 end; - int err; - - end = start + size - 1; - - do { - u64 block_start; - u64 block_end; - - block = list_first_entry_or_null(dfs, - struct drm_buddy_block, - tmp_link); - if (!block) - break; - - list_del(&block->tmp_link); - - block_start = drm_buddy_block_offset(block); - block_end = block_start + drm_buddy_block_size(mm, block) - 1; - - if (!overlaps(start, end, block_start, block_end)) - continue; - - if (drm_buddy_block_is_allocated(block)) { - err = -ENOSPC; - goto err_free; - } - - if (contains(start, end, block_start, block_end)) { - if (!drm_buddy_block_is_free(block)) { - err = -ENOSPC; - goto err_free; - } - - mark_allocated(block); - mm->avail -= drm_buddy_block_size(mm, block); - list_add_tail(&block->link, &allocated); - continue; - } - - if (!drm_buddy_block_is_split(block)) { - err = split_block(mm, block); - if (unlikely(err)) - goto err_undo; - } - - list_add(&block->right->tmp_link, dfs); - list_add(&block->left->tmp_link, dfs); - } while (1); - - list_splice_tail(&allocated, blocks); - return 0; - -err_undo: - /* - * We really don't want to leave around a bunch of split blocks, since - * bigger is better, so make sure we merge everything back before we - * free the allocated blocks. - */ - buddy = __get_buddy(block); - if (buddy && - (drm_buddy_block_is_free(block) && - drm_buddy_block_is_free(buddy))) - __drm_buddy_free(mm, block); - -err_free: - drm_buddy_free_list(mm, &allocated); - return err; -} - -static int __drm_buddy_alloc_range(struct drm_buddy *mm, - u64 start, - u64 size, - struct list_head *blocks) -{ - LIST_HEAD(dfs); - int i; - - for (i = 0; i < mm->n_roots; ++i) - list_add_tail(&mm->roots[i]->tmp_link, &dfs); - - return __alloc_range(mm, &dfs, start, size, blocks); -} - -/** - * drm_buddy_block_trim - free unused pages - * - * @mm: DRM buddy manager - * @new_size: original size requested - * @blocks: Input and output list of allocated blocks. - * MUST contain single block as input to be trimmed. - * On success will contain the newly allocated blocks - * making up the @new_size. Blocks always appear in - * ascending order - * - * For contiguous allocation, we round up the size to the nearest - * power of two value, drivers consume *actual* size, so remaining - * portions are unused and can be optionally freed with this function - * - * Returns: - * 0 on success, error code on failure. - */ -int kcl_drm_buddy_block_trim(struct drm_buddy *mm, - u64 new_size, - struct list_head *blocks) -{ - struct drm_buddy_block *parent; - struct drm_buddy_block *block; - LIST_HEAD(dfs); - u64 new_start; - int err; - - if (!list_is_singular(blocks)) - return -EINVAL; - - block = list_first_entry(blocks, - struct drm_buddy_block, - link); - - if (WARN_ON(!drm_buddy_block_is_allocated(block))) - return -EINVAL; - - if (new_size > drm_buddy_block_size(mm, block)) - return -EINVAL; - - if (!new_size || !IS_ALIGNED(new_size, mm->chunk_size)) - return -EINVAL; - - if (new_size == drm_buddy_block_size(mm, block)) - return 0; - - list_del(&block->link); - mark_free(mm, block); - mm->avail += drm_buddy_block_size(mm, block); - - /* Prevent recursively freeing this node */ - parent = block->parent; - block->parent = NULL; - - new_start = drm_buddy_block_offset(block); - list_add(&block->tmp_link, &dfs); - err = __alloc_range(mm, &dfs, new_start, new_size, blocks); - if (err) { - mark_allocated(block); - mm->avail -= drm_buddy_block_size(mm, block); - list_add(&block->link, blocks); - } - - block->parent = parent; - return err; -} -EXPORT_SYMBOL(kcl_drm_buddy_block_trim); - -/** - * drm_buddy_alloc_blocks - allocate power-of-two blocks - * - * @mm: DRM buddy manager to allocate from - * @start: start of the allowed range for this block - * @end: end of the allowed range for this block - * @size: size of the allocation - * @min_page_size: alignment of the allocation - * @blocks: output list head to add allocated blocks - * @flags: DRM_BUDDY_*_ALLOCATION flags - * - * alloc_range_bias() called on range limitations, which traverses - * the tree and returns the desired block. - * - * alloc_from_freelist() called when *no* range restrictions - * are enforced, which picks the block from the freelist. - * - * Returns: - * 0 on success, error code on failure. - */ -int kcl_drm_buddy_alloc_blocks(struct drm_buddy *mm, - u64 start, u64 end, u64 size, - u64 min_page_size, - struct list_head *blocks, - unsigned long flags) -{ - struct drm_buddy_block *block = NULL; - unsigned int min_order, order; - unsigned long pages; - LIST_HEAD(allocated); - int err; - - if (size < mm->chunk_size) - return -EINVAL; - - if (min_page_size < mm->chunk_size) - return -EINVAL; - - if (!is_power_of_2(min_page_size)) - return -EINVAL; - - if (!IS_ALIGNED(start | end | size, mm->chunk_size)) - return -EINVAL; - - if (end > mm->size) - return -EINVAL; - - if (range_overflows(start, size, mm->size)) - return -EINVAL; - - /* Actual range allocation */ - if (start + size == end) - return __drm_buddy_alloc_range(mm, start, size, blocks); - - if (!IS_ALIGNED(size, min_page_size)) - return -EINVAL; - - pages = size >> ilog2(mm->chunk_size); - order = fls(pages) - 1; - min_order = ilog2(min_page_size) - ilog2(mm->chunk_size); - - do { - order = min(order, (unsigned int)fls(pages) - 1); - BUG_ON(order > mm->max_order); - BUG_ON(order < min_order); - - do { - if (flags & DRM_BUDDY_RANGE_ALLOCATION) - /* Allocate traversing within the range */ - block = alloc_range_bias(mm, start, end, order); - else - /* Allocate from freelist */ - block = alloc_from_freelist(mm, order, flags); - - if (!IS_ERR(block)) - break; - - if (order-- == min_order) { - err = -ENOSPC; - goto err_free; - } - } while (1); - - mark_allocated(block); - mm->avail -= drm_buddy_block_size(mm, block); - //kmemleak_update_trace(block); - list_add_tail(&block->link, &allocated); - - pages -= BIT(order); - - if (!pages) - break; - } while (1); - - list_splice_tail(&allocated, blocks); - return 0; - -err_free: - drm_buddy_free_list(mm, &allocated); - return err; -} -EXPORT_SYMBOL(kcl_drm_buddy_alloc_blocks); - -/** - * drm_buddy_block_print - print block information - * - * @mm: DRM buddy manager - * @block: DRM buddy block - * @p: DRM printer to use - */ -void kcl_drm_buddy_block_print(struct drm_buddy *mm, - struct drm_buddy_block *block, - struct drm_printer *p) -{ - u64 start = drm_buddy_block_offset(block); - u64 size = drm_buddy_block_size(mm, block); - - drm_printf(p, "%#018llx-%#018llx: %llu\n", start, start + size, size); -} -EXPORT_SYMBOL(kcl_drm_buddy_block_print); - -/** - * drm_buddy_print - print allocator state - * - * @mm: DRM buddy manager - * @p: DRM printer to use - */ -void kcl_drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p) -{ - int order; - - drm_printf(p, "chunk_size: %lluKiB, total: %lluMiB, free: %lluMiB\n", - mm->chunk_size >> 10, mm->size >> 20, mm->avail >> 20); - - for (order = mm->max_order; order >= 0; order--) { - struct drm_buddy_block *block; - u64 count = 0, free; - - list_for_each_entry(block, &mm->free_list[order], link) { - BUG_ON(!drm_buddy_block_is_free(block)); - count++; - } - - drm_printf(p, "order-%d ", order); - - free = count * (mm->chunk_size << order); - if (free < SZ_1M) - drm_printf(p, "free: %lluKiB", free >> 10); - else - drm_printf(p, "free: %lluMiB", free >> 20); - - drm_printf(p, ", pages: %llu\n", count); - } -} -EXPORT_SYMBOL(kcl_drm_buddy_print); - -void amdkcl_drm_buddy_module_exit(void) -{ - kmem_cache_destroy(slab_blocks); -} - -int amdkcl_drm_buddy_module_init(void) -{ - slab_blocks = KMEM_CACHE(drm_buddy_block, 0); - if (!slab_blocks) - return -ENOMEM; - - return 0; -} - -#endif /* HAVE_DRM_DRM_BUDDY_H */ \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index a98196918c9f9..3e01ddf3f82a6 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -16,11 +16,6 @@ extern void amdkcl_sched_init(void); extern void amdkcl_numa_init(void); extern void amdkcl_workqueue_init(void); -#ifndef HAVE_DRM_DRM_BUDDY_H -extern int amdkcl_drm_buddy_module_init(void); -extern void amdkcl_drm_buddy_module_exit(void); -#endif - int __init amdkcl_init(void) { amdkcl_symbol_init(); @@ -36,9 +31,6 @@ int __init amdkcl_init(void) amdkcl_sched_init(); amdkcl_numa_init(); amdkcl_workqueue_init(); -#ifndef HAVE_DRM_DRM_BUDDY_H - amdkcl_drm_buddy_module_init(); -#endif return 0; } @@ -46,9 +38,7 @@ module_init(amdkcl_init); void __exit amdkcl_exit(void) { -#ifndef HAVE_DRM_DRM_BUDDY_H - amdkcl_drm_buddy_module_exit(); -#endif + } module_exit(amdkcl_exit); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 475cc32dcc47c..b57813353fe7b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -98,6 +98,5 @@ #include #include #include -#include #include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/header/drm/drm_buddy.h b/include/kcl/header/drm/drm_buddy.h deleted file mode 100644 index 37aa64b07a8e6..0000000000000 --- a/include/kcl/header/drm/drm_buddy.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER_DRM_BUDDY_H_H_ -#define _KCL_HEADER_DRM_BUDDY_H_H_ - -#ifdef HAVE_DRM_DRM_BUDDY_H -#include_next -#else -#include -#endif - -#endif diff --git a/include/kcl/kcl_drm_buddy.h b/include/kcl/kcl_drm_buddy.h deleted file mode 100644 index 4db95edb25369..0000000000000 --- a/include/kcl/kcl_drm_buddy.h +++ /dev/null @@ -1,171 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright © 2021 Intel Corporation - */ -#ifndef __KCL_KCL_DRM_BUDDY_H__ -#define __KCL_KCL_DRM_BUDDY_H__ - -#ifdef HAVE_DRM_DRM_BUDDY_H -#include -#else -#include -#include -#include -#include -#include -#include - -#define range_overflows(start, size, max) ({ \ - typeof(start) start__ = (start); \ - typeof(size) size__ = (size); \ - typeof(max) max__ = (max); \ - (void)(&start__ == &size__); \ - (void)(&start__ == &max__); \ - start__ >= max__ || size__ > max__ - start__; \ -}) - -#define DRM_BUDDY_RANGE_ALLOCATION (1 << 0) -#define DRM_BUDDY_TOPDOWN_ALLOCATION (1 << 1) - -struct drm_buddy_block { -#define DRM_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12) -#define DRM_BUDDY_HEADER_STATE GENMASK_ULL(11, 10) -#define DRM_BUDDY_ALLOCATED (1 << 10) -#define DRM_BUDDY_FREE (2 << 10) -#define DRM_BUDDY_SPLIT (3 << 10) -/* Free to be used, if needed in the future */ -#define DRM_BUDDY_HEADER_UNUSED GENMASK_ULL(9, 6) -#define DRM_BUDDY_HEADER_ORDER GENMASK_ULL(5, 0) - u64 header; - - struct drm_buddy_block *left; - struct drm_buddy_block *right; - struct drm_buddy_block *parent; - - void *private; /* owned by creator */ - - /* - * While the block is allocated by the user through drm_buddy_alloc*, - * the user has ownership of the link, for example to maintain within - * a list, if so desired. As soon as the block is freed with - * drm_buddy_free* ownership is given back to the mm. - */ - struct list_head link; - struct list_head tmp_link; -}; - -/* Order-zero must be at least PAGE_SIZE */ -#define DRM_BUDDY_MAX_ORDER (63 - PAGE_SHIFT) - -/* - * Binary Buddy System. - * - * Locking should be handled by the user, a simple mutex around - * drm_buddy_alloc* and drm_buddy_free* should suffice. - */ -struct drm_buddy { - /* Maintain a free list for each order. */ - struct list_head *free_list; - - /* - * Maintain explicit binary tree(s) to track the allocation of the - * address space. This gives us a simple way of finding a buddy block - * and performing the potentially recursive merge step when freeing a - * block. Nodes are either allocated or free, in which case they will - * also exist on the respective free list. - */ - struct drm_buddy_block **roots; - - /* - * Anything from here is public, and remains static for the lifetime of - * the mm. Everything above is considered do-not-touch. - */ - unsigned int n_roots; - unsigned int max_order; - - /* Must be at least PAGE_SIZE */ - u64 chunk_size; - u64 size; - u64 avail; -}; - -static inline u64 -drm_buddy_block_offset(struct drm_buddy_block *block) -{ - return block->header & DRM_BUDDY_HEADER_OFFSET; -} - -static inline unsigned int -drm_buddy_block_order(struct drm_buddy_block *block) -{ - return block->header & DRM_BUDDY_HEADER_ORDER; -} - -static inline unsigned int -drm_buddy_block_state(struct drm_buddy_block *block) -{ - return block->header & DRM_BUDDY_HEADER_STATE; -} - -static inline bool -drm_buddy_block_is_allocated(struct drm_buddy_block *block) -{ - return drm_buddy_block_state(block) == DRM_BUDDY_ALLOCATED; -} - -static inline bool -drm_buddy_block_is_free(struct drm_buddy_block *block) -{ - return drm_buddy_block_state(block) == DRM_BUDDY_FREE; -} - -static inline bool -drm_buddy_block_is_split(struct drm_buddy_block *block) -{ - return drm_buddy_block_state(block) == DRM_BUDDY_SPLIT; -} - -static inline u64 -drm_buddy_block_size(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - return mm->chunk_size << drm_buddy_block_order(block); -} - -int kcl_drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size); - -void kcl_drm_buddy_fini(struct drm_buddy *mm); - -struct drm_buddy_block * -kcl_drm_get_buddy(struct drm_buddy_block *block); - -int kcl_drm_buddy_alloc_blocks(struct drm_buddy *mm, - u64 start, u64 end, u64 size, - u64 min_page_size, - struct list_head *blocks, - unsigned long flags); - -int kcl_drm_buddy_block_trim(struct drm_buddy *mm, - u64 new_size, - struct list_head *blocks); - -void kcl_drm_buddy_free_block(struct drm_buddy *mm, struct drm_buddy_block *block); - -void kcl_drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects); - -void kcl_drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p); -void kcl_drm_buddy_block_print(struct drm_buddy *mm, - struct drm_buddy_block *block, - struct drm_printer *p); - -#define drm_buddy_print kcl_drm_buddy_print -#define drm_buddy_block_print kcl_drm_buddy_block_print -#define drm_buddy_alloc_blocks kcl_drm_buddy_alloc_blocks -#define drm_buddy_block_trim kcl_drm_buddy_block_trim -#define drm_buddy_free_list kcl_drm_buddy_free_list -#define drm_buddy_free_block kcl_drm_buddy_free_block -#define drm_get_buddy kcl_drm_get_buddy -#define drm_buddy_fini kcl_drm_buddy_fini -#define drm_buddy_init kcl_drm_buddy_init -#endif /* HAVE_DRM_DRM_BUDDY_H */ -#endif /* __KCL_KCL_DRM_BUDDY_H__ */ From 3e758a3129ad249e67fa90cd5b66bd51f41890c6 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 8 Nov 2022 12:59:15 +0800 Subject: [PATCH 0863/2653] drm/amdkcl: Fix reference counting error of dma_fence_chain that causing memory leak In the code path of creating a new dma_fence_chain object, the dma_fence_chain_init() function has initialized the reference count. The additional incorrect dma_fence_get(fence) call will increase the reference count from 1 to 2. This will lead to memory leak of dma_fence_chain objects. This fix patch "be5685d2b0f9 drm/amdkcl: join multiple exclusive fences instead of overwriting old fence" Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index 67f67bcd4e2b4..8edf3fccac3e9 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -367,9 +367,10 @@ static void dma_resv_add_excl_fence(struct dma_resv *obj, dma_fence_chain_init(chain, dma_fence_get(old_fence), dma_fence_get(fence), 1); fence = &chain->base; } + } else { + dma_fence_get(fence); } - dma_fence_get(fence); write_seqcount_begin(&obj->seq); /* write_seqcount_begin provides the necessary memory barrier */ From cbe608c5f7601755eb8b0ca3106f35ffc191fc16 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 8 Nov 2022 14:41:20 +0800 Subject: [PATCH 0864/2653] drm/amdkcl: Wrap the code under macro CONFIG_DRM_AMD_DC_DCN Wrap the code under macro CONFIG_DRM_AMD_DC_DCN to fix the compile error. Signed-off-by: Ma Jun Reviewed-by: Leslie Shi Change-Id: I3488aa2fe6d706f69e8741e1cb908cdda0e02bf4 --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++ drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index f058319219365..39b85d4867256 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1389,10 +1389,12 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context) * The OTG is set to disable on falling edge of VUPDATE so the plane disable * will still get it's double buffer update. */ +#ifdef CONFIG_DRM_AMD_DC_DCN if (is_phantom) { if (tg->funcs->disable_phantom_crtc) tg->funcs->disable_phantom_crtc(tg); } +#endif } } diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index 94896379ded9a..17ddcaeaa3636 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -307,7 +307,9 @@ static const struct timing_generator_funcs dcn32_tg_funcs = { .enable_crtc = optc32_enable_crtc, .disable_crtc = optc32_disable_crtc, .phantom_crtc_post_enable = optc32_phantom_crtc_post_enable, +#ifdef CONFIG_DRM_AMD_DC_DCN .disable_phantom_crtc = optc32_disable_phantom_otg, +#endif /* used by enable_timing_synchronization. Not need for FPGA */ .is_counter_moving = optc1_is_counter_moving, .get_position = optc1_get_position, From 0f5ac8a934b04d921deac04d40aed5be35153178 Mon Sep 17 00:00:00 2001 From: Jeremy Newton Date: Tue, 15 Nov 2022 17:50:11 -0500 Subject: [PATCH 0865/2653] Disable weak module updates This is not supported on some OS, such as RHEL and Fedora, so we should disable it since it's harmless to disable for all OS. Signed-off-by: Jeremy Newton Reviewed-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/dkms.conf | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index caa34f979ef96..bf06588ea6b9c 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -2,6 +2,8 @@ PACKAGE_NAME="amdgpu" PACKAGE_VERSION="1.0" AUTOINSTALL="yes" PRE_BUILD="amd/dkms/pre-build.sh $kernelver" +# not all OS supports weak module updates +NO_WEAK_MODULES="yes" # not work with RHEL DKMS #MODULES_CONF[0]="blacklist radeon" From 9fdeadcf91df5e05b0ccb7df38e3e88f0591d4f1 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Mon, 29 Aug 2022 22:28:18 -0400 Subject: [PATCH 0866/2653] drm/amdkfd: disable cooperative launch in gfx11 debug mode Since SA1 must be disabled during GFX11 debug mode, cooperative launch may shader hang on an indefinite barrier wait due to assymetrically enabled SEs. Prevent the debugger from attaching to a GWS using process or having the attached process create GWS using queues. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index b4a5593cf342a..a4f073969c55e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -601,7 +601,9 @@ static int kfd_gws_init(struct kfd_node *node) (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 0) && kfd->mec2_fw_version < 0x1b6) || (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1) - && kfd->mec2_fw_version < 0x30)) + && kfd->mec2_fw_version < 0x30) || + (KFD_GC_VERSION(kfd) >= IP_VERSION(11, 0, 0) && + KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0))) kfd->gws_debug_workaround = true; return ret; From f9332515a680a08d428a5f3faacaf3a88c802e66 Mon Sep 17 00:00:00 2001 From: Bob zhou Date: Mon, 14 Nov 2022 15:34:16 +0800 Subject: [PATCH 0867/2653] drm/amdkcl: Test whether drm_mode_init() is available Signed-off-by: Bob zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c | 12 ++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-mode-init.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_modes.h | 4 ++++ 5 files changed, 36 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-mode-init.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c index bf57f999e4fc2..e01b01bd4ae09 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c @@ -39,3 +39,15 @@ amdkcl_dummy_symbol(drm_mode_is_420_only, bool, return false, amdkcl_dummy_symbol(drm_mode_is_420_also, bool, return false, const struct drm_display_info *display, const struct drm_display_mode *mode) #endif + +#ifndef HAVE_DRM_MODE_INIT +void drm_mode_init(struct drm_display_mode *dst, const struct drm_display_mode *src) +{ + struct list_head head = dst->head; + + memset(dst, 0, sizeof(*dst)); + *dst = *src; + dst->head = head; +} +EXPORT_SYMBOL(drm_mode_init); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6b05c9524ab2e..647f60e742492 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -683,6 +683,9 @@ /* drm_mode_is_420_xxx() is available */ #define HAVE_DRM_MODE_IS_420_XXX 1 +/* drm_mode_init() is available */ +#define HAVE_DRM_MODE_INTT 1 + /* enum drm_mode_subconnector is available */ /* #undef HAVE_DRM_MODE_SUBCONNECTOR_ENUM */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-mode-init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-mode-init.m4 new file mode 100644 index 0000000000000..9a220e320f721 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-mode-init.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.17-rc2-403-g2d3eec897033 +dnl # drm: Add drm_mode_init() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_mode_init(NULL, NULL); + ], [drm_mode_init], [drivers/gpu/drm/drm_modes.c], [ + AC_DEFINE(HAVE_DRM_MODE_INIT, 1, + [drm_mode_init() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 491bcc3ac19b3..6b2f6160ce118 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -106,6 +106,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRIVER_RELEASE AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_AMDGPU_DRM_MODE_IS_420_XXX + AC_AMDGPU_DRM_MODE_INIT AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT AC_AMDGPU_STRSCPY AC_AMDGPU_DRM_DP_MST_TOPOLOGY diff --git a/include/kcl/kcl_drm_modes.h b/include/kcl/kcl_drm_modes.h index c47d691ca6e7a..efd58502aad15 100644 --- a/include/kcl/kcl_drm_modes.h +++ b/include/kcl/kcl_drm_modes.h @@ -36,4 +36,8 @@ bool drm_mode_is_420_also(const struct drm_display_info *display, const struct drm_display_mode *mode); #endif +#ifndef HAVE_DRM_MODE_INIT +void drm_mode_init(struct drm_display_mode *dst, const struct drm_display_mode *src); +#endif + #endif From f61c35ba11c45e0b385afb2977ef52546684e00d Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 23 Nov 2022 19:35:54 +0800 Subject: [PATCH 0868/2653] drm/amdkcl: Check if DECLARE_DYNDBG_CLASSMAP is defined Check if DECLARE_DYNDBG_CLASSMAP is defined. This macro definition is introduced in dyndbg: add DECLARE_DYNDBG_CLASSMAP macro Signed-off-by: Ma Jun Change-Id: I4877b8610c0134b96183697a047eeae3d4ffe4da --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_dynamic_debug.h | 64 +++++++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 include/kcl/kcl_dynamic_debug.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b57813353fe7b..685614933b096 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -99,4 +99,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_dynamic_debug.h b/include/kcl/kcl_dynamic_debug.h new file mode 100644 index 0000000000000..6c6f7296eba94 --- /dev/null +++ b/include/kcl/kcl_dynamic_debug.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef AMDKCL_DYNAMIC_DEBUG_H +#define AMDKCL_DYNAMIC_DEBUG_H + +#ifndef DECLARE_DYNDBG_CLASSMAP +enum class_map_type { + DD_CLASS_TYPE_DISJOINT_BITS, + /** + * DD_CLASS_TYPE_DISJOINT_BITS: classes are independent, one per bit. + * expecting hex input. Built for drm.debug, basis for other types. + */ + DD_CLASS_TYPE_LEVEL_NUM, + /** + * DD_CLASS_TYPE_LEVEL_NUM: input is numeric level, 0-N. + * N turns on just bits N-1 .. 0, so N=0 turns all bits off. + */ + DD_CLASS_TYPE_DISJOINT_NAMES, + /** + * DD_CLASS_TYPE_DISJOINT_NAMES: input is a CSV of [+-]CLASS_NAMES, + * classes are independent, like _DISJOINT_BITS. + */ + DD_CLASS_TYPE_LEVEL_NAMES, + /** + * DD_CLASS_TYPE_LEVEL_NAMES: input is a CSV of [+-]CLASS_NAMES, + * intended for names like: INFO,DEBUG,TRACE, with a module prefix + * avoid EMERG,ALERT,CRIT,ERR,WARNING: they're not debug + */ +}; + +struct ddebug_class_map { + struct list_head link; + struct module *mod; + const char *mod_name; /* needed for builtins */ + const char **class_names; + const int length; + const int base; /* index of 1st .class_id, allows split/shared space */ + enum class_map_type map_type; +}; + +/** + * DECLARE_DYNDBG_CLASSMAP - declare classnames known by a module + * @_var: a struct ddebug_class_map, passed to module_param_cb + * @_type: enum class_map_type, chooses bits/verbose, numeric/symbolic + * @_base: offset of 1st class-name. splits .class_id space + * @classes: class-names used to control class'd prdbgs + */ +#define DECLARE_DYNDBG_CLASSMAP(_var, _maptype, _base, ...) \ + static const char *_var##_classnames[] = { __VA_ARGS__ }; \ + static struct ddebug_class_map __aligned(8) __used \ + __section("__dyndbg_classes") _var = { \ + .mod = THIS_MODULE, \ + .mod_name = KBUILD_MODNAME, \ + .base = _base, \ + .map_type = _maptype, \ + .length = NUM_TYPE_ARGS(char*, __VA_ARGS__), \ + .class_names = _var##_classnames, \ + } +#define NUM_TYPE_ARGS(eltype, ...) \ + (sizeof((eltype[]){__VA_ARGS__}) / sizeof(eltype)) + +#endif + +#endif /* AMDKCL_DYNAMIC_DEBUG_H */ From be0c91d2272ae4f7a739e62f193008fe8e254cb0 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 23 Nov 2022 20:12:05 +0800 Subject: [PATCH 0869/2653] drm/amdkcl: Check if acpi_video_backlight_use_native() is implemented check if acpi_video_backlight_use_native is implemented Signed-off-by: Ma Jun Change-Id: I3c1fd6875436808205d7f6e6dbcf7d59a4722d3a --- .../gpu/drm/amd/amdgpu/atombios_encoders.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 | 22 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index 99bc6a0066e20..a4fb631f43924 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -186,10 +186,12 @@ void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *amdgpu_encode if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) goto register_acpi_backlight; +#ifdef HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE if (!acpi_video_backlight_use_native()) { drm_info(dev, "Skipping amdgpu atom DIG backlight registration\n"); goto register_acpi_backlight; } +#endif pdata = kmalloc(sizeof(struct amdgpu_backlight_privdata), GFP_KERNEL); if (!pdata) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 647f60e742492..b1b48ab97020e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -15,6 +15,9 @@ /* struct acpi_srat_generic_affinity is available */ #define HAVE_ACPI_SRAT_GENERIC_AFFINITY 1 + +/* acpi_video_backlight_use_native() is available */ +#define HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE 1 /* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ #define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 new file mode 100644 index 0000000000000..69f2cc28f537c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 @@ -0,0 +1,22 @@ +dnl # +dnl # commit: v6.1-rc1-17-da11ef832972 +dnl # drm/amdgpu: Don't register backlight when another +dnl # backlight should be used (v3) + +AC_DEFUN([AC_AMDGPU_ACPI_VIDEO_BACKLIGHT_USE_NATIVE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + acpi_video_backlight_use_native(); + ], [ + AC_DEFINE(HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE, 1, + [acpi_video_backlight_use_native() is available]) + ]) + ]) +]) + + +AC_DEFUN([AC_AMDGPU_ACPI_VIDEO_FUNCS], [ + AC_AMDGPU_ACPI_VIDEO_BACKLIGHT_USE_NATIVE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6b2f6160ce118..927dde661e30e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -218,6 +218,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_REGISTER_SHRINKER AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN + AC_AMDGPU_ACPI_VIDEO_FUNCS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 0716298f5353274df262e3f2e334752778faf81e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 23 Nov 2022 20:28:02 +0800 Subject: [PATCH 0870/2653] drm/amdkcl: check if acpi_video_register_backlight() is implemented check if acpi_video_register_backlight() is implemented Signed-off-by: Ma Jun Change-Id: I3e3930f01cf382a84fe2c0366b865c75d34febe6 --- .../gpu/drm/amd/amdgpu/atombios_encoders.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 4 ++++ .../gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 | 19 +++++++++++++++++++ 3 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index a4fb631f43924..76de119d863ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -230,7 +230,9 @@ void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *amdgpu_encode register_acpi_backlight: /* Try registering an ACPI video backlight device instead. */ +#ifdef HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT acpi_video_register_backlight(); +#endif } void diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b1b48ab97020e..7a9f2e696dbd8 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -19,6 +19,10 @@ /* acpi_video_backlight_use_native() is available */ #define HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE 1 + +/* acpi_video_register_backlight() is available */ +#define HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT 1 + /* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ #define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 index 69f2cc28f537c..d2a957a3c28a7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 @@ -16,7 +16,26 @@ AC_DEFUN([AC_AMDGPU_ACPI_VIDEO_BACKLIGHT_USE_NATIVE], [ ]) ]) +dnl # +dnl # commit: v6.1-rc1-161-c0f50c5de93b +dnl # drm/amdgpu: Register ACPI video backlight when +dnl # skipping amdgpu backlight registration + +AC_DEFUN([AC_AMDGPU_ACPI_VIDEO_REGISTER_BACKLIGHT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + acpi_video_register_backlight(); + ], [ + AC_DEFINE(HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT, 1, + [acpi_video_register_backlight() is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_ACPI_VIDEO_FUNCS], [ AC_AMDGPU_ACPI_VIDEO_BACKLIGHT_USE_NATIVE + AC_AMDGPU_ACPI_VIDEO_REGISTER_BACKLIGHT ]) From 3f6f47edbc3ae2dd3426191c6094ab3f3768f66c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 9 Jul 2024 10:49:51 +0800 Subject: [PATCH 0871/2653] drm/amdkcl: Check if DRM_PLANE_NO_SCALING is defined Check if DRM_PLANE_NO_SCALING is defined Signed-off-by: Ma Jun Change-Id: Iaa3041b8bf4765b992f57837bf8c7e69cf34a3f1 Signed-off-by: Asher Song --- include/kcl/kcl_drm_atomic_helper.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_atomic_helper.h b/include/kcl/kcl_drm_atomic_helper.h index 208a5e9edf330..7bedeace08ad0 100644 --- a/include/kcl/kcl_drm_atomic_helper.h +++ b/include/kcl/kcl_drm_atomic_helper.h @@ -34,6 +34,11 @@ #include #include +/* drm/atomic-helper: Remove _HELPER_ infix from DRM_PLANE_HELPER_NO_SCALING */ +#ifndef DRM_PLANE_NO_SCALING +#define DRM_PLANE_NO_SCALING (1<<16) +#endif + /* * v4.19-rc1-206-ge267364a6e1b * drm/atomic: Initialise planes with opaque alpha values From 09894e27b83b05f6d1c9756643d8a8767f8364e8 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 23 Nov 2022 20:47:11 +0800 Subject: [PATCH 0872/2653] drm/amdkcl: Remove redundant macro DRM_UT_STATE This macro is defined in enum class_map_type now. Signed-off-by: Ma Jun Change-Id: Iadbbab2a0abafb3a83b918537a56296e083a2f20 --- include/kcl/kcl_drm_print.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index bba9e048cf699..80d51e8721236 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -125,10 +125,6 @@ void kcl_drm_err(const char *format, ...); #define HAVE_DRM_ERR_MACRO #endif /* drm_err */ -#if !defined(DRM_UT_STATE) -#define DRM_UT_STATE 0x40 -#endif - #if !defined(DRM_UT_VBL) #define DRM_UT_VBL 0x20 #endif From d1d323495137c623d6c9881b7317d689d53f60af Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 23 Nov 2022 20:49:42 +0800 Subject: [PATCH 0873/2653] drm/amdkcl: Wrap code under HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE Signed-off-by: Ma Jun Change-Id: Ia7819db796197c1c00ccfd848dfc8b84372e32b0 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 52f738e893c85..cd99ee189bdbc 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5077,12 +5077,14 @@ amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) if (aconnector->bl_idx == -1) return; +#ifdef HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE if (!acpi_video_backlight_use_native()) { drm_info(drm, "Skipping amdgpu DM backlight registration\n"); /* Try registering an ACPI video backlight device instead. */ acpi_video_register_backlight(); return; } +#endif caps = &dm->backlight_caps[aconnector->bl_idx]; if (get_brightness_range(caps, &min, &max)) { From bac7bfece69b9f570ba932149b8c48835144c965 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 09:57:18 +0800 Subject: [PATCH 0874/2653] drm/amdkcl: Check if drm_plane_helper_destroy() is implemented Check if drm_plane_helper_destroy is implemented Signed-off-by: Ma Jun Change-Id: Iaed7658f55768048ea9534aaeed12dd4cba70e8a --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-plane-helper-funcs.m4 | 21 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_plane_helper.h | 15 +++++++++++++ 5 files changed, 41 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-plane-helper-funcs.m4 create mode 100644 include/kcl/kcl_drm_plane_helper.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 685614933b096..ca935a3ea4838 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -100,4 +100,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7a9f2e696dbd8..2758d0ce3479d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -705,6 +705,9 @@ /* drm_plane_helper_check_state is available */ /* #undef HAVE_DRM_PLANE_HELPER_CHECK_STATE */ +/* drm_plane_helper_destroy() is available */ +/* #undef HAVE_DRM_PLANE_HELPER_DESTROY */ + /* drm_plane_mask is available */ #define HAVE_DRM_PLANE_MASK 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-plane-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-plane-helper-funcs.m4 new file mode 100644 index 0000000000000..e4a2a7d627810 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-plane-helper-funcs.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit: v6.1-rc1-27-30c637151cfa +dnl # drm/plane-helper: Export individual helpers +dnl # + +AC_DEFUN([AC_AMDGPU_DRM_PLANE_HELPER_DESTROY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_plane_helper_destroy(NULL); + ], [ + AC_DEFINE(HAVE_DRM_PLANE_HELPER_DESTROY, 1, + [drm_plane_helper_destroy() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_PLANE_HELPER_FUNCS], [ + AC_AMDGPU_DRM_PLANE_HELPER_DESTROY +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 927dde661e30e..2ea185cbcb2be 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -219,6 +219,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN AC_AMDGPU_ACPI_VIDEO_FUNCS + AC_AMDGPU_DRM_PLANE_HELPER_FUNCS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_plane_helper.h b/include/kcl/kcl_drm_plane_helper.h new file mode 100644 index 0000000000000..d1bc40bcebb4d --- /dev/null +++ b/include/kcl/kcl_drm_plane_helper.h @@ -0,0 +1,15 @@ +#ifndef AMDKCL_DRM_PLANE_HELPER_H +#define AMDKCL_DRM_PLANE_HELPER_H + +#include + +#ifndef HAVE_DRM_PLANE_HELPER_DESTROY +static void kcl_drm_plane_helper_destroy(struct drm_plane *plane) +{ + drm_plane_cleanup(plane); + kfree(plane); +} + +#define drm_plane_helper_destroy kcl_drm_plane_helper_destroy +#endif +#endif \ No newline at end of file From d644fdeb357445dc8655c329090bb746094fa94f Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 10:11:25 +0800 Subject: [PATCH 0875/2653] drm/amdkcl: Check if display_info->luminance_range is defined check if display_info->luminance_range is defined Signed-off-by: Ma Jun Change-Id: I39fab65c8347df82fd857b6aa8a45bd50002244b --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm-display-info.m4 | 20 +++++++++++++++++++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index cd99ee189bdbc..776e17985539b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3657,7 +3657,9 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) struct amdgpu_dm_backlight_caps *caps; struct drm_connector *conn_base; struct amdgpu_device *adev; +#ifdef HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE struct drm_luminance_range_info *luminance_range; +#endif int min_input_signal_override; if (aconnector->bl_idx == -1 || @@ -3686,6 +3688,7 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) if (caps->aux_support) aconnector->dc_link->backlight_control_type = BACKLIGHT_CONTROL_AMD_AUX; +#ifdef HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE luminance_range = &conn_base->display_info.luminance_range; if (luminance_range->max_luminance) @@ -3697,6 +3700,7 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) caps->aux_min_input_signal = luminance_range->min_luminance; else caps->aux_min_input_signal = 1; +#endif min_input_signal_override = drm_get_panel_min_brightness_quirk(aconnector->drm_edid); if (min_input_signal_override >= 0) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2758d0ce3479d..4a6a44e1eb172 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -361,6 +361,9 @@ /* struct drm_display_info has monitor_range member */ #define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 +/* display_info->luminance_range is available */ +/* #undef HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE */ + /* display_info->max_dsc_bpp is available */ /* #undef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 index e498f3bc94867..f72df7f1ac808 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 @@ -54,8 +54,28 @@ AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_MAX_DSC_BPP], [ ]) ]) +dnl # +dnl # commit v6.1-rc1~27-a61bb3422e8d +dnl # drm/amdgpu_dm: Rely on split out luminance calculation function +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_LUMINANCE_RANGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_display_info *display_info = NULL; + display_info->luminance_range=NULL; + ],[ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE, 1, + [display_info->luminance_range is available]) + ]) + ]) +]) + + AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO], [ AC_AMDGPU_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE AC_AMDGPU_DRM_DISPLAY_INFO_MAX_DSC_BPP + AC_AMDGPU_DRM_DISPLAY_INFO_LUMINANCE_RANGE ]) From 85a0f85da5cc924017d4e0b52b2337e50c3876d1 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 11:09:31 +0800 Subject: [PATCH 0876/2653] drm/amdkcl: Rename the drm-dp-atomic-find-vcpi-slots.m4 Rename drm-dp-atomic-find-vcpi-slots.m4 to drm-dp-atomic-funcs.m4 for better compatability Signed-off-by: Ma Jun Change-Id: I1bda63ad4526270fd0850801a10d969a621946fd --- ...rm-dp-atomic-find-vcpi-slots.m4 => drm-dp-atomic-funcs.m4} | 4 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) rename drivers/gpu/drm/amd/dkms/m4/{drm-dp-atomic-find-vcpi-slots.m4 => drm-dp-atomic-funcs.m4} (94%) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 similarity index 94% rename from drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 rename to drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index 10cfe8e436f12..336e89b2a2874 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -43,3 +43,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ ]) ]) ]) + +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ + AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2ea185cbcb2be..3c98547bcab14 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -75,7 +75,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_CALC_PBN_MODE - AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS + AC_AMDGPU_DRM_DP_ATOMIC_FUNCS AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME From 2deac1baf4d21cc80540ec8074161fd8c311e414 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 11:17:26 +0800 Subject: [PATCH 0877/2653] drm/amdkcl: Check and implement the drm_dp_atomic_find_time_slots() Check and implement the drm_dp_atomic_find_time_slots() func Signed-off-by: Ma Jun Change-Id: I5fc1dd70ab3bbf0f62586136ccd999ef52606956 --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 19 +++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4a6a44e1eb172..54a5811fa3821 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -367,6 +367,9 @@ /* display_info->max_dsc_bpp is available */ /* #undef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP */ +/* drm_dp_atomic_find_time_slots() is available */ +/* #undef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS */ + /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index 336e89b2a2874..9f766ab7f8fc1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -44,6 +44,25 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ ]) ]) +dnl # +dnl # commit v6.1-rc1~27-df78f7f660cd +dnl # drm/display/dp_mst: Call them time slots, not VCPI slots +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_atomic_find_time_slots(NULL, NULL, NULL, 0, 0); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS, 1, + [drm_dp_atomic_find_time_slots() is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS + AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS ]) From c171f3ac0c8ddf5271e1efc8304f9b54c5d83631 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 12:41:17 +0800 Subject: [PATCH 0878/2653] drm/amdkcl: Implement the func drm_dp_atomic_find_time_slots() Signed-off-by: Ma Jun Change-Id: I4c07fabde6050973e25c0516166bc0e6ac256514 --- .../kcl/backport/kcl_drm_dp_mst_helper_backport.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 9be8ef18696a1..6a5e6961228bb 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -65,6 +65,18 @@ int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, #endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ #endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS */ +#if !defined(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS) +static inline +int _kcl_drm_dp_atomic_find_time_slots(struct drm_atomic_state *state, + struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, int pbn, + int pbn_div) +{ + return 0; +} +#define drm_dp_atomic_find_time_slots _kcl_drm_dp_atomic_find_time_slots +#endif + #ifndef HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS static inline int _kcl_drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr, From a3639a9dfa1d97a1c681b054c3ebe9b18495bedb Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 12:51:30 +0800 Subject: [PATCH 0879/2653] drm/amdkcl: Check if drm_dp_mst_atomic_setup_commit() is available Check if drm_dp_mst_atomic_setup_commit() is available Signed-off-by: Ma Jun Change-Id: I5653a9e25f19242d7b53c905efd1a92666b400a5 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 20 +++++++++++++++++++ 3 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 776e17985539b..a499d63fd5b29 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3647,7 +3647,9 @@ static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { #ifdef HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, +#ifdef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, +#endif }; #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 54a5811fa3821..211498db8c115 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -370,6 +370,9 @@ /* drm_dp_atomic_find_time_slots() is available */ /* #undef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS */ +/* drm_dp_mst_atomic_setup_commit() is available */ +/* #undef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT */ + /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index 9f766ab7f8fc1..0e5b9a432aa01 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -62,7 +62,27 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS], [ ]) ]) +dnl # +dnl # commit v6.1-rc1~27-a5c2c0d164e9 +dnl # drm/display/dp_mst: Add nonblocking helpers for DP MST +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_mst_atomic_setup_commit(NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_SETUP_COMMIT, 1, + [drm_dp_mst_atomic_setup_commit() is available]) + ]) + ]) +]) + + AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS + AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT ]) From c7943515184559d57362b4d1d330b09308391b1b Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 13:00:44 +0800 Subject: [PATCH 0880/2653] drm/amdkcl: Check if drm_dp_mst_atomic_wait_for_dependencies() is available Check if drm_dp_mst_atomic_wait_for_dependencies() is available Signed-off-by: Ma Jun Change-Id: Ibcfd90165754d5d8a0abbbaba850e5567e39bab4 --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 21 +++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 211498db8c115..8804528e63739 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -373,6 +373,9 @@ /* drm_dp_mst_atomic_setup_commit() is available */ /* #undef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT */ +/* drm_dp_mst_atomic_wait_for_dependencies() is available */ +/* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ + /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index 0e5b9a432aa01..bb74fab63718a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -80,9 +80,30 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT], [ ]) ]) +drm_dp_mst_atomic_wait_for_dependencies + +dnl # +dnl # commit v6.1-rc1~27-a5c2c0d164e9 +dnl # drm/display/dp_mst: Add nonblocking helpers for DP MST +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_mst_atomic_wait_for_dependencies(NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES, 1, + [drm_dp_mst_atomic_wait_for_dependencies() is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT + AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES ]) From 890b78bc047cb2ada9d492b2c5ecb23c0840d18f Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 13:15:48 +0800 Subject: [PATCH 0881/2653] drm/amdkcl: Check if drm_dp_mst_root_conn_atomic_check() is available Check if drm_dp_mst_root_conn_atomic_check() is available Signed-off-by: Ma Jun Change-Id: I3b91f33e2fd780e3b2c952aa2c5c95bcaae78a52 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 18 ++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a499d63fd5b29..5b274f5832b25 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7942,15 +7942,19 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, drm_atomic_get_old_connector_state(state, conn); struct drm_crtc *crtc = new_con_state->crtc; struct drm_crtc_state *new_crtc_state; +#ifdef HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); +#endif int ret; trace_amdgpu_dm_connector_atomic_check(new_con_state); if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { +#ifdef HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); if (ret < 0) return ret; +#endif } if (!crtc) @@ -8002,6 +8006,7 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, return 0; } #endif + static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) { #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8804528e63739..c5c347067a4b7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -430,6 +430,9 @@ /* struct drm_dp_mst_port has passthrough_aux member */ /* #undef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX */ +/* drm_dp_mst_root_conn_atomic_check() is available */ +/* #undef HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK */ + /* drm_dp_mst_port struct has full_pbn member */ #define HAVE_DRM_DP_MST_PORT_FULL_PBN 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index bb74fab63718a..c28aae7a0814a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -100,10 +100,28 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES], [ ]) ]) +dnl # +dnl # commit v6.1-rc1~27-a5c2c0d164e9 +dnl # drm/display/dp_mst: Add nonblocking helpers for DP MST +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_mst_root_conn_atomic_check(NULL, NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK, 1, + [drm_dp_mst_root_conn_atomic_check() is available]) + ]) + ]) +]) AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES + AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK ]) From d4f3c5700dd46b28ba7bef5eee39d68fe47b3f4f Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 13:25:40 +0800 Subject: [PATCH 0882/2653] drm/amdkcl: Check if drm_dp_atomic_release_time_slots() is available Check if drm_dp_atomic_release_time_slots() is available Signed-off-by: Ma Jun Change-Id: I1fa8e5977f98a88d638dd93c7fb2398fdf447147 --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 19 +++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 008f410cf6f57..3242c85d95098 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -597,11 +597,15 @@ dm_dp_mst_detect(struct drm_connector *connector, static int dm_dp_mst_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state) { +#ifdef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr; struct drm_dp_mst_port *mst_port = aconnector->mst_output_port; return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); +#else + return 0; +#endif } #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c5c347067a4b7..805e8794bac31 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -379,6 +379,9 @@ /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 +/* drm_dp_atomic_release_time_slots() is available */ +/* #undef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS */ + /* drm_dp_atomic_find_vcpi_slots() wants 5args */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index c28aae7a0814a..a67dc29ccbeb2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -118,10 +118,29 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK], [ ]) ]) +dnl # +dnl # commit v6.1-rc1~27-df78f7f660cd +dnl # drm/display/dp_mst: Call them time slots, not VCPI slots +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_atomic_release_time_slots(NULL, NULL, NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS, 1, + [drm_dp_atomic_release_time_slots() is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK + AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS ]) From b103286426bacf4a67668cc518c340e8f9b27edb Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 14:38:58 +0800 Subject: [PATCH 0883/2653] drm/amdkcl: Using amdkcl_ttm_resvp() to get bo->resv Using amdkcl_ttm_resvp() to get bo->resv Signed-off-by: Ma Jun Change-Id: I11553784cdba0f2a1c91d3bf41b274d14a843d3e --- drivers/gpu/drm/ttm/ttm_bo.c | 2 +- drivers/gpu/drm/ttm/ttm_bo_util.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index ba7b5b054faf3..cc80fd302a192 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -982,7 +982,7 @@ int ttm_bo_init_reserved(struct ttm_device *bdev, struct ttm_buffer_object *bo, err_unlock: if (!resv) - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); err_put: ttm_bo_put(bo); diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 490f415cd8db0..780980e72f978 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -521,7 +521,7 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, struct iosys_map *map) struct ttm_resource *mem = bo->resource; int ret; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); ret = ttm_mem_io_reserve(bo->bdev, mem); if (ret) @@ -589,7 +589,7 @@ void ttm_bo_vunmap(struct ttm_buffer_object *bo, struct iosys_map *map) { struct ttm_resource *mem = bo->resource; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (iosys_map_is_null(map)) return; From 0056d9a1b6d22b3add228370f1920e98cfce6926 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 14:48:06 +0800 Subject: [PATCH 0884/2653] drm/amdkcl: Rename idr-remove.m4 Rename idr-remove.m4 as idr.m4 for better compatability Signed-off-by: Ma Jun Change-Id: Iacfdba39cf4fd2224e51d8b3f018cb5dfcdbd5bd --- drivers/gpu/drm/amd/dkms/m4/{idr-remove.m4 => idr.m4} | 4 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) rename drivers/gpu/drm/amd/dkms/m4/{idr-remove.m4 => idr.m4} (90%) diff --git a/drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 b/drivers/gpu/drm/amd/dkms/m4/idr.m4 similarity index 90% rename from drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 rename to drivers/gpu/drm/amd/dkms/m4/idr.m4 index 397c76a73ed8e..0801f227c6421 100644 --- a/drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/idr.m4 @@ -17,3 +17,7 @@ AC_DEFUN([AC_AMDGPU_IDR_REMOVE], [ ]) ]) ]) + +AC_DEFUN([AC_AMDGPU_IDR], [ + AC_AMDGPU_IDR_REMOVE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3c98547bcab14..0b3c5c0adc05c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_KERNEL_SUPPORTED_AMD_CHIPS - AC_AMDGPU_IDR_REMOVE + AC_AMDGPU_IDR AC_AMDGPU_KREF_READ AC_AMDGPU_TYPE__POLL_T AC_AMDGPU_DMA_MAP_SGTABLE From 0302882af7c62961a3d0342c430685370db438a1 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 14:54:45 +0800 Subject: [PATCH 0885/2653] drm/amdkcl: Check and implement idr_init_base() Check and implement idr_init_base() Signed-off-by: Ma Jun Change-Id: Idb8feda0a5dd39b22b1e65e2cafec0c108640f4e --- drivers/gpu/drm/amd/dkms/m4/idr.m4 | 39 ++++++++++++++++++++++++++++++ include/kcl/kcl_idr.h | 16 ++++++++++++ 2 files changed, 55 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/idr.m4 b/drivers/gpu/drm/amd/dkms/m4/idr.m4 index 0801f227c6421..7816e84901c5a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/idr.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/idr.m4 @@ -18,6 +18,45 @@ AC_DEFUN([AC_AMDGPU_IDR_REMOVE], [ ]) ]) +dnl # +dnl # commit v6.1-rc1~27-c4f306e31632 +dnl # drm/amdgpu: use idr_init_base() to initialize fpriv->bo_list_handles +dnl # +AC_DEFUN([AC_AMDGPU_IDR_INIT_BASE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + void *i; + i = idr_init_base(NULL, 0); + ], [ + AC_DEFINE(HAVE_IDR_INIT_BASE, 1, + [idr_init_base() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v4.16-rc1~25-6ce711f27500 +dnl # idr: Make 1-based IDRs more efficient +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_IDE_IDR_BASE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct idr *idr = NULL; + idr->idr_base = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_IDE_IDR_BASE, 1, + [ide->idr_base is available]) + ]) + ]) +]) + + AC_DEFUN([AC_AMDGPU_IDR], [ AC_AMDGPU_IDR_REMOVE + AC_AMDGPU_IDR_INIT_BASE + AC_AMDGPU_STRUCT_IDE_IDR_BASE ]) diff --git a/include/kcl/kcl_idr.h b/include/kcl/kcl_idr.h index 63473317c2ead..1cdea5ec45d67 100644 --- a/include/kcl/kcl_idr.h +++ b/include/kcl/kcl_idr.h @@ -35,4 +35,20 @@ static inline void *_kcl_idr_remove(struct idr *idr, int id) #define idr_remove _kcl_idr_remove #endif /* HAVE_IDR_REMOVE_RETURN_VOID_POINTER */ +#ifndef HAVE_IDR_INIT_BASE +#ifdef HAVE_STRUCT_IDE_IDR_BASE +static inline void kc_idr_init_base(struct idr *idr, int base) +{ + INIT_RADIX_TREE(&idr->idr_rt, IDR_RT_MARKER); + idr->idr_base = base; + idr->idr_next = 0; +} +#else +static inline void kc_idr_init_base(struct idr *idr, int base) +{ + idr_init(idr); +} +#endif +#define idr_init_base kc_idr_init_base +#endif #endif /* AMDKCL_IDR_H */ From de63b78846f4a2f8c231e9d4e701befa786ac997 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 24 Nov 2022 15:18:34 +0800 Subject: [PATCH 0886/2653] drm/amdkcl: change label from error_abort to error_unlock It's caused by 4624459c84d71e0d5f94ea6a7b2c4eec4f1d122b drm/amdgpu: add gang submit frontend v6 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 2545699a35fb4..4481a795cc4fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1477,7 +1477,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) { r = -ERESTARTSYS; - goto error_abort; + goto error_unlock; } } #endif From 1a3009769b4639826352405092bf0d4733cea06e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 16:43:31 +0800 Subject: [PATCH 0887/2653] drm/amdkcl: Declare amdgpu_display_gem_fb_init() Declare amdgpu_display_gem_fb_init because this function still being used Signed-off-by: Ma Jun Change-Id: I5184237ba51dcd6623ca64c49118db63ed7211a7 --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 53e0463bfc07a..e5906df41a0ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -706,6 +706,11 @@ int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode); +int amdgpu_display_gem_fb_init(struct drm_device *dev, + struct amdgpu_framebuffer *rfb, + const struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object *obj); + int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); void amdgpu_enc_destroy(struct drm_encoder *encoder); From d95a75ca0185549b517b0d7c4533742e7047501e Mon Sep 17 00:00:00 2001 From: bobzhou Date: Wed, 23 Nov 2022 16:11:22 +0800 Subject: [PATCH 0888/2653] drm/amdkcl: rename the function name for HMM handling It's caused 735e66c12ec98751474db9e700c80e65355c1290 "drm/amdgpu: rename the files for HMM handling" Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 8 ++++---- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 4481a795cc4fe..8fdcb2e0bb4d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -41,6 +41,7 @@ #include "amdgpu_gem.h" #include "amdgpu_ras.h" #include "amdgpu_display.h" +#include "amdgpu_hmm.h" static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 43bb1ec468fe8..580c06da4c55f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -609,7 +609,7 @@ struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, } /** - * amdgpu_mn_register - register a BO for notifier updates + * amdgpu_hmm_register - register a BO for notifier updates * * @bo: amdgpu buffer object * @addr: userptr addr we should monitor @@ -617,7 +617,7 @@ struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, * Registers an MMU notifier for the given BO at the specified address. * Returns 0 on success, -ERRNO if anything goes wrong. */ -int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) +int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) { unsigned long end = addr + amdgpu_bo_size(bo) - 1; struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); @@ -676,7 +676,7 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) * * Remove any registration of MMU notifier updates from the buffer object. */ -void amdgpu_mn_unregister(struct amdgpu_bo *bo) +void amdgpu_hmm_unregister(struct amdgpu_bo *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); struct amdgpu_mn *amn; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index b70e93444fabb..38492d5c4d72b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -42,8 +42,8 @@ void amdgpu_mn_lock(struct amdgpu_mn *mn); void amdgpu_mn_unlock(struct amdgpu_mn *mn); struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, enum amdgpu_mn_type type); -int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); -void amdgpu_mn_unregister(struct amdgpu_bo *bo); +int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr); +void amdgpu_hmm_unregister(struct amdgpu_bo *bo); #else /* !CONFIG_MMU_NOTIFIER */ static inline void amdgpu_mn_lock(struct amdgpu_mn *mn) {} static inline void amdgpu_mn_unlock(struct amdgpu_mn *mn) {} @@ -52,11 +52,11 @@ static inline struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, { return NULL; } -static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) +static inline int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) { return -ENODEV; } -static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} +static inline void amdgpu_hmm_unregister(struct amdgpu_bo *bo) {} #endif /* CONFIG_MMU_NOTIFIER */ #else /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ #include From e9d2256b239c246ca06f68f9c10c32671d52f52d Mon Sep 17 00:00:00 2001 From: bobzhou Date: Wed, 23 Nov 2022 14:32:31 +0800 Subject: [PATCH 0889/2653] drm/amdkcl: modify fake function for amdgpu_ttm_tt_get_user_pages It's caused by 3da41b3e6f43161b0878d71c4b92211e6495a1c3 "drm/amdgpu: fix userptr HMM range handling v2" Signed-off-by: bobzhou Reviewed-by: Leslie Shi Change-Id: I5455256f52b011df8e0d100ca2d4ab01975fd9f8 --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 148 +++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +- 3 files changed, 78 insertions(+), 77 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index fce82223feef5..9d0b4e8964214 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1151,7 +1151,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, goto unregister_out; } - ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages, NULL); if (ret) { pr_err("%s: Failed to get user pages: %d\n", __func__, ret); goto free_out; @@ -2924,7 +2924,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, } /* Get updated user pages */ - ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages, NULL); if (ret) { mem->user_pages[0] = NULL; pr_info("%s: Failed to get user pages: %d\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 8fdcb2e0bb4d9..3bc373a9afbd2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -969,80 +969,80 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, } } #else - while (1) { - struct list_head need_pages; - - r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, - &duplicates); - if (unlikely(r != 0)) { - if (r != -ERESTARTSYS) - DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); - goto error_free_pages; - } - - INIT_LIST_HEAD(&need_pages); - amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { - struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); - - if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm, - &e->user_invalidated) && e->user_pages) { - - /* We acquired a page array, but somebody - * invalidated it. Free it and try again - */ - release_pages(e->user_pages, - bo->tbo.ttm->num_pages); - kvfree(e->user_pages); - e->user_pages = NULL; - } - - if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) && - !e->user_pages) { - list_del(&e->tv.head); - list_add(&e->tv.head, &need_pages); - - amdgpu_bo_unreserve(bo); - } - } - - if (list_empty(&need_pages)) - break; - - /* Unreserve everything again. */ - ttm_eu_backoff_reservation(&p->ticket, &p->validated); - - /* We tried too many times, just abort */ - if (!--tries) { - r = -EDEADLK; - DRM_ERROR("deadlock in %s\n", __func__); - goto error_free_pages; - } - - /* Fill the page arrays for all userptrs. */ - list_for_each_entry(e, &need_pages, tv.head) { - struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); - - e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages, - sizeof(struct page*), - GFP_KERNEL | __GFP_ZERO); - if (!e->user_pages) { - r = -ENOMEM; - DRM_ERROR("calloc failure in %s\n", __func__); - goto error_free_pages; - } - - r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages); - if (r) { - DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); - kvfree(e->user_pages); - e->user_pages = NULL; - goto error_free_pages; - } - } - - /* And try again. */ - list_splice(&need_pages, &p->validated); - } + while (1) { + struct list_head need_pages; + + r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, + &duplicates); + if (unlikely(r != 0)) { + if (r != -ERESTARTSYS) + DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); + goto error_free_pages; + } + + INIT_LIST_HEAD(&need_pages); + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + + if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm, + &e->user_invalidated) && e->user_pages) { + + /* We acquired a page array, but somebody + * invalidated it. Free it and try again + */ + release_pages(e->user_pages, + bo->tbo.ttm->num_pages); + kvfree(e->user_pages); + e->user_pages = NULL; + } + + if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) && + !e->user_pages) { + list_del(&e->tv.head); + list_add(&e->tv.head, &need_pages); + + amdgpu_bo_unreserve(bo); + } + } + + if (list_empty(&need_pages)) + break; + + /* Unreserve everything again. */ + ttm_eu_backoff_reservation(&p->ticket, &p->validated); + + /* We tried too many times, just abort */ + if (!--tries) { + r = -EDEADLK; + DRM_ERROR("deadlock in %s\n", __func__); + goto error_free_pages; + } + + /* Fill the page arrays for all userptrs. */ + list_for_each_entry(e, &need_pages, tv.head) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + + e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages, + sizeof(struct page*), + GFP_KERNEL | __GFP_ZERO); + if (!e->user_pages) { + r = -ENOMEM; + DRM_ERROR("calloc failure in %s\n", __func__); + goto error_free_pages; + } + + r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages, NULL); + if (r) { + DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); + kvfree(e->user_pages); + e->user_pages = NULL; + goto error_free_pages; + } + } + + /* And try again. */ + list_splice(&need_pages, &p->validated); + } #endif amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 5f99bc12642e4..8310476714b5c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -859,7 +859,8 @@ bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, * This provides a wrapper around the get_user_pages() call to provide * device accessible pages that back user memory. */ -int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, + struct hmm_range **range) { struct ttm_tt *ttm = bo->tbo.ttm; struct amdgpu_ttm_tt *gtt = (void *)ttm; From a3edbdef106903a0f30d2261c69f795687aed462 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 2 Dec 2022 19:35:35 +0800 Subject: [PATCH 0890/2653] Revert "dma-buf: fix dma_fence_default_wait() signaling check" This reverts commit 3cc3dd73c420dc70cd366f91a680035ef47edf4f. Signed-off-by: Asher Song --- drivers/dma-buf/dma-fence.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 3f78c56b58dca..a887f6a59a1f4 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -781,10 +781,10 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) unsigned long flags; signed long ret = timeout ? timeout : 1; - spin_lock_irqsave(fence->lock, flags); - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) - goto out; + return ret; + + spin_lock_irqsave(fence->lock, flags); if (intr && signal_pending(current)) { ret = -ERESTARTSYS; From ffbd802eefa6ea547be9b94e49b94238a39abd0d Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 28 Nov 2022 13:01:24 +0800 Subject: [PATCH 0891/2653] drm/amdkcl: fix macro for amdgpu_dm_mst_connector_early_unregister It's caused by m4 macro didn't align HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER and HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER Signed-off-by: Aurabindo Pillai Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 805e8794bac31..c39b6ce270174 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -144,10 +144,10 @@ #define HAVE_DOWN_WRITE_KILLABLE 1 /* drm_dp_mst_connector_early_unregister() is available */ -#define HAVE_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 +#define HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 /* drm_dp_mst_connector_late_register() is available */ -#define HAVE_DP_MST_CONNECTOR_LATE_REGISTER 1 +#define HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER 1 /* drm_accurate_vblank_count() is available */ /* #undef HAVE_DRM_ACCURATE_VBLANK_COUNT */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 index 611bd25368735..ef01260a09ddb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 @@ -63,9 +63,9 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ drm_dp_mst_connector_early_unregister(NULL, NULL); drm_dp_mst_connector_late_register(NULL, NULL); ], [ - AC_DEFINE(HAVE_DP_MST_CONNECTOR_EARLY_UNREGISTER, 1, [ + AC_DEFINE(HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER, 1, [ drm_dp_mst_connector_early_unregister() is available]) - AC_DEFINE(HAVE_DP_MST_CONNECTOR_LATE_REGISTER, 1, [ + AC_DEFINE(HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER, 1, [ drm_dp_mst_connector_late_register() is available]) ]) ]) From 4de5e67a841fc7ed8c892e49ad90dca0b42f1f77 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 28 Nov 2022 14:14:40 +0800 Subject: [PATCH 0892/2653] drm/amdkcl: update documentation of amdgpu_hmm_unregister Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 580c06da4c55f..ca7304e7f45b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -670,7 +670,7 @@ int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) } /** - * amdgpu_mn_unregister - unregister a BO for notifier updates + * amdgpu_hmm_unregister - unregister a BO for notifier updates * * @bo: amdgpu buffer object * From 0661429413ef2e6bd42329d975742e50f4c96a6a Mon Sep 17 00:00:00 2001 From: bobzhou Date: Wed, 30 Nov 2022 16:21:23 +0800 Subject: [PATCH 0893/2653] drm/amdkcl: fix marco for amdgpu_display_hotplug_work_func It's caused by 99d4c5b3ad086bf777a577f3aeb6bf443b8df65c "drm/amdgpu: move non-DC vblank handling out of irq code" Fuction "amdgpu_hotplug_work_func" is changed to "amdgpu_display_hotplug_work_func" But, kcl marco haven't been moved to amdgpu_display_hotplug_work_func Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index a0314cb301deb..beb9cfc6a7af7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -71,13 +71,22 @@ void amdgpu_display_hotplug_work_func(struct work_struct *work) struct drm_device *dev = adev_to_drm(adev); struct drm_mode_config *mode_config = &dev->mode_config; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif mutex_lock(&mode_config->mutex); +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) +#else + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) +#endif amdgpu_connector_hotplug(connector); + +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif mutex_unlock(&mode_config->mutex); /* Just fire off a uevent and let userspace tell us what to do */ drm_helper_hpd_irq_event(dev); From 16582497289f53ae46dba8146f6e0fdcac0f2821 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 7 Dec 2022 15:10:47 +0800 Subject: [PATCH 0894/2653] drm/amdkcl: Fix the type of function kcl_drm_plane_helper_destroy Fix the type of the function kcl_drm_plane_helper_destroy Signed-off-by: Ma Jun Change-Id: Ic2bdbbcd518581b3b5cd2ddd30997b8e7c9ba196 --- include/kcl/kcl_drm_plane_helper.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/kcl/kcl_drm_plane_helper.h b/include/kcl/kcl_drm_plane_helper.h index d1bc40bcebb4d..6b3798e0da151 100644 --- a/include/kcl/kcl_drm_plane_helper.h +++ b/include/kcl/kcl_drm_plane_helper.h @@ -4,12 +4,11 @@ #include #ifndef HAVE_DRM_PLANE_HELPER_DESTROY -static void kcl_drm_plane_helper_destroy(struct drm_plane *plane) +static inline void kcl_drm_plane_helper_destroy(struct drm_plane *plane) { drm_plane_cleanup(plane); kfree(plane); } - #define drm_plane_helper_destroy kcl_drm_plane_helper_destroy #endif #endif \ No newline at end of file From 62f7ae8a4048176236d14ed254aa3f49ba9d8686 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 7 Dec 2022 16:29:19 +0800 Subject: [PATCH 0895/2653] drm/amdkcl: Fix the warning of comment Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: If5721c8156ae7b147c90bb6dd2d9aff283b22ac6 --- drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c b/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c index fe36b386ff52b..f740a9626cd10 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c @@ -2,7 +2,7 @@ #include #ifndef for_each_cpu_wrap -/* copied from lib/cpumask.c +/* copied from lib/cpumask.c */ /** * cpumask_next_wrap - helper to implement for_each_cpu_wrap * @n: the cpu prior to the place to search From 03115d6c748e2668c382d0d99c03fdaf951d3666 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 5 Dec 2022 15:22:49 +0800 Subject: [PATCH 0896/2653] drm/amdkcl: Add support for drm_plane_enable_fb_damage_clips before v5.13 It's caused by 1f35cc57ec8c39b023bc1cfc4a29483e09fbbc89 "drm/amd/display: add FB_DAMAGE_CLIPS support" drm_plane_enable_fb_damage_clips is moved into core in v5.13-rc3-1669-gba6cd766e0bf Signed-off-by: bobzhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index ca935a3ea4838..cf0c936c52ad8 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -101,4 +101,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ From 17cc3ead665b70560c06908232ec9b162db2d8ab Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 8 Dec 2022 13:27:23 +0800 Subject: [PATCH 0897/2653] drm/dkms: Using the AS_HELPER_STRING intead of AC_HELP_STRING AC_HELP_STRING is deprecated now. So using the AS_HELPER_STRING intead of AC_HELP_STRING Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I144d13752fccf00f01a1a0dc4542603cebb9323f --- drivers/gpu/drm/amd/dkms/m4/config.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/config.m4 b/drivers/gpu/drm/amd/dkms/m4/config.m4 index e22a4a49a5233..d66b31b9b3536 100644 --- a/drivers/gpu/drm/amd/dkms/m4/config.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/config.m4 @@ -1,6 +1,6 @@ AC_DEFUN([AC_AMDGPU_CONFIG], [ AC_ARG_ENABLE([linux-builtin], - [AC_HELP_STRING([--enable-linux-builtin], + [AS_HELP_STRING([--enable-linux-builtin], [Configure for builtin kernel modules @<:@default=no@:>@])], [], [enable_linux_builtin=no]) From be19295759da00c440017a7d9772c1683938931c Mon Sep 17 00:00:00 2001 From: bobzhou Date: Fri, 9 Dec 2022 10:29:36 +0800 Subject: [PATCH 0898/2653] drm/amdkcl: Add missing comments in backport.h for drm_plane_enable_fb_damage_clips Signed-off-by: bobzhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index cf0c936c52ad8..bbdb386892d49 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -101,5 +101,11 @@ #include #include #include +/* + * v5.13-rc3-1669-gba6cd766e0bf + * ("drm/plane: Move drm_plane_enable_fb_damage_clips into core") + * move drm_plane_enable_fb_damage_clips() to drm_planer.h. + * include drm_damage_helper.h to fix the missing function declaration for legacy kernel. + */ #include #endif /* AMDGPU_BACKPORT_H */ From d1f13015d6684209605cc889922b8eb9ea532568 Mon Sep 17 00:00:00 2001 From: bobzhou2 Date: Wed, 21 Dec 2022 15:58:36 +0800 Subject: [PATCH 0899/2653] drm/amdkcl: wrap code under macro HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE It's caused by d090329b677c2f158755e886199c20b1acf93eb5 "drm/amd/display: save restore hdcp state when display is unplugged from mst hub" Signed-off-by: bobzhou2 Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5b274f5832b25..664eae6d44b85 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10411,6 +10411,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) enable_encryption = true; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE if (aconnector->dc_link && aconnector->dc_sink && aconnector->dc_link->type == dc_connection_mst_branch) { struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; @@ -10422,6 +10423,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) hdcp_w->content_protection[connector->index] = new_con_state->content_protection; } +#endif if (new_crtc_state && new_crtc_state->mode_changed && new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 3242c85d95098..eb17b09ecd119 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -460,6 +460,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) * plugged back with same display index, its hdcp properties * will be retrieved from hdcp_work within dm_dp_mst_get_modes */ +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE if (aconnector->dc_sink && connector->state) { struct drm_device *dev = connector->dev; struct amdgpu_device *adev = drm_to_adev(dev); @@ -475,6 +476,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) hdcp_w->content_protection[connector->index]; } } +#endif if (aconnector->dc_sink) { amdgpu_dm_update_freesync_caps( From 89083ab50c871ecbfaedb43a0733316461034330 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 5 Jan 2023 09:53:55 +0800 Subject: [PATCH 0900/2653] drm/amdkcl: Fix the compile warning when check dma_resv->seq Fix the compile warning when check dma_resv->seq Change-Id: I2580b66ff02a1991ce6e6b1b046365bc9cbfcb01 Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/dkms/Makefile | 2 +- drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index eec0d7868d7c2..9d2de6369b657 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -13,7 +13,7 @@ endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) -$(error dma_resv->seq is missing., exit...) +$(error dma_resv->seq is missing. exit...) endif ifeq ($(CC), gcc) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index 93c6dbc25ae22..8cf888eb3a6b4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -45,7 +45,8 @@ AC_DEFUN([AC_AMDGPU_DMA_RESV_SEQ], [ #include ], [ #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 18, 0) - int this_is_bug = 0; + int this_is_bug; + this_is_bug = 0; #else this_is_not_bug(); #endif From 44b23c5129c8b70c1c1e2442022bdc8391a08429 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 15 Dec 2022 16:58:43 +0800 Subject: [PATCH 0901/2653] drm/amdkcl: Return only kernel fences when iterating dma_resv with DMA_RESV_USAGE_KERNEL Avoid returning unnecessary write fences when extracting DMA_RESV_USAGE_KERNEL fences that could impact performance v2: dma_fence_put kernel_iter when iter restart v3: simplify code Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 174 ++++++++++++++++------ include/kcl/kcl_dma-resv.h | 6 + 2 files changed, 132 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index 8edf3fccac3e9..dc92c2d10f23d 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -342,44 +342,6 @@ void dma_resv_replace_fences(struct dma_resv *obj, uint64_t context, } EXPORT_SYMBOL(dma_resv_replace_fences); -/** - * dma_resv_add_excl_fence - Add an exclusive fence. - * @obj: the reservation object - * @fence: the exclusive fence to add - * - * Add a fence to the exclusive slot. @obj must be locked with dma_resv_lock(). - * See also &dma_resv.fence_excl for a discussion of the semantics. - */ -static void dma_resv_add_excl_fence(struct dma_resv *obj, - struct dma_fence *fence) -{ - struct dma_fence *old_fence = dma_resv_excl_fence(obj); - struct dma_fence_chain *chain; - - dma_resv_assert_held(obj); - - if (old_fence && !dma_fence_is_signaled(old_fence)) { - - chain = dma_fence_chain_alloc(); - if (unlikely(!chain)) - pr_err("dma_resv_add_excl_fence OOM\n"); - else { - dma_fence_chain_init(chain, dma_fence_get(old_fence), dma_fence_get(fence), 1); - fence = &chain->base; - } - } else { - dma_fence_get(fence); - } - - - write_seqcount_begin(&obj->seq); - /* write_seqcount_begin provides the necessary memory barrier */ - RCU_INIT_POINTER(obj->fence_excl, fence); - write_seqcount_end(&obj->seq); - - dma_fence_put(old_fence); -} - /** * dma_resv_add_fence - Add a fence to the dma_resv obj * @obj: the reservation object @@ -394,10 +356,28 @@ static void dma_resv_add_excl_fence(struct dma_resv *obj, void dma_resv_add_fence(struct dma_resv *obj, struct dma_fence *fence, enum dma_resv_usage usage) { - if (usage == DMA_RESV_USAGE_WRITE || usage == DMA_RESV_USAGE_KERNEL) - dma_resv_add_excl_fence(obj, fence); - else + struct dma_fence_chain *chain; + + if (usage >= DMA_RESV_USAGE_READ) { dma_resv_add_shared_fence(obj, fence); + return; + } + + chain = dma_fence_chain_alloc(); + if (unlikely(!chain)) { + /* We are out of memory, block as last resort */ + dma_fence_wait(fence, false); + return; + } + dma_fence_chain_init(chain, dma_resv_excl_fence(obj), dma_fence_get(fence), 1); + + /* Store the usage in the user bit to retrieve it later on */ + chain->base.flags |= usage << DMA_FENCE_FLAG_USER_BITS; + + /* Install the exclusive fence manually */ + write_seqcount_begin(&obj->seq); + RCU_INIT_POINTER(obj->fence_excl, &chain->base); + write_seqcount_end(&obj->seq); } EXPORT_SYMBOL(dma_resv_add_fence); @@ -408,6 +388,8 @@ static void dma_resv_iter_restart_unlocked(struct dma_resv_iter *cursor) cursor->seq = read_seqcount_begin(&cursor->obj->seq); cursor->index = -1; cursor->shared_count = 0; + cursor->excl_fence = NULL; + cursor->kernel_iter = NULL; if (cursor->usage >= DMA_RESV_USAGE_READ) { cursor->fences = dma_resv_shared_list(cursor->obj); if (cursor->fences) @@ -422,17 +404,55 @@ static void dma_resv_iter_restart_unlocked(struct dma_resv_iter *cursor) static void dma_resv_iter_walk_unlocked(struct dma_resv_iter *cursor) { struct dma_resv *obj = cursor->obj; + struct dma_fence_chain *chain; + struct dma_fence *f; + enum dma_resv_usage usage; do { /* Drop the reference from the previous round */ dma_fence_put(cursor->fence); if (cursor->index == -1) { - cursor->fence = dma_resv_excl_fence(obj); - cursor->index++; - if (!cursor->fence) - continue; - + if (cursor->usage >= DMA_RESV_USAGE_WRITE) { + cursor->fence = dma_resv_excl_fence(obj); + cursor->index++; + if (!cursor->fence) + continue; + } else { + cursor->fence = NULL; + /* Only return KERNEL fences */ + if (!cursor->excl_fence) { + cursor->excl_fence = dma_resv_excl_fence(obj); + if (!cursor->excl_fence) + break; + + cursor->excl_fence = dma_fence_get(cursor->excl_fence); + cursor->kernel_iter = dma_fence_get(cursor->excl_fence); + } + + while ((f = cursor->kernel_iter) != NULL) { + chain = to_dma_fence_chain(f); + if (!chain) { + dma_fence_put(f); + break; + } + + usage = chain->base.flags >> DMA_FENCE_FLAG_USER_BITS; + if (usage == DMA_RESV_USAGE_KERNEL && !dma_fence_is_signaled(chain->fence)) + cursor->fence = chain->fence; + + cursor->kernel_iter = dma_fence_chain_walk(f); + + if (cursor->fence) + break; + } + + if (!cursor->fence) { + dma_fence_put(cursor->excl_fence); + cursor->excl_fence = NULL; + break; + } + } } else if (!cursor->fences || cursor->index >= cursor->shared_count) { cursor->fence = NULL; @@ -464,10 +484,18 @@ static void dma_resv_iter_walk_unlocked(struct dma_resv_iter *cursor) */ struct dma_fence *dma_resv_iter_first_unlocked(struct dma_resv_iter *cursor) { + bool restart = false; + rcu_read_lock(); do { + if (restart) { + /* drop reference when iter restart */ + dma_fence_put(cursor->excl_fence); + dma_fence_put(cursor->kernel_iter); + } dma_resv_iter_restart_unlocked(cursor); dma_resv_iter_walk_unlocked(cursor); + restart = true; } while (read_seqcount_retry(&cursor->obj->seq, cursor->seq)); rcu_read_unlock(); @@ -493,8 +521,13 @@ struct dma_fence *dma_resv_iter_next_unlocked(struct dma_resv_iter *cursor) cursor->is_restarted = false; restart = read_seqcount_retry(&cursor->obj->seq, cursor->seq); do { - if (restart) + if (restart) { + /* drop reference when iter restart */ + dma_fence_put(cursor->excl_fence); + dma_fence_put(cursor->kernel_iter); + dma_resv_iter_restart_unlocked(cursor); + } dma_resv_iter_walk_unlocked(cursor); restart = true; } while (read_seqcount_retry(&cursor->obj->seq, cursor->seq)); @@ -515,7 +548,9 @@ EXPORT_SYMBOL(dma_resv_iter_next_unlocked); */ struct dma_fence *dma_resv_iter_first(struct dma_resv_iter *cursor) { - struct dma_fence *fence; + struct dma_fence *fence, *f; + struct dma_fence_chain *chain; + enum dma_resv_usage usage; dma_resv_assert_held(cursor->obj); @@ -525,11 +560,34 @@ struct dma_fence *dma_resv_iter_first(struct dma_resv_iter *cursor) else cursor->fences = NULL; + cursor->kernel_iter = NULL; fence = dma_resv_excl_fence(cursor->obj); if (!fence) fence = dma_resv_iter_next(cursor); + else if (cursor->usage == DMA_RESV_USAGE_KERNEL) { + cursor->kernel_iter = dma_fence_get(fence); + fence = NULL; + + while ((f = cursor->kernel_iter) != NULL) { + chain = to_dma_fence_chain(f); + if (!chain) { + dma_fence_put(f); + break; + } + + cursor->kernel_iter = dma_fence_chain_walk(f); + + usage = chain->base.flags >> DMA_FENCE_FLAG_USER_BITS; + if (usage == DMA_RESV_USAGE_KERNEL) + fence = chain->fence; + + if (fence) + break; + } + } cursor->is_restarted = true; + return fence; } EXPORT_SYMBOL_GPL(dma_resv_iter_first); @@ -544,10 +602,30 @@ EXPORT_SYMBOL_GPL(dma_resv_iter_first); struct dma_fence *dma_resv_iter_next(struct dma_resv_iter *cursor) { unsigned int idx; + struct dma_fence *f; + struct dma_fence_chain *chain; + enum dma_resv_usage usage; dma_resv_assert_held(cursor->obj); cursor->is_restarted = false; + + if (cursor->usage == DMA_RESV_USAGE_KERNEL && cursor->kernel_iter != NULL) { + while ((f = cursor->kernel_iter) != NULL) { + chain = to_dma_fence_chain(f); + if (!chain) { + dma_fence_put(f); + break; + } + + cursor->kernel_iter = dma_fence_chain_walk(f); + + usage = chain->base.flags >> DMA_FENCE_FLAG_USER_BITS; + if (usage == DMA_RESV_USAGE_KERNEL && chain->fence) + return chain->fence; + } + } + if (!cursor->fences || cursor->index >= cursor->fences->shared_count) return NULL; diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 4fe1fe0afac9d..a6b8ab359aa0d 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -171,6 +171,12 @@ struct dma_resv_iter { /** @is_restarted: true if this is the first returned fence */ bool is_restarted; + + /** @excl_fence: keep a reference to excl_fence when begin iterating kernel fences */ + struct dma_fence *excl_fence; + + /** @kernel_iter: next kernel fence pointer when iterating kernel fences */ + struct dma_fence *kernel_iter; }; #if defined(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T) From 50d4d99ecccecbb61e57861f5fa787d8d71c3a9d Mon Sep 17 00:00:00 2001 From: Horatio Zhang Date: Tue, 17 Jan 2023 18:23:23 +0800 Subject: [PATCH 0902/2653] drm/amdkcl: add macro DP_128B132B_TRAINING_AUX_RD_INTERVAL and DP_128B132B_SUPPORTED_LINK_RATES It's cause by 'commit 568c97c25cdb ("drm/amd/display: move dp link training logic to link_dp_training")' v6.0-2248-g568c97c25cdb Signed-off-by: Horatio Zhang Reviewed-by: Asher Song --- include/kcl/kcl_drm_dp_helper.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index cecb273e97d8a..4d3a14e7df501 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -326,4 +326,20 @@ enum drm_dp_phy { # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ #endif +/* + * v5.15-rc1-244-gba3078dad140 + * drm/dp: add helpers to read link training delays + */ +#ifndef DP_128B132B_TRAINING_AUX_RD_INTERVAL +#define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */ +#endif + +/* + * v5.9-rc5-1031-g7d56927efac7 + * drm/dp: add a number of DP 2.0 DPCD definitions + */ +#ifndef DP_128B132B_SUPPORTED_LINK_RATES +#define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */ +#endif + #endif /* _KCL_DRM_DP_HELPER_H_ */ From 095ff7d7a3440851de7f27b4f18516d6331f1108 Mon Sep 17 00:00:00 2001 From: bobzhou2 Date: Sun, 29 Jan 2023 10:45:54 +0800 Subject: [PATCH 0903/2653] drm/amdkcl: wrap code under macro HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT It's caused by 2f21ecf75a71b8aad4e28ce05758fb3f74eff4d1 "drm/amd/display: force connector state when bpc changes during compliance" Signed-off-by: bobzhou2 Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 664eae6d44b85..4761325639c69 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1526,7 +1526,11 @@ static void force_connector_state( mutex_unlock(&connector->dev->mode_config.mutex); mutex_lock(&aconnector->hpd_lock); - drm_kms_helper_connector_hotplug_event(connector); +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT + drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(connector->dev); +#endif mutex_unlock(&aconnector->hpd_lock); } From da2d833b8344d891e070e7d008e852a803258460 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 12 Jan 2023 17:19:59 +0800 Subject: [PATCH 0904/2653] drm/amdkcl: Use debugfs_remove_recursive to remove ttm directory Use debugfs_remove_recursive to remove the /sys/kernel/debug/ttm directory for better compatibility. Becuase debugfs_remove fails on older kernel. Change-Id: Ifcf180d18592a64b038c768c2257200416ef860b Signed-off-by: Ma Jun Reviewed-by: GuChun Chen --- drivers/gpu/drm/ttm/ttm_device.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c index f49a262462297..6ebe30bfb9d46 100644 --- a/drivers/gpu/drm/ttm/ttm_device.c +++ b/drivers/gpu/drm/ttm/ttm_device.c @@ -61,7 +61,13 @@ static void ttm_global_release(void) goto out; ttm_pool_mgr_fini(); - debugfs_remove(ttm_debugfs_root); + + /* + * Replace the debugfs_remove() with debugfs_remove_recursive() for dkms code. + * debugfs_remove() can't remove the ttm/ directory in legacy kernel. + * So use the debugfs_remove_recursive() here. + */ + debugfs_remove_recursive(ttm_debugfs_root); __free_page(glob->dummy_read_page); memset(glob, 0, sizeof(*glob)); From b38e3e9586668615543aa6e0ef45321f9763b970 Mon Sep 17 00:00:00 2001 From: bobzhou2 Date: Sun, 29 Jan 2023 13:23:45 +0800 Subject: [PATCH 0905/2653] drm/amdkcl: wrap code under CONFIG_DRM_AMD_DC_DSC_SUPPORT It's caused by a966a85e03653371931c13496e6a1c7638606666 "drm/amd/display: move eDP panel control logic to link_edp_panel_control" Signed-off-by: bobzhou2 Reviewed-by: Leslie Shi --- .../amd/display/dc/link/protocols/link_edp_panel_control.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index be714cbf66155..5fbc3e0240470 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -380,10 +380,14 @@ bool edp_is_ilr_optimization_required(struct dc_link *link, req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing, dc_link_get_highest_encoding_format(link)); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (!crtc_timing->flags.DSC) edp_decide_link_settings(link, &link_setting, req_bw); else decide_edp_link_settings_with_dsc(link, &link_setting, req_bw, LINK_RATE_UNKNOWN); +#else + decide_edp_link_settings(link, &link_setting, req_bw); +#endif if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate || lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) { From cf81a47ae782c837131020b70a0a9de7bb53e8b7 Mon Sep 17 00:00:00 2001 From: bobzhou2 Date: Sun, 29 Jan 2023 16:02:02 +0800 Subject: [PATCH 0906/2653] drm/amdkcl: add macro DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 It's caused by d9659c5e79a59264f633fbfec65d76a26bb8a274 "drm/amd/display: Enable AdaptiveSync in DC interface" Signed-off-by: bobzhou2 Reviewed-by: Leslie Shi --- include/kcl/kcl_drm_dp_helper.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 4d3a14e7df501..9f921c3d9db24 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -342,4 +342,12 @@ enum drm_dp_phy { #define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */ #endif +/* + * v6.0-2085-gbdf4b00bee5d + * drm/display: Add missing Adaptive Sync DPCD definitions + */ +#ifndef DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 +#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */ +#endif + #endif /* _KCL_DRM_DP_HELPER_H_ */ From 51a22260547f104fcc7b65449f1d3db2334869be Mon Sep 17 00:00:00 2001 From: bobzhou2 Date: Tue, 31 Jan 2023 14:07:03 +0800 Subject: [PATCH 0907/2653] drm/amdkcl: wrap code under macro HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE It's caused by 92ffdc98c5f71750ab18b01fd4a67c055127e59f "drm/amd/display: Enable Freesync over PCon" Signed-off-by: bobzhou2 Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4761325639c69..4c5c6b4923e5c 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12892,8 +12892,10 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) freesync_capable = true; +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; +#endif } } From e95eaecca5a8908c4e58814b4970381daf9fa424 Mon Sep 17 00:00:00 2001 From: bobzhou2 Date: Tue, 31 Jan 2023 15:30:55 +0800 Subject: [PATCH 0908/2653] drm/amdkcl: fix redefine issue due to backport.h It's caused by 92ffdc98c5f71750ab18b01fd4a67c055127e59f "drm/amd/display: Enable Freesync over PCon" Redefine fuction get_reg_field_value_ex and FD(reg_field). When backport.h includes dm_services.h, It shouldn't define get_reg_field_value_ex and FD(reg_field). Signed-off-by: bobzhou2 Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c | 7 +++++++ drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c index ca0c8a54b635e..88bf59ee5fea7 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c @@ -63,11 +63,18 @@ static void set_reg_field_values(struct dmub_reg_value_masks *field_value_mask, } } +/* + * v6.0-2372-g92ffdc98c5f7 + * ("drm/amd/display: Enable Freesync over PCon") + * verify __DM_SERVICES_H__ to fix the redefine function declaration for backport.h. + */ +#ifndef __DM_SERVICES_H__ static inline uint32_t get_reg_field_value_ex(uint32_t reg_value, uint32_t mask, uint8_t shift) { return (mask & reg_value) >> shift; } +#endif void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h index b314e60714ee2..10a87a277be22 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h @@ -50,7 +50,14 @@ struct dmub_srv; #define REG(reg) (REGS)->offset.reg +/* + * v6.0-2372-g92ffdc98c5f7 + * ("drm/amd/display: Enable Freesync over PCon") + * verify __DM_SERVICES_H__ to fix the redefine function declaration for backport.h. + */ +#ifndef __DM_SERVICES_H__ #define FD(reg_field) (REGS)->shift.reg_field, (REGS)->mask.reg_field +#endif #define FN(reg_name, field) FD(reg_name##__##field) From 1b6ccbce2371e64c3ae19663523f3dc445e9b181 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 15 Dec 2022 23:52:10 +0800 Subject: [PATCH 0909/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_DEV_DBG Since the function drm_dev_dbg() is available on oldest supported OS REL7.9, remove drm_dev_dbg check. Signed-off-by: Asher Song Reviewed-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 25 ---------------------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 | 11 ---------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/kcl_drm_print.h | 4 ---- 5 files changed, 44 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 9e0c95502367c..95e75be1d5ee8 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -59,31 +59,6 @@ void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf) EXPORT_SYMBOL(__drm_printfn_debug); #endif -#if !defined(HAVE_DRM_DEV_DBG) -void drm_dev_dbg(const struct device *dev, int category, - const char *format, ...) -{ - struct va_format vaf; - va_list args; - - if (!drm_debug_enabled(category)) - return; - - va_start(args, format); - vaf.fmt = format; - vaf.va = &args; - - if (dev) - dev_printk(KERN_DEBUG, dev, "[" DRM_NAME ":%ps] %pV", - __builtin_return_address(0), &vaf); - else - printk(KERN_DEBUG "[" DRM_NAME ":%ps] %pV", - __builtin_return_address(0), &vaf); - - va_end(args); -} -EXPORT_SYMBOL(drm_dev_dbg); -#endif #if !defined(HAVE_DRM_ERR_MACRO) void kcl_drm_err(const char *format, ...) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c39b6ce270174..7df0009c9f4ff 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -307,9 +307,6 @@ /* struct drm_device has pdev member */ /* #undef HAVE_DRM_DEVICE_PDEV */ -/* drm_dev_dbg() is available */ -#define HAVE_DRM_DEV_DBG 1 - /* drm_dev_enter() is available */ #define HAVE_DRM_DEV_ENTER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 deleted file mode 100644 index dfcc85e60e4bf..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 +++ /dev/null @@ -1,11 +0,0 @@ -dnl # -dnl # v4.16-rc1-493-gdb8708649258 -dnl # drm: Reduce object size of DRM_DEV_ uses -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DEV_DBG], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_dev_dbg], [drivers/gpu/drm/drm_print.c], [ - AC_DEFINE(HAVE_DRM_DEV_DBG, 1, [drm_dev_dbg() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0b3c5c0adc05c..d9d179bfb0f1a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -90,7 +90,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_DEVICE AC_AMDGPU_DRM_DRIVER_FEATURE AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET - AC_AMDGPU_DRM_DEV_DBG AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 80d51e8721236..a726abd73190d 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -153,10 +153,6 @@ void kcl_drm_err(const char *format, ...); } while (0) #endif -#if !defined(HAVE_DRM_DEV_DBG) -void drm_dev_dbg(const struct device *dev, int category, const char *format, ...); -#endif - #if !defined(drm_dbg_atomic) #define drm_dbg_atomic(drm, fmt, ...) \ drm_dev_dbg((drm)->dev, DRM_UT_ATOMIC, fmt, ##__VA_ARGS__) From 49063f36462738244b86ee42b0c050e83a459267 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 12 Dec 2022 16:34:58 +0800 Subject: [PATCH 0910/2653] drm/amdkcl: test whether MEMORY_DEVICE_COHERENT and MIGRATE_VMA_SELECT_DEVICE_PRIVATE is defined It's caused by 8dd9f5d2d0e4c14387e41c5231c3cff5a474b561 drm/amdkfd: add SPM support for SVM Signed-off-by: Felix Kuehling Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 | 22 ++++++++++++++++++++ 4 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index cd98c44accd34..22a7102f93dae 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -728,9 +728,11 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, migrate.end = end; #ifdef HAVE_MIGRATE_VMA_PGMAP_OWNER migrate.pgmap_owner = SVM_ADEV_PGMAP_OWNER(adev); +#ifdef HAVE_DEVICE_COHERENT if (adev->gmc.xgmi.connected_to_cpu) migrate.flags = MIGRATE_VMA_SELECT_DEVICE_COHERENT; else +#endif migrate.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE; #elif defined(HAVE_DEV_PAGEMAP_OWNER) migrate.src_owner = SVM_ADEV_PGMAP_OWNER(adev); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7df0009c9f4ff..43bdddd655540 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -80,6 +80,9 @@ /* devcgroup_check_permission() is available */ #define HAVE_DEVCGROUP_CHECK_PERMISSION 1 +/* MEMORY_DEVICE_COHERENT is availablea */ +#define HAVE_DEVICE_COHERENT 1 + /* devm_memremap_pages() wants struct dev_pagemap */ #define HAVE_DEVM_MEMREMAP_PAGES_DEV_PAGEMAP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d9d179bfb0f1a..93704b59ff7c9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -219,6 +219,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN AC_AMDGPU_ACPI_VIDEO_FUNCS AC_AMDGPU_DRM_PLANE_HELPER_FUNCS + AC_AMDGPU_MEMORY_DEVICE_COHERENT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 b/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 new file mode 100644 index 0000000000000..786ce2c5590ac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 @@ -0,0 +1,22 @@ +dnl # +dnl # commit f25cbb7a95a24ff9a2a3bebd308e303942ae6b2c +dnl # mm: add zone device coherent type memory support +dnl # +dnl # commit dd19e6d8ffaa1289d75d7833de97faf1b6b2c8e4 +dnl # mm: add device coherent vma selection for memory migration +dnl # +AC_DEFUN([AC_AMDGPU_MEMORY_DEVICE_COHERENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + int v = MEMORY_DEVICE_COHERENT; + int w = MIGRATE_VMA_SELECT_DEVICE_COHERENT; + ], [ + AC_DEFINE(HAVE_DEVICE_COHERENT, 1, + [MEMORY_DEVICE_COHERENT is availablea]) + ]) + ]) +]) + From b14edad08dc9f632ff4bdd6f68a25a058c494148 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 2 Feb 2023 11:09:33 +0800 Subject: [PATCH 0911/2653] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS It's caused by 4d07b0bc403403438d9cf88450506240c5faf92f "drm/display/dp_mst: Move all payload info into the atomic state" This patch is used to implent legacy payload code Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 161 +++++++++++++++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../amd/dkms/m4/drm-dp-mst-topology-state.m4 | 25 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 187 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 8c3af1ebaf024..6c1f14a9fbf02 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -234,6 +234,7 @@ enum dc_edid_status dm_helpers_parse_edid_caps( return result; } +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) static void fill_dc_mst_payload_table_from_drm(struct dc_link *link, bool enable, @@ -284,6 +285,44 @@ fill_dc_mst_payload_table_from_drm(struct dc_link *link, /* Overwrite the old table */ *table = new_table; } +#else +static void +fill_dc_mst_payload_table_from_drm(struct amdgpu_dm_connector *aconnector, + struct dc_dp_mst_stream_allocation_table *proposed_table) +{ + int i; + struct drm_dp_mst_topology_mgr *mst_mgr = + &aconnector->mst_port->mst_mgr; + + mutex_lock(&mst_mgr->payload_lock); + + proposed_table->stream_count = 0; + + /* number of active streams */ + for (i = 0; i < mst_mgr->max_payloads; i++) { + if (mst_mgr->payloads[i].num_slots == 0) + break; /* end of vcp_id table */ + + ASSERT(mst_mgr->payloads[i].payload_state != + DP_PAYLOAD_DELETE_LOCAL); + + if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL || + mst_mgr->payloads[i].payload_state == + DP_PAYLOAD_REMOTE) { + + struct dc_dp_mst_stream_allocation *sa = + &proposed_table->stream_allocations[ + proposed_table->stream_count]; + + sa->slot_count = mst_mgr->payloads[i].num_slots; + sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi; + proposed_table->stream_count++; + } + } + + mutex_unlock(&mst_mgr->payload_lock); +} +#endif /*HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS*/ void dm_helpers_dp_update_branch_info( struct dc_context *ctx, @@ -332,9 +371,26 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( bool enable) { struct amdgpu_dm_connector *aconnector; + struct drm_dp_mst_topology_mgr *mst_mgr; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) struct drm_dp_mst_topology_state *mst_state; struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload; - struct drm_dp_mst_topology_mgr *mst_mgr; +#else +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + struct dm_connector_state *dm_conn_state; +#endif + struct drm_dp_mst_port *mst_port; +#if !defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + int slots = 0; +#endif + bool ret; +#if !defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + int clock; + int bpp = 0; + int pbn = 0; +#endif + u8 link_coding_cap = DP_8b_10b_ENCODING; +#endif /*HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS*/ aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; /* Accessing the connector state is required for vcpi_slots allocation @@ -347,6 +403,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( return false; mst_mgr = &aconnector->mst_root->mst_mgr; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); @@ -370,7 +427,91 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( * sequence. copy DRM MST allocation to dc */ fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table); +#else +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + dm_conn_state = to_dm_connector_state(aconnector->base.state); +#endif + if (!mst_mgr->mst_state) + return false; + + mst_port = aconnector->port; + +#if defined(CONFIG_DRM_AMD_DC_DCN) + link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); +#endif + if (enable) { + +#if !defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + clock = stream->timing.pix_clk_100hz / 10; + + switch (stream->timing.display_color_depth) { + + case COLOR_DEPTH_666: + bpp = 6; + break; + case COLOR_DEPTH_888: + bpp = 8; + break; + case COLOR_DEPTH_101010: + bpp = 10; + break; + case COLOR_DEPTH_121212: + bpp = 12; + break; + case COLOR_DEPTH_141414: + bpp = 14; + break; + case COLOR_DEPTH_161616: + bpp = 16; + break; + default: + ASSERT(bpp != 0); + break; + } + + bpp = bpp * 3; + + /* TODO need to know link rate */ + pbn = drm_dp_calc_pbn_mode(clock, bpp, false); + + slots = drm_dp_find_vcpi_slots(mst_mgr, pbn); + ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, +#ifdef HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I + slots); +#else + &slots); +#endif /* HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I */ +#else + ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, + dm_conn_state->pbn, +#ifdef HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I + dm_conn_state->vcpi_slots); +#else + &dm_conn_state->vcpi_slots); +#endif /* HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I */ +#endif + if (!ret) + return false; + + } else { + drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port); + } + + /* It's OK for this to fail */ +#ifdef HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG + drm_dp_update_payload_part1(mst_mgr, (link_coding_cap == DP_CAP_ANSI_128B132B) ? 0:1); +#else + drm_dp_update_payload_part1(mst_mgr); +#endif + + /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or + * AUX message. The sequence is slot 1-63 allocated sequence for each + * stream. AMD ASIC stream slot allocation should follow the same + * sequence. copy DRM MST allocation to dc */ + + fill_dc_mst_payload_table_from_drm(aconnector, proposed_table); +#endif return true; } @@ -425,9 +566,13 @@ void dm_helpers_dp_mst_send_payload_allocation( const struct dc_stream_state *stream) { struct amdgpu_dm_connector *aconnector; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) struct drm_dp_mst_topology_state *mst_state; - struct drm_dp_mst_topology_mgr *mst_mgr; struct drm_dp_mst_atomic_payload *new_payload; +#else + struct drm_dp_mst_port *mst_port; +#endif + struct drm_dp_mst_topology_mgr *mst_mgr; enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; int ret = 0; @@ -438,11 +583,21 @@ void dm_helpers_dp_mst_send_payload_allocation( return; mst_mgr = &aconnector->mst_root->mst_mgr; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); - ret = drm_dp_add_payload_part2(mst_mgr, new_payload); +#else + mst_port = aconnector->port; + if (!mst_mgr->mst_state) + return; +#endif +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) + ret = drm_dp_add_payload_part2(mst_mgr, new_payload); +#else + ret = drm_dp_update_payload_part2(mst_mgr); +#endif if (ret) { amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, false); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 43bdddd655540..9804fc6da7ee1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -457,6 +457,9 @@ /* drm_dp_mst_topology_mgr_resume() wants 2 args */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS 1 +/* struct drm_dp_mst_topology_state has member payloads */ +#define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS 1 + /* struct drm_dp_mst_topology_state has member total_avail_slots */ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index 646dc3b137f68..8e57e77b7a138 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -22,3 +22,28 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS], [ ]) ]) + +dnl # +dnl # commit 8366f01fb15a54281c193658d1a916f6f2d5eb1e +dnl # drm/display/dp_mst: Move all payload info into the atomic state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ], [ + struct drm_dp_mst_topology_state * mst_state = NULL; + struct list_head payloads; + payloads = mst_state->payloads; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS, 1, + [struct drm_dp_mst_topology_state has member payloads]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 93704b59ff7c9..7c03d809afb77 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -220,6 +220,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ACPI_VIDEO_FUNCS AC_AMDGPU_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_MEMORY_DEVICE_COHERENT + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 4ccaf82b9d1e07ff07a1c9e3e86279909dbd3b3a Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 1 Feb 2023 11:15:13 +0800 Subject: [PATCH 0912/2653] drm/amdkcl:wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV It's caused by 4d07b0bc403403438d9cf88450506240c5faf92f "drm/display/dp_mst: Move all payload info into the atomic state" Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 22 +++++++++++++-- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-dp-mst-topology-state.m4 | 27 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 57 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4c5c6b4923e5c..cb8bca334b2fa 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8080,7 +8080,9 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; struct drm_dp_mst_topology_mgr *mst_mgr; struct drm_dp_mst_port *mst_port; +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV struct drm_dp_mst_topology_state *mst_state; +#endif enum dc_color_depth color_depth; int clock, bpp = 0; bool is_y420 = false; @@ -8111,11 +8113,13 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, if (!crtc_state->connectors_changed && !crtc_state->mode_changed) return 0; +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); if (IS_ERR(mst_state)) return PTR_ERR(mst_state); mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link)); +#endif if (!state->duplicated) { int max_bpc = conn_state->max_requested_bpc; @@ -12389,6 +12393,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS /* set the slot info for each mst_state based on the link encoding format */ @@ -12411,6 +12416,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, drm_connector_list_iter_end(&iter); } #endif +#endif #endif /** * Streams and planes are reset when there are changes that affect diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index eb17b09ecd119..3751cdb57ae4a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1102,11 +1102,18 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, int min_initial_slack; int next_index; int remaining_to_increase = 0; +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + int pbn_per_timeslot; +#endif int link_timeslots_used; int fair_pbn_alloc; int ret = 0; uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + pbn_per_timeslot = dm_mst_get_pbn_divider(dc_link); +#endif + for (i = 0; i < count; i++) { if (vars[i + k].dsc_enabled) { initial_slack[i] = @@ -1137,10 +1144,21 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, link_timeslots_used = 0; for (i = 0; i < count; i++) - link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, dfixed_trunc(mst_state->pbn_div)); + link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + dfixed_trunc(mst_state->pbn_div) +#else + pbn_per_timeslot +#endif + ); fair_pbn_alloc = - (63 - link_timeslots_used) / remaining_to_increase * dfixed_trunc(mst_state->pbn_div); + (63 - link_timeslots_used) / remaining_to_increase * +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + dfixed_trunc(mst_state->pbn_div); +#else + pbn_per_timeslot; +#endif if (initial_slack[next_index] > fair_pbn_alloc) { vars[next_index].pbn += fair_pbn_alloc; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9804fc6da7ee1..7ca5449092713 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -460,6 +460,9 @@ /* struct drm_dp_mst_topology_state has member payloads */ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS 1 +/* struct drm_dp_mst_topology_state has member pbn_div */ +#define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV 1 + /* struct drm_dp_mst_topology_state has member total_avail_slots */ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index 8e57e77b7a138..717d2d88653c3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -47,3 +47,30 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS], [ ]) ]) ]) + + +dnl # +dnl # commit v5.19-rc6-1771-g4d07b0bc4034 +dnl # drm/display/dp_mst: Move all payload info into the atomic state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ], [ + struct drm_dp_mst_topology_state * mst_state = NULL; + int pbn_div; + pbn_div = mst_state->pbn_div; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV, 1, + [struct drm_dp_mst_topology_state has member pbn_div]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7c03d809afb77..5ba208b8135e5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -221,6 +221,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_MEMORY_DEVICE_COHERENT AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 2758fb22758a32064434301f61ad7947cdbcd490 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 2 Feb 2023 13:27:02 +0800 Subject: [PATCH 0913/2653] drm/amdkcl: wrap code under macro HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS It's caused by 4d07b0bc403403438d9cf88450506240c5faf92f "drm/display/dp_mst: Move all payload info into the atomic state" Signed-off-by: Asher Song Reviewed-by: Leslie Shi Reviewed-by: Flora Cui --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 54 +++++++++++++++---- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 8 ++- .../backport/kcl_drm_dp_mst_helper_backport.h | 2 +- 5 files changed, 59 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index cb8bca334b2fa..bb287d10f162e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8136,7 +8136,11 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, - dm_new_connector_state->pbn); + dm_new_connector_state->pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(aconnector->dc_link) +#endif + ); if (dm_new_connector_state->vcpi_slots < 0) { DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); return dm_new_connector_state->vcpi_slots; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 3751cdb57ae4a..a4ecee5b72d72 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1165,7 +1165,11 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , pbn_per_timeslot +#endif + ); if (ret < 0) return ret; @@ -1177,7 +1181,11 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , pbn_per_timeslot +#endif + ); if (ret < 0) return ret; } @@ -1186,7 +1194,11 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , pbn_per_timeslot +#endif + ); if (ret < 0) return ret; @@ -1198,7 +1210,11 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , pbn_per_timeslot +#endif + ); if (ret < 0) return ret; } @@ -1261,7 +1277,11 @@ static int try_disable_dsc(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) { DRM_DEBUG_DRIVER("%s:%d MST_DSC index #%d, failed to set pbn to the state, %d\n", __func__, __LINE__, next_index, ret); @@ -1280,7 +1300,11 @@ static int try_disable_dsc(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) { DRM_DEBUG_DRIVER("%s:%d MST_DSC index #%d, failed to set pbn to the state, %d\n", __func__, __LINE__, next_index, ret); @@ -1402,7 +1426,11 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, vars[i + k].dsc_enabled = false; vars[i + k].bpp_x16 = 0; ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port, - vars[i + k].pbn); + vars[i + k].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) return ret; } @@ -1424,7 +1452,11 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, vars[i + k].dsc_enabled = true; vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16; ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, - params[i].port, vars[i + k].pbn); + params[i].port, vars[i + k].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) return ret; } else { @@ -1432,7 +1464,11 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, vars[i + k].dsc_enabled = false; vars[i + k].bpp_x16 = 0; ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, - params[i].port, vars[i + k].pbn); + params[i].port, vars[i + k].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) return ret; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7ca5449092713..dcbe08cc190ef 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -368,7 +368,7 @@ /* #undef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP */ /* drm_dp_atomic_find_time_slots() is available */ -/* #undef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS */ +#define HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS 1 /* drm_dp_mst_atomic_setup_commit() is available */ /* #undef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index a67dc29ccbeb2..f19d5bf4ea976 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -51,10 +51,16 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else #include + #endif ],[ int ret; - ret = drm_dp_atomic_find_time_slots(NULL, NULL, NULL, 0, 0); + ret = drm_dp_atomic_find_time_slots(NULL, NULL, NULL, 0); ],[ AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS, 1, [drm_dp_atomic_find_time_slots() is available]) diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 6a5e6961228bb..edac58606beb9 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -72,7 +72,7 @@ int _kcl_drm_dp_atomic_find_time_slots(struct drm_atomic_state *state, struct drm_dp_mst_port *port, int pbn, int pbn_div) { - return 0; + return drm_dp_atomic_find_vcpi_slots(state, mgr, port, pbn, pbn_div); } #define drm_dp_atomic_find_time_slots _kcl_drm_dp_atomic_find_time_slots #endif From 916327861c693b44bc310ab25a00e852d84ad0c6 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 1 Feb 2023 11:36:14 +0800 Subject: [PATCH 0914/2653] drm/amdkcl: wrap code under marco HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT It's caused by 4d07b0bc403403438d9cf88450506240c5faf92f "drm/display/dp_mst: Move all payload info into the atomic state" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 7 ++++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index a4ecee5b72d72..88707ec414a84 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -952,7 +952,12 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap); aconnector->mst_mgr.cbs = &dm_mst_cbs; drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev), - &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id); + &aconnector->dm_dp_aux.aux, 16, 4, +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT + max_link_enc_cap.lane_count, + drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate), +#endif + aconnector->connector_id); drm_connector_attach_dp_subconnector_property(&aconnector->base); } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index dcbe08cc190ef..e1c812cfd0b94 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -454,6 +454,9 @@ /* drm_dp_mst_topology_mgr_init() wants drm_device arg */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_DRM_DEV 1 +/* drm_dp_mst_topology_mgr_init() has max_lane_count and max_link_rate */ +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT */ + /* drm_dp_mst_topology_mgr_resume() wants 2 args */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS 1 From c8bade067ff32bd55465e5fa00154c9a76de0af1 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 2 Feb 2023 14:17:39 +0800 Subject: [PATCH 0915/2653] drm/amdkcl: check drm_dp_mst_atomic_enable_dsc whether has four arguments It's caused by 4d07b0bc403403438d9cf88450506240c5faf92f "drm/display/dp_mst: Move all payload info into the atomic state" Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ++++++++-- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 | 22 +++++++++++++++++++ 3 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index bb287d10f162e..1ab818d5ca87a 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8216,14 +8216,22 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, dm_conn_state->vcpi_slots = slot_num; ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, - dm_conn_state->pbn, false); + dm_conn_state->pbn, +#ifdef HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS + 0, +#endif + false); if (ret < 0) return ret; continue; } - vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); + vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, +#ifdef HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS + 0, +#endif + true); if (vcpi < 0) return vcpi; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e1c812cfd0b94..2e14b125d76e1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -421,6 +421,9 @@ /* drm_dp_mst_atomic_enable_dsc() is available */ #define HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC 1 +/* drm_dp_mst_atomic_enable_dsc() wants 5args */ +/* #undef HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS */ + /* drm_dp_mst_detect_port() wants p,p,p,p args */ #define HAVE_DRM_DP_MST_DETECT_PORT_PPPP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 index 806158f1562a8..0019f393b38f3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 @@ -17,6 +17,28 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ ], [drm_dp_mst_atomic_enable_dsc], [drivers/gpu/drm/drm_dp_mst_topology.c], [ AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC, 1, [drm_dp_mst_atomic_enable_dsc() is available]) + AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS, 1, + [drm_dp_mst_atomic_enable_dsc() wants 5args]) + ],[ + dnl # + dnl # commit 4d07b0bc403403438d9cf88450506240c5faf92f + dnl # drm/display/dp_mst: Move all payload info into the atomic state + dnl # + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ], [ + int vcpi; + vcpi = drm_dp_mst_atomic_enable_dsc(NULL, NULL, 0, false); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC, 1, + [drm_dp_atomic_find_vcpi_slots() is available]) + ]) ]) ]) ]) From f82ce1be01da68f50d5db424b282f4bc43bfbae3 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 6 Jan 2023 09:23:42 +0800 Subject: [PATCH 0916/2653] drm/amdkcl: Check the gcc and kernel version before the compilation starts Check the gcc and kernel version before the compilation starts. This is mainly used for some special application scenarios. For example, Some customers use kernel 5.4 and gcc 4.8.5 This will cause the compilations failure. So we check this case and provide a hint. Change-Id: I448d9c289ea66da701291df42bed504ed4dfb782 Signed-off-by: Ma Jun Suggested-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/Makefile | 52 ++++++++++++++++++++----------- 1 file changed, 34 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 9d2de6369b657..2e8db344899bd 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -1,27 +1,24 @@ -ifndef CONFIG_DRM -$(error CONFIG_DRM disabled, exit...) -endif - -ifeq (y,$(CONFIG_DRM_AMDGPU)) -$(error DRM_AMDGPU is built-in, exit...) -endif - -ifndef CONFIG_KALLSYMS -$(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) -endif - -_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") - -ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) -$(error dma_resv->seq is missing. exit...) -endif - ifeq ($(CC), gcc) GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) GCCPAT=$(shell echo __GNUC_PATCHLEVEL__ | $(CC) -E -x c - | tail -n 1) # CONFIG_GCC_VERSION returns x.xx.xx as the version format GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) + +KERNEL_MAJ=$(VERSION) +KERNEL_PATCHLEVEL=$(PATCHLEVEL) +KERNEL_SUBLEVEL=$(SUBLEVEL) +KERNEL_VER=$(shell printf "%d%02d%02d" $(KERNEL_MAJ) $(KERNEL_PATCHLEVEL), $(KERNEL_SUBLEVEL)) + +kernel-version = $(shell [ $(KERNEL_VER)0 $(1) $(2)000 ] && echo $(3) || echo $(4)) + +# gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. +ifeq ($(call cc-ifversion, -le, 0408, y), y) +ifeq ($(call kernel-version, -ge, 0504, y), y) +$(error "The GCC is too old for this kernel, please update the GCC to higher than 9.3") +endif +endif + ifdef CONFIG_CC_IS_GCC ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) $(warning "Local GCC version $(GCCSTR) does not match kernel compiler GCC version $(CONFIG_GCC_VERSION)") @@ -32,6 +29,25 @@ export CONFIG_CC_IS_GCC=y export CONFIG_GCC_VERSION=$(GCCSTR) $(warning "CONFIG_CC_IS_GCC is not defined. Let's export it with version $(CONFIG_GCC_VERSION)") endif + +endif + +ifndef CONFIG_DRM +$(error CONFIG_DRM disabled, exit...) +endif + +ifeq (y,$(CONFIG_DRM_AMDGPU)) +$(error DRM_AMDGPU is built-in, exit...) +endif + +ifndef CONFIG_KALLSYMS +$(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) +endif + +_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") + +ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) +$(error dma_resv->seq is missing. exit...) endif DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) From b28456d4b5ba0c09989eeb89d5dde6174c5aa954 Mon Sep 17 00:00:00 2001 From: Horatio Zhang Date: Mon, 30 Jan 2023 16:52:42 +0800 Subject: [PATCH 0917/2653] drm/amdkcl: wrap code under CONFIG_DRM_AMD_DC_DSC_SUPPORT and CONFIG_DRM_AMD_DC_DCN It's cause by 'commit 05c1deaaaa92 ("drm/amd/display: move dp capability related logic to link_dp_capability")' 'commit 9a29f20c0621 ("drm/amd/display: move dp link training logic to link_dp_training")' Missing macro during code movement. link_dp_capability - missing CONFIG_DRM_AMD_DC_DCN macro link_dp_training - missing CONFIG_DRM_AMD_DC_DSC_SUPPORT macro when moving code from dc_link_dp.c link_dp_training_8b_10b - missing CONFIG_DRM_AMD_DC_DSC_SUPPORT macro when moving code from dc_link_dp.c link_dp_training_dpia - missing CONFIG_DRM_AMD_DC_DSC_SUPPORT macro when moving code from link_dp_dpia.c Signed-off-by: Horatio Zhang --- .../amd/display/dc/link/protocols/link_dp_capability.c | 8 +++++++- .../drm/amd/display/dc/link/protocols/link_dp_training.c | 3 +++ .../display/dc/link/protocols/link_dp_training_8b_10b.c | 2 ++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index e0c4416993d94..c13e154e6ffec 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -161,11 +161,12 @@ uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count) uint32_t dp_get_closest_lttpr_offset(uint8_t lttpr_count) { /* Calculate offset for LTTPR closest to DPTX which is highest in the chain - * Offset is 0 for single LTTPR cases as base LTTPR DPCD addresses target LTTPR 1 + * Offset is 1 for single LTTPR cases as base LTTPR DPCD addresses target LTTPR 1 */ return DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE * (lttpr_count - 1); } +#if defined(CONFIG_DRM_AMD_DC_DCN) uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw) { switch (bw) { @@ -185,6 +186,7 @@ uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw) return 0; } +#endif static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz) { @@ -249,6 +251,7 @@ static union dp_cable_id intersect_cable_id( return out; } +#if defined(CONFIG_DRM_AMD_DC_DCN) /* * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw. */ @@ -278,6 +281,7 @@ static uint32_t intersect_frl_link_bw_support( return supported_bw_in_kbps; } +#endif static enum clock_source_id get_clock_source_id(struct dc_link *link) { @@ -1220,6 +1224,7 @@ static void get_active_converter_info( translate_dpcd_max_bpc( hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT); +#if defined(CONFIG_DRM_AMD_DC_DCN) if (link->dc->caps.dp_hdmi21_pcon_support) { link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = @@ -1231,6 +1236,7 @@ static void get_active_converter_info( if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0) link->dpcd_caps.dongle_caps.extendedCapValid = true; } +#endif if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0) link->dpcd_caps.dongle_caps.extendedCapValid = true; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c index 134093ce5a8e8..aaf2853cb7fb1 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c @@ -777,8 +777,11 @@ void override_training_settings( lt_settings->pattern_for_eq = *overrides->pattern_for_eq; if (overrides->enhanced_framing != NULL) lt_settings->enhanced_framing = *overrides->enhanced_framing; + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (link->preferred_training_settings.fec_enable != NULL) lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable; +#endif /* Check DP tunnel LTTPR mode debug option. */ if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->dc->debug.dpia_debug.bits.force_non_lttpr) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c index 66d0fb1b9b9d2..ee1a1c755332c 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c @@ -136,7 +136,9 @@ void decide_8b_10b_training_settings( lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting); lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_res, link_setting); lt_settings->enhanced_framing = 1; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT lt_settings->should_set_fec_ready = true; +#endif lt_settings->disallow_per_lane_settings = true; lt_settings->always_match_dpcd_with_hw_lane_settings = true; lt_settings->lttpr_mode = dp_decide_8b_10b_lttpr_mode(link); From 924c9ce40aa7e9db5984b5a439b2508c7f75563b Mon Sep 17 00:00:00 2001 From: Horatio Zhang Date: Tue, 31 Jan 2023 12:53:17 +0800 Subject: [PATCH 0918/2653] drm/amdkcl: wrap code under macro CONFIG_DRM_AMD_DC_DSC_SUPPORT It's cause by 'commit 05c1deaaaa92 ("drm/amd/display: move dp capability related logic to link_dp_capability")' Missing macro during code movement. link_dp_capability - missing CONFIG_DRM_AMD_DC_DSC_SUPPORT macro when moving code from dc_link_dp.c link_edp_panel_control - fuction "decide_edp_link_settings" is changed to "dc_link_decide_edp_link_settings" Signed-off-by: Horatio Zhang --- .../drm/amd/display/dc/link/protocols/link_dp_capability.c | 6 ++++++ .../drm/amd/display/dc/link/protocols/link_dp_capability.h | 2 ++ .../amd/display/dc/link/protocols/link_edp_panel_control.c | 2 +- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index c13e154e6ffec..5b64c03c91b55 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -452,6 +452,7 @@ static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link) return lttpr_max_link_rate; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link) { enum dc_link_rate cable_max_link_rate = LINK_RATE_UNKNOWN; @@ -471,6 +472,7 @@ static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link) return cable_max_link_rate; } +#endif static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) { @@ -813,6 +815,7 @@ bool edp_decide_link_settings(struct dc_link *link, return false; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool decide_edp_link_settings_with_dsc(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw, @@ -941,6 +944,7 @@ bool decide_edp_link_settings_with_dsc(struct dc_link *link, } return false; } +#endif static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting) { @@ -1947,6 +1951,7 @@ static bool retrieve_link_cap(struct dc_link *link) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT memset(&link->dpcd_caps.dsc_caps, '\0', sizeof(link->dpcd_caps.dsc_caps)); memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap)); @@ -2014,6 +2019,7 @@ static bool retrieve_link_cap(struct dc_link *link) } else link->wa_flags.dpia_forced_tbt3_mode = false; } +#endif if (!dpcd_read_sink_ext_caps(link)) link->dpcd_sink_ext_caps.raw = 0; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h index 7170db5a1c13e..f46c4d3537e38 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h @@ -81,10 +81,12 @@ bool link_decide_link_settings( bool edp_decide_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool decide_edp_link_settings_with_dsc(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw, enum dc_link_rate max_link_rate); +#endif enum dp_link_encoding mst_decide_link_encoding_format(const struct dc_link *link); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 5fbc3e0240470..3c7b68456753a 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -386,7 +386,7 @@ bool edp_is_ilr_optimization_required(struct dc_link *link, else decide_edp_link_settings_with_dsc(link, &link_setting, req_bw, LINK_RATE_UNKNOWN); #else - decide_edp_link_settings(link, &link_setting, req_bw); + dc_link_decide_edp_link_settings(link, &link_setting, req_bw); #endif if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate || From 744c7140e237b58df4a7f995abd29c0097deea56 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 14 Feb 2023 17:02:38 +0800 Subject: [PATCH 0919/2653] drm/amdkcl: update kcl macro for amdgpu_dm_atomic_check() It's caused by 52be8da751ab9476a0adfcd71d112850dae8248c "drm/amdgpu/display/mst: Fix mst_state->pbn_div and slot count assignments" Signed-off-by: Bob Zhou Reviewed-by: Asher Song Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1ab818d5ca87a..6409a8de2ce57 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12070,9 +12070,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, bool is_top_most_overlay = true; struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS struct drm_dp_mst_topology_mgr *mgr; -#endif struct drm_dp_mst_topology_state *mst_state; struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; #endif @@ -12405,7 +12403,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } -#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS /* set the slot info for each mst_state based on the link encoding format */ @@ -12415,6 +12412,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_connector_list_iter iter; u8 link_coding_cap; +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + if (!mgr->mst_state ) + continue; +#endif drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { if (connector->index == mst_state->mgr->conn_base_id) { From 194b50885e5873e89311e4990c8d0886d0c89760 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 7 Feb 2023 17:24:27 +0800 Subject: [PATCH 0920/2653] drm/amdkcl: modify the naming of mst_port and port for kcl code It's caused by d6daeede3abe864d0dca1c74edf1af5a3a018297 "drm/amdgpu/display/mst: adjust the naming of mst_port and port of aconnector" The term (i.e. port & mst_port) are renamed to mst_output_port & mst_root respectively. So some code under kcl macro need to be renamed. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 +++--- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 6c1f14a9fbf02..84db62f16a1d2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -292,7 +292,7 @@ fill_dc_mst_payload_table_from_drm(struct amdgpu_dm_connector *aconnector, { int i; struct drm_dp_mst_topology_mgr *mst_mgr = - &aconnector->mst_port->mst_mgr; + &aconnector->mst_root->mst_mgr; mutex_lock(&mst_mgr->payload_lock); @@ -434,7 +434,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( if (!mst_mgr->mst_state) return false; - mst_port = aconnector->port; + mst_port = aconnector->mst_output_port; #if defined(CONFIG_DRM_AMD_DC_DCN) link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); @@ -588,7 +588,7 @@ void dm_helpers_dp_mst_send_payload_allocation( new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); #else - mst_port = aconnector->port; + mst_port = aconnector->mst_output_port; if (!mst_mgr->mst_state) return; #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 88707ec414a84..a5d5617542654 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -148,13 +148,13 @@ static enum drm_connector_status dm_dp_mst_detect(struct drm_connector *connector, bool force) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); - struct amdgpu_dm_connector *master = aconnector->mst_port; + struct amdgpu_dm_connector *master = aconnector->mst_root; enum drm_connector_status status = drm_dp_mst_detect_port( connector, &master->mst_mgr, - aconnector->port); + aconnector->mst_output_port); return status; } @@ -856,7 +856,7 @@ static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n", - aconnector, connector->base.id, aconnector->mst_port); + aconnector, connector->base.id, aconnector->mst_root); if (aconnector->dc_sink) { amdgpu_dm_update_freesync_caps(connector, NULL); From f1a247500a303913ba49445bd3e008e998fbe6fa Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 14 Feb 2023 13:03:24 +0800 Subject: [PATCH 0921/2653] drm/amdkcl: check drm/drm_fbdev_generic.h whether exist It's caused by 8ab59da26bc0ae0abfcaabc4218c74827d154256 "drm/fb-helper: Move generic fbdev emulation into separate source file" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 055736d17b86a..ccdccb0e48d30 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -92,4 +92,11 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/amdgpu: add drm buddy support to amdgpu dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_buddy.h]) + + dnl # + dnl # v6.1-rc2-542-g8ab59da26bc0 + dnl # drm/fb-helper: Move generic fbdev emulation into separate source file + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_fbdev_generic.h]) + ]) From 64275564e2db503d48be277b7b3cebd824462ed0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 14 Feb 2023 13:04:54 +0800 Subject: [PATCH 0922/2653] drm/amdkcl: for instance of ttm_resource struct, change member num_pages to size It's caused by 0f9cd1ea10d307cad221d6693b648a8956e812b0 "drm/ttm: fix bulk move handling v2" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 2b7cb217472b9..0301a5e4375a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -715,11 +715,11 @@ int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data, return r; abo = gem_to_amdgpu_bo(gobj); - dma_addr = kmalloc_array(abo->tbo.resource->num_pages, sizeof(dma_addr_t), GFP_KERNEL); + dma_addr = kmalloc_array(PFN_UP(abo->tbo.resource->size), sizeof(dma_addr_t), GFP_KERNEL); if (unlikely(dma_addr == NULL)) goto release_object; - for (i = 0; i < abo->tbo.resource->num_pages; i++) + for (i = 0; i < PFN_UP(abo->tbo.resource->size); i++) dma_addr[i] = args->addr + i * PAGE_SIZE; abo->dgma_import_base = args->addr; abo->dgma_addr = (void *)dma_addr; From cbff70c672c6292c54925933163a760d1494d180 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 14 Feb 2023 16:45:45 +0800 Subject: [PATCH 0923/2653] drm/amdkcl: test struct migrate_vma whether has member fault_page It's caused by 16ce101db85d "mm/memory.c: fix race when faulting a device private page" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/migrate_vma_fault_page.m4 | 19 +++++++++++++++++++ 3 files changed, 22 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 22a7102f93dae..6d6b07de96df8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -746,7 +746,9 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, migrate.src = buf; migrate.dst = migrate.src + npages; +#ifdef HAVE_MIGRATE_VMA_FAULT_PAGE migrate.fault_page = fault_page; +#endif scratch = (dma_addr_t *)(migrate.dst + npages); kfd_smi_event_migration_start(node, p->lead_thread->pid, diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5ba208b8135e5..3a8102d9576cd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -222,6 +222,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MEMORY_DEVICE_COHERENT AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 b/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 new file mode 100644 index 0000000000000..406fa50e310c5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit v6.0-rc3-595-g16ce101db85d +dnl # mm/memory.c: fix race when faulting a device private page +dnl # +AC_DEFUN([AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct migrate_vma mig = {0}; + struct page *fault_page; + mig.fault_page = fault_page; + ], [ + AC_DEFINE(HAVE_MIGRATE_VMA_FAULT_PAGE, 1, + [struct migrate_vma has fault_page]) + ]) + ]) +]) + From d304912f24e70654ef6cd2da0fff02d8a8631ed0 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 2 Feb 2023 16:36:38 +0800 Subject: [PATCH 0924/2653] drm/amdkcl: move drm_buddy and drm_ttm_helper compile config from Makefile to subfile Create new files Makefile.drm_buddy and Makefile.drm_ttm_helper, and move drm_buddy and drm_ttm_helper compile config into them. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 16 +++------------- drivers/gpu/drm/amd/dkms/Makefile.drm_buddy | 6 ++++++ drivers/gpu/drm/amd/dkms/Makefile.drm_ttm_helper | 8 ++++++++ 3 files changed, 17 insertions(+), 13 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/Makefile.drm_buddy create mode 100644 drivers/gpu/drm/amd/dkms/Makefile.drm_ttm_helper diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 2e8db344899bd..a0e67352e5b38 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -210,18 +210,8 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DSC_SUPPORT endif endif -export CONFIG_DRM_TTM_HELPER=m -subdir-ccflags-y += -DCONFIG_DRM_TTM_HELPER -CFLAGS_drm_gem_ttm_helper.o += -include $(src)/ttm/backport/backport.h \ - -include $(src)/include/kcl/backport/kcl_drm_gem.h \ - -DHAVE_CONFIG_H -amddrm_ttm_helper-y := drm_gem_ttm_helper.o -obj-$(CONFIG_DRM_TTM_HELPER) += amddrm_ttm_helper.o - -export CONFIG_DRM_BUDDY=m -subdir-ccflags-y += -DCONFIG_DRM_BUDDY -CFLAGS_drm_buddy.o += -DHAVE_CONFIG_H -amddrm_buddy-y := drm_buddy.o -obj-$(CONFIG_DRM_BUDDY) += amddrm_buddy.o +include $(src)/amd/dkms/Makefile.drm_ttm_helper + +include $(src)/amd/dkms/Makefile.drm_buddy obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy b/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy new file mode 100644 index 0000000000000..208c05b48758d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy @@ -0,0 +1,6 @@ +export CONFIG_DRM_BUDDY=m + +subdir-ccflags-y += -DCONFIG_DRM_BUDDY +CFLAGS_drm_buddy.o += -DHAVE_CONFIG_H +amddrm_buddy-y := drm_buddy.o +obj-$(CONFIG_DRM_BUDDY) += amddrm_buddy.o diff --git a/drivers/gpu/drm/amd/dkms/Makefile.drm_ttm_helper b/drivers/gpu/drm/amd/dkms/Makefile.drm_ttm_helper new file mode 100644 index 0000000000000..b76db38d020a2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.drm_ttm_helper @@ -0,0 +1,8 @@ +export CONFIG_DRM_TTM_HELPER=m + +subdir-ccflags-y += -DCONFIG_DRM_TTM_HELPER +CFLAGS_drm_gem_ttm_helper.o += -include $(src)/ttm/backport/backport.h \ + -include $(src)/include/kcl/backport/kcl_drm_gem.h \ + -DHAVE_CONFIG_H +amddrm_ttm_helper-y := drm_gem_ttm_helper.o +obj-$(CONFIG_DRM_TTM_HELPER) += amddrm_ttm_helper.o From df5588bf3d5e419f78b05959282bda22845d527d Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 1 Feb 2023 16:19:14 +0800 Subject: [PATCH 0925/2653] drm/amdkcl: Implement the drm_kms_helper_connector_hotplug_event() Implement the drm_kms_helper_connector_hotplug_event() for legacy os Signed-off-by: Bob Zhou Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 ------------------- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 -------- include/kcl/backport/kcl_drm_probe_helper.h | 16 +++++++++++++++ 4 files changed, 17 insertions(+), 28 deletions(-) create mode 100644 include/kcl/backport/kcl_drm_probe_helper.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index bbdb386892d49..76bf0d096d295 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -108,4 +108,5 @@ * include drm_damage_helper.h to fix the missing function declaration for legacy kernel. */ #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6409a8de2ce57..99f7649ea0143 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1526,11 +1526,7 @@ static void force_connector_state( mutex_unlock(&connector->dev->mode_config.mutex); mutex_lock(&aconnector->hpd_lock); -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(connector->dev); -#endif mutex_unlock(&aconnector->hpd_lock); } @@ -3897,11 +3893,7 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) drm_modeset_unlock_all(dev); if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(dev); -#endif } else { scoped_guard(mutex, &adev->dm.dc_lock) { dc_exit_ips_for_hw_access(dc); @@ -3917,11 +3909,7 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) drm_modeset_unlock_all(dev); if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(dev); -#endif } } } @@ -4054,11 +4042,7 @@ static void handle_hpd_rx_irq(void *param) dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(dev); -#endif } else { bool ret = false; @@ -4077,11 +4061,7 @@ static void handle_hpd_rx_irq(void *param) dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(dev); -#endif } } } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 7f0c4458b85ea..74fe83820e811 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -1505,11 +1505,7 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(dev); -#endif } else if (param[0] == 0) { if (!aconnector->dc_link) goto unlock; @@ -1535,11 +1531,7 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(dev); -#endif } unlock: diff --git a/include/kcl/backport/kcl_drm_probe_helper.h b/include/kcl/backport/kcl_drm_probe_helper.h new file mode 100644 index 0000000000000..3ac7310361bb4 --- /dev/null +++ b/include/kcl/backport/kcl_drm_probe_helper.h @@ -0,0 +1,16 @@ +#ifndef AMDKCL_BACKPORT_DRM_PROBE_HELPER_H +#define AMDKCL_BACKPORT_DRM_PROBE_HELPER_H + +#include + +#ifndef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT +static inline void _kcl_drm_kms_helper_connector_hotplug_event(struct drm_connector *connector) +{ + drm_kms_helper_hotplug_event(connector->dev); +} + +#define drm_kms_helper_connector_hotplug_event _kcl_drm_kms_helper_connector_hotplug_event + + +#endif +#endif From 5d209259f249a72c124b9f337943b0be4a05dec0 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 8 Feb 2023 17:48:59 +0800 Subject: [PATCH 0926/2653] drm/admkcl: wrap code under macro CONFIG_DRM_AMD_DC_DSC_SUPPORT It's caused by def6ddd09e22c65b4367fbf56310a8ed329a713a "drm/amd/display: break down dc_link.c" [why] Move remaining dc_link.c functions into link_detection, link_dpms, link_validation, link_resource, and link_fpga and remove dc_link. [how] Restore macro CONFIG_DRM_AMD_DC_DSC_SUPPORT for these new file. Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 9 ++++++++- drivers/gpu/drm/amd/display/dc/link/link_validation.c | 7 ++++++- .../gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c | 2 ++ .../gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h | 1 - 4 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index cb80b45999360..0e43ae9178bd2 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -769,6 +769,7 @@ static void dsc_optc_config_log(struct display_stream_compressor *dsc, DC_LOG_DSC("\tslice_width %d", config->slice_width); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) { struct dc *dc = pipe_ctx->stream->ctx->dc; @@ -781,6 +782,7 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); return result; } +#endif static bool dp_set_hblank_reduction_on_rx(struct pipe_ctx *pipe_ctx) { @@ -1007,6 +1009,7 @@ bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immedi return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) { struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; @@ -1030,6 +1033,7 @@ bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) out: return result; } +#endif bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) { @@ -2563,12 +2567,13 @@ void link_set_dpms_on( * will be automatically set at a later time when the video is enabled * (DP_VID_STREAM_EN = 1). */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe_ctx->stream->timing.flags.DSC) { if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) link_set_dsc_enable(pipe_ctx, true); } - +#endif status = enable_link(state, pipe_ctx); if (status != DC_OK) { @@ -2613,6 +2618,7 @@ void link_set_dpms_on( dc->hwss.enable_stream(pipe_ctx); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DPS PPS SDP (AKA "info frames") */ if (pipe_ctx->stream->timing.flags.DSC) { if (dc_is_dp_signal(pipe_ctx->stream->signal) || @@ -2621,6 +2627,7 @@ void link_set_dpms_on( link_set_dsc_pps_packet(pipe_ctx, true, true); } } +#endif if (dc_is_dp_signal(pipe_ctx->stream->signal)) dp_set_hblank_reduction_on_rx(pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c index acdc162de5353..937586151e78e 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c @@ -144,10 +144,13 @@ static bool dp_active_dongle_validate_timing( return false; } } - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 && dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 && dongle_caps->dfp_cap_ext.supported) { +#else + if (dongle_caps->dfp_cap_ext.supported) { +#endif if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000)) return false; @@ -242,10 +245,12 @@ uint32_t dp_link_bandwidth_kbps( */ link_rate_per_lane_kbps = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE; total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (dp_should_enable_fec(link)) { total_data_bw_efficiency_x10000 /= 100; total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100; } +#endif break; case DP_128b_132b_ENCODING: /* For 128b/132b encoding: diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c index 49521ac4b0e85..4ac00f9a2c183 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c @@ -135,6 +135,7 @@ void dp_set_drive_settings( dpcd_set_lane_settings(link, lt_settings, DPRX); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready) { /* FEC has to be "set ready" before the link training. @@ -176,6 +177,7 @@ enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource return status; } +#endif void dp_set_fec_enable(struct dc_link *link, const struct link_resource *link_res, bool enable) { diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h index ab1c1f8f1f8b8..e3cbaf6726713 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h @@ -48,7 +48,6 @@ void dp_set_drive_settings( struct dc_link *link, const struct link_resource *link_res, struct link_training_settings *lt_settings); - enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready); From 897399844e3648aa8eac2371747409cefd073895 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 14 Feb 2023 13:25:23 +0800 Subject: [PATCH 0927/2653] drm/admkcl: wrap code under macro CONFIG_DRM_AMD_DC_DSC_SUPPORT It's caused by f57b3411356d482078ad46aadece1847e74e4c83 "drm/amd/display: do not set RX back to SST mode for non 0 mst stream count" A part of disable_link() is moved into disable_link_dp(), so these kcl macro is restored. Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index 0e43ae9178bd2..ee9fba31b877d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -1918,7 +1918,9 @@ static void disable_link_dp(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal) { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_link_settings link_settings = link->cur_link_settings; +#endif if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && link->mst_stream_alloc_table.stream_count > 0) @@ -1935,12 +1937,13 @@ static void disable_link_dp(struct dc_link *link, if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) /* set the sink to SST mode after disabling the link */ enable_mst_on_sink(link, false); - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (link_dp_get_encoding_format(&link_settings) == DP_8b_10b_ENCODING) { dp_set_fec_enable(link, link_res, false); dp_set_fec_ready(link, link_res, false); } +#endif } static void disable_link(struct dc_link *link, From caff4fe4fcfd45b3ed013258e7911111e2dd503a Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 18 Feb 2023 14:59:16 +0800 Subject: [PATCH 0928/2653] drm/amdkcl: add kcl_rbtee.h It's caused by 08fb97de03aa2205c6791301bd83a095abc1949c "drm/sched: Add FIFO sched policy to run queue" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/rbtree.m4 | 19 +++++ include/drm/gpu_scheduler.h | 1 + include/kcl/kcl_rbtree.h | 99 +++++++++++++++++++++++++ 5 files changed, 121 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/rbtree.m4 create mode 100644 include/kcl/kcl_rbtree.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 76bf0d096d295..29f5ada3bd6b3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -109,4 +109,5 @@ */ #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3a8102d9576cd..6632d9f6d97d1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -223,6 +223,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE + AC_AMDGPU_RB_ADD_CACHED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/rbtree.m4 b/drivers/gpu/drm/amd/dkms/m4/rbtree.m4 new file mode 100644 index 0000000000000..0a29c2b864323 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/rbtree.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v5.11-20-g2d24dd5798d0 +dnl # rbtree: Add generic add and find helpers +dnl # +AC_DEFUN([AC_AMDGPU_RB_ADD_CACHED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + rb_add_cached(NULL, NULL, NULL); + ],[ + AC_DEFINE(HAVE_RB_ADD_CACHED, 1, + [rb_add_cached is available]) + ]) + ]) +]) + + + diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h index daba51a67ad4c..d487fda4e7fa2 100644 --- a/include/drm/gpu_scheduler.h +++ b/include/drm/gpu_scheduler.h @@ -29,6 +29,7 @@ #include #include #include +#include #define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000) diff --git a/include/kcl/kcl_rbtree.h b/include/kcl/kcl_rbtree.h new file mode 100644 index 0000000000000..6d3bf91f7b4f9 --- /dev/null +++ b/include/kcl/kcl_rbtree.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef AMDKCL_LINUX_RBTREE_H +#define AMDKCL_LINUX_RBTREE_H + +#include + +#ifndef HAVE_RB_ROOT_CACHED +/* + * Leftmost-cached rbtrees. + * + * We do not cache the rightmost node based on footprint + * size vs number of potential users that could benefit + * from O(1) rb_last(). Just not worth it, users that want + * this feature can always implement the logic explicitly. + * Furthermore, users that want to cache both pointers may + * find it a bit asymmetric, but that's ok. + */ +struct rb_root_cached { + struct rb_root rb_root; + struct rb_node *rb_leftmost; +}; + +#define RB_ROOT_CACHED (struct rb_root_cached) { {NULL, }, NULL } +#define rb_first_cached(root) (root)->rb_leftmost + +static inline struct rb_node * +rb_erase_cached(struct rb_node *node, struct rb_root_cached *root) +{ + struct rb_node *leftmost = NULL; + + if (root->rb_leftmost == node) + leftmost = root->rb_leftmost = rb_next(node); + + rb_erase(node, &root->rb_root); + + return leftmost; +} + +static inline void rb_insert_color_cached(struct rb_node *node, + struct rb_root_cached *root, + bool leftmost) +{ + if (leftmost) + root->rb_leftmost = node; + rb_insert_color(node, &root->rb_root); +} +#endif + +#ifndef HAVE_RB_ADD_CACHED +/* + * The below helper functions use 2 operators with 3 different + * calling conventions. The operators are related like: + * + * comp(a->key,b) < 0 := less(a,b) + * comp(a->key,b) > 0 := less(b,a) + * comp(a->key,b) == 0 := !less(a,b) && !less(b,a) + * + * If these operators define a partial order on the elements we make no + * guarantee on which of the elements matching the key is found. See + * rb_find(). + * + * The reason for this is to allow the find() interface without requiring an + * on-stack dummy object, which might not be feasible due to object size. + */ + +/** + * rb_add_cached() - insert @node into the leftmost cached tree @tree + * @node: node to insert + * @tree: leftmost cached tree to insert @node into + * @less: operator defining the (partial) node order + * + * Returns @node when it is the new leftmost, or NULL. + */ +static __always_inline struct rb_node * +rb_add_cached(struct rb_node *node, struct rb_root_cached *tree, + bool (*less)(struct rb_node *, const struct rb_node *)) +{ + struct rb_node **link = &tree->rb_root.rb_node; + struct rb_node *parent = NULL; + bool leftmost = true; + + while (*link) { + parent = *link; + if (less(node, parent)) { + link = &parent->rb_left; + } else { + link = &parent->rb_right; + leftmost = false; + } + } + + rb_link_node(node, parent, link); + rb_insert_color_cached(node, tree, leftmost); + + return leftmost ? node : NULL; +} +#endif + +#endif From eb9130b48bb1c05c920ba0c2c65ffbd2763d4cba Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 18 Feb 2023 16:19:33 +0800 Subject: [PATCH 0929/2653] drm/amdkcl:wrap code under macro HAVE_AMDKCL_HMM_MIRROR_ENABLED It's caused by e43a06a5ef73e1329861ad3a70c490d3eb6e072b "drm/amdgpu: Add notifier lock for KFD userptrs" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 15 ++++-- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 47 ++++++++++++------- 2 files changed, 42 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index bbeac961f7381..86428884867f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -72,7 +72,11 @@ struct kgd_mem { struct amdgpu_bo *bo; struct kfd_ipc_obj *ipc_obj; struct dma_buf *dmabuf; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED struct hmm_range *range; +#else + struct page **user_pages; +#endif struct list_head attachments; /* protected by amdkfd_process_info.lock */ struct list_head validate_list; @@ -84,9 +88,6 @@ struct kgd_mem { uint32_t invalid; struct amdkfd_process_info *process_info; -#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED - struct page **user_pages; -#endif struct amdgpu_sync sync; @@ -200,8 +201,12 @@ int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data); bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm); struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f); void amdgpu_amdkfd_remove_all_eviction_fences(struct amdgpu_bo *bo); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, unsigned long cur_seq, struct kgd_mem *mem); +#else +int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm); +#endif int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, uint32_t domain, struct dma_fence *fence); @@ -224,8 +229,12 @@ void amdgpu_amdkfd_remove_all_eviction_fences(struct amdgpu_bo *bo) } static inline +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, unsigned long cur_seq, struct kgd_mem *mem) +#else +int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm) +#endif { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 9d0b4e8964214..15d175883e121 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1978,21 +1978,21 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( /* Cleanup user pages and MMU notifiers */ if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) { amdgpu_hmm_unregister(mem->bo); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mutex_lock(&process_info->notifier_lock); amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range); mutex_unlock(&process_info->notifier_lock); - } - -#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED - /* Free user pages if necessary */ - if (mem->user_pages) { - pr_debug("%s: Freeing user_pages array\n", __func__); - if (mem->user_pages[0]) - release_pages(mem->user_pages, +#else + /* Free user pages if necessary */ + if (mem->user_pages) { + pr_debug("%s: Freeing user_pages array\n", __func__); + if (mem->user_pages[0]) + release_pages(mem->user_pages, mem->bo->tbo.ttm->num_pages); - kvfree(mem->user_pages); - } + kvfree(mem->user_pages); + } #endif + } ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx); if (unlikely(ret)) @@ -2782,9 +2782,16 @@ int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, * restore, where we get updated page addresses. This function only * ensures that GPU access to the BO is stopped. */ +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, unsigned long cur_seq, struct kgd_mem *mem) { + struct mm_struct *mm = mni->mm; +#else +int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, + struct mm_struct *mm) +{ +#endif struct amdkfd_process_info *process_info = mem->process_info; int r = 0; @@ -2795,12 +2802,14 @@ int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, return 0; mutex_lock(&process_info->notifier_lock); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mmu_interval_set_seq(mni, cur_seq); +#endif mem->invalid++; if (++process_info->evicted_bos == 1) { /* First eviction, stop the queues */ - r = kgd2kfd_quiesce_mm(mni->mm, + r = kgd2kfd_quiesce_mm(mm, KFD_QUEUE_EVICTION_TRIGGER_USERPTR); if (r && r != -ESRCH) @@ -2853,8 +2862,10 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, bo = mem->bo; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range); mem->range = NULL; +#endif /* BO reservations and getting user pages (hmm_range_fault) * must happen outside the notifier lock @@ -3023,7 +3034,7 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) #else /* Copy pages array and validate the BO if we got user pages */ - if (mem->user_pages[0]) { + if (mem->user_pages && mem->user_pages[0]) { amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, mem->user_pages); amdgpu_bo_placement_from_domain(bo, mem->domain); @@ -3035,12 +3046,12 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) } /* Validate succeeded, now the BO owns the pages, free - * our copy of the pointer array. Put this BO back on - * the userptr_valid_list. If we need to revalidate - * it, we need to start from scratch. + * our copy of the pointer array. */ - kvfree(mem->user_pages); - mem->user_pages = NULL; + if (mem->user_pages) { + kvfree(mem->user_pages); + mem->user_pages = NULL; + } #endif /* Update mapping. If the BO was not validated @@ -3089,6 +3100,7 @@ static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_i list_for_each_entry_safe(mem, tmp_mem, &process_info->userptr_inval_list, validate_list) { +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool valid; /* keep mem without hmm range at userptr_inval_list */ @@ -3105,6 +3117,7 @@ static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_i ret = -EAGAIN; continue; } +#endif if (mem->invalid) { WARN(1, "Valid BO is marked invalid"); From 20b26e47f9156c0a87c31419439c342b4a9a011d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 21 Feb 2023 14:41:33 +0800 Subject: [PATCH 0930/2653] drm/amdkcl: wrap the code under macro HAVE_DRM_MODE_CONFIG_FB_BASE It's caused by 7c99616e3fe7f35fe25bf6f5797267da29b4751e "drm: Remove drm_mode_config::fb_base" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 65bf30a84fdd3..7aee5aeeecc91 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -261,7 +261,9 @@ static int amdgpufb_create(struct drm_fb_helper *helper, drm_fb_helper_fill_info(info, &rfbdev->helper, sizes); /* setup aperture base/size for vesafb takeover */ +#ifdef HAVE_DRM_MODE_CONFIG_FB_BASE info->apertures->ranges[0].base = adev_to_drm(adev)->mode_config.fb_base; +#endif info->apertures->ranges[0].size = adev->gmc.aper_size; /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 index add5633e0f26f..4b809aec8cd50 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 @@ -12,7 +12,25 @@ AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED], [ ]) ]) +dnl # +dnl # v6.1-rc1-103-g7c99616e3fe7 drm: Remove drm_mode_config::fb_base +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG_FB_BASE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_mode_config *mode_config = NULL; + mode_config->fb_base = 0; + ], [ + AC_DEFINE(HAVE_DRM_MODE_CONFIG_FB_BASE, 1, + [drm_mode_config->fb_base is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG], [ AC_AMDGPU_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED + AC_AMDGPU_DRM_MODE_CONFIG_FB_BASE ]) From 3ab40be83aa55e6d4829dcbf2c09ce8f14d4ef9c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 21 Feb 2023 23:31:30 +0800 Subject: [PATCH 0931/2653] drm/amdkcl: update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2e14b125d76e1..07ebdbb9ea0d3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -23,6 +23,9 @@ /* acpi_video_register_backlight() is available */ #define HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT 1 +/* acpi_video_report_nolcd() is available */ +#define HAVE_ACPI_VIDEO_REPORT_NOLCD 1 + /* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ #define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 @@ -597,12 +600,15 @@ #define HAVE_DRM_ENCODER_FIND_VALID_WITH_FILE 1 /* drm_fbdev_generic_setup() is available */ -#define HAVE_DRM_FBDEV_GENERIC_SETUP 1 +/* #undef HAVE_DRM_FBDEV_GENERIC_SETUP */ /* drm_fb_helper_single_add_all_connectors() && drm_fb_helper_remove_one_connector() are symbol */ /* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ +/* drm_fb_helper_alloc_info() is available */ +#define HAVE_DRM_FB_HELPER_ALLOC_INFO 1 + /* drm_fb_helper_fill_info() is available */ #define HAVE_DRM_FB_HELPER_FILL_INFO 1 @@ -618,6 +624,9 @@ /* drm_fb_helper_set_suspend_unlocked() is available */ #define HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED 1 +/* drm_fb_helper_unregister_info() is available */ +#define HAVE_DRM_FB_HELPER_UNREGISTER_INFO 1 + /* drm_firmware_drivers_only() is available */ #define HAVE_DRM_FIRMWARE_DRIVERS_ONLY 1 @@ -702,6 +711,9 @@ /* drm_mode_config->dp_subconnector_property is available */ #define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 +/* drm_mode_config->fb_base is available */ +/* #undef HAVE_DRM_MODE_CONFIG_FB_BASE */ + /* drm_mode_config->fb_modifiers_not_supported is available */ #define HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED 1 @@ -1108,6 +1120,12 @@ /* pxm_to_node() is available */ #define HAVE_PXM_TO_NODE 1 +/* rb_add_cached is available */ +#define HAVE_RB_ADD_CACHED 1 + +/* struct rb_root_cached is available */ +#define HAVE_RB_ROOT_CACHED 1 + /* whether register_shrinker(x, x) is available */ #define HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS 1 @@ -1383,7 +1401,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 5.19.0" +#define PACKAGE_STRING "amdgpu-dkms 6.1.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1392,7 +1410,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "5.19.0" +#define PACKAGE_VERSION "6.1.0" #include "config-amd-chips.h" From dedc7a350c2398ebcd75baf41c5e1b823293768d Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 6 Feb 2023 14:52:54 +0800 Subject: [PATCH 0932/2653] drm/amdkcl: kcl-cleanup HAVE___PRINT_ARRAY This reverts commit 0932cfd7e5a93dfe3b19df0e4cfd88b47c236491. and ecd11581e729557a93f588eb1ad76b23100cec04 Change-Id: If5edf6583655ad7f59e528bbd1e3e0e688f3b35a Signed-off-by: Ma Jun Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c | 56 ------------------- drivers/gpu/drm/amd/backport/backport.h | 1 - drivers/gpu/drm/amd/dkms/config/config.h | 3 - .../drm/amd/dkms/m4/ftrace_print_array_seq.m4 | 23 -------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/kcl_ftrace.h | 18 ------ 7 files changed, 1 insertion(+), 103 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/ftrace_print_array_seq.m4 delete mode 100644 include/kcl/kcl_ftrace.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 8e3650b52cfc0..db840d6c94c4a 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -10,7 +10,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ - kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ + kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c b/drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c deleted file mode 100644 index 115bdc26363a5..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * trace_output.c - * - * Copyright (C) 2008 Red Hat Inc, Steven Rostedt - * - */ -#include - -/* Copied from v3.19-rc1-6-g6ea22486ba46 kernel/trace/trace_output.c */ -#if !defined(HAVE___PRINT_ARRAY) -const char * -ftrace_print_array_seq(struct trace_seq *p, const void *buf, int count, - size_t el_size) -{ - const char *ret = trace_seq_buffer_ptr(p); - const char *prefix = ""; - void *ptr = (void *)buf; - size_t buf_len = count * el_size; - - trace_seq_putc(p, '{'); - - while (ptr < buf + buf_len) { - switch (el_size) { - case 1: - trace_seq_printf(p, "%s0x%x", prefix, - *(u8 *)ptr); - break; - case 2: - trace_seq_printf(p, "%s0x%x", prefix, - *(u16 *)ptr); - break; - case 4: - trace_seq_printf(p, "%s0x%x", prefix, - *(u32 *)ptr); - break; - case 8: - trace_seq_printf(p, "%s0x%llx", prefix, - *(u64 *)ptr); - break; - default: - trace_seq_printf(p, "BAD SIZE:%zu 0x%x", el_size, - *(u8 *)ptr); - el_size = 1; - } - prefix = ","; - ptr += el_size; - } - - trace_seq_putc(p, '}'); - trace_seq_putc(p, 0); - - return ret; -} -EXPORT_SYMBOL(ftrace_print_array_seq); -#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 29f5ada3bd6b3..aa1fbf2145202 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -60,7 +60,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 07ebdbb9ea0d3..8dc15b3fc56aa 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1373,9 +1373,6 @@ /* __kthread_should_park() is available */ #define HAVE___KTHREAD_SHOULD_PARK 1 -/* __print_array is available */ -#define HAVE___PRINT_ARRAY 1 - /* kobj_type->default_groups is available */ #define HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/ftrace_print_array_seq.m4 b/drivers/gpu/drm/amd/dkms/m4/ftrace_print_array_seq.m4 deleted file mode 100644 index ecc2aa76f18b1..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/ftrace_print_array_seq.m4 +++ /dev/null @@ -1,23 +0,0 @@ -dnl # -dnl # commit 0fe7e2764d6f -dnl # add new trace event for page table update -dnl # ftrace_print_array_seq() is exported in v3.19-rc1-6-g6ea22486ba46 -dnl # -AC_DEFUN([AC_AMDGPU___PRINT_ARRAY], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([ftrace_print_array_seq], [kernel/trace/trace_output.c], [ - AC_DEFINE(HAVE___PRINT_ARRAY, 1, [__print_array is available]) - ], [ - dnl # - dnl # 645df987f7c - dnl # trace_print_array_seq() is exported in v4.1-rc3-8-g645df987f7c1 - dnl # - AC_KERNEL_CHECK_SYMBOL_EXPORT( - [trace_print_array_seq], - [kernel/trace/trace_output.c],[ - AC_DEFINE(HAVE___PRINT_ARRAY, 1, - [__print_array is available]) - ]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6632d9f6d97d1..10d995c6985a7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -126,7 +126,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_JIFFIES64_TO_MSECS - AC_AMDGPU___PRINT_ARRAY AC_AMDGPU_ACPI_PUT_TABLE AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS AC_AMDGPU_DRM_FORMAT_INFO diff --git a/include/kcl/kcl_ftrace.h b/include/kcl/kcl_ftrace.h deleted file mode 100644 index ae106eff452b0..0000000000000 --- a/include/kcl/kcl_ftrace.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef AMDKCL_FTRACE_H -#define AMDKCL_FTRACE_H - -#include -/* Copied from v3.19-rc1-6-g6ea22486ba46 include/trace/ftrace.h */ -#if !defined(HAVE___PRINT_ARRAY) -extern const char * ftrace_print_array_seq(struct trace_seq *p, const void *buf, int count, - size_t el_size); -#define __print_array(array, count, el_size) \ - ({ \ - BUILD_BUG_ON(el_size != 1 && el_size != 2 && \ - el_size != 4 && el_size != 8); \ - ftrace_print_array_seq(p, array, count, el_size); \ - }) -#endif - -#endif From 1de1b9e4d5007b4bdf30c8fb4e13e414994a3d32 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 6 Feb 2023 17:10:56 +0800 Subject: [PATCH 0933/2653] drm/amdkcl: kcl-cleanup HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET* cleanup the HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET and HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX Change-Id: I8e7c105e57c42e4f03c42daac53d1eec132cbfe5 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 - drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 211 ------------------ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 11 - drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 - drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 - drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 - drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 - drivers/gpu/drm/amd/dkms/config/config.h | 6 - .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 35 --- 9 files changed, 283 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 7519251a91a76..0b3a6a4b2fa1c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -480,11 +480,7 @@ struct amdgpu_sa_manager { */ struct amdgpu_flip_work { -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET struct delayed_work flip_work; -#else - struct work_struct flip_work; -#endif struct work_struct unpin_work; struct amdgpu_device *adev; int crtc_id; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index beb9cfc6a7af7..9d968c2df5a7d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -104,11 +104,7 @@ static void amdgpu_display_flip_callback(struct dma_fence *f, container_of(cb, struct amdgpu_flip_work, cb); dma_fence_put(f); -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET schedule_work(&work->flip_work.work); -#else - schedule_work(&work->flip_work); -#endif } static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, @@ -129,87 +125,6 @@ static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, return false; } -#if !defined(HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET) -static void amdgpu_flip_work_func(struct work_struct *__work) -{ - struct amdgpu_flip_work *work = - container_of(__work, struct amdgpu_flip_work, flip_work); - struct amdgpu_device *adev = work->adev; - struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id]; - - struct drm_crtc *crtc = &amdgpuCrtc->base; - unsigned long flags; - unsigned i, repcnt = 4; - int vpos, hpos, stat, min_udelay = 0; - struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; - - - for (i = 0; i < work->shared_count; ++i) - if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) - return; - - /* We borrow the event spin lock for protecting flip_status */ - spin_lock_irqsave(&crtc->dev->event_lock, flags); - - /* If this happens to execute within the "virtually extended" vblank - * interval before the start of the real vblank interval then it needs - * to delay programming the mmio flip until the real vblank is entered. - * This prevents completing a flip too early due to the way we fudge - * our vblank counter and vblank timestamps in order to work around the - * problem that the hw fires vblank interrupts before actual start of - * vblank (when line buffer refilling is done for a frame). It - * complements the fudging logic in amdgpu_display_get_crtc_scanoutpos() for - * timestamping and amdgpu_get_vblank_counter_kms() for vblank counts. - * - * In practice this won't execute very often unless on very fast - * machines because the time window for this to happen is very small. - */ - while (amdgpuCrtc->enabled && --repcnt) { - /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank - * start in hpos, and to the "fudged earlier" vblank start in - * vpos. - */ - stat = amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, - GET_DISTANCE_TO_VBLANKSTART, - &vpos, &hpos, NULL, NULL, - &crtc->hwmode); - - if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != - (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) || - !(vpos >= 0 && hpos <= 0)) - break; - - /* Sleep at least until estimated real start of hw vblank */ - min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); - if (min_udelay > vblank->framedur_ns / 2000) { - /* Don't wait ridiculously long - something is wrong */ - repcnt = 0; - break; - } - spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - usleep_range(min_udelay, 2 * min_udelay); - spin_lock_irqsave(&crtc->dev->event_lock, flags); - } - - if (!repcnt) - DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, " - "framedur %d, linedur %d, stat %d, vpos %d, " - "hpos %d\n", work->crtc_id, min_udelay, - vblank->framedur_ns / 1000, - vblank->linedur_ns / 1000, stat, vpos, hpos); - - /* Do the flip (mmio) */ - adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); - - /* Set the flip status */ - amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; - spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - - - DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", - amdgpuCrtc->crtc_id, amdgpuCrtc, work); -} -#else static void amdgpu_display_flip_work_func(struct work_struct *__work) { struct delayed_work *delayed_work = @@ -259,7 +174,6 @@ static void amdgpu_display_flip_work_func(struct work_struct *__work) amdgpu_crtc->crtc_id, amdgpu_crtc, work); } -#endif /* * Handle unpin events outside the interrupt handler proper. @@ -283,16 +197,11 @@ static void amdgpu_display_unpin_work_func(struct work_struct *__work) kfree(work); } -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX uint32_t page_flip_flags, uint32_t target, struct drm_modeset_acquire_ctx *ctx) -#else - uint32_t page_flip_flags, uint32_t target) -#endif { struct drm_device *dev = crtc->dev; struct amdgpu_device *adev = drm_to_adev(dev); @@ -407,127 +316,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, return r; } -#else -int amdgpu_crtc_page_flip(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_pending_vblank_event *event, - uint32_t page_flip_flags) -{ - struct drm_device *dev = crtc->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - struct amdgpu_framebuffer *old_amdgpu_fb; - struct amdgpu_framebuffer *new_amdgpu_fb; - struct drm_gem_object *obj; - struct amdgpu_flip_work *work; - struct amdgpu_bo *new_abo; - unsigned long flags; - u64 tiling_flags; - u64 base; - int i, r; - - work = kzalloc(sizeof *work, GFP_KERNEL); - if (work == NULL) - return -ENOMEM; - - INIT_WORK(&work->flip_work, amdgpu_flip_work_func); - INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); - - work->event = event; - work->adev = adev; - work->crtc_id = amdgpu_crtc->crtc_id; - work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; - - /* schedule unpin of the old buffer */ - old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); - obj = old_amdgpu_fb->obj; - - /* take a reference to the old object */ - work->old_abo = gem_to_amdgpu_bo(obj); - amdgpu_bo_ref(work->old_abo); - - new_amdgpu_fb = to_amdgpu_framebuffer(fb); - obj = new_amdgpu_fb->obj; - new_abo = gem_to_amdgpu_bo(obj); - /* pin the new buffer */ - r = amdgpu_bo_reserve(new_abo, false); - if (unlikely(r != 0)) { - DRM_ERROR("failed to reserve new abo buffer before flip\n"); - goto cleanup; - } - - r = amdgpu_bo_pin(new_abo, AMDGPU_GEM_DOMAIN_VRAM); - if (unlikely(r != 0)) { - r = -EINVAL; - DRM_ERROR("failed to pin new abo buffer before flip\n"); - goto unreserve; - } - - r = dma_resv_get_fences(amdkcl_ttm_resvp(&new_abo->tbo), DMA_RESV_USAGE_WRITE, - &work->shared_count, - &work->shared); - if (unlikely(r != 0)) { - DRM_ERROR("failed to get fences for buffer\n"); - goto unpin; - } - - amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); - amdgpu_bo_unreserve(new_abo); - - work->base = base; - - r = drm_crtc_vblank_get(crtc); - if (r) { - DRM_ERROR("failed to get vblank before flip\n"); - goto pflip_cleanup; - } - - /* we borrow the event spin lock for protecting flip_wrok */ - spin_lock_irqsave(&crtc->dev->event_lock, flags); - if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { - DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); - spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - r = -EBUSY; - goto vblank_cleanup; - } - - amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; - amdgpu_crtc->pflip_works = work; - - - DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", - amdgpu_crtc->crtc_id, amdgpu_crtc, work); - /* update crtc fb */ - crtc->primary->fb = fb; - spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - amdgpu_flip_work_func(&work->flip_work); - return 0; - -vblank_cleanup: - drm_crtc_vblank_put(crtc); - -pflip_cleanup: - if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { - DRM_ERROR("failed to reserve new abo in error path\n"); - goto cleanup; - } -unpin: - amdgpu_bo_unpin(new_abo); - -unreserve: - amdgpu_bo_unreserve(new_abo); - -cleanup: - amdgpu_bo_unref(&work->old_abo); - for (i = 0; i < work->shared_count; ++i) - fence_put(work->shared[i]); - kfree(work->shared); - kfree(work); - - return r; -} -#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX int amdgpu_display_crtc_set_config(struct drm_mode_set *set, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index e5906df41a0ae..5c1b691abec39 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -748,22 +748,11 @@ int amdgpu_display_crtc_set_config(struct drm_mode_set *set, int amdgpu_display_crtc_set_config(struct drm_mode_set *set); #endif -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX uint32_t page_flip_flags, uint32_t target, struct drm_modeset_acquire_ctx *ctx); -#else - uint32_t page_flip_flags, uint32_t target); -#endif -#else -int amdgpu_crtc_page_flip(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_pending_vblank_event *event, - uint32_t page_flip_flags); -#endif extern const struct drm_mode_config_funcs amdgpu_mode_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 278ea8f596d83..6d1be1b834c6f 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2572,11 +2572,7 @@ static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { .gamma_set = dce_v10_0_crtc_gamma_set, .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v10_0_crtc_destroy, -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET .page_flip_target = amdgpu_display_crtc_page_flip_target, -#else - .page_flip = amdgpu_crtc_page_flip, -#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index c9867a927c8ce..ba8e9e181f7d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2656,11 +2656,7 @@ static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { .gamma_set = dce_v11_0_crtc_gamma_set, .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v11_0_crtc_destroy, -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET .page_flip_target = amdgpu_display_crtc_page_flip_target, -#else - .page_flip = amdgpu_crtc_page_flip, -#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 11643f7194683..432b8b5290cd1 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2552,11 +2552,7 @@ static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = { .gamma_set = dce_v6_0_crtc_gamma_set, .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v6_0_crtc_destroy, -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET .page_flip_target = amdgpu_display_crtc_page_flip_target, -#else - .page_flip = amdgpu_crtc_page_flip, -#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 255ca61e82990..dc41daf5b582a 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2490,11 +2490,7 @@ static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = { .gamma_set = dce_v8_0_crtc_gamma_set, .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v8_0_crtc_destroy, -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET .page_flip_target = amdgpu_display_crtc_page_flip_target, -#else - .page_flip = amdgpu_crtc_page_flip, -#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8dc15b3fc56aa..82f2bab540ae6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1213,12 +1213,6 @@ /* drm_crtc_funcs->{get,verify}_crc_sources() is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES 1 -/* drm_crtc_funcs->page_flip_target() is available */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET 1 - -/* drm_crtc_funcs->page_flip_target() wants ctx parameter */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX 1 - /* drm_crtc_funcs->set_config() wants ctx parameter */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 41d85b15ac85f..a50e4f519bafd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -39,40 +39,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG], [ ]) ]) -dnl # -dnl # v4.11-rc3-945-g41292b1fa13a -dnl # drm: Add acquire ctx parameter to ->page_flip(_target) -dnl # -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_crtc_funcs *funcs = NULL; - funcs->page_flip_target(NULL, NULL, NULL, 0, 0, NULL); - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX, 1, - [drm_crtc_funcs->page_flip_target() wants ctx parameter]) - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET, 1, - [drm_crtc_funcs->page_flip_target() is available]) - ], [ - dnl # - dnl # v4.8-rc1-112-gc229bfbbd04a - dnl # drm: Add page_flip_target CRTC hook v2 - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_crtc_funcs *funcs = NULL; - funcs->page_flip_target(NULL, NULL, NULL, 0, 0); - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET, 1, - [drm_crtc_funcs->page_flip_target() is available]) - ]) - ]) - ]) -]) - dnl # dnl # commit v4.10-rc5-1070-g84e354839b15 dnl # drm: add vblank hooks to struct drm_crtc_funcs @@ -194,7 +160,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG - AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER From 7cc9c4396cdecca2c233c7dec07d6c974da7e57f Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 7 Feb 2023 10:03:49 +0800 Subject: [PATCH 0934/2653] drm/amdkcl: kcl-cleanup HAVE_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER Revert "drm/amdkcl: Check if drm_crtc_funcs->late_register() is defined" This reverts commit d3b4a52d2f8394b6d8e309e99a0cda2c7a8de651. Change-Id: I9d026fa4c039e635b2d55b89a895abf996592d73 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 4 ---- drivers/gpu/drm/amd/dkms/config/config.h | 9 --------- .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 19 ------------------- 3 files changed, 32 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 8bb58a8a860fb..633d6192bdac2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -464,7 +464,6 @@ static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc) } #ifdef CONFIG_DEBUG_FS -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) { crtc_debugfs_init(crtc); @@ -472,7 +471,6 @@ static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) return 0; } #endif -#endif #ifdef AMD_PRIVATE_COLOR /** @@ -563,10 +561,8 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, #endif #if defined(CONFIG_DEBUG_FS) -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER .late_register = amdgpu_dm_crtc_late_register, #endif -#endif #ifdef AMD_PRIVATE_COLOR .atomic_set_property = amdgpu_dm_atomic_crtc_set_property, .atomic_get_property = amdgpu_dm_atomic_crtc_get_property, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 82f2bab540ae6..0ad029e6f6e51 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1216,15 +1216,6 @@ /* drm_crtc_funcs->set_config() wants ctx parameter */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX 1 -/* drm_crtc_funcs->late_register() is available */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER 1 - -/* crtc->funcs->set_crc_source() is available */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CRC_SOURCE 1 - -/* crtc->funcs->set_crc_source() wants 2 args */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CRC_SOURCE_2ARGS 1 - /* struct drm_crtc_state->async_flip is available */ #define HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index a50e4f519bafd..a51f0225b4ad1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -137,24 +137,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL], [ ]) ]) -dnl # -dnl # commit v4.8-rc1~62-79190ea26 -dnl # drm: Add callbacks for late registering -dnl # -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_crtc_funcs *crtc_funcs = NULL; - crtc_funcs->late_register(NULL); - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER, 1, [ - drm_crtc_funcs->late_register() is available]) - ]) - ]) -]) - AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK @@ -162,5 +144,4 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL - AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER ]) From 00f589b58f1f6ee06a8af2182bf48bd4cda20d8d Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 7 Feb 2023 10:26:52 +0800 Subject: [PATCH 0935/2653] drm/amdkcl: kcl-cleanup HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS/6ARGS Revert "drm/amdkcl: test drm_crtc_funcs->gamma_set" This reverts commit 4953b2eebbb829ceb89fd09b9edf67feae804a9d. Change-Id: Ie40ae7f3b4608af54680497403c1c12befae1143 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 21 -------- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 21 -------- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 21 -------- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 21 -------- drivers/gpu/drm/amd/dkms/config/config.h | 6 --- .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 48 ------------------- 6 files changed, 138 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 6d1be1b834c6f..c9debcc3dc0cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2528,12 +2528,6 @@ static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) } } -/* - * TODO: drm_fb_helper_setcmap() prev commit v4.12-rc7-1385-g964c60063bff - * ("drm/fb-helper: separate the fb_setcmap helper into atomic and legacy paths") - * don't work as expected. - */ -#if defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS) static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, uint32_t size, struct drm_modeset_acquire_ctx *ctx) @@ -2542,21 +2536,6 @@ static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, return 0; } -#elif defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS) -static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t size) -{ - dce_v10_0_crtc_load_lut(crtc); - - return 0; -} -#else -static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t start, uint32_t size) -{ - dce_v10_0_crtc_load_lut(crtc); -} -#endif static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index ba8e9e181f7d0..521da0ed73f6e 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2612,12 +2612,6 @@ static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) } } -/* - * TODO: drm_fb_helper_setcmap() prev commit v4.12-rc7-1385-g964c60063bff - * ("drm/fb-helper: separate the fb_setcmap helper into atomic and legacy paths") - * don't work as expected. - */ -#if defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS) static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, uint32_t size, struct drm_modeset_acquire_ctx *ctx) @@ -2626,21 +2620,6 @@ static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, return 0; } -#elif defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS) -static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t size) -{ - dce_v11_0_crtc_load_lut(crtc); - - return 0; -} -#else -static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t start, uint32_t size) -{ - dce_v11_0_crtc_load_lut(crtc); -} -#endif static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 432b8b5290cd1..89e25807fa9ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2508,12 +2508,6 @@ static void dce_v6_0_cursor_reset(struct drm_crtc *crtc) } } -/* - * TODO: drm_fb_helper_setcmap() prev commit v4.12-rc7-1385-g964c60063bff - * ("drm/fb-helper: separate the fb_setcmap helper into atomic and legacy paths") - * don't work as expected. - */ -#if defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS) static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, uint32_t size, struct drm_modeset_acquire_ctx *ctx) @@ -2522,21 +2516,6 @@ static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, return 0; } -#elif defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS) -static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t size) -{ - dce_v6_0_crtc_load_lut(crtc); - - return 0; -} -#else -static void dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t start, uint32_t size) -{ - dce_v6_0_crtc_load_lut(crtc); -} -#endif static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index dc41daf5b582a..56a197182e537 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2446,12 +2446,6 @@ static void dce_v8_0_cursor_reset(struct drm_crtc *crtc) } } -/* - * TODO: drm_fb_helper_setcmap() prev commit v4.12-rc7-1385-g964c60063bff - * ("drm/fb-helper: separate the fb_setcmap helper into atomic and legacy paths") - * don't work as expected. - */ -#if defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS) static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, uint32_t size, struct drm_modeset_acquire_ctx *ctx) @@ -2460,21 +2454,6 @@ static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, return 0; } -#elif defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS) -static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t size) -{ - dce_v8_0_crtc_load_lut(crtc); - - return 0; -} -#else -static void dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t start, uint32_t size) -{ - dce_v8_0_crtc_load_lut(crtc); -} -#endif static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0ad029e6f6e51..955a5f9c9a17d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1198,12 +1198,6 @@ /* drm_crtc_funcs->enable_vblank() is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK 1 -/* crtc->funcs->gamma_set() wants 5 args */ -/* #undef HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS */ - -/* crtc->funcs->gamma_set() wants 6 args */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS 1 - /* HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index a51f0225b4ad1..2e19306272912 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -78,53 +78,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES], [ ]) ]) -dnl # -dnl # v4.11-rc5-1392-g6d124ff84533 drm: Add acquire ctx to ->gamma_set hook -dnl # int (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, -dnl # - uint32_t size); -dnl # + uint32_t size, -dnl # + struct drm_modeset_acquire_ctx *ctx); -dnl # v4.7-rc1-260-g7ea772838782 drm/core: Change declaration for gamma_set. -dnl # - void (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, -dnl # - uint32_t start, uint32_t size); -dnl # + int (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, -dnl # + uint32_t size); -dnl # v2.6.35-260-g7203425a943e drm: expand gamma_set -dnl # void (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, -dnl # - uint32_t size); -dnl # + uint32_t start, uint32_t size); -dnl # v2.6.28-8-gf453ba046074 DRM: add mode setting support -dnl # + void (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, -dnl # + uint32_t size); -dnl # -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_crtc *crtc = NULL; - int ret; - - ret = crtc->funcs->gamma_set(NULL, NULL, NULL, NULL, 0, NULL); - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS, 1, - [crtc->funcs->gamma_set() wants 6 args]) - ], [ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_crtc *crtc = NULL; - int ret; - - ret = crtc->funcs->gamma_set(NULL, NULL, NULL, NULL, 0); - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS, 1, - [crtc->funcs->gamma_set() wants 5 args]) - ]) - ]) - ]) -]) - dnl # dnl # v5.10-1961-g6ca2ab8086af drm: automatic legacy gamma support dnl # @@ -142,6 +95,5 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG - AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL ]) From dad87b280a9c062c60361b8db058dcff7b11b758 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 7 Feb 2023 15:04:42 +0800 Subject: [PATCH 0936/2653] drm/amdkcl: kcl-cleanup HAVE_LINUX_DMA_FENCE_H cleanup the HAVE_LINUX_DMA_FENCE_H and refactor related code Change-Id: I72ea2ff319cb741ff236dad4b8c30e770291807c Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 4 - drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c | 149 ------------------ drivers/gpu/drm/amd/dkms/config/config.h | 3 - .../gpu/drm/amd/dkms/m4/dma-fence-headers.m4 | 18 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 +- include/kcl/header/linux/dma-fence-array.h | 6 +- include/kcl/header/linux/dma-fence.h | 11 -- include/kcl/kcl_dma_fence.h | 4 +- include/kcl/kcl_dma_fence_chain.h | 4 - include/kcl/kcl_fence.h | 44 ------ include/kcl/kcl_fence_array.h | 93 ----------- 13 files changed, 10 insertions(+), 335 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 delete mode 100644 include/kcl/header/linux/dma-fence.h delete mode 100644 include/kcl/kcl_fence_array.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index db840d6c94c4a..0accf6c787b2b 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -7,7 +7,7 @@ amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o kcl_seq_file.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ - kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ + kcl_fence.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index 1969d6e0f289c..6b962278954e6 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -238,11 +238,7 @@ EXPORT_SYMBOL(_kcl_fence_enable_signaling); */ void amdkcl_fence_init(void) { -#if defined(HAVE_LINUX_DMA_FENCE_H) _kcl_fence_default_wait_cb = amdkcl_fp_setup("dma_fence_default_wait_cb", NULL); -#else - _kcl_fence_default_wait_cb = amdkcl_fp_setup("fence_default_wait_cb", NULL); -#endif } #if !defined(HAVE_DMA_FENCE_DESCRIBE) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c deleted file mode 100644 index d42a986ecfe1d..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * fence-array: aggregate fences to be waited together - * - * Copyright (C) 2016 Collabora Ltd - * Copyright (C) 2016 Advanced Micro Devices, Inc. - * Authors: - * Gustavo Padovan - * Christian König - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include -#include -#include -#include - -#if !defined(HAVE_LINUX_DMA_FENCE_H) && !defined(HAVE_LINUX_FENCE_ARRAY_H) -static void fence_array_cb_func(struct fence *f, struct fence_cb *cb); - -static const char *fence_array_get_driver_name(struct fence *fence) -{ - return "fence_array"; -} - -static const char *fence_array_get_timeline_name(struct fence *fence) -{ - return "unbound"; -} - -static void fence_array_cb_func(struct fence *f, struct fence_cb *cb) -{ - struct fence_array_cb *array_cb = - container_of(cb, struct fence_array_cb, cb); - struct fence_array *array = array_cb->array; - - if (atomic_dec_and_test(&array->num_pending)) - fence_signal(&array->base); - fence_put(&array->base); -} - -static bool fence_array_enable_signaling(struct fence *fence) -{ - struct fence_array *array = to_fence_array(fence); - struct fence_array_cb *cb = (void *)(&array[1]); - unsigned i; - - for (i = 0; i < array->num_fences; ++i) { - cb[i].array = array; - /* - * As we may report that the fence is signaled before all - * callbacks are complete, we need to take an additional - * reference count on the array so that we do not free it too - * early. The core fence handling will only hold the reference - * until we signal the array as complete (but that is now - * insufficient). - */ - fence_get(&array->base); - if (fence_add_callback(array->fences[i], &cb[i].cb, - fence_array_cb_func)) { - fence_put(&array->base); - if (atomic_dec_and_test(&array->num_pending)) - return false; - } - } - - return true; -} - -static bool fence_array_signaled(struct fence *fence) -{ - struct fence_array *array = to_fence_array(fence); - - return atomic_read(&array->num_pending) <= 0; -} - -static void fence_array_release(struct fence *fence) -{ - struct fence_array *array = to_fence_array(fence); - unsigned i; - - for (i = 0; i < array->num_fences; ++i) - fence_put(array->fences[i]); - - kfree(array->fences); - fence_free(fence); -} - -const struct fence_ops fence_array_ops = { - .get_driver_name = fence_array_get_driver_name, - .get_timeline_name = fence_array_get_timeline_name, - .enable_signaling = fence_array_enable_signaling, - .signaled = fence_array_signaled, - .wait = _kcl_fence_default_wait, - .release = fence_array_release, -}; - -/** - * fence_array_create - Create a custom fence array - * @num_fences: [in] number of fences to add in the array - * @fences: [in] array containing the fences - * @context: [in] fence context to use - * @seqno: [in] sequence number to use - * @signal_on_any [in] signal on any fence in the array - * - * Allocate a fence_array object and initialize the base fence with fence_init(). - * In case of error it returns NULL. - * - * The caller should allocte the fences array with num_fences size - * and fill it with the fences it wants to add to the object. Ownership of this - * array is take and fence_put() is used on each fence on release. - * - * If @signal_on_any is true the fence array signals if any fence in the array - * signals, otherwise it signals when all fences in the array signal. - */ -struct fence_array *fence_array_create(int num_fences, struct fence **fences, - u64 context, unsigned seqno, - bool signal_on_any) -{ - struct fence_array *array; - size_t size = sizeof(*array); - - /* Allocate the callback structures behind the array. */ - size += num_fences * sizeof(struct fence_array_cb); - array = kzalloc(size, GFP_KERNEL); - if (!array) - return NULL; - - spin_lock_init(&array->lock); - fence_init(&array->base, &fence_array_ops, &array->lock, - context, seqno); - - array->num_fences = num_fences; - atomic_set(&array->num_pending, signal_on_any ? 1 : num_fences); - array->fences = fences; - - return array; -} -EXPORT_SYMBOL(fence_array_create); - -#endif /* !defined(HAVE_LINUX_DMA_FENCE_H) && !defined(HAVE_LINUX_FENCE_ARRAY_H) */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 955a5f9c9a17d..77b05f13f101a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -961,9 +961,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_FENCE_CHAIN_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_DMA_FENCE_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_MAP_OPS_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 deleted file mode 100644 index 843491bfe3aef..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 +++ /dev/null @@ -1,18 +0,0 @@ -dnl # -dnl # commit f54d1867005c3323f5d8ad83eed823e84226c429 -dnl # dma-buf: Rename struct fence to dma_fence -dnl # -AC_DEFUN([AC_AMDGPU_DMA_FENCE_HEADERS], [ - AS_IF([test $HAVE_LINUX_DMA_FENCE_H], [ - AC_KERNEL_DO_BACKGROUND([ - ]) - ], [ - dnl # - dnl # commit b3dfbdf261e076a997f812323edfdba84ba80256 - dnl # dma-buf/fence: add fence_array fences v6 - dnl # - AC_KERNEL_CHECK_HEADERS([linux/fence-array.h]) - AC_KERNEL_DO_BACKGROUND([ - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 10d995c6985a7..f671cc1eb531c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -51,7 +51,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_SCHED_SET_FIFO_LOW - AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_SG_TT_INIT AC_AMDGPU_TTM_BUFFER_OBJECT diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 0b21b17421ef2..c90bc2c7d2fd7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -38,10 +38,10 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ AC_KERNEL_CHECK_HEADERS([linux/compiler_attributes.h]) dnl # - dnl # v4.9-rc2-299-gf54d1867005c - dnl # dma-buf: Rename struct fence to dma_fence + dnl # commit b3dfbdf261e076a997f812323edfdba84ba80256 + dnl # dma-buf/fence: add fence_array fences v6 dnl # - AC_KERNEL_CHECK_HEADERS([linux/dma-fence.h]) + AC_KERNEL_CHECK_HEADERS([linux/fence-array.h]) dnl # dnl # v5.3-rc1-449-g52791eeec1d9 diff --git a/include/kcl/header/linux/dma-fence-array.h b/include/kcl/header/linux/dma-fence-array.h index 49bb1fcd2a798..bc3d2e4bbaca2 100644 --- a/include/kcl/header/linux/dma-fence-array.h +++ b/include/kcl/header/linux/dma-fence-array.h @@ -2,10 +2,10 @@ #ifndef _KCL_HEADER__LINUX_DMA_FENCE_ARRAY_H_H_ #define _KCL_HEADER__LINUX_DMA_FENCE_ARRAY_H_H_ -#if defined(HAVE_LINUX_DMA_FENCE_H) +#if !defined(HAVE_LINUX_FENCE_ARRAY_H) #include_next -#elif defined(HAVE_LINUX_FENCE_ARRAY_H) -#include +#else +#include_next #endif #endif diff --git a/include/kcl/header/linux/dma-fence.h b/include/kcl/header/linux/dma-fence.h deleted file mode 100644 index d4bb6177302a3..0000000000000 --- a/include/kcl/header/linux/dma-fence.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER__LINUX_DMA_FENCE_H_H_ -#define _KCL_HEADER__LINUX_DMA_FENCE_H_H_ - -#if defined(HAVE_LINUX_DMA_FENCE_H) -#include_next -#else -#include -#endif - -#endif diff --git a/include/kcl/kcl_dma_fence.h b/include/kcl/kcl_dma_fence.h index cbf594a40d4de..20a014352f967 100644 --- a/include/kcl/kcl_dma_fence.h +++ b/include/kcl/kcl_dma_fence.h @@ -14,9 +14,11 @@ #define AMDKCL_DMA_FENCE_H #ifndef HAVE_DMA_FENCE_IS_CONTAINER -#include #include +#if !defined(HAVE_LINUX_FENCE_ARRAY_H) +#include +#endif /** * dma_fence_is_chain - check if a fence is from the chain subclass * @fence: the fence to test diff --git a/include/kcl/kcl_dma_fence_chain.h b/include/kcl/kcl_dma_fence_chain.h index b7b66a3b93c90..97900481479c5 100644 --- a/include/kcl/kcl_dma_fence_chain.h +++ b/include/kcl/kcl_dma_fence_chain.h @@ -14,11 +14,7 @@ #endif #if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) -#ifdef HAVE_LINUX_DMA_FENCE_H #include -#else -#include -#endif #include #include diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index e8adf7bef1c57..a4a94e8a03e54 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -15,36 +15,6 @@ #include #include #include -#include - -#if !defined(HAVE_LINUX_DMA_FENCE_H) -#define dma_fence_cb fence_cb -#define dma_fence_ops fence_ops -#define dma_fence_array fence_array -#define dma_fence fence -#define dma_fence_init fence_init -#define dma_fence_context_alloc fence_context_alloc -#define DMA_FENCE_TRACE FENCE_TRACE -#define DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT FENCE_FLAG_ENABLE_SIGNAL_BIT -#define DMA_FENCE_FLAG_SIGNALED_BIT FENCE_FLAG_SIGNALED_BIT -#define DMA_FENCE_FLAG_USER_BITS FENCE_FLAG_USER_BITS -#define dma_fence_wait fence_wait -#define dma_fence_get fence_get -#define dma_fence_put fence_put -#define dma_fence_is_signaled fence_is_signaled -#define dma_fence_signal fence_signal -#define dma_fence_signal_locked fence_signal_locked -#define dma_fence_get_rcu fence_get_rcu -#define dma_fence_array_create fence_array_create -#define dma_fence_add_callback fence_add_callback -#define dma_fence_remove_callback fence_remove_callback -#define dma_fence_enable_sw_signaling fence_enable_sw_signaling -#define dma_fence_default_wait fence_default_wait -#define dma_fence_free fence_free -#define dma_fence_get_rcu_safe fence_get_rcu - -#define dma_fence_set_error fence_set_error -#endif #if !defined(HAVE__DMA_FENCE_IS_LATER_2ARGS) @@ -81,20 +51,6 @@ static inline bool __dma_fence_is_later(u64 f1, u64 f2, #endif #endif /* HAVE__DMA_FENCE_IS_LATER_2ARGS */ -/* commit v4.5-rc3-715-gb47bcb93bbf2 - * fall back to HAVE_LINUX_DMA_FENCE_H check directly - * as it's hard to detect the implementation in kernel - */ -#if !defined(HAVE_LINUX_DMA_FENCE_H) -static inline bool dma_fence_is_later(struct dma_fence *f1, struct dma_fence *f2) -{ - if (WARN_ON(f1->context != f2->context)) - return false; - - return (int)(f1->seqno - f2->seqno) > 0; -} -#endif - /* * commit v4.18-rc2-533-g418cc6ca0607 * dma-fence: Allow wait_any_timeout for all fences) diff --git a/include/kcl/kcl_fence_array.h b/include/kcl/kcl_fence_array.h deleted file mode 100644 index 060edd1567fda..0000000000000 --- a/include/kcl/kcl_fence_array.h +++ /dev/null @@ -1,93 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * this file is the copy of include/linux/fence-array.h, don't modify it - * - * fence-array: aggregates fence to be waited together - * - * Copyright (C) 2016 Collabora Ltd - * Copyright (C) 2016 Advanced Micro Devices, Inc. - * Authors: - * Gustavo Padovan - * Christian König - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef AMDKCL_FENCE_ARRAY_H -#define AMDKCL_FENCE_ARRAY_H - -#include - -#if !defined(HAVE_LINUX_DMA_FENCE_H) -#if !defined(HAVE_LINUX_FENCE_ARRAY_H) -#include - -/** - * struct fence_array_cb - callback helper for fence array - * @cb: fence callback structure for signaling - * @array: reference to the parent fence array object - */ -struct fence_array_cb { - struct fence_cb cb; - struct fence_array *array; -}; - -/** - * struct fence_array - fence to represent an array of fences - * @base: fence base class - * @lock: spinlock for fence handling - * @num_fences: number of fences in the array - * @num_pending: fences in the array still pending - * @fences: array of the fences - */ -struct fence_array { - struct fence base; - - spinlock_t lock; - unsigned num_fences; - atomic_t num_pending; - struct fence **fences; -}; - -extern const struct fence_ops fence_array_ops; - -/** - * to_fence_array - cast a fence to a fence_array - * @fence: fence to cast to a fence_array - * - * Returns NULL if the fence is not a fence_array, - * or the fence_array otherwise. - */ -static inline struct fence_array *to_fence_array(struct fence *fence) -{ - if (fence->ops != &fence_array_ops) - return NULL; - - return container_of(fence, struct fence_array, base); -} - -struct fence_array *fence_array_create(int num_fences, struct fence **fences, - u64 context, unsigned seqno, - bool signal_on_any); -/** - * dma_fence_is_array - check if a fence is from the array subclass - * @fence: the fence to test - * - * Return true if it is a dma_fence_array and false otherwise. - */ -static inline bool dma_fence_is_array(struct dma_fence *fence) -{ - return false; -} - -#endif -#endif - -#endif /* __LINUX_FENCE_ARRAY_H */ From eec9d2e062632a10d43407065f3082a10fb335ac Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 7 Feb 2023 11:14:50 +0800 Subject: [PATCH 0937/2653] drm/amdkcl: kcl-cleanup HAVE_STRUCT_DRM_CRTC_DEBUGFS_ENTRY Revert "drm/amdkcl: Check if drm_crtc->debugfs_entry is defined" This reverts commit 015821cc652732fc336dc752dbd2ea6f6acc3ac1. Change-Id: I18b1d0387b2448f3267c105ed87163314ae25568 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 -- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 | 21 ------------------- 4 files changed, 27 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 74fe83820e811..8e7f9a7ad68b5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3803,12 +3803,10 @@ void crtc_debugfs_init(struct drm_crtc *crtc) &crc_win_update_fops); dput(dir); #endif -#ifdef HAVE_STRUCT_DRM_CRTC_DEBUGFS_ENTRY debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry, crtc, &amdgpu_current_bpc_fops); debugfs_create_file("amdgpu_current_colorspace", 0644, crtc->debugfs_entry, crtc, &amdgpu_current_colorspace_fops); -#endif } /* diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 77b05f13f101a..a3478a34d9288 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1213,9 +1213,6 @@ /* struct drm_crtc_state has flag for flip */ #define HAVE_STRUCT_DRM_CRTC_STATE_FLIP_FLAG 1 -/* drm_crtc->debugfs_entry is available */ -#define HAVE_STRUCT_DRM_CRTC_DEBUGFS_ENTRY 1 - /* struct drm_crtc_state->pageflip_flags is available */ /* #undef HAVE_STRUCT_DRM_CRTC_STATE_PAGEFLIP_FLAGS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f671cc1eb531c..7b644fe7683e1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -211,7 +211,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB AC_AMDGPU_BITMAP_TO_ARR32 - AC_AMDGPU_STRUCT_DRM_CRTC AC_AMDGPU_REGISTER_SHRINKER AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 deleted file mode 100644 index 5c02ff4595856..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 +++ /dev/null @@ -1,21 +0,0 @@ -dnl # -dnl # commit v4.10-rc1~154-9edbf1fa6 -dnl # drm: Add API for capturing frame CRCs -dnl # -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_DEBUGFS_ENTRY], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_crtc *test = NULL; - test->debugfs_entry = NULL; - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_DEBUGFS_ENTRY, 1, [ - drm_crtc->debugfs_entry is available]) - ]) - ]) -]) - -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC], [ - AC_AMDGPU_STRUCT_DRM_CRTC_DEBUGFS_ENTRY -]) From 41c18cf34d6dff194d88ba2297cfbd9756aa43a6 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 8 Feb 2023 14:43:23 +0800 Subject: [PATCH 0938/2653] drm/amdkcl: kcl-cleanup HAVE_KTIME_GET_MONO_FAST_NS Revert "drm/amdkcl: add kcl for ktime_get_mono_fast_ns" This reverts commit c92bddf26415a7f42e5d9187cdda3ee0be490317. Change-Id: Ib3634b509369d67268f99057a335cbe9a92d0c76 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 | 16 ---------------- include/kcl/kcl_timekeeping.h | 7 ------- 4 files changed, 27 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a3478a34d9288..4fa2881b001b1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -913,9 +913,6 @@ /* ktime_get_boottime_ns() is available */ #define HAVE_KTIME_GET_BOOTTIME_NS 1 -/* ktime_get_mono_fast_ns is available */ -#define HAVE_KTIME_GET_MONO_FAST_NS 1 - /* ktime_get_ns is available */ #define HAVE_KTIME_GET_NS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7b644fe7683e1..228b27d2ec61b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -38,7 +38,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_KTIME_GET_RAW_NS AC_AMDGPU_KTIME_GET_REAL_SECONDS - AC_AMDGPU_KTIME_GET_FAST_NS AC_AMDGPU_MEMALLOC_NOFS_SAVE AC_AMDGPU_ZONE_MANAGED_PAGES AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 deleted file mode 100644 index 9e7158950fcbb..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit v3.16-rc5-111-g4396e058c52e -dnl # timekeeping: Provide fast and NMI safe access to CLOCK_MONOTONIC -dnl # -AC_DEFUN([AC_AMDGPU_KTIME_GET_FAST_NS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - ktime_get_mono_fast_ns(); - ], [ - AC_DEFINE(HAVE_KTIME_GET_MONO_FAST_NS, 1, - [ktime_get_mono_fast_ns is available]) - ]) - ]) -]) diff --git a/include/kcl/kcl_timekeeping.h b/include/kcl/kcl_timekeeping.h index 60b8c7fec82e5..90e1b1c045a75 100644 --- a/include/kcl/kcl_timekeeping.h +++ b/include/kcl/kcl_timekeeping.h @@ -47,13 +47,6 @@ static inline time64_t ktime_get_real_seconds(void) } #endif -#if !defined(HAVE_KTIME_GET_MONO_FAST_NS) -static inline u64 ktime_get_mono_fast_ns(void) -{ - return ktime_to_ns(ktime_get()); -} -#endif - #ifndef HAVE_JIFFIES64_TO_MSECS extern u64 jiffies64_to_msecs(u64 j); #endif From 56e95af4f6c2852d775187f0025dd59d480de35b Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 8 Feb 2023 14:52:17 +0800 Subject: [PATCH 0939/2653] drm/amdkcl: kcl-cleanup HAVE_KTHREAD_PARK_XX Change-Id: I040d5a11471e6e0d915cbf51f9a0d2eb693f4aa8 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_kthread.c | 50 ------------------- drivers/gpu/drm/amd/amdkcl/main.c | 2 - drivers/gpu/drm/amd/dkms/config/config.h | 3 -- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../gpu/drm/amd/dkms/m4/kthread-park-xx.m4 | 14 ------ include/kcl/backport/kcl_kthread_backport.h | 6 --- include/kcl/kcl_kthread.h | 7 --- 7 files changed, 83 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/kthread-park-xx.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c b/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c index bfc57cb644dc9..df0b9d1c52b25 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c @@ -23,53 +23,3 @@ bool __kcl_kthread_should_park(struct task_struct *k) } EXPORT_SYMBOL(__kcl_kthread_should_park); #endif - -#if !defined(HAVE_KTHREAD_PARK_XX) -bool (*_kcl_kthread_should_park)(void); -EXPORT_SYMBOL(_kcl_kthread_should_park); - -void (*_kcl_kthread_parkme)(void); -EXPORT_SYMBOL(_kcl_kthread_parkme); - -void (*_kcl_kthread_unpark)(struct task_struct *k); -EXPORT_SYMBOL(_kcl_kthread_unpark); - -int (*_kcl_kthread_park)(struct task_struct *k); -EXPORT_SYMBOL(_kcl_kthread_park); - -static bool _kcl_kthread_should_park_stub(void) -{ - pr_warn_once("This kernel version not support API: kthread_should_park!\n"); - return false; -} - -static void _kcl_kthread_parkme_stub(void) -{ - pr_warn_once("This kernel version not support API: kthread_parkme!\n"); -} - -static void _kcl_kthread_unpark_stub(struct task_struct *k) -{ - pr_warn_once("This kernel version not support API: kthread_unpark!\n"); -} - -static int _kcl_kthread_park_stub(struct task_struct *k) -{ - pr_warn_once("This kernel version not support API: kthread_park!\n"); - return 0; -} -#endif - -void amdkcl_kthread_init(void) -{ -#if !defined(HAVE_KTHREAD_PARK_XX) - _kcl_kthread_should_park = amdkcl_fp_setup("kthread_should_park", - _kcl_kthread_should_park_stub); - _kcl_kthread_parkme = amdkcl_fp_setup("kthread_parkme", - _kcl_kthread_parkme_stub); - _kcl_kthread_unpark = amdkcl_fp_setup("kthread_unpark", - _kcl_kthread_unpark_stub); - _kcl_kthread_park = amdkcl_fp_setup("kthread_park", - _kcl_kthread_park_stub); -#endif -} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 3e01ddf3f82a6..58c46b4f04ae5 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -7,7 +7,6 @@ extern void amdkcl_dev_cgroup_init(void); extern void amdkcl_fence_init(void); extern void amdkcl_reservation_init(void); extern void amdkcl_io_init(void); -extern void amdkcl_kthread_init(void); extern void amdkcl_mm_init(void); extern void amdkcl_perf_event_init(void); extern void amdkcl_pci_init(void); @@ -23,7 +22,6 @@ int __init amdkcl_init(void) amdkcl_fence_init(); amdkcl_reservation_init(); amdkcl_io_init(); - amdkcl_kthread_init(); amdkcl_mm_init(); amdkcl_perf_event_init(); amdkcl_pci_init(); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4fa2881b001b1..44575442400d2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -904,9 +904,6 @@ /* ksys_sync_helper() is available */ #define HAVE_KSYS_SYNC_HELPER 1 -/* kthread_{park/unpark/parkme/should_park}() is available */ -#define HAVE_KTHREAD_PARK_XX 1 - /* kthread_{use,unuse}_mm() is available */ #define HAVE_KTHREAD_USE_MM 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 228b27d2ec61b..f5ad3f249279b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -18,7 +18,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS AC_AMDGPU_DEV_PM_SET_DRIVER_FLAGS AC_AMDGPU_COMPAT_PTR_IOCTL - AC_AMDGPU_KTHREAD_PARK_XX AC_AMDGPU___KTHREAD_SHOULD_PARK AC_AMDGPU_LIST_ROTATE_TO_FRONT AC_AMDGPU_LIST_IS_FIRST diff --git a/drivers/gpu/drm/amd/dkms/m4/kthread-park-xx.m4 b/drivers/gpu/drm/amd/dkms/m4/kthread-park-xx.m4 deleted file mode 100644 index 06a8af53dcfe9..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/kthread-park-xx.m4 +++ /dev/null @@ -1,14 +0,0 @@ -dnl # -dnl # introduced commit 2a1d446019f9a5983ec5a335b95e8593fdb6fa2e -dnl # kthread: Implement park/unpark facility -dnl # exported commit 18896451eaeee497ef5c397d76902c6376a8787d -dnl # kthread: export kthread functions -dnl # -AC_DEFUN([AC_AMDGPU_KTHREAD_PARK_XX], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([kthread_parkme kthread_park kthread_unpark kthread_should_park],[kernel/kthread.c],[ - AC_DEFINE(HAVE_KTHREAD_PARK_XX, 1, - [kthread_{park/unpark/parkme/should_park}() is available]) - ]) - ]) -]) diff --git a/include/kcl/backport/kcl_kthread_backport.h b/include/kcl/backport/kcl_kthread_backport.h index 898766aa6e427..60732dc17f10e 100644 --- a/include/kcl/backport/kcl_kthread_backport.h +++ b/include/kcl/backport/kcl_kthread_backport.h @@ -9,10 +9,4 @@ #define __kthread_should_park __kcl_kthread_should_park #endif -#if !defined(HAVE_KTHREAD_PARK_XX) -#define kthread_parkme _kcl_kthread_parkme -#define kthread_unpark _kcl_kthread_unpark -#define kthread_park _kcl_kthread_park -#define kthread_should_park _kcl_kthread_should_park -#endif #endif diff --git a/include/kcl/kcl_kthread.h b/include/kcl/kcl_kthread.h index f9cca65e1ea6c..a4e7fdf6bb12f 100644 --- a/include/kcl/kcl_kthread.h +++ b/include/kcl/kcl_kthread.h @@ -10,13 +10,6 @@ extern bool __kcl_kthread_should_park(struct task_struct *k); #endif -#if !defined(HAVE_KTHREAD_PARK_XX) -extern void (*_kcl_kthread_parkme)(void); -extern void (*_kcl_kthread_unpark)(struct task_struct *k); -extern int (*_kcl_kthread_park)(struct task_struct *k); -extern bool (*_kcl_kthread_should_park)(void); -#endif - /* Copied from v5.7-13665-g9bf5b9eb232b kernel/kthread.c */ #ifndef HAVE_KTHREAD_USE_MM static inline From 11b2de9191e3f47f0a3eb7881341eb0d31830188 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 8 Feb 2023 15:55:49 +0800 Subject: [PATCH 0940/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE Change-Id: Id5feee587dc3623b9c9e800b34885fa2979cf857 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ---- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- 2 files changed, 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 99f7649ea0143..94ddba289768a 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3644,14 +3644,12 @@ static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { .atomic_commit = drm_atomic_helper_commit, }; -#ifdef HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, #ifdef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, #endif }; -#endif #ifdef HAVE_HDR_SINK_METADATA static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) @@ -4690,9 +4688,7 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) adev->mode_info.mode_config_initialized = true; adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; -#ifdef HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; -#endif adev_to_drm(adev)->mode_config.max_width = 16384; adev_to_drm(adev)->mode_config.max_height = 16384; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 44575442400d2..e901d41c41c83 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -720,9 +720,6 @@ /* drm_mode_config_funcs->atomic_state_alloc() is available */ #define HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC 1 -/* drm_mode_config->helper_private is available */ -#define HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE 1 - /* drm_mode_config_helper_{suspend/resume}() is available */ #define HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND 1 From d3ddabbc54caa2b3b1eb60b79151ce4f776795dd Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 9 Feb 2023 17:19:30 +0800 Subject: [PATCH 0941/2653] drm/amdkcl: Fix the dma_resv.seq checking bug Fix the dma_resv->seq checking bug Change-Id: I0ea3efe3d36d1e3996623f5f7fc5de16702516c9 Signed-off-by: Ma Jun Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 98 ++++++++++--------------- 1 file changed, 38 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index 8cf888eb3a6b4..f65379d76636f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -1,78 +1,57 @@ dnl # -dnl # v5.8-rc6-36-gcd29f22019ec dma-buf: Use sequence counter with associated wound/wait mutex -dnl # v5.8-rc6-35-g318ce71f3e3a dma-buf: Remove custom seqcount lockdep class key +dnl # v5.18-rc1-237-g047a1b877ed4 +dnl # dma-buf & drm/amdgpu: remove dma_resv workaround dnl # -AC_DEFUN([AC_AMDGPU_DMA_RESV_SEQ], [ +AC_DEFUN([AC_AMDGPU_DMA_RESV_FENCES], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ #include ], [ - struct dma_resv *obj = NULL; - seqcount_ww_mutex_init(&obj->seq, &obj->lock); + struct dma_resv *resv = NULL; + resv->fences = NULL; ], [ - AC_DEFINE(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T, 1, - [dma_resv->seq is seqcount_ww_mutex_t]) - AC_DEFINE(HAVE_DMA_RESV_SEQ, 1, - [dma_resv->seq is available]) + dnl # this is the latest kernel + AC_DEFINE(HAVE_DMA_RESV_FENCES, 1,[dma_resv->fences is available]) ], [ dnl # - dnl # v5.3-rc1-476-gb016cd6ed4b7 dma-buf: Restore seqlock around dma_resv updates - dnl # v5.3-rc1-449-g52791eeec1d9 dma-buf: rename reservation_object to dma_resv - dnl # v5.3-rc1-448-g5d344f58da76 dma-buf: nuke reservation_object seq number + dnl # v5.8-rc6-36-gcd29f22019ec dma-buf: Use sequence counter with associated wound/wait mutex + dnl # v5.8-rc6-35-g318ce71f3e3a dma-buf: Remove custom seqcount lockdep class key dnl # AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_LINUX_DMA_RESV_H #include - #else - #include - #endif ], [ - #ifdef HAVE_LINUX_DMA_RESV_H - struct dma_resv *resv = NULL; - #else - struct reservation_object *resv = NULL; - #endif - write_seqcount_begin(&resv->seq); + struct dma_resv *obj = NULL; + seqcount_ww_mutex_init(&obj->seq, &obj->lock); + ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T, 1, [dma_resv->seq is seqcount_ww_mutex_t]) ], [ - AC_DEFINE(HAVE_DMA_RESV_SEQ, 1, - [dma_resv->seq is available]) - ],[ - dnl # - dnl # dma_resv->seq is dropped since kernle 5.18.0 - dnl # So trigger the bug only for the kernel_version < 5.18.0 - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 18, 0) - int this_is_bug; - this_is_bug = 0; - #else - this_is_not_bug(); - #endif - ], [ - AC_DEFINE(HAVE_DMA_RESV_SEQ_BUG, 1, - [bug for missing dma_resv->seq]) - ]) + dnl # + dnl # v5.3-rc1-476-gb016cd6ed4b7 dma-buf: Restore seqlock around dma_resv updates + dnl # v5.3-rc1-449-g52791eeec1d9 dma-buf: rename reservation_object to dma_resv + dnl # v5.3-rc1-448-g5d344f58da76 dma-buf: nuke reservation_object seq number + dnl # + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_LINUX_DMA_RESV_H + #include + #else + #include + #endif + ], [ + #ifdef HAVE_LINUX_DMA_RESV_H + struct dma_resv *resv = NULL; + #else + struct reservation_object *resv = NULL; + #endif + write_seqcount_begin(&resv->seq); + ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQ, 1,[dma_resv->seq is available]) + ],[ + dnl # + dnl # Trigger the bug for dma_resv->seq definition + dnl # + AC_DEFINE(HAVE_DMA_RESV_SEQ_BUG, 1, [Reporting dma_resv->seq bug]) ]) ]) - ]) -]) - -dnl # -dnl # v5.18-rc1-237-g047a1b877ed4 -dnl # dma-buf & drm/amdgpu: remove dma_resv workaround -dnl # -AC_DEFUN([AC_AMDGPU_DMA_RESV_FENCES], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct dma_resv *resv = NULL; - resv->fences = NULL; - ], [ - AC_DEFINE(HAVE_DMA_RESV_FENCES, 1, - [dma_resv->fences is available]) ]) ]) ]) @@ -99,7 +78,6 @@ AC_DEFUN([AC_AMDGPU_RESERVATION_OBJECT_STAGED], [ ]) AC_DEFUN([AC_AMDGPU_DMA_RESV], [ - AC_AMDGPU_DMA_RESV_SEQ AC_AMDGPU_DMA_RESV_FENCES AC_AMDGPU_RESERVATION_OBJECT_STAGED ]) From 26a973dea7c0c2e8419ff026c66232d0721a6608 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 8 Feb 2023 10:49:20 +0800 Subject: [PATCH 0942/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 10 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 32 ------------- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 14 ------ drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c | 30 ------------ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 40 ---------------- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 40 ---------------- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 48 ------------------- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 40 ---------------- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 34 ------------- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 8 ---- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 ---- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 8 ---- drivers/gpu/drm/amd/dkms/config/config.h | 3 -- .../dkms/m4/drm-connector-list-iter-begin.m4 | 16 ------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 15 files changed, 332 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-list-iter-begin.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 8d3f165f4686d..250cfb0dcf20f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -1658,9 +1658,7 @@ amdgpu_connector_add(struct amdgpu_device *adev, { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector; struct amdgpu_connector_atom_dig *amdgpu_dig_connector; struct drm_encoder *encoder; @@ -1675,18 +1673,12 @@ amdgpu_connector_add(struct amdgpu_device *adev, return; /* see if we already added it */ -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->connector_id == connector_id) { amdgpu_connector->devices |= supported_device; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif return; } if (amdgpu_connector->ddc_bus && i2c_bus->valid) { @@ -1701,9 +1693,7 @@ amdgpu_connector_add(struct amdgpu_device *adev, } } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif /* check if it's a dp bridge */ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 9d968c2df5a7d..fdcb021d2f537 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -71,22 +71,14 @@ void amdgpu_display_hotplug_work_func(struct work_struct *work) struct drm_device *dev = adev_to_drm(adev); struct drm_mode_config *mode_config = &dev->mode_config; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif mutex_lock(&mode_config->mutex); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) -#endif amdgpu_connector_hotplug(connector); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif mutex_unlock(&mode_config->mutex); /* Just fire off a uevent and let userspace tell us what to do */ drm_helper_hpd_irq_event(dev); @@ -430,19 +422,13 @@ void amdgpu_display_print_display_setup(struct drm_device *dev) struct amdgpu_connector *amdgpu_connector; struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif uint32_t devices; int i = 0; DRM_INFO("AMDGPU Display Connectors\n"); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif amdgpu_connector = to_amdgpu_connector(connector); DRM_INFO("Connector %d:\n", i); DRM_INFO(" %s\n", connector->name); @@ -506,9 +492,7 @@ void amdgpu_display_print_display_setup(struct drm_device *dev) } i++; } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, @@ -1789,27 +1773,19 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) struct drm_crtc *crtc; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif int r; drm_kms_helper_poll_disable(dev); /* turn off display hw */ drm_modeset_lock_all(dev); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) -#endif drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif drm_modeset_unlock_all(dev); /* unpin the front buffers and cursors */ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { @@ -1857,9 +1833,7 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct drm_crtc *crtc; int r; @@ -1887,18 +1861,12 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev) /* turn on display hw */ drm_modeset_lock_all(dev); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) -#endif drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif drm_modeset_unlock_all(dev); drm_kms_helper_poll_enable(dev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 36e5243190a28..c07c1f0cf1280 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2763,9 +2763,7 @@ static int amdgpu_runtime_idle_check_display(struct device *dev) if (adev->mode_info.num_crtc) { struct drm_connector *list_connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif int ret = 0; if (amdgpu_runtime_pm != -2) { @@ -2775,20 +2773,14 @@ static int amdgpu_runtime_idle_check_display(struct device *dev) * the GPU was in suspend. Remove this once that is fixed. */ mutex_lock(&drm_dev->mode_config.mutex); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(drm_dev, &iter); drm_for_each_connector_iter(list_connector, &iter) { -#else - list_for_each_entry(list_connector, &(drm_dev)->mode_config.connector_list, head) { -#endif if (list_connector->status == connector_status_connected) { ret = -EBUSY; break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif mutex_unlock(&drm_dev->mode_config.mutex); if (ret) @@ -2810,21 +2802,15 @@ static int amdgpu_runtime_idle_check_display(struct device *dev) mutex_lock(&drm_dev->mode_config.mutex); drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(drm_dev, &iter); drm_for_each_connector_iter(list_connector, &iter) { -#else - list_for_each_entry(list_connector, &(drm_dev)->mode_config.connector_list, head) { -#endif if (list_connector->dpms == DRM_MODE_DPMS_ON) { ret = -EBUSY; break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); mutex_unlock(&drm_dev->mode_config.mutex); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c index ccd095286b0b0..dbd12456ff5fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c @@ -36,20 +36,14 @@ amdgpu_link_encoder_connector(struct drm_device *dev) { struct amdgpu_device *adev = drm_to_adev(dev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector; struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); /* walk the list and link encoders to connectors */ drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif amdgpu_connector = to_amdgpu_connector(connector); list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { amdgpu_encoder = to_amdgpu_encoder(encoder); @@ -62,9 +56,7 @@ amdgpu_link_encoder_connector(struct drm_device *dev) } } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } void amdgpu_encoder_set_active_device(struct drm_encoder *encoder) @@ -72,14 +64,10 @@ void amdgpu_encoder_set_active_device(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -89,9 +77,7 @@ void amdgpu_encoder_set_active_device(struct drm_encoder *encoder) amdgpu_connector->devices, encoder->encoder_type); } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } struct drm_connector * @@ -100,26 +86,18 @@ amdgpu_get_connector_for_encoder(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct drm_connector *connector, *found = NULL; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_encoder->active_device & amdgpu_connector->devices) { found = connector; break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif return found; } @@ -129,26 +107,18 @@ amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct drm_connector *connector, *found = NULL; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_encoder->devices & amdgpu_connector->devices) { found = connector; break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif return found; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index c9debcc3dc0cc..b1462aecffbda 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -334,17 +334,11 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -381,9 +375,7 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev) amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } /** @@ -398,17 +390,11 @@ static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -421,9 +407,7 @@ static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev) @@ -1251,9 +1235,7 @@ static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp; int interlace = 0; @@ -1261,20 +1243,14 @@ static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, if (!dig || !dig->afmt || !dig->afmt->pin) return; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1305,9 +1281,7 @@ static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp; u8 *sadb = NULL; @@ -1316,20 +1290,14 @@ static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder if (!dig || !dig->afmt || !dig->afmt->pin) return; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1369,9 +1337,7 @@ static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; struct cea_sad *sads; int i, sad_count; @@ -1394,20 +1360,14 @@ static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) if (!dig || !dig->afmt || !dig->afmt->pin) return; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 521da0ed73f6e..52c71b28a940b 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -358,17 +358,11 @@ static void dce_v11_0_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -404,9 +398,7 @@ static void dce_v11_0_hpd_init(struct amdgpu_device *adev) dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } /** @@ -421,17 +413,11 @@ static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -443,9 +429,7 @@ static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev) @@ -1283,9 +1267,7 @@ static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp; int interlace = 0; @@ -1293,20 +1275,14 @@ static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, if (!dig || !dig->afmt || !dig->afmt->pin) return; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1337,9 +1313,7 @@ static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp; u8 *sadb = NULL; @@ -1348,20 +1322,14 @@ static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder if (!dig || !dig->afmt || !dig->afmt->pin) return; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1401,9 +1369,7 @@ static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; struct cea_sad *sads; int i, sad_count; @@ -1426,20 +1392,14 @@ static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) if (!dig || !dig->afmt || !dig->afmt->pin) return; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 89e25807fa9ea..ceb1ab8d25985 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -313,17 +313,11 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -350,9 +344,7 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev) dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } /** @@ -367,17 +359,11 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -389,9 +375,7 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev) @@ -1223,27 +1207,19 @@ static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; int interlace = 0; u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1275,28 +1251,20 @@ static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; u8 *sadb = NULL; int sad_count; u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1345,9 +1313,7 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; u32 offset; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; struct cea_sad *sads; int i, sad_count; @@ -1372,20 +1338,14 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) offset = dig->afmt->pin->offset; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1776,9 +1736,7 @@ static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); int bpc = 8; @@ -1786,20 +1744,14 @@ static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, if (!dig || !dig->afmt) return; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 56a197182e537..1a549b474ebf9 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -296,17 +296,11 @@ static void dce_v8_0_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -333,9 +327,7 @@ static void dce_v8_0_hpd_init(struct amdgpu_device *adev) dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } /** @@ -350,17 +342,11 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -372,9 +358,7 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev) amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev) @@ -1206,9 +1190,7 @@ static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp = 0, offset; @@ -1217,20 +1199,14 @@ static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder, offset = dig->afmt->pin->offset; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1275,9 +1251,7 @@ static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 offset, tmp; u8 *sadb = NULL; @@ -1288,20 +1262,14 @@ static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) offset = dig->afmt->pin->offset; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1337,9 +1305,7 @@ static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; u32 offset; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; struct cea_sad *sads; int i, sad_count; @@ -1364,20 +1330,14 @@ static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) offset = dig->afmt->pin->offset; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 94ddba289768a..332098fda7085 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -793,9 +793,7 @@ static void dmub_hpd_callback(struct amdgpu_device *adev, struct amdgpu_dm_connector *aconnector; struct amdgpu_dm_connector *hpd_aconnector = NULL; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct dc_link *link; u8 link_index = 0; struct drm_device *dev; @@ -822,12 +820,8 @@ static void dmub_hpd_callback(struct amdgpu_device *adev, link_index = notify->link_index; link = adev->dm.dc->links[link_index]; dev = adev->dm.ddev; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -846,9 +840,7 @@ static void dmub_hpd_callback(struct amdgpu_device *adev, break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif drm_modeset_unlock(&dev->mode_config.connection_mutex); if (hpd_aconnector) { @@ -1081,9 +1073,7 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, struct drm_device *dev = dev_get_drvdata(kdev); struct amdgpu_device *adev = drm_to_adev(dev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter conn_iter; -#endif struct amdgpu_dm_connector *aconnector; int ret = 0; @@ -1091,12 +1081,8 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, mutex_lock(&adev->dm.audio_lock); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -1112,9 +1098,7 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, break; } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&conn_iter); -#endif mutex_unlock(&adev->dm.audio_lock); @@ -2642,17 +2626,11 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev) { struct amdgpu_dm_connector *aconnector; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif int ret = 0; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -2674,9 +2652,7 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev) } } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif return ret; } @@ -2824,17 +2800,11 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend) { struct amdgpu_dm_connector *aconnector; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct drm_dp_mst_topology_mgr *mgr; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -2864,9 +2834,7 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend) resume_mst_branch_status(mgr); } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } @@ -3401,9 +3369,7 @@ static int dm_resume(struct amdgpu_ip_block *ip_block) struct amdgpu_display_manager *dm = &adev->dm; struct amdgpu_dm_connector *aconnector; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); enum dc_connection_type new_connection_type = dc_connection_none; struct dc_state *dc_state; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index 0289299c273f6..a720908068a9d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -616,16 +616,10 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) dm_is_crc_source_dprx(cur_crc_src))) { struct amdgpu_dm_connector *aconn = NULL; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter conn_iter; -#endif -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(crtc->dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { -#else - list_for_each_entry(connector, &(crtc->dev)->mode_config.connector_list, head) { -#endif if (!connector->state || connector->state->crtc != crtc) continue; @@ -635,9 +629,7 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) aconn = to_amdgpu_dm_connector(connector); break; } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&conn_iter); -#endif if (!aconn) { DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 8e7f9a7ad68b5..a62981a37ec50 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3876,17 +3876,11 @@ static int mst_topo_show(struct seq_file *m, void *unused) struct amdgpu_device *adev = (struct amdgpu_device *)m->private; struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter conn_iter; -#endif struct amdgpu_dm_connector *aconnector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) continue; @@ -3899,9 +3893,7 @@ static int mst_topo_show(struct seq_file *m, void *unused) seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&conn_iter); -#endif return 0; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index a5d5617542654..c6303414be75d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -894,10 +894,6 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector) struct drm_device *dev = connector->dev; struct amdgpu_device *adev = drm_to_adev(dev); -#ifndef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN - drm_modeset_lock_all(dev); -#endif - #ifndef HAVE_DRM_DEVICE_FB_HELPER if (adev->mode_info.rfbdev) drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector); @@ -905,10 +901,6 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector) DRM_ERROR("adev->mode_info.rfbdev is NULL\n"); #endif -#ifndef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN - drm_modeset_unlock_all(dev); -#endif - drm_connector_register(connector); } #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e901d41c41c83..d6b64b16fc9de 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -242,9 +242,6 @@ /* drm_connector_init_with_ddc() is available */ #define HAVE_DRM_CONNECTOR_INIT_WITH_DDC 1 -/* drm_connector_list_iter_begin() is available */ -#define HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN 1 - /* connector property "max bpc" is available */ #define HAVE_DRM_CONNECTOR_PROPERTY_MAX_BPC 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-list-iter-begin.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-list-iter-begin.m4 deleted file mode 100644 index b9b18381ae244..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-list-iter-begin.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit 613051dac40da1751ab269572766d3348d45a197 -dnl # drm: locking&new iterators for connector_list -dnl # -AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_LIST_ITER_BEGIN], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - drm_connector_list_iter_begin(NULL, NULL); - ],[ - AC_DEFINE(HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN, 1, - [drm_connector_list_iter_begin() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f5ad3f249279b..805eea07ed16d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -108,7 +108,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS - AC_AMDGPU_DRM_CONNECTOR_LIST_ITER_BEGIN AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC From 86ebebaabb3eedb5373dbe80ca04db05de70e7f4 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 10 Feb 2023 14:36:54 +0800 Subject: [PATCH 0943/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_MODE_SUBCONNECTOR_ENUM Change-Id: I9c1a099e3cb61582473c3f0bea74aa90e3bf2543 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 | 9 --------- include/kcl/kcl_drm_connector.h | 13 ------------- 3 files changed, 25 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d6b64b16fc9de..8fe4415393f1f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -729,9 +729,6 @@ /* drm_mode_init() is available */ #define HAVE_DRM_MODE_INTT 1 -/* enum drm_mode_subconnector is available */ -/* #undef HAVE_DRM_MODE_SUBCONNECTOR_ENUM */ - /* drm_need_swiotlb() is availablea */ #define HAVE_DRM_NEED_SWIOTLB 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 index a6c7c75f41f9e..527068f2403f8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 @@ -12,15 +12,6 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_SUBCONNECTOR], [ ], [ AC_DEFINE(HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY, 1, [drm_mode_config->dp_subconnector_property is available]) - ], [ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - enum drm_mode_subconnector sub = 0; - ], [ - AC_DEFINE(HAVE_DRM_MODE_SUBCONNECTOR_ENUM, 1, - [enum drm_mode_subconnector is available]) - ]) ]) ]) ]) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 96e58541b57a4..ee8d72d7a4d72 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -76,24 +76,11 @@ void drm_connector_attach_dp_subconnector_property(struct drm_connector *connect void drm_dp_set_subconnector_property(struct drm_connector *connector, enum drm_connector_status status, const u8 *dpcd, const u8 prot_cap[4]); -#ifdef HAVE_DRM_MODE_SUBCONNECTOR_ENUM #define DRM_MODE_SUBCONNECTOR_VGA 1 #define DRM_MODE_SUBCONNECTOR_DisplayPort 10 #define DRM_MODE_SUBCONNECTOR_HDMIA 11 #define DRM_MODE_SUBCONNECTOR_Native 15 #define DRM_MODE_SUBCONNECTOR_Wireless 18 -#else -/* Copied from include/uapi/drm/drm_mode.h */ -/* This is for connectors with multiple signal types. */ -/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ -enum drm_mode_subconnector { - DRM_MODE_SUBCONNECTOR_VGA = 1, /* DP */ - DRM_MODE_SUBCONNECTOR_DisplayPort = 10, /* DP */ - DRM_MODE_SUBCONNECTOR_HDMIA = 11, /* DP */ - DRM_MODE_SUBCONNECTOR_Native = 15, /* DP */ - DRM_MODE_SUBCONNECTOR_Wireless = 18, /* DP */ -}; -#endif /* HAVE_DRM_MODE_SUBCONNECTOR_ENUM */ #endif /* HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY */ #ifndef HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL From 03492b962a42684f5d3d76a319e2d2f347decb60 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 9 Feb 2023 10:53:37 +0800 Subject: [PATCH 0944/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 12 +++--------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 | 19 ------------------- 3 files changed, 3 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index a1b159275b88f..e941d3a06b2f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -128,13 +128,11 @@ static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = { #endif }; -static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc +static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc, #if defined(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE) - , struct drm_atomic_state *state) -#elif defined(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE) - , struct drm_crtc_state *state) + struct drm_atomic_state *state) #else - ) + struct drm_crtc_state *state) #endif { drm_crtc_vblank_on(crtc); @@ -175,11 +173,7 @@ static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = { .atomic_flush = amdgpu_vkms_crtc_atomic_flush, -#if defined(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE) .atomic_enable = amdgpu_vkms_crtc_atomic_enable, -#else - .enable = amdgpu_vkms_crtc_atomic_enable, -#endif .atomic_disable = amdgpu_vkms_crtc_atomic_disable, }; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8fe4415393f1f..e76319721412d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -286,9 +286,6 @@ drm_atomic_state arg */ #define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE 1 -/* have drm_crtc_helper_funcs->atomic_enable() */ -#define HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE 1 - /* drm_crtc_init_with_planes() wants name */ #define HAVE_DRM_CRTC_INIT_WITH_PLANES_VALID_WITH_NAME 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 index ea944aff250c5..5bfb416a8ed5e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 @@ -35,25 +35,6 @@ AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE], [ ], [ AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE, 1, [drm_crtc_helper_funcs->atomic_enable()/atomic_disable() wants struct drm_atomic_state arg]) - AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE, 1, - [have drm_crtc_helper_funcs->atomic_enable()]) - - ],[ - dnl # - dnl # v4.12-rc7-1332-g0b20a0f8c3cb - dnl # drm: Add old state pointer to CRTC .enable() helper function - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - #include - ], [ - struct drm_crtc_helper_funcs *p = NULL; - p->atomic_enable(NULL, NULL); - ], [ - AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE, 1, - [have drm_crtc_helper_funcs->atomic_enable()]) - ]) - ]) ]) ]) From 1bc206388213502b91d02cb03e493bd13442a133 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 9 Feb 2023 11:27:07 +0800 Subject: [PATCH 0945/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_DEVICE_DRIVER_FEATURES Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 14 +------------- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 4 ---- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../gpu/drm/amd/dkms/m4/struct_drm_device.m4 | 19 ------------------- 4 files changed, 1 insertion(+), 39 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index c07c1f0cf1280..f4370360f4b19 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2428,17 +2428,8 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, kcl_drm_vma_offset_manager_init(ddev->vma_offset_manager); -#ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; -#else - /* warn the user if they mix atomic and non-atomic capable GPUs */ - if ((amdgpu_kms_driver.driver_features & DRIVER_ATOMIC) && !supports_atomic) - DRM_ERROR("Mixing atomic and non-atomic capable GPUs!\n"); - /* support atomic early so the atomic debugfs stuff gets created */ - if (supports_atomic) - amdgpu_kms_driver.driver_features |= DRIVER_ATOMIC; -#endif kcl_pci_create_measure_file(pdev); kcl_pci_configure_extended_tags(pdev); @@ -3115,10 +3106,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { static struct drm_driver amdgpu_kms_driver = { .driver_features = - 0 -#ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES - | DRIVER_ATOMIC -#endif /* HAVE_DRM_DEVICE_DRIVER_FEATURES */ + DRIVER_ATOMIC | DRIVER_HAVE_IRQ #ifdef HAVE_DRM_DRV_DRIVER_IRQ_SHARED | DRIVER_IRQ_SHARED diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index a5225e6f41cf1..13f0cdeb59c46 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -64,11 +64,7 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev) adev->mode_info.num_crtc = 1; adev->enable_virtual_display = true; } -#ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES ddev->driver_features &= ~DRIVER_ATOMIC; -#else - ddev->driver->driver_features &= ~DRIVER_ATOMIC; -#endif adev->cg_flags = 0; adev->pg_flags = 0; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e76319721412d..9d32fd86a3ac0 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -292,9 +292,6 @@ /* drm_debug_enabled() is available */ #define HAVE_DRM_DEBUG_ENABLED 1 -/* dev_device->driver_features is available */ -#define HAVE_DRM_DEVICE_DRIVER_FEATURES 1 - /* struct drm_device has fb_helper member */ #define HAVE_DRM_DEVICE_FB_HELPER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 index 7ea0061caa47e..929e3edc5f603 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 @@ -1,21 +1,3 @@ -dnl # -dnl # commit v4.19-rc1-194-g18ace11f87e6 -dnl # drm: Introduce per-device driver_features -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - struct drm_device *ddev = NULL; - ddev->driver_features = 0; - ],[ - AC_DEFINE(HAVE_DRM_DEVICE_DRIVER_FEATURES, 1, - [dev_device->driver_features is available]) - ]) - ]) -]) - dnl # dnl # commit v5.5-rc2-1419-g7e13ad896484 dnl # drm: Avoid drm_global_mutex for simple inc/dec of dev->open_count @@ -35,6 +17,5 @@ AC_DEFUN([AC_AMDGPU_DRM_DEVICE_OPEN_COUNT], [ ]) AC_DEFUN([AC_AMDGPU_STRUCT_DRM_DEVICE], [ - AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES AC_AMDGPU_DRM_DEVICE_OPEN_COUNT ]) From 90d3f6a629ac807eae9d5081cdfaaac28c0efec4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 9 Feb 2023 11:45:51 +0800 Subject: [PATCH 0946/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_DEVICE_FB_HELPER Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 11 ---------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../drm/amd/dkms/m4/drm-device-fb-helper.m4 | 21 ------------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/backport/kcl_drm_fb.h | 3 +-- 5 files changed, 1 insertion(+), 38 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index c6303414be75d..5617a1e740696 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -870,10 +870,6 @@ static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, mutex_unlock(&mgr->lock); } drm_connector_unregister(connector); -#if defined(HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS) && !defined(HAVE_DRM_DEVICE_FB_HELPER) - if (adev->mode_info.rfbdev) - drm_fb_helper_remove_one_connector(&adev->mode_info.rfbdev->helper, connector); -#endif drm_connector_put(connector); } #endif @@ -894,13 +890,6 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector) struct drm_device *dev = connector->dev; struct amdgpu_device *adev = drm_to_adev(dev); -#ifndef HAVE_DRM_DEVICE_FB_HELPER - if (adev->mode_info.rfbdev) - drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector); - else - DRM_ERROR("adev->mode_info.rfbdev is NULL\n"); -#endif - drm_connector_register(connector); } #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9d32fd86a3ac0..4a5bb2f588ebf 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -292,9 +292,6 @@ /* drm_debug_enabled() is available */ #define HAVE_DRM_DEBUG_ENABLED 1 -/* struct drm_device has fb_helper member */ -#define HAVE_DRM_DEVICE_FB_HELPER 1 - /* drm_device->filelist_mutex is available */ #define HAVE_DRM_DEVICE_FILELIST_MUTEX 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 deleted file mode 100644 index b5e24caf0a842..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 +++ /dev/null @@ -1,21 +0,0 @@ -dnl # -dnl # commit v4.14-rc3-575-g29ad20b22c8f -dnl # drm: Add drm_device->fb_helper pointer -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DEVICE_FB_HELPER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - #include - #endif - #ifdef HAVE_DRM_DRM_DEVICE_H - #include - #endif - ], [ - struct drm_device *pdd = NULL; - pdd->fb_helper = NULL; - ], [ - AC_DEFINE(HAVE_DRM_DEVICE_FB_HELPER, 1, [struct drm_device has fb_helper member]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 805eea07ed16d..8cbe175685506 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -165,7 +165,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT AC_AMDGPU_DRM_MODE_CONFIG_HELPER_SUSPEND AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP - AC_AMDGPU_DRM_DEVICE_FB_HELPER AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index f1d242ac9d61f..1269be6e2d9c9 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -38,8 +38,7 @@ void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, #define drm_helper_mode_fill_fb_struct _kcl_drm_helper_mode_fill_fb_struct #endif -#if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) && \ - defined(HAVE_DRM_DEVICE_FB_HELPER) +#if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) #define AMDKCL_DRM_FBDEV_GENERIC #endif From 1472dd4c466ffa5c5a39a3558b74aee05dd4271e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 9 Feb 2023 12:14:45 +0800 Subject: [PATCH 0947/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_DEV_ENTER also remove macro HAVE_DRM_DEV_IS_UNPLUGGED Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c | 73 ------------------- drivers/gpu/drm/amd/dkms/config/config.h | 6 -- drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 | 19 ----- .../drm/amd/dkms/m4/drm-dev-is-unplugged.m4 | 21 ------ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 - include/kcl/kcl_drm_drv.h | 70 ------------------ 7 files changed, 1 insertion(+), 192 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 delete mode 100644 include/kcl/kcl_drm_drv.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 0accf6c787b2b..eb1682f507b91 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,7 +12,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ - kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ + kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c deleted file mode 100644 index 8014069a7c654..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org - * - * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Author Rickard E. (Rik) Faith - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef HAVE_DRM_DEV_ENTER -#include -#include - -DEFINE_STATIC_SRCU(drm_unplug_srcu); - -/** - * drm_dev_enter - Enter device critical section - * @dev: DRM device - * @idx: Pointer to index that will be passed to the matching drm_dev_exit() - * - * This function marks and protects the beginning of a section that should not - * be entered after the device has been unplugged. The section end is marked - * with drm_dev_exit(). Calls to this function can be nested. - * - * Returns: - * True if it is OK to enter the section, false otherwise. - */ -bool drm_dev_enter(struct drm_device *dev, int *idx) -{ - *idx = srcu_read_lock(&drm_unplug_srcu); - - if (atomic_read(&dev->unplugged)) { - srcu_read_unlock(&drm_unplug_srcu, *idx); - return false; - } - - return true; -} -EXPORT_SYMBOL(drm_dev_enter); - -/** - * drm_dev_exit - Exit device critical section - * @idx: index returned from drm_dev_enter() - * - * This function marks the end of a section that should not be entered after - * the device has been unplugged. - */ -void drm_dev_exit(int idx) -{ - srcu_read_unlock(&drm_unplug_srcu, idx); -} -EXPORT_SYMBOL(drm_dev_exit); - -#endif /* HAVE_DRM_DEV_ENTER */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4a5bb2f588ebf..09cc0d5883ca2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -301,12 +301,6 @@ /* struct drm_device has pdev member */ /* #undef HAVE_DRM_DEVICE_PDEV */ -/* drm_dev_enter() is available */ -#define HAVE_DRM_DEV_ENTER 1 - -/* drm_dev_is_unplugged() is available */ -#define HAVE_DRM_DEV_IS_UNPLUGGED 1 - /* drm_dev_put() is available */ #define HAVE_DRM_DEV_PUT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 deleted file mode 100644 index 4ac5579c0f5c2..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 +++ /dev/null @@ -1,19 +0,0 @@ -dnl # -dnl # commit bee330f3d67273a68dcb99f59480d59553c008b2 -dnl # drm: Use srcu to protect drm_device.unplugged -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DEV_ENTER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DRMP_H - #include - #else - #include - #endif - ], [ - drm_dev_enter(NULL, NULL); - ], [drm_dev_enter], [drivers/gpu/drm/drm_drv.c], [ - AC_DEFINE(HAVE_DRM_DEV_ENTER, 1, [drm_dev_enter() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 deleted file mode 100644 index 4a05d157649e4..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 +++ /dev/null @@ -1,21 +0,0 @@ -dnl # -dnl # commit bee330f3d67273a68dcb99f59480d59553c008b2 -dnl # drm: Use srcu to protect drm_device.unplugged -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DEV_IS_UNPLUGGED], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - #include - #endif - #ifdef HAVE_DRM_DRM_DRV_H - #include - #endif - ], [ - drm_dev_is_unplugged(NULL); - ], [ - AC_DEFINE(HAVE_DRM_DEV_IS_UNPLUGGED, 1, - [drm_dev_is_unplugged() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8cbe175685506..034c153353f75 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -158,8 +158,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA - AC_AMDGPU_DRM_DEV_ENTER - AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT diff --git a/include/kcl/kcl_drm_drv.h b/include/kcl/kcl_drm_drv.h deleted file mode 100644 index 0360a07613727..0000000000000 --- a/include/kcl/kcl_drm_drv.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * Copyright (c) 2009-2010, Code Aurora Forum. - * Copyright 2016 Intel Corp. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef __KCL_KCL_DRM_DRV_H__ -#define __KCL_KCL_DRM_DRV_H__ - -#include -#include - -#ifndef HAVE_DRM_DEV_ENTER -/* Copied from include/drm/drm_drv.h*/ - -bool drm_dev_enter(struct drm_device *dev, int *idx); -void drm_dev_exit(int idx); - -#ifndef HAVE_DRM_DEV_IS_UNPLUGGED -/** - * drm_dev_is_unplugged - is a DRM device unplugged - * @dev: DRM device - * - * This function can be called to check whether a hotpluggable is unplugged. - * Unplugging itself is singalled through drm_dev_unplug(). If a device is - * unplugged, these two functions guarantee that any store before calling - * drm_dev_unplug() is visible to callers of this function after it completes - * - * WARNING: This function fundamentally races against drm_dev_unplug(). It is - * recommended that drivers instead use the underlying drm_dev_enter() and - * drm_dev_exit() function pairs. - */ -static inline bool drm_dev_is_unplugged(struct drm_device *dev) -{ - int idx; - - if (drm_dev_enter(dev, &idx)) { - drm_dev_exit(idx); - return false; - } - - return true; -} -#endif /* HAVE_DRM_DEV_IS_UNPLUGGED */ -#endif /* HAVE_DRM_DEV_ENTER */ - -#ifndef HAVE_DRM_FIRMWARE_DRIVERS_ONLY -extern bool drm_firmware_drivers_only(void); -#endif /* HAVE_DRM_FIRMWARE_DRIVERS_ONLY */ - -#endif From d71bad54bda6974364333c36398238cf97b76cd9 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 13 Feb 2023 09:40:57 +0800 Subject: [PATCH 0948/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED Change-Id: I47eeadd6c7a9fd91ccaff1d8d7077a6961b543ee Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c | 23 +------------------ drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../m4/drm-fb-helper-set-suspend-unlocked.m4 | 20 ---------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/kcl_drm_fb.h | 11 --------- 5 files changed, 1 insertion(+), 57 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c index 139e955f225eb..bdd63a1cc9b36 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -56,25 +56,4 @@ void drm_fb_helper_fill_info(struct fb_info *info, } EXPORT_SYMBOL(drm_fb_helper_fill_info); -#endif - -#ifndef HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED -/** - * Copied from drivers/gpu/drm/drm_fb_helper.c and modified for KCL. - * _kcl_drm_fb_helper_set_suspend_stub - wrapper around fb_set_suspend - * @fb_helper: driver-allocated fbdev helper - * @state: desired state, zero to resume, non-zero to suspend - * - * A wrapper around fb_set_suspend implemented by fbdev core - */ -void _kcl_drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, int state) -{ - if (!fb_helper || !fb_helper->fbdev) - return; - - console_lock(); - fb_set_suspend(fb_helper->fbdev, state); - console_unlock(); -} -EXPORT_SYMBOL(_kcl_drm_fb_helper_set_suspend_unlocked); -#endif +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 09cc0d5883ca2..57ad3ec5d0b8f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -603,9 +603,6 @@ /* whether drm_fb_helper_lastclose() is available */ #define HAVE_DRM_FB_HELPER_LASTCLOSE 1 -/* drm_fb_helper_set_suspend_unlocked() is available */ -#define HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED 1 - /* drm_fb_helper_unregister_info() is available */ #define HAVE_DRM_FB_HELPER_UNREGISTER_INFO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 deleted file mode 100644 index c2502e2f914da..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 +++ /dev/null @@ -1,20 +0,0 @@ -dnl # -dnl # commit cfe63423d9be3e7020296c3dfb512768a83cd099 -dnl # drm/fb-helper: Add drm_fb_helper_set_suspend_unlocked() -dnl # -AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; - #include - #endif - #include - ], [ - drm_fb_helper_set_suspend_unlocked(NULL,0); - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED, 1, - [drm_fb_helper_set_suspend_unlocked() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 034c153353f75..55ec00b0277a2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -90,7 +90,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_FB_HELPER_FILL_INFO - AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_FB_HELPER_INIT AC_AMDGPU_DRM_GET_FORMAT_INFO diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 392638c78018c..795395d696484 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -61,17 +61,6 @@ void drm_fb_helper_fill_info(struct fb_info *info, struct drm_fb_helper_surface_size *sizes); #endif -#ifndef HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED -extern void _kcl_drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, int state); -static inline -void drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, - bool suspend) - -{ - _kcl_drm_fb_helper_set_suspend_unlocked(fb_helper, suspend); -} -#endif - #ifndef HAVE_IS_FIRMWARE_FRAMEBUFFER extern bool is_firmware_framebuffer(struct apertures_struct *a); #endif From 30e00df6da912f37389b12efb017fd5766b7d421 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 13 Feb 2023 09:44:24 +0800 Subject: [PATCH 0949/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_EDID_GET_MONITOR_NAME Change-Id: I919069ffe537d38ff16ebe6123eb5b33c6aa5276 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 21 +------------------ drivers/gpu/drm/amd/dkms/config/config.h | 9 -------- .../amd/dkms/m4/drm-edid-get-monitor-name.m4 | 17 --------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 4 files changed, 1 insertion(+), 47 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 84db62f16a1d2..d468a987ae60a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -149,9 +149,6 @@ enum dc_edid_status dm_helpers_parse_edid_caps( int sadb_count = -1; int i = 0; uint8_t *sadb = NULL; -#if !defined(HAVE_DRM_EDID_GET_MONITOR_NAME) - int j = 0; -#endif enum dc_edid_status result = EDID_OK; @@ -168,26 +165,10 @@ enum dc_edid_status dm_helpers_parse_edid_caps( edid_caps->serial_number = edid_buf->serial; edid_caps->manufacture_week = edid_buf->mfg_week; edid_caps->manufacture_year = edid_buf->mfg_year; -#if defined(HAVE_DRM_EDID_GET_MONITOR_NAME) + drm_edid_get_monitor_name(edid_buf, edid_caps->display_name, AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); -#else - /* One of the four detailed_timings stores the monitor name. It's - * stored in an array of length 13. */ - for (i = 0; i < 4; i++) { - if (edid_buf->detailed_timings[i].data.other_data.type == 0xfc) { - while (j < 13 && edid_buf->detailed_timings[i].data.other_data.data.str.str[j]) { - if (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] == '\n') - break; - - edid_caps->display_name[j] = - edid_buf->detailed_timings[i].data.other_data.data.str.str[j]; - j++; - } - } - } -#endif #if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) edid_caps->edid_hdmi = connector->display_info.is_hdmi; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 57ad3ec5d0b8f..fe52f0eaa04b3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1298,15 +1298,6 @@ /* drm_dsc_pps_payload_pack() is available */ #define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 -/* drm_edid_get_monitor_name is available*/ -#define HAVE_DRM_EDID_GET_MONITOR_NAME 1 - -/* __drm_atomic_helper_connector_destroy_state() wants 1 arg */ -#define HAVE___DRM_ATOMIC_HELPER_CONNECTOR_DESTROY_STATE_P 1 - -/* __drm_atomic_helper_crtc_destroy_state() wants 1 arg */ -#define HAVE___DRM_ATOMIC_HELPER_CRTC_DESTROY_STATE_P 1 - /* __drm_atomic_helper_crtc_reset() is available */ #define HAVE___DRM_ATOMIC_HELPER_CRTC_RESET 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 deleted file mode 100644 index 4a6a10c962f4c..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 +++ /dev/null @@ -1,17 +0,0 @@ -dnl # -dnl # commit v4.6-rc2-221-g59f7c0fa325e -dnl # drm/edid: Add drm_edid_get_monitor_name() -dnl # -AC_DEFUN([AC_AMDGPU_DRM_EDID_GET_MONITOR_NAME], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_edid_get_monitor_name(NULL, NULL, 0); - ], [drm_edid_get_monitor_name], [drivers/gpu/drm/drm_edid.c], [ - AC_DEFINE(HAVE_DRM_EDID_GET_MONITOR_NAME, 1, - [drm_edid_get_monitor_name() are available]) - ]) - ]) -]) - diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 55ec00b0277a2..e07c72812effb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -166,7 +166,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI AC_AMDGPU_DRM_BITMAP_FUNCS - AC_AMDGPU_DRM_EDID_GET_MONITOR_NAME AC_AMDGPU_STRUCT_KOBJ_TYPE AC_AMDGPU_CLOSE_FD AC_AMDGPU_IS_FIRMWARE_FRAMEBUFFER From a0c51adc797779a1f6c03fe2518f619781ceaae7 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 13 Feb 2023 10:33:59 +0800 Subject: [PATCH 0950/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_DRM_PRINT_H Also removed related macro HAVE_DRM_PRINTER_PREFIX Change-Id: Iac8228a7ce9011fbb67423ea55d811e3e810717d Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 34 ---------------- drivers/gpu/drm/amd/dkms/config/config.h | 6 --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 --- drivers/gpu/drm/amd/dkms/m4/drm_print.m4 | 21 ---------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/header/drm/drm_print.h | 2 - include/kcl/kcl_drm_print.h | 46 ---------------------- 7 files changed, 116 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_print.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 95e75be1d5ee8..68e4abe6470c6 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -26,40 +26,6 @@ #include #include -#if !defined(HAVE_DRM_DRM_PRINT_H) -void drm_printf(struct drm_printer *p, const char *f, ...) -{ - struct va_format vaf; - va_list args; - - va_start(args, f); - vaf.fmt = f; - vaf.va = &args; - p->printfn(p, &vaf); - va_end(args); -} -EXPORT_SYMBOL(drm_printf); - -void __drm_printfn_seq_file(struct drm_printer *p, struct va_format *vaf) -{ - seq_printf(p->arg, "%pV", vaf); -} -EXPORT_SYMBOL(__drm_printfn_seq_file); -#endif - -#if !defined(HAVE_DRM_PRINTER_PREFIX) -void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf) -{ -#ifndef HAVE_DRM_DRM_PRINT_H - printk(KERN_DEBUG "[" DRM_NAME ":]" "%s %pV", p->prefix, vaf); -#else - printk(KERN_DEBUG "[" DRM_NAME ":]" "%s %pV", "no prefix", vaf); -#endif -} -EXPORT_SYMBOL(__drm_printfn_debug); -#endif - - #if !defined(HAVE_DRM_ERR_MACRO) void kcl_drm_err(const char *format, ...) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index fe52f0eaa04b3..8ee02622b581d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -542,9 +542,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PLANE_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_PRINT_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 @@ -742,9 +739,6 @@ /* drm_prime_sg_to_dma_addr_array() is available */ #define HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY 1 -/* drm_printer->prefix is available */ -#define HAVE_DRM_PRINTER_PREFIX 1 - /* drm_print_bits() is available */ #define HAVE_DRM_PRINT_BITS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index ccdccb0e48d30..5004222733f88 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -9,12 +9,6 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/amdgpu_pciid.h]) - dnl # - dnl # commit v4.9-rc2-477-gd8187177b0b1 - dnl # drm: add helper for printing to log or seq_file - dnl # - AC_KERNEL_CHECK_HEADERS([drm/drm_print.h]) - dnl # dnl # commit v5.0-rc1-342-gfcd70cd36b9b dnl # drm: Split out drm_probe_helper.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_print.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_print.m4 deleted file mode 100644 index 3c4a306d53cd3..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_print.m4 +++ /dev/null @@ -1,21 +0,0 @@ -dnl # -dnl # v4.9-rc2-477-gd8187177b0b1 drm: add helper for printing to log or seq_file -dnl # -AC_DEFUN([AC_AMDGPU_DRM_PRINTER], [ - AC_KERNEL_DO_BACKGROUND([ - AS_IF([test $HAVE_DRM_DRM_PRINT_H], [ - dnl # - dnl # v4.9-rc8-1738-gb5c3714fe878 drm/mm: Convert to drm_printer - dnl # v4.9-rc8-1737-g3d387d923c18 drm/printer: add debug printer - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_printer *p = NULL; - p->prefix = NULL; - ], [ - AC_DEFINE(HAVE_DRM_PRINTER_PREFIX, 1, [drm_printer->prefix is available]) - ]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e07c72812effb..0fa70bba4bd10 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -79,7 +79,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT - AC_AMDGPU_DRM_PRINTER AC_AMDGPU_DRM_PRINT_BITS AC_AMDGPU_DRM_MM_INSERT_MODE AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES diff --git a/include/kcl/header/drm/drm_print.h b/include/kcl/header/drm/drm_print.h index 0f1db6376a8a3..a6734c48c8eb5 100644 --- a/include/kcl/header/drm/drm_print.h +++ b/include/kcl/header/drm/drm_print.h @@ -2,9 +2,7 @@ #ifndef _KCL_HEADER_DRM_PRINT_H_H_ #define _KCL_HEADER_DRM_PRINT_H_H_ -#if defined(HAVE_DRM_DRM_PRINT_H) #include_next -#endif #include #endif diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index a726abd73190d..71a5b6f419e46 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -29,52 +29,6 @@ #include #include -#if !defined(HAVE_DRM_DRM_PRINT_H) -/* Copied from d8187177b0b1 include/drm/drm_print.h */ -struct drm_printer { - void (*printfn)(struct drm_printer *p, struct va_format *vaf); - void *arg; - const char *prefix; -}; - -void drm_printf(struct drm_printer *p, const char *f, ...); -void __drm_printfn_seq_file(struct drm_printer *p, struct va_format *vaf); -static inline struct drm_printer drm_seq_file_printer(struct seq_file *f) -{ - struct drm_printer p = { - .printfn = __drm_printfn_seq_file, - .arg = f, - }; - return p; -} -#endif - -/* Copied from 3d387d923c18 include/drm/drm_print.h */ -#if !defined(HAVE_DRM_PRINTER_PREFIX) -extern void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf); - -static inline struct drm_printer drm_debug_printer(const char *prefix) -{ - struct drm_printer p = { - .printfn = __drm_printfn_debug, -#ifndef HAVE_DRM_DRM_PRINT_H - .prefix = prefix -#endif - }; - return p; -} - -static inline -void drm_mm_print(const struct drm_mm *mm, struct drm_printer *p) -{ -#ifndef HAVE_DRM_DRM_PRINT_H - drm_mm_debug_table((struct drm_mm *)mm, p->prefix); -#else - drm_mm_debug_table((struct drm_mm *)mm, "no prefix"); -#endif -} -#endif - #ifndef _DRM_PRINTK #define _DRM_PRINTK(once, level, fmt, ...) \ do { \ From 539e8fe53d482a3e91fe7b74f2e7d16301927de9 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 10 Feb 2023 10:58:47 +0800 Subject: [PATCH 0951/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../m4/drm-dp-cec-correlation-functions.m4 | 21 ------------------- include/kcl/kcl_drm_dp_cec.h | 14 ------------- 3 files changed, 38 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8ee02622b581d..e1ed70e354d3e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -376,9 +376,6 @@ /* drm_dp_calc_pbn_mode() wants 3args */ #define HAVE_DRM_DP_CALC_PBN_MODE_3ARGS 1 -/* drm_dp_cec* correlation functions are available */ -#define HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS 1 - /* drm_dp_cec_register_connector() wants p,p interface */ #define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 index 30cf21b106f4b..3ba925a8e076f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 @@ -17,27 +17,6 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ ], [ AC_DEFINE(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP, 1, [drm_dp_cec_register_connector() wants p,p interface]) - AC_DEFINE(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS, 1, - [drm_dp_cec* correlation functions are available]) - ], [ - AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) - #include - #else - #include - #endif - ], [ - drm_dp_cec_irq(NULL); - drm_dp_cec_register_connector(NULL, NULL, NULL); - drm_dp_cec_unregister_connector(NULL); - drm_dp_cec_set_edid(NULL, NULL); - drm_dp_cec_unset_edid(NULL); - ], [ - AC_DEFINE(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS, 1, - [drm_dp_cec* correlation functions are available]) - ]) ]) ]) ]) diff --git a/include/kcl/kcl_drm_dp_cec.h b/include/kcl/kcl_drm_dp_cec.h index 58549a2e15bf1..a50c290cc7248 100644 --- a/include/kcl/kcl_drm_dp_cec.h +++ b/include/kcl/kcl_drm_dp_cec.h @@ -22,7 +22,6 @@ #if defined(AMDKCL_DRM_DP_CEC_XXX_CHECK_CB) static inline void _kcl_drm_dp_cec_irq(struct drm_dp_aux *aux) { -#if defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) #ifdef CONFIG_DRM_DP_CEC /* No transfer function was set, so not a DP connector */ if (!aux->transfer) @@ -30,13 +29,11 @@ static inline void _kcl_drm_dp_cec_irq(struct drm_dp_aux *aux) #endif drm_dp_cec_irq(aux); -#endif } static inline void _kcl_drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid) { -#if defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) #ifdef CONFIG_DRM_DP_CEC /* No transfer function was set, so not a DP connector */ if (!aux->transfer) @@ -44,12 +41,10 @@ static inline void _kcl_drm_dp_cec_set_edid(struct drm_dp_aux *aux, #endif drm_dp_cec_set_edid(aux, edid); -#endif } static inline void _kcl_drm_dp_cec_unset_edid(struct drm_dp_aux *aux) { -#if defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) #ifdef CONFIG_DRM_DP_CEC /* No transfer function was set, so not a DP connector */ if (!aux->transfer) @@ -57,13 +52,6 @@ static inline void _kcl_drm_dp_cec_unset_edid(struct drm_dp_aux *aux) #endif drm_dp_cec_unset_edid(aux); -#endif -} -#endif - -#if !defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) -static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) -{ } #endif @@ -71,14 +59,12 @@ static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) static inline void _kcl_drm_dp_cec_register_connector(struct drm_dp_aux *aux, struct drm_connector *connector) { -#if defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) #ifdef CONFIG_DRM_DP_CEC if (WARN_ON(!aux->transfer)) return; #endif drm_dp_cec_register_connector(aux, connector->name, connector->dev->dev); -#endif } #endif From 86efbbbf6dafe5d0a688a556a6c4e5a4b4c0b5c4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 10 Feb 2023 12:48:43 +0800 Subject: [PATCH 0952/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 8 -------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 | 16 ---------------- 3 files changed, 27 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index d468a987ae60a..a7ae4a866d83b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -458,19 +458,11 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( slots = drm_dp_find_vcpi_slots(mst_mgr, pbn); ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, -#ifdef HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I slots); -#else - &slots); -#endif /* HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I */ #else ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, dm_conn_state->pbn, -#ifdef HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I dm_conn_state->vcpi_slots); -#else - &dm_conn_state->vcpi_slots); -#endif /* HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I */ #endif if (!ret) return false; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e1ed70e354d3e..94507b36365e5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -394,9 +394,6 @@ /* drm_dp_mst_add_affected_dsc_crtcs() is available */ #define HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS 1 -/* drm_dp_mst_allocate_vcpi() has p,p,i,i interface */ -#define HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I 1 - /* drm_dp_mst_atomic_check() is available */ #define HAVE_DRM_DP_MST_ATOMIC_CHECK 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 index ef01260a09ddb..cf4afe7538011 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 @@ -6,22 +6,6 @@ dnl # Note: This autoconf only works with compiler flag -Werror dnl # The interface types are specified in Hungarian notation dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else - #include - #endif - ], [ - drm_dp_mst_allocate_vcpi(NULL, NULL, 1, 1); - ], [ - AC_DEFINE(HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I, 1, [ - drm_dp_mst_allocate_vcpi() has p,p,i,i interface]) - ]) - ]) dnl # dnl # commit d25689760b747287c6ca03cfe0729da63e0717f4 dnl # drm/amdgpu/display: Keep malloc ref to MST port From 48de2272884283515b3343f5a34e8b1e1699df3b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 10 Feb 2023 13:17:02 +0800 Subject: [PATCH 0953/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG This also remove macro HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL and HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_RETURN_BOOL Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- .../drm/amd/backport/include/kcl/kcl_amdgpu.h | 45 -------------- drivers/gpu/drm/amd/dkms/config/config.h | 9 --- .../drm_calc_vbltimestamp_from_scanoutpos.m4 | 58 ------------------- .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 2 - 4 files changed, 114 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_calc_vbltimestamp_from_scanoutpos.m4 diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h index 9b26a06085c84..33bf87c0568bd 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -28,7 +28,6 @@ static inline void kcl_amdgpu_disable_vblank_kms(struct drm_device *dev, unsigne return amdgpu_disable_vblank_kms(drm_crtc); } -#if defined(HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL) static inline bool kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, bool in_vblank_irq, int *vpos, int *hpos, ktime_t *stime, ktime_t *etime, @@ -36,57 +35,13 @@ static inline bool kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, { return !!amdgpu_display_get_crtc_scanoutpos(dev, pipe, in_vblank_irq, vpos, hpos, stime, etime, mode); } -#else -static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, - unsigned int flags, int *vpos, int *hpos, - ktime_t *stime, ktime_t *etime, - const struct drm_display_mode *mode) -{ - return amdgpu_display_get_crtc_scanoutpos(dev, pipe, flags, vpos, hpos, stime, etime, mode); -} -#endif -#if defined(HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG) static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, int *max_error, ktime_t *vblank_time, bool in_vblank_irq) { return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, vblank_time, in_vblank_irq); } -#elif defined(HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_RETURN_BOOL) -static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, - int *max_error, struct timeval *vblank_time, - bool in_vblank_irq) -{ - return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, vblank_time, in_vblank_irq); -} -#else -static inline int kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, - int *max_error, struct timeval *vblank_time, - unsigned flags) -{ - struct drm_crtc *crtc; - struct amdgpu_device *adev = drm_to_adev(dev); - - if (pipe >= dev->num_crtcs) { - DRM_ERROR("Invalid crtc %u\n", pipe); - return -EINVAL; - } - - /* Get associated drm_crtc: */ - crtc = &adev->mode_info.crtcs[pipe]->base; - if (!crtc) { - /* This can occur on driver load if some component fails to - * initialize completely and driver is unloaded */ - DRM_ERROR("Uninitialized crtc %d\n", pipe); - return -EINVAL; - } - - return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, - vblank_time, flags, - &crtc->hwmode); -} -#endif /* HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG */ #endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP */ static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 94507b36365e5..327d660f20628 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -463,15 +463,6 @@ /* drm_driver->gem_prime_res_obj() is available */ /* #undef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ */ -/* drm_driver->get_scanout_position() return bool */ -/* #undef HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL */ - -/* drm_driver->get_vblank_timestamp() return bool */ -/* #undef HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_RETURN_BOOL */ - -/* drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg */ -/* #undef HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG */ - /* drm_vblank struct use ktime_t for time field */ #define HAVE_DRM_VBLANK_USE_KTIME_T 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_calc_vbltimestamp_from_scanoutpos.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_calc_vbltimestamp_from_scanoutpos.m4 deleted file mode 100644 index 35e273468a27f..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_calc_vbltimestamp_from_scanoutpos.m4 +++ /dev/null @@ -1,58 +0,0 @@ -dnl # -dnl # commit v4.14-rc3-721-g67680d3c0464 -dnl # drm: vblank: use ktime_t instead of timeval -dnl # -AC_DEFUN([AC_AMDGPU_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; - #include - #else - #include - #include - #endif - ], [ - struct drm_driver *kms_driver = NULL; - bool (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe, - int *max_error, - ktime_t *vblank_time, - bool in_vblank_irq); - drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, (ktime_t *)NULL, 0); - kms_driver->get_vblank_timestamp = get_vblank_timestamp; - ], [ - AC_DEFINE(HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG, 1, - [drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg]) - AC_DEFINE(HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL, 1, - [drm_driver->get_scanout_position() return bool]) - ], [ - dnl # - dnl # v4.11-rc7-1902-g1bf6ad622b9b drm/vblank: drop the mode argument from drm_calc_vbltimestamp_from_scanoutpos - dnl # v4.11-rc7-1900-g3fcdcb270936 drm/vblank: Switch to bool in_vblank_irq in get_vblank_timestamp - dnl # v4.11-rc7-1899-gd673c02c4bdb drm/vblank: Switch drm_driver->get_vblank_timestamp to return a bool - dnl # - AC_KERNEL_TRY_COMPILE([ - struct vm_area_struct; - #include - ], [ - struct drm_driver *kms_driver = NULL; - bool (*get_scanout_position) (struct drm_device *dev, unsigned int pipe, - bool in_vblank_irq, int *vpos, int *hpos, - ktime_t *stime, ktime_t *etime, - const struct drm_display_mode *mode); - bool (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe, - int *max_error, - struct timeval *vblank_time, - bool in_vblank_irq); - kms_driver->get_scanout_position = get_scanout_position; - kms_driver->get_vblank_timestamp = get_vblank_timestamp; - drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, (struct timeval *)NULL, 0); - ], [ - AC_DEFINE(HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL, 1, - [drm_driver->get_scanout_position() return bool]) - AC_DEFINE(HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_RETURN_BOOL, 1, - [drm_driver->get_vblank_timestamp() return bool]) - ]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 2e19306272912..7d78d8122d1dc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -15,8 +15,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP], [ AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP, 1, [struct drm_crtc_funcs->get_vblank_timestamp() is available]) - ],[ - AC_AMDGPU_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS ]) ]) ]) From f96d4e93de47866c74653a6919b889115d13dc33 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 10 Feb 2023 13:35:49 +0800 Subject: [PATCH 0954/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_DRIVER_RELEASE Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 12 ---------- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 -- drivers/gpu/drm/amd/backport/kcl_drm_drv.c | 13 ----------- drivers/gpu/drm/amd/dkms/config/config.h | 6 ----- .../gpu/drm/amd/dkms/m4/drm-driver-release.m4 | 22 ------------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 8 files changed, 64 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 0b3a6a4b2fa1c..e62be5cd1293e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -956,11 +956,7 @@ enum amdgpu_enforce_isolation_mode { struct amdgpu_device { struct device *dev; struct pci_dev *pdev; -#ifdef HAVE_DRM_DRIVER_RELEASE struct drm_device ddev; -#else - struct drm_device *ddev; -#endif #ifdef CONFIG_DRM_AMD_ACP struct amdgpu_acp acp; @@ -1350,20 +1346,12 @@ static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) { -#ifdef HAVE_DRM_DRIVER_RELEASE return container_of(ddev, struct amdgpu_device, ddev); -#else - return ddev->dev_private; -#endif } static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) { -#ifdef HAVE_DRM_DRIVER_RELEASE return &adev->ddev; -#else - return adev->ddev; -#endif } static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 9ebaeaed3b3a0..80034943c0b39 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4884,11 +4884,7 @@ static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev) { /* Clear all CPU mappings pointing to this device */ -#ifdef HAVE_DRM_DRIVER_RELEASE unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1); -#else - unmap_mapping_range(adev->ddev->anon_inode->i_mapping, 0, 0, 1); -#endif /* Unmap all mapped bars - Doorbell, registers and VRAM */ amdgpu_doorbell_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index f4370360f4b19..a06f626b30233 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2577,7 +2577,6 @@ amdgpu_pci_remove(struct pci_dev *pdev) #endif } -#ifdef HAVE_DRM_DRIVER_RELEASE #ifndef HAVE_DRM_DRM_MANAGED_H static void amdgpu_driver_release(struct drm_device *ddev) { @@ -2587,7 +2586,6 @@ static void amdgpu_driver_release(struct drm_device *ddev) kfree(adev); } #endif -#endif static void amdgpu_pci_shutdown(struct pci_dev *pdev) @@ -3150,9 +3148,7 @@ static struct drm_driver amdgpu_kms_driver = { .dumb_map_offset = amdgpu_mode_dumb_mmap, DRM_FBDEV_TTM_DRIVER_OPS, .fops = &amdgpu_driver_kms_fops, -#ifdef HAVE_DRM_DRIVER_RELEASE .release = &amdgpu_driver_release_kms, -#endif #ifdef CONFIG_PROC_FS .show_fdinfo = amdgpu_show_fdinfo, #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 9225c63bb41de..7ed162e9fa22f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1584,7 +1584,6 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, pm_runtime_put_autosuspend(dev->dev); } -#ifdef HAVE_DRM_DRIVER_RELEASE void amdgpu_driver_release_kms(struct drm_device *dev) { struct amdgpu_device *adev = drm_to_adev(dev); @@ -1596,7 +1595,6 @@ void amdgpu_driver_release_kms(struct drm_device *dev) kfree(adev); #endif } -#endif /* * VBlank related functions. diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_drv.c b/drivers/gpu/drm/amd/backport/kcl_drm_drv.c index 9783e852192a5..0d243c59b5f6a 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_drv.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_drv.c @@ -41,7 +41,6 @@ void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, if (!container) return ERR_PTR(-ENOMEM); -#ifdef HAVE_DRM_DRIVER_RELEASE drm = container + offset; ret = drm_dev_init(drm, driver, parent); if (ret) { @@ -50,12 +49,6 @@ void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, } #ifdef HAVE_DRM_DRM_MANAGED_H drmm_add_final_kfree(drm, container); -#endif -#else - drm = drm_dev_alloc(driver, parent); - if (IS_ERR(drm)) - return PTR_ERR(drm); - ((struct amdgpu_device*)container)->ddev = drm; #endif drm->dev_private = container; return container; @@ -63,12 +56,6 @@ void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, void amdkcl_drm_dev_release(struct drm_device *ddev) { -#ifndef HAVE_DRM_DRIVER_RELEASE - if (ddev) { - kfree(drm_to_adev(ddev)); - ddev->dev_private = NULL; - } -#endif drm_dev_put(ddev); } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 327d660f20628..839000a6323fa 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -466,12 +466,6 @@ /* drm_vblank struct use ktime_t for time field */ #define HAVE_DRM_VBLANK_USE_KTIME_T 1 -/* drm_vblank->time is array */ -/* #undef HAVE_DRM_VBLANK_CRTC_HAS_ARRAY_TIME_FIELD */ - -/* drm_driver->release() is available */ -#define HAVE_DRM_DRIVER_RELEASE 1 - /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRMP_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 deleted file mode 100644 index 8d844a5d7124c..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 +++ /dev/null @@ -1,22 +0,0 @@ -dnl # -dnl # commit v4.10-rc5-1045-gf30c92576af4 -dnl # drm: Provide a driver hook for drm_dev_release() -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DRIVER_RELEASE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - struct vm_area_struct; - #ifdef HAVE_DRM_DRM_DRV_H - #include - #else - #include - #endif - ],[ - struct drm_driver *ddrv = NULL; - ddrv->release = NULL; - ],[ - AC_DEFINE(HAVE_DRM_DRIVER_RELEASE, 1, - [drm_driver->release() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0fa70bba4bd10..fc7d7fdd63a02 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -97,7 +97,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_EDID AC_AMDGPU_DRM_KMS_HELPER_IS_POLL_WORKER - AC_AMDGPU_DRM_DRIVER_RELEASE AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_MODE_INIT From f2725ec057a4828d1216202aeac788c5e6045126 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 13 Feb 2023 13:03:04 +0800 Subject: [PATCH 0955/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 8 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 3 -- drivers/gpu/drm/amd/backport/Makefile | 3 +- drivers/gpu/drm/amd/backport/backport.h | 1 - .../kcl_amdgpu_drm_gem_framebuffer_helper.h | 30 -------------- .../backport/kcl_drm_gem_framebuffer_helper.c | 40 ------------------- drivers/gpu/drm/amd/dkms/config/config.h | 10 ----- 8 files changed, 6 insertions(+), 91 deletions(-) delete mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h delete mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index fdcb021d2f537..fe57a4a593040 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1217,7 +1217,7 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev, struct drm_gem_object *obj) { int ret; - kcl_drm_gem_fb_set_obj(&rfb->base, 0, obj); + rfb->base.obj[0] = obj; drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); @@ -1231,7 +1231,7 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev, return 0; err: drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret); - kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); + rfb->base.obj[0] = NULL; return ret; } @@ -1243,7 +1243,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, { int ret; - kcl_drm_gem_fb_set_obj(&rfb->base, 0, obj); + rfb->base.obj[0] = obj; drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED @@ -1275,7 +1275,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, return 0; err: drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret); - kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); + rfb->base.obj[0] = NULL; return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 7aee5aeeecc91..1d531c41fa5e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -314,7 +314,7 @@ static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfb drm_gem_object_put(obj); #endif amdgpufb_destroy_pinned_object(obj); - kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); + rfb->base.obj[0] = NULL; drm_framebuffer_unregister_private(&rfb->base); drm_framebuffer_cleanup(&rfb->base); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 5c1b691abec39..8a02d2b6bec87 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -303,9 +303,6 @@ struct amdgpu_display_funcs { struct amdgpu_framebuffer { struct drm_framebuffer base; -#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H - struct drm_gem_object *obj; -#endif uint64_t tiling_flags; bool tmz_surface; diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index cba90812f73b2..335363b5b8ee5 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,7 +1,6 @@ # SPDX-License-Identifier: MIT BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ - kcl_drm_gem_framebuffer_helper.o kcl_drm_gem.o \ - kcl_drm_modeset_helper.o + kcl_drm_gem.o kcl_drm_modeset_helper.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index aa1fbf2145202..3200b99717ce1 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -71,7 +71,6 @@ #include #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" -#include "kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" #include "kcl/kcl_amdgpu_drm_gem.h" diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h deleted file mode 100644 index bbd3326b824bf..0000000000000 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_FRAMEBUFFER_HELPER_H__ -#define __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_FRAMEBUFFER_HELPER_H__ - -#include -#include "amdgpu.h" - -static inline -void kcl_drm_gem_fb_set_obj(struct drm_framebuffer *fb, int index, struct drm_gem_object *obj) -{ -#ifdef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H - if (fb) - fb->obj[index] = obj; -#else - struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); - (void)index; /* for compile un-used warning */ - if (afb) - afb->obj = obj; -#endif -} - -#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H -/* Copied from include/drm/drm_gem_framebuffer_helper.h */ -struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, - unsigned int plane); -void drm_gem_fb_destroy(struct drm_framebuffer *fb); -int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, - unsigned int *handle); -#endif - -#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c deleted file mode 100644 index 1f68cf8bbe2b3..0000000000000 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * drm gem framebuffer helper functions - * - * Copyright (C) 2017 Noralf Trønnes - */ - -#include - -/* Copied from drivers/gpu/drm/drm_gem_framebuffer_helper.c and modified for KCL */ -#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H -struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, - unsigned int plane) -{ - struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); - (void)plane; /* for compile un-used warning */ - if (afb) - return afb->obj; - else - return NULL; -} - -void drm_gem_fb_destroy(struct drm_framebuffer *fb) -{ - struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); - - drm_gem_object_put(amdgpu_fb->obj); - - drm_framebuffer_cleanup(fb); - kfree(fb); -} - -int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, - unsigned int *handle) -{ - struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); - - return drm_gem_handle_create(file, amdgpu_fb->obj, handle); -} -#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 839000a6323fa..a3bd15f4843bd 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -496,16 +496,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_DRV_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_ENCODER_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_FILE_H 1 - -/* Define to 1 if you have the header file. - */ -#define HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_HDCP_H 1 From c31afaaeecb31a96607462183eb96bb57b41f222 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 15 Feb 2023 10:01:02 +0800 Subject: [PATCH 0956/2653] drm/amdkcl: kcl-cleanup HAVE_UAPI_LINUX_SCHED_TYPES_H Change-Id: I48aec8289333a37f5cdce644fc3bdeef9e292872 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 ------ include/kcl/header/uapi/linux/sched/types.h | 9 --------- 3 files changed, 18 deletions(-) delete mode 100644 include/kcl/header/uapi/linux/sched/types.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a3bd15f4843bd..478750a214174 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1195,9 +1195,6 @@ /* __poll_t is available */ #define HAVE_TYPE__POLL_T 1 -/* Define to 1 if you have the header file. */ -#define HAVE_UAPI_LINUX_SCHED_TYPES_H 1 - /* vga_client_register() don't pass a cookie */ #define HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index c90bc2c7d2fd7..2c9f72c524583 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -25,12 +25,6 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([asm/fpu/api.h]) - dnl # - dnl # commit 607ca46e97a1b6594b29647d98a32d545c24bdff - dnl # UAPI: (Scripted) Disintegrate include/linux - dnl # - AC_KERNEL_CHECK_HEADERS([uapi/linux/sched/types.h]) - dnl # dnl # v4.19-rc6-7-ga3f8a30f3f00 dnl # Compiler Attributes: use feature checks instead of version checks diff --git a/include/kcl/header/uapi/linux/sched/types.h b/include/kcl/header/uapi/linux/sched/types.h deleted file mode 100644 index 871f2abf23d37..0000000000000 --- a/include/kcl/header/uapi/linux/sched/types.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER_UAPI_LINUX_SCHED_TYPES_H_H_ -#define _KCL_HEADER_UAPI_LINUX_SCHED_TYPES_H_H_ - -#ifdef HAVE_UAPI_LINUX_SCHED_TYPES_H -#include_next -#endif - -#endif From 84dfa115eaac9b445b8d611b789e30d50027ad46 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 15 Feb 2023 10:11:01 +0800 Subject: [PATCH 0957/2653] drm/amdkcl: kcl-cleanup HAVE_TTM_SG_TT_INIT Change-Id: Ib30a80618a524ae9f1b68ce8fdd7a73c87898204 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 | 11 ----------- drivers/gpu/drm/ttm/ttm_tt.c | 5 +---- include/kcl/kcl_drm_prime.h | 12 ------------ 5 files changed, 1 insertion(+), 31 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 478750a214174..4a7be829e0a04 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1189,9 +1189,6 @@ /* interval_tree_insert have struct rb_root_cached */ #define HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED 1 -/* ttm_sg_tt_init() is available */ -#define HAVE_TTM_SG_TT_INIT 1 - /* __poll_t is available */ #define HAVE_TYPE__POLL_T 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fc7d7fdd63a02..de834d9db3c16 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -50,7 +50,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_SCHED_SET_FIFO_LOW AC_AMDGPU_DMA_RESV - AC_AMDGPU_TTM_SG_TT_INIT AC_AMDGPU_TTM_BUFFER_OBJECT AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION AC_AMDGPU_HMM diff --git a/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 b/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 deleted file mode 100644 index 5cbf835eaf401..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 +++ /dev/null @@ -1,11 +0,0 @@ -dnl # -dnl # v4.16-rc1-1232-g75a57669cbc8 drm/ttm: add ttm_sg_tt_init -dnl # v4.16-rc1-409-g186ca446aea1 drm/prime: make the pages array optional for drm_prime_sg_to_page_addr_arrays -dnl # -AC_DEFUN([AC_AMDGPU_TTM_SG_TT_INIT], [ - AC_KERNEL_DO_BACKGROUND([ - AS_IF([grep -q ttm_sg_tt_init $LINUX/include/drm/ttm/ttm_tt.h > /dev/null 2>&1], [ - AC_DEFINE(HAVE_TTM_SG_TT_INIT, 1, [ttm_sg_tt_init() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 8772617d3f25f..210a27bd0aec3 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -214,14 +214,11 @@ int ttm_sg_tt_init(struct ttm_tt *ttm, struct ttm_buffer_object *bo, ttm_tt_init_fields(ttm, bo, page_flags, caching, 0); -#ifndef HAVE_TTM_SG_TT_INIT - ret = ttm_dma_tt_alloc_page_directory(ttm); -#else if (page_flags & TTM_TT_FLAG_EXTERNAL) ret = ttm_sg_tt_alloc_page_directory(ttm); else ret = ttm_dma_tt_alloc_page_directory(ttm); -#endif + if (ret) { pr_err("Failed allocating page table\n"); return -ENOMEM; diff --git a/include/kcl/kcl_drm_prime.h b/include/kcl/kcl_drm_prime.h index 2c5e972520576..c55e8d05c0318 100644 --- a/include/kcl/kcl_drm_prime.h +++ b/include/kcl/kcl_drm_prime.h @@ -12,19 +12,7 @@ static inline int drm_prime_sg_to_dma_addr_array(struct sg_table *sgt, dma_addr_t *addrs, int max_entries) { -#ifdef HAVE_TTM_SG_TT_INIT return drm_prime_sg_to_page_addr_arrays(sgt, NULL, addrs, max_entries); -#else - /* - * the page array stands right next to dma address array, - * so get the page array pointer directly by max_entries offset - * refer to ttm_sg_tt_init() for initial array allocation and - * c67e62790f5c drm/prime: split array import functions v4 for - * the change to drm_prime_sg_to_page_addr_arrays() - */ - struct page **pages = (void*)((unsigned long)addrs - max_entries*sizeof(dma_addr_t)); - return drm_prime_sg_to_page_addr_arrays(sgt, pages, addrs, max_entries); -#endif } #endif /* HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY */ #endif From 04b641087eeddcff745b2b09da6a0e0077e3dd13 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 15 Feb 2023 10:12:58 +0800 Subject: [PATCH 0958/2653] drm/amdkcl: kcl-cleanup HAVE_TIMER_SETUP Change-Id: Ib4c13dbfe337150f6bedb3c147692d7bbc04576b Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 14 -------------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 | 16 ---------------- 4 files changed, 34 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index ec0f26fed010a..d5f7c6a739d8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -291,7 +291,6 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring) * * Checks for fence activity. */ -#if defined(HAVE_TIMER_SETUP) static void amdgpu_fence_fallback(struct timer_list *t) { struct amdgpu_ring *ring = timer_container_of(ring, t, @@ -302,14 +301,6 @@ static void amdgpu_fence_fallback(struct timer_list *t) "Fence fallback timer expired on ring %s\n", ring->name); } -#else -static void amdgpu_fence_fallback(unsigned long arg) -{ - struct amdgpu_ring *ring = (void *)arg; - - amdgpu_fence_process(ring); -} -#endif /** * amdgpu_fence_wait_empty - wait for all fences to signal @@ -501,12 +492,7 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring) atomic_set(&ring->fence_drv.last_seq, 0); ring->fence_drv.initialized = false; -#if defined(HAVE_TIMER_SETUP) timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0); -#else - setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, - (unsigned long)ring); -#endif ring->fence_drv.num_fences_mask = ring->num_hw_submission * 2 - 1; spin_lock_init(&ring->fence_drv.lock); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4a7be829e0a04..da5821b104ac7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1183,9 +1183,6 @@ /* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 -/* timer_setup() is available */ -#define HAVE_TIMER_SETUP 1 - /* interval_tree_insert have struct rb_root_cached */ #define HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index de834d9db3c16..d072bfb9aa6cb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -60,7 +60,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_GET_USER_PAGES AC_AMDGPU_DMA_BUF AC_AMDGPU_LIST_FOR_EACH_ENTRY - AC_AMDGPU_TIMER_SETUP AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX AC_AMDGPU_DEV_PAGEMAP diff --git a/drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 b/drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 deleted file mode 100644 index 63a4498b7476a..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # timer_setup is available -dnl # -dnl # -AC_DEFUN([AC_AMDGPU_TIMER_SETUP], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - timer_setup(NULL, NULL, 0); - ],[ - AC_DEFINE(HAVE_TIMER_SETUP, 1, - [timer_setup() is available]) - ]) - ]) -]) From 9e8978cdbc3599cc9c50b299e8724ec755d03218 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 15 Feb 2023 11:32:01 +0800 Subject: [PATCH 0959/2653] drm/amdkcl: kcl-cleanup HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK Change-Id: I081d9f81f01145d5b7cf627acae3a621c3ac1d6a Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ---- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../dkms/m4/struct_drm_plane_helper_funcs.m4 | 19 ------------------- 3 files changed, 26 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index ee748e193b5bb..fbf9bd2c0bda8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1307,7 +1307,6 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, return -EINVAL; } -#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, #ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS struct drm_atomic_state *state, bool flip) @@ -1335,7 +1334,6 @@ static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, return 0; } -#endif int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, struct dc_cursor_position *position) @@ -1505,10 +1503,8 @@ static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { .prepare_fb = amdgpu_dm_plane_helper_prepare_fb, .cleanup_fb = amdgpu_dm_plane_helper_cleanup_fb, .atomic_check = amdgpu_dm_plane_atomic_check, -#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK .atomic_async_check = amdgpu_dm_plane_atomic_async_check, .atomic_async_update = amdgpu_dm_plane_atomic_async_update -#endif }; static const struct drm_plane_helper_funcs dm_primary_plane_helper_funcs = { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index da5821b104ac7..28264715502d5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1152,9 +1152,6 @@ /* drm_pending_vblank_event->sequence is available */ #define HAVE_STRUCT_DRM_PENDING_VBLANK_EVENT_SEQUENCE 1 -/* drm_plane_helper_funcs->atomic_async_check() is available */ -#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK 1 - /* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 index 59fe64ed86c35..495dd9ef97c12 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 @@ -1,22 +1,3 @@ -dnl # -dnl # v4.12-rc7-1335-gfef9df8b5945 -dnl # drm/atomic: initial support for asynchronous plane update -dnl # -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_plane_helper_funcs *funcs = NULL; - funcs->atomic_async_check(NULL, NULL); - funcs->atomic_async_update(NULL, NULL); - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK, 1, - [drm_plane_helper_funcs->atomic_async_check() is available]) - ]) - ]) -]) - dnl # commit v5.11-rc2-701-g7c11b99a8e58 dnl # drm/atomic: Pass the full state to planes atomic_check AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS], [ From 1672a0129a2ecd71758150f9e56e6e8de48c85ab Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 15 Feb 2023 14:20:50 +0800 Subject: [PATCH 0960/2653] drm/amdkcl: kcl-cleanup HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX Change-Id: I6117793d101c0b2321622d54dcbc3e1473b26efd Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 --------- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 ---- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 19 ------------------- 4 files changed, 35 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index fe57a4a593040..dbf7ab5b1eb6f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -309,13 +309,8 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, return r; } - -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX int amdgpu_display_crtc_set_config(struct drm_mode_set *set, struct drm_modeset_acquire_ctx *ctx) -#else -int amdgpu_display_crtc_set_config(struct drm_mode_set *set) -#endif { struct drm_device *dev; struct amdgpu_device *adev; @@ -332,11 +327,7 @@ int amdgpu_display_crtc_set_config(struct drm_mode_set *set) if (ret < 0) goto out; -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX ret = drm_crtc_helper_set_config(set, ctx); -#else - ret = drm_crtc_helper_set_config(set); -#endif list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) if (crtc->enabled) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 8a02d2b6bec87..e0d24f0069081 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -738,12 +738,8 @@ int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tile /* amdgpu_display.c */ void amdgpu_display_print_display_setup(struct drm_device *dev); int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX int amdgpu_display_crtc_set_config(struct drm_mode_set *set, struct drm_modeset_acquire_ctx *ctx); -#else -int amdgpu_display_crtc_set_config(struct drm_mode_set *set); -#endif int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, struct drm_framebuffer *fb, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 28264715502d5..0c60f7e2566bf 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1134,9 +1134,6 @@ /* drm_crtc_funcs->{get,verify}_crc_sources() is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES 1 -/* drm_crtc_funcs->set_config() wants ctx parameter */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX 1 - /* struct drm_crtc_state->async_flip is available */ #define HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 7d78d8122d1dc..facfeb5ef02a9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -19,24 +19,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP], [ ]) ]) -dnl # -dnl # v4.11-rc3-950-ga4eff9aa6db8 -dnl # drm: Add acquire ctx parameter to ->set_config -dnl # -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_crtc_funcs *funcs = NULL; - funcs->set_config(NULL, NULL); - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX, 1, - [drm_crtc_funcs->set_config() wants ctx parameter]) - ]) - ]) -]) - dnl # dnl # commit v4.10-rc5-1070-g84e354839b15 dnl # drm: add vblank hooks to struct drm_crtc_funcs @@ -92,6 +74,5 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES - AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL ]) From 20c9f411dd431a971102e0703a0dff1d4a8717f0 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 16 Feb 2023 13:40:47 +0800 Subject: [PATCH 0961/2653] drm/amdkcl: kcl-cleanup HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES Change-Id: Ie8e3067682507105f6e50038cc539614b5dcdab0 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 -- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 4 ---- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 2 -- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 -- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 22 ------------------- 6 files changed, 35 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 332098fda7085..83e3e07fe8cc9 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -669,9 +669,7 @@ static void dm_crtc_high_irq(void *interrupt_params) * Following stuff must happen at start of vblank, for crc * computation and below-the-range btr support in vrr mode. */ -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); -#endif /* BTR updates need to happen before VUPDATE on Vega and above. */ if (adev->family < AMDGPU_FAMILY_AI) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index a720908068a9d..e20aa74380665 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -33,7 +33,6 @@ #include "amdgpu_securedisplay.h" #include "amdgpu_dm_psr.h" -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES static const char *const pipe_crc_sources[] = { "none", "crtc", @@ -42,7 +41,6 @@ static const char *const pipe_crc_sources[] = { "dprx dither", "auto", }; -#endif static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source) { @@ -79,7 +77,6 @@ static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src) (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE); } -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, size_t *count) { @@ -496,7 +493,6 @@ amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, *values_cnt = 3; return 0; } -#endif int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, struct dm_crtc_state *dm_crtc_state, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h index 23c4afe44522e..040d053da1b02 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h @@ -127,13 +127,11 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, enum amdgpu_dm_pipe_crc_source source); int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name); -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, size_t *values_cnt); const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, size_t *count); -#endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES */ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); #else #define amdgpu_dm_crtc_set_crc_source NULL diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 633d6192bdac2..6014b0bcad702 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -548,10 +548,8 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state, .atomic_destroy_state = amdgpu_dm_crtc_destroy_state, .set_crc_source = amdgpu_dm_crtc_set_crc_source, -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, -#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK .enable_vblank = amdgpu_dm_crtc_enable_vblank, .disable_vblank = amdgpu_dm_crtc_disable_vblank, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0c60f7e2566bf..647fb3321c8ab 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1131,9 +1131,6 @@ /* struct drm_crtc_funcs->get_vblank_timestamp() is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP 1 -/* drm_crtc_funcs->{get,verify}_crc_sources() is available */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES 1 - /* struct drm_crtc_state->async_flip is available */ #define HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index facfeb5ef02a9..747ec89036bd4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -37,27 +37,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK], [ ]) ]) -dnl # -dnl # v5.2-rc5-2034-g8fb843d179a6 drm/amd/display: add functionality to get pipe CRC source. -dnl # v4.18-rc3-759-g3b3b8448ebd1 drm/amdgpu_dm/crc: Implement verify_crc_source callback -dnl # v4.18-rc3-757-g4396551e9cf3 drm: crc: Introduce get_crc_sources callback -dnl # v4.18-rc3-756-gd5cc15a0c66e drm: crc: Introduce verify_crc_source callback -dnl # -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_crtc_funcs *crtc_funcs = NULL; - crtc_funcs->get_crc_sources(NULL, NULL); - crtc_funcs->verify_crc_source(NULL, NULL, NULL); - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES, 1, [ - drm_crtc_funcs->{get,verify}_crc_sources() is available]) - ]) - ]) -]) - dnl # dnl # v5.10-1961-g6ca2ab8086af drm: automatic legacy gamma support dnl # @@ -73,6 +52,5 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL], [ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK - AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL ]) From 41b1d61ee0206b88fd0527fb587fd1bc8f35c277 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 16 Feb 2023 13:42:14 +0800 Subject: [PATCH 0962/2653] drm/amdkcl: kcl-cleanup HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK Change-Id: If26eecc53b7d105cd064e69ad7a54f93b1f4f267 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 -- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 19 ------------------- 3 files changed, 24 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 6014b0bcad702..b9abdd6ca06c7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -550,10 +550,8 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .set_crc_source = amdgpu_dm_crtc_set_crc_source, .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK .enable_vblank = amdgpu_dm_crtc_enable_vblank, .disable_vblank = amdgpu_dm_crtc_disable_vblank, -#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 647fb3321c8ab..7849a8d199f39 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1122,9 +1122,6 @@ /* drm_connector->ycbcr_420_allowed is available */ #define HAVE_STRUCT_DRM_CONNECTOR_YCBCR_420_ALLOWED 1 -/* drm_crtc_funcs->enable_vblank() is available */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK 1 - /* HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 747ec89036bd4..8ad24bc40f5fb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -19,24 +19,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP], [ ]) ]) -dnl # -dnl # commit v4.10-rc5-1070-g84e354839b15 -dnl # drm: add vblank hooks to struct drm_crtc_funcs -dnl # -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_crtc_funcs *crtc_funcs = NULL; - crtc_funcs->enable_vblank(NULL); - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK, 1, [ - drm_crtc_funcs->enable_vblank() is available]) - ]) - ]) -]) - dnl # dnl # v5.10-1961-g6ca2ab8086af drm: automatic legacy gamma support dnl # @@ -51,6 +33,5 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL], [ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP - AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL ]) From 99d19d9b84e4482ec5b9bd82823e6934ccb45ae5 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 16 Feb 2023 13:44:58 +0800 Subject: [PATCH 0963/2653] drm/amdkcl: kcl-cleanup HAVE_STRSCPY Change-Id: I8eb0e883ffb1241a4fcea40aa02d0b7dea9b4bdf Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +---------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/strscpy.m4 | 17 ----------------- 4 files changed, 1 insertion(+), 31 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/strscpy.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 83e3e07fe8cc9..3ff5bc2bb8db7 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6531,15 +6531,9 @@ static void fill_audio_info(struct audio_info *audio_info, cea_revision = drm_connector->display_info.cea_rev; -#if !defined(HAVE_STRSCPY) - strncpy(audio_info->display_name, - edid_caps->display_name, - AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1); -#else strscpy(audio_info->display_name, edid_caps->display_name, AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); -#endif if (cea_revision >= 3) { audio_info->mode_count = edid_caps->audio_mode_count; @@ -8255,11 +8249,8 @@ amdgpu_dm_create_common_mode(struct drm_encoder *encoder, mode->hdisplay = hdisplay; mode->vdisplay = vdisplay; mode->type &= ~DRM_MODE_TYPE_PREFERRED; -#if !defined(HAVE_STRSCPY) - strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN); -#else + strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); -#endif return mode; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7849a8d199f39..53017b5d7e65d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1092,9 +1092,6 @@ /* is_smca_umc_v2() is available */ /* #undef HAVE_SMCA_UMC_V2 */ -/* strscpy() is available */ -#define HAVE_STRSCPY 1 - /* struct dma_buf_ops->allow_peer2peer is available */ #define HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d072bfb9aa6cb..b5b1895356b0d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -99,7 +99,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_MODE_INIT AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT - AC_AMDGPU_STRSCPY AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS diff --git a/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 b/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 deleted file mode 100644 index 35ace5a7694c7..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 +++ /dev/null @@ -1,17 +0,0 @@ -dnl # -dnl # commit 30035e45753b708e7d47a98398500ca005e02b86 -dnl # Author: Chris Metcalf -dnl # Date: Wed Apr 29 12:52:04 2015 -0400 -dnl # string: provide strscpy() -dnl # -AC_DEFUN([AC_AMDGPU_STRSCPY], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - strscpy(NULL, NULL, 8); - ], [strscpy], [lib/string.c], [ - AC_DEFINE(HAVE_STRSCPY, 1, [strscpy() is available]) - ]) - ]) -]) From ac0e8559eb4db3b5f602e6f5dc22fd1df9e31a72 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 16 Feb 2023 15:14:08 +0800 Subject: [PATCH 0964/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/dkms/config/config.h | 3 -- .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 30 +++---------------- .../backport/kcl_drm_dp_mst_helper_backport.h | 2 -- 3 files changed, 4 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 53017b5d7e65d..ce918a175fb6b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -361,9 +361,6 @@ /* drm_dp_mst_atomic_wait_for_dependencies() is available */ /* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ -/* drm_dp_atomic_find_vcpi_slots() is available */ -#define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 - /* drm_dp_atomic_release_time_slots() is available */ /* #undef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index f19d5bf4ea976..c89bcdbf10edd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -4,7 +4,7 @@ dnl # drm/dp: Add DP MST helpers to atomically find and release vcpi slots dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ + AC_KERNEL_TRY_COMPILE([ #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) #include #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) @@ -14,32 +14,10 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ #endif ], [ int retval; - retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0); - ], [drm_dp_atomic_find_vcpi_slots], [drivers/gpu/drm/drm_dp_mst_topology.c], [ - AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS, 1, - [drm_dp_atomic_find_vcpi_slots() is available]) + retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0, 0); ], [ - dnl # - dnl # commit dad1c2499a8f6d7ee01db8148f05ebba73cc41bd - dnl # drm/dp_mst: Manually overwrite PBN divider for calculating timeslots - dnl # - AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else - #include - #endif - ], [ - int retval; - retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0, 0); - ], [ - AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS, 1, - [drm_dp_atomic_find_vcpi_slots() wants 5args]) - AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS, 1, - [drm_dp_atomic_find_vcpi_slots() is available]) - ]) + AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS, 1, + [drm_dp_atomic_find_vcpi_slots() wants 5args]) ]) ]) ]) diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index edac58606beb9..97af03bd3e628 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -38,7 +38,6 @@ int _kcl_drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) #define drm_dp_calc_pbn_mode _kcl_drm_dp_calc_pbn_mode #endif -#if defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS) #if !defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS) static inline int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, @@ -63,7 +62,6 @@ int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, } #define drm_dp_atomic_find_vcpi_slots _kcl_drm_dp_atomic_find_vcpi_slots #endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ -#endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS */ #if !defined(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS) static inline From e8dbe0baa4ab52b7450414708b2d6dbec0794460 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 20 Feb 2023 15:35:34 +0800 Subject: [PATCH 0965/2653] drm/amdkcl: Fix the "array-bound" warning info when compile conftest.c There is a bug in gcc12 which caused the warning info below: "array subscript 0 is outside array bounds of 'atomic_t[0]' [-Werror=array-bounds]" To fix this issue, we add "-Wno-error=array-bounds" to ingore this warning. The same problem in the kernel has been fixed by the following patch: f0be87c42cbd gcc-12: disable '-Warray-bounds' universally for now Change-Id: If810c289579311bb0aafd43d2045e965dd710052 Signed-off-by: Ma Jun Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b5b1895356b0d..4becf50942192 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -418,7 +418,7 @@ AC_DEFUN([AC_KERNEL_COMPILE_MODULE_IFELSE], [ test "x$enable_linux_builtin" = xyes && kbuild_src_flag='KBUILD_SRC=' # override KBUILD_SRC test "x$enable_linux_builtin" = xyes && kbuild_workaround_flag='sub_make_done=' # override sub_make_done AS_IF( - [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=uninitialized -Wno-error=unused-variable" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], + [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=uninitialized -Wno-error=unused-variable -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], [$4], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] ) From a166d04345bb8c7a8ec3c4e10ca17aadb1a9b736 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 1 Mar 2023 17:30:47 +0800 Subject: [PATCH 0966/2653] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To remove following compiling warning, wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS. /var/lib/dkms/amdgpu-pro/1.0/build/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.c: In function ‘dm_helpers_dp_mst_send_payload_allocation’: /var/lib/dkms/amdgpu-pro/1.0/build/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.c:460:13: warning: unused variable ‘ret’ [-Wunused-variable] 460 | int ret = 0; | ^~~ Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index a7ae4a866d83b..73bf37387a935 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -548,7 +548,9 @@ void dm_helpers_dp_mst_send_payload_allocation( struct drm_dp_mst_topology_mgr *mst_mgr; enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) int ret = 0; +#endif aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; From 1013110bed96094ddb296846c12b13843707e26f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 7 Mar 2023 09:36:24 +0800 Subject: [PATCH 0967/2653] drm/amdkcl: wrap code under macro RB_ROOT_CACHED Signed-off-by: Asher Song --- include/kcl/kcl_rbtree.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_rbtree.h b/include/kcl/kcl_rbtree.h index 6d3bf91f7b4f9..6a0f687a0801e 100644 --- a/include/kcl/kcl_rbtree.h +++ b/include/kcl/kcl_rbtree.h @@ -4,7 +4,7 @@ #include -#ifndef HAVE_RB_ROOT_CACHED +#ifndef RB_ROOT_CACHED /* * Leftmost-cached rbtrees. * From 006ab9293ad5866e030cac2526b1097d9f9635ee Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 10 Aug 2022 18:53:07 -0400 Subject: [PATCH 0968/2653] drm/amdkfd: Try to schedule bottom half on same core On systems that support SMT (hyperthreading) schedule the bottom half of the KFD interrupt handler on the same core. This makes it possible to reserve a core for interrupt handling and have the bottom half run on that same core. On systems without SMT, pick another core in the same NUMA node, as before. Use for_each_cpu_wrap instead of open-coding it. Signed-off-by: Felix Kuehling Reviewed-by: Philip Yang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index a4f073969c55e..41b2a353c57d9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "kfd_priv.h" #include "kfd_device_queue_manager.h" #include "kfd_pm4_headers_vi.h" From c134826ab8db5cdb7e2757d3c52b64f71c39aad0 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 16 Feb 2023 14:39:55 +0800 Subject: [PATCH 0969/2653] drm/amdkcl: kcl-cleanup HAVE_RESERVATION_OBJECT_STAGED Change-Id: I7e226cc12719abd32970d33c08eaa965db50190b Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_reservation.c | 153 +------------------ drivers/gpu/drm/amd/dkms/config/config.h | 3 - drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 22 --- include/kcl/kcl_dma-resv.h | 9 -- include/kcl/reservation.h | 17 --- 5 files changed, 1 insertion(+), 203 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c index bad215a62e54d..e1b018386c601 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c @@ -37,155 +37,4 @@ void amdkcl_reservation_init(void) { amdkcl_fp_setup("reservation_ww_class", NULL); -} - -#if defined(HAVE_RESERVATION_OBJECT_STAGED) -/* - * Copied from v4.19-rc6-1514-g27836b641c1b^:drivers/dma-buf/reservation.c - * and modified for KCL - */ -static void -reservation_object_add_shared_inplace(struct reservation_object *obj, - struct reservation_object_list *fobj, - struct dma_fence *fence) -{ - struct dma_fence *signaled = NULL; - u32 i, signaled_idx; - - dma_fence_get(fence); - - preempt_disable(); - write_seqcount_begin(&obj->seq); - - for (i = 0; i < fobj->shared_count; ++i) { - struct dma_fence *old_fence; - - old_fence = rcu_dereference_protected(fobj->shared[i], - dma_resv_held(obj)); - - if (old_fence->context == fence->context) { - /* memory barrier is added by write_seqcount_begin */ - RCU_INIT_POINTER(fobj->shared[i], fence); - write_seqcount_end(&obj->seq); - preempt_enable(); - - dma_fence_put(old_fence); - return; - } - - if (!signaled && dma_fence_is_signaled(old_fence)) { - signaled = old_fence; - signaled_idx = i; - } - } - - /* - * memory barrier is added by write_seqcount_begin, - * fobj->shared_count is protected by this lock too - */ - if (signaled) { - RCU_INIT_POINTER(fobj->shared[signaled_idx], fence); - } else { - BUG_ON(fobj->shared_count >= fobj->shared_max); - RCU_INIT_POINTER(fobj->shared[fobj->shared_count], fence); - fobj->shared_count++; - } - - write_seqcount_end(&obj->seq); - preempt_enable(); - - dma_fence_put(signaled); -} - -static void -reservation_object_add_shared_replace(struct reservation_object *obj, - struct reservation_object_list *old, - struct reservation_object_list *fobj, - struct dma_fence *fence) -{ - unsigned i, j, k; - - dma_fence_get(fence); - - if (!old) { - RCU_INIT_POINTER(fobj->shared[0], fence); - fobj->shared_count = 1; - goto done; - } - - /* - * no need to bump fence refcounts, rcu_read access - * requires the use of kref_get_unless_zero, and the - * references from the old struct are carried over to - * the new. - */ - for (i = 0, j = 0, k = fobj->shared_max; i < old->shared_count; ++i) { - struct dma_fence *check; - - check = rcu_dereference_protected(old->shared[i], - dma_resv_held(obj)); - - if (check->context == fence->context || - dma_fence_is_signaled(check)) - RCU_INIT_POINTER(fobj->shared[--k], check); - else - RCU_INIT_POINTER(fobj->shared[j++], check); - } - fobj->shared_count = j; - RCU_INIT_POINTER(fobj->shared[fobj->shared_count], fence); - fobj->shared_count++; - -done: - preempt_disable(); - write_seqcount_begin(&obj->seq); - /* - * RCU_INIT_POINTER can be used here, - * seqcount provides the necessary barriers - */ - RCU_INIT_POINTER(obj->fence, fobj); - write_seqcount_end(&obj->seq); - preempt_enable(); - - if (!old) - return; - - /* Drop the references to the signaled fences */ - for (i = k; i < fobj->shared_max; ++i) { - struct dma_fence *f; - - f = rcu_dereference_protected(fobj->shared[i], - dma_resv_held(obj)); - dma_fence_put(f); - } - kfree_rcu(old, rcu); -} - -void _kcl_dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fence) -{ - struct dma_resv_list *old, *fobj = obj->staged; - - old = dma_resv_shared_list(obj); - obj->staged = NULL; - - if (!fobj) - reservation_object_add_shared_inplace(obj, old, fence); - else - reservation_object_add_shared_replace(obj, old, fobj, fence); -} -EXPORT_SYMBOL(_kcl_dma_resv_add_shared_fence); - -int _kcl_dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src) -{ - int ret; - - ret = dma_resv_copy_fences(dst, src); - if (ret) - return ret; - - kfree(dst->staged); - dst->staged = NULL; - - return ret; -} -EXPORT_SYMBOL(_kcl_dma_resv_copy_fences); -#endif +} \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ce918a175fb6b..c954718059f45 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1065,9 +1065,6 @@ /* request_firmware_direct() is available */ #define HAVE_REQUEST_FIRMWARE_DIRECT 1 -/* reservation_object->staged is available */ -/* #undef HAVE_RESERVATION_OBJECT_STAGED */ - /* sched_set_fifo_low() is available */ #define HAVE_SCHED_SET_FIFO_LOW 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index f65379d76636f..baeb0ee766979 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -56,28 +56,6 @@ AC_DEFUN([AC_AMDGPU_DMA_RESV_FENCES], [ ]) ]) - -dnl # -dnl # v4.19-rc6-1514-g27836b641c1b -dnl # dma-buf: remove shared fence staging in reservation object -dnl # -AC_DEFUN([AC_AMDGPU_RESERVATION_OBJECT_STAGED], [ - AC_KERNEL_DO_BACKGROUND([ - AS_IF([test x$HAVE_LINUX_DMA_RESV_H = x ], [ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct reservation_object *resv = NULL; - resv->staged = NULL; - ], [ - AC_DEFINE(HAVE_RESERVATION_OBJECT_STAGED, 1, - [reservation_object->staged is available]) - ]) - ]) - ]) -]) - AC_DEFUN([AC_AMDGPU_DMA_RESV], [ AC_AMDGPU_DMA_RESV_FENCES - AC_AMDGPU_RESERVATION_OBJECT_STAGED ]) diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index a6b8ab359aa0d..4c2b2576374ed 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -187,15 +187,6 @@ struct dma_resv { struct dma_fence __rcu *fence_excl; struct dma_resv_list __rcu *fence; }; -#elif defined(HAVE_RESERVATION_OBJECT_STAGED) -struct dma_resv { - struct ww_mutex lock; - seqcount_t seq; - - struct dma_fence __rcu *fence_excl; - struct dma_resv_list __rcu *fence; - struct dma_resv_list *staged; -}; #else struct dma_resv { struct ww_mutex lock; diff --git a/include/kcl/reservation.h b/include/kcl/reservation.h index fbd036fdd650d..8dcc5e3c18479 100644 --- a/include/kcl/reservation.h +++ b/include/kcl/reservation.h @@ -4,23 +4,6 @@ #ifndef HAVE_LINUX_DMA_RESV_H #include - -#if defined(HAVE_RESERVATION_OBJECT_STAGED) -static inline void -_kcl_reservation_object_fini(struct reservation_object *obj) -{ - dma_resv_fini(obj); - kfree(obj->staged); -} -#define amddma_resv_fini _kcl_reservation_object_fini - -void _kcl_dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fence); -#define amddma_resv_add_shared_fence _kcl_dma_resv_add_shared_fence - -int _kcl_dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src); -#define amddma_resv_copy_fences _kcl_dma_resv_copy_fences - -#endif /* HAVE_RESERVATION_OBJECT_STAGED */ #endif /* HAVE_LINUX_DMA_RESV_H */ #endif From 02f103463a80b332a8499b255a6bdd527922263e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 16 Feb 2023 15:52:24 +0800 Subject: [PATCH 0970/2653] drm/amdkcl: kcl-cleanup HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS Also removed HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP Change-Id: Ic77c42f0aebab15c6efece839c0ad7796ab1acf8 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 41 ------------------- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h | 12 ++---- drivers/gpu/drm/amd/dkms/config/config.h | 6 --- ...ure_remove_conflicting_pci_framebuffers.m4 | 17 -------- 4 files changed, 3 insertions(+), 73 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c index ce1cdaad500a0..920cf50033339 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -13,47 +13,6 @@ #include -/* Copied from drivers/video/fbdev/core/fbmem.c and modified for KCL */ -#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) && \ - !defined(HAVE_DRM_DRM_APERTURE_H) -int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) -{ - struct apertures_struct *ap; - bool primary = false; - int err, idx, bar; - - for (idx = 0, bar = 0; bar < PCI_ROM_RESOURCE; bar++) { - if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) - continue; - idx++; - } - - ap = alloc_apertures(idx); - if (!ap) - return -ENOMEM; - - for (idx = 0, bar = 0; bar < PCI_ROM_RESOURCE; bar++) { - if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) - continue; - ap->ranges[idx].base = pci_resource_start(pdev, bar); - ap->ranges[idx].size = pci_resource_len(pdev, bar); - dev_dbg(&pdev->dev, "%s: bar %d: 0x%lx -> 0x%lx\n", __func__, bar, - (unsigned long)pci_resource_start(pdev, bar), - (unsigned long)pci_resource_end(pdev, bar)); - idx++; - } - -#ifdef CONFIG_X86 - primary = pdev->resource[PCI_ROM_RESOURCE].flags & - IORESOURCE_ROM_SHADOW; -#endif - err = remove_conflicting_framebuffers(ap, name, primary); - kfree(ap); - return err; -} -EXPORT_SYMBOL(remove_conflicting_pci_framebuffers); -#endif - #ifndef HAVE_IS_FIRMWARE_FRAMEBUFFER bool is_firmware_framebuffer(struct apertures_struct *a) { diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h index b734ca7c3d36a..5275dfcb6b6ca 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h @@ -5,17 +5,13 @@ #include #include -/* Copied from include/linux/fb.h */ -#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) && \ - !defined(HAVE_DRM_DRM_APERTURE_H) -extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, - const char *name); -#endif static inline int _kcl_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) { -#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP + return remove_conflicting_pci_framebuffers(pdev, name); +#else /** * v5.1-rc3-20-gb0e999c95581 fbdev: list all pci memory bars as conflicting apertures * handle bar 0 directly. @@ -32,8 +28,6 @@ int _kcl_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, */ pr_warn_once("remove conflicting pci framebuffers on bar 0\n"); return remove_conflicting_pci_framebuffers(pdev, 0, name); -#else - return remove_conflicting_pci_framebuffers(pdev, name); #endif } #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c954718059f45..61418cce19b4d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1053,12 +1053,6 @@ /* whether register_shrinker(x, x) is available */ #define HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS 1 -/* remove_conflicting_pci_framebuffers() is available */ -/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ - -/* remove_conflicting_pci_framebuffers() wants p,i,p args */ -/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP */ - /* remove_conflicting_pci_framebuffers() wants p,p args */ /* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 index 87f2f1c951581..f4c7be22ebded 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 @@ -16,23 +16,6 @@ AC_DEFUN([AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ ], [ AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, [remove_conflicting_pci_framebuffers() wants p,p args]) - AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, - [remove_conflicting_pci_framebuffers() is available]) - ], [ - dnl # - dnl # v4.19-rc1-110-g4d18975c78f2 fbdev: add remove_conflicting_pci_framebuffers() - dnl # - AC_KERNEL_TRY_COMPILE([ - struct task_struct; - #include - ], [ - remove_conflicting_pci_framebuffers(NULL, 0, NULL); - ], [ - AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP, 1, - [remove_conflicting_pci_framebuffers() wants p,i,p args]) - AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, - [remove_conflicting_pci_framebuffers() is available]) - ]) ]) ]) ]) From 978f7cafbe94efe691ab3584cf1074b7d1c96810 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 16 Feb 2023 15:52:55 +0800 Subject: [PATCH 0971/2653] drm/amdkcl: kcl-cleanup HAVE_PERF_EVENT_UPDATE_USERPAGE Change-Id: I44c5c04cbfb658c2faa84945e832fc5da5ebb3d6 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c | 23 ------------------- drivers/gpu/drm/amd/amdkcl/main.c | 2 -- drivers/gpu/drm/amd/backport/backport.h | 1 - drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../amd/dkms/m4/perf-event-update-userpage.m4 | 14 ----------- .../kcl/backport/kcl_perf_event_backport.h | 10 -------- 8 files changed, 1 insertion(+), 55 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/perf-event-update-userpage.m4 delete mode 100644 include/kcl/backport/kcl_perf_event_backport.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index eb1682f507b91..0f953fafc56ab 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -5,7 +5,7 @@ amdkcl-y += kcl_kernel_params.o amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ - kcl_kthread.o kcl_io.o kcl_perf_event.o kcl_seq_file.o \ + kcl_kthread.o kcl_io.o kcl_seq_file.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ kcl_fence.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c b/drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c deleted file mode 100644 index 8c7914b6ff67d..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Performance events core code: - * - * Copyright (C) 2008 Thomas Gleixner - * Copyright (C) 2008-2011 Red Hat, Inc., Ingo Molnar - * Copyright (C) 2008-2011 Red Hat, Inc., Peter Zijlstra - * Copyright © 2009 Paul Mackerras, IBM Corp. - */ -#include - -#if !defined(HAVE_PERF_EVENT_UPDATE_USERPAGE) -void (*_kcl_perf_event_update_userpage)(struct perf_event *event); -EXPORT_SYMBOL(_kcl_perf_event_update_userpage); -#endif - -void amdkcl_perf_event_init(void) -{ -#if !defined(HAVE_PERF_EVENT_UPDATE_USERPAGE) - _kcl_perf_event_update_userpage = amdkcl_fp_setup("perf_event_update_userpage", NULL); -#endif -} - diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 58c46b4f04ae5..b4c76ba82d292 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -8,7 +8,6 @@ extern void amdkcl_fence_init(void); extern void amdkcl_reservation_init(void); extern void amdkcl_io_init(void); extern void amdkcl_mm_init(void); -extern void amdkcl_perf_event_init(void); extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); extern void amdkcl_sched_init(void); @@ -23,7 +22,6 @@ int __init amdkcl_init(void) amdkcl_reservation_init(); amdkcl_io_init(); amdkcl_mm_init(); - amdkcl_perf_event_init(); amdkcl_pci_init(); amdkcl_suspend_init(); amdkcl_sched_init(); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 3200b99717ce1..109b65af58cf6 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 61418cce19b4d..1859c70e94fe2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1026,9 +1026,6 @@ /* pci_upstream_bridge() is available */ #define HAVE_PCI_UPSTREAM_BRIDGE 1 -/* perf_event_update_userpage() is exported */ -#define HAVE_PERF_EVENT_UPDATE_USERPAGE 1 - /* pfn_t is defined */ #define HAVE_PFN_T 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4becf50942192..3a13b25052a2f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -24,7 +24,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS AC_AMDGPU_IN_COMPAT_SYSCALL - AC_AMDGPU_PERF_EVENT_UPDATE_USERPAGE AC_AMDGPU_SEQ_HEX_DUMP AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP diff --git a/drivers/gpu/drm/amd/dkms/m4/perf-event-update-userpage.m4 b/drivers/gpu/drm/amd/dkms/m4/perf-event-update-userpage.m4 deleted file mode 100644 index bf52b37b31d84..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/perf-event-update-userpage.m4 +++ /dev/null @@ -1,14 +0,0 @@ -dnl # -dnl # commit v4.15-rc3-1-g82975c46da82 -dnl # perf: Export perf_event_update_userpage -dnl # Export perf_event_update_userpage() so that PMU driver using them, -dnl # can be built as modules -dnl # -AC_DEFUN([AC_AMDGPU_PERF_EVENT_UPDATE_USERPAGE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([perf_event_update_userpage],[kernel/events/core.c],[ - AC_DEFINE(HAVE_PERF_EVENT_UPDATE_USERPAGE, 1, - [perf_event_update_userpage() is exported]) - ]) - ]) -]) diff --git a/include/kcl/backport/kcl_perf_event_backport.h b/include/kcl/backport/kcl_perf_event_backport.h deleted file mode 100644 index 41f336d7039a7..0000000000000 --- a/include/kcl/backport/kcl_perf_event_backport.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef AMD_KCL_PERF_EVENT_BACKPORT_H -#define AMD_KCL_PERF_EVENT_BACKPORT_H -#include -#include - -#if !defined(HAVE_PERF_EVENT_UPDATE_USERPAGE) -#define perf_event_update_userpage _kcl_perf_event_update_userpage -#endif -#endif From 15600643c70c6edcc52f3628c3c0ace3feeda460 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 16 Feb 2023 16:02:53 +0800 Subject: [PATCH 0972/2653] drm/amdkcl: kcl-cleanup HAVE_PCI_IRQ_VECTOR Change-Id: I6295c98fa61a0c09945ffe1af3491549a1235979 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 | 16 ---------------- include/kcl/kcl_pci.h | 9 --------- 4 files changed, 29 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1859c70e94fe2..0884c116da9ed 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1011,9 +1011,6 @@ /* struct pci_driver has field dev_groups */ #define HAVE_PCI_DRIVER_DEV_GROUPS 1 -/* pci_irq_vector() is available */ -#define HAVE_PCI_IRQ_VECTOR 1 - /* pci_is_thunderbolt_attached() is available */ #define HAVE_PCI_IS_THUNDERBOLD_ATTACHED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3a13b25052a2f..3e7f141e1a332 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -175,7 +175,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ AC_AMDGPU__DMA_FENCE_IS_LATER - AC_AMDGPU_PCI_IRQ_VECTOR AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY AC_AMDGPU_DMA_FENCE_DESCRIBE AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 deleted file mode 100644 index 5567ed9920070..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # v4.7-rc6-10-gaff171641d18 -dnl # PCI: Provide sensible IRQ vector alloc/free routines -dnl # -AC_DEFUN([AC_AMDGPU_PCI_IRQ_VECTOR], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - pci_irq_vector(NULL, 0); - ], [ - AC_DEFINE(HAVE_PCI_IRQ_VECTOR, 1, - [pci_irq_vector() is available]) - ]) - ]) -]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index cf46e2db8d19b..f10e5e5c84106 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -241,13 +241,4 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) #endif /* PCI_REBAR_CTRL_BAR_SHIFT */ -#if !defined(HAVE_PCI_IRQ_VECTOR) -static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) -{ - if (WARN_ON_ONCE(nr > 0)) - return -EINVAL; - return dev->irq; -} -#endif /* HAVE_PCI_IRQ_VECTOR */ - #endif /* AMDKCL_PCI_H */ From e58ef1b7a4d47f3f83f459c3b9dcf083032677cd Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Feb 2023 14:10:18 +0800 Subject: [PATCH 0973/2653] drm/amdkcl: kcl-cleanup HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP Change-Id: I6e00c1b00b4640cbc0cf29649845d736a00e572c Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 68 ------------------- drivers/gpu/drm/amd/dkms/config/config.h | 3 - drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../amd/dkms/m4/pcie-get-speed-width-cap.m4 | 12 ---- include/kcl/backport/kcl_pci_backport.h | 4 -- include/kcl/kcl_pci.h | 13 ---- 6 files changed, 101 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index 42ca0b4a36945..e334a99db43b9 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -104,70 +104,6 @@ u32 _kcl_pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting EXPORT_SYMBOL(_kcl_pcie_bandwidth_available); #endif /* HAVE_PCIE_BANDWIDTH_AVAILABLE */ -#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) -/* - * pcie_get_speed_cap - query for the PCI device's link speed capability - * @dev: PCI device to query - * - * Query the PCI device speed capability. Return the maximum link speed - * supported by the device. - */ -enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) -{ - u32 lnkcap2, lnkcap; - - /* - * PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link - * Speeds Vector in Link Capabilities 2 when supported, falling - * back to Max Link Speed in Link Capabilities otherwise. - */ - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); - if (lnkcap2) { /* PCIe r3.0-compliant */ - if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) - return PCIE_SPEED_16_0GT; - else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) - return PCIE_SPEED_8_0GT; - else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) - return PCIE_SPEED_5_0GT; - else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) - return PCIE_SPEED_2_5GT; - return PCI_SPEED_UNKNOWN; - } - - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); - if (lnkcap) { - if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) - return PCIE_SPEED_16_0GT; - else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) - return PCIE_SPEED_8_0GT; - else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) - return PCIE_SPEED_5_0GT; - else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) - return PCIE_SPEED_2_5GT; - } - - return PCI_SPEED_UNKNOWN; -} - -/** - * pcie_get_width_cap - query for the PCI device's link width capability - * @dev: PCI device to query - * - * Query the PCI device width capability. Return the maximum link width - * supported by the device. - */ -enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev) -{ - u32 lnkcap; - - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); - if (lnkcap) - return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; - - return PCIE_LNK_WIDTH_UNKNOWN; -} -#endif - enum pci_bus_speed (*_kcl_pcie_get_speed_cap)(struct pci_dev *dev); EXPORT_SYMBOL(_kcl_pcie_get_speed_cap); @@ -176,10 +112,6 @@ EXPORT_SYMBOL(_kcl_pcie_get_width_cap); void amdkcl_pci_init(void) { -#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) - _kcl_pcie_get_speed_cap = amdkcl_fp_setup("pcie_get_speed_cap", pcie_get_speed_cap); - _kcl_pcie_get_width_cap = amdkcl_fp_setup("pcie_get_width_cap", pcie_get_width_cap); -#endif #if !defined(HAVE_PCIE_BANDWIDTH_AVAILABLE) _kcl_pcie_link_speed = (const unsigned char *) amdkcl_fp_setup("pcie_link_speed", _kcl_pcie_link_speed_stub); #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0884c116da9ed..10ad6f49ec9ca 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -999,9 +999,6 @@ /* pci_enable_atomic_ops_to_root() exist */ #define HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT 1 -/* pcie_get_speed_cap() and pcie_get_width_cap() exist */ -#define HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP 1 - /* PCI driver handles extended tags */ #define HAVE_PCI_CONFIGURE_EXTENDED_TAGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3e7f141e1a332..dadd4462d358a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -26,7 +26,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IN_COMPAT_SYSCALL AC_AMDGPU_SEQ_HEX_DUMP AC_AMDGPU_KSYS_SYNC_HELPER - AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_AMDGPU_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT AC_AMDGPU_PCI_UPSTREAM_BRIDGE AC_AMDGPU_PCIE_BANDWIDTH_AVAILABLE diff --git a/drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 b/drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 deleted file mode 100644 index 905b62bc15628..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 +++ /dev/null @@ -1,12 +0,0 @@ -dnl # -dnl # commit 576c7218a1546e0153480b208b125509cec71470 -dnl # PCI: Export pcie_get_speed_cap and pcie_get_width_cap -dnl # -AC_DEFUN([AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([pcie_get_speed_cap pcie_get_width_cap], [drivers/pci/pci.c], [ - AC_DEFINE(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP, 1, - [pcie_get_speed_cap() and pcie_get_width_cap() exist]) - ]) - ]) -]) diff --git a/include/kcl/backport/kcl_pci_backport.h b/include/kcl/backport/kcl_pci_backport.h index 2cf66ef4aa69f..f75f4fbd7e7fa 100644 --- a/include/kcl/backport/kcl_pci_backport.h +++ b/include/kcl/backport/kcl_pci_backport.h @@ -6,10 +6,6 @@ #include #include -#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) -#define pcie_get_speed_cap _kcl_pcie_get_speed_cap -#endif - #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0) #define AMDKCL_PCIE_BRIDGE_PM_USABLE #endif diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index f10e5e5c84106..e9547c0d7ffd1 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -97,27 +97,14 @@ 0) #endif -#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) -extern enum pci_bus_speed (*_kcl_pcie_get_speed_cap)(struct pci_dev *dev); -extern enum pcie_link_width (*_kcl_pcie_get_width_cap)(struct pci_dev *dev); -#endif - static inline enum pci_bus_speed kcl_pcie_get_speed_cap(struct pci_dev *dev) { -#if defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) return pcie_get_speed_cap(dev); -#else - return _kcl_pcie_get_speed_cap(dev); -#endif } static inline enum pcie_link_width kcl_pcie_get_width_cap(struct pci_dev *dev) { -#if defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) return pcie_get_width_cap(dev); -#else - return _kcl_pcie_get_width_cap(dev); -#endif } #if !defined(HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT) From 9c9717b56ab1627050b8048b4890b55571e1b66c Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Feb 2023 14:21:08 +0800 Subject: [PATCH 0974/2653] drm/amdkcl: kcl-cleanup HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT Change-Id: Ia12c8c8690eb14142d092a19d39d6bdf87d0dc92 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 87 ------------------- drivers/gpu/drm/amd/dkms/config/config.h | 3 - drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../dkms/m4/pcie-enable-atomic-ops-to-root.m4 | 18 ---- include/kcl/kcl_pci.h | 9 -- 5 files changed, 118 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/pcie-enable-atomic-ops-to-root.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index e334a99db43b9..f5664e46c26e2 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -117,93 +117,6 @@ void amdkcl_pci_init(void) #endif } -#if !defined(HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT) -/** - * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port - * @dev: the PCI device - * @comp_caps: Caps required for atomic request completion - * - * Return 0 if all upstream bridges support AtomicOp routing, egress - * blocking is disabled on all upstream ports, and the root port - * supports the requested completion capabilities (32-bit, 64-bit - * and/or 128-bit AtomicOp completion), or negative otherwise. - * - */ -int _kcl_pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 comp_caps) -{ - struct pci_bus *bus = dev->bus; - - if (!pci_is_pcie(dev)) - return -EINVAL; - - switch (pci_pcie_type(dev)) { - /* - * PCIe 3.0, 6.15 specifies that endpoints and root ports are permitted - * to implement AtomicOp requester capabilities. - */ - case PCI_EXP_TYPE_ENDPOINT: - case PCI_EXP_TYPE_LEG_END: - case PCI_EXP_TYPE_RC_END: - break; - default: - return -EINVAL; - } - - while (bus->parent) { - struct pci_dev *bridge = bus->self; - u32 cap; - - pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); - - switch (pci_pcie_type(bridge)) { - /* - * Upstream, downstream and root ports may implement AtomicOp - * routing capabilities. AtomicOp routing via a root port is - * not considered. - */ - case PCI_EXP_TYPE_UPSTREAM: - case PCI_EXP_TYPE_DOWNSTREAM: - if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) - return -EINVAL; - break; - - /* - * Root ports are permitted to implement AtomicOp completion - * capabilities. - */ - case PCI_EXP_TYPE_ROOT_PORT: - if ((cap & comp_caps) != comp_caps) - return -EINVAL; - break; - } - - /* - * Upstream ports may block AtomicOps on egress. - */ -#if defined(OS_NAME_RHEL_6) - if (pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM) { -#else - if (!bridge->has_secondary_link) { -#endif - u32 ctl2; - - pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, - &ctl2); - if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_BLOCK) - return -EINVAL; - } - - bus = bus->parent; - } - - pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, - PCI_EXP_DEVCTL2_ATOMIC_REQ); - - return 0; -} -EXPORT_SYMBOL(_kcl_pci_enable_atomic_ops_to_root); -#endif - #if !defined(HAVE_PCI_CONFIGURE_EXTENDED_TAGS) void _kcl_pci_configure_extended_tags(struct pci_dev *dev) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 10ad6f49ec9ca..896dde34a8904 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -996,9 +996,6 @@ /* pcie_bandwidth_available() is available */ #define HAVE_PCIE_BANDWIDTH_AVAILABLE 1 -/* pci_enable_atomic_ops_to_root() exist */ -#define HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT 1 - /* PCI driver handles extended tags */ #define HAVE_PCI_CONFIGURE_EXTENDED_TAGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index dadd4462d358a..375e4463a51c3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -26,7 +26,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IN_COMPAT_SYSCALL AC_AMDGPU_SEQ_HEX_DUMP AC_AMDGPU_KSYS_SYNC_HELPER - AC_AMDGPU_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT AC_AMDGPU_PCI_UPSTREAM_BRIDGE AC_AMDGPU_PCIE_BANDWIDTH_AVAILABLE AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS diff --git a/drivers/gpu/drm/amd/dkms/m4/pcie-enable-atomic-ops-to-root.m4 b/drivers/gpu/drm/amd/dkms/m4/pcie-enable-atomic-ops-to-root.m4 deleted file mode 100644 index fe1539a268b96..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/pcie-enable-atomic-ops-to-root.m4 +++ /dev/null @@ -1,18 +0,0 @@ -dnl # -dnl # commit 430a23689dea2e36ae5a0fc75a67301fd46b18bf -dnl # Author: Jay Cornwall -dnl # Date: Thu Jan 4 19:44:59 2018 -0500 -dnl # PCI: Add pci_enable_atomic_ops_to_root() -dnl # -AC_DEFUN([AC_AMDGPU_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - pci_enable_atomic_ops_to_root(NULL, 0); - ], [pci_enable_atomic_ops_to_root], [drivers/pci/pci.c], [ - AC_DEFINE(HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT, 1, - [pci_enable_atomic_ops_to_root() exist]) - ]) - ]) -]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index e9547c0d7ffd1..f3dd051548960 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -107,15 +107,6 @@ static inline enum pcie_link_width kcl_pcie_get_width_cap(struct pci_dev *dev) return pcie_get_width_cap(dev); } -#if !defined(HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT) -int _kcl_pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 comp_caps); -static inline -int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) -{ - return _kcl_pci_enable_atomic_ops_to_root(dev, cap_mask); -} -#endif - /* Copied from v3.12-rc2-29-gc6bde215acfd include/linux/pci.h */ #if !defined(HAVE_PCI_UPSTREAM_BRIDGE) static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) From d85835dd0993451bc364c20d61fa49aa8feecc3a Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Feb 2023 14:23:02 +0800 Subject: [PATCH 0975/2653] drm/amdkcl: kcl-cleanup HAVE_PCIE_BANDWIDTH_AVAILABLE Change-Id: I39e6f5f778632ceb7d21d951c840f32b8b5a0bbf Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 90 ------------------- drivers/gpu/drm/amd/amdkcl/main.c | 2 - drivers/gpu/drm/amd/dkms/config/config.h | 3 - drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../amd/dkms/m4/pcie-bandwidth-available.m4 | 16 ---- include/kcl/kcl_pci.h | 13 --- 6 files changed, 125 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/pcie-bandwidth-available.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index f5664e46c26e2..c62f0a2f9d6e9 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -21,102 +21,12 @@ #include #include -#if !defined(HAVE_PCIE_BANDWIDTH_AVAILABLE) -/* Copied from drivers/pci/probe.c and modified for KCL */ -const unsigned char *_kcl_pcie_link_speed; - -const unsigned char _kcl_pcie_link_speed_stub[] = { - PCI_SPEED_UNKNOWN, /* 0 */ - PCIE_SPEED_2_5GT, /* 1 */ - PCIE_SPEED_5_0GT, /* 2 */ - PCIE_SPEED_8_0GT, /* 3 */ - PCI_SPEED_UNKNOWN, /* 4 */ - PCI_SPEED_UNKNOWN, /* 5 */ - PCI_SPEED_UNKNOWN, /* 6 */ - PCI_SPEED_UNKNOWN, /* 7 */ - PCI_SPEED_UNKNOWN, /* 8 */ - PCI_SPEED_UNKNOWN, /* 9 */ - PCI_SPEED_UNKNOWN, /* A */ - PCI_SPEED_UNKNOWN, /* B */ - PCI_SPEED_UNKNOWN, /* C */ - PCI_SPEED_UNKNOWN, /* D */ - PCI_SPEED_UNKNOWN, /* E */ - PCI_SPEED_UNKNOWN /* F */ -}; - -/* Copied from drivers/pci/pci.c */ -/** - * pcie_bandwidth_available - determine minimum link settings of a PCIe - * device and its bandwidth limitation - * @dev: PCI device to query - * @limiting_dev: storage for device causing the bandwidth limitation - * @speed: storage for speed of limiting device - * @width: storage for width of limiting device - * - * Walk up the PCI device chain and find the point where the minimum - * bandwidth is available. Return the bandwidth available there and (if - * limiting_dev, speed, and width pointers are supplied) information about - * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of - * raw bandwidth. - */ -u32 _kcl_pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, - enum pci_bus_speed *speed, - enum pcie_link_width *width) -{ - u16 lnksta; - enum pci_bus_speed next_speed; - enum pcie_link_width next_width; - u32 bw, next_bw; - - if (speed) - *speed = PCI_SPEED_UNKNOWN; - if (width) - *width = PCIE_LNK_WIDTH_UNKNOWN; - - bw = 0; - - while (dev) { - pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); - - next_speed = _kcl_pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; - next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> - PCI_EXP_LNKSTA_NLW_SHIFT; - - next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed); - - /* Check if current device limits the total bandwidth */ - if (!bw || next_bw <= bw) { - bw = next_bw; - - if (limiting_dev) - *limiting_dev = dev; - if (speed) - *speed = next_speed; - if (width) - *width = next_width; - } - - dev = pci_upstream_bridge(dev); - } - - return bw; -} -EXPORT_SYMBOL(_kcl_pcie_bandwidth_available); -#endif /* HAVE_PCIE_BANDWIDTH_AVAILABLE */ - enum pci_bus_speed (*_kcl_pcie_get_speed_cap)(struct pci_dev *dev); EXPORT_SYMBOL(_kcl_pcie_get_speed_cap); enum pcie_link_width (*_kcl_pcie_get_width_cap)(struct pci_dev *dev); EXPORT_SYMBOL(_kcl_pcie_get_width_cap); -void amdkcl_pci_init(void) -{ -#if !defined(HAVE_PCIE_BANDWIDTH_AVAILABLE) - _kcl_pcie_link_speed = (const unsigned char *) amdkcl_fp_setup("pcie_link_speed", _kcl_pcie_link_speed_stub); -#endif -} - #if !defined(HAVE_PCI_CONFIGURE_EXTENDED_TAGS) void _kcl_pci_configure_extended_tags(struct pci_dev *dev) { diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index b4c76ba82d292..d33b1db010e1a 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -8,7 +8,6 @@ extern void amdkcl_fence_init(void); extern void amdkcl_reservation_init(void); extern void amdkcl_io_init(void); extern void amdkcl_mm_init(void); -extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); extern void amdkcl_sched_init(void); extern void amdkcl_numa_init(void); @@ -22,7 +21,6 @@ int __init amdkcl_init(void) amdkcl_reservation_init(); amdkcl_io_init(); amdkcl_mm_init(); - amdkcl_pci_init(); amdkcl_suspend_init(); amdkcl_sched_init(); amdkcl_numa_init(); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 896dde34a8904..08d13941a77e8 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -993,9 +993,6 @@ /* pcie_aspm_enabled() is available */ #define HAVE_PCIE_ASPM_ENABLED 1 -/* pcie_bandwidth_available() is available */ -#define HAVE_PCIE_BANDWIDTH_AVAILABLE 1 - /* PCI driver handles extended tags */ #define HAVE_PCI_CONFIGURE_EXTENDED_TAGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 375e4463a51c3..8023dedaba4a9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -27,7 +27,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SEQ_HEX_DUMP AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCI_UPSTREAM_BRIDGE - AC_AMDGPU_PCIE_BANDWIDTH_AVAILABLE AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS AC_AMDGPU_PCI_DEV_ID AC_AMDGPU_PCI_REBAR_BYTES_TO_SIZE diff --git a/drivers/gpu/drm/amd/dkms/m4/pcie-bandwidth-available.m4 b/drivers/gpu/drm/amd/dkms/m4/pcie-bandwidth-available.m4 deleted file mode 100644 index e733ecc72488c..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/pcie-bandwidth-available.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit 6db79a88c67e4679d9c1e4a3f05c6385e21f6e9a -dnl # PCI: Add pcie_bandwidth_available() to compute bandwidth available to device -dnl # -AC_DEFUN([AC_AMDGPU_PCIE_BANDWIDTH_AVAILABLE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - pcie_bandwidth_available(NULL, NULL, NULL, NULL); - ], [pcie_bandwidth_available], [drivers/pci/pci.c], [ - AC_DEFINE(HAVE_PCIE_BANDWIDTH_AVAILABLE, 1, - [pcie_bandwidth_available() is available]) - ]) - ]) -]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index f3dd051548960..62e8d734fdf5c 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -119,19 +119,6 @@ static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) } #endif -#if !defined(HAVE_PCIE_BANDWIDTH_AVAILABLE) -u32 _kcl_pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, - enum pci_bus_speed *speed, - enum pcie_link_width *width); -static inline -u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, - enum pci_bus_speed *speed, - enum pcie_link_width *width) -{ - return _kcl_pcie_bandwidth_available(dev, limiting_dev, speed, width); -} -#endif - #if !defined(HAVE_PCI_CONFIGURE_EXTENDED_TAGS) void _kcl_pci_configure_extended_tags(struct pci_dev *dev); #endif From 0a0bec34a8334d4cb57fb3c18fc2ec5023a47af4 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 16 Feb 2023 14:42:08 +0800 Subject: [PATCH 0976/2653] drm/amdkcl: kcl-cleanup HAVE_REQUEST_FIRMWARE_DIRECT Change-Id: I91f5937cd38c55d365f385d874a796f92befd366 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 - drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../drm/amd/dkms/m4/request-firmware-direct.m4 | 16 ---------------- include/kcl/kcl_firmware.h | 12 ------------ 5 files changed, 33 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/request-firmware-direct.m4 delete mode 100644 include/kcl/kcl_firmware.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 109b65af58cf6..e913c8e92c80c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 08d13941a77e8..1a92ecfb2ac53 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1041,9 +1041,6 @@ /* remove_conflicting_pci_framebuffers() wants p,p args */ /* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ -/* request_firmware_direct() is available */ -#define HAVE_REQUEST_FIRMWARE_DIRECT 1 - /* sched_set_fifo_low() is available */ #define HAVE_SCHED_SET_FIFO_LOW 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8023dedaba4a9..5212943ec5a1c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -14,7 +14,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_MAP_SGTABLE AC_AMDGPU_I2C_NEW_CLIENT_DEVICE AC_AMDGPU_I2C_LOCK_OPERATIONS_STRUCT - AC_AMDGPU_REQUEST_FIRMWARE_DIRECT AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS AC_AMDGPU_DEV_PM_SET_DRIVER_FLAGS AC_AMDGPU_COMPAT_PTR_IOCTL diff --git a/drivers/gpu/drm/amd/dkms/m4/request-firmware-direct.m4 b/drivers/gpu/drm/amd/dkms/m4/request-firmware-direct.m4 deleted file mode 100644 index 218e403328bc8..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/request-firmware-direct.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # v3.13-rc2-51-gbba3a87e982a -dnl # firmware: Introduce request_firmware_direct() -dnl # -AC_DEFUN([AC_AMDGPU_REQUEST_FIRMWARE_DIRECT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - request_firmware_direct(NULL, NULL, NULL); - ], [ - AC_DEFINE(HAVE_REQUEST_FIRMWARE_DIRECT, 1, - [request_firmware_direct() is available]) - ]) - ]) -]) diff --git a/include/kcl/kcl_firmware.h b/include/kcl/kcl_firmware.h deleted file mode 100644 index b846e2d4eee5d..0000000000000 --- a/include/kcl/kcl_firmware.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef AMDKCL_FIRMWARE_H -#define AMDKCL_FIRMWARE_H - -#if !defined(HAVE_REQUEST_FIRMWARE_DIRECT) -#include - -#define request_firmware_direct request_firmware - -#endif -#endif /* AMDKCL_FIRMWARE_H */ - From 037585b4e6ebd1ae9c1d4ba6ced3dbc735376844 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 23 Feb 2023 11:02:14 +0800 Subject: [PATCH 0977/2653] drm/amdkcl:kcl-cleanup HAVE_DRM_GEM_MAP_ATTACH_2ARGS Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 8 +------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 2 -- drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 | 14 -------------- 4 files changed, 1 insertion(+), 26 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index e86813cf37651..8e990c2947585 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -148,9 +148,6 @@ __dma_resv_make_exclusive(struct dma_resv *obj) * 0 on success or a negative error code on failure. */ static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf, -#ifndef HAVE_DRM_GEM_MAP_ATTACH_2ARGS - struct device *target_dev, -#endif struct dma_buf_attachment *attach) { struct drm_gem_object *obj = dma_buf->priv; @@ -158,11 +155,8 @@ static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf, struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); long r; -#ifdef HAVE_DRM_GEM_MAP_ATTACH_2ARGS r = drm_gem_map_attach(dma_buf, attach); -#else - r = drm_gem_map_attach(dma_buf, target_dev, attach); -#endif + if (r) return r; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1a92ecfb2ac53..fc5045038fa80 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -581,9 +581,6 @@ /* drm_gem_plane_helper_prepare_fb() is available */ #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 -/* drm_gem_map_attach() wants 2 arguments */ -/* #undef HAVE_DRM_GEM_MAP_ATTACH_2ARGS */ - /* drm_gem_object_funcs->vmap() has 2 args */ #define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 index d4f139e428849..86159c3f96200 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -52,8 +52,6 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ ],[ AC_DEFINE(HAVE_DMA_BUF_OPS_LEGACY, 1, [dma_buf->dynamic_mapping is not available]) - - AC_AMDGPU_DRM_GEM_MAP_ATTACH ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 deleted file mode 100644 index 031d62f21740f..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 +++ /dev/null @@ -1,14 +0,0 @@ -dnl # -dnl # commit v4.17-rc3-491-ga19741e5e5a9 -dnl # dma_buf: remove device parameter from attach callback v2 -dnl # -AC_DEFUN([AC_AMDGPU_DRM_GEM_MAP_ATTACH], [ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_gem_map_attach(NULL, NULL); - ], [drm_gem_map_attach], [drivers/gpu/drm/drm_prime.c], [ - AC_DEFINE(HAVE_DRM_GEM_MAP_ATTACH_2ARGS, 1, - [drm_gem_map_attach() wants 2 arguments]) - ]) -]) From 6b643892050ae6285dd7448300788a6d0ac89420 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 24 Feb 2023 13:11:05 +0800 Subject: [PATCH 0978/2653] drm/amdkcl:kcl-cleanup CONFIG_DRM_AMD_DC_DSC_SUPPORT Signed-off-by: Ma Jun Reviewed-by: Leslie Shi Reviewed-by: Folra Cui --- .../gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c | 5 +-- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ----- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 ----- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 4 --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 6 ---- drivers/gpu/drm/amd/display/dc/core/dc.c | 12 ------- .../gpu/drm/amd/display/dc/core/dc_resource.c | 6 ---- .../gpu/drm/amd/display/dc/core/dc_stream.c | 4 --- drivers/gpu/drm/amd/display/dc/dc.h | 4 --- drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 -- drivers/gpu/drm/amd/display/dc/dc_types.h | 2 -- drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 4 --- .../display/dc/dcn201/dcn201_link_encoder.c | 2 -- .../amd/display/dc/dcn21/dcn21_link_encoder.c | 2 -- .../display/dc/dio/dcn20/dcn20_link_encoder.c | 6 ---- .../display/dc/dio/dcn20/dcn20_link_encoder.h | 2 -- .../dc/dio/dcn20/dcn20_stream_encoder.c | 6 ---- .../dc/dio/dcn30/dcn30_dio_link_encoder.c | 2 -- .../dc/dio/dcn30/dcn30_dio_stream_encoder.c | 4 --- .../dc/dio/dcn301/dcn301_dio_link_encoder.c | 2 -- .../dc/dio/dcn31/dcn31_dio_link_encoder.c | 6 ---- .../dc/dio/dcn314/dcn314_dio_stream_encoder.c | 6 ---- .../dc/dio/dcn32/dcn32_dio_link_encoder.c | 2 -- .../dc/dio/dcn32/dcn32_dio_stream_encoder.c | 3 -- .../dc/dio/dcn321/dcn321_dio_link_encoder.c | 2 -- .../amd/display/dc/dml/display_mode_enums.h | 2 -- .../drm/amd/display/dc/dml/dsc/rc_calc_fpu.c | 2 -- .../drm/amd/display/dc/dml/dsc/rc_calc_fpu.h | 2 -- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 2 -- .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 2 -- .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h | 2 -- drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 2 -- .../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 2 -- .../hpo/dcn31/dcn31_hpo_dp_stream_encoder.c | 2 -- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 4 --- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 8 ----- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.h | 2 -- .../amd/display/dc/hwss/dcn20/dcn20_init.c | 4 --- .../amd/display/dc/hwss/dcn21/dcn21_init.c | 2 -- .../amd/display/dc/hwss/dcn30/dcn30_init.c | 2 -- .../amd/display/dc/hwss/dcn301/dcn301_init.c | 2 -- .../amd/display/dc/hwss/dcn302/dcn302_hwseq.c | 2 -- .../amd/display/dc/hwss/dcn302/dcn302_hwseq.h | 2 -- .../amd/display/dc/hwss/dcn302/dcn302_init.c | 2 -- .../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 6 ---- .../amd/display/dc/hwss/dcn31/dcn31_init.c | 2 -- .../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 4 --- .../amd/display/dc/hwss/dcn314/dcn314_init.c | 2 -- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 4 --- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.h | 2 -- .../amd/display/dc/hwss/dcn32/dcn32_init.c | 2 -- .../gpu/drm/amd/display/dc/inc/core_types.h | 4 --- .../drm/amd/display/dc/inc/hw/link_encoder.h | 4 --- .../amd/display/dc/inc/hw/timing_generator.h | 2 -- drivers/gpu/drm/amd/display/dc/inc/link.h | 5 ++- .../gpu/drm/amd/display/dc/link/link_dpms.c | 12 ------- .../drm/amd/display/dc/link/link_validation.c | 7 ----- .../dc/link/protocols/link_dp_capability.c | 7 +---- .../dc/link/protocols/link_dp_capability.h | 2 -- .../display/dc/link/protocols/link_dp_phy.c | 2 -- .../dc/link/protocols/link_dp_training.c | 2 -- .../link/protocols/link_dp_training_8b_10b.c | 2 -- .../dc/link/protocols/link_dp_training_dpia.c | 2 -- .../link/protocols/link_edp_panel_control.c | 4 --- .../amd/display/dc/optc/dcn20/dcn20_optc.c | 9 ------ .../amd/display/dc/optc/dcn20/dcn20_optc.h | 2 -- .../amd/display/dc/optc/dcn201/dcn201_optc.c | 2 -- .../amd/display/dc/optc/dcn30/dcn30_optc.c | 4 --- .../amd/display/dc/optc/dcn30/dcn30_optc.h | 2 -- .../amd/display/dc/optc/dcn31/dcn31_optc.c | 2 -- .../amd/display/dc/optc/dcn314/dcn314_optc.c | 2 -- .../amd/display/dc/optc/dcn32/dcn32_optc.c | 2 -- .../dc/resource/dcn20/dcn20_resource.c | 31 ------------------- .../dc/resource/dcn20/dcn20_resource.h | 2 -- .../dc/resource/dcn201/dcn201_resource.c | 2 -- .../dc/resource/dcn21/dcn21_resource.c | 14 --------- .../dc/resource/dcn30/dcn30_resource.c | 22 ------------- .../dc/resource/dcn301/dcn301_resource.c | 14 --------- .../dc/resource/dcn302/dcn302_resource.c | 12 ------- .../dc/resource/dcn303/dcn303_resource.c | 10 ------ .../dc/resource/dcn31/dcn31_resource.c | 12 ------- .../dc/resource/dcn314/dcn314_resource.c | 10 ------ .../dc/resource/dcn315/dcn315_resource.c | 14 --------- .../dc/resource/dcn316/dcn316_resource.c | 14 --------- .../dc/resource/dcn32/dcn32_resource.c | 10 ------ .../resource/dcn32/dcn32_resource_helpers.c | 2 -- .../dc/resource/dcn321/dcn321_resource.c | 2 -- .../dc/virtual/virtual_stream_encoder.c | 8 ----- drivers/gpu/drm/amd/dkms/Makefile | 3 -- include/kcl/kcl_drm_dsc_helper.h | 3 -- 90 files changed, 4 insertions(+), 440 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c index f5546b4049608..8c799582dbbd7 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c @@ -15,7 +15,6 @@ * device expects the PPS payload in big endian format for fields * that span more than 1 byte. */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include #include @@ -330,6 +329,4 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) return 0; } EXPORT_SYMBOL(drm_dsc_compute_rc_parameters); -#endif /* HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS */ - -#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ +#endif /* HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS */ \ No newline at end of file diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3ff5bc2bb8db7..b4f708b0170b4 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8088,7 +8088,6 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { .atomic_check = dm_encoder_helper_atomic_check }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, struct dc_state *dc_state, @@ -8175,7 +8174,6 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, return 0; } #endif -#endif static int to_drm_connector_type(enum signal_type st) { @@ -12000,11 +11998,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, bool lock_and_validation_needed = false; bool is_top_most_overlay = true; struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct drm_dp_mst_topology_mgr *mgr; struct drm_dp_mst_topology_state *mst_state; struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; -#endif trace_amdgpu_dm_atomic_check_begin(state); ret = drm_atomic_helper_check_modeset(dev, state); @@ -12334,7 +12330,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS /* set the slot info for each mst_state based on the link encoding format */ for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { @@ -12359,8 +12354,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } drm_connector_list_iter_end(&iter); } -#endif -#endif #endif /** * Streams and planes are reset when there are changes that affect diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index a62981a37ec50..b02aa290d6d09 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -1361,7 +1361,6 @@ static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *b * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support * */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static int dp_dsc_fec_support_show(struct seq_file *m, void *data) { struct drm_connector *connector = m->private; @@ -1417,7 +1416,6 @@ static int dp_dsc_fec_support_show(struct seq_file *m, void *data) return ret; } -#endif /* function: Trigger virtual HPD redetection on connector * @@ -1555,7 +1553,6 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, * 1 - means that DSC is currently enabled * 0 - means that DSC is disabled */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { @@ -2526,7 +2523,6 @@ static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, kfree(rd_buf); return result; } -#endif /* * function description: Read max_requested_bpc property from the connector @@ -2937,7 +2933,6 @@ DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); DEFINE_SHOW_ATTRIBUTE(is_dpia_link); DEFINE_SHOW_STORE_ATTRIBUTE(hdmi_cec_state); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static const struct file_operations dp_dsc_clock_en_debugfs_fops = { .owner = THIS_MODULE, .read = dp_dsc_clock_en_read, @@ -2989,7 +2984,6 @@ static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { .read = dp_dsc_slice_bpg_offset_read, .llseek = default_llseek }; -#endif static const struct file_operations trigger_hotplug_debugfs_fops = { .owner = THIS_MODULE, @@ -3063,8 +3057,6 @@ static const struct { {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, -#endif - {"max_bpc", &dp_max_bpc_debugfs_fops}, {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, #ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 73bf37387a935..16018e908b560 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -837,7 +837,6 @@ bool dm_helpers_execute_fused_io( return amdgpu_dm_execute_fused_io(dev, link, commands, count, timeout_us); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, bool is_write_cmd, unsigned char cmd, @@ -1015,9 +1014,7 @@ static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( return ret; } -#endif -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool dm_helpers_dp_write_dsc_enable( struct dc_context *ctx, const struct dc_stream_state *stream, @@ -1110,7 +1107,6 @@ bool dm_helpers_dp_write_dsc_enable( return ret; } -#endif bool dm_helpers_dp_write_hblank_reduction(struct dc_context *ctx, const struct dc_stream_state *stream) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 5617a1e740696..a6382fb0bad2a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -268,7 +268,6 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { #endif /* HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER */ }; -#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) bool needs_dsc_aux_workaround(struct dc_link *link) { if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && @@ -360,7 +359,6 @@ static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnect return true; } #endif -#endif static int dm_dp_mst_get_modes(struct drm_connector *connector) { @@ -482,7 +480,6 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) amdgpu_dm_update_freesync_caps( connector, aconnector->drm_edid); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) #if defined(CONFIG_DRM_AMD_DC_FP) if (!validate_dsc_caps_on_connector(aconnector)) @@ -493,7 +490,6 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) if (!retrieve_downstream_port_device(aconnector)) memset(&aconnector->mst_downstream_port_present, 0, sizeof(aconnector->mst_downstream_port_present)); -#endif #endif } } @@ -952,7 +948,6 @@ int dm_mst_get_pbn_divider(struct dc_link *link) dc_link_get_link_cap(link)) / (8 * 1000 * 54); } -#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) #if defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) struct dsc_mst_fairness_params { struct dc_crtc_timing *timing; @@ -2158,4 +2153,3 @@ enum dc_status dm_dp_mst_is_port_support_mode( #endif return DC_OK; } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 39b85d4867256..042ac796da1f2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -66,9 +66,7 @@ #include "dc_dmub_srv.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dsc.h" -#endif #include "vm_helper.h" @@ -721,9 +719,7 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, param.windowb_y_end = crc_window->windowb_y_end; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0; -#endif param.odm_mode = pipe->next_odm_pipe ? 1:0; /* Default to the union of both windows */ @@ -2959,10 +2955,8 @@ static enum surface_update_type check_update_surfaces_for_stream( if (stream_update->wb_update) su_flags->bits.wb_update = 1; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (stream_update->dsc_config) su_flags->bits.dsc_changed = 1; -#endif if (stream_update->mst_bw_update) su_flags->bits.mst_bw = 1; @@ -3215,9 +3209,7 @@ static void copy_stream_update_to_stream(struct dc *dc, struct dc_stream_state *stream, struct dc_stream_update *update) { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_context *dc_ctx = dc->ctx; -#endif if (update == NULL || stream == NULL) return; @@ -3319,7 +3311,6 @@ static void copy_stream_update_to_stream(struct dc *dc, update->wb_update->writeback_info[i]; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (update->dsc_config) { struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg; uint32_t old_dsc_enabled = stream->timing.flags.DSC; @@ -3345,7 +3336,6 @@ static void copy_stream_update_to_stream(struct dc *dc, update->dsc_config = NULL; } } -#endif if (update->scaler_sharpener_update) stream->scaler_sharpener_update = *update->scaler_sharpener_update; if (update->sharpening_required) @@ -3647,10 +3637,8 @@ static void commit_planes_do_stream_update(struct dc *dc, if (update_type == UPDATE_TYPE_FAST) continue; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (stream_update->dsc_config) dc->link_srv->update_dsc_config(pipe_ctx); -#endif if (stream_update->mst_bw_update) { if (stream_update->mst_bw_update->is_increase) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 54ae2faaa94e6..4d6181e7c612b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -3983,11 +3983,7 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc) if (dc->res_pool == NULL) return false; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT return dc->res_pool->res_cap->num_dsc > 0; -#else - return 0; -#endif } static bool planes_changed_for_existing_stream(struct dc_state *context, @@ -4908,10 +4904,8 @@ bool pipe_need_reprogram( false == pipe_ctx_old->stream->dpms_off) return true; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc) return true; -#endif if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc) return true; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 73c02d581133a..4d6bc9fd4faa8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -111,7 +111,6 @@ bool dc_stream_construct(struct dc_stream_state *stream, /* EDID CAP translation for HDMI 2.0 */ stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); stream->timing.dsc_cfg.num_slices_h = 0; stream->timing.dsc_cfg.num_slices_v = 0; @@ -120,7 +119,6 @@ bool dc_stream_construct(struct dc_stream_state *stream, stream->timing.dsc_cfg.linebuf_depth = 9; stream->timing.dsc_cfg.version_minor = 2; stream->timing.dsc_cfg.ycbcr422_simple = 0; -#endif update_stream_signal(stream, dc_sink_data); @@ -791,7 +789,6 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc, return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, struct dc_state *state, struct dc_stream_state *stream) @@ -802,7 +799,6 @@ enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, return DC_NO_DSC_RESOURCE; } } -#endif struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 314de71706b33..5653c1673aece 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -963,7 +963,6 @@ struct dc_debug_options { bool disable_dfs_bypass; bool disable_dpp_power_gate; bool disable_hubp_power_gate; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool disable_dsc_power_gate; bool disable_optc_power_gate; bool disable_hpo_power_gate; @@ -972,7 +971,6 @@ struct dc_debug_options { bool disable_dio_power_gate; int dsc_min_slice_height_override; int dsc_bpp_increment_div; -#endif bool disable_pplib_wm_range; enum wm_report_mode pplib_wm_report_mode; unsigned int min_disp_clk_khz; @@ -2475,7 +2473,6 @@ struct dc_container_id { }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_sink_dsc_caps { // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), // 'false' if they are sink's DSC caps @@ -2485,7 +2482,6 @@ struct dc_sink_dsc_caps { bool is_dsc_passthrough_supported; struct dsc_dec_dpcd_caps dsc_dec_caps; }; -#endif struct dc_sink_hblank_expansion_caps { // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 1034e0fed5932..5fc6fea211de3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -445,11 +445,9 @@ bool dc_stream_remove_writeback(struct dc *dc, struct dc_stream_state *stream, uint32_t dwb_pipe_inst); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, struct dc_state *state, struct dc_stream_state *stream); -#endif bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream); diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index e68d25be0f779..2e2dea21b3321 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -542,9 +542,7 @@ enum dc_infoframe_type { DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DC_DP_INFOFRAME_TYPE_PPS = 0x10, -#endif }; struct dc_info_packet { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index 9839dd8468554..4482609dce2d3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -379,9 +379,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us; copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; copy_settings_data->panel_inst = panel_inst; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1); -#endif /** * WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update) * Note that PSRSU+DSC is still under development. @@ -394,7 +392,6 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (((link->dpcd_caps.fec_cap.bits.FEC_CAPABLE && !link->dc->debug.disable_fec) && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && @@ -407,7 +404,6 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, sizeof(DP_SINK_DEVICE_STR_ID_2)))) copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 1; else -#endif copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 0; if (link->psr_settings.psr_version == DC_PSR_VERSION_1 && diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c index 789d6800ff08c..8d31fa131cd60 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c @@ -77,9 +77,7 @@ static bool dcn201_link_encoder_is_in_alt_mode(struct link_encoder *enc) } static const struct link_encoder_funcs dcn201_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c index 24fedaf5df408..eb9abb9f96986 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c @@ -298,9 +298,7 @@ static void dcn21_link_encoder_disable_output(struct link_encoder *enc, static const struct link_encoder_funcs dcn21_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c index d1518602a1702..182437fd0e147 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c @@ -173,10 +173,8 @@ static struct mpll_cfg dcn2_mpll_cfg[] = { void enc2_fec_set_enable(struct link_encoder *enc, bool enable) { struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DC_LOG_DSC("%s FEC at link encoder inst %d", enable ? "Enabling" : "Disabling", enc->id.enum_id); -#endif REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable); } @@ -197,7 +195,6 @@ bool enc2_fec_is_active(struct link_encoder *enc) return (active != 0); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* this function reads dsc related register fields to be logged later in dcn10_log_hw_state * into a dcn_dsc_state struct. */ @@ -210,7 +207,6 @@ void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s) REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete); } -#endif static bool update_cfg_data( struct dcn10_link_encoder *enc10, @@ -360,9 +356,7 @@ void enc2_hw_init(struct link_encoder *enc) } static const struct link_encoder_funcs dcn20_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h index 39a5f6882cf95..762c579fcb44d 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h @@ -342,9 +342,7 @@ void enc2_fec_set_ready(struct link_encoder *enc, bool ready); bool enc2_fec_is_active(struct link_encoder *enc); void enc2_hw_init(struct link_encoder *enc); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s); -#endif void dcn20_link_encoder_enable_dp_output( struct link_encoder *enc, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c index 2fa2816e28aa0..1953c56367d32 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c @@ -207,7 +207,6 @@ static void enc2_stream_encoder_stop_hdmi_info_packets( HDMI_GENERIC7_LINE, 0); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Update GSP7 SDP 128 byte long */ static void enc2_update_gsp7_128_info_packet( struct dcn10_stream_encoder *enc1, @@ -365,7 +364,6 @@ static void enc2_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } -#endif /* Set Dynamic Metadata-configuration. * enable_dme: TRUE: enables Dynamic Metadata Enfine, FALSE: disables DME @@ -461,10 +459,8 @@ static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing) { bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 && !timing->dsc_cfg.ycbcr422_simple); -#endif return two_pix; } @@ -635,11 +631,9 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc2_read_state, .dp_set_dsc_config = enc2_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet, -#endif .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, .get_fifo_cal_average_level = enc2_get_fifo_cal_average_level, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c index 504b70931b701..b8e31b5ea1140 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c @@ -56,9 +56,7 @@ bool dcn30_link_encoder_validate_output_with_stream( } static const struct link_encoder_funcs dcn30_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc3_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c index 106e963256c44..e93be7b6d9b03 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c @@ -295,7 +295,6 @@ void enc3_stream_encoder_stop_hdmi_info_packets( HDMI_GENERIC14_LINE, 0); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: Bytes per pixel in u3.28 format @@ -402,7 +401,6 @@ static void enc3_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } -#endif void enc3_stream_encoder_update_dp_info_packets_sdp_line_num( struct stream_encoder *enc, @@ -867,11 +865,9 @@ static const struct stream_encoder_funcs dcn30_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc3_read_state, .dp_set_dsc_config = enc3_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, -#endif .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c index 100953da7bc48..1b39a6e8a1ac5 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c @@ -48,9 +48,7 @@ (enc10->link_regs->index) static const struct link_encoder_funcs dcn301_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc3_hw_init, .setup = dcn10_link_encoder_setup, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c index 5abed61b96860..9a92f73d5b7fe 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c @@ -247,9 +247,7 @@ void enc31_hw_init(struct link_encoder *enc) } static const struct link_encoder_funcs dcn31_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc31_hw_init, @@ -484,9 +482,7 @@ void dcn31_link_encoder_enable_dp_output( if (link) { dpia_control.dpia_id = link->ddc_hw_inst; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dpia_control.fec_rdy = link->dc->link_srv->dp_should_enable_fec(link); -#endif } else { DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__); BREAK_TO_DEBUGGER(); @@ -533,9 +529,7 @@ void dcn31_link_encoder_enable_dp_mst_output( if (link) { dpia_control.dpia_id = link->ddc_hw_inst; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dpia_control.fec_rdy = link->dc->link_srv->dp_should_enable_fec(link); -#endif } else { DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__); BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c index 6bb66e4d37e02..1153caa60d5b7 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c @@ -384,7 +384,6 @@ void enc314_stream_encoder_dp_unblank( link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32 @@ -419,7 +418,6 @@ void enc314_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } -#endif void enc314_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container) { @@ -468,14 +466,10 @@ static const struct stream_encoder_funcs dcn314_str_enc_funcs = { .set_avmute = enc1_stream_encoder_set_avmute, .dig_connect_to_otg = enc1_dig_connect_to_otg, .dig_source_otg = enc1_dig_source_otg, - .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, - -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc314_read_state, .dp_set_dsc_config = enc314_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, -#endif .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c index cfcd48a67c760..06907e8a4eda1 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c @@ -195,9 +195,7 @@ void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc, static const struct link_encoder_funcs dcn32_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc32_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c index 173225fcdb6b5..1a9bb614c41e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c @@ -346,7 +346,6 @@ void enc32_stream_encoder_dp_unblank( link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32 @@ -381,7 +380,6 @@ static void enc32_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } -#endif static void enc32_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container) { @@ -460,7 +458,6 @@ static const struct stream_encoder_funcs dcn32_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc32_read_state, .dp_set_dsc_config = enc32_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c index b555264990f6b..2ed382a8e79c6 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c @@ -60,9 +60,7 @@ dm_write_reg(CTX, AUX_REG(reg_name), val) static const struct link_encoder_funcs dcn321_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc32_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h index 8975cd1529fa3..d5831a34f5a19 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h @@ -174,9 +174,7 @@ enum dm_validation_status { DML_FAIL_DIO_SUPPORT, DML_FAIL_NOT_ENOUGH_DSC, DML_FAIL_DSC_CLK_REQUIRED, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DML_FAIL_DSC_VALIDATION_FAILURE, -#endif DML_FAIL_URGENT_LATENCY, DML_FAIL_REORDERING_BUFFER, DML_FAIL_DISPCLK_DPPCLK, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c index e14e11ccf7d08..bf01d8a9e538b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c @@ -23,7 +23,6 @@ * */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "rc_calc_fpu.h" #include "qp_tables.h" @@ -258,4 +257,3 @@ void _do_calc_rc_params(struct rc_params *rc, rc->rc_buf_thresh[12] = 8000; rc->rc_buf_thresh[13] = 8064; } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h index 0b70eb9bcc6b9..d7cd8cc247583 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h +++ b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h @@ -23,7 +23,6 @@ * */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifndef __RC_CALC_FPU_H__ #define __RC_CALC_FPU_H__ @@ -89,4 +88,3 @@ void _do_calc_rc_params(struct rc_params *rc, int minor_version); #endif -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 1c8711a4b88e9..1f53a9f0c0ac3 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -22,7 +22,6 @@ * Author: AMD */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include #include #include "dc_hw_types.h" @@ -1453,4 +1452,3 @@ void dc_dsc_get_default_config_option(const struct dc *dc, struct dc_dsc_config_ options->slice_height_granularity = 1; options->force_dsc_when_not_needed = false; } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c index 72bb616c00405..58f44309058eb 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c @@ -23,7 +23,6 @@ * */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include #include "reg_helper.h" @@ -770,4 +769,3 @@ static void dsc_write_to_registers(struct display_stream_compressor *dsc, const RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h index 582c8deb5c47a..315c2b67d8dbe 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h @@ -21,7 +21,6 @@ * Authors: AMD * */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifndef __DCN20_DSC_H__ #define __DCN20_DSC_H__ @@ -616,4 +615,3 @@ void dsc2_disconnect(struct display_stream_compressor *dsc); void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc); #endif -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c index 1699a57ab7cb1..25ea69bd2e820 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c @@ -1,4 +1,3 @@ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* * Copyright 2017 Advanced Micro Devices, Inc. @@ -68,4 +67,3 @@ void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps) DC_FP_END(); #endif } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c index 13fc27926468f..6f5ad09ad1404 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c @@ -1,4 +1,3 @@ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* * Copyright 2012-17 Advanced Micro Devices, Inc. * @@ -122,4 +121,3 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, dsc_params->rc_buffer_model_size = dsc_cfg.rc_bits; return ret; } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c index 7b181d4f959b2..759b453385c46 100644 --- a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c @@ -564,9 +564,7 @@ static void dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet( /* Load PPS into infoframe (SDP) registers */ pps_sdp.valid = true; pps_sdp.hb0 = 0; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS; -#endif pps_sdp.hb2 = 127; pps_sdp.hb3 = 0; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 04ce194010ef9..39910f73ecd06 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -49,9 +49,7 @@ #include "clk_mgr.h" #include "link_hwss.h" #include "dpcd_defs.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dsc.h" -#endif #include "dce/dmub_psr.h" #include "dc_dmub_srv.h" #include "dce/dmub_hw_lock_mgr.h" @@ -646,7 +644,6 @@ void dcn10_log_hw_state(struct dc *dc, } DTN_INFO("\n"); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT // dcn_dsc_state struct field bytes_per_pixel was renamed to bits_per_pixel // TODO: Update golden log header to reflect this name change DTN_INFO("DSC: CLOCK_EN SLICE_WIDTH Bytes_pp\n"); @@ -703,7 +700,6 @@ void dcn10_log_hw_state(struct dc *dc, } } DTN_INFO("\n"); -#endif DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n" "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n", diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 55dd8f52e40e3..7d24fa1517bf1 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -32,9 +32,7 @@ #include "dcn20/dcn20_resource.h" #include "dcn20_hwseq.h" #include "dce/dce_hwseq.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" -#endif #include "dcn20/dcn20_optc.h" #include "abm.h" #include "clk_mgr.h" @@ -473,7 +471,6 @@ void dcn20_init_blank( hws->funcs.wait_for_blank_complete(opp); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn20_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -550,7 +547,6 @@ void dcn20_dsc_pg_control( if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } -#endif void dcn20_dpp_pg_control( struct dce_hwseq *hws, @@ -2608,7 +2604,6 @@ bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dce_hwseq *hws = dc->hwseq; if (pipe_ctx->stream_res.dsc) { @@ -2620,12 +2615,10 @@ void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) odm_pipe = odm_pipe->next_odm_pipe; } } -#endif } void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dce_hwseq *hws = dc->hwseq; if (pipe_ctx->stream_res.dsc) { @@ -2637,7 +2630,6 @@ void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) odm_pipe = odm_pipe->next_odm_pipe; } } -#endif } void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h index 1424a0f2c09d8..9d1ad3b29ca52 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h @@ -130,12 +130,10 @@ void dcn20_init_vm_ctx( void dcn20_set_flip_control_gsl( struct pipe_ctx *pipe_ctx, bool flip_immediate); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn20_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on); -#endif void dcn20_fpga_init_hw(struct dc *dc); bool dcn20_wait_for_blank_complete( struct output_pixel_processor *opp); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c index 8ad1455284fc9..ad253c586ea1a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c @@ -129,11 +129,7 @@ static const struct hwseq_private_funcs dcn20_private_funcs = { .dpp_pg_control = dcn20_dpp_pg_control, .hubp_pg_control = dcn20_hubp_pg_control, .update_odm = dcn20_update_odm, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, -#else - .dsc_pg_control = NULL, -#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c index 46b06ea163ced..c7701a8b574aa 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c @@ -132,9 +132,7 @@ static const struct hwseq_private_funcs dcn21_private_funcs = { .dpp_pg_control = dcn20_dpp_pg_control, .hubp_pg_control = dcn20_hubp_pg_control, .update_odm = dcn20_update_odm, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, -#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c index 2d92ff4ababb8..2ac5d54d16269 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c @@ -138,9 +138,7 @@ static const struct hwseq_private_funcs dcn30_private_funcs = { .hubp_pg_control = dcn20_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, -#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c index a9838babe0fa0..8d7ceb7b32b86 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c @@ -136,9 +136,7 @@ static const struct hwseq_private_funcs dcn301_private_funcs = { .hubp_pg_control = dcn20_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, -#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c index 40fad52521647..0a6d58dd8f6da 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c @@ -156,7 +156,6 @@ void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) { uint32_t power_gate = power_on ? 0 : 1; @@ -222,4 +221,3 @@ void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool po if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h index 6317b4a0f363e..1e5126a0e695d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h @@ -30,8 +30,6 @@ void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on); void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on); -#endif #endif /* __DC_HWSS_DCN302_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c index 1602be017597a..637f9514d37b2 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c @@ -37,7 +37,5 @@ void dcn302_hw_sequencer_construct(struct dc *dc) dc->hwseq->funcs.dpp_pg_control = dcn302_dpp_pg_control; dc->hwseq->funcs.hubp_pg_control = dcn302_hubp_pg_control; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dc->hwseq->funcs.dsc_pg_control = dcn302_dsc_pg_control; -#endif } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index 5f148e79319ab..71d04e6015808 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -278,7 +278,6 @@ void dcn31_init_hw(struct dc *dc) dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn31_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -341,7 +340,6 @@ void dcn31_dsc_pg_control( } } -#endif void dcn31_enable_power_gating_plane( @@ -365,10 +363,8 @@ void dcn31_enable_power_gating_plane( REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); force_on = true; /* disable power gating */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) force_on = false; -#endif /* DCS0/1/2/3/4/5 */ REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); @@ -540,11 +536,9 @@ static void dcn31_reset_back_end_for_pipe( dc->hwseq->wa_state.skip_blank_stream = true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT pipe_ctx->stream_res.tg->funcs->set_dsc_config( pipe_ctx->stream_res.tg, OPTC_DSC_DISABLED, 0, 0); -#endif pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c index 060e3db29052b..556f4fe57eda7 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c @@ -139,9 +139,7 @@ static const struct hwseq_private_funcs dcn31_private_funcs = { .hubp_pg_control = dcn31_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn31_dsc_pg_control, -#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c index 677499078988e..e68f21fd5f0fb 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c @@ -221,7 +221,6 @@ void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn314_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -292,7 +291,6 @@ void dcn314_dsc_pg_control( } } -#endif void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) { @@ -313,10 +311,8 @@ void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); force_on = true; /* disable power gating */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) force_on = false; -#endif /* DCS0/1/2/3/4 */ REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c index 6544d15917a49..f5112742edf9b 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c @@ -143,9 +143,7 @@ static const struct hwseq_private_funcs dcn314_private_funcs = { .hubp_pg_control = dcn31_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn314_update_odm, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn314_dsc_pg_control, -#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index b60e3e6787670..52a8d928458a5 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -66,7 +66,6 @@ #define FN(reg_name, field_name) \ hws->shifts->field_name, hws->masks->field_name -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn32_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -129,7 +128,6 @@ void dcn32_dsc_pg_control( if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } -#endif void dcn32_enable_power_gating_plane( struct dce_hwseq *hws, @@ -1509,7 +1507,6 @@ bool dcn32_dsc_pg_status( return pwr_status == 0; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn32_update_dsc_pg(struct dc *dc, struct dc_state *context, bool safe_to_disable) @@ -1532,7 +1529,6 @@ void dcn32_update_dsc_pg(struct dc *dc, } } } -#endif void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context) { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h index 644d141cd01e7..0303a59536737 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h @@ -107,11 +107,9 @@ bool dcn32_dsc_pg_status( struct dce_hwseq *hws, unsigned int dsc_inst); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn32_update_dsc_pg(struct dc *dc, struct dc_state *context, bool safe_to_disable); -#endif void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c index 14d700deaac31..b971356d30b18 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c @@ -115,9 +115,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = { .update_visual_confirm_color = dcn10_update_visual_confirm_color, .subvp_pipe_control_lock_fast = dcn32_subvp_pipe_control_lock_fast, .update_phantom_vp_position = dcn32_update_phantom_vp_position, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .update_dsc_pg = dcn32_update_dsc_pg, -#endif .apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom, .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless, .calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider, diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 725079acc10c6..938737a828331 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -200,11 +200,9 @@ struct resource_funcs { const struct resource_pool *pool, struct dc_3dlut **lut, struct dc_transfer_func **shaper); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status (*add_dsc_to_stream_resource)( struct dc *dc, struct dc_state *state, struct dc_stream_state *stream); -#endif void (*add_phantom_pipes)( struct dc *dc, @@ -265,9 +263,7 @@ struct resource_pool { unsigned int gsl_2:1; } gsl_groups; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct display_stream_compressor *dscs[MAX_PIPES]; -#endif unsigned int pipe_count; unsigned int underlay_pipe_index; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 42bc4a0bdf823..08c16ba52a51f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -89,7 +89,6 @@ struct link_encoder { bool usbc_combo_phy; }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct link_enc_state { uint32_t dphy_fec_en; @@ -98,7 +97,6 @@ struct link_enc_state { uint32_t dp_link_training_complete; }; -#endif enum encoder_type_select { ENCODER_TYPE_DIG = 0, @@ -107,10 +105,8 @@ enum encoder_type_select { }; struct link_encoder_funcs { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void (*read_state)( struct link_encoder *enc, struct link_enc_state *s); -#endif bool (*validate_output_with_stream)( struct link_encoder *enc, const struct dc_stream_state *stream); void (*hw_init)(struct link_encoder *enc); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 64cd9d345a359..267ace4eef8a3 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -136,9 +136,7 @@ struct crc_params { enum crc_selection selection; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT uint8_t dsc_mode; -#endif uint8_t odm_mode; bool continuous_mode; diff --git a/drivers/gpu/drm/amd/display/dc/inc/link.h b/drivers/gpu/drm/amd/display/dc/inc/link.h index 0cce49d95e261..c51665f34074d 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/link.h +++ b/drivers/gpu/drm/amd/display/dc/inc/link.h @@ -168,7 +168,6 @@ struct link_service { bool (*set_dsc_enable)(struct pipe_ctx *pipe_ctx, bool enable); bool (*update_dsc_config)(struct pipe_ctx *pipe_ctx); - /*************************** DDC **************************************/ struct ddc_service *(*create_ddc_service)( struct ddc_service_init_data *ddc_init_data); @@ -231,9 +230,9 @@ struct link_service { const struct link_resource *link_res, struct link_training_settings *lt_settings); void (*dpcd_write_rx_power_ctrl)(struct dc_link *link, bool on); + - - /*************************** DP IRQ Handler ***************************/ + /*************************** DP IRQ Handler ***************************/ bool (*dp_parse_link_loss_status)( struct dc_link *link, union hpd_irq_data *hpd_irq_dpcd_data); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index ee9fba31b877d..d7a165ab588c0 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -769,7 +769,6 @@ static void dsc_optc_config_log(struct display_stream_compressor *dsc, DC_LOG_DSC("\tslice_width %d", config->slice_width); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) { struct dc *dc = pipe_ctx->stream->ctx->dc; @@ -782,7 +781,6 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); return result; } -#endif static bool dp_set_hblank_reduction_on_rx(struct pipe_ctx *pipe_ctx) { @@ -1009,7 +1007,6 @@ bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immedi return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) { struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; @@ -1033,7 +1030,6 @@ bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) out: return result; } -#endif bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) { @@ -1918,9 +1914,7 @@ static void disable_link_dp(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal) { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_link_settings link_settings = link->cur_link_settings; -#endif if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && link->mst_stream_alloc_table.stream_count > 0) @@ -1937,13 +1931,11 @@ static void disable_link_dp(struct dc_link *link, if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) /* set the sink to SST mode after disabling the link */ enable_mst_on_sink(link, false); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (link_dp_get_encoding_format(&link_settings) == DP_8b_10b_ENCODING) { dp_set_fec_enable(link, link_res, false); dp_set_fec_ready(link, link_res, false); } -#endif } static void disable_link(struct dc_link *link, @@ -2570,13 +2562,11 @@ void link_set_dpms_on( * will be automatically set at a later time when the video is enabled * (DP_VID_STREAM_EN = 1). */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe_ctx->stream->timing.flags.DSC) { if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) link_set_dsc_enable(pipe_ctx, true); } -#endif status = enable_link(state, pipe_ctx); if (status != DC_OK) { @@ -2621,7 +2611,6 @@ void link_set_dpms_on( dc->hwss.enable_stream(pipe_ctx); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DPS PPS SDP (AKA "info frames") */ if (pipe_ctx->stream->timing.flags.DSC) { if (dc_is_dp_signal(pipe_ctx->stream->signal) || @@ -2630,7 +2619,6 @@ void link_set_dpms_on( link_set_dsc_pps_packet(pipe_ctx, true, true); } } -#endif if (dc_is_dp_signal(pipe_ctx->stream->signal)) dp_set_hblank_reduction_on_rx(pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c index 937586151e78e..975894d1f0b5c 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c @@ -144,14 +144,9 @@ static bool dp_active_dongle_validate_timing( return false; } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 && dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 && dongle_caps->dfp_cap_ext.supported) { -#else - if (dongle_caps->dfp_cap_ext.supported) { -#endif - if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000)) return false; @@ -245,12 +240,10 @@ uint32_t dp_link_bandwidth_kbps( */ link_rate_per_lane_kbps = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE; total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (dp_should_enable_fec(link)) { total_data_bw_efficiency_x10000 /= 100; total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100; } -#endif break; case DP_128b_132b_ENCODING: /* For 128b/132b encoding: diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 5b64c03c91b55..288d8d7f0a52b 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -452,7 +452,6 @@ static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link) return lttpr_max_link_rate; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link) { enum dc_link_rate cable_max_link_rate = LINK_RATE_UNKNOWN; @@ -472,7 +471,6 @@ static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link) return cable_max_link_rate; } -#endif static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) { @@ -815,7 +813,7 @@ bool edp_decide_link_settings(struct dc_link *link, return false; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + bool decide_edp_link_settings_with_dsc(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw, @@ -944,7 +942,6 @@ bool decide_edp_link_settings_with_dsc(struct dc_link *link, } return false; } -#endif static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting) { @@ -1951,7 +1948,6 @@ static bool retrieve_link_cap(struct dc_link *link) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT memset(&link->dpcd_caps.dsc_caps, '\0', sizeof(link->dpcd_caps.dsc_caps)); memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap)); @@ -2019,7 +2015,6 @@ static bool retrieve_link_cap(struct dc_link *link) } else link->wa_flags.dpia_forced_tbt3_mode = false; } -#endif if (!dpcd_read_sink_ext_caps(link)) link->dpcd_sink_ext_caps.raw = 0; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h index f46c4d3537e38..7170db5a1c13e 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h @@ -81,12 +81,10 @@ bool link_decide_link_settings( bool edp_decide_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool decide_edp_link_settings_with_dsc(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw, enum dc_link_rate max_link_rate); -#endif enum dp_link_encoding mst_decide_link_encoding_format(const struct dc_link *link); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c index 4ac00f9a2c183..49521ac4b0e85 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c @@ -135,7 +135,6 @@ void dp_set_drive_settings( dpcd_set_lane_settings(link, lt_settings, DPRX); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready) { /* FEC has to be "set ready" before the link training. @@ -177,7 +176,6 @@ enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource return status; } -#endif void dp_set_fec_enable(struct dc_link *link, const struct link_resource *link_res, bool enable) { diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c index aaf2853cb7fb1..fce83f4f94482 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c @@ -778,10 +778,8 @@ void override_training_settings( if (overrides->enhanced_framing != NULL) lt_settings->enhanced_framing = *overrides->enhanced_framing; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (link->preferred_training_settings.fec_enable != NULL) lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable; -#endif /* Check DP tunnel LTTPR mode debug option. */ if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->dc->debug.dpia_debug.bits.force_non_lttpr) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c index ee1a1c755332c..66d0fb1b9b9d2 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c @@ -136,9 +136,7 @@ void decide_8b_10b_training_settings( lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting); lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_res, link_setting); lt_settings->enhanced_framing = 1; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT lt_settings->should_set_fec_ready = true; -#endif lt_settings->disallow_per_lane_settings = true; lt_settings->always_match_dpcd_with_hw_lane_settings = true; lt_settings->lttpr_mode = dp_decide_8b_10b_lttpr_mode(link); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c index 04fdc70ae6da3..603537ffd1284 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c @@ -101,9 +101,7 @@ static enum link_training_result dpia_configure_link( struct link_training_settings *lt_settings) { enum dc_status status; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool fec_enable; -#endif DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) configuring\n - LTTPR mode(%d)\n", __func__, diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 3c7b68456753a..be714cbf66155 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -380,14 +380,10 @@ bool edp_is_ilr_optimization_required(struct dc_link *link, req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing, dc_link_get_highest_encoding_format(link)); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (!crtc_timing->flags.DSC) edp_decide_link_settings(link, &link_setting, req_bw); else decide_edp_link_settings_with_dsc(link, &link_setting, req_bw, LINK_RATE_UNKNOWN); -#else - dc_link_decide_edp_link_settings(link, &link_setting, req_bw); -#endif if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate || lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) { diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c index d3d3fadce5dab..e7a90a437fffb 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c @@ -124,7 +124,6 @@ void optc2_set_gsl_source_select( } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: Bytes per pixel in u3.28 format @@ -146,7 +145,6 @@ void optc2_set_dsc_config(struct timing_generator *optc, REG_UPDATE(OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, dsc_slice_width); } -#endif /* Get DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format @@ -489,14 +487,9 @@ bool optc2_configure_crc(struct timing_generator *optc, { struct optc *optc1 = DCN10TG_FROM_TG(optc); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT REG_SET_2(OTG_CRC_CNTL2, 0, OTG_CRC_DSC_MODE, params->dsc_mode, OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode); -#else - REG_SET(OTG_CRC_CNTL2, 0, - OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode); -#endif return optc1_configure_crc(optc, params); } @@ -555,9 +548,7 @@ static const struct timing_generator_funcs dcn20_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc2_set_dsc_config, -#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = optc2_set_dwb_source, .set_odm_bypass = optc2_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h index 09f16dc1c5048..928e110b95fb5 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h @@ -98,12 +98,10 @@ void optc2_set_gsl_source_select(struct timing_generator *optc, int group_idx, uint32_t gsl_ready_signal); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void optc2_set_dsc_config(struct timing_generator *optc, enum optc_dsc_mode dsc_mode, uint32_t dsc_bytes_per_pixel, uint32_t dsc_slice_width); -#endif void optc2_get_dsc_status(struct timing_generator *optc, uint32_t *dsc_mode); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c index fcc5d6138e5a6..772a8bfb949c1 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c @@ -172,9 +172,7 @@ static const struct timing_generator_funcs dcn201_tg_funcs = { .clear_optc_underflow = optc1_clear_optc_underflow, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc2_set_dsc_config, -#endif .set_dwb_source = NULL, .get_optc_source = optc201_get_optc_source, .set_vtg_params = optc1_set_vtg_params, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c index ddf112c87267d..ee4665aa49e9f 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c @@ -176,7 +176,6 @@ void optc3_set_vtotal_change_limit(struct timing_generator *optc, } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: Bytes per pixel in u3.28 format @@ -192,7 +191,6 @@ void optc3_set_dsc_config(struct timing_generator *optc, optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel, dsc_slice_width); REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0); } -#endif void optc3_set_odm_bypass(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing) @@ -402,9 +400,7 @@ static const struct timing_generator_funcs dcn30_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, -#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .set_odm_bypass = optc3_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h index f3ca2df9a3a00..e2303f9eaf13b 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h @@ -348,12 +348,10 @@ void optc3_program_blank_color(struct timing_generator *optc, void optc3_set_vtotal_change_limit(struct timing_generator *optc, uint32_t limit); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void optc3_set_dsc_config(struct timing_generator *optc, enum optc_dsc_mode dsc_mode, uint32_t dsc_bytes_per_pixel, uint32_t dsc_slice_width); -#endif void optc3_set_timing_db_mode(struct timing_generator *optc, bool enable); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c index 1b7d2879b084d..4f1830ba619f0 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c @@ -359,9 +359,7 @@ static const struct timing_generator_funcs dcn31_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, -#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .set_odm_bypass = optc3_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c index 32debad43c8c1..4a2caca372556 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c @@ -237,9 +237,7 @@ static const struct timing_generator_funcs dcn314_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc1_configure_crc, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, -#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .get_optc_source = optc2_get_optc_source, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index 17ddcaeaa3636..368d84acc17ae 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -344,9 +344,7 @@ static const struct timing_generator_funcs dcn32_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc1_configure_crc, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, -#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .set_odm_bypass = optc32_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index 8b14bc26e984e..cce06057e9e7c 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -618,7 +618,6 @@ static int map_transmitter_id_to_phy_instance( } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -640,7 +639,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dccg_registers dccg_regs = { DCCG_REG_LIST_DCN2() @@ -664,9 +662,7 @@ static const struct resource_caps res_cap_nv10 = { .num_dwb = 1, .num_ddc = 6, .num_vmid = 16, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 6, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -704,9 +700,7 @@ static const struct resource_caps res_cap_nv14 = { .num_dwb = 1, .num_ddc = 5, .num_vmid = 16, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 5, -#endif }; static const struct dc_debug_options debug_defaults_drv = { @@ -1062,7 +1056,6 @@ void dcn20_clock_source_destroy(struct clock_source **clk_src) *clk_src = NULL; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct display_stream_compressor *dcn20_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1083,7 +1076,6 @@ void dcn20_dsc_destroy(struct display_stream_compressor **dsc) kfree(container_of(*dsc, struct dcn20_dsc, base)); *dsc = NULL; } -#endif static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) { @@ -1096,12 +1088,10 @@ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1329,7 +1319,6 @@ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state return status; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn20_acquire_dsc(const struct dc *dc, struct resource_context *res_ctx, struct display_stream_compressor **dsc, @@ -1434,7 +1423,6 @@ static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, else return DC_OK; } -#endif enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { @@ -1445,11 +1433,9 @@ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, if (result == DC_OK) result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Get a DSC if required and available */ if (result == DC_OK && dc_stream->timing.flags.DSC) result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream); -#endif if (result == DC_OK) result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream); @@ -1462,9 +1448,7 @@ enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ { enum dc_status result = DC_OK; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream); -#endif return result; } @@ -1503,9 +1487,7 @@ bool dcn20_split_stream_for_odm( next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT next_odm_pipe->stream_res.dsc = NULL; -#endif if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe; @@ -1532,15 +1514,12 @@ bool dcn20_split_stream_for_odm( next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; else next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) { dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx); ASSERT(next_odm_pipe->stream_res.dsc); if (next_odm_pipe->stream_res.dsc == NULL) return false; } -#endif - return true; } @@ -1563,9 +1542,7 @@ void dcn20_split_stream_for_mpc( secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT secondary_pipe->stream_res.dsc = NULL; -#endif if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { ASSERT(!secondary_pipe->bottom_pipe); secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; @@ -1656,7 +1633,6 @@ void dcn20_set_mcif_arb_params( } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) { int i; @@ -1691,7 +1667,6 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) } return true; } -#endif struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, struct resource_context *res_ctx, @@ -1795,10 +1770,8 @@ void dcn20_merge_pipes_for_validate( odm_pipe->bottom_pipe = NULL; odm_pipe->prev_odm_pipe = NULL; odm_pipe->next_odm_pipe = NULL; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (odm_pipe->stream_res.dsc) dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); -#endif /* Clear plane_res and stream_res */ memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res)); @@ -2244,9 +2217,7 @@ static const struct resource_funcs dcn20_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn20_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, @@ -2714,7 +2685,6 @@ static bool dcn20_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn20_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2723,7 +2693,6 @@ static bool dcn20_resource_construct( goto create_fail; } } -#endif if (!dcn20_dwbc_create(ctx, &pool->base)) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h index 072bfaa3185c8..e997d35a8b86e 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h @@ -132,9 +132,7 @@ int dcn20_validate_apply_pipe_split_flags( void dcn20_release_dsc(struct resource_context *res_ctx, const struct resource_pool *pool, struct display_stream_compressor **dsc); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx); -#endif void dcn20_split_stream_for_mpc( struct resource_context *res_ctx, const struct resource_pool *pool, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c index d9aac402615f5..e4a1338d21e01 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c @@ -1072,9 +1072,7 @@ static struct resource_funcs dcn201_res_pool_funcs = { .validate_bandwidth = dcn20_validate_bandwidth, .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, .add_stream_to_ctx = dcn20_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = NULL, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .acquire_free_pipe_as_secondary_dpp_pipe = dcn201_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 584e7e429fb97..1f94e4afca1e1 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -362,7 +362,6 @@ static const struct dcn20_vmid_mask vmid_masks = { DCN20_VMID_MASK_SH_LIST(_MASK) }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -384,7 +383,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif #define ipp_regs(id)\ [id] = {\ @@ -580,9 +578,7 @@ static const struct resource_caps res_cap_rn = { .num_dwb = 1, .num_ddc = 5, .num_vmid = 16, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -665,12 +661,10 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -905,14 +899,12 @@ bool dcn21_fast_validate_bw(struct dc *dc, ASSERT(0); } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Actual dsc count per stream dsc validation*/ if (!dcn20_validate_dsc(dc, context)) { context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; goto validate_fail; } -#endif *vlevel_out = vlevel; @@ -1093,7 +1085,6 @@ static void read_dce_straps( } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx, uint32_t inst) { @@ -1108,7 +1099,6 @@ static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) { @@ -1377,9 +1367,7 @@ static const struct resource_funcs dcn21_res_pool_funcs = { .validate_bandwidth = dcn21_validate_bandwidth, .populate_dml_pipes = dcn21_populate_dml_pipes_from_context, .add_stream_to_ctx = dcn20_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, @@ -1664,7 +1652,6 @@ static bool dcn21_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn21_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -1673,7 +1660,6 @@ static bool dcn21_resource_construct( goto create_fail; } } -#endif if (!dcn20_dwbc_create(ctx, &pool->base)) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c index 112e0ab4b226c..895349d9ca07c 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c @@ -46,9 +46,7 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" -#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" @@ -513,7 +511,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { DSC_REG_LIST_DCN20(id)\ } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static const struct dcn20_dsc_registers dsc_regs[] = { dsc_regsDCN20(0), dsc_regsDCN20(1), @@ -530,7 +527,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -681,9 +677,7 @@ static const struct resource_caps res_cap_dcn3 = { .num_ddc = 6, .num_vmid = 16, .num_mpc_3dlut = 3, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 6, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -1087,12 +1081,10 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1270,7 +1262,6 @@ static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn30_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1285,7 +1276,6 @@ static struct display_stream_compressor *dcn30_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { @@ -1546,9 +1536,7 @@ static bool dcn30_split_stream_for_mpc_or_odm( sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT sec_pipe->stream_res.dsc = NULL; -#endif if (odm) { if (pri_pipe->next_odm_pipe) { ASSERT(pri_pipe->next_odm_pipe != sec_pipe); @@ -1570,14 +1558,12 @@ static bool dcn30_split_stream_for_mpc_or_odm( sec_pipe->stream_res.opp = pool->opps[pipe_idx]; else sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (sec_pipe->stream->timing.flags.DSC == 1) { dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); ASSERT(sec_pipe->stream_res.dsc); if (sec_pipe->stream_res.dsc == NULL) return false; } -#endif } else { if (pri_pipe->bottom_pipe) { ASSERT(pri_pipe->bottom_pipe != sec_pipe); @@ -1752,10 +1738,8 @@ noinline bool dcn30_internal_validate_bw( pipe->stream = NULL; pipe->top_pipe = NULL; pipe->prev_odm_pipe = NULL; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe->stream_res.dsc) dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); -#endif memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); repopulate_pipes = true; @@ -1874,13 +1858,11 @@ noinline bool dcn30_internal_validate_bw( } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Actual dsc count per stream dsc validation*/ if (!dcn20_validate_dsc(dc, context)) { vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; goto validate_fail; } -#endif if (repopulate_pipes) pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); @@ -2257,9 +2239,7 @@ static const struct resource_funcs dcn30_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -2552,7 +2532,6 @@ static bool dcn30_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn30_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2561,7 +2540,6 @@ static bool dcn30_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn30_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index 6c0c8b6cb45aa..7cbf7cbc7d9db 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -47,9 +47,7 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" -#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dce/dce_clock_source.h" @@ -491,7 +489,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -510,7 +507,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -652,9 +648,7 @@ static struct resource_caps res_cap_dcn301 = { .num_ddc = 4, .num_vmid = 16, .num_mpc_3dlut = 2, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -1058,12 +1052,10 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1230,7 +1222,6 @@ static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn301_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1245,7 +1236,6 @@ static struct display_stream_compressor *dcn301_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif static void dcn301_destroy_resource_pool(struct resource_pool **pool) { @@ -1401,9 +1391,7 @@ static struct resource_funcs dcn301_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -1663,7 +1651,6 @@ static bool dcn301_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn301_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -1672,7 +1659,6 @@ static bool dcn301_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn301_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c index 1d14b741b7daf..3345068a878c1 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c @@ -40,9 +40,7 @@ #include "dcn30/dcn30_optc.h" #include "dcn30/dcn30_resource.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" -#endif #include "dcn20/dcn20_resource.h" #include "dml/dcn30/dcn30_fpu.h" @@ -130,9 +128,7 @@ static const struct resource_caps res_cap_dcn302 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 5, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -661,7 +657,6 @@ static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int n return &mpc30->base; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = { DSC_REG_LIST_DCN20(id) } @@ -693,7 +688,6 @@ static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ct dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif #define dwbc_regs_dcn3(id)\ [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } @@ -1009,12 +1003,10 @@ static void dcn302_resource_destruct(struct resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { if (pool->dscs[i] != NULL) dcn20_dsc_destroy(&pool->dscs[i]); } -#endif if (pool->mpc != NULL) { kfree(TO_DCN20_MPC(pool->mpc)); @@ -1149,9 +1141,7 @@ static struct resource_funcs dcn302_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -1439,7 +1429,6 @@ static bool dcn302_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { pool->dscs[i] = dcn302_dsc_create(ctx, i); if (pool->dscs[i] == NULL) { @@ -1448,7 +1437,6 @@ static bool dcn302_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn302_dwbc_create(ctx, pool)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c index 48218ab297e6f..3479e1eab4cd7 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c @@ -126,9 +126,7 @@ static const struct resource_caps res_cap_dcn303 = { .num_ddc = 2, .num_vmid = 16, .num_mpc_3dlut = 1, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 2, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -624,7 +622,6 @@ static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int n return &mpc30->base; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = { DSC_REG_LIST_DCN20(id) } @@ -653,7 +650,6 @@ static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ct dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif #define dwbc_regs_dcn3(id)\ [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } @@ -952,12 +948,10 @@ static void dcn303_resource_destruct(struct resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { if (pool->dscs[i] != NULL) dcn20_dsc_destroy(&pool->dscs[i]); } -#endif if (pool->mpc != NULL) { kfree(TO_DCN20_MPC(pool->mpc)); @@ -1092,9 +1086,7 @@ static struct resource_funcs dcn303_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -1370,7 +1362,6 @@ static bool dcn303_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { pool->dscs[i] = dcn303_dsc_create(ctx, i); if (pool->dscs[i] == NULL) { @@ -1379,7 +1370,6 @@ static bool dcn303_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn303_dwbc_create(ctx, pool)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c index 60df1c2308402..ca17e5d8fdc2a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c @@ -563,7 +563,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -582,7 +581,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -826,9 +824,7 @@ static const struct resource_caps res_cap_dcn31 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -1386,12 +1382,10 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1566,7 +1560,6 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1581,7 +1574,6 @@ static struct display_stream_compressor *dcn31_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif static void dcn31_destroy_resource_pool(struct resource_pool **pool) { @@ -1847,9 +1839,7 @@ static struct resource_funcs dcn31_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn31_set_mcif_arb_params, @@ -2150,7 +2140,6 @@ static bool dcn31_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn31_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2159,7 +2148,6 @@ static bool dcn31_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c index f45f682fc21a5..663c49cce4aa3 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c @@ -574,7 +574,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { DSC_REG_LIST_DCN20(id)\ } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static const struct dcn20_dsc_registers dsc_regs[] = { dsc_regsDCN314(0), dsc_regsDCN314(1), @@ -589,7 +588,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -1442,12 +1440,10 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1621,7 +1617,6 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn314_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1636,7 +1631,6 @@ static struct display_stream_compressor *dcn314_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif static void dcn314_destroy_resource_pool(struct resource_pool **pool) { @@ -1774,9 +1768,7 @@ static struct resource_funcs dcn314_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -2071,7 +2063,6 @@ static bool dcn314_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn314_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2080,7 +2071,6 @@ static bool dcn314_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index 44a02ea5f72d8..82cc78c291d82 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -49,9 +49,7 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" -#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" @@ -568,7 +566,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -587,7 +584,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -827,9 +823,7 @@ static const struct resource_caps res_cap_dcn31 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -1388,12 +1382,10 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1568,7 +1560,6 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1583,7 +1574,6 @@ static struct display_stream_compressor *dcn31_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif static void dcn315_destroy_resource_pool(struct resource_pool **pool) { @@ -1842,9 +1832,7 @@ static struct resource_funcs dcn315_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn31_set_mcif_arb_params, @@ -2100,7 +2088,6 @@ static bool dcn315_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn31_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2109,7 +2096,6 @@ static bool dcn315_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c index e35af428f0853..ad65ec167cf0b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c @@ -49,9 +49,7 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" -#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" @@ -560,7 +558,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -579,7 +576,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -823,9 +819,7 @@ static const struct resource_caps res_cap_dcn31 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -1385,12 +1379,10 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1562,7 +1554,6 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1577,7 +1568,6 @@ static struct display_stream_compressor *dcn31_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif static void dcn316_destroy_resource_pool(struct resource_pool **pool) { @@ -1720,9 +1710,7 @@ static struct resource_funcs dcn316_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn31_set_mcif_arb_params, @@ -1969,7 +1957,6 @@ static bool dcn316_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn31_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -1978,7 +1965,6 @@ static bool dcn316_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index f36507b166f7a..9917b366f00c6 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -438,7 +438,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { #define dsc_regsDCN20_init(id)\ DSC_REG_LIST_DCN20_RI(id) -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct dcn20_dsc_registers dsc_regs[4]; static const struct dcn20_dsc_shift dsc_shift = { @@ -448,7 +447,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static struct dcn30_mpc_registers mpc_regs; @@ -1389,12 +1387,10 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1562,7 +1558,6 @@ static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn32_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1587,7 +1582,6 @@ static struct display_stream_compressor *dcn32_dsc_create( return &dsc->base; } -#endif static void dcn32_destroy_resource_pool(struct resource_pool **pool) { @@ -2104,9 +2098,7 @@ static struct resource_funcs dcn32_res_pool_funcs = { .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -2452,7 +2444,6 @@ static bool dcn32_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* DSCs */ for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn32_dsc_create(ctx, i); @@ -2462,7 +2453,6 @@ static bool dcn32_resource_construct( goto create_fail; } } -#endif /* DWB */ if (!dcn32_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c index eb78191838c7c..f5a4e97c40ced 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c @@ -128,10 +128,8 @@ void dcn32_merge_pipes_for_subvp(struct dc *dc, pipe->stream = NULL; pipe->top_pipe = NULL; pipe->prev_odm_pipe = NULL; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe->stream_res.dsc) dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); -#endif memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c index 061c0907d802d..8d4b37265e725 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c @@ -445,7 +445,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; - static struct dcn30_mpc_registers mpc_regs; #define dcn_mpc_regs_init()\ MPC_REG_LIST_DCN3_2_RI(0),\ @@ -1373,7 +1372,6 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } - if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); pool->base.mpc = NULL; diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c index 6f138e445421b..6ffc74fc9dcd8 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c @@ -88,12 +88,10 @@ static void virtual_stream_encoder_reset_hdmi_stream_attribute( struct stream_encoder *enc) {} -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static void virtual_enc_dp_set_odm_combine( struct stream_encoder *enc, bool odm_combine) {} -#endif static void virtual_dig_connect_to_otg( struct stream_encoder *enc, @@ -106,20 +104,16 @@ static void virtual_setup_stereo_sync( bool enable) {} -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static void virtual_stream_encoder_set_dsc_pps_info_packet( struct stream_encoder *enc, bool enable, uint8_t *dsc_packed_pps, bool immediate_update) {} -#endif static const struct stream_encoder_funcs virtual_str_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dp_set_odm_combine = virtual_enc_dp_set_odm_combine, -#endif .dp_set_stream_attribute = virtual_stream_encoder_dp_set_stream_attribute, .hdmi_set_stream_attribute = @@ -148,9 +142,7 @@ static const struct stream_encoder_funcs virtual_str_enc_funcs = { .hdmi_reset_stream_attribute = virtual_stream_encoder_reset_hdmi_stream_attribute, .dig_connect_to_otg = virtual_dig_connect_to_otg, .setup_stereo_sync = virtual_setup_stereo_sync, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dp_set_dsc_pps_info_packet = virtual_stream_encoder_set_dsc_pps_info_packet, -#endif }; bool virtual_stream_encoder_construct( diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index a0e67352e5b38..c90d2e3182c23 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -204,9 +204,6 @@ ifndef CONFIG_ARM64 ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) export CONFIG_DRM_AMD_DC_DCN=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN - -export CONFIG_DRM_AMD_DC_DSC_SUPPORT=y -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DSC_SUPPORT endif endif diff --git a/include/kcl/kcl_drm_dsc_helper.h b/include/kcl/kcl_drm_dsc_helper.h index 207bc76eb1195..0c61de575753d 100644 --- a/include/kcl/kcl_drm_dsc_helper.h +++ b/include/kcl/kcl_drm_dsc_helper.h @@ -3,8 +3,6 @@ #ifndef _KCL_KCL_DRM_DSC_HELPER_H #define _KCL_KCL_DRM_DSC_HELPER_H -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT - #include #include @@ -17,6 +15,5 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); #endif -#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ #endif /* _KCL_KCL_DRM_DSC_HELPER_H */ From a1a1dd40c14ce2debdbd1d2f55c96c8bbaca8b41 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 17 Feb 2023 12:44:59 +0800 Subject: [PATCH 0979/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_FRAMEBUFFER_FORMAT Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 4 ---- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 17 -------------- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 17 -------------- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 17 -------------- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 17 -------------- drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c | 6 +---- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ---------- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 23 +------------------ drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../drm/amd/dkms/m4/drm-framebuffer-format.m4 | 21 ----------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 11 files changed, 2 insertions(+), 136 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 1d531c41fa5e6..fa30102663de1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -276,11 +276,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper, DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base); DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo)); -#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) - DRM_INFO("fb depth is %d\n", fb->depth); -#else DRM_INFO("fb depth is %d\n", fb->format->depth); -#endif DRM_INFO("pitch is %d\n", fb->pitches[0]); vga_switcheroo_client_fb_set(adev->pdev, info); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index b1462aecffbda..8a9f84d22b57c 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -244,13 +244,8 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev, GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0); WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); /* update pitch */ -#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb->pitches[0] / fb->format->cpp[0]); -#else - WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, - fb->pitches[0] / (fb->bits_per_pixel / 8)); -#endif /* update the primary scanout address */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -1906,11 +1901,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); -#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) - switch (target_fb->pixel_format) { -#else switch (target_fb->format->format) { -#endif case DRM_FORMAT_C8: fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); @@ -1994,11 +1985,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, break; default: DRM_ERROR("Unsupported screen format %p4cc\n", -#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) &target_fb->format->format); -#else - &target_fb->pixel_format); -#endif return -EINVAL; } @@ -2073,11 +2060,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); -#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) - fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); -#else fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; -#endif WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); dce_v10_0_grph_enable(crtc, true); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 52c71b28a940b..84fa0f8902dc4 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -268,13 +268,8 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev, GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0); WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); /* update pitch */ -#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb->pitches[0] / fb->format->cpp[0]); -#else - WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, - fb->pitches[0] / (fb->bits_per_pixel / 8)); -#endif /* update the scanout addresses */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -1956,11 +1951,7 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); -#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) - switch (target_fb->pixel_format) { -#else switch (target_fb->format->format) { -#endif case DRM_FORMAT_C8: fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); @@ -2044,11 +2035,7 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, break; default: DRM_ERROR("Unsupported screen format %p4cc\n", -#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) &target_fb->format->format); -#else - &target_fb->pixel_format); -#endif return -EINVAL; } @@ -2123,11 +2110,7 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); -#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) - fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); -#else fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; -#endif WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); dce_v11_0_grph_enable(crtc, true); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index ceb1ab8d25985..c2ac8ef3b15cd 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -208,13 +208,8 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev, WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); /* update pitch */ -#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb->pitches[0] / fb->format->cpp[0]); -#else - WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, - fb->pitches[0] / (fb->bits_per_pixel / 8)); -#endif /* update the scanout addresses */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -1941,11 +1936,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, amdgpu_bo_get_tiling_flags(abo, &tiling_flags); amdgpu_bo_unreserve(abo); -#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) - switch (target_fb->pixel_format) { -#else switch (target_fb->format->format) { -#endif case DRM_FORMAT_C8: fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); @@ -2021,11 +2012,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, break; default: DRM_ERROR("Unsupported screen format %p4cc\n", -#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) &target_fb->format->format); -#else - &target_fb->pixel_format); -#endif return -EINVAL; } @@ -2088,11 +2075,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); -#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) - fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); -#else fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; -#endif WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); dce_v6_0_grph_enable(crtc, true); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 1a549b474ebf9..3364aa98e33bb 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -191,13 +191,8 @@ static void dce_v8_0_page_flip(struct amdgpu_device *adev, /* flip at hsync for async, default is vsync */ WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); -#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb->pitches[0] / fb->format->cpp[0]); -#else - WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, - fb->pitches[0] / (fb->bits_per_pixel / 8)); -#endif /* update the primary scanout addresses */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -1852,11 +1847,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); -#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) - switch (target_fb->pixel_format) { -#else switch (target_fb->format->format) { -#endif case DRM_FORMAT_C8: fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); @@ -1932,11 +1923,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, break; default: DRM_ERROR("Unsupported screen format %p4cc\n", -#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) &target_fb->format->format); -#else - &target_fb->pixel_format); -#endif return -EINVAL; } @@ -1999,11 +1986,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); -#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) - fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); -#else fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; -#endif WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); dce_v8_0_grph_enable(crtc, true); diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c index bdd63a1cc9b36..11e5390896f68 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -42,11 +42,7 @@ void drm_fb_helper_fill_info(struct fb_info *info, { struct drm_framebuffer *fb = fb_helper->fb; -#ifdef HAVE_DRM_FRAMEBUFFER_FORMAT drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth); -#else - drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth); -#endif drm_fb_helper_fill_var(info, fb_helper, sizes->fb_width, sizes->fb_height); @@ -56,4 +52,4 @@ void drm_fb_helper_fill_info(struct fb_info *info, } EXPORT_SYMBOL(drm_fb_helper_fill_info); -#endif \ No newline at end of file +#endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b4f708b0170b4..b2049384db93e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5822,11 +5822,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, memset(plane_info, 0, sizeof(*plane_info)); -#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT - switch (fb->pixel_format) { -#else switch (fb->format->format) { -#endif case DRM_FORMAT_C8: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; @@ -5882,11 +5878,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, default: drm_err(adev_to_drm(adev), "Unsupported screen format %p4cc\n", -#ifdef HAVE_DRM_FRAMEBUFFER_FORMAT &fb->format->format); -#else - &fb->pixel_format); -#endif return -EINVAL; } @@ -11333,11 +11325,7 @@ static bool should_reset_plane(struct drm_atomic_state *state, continue; /* Pixel format changes can require bandwidth updates. */ -#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT - if (old_other_state->fb->pixel_format != new_other_state->fb->pixel_format) -#else if (old_other_state->fb->format != new_other_state->fb->format) -#endif return true; old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index fbf9bd2c0bda8..2ef798c2c3a07 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -874,11 +874,7 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, plane_size->surface_size.width = fb->width; plane_size->surface_size.height = fb->height; plane_size->surface_pitch = -#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT - fb->pitches[0] / (fb->bits_per_pixel / 8); -#else fb->pitches[0] / fb->format->cpp[0]; -#endif address->type = PLN_ADDR_TYPE_GRAPHICS; address->grph.addr.low_part = lower_32_bits(addr); @@ -892,11 +888,7 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, plane_size->surface_size.width = fb->width; plane_size->surface_size.height = fb->height; plane_size->surface_pitch = -#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT - fb->pitches[0] / (fb->bits_per_pixel / 8); -#else fb->pitches[0] / fb->format->cpp[0]; -#endif plane_size->chroma_size.x = 0; plane_size->chroma_size.y = 0; @@ -905,11 +897,7 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, plane_size->chroma_size.height = fb->height / 2; plane_size->chroma_pitch = -#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT - fb->pitches[1] / (fb->bits_per_pixel / 8)/2; -#else fb->pitches[1] / fb->format->cpp[1]; -#endif address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; address->video_progressive.luma_addr.low_part = @@ -1077,11 +1065,7 @@ static void amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_device *dev, /* Caps for all supported planes are the same on DCE and DCN 1 - 3 */ struct dc_plane_cap *plane_cap = &dc->caps.planes[0]; -#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT - switch (fb->pixel_format) { -#else switch (fb->format->format) { -#endif case DRM_FORMAT_P010: case DRM_FORMAT_NV12: case DRM_FORMAT_NV21: @@ -1194,12 +1178,7 @@ int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, */ if (((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) && - (state->fb && -#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT - state->fb->pixel_format == DRM_FORMAT_NV12 && -#else - state->fb->format->format == DRM_FORMAT_NV12 && -#endif + (state->fb && state->fb->format->format == DRM_FORMAT_NV12 && (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0))) return -EINVAL; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index fc5045038fa80..3fb946701f54b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -575,9 +575,6 @@ /* drm_format_info.block_w and rm_format_info.block_h is available */ #define HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED 1 -/* whether struct drm_framebuffer have format */ -#define HAVE_DRM_FRAMEBUFFER_FORMAT 1 - /* drm_gem_plane_helper_prepare_fb() is available */ #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 deleted file mode 100644 index 5a219b26d81bb..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 +++ /dev/null @@ -1,21 +0,0 @@ -dnl # -dnl # commit e14c23c647abfc1fed96a55ba376cd9675a54098 -dnl # drm: Store a pointer to drm_format_info under drm_framebuffer -dnl # -AC_DEFUN([AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; - #include - #endif - #include - ], [ - struct drm_framebuffer *foo = NULL; - foo->format = NULL; - ], [ - AC_DEFINE(HAVE_DRM_FRAMEBUFFER_FORMAT, 1, - [whether struct drm_framebuffer have format]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5212943ec5a1c..4ea9cda9b43f5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -93,7 +93,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_MODE_INIT - AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS From 06b8969be90db35112cb267750870fceff3991c7 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 20 Feb 2023 10:46:05 +0800 Subject: [PATCH 0980/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_GET_FORMAT_INFO Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 6 ------ drivers/gpu/drm/amd/dkms/config/config.h | 6 ------ drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 | 13 ------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 4 files changed, 26 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index fa30102663de1..09b60070309e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -123,9 +123,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **gobj_p) { -#ifdef HAVE_DRM_GET_FORMAT_INFO const struct drm_format_info *info; -#endif struct amdgpu_device *adev = rfbdev->adev; struct drm_gem_object *gobj = NULL; struct amdgpu_bo *abo = NULL; @@ -139,12 +137,8 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | AMDGPU_GEM_CREATE_VRAM_CLEARED; -#ifdef HAVE_DRM_GET_FORMAT_INFO info = drm_get_format_info(adev_to_drm(adev), mode_cmd); cpp = info->cpp[0]; -#else - cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0); -#endif /* need to align pitch with crtc limits */ mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3fb946701f54b..f40e35e902be5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -599,12 +599,6 @@ /* drm_gen_fb_init_with_funcs() is available */ #define HAVE_DRM_GEN_FB_INIT_WITH_FUNCS 1 -/* drm_get_format_info() is available */ -#define HAVE_DRM_GET_FORMAT_INFO 1 - -/* drm_get_format_name() has i,p interface */ -/* #undef HAVE_DRM_GET_FORMAT_NAME_I_P */ - /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 deleted file mode 100644 index 5c797f77620f5..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 +++ /dev/null @@ -1,13 +0,0 @@ -dnl # -dnl # commit v4.11-rc1-237-g6a0f9ebfc5e7 -dnl # drm: Add mode_config .get_format_info() hook -dnl # -AC_DEFUN([AC_AMDGPU_DRM_GET_FORMAT_INFO], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_get_format_info], - [drivers/gpu/drm/drm_fourcc.c], [ - AC_DEFINE(HAVE_DRM_GET_FORMAT_INFO, 1, - [drm_get_format_info() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4ea9cda9b43f5..80010f58ecdd8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -84,7 +84,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_FB_HELPER_INIT - AC_AMDGPU_DRM_GET_FORMAT_INFO AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS From 798cae28a3fb8fcfe660ebf4237899176679b189 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 20 Feb 2023 10:50:09 +0800 Subject: [PATCH 0981/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE_P_P_P Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ---- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- ...drm-hdmi-vendor-infoframe-from-display-mode.m4 | 15 --------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 4 files changed, 23 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-hdmi-vendor-infoframe-from-display-mode.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b2049384db93e..e5ea68ecea485 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6458,16 +6458,12 @@ static void fill_stream_properties_from_drm_display_mode( drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, mode_in); #endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ timing_out->vic = avi_frame.video_code; -#if defined(HAVE_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); if (err < 0) drm_warn_once(connector->dev, "Failed to setup vendor infoframe on connector %s: %zd\n", connector->name, err); -#else - drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, mode_in); -#endif timing_out->hdmi_vic = hv_frame.vic; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f40e35e902be5..204b69961cd3f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -608,9 +608,6 @@ /* drm_hdmi_avi_infoframe_from_display_mode() has p,p,p interface */ #define HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P 1 -/* drm_hdmi_vendor_infoframe_from_display_mode() has p,p,p interface */ -#define HAVE_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE_P_P_P 1 - /* drm_helper_force_disable_all() is available */ #define HAVE_DRM_HELPER_FORCE_DISABLE_ALL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdmi-vendor-infoframe-from-display-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdmi-vendor-infoframe-from-display-mode.m4 deleted file mode 100644 index c9f2c8a635e43..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-hdmi-vendor-infoframe-from-display-mode.m4 +++ /dev/null @@ -1,15 +0,0 @@ -dnl f1781e9bb2dd2305d8d7ffbede1888ae22119557 -dnl # drm/edid: Allow HDMI infoframe without VIC or S3D -dnl # -AC_DEFUN([AC_AMDGPU_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_hdmi_vendor_infoframe_from_display_mode(NULL, NULL, NULL); - ], [drm_hdmi_vendor_infoframe_from_display_mode], [drivers/gpu/drm/drm_edid.c], [ - AC_DEFINE(HAVE_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE_P_P_P, 1, - [drm_hdmi_vendor_infoframe_from_display_mode() has p,p,p interface]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 80010f58ecdd8..6e0948decbc20 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -93,7 +93,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_MODE_INIT AC_AMDGPU_DRM_DP_MST_TOPOLOGY - AC_AMDGPU_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK From 1f4593f5d78d40a1f89c6bd28d28f61dc4f0633b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 20 Feb 2023 10:55:32 +0800 Subject: [PATCH 0982/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/dkms/config/config.h | 6 ------ .../dkms/m4/drm_helper_mode_fill_fb_struct.m4 | 16 ---------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/backport/kcl_drm_fb.h | 13 ------------- 4 files changed, 36 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 204b69961cd3f..95d21bf481c6f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -611,12 +611,6 @@ /* drm_helper_force_disable_all() is available */ #define HAVE_DRM_HELPER_FORCE_DISABLE_ALL 1 -/* drm_helper_mode_fill_fb_struct() wants dev arg */ -#define HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV 1 - -/* drm_is_current_master() is available */ -#define HAVE_DRM_IS_CURRENT_MASTER 1 - /* drm_kms_helper_connector_hotplug_event() function is available */ #define HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 deleted file mode 100644 index 3d662319c8e11..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # v4.9-rc8-1647-g95bce7601581 drm: Populate fb->dev from drm_helper_mode_fill_fb_struct() -dnl # v4.9-rc8-1643-ga3f913ca9892 drm: Pass 'dev' to drm_helper_mode_fill_fb_struct() -dnl # -AC_DEFUN([AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - drm_helper_mode_fill_fb_struct(NULL, NULL, NULL); - ], [ - AC_DEFINE(HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV, 1, - [drm_helper_mode_fill_fb_struct() wants dev arg]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6e0948decbc20..46005b06c6fb3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -82,7 +82,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_FB_HELPER_FILL_INFO - AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_FB_HELPER_INIT AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index 1269be6e2d9c9..e14f228fc86fb 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -25,19 +25,6 @@ #include #include -#ifndef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV -static inline -void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, - struct drm_framebuffer *fb, - const struct drm_mode_fb_cmd2 *mode_cmd) -{ - fb->dev = dev; - drm_helper_mode_fill_fb_struct(fb, mode_cmd); -} - -#define drm_helper_mode_fill_fb_struct _kcl_drm_helper_mode_fill_fb_struct -#endif - #if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) #define AMDKCL_DRM_FBDEV_GENERIC #endif From d3c122f78cf8e2e6d4f52d71b2168c57ef5b44a9 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 2 Jan 2024 16:53:11 +0800 Subject: [PATCH 0983/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_KMS_HELPER_IS_POLL_WORKER Signed-off-by: Leslie Shi Reviewed-by: Ma Jun Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 7 ------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 | 13 ------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 4 files changed, 24 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 250cfb0dcf20f..470ae8a879558 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -40,13 +40,6 @@ #include -#ifndef HAVE_DRM_KMS_HELPER_IS_POLL_WORKER -bool inline drm_kms_helper_is_poll_worker(void) -{ - return false; -} -#endif - void amdgpu_connector_hotplug(struct drm_connector *connector) { struct drm_device *dev = connector->dev; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 95d21bf481c6f..25abf2431cefd 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -614,9 +614,6 @@ /* drm_kms_helper_connector_hotplug_event() function is available */ #define HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT 1 -/* drm_kms_helper_is_poll_worker() is available */ -#define HAVE_DRM_KMS_HELPER_IS_POLL_WORKER 1 - /* drm_memcpy_from_wc() is availablea */ /* #undef HAVE_DRM_MEMCPY_FROM_WC */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 deleted file mode 100644 index dda9b0e2e2c79..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 +++ /dev/null @@ -1,13 +0,0 @@ -dnl # -dnl # commit v4.15-rc8-13-g25c058ccaf2e -dnl # drm: Allow determining if current task is output poll worker -dnl # -AC_DEFUN([AC_AMDGPU_DRM_KMS_HELPER_IS_POLL_WORKER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_kms_helper_is_poll_worker], - [drivers/gpu/drm/drm_probe_helper.c], [ - AC_DEFINE(HAVE_DRM_KMS_HELPER_IS_POLL_WORKER, 1, - [drm_kms_helper_is_poll_worker() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 46005b06c6fb3..8045c2cc6c8ec 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -87,7 +87,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_EDID_TO_ELD AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_EDID - AC_AMDGPU_DRM_KMS_HELPER_IS_POLL_WORKER AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_MODE_INIT From 6007c3ddbae29385d9259910e6b551638b7183d9 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 20 Feb 2023 11:58:45 +0800 Subject: [PATCH 0984/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_MM_INSERT_MODE This patch also removes macro HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/backport/backport.h | 1 - drivers/gpu/drm/amd/dkms/config/config.h | 6 -- .../gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 | 17 ----- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/ttm/backport/backport.h | 2 - include/kcl/backport/kcl_drm_mm_backport.h | 27 -------- include/kcl/kcl_drm_mm.h | 68 ------------------- 7 files changed, 122 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 delete mode 100644 include/kcl/backport/kcl_drm_mm_backport.h delete mode 100644 include/kcl/kcl_drm_mm.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e913c8e92c80c..81237794ee36b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -65,7 +65,6 @@ #include #include #include -#include #include #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 25abf2431cefd..25e1cc64e040e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -620,12 +620,6 @@ /* drm_memcpy_from_wc() is availablea and has struct iosys_map* arg */ #define HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG 1 -/* whether drm_mm_insert_mode is available */ -#define HAVE_DRM_MM_INSERT_MODE 1 - -/* drm_mm_insert_node has three parameters */ -#define HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS 1 - /* drm_mode_config->dp_subconnector_property is available */ #define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 deleted file mode 100644 index 633f7925b0aec..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 +++ /dev/null @@ -1,17 +0,0 @@ -dnl # -dnl # commit 4e64e5539d152e202ad6eea2b6f65f3ab58d9428 -dnl # Author: Chris Wilson -dnl # Date: Thu Feb 2 21:04:38 2017 +0000 -dnl # -AC_DEFUN([AC_AMDGPU_DRM_MM_INSERT_MODE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - enum drm_mm_insert_mode mode = DRM_MM_INSERT_BEST; - ],[ - AC_DEFINE(HAVE_DRM_MM_INSERT_MODE, 1, - [whether drm_mm_insert_mode is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8045c2cc6c8ec..7924541bc2507 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -73,7 +73,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT AC_AMDGPU_DRM_PRINT_BITS - AC_AMDGPU_DRM_MM_INSERT_MODE AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL AC_AMDGPU_STRUCT_DRM_DEVICE diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 23eea49ccf6ae..57158f3fc9465 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -12,8 +12,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/include/kcl/backport/kcl_drm_mm_backport.h b/include/kcl/backport/kcl_drm_mm_backport.h deleted file mode 100644 index 1a2614d47ab59..0000000000000 --- a/include/kcl/backport/kcl_drm_mm_backport.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef AMDKCL_DRM_MM_H -#define AMDKCL_DRM_MM_H - -/** - * interface change in mainline kernel 4.10 - * v4.10-rc5-1060-g4e64e5539d15 drm: Improve drm_mm search (and fix topdown allocation) - * with rbtrees - */ - -#include - -#ifndef HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS -static inline int _kcl_drm_mm_insert_node(struct drm_mm *mm, - struct drm_mm_node *node, - u64 size) -{ - return drm_mm_insert_node(mm, node, size, 0, DRM_MM_SEARCH_DEFAULT); -} -#define drm_mm_insert_node _kcl_drm_mm_insert_node -#endif /* HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS */ - -#ifndef HAVE_DRM_MM_INSERT_MODE -#define drm_mm_insert_node_in_range _kcl_drm_mm_insert_node_in_range -#endif - -#endif /* AMDKCL_DRM_MM_H */ diff --git a/include/kcl/kcl_drm_mm.h b/include/kcl/kcl_drm_mm.h deleted file mode 100644 index 5387e6c05bc65..0000000000000 --- a/include/kcl/kcl_drm_mm.h +++ /dev/null @@ -1,68 +0,0 @@ -/************************************************************************** - * - * Copyright 2006-2008 Tungsten Graphics, Inc., Cedar Park, TX. USA. - * Copyright 2016 Intel Corporation - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * - **************************************************************************/ -/* - * Authors: - * Thomas Hellstrom - */ -#ifndef _KCL_KCL_DRM_MM_H_H_ -#define _KCL_KCL_DRM_MM_H_H_ -#include - -#ifndef HAVE_DRM_MM_INSERT_MODE -/* Copied from 4e64e5539d15 include/drm/drm_mm.h */ -enum drm_mm_insert_mode { - DRM_MM_INSERT_BEST = 0, - DRM_MM_INSERT_LOW, - DRM_MM_INSERT_HIGH, - DRM_MM_INSERT_EVICT, -}; - -static inline -int _kcl_drm_mm_insert_node_in_range(struct drm_mm * const mm, - struct drm_mm_node * const node, - u64 size, u64 alignment, - unsigned long color, - u64 range_start, u64 range_end, - enum drm_mm_insert_mode mode) -{ - enum drm_mm_search_flags sflags = DRM_MM_SEARCH_BEST; - enum drm_mm_allocator_flags aflags = DRM_MM_CREATE_DEFAULT; - - if (mode == DRM_MM_INSERT_HIGH) { - sflags = DRM_MM_SEARCH_BELOW; - aflags = DRM_MM_CREATE_TOP; - } - - return drm_mm_insert_node_in_range_generic(mm, node, size, - alignment, color, range_start, range_end, - sflags, aflags); -} -#endif /* HAVE_DRM_MM_INSERT_MODE */ - -#endif From 99020e2afa3be310ea8a28679f2f93926f73d15e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 20 Feb 2023 12:07:53 +0800 Subject: [PATCH 0985/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 3 - drivers/gpu/drm/amd/backport/Makefile | 2 +- drivers/gpu/drm/amd/backport/backport.h | 1 - .../kcl/kcl_amdgpu_drm_modeset_helper.h | 31 ------- .../drm/amd/backport/kcl_drm_modeset_helper.c | 89 ------------------- drivers/gpu/drm/amd/dkms/config/config.h | 3 - .../dkms/m4/drm_mode_config_helper_suspend.m4 | 13 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 8 files changed, 1 insertion(+), 142 deletions(-) delete mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_modeset_helper.h delete mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_modeset_helper.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_config_helper_suspend.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index e0d24f0069081..b8ef62fa14c8b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -360,9 +360,6 @@ struct amdgpu_mode_info { int disp_priority; const struct amdgpu_display_funcs *funcs; const enum drm_plane_type *plane_type; -#ifndef HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND - struct drm_atomic_state *suspend_state; -#endif /* Driver-private color mgmt props */ diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index 335363b5b8ee5..f5b5d3b9a2d33 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: MIT BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ - kcl_drm_gem.o kcl_drm_modeset_helper.o + kcl_drm_gem.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 81237794ee36b..04a3b11a3931a 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -72,7 +72,6 @@ #include "kcl/kcl_amdgpu_drm_drv.h" #include "kcl/kcl_amdgpu_drm_gem.h" #include "kcl/kcl_drm_gem_ttm_helper.h" -#include "kcl/kcl_amdgpu_drm_modeset_helper.h" #include "kcl/kcl_mce.h" #include "kcl/kcl_drm_aperture.h" #include diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_modeset_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_modeset_helper.h deleted file mode 100644 index 611d801aa6c33..0000000000000 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_modeset_helper.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that copyright - * notice and this permission notice appear in supporting documentation, and - * that the name of the copyright holders not be used in advertising or - * publicity pertaining to distribution of the software without specific, - * written prior permission. The copyright holders make no representations - * about the suitability of this software for any purpose. It is provided "as - * is" without express or implied warranty. - * - * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE - * OF THIS SOFTWARE. - */ - -#ifndef AMDGPU_BACKPORT_KCL_AMDGPU_DRM_MODESET_HELPER_H -#define AMDGPU_BACKPORT_KCL_AMDGPU_DRM_MODESET_HELPER_H - -#ifndef HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND -int drm_mode_config_helper_suspend(struct drm_device *dev); -int drm_mode_config_helper_resume(struct drm_device *dev); -#endif - -#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_modeset_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_modeset_helper.c deleted file mode 100644 index e6015f0a7efce..0000000000000 --- a/drivers/gpu/drm/amd/backport/kcl_drm_modeset_helper.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that copyright - * notice and this permission notice appear in supporting documentation, and - * that the name of the copyright holders not be used in advertising or - * publicity pertaining to distribution of the software without specific, - * written prior permission. The copyright holders make no representations - * about the suitability of this software for any purpose. It is provided "as - * is" without express or implied warranty. - * - * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE - * OF THIS SOFTWARE. - */ - -#include -#include "amdgpu.h" - -/* Copied from drivers/gpu/drm/drm_modeset_helper.c and modified for KCL */ -#ifndef HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND -int drm_mode_config_helper_suspend(struct drm_device *dev) -{ - struct drm_atomic_state *state; - struct amdgpu_device *adev; - struct amdgpu_fbdev *afbdev; - struct drm_fb_helper *fb_helper; - - if (!dev) - return 0; - - adev = drm_to_adev(dev); - afbdev = adev->mode_info.rfbdev; - if (!afbdev) - return 0; - - fb_helper = &afbdev->helper; - - drm_kms_helper_poll_disable(dev); - drm_fb_helper_set_suspend_unlocked(fb_helper, 1); - state = drm_atomic_helper_suspend(dev); - if (IS_ERR(state)) { - drm_fb_helper_set_suspend_unlocked(fb_helper, 0); - drm_kms_helper_poll_enable(dev); - return PTR_ERR(state); - } - - adev->mode_info.suspend_state = state; - - return 0; -} - -int drm_mode_config_helper_resume(struct drm_device *dev) -{ - int ret; - struct amdgpu_device *adev; - struct amdgpu_fbdev *afbdev; - struct drm_fb_helper *fb_helper; - - if (!dev) - return 0; - - adev = drm_to_adev(dev); - afbdev = adev->mode_info.rfbdev; - if (!afbdev) - return 0; - - fb_helper = &afbdev->helper; - - if (WARN_ON(!adev->mode_info.suspend_state)) - return -EINVAL; - - ret = drm_atomic_helper_resume(dev, adev->mode_info.suspend_state); - if (ret) - DRM_ERROR("Failed to resume (%d)\n", ret); - adev->mode_info.suspend_state = NULL; - - drm_fb_helper_set_suspend_unlocked(fb_helper, 0); - drm_kms_helper_poll_enable(dev); - - return ret; -} -#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 25e1cc64e040e..94eda3a291536 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -632,9 +632,6 @@ /* drm_mode_config_funcs->atomic_state_alloc() is available */ #define HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC 1 -/* drm_mode_config_helper_{suspend/resume}() is available */ -#define HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND 1 - /* drm_mode_get_hv_timing is available */ #define HAVE_DRM_MODE_GET_HV_TIMING 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_helper_suspend.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_helper_suspend.m4 deleted file mode 100644 index 8d30e1afba578..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_helper_suspend.m4 +++ /dev/null @@ -1,13 +0,0 @@ -dnl # -dnl # v4.14-rc7-1626-gca038cfb5cfa -dnl # drm/modeset-helper: Add simple modeset suspend/resume helpers -dnl # -AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG_HELPER_SUSPEND], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_mode_config_helper_suspend drm_mode_config_helper_resume], - [drivers/gpu/drm/drm_modeset_helper.c],[ - AC_DEFINE(HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND, 1, - [drm_mode_config_helper_{suspend/resume}() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7924541bc2507..9893eab4caec5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -144,7 +144,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT - AC_AMDGPU_DRM_MODE_CONFIG_HELPER_SUSPEND AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS From b3f62dccb831fbb7aa2efd506d825af8edcfc88e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 14 Jun 2023 17:17:10 +0800 Subject: [PATCH 0986/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_MODE_IS_420_XXX Signed-off-by: Leslie Shi Reviewed-by: Ma Jun Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c | 7 ------- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 -- drivers/gpu/drm/amd/dkms/config/config.h | 6 ------ .../gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 | 17 ----------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/kcl_drm_modes.h | 7 ------- 6 files changed, 40 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c index e01b01bd4ae09..a7963c347e685 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c @@ -33,13 +33,6 @@ #include #include -#ifndef HAVE_DRM_MODE_IS_420_XXX -amdkcl_dummy_symbol(drm_mode_is_420_only, bool, return false, - const struct drm_display_info *display, const struct drm_display_mode *mode) -amdkcl_dummy_symbol(drm_mode_is_420_also, bool, return false, - const struct drm_display_info *display, const struct drm_display_mode *mode) -#endif - #ifndef HAVE_DRM_MODE_INIT void drm_mode_init(struct drm_display_mode *dst, const struct drm_display_mode *src) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e5ea68ecea485..62c214c003391 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6210,7 +6210,6 @@ convert_color_depth_from_display_info(const struct drm_connector *connector, /* Assume 8 bpc by default if no bpc is specified. */ bpc = bpc ? bpc : 8; -#ifdef HAVE_DRM_MODE_IS_420_XXX if (is_y420) { bpc = 8; @@ -6222,7 +6221,6 @@ convert_color_depth_from_display_info(const struct drm_connector *connector, else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) bpc = 10; } -#endif if (requested_bpc > 0) { /* diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 94eda3a291536..00be7562e5ece 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -632,12 +632,6 @@ /* drm_mode_config_funcs->atomic_state_alloc() is available */ #define HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC 1 -/* drm_mode_get_hv_timing is available */ -#define HAVE_DRM_MODE_GET_HV_TIMING 1 - -/* drm_mode_is_420_xxx() is available */ -#define HAVE_DRM_MODE_IS_420_XXX 1 - /* drm_mode_init() is available */ #define HAVE_DRM_MODE_INTT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 deleted file mode 100644 index 65c9ec9268e1b..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 +++ /dev/null @@ -1,17 +0,0 @@ -dnl # -dnl # commit 2570fe2586254ff174c2ba5a20dabbde707dbb9b -dnl # drm: add helper functions for YCBCR420 handling -dnl # -AC_DEFUN([AC_AMDGPU_DRM_MODE_IS_420_XXX], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_mode_is_420_only(NULL, NULL); - drm_mode_is_420_also(NULL, NULL); - ], [drm_mode_is_420_only drm_mode_is_420_also],[drivers/gpu/drm/drm_modes.c],[ - AC_DEFINE(HAVE_DRM_MODE_IS_420_XXX, 1, - [drm_mode_is_420_xxx() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9893eab4caec5..95e86bc97ed87 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -87,7 +87,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_EDID AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER - AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_MODE_INIT AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS diff --git a/include/kcl/kcl_drm_modes.h b/include/kcl/kcl_drm_modes.h index efd58502aad15..d3a387bad9988 100644 --- a/include/kcl/kcl_drm_modes.h +++ b/include/kcl/kcl_drm_modes.h @@ -29,13 +29,6 @@ #include -#ifndef HAVE_DRM_MODE_IS_420_XXX -bool drm_mode_is_420_only(const struct drm_display_info *display, - const struct drm_display_mode *mode); -bool drm_mode_is_420_also(const struct drm_display_info *display, - const struct drm_display_mode *mode); -#endif - #ifndef HAVE_DRM_MODE_INIT void drm_mode_init(struct drm_display_mode *dst, const struct drm_display_mode *src); #endif From 8465a88f58e712df116782ca77aef6dc321c6c67 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Wed, 1 Mar 2023 12:17:08 +0800 Subject: [PATCH 0987/2653] drm/amdkcl: check if fsleep() is available It's caused by b1121d678231324d281db891755aa547506457a9 "drm/amd/display: Reduce CPU busy-waiting for long delays" Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/fsleep.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_delay.h | 18 ++++++++++++++++++ 5 files changed, 40 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/fsleep.m4 create mode 100644 include/kcl/kcl_delay.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 04a3b11a3931a..e9ad69f3afd3d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -104,4 +104,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 00be7562e5ece..944d1edf86e31 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -149,6 +149,9 @@ /* down_write_killable() is available */ #define HAVE_DOWN_WRITE_KILLABLE 1 +/* fsleep() is available */ +#define HAVE_FSLEEP 1 + /* drm_dp_mst_connector_early_unregister() is available */ #define HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/fsleep.m4 b/drivers/gpu/drm/amd/dkms/m4/fsleep.m4 new file mode 100644 index 0000000000000..782402a16e6a4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/fsleep.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.7-rc2-1263-gc6af13d33475 +dnl # timer: add fsleep for flexible sleeping +dnl # +AC_DEFUN([AC_AMDGPU_FSLEEP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + unsigned long usecs = 0; + fsleep(usecs); + ], [ + AC_DEFINE(HAVE_FSLEEP, 1, + [fsleep() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 95e86bc97ed87..1a3e59727c095 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -35,6 +35,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MEMALLOC_NOFS_SAVE AC_AMDGPU_ZONE_MANAGED_PAGES AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST + AC_AMDGPU_FSLEEP AC_AMDGPU_VMF_INSERT AC_AMDGPU_VMF_INSERT_MIXED_PROT AC_AMDGPU_VMF_INSERT_PFN_PROT diff --git a/include/kcl/kcl_delay.h b/include/kcl/kcl_delay.h new file mode 100644 index 0000000000000..f5f2962c6bb6d --- /dev/null +++ b/include/kcl/kcl_delay.h @@ -0,0 +1,18 @@ +#ifndef AMDKCL_DELAY_H +#define AMDKCL_DELAY_H + +#ifndef HAVE_FSLEEP +static inline void _kcl_fsleep(unsigned long usecs) +{ + if (usecs <= 10) + udelay(usecs); + else if (usecs <= 20000) + usleep_range(usecs, 2 * usecs); + else + msleep(DIV_ROUND_UP(usecs, 1000)); +} + +#define fsleep _kcl_fsleep + +#endif +#endif From c0641772f4b03af04d1de7e9e9da1377bd04f2b2 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 20 Feb 2023 16:16:42 +0800 Subject: [PATCH 0988/2653] drm/amdkcl: kcl-cleanup HAVE_KREF_READ Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c | 1 - drivers/gpu/drm/amd/backport/backport.h | 1 - drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/kref-read.m4 | 16 ---------------- drivers/gpu/drm/scheduler/backport/backport.h | 1 - drivers/gpu/drm/ttm/backport/backport.h | 1 - include/kcl/kcl_kref.h | 7 ------- 7 files changed, 28 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/kref-read.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c index d19d8b3733657..aef948cfe4ad2 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c @@ -9,7 +9,6 @@ #if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) -#include #include #include diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e9ad69f3afd3d..b4c60325bd5d0 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1a3e59727c095..be43f0a88f71f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -9,7 +9,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_KERNEL_SUPPORTED_AMD_CHIPS AC_AMDGPU_IDR - AC_AMDGPU_KREF_READ AC_AMDGPU_TYPE__POLL_T AC_AMDGPU_DMA_MAP_SGTABLE AC_AMDGPU_I2C_NEW_CLIENT_DEVICE diff --git a/drivers/gpu/drm/amd/dkms/m4/kref-read.m4 b/drivers/gpu/drm/amd/dkms/m4/kref-read.m4 deleted file mode 100644 index da7e2bf0aac37..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/kref-read.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit 2c935bc57221cc2edc787c72ea0e2d30cdcd3d5e -dnl # locking/atomic, kref: Add kref_read() -dnl # -AC_DEFUN([AC_AMDGPU_KREF_READ], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - kref_read(NULL); - ], [ - AC_DEFINE(HAVE_KREF_READ, 1, - [kref_read() function is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 3327879e06a15..25460de490b35 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -8,6 +8,5 @@ #include #include #include -#include #endif diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 57158f3fc9465..e6cab104d2b34 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -3,7 +3,6 @@ #define AMDTTM_BACKPORT_H #include -#include #include #include #include diff --git a/include/kcl/kcl_kref.h b/include/kcl/kcl_kref.h index 0cc53e385e8db..491ce5398137b 100644 --- a/include/kcl/kcl_kref.h +++ b/include/kcl/kcl_kref.h @@ -15,11 +15,4 @@ #include /* Copied from include/linux/kref.h */ -#if !defined(HAVE_KREF_READ) -static inline unsigned int kref_read(const struct kref *kref) -{ - return atomic_read(&kref->refcount); -} -#endif - #endif /* AMDKCL_KREF_H */ From 18024148c72df963b6eb13cd7ee7a19104fa2e7d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 20 Feb 2023 16:30:12 +0800 Subject: [PATCH 0989/2653] drm/amdkcl: kcl-cleanup HAVE_KTIME_GET_REAL_SECONDS Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../drm/amd/dkms/m4/ktime-get-real-seconds.m4 | 20 ------------------- include/kcl/kcl_timekeeping.h | 10 ---------- 4 files changed, 34 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 944d1edf86e31..e4279ab2c050c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -813,9 +813,6 @@ /* ktime_get_raw_ns is available */ #define HAVE_KTIME_GET_RAW_NS 1 -/* ktime_get_real_seconds() is available */ -#define HAVE_KTIME_GET_REAL_SECONDS 1 - /* ktime_t is union */ /* #undef HAVE_KTIME_IS_UNION */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index be43f0a88f71f..fa09ee8461dab 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -30,7 +30,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_REBAR_BYTES_TO_SIZE AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_KTIME_GET_RAW_NS - AC_AMDGPU_KTIME_GET_REAL_SECONDS AC_AMDGPU_MEMALLOC_NOFS_SAVE AC_AMDGPU_ZONE_MANAGED_PAGES AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 deleted file mode 100644 index 6ba2dff0aca08..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 +++ /dev/null @@ -1,20 +0,0 @@ -AC_DEFUN([AC_AMDGPU_KTIME_GET_REAL_SECONDS], [ - AC_KERNEL_DO_BACKGROUND([ - dnl # - dnl # commit dbe7aa622db96b5cd601f59d09c4f00b98b76079 - dnl # timekeeping: Provide y2038 safe accessor to the seconds portion of CLOCK_REALTIME - dnl # - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRM_BACKPORT_H - #include - #endif - #include - #include - ], [ - ktime_get_real_seconds(); - ], [ - AC_DEFINE(HAVE_KTIME_GET_REAL_SECONDS, 1, - [ktime_get_real_seconds() is available]) - ]) - ]) -]) diff --git a/include/kcl/kcl_timekeeping.h b/include/kcl/kcl_timekeeping.h index 90e1b1c045a75..644228c997baf 100644 --- a/include/kcl/kcl_timekeeping.h +++ b/include/kcl/kcl_timekeeping.h @@ -37,16 +37,6 @@ static inline u64 ktime_get_raw_ns(void) } #endif -#ifndef HAVE_KTIME_GET_REAL_SECONDS -static inline time64_t ktime_get_real_seconds(void) -{ - struct timeval ts; - - do_gettimeofday(&ts); - return (time64_t)ts.tv_sec; -} -#endif - #ifndef HAVE_JIFFIES64_TO_MSECS extern u64 jiffies64_to_msecs(u64 j); #endif From 273e62a2491d88a84119633fd89d21e5bdcc7279 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Thu, 2 Mar 2023 13:15:42 +0800 Subject: [PATCH 0990/2653] drm/amdkcl: wrap code under macro HAVE_STRUCT_XARRAY It's caused by 1d34dd584ae816e858b1177294262e80efe7d932 "drm/scheduler: rework entity flush, kill and fini" Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/scheduler/sched_entity.c | 100 ++++++++++++++++++++++- 1 file changed, 97 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c index 03fe677a4f129..59f52bef11e62 100644 --- a/drivers/gpu/drm/scheduler/sched_entity.c +++ b/drivers/gpu/drm/scheduler/sched_entity.c @@ -182,6 +182,7 @@ static void drm_sched_entity_kill_jobs_work(struct work_struct *wrk) job->sched->ops->free_job(job); } +#ifdef HAVE_STRUCT_XARRAY /* Signal the scheduler finished fence when the entity in question is killed. */ static void drm_sched_entity_kill_jobs_cb(struct dma_fence *f, struct dma_fence_cb *cb) @@ -262,7 +263,7 @@ static void drm_sched_entity_kill(struct drm_sched_entity *entity) } dma_fence_put(prev); } - +#endif /** * drm_sched_entity_flush - Flush a context entity * @@ -302,14 +303,75 @@ long drm_sched_entity_flush(struct drm_sched_entity *entity, long timeout) /* For killed process disable any more IBs enqueue right now */ last_user = cmpxchg(&entity->last_user, current->group_leader, NULL); +#ifdef HAVE_STRUCT_XARRAY if ((!last_user || last_user == current->group_leader) && (current->flags & PF_EXITING) && (current->exit_code == SIGKILL)) drm_sched_entity_kill(entity); - +#else + if ((!last_user || last_user == current->group_leader) && + (current->flags & PF_EXITING) && (current->exit_code == SIGKILL)) { + spin_lock(&entity->lock); + entity->stopped = true; + drm_sched_rq_remove_entity(entity->rq, entity); + spin_unlock(&entity->lock); + } +#endif return ret; } EXPORT_SYMBOL(drm_sched_entity_flush); +#ifndef HAVE_STRUCT_XARRAY +/* Signal the scheduler finished fence when the entity in question is killed. */ +static void drm_sched_entity_kill_jobs_cb(struct dma_fence *f, + struct dma_fence_cb *cb) +{ + struct drm_sched_job *job = container_of(cb, struct drm_sched_job, + finish_cb); + + dma_fence_put(f); + INIT_WORK(&job->work, drm_sched_entity_kill_jobs_work); + schedule_work(&job->work); +} + +static void drm_sched_entity_kill_jobs(struct drm_sched_entity *entity) +{ + struct drm_sched_job *job; + struct dma_fence *f; + int r; + + while ((job = drm_sched_entity_queue_pop(entity))) { + struct drm_sched_fence *s_fence = job->s_fence; + + /* Wait for all dependencies to avoid data corruptions */ + while ((f = job->sched->ops->dependency(job, entity))) { + dma_fence_wait(f, false); + dma_fence_put(f); + } + + drm_sched_fence_scheduled(s_fence, f); + dma_fence_set_error(&s_fence->finished, -ESRCH); + + /* + * When pipe is hanged by older entity, new entity might + * not even have chance to submit it's first job to HW + * and so entity->last_scheduled will remain NULL + */ + if (!entity->last_scheduled) { + drm_sched_entity_kill_jobs_cb(NULL, &job->finish_cb); + continue; + } + + dma_fence_get(entity->last_scheduled); + r = dma_fence_add_callback(entity->last_scheduled, + &job->finish_cb, + drm_sched_entity_kill_jobs_cb); + if (r == -ENOENT) + drm_sched_entity_kill_jobs_cb(NULL, &job->finish_cb); + else if (r) + DRM_ERROR("fence add callback failed (%d)\n", r); + } +} +#endif /** * drm_sched_entity_fini - Destroy a context entity * @@ -323,6 +385,36 @@ EXPORT_SYMBOL(drm_sched_entity_flush); */ void drm_sched_entity_fini(struct drm_sched_entity *entity) { +#ifndef HAVE_STRUCT_XARRAY + struct drm_gpu_scheduler *sched = NULL; + + if (entity->rq) { + sched = entity->rq->sched; + drm_sched_rq_remove_entity(entity->rq, entity); + } + + /* Consumption of existing IBs wasn't completed. Forcefully + * remove them here. + */ + if (spsc_queue_count(&entity->job_queue)) { + if (sched) { + /* + * Wait for thread to idle to make sure it isn't processing + * this entity. + */ + wait_for_completion(&entity->entity_idle); + + } + if (entity->dependency) { + dma_fence_remove_callback(entity->dependency, + &entity->cb); + dma_fence_put(entity->dependency); + entity->dependency = NULL; + } + + drm_sched_entity_kill_jobs(entity); + } +#else /* * If consumption of existing IBs wasn't completed. Forcefully remove * them here. Also makes sure that the scheduler won't touch this entity @@ -335,7 +427,7 @@ void drm_sched_entity_fini(struct drm_sched_entity *entity) dma_fence_put(entity->dependency); entity->dependency = NULL; } - +#endif dma_fence_put(rcu_dereference_check(entity->last_scheduled, true)); RCU_INIT_POINTER(entity->last_scheduled, NULL); } @@ -429,6 +521,7 @@ static bool drm_sched_entity_add_dependency_cb(struct drm_sched_entity *entity) return false; } +#ifdef HAVE_STRUCT_XARRAY static struct dma_fence * drm_sched_job_dependency(struct drm_sched_job *job, struct drm_sched_entity *entity) @@ -450,6 +543,7 @@ drm_sched_job_dependency(struct drm_sched_job *job, return NULL; } +#endif struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity) { From 1c37646d34c92b9ee296ff265447d3f7e08ad7e3 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Thu, 2 Mar 2023 13:19:09 +0800 Subject: [PATCH 0991/2653] drm/amdkcl: rename dependency callback into prepare_job It's caused by a25fe9259b68c90033850033ad1b0f20b41e8980 "drm/scheduler: rename dependency callback into prepare_job" Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/scheduler/sched_entity.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c index 59f52bef11e62..5356cb529e93a 100644 --- a/drivers/gpu/drm/scheduler/sched_entity.c +++ b/drivers/gpu/drm/scheduler/sched_entity.c @@ -343,7 +343,7 @@ static void drm_sched_entity_kill_jobs(struct drm_sched_entity *entity) struct drm_sched_fence *s_fence = job->s_fence; /* Wait for all dependencies to avoid data corruptions */ - while ((f = job->sched->ops->dependency(job, entity))) { + while ((f = job->sched->ops->prepare_job(job, entity))) { dma_fence_wait(f, false); dma_fence_put(f); } @@ -560,7 +560,7 @@ struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity) #ifdef HAVE_STRUCT_XARRAY drm_sched_job_dependency(sched_job, entity))) { #else - sched->ops->dependency(sched_job, entity))) { + sched->ops->prepare_job(sched_job, entity))) { #endif if (drm_sched_entity_add_dependency_cb(entity)) { trace_drm_sched_job_unschedulable(sched_job, entity->dependency); From b5c47b6671d734e34447c6665651387d5a86a327 Mon Sep 17 00:00:00 2001 From: Daniel Phillips Date: Sun, 5 Mar 2023 22:54:35 -0800 Subject: [PATCH 0992/2653] amdkfd: Fix memory availability double accounting of kfd pinned objects Pinned objects that are not kfd objects reduce the total vram available to kfd, so we subtract the total size of pinned objects from kdf vram availability. However this double counts objects pinned by kfd itself, because they are counted both as used and pinned. So track the total size of objects pinned by kfd and add it back to kfd availability to remove the double accounting. Signed-off-by: Daniel Phillips Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 86428884867f9..ed53850e9b295 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -109,6 +109,7 @@ struct amdgpu_kfd_dev { struct kfd_dev *dev; int64_t vram_used[MAX_XCP]; uint64_t vram_used_aligned[MAX_XCP]; + atomic64_t vram_pinned; bool init_complete; struct work_struct reset_work; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 15d175883e121..e5ef013433e49 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1577,6 +1577,11 @@ int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) pr_err("Error in Pinning BO to domain: %d\n", domain); amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false); + + if (!ret && bo->tbo.resource->mem_type == TTM_PL_VRAM) + atomic64_add(amdgpu_bo_size(bo), + &amdgpu_ttm_adev(bo->tbo.bdev)->kfd.vram_pinned); + out: amdgpu_bo_unreserve(bo); return ret; @@ -1599,6 +1604,11 @@ void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo) return; amdgpu_bo_unpin(bo); + + if (bo->tbo.resource->mem_type == TTM_PL_VRAM) + atomic64_sub(amdgpu_bo_size(bo), + &amdgpu_ttm_adev(bo->tbo.bdev)->kfd.vram_pinned); + amdgpu_bo_unreserve(bo); } @@ -1716,6 +1726,7 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id) - adev->kfd.vram_used_aligned[xcp_id] - atomic64_read(&adev->vram_pin_size) + + atomic64_read(&adev->kfd.vram_pinned) - reserved_for_pt - reserved_for_ras; From ec530e1a7a2c29a60ee31c28dfc3fab5426a51cf Mon Sep 17 00:00:00 2001 From: bobzhou Date: Wed, 15 Mar 2023 14:20:22 +0800 Subject: [PATCH 0993/2653] drm/amdkcl: Rename DCN config to FP It's cauesd by 284c5833d58fd8c267d2d0858528e8a997183352 "drm/amd/display: Rename DCN config to FP" Signed-off-by: bobzhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- .../drm/amd/display/dc/link/protocols/link_dp_capability.c | 6 +++--- drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c | 2 +- drivers/gpu/drm/amd/dkms/Makefile | 4 ++-- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 16018e908b560..7fc44b05ffc44 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -417,7 +417,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( mst_port = aconnector->mst_output_port; -#if defined(CONFIG_DRM_AMD_DC_DCN) +#if defined(CONFIG_DRM_AMD_DC_FP) link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); #endif diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 042ac796da1f2..c0a2829a0d12e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1385,7 +1385,7 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context) * The OTG is set to disable on falling edge of VUPDATE so the plane disable * will still get it's double buffer update. */ -#ifdef CONFIG_DRM_AMD_DC_DCN +#ifdef CONFIG_DRM_AMD_DC_FP if (is_phantom) { if (tg->funcs->disable_phantom_crtc) tg->funcs->disable_phantom_crtc(tg); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 288d8d7f0a52b..7247cde8a92b9 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -166,7 +166,7 @@ uint32_t dp_get_closest_lttpr_offset(uint8_t lttpr_count) return DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE * (lttpr_count - 1); } -#if defined(CONFIG_DRM_AMD_DC_DCN) +#if defined(CONFIG_DRM_AMD_DC_FP) uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw) { switch (bw) { @@ -251,7 +251,7 @@ static union dp_cable_id intersect_cable_id( return out; } -#if defined(CONFIG_DRM_AMD_DC_DCN) +#if defined(CONFIG_DRM_AMD_DC_FP) /* * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw. */ @@ -1225,7 +1225,7 @@ static void get_active_converter_info( translate_dpcd_max_bpc( hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT); -#if defined(CONFIG_DRM_AMD_DC_DCN) +#if defined(CONFIG_DRM_AMD_DC_FP) if (link->dc->caps.dp_hdmi21_pcon_support) { link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index 368d84acc17ae..03245307a599d 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -307,7 +307,7 @@ static const struct timing_generator_funcs dcn32_tg_funcs = { .enable_crtc = optc32_enable_crtc, .disable_crtc = optc32_disable_crtc, .phantom_crtc_post_enable = optc32_phantom_crtc_post_enable, -#ifdef CONFIG_DRM_AMD_DC_DCN +#ifdef CONFIG_DRM_AMD_DC_FP .disable_phantom_crtc = optc32_disable_phantom_otg, #endif /* used by enable_timing_synchronization. Not need for FPGA */ diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index c90d2e3182c23..b4e3343fd05d5 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -202,8 +202,8 @@ endif # if core2 isn't in the compiler flags ifndef CONFIG_ARM64 ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) -export CONFIG_DRM_AMD_DC_DCN=y -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN +export CONFIG_DRM_AMD_DC_FP=y +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_FP endif endif From 1d2c63f21825fceb53b5a5a9f07a0b17ff8d1f70 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Tue, 14 Mar 2023 20:45:51 +0800 Subject: [PATCH 0994/2653] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS It's caused by c602664a579de061dba08beb690f2718e4fb1b52 "drm/amd/display: Pass the right info to drm_dp_remove_payload" Signed-off-by: bobzhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 7fc44b05ffc44..2e99c6839177b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -309,7 +309,7 @@ void dm_helpers_dp_update_branch_info( struct dc_context *ctx, const struct dc_link *link) {} - +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) static void dm_helpers_construct_old_payload( struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_topology_state *mst_state, @@ -341,6 +341,7 @@ static void dm_helpers_construct_old_payload( old_payload->time_slots = allocated_time_slots; old_payload->pbn = allocated_time_slots * pbn_per_slot; } +#endif /* * Writes payload allocation table in immediate downstream device. From 26d8a7e0c6e2261e4f01bf0f0aae19c0108dba13 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 17 Mar 2023 10:45:23 +0800 Subject: [PATCH 0995/2653] drm/amdkcl: kcl-cleanup DEFINE_SRCU for legacy os Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_module.c | 9 --------- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 13 ------------- 2 files changed, 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index ea7aca6d9d874..5f8093e03d340 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -26,11 +26,6 @@ #include "kfd_priv.h" #include "amdgpu_amdkfd.h" -#ifndef DEFINE_SRCU -void kfd_init_processes_srcu(void); -void kfd_cleanup_processes_srcu(void); -#endif - static int kfd_init(void) { int err; @@ -75,10 +70,6 @@ static int kfd_init(void) kfd_debugfs_init(); -#ifndef DEFINE_SRCU - kfd_init_processes_srcu(); -#endif - return 0; err_create_wq: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index e219d556e2ad1..76c2a7ae41b01 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -53,20 +53,7 @@ struct mm_struct; DEFINE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE); DEFINE_MUTEX(kfd_processes_mutex); -#ifndef DEFINE_SRCU -struct srcu_struct kfd_processes_srcu; -void kfd_init_processes_srcu(void) -{ - init_srcu_struct(&kfd_processes_srcu); -} - -void kfd_cleanup_processes_srcu(void) -{ - cleanup_srcu_struct(&kfd_processes_srcu); -} -#else DEFINE_SRCU(kfd_processes_srcu); -#endif /* For process termination handling */ static struct workqueue_struct *kfd_process_wq; From 3712f2f7be9373e7fa55f943980dc6a9cb4878ed Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Mar 2023 10:08:24 +0800 Subject: [PATCH 0996/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_EDID_TO_ELD Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 6 -- .../gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 | 19 ------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/backport/kcl_drm_encoder.h | 57 ------------------- 4 files changed, 83 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 delete mode 100644 include/kcl/backport/kcl_drm_encoder.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e4279ab2c050c..34db650f22fe3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -541,12 +541,6 @@ /* drm_dsc_compute_rc_parameters() is available */ #define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 -/* drm_edid_to_eld() are available */ -/* #undef HAVE_DRM_EDID_TO_ELD */ - -/* drm_encoder_find() wants file_priv */ -#define HAVE_DRM_ENCODER_FIND_VALID_WITH_FILE 1 - /* drm_fbdev_generic_setup() is available */ /* #undef HAVE_DRM_FBDEV_GENERIC_SETUP */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 deleted file mode 100644 index f0efb113db67b..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 +++ /dev/null @@ -1,19 +0,0 @@ -dnl # -dnl # commit v4.14-rc3-594-g79436a1c9bcc -dnl # drm/edid: make drm_edid_to_eld() static -dnl # -dnl # commit v3.1-rc6-139-g76adaa34db40 -dnl # drm: support routines for HDMI/DP ELD -dnl # -AC_DEFUN([AC_AMDGPU_DRM_EDID_TO_ELD], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_edid_to_eld(NULL, NULL); - ], [drm_edid_to_eld], [drivers/gpu/drm/drm_edid.c], [ - AC_DEFINE(HAVE_DRM_EDID_TO_ELD, 1, - [drm_edid_to_eld() are available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fa09ee8461dab..87e84ff4b7942 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -82,7 +82,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_INIT AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL - AC_AMDGPU_DRM_EDID_TO_ELD AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_EDID AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER diff --git a/include/kcl/backport/kcl_drm_encoder.h b/include/kcl/backport/kcl_drm_encoder.h deleted file mode 100644 index 0efc8f747defd..0000000000000 --- a/include/kcl/backport/kcl_drm_encoder.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2006 Luc Verhaegen (quirks list) - * Copyright (c) 2007-2008 Intel Corporation - * Jesse Barnes - * Copyright 2010 Red Hat, Inc. - * - * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from - * FB layer. - * Copyright (C) 2006 Dennis Munsie - * For codes copied from drivers/gpu/drm/drm_edid.c - * - * Copyright (c) 2016 Intel Corporation - * For codes copied from include/drm/drm_encoder.h - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sub license, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef KCL_BACKPORT_KCL_DRM_ENCODER_H -#define KCL_BACKPORT_KCL_DRM_ENCODER_H - -#include -#include - -/* Copied from drivers/gpu/drm/drm_edid.c and modified for KCL */ -#if defined(HAVE_DRM_EDID_TO_ELD) -static inline -int _kcl_drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) -{ - int ret; - - ret = drm_add_edid_modes(connector, edid); - - if (drm_edid_is_valid(edid)) - drm_edid_to_eld(connector, edid); - - return ret; -} -#define drm_add_edid_modes _kcl_drm_add_edid_modes -#endif - -#endif From 671c6e5e09ddf24b064c69baf8c5c6335a674cea Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Mar 2023 13:30:18 +0800 Subject: [PATCH 0997/2653] drm/amdkcl: Remove the temp build directory Sometimes there are temp build directory left after execute the command "make -f dirvers/gpu/drm/amd/dkms/Makefile.config". So remove them all. Signed-off-by: Ma Jun Reviewd-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile.config b/drivers/gpu/drm/amd/dkms/Makefile.config index f6d23defbaae6..211fd393987e3 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile.config +++ b/drivers/gpu/drm/amd/dkms/Makefile.config @@ -15,7 +15,7 @@ config: force clean: force @( \ cd $(srctree)/$(dkmstree); \ - rm -f aclocal.m4 config.* configure config/*.in* \ + rm -rf aclocal.m4 config.* configure config/*.in* build_*\ ) .PHONY: all force From 35fcd514acb2f97dc3d17be30bd91caa9e03683a Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Mar 2023 13:41:41 +0800 Subject: [PATCH 0998/2653] drm/amdkcl: Fix the bug when check luminance_range Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 34db650f22fe3..0a55b376358d2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -350,7 +350,7 @@ #define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 /* display_info->luminance_range is available */ -/* #undef HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE */ +#define HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE 1 /* display_info->max_dsc_bpp is available */ /* #undef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 index f72df7f1ac808..ad9ebac619d6e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 @@ -64,7 +64,8 @@ AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_LUMINANCE_RANGE], [ #include ],[ struct drm_display_info *display_info = NULL; - display_info->luminance_range=NULL; + struct drm_luminance_range_info *luminance_range; + luminance_range = &display_info->luminance_range; ],[ AC_DEFINE(HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE, 1, [display_info->luminance_range is available]) From f0a7da126ef330e9139528d02dd4164348aa2c46 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Mar 2023 10:53:00 +0800 Subject: [PATCH 0999/2653] drm/amdkcl: Fix the return value of idr_init_base Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 6 ++++++ drivers/gpu/drm/amd/dkms/m4/idr.m4 | 3 +-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0a55b376358d2..07953cece74d8 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -756,6 +756,9 @@ /* i2c_new_client_device() is enabled */ #define HAVE_I2C_NEW_CLIENT_DEVICE 1 +/* idr_init_base() is available */ +#define HAVE_IDR_INIT_BASE 1 + /* idr_remove return void pointer */ #define HAVE_IDR_REMOVE_RETURN_VOID_POINTER 1 @@ -1075,6 +1078,9 @@ /* drm_plane_helper_funcs->prepare_fb() wants p,p arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_PP 1 +/* ide->idr_base is available */ +#define HAVE_STRUCT_IDE_IDR_BASE 1 + /* struct smca_bank is available */ /* #undef HAVE_STRUCT_SMCA_BANK */ diff --git a/drivers/gpu/drm/amd/dkms/m4/idr.m4 b/drivers/gpu/drm/amd/dkms/m4/idr.m4 index 7816e84901c5a..1c678e3c401b7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/idr.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/idr.m4 @@ -27,8 +27,7 @@ AC_DEFUN([AC_AMDGPU_IDR_INIT_BASE], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - void *i; - i = idr_init_base(NULL, 0); + idr_init_base(NULL, 0); ], [ AC_DEFINE(HAVE_IDR_INIT_BASE, 1, [idr_init_base() is available]) From 68622b2c3578b733fb14ff0aceb0f0902a969d0f Mon Sep 17 00:00:00 2001 From: bobzhou Date: Fri, 17 Mar 2023 10:13:24 +0800 Subject: [PATCH 1000/2653] drm/amdkcl: fix macro for amdgpu_acpi_should_gpu_reset() It's caused by ed199fb30b0178ed82311c4f0d5515b0718c9cc4 "drm/amdgpu: reposition the gpu reset checking for reuse" The amdgpu_acpi_should_gpu_reset() is moved, but the kcl macro haven't been include, so fix the kcl macro in new amdgpu_acpi_should_gpu_reset(). Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index b108c23873ef0..8ad81a9cd4ef1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -1388,7 +1388,11 @@ bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) return false; #if IS_ENABLED(CONFIG_SUSPEND) +#ifdef HAVE_PM_SUSPEND_TARGET_STATE return pm_suspend_target_state != PM_SUSPEND_TO_IDLE; +#else + return false; +#endif #else return true; #endif From b0847c91a4c9e05c1e387950764027e1e35cf3d1 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Fri, 17 Mar 2023 11:00:18 +0800 Subject: [PATCH 1001/2653] drm/amdkcl: wrap code under macro HAVE_MMU_NOTIFIER_PUT It's caused by 0e9398dcb6ecc5a2cde03a1224cd806278ac13e4 "drm/amdkfd: Fixed kfd_process cleanup on module exit." The non-upstream code in kfd_process_notifier_release() is moved into kfd_process_notifier_release_internal(). Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 76c2a7ae41b01..581931ad80231 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1218,6 +1218,7 @@ static void kfd_process_destroy_delayed(struct rcu_head *rcu) static void kfd_process_notifier_release_internal(struct kfd_process *p) { int i; + struct mm_struct *mm = p->mm; cancel_delayed_work_sync(&p->eviction_work); cancel_delayed_work_sync(&p->restore_work); @@ -1252,7 +1253,12 @@ static void kfd_process_notifier_release_internal(struct kfd_process *p) srcu_read_unlock(&kfd_processes_srcu, idx); } +#ifdef HAVE_MMU_NOTIFIER_PUT mmu_notifier_put(&p->mmu_notifier); +#else + mmu_notifier_unregister_no_release(&p->mmu_notifier, mm); + mmu_notifier_call_srcu(&p->rcu, &kfd_process_destroy_delayed); +#endif } static void kfd_process_notifier_release(struct mmu_notifier *mn, From 0807d660457c88ac4ccaca3869f716fc56f23cb4 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Fri, 17 Mar 2023 11:04:11 +0800 Subject: [PATCH 1002/2653] drm/amdkcl: open the macro HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP In dkms-6.0 the HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP has been support, so open the macro. Signed-off-by: bobzhou Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 07953cece74d8..490894e54de11 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -353,7 +353,7 @@ #define HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE 1 /* display_info->max_dsc_bpp is available */ -/* #undef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP */ +#define HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP 1 /* drm_dp_atomic_find_time_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS 1 From 5de5779a54ab357341842d1a71ee5ed01f26214a Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 20 Mar 2023 14:41:20 +0800 Subject: [PATCH 1003/2653] drm/amdkcl: fake drm_warn macro It's caused by 2b7cb41b58aa950da4a61b21cfa9a62a49127edf "drm/amd/display/amdgpu_dm: Refactor register_backlight_device()" Signed-off-by: bobzhou Reviewed-by: Guchun Chen Reviewed-by: Leslie Shi --- include/kcl/kcl_drm_print.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 71a5b6f419e46..c71867326f13b 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -79,6 +79,11 @@ void kcl_drm_err(const char *format, ...); #define HAVE_DRM_ERR_MACRO #endif /* drm_err */ +#ifndef drm_warn +#define drm_warn(drm, fmt, ...) \ + dev_warn((drm)->dev, "[drm] " fmt, ##__VA_ARGS__) +#endif /* drm_warn */ + #if !defined(DRM_UT_VBL) #define DRM_UT_VBL 0x20 #endif From e1d2cc14566103713878dea466ce833531fabd26 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 20 Mar 2023 16:09:13 +0800 Subject: [PATCH 1004/2653] drm/amdkcl: Drop unnecessary FP guards [Why & How] drm-next branch code drop unnecessary FP guards, so clean up FP guards under kcl macro. Signed-off-by: bobzhou Reviewed-by: majun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 -- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 -- .../drm/amd/display/dc/link/protocols/link_dp_capability.c | 6 ------ drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c | 2 -- 4 files changed, 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 2e99c6839177b..7e09a7f82efc2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -418,9 +418,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( mst_port = aconnector->mst_output_port; -#if defined(CONFIG_DRM_AMD_DC_FP) link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); -#endif if (enable) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index c0a2829a0d12e..8229abc65670a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1385,12 +1385,10 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context) * The OTG is set to disable on falling edge of VUPDATE so the plane disable * will still get it's double buffer update. */ -#ifdef CONFIG_DRM_AMD_DC_FP if (is_phantom) { if (tg->funcs->disable_phantom_crtc) tg->funcs->disable_phantom_crtc(tg); } -#endif } } diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 7247cde8a92b9..9e24ae6e9c93c 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -166,7 +166,6 @@ uint32_t dp_get_closest_lttpr_offset(uint8_t lttpr_count) return DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE * (lttpr_count - 1); } -#if defined(CONFIG_DRM_AMD_DC_FP) uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw) { switch (bw) { @@ -186,7 +185,6 @@ uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw) return 0; } -#endif static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz) { @@ -251,7 +249,6 @@ static union dp_cable_id intersect_cable_id( return out; } -#if defined(CONFIG_DRM_AMD_DC_FP) /* * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw. */ @@ -281,7 +278,6 @@ static uint32_t intersect_frl_link_bw_support( return supported_bw_in_kbps; } -#endif static enum clock_source_id get_clock_source_id(struct dc_link *link) { @@ -1225,7 +1221,6 @@ static void get_active_converter_info( translate_dpcd_max_bpc( hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT); -#if defined(CONFIG_DRM_AMD_DC_FP) if (link->dc->caps.dp_hdmi21_pcon_support) { link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = @@ -1237,7 +1232,6 @@ static void get_active_converter_info( if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0) link->dpcd_caps.dongle_caps.extendedCapValid = true; } -#endif if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0) link->dpcd_caps.dongle_caps.extendedCapValid = true; diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index 03245307a599d..b2b226bcd871c 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -307,9 +307,7 @@ static const struct timing_generator_funcs dcn32_tg_funcs = { .enable_crtc = optc32_enable_crtc, .disable_crtc = optc32_disable_crtc, .phantom_crtc_post_enable = optc32_phantom_crtc_post_enable, -#ifdef CONFIG_DRM_AMD_DC_FP .disable_phantom_crtc = optc32_disable_phantom_otg, -#endif /* used by enable_timing_synchronization. Not need for FPGA */ .is_counter_moving = optc1_is_counter_moving, .get_position = optc1_get_position, From c7f11d8b236aa2143deb970d5aebce161dd8fe41 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Wed, 22 Mar 2023 17:13:54 +0800 Subject: [PATCH 1005/2653] drm/amdkcl: wrap unused variable under HAVE_MMU_NOTIFIER_PUT When HAVE_MMU_NOTIFIER_PUT is closed, mm variable isn't used. So move it into macro HAVE_MMU_NOTIFIER_PUT. Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 581931ad80231..333205b2cbeeb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1218,7 +1218,9 @@ static void kfd_process_destroy_delayed(struct rcu_head *rcu) static void kfd_process_notifier_release_internal(struct kfd_process *p) { int i; +#ifndef HAVE_MMU_NOTIFIER_PUT struct mm_struct *mm = p->mm; +#endif cancel_delayed_work_sync(&p->eviction_work); cancel_delayed_work_sync(&p->restore_work); From 2183cb89e61c89b703abd7be8e0164a0b5185fb0 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Tue, 21 Mar 2023 11:09:10 +0800 Subject: [PATCH 1006/2653] drm/amdkcl: modify the C standard to gnu99 for legacy gcc [Why & How] Upstream patches now uses gnu11/gnu99 as the default C standard version. However, gcc in legacy OS still uses gnu89, which will introduce a standard build gap leading to a DKMS build failure possibly. Add KBUILD_CFLAGS check to move gnu89 to gnu99 if KBUILD_CFLAGS still uses gnu89. Signed-off-by: bobzhou Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index b4e3343fd05d5..ff21ca820d731 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -207,6 +207,16 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_FP endif endif +# v5.17-rc4-3-ge8c07082a810 (Kbuild: move to -std=gnu11) +# Upstream patches now uses gnu11/gnu99 as the default C standard version. +# However, gcc in legacy OS still uses gnu89, which will introduce a standard +# build gap leading to a DKMS build failure possibly. So add below check to +# move gnu89 to gnu99 if KBUILD_CFLAGS still uses gnu89. +ifeq ($(findstring gnu89,$(KBUILD_CFLAGS)),gnu89) +KBUILD_CFLAGS := $(subst gnu89,gnu99,$(KBUILD_CFLAGS)) +$(warning "The local C standard(gnu89) doesn't match kernel default C standard(gnu11/gnu99)") +endif + include $(src)/amd/dkms/Makefile.drm_ttm_helper include $(src)/amd/dkms/Makefile.drm_buddy From 228441b3936980b43beb42b816e07cf43f3f9b54 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Tue, 21 Mar 2023 11:37:33 -0600 Subject: [PATCH 1007/2653] drm/display: Add missing OLED Vesa brightnesses definitions Reviewed-by: Harry Wentland Signed-off-by: Rodrigo Siqueira --- include/drm/display/drm_dp.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 811e9238a77cc..ba4861db1cd03 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -1033,6 +1033,8 @@ # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5) # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6) # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7) +#define DP_EDP_OLED_VESA_BRIGHTNESS_ON 0x80 +# define DP_EDP_OLED_VESA_CAP (1 << 4) #define DP_EDP_GENERAL_CAP_2 0x703 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0) From 44029f510175eba6b82385eaad6f2456d10316d5 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 20 Mar 2023 16:30:48 +0800 Subject: [PATCH 1008/2653] drm/amdkcl: wrap code under macro HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP v2 It's caused by c88ea46c1474c09939bf1546d5a44e8e42c23361 "drm/amd/display: Add height granularity limitation for dsc slice height calculation" v2: add support for struct dsc_options and reuse legacy data fill it. Signed-off-by: bobzhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index a6382fb0bad2a..29e8fd863d4df 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -998,7 +998,11 @@ static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *p drm_connector = ¶ms[i].aconnector->base; dc_dsc_get_default_config_option(params[i].sink->ctx->dc, &dsc_options); +#ifdef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16; +#else + dsc_options.max_target_bpp_limit_override_x16 = params[i].sink->edid_caps.panel_patch.max_dsc_target_bpp_limit * 16; +#endif memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); if (vars[i + k].dsc_enabled && dc_dsc_compute_config( From 383b2223c310eb52123b9327eaad0609829d3e05 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Thu, 23 Mar 2023 15:19:56 +0800 Subject: [PATCH 1009/2653] drm/amdkcl: wrap code under macro HAVE_HDR_SINK_METADATA It's caused by a5465aa219a1c3ef1365a12b00e2d51e110af538 "drm/amd/display/amdgpu_dm: Move most backlight setup into setup_backlight_device()" Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 62c214c003391..7b4822be83466 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5129,8 +5129,9 @@ static void setup_backlight_device(struct amdgpu_display_manager *dm, amdgpu_dm_update_backlight_caps(dm, bl_idx); dm->backlight_link[bl_idx] = link; dm->num_of_edps++; - +#ifdef HAVE_HDR_SINK_METADATA update_connector_ext_caps(aconnector); +#endif } static void amdgpu_set_panel_orientation(struct drm_connector *connector); From 33533c540b65cbabc75077337fbdd601957e9e8f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 1 Apr 2023 12:01:56 +0800 Subject: [PATCH 1010/2653] drm/amdgpu: [hybrid] remove sync obj in the job It's caused by 1728baa7e4e60054bf13dd9b1212d133cbd53b3f "drm/amdgpu: use scheduler dependencies for CS" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 3bc373a9afbd2..625b6be7aca9a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -674,7 +674,7 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) } for (i = 0; i < p->gang_size; ++i) { - r = amdgpu_sem_add_cs(p->ctx, p->entities[i], &p->jobs[i]->sync); + r = amdgpu_sem_add_cs(p->ctx, p->entities[i], &p->sync); if (r) return r; } From 09fe8926493cdd582ecbb8dd37dd385144343bf5 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 3 Apr 2023 16:07:11 +0800 Subject: [PATCH 1011/2653] drm/amdkcl: change included file from ttm_bo_api.h to ttm_bo.h It's caused by a3185f91d0579b61a0a0dce3df1c67d6e324ebc8 "drm/ttm: merge ttm_bo_api.h and ttm_bo_driver.h v2" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c index 04b308171928f..3f3a70274a81c 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -4,8 +4,7 @@ #include #include -#include -#include +#include #include #include #include From 4f9e6d3aa6e273493de3936dd7a8b6d8a48c66e9 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 14:44:21 +0800 Subject: [PATCH 1012/2653] drm/amdkcl: test whether apple_gmux.h is available and fake apple_gmux_detect() It's caused by 1e98231de4609b9e4597b52d0f29bb664e4938d2 "drm/amdgpu: register a vga_switcheroo client for MacBooks with apple-gmux" Signed-off-by: bobzhou Reviewed-by: Leslie Shi Reviewed-by: Flora Cui Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 16 +++++--------- .../gpu/drm/amd/dkms/m4/apple_gmux_detect.m4 | 16 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/linux/apple-gmux.h | 9 ++++++++ include/kcl/kcl_apple-gmux.h | 21 +++++++++++++++++++ 7 files changed, 58 insertions(+), 11 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/apple_gmux_detect.m4 create mode 100644 include/kcl/header/linux/apple-gmux.h create mode 100644 include/kcl/kcl_apple-gmux.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b4c60325bd5d0..98902bf9e06b1 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -104,4 +104,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 490894e54de11..510f6cfc25b20 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -373,6 +373,9 @@ /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 +/* apple_gmux_detect() is available */ +#define HAVE_APPLE_GMUX_DETECT 1 + /* drm_dp_calc_pbn_mode() wants 3args */ #define HAVE_DRM_DP_CALC_PBN_MODE_3ARGS 1 @@ -813,17 +816,8 @@ /* ktime_t is union */ /* #undef HAVE_KTIME_IS_UNION */ -/* kvcalloc() is available */ -#define HAVE_KVCALLOC 1 - -/* kvfree() is available */ -#define HAVE_KVFREE 1 - -/* kvmalloc_array() is available */ -#define HAVE_KVMALLOC_ARRAY 1 - -/* kv[mz]alloc() are available */ -#define HAVE_KVZALLOC_KVMALLOC 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_APPLE_GMUX_H 1 /* Define to 1 if you have the header file. */ #define HAVE_LINUX_BITS_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/apple_gmux_detect.m4 b/drivers/gpu/drm/amd/dkms/m4/apple_gmux_detect.m4 new file mode 100644 index 0000000000000..defc80545265e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/apple_gmux_detect.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.1-2256-gbd100f492c7e +dnl # platform/x86: apple-gmux: Add apple_gmux_detect() helper +dnl # +AC_DEFUN([AC_AMDGPU_APPLE_GMUX_DETECT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + apple_gmux_detect(NULL, NULL); + ],[ + AC_DEFINE(HAVE_APPLE_GMUX_DETECT, 1, + [apple_gmux_detect() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 87e84ff4b7942..34dda9768ca8b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -192,6 +192,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE AC_AMDGPU_RB_ADD_CACHED + AC_AMDGPU_APPLE_GMUX_DETECT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 2c9f72c524583..f99ed5020b2e7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -114,4 +114,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # dma-mapping: split dnl # AC_KERNEL_CHECK_HEADERS([linux/dma-map-ops.h]) + + dnl #v4.5-rc3-203-g2413306c2566 + dnl #apple-gmux: Add helper for presence detect + dnl + AC_KERNEL_CHECK_HEADERS([linux/apple-gmux.h]) ]) diff --git a/include/kcl/header/linux/apple-gmux.h b/include/kcl/header/linux/apple-gmux.h new file mode 100644 index 0000000000000..19c858a0be836 --- /dev/null +++ b/include/kcl/header/linux/apple-gmux.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_APPLE_GMUX_H_H +#define _KCL_HEADER_LINUX_APPLE_GMUX_H_H + +#ifdef HAVE_LINUX_APPLE_GMUX_H +#include_next +#endif + +#endif diff --git a/include/kcl/kcl_apple-gmux.h b/include/kcl/kcl_apple-gmux.h new file mode 100644 index 0000000000000..27d96810046e7 --- /dev/null +++ b/include/kcl/kcl_apple-gmux.h @@ -0,0 +1,21 @@ +#ifndef AMDKCL_APPLE_GMUX_H +#define AMDKCL_APPLE_GMUX_H + +#include + +#ifndef HAVE_APPLE_GMUX_DETECT +#if IS_ENABLED(CONFIG_APPLE_GMUX) +static inline bool apple_gmux_detect(struct pnp_dev *pnp_dev, bool *indexed_ret) +{ + pr_warn_once("legacy kernel without apple_gmux_detect()\n"); + return false; +} +#else +static inline bool apple_gmux_detect(struct pnp_dev *pnp_dev, bool *indexed_ret) +{ + return false; +} +#endif +#endif + +#endif /* AMDKCL_APPLE_GMUX_H */ From 00b78eb3ec3c12ba693931505dd829d68f4f8a97 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 12 Apr 2023 16:52:08 +0800 Subject: [PATCH 1013/2653] drm/amdkcl: include linux/dma-resv.h in ttm_bo.h It's caused by a3185f91d0579b61a0a0dce3df1c67d6e324ebc8 "drm/ttm: merge ttm_bo_api.h and ttm_bo_driver.h v2" Signed-off-by: Asher Song --- include/drm/ttm/ttm_bo.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h index 3e67b442400e3..865f386f19b25 100644 --- a/include/drm/ttm/ttm_bo.h +++ b/include/drm/ttm/ttm_bo.h @@ -35,6 +35,7 @@ #include #include +#include #include "ttm_device.h" #ifndef HAVE_CONFIG_H From 48722413cdec0fe3fda1b196377274b4610bbeab Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 12 Apr 2023 17:12:30 +0800 Subject: [PATCH 1014/2653] drm/amdkcl:Use amdkcl_ttm_resvp to check whether drm_gem_object->resv is available Signed-off-by: Asher Song --- drivers/gpu/drm/ttm/ttm_bo_util.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 780980e72f978..21e07a801ef12 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -609,7 +609,7 @@ static int ttm_bo_wait_free_node(struct ttm_buffer_object *bo, { long ret; - ret = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP, + ret = dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP, false, 15 * HZ); if (ret == 0) return -EBUSY; @@ -768,7 +768,7 @@ int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo) int ret; /* If already idle, no need for ghost object dance. */ - if (dma_resv_test_signaled(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP)) { + if (dma_resv_test_signaled(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP)) { if (!bo->ttm) { /* See comment below about clearing. */ ret = ttm_tt_create(bo, true); @@ -805,7 +805,7 @@ int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo) ret = dma_resv_copy_fences(&amdkcl_ttm_resv(ghost), amdkcl_ttm_resvp(bo)); /* Last resort, wait for the BO to be idle when we are OOM */ if (ret) { - dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP, + dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP, false, MAX_SCHEDULE_TIMEOUT); } From 98cfc818017d779d588ec0a6d1a4451498f19683 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 12 Apr 2023 21:28:19 +0800 Subject: [PATCH 1015/2653] drm/amdkcl: wrap code under macro HAVE_STRUCT_XARRAY It's caused by 4f91790b42ffba72d80434d901548979ab41dc7c "drm/amdgpu: use drm_sched_job_add_resv_dependencies for moves" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 ++ 5 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 625b6be7aca9a..caaafb89f980e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1437,11 +1437,13 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, fence = &p->jobs[i]->base.s_fence->scheduled; dma_fence_get(fence); +#ifdef HAVE_STRUCT_XARRAY r = drm_sched_job_add_dependency(&leader->base, fence); if (r) { dma_fence_put(fence); return r; } +#endif } if (p->gang_size > 1) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index 8858dd9ffb021..04afbbfd7bb1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -444,11 +444,13 @@ int amdgpu_sync_push_to_job(struct amdgpu_sync *sync, struct amdgpu_job *job) } dma_fence_get(f); +#ifdef HAVE_STRUCT_XARRAY r = drm_sched_job_add_dependency(&job->base, f); if (r) { dma_fence_put(f); return r; } +#endif } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 8310476714b5c..c3e5fe3b78d31 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2593,11 +2593,15 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, adev->gart.bo); (*job)->vm_needs_flush = true; } +#ifndef HAVE_STRUCT_XARRAY + return 0; +#else if (!resv) return 0; return drm_sched_job_add_resv_dependencies(&(*job)->base, resv, DMA_RESV_USAGE_BOOKKEEP); +#endif } #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 78b272faf10da..13128d095ccbf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -1169,11 +1169,13 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, if (r) goto err_free; } else { +#ifdef HAVE_STRUCT_XARRAY r = drm_sched_job_add_resv_dependencies(&job->base, amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL); if (r) goto err_free; +#endif f = amdgpu_job_submit(job); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index 3ca6cf8297d2e..b1c44648da82b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -231,12 +231,14 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, dma_resv_iter_begin(&cursor, amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL); dma_resv_for_each_fence_unlocked(&cursor, fence) { dma_fence_get(fence); + #ifdef HAVE_STRUCT_XARRAY r = drm_sched_job_add_dependency(&p->job->base, fence); if (r) { dma_fence_put(fence); dma_resv_iter_end(&cursor); return r; } +#endif } dma_resv_iter_end(&cursor); From 52285867f7466947baaa2be165d80a1eb7ec882b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 14 Apr 2023 15:10:32 +0800 Subject: [PATCH 1016/2653] drm/amdkcl: define macro VM_ACCESS_FLAGS It's caused by cc03817c0e8417419ede18a8e0749c5b9699b135 "amdgpu: use VM_ACCESS_FLAGS" Signed-off-by: Asher Song --- include/kcl/kcl_mm.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index a3fb87d51aa61..112aeb2591136 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -86,4 +86,10 @@ struct vm_area_struct *vma_lookup(struct mm_struct *mm, unsigned long addr) } #endif /* HAVE_VMA_LOOKUP */ +#ifndef VM_ACCESS_FLAGS +/* Copied from v5.6-12367-g6cb4d9a2870d mm/vma: introduce VM_ACCESS_FLAGS*/ +/* VMA basic access permission flags */ +#define VM_ACCESS_FLAGS (VM_READ | VM_WRITE | VM_EXEC) +#endif + #endif /* AMDKCL_MM_H */ From 606299840e4ba37699155906caafab89e8001879 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 6 Apr 2023 18:17:24 +0800 Subject: [PATCH 1017/2653] drm/amdkcl: clean-up HAVE_IS_FIRMWARE_FRAMEBUFFER Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 23 ------------------- .../amd/dkms/m4/is-firmware-framebuffer.m4 | 13 ----------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/kcl_drm_fb.h | 4 ---- 5 files changed, 1 insertion(+), 42 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/is-firmware-framebuffer.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 0f953fafc56ab..306044881cd3d 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -8,7 +8,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_seq_file.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ kcl_fence.o kcl_reservation.o kcl_drm_cache.o \ - kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ + kcl_drm_fb.o kcl_drm_print.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c deleted file mode 100644 index 920cf50033339..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/drivers/video/fbmem.c - * - * Copyright (C) 1994 Martin Schaller - * - * 2001 - Documented with DocBook - * - Brad Douglas - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include - -#ifndef HAVE_IS_FIRMWARE_FRAMEBUFFER -bool is_firmware_framebuffer(struct apertures_struct *a) -{ - pr_warn_once("%s:enable the runtime pm\n", __func__); - return false; -} -EXPORT_SYMBOL(is_firmware_framebuffer); -#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/is-firmware-framebuffer.m4 b/drivers/gpu/drm/amd/dkms/m4/is-firmware-framebuffer.m4 deleted file mode 100644 index 44d0db303a161..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/is-firmware-framebuffer.m4 +++ /dev/null @@ -1,13 +0,0 @@ -dnl # -dnl # commit a99952170b19db855b7b45fba8e263ddc5205a0c -dnl # drm/amdgpu: disable runpm if we are the primary adapter -dnl # - -AC_DEFUN([AC_AMDGPU_IS_FIRMWARE_FRAMEBUFFER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([is_firmware_framebuffer], [include/linux/fb.h], [ - AC_DEFINE(HAVE_IS_FIRMWARE_FRAMEBUFFER, 1, [is_firmware_framebuffer() is available]) - ],[ - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 34dda9768ca8b..15fed4cefc1dc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -148,7 +148,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_BITMAP_FUNCS AC_AMDGPU_STRUCT_KOBJ_TYPE AC_AMDGPU_CLOSE_FD - AC_AMDGPU_IS_FIRMWARE_FRAMEBUFFER AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 795395d696484..9c0341fca3043 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -61,8 +61,4 @@ void drm_fb_helper_fill_info(struct fb_info *info, struct drm_fb_helper_surface_size *sizes); #endif -#ifndef HAVE_IS_FIRMWARE_FRAMEBUFFER -extern bool is_firmware_framebuffer(struct apertures_struct *a); -#endif - #endif From 6aa4b3fc753ac3213d72abbc65559b10bdb4e185 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 23 Feb 2023 11:06:01 +0800 Subject: [PATCH 1018/2653] drm/amdkcl:kcl-cleanup HAVE_DRM_FBDEV_GENERIC_SETUP Change-Id: I77e289c6ba211d528916193ed2b37ff9759368fb Signed-off-by: Ma Jun Reviewed-by: Leslie Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 +--------- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 8 +----- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 28 ------------------- drivers/gpu/drm/amd/dkms/config/config.h | 3 -- .../amd/dkms/m4/drm-fbdev-generic-setup.m4 | 16 ----------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/backport/kcl_drm_fb.h | 4 --- 9 files changed, 3 insertions(+), 79 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index dda726c04b7b4..56c0a7b960b45 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -50,7 +50,7 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \ amdgpu_atombios.o atombios_crtc.o amdgpu_connectors.o \ atom.o amdgpu_fence.o amdgpu_ttm.o amdgpu_object.o amdgpu_gart.o \ amdgpu_encoders.o amdgpu_display.o amdgpu_i2c.o \ - amdgpu_fb.o amdgpu_gem.o amdgpu_ring.o \ + amdgpu_gem.o amdgpu_ring.o \ amdgpu_cs.o amdgpu_bios.o amdgpu_benchmark.o \ atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \ atombios_encoders.o amdgpu_sa.o atombios_i2c.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 80034943c0b39..acc505e2c1a23 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4750,9 +4750,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, /* Get a log2 for easy divisions. */ adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); -#ifndef AMDKCL_DRM_FBDEV_GENERIC - amdgpu_fbdev_init(adev); -#endif /* * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost. * Otherwise the mgpu fan boost feature will be skipped due to the @@ -4949,9 +4946,6 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) amdgpu_reg_state_sysfs_fini(adev); amdgpu_xcp_sysfs_fini(adev); -#ifndef AMDKCL_DRM_FBDEV_GENERIC - amdgpu_fbdev_fini(adev); -#endif /* disable ras feature must before hw fini */ amdgpu_ras_pre_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index dbf7ab5b1eb6f..b43beaa406f82 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1741,7 +1741,6 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, stime, etime, mode); } -#ifdef AMDKCL_DRM_FBDEV_GENERIC static bool amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) { @@ -1756,7 +1755,6 @@ amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) return true; } -#endif int amdgpu_display_suspend_helper(struct amdgpu_device *adev) { @@ -1798,16 +1796,7 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) continue; robj = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); -#ifndef AMDKCL_DRM_FBDEV_GENERIC - /* don't unpin kernel fb objects */ - if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { - r = amdgpu_bo_reserve(robj, true); - if (r == 0) { - amdgpu_bo_unpin(robj); - amdgpu_bo_unreserve(robj); - } - } -#else + if (!amdgpu_display_robj_is_fb(adev, robj)) { r = amdgpu_bo_reserve(robj, true); if (r == 0) { @@ -1815,7 +1804,6 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) amdgpu_bo_unreserve(robj); } } -#endif } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 0301a5e4375a0..9e575b54e0fb5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -1173,7 +1173,6 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, return r; } -#ifdef AMDKCL_DRM_FBDEV_GENERIC static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, int width, int cpp, @@ -1199,7 +1198,6 @@ static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, aligned &= ~pitch_mask; return aligned * cpp; } -#endif int amdgpu_mode_dumb_create(struct drm_file *file_priv, struct drm_device *dev, @@ -1223,13 +1221,9 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv, if (adev->mman.buffer_funcs_enabled) flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; -#ifdef AMDKCL_DRM_FBDEV_GENERIC args->pitch = amdgpu_gem_align_pitch(adev, args->width, DIV_ROUND_UP(args->bpp, 8), 0); -#else - args->pitch = amdgpu_align_pitch(adev, args->width, - DIV_ROUND_UP(args->bpp, 8), 0); -#endif + args->size = (u64)args->pitch * args->height; args->size = ALIGN(args->size, PAGE_SIZE); domain = amdgpu_bo_get_preferred_domain(adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index b8ef62fa14c8b..df3749664f675 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -231,11 +231,6 @@ struct amdgpu_i2c_chan { struct mutex mutex; }; - -#ifndef AMDKCL_DRM_FBDEV_GENERIC -struct amdgpu_fbdev; -#endif - struct amdgpu_afmt { bool enabled; int offset; @@ -312,15 +307,6 @@ struct amdgpu_framebuffer { uint64_t address; }; -#ifndef AMDKCL_DRM_FBDEV_GENERIC -struct amdgpu_fbdev { - struct drm_fb_helper helper; - struct amdgpu_framebuffer rfb; - struct list_head fbdev_list; - struct amdgpu_device *adev; -}; -#endif - struct amdgpu_mode_info { struct atom_context *atom_context; struct card_info *atom_card_info; @@ -343,10 +329,6 @@ struct amdgpu_mode_info { /* hardcoded DFP edid from BIOS */ const struct drm_edid *bios_hardcoded_edid; -#ifndef AMDKCL_DRM_FBDEV_GENERIC - /* pointer to fbdev info structure */ - struct amdgpu_fbdev *rfbdev; -#endif /* firmware flags */ u32 firmware_flags; /* pointer to backlight encoder */ @@ -721,16 +703,6 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode); -#ifndef AMDKCL_DRM_FBDEV_GENERIC -/* fbdev layer */ -int amdgpu_fbdev_init(struct amdgpu_device *adev); -void amdgpu_fbdev_fini(struct amdgpu_device *adev); -void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); -int amdgpu_fbdev_total_size(struct amdgpu_device *adev); -bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); - -int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); -#endif /* amdgpu_display.c */ void amdgpu_display_print_display_setup(struct drm_device *dev); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 510f6cfc25b20..eeac4e9e0864b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -544,9 +544,6 @@ /* drm_dsc_compute_rc_parameters() is available */ #define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 -/* drm_fbdev_generic_setup() is available */ -/* #undef HAVE_DRM_FBDEV_GENERIC_SETUP */ - /* drm_fb_helper_single_add_all_connectors() && drm_fb_helper_remove_one_connector() are symbol */ /* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 deleted file mode 100644 index cfd16b033ccbf..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit v4.18-rc3-614-g9060d7f49376 -dnl # drm/fb-helper: Finish the generic fbdev emulation -dnl # -AC_DEFUN([AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_fbdev_generic_setup(NULL, 0); - ], [drm_fbdev_generic_setup], [drivers/gpu/drm/drm_fb_helper.c],[ - AC_DEFINE(HAVE_DRM_FBDEV_GENERIC_SETUP, 1, - [drm_fbdev_generic_setup() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 15fed4cefc1dc..ce5db63b7f78a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -141,7 +141,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT - AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index e14f228fc86fb..4b869a664735f 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -25,8 +25,4 @@ #include #include -#if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) -#define AMDKCL_DRM_FBDEV_GENERIC -#endif - #endif From 9be638d978adb16d4ffaedbe021d6473bf0212b0 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 3 Apr 2023 15:01:11 +0800 Subject: [PATCH 1019/2653] drm/amdkcl: remove unexpected comma Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index ff21ca820d731..ab6ae33fa71b6 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -8,7 +8,7 @@ GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) KERNEL_MAJ=$(VERSION) KERNEL_PATCHLEVEL=$(PATCHLEVEL) KERNEL_SUBLEVEL=$(SUBLEVEL) -KERNEL_VER=$(shell printf "%d%02d%02d" $(KERNEL_MAJ) $(KERNEL_PATCHLEVEL), $(KERNEL_SUBLEVEL)) +KERNEL_VER=$(shell printf "%d%02d%02d" $(KERNEL_MAJ) $(KERNEL_PATCHLEVEL) $(KERNEL_SUBLEVEL)) kernel-version = $(shell [ $(KERNEL_VER)0 $(1) $(2)000 ] && echo $(3) || echo $(4)) From d187874ac445b9f89cb01eb62d89dc5edd8cb4c8 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 3 Apr 2023 15:12:00 +0800 Subject: [PATCH 1020/2653] drm/amdkcl: use gcc-min-version macro to test gcc version This is caused by following commit: 88b61e3bff93 "Makefile.compiler: replace cc-ifversion with compiler-specific macros" Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index ab6ae33fa71b6..a6b1568f0b0c8 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -12,13 +12,6 @@ KERNEL_VER=$(shell printf "%d%02d%02d" $(KERNEL_MAJ) $(KERNEL_PATCHLEVEL) $(KERN kernel-version = $(shell [ $(KERNEL_VER)0 $(1) $(2)000 ] && echo $(3) || echo $(4)) -# gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. -ifeq ($(call cc-ifversion, -le, 0408, y), y) -ifeq ($(call kernel-version, -ge, 0504, y), y) -$(error "The GCC is too old for this kernel, please update the GCC to higher than 9.3") -endif -endif - ifdef CONFIG_CC_IS_GCC ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) $(warning "Local GCC version $(GCCSTR) does not match kernel compiler GCC version $(CONFIG_GCC_VERSION)") @@ -32,6 +25,17 @@ endif endif +ifndef gcc-min-version +export gcc-min-version=$(shell [ $(CONFIG_GCC_VERSION)0 -ge $(1)0 ] && echo y) +endif + +# gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. +ifneq ($(call gcc-min-version, 40805), y) +ifeq ($(call kernel-version, -ge, 0504, y), y) +$(error "The GCC is too old for this kernel, please update the GCC to higher than 9.3") +endif +endif + ifndef CONFIG_DRM $(error CONFIG_DRM disabled, exit...) endif From 77d85c7648c1d0d0ba0264c1fe1013087bf597d4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 4 Apr 2023 13:16:06 +0800 Subject: [PATCH 1021/2653] drm/amdkcl: Explicitly define gcc-min-version in separate file If we export gcc-min-version in dkms/Makefile, the function gcc-min-version cannot output correct value with gcc version 40805 in file display/dc/dml/Makefile for distro RHEL7.9. Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/dc/dml/Makefile | 2 ++ drivers/gpu/drm/amd/dkms/Makefile | 4 +--- drivers/gpu/drm/amd/dkms/Makefile.compiler | 3 +++ 3 files changed, 6 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/Makefile.compiler diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile index b357683b4255a..9e7f9713bba0b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile @@ -28,6 +28,8 @@ dml_ccflags := $(CC_FLAGS_FPU) dml_rcflags := $(CC_FLAGS_NO_FPU) +include $(src)/../dkms/Makefile.compiler + ifneq ($(CONFIG_FRAME_WARN),0) ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) frame_warn_limit := 3072 diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index a6b1568f0b0c8..0c7477083f0ec 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -25,9 +25,7 @@ endif endif -ifndef gcc-min-version -export gcc-min-version=$(shell [ $(CONFIG_GCC_VERSION)0 -ge $(1)0 ] && echo y) -endif +include $(src)/amd/dkms/Makefile.compiler # gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. ifneq ($(call gcc-min-version, 40805), y) diff --git a/drivers/gpu/drm/amd/dkms/Makefile.compiler b/drivers/gpu/drm/amd/dkms/Makefile.compiler new file mode 100644 index 0000000000000..9c546ebcbee5a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.compiler @@ -0,0 +1,3 @@ +ifndef gcc-min-version +gcc-min-version = $(shell [ $(CONFIG_GCC_VERSION)0 -ge $(1)0 ] && echo y) +endif From d5362e9c7822a0c07718777379842c7a9e079718 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 21 Apr 2023 14:12:37 +0800 Subject: [PATCH 1022/2653] drm/amdkcl: kcl-cleanup remove amdgpu/amdgpu_fb.c file Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 409 ------------------------- 1 file changed, 409 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c deleted file mode 100644 index 09b60070309e1..0000000000000 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ /dev/null @@ -1,409 +0,0 @@ -/* - * Copyright © 2007 David Airlie - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * David Airlie - */ - -#ifndef AMDKCL_DRM_FBDEV_GENERIC - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "amdgpu.h" -#include "cikd.h" -#include "amdgpu_gem.h" - -#include "amdgpu_display.h" - -/* object hierarchy - - this contains a helper + a amdgpu fb - the helper contains a pointer to amdgpu framebuffer baseclass. -*/ - -static int -amdgpufb_open(struct fb_info *info, int user) -{ - struct drm_fb_helper *fb_helper = info->par; - int ret = pm_runtime_get_sync(fb_helper->dev->dev); - if (ret < 0 && ret != -EACCES) { - pm_runtime_mark_last_busy(fb_helper->dev->dev); - pm_runtime_put_autosuspend(fb_helper->dev->dev); - return ret; - } - return 0; -} - -static int -amdgpufb_release(struct fb_info *info, int user) -{ - struct drm_fb_helper *fb_helper = info->par; - - pm_runtime_mark_last_busy(fb_helper->dev->dev); - pm_runtime_put_autosuspend(fb_helper->dev->dev); - return 0; -} - -static const struct fb_ops amdgpufb_ops = { - .owner = THIS_MODULE, - DRM_FB_HELPER_DEFAULT_OPS, - .fb_open = amdgpufb_open, - .fb_release = amdgpufb_release, - .fb_fillrect = drm_fb_helper_cfb_fillrect, - .fb_copyarea = drm_fb_helper_cfb_copyarea, - .fb_imageblit = drm_fb_helper_cfb_imageblit, -}; - - -int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled) -{ - int aligned = width; - int pitch_mask = 0; - - switch (cpp) { - case 1: - pitch_mask = 255; - break; - case 2: - pitch_mask = 127; - break; - case 3: - case 4: - pitch_mask = 63; - break; - } - - aligned += pitch_mask; - aligned &= ~pitch_mask; - return aligned * cpp; -} - -static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj) -{ - struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); - int ret; - - ret = amdgpu_bo_reserve(abo, true); - if (likely(ret == 0)) { - amdgpu_bo_kunmap(abo); - amdgpu_bo_unpin(abo); - amdgpu_bo_unreserve(abo); - } - drm_gem_object_put(gobj); -} - -static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, - struct drm_mode_fb_cmd2 *mode_cmd, - struct drm_gem_object **gobj_p) -{ - const struct drm_format_info *info; - struct amdgpu_device *adev = rfbdev->adev; - struct drm_gem_object *gobj = NULL; - struct amdgpu_bo *abo = NULL; - bool fb_tiled = false; /* useful for testing */ - u32 tiling_flags = 0, domain; - int ret; - int aligned_size, size; - int height = mode_cmd->height; - u32 cpp; - u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | - AMDGPU_GEM_CREATE_VRAM_CLEARED; - - info = drm_get_format_info(adev_to_drm(adev), mode_cmd); - cpp = info->cpp[0]; - - /* need to align pitch with crtc limits */ - mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, - fb_tiled); - domain = amdgpu_display_supported_domains(adev, flags); - height = ALIGN(mode_cmd->height, 8); - size = mode_cmd->pitches[0] * height; - aligned_size = ALIGN(size, PAGE_SIZE); - ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, flags, - ttm_bo_type_device, NULL, &gobj); - if (ret) { - pr_err("failed to allocate framebuffer (%d)\n", aligned_size); - return -ENOMEM; - } - abo = gem_to_amdgpu_bo(gobj); - - if (fb_tiled) - tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1); - - ret = amdgpu_bo_reserve(abo, false); - if (unlikely(ret != 0)) - goto out_unref; - - if (tiling_flags) { - ret = amdgpu_bo_set_tiling_flags(abo, - tiling_flags); - if (ret) - dev_err(adev->dev, "FB failed to set tiling flags\n"); - } - - ret = amdgpu_bo_pin(abo, domain); - if (ret) { - amdgpu_bo_unreserve(abo); - goto out_unref; - } - - ret = amdgpu_ttm_alloc_gart(&abo->tbo); - if (ret) { - amdgpu_bo_unreserve(abo); - dev_err(adev->dev, "%p bind failed\n", abo); - goto out_unref; - } - - ret = amdgpu_bo_kmap(abo, NULL); - amdgpu_bo_unreserve(abo); - if (ret) { - goto out_unref; - } - - *gobj_p = gobj; - return 0; -out_unref: - amdgpufb_destroy_pinned_object(gobj); - *gobj_p = NULL; - return ret; -} - -static int amdgpufb_create(struct drm_fb_helper *helper, - struct drm_fb_helper_surface_size *sizes) -{ - struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper; - struct amdgpu_device *adev = rfbdev->adev; - struct fb_info *info; - struct drm_framebuffer *fb = NULL; - struct drm_mode_fb_cmd2 mode_cmd; - struct drm_gem_object *gobj = NULL; - struct amdgpu_bo *abo = NULL; - int ret; - - memset(&mode_cmd, 0, sizeof(mode_cmd)); - mode_cmd.width = sizes->surface_width; - mode_cmd.height = sizes->surface_height; - - if (sizes->surface_bpp == 24) - sizes->surface_bpp = 32; - - mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, - sizes->surface_depth); - - ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj); - if (ret) { - DRM_ERROR("failed to create fbcon object %d\n", ret); - return ret; - } - - abo = gem_to_amdgpu_bo(gobj); - - /* okay we have an object now allocate the framebuffer */ - info = drm_fb_helper_alloc_fbi(helper); - if (IS_ERR(info)) { - ret = PTR_ERR(info); - goto out; - } - - ret = amdgpu_display_gem_fb_init(adev_to_drm(adev), &rfbdev->rfb, - &mode_cmd, gobj); - if (ret) { - DRM_ERROR("failed to initialize framebuffer %d\n", ret); - goto out; - } - - fb = &rfbdev->rfb.base; - - /* setup helper */ - rfbdev->helper.fb = fb; - - info->fbops = &amdgpufb_ops; - - info->fix.smem_start = amdgpu_gmc_vram_cpu_pa(adev, abo); - info->fix.smem_len = amdgpu_bo_size(abo); - info->screen_base = amdgpu_bo_kptr(abo); - info->screen_size = amdgpu_bo_size(abo); - - drm_fb_helper_fill_info(info, &rfbdev->helper, sizes); - - /* setup aperture base/size for vesafb takeover */ -#ifdef HAVE_DRM_MODE_CONFIG_FB_BASE - info->apertures->ranges[0].base = adev_to_drm(adev)->mode_config.fb_base; -#endif - info->apertures->ranges[0].size = adev->gmc.aper_size; - - /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ - - if (info->screen_base == NULL) { - ret = -ENOSPC; - goto out; - } - - DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); - DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base); - DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo)); - DRM_INFO("fb depth is %d\n", fb->format->depth); - DRM_INFO("pitch is %d\n", fb->pitches[0]); - - vga_switcheroo_client_fb_set(adev->pdev, info); - return 0; - -out: - if (abo) { - - } - if (fb && ret) { - drm_gem_object_put(gobj); - drm_framebuffer_unregister_private(fb); - drm_framebuffer_cleanup(fb); - kfree(fb); - } - return ret; -} - -static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev) -{ - struct amdgpu_framebuffer *rfb = &rfbdev->rfb; - struct drm_gem_object *obj = NULL; - int i; - - drm_fb_helper_unregister_fbi(&rfbdev->helper); - obj = drm_gem_fb_get_obj(&rfb->base, 0); - - if (obj) { -#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED - for (i = 0; i < rfb->base.format->num_planes; i++) - drm_gem_object_put(obj); -#endif - amdgpufb_destroy_pinned_object(obj); - rfb->base.obj[0] = NULL; - drm_framebuffer_unregister_private(&rfb->base); - drm_framebuffer_cleanup(&rfb->base); - } - drm_fb_helper_fini(&rfbdev->helper); - - return 0; -} - -static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = { - .fb_probe = amdgpufb_create, -}; - -int amdgpu_fbdev_init(struct amdgpu_device *adev) -{ - struct amdgpu_fbdev *rfbdev; - int bpp_sel = 32; - int ret; - - /* don't init fbdev on hw without DCE */ - if (!adev->mode_info.mode_config_initialized) - return 0; - - /* don't init fbdev if there are no connectors */ - if (list_empty(&adev_to_drm(adev)->mode_config.connector_list)) - return 0; - - /* select 8 bpp console on low vram cards */ - if (adev->gmc.real_vram_size <= (32*1024*1024)) - bpp_sel = 8; - - rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL); - if (!rfbdev) - return -ENOMEM; - - rfbdev->adev = adev; - adev->mode_info.rfbdev = rfbdev; - - drm_fb_helper_prepare(adev_to_drm(adev), &rfbdev->helper, - &amdgpu_fb_helper_funcs); - -#if defined(HAVE_DRM_FB_HELPER_INIT_2ARGS) - ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper); -#elif defined(HAVE_DRM_FB_HELPER_INIT_3ARGS) - ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper, - AMDGPUFB_CONN_LIMIT); -#else - ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper, - adev->mode_info.num_crtc, AMDGPUFB_CONN_LIMIT); -#endif - - if (ret) { - kfree(rfbdev); - return ret; - } - - /* disable all the possible outputs/crtcs before entering KMS mode */ - if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev))) - drm_helper_disable_unused_functions(adev_to_drm(adev)); - - drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); - return 0; -} - -void amdgpu_fbdev_fini(struct amdgpu_device *adev) -{ - if (!adev->mode_info.rfbdev) - return; - - amdgpu_fbdev_destroy(adev_to_drm(adev), adev->mode_info.rfbdev); - kfree(adev->mode_info.rfbdev); - adev->mode_info.rfbdev = NULL; -} - -void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state) -{ - if (adev->mode_info.rfbdev) - drm_fb_helper_set_suspend_unlocked(&adev->mode_info.rfbdev->helper, - state); -} - -int amdgpu_fbdev_total_size(struct amdgpu_device *adev) -{ - struct amdgpu_bo *robj; - int size = 0; - - if (!adev->mode_info.rfbdev) - return 0; - - robj = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&adev->mode_info.rfbdev->rfb.base, 0)); - size += amdgpu_bo_size(robj); - return size; -} - -bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) -{ - if (!adev->mode_info.rfbdev) - return false; - if (robj == gem_to_amdgpu_bo(drm_gem_fb_get_obj(&adev->mode_info.rfbdev->rfb.base, 0))) - return true; - return false; -} -#endif From f1175e627a5e8fad70df614dbf4ebf09f9f2c6ba Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 7 Apr 2023 10:01:43 +0800 Subject: [PATCH 1023/2653] drm/amdkcl: Add missing macro definition in config.h Signed-off-by: Ma Jun Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index eeac4e9e0864b..7029f6f7e22dc 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -520,11 +520,8 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_BUDDY_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_UTIL_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_VBLANK_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_FBDEV_GENERIC_H 1 /* drm_driver_feature DRIVER_IRQ_SHARED is available */ /* #undef HAVE_DRM_DRV_DRIVER_IRQ_SHARED */ From dfd35d4bd80713faeeedffaef3ce69b2520568d8 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 4 Apr 2023 10:04:12 +0800 Subject: [PATCH 1024/2653] drm/amdkcl: kcl-cleanup HAVE_DRM_DRM_BUDDY_H Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ------ 2 files changed, 9 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7029f6f7e22dc..b973f3cc82458 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -517,9 +517,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_BUDDY_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_FBDEV_GENERIC_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 5004222733f88..a88e31ef833a7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -81,12 +81,6 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([linux/pgtable.h]) - dnl # - dnl # v5.19-rc1- c9cad937c0 - dnl # drm/amdgpu: add drm buddy support to amdgpu - dnl # - AC_KERNEL_CHECK_HEADERS([drm/drm_buddy.h]) - dnl # dnl # v6.1-rc2-542-g8ab59da26bc0 dnl # drm/fb-helper: Move generic fbdev emulation into separate source file From 27bad4c0a1d80d383b2e0e7a928df75d230b5b6c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 28 Jun 2023 11:01:55 +0800 Subject: [PATCH 1025/2653] drm/amdkcl: Update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 93 ------------------------ 1 file changed, 93 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b973f3cc82458..975baa2ee9204 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -177,51 +177,9 @@ drm_driver* */ #define HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG 1 -/* drm_atomic_get_old_crtc_state() and drm_atomic_get_new_crtc_state() are - available */ -#define HAVE_DRM_ATOMIC_GET_CRTC_STATE 1 - -/* drm_atomic_get_new_plane_state() is available */ -#define HAVE_DRM_ATOMIC_GET_NEW_PLANE_STATE 1 - /* drm_atomic_helper_calc_timestamping_constants() is available */ #define HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS 1 -/* drm_atomic_helper_check_plane_state() is available */ -#define HAVE_DRM_ATOMIC_HELPER_CHECK_PLANE_STATE 1 - -/* drm_atomic_helper_shutdown() is available */ -#define HAVE_DRM_ATOMIC_HELPER_SHUTDOWN 1 - -/* drm_atomic_helper_wait_for_flip_done() is available */ -#define HAVE_DRM_ATOMIC_HELPER_WAIT_FOR_FLIP_DONE 1 - -/* {drm_atomic_helper_crtc_set_property, drm_atomic_helper_plane_set_property, - drm_atomic_helper_connector_set_property, drm_atomic_helper_connector_dpms} - is available */ -/* #undef HAVE_DRM_ATOMIC_HELPER_XXX_SET_PROPERTY */ - -/* drm_atomic_nonblocking_commit() is available */ -#define HAVE_DRM_ATOMIC_NONBLOCKING_COMMIT 1 - -/* drm_atomic_plane_disabling() wants drm_plane_state * arg */ -#define HAVE_DRM_ATOMIC_PLANE_DISABLING_DRM_PLANE_STATE 1 - -/* drm_atomic_private_obj_init() is available */ -#define HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT 1 - -/* drm_atomic_private_obj_init() has p,p,p,p interface */ -#define HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT_P_P_P_P 1 - -/* whether struct drm_atomic_state have async_update */ -#define HAVE_DRM_ATOMIC_STATE_ASYNC_UPDATE 1 - -/* drm_atomic_state_put() is available */ -#define HAVE_DRM_ATOMIC_STATE_PUT 1 - -/* drm_color_lut_size() is available */ -#define HAVE_DRM_COLOR_LUT_SIZE 1 - /* drm_connector_atomic_hdr_metadata_equal() is available */ #define HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL 1 @@ -289,9 +247,6 @@ drm_atomic_state arg */ #define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE 1 -/* drm_crtc_init_with_planes() wants name */ -#define HAVE_DRM_CRTC_INIT_WITH_PLANES_VALID_WITH_NAME 1 - /* drm_debug_enabled() is available */ #define HAVE_DRM_DEBUG_ENABLED 1 @@ -532,9 +487,6 @@ /* drm_gem_prime_export() with p,i arg is available */ #define HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI 1 -/* drm_drv_uses_atomic_modeset() is available */ -#define HAVE_DRM_DRV_USES_ATOMIC_MODESET 1 - /* drm_dsc_compute_rc_parameters() is available */ #define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 @@ -575,9 +527,6 @@ /* drm_gem_object_funcs.vmap hsa iosys_map arg */ #define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG 1 -/* drm_gem_object_lookup() wants 2 args */ -#define HAVE_DRM_GEM_OBJECT_LOOKUP_2ARGS 1 - /* drm_gem_object_put() is available */ #define HAVE_DRM_GEM_OBJECT_PUT 1 @@ -629,12 +578,6 @@ /* drm_need_swiotlb() is availablea */ #define HAVE_DRM_NEED_SWIOTLB 1 -/* drm atomic nonblocking commit support is available */ -#define HAVE_DRM_NONBLOCKING_COMMIT_SUPPORT 1 - -/* drm_plane_helper_check_state is available */ -/* #undef HAVE_DRM_PLANE_HELPER_CHECK_STATE */ - /* drm_plane_helper_destroy() is available */ /* #undef HAVE_DRM_PLANE_HELPER_DESTROY */ @@ -666,42 +609,12 @@ /* drm_simple_encoder is available */ #define HAVE_DRM_SIMPLE_ENCODER_INIT 1 -/* drm_syncobj_fence_get() is available */ -/* #undef HAVE_DRM_SYNCOBJ_FENCE_GET */ - -/* drm_syncobj_find_fence() is available */ -#define HAVE_DRM_SYNCOBJ_FIND_FENCE 1 - -/* whether drm_syncobj_find_fence() wants 3 args */ -/* #undef HAVE_DRM_SYNCOBJ_FIND_FENCE_3ARGS */ - -/* whether drm_syncobj_find_fence() wants 4 args */ -/* #undef HAVE_DRM_SYNCOBJ_FIND_FENCE_4ARGS */ - -/* whether drm_syncobj_find_fence() wants 5 args */ -#define HAVE_DRM_SYNCOBJ_FIND_FENCE_5ARGS 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 -/* drm_universal_plane_init() wants 7 args */ -/* #undef HAVE_DRM_UNIVERSAL_PLANE_INIT_7ARGS */ - -/* drm_universal_plane_init() wants 8 args */ -/* #undef HAVE_DRM_UNIVERSAL_PLANE_INIT_8ARGS */ - -/* drm_universal_plane_init() wants 9 args */ -#define HAVE_DRM_UNIVERSAL_PLANE_INIT_9ARGS 1 - /* drm_vblank->time uses ktime_t type */ #define HAVE_DRM_VBLANK_USE_KTIME_T 1 -/* drm_vma_node_verify_access() 2nd argument is drm_file */ -#define HAVE_DRM_VMA_NODE_VERIFY_ACCESS_HAS_DRM_FILE 1 - -/* Variable refresh rate(vrr) is supported */ -#define HAVE_DRM_VRR_SUPPORTED 1 - /* fault_flag_allow_retry_first() is available */ #define HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST 1 @@ -930,9 +843,6 @@ /* release_pages() wants 2 args */ #define HAVE_MM_RELEASE_PAGES_2ARGS 1 -/* num_u32_u32 is available */ -#define HAVE_MUL_U32_U32 1 - /* pcie_aspm_enabled() is available */ #define HAVE_PCIE_ASPM_ENABLED 1 @@ -1029,9 +939,6 @@ /* struct drm_connector_state->self_refresh_aware is available */ #define HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE 1 -/* drm_connector->ycbcr_420_allowed is available */ -#define HAVE_STRUCT_DRM_CONNECTOR_YCBCR_420_ALLOWED 1 - /* HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL 1 From 56788ae659d245db1d92c1104ec1f041f70b6595 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 11 Apr 2023 18:18:49 +0800 Subject: [PATCH 1026/2653] drm/amdkcl: fake drm_dp_atomic_release_time_slots() It's caused by df78f7f660cdd5974b68649a95dbb34da4d4dfa7 "drm/display/dp_mst: Call them time slots, not VCPI slots" Signed-off-by: Asher Song Reviewed-by: Perry Yuan Reviewed-by: Guchun Chen Reviewed-by: Leslie Shi Reviewed-by: bobzhou --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 -- drivers/gpu/drm/amd/dkms/config/config.h | 11 +-- .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 69 +++++++++++++------ .../backport/kcl_drm_dp_mst_helper_backport.h | 16 ++++- 4 files changed, 71 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 29e8fd863d4df..86a0b8c1345e6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -595,15 +595,11 @@ dm_dp_mst_detect(struct drm_connector *connector, static int dm_dp_mst_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state) { -#ifdef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr; struct drm_dp_mst_port *mst_port = aconnector->mst_output_port; return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); -#else - return 0; -#endif } #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 975baa2ee9204..48422a616c7fb 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -313,6 +313,12 @@ /* drm_dp_atomic_find_time_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS 1 +/* drm_dp_atomic_find_vcpi_slots() wants 5args */ +/* #undef HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ + +/* drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is available */ +/* #undef HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT */ + /* drm_dp_mst_atomic_setup_commit() is available */ /* #undef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT */ @@ -320,10 +326,7 @@ /* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ /* drm_dp_atomic_release_time_slots() is available */ -/* #undef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS */ - -/* drm_dp_atomic_find_vcpi_slots() wants 5args */ -#define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS 1 +#define HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index c89bcdbf10edd..d50c35a4fd1bc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -22,8 +22,55 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ ]) ]) + dnl # -dnl # commit v6.1-rc1~27-df78f7f660cd +dnl # commit v5.19-rc6-1758-gdf78f7f660cd +dnl # drm/display/dp_mst: Call them time slots, not VCPI slots +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ],[ + int ret; + ret = drm_dp_atomic_release_time_slots(NULL, NULL, NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS, 1, + [drm_dp_atomic_release_time_slots() is available]) + ],[ + dnl # + dnl # commit v4.20-rc4-1031-geceae1472467 + dnl # drm/dp_mst: Start tracking per-port VCPI allocations + dnl # + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ],[ + int ret; + struct drm_dp_mst_port *port; + ret = drm_dp_atomic_release_vcpi_slots(NULL, NULL, port); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT, 1, + [drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is available]) + ]) + ]) + ]) +]) + + +dnl # +dnl # commit v5.19-rc6-1758-gdf78f7f660cd dnl # drm/display/dp_mst: Call them time slots, not VCPI slots dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS], [ @@ -102,29 +149,11 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK], [ ]) ]) -dnl # -dnl # commit v6.1-rc1~27-df78f7f660cd -dnl # drm/display/dp_mst: Call them time slots, not VCPI slots -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - int ret; - ret = drm_dp_atomic_release_time_slots(NULL, NULL, NULL); - ],[ - AC_DEFINE(HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS, 1, - [drm_dp_atomic_release_time_slots() is available]) - ]) - ]) -]) - AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS + AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK - AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS ]) diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 97af03bd3e628..c6de78678e856 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -38,6 +38,8 @@ int _kcl_drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) #define drm_dp_calc_pbn_mode _kcl_drm_dp_calc_pbn_mode #endif + +#if !defined(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS) #if !defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS) static inline int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, @@ -63,7 +65,6 @@ int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, #define drm_dp_atomic_find_vcpi_slots _kcl_drm_dp_atomic_find_vcpi_slots #endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ -#if !defined(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS) static inline int _kcl_drm_dp_atomic_find_time_slots(struct drm_atomic_state *state, struct drm_dp_mst_topology_mgr *mgr, @@ -73,6 +74,19 @@ int _kcl_drm_dp_atomic_find_time_slots(struct drm_atomic_state *state, return drm_dp_atomic_find_vcpi_slots(state, mgr, port, pbn, pbn_div); } #define drm_dp_atomic_find_time_slots _kcl_drm_dp_atomic_find_time_slots +#endif /* HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS */ + +#if !defined(HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS) +#ifdef HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT +static inline +int _kcl_drm_dp_atomic_release_time_slots(struct drm_atomic_state *state, + struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port) +{ + return drm_dp_atomic_release_vcpi_slots(state, mgr, port); +} +#define drm_dp_atomic_release_time_slots _kcl_drm_dp_atomic_release_time_slots +#endif #endif #ifndef HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS From 44852f6657773c7f27f33a01a0446e7f2e9a0726 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 6 Apr 2023 17:10:27 +0800 Subject: [PATCH 1027/2653] drm/amdkcl: update dkms/config/config.h Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 189 +++++++++-------------- 1 file changed, 71 insertions(+), 118 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 48422a616c7fb..91f82ff6e6b87 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -15,11 +15,10 @@ /* struct acpi_srat_generic_affinity is available */ #define HAVE_ACPI_SRAT_GENERIC_AFFINITY 1 - + /* acpi_video_backlight_use_native() is available */ #define HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE 1 - /* acpi_video_register_backlight() is available */ #define HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT 1 @@ -47,6 +46,9 @@ /* amd_iommu_pc_supported() is available */ #define HAVE_AMD_IOMMU_PC_SUPPORTED 1 +/* apple_gmux_detect() is available */ +#define HAVE_APPLE_GMUX_DETECT 1 + /* arch_io_{reserve/free}_memtype_wc() are available */ #define HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC 1 @@ -59,7 +61,7 @@ /* backlight_device_set_brightness() is available */ #define HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS 1 -/* bitmap_free() is available */ +/* bitmap_free(),bitmap_alloc(),bitmap_zalloc is available */ #define HAVE_BITMAP_FUNCS 1 /* bitmap_to_arr32() is available */ @@ -80,6 +82,9 @@ /* debugfs_create_file_size() is available */ #define HAVE_DEBUGFS_CREATE_FILE_SIZE 1 +/* kobj_type->default_groups is available */ +#define HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE 1 + /* devcgroup_check_permission() is available */ #define HAVE_DEVCGROUP_CHECK_PERMISSION 1 @@ -110,6 +115,9 @@ /* dma_fence_chain_alloc() is available */ #define HAVE_DMA_FENCE_CHAIN_ALLOC 1 +/* dma_fence_chain_contained() is available */ +#define HAVE_DMA_FENCE_CHAIN_CONTAINED 1 + /* dma_fence_describe() is available */ #define HAVE_DMA_FENCE_DESCRIBE 1 @@ -140,7 +148,7 @@ /* dma_resv->seq is seqcount_ww_mutex_t */ /* #undef HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T */ -/* bug for missing dma_resv->seq */ +/* Reporting dma_resv->seq bug */ /* #undef HAVE_DMA_RESV_SEQ_BUG */ /* down_read_killable() is available */ @@ -149,30 +157,12 @@ /* down_write_killable() is available */ #define HAVE_DOWN_WRITE_KILLABLE 1 -/* fsleep() is available */ -#define HAVE_FSLEEP 1 - -/* drm_dp_mst_connector_early_unregister() is available */ -#define HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 - -/* drm_dp_mst_connector_late_register() is available */ -#define HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER 1 - -/* drm_accurate_vblank_count() is available */ -/* #undef HAVE_DRM_ACCURATE_VBLANK_COUNT */ - -/* DRM_AMDGPU_FENCE_TO_HANDLE is defined */ -#define HAVE_DRM_AMDGPU_FENCE_TO_HANDLE 1 - /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_AMDGPU_PCIID_H */ /* Define to 1 if you have the header file. */ #define HAVE_DRM_AMD_ASIC_TYPE_H 1 -/* drm_aperture_remove_* is availablea */ -#define HAVE_DRM_APERTURE 1 - /* drm_aperture_remove_conflicting_pci_framebuffers() second arg is drm_driver* */ #define HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG 1 @@ -271,7 +261,8 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DISPLAY_DRM_DP_HELPER_H 1 -/* Define to 1 if you have the header file. */ +/* Define to 1 if you have the header file. + */ #define HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H 1 /* Define to 1 if you have the header file. */ @@ -298,25 +289,26 @@ /* display_info->is_hdmi is available */ #define HAVE_DRM_DISPLAY_INFO_IS_HDMI 1 -/* display_info->max_tmds_clock is available */ -#define HAVE_DRM_DISPLAY_INFO_MAX_TMDS_CLOCK 1 - -/* struct drm_display_info has monitor_range member */ -#define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 - /* display_info->luminance_range is available */ #define HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE 1 /* display_info->max_dsc_bpp is available */ #define HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP 1 +/* struct drm_display_info has monitor_range member */ +#define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 + /* drm_dp_atomic_find_time_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS 1 /* drm_dp_atomic_find_vcpi_slots() wants 5args */ /* #undef HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ -/* drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is available */ +/* drm_dp_atomic_release_time_slots() is available */ +#define HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS 1 + +/* drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is + available */ /* #undef HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT */ /* drm_dp_mst_atomic_setup_commit() is available */ @@ -325,15 +317,9 @@ /* drm_dp_mst_atomic_wait_for_dependencies() is available */ /* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ -/* drm_dp_atomic_release_time_slots() is available */ -#define HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS - /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 -/* apple_gmux_detect() is available */ -#define HAVE_APPLE_GMUX_DETECT 1 - /* drm_dp_calc_pbn_mode() wants 3args */ #define HAVE_DRM_DP_CALC_PBN_MODE_3ARGS 1 @@ -364,6 +350,12 @@ /* drm_dp_mst_atomic_enable_dsc() wants 5args */ /* #undef HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS */ +/* drm_dp_mst_connector_early_unregister() is available */ +#define HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 + +/* drm_dp_mst_connector_late_register() is available */ +#define HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER 1 + /* drm_dp_mst_detect_port() wants p,p,p,p args */ #define HAVE_DRM_DP_MST_DETECT_PORT_PPPP 1 @@ -373,15 +365,15 @@ /* drm_dp_mst_{get,put}_port_malloc() is available */ #define HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC 1 +/* drm_dp_mst_port struct has full_pbn member */ +#define HAVE_DRM_DP_MST_PORT_FULL_PBN 1 + /* struct drm_dp_mst_port has passthrough_aux member */ -/* #undef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX */ +#define HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX 1 /* drm_dp_mst_root_conn_atomic_check() is available */ /* #undef HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK */ -/* drm_dp_mst_port struct has full_pbn member */ -#define HAVE_DRM_DP_MST_PORT_FULL_PBN 1 - /* struct drm_dp_mst_topology_cbs->destroy_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR */ @@ -419,14 +411,11 @@ #define HAVE_DRM_DP_START_CRC 1 /* drm_dp_update_payload_part1() function has start_slot argument */ -#define HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG 1 +/* #undef HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG */ -/* drm_driver->gem_prime_res_obj() is available */ +/* drm_driver->gem_prime_res_obj() is availab/le */ /* #undef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ */ -/* drm_vblank struct use ktime_t for time field */ -#define HAVE_DRM_VBLANK_USE_KTIME_T 1 - /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRMP_H */ @@ -445,26 +434,8 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRM_BACKPORT_H */ -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_CONNECTOR_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_DEBUGFS_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_DEVICE_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_DRV_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_HDCP_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_IOCTL_H 1 - -/* Define to 1 if you have the header file. */ -/* #undef HAVE_DRM_DRM_IRQ_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_FBDEV_GENERIC_H 1 /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_MANAGED_H 1 @@ -475,9 +446,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_FBDEV_GENERIC_H 1 - /* drm_driver_feature DRIVER_IRQ_SHARED is available */ /* #undef HAVE_DRM_DRV_DRIVER_IRQ_SHARED */ @@ -493,6 +461,12 @@ /* drm_dsc_compute_rc_parameters() is available */ #define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 +/* struct drm_dsc_config has member simple_422 */ +#define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 + +/* drm_dsc_pps_payload_pack() is available */ +#define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 + /* drm_fb_helper_single_add_all_connectors() && drm_fb_helper_remove_one_connector() are symbol */ /* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ @@ -521,9 +495,6 @@ /* drm_format_info.block_w and rm_format_info.block_h is available */ #define HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED 1 - /* drm_gem_plane_helper_prepare_fb() is available */ - #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 - /* drm_gem_object_funcs->vmap() has 2 args */ #define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS 1 @@ -539,8 +510,8 @@ /* ttm_buffer_object->base is available */ #define HAVE_DRM_GEM_OBJECT_RESV 1 -/* drm_gen_fb_init_with_funcs() is available */ -#define HAVE_DRM_GEN_FB_INIT_WITH_FUNCS 1 +/* drm_gem_plane_helper_prepare_fb() is available */ +#define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 @@ -563,6 +534,9 @@ /* drm_memcpy_from_wc() is availablea and has struct iosys_map* arg */ #define HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG 1 +/* drm_modeset_backoff() has int return */ +#define HAVE_DRM_MODESET_BACKOFF_RETURN_INT 1 + /* drm_mode_config->dp_subconnector_property is available */ #define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 @@ -572,11 +546,8 @@ /* drm_mode_config->fb_modifiers_not_supported is available */ #define HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED 1 -/* drm_mode_config_funcs->atomic_state_alloc() is available */ -#define HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC 1 - /* drm_mode_init() is available */ -#define HAVE_DRM_MODE_INTT 1 +#define HAVE_DRM_MODE_INIT 1 /* drm_need_swiotlb() is availablea */ #define HAVE_DRM_NEED_SWIOTLB 1 @@ -618,11 +589,14 @@ /* drm_vblank->time uses ktime_t type */ #define HAVE_DRM_VBLANK_USE_KTIME_T 1 +/* struct drm_vma_offset_node has readonly field */ +/* #undef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD */ + /* fault_flag_allow_retry_first() is available */ #define HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST 1 -/* drm_mode_object->free_cb is available */ -/* #undef HAVE_FREE_CB_IN_STRUCT_DRM_MODE_OBJECT */ +/* fsleep() is available */ +#define HAVE_FSLEEP 1 /* fs_reclaim_acquire() is available */ #define HAVE_FS_RECLAIM_ACQUIRE 1 @@ -660,6 +634,9 @@ /* hmm_range_fault() wants 1 arg */ #define HAVE_HMM_RANGE_FAULT_1ARG 1 +/* hypervisor_is_type() is available */ +#define HAVE_HYPERVISOR_IS_TYPE 1 + /* struct i2c_lock_operations is defined */ #define HAVE_I2C_LOCK_OPERATIONS_STRUCT 1 @@ -693,6 +670,9 @@ /* kallsyms_lookup_name is available */ /* #undef HAVE_KALLSYMS_LOOKUP_NAME */ +/* close_fd() is available */ +#define HAVE_KERNEL_CLOSE_FD 1 + /* kernel_write() take arg type of position as pointer */ #define HAVE_KERNEL_WRITE_PPOS 1 @@ -702,8 +682,8 @@ /* krealloc_array() is available */ #define HAVE_KREALLOC_ARRAY 1 -/* kref_read() function is available */ -#define HAVE_KREF_READ 1 +/* ksys_fd() is available */ +/* #undef HAVE_KSYS_CLOSE_FD */ /* ksys_sync_helper() is available */ #define HAVE_KSYS_SYNC_HELPER 1 @@ -807,9 +787,6 @@ /* list_rotate_to_front() is available */ #define HAVE_LIST_ROTATE_TO_FRONT 1 -/* strurct pci_dev->ltr_path is available */ -#define HAVE_PCI_DEV_LTR_PATH 1 - /* enum MCE_PRIO_UC is available */ #define HAVE_MCE_PRIO_UC 1 @@ -819,6 +796,9 @@ /* memalloc_noreclaim_save() is available */ #define HAVE_MEMALLOC_NORECLAIM_SAVE 1 +/* struct migrate_vma has fault_page */ +#define HAVE_MIGRATE_VMA_FAULT_PAGE 1 + /* migrate_vma->pgmap_owner is available */ #define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 @@ -855,6 +835,9 @@ /* pci_dev_id() is available */ #define HAVE_PCI_DEV_ID 1 +/* strurct pci_dev->ltr_path is available */ +#define HAVE_PCI_DEV_LTR_PATH 1 + /* struct pci_driver has field dev_groups */ #define HAVE_PCI_DRIVER_DEV_GROUPS 1 @@ -876,8 +859,8 @@ /* vm_insert_mixed() wants pfn_t arg */ /* #undef HAVE_PFN_T_VM_INSERT_MIXED */ -/* pm_genpd_remove_device() wants 2 arguments */ -/* #undef HAVE_PM_GENPD_REMOVE_DEVICE_2ARGS */ +/* pm_suspend_target_state is available */ +#define HAVE_PM_SUSPEND_TARGET_STATE 1 /* pm_suspend_via_firmware() is available */ #define HAVE_PM_SUSPEND_VIA_FIRMWARE 1 @@ -918,9 +901,6 @@ /* is_smca_umc_v2() is available */ /* #undef HAVE_SMCA_UMC_V2 */ -/* struct dma_buf_ops->allow_peer2peer is available */ -#define HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER 1 - /* struct dma_buf_attach_ops->allow_peer2peer is available */ #define HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER 1 @@ -930,9 +910,6 @@ /* struct dma_fence_chain is available */ #define HAVE_STRUCT_DMA_FENCE_CHAIN 1 -/* dma_fence_chain_contained() is available */ -#define HAVE_DMA_FENCE_CHAIN_CONTAINED 1 - /* struct drm_connector_state->duplicated is available */ #define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 @@ -1045,8 +1022,8 @@ /* ww_mutex_trylock() has context arg */ #define HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG 1 -/* is_device_page is available */ -/* #undef HAVE_ZONE_DEVICE_PUBLIC */ +/* enum x86_hypervisor_type is available */ +#define HAVE_X86_HYPERVISOR_TYPE 1 /* zone_managed_pages() is available */ #define HAVE_ZONE_MANAGED_PAGES 1 @@ -1057,36 +1034,12 @@ /* __dma_fence_is_later() is available and has ops arg */ #define HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG 1 -/* struct drm_dsc_config has member simple_422 */ -#define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 - -/* drm_dsc_pps_payload_pack() is available */ -#define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 - /* __drm_atomic_helper_crtc_reset() is available */ #define HAVE___DRM_ATOMIC_HELPER_CRTC_RESET 1 /* __kthread_should_park() is available */ #define HAVE___KTHREAD_SHOULD_PARK 1 -/* kobj_type->default_groups is available */ -#define HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE 1 - -/* close_fd() is available */ -#define HAVE_KERNEL_CLOSE_FD 1 - -/* ksys_close() is available */ -#define HAVE_KSYS_CLOSE_FD 1 - -/* pm_suspend_target_state is available */ -#define HAVE_PM_SUSPEND_TARGET_STATE 1 - -/* enum x86_hypervisor_type is available */ -#define HAVE_X86_HYPERVISOR_TYPE 1 - -/* hypervisor_is_type() is available */ -#define HAVE_HYPERVISOR_IS_TYPE 1 - /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" From 6181df55e37d625d8adbc6e026705ba03b01f3d5 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 3 Apr 2023 13:46:08 +0800 Subject: [PATCH 1028/2653] drm/amdkcl: fake kcl copy of zone_device_page_init Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 14 ++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/zone_device_page_init.m4 | 12 ++++++++++++ include/kcl/kcl_mm.h | 4 ++++ 5 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index 9d7534002b7e1..d151a6db046cc 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -5,6 +5,7 @@ * Copyright (C) 1991, 1992 Linus Torvalds */ #include +#include #ifndef HAVE_MMPUT_ASYNC void (*_kcl_mmput_async)(struct mm_struct *mm); @@ -16,6 +17,19 @@ void __kcl_mmput_async(struct mm_struct *mm) } #endif +#ifndef HAVE_ZONE_DEVICE_PAGE_INIT +/* copied from v6.0-rc3-597-g0dc45ca1ce18 mm/memremap.c and modified for kcl usage */ +void zone_device_page_init(struct page *page) +{ +/* v5.17-rc4-75-g27674ef6c73f mm: remove the extra ZONE_DEVICE struct page refcount */ +#if IS_ENABLED(CONFIG_DEV_PAGEMAP_OPS) + get_page(page); +#endif + lock_page(page); +} +EXPORT_SYMBOL_GPL(zone_device_page_init); +#endif + void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 91f82ff6e6b87..f864d87d135a2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1025,6 +1025,9 @@ /* enum x86_hypervisor_type is available */ #define HAVE_X86_HYPERVISOR_TYPE 1 +/* zone_device_page_init() is available */ +#define HAVE_ZONE_DEVICE_PAGE_INIT 1 + /* zone_managed_pages() is available */ #define HAVE_ZONE_MANAGED_PAGES 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ce5db63b7f78a..7ac69da15aed0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -191,6 +191,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE AC_AMDGPU_RB_ADD_CACHED AC_AMDGPU_APPLE_GMUX_DETECT + AC_AMDGPU_ZONE_DEVICE_PAGE_INIT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 b/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 new file mode 100644 index 0000000000000..d73aab950a652 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 @@ -0,0 +1,12 @@ +dnl # +dnl # v6.0-rc3-597-g0dc45ca1ce18 mm/memremap.c: take a pgmap reference on page allocation +dnl # v6.0-rc3-596-gef233450898f mm: free device private pages have zero refcount +dnl # v5.17-rc4-75-g27674ef6c73f mm: remove the extra ZONE_DEVICE struct page refcount +dnl # +AC_DEFUN([AC_AMDGPU_ZONE_DEVICE_PAGE_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([zone_device_page_init], [mm/memremap.c], [ + AC_DEFINE(HAVE_ZONE_DEVICE_PAGE_INIT, 1, [zone_device_page_init() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 112aeb2591136..2379879ed9932 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -26,6 +26,10 @@ extern void (*_kcl_mmput_async)(struct mm_struct *mm); #endif +#ifndef HAVE_ZONE_DEVICE_PAGE_INIT +void zone_device_page_init(struct page *page); +#endif + #ifndef HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST static inline bool fault_flag_allow_retry_first(unsigned int flags) { From c8027ba80eccc2e94d041776ca172f46a2d3749c Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 29 Mar 2023 18:50:38 -0400 Subject: [PATCH 1029/2653] drm/amdkfd: Remove deprecated references to ZONE_DEVICE_PUBLIC This was replaced by ZONE_DEVICE_COHERENT in the final upstream version. Signed-off-by: Felix Kuehling Reviewed-by: Alex Sierra --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 6d6b07de96df8..5f5f6c92c6b48 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -221,13 +221,8 @@ svm_migrate_get_vram_page(struct svm_range *prange, unsigned long pfn) page = pfn_to_page(pfn); svm_range_bo_ref(prange->svm_bo); page->zone_device_data = prange->svm_bo; -#ifdef HAVE_ZONE_DEVICE_PUBLIC - VM_BUG_ON_PAGE(page_ref_count(page), page); - init_page_count(page); -#else #if IS_ENABLED(CONFIG_DEV_PAGEMAP_OPS) get_page(page); -#endif #endif lock_page(page); } From 947cea91f0e0563717661f9ef786bcedbdf92110 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 29 Mar 2023 19:19:38 -0400 Subject: [PATCH 1030/2653] drm/amdkfd: Fix HMM migrations on monolithic builds Use the new zone_device_page_init KCL helper, which encapsulates all the logic around locking and reference counting device pages. This makes the DKMS branch code in svm_migrate_get_vram_page look the same as upstream. Cc: Flora Cui Signed-off-by: Felix Kuehling Reviewed-and-tested-by: Guchun Chen --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 5f5f6c92c6b48..f58d070c9cc88 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -221,10 +221,7 @@ svm_migrate_get_vram_page(struct svm_range *prange, unsigned long pfn) page = pfn_to_page(pfn); svm_range_bo_ref(prange->svm_bo); page->zone_device_data = prange->svm_bo; -#if IS_ENABLED(CONFIG_DEV_PAGEMAP_OPS) - get_page(page); -#endif - lock_page(page); + zone_device_page_init(page); } static void From 7d26907ddb4fd44f1da32b78b44fc30c962f0c2c Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 17 Apr 2023 16:30:57 +0800 Subject: [PATCH 1031/2653] drm/amdkcl: convert gfx.kiq to array type It's caused by 81a6a08325e46b446a249fca7f76b77937b3f77d "drm/amdgpu: convert gfx.kiq to array type (v3)" After modifying the struct amdgpu_gfx, some non-upstream code need to be updated. Signed-off-by: bobzhou Reviewed-by: Guchun Chen --- .../drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 24 +++++++++---------- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 +++---- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 8 +++---- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +++---- 4 files changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index 1dd189536c764..f58291c1fd40b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -27,32 +27,32 @@ void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, bool cntl) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; - spin_lock(&adev->gfx.kiq.ring_lock); + spin_lock(&adev->gfx.kiq[0].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); if (cntl) adev->gfx.spmfuncs->start(adev); else adev->gfx.spmfuncs->stop(adev); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq.ring_lock); + spin_unlock(&adev->gfx.kiq[0].ring_lock); } void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; - spin_lock(&adev->gfx.kiq.ring_lock); + spin_lock(&adev->gfx.kiq[0].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); adev->gfx.spmfuncs->set_rdptr(adev, rptr); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq.ring_lock); + spin_unlock(&adev->gfx.kiq[0].ring_lock); } int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm *vm, u64 gpu_addr, u32 size) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; int r; if (!adev->gfx.rlc.funcs->update_spm_vmid) @@ -66,24 +66,24 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm * adev->gfx.rlc.funcs->update_spm_vmid(adev, 0); /* set spm ring registers */ - spin_lock(&adev->gfx.kiq.ring_lock); + spin_lock(&adev->gfx.kiq[0].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); adev->gfx.spmfuncs->set_spm_perfmon_ring_buf(adev, gpu_addr, size); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq.ring_lock); + spin_unlock(&adev->gfx.kiq[0].ring_lock); return r; } void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm *vm) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; /* stop spm stream and interrupt */ - spin_lock(&adev->gfx.kiq.ring_lock); + spin_lock(&adev->gfx.kiq[0].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); adev->gfx.spmfuncs->stop(adev); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq.ring_lock); + spin_unlock(&adev->gfx.kiq[0].ring_lock); amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB_0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 266382e7713af..3a19ff380f3f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7799,7 +7799,7 @@ static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, static void gfx_v10_0_spm_start(struct amdgpu_device *adev) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, 0); @@ -7829,7 +7829,7 @@ static void gfx_v10_0_spm_start(struct amdgpu_device *adev) static void gfx_v10_0_spm_stop(struct amdgpu_device *adev) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; data = REG_SET_FIELD(0, CP_PERFMON_CNTL, PERFMON_STATE, @@ -7845,7 +7845,7 @@ static void gfx_v10_0_spm_stop(struct amdgpu_device *adev) static void gfx_v10_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), rptr); @@ -7854,7 +7854,7 @@ static void gfx_v10_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) static void gfx_v10_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, u64 gpu_addr, u32 size) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_RING_BASE_LO), lower_32_bits(gpu_addr)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index c558ba8f1500f..de5e273967848 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -5237,7 +5237,7 @@ static void gfx_v8_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, static void gfx_v8_0_spm_start(struct amdgpu_device *adev) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, 0); @@ -5262,7 +5262,7 @@ static void gfx_v8_0_spm_start(struct amdgpu_device *adev) static void gfx_v8_0_spm_stop(struct amdgpu_device *adev) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; data = REG_SET_FIELD(0, CP_PERFMON_CNTL, @@ -5276,7 +5276,7 @@ static void gfx_v8_0_spm_stop(struct amdgpu_device *adev) static void gfx_v8_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_RING_RDPTR, rptr); } @@ -5284,7 +5284,7 @@ static void gfx_v8_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) static void gfx_v8_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, u64 gpu_addr, u32 size) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_PERFMON_RING_BASE_LO, lower_32_bits(gpu_addr)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index eb6d5b4278b94..09353385b4772 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4802,7 +4802,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) static void gfx_v9_0_spm_start(struct amdgpu_device *adev) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; data = RREG32_SOC15(GC, 0, mmRLC_SPM_PERFMON_CNTL); @@ -4826,7 +4826,7 @@ static void gfx_v9_0_spm_start(struct amdgpu_device *adev) static void gfx_v9_0_spm_stop(struct amdgpu_device *adev) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, @@ -4842,7 +4842,7 @@ static void gfx_v9_0_spm_stop(struct amdgpu_device *adev) static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), rptr); @@ -4850,7 +4850,7 @@ static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) static void gfx_v9_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, u64 gpu_addr, u32 size) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_RING_BASE_LO), lower_32_bits(gpu_addr)); From 9b8c545a25d44675597ae77ebcdb74899755026d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 17 Apr 2023 15:13:41 +0800 Subject: [PATCH 1032/2653] drm/amdkcl: drop obsolete file symbols not needed anymore Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/symbols | 1 - drivers/gpu/drm/amd/dkms/pre-build.sh | 9 --------- 3 files changed, 1 insertion(+), 11 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/symbols diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 306044881cd3d..a444ae80f06af 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: MIT -amdkcl-y += main.o symbols.o kcl_common.o +amdkcl-y += main.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += dma-buf/dma-resv.o diff --git a/drivers/gpu/drm/amd/amdkcl/symbols b/drivers/gpu/drm/amd/amdkcl/symbols deleted file mode 100644 index fe167314985be..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/symbols +++ /dev/null @@ -1 +0,0 @@ -SYMS="" diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 07df3f07ea532..3d7f2084cae3e 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -27,17 +27,8 @@ version_le () { [ "$KERNELVER_BASE" = "$oldest" ] } -source $KCL/symbols source $KCL/files -# lookup symbol address. obsolete. -echo '// auto generated by DKMS pre-build.sh' > $KCL/symbols.c -for sym in $SYMS; do - awk -v sym=$sym '$3 == sym { - print "void *_kcl_" $3 " = (void *)0x" $1 ";" - }' /boot/System.map-$KERNELVER >>$KCL/symbols.c -done - sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ -e '/dma_resv_lockdep/,/subsys_initcall/d' $KCL/dma-buf/dma-resv.c sed -i -e '/extern struct ww_class reservation_ww_class/i #include ' \ From f338b9bd22772e4827fc2fac9cae7eaf5a5383a0 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 19 Apr 2023 10:27:09 +0800 Subject: [PATCH 1033/2653] drm/amdkcl: fix warning for kcl_apple-gmux.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit add linux/pnp.h for build warning include/kcl/kcl_apple-gmux.h:8:45: warning: ‘struct pnp_dev’ declared inside parameter list will not be visible outside of this definition or declaration static inline bool apple_gmux_detect(struct pnp_dev *pnp_dev, bool *indexed_ret) ^~~~~~~ Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- include/kcl/kcl_apple-gmux.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/kcl/kcl_apple-gmux.h b/include/kcl/kcl_apple-gmux.h index 27d96810046e7..4e478cb3a1e87 100644 --- a/include/kcl/kcl_apple-gmux.h +++ b/include/kcl/kcl_apple-gmux.h @@ -2,6 +2,7 @@ #define AMDKCL_APPLE_GMUX_H #include +#include #ifndef HAVE_APPLE_GMUX_DETECT #if IS_ENABLED(CONFIG_APPLE_GMUX) From f2d92384039ae80b55fbab860c5a04a45011f1c3 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Tue, 18 Apr 2023 15:06:01 +0800 Subject: [PATCH 1034/2653] drm/amdkcl: add fake macros for link_edp_panel_control.c It's caused by 200199ae9a64ad94e42ea995f9a9d4d362b3ff99 "drm/amd/display: Adding support for VESA SCR" Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- include/kcl/kcl_drm_dp_helper.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 9f921c3d9db24..532d8160eba9d 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -350,4 +350,18 @@ enum drm_dp_phy { #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */ #endif +/* + * v6.1-4885-g200199ae9a64 + * drm/amd/display: Adding support for VESA SCR + */ +#ifndef DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE +#define DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE (1 << 4) +#endif +#ifndef DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE +#define DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE (1 << 7) +#endif +#ifndef DP_EDP_PANEL_TARGET_LUMINANCE_VALUE +#define DP_EDP_PANEL_TARGET_LUMINANCE_VALUE 0x734 +#endif + #endif /* _KCL_DRM_DP_HELPER_H_ */ From e0834812b3c6cf5870e4ae380f15c81d82efe42f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 19 Apr 2023 10:47:22 +0800 Subject: [PATCH 1035/2653] drm/amdkcl: include string_helpers.h for str_yes_no() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit dkms build on some distro system reports amd/amdgpu/../display/dc/link/protocols/link_dp_capability.c:1708:47: error: implicit declaration of function ‘str_yes_no’; did you mean ‘strcspn’? [-Werror=implicit-function-declaration] these distro systems need linux/string_helpers.h, so include it. Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- include/kcl/kcl_string_helpers.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_string_helpers.h b/include/kcl/kcl_string_helpers.h index ceac153f44bfd..e02c0059b3ade 100644 --- a/include/kcl/kcl_string_helpers.h +++ b/include/kcl/kcl_string_helpers.h @@ -2,7 +2,7 @@ #ifndef AMDKCL_STRING_HELPERS_H #define AMDKCL_STRING_HELPERS_H - +#include /* Copied from v5.17-rc2-224-gea4692c75e1c linux/string_helpers.h */ #ifndef HAVE_STR_YES_NO From 2803c8e9f1f536ddbc94f876816e707f686d82e4 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 2 Mar 2023 17:11:25 +0530 Subject: [PATCH 1036/2653] drm/amdgpu: Use correct mask for legacy pci check For legacy PCI compatibility check, use the mask which was set during gmc init rather than hardcoding to 44 bits width. Signed-off-by: Lijo Lazar Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index c3e5fe3b78d31..821eedaa1cf81 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2252,7 +2252,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) * IGP - can handle 44-bits * PCI - dma32 for legacy pci gart */ - need_dma32 = !!pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(44)); + need_dma32 = !!pci_set_dma_mask(adev->pdev, dma_get_mask(adev->dev)); #else need_dma32 = dma_addressing_limited(adev->dev); #endif From 106680a6f709f9c5a75567ea8b021dab3026deb6 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 21 Apr 2023 15:37:15 +0800 Subject: [PATCH 1037/2653] drm/amdkcl: fake migrate_enable/disable() It's caused by 71c32def3700558ae3ecbb0e8aaea2378651b59c "drm/amd/display: Disable migration to ensure consistency of per-CPU variable" Signed-off-by: Bob Zhou Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 | 16 ++++++++++++++++ include/kcl/kcl_preempt.h | 11 +++++++++++ 4 files changed, 31 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f864d87d135a2..be91c749045c6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -474,6 +474,9 @@ /* drm_fb_helper_alloc_info() is available */ #define HAVE_DRM_FB_HELPER_ALLOC_INFO 1 +/* migrate_disable() is available */ +#define HAVE_MIGRATE_DISABLE 1 + /* drm_fb_helper_fill_info() is available */ #define HAVE_DRM_FB_HELPER_FILL_INFO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7ac69da15aed0..2776f2cabe299 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -146,6 +146,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI AC_AMDGPU_DRM_BITMAP_FUNCS AC_AMDGPU_STRUCT_KOBJ_TYPE + AC_AMDGPU_MIGRATE_DISABLE AC_AMDGPU_CLOSE_FD AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG diff --git a/drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 b/drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 new file mode 100644 index 0000000000000..5ffb95e258143 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.6-rc2-1-g66630058e56b +dnl # sched/rt: Provide migrate_disable/enable() inlines +dnl # +AC_DEFUN([AC_AMDGPU_MIGRATE_DISABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + migrate_disable(); + ],[ + AC_DEFINE(HAVE_MIGRATE_DISABLE, 1, + [migrate_disable() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_preempt.h b/include/kcl/kcl_preempt.h index 1e59cbca1bf73..cc861beb098ae 100644 --- a/include/kcl/kcl_preempt.h +++ b/include/kcl/kcl_preempt.h @@ -53,4 +53,15 @@ (NMI_MASK | HARDIRQ_MASK | SOFTIRQ_OFFSET))) #endif +#ifndef HAVE_MIGRATE_DISABLE +static __always_inline void migrate_disable(void) +{ + preempt_disable(); +} +static __always_inline void migrate_enable(void) +{ + preempt_enable(); +} +#endif /* HAVE_MIGRATE_DISABLE */ + #endif /* AMDKCL_PREEMPT_H */ From a341ed7cc49cf404e4b6550198d9b5c680d1ec9a Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 9 Jul 2024 16:25:06 +0800 Subject: [PATCH 1038/2653] drm/amdkcl: test whether drm_edid_override_connector_update() is available It's caused by 068553e14f869664ca66e63e5200b69db8ae8990 "drm/amd/display: assign edid_blob_ptr with edid from debugfs" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 6 +++++ drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 | 32 ++++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_edid.h | 20 +++++++++++++++ 5 files changed, 60 insertions(+) create mode 100644 include/kcl/backport/kcl_drm_edid.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 98902bf9e06b1..97a361d50c76d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -105,4 +105,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index be91c749045c6..90022931f3e78 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -519,6 +519,12 @@ /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 +/* drm_edid_override_connector_update() is available */ +#define HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE 1 + +/* drm_add_override_edid_modes() is available */ +/* #undef HAVE_DRM_ADD_OVERRIDE_EDID_MODES */ + /* drm_hdmi_avi_infoframe_from_display_mode() has p,p,b interface */ /* #undef HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 index 02a5a8a2b5875..e2a939c448834 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 @@ -33,3 +33,35 @@ AC_DEFUN([AC_AMDGPU_DRM_EDID], [ ]) ]) ]) + +dnl # +dnl # v6.1-rc1-143-g019b93874834 +dnl # drm/edid: rename drm_add_override_edid_modes() to drm_edid_override_connector_update() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_edid_override_connector_update(NULL); + ],[ + AC_DEFINE(HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE, 1, + [drm_edid_override_connector_update() is available]) + ],[ + dnl # + dnl # v5.2-rc2-25-g48eaeb7664c7 + dnl # drm: add fallback override/firmware EDID modes workaround + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_add_override_edid_modes(NULL); + ],[ + AC_DEFINE(HAVE_DRM_ADD_OVERRIDE_EDID_MODES, 1, + [drm_add_override_edid_modes() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2776f2cabe299..985a121c552ab 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -85,6 +85,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_EDID AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER + AC_AMDGPU_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE AC_AMDGPU_DRM_MODE_INIT AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS diff --git a/include/kcl/backport/kcl_drm_edid.h b/include/kcl/backport/kcl_drm_edid.h new file mode 100644 index 0000000000000..2076f6fe8b2b2 --- /dev/null +++ b/include/kcl/backport/kcl_drm_edid.h @@ -0,0 +1,20 @@ +#ifndef AMDKCL_BACKPORT_DRM_EDID_H +#define AMDKCL_BACKPORT_DRM_EDID_H + +#include + +#if !defined(HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE) +#ifdef HAVE_DRM_ADD_OVERRIDE_EDID_MODES +static inline int _kcl_drm_edid_override_connector_update(struct drm_connector *connector) +{ + int ret; + + ret = drm_add_override_edid_modes(connector); + return ret; +} + +#define drm_edid_override_connector_update _kcl_drm_edid_override_connector_update +#endif +#endif + +#endif From ba700c98fcde3ca9d3711683f4b3dfcfed660085 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Sun, 23 Apr 2023 10:56:25 +0800 Subject: [PATCH 1039/2653] drm/amdkcl: wrap code under macro HAVE_AMDKCL_HMM_MIRROR_ENABLED It's caused by 529960ba2a622107c0115345f648de441048e244 "drm/amdkfd: Fix an issue at userptr buffer validation process." Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index e5ef013433e49..0d853f7cc46b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2967,7 +2967,9 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, goto unlock_out; } /* set mem valid if mem has hmm range associated */ +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (mem->range) +#endif mem->invalid = 0; } From 7c4a9f82ec69e4ccad8aec7c3e7b9d1399ae2b5a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Sun, 23 Apr 2023 11:29:55 +0800 Subject: [PATCH 1040/2653] drm/amdkcl: test whether drm_connector->edid_override is available It's caused by 4596e8af5f3d520dcd2edf009aa785ad4cdc50e8 "drm/amd/display: implement force function in amdgpu_dm_connector_funcs" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 | 20 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7b4822be83466..5bf5647d3304c 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7482,6 +7482,7 @@ amdgpu_dm_connector_late_register(struct drm_connector *connector) return 0; } +#ifdef HAVE_DRM_CONNECTOR_EDID_OVERRIDE static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); @@ -7518,6 +7519,7 @@ static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) &dc_em_sink->edid_caps); } } +#endif static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { .reset = amdgpu_dm_connector_funcs_reset, @@ -7530,7 +7532,9 @@ static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { .atomic_get_property = amdgpu_dm_connector_atomic_get_property, .late_register = amdgpu_dm_connector_late_register, .early_unregister = amdgpu_dm_connector_unregister, +#ifdef HAVE_DRM_CONNECTOR_EDID_OVERRIDE .force = amdgpu_dm_connector_funcs_force +#endif }; static int get_modes(struct drm_connector *connector) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 90022931f3e78..33c61997d5446 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -805,6 +805,9 @@ /* memalloc_noreclaim_save() is available */ #define HAVE_MEMALLOC_NORECLAIM_SAVE 1 +/* drm_connector->edid_override is available */ +#define HAVE_DRM_CONNECTOR_EDID_OVERRIDE 1 + /* struct migrate_vma has fault_page */ #define HAVE_MIGRATE_VMA_FAULT_PAGE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 new file mode 100644 index 0000000000000..43fb1565aabc0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # v6.1-rc1-146-g90b575f52c6a +dnl # drm/edid: detach debugfs EDID override from EDID property update +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector *connector = NULL; + connector->edid_override = NULL; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_EDID_OVERRIDE, 1, + [drm_connector->edid_override is available]) + ]) + ]) +]) + + + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 985a121c552ab..e7a96411564cb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -93,6 +93,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS + AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE AC_AMDGPU_DRM_DP_MST_DETECT_PORT AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT From 51f995e7ead1035f0e40a14544629c87b6bcc962 Mon Sep 17 00:00:00 2001 From: tiancyin Date: Wed, 26 Apr 2023 11:45:08 +0800 Subject: [PATCH 1041/2653] drm/amdkcl: fix display dp mst malfunction It's caused by ffac9721939dca3f0ac7bfa90f3dc484b19c2706 "drm/display/dp_mst: Don't open code modeset checks for releasing time slots" Reviewed-by: Flora Cui Signed-off-by: tiancyin --- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 86a0b8c1345e6..b47cff81787f1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -598,7 +598,24 @@ static int dm_dp_mst_atomic_check(struct drm_connector *connector, struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr; struct drm_dp_mst_port *mst_port = aconnector->mst_output_port; +#ifndef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS + struct drm_connector_state *new_conn_state = + drm_atomic_get_new_connector_state(state, connector); + struct drm_connector_state *old_conn_state = + drm_atomic_get_old_connector_state(state, connector); + struct drm_crtc_state *new_crtc_state; + + if (!old_conn_state->crtc) + return 0; + if (new_conn_state->crtc) { + new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); + if (!new_crtc_state || + !drm_atomic_crtc_needs_modeset(new_crtc_state) || + new_crtc_state->enable) + return 0; + } +#endif return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); } #endif From bb50a79b736a0a2023804d4ed5d82f7fb3055a80 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 27 Apr 2023 17:30:43 +0800 Subject: [PATCH 1042/2653] drm/amdkcl: fake macro DEFINE_DEBUGFS_ATTRIBUTE_SIGNED It's caused by 891d215cff04e230777a4b2b8611df31e7b822d2 "drm/amdgpu: add amdgpu_error_* debugfs file" Signed-off-by: Flora Cui Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 6 +- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c | 97 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_debugfs.h | 56 +++++++++++ 5 files changed, 159 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c create mode 100644 include/kcl/kcl_debugfs.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 3048ba9d18233..69b0dce1fa6b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -628,6 +628,7 @@ static const struct file_operations amdgpu_debugfs_mqd_fops = { .llseek = default_llseek }; +#ifdef DEFINE_DEBUGFS_ATTRIBUTE static int amdgpu_debugfs_ring_error(void *data, u64 val) { struct amdgpu_ring *ring = data; @@ -638,7 +639,7 @@ static int amdgpu_debugfs_ring_error(void *data, u64 val) DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(amdgpu_debugfs_error_fops, NULL, amdgpu_debugfs_ring_error, "%lld\n"); - +#endif #endif void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, @@ -666,10 +667,11 @@ void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, ring->mqd_size); } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE sprintf(name, "amdgpu_error_%s", ring->name); debugfs_create_file(name, 0200, root, ring, &amdgpu_debugfs_error_fops); - +#endif #endif } diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index a444ae80f06af..5c0d3f39cf2f1 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -17,7 +17,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o -amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o +amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o kcl_debugfs_file.o amdkcl-$(CONFIG_SYSFS) += kcl_sysfs_emit.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c b/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c new file mode 100644 index 0000000000000..def9db4463a22 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * inode.c - part of debugfs, a tiny little debug file system + * + * Copyright (C) 2004,2019 Greg Kroah-Hartman + * Copyright (C) 2004 IBM Inc. + * Copyright (C) 2019 Linux Foundation + * + * debugfs is for people to use instead of /proc or /sys. + * See ./Documentation/core-api/kernel-api.rst for more details. + */ + +#include +#include +#include + +#ifdef KCL_FAKE_DEBUGFS_ATTRIBUTE_SIGNED +/* Copied from fs/libfs.c */ +struct simple_attr { + int (*get)(void *, u64 *); + int (*set)(void *, u64); + char get_buf[24]; /* enough to store a u64 and "\n\0" */ + char set_buf[24]; + void *data; + const char *fmt; /* format for read operation */ + struct mutex mutex; /* protects access to these buffers */ +}; + +static ssize_t simple_attr_write_xsigned(struct file *file, const char __user *buf, + size_t len, loff_t *ppos, bool is_signed) +{ + struct simple_attr *attr; + unsigned long long val; + size_t size; + ssize_t ret; + + attr = file->private_data; + if (!attr->set) + return -EACCES; + + ret = mutex_lock_interruptible(&attr->mutex); + if (ret) + return ret; + + ret = -EFAULT; + size = min(sizeof(attr->set_buf) - 1, len); + if (copy_from_user(attr->set_buf, buf, size)) + goto out; + + attr->set_buf[size] = '\0'; + if (is_signed) + ret = kstrtoll(attr->set_buf, 0, &val); + else + ret = kstrtoull(attr->set_buf, 0, &val); + if (ret) + goto out; + ret = attr->set(attr->data, val); + if (ret == 0) + ret = len; /* on success, claim we got the whole input */ +out: + mutex_unlock(&attr->mutex); + return ret; +} + +ssize_t simple_attr_write_signed(struct file *file, const char __user *buf, + size_t len, loff_t *ppos) +{ + return simple_attr_write_xsigned(file, buf, len, ppos, true); +} +EXPORT_SYMBOL_GPL(simple_attr_write_signed); + +/* Copied from fs/debugfs/file.c */ +#define F_DENTRY(filp) ((filp)->f_path.dentry) +static ssize_t debugfs_attr_write_xsigned(struct file *file, const char __user *buf, + size_t len, loff_t *ppos, bool is_signed) +{ + struct dentry *dentry = F_DENTRY(file); + ssize_t ret; + + ret = debugfs_file_get(dentry); + if (unlikely(ret)) + return ret; + if (is_signed) + ret = simple_attr_write_signed(file, buf, len, ppos); + else + ret = simple_attr_write(file, buf, len, ppos); + debugfs_file_put(dentry); + return ret; +} + +ssize_t debugfs_attr_write_signed(struct file *file, const char __user *buf, + size_t len, loff_t *ppos) +{ + return debugfs_attr_write_xsigned(file, buf, len, ppos, true); +} +EXPORT_SYMBOL_GPL(debugfs_attr_write_signed); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 97a361d50c76d..40a3fb993aa29 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -106,4 +106,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_debugfs.h b/include/kcl/kcl_debugfs.h new file mode 100644 index 0000000000000..ca6a8d391da78 --- /dev/null +++ b/include/kcl/kcl_debugfs.h @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * debugfs.h - a tiny little debug file system + * + * Copyright (C) 2004 Greg Kroah-Hartman + * Copyright (C) 2004 IBM Inc. + * + * debugfs is for people to use instead of /proc or /sys. + * See Documentation/filesystems/ for more details. + */ + +#ifndef KCL_DEBUGFS_H_ +#define KCL_DEBUGFS_H_ + +#include +#include +#include + +#include +#include + +#if defined(DEFINE_DEBUGFS_ATTRIBUTE) && !defined(DEFINE_DEBUGFS_ATTRIBUTE_SIGNED) +#define KCL_FAKE_DEBUGFS_ATTRIBUTE_SIGNED +#define DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, __is_signed) \ +static int __fops ## _open(struct inode *inode, struct file *file) \ +{ \ + __simple_attr_check_format(__fmt, 0ull); \ + return simple_attr_open(inode, file, __get, __set, __fmt); \ +} \ +static const struct file_operations __fops = { \ + .owner = THIS_MODULE, \ + .open = __fops ## _open, \ + .release = simple_attr_release, \ + .read = debugfs_attr_read, \ + .write = (__is_signed) ? debugfs_attr_write_signed : debugfs_attr_write, \ + .llseek = no_llseek, \ +} + +#define DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(__fops, __get, __set, __fmt) \ + DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, true) + +#if defined(CONFIG_DEBUG_FS) +ssize_t debugfs_attr_write_signed(struct file *file, const char __user *buf, + size_t len, loff_t *ppos); +#else +static inline ssize_t debugfs_attr_write_signed(struct file *file, + const char __user *buf, + size_t len, loff_t *ppos) +{ + return -ENODEV; +} +#endif /* CONFIG_DEBUG_FS */ + +#endif /* DEFINE_DEBUGFS_ATTRIBUTE_SIGNED */ + +#endif From b15ae2f2a6636ac351b69b0b41d55761128f63f2 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 10 May 2023 17:39:34 +0800 Subject: [PATCH 1043/2653] Revert "drm/amdgpu: mark force completed fences with -ECANCELED" This reverts commit 44c41d7de74acbfec110ea28e400e051c1333f0d. This reverted patch causes a modprobe issue. (SWDEV-398339) Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index d5f7c6a739d8c..779415d96e171 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -732,7 +732,6 @@ void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error) */ void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) { - amdgpu_fence_driver_set_error(ring, -ECANCELED); amdgpu_fence_write(ring, ring->fence_drv.sync_seq); amdgpu_fence_process(ring); } From 114271830aa114397a9228d2a6621b827b41e49d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 20 Apr 2023 15:07:57 +0800 Subject: [PATCH 1044/2653] drm/amdkcl: fake kmalloc_size_roundup Signed-off-by: Flora Cui Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 12 +++++ drivers/gpu/drm/amd/amdkcl/kcl_mm_slab.c | 44 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/mm-kmalloc_size_roundup.m4 | 17 +++++++ include/kcl/kcl_slab.h | 4 ++ 7 files changed, 82 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_mm_slab.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 5c0d3f39cf2f1..ac231fe69b8ac 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o + kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index d151a6db046cc..637ecefbb9773 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -30,9 +30,21 @@ void zone_device_page_init(struct page *page) EXPORT_SYMBOL_GPL(zone_device_page_init); #endif +#ifndef HAVE_KMALLOC_SIZE_ROUNDUP +#ifndef CONFIG_SLOB +extern struct kmem_cache *(*_kcl_kmalloc_slab)(size_t size, gfp_t flags); +#endif +#endif /* HAVE_KMALLOC_SIZE_ROUNDUP */ + void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC _kcl_mmput_async = amdkcl_fp_setup("mmput_async", __kcl_mmput_async); #endif + +#ifndef HAVE_KMALLOC_SIZE_ROUNDUP +#ifndef CONFIG_SLOB + _kcl_kmalloc_slab = amdkcl_fp_setup("kmalloc_slab", NULL); +#endif +#endif } diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm_slab.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm_slab.c new file mode 100644 index 0000000000000..3de9dfff5d0df --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm_slab.c @@ -0,0 +1,44 @@ +#include +#include +#include + +#if !defined(HAVE_KMALLOC_SIZE_ROUNDUP) +#ifdef CONFIG_SLOB +/* copy from mm/slob.c */ +size_t kmalloc_size_roundup(size_t size) +{ + /* Short-circuit the 0 size case. */ + if (unlikely(size == 0)) + return 0; + /* Short-circuit saturated "too-large" case. */ + if (unlikely(size == SIZE_MAX)) + return SIZE_MAX; + + return ALIGN(size, ARCH_KMALLOC_MINALIGN); +} + +EXPORT_SYMBOL(kmalloc_size_roundup); +#else +/* copy from mm/slab_common.c and modified for KCL usage. */ +struct kmem_cache *(*_kcl_kmalloc_slab)(size_t size, gfp_t flags); +size_t kmalloc_size_roundup(size_t size) +{ + struct kmem_cache *c; + + /* Short-circuit the 0 size case. */ + if (unlikely(size == 0)) + return 0; + /* Short-circuit saturated "too-large" case. */ + if (unlikely(size == SIZE_MAX)) + return SIZE_MAX; + /* Above the smaller buckets, size is a multiple of page size. */ + if (size > KMALLOC_MAX_CACHE_SIZE) + return PAGE_SIZE << get_order(size); + + /* The flags don't matter since size_index is common to all. */ + c = _kcl_kmalloc_slab(size, GFP_KERNEL); + return c ? kmem_cache_size(c) : 0; +} +EXPORT_SYMBOL(kmalloc_size_roundup); +#endif +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 33c61997d5446..bf7d3b30ca85c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -685,6 +685,9 @@ /* kernel_write() take arg type of position as pointer */ #define HAVE_KERNEL_WRITE_PPOS 1 +/* kmalloc_size_roundup is available */ +#define HAVE_KMALLOC_SIZE_ROUNDUP 1 + /* kmap_local_* is available */ #define HAVE_KMAP_LOCAL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e7a96411564cb..b908923d93b53 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -194,6 +194,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE AC_AMDGPU_RB_ADD_CACHED AC_AMDGPU_APPLE_GMUX_DETECT + AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP AC_AMDGPU_ZONE_DEVICE_PAGE_INIT AC_KERNEL_WAIT diff --git a/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 b/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 new file mode 100644 index 0000000000000..ab6586797229a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.0-rc2-7-g05a940656e1e +dnl # slab: Introduce kmalloc_size_roundup() +dnl # +AC_DEFUN([AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + size_t a, b; + a = kmalloc_size_roundup(b); + ], [ + AC_DEFINE(HAVE_KMALLOC_SIZE_ROUNDUP, 1, + [kmalloc_size_roundup is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_slab.h b/include/kcl/kcl_slab.h index e095f8a46088e..a23a565eab992 100644 --- a/include/kcl/kcl_slab.h +++ b/include/kcl/kcl_slab.h @@ -34,4 +34,8 @@ krealloc_array(void *p, size_t new_n, size_t new_size, gfp_t flags) } #endif +#ifndef HAVE_KMALLOC_SIZE_ROUNDUP +size_t kmalloc_size_roundup(size_t size); +#endif + #endif From a491768080c10d1b3260d9c857cfc198d9fd3851 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 9 May 2023 17:16:23 -0400 Subject: [PATCH 1045/2653] Fix unsteady amdgpu dkms build against 5.x kernels Make rules robust against "Argument list too long" error. SWDEV-397841 Change-Id: Ib7e26359097e275801658c1a865831060b11bc51 Signed-off-by: Slava Grigorev Reviewed-by: Jeremy Newton Reviewed-by: Slava Abramov --- drivers/gpu/drm/amd/dkms/dkms.conf | 2 ++ drivers/gpu/drm/amd/dkms/post-build.sh | 23 +++++++++++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 34 ++++++++++++++++++++++++++ 3 files changed, 59 insertions(+) create mode 100755 drivers/gpu/drm/amd/dkms/post-build.sh diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index bf06588ea6b9c..ec2c979254b55 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -2,6 +2,8 @@ PACKAGE_NAME="amdgpu" PACKAGE_VERSION="1.0" AUTOINSTALL="yes" PRE_BUILD="amd/dkms/pre-build.sh $kernelver" +POST_BUILD="amd/dkms/post-build.sh $kernelver" +POST_REMOVE="amd/dkms/post-build.sh $kernelver" # not all OS supports weak module updates NO_WEAK_MODULES="yes" diff --git a/drivers/gpu/drm/amd/dkms/post-build.sh b/drivers/gpu/drm/amd/dkms/post-build.sh new file mode 100755 index 0000000000000..962903db89aca --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/post-build.sh @@ -0,0 +1,23 @@ +#!/bin/bash + +KERNELVER=$1 + +# +# Restore original kernel 5.x scripts/Makefile.build modified by post-add.sh +# +if [[ ${KERNELVER%%.*} -eq 5 ]]; then + moddir="/lib/modules/$KERNELVER" + mkfile="scripts/Makefile.build" + + if [[ -d "$moddir/source" ]]; then + mkfile="$moddir/source/$mkfile" + else + mkfile="$moddir/build/$mkfile" + fi + + mkfile=$(readlink -f $mkfile) + + if [[ -f "$mkfile~" ]]; then + mv -f $mkfile{~,} + fi +fi diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 3d7f2084cae3e..cdbac6500036c 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -55,6 +55,40 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile done +#!/bin/bash + +KERNELVER=$1 + +# +# Kernel 5.x scripts/Makefile.build patch +# The patch makes rules robust against "Argument list too long" error +# +if [[ ${KERNELVER%%.*} -eq 5 ]]; then + moddir="/lib/modules/$KERNELVER" + mkfile="scripts/Makefile.build" + + if [[ -d "$moddir/source" ]]; then + mkfile="$moddir/source/$mkfile" + else + mkfile="$moddir/build/$mkfile" + fi + + mkfile=$(readlink -e $mkfile) + + if [[ "$?" -eq 0 ]] && [[ ! -f "$mkfile~" ]]; then + cp -a ${mkfile}{,~} + sed -i -e "/^cmd_mod = {/,/} > \$@$/c"` + `"cmd_mod = printf '%s\x5Cn' \$(call real-search, \$*.o, .o, -objs -y -m) | \\\\\n"` + `"\t\$(AWK) '!x[\$\$0]++ { print(\"\$(obj)\/\"\$\$0) }' > \$@" \ + -e "s/^[[:space:]]\+cmd_link_multi-m =.*$/"` + `"cmd_link_multi-m = \\\\\n"` + `"\t\$(file >\$@.in,\$(filter %.o,$^)) \\\\\n"` + `"\t\$(LD) \$(ld_flags) -r -o \$@ @\$@.in; \\\\\n"` + `"\trm -f \$@.in/" \ + $mkfile + fi +fi + export KERNELVER (cd $SRC && ./configure) From 995b11680752d40266ba8a76ead798855e1cc929 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 17 May 2023 15:07:40 +0800 Subject: [PATCH 1046/2653] drm/amdkcl: modify AMDGPU_GFXHUB_0 to AMDGPU_GFXHUB(0) It's caused by 43ca920837c4ec57875b51272fe66421a4d24666 "drm/amdgpu: introduce vmhub definition for multi-partition cases (v3)" Signed-off-by: Bob Zhou Reviewed-by: majun --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index f58291c1fd40b..82c270b3a6946 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -58,7 +58,7 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm * if (!adev->gfx.rlc.funcs->update_spm_vmid) return -EINVAL; - r = amdgpu_vmid_alloc_reserved(adev, vm, AMDGPU_GFXHUB_0); + r = amdgpu_vmid_alloc_reserved(adev, vm, AMDGPU_GFXHUB(0)); if (r) return r; @@ -85,7 +85,7 @@ void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm amdgpu_ring_commit(kiq_ring); spin_unlock(&adev->gfx.kiq[0].ring_lock); - amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB_0); + amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB(0)); /* revert spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) From 26e9ef6e0eefb77509edcb143747a8df65b7957b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 25 May 2023 16:26:31 +0800 Subject: [PATCH 1047/2653] drm/amdkcl: add mem_id_plus1 argument when invoke amdgpu_gem_object_create It's caused by 4a31ec3828d09618e496bbf16c15e05a2eeaf1ed drm/amdgpu: Add memory partition mem_id to amdgpu_bo Due to mem_id_plus1 is added as a parameter, modify the argument when invoke amdgpu_gem_object_create. Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 9e575b54e0fb5..08babd4db37d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -699,6 +699,7 @@ int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data, { struct amdgpu_device *adev = drm_to_adev(dev); struct drm_amdgpu_gem_dgma *args = data; + struct amdgpu_fpriv *fpriv = filp->driver_priv; struct drm_gem_object *gobj; struct amdgpu_bo *abo; dma_addr_t *dma_addr; @@ -710,7 +711,7 @@ int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data, /* create a gem object to contain this object in */ r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_DGMA_IMPORT, 0, - 0, NULL, &gobj); + 0, NULL, &gobj, fpriv->xcp_id + 1); if (r) return r; From 7589204a65fa28e0adb5c5be6abe42666ee6d323 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 18 May 2023 13:38:44 +0800 Subject: [PATCH 1048/2653] drm/amdkcl: wrap code under macro HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE It's caused by 8764cee060df560171cf9ac266fa93366200e209 "drm/amdgpu: support partition drm devices" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index a06f626b30233..5f84e9e7b8574 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3188,8 +3188,11 @@ static struct drm_driver amdgpu_kms_driver = { const struct drm_driver amdgpu_partition_driver = { .driver_features = - DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | - DRIVER_SYNCOBJ_TIMELINE, + DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ +#ifdef HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE + | DRIVER_SYNCOBJ_TIMELINE +#endif /* HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE */ + , .open = amdgpu_driver_open_kms, .postclose = amdgpu_driver_postclose_kms, .ioctls = amdgpu_ioctls_kms, From a0a433ebe2c59a8ca8e71239381dbe5cac0cfcab Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 18 May 2023 13:50:38 +0800 Subject: [PATCH 1049/2653] drm/amdkcl: fake page_to_virt() It's caused by 5a3a28ac173e5dab4f4c3533693bd76596a5ae0e "drm/amdgpu: Allocate GART table in RAM for AMD APU" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- include/kcl/kcl_mm.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 2379879ed9932..a230fc776153a 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -96,4 +96,8 @@ struct vm_area_struct *vma_lookup(struct mm_struct *mm, unsigned long addr) #define VM_ACCESS_FLAGS (VM_READ | VM_WRITE | VM_EXEC) #endif +#ifndef page_to_virt +#define page_to_virt(x) __va(PFN_PHYS(page_to_pfn(x))) +#endif + #endif /* AMDKCL_MM_H */ From 9cd549b2d7fea445bcff38e59c58938b1edfab88 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 18 May 2023 15:27:33 +0800 Subject: [PATCH 1050/2653] drm/amdkcl: use amdkcl_ttm_resv to get resv It's caused by 33403d2365e4710712ac8575dd83bd6df61186c0 "drm/amdgpu: Add memory partition mem_id to amdgpu_bo" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 0d853f7cc46b0..7316c5f5120ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -330,7 +330,7 @@ create_dmamap_sg_bo(struct amdgpu_device *adev, ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, 1, AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE | flags, - ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj, 0); + ttm_bo_type_sg, amdkcl_ttm_resvp(&mem->bo->tbo), &gem_obj, 0); amdgpu_bo_unreserve(mem->bo); From 3ff21b5617155b8e39b821baf4ae63e8238fb15a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 18 May 2023 17:03:33 +0800 Subject: [PATCH 1051/2653] drm/amdkcl: fix non-upstream code for modifing kfd_dev to kfd_node It's caused by b0be1be09f5e15f00125940937bbab98c0dbc59d "drm/amdkfd: Introduce kfd_node struct (v5)" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 6 +++--- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 8 ++++---- drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 8 ++++---- drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 5 +++-- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 +- 9 files changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 7fa4441667eca..31dfaaccd3c09 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2413,7 +2413,7 @@ static int criu_restore_memory_of_gpu_ipc(struct kfd_process_device *pdd, struct kgd_mem **kgd_mem) { uint64_t alloc_handle = MAKE_HANDLE(pdd->user_gpu_id, bo_priv->idr_handle); - struct kfd_dev *dev = pdd->dev; + struct kfd_node *dev = pdd->dev; struct kfd_bo *kfd_bo; int ret, idr_handle; uint64_t offset; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 41b2a353c57d9..5aaa1451982c4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -605,7 +605,7 @@ static int kfd_gws_init(struct kfd_node *node) && kfd->mec2_fw_version < 0x30) || (KFD_GC_VERSION(kfd) >= IP_VERSION(11, 0, 0) && KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0))) - kfd->gws_debug_workaround = true; + node->gws_debug_workaround = true; return ret; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index cbd0d109ea883..3368779e354af 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -174,7 +174,7 @@ void kfd_doorbell_unmap_locked(struct kfd_process_device *pdd) pr_debug("Process %d unmapping doorbell 0x%lx\n", process->pasid, vma->vm_start); - size = kfd_doorbell_process_slice(pdd->dev); + size = kfd_doorbell_process_slice(pdd->dev->kfd); zap_vma_ptes(vma, vma->vm_start, size); pdd->qpd.doorbell_mapped = 0; } @@ -201,7 +201,7 @@ int kfd_doorbell_remap(struct kfd_process_device *pdd) /* Calculate physical address of doorbell */ address = kfd_get_process_doorbells(pdd); vma = pdd->qpd.doorbell_vma; - size = kfd_doorbell_process_slice(pdd->dev); + size = kfd_doorbell_process_slice(pdd->dev->kfd); pr_debug("Process %d remap doorbell 0x%lx\n", process->pasid, vma->vm_start); @@ -251,7 +251,7 @@ int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, " vm_flags == 0x%04lX\n" " size == 0x%04lX\n", process->pasid, (unsigned long long) vma->vm_start, - address, vma->vm_flags, kfd_doorbell_process_slice(dev)); + address, vma->vm_flags, kfd_doorbell_process_slice(dev->kfd)); pdd = kfd_get_process_device_data(dev, process); if (WARN_ON_ONCE(!pdd)) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index 9cb5155809752..ab5769b0fe078 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -130,7 +130,7 @@ int kfd_ipc_init(void) return 0; } -static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, +static int kfd_import_dmabuf_create_kfd_bo(struct kfd_node *dev, struct kfd_process *p, uint32_t gpu_id, struct dma_buf *dmabuf, struct kfd_ipc_obj *ipc_obj, @@ -180,7 +180,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, return r; } -int kfd_ipc_import_dmabuf(struct kfd_dev *dev, +int kfd_ipc_import_dmabuf(struct kfd_node *dev, struct kfd_process *p, uint32_t gpu_id, int dmabuf_fd, uint64_t va_addr, uint64_t *handle, @@ -202,7 +202,7 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *dev, return r; } -int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, +int kfd_ipc_import_handle(struct kfd_node *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, uint64_t *mmap_offset, uint32_t *pflags, bool restore) @@ -253,7 +253,7 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, return r; } -int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, +int kfd_ipc_export_as_handle(struct kfd_node *dev, struct kfd_process *p, uint64_t handle, uint32_t *ipc_handle, uint32_t flags) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h index be0bf2b388194..6e92cce265d9e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -28,7 +28,7 @@ #include /* avoid including kfd_priv.h */ -struct kfd_dev; +struct kfd_node; struct kfd_process; struct kfd_ipc_obj { @@ -39,15 +39,15 @@ struct kfd_ipc_obj { uint32_t flags; }; -int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, +int kfd_ipc_import_handle(struct kfd_node *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, uint64_t *mmap_offset, uint32_t *pflags, bool restore); -int kfd_ipc_import_dmabuf(struct kfd_dev *kfd, struct kfd_process *p, +int kfd_ipc_import_dmabuf(struct kfd_node *kfd, struct kfd_process *p, uint32_t gpu_id, int dmabuf_fd, uint64_t va_addr, uint64_t *handle, uint64_t *mmap_offset); -int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, +int kfd_ipc_export_as_handle(struct kfd_node *dev, struct kfd_process *p, uint64_t handle, uint32_t *ipc_handle, uint32_t flags); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index 09cf783e460d3..50541b1dac44a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -140,7 +140,7 @@ struct amd_mem_context { uint64_t size; unsigned long offset; struct amdgpu_bo *bo; - struct kfd_dev *dev; + struct kfd_node *dev; struct sg_table *pages; struct device *dma_dev; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index cab6a7cadfbf0..67872df8e1446 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -400,7 +400,7 @@ struct kfd_ipc_obj; struct kfd_bo { void *mem; struct interval_tree_node it; - struct kfd_dev *dev; + struct kfd_node *dev; /* page-aligned VA address */ uint64_t cpuva; unsigned int mem_type; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index b1fc5ace4015d..00da1cabcbd45 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -403,7 +403,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev int kfd_rlc_spm(struct kfd_process *p, void *data) { struct kfd_ioctl_spm_args *args = data; - struct kfd_dev *dev; + struct kfd_node *dev; struct kfd_process_device *pdd; dev = kfd_device_by_id(args->gpu_id); @@ -434,9 +434,10 @@ int kfd_rlc_spm(struct kfd_process *p, void *data) return -EINVAL; } -void kgd2kfd_spm_interrupt(struct kfd_dev *dev) +void kgd2kfd_spm_interrupt(struct kfd_dev *kfd) { struct kfd_process_device *pdd; + struct kfd_node *dev = kfd->nodes[0]; uint16_t pasid = dev->spm_pasid; struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 2d561e679770c..f35b7539da007 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1278,7 +1278,7 @@ static void kfd_set_iolink_no_atomics(struct kfd_topology_device *dev, return; /* checkout source dev has atomics support on root. */ - if (dev->gpu && (!dev->gpu->pci_atomic_requested || + if (dev->gpu && (!dev->gpu->kfd->pci_atomic_requested || dev->gpu->adev->asic_type == CHIP_HAWAII)) { link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT | CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT; From 41a2af4b497cde8a2ce526308756ef4f6c92d8ff Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 18 May 2023 17:21:50 +0800 Subject: [PATCH 1052/2653] drm/amdkcl: test whether acpi_dev_get_first_match_dev() is available It's caused by 69262b1d049af914e2adfd8faf4ea5a78c08d908 "drm/amdgpu: Add parsing of acpi xcc objects" Signed-off-by: Bob Zhou Acked-by: Leslie Shi drm/amdkcl: update range of HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV Clear up some HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV to enable mem_partitions feature. By return NULL, fake acpi_dev_get_first_match_dev bypass APU with old kernel. Signed-off-by: Bob Zhou Reviewed-by:Lijo Lazar --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_acpi.h | 8 ++++++++ 4 files changed, 25 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index bf7d3b30ca85c..5a4b71af7ef94 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -317,6 +317,9 @@ /* drm_dp_mst_atomic_wait_for_dependencies() is available */ /* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ +/* acpi_dev_get_first_match_dev() is available */ +#define HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 1 + /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 new file mode 100644 index 0000000000000..f83c2733ac2e1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit: v5.1-rc3-1-g817b4d64da03 +dnl # ACPI / utils: Introduce acpi_dev_get_first_match_dev() helper +dnl # +AC_DEFUN([AC_AMDGPU_ACPI_DEV_GET_FIRST_MATCH_DEV], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([acpi_dev_get_first_match_dev], + [drivers/acpi/utils.c], [ + AC_DEFINE(HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV, 1, + [acpi_dev_get_first_match_dev() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b908923d93b53..93cd5c21a18cc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -105,6 +105,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU_ACPI_PUT_TABLE + AC_AMDGPU_ACPI_DEV_GET_FIRST_MATCH_DEV AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS AC_AMDGPU_DRM_FORMAT_INFO AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE diff --git a/include/kcl/kcl_acpi.h b/include/kcl/kcl_acpi.h index d6f499640f0b8..4ad8d53bf3cec 100644 --- a/include/kcl/kcl_acpi.h +++ b/include/kcl/kcl_acpi.h @@ -23,4 +23,12 @@ #define ACPI_HANDLE(dev) DEVICE_ACPI_HANDLE(dev) #endif +#ifndef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV +static inline struct acpi_device * +acpi_dev_get_first_match_dev(const char *hid, const char *uid, s64 hrv) +{ + return NULL; +} +#endif + #endif /* AMDKCL_ACPI_H */ From 411dfdeab0d7787b49c17918b2e3f67eed820a0c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 30 May 2023 16:28:19 +0800 Subject: [PATCH 1053/2653] drm/amdkcl: amdxcp module add kcl support It's caused by 7dd353a7623ec9a10f9bfde53b19982f760995a2 "drm/amdxcp: add platform device driver for amdxcp" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdxcp/Makefile | 3 + drivers/gpu/drm/amd/amdxcp/backport/Makefile | 10 +++ .../gpu/drm/amd/amdxcp/backport/backport.h | 1 + .../backport/include/kcl/kcl_amdgpu_drm_drv.h | 42 +++++++++ .../gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c | 85 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/Makefile | 2 +- drivers/gpu/drm/amd/dkms/dkms.conf | 4 + 7 files changed, 146 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdxcp/backport/Makefile create mode 100644 drivers/gpu/drm/amd/amdxcp/backport/backport.h create mode 100644 drivers/gpu/drm/amd/amdxcp/backport/include/kcl/kcl_amdgpu_drm_drv.h create mode 100644 drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c diff --git a/drivers/gpu/drm/amd/amdxcp/Makefile b/drivers/gpu/drm/amd/amdxcp/Makefile index 870501a4bb8c0..5790475464f02 100644 --- a/drivers/gpu/drm/amd/amdxcp/Makefile +++ b/drivers/gpu/drm/amd/amdxcp/Makefile @@ -23,3 +23,6 @@ amdxcp-y := amdgpu_xcp_drv.o obj-$(CONFIG_DRM_AMDGPU) += amdxcp.o + +AMD_XCP_PATH := $(src) +include $(AMD_XCP_PATH)/backport/Makefile diff --git a/drivers/gpu/drm/amd/amdxcp/backport/Makefile b/drivers/gpu/drm/amd/amdxcp/backport/Makefile new file mode 100644 index 0000000000000..4217ff962b225 --- /dev/null +++ b/drivers/gpu/drm/amd/amdxcp/backport/Makefile @@ -0,0 +1,10 @@ +BACKPORT_OBJS := kcl_drm_drv.o + +amdxcp-y += $(addprefix ./backport/,$(BACKPORT_OBJS)) + +ccflags-y += \ + -I$(AMD_XCP_PATH)/ \ + -I$(AMD_XCP_PATH)/backport/include \ + -I$(AMD_XCP_PATH)/../dkms \ + -include config/config.h \ + -include backport/backport.h diff --git a/drivers/gpu/drm/amd/amdxcp/backport/backport.h b/drivers/gpu/drm/amd/amdxcp/backport/backport.h new file mode 100644 index 0000000000000..155f55d669456 --- /dev/null +++ b/drivers/gpu/drm/amd/amdxcp/backport/backport.h @@ -0,0 +1 @@ +#include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/drivers/gpu/drm/amd/amdxcp/backport/include/kcl/kcl_amdgpu_drm_drv.h b/drivers/gpu/drm/amd/amdxcp/backport/include/kcl/kcl_amdgpu_drm_drv.h new file mode 100644 index 0000000000000..c331d7f60606b --- /dev/null +++ b/drivers/gpu/drm/amd/amdxcp/backport/include/kcl/kcl_amdgpu_drm_drv.h @@ -0,0 +1,42 @@ +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * Copyright 2016 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDXCP_BACKPORT_KCL_DRM_DRV_H__ +#define __AMDXCP_BACKPORT_KCL_DRM_DRV_H__ + +#include + +/* Copied from v5.7-rc1-343-gb0b5849e0cc0 include/drm/drm_drv.h */ +#ifndef devm_drm_dev_alloc +#define AMDKCL_DEVM_DRM_DEV_ALLOC 1 +void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, + size_t size, size_t offset); +#define devm_drm_dev_alloc(parent, driver, type, member) \ + ((type *) __devm_drm_dev_alloc(parent, driver, sizeof(type), \ + offsetof(type, member))) + +#endif + +#endif diff --git a/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c b/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c new file mode 100644 index 0000000000000..4b2d043f4665a --- /dev/null +++ b/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c @@ -0,0 +1,85 @@ +/* + * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org + * + * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Author Rickard E. (Rik) Faith + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include + +#ifdef AMDKCL_DEVM_DRM_DEV_ALLOC +static void devm_drm_dev_init_release(void *data) +{ + drm_dev_put(data); + +#ifndef HAVE_DRM_DRM_MANAGED_H + if(data){ + struct drm_device *dev = data; + if(!kref_read(&dev->ref)) + kfree(dev->dev_private); + } +#endif +} +/* Copied from v5.7-rc1-343-gb0b5849e0cc0 drivers/gpu/drm/drm_drv.c and modified for KCL */ +static int devm_drm_dev_init(struct device *parent, + struct drm_device *dev, + const struct drm_driver *driver) +{ + int ret; + + ret = drm_dev_init(dev, driver, parent); + if (ret) + return ret; + + return devm_add_action_or_reset(parent, + devm_drm_dev_init_release, dev); +} + +void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, + size_t size, size_t offset) +{ + void *container; + struct drm_device *drm; + int ret; + + container = kzalloc(size, GFP_KERNEL); + if (!container) + return ERR_PTR(-ENOMEM); + + drm = container + offset; + ret = devm_drm_dev_init(parent, drm, driver); + if (ret) { + kfree(container); + return ERR_PTR(ret); + } +#ifdef HAVE_DRM_DRM_MANAGED_H + drmm_add_final_kfree(drm, container); +#else + drm->dev_private = container; +#endif + return container; +} + +#endif diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 0c7477083f0ec..39facc822b351 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -223,4 +223,4 @@ include $(src)/amd/dkms/Makefile.drm_ttm_helper include $(src)/amd/dkms/Makefile.drm_buddy -obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ +obj-m += scheduler/ amd/amdgpu/ amd/amdxcp/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index ec2c979254b55..78cc07704d491 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -34,6 +34,10 @@ BUILT_MODULE_NAME[5]="amddrm_buddy" BUILT_MODULE_LOCATION[5]="." DEST_MODULE_LOCATION[5]="/kernel/drivers/gpu/drm" +BUILT_MODULE_NAME[6]="amdxcp" +BUILT_MODULE_LOCATION[6]="amd/amdxcp" +DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm/amd/amdxcp" + MAKE[0]="make TTM_NAME=${BUILT_MODULE_NAME[1]} \ SCHED_NAME=${BUILT_MODULE_NAME[3]} \ -C $kernel_source_dir \ From e7f1910ea4a38bfdf24d2fe59d0ec9d644fc1c7b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 5 Jun 2023 13:51:23 +0800 Subject: [PATCH 1054/2653] drm/amdkcl: fake macro DECLARE_FLEX_ARRAY It's caused by 46ca366ec5b07937357d6c0aaecf706b3b762abd "drm/amdgpu/discovery: Replace fake flex-arrays with flexible-array members" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- include/kcl/kcl_stddef.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/kcl/kcl_stddef.h b/include/kcl/kcl_stddef.h index dc455e1423ab1..2656ab3239f48 100644 --- a/include/kcl/kcl_stddef.h +++ b/include/kcl/kcl_stddef.h @@ -13,4 +13,22 @@ #define sizeof_field(TYPE, MEMBER) sizeof((((TYPE *)0)->MEMBER)) #endif +#ifndef DECLARE_FLEX_ARRAY +/** + * DECLARE_FLEX_ARRAY() - Declare a flexible array usable in a union + * + * @TYPE: The type of each flexible array element + * @NAME: The name of the flexible array member + * + * In order to have a flexible array member in a union or alone in a + * struct, it needs to be wrapped in an anonymous struct with at least 1 + * named member, but that member can be empty. + */ +#define DECLARE_FLEX_ARRAY(TYPE, NAME) \ + struct { \ + struct { } __empty_ ## NAME; \ + TYPE NAME[]; \ + } +#endif + #endif From a6bdf173490b260b7ab3ef9fa0630ef3abf263e8 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 7 Jun 2023 14:13:26 +0800 Subject: [PATCH 1055/2653] drm/amdkcl: check whether drm_gem_object->resv is available It's caused by c7cc29bdccb3ba26fe4de78df70c4c9c8a279af8 "drm/amdgpu: Add a low priority scheduler for VRAM clearing" Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index c7289071dadfa..6a53b1fd15fd3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -740,7 +740,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev, bo->tbo.resource->mem_type == TTM_PL_VRAM) { struct dma_fence *fence; - r = amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, &fence); + r = amdgpu_ttm_clear_buffer(bo, amdkcl_ttm_resvp(&bo->tbo), &fence); if (unlikely(r)) goto fail_unreserve; @@ -1351,12 +1351,12 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) if (r) goto out; - r = amdgpu_fill_buffer(abo, 0, &bo->base._resv, &fence, true); + r = amdgpu_fill_buffer(abo, 0, &amdkcl_ttm_resv(bo), &fence, true); if (WARN_ON(r)) goto out; amdgpu_vram_mgr_set_cleared(bo->resource); - dma_resv_add_fence(&bo->base._resv, fence, DMA_RESV_USAGE_KERNEL); + dma_resv_add_fence(&amdkcl_ttm_resv(bo), fence, DMA_RESV_USAGE_KERNEL); dma_fence_put(fence); out: From d36683eb2b7c5e7e560398ff002b9ee32d82efa0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 1 Aug 2023 17:10:04 +0800 Subject: [PATCH 1056/2653] drm/amdkcl: kcl-cleanup for_each_{old/new/oldnew}_{plane/connector/crtc}_in_state Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 31 ------------------- 2 files changed, 35 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5bf5647d3304c..d77cc41828733 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12211,11 +12211,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; } -#if !defined(for_each_new_crtc_in_state) - for_each_crtc_in_state(state, crtc, new_crtc_state, i) { -#else for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { -#endif dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); if (dm_new_crtc_state->mpo_requested) drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 5a3d99c944f10..30d25f7037ddf 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -223,31 +223,6 @@ struct amdgpu_dm_backlight_caps { struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; }; -/** - * for_each_oldnew_plane_in_state_reverse - iterate over all planes in an atomic - * update in reverse order - * @__state: &struct drm_atomic_state pointer - * @plane: &struct drm_plane iteration cursor - * @old_plane_state: &struct drm_plane_state iteration cursor for the old state - * @new_plane_state: &struct drm_plane_state iteration cursor for the new state - * @__i: int iteration cursor, for macro-internal use - * - * This iterates over all planes in an atomic update in reverse order, - * tracking both old and new state. This is useful in places where the - * state delta needs to be considered, for example in atomic check functions. - */ -#if !defined(for_each_oldnew_plane_in_state_reverse) && \ - defined(for_each_oldnew_plane_in_state) -#define for_each_oldnew_plane_in_state_reverse(__state, plane, old_plane_state, new_plane_state, __i) \ - for ((__i) = ((__state)->dev->mode_config.num_total_plane - 1); \ - (__i) >= 0; \ - (__i)--) \ - for_each_if ((__state)->planes[__i].ptr && \ - ((plane) = (__state)->planes[__i].ptr, \ - (old_plane_state) = (__state)->planes[__i].old_state,\ - (new_plane_state) = (__state)->planes[__i].new_state, 1)) -#endif - /** * struct dal_allocation - Tracks mapped FB memory for SMU communication * @list: list of dal allocations @@ -262,7 +237,6 @@ struct dal_allocation { u64 gpu_addr; }; - /** * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq * offload work @@ -1097,12 +1071,7 @@ int dm_atomic_get_state(struct drm_atomic_state *state, struct drm_connector * amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, -#ifndef for_each_new_connector_in_state - struct drm_crtc *crtc, - bool from_state_var); -#else struct drm_crtc *crtc); -#endif int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); From 0746c97b3c1d892239156888cf42107417bb81f0 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 7 Jun 2023 18:46:51 +0800 Subject: [PATCH 1057/2653] drm/amdkcl: Optimize the interrupt the process function Fake the generic_handle_domain_irq function to optimize the irq process function Signed-off-by: Ma Jun Reviewed-by: Flora.Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 5 ---- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_irqdesc.c | 38 ++++++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_irqdesc.h | 11 +++++++ 5 files changed, 52 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_irqdesc.c create mode 100644 include/kcl/kcl_irqdesc.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 2e0c6b43e2799..bd5c3b4666888 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -477,12 +477,7 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev, } else if (((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) || (client_id == SOC15_IH_CLIENTID_ISP)) && adev->irq.virq[src_id]) { -#ifdef HAVE_GENERIC_HANDLE_DOMAIN_IRQ generic_handle_domain_irq(adev->irq.domain, src_id); -#else - generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id)); -#endif - } else if (!adev->irq.client[client_id].sources) { dev_dbg(adev->dev, "Unregistered interrupt client_id: %d src_id: %d\n", diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index ac231fe69b8ac..08b2e37192c57 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o + kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ + kcl_irqdesc.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_irqdesc.c b/drivers/gpu/drm/amd/amdkcl/kcl_irqdesc.c new file mode 100644 index 0000000000000..e53a60dbb71f0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_irqdesc.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar + * Copyright (C) 2005-2006, Thomas Gleixner, Russell King + * + * This file contains the interrupt descriptor management code. Detailed + * information is available in Documentation/core-api/genericirq.rst + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +/** + * generic_handle_irq - Invoke the handler for a particular irq + * @irq: The irq number to handle + * + * Returns: 0 on success, or -EINVAL if conversion has failed + * + * This function must be called from an IRQ context with irq regs + * initialized. + */ +#ifndef HAVE_GENERIC_HANDLE_DOMAIN_IRQ +int kcl_generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwirq) +{ + int irq; + irq = irq_find_mapping(domain, hwirq); + + return generic_handle_irq(irq); +} +EXPORT_SYMBOL_GPL(kcl_generic_handle_domain_irq); +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 40a3fb993aa29..259c928e8a2f5 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -107,4 +107,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_irqdesc.h b/include/kcl/kcl_irqdesc.h new file mode 100644 index 0000000000000..1e439ea146d7c --- /dev/null +++ b/include/kcl/kcl_irqdesc.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMDKCL_IRQDESC_H +#define AMDKCL_IRQDESC_H + +#ifndef HAVE_GENERIC_HANDLE_DOMAIN_IRQ +int kcl_generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwirq); +#define generic_handle_domain_irq kcl_generic_handle_domain_irq +#endif /* HAVE_GENERIC_HANDLE_DOMAIN_IRQ */ + +#endif From ea669df501c079d80be1826c0b33c73dad8ced2f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 29 May 2023 16:08:12 +0800 Subject: [PATCH 1058/2653] drm/amdkcl:drop redundant sched job cleanup It's caused by e9cc9cd75f2ce58751619436133cf44617268060 "drm/amdgpu: drop redundant sched job cleanup when cs is aborted" Signed-off-by: Asher Song Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index caaafb89f980e..4c27e8dc1aaea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1480,7 +1480,8 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) { r = -ERESTARTSYS; - goto error_unlock; + amdgpu_mn_unlock(p->mn); + return r; } } #endif From b306cbd50a3b365dfae01105da0d996d4d473fb8 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 9 Jun 2023 15:13:26 +0800 Subject: [PATCH 1059/2653] drm/amdkcl: fake macro PCI_CLASS_ACCELERATOR_PROCESSING It's caused by 186e61eda3749bf2ec669f73fa7c10bdf049a7ce "drm/amdgpu: add the accelerator PCIe class" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_pci_ids.h | 10 ++++++++++ 2 files changed, 11 insertions(+) create mode 100644 include/kcl/kcl_pci_ids.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 259c928e8a2f5..e69fb1878b8b7 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -108,4 +108,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_pci_ids.h b/include/kcl/kcl_pci_ids.h new file mode 100644 index 0000000000000..e56bf58438f5b --- /dev/null +++ b/include/kcl/kcl_pci_ids.h @@ -0,0 +1,10 @@ +#ifndef AMDKCL_PCI_IDS_H +#define AMDKCL_PCI_IDS_H + +#include + +#ifndef PCI_CLASS_ACCELERATOR_PROCESSING +#define PCI_CLASS_ACCELERATOR_PROCESSING 0x1200 +#endif + +#endif \ No newline at end of file From 8e08ab6485dbabace8c93620542991ac31f6f84b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 9 Jun 2023 13:39:20 +0800 Subject: [PATCH 1060/2653] drm/amdkcl: fake drm_mode_create_colorspace_property functions It's cauesd by a9fa9b21c98f7ebeb76897c1f9c6796508aed5a5 "drm/amd/display: Register Colorspace property for DP and HDMI" Signed-off-by: Bob Zhou --- .../gpu/drm/amd/amdkcl/kcl_drm_connector.c | 163 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 9 + ...rm_mode_create_hdmi_colorspace_property.m4 | 49 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 50 ++++++ 5 files changed, 272 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index a4a4e8d2e9acf..559b2610f2966 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -89,3 +89,166 @@ int _kcl_drm_connector_set_panel_orientation_with_quirk( } EXPORT_SYMBOL(_kcl_drm_connector_set_panel_orientation_with_quirk); #endif + +#ifndef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY +struct drm_property *prop = NULL; +int _kcl_drm_connector_attach_colorspace_property(struct drm_connector *connector) +{ + if(prop) + drm_object_attach_property(&connector->base, prop, DRM_MODE_COLORIMETRY_DEFAULT); + + return 0; +} +EXPORT_SYMBOL(_kcl_drm_connector_attach_colorspace_property); +#endif + +#ifdef KCL_DRM_MODE_CREATE_COLORSPACE_PROPERTY +/* copy from drivers/gpu/drm/drm_connector.c (v6.1-5788-gac3470b13f0d) */ +static const char * const colorspace_names[] = { + /* For Default case, driver will set the colorspace */ + [DRM_MODE_COLORIMETRY_DEFAULT] = "Default", + /* Standard Definition Colorimetry based on CEA 861 */ + [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = "SMPTE_170M_YCC", + [DRM_MODE_COLORIMETRY_BT709_YCC] = "BT709_YCC", + /* Standard Definition Colorimetry based on IEC 61966-2-4 */ + [DRM_MODE_COLORIMETRY_XVYCC_601] = "XVYCC_601", + /* High Definition Colorimetry based on IEC 61966-2-4 */ + [DRM_MODE_COLORIMETRY_XVYCC_709] = "XVYCC_709", + /* Colorimetry based on IEC 61966-2-1/Amendment 1 */ + [DRM_MODE_COLORIMETRY_SYCC_601] = "SYCC_601", + /* Colorimetry based on IEC 61966-2-5 [33] */ + [DRM_MODE_COLORIMETRY_OPYCC_601] = "opYCC_601", + /* Colorimetry based on IEC 61966-2-5 */ + [DRM_MODE_COLORIMETRY_OPRGB] = "opRGB", + /* Colorimetry based on ITU-R BT.2020 */ + [DRM_MODE_COLORIMETRY_BT2020_CYCC] = "BT2020_CYCC", + /* Colorimetry based on ITU-R BT.2020 */ + [DRM_MODE_COLORIMETRY_BT2020_RGB] = "BT2020_RGB", + /* Colorimetry based on ITU-R BT.2020 */ + [DRM_MODE_COLORIMETRY_BT2020_YCC] = "BT2020_YCC", + /* Added as part of Additional Colorimetry Extension in 861.G */ + [DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65] = "DCI-P3_RGB_D65", + [DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER] = "DCI-P3_RGB_Theater", + [DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED] = "RGB_WIDE_FIXED", + /* Colorimetry based on scRGB (IEC 61966-2-2) */ + [DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT] = "RGB_WIDE_FLOAT", + [DRM_MODE_COLORIMETRY_BT601_YCC] = "BT601_YCC", +}; + +static const u32 hdmi_colorspaces = + BIT(DRM_MODE_COLORIMETRY_SMPTE_170M_YCC) | + BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | + BIT(DRM_MODE_COLORIMETRY_XVYCC_601) | + BIT(DRM_MODE_COLORIMETRY_XVYCC_709) | + BIT(DRM_MODE_COLORIMETRY_SYCC_601) | + BIT(DRM_MODE_COLORIMETRY_OPYCC_601) | + BIT(DRM_MODE_COLORIMETRY_OPRGB) | + BIT(DRM_MODE_COLORIMETRY_BT2020_CYCC) | + BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | + BIT(DRM_MODE_COLORIMETRY_BT2020_YCC) | + BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65) | + BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER); + +static const u32 dp_colorspaces = + BIT(DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED) | + BIT(DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT) | + BIT(DRM_MODE_COLORIMETRY_OPRGB) | + BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65) | + BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | + BIT(DRM_MODE_COLORIMETRY_BT601_YCC) | + BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | + BIT(DRM_MODE_COLORIMETRY_XVYCC_601) | + BIT(DRM_MODE_COLORIMETRY_XVYCC_709) | + BIT(DRM_MODE_COLORIMETRY_SYCC_601) | + BIT(DRM_MODE_COLORIMETRY_OPYCC_601) | + BIT(DRM_MODE_COLORIMETRY_BT2020_CYCC) | + BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); + +static int drm_mode_create_colorspace_property(struct drm_connector *connector, + u32 supported_colorspaces) +{ + struct drm_device *dev = connector->dev; + u32 colorspaces = supported_colorspaces | BIT(DRM_MODE_COLORIMETRY_DEFAULT); + struct drm_prop_enum_list enum_list[DRM_MODE_COLORIMETRY_COUNT]; + int i, len; + +#ifdef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY + if (connector->colorspace_property) +#else + if (prop) +#endif + return 0; + + + if (!supported_colorspaces) { + drm_err(dev, "No supported colorspaces provded on [CONNECTOR:%d:%s]\n", + connector->base.id, connector->name); + return -EINVAL; + } + + if ((supported_colorspaces & -BIT(DRM_MODE_COLORIMETRY_COUNT)) != 0) { + drm_err(dev, "Unknown colorspace provded on [CONNECTOR:%d:%s]\n", + connector->base.id, connector->name); + return -EINVAL; + } + + len = 0; + for (i = 0; i < DRM_MODE_COLORIMETRY_COUNT; i++) { + if ((colorspaces & BIT(i)) == 0) + continue; + + enum_list[len].type = i; + enum_list[len].name = colorspace_names[i]; + len++; + } +#ifdef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY + connector->colorspace_property = +#else + prop = +#endif + drm_property_create_enum(dev, DRM_MODE_PROP_ENUM, "Colorspace", + enum_list, + len); + +#ifdef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY + if (!connector->colorspace_property) +#else + if (!prop) +#endif + return -ENOMEM; + + return 0; +} +#endif /* KCL_DRM_MODE_CREATE_COLORSPACE_PROPERTY */ + +#ifndef HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS +int _kcl_drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector, + u32 supported_colorspaces) +{ + u32 colorspaces; + + if (supported_colorspaces) + colorspaces = supported_colorspaces & hdmi_colorspaces; + else + colorspaces = hdmi_colorspaces; + + return drm_mode_create_colorspace_property(connector, colorspaces); +} +EXPORT_SYMBOL(_kcl_drm_mode_create_hdmi_colorspace_property); +#endif + +#ifndef HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS +int _kcl_drm_mode_create_dp_colorspace_property(struct drm_connector *connector, + u32 supported_colorspaces) +{ + u32 colorspaces; + + if (supported_colorspaces) + colorspaces = supported_colorspaces & dp_colorspaces; + else + colorspaces = dp_colorspaces; + + return drm_mode_create_colorspace_property(connector, colorspaces); +} +EXPORT_SYMBOL(_kcl_drm_mode_create_dp_colorspace_property); +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5a4b71af7ef94..ede397b0a6612 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -464,6 +464,15 @@ /* drm_dsc_compute_rc_parameters() is available */ #define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 +/* drm_connector_attach_colorspace_property() is available */ +#define HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY 1 + +/* drm_mode_create_hdmi_colorspace_property() has 2 args */ +#define HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS 1 + +/* drm_mode_create_dp_colorspace_property() has 2 args */ +#define HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS 1 + /* struct drm_dsc_config has member simple_422 */ #define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 new file mode 100644 index 0000000000000..7a8fe049ac51b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 @@ -0,0 +1,49 @@ +dnl # +dnl # commit v5.3-rc1-675-g8806cd3aa025 +dnl # drm: Rename HDMI colorspace property creation function +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_connector_attach_colorspace_property], [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY, 1, + [drm_connector_attach_colorspace_property() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v6.1-5783-g08383039cd19 +dnl # drm/connector: Allow drivers to pass list of supported colorspaces +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_mode_create_hdmi_colorspace_property(NULL, 0); + ], [drm_mode_create_hdmi_colorspace_property], [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS, 1, + [drm_mode_create_hdmi_colorspace_property() has 2 args]) + ]) +]) + +dnl # +dnl # commit v6.1-5783-g08383039cd19 +dnl # drm/connector: Allow drivers to pass list of supported colorspaces +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_mode_create_dp_colorspace_property(NULL, 0); + ], [drm_mode_create_dp_colorspace_property], [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS, 1, + [drm_mode_create_dp_colorspace_property() has 2 args]) + ]) +]) + + +AC_DEFUN([AC_AMDGPU_DRM_MODE_CREATE_COLORSPACE_PROPERTY_FUNCS], [ + AC_AMDGPU_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY + AC_AMDGPU_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY + AC_AMDGPU_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 93cd5c21a18cc..7d456d6b0431d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -103,6 +103,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MODE_CONFIG AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION + AC_AMDGPU_DRM_MODE_CREATE_COLORSPACE_PROPERTY_FUNCS AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU_ACPI_PUT_TABLE AC_AMDGPU_ACPI_DEV_GET_FIRST_MATCH_DEV diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index ee8d72d7a4d72..9e95e282f458a 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -25,6 +25,7 @@ #include #include #include +#include /* * commit v4.9-rc4-949-g949f08862d66 @@ -108,6 +109,29 @@ int drm_connector_set_panel_orientation_with_quirk( } #endif +#ifndef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY +int _kcl_drm_connector_attach_colorspace_property(struct drm_connector *connector); +#define drm_connector_attach_colorspace_property _kcl_drm_connector_attach_colorspace_property +#endif /* HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY */ + +#ifndef HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS +#define KCL_DRM_MODE_CREATE_COLORSPACE_PROPERTY +int _kcl_drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector, + u32 supported_colorspaces); +#define drm_mode_create_hdmi_colorspace_property _kcl_drm_mode_create_hdmi_colorspace_property +#endif /* HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS */ + +#ifndef HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS +#define KCL_DRM_MODE_CREATE_COLORSPACE_PROPERTY +int _kcl_drm_mode_create_dp_colorspace_property(struct drm_connector *connector, + u32 supported_colorspaces); +#define drm_mode_create_dp_colorspace_property _kcl_drm_mode_create_dp_colorspace_property +#endif /* HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS */ + +#ifdef KCL_DRM_MODE_CREATE_COLORSPACE_PROPERTY +#define DRM_MODE_COLORIMETRY_COUNT 16 +#endif + #ifndef DRM_COLOR_FORMAT_YCBCR444 #define DRM_COLOR_FORMAT_YCBCR444 (1<<1) #endif @@ -120,4 +144,30 @@ int drm_connector_set_panel_orientation_with_quirk( #define DRM_COLOR_FORMAT_YCBCR420 (1<<3) #endif +/* For Default case, driver will set the colorspace */ +#ifndef DRM_MODE_COLORIMETRY_DEFAULT +/* For Default case, driver will set the colorspace */ +#define DRM_MODE_COLORIMETRY_DEFAULT 0 +/* CEA 861 Normal Colorimetry options */ +#define DRM_MODE_COLORIMETRY_NO_DATA 0 +#define DRM_MODE_COLORIMETRY_SMPTE_170M_YCC 1 +#define DRM_MODE_COLORIMETRY_BT709_YCC 2 +/* CEA 861 Extended Colorimetry Options */ +#define DRM_MODE_COLORIMETRY_XVYCC_601 3 +#define DRM_MODE_COLORIMETRY_XVYCC_709 4 +#define DRM_MODE_COLORIMETRY_SYCC_601 5 +#define DRM_MODE_COLORIMETRY_OPYCC_601 6 +#define DRM_MODE_COLORIMETRY_OPRGB 7 +#define DRM_MODE_COLORIMETRY_BT2020_CYCC 8 +#define DRM_MODE_COLORIMETRY_BT2020_RGB 9 +#define DRM_MODE_COLORIMETRY_BT2020_YCC 10 +/* Additional Colorimetry extension added as part of CTA 861.G */ +#define DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65 11 +#define DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER 12 +/* Additional Colorimetry Options added for DP 1.4a VSC Colorimetry Format */ +#define DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED 13 +#define DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT 14 +#define DRM_MODE_COLORIMETRY_BT601_YCC 15 +#endif /* DRM_MODE_COLORIMETRY_DEFAULT */ + #endif /* AMDKCL_DRM_CONNECTOR_H */ From 345ae53a2b1d0d97ee122c529c166d68223a99fe Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 Jun 2023 15:44:45 +0800 Subject: [PATCH 1061/2653] drm/amdkcl: fix non-upsteam code for amdgpu_vmid_alloc/free_reserved() It's caused by b43f292541814d06ee154d16cd0eae0d80a81ab6 "drm/amdgpu: add option params to enforce process isolation between graphics and compute" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index 82c270b3a6946..0d1007d6f146b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -58,9 +58,12 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm * if (!adev->gfx.rlc.funcs->update_spm_vmid) return -EINVAL; - r = amdgpu_vmid_alloc_reserved(adev, vm, AMDGPU_GFXHUB(0)); + if (!vm->reserved_vmid[AMDGPU_GFXHUB(0)]) { + r = amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0)); if (r) return r; + vm->reserved_vmid[AMDGPU_GFXHUB(0)] = true; + } /* init spm vmid with 0x0 */ adev->gfx.rlc.funcs->update_spm_vmid(adev, 0); @@ -85,7 +88,10 @@ void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm amdgpu_ring_commit(kiq_ring); spin_unlock(&adev->gfx.kiq[0].ring_lock); - amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB(0)); + if (vm->reserved_vmid[AMDGPU_GFXHUB(0)]) { + amdgpu_vmid_free_reserved(adev,AMDGPU_GFXHUB(0)); + vm->reserved_vmid[AMDGPU_GFXHUB(0)] = false; + } /* revert spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) From 8ec0e180df356ce6924033d3d97317a4202ede78 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 14 Jun 2023 19:21:19 +0800 Subject: [PATCH 1062/2653] Revert "Revert "drm/amdgpu: remove TOPDOWN flags when allocating VRAM" This reverts commit a56a0c9058b69133897ad4b54c1e76b2efc8fe5b. This patch causes a jira issue: SWDEV-405451 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 6a53b1fd15fd3..1ba8c2fe7c6fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -153,7 +153,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) places[c].lpfn = min_not_zero(places[c].lpfn, visible_pfn); - else + else if (adev->gmc.real_vram_size != adev->gmc.visible_vram_size) places[c].flags |= TTM_PL_FLAG_TOPDOWN; if (abo->tbo.type == ttm_bo_type_kernel && From d2c47bc2743a69733c16891adccc91b01979193b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 19 Jun 2023 12:25:00 +0800 Subject: [PATCH 1063/2653] drm/amdkcl: wrap code under macro HAVE_PCI_DRIVER_DEV_GROUPS It's caused by 93ca881fcda746abc14b5c5794b456d4a9977977 "drm/amdgpu: Add vbios attribute only if supported" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 12f52c42da34c..ab48a0f960f6b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -1828,7 +1828,6 @@ static struct attribute *amdgpu_vbios_version_attrs[] = { const struct attribute_group amdgpu_vbios_version_attr_group = { .attrs = amdgpu_vbios_version_attrs }; -#endif int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev) { @@ -1838,6 +1837,7 @@ int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev) return 0; } +#endif /** * amdgpu_atombios_fini - free the driver info and callbacks for atombios diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h index 867bc5c5ce67d..ae32b280273aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h @@ -215,6 +215,8 @@ int amdgpu_atombios_get_data_table(struct amdgpu_device *adev, void amdgpu_atombios_fini(struct amdgpu_device *adev); int amdgpu_atombios_init(struct amdgpu_device *adev); +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev); +#endif #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index acc505e2c1a23..6695bb19f0236 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4783,10 +4783,12 @@ int amdgpu_device_init(struct amdgpu_device *adev, * operations performed in `late_init` might affect the sysfs * interfaces creating. */ +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS r = amdgpu_atombios_sysfs_init(adev); if (r) drm_err(&adev->ddev, "registering atombios sysfs failed (%d).\n", r); +#endif r = amdgpu_pm_sysfs_init(adev); if (r) From a28c0f12f46d2da1319006b4cce6c1903b1870c3 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 19 Jun 2023 13:25:52 +0800 Subject: [PATCH 1064/2653] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE It's caused by 4d291ee797a2d278d1af143e9d94b4deaecb930e "drm/amd/display: Add MST Preferred Link Setting Entry" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index b02aa290d6d09..6df87d119649d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -341,6 +341,7 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, return size; } +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector) { bool is_end_device = false; @@ -487,7 +488,7 @@ static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf, kfree(wr_buf); return size; } - +#endif /* function: get current DP PHY settings: voltage swing, pre-emphasis, * post-cursor2 (defined by VESA DP specification) * @@ -3029,12 +3030,13 @@ static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { .write = dp_dsc_passthrough_set, .llseek = default_llseek }; - +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE static const struct file_operations dp_mst_link_settings_debugfs_fops = { .owner = THIS_MODULE, .write = dp_mst_link_setting, .llseek = default_llseek }; +#endif static const struct { char *name; @@ -3064,7 +3066,9 @@ static const struct { #endif {"mst_progress_status", &dp_mst_progress_status_fops}, {"is_dpia_link", &is_dpia_link_fops}, +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE {"mst_link_settings", &dp_mst_link_settings_debugfs_fops} +#endif }; static const struct { From 686fe74d63ebbde5020c9a62700abbbbf5b2d13f Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Mon, 17 Apr 2023 18:52:54 -0400 Subject: [PATCH 1065/2653] drm/ttm: Update TTM memory limit for GFX9.4.3 APU This patch sets the TTM memory limit to be 3/4th of system memory for GFX 9.4.3 APU. This patch is only intended for DKMS branch. Signed-off-by: Mukul Joshi Reviewed-by: Felix Kuehling --- drivers/gpu/drm/ttm/ttm_device.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c index 6ebe30bfb9d46..bde34f69a7583 100644 --- a/drivers/gpu/drm/ttm/ttm_device.c +++ b/drivers/gpu/drm/ttm/ttm_device.c @@ -79,6 +79,9 @@ static int ttm_global_init(void) { struct ttm_global *glob = &ttm_glob; unsigned long num_pages, num_dma32; +#if IS_ENABLED(CONFIG_X86) + struct cpuinfo_x86 *c = &cpu_data(0); +#endif struct sysinfo si; int ret = 0; @@ -97,7 +100,17 @@ static int ttm_global_init(void) * system memory. */ num_pages = ((u64)si.totalram * si.mem_unit) >> PAGE_SHIFT; +#if IS_ENABLED(CONFIG_X86) + /* For GFX 9.4.3 APU, set mem limit to be 3/4th of + * system memory. + */ + if (c->x86 == 0x19 && c->x86_model == 0x90) + num_pages = (num_pages * 3) / 4; + else + num_pages /= 2; +#else num_pages /= 2; +#endif /* But for DMA32 we limit ourself to only use 2GiB maximum. */ num_dma32 = (u64)(si.totalram - si.totalhigh) * si.mem_unit From d16d614f308d3add59ea8b447f45bd40bcd58112 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 16 Jun 2023 10:48:18 +0800 Subject: [PATCH 1066/2653] drm/amdkcl: test whether drm_connector_state->colorspace is available It's caused by 95f27fa77de8dbc1e277af8dbb7d6f8640f650d1 "drm/amd/display: Send correct DP colorspace infopacket" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 46 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/struct_drm_connector_state.m4 | 21 +++++++++ 4 files changed, 71 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d77cc41828733..0d80dc78da1e4 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6270,6 +6270,7 @@ get_aspect_ratio(const struct drm_display_mode *mode_in) return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; } +#ifdef HAVE_DRM_CONNECTOR_STATE_COLORSPACE static enum dc_color_space get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, const struct drm_connector_state *connector_state) @@ -6328,6 +6329,51 @@ get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, return color_space; } +#else +static enum dc_color_space +get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, + const struct drm_connector_state *connector_state) +{ + enum dc_color_space color_space = COLOR_SPACE_SRGB; + + switch (dc_crtc_timing->pixel_encoding) { + case PIXEL_ENCODING_YCBCR422: + case PIXEL_ENCODING_YCBCR444: + case PIXEL_ENCODING_YCBCR420: + { + /* + * 27030khz is the separation point between HDTV and SDTV + * according to HDMI spec, we use YCbCr709 and YCbCr601 + * respectively + */ + if (dc_crtc_timing->pix_clk_100hz > 270300) { + if (dc_crtc_timing->flags.Y_ONLY) + color_space = + COLOR_SPACE_YCBCR709_LIMITED; + else + color_space = COLOR_SPACE_YCBCR709; + } else { + if (dc_crtc_timing->flags.Y_ONLY) + color_space = + COLOR_SPACE_YCBCR601_LIMITED; + else + color_space = COLOR_SPACE_YCBCR601; + } + + } + break; + case PIXEL_ENCODING_RGB: + color_space = COLOR_SPACE_SRGB; + break; + + default: + WARN_ON(1); + break; + } + + return color_space; +} +#endif static enum display_content_type get_output_content_type(const struct drm_connector_state *connector_state) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ede397b0a6612..8cc22fa267d19 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -473,6 +473,9 @@ /* drm_mode_create_dp_colorspace_property() has 2 args */ #define HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS 1 +/* drm_connector_state->colorspace is available */ +#define HAVE_DRM_CONNECTOR_STATE_COLORSPACE 1 + /* struct drm_dsc_config has member simple_422 */ #define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7d456d6b0431d..8d98aefbeba47 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -104,6 +104,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_DRM_MODE_CREATE_COLORSPACE_PROPERTY_FUNCS + AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU_ACPI_PUT_TABLE AC_AMDGPU_ACPI_DEV_GET_FIRST_MATCH_DEV diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 new file mode 100644 index 0000000000000..845426d6fe7bf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v5.0-rc7-1020-gd2c6a405846c +dnl # drm: Add HDMI colorspace property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STATE_COLORSPACE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *connector_state = NULL; + connector_state->colorspace = 0; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_STATE_COLORSPACE, 1, + [drm_connector_state->colorspace is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE], [ + AC_AMDGPU_DRM_CONNECTOR_STATE_COLORSPACE +]) \ No newline at end of file From d5892a4a15af0a3970b10afc5c43b94b0e55eb3a Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 20 Jun 2023 14:42:14 +0800 Subject: [PATCH 1067/2653] drm/amdkcl: Optimize the vma init function Rename the vma init funciton and initialize the vma manager only if the vam space less than 16T Signed-off-by: Ma Jun Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- .../kcl/backport/kcl_drm_vma_manager_backport.h | 15 ++++++++++++--- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 5f84e9e7b8574..b280f5452a63e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2426,7 +2426,8 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, adev->pdev = pdev; ddev = adev_to_drm(adev); - kcl_drm_vma_offset_manager_init(ddev->vma_offset_manager); + /* Check and increase the vma range */ + kcl_drm_vma_offset_manager_adjust(ddev->vma_offset_manager); if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; diff --git a/include/kcl/backport/kcl_drm_vma_manager_backport.h b/include/kcl/backport/kcl_drm_vma_manager_backport.h index 9893688f6fac2..b7b16df2f6d2c 100644 --- a/include/kcl/backport/kcl_drm_vma_manager_backport.h +++ b/include/kcl/backport/kcl_drm_vma_manager_backport.h @@ -42,16 +42,25 @@ #define DRM_FILE_PAGE_OFFSET_SIZE ((0xFFFFFFFFULL >> PAGE_SHIFT) * 4096) static inline void -kcl_drm_vma_offset_manager_init(struct drm_vma_offset_manager *mgr) +kcl_drm_vma_offset_manager_adjust(struct drm_vma_offset_manager *mgr) { - drm_vma_offset_manager_destroy(mgr); + u64 size; + + BUG_ON(!mgr); + + size = mgr->vm_addr_space_mm.head_node.hole_size; + if (size < DRM_FILE_PAGE_OFFSET_SIZE) + drm_vma_offset_manager_destroy(mgr); + else + return; + drm_vma_offset_manager_init(mgr, DRM_FILE_PAGE_OFFSET_START, DRM_FILE_PAGE_OFFSET_SIZE); } #else static inline void -kcl_drm_vma_offset_manager_init(struct drm_vma_offset_manager *mgr) +kcl_drm_vma_offset_manager_adjust(struct drm_vma_offset_manager *mgr) { } #endif From 8b1a9d6679b8656bc0b050d5833b14bca072764a Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 17 Jul 2023 16:22:47 +0800 Subject: [PATCH 1068/2653] drm/amdkcl: fake suballoc* It's caused by 849ee8a2f0df7a4ed4d281e19d3c9824b8e60bc2 drm/suballoc: Extract amdgpu_sa.c as generic suballocation helper Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c | 461 ++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../include/kcl/kcl_amdgpu_drm_fb_helper.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 5 + drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 | 17 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/header/drm/drm_suballoc.h | 10 + include/kcl/kcl_drm_suballoc.h | 113 +++++ 9 files changed, 610 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 create mode 100644 include/kcl/header/drm/drm_suballoc.h create mode 100644 include/kcl/kcl_drm_suballoc.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 08b2e37192c57..f8e0cdb1dd258 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o + kcl_irqdesc.o kcl_drm_suballoc.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c new file mode 100644 index 0000000000000..8ad6e3d9b60eb --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c @@ -0,0 +1,461 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2011 Red Hat Inc. + * Copyright 2023 Intel Corporation. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ +/* Algorithm: + * + * We store the last allocated bo in "hole", we always try to allocate + * after the last allocated bo. Principle is that in a linear GPU ring + * progression was is after last is the oldest bo we allocated and thus + * the first one that should no longer be in use by the GPU. + * + * If it's not the case we skip over the bo after last to the closest + * done bo if such one exist. If none exist and we are not asked to + * block we report failure to allocate. + * + * If we are asked to block we wait on all the oldest fence of all + * rings. We just wait for any of those fence to complete. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef HAVE_DRM_SUBALLOC_MANAGER_INIT +static void drm_suballoc_remove_locked(struct drm_suballoc *sa); +static void drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager); + +/** + * drm_suballoc_manager_init() - Initialise the drm_suballoc_manager + * @sa_manager: pointer to the sa_manager + * @size: number of bytes we want to suballocate + * @align: alignment for each suballocated chunk + * + * Prepares the suballocation manager for suballocations. + */ +void drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, + size_t size, size_t align) +{ + unsigned int i; + + BUILD_BUG_ON(!is_power_of_2(DRM_SUBALLOC_MAX_QUEUES)); + + if (!align) + align = 1; + + /* alignment must be a power of 2 */ + if (WARN_ON_ONCE(align & (align - 1))) + align = roundup_pow_of_two(align); + + init_waitqueue_head(&sa_manager->wq); + sa_manager->size = size; + sa_manager->align = align; + sa_manager->hole = &sa_manager->olist; + INIT_LIST_HEAD(&sa_manager->olist); + for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) + INIT_LIST_HEAD(&sa_manager->flist[i]); +} +EXPORT_SYMBOL(drm_suballoc_manager_init); + +/** + * drm_suballoc_manager_fini() - Destroy the drm_suballoc_manager + * @sa_manager: pointer to the sa_manager + * + * Cleans up the suballocation manager after use. All fences added + * with drm_suballoc_free() must be signaled, or we cannot clean up + * the entire manager. + */ +void drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager) +{ + struct drm_suballoc *sa, *tmp; + + if (!sa_manager->size) + return; + + if (!list_empty(&sa_manager->olist)) { + sa_manager->hole = &sa_manager->olist; + drm_suballoc_try_free(sa_manager); + if (!list_empty(&sa_manager->olist)) + DRM_ERROR("sa_manager is not empty, clearing anyway\n"); + } + list_for_each_entry_safe(sa, tmp, &sa_manager->olist, olist) { + drm_suballoc_remove_locked(sa); + } + + sa_manager->size = 0; +} +EXPORT_SYMBOL(drm_suballoc_manager_fini); + +static void drm_suballoc_remove_locked(struct drm_suballoc *sa) +{ + struct drm_suballoc_manager *sa_manager = sa->manager; + + if (sa_manager->hole == &sa->olist) + sa_manager->hole = sa->olist.prev; + + list_del_init(&sa->olist); + list_del_init(&sa->flist); + dma_fence_put(sa->fence); + kfree(sa); +} + +static void drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager) +{ + struct drm_suballoc *sa, *tmp; + + if (sa_manager->hole->next == &sa_manager->olist) + return; + + sa = list_entry(sa_manager->hole->next, struct drm_suballoc, olist); + list_for_each_entry_safe_from(sa, tmp, &sa_manager->olist, olist) { + if (!sa->fence || !dma_fence_is_signaled(sa->fence)) + return; + + drm_suballoc_remove_locked(sa); + } +} + +static size_t drm_suballoc_hole_soffset(struct drm_suballoc_manager *sa_manager) +{ + struct list_head *hole = sa_manager->hole; + + if (hole != &sa_manager->olist) + return list_entry(hole, struct drm_suballoc, olist)->eoffset; + + return 0; +} + +static size_t drm_suballoc_hole_eoffset(struct drm_suballoc_manager *sa_manager) +{ + struct list_head *hole = sa_manager->hole; + + if (hole->next != &sa_manager->olist) + return list_entry(hole->next, struct drm_suballoc, olist)->soffset; + return sa_manager->size; +} + +static bool drm_suballoc_try_alloc(struct drm_suballoc_manager *sa_manager, + struct drm_suballoc *sa, + size_t size, size_t align) +{ + size_t soffset, eoffset, wasted; + + soffset = drm_suballoc_hole_soffset(sa_manager); + eoffset = drm_suballoc_hole_eoffset(sa_manager); + wasted = round_up(soffset, align) - soffset; + + if ((eoffset - soffset) >= (size + wasted)) { + soffset += wasted; + + sa->manager = sa_manager; + sa->soffset = soffset; + sa->eoffset = soffset + size; + list_add(&sa->olist, sa_manager->hole); + INIT_LIST_HEAD(&sa->flist); + sa_manager->hole = &sa->olist; + return true; + } + return false; +} + +static bool __drm_suballoc_event(struct drm_suballoc_manager *sa_manager, + size_t size, size_t align) +{ + size_t soffset, eoffset, wasted; + unsigned int i; + + for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) + if (!list_empty(&sa_manager->flist[i])) + return true; + + soffset = drm_suballoc_hole_soffset(sa_manager); + eoffset = drm_suballoc_hole_eoffset(sa_manager); + wasted = round_up(soffset, align) - soffset; + + return ((eoffset - soffset) >= (size + wasted)); +} + +/** + * drm_suballoc_event() - Check if we can stop waiting + * @sa_manager: pointer to the sa_manager + * @size: number of bytes we want to allocate + * @align: alignment we need to match + * + * Return: true if either there is a fence we can wait for or + * enough free memory to satisfy the allocation directly. + * false otherwise. + */ +static bool drm_suballoc_event(struct drm_suballoc_manager *sa_manager, + size_t size, size_t align) +{ + bool ret; + + spin_lock(&sa_manager->wq.lock); + ret = __drm_suballoc_event(sa_manager, size, align); + spin_unlock(&sa_manager->wq.lock); + return ret; +} + +static bool drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, + struct dma_fence **fences, + unsigned int *tries) +{ + struct drm_suballoc *best_bo = NULL; + unsigned int i, best_idx; + size_t soffset, best, tmp; + + /* if hole points to the end of the buffer */ + if (sa_manager->hole->next == &sa_manager->olist) { + /* try again with its beginning */ + sa_manager->hole = &sa_manager->olist; + return true; + } + + soffset = drm_suballoc_hole_soffset(sa_manager); + /* to handle wrap around we add sa_manager->size */ + best = sa_manager->size * 2; + /* go over all fence list and try to find the closest sa + * of the current last + */ + for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) { + struct drm_suballoc *sa; + + fences[i] = NULL; + + if (list_empty(&sa_manager->flist[i])) + continue; + + sa = list_first_entry(&sa_manager->flist[i], + struct drm_suballoc, flist); + + if (!dma_fence_is_signaled(sa->fence)) { + fences[i] = sa->fence; + continue; + } + + /* limit the number of tries each freelist gets */ + if (tries[i] > 2) + continue; + + tmp = sa->soffset; + if (tmp < soffset) { + /* wrap around, pretend it's after */ + tmp += sa_manager->size; + } + tmp -= soffset; + if (tmp < best) { + /* this sa bo is the closest one */ + best = tmp; + best_idx = i; + best_bo = sa; + } + } + + if (best_bo) { + ++tries[best_idx]; + sa_manager->hole = best_bo->olist.prev; + + /* + * We know that this one is signaled, + * so it's safe to remove it. + */ + drm_suballoc_remove_locked(best_bo); + return true; + } + return false; +} + +/** + * drm_suballoc_new() - Make a suballocation. + * @sa_manager: pointer to the sa_manager + * @size: number of bytes we want to suballocate. + * @gfp: gfp flags used for memory allocation. Typically GFP_KERNEL but + * the argument is provided for suballocations from reclaim context or + * where the caller wants to avoid pipelining rather than wait for + * reclaim. + * @intr: Whether to perform waits interruptible. This should typically + * always be true, unless the caller needs to propagate a + * non-interruptible context from above layers. + * @align: Alignment. Must not exceed the default manager alignment. + * If @align is zero, then the manager alignment is used. + * + * Try to make a suballocation of size @size, which will be rounded + * up to the alignment specified in specified in drm_suballoc_manager_init(). + * + * Return: a new suballocated bo, or an ERR_PTR. + */ +struct drm_suballoc * +drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, + gfp_t gfp, bool intr, size_t align) +{ + struct dma_fence *fences[DRM_SUBALLOC_MAX_QUEUES]; + unsigned int tries[DRM_SUBALLOC_MAX_QUEUES]; + unsigned int count; + int i, r; + struct drm_suballoc *sa; + + if (WARN_ON_ONCE(align > sa_manager->align)) + return ERR_PTR(-EINVAL); + if (WARN_ON_ONCE(size > sa_manager->size || !size)) + return ERR_PTR(-EINVAL); + + if (!align) + align = sa_manager->align; + + sa = kmalloc(sizeof(*sa), gfp); + if (!sa) + return ERR_PTR(-ENOMEM); + sa->manager = sa_manager; + sa->fence = NULL; + INIT_LIST_HEAD(&sa->olist); + INIT_LIST_HEAD(&sa->flist); + + spin_lock(&sa_manager->wq.lock); + do { + for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) + tries[i] = 0; + + do { + drm_suballoc_try_free(sa_manager); + + if (drm_suballoc_try_alloc(sa_manager, sa, + size, align)) { + spin_unlock(&sa_manager->wq.lock); + return sa; + } + + /* see if we can skip over some allocations */ + } while (drm_suballoc_next_hole(sa_manager, fences, tries)); + + for (i = 0, count = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) + if (fences[i]) + fences[count++] = dma_fence_get(fences[i]); + + if (count) { + long t; + + spin_unlock(&sa_manager->wq.lock); + t = dma_fence_wait_any_timeout(fences, count, intr, + MAX_SCHEDULE_TIMEOUT, + NULL); + for (i = 0; i < count; ++i) + dma_fence_put(fences[i]); + + r = (t > 0) ? 0 : t; + spin_lock(&sa_manager->wq.lock); + } else if (intr) { + /* if we have nothing to wait for block */ + r = wait_event_interruptible_locked + (sa_manager->wq, + __drm_suballoc_event(sa_manager, size, align)); + } else { + spin_unlock(&sa_manager->wq.lock); + wait_event(sa_manager->wq, + drm_suballoc_event(sa_manager, size, align)); + r = 0; + spin_lock(&sa_manager->wq.lock); + } + } while (!r); + + spin_unlock(&sa_manager->wq.lock); + kfree(sa); + return ERR_PTR(r); +} +EXPORT_SYMBOL(drm_suballoc_new); + +/** + * drm_suballoc_free - Free a suballocation + * @suballoc: pointer to the suballocation + * @fence: fence that signals when suballocation is idle + * + * Free the suballocation. The suballocation can be re-used after @fence signals. + */ +void drm_suballoc_free(struct drm_suballoc *suballoc, + struct dma_fence *fence) +{ + struct drm_suballoc_manager *sa_manager; + + if (!suballoc) + return; + + sa_manager = suballoc->manager; + + spin_lock(&sa_manager->wq.lock); + if (fence && !dma_fence_is_signaled(fence)) { + u32 idx; + + suballoc->fence = dma_fence_get(fence); + idx = fence->context & (DRM_SUBALLOC_MAX_QUEUES - 1); + list_add_tail(&suballoc->flist, &sa_manager->flist[idx]); + } else { + drm_suballoc_remove_locked(suballoc); + } + wake_up_all_locked(&sa_manager->wq); + spin_unlock(&sa_manager->wq.lock); +} +EXPORT_SYMBOL(drm_suballoc_free); + +#ifdef CONFIG_DEBUG_FS +void drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, + struct drm_printer *p, + unsigned long long suballoc_base) +{ + struct drm_suballoc *i; + + spin_lock(&sa_manager->wq.lock); + list_for_each_entry(i, &sa_manager->olist, olist) { + unsigned long long soffset = i->soffset; + unsigned long long eoffset = i->eoffset; + + if (&i->olist == sa_manager->hole) + drm_puts(p, ">"); + else + drm_puts(p, " "); + + drm_printf(p, "[0x%010llx 0x%010llx] size %8lld", + suballoc_base + soffset, suballoc_base + eoffset, + eoffset - soffset); + + if (i->fence) + drm_printf(p, " protected by 0x%016llx on context %llu", + (unsigned long long)i->fence->seqno, + (unsigned long long)i->fence->context); + + drm_puts(p, "\n"); + } + spin_unlock(&sa_manager->wq.lock); +} +EXPORT_SYMBOL(drm_suballoc_dump_debug_info); +#endif +MODULE_AUTHOR("Multiple"); +MODULE_DESCRIPTION("Range suballocator helper"); +MODULE_LICENSE("Dual MIT/GPL"); +#endif /*HAVE_DRM_SUBALLOC_MANAGER_INIT*/ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e69fb1878b8b7..2a284365ba73c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -109,4 +109,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h index b67bfda700d77..5abb5cf97824c 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -32,6 +32,7 @@ #include #include +#include #include "amdgpu.h" #ifndef HAVE_DRM_FB_HELPER_LASTCLOSE diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index a88e31ef833a7..642993ebcc9cb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -87,4 +87,9 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_fbdev_generic.h]) + dnl # + dnl # v6.2-rc6-1265-g849ee8a2f0df + dnl # drm/suballoc: Extract amdgpu_sa.c as generic suballocation helper + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_suballoc.h]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 new file mode 100644 index 0000000000000..bcb026ad2c36d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.2-rc6-1265-g849ee8a2f0df +dnl # drm/suballoc: Extract amdgpu_sa.c as generic suballocation helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_suballoc_manager_init(NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_DRM_SUBALLOC_MANAGER_INIT, 1, + [Has function drm_suballoc_manager_init()]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8d98aefbeba47..f627fd2334515 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -199,6 +199,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_APPLE_GMUX_DETECT AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP AC_AMDGPU_ZONE_DEVICE_PAGE_INIT + AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/header/drm/drm_suballoc.h b/include/kcl/header/drm/drm_suballoc.h new file mode 100644 index 0000000000000..3eca4a8774ac4 --- /dev/null +++ b/include/kcl/header/drm/drm_suballoc.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_SUBALLOC_H_H_ +#define _KCL_HEADER_DRM_SUBALLOC_H_H_ + +#ifdef HAVE_DRM_DRM_SUBALLOC_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_drm_suballoc.h b/include/kcl/kcl_drm_suballoc.h new file mode 100644 index 0000000000000..46c61883e392f --- /dev/null +++ b/include/kcl/kcl_drm_suballoc.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2011 Red Hat Inc. + * Copyright © 2022 Intel Corporation + */ +#ifndef _KCL_DRM_SUBALLOC_H_ +#define _KCL_DRM_SUBALLOC_H_ + +#include + +#ifndef HAVE_DRM_DRM_SUBALLOC_H + +#include + +#include +#include + +#define DRM_SUBALLOC_MAX_QUEUES 32 +/** + * struct drm_suballoc_manager - fenced range allocations + * @wq: Wait queue for sleeping allocations on contention. + * @hole: Pointer to first hole node. + * @olist: List of allocated ranges. + * @flist: Array[fence context hash] of queues of fenced allocated ranges. + * @size: Size of the managed range. + * @align: Default alignment for the managed range. + */ +struct drm_suballoc_manager { + wait_queue_head_t wq; + struct list_head *hole; + struct list_head olist; + struct list_head flist[DRM_SUBALLOC_MAX_QUEUES]; + size_t size; + size_t align; +}; + +/** + * struct drm_suballoc - Sub-allocated range + * @olist: List link for list of allocated ranges. + * @flist: List linkk for the manager fenced allocated ranges queues. + * @manager: The drm_suballoc_manager. + * @soffset: Start offset. + * @eoffset: End offset + 1 so that @eoffset - @soffset = size. + * @dma_fence: The fence protecting the allocation. + */ +struct drm_suballoc { + struct list_head olist; + struct list_head flist; + struct drm_suballoc_manager *manager; + size_t soffset; + size_t eoffset; + struct dma_fence *fence; +}; + +void drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, + size_t size, size_t align); + +void drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager); + +struct drm_suballoc * +drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, + gfp_t gfp, bool intr, size_t align); + +void drm_suballoc_free(struct drm_suballoc *sa, struct dma_fence *fence); + +/** + * drm_suballoc_soffset - Range start. + * @sa: The struct drm_suballoc. + * + * Return: The start of the allocated range. + */ +static inline size_t drm_suballoc_soffset(struct drm_suballoc *sa) +{ + return sa->soffset; +} + +/** + * drm_suballoc_eoffset - Range end. + * @sa: The struct drm_suballoc. + * + * Return: The end of the allocated range + 1. + */ +static inline size_t drm_suballoc_eoffset(struct drm_suballoc *sa) +{ + return sa->eoffset; +} + +/** + * drm_suballoc_size - Range size. + * @sa: The struct drm_suballoc. + * + * Return: The size of the allocated range. + */ +static inline size_t drm_suballoc_size(struct drm_suballoc *sa) +{ + return sa->eoffset - sa->soffset; +} + +#ifdef CONFIG_DEBUG_FS +void drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, + struct drm_printer *p, + unsigned long long suballoc_base); +#else +static inline void +drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, + struct drm_printer *p, + unsigned long long suballoc_base) +{ } + +#endif +#endif /*HAVE_DRM_DRM_SUBALLOC_H*/ + +#endif /* _KCL_DRM_SUBALLOC_H_ */ From 725c9e404a82e307f3ee7d83de698601b8691601 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 17 Jul 2023 17:32:49 +0800 Subject: [PATCH 1069/2653] drm/amdkcl: drop include path include/kcl/header/uapi in dkms Makefile The file include/kcl/header/uapi has been clean up, so remove it from include path of dkms package. Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 39facc822b351..a73a7f7227df2 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -161,7 +161,6 @@ LINUXINCLUDE := \ -include $(src)/amd/dkms/config/config.h \ $(LINUX_SRCTREE_INCLUDE) \ -I$(src)/include/uapi \ - -I$(src)/include/kcl/header/uapi \ $(USER_INCLUDE) export CONFIG_HSA_AMD=y From 654d6add204e075cdd324be4451afdc3815d6dfb Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 17 Jul 2023 18:14:23 +0800 Subject: [PATCH 1070/2653] drm/amdkcl: fake vm_flags_{set, clear} It's caused by v6.2-rc4-446-gbc292ab00f6c mm: introduce vma->vm_flags wrapper functions Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 ++ .../amd/dkms/m4/mmap_assert_write_locked.m4 | 17 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 | 18 +++++++++++++++++ include/kcl/kcl_mm.h | 20 +++++++++++++++++++ 4 files changed, 57 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mmap_assert_write_locked.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f627fd2334515..53354926fc558 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -200,6 +200,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP AC_AMDGPU_ZONE_DEVICE_PAGE_INIT AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT + AC_AMDGPU_VM_FLAGS_SET + AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/mmap_assert_write_locked.m4 b/drivers/gpu/drm/amd/dkms/m4/mmap_assert_write_locked.m4 new file mode 100644 index 0000000000000..e79d2af6625ec --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmap_assert_write_locked.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 7dea19f9ee636cb244109a4dba426bbb3e5304b7 +dnl # mm: introduce memalloc_nofs_{save,restore} API +dnl # +AC_DEFUN([AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + mmap_assert_write_locked(NULL); + ], [ + AC_DEFINE(HAVE_MMAP_ASSERT_WRITE_LOCKED, 1, + [mmap_assert_write_locked() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 index 1eb0129ff303c..74cd3b8edd7ce 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 @@ -14,3 +14,21 @@ AC_DEFUN([AC_AMDGPU_VMA_LOOKUP], [ ]) ]) ]) + +dnl # +dnl # v6.2-rc4-446-gbc292ab00f6c +dnl # mm: introduce vma->vm_flags wrapper functions +dnl # +AC_DEFUN([AC_AMDGPU_VM_FLAGS_SET], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vm_flags_set(NULL, 0); + vm_flags_clear(NULL, 0); + ], [ + AC_DEFINE(HAVE_VM_FLAGS_SET, 1, + [vm_flags_{set, clear} is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index a230fc776153a..9d6df88ddf9fb 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -100,4 +100,24 @@ struct vm_area_struct *vma_lookup(struct mm_struct *mm, unsigned long addr) #define page_to_virt(x) __va(PFN_PHYS(page_to_pfn(x))) #endif +#ifndef HAVE_VM_FLAGS_SET +static inline void vm_flags_set(struct vm_area_struct *vma, + vm_flags_t flags) +{ +#ifdef HAVE_MMAP_ASSERT_WRITE_LOCKED + mmap_assert_write_locked(vma->vm_mm); +#endif + vma->vm_flags |= flags; +} + +static inline void vm_flags_clear(struct vm_area_struct *vma, + vm_flags_t flags) +{ +#ifdef HAVE_MMAP_ASSERT_WRITE_LOCKED + mmap_assert_write_locked(vma->vm_mm); +#endif + vma->vm_flags &= ~flags; +} +#endif + #endif /* AMDKCL_MM_H */ From 1e22fca948f56733dc52f0975537d9b9dc0c1a61 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Mon, 12 Jun 2023 12:05:28 -0400 Subject: [PATCH 1071/2653] drm/amdkfd: remove old debugger Remove the old debugger to make way for the upstreamed debugger. Signed-off-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 11 +++++++++++ include/uapi/linux/kfd_ioctl.h | 4 +++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 31dfaaccd3c09..00a2a96acd5e9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1749,6 +1749,14 @@ static int kfd_ioctl_export_dmabuf(struct file *filep, return ret; } +/* Place holder for deprecated DBG API */ +static int kfd_ioctl_dbg_set_debug_trap_deprecated(struct file *filep, + struct kfd_process *p, void *data) +{ + dev_dbg(kfd_device, "AMDKFD_IOC_DBG_TRAP is deprecated.\n"); + return -EINVAL; +} + /* Place holder for deprecated CMA API */ static int kfd_ioctl_cross_memory_copy_deprecated(struct file *filep, struct kfd_process *local_p, void *data) { @@ -3461,6 +3469,9 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_IPC_EXPORT_HANDLE, kfd_ioctl_ipc_export_handle, 0), + AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP_DEPRECATED, + kfd_ioctl_dbg_set_debug_trap_deprecated, 0), + AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, kfd_ioctl_rlc_spm, 0), diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 03178b1cd3206..10b03e950ac4a 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -248,7 +248,7 @@ struct kfd_ioctl_dbg_wave_control_args { #define KFD_INVALID_FD 0xffffffff -struct kfd_ioctl_dbg_trap_args { +struct kfd_ioctl_dbg_trap_args_deprecated { __u64 exception_mask; /* to KFD */ __u64 ptr; /* to KFD -- used for pointer arguments: queue arrays */ __u32 pid; /* to KFD */ @@ -1799,6 +1799,8 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_IPC_EXPORT_HANDLE \ AMDKFD_IOWR(0x81, struct kfd_ioctl_ipc_export_handle_args) +#define AMDKFD_IOC_DBG_TRAP_DEPRECATED \ + AMDKFD_IOWR(0x82, struct kfd_ioctl_dbg_trap_args_deprecated) #define AMDKFD_IOC_CROSS_MEMORY_COPY_DEPRECATED \ AMDKFD_IOWR(0x83, struct kfd_ioctl_cross_memory_copy_deprecated_args) From 19fbd3739aeafaeacecea80cd9a49667b0adf233 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 18 Jul 2023 15:32:09 +0800 Subject: [PATCH 1072/2653] drm/amdkcl: test whether drm_dp_mst_hpd_irq_handle_event() is available It's caused by 55970ce5015265eb0985f518995aa8fc4b3fa384 "drm/dp_mst: Clear MSG_RDY flag before sending new message" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 24 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../m4/drm_dp_mst_hpd_irq_handle_event.m4 | 16 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 44 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_hpd_irq_handle_event.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index b47cff81787f1..e97ac123fa977 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -814,6 +814,7 @@ void dm_handle_mst_sideband_msg_ready_event( /* handle MST irq */ if (aconnector->mst_mgr.mst_state) +#ifdef HAVE_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr, esi, ack, @@ -837,6 +838,29 @@ void dm_handle_mst_sideband_msg_ready_event( } drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr); +#else + drm_dp_mst_hpd_irq( + &aconnector->mst_mgr, + esi, + &new_irq_handled); + + if (new_irq_handled) { + /* ACK at DPCD to notify down stream */ + const int ack_dpcd_bytes_to_write = + dpcd_bytes_to_read - 1; + + for (retry = 0; retry < 3; retry++) { + u8 wret; + + wret = drm_dp_dpcd_write( + &aconnector->dm_dp_aux.aux, + dpcd_addr + 1, + &esi[1], + ack_dpcd_bytes_to_write); + if (wret == ack_dpcd_bytes_to_write) + break; + } +#endif new_irq_handled = false; } else { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8cc22fa267d19..64bf8375a4dd4 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -368,6 +368,9 @@ /* drm_dp_mst_{get,put}_port_malloc() is available */ #define HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC 1 +/* drm_dp_mst_hpd_irq_handle_event() is available */ +#define HAVE_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT 1 + /* drm_dp_mst_port struct has full_pbn member */ #define HAVE_DRM_DP_MST_PORT_FULL_PBN 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_hpd_irq_handle_event.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_hpd_irq_handle_event.m4 new file mode 100644 index 0000000000000..a70fd97681104 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_hpd_irq_handle_event.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.2-4472-g55970ce50152 +dnl # drm/dp_mst: Clear MSG_RDY flag before sending new message +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_mst_hpd_irq_handle_event(NULL, NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT, 1, + [drm_dp_mst_hpd_irq_handle_event() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 53354926fc558..26a5728a7550b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -153,6 +153,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_KOBJ_TYPE AC_AMDGPU_MIGRATE_DISABLE AC_AMDGPU_CLOSE_FD + AC_AMDGPU_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG From c02016040698e37940d1ee8cdeab829421df8c5c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 18 Jul 2023 16:55:33 +0800 Subject: [PATCH 1073/2653] drm/amdkcl: test whether drm_dp_mst_topology_cbs->poll_hpd_irq is available It's caused by ed8496801ab71fdfb9c9fdcbef058aa20a549ebd "drm/amd/display: Add polling method to handle MST reply packet" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-dp-mst-topology-cbs.m4 | 23 +++++++++++++++++++ 3 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index e97ac123fa977..b447afffbc95a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -874,10 +874,12 @@ void dm_handle_mst_sideband_msg_ready_event( DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); } +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr) { dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT); } +#endif #ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, @@ -938,7 +940,9 @@ static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { #ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR .register_connector = dm_dp_mst_register_connector #endif +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready, +#endif }; void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 64bf8375a4dd4..cfecf73ffef02 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -386,6 +386,9 @@ /* struct drm_dp_mst_topology_cbs has hotplug member */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG */ +/* struct drm_dp_mst_topology_cbs->poll_hpd_irq is available */ +#define HAVE_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ 1 + /* struct drm_dp_mst_topology_cbs->register_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 index 683d563cfc7bb..02dac4390e913 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -68,10 +68,33 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR], [ ]) ]) +dnl # +dnl # commit v5.7-rc1-646-g471bdd0df0d5 +dnl # drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ], [ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ], [ + struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; + dp_mst_cbs->poll_hpd_irq(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ, 1, + [struct drm_dp_mst_topology_cbs->poll_hpd_irq is available]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS], [ AC_KERNEL_DO_BACKGROUND([ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ ]) ]) From bee979aedf16b449371898345475d12190aeaa89 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 21 Jul 2023 14:13:55 +0800 Subject: [PATCH 1074/2653] drm/amdkcl: check PIDTYPE_PID whether exits It's caused by 6883f81aac6f44e7df70a6af189b3689ff52cbfb pid: Implement PIDTYPE_TGID Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 7 ++++++- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/pid_type.m4 | 17 +++++++++++++++++ 3 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pid_type.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 08babd4db37d8..f22ae84b50b66 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -1270,7 +1270,12 @@ static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused) */ rcu_read_lock(); pid = rcu_dereference(file->pid); - task = pid_task(pid, PIDTYPE_TGID); + task = pid_task(pid, +#ifdef HAVE_PIDTYPE_TGID + PIDTYPE_TGID); +#else + PIDTYPE_PID); +#endif seq_printf(m, "pid %8d command %s:\n", pid_nr(pid), task ? task->comm : ""); rcu_read_unlock(); diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 26a5728a7550b..0d16142cb24c9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -203,6 +203,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT AC_AMDGPU_VM_FLAGS_SET AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED + AC_AMDGPU_PID_TYPE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/pid_type.m4 b/drivers/gpu/drm/amd/dkms/m4/pid_type.m4 new file mode 100644 index 0000000000000..da986da3833f3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pid_type.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v4.18-rc1-6-g6883f81aac6f +dnl # pid: Implement PIDTYPE_TGID +dnl # +AC_DEFUN([AC_AMDGPU_PID_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum pid_type a; + a = PIDTYPE_TGID; + ], [ + AC_DEFINE(HAVE_PIDTYPE_TGID, 1, + [PIDTYPE is availablea]) + ]) + ]) +]) From 2b0562912d34e43aeec7a4ff2a0fa675df43a7c0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 24 Jul 2023 14:40:22 +0800 Subject: [PATCH 1075/2653] drm/amdkcl: Test struct dma_fence_ops whether has set_deadline It's caused by v6.3-rc2-1-gaec11c8d7cb3 dma-buf/dma-fence: Add deadline awareness Signed-off-by: Asher Song --- drivers/dma-buf/dma-resv.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/scheduler/sched_fence.c | 11 +++++++++- 4 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c index bea3e9858aca5..2e78a095eaaf6 100644 --- a/drivers/dma-buf/dma-resv.c +++ b/drivers/dma-buf/dma-resv.c @@ -708,6 +708,7 @@ EXPORT_SYMBOL_GPL(dma_resv_wait_timeout); * May be called without holding the dma_resv lock. Sets @deadline on * all fences filtered by @usage. */ +#ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE void dma_resv_set_deadline(struct dma_resv *obj, enum dma_resv_usage usage, ktime_t deadline) { @@ -721,6 +722,7 @@ void dma_resv_set_deadline(struct dma_resv *obj, enum dma_resv_usage usage, dma_resv_iter_end(&cursor); } EXPORT_SYMBOL_GPL(dma_resv_set_deadline); +#endif /** * dma_resv_test_signaled - Test if a reservation object's fences have been diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 index c10c92dfb503e..5fd3aeec58e80 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 @@ -15,3 +15,24 @@ AC_DEFUN([AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO], [ ]) ]) ]) + + +dnl # +dnl # v6.3-rc2-1-gaec11c8d7cb3 +dnl # dma-buf/dma-fence: Add deadline awareness +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_t deadline = 0; + struct dma_fence_ops *ops = NULL; + ops->set_deadline(NULL, deadline); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_OPS_SET_DEADLINE, 1, + [struct dma_fence_ops has callback set_deadline]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0d16142cb24c9..45ebd39abb906 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -204,6 +204,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VM_FLAGS_SET AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED AC_AMDGPU_PID_TYPE + AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/scheduler/sched_fence.c b/drivers/gpu/drm/scheduler/sched_fence.c index acd4eaab1fd03..5cba4c3477a18 100644 --- a/drivers/gpu/drm/scheduler/sched_fence.c +++ b/drivers/gpu/drm/scheduler/sched_fence.c @@ -48,6 +48,7 @@ static void __exit drm_sched_fence_slab_fini(void) kmem_cache_destroy(sched_fence_slab); } +#ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE static void drm_sched_fence_set_parent(struct drm_sched_fence *s_fence, struct dma_fence *fence) { @@ -61,6 +62,7 @@ static void drm_sched_fence_set_parent(struct drm_sched_fence *s_fence, &s_fence->finished.flags)) dma_fence_set_deadline(fence, s_fence->deadline); } +#endif void drm_sched_fence_scheduled(struct drm_sched_fence *fence, struct dma_fence *parent) @@ -72,8 +74,11 @@ void drm_sched_fence_scheduled(struct drm_sched_fence *fence, * up. */ if (!IS_ERR_OR_NULL(parent)) +#ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE drm_sched_fence_set_parent(fence, parent); - +#else + fence->parent = dma_fence_get(parent); +#endif dma_fence_signal(&fence->scheduled); } @@ -149,6 +154,7 @@ static void drm_sched_fence_release_finished(struct dma_fence *f) dma_fence_put(&fence->scheduled); } +#ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE static void drm_sched_fence_set_deadline_finished(struct dma_fence *f, ktime_t deadline) { @@ -179,6 +185,7 @@ static void drm_sched_fence_set_deadline_finished(struct dma_fence *f, if (parent) dma_fence_set_deadline(parent, deadline); } +#endif static const struct dma_fence_ops drm_sched_fence_ops_scheduled = { .get_driver_name = drm_sched_fence_get_driver_name, @@ -194,7 +201,9 @@ static const struct dma_fence_ops drm_sched_fence_ops_finished = { AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = drm_sched_fence_release_finished, +#ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE .set_deadline = drm_sched_fence_set_deadline_finished, +#endif }; struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f) From 22065b027225f6c4fc92ba89f693b6d4aaeb8f48 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 16:57:45 +0800 Subject: [PATCH 1076/2653] drm/amdkcl: update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index cfecf73ffef02..d2c77e315b716 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -127,6 +127,9 @@ /* dma_fence_is_container() is available */ #define HAVE_DMA_FENCE_IS_CONTAINER 1 +/* struct dma_fence_ops has callback set_deadline */ +#define HAVE_DMA_FENCE_OPS_SET_DEADLINE 1 + /* struct dma_fence_ops has use_64bit_seqno field */ #define HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO 1 @@ -455,6 +458,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_SUBALLOC_H 1 + /* drm_driver_feature DRIVER_IRQ_SHARED is available */ /* #undef HAVE_DRM_DRV_DRIVER_IRQ_SHARED */ @@ -613,6 +619,9 @@ /* drm_simple_encoder is available */ #define HAVE_DRM_SIMPLE_ENCODER_INIT 1 +/* Has function drm_suballoc_manager_init() */ +#define HAVE_DRM_SUBALLOC_MANAGER_INIT 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 @@ -838,8 +847,8 @@ /* migrate_vma->pgmap_owner is available */ #define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 -/* mmgrab() is available */ -#define HAVE_MMGRAB 1 +/* mmap_assert_write_locked() is available */ +#define HAVE_MMAP_ASSERT_WRITE_LOCKED 1 /* mmput_async() is available */ #define HAVE_MMPUT_ASYNC 1 @@ -895,6 +904,9 @@ /* vm_insert_mixed() wants pfn_t arg */ /* #undef HAVE_PFN_T_VM_INSERT_MIXED */ +/* PIDTYPE is availablea */ +#define HAVE_PIDTYPE_TGID 1 + /* pm_suspend_target_state is available */ #define HAVE_PM_SUSPEND_TARGET_STATE 1 @@ -1046,6 +1058,9 @@ /* vm_fault->{address/vam} is available */ #define HAVE_VM_FAULT_ADDRESS_VMA 1 +/* vm_flags_{set, clear} is available */ +#define HAVE_VM_FLAGS_SET 1 + /* vm_insert_pfn_prot() is available */ /* #undef HAVE_VM_INSERT_PFN_PROT */ From 6fc4091fac4a45e6434f80fc6453af916fd4a230 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 26 Jul 2023 13:38:15 +0800 Subject: [PATCH 1077/2653] drm/amdkcl: use vm_flags function to set vm_flags It's caused by bc292ab00f6c7a661a8a605c714e8a148f629ef6 "mm: introduce vma->vm_flags wrapper functions" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/kcl_drm_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c index 359099cb8af9e..84ffb99293e93 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c @@ -70,7 +70,7 @@ static int _kcl_drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_s goto err_drm_gem_object_put; } - vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP; + vm_flags_set(vma, VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP); vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); } From 7a15395a4ec3e57ff09c01a97c8550dd91c08e3b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 27 Jul 2023 01:05:14 +0800 Subject: [PATCH 1078/2653] drm/amdkfd: fix a build issue fix the following compile error: 2023-07-26T03:35:53.838Z] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_doorbell.c:194:6: error: no previous prototype for 'kfd_doorbell_unmap_locked' [-Werror=missing-prototypes] [2023-07-26T03:35:53.838Z] void kfd_doorbell_unmap_locked(struct kfd_process_device *pdd) [2023-07-26T03:35:53.838Z] ^~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index 3368779e354af..99e0d445ff2d9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -156,7 +156,7 @@ static const struct vm_operations_struct kfd_doorbell_vm_ops = { .fault = kfd_doorbell_vm_fault, }; -void kfd_doorbell_unmap_locked(struct kfd_process_device *pdd) +static void kfd_doorbell_unmap_locked(struct kfd_process_device *pdd) { struct kfd_process *process = pdd->process; struct vm_area_struct *vma; From 7e72a08ba60be50b31e401f890523877b6de1001 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 28 Jul 2023 15:15:50 +0800 Subject: [PATCH 1079/2653] drm/amdkcl: change the test for HMM support in kernel Because mmu_notifier_range.vma field is removed in kernel 6.3 by commit 7d4a8be0c4b2b7ffb367 (mm/mmu_notifier: remove unused mmu_notifier_range_update_to_read_only export), We should change the test for HMM support. Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 index 72147cbe68a28..72a1a8260873a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -49,6 +49,7 @@ dnl # 107e899874e9 - mm/hmm: define the pre-processor related parts of hmm.h eve dnl # v5.4-rc5-20-g04ec32fbc2b2 - mm/hmm: allow hmm_range to be used with a mmu_interval_notifier or hmm_mirror 2019-11-23 19:56:44 -0400 dnl # 99cb252f5e68 - mm/mmu_notifier: add an interval tree notifier 2019-11-23 19:56:44 -0400 dnl # 56f434f40f05 - mm/mmu_notifier: define the header pre-processor parts even if disabled 2019-11-12 20:18:27 -0400 +dnl # 7d4a8be0c4b2 - mm/mmu_notifier: remove unused mmu_notifier_range_update_to_read_only export dnl # AC_DEFUN([AC_AMDGPU_HMM], [ AC_KERNEL_DO_BACKGROUND([ @@ -61,7 +62,7 @@ AC_DEFUN([AC_AMDGPU_HMM], [ struct mmu_notifier_range *mmu_range = NULL; range->notifier = NULL; - mmu_range->vma = NULL; + mmu_range->event = 0; #else #error CONFIG_HMM_MIRROR not enabled #endif From 1c8fae3ca280410962e79b49070f3ff0711c9e0d Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Wed, 1 Sep 2021 17:02:38 -0400 Subject: [PATCH 1080/2653] drm/amdkfd: set conditional trap_en on aldebaran To ensure performance benchmarks remain suitable for non-debugged processes on aldebaran, make the per-vmid SPI debug TRAP_EN bit conditional on the HSA_ENABLE_DEBUG ENV variable for running processes. For single process debug devices, TRAP_EN will always be on but by spec, the KFD should still report the ttmp setup status set by runtime through the ENV variable. The debugger can choose to ignore this status from its own device lookup. Note: some of the functions that refresh the runlist can be cleaned up now that the dispatch index save is no longer toggled in the initialization or updating of the MQD and there will be a follow on set of patches to do this since they are not functional critical at the moment. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c index 8058ea91ecafd..fdaa7e72a62cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c @@ -772,7 +772,7 @@ void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev, for (i = first_vmid; i < last_vmid; i++) { data = 0; soc15_grbm_select(adev, 0, 0, 0, i, 0); - data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); + data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 0); data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0); data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0); From ba4c0af8ba3827caa83c6e576b46c8da5f45e795 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 28 Jun 2023 10:21:20 +0800 Subject: [PATCH 1081/2653] drm/amkcl: fake drm_edid_encode_panel_id() It's caused by de1da2f7fe25828288af8ca287a21fb8f0172c3e "drm/amd/display: Add monitor specific edid quirk" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_drm_edid.h | 14 ++++++++++++++ 2 files changed, 15 insertions(+) create mode 100644 include/kcl/kcl_drm_edid.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 2a284365ba73c..0f775ed076173 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -110,4 +110,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h new file mode 100644 index 0000000000000..dd472225c0477 --- /dev/null +++ b/include/kcl/kcl_drm_edid.h @@ -0,0 +1,14 @@ +#ifndef AMDKCL_DRM_EDID_H +#define AMDKCL_DRM_EDID_H + +#include + +#ifndef drm_edid_encode_panel_id +#define drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, product_id) \ + ((((u32)(vend_chr_0) - '@') & 0x1f) << 26 | \ + (((u32)(vend_chr_1) - '@') & 0x1f) << 21 | \ + (((u32)(vend_chr_2) - '@') & 0x1f) << 16 | \ + ((product_id) & 0xffff)) +#endif /* drm_edid_encode_panel_id */ + +#endif From 7d2e2c80fa38e93ca51809e2febad973cc417b3f Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 28 Jun 2023 17:59:26 -0400 Subject: [PATCH 1082/2653] drm/amdkcl: Some tests fix Fix tests that produce invalid results. AC_KERNEL_TRY_COMPILE_SYMBOL macro requires all possible locations of .c files to search for exported symbols. If file locations either missing or invalid the tests always return 'false'. Change-Id: I717cdfb283c3e7fe81c397d9ef3702b9593e5662 Signed-off-by: Slava Grigorev --- .../gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 | 2 +- .../drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 index 5dc461c4db3df..fd42b70c0fd97 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 @@ -16,7 +16,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; drm_dp_link_train_channel_eq_delay(aux, dpcd); - ], [drm_dp_link_train_channel_eq_delay],[drm/drm_dp_helper.c],[ + ], [drm_dp_link_train_channel_eq_delay],[drivers/gpu/drm/drm_dp_helper.c drivers/gpu/drm/display/drm_dp_helper.c],[ AC_DEFINE(HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS, 1, [drm_dp_link_train_channel_eq_delay() has 2 args]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 index 4d0c1a7e21313..dbd7be4543404 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 @@ -16,7 +16,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; drm_dp_link_train_clock_recovery_delay(aux, dpcd); - ], [drm_dp_link_train_clock_recovery_delay],[drm/drm_dp_helper.c],[ + ], [drm_dp_link_train_clock_recovery_delay],[drivers/gpu/drm/drm_dp_helper.c drivers/gpu/drm/display/drm_dp_helper.c],[ AC_DEFINE(HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS, 1, [drm_dp_link_train_clock_recovery_delay() has 2 args]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 index 318f729096712..883dc5867886e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 @@ -15,7 +15,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK], [ ], [ int ret; ret = drm_dp_mst_atomic_check(NULL); - ], [drm_dp_mst_atomic_check], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + ], [drm_dp_mst_atomic_check], [drivers/gpu/drm/drm_dp_mst_topology.c drivers/gpu/drm/display/drm_dp_mst_topology.c], [ AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_CHECK, 1, [drm_dp_mst_atomic_check() is available]) ]) From 9c31a47cac927a46e20045e3db51b7db81396669 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 29 Jun 2023 12:37:25 -0400 Subject: [PATCH 1083/2653] drm/amdkcl: Add including of a missing header file This fixes the build against older kernels that don't have drm/display/drm_hdcp_helper.h in their source trees. Change-Id: I25338fac38453a8bc7ee8adac9381000d2b4424d Signed-off-by: Slava Grigorev Reviewed-by: Slava Abramov --- include/kcl/header/drm/display/drm_hdcp_helper.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/kcl/header/drm/display/drm_hdcp_helper.h b/include/kcl/header/drm/display/drm_hdcp_helper.h index 047decb7fc695..8805018a9a244 100644 --- a/include/kcl/header/drm/display/drm_hdcp_helper.h +++ b/include/kcl/header/drm/display/drm_hdcp_helper.h @@ -4,6 +4,8 @@ #if defined(HAVE_DRM_DISPLAY_DRM_HDCP_HELPER_H) #include_next +#else +#include #endif #endif From 078d2055951fc42363726868c46be3332dc42db0 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 4 Jul 2023 11:13:36 +0800 Subject: [PATCH 1084/2653] drm/amdkcl: Test whether amdgpu_attr_group->is_bin_visible is available It's caused by fd536660bcbdbb15d6b715f2104d59fa1de50260 "drm/amd: Detect IFWI or PD upgrade support in psp_early_init()" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/struct_attribute_group.m4 | 17 +++++++++++++++++ 4 files changed, 25 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 75911600d5047..de8c01969e660 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -4306,6 +4306,7 @@ static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribu return adev->psp.sup_ifwi_up ? 0440 : 0; } +#ifdef HAVE_ATTRIBUTE_GROUP_IS_BIN_VISIBLE static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, const struct bin_attribute *attr, int idx) @@ -4316,11 +4317,14 @@ static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, return adev->psp.sup_ifwi_up ? 0660 : 0; } +#endif const struct attribute_group amdgpu_flash_attr_group = { .attrs = flash_attrs, .bin_attrs_new = bin_flash_attrs, +#ifdef HAVE_ATTRIBUTE_GROUP_IS_BIN_VISIBLE .is_bin_visible = amdgpu_bin_flash_attr_is_visible, +#endif .is_visible = amdgpu_flash_attr_is_visible, }; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d2c77e315b716..09075d9cca099 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -58,6 +58,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_ASM_SET_MEMORY_H 1 +/* amdgpu_attr_group->is_bin_visible is available */ +#define HAVE_ATTRIBUTE_GROUP_IS_BIN_VISIBLE 1 + /* backlight_device_set_brightness() is available */ #define HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 45ebd39abb906..f8e30f77009a8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -151,6 +151,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI AC_AMDGPU_DRM_BITMAP_FUNCS AC_AMDGPU_STRUCT_KOBJ_TYPE + AC_AMDGPU_ATTRIBUTE_GROUP_IS_BIN_VISIBLE AC_AMDGPU_MIGRATE_DISABLE AC_AMDGPU_CLOSE_FD AC_AMDGPU_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 new file mode 100644 index 0000000000000..80990947459d3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v4.3-rc4-9-g7f5028cf6190 +dnl # sysfs: Support is_visible() on binary attributes +dnl # +AC_DEFUN([AC_AMDGPU_ATTRIBUTE_GROUP_IS_BIN_VISIBLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct attribute_group *amdgpu_attr_group = NULL; + amdgpu_attr_group->is_bin_visible = NULL; + ],[ + AC_DEFINE(HAVE_ATTRIBUTE_GROUP_IS_BIN_VISIBLE, 1, + [amdgpu_attr_group->is_bin_visible is available]) + ]) + ]) +]) \ No newline at end of file From a05a32be0779cfd312c08147eff02ef9bf5207cb Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 29 Jun 2023 14:45:41 +0800 Subject: [PATCH 1085/2653] drm/amdkcl: fix m4 issue and update config.h Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 88 +++++++------------ drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 | 2 +- .../m4/drm-hdcp-update-content-protection.m4 | 5 +- 4 files changed, 37 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 09075d9cca099..5a0ced8b60313 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -10,6 +10,9 @@ /* whether access_ok(x, x) is available */ #define HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS 1 +/* acpi_dev_get_first_match_dev() is available */ +#define HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 1 + /* acpi_put_table() is available */ #define HAVE_ACPI_PUT_TABLE 1 @@ -163,6 +166,9 @@ /* down_write_killable() is available */ #define HAVE_DOWN_WRITE_KILLABLE 1 +/* drm_add_override_edid_modes() is available */ +/* #undef HAVE_DRM_ADD_OVERRIDE_EDID_MODES */ + /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_AMDGPU_PCIID_H */ @@ -182,6 +188,9 @@ /* drm_connector_attach_hdr_output_metadata_property() is available */ #define HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY 1 +/* drm_connector->edid_override is available */ +#define HAVE_DRM_CONNECTOR_EDID_OVERRIDE 1 + /* drm_connector_for_each_possible_encoder() wants 2 arguments */ #define HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS 1 @@ -211,29 +220,17 @@ /* drm_connector_set_panel_orientation_with_quirk() is available */ #define HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK 1 +/* drm_connector_state->colorspace is available */ +#define HAVE_DRM_CONNECTOR_STATE_COLORSPACE 1 + /* struct drm_connector_state has hdcp_content_type member */ #define HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE 1 /* struct drm_connector_state has hdr_output_metadata member */ #define HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA 1 -/* drm_connector_unreference() is available */ -/* #undef HAVE_DRM_CONNECTOR_UNREFERENCE */ - -/* drm_connector_xxx() drop _mode_ */ -#define HAVE_DRM_CONNECTOR_XXX_DROP_MODE 1 - -/* ddrm_atomic_stat has __drm_crtcs_state */ -/* #undef HAVE_DRM_CRTCS_STATE_MEMBER */ - -/* drm_crtc_accurate_vblank_count() is available */ -#define HAVE_DRM_CRTC_ACCURATE_VBLANK_COUNT 1 - -/* drm_crtc_enable_color_mgmt() is available */ -#define HAVE_DRM_CRTC_ENABLE_COLOR_MGMT 1 - -/* drm_crtc_from_index() is available */ -#define HAVE_DRM_CRTC_FROM_INDEX 1 +/* drm_connector_attach_colorspace_property() is available */ +#define HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY 1 /* drm_crtc_helper_funcs->atomic_check()/atomic_flush()/atomic_begin() wants struct drm_atomic_state arg */ @@ -323,9 +320,6 @@ /* drm_dp_mst_atomic_wait_for_dependencies() is available */ /* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ -/* acpi_dev_get_first_match_dev() is available */ -#define HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 1 - /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 @@ -428,7 +422,7 @@ /* drm_dp_update_payload_part1() function has start_slot argument */ /* #undef HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG */ -/* drm_driver->gem_prime_res_obj() is availab/le */ +/* drm_driver->gem_prime_res_obj() is available */ /* #undef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ */ /* Define to 1 if you have the header file. */ @@ -479,24 +473,15 @@ /* drm_dsc_compute_rc_parameters() is available */ #define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 -/* drm_connector_attach_colorspace_property() is available */ -#define HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY 1 - -/* drm_mode_create_hdmi_colorspace_property() has 2 args */ -#define HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS 1 - -/* drm_mode_create_dp_colorspace_property() has 2 args */ -#define HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS 1 - -/* drm_connector_state->colorspace is available */ -#define HAVE_DRM_CONNECTOR_STATE_COLORSPACE 1 - /* struct drm_dsc_config has member simple_422 */ #define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 /* drm_dsc_pps_payload_pack() is available */ #define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 +/* drm_edid_override_connector_update() is available */ +#define HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE 1 + /* drm_fb_helper_single_add_all_connectors() && drm_fb_helper_remove_one_connector() are symbol */ /* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ @@ -504,9 +489,6 @@ /* drm_fb_helper_alloc_info() is available */ #define HAVE_DRM_FB_HELPER_ALLOC_INFO 1 -/* migrate_disable() is available */ -#define HAVE_MIGRATE_DISABLE 1 - /* drm_fb_helper_fill_info() is available */ #define HAVE_DRM_FB_HELPER_FILL_INFO 1 @@ -549,12 +531,6 @@ /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 -/* drm_edid_override_connector_update() is available */ -#define HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE 1 - -/* drm_add_override_edid_modes() is available */ -/* #undef HAVE_DRM_ADD_OVERRIDE_EDID_MODES */ - /* drm_hdmi_avi_infoframe_from_display_mode() has p,p,b interface */ /* #undef HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B */ @@ -574,7 +550,7 @@ #define HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG 1 /* drm_modeset_backoff() has int return */ -#define HAVE_DRM_MODESET_BACKOFF_RETURN_INT 1 +/* #undef HAVE_DRM_MODESET_BACKOFF_RETURN_INT */ /* drm_mode_config->dp_subconnector_property is available */ #define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 @@ -585,6 +561,12 @@ /* drm_mode_config->fb_modifiers_not_supported is available */ #define HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED 1 +/* drm_mode_create_dp_colorspace_property() has 2 args */ +#define HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS 1 + +/* drm_mode_create_hdmi_colorspace_property() has 2 args */ +#define HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS 1 + /* drm_mode_init() is available */ #define HAVE_DRM_MODE_INIT 1 @@ -808,14 +790,8 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PROCESSOR_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_SCHED_MM_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_SCHED_SIGNAL_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_SCHED_TASK_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_RBTREE_TYPES_H 1 /* Define to 1 if you have the header file. */ #define HAVE_LINUX_STDARG_H 1 @@ -841,8 +817,8 @@ /* memalloc_noreclaim_save() is available */ #define HAVE_MEMALLOC_NORECLAIM_SAVE 1 -/* drm_connector->edid_override is available */ -#define HAVE_DRM_CONNECTOR_EDID_OVERRIDE 1 +/* migrate_disable() is available */ +#define HAVE_MIGRATE_DISABLE 1 /* struct migrate_vma has fault_page */ #define HAVE_MIGRATE_VMA_FAULT_PAGE 1 @@ -869,7 +845,7 @@ #define HAVE_MMU_NOTIFIER_SYNCHRONIZE 1 /* mm_access() is available */ -#define HAVE_MM_ACCESS 1 +/* #undef HAVE_MM_ACCESS */ /* release_pages() wants 2 args */ #define HAVE_MM_RELEASE_PAGES_2ARGS 1 @@ -1104,7 +1080,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 6.1.0" +#define PACKAGE_STRING "amdgpu-dkms 6.2.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1113,7 +1089,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "6.1.0" +#define PACKAGE_VERSION "6.2.0" #include "config-amd-chips.h" diff --git a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 index b0cabe1643a14..063fdc3d8f23b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 @@ -9,7 +9,7 @@ AC_DEFUN([AC_AMDGPU_CANCEL_WORK], [ #include ], [ cancel_work(NULL); - ], [ + ], [cancel_work], [], [ AC_DEFINE(HAVE_CANCEL_WORK, 1, [cancel_work() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 index 43fb1565aabc0..653c3e1e1ec98 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 @@ -5,7 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #include + #include ],[ struct drm_connector *connector = NULL; connector->edid_override = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 index f91f55f90ced8..e79473b4902ab 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 @@ -5,7 +5,8 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H + #ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H + #include #include #else #include @@ -17,4 +18,4 @@ AC_DEFUN([AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION], [ [drm_hdcp_update_content_protection is available]) ]) ]) -]) +]) \ No newline at end of file From 62da5ee57951fc9f94d5b2bb45c42771556e1997 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 11 Jul 2023 12:14:26 -0400 Subject: [PATCH 1086/2653] drm/amdkcl: Add including of a missing header file This fixes the build against older kernels that don't have linux/iosys-map.h in their source trees. Change-Id: Ibffc262ec70c63220b92573119749fd6cccaba58 Signed-off-by: Slava Grigorev Reviewed-by: Slava Abramov --- include/kcl/header/linux/iosys-map.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/kcl/header/linux/iosys-map.h b/include/kcl/header/linux/iosys-map.h index a96b1547378c6..9ce52ad756e1d 100644 --- a/include/kcl/header/linux/iosys-map.h +++ b/include/kcl/header/linux/iosys-map.h @@ -3,7 +3,8 @@ #ifdef HAVE_LINUX_IOSYS_MAP_H #include_next +#else +#include #endif #endif - From 5d5f2e200842bcc007d9f5be3e34ffa94d0163c9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 7 Jul 2023 14:26:32 +0800 Subject: [PATCH 1087/2653] drm/amdkcl: kcl-cleanup AMDKCL_AMDGPU_DRM_CONNECTOR_STATUS_DETECT_MANDATORY Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- include/kcl/kcl_drm_connector.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 9e95e282f458a..c0e2b217ddcc5 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -27,14 +27,6 @@ #include #include -/* - * commit v4.9-rc4-949-g949f08862d66 - * drm: Make the connector .detect() callback optional - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 10, 0) -#define AMDKCL_AMDGPU_DRM_CONNECTOR_STATUS_DETECT_MANDATORY -#endif - /** * drm_connector_for_each_possible_encoder - iterate connector's possible encoders * @connector: &struct drm_connector pointer From ffee8f85ea3efd726dafb8bbc848f1dcecd9d3f6 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 12 Jul 2023 10:21:55 +0800 Subject: [PATCH 1088/2653] drm/amdkcl: wrap code under macro HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP It's caused by 3f86b60691e60c57ad4ccc87a9b81e059c10af7e "drm/amd/display: only accept async flips for fast updates" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0d80dc78da1e4..5260d825347e7 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9640,7 +9640,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, * dm_crtc_helper_atomic_check() only accepts async flips with * fast updates. */ +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) if (crtc->state->async_flip && +#else + if ((crtc->state->pageflip_flags & + DRM_MODE_PAGE_FLIP_ASYNC) != 0 && +#endif (acrtc_state->update_type != UPDATE_TYPE_FAST || get_mem_type(old_plane_state->fb) != get_mem_type(fb))) drm_warn_once(state->dev, From e4bdfb2d8387c099e4f1709cad0662f602e32f5f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 13 Jul 2023 11:59:54 +0800 Subject: [PATCH 1089/2653] drm/amdkcl: fake drm_warn_once() It's caused by 3f86b60691e60c57ad4ccc87a9b81e059c10af7e "drm/amd/display: only accept async flips for fast updates" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- include/kcl/kcl_drm_print.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index c71867326f13b..15abde9faeb53 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -84,6 +84,11 @@ void kcl_drm_err(const char *format, ...); dev_warn((drm)->dev, "[drm] " fmt, ##__VA_ARGS__) #endif /* drm_warn */ +#ifndef drm_warn_once +#define drm_warn_once(drm, fmt, ...) \ + dev_warn_once((drm)->dev, "[drm] " fmt, ##__VA_ARGS__) +#endif /* drm_warn_once */ + #if !defined(DRM_UT_VBL) #define DRM_UT_VBL 0x20 #endif From 828b51c7d3443ee24aac3f3e0282de91fb723f9f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 14 Jul 2023 10:53:22 +0800 Subject: [PATCH 1090/2653] drm/amdkcl: fake want_init_on_free() It's caused by 88181f344c9156ee111013c7e38187803b15612c "drm/ttm: Use init_on_free to delay release TTM BOs" Signed-off-by: Bob Zhou Change-Id: I56137fef24020b8ab3c341cff07b2d4b7d5db8b9 --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 | 16 ++++++++++++++++ include/kcl/kcl_mm.h | 8 ++++++++ 4 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5a0ced8b60313..917f00952c434 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1049,6 +1049,9 @@ /* wait_queue_entry_t exists */ #define HAVE_WAIT_QUEUE_ENTRY 1 +/* want_init_on_free() is available */ +#define HAVE_WANT_INIT_ON_FREE 1 + /* ww_mutex_trylock() has context arg */ #define HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f8e30f77009a8..0ffb6b873f1fc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -198,6 +198,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE AC_AMDGPU_RB_ADD_CACHED + AC_AMDGPU_WANT_INIT_ON_FREE AC_AMDGPU_APPLE_GMUX_DETECT AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP AC_AMDGPU_ZONE_DEVICE_PAGE_INIT diff --git a/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 b/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 new file mode 100644 index 0000000000000..8503b32aeee1e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.2-5754-g6471384af2a6 +dnl # mm: security: introduce init_on_alloc=1 and init_on_free=1 boot options +dnl # +AC_DEFUN([AC_AMDGPU_WANT_INIT_ON_FREE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool r = want_init_on_free(); + ], [ + AC_DEFINE(HAVE_WANT_INIT_ON_FREE, 1, + [want_init_on_free() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 9d6df88ddf9fb..9151bdbed8785 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -120,4 +120,12 @@ static inline void vm_flags_clear(struct vm_area_struct *vma, } #endif +#ifndef HAVE_WANT_INIT_ON_FREE +static inline bool want_init_on_free(void) +{ + pr_warn_once("legacy kernel without want_init_on_free()\n"); + return false; +} +#endif + #endif /* AMDKCL_MM_H */ From 7f284fb22b20d9813937db7e5de4ccccdfb20f0c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 17 Jul 2023 10:45:58 +0800 Subject: [PATCH 1091/2653] drm/amdkcl: fake macros DRM_FORMAT_ARG* It's caused by fb69732876d0ef8e6252fed2585a2acb4f75f121 "drm/amd/display: Expose more formats for overlay planes on DCN" Signed-off-by: Bob Zhou Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- include/kcl/kcl_drm_fourcc.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h index 959f64bb803a6..f28a041070a75 100644 --- a/include/kcl/kcl_drm_fourcc.h +++ b/include/kcl/kcl_drm_fourcc.h @@ -222,4 +222,10 @@ #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ #endif +#ifndef DRM_FORMAT_ARGB16161616 +#define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ +#define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ +#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ +#endif + #endif /* KCL_KCL_DRM_FOURCC_H */ From 3b134dab2ff80ab9f0c5dfb4dced8e9d0bfbc405 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 17 Jul 2023 12:26:55 +0800 Subject: [PATCH 1092/2653] drm/amdkcl: wrap code under macro HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES It's caused by 6027cda96685ed287140febe7926a78c26a8ece4 "drm/amd/display: Fix race condition when turning off an output alone" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5260d825347e7..809e17f8cc95e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10296,7 +10296,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) trace_amdgpu_dm_atomic_commit_tail_begin(state); drm_atomic_helper_update_legacy_modeset_state(dev, state); +#ifdef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES drm_dp_mst_atomic_wait_for_dependencies(state); +#endif dm_state = dm_atomic_get_new_state(state); if (dm_state && dm_state->context) { From 954a3b143c0bf7e633795dc7028513a7f7d855a7 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 20 Jul 2023 09:13:54 -0400 Subject: [PATCH 1093/2653] drm/amdkcl: Fix tests for exported symbols Fix tests that produce invalid results. AC_KERNEL_TRY_COMPILE_SYMBOL macro requires all possible locations of .c files to search for exported symbols. If file locations either missing or invalid the tests always return 'false'. Change-Id: I3ef01cece3da727bfdd912b616b486f9ee407bdb Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 | 7 +++++-- .../amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 | 2 +- .../drm-connector-attach-hdr-output-metadata-property.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 4 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 index 27001acd98f95..83a0b1e027b9b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 @@ -4,8 +4,11 @@ dnl # ACPICA: Tables: Back port acpi_get_table_with_size() and dnl # early_acpi_os_unmap_memory() from Linux kernel AC_DEFUN([AC_AMDGPU_ACPI_PUT_TABLE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([acpi_put_table], - [drivers/acpi/acpica/tbxface.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + acpi_put_table(NULL); + ], [acpi_put_table], [drivers/acpi/acpica/tbxface.c], [ AC_DEFINE(HAVE_ACPI_PUT_TABLE, 1, [acpi_put_table() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 index 7ae2c3fd78efd..211e6fdd63702 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL], [ #include ], [ drm_connector_atomic_hdr_metadata_equal(NULL, NULL); - ], [drm_connector_atomic_hdr_metadata_equal], [drm/drm_connector.c], [ + ], [drm_connector_atomic_hdr_metadata_equal], [drivers/gpu/drm/drm_connector.c], [ AC_DEFINE(HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL, 1, [drm_connector_atomic_hdr_metadata_equal() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 index fccf8755fc7fe..7ea380c7d60eb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY], [ #include ], [ drm_connector_attach_hdr_output_metadata_property(NULL); - ], [drm_connector_attach_hdr_output_metadata_property], [drm/drm_connector.c], [ + ], [drm_connector_attach_hdr_output_metadata_property], [drivers/gpu/drm/drm_connector.c], [ AC_DEFINE(HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY, 1, [drm_connector_attach_hdr_output_metadata_property() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0ffb6b873f1fc..2787bebab1651 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -519,7 +519,7 @@ AC_DEFUN([AC_KERNEL_CHECK_SYMBOL_EXPORT], [ split(s, symbols, " ") } { for (i in symbols) { - s="EXPORT_SYMBOL.*\\("symbols[[i]]"\\);" + s="EXPORT_SYMBOL.*\\("symbols[[i]]"\\)" if ($[0] ~ s) n++ } From 43345ed14e315973f1523dfd1dfa2b83a79a52e8 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 24 Jul 2023 11:58:23 +0800 Subject: [PATCH 1094/2653] drm/amdkcl: apply amdkcl_ttm_resvp to dma_resv_trylock() It's caused by d769528e46493d56f9151fdecf25091b74c4eb49 "drm/amdgpu: add VISIBLE info in amdgpu_bo_print_info" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 1ba8c2fe7c6fc..5632f6ffc1fc8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1638,7 +1638,7 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) unsigned int pin_count; u64 size; - if (dma_resv_trylock(bo->tbo.base.resv)) { + if (dma_resv_trylock(amdkcl_ttm_resvp(&bo->tbo))) { if (!bo->tbo.resource) { placement = "NONE"; } else { @@ -1679,7 +1679,7 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) break; } } - dma_resv_unlock(bo->tbo.base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(&bo->tbo)); } else { placement = "UNKNOWN"; } From 92c8e27d7751227978e61a4b2e3c4da3dea63ebd Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 26 Jul 2023 10:19:59 +0800 Subject: [PATCH 1095/2653] drm/amdkcl: fake _dynamic_func_call_no_desc() It's caused by 3f4e4c813a265803029c1c7e1a9915ceb0fc5da4 "drm/amdkfd: avoid svm dump when dynamic debug disabled" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- include/kcl/kcl_dynamic_debug.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/kcl/kcl_dynamic_debug.h b/include/kcl/kcl_dynamic_debug.h index 6c6f7296eba94..0d5ad3a9d2d52 100644 --- a/include/kcl/kcl_dynamic_debug.h +++ b/include/kcl/kcl_dynamic_debug.h @@ -3,6 +3,8 @@ #ifndef AMDKCL_DYNAMIC_DEBUG_H #define AMDKCL_DYNAMIC_DEBUG_H +#include + #ifndef DECLARE_DYNDBG_CLASSMAP enum class_map_type { DD_CLASS_TYPE_DISJOINT_BITS, @@ -61,4 +63,16 @@ struct ddebug_class_map { #endif +#if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) +#ifndef _dynamic_func_call_no_desc +#define __dynamic_func_call_no_desc(id, fmt, func, ...) do { \ + DEFINE_DYNAMIC_DEBUG_METADATA(id, fmt); \ + if (DYNAMIC_DEBUG_BRANCH(id)) \ + func(__VA_ARGS__); \ +} while (0) + +#define _dynamic_func_call_no_desc(fmt, func, ...) \ + __dynamic_func_call_no_desc(__UNIQUE_ID(ddebug), fmt, func, ##__VA_ARGS__) +#endif /* _dynamic_func_call_no_desc */ +#endif /* CONFIG_DYNAMIC_DEBUG */ #endif /* AMDKCL_DYNAMIC_DEBUG_H */ From 02afaaf454007bcd94877bb72ef648f04209c924 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 28 Jul 2023 14:31:36 +0800 Subject: [PATCH 1096/2653] drm/amdkcl: update KCL M4 find path for drm_dp_mst_helper.h The file path of drm_dp_mst_helper.h has been modify to 'drm/display/', some old KCL script path is invalid. So update new path and fix m4 test issue for drm_dp_mst_atomic_wait_for_dependencies. Fixes: 7607389cc536 ("drm/amdkcl: Check if drm_dp_mst_atomic_wait_for_dependencies() is available") Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 6 +++--- .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 21 +++++++++++++++++-- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 917f00952c434..b0e608eb0d3b7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -315,10 +315,10 @@ /* #undef HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT */ /* drm_dp_mst_atomic_setup_commit() is available */ -/* #undef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT */ +#define HAVE_DRM_DP_ATOMIC_SETUP_COMMIT 1 /* drm_dp_mst_atomic_wait_for_dependencies() is available */ -/* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ +#define HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES 1 /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 @@ -378,7 +378,7 @@ #define HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX 1 /* drm_dp_mst_root_conn_atomic_check() is available */ -/* #undef HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK */ +#define HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK 1 /* struct drm_dp_mst_topology_cbs->destroy_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index d50c35a4fd1bc..96acc6bf42724 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -100,7 +100,13 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else #include + #endif ],[ int ret; ret = drm_dp_mst_atomic_setup_commit(NULL); @@ -120,10 +126,15 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else #include + #endif ],[ - int ret; - ret = drm_dp_mst_atomic_wait_for_dependencies(NULL); + drm_dp_mst_atomic_wait_for_dependencies(NULL); ],[ AC_DEFINE(HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES, 1, [drm_dp_mst_atomic_wait_for_dependencies() is available]) @@ -138,7 +149,13 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else #include + #endif ],[ int ret; ret = drm_dp_mst_root_conn_atomic_check(NULL, NULL); From f168de054a67bce8f2734befaa6722caabcfe8d5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 28 Jul 2023 15:07:56 +0800 Subject: [PATCH 1097/2653] drm/amdkcl: test whether drm_gem_atomic_helper.h is available Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 8 +++++++- include/kcl/header/drm/drm_gem_atomic_helper.h | 2 +- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b0e608eb0d3b7..c3ae177ad49a7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -446,6 +446,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_FBDEV_GENERIC_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_GEM_ATOMIC_HELPER_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_MANAGED_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 642993ebcc9cb..38a64fd0deb08 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -55,7 +55,13 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/dp: Move public DisplayPort headers into dp/ dnl # AC_KERNEL_CHECK_HEADERS([drm/dp/drm_dp_mst_helper.h]) - + + dnl # + dnl # v5.11-rc2-620-g6dd7b6ce43ac + dnl # drm: Add additional atomic helpers for shadow-buffered planes + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_gem_atomic_helper.h]) + dnl # dnl # v5.18-rc2-594-gda68386d9edb dnl # drm: Rename dp/ to display/ diff --git a/include/kcl/header/drm/drm_gem_atomic_helper.h b/include/kcl/header/drm/drm_gem_atomic_helper.h index ba17f457edc4f..1eb467c2c3327 100644 --- a/include/kcl/header/drm/drm_gem_atomic_helper.h +++ b/include/kcl/header/drm/drm_gem_atomic_helper.h @@ -2,7 +2,7 @@ #ifndef _KCL_HEADER_DRM_GEM_ATOMIC_HELPER_PREPARE_H_H_ #define _KCL_HEADER_DRM_GEM_ATOMIC_HELPER_PREPARE_H_H_ -#if defined(HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB) +#if defined(HAVE_DRM_DRM_GEM_ATOMIC_HELPER_H) #include_next #endif From b703cce6ce28a3d10bf336049db1169a151ca1ff Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 2 Aug 2023 10:33:07 +0800 Subject: [PATCH 1098/2653] drm/amdkcl: Fix typo in m4 file Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 b/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 index 6bf4a39e9679c..ed0b163902c11 100644 --- a/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 @@ -17,7 +17,7 @@ AC_DEFUN([AC_AMDGPU_TTM_BUFFER_OBJECT], [ gem_obj->resv = &gem_obj->_resv; ], [ AC_DEFINE(HAVE_DRM_GEM_OBJECT_RESV, 1, - [ttm_buffer_object->base is available]) + [drm_gem_object->resv/_resv is available]) ]) ]) ]) From 4b7d4f4e1bb97dd83b2d472c7e978e68fd446fd6 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 28 Jul 2023 17:34:58 +0800 Subject: [PATCH 1099/2653] drm/amdkcl: add kcl_header support for dkms m4 All of m4 script is using the same code block to verify if the header file is available, So add fake kcl header file and cleanup the verify for header files The M4 script will ben't blocked by the header file. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- .../gpu/drm/amd/dkms/m4/drm-device-pdev.m4 | 2 - .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 44 +------------------ .../gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 | 8 +--- .../drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 | 6 --- .../m4/drm-dp-cec-correlation-functions.m4 | 6 --- .../m4/drm-dp-link-train-channel-eq-delay.m4 | 8 +--- .../drm-dp-link-train-clock-recovery-delay.m4 | 6 --- .../m4/drm-dp-mst-add-affected-dsc-crtcs.m4 | 6 --- .../amd/dkms/m4/drm-dp-mst-atomic-check.m4 | 6 --- .../dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 | 12 ----- .../drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 | 6 --- .../dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 | 6 --- .../amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 | 6 --- .../gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 | 6 --- .../amd/dkms/m4/drm-dp-mst-topology-cbs.m4 | 24 ---------- .../dkms/m4/drm-dp-mst-topology-mgr-resume.m4 | 6 --- .../amd/dkms/m4/drm-dp-mst-topology-state.m4 | 18 -------- .../drm/amd/dkms/m4/drm-dp-mst-topology.m4 | 12 ----- .../dkms/m4/drm-dp-send-real-edid-checksum.m4 | 8 +--- .../gpu/drm/amd/dkms/m4/drm-driver-feature.m4 | 9 ---- .../amd/dkms/m4/drm-driver-gem-open-object.m4 | 4 -- .../dkms/m4/drm-driver-gem-prime-res-obj.m4 | 4 -- .../amd/dkms/m4/drm-fb-helper-fill-info.m4 | 3 -- .../m4/drm-hdcp-update-content-protection.m4 | 5 --- ...-up-update-payload-part1-start-slot-arg.m4 | 6 --- .../amd/dkms/m4/drm_dp_mst_topology_mgr.m4 | 6 --- .../dkms/m4/drm_dp_mst_topology_mgr_init.m4 | 6 --- .../dkms/m4/drm_dsc_compute_rc_parameters.m4 | 6 +-- drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 | 4 -- .../amd/dkms/m4/drm_dsc_pps_payload_pack.m4 | 4 -- .../gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 | 4 -- .../drm/amd/dkms/m4/kernel_single_target.m4 | 3 ++ .../amd/dkms/tiny_wrapper/include/drm/drmP.h | 10 +++++ .../tiny_wrapper/include/drm/drm_aperture.h | 9 ++++ .../tiny_wrapper/include/drm/drm_dp_helper.h | 14 ++++++ .../include/drm/drm_dp_mst_helper.h | 14 ++++++ .../dkms/tiny_wrapper/include/drm/drm_dsc.h | 17 +++++++ .../dkms/tiny_wrapper/include/drm/drm_hdcp.h | 12 +++++ 38 files changed, 84 insertions(+), 252 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drmP.h create mode 100644 drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_aperture.h create mode 100644 drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_helper.h create mode 100644 drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_mst_helper.h create mode 100644 drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dsc.h create mode 100644 drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_hdcp.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 index 25f5b1ca72eca..7bbbd70aab907 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 @@ -5,9 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DEVICE_PDEV], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H #include - #endif #include ], [ struct drm_device *pdd = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index 96acc6bf42724..2e5156f632700 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ int retval; retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0, 0); @@ -30,13 +24,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else - #include - #endif + #include ],[ int ret; ret = drm_dp_atomic_release_time_slots(NULL, NULL, NULL); @@ -49,13 +37,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS], [ dnl # drm/dp_mst: Start tracking per-port VCPI allocations dnl # AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ],[ int ret; struct drm_dp_mst_port *port; @@ -76,13 +58,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ],[ int ret; ret = drm_dp_atomic_find_time_slots(NULL, NULL, NULL, 0); @@ -100,13 +76,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ],[ int ret; ret = drm_dp_mst_atomic_setup_commit(NULL); @@ -126,13 +96,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ],[ drm_dp_mst_atomic_wait_for_dependencies(NULL); ],[ @@ -149,13 +113,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ],[ int ret; ret = drm_dp_mst_root_conn_atomic_check(NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 index a20efecd2b022..cef22c56ee51c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_AUX_DRM_DEV], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) - #include - #else - #include - #endif + #include ], [ struct drm_dp_aux dda; dda.drm_dev = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 index eabc0261dd0be..d168a591bcd23 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_calc_pbn_mode(0, 0, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 index 3ba925a8e076f..3ded1ff2015a2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_cec_register_connector(NULL, NULL); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 index fd42b70c0fd97..32db29f7c3936 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) - #include - #else - #include - #endif + #include ], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 index dbd7be4543404..327cd21b0200c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 index 42d7b5595403a..1d4564270d065 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ int ret; ret = drm_dp_mst_add_affected_dsc_crtcs(NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 index 883dc5867886e..e56284f5a5a2c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ int ret; ret = drm_dp_mst_atomic_check(NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 index 0019f393b38f3..ad901210aeaba 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_mst_atomic_enable_dsc(NULL, NULL, 0, 0, false); ], [drm_dp_mst_atomic_enable_dsc], [drivers/gpu/drm/drm_dp_mst_topology.c], [ @@ -25,13 +19,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ dnl # drm/display/dp_mst: Move all payload info into the atomic state dnl # AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ int vcpi; vcpi = drm_dp_mst_atomic_enable_dsc(NULL, NULL, 0, false); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 index 7c01c0479075e..4198140ed6a0e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DETECT_PORT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ int ret; ret = drm_dp_mst_detect_port(NULL, NULL, NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 index 522d9e0e4b565..06d77b61ab828 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_mst_dsc_aux_for_port(NULL); ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 index dc2ce8bd06835..e45e020edc7fc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_port *mst_port = NULL; mst_port->full_pbn = 0; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 index a1f26ca53e149..c66ffa1496233 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 @@ -5,13 +5,7 @@ dnl AC_DEFUN([AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_port *dp_mst_port = NULL; dp_mst_port->passthrough_aux = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 index 02dac4390e913..4e54d919e6a3c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -4,13 +4,7 @@ dnl # drm/dp-mst-helper: Remove hotplug callback dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG], [ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->hotplug(NULL); @@ -30,13 +24,7 @@ dnl # drm/dp/mst: split connector registration into two parts (v2) dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR], [ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->register_connector(NULL); @@ -52,13 +40,7 @@ dnl # drm/dp_mst: Remove drm_dp_mst_topology_cbs.destroy_connector dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR], [ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->destroy_connector(NULL, NULL); @@ -74,13 +56,7 @@ dnl # drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ], [ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->poll_hpd_irq(NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 index 961c150fe148e..3c491e182062e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ int ret; ret = drm_dp_mst_topology_mgr_resume(NULL, 0); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index 717d2d88653c3..5ac79129a86fe 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_state * mst_state = NULL; mst_state->total_avail_slots = 0; @@ -30,13 +24,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_state * mst_state = NULL; struct list_head payloads; @@ -56,13 +44,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_state * mst_state = NULL; int pbn_div; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 index cf4afe7538011..6de9a34aa627d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 @@ -15,13 +15,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_mst_get_port_malloc(NULL); drm_dp_mst_put_port_malloc(NULL); @@ -36,13 +30,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_mst_connector_early_unregister(NULL, NULL); drm_dp_mst_connector_late_register(NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 index 27b63066be2dc..f09bb93dd8a35 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) - #include - #else - #include - #endif + #include ], [ drm_dp_send_real_edid_checksum(NULL, 0); ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 index d10e0fcde3942..e480396741ffe 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 @@ -9,10 +9,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; #include - #endif #include ],[ int _ = DRIVER_SYNCOBJ_TIMELINE; @@ -28,10 +25,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; #include - #endif #include ],[ int _ = DRIVER_IRQ_SHARED; @@ -47,10 +41,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; #include - #endif #include ],[ int _ = DRIVER_PRIME; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 index 6631ba066edcf..0030f68fac152 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 @@ -15,12 +15,8 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_OPEN_OBJECT], [ dnl # commit v5.9-rc5-1077-gd693def4fd1c dnl # drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver AC_KERNEL_TRY_COMPILE([ - struct vm_area_struct; - #ifdef HAVE_DRM_DRMP_H #include - #else #include - #endif ],[ struct drm_driver *drv = NULL; drv->gem_open_object = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 index cf63fed2c4727..226e89eebe85c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 @@ -5,12 +5,8 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; #include - #else #include - #endif ], [ struct drm_driver *drv = NULL; drv->gem_prime_res_obj(NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 index bf7fcc83d14df..7eddabe7c8387 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 @@ -5,10 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_FILL_INFO], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; #include - #endif #include ], [ drm_fb_helper_fill_info(NULL, NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 index e79473b4902ab..55570026acaff 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 @@ -5,12 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H - #include - #include - #else #include - #endif ], [ drm_hdcp_update_content_protection(NULL, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 index 7839b7b00baee..1b341003bb985 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_update_payload_part1(NULL, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 index 06cdbe40de8cf..c674432e635f2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif #include ], [ struct drm_dp_mst_topology_mgr *mst_mgr = 0; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 index 66d1beb0b8a34..98d2982594b7c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_mst_topology_mgr_init(NULL, (struct drm_device *)NULL, NULL, 0, 0, 0, 0, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 index 57d179067d66b..a6f72c8fe6ba9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 @@ -5,11 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) - #include - #else - #include - #endif + #include ], [ drm_dsc_compute_rc_parameters(NULL); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 index c5c3c2c4418bb..e10e43c6dfe6c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 @@ -5,11 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DSC_H) - #include - #else #include - #endif ], [ struct drm_dsc_config *conf = NULL; conf->simple_422 = true; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 index 624e489e45e3a..b85668160976c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 @@ -5,11 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) - #include - #else #include - #endif ], [ drm_dsc_pps_payload_pack(NULL, NULL); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 index 8c0d4b9e932ea..5bbcaa354dfde 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 @@ -5,9 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_INIT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DRMP_H #include - #endif #include ], [ drm_fb_helper_init(NULL, NULL); @@ -20,9 +18,7 @@ AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_INIT], [ dnl # drm: Rely on mode_config data for fb_helper initialization dnl # AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DRMP_H #include - #endif #include ], [ drm_fb_helper_init(NULL, NULL, 0); diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index 7fd86cef1e099..91b36b22a7824 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -22,6 +22,9 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ -e '/-I/p; /-include/p; /-isystem/p; /-D/p' | \ xargs) + CFLAGS=$(echo $CFLAGS | \ + sed -e "s|nostdinc|nostdinc -I../tiny_wrapper/include|") + AC_SUBST(CC) AC_SUBST(CFLAGS) AC_SUBST(CPPFLAGS) diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drmP.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drmP.h new file mode 100644 index 0000000000000..c616e0e2c1798 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drmP.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRMP_H_H_ +#define _KCL_HEADER_DRMP_H_H_ + +#ifdef HAVE_DRM_DRMP_H +struct vm_area_struct; +#include_next +#endif + +#endif diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_aperture.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_aperture.h new file mode 100644 index 0000000000000..9197d9538fc69 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_aperture.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_APERTURE_H_H_ +#define _KCL_HEADER_DRM_APERTURE_H_H_ + +#if defined(HAVE_DRM_DRM_APERTURE_H) +#include_next +#endif + +#endif diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_helper.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_helper.h new file mode 100644 index 0000000000000..820228761e24b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_helper.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DP_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DP_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) +#include +#else +#include_next +#endif + +#endif + diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_mst_helper.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_mst_helper.h new file mode 100644 index 0000000000000..8a1cf0f4f9e33 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_mst_helper.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DP_MST_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DP_MST_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) +#include +#else +#include_next +#endif + +#endif + diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dsc.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dsc.h new file mode 100644 index 0000000000000..dfc77f48cef83 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dsc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DSC_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DSC_H_H_ + + +#if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) +#include +#endif + +#if defined(HAVE_DRM_DISPLAY_DRM_DSC_H) +#include +#else +#include_next +#endif + +#endif + diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_hdcp.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_hdcp.h new file mode 100644 index 0000000000000..309ffe3820d70 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_hdcp.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_DISPLAY_HDCP_H_INCLUDED_H_ +#define _KCL_HEADER_DRM_DISPLAY_HDCP_H_INCLUDED_H_ + +#ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H +#include +#include +#else +#include_next +#endif + +#endif From 57ad36f8f3376218906a641c41c64f78d668709b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 1 Aug 2023 14:43:21 +0800 Subject: [PATCH 1100/2653] drm/amdkcl: fake totalram_pages() It's caused by 83c53bcd07ebbd0dd213049a5abd799dee842775 "drm/amd: Disable S/G for APUs when 64GB or more host memory" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 9 +++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/totalram_pages.m4 | 17 +++++++++++++++++ include/kcl/kcl_mm.h | 8 ++++++++ 5 files changed, 38 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/totalram_pages.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index 637ecefbb9773..6357e5db55df3 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -36,6 +36,11 @@ extern struct kmem_cache *(*_kcl_kmalloc_slab)(size_t size, gfp_t flags); #endif #endif /* HAVE_KMALLOC_SIZE_ROUNDUP */ +#ifndef HAVE_TOTALRAM_PAGES +unsigned long *_kcl_totalram_pages; +EXPORT_SYMBOL(_kcl_totalram_pages); +#endif /* HAVE_TOTALRAM_PAGES */ + void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC @@ -47,4 +52,8 @@ void amdkcl_mm_init(void) _kcl_kmalloc_slab = amdkcl_fp_setup("kmalloc_slab", NULL); #endif #endif + +#ifndef HAVE_TOTALRAM_PAGES + _kcl_totalram_pages = (unsigned long *) amdkcl_fp_setup("totalram_pages", NULL); +#endif } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c3ae177ad49a7..7523702059057 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1001,6 +1001,9 @@ /* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 +/* totalram_pages() is available */ +#define HAVE_TOTALRAM_PAGES 1 + /* interval_tree_insert have struct rb_root_cached */ #define HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2787bebab1651..c0c5de884afb9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -180,6 +180,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CANCEL_WORK AC_AMDGPU_DMA_FENCE_IS_CONTAINER AC_AMDGPU_STR_YES_NO + AC_AMDGPU_TOTALRAM_PAGES AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE diff --git a/drivers/gpu/drm/amd/dkms/m4/totalram_pages.m4 b/drivers/gpu/drm/amd/dkms/m4/totalram_pages.m4 new file mode 100644 index 0000000000000..f57daa513df71 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/totalram_pages.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v4.20-6506-gca79b0c211af +dnl # mm: convert totalram_pages and totalhigh_pages variables to atomic +dnl # +AC_DEFUN([AC_AMDGPU_TOTALRAM_PAGES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + unsigned long ret; + ret = totalram_pages(); + ], [ + AC_DEFINE(HAVE_TOTALRAM_PAGES, 1, + [totalram_pages() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 9151bdbed8785..892cd2805e432 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -128,4 +128,12 @@ static inline bool want_init_on_free(void) } #endif +#ifndef HAVE_TOTALRAM_PAGES +extern unsigned long *_kcl_totalram_pages; +static inline unsigned long totalram_pages(void) +{ + return *_kcl_totalram_pages; +} +#endif /* HAVE_TOTALRAM_PAGES */ + #endif /* AMDKCL_MM_H */ From 699fec716eaf852c3cdd8c3f1e0a4d5cb13f7ec7 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 3 Aug 2023 14:08:16 +0800 Subject: [PATCH 1101/2653] drm/amdkcl: fix 'totalram_pages' redeclared as different kind of symbol cleanup _kcl_totalram_pages symbol and replace totalram_pages to _totalram_pages Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 9 --------- include/kcl/kcl_mm.h | 8 +++++--- 2 files changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index 6357e5db55df3..637ecefbb9773 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -36,11 +36,6 @@ extern struct kmem_cache *(*_kcl_kmalloc_slab)(size_t size, gfp_t flags); #endif #endif /* HAVE_KMALLOC_SIZE_ROUNDUP */ -#ifndef HAVE_TOTALRAM_PAGES -unsigned long *_kcl_totalram_pages; -EXPORT_SYMBOL(_kcl_totalram_pages); -#endif /* HAVE_TOTALRAM_PAGES */ - void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC @@ -52,8 +47,4 @@ void amdkcl_mm_init(void) _kcl_kmalloc_slab = amdkcl_fp_setup("kmalloc_slab", NULL); #endif #endif - -#ifndef HAVE_TOTALRAM_PAGES - _kcl_totalram_pages = (unsigned long *) amdkcl_fp_setup("totalram_pages", NULL); -#endif } diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 892cd2805e432..188cff38d5db6 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -129,11 +130,12 @@ static inline bool want_init_on_free(void) #endif #ifndef HAVE_TOTALRAM_PAGES -extern unsigned long *_kcl_totalram_pages; -static inline unsigned long totalram_pages(void) +extern unsigned long totalram_pages; +static inline unsigned long _kcl_totalram_pages(void) { - return *_kcl_totalram_pages; + return totalram_pages; } +#define totalram_pages _kcl_totalram_pages #endif /* HAVE_TOTALRAM_PAGES */ #endif /* AMDKCL_MM_H */ From 27f33d3ae0061c287256211d331915674eb17583 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 2 Aug 2023 13:53:34 +0800 Subject: [PATCH 1102/2653] drm/amdkcl: Fix the compile warnnings in m4 files Fix the compile warnnings of "-Wunused-variable" and "-Wuninitialized" in m4 files Signed-off-by: Ma Jun Reviewed-by: Bob Zhou --- .../gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 | 7 +++++-- drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 | 3 ++- drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 4 ++-- drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 | 9 ++++++--- drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 | 10 +++++----- drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 | 5 +++-- drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 | 3 ++- drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 | 3 ++- drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 | 3 ++- drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 | 3 ++- 12 files changed, 33 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 index ff2bf9c8949ad..7255ba02bca92 100644 --- a/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 @@ -7,8 +7,11 @@ AC_DEFUN([AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - void (*f)(struct pci_dev *pdev, u32 pasid); - amd_iommu_invalidate_ctx callback = f; + struct pci_dev *pdev = NULL; + u32 pasid = 0; + amd_iommu_invalidate_ctx callback = NULL; + + callback(pdev, pasid); ], [ AC_DEFINE(HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32, 1, [amd_iommu_invalidate_ctx take arg type of pasid as u32]) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 index 7867a6283d95f..1627d69677f9e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 @@ -24,7 +24,8 @@ AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - struct dma_fence_chain *chain = NULL; + struct dma_fence_chain *chain; + chain = NULL; ], [ AC_DEFINE(HAVE_STRUCT_DMA_FENCE_CHAIN, 1, [struct dma_fence_chain is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index 2e5156f632700..c0441f45a7861 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -40,11 +40,11 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS], [ #include ],[ int ret; - struct drm_dp_mst_port *port; + struct drm_dp_mst_port *port = NULL; ret = drm_dp_atomic_release_vcpi_slots(NULL, NULL, port); ],[ AC_DEFINE(HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT, 1, - [drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is available]) + [drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is available]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 index e480396741ffe..5ca66e8289bc1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 @@ -12,7 +12,8 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ #include #include ],[ - int _ = DRIVER_SYNCOBJ_TIMELINE; + int flag; + flag = DRIVER_SYNCOBJ_TIMELINE; ],[ AC_DEFINE(HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE, 1, [ drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available]) @@ -28,7 +29,8 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ #include #include ],[ - int _ = DRIVER_IRQ_SHARED; + int flag; + flag = DRIVER_IRQ_SHARED; ],[ AC_DEFINE(HAVE_DRM_DRV_DRIVER_IRQ_SHARED, 1, [ drm_driver_feature DRIVER_IRQ_SHARED is available]) @@ -44,7 +46,8 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ #include #include ],[ - int _ = DRIVER_PRIME; + int flag; + flag = DRIVER_PRIME; ],[ AC_DEFINE(HAVE_DRM_DRV_DRIVER_PRIME, 1, [ drm_driver_feature DRIVER_PRIME is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 index 95a45563d402e..54d06ba68400f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 @@ -7,11 +7,11 @@ AC_DEFUN([AC_AMDGPU_DRM_FORMAT_INFO], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - struct drm_format_info format = { - .format = DRM_FORMAT_XRGB16161616F, - .block_w = {0}, - .block_h = {0}, - }; + struct drm_format_info format; + + format.format = DRM_FORMAT_XRGB16161616F; + format.block_w[0] = 0; + format.block_h[0] = 0; ], [ AC_DEFINE(HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED, 1, [drm_format_info.block_w and rm_format_info.block_h is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 b/drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 index a629dac5f4aad..bb3cf8a0beff9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_PCI_DEV_LTR_PATH], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - struct pci_dev *dev; + struct pci_dev *dev = NULL; dev->ltr_path = 0; ], [ AC_DEFINE(HAVE_PCI_DEV_LTR_PATH, 1, diff --git a/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 b/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 index 786ce2c5590ac..53d34285e3b83 100644 --- a/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 @@ -11,8 +11,9 @@ AC_DEFUN([AC_AMDGPU_MEMORY_DEVICE_COHERENT], [ #include #include ], [ - int v = MEMORY_DEVICE_COHERENT; - int w = MIGRATE_VMA_SELECT_DEVICE_COHERENT; + int v, w; + v = MEMORY_DEVICE_COHERENT; + w = MIGRATE_VMA_SELECT_DEVICE_COHERENT; ], [ AC_DEFINE(HAVE_DEVICE_COHERENT, 1, [MEMORY_DEVICE_COHERENT is availablea]) diff --git a/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 b/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 index ab6586797229a..108c7086638bd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 @@ -7,7 +7,7 @@ AC_DEFUN([AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - size_t a, b; + size_t a, b = 0; a = kmalloc_size_roundup(b); ], [ AC_DEFINE(HAVE_KMALLOC_SIZE_ROUNDUP, 1, diff --git a/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 b/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 index 9ca6f08ae00e7..5aefabf94021b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 @@ -7,7 +7,8 @@ AC_DEFUN([AC_AMDGPU_STR_YES_NO], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - const char *str = str_yes_no(true); + const char *str; + str = str_yes_no(true); ], [ AC_DEFINE(HAVE_STR_YES_NO, 1, [str_yes_no() is defined]) diff --git a/drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 b/drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 index a5744a51a8ffb..3ac6f9d5a31ea 100644 --- a/drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 @@ -7,7 +7,8 @@ AC_DEFUN([AC_AMDGPU_TYPE__POLL_T], [ AC_KERNEL_TRY_COMPILE([ #include ],[ - __poll_t mask = 0; + __poll_t mask; + mask = 0; ],[ AC_DEFINE(HAVE_TYPE__POLL_T, 1, [__poll_t is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 b/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 index 8503b32aeee1e..47463793e94b1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 @@ -7,7 +7,8 @@ AC_DEFUN([AC_AMDGPU_WANT_INIT_ON_FREE], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - bool r = want_init_on_free(); + bool r; + r = want_init_on_free(); ], [ AC_DEFINE(HAVE_WANT_INIT_ON_FREE, 1, [want_init_on_free() is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 b/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 index e3018a1b798e0..9d87289b3bfc8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 @@ -7,7 +7,8 @@ AC_DEFUN([AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - int r = ww_mutex_trylock(NULL, NULL); + int r; + r = ww_mutex_trylock(NULL, NULL); ], [ AC_DEFINE(HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG, 1, [ww_mutex_trylock() has context arg]) From 37ea0699ef63e932629a678c9842d302a8cde7ba Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 3 Aug 2023 11:08:58 +0800 Subject: [PATCH 1103/2653] drm/amdkcl: Optimize the code wrapped in the macro HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG [1] Fix the typo. [2] The fault function is not used here, so remove it. [3] Optimize the code wrapped in this macro. Only the vm_operations_struct->falut() function needs this macro Signed-off-by: Ma Jun Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 ----- drivers/gpu/drm/amd/dkms/config/config.h | 5 +-- .../drm/amd/dkms/m4/vm_operations_struct.m4 | 5 ++- drivers/gpu/drm/ttm/ttm_bo_vm.c | 35 ++----------------- include/drm/ttm/ttm_bo.h | 12 ++----- 5 files changed, 7 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 821eedaa1cf81..ae20966fc21ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2616,11 +2616,7 @@ static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf) #endif vm_fault_t ret; -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG - ret = ttm_bo_vm_reserve(bo, vmf, vma); -#else ret = ttm_bo_vm_reserve(bo, vmf); -#endif if (ret) return ret; @@ -2628,12 +2624,8 @@ static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf) if (ret) goto unlock; -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG - ret = ttm_bo_vm_fault_reserved(vmf, vma, vma->vm_page_prot, TTM_BO_VM_NUM_PREFAULT); -#else ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, TTM_BO_VM_NUM_PREFAULT); -#endif if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) return ret; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7523702059057..f59799ab2ed52 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1037,10 +1037,7 @@ /* vmf_insert_pfn_prot() is available */ #define HAVE_VMF_INSERT_PFN_PROT 1 -/* vmf_insert_pfn_pud() is available */ -/* #undef HAVE_VMF_INSERT_PFN_PUD */ - -/* vm_fault->{address/vam} is available */ +/* vm_fault->{address/vma} is available */ #define HAVE_VM_FAULT_ADDRESS_VMA 1 /* vm_flags_{set, clear} is available */ diff --git a/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 b/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 index 9e01b9fb9f36b..111d006f1ac28 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 @@ -7,14 +7,13 @@ AC_DEFUN([AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - int (*fault)(struct vm_area_struct *vma, struct vm_fault *vmf) = 0; struct vm_operations_struct *vm_ops = NULL; vm_ops->fault(NULL); ], [ AC_DEFINE(HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG, 1, [vm_operations_struct->fault() wants 1 arg]) AC_DEFINE(HAVE_VM_FAULT_ADDRESS_VMA, 1, - [vm_fault->{address/vam} is available]) + [vm_fault->{address/vma} is available]) ], [ dnl # dnl # commit v4.9-7746-g82b0f8c39a38 @@ -28,7 +27,7 @@ AC_DEFUN([AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT], [ ptest->vma = NULL; ], [ AC_DEFINE(HAVE_VM_FAULT_ADDRESS_VMA, 1, - [vm_fault->{address/vam} is available]) + [vm_fault->{address/vma} is available]) ]) ]) ]) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 18e898018c266..d96202a8bf56b 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -119,17 +119,10 @@ static unsigned long ttm_bo_io_mem_pfn(struct ttm_buffer_object *bo, * VM_FAULT_RETRY if blocking wait. * VM_FAULT_NOPAGE if blocking wait and retrying was not allowed. */ -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG -vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, - struct vm_fault *vmf, - struct vm_area_struct *vma) -{ -#else vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, struct vm_fault *vmf) { struct vm_area_struct *vma = vmf->vma; -#endif /* * Work around locking order reversal in fault / nopfn * between mmap_lock and bo_reserve: Perform a trylock operation @@ -192,19 +185,11 @@ EXPORT_SYMBOL(ttm_bo_vm_reserve); * VM_FAULT_OOM on out-of-memory * VM_FAULT_RETRY if retryable wait */ -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG -vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, - struct vm_area_struct *vma, - pgprot_t prot, - pgoff_t num_prefault) -{ -#else vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, pgprot_t prot, pgoff_t num_prefault) { struct vm_area_struct *vma = vmf->vma; -#endif struct ttm_buffer_object *bo = vma->vm_private_data; struct ttm_device *bdev = bo->bdev; unsigned long page_offset; @@ -315,14 +300,9 @@ static void ttm_bo_release_dummy_page(struct drm_device *dev, void *res) __free_page(dummy_page); } -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG -vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, struct vm_area_struct *vma, pgprot_t prot) -{ -#else vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, pgprot_t prot) { struct vm_area_struct *vma = vmf->vma; -#endif struct ttm_buffer_object *bo = vma->vm_private_data; struct drm_device *ddev = bo->base.dev; vm_fault_t ret = VM_FAULT_NOPAGE; @@ -366,30 +346,19 @@ vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf) vm_fault_t ret; int idx; -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG - ret = ttm_bo_vm_reserve(bo, vmf, vma); -#else ret = ttm_bo_vm_reserve(bo, vmf); -#endif if (ret) return ret; prot = vma->vm_page_prot; - if (drm_dev_enter(ddev, &idx)) { -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG - ret = ttm_bo_vm_fault_reserved(vmf, vma, prot, TTM_BO_VM_NUM_PREFAULT); -#else + if (drm_dev_enter(ddev, &idx)) { ret = ttm_bo_vm_fault_reserved(vmf, prot, TTM_BO_VM_NUM_PREFAULT); -#endif drm_dev_exit(idx); } else { -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG - ret = ttm_bo_vm_dummy_page(vmf, vma, prot); -#else ret = ttm_bo_vm_dummy_page(vmf, prot); -#endif } + if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) return ret; diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h index 865f386f19b25..808b8889417e1 100644 --- a/include/drm/ttm/ttm_bo.h +++ b/include/drm/ttm/ttm_bo.h @@ -456,23 +456,15 @@ int ttm_bo_evict_first(struct ttm_device *bdev, int ttm_bo_access(struct ttm_buffer_object *bo, unsigned long offset, void *buf, int len, int write); -#if defined(HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG) vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, struct vm_fault *vmf); vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, pgprot_t prot, pgoff_t num_prefault); + +#if defined(HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG) vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf); #else -vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, - struct vm_fault *vmf, - struct vm_area_struct *vma); - -vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, - struct vm_area_struct *vma, - pgprot_t prot, - pgoff_t num_prefault); - vm_fault_t ttm_bo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf); #endif From c22f8d6c31bd8b2d3ba7fb442d1e8a0dedb47685 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 3 Aug 2023 13:10:47 +0800 Subject: [PATCH 1104/2653] drm/amdkcl: Modify compile CFLAGS for m4 files Removing "-Wno-error=uninitialized -Wno-error=unused-variable" to make these two kinds of warnning as error when compile m4 files. Signed-off-by: Ma Jun Reviewed-by: Bob Zhou Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c0c5de884afb9..b096d25b6e94d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -418,7 +418,7 @@ AC_DEFUN([AC_KERNEL_COMPILE_MODULE_IFELSE], [ test "x$enable_linux_builtin" = xyes && kbuild_src_flag='KBUILD_SRC=' # override KBUILD_SRC test "x$enable_linux_builtin" = xyes && kbuild_workaround_flag='sub_make_done=' # override sub_make_done AS_IF( - [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=uninitialized -Wno-error=unused-variable -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], + [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], [$4], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] ) From acbf019d6fb2915c294943565e192254e271a5b8 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 8 Aug 2023 10:10:19 +0800 Subject: [PATCH 1105/2653] drm/amdkcl: wrap code under macro HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP It's caused by 6fb5589425ee17f732aaae462532d5034b096212 "drm/amd/display: ensure async flips are only accepted for fast updates" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 809e17f8cc95e..38bdbfa6d238c 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12512,7 +12512,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, * Only allow async flips for fast updates that don't change * the FB pitch, the DCC state, rotation, mem_type, etc. */ +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) if (new_crtc_state->async_flip && +#else + if ((new_crtc_state->pageflip_flags & + DRM_MODE_PAGE_FLIP_ASYNC) != 0 && +#endif (lock_and_validation_needed || amdgpu_dm_crtc_mem_type_changed(dev, state, new_crtc_state))) { drm_dbg_atomic(crtc->dev, From 63d11a2d478ba917c2a613adfff481c2a028ad55 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 11 Aug 2023 13:42:06 +0800 Subject: [PATCH 1106/2653] drm/amdkcl: Fix the uninitialized warning in m4 Signed-off-by: Ma Jun Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 b/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 index 406fa50e310c5..f989b29503c45 100644 --- a/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE], [ #include ], [ struct migrate_vma mig = {0}; - struct page *fault_page; + struct page *fault_page = NULL; mig.fault_page = fault_page; ], [ AC_DEFINE(HAVE_MIGRATE_VMA_FAULT_PAGE, 1, From c4e8dd8bcb9a4db56bafc8a17de523d168819303 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 14 Aug 2023 11:11:40 +0800 Subject: [PATCH 1107/2653] drm/amdkcl: fix file search path for m4 script Some file path has been modified, so update these file search path. Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 | 2 +- .../gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 index 063fdc3d8f23b..1f0558d0ade28 100644 --- a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 @@ -9,7 +9,7 @@ AC_DEFUN([AC_AMDGPU_CANCEL_WORK], [ #include ], [ cancel_work(NULL); - ], [cancel_work], [], [ + ], [cancel_work], [kernel/workqueue.c], [ AC_DEFINE(HAVE_CANCEL_WORK, 1, [cancel_work() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 index 1d4564270d065..c9127ca8d82c3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 @@ -9,7 +9,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS], [ ], [ int ret; ret = drm_dp_mst_add_affected_dsc_crtcs(NULL, NULL); - ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c drivers/gpu/drm/display/drm_dp_mst_topology.c], [ AC_DEFINE(HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS, 1, [drm_dp_mst_add_affected_dsc_crtcs() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 index 06d77b61ab828..6d83fb019062d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT], [ #include ], [ drm_dp_mst_dsc_aux_for_port(NULL); - ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c drivers/gpu/drm/display/drm_dp_mst_topology.c], [ AC_DEFINE(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT, 1, [drm_dp_mst_dsc_aux_for_port() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 index f09bb93dd8a35..44343cb753bbe 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 @@ -5,10 +5,10 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include + #include ], [ drm_dp_send_real_edid_checksum(NULL, 0); - ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c], [ + ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c drivers/gpu/drm/display/drm_dp_helper.c], [ AC_DEFINE(HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM, 1, [drm_dp_send_real_edid_checksum() is available]) ]) From 7b0dac6d6edc4c44d66a0479f154d9b130eef77f Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 15 Aug 2023 17:31:22 +0800 Subject: [PATCH 1108/2653] drm/amdkcl: Fix error in HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 check The original code can't detect the wrong param type. Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 index 7255ba02bca92..3ddbe27c03284 100644 --- a/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 @@ -7,11 +7,10 @@ AC_DEFUN([AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - struct pci_dev *pdev = NULL; - u32 pasid = 0; - amd_iommu_invalidate_ctx callback = NULL; + void (*f)(struct pci_dev *pdev, u32 pasid) = NULL; + amd_iommu_invalidate_ctx callback; - callback(pdev, pasid); + callback = f; ], [ AC_DEFINE(HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32, 1, [amd_iommu_invalidate_ctx take arg type of pasid as u32]) From 517c3ddb33756f191c121c7b1614bf8f18ff31bc Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 16 Aug 2023 11:48:36 +0800 Subject: [PATCH 1109/2653] drm/amdkfd: Correct some spacing errors introduced in rebase process Signed-off-by: Asher Song Reviewd-by: Kent Russell --- drivers/gpu/drm/amd/amdkfd/Makefile | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index ee40591c23b31..cf668e22a80c0 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -59,7 +59,7 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_smi_events.o \ $(AMDKFD_PATH)/kfd_crat.o \ $(AMDKFD_PATH)/kfd_peerdirect.o \ - $(AMDKFD_PATH)/kfd_ipc.o \ + $(AMDKFD_PATH)/kfd_ipc.o \ $(AMDKFD_PATH)/kfd_trace.o \ $(AMDKFD_PATH)/kfd_spm.o \ $(AMDKFD_PATH)/kfd_debug.o diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 00a2a96acd5e9..a61a59953b671 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1751,17 +1751,17 @@ static int kfd_ioctl_export_dmabuf(struct file *filep, /* Place holder for deprecated DBG API */ static int kfd_ioctl_dbg_set_debug_trap_deprecated(struct file *filep, - struct kfd_process *p, void *data) + struct kfd_process *p, void *data) { - dev_dbg(kfd_device, "AMDKFD_IOC_DBG_TRAP is deprecated.\n"); - return -EINVAL; + dev_dbg(kfd_device, "AMDKFD_IOC_DBG_TRAP is deprecated.\n"); + return -EINVAL; } /* Place holder for deprecated CMA API */ static int kfd_ioctl_cross_memory_copy_deprecated(struct file *filep, - struct kfd_process *local_p, void *data) { - dev_dbg(kfd_device, "AMDKFD_IOC_CROSS_MEMORY_COPY is deprecated.\n"); - return -EINVAL; + struct kfd_process *local_p, void *data) { + dev_dbg(kfd_device, "AMDKFD_IOC_CROSS_MEMORY_COPY is deprecated.\n"); + return -EINVAL; } /* Handle requests for watching SMI events */ @@ -3469,8 +3469,8 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_IPC_EXPORT_HANDLE, kfd_ioctl_ipc_export_handle, 0), - AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP_DEPRECATED, - kfd_ioctl_dbg_set_debug_trap_deprecated, 0), + AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP_DEPRECATED, + kfd_ioctl_dbg_set_debug_trap_deprecated, 0), AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, kfd_ioctl_rlc_spm, 0), From 7a406eac89f0d999482adf4ce5e4ae7760e002c7 Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Wed, 23 Aug 2023 10:32:16 +0800 Subject: [PATCH 1110/2653] drm/amd/pm: workaround for the wrong ac power detection on smu 13.0.0 Workaround for the wrong ac power detection on smu 13.0.0. This is a temporary solution and will be dropped in the future. Signed-off-by: Kenneth Feng Reviewed-by: Evan Quan Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 +-- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1 - 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 1a1f2a6b2e521..19628827f15a0 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -1002,8 +1002,7 @@ static int smu_v13_0_process_pending_interrupt(struct smu_context *smu) { int ret = 0; - if (smu->dc_controlled_by_gpio && - smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) ret = smu_v13_0_allow_ih_interrupt(smu); return ret; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index e084ed99ec0e9..7902fc4cd3bc5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -3268,7 +3268,6 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost, .get_power_limit = smu_v13_0_0_get_power_limit, .set_power_limit = smu_v13_0_0_set_power_limit, - .set_power_source = smu_v13_0_set_power_source, .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode, .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode, .run_btc = smu_v13_0_run_btc, From aa2867fd5ef6c645ac6969b23724b5370cbff5bd Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 16 Aug 2023 10:12:07 +0800 Subject: [PATCH 1111/2653] drm/amdkcl: drop the direct call for AC_KERNEL_CHECK_SYMBOL_EXPORT [why] To support distros systems, AC_KERNEL_CHECK_SYMBOL_EXPORT create symbol config entry by parsing Modules.symvers. But Modules.symvers is unavailable for intree build, so that the AC_KERNEL_CHECK_SYMBOL_EXPORT is invalid. [how] The AC_KERNEL_TRY_COMPILE_SYMBOL adds function signatures check base on AC_KERNEL_CHECK_SYMBOL_EXPORT. So modify all of AC_KERNEL_CHECK_SYMBOL_EXPORT to AC_KERNEL_TRY_COMPILE_SYMBOL and conduct function signatures check for all symbol config entries to support intree build. Signed-off-by: Bob Zhou Reviewed-by: Tim Huang --- .../dkms/m4/__drm_atomic_helper_crtc_reset.m4 | 8 ++- .../drm/amd/dkms/m4/__kthread-should-park.m4 | 6 +- .../dkms/m4/acpi_dev_get_first_match_dev.m4 | 7 +- .../drm/amd/dkms/m4/amd-iommu-pc-supported.m4 | 7 +- drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 | 7 +- .../gpu/drm/amd/dkms/m4/down-read-killable.m4 | 11 ++-- ...nector-set-panel-orientation-with-quirk.m4 | 9 ++- .../gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 | 11 ++-- ...omic_helper_calc_timestamping_constants.m4 | 7 +- .../dkms/m4/drm_helper_force_disable_all.m4 | 6 +- ...rm_mode_create_hdmi_colorspace_property.m4 | 8 ++- drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 | 9 ++- drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 | 7 +- .../drm/amd/dkms/m4/drm_simple_kms_helper.m4 | 8 ++- .../drm/amd/dkms/m4/get-user-pages-remote.m4 | 66 +++++++++---------- .../drm/amd/dkms/m4/i2c_new_client_device.m4 | 7 +- .../gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 | 6 +- .../drm/amd/dkms/m4/kallsyms-lookup-name.m4 | 8 ++- drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 | 6 +- .../gpu/drm/amd/dkms/m4/pci_pr3_present.m4 | 6 +- drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 | 7 +- .../gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 | 7 +- .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 10 +-- .../drm/amd/dkms/m4/synchronize-shrinkers.m4 | 11 ++-- drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 | 11 ++-- .../drm/amd/dkms/m4/zone_device_page_init.m4 | 9 ++- 26 files changed, 169 insertions(+), 96 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 b/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 index 637a0bc453cd7..532031624b3a1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 @@ -4,9 +4,11 @@ dnl # drm/atomic: Create __drm_atomic_helper_crtc_reset() for subclassing crtc_s dnl # AC_DEFUN([AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([__drm_atomic_helper_crtc_reset], - [drivers/gpu/drm/drm_atomic_state_helper.c], - [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + __drm_atomic_helper_crtc_reset(NULL, NULL); + ],[__drm_atomic_helper_crtc_reset], [drivers/gpu/drm/drm_atomic_state_helper.c],[ AC_DEFINE(HAVE___DRM_ATOMIC_HELPER_CRTC_RESET, 1, [__drm_atomic_helper_crtc_reset() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/__kthread-should-park.m4 b/drivers/gpu/drm/amd/dkms/m4/__kthread-should-park.m4 index 2cb67699eef67..e4b111dff02e1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/__kthread-should-park.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/__kthread-should-park.m4 @@ -4,7 +4,11 @@ dnl # kthread: Add __kthread_should_park() dnl # AC_DEFUN([AC_AMDGPU___KTHREAD_SHOULD_PARK], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([__kthread_should_park],[kernel/kthread.c],[ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + __kthread_should_park(NULL); + ],[__kthread_should_park],[kernel/kthread.c],[ AC_DEFINE(HAVE___KTHREAD_SHOULD_PARK, 1, [__kthread_should_park() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 index f83c2733ac2e1..5668a2d728b89 100644 --- a/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 @@ -4,8 +4,11 @@ dnl # ACPI / utils: Introduce acpi_dev_get_first_match_dev() helper dnl # AC_DEFUN([AC_AMDGPU_ACPI_DEV_GET_FIRST_MATCH_DEV], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([acpi_dev_get_first_match_dev], - [drivers/acpi/utils.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + acpi_dev_get_first_match_dev(NULL, NULL, 0); + ],[acpi_dev_get_first_match_dev],[drivers/acpi/utils.c], [ AC_DEFINE(HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV, 1, [acpi_dev_get_first_match_dev() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 b/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 index 67cbbec8cac3e..c42fcb583b362 100644 --- a/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 @@ -12,8 +12,11 @@ AC_DEFUN([AC_AMDGPU_AMD_IOMMU_PC_GET_MAX_BANKS], [ AC_DEFINE(HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED, 1, [amd_iommu_pc_get_max_banks() declared]) ], [ - AC_KERNEL_CHECK_SYMBOL_EXPORT([get_amd_iommu], - [drivers/iommu/amd/init.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + get_amd_iommu(0); + ],[get_amd_iommu],[drivers/iommu/amd/init.c], [ AC_DEFINE(HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_UINT, 1, [amd_iommu_pc_get_max_banks() arg is unsigned int]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 b/drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 index 3f4be7129b920..29b066233e0d4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 @@ -4,8 +4,11 @@ dnl # debugfs: Provide a file creation function dnl # that also takes an initial size AC_DEFUN([AC_AMDGPU_DEBUGFS_CREATE_FILE_SIZE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([debugfs_create_file_size], - [fs/debugfs/inode.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + debugfs_create_file_size(NULL, 0, NULL, NULL, NULL, 0); + ],[debugfs_create_file_size], [fs/debugfs/inode.c], [ AC_DEFINE(HAVE_DEBUGFS_CREATE_FILE_SIZE, 1, [debugfs_create_file_size() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 b/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 index 6de71b3c0a40d..7a74bd4d25889 100644 --- a/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 @@ -4,10 +4,13 @@ #dnl AC_DEFUN([AC_AMDGPU_DOWN_READ_KILLABLE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT( - [down_read_killable], - [kernel/locking/rwsem.c], - [AC_DEFINE(HAVE_DOWN_READ_KILLABLE, 1, + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + int ret; + ret = down_read_killable(NULL); + ],[down_read_killable], [kernel/locking/rwsem.c],[ + AC_DEFINE(HAVE_DOWN_READ_KILLABLE, 1, [down_read_killable() is available])] ) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 index 463767cb7e3a6..0ae5de382dec8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 @@ -3,9 +3,12 @@ dnl # commit v5.5-rc2-1360-g69654c632d80 dnl # drm/connector: Split out orientation quirk detection (v2) dnl # AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_connector_set_panel_orientation_with_quirk], - [drivers/gpu/drm/drm_connector.c], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_connector_set_panel_orientation_with_quirk(NULL, 0, 0, 0); + ],[drm_connector_set_panel_orientation_with_quirk], [drivers/gpu/drm/drm_connector.c], [ AC_DEFINE(HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK, 1, [drm_connector_set_panel_orientation_with_quirk() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 index c4d2a03ec81c0..36c0a786c849f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 @@ -13,10 +13,13 @@ AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_PUT], [ AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT, 1, [drm_gem_object_put() is available]) - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_gem_object_put], - [drivers/gpu/drm/drm_gem.c], [ - AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_SYMBOL, 1, - [drm_gem_object_put() is exported]) + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_gem_object_put(NULL); + ],[drm_gem_object_put],[drivers/gpu/drm/drm_gem.c], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_SYMBOL, 1, + [drm_gem_object_put() is exported]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 index 79ab39b5802f3..7b6d31518fe3c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 @@ -4,8 +4,11 @@ dnl # Extract drm_atomic_helper_calc_timestamping_constants() dnl # AC_DEFUN([AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_atomic_helper_calc_timestamping_constants], - [drivers/gpu/drm/drm_atomic_helper.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_atomic_helper_calc_timestamping_constants(NULL); + ],[drm_atomic_helper_calc_timestamping_constants], [drivers/gpu/drm/drm_atomic_helper.c], [ AC_DEFINE(HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS, 1, [drm_atomic_helper_calc_timestamping_constants() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 index f52b3c10ccd43..69513e0cacc39 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 @@ -7,7 +7,11 @@ dnl # drm: Move the legacy kms disable_all helper to crtc helpers dnl # AC_DEFUN([AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_helper_force_disable_all], [drivers/gpu/drm/drm_crtc_helper.c],[ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_helper_force_disable_all(NULL); + ],[drm_helper_force_disable_all], [drivers/gpu/drm/drm_crtc_helper.c],[ AC_DEFINE(HAVE_DRM_HELPER_FORCE_DISABLE_ALL, 1, [drm_helper_force_disable_all() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 index 7a8fe049ac51b..ecc33db72dcbd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 @@ -4,8 +4,12 @@ dnl # drm: Rename HDMI colorspace property creation function dnl # AC_DEFUN([AC_AMDGPU_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_connector_attach_colorspace_property], [drivers/gpu/drm/drm_connector.c], [ - AC_DEFINE(HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY, 1, + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_connector_attach_colorspace_property(NULL); + ],[drm_connector_attach_colorspace_property], [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY, 1, [drm_connector_attach_colorspace_property() is available]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 index 4a1160753c960..bae97886408be 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 @@ -4,8 +4,13 @@ dnl # drm/prime: split array import functions v4 dnl # AC_DEFUN([AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_prime_sg_to_dma_addr_array], [drivers/gpu/drm/drm_prime.c], [ - AC_DEFINE(HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY, 1, [drm_prime_sg_to_dma_addr_array() is available]) + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_prime_sg_to_dma_addr_array(NULL, NULL, 0); + ],[drm_prime_sg_to_dma_addr_array], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY, 1, + [drm_prime_sg_to_dma_addr_array() is available]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 index 62209f24b90e0..fb7266321075c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 @@ -16,8 +16,11 @@ AC_DEFUN([AC_AMDGPU_DRM_PRINT_BITS], [ ], [ dnl # v5.3-rc1-622-g2dc5d44ccc5e dnl # drm: add drm_print_bits - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_print_bits], - [drivers/gpu/drm/drm_print.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_print_bits(NULL, 0, NULL, 0, 0); + ],[drm_print_bits], [drivers/gpu/drm/drm_print.c], [ AC_DEFINE(HAVE_DRM_PRINT_BITS, 1, [drm_print_bits() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 index 0ffcd218e5a99..7f8cf4e9ad0a1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 @@ -3,9 +3,11 @@ dnl # v5.6-rc2-359-g63170ac6f2e8 dnl # drm/simple-kms: Add drm_simple_encoder_{init,create}() dnl # AC_DEFUN([AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT], [ - AC_KERNEL_CHECK_SYMBOL_EXPORT( - [drm_simple_encoder_init], - [drivers/gpu/drm/drm_simple_kms_helper.c],[ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_simple_encoder_init(NULL, NULL, 0); + ],[drm_simple_encoder_init], [drivers/gpu/drm/drm_simple_kms_helper.c],[ AC_DEFINE(HAVE_DRM_SIMPLE_ENCODER_INIT, 1, [drm_simple_encoder is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 index 8f70124da00f0..e2fe781b7d7dc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 @@ -1,53 +1,47 @@ AC_DEFUN([AC_AMDGPU_GET_USER_PAGES_REMOTE], [ AC_KERNEL_DO_BACKGROUND([ dnl # - dnl # v4.5-rc4-71-g1e9877902dc7 - dnl # mm/gup: Introduce get_user_pages_remote() + dnl # v5.8-12463-g64019a2e467a + dnl # mm/gup: remove task_struct pointer for all gup code dnl # - AC_KERNEL_CHECK_SYMBOL_EXPORT([get_user_pages_remote],[mm/gup.c], - [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages_remote(NULL, 0, 0, 0, NULL, NULL, NULL); + ], [get_user_pages_remote],[mm/gup.c],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT, 1, + [get_user_pages_remote() remove task_struct pointer]) + ], [ dnl # - dnl # v5.8-12463-g64019a2e467a - dnl # mm/gup: remove task_struct pointer for all gup code + dnl # commit v4.9-7744-g5b56d49fc31d + dnl # mm: add locked parameter to get_user_pages_remote() dnl # - AC_KERNEL_TRY_COMPILE([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ #include ], [ - get_user_pages_remote(NULL, 0, 0, 0, NULL, NULL, NULL); - ], [ - AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT, 1, - [get_user_pages_remote() remove task_struct pointer]) - ], [ + get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL, NULL); + ], [get_user_pages_remote],[mm/gup.c],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_LOCKED, 1, + [get_user_pages_remote() wants locked parameter]) + ],[ dnl # - dnl # commit v4.9-7744-g5b56d49fc31d - dnl # mm: add locked parameter to get_user_pages_remote() + dnl # commit v4.8-14096-g9beae1ea8930 + dnl # mm: replace get_user_pages_remote() write/force parameters + dnl # with gup_flags dnl # - AC_KERNEL_TRY_COMPILE([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ #include ], [ - get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL, NULL); - ], [ - AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_LOCKED, 1, - [get_user_pages_remote() wants locked parameter]) - ], [ - dnl # - dnl # commit v4.8-14096-g9beae1ea8930 - dnl # mm: replace get_user_pages_remote() write/force parameters - dnl # with gup_flags - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL); - ], [ - AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS, 1, - [get_user_pages_remote() wants gup_flags parameter]) - ],[ - AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED, 1, - [get_user_pages_remote() is introduced with initial prototype]) - ]) + get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL); + ], [get_user_pages_remote],[mm/gup.c],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS, 1, + [get_user_pages_remote() wants gup_flags parameter]) + ],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED, 1, + [get_user_pages_remote() is introduced with initial prototype]) ]) ]) ]) ]) ]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 b/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 index cedd29e0fe70e..a4d3e37bfa38c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 @@ -4,8 +4,11 @@ dnl # i2c: core: improve return value handling of i2c_new_device and i2c_new_dum dnl # AC_DEFUN([AC_AMDGPU_I2C_NEW_CLIENT_DEVICE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([i2c_new_client_device], [drivers/i2c/i2c-core-base.c], - [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + i2c_new_client_device(NULL, NULL); + ],[i2c_new_client_device], [drivers/i2c/i2c-core-base.c],[ AC_DEFINE(HAVE_I2C_NEW_CLIENT_DEVICE, 1, [i2c_new_client_device() is enabled]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 b/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 index e44504998e830..29cc9b9271330 100644 --- a/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 @@ -4,7 +4,11 @@ dnl # time: Introduce jiffies64_to_msecs() dnl # AC_DEFUN([AC_AMDGPU_JIFFIES64_TO_MSECS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([jiffies64_to_msecs], [kernel/time/time.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + jiffies64_to_msecs(0); + ],[jiffies64_to_msecs], [kernel/time/time.c], [ AC_DEFINE(HAVE_JIFFIES64_TO_MSECS, 1, [jiffies64_to_msecs() is available]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 b/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 index 62e540f41a7df..4e123cddf2838 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 @@ -4,9 +4,11 @@ dnl # v2.6.32-rc4-272-gf60d24d2ad04 hw-breakpoints: Fix broken hw-breakpoint sam dnl # AC_DEFUN([AC_AMDGPU_KALLSYMS_LOOKUP_NAME], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([kallsyms_lookup_name], - [kernel/kallsyms.c], - [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + kallsyms_lookup_name(NULL); + ],[kallsyms_lookup_name],[kernel/kallsyms.c],[ AC_DEFINE(HAVE_KALLSYMS_LOOKUP_NAME, 1, [kallsyms_lookup_name is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 b/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 index 2c8863597781f..bdfb1256a9ccb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 @@ -5,7 +5,11 @@ dnl # v4.6-6601-gec8d7c14ea14 mm, oom_reaper: do not mmput synchronously from th dnl # AC_DEFUN([AC_AMDGPU_MMPUT_ASYNC], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([mmput_async], [kernel/fork.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + mmput_async(NULL); + ],[mmput_async], [kernel/fork.c], [ AC_DEFINE(HAVE_MMPUT_ASYNC, 1, [mmput_async() is available]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 b/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 index 38e50b2c0766f..e0fbc073caf06 100644 --- a/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 @@ -4,7 +4,11 @@ dnl # PCI: Add a helper to check Power Resource Requirements _PR3 existence dnl # AC_DEFUN([AC_AMDGPU_PCI_PR3_PRESENT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([pci_pr3_present], [drivers/pci/pci.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + pci_pr3_present(NULL); + ],[pci_pr3_present], [drivers/pci/pci.c], [ AC_DEFINE(HAVE_PCI_PR3_PRESENT, 1, [pci_pr3_present() is available]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 b/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 index 35651096f8e2a..a69d9f2264f6c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 @@ -4,8 +4,11 @@ dnl # virtio-mem: Allow to specify an ACPI PXM as nid dnl # AC_DEFUN([AC_AMDGPU_PXM_TO_NODE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([pxm_to_node], - [drivers/acpi/numa/srat.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + pxm_to_node(0); + ],[pxm_to_node], [drivers/acpi/numa/srat.c], [ AC_DEFINE(HAVE_PXM_TO_NODE, 1, [pxm_to_node() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 b/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 index 422b5d833b653..6a7fdf55ded70 100644 --- a/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 @@ -4,8 +4,11 @@ dnl # sched: Provide sched_set_fifo() dnl # AC_DEFUN([AC_AMDGPU_SCHED_SET_FIFO_LOW], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([sched_set_fifo_low], - [kernel/sched/core.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + sched_set_fifo_low(NULL); + ], [sched_set_fifo_low], [kernel/sched/core.c], [ AC_DEFINE(HAVE_SCHED_SET_FIFO_LOW, 1, [sched_set_fifo_low() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 8ad24bc40f5fb..6b53674fb88bc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -23,12 +23,14 @@ dnl # dnl # v5.10-1961-g6ca2ab8086af drm: automatic legacy gamma support dnl # AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL], [ - AC_KERNEL_CHECK_SYMBOL_EXPORT( - [drm_atomic_helper_legacy_gamma_set], [drivers/gpu/drm/drm_atomic_helper.c], [], - [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_atomic_helper_legacy_gamma_set(NULL, NULL, NULL, NULL, 0, NULL); + ], [drm_atomic_helper_legacy_gamma_set], [drivers/gpu/drm/drm_atomic_helper.c],[],[ AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL, 1, [HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available]) - ]) + ]) ]) AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 index 3abf21e7f2b67..3033e4be5a17c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 @@ -4,10 +4,13 @@ dnl # mm/vmscan: add sync_shrinkers function v3 dnl # AC_DEFUN([AC_AMDGPU_SYNCHRONIZE_SHRINKERS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([synchronize_shrinkers], - [mm/vmscan.c], [ - AC_DEFINE(HAVE_SYNCHRONIZE_SHRINKERS, 1, - [synchronize_shrinkers() is available]) + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + synchronize_shrinkers(); + ], [synchronize_shrinkers], [mm/vmscan.c], [ + AC_DEFINE(HAVE_SYNCHRONIZE_SHRINKERS, 1, + [synchronize_shrinkers() is available]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 index c1dc1717cc324..7c355cae6ed01 100644 --- a/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 @@ -4,13 +4,14 @@ dnl # sysfs: Add sysfs_emit and sysfs_emit_at dnl # to format sysfs output AC_DEFUN([AC_AMDGPU_SYSFS_EMIT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([sysfs_emit sysfs_emit_at], - [fs/sysfs/file.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + sysfs_emit(NULL, NULL); + sysfs_emit_at(NULL, 0, NULL); + ],[sysfs_emit sysfs_emit_at],[fs/sysfs/file.c], [ AC_DEFINE(HAVE_SYSFS_EMIT, 1, [sysfs_emit() and sysfs_emit_at() are available]) ]) ]) ]) - - -) diff --git a/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 b/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 index d73aab950a652..56eaeb4b6d888 100644 --- a/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 @@ -5,8 +5,13 @@ dnl # v5.17-rc4-75-g27674ef6c73f mm: remove the extra ZONE_DEVICE struct page re dnl # AC_DEFUN([AC_AMDGPU_ZONE_DEVICE_PAGE_INIT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([zone_device_page_init], [mm/memremap.c], [ - AC_DEFINE(HAVE_ZONE_DEVICE_PAGE_INIT, 1, [zone_device_page_init() is available]) + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + zone_device_page_init(NULL); + ], [zone_device_page_init], [mm/memremap.c], [ + AC_DEFINE(HAVE_ZONE_DEVICE_PAGE_INIT, 1, + [zone_device_page_init() is available]) ]) ]) ]) From 69ad946c1153caf74bf522ff643fcfdbcfc7de88 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 21 Aug 2023 17:47:36 +0800 Subject: [PATCH 1112/2653] drm/amdkcl: fix m4 include for HAVE_SYNCHRONIZE_SHRINKERS To support difference version shrinkers.h in distro systems, including mmzone.h header file make m4 script detect success. Signed-off-by: Bob Zhou Reviewed-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 index 3033e4be5a17c..9429112a66d2b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 @@ -5,6 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_SYNCHRONIZE_SHRINKERS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include #include ], [ synchronize_shrinkers(); From 12e68267f989bd323d28b0f0e82d85727b6b7a3c Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Aug 2023 17:59:02 +0800 Subject: [PATCH 1113/2653] drm/amdkcl: Include kcl_rbtree.h in the backport.h Include kcl_rbtree.h in the backport.h instead of gpu_scheduler.h Signed-off-by: Ma Jun Reviewed-by: Flora Cui --- drivers/gpu/drm/scheduler/backport/backport.h | 2 +- include/drm/gpu_scheduler.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 25460de490b35..8b9c265bf8bce 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -8,5 +8,5 @@ #include #include #include - +#include #endif diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h index d487fda4e7fa2..daba51a67ad4c 100644 --- a/include/drm/gpu_scheduler.h +++ b/include/drm/gpu_scheduler.h @@ -29,7 +29,6 @@ #include #include #include -#include #define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000) From 86d94665005020b1477eca1a45d5f889cf2e56a8 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 28 Aug 2023 11:23:40 +0800 Subject: [PATCH 1114/2653] drm/amdkcl: update include sequence for kcl_rbtree.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit the kcl_amdgpu_drm_fb_helper.h should includes kcl_rbtree.h to avoid the below issue about struct lack. In file included from /var/lib/dkms/amdgpu-pro/1.0/build/amd/amdgpu/amdgpu_ring.h:28:0, from /var/lib/dkms/amdgpu-pro/1.0/build/amd/amdgpu/amdgpu_ctx.h:29, from /var/lib/dkms/amdgpu-pro/1.0/build/amd/amdgpu/amdgpu.h:43, from /var/lib/dkms/amdgpu-pro/1.0/build/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h:36, from /var/lib/dkms/amdgpu-pro/1.0/build/amd/backport/backport.h:69, from :0: /var/lib/dkms/amdgpu-pro/1.0/build/include/drm/gpu_scheduler.h:262:25: error: field ‘rb_tree_root’ has incomplete type struct rb_root_cached rb_tree_root; Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- .../gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h index 5abb5cf97824c..8c75bfc4e993b 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -33,6 +33,7 @@ #include #include #include +#include #include "amdgpu.h" #ifndef HAVE_DRM_FB_HELPER_LASTCLOSE From f22dc829375cc8f592f54e5135cef734c5b08ba8 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 25 Aug 2023 11:29:55 +0800 Subject: [PATCH 1115/2653] drm/amdkcl: change the order of the judgment for mem_type To avoid the following Null pointer dereference error, change the order of the judgment for old_mem->mem_type Signed-off-by: Asher Song Acked-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index ae20966fc21ab..ecefd544ee033 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -532,10 +532,6 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, abo = ttm_to_amdgpu_bo(bo); - if (old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA || - old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA_IMPORT) - return -EINVAL; - adev = amdgpu_ttm_adev(bo->bdev); if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM && @@ -544,6 +540,10 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, ttm_bo_move_null(bo, new_mem); return 0; } + if (old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA || + old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA_IMPORT) + return -EINVAL; + if (old_mem->mem_type == TTM_PL_SYSTEM && (new_mem->mem_type == TTM_PL_TT || new_mem->mem_type == AMDGPU_PL_PREEMPT)) { From 7e865c93246917be4251b3620e3f6e915e939d37 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 13 Sep 2023 14:57:49 +0800 Subject: [PATCH 1116/2653] drm/amdkcl: fake drm_show_fdinfo It's caused v6.4-rc1-190-g3f09a0cd4ea3 drm: Add common fdinfo helper Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 + drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c | 68 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/dkms/m4/drm-show-fdinfo.m4 | 37 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_file.h | 8 +++ 7 files changed, 118 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-show-fdinfo.m4 create mode 100644 include/kcl/kcl_drm_file.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index b280f5452a63e..22a6fedb8e103 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3150,9 +3150,11 @@ static struct drm_driver amdgpu_kms_driver = { DRM_FBDEV_TTM_DRIVER_OPS, .fops = &amdgpu_driver_kms_fops, .release = &amdgpu_driver_release_kms, +#ifdef HAVE_DRM_DRIVER_SHOW_FDINFO #ifdef CONFIG_PROC_FS .show_fdinfo = amdgpu_show_fdinfo, #endif +#endif #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK .gem_prime_export = amdgpu_gem_prime_export, diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index f8e0cdb1dd258..bd294b351ebe7 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o kcl_drm_suballoc.o + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c new file mode 100644 index 0000000000000..7ddc32cafc5b7 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c @@ -0,0 +1,68 @@ +/* + * \author Rickard E. (Rik) Faith + * \author Daryll Strauss + * \author Gareth Hughes + */ + +/* + * Created: Mon Jan 4 08:58:31 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include +#include +#include +#ifndef HAVE_DRM_SHOW_FDINFO +/** + * drm_show_fdinfo - helper for drm file fops + * @m: output stream + * @f: the device file instance + * + * Helper to implement fdinfo, for userspace to query usage stats, etc, of a + * process using the GPU. See also &drm_driver.show_fdinfo. + * + * For text output format description please see Documentation/gpu/drm-usage-stats.rst + */ +void drm_show_fdinfo(struct seq_file *m, struct file *f) +{ + struct drm_file *file = f->private_data; + struct drm_device *dev = file->minor->dev; + struct drm_printer p = drm_seq_file_printer(m); + + drm_printf(&p, "drm-driver:\t%s\n", dev->driver->name); + + if (dev_is_pci(dev->dev)) { + struct pci_dev *pdev = to_pci_dev(dev->dev); + + drm_printf(&p, "drm-pdev:\t%04x:%02x:%02x.%d\n", + pci_domain_nr(pdev->bus), pdev->bus->number, + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); + } +} +EXPORT_SYMBOL(drm_show_fdinfo); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 0f775ed076173..27819f54eea30 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -111,4 +111,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-show-fdinfo.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-show-fdinfo.m4 new file mode 100644 index 0000000000000..a144bfa3967d4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-show-fdinfo.m4 @@ -0,0 +1,37 @@ +dnl # +dnl # v6.4-rc1-190-g3f09a0cd4ea3:drm: Add common fdinfo helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FILE_DRM_SHOW_FDINFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_show_fdinfo(NULL, NULL); + ],[drm_show_fdinfo], [drivers/gpu/drm/drm_file.c], [ + AC_DEFINE(HAVE_DRM_SHOW_FDINFO, 1, [drm_show_fdinfo() is available]) + ]) + ]) +]) + +dnl # +dnl # v6.4-rc1-190-g3f09a0cd4ea3:drm: Add common fdinfo helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_SHOW_FDINFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_driver *drm_driver = NULL; + + drm_driver->show_fdinfo(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DRIVER_SHOW_FDINFO, 1, + [drm_driver->show_fdinfo() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_SHOW_FDINFO], [ + AC_AMDGPU_DRM_FILE_DRM_SHOW_FDINFO + AC_AMDGPU_DRM_DRIVER_SHOW_FDINFO +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b096d25b6e94d..e724745eb5d98 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -208,6 +208,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED AC_AMDGPU_PID_TYPE AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE + AC_AMDGPU_DRM_SHOW_FDINFO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_file.h b/include/kcl/kcl_drm_file.h new file mode 100644 index 0000000000000..d23292e37dc25 --- /dev/null +++ b/include/kcl/kcl_drm_file.h @@ -0,0 +1,8 @@ +#ifndef __AMDKCL_KCL_DRM_DRV_H__ +#define __AMDKCL_KCL_DRM_DRV_H__ +#include + +#ifndef HAVE_DRM_SHOW_FDINFO +void drm_show_fdinfo(struct seq_file *m, struct file *f); +#endif +#endif From 7333811bf6ffe63776cbbf81c727e1c9fba74309 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 18 Sep 2023 17:03:05 +0800 Subject: [PATCH 1117/2653] drm/amdkcl: fake drm_exec_* It's caused by v6.4-rc7-2018-g09593216bff1 drm: execution context for GEM buffers v7 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c | 334 +++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 7 + include/kcl/header/drm/drm_exec.h | 9 + include/kcl/kcl_drm_exec.h | 124 ++++++++ 6 files changed, 476 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c create mode 100644 include/kcl/header/drm/drm_exec.h create mode 100644 include/kcl/kcl_drm_exec.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index bd294b351ebe7..f1367b6447788 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o kcl_drm_exec.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c new file mode 100644 index 0000000000000..8fc292da898b0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c @@ -0,0 +1,334 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT + +#include +#include +#include +#include + +#ifndef HAVE_DRM_DRM_EXEC_H +/** + * DOC: Overview + * + * This component mainly abstracts the retry loop necessary for locking + * multiple GEM objects while preparing hardware operations (e.g. command + * submissions, page table updates etc..). + * + * If a contention is detected while locking a GEM object the cleanup procedure + * unlocks all previously locked GEM objects and locks the contended one first + * before locking any further objects. + * + * After an object is locked fences slots can optionally be reserved on the + * dma_resv object inside the GEM object. + * + * A typical usage pattern should look like this:: + * + * struct drm_gem_object *obj; + * struct drm_exec exec; + * unsigned long index; + * int ret; + * + * drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT); + * drm_exec_until_all_locked(&exec) { + * ret = drm_exec_prepare_obj(&exec, boA, 1); + * drm_exec_retry_on_contention(&exec); + * if (ret) + * goto error; + * + * ret = drm_exec_prepare_obj(&exec, boB, 1); + * drm_exec_retry_on_contention(&exec); + * if (ret) + * goto error; + * } + * + * drm_exec_for_each_locked_object(&exec, index, obj) { + * dma_resv_add_fence(obj->resv, fence, DMA_RESV_USAGE_READ); + * ... + * } + * drm_exec_fini(&exec); + * + * See struct dma_exec for more details. + */ + +/* Dummy value used to initially enter the retry loop */ +#define DRM_EXEC_DUMMY ((void *)~0) + +/* Unlock all objects and drop references */ +static void drm_exec_unlock_all(struct drm_exec *exec) +{ + struct drm_gem_object *obj; + unsigned long index; + + drm_exec_for_each_locked_object(exec, index, obj) { + dma_resv_unlock(obj->resv); + drm_gem_object_put(obj); + } + + drm_gem_object_put(exec->prelocked); + exec->prelocked = NULL; +} + +/** + * drm_exec_init - initialize a drm_exec object + * @exec: the drm_exec object to initialize + * @flags: controls locking behavior, see DRM_EXEC_* defines + * + * Initialize the object and make sure that we can track locked objects. + */ +void drm_exec_init(struct drm_exec *exec, uint32_t flags) +{ + exec->flags = flags; + exec->objects = kmalloc(PAGE_SIZE, GFP_KERNEL); + + /* If allocation here fails, just delay that till the first use */ + exec->max_objects = exec->objects ? PAGE_SIZE / sizeof(void *) : 0; + exec->num_objects = 0; + exec->contended = DRM_EXEC_DUMMY; + exec->prelocked = NULL; +} +EXPORT_SYMBOL(drm_exec_init); + +/** + * drm_exec_fini - finalize a drm_exec object + * @exec: the drm_exec object to finalize + * + * Unlock all locked objects, drop the references to objects and free all memory + * used for tracking the state. + */ +void drm_exec_fini(struct drm_exec *exec) +{ + drm_exec_unlock_all(exec); + kvfree(exec->objects); + if (exec->contended != DRM_EXEC_DUMMY) { + drm_gem_object_put(exec->contended); + ww_acquire_fini(&exec->ticket); + } +} +EXPORT_SYMBOL(drm_exec_fini); + +/** + * drm_exec_cleanup - cleanup when contention is detected + * @exec: the drm_exec object to cleanup + * + * Cleanup the current state and return true if we should stay inside the retry + * loop, false if there wasn't any contention detected and we can keep the + * objects locked. + */ +bool drm_exec_cleanup(struct drm_exec *exec) +{ + if (likely(!exec->contended)) { + ww_acquire_done(&exec->ticket); + return false; + } + + if (likely(exec->contended == DRM_EXEC_DUMMY)) { + exec->contended = NULL; + ww_acquire_init(&exec->ticket, &reservation_ww_class); + return true; + } + + drm_exec_unlock_all(exec); + exec->num_objects = 0; + return true; +} +EXPORT_SYMBOL(drm_exec_cleanup); + +/* Track the locked object in the array */ +static int drm_exec_obj_locked(struct drm_exec *exec, + struct drm_gem_object *obj) +{ + if (unlikely(exec->num_objects == exec->max_objects)) { + size_t size = exec->max_objects * sizeof(void *); + void *tmp; + + tmp = kvrealloc(exec->objects, size, size + PAGE_SIZE, + GFP_KERNEL); + if (!tmp) + return -ENOMEM; + + exec->objects = tmp; + exec->max_objects += PAGE_SIZE / sizeof(void *); + } + drm_gem_object_get(obj); + exec->objects[exec->num_objects++] = obj; + + return 0; +} + +/* Make sure the contended object is locked first */ +static int drm_exec_lock_contended(struct drm_exec *exec) +{ + struct drm_gem_object *obj = exec->contended; + int ret; + + if (likely(!obj)) + return 0; + + /* Always cleanup the contention so that error handling can kick in */ + exec->contended = NULL; + if (exec->flags & DRM_EXEC_INTERRUPTIBLE_WAIT) { + ret = dma_resv_lock_slow_interruptible(obj->resv, + &exec->ticket); + if (unlikely(ret)) + goto error_dropref; + } else { + dma_resv_lock_slow(obj->resv, &exec->ticket); + } + + ret = drm_exec_obj_locked(exec, obj); + if (unlikely(ret)) + goto error_unlock; + + exec->prelocked = obj; + return 0; + +error_unlock: + dma_resv_unlock(obj->resv); + +error_dropref: + drm_gem_object_put(obj); + return ret; +} + +/** + * drm_exec_lock_obj - lock a GEM object for use + * @exec: the drm_exec object with the state + * @obj: the GEM object to lock + * + * Lock a GEM object for use and grab a reference to it. + * + * Returns: -EDEADLK if a contention is detected, -EALREADY when object is + * already locked (can be suppressed by setting the DRM_EXEC_IGNORE_DUPLICATES + * flag), -ENOMEM when memory allocation failed and zero for success. + */ +int drm_exec_lock_obj(struct drm_exec *exec, struct drm_gem_object *obj) +{ + int ret; + + ret = drm_exec_lock_contended(exec); + if (unlikely(ret)) + return ret; + + if (exec->prelocked == obj) { + drm_gem_object_put(exec->prelocked); + exec->prelocked = NULL; + return 0; + } + + if (exec->flags & DRM_EXEC_INTERRUPTIBLE_WAIT) + ret = dma_resv_lock_interruptible(obj->resv, &exec->ticket); + else + ret = dma_resv_lock(obj->resv, &exec->ticket); + + if (unlikely(ret == -EDEADLK)) { + drm_gem_object_get(obj); + exec->contended = obj; + return -EDEADLK; + } + + if (unlikely(ret == -EALREADY) && + exec->flags & DRM_EXEC_IGNORE_DUPLICATES) + return 0; + + if (unlikely(ret)) + return ret; + + ret = drm_exec_obj_locked(exec, obj); + if (ret) + goto error_unlock; + + return 0; + +error_unlock: + dma_resv_unlock(obj->resv); + return ret; +} +EXPORT_SYMBOL(drm_exec_lock_obj); + +/** + * drm_exec_unlock_obj - unlock a GEM object in this exec context + * @exec: the drm_exec object with the state + * @obj: the GEM object to unlock + * + * Unlock the GEM object and remove it from the collection of locked objects. + * Should only be used to unlock the most recently locked objects. It's not time + * efficient to unlock objects locked long ago. + */ +void drm_exec_unlock_obj(struct drm_exec *exec, struct drm_gem_object *obj) +{ + unsigned int i; + + for (i = exec->num_objects; i--;) { + if (exec->objects[i] == obj) { + dma_resv_unlock(obj->resv); + for (++i; i < exec->num_objects; ++i) + exec->objects[i - 1] = exec->objects[i]; + --exec->num_objects; + drm_gem_object_put(obj); + return; + } + + } +} +EXPORT_SYMBOL(drm_exec_unlock_obj); + +/** + * drm_exec_prepare_obj - prepare a GEM object for use + * @exec: the drm_exec object with the state + * @obj: the GEM object to prepare + * @num_fences: how many fences to reserve + * + * Prepare a GEM object for use by locking it and reserving fence slots. + * + * Returns: -EDEADLK if a contention is detected, -EALREADY when object is + * already locked, -ENOMEM when memory allocation failed and zero for success. + */ +int drm_exec_prepare_obj(struct drm_exec *exec, struct drm_gem_object *obj, + unsigned int num_fences) +{ + int ret; + + ret = drm_exec_lock_obj(exec, obj); + if (ret) + return ret; + + ret = dma_resv_reserve_fences(obj->resv, num_fences); + if (ret) { + drm_exec_unlock_obj(exec, obj); + return ret; + } + + return 0; +} +EXPORT_SYMBOL(drm_exec_prepare_obj); + +/** + * drm_exec_prepare_array - helper to prepare an array of objects + * @exec: the drm_exec object with the state + * @objects: array of GEM object to prepare + * @num_objects: number of GEM objects in the array + * @num_fences: number of fences to reserve on each GEM object + * + * Prepares all GEM objects in an array, aborts on first error. + * Reserves @num_fences on each GEM object after locking it. + * + * Returns: -EDEADLOCK on contention, -EALREADY when object is already locked, + * -ENOMEM when memory allocation failed and zero for success. + */ +int drm_exec_prepare_array(struct drm_exec *exec, + struct drm_gem_object **objects, + unsigned int num_objects, + unsigned int num_fences) +{ + int ret; + + for (unsigned int i = 0; i < num_objects; ++i) { + ret = drm_exec_prepare_obj(exec, objects[i], num_fences); + if (unlikely(ret)) + return ret; + } + + return 0; +} +EXPORT_SYMBOL(drm_exec_prepare_array); + +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 27819f54eea30..1b3c7daede330 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -112,4 +112,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 38a64fd0deb08..76f76c549528a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -98,4 +98,11 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/suballoc: Extract amdgpu_sa.c as generic suballocation helper dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_suballoc.h]) + + dnl # + dnl # v6.4-rc7-2018-g09593216bff1 + dnl # drm: execution context for GEM buffers v7 + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_exec.h]) + ]) diff --git a/include/kcl/header/drm/drm_exec.h b/include/kcl/header/drm/drm_exec.h new file mode 100644 index 0000000000000..62aff24d17425 --- /dev/null +++ b/include/kcl/header/drm/drm_exec.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_EXEC_H_H_ +#define _KCL_HEADER_DRM_EXEC_H_H_ + +#ifdef HAVE_DRM_DRM_EXEC_H +#include_next +#endif + +#endif diff --git a/include/kcl/kcl_drm_exec.h b/include/kcl/kcl_drm_exec.h new file mode 100644 index 0000000000000..90cd2a6a4f1c8 --- /dev/null +++ b/include/kcl/kcl_drm_exec.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ + +#ifndef AMDKCL_DRM_EXEC_H +#define AMDKCL_DRM_EXEC_H + +#include +#include + +#ifndef HAVE_DRM_DRM_EXEC_H +#define DRM_EXEC_INTERRUPTIBLE_WAIT BIT(0) +#define DRM_EXEC_IGNORE_DUPLICATES BIT(1) + +struct drm_gem_object; + +/** + * struct drm_exec - Execution context + */ +struct drm_exec { + /** + * @flags: Flags to control locking behavior + */ + uint32_t flags; + + /** + * @ticket: WW ticket used for acquiring locks + */ + struct ww_acquire_ctx ticket; + + /** + * @num_objects: number of objects locked + */ + unsigned int num_objects; + + /** + * @max_objects: maximum objects in array + */ + unsigned int max_objects; + + /** + * @objects: array of the locked objects + */ + struct drm_gem_object **objects; + + /** + * @contended: contended GEM object we backed off for + */ + struct drm_gem_object *contended; + + /** + * @prelocked: already locked GEM object due to contention + */ + struct drm_gem_object *prelocked; +}; + +/** + * drm_exec_for_each_locked_object - iterate over all the locked objects + * @exec: drm_exec object + * @index: unsigned long index for the iteration + * @obj: the current GEM object + * + * Iterate over all the locked GEM objects inside the drm_exec object. + */ +#define drm_exec_for_each_locked_object(exec, index, obj) \ + for (index = 0, obj = (exec)->objects[0]; \ + index < (exec)->num_objects; \ + ++index, obj = (exec)->objects[index]) + +/** + * drm_exec_until_all_locked - loop until all GEM objects are locked + * @exec: drm_exec object + * + * Core functionality of the drm_exec object. Loops until all GEM objects are + * locked and no more contention exists. At the beginning of the loop it is + * guaranteed that no GEM object is locked. + * + * Since labels can't be defined local to the loops body we use a jump pointer + * to make sure that the retry is only used from within the loops body. + */ +#define drm_exec_until_all_locked(exec) \ +__PASTE(__drm_exec_, __LINE__): \ + for (void *__drm_exec_retry_ptr; ({ \ + __drm_exec_retry_ptr = &&__PASTE(__drm_exec_, __LINE__);\ + (void)__drm_exec_retry_ptr; \ + drm_exec_cleanup(exec); \ + });) + +/** + * drm_exec_retry_on_contention - restart the loop to grap all locks + * @exec: drm_exec object + * + * Control flow helper to continue when a contention was detected and we need to + * clean up and re-start the loop to prepare all GEM objects. + */ +#define drm_exec_retry_on_contention(exec) \ + do { \ + if (unlikely(drm_exec_is_contended(exec))) \ + goto *__drm_exec_retry_ptr; \ + } while (0) + +/** + * drm_exec_is_contended - check for contention + * @exec: drm_exec object + * + * Returns true if the drm_exec object has run into some contention while + * locking a GEM object and needs to clean up. + */ +static inline bool drm_exec_is_contended(struct drm_exec *exec) +{ + return !!exec->contended; +} + +void drm_exec_init(struct drm_exec *exec, uint32_t flags); +void drm_exec_fini(struct drm_exec *exec); +bool drm_exec_cleanup(struct drm_exec *exec); +int drm_exec_lock_obj(struct drm_exec *exec, struct drm_gem_object *obj); +void drm_exec_unlock_obj(struct drm_exec *exec, struct drm_gem_object *obj); +int drm_exec_prepare_obj(struct drm_exec *exec, struct drm_gem_object *obj, + unsigned int num_fences); +int drm_exec_prepare_array(struct drm_exec *exec, + struct drm_gem_object **objects, + unsigned int num_objects, + unsigned int num_fences); +#endif +#endif From 47c6bef1d5fec84be917a64a7893c6e8e9f27bbc Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 13 Sep 2023 17:38:41 +0800 Subject: [PATCH 1118/2653] drm/amdkcl: fake local64_try_cmpxchg It's caused by 8fc4fddaf9a184eea7da21290236a1764e608a01 locking/generic: Wire up local{,64}_try_cmpxchg() Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../amd/dkms/m4/atomic-long-try-cmpxchg.m4 | 37 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 + include/kcl/kcl_local64.h | 33 +++++++++++++++++ 4 files changed, 73 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/atomic-long-try-cmpxchg.m4 create mode 100644 include/kcl/kcl_local64.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1b3c7daede330..a11eebffea589 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -113,4 +113,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/atomic-long-try-cmpxchg.m4 b/drivers/gpu/drm/amd/dkms/m4/atomic-long-try-cmpxchg.m4 new file mode 100644 index 0000000000000..5d20db398bf97 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/atomic-long-try-cmpxchg.m4 @@ -0,0 +1,37 @@ +dnl # +dnl # v5.13-rc1-138-g67d1b0de258a locking/atomic: add arch_atomic_long*() +dnl # +AC_DEFUN([AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool t; + long r = 0; + t = atomic_long_try_cmpxchg(NULL, NULL, r); + ], [ + AC_DEFINE(HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG, 1, + [atomic_long_try_cmpxchg() is available]) + ]) + ]) +]) + +dnl # +dnl # v6.3-rc1-6-g8fc4fddaf9a1 +dnl # locking/generic: Wire up local{,64}_try_cmpxchg() +dnl # +AC_DEFUN([AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool t; + s64 r = 0; + local_t *l = NULL; + t = local_try_cmpxchg(l, NULL, r); + ], [ + AC_DEFINE(HAVE_LINUX_LOCAL_TRY_CMPXCHG, 1, + [local_try_cmpchg() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e724745eb5d98..9565c3fabab2c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -209,6 +209,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PID_TYPE AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE AC_AMDGPU_DRM_SHOW_FDINFO + AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG + AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_local64.h b/include/kcl/kcl_local64.h new file mode 100644 index 0000000000000..0b374fef81d85 --- /dev/null +++ b/include/kcl/kcl_local64.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_ASM_GENERIC_LOCAL64_H +#define AMDKCL_ASM_GENERIC_LOCAL64_H + +#include +#include +#include + +/* + * A signed long type for operations which are atomic for a single CPU. + * Usually used in combination with per-cpu variables. + * + * This is the default implementation, which uses atomic64_t. Which is + * rather pointless. The whole point behind local64_t is that some processors + * can perform atomic adds and subtracts in a manner which is atomic wrt IRQs + * running on this CPU. local64_t allows exploitation of such capabilities. + */ + +/* Implement in terms of atomics. */ + +#if !defined HAVE_LINUX_LOCAL_TRY_CMPXCHG && defined HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG +#define local_try_cmpxchg(l, po, n) atomic_long_try_cmpxchg((&(l)->a), (po), (n)) +#if BITS_PER_LONG == 64 + +static inline bool local64_try_cmpxchg(local64_t *l, s64 *old, s64 new) +{ + return local_try_cmpxchg(&l->a, (long *)old, new); +} +#else +#define local64_try_cmpxchg(l, po, n) atomic64_try_cmpxchg((&(l)->a), (po), (n)) +#endif +#endif +#endif From cfd85868f4e8827d26d3b48206a7e8b535cf54c8 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 19 Sep 2023 14:54:33 +0800 Subject: [PATCH 1119/2653] drm/amdkcl: test whether atomoic_long_try_cmpxchg() exist It's caused by v6.5-rc2-955-g9e761bff03e1 drm/amdgpu: Use local64_try_cmpxchg in amdgpu_perf_read Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c index 6e91ea1de5aaf..1017a30d3687d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c @@ -275,9 +275,13 @@ static void amdgpu_perf_read(struct perf_event *event) if ((!pe->adev->df.funcs) || (!pe->adev->df.funcs->pmc_get_count)) return; - +#ifdef HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG prev = local64_read(&hwc->prev_count); +#endif do { +#ifndef HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG + prev = local64_read(&hwc->prev_count); +#endif switch (hwc->config_base) { case AMDGPU_PMU_EVENT_CONFIG_TYPE_DF: case AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI: @@ -288,8 +292,11 @@ static void amdgpu_perf_read(struct perf_event *event) count = 0; break; } +#ifdef HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG } while (!local64_try_cmpxchg(&hwc->prev_count, &prev, count)); - +#else + } while (local64_cmpxchg(&hwc->prev_count, prev, count) != prev); +#endif local64_add(count - prev, &event->count); } From 6e0cf7639ce98e7aef7b4bb0dace142fd547ab65 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Sep 2023 17:04:21 +0800 Subject: [PATCH 1120/2653] drm/amdkcl: test create_class's argument quantity It's caused by v6.3-rc1-13-g1aaba11da9aa driver core: class: remove module * from class_create() Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/create_class.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/linux/class.h | 10 ++++++++++ include/kcl/kcl_class.h | 17 +++++++++++++++++ 6 files changed, 50 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/create_class.m4 create mode 100644 include/kcl/header/linux/class.h create mode 100644 include/kcl/kcl_class.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a11eebffea589..b6546e738c026 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -114,4 +114,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/create_class.m4 b/drivers/gpu/drm/amd/dkms/m4/create_class.m4 new file mode 100644 index 0000000000000..bb9bd7bd2d13d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/create_class.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.3-rc1-13-g1aaba11da9aa driver core: class: remove module * from class_create() +dnl # +AC_DEFUN([AC_AMDGPU_LINUX_DEVICE_CLASS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct class* class = NULL; + class = class_create(NULL); + ], [ + AC_DEFINE(HAVE_ONE_ARGUMENT_OF_CLASS_CREATE, 1, + [class_create has one argument]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9565c3fabab2c..4fe63ea2cdce9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -211,6 +211,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_SHOW_FDINFO AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG + AC_AMDGPU_LINUX_DEVICE_CLASS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index f99ed5020b2e7..557b1a1589e6d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -119,4 +119,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #apple-gmux: Add helper for presence detect dnl AC_KERNEL_CHECK_HEADERS([linux/apple-gmux.h]) + + dnl #v5.5-rc2-6-ga8ae608529ab + dnl #device.h: move 'struct class' stuff out to device/class.h + dnl + AC_KERNEL_CHECK_HEADERS([linux/device/class.h]) ]) diff --git a/include/kcl/header/linux/class.h b/include/kcl/header/linux/class.h new file mode 100644 index 0000000000000..595b34ca30dbe --- /dev/null +++ b/include/kcl/header/linux/class.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_CLASS_H_H_ +#define _KCL_HEADER_LINUX_CLASS_H_H_ + +#ifdef HAVE_LINUX_DEVICE_CLASS_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_class.h b/include/kcl/kcl_class.h new file mode 100644 index 0000000000000..fbce818309960 --- /dev/null +++ b/include/kcl/kcl_class.h @@ -0,0 +1,17 @@ +#ifndef __AMDKCL_CLASS_H__ +#define __AMDKCL_CLASS_H__ + +#ifdef HAVE_LINUX_DEVICE_CLASS_H +#include +#endif +#include +static inline struct class* kcl_class_create(struct module *owner, const char* name) +{ +#ifdef HAVE_ONE_ARGUMENT_OF_CLASS_CREATE + return class_create(name); +#else + return class_create(owner, name); +#endif +} +#endif + From 625a39802caba74d35b4a14df4c0a89957aca5c7 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 19 Sep 2023 17:32:53 +0800 Subject: [PATCH 1121/2653] drm/amdkcl: test drm_gem_object->resv whether exist It's caused by v6.4-rc7-2018-g09593216bff1 drm: execution context for GEM buffers v7 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c | 18 +++++++++--------- include/kcl/kcl_drm_exec.h | 7 +++++++ 2 files changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c index 8fc292da898b0..4bf8c653fa2f4 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c @@ -59,7 +59,7 @@ static void drm_exec_unlock_all(struct drm_exec *exec) unsigned long index; drm_exec_for_each_locked_object(exec, index, obj) { - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); drm_gem_object_put(obj); } @@ -166,12 +166,12 @@ static int drm_exec_lock_contended(struct drm_exec *exec) /* Always cleanup the contention so that error handling can kick in */ exec->contended = NULL; if (exec->flags & DRM_EXEC_INTERRUPTIBLE_WAIT) { - ret = dma_resv_lock_slow_interruptible(obj->resv, + ret = dma_resv_lock_slow_interruptible(amdkcl_gem_resvp(obj), &exec->ticket); if (unlikely(ret)) goto error_dropref; } else { - dma_resv_lock_slow(obj->resv, &exec->ticket); + dma_resv_lock_slow(amdkcl_gem_resvp(obj), &exec->ticket); } ret = drm_exec_obj_locked(exec, obj); @@ -182,7 +182,7 @@ static int drm_exec_lock_contended(struct drm_exec *exec) return 0; error_unlock: - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); error_dropref: drm_gem_object_put(obj); @@ -215,9 +215,9 @@ int drm_exec_lock_obj(struct drm_exec *exec, struct drm_gem_object *obj) } if (exec->flags & DRM_EXEC_INTERRUPTIBLE_WAIT) - ret = dma_resv_lock_interruptible(obj->resv, &exec->ticket); + ret = dma_resv_lock_interruptible(amdkcl_gem_resvp(obj), &exec->ticket); else - ret = dma_resv_lock(obj->resv, &exec->ticket); + ret = dma_resv_lock(amdkcl_gem_resvp(obj), &exec->ticket); if (unlikely(ret == -EDEADLK)) { drm_gem_object_get(obj); @@ -239,7 +239,7 @@ int drm_exec_lock_obj(struct drm_exec *exec, struct drm_gem_object *obj) return 0; error_unlock: - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); return ret; } EXPORT_SYMBOL(drm_exec_lock_obj); @@ -259,7 +259,7 @@ void drm_exec_unlock_obj(struct drm_exec *exec, struct drm_gem_object *obj) for (i = exec->num_objects; i--;) { if (exec->objects[i] == obj) { - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); for (++i; i < exec->num_objects; ++i) exec->objects[i - 1] = exec->objects[i]; --exec->num_objects; @@ -291,7 +291,7 @@ int drm_exec_prepare_obj(struct drm_exec *exec, struct drm_gem_object *obj, if (ret) return ret; - ret = dma_resv_reserve_fences(obj->resv, num_fences); + ret = dma_resv_reserve_fences(amdkcl_gem_resvp(obj), num_fences); if (ret) { drm_exec_unlock_obj(exec, obj); return ret; diff --git a/include/kcl/kcl_drm_exec.h b/include/kcl/kcl_drm_exec.h index 90cd2a6a4f1c8..8a3f47f0520f6 100644 --- a/include/kcl/kcl_drm_exec.h +++ b/include/kcl/kcl_drm_exec.h @@ -6,7 +6,14 @@ #include #include +#ifdef HAVE_DRM_GEM_OBJECT_RESV +#define amdkcl_gem_resvp(bo) (bo->resv) +#else +#define amdkcl_gem_resvp(bo) (container_of(bo, struct ttm_buffer_object, base)->resv) +#endif #ifndef HAVE_DRM_DRM_EXEC_H +#include +#include #define DRM_EXEC_INTERRUPTIBLE_WAIT BIT(0) #define DRM_EXEC_IGNORE_DUPLICATES BIT(1) From fdcedbb4f6468424fcc53d26ac62699e78d142b7 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 19 Sep 2023 17:39:12 +0800 Subject: [PATCH 1122/2653] drm/amdkcl: add dkms support for hmm using new drm_exec object It's caused by v6.4-rc7-2018-g09593216bff1 drm: execution context for GEM buffers v7 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 93 ++++++++++++--------- 2 files changed, 55 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h index 204bee0e32562..2458bbed8cc5b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h @@ -24,6 +24,7 @@ #define __AMDGPU_BO_LIST_H__ #include +#include struct hmm_range; @@ -44,6 +45,7 @@ struct amdgpu_bo_list_entry { bool user_invalidated; #else int user_invalidated; + struct ttm_validate_buffer tv; #endif }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 4c27e8dc1aaea..6b4b67a6cfcca 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -968,21 +968,62 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto out_free_user_pages; } } + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + struct mm_struct *usermm; + + usermm = amdgpu_ttm_tt_get_usermm(e->bo->tbo.ttm); + if (usermm && usermm != current->mm) { + r = -EPERM; + goto out_free_user_pages; + } + + if (amdgpu_ttm_tt_is_userptr(e->bo->tbo.ttm) && + e->user_invalidated && e->user_pages) { + amdgpu_bo_placement_from_domain(e->bo, + AMDGPU_GEM_DOMAIN_CPU); + r = ttm_bo_validate(&e->bo->tbo, &e->bo->placement, + &ctx); + if (r) + goto out_free_user_pages; + + amdgpu_ttm_tt_set_user_pages(e->bo->tbo.ttm, + e->user_pages); + } + + kvfree(e->user_pages); + e->user_pages = NULL; + } #else while (1) { struct list_head need_pages; + drm_exec_until_all_locked(&p->exec) { + r = amdgpu_vm_lock_pd(&fpriv->vm, &p->exec, 1 + p->gang_size); + drm_exec_retry_on_contention(&p->exec); + if (unlikely(r)) + goto error_free_pages; - r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, - &duplicates); - if (unlikely(r != 0)) { - if (r != -ERESTARTSYS) - DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); - goto error_free_pages; - } + amdgpu_bo_list_for_each_entry(e, p->bo_list) { + /* One fence for TTM and one for each CS job */ + r = drm_exec_prepare_obj(&p->exec, &e->bo->tbo.base, + 1 + p->gang_size); + drm_exec_retry_on_contention(&p->exec); + if (unlikely(r)) + goto error_free_pages; + + e->bo_va = amdgpu_vm_bo_find(vm, e->bo); + } + if (p->uf_bo) { + r = drm_exec_prepare_obj(&p->exec, &p->uf_bo->tbo.base, + 1 + p->gang_size); + drm_exec_retry_on_contention(&p->exec); + if (unlikely(r)) + goto error_free_pages; + } + } INIT_LIST_HEAD(&need_pages); amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { - struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + struct amdgpu_bo *bo = e->bo; if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm, &e->user_invalidated) && e->user_pages) { @@ -1009,7 +1050,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, break; /* Unreserve everything again. */ - ttm_eu_backoff_reservation(&p->ticket, &p->validated); + drm_exec_fini(&p->exec); /* We tried too many times, just abort */ if (!--tries) { @@ -1039,37 +1080,9 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto error_free_pages; } } - - /* And try again. */ - list_splice(&need_pages, &p->validated); } #endif - amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { - struct mm_struct *usermm; - - usermm = amdgpu_ttm_tt_get_usermm(e->bo->tbo.ttm); - if (usermm && usermm != current->mm) { - r = -EPERM; - goto out_free_user_pages; - } - - if (amdgpu_ttm_tt_is_userptr(e->bo->tbo.ttm) && - e->user_invalidated && e->user_pages) { - amdgpu_bo_placement_from_domain(e->bo, - AMDGPU_GEM_DOMAIN_CPU); - r = ttm_bo_validate(&e->bo->tbo, &e->bo->placement, - &ctx); - if (r) - goto out_free_user_pages; - - amdgpu_ttm_tt_set_user_pages(e->bo->tbo.ttm, - e->user_pages); - } - - kvfree(e->user_pages); - e->user_pages = NULL; - } amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold, &p->bytes_moved_vis_threshold); @@ -1107,8 +1120,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, return 0; -#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED out_free_user_pages: +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { struct amdgpu_bo *bo = e->bo; @@ -1496,13 +1509,13 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, if (p->jobs[i] == leader) continue; - dma_resv_add_fence(gobj->resv, + dma_resv_add_fence(amdkcl_gem_resvp(gobj), &p->jobs[i]->base.s_fence->finished, DMA_RESV_USAGE_READ); } /* The gang leader as remembered as writer */ - dma_resv_add_fence(gobj->resv, p->fence, DMA_RESV_USAGE_WRITE); + dma_resv_add_fence(amdkcl_gem_resvp(gobj), p->fence, DMA_RESV_USAGE_WRITE); } seq = amdgpu_ctx_add_fence(p->ctx, p->entities[p->gang_leader_idx], From d2f8bb68062495dec2a5ff42f1ae561308bc41eb Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 4 Sep 2023 17:12:58 +0800 Subject: [PATCH 1123/2653] drm/amdkcl: fake macro static_assert() It's caused by ff6320eb2b5616b4843588b066652837e6972666 "drm/amdgpu: add UMSCH 4.0 api definition" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_build_bug.h | 10 ++++++++++ 2 files changed, 11 insertions(+) create mode 100644 include/kcl/kcl_build_bug.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b6546e738c026..4744c221f7df3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -115,4 +115,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_build_bug.h b/include/kcl/kcl_build_bug.h new file mode 100644 index 0000000000000..eb39ce95a8d7d --- /dev/null +++ b/include/kcl/kcl_build_bug.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_LINUX_BUILD_BUG_H +#define AMDKCL_LINUX_BUILD_BUG_H + +#ifndef static_assert +#define static_assert(expr, ...) __static_assert(expr, ##__VA_ARGS__, #expr) +#define __static_assert(expr, msg, ...) _Static_assert(expr, msg) +#endif + +#endif /* AMDKCL_LINUX_BUILD_BUG_H */ \ No newline at end of file From 037b61d958b756e6dca1ca5b747f73e06db7e701 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 17 Sep 2023 12:16:17 +0800 Subject: [PATCH 1124/2653] drm/amdkcl: fake kvrealloc It's caused by 5f5b3abc312ec75134dd2e18aedcdf85e512d669 drm/amdkcl: fake drm_exec_* v6.9-rc4-85-g7bd230a26648 mm/slab: enable slab allocation tagging for kmalloc and friends Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 19 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 | 22 +++++++++++++++++++ include/kcl/kcl_slab.h | 4 ++++ 4 files changed, 46 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index 637ecefbb9773..06854f1c32809 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -6,6 +6,7 @@ */ #include #include +#include #ifndef HAVE_MMPUT_ASYNC void (*_kcl_mmput_async)(struct mm_struct *mm); @@ -36,6 +37,24 @@ extern struct kmem_cache *(*_kcl_kmalloc_slab)(size_t size, gfp_t flags); #endif #endif /* HAVE_KMALLOC_SIZE_ROUNDUP */ +#if !defined(HAVE_KVREALLOC) && !defined(kvrealloc) +void *kvrealloc(const void *p, size_t oldsize, size_t newsize, gfp_t flags) +{ + void *newp; + + if (oldsize >= newsize) + return (void *)p; + newp = kvmalloc(newsize, flags); + if (!newp) + return NULL; + memcpy(newp, p, oldsize); + kvfree(p); + return newp; +} +EXPORT_SYMBOL(kvrealloc); +#endif + + void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4fe63ea2cdce9..87b89e0121b57 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -212,6 +212,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_AMDGPU_LINUX_DEVICE_CLASS + AC_AMDGPU_KVREALLOC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 b/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 index f9f0fa0a1862f..0cd6663de85ce 100644 --- a/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 @@ -16,3 +16,25 @@ AC_DEFUN([AC_AMDGPU_KREALLOC_ARRAY], [ ]) ]) ]) + +dnl # +dnl # +dnl #v5.15-11-g8587ca6f3415 mm: move kvmalloc-related functions to slab.h +dnl #v5.14-rc4-23-gde2860f46362 mm: Add kvrealloc() +dnl # +AC_DEFUN([AC_AMDGPU_KVREALLOC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + #include + ], [ + void *p = NULL; + p = kvrealloc(NULL, 0, 0, GFP_KERNEL); + ], [ + AC_DEFINE(HAVE_KVREALLOC, 1, + [kvrealloc() is available]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_slab.h b/include/kcl/kcl_slab.h index a23a565eab992..42faba605dcb6 100644 --- a/include/kcl/kcl_slab.h +++ b/include/kcl/kcl_slab.h @@ -38,4 +38,8 @@ krealloc_array(void *p, size_t new_n, size_t new_size, gfp_t flags) size_t kmalloc_size_roundup(size_t size); #endif +#if !defined(HAVE_KVREALLOC) && !defined(kvrealloc) +extern void *kvrealloc(const void *p, size_t oldsize, size_t newsize, gfp_t flags); +#endif + #endif From 2b18fb241a71a950e42194eef13c2b3e399211d3 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Sep 2023 15:43:50 +0800 Subject: [PATCH 1125/2653] drm/amdkcl: Test whether get_user_{pages/pages_remote}() wants {6/4} args It's caused by v6.4-rc4-55-gca5e863233e8 mm/gup: remove vmas parameter from get_user_pages_remote() v6.4-rc4-53-g54d020692b34 mm/gup: remove unused vmas parameter from get_user_pages() Signed-off-by: Asher Song --- .../drm/amd/dkms/m4/get-user-pages-remote.m4 | 17 +++++++++++++++-- drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 | 19 ++++++++++++++++--- include/kcl/backport/kcl_mm_backport.h | 4 ++++ 3 files changed, 35 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 index e2fe781b7d7dc..d538ceb02d6b2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 @@ -37,8 +37,21 @@ AC_DEFUN([AC_AMDGPU_GET_USER_PAGES_REMOTE], [ AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS, 1, [get_user_pages_remote() wants gup_flags parameter]) ],[ - AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED, 1, - [get_user_pages_remote() is introduced with initial prototype]) + dnl # + dnl # commit v6.4-rc4-55-gca5e863233e8 + dnl # mm/gup: remove vmas parameter from get_user_pages_remote() + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages_remote(NULL, 0, 0, 0, NULL, NULL); + ], [get_user_pages_remote],[mm/gup.c],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_REMOVE_VMAS, 1, + [get_user_pages_remote() remove argument vmas]) + ],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED, 1, + [get_user_pages_remote() is introduced with initial prototype]) + ]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 b/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 index 7f9931fdf453f..8042f69a0228e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 @@ -24,7 +24,20 @@ AC_DEFUN([AC_AMDGPU_GET_USER_PAGES], [ ], [get_user_pages], [mm/gup.c], [ AC_DEFINE(HAVE_GET_USER_PAGES_6ARGS, 1, [get_user_pages() wants 6 args]) - ]) - ]) - ]) + ],[ + dnl # + dnl # commit v6.4-rc4-53-g54d020692b34 + dnl # mm/gup: remove unused vmas parameter from get_user_pages() + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages(0, 0, 0, NULL); + ], [get_user_pages], [mm/gup.c], [ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOVE_VMAS, 1, + [get_user_pages() remove vmas argument]) + ]) + ]) + ]) + ]) ]) diff --git a/include/kcl/backport/kcl_mm_backport.h b/include/kcl/backport/kcl_mm_backport.h index 48312d64e5869..27c77cd60bbea 100644 --- a/include/kcl/backport/kcl_mm_backport.h +++ b/include/kcl/backport/kcl_mm_backport.h @@ -31,6 +31,8 @@ long kcl_get_user_pages_remote(struct task_struct *tsk, struct mm_struct *mm, #elif defined(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED) return get_user_pages_remote(tsk, mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), !!(gup_flags & FOLL_FORCE), pages, vmas); +#elif defined(HAVE_GET_USER_PAGES_REMOTE_REMOVE_VMAS) + return get_user_pages_remote(mm, start, nr_pages, gup_flags, pages, locked); #else return get_user_pages(tsk, mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), !!(gup_flags & FOLL_FORCE), pages, vmas); @@ -46,6 +48,8 @@ long _kcl_get_user_pages(unsigned long start, unsigned long nr_pages, #if defined(HAVE_GET_USER_PAGES_6ARGS) return get_user_pages(start, nr_pages, !!(gup_flags & FOLL_WRITE), !!(gup_flags & FOLL_FORCE), pages, vmas); +#elif defined(HAVE_GET_USER_PAGES_REMOVE_VMAS) + return get_user_pages(start, nr_pages, gup_flags, pages); #else return get_user_pages(current, current->mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), !!(gup_flags & FOLL_FORCE), pages, vmas); From ae56c8031c4559b25c14fc906439dbea48d857de Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Sep 2023 16:20:08 +0800 Subject: [PATCH 1126/2653] drm/amdkcl: Test struct drm_driver whether has member gem_prime_mmap It's caused by v6.4-rc2-425-g0adec22702d4 drm: Remove struct drm_driver.gem_prime_mmap Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +++++ .../dkms/m4/drm-driver-gem-prime-res-obj.m4 | 20 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 22a6fedb8e103..a63092fc8d4f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3180,7 +3180,9 @@ static struct drm_driver amdgpu_kms_driver = { .gem_prime_vunmap = amdgpu_gem_prime_vunmap, #endif +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_MMAP .gem_prime_mmap = amdkcl_drm_gem_prime_mmap, +#endif .name = DRIVER_NAME, .desc = DRIVER_DESC, @@ -3207,6 +3209,9 @@ const struct drm_driver amdgpu_partition_driver = { .release = &amdgpu_driver_release_kms, .gem_prime_import = amdgpu_gem_prime_import, +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_MMAP + .gem_prime_mmap = drm_gem_prime_mmap, +#endif .name = DRIVER_NAME, .desc = DRIVER_DESC, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 index 226e89eebe85c..80cba3a5a1459 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 @@ -16,3 +16,23 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ], [ ]) ]) ]) +dnl # +dnl # commit 4.9-rc4-834-g85e634bce01a +dnl # drm: Extract drm_drv.h +dnl # +dnl # commit v6.4-rc2-425-g0adec22702d4 +dnl # drm: Remove struct drm_driver.gem_prime_mmap +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_driver *drv = NULL; + drv->gem_prime_mmap(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DRIVER_GEM_PRIME_MMAP, 1, + [drm_driver->gem_prime_mmap() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 87b89e0121b57..82f62f517eb72 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -213,6 +213,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_AMDGPU_LINUX_DEVICE_CLASS AC_AMDGPU_KVREALLOC + AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From e3e1809d7382ef3edccf5bc9bb87e6eb6e66cfde Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Nov 2024 20:41:13 +0800 Subject: [PATCH 1127/2653] drm/amdkcl: update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 49 ++++++++++++++++++------ drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 2 files changed, 39 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f59799ab2ed52..2a2a0cd5957f3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -25,9 +25,6 @@ /* acpi_video_register_backlight() is available */ #define HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT 1 -/* acpi_video_report_nolcd() is available */ -#define HAVE_ACPI_VIDEO_REPORT_NOLCD 1 - /* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ #define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 @@ -422,9 +419,15 @@ /* drm_dp_update_payload_part1() function has start_slot argument */ /* #undef HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG */ +/* drm_driver->gem_prime_mmap() is available */ +/* #undef HAVE_DRM_DRIVER_GEM_PRIME_MMAP */ + /* drm_driver->gem_prime_res_obj() is available */ /* #undef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ */ +/* drm_driver->show_fdinfo() is available */ +#define HAVE_DRM_DRIVER_SHOW_FDINFO 1 + /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRMP_H */ @@ -443,6 +446,9 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRM_BACKPORT_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_EXEC_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_FBDEV_GENERIC_H 1 @@ -525,7 +531,7 @@ /* drm_gem_object_put() is exported */ /* #undef HAVE_DRM_GEM_OBJECT_PUT_SYMBOL */ -/* ttm_buffer_object->base is available */ +/* drm_gem_object->resv/_resv is available */ #define HAVE_DRM_GEM_OBJECT_RESV 1 /* drm_gem_plane_helper_prepare_fb() is available */ @@ -604,6 +610,9 @@ /* drm_print_bits() has 4 args */ #define HAVE_DRM_PRINT_BITS_4ARGS 1 +/* drm_show_fdinfo() is available */ +#define HAVE_DRM_SHOW_FDINFO 1 + /* drm_simple_encoder is available */ #define HAVE_DRM_SIMPLE_ENCODER_INIT 1 @@ -638,7 +647,7 @@ /* #undef HAVE_GET_USER_PAGES_6ARGS */ /* get_user_pages() wants gup_flags parameter */ -#define HAVE_GET_USER_PAGES_GUP_FLAGS 1 +/* #undef HAVE_GET_USER_PAGES_GUP_FLAGS */ /* get_user_pages_remote() wants gup_flags parameter */ /* #undef HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS */ @@ -650,7 +659,13 @@ /* #undef HAVE_GET_USER_PAGES_REMOTE_LOCKED */ /* get_user_pages_remote() remove task_struct pointer */ -#define HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT 1 +/* #undef HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT */ + +/* get_user_pages_remote() remove argument vmas */ +#define HAVE_GET_USER_PAGES_REMOTE_REMOVE_VMAS 1 + +/* get_user_pages() remove vmas argument */ +#define HAVE_GET_USER_PAGES_REMOVE_VMAS 1 /* drm_connector_hdr_sink_metadata() is available */ #define HAVE_HDR_SINK_METADATA 1 @@ -733,9 +748,15 @@ /* ktime_t is union */ /* #undef HAVE_KTIME_IS_UNION */ +/* kvrealloc() is available */ +#define HAVE_KVREALLOC 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_APPLE_GMUX_H 1 +/* atomic_long_try_cmpxchg() is available */ +#define HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_BITS_H 1 @@ -748,6 +769,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_CONTAINER_OF_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DEVICE_CLASS_H 1 + /* Define to 1 if you have the header file. */ /* #undef HAVE_LINUX_DMA_ATTRS_H */ @@ -772,8 +796,8 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_IO_64_NONATOMIC_LO_HI_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_MEM_ENCRYPT_H 1 +/* local_try_cmpchg() is available */ +#define HAVE_LINUX_LOCAL_TRY_CMPXCHG 1 /* Define to 1 if you have the header file. */ #define HAVE_LINUX_MMAP_LOCK_H 1 @@ -853,6 +877,9 @@ /* release_pages() wants 2 args */ #define HAVE_MM_RELEASE_PAGES_2ARGS 1 +/* class_create has one argument */ +#define HAVE_ONE_ARGUMENT_OF_CLASS_CREATE 1 + /* pcie_aspm_enabled() is available */ #define HAVE_PCIE_ASPM_ENABLED 1 @@ -1026,7 +1053,7 @@ #define HAVE_VMF_INSERT 1 /* vmf_insert_mixed_prot() is available */ -#define HAVE_VMF_INSERT_MIXED_PROT 1 +/* #undef HAVE_VMF_INSERT_MIXED_PROT */ /* vmf_insert_pfn_{pmd,pud}() wants 3 args */ /* #undef HAVE_VMF_INSERT_PFN_PMD_3ARGS */ @@ -1086,7 +1113,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 6.2.0" +#define PACKAGE_STRING "amdgpu-dkms 6.5.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1095,7 +1122,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "6.2.0" +#define PACKAGE_VERSION "6.5.0" #include "config-amd-chips.h" diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index fb89f280535c4..666a4766a10b2 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 5.19.0) +AC_INIT(amdgpu-dkms, 6.5.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From acb087cb9b52cd243a2ef68e0f298f518868efbd Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 27 Sep 2023 17:01:59 +0800 Subject: [PATCH 1128/2653] drm/amdkcl: assign to .prime_handle_to_fd and .prime_fd_to_handle of amdgpu_kms_driver It's caused by v6.4-rc7-1904-g71a7974ac701 drm/prime: Unexport helpers for fd/handle conversion Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 +++++++++ drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 | 20 ++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index a63092fc8d4f7..6d56f10bc4d49 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3156,6 +3156,11 @@ static struct drm_driver amdgpu_kms_driver = { #endif #endif +#ifdef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, +#endif + #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK .gem_prime_export = amdgpu_gem_prime_export, #endif @@ -3208,6 +3213,10 @@ const struct drm_driver amdgpu_partition_driver = { .fops = &amdgpu_driver_kms_fops, .release = &amdgpu_driver_release_kms, +#ifdef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, +#endif .gem_prime_import = amdgpu_gem_prime_import, #ifdef HAVE_DRM_DRIVER_GEM_PRIME_MMAP .gem_prime_mmap = drm_gem_prime_mmap, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 index bae97886408be..5d14a0d6b877a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 @@ -14,3 +14,23 @@ AC_DEFUN([AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY], [ ]) ]) ]) + +dnl # +dnl # commit v3.3-9296-g3248877ea179 +dnl # drm: base prime/dma-buf support (v5) +dnl # +dnl # commit v6.4-rc7-1904-g71a7974ac701 +dnl # drm/prime: Unexport helpers for fd/handle conversion +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_gem_prime_handle_to_fd(NULL, NULL, 0, 0, NULL); + ],[drm_gem_prime_handle_to_fd], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_GEM_PRIME_HANDLE_TO_FD, 1, + [drm_gem_prime_handle_to_fd() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 82f62f517eb72..12919268804dd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -214,6 +214,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_DEVICE_CLASS AC_AMDGPU_KVREALLOC AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP + AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 17a2e908c5c63ebfac4617950825c7d7d23e5cf9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 4 Sep 2023 15:39:25 +0800 Subject: [PATCH 1129/2653] drm/amdkcl: Fix unsteady amdgpu dkms build against 4.x kernels The error "Argument list too long" occur on rhel8.*, So extend the previous workaround to fix the error. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/post-build.sh | 4 ++-- drivers/gpu/drm/amd/dkms/pre-build.sh | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/post-build.sh b/drivers/gpu/drm/amd/dkms/post-build.sh index 962903db89aca..59ccb1bf481e6 100755 --- a/drivers/gpu/drm/amd/dkms/post-build.sh +++ b/drivers/gpu/drm/amd/dkms/post-build.sh @@ -3,9 +3,9 @@ KERNELVER=$1 # -# Restore original kernel 5.x scripts/Makefile.build modified by post-add.sh +# Restore original kernel 5.x and Kernel 4.x scripts/Makefile.build modified by post-add.sh # -if [[ ${KERNELVER%%.*} -eq 5 ]]; then +if [ ${KERNELVER%%.*} -eq 5 -o ${KERNELVER%%.*} -eq 4 ]; then moddir="/lib/modules/$KERNELVER" mkfile="scripts/Makefile.build" diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index cdbac6500036c..1eba510fa6eb1 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -60,10 +60,10 @@ done KERNELVER=$1 # -# Kernel 5.x scripts/Makefile.build patch +# Kernel 5.x and Kernel 4.x scripts/Makefile.build patch # The patch makes rules robust against "Argument list too long" error # -if [[ ${KERNELVER%%.*} -eq 5 ]]; then +if [ ${KERNELVER%%.*} -eq 5 -o ${KERNELVER%%.*} -eq 4 ]; then moddir="/lib/modules/$KERNELVER" mkfile="scripts/Makefile.build" @@ -80,7 +80,7 @@ if [[ ${KERNELVER%%.*} -eq 5 ]]; then sed -i -e "/^cmd_mod = {/,/} > \$@$/c"` `"cmd_mod = printf '%s\x5Cn' \$(call real-search, \$*.o, .o, -objs -y -m) | \\\\\n"` `"\t\$(AWK) '!x[\$\$0]++ { print(\"\$(obj)\/\"\$\$0) }' > \$@" \ - -e "s/^[[:space:]]\+cmd_link_multi-m =.*$/"` + -e "s/^[[:space:]]*cmd_link_multi-m = \$(LD).*$/"` `"cmd_link_multi-m = \\\\\n"` `"\t\$(file >\$@.in,\$(filter %.o,$^)) \\\\\n"` `"\t\$(LD) \$(ld_flags) -r -o \$@ @\$@.in; \\\\\n"` From 85429618325d19b07dbb3cb2ef24e1c48f8e788e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 6 Sep 2023 11:15:25 +0800 Subject: [PATCH 1130/2653] drm/amdkcl: fix the missing build_bug.h and update config.h It's caused by ff6320eb2b5616b4843588b066652837e6972666 "drm/amdgpu: add UMSCH 4.0 api definition" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 7 ++++++- include/kcl/header/linux/build_bug.h | 9 +++++++++ include/kcl/kcl_build_bug.h | 2 ++ 4 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 include/kcl/header/linux/build_bug.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2a2a0cd5957f3..dcf82b79b0166 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -760,6 +760,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_BITS_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_BUILD_BUG_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_CC_PLATFORM_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 557b1a1589e6d..a9a77d3a9cdf4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -114,7 +114,7 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # dma-mapping: split dnl # AC_KERNEL_CHECK_HEADERS([linux/dma-map-ops.h]) - + dnl #v4.5-rc3-203-g2413306c2566 dnl #apple-gmux: Add helper for presence detect dnl @@ -124,4 +124,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #device.h: move 'struct class' stuff out to device/class.h dnl AC_KERNEL_CHECK_HEADERS([linux/device/class.h]) + + dnl #v4.12-10499-gbc6245e5efd7 + dnl #bug: split BUILD_BUG stuff out into + dnl + AC_KERNEL_CHECK_HEADERS([linux/build_bug.h]) ]) diff --git a/include/kcl/header/linux/build_bug.h b/include/kcl/header/linux/build_bug.h new file mode 100644 index 0000000000000..d97f9812224e1 --- /dev/null +++ b/include/kcl/header/linux/build_bug.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_BUG_BUILD_H_H +#define _KCL_HEADER_LINUX_BUG_BUILD_H_H + +#ifdef HAVE_LINUX_BUILD_BUG_H +#include_next +#endif + +#endif \ No newline at end of file diff --git a/include/kcl/kcl_build_bug.h b/include/kcl/kcl_build_bug.h index eb39ce95a8d7d..7abac2512a33d 100644 --- a/include/kcl/kcl_build_bug.h +++ b/include/kcl/kcl_build_bug.h @@ -2,6 +2,8 @@ #ifndef AMDKCL_LINUX_BUILD_BUG_H #define AMDKCL_LINUX_BUILD_BUG_H +#include + #ifndef static_assert #define static_assert(expr, ...) __static_assert(expr, ##__VA_ARGS__, #expr) #define __static_assert(expr, msg, ...) _Static_assert(expr, msg) From 41a0393c5531c7666f16bd2beb1dc941b337d2c3 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 8 Sep 2023 12:30:39 +0800 Subject: [PATCH 1131/2653] drm/amdkcl: kcl cleanup macro PCI_IRQ_MSI It's caused by df9155c8fe089418a999d7c0d188897cb694645c "drm/amd: Fix the flag setting code for interrupt request" The macro is included for fixing build for centos7.4 3.10.0-693.el7.x86_64. The latest system is rhel7.9 with kernel 3.10, so clean up the KCL macro. Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index bd5c3b4666888..dc1c256b8fe06 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -336,11 +336,7 @@ void amdgpu_irq_fini_hw(struct amdgpu_device *adev) free_irq(adev->irq.irq, adev_to_drm(adev)); adev->irq.installed = false; if (adev->irq.msi_enabled) -#ifdef PCI_IRQ_MSI pci_free_irq_vectors(adev->pdev); -#else - pci_disable_msi(adev->pdev); -#endif } amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); From bf3110aec5eeae6d537fafb38e2773fe76615937 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 11 Sep 2023 14:50:39 +0800 Subject: [PATCH 1132/2653] drm/amdkcl: fake drm_dp_read_dpcd_caps() It's caused by 58b80b00d4e27a08ea10a281b7e79a4553b70557 "drm/amd/display: Adjust the MST resume flow" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_drm_dp_helper.c | 118 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 | 16 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../kcl/backport/kcl_drm_dp_helper_backport.h | 10 ++ 6 files changed, 149 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_helper.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index f1367b6447788..49b0fe52e6ddc 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o kcl_drm_exec.o + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o kcl_drm_exec.o kcl_drm_dp_helper.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_helper.c new file mode 100644 index 0000000000000..c27581210a3d6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_helper.c @@ -0,0 +1,118 @@ +/* + * Copyright © 2009 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#include +#include +#include + +#ifndef HAVE_DRM_DP_READ_DPCD_CAPS +static int _kcl_drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, + u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; + int ret; + struct drm_device *drm_dev = NULL; + + if (aux) { + struct drm_dp_mst_topology_mgr *mgr = + container_of(&aux, struct drm_dp_mst_topology_mgr, aux); + drm_dev = mgr->dev; + } + /* + * Prior to DP1.3 the bit represented by + * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved. + * If it is set DP_DPCD_REV at 0000h could be at a value less than + * the true capability of the panel. The only way to check is to + * then compare 0000h and 2200h. + */ + if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & + DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT)) + return 0; + + ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext, + sizeof(dpcd_ext)); + if (ret < 0) + return ret; + if (ret != sizeof(dpcd_ext)) + return -EIO; + + if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { + drm_dbg_kms( + drm_dev, + "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n", + aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); + return 0; + } + + if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))) + return 0; + + drm_dbg_kms(drm_dev, "%s: Base DPCD: %*ph\n", aux->name, + DP_RECEIVER_CAP_SIZE, dpcd); + + memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext)); + + return 0; +} + +/** + * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if + * available + * @aux: DisplayPort AUX channel + * @dpcd: Buffer to store the resulting DPCD in + * + * Attempts to read the base DPCD caps for @aux. Additionally, this function + * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if + * present. + * + * Returns: %0 if the DPCD was read successfully, negative error code + * otherwise. + */ +int _kcl_drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, + u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + int ret; + struct drm_device *drm_dev = NULL; + + if (aux) { + struct drm_dp_mst_topology_mgr *mgr = + container_of(&aux, struct drm_dp_mst_topology_mgr, aux); + drm_dev = mgr->dev; + } + + ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE); + if (ret < 0) + return ret; + if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0) + return -EIO; + + ret = _kcl_drm_dp_read_extended_dpcd_caps(aux, dpcd); + if (ret < 0) + return ret; + + drm_dbg_kms(drm_dev, "%s: DPCD: %*ph\n", aux->name, + DP_RECEIVER_CAP_SIZE, dpcd); + + return ret; +} +EXPORT_SYMBOL(_kcl_drm_dp_read_dpcd_caps); +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index dcf82b79b0166..55cbd30d9466e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -410,6 +410,9 @@ /* struct drm_dp_mst_topology_state has member total_avail_slots */ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS 1 +/* drm_dp_read_dpcd_caps() is available */ +#define HAVE_DRM_DP_READ_DPCD_CAPS 1 + /* drm_dp_send_real_edid_checksum() is available */ #define HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 new file mode 100644 index 0000000000000..dbd64ba5dbbe8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.9-rc1-294-gb9936121d95b +dnl # drm/i915/dp: Extract drm_dp_read_dpcd_caps() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_READ_DPCD_CAPS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_read_dpcd_caps(NULL, NULL); + ], [drm_dp_read_dpcd_caps], [drivers/gpu/drm/display/drm_dp_helper.c], [ + AC_DEFINE(HAVE_DRM_DP_READ_DPCD_CAPS, 1, + [drm_dp_read_dpcd_caps() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 12919268804dd..3a496b0adec82 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -185,6 +185,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 + AC_AMDGPU_DRM_DP_READ_DPCD_CAPS AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB diff --git a/include/kcl/backport/kcl_drm_dp_helper_backport.h b/include/kcl/backport/kcl_drm_dp_helper_backport.h index 4c541b78127d7..61b4a14bb0151 100644 --- a/include/kcl/backport/kcl_drm_dp_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_helper_backport.h @@ -17,4 +17,14 @@ #if !defined(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP) #define drm_dp_cec_register_connector _kcl_drm_dp_cec_register_connector #endif + +#if !defined(HAVE_DRM_DP_READ_DPCD_CAPS) +int _kcl_drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, + u8 dpcd[DP_RECEIVER_CAP_SIZE]); +static inline int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, + u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return _kcl_drm_dp_read_dpcd_caps(aux, dpcd); +} +#endif #endif From 2b1d074b965c589c105bdbf30d5bc8729bb5fa93 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 14 Sep 2023 15:39:05 +0800 Subject: [PATCH 1133/2653] drm/amdkcl: fake drm_dp_add_payload_part{1,2}() It's caused by 7c5343f2a75336d865edea2d15f5f0234eaf8054 "drm/mst: Refactor the flow for payload allocation/removement" The function drm_dp_remove_payload() has been splited to two subfuctions, so add kcl macro bypass the new feature. Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 5 ++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-dp-remove-payload-part.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-remove-payload-part.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 7e09a7f82efc2..fd6f7241b432d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -399,8 +399,11 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( dm_helpers_construct_old_payload(mst_mgr, mst_state, new_payload, &old_payload); target_payload = &old_payload; - +#ifdef HAVE_DRM_DP_REMOVE_RAYLOAD_PART drm_dp_remove_payload_part1(mst_mgr, mst_state, new_payload); +#else + drm_dp_remove_payload(mst_mgr, mst_state, &old_payload, new_payload); +#endif } /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 55cbd30d9466e..0bcee7d1d221a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -413,6 +413,9 @@ /* drm_dp_read_dpcd_caps() is available */ #define HAVE_DRM_DP_READ_DPCD_CAPS 1 +/* drm_dp_remove_payload_part{1,2}() is available */ +#define HAVE_DRM_DP_REMOVE_RAYLOAD_PART 1 + /* drm_dp_send_real_edid_checksum() is available */ #define HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-remove-payload-part.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-remove-payload-part.m4 new file mode 100644 index 0000000000000..10468731e64f9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-remove-payload-part.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.3-5135-g7c5343f2a753 +dnl # "drm/mst: Refactor the flow for payload allocation/removement" +dnl +AC_DEFUN([AC_AMDGPU_DRM_DP_REMOVE_RAYLOAD_PART], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_remove_payload_part1(NULL, NULL, NULL); + ], [drm_dp_remove_payload_part1],[drivers/gpu/drm/display/drm_dp_mst_topology.c],[ + AC_DEFINE(HAVE_DRM_DP_REMOVE_RAYLOAD_PART, 1, + [drm_dp_remove_payload_part{1,2}() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3a496b0adec82..647c8b65251ca 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -186,6 +186,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 AC_AMDGPU_DRM_DP_READ_DPCD_CAPS + AC_AMDGPU_DRM_DP_REMOVE_RAYLOAD_PART AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB From ce6ea537166b027a6a8fcdcb8a958e59e5984081 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 15 Sep 2023 15:24:23 +0800 Subject: [PATCH 1134/2653] drm/amdkcl: wrap code under macro DEFINE_DEBUGFS_ATTRIBUTE It's caused by 402742b54302cbf0faf126cdf2c7c01265ffb586 "drm/amdgpu: add amdgpu mca debug sysfs support" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c index 3ca03b5e0f913..91d4819cd7f12 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c @@ -613,8 +613,10 @@ static const struct file_operations mca_ue_dump_debug_fops = { .release = single_release, }; +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_set, "%llu\n"); #endif +#endif void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root) { @@ -622,7 +624,9 @@ void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root if (!root) return; +#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file("mca_debug_mode", 0200, root, adev, &mca_debug_mode_fops); +#endif debugfs_create_file("mca_ue_dump", 0400, root, adev, &mca_ue_dump_debug_fops); debugfs_create_file("mca_ce_dump", 0400, root, adev, &mca_ce_dump_debug_fops); #endif From 4a01755afc92e04e6339876eeed4bb1fcb6d0d5c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 18 Sep 2023 13:39:35 +0800 Subject: [PATCH 1135/2653] drm/amdkcl: fix function return in HAVE_DMA_FENCE_CHAIN_ALLOC To support rhel9.3, add function return verify in M4 HAVE_DMA_FENCE_CHAIN_ALLOC Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 index 1627d69677f9e..f35b2f8d404ca 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 @@ -7,7 +7,8 @@ AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_ALLOC], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - dma_fence_chain_alloc(); + struct dma_fence_chain *chain = NULL; + chain = dma_fence_chain_alloc(); ], [ AC_DEFINE(HAVE_DMA_FENCE_CHAIN_ALLOC, 1, [dma_fence_chain_alloc() is available]) From 8895bd57e28520c65d563c51ddcbd0fb442671bd Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 25 Sep 2023 12:48:51 +0800 Subject: [PATCH 1136/2653] drm/amdkcl: fake drm_dbg_dp() It's caused by ec1e3bdbb037d7d4397cb8c14db801cc3b839860 "drm/amd/display: switch DC over to the new DRM logging macros" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_drm_print.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 15abde9faeb53..c1aa05a71ff23 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -137,6 +137,11 @@ void kcl_drm_err(const char *format, ...); drm_dev_dbg((drm)->dev, 0x04, fmt, ##__VA_ARGS__) #endif +#if !defined(drm_dbg_dp) +#define drm_dbg_dp(drm, fmt, ...) \ + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DP, fmt, ##__VA_ARGS__) +#endif + #ifndef HAVE_DRM_DEBUG_ENABLED /* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ static inline bool drm_debug_enabled(unsigned int category) From 839d52258f51c9366dd29aa3571a297ce8ce239c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 25 Sep 2023 12:50:14 +0800 Subject: [PATCH 1137/2653] drm/amdkcl: wrap code under macro HAVE_DRM_DP_AUX_DRM_DEV and HAVE_KTIME_IS_UNION It's caused by ec1e3bdbb037d7d4397cb8c14db801cc3b839860 "drm/amd/display: switch DC over to the new DRM logging macros" the old macro DC_LOG_DC has been modified, so update DC_LOG_DC to DRM_DEBUG_KMS. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 23 ++++++++++++++----- 2 files changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 38bdbfa6d238c..13789b7434628 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -543,8 +543,8 @@ static void dm_vupdate_high_irq(void *interrupt_params) struct common_irq_params *irq_params = interrupt_params; struct amdgpu_device *adev = irq_params->adev; struct amdgpu_crtc *acrtc; -#ifndef HAVE_KTIME_IS_UNION struct drm_device *drm_dev; +#ifndef HAVE_KTIME_IS_UNION struct drm_vblank_crtc *vblank; ktime_t frame_duration_ns, previous_timestamp; #endif @@ -555,8 +555,8 @@ static void dm_vupdate_high_irq(void *interrupt_params) if (acrtc) { vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); -#ifndef HAVE_KTIME_IS_UNION drm_dev = acrtc->base.dev; +#ifndef HAVE_KTIME_IS_UNION vblank = drm_crtc_vblank_crtc(&acrtc->base); previous_timestamp = atomic64_read(&irq_params->previous_timestamp); frame_duration_ns = get_drm_vblank_crtc_time(vblank) - previous_timestamp; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index fd6f7241b432d..b6c558fc40175 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -902,8 +902,11 @@ static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, // read rc data drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length); } - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "success = %d\n", success); +#else + DRM_DEBUG_KMS("%s: success = %d\n", __func__, success); +#endif return success; @@ -915,9 +918,11 @@ static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) { unsigned char data[16] = {0}; - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "Start\n"); - +#else + DRM_DEBUG_KMS("Start %s\n", __func__); +#endif // Step 2 data[0] = 'P'; data[1] = 'R'; @@ -973,8 +978,11 @@ static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) // Step 6 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL)) return; - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "Done\n"); +#else + DRM_DEBUG_KMS("Done %s\n", __func__); +#endif } /* MST Dock */ @@ -986,9 +994,12 @@ static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( bool enable) { uint8_t ret = 0; - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "MST_DSC Configure DSC to non-virtual dpcd synaptics\n"); +#else + DRM_DEBUG_KMS("MST_DSC Configure DSC to non-virtual dpcd synaptics\n"); +#endif if (enable) { /* When DSC is enabled on previous boot and reboot with the hub, @@ -1088,7 +1099,7 @@ bool dm_helpers_dp_write_dsc_enable( } #else ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1); - DC_LOG_DC("Send DSC %s to MST RX\n", enable_dsc ? "enable" : "disable"); + DRM_DEBUG_KMS("Send DSC %s to MST RX\n", enable_dsc ? "enable" : "disable"); #endif } From dd05788b60fd1bd09b3fcac6f25cb3f211fc0af9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 9 Oct 2023 14:03:46 +0800 Subject: [PATCH 1138/2653] drm/amdkcl: keep drm DPCD declarations for KCL It's caused by f53df85fbe6576ea111f11333ae3fbcd9d9220f3 "drm/amd/display: Remove unused DPCD declarations" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_drm_dp.h | 67 +++++++++++++++++++++++++ 2 files changed, 68 insertions(+) create mode 100644 include/kcl/kcl_drm_dp.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 4744c221f7df3..e2331135ef531 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -116,4 +116,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_drm_dp.h b/include/kcl/kcl_drm_dp.h new file mode 100644 index 0000000000000..1f277a16b5874 --- /dev/null +++ b/include/kcl/kcl_drm_dp.h @@ -0,0 +1,67 @@ +/* + * Copyright © 2008 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ +#ifndef _KCL_DRM_DP_H +#define _KCL_DRM_DP_H + +#ifndef DP_SINK_VIDEO_FALLBACK_FORMATS +#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 +#endif +#ifndef DP_FEC_CAPABILITY_1 +#define DP_FEC_CAPABILITY_1 0x091 +#endif + +#ifndef DP_DSC_CONFIGURATION +#define DP_DSC_CONFIGURATION 0x161 +#endif +#ifndef DP_PHY_SQUARE_PATTERN +#define DP_PHY_SQUARE_PATTERN 0x249 +#endif + +#ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 +#endif +#ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK +#define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) +#endif +#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK +#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) +#endif +#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT +#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 +#endif +#ifndef DP_DSC_DECODER_COUNT_MASK +#define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) +#endif +#ifndef DP_DSC_DECODER_COUNT_SHIFT +#define DP_DSC_DECODER_COUNT_SHIFT 5 +#endif +#ifndef DP_MAIN_LINK_CHANNEL_CODING_SET +#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 +#endif +#ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 +#endif +#ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION +#define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) +#endif + +#endif \ No newline at end of file From 96994143e5bd297d14208351988c354ec838b365 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 9 Oct 2023 14:12:29 +0800 Subject: [PATCH 1139/2653] drm/amdkcl: test whether drm_connector_helper_funcs->prepare_writeback_job is available It's caused by 457ca82075a522bc5655d0abe363761d05ab2609 "drm/amd/display: Initialize writeback connector" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm_connector_helper_funcs.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 21 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0bcee7d1d221a..503f5813fced4 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -202,6 +202,9 @@ arg */ #define HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE 1 +/* drm_connector_helper_funcs->prepare_writeback_job is available */ +#define HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB 1 + /* drm_connector_init_with_ddc() is available */ #define HAVE_DRM_CONNECTOR_INIT_WITH_DDC 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 new file mode 100644 index 0000000000000..fe75c0300c099 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.1-rc1-14-g9d2230dc1351 +dnl # drm: writeback: Add job prepare and cleanup operations +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_helper_funcs *funcs; + funcs->prepare_writeback_job = NULL; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB, 1, + [drm_connector_helper_funcs->prepare_writeback_job is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 647c8b65251ca..5d08ef0df519b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -79,6 +79,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM + AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_INIT AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL From 581c0fd94571ac79cf76713cfb381d859e8f8b25 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 9 Oct 2023 14:13:50 +0800 Subject: [PATCH 1140/2653] drm/amdkcl: test whether drm_writeback_connector_init() has 7 args It's caused by 457ca82075a522bc5655d0abe363761d05ab2609 "drm/amd/display: Initialize writeback connector" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../dkms/m4/drm_writeback_connector_init.m4 | 16 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_writeback.h | 31 +++++++++++++++++++ 5 files changed, 52 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_writeback_connector_init.m4 create mode 100644 include/kcl/kcl_drm_writeback.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e2331135ef531..a504ed69b614e 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -117,4 +117,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 503f5813fced4..48f076807fb4e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -637,6 +637,9 @@ /* struct drm_vma_offset_node has readonly field */ /* #undef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD */ +/* drm_writeback_connector_init() has 7 args */ +#define HAVE_DRM_WRITEBACK_CONNECTOR_INIT_7_ARGS 1 + /* fault_flag_allow_retry_first() is available */ #define HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_writeback_connector_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_writeback_connector_init.m4 new file mode 100644 index 0000000000000..7f2c208c36f96 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_writeback_connector_init.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.18-rc2-67-g57b8280a0a41 +dnl # drm: allow passing possible_crtcs to drm_writeback_connector_init() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_WRITEBACK_CONNECTOR_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_writeback_connector_init(NULL, NULL, NULL, NULL, NULL, 0, 0); + ],[drm_writeback_connector_init], [drivers/gpu/drm/drm_writeback.c],[ + AC_DEFINE(HAVE_DRM_WRITEBACK_CONNECTOR_INIT_7_ARGS, 1, + [drm_writeback_connector_init() has 7 args]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5d08ef0df519b..e1f6d24d7ae0c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -79,6 +79,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM + AC_AMDGPU_DRM_WRITEBACK_CONNECTOR_INIT AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_INIT diff --git a/include/kcl/kcl_drm_writeback.h b/include/kcl/kcl_drm_writeback.h new file mode 100644 index 0000000000000..14b6d63f4b4b3 --- /dev/null +++ b/include/kcl/kcl_drm_writeback.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. + * Author: Brian Starkey + * + * This program is free software and is provided to you under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation, and any use by you of this program is subject to the terms + * of such GNU licence. + */ +#ifndef AMDKCL_DRM_WRITEBACK_H +#define AMDKCL_DRM_WRITEBACK_H + +#include + +#ifndef HAVE_DRM_WRITEBACK_CONNECTOR_INIT_7_ARGS +static inline int _kcl_drm_writeback_connector_init(struct drm_device *dev, + struct drm_writeback_connector *wb_connector, + const struct drm_connector_funcs *con_funcs, + const struct drm_encoder_helper_funcs *enc_helper_funcs, + const u32 *formats, int n_formats, + u32 possible_crtcs) +{ + wb_connector->encoder.possible_crtcs = possible_crtcs; + + return drm_writeback_connector_init(dev, wb_connector, con_funcs, enc_helper_funcs, formats, n_formats); +} +#define drm_writeback_connector_init _kcl_drm_writeback_connector_init +#endif + +#endif \ No newline at end of file From 19ffccf83985de5fe98f3477120db30370f9c7be Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 9 Oct 2023 14:29:36 +0800 Subject: [PATCH 1141/2653] drm/amdkcl: wrap code under macro HAVE_STRUCT_XARRAY It's caused by ed5694767b668f36d80b2c986af8703ed9c51a5f "drm/amdgpu: add cached GPU fault structure to vm struct" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 +++ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 ++- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 3 ++- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- 6 files changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index faf409e8d13a2..ab55a669eab06 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -3183,6 +3183,7 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m) * * Cache the fault info for later use by userspace in debugging. */ +#ifdef HAVE_STRUCT_XARRAY void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, unsigned int pasid, uint64_t addr, @@ -3229,6 +3230,7 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, } xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); } +#endif /** * amdgpu_vm_is_bo_always_valid - check if the BO is VM always valid diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 0298898579863..504b068b0ef33 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -667,11 +667,14 @@ static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) mutex_unlock(&vm->eviction_lock); } +#ifdef HAVE_STRUCT_XARRAY void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, unsigned int pasid, uint64_t addr, uint32_t status, unsigned int vmhub); +#endif + void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct dma_fence **fence); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 7031dd8c3c5eb..d05032ab31cf3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -150,9 +150,10 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, status = RREG32(hub->vm_l2_pro_fault_status); WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); - +#ifdef HAVE_STRUCT_XARRAY amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); +#endif } if (!printk_ratelimit()) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 93d2b0bbe6419..37e56289dc900 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -120,9 +120,10 @@ static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, status = RREG32(hub->vm_l2_pro_fault_status); WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); - +#ifdef HAVE_STRUCT_XARRAY amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); +#endif } if (printk_ratelimit()) { diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 93d7ccb7d013a..5dfdc0019c414 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1269,10 +1269,10 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, if (!addr && !status) return 0; - +#ifdef HAVE_STRUCT_XARRAY amdgpu_vm_update_fault_cache(adev, entry->pasid, ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0)); - +#endif if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) gmc_v7_0_set_fault_enable_default(adev, false); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index ded48f11dc0ee..82bfb991c2995 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1452,10 +1452,10 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, if (!addr && !status) return 0; - +#ifdef HAVE_STRUCT_XARRAY amdgpu_vm_update_fault_cache(adev, entry->pasid, ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0)); - +#endif if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) gmc_v8_0_set_fault_enable_default(adev, false); From 35fd3e4463ceca27fa9a586cd8cee5bf02bdac48 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 9 Oct 2023 14:32:52 +0800 Subject: [PATCH 1142/2653] drm/amdkcl: wrap code under macro HAVE_STRUCT_XARRAY It's caused by 2b332c97042ed499b7f04d2648736848c8f007a4 "drm/amdgpu: add new INFO ioctl query for the last GPU page fault" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 7ed162e9fa22f..7d1a16b072b20 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1359,6 +1359,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return copy_to_user(out, max_ibs, min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; } +#ifdef HAVE_STRUCT_XARRAY case AMDGPU_INFO_GPUVM_FAULT: { struct amdgpu_fpriv *fpriv = filp->driver_priv; struct amdgpu_vm *vm = &fpriv->vm; @@ -1379,6 +1380,8 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return copy_to_user(out, &gpuvm_fault, min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0; } +#endif + case AMDGPU_INFO_UQ_FW_AREAS: { struct drm_amdgpu_info_uq_metadata meta_info = {}; From 256c71084eb6b64d8edf130db5c926c703229181 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 9 Oct 2023 14:39:02 +0800 Subject: [PATCH 1143/2653] drm/amdkcl: wrap code under macro HAVE_PCI_DRIVER_DEV_GROUPS It's caused by 442a478469621f459834b27d5ac1c392bacd9c25 "drm/amdgpu: Add sysfs attribute to get board info" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 6695bb19f0236..aa916e62b1cfc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -358,7 +358,7 @@ int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block) * - "unknown" - Not known * */ - +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static ssize_t amdgpu_device_get_board_info(struct device *dev, struct device_attribute *attr, char *buf) @@ -410,6 +410,7 @@ static const struct attribute_group amdgpu_board_attrs_group = { .attrs = amdgpu_board_attrs, .is_visible = amdgpu_board_attrs_is_visible }; +#endif static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); @@ -4804,11 +4805,12 @@ int amdgpu_device_init(struct amdgpu_device *adev, r = amdgpu_device_attr_sysfs_init(adev); if (r) dev_err(adev->dev, "Could not create amdgpu device attr\n"); - +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS r = devm_device_add_group(adev->dev, &amdgpu_board_attrs_group); if (r) dev_err(adev->dev, "Could not create amdgpu board attributes\n"); +#endif amdgpu_fru_sysfs_init(adev); amdgpu_reg_state_sysfs_init(adev); From 13cbcaa1f1fd35858cf3f2c81b3d9413d4f1d254 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 12 Oct 2023 11:01:39 +0800 Subject: [PATCH 1144/2653] drm/amdkcl: add return statements for KCL It's caused by 0da86105f4b82253e4521281aa377bd1a2c989b1 "drm/amdgpu: Drop unnecessary return statements" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index 76de119d863ac..b77c6ca5e7599 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -232,6 +232,8 @@ void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *amdgpu_encode /* Try registering an ACPI video backlight device instead. */ #ifdef HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT acpi_video_register_backlight(); +#else + return; #endif } From ba1bca1ee3283b1b871b97f8267f86b6524f63e8 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 24 Oct 2023 14:03:17 +0800 Subject: [PATCH 1145/2653] drm/amdkcl: update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 24 +++--------------------- 1 file changed, 3 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 48f076807fb4e..2d6f99358a9c4 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -252,12 +252,6 @@ /* struct drm_device has pdev member */ /* #undef HAVE_DRM_DEVICE_PDEV */ -/* drm_dev_put() is available */ -#define HAVE_DRM_DEV_PUT 1 - -/* drm_dev_unplug() is available */ -#define HAVE_DRM_DEV_UNPLUG 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_DISPLAY_DRM_DP_H 1 @@ -422,9 +416,6 @@ /* drm_dp_send_real_edid_checksum() is available */ #define HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM 1 -/* drm_dp_start_crc() is available */ -#define HAVE_DRM_DP_START_CRC 1 - /* drm_dp_update_payload_part1() function has start_slot argument */ /* #undef HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG */ @@ -546,6 +537,9 @@ /* drm_gem_plane_helper_prepare_fb() is available */ #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 +/* drm_gem_prime_handle_to_fd() is available */ +/* #undef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD */ + /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 @@ -649,9 +643,6 @@ /* fs_reclaim_acquire() is available */ #define HAVE_FS_RECLAIM_ACQUIRE 1 -/* drm_driver->gem_free_object_unlocked() is available */ -/* #undef HAVE_GEM_FREE_OBJECT_UNLOCKED_IN_DRM_DRIVER */ - /* generic_handle_domain_irq() is available */ #define HAVE_GENERIC_HANDLE_DOMAIN_IRQ 1 @@ -958,12 +949,6 @@ /* seq_hex_dump() is available */ #define HAVE_SEQ_HEX_DUMP 1 -/* drm_driver->set_busid is available */ -/* #undef HAVE_SET_BUSID_IN_STRUCT_DRM_DRIVER */ - -/* whether si_mem_available() is available */ -#define HAVE_SI_MEM_AVAILABLE 1 - /* smca_get_bank_type(x) is available */ /* #undef HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT */ @@ -1009,9 +994,6 @@ /* drm_gem_open_object is defined in struct drm_drv */ /* #undef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ -/* drm_pending_vblank_event->sequence is available */ -#define HAVE_STRUCT_DRM_PENDING_VBLANK_EVENT_SEQUENCE 1 - /* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 From 94013d0c324d3beded45ce4cf903c0a0339d4266 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 24 Oct 2023 16:42:09 +0800 Subject: [PATCH 1146/2653] drm/amdgpu: add missing null check for tbo.resource It's caused by 2e6dcc672567d7ffe913fac226ad1f4bd139e88e "drm/ttm: stop allocating dummy resources during BO creation" The latest ttm beable to handle the move without a resource, so some tbo.resource is null when bo release. Then add null pointer chec when adding AMDGPU_PL_DGMA support. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index f22ae84b50b66..799ca7e6045bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -216,10 +216,10 @@ static void amdgpu_gem_object_free(struct drm_gem_object *gobj) } } - if (aobj->tbo.resource->mem_type == AMDGPU_PL_DGMA) + if (aobj->tbo.resource && aobj->tbo.resource->mem_type == AMDGPU_PL_DGMA) atomic64_sub(amdgpu_bo_size(aobj), &adev->direct_gma.vram_usage); - else if (aobj->tbo.resource->mem_type == AMDGPU_PL_DGMA_IMPORT) + else if (aobj->tbo.resource && aobj->tbo.resource->mem_type == AMDGPU_PL_DGMA_IMPORT) atomic64_sub(amdgpu_bo_size(aobj), &adev->direct_gma.gart_usage); From d3d9ee1311ac20c9026e61b818801812c641f66f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 27 Oct 2023 14:44:27 +0800 Subject: [PATCH 1147/2653] drm/amdkcl: align M4 format Update some M4 to align the format. Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- .../drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 | 16 +++++++++------- .../drm/amd/dkms/m4/drm_simple_kms_helper.m4 | 16 +++++++++------- .../gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 | 18 ++++++++++-------- 3 files changed, 28 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 index 5854aa864fd2e..cae3e54d7c7f7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 @@ -3,12 +3,14 @@ dnl # commit 707d561f77b5e2a6f90c9786bee44ee7a8dedc7e dnl # drm: allow limiting the scatter list size. dnl # AC_DEFUN([AC_AMDGPU_DRM_PRIME_PAGES_TO_SG], [ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_prime_pages_to_sg(NULL, NULL, 0); - ], [drm_prime_pages_to_sg], [drivers/gpu/drm/drm_prime.c], [ - AC_DEFINE(HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS, 1, - [drm_prime_pages_to_sg() wants 3 arguments]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_prime_pages_to_sg(NULL, NULL, 0); + ], [drm_prime_pages_to_sg], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS, 1, + [drm_prime_pages_to_sg() wants 3 arguments]) + ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 index 7f8cf4e9ad0a1..837e690cc9c32 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 @@ -3,12 +3,14 @@ dnl # v5.6-rc2-359-g63170ac6f2e8 dnl # drm/simple-kms: Add drm_simple_encoder_{init,create}() dnl # AC_DEFUN([AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT], [ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ],[ - drm_simple_encoder_init(NULL, NULL, 0); - ],[drm_simple_encoder_init], [drivers/gpu/drm/drm_simple_kms_helper.c],[ - AC_DEFINE(HAVE_DRM_SIMPLE_ENCODER_INIT, 1, - [drm_simple_encoder is available]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_simple_encoder_init(NULL, NULL, 0); + ],[drm_simple_encoder_init], [drivers/gpu/drm/drm_simple_kms_helper.c],[ + AC_DEFINE(HAVE_DRM_SIMPLE_ENCODER_INIT, 1, + [drm_simple_encoder is available]) + ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 index ac2a78006ea2e..e3d33a862d7fb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 @@ -3,13 +3,15 @@ dnl # dnl # v5.5-rc2-5-g8438b84ab42d x86/mce: Take action on UCNA/Deferred errors again dnl # AC_DEFUN([AC_AMDGPU_MCE_PRIO_UC], [ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - enum mce_notifier_prios pri; - pri = MCE_PRIO_UC; - ], [ - AC_DEFINE(HAVE_MCE_PRIO_UC, 1, - [enum MCE_PRIO_UC is available]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum mce_notifier_prios pri; + pri = MCE_PRIO_UC; + ], [ + AC_DEFINE(HAVE_MCE_PRIO_UC, 1, + [enum MCE_PRIO_UC is available]) + ]) ]) ]) From 03dc667ba7501102eb38b3655777f6fdc2d7e6fb Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 27 Oct 2023 14:45:50 +0800 Subject: [PATCH 1148/2653] drm/amdkcl: update prepare_writeback_job to limit param The latest HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB hasn't been defined, so update M4 to fix the issue and limit params. Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 index fe75c0300c099..11f356754b2c5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 @@ -7,8 +7,8 @@ AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB], [ AC_KERNEL_TRY_COMPILE([ #include ],[ - struct drm_connector_helper_funcs *funcs; - funcs->prepare_writeback_job = NULL; + struct drm_connector_helper_funcs *funcs = NULL; + funcs->prepare_writeback_job((struct drm_writeback_connector *)NULL, (struct drm_writeback_job *)NULL); ],[ AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB, 1, [drm_connector_helper_funcs->prepare_writeback_job is available]) From 4d9e3c098d9e59c55ee42c0daf1003908e0cc419 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 24 Oct 2023 12:47:03 -0400 Subject: [PATCH 1149/2653] Shorten path to DKMS module build directory Make the build robust against too long argument error Change-Id: Ifb3f146f55d645bb1809f79751902690f937b096 Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/dkms.conf | 8 +++--- drivers/gpu/drm/amd/dkms/post-build.sh | 23 ++------------- drivers/gpu/drm/amd/dkms/pre-build.sh | 39 ++++---------------------- 3 files changed, 11 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 78cc07704d491..6067de790980c 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -1,9 +1,9 @@ PACKAGE_NAME="amdgpu" PACKAGE_VERSION="1.0" AUTOINSTALL="yes" -PRE_BUILD="amd/dkms/pre-build.sh $kernelver" -POST_BUILD="amd/dkms/post-build.sh $kernelver" -POST_REMOVE="amd/dkms/post-build.sh $kernelver" +module_build_dir="$(mktemp -ut amd.XXXXXXXX)" +PRE_BUILD="amd/dkms/pre-build.sh $kernelver $dkms_tree $module $module_version $module_build_dir" +POST_BUILD="amd/dkms/post-build.sh $module_build_dir" # not all OS supports weak module updates NO_WEAK_MODULES="yes" @@ -41,4 +41,4 @@ DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm/amd/amdxcp" MAKE[0]="make TTM_NAME=${BUILT_MODULE_NAME[1]} \ SCHED_NAME=${BUILT_MODULE_NAME[3]} \ -C $kernel_source_dir \ - M=$dkms_tree/$module/$module_version/build" + M=$module_build_dir" diff --git a/drivers/gpu/drm/amd/dkms/post-build.sh b/drivers/gpu/drm/amd/dkms/post-build.sh index 59ccb1bf481e6..0c600db277937 100755 --- a/drivers/gpu/drm/amd/dkms/post-build.sh +++ b/drivers/gpu/drm/amd/dkms/post-build.sh @@ -1,23 +1,4 @@ #!/bin/bash -KERNELVER=$1 - -# -# Restore original kernel 5.x and Kernel 4.x scripts/Makefile.build modified by post-add.sh -# -if [ ${KERNELVER%%.*} -eq 5 -o ${KERNELVER%%.*} -eq 4 ]; then - moddir="/lib/modules/$KERNELVER" - mkfile="scripts/Makefile.build" - - if [[ -d "$moddir/source" ]]; then - mkfile="$moddir/source/$mkfile" - else - mkfile="$moddir/build/$mkfile" - fi - - mkfile=$(readlink -f $mkfile) - - if [[ -f "$mkfile~" ]]; then - mv -f $mkfile{~,} - fi -fi +MODULE_BUILD_DIR=$1 +rm -rf $MODULE_BUILD_DIR diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 1eba510fa6eb1..ca64bd8c9fc66 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -5,6 +5,10 @@ INC="include" SRC="amd/dkms" KERNELVER=$1 +DKMS_TREE=$2 +MODULE=$3 +MODULE_VERSION=$4 +MODULE_BUILD_DIR=$5 KERNELVER_BASE=${KERNELVER%%-*} version_lt () { @@ -55,41 +59,8 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile done -#!/bin/bash - -KERNELVER=$1 - -# -# Kernel 5.x and Kernel 4.x scripts/Makefile.build patch -# The patch makes rules robust against "Argument list too long" error -# -if [ ${KERNELVER%%.*} -eq 5 -o ${KERNELVER%%.*} -eq 4 ]; then - moddir="/lib/modules/$KERNELVER" - mkfile="scripts/Makefile.build" - - if [[ -d "$moddir/source" ]]; then - mkfile="$moddir/source/$mkfile" - else - mkfile="$moddir/build/$mkfile" - fi - - mkfile=$(readlink -e $mkfile) - - if [[ "$?" -eq 0 ]] && [[ ! -f "$mkfile~" ]]; then - cp -a ${mkfile}{,~} - sed -i -e "/^cmd_mod = {/,/} > \$@$/c"` - `"cmd_mod = printf '%s\x5Cn' \$(call real-search, \$*.o, .o, -objs -y -m) | \\\\\n"` - `"\t\$(AWK) '!x[\$\$0]++ { print(\"\$(obj)\/\"\$\$0) }' > \$@" \ - -e "s/^[[:space:]]*cmd_link_multi-m = \$(LD).*$/"` - `"cmd_link_multi-m = \\\\\n"` - `"\t\$(file >\$@.in,\$(filter %.o,$^)) \\\\\n"` - `"\t\$(LD) \$(ld_flags) -r -o \$@ @\$@.in; \\\\\n"` - `"\trm -f \$@.in/" \ - $mkfile - fi -fi - export KERNELVER +ln -s $DKMS_TREE/$MODULE/$MODULE_VERSION/build $MODULE_BUILD_DIR (cd $SRC && ./configure) # rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o From 69c5cd374d00eea63fbd6a459556bb67c6c2aea8 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Mon, 30 Oct 2023 22:20:57 -0400 Subject: [PATCH 1150/2653] Fix dkms driver build on Oracle Linux 8.x Change-Id: I953c377749fb2d7cec6dbb4b1bbf8211454cc19d Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/Makefile | 1 + drivers/gpu/drm/amd/dkms/dkms.conf | 2 +- drivers/gpu/drm/amd/dkms/pre-build.sh | 12 ++++++++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index a73a7f7227df2..0e41d5633a6f9 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -179,6 +179,7 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC +subdir-ccflags-y += -Wno-error ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) ifdef CONFIG_DEVICE_PRIVATE diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 6067de790980c..1006d000952ed 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -38,7 +38,7 @@ BUILT_MODULE_NAME[6]="amdxcp" BUILT_MODULE_LOCATION[6]="amd/amdxcp" DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm/amd/amdxcp" -MAKE[0]="make TTM_NAME=${BUILT_MODULE_NAME[1]} \ +MAKE[0]=". $module_build_dir/.env && make TTM_NAME=${BUILT_MODULE_NAME[1]} \ SCHED_NAME=${BUILT_MODULE_NAME[3]} \ -C $kernel_source_dir \ M=$module_build_dir" diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index ca64bd8c9fc66..796020ae1570f 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -61,6 +61,18 @@ done export KERNELVER ln -s $DKMS_TREE/$MODULE/$MODULE_VERSION/build $MODULE_BUILD_DIR + +# Enable gcc-toolset for kernels that are built with non-default compiler +if [[ -d /opt/rh ]]; then + for f in $(find /opt/rh -type f -a -name gcc); do + if strings /boot/vmlinuz-$KERNELVER | grep -q "$($f --version | head -1)"; then + . ${f%/*}/../../../enable + break + fi + done +fi +echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env + (cd $SRC && ./configure) # rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o From 7514d575518b97fc0d1dc35028bd5ca43e6b707e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 2 Nov 2023 11:18:00 +0800 Subject: [PATCH 1151/2653] drm/amdkcl: fake dev_is_removable() repalce pci_is_thunderbolt_attached() It's caused by 99abe09a40d2c87d849a2cb1930c2792fc5e3396 "drm/amdgpu: don't use pci_is_thunderbolt_attached()" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 7 ++----- drivers/gpu/drm/amd/dkms/m4/dev_is_removable.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_device.h | 8 ++++++++ 4 files changed, 28 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dev_is_removable.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2d6f99358a9c4..3920f051c488d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -94,11 +94,8 @@ /* MEMORY_DEVICE_COHERENT is availablea */ #define HAVE_DEVICE_COHERENT 1 -/* devm_memremap_pages() wants struct dev_pagemap */ -#define HAVE_DEVM_MEMREMAP_PAGES_DEV_PAGEMAP 1 - -/* devm_memremap_pages() wants p,p,p,p interface */ -/* #undef HAVE_DEVM_MEMREMAP_PAGES_P_P_P_P */ +/* dev_is_removable() is available */ +#define HAVE_DEV_IS_REMOVABLE 1 /* dev_pagemap->owner is available */ #define HAVE_DEV_PAGEMAP_OWNER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dev_is_removable.m4 b/drivers/gpu/drm/amd/dkms/m4/dev_is_removable.m4 new file mode 100644 index 0000000000000..14ddb4989bbac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dev_is_removable.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.13-rc2-70-g70f400d4d957 +dnl # driver core: Move the "removable" attribute from USB to core +dnl # +AC_DEFUN([AC_AMDGPU_DEV_IS_REMOVABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool res = 0; + res = dev_is_removable(NULL); + ], [ + AC_DEFINE(HAVE_DEV_IS_REMOVABLE, 1, + [dev_is_removable() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e1f6d24d7ae0c..d1ecc5062e683 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -148,6 +148,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT + AC_AMDGPU_DEV_IS_REMOVABLE AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI diff --git a/include/kcl/kcl_device.h b/include/kcl/kcl_device.h index a4d0dfbb334bc..a6480630d0ab2 100644 --- a/include/kcl/kcl_device.h +++ b/include/kcl/kcl_device.h @@ -60,4 +60,12 @@ static inline void dev_pm_set_driver_flags(struct device *dev, u32 flags) } #endif +#ifndef HAVE_DEV_IS_REMOVABLE +static inline bool _kcl_dev_is_removable(struct device *dev) +{ + return false; +} +#define dev_is_removable _kcl_dev_is_removable +#endif + #endif /* AMDKCL_DEVICE_H */ From ae1a90a640621c170186978c3b76b7f4bb78a675 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 3 Nov 2023 15:38:40 +0800 Subject: [PATCH 1152/2653] drm/amdkcl: wrap code under amdkcl_ttm_resvp() It's caused by 0c0e51e78d7697be597eefb1e2dcbec3c3bf801d "drm/amdgpu: Attach eviction fence on alloc" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 7316c5f5120ec..5610abd8bdef5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -438,11 +438,11 @@ int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, if (ret) goto unreserve_out; - ret = dma_resv_reserve_fences(bo->tbo.base.resv, 1); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(&bo->tbo), 1); if (ret) goto unreserve_out; - dma_resv_add_fence(bo->tbo.base.resv, fence, + dma_resv_add_fence(amdkcl_ttm_resvp(&bo->tbo), fence, DMA_RESV_USAGE_BOOKKEEP); unreserve_out: From 84eb37105293700f8c43ca2b703cd3f0f6ad5911 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 3 Nov 2023 19:43:26 -0400 Subject: [PATCH 1153/2653] Fix dkms parrallel build 'dkms' has a bug and can't substitute 'make' command if it is not the first word in the command line. So, we restore -j option that used to be in dkms.conf before it was integrated into dkms. Change-Id: I39653f4bace4832bb110e3debcee89c51b106bf0 Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/dkms.conf | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 1006d000952ed..ceef7d15a7c26 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -38,7 +38,17 @@ BUILT_MODULE_NAME[6]="amdxcp" BUILT_MODULE_LOCATION[6]="amd/amdxcp" DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm/amd/amdxcp" -MAKE[0]=". $module_build_dir/.env && make TTM_NAME=${BUILT_MODULE_NAME[1]} \ +num_cpu_cores() +{ + if [ -x /usr/bin/nproc ]; then + nproc + else + echo "1" + fi +} + +MAKE[0]=". $module_build_dir/.env && make -j$(num_cpu_cores) KERNELRELEASE=$kernelver \ + TTM_NAME=${BUILT_MODULE_NAME[1]} \ SCHED_NAME=${BUILT_MODULE_NAME[3]} \ -C $kernel_source_dir \ M=$module_build_dir" From 893ce3c424cbcdadf74eef131d2e45b36b642c02 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 10 Nov 2023 16:34:53 -0500 Subject: [PATCH 1154/2653] drm/amdkcl: fix DRM_DP_READ_DPCD_CAPS test Add another location to search for drm_dp_read_dpcd_caps exported symbol to cover older kernels. Change-Id: I216e6ffcb1f66947974acd0d4ef1b9477826852c Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 index dbd64ba5dbbe8..8306568c2e0ca 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 @@ -8,9 +8,9 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_READ_DPCD_CAPS], [ #include ], [ drm_dp_read_dpcd_caps(NULL, NULL); - ], [drm_dp_read_dpcd_caps], [drivers/gpu/drm/display/drm_dp_helper.c], [ + ], [drm_dp_read_dpcd_caps], [drivers/gpu/drm/display/drm_dp_helper.c drivers/gpu/drm/drm_dp_helper.c], [ AC_DEFINE(HAVE_DRM_DP_READ_DPCD_CAPS, 1, [drm_dp_read_dpcd_caps() is available]) ]) ]) -]) \ No newline at end of file +]) From e92ad63fd0004a801adbf9fbf01291cc7fb33707 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 14 Nov 2023 19:06:19 +0800 Subject: [PATCH 1155/2653] Revert "drm/amdgpu: fix AGP init order" The reverted patch cause a page fault error on navi32 when modprobe. Temporarily revert it. This reverts commit 00ee8d37fae64ce4e6d01bf83707e7e39d6a6398. Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 +++ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 -- 7 files changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 5632f6ffc1fc8..15fd25f943fcc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1092,6 +1092,9 @@ static const char * const amdgpu_vram_names[] = { */ int amdgpu_bo_init(struct amdgpu_device *adev) { + /* set the default AGP aperture state */ + amdgpu_gmc_set_agp_default(adev, &adev->gmc); + /* On A+A platform, VRAM can be mapped as WB */ if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { /* reserve PAT memory space to WC for VRAM */ diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index d05032ab31cf3..29da06f985002 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -673,7 +673,6 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, /* add the xgmi offset of the physical node */ base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, &adev->gmc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 37e56289dc900..5d9f3abbf6099 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -643,7 +643,6 @@ static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, base = adev->mmhub.funcs->get_fb_location(adev); - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, &adev->gmc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_HIGH); if (!amdgpu_sriov_vf(adev) && diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index f6ad7911f1e6f..41eedb6d1628f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -211,7 +211,6 @@ static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, base <<= 24; - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, mc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 5dfdc0019c414..4924568b0c618 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -242,7 +242,6 @@ static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, base <<= 24; - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, mc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 82bfb991c2995..38f81c6ccc965 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -417,7 +417,6 @@ static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; base <<= 24; - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, mc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 8404695eb13fe..e12b833fa8989 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1665,8 +1665,6 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, { u64 base = adev->mmhub.funcs->get_fb_location(adev); - amdgpu_gmc_set_agp_default(adev, mc); - /* add the xgmi offset of the physical node */ base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; if (amdgpu_gmc_is_pdb0_enabled(adev)) { From 1c7102e2a4524c09cc4bec89aa46caa726f8e266 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 14 Nov 2023 13:36:34 +0800 Subject: [PATCH 1156/2653] drm/amdkcl: wrap code under macro DEFINE_DEBUGFS_ATTRIBUTE It's caused by f8340195642eae0367646d59fbc046a380ccce9e "drm/amd/display: add a debugfs interface for the DMUB trace mask" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 6df87d119649d..4a9866b7c7718 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3211,6 +3211,7 @@ static int allow_edp_hotplug_detection_set(void *data, u64 val) return 0; } +#if defined(DEFINE_DEBUGFS_ATTRIBUTE) /* check if kernel disallow eDP enter psr state * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr * 0: allow edp enter psr; 1: disallow @@ -3336,7 +3337,7 @@ static int dmub_trace_mask_show(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(dmub_trace_mask_fops, dmub_trace_mask_show, dmub_trace_mask_set, "0x%llx\n"); - +#endif /* * Set dmcub trace event IRQ enable or disable. * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en From 80f96496af7da005cdfd3f19e9f89243012b789d Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 9 Nov 2023 13:08:13 +0530 Subject: [PATCH 1157/2653] drm/amdgpu: Skip execution of pending reset jobs cancel_work is not backported to all custom kernels. Add a workaround to skip execution of already queued recovery jobs, if the device is already reset. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 9 +++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 16 ++++++++++++++++ 3 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index aa916e62b1cfc..0c4c9855db58e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6150,6 +6150,8 @@ static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + amdgpu_reset_domain_clear_pending(adev->reset_domain); + #if defined(CONFIG_DEBUG_FS) if (!amdgpu_sriov_vf(adev)) cancel_work(&adev->reset_work); @@ -6185,6 +6187,9 @@ static int amdgpu_device_recovery_prepare(struct amdgpu_device *adev, struct amdgpu_device *tmp_adev = NULL; int r; + if (amdgpu_reset_domain_in_drain_mode(adev->reset_domain)) + return 0; + /* * Build list of devices to reset. * In case we are in XGMI hive mode, resort the device list diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c index dabfbdf6f1ce6..7eb3c81fe75a5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c @@ -271,6 +271,14 @@ void amdgpu_reset_destroy_reset_domain(struct kref *ref) kvfree(reset_domain); } +static void amdgpu_reset_domain_cancel_all_work(struct work_struct *work) +{ + struct amdgpu_reset_domain *reset_domain = + container_of(work, struct amdgpu_reset_domain, clear); + + reset_domain->drain = false; +} + struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type, char *wq_name) { @@ -293,6 +301,7 @@ struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_d } + INIT_WORK(&reset_domain->clear, amdgpu_reset_domain_cancel_all_work); atomic_set(&reset_domain->in_gpu_reset, 0); atomic_set(&reset_domain->reset_res, 0); init_rwsem(&reset_domain->sem); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h index 4d9b9701139be..5ae71c0d5aecd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h @@ -98,6 +98,8 @@ struct amdgpu_reset_domain { struct rw_semaphore sem; atomic_t in_gpu_reset; atomic_t reset_res; + struct work_struct clear; + bool drain; }; int amdgpu_reset_init(struct amdgpu_device *adev); @@ -136,6 +138,20 @@ static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *doma return queue_work(domain->wq, work); } +static inline void amdgpu_reset_domain_clear_pending(struct amdgpu_reset_domain *domain) +{ + domain->drain = true; + /* queue one more work to the domain queue. Till this work is finished, + * domain is in drain mode. + */ + queue_work(domain->wq, &domain->clear); +} + +static inline bool amdgpu_reset_domain_in_drain_mode(struct amdgpu_reset_domain *domain) +{ + return domain->drain; +} + static inline bool amdgpu_reset_pending(struct amdgpu_reset_domain *domain) { lockdep_assert_held(&domain->sem); From 3204414592d6d6b66dd5ca319546100210ff0ee8 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 23 Nov 2023 12:18:21 +0800 Subject: [PATCH 1158/2653] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS It's caused by 1b6d631dea0b57f564722f78c144ee621691d5be "drm/amd/display: adjust flow for deallocation mst payload" Signed-off-by: Bob Zhou Reviewed-by: Asher Song Reviewed-by: Ma Jun Reviewed-by: Slava Abramov --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index b6c558fc40175..e1f6a51acf88b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -550,9 +550,7 @@ void dm_helpers_dp_mst_send_payload_allocation( struct drm_dp_mst_topology_mgr *mst_mgr; enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; -#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) int ret = 0; -#endif aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; @@ -591,9 +589,13 @@ void dm_helpers_dp_mst_update_mst_mgr_for_deallocation( const struct dc_stream_state *stream) { struct amdgpu_dm_connector *aconnector; - struct drm_dp_mst_topology_state *mst_state; struct drm_dp_mst_topology_mgr *mst_mgr; +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS + struct drm_dp_mst_topology_state *mst_state; struct drm_dp_mst_atomic_payload *new_payload, old_payload; +#else + struct drm_dp_mst_port *mst_port; +#endif enum mst_progress_status set_flag = MST_CLEAR_ALLOCATED_PAYLOAD; enum mst_progress_status clr_flag = MST_ALLOCATE_NEW_PAYLOAD; @@ -603,15 +605,26 @@ void dm_helpers_dp_mst_update_mst_mgr_for_deallocation( return; mst_mgr = &aconnector->mst_root->mst_mgr; +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); +#ifdef HAVE_DRM_DP_REMOVE_RAYLOAD_PART dm_helpers_construct_old_payload(mst_mgr, mst_state, new_payload, &old_payload); drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload, new_payload); +#endif +#else + mst_port = aconnector->mst_output_port; + if (!mst_mgr->mst_state) + return; +#endif amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, true); amdgpu_dm_set_mst_status(&aconnector->mst_status, clr_flag, false); +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS + drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port); +#endif } void dm_dtn_log_begin(struct dc_context *ctx, From 7d1c32dd81225b8195dd3a76c1722bd85a14e6c4 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 24 Nov 2023 16:17:56 -0500 Subject: [PATCH 1159/2653] drm/amdkcl: compare only gcc version Compare only CONFIG_GCC_VERSION kernel build option with gcc version. "gcc --version" line embedded into the kernel binary could be different. For example the kernel 5.15 in Oracle 8 contains this version string: gcc (GCC) 11.2.1 20220127 (Red Hat 11.2.1-9.1.0.6) but gcc-toolset-11 prints gcc (GCC) 11.2.1 20220127 (Red Hat 11.2.1-9.2.0.1) Regardless the gcc versions are identical the compiler vendor portion is different. To avoid mismatching we compare only actual gcc version. SWDEV-427914 Change-Id: I7903db72f01b3880d9ce8514c6a841f573c241cd Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/pre-build.sh | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 796020ae1570f..5f922ec16986c 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -65,7 +65,11 @@ ln -s $DKMS_TREE/$MODULE/$MODULE_VERSION/build $MODULE_BUILD_DIR # Enable gcc-toolset for kernels that are built with non-default compiler if [[ -d /opt/rh ]]; then for f in $(find /opt/rh -type f -a -name gcc); do - if strings /boot/vmlinuz-$KERNELVER | grep -q "$($f --version | head -1)"; then + [[ -f /boot/config-$KERNELVER ]] || continue + config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) + IFS='.' read -ra ver <<<$($f -dumpfullversion) + gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) + if [[ "$config_gcc_version" = "$gcc_version" ]]; then . ${f%/*}/../../../enable break fi From 2e80747e328d4cee698c21557b58ca3ea87d0744 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 30 Nov 2023 18:09:19 +0800 Subject: [PATCH 1160/2653] drm/amdkcl: fake dma_fence_timestamp Signed-off-by: Asher Song --- .../drm/amd/dkms/m4/dma-fence-timestamp.m4 | 17 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma_fence.h | 21 +++++++++++++++++++ 3 files changed, 39 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-timestamp.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-timestamp.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-timestamp.m4 new file mode 100644 index 0000000000000..8054979dd1b6a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-timestamp.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.6-rc1-33-gb83ce9cb4a46 +dnl # dma-buf: add dma_fence_timestamp helper +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_TIMESTAMP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_t time; + time = dma_fence_timestamp(NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_TIMESTAMP, 1, [dma_fence_TIMESTAMP() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d1ecc5062e683..112bd204cb996 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -220,6 +220,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KVREALLOC AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD + AC_AMDGPU_DMA_FENCE_TIMESTAMP AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_dma_fence.h b/include/kcl/kcl_dma_fence.h index 20a014352f967..ae63b65466e00 100644 --- a/include/kcl/kcl_dma_fence.h +++ b/include/kcl/kcl_dma_fence.h @@ -45,4 +45,25 @@ static inline bool dma_fence_is_container(struct dma_fence *fence) #endif /* HAVE_DMA_FENCE_IS_CONTAINER */ +#ifndef HAVE_DMA_FENCE_TIMESTAMP +/** + * dma_fence_timestamp - helper to get the completion timestamp of a fence + * @fence: fence to get the timestamp from. + * + * After a fence is signaled the timestamp is updated with the signaling time, + * but setting the timestamp can race with tasks waiting for the signaling. This + * helper busy waits for the correct timestamp to appear. + */ +static inline ktime_t dma_fence_timestamp(struct dma_fence *fence) +{ + if (WARN_ON(!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))) + return ktime_get(); + + while (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags)) + cpu_relax(); + + return fence->timestamp; +} +#endif + #endif From d38ad686f5e2e2653706e4a284793b8ae11831cd Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 3 Dec 2023 17:21:54 +0800 Subject: [PATCH 1161/2653] drm/amdkcl: test macro __counted_by whether is defined It's caused by v6.5-rc2-17-gc8248faf3ca2 Compiler Attributes: counted_by: Adjust name and identifier expansion Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 6 +++++- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 ++++ drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h | 6 +++++- 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h index 2458bbed8cc5b..47734741388fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h @@ -61,8 +61,12 @@ struct amdgpu_bo_list { /* Protect access during command submission. */ struct mutex bo_list_mutex; - +#ifdef __counted_by struct amdgpu_bo_list_entry entries[] __counted_by(num_entries); +#else + struct amdgpu_bo_list_entry entries[]; +#endif + }; int amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index f2f18fb422c3b..63a6586403c7e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -786,7 +786,11 @@ struct ip_hw_instance { u8 harvest; int num_base_addresses; +#ifdef __counted_by u32 base_addr[] __counted_by(num_base_addresses); +#else + u32 base_addr[]; +#endif }; struct ip_hw_id { diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h index 42adc2a3dcbc1..ec6cec793c25c 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h @@ -192,7 +192,11 @@ struct smu10_clock_voltage_dependency_record { struct smu10_voltage_dependency_table { uint32_t count; - struct smu10_clock_voltage_dependency_record entries[] __counted_by(count); + struct smu10_clock_voltage_dependency_record entries[] +#ifdef __counted_by + __counted_by(count) +#endif + ; }; struct smu10_clock_voltage_information { From 02aa475e26ca8e7dad8eb03a9c28285012e495e1 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 3 Dec 2023 20:03:38 +0800 Subject: [PATCH 1162/2653] drm/amdkcl:test whether shrinker_register exists It's caused by v6.6-rc4-53-gc42d50aefd17 mm: shrinker: add infrastructure for dynamically allocating shrinker Signed-off-by: Asher Song Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- .../gpu/drm/amd/dkms/m4/register_shrinker.m4 | 22 +++++++++++++++ drivers/gpu/drm/ttm/ttm_pool.c | 28 +++++++++++++++++-- include/kcl/kcl_shrinker.h | 2 ++ 4 files changed, 51 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 112bd204cb996..fcc462aec9c0a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -194,7 +194,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB AC_AMDGPU_BITMAP_TO_ARR32 - AC_AMDGPU_REGISTER_SHRINKER + AC_AMDGPU_SHRINKER AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN AC_AMDGPU_ACPI_VIDEO_FUNCS diff --git a/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 b/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 index 903f100bf18bd..98c49b53ddc6f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 @@ -17,3 +17,25 @@ AC_DEFUN([AC_AMDGPU_REGISTER_SHRINKER], [ ]) ]) ]) + +dnl # +dnl # commit: v6.6-rc4-53-gc42d50aefd17 +dnl # mm: shrinker: add infrastructure for dynamically allocating shrinker +dnl # +AC_DEFUN([AC_AMDGPU_SHRINKER_REGISTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + shrinker_register(NULL); + ], [shrinker_register], [mm/shrinker.c], [ + AC_DEFINE(HAVE_SHRINKER_REGISTER, 1, + [shrinker_register() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_SHRINKER], [ + AC_AMDGPU_REGISTER_SHRINKER + AC_AMDGPU_SHRINKER_REGISTER +]) diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c index 6c6cc6a43815d..4d5fc41d4db86 100644 --- a/drivers/gpu/drm/ttm/ttm_pool.c +++ b/drivers/gpu/drm/ttm/ttm_pool.c @@ -128,7 +128,12 @@ static struct ttm_pool_type global_dma32_uncached[NR_PAGE_ORDERS]; static spinlock_t shrinker_lock; static struct list_head shrinker_list; -static struct shrinker *mm_shrinker; +static struct shrinker +#ifdef HAVE_SHRINKER_REGISTER +*mm_shrinker; +#else +mm_shrinker; +#endif static DECLARE_RWSEM(pool_shrink_rwsem); /* Allocate pages of size 1 << order with the given gfp_flags */ @@ -1284,9 +1289,17 @@ static int ttm_pool_debugfs_shrink_show(struct seq_file *m, void *data) unsigned long count; fs_reclaim_acquire(GFP_KERNEL); + +#ifdef HAVE_SHRINKER_REGISTER count = ttm_pool_shrinker_count(mm_shrinker, &sc); seq_printf(m, "%lu/%lu\n", count, ttm_pool_shrinker_scan(mm_shrinker, &sc)); +#else + count = ttm_pool_shrinker_count(&mm_shrinker, &sc); + seq_printf(m, "%lu/%lu\n", count, + ttm_pool_shrinker_scan(&mm_shrinker, &sc)); +#endif + fs_reclaim_release(GFP_KERNEL); return 0; @@ -1334,6 +1347,7 @@ int ttm_pool_mgr_init(unsigned long num_pages) #endif #endif +#ifdef HAVE_SHRINKER_REGISTER mm_shrinker = shrinker_alloc(0, "drm-ttm_pool"); if (!mm_shrinker) return -ENOMEM; @@ -1344,8 +1358,14 @@ int ttm_pool_mgr_init(unsigned long num_pages) mm_shrinker->seeks = 1; shrinker_register(mm_shrinker); - return 0; +#else + mm_shrinker.count_objects = ttm_pool_shrinker_count; + mm_shrinker.scan_objects = ttm_pool_shrinker_scan; + mm_shrinker.seeks = 1; + + return kcl_register_shrinker(&mm_shrinker, "drm-ttm_pool"); +#endif } /** @@ -1365,6 +1385,10 @@ void ttm_pool_mgr_fini(void) ttm_pool_type_fini(&global_dma32_uncached[i]); } +#ifdef HAVE_SHRINKER_REGISTER shrinker_free(mm_shrinker); +#else + unregister_shrinker(&mm_shrinker); +#endif WARN_ON(!list_empty(&shrinker_list)); } diff --git a/include/kcl/kcl_shrinker.h b/include/kcl/kcl_shrinker.h index c237de4b867cf..ca93cd0197f9f 100644 --- a/include/kcl/kcl_shrinker.h +++ b/include/kcl/kcl_shrinker.h @@ -7,6 +7,7 @@ extern void synchronize_shrinkers(void); #endif +#ifndef HAVE_SHRINKER_REGISTER static inline int __printf(2, 3) kcl_register_shrinker(struct shrinker *shrinker, const char *fmt, ...) { @@ -16,5 +17,6 @@ static inline int __printf(2, 3) kcl_register_shrinker(struct shrinker *shrinker return register_shrinker(shrinker); #endif } +#endif #endif From 48c0b80654d5ec4a2430c9495673a92605cf8f08 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 6 Dec 2023 13:29:14 +0800 Subject: [PATCH 1163/2653] drm/amdkcl: fake pci_get_base_class It's caused by v6.6-rc1-1-gd427da2323b0 PCI: Add pci_get_base_class() helper Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 57 +++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 | 22 +++++++++ include/kcl/kcl_pci.h | 10 ++++ 4 files changed, 90 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index c62f0a2f9d6e9..742ba33ab1884 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -249,3 +249,60 @@ u32 _kcl_pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) EXPORT_SYMBOL(_kcl_pci_rebar_get_possible_sizes); #endif /* HAVE_PCI_REBAR_BYTES_TO_SIZE */ #endif /* AMDKCL_ENABLE_RESIZE_FB_BAR */ + +/* Copied from drivers/pci/pci.c */ +#ifndef HAVE_PCI_GET_BASE_CLASS +static inline const struct pci_device_id * +pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) +{ + if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && + (id->device == PCI_ANY_ID || id->device == dev->device) && + (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && + (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && + !((id->class ^ dev->class) & id->class_mask)) + return id; + return NULL; +} + +static int match_pci_dev_by_id(struct device *dev, const void *data) +{ + struct pci_dev *pdev = to_pci_dev(dev); + const struct pci_device_id *id = data; + + if (pci_match_one_device(id, pdev)) + return 1; + return 0; +} + +static struct pci_dev *pci_get_dev_by_id(const struct pci_device_id *id, + struct pci_dev *from) +{ + struct device *dev; + struct device *dev_start = NULL; + struct pci_dev *pdev = NULL; + + if (from) + dev_start = &from->dev; + dev = bus_find_device(&pci_bus_type, dev_start, (void *)id, + match_pci_dev_by_id); + if (dev) + pdev = to_pci_dev(dev); + pci_dev_put(from); + return pdev; +} + +struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from) +{ + struct pci_device_id id = { + .vendor = PCI_ANY_ID, + .device = PCI_ANY_ID, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + .class_mask = 0xFF0000, + .class = class << 16, + }; + + return pci_get_dev_by_id(&id, from); +} +EXPORT_SYMBOL(pci_get_base_class); +#endif /*HAVE_PCI_GET_BASE_CLASS*/ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fcc462aec9c0a..b294ceab1de6a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -26,7 +26,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCI_UPSTREAM_BRIDGE AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS - AC_AMDGPU_PCI_DEV_ID + AC_AMDGPU_PCI AC_AMDGPU_PCI_REBAR_BYTES_TO_SIZE AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_KTIME_GET_RAW_NS diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 index 29c0928f6bd40..0138c0b995d3c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 @@ -14,3 +14,25 @@ AC_DEFUN([AC_AMDGPU_PCI_DEV_ID], [ ]) ]) ]) + +dnl # +dnl # commit: v6.6-rc1-1-gd427da2323b0 +dnl # PCI: Add pci_get_base_class() helper +dnl # +AC_DEFUN([AC_AMDGPU_PCI_GET_BASE_CLASS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + pci_get_base_class(0, NULL); + ], [pci_get_base_class], [drivers/pci/search.c], [ + AC_DEFINE(HAVE_PCI_GET_BASE_CLASS, 1, + [pci_get_base_class() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_PCI], [ + AC_AMDGPU_PCI_DEV_ID + AC_AMDGPU_PCI_GET_BASE_CLASS +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 62e8d734fdf5c..26bb0043066a0 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -206,4 +206,14 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) #endif /* PCI_REBAR_CTRL_BAR_SHIFT */ +/* Copied from include/linux/pci.h */ +#ifndef HAVE_PCI_GET_BASE_CLASS +#ifdef CONFIG_PCI +struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from); +#else /*CONFIG_PCI*/ +static inline struct pci_dev *pci_get_base_class(unsigned int class, + struct pci_dev *from) +{ return NULL; } +#endif /*CONFIG_PCI*/ +#endif /*HAVE_PCI_GET_BASE_CLASS*/ #endif /* AMDKCL_PCI_H */ From e3a0cd281610125327be52d62d92d68716178cbf Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 3 Dec 2023 21:26:06 +0800 Subject: [PATCH 1164/2653] drm/amdkcl:fake vma_is_init_{heap, stack} It's caused by v6.5-rc4-265-g11250fd12eb8 mm: factor out VMA stack and heap checks Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 | 19 +++++++++++++++ include/kcl/kcl_mm.h | 28 +++++++++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b294ceab1de6a..d69b78822722e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -221,6 +221,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD AC_AMDGPU_DMA_FENCE_TIMESTAMP + AC_AMDGPU_VMA_IS_INITIAL AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 index 74cd3b8edd7ce..537ee8180393a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 @@ -32,3 +32,22 @@ AC_DEFUN([AC_AMDGPU_VM_FLAGS_SET], [ ]) ]) ]) + +dnl # +dnl # v6.5-rc4-265-g11250fd12eb8 +dnl # mm: factor out VMA stack and heap checks +dnl # +AC_DEFUN([AC_AMDGPU_VMA_IS_INITIAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vma_is_initial_heap(NULL); + vma_is_initial_stack(NULL); + ], [ + AC_DEFINE(HAVE_VMA_IS_INITIAL_HEAP, 1, + [vma_is_initial_{heap, stack} is available]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 188cff38d5db6..646ba0d687544 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -138,4 +138,32 @@ static inline unsigned long _kcl_totalram_pages(void) #define totalram_pages _kcl_totalram_pages #endif /* HAVE_TOTALRAM_PAGES */ +/*copy from include/linux/mm.h */ +#ifndef HAVE_VMA_IS_INITIAL_HEAP +/* + * Indicate if the VMA is a heap for the given task; for + * /proc/PID/maps that is the heap of the main task. + */ +static inline bool vma_is_initial_heap(const struct vm_area_struct *vma) +{ + return vma->vm_start <= vma->vm_mm->brk && + vma->vm_end >= vma->vm_mm->start_brk; +} + +/* + * Indicate if the VMA is a stack for the given task; for + * /proc/PID/maps that is the stack of the main task. + */ +static inline bool vma_is_initial_stack(const struct vm_area_struct *vma) +{ + /* + * We make no effort to guess what a given thread considers to be + * its "stack". It's not even well-defined for programs written + * languages like Go. + */ + return vma->vm_start <= vma->vm_mm->start_stack && + vma->vm_end >= vma->vm_mm->start_stack; +} +#endif + #endif /* AMDKCL_MM_H */ From 0069a17562c5b20dee32009eb731082f87496f1d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 3 Dec 2023 21:26:57 +0800 Subject: [PATCH 1165/2653] drm/amdkcl: test struct x86 whether has member topo Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 4 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/processor.m4 | 18 ++++++++++++++++++ 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/processor.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index f35b7539da007..2bc99a24c536b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -2414,7 +2414,11 @@ static int kfd_cpumask_to_apic_id(const struct cpumask *cpumask) if (first_cpu_of_numa_node >= nr_cpu_ids) return -1; #ifdef CONFIG_X86_64 +#ifdef HAVE_CPUINFO_TOPOLOGY_IN_CPUINFO_X86_STRUCT return cpu_data(first_cpu_of_numa_node).topo.apicid; +#else + return cpu_data(first_cpu_of_numa_node).apicid; +#endif #else return first_cpu_of_numa_node; #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d69b78822722e..443e3e8981259 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -222,6 +222,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD AC_AMDGPU_DMA_FENCE_TIMESTAMP AC_AMDGPU_VMA_IS_INITIAL + AC_AMDGPU_CPUINFO_X86 AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/processor.m4 b/drivers/gpu/drm/amd/dkms/m4/processor.m4 new file mode 100644 index 0000000000000..66dececcd8989 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/processor.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v6.6-rc1-4-gb9655e702dc5 +dnl # x86/cpu: Encapsulate topology information in cpuinfo_x86 +dnl # +AC_DEFUN([AC_AMDGPU_CPUINFO_X86], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct cpuinfo_x86* cpuinfo = NULL; + struct cpuinfo_topology topo; + topo = cpuinfo -> topo; + ],[ + AC_DEFINE(HAVE_CPUINFO_TOPOLOGY_IN_CPUINFO_X86_STRUCT, 1, + [ cpuinfo_x86.topo is available]) + ]) + ]) +]) From 960a66c9ba356137f3431f4c7b9e33b85bb6db98 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 6 Dec 2023 17:53:42 +0800 Subject: [PATCH 1166/2653] drm/amdkcl: update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 28 ++++++++++++++---------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3920f051c488d..9a762166f2fe2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -35,7 +35,7 @@ #define HAVE_AMDKCL_HMM_MIRROR_ENABLED 1 /* amd_iommu_invalidate_ctx take arg type of pasid as u32 */ -#define HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 1 +/* #undef HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 */ /* amd_iommu_pc_get_max_banks() declared */ #define HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED 1 @@ -82,6 +82,9 @@ /* compat_ptr_ioctl() is available */ #define HAVE_COMPAT_PTR_IOCTL 1 +/* cpuinfo_x86.topo is available */ +#define HAVE_CPUINFO_TOPOLOGY_IN_CPUINFO_X86_STRUCT 1 + /* debugfs_create_file_size() is available */ #define HAVE_DEBUGFS_CREATE_FILE_SIZE 1 @@ -133,11 +136,8 @@ /* struct dma_fence_ops has use_64bit_seqno field */ #define HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO 1 -/* dma_fence_set_error() is available */ -#define HAVE_DMA_FENCE_SET_ERROR 1 - -/* dma_map_resource() is enabled */ -#define HAVE_DMA_MAP_RESOURCE 1 +/* dma_fence_TIMESTAMP() is available */ +#define HAVE_DMA_FENCE_TIMESTAMP 1 /* dma_map_sgtable() is enabled */ #define HAVE_DMA_MAP_SGTABLE 1 @@ -898,8 +898,8 @@ /* struct pci_driver has field dev_groups */ #define HAVE_PCI_DRIVER_DEV_GROUPS 1 -/* pci_is_thunderbolt_attached() is available */ -#define HAVE_PCI_IS_THUNDERBOLD_ATTACHED 1 +/* pci_get_base_class() is available */ +#define HAVE_PCI_GET_BASE_CLASS 1 /* pci_pr3_present() is available */ #define HAVE_PCI_PR3_PRESENT 1 @@ -935,7 +935,7 @@ #define HAVE_RB_ROOT_CACHED 1 /* whether register_shrinker(x, x) is available */ -#define HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS 1 +/* #undef HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS */ /* remove_conflicting_pci_framebuffers() wants p,p args */ /* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ @@ -946,6 +946,9 @@ /* seq_hex_dump() is available */ #define HAVE_SEQ_HEX_DUMP 1 +/* shrinker_register() is available */ +#define HAVE_SHRINKER_REGISTER 1 + /* smca_get_bank_type(x) is available */ /* #undef HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT */ @@ -1017,7 +1020,7 @@ #define HAVE_STR_YES_NO 1 /* synchronize_shrinkers() is available */ -#define HAVE_SYNCHRONIZE_SHRINKERS 1 +/* #undef HAVE_SYNCHRONIZE_SHRINKERS */ /* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 @@ -1040,6 +1043,9 @@ /* vga_switcheroo_set_dynamic_switch() exist */ /* #undef HAVE_VGA_SWITCHEROO_SET_DYNAMIC_SWITCH */ +/* vma_is_initial_{heap, stack} is available */ +#define HAVE_VMA_IS_INITIAL_HEAP 1 + /* vma_lookup() is available */ #define HAVE_VMA_LOOKUP 1 @@ -1098,7 +1104,7 @@ #define HAVE___DRM_ATOMIC_HELPER_CRTC_RESET 1 /* __kthread_should_park() is available */ -#define HAVE___KTHREAD_SHOULD_PARK 1 +/* #undef HAVE___KTHREAD_SHOULD_PARK */ /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" From a7ef57939e5b9b817e774c879f9c5e1a8a8c71f2 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 7 Dec 2023 17:25:32 +0800 Subject: [PATCH 1167/2653] drm/amdkcl: fake dma_fence_is_later_or_same It's caused by v6.7-rc1-17-g95ba893c9f4f dma-buf: fix check in dma_resv_add_fence Signed-off-by: Asher Song --- .../gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma_fence.h | 8 ++++++++ 3 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 index bbc3eb8117f9c..0523264d08807 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 @@ -28,3 +28,19 @@ AC_DEFUN([AC_AMDGPU__DMA_FENCE_IS_LATER], [ ]) ]) ]) + +dnl # +dnl # v6.7-rc1-17-g95ba893c9f4f +dnl # dma-buf: fix check in dma_resv_add_fence +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_IS_LATER_OR_SAME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_is_later_or_same(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_IS_LATER_OR_SAME, 1, [dma_fence_is_later_or_same() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 443e3e8981259..dcec3ece0d776 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -223,6 +223,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_TIMESTAMP AC_AMDGPU_VMA_IS_INITIAL AC_AMDGPU_CPUINFO_X86 + AC_AMDGPU_DMA_FENCE_IS_LATER_OR_SAME AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_dma_fence.h b/include/kcl/kcl_dma_fence.h index ae63b65466e00..a24278c214244 100644 --- a/include/kcl/kcl_dma_fence.h +++ b/include/kcl/kcl_dma_fence.h @@ -66,4 +66,12 @@ static inline ktime_t dma_fence_timestamp(struct dma_fence *fence) } #endif +/* copy from include/linux/dma-fence.h*/ +#ifndef HAVE_DMA_FENCE_IS_LATER_OR_SAME +static inline bool dma_fence_is_later_or_same(struct dma_fence *f1, + struct dma_fence *f2) +{ + return f1 == f2 || dma_fence_is_later(f1, f2); +} +#endif /*HAVE_DMA_FENCE_IS_LATER_OR_SAME*/ #endif From e2dafb648f6f7b2fe269a42d7fb591af0b827d88 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 5 Dec 2023 15:23:43 +0800 Subject: [PATCH 1168/2653] drm/amdkcl: tset whether list_cmp_func is const param It's caused by 93de84df60bc71c5f0d95de84a71eb119b51afe1 "drm/amdgpu: optimize the printing order of error data" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/list-sort.m4 | 18 ++++++++++++++++++ 4 files changed, 25 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/list-sort.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 0f06793e7ec05..0a840f143f0c5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -5152,7 +5152,11 @@ static struct ras_err_node *amdgpu_ras_error_node_new(void) return err_node; } +#ifdef HAVE_LIST_CMP_FUNC_IS_CONST_PARAM static int ras_err_info_cmp(void *priv, const struct list_head *a, const struct list_head *b) +#else +static int ras_err_info_cmp(void *priv, struct list_head *a, struct list_head *b) +#endif { struct ras_err_node *nodea = container_of(a, struct ras_err_node, node); struct ras_err_node *nodeb = container_of(b, struct ras_err_node, node); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9a762166f2fe2..72be60c4d66b2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -829,8 +829,8 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_XARRAY_H 1 -/* list_bulk_move_tail() is available */ -#define HAVE_LIST_BULK_MOVE_TAIL 1 +/* list_cmp_func() is const param */ +#define HAVE_LIST_CMP_FUNC_IS_CONST_PARAM 1 /* list_is_first() is available */ #define HAVE_LIST_IS_FIRST 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index dcec3ece0d776..3db7751d8e9c7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -212,6 +212,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VM_FLAGS_SET AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED AC_AMDGPU_PID_TYPE + AC_AMDGPU_LIST_CMP_FUNC_IS_CONST_PARAM AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE AC_AMDGPU_DRM_SHOW_FDINFO AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG diff --git a/drivers/gpu/drm/amd/dkms/m4/list-sort.m4 b/drivers/gpu/drm/amd/dkms/m4/list-sort.m4 new file mode 100644 index 0000000000000..aa7b739d04961 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/list-sort.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.12-rc6-9-g4f0f586bf0c8 +dnl # treewide: Change list_sort to use const pointers +dnl # +AC_DEFUN([AC_AMDGPU_LIST_CMP_FUNC_IS_CONST_PARAM], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + list_cmp_func_t cmp = NULL; + struct list_head a, b; + cmp(NULL, &a, &b); + ], [ + AC_DEFINE(HAVE_LIST_CMP_FUNC_IS_CONST_PARAM, 1, + [list_cmp_func() is const param]) + ]) + ]) +]) \ No newline at end of file From 9be232c53908baa18e6d0368a45b39ee54a425d4 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Tue, 21 Nov 2023 16:47:57 +0800 Subject: [PATCH 1169/2653] drm/amd/kcl: fix issue of missing mca-debug-mode debugfs node v1: fix issue of missing mca-debug-mode debugfs node. v2: using helper macro DEFINE_SIMPLE_ATTRIBUTE to simple code Fixes: 96e2072e93c0 ("drm/amdkcl: wrap code under macro DEFINE_DEBUGFS_ATTRIBUTE") Signed-off-by: Yang Wang Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c index 91d4819cd7f12..78a89601e4e5e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c @@ -615,6 +615,8 @@ static const struct file_operations mca_ue_dump_debug_fops = { #ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_set, "%llu\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_set, "%llu\n"); #endif #endif @@ -624,9 +626,7 @@ void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root if (!root) return; -#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file("mca_debug_mode", 0200, root, adev, &mca_debug_mode_fops); -#endif debugfs_create_file("mca_ue_dump", 0400, root, adev, &mca_ue_dump_debug_fops); debugfs_create_file("mca_ce_dump", 0400, root, adev, &mca_ce_dump_debug_fops); #endif From 97473fddf87f97973aa15a5b6fe32baddc0a222d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 4 Dec 2023 15:54:47 +0800 Subject: [PATCH 1170/2653] drm/amdkcl: reduce argunemts of kgd2kfd_resume To aliagn with kgd2kfd_resume prototype, reduce arguments of dummy kgd2kfd_resume. Signed-off-by: Asher Song Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index ed53850e9b295..db04d68a0bb3a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -534,7 +534,7 @@ static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc, bool { } -static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm, bool sync) +static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) { return 0; } From 3614d50eaf1dbae69425e37654a28f67e4217725 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 7 Dec 2023 13:46:52 +0800 Subject: [PATCH 1171/2653] drm/amdkcl: update config.h It's caused by 9a893b4afa61a72b3a81dd334c210fdb4ca93154 Revert "drm/prime: Unexport helpers for fd/handle conversion" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 72be60c4d66b2..d68e21bae9efe 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -535,7 +535,7 @@ #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 /* drm_gem_prime_handle_to_fd() is available */ -/* #undef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD */ +#define HAVE_DRM_GEM_PRIME_HANDLE_TO_FD 1 /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 From 16747886f3c9909488a06e1682d479bf4db070c4 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 7 Dec 2023 11:13:44 +0800 Subject: [PATCH 1172/2653] drm/amdkcl: fake drm_client_register() It's caused by 6a56a446d0dfd620c451772f742c20dafa9fe83b "drm/amdkfd: Export DMABufs from KFD using GEM handles" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm_client_register.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_client.h | 14 ++++++++++++++ 5 files changed, 35 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_client_register.m4 create mode 100644 include/kcl/kcl_drm_client.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a504ed69b614e..a5442efc9dcbe 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -118,4 +118,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d68e21bae9efe..fb72dc472797e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -176,6 +176,9 @@ /* drm_atomic_helper_calc_timestamping_constants() is available */ #define HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS 1 +/* drm_client_register() is available */ +#define HAVE_DRM_CLIENT_REGISTER 1 + /* drm_connector_atomic_hdr_metadata_equal() is available */ #define HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_client_register.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_client_register.m4 new file mode 100644 index 0000000000000..ef060260bee20 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_client_register.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.1-rc2-1103-ge33898a20744 +dnl # drm/client: Rename drm_client_add() to drm_client_register() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CLIENT_REGISTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_client_register(NULL); + ],[ + AC_DEFINE(HAVE_DRM_CLIENT_REGISTER, 1, + [drm_client_register() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3db7751d8e9c7..e8f24b1c2769f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -219,6 +219,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_AMDGPU_LINUX_DEVICE_CLASS AC_AMDGPU_KVREALLOC + AC_AMDGPU_DRM_CLIENT_REGISTER AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD AC_AMDGPU_DMA_FENCE_TIMESTAMP diff --git a/include/kcl/kcl_drm_client.h b/include/kcl/kcl_drm_client.h new file mode 100644 index 0000000000000..0857e2fc2cd65 --- /dev/null +++ b/include/kcl/kcl_drm_client.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef KCL_KCL_DRM_CLIENT_H +#define KCL_KCL_DRM_CLIENT_H + +#include + +#ifndef HAVE_DRM_CLIENT_REGISTER +static inline void drm_client_register(struct drm_client_dev *client) +{ + drm_client_add(client); +} +#endif /* HAVE_DRM_CLIENT_REGISTER */ + +#endif From 2fff964364466fe9ea214f35fb1e4d691484a6f9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 15 Dec 2023 10:57:13 +0800 Subject: [PATCH 1173/2653] drm/amdkcl: fake drm_dbg_driver() It's casued by eb826a227c7d72fecb1b40d49d1d6ec611fa4219 "drm/amd/display: add plane shaper LUT support" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- include/kcl/kcl_drm_print.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index c1aa05a71ff23..e2855aa2a299d 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -142,6 +142,11 @@ void kcl_drm_err(const char *format, ...); drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DP, fmt, ##__VA_ARGS__) #endif +#if !defined(drm_dbg_driver) +#define drm_dbg_driver(drm, fmt, ...) \ + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DRIVER, fmt, ##__VA_ARGS__) +#endif + #ifndef HAVE_DRM_DEBUG_ENABLED /* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ static inline bool drm_debug_enabled(unsigned int category) From 469f549804acbd0c5047e5e8515073cac7d6bc30 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 23 Aug 2024 18:54:39 +0800 Subject: [PATCH 1174/2653] drm/amdkcl: check whether acpi_amd_wbrf.h exist It's caused by v6.7-rc1-2-g58e82a62669d platform/x86/amd: Add support for AMD ACPI based Wifi band RFI mitigation feature Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_wbrf.c | 319 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 + include/kcl/header/linux/acpi_amd_wbrf.h | 9 + include/kcl/kcl_acpi_amd_wbrf.h | 94 ++++++ 6 files changed, 429 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_wbrf.c create mode 100644 include/kcl/header/linux/acpi_amd_wbrf.h create mode 100644 include/kcl/kcl_acpi_amd_wbrf.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 49b0fe52e6ddc..d5a8a1db57bac 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -20,7 +20,7 @@ amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o kcl_debugfs_file.o amdkcl-$(CONFIG_SYSFS) += kcl_sysfs_emit.o - +amdkcl-$(CONFIG_AMD_WBRF) += kcl_wbrf.o CFLAGS_kcl_fence.o := -I$(src) ccflags-y += \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_wbrf.c b/drivers/gpu/drm/amd/amdkcl/kcl_wbrf.c new file mode 100644 index 0000000000000..3299b4e78c7a7 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_wbrf.c @@ -0,0 +1,319 @@ +//SPDX-License-Identifier: GPL-2.0 +/* + * Wifi Frequency Band Manage Interface + * Copyright (C) 2023 Advanced Micro Devices + */ + +#include +#include + +#ifndef HAVE_LINUX_ACPI_AMD_WBRF_H +/* + * Functions bit vector for WBRF method + * + * Bit 0: WBRF supported. + * Bit 1: Function 1 (Add / Remove frequency) is supported. + * Bit 2: Function 2 (Get frequency list) is supported. + */ +#define WBRF_ENABLED 0x0 +#define WBRF_RECORD 0x1 +#define WBRF_RETRIEVE 0x2 + +#define WBRF_REVISION 0x1 + +/* + * The data structure used for WBRF_RETRIEVE is not naturally aligned. + * And unfortunately the design has been settled down. + */ +struct amd_wbrf_ranges_out { + u32 num_of_ranges; + struct freq_band_range band_list[MAX_NUM_OF_WBRF_RANGES]; +} __packed; + +static const guid_t wifi_acpi_dsm_guid = + GUID_INIT(0x7b7656cf, 0xdc3d, 0x4c1c, + 0x83, 0xe9, 0x66, 0xe7, 0x21, 0xde, 0x30, 0x70); + +/* + * Used to notify consumer (amdgpu driver currently) about + * the wifi frequency is change. + */ +static BLOCKING_NOTIFIER_HEAD(wbrf_chain_head); + +static int wbrf_record(struct acpi_device *adev, uint8_t action, struct wbrf_ranges_in_out *in) +{ + union acpi_object argv4; + union acpi_object *tmp; + union acpi_object *obj; + u32 num_of_ranges = 0; + u32 num_of_elements; + u32 arg_idx = 0; + int ret; + u32 i; + + if (!in) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(in->band_list); i++) { + if (in->band_list[i].start && in->band_list[i].end) + num_of_ranges++; + } + + /* + * The num_of_ranges value in the "in" object supplied by + * the caller is required to be equal to the number of + * entries in the band_list array in there. + */ + if (num_of_ranges != in->num_of_ranges) + return -EINVAL; + + /* + * Every input frequency band comes with two end points(start/end) + * and each is accounted as an element. Meanwhile the range count + * and action type are accounted as an element each. + * So, the total element count = 2 * num_of_ranges + 1 + 1. + */ + num_of_elements = 2 * num_of_ranges + 2; + + tmp = kcalloc(num_of_elements, sizeof(*tmp), GFP_KERNEL); + if (!tmp) + return -ENOMEM; + + argv4.package.type = ACPI_TYPE_PACKAGE; + argv4.package.count = num_of_elements; + argv4.package.elements = tmp; + + /* save the number of ranges*/ + tmp[0].integer.type = ACPI_TYPE_INTEGER; + tmp[0].integer.value = num_of_ranges; + + /* save the action(WBRF_RECORD_ADD/REMOVE/RETRIEVE) */ + tmp[1].integer.type = ACPI_TYPE_INTEGER; + tmp[1].integer.value = action; + + arg_idx = 2; + for (i = 0; i < ARRAY_SIZE(in->band_list); i++) { + if (!in->band_list[i].start || !in->band_list[i].end) + continue; + + tmp[arg_idx].integer.type = ACPI_TYPE_INTEGER; + tmp[arg_idx++].integer.value = in->band_list[i].start; + tmp[arg_idx].integer.type = ACPI_TYPE_INTEGER; + tmp[arg_idx++].integer.value = in->band_list[i].end; + } + + obj = acpi_evaluate_dsm(adev->handle, &wifi_acpi_dsm_guid, + WBRF_REVISION, WBRF_RECORD, &argv4); + + if (!obj) + return -EINVAL; + + if (obj->type != ACPI_TYPE_INTEGER) { + ret = -EINVAL; + goto out; + } + + ret = obj->integer.value; + if (ret) + ret = -EINVAL; + +out: + ACPI_FREE(obj); + kfree(tmp); + + return ret; +} + +/** + * acpi_amd_wbrf_add_remove - add or remove the frequency band the device is using + * + * @dev: device pointer + * @action: remove or add the frequency band into bios + * @in: input structure containing the frequency band the device is using + * + * Broadcast to other consumers the frequency band the device starts + * to use. Underneath the surface the information is cached into an + * internal buffer first. Then a notification is sent to all those + * registered consumers. So then they can retrieve that buffer to + * know the latest active frequency bands. Consumers that haven't + * yet been registered can retrieve the information from the cache + * when they register. + * + * Return: + * 0 for success add/remove wifi frequency band. + * Returns a negative error code for failure. + */ +int acpi_amd_wbrf_add_remove(struct device *dev, uint8_t action, struct wbrf_ranges_in_out *in) +{ + struct acpi_device *adev; + int ret; + + adev = ACPI_COMPANION(dev); + if (!adev) + return -ENODEV; + + ret = wbrf_record(adev, action, in); + if (ret) + return ret; + + blocking_notifier_call_chain(&wbrf_chain_head, WBRF_CHANGED, NULL); + + return 0; +} +EXPORT_SYMBOL_GPL(acpi_amd_wbrf_add_remove); + +/** + * acpi_amd_wbrf_supported_producer - determine if the WBRF can be enabled + * for the device as a producer + * + * @dev: device pointer + * + * Check if the platform equipped with necessary implementations to + * support WBRF for the device as a producer. + * + * Return: + * true if WBRF is supported, otherwise returns false + */ +bool acpi_amd_wbrf_supported_producer(struct device *dev) +{ + struct acpi_device *adev; + + adev = ACPI_COMPANION(dev); + if (!adev) + return false; + + return acpi_check_dsm(adev->handle, &wifi_acpi_dsm_guid, + WBRF_REVISION, BIT(WBRF_RECORD)); +} +EXPORT_SYMBOL_GPL(acpi_amd_wbrf_supported_producer); + +/** + * acpi_amd_wbrf_supported_consumer - determine if the WBRF can be enabled + * for the device as a consumer + * + * @dev: device pointer + * + * Determine if the platform equipped with necessary implementations to + * support WBRF for the device as a consumer. + * + * Return: + * true if WBRF is supported, otherwise returns false. + */ +bool acpi_amd_wbrf_supported_consumer(struct device *dev) +{ + struct acpi_device *adev; + + adev = ACPI_COMPANION(dev); + if (!adev) + return false; + + return acpi_check_dsm(adev->handle, &wifi_acpi_dsm_guid, + WBRF_REVISION, BIT(WBRF_RETRIEVE)); +} +EXPORT_SYMBOL_GPL(acpi_amd_wbrf_supported_consumer); + +/** + * amd_wbrf_retrieve_freq_band - retrieve current active frequency bands + * + * @dev: device pointer + * @out: output structure containing all the active frequency bands + * + * Retrieve the current active frequency bands which were broadcasted + * by other producers. The consumer who calls this API should take + * proper actions if any of the frequency band may cause RFI with its + * own frequency band used. + * + * Return: + * 0 for getting wifi freq band successfully. + * Returns a negative error code for failure. + */ +int amd_wbrf_retrieve_freq_band(struct device *dev, struct wbrf_ranges_in_out *out) +{ + struct amd_wbrf_ranges_out acpi_out = {0}; + struct acpi_device *adev; + union acpi_object *obj; + union acpi_object param; + int ret = 0; + + adev = ACPI_COMPANION(dev); + if (!adev) + return -ENODEV; + + param.type = ACPI_TYPE_STRING; + param.string.length = 0; + param.string.pointer = NULL; + + obj = acpi_evaluate_dsm(adev->handle, &wifi_acpi_dsm_guid, + WBRF_REVISION, WBRF_RETRIEVE, ¶m); + if (!obj) + return -EINVAL; + + /* + * The return buffer is with variable length and the format below: + * number_of_entries(1 DWORD): Number of entries + * start_freq of 1st entry(1 QWORD): Start frequency of the 1st entry + * end_freq of 1st entry(1 QWORD): End frequency of the 1st entry + * ... + * ... + * start_freq of the last entry(1 QWORD) + * end_freq of the last entry(1 QWORD) + * + * Thus the buffer length is determined by the number of entries. + * - For zero entry scenario, the buffer length will be 4 bytes. + * - For one entry scenario, the buffer length will be 20 bytes. + */ + if (obj->buffer.length > sizeof(acpi_out) || obj->buffer.length < 4) { + dev_err(dev, "Wrong sized WBRT information"); + ret = -EINVAL; + goto out; + } + memcpy(&acpi_out, obj->buffer.pointer, obj->buffer.length); + + out->num_of_ranges = acpi_out.num_of_ranges; + memcpy(out->band_list, acpi_out.band_list, sizeof(acpi_out.band_list)); + +out: + ACPI_FREE(obj); + return ret; +} +EXPORT_SYMBOL_GPL(amd_wbrf_retrieve_freq_band); + +/** + * amd_wbrf_register_notifier - register for notifications of frequency + * band update + * + * @nb: driver notifier block + * + * The consumer should register itself via this API so that it can get + * notified on the frequency band updates from other producers. + * + * Return: + * 0 for registering a consumer driver successfully. + * Returns a negative error code for failure. + */ +int amd_wbrf_register_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&wbrf_chain_head, nb); +} +EXPORT_SYMBOL_GPL(amd_wbrf_register_notifier); + +/** + * amd_wbrf_unregister_notifier - unregister for notifications of + * frequency band update + * + * @nb: driver notifier block + * + * The consumer should call this API when it is longer interested with + * the frequency band updates from other producers. Usually, this should + * be performed during driver cleanup. + * + * Return: + * 0 for unregistering a consumer driver. + * Returns a negative error code for failure. + */ +int amd_wbrf_unregister_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&wbrf_chain_head, nb); +} +EXPORT_SYMBOL_GPL(amd_wbrf_unregister_notifier); +#endif /*HAVE_LINUX_ACPI_AMD_WBRF_H*/ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a5442efc9dcbe..f82375d7f8f10 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -119,4 +119,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index a9a77d3a9cdf4..88fa953aa980a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -129,4 +129,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #bug: split BUILD_BUG stuff out into dnl AC_KERNEL_CHECK_HEADERS([linux/build_bug.h]) + + dnl #v6.7-rc1-2-g58e82a62669d + dnl #platform/x86/amd: Add support for AMD ACPI based Wifi band RFI mitigation feature + dnl + AC_KERNEL_CHECK_HEADERS([linux/acpi_amd_wbrf.h]) ]) diff --git a/include/kcl/header/linux/acpi_amd_wbrf.h b/include/kcl/header/linux/acpi_amd_wbrf.h new file mode 100644 index 0000000000000..ecf5be29494d4 --- /dev/null +++ b/include/kcl/header/linux/acpi_amd_wbrf.h @@ -0,0 +1,9 @@ +#ifndef _KCL_HEADER___ACPI_AMD_WBRF_H___H_ +#define _KCL_HEADER___ACPI_AMD_WBRF_H___H_ + +#ifdef HAVE_LINUX_ACPI_AMD_WBRF_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_acpi_amd_wbrf.h b/include/kcl/kcl_acpi_amd_wbrf.h new file mode 100644 index 0000000000000..b8178e740f171 --- /dev/null +++ b/include/kcl/kcl_acpi_amd_wbrf.h @@ -0,0 +1,94 @@ +/*Copy from include/linux/acpi_amd_wbrf.h*/ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Wifi Band Exclusion Interface (AMD ACPI Implementation) + * Copyright (C) 2023 Advanced Micro Devices + */ + +#ifndef _KCL_ACPI_AMD_WBRF_H +#define _KCL_ACPI_AMD_WBRF_H + +#ifndef HAVE_LINUX_ACPI_AMD_WBRF_H +#include +#include + +/* The maximum number of frequency band ranges */ +#define MAX_NUM_OF_WBRF_RANGES 11 + +/* Record actions */ +#define WBRF_RECORD_ADD 0x0 +#define WBRF_RECORD_REMOVE 0x1 + +/** + * struct freq_band_range - Wifi frequency band range definition + * @start: start frequency point (in Hz) + * @end: end frequency point (in Hz) + */ +struct freq_band_range { + u64 start; + u64 end; +}; + +/** + * struct wbrf_ranges_in_out - wbrf ranges info + * @num_of_ranges: total number of band ranges in this struct + * @band_list: array of Wifi band ranges + */ +struct wbrf_ranges_in_out { + u64 num_of_ranges; + struct freq_band_range band_list[MAX_NUM_OF_WBRF_RANGES]; +}; + +/** + * enum wbrf_notifier_actions - wbrf notifier actions index + * @WBRF_CHANGED: there was some frequency band updates. The consumers + * should retrieve the latest active frequency bands. + */ +enum wbrf_notifier_actions { + WBRF_CHANGED, +}; + +#if IS_ENABLED(CONFIG_AMD_WBRF) +bool acpi_amd_wbrf_supported_producer(struct device *dev); +int acpi_amd_wbrf_add_remove(struct device *dev, uint8_t action, struct wbrf_ranges_in_out *in); +bool acpi_amd_wbrf_supported_consumer(struct device *dev); +int amd_wbrf_retrieve_freq_band(struct device *dev, struct wbrf_ranges_in_out *out); +int amd_wbrf_register_notifier(struct notifier_block *nb); +int amd_wbrf_unregister_notifier(struct notifier_block *nb); +#else +static inline +bool acpi_amd_wbrf_supported_consumer(struct device *dev) +{ + return false; +} + +static inline +int acpi_amd_wbrf_add_remove(struct device *dev, uint8_t action, struct wbrf_ranges_in_out *in) +{ + return -ENODEV; +} + +static inline +bool acpi_amd_wbrf_supported_producer(struct device *dev) +{ + return false; +} +static inline +int amd_wbrf_retrieve_freq_band(struct device *dev, struct wbrf_ranges_in_out *out) +{ + return -ENODEV; +} +static inline +int amd_wbrf_register_notifier(struct notifier_block *nb) +{ + return -ENODEV; +} +static inline +int amd_wbrf_unregister_notifier(struct notifier_block *nb) +{ + return -ENODEV; +} +#endif /* CONFIG_AMD_WBRF */ + +#endif /* HAVE_LINUX_ACPI_AMD_WBRF */ +#endif /* _KCL_ACPI_AMD_WBRF_H */ From 1c4714dbf326246cde27006bc0d53abf8909d032 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Dec 2023 17:15:52 +0800 Subject: [PATCH 1175/2653] drm/amdkcl: check whether drm/drm_eld.h exist It's caused by v6.6-rc2-771-g8eb80946ab0c drm/edid: split out drm_eld.h from drm_edid.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 5 +++++ include/kcl/header/drm/drm_eld.h | 9 +++++++++ 2 files changed, 14 insertions(+) create mode 100644 include/kcl/header/drm/drm_eld.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 76f76c549528a..6dd1ab847b3bb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -105,4 +105,9 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_exec.h]) + dnl # + dnl # v6.6-rc2-771-g8eb80946ab0c + dnl # drm/edid: split out drm_eld.h from drm_edid.h + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_eld.h]) ]) diff --git a/include/kcl/header/drm/drm_eld.h b/include/kcl/header/drm/drm_eld.h new file mode 100644 index 0000000000000..e531edccae0d7 --- /dev/null +++ b/include/kcl/header/drm/drm_eld.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_ELD_H_ +#define _KCL_HEADER_DRM_ELD_H_H_ + +#ifdef HAVE_DRM_DRM_ELD_H +#include_next +#endif + +#endif From 3edab8bb2a4d6c0785144ca3d5f1ce49000c57cd Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 21 Dec 2023 14:19:22 +0800 Subject: [PATCH 1176/2653] drm/amdkcl: test drm_dp_calc_pbn_mode whether has two argument It's caused by v6.6-rc2-668-g7707dd602259 drm/dp_mst: Fix fractional DSC bpp handling Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 | 7 +++++-- include/kcl/backport/kcl_drm_dp_mst_helper_backport.h | 11 ++++++++--- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 13789b7434628..42cb16554b677 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8102,7 +8102,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, max_bpc); bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; clock = adjusted_mode->clock; - dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4); + dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false); } dm_new_connector_state->vcpi_slots = diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 index d168a591bcd23..7261c98f40b18 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 @@ -1,7 +1,10 @@ dnl # -dnl # commit 9a7c0da823fd4e65098bd466a996503cc8309c0e +dnl # commit v5.5-rc2-902-gdc48529fb14e dnl # drm/dp_mst: Add PBN calculation for DSC modes dnl # +dnl #v6.6-rc2-668-g7707dd602259 +dnl #drm/dp_mst: Fix fractional DSC bpp handling +dnl AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ @@ -10,7 +13,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ drm_dp_calc_pbn_mode(0, 0, 0); ], [ AC_DEFINE(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS, 1, - [drm_dp_calc_pbn_mode() wants 3args]) + [drm_dp_calc_pbn_mode() wants 3 args]) ]) ]) ]) diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index c6de78678e856..9791910ed58b0 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -25,15 +25,20 @@ #include /* Copied from drivers/gpu/drm/drm_dp_mst_topology.c and modified for KCL */ -#if !defined(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS) +#ifndef HAVE_DRM_DP_CALC_PBN_MODE_3ARGS static inline int _kcl_drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) { +#ifndef HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H if (dsc) return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006), 8 * 54 * 1000 * 1000); - - return drm_dp_calc_pbn_mode(clock, bpp); +#endif + return drm_dp_calc_pbn_mode(clock, bpp +#ifdef HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H + << 4 +#endif + ); } #define drm_dp_calc_pbn_mode _kcl_drm_dp_calc_pbn_mode #endif From 788bb239aee8b5b24c955c4ecd5daec79f7c65c7 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 21 Dec 2023 16:14:20 +0800 Subject: [PATCH 1177/2653] drm/amdkcl: test struct drm_dp_mst_topology_state whether has union member pbn_div It's caused by v6.6-rc2-733-g191dc43935d1 drm/dp_mst: Store the MST PBN divider value in fixed point format Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++++++---- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 5 +++++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 12 ++++++++---- .../amd/dkms/m4/drm-dp-mst-topology-state.m4 | 19 +++++++++++++++---- 4 files changed, 35 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 42cb16554b677..e3daa82dd6673 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8051,7 +8051,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; struct drm_dp_mst_topology_mgr *mst_mgr; struct drm_dp_mst_port *mst_port; -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) || defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) struct drm_dp_mst_topology_state *mst_state; #endif enum dc_color_depth color_depth; @@ -8084,12 +8084,15 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, if (!crtc_state->connectors_changed && !crtc_state->mode_changed) return 0; -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) || defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); if (IS_ERR(mst_state)) return PTR_ERR(mst_state); - +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link)); +#else + mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); +#endif #endif if (!state->duplicated) { @@ -12374,7 +12377,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_connector_list_iter iter; u8 link_coding_cap; -#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#if !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) && !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) if (!mgr->mst_state ) continue; #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index e1f6a51acf88b..e2a3f4283c2d0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -317,7 +317,12 @@ static void dm_helpers_construct_old_payload( struct drm_dp_mst_atomic_payload *old_payload) { struct drm_dp_mst_atomic_payload *pos; +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION int pbn_per_slot = dfixed_trunc(mst_state->pbn_div); +#elif HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT + int pbn_per_slot = mst_state->pbn_div; +#endif + u8 next_payload_vc_start = mgr->next_start_slot; u8 payload_vc_start = new_payload->vc_start_slot; u8 allocated_time_slots; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index b447afffbc95a..9c275e15e5f19 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1128,7 +1128,7 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, int min_initial_slack; int next_index; int remaining_to_increase = 0; -#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#if !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) && !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) int pbn_per_timeslot; #endif int link_timeslots_used; @@ -1136,7 +1136,7 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, int ret = 0; uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); -#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#if !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) && !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) pbn_per_timeslot = dm_mst_get_pbn_divider(dc_link); #endif @@ -1171,8 +1171,10 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, for (i = 0; i < count; i++) link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION dfixed_trunc(mst_state->pbn_div) +#elif HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT + mst_state->pbn_div #else pbn_per_timeslot #endif @@ -1180,8 +1182,10 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION dfixed_trunc(mst_state->pbn_div); +#elif HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT + mst_state->pbn_div; #else pbn_per_timeslot; #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index 5ac79129a86fe..424778ea6606b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -44,14 +44,25 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #include + #include ], [ struct drm_dp_mst_topology_state * mst_state = NULL; - int pbn_div; - pbn_div = mst_state->pbn_div; + mst_state->pbn_div = 0; ], [ - AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV, 1, + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT, 1, [struct drm_dp_mst_topology_state has member pbn_div]) + ]) + ]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_state * mst_state = NULL; + fixed20_12 pbn_div; + pbn_div = mst_state->pbn_div; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION, 1, + [struct drm_dp_mst_topology_state has union member pbn_div]) ]) ]) ]) From a8bb1b7358aa9baf9e11ed660e3de29c733ed9b0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 22 Dec 2023 10:50:30 +0800 Subject: [PATCH 1178/2653] drm/amdkcl: fake drm_WARN_ON It's caused by a78422e9dff366b3a46ae44caf6ec8ded9c9fc2f drm/sched: implement dynamic job-flow control Signed-off-by: Asher Song --- drivers/gpu/drm/scheduler/backport/backport.h | 1 + include/kcl/kcl_drm_print.h | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 8b9c265bf8bce..04ad51ff373e2 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -9,4 +9,5 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index e2855aa2a299d..888592871d7ca 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -54,6 +54,19 @@ dev_name((drm)->dev), ## arg) #endif +#ifndef drm_WARN +#define drm_WARN(drm, condition, format, arg...) \ + WARN(condition, "%s %s: " format, \ + dev_driver_string((drm)->dev), \ + dev_name((drm)->dev), ## arg) +#endif + +#ifndef drm_WARN_ON +#define drm_WARN_ON(drm, x) \ + drm_WARN((drm), (x), "%s", \ + "drm_WARN_ON(" __stringify(x) ")") +#endif + #ifndef DRM_NOTE #define DRM_NOTE(fmt, ...) \ _DRM_PRINTK(, NOTICE, fmt, ##__VA_ARGS__) From e0eabea81c4b0ea28c1c6ae975ce61e8fe6049c8 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 25 Mar 2024 17:15:20 +0800 Subject: [PATCH 1179/2653] drm/amdkcl: fake queue_work_node It's caused by v6.7-rc1-196-gb0a7ce53d494 drm/ttm: Schedule delayed_delete worker closer Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 | 22 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/backport/kcl_workqueue_backport.h | 10 +++++++++ 4 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 index 1f0558d0ade28..a9167fe9d15c0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 @@ -15,3 +15,25 @@ AC_DEFUN([AC_AMDGPU_CANCEL_WORK], [ ]) ]) ]) + +dnl # +dnl # commit id:v5.0-rc2-28-g8204e0c1113d +dnl # workqueue: Provide queue_work_node to queue work near a given NUMA node +dnl # +AC_DEFUN([AC_AMDGPU_QUEUE_WORK_NODE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + queue_work_node(0,NULL, NULL); + ], [queue_work_node], [kernel/workqueue.c], [ + AC_DEFINE(HAVE_QUEUE_WORK_NODE, 1, + [queue_work_node() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_WORKQUEUE], [ + AC_AMDGPU_CANCEL_WORK + AC_AMDGPU_QUEUE_WORK_NODE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e8f24b1c2769f..702c80e0aba00 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -180,7 +180,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_X86_HYPERVISOR_TYPE AC_AMDGPU_HYPERVISOR_IS_TYPE AC_AMDGPU_PCI_DEV_LTR_PATH - AC_AMDGPU_CANCEL_WORK AC_AMDGPU_DMA_FENCE_IS_CONTAINER AC_AMDGPU_STR_YES_NO AC_AMDGPU_TOTALRAM_PAGES @@ -226,6 +225,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMA_IS_INITIAL AC_AMDGPU_CPUINFO_X86 AC_AMDGPU_DMA_FENCE_IS_LATER_OR_SAME + AC_AMDGPU_WORKQUEUE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index e6cab104d2b34..032baf13deb03 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -19,5 +19,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/backport/kcl_workqueue_backport.h b/include/kcl/backport/kcl_workqueue_backport.h index ac9ffbddd468c..db95877443f53 100644 --- a/include/kcl/backport/kcl_workqueue_backport.h +++ b/include/kcl/backport/kcl_workqueue_backport.h @@ -10,4 +10,14 @@ extern bool kcl_cancel_work(struct work_struct *work); #define cancel_work kcl_cancel_work #endif +/* Copied from kernel/workqueue.c and modified for KCL */ +#ifndef HAVE_QUEUE_WORK_NODE +static inline +bool _kcl_queue_work_node(int node, struct workqueue_struct *wq, + struct work_struct *work) +{ + return queue_work(wq, work); +} +#define queue_work_node _kcl_queue_work_node +#endif #endif /* KCL_LINUX_WORKQUEUE_BACKPORT_H */ From f2abc509e44f569102bb0544be648d5a84c757b0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 23 Dec 2023 14:19:16 +0800 Subject: [PATCH 1180/2653] drm/amdkcl: test linux/units.h whether exists It's caused by v6.7-rc5-897-g18df969b44a0 drm/amd/pm: enable Wifi RFI mitigation feature support for SMU13.0.0 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/linux/units.h | 10 ++++++++++ include/kcl/kcl_units.h | 12 ++++++++++++ 4 files changed, 28 insertions(+) create mode 100644 include/kcl/header/linux/units.h create mode 100644 include/kcl/kcl_units.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index f82375d7f8f10..56f3b083e931b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -120,4 +120,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 88fa953aa980a..4df530c27442c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -134,4 +134,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #platform/x86/amd: Add support for AMD ACPI based Wifi band RFI mitigation feature dnl AC_KERNEL_CHECK_HEADERS([linux/acpi_amd_wbrf.h]) + + dnl #v5.5-5479-g23331e489361 + dnl #include/linux/units.h: add helpers for kelvin to/from Celsius conversion + dnl + AC_KERNEL_CHECK_HEADERS([linux/units.h]) ]) diff --git a/include/kcl/header/linux/units.h b/include/kcl/header/linux/units.h new file mode 100644 index 0000000000000..228273e685fc1 --- /dev/null +++ b/include/kcl/header/linux/units.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _KCL_HEADER_LINUX_UNITS_H_H +#define _KCL_HEADER_LINUX_UNITS_H_H + +#ifdef HAVE_LINUX_UNITS_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_units.h b/include/kcl/kcl_units.h new file mode 100644 index 0000000000000..21d9f45fb1c5e --- /dev/null +++ b/include/kcl/kcl_units.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef KCL_KCL_LINUX_UNITS_H +#define KCL_KCL_LINUX_UNITS_H + +#include + +#ifndef HZ_PER_MHZ +#define HZ_PER_MHZ 1000000UL +#endif + +#endif + From cdc8358d1de96210f8269e5386a5cf462ae60381 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 23 Dec 2023 16:16:43 +0800 Subject: [PATCH 1181/2653] drm/amdkcl: test whether drm_gem_object->resv whether exist It's caused by v6.7-rc3-500-gdfc03588cf8c drm/amd/display: Initialize writeback connector Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c index d9527c05fc878..3ca85a9ebd38e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c @@ -106,7 +106,7 @@ static int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector return r; } - r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&rbo->tbo), 1); if (r) { drm_err(adev_to_drm(adev), "reserving fence slot failed (%d)\n", r); goto error_unlock; From b39076acf2e67ddec4f2f2d2f9275ac76e2487e0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 23 Dec 2023 16:35:19 +0800 Subject: [PATCH 1182/2653] drm/amdkcl: wrap code under macro HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB It's caused by v6.7-rc3-500-gdfc03588cf8c drm/amd/display: Initialize writeback connector Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c index 3ca85a9ebd38e..fab8b363e6477 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c @@ -80,6 +80,7 @@ static int amdgpu_dm_wb_connector_get_modes(struct drm_connector *connector) return drm_add_modes_noedid(connector, 3840, 2160); } +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB static int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector, struct drm_writeback_job *job) { @@ -164,6 +165,7 @@ static void amdgpu_dm_wb_cleanup_job(struct drm_writeback_connector *connector, amdgpu_bo_unreserve(rbo); amdgpu_bo_unref(&rbo); } +#endif static const struct drm_encoder_helper_funcs amdgpu_dm_wb_encoder_helper_funcs = { .atomic_check = amdgpu_dm_wb_encoder_atomic_check, @@ -179,8 +181,10 @@ static const struct drm_connector_funcs amdgpu_dm_wb_connector_funcs = { static const struct drm_connector_helper_funcs amdgpu_dm_wb_conn_helper_funcs = { .get_modes = amdgpu_dm_wb_connector_get_modes, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB .prepare_writeback_job = amdgpu_dm_wb_prepare_job, .cleanup_writeback_job = amdgpu_dm_wb_cleanup_job, +#endif }; int amdgpu_dm_wb_connector_init(struct amdgpu_display_manager *dm, From 0aed8d246055a9d3ea70c8f1442bcc1211efd4b2 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 23 Dec 2023 20:02:46 +0800 Subject: [PATCH 1183/2653] drm/amdgpu: [hybrid] remove DRM_UNLOCKED flag This is caused by v6.7-rc3-559-g2798ffcc1d6a drm: Remove locking for legacy ioctls and DRM_UNLOCKED Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 6d56f10bc4d49..c374f74d48b56 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3100,7 +3100,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_DGMA, amdgpu_gem_dgma_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW) + DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) }; static struct drm_driver amdgpu_kms_driver = { From ce7b4948c517284b41cb35c91094e3a3521afe22 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 24 Dec 2023 11:12:29 +0800 Subject: [PATCH 1184/2653] drm/amdkcl: update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 26 ++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index fb72dc472797e..3c291cebb584e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -130,6 +130,9 @@ /* dma_fence_is_container() is available */ #define HAVE_DMA_FENCE_IS_CONTAINER 1 +/* dma_fence_is_later_or_same() is available */ +#define HAVE_DMA_FENCE_IS_LATER_OR_SAME 1 + /* struct dma_fence_ops has callback set_deadline */ #define HAVE_DMA_FENCE_OPS_SET_DEADLINE 1 @@ -317,8 +320,8 @@ /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 -/* drm_dp_calc_pbn_mode() wants 3args */ -#define HAVE_DRM_DP_CALC_PBN_MODE_3ARGS 1 +/* drm_dp_calc_pbn_mode() wants 3 args */ +/* #undef HAVE_DRM_DP_CALC_PBN_MODE_3ARGS */ /* drm_dp_cec_register_connector() wants p,p interface */ #define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 @@ -402,7 +405,10 @@ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS 1 /* struct drm_dp_mst_topology_state has member pbn_div */ -#define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV 1 +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT */ + +/* struct drm_dp_mst_topology_state has union member pbn_div */ +#define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION 1 /* struct drm_dp_mst_topology_state has member total_avail_slots */ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS 1 @@ -446,6 +452,9 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRM_BACKPORT_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_ELD_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_EXEC_H 1 @@ -754,6 +763,9 @@ /* kvrealloc() is available */ #define HAVE_KVREALLOC 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_ACPI_AMD_WBRF_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_APPLE_GMUX_H 1 @@ -829,6 +841,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_STDARG_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_UNITS_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_XARRAY_H 1 @@ -931,6 +946,9 @@ /* pxm_to_node() is available */ #define HAVE_PXM_TO_NODE 1 +/* queue_work_node() is available */ +#define HAVE_QUEUE_WORK_NODE 1 + /* rb_add_cached is available */ #define HAVE_RB_ADD_CACHED 1 @@ -1116,7 +1134,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 6.5.0" +#define PACKAGE_STRING "amdgpu-dkms 6.7.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" From c272dc7ca894960172084e33024af527bf02c779 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 28 Dec 2023 18:13:37 +0800 Subject: [PATCH 1185/2653] drm/amdkcl: add clang support Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 702c80e0aba00..9f9912a12530f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -433,10 +433,16 @@ AC_DEFUN([AC_KERNEL_COMPILE_MODULE_IFELSE], [ kbuild_src_flag='' kbuild_modpost_flag='KBUILD_MODPOST_NOFINAL=1 KBUILD_MODPOST_WARN=1' kbuild_workaround_flag='' + kbuild_cc='' + if test -s ${LINUX_OBJ}/.config; then + if grep -q 'CONFIG_CC_IS_CLANG=y' "${LINUX_OBJ}/.config"; then + kbuild_cc='CC=clang' + fi + fi test "x$enable_linux_builtin" = xyes && kbuild_src_flag='KBUILD_SRC=' # override KBUILD_SRC test "x$enable_linux_builtin" = xyes && kbuild_workaround_flag='sub_make_done=' # override sub_make_done AS_IF( - [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], + [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag $kbuild_cc) >/dev/null && AC_TRY_COMMAND([$3])], [$4], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] ) From 10384fa81377937f0b460b984248dbeb7c8c9e6d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 4 Jan 2024 19:44:03 +0800 Subject: [PATCH 1186/2653] drm/amdkcl: initialize the variables in m4. Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 index 326a3fc8e64c4..4527ccd0a9659 100644 --- a/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 @@ -7,7 +7,7 @@ AC_DEFUN([AC_AMDGPU_KMAP_LOCAL], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - pgprot_t prot; + pgprot_t prot = {0}; kmap_local_page_prot(NULL, prot); ], [ AC_DEFINE(HAVE_KMAP_LOCAL, 1, [kmap_local_* is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 index d1f869507e4dd..192bb1767dda5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_VMF_INSERT_PFN_PROT], [ #include #include ],[ - pgprot_t prot; + pgprot_t prot = {0}; vmf_insert_pfn_prot(NULL, 0, 0, prot); ],[ AC_DEFINE(HAVE_VMF_INSERT_PFN_PROT, @@ -23,7 +23,7 @@ AC_DEFUN([AC_AMDGPU_VMF_INSERT_PFN_PROT], [ #include #include ],[ - pgprot_t prot; + pgprot_t prot = {0}; vm_insert_pfn_prot(NULL, 0, 0, prot); ],[ AC_DEFINE(HAVE_VM_INSERT_PFN_PROT, From 643508cba5304656c5f6dde94667d8ec90f9a7a9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 9 Jan 2024 13:32:34 +0800 Subject: [PATCH 1187/2653] drm/amdkcl: test whether dma_buf_is_dynamic() is available It's caused by 79e7fdec71f255c9961fae19619532bb4493742a "drm/amdgpu: Auto-validate DMABuf imports in compute VMs" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/dma_buf_is_dynamic.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma-buf.h | 18 ++++++++++++++++++ 5 files changed, 39 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma_buf_is_dynamic.m4 create mode 100644 include/kcl/kcl_dma-buf.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 56f3b083e931b..e51f3d7932a86 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -121,4 +121,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3c291cebb584e..2dd97d2168fbb 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -109,6 +109,9 @@ /* dev_pm_set_driver_flags() is available */ #define HAVE_DEV_PM_SET_DRIVER_FLAGS 1 +/* dma_buf_is_dynamic() is available */ +#define HAVE_DMA_BUF_IS_DYNAMIC 1 + /* dma_buf->dynamic_mapping is available */ /* #undef HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING */ diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_buf_is_dynamic.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_buf_is_dynamic.m4 new file mode 100644 index 0000000000000..0b5844f8c43dc --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_buf_is_dynamic.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.4-rc4-863-g15fd552d186c +dnl # dma-buf: change DMA-buf locking convention v3 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_BUF_IS_DYNAMIC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + dma_buf_is_dynamic(NULL); + ],[ + AC_DEFINE(HAVE_DMA_BUF_IS_DYNAMIC, 1, + [dma_buf_is_dynamic() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9f9912a12530f..60af374e944f4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -218,6 +218,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_AMDGPU_LINUX_DEVICE_CLASS AC_AMDGPU_KVREALLOC + AC_AMDGPU_DMA_BUF_IS_DYNAMIC AC_AMDGPU_DRM_CLIENT_REGISTER AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD diff --git a/include/kcl/kcl_dma-buf.h b/include/kcl/kcl_dma-buf.h new file mode 100644 index 0000000000000..fe7094bc3071e --- /dev/null +++ b/include/kcl/kcl_dma-buf.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Pointer to dma-buf-mapped memory, plus helpers. + * Copied from include/kcl/dma-buf.h + */ +#ifndef _KCL_KCL__DMA_BUF_H__H__ +#define _KCL_KCL__DMA_BUF_H__H__ + +#include + +#ifndef HAVE_DMA_BUF_IS_DYNAMIC +static inline bool dma_buf_is_dynamic(struct dma_buf *dmabuf) +{ + return false; +} +#endif + +#endif \ No newline at end of file From dd07b20ecaa5fa1747d1f17fd9a7a608cc6b414f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 9 Jan 2024 11:36:56 +0800 Subject: [PATCH 1188/2653] drm/amdkcl: wrap code under amdkcl_ttm_resvp() It's caused by 79e7fdec71f255c9961fae19619532bb4493742a "drm/amdgpu: Auto-validate DMABuf imports in compute VMs" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index ab55a669eab06..43729bb68b322 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -632,7 +632,7 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, bo = bo_base->bo; - if (dma_resv_locking_ctx(bo->tbo.base.resv) != ticket) { + if (dma_resv_locking_ctx(amdkcl_ttm_resvp(&bo->tbo)) != ticket) { struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm); pr_warn_ratelimited("Evicted user BO is not reserved\n"); From 4417b076c948c4c02aa81b6694e3bb79477168c5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 10 Jan 2024 14:01:23 +0800 Subject: [PATCH 1189/2653] drm/amdkcl: wrap code under macro DEFINE_DEBUGFS_ATTRIBUTE It's caused by 455b15748da59235d86edd764c0fcc35b71d6b69 "drm/amdgpu: add ACA bank dump debugfs support" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c index cbc40cad581b4..d7c37124e932c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c @@ -957,7 +957,11 @@ static const struct file_operations aca_ue_dump_debug_fops = { .release = single_release, }; +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(aca_debug_mode_fops, NULL, amdgpu_aca_smu_debug_mode_set, "%llu\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(aca_debug_mode_fops, NULL, amdgpu_aca_smu_debug_mode_set, "%llu\n"); +#endif #endif void amdgpu_aca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root) From d7c03976a220ed45aee836c8cf8221a82c622dcd Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 17 Jan 2024 14:07:56 +0800 Subject: [PATCH 1190/2653] drm/amdgpu: Synchronize after mapping into a compute VM Compute VMs use user mode queues for command submission. They cannot use a CS ioctl to synchronize with pending PTE updates and flush TLBs. Do this synchronization in amdgpu_gem_va_ioctl for compute VMs. Signed-off-by: Felix Kuehling Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 799ca7e6045bc..860c23f8fde0b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -902,11 +902,12 @@ int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, */ static struct dma_fence * amdgpu_gem_va_update_vm(struct amdgpu_device *adev, - struct amdgpu_vm *vm, + struct amdgpu_fpriv *fpriv, struct amdgpu_bo_va *bo_va, uint32_t operation) { struct dma_fence *fence = dma_fence_get_stub(); + struct amdgpu_vm *vm = &fpriv->vm; int r; if (!amdgpu_vm_ready(vm)) @@ -924,6 +925,25 @@ amdgpu_gem_va_update_vm(struct amdgpu_device *adev, } r = amdgpu_vm_update_pdes(adev, vm, false); + if (r) + goto error; + + if (vm->is_compute_context) { + if (bo_va->last_pt_update) + r = dma_fence_wait(bo_va->last_pt_update, true); + if (!r && vm->last_update) + r = dma_fence_wait(vm->last_update, true); + if (!r) { + uint32_t xcc_mask = (!adev->xcp_mgr || + fpriv->xcp_id == ~0) ? 1 : + adev->xcp_mgr->xcp[fpriv->xcp_id] + .ip[AMDGPU_XCP_GFX].inst_mask; + + r = amdgpu_vm_flush_compute_tlb(adev, vm, + TLB_FLUSH_LEGACY, + xcc_mask); + } + } error: if (r && r != -ERESTARTSYS) @@ -1077,7 +1097,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, break; } if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !adev->debug_vm) { - fence = amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, + fence = amdgpu_gem_va_update_vm(adev, fpriv, bo_va, args->operation); if (timeline_syncobj) From 2cdfdadfd8b3a66a98289b45f2ab33d8a03ddabb Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 18 Jan 2024 11:40:44 +0800 Subject: [PATCH 1191/2653] drm/amdgpu: update update_spm_vmid() param for non-upstream code It's caused by 3a260e1feaa636b3d718055a3259228fbd1d6bb4 "drm/amd/amdgpu: Update RLC_SPM_MC_CNT by ring wreg in guest" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index 0d1007d6f146b..037e9aea2b691 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -66,7 +66,7 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm * } /* init spm vmid with 0x0 */ - adev->gfx.rlc.funcs->update_spm_vmid(adev, 0); + adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0); /* set spm ring registers */ spin_lock(&adev->gfx.kiq[0].ring_lock); @@ -95,7 +95,7 @@ void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm /* revert spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); + adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); } void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev) From bbdb85cdfe4ffeee0e620b7daae3516795857ec4 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 19 Jan 2024 14:47:53 +0800 Subject: [PATCH 1192/2653] drm/amdkcl: include fake drm_gem_object_put() for kcl_drm_exec.c In RHEL7.9, drm_gem_object_put will not check obj pointer that cause null point issue. So kcl_drm_exex.c need use fake drm_gem_object_put(). Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c index 4bf8c653fa2f4..1ce1651265c24 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c @@ -4,6 +4,7 @@ #include #include #include +#include #ifndef HAVE_DRM_DRM_EXEC_H /** From fbf44f0dee8e227dc5af4057fec31c23985a8ff2 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 6 Feb 2024 19:14:59 +0800 Subject: [PATCH 1193/2653] drm/amdkcl: export drm_gem_prime_handle_to_fd and drm_gem_prime_fd_to_handle On rhel9.4 which using kernel 6.4, drm_gem_prime_handle_to_fd and drm_gem_prime_fd_to_handle are unexported, so export it. It's caused by v6.4-rc7-1904-g71a7974ac701 drm/prime: Unexport helpers for fd/handle conversion eec9e451b drm/amdkfd: Export DMABufs from KFD using GEM handles Signed-off-by: Asher Song Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ----- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_prime.c | 28 ++++++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 ++ include/kcl/backport/kcl_drm_prime.h | 13 ++++++++++ 5 files changed, 44 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_prime.c diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index c374f74d48b56..637717dcb2d05 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3155,12 +3155,8 @@ static struct drm_driver amdgpu_kms_driver = { .show_fdinfo = amdgpu_show_fdinfo, #endif #endif - -#ifdef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, -#endif - #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK .gem_prime_export = amdgpu_gem_prime_export, #endif @@ -3213,10 +3209,8 @@ const struct drm_driver amdgpu_partition_driver = { .fops = &amdgpu_driver_kms_fops, .release = &amdgpu_driver_release_kms, -#ifdef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, -#endif .gem_prime_import = amdgpu_gem_prime_import, #ifdef HAVE_DRM_DRIVER_GEM_PRIME_MMAP .gem_prime_mmap = drm_gem_prime_mmap, diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index d5a8a1db57bac..82abb89903b8c 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o kcl_drm_exec.o kcl_drm_dp_helper.o + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_prime.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_prime.c new file mode 100644 index 0000000000000..36ca9dec40c2b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_prime.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * driver/drm/drm_prime.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ +#include + +#ifndef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD +int (*_kcl_drm_gem_prime_handle_to_fd)(struct drm_device *dev, + struct drm_file *file_priv, uint32_t handle, + uint32_t flags, + int *prime_fd); +EXPORT_SYMBOL(_kcl_drm_gem_prime_handle_to_fd); + +int (*_kcl_drm_gem_prime_fd_to_handle)(struct drm_device *dev, + struct drm_file *file_priv, int prime_fd, + uint32_t *handle); +EXPORT_SYMBOL(_kcl_drm_gem_prime_fd_to_handle); +#endif + +void amdkcl_prime_init(void) +{ +#ifndef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD + _kcl_drm_gem_prime_handle_to_fd = amdkcl_fp_setup("drm_gem_prime_handle_to_fd", NULL); + _kcl_drm_gem_prime_fd_to_handle = amdkcl_fp_setup("drm_gem_prime_fd_to_handle", NULL); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index d33b1db010e1a..7ede3a4fa2a6f 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -12,6 +12,7 @@ extern void amdkcl_suspend_init(void); extern void amdkcl_sched_init(void); extern void amdkcl_numa_init(void); extern void amdkcl_workqueue_init(void); +extern void amdkcl_prime_init(void); int __init amdkcl_init(void) { @@ -25,6 +26,7 @@ int __init amdkcl_init(void) amdkcl_sched_init(); amdkcl_numa_init(); amdkcl_workqueue_init(); + amdkcl_prime_init(); return 0; } diff --git a/include/kcl/backport/kcl_drm_prime.h b/include/kcl/backport/kcl_drm_prime.h index 33187c1891d71..de796e551b712 100644 --- a/include/kcl/backport/kcl_drm_prime.h +++ b/include/kcl/backport/kcl_drm_prime.h @@ -50,4 +50,17 @@ struct sg_table *_kcl_drm_prime_pages_to_sg(struct drm_device *dev, #define drm_prime_pages_to_sg _kcl_drm_prime_pages_to_sg #endif +#ifndef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD +int _kcl_drm_gem_prime_handle_to_fd(struct drm_device *dev, + struct drm_file *file_priv, uint32_t handle, + uint32_t flags, + int *prime_fd); +#define drm_gem_prime_handle_to_fd _kcl_drm_gem_prime_handle_to_fd + +int _kcl_drm_gem_prime_fd_to_handle(struct drm_device *dev, + struct drm_file *file_priv, int prime_fd, + uint32_t *handle); +#define drm_gem_prime_fd_to_handle _kcl_drm_gem_prime_fd_to_handle +#endif + #endif From a8fb668e2076bd8c81b3d82c9c438481f998c6eb Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 26 Feb 2024 21:24:54 +0800 Subject: [PATCH 1194/2653] drm/amdkcl: Check MAX_ORDER whether defined It's caused by 5e0a760b44417f7cadd79de2204d6247109558a0 mm, treewide: rename MAX_ORDER to MAX_PAGE_ORDER On kernel 6.8, macro MAX_ORDER is renamed to MAX_PAGE_ORDER. Signed-off-by: Asher Song Reviewed-by: Leslie Shi Reviewed-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_drm_exec.h | 1 + include/kcl/kcl_mmzone.h | 21 +++++++++++++++++++++ 4 files changed, 24 insertions(+) create mode 100644 include/kcl/kcl_mmzone.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e51f3d7932a86..a7011ba5a34a6 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -66,6 +66,7 @@ #include #include #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 032baf13deb03..f9e3e75824090 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -20,5 +20,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_drm_exec.h b/include/kcl/kcl_drm_exec.h index 8a3f47f0520f6..2ffba4ce2fef7 100644 --- a/include/kcl/kcl_drm_exec.h +++ b/include/kcl/kcl_drm_exec.h @@ -13,6 +13,7 @@ #endif #ifndef HAVE_DRM_DRM_EXEC_H #include +#include #include #define DRM_EXEC_INTERRUPTIBLE_WAIT BIT(0) #define DRM_EXEC_IGNORE_DUPLICATES BIT(1) diff --git a/include/kcl/kcl_mmzone.h b/include/kcl/kcl_mmzone.h new file mode 100644 index 0000000000000..7cd5ea05d5af8 --- /dev/null +++ b/include/kcl/kcl_mmzone.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_MMZONE_H +#define _KCL_MMZONE_H + +#include + +#ifndef __ASSEMBLY__ +#ifndef __GENERATING_BOUNDS_H + +#ifndef MAX_PAGE_ORDER +#define MAX_PAGE_ORDER MAX_ORDER +#endif + +#ifndef NR_PAGE_ORDERS +#define NR_PAGE_ORDERS (MAX_PAGE_ORDER + 1) +#endif + +#endif +#endif + +#endif From 13ff756a5ee4b7fa9fa552683550c4aafb130c70 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 27 Feb 2024 12:22:07 +0800 Subject: [PATCH 1195/2653] drm/amdkcl: test drm_exec_init whether has three arguments It's caused by 05d249352f1ae909230c230767ca8f4e9fdf8e7b drm/exec: Pass in initial # of objects On kenrel 6.8, drm_exec_init has three arguments. Signed-off-by: Asher Song Reviewed-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 8 ++------ drivers/gpu/drm/amd/dkms/m4/drm-exec.m4 | 20 ++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_exec.h | 18 ++++++++++++++++++ 5 files changed, 42 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-exec.m4 create mode 100644 include/kcl/backport/kcl_drm_exec.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a7011ba5a34a6..70898b45f1388 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -123,4 +123,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2dd97d2168fbb..38237fcc9187b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -503,12 +503,8 @@ /* drm_edid_override_connector_update() is available */ #define HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE 1 -/* drm_fb_helper_single_add_all_connectors() && - drm_fb_helper_remove_one_connector() are symbol */ -/* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ - -/* drm_fb_helper_alloc_info() is available */ -#define HAVE_DRM_FB_HELPER_ALLOC_INFO 1 +/* drm_exec() has 3 arguments */ +#define HAVE_DRM_EXEC_INIT_3_ARGUMENTS /* drm_fb_helper_fill_info() is available */ #define HAVE_DRM_FB_HELPER_FILL_INFO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-exec.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-exec.m4 new file mode 100644 index 0000000000000..b481cf6b7945e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-exec.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit 05d249352f1ae909230c230767ca8f4e9fdf8e7b +dnl # drm/exec: Pass in initial # of objects +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EXEC_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_exec_init(NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_DRM_EXEC_INIT_3_ARGUMENTS, 1, + [drm_exec() has 3 arguments]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_EXEC], [ + AC_AMDGPU_DRM_EXEC_INIT +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 60af374e944f4..d0f32656a5028 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -227,6 +227,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CPUINFO_X86 AC_AMDGPU_DMA_FENCE_IS_LATER_OR_SAME AC_AMDGPU_WORKQUEUE + AC_AMDGPU_DRM_EXEC_INIT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_exec.h b/include/kcl/backport/kcl_drm_exec.h new file mode 100644 index 0000000000000..0d86a455cabdc --- /dev/null +++ b/include/kcl/backport/kcl_drm_exec.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_BACKPORT_KCL_DRM_EXEC_H +#define AMDKCL_BACKPORT_KCL_DRM_EXEC_H + +#include +#include + +#ifndef HAVE_DRM_EXEC_INIT_3_ARGUMENTS +static inline +void _kcl_drm_exec_init(struct drm_exec *exec, uint32_t flags, unsigned nr) +{ + return drm_exec_init(exec, flags); +} + +#define drm_exec_init _kcl_drm_exec_init +#endif /* HAVE_DRM_EXEC_INIT_3_ARGUMENTS */ + +#endif From 73d7120a8f73a952c2fa47ab7571ec2ea90cc584 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Fri, 21 Jul 2023 11:16:56 -0400 Subject: [PATCH 1196/2653] drm/amdkfd/kfd_ioctl: add pc sampling support Add pc sampling support in kfd_ioctl. The user mode code which uses this new kfd_ioctl is linked to https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface with master branch. Co-developed-by: James Zhu Signed-off-by: James Zhu Signed-off-by: David Yat Sin Tested-by: Vladimir Indic --- include/uapi/linux/kfd_ioctl.h | 61 +++++++++++++++++++++++++++++++++- 1 file changed, 60 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 10b03e950ac4a..7649c334dedb5 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1669,6 +1669,62 @@ struct kfd_ioctl_dbg_trap_args { }; }; +/** + * kfd_ioctl_pc_sample_op - PC Sampling ioctl operations + * + * @KFD_IOCTL_PCS_OP_QUERY_CAPABILITIES: Query device PC Sampling capabilities + * @KFD_IOCTL_PCS_OP_CREATE: Register this process with a per-device PC sampler instance + * @KFD_IOCTL_PCS_OP_DESTROY: Unregister from a previously registered PC sampler instance + * @KFD_IOCTL_PCS_OP_START: Process begins taking samples from a previously registered PC sampler instance + * @KFD_IOCTL_PCS_OP_STOP: Process stops taking samples from a previously registered PC sampler instance + */ +enum kfd_ioctl_pc_sample_op { + KFD_IOCTL_PCS_OP_QUERY_CAPABILITIES, + KFD_IOCTL_PCS_OP_CREATE, + KFD_IOCTL_PCS_OP_DESTROY, + KFD_IOCTL_PCS_OP_START, + KFD_IOCTL_PCS_OP_STOP, +}; + +/* Values have to be a power of 2*/ +#define KFD_IOCTL_PCS_FLAG_POWER_OF_2 0x00000001 + +enum kfd_ioctl_pc_sample_method { + KFD_IOCTL_PCS_METHOD_HOSTTRAP = 1, + KFD_IOCTL_PCS_METHOD_STOCHASTIC, +}; + +enum kfd_ioctl_pc_sample_type { + KFD_IOCTL_PCS_TYPE_TIME_US, + KFD_IOCTL_PCS_TYPE_CLOCK_CYCLES, + KFD_IOCTL_PCS_TYPE_INSTRUCTIONS +}; + +struct kfd_pc_sample_info { + __u64 interval; /* [IN] if PCS_TYPE_INTERVAL_US: sample interval in us + * if PCS_TYPE_CLOCK_CYCLES: sample interval in graphics core clk cycles + * if PCS_TYPE_INSTRUCTIONS: sample interval in instructions issued by + * graphics compute units + */ + __u64 interval_min; /* [OUT] */ + __u64 interval_max; /* [OUT] */ + __u64 flags; /* [OUT] indicate potential restrictions e.g FLAG_POWER_OF_2 */ + __u32 method; /* [IN/OUT] kfd_ioctl_pc_sample_method */ + __u32 type; /* [IN/OUT] kfd_ioctl_pc_sample_type */ +}; + +#define KFD_IOCTL_PCS_QUERY_TYPE_FULL (1 << 0) /* If not set, return current */ + +struct kfd_ioctl_pc_sample_args { + __u64 sample_info_ptr; /* array of kfd_pc_sample_info */ + __u32 num_sample_info; + __u32 op; /* kfd_ioctl_pc_sample_op */ + __u32 gpu_id; + __u32 trace_id; + __u32 flags; /* kfd_ioctl_pcs_query flags */ + __u32 reserved; +}; + #define AMDKFD_IOCTL_BASE 'K' #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) @@ -1808,7 +1864,10 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_RLC_SPM \ AMDKFD_IOWR(0x84, struct kfd_ioctl_spm_args) +#define AMDKFD_IOC_PC_SAMPLE \ + AMDKFD_IOWR(0x85, struct kfd_ioctl_pc_sample_args) + #define AMDKFD_COMMAND_START_2 0x80 -#define AMDKFD_COMMAND_END_2 0x85 +#define AMDKFD_COMMAND_END_2 0x86 #endif From 307bb09c8ac5157e289442053e253560be78be2d Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Fri, 21 Jul 2023 12:09:14 -0400 Subject: [PATCH 1197/2653] drm/amdkfd: add pc sampling support Add pc sampling functions in amdkfd. Co-developed-by: James Zhu Signed-off-by: James Zhu Signed-off-by: David Yat Sin Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/Makefile | 3 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 46 ++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 78 ++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h | 34 +++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 13 ++++ 5 files changed, 173 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index cf668e22a80c0..826fe822b61d2 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -62,7 +62,8 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_ipc.o \ $(AMDKFD_PATH)/kfd_trace.o \ $(AMDKFD_PATH)/kfd_spm.o \ - $(AMDKFD_PATH)/kfd_debug.o + $(AMDKFD_PATH)/kfd_debug.o \ + $(AMDKFD_PATH)/kfd_pc_sampling.o ifneq ($(CONFIG_DEBUG_FS),) AMDKFD_FILES += $(AMDKFD_PATH)/kfd_debugfs.o diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index a61a59953b671..2e0b3bb6669f3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -41,6 +41,7 @@ #include "kfd_svm.h" #include "kfd_ipc.h" #include "kfd_trace.h" +#include "kfd_pc_sampling.h" #include "amdgpu_amdkfd.h" #include "kfd_smi_events.h" @@ -1852,6 +1853,39 @@ static int kfd_ioctl_rlc_spm(struct file *filep, return kfd_rlc_spm(p, data); } +static int kfd_ioctl_pc_sample(struct file *filep, + struct kfd_process *p, void __user *data) +{ + struct kfd_ioctl_pc_sample_args *args = data; + struct kfd_process_device *pdd; + int ret = 0; + + if (sched_policy == KFD_SCHED_POLICY_NO_HWS) { + pr_err("PC Sampling does not support sched_policy %i", sched_policy); + return -EINVAL; + } + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + + if (!pdd) { + pr_debug("could not find gpu id 0x%x.", args->gpu_id); + ret = -EINVAL; + } else if (args->op == KFD_IOCTL_PCS_OP_START) { + pdd = kfd_bind_process_to_device(pdd->dev, p); + if (IS_ERR(pdd)) { + pr_debug("failed to bind process %p with gpu id 0x%x", p, args->gpu_id); + ret = -ESRCH; + } + } + + if (!ret) + ret = kfd_pc_sample(pdd, args); + mutex_unlock(&p->mutex); + + return ret; +} + static int criu_checkpoint_process(struct kfd_process *p, uint8_t __user *user_priv_data, uint64_t *priv_offset) @@ -3477,6 +3511,10 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_CROSS_MEMORY_COPY_DEPRECATED, kfd_ioctl_cross_memory_copy_deprecated, 0), + + /* TODO: KFD_IOC_FLAG_PERFMON is not required for host-trap, disable first */ + AMDKFD_IOCTL_DEF(AMDKFD_IOC_PC_SAMPLE, + kfd_ioctl_pc_sample, 0), }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) @@ -3549,6 +3587,14 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) } } + /* PC Sampling Monitor */ + if (unlikely(ioctl->flags & KFD_IOC_FLAG_PERFMON)) { + if (!capable(CAP_PERFMON) && !capable(CAP_SYS_ADMIN)) { + retcode = -EACCES; + goto err_i1; + } + } + if (cmd & (IOC_IN | IOC_OUT)) { if (asize <= sizeof(stack_kdata)) { kdata = stack_kdata; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c new file mode 100644 index 0000000000000..a7e78ff42d079 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "kfd_priv.h" +#include "amdgpu_amdkfd.h" +#include "kfd_pc_sampling.h" + +static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, + struct kfd_ioctl_pc_sample_args __user *user_args) +{ + return -EINVAL; +} + +static int kfd_pc_sample_start(struct kfd_process_device *pdd) +{ + return -EINVAL; +} + +static int kfd_pc_sample_stop(struct kfd_process_device *pdd) +{ + return -EINVAL; + +} + +static int kfd_pc_sample_create(struct kfd_process_device *pdd, + struct kfd_ioctl_pc_sample_args __user *user_args) +{ + return -EINVAL; +} + +static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_id) +{ + return -EINVAL; + +} + +int kfd_pc_sample(struct kfd_process_device *pdd, + struct kfd_ioctl_pc_sample_args __user *args) +{ + switch (args->op) { + case KFD_IOCTL_PCS_OP_QUERY_CAPABILITIES: + return kfd_pc_sample_query_cap(pdd, args); + + case KFD_IOCTL_PCS_OP_CREATE: + return kfd_pc_sample_create(pdd, args); + + case KFD_IOCTL_PCS_OP_DESTROY: + return kfd_pc_sample_destroy(pdd, args->trace_id); + + case KFD_IOCTL_PCS_OP_START: + return kfd_pc_sample_start(pdd); + + case KFD_IOCTL_PCS_OP_STOP: + return kfd_pc_sample_stop(pdd); + } + + return -EINVAL; +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h new file mode 100644 index 0000000000000..4eeded4ea5b6c --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef KFD_PC_SAMPLING_H_ +#define KFD_PC_SAMPLING_H_ + +#include "amdgpu.h" +#include "kfd_priv.h" + +int kfd_pc_sample(struct kfd_process_device *pdd, + struct kfd_ioctl_pc_sample_args __user *args); + +#endif /* KFD_PC_SAMPLING_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 67872df8e1446..fdba7ce49af4d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -149,6 +149,19 @@ enum kfd_ioctl_flags { * we also allow ioctls with SYS_ADMIN capability. */ KFD_IOC_FLAG_CHECKPOINT_RESTORE = BIT(0), + + /* + * @KFD_IOC_FLAG_PERFMON: + * Performance monitoring feature, GPU performance monitoring can allow users + * to gather some information about other processes. PC sampling can allow + * users to infer information about wavefronts from other processes that are + * running on the same CUs, such as which execution units they are using. As + * such, this type of performance monitoring should be protected and only + * available to users with sufficient capabilities: either CAP_PERFMON, or, + * for backwards compatibility, CAP_SYS_ADMIN. + */ + + KFD_IOC_FLAG_PERFMON = BIT(1), }; /* * Kernel module parameter to specify maximum number of supported queues per From 772805f36e95501cfc050efcdab3c67b2e9f6541 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Fri, 21 Jul 2023 12:24:13 -0400 Subject: [PATCH 1198/2653] drm/amdkfd: enable pc sampling query Enable pc sampling to query system capability. Co-developed-by: James Zhu Signed-off-by: James Zhu Signed-off-by: David Yat Sin Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 65 +++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index a7e78ff42d079..e9277c9beec73 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -25,10 +25,73 @@ #include "amdgpu_amdkfd.h" #include "kfd_pc_sampling.h" +struct supported_pc_sample_info { + uint32_t ip_version; + const struct kfd_pc_sample_info *sample_info; +}; + +const struct kfd_pc_sample_info sample_info_hosttrap_9_0_0 = { + 0, 1, ~0ULL, 0, KFD_IOCTL_PCS_METHOD_HOSTTRAP, KFD_IOCTL_PCS_TYPE_TIME_US }; + +struct supported_pc_sample_info supported_formats[] = { + { IP_VERSION(9, 4, 1), &sample_info_hosttrap_9_0_0 }, + { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, +}; + static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, struct kfd_ioctl_pc_sample_args __user *user_args) { - return -EINVAL; + uint64_t sample_offset; + int num_method = 0; + int ret; + int i; + + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) + if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version) + num_method++; + + if (!num_method) { + pr_debug("PC Sampling not supported on GC_HWIP:0x%x.", + pdd->dev->adev->ip_versions[GC_HWIP][0]); + return -EOPNOTSUPP; + } + + ret = 0; + mutex_lock(&pdd->dev->pcs_data.mutex); + if (user_args->flags != KFD_IOCTL_PCS_QUERY_TYPE_FULL && + pdd->dev->pcs_data.hosttrap_entry.base.use_count) { + /* If we already have a session, restrict returned list to current method */ + user_args->num_sample_info = 1; + + if (user_args->sample_info_ptr) + ret = copy_to_user((void __user *) user_args->sample_info_ptr, + &pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, + sizeof(struct kfd_pc_sample_info)); + mutex_unlock(&pdd->dev->pcs_data.mutex); + return ret ? -EFAULT : 0; + } + mutex_unlock(&pdd->dev->pcs_data.mutex); + + if (!user_args->sample_info_ptr || user_args->num_sample_info < num_method) { + user_args->num_sample_info = num_method; + pr_debug("ASIC requires space for %d kfd_pc_sample_info entries.", num_method); + return -ENOSPC; + } + + sample_offset = user_args->sample_info_ptr; + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { + if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version) { + ret = copy_to_user((void __user *) sample_offset, + supported_formats[i].sample_info, sizeof(struct kfd_pc_sample_info)); + if (ret) { + pr_debug("Failed to copy PC sampling info to user."); + return -EFAULT; + } + sample_offset += sizeof(struct kfd_pc_sample_info); + } + } + + return 0; } static int kfd_pc_sample_start(struct kfd_process_device *pdd) From 34ca015e6fa04995fa88d1f82073af1134b497ac Mon Sep 17 00:00:00 2001 From: James Zhu Date: Sun, 6 Aug 2023 16:26:26 -0400 Subject: [PATCH 1199/2653] drm/amdkfd: add pc sampling mutex Add pc sampling mutex per node, and do init/destroy in node init. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 12 ++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 7 +++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 5aaa1451982c4..c87443b720396 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -616,6 +616,16 @@ static void kfd_smi_init(struct kfd_node *dev) spin_lock_init(&dev->smi_lock); } +static void kfd_pc_sampling_init(struct kfd_node *dev) +{ + mutex_init(&dev->pcs_data.mutex); +} + +static void kfd_pc_sampling_exit(struct kfd_node *dev) +{ + mutex_destroy(&dev->pcs_data.mutex); +} + static int kfd_init_node(struct kfd_node *node) { int err = -1; @@ -646,6 +656,7 @@ static int kfd_init_node(struct kfd_node *node) } kfd_smi_init(node); + kfd_pc_sampling_init(node); return 0; @@ -684,6 +695,7 @@ static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) kfd_topology_remove_device(knode); if (knode->gws) amdgpu_amdkfd_free_gws(knode->adev, knode->gws); + kfd_pc_sampling_exit(knode); kfree(knode); kfd->nodes[i] = NULL; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index fdba7ce49af4d..13b2e0714960a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -286,6 +286,11 @@ struct kfd_vmid_info { struct kfd_dev; +/* Per device PC Sampling data */ +struct kfd_dev_pc_sampling { + struct mutex mutex; +}; + struct kfd_node { unsigned int node_id; struct amdgpu_device *adev; /* Duplicated here along with keeping @@ -341,6 +346,8 @@ struct kfd_node { /* Track per device allocated watch points */ uint32_t alloc_watch_ids; spinlock_t watch_points_lock; + + struct kfd_dev_pc_sampling pcs_data; }; struct kfd_dev { From 16a8f378e93212eda1ffa599e4a18fbc8e6d944f Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Fri, 21 Jul 2023 14:43:49 -0400 Subject: [PATCH 1200/2653] drm/amdkfd: enable pc sampling create Enable pc sampling create. Co-developed-by: James Zhu Signed-off-by: James Zhu Signed-off-by: David Yat Sin Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 59 +++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 10 ++++ 2 files changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index e9277c9beec73..9267de0bbdac3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -108,7 +108,64 @@ static int kfd_pc_sample_stop(struct kfd_process_device *pdd) static int kfd_pc_sample_create(struct kfd_process_device *pdd, struct kfd_ioctl_pc_sample_args __user *user_args) { - return -EINVAL; + struct kfd_pc_sample_info *supported_format = NULL; + struct kfd_pc_sample_info user_info; + int ret; + int i; + + if (user_args->num_sample_info != 1) + return -EINVAL; + + ret = copy_from_user(&user_info, (void __user *) user_args->sample_info_ptr, + sizeof(struct kfd_pc_sample_info)); + if (ret) { + pr_debug("Failed to copy PC sampling info from user\n"); + return -EFAULT; + } + + if (user_info.flags & KFD_IOCTL_PCS_FLAG_POWER_OF_2 && + user_info.interval & (user_info.interval - 1)) { + pr_debug("Sampling interval's power is unmatched!"); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { + if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version + && user_info.method == supported_formats[i].sample_info->method + && user_info.type == supported_formats[i].sample_info->type + && user_info.interval <= supported_formats[i].sample_info->interval_max + && user_info.interval >= supported_formats[i].sample_info->interval_min) { + supported_format = + (struct kfd_pc_sample_info *)supported_formats[i].sample_info; + break; + } + } + + if (!supported_format) { + pr_debug("Sampling format is not supported!"); + return -EOPNOTSUPP; + } + + mutex_lock(&pdd->dev->pcs_data.mutex); + if (pdd->dev->pcs_data.hosttrap_entry.base.use_count && + memcmp(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, + &user_info, sizeof(user_info))) { + ret = copy_to_user((void __user *) user_args->sample_info_ptr, + &pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, + sizeof(struct kfd_pc_sample_info)); + mutex_unlock(&pdd->dev->pcs_data.mutex); + return ret ? -EFAULT : -EEXIST; + } + + /* TODO: add trace_id return */ + + if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) + pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info = user_info; + + pdd->dev->pcs_data.hosttrap_entry.base.use_count++; + mutex_unlock(&pdd->dev->pcs_data.mutex); + + return 0; } static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_id) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 13b2e0714960a..c4f8e7660688b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -286,9 +286,19 @@ struct kfd_vmid_info { struct kfd_dev; +struct kfd_dev_pc_sampling_data { + uint32_t use_count; /* Num of PC sampling sessions */ + struct kfd_pc_sample_info pc_sample_info; +}; + +struct kfd_dev_pcs_hosttrap { + struct kfd_dev_pc_sampling_data base; +}; + /* Per device PC Sampling data */ struct kfd_dev_pc_sampling { struct mutex mutex; + struct kfd_dev_pcs_hosttrap hosttrap_entry; }; struct kfd_node { From 3798a5847ddf82fbaf1a2a59f13aa530fe1f7d1e Mon Sep 17 00:00:00 2001 From: James Zhu Date: Tue, 8 Aug 2023 16:13:46 -0400 Subject: [PATCH 1201/2653] drm/amdkfd: add trace_id return Add trace_id return for new pc sampling creation per device, Use IDR to quickly locate pc_sampling_entry for reference. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 ++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 20 +++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 6 ++++++ 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index c87443b720396..d27e8bf3448e4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -619,10 +619,12 @@ static void kfd_smi_init(struct kfd_node *dev) static void kfd_pc_sampling_init(struct kfd_node *dev) { mutex_init(&dev->pcs_data.mutex); + idr_init_base(&dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, 1); } static void kfd_pc_sampling_exit(struct kfd_node *dev) { + idr_destroy(&dev->pcs_data.hosttrap_entry.base.pc_sampling_idr); mutex_destroy(&dev->pcs_data.mutex); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 9267de0bbdac3..a607fc1489587 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -110,6 +110,7 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, { struct kfd_pc_sample_info *supported_format = NULL; struct kfd_pc_sample_info user_info; + struct pc_sampling_entry *pcs_entry; int ret; int i; @@ -157,7 +158,19 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, return ret ? -EFAULT : -EEXIST; } - /* TODO: add trace_id return */ + pcs_entry = kzalloc(sizeof(*pcs_entry), GFP_KERNEL); + if (!pcs_entry) { + mutex_unlock(&pdd->dev->pcs_data.mutex); + return -ENOMEM; + } + + i = idr_alloc_cyclic(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, + pcs_entry, 1, 0, GFP_KERNEL); + if (i < 0) { + mutex_unlock(&pdd->dev->pcs_data.mutex); + kfree(pcs_entry); + return i; + } if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info = user_info; @@ -165,6 +178,11 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, pdd->dev->pcs_data.hosttrap_entry.base.use_count++; mutex_unlock(&pdd->dev->pcs_data.mutex); + pcs_entry->pdd = pdd; + user_args->trace_id = (uint32_t)i; + + pr_debug("alloc pcs_entry = %p, trace_id = 0x%x on gpu 0x%x", pcs_entry, i, pdd->dev->id); + return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index c4f8e7660688b..a4d8215942dcd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -288,6 +288,7 @@ struct kfd_dev; struct kfd_dev_pc_sampling_data { uint32_t use_count; /* Num of PC sampling sessions */ + struct idr pc_sampling_idr; struct kfd_pc_sample_info pc_sample_info; }; @@ -817,6 +818,11 @@ enum kfd_pdd_bound { */ #define SDMA_ACTIVITY_DIVISOR 100 +struct pc_sampling_entry { + bool enabled; + struct kfd_process_device *pdd; +}; + /* Data that is per-process-per device. */ struct kfd_process_device { /* The device that owns this data. */ From e94656e4064561fd61ebe1052e91ace5d2d55f4e Mon Sep 17 00:00:00 2001 From: James Zhu Date: Tue, 8 Aug 2023 16:28:47 -0400 Subject: [PATCH 1202/2653] drm/amdkfd: check pcs_entry valid Check pcs_entry valid for pc sampling ioctl. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 33 ++++++++++++++++++-- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index a607fc1489587..72c66d4bd24f9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -195,6 +195,24 @@ static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_ int kfd_pc_sample(struct kfd_process_device *pdd, struct kfd_ioctl_pc_sample_args __user *args) { + struct pc_sampling_entry *pcs_entry; + + if (args->op != KFD_IOCTL_PCS_OP_QUERY_CAPABILITIES && + args->op != KFD_IOCTL_PCS_OP_CREATE) { + + mutex_lock(&pdd->dev->pcs_data.mutex); + pcs_entry = idr_find(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, + args->trace_id); + mutex_unlock(&pdd->dev->pcs_data.mutex); + + /* pcs_entry is only for this pc sampling process, + * which has kfd_process->mutex protected here. + */ + if (!pcs_entry || + pcs_entry->pdd != pdd) + return -EINVAL; + } + switch (args->op) { case KFD_IOCTL_PCS_OP_QUERY_CAPABILITIES: return kfd_pc_sample_query_cap(pdd, args); @@ -203,13 +221,22 @@ int kfd_pc_sample(struct kfd_process_device *pdd, return kfd_pc_sample_create(pdd, args); case KFD_IOCTL_PCS_OP_DESTROY: - return kfd_pc_sample_destroy(pdd, args->trace_id); + if (pcs_entry->enabled) + return -EBUSY; + else + return kfd_pc_sample_destroy(pdd, args->trace_id); case KFD_IOCTL_PCS_OP_START: - return kfd_pc_sample_start(pdd); + if (pcs_entry->enabled) + return -EALREADY; + else + return kfd_pc_sample_start(pdd); case KFD_IOCTL_PCS_OP_STOP: - return kfd_pc_sample_stop(pdd); + if (!pcs_entry->enabled) + return -EALREADY; + else + return kfd_pc_sample_stop(pdd); } return -EINVAL; From f971e4210cb039e95a3b6a274949e8b40f12a871 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 14:50:00 -0400 Subject: [PATCH 1203/2653] drm/amdkfd: enable pc sampling destroy Enable pc sampling destroy. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 72c66d4bd24f9..b46caa52fbe83 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -186,10 +186,24 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, return 0; } -static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_id) +static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_id, + struct pc_sampling_entry *pcs_entry) { - return -EINVAL; + pr_debug("free pcs_entry = %p, trace_id = 0x%x on gpu 0x%x", + pcs_entry, trace_id, pdd->dev->id); + + mutex_lock(&pdd->dev->pcs_data.mutex); + pdd->dev->pcs_data.hosttrap_entry.base.use_count--; + idr_remove(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, trace_id); + if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) + memset(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, 0x0, + sizeof(struct kfd_pc_sample_info)); + mutex_unlock(&pdd->dev->pcs_data.mutex); + + kfree(pcs_entry); + + return 0; } int kfd_pc_sample(struct kfd_process_device *pdd, @@ -224,7 +238,7 @@ int kfd_pc_sample(struct kfd_process_device *pdd, if (pcs_entry->enabled) return -EBUSY; else - return kfd_pc_sample_destroy(pdd, args->trace_id); + return kfd_pc_sample_destroy(pdd, args->trace_id, pcs_entry); case KFD_IOCTL_PCS_OP_START: if (pcs_entry->enabled) From b9c0a37fd03d6571fff9355ca6f1c8b769258824 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 14:11:56 -0400 Subject: [PATCH 1204/2653] drm/amdkfd: add interface to trigger pc sampling trap Add interface to trigger pc sampling trap. -v6: add multiple instances support Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index ed07155666ab6..32f92e0ac3588 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -31,6 +31,8 @@ #include #include #include +#include + #include "amdgpu_irq.h" #include "amdgpu_gfx.h" @@ -338,6 +340,12 @@ struct kfd2kgd_calls { uint32_t inst, unsigned int utimeout); uint32_t (*hqd_sdma_get_doorbell)(struct amdgpu_device *adev, int engine, int queue); + uint32_t (*trigger_pc_sample_trap)(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst); }; #endif /* KGD_KFD_INTERFACE_H_INCLUDED */ From 29f50f715e8fb04924822ed5a32eaad1c6c430b7 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Sun, 6 Aug 2023 12:41:03 -0400 Subject: [PATCH 1205/2653] drm/amdkfd: trigger pc sampling trap for gfx v9 Implement trigger pc sampling trap for gfx v9. -v6: add multiple instances support Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 36 +++++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h | 8 +++++ 2 files changed, 44 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index 088d09cc7a724..a01917aa8b75d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1225,8 +1225,44 @@ uint64_t kgd_gfx_v9_hqd_reset(struct amdgpu_device *adev, uint32_t kgd_gfx_v9_hqd_sdma_get_doorbell(struct amdgpu_device *adev, int engine, int queue) +{ + return 0; +} +uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t max_wave_slot, + uint32_t max_simd, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) { + if (method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + uint32_t value = 0; + + value = REG_SET_FIELD(value, SQ_CMD, CMD, SQ_IND_CMD_CMD_TRAP); + value = REG_SET_FIELD(value, SQ_CMD, MODE, SQ_IND_CMD_MODE_SINGLE); + + /* select *target_simd */ + value = REG_SET_FIELD(value, SQ_CMD, SIMD_ID, *target_simd); + /* select *target_wave_slot */ + value = REG_SET_FIELD(value, SQ_CMD, WAVE_ID, (*target_wave_slot)++); + + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_CMD, value); + mutex_unlock(&adev->grbm_idx_mutex); + + *target_wave_slot %= max_wave_slot; + if (!(*target_wave_slot)) { + (*target_simd)++; + *target_simd %= max_simd; + } + } else { + pr_debug("PC Sampling method %d not supported.", method); + return -EOPNOTSUPP; + } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h index 704452ca62f8e..892c91a1c1b63 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h @@ -114,3 +114,11 @@ uint64_t kgd_gfx_v9_hqd_reset(struct amdgpu_device *adev, unsigned int utimeout); uint32_t kgd_gfx_v9_hqd_sdma_get_doorbell(struct amdgpu_device *adev, int engine, int queue); +uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t max_wave_slot, + uint32_t max_simd, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst); From 003cae012c1d23323b43052f63ce713605187e7c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 4 Mar 2025 21:49:25 +0800 Subject: [PATCH 1206/2653] Revert "drm/amdkfd: Clear MODE.VSKIP in gfx9 trap handler" This reverts commit 1241b64d4be8f9cc013711df9847436ef1599b24. --- .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 2851 ++++++++--------- .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 4 +- 2 files changed, 1424 insertions(+), 1431 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index 0320163b6e740..daa88ffd8a893 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -274,7 +274,7 @@ static const uint32_t cwsr_trap_gfx8_hex[] = { static const uint32_t cwsr_trap_gfx9_hex[] = { - 0xbf820001, 0xbf820259, + 0xbf820001, 0xbf820258, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -390,142 +390,98 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0xbefe007c, 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbf108080, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xbefc007e, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf85004d, 0xbe840080, + 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840063, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf84005f, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850030, - 0x24040682, 0xd86e4000, - 0x00000002, 0xbf8cc07f, 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000200, - 0xd0c9006a, 0x0000f702, - 0xbf87ffd2, 0xbf820015, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbf87fff7, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2a05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, - 0x807bff7b, 0x00001000, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb4306, 0x867bc17b, + 0xbf840063, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf84005f, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, + 0xbf850030, 0x24040682, + 0xd86e4000, 0x00000002, + 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -544,138 +500,181 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x680404ff, + 0x00000200, 0xd0c9006a, + 0x0000f702, 0xbf87ffd2, + 0xbf820015, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbf87fff7, 0xbef70000, + 0xbef000ff, 0x00000400, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb2a05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850051, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0x807c847c, 0x8070ff70, - 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xbf8200c7, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf84001e, - 0xbefe00c1, 0xbeff00c1, - 0xb8ef4306, 0x866fc16f, - 0xbf840019, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82a05, 0x80788178, - 0x8e788a78, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0x807cff7c, 0x00000200, - 0x8078ff78, 0x00000200, - 0xbf0a6f7c, 0xbf85fff6, - 0xbefe00c1, 0xbeff00c1, - 0xbef600ff, 0x01000000, - 0xb8ef2a05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, - 0xbf11087c, 0xe0524000, - 0x781d0000, 0xe0524100, - 0x781d0100, 0xe0524200, - 0x781d0200, 0xe0524300, - 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0x807c847c, 0x8078ff78, - 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82a05, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xbf8200c7, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf84001e, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf840019, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82a05, 0x80788178, 0x8e788a78, 0xb8ee1605, 0x806e816e, 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, + 0x8078ff78, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0x807cff7c, + 0x00000200, 0x8078ff78, + 0x00000200, 0xbf0a6f7c, + 0xbf85fff6, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2a05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, 0xb8f82a05, 0x80788178, 0x8e788a78, 0xb8ee1605, 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82a05, + 0x80788178, 0x8e788a78, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2a05, 0x806e816e, - 0x8e6e8a6e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b77, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2a05, + 0x806e816e, 0x8e6e8a6e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b77, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, }; static const uint32_t cwsr_trap_nv1x_hex[] = { @@ -1303,7 +1302,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { }; static const uint32_t cwsr_trap_arcturus_hex[] = { - 0xbf820001, 0xbf8202d5, + 0xbf820001, 0xbf8202d4, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -1420,37 +1419,99 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0xbefe007c, 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbf108080, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, - 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, - 0xbef600ff, 0x01000000, + 0xbefc007e, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85004d, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb4306, + 0x867bc17b, 0xbf840064, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf840060, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, + 0xbf850030, 0x24040682, + 0xd86e4000, 0x00000002, + 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -1469,50 +1530,31 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, - 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, - 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, - 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, + 0xbf84ffee, 0x680404ff, + 0x00000200, 0xd0c9006a, + 0x0000f702, 0xbf87ffd2, + 0xbf820015, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbf87fff7, 0xbef70000, + 0xbef000ff, 0x00000400, 0xbefe00c1, 0xbeff00c1, - 0xb8fb4306, 0x867bc17b, - 0xbf840064, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf840060, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, + 0xb8fb2a05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850030, - 0x24040682, 0xd86e4000, - 0x00000002, 0xbf8cc07f, + 0x10000000, 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -1532,259 +1574,215 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000200, - 0xd0c9006a, 0x0000f702, - 0xbf87ffd2, 0xbf820015, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbf87fff7, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2a05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, - 0x807bff7b, 0x00001000, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000903, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0x807c847c, 0x8070ff70, - 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xbefc0080, 0xbf11017c, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf850059, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xbe840080, - 0xd2890000, 0x00000900, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000903, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, - 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffa9, - 0xbf9c0000, 0xbf820016, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0x807c847c, 0x8070ff70, - 0x00000400, 0xbf0a7b7c, - 0xbf85ffeb, 0xbf9c0000, - 0xbf8200e3, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf84001f, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf8200e3, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf84001f, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf84001a, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82a05, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, 0xbefe00c1, 0xbeff00c1, - 0xb8ef4306, 0x866fc16f, - 0xbf84001a, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82a05, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2a05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xbefc0080, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0xd3d94000, - 0x18000100, 0xd3d94001, - 0x18000101, 0xd3d94002, - 0x18000102, 0xd3d94003, - 0x18000103, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffea, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, - 0xb8f82a05, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, - 0xb8f82a05, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0xb8ef2a05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, + 0xbf11087c, 0xe0524000, + 0x781d0000, 0xe0524100, + 0x781d0100, 0xe0524200, + 0x781d0200, 0xe0524300, + 0x781d0300, 0xbf8c0f70, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0x807c847c, 0x8078ff78, + 0x00000400, 0xbf0a6f7c, + 0xbf85ffee, 0xbefc0080, + 0xbf11087c, 0xe0524000, + 0x781d0000, 0xe0524100, + 0x781d0100, 0xe0524200, + 0x781d0200, 0xe0524300, + 0x781d0300, 0xbf8c0f70, + 0xd3d94000, 0x18000100, + 0xd3d94001, 0x18000101, + 0xd3d94002, 0x18000102, + 0xd3d94003, 0x18000103, + 0x807c847c, 0x8078ff78, + 0x00000400, 0xbf0a6f7c, + 0xbf85ffea, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82a05, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, + 0xbef600ff, 0x01000000, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82a05, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2a05, - 0x806e816e, 0x8e6e8a6e, - 0x8e6e816e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b77, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2a05, 0x806e816e, + 0x8e6e8a6e, 0x8e6e816e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b77, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, }; static const uint32_t cwsr_trap_aldebaran_hex[] = { - 0xbf820001, 0xbf8202e0, + 0xbf820001, 0xbf8202df, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -1831,169 +1829,106 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x0000ffff, 0x8f7a8b77, 0x867aff7a, 0x001f8000, 0xb97af807, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e8378, - 0xb96ee0c2, 0xbf800002, - 0xb9780002, 0xbe801f6c, - 0x866dff6d, 0x0000ffff, - 0xbefa0080, 0xb97a0283, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbf900004, 0x877a8478, - 0xb97af802, 0xbf8e0002, - 0xbf88fffe, 0xb8fa2985, - 0x807a817a, 0x8e7a8a7a, - 0x8e7a817a, 0xb8fb1605, - 0x807b817b, 0x8e7b867b, - 0x807a7b7a, 0x807a7e7a, - 0x827b807f, 0x867bff7b, - 0x0000ffff, 0xc04b1c3d, - 0x00000050, 0xbf8cc07f, - 0xc04b1d3d, 0x00000060, - 0xbf8cc07f, 0xc0431e7d, - 0x00000074, 0xbf8cc07f, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0xbef1007c, 0xbef00080, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611b3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611bba, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bfa, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611e3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8fbf803, - 0xbefe007c, 0xbefc0070, - 0xc0611efa, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a3a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611a7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8f1f801, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbf108080, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, - 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, - 0xbef600ff, 0x01000000, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, - 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, - 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, - 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, - 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb4306, 0x867bc17b, - 0xbf840064, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf840060, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, + 0x86ea6a6a, 0x8f6e8378, + 0xb96ee0c2, 0xbf800002, + 0xb9780002, 0xbe801f6c, + 0x866dff6d, 0x0000ffff, + 0xbefa0080, 0xb97a0283, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8977ff77, 0xfc000000, + 0x87777a77, 0xba7ff807, + 0x00000000, 0xbeee007e, + 0xbeef007f, 0xbefe0180, + 0xbf900004, 0x877a8478, + 0xb97af802, 0xbf8e0002, + 0xbf88fffe, 0xb8fa2985, + 0x807a817a, 0x8e7a8a7a, + 0x8e7a817a, 0xb8fb1605, + 0x807b817b, 0x8e7b867b, + 0x807a7b7a, 0x807a7e7a, + 0x827b807f, 0x867bff7b, + 0x0000ffff, 0xc04b1c3d, + 0x00000050, 0xbf8cc07f, + 0xc04b1d3d, 0x00000060, + 0xbf8cc07f, 0xc0431e7d, + 0x00000074, 0xbf8cc07f, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0xbef1007c, 0xbef00080, 0xb8f02985, 0x80708170, 0x8e708a70, 0x8e708170, 0xb8fa1605, 0x807a817a, 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611b3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611b7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611bba, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611bfa, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611e3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8fbf803, + 0xbefe007c, 0xbefc0070, + 0xc0611efa, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611a7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8f1f801, + 0xbefe007c, 0xbefc0070, + 0xc0611c7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850030, - 0x24040682, 0xd86e4000, - 0x00000002, 0xbf8cc07f, + 0x10000000, 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -2013,31 +1948,50 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000200, - 0xd0c9006a, 0x0000f702, - 0xbf87ffd2, 0xbf820015, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbf87fff7, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2b05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, - 0x807bff7b, 0x00001000, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb4306, + 0x867bc17b, 0xbf840064, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf840060, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, + 0xbf850030, 0x24040682, + 0xd86e4000, 0x00000002, + 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -2056,51 +2010,31 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, - 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, - 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, - 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0x807c847c, 0x8070ff70, - 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xb8fb2985, 0x807b817b, - 0x8e7b837b, 0xb8fa2b05, - 0x807a817a, 0x8e7a827a, - 0x80fb7a7b, 0x867b7b7b, - 0xbf84007a, 0x807bff7b, - 0x00001000, 0xbefc0080, - 0xbf11017c, 0x867aff78, + 0xbf84ffee, 0x680404ff, + 0x00000200, 0xd0c9006a, + 0x0000f702, 0xbf87ffd2, + 0xbf820015, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbf87fff7, 0xbef70000, + 0xbef000ff, 0x00000400, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb2b05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850059, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0x10000000, 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -2140,139 +2074,202 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, 0xbf0a7b7c, - 0xbf85ffa9, 0xbf9c0000, - 0xbf820016, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xe0724000, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffeb, - 0xbf9c0000, 0xbf8200ee, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf84001f, 0xbefe00c1, - 0xbeff00c1, 0xb8ef4306, - 0x866fc16f, 0xbf84001a, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0x807cff7c, 0x00000200, - 0x8078ff78, 0x00000200, - 0xbf0a6f7c, 0xbf85fff6, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xb8fb2985, + 0x807b817b, 0x8e7b837b, + 0xb8fa2b05, 0x807a817a, + 0x8e7a827a, 0x80fb7a7b, + 0x867b7b7b, 0xbf84007a, + 0x807bff7b, 0x00001000, + 0xbefc0080, 0xbf11017c, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf850059, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, + 0x00000900, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, + 0x80048104, 0xd2890002, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000902, + 0x80048104, 0xd2890001, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, + 0x80048104, 0xd2890003, + 0x00000902, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffa9, + 0xbf9c0000, 0xbf820016, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffeb, 0xbf9c0000, + 0xbf8200ee, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf84001f, 0xbefe00c1, 0xbeff00c1, + 0xb8ef4306, 0x866fc16f, + 0xbf84001a, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xb8ef2b05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0x807cff7c, + 0x00000200, 0x8078ff78, + 0x00000200, 0xbf0a6f7c, + 0xbf85fff6, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2b05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xb8ef2985, 0x806f816f, + 0x8e6f836f, 0xb8f92b05, + 0x80798179, 0x8e798279, + 0x80ef796f, 0x866f6f6f, + 0xbf84001a, 0x806fff6f, + 0x00008000, 0xbefc0080, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, + 0xd3d94000, 0x18000100, + 0xd3d94001, 0x18000101, + 0xd3d94002, 0x18000102, + 0xd3d94003, 0x18000103, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xb8ef2985, - 0x806f816f, 0x8e6f836f, - 0xb8f92b05, 0x80798179, - 0x8e798279, 0x80ef796f, - 0x866f6f6f, 0xbf84001a, - 0x806fff6f, 0x00008000, - 0xbefc0080, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0xd3d94000, - 0x18000100, 0xd3d94001, - 0x18000101, 0xd3d94002, - 0x18000102, 0xd3d94003, - 0x18000103, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffea, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0xbf85ffea, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, + 0xbef600ff, 0x01000000, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2985, - 0x806e816e, 0x8e6e8a6e, - 0x8e6e816e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b77, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2985, 0x806e816e, + 0x8e6e8a6e, 0x8e6e816e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b77, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, }; static const uint32_t cwsr_trap_gfx10_hex[] = { @@ -3154,7 +3151,7 @@ static const uint32_t cwsr_trap_gfx11_hex[] = { }; static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { - 0xbf820001, 0xbf8202dc, + 0xbf820001, 0xbf8202db, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -3225,143 +3222,80 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0x00000074, 0xbf8cc07f, 0xbef4007e, 0x8675ff7f, 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0xbef1007c, 0xbef00080, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611b3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611bba, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bfa, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611e3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8fbf803, - 0xbefe007c, 0xbefc0070, - 0xc0611efa, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a3a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611a7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8f1f801, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbf108080, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, - 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, - 0xbef600ff, 0x01000000, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, - 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, - 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, - 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, - 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb4306, 0x867bc17b, - 0xbf840064, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf840060, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0xbef1007c, 0xbef00080, 0xb8f02985, 0x80708170, 0x8e708a70, 0x8e708170, 0xb8fa1605, 0x807a817a, 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611b3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611b7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611bba, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611bfa, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611e3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8fbf803, + 0xbefe007c, 0xbefc0070, + 0xc0611efa, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611a7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8f1f801, + 0xbefe007c, 0xbefc0070, + 0xc0611c7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850030, - 0x24040682, 0xd86e4000, - 0x00000002, 0xbf8cc07f, + 0x10000000, 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -3381,31 +3315,50 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000200, - 0xd0c9006a, 0x0000f702, - 0xbf87ffd2, 0xbf820015, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbf87fff7, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2b05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, - 0x807bff7b, 0x00001000, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb4306, + 0x867bc17b, 0xbf840064, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf840060, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, + 0xbf850030, 0x24040682, + 0xd86e4000, 0x00000002, + 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -3424,51 +3377,31 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, - 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, - 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, - 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0x807c847c, 0x8070ff70, - 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xb8fb2985, 0x807b817b, - 0x8e7b837b, 0xb8fa2b05, - 0x807a817a, 0x8e7a827a, - 0x80fb7a7b, 0x867b7b7b, - 0xbf84007a, 0x807bff7b, - 0x00001000, 0xbefc0080, - 0xbf11017c, 0x867aff78, + 0xbf84ffee, 0x680404ff, + 0x00000200, 0xd0c9006a, + 0x0000f702, 0xbf87ffd2, + 0xbf820015, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbf87fff7, 0xbef70000, + 0xbef000ff, 0x00000400, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb2b05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850059, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0x10000000, 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -3508,139 +3441,202 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, 0xbf0a7b7c, - 0xbf85ffa9, 0xbf9c0000, - 0xbf820016, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xe0724000, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffeb, - 0xbf9c0000, 0xbf8200ee, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf84001f, 0xbefe00c1, - 0xbeff00c1, 0xb8ef4306, - 0x866fc16f, 0xbf84001a, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0x807cff7c, 0x00000200, - 0x8078ff78, 0x00000200, - 0xbf0a6f7c, 0xbf85fff6, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xb8fb2985, + 0x807b817b, 0x8e7b837b, + 0xb8fa2b05, 0x807a817a, + 0x8e7a827a, 0x80fb7a7b, + 0x867b7b7b, 0xbf84007a, + 0x807bff7b, 0x00001000, + 0xbefc0080, 0xbf11017c, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf850059, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, + 0x00000900, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, + 0x80048104, 0xd2890002, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000902, + 0x80048104, 0xd2890001, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, + 0x80048104, 0xd2890003, + 0x00000902, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffa9, + 0xbf9c0000, 0xbf820016, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffeb, 0xbf9c0000, + 0xbf8200ee, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf84001f, 0xbefe00c1, 0xbeff00c1, + 0xb8ef4306, 0x866fc16f, + 0xbf84001a, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xb8ef2b05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0x807cff7c, + 0x00000200, 0x8078ff78, + 0x00000200, 0xbf0a6f7c, + 0xbf85fff6, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2b05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xb8ef2985, 0x806f816f, + 0x8e6f836f, 0xb8f92b05, + 0x80798179, 0x8e798279, + 0x80ef796f, 0x866f6f6f, + 0xbf84001a, 0x806fff6f, + 0x00008000, 0xbefc0080, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, + 0xd3d94000, 0x18000100, + 0xd3d94001, 0x18000101, + 0xd3d94002, 0x18000102, + 0xd3d94003, 0x18000103, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xb8ef2985, - 0x806f816f, 0x8e6f836f, - 0xb8f92b05, 0x80798179, - 0x8e798279, 0x80ef796f, - 0x866f6f6f, 0xbf84001a, - 0x806fff6f, 0x00008000, - 0xbefc0080, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0xd3d94000, - 0x18000100, 0xd3d94001, - 0x18000101, 0xd3d94002, - 0x18000102, 0xd3d94003, - 0x18000103, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffea, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0xbf85ffea, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, + 0xbef600ff, 0x01000000, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2985, - 0x806e816e, 0x8e6e8a6e, - 0x8e6e816e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b79, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2985, 0x806e816e, + 0x8e6e8a6e, 0x8e6e816e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b79, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, }; static const uint32_t cwsr_trap_gfx12_hex[] = { @@ -4172,7 +4168,7 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { }; static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { - 0xbf820001, 0xbf8202ca, + 0xbf820001, 0xbf8202c9, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -4287,99 +4283,133 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0xbefe007c, 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbf108080, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, - 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, - 0xbef600ff, 0x01000000, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, + 0xbefc007e, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85004d, 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb5306, 0x867bc17b, - 0xbf840052, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf84004e, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb5306, + 0x867bc17b, 0xbf840052, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf84004e, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf85001d, 0x24040682, + 0xd86c0000, 0x00000002, + 0xbf8cc07f, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, + 0x00000900, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x680404ff, 0x00000100, + 0xd0c9006a, 0x0000f702, + 0xbf87ffe5, 0xbf820016, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbefe016a, + 0xbf87fff6, 0xbef70000, + 0xbef000ff, 0x00000400, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb2b05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85001d, - 0x24040682, 0xd86c0000, - 0x00000002, 0xbf8cc07f, + 0x10000000, 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -4389,32 +4419,61 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000100, 0xd0c9006a, - 0x0000f702, 0xbf87ffe5, - 0xbf820016, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbefe016a, 0xbf87fff6, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2b05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xb8fb2985, + 0x807b817b, 0x8e7b837b, + 0xb8fa2b05, 0x807a817a, + 0x8e7a827a, 0x80fb7a7b, + 0x867b7b7b, 0xbf84007a, 0x807bff7b, 0x00001000, + 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, + 0xbf850059, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -4453,204 +4512,140 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, + 0xbf0a7b7c, 0xbf85ffa9, + 0xbf9c0000, 0xbf820016, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xb8fb2985, 0x807b817b, - 0x8e7b837b, 0xb8fa2b05, - 0x807a817a, 0x8e7a827a, - 0x80fb7a7b, 0x867b7b7b, - 0xbf84007a, 0x807bff7b, - 0x00001000, 0xbefc0080, - 0xbf11017c, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850059, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffa9, 0xbf9c0000, - 0xbf820016, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffeb, - 0xbf9c0000, 0xbf8200f4, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf840025, 0xbefe00c1, - 0xbeff00c1, 0xb8ef5306, - 0x866fc16f, 0xbf840020, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0xe0510200, 0x781d0000, - 0xe0510300, 0x781d0000, - 0xe0510400, 0x781d0000, - 0x807cff7c, 0x00000500, - 0x8078ff78, 0x00000500, - 0xbf0a6f7c, 0xbf85fff0, + 0xbf85ffeb, 0xbf9c0000, + 0xbf8200f4, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf840025, 0xbefe00c1, 0xbeff00c1, + 0xb8ef5306, 0x866fc16f, + 0xbf840020, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xb8ef2b05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0xe0510200, + 0x781d0000, 0xe0510300, + 0x781d0000, 0xe0510400, + 0x781d0000, 0x807cff7c, + 0x00000500, 0x8078ff78, + 0x00000500, 0xbf0a6f7c, + 0xbf85fff0, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2b05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xb8ef2985, 0x806f816f, + 0x8e6f836f, 0xb8f92b05, + 0x80798179, 0x8e798279, + 0x80ef796f, 0x866f6f6f, + 0xbf84001a, 0x806fff6f, + 0x00008000, 0xbefc0080, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, + 0xd3d94000, 0x18000100, + 0xd3d94001, 0x18000101, + 0xd3d94002, 0x18000102, + 0xd3d94003, 0x18000103, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xb8ef2985, - 0x806f816f, 0x8e6f836f, - 0xb8f92b05, 0x80798179, - 0x8e798279, 0x80ef796f, - 0x866f6f6f, 0xbf84001a, - 0x806fff6f, 0x00008000, - 0xbefc0080, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0xd3d94000, - 0x18000100, 0xd3d94001, - 0x18000101, 0xd3d94002, - 0x18000102, 0xd3d94003, - 0x18000103, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffea, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0xbf85ffea, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, + 0xbef600ff, 0x01000000, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2985, - 0x806e816e, 0x8e6e8a6e, - 0x8e6e816e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b79, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2985, 0x806e816e, + 0x8e6e8a6e, 0x8e6e816e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b79, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, }; diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index 6869e07a2fff2..0eabb7a8cab94 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -447,9 +447,7 @@ L_SAVE: s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) //MODE write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) - // Clear VSKIP state now that MODE.VSKIP has been saved. - // If user shader set it then vector instructions would be skipped. - s_setvskip 0,0 + /* the first wave in the threadgroup */ s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit From b9c4e70f37994ff1dea7431c04fb7cfb284467a2 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Sat, 12 Aug 2023 14:46:44 -0400 Subject: [PATCH 1207/2653] drm/amdkfd/gfx9: enable host trap Enable host trap. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 63 +++++++++++-------- .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 24 ++++--- 2 files changed, 52 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index daa88ffd8a893..91696f6a8ace6 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -274,14 +274,14 @@ static const uint32_t cwsr_trap_gfx8_hex[] = { static const uint32_t cwsr_trap_gfx9_hex[] = { - 0xbf820001, 0xbf820258, + 0xbf820001, 0xbf82025e, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840009, 0x866eff6d, 0x00ff0000, 0xbf85001e, 0x866eff7b, 0x00000400, - 0xbf850055, 0xbf8e0010, + 0xbf85005b, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03c00900, 0xbf850015, 0x866eff7b, @@ -294,7 +294,7 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0xbf850007, 0xb8eef801, 0x866eff6e, 0x00000800, 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, + 0x00000400, 0xbf850040, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8977ff77, 0xfc000000, @@ -303,13 +303,16 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0xb8fbf813, 0x8efa887a, 0xbf0d8f7b, 0xbf840002, 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8977ff77, 0x00800000, - 0x87776e77, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, + 0xc0031c3d, 0x00000010, + 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, + 0xbf8cc07f, 0x8671ff6d, + 0x01000000, 0xbf840004, + 0x92f1ff70, 0x00010001, + 0xbf840016, 0xbf820005, + 0x86708170, 0x8e709770, + 0x8977ff77, 0x00800000, + 0x87777077, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, 0x8778ff78, @@ -1302,14 +1305,14 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { }; static const uint32_t cwsr_trap_arcturus_hex[] = { - 0xbf820001, 0xbf8202d4, + 0xbf820001, 0xbf8202da, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840009, 0x866eff6d, 0x00ff0000, 0xbf85001e, 0x866eff7b, 0x00000400, - 0xbf850055, 0xbf8e0010, + 0xbf85005b, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03c00900, 0xbf850015, 0x866eff7b, @@ -1322,7 +1325,7 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0xbf850007, 0xb8eef801, 0x866eff6e, 0x00000800, 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, + 0x00000400, 0xbf850040, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8977ff77, 0xfc000000, @@ -1331,13 +1334,16 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0xb8fbf813, 0x8efa887a, 0xbf0d8f7b, 0xbf840002, 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8977ff77, 0x00800000, - 0x87776e77, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, + 0xc0031c3d, 0x00000010, + 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, + 0xbf8cc07f, 0x8671ff6d, + 0x01000000, 0xbf840004, + 0x92f1ff70, 0x00010001, + 0xbf840016, 0xbf820005, + 0x86708170, 0x8e709770, + 0x8977ff77, 0x00800000, + 0x87777077, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, 0x8778ff78, @@ -1782,14 +1788,14 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { }; static const uint32_t cwsr_trap_aldebaran_hex[] = { - 0xbf820001, 0xbf8202df, + 0xbf820001, 0xbf8202e5, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840009, 0x866eff6d, 0x00ff0000, 0xbf85001e, 0x866eff7b, 0x00000400, - 0xbf850055, 0xbf8e0010, + 0xbf85005b, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03c00900, 0xbf850015, 0x866eff7b, @@ -1802,7 +1808,7 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xbf850007, 0xb8eef801, 0x866eff6e, 0x00000800, 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, + 0x00000400, 0xbf850040, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8977ff77, 0xfc000000, @@ -1811,13 +1817,16 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xb8fbf813, 0x8efa887a, 0xbf0d8f7b, 0xbf840002, 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8977ff77, 0x00800000, - 0x87776e77, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, + 0xc0031c3d, 0x00000010, + 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, + 0xbf8cc07f, 0x8671ff6d, + 0x01000000, 0xbf840004, + 0x92f1ff70, 0x00010001, + 0xbf840016, 0xbf820005, + 0x86708170, 0x8e709770, + 0x8977ff77, 0x00800000, + 0x87777077, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, 0x8778ff78, diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index 0eabb7a8cab94..ada7df7e6f21b 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -121,6 +121,10 @@ var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x1F8000 var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800 +var TMA_HOST_TRAP_EN_SHIFT = 1 +var TMA_HOST_TRAP_EN_SIZE = 1 +var TMA_HOST_TRAP_EN_BFE = (TMA_HOST_TRAP_EN_SHIFT | (TMA_HOST_TRAP_EN_SIZE << 16)) + var TTMP_SAVE_RCNT_FIRST_REPLAY_SHIFT = 26 // bits [31:26] unused by SPI debug data var TTMP_SAVE_RCNT_FIRST_REPLAY_MASK = 0xFC000000 var TTMP_DEBUG_TRAP_ENABLED_SHIFT = 23 @@ -305,17 +309,21 @@ L_FETCH_2ND_TRAP: s_or_b32 ttmp15, ttmp15, 0xFFFF0000 L_NO_SIGN_EXTEND_TMA: - s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 glc:1 // debug trap enabled flag - s_waitcnt lgkmcnt(0) - s_lshl_b32 ttmp2, ttmp2, TTMP_DEBUG_TRAP_ENABLED_SHIFT - s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_DEBUG_TRAP_ENABLED_MASK - s_or_b32 s_save_ib_sts, s_save_ib_sts, ttmp2 - + s_load_dword ttmp4, [ttmp14, ttmp15], 0x10 glc:1 // enable flags from 1st level TMA s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 // second-level TBA - s_waitcnt lgkmcnt(0) s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA s_waitcnt lgkmcnt(0) - + s_and_b32 ttmp5, s_save_pc_hi, S_SAVE_PC_HI_HT_MASK // host trap request + s_cbranch_scc0 L_NOT_HT + s_bfe_u32 ttmp5, ttmp4, TMA_HOST_TRAP_EN_BFE // extract host_trap_en to ttmp5[0] + s_cbranch_scc0 L_EXIT_TRAP // HT requested, but host traps not enabled + s_branch L_GOTO_2ND_TRAP +L_NOT_HT: + s_and_b32 ttmp4, ttmp4, 0x1 // debug_enable bit left over + s_lshl_b32 ttmp4, ttmp4, TTMP_DEBUG_TRAP_ENABLED_SHIFT + s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_DEBUG_TRAP_ENABLED_MASK + s_or_b32 s_save_ib_sts, s_save_ib_sts, ttmp4 +L_GOTO_2ND_TRAP: s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler From 4a2065acdd7d6170876e2b681bfbcf2e30f56f1b Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 27 Sep 2023 11:01:18 -0400 Subject: [PATCH 1208/2653] drm/amdgpu: use trapID 4 for host trap Since TRAPSTS.HOST_TRAP won't work pre-gfx943, so use TTMP1 (bit 24: HT) and (bit 16-23: trapID) to identify the host trap. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 2 + .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 2103 +++++++++-------- .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 5 + 3 files changed, 1063 insertions(+), 1047 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index a01917aa8b75d..7e059eb963d54 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1248,6 +1248,8 @@ uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, value = REG_SET_FIELD(value, SQ_CMD, SIMD_ID, *target_simd); /* select *target_wave_slot */ value = REG_SET_FIELD(value, SQ_CMD, WAVE_ID, (*target_wave_slot)++); + /* set TrapID 4 for HOSTTRAP */ + value = REG_SET_FIELD(value, SQ_CMD, DATA, 0x4); mutex_lock(&adev->grbm_idx_mutex); amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index 91696f6a8ace6..dba37ed1de505 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -274,155 +274,263 @@ static const uint32_t cwsr_trap_gfx8_hex[] = { static const uint32_t cwsr_trap_gfx9_hex[] = { - 0xbf820001, 0xbf82025e, + 0xbf820001, 0xbf820263, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001e, + 0x00ff0000, 0xbf850023, 0x866eff7b, 0x00000400, - 0xbf85005b, 0xbf8e0010, + 0xbf850060, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03c00900, - 0xbf850015, 0x866eff7b, - 0x000071ff, 0xbf840008, - 0x866fff7b, 0x00007080, - 0xbf840001, 0xbeee1a87, - 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf85000a, - 0x866eff6d, 0x00ff0000, - 0xbf850007, 0xb8eef801, - 0x866eff6e, 0x00000800, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf850040, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xb8faf812, - 0xb8fbf813, 0x8efa887a, - 0xbf0d8f7b, 0xbf840002, - 0x877bff7b, 0xffff0000, - 0xc0031c3d, 0x00000010, - 0xc0071bbd, 0x00000000, - 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x8671ff6d, - 0x01000000, 0xbf840004, - 0x92f1ff70, 0x00010001, - 0xbf840016, 0xbf820005, - 0x86708170, 0x8e709770, - 0x8977ff77, 0x00800000, - 0x87777077, 0x86ee6e6e, - 0xbf840001, 0xbe801d6e, - 0x866eff6d, 0x01ff0000, - 0xbf850005, 0x8778ff78, - 0x00002000, 0x80ec886c, - 0x82ed806d, 0xbf820005, - 0x866eff6d, 0x01000000, - 0xbf850002, 0x806c846c, - 0x826d806d, 0x866dff6d, - 0x0000ffff, 0x8f7a8b77, + 0xbf85001a, 0x866eff6d, + 0x01ff0000, 0xbf06ff6e, + 0x01040000, 0xbf850015, + 0x866eff7b, 0x000071ff, + 0xbf840008, 0x866fff7b, + 0x00007080, 0xbf840001, + 0xbeee1a87, 0xb8eff801, + 0x8e6e8c6e, 0x866e6f6e, + 0xbf85000a, 0x866eff6d, + 0x00ff0000, 0xbf850007, + 0xb8eef801, 0x866eff6e, + 0x00000800, 0xbf850003, + 0x866eff7b, 0x00000400, + 0xbf850040, 0xb8faf807, 0x867aff7a, 0x001f8000, - 0xb97af807, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e8378, - 0xb96ee0c2, 0xbf800002, - 0xb9780002, 0xbe801f6c, + 0x8e7a8b7a, 0x8977ff77, + 0xfc000000, 0x87777a77, + 0xba7ff807, 0x00000000, + 0xb8faf812, 0xb8fbf813, + 0x8efa887a, 0xbf0d8f7b, + 0xbf840002, 0x877bff7b, + 0xffff0000, 0xc0031c3d, + 0x00000010, 0xc0071bbd, + 0x00000000, 0xc0071ebd, + 0x00000008, 0xbf8cc07f, + 0x8671ff6d, 0x01000000, + 0xbf840004, 0x92f1ff70, + 0x00010001, 0xbf840016, + 0xbf820005, 0x86708170, + 0x8e709770, 0x8977ff77, + 0x00800000, 0x87777077, + 0x86ee6e6e, 0xbf840001, + 0xbe801d6e, 0x866eff6d, + 0x01ff0000, 0xbf850005, + 0x8778ff78, 0x00002000, + 0x80ec886c, 0x82ed806d, + 0xbf820005, 0x866eff6d, + 0x01000000, 0xbf850002, + 0x806c846c, 0x826d806d, 0x866dff6d, 0x0000ffff, - 0xbefa0080, 0xb97a0283, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbf900004, 0x877a8478, - 0xb97af802, 0xbf8e0002, - 0xbf88fffe, 0xb8fa2a05, - 0x807a817a, 0x8e7a8a7a, - 0xb8fb1605, 0x807b817b, - 0x8e7b867b, 0x807a7b7a, - 0x807a7e7a, 0x827b807f, - 0x867bff7b, 0x0000ffff, - 0xc04b1c3d, 0x00000050, - 0xbf8cc07f, 0xc04b1d3d, - 0x00000060, 0xbf8cc07f, - 0xc0431e7d, 0x00000074, - 0xbf8cc07f, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0xbef1007c, - 0xbef00080, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, + 0x8f7a8b77, 0x867aff7a, + 0x001f8000, 0xb97af807, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e8378, 0xb96ee0c2, + 0xbf800002, 0xb9780002, + 0xbe801f6c, 0x866dff6d, + 0x0000ffff, 0xbefa0080, + 0xb97a0283, 0xb8faf807, + 0x867aff7a, 0x001f8000, + 0x8e7a8b7a, 0x8977ff77, + 0xfc000000, 0x87777a77, + 0xba7ff807, 0x00000000, + 0xbeee007e, 0xbeef007f, + 0xbefe0180, 0xbf900004, + 0x877a8478, 0xb97af802, + 0xbf8e0002, 0xbf88fffe, + 0xb8fa2a05, 0x807a817a, + 0x8e7a8a7a, 0xb8fb1605, + 0x807b817b, 0x8e7b867b, + 0x807a7b7a, 0x807a7e7a, + 0x827b807f, 0x867bff7b, + 0x0000ffff, 0xc04b1c3d, + 0x00000050, 0xbf8cc07f, + 0xc04b1d3d, 0x00000060, + 0xbf8cc07f, 0xc0431e7d, + 0x00000074, 0xbf8cc07f, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0xbef1007c, 0xbef00080, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0xbef60084, + 0xbef600ff, 0x01000000, 0xbefe007c, 0xbefc0070, - 0xc0611b3a, 0x0000007c, + 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b7a, + 0xbefc0070, 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bba, 0x0000007c, + 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bfa, + 0xbefc0070, 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611e3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8fbf803, - 0xbefe007c, 0xbefc0070, - 0xc0611efa, 0x0000007c, + 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a3a, + 0xbefc0070, 0xc0611e3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8fbf803, 0xbefe007c, + 0xbefc0070, 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8f1f801, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, + 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02a05, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8f1f801, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85004d, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb4306, + 0x867bc17b, 0xbf840063, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf84005f, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02a05, 0x80708170, 0x8e708a70, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2a05, + 0x807b817b, 0x8e7b827b, 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, + 0x807bff7b, 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -460,224 +568,119 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffef, 0xbf9c0000, + 0xbf8200c7, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf84001e, 0xbefe00c1, 0xbeff00c1, - 0xb8fb4306, 0x867bc17b, - 0xbf840063, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf84005f, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, + 0xb8ef4306, 0x866fc16f, + 0xbf840019, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, - 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, 0xbefe00c1, 0xbeff00c1, - 0xb8fb2a05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xbf8200c7, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf84001e, 0xbefe00c1, - 0xbeff00c1, 0xb8ef4306, - 0x866fc16f, 0xbf840019, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82a05, + 0xbef600ff, 0x01000000, + 0xb8ef2a05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, + 0xbf11087c, 0xe0524000, + 0x781d0000, 0xe0524100, + 0x781d0100, 0xe0524200, + 0x781d0200, 0xe0524300, + 0x781d0300, 0xbf8c0f70, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0x807c847c, 0x8078ff78, + 0x00000400, 0xbf0a6f7c, + 0xbf85ffee, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82a05, 0x80788178, 0x8e788a78, 0xb8ee1605, 0x806e816e, 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2a05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, 0xb8f82a05, 0x80788178, 0x8e788a78, 0xb8ee1605, 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, + 0x80786e78, 0xbef60084, 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2a05, - 0x806e816e, 0x8e6e8a6e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b77, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2a05, 0x806e816e, + 0x8e6e8a6e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b77, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf810000, 0x00000000, }; static const uint32_t cwsr_trap_nv1x_hex[] = { @@ -1305,219 +1308,265 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { }; static const uint32_t cwsr_trap_arcturus_hex[] = { - 0xbf820001, 0xbf8202da, + 0xbf820001, 0xbf8202df, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001e, + 0x00ff0000, 0xbf850023, 0x866eff7b, 0x00000400, - 0xbf85005b, 0xbf8e0010, + 0xbf850060, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03c00900, - 0xbf850015, 0x866eff7b, - 0x000071ff, 0xbf840008, - 0x866fff7b, 0x00007080, - 0xbf840001, 0xbeee1a87, - 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf85000a, - 0x866eff6d, 0x00ff0000, - 0xbf850007, 0xb8eef801, - 0x866eff6e, 0x00000800, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf850040, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xb8faf812, - 0xb8fbf813, 0x8efa887a, - 0xbf0d8f7b, 0xbf840002, - 0x877bff7b, 0xffff0000, - 0xc0031c3d, 0x00000010, - 0xc0071bbd, 0x00000000, - 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x8671ff6d, - 0x01000000, 0xbf840004, - 0x92f1ff70, 0x00010001, - 0xbf840016, 0xbf820005, - 0x86708170, 0x8e709770, - 0x8977ff77, 0x00800000, - 0x87777077, 0x86ee6e6e, - 0xbf840001, 0xbe801d6e, - 0x866eff6d, 0x01ff0000, - 0xbf850005, 0x8778ff78, - 0x00002000, 0x80ec886c, - 0x82ed806d, 0xbf820005, - 0x866eff6d, 0x01000000, - 0xbf850002, 0x806c846c, - 0x826d806d, 0x866dff6d, - 0x0000ffff, 0x8f7a8b77, + 0xbf85001a, 0x866eff6d, + 0x01ff0000, 0xbf06ff6e, + 0x01040000, 0xbf850015, + 0x866eff7b, 0x000071ff, + 0xbf840008, 0x866fff7b, + 0x00007080, 0xbf840001, + 0xbeee1a87, 0xb8eff801, + 0x8e6e8c6e, 0x866e6f6e, + 0xbf85000a, 0x866eff6d, + 0x00ff0000, 0xbf850007, + 0xb8eef801, 0x866eff6e, + 0x00000800, 0xbf850003, + 0x866eff7b, 0x00000400, + 0xbf850040, 0xb8faf807, 0x867aff7a, 0x001f8000, - 0xb97af807, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e8378, - 0xb96ee0c2, 0xbf800002, - 0xb9780002, 0xbe801f6c, + 0x8e7a8b7a, 0x8977ff77, + 0xfc000000, 0x87777a77, + 0xba7ff807, 0x00000000, + 0xb8faf812, 0xb8fbf813, + 0x8efa887a, 0xbf0d8f7b, + 0xbf840002, 0x877bff7b, + 0xffff0000, 0xc0031c3d, + 0x00000010, 0xc0071bbd, + 0x00000000, 0xc0071ebd, + 0x00000008, 0xbf8cc07f, + 0x8671ff6d, 0x01000000, + 0xbf840004, 0x92f1ff70, + 0x00010001, 0xbf840016, + 0xbf820005, 0x86708170, + 0x8e709770, 0x8977ff77, + 0x00800000, 0x87777077, + 0x86ee6e6e, 0xbf840001, + 0xbe801d6e, 0x866eff6d, + 0x01ff0000, 0xbf850005, + 0x8778ff78, 0x00002000, + 0x80ec886c, 0x82ed806d, + 0xbf820005, 0x866eff6d, + 0x01000000, 0xbf850002, + 0x806c846c, 0x826d806d, 0x866dff6d, 0x0000ffff, - 0xbefa0080, 0xb97a0283, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbf900004, 0x877a8478, - 0xb97af802, 0xbf8e0002, - 0xbf88fffe, 0xb8fa2a05, - 0x807a817a, 0x8e7a8a7a, - 0x8e7a817a, 0xb8fb1605, - 0x807b817b, 0x8e7b867b, - 0x807a7b7a, 0x807a7e7a, - 0x827b807f, 0x867bff7b, - 0x0000ffff, 0xc04b1c3d, - 0x00000050, 0xbf8cc07f, - 0xc04b1d3d, 0x00000060, - 0xbf8cc07f, 0xc0431e7d, - 0x00000074, 0xbf8cc07f, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0xbef1007c, 0xbef00080, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, + 0x8f7a8b77, 0x867aff7a, + 0x001f8000, 0xb97af807, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e8378, 0xb96ee0c2, + 0xbf800002, 0xb9780002, + 0xbe801f6c, 0x866dff6d, + 0x0000ffff, 0xbefa0080, + 0xb97a0283, 0xb8faf807, + 0x867aff7a, 0x001f8000, + 0x8e7a8b7a, 0x8977ff77, + 0xfc000000, 0x87777a77, + 0xba7ff807, 0x00000000, + 0xbeee007e, 0xbeef007f, + 0xbefe0180, 0xbf900004, + 0x877a8478, 0xb97af802, + 0xbf8e0002, 0xbf88fffe, + 0xb8fa2a05, 0x807a817a, + 0x8e7a8a7a, 0x8e7a817a, + 0xb8fb1605, 0x807b817b, + 0x8e7b867b, 0x807a7b7a, + 0x807a7e7a, 0x827b807f, + 0x867bff7b, 0x0000ffff, + 0xc04b1c3d, 0x00000050, + 0xbf8cc07f, 0xc04b1d3d, + 0x00000060, 0xbf8cc07f, + 0xc0431e7d, 0x00000074, + 0xbf8cc07f, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0xbef1007c, + 0xbef00080, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0xbef60084, + 0xbef600ff, 0x01000000, 0xbefe007c, 0xbefc0070, - 0xc0611b3a, 0x0000007c, + 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b7a, + 0xbefc0070, 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bba, 0x0000007c, + 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bfa, + 0xbefc0070, 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611e3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8fbf803, - 0xbefe007c, 0xbefc0070, - 0xc0611efa, 0x0000007c, + 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a3a, + 0xbefc0070, 0xc0611e3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8fbf803, 0xbefe007c, + 0xbefc0070, 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8f1f801, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, + 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8f1f801, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf85004d, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, + 0x80048104, 0xd2890002, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb4306, 0x867bc17b, + 0xbf840064, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf840060, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840064, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf840060, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2a05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, + 0x807bff7b, 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -1536,471 +1585,368 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb2a05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffef, 0xbf9c0000, + 0xbefc0080, 0xbf11017c, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf850059, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xbe840080, + 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, + 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xbefc0080, - 0xbf11017c, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850059, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffa9, 0xbf9c0000, - 0xbf820016, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffeb, - 0xbf9c0000, 0xbf8200e3, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf84001f, 0xbefe00c1, - 0xbeff00c1, 0xb8ef4306, - 0x866fc16f, 0xbf84001a, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0x807cff7c, 0x00000200, - 0x8078ff78, 0x00000200, - 0xbf0a6f7c, 0xbf85fff6, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffa9, + 0xbf9c0000, 0xbf820016, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffeb, 0xbf9c0000, + 0xbf8200e3, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf84001f, 0xbefe00c1, 0xbeff00c1, + 0xb8ef4306, 0x866fc16f, + 0xbf84001a, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xb8ef2a05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, - 0xbf11087c, 0xe0524000, - 0x781d0000, 0xe0524100, - 0x781d0100, 0xe0524200, - 0x781d0200, 0xe0524300, - 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0x807c847c, 0x8078ff78, - 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xbefc0080, - 0xbf11087c, 0xe0524000, - 0x781d0000, 0xe0524100, - 0x781d0100, 0xe0524200, - 0x781d0200, 0xe0524300, - 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, - 0x807c847c, 0x8078ff78, - 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0x807cff7c, + 0x00000200, 0x8078ff78, + 0x00000200, 0xbf0a6f7c, + 0xbf85fff6, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2a05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2a05, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b77, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2a05, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b77, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf810000, 0x00000000, }; static const uint32_t cwsr_trap_aldebaran_hex[] = { - 0xbf820001, 0xbf8202e5, + 0xbf820001, 0xbf8202ea, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001e, + 0x00ff0000, 0xbf850023, 0x866eff7b, 0x00000400, - 0xbf85005b, 0xbf8e0010, + 0xbf850060, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03c00900, - 0xbf850015, 0x866eff7b, - 0x000071ff, 0xbf840008, - 0x866fff7b, 0x00007080, - 0xbf840001, 0xbeee1a87, - 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf85000a, - 0x866eff6d, 0x00ff0000, - 0xbf850007, 0xb8eef801, - 0x866eff6e, 0x00000800, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf850040, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xb8faf812, - 0xb8fbf813, 0x8efa887a, - 0xbf0d8f7b, 0xbf840002, - 0x877bff7b, 0xffff0000, - 0xc0031c3d, 0x00000010, - 0xc0071bbd, 0x00000000, - 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x8671ff6d, - 0x01000000, 0xbf840004, - 0x92f1ff70, 0x00010001, - 0xbf840016, 0xbf820005, - 0x86708170, 0x8e709770, - 0x8977ff77, 0x00800000, - 0x87777077, 0x86ee6e6e, - 0xbf840001, 0xbe801d6e, - 0x866eff6d, 0x01ff0000, - 0xbf850005, 0x8778ff78, - 0x00002000, 0x80ec886c, - 0x82ed806d, 0xbf820005, - 0x866eff6d, 0x01000000, - 0xbf850002, 0x806c846c, - 0x826d806d, 0x866dff6d, - 0x0000ffff, 0x8f7a8b77, + 0xbf85001a, 0x866eff6d, + 0x01ff0000, 0xbf06ff6e, + 0x01040000, 0xbf850015, + 0x866eff7b, 0x000071ff, + 0xbf840008, 0x866fff7b, + 0x00007080, 0xbf840001, + 0xbeee1a87, 0xb8eff801, + 0x8e6e8c6e, 0x866e6f6e, + 0xbf85000a, 0x866eff6d, + 0x00ff0000, 0xbf850007, + 0xb8eef801, 0x866eff6e, + 0x00000800, 0xbf850003, + 0x866eff7b, 0x00000400, + 0xbf850040, 0xb8faf807, 0x867aff7a, 0x001f8000, - 0xb97af807, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e8378, - 0xb96ee0c2, 0xbf800002, - 0xb9780002, 0xbe801f6c, + 0x8e7a8b7a, 0x8977ff77, + 0xfc000000, 0x87777a77, + 0xba7ff807, 0x00000000, + 0xb8faf812, 0xb8fbf813, + 0x8efa887a, 0xbf0d8f7b, + 0xbf840002, 0x877bff7b, + 0xffff0000, 0xc0031c3d, + 0x00000010, 0xc0071bbd, + 0x00000000, 0xc0071ebd, + 0x00000008, 0xbf8cc07f, + 0x8671ff6d, 0x01000000, + 0xbf840004, 0x92f1ff70, + 0x00010001, 0xbf840016, + 0xbf820005, 0x86708170, + 0x8e709770, 0x8977ff77, + 0x00800000, 0x87777077, + 0x86ee6e6e, 0xbf840001, + 0xbe801d6e, 0x866eff6d, + 0x01ff0000, 0xbf850005, + 0x8778ff78, 0x00002000, + 0x80ec886c, 0x82ed806d, + 0xbf820005, 0x866eff6d, + 0x01000000, 0xbf850002, + 0x806c846c, 0x826d806d, 0x866dff6d, 0x0000ffff, - 0xbefa0080, 0xb97a0283, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbf900004, 0x877a8478, - 0xb97af802, 0xbf8e0002, - 0xbf88fffe, 0xb8fa2985, - 0x807a817a, 0x8e7a8a7a, - 0x8e7a817a, 0xb8fb1605, - 0x807b817b, 0x8e7b867b, - 0x807a7b7a, 0x807a7e7a, - 0x827b807f, 0x867bff7b, - 0x0000ffff, 0xc04b1c3d, - 0x00000050, 0xbf8cc07f, - 0xc04b1d3d, 0x00000060, - 0xbf8cc07f, 0xc0431e7d, - 0x00000074, 0xbf8cc07f, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0xbef1007c, 0xbef00080, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, + 0x8f7a8b77, 0x867aff7a, + 0x001f8000, 0xb97af807, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e8378, 0xb96ee0c2, + 0xbf800002, 0xb9780002, + 0xbe801f6c, 0x866dff6d, + 0x0000ffff, 0xbefa0080, + 0xb97a0283, 0xb8faf807, + 0x867aff7a, 0x001f8000, + 0x8e7a8b7a, 0x8977ff77, + 0xfc000000, 0x87777a77, + 0xba7ff807, 0x00000000, + 0xbeee007e, 0xbeef007f, + 0xbefe0180, 0xbf900004, + 0x877a8478, 0xb97af802, + 0xbf8e0002, 0xbf88fffe, + 0xb8fa2985, 0x807a817a, + 0x8e7a8a7a, 0x8e7a817a, + 0xb8fb1605, 0x807b817b, + 0x8e7b867b, 0x807a7b7a, + 0x807a7e7a, 0x827b807f, + 0x867bff7b, 0x0000ffff, + 0xc04b1c3d, 0x00000050, + 0xbf8cc07f, 0xc04b1d3d, + 0x00000060, 0xbf8cc07f, + 0xc0431e7d, 0x00000074, + 0xbf8cc07f, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0xbef1007c, + 0xbef00080, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0xbef60084, + 0xbef600ff, 0x01000000, 0xbefe007c, 0xbefc0070, - 0xc0611b3a, 0x0000007c, + 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b7a, + 0xbefc0070, 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bba, 0x0000007c, + 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bfa, + 0xbefc0070, 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611e3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8fbf803, - 0xbefe007c, 0xbefc0070, - 0xc0611efa, 0x0000007c, + 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a3a, + 0xbefc0070, 0xc0611e3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8fbf803, 0xbefe007c, + 0xbefc0070, 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8f1f801, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, + 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840064, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf840060, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8f1f801, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -2019,31 +1965,50 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000902, + 0x80048104, 0xd2890001, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, + 0x80048104, 0xd2890003, + 0x00000902, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, 0xbefe00c1, 0xbeff00c1, - 0xb8fb2b05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, + 0xb8fb4306, 0x867bc17b, + 0xbf840064, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf840060, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -2063,51 +2028,31 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xb8fb2985, - 0x807b817b, 0x8e7b837b, - 0xb8fa2b05, 0x807a817a, - 0x8e7a827a, 0x80fb7a7b, - 0x867b7b7b, 0xbf84007a, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2b05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, 0x807bff7b, 0x00001000, - 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850059, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -2146,139 +2091,203 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffa9, - 0xbf9c0000, 0xbf820016, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffeb, 0xbf9c0000, - 0xbf8200ee, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf84001f, + 0xbf85ffef, 0xbf9c0000, + 0xb8fb2985, 0x807b817b, + 0x8e7b837b, 0xb8fa2b05, + 0x807a817a, 0x8e7a827a, + 0x80fb7a7b, 0x867b7b7b, + 0xbf84007a, 0x807bff7b, + 0x00001000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf8200ee, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf84001f, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf84001a, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, 0xbefe00c1, 0xbeff00c1, - 0xb8ef4306, 0x866fc16f, - 0xbf84001a, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2b05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xb8ef2985, 0x806f816f, - 0x8e6f836f, 0xb8f92b05, - 0x80798179, 0x8e798279, - 0x80ef796f, 0x866f6f6f, - 0xbf84001a, 0x806fff6f, - 0x00008000, 0xbefc0080, + 0xb8ef2b05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbf85ffee, 0xb8ef2985, + 0x806f816f, 0x8e6f836f, + 0xb8f92b05, 0x80798179, + 0x8e798279, 0x80ef796f, + 0x866f6f6f, 0xbf84001a, + 0x806fff6f, 0x00008000, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2985, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b77, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2985, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b77, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf810000, 0x00000000, }; static const uint32_t cwsr_trap_gfx10_hex[] = { diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index ada7df7e6f21b..972bacf767ed3 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -261,6 +261,11 @@ L_NOT_HALTED: SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK s_cbranch_scc1 L_FETCH_2ND_TRAP + // Check TTMP1 bits 24 (HT) and 23:16(trapID): HT == 1 & trapID == 4 + s_and_b32 ttmp2, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) + s_cmp_eq_u32 ttmp2, 0x1040000 + s_cbranch_scc1 L_FETCH_2ND_TRAP + // Check for maskable exceptions in trapsts.excp and trapsts.excp_hi. // Maskable exceptions only cause the wave to enter the trap handler if // their respective bit in mode.excp_en is set. From fd6b65eae3b9355a7930c63c4da9cf6c3ed5a65e Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 27 Sep 2023 10:56:13 -0400 Subject: [PATCH 1209/2653] drm/amdgpu: add sq host trap status check Before fire a new host trap, check the host trap status. -v6: add multiple instances support Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 36 +++++++++++++++++++ .../amd/include/asic_reg/gc/gc_9_0_offset.h | 2 ++ .../amd/include/asic_reg/gc/gc_9_0_sh_mask.h | 5 +++ 3 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index 7e059eb963d54..d45923bfde87f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1229,6 +1229,36 @@ uint32_t kgd_gfx_v9_hqd_sdma_get_doorbell(struct amdgpu_device *adev, return 0; } +static uint32_t kgd_aldebaran_get_hosttrap_status(struct amdgpu_device *adev, + uint32_t inst) +{ + uint32_t sq_hosttrap_status = 0x0; + int i, j; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { + amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, inst); + sq_hosttrap_status = RREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_HOSTTRAP_STATUS); + + if (sq_hosttrap_status & SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK) { + WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_HOSTTRAP_STATUS, + SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK); + sq_hosttrap_status = 0x0; + continue; + } + if (sq_hosttrap_status) + goto out; + } + } + +out: + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + mutex_unlock(&adev->grbm_idx_mutex); + + return sq_hosttrap_status; +} + uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, uint32_t vmid, uint32_t max_wave_slot, @@ -1240,6 +1270,12 @@ uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, { if (method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { uint32_t value = 0; + uint32_t sq_hosttrap_status = 0x0; + + sq_hosttrap_status = kgd_aldebaran_get_hosttrap_status(adev, inst); + /* skip when last host trap request is still pending to complete */ + if (sq_hosttrap_status) + return 0; value = REG_SET_FIELD(value, SQ_CMD, CMD, SQ_IND_CMD_CMD_TRAP); value = REG_SET_FIELD(value, SQ_CMD, MODE, SQ_IND_CMD_MODE_SINGLE); diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h index 12d451e5475b7..5b17d90664524 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h @@ -462,6 +462,8 @@ #define mmSQ_IND_DATA_BASE_IDX 0 #define mmSQ_CMD 0x037b #define mmSQ_CMD_BASE_IDX 0 +#define mmSQ_HOSTTRAP_STATUS 0x0376 +#define mmSQ_HOSTTRAP_STATUS_BASE_IDX 0 #define mmSQ_TIME_HI 0x037c #define mmSQ_TIME_HI_BASE_IDX 0 #define mmSQ_TIME_LO 0x037d diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h index 2dfa0e5b1aa3e..3e0210c2bf369 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h @@ -2616,6 +2616,11 @@ //SQ_CMD_TIMESTAMP #define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 #define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL +//SQ_HOSTTRAP_STATUS +#define SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT__SHIFT 0x0 +#define SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE__SHIFT 0x8 +#define SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT_MASK 0x000000FFL +#define SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK 0x00000100L //SQ_IND_INDEX #define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 #define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 From 433d04bf14edfe40b5d6a553ce7df93cb0cd076f Mon Sep 17 00:00:00 2001 From: James Zhu Date: Sat, 12 Aug 2023 11:58:46 -0400 Subject: [PATCH 1210/2653] drm/amdkfd: trigger pc sampling trap for arcturus Implement trigger pc sampling trap for arcturus. -v6: add multiple instances support Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c index 1105a09e55dc1..01b0a33a17042 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c @@ -389,6 +389,18 @@ static uint32_t kgd_arcturus_disable_debug_trap(struct amdgpu_device *adev, return 0; } + +static uint32_t kgd_arcturus_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) +{ + return kgd_gfx_v9_trigger_pc_sample_trap(adev, vmid, 10, 4, + target_simd, target_wave_slot, method, inst); +} + const struct kfd2kgd_calls arcturus_kfd2kgd = { .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, @@ -420,5 +432,6 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = { .program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings, .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, .hqd_reset = kgd_gfx_v9_hqd_reset, - .hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell + .hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell, + .trigger_pc_sample_trap = kgd_arcturus_trigger_pc_sample_trap }; From 2ef0cae736bf463917ecbada050c35c0f38cecf5 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 14:15:57 -0400 Subject: [PATCH 1211/2653] drm/amdkfd: trigger pc sampling trap for aldebaran Implement trigger pc sampling trap for aldebaran. -v6: add multiple instances support Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c index c55bc29a2c77c..af2f201eb32f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c @@ -164,6 +164,17 @@ static uint32_t kgd_gfx_aldebaran_set_address_watch( return watch_address_cntl; } +static uint32_t kgd_aldebaran_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) +{ + return kgd_gfx_v9_trigger_pc_sample_trap(adev, vmid, 8, 4, + target_simd, target_wave_slot, method, inst); +} + const struct kfd2kgd_calls aldebaran_kfd2kgd = { .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, @@ -194,5 +205,6 @@ const struct kfd2kgd_calls aldebaran_kfd2kgd = { .program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings, .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, .hqd_reset = kgd_gfx_v9_hqd_reset, - .hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell + .hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell, + .trigger_pc_sample_trap = kgd_aldebaran_trigger_pc_sample_trap }; From 86eaedd370c54cc48a1367d020db4083d05b8dd3 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 27 Jul 2023 20:20:20 -0400 Subject: [PATCH 1212/2653] drm/amdkfd: use bit operation set debug trap 1st level TMA's 2nd byte which used for trap type setting, to use bit operation to change selected bit only. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 333205b2cbeeb..5228303759296 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1504,13 +1504,23 @@ bool kfd_process_xnack_mode(struct kfd_process *p, bool supported) return true; } +/* bit offset in 1st-level TMA's 2nd byte which used for KFD_TRAP_TYPE_BIT */ +enum KFD_TRAP_TYPE_BIT { + KFD_TRAP_TYPE_DEBUG = 0, /* bit 0 for debug trap */ + KFD_TRAP_TYPE_HOST, + KFD_TRAP_TYPE_STOCHASTIC, +}; + void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, bool enabled) { if (qpd->cwsr_kaddr) { - uint64_t *tma = - (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET); - tma[2] = enabled; + volatile unsigned long *tma = + (volatile unsigned long *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET); + if (enabled) + set_bit(KFD_TRAP_TYPE_DEBUG, &tma[2]); + else + clear_bit(KFD_TRAP_TYPE_DEBUG, &tma[2]); } } From 1face14e45f0ef0e7eff6428400f7b0b10e2f324 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 14:58:57 -0400 Subject: [PATCH 1213/2653] drm/amdkfd: add setting trap pc sampling flag Add setting trap pc sampling flag. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 ++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 13 +++++++++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index a4d8215942dcd..4f3f2341122e9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1311,6 +1311,8 @@ void kfd_process_set_trap_handler(struct qcm_process_device *qpd, uint64_t tma_addr); void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, bool enabled); +void kfd_process_set_trap_pc_sampling_flag(struct qcm_process_device *qpd, + enum kfd_ioctl_pc_sample_method method, bool enabled); /* CWSR initialization */ int kfd_process_init_cwsr_apu(struct kfd_process *process, struct file *filep); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 5228303759296..de01e80a0feca 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1524,6 +1524,19 @@ void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, } } +void kfd_process_set_trap_pc_sampling_flag(struct qcm_process_device *qpd, + enum kfd_ioctl_pc_sample_method method, bool enabled) +{ + if (qpd->cwsr_kaddr) { + volatile unsigned long *tma = + (volatile unsigned long *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET); + if (enabled) + set_bit(method, &tma[2]); + else + clear_bit(method, &tma[2]); + } +} + /* * On return the kfd_process is fully operational and will be freed when the * mm is released From e70230f9423b930d167e26d0bfa43c8905aeef4d Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 17:10:08 -0400 Subject: [PATCH 1214/2653] drm/amdkfd: enable pc sampling stop Enable pc sampling stop. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 19 ++++++++++++++++--- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 +++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index b46caa52fbe83..8796c6c28172e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -99,10 +99,23 @@ static int kfd_pc_sample_start(struct kfd_process_device *pdd) return -EINVAL; } -static int kfd_pc_sample_stop(struct kfd_process_device *pdd) +static int kfd_pc_sample_stop(struct kfd_process_device *pdd, + struct pc_sampling_entry *pcs_entry) { - return -EINVAL; + bool pc_sampling_stop = false; + + pcs_entry->enabled = false; + mutex_lock(&pdd->dev->pcs_data.mutex); + pdd->dev->pcs_data.hosttrap_entry.base.active_count--; + if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) + pc_sampling_stop = true; + mutex_unlock(&pdd->dev->pcs_data.mutex); + + kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, + pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info.method, false); + + return 0; } static int kfd_pc_sample_create(struct kfd_process_device *pdd, @@ -250,7 +263,7 @@ int kfd_pc_sample(struct kfd_process_device *pdd, if (!pcs_entry->enabled) return -EALREADY; else - return kfd_pc_sample_stop(pdd); + return kfd_pc_sample_stop(pdd, pcs_entry); } return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 4f3f2341122e9..662aa6acc27a0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -288,6 +288,9 @@ struct kfd_dev; struct kfd_dev_pc_sampling_data { uint32_t use_count; /* Num of PC sampling sessions */ + uint32_t active_count; /* Num of active sessions */ + uint32_t target_simd; /* target simd for trap */ + uint32_t target_wave_slot; /* target wave slot for trap */ struct idr pc_sampling_idr; struct kfd_pc_sample_info pc_sample_info; }; From 998c57cb8a94a444e5265b9eed6f107e6193ab89 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Sun, 6 Aug 2023 13:07:28 -0400 Subject: [PATCH 1215/2653] drm/amdkfd: add queue remapping Add queue remapping to ensure that any waves executing the PC sampling part of the trap handler are done before kfd_pc_sample_stop returns, and that no new waves enter that part of the trap handler afterwards. This avoids race conditions that could lead to use-after-free. Unmapping and remapping the queues either waits for the waves to drain, or preempts them with CWSR, which itself executes a trap and waits for previous traps to finish. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 12 ++++++++++++ .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 5 +++++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 3 +++ 3 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index ef7615279ac9b..488c8d81786f3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -3673,6 +3673,17 @@ int debug_refresh_runlist(struct device_queue_manager *dqm) return debug_map_and_unlock(dqm); } +void remap_queue(struct device_queue_manager *dqm, + enum kfd_unmap_queues_filter filter, + uint32_t filter_param, + uint32_t grace_period) +{ + dqm_lock(dqm); + if (!dqm->dev->kfd->shared_resources.enable_mes) + execute_queues_cpsch(dqm, filter, filter_param, grace_period); + dqm_unlock(dqm); +} + bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm, struct qcm_process_device *qpd, int doorbell_off, u32 *queue_format) @@ -3697,6 +3708,7 @@ bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm, dqm_unlock(dqm); return r; } + #if defined(CONFIG_DEBUG_FS) static void seq_reg_dump(struct seq_file *m, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 5a003901d94ba..f276024ff2337 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -330,6 +330,11 @@ bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm, struct qcm_process_device *qpd, int doorbell_off, u32 *queue_format); +void remap_queue(struct device_queue_manager *dqm, + enum kfd_unmap_queues_filter filter, + uint32_t filter_param, + uint32_t grace_period); + static inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd) { return (pdd->lds_base >> 16) & 0xFF; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 8796c6c28172e..5d78fb38620dd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -24,6 +24,7 @@ #include "kfd_priv.h" #include "amdgpu_amdkfd.h" #include "kfd_pc_sampling.h" +#include "kfd_device_queue_manager.h" struct supported_pc_sample_info { uint32_t ip_version; @@ -114,6 +115,8 @@ static int kfd_pc_sample_stop(struct kfd_process_device *pdd, kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info.method, false); + remap_queue(pdd->dev->dqm, + KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); return 0; } From 977e02822d8159edb714d2418d25b5b9810a9498 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 17:03:13 -0400 Subject: [PATCH 1216/2653] drm/amdkfd: enable pc sampling start Enable pc sampling start. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 5d78fb38620dd..e3512c6dec5e2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -95,9 +95,23 @@ static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, return 0; } -static int kfd_pc_sample_start(struct kfd_process_device *pdd) +static int kfd_pc_sample_start(struct kfd_process_device *pdd, + struct pc_sampling_entry *pcs_entry) { - return -EINVAL; + bool pc_sampling_start = false; + + pcs_entry->enabled = true; + mutex_lock(&pdd->dev->pcs_data.mutex); + + kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, + pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info.method, true); + + if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) + pc_sampling_start = true; + pdd->dev->pcs_data.hosttrap_entry.base.active_count++; + mutex_unlock(&pdd->dev->pcs_data.mutex); + + return 0; } static int kfd_pc_sample_stop(struct kfd_process_device *pdd, @@ -260,7 +274,7 @@ int kfd_pc_sample(struct kfd_process_device *pdd, if (pcs_entry->enabled) return -EALREADY; else - return kfd_pc_sample_start(pdd); + return kfd_pc_sample_start(pdd, pcs_entry); case KFD_IOCTL_PCS_OP_STOP: if (!pcs_entry->enabled) From 4766e644c36507f7af3e684d557fa8833f6db547 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 18:42:49 -0400 Subject: [PATCH 1217/2653] drm/amdkfd: add pc sampling thread to trigger trap Add a kthread to trigger pc sampling trap. -v6: add multiple instances support Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 103 ++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + 2 files changed, 103 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index e3512c6dec5e2..fc991dd893b18 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -39,6 +39,92 @@ struct supported_pc_sample_info supported_formats[] = { { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, }; +static int kfd_pc_sample_thread(void *param) +{ + struct amdgpu_device *adev; + struct kfd_node *node = param; + uint32_t timeout = 0; + ktime_t next_trap_time; + bool need_wait; + + mutex_lock(&node->pcs_data.mutex); + if (node->pcs_data.hosttrap_entry.base.active_count && + node->pcs_data.hosttrap_entry.base.pc_sample_info.interval && + node->kfd2kgd->trigger_pc_sample_trap) { + switch (node->pcs_data.hosttrap_entry.base.pc_sample_info.type) { + case KFD_IOCTL_PCS_TYPE_TIME_US: + timeout = (uint32_t)node->pcs_data.hosttrap_entry.base.pc_sample_info.interval; + break; + default: + pr_debug("PC Sampling type %d not supported.", + node->pcs_data.hosttrap_entry.base.pc_sample_info.type); + } + } + mutex_unlock(&node->pcs_data.mutex); + if (!timeout) + return -EINVAL; + + adev = node->adev; + need_wait = false; + allow_signal(SIGKILL); + while (!kthread_should_stop() && + !signal_pending(node->pcs_data.hosttrap_entry.base.pc_sample_thread)) { + if (!need_wait) { + uint32_t inst; + + next_trap_time = ktime_add_us(ktime_get_raw(), timeout); + + for_each_inst(inst, node->xcc_mask) { + node->kfd2kgd->trigger_pc_sample_trap(adev, node->vm_info.last_vmid_kfd, + &node->pcs_data.hosttrap_entry.base.target_simd, + &node->pcs_data.hosttrap_entry.base.target_wave_slot, + node->pcs_data.hosttrap_entry.base.pc_sample_info.method, + inst); + } + pr_debug_ratelimited("triggered a host trap."); + need_wait = true; + } else { + ktime_t wait_time; + s64 wait_ns, wait_us; + + wait_time = ktime_sub(next_trap_time, ktime_get_raw()); + wait_ns = ktime_to_ns(wait_time); + wait_us = ktime_to_us(wait_time); + if (wait_ns >= 10000) + usleep_range(wait_us - 10, wait_us); + else if (wait_ns > 0) + schedule(); + else + need_wait = false; + } + } + + node->pcs_data.hosttrap_entry.base.target_simd = 0; + node->pcs_data.hosttrap_entry.base.target_wave_slot = 0; + node->pcs_data.hosttrap_entry.base.pc_sample_thread = NULL; + + return 0; +} + +static int kfd_pc_sample_thread_start(struct kfd_node *node) +{ + char thread_name[16]; + int ret = 0; + + snprintf(thread_name, 16, "pcs_%d", node->adev->ddev.render->index); + node->pcs_data.hosttrap_entry.base.pc_sample_thread = + kthread_run(kfd_pc_sample_thread, node, thread_name); + + if (IS_ERR(node->pcs_data.hosttrap_entry.base.pc_sample_thread)) { + ret = PTR_ERR(node->pcs_data.hosttrap_entry.base.pc_sample_thread); + node->pcs_data.hosttrap_entry.base.pc_sample_thread = NULL; + pr_debug("Failed to create pc sample thread for %s with ret = %d.", + thread_name, ret); + } + + return ret; +} + static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, struct kfd_ioctl_pc_sample_args __user *user_args) { @@ -99,6 +185,7 @@ static int kfd_pc_sample_start(struct kfd_process_device *pdd, struct pc_sampling_entry *pcs_entry) { bool pc_sampling_start = false; + int ret = 0; pcs_entry->enabled = true; mutex_lock(&pdd->dev->pcs_data.mutex); @@ -108,10 +195,21 @@ static int kfd_pc_sample_start(struct kfd_process_device *pdd, if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) pc_sampling_start = true; + pdd->dev->pcs_data.hosttrap_entry.base.active_count++; mutex_unlock(&pdd->dev->pcs_data.mutex); - return 0; + while (pc_sampling_start) { + /* true means pc_sample_thread stop is in progress */ + if (READ_ONCE(pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_thread)) { + usleep_range(1000, 2000); + } else { + ret = kfd_pc_sample_thread_start(pdd->dev); + break; + } + } + + return ret; } static int kfd_pc_sample_stop(struct kfd_process_device *pdd, @@ -132,6 +230,9 @@ static int kfd_pc_sample_stop(struct kfd_process_device *pdd, remap_queue(pdd->dev->dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); + if (pc_sampling_stop) + kthread_stop(pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_thread); + return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 662aa6acc27a0..26331ad5abed9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -292,6 +292,7 @@ struct kfd_dev_pc_sampling_data { uint32_t target_simd; /* target simd for trap */ uint32_t target_wave_slot; /* target wave slot for trap */ struct idr pc_sampling_idr; + struct task_struct *pc_sample_thread; struct kfd_pc_sample_info pc_sample_info; }; From 37814d3d379f7f2ab31d92c6df5a8e3a162bfc22 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 18:48:43 -0400 Subject: [PATCH 1218/2653] drm/amdkfd: add pc sampling release when process release Add pc sampling release when process release, it will force to stop all activate sessions with this process. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 25 ++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h | 1 + drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 ++++ 3 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index fc991dd893b18..94bd601129c1f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -337,6 +337,31 @@ static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_ return 0; } +void kfd_pc_sample_release(struct kfd_process_device *pdd) +{ + struct pc_sampling_entry *pcs_entry; + struct idr *idp; + uint32_t id; + + /* force to release all PC sampling task for this process */ + idp = &pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr; + do { + pcs_entry = NULL; + mutex_lock(&pdd->dev->pcs_data.mutex); + idr_for_each_entry(idp, pcs_entry, id) { + if (pcs_entry->pdd != pdd) + continue; + break; + } + mutex_unlock(&pdd->dev->pcs_data.mutex); + if (pcs_entry) { + if (pcs_entry->enabled) + kfd_pc_sample_stop(pdd, pcs_entry); + kfd_pc_sample_destroy(pdd, id, pcs_entry); + } + } while (pcs_entry); +} + int kfd_pc_sample(struct kfd_process_device *pdd, struct kfd_ioctl_pc_sample_args __user *args) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h index 4eeded4ea5b6c..6175563ca9bea 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h @@ -30,5 +30,6 @@ int kfd_pc_sample(struct kfd_process_device *pdd, struct kfd_ioctl_pc_sample_args __user *args); +void kfd_pc_sample_release(struct kfd_process_device *pdd); #endif /* KFD_PC_SAMPLING_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index de01e80a0feca..1029f70533aeb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -45,6 +45,7 @@ struct mm_struct; #include "kfd_trace.h" #include "kfd_smi_events.h" #include "kfd_debug.h" +#include "kfd_pc_sampling.h" /* * List of struct kfd_process (field kfd_process). @@ -1048,6 +1049,9 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) pr_debug("Releasing pdd (topology id %d, for pid %d)\n", pdd->dev->id, p->lead_thread->pid); + + kfd_pc_sample_release(pdd); + kfd_process_device_destroy_cwsr_dgpu(pdd); kfd_process_device_destroy_ib_mem(pdd); From bc5f5ac0de2d4194d367a79de9df593e7bd80198 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Thu, 14 Dec 2023 18:45:49 +0000 Subject: [PATCH 1219/2653] drm/amdkfd: Set debug trap bit when enabling PC Sampling We need the SPI_GDBG_PER_VMID_CNTL.TRAP_EN bit to be set during PC Sampling so that the TTMP registers are valid inside the sampling data. runtime_info.ttmp_setup will be cleared when the user application does the AMDKFD_IOC_RUNTIME_ENABLE ioctl without KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK flag on exit. It is also not valid to have the debugger attached to a process while PC sampling is enabled so adding some checks to prevent this. Co-developed-by: James Zhu Signed-off-by: David Yat Sin Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 30 ++++++-------------- drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 26 +++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_debug.h | 3 ++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 13 +++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 ++ 5 files changed, 54 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 2e0b3bb6669f3..548f1d570ce53 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -3046,26 +3046,9 @@ static int runtime_enable(struct kfd_process *p, uint64_t r_debug, p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_ENABLED; p->runtime_info.r_debug = r_debug; - p->runtime_info.ttmp_setup = enable_ttmp_setup; - if (p->runtime_info.ttmp_setup) { - for (i = 0; i < p->n_pdds; i++) { - struct kfd_process_device *pdd = p->pdds[i]; - - if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) { - amdgpu_gfx_off_ctrl(pdd->dev->adev, false); - pdd->dev->kfd2kgd->enable_debug_trap( - pdd->dev->adev, - true, - pdd->dev->vm_info.last_vmid_kfd); - } else if (kfd_dbg_is_per_vmid_supported(pdd->dev)) { - pdd->spi_dbg_override = pdd->dev->kfd2kgd->enable_debug_trap( - pdd->dev->adev, - false, - 0); - } - } - } + if (enable_ttmp_setup) + kfd_dbg_enable_ttmp_setup(p); retry: if (p->debug_trap_enabled) { @@ -3215,10 +3198,10 @@ static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, v goto out; } - /* Check if target is still PTRACED. */ rcu_read_lock(); + /* Check if target is still PTRACED. */ if (target != p && args->op != KFD_IOC_DBG_TRAP_DISABLE - && ptrace_parent(target->lead_thread) != current) { + && ptrace_parent(target->lead_thread) != current) { pr_err("PID %i is not PTRACED and cannot be debugged\n", args->pid); r = -EPERM; } @@ -3228,6 +3211,11 @@ static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, v goto out; mutex_lock(&target->mutex); + if (!!target->pc_sampling_ref) { + pr_debug("Cannot enable debug trap on PID:%d because PC Sampling active\n", args->pid); + r = -EBUSY; + goto unlock_out; + } if (args->op != KFD_IOC_DBG_TRAP_ENABLE && !target->debug_trap_enabled) { pr_err("PID %i not debug enabled for op %i\n", args->pid, args->op); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c index ba99e0f258aee..aa2bc0dbe2888 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c @@ -1150,3 +1150,29 @@ void kfd_dbg_set_enabled_debug_exception_mask(struct kfd_process *target, mutex_unlock(&target->event_mutex); } + +void kfd_dbg_enable_ttmp_setup(struct kfd_process *p) +{ + int i; + + if (p->runtime_info.ttmp_setup) + return; + + p->runtime_info.ttmp_setup = true; + for (i = 0; i < p->n_pdds; i++) { + struct kfd_process_device *pdd = p->pdds[i]; + + if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) { + amdgpu_gfx_off_ctrl(pdd->dev->adev, false); + pdd->dev->kfd2kgd->enable_debug_trap( + pdd->dev->adev, + true, + pdd->dev->vm_info.last_vmid_kfd); + } else if (kfd_dbg_is_per_vmid_supported(pdd->dev)) { + pdd->spi_dbg_override = pdd->dev->kfd2kgd->enable_debug_trap( + pdd->dev->adev, + false, + 0); + } + } +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.h b/drivers/gpu/drm/amd/amdkfd/kfd_debug.h index 27aa1a5b120ff..894753818cba2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.h @@ -92,6 +92,9 @@ int kfd_dbg_trap_device_snapshot(struct kfd_process *target, void kfd_dbg_set_enabled_debug_exception_mask(struct kfd_process *target, uint64_t exception_set_mask); + +void kfd_dbg_enable_ttmp_setup(struct kfd_process *p); + /* * If GFX off is enabled, chips that do not support RLC restore for the debug * registers will disable GFX off temporarily for the entire debug session. diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 94bd601129c1f..fc5333603613b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -24,6 +24,7 @@ #include "kfd_priv.h" #include "amdgpu_amdkfd.h" #include "kfd_pc_sampling.h" +#include "kfd_debug.h" #include "kfd_device_queue_manager.h" struct supported_pc_sample_info { @@ -312,6 +313,14 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, pcs_entry->pdd = pdd; user_args->trace_id = (uint32_t)i; + /* + * Set SPI_GDBG_PER_VMID_CNTL.TRAP_EN so that TTMP registers are valid in the sampling data + * p->runtime_info.ttmp_setup will be cleared when user application calls runtime_disable + * on exit. + */ + kfd_dbg_enable_ttmp_setup(pdd->process); + pdd->process->pc_sampling_ref++; + pr_debug("alloc pcs_entry = %p, trace_id = 0x%x on gpu 0x%x", pcs_entry, i, pdd->dev->id); return 0; @@ -323,6 +332,7 @@ static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_ pr_debug("free pcs_entry = %p, trace_id = 0x%x on gpu 0x%x", pcs_entry, trace_id, pdd->dev->id); + pdd->process->pc_sampling_ref--; mutex_lock(&pdd->dev->pcs_data.mutex); pdd->dev->pcs_data.hosttrap_entry.base.use_count--; idr_remove(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, trace_id); @@ -381,6 +391,9 @@ int kfd_pc_sample(struct kfd_process_device *pdd, if (!pcs_entry || pcs_entry->pdd != pdd) return -EINVAL; + } else if (pdd->process->debug_trap_enabled) { + pr_debug("Cannot have PC Sampling and debug trap simultaneously"); + return -EBUSY; } switch (args->op) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 26331ad5abed9..7bb5f80739f00 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1115,6 +1115,9 @@ struct kfd_process { /* if gpu page fault sent to KFD */ bool gpu_page_fault; + + /* Indicates process' PC Sampling ref cnt*/ + uint32_t pc_sampling_ref; }; #define KFD_PROCESS_TABLE_SIZE 5 /* bits: 32 entries */ From 386abf00263f90078915c77c48d80dc016eeffb1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 4 Mar 2024 16:05:46 +0800 Subject: [PATCH 1220/2653] drm/amdkcl: fake macros DRM_EDID_RANGE_OFFSET_{MIN/MAX}_{VFREQ/HFREQ} It's caused by 5f3e0476a2e2efe4595b4579e74a6028400abbfd "drm/amd/display: handle range offsets in VRR ranges" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_drm_edid.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h index dd472225c0477..b121281e6f45a 100644 --- a/include/kcl/kcl_drm_edid.h +++ b/include/kcl/kcl_drm_edid.h @@ -11,4 +11,11 @@ ((product_id) & 0xffff)) #endif /* drm_edid_encode_panel_id */ +#ifndef DRM_EDID_RANGE_OFFSET_MIN_VFREQ +#define DRM_EDID_RANGE_OFFSET_MIN_VFREQ (1 << 0) /* 1.4 */ +#define DRM_EDID_RANGE_OFFSET_MAX_VFREQ (1 << 1) /* 1.4 */ +#define DRM_EDID_RANGE_OFFSET_MIN_HFREQ (1 << 2) /* 1.4 */ +#define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << 3) /* 1.4 */ +#endif + #endif From 579a895052d7eb7e46405fe2b2dc91f2f7dd50a4 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 4 Mar 2024 10:37:18 +0800 Subject: [PATCH 1221/2653] drm/amdkcl: modify kcl code under macro HAVE_STRUCT_XARRAY some kcl code under macro HAVE_STRUCT_XARRAY could be implemented by spin_lock_irqsave, so improve these code. Signed-off-by: Bob Zhou Reviewed-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11 +++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 +++++++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 -- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 -- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 2 -- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- 7 files changed, 24 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 7d1a16b072b20..73637f7d035ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1359,7 +1359,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return copy_to_user(out, max_ibs, min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; } -#ifdef HAVE_STRUCT_XARRAY + case AMDGPU_INFO_GPUVM_FAULT: { struct amdgpu_fpriv *fpriv = filp->driver_priv; struct amdgpu_vm *vm = &fpriv->vm; @@ -1371,16 +1371,23 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) memset(&gpuvm_fault, 0, sizeof(gpuvm_fault)); +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, flags); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); +#endif gpuvm_fault.addr = vm->fault_info.addr; gpuvm_fault.status = vm->fault_info.status; gpuvm_fault.vmhub = vm->fault_info.vmhub; +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); +#else + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); +#endif return copy_to_user(out, &gpuvm_fault, min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0; } -#endif case AMDGPU_INFO_UQ_FW_AREAS: { struct drm_amdgpu_info_uq_metadata meta_info = {}; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 43729bb68b322..42a96476cbb23 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -3183,7 +3183,7 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m) * * Cache the fault info for later use by userspace in debugging. */ -#ifdef HAVE_STRUCT_XARRAY + void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, unsigned int pasid, uint64_t addr, @@ -3193,9 +3193,14 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, struct amdgpu_vm *vm; unsigned long flags; +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, flags); - vm = xa_load(&adev->vm_manager.pasids, pasid); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); + vm = idr_find(&adev->vm_manager.pasid_idr, pasid); +#endif + /* Don't update the fault cache if status is 0. In the multiple * fault case, subsequent faults will return a 0 status which is * useless for userspace and replaces the useful fault status, so @@ -3228,9 +3233,12 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, WARN_ONCE(1, "Invalid vmhub %u\n", vmhub); } } +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); -} +#else + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); #endif +} /** * amdgpu_vm_is_bo_always_valid - check if the BO is VM always valid diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 504b068b0ef33..081e485a7677b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -667,13 +667,11 @@ static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) mutex_unlock(&vm->eviction_lock); } -#ifdef HAVE_STRUCT_XARRAY void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, unsigned int pasid, uint64_t addr, uint32_t status, unsigned int vmhub); -#endif void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 29da06f985002..68be789c0d493 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -150,10 +150,8 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, status = RREG32(hub->vm_l2_pro_fault_status); WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); -#ifdef HAVE_STRUCT_XARRAY amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); -#endif } if (!printk_ratelimit()) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 5d9f3abbf6099..7db0048d2294b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -120,10 +120,8 @@ static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, status = RREG32(hub->vm_l2_pro_fault_status); WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); -#ifdef HAVE_STRUCT_XARRAY amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); -#endif } if (printk_ratelimit()) { diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 4924568b0c618..3851033f4bd5b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1268,10 +1268,10 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, if (!addr && !status) return 0; -#ifdef HAVE_STRUCT_XARRAY + amdgpu_vm_update_fault_cache(adev, entry->pasid, ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0)); -#endif + if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) gmc_v7_0_set_fault_enable_default(adev, false); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 38f81c6ccc965..7ea209a3da202 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1451,10 +1451,10 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, if (!addr && !status) return 0; -#ifdef HAVE_STRUCT_XARRAY + amdgpu_vm_update_fault_cache(adev, entry->pasid, ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0)); -#endif + if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) gmc_v8_0_set_fault_enable_default(adev, false); From 4c3af1d1ae1376d87dd9ce030743c56e58ec959e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 8 Mar 2024 10:02:45 +0800 Subject: [PATCH 1222/2653] drm/amdkcl: fake macro CAP_PERFMON It's caused by 68592cff2583a71a6af1810a687bc5f86aaafea3 "drm/amdkfd: add pc sampling support" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_capability.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_capability.h b/include/kcl/kcl_capability.h index 2cc984db5ac19..52448ad625f96 100644 --- a/include/kcl/kcl_capability.h +++ b/include/kcl/kcl_capability.h @@ -28,4 +28,8 @@ #define CAP_CHECKPOINT_RESTORE CAP_SYS_ADMIN #endif +#ifndef CAP_PERFMON +#define CAP_PERFMON 38 +#endif + #endif From f579b3a068ef9ec07c5eb7023901d818292910b9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 8 Mar 2024 15:57:48 +0800 Subject: [PATCH 1223/2653] drm/amdkcl: modify struct kfd_class to non-const For some old kernel, the device_create and class_register APIs use the non-const param, so when define the struct kfd_class to const that causes unpredictable issue. v6.3-rc1-21-g2bd5c63978b7 "driver core: device: make device_create*() take a const struct class *" v6.3-rc5-105-g43a7206b0963 "driver core: class: make class_register() take a const *" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 548f1d570ce53..76971e0a8a5f9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -66,7 +66,7 @@ static const struct file_operations kfd_fops = { static int kfd_char_dev_major = -1; struct device *kfd_device; -static const struct class kfd_class = { +static struct class kfd_class = { .name = kfd_dev_name, }; From 775571e8304b7143a5dc142c4019a144cb9b0084 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 11 Mar 2024 13:09:34 +0800 Subject: [PATCH 1224/2653] drm/amdkcl: fake macro DRM_EDID_FEATURE_CONTINUOUS_FREQ It's caused by db3e4f1cbb842e29999fa2dbc5cec4341aade464 "drm/amd/display: Use freesync when `DRM_EDID_FEATURE_CONTINUOUS_FREQ` found" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_drm_edid.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h index b121281e6f45a..0e5b0fab8f8e3 100644 --- a/include/kcl/kcl_drm_edid.h +++ b/include/kcl/kcl_drm_edid.h @@ -18,4 +18,8 @@ #define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << 3) /* 1.4 */ #endif +#ifndef DRM_EDID_FEATURE_CONTINUOUS_FREQ +#define DRM_EDID_FEATURE_CONTINUOUS_FREQ (1 << 0) /* 1.4 */ +#endif + #endif From 53ba15b85ad2140e16fc886a2cca790e4804fb99 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 15 Mar 2024 10:18:09 +0800 Subject: [PATCH 1225/2653] drm/amdkcl: fake macros PCI_ERROR_RESPONSE It's caused by bedb8766222115ae69345fe158eb3cd8027da3f7 "drm/amdgpu: Do a basic health check before reset" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_pci.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 26bb0043066a0..d9ea67cc3dee3 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -97,6 +97,12 @@ 0) #endif +#ifndef PCI_ERROR_RESPONSE +#define PCI_ERROR_RESPONSE (~0ULL) +#define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) +#define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) +#endif + static inline enum pci_bus_speed kcl_pcie_get_speed_cap(struct pci_dev *dev) { return pcie_get_speed_cap(dev); From 8e347f1c7f447e898e984627935c0fbc8652e753 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 22 Mar 2024 16:44:07 +0800 Subject: [PATCH 1226/2653] drm/amdkcl: check dgb_printer whether defined Signed-off-by: Asher Song --- .../gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_print.h | 12 ++++++++++++ 3 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 index 0250d30115d15..38c1584359f8b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 @@ -15,3 +15,21 @@ AC_DEFUN([AC_AMDGPU_DRM_DEBUG_ENABLED], [ ]) ]) ]) + +dnl # +dnl # commit v6.8-rc3-242-g9fd6f61a297e +dnl # drm/print: add drm_dbg_printer() for drm device specific printer +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DBG_PRINTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_dbg_printer(NULL, 0, NULL); + ],[ + AC_DEFINE(HAVE_DRM_DBG_PRINTER, + 1, + [drm_dbg_printer() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d0f32656a5028..80faf81e929ad 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -228,6 +228,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_IS_LATER_OR_SAME AC_AMDGPU_WORKQUEUE AC_AMDGPU_DRM_EXEC_INIT + AC_AMDGPU_DRM_DBG_PRINTER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_print.h b/include/kcl/backport/kcl_drm_print.h index 379308c2563d4..5dc86123ce523 100644 --- a/include/kcl/backport/kcl_drm_print.h +++ b/include/kcl/backport/kcl_drm_print.h @@ -48,4 +48,16 @@ void _kcl_drm_print_bits(struct drm_printer *p, unsigned long value, #define drm_print_bits _kcl_drm_print_bits #endif + +#ifndef HAVE_DRM_DBG_PRINTER +static inline +struct drm_printer _kcl_drm_dbg_printer(struct drm_device *drm, + enum drm_debug_category category, + const char *prefix) +{ + return drm_debug_printer(prefix); +} +#define drm_dbg_printer _kcl_drm_dbg_printer +#endif + #endif From a47e8370a78ace9eb13b0c433ae90727e2d191d9 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 22 Mar 2024 17:09:33 +0800 Subject: [PATCH 1227/2653] drm/amdkcl: check drm_gem_object_is_shared_for_memory_stats whether exits It's caused by v6.8-rc3-288-gba1a58d5b907 drm/amdgpu: add shared fdinfo stats Signed-off-by: Asher Song --- .../gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_gem.h | 8 ++++++++ 3 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 index 36c0a786c849f..8f42e769f8845 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 @@ -24,3 +24,19 @@ AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_PUT], [ ]) ]) ]) + +dnl # +dnl # v6.8-rc3-286-gb31f5eba32ae drm: add drm_gem_object_is_shared_for_memory_stats() helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_gem_object_is_shared_for_memory_stats(NULL); + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS, 1, + [drm_gem_object_is_shared_for_memory_stats() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 80faf81e929ad..5845686a71c97 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -229,6 +229,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_WORKQUEUE AC_AMDGPU_DRM_EXEC_INIT AC_AMDGPU_DRM_DBG_PRINTER + AC_AMDGPU_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_gem.h b/include/kcl/kcl_drm_gem.h index cded9b424aa89..73518a8a22f8b 100644 --- a/include/kcl/kcl_drm_gem.h +++ b/include/kcl/kcl_drm_gem.h @@ -57,4 +57,12 @@ drm_gem_object_get(struct drm_gem_object *obj) } #endif /* HAVE_DRM_GEM_OBJECT_PUT */ +/* copy from include/drm/drm_gem.h */ +#ifndef HAVE_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS +static inline bool drm_gem_object_is_shared_for_memory_stats(struct drm_gem_object *obj) +{ + return (obj->handle_count > 1) || obj->dma_buf; +} +#endif /* HAVE_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS */ + #endif From 038c64b1bd665d61015d3278910a3c79f8ae4ca5 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 22 Mar 2024 18:11:20 +0800 Subject: [PATCH 1228/2653] drm/amdkcl: check enum drm_debug_category whether exits It's caused by v6.8-rc3-249-ge154c4fc7bf2 drm: remove drm_debug_printer in favor of drm_dbg_printer Signed-off-by: Asher Song --- .../gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 | 19 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_print.h | 6 ++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 index 38c1584359f8b..88be95171ea7b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 @@ -33,3 +33,22 @@ AC_DEFUN([AC_AMDGPU_DRM_DBG_PRINTER], [ ]) ]) ]) + +dnl # +dnl # commit v5.4-rc4-974-g876905b8fe59 +dnl # drm/print: convert debug category macros into an enum +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEBUG_CATEGORY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + enum drm_debug_category category; + category = DRM_UT_CORE; + ],[ + AC_DEFINE(HAVE_DRM_DEBUG_CATEGORY, + 1, + [enum drm_debug_category is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5845686a71c97..51dd63a86cae7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -230,6 +230,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_EXEC_INIT AC_AMDGPU_DRM_DBG_PRINTER AC_AMDGPU_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS + AC_AMDGPU_DRM_DEBUG_CATEGORY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 888592871d7ca..4c7dd20cd01f8 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -179,4 +179,10 @@ void drm_print_bits(struct drm_printer *p, unsigned long value, const char * const bits[], unsigned int nbits); #endif +#ifndef HAVE_DRM_DEBUG_CATEGORY +enum drm_debug_category { + KCL_DRM_DEBUG_CATEGORY +}; +#endif + #endif From c5e9ad294fdda61a51e4208ff5bc8a0261b85262 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 25 Mar 2024 15:38:11 +0800 Subject: [PATCH 1229/2653] drm/amdkcl: test drm_info whether exists Signed-off-by: Asher Song --- include/kcl/kcl_drm_print.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 4c7dd20cd01f8..0546bd944b72c 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -185,4 +185,20 @@ enum drm_debug_category { }; #endif +#ifndef drm_info +/* + * struct drm_device based logging + * + * Prefer drm_device based logging over device or prink based logging. + */ + +/* Helper for struct drm_device based logging. */ +#define __drm_printk(drm, level, type, fmt, ...) \ + dev_##level##type((drm) ? (drm)->dev : NULL, "[drm] " fmt, ##__VA_ARGS__) + + +#define drm_info(drm, fmt, ...) \ + __drm_printk((drm), info,, fmt, ##__VA_ARGS__) +#endif + #endif From cfab74819c1e1396272f8a91ab004925e7917e9b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 4 Mar 2024 10:29:57 +0800 Subject: [PATCH 1230/2653] drm/amdkcl: wrap code under macro HAVE_STRUCT_XARRAY It's caused by 0e70df0c1c78cfbaa632efc9e06ad1b62912026d "drm/amdgpu: change vm->task_info handling" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 42a96476cbb23..06f3a177eeea1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2477,9 +2477,15 @@ amdgpu_vm_get_vm_from_pasid(struct amdgpu_device *adev, u32 pasid) struct amdgpu_vm *vm; unsigned long flags; +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, flags); vm = xa_load(&adev->vm_manager.pasids, pasid); xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); + vm = idr_find(&adev->vm_manager.pasid_idr, pasid); + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); +#endif return vm; } From b11f295e1f511c8725d307db7fe12ebcebfee6e1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 7 Mar 2024 10:07:44 +0800 Subject: [PATCH 1231/2653] drm/amdkcl: wrap code under macro HAVE_PCI_DEV_LTR_PATH It's caused by 93b9f1c838ae024313d9d96a910a864d1b87aa49 "drm/amdgpu: Add nbif v6_3_1 ip block support" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c index 9b4025c39e440..95de56d8e44b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c @@ -331,12 +331,14 @@ static void nbif_v6_3_1_program_ltr(struct amdgpu_device *adev) pcie_capability_read_word(adev->pdev, PCI_EXP_DEVCTL2, &devctl2); +#ifdef HAVE_PCI_DEV_LTR_PATH if (adev->pdev->ltr_path == (devctl2 & PCI_EXP_DEVCTL2_LTR_EN)) return; if (adev->pdev->ltr_path) pcie_capability_set_word(adev->pdev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN); else +#endif pcie_capability_clear_word(adev->pdev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN); } #endif From 9c1f94e89f479fe94fe1c9e4d83cf0fe5775e872 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 1 Apr 2024 11:42:00 +0800 Subject: [PATCH 1232/2653] drm/amdkcl: update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 89 +++--------------------- 1 file changed, 11 insertions(+), 78 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 38237fcc9187b..b0771ee3ad969 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -76,9 +76,6 @@ /* whether CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL is defined */ #define HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL 1 -/* whether CHUNK_ID_SYNOBJ_IN_OUT is defined */ -#define HAVE_CHUNK_ID_SYNOBJ_IN_OUT 1 - /* compat_ptr_ioctl() is available */ #define HAVE_COMPAT_PTR_IOCTL 1 @@ -197,9 +194,6 @@ /* drm_connector_for_each_possible_encoder() wants 2 arguments */ #define HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS 1 -/* struct drm_connector_funcs has register members */ -#define HAVE_DRM_CONNECTOR_FUNCS_REGISTER 1 - /* atomic_best_encoder take 2nd arg type of state as struct drm_atomic_state */ #define HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_BEST_ENCODER_ARG_DRM_ATOMIC_STATE 1 @@ -246,6 +240,12 @@ drm_atomic_state arg */ #define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE 1 +/* drm_dbg_printer() is available */ +#define HAVE_DRM_DBG_PRINTER 1 + +/* enum drm_debug_category is available */ +#define HAVE_DRM_DEBUG_CATEGORY 1 + /* drm_debug_enabled() is available */ #define HAVE_DRM_DEBUG_ENABLED 1 @@ -395,9 +395,6 @@ /* struct drm_dp_mst_topology_mgr.base is available */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE 1 -/* drm_dp_mst_topology_mgr_init() wants drm_device arg */ -#define HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_DRM_DEV 1 - /* drm_dp_mst_topology_mgr_init() has max_lane_count and max_link_rate */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT */ @@ -443,15 +440,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_APERTURE_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_ATOMIC_UAPI_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_AUDIO_COMPONENT_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_AUTH_H 1 - /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRM_BACKPORT_H */ @@ -470,9 +458,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_MANAGED_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_PLANE_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 @@ -504,7 +489,7 @@ #define HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE 1 /* drm_exec() has 3 arguments */ -#define HAVE_DRM_EXEC_INIT_3_ARGUMENTS +#define HAVE_DRM_EXEC_INIT_3_ARGUMENTS 1 /* drm_fb_helper_fill_info() is available */ #define HAVE_DRM_FB_HELPER_FILL_INFO 1 @@ -515,12 +500,6 @@ /* drm_fb_helper_init() has 3 args */ /* #undef HAVE_DRM_FB_HELPER_INIT_3ARGS */ -/* whether drm_fb_helper_lastclose() is available */ -#define HAVE_DRM_FB_HELPER_LASTCLOSE 1 - -/* drm_fb_helper_unregister_info() is available */ -#define HAVE_DRM_FB_HELPER_UNREGISTER_INFO 1 - /* drm_firmware_drivers_only() is available */ #define HAVE_DRM_FIRMWARE_DRIVERS_ONLY 1 @@ -533,6 +512,9 @@ /* drm_gem_object_funcs.vmap hsa iosys_map arg */ #define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG 1 +/* drm_gem_object_is_shared_for_memory_stats() is available */ +#define HAVE_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS 1 + /* drm_gem_object_put() is available */ #define HAVE_DRM_GEM_OBJECT_PUT 1 @@ -569,9 +551,6 @@ /* drm_memcpy_from_wc() is availablea and has struct iosys_map* arg */ #define HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG 1 -/* drm_modeset_backoff() has int return */ -/* #undef HAVE_DRM_MODESET_BACKOFF_RETURN_INT */ - /* drm_mode_config->dp_subconnector_property is available */ #define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 @@ -594,20 +573,7 @@ #define HAVE_DRM_NEED_SWIOTLB 1 /* drm_plane_helper_destroy() is available */ -/* #undef HAVE_DRM_PLANE_HELPER_DESTROY */ - -/* drm_plane_mask is available */ -#define HAVE_DRM_PLANE_MASK 1 - -/* drm_plane_create_alpha_property, drm_plane_create_blend_mode_property are - available */ -#define HAVE_DRM_PLANE_PROPERTY_ALPHA_BLEND_MODE 1 - -/* drm_plane_create_color_properties is available */ -#define HAVE_DRM_PLANE_PROPERTY_COLOR_ENCODING_RANGE 1 - -/* drm_plane_create_rotation_property is available */ -#define HAVE_DRM_PLANE_PROPERTY_ROTATION 1 +#define HAVE_DRM_PLANE_HELPER_DESTROY 1 /* drm_prime_pages_to_sg() wants 3 arguments */ #define HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS 1 @@ -633,9 +599,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 -/* drm_vblank->time uses ktime_t type */ -#define HAVE_DRM_VBLANK_USE_KTIME_T 1 - /* struct drm_vma_offset_node has readonly field */ /* #undef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD */ @@ -819,12 +782,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_MMAP_LOCK_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_NOSPEC_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_OVERFLOW_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PCI_P2PDMA_H 1 @@ -834,9 +791,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PROCESSOR_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_RBTREE_TYPES_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_LINUX_STDARG_H 1 @@ -891,9 +845,6 @@ /* mmu_notifier_synchronize() is available */ #define HAVE_MMU_NOTIFIER_SYNCHRONIZE 1 -/* mm_access() is available */ -/* #undef HAVE_MM_ACCESS */ - /* release_pages() wants 2 args */ #define HAVE_MM_RELEASE_PAGES_2ARGS 1 @@ -951,9 +902,6 @@ /* rb_add_cached is available */ #define HAVE_RB_ADD_CACHED 1 -/* struct rb_root_cached is available */ -#define HAVE_RB_ROOT_CACHED 1 - /* whether register_shrinker(x, x) is available */ /* #undef HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS */ @@ -1018,12 +966,6 @@ arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 -/* drm_plane_helper_funcs->prepare_fb() wants const p arg */ -/* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_CONST */ - -/* drm_plane_helper_funcs->prepare_fb() wants p,p arg */ -#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_PP 1 - /* ide->idr_base is available */ #define HAVE_STRUCT_IDE_IDR_BASE 1 @@ -1060,9 +1002,6 @@ /* vga_remove_vgacon() is available */ #define HAVE_VGA_REMOVE_VGACON 1 -/* vga_switcheroo_set_dynamic_switch() exist */ -/* #undef HAVE_VGA_SWITCHEROO_SET_DYNAMIC_SWITCH */ - /* vma_is_initial_{heap, stack} is available */ #define HAVE_VMA_IS_INITIAL_HEAP 1 @@ -1075,12 +1014,6 @@ /* vmf_insert_mixed_prot() is available */ /* #undef HAVE_VMF_INSERT_MIXED_PROT */ -/* vmf_insert_pfn_{pmd,pud}() wants 3 args */ -/* #undef HAVE_VMF_INSERT_PFN_PMD_3ARGS */ - -/* vmf_insert_pfn_{pmd,pud}_prot() is available */ -#define HAVE_VMF_INSERT_PFN_PMD_PROT 1 - /* vmf_insert_pfn_prot() is available */ #define HAVE_VMF_INSERT_PFN_PROT 1 From 7f40c72eeface7c2e686bc889bb82b08a9a3c339 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 18 Mar 2024 15:19:12 +0800 Subject: [PATCH 1233/2653] drm/amdkcl: Fix mst hotplug issue It's caused by bd4e5321fb2237d50a1dcce5602fb3da40a4c506 "drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS" 02e1db74d7ba5b2607421fedce5fc002d4299459 "drm/amd/display: adjust flow for deallocation mst payload" For some old kernel, the asdn code need be keep. So wrap these code under HAVE_DRM_DP_REMOVE_RAYLOAD_PART to fix it. Signed-off-by: Wayne Lin Signed-off-by: Bob Zhou Reviewed-by: Jun Ma --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 +++++ drivers/gpu/drm/amd/display/dc/dc.h | 3 + .../gpu/drm/amd/display/dc/link/link_dpms.c | 83 +++++++++++++++++++ 3 files changed, 105 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e3daa82dd6673..0dc5c4dd049ef 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2028,6 +2028,25 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ adev->dm.dc->debug.ignore_cable_id = true; +#ifndef HAVE_DRM_DP_REMOVE_RAYLOAD_PART + /* TODO: There is a new drm mst change where the freedom of + * vc_next_start_slot update is revoked/moved into drm, instead of in + * driver. This forces us to make sure to get vc_next_start_slot updated + * in drm function each time without considering if mst_state is active + * or not. Otherwise, next time hotplug will give wrong start_slot + * number. We are implementing a temporary solution to even notify drm + * mst deallocation when link is no longer of MST type when uncommitting + * the stream so we will have more time to work on a proper solution. + * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we + * should notify drm to do a complete "reset" of its states and stop + * calling further drm mst functions when link is no longer of an MST + * type. This could happen when we unplug an MST hubs/displays. When + * uncommit stream comes later after unplug, we should just reset + * hardware states only. + */ + adev->dm.dc->debug.temp_mst_deallocation_sequence = true; +#endif //HAVE_DRM_DP_REMOVE_RAYLOAD_PART + if (adev->dm.dc->caps.dp_hdmi21_pcon_support) drm_info(adev_to_drm(adev), "DP-HDMI FRL PCON supported\n"); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5653c1673aece..4c194aa91488c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1094,6 +1094,9 @@ struct dc_debug_options { unsigned int min_prefetch_in_strobe_ns; bool disable_unbounded_requesting; bool dig_fifo_off_in_blank; + #ifndef HAVE_DRM_DP_REMOVE_RAYLOAD_PART + bool temp_mst_deallocation_sequence; + #endif bool override_dispclk_programming; bool otg_crc_db; bool disallow_dispclk_dppclk_ds; diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index d7a165ab588c0..eff53d945f4ea 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -1327,6 +1327,85 @@ static void remove_stream_from_alloc_table( } } +#ifndef HAVE_DRM_DP_REMOVE_RAYLOAD_PART +static enum dc_status deallocate_mst_payload_with_temp_drm_wa( + struct pipe_ctx *pipe_ctx) +{ + struct dc_stream_state *stream = pipe_ctx->stream; + struct dc_link *link = stream->link; + struct dc_dp_mst_stream_allocation_table proposed_table = {0}; + struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); + int i; + bool mst_mode = (link->type == dc_connection_mst_branch); + /* adjust for drm changes*/ + const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); + const struct dc_link_settings empty_link_settings = {0}; + DC_LOGGER_INIT(link->ctx->logger); + + if (link_hwss->ext.set_throttled_vcp_size) + link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); + if (link_hwss->ext.set_hblank_min_symbol_width) + link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, + &empty_link_settings, + avg_time_slots_per_mtp); + + if (dm_helpers_dp_mst_write_payload_allocation_table( + stream->ctx, + stream, + &proposed_table, + false)) + update_mst_stream_alloc_table( + link, + pipe_ctx->stream_res.stream_enc, + pipe_ctx->stream_res.hpo_dp_stream_enc, + &proposed_table); + else + DC_LOG_WARNING("Failed to update" + "MST allocation table for" + "pipe idx:%d\n", + pipe_ctx->pipe_idx); + + DC_LOG_MST("%s" + "stream_count: %d: ", + __func__, + link->mst_stream_alloc_table.stream_count); + + for (i = 0; i < MAX_CONTROLLER_NUM; i++) { + DC_LOG_MST("stream_enc[%d]: %p " + "stream[%d].hpo_dp_stream_enc: %p " + "stream[%d].vcp_id: %d " + "stream[%d].slot_count: %d\n", + i, + (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, + i, + (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, + i, + link->mst_stream_alloc_table.stream_allocations[i].vcp_id, + i, + link->mst_stream_alloc_table.stream_allocations[i].slot_count); + } + + if (link_hwss->ext.update_stream_allocation_table == NULL || + link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { + DC_LOG_DEBUG("Unknown encoding format\n"); + return DC_ERROR_UNEXPECTED; + } + + link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, + &link->mst_stream_alloc_table); + + if (mst_mode) { + dm_helpers_dp_mst_poll_for_allocation_change_trigger( + stream->ctx, + stream); + } + + dm_helpers_dp_mst_update_mst_mgr_for_deallocation(stream->ctx, stream); + + return DC_OK; +} +#endif + static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) { struct dc_stream_state *stream = pipe_ctx->stream; @@ -1339,6 +1418,10 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) const struct dc_link_settings empty_link_settings = {0}; DC_LOGGER_INIT(link->ctx->logger); +#ifndef HAVE_DRM_DP_REMOVE_RAYLOAD_PART + if (link->dc->debug.temp_mst_deallocation_sequence) + return deallocate_mst_payload_with_temp_drm_wa(pipe_ctx); +#endif /* deallocate_mst_payload is called before disable link. When mode or * disable/enable monitor, new stream is created which is not in link * stream[] yet. For this, payload is not allocated yet, so de-alloc From 22127ac9d56c54696615569abecbc3a4fe931337 Mon Sep 17 00:00:00 2001 From: Lancelot SIX Date: Tue, 12 Mar 2024 11:46:34 +0000 Subject: [PATCH 1234/2653] drm/amdkfd: handle masking host traps in cwsr_trap_handler This patch ensures that the 1st level trap handler for gfx9 (cwsr_trap_handler_gfx9.asm) can correctly handle the case where a non-driver-maskable exception and a host trap (driver maskable) are received simultaneously. It also fixes an issue with the current trap handler which uses ttmp4 temporally, overwriting information needed by the debugger. Tested on gfx90a and gfx942. Co-developed-by: Joseph Greathouse Signed-off-by: Lancelot SIX Signed-off-by: Joseph Greathouse Tested-by: Vladimir Indic Reviewed-by: Laurent Morichetti --- .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 906 +++++++++--------- .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 100 +- 2 files changed, 529 insertions(+), 477 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index dba37ed1de505..e0d44552b727c 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -274,47 +274,49 @@ static const uint32_t cwsr_trap_gfx8_hex[] = { static const uint32_t cwsr_trap_gfx9_hex[] = { - 0xbf820001, 0xbf820263, + 0xbf820001, 0xbf820267, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf850023, - 0x866eff7b, 0x00000400, - 0xbf850060, 0xbf8e0010, - 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf85001a, 0x866eff6d, - 0x01ff0000, 0xbf06ff6e, - 0x01040000, 0xbf850015, + 0xbf840008, 0xbf0d986d, + 0xbf850023, 0x866eff7b, + 0x00000400, 0xbf850065, + 0xbf8e0010, 0xb8fbf803, + 0xbf82fffa, 0x866eff7b, + 0x03800900, 0xbf850019, 0x866eff7b, 0x000071ff, 0xbf840008, 0x866fff7b, 0x00007080, 0xbf840001, 0xbeee1a87, 0xb8eff801, 0x8e6e8c6e, 0x866e6f6e, - 0xbf85000a, 0x866eff6d, - 0x00ff0000, 0xbf850007, + 0xbf85000e, 0xbf0d986d, + 0xbf850003, 0x866eff6d, + 0x00ff0000, 0xbf850009, 0xb8eef801, 0x866eff6e, - 0x00000800, 0xbf850003, + 0x00000800, 0xbf850005, + 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850040, 0xb8faf807, - 0x867aff7a, 0x001f8000, - 0x8e7a8b7a, 0x8977ff77, - 0xfc000000, 0x87777a77, - 0xba7ff807, 0x00000000, - 0xb8faf812, 0xb8fbf813, - 0x8efa887a, 0xbf0d8f7b, - 0xbf840002, 0x877bff7b, - 0xffff0000, 0xc0031c3d, - 0x00000010, 0xc0071bbd, - 0x00000000, 0xc0071ebd, - 0x00000008, 0xbf8cc07f, - 0x8671ff6d, 0x01000000, - 0xbf840004, 0x92f1ff70, - 0x00010001, 0xbf840016, - 0xbf820005, 0x86708170, - 0x8e709770, 0x8977ff77, - 0x00800000, 0x87777077, + 0xbf850046, 0xbeed1a9d, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8977ff77, 0xfc000000, + 0x87777a77, 0xba7ff807, + 0x00000000, 0xb8faf812, + 0xb8fbf813, 0x8efa887a, + 0xbf0d8f7b, 0xbf840002, + 0x877bff7b, 0xffff0000, + 0xc0031e7d, 0x00000010, + 0xc0071bbd, 0x00000000, + 0xc0071ebd, 0x00000008, + 0xbf8cc07f, 0x8e799779, + 0x8977ff77, 0x01800000, + 0x87777977, 0xbf0d986d, + 0xbf840009, 0xbf0d9877, + 0xbf850007, 0x896dff6d, + 0x01ff0000, 0xba7f0583, + 0x00000000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840012, + 0xbef71898, 0xbeed189d, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, @@ -680,7 +682,7 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0x8f6e837a, 0xb96ee0c2, 0xbf800002, 0xb97a0002, 0xbf8a0000, 0xbe801f6c, - 0xbf810000, 0x00000000, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_nv1x_hex[] = { @@ -1308,47 +1310,49 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { }; static const uint32_t cwsr_trap_arcturus_hex[] = { - 0xbf820001, 0xbf8202df, + 0xbf820001, 0xbf8202e3, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf850023, - 0x866eff7b, 0x00000400, - 0xbf850060, 0xbf8e0010, - 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf85001a, 0x866eff6d, - 0x01ff0000, 0xbf06ff6e, - 0x01040000, 0xbf850015, + 0xbf840008, 0xbf0d986d, + 0xbf850023, 0x866eff7b, + 0x00000400, 0xbf850065, + 0xbf8e0010, 0xb8fbf803, + 0xbf82fffa, 0x866eff7b, + 0x03800900, 0xbf850019, 0x866eff7b, 0x000071ff, 0xbf840008, 0x866fff7b, 0x00007080, 0xbf840001, 0xbeee1a87, 0xb8eff801, 0x8e6e8c6e, 0x866e6f6e, - 0xbf85000a, 0x866eff6d, - 0x00ff0000, 0xbf850007, + 0xbf85000e, 0xbf0d986d, + 0xbf850003, 0x866eff6d, + 0x00ff0000, 0xbf850009, 0xb8eef801, 0x866eff6e, - 0x00000800, 0xbf850003, + 0x00000800, 0xbf850005, + 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850040, 0xb8faf807, - 0x867aff7a, 0x001f8000, - 0x8e7a8b7a, 0x8977ff77, - 0xfc000000, 0x87777a77, - 0xba7ff807, 0x00000000, - 0xb8faf812, 0xb8fbf813, - 0x8efa887a, 0xbf0d8f7b, - 0xbf840002, 0x877bff7b, - 0xffff0000, 0xc0031c3d, - 0x00000010, 0xc0071bbd, - 0x00000000, 0xc0071ebd, - 0x00000008, 0xbf8cc07f, - 0x8671ff6d, 0x01000000, - 0xbf840004, 0x92f1ff70, - 0x00010001, 0xbf840016, - 0xbf820005, 0x86708170, - 0x8e709770, 0x8977ff77, - 0x00800000, 0x87777077, + 0xbf850046, 0xbeed1a9d, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8977ff77, 0xfc000000, + 0x87777a77, 0xba7ff807, + 0x00000000, 0xb8faf812, + 0xb8fbf813, 0x8efa887a, + 0xbf0d8f7b, 0xbf840002, + 0x877bff7b, 0xffff0000, + 0xc0031e7d, 0x00000010, + 0xc0071bbd, 0x00000000, + 0xc0071ebd, 0x00000008, + 0xbf8cc07f, 0x8e799779, + 0x8977ff77, 0x01800000, + 0x87777977, 0xbf0d986d, + 0xbf840009, 0xbf0d9877, + 0xbf850007, 0x896dff6d, + 0x01ff0000, 0xba7f0583, + 0x00000000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840012, + 0xbef71898, 0xbeed189d, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, @@ -1790,51 +1794,53 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0x8f6e837a, 0xb96ee0c2, 0xbf800002, 0xb97a0002, 0xbf8a0000, 0xbe801f6c, - 0xbf810000, 0x00000000, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_aldebaran_hex[] = { - 0xbf820001, 0xbf8202ea, + 0xbf820001, 0xbf8202ee, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf850023, - 0x866eff7b, 0x00000400, - 0xbf850060, 0xbf8e0010, - 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf85001a, 0x866eff6d, - 0x01ff0000, 0xbf06ff6e, - 0x01040000, 0xbf850015, + 0xbf840008, 0xbf0d986d, + 0xbf850023, 0x866eff7b, + 0x00000400, 0xbf850065, + 0xbf8e0010, 0xb8fbf803, + 0xbf82fffa, 0x866eff7b, + 0x03800900, 0xbf850019, 0x866eff7b, 0x000071ff, 0xbf840008, 0x866fff7b, 0x00007080, 0xbf840001, 0xbeee1a87, 0xb8eff801, 0x8e6e8c6e, 0x866e6f6e, - 0xbf85000a, 0x866eff6d, - 0x00ff0000, 0xbf850007, + 0xbf85000e, 0xbf0d986d, + 0xbf850003, 0x866eff6d, + 0x00ff0000, 0xbf850009, 0xb8eef801, 0x866eff6e, - 0x00000800, 0xbf850003, + 0x00000800, 0xbf850005, + 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850040, 0xb8faf807, - 0x867aff7a, 0x001f8000, - 0x8e7a8b7a, 0x8977ff77, - 0xfc000000, 0x87777a77, - 0xba7ff807, 0x00000000, - 0xb8faf812, 0xb8fbf813, - 0x8efa887a, 0xbf0d8f7b, - 0xbf840002, 0x877bff7b, - 0xffff0000, 0xc0031c3d, - 0x00000010, 0xc0071bbd, - 0x00000000, 0xc0071ebd, - 0x00000008, 0xbf8cc07f, - 0x8671ff6d, 0x01000000, - 0xbf840004, 0x92f1ff70, - 0x00010001, 0xbf840016, - 0xbf820005, 0x86708170, - 0x8e709770, 0x8977ff77, - 0x00800000, 0x87777077, + 0xbf850046, 0xbeed1a9d, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8977ff77, 0xfc000000, + 0x87777a77, 0xba7ff807, + 0x00000000, 0xb8faf812, + 0xb8fbf813, 0x8efa887a, + 0xbf0d8f7b, 0xbf840002, + 0x877bff7b, 0xffff0000, + 0xc0031e7d, 0x00000010, + 0xc0071bbd, 0x00000000, + 0xc0071ebd, 0x00000008, + 0xbf8cc07f, 0x8e799779, + 0x8977ff77, 0x01800000, + 0x87777977, 0xbf0d986d, + 0xbf840009, 0xbf0d9877, + 0xbf850007, 0x896dff6d, + 0x01ff0000, 0xba7f0583, + 0x00000000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840012, + 0xbef71898, 0xbeed189d, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, @@ -2287,7 +2293,7 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x8f6e837a, 0xb96ee0c2, 0xbf800002, 0xb97a0002, 0xbf8a0000, 0xbe801f6c, - 0xbf810000, 0x00000000, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_gfx10_hex[] = { @@ -3169,25 +3175,27 @@ static const uint32_t cwsr_trap_gfx11_hex[] = { }; static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { - 0xbf820001, 0xbf8202db, + 0xbf820001, 0xbf8202ea, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001a, + 0xbf840008, 0xbf0d986d, + 0xbf85001f, 0x866eff7b, + 0x00000400, 0xbf850061, + 0xbf8e0010, 0xb8fbf803, + 0xbf82fffa, 0x866eff7b, + 0x03800900, 0xbf850015, + 0x866eff7b, 0x000071ff, + 0xbf840008, 0x866fff7b, + 0x00007080, 0xbf840001, + 0xbeee1a87, 0xb8eff801, + 0x8e6e8c6e, 0x866e6f6e, + 0xbf85000a, 0xbf0d986d, + 0xbf850003, 0x866eff6d, + 0x00ff0000, 0xbf850005, + 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850051, 0xbf8e0010, - 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf850011, 0x866eff7b, - 0x000071ff, 0xbf840008, - 0x866fff7b, 0x00007080, - 0xbf840001, 0xbeee1a87, - 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf850006, - 0x866eff6d, 0x00ff0000, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, + 0xbf850046, 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8979ff79, 0xfc000000, @@ -3196,187 +3204,130 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0xb8fbf813, 0x8efa887a, 0xbf0d8f7b, 0xbf840002, 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8979ff79, 0x00800000, - 0x87796e79, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, + 0xc0031cfd, 0x00000010, + 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, - 0xbf840001, 0xbe801d6e, - 0x866eff6d, 0x01ff0000, - 0xbf850005, 0x8778ff78, - 0x00002000, 0x80ec886c, - 0x82ed806d, 0xbf820005, - 0x866eff6d, 0x01000000, - 0xbf850002, 0x806c846c, - 0x826d806d, 0x866dff6d, - 0x0000ffff, 0x8f7a8b79, - 0x867aff7a, 0x001f8000, - 0xb97af807, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e8378, - 0xb96ee0c2, 0xbf800002, - 0xb9780002, 0xbe801f6c, + 0xbf8cc07f, 0x8e739773, + 0x8979ff79, 0x01800000, + 0x87797379, 0xbf0d986d, + 0xbf840009, 0xbf0d9879, + 0xbf850007, 0x896dff6d, + 0x01ff0000, 0xba7f0583, + 0x00000000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840012, + 0xbef91898, 0xbeed189d, + 0x86ee6e6e, 0xbf840001, + 0xbe801d6e, 0x866eff6d, + 0x01ff0000, 0xbf850005, + 0x8778ff78, 0x00002000, + 0x80ec886c, 0x82ed806d, + 0xbf820005, 0x866eff6d, + 0x01000000, 0xbf850002, + 0x806c846c, 0x826d806d, 0x866dff6d, 0x0000ffff, - 0xbefa0080, 0xb97a0283, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8979ff79, 0xfc000000, - 0x87797a79, 0xba7ff807, - 0x00000000, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbf900004, 0x877a8478, - 0xb97af802, 0xbf8e0002, - 0xbf88fffe, 0xb8fa2985, - 0x807a817a, 0x8e7a8a7a, - 0x8e7a817a, 0xb8fb1605, - 0x807b817b, 0x8e7b867b, - 0x807a7b7a, 0x807a7e7a, - 0x827b807f, 0x867bff7b, - 0x0000ffff, 0xc04b1c3d, - 0x00000050, 0xbf8cc07f, - 0xc04b1d3d, 0x00000060, - 0xbf8cc07f, 0xc0431e7d, - 0x00000074, 0xbf8cc07f, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0xbef1007c, 0xbef00080, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, + 0x8f7a8b79, 0x867aff7a, + 0x001f8000, 0xb97af807, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e8378, 0xb96ee0c2, + 0xbf800002, 0xb9780002, + 0xbe801f6c, 0x866dff6d, + 0x0000ffff, 0xbefa0080, + 0xb97a0283, 0xb8faf807, + 0x867aff7a, 0x001f8000, + 0x8e7a8b7a, 0x8979ff79, + 0xfc000000, 0x87797a79, + 0xba7ff807, 0x00000000, + 0xbeee007e, 0xbeef007f, + 0xbefe0180, 0xbf900004, + 0x877a8478, 0xb97af802, + 0xbf8e0002, 0xbf88fffe, + 0xb8fa2985, 0x807a817a, + 0x8e7a8a7a, 0x8e7a817a, + 0xb8fb1605, 0x807b817b, + 0x8e7b867b, 0x807a7b7a, + 0x807a7e7a, 0x827b807f, + 0x867bff7b, 0x0000ffff, + 0xc04b1c3d, 0x00000050, + 0xbf8cc07f, 0xc04b1d3d, + 0x00000060, 0xbf8cc07f, + 0xc0431e7d, 0x00000074, + 0xbf8cc07f, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0xbef1007c, + 0xbef00080, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0xbef60084, + 0xbef600ff, 0x01000000, 0xbefe007c, 0xbefc0070, - 0xc0611b3a, 0x0000007c, + 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b7a, + 0xbefc0070, 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bba, 0x0000007c, + 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bfa, + 0xbefc0070, 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611e3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8fbf803, - 0xbefe007c, 0xbefc0070, - 0xc0611efa, 0x0000007c, + 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a3a, + 0xbefc0070, 0xc0611e3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8fbf803, 0xbefe007c, + 0xbefc0070, 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8f1f801, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, + 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840064, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf840060, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8f1f801, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -3395,31 +3346,50 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000902, + 0x80048104, 0xd2890001, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, + 0x80048104, 0xd2890003, + 0x00000902, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, 0xbefe00c1, 0xbeff00c1, - 0xb8fb2b05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, + 0xb8fb4306, 0x867bc17b, + 0xbf840064, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf840060, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -3439,51 +3409,31 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xb8fb2985, - 0x807b817b, 0x8e7b837b, - 0xb8fa2b05, 0x807a817a, - 0x8e7a827a, 0x80fb7a7b, - 0x867b7b7b, 0xbf84007a, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2b05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, 0x807bff7b, 0x00001000, - 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850059, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -3522,139 +3472,203 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffa9, - 0xbf9c0000, 0xbf820016, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffeb, 0xbf9c0000, - 0xbf8200ee, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf84001f, + 0xbf85ffef, 0xbf9c0000, + 0xb8fb2985, 0x807b817b, + 0x8e7b837b, 0xb8fa2b05, + 0x807a817a, 0x8e7a827a, + 0x80fb7a7b, 0x867b7b7b, + 0xbf84007a, 0x807bff7b, + 0x00001000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf8200ee, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf84001f, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf84001a, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, 0xbefe00c1, 0xbeff00c1, - 0xb8ef4306, 0x866fc16f, - 0xbf84001a, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2b05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xb8ef2985, 0x806f816f, - 0x8e6f836f, 0xb8f92b05, - 0x80798179, 0x8e798279, - 0x80ef796f, 0x866f6f6f, - 0xbf84001a, 0x806fff6f, - 0x00008000, 0xbefc0080, + 0xb8ef2b05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbf85ffee, 0xb8ef2985, + 0x806f816f, 0x8e6f836f, + 0xb8f92b05, 0x80798179, + 0x8e798279, 0x80ef796f, + 0x866f6f6f, 0xbf84001a, + 0x806fff6f, 0x00008000, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2985, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b79, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2985, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b79, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_gfx12_hex[] = { diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index 972bacf767ed3..8014b010654cf 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -100,6 +100,7 @@ var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT = 7 var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 var SQ_WAVE_TRAPSTS_HOST_TRAP_MASK = 0x400000 +var SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT = 22 var SQ_WAVE_TRAPSTS_WAVE_BEGIN_MASK = 0x800000 var SQ_WAVE_TRAPSTS_WAVE_END_MASK = 0x1000000 var SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK = 0x2000000 @@ -121,20 +122,25 @@ var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x1F8000 var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800 -var TMA_HOST_TRAP_EN_SHIFT = 1 -var TMA_HOST_TRAP_EN_SIZE = 1 -var TMA_HOST_TRAP_EN_BFE = (TMA_HOST_TRAP_EN_SHIFT | (TMA_HOST_TRAP_EN_SIZE << 16)) - var TTMP_SAVE_RCNT_FIRST_REPLAY_SHIFT = 26 // bits [31:26] unused by SPI debug data var TTMP_SAVE_RCNT_FIRST_REPLAY_MASK = 0xFC000000 var TTMP_DEBUG_TRAP_ENABLED_SHIFT = 23 var TTMP_DEBUG_TRAP_ENABLED_MASK = 0x800000 +var TTMP_HOST_TRAP_ENABLED_SHIFT = 24 +var TTMP_HOST_TRAP_ENABLED_MASK = 0x1000000 +var TTMP_FEATURES_ENABLED_FLAGS_SHIFT = TTMP_DEBUG_TRAP_ENABLED_SHIFT +var TTMP_FEATURES_ENABLED_FLAGS_MASK = TTMP_DEBUG_TRAP_ENABLED_MASK | TTMP_HOST_TRAP_ENABLED_MASK /* Save */ var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE var S_SAVE_PC_HI_TRAP_ID_MASK = 0x00FF0000 var S_SAVE_PC_HI_HT_MASK = 0x01000000 +var S_SAVE_PC_HI_HT_SHIFT = 24 +var S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP = 29 // Only used by the 1st level trap handler to remember if + // we saw a trap type that the driver could not mask, so that + // we can still go to the 2nd-level handler if we driver-mask another + // simultaneous trap. var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 @@ -160,9 +166,15 @@ var s_save_m0 = ttmp5 var s_save_ttmps_lo = s_save_tmp //no conflict var s_save_ttmps_hi = s_save_trapsts //no conflict #if ASIC_FAMILY >= CHIP_GC_9_4_3 -var s_save_ib_sts = ttmp13 +var s_save_ib_sts = ttmp13 // bits 31:26 hold IB_STS, bit 23 to hold debug flag to 2nd-level, + // bit 24 to hold host-trap request + // so bits 22:0 are available for stashing next variable's backup. +var s_tma_flags = ttmp7 // free #else -var s_save_ib_sts = ttmp11 +var s_save_ib_sts = ttmp11 // bits 31:26 hold IB_STS, bit 23 to hold debug flag to 2nd-level, + // bit 24 to hold host-trap request, bit 6 is no-scratch, bits 5-0 are wave-in-wg + // so bits 22:7 are available for stashing next variable's backup +var s_tma_flags = ttmp13 // free #endif /* Restore */ @@ -231,8 +243,8 @@ L_SKIP_RESTORE: L_HALTED: // Host trap may occur while wave is halted. - s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK - s_cbranch_scc1 L_FETCH_2ND_TRAP + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc1 L_FETCH_2ND_TRAP_DRIVER_MASKABLE L_CHECK_SAVE: s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save @@ -250,22 +262,16 @@ L_NOT_HALTED: // Any concurrent SAVECTX will be handled upon re-entry once halted. // Check non-maskable exceptions. memory_violation, illegal_instruction - // and debugger (host trap, wave start/end, trap after instruction) - // exceptions always cause the wave to enter the trap handler. + // and debugger (wave start/end, trap after instruction) exceptions always + // cause the wave to enter the trap handler. s_and_b32 ttmp2, s_save_trapsts, \ SQ_WAVE_TRAPSTS_MEM_VIOL_MASK | \ SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK | \ - SQ_WAVE_TRAPSTS_HOST_TRAP_MASK | \ SQ_WAVE_TRAPSTS_WAVE_BEGIN_MASK | \ SQ_WAVE_TRAPSTS_WAVE_END_MASK | \ SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK s_cbranch_scc1 L_FETCH_2ND_TRAP - // Check TTMP1 bits 24 (HT) and 23:16(trapID): HT == 1 & trapID == 4 - s_and_b32 ttmp2, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) - s_cmp_eq_u32 ttmp2, 0x1040000 - s_cbranch_scc1 L_FETCH_2ND_TRAP - // Check for maskable exceptions in trapsts.excp and trapsts.excp_hi. // Maskable exceptions only cause the wave to enter the trap handler if // their respective bit in mode.excp_en is set. @@ -283,9 +289,15 @@ L_NOT_ADDR_WATCH: s_cbranch_scc1 L_FETCH_2ND_TRAP L_CHECK_TRAP_ID: - // Check trap_id != 0 + // Check trap_id != 0. If this is a host trap (ttmp1.HT == 1), trap_id is + // non 0, but we defer that part of the check until later as this exception + // is driver maskable. We need to make sure that all non-driver-maskable + // exceptions are accounted for before checking for driver-maskable ones. + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc1 L_SKIP_CHECK_TRAP_ID s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK s_cbranch_scc1 L_FETCH_2ND_TRAP +L_SKIP_CHECK_TRAP_ID: if SINGLE_STEP_MISSED_WORKAROUND // Prioritize single step exception over context save. @@ -295,16 +307,22 @@ if SINGLE_STEP_MISSED_WORKAROUND s_cbranch_scc1 L_FETCH_2ND_TRAP end + // Check TTMP1 bits 24 (HT) == 1 + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc1 L_FETCH_2ND_TRAP_DRIVER_MASKABLE + s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK s_cbranch_scc1 L_SAVE L_FETCH_2ND_TRAP: + s_bitset1_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP +L_FETCH_2ND_TRAP_DRIVER_MASKABLE: // Preserve and clear scalar XNACK state before issuing scalar reads. save_and_clear_ib_sts(ttmp14) // Read second-level TBA/TMA from first-level TMA and jump if available. - // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) - // ttmp12 holds SQ_WAVE_STATUS + // ttmp[2:5] and s_tma_flags can be used (others hold SPI-initialized debug + // data) ttmp12 holds SQ_WAVE_STATUS s_getreg_b32 ttmp14, hwreg(HW_REG_SQ_SHADER_TMA_LO) s_getreg_b32 ttmp15, hwreg(HW_REG_SQ_SHADER_TMA_HI) s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 @@ -313,22 +331,42 @@ L_FETCH_2ND_TRAP: s_cbranch_scc0 L_NO_SIGN_EXTEND_TMA s_or_b32 ttmp15, ttmp15, 0xFFFF0000 L_NO_SIGN_EXTEND_TMA: - - s_load_dword ttmp4, [ttmp14, ttmp15], 0x10 glc:1 // enable flags from 1st level TMA + s_load_dword s_tma_flags, [ttmp14, ttmp15], 0x10 glc:1 //Load the debug enables and host trap enabled flags s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 // second-level TBA s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA s_waitcnt lgkmcnt(0) - s_and_b32 ttmp5, s_save_pc_hi, S_SAVE_PC_HI_HT_MASK // host trap request - s_cbranch_scc0 L_NOT_HT - s_bfe_u32 ttmp5, ttmp4, TMA_HOST_TRAP_EN_BFE // extract host_trap_en to ttmp5[0] - s_cbranch_scc0 L_EXIT_TRAP // HT requested, but host traps not enabled - s_branch L_GOTO_2ND_TRAP -L_NOT_HT: - s_and_b32 ttmp4, ttmp4, 0x1 // debug_enable bit left over - s_lshl_b32 ttmp4, ttmp4, TTMP_DEBUG_TRAP_ENABLED_SHIFT - s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_DEBUG_TRAP_ENABLED_MASK - s_or_b32 s_save_ib_sts, s_save_ib_sts, ttmp4 + + // Put debug enable bit and host trap bit into SAVE_IB_STS register, bits + // 23 and 24, respectively. + s_lshl_b32 s_tma_flags, s_tma_flags, TTMP_FEATURES_ENABLED_FLAGS_SHIFT + s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_FEATURES_ENABLED_FLAGS_MASK + s_or_b32 s_save_ib_sts, s_save_ib_sts, s_tma_flags + + // If not a host trap, then driver cannot mask this. Go to the 2nd-level + // trap handler now. + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc0 L_GOTO_2ND_TRAP + + // If driver said host traps are OK, go to the 2nd-level handler now. + s_bitcmp1_b32 s_save_ib_sts, TTMP_HOST_TRAP_ENABLED_SHIFT + s_cbranch_scc1 L_GOTO_2ND_TRAP + + // The driver said host traps are masked, zero out host trap and trapID. + s_andn2_b32 s_save_pc_hi, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) + s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT, 1), 0x0 + + // If there was another trap besides this masked host trap, go handle it in + // 2nd-level handler. + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP + s_bitset0_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP // zero this out + s_cbranch_scc0 L_EXIT_TRAP // Otherwise, exit the trap handler + L_GOTO_2ND_TRAP: + // Reset bits used temporarily by 1st level trap handler so they do not + // leak to the 2nd level trap handler. + s_bitset0_b32 s_save_ib_sts, TTMP_HOST_TRAP_ENABLED_SHIFT + s_bitset0_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP + s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler From fd5c2e37f6fe1b0f2900a4a29d6bbd7d130a81c7 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 20 Mar 2024 12:14:20 +0800 Subject: [PATCH 1235/2653] drm/amdkcl: wrap code under amdkcl_ttm_resvp() It's caused by 0af3db3ac5b50b67ca88dda58de9b6c4637a8b9c "drm/amdgpu: implement TLB flush fence" Signed-off-by: Bob Zhou Reviewed-by: Jun Ma --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 06f3a177eeea1..14ba21e82bc8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1068,7 +1068,7 @@ amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params, amdgpu_vm_tlb_fence_create(params->adev, vm, fence); /* Makes sure no PD/PT is freed before the flush */ - dma_resv_add_fence(vm->root.bo->tbo.base.resv, *fence, + dma_resv_add_fence(amdkcl_ttm_resvp(&vm->root.bo->tbo), *fence, DMA_RESV_USAGE_BOOKKEEP); } } From b96377d113752d93841a0553a5fe0ea7e4b6d7e2 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 29 Mar 2024 11:22:23 +0800 Subject: [PATCH 1236/2653] drm/amdkcl: fake macro function DIV64_U64_ROUND_UP It's caused by 1f0f4865388bd1d19701d1d65552535dd890e566 "drm/amd/display: Add timing pixel encoding for mst mode validation" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_math64.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/kcl/kcl_math64.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 70898b45f1388..5b6a4ed692d8d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -124,4 +124,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_math64.h b/include/kcl/kcl_math64.h new file mode 100644 index 0000000000000..f1d04dee6b8c5 --- /dev/null +++ b/include/kcl/kcl_math64.h @@ -0,0 +1,11 @@ +#ifndef AMDKCL_MATH64_H +#define AMDKCL_MATH64_H + +#include + +#ifndef DIV64_U64_ROUND_UP +#define DIV64_U64_ROUND_UP(ll, d) \ + ({ u64 _tmp = (d); div64_u64((ll) + _tmp - 1, _tmp); }) +#endif + +#endif \ No newline at end of file From 677ffee539b678a8be774a94cd082f11df15b6f5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 29 Mar 2024 11:29:47 +0800 Subject: [PATCH 1237/2653] drm/amdkcl: wrap code out of macro HAVE_DRM_DP_MST_ATOMIC_CHECK It's caused by 1f0f4865388bd1d19701d1d65552535dd890e566 "drm/amd/display: Add timing pixel encoding for mst mode validation" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 9c275e15e5f19..39a3cdbcb6a7d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1002,6 +1002,7 @@ struct dsc_mst_fairness_params { uint32_t bpp_overwrite; struct amdgpu_dm_connector *aconnector; }; +#endif #if defined(CONFIG_DRM_AMD_DC_FP) static uint16_t get_fec_overhead_multiplier(struct dc_link *dc_link) @@ -1026,6 +1027,7 @@ static int kbps_to_peak_pbn(int kbps, uint16_t fec_overhead_multiplier_x1000) return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000)); } +#if defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params, struct dsc_mst_fairness_vars *vars, int count, From 80503912179000b434d391187f7d3ddb753b4424 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 1 Apr 2024 17:53:57 +0800 Subject: [PATCH 1238/2653] drm/amdkcl: fake display legacy macros It's caused by fd4faa19ceb32ed720c818570e5a01d0da456396 "drm/amd/display: Drop legacy code" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- include/kcl/kcl_drm_dp.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/kcl/kcl_drm_dp.h b/include/kcl/kcl_drm_dp.h index 1f277a16b5874..25c848be0df94 100644 --- a/include/kcl/kcl_drm_dp.h +++ b/include/kcl/kcl_drm_dp.h @@ -22,6 +22,8 @@ #ifndef _KCL_DRM_DP_H #define _KCL_DRM_DP_H +#include + #ifndef DP_SINK_VIDEO_FALLBACK_FORMATS #define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 #endif @@ -64,4 +66,14 @@ #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) #endif +#ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 +#endif +#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0 +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230 +#endif +#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256 +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250 +#endif + #endif \ No newline at end of file From 0bfcd571482698a025b24f8c1606a6d348d79b17 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Mon, 1 Apr 2024 13:30:38 +0000 Subject: [PATCH 1239/2653] drm/amdkfd: return success when no buffer provided For PC Sampling, when user application queries current device capabilities and does not provide buffer, this is used to query the size of buffer needed. Return success instead of error. Return the number of valid samples to the user in case the user provided a larger buffer than needed. Signed-off-by: David Yat Sin Acked-by: Felix Kuehling Reviewed-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index fc5333603613b..4572ac447ee4b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -133,6 +133,7 @@ static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, int num_method = 0; int ret; int i; + const uint32_t user_num_sample_info = user_args->num_sample_info; for (i = 0; i < ARRAY_SIZE(supported_formats); i++) if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version) @@ -160,8 +161,15 @@ static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, } mutex_unlock(&pdd->dev->pcs_data.mutex); - if (!user_args->sample_info_ptr || user_args->num_sample_info < num_method) { - user_args->num_sample_info = num_method; + user_args->num_sample_info = num_method; + + if (!user_args->sample_info_ptr || !user_num_sample_info) { + /* + * User application is querying the size of buffer needed. Application will + * allocate required buffer size and send a second query. + */ + return 0; + } else if (user_num_sample_info < num_method) { pr_debug("ASIC requires space for %d kfd_pc_sample_info entries.", num_method); return -ENOSPC; } From 16b88d93506b8de15f070944fef6a9a526453dc9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 22 Apr 2024 10:53:24 +0800 Subject: [PATCH 1240/2653] drm/amdkcl: fake macro AMD_FMT_MOD_TILE_VER_GFX12 and AMD_FMT_MOD_TILE_GFX12_64K_2D It's caused by 2de480179f2a5cbb54e970ba1312f3aac246f33a "drm/amd/display: Add gfx12 modifiers" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- include/kcl/kcl_drm_fourcc.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h index f28a041070a75..9b1a99ec6d52b 100644 --- a/include/kcl/kcl_drm_fourcc.h +++ b/include/kcl/kcl_drm_fourcc.h @@ -100,6 +100,11 @@ #define AMD_FMT_MOD_TILE_VER_GFX11 4 #endif +#ifndef AMD_FMT_MOD_TILE_VER_GFX12 +#define AMD_FMT_MOD_TILE_VER_GFX12 5 +#define AMD_FMT_MOD_TILE_GFX12_64K_2D 3 +#endif + #ifndef AMD_FMT_MOD_TILE_GFX11_256K_R_X #define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31 #endif From 924e38e374c0c641b56c8d9a1c55dc1db964a6d7 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 22 Apr 2024 14:34:46 +0800 Subject: [PATCH 1241/2653] drm/amdkcl: fix __devm_drm_dev_alloc in amdxcp/backport Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- .../gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c | 33 ++----------------- 1 file changed, 3 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c b/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c index 4b2d043f4665a..cc1da02e06e84 100644 --- a/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c +++ b/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c @@ -30,33 +30,7 @@ #include #ifdef AMDKCL_DEVM_DRM_DEV_ALLOC -static void devm_drm_dev_init_release(void *data) -{ - drm_dev_put(data); - -#ifndef HAVE_DRM_DRM_MANAGED_H - if(data){ - struct drm_device *dev = data; - if(!kref_read(&dev->ref)) - kfree(dev->dev_private); - } -#endif -} /* Copied from v5.7-rc1-343-gb0b5849e0cc0 drivers/gpu/drm/drm_drv.c and modified for KCL */ -static int devm_drm_dev_init(struct device *parent, - struct drm_device *dev, - const struct drm_driver *driver) -{ - int ret; - - ret = drm_dev_init(dev, driver, parent); - if (ret) - return ret; - - return devm_add_action_or_reset(parent, - devm_drm_dev_init_release, dev); -} - void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, size_t size, size_t offset) { @@ -69,16 +43,15 @@ void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, return ERR_PTR(-ENOMEM); drm = container + offset; - ret = devm_drm_dev_init(parent, drm, driver); + ret = drm_dev_init(drm, driver, parent); if (ret) { - kfree(container); + drm_dev_put(drm); return ERR_PTR(ret); } #ifdef HAVE_DRM_DRM_MANAGED_H drmm_add_final_kfree(drm, container); -#else - drm->dev_private = container; #endif + drm->dev_private = container; return container; } From e1b57f5057daad894a5e3ba779782c91676207b7 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 22 Apr 2024 14:48:35 +0800 Subject: [PATCH 1242/2653] drm/amdkcl: seperate check for DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED as they're introduced in another commit 45cf0e91df8c("drm: Add DisplayPort colorspace property creation function") Signed-off-by: Flora Cui Reviewed-by: Jun Ma --- include/kcl/kcl_drm_connector.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index c0e2b217ddcc5..c0a969519be7f 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -156,10 +156,14 @@ int _kcl_drm_mode_create_dp_colorspace_property(struct drm_connector *connector, /* Additional Colorimetry extension added as part of CTA 861.G */ #define DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65 11 #define DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER 12 +#endif /* DRM_MODE_COLORIMETRY_DEFAULT */ + +/* v5.3-rc1-676-g45cf0e91df8c */ +#ifndef DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED /* Additional Colorimetry Options added for DP 1.4a VSC Colorimetry Format */ #define DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED 13 #define DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT 14 #define DRM_MODE_COLORIMETRY_BT601_YCC 15 -#endif /* DRM_MODE_COLORIMETRY_DEFAULT */ +#endif #endif /* AMDKCL_DRM_CONNECTOR_H */ From 6f0389ee32959424e1fa5b4c4ae8bff7477b49eb Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 22 Apr 2024 15:07:10 +0800 Subject: [PATCH 1243/2653] drm/amdkcl: rename kcl copy drm_mode_create_colorspace_property to avoid conflict with the drm counterpart Signed-off-by: Flora Cui Reviewed-by: Jun Ma --- drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index 559b2610f2966..7616f113d4afb 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -164,7 +164,7 @@ static const u32 dp_colorspaces = BIT(DRM_MODE_COLORIMETRY_BT2020_CYCC) | BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); -static int drm_mode_create_colorspace_property(struct drm_connector *connector, +static int _kcl_drm_mode_create_colorspace_property(struct drm_connector *connector, u32 supported_colorspaces) { struct drm_device *dev = connector->dev; @@ -232,7 +232,7 @@ int _kcl_drm_mode_create_hdmi_colorspace_property(struct drm_connector *connecto else colorspaces = hdmi_colorspaces; - return drm_mode_create_colorspace_property(connector, colorspaces); + return _kcl_drm_mode_create_colorspace_property(connector, colorspaces); } EXPORT_SYMBOL(_kcl_drm_mode_create_hdmi_colorspace_property); #endif @@ -248,7 +248,7 @@ int _kcl_drm_mode_create_dp_colorspace_property(struct drm_connector *connector, else colorspaces = dp_colorspaces; - return drm_mode_create_colorspace_property(connector, colorspaces); + return _kcl_drm_mode_create_colorspace_property(connector, colorspaces); } EXPORT_SYMBOL(_kcl_drm_mode_create_dp_colorspace_property); #endif \ No newline at end of file From b40dc0ded5ca18f1365421aac9745d703f481fd3 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 26 Apr 2024 13:57:08 +0800 Subject: [PATCH 1244/2653] drm/amdkcl: Support fdinfo interface for older drm version Fake a drm_show_fdinfo for old kernel version which should print gpu memory stat. Signed-off-by: Philip Yang Signed-off-by: Asher Song Reviewed-by: Philip Yang --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/backport/Makefile | 2 +- .../gpu/drm/amd/backport/include}/kcl/kcl_drm_file.h | 4 ++-- drivers/gpu/drm/amd/{amdkcl => backport}/kcl_drm_file.c | 4 +++- 4 files changed, 7 insertions(+), 5 deletions(-) rename {include => drivers/gpu/drm/amd/backport/include}/kcl/kcl_drm_file.h (60%) rename drivers/gpu/drm/amd/{amdkcl => backport}/kcl_drm_file.c (97%) diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 82abb89903b8c..90398c82f9c30 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index f5b5d3b9a2d33..8bc3adedebc57 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: MIT BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ - kcl_drm_gem.o + kcl_drm_gem.o kcl_drm_file.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/include/kcl/kcl_drm_file.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h similarity index 60% rename from include/kcl/kcl_drm_file.h rename to drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h index d23292e37dc25..a067b59578b6c 100644 --- a/include/kcl/kcl_drm_file.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h @@ -1,5 +1,5 @@ -#ifndef __AMDKCL_KCL_DRM_DRV_H__ -#define __AMDKCL_KCL_DRM_DRV_H__ +#ifndef __AMDGPU_BACKPORT_KCL_DRM_DRV_H__ +#define __AMDGPU_BACKPORT_KCL_DRM_DRV_H__ #include #ifndef HAVE_DRM_SHOW_FDINFO diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c b/drivers/gpu/drm/amd/backport/kcl_drm_file.c similarity index 97% rename from drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c rename to drivers/gpu/drm/amd/backport/kcl_drm_file.c index 7ddc32cafc5b7..5bc74f05d555e 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_file.c @@ -37,6 +37,7 @@ #include #include #include +#include "amdgpu_fdinfo.h" #ifndef HAVE_DRM_SHOW_FDINFO /** * drm_show_fdinfo - helper for drm file fops @@ -63,6 +64,7 @@ void drm_show_fdinfo(struct seq_file *m, struct file *f) pci_domain_nr(pdev->bus), pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); } + + amdgpu_show_fdinfo(&p, file); } -EXPORT_SYMBOL(drm_show_fdinfo); #endif From 69fd48ed1b6a248564ec3ba55c9c1e6716447781 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Nov 2024 20:42:39 +0800 Subject: [PATCH 1245/2653] drm/amdkcl: Test whether radix_tree_iter_delete() is available It's caused by e760d0b2a1c1613f1a0e2ecf77ba6023d4f7bcdf "drm/amdgpu: prepare for logging ecc errors" Signed-off-by: Bob Zhou Reviewed-by: Asher Song Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++++++ drivers/gpu/drm/amd/dkms/config/config.h | 5 ++++- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/radix-tree-iter-delete.m4 | 16 ++++++++++++++++ 4 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/radix-tree-iter-delete.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 0a840f143f0c5..4c253dbd1fa94 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3315,6 +3315,7 @@ static int amdgpu_ras_get_poison_req(struct amdgpu_device *adev, return kfifo_get(&con->poison_fifo, poison_msg); } +#ifdef HAVE_RADIX_TREE_ITER_DELETE static void amdgpu_ras_ecc_log_init(struct ras_ecc_log_info *ecc_log) { mutex_init(&ecc_log->lock); @@ -3343,6 +3344,7 @@ static void amdgpu_ras_ecc_log_fini(struct ras_ecc_log_info *ecc_log) ecc_log->de_queried_count = 0; ecc_log->prev_de_queried_count = 0; } +#endif static bool amdgpu_ras_schedule_retirement_dwork(struct amdgpu_ras *con, uint32_t delayed_ms) @@ -3677,7 +3679,9 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info) } INIT_DELAYED_WORK(&con->page_retirement_dwork, amdgpu_ras_do_page_retirement); +#ifdef HAVE_RADIX_TREE_ITER_DELETE amdgpu_ras_ecc_log_init(&con->umc_ecc_log); +#endif #ifdef CONFIG_X86_MCE_AMD #ifdef HAVE_SMCA_UMC_V2 if ((adev->asic_type == CHIP_ALDEBARAN) && @@ -3736,7 +3740,9 @@ static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) cancel_delayed_work_sync(&con->page_retirement_dwork); +#ifdef HAVE_RADIX_TREE_ITER_DELETE amdgpu_ras_ecc_log_fini(&con->umc_ecc_log); +#endif mutex_lock(&con->recovery_lock); con->eh_data = NULL; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b0771ee3ad969..8e321dd5b45b1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -899,6 +899,9 @@ /* queue_work_node() is available */ #define HAVE_QUEUE_WORK_NODE 1 +/* radix_tree_iter_delete() is available */ +#define HAVE_RADIX_TREE_ITER_DELETE 1 + /* rb_add_cached is available */ #define HAVE_RB_ADD_CACHED 1 @@ -1066,7 +1069,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 6.7.0" +#define PACKAGE_STRING "amdgpu-dkms 6.8.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 51dd63a86cae7..1dac3f0eca171 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -219,6 +219,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_DEVICE_CLASS AC_AMDGPU_KVREALLOC AC_AMDGPU_DMA_BUF_IS_DYNAMIC + AC_AMDGPU_RADIX_TREE_ITER_DELETE AC_AMDGPU_DRM_CLIENT_REGISTER AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD diff --git a/drivers/gpu/drm/amd/dkms/m4/radix-tree-iter-delete.m4 b/drivers/gpu/drm/amd/dkms/m4/radix-tree-iter-delete.m4 new file mode 100644 index 0000000000000..ed747fab8a781 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/radix-tree-iter-delete.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v4.10-rc5-380-g0ac398ef391b +dnl # radix-tree: Add radix_tree_iter_delete +dnl # +AC_DEFUN([AC_AMDGPU_RADIX_TREE_ITER_DELETE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + radix_tree_iter_delete(NULL,NULL,NULL); + ], [ + AC_DEFINE(HAVE_RADIX_TREE_ITER_DELETE, 1, + [radix_tree_iter_delete() is available]) + ]) + ]) +]) From efddb8af00cc7c659825e8f8891667195aa1f69c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 26 Apr 2024 15:03:08 +0800 Subject: [PATCH 1246/2653] drm/amdkcl: Test wehther kfifo_put() use non pointer parameter It's caused by 8a61ce30f4b3c9b100c0e74fb082a23da7002c74 "drm/amdgpu: add message fifo to handle RAS poison events" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/kfifo_put.m4 | 20 ++++++++++++++++++++ 5 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/kfifo_put.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 4c253dbd1fa94..6d8db035bee3f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2317,6 +2317,7 @@ static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj event_id = amdgpu_ras_acquire_event_id(adev, type); RAS_EVENT_LOG(adev, event_id, "Poison is created\n"); +#ifdef HAVE_KFIFO_PUT_NON_POINTER if (amdgpu_ip_version(obj->adev, UMC_HWIP, 0) >= IP_VERSION(12, 0, 0)) { struct amdgpu_ras *con = amdgpu_ras_get_context(obj->adev); @@ -2325,6 +2326,7 @@ static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj wake_up(&con->page_retirement_wq); } +#endif } static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj, @@ -3283,6 +3285,7 @@ static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev, } } +#ifdef HAVE_KFIFO_PUT_NON_POINTER int amdgpu_ras_put_poison_req(struct amdgpu_device *adev, enum amdgpu_ras_block block, uint16_t pasid, pasid_notify pasid_fn, void *data, uint32_t reset) @@ -3314,6 +3317,7 @@ static int amdgpu_ras_get_poison_req(struct amdgpu_device *adev, return kfifo_get(&con->poison_fifo, poison_msg); } +#endif #ifdef HAVE_RADIX_TREE_ITER_DELETE static void amdgpu_ras_ecc_log_init(struct ras_ecc_log_info *ecc_log) @@ -3530,6 +3534,7 @@ static int amdgpu_ras_page_retirement_thread(void *param) } } while (atomic_read(&con->poison_creation_count)); +#ifdef HAVE_KFIFO_PUT_NON_POINTER if (ret != -EIO) { msg_count = kfifo_len(&con->poison_fifo); if (msg_count) { @@ -3572,6 +3577,7 @@ static int amdgpu_ras_page_retirement_thread(void *param) /* Wake up work to save bad pages to eeprom */ schedule_delayed_work(&con->page_retirement_dwork, 0); } +#endif } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c index c92b8794aa73d..bfc86f1e84e59 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c @@ -248,12 +248,16 @@ int amdgpu_umc_pasid_poison_handler(struct amdgpu_device *adev, struct amdgpu_ras *con = amdgpu_ras_get_context(adev); int ret; +#ifdef HAVE_KFIFO_PUT_NON_POINTER ret = amdgpu_ras_put_poison_req(adev, block, pasid, pasid_fn, data, reset); if (!ret) { +#endif atomic_inc(&con->page_retirement_req_cnt); wake_up(&con->page_retirement_wq); +#ifdef HAVE_KFIFO_PUT_NON_POINTER } +#endif } } else { if (adev->virt.ops && adev->virt.ops->ras_poison_handler) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8e321dd5b45b1..b46cf201f7a0a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -692,6 +692,9 @@ /* kernel_write() take arg type of position as pointer */ #define HAVE_KERNEL_WRITE_PPOS 1 +/* kfifo_put() have non pointer parameter */ +#define HAVE_KFIFO_PUT_NON_POINTER 1 + /* kmalloc_size_roundup is available */ #define HAVE_KMALLOC_SIZE_ROUNDUP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1dac3f0eca171..4ba7b2adeb555 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -220,6 +220,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KVREALLOC AC_AMDGPU_DMA_BUF_IS_DYNAMIC AC_AMDGPU_RADIX_TREE_ITER_DELETE + AC_AMDGPU_KFIFO_PUT AC_AMDGPU_DRM_CLIENT_REGISTER AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD diff --git a/drivers/gpu/drm/amd/dkms/m4/kfifo_put.m4 b/drivers/gpu/drm/amd/dkms/m4/kfifo_put.m4 new file mode 100644 index 0000000000000..6668ba3281246 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kfifo_put.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # v3.12-8403-g498d319bb512 +dnl # kfifo API type safety +dnl # +AC_DEFUN([AC_AMDGPU_KFIFO_PUT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + static DEFINE_KFIFO(fifo, int, 2); + kfifo_put(&fifo, 0); + ],[ + AC_DEFINE(HAVE_KFIFO_PUT_NON_POINTER, 1, + [kfifo_put() have non pointer parameter]) + ]) + ]) +]) + + + From f8c1219528b5744386a7d316663a5a9e7fad9d9e Mon Sep 17 00:00:00 2001 From: Jesse Zhang Date: Mon, 6 May 2024 14:40:21 +0800 Subject: [PATCH 1247/2653] drm/amd/pm: fix the uninitialized scalar variable warning Fix warning for using uninitialized values sclk_mask, mclk_mask and soc_mask. v2:Set default variable to UMD PSTATE(Tim Huang) Signed-off-by: Jesse Zhang Acked-by: Yang Wang Signed-off-by: Jesse Zhang --- .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 29 ++++++++++++++++--- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c index e97b0cf19197e..e1787070a79a5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c @@ -830,10 +830,20 @@ static int renoir_force_clk_levels(struct smu_context *smu, ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL); + /* = 0: min_freq + * = 1: UMD_PSTATE_CLK + * >= 2: max_freq + */ + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, + soft_max_level == 0 ? min_freq : + soft_max_level == 1 ? RENOIR_UMD_PSTATE_SOCCLK : max_freq, + NULL); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, + soft_min_level == 0 ? min_freq : + soft_min_level == 1 ? RENOIR_UMD_PSTATE_SOCCLK : max_freq, + NULL); if (ret) return ret; break; @@ -845,10 +855,21 @@ static int renoir_force_clk_levels(struct smu_context *smu, ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL); + /* mclk levels are in reverse order + * = 0: max_freq + * = 1: UMD_PSTATE_CLK + * >= 2: min_freq + */ + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, + soft_max_level >= 2 ? min_freq : + soft_max_level == 1 ? RENOIR_UMD_PSTATE_FCLK : max_freq, + NULL); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, + soft_min_level >= 2 ? min_freq : + soft_min_level == 1 ? RENOIR_UMD_PSTATE_SOCCLK : max_freq, + NULL); if (ret) return ret; break; From f232071004bcda0e60f49779d50baf90e24bf760 Mon Sep 17 00:00:00 2001 From: Jesse Zhang Date: Tue, 7 May 2024 13:17:32 +0800 Subject: [PATCH 1248/2653] drm/amd/pm: revert "drm/amd/pm: fix the uninitialized scalar variable warning" Revert commit 576bffd10d01 ("drm/amd/pm: fix the uninitialized scalar variable warning") and will update new patch. Signed-off-by: Jesse Zhang Reviewed-by: Tim Huang Signed-off-by: Jesse Zhang --- .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 29 +++---------------- 1 file changed, 4 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c index e1787070a79a5..e97b0cf19197e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c @@ -830,20 +830,10 @@ static int renoir_force_clk_levels(struct smu_context *smu, ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); if (ret) return ret; - /* = 0: min_freq - * = 1: UMD_PSTATE_CLK - * >= 2: max_freq - */ - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, - soft_max_level == 0 ? min_freq : - soft_max_level == 1 ? RENOIR_UMD_PSTATE_SOCCLK : max_freq, - NULL); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, - soft_min_level == 0 ? min_freq : - soft_min_level == 1 ? RENOIR_UMD_PSTATE_SOCCLK : max_freq, - NULL); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL); if (ret) return ret; break; @@ -855,21 +845,10 @@ static int renoir_force_clk_levels(struct smu_context *smu, ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); if (ret) return ret; - /* mclk levels are in reverse order - * = 0: max_freq - * = 1: UMD_PSTATE_CLK - * >= 2: min_freq - */ - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, - soft_max_level >= 2 ? min_freq : - soft_max_level == 1 ? RENOIR_UMD_PSTATE_FCLK : max_freq, - NULL); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, - soft_min_level >= 2 ? min_freq : - soft_min_level == 1 ? RENOIR_UMD_PSTATE_SOCCLK : max_freq, - NULL); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL); if (ret) return ret; break; From f7a9fa6bd41defa3b7a1d0c36a02955d676aff85 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Fri, 5 Apr 2024 17:59:53 -0400 Subject: [PATCH 1249/2653] drm/amdgpu: Skip dma map resource for null RDMA device To test RDMA using dummy driver on the system without NIC/RDMA device, the get/put dma pages pass in null device pointer, skip the dma map/unmap resource and sg table to avoid null pointer access. Signed-off-by: Philip Yang Reviewed-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 33 +++++++++++--------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 95a63a7c18154..168dea1eef0e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -758,12 +758,15 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, unsigned long size = min(cursor.size, AMDGPU_MAX_SG_SEGMENT_SIZE); dma_addr_t addr; - addr = dma_map_resource(dev, phys, size, dir, - DMA_ATTR_SKIP_CPU_SYNC); - r = dma_mapping_error(dev, addr); - if (r) - goto error_unmap; - + if (dev) { + addr = dma_map_resource(dev, phys, size, dir, + DMA_ATTR_SKIP_CPU_SYNC); + r = dma_mapping_error(dev, addr); + if (r) + goto error_unmap; + } else { + addr = phys; + } sg_set_page(sg, NULL, size, 0); sg_dma_address(sg) = addr; sg_dma_len(sg) = size; @@ -777,10 +780,10 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, for_each_sgtable_sg((*sgt), sg, i) { if (!sg->length) continue; - - dma_unmap_resource(dev, sg->dma_address, - sg->length, dir, - DMA_ATTR_SKIP_CPU_SYNC); + if (dev) + dma_unmap_resource(dev, sg->dma_address, + sg->length, dir, + DMA_ATTR_SKIP_CPU_SYNC); } sg_free_table(*sgt); @@ -805,10 +808,12 @@ void amdgpu_vram_mgr_free_sgt(struct device *dev, struct scatterlist *sg; int i; - for_each_sgtable_sg(sgt, sg, i) - dma_unmap_resource(dev, sg->dma_address, - sg->length, dir, - DMA_ATTR_SKIP_CPU_SYNC); + if (dev) { + for_each_sgtable_sg(sgt, sg, i) + dma_unmap_resource(dev, sg->dma_address, + sg->length, dir, + DMA_ATTR_SKIP_CPU_SYNC); + } sg_free_table(sgt); kfree(sgt); } From 23b3a2f8cbf44a6902d2a897f6473668d5babd17 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Fri, 5 Apr 2024 18:54:51 -0400 Subject: [PATCH 1250/2653] drm/amdkfd: Allow peer direct dma map with null RDMA device To test KFD peer direct RDMA functions on system without NIC/RDMA device. Add dynamic debug message to dump sg table segments address and size, to help debug contiguous VRAM peer direct RDMA. Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 11 +++++++---- drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 13 ++++++++++--- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 5610abd8bdef5..fc6411b92e89e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2588,9 +2588,11 @@ int amdgpu_amdkfd_gpuvm_get_sg_table(struct amdgpu_device *adev, cur_page++; } - ret = dma_map_sgtable(dma_dev, sg, dir, DMA_ATTR_SKIP_CPU_SYNC); - if (ret) - goto out_of_range; + if (dma_dev) { + ret = dma_map_sgtable(dma_dev, sg, dir, DMA_ATTR_SKIP_CPU_SYNC); + if (ret) + goto out_of_range; + } *ret_sg = sg; return 0; @@ -2614,7 +2616,8 @@ void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, } /* Unmap system memory */ - dma_unmap_sgtable(dma_dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC); + if (dma_dev) + dma_unmap_sgtable(dma_dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC); sg_free_table(sgt); kfree(sgt); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index 50541b1dac44a..637a6ceaffefe 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -281,7 +281,9 @@ static int amd_dma_map(struct sg_table *sg_head, void *client_context, struct device *dma_device, int dmasync, int *nmap) { struct sg_table *sg_table_tmp; + struct scatterlist *sg; int ret; + int i; /* * NOTE/TODO: @@ -308,7 +310,7 @@ static int amd_dma_map(struct sg_table *sg_head, void *client_context, pr_debug("Client context: 0x%p, sg_head: 0x%p\n", client_context, sg_head); - if (!mem_context || !mem_context->bo || !mem_context->dev) { + if (!mem_context || !mem_context->bo) { pr_warn("Invalid client context"); return -EINVAL; } @@ -328,6 +330,11 @@ static int amd_dma_map(struct sg_table *sg_head, void *client_context, return ret; } + pr_debug("size 0x%llx nents %d\n", mem_context->size, sg_table_tmp->nents); + for_each_sgtable_sg(sg_table_tmp, sg, i) + pr_debug("segment_%d dma_address 0x%llx length 0x%x dma_length 0x%x\n", + i, sg->dma_address, sg->length, sg->dma_length); + /* Maintain a copy of the handle to sg_table */ mem_context->pages = sg_table_tmp; mem_context->dma_dev = dma_device; @@ -335,7 +342,7 @@ static int amd_dma_map(struct sg_table *sg_head, void *client_context, /* Copy information about previosly allocated sg_table */ *sg_head = *mem_context->pages; - /* Return number of pages */ + /* Return number of sg table segments */ *nmap = mem_context->pages->nents; return ret; @@ -350,7 +357,7 @@ static int amd_dma_unmap(struct sg_table *sg_head, void *client_context, pr_debug("Client context: 0x%p, sg_table: 0x%p\n", client_context, sg_head); - if (!mem_context || !mem_context->bo || !mem_context->dma_dev) { + if (!mem_context || !mem_context->bo) { pr_warn("Invalid client context"); return -EINVAL; } From 8b739968f955d840f740c04d6bcd4aba02b4f644 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 15 May 2024 11:02:55 +0800 Subject: [PATCH 1251/2653] drm/amdkcl: wrap code under macro HAVE_HDR_SINK_METADATA It's caused by e559239eabe628d65d3fbe184890f73477fca0f9 "drm/amd/display: Don't register panel_power_savings on OLED panels" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0dc5c4dd049ef..3bb10a71b9be3 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7395,6 +7395,7 @@ amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector) if (amdgpu_dm_connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) return false; +#ifdef HAVE_HDR_SINK_METADATA /* check for OLED panels */ if (amdgpu_dm_connector->bl_idx >= 0) { struct drm_device *drm = amdgpu_dm_connector->base.dev; @@ -7405,6 +7406,7 @@ amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector) if (caps->aux_support) return false; } +#endif return true; } From 17a411fa0525eb8e168ad774ce5ecbf7e568dfb6 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 9 May 2024 15:52:44 -0400 Subject: [PATCH 1252/2653] drm/amdkfd: clear soft lockup issue with host trap When user sets an interval less than what driver can handle, soft lockup arises. To clear this soft lockup with adding a schedule before trigger a new host trap. [ 2896.405488] watchdog: BUG: soft lockup - CPU#22 stuck for 26s! [pcs_130:38057] [ 2896.405676] Supported: No, Unsupported modules are loaded [ 2896.405678] CPU: 22 PID: 38057 Comm: pcs_130 Kdump: loaded Tainted: G OE X N 5.14.21-150500.55.59-default #1 SLE15-SP5 3a8569df5696e57cdcb648c7e890af33bdc23f85 [ 2896.405683] Hardware name: Dell Inc. PowerEdge R7525/0590KW, BIOS 2.6.6 01/13/2022 [ 2896.405684] RIP: 0010:amdgpu_device_rreg.part.42+0x57/0x1d0 [amdgpu] [ 2896.405978] Code: 6f 4c 9c 00 4c 8b 83 b8 08 00 00 4d 01 e0 85 c9 74 15 65 48 8b 04 25 00 1c 02 00 3b 88 b8 09 00 00 0f 85 52 01 00 00 41 8b 28 <8b> 05 43 4c 9c 00 85 c0 74 56 65 48 8b 14 25 00 1c 02 00 39 82 b8 [ 2896.405981] RSP: 0018:ffffb7a6ecc33e30 EFLAGS: 00000246 [ 2896.405984] RAX: ffff949389f18000 RBX: ffff94d3d1100000 RCX: 00000000000094a9 [ 2896.405985] RDX: 0000000000000000 RSI: 0000000000002376 RDI: ffff94d3d1100000 [ 2896.405987] RBP: 0000000000000000 R08: ffffb7a6e2b88dd8 R09: ffff94d30e3b1f14 [ 2896.405989] R10: ffffb7a6c0427d88 R11: ffffb7a6ecc33c80 R12: 0000000000008dd8 [ 2896.405990] R13: 0000000000002376 R14: ffff94d30e3b1f14 R15: ffff94d3d1100000 [ 2896.405992] FS: 0000000000000000(0000) GS:ffff9512ff580000(0000) knlGS:0000000000000000 [ 2896.405994] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 2896.405996] CR2: 00007f5b2b732000 CR3: 0000006a1ee10003 CR4: 0000000000770ee0 [ 2896.405998] PKRU: 55555554 [ 2896.405999] Call Trace: [ 2896.406004] [ 2896.406007] kgd_gfx_v9_trigger_pc_sample_trap+0x1d6/0x4f0 [amdgpu 75bb93fc913928fc00917a1c71d5c2dca258175d] Signed-off-by: James Zhu Tested-by: Vladimir Indic Reviewed-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 4572ac447ee4b..2a9a7a9bb6e6d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -91,12 +91,13 @@ static int kfd_pc_sample_thread(void *param) wait_time = ktime_sub(next_trap_time, ktime_get_raw()); wait_ns = ktime_to_ns(wait_time); wait_us = ktime_to_us(wait_time); - if (wait_ns >= 10000) + if (wait_ns >= 10000) { usleep_range(wait_us - 10, wait_us); - else if (wait_ns > 0) + } else { schedule(); - else - need_wait = false; + if (wait_ns <= 0) + need_wait = false; + } } } From 1f5c4dfc4a5cceee94f328ad4b526aada9c470db Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 22 Aug 2024 15:45:53 +0800 Subject: [PATCH 1253/2653] drm/amdkfd: [WA] disable SQ core clock gate When host trap pc sampling is activted. Since Command bus from SPI/SQG to SQ may have some conflict with SQ internal clock gating, when we have many host trap command it will trigger qcm fence timeout. Signed-off-by: James Zhu Tested-by: Vladimir Indic Reviewed-by: Vladimir Indic Signed-off-by: Asher Song --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 3 ++- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 3 ++- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 16 ++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h | 3 +++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 11 +++++++++-- drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 3 +++ 6 files changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c index af2f201eb32f9..31314ed5bb0b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c @@ -206,5 +206,6 @@ const struct kfd2kgd_calls aldebaran_kfd2kgd = { .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, .hqd_reset = kgd_gfx_v9_hqd_reset, .hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell, - .trigger_pc_sample_trap = kgd_aldebaran_trigger_pc_sample_trap + .trigger_pc_sample_trap = kgd_aldebaran_trigger_pc_sample_trap, + .override_core_cg = kgd_gfx_v9_override_core_cg, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c index 01b0a33a17042..c9a4ef391f0d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c @@ -433,5 +433,6 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = { .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, .hqd_reset = kgd_gfx_v9_hqd_reset, .hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell, - .trigger_pc_sample_trap = kgd_arcturus_trigger_pc_sample_trap + .trigger_pc_sample_trap = kgd_arcturus_trigger_pc_sample_trap, + .override_core_cg = kgd_gfx_v9_override_core_cg }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index d45923bfde87f..07f26968a598a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1259,6 +1259,22 @@ static uint32_t kgd_aldebaran_get_hosttrap_status(struct amdgpu_device *adev, return sq_hosttrap_status; } +void kgd_gfx_v9_override_core_cg(struct amdgpu_device *adev, + uint32_t value, + uint32_t inst) +{ + uint32_t clk_cntl; + + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + + RREG32_SOC15(GC, GET_INST(GC, inst), mmCGTT_SQ_CLK_CTRL); + clk_cntl = REG_SET_FIELD(clk_cntl, CGTT_SQ_CLK_CTRL, CORE_OVERRIDE, value); + WREG32_SOC15(GC, GET_INST(GC, inst), mmCGTT_SQ_CLK_CTRL, clk_cntl); + + mutex_unlock(&adev->grbm_idx_mutex); +} + uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, uint32_t vmid, uint32_t max_wave_slot, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h index 892c91a1c1b63..675054356eca6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h @@ -122,3 +122,6 @@ uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, uint32_t *target_wave_slot, enum kfd_ioctl_pc_sample_method method, uint32_t inst); +void kgd_gfx_v9_override_core_cg(struct amdgpu_device *adev, + uint32_t value, + uint32_t inst); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 2a9a7a9bb6e6d..72042277cc2b8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -47,6 +47,7 @@ static int kfd_pc_sample_thread(void *param) uint32_t timeout = 0; ktime_t next_trap_time; bool need_wait; + uint32_t inst; mutex_lock(&node->pcs_data.mutex); if (node->pcs_data.hosttrap_entry.base.active_count && @@ -68,11 +69,14 @@ static int kfd_pc_sample_thread(void *param) adev = node->adev; need_wait = false; allow_signal(SIGKILL); + + if (node->kfd2kgd->override_core_cg) + for_each_inst(inst, node->xcc_mask) + node->kfd2kgd->override_core_cg(adev, 1, inst); + while (!kthread_should_stop() && !signal_pending(node->pcs_data.hosttrap_entry.base.pc_sample_thread)) { if (!need_wait) { - uint32_t inst; - next_trap_time = ktime_add_us(ktime_get_raw(), timeout); for_each_inst(inst, node->xcc_mask) { @@ -100,6 +104,9 @@ static int kfd_pc_sample_thread(void *param) } } } + if (node->kfd2kgd->override_core_cg) + for_each_inst(inst, node->xcc_mask) + node->kfd2kgd->override_core_cg(adev, 0, inst); node->pcs_data.hosttrap_entry.base.target_simd = 0; node->pcs_data.hosttrap_entry.base.target_wave_slot = 0; diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 32f92e0ac3588..26f5a542877cc 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -346,6 +346,9 @@ struct kfd2kgd_calls { uint32_t *target_wave_slot, enum kfd_ioctl_pc_sample_method method, uint32_t inst); + void (*override_core_cg)(struct amdgpu_device *adev, + uint32_t value, + uint32_t inst); }; #endif /* KGD_KFD_INTERFACE_H_INCLUDED */ From 1e5d37d419edd3266a87f9a04a4c50b89b1d0a37 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 16 May 2024 14:00:18 +0800 Subject: [PATCH 1254/2653] drm/amdkcl: kcl-cleanup HAVE_SMCA_UMC_V2 is_smca_umc_v2 function never occurs in upstream kernel, macro HAVE_SMCA_UMC_V2 is undefined all the time, which cause MCE notifications is not handled on MI200 A+A platform. So we drop macro HAVE_SMCA_UMC_V2. On the other hand, on Centos 7.9, SMCA_UMC_V2 is not defined in arch/x86/include/asm/mce.h, we don't care umc_v2 error notification on centos 7.9. Signed-off-by: Asher Song Reviewed-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 10 ++-------- drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- .../gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 | 13 ------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- .../gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 | 17 +++++++++++++++++ 5 files changed, 22 insertions(+), 24 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 6d8db035bee3f..d24671eaefb56 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -45,10 +45,8 @@ #ifdef CONFIG_X86_MCE_AMD #include -#ifdef HAVE_SMCA_UMC_V2 static bool notifier_registered; #endif -#endif static const char *RAS_FS_NAME = "ras"; const char *ras_error_string[] = { @@ -150,7 +148,6 @@ static void amdgpu_ras_critical_region_init(struct amdgpu_device *adev); static void amdgpu_ras_critical_region_fini(struct amdgpu_device *adev); #ifdef CONFIG_X86_MCE_AMD -#ifdef HAVE_SMCA_UMC_V2 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev); struct mce_notifier_adev_list { struct amdgpu_device *devs[MAX_GPU_INSTANCE]; @@ -158,7 +155,6 @@ struct mce_notifier_adev_list { }; static struct mce_notifier_adev_list mce_adev_list; #endif -#endif void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) { @@ -3689,11 +3685,9 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info) amdgpu_ras_ecc_log_init(&con->umc_ecc_log); #endif #ifdef CONFIG_X86_MCE_AMD -#ifdef HAVE_SMCA_UMC_V2 if ((adev->asic_type == CHIP_ALDEBARAN) && (adev->gmc.xgmi.connected_to_cpu)) amdgpu_register_bad_pages_mca_notifier(adev); -#endif #endif return 0; @@ -4690,7 +4684,6 @@ void amdgpu_release_ras_context(struct amdgpu_device *adev) } #ifdef CONFIG_X86_MCE_AMD -#ifdef HAVE_SMCA_UMC_V2 static struct amdgpu_device *find_adev(uint32_t node_id) { int i; @@ -4726,8 +4719,10 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, * and error occurred in DramECC (Extended error code = 0) then only * process the error, else bail out. */ +#ifdef HAVE_SMCA_UMC_V2 if (!m || !((kcl_smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && (XEC(m->status, 0x3f) == 0x0))) +#endif return NOTIFY_DONE; /* @@ -4791,7 +4786,6 @@ static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev) } } #endif -#endif struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b46cf201f7a0a..79f02869cafc8 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -929,8 +929,8 @@ /* whether smca_get_bank_type(x, x) is available */ #define HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS 1 -/* is_smca_umc_v2() is available */ -/* #undef HAVE_SMCA_UMC_V2 */ +/* enum SMCA_UMC_V2 is available */ +#define HAVE_SMCA_UMC_V2 1 /* struct dma_buf_attach_ops->allow_peer2peer is available */ #define HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 b/drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 deleted file mode 100644 index 28eda1decdae2..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 +++ /dev/null @@ -1,13 +0,0 @@ -dnl # -dnl # -dnl # is_smca_umc_v2() -dnl # -AC_DEFUN([AC_AMDGPU_CHECK_SMCA_UMC_V2], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([is_smca_umc_v2], - [arch/x86/kernel/cpu/mce/amd.c], [ - AC_DEFINE(HAVE_SMCA_UMC_V2, 1, - [is_smca_umc_v2() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4ba7b2adeb555..c388978705f9a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -125,7 +125,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PM_SUSPEND_VIA_FIRMWARE AC_AMDGPU_SYSFS_EMIT AC_AMDGPU_KTIME_IS_UNION - AC_AMDGPU_CHECK_SMCA_UMC_V2 AC_AMDGPU_PXM_TO_NODE AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY AC_AMDGPU_KERNEL_WRITE @@ -233,6 +232,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DBG_PRINTER AC_AMDGPU_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS AC_AMDGPU_DRM_DEBUG_CATEGORY + AC_AMDGPU_SMCA_UMC_V2 AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 index e3d33a862d7fb..de3f546345a28 100644 --- a/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 @@ -15,3 +15,20 @@ AC_DEFUN([AC_AMDGPU_MCE_PRIO_UC], [ ]) ]) ]) +dnl # +dnl # v5.13-rc3-1-g94a311ce248e +dnl # x86/MCE/AMD, EDAC/mce_amd: Add new SMCA bank types +dnl # +AC_DEFUN([AC_AMDGPU_SMCA_UMC_V2], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum smca_bank_types bank_type; + bank_type = SMCA_UMC_V2; + ], [ + AC_DEFINE(HAVE_SMCA_UMC_V2, 1, + [enum SMCA_UMC_V2 is available]) + ]) + ]) +]) From 0ffca40a9eced57e5e4a8569b5f246d6bfa0356e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 17 May 2024 11:52:59 +0800 Subject: [PATCH 1255/2653] drm/amdkcl: fake smca_get_bank_type When redefining HAVE_SMCA_UMC_V2, the fake function smca_get_bank_type is called by amdgpu_bad_page_notifier. However origin fake function can not be referenced when making intree build as it defined in amdkcl modules. So we make a macro for the fake function in backport/kcl_mce.h Signed-off-by: Asher Song Reviewed-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c | 37 +++++------------------- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/backport/kcl_mce.h | 13 +++++++++ include/kcl/kcl_mce.h | 26 +++++++++++++---- 5 files changed, 42 insertions(+), 37 deletions(-) create mode 100644 include/kcl/backport/kcl_mce.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index d24671eaefb56..7985941728bfd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -4720,7 +4720,7 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, * process the error, else bail out. */ #ifdef HAVE_SMCA_UMC_V2 - if (!m || !((kcl_smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && + if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && (XEC(m->status, 0x3f) == 0x0))) #endif return NOTIFY_DONE; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c index bd90d447713f5..e2cd6191d7171 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c @@ -7,24 +7,11 @@ * * All MC4_MISCi registers are shared between cores on a node. */ - - #ifdef CONFIG_X86_MCE_AMD #include -#if defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) -enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) -{ - return smca_get_bank_type(cpu, bank); -} -#elif defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) -enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) -{ - return smca_get_bank_type(bank); -} - -/* Copied from v5.15-rc2-452-gf38ce910d8df:arch/x86/kernel/cpu/mce/amd.c and modified for KCL */ -#elif defined(HAVE_STRUCT_SMCA_BANK) +#if !defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) && !defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) +#if defined(HAVE_STRUCT_SMCA_BANK) enum smca_bank_types smca_get_bank_type(unsigned int bank) { struct smca_bank *b; @@ -38,24 +25,14 @@ enum smca_bank_types smca_get_bank_type(unsigned int bank) return b->hwid->bank_type; } -enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) -{ - return smca_get_bank_type(bank); -} - #else int smca_get_bank_type(unsigned int bank) { - pr_warn_once("smca_get_bank_type is not supported\n"); - return 0; + pr_warn_once("smca_get_bank_type is not supported\n"); + return 0; } - -int kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) -{ - return smca_get_bank_type(bank); -} - -#endif -EXPORT_SYMBOL_GPL(kcl_smca_get_bank_type); +#endif +EXPORT_SYMBOL_GPL(smca_get_bank_type); +#endif #endif /* CONFIG_X86_MCE_AMD */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 5b6a4ed692d8d..78ab1d617f6b3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -125,4 +125,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/backport/kcl_mce.h b/include/kcl/backport/kcl_mce.h new file mode 100644 index 0000000000000..08c69209a1a49 --- /dev/null +++ b/include/kcl/backport/kcl_mce.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_BACKPORT_KCL_MCE_H +#define _KCL_BACKPORT_KCL_MCE_H + +#include + +#ifdef CONFIG_X86_MCE_AMD +#ifndef HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS +#define smca_get_bank_type _kcl_smca_get_bank_type +#endif /* HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS */ +#endif /* CONFIG_X86_MCE_AMD */ + +#endif /* _KCL_BACKPORT_KCL_MCE_H */ diff --git a/include/kcl/kcl_mce.h b/include/kcl/kcl_mce.h index fd6098c99a240..223c2bd03bb87 100644 --- a/include/kcl/kcl_mce.h +++ b/include/kcl/kcl_mce.h @@ -11,15 +11,29 @@ #define XEC(x, mask) (((x) >> 16) & mask) #endif -#if defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) || defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) || defined(HAVE_STRUCT_SMCA_BANK) -enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank); -#else -int kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank); -#endif - #ifndef HAVE_MCE_PRIO_UC #define MCE_PRIO_UC MCE_PRIO_SRAO #endif +#if !defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) +#if defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) || defined(HAVE_STRUCT_SMCA_BANK) +#if defined(HAVE_STRUCT_SMCA_BANK) +enum smca_bank_types smca_get_bank_type(unsigned int bank); +#endif +static inline +enum smca_bank_types _kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) +{ + return smca_get_bank_type(bank); +} +#else +int smca_get_bank_type(unsigned int bank); +static inline +int _kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) +{ + return smca_get_bank_type(bank); +} +#endif +#endif + #endif /* CONFIG_X86_MCE_AMD */ #endif From 09cf8cb8effb388ca36e9b4621180efa3ef616c1 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 22 May 2024 21:00:34 +0800 Subject: [PATCH 1256/2653] drm/amdkcl:test topology_num_cores_per_package whether exist It's caused by v6.8-rc4-71-g89b0f15f408f x86/cpu/topology: Get rid of cpuinfo::x86_max_cores Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/asm_topology.m4 | 19 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 4 ++++ 3 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/asm_topology.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/asm_topology.m4 b/drivers/gpu/drm/amd/dkms/m4/asm_topology.m4 new file mode 100644 index 0000000000000..ec603c4bd1a9b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/asm_topology.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v6.8-rc4-70-gfd43b8ae76e9 +dnl # x86/cpu/topology: Provide __num_[cores|threads]_per_package +dnl # +AC_DEFUN([AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + int a = 0; + a = topology_num_cores_per_package(); + ], [ + AC_DEFINE(HAVE_TOPOLOGY_NUM_CORES_PER_PACKAGE, 1, + [topology_num_cores_per_package is availablea]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c388978705f9a..01d7f526f7405 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -233,6 +233,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS AC_AMDGPU_DRM_DEBUG_CATEGORY AC_AMDGPU_SMCA_UMC_V2 + AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index 2c9869feba610..a4b4c01b9bd95 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -453,7 +453,11 @@ static int vangogh_init_smc_tables(struct smu_context *smu) #ifdef CONFIG_X86 /* AMD x86 APU only */ +#ifdef HAVE_TOPOLOGY_NUM_CORES_PER_PACKAGE smu->cpu_core_num = topology_num_cores_per_package(); +#else + smu->cpu_core_num = boot_cpu_data.x86_max_cores; +#endif #else smu->cpu_core_num = 4; #endif From 8f4896f02c0703927a0acbd1bbcdc517b0351cd3 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 23 May 2024 13:59:58 +0800 Subject: [PATCH 1257/2653] drm/amdkcl: fake linux/pgtable.h header It's caused by v6.8-rc6-1469-g2c6f6831876a drm/ttm: make ttm_caching.h self-contained Signed-off-by: Asher Song --- include/kcl/header/linux/pgtable.h | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 include/kcl/header/linux/pgtable.h diff --git a/include/kcl/header/linux/pgtable.h b/include/kcl/header/linux/pgtable.h new file mode 100644 index 0000000000000..27198a089c730 --- /dev/null +++ b/include/kcl/header/linux/pgtable.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_PGTABLE_H_H_ +#define _KCL_HEADER_LINUX_PGTABLE_H_H_ + +#ifdef HAVE_LINUX_PGTABLE_H +#include_next +#else +#include +#endif + +#endif From 813d12bb7ba45e144e3d172784a44cc70ceab955 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 23 May 2024 14:41:31 +0800 Subject: [PATCH 1258/2653] drm/amdkcl: fake drm_info_once It's caused by v6.9-rc1-50-g27906e5d7824 drm/ttm: Print the memory decryption status just once Signed-off-by: Asher Song --- include/kcl/kcl_drm_print.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 0546bd944b72c..0506b7a41f121 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -201,4 +201,10 @@ enum drm_debug_category { __drm_printk((drm), info,, fmt, ##__VA_ARGS__) #endif +#ifndef drm_info_once +/* copied from include/drm/drm_print.h */ +#define drm_info_once(drm, fmt, ...) \ + __drm_printk((drm), info, _once, fmt, ##__VA_ARGS__) +#endif + #endif From 5176bb0f9adaabe021c5565b5138844d59e538dd Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 23 May 2024 14:58:19 +0800 Subject: [PATCH 1259/2653] drm/amdkcl: Test whether drm_gem_object->resv is available It's caused by v6.8-rc6-1519-g5a95f39d9b21 drm/ttm: warn when resv objs are mixed in a bulk_move v6.4-rc2-1582-ge2ad8e2df432 drm/amdgpu: make sure BOs are locked in amdgpu_vm_get_memory Signed-off-by: Asher Song --- drivers/gpu/drm/ttm/ttm_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c index 185d23323db70..af19a71571932 100644 --- a/drivers/gpu/drm/ttm/ttm_resource.c +++ b/drivers/gpu/drm/ttm/ttm_resource.c @@ -232,7 +232,7 @@ static void ttm_lru_bulk_move_add(struct ttm_lru_bulk_move *bulk, pos->first = res; pos->last = res; } else { - WARN_ON(pos->first->bo->base.resv != res->bo->base.resv); + WARN_ON(amdkcl_ttm_resvp(pos->first->bo) != amdkcl_ttm_resvp(res->bo)); ttm_lru_bulk_move_pos_tail(pos, res); } } From 8f12d5027556159ad4d7f179ff50aabbcac38f0b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 29 May 2024 17:39:47 +0800 Subject: [PATCH 1260/2653] drm/amdkcl: remove macro HAVE_AMD_IOMMU_PC_SUPPORTED Due IOMMUv2 support have been removed, this macro is not required. c99a2e7ae291e5b19b60443eb drm/amdkfd: drop IOMMUv2 support Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 18 ------------------ drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 6 ------ 2 files changed, 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 2bc99a24c536b..df47004cb69ba 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -115,9 +115,7 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) struct kfd_cache_properties *cache; struct kfd_iolink_properties *iolink; struct kfd_iolink_properties *p2plink; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties *perf; -#endif list_del(&dev->list); @@ -149,14 +147,12 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) kfree(p2plink); } -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED while (dev->perf_props.next != &dev->perf_props) { perf = container_of(dev->perf_props.next, struct kfd_perf_properties, list); list_del(&perf->list); kfree(perf); } -#endif kfree(dev); } @@ -193,9 +189,7 @@ struct kfd_topology_device *kfd_create_topology_device( INIT_LIST_HEAD(&dev->cache_props); INIT_LIST_HEAD(&dev->io_link_props); INIT_LIST_HEAD(&dev->p2p_link_props); -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED INIT_LIST_HEAD(&dev->perf_props); -#endif list_add_tail(&dev->list, device_list); @@ -389,7 +383,6 @@ static const struct kobj_type cache_type = { .sysfs_ops = &cache_ops, }; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED /****** Sysfs of Performance Counters ******/ struct kfd_perf_attr { @@ -423,7 +416,6 @@ static struct kfd_perf_attr perf_attr_iommu[] = { KFD_PERF_DESC(counter_ids, 0), }; /****************************************/ -#endif static ssize_t node_show(struct kobject *kobj, struct attribute *attr, char *buffer) @@ -585,9 +577,7 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) struct kfd_iolink_properties *iolink; struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties *perf; -#endif if (dev->kobj_p2plink) { list_for_each_entry(p2plink, &dev->p2p_link_props, list) @@ -653,7 +643,6 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) dev->kobj_mem = NULL; } -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED if (dev->kobj_perf) { list_for_each_entry(perf, &dev->perf_props, list) { kfree(perf->attr_group); @@ -663,7 +652,6 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) kobject_put(dev->kobj_perf); dev->kobj_perf = NULL; } -#endif if (dev->kobj_node) { sysfs_remove_file(dev->kobj_node, &dev->attr_gpuid); @@ -682,11 +670,9 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, struct kfd_iolink_properties *iolink; struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties *perf; uint32_t num_attrs; struct attribute **attrs; -#endif int ret; uint32_t i; @@ -723,11 +709,9 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, if (!dev->kobj_p2plink) return -ENOMEM; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED dev->kobj_perf = kobject_create_and_add("perf", dev->kobj_node); if (!dev->kobj_perf) return -ENOMEM; -#endif /* * Creating sysfs files for node properties @@ -846,7 +830,6 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, i++; } -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED /* All hardware blocks have the same number of attributes. */ num_attrs = ARRAY_SIZE(perf_attr_iommu); list_for_each_entry(perf, &dev->perf_props, list) { @@ -872,7 +855,6 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, if (ret < 0) return ret; } -#endif return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index e4f9d839be01e..ab7a3bf1bdefe 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -135,14 +135,12 @@ struct kfd_iolink_properties { struct attribute attr; }; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties { struct list_head list; char block_name[16]; uint32_t max_concurrent; struct attribute_group *attr_group; }; -#endif struct kfd_topology_device { struct list_head list; @@ -153,18 +151,14 @@ struct kfd_topology_device { struct list_head cache_props; struct list_head io_link_props; struct list_head p2p_link_props; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct list_head perf_props; -#endif struct kfd_node *gpu; struct kobject *kobj_node; struct kobject *kobj_mem; struct kobject *kobj_cache; struct kobject *kobj_iolink; struct kobject *kobj_p2plink; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kobject *kobj_perf; -#endif struct attribute attr_gpuid; struct attribute attr_name; struct attribute attr_props; From 954f6cadd8c72e566837f838eb5e67498eed2973 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 17 May 2024 15:18:01 +0800 Subject: [PATCH 1261/2653] drm/amdgpu: fix the used uninitialized issue The vailable clk_cntl is used uninitialized, so initialize it to fix intree build issue. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index 07f26968a598a..ad08db2887687 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1263,7 +1263,7 @@ void kgd_gfx_v9_override_core_cg(struct amdgpu_device *adev, uint32_t value, uint32_t inst) { - uint32_t clk_cntl; + uint32_t clk_cntl = 0; mutex_lock(&adev->grbm_idx_mutex); amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); From e87692882d0512dc0fe01a6bc3d1878f020e32f9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 20 May 2024 10:57:42 +0800 Subject: [PATCH 1262/2653] drm/amdkcl: wrap code under macro HAVE_PCI_DRIVER_DEV_GROUPS It's caused by 7535d371a27cc788d8f41394a22e3fd492ee5d2c "drm/amd/pm: Add support for DPM policies" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 4b64851fdb42e..12d6b03529bbc 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -4453,6 +4453,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) dev_info(adev->dev, "overdrive feature is not supported\n"); } +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS if (amdgpu_dpm_get_pm_policy_info(adev, PP_PM_POLICY_NONE, NULL) != -EOPNOTSUPP) { ret = devm_device_add_group(adev->dev, @@ -4460,6 +4461,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) if (ret) goto err_out0; } +#endif adev->pm.sysfs_initialized = true; From 2ee32d9d8a8adbacf47f21a92cf91ad684b23b0b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 27 May 2024 10:54:39 +0800 Subject: [PATCH 1263/2653] drm/amdkcl: wrap code under macro HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY It's caused by e3a473ed04f7f1b061860437876a269073dc302d "drm/amd/display: Enable colorspace property for MST connectors" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 39a3cdbcb6a7d..48226ff0d0315 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -727,10 +727,12 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, &connector->base, dev->mode_config.tile_property, 0); + +#ifdef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY connector->colorspace_property = master->base.colorspace_property; if (connector->colorspace_property) drm_connector_attach_colorspace_property(connector); - +#endif drm_connector_set_path_property(connector, pathprop); /* From 1a611bc9019c60df4117c7383f4245283923cf6e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 27 May 2024 10:56:52 +0800 Subject: [PATCH 1264/2653] drm/amdkcl: fake macro fuction __counted_by() It's caused by d4fa69b7bd8a7c950a0b838ca0c1feef2bb03d84 "drm/amdgpu: silence UBSAN warning" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_compiler_attributes.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/kcl/kcl_compiler_attributes.h b/include/kcl/kcl_compiler_attributes.h index 34d035352059c..e844e68139479 100644 --- a/include/kcl/kcl_compiler_attributes.h +++ b/include/kcl/kcl_compiler_attributes.h @@ -10,4 +10,16 @@ #define fallthrough do {} while (0) /* fallthrough */ #endif +#ifndef __has_attribute +#define __has_attribute(x) 0 +#endif + +#ifndef __counted_by +#if __has_attribute(__counted_by__) +# define __counted_by(member) __attribute__((__counted_by__(member))) +#else +# define __counted_by(member) +#endif +#endif + #endif /* AMDKCL_COMPILER_ATTRIBUTES_H */ From fa88fb21f3ea9fa53c06c4cee314ba76336ee6b8 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 28 May 2024 14:45:06 +0800 Subject: [PATCH 1265/2653] drm/amd/display: add judge condition to fix intree build issue Due to dkms backport includes ASSERT macro, so add judge condition to avoid redefined macro. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- .../dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c index e17b5ceba4471..3bb835b5585ac 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c @@ -4,7 +4,9 @@ #include "lib_float_math.h" +#ifndef ASSERT #define ASSERT(condition) +#endif #define isNaN(number) ((number) != (number)) From ca799300559b6593d595364bead984d9d4cb1ec7 Mon Sep 17 00:00:00 2001 From: Bing Ma Date: Thu, 30 May 2024 14:07:15 -0700 Subject: [PATCH 1266/2653] drm/amdkfd: Fix various crash, hang and corruption issues for KFD SPM support 1. Need to convert drm_priv to amdgpu_vm when calling amdgpu_amdkfd_rlc_spm_*() functions. 2. Per RLC spec, ring_wptr = 0 and ring_rptr = 0 point to mmRLC_SPM_PERFMON_RING_BASE+0x20, change code accordingly. Signed-off-by: Bing Ma Reviewed-by: Harish Kasiviwanathan --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 26 ++++++++------------------ 1 file changed, 8 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 00da1cabcbd45..6480e9c49f608 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -39,7 +39,6 @@ struct kfd_spm_cntr { struct mutex spm_worker_mutex; u64 gpu_addr; u32 ring_size; - u32 ring_mask; u32 ring_rptr; u32 size_copied; u32 has_data_loss; @@ -63,7 +62,8 @@ static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) return -EFAULT; user_address = (uint64_t *)((uint64_t)spm->ubuf.user_addr + spm->size_copied); - ring_buf = (uint64_t *)((uint64_t)spm->cpu_addr + spm->ring_rptr); + // From RLC spec, ring_rptr = 0 points to spm->cpu_addr+0x20 + ring_buf = (uint64_t *)((uint64_t)spm->cpu_addr + spm->ring_rptr + 0x20); if (user_address == NULL) return -EFAULT; @@ -101,7 +101,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) int ret = 0; u32 ring_wptr; - ring_wptr = READ_ONCE(spm->cpu_addr[0]) & spm->ring_mask; + ring_wptr = READ_ONCE(spm->cpu_addr[0]); /* keep SPM ring buffer running */ if (!spm->has_user_buf || spm->is_user_buf_filled) { @@ -118,13 +118,6 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) if (spm->ring_rptr == ring_wptr) goto exit; - if ((spm->ring_rptr >= 0) && (spm->ring_rptr < 0x20)) { - /* - * First 8DW, only use for WritePtr, it is not Counter data - */ - spm->ring_rptr = 0x20; - } - if (ring_wptr > spm->ring_rptr) { size_to_copy = ring_wptr - spm->ring_rptr; ret = kfd_spm_data_copy(pdd, size_to_copy); @@ -139,7 +132,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) spm->ring_rptr = ring_wptr; goto exit; } - spm->ring_rptr = 0x20; + spm->ring_rptr = 0; size_to_copy = ring_wptr - spm->ring_rptr; if (!ret) ret = kfd_spm_data_copy(pdd, size_to_copy); @@ -192,12 +185,10 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device mutex_unlock(&pdd->spm_mutex); return -ENOMEM; } - mutex_unlock(&pdd->spm_mutex); /* git spm ring buffer 4M */ pdd->spm_cntr->ring_size = order_base_2(4 * 1024 * 1024/4); - pdd->spm_cntr->ring_size = (1 << pdd->spm_cntr->ring_size) * 4 - 0xff; - pdd->spm_cntr->ring_mask = pdd->spm_cntr->ring_size - 1; + pdd->spm_cntr->ring_size = (1 << pdd->spm_cntr->ring_size) * 4; pdd->spm_cntr->has_user_buf = false; ret = amdgpu_amdkfd_alloc_gtt_mem(adev, @@ -208,7 +199,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device if (ret) goto alloc_gtt_mem_failure; - ret = amdgpu_amdkfd_rlc_spm_acquire(adev, pdd->drm_priv, + ret = amdgpu_amdkfd_rlc_spm_acquire(adev, drm_priv_to_vm(pdd->drm_priv), pdd->spm_cntr->gpu_addr, pdd->spm_cntr->ring_size); /* @@ -233,12 +224,11 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device amdgpu_amdkfd_free_gtt_mem(adev, pdd->spm_cntr->spm_obj); alloc_gtt_mem_failure: - mutex_lock(&pdd->spm_mutex); kfree(pdd->spm_cntr); pdd->spm_cntr = NULL; - mutex_unlock(&pdd->spm_mutex); out: + mutex_unlock(&pdd->spm_mutex); return ret; } @@ -259,7 +249,7 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device flush_work(&pdd->spm_work); wake_up_all(&pdd->spm_cntr->spm_buf_wq); - amdgpu_amdkfd_rlc_spm_release(adev, pdd->drm_priv); + amdgpu_amdkfd_rlc_spm_release(adev, drm_priv_to_vm(pdd->drm_priv)); amdgpu_amdkfd_free_gtt_mem(adev, pdd->spm_cntr->spm_obj); spin_lock_irqsave(&pdd->spm_irq_lock, flags); From c4ca934bdcaa09c65e4a89855cd3fae56ff24538 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 13 Jun 2024 13:39:28 +0800 Subject: [PATCH 1267/2653] drm/amdkcl: Test drm_atomic_plane_enabling() is available It's caused by 1d0c9ded451944ef616149be5fe4a7d9a9d428da "drm/amd/display: Introduce overlay cursor mode" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm_atomic_plane_enabling.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_atomic_helper.h | 16 ++++++++++++++++ 4 files changed, 36 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_atomic_plane_enabling.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 79f02869cafc8..e3d7945fe704e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -179,6 +179,9 @@ /* drm_atomic_helper_calc_timestamping_constants() is available */ #define HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS 1 +/* drm_atomic_plane_enabling() is available */ +#define HAVE_DRM_ATOMIC_PLANE_ENABLING 1 + /* drm_client_register() is available */ #define HAVE_DRM_CLIENT_REGISTER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_atomic_plane_enabling.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_plane_enabling.m4 new file mode 100644 index 0000000000000..5fe466630d8dd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_plane_enabling.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.2-rc6-1230-g169b9182f192 +dnl # drm/atomic-helper: Add atomic_enable plane-helper callback +dnl # +AC_DEFUN([AC_AMDGPU_DRM_ATOMIC_PLANE_ENABLING], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_atomic_plane_enabling(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_ATOMIC_PLANE_ENABLING, 1, + [drm_atomic_plane_enabling() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 01d7f526f7405..b7ca9c962d119 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -91,6 +91,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MODE_INIT AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS + AC_AMDGPU_DRM_ATOMIC_PLANE_ENABLING AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC diff --git a/include/kcl/kcl_drm_atomic_helper.h b/include/kcl/kcl_drm_atomic_helper.h index 7bedeace08ad0..3af6d075cbe99 100644 --- a/include/kcl/kcl_drm_atomic_helper.h +++ b/include/kcl/kcl_drm_atomic_helper.h @@ -58,4 +58,20 @@ void __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, void drm_atomic_helper_calc_timestamping_constants(struct drm_atomic_state *state); #endif +#ifndef HAVE_DRM_ATOMIC_PLANE_ENABLING +static inline bool drm_atomic_plane_enabling(struct drm_plane_state *old_plane_state, + struct drm_plane_state *new_plane_state) +{ + /* + * When enabling a plane, CRTC and FB should always be set together. + * Anything else should be considered a bug in the atomic core, so we + * gently warn about it. + */ + WARN_ON((!new_plane_state->crtc && new_plane_state->fb) || + (new_plane_state->crtc && !new_plane_state->fb)); + + return !old_plane_state->crtc && new_plane_state->crtc; +} +#endif + #endif From c15b19e3bf34d5498bc6029e858ff27a83d675a1 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Mon, 17 Jun 2024 14:41:40 -0400 Subject: [PATCH 1268/2653] drm/amdkfd: remove gfx(9, 4, 1) pc sampling support Since it is not stable on stress test. Signed-off-by: James Zhu Reviewed-by: Felix Kuehling Reviewed-by: Vladimir Indic Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 72042277cc2b8..de91e4e53df6a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -36,7 +36,6 @@ const struct kfd_pc_sample_info sample_info_hosttrap_9_0_0 = { 0, 1, ~0ULL, 0, KFD_IOCTL_PCS_METHOD_HOSTTRAP, KFD_IOCTL_PCS_TYPE_TIME_US }; struct supported_pc_sample_info supported_formats[] = { - { IP_VERSION(9, 4, 1), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, }; From 3b9799d806c26d0b0cb093fe21845a349f85b80f Mon Sep 17 00:00:00 2001 From: James Zhu Date: Mon, 17 Jun 2024 15:12:30 -0400 Subject: [PATCH 1269/2653] drm/amdkfd: use version field to pass back pc sampling revision temporarily not for upstream. -v2: fix typo -v3: rename kfd_ioctl_pc_sample_args "reserved" to "version" Signed-off-by: James Zhu Reviewed-by: Felix Kuehling Reviewed-by: Vladimir Indic Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 11 +++++++++++ include/uapi/linux/kfd_ioctl.h | 2 +- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index de91e4e53df6a..435ebba8c0de7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -27,6 +27,14 @@ #include "kfd_debug.h" #include "kfd_device_queue_manager.h" +/* + * PC Sampling revision change log + * + * 0.1 - Initial revision + */ +#define KFD_IOCTL_PCS_MAJOR_VERSION 0 +#define KFD_IOCTL_PCS_MINOR_VERSION 1 + struct supported_pc_sample_info { uint32_t ip_version; const struct kfd_pc_sample_info *sample_info; @@ -142,6 +150,9 @@ static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, int i; const uint32_t user_num_sample_info = user_args->num_sample_info; + /* use version field to pass back pc sampling revision temporarily, not for upstream */ + user_args->version = KFD_IOCTL_PCS_MAJOR_VERSION << 16 | KFD_IOCTL_PCS_MINOR_VERSION; + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version) num_method++; diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 7649c334dedb5..d0fbe5423e35d 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1722,7 +1722,7 @@ struct kfd_ioctl_pc_sample_args { __u32 gpu_id; __u32 trace_id; __u32 flags; /* kfd_ioctl_pcs_query flags */ - __u32 reserved; + __u32 version; }; #define AMDKFD_IOCTL_BASE 'K' From 7fbf51f155318ccba88a10594ae75f059ff12c93 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 26 Jun 2024 11:06:09 +0800 Subject: [PATCH 1270/2653] drm/amdkcl: wrap code under macro HAVE_KFIFO_PUT_NON_POINTER It's caused by 1470f94093b4b2ba5760b18fbd0e105b862af165 "drm/amdgpu: add gpu reset check and exception handling" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 7985941728bfd..2ed3059a92a58 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3444,6 +3444,7 @@ static int amdgpu_ras_poison_creation_handler(struct amdgpu_device *adev, return 0; } +#ifdef HAVE_KFIFO_PUT_NON_POINTER static void amdgpu_ras_clear_poison_fifo(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); @@ -3498,6 +3499,7 @@ static int amdgpu_ras_poison_consumption_handler(struct amdgpu_device *adev, return 0; } +#endif static int amdgpu_ras_page_retirement_thread(void *param) { From 649ba9ad5d43c5043fce3177863cd0c5b211222f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 13 Jun 2024 13:28:41 +0800 Subject: [PATCH 1271/2653] drm/amdkcl: fake macros DP_LINK_BW_{10/13_5/20} It's caused by 13ba1f22181d90f4d62f9103351581b94d2442b2 "drm/amd/display: Refactor function dm_dp_mst_is_port_support_mode()" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_drm_dp.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/kcl/kcl_drm_dp.h b/include/kcl/kcl_drm_dp.h index 25c848be0df94..7f3607f89c6a4 100644 --- a/include/kcl/kcl_drm_dp.h +++ b/include/kcl/kcl_drm_dp.h @@ -76,4 +76,12 @@ #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250 #endif +/* v5.9-rc5-1031-g7d56927efac7 * + * drm/dp: add a number of DP 2.0 DPCD definitions */ +#ifndef DP_LINK_BW_10 +#define DP_LINK_BW_10 0x01 /* 2.0 128b/132b Link Layer */ +#define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b Link Layer */ +#define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */ +#endif + #endif \ No newline at end of file From 280827e92314514066d773d0991c9dbbcc864055 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 27 Jun 2024 16:46:37 +0800 Subject: [PATCH 1272/2653] drm/amdkcl: wrap code under macro HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS It's caused by 583ed0fe6bff86af2ce28a451f31cfa0c36013d1 "drm/amd/display: Introduce overlay cursor mode" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 2ef798c2c3a07..473fea6e16cc9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1304,8 +1304,12 @@ static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, return -EINVAL; } +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS new_plane_state = drm_atomic_get_new_plane_state(state, plane); new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); +#else + new_crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); +#endif dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); /* Reject overlay cursors for now*/ if (!flip && dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) From c3c4cb302d78d3cbb7aa8dc0f871ac561d7ea552 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 1 Jul 2024 16:28:43 +0800 Subject: [PATCH 1273/2653] drm/amdkcl: wrap code under macro HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE It's caused by f12e6db4a019bcb24dc99a909534dec35bcdd408 "drm/amd/display: Fix refresh rate range for some panel" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 -- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3bb10a71b9be3..9c1d873a83bd5 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12705,6 +12705,7 @@ static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, return ret; } +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE static void parse_edid_displayid_vrr(struct drm_connector *connector, const struct edid *edid) { @@ -12747,6 +12748,7 @@ static void parse_edid_displayid_vrr(struct drm_connector *connector, j++; } } +#endif static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, const struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) @@ -12868,10 +12870,12 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE /* Some eDP panels only have the refresh rate range info in DisplayID */ if ((connector->display_info.monitor_range.min_vfreq == 0 || connector->display_info.monitor_range.max_vfreq == 0)) parse_edid_displayid_vrr(connector, edid); +#endif if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || sink->sink_signal == SIGNAL_TYPE_EDP)) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 473fea6e16cc9..e3b8c75f12216 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -168,12 +168,10 @@ static void amdgpu_dm_plane_add_modifier(uint64_t **mods, uint64_t *size, uint64 *size += 1; } -#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static bool amdgpu_dm_plane_modifier_has_dcc(uint64_t modifier) { return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); } -#endif static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier) { From 94253ede771fef0dffb2f5856f3365908d8d91dc Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 1 Jul 2024 16:27:27 +0800 Subject: [PATCH 1274/2653] drm/amdkcl: fake macro AMD_FMT_MOD_TILE_GFX12_* It's caused by 2146fa1d796c804c337ea2fee8f2628bda4eb2ab "drm/amdgpu/display: add all gfx12 modifiers" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_drm_fourcc.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h index 9b1a99ec6d52b..cc36737aafae0 100644 --- a/include/kcl/kcl_drm_fourcc.h +++ b/include/kcl/kcl_drm_fourcc.h @@ -233,4 +233,13 @@ #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ #endif +#ifndef AMD_FMT_MOD_TILE_GFX12_256B_2D +#define AMD_FMT_MOD_TILE_GFX12_256B_2D 1 +#define AMD_FMT_MOD_TILE_GFX12_4K_2D 2 +#endif + +#ifndef AMD_FMT_MOD_TILE_GFX12_256K_2D +#define AMD_FMT_MOD_TILE_GFX12_256K_2D 4 +#endif + #endif /* KCL_KCL_DRM_FOURCC_H */ From f574b56f5084e2d2a203556252801376609838e8 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 25 Jun 2024 11:00:46 +0530 Subject: [PATCH 1275/2653] drm/amd/pm: Add phase detect control support Add support to tune phase detect parameters. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/include/kgd_pp_interface.h | 9 ++++ drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 53 +++++++++++++++++++ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 35 ++++++++++++ 3 files changed, 97 insertions(+) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index e2b1ea7467b09..5a2ccc9df4a5b 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -299,6 +299,15 @@ enum pp_policy_soc_pstate { #define PP_POLICY_MAX_LEVELS 5 +enum pp_pm_phase_det_param_id { + PP_PM_PHASE_DET_LO_FREQ = 0, + PP_PM_PHASE_DET_HI_FREQ = 1, + PP_PM_PHASE_DET_THRESH = 2, + PP_PM_PHASE_DET_ALPHA = 3, + PP_PM_PHASE_DET_HYST = 4, + PP_PM_PHASE_DET_ALL = 5, +}; + #define PP_GROUP_MASK 0xF0000000 #define PP_GROUP_SHIFT 28 diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 756afe78a6e5a..fab694350b7ed 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -4067,3 +4067,56 @@ int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask) return 0; } + +int smu_set_phase_det_param(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, uint32_t val) +{ + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !pd_ctl) + return -EOPNOTSUPP; + + if (!pd_ctl->ops || !pd_ctl->ops->set) + return -EOPNOTSUPP; + + if (pd_ctl->status == SMU_PHASE_DET_DISABLED) + return -EPERM; + + return pd_ctl->ops->set(smu, id, val); +} + +int smu_get_phase_det_param(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, uint32_t *val) +{ + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !pd_ctl) + return -EOPNOTSUPP; + + if (!pd_ctl->ops || !pd_ctl->ops->get) + return -EOPNOTSUPP; + + return pd_ctl->ops->get(smu, id, val); +} + +int smu_phase_det_enable(struct smu_context *smu, bool enable) +{ + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !pd_ctl) + return -EOPNOTSUPP; + + if (!pd_ctl->ops || !pd_ctl->ops->enable) + return -EOPNOTSUPP; + + if (pd_ctl->status == SMU_PHASE_DET_DISABLED) + return -EPERM; + + return pd_ctl->ops->enable(smu, enable); +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index b52e194397e2e..b0fefdbdf2f2f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -383,6 +383,34 @@ struct smu_dpm_policy_ctxt { unsigned long policy_mask; }; +struct smu_phase_det_params { + uint32_t freq_hi; + uint32_t freq_lo; + uint32_t thresh; + uint32_t hyst; + uint32_t alpha; +}; + +struct smu_phase_det_ops { + int (*set)(struct smu_context *smu, enum pp_pm_phase_det_param_id id, + uint32_t val); + int (*get)(struct smu_context *smu, enum pp_pm_phase_det_param_id id, + uint32_t *val); + int (*enable)(struct smu_context *smu, bool enable); +}; + +enum phase_det_state { + SMU_PHASE_DET_OFF = 0, + SMU_PHASE_DET_ON = 1, + SMU_PHASE_DET_DISABLED = -1, +}; + +struct smu_phase_det_ctl { + struct smu_phase_det_params params; + struct smu_phase_det_ops *ops; + enum phase_det_state status; +}; + struct smu_dpm_context { uint32_t dpm_context_size; void *dpm_context; @@ -394,6 +422,7 @@ struct smu_dpm_context { struct smu_power_state *dpm_current_power_state; struct mclock_latency_table *mclk_latency_table; struct smu_dpm_policy_ctxt *dpm_policies; + struct smu_phase_det_ctl *pd_ctl; }; struct smu_power_gate { @@ -1678,5 +1707,11 @@ int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, ssize_t smu_get_pm_policy_info(struct smu_context *smu, enum pp_pm_policy p_type, char *sysbuf); +int smu_set_phase_det_param(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, uint32_t val); +int smu_get_phase_det_param(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, uint32_t *val); +int smu_phase_det_enable(struct smu_context *smu, bool enable); + #endif #endif From 7095bef36603c928e661fc2970a90c8e2eb16b93 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 25 Jun 2024 16:35:36 +0530 Subject: [PATCH 1276/2653] drm/amd/pm: Add debugfs controls for phase detect Add debugfs nodes for enabling/disabling and tuning parameters used in phase detect. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 8 ++ drivers/gpu/drm/amd/pm/amdgpu_pm.c | 1 + drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 1 + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 96 +++++++++++++++++++ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 1 + 5 files changed, 107 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index 71d986dd7a6e8..597e62ff3d541 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -2068,3 +2068,11 @@ ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id, return ret; } + +void amdgpu_dpm_phase_det_debugfs_init(struct amdgpu_device *adev) +{ + if (!is_support_sw_smu(adev)) + return; + + amdgpu_smu_phase_det_debugfs_init(adev); +} diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 12d6b03529bbc..dbaebe1415e25 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -4756,5 +4756,6 @@ void amdgpu_debugfs_pm_init(struct amdgpu_device *adev) adev->pm.smu_prv_buffer_size); amdgpu_dpm_stb_debug_fs_init(adev); + amdgpu_dpm_phase_det_debugfs_init(adev); #endif } diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h index 768317ee1486b..37934716e972a 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h @@ -612,6 +612,7 @@ ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, enum pp_pm_policy p_type, char *buf); int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask); bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev); +void amdgpu_dpm_phase_det_debugfs_init(struct amdgpu_device *adev); int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask); #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index fab694350b7ed..0317da047e48f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -4120,3 +4120,99 @@ int smu_phase_det_enable(struct smu_context *smu, bool enable) return pd_ctl->ops->enable(smu, enable); } + +#if defined(CONFIG_DEBUG_FS) + +static int smu_phase_det_debugfs_status(void *data, u64 *val) +{ + struct smu_context *smu = (struct smu_context *)data; + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + + *val = pd_ctl->status; + + return 0; +} + +static int smu_phase_det_debugfs_enable(void *data, u64 val) +{ + struct smu_context *smu = (struct smu_context *)data; + struct amdgpu_device *adev = smu->adev; + + if (amdgpu_in_reset(adev) || adev->in_suspend) + return -EPERM; + + return smu_phase_det_enable(smu, !!val); +} + +#define DEBUGFS_PHASE_DET_FOPS(param) \ + static int smu_phase_det_fops_##param##_get(void *data, u64 *val) \ + { \ + struct smu_context *smu = (struct smu_context *)data; \ + int r; \ + u32 v; \ + \ + r = smu_get_phase_det_param(smu, PP_PM_PHASE_DET_##param, &v); \ + *val = v; \ + return r; \ + } \ + \ + static int smu_phase_det_fops_##param##_set(void *data, u64 val) \ + { \ + struct smu_context *smu = (struct smu_context *)data; \ + struct amdgpu_device *adev = smu->adev; \ + \ + if (amdgpu_in_reset(adev) || adev->in_suspend) \ + return -EPERM; \ + \ + return smu_set_phase_det_param(smu, PP_PM_PHASE_DET_##param, \ + (u32)val); \ + } \ + DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_##param, \ + smu_phase_det_fops_##param##_get, \ + smu_phase_det_fops_##param##_set, "%llu\n") + +DEBUGFS_PHASE_DET_FOPS(LO_FREQ); +DEBUGFS_PHASE_DET_FOPS(HI_FREQ); +DEBUGFS_PHASE_DET_FOPS(THRESH); +DEBUGFS_PHASE_DET_FOPS(ALPHA); +DEBUGFS_PHASE_DET_FOPS(HYST); + +DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, + smu_phase_det_debugfs_enable, "%llu\n"); + +#define DEBUGFS_CREATE_PHASE_DET_ATTR(name, param) \ + debugfs_create_file(#name, 0644, dir, smu, &smu_phase_det_fops_##param) + +#define AMDGPU_SMU_PHASE_DET "smu_phase_detect" +#endif + +void amdgpu_smu_phase_det_debugfs_init(struct amdgpu_device *adev) +{ +#if defined(CONFIG_DEBUG_FS) + + struct smu_context *smu = adev->powerplay.pp_handle; + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + struct dentry *dir; + + pd_ctl = dpm_ctxt->pd_ctl; + + if (!smu || !pd_ctl) + return; + + dir = debugfs_create_dir(AMDGPU_SMU_PHASE_DET, + adev_to_drm(adev)->primary->debugfs_root); + + debugfs_create_file("enable", 0644, dir, smu, &smu_phase_det_fops_en); + + DEBUGFS_CREATE_PHASE_DET_ATTR(freq_lo, LO_FREQ); + DEBUGFS_CREATE_PHASE_DET_ATTR(freq_hi, HI_FREQ); + DEBUGFS_CREATE_PHASE_DET_ATTR(threshold, THRESH); + DEBUGFS_CREATE_PHASE_DET_ATTR(alpha, ALPHA); + DEBUGFS_CREATE_PHASE_DET_ATTR(hyst, HYST); + +#endif +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index b0fefdbdf2f2f..686ad42f9ae0a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -1712,6 +1712,7 @@ int smu_set_phase_det_param(struct smu_context *smu, int smu_get_phase_det_param(struct smu_context *smu, enum pp_pm_phase_det_param_id id, uint32_t *val); int smu_phase_det_enable(struct smu_context *smu, bool enable); +void amdgpu_smu_phase_det_debugfs_init(struct amdgpu_device *adev); #endif #endif From 77299735523bea06d68612d6298595162e61ef30 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 26 Jun 2024 13:15:32 +0530 Subject: [PATCH 1277/2653] drm/amd/pm: Add phase detect support to SMUv13.0.6 Add support for enabling phase detect and tuning params for SMUv13.0.6 SOCs. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- .../pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 6 + drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 6 + .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 1 + .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 149 +++++++++++++++++- 4 files changed, 161 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h index 41f2683136134..32131debe242f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h @@ -93,6 +93,12 @@ #define PPSMC_MSG_SelectPLPDMode 0x40 #define PPSMC_MSG_RmaDueToBadPageThreshold 0x43 #define PPSMC_MSG_SetThrottlingPolicy 0x44 +#define PPSMC_MSG_SetPhsDetWRbwThreshold 0x45 +#define PPSMC_MSG_SetPhsDetWRbwFreqHigh 0x46 +#define PPSMC_MSG_SetPhsDetWRbwFreqLow 0x47 +#define PPSMC_MSG_SetPhsDetWRbwHystDown 0x48 +#define PPSMC_MSG_SetPhsDetWRbwAlpha 0x49 +#define PPSMC_MSG_SetPhsDetOnOff 0x4A #define PPSMC_MSG_ResetSDMA 0x4D #define PPSMC_MSG_ResetVCN 0x4E #define PPSMC_MSG_GetStaticMetricsTable 0x59 diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h index d7a9e41820fae..65035c498fa9c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -276,6 +276,12 @@ __SMU_DUMMY_MAP(SetThrottlingPolicy), \ __SMU_DUMMY_MAP(MALLPowerController), \ __SMU_DUMMY_MAP(MALLPowerState), \ + __SMU_DUMMY_MAP(SetPhsDetWRbwThreshold), \ + __SMU_DUMMY_MAP(SetPhsDetWRbwFreqHigh), \ + __SMU_DUMMY_MAP(SetPhsDetWRbwFreqLow), \ + __SMU_DUMMY_MAP(SetPhsDetWRbwHystDown), \ + __SMU_DUMMY_MAP(SetPhsDetWRbwAlpha), \ + __SMU_DUMMY_MAP(SetPhsDetOnOff), \ __SMU_DUMMY_MAP(ResetSDMA), \ __SMU_DUMMY_MAP(ResetVCN), \ __SMU_DUMMY_MAP(GetStaticMetricsTable), diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 19628827f15a0..b8e6169481c4d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -531,6 +531,7 @@ int smu_v13_0_fini_smc_tables(struct smu_context *smu) smu_table->watermarks_table = NULL; smu_table->metrics_time = 0; + kfree(smu_dpm->pd_ctl); kfree(smu_dpm->dpm_policies); kfree(smu_dpm->dpm_context); kfree(smu_dpm->golden_dpm_context); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 9cc294f4708bc..ed04edb79cd9c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -178,6 +178,12 @@ static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COU MSG_MAP(ResetSDMA, PPSMC_MSG_ResetSDMA, 0), MSG_MAP(ResetVCN, PPSMC_MSG_ResetVCN, 0), MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 0), + MSG_MAP(SetPhsDetWRbwThreshold, PPSMC_MSG_SetPhsDetWRbwThreshold, 0), + MSG_MAP(SetPhsDetWRbwFreqHigh, PPSMC_MSG_SetPhsDetWRbwFreqHigh, 0), + MSG_MAP(SetPhsDetWRbwFreqLow, PPSMC_MSG_SetPhsDetWRbwFreqLow, 0), + MSG_MAP(SetPhsDetWRbwHystDown, PPSMC_MSG_SetPhsDetWRbwHystDown, 0), + MSG_MAP(SetPhsDetWRbwAlpha, PPSMC_MSG_SetPhsDetWRbwAlpha, 0), + MSG_MAP(SetPhsDetOnOff, PPSMC_MSG_SetPhsDetOnOff, 0), }; // clang-format on @@ -620,6 +626,112 @@ static int smu_v13_0_6_select_plpd_policy(struct smu_context *smu, int level) return ret; } +static int smu_v13_0_6_phase_det_set(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, + uint32_t val) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + uint32_t *param; + int r, msg_id; + + pd_ctl = smu_dpm->pd_ctl; + if (!pd_ctl) + return -EINVAL; + + switch (id) { + case PP_PM_PHASE_DET_LO_FREQ: + msg_id = SMU_MSG_SetPhsDetWRbwFreqLow; + param = &pd_ctl->params.freq_lo; + break; + case PP_PM_PHASE_DET_HI_FREQ: + msg_id = SMU_MSG_SetPhsDetWRbwFreqHigh; + param = &pd_ctl->params.freq_hi; + break; + case PP_PM_PHASE_DET_THRESH: + msg_id = SMU_MSG_SetPhsDetWRbwThreshold; + param = &pd_ctl->params.thresh; + break; + case PP_PM_PHASE_DET_ALPHA: + msg_id = SMU_MSG_SetPhsDetWRbwAlpha; + param = &pd_ctl->params.alpha; + break; + case PP_PM_PHASE_DET_HYST: + msg_id = SMU_MSG_SetPhsDetWRbwHystDown; + param = &pd_ctl->params.hyst; + break; + default: + return -EINVAL; + } + + r = smu_cmn_send_smc_msg_with_param(smu, msg_id, val, NULL); + if (!r) + *param = val; + + return r; +} + +static int smu_v13_0_6_phase_det_get(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, + uint32_t *val) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = smu_dpm->pd_ctl; + if (!pd_ctl || !val) + return -EINVAL; + + switch (id) { + case PP_PM_PHASE_DET_LO_FREQ: + *val = pd_ctl->params.freq_lo; + break; + case PP_PM_PHASE_DET_HI_FREQ: + *val = pd_ctl->params.freq_hi; + break; + case PP_PM_PHASE_DET_THRESH: + *val = pd_ctl->params.thresh; + break; + case PP_PM_PHASE_DET_ALPHA: + *val = pd_ctl->params.alpha; + break; + case PP_PM_PHASE_DET_HYST: + *val = pd_ctl->params.hyst; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int smu_v13_0_6_phase_det_enable(struct smu_context *smu, bool enable) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + int r; + + pd_ctl = smu_dpm->pd_ctl; + r = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPhsDetOnOff, enable, + NULL); + + if (!r) { + pd_ctl->status = enable ? SMU_PHASE_DET_ON : SMU_PHASE_DET_OFF; + } else { + dev_warn(smu->adev->dev, "Phase detect %s failed", + enable ? "enable" : "disable"); + pd_ctl->status = SMU_PHASE_DET_DISABLED; + } + + return r; +} + +static struct smu_phase_det_ops smu_v13_0_6_pd_ops = { + .set = smu_v13_0_6_phase_det_set, + .get = smu_v13_0_6_phase_det_get, + .enable = smu_v13_0_6_phase_det_enable, +}; + static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu) { struct smu_dpm_context *smu_dpm = &smu->smu_dpm; @@ -638,6 +750,17 @@ static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu) return -ENOMEM; } + smu_dpm->pd_ctl = kzalloc(sizeof(struct smu_phase_det_ctl), GFP_KERNEL); + if (!smu_dpm->pd_ctl) { + kfree(smu_dpm->dpm_policies); + kfree(smu_dpm->dpm_context); + return -ENOMEM; + } + smu_dpm->pd_ctl->ops = &smu_v13_0_6_pd_ops; + smu_dpm->pd_ctl->status = SMU_PHASE_DET_OFF; + /* Init to 0xFF to indicate that present values are unknown */ + memset(&smu_dpm->pd_ctl->params, 0xFF, sizeof(struct smu_phase_det_params)); + if (!(smu->adev->flags & AMD_IS_APU)) { policy = &(smu_dpm->dpm_policies->policies[0]); @@ -989,6 +1112,7 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; struct smu_table_context *smu_table = &smu->smu_table; struct smu_13_0_dpm_table *dpm_table = NULL; + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; struct PPTable_t *pptable = (struct PPTable_t *)smu_table->driver_pptable; uint32_t gfxclkmin, gfxclkmax, levels; @@ -1021,6 +1145,12 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) ~BIT(PP_PM_POLICY_SOC_PSTATE); } + if (smu_dpm->pd_ctl && !(smu->adev->flags & AMD_IS_APU) && + (smu->smc_fw_version < 0x00556E00)) { + kfree(smu_dpm->pd_ctl); + smu_dpm->pd_ctl = NULL; + } + smu_v13_0_6_pm_policy_init(smu); /* gfxclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.gfx_table; @@ -3152,6 +3282,23 @@ static int smu_v13_0_6_reset_sdma(struct smu_context *smu, uint32_t inst_mask) return ret; } +static int smu_v13_0_6_post_init(struct smu_context *smu) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + bool enable; + + pd_ctl = smu_dpm->pd_ctl; + + if (!pd_ctl || pd_ctl->status == SMU_PHASE_DET_DISABLED) + return 0; + + enable = (pd_ctl->status == SMU_PHASE_DET_ON) ? true : false; + smu_v13_0_6_phase_det_enable(smu, enable); + + return 0; +} + static int smu_v13_0_6_reset_vcn(struct smu_context *smu, uint32_t inst_mask) { int ret = 0; @@ -3164,7 +3311,6 @@ static int smu_v13_0_6_reset_vcn(struct smu_context *smu, uint32_t inst_mask) return ret; } - static int mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable) { struct smu_context *smu = adev->powerplay.pp_handle; @@ -3839,6 +3985,7 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { .send_rma_reason = smu_v13_0_6_send_rma_reason, .reset_sdma = smu_v13_0_6_reset_sdma, .reset_sdma_is_supported = smu_v13_0_6_reset_sdma_is_supported, + .post_init = smu_v13_0_6_post_init, .dpm_reset_vcn = smu_v13_0_6_reset_vcn, }; From 6729028f80888d80435a6bc493391824126ff23b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 8 Jul 2024 16:14:55 +0800 Subject: [PATCH 1278/2653] drm/amdkcl: wrap code under macro DEFINE_DEBUGFS_ATTRIBUTE It's caused by 4134c8ebf636e6d2d5b43c1a246b21d833bf9651 "drm/amd/pm: Add debugfs controls for phase detect" Signed-off-by: Bob Zhou Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 34 +++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 0317da047e48f..f45409778be46 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -4147,6 +4147,7 @@ static int smu_phase_det_debugfs_enable(void *data, u64 val) return smu_phase_det_enable(smu, !!val); } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE #define DEBUGFS_PHASE_DET_FOPS(param) \ static int smu_phase_det_fops_##param##_get(void *data, u64 *val) \ { \ @@ -4173,6 +4174,34 @@ static int smu_phase_det_debugfs_enable(void *data, u64 val) DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_##param, \ smu_phase_det_fops_##param##_get, \ smu_phase_det_fops_##param##_set, "%llu\n") +#else +#define DEBUGFS_PHASE_DET_FOPS(param) \ + static int smu_phase_det_fops_##param##_get(void *data, u64 *val) \ + { \ + struct smu_context *smu = (struct smu_context *)data; \ + int r; \ + u32 v; \ + \ + r = smu_get_phase_det_param(smu, PP_PM_PHASE_DET_##param, &v); \ + *val = v; \ + return r; \ + } \ + \ + static int smu_phase_det_fops_##param##_set(void *data, u64 val) \ + { \ + struct smu_context *smu = (struct smu_context *)data; \ + struct amdgpu_device *adev = smu->adev; \ + \ + if (amdgpu_in_reset(adev) || adev->in_suspend) \ + return -EPERM; \ + \ + return smu_set_phase_det_param(smu, PP_PM_PHASE_DET_##param, \ + (u32)val); \ + } \ + DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_##param, \ + smu_phase_det_fops_##param##_get, \ + smu_phase_det_fops_##param##_set, "%llu\n") +#endif DEBUGFS_PHASE_DET_FOPS(LO_FREQ); DEBUGFS_PHASE_DET_FOPS(HI_FREQ); @@ -4180,8 +4209,13 @@ DEBUGFS_PHASE_DET_FOPS(THRESH); DEBUGFS_PHASE_DET_FOPS(ALPHA); DEBUGFS_PHASE_DET_FOPS(HYST); +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, smu_phase_det_debugfs_enable, "%llu\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, + smu_phase_det_debugfs_enable, "%llu\n"); +#endif #define DEBUGFS_CREATE_PHASE_DET_ATTR(name, param) \ debugfs_create_file(#name, 0644, dir, smu, &smu_phase_det_fops_##param) From 8c1a8fb30abe1a76b83ba6087977dab1c79eb4a8 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 9 Jul 2024 17:45:27 +0530 Subject: [PATCH 1279/2653] drm/amd/pm: Restrict phase detect to SMUv13.0.6 Phase detect controls are only available for SMUv13.0.6 dGPUs. Create control object only on those. Signed-off-by: Lijo Lazar Reviewed-by: Feifei Xu Reviewed-by: Hawking Zhang --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 28 +++++++++++-------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index ed04edb79cd9c..079ee29c7faf5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -750,17 +750,22 @@ static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu) return -ENOMEM; } - smu_dpm->pd_ctl = kzalloc(sizeof(struct smu_phase_det_ctl), GFP_KERNEL); - if (!smu_dpm->pd_ctl) { - kfree(smu_dpm->dpm_policies); - kfree(smu_dpm->dpm_context); - return -ENOMEM; - } - smu_dpm->pd_ctl->ops = &smu_v13_0_6_pd_ops; - smu_dpm->pd_ctl->status = SMU_PHASE_DET_OFF; - /* Init to 0xFF to indicate that present values are unknown */ - memset(&smu_dpm->pd_ctl->params, 0xFF, sizeof(struct smu_phase_det_params)); + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) && + !(smu->adev->flags & AMD_IS_APU)) { + smu_dpm->pd_ctl = + kzalloc(sizeof(struct smu_phase_det_ctl), GFP_KERNEL); + if (!smu_dpm->pd_ctl) { + kfree(smu_dpm->dpm_policies); + kfree(smu_dpm->dpm_context); + return -ENOMEM; + } + smu_dpm->pd_ctl->ops = &smu_v13_0_6_pd_ops; + smu_dpm->pd_ctl->status = SMU_PHASE_DET_OFF; + /* Init to 0xFF to indicate that present values are unknown */ + memset(&smu_dpm->pd_ctl->params, 0xFF, + sizeof(struct smu_phase_det_params)); + } if (!(smu->adev->flags & AMD_IS_APU)) { policy = &(smu_dpm->dpm_policies->policies[0]); @@ -1145,8 +1150,7 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) ~BIT(PP_PM_POLICY_SOC_PSTATE); } - if (smu_dpm->pd_ctl && !(smu->adev->flags & AMD_IS_APU) && - (smu->smc_fw_version < 0x00556E00)) { + if (smu_dpm->pd_ctl && (smu->smc_fw_version < 0x00556E00)) { kfree(smu_dpm->pd_ctl); smu_dpm->pd_ctl = NULL; } From 7a7697e0141d55f746a422103e25d28038d9fa5a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 18 Jul 2024 15:42:08 +0800 Subject: [PATCH 1280/2653] drm/amdkcl: cleanup dma-resv stuff Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 7 ++++--- drivers/gpu/drm/amd/dkms/pre-build.sh | 12 +++++------- 3 files changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 90398c82f9c30..64dd31cf1bc84 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -2,7 +2,7 @@ amdkcl-y += main.o kcl_common.o amdkcl-y += kcl_kernel_params.o -amdkcl-y += dma-buf/dma-resv.o +amdkcl-y += dma-buf/dma-resv.o kcl_dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_seq_file.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index dc92c2d10f23d..f2a2cdcbf3165 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -32,6 +32,10 @@ /* * Authors: Thomas Hellstrom */ + +/* Copied from drivers/dma-buf/dma-resv.c */ +#ifndef HAVE_DMA_RESV_FENCES + #include #include #include @@ -41,9 +45,6 @@ #include #include -/* Copied from drivers/dma-buf/dma-resv.c */ -#ifndef HAVE_DMA_RESV_FENCES - /** * DOC: Reservation Object Overview * diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 5f922ec16986c..ec0c41cd4411e 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -34,10 +34,12 @@ version_le () { source $KCL/files sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ - -e '/dma_resv_lockdep/,/subsys_initcall/d' $KCL/dma-buf/dma-resv.c + -e '/dma_resv_lockdep/,/subsys_initcall/d' \ + -e '1i\#ifdef HAVE_DMA_RESV_FENCES' \ + -e '$a\#endif' $KCL/dma-buf/dma-resv.c sed -i -e '/extern struct ww_class reservation_ww_class/i #include ' \ - -e '/struct dma_resv {/, /}/d' $INC/linux/dma-resv.h \ - -e '/struct dma_resv_iter {/, /}/d' $INC/linux/dma-resv.h \ + -e '/struct dma_resv {/, /}/d' \ + -e '/struct dma_resv_iter {/, /}/d' \ -e '/enum dma_resv_usage {/, /}/d' $INC/linux/dma-resv.h # add amd prefix to exported symbols @@ -86,7 +88,3 @@ if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then sed -i 's|\(CFLAGS_[A-Z_]*\)$(AMDDALPATH)/.*/\(.*\.o\)|\1\2|' $file done fi - -if ! grep -q 'define HAVE_DMA_RESV_FENCES' $SRC/config/config.h; then - sed -i 's|dma-buf/dma-resv.o|kcl_dma-resv.o|' amd/amdkcl/Makefile -fi From f6ec4055d86f0ad9d915b99f558b39ad90f01d55 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 1 Mar 2024 11:25:34 -0500 Subject: [PATCH 1281/2653] drm/amdkfd: add Host Trap Sampling support on gfx943 Add Host Trap Sampling support on gfx943. Signed-off-by: James Zhu Reviewed-by: Vladimir Indic Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c index 89a45a9218f3f..b9d226aa7b133 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c @@ -520,6 +520,17 @@ static uint32_t kgd_gfx_v9_4_3_hqd_sdma_get_doorbell(struct amdgpu_device *adev, return is_active ? doorbell_off >> 2 : 0; } +static uint32_t kgd_v9_4_3_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) +{ + return kgd_gfx_v9_trigger_pc_sample_trap(adev, vmid, 8, 4, + target_simd, target_wave_slot, method, inst); +} + const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_gfx_v9_4_3_set_pasid_vmid_mapping, @@ -555,5 +566,7 @@ const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .clear_address_watch = kgd_gfx_v9_4_3_clear_address_watch, .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, .hqd_reset = kgd_gfx_v9_hqd_reset, - .hqd_sdma_get_doorbell = kgd_gfx_v9_4_3_hqd_sdma_get_doorbell + .hqd_sdma_get_doorbell = kgd_gfx_v9_4_3_hqd_sdma_get_doorbell, + .trigger_pc_sample_trap = kgd_v9_4_3_trigger_pc_sample_trap, + .override_core_cg = kgd_gfx_v9_override_core_cg }; From d66436192c09ad526d865533d9b4ef5f6d7f3aa3 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 25 Jul 2024 13:21:23 -0400 Subject: [PATCH 1282/2653] drm/amdkfd: enable Host Trap PC sampling for gfx943 Enable Host Trap PC sampling for gfx943. Signed-off-by: James Zhu Reviewed-by: Vladimir Indic Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 435ebba8c0de7..c829676d631a6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -31,9 +31,10 @@ * PC Sampling revision change log * * 0.1 - Initial revision + * 0.2 - Support gfx9_4_3 Host Trap PC sampling */ #define KFD_IOCTL_PCS_MAJOR_VERSION 0 -#define KFD_IOCTL_PCS_MINOR_VERSION 1 +#define KFD_IOCTL_PCS_MINOR_VERSION 2 struct supported_pc_sample_info { uint32_t ip_version; @@ -45,6 +46,7 @@ const struct kfd_pc_sample_info sample_info_hosttrap_9_0_0 = { struct supported_pc_sample_info supported_formats[] = { { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, + { IP_VERSION(9, 4, 3), &sample_info_hosttrap_9_0_0 }, }; static int kfd_pc_sample_thread(void *param) From 53953bcd69489054627a9425699ebf25dd0bff46 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 30 Jul 2024 16:25:47 +0800 Subject: [PATCH 1283/2653] drm/amdkcl: fake drm_edid_{alloc/free/raw/valid}() It's caused by 1dc166feb7e808f16ec2289bf1da3adb7018248a "drm/amdgpu: convert bios_hardcoded_edid to drm_edid" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c | 95 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 9 ++ drivers/gpu/drm/amd/dkms/m4/drm_edid_alloc.m4 | 57 +++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_edid.h | 34 +++++++ 6 files changed, 197 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_edid_alloc.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 64dd31cf1bc84..3fbd585862102 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -8,7 +8,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_seq_file.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ kcl_fence.o kcl_reservation.o kcl_drm_cache.o \ - kcl_drm_fb.o kcl_drm_print.o \ + kcl_drm_fb.o kcl_drm_print.o kcl_drm_edid.o\ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c new file mode 100644 index 0000000000000..c5272121a0ab4 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation. + * + * Authors: + * Ramalingam C + */ +#include +#include + +#ifndef HAVE_DRM_EDID_MALLOC +static const struct drm_edid *__kcl_drm_edid_alloc(const void *edid, size_t size) +{ + struct drm_edid *drm_edid; + + if (!edid || !size || size < EDID_LENGTH) + return NULL; + + drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); + if (drm_edid) { + drm_edid->edid = edid; + drm_edid->size = size; + } + + return drm_edid; +} + +const struct drm_edid *_kcl_drm_edid_alloc(const void *edid, size_t size) +{ + const struct drm_edid *drm_edid; + + if (!edid || !size || size < EDID_LENGTH) + return NULL; + + edid = kmemdup(edid, size, GFP_KERNEL); + if (!edid) + return NULL; + + drm_edid = __kcl_drm_edid_alloc(edid, size); + if (!drm_edid) + kfree(edid); + + return drm_edid; +} +EXPORT_SYMBOL(_kcl_drm_edid_alloc); + +void _kcl_drm_edid_free(const struct drm_edid *drm_edid) +{ + if (!drm_edid) + return; + + kfree(drm_edid->edid); + kfree(drm_edid); +} +EXPORT_SYMBOL(_kcl_drm_edid_free); +#endif + +#ifndef HAVE_DRM_EDID_RAW +static int edid_extension_block_count(const struct edid *edid) +{ + return edid->extensions; +} + +static int edid_block_count(const struct edid *edid) +{ + return edid_extension_block_count(edid) + 1; +} + +static int edid_size_by_blocks(int num_blocks) +{ + return num_blocks * EDID_LENGTH; +} + +static int edid_size(const struct edid *edid) +{ + return edid_size_by_blocks(edid_block_count(edid)); +} + +const struct edid *_kcl_drm_edid_raw(const struct drm_edid *drm_edid) +{ + if (!drm_edid || !drm_edid->size) + return NULL; + + /* + * Do not return pointers where relying on EDID extension count would + * lead to buffer overflow. + */ + if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) + return NULL; + + return drm_edid->edid; +} +EXPORT_SYMBOL(_kcl_drm_edid_raw); +#endif + diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e3d7945fe704e..077e9c583ac57 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -488,9 +488,18 @@ /* drm_dsc_pps_payload_pack() is available */ #define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 +/* drm_edid_alloc() is available */ +#define HAVE_DRM_EDID_MALLOC 1 + /* drm_edid_override_connector_update() is available */ #define HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE 1 +/* drm_edid_raw() is available */ +#define HAVE_DRM_EDID_RAW 1 + +/* drm_edid_valid() is available */ +#define HAVE_DRM_EDID_VALID 1 + /* drm_exec() has 3 arguments */ #define HAVE_DRM_EXEC_INIT_3_ARGUMENTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_edid_alloc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_edid_alloc.m4 new file mode 100644 index 0000000000000..86301a9a861f4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_edid_alloc.m4 @@ -0,0 +1,57 @@ +dnl # +dnl # commit v5.18-rc5-1218-g6537f79a2aae +dnl # drm/edid: add new interfaces around struct drm_edid +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_MALLOC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_edid_alloc(NULL, 0); + ],[ + AC_DEFINE(HAVE_DRM_EDID_MALLOC, 1, + [drm_edid_alloc() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v5.19-rc2-380-g3d1ab66e043f +dnl # drm/edid: add drm_edid_raw() to access the raw EDID data +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_RAW], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_edid_raw(NULL); + ],[ + AC_DEFINE(HAVE_DRM_EDID_RAW, 1, + [drm_edid_raw() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v6.1-rc1-145-g6c9b3db70aad +dnl # drm/edid: add function for checking drm_edid validity +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_VALID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_edid_valid(NULL); + ],[ + AC_DEFINE(HAVE_DRM_EDID_VALID, 1, + [drm_edid_valid() is available]) + ]) + ]) +]) + + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_EDID], [ + AC_AMDGPU_DRM_EDID_MALLOC + AC_AMDGPU_DRM_EDID_RAW + AC_AMDGPU_DRM_EDID_VALID +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b7ca9c962d119..adc6a15b33808 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -194,6 +194,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB AC_AMDGPU_BITMAP_TO_ARR32 AC_AMDGPU_SHRINKER + AC_AMDGPU_STRUCT_DRM_EDID AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN AC_AMDGPU_ACPI_VIDEO_FUNCS diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h index 0e5b0fab8f8e3..05afadb754485 100644 --- a/include/kcl/kcl_drm_edid.h +++ b/include/kcl/kcl_drm_edid.h @@ -22,4 +22,38 @@ #define DRM_EDID_FEATURE_CONTINUOUS_FREQ (1 << 0) /* 1.4 */ #endif + +/* commit v5.18-rc5-1046-ge4ccf9a777d3 + drm/edid: add struct drm_edid container */ +#if !defined(HAVE_DRM_EDID_MALLOC) || !defined(HAVE_DRM_EDID_RAW) || !defined(HAVE_DRM_EDID_VALID) +struct drm_edid { + /* Size allocated for edid */ + size_t size; + const struct edid *edid; +}; +#endif + +#ifndef HAVE_DRM_EDID_MALLOC +const struct drm_edid *_kcl_drm_edid_alloc(const void *edid, size_t size); +void _kcl_drm_edid_free(const struct drm_edid *drm_edid); +#define drm_edid_alloc _kcl_drm_edid_alloc +#define drm_edid_free _kcl_drm_edid_free +#endif + +#ifndef HAVE_DRM_EDID_RAW +const struct edid *_kcl_drm_edid_raw(const struct drm_edid *drm_edid); +#define drm_edid_raw _kcl_drm_edid_raw +#endif + +#ifndef HAVE_DRM_EDID_VALID +static inline bool _kcl_drm_edid_valid(const struct drm_edid *drm_edid) +{ + if (!drm_edid) + return false; + + return drm_edid_is_valid(drm_edid->edid); +} +#define drm_edid_valid _kcl_drm_edid_valid +#endif + #endif From bfeb0f4d057986ea171b9e2e184a2e9d97957e90 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 15 Jul 2024 15:46:30 +0530 Subject: [PATCH 1284/2653] drm/amd/pm: Add phase detect residency support Add support to get phase detect residency through debugfs Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 39 +++++++++++++++++++ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 + 2 files changed, 41 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index f45409778be46..22472adc0893f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -4121,8 +4121,40 @@ int smu_phase_det_enable(struct smu_context *smu, bool enable) return pd_ctl->ops->enable(smu, enable); } +static int smu_phase_det_get_residency(struct smu_context *smu, uint32_t *res) +{ + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !pd_ctl) + return -EOPNOTSUPP; + + if (!pd_ctl->ops || !pd_ctl->ops->get_residency) + return -EOPNOTSUPP; + + if (pd_ctl->status == SMU_PHASE_DET_DISABLED) + return -EPERM; + + return pd_ctl->ops->get_residency(smu, res); +} + #if defined(CONFIG_DEBUG_FS) +static int smu_phase_det_debugfs_get_residency(void *data, u64 *val) +{ + struct smu_context *smu = (struct smu_context *)data; + uint32_t res; + int r; + + r = smu_phase_det_get_residency(smu, &res); + if (r) + return r; + *val = res; + + return 0; +} + static int smu_phase_det_debugfs_status(void *data, u64 *val) { struct smu_context *smu = (struct smu_context *)data; @@ -4217,6 +4249,9 @@ DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, smu_phase_det_debugfs_enable, "%llu\n"); #endif +DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_res, + smu_phase_det_debugfs_get_residency, NULL, "%llu\n"); + #define DEBUGFS_CREATE_PHASE_DET_ATTR(name, param) \ debugfs_create_file(#name, 0644, dir, smu, &smu_phase_det_fops_##param) @@ -4242,6 +4277,10 @@ void amdgpu_smu_phase_det_debugfs_init(struct amdgpu_device *adev) debugfs_create_file("enable", 0644, dir, smu, &smu_phase_det_fops_en); + if (pd_ctl->ops->get_residency) + debugfs_create_file("residency", 0444, dir, smu, + &smu_phase_det_fops_res); + DEBUGFS_CREATE_PHASE_DET_ATTR(freq_lo, LO_FREQ); DEBUGFS_CREATE_PHASE_DET_ATTR(freq_hi, HI_FREQ); DEBUGFS_CREATE_PHASE_DET_ATTR(threshold, THRESH); diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 686ad42f9ae0a..af7485ff8bd72 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -397,6 +397,7 @@ struct smu_phase_det_ops { int (*get)(struct smu_context *smu, enum pp_pm_phase_det_param_id id, uint32_t *val); int (*enable)(struct smu_context *smu, bool enable); + int (*get_residency)(struct smu_context *smu, uint32_t *res); }; enum phase_det_state { @@ -409,6 +410,7 @@ struct smu_phase_det_ctl { struct smu_phase_det_params params; struct smu_phase_det_ops *ops; enum phase_det_state status; + uint32_t residency; }; struct smu_dpm_context { From 66df314067bfeea88a698f5d30f4640b678793fb Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 15 Jul 2024 16:46:08 +0530 Subject: [PATCH 1285/2653] drm/amd/pm: Add SMUv13.0.6 phase detect residency Add support to get phase detect residency information on SMUv13.0.6 SOCs. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- .../pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 1 + drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 1 + .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 24 +++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h index 32131debe242f..373d994cad496 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h @@ -99,6 +99,7 @@ #define PPSMC_MSG_SetPhsDetWRbwHystDown 0x48 #define PPSMC_MSG_SetPhsDetWRbwAlpha 0x49 #define PPSMC_MSG_SetPhsDetOnOff 0x4A +#define PPSMC_MSG_GetPhsDetResidency 0x4B #define PPSMC_MSG_ResetSDMA 0x4D #define PPSMC_MSG_ResetVCN 0x4E #define PPSMC_MSG_GetStaticMetricsTable 0x59 diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h index 65035c498fa9c..53207317c09ce 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -282,6 +282,7 @@ __SMU_DUMMY_MAP(SetPhsDetWRbwHystDown), \ __SMU_DUMMY_MAP(SetPhsDetWRbwAlpha), \ __SMU_DUMMY_MAP(SetPhsDetOnOff), \ + __SMU_DUMMY_MAP(GetPhsDetResidency), \ __SMU_DUMMY_MAP(ResetSDMA), \ __SMU_DUMMY_MAP(ResetVCN), \ __SMU_DUMMY_MAP(GetStaticMetricsTable), diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 079ee29c7faf5..aa5f285184c55 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -184,6 +184,7 @@ static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COU MSG_MAP(SetPhsDetWRbwHystDown, PPSMC_MSG_SetPhsDetWRbwHystDown, 0), MSG_MAP(SetPhsDetWRbwAlpha, PPSMC_MSG_SetPhsDetWRbwAlpha, 0), MSG_MAP(SetPhsDetOnOff, PPSMC_MSG_SetPhsDetOnOff, 0), + MSG_MAP(GetPhsDetResidency, PPSMC_MSG_GetPhsDetResidency, 0), }; // clang-format on @@ -726,10 +727,30 @@ static int smu_v13_0_6_phase_det_enable(struct smu_context *smu, bool enable) return r; } +static int smu_v13_0_6_phase_det_get_residency(struct smu_context *smu, + uint32_t *res) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = smu_dpm->pd_ctl; + + if (!res) + return -EINVAL; + + if (pd_ctl->status != SMU_PHASE_DET_ON) { + *res = 0; + return 0; + } + + return smu_cmn_send_smc_msg(smu, SMU_MSG_GetPhsDetResidency, res); +} + static struct smu_phase_det_ops smu_v13_0_6_pd_ops = { .set = smu_v13_0_6_phase_det_set, .get = smu_v13_0_6_phase_det_get, .enable = smu_v13_0_6_phase_det_enable, + .get_residency = smu_v13_0_6_phase_det_get_residency, }; static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu) @@ -1155,6 +1176,9 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) smu_dpm->pd_ctl = NULL; } + if (smu_dpm->pd_ctl && (smu->smc_fw_version < 0x00556F78)) + smu_dpm->pd_ctl->ops->get_residency = NULL; + smu_v13_0_6_pm_policy_init(smu); /* gfxclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.gfx_table; From e30be1b6bf39d556a3c33b5c71097d03966cdcf7 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 8 Aug 2024 17:08:05 +0800 Subject: [PATCH 1286/2653] drm/amdkcl: add oot build support Signed-off-by: Flora Cui Signed-off-by: Bob Zhou Reviewed-by: Horatio Zhang --- drivers/gpu/drm/amd/dkms/oot/Makefile.oot | 41 ++++++++ drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec | 96 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/oot/pre-build.sh | 91 ++++++++++++++++++ 3 files changed, 228 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/oot/Makefile.oot create mode 100644 drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec create mode 100644 drivers/gpu/drm/amd/dkms/oot/pre-build.sh diff --git a/drivers/gpu/drm/amd/dkms/oot/Makefile.oot b/drivers/gpu/drm/amd/dkms/oot/Makefile.oot new file mode 100644 index 0000000000000..5c8c78df4e932 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/oot/Makefile.oot @@ -0,0 +1,41 @@ +ifneq ($(KERNELRELEASE),) +include $(src)/amd/dkms/Makefile +else +KERNELVER := $(shell uname -r) +kernel_build_dir := /lib/modules/$(KERNELVER)/build +PACKAGE_NAME := $(shell sed -n '/PACKAGE_NAME/s|.*=||p' amd/dkms/dkms.conf) +PACKAGE_VERSION := $(shell sed -n '/PACKAGE_VERSION/s|.*=||p' amd/dkms/dkms.conf) +module_src_dir := $(CURDIR) +module_build_dir := $(shell mktemp -ut amd.XXXXXXXX) +module_build_flags := +num_cpu_cores := $(shell nproc) +Q := @ + +ifeq ($(wildcard $(kernel_build_dir)/include/config/auto.conf),) +$(error "invalid kernel obj dir, is kernel-devel installed?") +endif + +.PHONY: modules pre-build + +include $(kernel_build_dir)/include/config/auto.conf + +ifneq ($(CONFIG_CC_IS_CLANG),) +module_build_flags += CC=clang +endif +ifneq ($(CONFIG_LD_IS_LLD),) +module_build_flags += LD=ld.lld +endif + +modules:pre-build + $(Q)make -j$(num_cpu_cores) KERNELRELEASE=$(KERNELVER) \ + TTM_NAME=amdttm \ + SCHED_NAME=amd-sched \ + -C $(kernel_build_dir) \ + M=$(module_build_dir) $(module_build_flags) + $(Q)unlink $(module_build_dir) + +pre-build: + $(Q)cp -f amd/dkms/oot/pre-build.sh amd/dkms + $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(PACKAGE_NAME) $(PACKAGE_VERSION) $(module_build_dir) + +endif diff --git a/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec new file mode 100644 index 0000000000000..dd92860353f46 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec @@ -0,0 +1,96 @@ +%global pkg amdgpu +%global kernel kernel version +%define pkg_version 6.8.7 +%define osdb_version 1798298 +%define anolis_release 1 + +%global debug_package %{nil} + +Name: kmod-%{pkg} +Version: %(echo %{kernel} | sed -E 's/-/~/g; s/\.(an|al)[0-9]+$//g') +Release: %{pkg_version}_%{osdb_version}~%{anolis_release}%{?dist} +Summary: The amdgpu Linux kernel driver + +License: GPLv2 and Redistributable, no modification permitted +URL: http://www.amd.com/ +Source0: kmod-%{pkg}-%{pkg_version}.tar.gz + +BuildRequires: gcc +BuildRequires: make +Requires: kernel >= %{kernel} + +%description +The AMD display driver kernel module in DKMS format for AMD graphics S/W + +%prep +%autosetup -n kmod-%{pkg}-%{pkg_version} -p1 + +%build +pushd src +%{__make} -f amd/dkms/oot/Makefile.oot KERNELVER=%(uname -r) +popd + +%install +mkdir -p %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu +%{__install} -D -t %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu src/amddrm_buddy.ko src/amddrm_ttm_helper.ko src/scheduler/amd-sched.ko src/ttm/amdttm.ko src/amd/amdxcp/amdxcp.ko src/amd/amdgpu/amdgpu.ko src/amd/amdkcl/amdkcl.ko + +# Make .ko objects temporarily executable for automatic stripping +find %{buildroot}/lib/modules -type f -name \*.ko -exec chmod u+x \{\} \+ + +# Generate depmod.conf +%{__install} -d %{buildroot}/%{_sysconfdir}/depmod.d/ +for kmod in $(find %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra -type f -name \*.ko -printf "%%P\n" | sort) +do + echo "override $(basename $kmod .ko) * weak-updates/$(dirname $kmod)" >> %{buildroot}/%{_sysconfdir}/depmod.d/%{pkg}.conf + echo "override $(basename $kmod .ko) * extra/$(dirname $kmod)" >> %{buildroot}/%{_sysconfdir}/depmod.d/%{pkg}.conf +done + +%clean +%{__rm} -rf %{buildroot} + +%post +depmod -a > /dev/null 2>&1 + +if [ -x "/usr/sbin/weak-modules" ]; then + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdgpu.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdkcl.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdxcp.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_buddy.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_ttm_helper.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules +fi + +%preun +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdgpu.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdkcl.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdxcp.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_buddy.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_ttm_helper.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko" >> /var/run/rpm-%{pkg}-modules.list + +%postun +depmod -a > /dev/null 2>&1 + +if [ -x "/usr/sbin/weak-modules" ]; then + modules=( $(cat /var/run/rpm-%{pkg}-modules.list) ) + printf '%s\n' "${modules[@]}" | /usr/sbin/weak-modules --no-initramfs --remove-modules +fi +rm /var/run/rpm-%{pkg}-modules.list + +%files +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdgpu.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdkcl.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdxcp.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_buddy.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_ttm_helper.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko +%defattr(644,root,root,755) +%license licenses +%config(noreplace) %{_sysconfdir}/depmod.d/%{pkg}.conf + +%changelog +* Thu Jul 18 2024 Bob Zhou - 6.8.7-1798298 +- diff --git a/drivers/gpu/drm/amd/dkms/oot/pre-build.sh b/drivers/gpu/drm/amd/dkms/oot/pre-build.sh new file mode 100644 index 0000000000000..7cb58df401aa8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/oot/pre-build.sh @@ -0,0 +1,91 @@ +#!/bin/bash + +KCL="amd/amdkcl" +INC="include" +SRC="amd/dkms" + +KERNELVER=$1 +DKMS_TREE=$2 +MODULE=$3 +MODULE_VERSION=$4 +MODULE_BUILD_DIR=$5 +KERNELVER_BASE=${KERNELVER%%-*} + +version_lt () { + newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) + [ "$KERNELVER_BASE" != "$newest" ] +} + +version_ge () { + newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) + [ "$KERNELVER_BASE" = "$newest" ] +} + +version_gt () { + oldest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | head -n1) + [ "$KERNELVER_BASE" != "$oldest" ] +} + +version_le () { + oldest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | head -n1) + [ "$KERNELVER_BASE" = "$oldest" ] +} + +source $KCL/files + +sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ + -e '/dma_resv_lockdep/,/subsys_initcall/d' \ + -e '1i\#ifdef HAVE_DMA_RESV_FENCES' \ + -e '$a\#endif' $KCL/dma-buf/dma-resv.c +sed -i -e '/extern struct ww_class reservation_ww_class/i #include ' \ + -e '/struct dma_resv {/, /}/d' \ + -e '/struct dma_resv_iter {/, /}/d' \ + -e '/enum dma_resv_usage {/, /}/d' $INC/linux/dma-resv.h + +# add amd prefix to exported symbols +for file in $FILES; do + awk -F'[()]' '/EXPORT_SYMBOL/ { + print "#define "$2" amd"$2" //"$0 + }' $file | sort -u >>$INC/rename_symbol.h +done + +# rename CONFIG_xxx to CONFIG_xxx_AMDKCL +# otherwise kernel config would override dkms package config +AMDGPU_CONFIG=$(find -name Kconfig -exec grep -h '^config' {} + | sed 's/ /_/' | tr 'a-z' 'A-Z') +TTM_CONFIG=$(awk '/CONFIG_DRM/{gsub(".*\\(CONFIG_DRM","CONFIG_DRM");gsub("\\).*","");print $0}' ttm/Makefile) +SCHED_CONFIG=$(awk '/CONFIG_DRM/{gsub(".*\\(CONFIG_DRM","CONFIG_DRM");gsub("\\).*","");print $0}' scheduler/Makefile) +for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do + for file in $(grep -rl $config ./); do + sed -i "s/\<$config\>/&_AMDKCL/" $file + done + sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile +done + +export KERNELVER +ln -s $DKMS_TREE $MODULE_BUILD_DIR + +# Enable gcc-toolset for kernels that are built with non-default compiler +# perform this check only when permissions allow +if [[ -d /opt/rh && `id -u` -eq 0 ]]; then + for f in $(find /opt/rh -type f -a -name gcc); do + [[ -f /boot/config-$KERNELVER ]] || continue + config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) + IFS='.' read -ra ver <<<$($f -dumpfullversion) + gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) + if [[ "$config_gcc_version" = "$gcc_version" ]]; then + . ${f%/*}/../../../enable + break + fi + done +fi +echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env + +(cd $SRC && ./configure) + +# rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o +# for kernel version < 5.3 +if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then + for file in $(grep -rl 'CFLAGS_' amd/display/); do + sed -i 's|\(CFLAGS_[A-Z_]*\)$(AMDDALPATH)/.*/\(.*\.o\)|\1\2|' $file + done +fi From 0a70476bb0b3f4c5225566c9e1045ac7277b56a2 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 12 Aug 2024 18:43:59 +0800 Subject: [PATCH 1287/2653] drm/amdkcl: wrap code under DEFINE_DEBUGFS_ATTRIBUTE It's caused by 7368b413ed6e5a98516b8018e8e47850f32cd1d3 "drm/amd/pm: Add phase detect residency support" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 22472adc0893f..d36bbfd01daee 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -4249,8 +4249,13 @@ DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, smu_phase_det_debugfs_enable, "%llu\n"); #endif +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_res, smu_phase_det_debugfs_get_residency, NULL, "%llu\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_res, + smu_phase_det_debugfs_get_residency, NULL, "%llu\n"); +#endif #define DEBUGFS_CREATE_PHASE_DET_ATTR(name, param) \ debugfs_create_file(#name, 0644, dir, smu, &smu_phase_det_fops_##param) From f85e97971389b3ae45c6ea83c029ce5a6d347dad Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 12 Aug 2024 18:56:27 +0800 Subject: [PATCH 1288/2653] drm/amdkcl: update kbps_to_peak_pbn param for non-upstream code It's caused by 4b6564cb120c9872ba6b2c108e634586acebc792 "drm/amd/display: Fix MST BW calculation Regression" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 48226ff0d0315..63b3029585ead 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -2175,11 +2175,13 @@ enum dc_status dm_dp_mst_is_port_support_mode( */ int pbn_div, slot_num, max_slot_num; enum dc_link_encoding_format link_encoding; + uint16_t fec_overhead_multiplier_x1000 = + get_fec_overhead_multiplier(stream->link); uint32_t stream_kbps = dc_bandwidth_in_kbps_from_timing( &stream->timing, dc_link_get_highest_encoding_format(stream->link)); - pbn = kbps_to_peak_pbn(stream_kbps); + pbn = kbps_to_peak_pbn(stream_kbps, fec_overhead_multiplier_x1000); pbn_div = dm_mst_get_pbn_divider(stream->link); slot_num = DIV_ROUND_UP(pbn, pbn_div); From 54774c32237f647cc39327c24950f93314af9cdc Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 18 Aug 2024 13:48:05 +0800 Subject: [PATCH 1289/2653] drm/kcl: fake drm/drm_fbdev_ttm.h header It's caused by v6.9-rc6-1436-gaae4682e5d66 drm/fbdev-generic: Convert to fbdev-ttm v6.1-rc2-542-g8ab59da26bc0 drm/fb-helper: Move generic fbdev emulation into separate source file Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 7 +++++++ include/kcl/backport/kcl_drm_fbdev_ttm.h | 16 ++++++++++++++++ include/kcl/header/drm/drm_fbdev_generic.h | 9 +++++++++ include/kcl/header/drm/drm_fbdev_ttm.h | 11 +++++++++++ 5 files changed, 44 insertions(+) create mode 100644 include/kcl/backport/kcl_drm_fbdev_ttm.h create mode 100644 include/kcl/header/drm/drm_fbdev_generic.h create mode 100644 include/kcl/header/drm/drm_fbdev_ttm.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 78ab1d617f6b3..2c85c76158ba5 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -126,4 +126,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 6dd1ab847b3bb..6b06ae6f73fef 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -110,4 +110,11 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/edid: split out drm_eld.h from drm_edid.h dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_eld.h]) + + dnl # + dnl # v6.9-rc6-1436-gaae4682e5d66 + dnl # drm/fbdev-generic: Convert to fbdev-ttm + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_fbdev_ttm.h]) + ]) diff --git a/include/kcl/backport/kcl_drm_fbdev_ttm.h b/include/kcl/backport/kcl_drm_fbdev_ttm.h new file mode 100644 index 0000000000000..03ddc7699ddb1 --- /dev/null +++ b/include/kcl/backport/kcl_drm_fbdev_ttm.h @@ -0,0 +1,16 @@ +#ifndef __KCL_BACKPORT_KCL_DRM_DRV_H_ +#define __KCL_BACKPORT_KCL_DRM_DRV_H__ + +#include +#include + +#ifndef HAVE_DRM_DRM_FBDEV_TTM_H +static inline +void _kcl_drm_fbdev_ttm_setup(struct drm_device *dev, unsigned int preferred_bpp) +{ + return drm_fbdev_generic_setup(dev, preferred_bpp); +} +#define drm_fbdev_ttm_setup _kcl_drm_fbdev_ttm_setup +#endif + +#endif diff --git a/include/kcl/header/drm/drm_fbdev_generic.h b/include/kcl/header/drm/drm_fbdev_generic.h new file mode 100644 index 0000000000000..13b6f65c37f01 --- /dev/null +++ b/include/kcl/header/drm/drm_fbdev_generic.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_DRM_FBDEV_GENERIC_H_H_ +#define _KCL_HEADER_DRM_DRM_FBDEV_GENERIC_H_H_ + +#ifdef HAVE_DRM_DRM_FBDEV_GENERIC_H +#include_next +#endif + +#endif diff --git a/include/kcl/header/drm/drm_fbdev_ttm.h b/include/kcl/header/drm/drm_fbdev_ttm.h new file mode 100644 index 0000000000000..dbf67afb91594 --- /dev/null +++ b/include/kcl/header/drm/drm_fbdev_ttm.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_DRM_FBDEV_TTM_H_H_ +#define _KCL_HEADER_DRM_DRM_FBDEV_TTM_H_H_ + +#ifdef HAVE_DRM_DRM_FBDEV_TTM_H +#include_next +#else +#include +#endif + +#endif From dcbfb0d35e3e1e2342c2d1059cf09eafbf6444d7 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 23 Aug 2024 16:21:31 +0800 Subject: [PATCH 1290/2653] drm/amdkcl: fake drm_crtc_vblank_crtc It's caused by v6.9-rc2-247-gd12e36494dc2 drm/vblank: Introduce drm_crtc_vblank_crtc() Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_vblank.c | 43 +++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-vblank.m4 | 16 ++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_vblank.h | 36 +++++++++++++++++ 6 files changed, 99 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_vblank.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-vblank.m4 create mode 100644 include/kcl/kcl_drm_vblank.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 3fbd585862102..fd7c388cef2bf 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o \ + kcl_drm_vblank.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_vblank.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_vblank.c new file mode 100644 index 0000000000000..f8d4ab7de31e3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_vblank.c @@ -0,0 +1,43 @@ +/* + * drm_irq.c IRQ and vblank support + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include + +/*copy from drivers/gpu/drm/drm_vblank.c */ +#ifndef HAVE_CRTC_DRM_VBLANK_CRTC +static struct drm_vblank_crtc * +drm_vblank_crtc(struct drm_device *dev, unsigned int pipe) +{ + return &dev->vblank[pipe]; +} + +struct drm_vblank_crtc * +drm_crtc_vblank_crtc(struct drm_crtc *crtc) +{ + return drm_vblank_crtc(crtc->dev, drm_crtc_index(crtc)); +} +EXPORT_SYMBOL(drm_crtc_vblank_crtc); +#endif + diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 2c85c76158ba5..7ce2f26657bf8 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -127,4 +127,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-vblank.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-vblank.m4 new file mode 100644 index 0000000000000..d2f9038b46063 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-vblank.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.9-rc2-247-gd12e36494dc2 +dnl # drm/vblank: Introduce drm_crtc_vblank_crtc() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_VBLANK_CRTC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_crtc_vblank_crtc(NULL); + ],[ + AC_DEFINE(HAVE_CRTC_DRM_VBLANK_CRTC, 1, + [drm_edid_raw() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index adc6a15b33808..3f87ed87dbddc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -236,6 +236,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEBUG_CATEGORY AC_AMDGPU_SMCA_UMC_V2 AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE + AC_AMDGPU_DRM_CRTC_VBLANK_CRTC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_vblank.h b/include/kcl/kcl_drm_vblank.h new file mode 100644 index 0000000000000..4a74049654c92 --- /dev/null +++ b/include/kcl/kcl_drm_vblank.h @@ -0,0 +1,36 @@ +/* + * Copyright 2016 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_DRM_VBLANK_H +#define _KCL_KCL_DRM_VBLANK_H + +#include +#include +#include + +/*copy from include/drm/drm_vblank.h */ +#ifndef HAVE_CRTC_DRM_VBLANK_CRTC +struct drm_vblank_crtc *drm_crtc_vblank_crtc(struct drm_crtc *crtc); +#endif + +#endif /*_KCL_KCL_DRM_VBLANK_H */ From bfb6805a62d018c7f7f11cacfb11efdb2e0b7934 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 21 Aug 2024 18:02:16 +0800 Subject: [PATCH 1291/2653] drm/amdkcl: modify the makefile for dml It's caused by v6.9-9706-g6cbd1d6d36c5 arch: add ARCH_HAS_KERNEL_FPU_SUPPORT`` Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 35 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/dml/Makefile | 38 ++++++++++++++++++- drivers/gpu/drm/amd/display/dc/dml2/Makefile | 38 +++++++++++++++++++ 3 files changed, 110 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c index e46f8ce41d871..dab8eb705cafa 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c @@ -26,7 +26,20 @@ #include "dc_trace.h" +#ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT #include +#else +#if defined(CONFIG_X86) +#include +#elif defined(CONFIG_PPC64) +#include +#include +#elif defined(CONFIG_ARM64) +#include +#elif defined(CONFIG_LOONGARCH) +#include +#endif +#endif /** * DOC: DC FPU manipulation overview @@ -79,8 +92,19 @@ void dc_fpu_begin(const char *function_name, const int line) preempt_disable(); depth = __this_cpu_inc_return(fpu_recursion_depth); if (depth == 1) { +#ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT BUG_ON(!kernel_fpu_available()); kernel_fpu_begin(); +#else +#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) + kernel_fpu_begin(); +#elif defined(CONFIG_PPC64) + if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) + enable_kernel_fp(); +#elif defined(CONFIG_ARM64) + kernel_neon_begin(); +#endif +#endif } TRACE_DCN_FPU(true, function_name, line, depth); @@ -102,7 +126,18 @@ void dc_fpu_end(const char *function_name, const int line) depth = __this_cpu_dec_return(fpu_recursion_depth); if (depth == 0) { +#ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT + kernel_fpu_end(); +#else +#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) kernel_fpu_end(); +#elif defined(CONFIG_PPC64) + if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) + disable_kernel_fp(); +#elif defined(CONFIG_ARM64) + kernel_neon_end(); +#endif +#endif } else { WARN_ON_ONCE(depth < 0); } diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile index 9e7f9713bba0b..bfd2f14f57681 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile @@ -24,12 +24,48 @@ # Makefile for the 'utils' sub-component of DAL. # It provides the general basic services required by other DAL # subcomponents. - +# +ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT dml_ccflags := $(CC_FLAGS_FPU) dml_rcflags := $(CC_FLAGS_NO_FPU) +else +ifdef CONFIG_X86 +dml_ccflags-$(CONFIG_CC_IS_GCC) := -mhard-float +dml_ccflags := $(dml_ccflags-y) -msse +endif + +ifdef CONFIG_PPC64 +dml_ccflags := -mhard-float -maltivec +endif + +ifdef CONFIG_ARM64 +dml_rcflags := -mgeneral-regs-only +endif + +ifdef CONFIG_LOONGARCH +dml_ccflags := -mfpu=64 +dml_rcflags := -msoft-float +endif include $(src)/../dkms/Makefile.compiler +ifneq ($(call gcc-min-version, 70100),y) +IS_OLD_GCC = 1 +endif + +ifdef CONFIG_X86 +ifdef IS_OLD_GCC +# Stack alignment mismatch, proceed with caution. +# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 +# (8B stack alignment). +dml_ccflags += -mpreferred-stack-boundary=4 +else +dml_ccflags += -msse2 +endif +endif + +endif #CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT + ifneq ($(CONFIG_FRAME_WARN),0) ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) frame_warn_limit := 3072 diff --git a/drivers/gpu/drm/amd/display/dc/dml2/Makefile b/drivers/gpu/drm/amd/display/dc/dml2/Makefile index 4c21ce42054c5..9a6cc5b79b778 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml2/Makefile @@ -24,8 +24,46 @@ # # Makefile for dml2. +ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT dml2_ccflags := $(CC_FLAGS_FPU) dml2_rcflags := $(CC_FLAGS_NO_FPU) +else +ifdef CONFIG_X86 +dml2_ccflags-$(CONFIG_CC_IS_GCC) := -mhard-float +dml2_ccflags := $(dml2_ccflags-y) -msse +endif + +ifdef CONFIG_PPC64 +dml2_ccflags := -mhard-float -maltivec +endif + +ifdef CONFIG_ARM64 +dml2_rcflags := -mgeneral-regs-only +endif + +ifdef CONFIG_LOONGARCH +dml2_ccflags := -mfpu=64 +dml2_rcflags := -msoft-float +endif + +ifdef CONFIG_CC_IS_GCC +ifeq ($(call cc-ifversion, -lt, 0701, y), y) +IS_OLD_GCC = 1 +endif +endif + +ifdef CONFIG_X86 +ifdef IS_OLD_GCC +# Stack alignment mismatch, proceed with caution. +# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 +# (8B stack alignment). +dml2_ccflags += -mpreferred-stack-boundary=4 +else +dml2_ccflags += -msse2 +endif +endif + +endif #CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT ifneq ($(CONFIG_FRAME_WARN),0) ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) From d12bf5c9d722820d069edfec3093f74d50276bc5 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 19 Jan 2022 11:10:38 +0800 Subject: [PATCH 1292/2653] drm/amdkcl: include correct header when macro HAVE_ASM_FPU_API_H isn't defined Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c index dab8eb705cafa..35066ae9acbce 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c @@ -30,7 +30,11 @@ #include #else #if defined(CONFIG_X86) +#if defined(HAVE_ASM_FPU_API_H) #include +#else +#include +#endif #elif defined(CONFIG_PPC64) #include #include From 414b9391b32d2f3997e34a7db02903cbc04a5b8d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 23 Aug 2024 17:02:07 +0800 Subject: [PATCH 1293/2653] drm/amdkcl: check PCI_IRQ_INTX whether exist It's caused by v6.7-rc1-1-g58ff9c5acb4a PCI: Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX v6.9-rc1-32-g0e1fdd222f0 PCI: Remove PCI_IRQ_LEGACY Signed-off-by: Asher Song --- include/kcl/kcl_pci.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index d9ea67cc3dee3..11dd0f05f5879 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -222,4 +222,10 @@ static inline struct pci_dev *pci_get_base_class(unsigned int class, { return NULL; } #endif /*CONFIG_PCI*/ #endif /*HAVE_PCI_GET_BASE_CLASS*/ + +/* Copied from include/linux/pci.h */ +#ifndef PCI_IRQ_INTX +#define PCI_IRQ_INTX PCI_IRQ_LEGACY +#endif + #endif /* AMDKCL_PCI_H */ From 3dd6d5332248b0ba2d8cb0aca6731f1b124ea82b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 18 Dec 2023 13:54:33 +0800 Subject: [PATCH 1294/2653] drm/amdkcl: test whether struct drm_color_ctm_3x4 is available It's caused by 2d4457c2d03ed0e2fcf4206a10c0bdfcab4fd03f "drm/amd/display: Add 3x4 CTM support for plane CTM" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/struct_drm_color_ctm_3x4.m4 | 20 +++++++++++++++++++ include/uapi/drm/amdgpu_drm.h | 2 ++ 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_color_ctm_3x4.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3f87ed87dbddc..33378061d9d21 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -223,6 +223,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_RADIX_TREE_ITER_DELETE AC_AMDGPU_KFIFO_PUT AC_AMDGPU_DRM_CLIENT_REGISTER + AC_AMDGPU_DRM_COLOR_CTM_3X4 AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD AC_AMDGPU_DMA_FENCE_TIMESTAMP diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_color_ctm_3x4.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_color_ctm_3x4.m4 new file mode 100644 index 0000000000000..cef143831f813 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_color_ctm_3x4.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # v6.5-2548-g2d4457c2d03e +dnl # drm/amd/display: Add 3x4 CTM support for plane CTM +dnl # +AC_DEFUN([AC_AMDGPU_DRM_COLOR_CTM_3X4], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_color_ctm_3x4 *ctm = NULL; + ctm->matrix[0] = 0; + ],[ + AC_DEFINE(HAVE_DRM_COLOR_CTM_3X4, 1, + [struct drm_color_ctm_3x4 is available]) + ]) + ]) +]) + + + diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index b2c06f61448fa..c188896a31ec8 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -1696,6 +1696,7 @@ struct drm_amdgpu_info_uq_metadata { #define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */ #define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */ +#ifndef HAVE_DRM_COLOR_CTM_3X4 /* FIXME wrong namespace! */ struct drm_color_ctm_3x4 { /* @@ -1704,6 +1705,7 @@ struct drm_color_ctm_3x4 { */ __u64 matrix[12]; }; +#endif /** * Definition of System Unified Address (SUA) apertures From cd1a73900e7e68f4aa8dc8250b3e560f5088bd4c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 27 Aug 2024 09:35:42 +0800 Subject: [PATCH 1295/2653] drm/amdkcl: check drm_dp_add_payload_part2 whether requires three argunments It's caused by v6.9-rc6-1554-g8a0a7b98d4b6 drm/mst: Fix NULL pointer dereference at drm_dp_add_payload_part2 commit v5.19-rc6-1771-g4d07b0bc4034 drm/display/dp_mst: Move all payload info into the atomic state Signed-off-by: Asher Song --- .../amd/dkms/m4/drm-dp-mst-topology-state.m4 | 20 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../backport/kcl_drm_dp_mst_helper_backport.h | 13 ++++++++++++ 3 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index 424778ea6606b..d5928adc09844 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -67,3 +67,23 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV], [ ]) ]) +dnl # +dnl # commit v6.9-rc6-1554-g8a0a7b98d4b6 +dnl # drm/mst: Fix NULL pointer dereference at drm_dp_add_payload_part2 +dnl # +dnl # commit v5.19-rc6-1771-g4d07b0bc4034 +dnl # drm/display/dp_mst: Move all payload info into the atomic state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int a = 0; + a = drm_dp_add_payload_part2(NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS, 1, + [drm_dp_add_payload_part2 has three arguments]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 33378061d9d21..89e8cd943f3ad 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -238,6 +238,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SMCA_UMC_V2 AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE AC_AMDGPU_DRM_CRTC_VBLANK_CRTC + AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 9791910ed58b0..a84cd2ac22cc2 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -104,4 +104,17 @@ _kcl_drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr, #define drm_dp_mst_topology_mgr_resume _kcl_drm_dp_mst_topology_mgr_resume #endif +#ifdef HAVE_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS +static inline int +_kcl_drm_dp_add_payload_part2(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_atomic_payload *payload) +{ + struct drm_dp_mst_topology_state *mst_state; + + mst_state = to_drm_dp_mst_topology_state(mgr->base.state); + return drm_dp_add_payload_part2(mgr, mst_state->base.state, payload); +} +#define drm_dp_add_payload_part2 _kcl_drm_dp_add_payload_part2 +#endif + #endif From a3d35b697bd9873eb2c2bc7536e6772060cd240b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 28 Aug 2024 14:15:33 +0800 Subject: [PATCH 1296/2653] drm/amdkcl: test follow_pfn() is available It's caused by cb10c28ac82c9b7a5e9b3b1dc7157036c20c36dd "mm: remove follow_pfn" Signed-off-by: Bob Zhou Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/Makefile | 2 +- drivers/gpu/drm/amd/backport/kcl_memory.c | 20 ++++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_mm.h | 6 ++++++ 6 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/backport/kcl_memory.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index 8bc3adedebc57..2d01094326e2c 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: MIT BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ - kcl_drm_gem.o kcl_drm_file.o + kcl_drm_gem.o kcl_drm_file.o kcl_memory.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/kcl_memory.c b/drivers/gpu/drm/amd/backport/kcl_memory.c new file mode 100644 index 0000000000000..153710b6883de --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_memory.c @@ -0,0 +1,20 @@ +#include + +#ifndef HAVE_FOLLOW_PFN +int _kcl_follow_pfn(struct vm_area_struct *vma, unsigned long address, + unsigned long *pfn) +{ + int ret = -EINVAL; + spinlock_t *ptl; + pte_t *ptep; + + ret = follow_pte(vma, address, &ptep, &ptl); + if (ret) + return ret; + *pfn = pte_pfn(ptep_get(ptep)); + pte_unmap_unlock(ptep, ptl); + return 0; +} + +EXPORT_SYMBOL(_kcl_follow_pfn); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 077e9c583ac57..2cdb75ac823fd 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -602,6 +602,9 @@ /* drm_show_fdinfo() is available */ #define HAVE_DRM_SHOW_FDINFO 1 +/* follow_pfn() is available */ +/* #undef HAVE_FOLLOW_PFN */ + /* drm_simple_encoder is available */ #define HAVE_DRM_SIMPLE_ENCODER_INIT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 b/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 new file mode 100644 index 0000000000000..ea2c47c00ab90 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.9-rc4-152-gcb10c28ac82c +dnl # mm: remove follow_pfn +dnl # +AC_DEFUN([AC_AMDGPU_FOLLOW_PFN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + follow_pfn(NULL, 0, NULL); + ],[follow_pfn], [mm/memory.c],[ + AC_DEFINE(HAVE_FOLLOW_PFN, 1, + [follow_pfn() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 89e8cd943f3ad..21e16170a2dd9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -212,6 +212,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VM_FLAGS_SET AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED AC_AMDGPU_PID_TYPE + AC_AMDGPU_FOLLOW_PFN AC_AMDGPU_LIST_CMP_FUNC_IS_CONST_PARAM AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE AC_AMDGPU_DRM_SHOW_FDINFO diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 646ba0d687544..b502b239610ef 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -166,4 +166,10 @@ static inline bool vma_is_initial_stack(const struct vm_area_struct *vma) } #endif +#ifndef HAVE_FOLLOW_PFN +int _kcl_follow_pfn(struct vm_area_struct *vma, unsigned long address, + unsigned long *pfn); +#define follow_pfn _kcl_follow_pfn +#endif + #endif /* AMDKCL_MM_H */ From ef8bd9997a070c60923952d30e57acbd23421a2b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 28 Aug 2024 16:42:05 +0800 Subject: [PATCH 1297/2653] drm/amdkcl: test whether __assign_str() wants 1 arguments It's caused by 2c92ca849fcc6ee7d0c358e9959abc9f58661aea "tracing/treewide: Remove second parameter of __assign_str()" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 14 +++++++------- drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h | 6 +++--- drivers/gpu/drm/amd/amdkfd/kfd_trace.h | 6 +++--- drivers/gpu/drm/amd/backport/backport.h | 1 + .../drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/assign_str.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/scheduler/backport/backport.h | 1 + drivers/gpu/drm/scheduler/gpu_scheduler_trace.h | 2 +- include/kcl/kcl_tracepoint.h | 13 +++++++++++++ 11 files changed, 51 insertions(+), 15 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/assign_str.m4 create mode 100644 include/kcl/kcl_tracepoint.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index 72f13cd5f5407..d97e196023058 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -176,10 +176,10 @@ TRACE_EVENT(amdgpu_cs_ioctl, ), TP_fast_assign( - __assign_str(timeline); + __amdkcl_assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job)); __entry->context = job->base.s_fence->finished.context; __entry->seqno = job->base.s_fence->finished.seqno; - __assign_str(ring); + __amdkcl_assign_str(ring, to_amdgpu_ring(job->base.sched)->name); __entry->num_ibs = job->num_ibs; ), TP_printk("timeline=%s, fence=%llu:%llu, ring_name=%s, num_ibs=%u", @@ -199,10 +199,10 @@ TRACE_EVENT(amdgpu_sched_run_job, ), TP_fast_assign( - __assign_str(timeline); + __amdkcl_assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job)); __entry->context = job->base.s_fence->finished.context; __entry->seqno = job->base.s_fence->finished.seqno; - __assign_str(ring); + __amdkcl_assign_str(ring, to_amdgpu_ring(job->base.sched)->name); __entry->num_ibs = job->num_ibs; ), TP_printk("timeline=%s, fence=%llu:%llu, ring_name=%s, num_ibs=%u", @@ -227,7 +227,7 @@ TRACE_EVENT(amdgpu_vm_grab_id, TP_fast_assign( __entry->pasid = vm->pasid; - __assign_str(ring); + __amdkcl_assign_str(ring, ring->name); __entry->vmid = job->vmid; __entry->vm_hub = ring->vm_hub, __entry->pd_addr = job->vm_pd_addr; @@ -421,7 +421,7 @@ TRACE_EVENT(amdgpu_vm_flush, ), TP_fast_assign( - __assign_str(ring); + __amdkcl_assign_str(ring, ring->name); __entry->vmid = vmid; __entry->vm_hub = ring->vm_hub; __entry->pd_addr = pd_addr; @@ -553,7 +553,7 @@ TRACE_EVENT(amdgpu_ib_pipe_sync, ), TP_fast_assign( - __assign_str(ring); + __amdkcl_assign_str(ring, sched_job->base.sched->name); __entry->fence = fence; __entry->ctx = fence->context; __entry->seqno = fence->seqno; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h b/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h index 7c857ba3c31c0..5a74e165c087f 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h @@ -3,7 +3,7 @@ #if !defined(_TRACE_KCL_FENCE_H) || defined(TRACE_HEADER_MULTI_READ) #define _TRACE_KCL_FENCE_H -#include +#include #undef TRACE_SYSTEM #define TRACE_SYSTEM kcl_fence @@ -25,8 +25,8 @@ DECLARE_EVENT_CLASS(kcl_fence, ), TP_fast_assign( - __assign_str(driver, fence->ops->get_driver_name(fence)) - __assign_str(timeline, fence->ops->get_timeline_name(fence)) + __amdkcl_assign_str(driver, fence->ops->get_driver_name(fence)); + __amdkcl_assign_str(timeline, fence->ops->get_timeline_name(fence)); __entry->context = fence->context; __entry->seqno = fence->seqno; ), diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_trace.h b/drivers/gpu/drm/amd/amdkfd/kfd_trace.h index 5d27a98055377..16470bec1c317 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_trace.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_trace.h @@ -61,7 +61,7 @@ TRACE_EVENT(kfd_map_memory_to_gpu_end, TP_fast_assign( __entry->pasid = p->pasid; __entry->array_size = array_size; - __assign_str(pStatusMsg, pStatusMsg); + __amdkcl_assign_str(pStatusMsg, pStatusMsg); ), TP_printk("pasid = %u, array_size = %u, StatusMsg=%s", __entry->pasid, @@ -109,7 +109,7 @@ TRACE_EVENT(kfd_evict_process_worker_end, ), TP_fast_assign( __entry->pasid = p->pasid; - __assign_str(pStatusMsg, pStatusMsg); + __amdkcl_assign_str(pStatusMsg, pStatusMsg); ), TP_printk("pasid=%u, StatusMsg=%s", __entry->pasid, __get_str(pStatusMsg)) @@ -137,7 +137,7 @@ TRACE_EVENT(kfd_restore_process_worker_end, ), TP_fast_assign( entry->pasid = p->pasid; - __assign_str(pStatusMsg, pStatusMsg); + __amdkcl_assign_str(pStatusMsg, pStatusMsg); ), TP_printk("pasid=%u, StatusMsg=%s", __entry->pasid, __get_str(pStatusMsg)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7ce2f26657bf8..6ec330de9f4dd 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -128,4 +128,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h index cf168868a0f16..d7b955f964f4f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h @@ -89,7 +89,7 @@ TRACE_EVENT(amdgpu_dc_performance, __entry->writes = write_count; __entry->read_delta = read_count - *last_read; __entry->write_delta = write_count - *last_write; - __assign_str(func); + __amdkcl_assign_str(func, func); __entry->line = line; *last_read = read_count; *last_write = write_count; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2cdb75ac823fd..f3131a813275d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -602,6 +602,9 @@ /* drm_show_fdinfo() is available */ #define HAVE_DRM_SHOW_FDINFO 1 +/* __assign_str() wants 1 arguments */ +#define HAVE_ASSIGN_STR_ONE_ARGUMENT 1 + /* follow_pfn() is available */ /* #undef HAVE_FOLLOW_PFN */ diff --git a/drivers/gpu/drm/amd/dkms/m4/assign_str.m4 b/drivers/gpu/drm/amd/dkms/m4/assign_str.m4 new file mode 100644 index 0000000000000..477d281b98373 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/assign_str.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v6.9-11925-g2c92ca849fcc +dnl # tracing/treewide: Remove second parameter of __assign_str() +dnl # Due to trace system bases on runtime, so use script to handle specially +dnl # +AC_DEFUN([AC_AMDGPU_ASSIGN_STR], [ + AC_KERNEL_DO_BACKGROUND([ + header_file=stage6_event_callback.h + header_file_src=$LINUX/include/trace/stages/$header_file + AS_IF([test -f "$header_file_src"], [ + AS_IF([grep -q '^#define __assign_str(dst)' $header_file_src], [ + AC_DEFINE(HAVE_ASSIGN_STR_ONE_ARGUMENT, 1, + [__assign_str() wants 1 arguments]) + ]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 21e16170a2dd9..1327462fd271a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -240,6 +240,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE AC_AMDGPU_DRM_CRTC_VBLANK_CRTC AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS + AC_AMDGPU_ASSIGN_STR AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 04ad51ff373e2..ead9183b08d56 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -10,4 +10,5 @@ #include #include #include +#include #endif diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h b/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h index 0f965676764f7..0bd32514d54c4 100644 --- a/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h +++ b/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h @@ -68,7 +68,7 @@ DECLARE_EVENT_CLASS(drm_sched_job, ), TP_fast_assign( - __assign_str(name); + __amdkcl_assign_str(name, sched_job->sched->name); __entry->job_count = spsc_queue_count(&entity->job_queue); __entry->hw_job_count = atomic_read( &sched_job->sched->credit_count); diff --git a/include/kcl/kcl_tracepoint.h b/include/kcl/kcl_tracepoint.h new file mode 100644 index 0000000000000..10eafc91c9486 --- /dev/null +++ b/include/kcl/kcl_tracepoint.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_TRACEPOINT_H_ +#define _KCL_TRACEPOINT_H_ + +#include + +#ifdef HAVE_ASSIGN_STR_ONE_ARGUMENT +#define __amdkcl_assign_str(dst, src) __assign_str(dst) +#else +#define __amdkcl_assign_str(dst, src) __assign_str(dst, src) +#endif + +#endif From 6fb9db1505557b005c7ef537ed9ffbefb22dc3b4 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 30 Aug 2024 08:58:00 +0800 Subject: [PATCH 1298/2653] drm/amdgpu: fix a call trace when unload amdgpu driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In some APUs, the bo type of GART page table is ttm_bo_type_sg. Those type BOs is released by bo->delayed_delete which is added in ttm_device->wq, not released immediately. To make sure all the ttm_resource is released before ttm_resource_manager is finilized, drain the workqueue in ttm_device. v2: move drain_workqueue to amdgpu_ttm.c Fixes:d99fbd9aab62 ("drm/ttm: Always take the bo delayed cleanup path for imported bos") Suggested-by: Christian König Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index ecefd544ee033..dd4dbd0b29e74 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2487,6 +2487,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) drm_dev_exit(idx); } + drain_workqueue(adev->mman.bdev.wq); amdgpu_direct_gma_fini(adev); amdgpu_vram_mgr_fini(adev); amdgpu_gtt_mgr_fini(adev); From c0042f354406c7245c284735fc89583cb7426151 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 2 Sep 2024 14:25:24 +0800 Subject: [PATCH 1299/2653] drm/amdkcl: wrap code under amdkcl_ttm_resvp() It's caused by 5efa478729c8f2c8eb3c05034a37ad72654307af "drm/amdgpu: re-work VM syncing" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- drivers/gpu/drm/ttm/ttm_bo_util.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 14ba21e82bc8c..23b300ed26c1d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1322,7 +1322,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, pages_addr = (dma_addr_t *)bo->dgma_addr; /* Implicitly sync to moving fences before mapping anything */ - r = amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv, + r = amdgpu_sync_resv(adev, &sync, amdkcl_ttm_resvp(&bo->tbo), AMDGPU_SYNC_EXPLICIT, vm); if (r) goto error_free; diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 21e07a801ef12..0b51db4b1dc12 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -826,13 +826,13 @@ static bool ttm_lru_walk_trylock(struct ttm_bo_lru_cursor *curs, curs->needs_unlock = false; - if (dma_resv_trylock(bo->base.resv)) { + if (dma_resv_trylock(amdkcl_ttm_resvp(bo))) { curs->needs_unlock = true; return true; } - if (bo->base.resv == ctx->resv && ctx->allow_res_evict) { - dma_resv_assert_held(bo->base.resv); + if (amdkcl_ttm_resvp(bo) == ctx->resv && ctx->allow_res_evict) { + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); return true; } @@ -843,7 +843,7 @@ static int ttm_lru_walk_ticketlock(struct ttm_bo_lru_cursor *curs, struct ttm_buffer_object *bo) { struct ttm_lru_walk_arg *arg = curs->arg; - struct dma_resv *resv = bo->base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(bo); int ret; if (arg->ctx->interruptible) From e4831c4b1d61a68bd46cc88d1ed0029c270610aa Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 5 Sep 2024 17:22:51 +0800 Subject: [PATCH 1300/2653] drm/amdkcl: update config.h Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f3131a813275d..2b05f67fdaa51 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -58,6 +58,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_ASM_SET_MEMORY_H 1 +/* __assign_str() wants 1 arguments */ +#define HAVE_ASSIGN_STR_ONE_ARGUMENT 1 + /* amdgpu_attr_group->is_bin_visible is available */ #define HAVE_ATTRIBUTE_GROUP_IS_BIN_VISIBLE 1 @@ -82,6 +85,9 @@ /* cpuinfo_x86.topo is available */ #define HAVE_CPUINFO_TOPOLOGY_IN_CPUINFO_X86_STRUCT 1 +/* drm_edid_raw() is available */ +#define HAVE_CRTC_DRM_VBLANK_CRTC 1 + /* debugfs_create_file_size() is available */ #define HAVE_DEBUGFS_CREATE_FILE_SIZE 1 @@ -602,12 +608,6 @@ /* drm_show_fdinfo() is available */ #define HAVE_DRM_SHOW_FDINFO 1 -/* __assign_str() wants 1 arguments */ -#define HAVE_ASSIGN_STR_ONE_ARGUMENT 1 - -/* follow_pfn() is available */ -/* #undef HAVE_FOLLOW_PFN */ - /* drm_simple_encoder is available */ #define HAVE_DRM_SIMPLE_ENCODER_INIT 1 @@ -626,6 +626,9 @@ /* fault_flag_allow_retry_first() is available */ #define HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST 1 +/* follow_pfn() is available */ +/* #undef HAVE_FOLLOW_PFN */ + /* fsleep() is available */ #define HAVE_FSLEEP 1 @@ -1090,7 +1093,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 6.8.0" +#define PACKAGE_STRING "amdgpu-dkms 6.10.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1099,7 +1102,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "6.5.0" +#define PACKAGE_VERSION "6.10.0" #include "config-amd-chips.h" From 91720d5e41f313848a8321be983b7c73affd2d57 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 2 Sep 2024 14:27:41 +0800 Subject: [PATCH 1301/2653] drm/amdkcl: test import_guid() is available It's caused by ea612cbee8cea66d71922f446cdd3223636e1df2 "drm/amd/display: switch to guid_gen() to generate valid GUIDs" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/import_guid.m4 | 19 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_uuid.h | 19 +++++++++++++++++++ 5 files changed, 43 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/import_guid.m4 create mode 100644 include/kcl/kcl_uuid.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6ec330de9f4dd..013a98f215a07 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -129,4 +129,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2b05f67fdaa51..de3fdc6a43758 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -686,6 +686,9 @@ /* idr_remove return void pointer */ #define HAVE_IDR_REMOVE_RETURN_VOID_POINTER 1 +/* import_guid() is available */ +#define HAVE_IMPORT_GUID 1 + /* in_compat_syscall is defined */ #define HAVE_IN_COMPAT_SYSCALL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/import_guid.m4 b/drivers/gpu/drm/amd/dkms/m4/import_guid.m4 new file mode 100644 index 0000000000000..c96b4703e6cf9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/import_guid.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v5.6-rc7-127-gd01cd62400b3 +dnl # uuid: Add inline helpers to import / export UUIDs +dnl # +AC_DEFUN([AC_AMDGPU_IMPORT_GUID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + import_guid(NULL, NULL); + ],[ + AC_DEFINE(HAVE_IMPORT_GUID, 1, + [import_guid() is available]) + ]) + ]) +]) + + + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1327462fd271a..c21ed329e8040 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -213,6 +213,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED AC_AMDGPU_PID_TYPE AC_AMDGPU_FOLLOW_PFN + AC_AMDGPU_IMPORT_GUID AC_AMDGPU_LIST_CMP_FUNC_IS_CONST_PARAM AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE AC_AMDGPU_DRM_SHOW_FDINFO diff --git a/include/kcl/kcl_uuid.h b/include/kcl/kcl_uuid.h new file mode 100644 index 0000000000000..be6580926dabc --- /dev/null +++ b/include/kcl/kcl_uuid.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef KCL_KCL_UUID_H +#define KCL_KCL_UUID_H + +#include + +#ifndef HAVE_IMPORT_GUID +static inline void import_guid(guid_t *dst, const __u8 *src) +{ + memcpy(dst, src, sizeof(guid_t)); +} + +static inline void export_guid(__u8 *dst, const guid_t *src) +{ + memcpy(dst, src, sizeof(guid_t)); +} +#endif + +#endif \ No newline at end of file From ff63e843fd72bf97b8bff509cb9e5ac1eb683e3f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 5 Sep 2024 17:17:04 +0800 Subject: [PATCH 1302/2653] drm/amdkcl: test struct drm_dp_mst_branch has guid_t It's caused by ea612cbee8cea66d71922f446cdd3223636e1df2 "drm/amd/display: switch to guid_gen() to generate valid GUIDs" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/struct_drm_dp_mst_branch.m4 | 21 +++++++++++++++++++ 4 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_dp_mst_branch.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9c1d873a83bd5..ecfeea3f123be 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2765,7 +2765,11 @@ static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) } } +#ifdef HAVE_DRM_DP_MST_BRANCH_GUID_T guid_copy(&mgr->mst_primary->guid, &guid); +#else + memcpy(mgr->mst_primary->guid, &guid, 16); +#endif out_fail: mutex_unlock(&mgr->lock); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index de3fdc6a43758..064e9aa5b515e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -362,6 +362,9 @@ /* drm_dp_mst_atomic_enable_dsc() wants 5args */ /* #undef HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS */ +/* the guid of struct drm_dp_mst_branch is guid_t */ +#define HAVE_DRM_DP_MST_BRANCH_GUID_T 1 + /* drm_dp_mst_connector_early_unregister() is available */ #define HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c21ed329e8040..caf31276e4669 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -214,6 +214,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PID_TYPE AC_AMDGPU_FOLLOW_PFN AC_AMDGPU_IMPORT_GUID + AC_AMDGPU_DRM_DP_MST_BRANCH_GUID_T AC_AMDGPU_LIST_CMP_FUNC_IS_CONST_PARAM AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE AC_AMDGPU_DRM_SHOW_FDINFO diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_dp_mst_branch.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_dp_mst_branch.m4 new file mode 100644 index 0000000000000..753914f3cc392 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_dp_mst_branch.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # v5.6-rc7-127-gd01cd62400b3 +dnl # uuid: Add inline helpers to import / export UUIDs +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_BRANCH_GUID_T], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_dp_mst_branch mst_primary; + const guid_t guid; + guid_copy(&mst_primary.guid, &guid); + ],[ + AC_DEFINE(HAVE_DRM_DP_MST_BRANCH_GUID_T, 1, + [the guid of struct drm_dp_mst_branch is guid_t]) + ]) + ]) +]) + + + From a88ae6902a4428d6f56c4b7c0a113fb09e4271a1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 6 Sep 2024 16:17:17 +0800 Subject: [PATCH 1303/2653] drm/amdkcl: test drm_vblank_crtc_config is available It's caused by 786628e0bf493cabcaa1c7a5ef5c27e2fa530c18 "drm/amd/display: use new vblank enable policy for DCN35+" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm_vblank_crtc_config .m4 | 19 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config .m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ecfeea3f123be..3e0b40ad32d74 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8924,6 +8924,7 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc, struct dm_crtc_state *acrtc_state) { +#ifdef HAVE_DRM_VBLANK_CRTC_CONFIG struct drm_vblank_crtc_config config = {0}; struct dc_crtc_timing *timing; int offdelay; @@ -8979,6 +8980,12 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, } else { drm_crtc_vblank_off(&acrtc->base); } +#else + if (acrtc_state) + drm_crtc_vblank_on(&acrtc->base); + else + drm_crtc_vblank_off(&acrtc->base); +#endif } static void dm_update_pflip_irq_state(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 064e9aa5b515e..33f2210e93097 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -620,6 +620,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 +/* drm_vblank_crtc_config is available */ +/* #undef HAVE_DRM_VBLANK_CRTC_CONFIG */ + /* struct drm_vma_offset_node has readonly field */ /* #undef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config .m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config .m4 new file mode 100644 index 0000000000000..90ef0ba2c3cc5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config .m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v5.11-20-g2d24dd5798d0 +dnl # rbtree: Add generic add and find helpers +dnl # +AC_DEFUN([AC_AMDGPU_DRM_VBLANK_CRTC_CONFIG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_vblank_crtc_config config; + ],[ + AC_DEFINE(HAVE_DRM_VBLANK_CRTC_CONFIG, 1, + [drm_vblank_crtc_config is available]) + ]) + ]) +]) + + + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index caf31276e4669..7115502fca61e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -104,6 +104,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_HAVE_HDR_SINK_METADATA AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_AMDGPU_DRM_MODE_CONFIG + AC_AMDGPU_DRM_VBLANK_CRTC_CONFIG AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_DRM_MODE_CREATE_COLORSPACE_PROPERTY_FUNCS From ac2478b868a36f2532cf9093944869cb14a8f04f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 20 Sep 2024 18:37:18 +0800 Subject: [PATCH 1304/2653] drm/amdkcl: wrap code out of HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT is for validate_dsc_caps_on_connector. It should not be guarding retrieve_downstream_port_device. Signed-off-by: Kent Russell --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 63b3029585ead..ea5c1b5b59623 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -339,6 +339,7 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto return true; } #endif +#endif static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector) { @@ -358,7 +359,6 @@ static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnect return true; } -#endif static int dm_dp_mst_get_modes(struct drm_connector *connector) { @@ -486,11 +486,10 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) memset(&aconnector->dc_sink->dsc_caps, 0, sizeof(aconnector->dc_sink->dsc_caps)); #endif - +#endif if (!retrieve_downstream_port_device(aconnector)) memset(&aconnector->mst_downstream_port_present, 0, sizeof(aconnector->mst_downstream_port_present)); -#endif } } From 7445a58354fa82228e338d06c27081cbbba78607 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 19 Sep 2024 15:38:15 +0800 Subject: [PATCH 1305/2653] drm/amdkcl: wrap code under macro DEFINE_DEBUGFS_ATTRIBUTE It's caused by 71372e402994d29b6d456b714e6e8608c8112e91 "drm/amdgpu: add amdgpu_jpeg_sched_mask debugfs" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c index 82d58ac7afb01..b409c5ef5b734 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c @@ -399,9 +399,15 @@ static int amdgpu_debugfs_jpeg_sched_mask_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_jpeg_sched_mask_fops, amdgpu_debugfs_jpeg_sched_mask_get, amdgpu_debugfs_jpeg_sched_mask_set, "%llx\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_jpeg_sched_mask_fops, + amdgpu_debugfs_jpeg_sched_mask_get, + amdgpu_debugfs_jpeg_sched_mask_set, "%llx\n"); +#endif #endif From ef7a588619e1e039de1ac0d52b97f1564928fd5c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 23 Sep 2024 13:22:28 +0800 Subject: [PATCH 1306/2653] drm/amdkcl: test drm_gem_prime_handle_to_dmabuf() is available It's caused by eeab2428df5a886d40c08f9847ea4d2c2fbce7e0 "drm/amdgpu: fix a race in kfd_mem_export_dmabuf()" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 14 ++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../dkms/m4/drm_gem_prime_handle_to_dmabuf.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_gem_prime_handle_to_dmabuf.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index fc6411b92e89e..1093bbd605868 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -805,12 +806,25 @@ static int kfd_mem_export_dmabuf(struct kgd_mem *mem) if (!mem->dmabuf) { struct amdgpu_device *bo_adev; struct dma_buf *dmabuf; +#ifndef HAVE_DRM_GEM_PRIME_HANDLE_TO_DMABUF + int r, fd; + bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); + r = drm_gem_prime_handle_to_fd(&bo_adev->ddev, bo_adev->kfd.client.file, + mem->gem_handle, + mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? + DRM_RDWR : 0, &fd); + if (r) + return r; + dmabuf = dma_buf_get(fd); + close_fd(fd); +#else bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); dmabuf = drm_gem_prime_handle_to_dmabuf(&bo_adev->ddev, bo_adev->kfd.client.file, mem->gem_handle, mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0); +#endif if (IS_ERR(dmabuf)) return PTR_ERR(dmabuf); mem->dmabuf = dmabuf; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 33f2210e93097..a3d47398d8c1c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -548,6 +548,9 @@ /* drm_gem_plane_helper_prepare_fb() is available */ #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 +/* drm_gem_prime_handle_to_dmabuf() is available */ +#define HAVE_DRM_GEM_PRIME_HANDLE_TO_DMABUF 1 + /* drm_gem_prime_handle_to_fd() is available */ #define HAVE_DRM_GEM_PRIME_HANDLE_TO_FD 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_gem_prime_handle_to_dmabuf.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_gem_prime_handle_to_dmabuf.m4 new file mode 100644 index 0000000000000..cfdf6da657222 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_gem_prime_handle_to_dmabuf.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.10-3140-ge9b641807e5e +dnl # drm: new helper: drm_gem_prime_handle_to_dmabuf() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_DMABUF], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_gem_prime_handle_to_dmabuf(NULL, NULL, 0, 0); + ],[drm_gem_prime_handle_to_dmabuf],[drivers/gpu/drm/drm_prime.c],[ + AC_DEFINE(HAVE_DRM_GEM_PRIME_HANDLE_TO_DMABUF, 1, + [drm_gem_prime_handle_to_dmabuf() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7115502fca61e..a1f792b4e62e3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -212,6 +212,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT AC_AMDGPU_VM_FLAGS_SET AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED + AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_DMABUF AC_AMDGPU_PID_TYPE AC_AMDGPU_FOLLOW_PFN AC_AMDGPU_IMPORT_GUID From ee1bcc3ec8de899d985e5fbdb20890d46ed5570b Mon Sep 17 00:00:00 2001 From: Bing Ma Date: Fri, 20 Sep 2024 10:46:49 -0700 Subject: [PATCH 1307/2653] drm/amdkfd: [SPM] Fix a crash issue when running SPM on latest kernel driver Root cause: Parameter type for amdgpu_amdkfd_free_gtt_mem() has changed. Fix: Change SPM code to match this change. Signed-off-by: Bing Ma Reviewed-by: James Zhu --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 6480e9c49f608..a9354d43bba3b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -62,7 +62,7 @@ static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) return -EFAULT; user_address = (uint64_t *)((uint64_t)spm->ubuf.user_addr + spm->size_copied); - // From RLC spec, ring_rptr = 0 points to spm->cpu_addr+0x20 + /* From RLC spec, ring_rptr = 0 points to spm->cpu_addr + 0x20 */ ring_buf = (uint64_t *)((uint64_t)spm->cpu_addr + spm->ring_rptr + 0x20); if (user_address == NULL) @@ -221,7 +221,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device goto out; acquire_spm_failure: - amdgpu_amdkfd_free_gtt_mem(adev, pdd->spm_cntr->spm_obj); + amdgpu_amdkfd_free_gtt_mem(adev, &pdd->spm_cntr->spm_obj); alloc_gtt_mem_failure: kfree(pdd->spm_cntr); @@ -250,7 +250,7 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device wake_up_all(&pdd->spm_cntr->spm_buf_wq); amdgpu_amdkfd_rlc_spm_release(adev, drm_priv_to_vm(pdd->drm_priv)); - amdgpu_amdkfd_free_gtt_mem(adev, pdd->spm_cntr->spm_obj); + amdgpu_amdkfd_free_gtt_mem(adev, &pdd->spm_cntr->spm_obj); spin_lock_irqsave(&pdd->spm_irq_lock, flags); kfree(pdd->spm_cntr); From 5f579a87c7005862560f3a1603c059f3b6eca1cd Mon Sep 17 00:00:00 2001 From: Bing Ma Date: Fri, 20 Sep 2024 11:13:12 -0700 Subject: [PATCH 1308/2653] drm/amdgpu: [SPM] Remove 'SPM Start' logic from gfx_v9_0_spm_start() We should start SPM only after all SPM configurations are done, otherwise we might see garbage data or other undefined behaviors. Because user mode module (profiler) is responsible for SPM configurations, we will let user mode module to start SPM. Signed-off-by: Bing Ma Acked-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 09353385b4772..91752afaef323 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4815,11 +4815,6 @@ static void gfx_v9_0_spm_start(struct amdgpu_device *adev) gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); - data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, - STRM_PERFMON_STATE_START_COUNTING); - gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, - SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); - gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_INT_CNTL), 1); } From abf5f75f6662892b67d0abb14cc080f6ead93a03 Mon Sep 17 00:00:00 2001 From: Bing Ma Date: Tue, 24 Sep 2024 16:58:03 -0700 Subject: [PATCH 1309/2653] drm/amd: [SPM] Reset SPM ringbuffer 'rptr' When SPM is reset When SPM is reset, RLC automatically resets wptr to 0. We need to manually reset rptr to match this. Signed-off-by: Bing Ma Reviewed-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 ++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 8 ++++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 91752afaef323..2d5c6089819f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4815,6 +4815,12 @@ static void gfx_v9_0_spm_start(struct amdgpu_device *adev) gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + /* When SPM is reset, RLC automatically resets wptr to 0. + * Manually reset rptr to match this. + */ + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), 0); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_INT_CNTL), 1); } @@ -4833,6 +4839,12 @@ static void gfx_v9_0_spm_stop(struct amdgpu_device *adev) CP_PERFMON_STATE_DISABLE_AND_RESET); gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + /* When SPM is reset, RLC automatically resets wptr to 0. + * Manually reset rptr to match this. + */ + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), 0); } static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index a9354d43bba3b..0827e2d4163c0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -371,6 +371,10 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev amdgpu_amdkfd_rlc_spm_cntl(adev, 1); spin_lock_irqsave(&pdd->spm_irq_lock, flags); spm->is_spm_started = true; + /* amdgpu_amdkfd_rlc_spm_cntl() will reset SPM and wptr will become 0. + * Adjust rptr accordingly + */ + spm->ring_rptr = 0; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); } else { /* If SPM was already started, there may already @@ -382,6 +386,10 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev amdgpu_amdkfd_rlc_spm_cntl(adev, 0); spin_lock_irqsave(&pdd->spm_irq_lock, flags); spm->is_spm_started = false; + /* amdgpu_amdkfd_rlc_spm_cntl() will reset SPM and wptr will become 0. + * Adjust rptr accordingly + */ + spm->ring_rptr = 0; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); } From 1eef89f1ba931d645e3cae1c9b534ceee54d5818 Mon Sep 17 00:00:00 2001 From: Bing Ma Date: Fri, 20 Sep 2024 15:29:40 -0700 Subject: [PATCH 1310/2653] drm/amdkfd: [SPM] Remove 'rptr = wptr' when 'is_user_buf_filled == true'. We cannot set rptr = wptr here, because wptr is always set at segment boundary and profiler uses this knowledge to parse SPM counters. But rptr is not always set at segment boundary, and if we force 'rptr = wptr', we might leave an incomplete segment to user mode profiler and profiler won't be able to parse the counter properly. Signed-off-by: Bing Ma Acked-by: James Zhu --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 0827e2d4163c0..9b829adfc8ed9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -103,9 +103,12 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) ring_wptr = READ_ONCE(spm->cpu_addr[0]); - /* keep SPM ring buffer running */ + /* SPM might stall if we cannot copy data out of SPM ringbuffer. + * spm->has_data_loss is only a hint here since stall is only a + * possibility and data loss might not happen. But it is a useful + * hint for user mode profiler to take extra actions. + */ if (!spm->has_user_buf || spm->is_user_buf_filled) { - spm->ring_rptr = ring_wptr; spm->has_data_loss = true; /* set flag due to there is no flag setup * when read ring buffer timeout. From 30d2be0511b552ab01adc6a81ab49c606065221c Mon Sep 17 00:00:00 2001 From: Bing Ma Date: Fri, 20 Sep 2024 15:33:02 -0700 Subject: [PATCH 1311/2653] drm/amdkfd: [SPM] Merge spm_copy_data_to_usr() and spm_set_dest_info() into one function spm_update_dest_info() The gap between the two functions will trigger unnecessary data loss condition in kfd_spm_read_ring_buffer(). Signed-off-by: Bing Ma Reviewed-by: James Zhu --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 45 +++++++++++++--------------- 1 file changed, 21 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 9b829adfc8ed9..45a81dd764eab 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -264,26 +264,24 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device return 0; } -static void spm_copy_data_to_usr(struct kfd_ioctl_spm_args *user_spm_data, - struct kfd_process_device *pdd) -{ - mutex_lock(&pdd->spm_cntr->spm_worker_mutex); - user_spm_data->bytes_copied = pdd->spm_cntr->size_copied; - user_spm_data->has_data_loss = pdd->spm_cntr->has_data_loss; - pdd->spm_cntr->has_user_buf = false; - mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); -} - -static void spm_set_dest_info(struct kfd_process_device *pdd, +static void spm_update_dest_info(struct kfd_process_device *pdd, struct kfd_ioctl_spm_args *user_spm_data) { + struct kfd_spm_cntr *spm = pdd->spm_cntr; mutex_lock(&pdd->spm_cntr->spm_worker_mutex); - pdd->spm_cntr->ubuf.user_addr = (uint64_t *)user_spm_data->dest_buf; - pdd->spm_cntr->ubuf.ubufsize = user_spm_data->buf_size; - pdd->spm_cntr->has_data_loss = false; - pdd->spm_cntr->size_copied = 0; - pdd->spm_cntr->is_user_buf_filled = false; - pdd->spm_cntr->has_user_buf = true; + if (spm->has_user_buf) { + user_spm_data->bytes_copied = spm->size_copied; + user_spm_data->has_data_loss = spm->has_data_loss; + spm->has_user_buf = false; + } + if (user_spm_data->dest_buf) { + spm->ubuf.user_addr = (uint64_t *)user_spm_data->dest_buf; + spm->ubuf.ubufsize = user_spm_data->buf_size; + spm->has_data_loss = false; + spm->size_copied = 0; + spm->is_user_buf_filled = false; + spm->has_user_buf = true; + } mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); } @@ -360,16 +358,15 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev flush_work(&pdd->spm_work); } - if (spm->has_user_buf) { - /* get info about filled space in previous output buffer */ - spm_copy_data_to_usr(user_spm_data, pdd); + if (spm->has_user_buf || user_spm_data->dest_buf) { + /* Get info about filled space in previous output buffer. + * Setup new dest buf if provided. + */ + spm_update_dest_info(pdd, user_spm_data); } if (user_spm_data->dest_buf) { - /* setup new dest buf, start streaming if necessary */ - spm_set_dest_info(pdd, user_spm_data); - - /* Start SPM */ + /* Start SPM if necessary*/ if (spm->is_spm_started == false) { amdgpu_amdkfd_rlc_spm_cntl(adev, 1); spin_lock_irqsave(&pdd->spm_irq_lock, flags); From 9d5d27d20e8c6a9b51ec0567264b4834a8958ac3 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Mon, 23 Sep 2024 10:15:39 -0400 Subject: [PATCH 1312/2653] drm/amdkfd: release spm when process destroy If process is killed, process destroy will be called. Signed-off-by: James Zhu Tested-by: Bing Ma --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + drivers/gpu/drm/amd/amdkfd/kfd_process.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 7bb5f80739f00..949ea9d1384de 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1676,6 +1676,7 @@ int kfd_send_exception_to_runtime(struct kfd_process *p, bool kfd_is_locked(struct kfd_dev *kfd); void kfd_spm_init_process_device(struct kfd_process_device *pdd); +int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev); int kfd_rlc_spm(struct kfd_process *p, void __user *data); /* PeerDirect support */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 1029f70533aeb..274d18a4a5d45 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1051,6 +1051,7 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) pdd->dev->id, p->lead_thread->pid); kfd_pc_sample_release(pdd); + kfd_release_spm(pdd, pdd->dev->adev); kfd_process_device_destroy_cwsr_dgpu(pdd); kfd_process_device_destroy_ib_mem(pdd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 45a81dd764eab..9a27949e00f59 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -235,7 +235,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device return ret; } -static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) { unsigned long flags; From d33cd8edce70047f85dae7a0844d8e15dde2dda2 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Mon, 23 Sep 2024 11:05:44 -0400 Subject: [PATCH 1313/2653] drm/amdkfd: workaround for spm overflow reserve space to avoid page fault and data loss. Signed-off-by: James Zhu Reviewed-by: Bing Ma --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 ++ drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 40 ++++++++++++++++++++++++++- 2 files changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 949ea9d1384de..17df472bea593 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -879,6 +879,8 @@ struct kfd_process_device { struct mutex spm_mutex; struct work_struct spm_work; spinlock_t spm_irq_lock; + /* reserve space to fix spm overflow */ + u32 spm_overflow_reserved; /* Eviction activity tracking */ uint64_t last_evict_timestamp; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 9a27949e00f59..d6a03240f36af 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -50,6 +50,21 @@ struct kfd_spm_cntr { bool is_spm_started; }; +/* used to detect SPM overflow */ +#define SPM_OVERFLOW_MAGIC 0xBEEFABCDDEADABCD + +static void kfd_spm_preset(struct kfd_process_device *pdd, u32 size) +{ + uint64_t *overflow_ptr, *overflow_end_ptr; + + overflow_ptr = (uint64_t *)((uint64_t)pdd->spm_cntr->cpu_addr + + pdd->spm_cntr->ring_size + 0x20); + overflow_end_ptr = overflow_ptr + (size >> 3); + /* SPM data filling is 0x20 alignment */ + for ( ; overflow_ptr < overflow_end_ptr; overflow_ptr += 4) + *overflow_ptr = SPM_OVERFLOW_MAGIC; +} + static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) { struct kfd_spm_cntr *spm = pdd->spm_cntr; @@ -97,6 +112,7 @@ static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) { struct kfd_spm_cntr *spm = pdd->spm_cntr; + u32 overflow_size = 0; u32 size_to_copy; int ret = 0; u32 ring_wptr; @@ -125,6 +141,19 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) size_to_copy = ring_wptr - spm->ring_rptr; ret = kfd_spm_data_copy(pdd, size_to_copy); } else { + uint64_t *ring_start, *ring_end; + + ring_start = (uint64_t *)((uint64_t)pdd->spm_cntr->cpu_addr + 0x20); + ring_end = ring_start + (pdd->spm_cntr->ring_size >> 3); + for ( ; overflow_size < pdd->spm_overflow_reserved; overflow_size += 0x20) { + uint64_t *overflow_ptr = ring_end + (overflow_size >> 3); + + if (*overflow_ptr == SPM_OVERFLOW_MAGIC) + break; + } + /* move overflow counters into ring buffer to avoid data loss */ + memcpy(ring_start, ring_end, overflow_size); + size_to_copy = spm->ring_size - spm->ring_rptr; ret = kfd_spm_data_copy(pdd, size_to_copy); @@ -143,6 +172,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) } exit: + kfd_spm_preset(pdd, overflow_size); amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->adev, spm->ring_rptr); return ret; } @@ -168,6 +198,10 @@ static void kfd_spm_work(struct work_struct *work) void kfd_spm_init_process_device(struct kfd_process_device *pdd) { + /* pre-gfx11 spm has a hardware bug to cause overflow */ + if (pdd->dev->adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 1)) + pdd->spm_overflow_reserved = 0x400; + mutex_init(&pdd->spm_mutex); pdd->spm_cntr = NULL; } @@ -202,7 +236,9 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device if (ret) goto alloc_gtt_mem_failure; - ret = amdgpu_amdkfd_rlc_spm_acquire(adev, drm_priv_to_vm(pdd->drm_priv), + /* reserve space to fix spm overflow */ + pdd->spm_cntr->ring_size -= pdd->spm_overflow_reserved; + ret = amdgpu_amdkfd_rlc_spm_acquire(adev, drm_priv_to_vm(pdd->drm_priv), pdd->spm_cntr->gpu_addr, pdd->spm_cntr->ring_size); /* @@ -221,6 +257,8 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device spin_lock_init(&pdd->spm_irq_lock); + kfd_spm_preset(pdd, pdd->spm_overflow_reserved); + goto out; acquire_spm_failure: From 9643e5870ffe732fdd19b634ad206feef3d23e5d Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Sun, 29 Sep 2024 11:50:28 +0800 Subject: [PATCH 1314/2653] drm/amdkcl: wrap code under HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE It's caused by c7de57033d9b55b4bdc89dfeae6f57ba45401032 "drm/amdgpu: Add sysfs nodes to get xcp details" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c index c417f86892207..abb801021c0e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c @@ -722,7 +722,9 @@ static const char *nps_desc[] = { [AMDGPU_NPS8_PARTITION_MODE] = "NPS8", }; +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(xcp_cfg_res_sysfs); +#endif #define to_xcp_attr(x) \ container_of(x, struct amdgpu_xcp_res_sysfs_attribute, attr) @@ -749,7 +751,11 @@ static const struct sysfs_ops xcp_cfg_res_sysfs_ops = { static const struct kobj_type xcp_cfg_res_sysfs_ktype = { .sysfs_ops = &xcp_cfg_res_sysfs_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = xcp_cfg_res_sysfs_groups, +#else + .default_attrs = xcp_cfg_res_sysfs_attrs, +#endif }; const char *xcp_res_names[] = { From 741685bad2d8d9f31da4b3a864f77afe6334fd01 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Sun, 29 Sep 2024 11:52:03 +0800 Subject: [PATCH 1315/2653] drm/amdkcl: test if macro __ATTR_RW_MODE is available It's caused by c7de57033d9b55b4bdc89dfeae6f57ba45401032 "drm/amdgpu: Add sysfs nodes to get xcp details" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c index abb801021c0e3..2017c321cdcb2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c @@ -856,7 +856,11 @@ static ssize_t xcp_config_store(struct kobject *kobj, } static struct kobj_attribute xcp_cfg_sysfs_mode = +#ifdef __ATTR_RW_MODE __ATTR_RW_MODE(xcp_config, 0644); +#else + __ATTR(xcp_config, 0644, xcp_config_show, xcp_config_store); +#endif static void xcp_cfg_sysfs_release(struct kobject *kobj) { From 318defe571d6b989d1b38a21be2835c80a2266bb Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 14 Oct 2024 10:54:32 +0800 Subject: [PATCH 1316/2653] drm/amdkcl: rename TAINT_CPU_OUT_OF_SPEC to TAINT_UNSAFE_SMP It's caused by fe6db14d2f114fce6a607d1b09f9d0a5d2b1a609 "drm/amd: Taint the kernel when enabling overdrive" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_kernel.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index d055fad138c19..47e8853f7e144 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -29,4 +29,9 @@ #define __GFP_KSWAPD_RECLAIM ((__force gfp_t)___GFP_KSWAPD_RECLAIM) /* kswapd can wake */ #endif /* ___GFP_KSWAPD_RECLAIM */ +/* v5.13-335-gf39650de687e ("kernel.h: split out panic and oops helpers") */ +#ifndef TAINT_CPU_OUT_OF_SPEC +#define TAINT_CPU_OUT_OF_SPEC TAINT_UNSAFE_SMP +#endif + #endif /* AMDKCL_KERNEL_H */ From 138cf8a99943f83f927f70dc650819e5c9be37a0 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 14 Oct 2024 11:08:17 +0800 Subject: [PATCH 1317/2653] drm/amdkcl: test whether pm_runtime_resume_and_get() is available It's caused by 718922a1d2231f11f73c7f0f12c351cbdaf1e808 "drm/amd/pm: use pm_runtime_resume_and_get" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/pm_runtime_resume_and_get.m4 | 16 +++++++++++ include/kcl/kcl_pm_runtime.h | 27 +++++++++++++++++++ 5 files changed, 48 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pm_runtime_resume_and_get.m4 create mode 100644 include/kcl/kcl_pm_runtime.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 013a98f215a07..dab965ea623e9 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -130,4 +130,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a3d47398d8c1c..bd071940a9d87 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -923,6 +923,9 @@ /* PIDTYPE is availablea */ #define HAVE_PIDTYPE_TGID 1 +/* pm_runtime_resume_and_get() is available */ +#define HAVE_PM_RUNTIME_RESUME_AND_GET 1 + /* pm_suspend_target_state is available */ #define HAVE_PM_SUSPEND_TARGET_STATE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a1f792b4e62e3..0c21455673640 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -243,6 +243,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SMCA_UMC_V2 AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE AC_AMDGPU_DRM_CRTC_VBLANK_CRTC + AC_AMDGPU_PM_RUNTIME_RESUME_AND_GET AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS AC_AMDGPU_ASSIGN_STR diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_runtime_resume_and_get.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_resume_and_get.m4 new file mode 100644 index 0000000000000..738b08a40004b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_resume_and_get.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.10-rc3-244-gdd8088d5a896 +dnl # PM: runtime: Add pm_runtime_resume_and_get to deal with usage counter +dnl # +AC_DEFUN([AC_AMDGPU_PM_RUNTIME_RESUME_AND_GET], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + pm_runtime_resume_and_get(NULL); + ],[ + AC_DEFINE(HAVE_PM_RUNTIME_RESUME_AND_GET, 1, + [pm_runtime_resume_and_get() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pm_runtime.h b/include/kcl/kcl_pm_runtime.h new file mode 100644 index 0000000000000..77513261a62b1 --- /dev/null +++ b/include/kcl/kcl_pm_runtime.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * pm.h - Power management interface + * + * Copyright (C) 2000 Andrew Henroid + */ +#ifndef KCL_KCL_PM_RUNTIME_H +#define KCL_KCL_PM_RUNTIME_H + +#include + +#ifndef HAVE_PM_RUNTIME_RESUME_AND_GET +static inline int pm_runtime_resume_and_get(struct device *dev) +{ + int ret; + + ret = __pm_runtime_resume(dev, RPM_GET_PUT); + if (ret < 0) { + pm_runtime_put_noidle(dev); + return ret; + } + + return 0; +} +#endif + +#endif From 51a041c168eb1399ddd2e1eb35577e20fc1a452f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 14 Oct 2024 16:45:18 +0800 Subject: [PATCH 1318/2653] drm/amdkcl: test whether pm_runtime_get_if_active() is available It's caused by e13590646ddac10c9a433c1d9d2d3ad8cbdad738 "drm/amd/pm: use pm_runtime_get_if_active for debugfs getters" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 6 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/pm_runtime_get_if_active.m4 | 25 +++++++++++++++++++ include/kcl/kcl_pm_runtime.h | 18 ++++++++++++- 4 files changed, 49 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index bd071940a9d87..18c055502207f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -923,6 +923,12 @@ /* PIDTYPE is availablea */ #define HAVE_PIDTYPE_TGID 1 +/* pm_runtime_get_if_active() has one parameters */ +#define HAVE_PM_RUNTIME_GET_IF_ACTIVE_1ARGS 1 + +/* pm_runtime_get_if_active() has two parameters */ +/* #undef HAVE_PM_RUNTIME_GET_IF_ACTIVE_2ARGS */ + /* pm_runtime_resume_and_get() is available */ #define HAVE_PM_RUNTIME_RESUME_AND_GET 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0c21455673640..ac4aeda94cf48 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -244,6 +244,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE AC_AMDGPU_DRM_CRTC_VBLANK_CRTC AC_AMDGPU_PM_RUNTIME_RESUME_AND_GET + AC_AMDGPU_PM_RUNTIME_GET_IF_ACTIVE AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS AC_AMDGPU_ASSIGN_STR diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 new file mode 100644 index 0000000000000..9615da53282ad --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 @@ -0,0 +1,25 @@ +dnl # +dnl # commit v5.6-rc4-1-gc111566bea7c +dnl # PM: runtime: Add pm_runtime_get_if_active() +dnl # +AC_DEFUN([AC_AMDGPU_PM_RUNTIME_GET_IF_ACTIVE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + pm_runtime_get_if_active(NULL); + ],[pm_runtime_get_if_active],[drivers\base\power\runtime.c],[ + AC_DEFINE(HAVE_PM_RUNTIME_GET_IF_ACTIVE_1ARGS, 1, + [pm_runtime_get_if_active() has one parameters]) + ],[ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + pm_runtime_get_if_active(NULL, 0); + ],[pm_runtime_get_if_active],[drivers\base\power\runtime.c],[ + AC_DEFINE(HAVE_PM_RUNTIME_GET_IF_ACTIVE_2ARGS, 1, + [pm_runtime_get_if_active() has two parameters]) + ]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pm_runtime.h b/include/kcl/kcl_pm_runtime.h index 77513261a62b1..54df71e7b5b24 100644 --- a/include/kcl/kcl_pm_runtime.h +++ b/include/kcl/kcl_pm_runtime.h @@ -24,4 +24,20 @@ static inline int pm_runtime_resume_and_get(struct device *dev) } #endif -#endif +#ifdef CONFIG_PM +#if defined(HAVE_PM_RUNTIME_GET_IF_ACTIVE_2ARGS) +static inline int _kcl_pm_runtime_get_if_active(struct device *dev) +{ + return pm_runtime_get_if_active(dev, true); +} +#define pm_runtime_get_if_active _kcl_pm_runtime_get_if_active +#elif !defined(HAVE_PM_RUNTIME_GET_IF_ACTIVE_1ARGS) +static inline int _kcl_pm_runtime_get_if_active(struct device *dev) +{ + return pm_runtime_get_if_in_use(dev); +} +#define pm_runtime_get_if_active _kcl_pm_runtime_get_if_active +#endif /* HAVE_PM_RUNTIME_GET_IF_ACTIVE_2ARGS */ +#endif /* CONFIG_PM */ + +#endif /* KCL_KCL_PM_RUNTIME_H */ \ No newline at end of file From 75aa2603968986d5fe2580695b9e0b26e995cd0f Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 15 Oct 2024 11:10:37 +0800 Subject: [PATCH 1319/2653] drm/amdkcl: Accounting pdd vram_usage for svm on non-upstream code It's caused by 9bc846f3ad947d195921926f225fe088f0acd9ec "drm/amdkfd: Accounting pdd vram_usage for svm" The pdd->vram_usage change from uint64_t type to atomic64_t type Signed-off-by: chengjya --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 76971e0a8a5f9..7b2402dc318fa 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2531,7 +2531,7 @@ static int criu_restore_memory_of_gpu_ipc(struct kfd_process_device *pdd, bo_bucket->restored_offset = offset; if ((bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) && !bo_priv->is_imported) /* Update the VRAM usage count */ - WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + bo_bucket->size); + atomic64_add(bo_bucket->size, &pdd->vram_usage); return 0; } From 634b306512268f7768da26db1b4ce15e9ab48278 Mon Sep 17 00:00:00 2001 From: chengjya Date: Thu, 24 Oct 2024 10:23:11 +0800 Subject: [PATCH 1320/2653] drm/amdkcl: test whether drm_dp_mst_edid_read is available It's caused by 7f082eb3011c4f1146436bbf9c550b7adbcf42ec "drm/amd/display: switch amdgpu_dm_connector to use struct drm_edid Signed-off-by: chengjya Reviewed-by: Bob Zhou --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 135 +++++++++++++++++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 8 ++ .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 22 +++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 45 ++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../drm/amd/dkms/m4/drm_dp_mst_edid_read.m4 | 16 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 7 files changed, 229 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_edid_read.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3e0b40ad32d74..f37026e7f1426 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3740,7 +3740,11 @@ void amdgpu_dm_update_connector_after_detect( aconnector->dc_sink = sink; dc_sink_retain(aconnector->dc_sink); amdgpu_dm_update_freesync_caps(connector, +#ifdef HAVE_DRM_DP_MST_EDID_READ aconnector->drm_edid); +#else + aconnector->edid); +#endif } else { amdgpu_dm_update_freesync_caps(connector, NULL); if (!aconnector->dc_sink) { @@ -3791,12 +3795,17 @@ void amdgpu_dm_update_connector_after_detect( aconnector->dc_sink = sink; dc_sink_retain(aconnector->dc_sink); if (sink->dc_edid.length == 0) { +#ifdef HAVE_DRM_DP_MST_EDID_READ aconnector->drm_edid = NULL; +#else + aconnector->edid = NULL; +#endif hdmi_cec_unset_edid(aconnector); if (aconnector->dc_link->aux_mode) { drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); } } else { +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct edid *edid = (const struct edid *)sink->dc_edid.raw_edid; aconnector->drm_edid = drm_edid_alloc(edid, sink->dc_edid.length); @@ -3806,6 +3815,15 @@ void amdgpu_dm_update_connector_after_detect( if (aconnector->dc_link->aux_mode) drm_dp_cec_attach(&aconnector->dm_dp_aux.aux, connector->display_info.source_physical_address); +#else + aconnector->edid = + (struct edid *)sink->dc_edid.raw_edid; + + hdmi_cec_set_edid(aconnector); + if (aconnector->dc_link->aux_mode) + drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, + aconnector->edid); +#endif } if (!aconnector->timing_requested) { @@ -3816,7 +3834,11 @@ void amdgpu_dm_update_connector_after_detect( "failed to create aconnector->requested_timing\n"); } +#ifdef HAVE_DRM_DP_MST_EDID_READ amdgpu_dm_update_freesync_caps(connector, aconnector->drm_edid); +#else + amdgpu_dm_update_freesync_caps(connector, aconnector->edid); +#endif #ifdef HAVE_HDR_SINK_METADATA update_connector_ext_caps(aconnector); #endif @@ -3827,8 +3849,12 @@ void amdgpu_dm_update_connector_after_detect( aconnector->num_modes = 0; dc_sink_release(aconnector->dc_sink); aconnector->dc_sink = NULL; +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_free(aconnector->drm_edid); aconnector->drm_edid = NULL; +#else + aconnector->edid = NULL; +#endif kfree(aconnector->timing_requested); aconnector->timing_requested = NULL; /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ @@ -7559,6 +7585,7 @@ static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct dc_link *dc_link = aconnector->dc_link; struct dc_sink *dc_em_sink = aconnector->dc_em_sink; +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid; struct i2c_adapter *ddc; struct drm_device *dev = connector->dev; @@ -7571,15 +7598,39 @@ static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) drm_edid = drm_edid_read_ddc(connector, ddc); drm_edid_connector_update(connector, drm_edid); if (!drm_edid) { +#else + struct edid *edid; + struct i2c_adapter *ddc; + + if (dc_link && dc_link->aux_mode) + ddc = &aconnector->dm_dp_aux.aux.ddc; + else + ddc = &aconnector->i2c->base; + + /* + * Note: drm_get_edid gets edid in the following order: + * 1) override EDID if set via edid_override debugfs, + * 2) firmware EDID if set via edid_firmware module parameter + * 3) regular DDC read. + */ + edid = drm_get_edid(connector, ddc); + if (!edid) { +#endif drm_err(dev, "No EDID found on connector: %s.\n", connector->name); return; } +#ifdef HAVE_DRM_DP_MST_EDID_READ aconnector->drm_edid = drm_edid; +#else + aconnector->edid = edid; +#endif /* Update emulated (virtual) sink's EDID */ if (dc_em_sink && dc_link) { +#ifdef HAVE_DRM_DP_MST_EDID_READ // FIXME: Get rid of drm_edid_raw() const struct edid *edid = drm_edid_raw(drm_edid); +#endif memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps)); memmove(dc_em_sink->dc_edid.raw_edid, edid, @@ -7621,6 +7672,7 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector) .link = aconnector->dc_link, .sink_signal = SIGNAL_TYPE_VIRTUAL }; +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid; const struct edid *edid; struct i2c_adapter *ddc; @@ -7633,16 +7685,42 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector) drm_edid = drm_edid_read_ddc(connector, ddc); drm_edid_connector_update(connector, drm_edid); if (!drm_edid) { +#else + struct dc_link *dc_link = aconnector->dc_link; + struct edid *edid; + struct i2c_adapter *ddc; + + if (dc_link->aux_mode) + ddc = &aconnector->dm_dp_aux.aux.ddc; + else + ddc = &aconnector->i2c->base; + + /* + * Note: drm_get_edid gets edid in the following order: + * 1) override EDID if set via edid_override debugfs, + * 2) firmware EDID if set via edid_firmware module parameter + * 3) regular DDC read. + */ + edid = drm_get_edid(connector, ddc); + if (!edid) { +#endif drm_err(connector->dev, "No EDID found on connector: %s.\n", connector->name); return; } +#ifdef HAVE_DRM_DP_MST_EDID_READ if (connector->display_info.is_hdmi) init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; aconnector->drm_edid = drm_edid; edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() +#else + if (drm_detect_hdmi_monitor(edid)) + init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; + + aconnector->edid = edid; +#endif aconnector->dc_em_sink = dc_link_add_remote_sink( aconnector->dc_link, (uint8_t *)edid, @@ -8412,17 +8490,28 @@ static void amdgpu_set_panel_orientation(struct drm_connector *connector) } static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid) +#else + struct edid *edid) +#endif { struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); +#ifdef HAVE_DRM_DP_MST_EDID_READ if (drm_edid) { +#else + if (edid) { +#endif /* empty probed_modes */ INIT_LIST_HEAD(&connector->probed_modes); amdgpu_dm_connector->num_modes = +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_connector_add_modes(connector); - +#else + drm_add_edid_modes(connector, edid); +#endif /* sorting the probed modes before calling function * amdgpu_dm_get_native_mode() since EDID can have * more than one preferred mode. The modes that are @@ -8438,7 +8527,11 @@ static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, * drm_edid_connector_add_modes() and need to be * restored here. */ +#ifdef HAVE_DRM_DP_MST_EDID_READ amdgpu_dm_update_freesync_caps(connector, drm_edid); +#else + amdgpu_dm_update_freesync_caps(connector, edid); +#endif } else { amdgpu_dm_connector->num_modes = 0; } @@ -8538,12 +8631,20 @@ static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) } static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid) +#else + struct edid *edid) +#endif { struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); +#ifdef HAVE_DRM_DP_MST_EDID_READ if (!(amdgpu_freesync_vid_mode && drm_edid)) +#else + if (!(amdgpu_freesync_vid_mode && edid)) +#endif return; if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) @@ -8556,25 +8657,41 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); struct drm_encoder *encoder; +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid = amdgpu_dm_connector->drm_edid; +#else + struct edid *edid = amdgpu_dm_connector->edid; +#endif struct dc_link_settings *verified_link_cap = &amdgpu_dm_connector->dc_link->verified_link_cap; const struct dc *dc = amdgpu_dm_connector->dc_link->dc; encoder = amdgpu_dm_connector_to_encoder(connector); +#ifdef HAVE_DRM_DP_MST_EDID_READ if (!drm_edid) { +#else + if (!edid) { +#endif amdgpu_dm_connector->num_modes = drm_add_modes_noedid(connector, 640, 480); if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) amdgpu_dm_connector->num_modes += drm_add_modes_noedid(connector, 1920, 1080); } else { +#ifdef HAVE_DRM_DP_MST_EDID_READ amdgpu_dm_connector_ddc_get_modes(connector, drm_edid); +#else + amdgpu_dm_connector_ddc_get_modes(connector, edid); +#endif if (encoder && (connector->connector_type != DRM_MODE_CONNECTOR_eDP) && (connector->connector_type != DRM_MODE_CONNECTOR_LVDS)) amdgpu_dm_connector_add_common_modes(encoder, connector); +#ifdef HAVE_DRM_DP_MST_EDID_READ amdgpu_dm_connector_add_freesync_modes(connector, drm_edid); +#else + amdgpu_dm_connector_add_freesync_modes(connector, edid); +#endif } amdgpu_dm_fbc_init(connector); @@ -12840,7 +12957,11 @@ static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, * FreeSync parameters. */ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid) +#else + struct edid *edid) +#endif { int i = 0; struct amdgpu_dm_connector *amdgpu_dm_connector = @@ -12849,7 +12970,9 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, struct dc_sink *sink; struct amdgpu_device *adev = drm_to_adev(connector->dev); struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct edid *edid; +#endif bool freesync_capable = false; enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; @@ -12862,9 +12985,13 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, amdgpu_dm_connector->dc_sink : amdgpu_dm_connector->dc_em_sink; +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_connector_update(connector, drm_edid); if (!drm_edid || !sink) { +#else + if (!edid || !sink) { +#endif dm_con_state = to_dm_connector_state(connector->state); amdgpu_dm_connector->min_vfreq = 0; @@ -12879,7 +13006,9 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (!adev->dm.freesync_module) goto update; +#ifdef HAVE_DRM_DP_MST_EDID_READ edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() +#endif #ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE /* Some eDP panels only have the refresh rate range info in DisplayID */ @@ -12907,7 +13036,11 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP; } +#ifdef HAVE_DRM_DP_MST_EDID_READ } else if (drm_edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { +#else + } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { +#endif i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); if (i >= 0 && vsdb_info.freesync_supported) { amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 30d25f7037ddf..eaacdbd17e6cf 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -737,7 +737,11 @@ struct amdgpu_dm_connector { /* we need to mind the EDID between detect and get modes due to analog/digital/tvencoder */ +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid; +#else + struct edid *edid; +#endif /* shared with amdgpu */ struct amdgpu_hpd hpd; @@ -1019,7 +1023,11 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector); void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid); +#else + struct edid *edid); +#endif void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index e2a3f4283c2d0..715aa904155bf 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -1161,6 +1161,7 @@ bool dm_helpers_is_dp_sink_present(struct dc_link *link) return dp_sink_present; } +#ifdef HAVE_DRM_DP_MST_EDID_READ static int dm_helpers_probe_acpi_edid(void *data, u8 *buf, unsigned int block, size_t len) { @@ -1221,6 +1222,7 @@ dm_helpers_read_acpi_edid(struct amdgpu_dm_connector *aconnector) return drm_edid_read_custom(connector, dm_helpers_probe_acpi_edid, connector); } +#endif enum dc_edid_status dm_helpers_read_local_edid( struct dc_context *ctx, @@ -1234,7 +1236,9 @@ enum dc_edid_status dm_helpers_read_local_edid( struct i2c_adapter *ddc; int retry = 3; enum dc_edid_status edid_status; +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid; +#endif const struct edid *edid; if (link->aux_mode) @@ -1246,28 +1250,42 @@ enum dc_edid_status dm_helpers_read_local_edid( * do check sum and retry to make sure read correct edid. */ do { +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid = dm_helpers_read_acpi_edid(aconnector); if (drm_edid) drm_info(connector->dev, "Using ACPI provided EDID for %s\n", connector->name); else drm_edid = drm_edid_read_ddc(connector, ddc); drm_edid_connector_update(connector, drm_edid); +#else + edid = drm_get_edid(&aconnector->base, ddc); +#endif #ifdef HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM /* DP Compliance Test 4.2.2.6 */ if (link->aux_mode && connector->edid_corrupt) drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); +#ifdef HAVE_DRM_DP_MST_EDID_READ if (!drm_edid && connector->edid_corrupt) { +#else + if (!edid && connector->edid_corrupt) { +#endif connector->edid_corrupt = false; return EDID_BAD_CHECKSUM; } #endif +#ifdef HAVE_DRM_DP_MST_EDID_READ if (!drm_edid) +#else + if (!edid) +#endif return EDID_NO_RESPONSE; +#ifdef HAVE_DRM_DP_MST_EDID_READ edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() +#endif if (!edid || edid->extensions >= sizeof(sink->dc_edid.raw_edid) / EDID_LENGTH) return EDID_BAD_INPUT; @@ -1276,7 +1294,11 @@ enum dc_edid_status dm_helpers_read_local_edid( memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); /* We don't need the original edid anymore */ +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_free(drm_edid); +#else + kfree(edid); +#endif edid_status = dm_helpers_parse_edid_caps( link, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index ea5c1b5b59623..2b537b9b3f4b8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -173,7 +173,11 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector) } #endif +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_free(aconnector->drm_edid); +#else + kfree(aconnector->edid); +#endif drm_connector_cleanup(connector); #if defined(HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC) @@ -206,9 +210,15 @@ amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) static inline void amdgpu_dm_mst_reset_mst_connector_setting(struct amdgpu_dm_connector *aconnector) { +#ifdef HAVE_DRM_DP_MST_EDID_READ aconnector->drm_edid = NULL; +#else + aconnector->edid = NULL; +#endif aconnector->dsc_aux = NULL; +#ifdef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX aconnector->mst_output_port->passthrough_aux = NULL; +#endif aconnector->mst_local_bw = 0; aconnector->vc_full_pbn = 0; } @@ -368,6 +378,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) if (!aconnector) return drm_add_edid_modes(connector, NULL); +#ifdef HAVE_DRM_DP_MST_EDID_READ if (!aconnector->drm_edid) { const struct drm_edid *drm_edid; @@ -376,12 +387,25 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) aconnector->mst_output_port); if (!drm_edid) { +#else + if (!aconnector->edid) { + struct edid *edid; + edid = drm_dp_mst_get_edid(connector, &aconnector->mst_root->mst_mgr, aconnector->mst_output_port); + + if (!edid) { +#endif amdgpu_dm_set_mst_status(&aconnector->mst_status, MST_REMOTE_EDID, false); +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_connector_update( &aconnector->base, NULL); +#else + drm_connector_update_edid_property( + &aconnector->base, + NULL); +#endif DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name); if (!aconnector->dc_sink) { @@ -413,7 +437,11 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) return ret; } +#ifdef HAVE_DRM_DP_MST_EDID_READ aconnector->drm_edid = drm_edid; +#else + aconnector->edid = edid; +#endif amdgpu_dm_set_mst_status(&aconnector->mst_status, MST_REMOTE_EDID, true); } @@ -428,13 +456,20 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) struct dc_sink_init_data init_params = { .link = aconnector->dc_link, .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct edid *edid; edid = drm_edid_raw(aconnector->drm_edid); // FIXME: Get rid of drm_edid_raw() +#endif dc_sink = dc_link_add_remote_sink( aconnector->dc_link, +#ifdef HAVE_DRM_DP_MST_EDID_READ (uint8_t *)edid, (edid->extensions + 1) * EDID_LENGTH, +#else + (uint8_t *)aconnector->edid, + (aconnector->edid->extensions + 1) * EDID_LENGTH, +#endif &init_params); if (!dc_sink) { @@ -478,7 +513,11 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) if (aconnector->dc_sink) { amdgpu_dm_update_freesync_caps( +#ifdef HAVE_DRM_DP_MST_EDID_READ connector, aconnector->drm_edid); +#else + connector, aconnector->edid); +#endif #if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) #if defined(CONFIG_DRM_AMD_DC_FP) @@ -493,10 +532,16 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) } } +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_connector_update(&aconnector->base, aconnector->drm_edid); ret = drm_edid_connector_add_modes(connector); +#else + drm_connector_update_edid_property( + &aconnector->base, aconnector->edid); + ret = drm_add_edid_modes(connector, aconnector->edid); +#endif return ret; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 18c055502207f..27ba4dd1b2a5b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -377,6 +377,9 @@ /* drm_dp_mst_dsc_aux_for_port() is available */ #define HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT 1 +/* drm_dp_mst_edid_read() is available */ +#define HAVE_DRM_DP_MST_EDID_READ 1 + /* drm_dp_mst_{get,put}_port_malloc() is available */ #define HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_edid_read.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_edid_read.m4 new file mode 100644 index 0000000000000..6d733484238af --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_edid_read.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.4-rc2-497-gc1c9042b2003 +dnl # drm/display/dp_mst: convert to struct drm_edid +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_EDID_READ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_mst_edid_read(NULL, NULL, NULL); + ], [drm_dp_mst_edid_read], [drivers/gpu/drm/display/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_EDID_READ, 1, + [drm_dp_mst_edid_read() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ac4aeda94cf48..2a6aa944142a7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -247,6 +247,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PM_RUNTIME_GET_IF_ACTIVE AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS AC_AMDGPU_ASSIGN_STR + AC_AMDGPU_DRM_DP_MST_EDID_READ AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From d24906e38ecce35dc85bc746803ac9bddafb9aa9 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 21 Oct 2024 16:05:17 +0800 Subject: [PATCH 1321/2653] drm/amdkcl: test whether usleep_range_state() is available It's caused by 4ba1ee36b0f95cb5a2f639e7d7ba959f75496db3 "drm/amd/display: Add a Precise Delay Routine" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/usleep_range_state.m4 | 17 +++++++++++++++++ include/kcl/kcl_delay.h | 18 ++++++++++++++++++ 4 files changed, 39 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 27ba4dd1b2a5b..02543c1b8d2d3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1047,6 +1047,9 @@ /* __poll_t is available */ #define HAVE_TYPE__POLL_T 1 +/* usleep_range_stat() is available */ +#define HAVE_USLEEP_RANGE_STATE 1 + /* vga_client_register() don't pass a cookie */ #define HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2a6aa944142a7..995858844b4f0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -34,6 +34,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ZONE_MANAGED_PAGES AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_AMDGPU_FSLEEP + AC_AMDGPU_USLEEP_RANGE_STATE AC_AMDGPU_VMF_INSERT AC_AMDGPU_VMF_INSERT_MIXED_PROT AC_AMDGPU_VMF_INSERT_PFN_PROT diff --git a/drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 b/drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 new file mode 100644 index 0000000000000..7540052fefc59 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.16-rc4-168-ge4779015fd5d +dnl # timers: implement usleep_idle_range() +dnl # +AC_DEFUN([AC_AMDGPU_USLEEP_RANGE_STATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ], [ + usleep_range_state(0, 0, TASK_UNINTERRUPTIBLE); + ], [usleep_range_state], [kernel/time/timer.c], [ + AC_DEFINE(HAVE_USLEEP_RANGE_STATE, 1, + [usleep_range_state() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_delay.h b/include/kcl/kcl_delay.h index f5f2962c6bb6d..a7e76948be28c 100644 --- a/include/kcl/kcl_delay.h +++ b/include/kcl/kcl_delay.h @@ -1,6 +1,10 @@ #ifndef AMDKCL_DELAY_H #define AMDKCL_DELAY_H +#include +#include +#include + #ifndef HAVE_FSLEEP static inline void _kcl_fsleep(unsigned long usecs) { @@ -15,4 +19,18 @@ static inline void _kcl_fsleep(unsigned long usecs) #define fsleep _kcl_fsleep #endif + +#ifndef HAVE_USLEEP_RANGE_STATE +static inline void _kcl_usleep_range_state(unsigned long min, unsigned long max, + unsigned int state) +{ + if (state != TASK_UNINTERRUPTIBLE) + pr_warn_once("legacy kernel without usleep_range_state()\n"); + + usleep_range(min, max); +} + +#define usleep_range_state _kcl_usleep_range_state +#endif + #endif From c6032724da26f8bee1d2c8c3ec7586fdee2a4b96 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 15 Oct 2024 13:53:05 +0800 Subject: [PATCH 1322/2653] drm/amdkcl: test whether drm_dp_cec_attach() is available It's caused by 73497e063c6dc0d6d9224175475ada8b67a60907 "drm/amd/display: switch to setting physical address directly" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 ++++++--------- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm_dp_cec_attach.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 26 insertions(+), 9 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_cec_attach.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f37026e7f1426..9465dd36cd63d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3805,24 +3805,21 @@ void amdgpu_dm_update_connector_after_detect( drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); } } else { -#ifdef HAVE_DRM_DP_MST_EDID_READ const struct edid *edid = (const struct edid *)sink->dc_edid.raw_edid; - +#ifdef HAVE_DRM_DP_MST_EDID_READ aconnector->drm_edid = drm_edid_alloc(edid, sink->dc_edid.length); drm_edid_connector_update(connector, aconnector->drm_edid); +#else + aconnector->edid = edid; +#endif hdmi_cec_set_edid(aconnector); if (aconnector->dc_link->aux_mode) +#ifdef HAVE_DRM_DP_CEC_ATTACH drm_dp_cec_attach(&aconnector->dm_dp_aux.aux, connector->display_info.source_physical_address); #else - aconnector->edid = - (struct edid *)sink->dc_edid.raw_edid; - - hdmi_cec_set_edid(aconnector); - if (aconnector->dc_link->aux_mode) - drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, - aconnector->edid); + drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, edid); #endif } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 02543c1b8d2d3..d84697b3220a6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -335,6 +335,9 @@ /* drm_dp_calc_pbn_mode() wants 3 args */ /* #undef HAVE_DRM_DP_CALC_PBN_MODE_3ARGS */ +/* drm_dp_cec_attach() is available */ +#define HAVE_DRM_DP_CEC_ATTACH 1 + /* drm_dp_cec_register_connector() wants p,p interface */ #define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_cec_attach.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_cec_attach.m4 new file mode 100644 index 0000000000000..b17bff9ecd850 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_cec_attach.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.5-rc2-872-g113cdddcded6 +dnl # drm/cec: add drm_dp_cec_attach() as the non-edid version of set edid +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_ATTACH], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_cec_attach(NULL, 0); + ], [drm_dp_cec_attach], [drivers/gpu/drm/display/drm_dp_cec.c], [ + AC_DEFINE(HAVE_DRM_DP_CEC_ATTACH, 1, + [drm_dp_cec_attach() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 995858844b4f0..8b123ff6002f2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -249,6 +249,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS AC_AMDGPU_ASSIGN_STR AC_AMDGPU_DRM_DP_MST_EDID_READ + AC_AMDGPU_DRM_DP_CEC_ATTACH AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From bcaeb1c038e04ee7106b324ad796796a8fe4aebe Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 28 Oct 2024 17:21:46 +0800 Subject: [PATCH 1323/2653] drm/amdkcl: update initrd for oot build Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec index dd92860353f46..5f00c10afe2db 100644 --- a/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec +++ b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec @@ -60,6 +60,7 @@ if [ -x "/usr/sbin/weak-modules" ]; then printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules fi +dracut -f --kver %{kernel}.%{_arch} %preun echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdgpu.ko" >> /var/run/rpm-%{pkg}-modules.list @@ -78,6 +79,7 @@ if [ -x "/usr/sbin/weak-modules" ]; then printf '%s\n' "${modules[@]}" | /usr/sbin/weak-modules --no-initramfs --remove-modules fi rm /var/run/rpm-%{pkg}-modules.list +dracut -f --kver %{kernel}.%{_arch} %files /lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdgpu.ko From fab3c5ca606a8422301864128cf1e67b6a8ae457 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 28 Oct 2024 14:29:00 +0800 Subject: [PATCH 1324/2653] drm/amdkcl: fix miss code under HAVE_DRM_DP_MST_EDID_READ It's caused by 457fdc01f440a3ac2c32d9784fd015f112da7692 "drm/amd/display: always call connector_update when parsing freesync_caps" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9465dd36cd63d..6006ff1b13a68 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12987,6 +12987,8 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (!drm_edid || !sink) { #else + drm_connector_update_edid_property(connector, edid); + if (!edid || !sink) { #endif dm_con_state = to_dm_connector_state(connector->state); From 84fac8c55738a8624e89539d41d20fe3b6cba6cf Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 29 Oct 2024 13:51:36 +0800 Subject: [PATCH 1325/2653] drm/amdkcl: fake pm_resume_via_firmware under HAVE_PM_SUSPEND_VIA_FIRMWARE It's caused by following commit 14c2c55eca4b07a2cbe7fd62562f8cf9c327c1cd "drm/amdgpu: correct the S3 abort check condition" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- include/kcl/kcl_suspend.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/kcl/kcl_suspend.h b/include/kcl/kcl_suspend.h index fb2c02994f763..8c11fe68bb540 100644 --- a/include/kcl/kcl_suspend.h +++ b/include/kcl/kcl_suspend.h @@ -17,6 +17,8 @@ static inline void ksys_sync_helper(void) {} #ifndef HAVE_PM_SUSPEND_VIA_FIRMWARE static inline bool pm_suspend_via_firmware(void) { return false; } + +static inline bool pm_resume_via_firmware(void) { return false; } #endif /* HAVE_PM_SUSPEND_VIA_FIRMWARE */ #endif /* AMDKCL_SUSPEND_H */ From d92aa08a95274099e54bb971259ef80f302db560 Mon Sep 17 00:00:00 2001 From: chengjya Date: Wed, 30 Oct 2024 17:16:15 +0800 Subject: [PATCH 1326/2653] drm/amdkcl: fix missing header file It's caused by following commit 14c2c55eca4b07a2cbe7fd62562f8cf9c327c1cd "drm/amdgpu: correct the S3 abort check condition" This commit fixes a compilation issue caused by linux/suspend.h that isn't included in some c files in older kernel versions. Signed-off-by: chengjya Reviewed-by: Bob Zhou --- include/kcl/kcl_suspend.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/kcl/kcl_suspend.h b/include/kcl/kcl_suspend.h index 8c11fe68bb540..e08385f9aedaa 100644 --- a/include/kcl/kcl_suspend.h +++ b/include/kcl/kcl_suspend.h @@ -2,6 +2,8 @@ #ifndef AMDKCL_SUSPEND_H #define AMDKCL_SUSPEND_H +#include + #ifndef HAVE_KSYS_SYNC_HELPER #ifdef CONFIG_PM_SLEEP extern void _kcl_ksys_sync_helper(void); From ae67c4374b970bcaaadff1be4b15c4467e95f1e9 Mon Sep 17 00:00:00 2001 From: Cruz Zhao Date: Thu, 31 Oct 2024 12:33:05 +0800 Subject: [PATCH 1327/2653] drm/amdkfd: fix the incorrect exception handling logic in function amd_acquire() In function amd_acquire(), kfd_get_process() is call to get process. When judge whether we get an exception pointer, we shouldn't judge whether it's a null pointer, because kfd_get_process will return ERR_PTR(-EINVAL) instead of null pointer if error. Because of this wrong logic, the kernel will panic then once kfd_get_process() returns ERR_PTR(-EINVAL). So, the correct logic should be: if (IS_ERR(p)) { Fixes: commit 779b4d05a1c9("drm/amdkfd: Add RDMA and PeerDirect support") Signed-off-by: Cruz Zhao Signed-off-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index 637a6ceaffefe..ed93247d83caa 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -178,7 +178,7 @@ static int amd_acquire(unsigned long addr, size_t size, p = peer_mem_private_data; } else { p = kfd_get_process(current); - if (!p) { + if (IS_ERR(p)) { pr_debug("Not a KFD process\n"); return 0; } From 8084b127f8b141d4277375d2435a8c764633e5b6 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 11 Nov 2024 19:32:12 +0800 Subject: [PATCH 1328/2653] drm/amdkcl: check whether .fop_flags is in file_operation It's caused by v6.9-rc1-17-g210a03c9d51a fs: claw back a few FMODE_* bits Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 | 21 +++++++++++++++++++++ 3 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 637717dcb2d05..887091730dfe0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3060,7 +3060,9 @@ static const struct file_operations amdgpu_driver_kms_fops = { #ifdef CONFIG_PROC_FS .show_fdinfo = drm_show_fdinfo, #endif +#ifdef HAVE_FILE_OPERATION_FOP_FLAGS .fop_flags = FOP_UNSIGNED_OFFSET, +#endif }; int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8b123ff6002f2..2699bc6743974 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -250,6 +250,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ASSIGN_STR AC_AMDGPU_DRM_DP_MST_EDID_READ AC_AMDGPU_DRM_DP_CEC_ATTACH + AC_AMDGPU_STRUCT_FILE_OPERATION AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 new file mode 100644 index 0000000000000..07011778633f9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v6.9-rc1-17-g210a03c9d51a +dnl # fs: claw back a few FMODE_* bits +dnl # +AC_DEFUN([AC_AMDGPU_FILE_OPERATION_FOP_FLAGS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct file_operations file_operation; + file_operation.fop_flags = 0; + ],[ + AC_DEFINE(HAVE_FILE_OPERATION_FOP_FLAGS, 1, + [file_operation->fop_flags is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_FILE_OPERATION], [ + AC_AMDGPU_FILE_OPERATION_FOP_FLAGS +]) From 1067102d748b0cca3b3aafd8be10574f5296df2d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 11 Nov 2024 19:51:59 +0800 Subject: [PATCH 1329/2653] drm/amdkcl: fake linux/unasigned.h It's caused by v6.12-rc1-3-g5f60d5f6bbc1 move asm/unaligned.h to linux/unaligned.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 5 +++++ include/kcl/header/linux/unaligned.h | 12 ++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 include/kcl/header/linux/unaligned.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 6b06ae6f73fef..a8bcd262b8440 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -117,4 +117,9 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_fbdev_ttm.h]) + dnl # + dnl # v6.12-rc1-3-g5f60d5f6bbc1 + dnl # move asm/unaligned.h to linux/unaligned.h + dnl # + AC_KERNEL_CHECK_HEADERS([linux/unaligned.h]) ]) diff --git a/include/kcl/header/linux/unaligned.h b/include/kcl/header/linux/unaligned.h new file mode 100644 index 0000000000000..e64489be09fe2 --- /dev/null +++ b/include/kcl/header/linux/unaligned.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_UNALIGNED_H +#define _KCL_HEADER_LINUX_UNALIGNED_H + +#ifdef HAVE_LINUX_UNALIGNED_H +#include_next +#else +#include +#endif + +#endif + From 546eb10963bbf9e43417aef9766e97856d5f0456 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 11 Nov 2024 20:05:26 +0800 Subject: [PATCH 1330/2653] drm/amdkcl: define macro BACKLIGHT_POWER_ON It's caused by v6.10-rc1-7-ga1cacb8a8e70 backlight: Add BACKLIGHT_POWER_ constants for power states Signed-off-by: Asher Song --- include/kcl/kcl_backlight.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/kcl/kcl_backlight.h b/include/kcl/kcl_backlight.h index 1d06b61502c3c..bc2696815393d 100644 --- a/include/kcl/kcl_backlight.h +++ b/include/kcl/kcl_backlight.h @@ -13,4 +13,11 @@ int backlight_device_set_brightness(struct backlight_device *bd, unsigned long brightness); #endif /* HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS */ + +#ifndef BACKLIGHT_POWER_ON +#define BACKLIGHT_POWER_ON (0) +#define BACKLIGHT_POWER_OFF (4) +#define BACKLIGHT_POWER_REDUCED (1) // deprecated; don't use in new code +#endif + #endif From 6942ecb558190578c610502fb6251c2f173b2841 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 11 Nov 2024 20:41:52 +0800 Subject: [PATCH 1331/2653] drm/amdkcl: define macro fd_file It's caused by v6.11-rc1-1-g1da91ea87aef introduce fd_file(), convert all accessors to it. Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_file.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/kcl/kcl_file.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index dab965ea623e9..94639bcc8e4bc 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -131,4 +131,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_file.h b/include/kcl/kcl_file.h new file mode 100644 index 0000000000000..2b81dc3f31644 --- /dev/null +++ b/include/kcl/kcl_file.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_LINUX_FILE_H +#define AMDKCL_LINUX_FILE_H + +#include + +#ifndef fd_file +#define fd_file(f) ((f).file) +#endif + +#endif From 0a4176f22e8d846727fa6727a368b38bd6190a8d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 12 Nov 2024 11:50:21 +0800 Subject: [PATCH 1332/2653] drm/amdkcl: check macro MAX whether exists in linux/minmax.h It's caused by v6.11-rc1-1-g1a251f52cfdc minmax: make generic MIN() and MAX() macros available everywhere Signed-off-by: Asher Song --- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 59f9abd0f7b8c..1fbcee82a17b3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -803,7 +803,12 @@ static const char *smu_get_feature_name(struct smu_context *smu, size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu, char *buf) { +#ifdef MAX int8_t sort_feature[MAX(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)]; +#else + int8_t sort_feature[max(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)]; +#endif + uint64_t feature_mask; int i, feature_index; uint32_t count = 0; From 644553bc94a2c05c1387b8465fbe7efc2f4b039e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 13 Nov 2024 14:46:43 +0800 Subject: [PATCH 1333/2653] drm/amdkcl: test follow_pfnmap_start whether exist It's caused by v6.11-rc6-389-g6da8e9634bb7 mm: new follow_pfnmap API Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/kcl_memory.c | 15 ++++++++++++++- drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 | 20 +++++++++++++++++++- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/backport/kcl_memory.c b/drivers/gpu/drm/amd/backport/kcl_memory.c index 153710b6883de..2ade0fbdbc8e1 100644 --- a/drivers/gpu/drm/amd/backport/kcl_memory.c +++ b/drivers/gpu/drm/amd/backport/kcl_memory.c @@ -5,14 +5,27 @@ int _kcl_follow_pfn(struct vm_area_struct *vma, unsigned long address, unsigned long *pfn) { int ret = -EINVAL; +#ifdef HAVE_FOLLOW_PFNMAP_START + struct follow_pfnmap_args args = { + .vma = vma, + .address = address, + }; + ret = follow_pfnmap_start(&args); + + if (ret) + return ret; + *pfn = args.pfn; + follow_pfnmap_end(&args); +#else spinlock_t *ptl; pte_t *ptep; - ret = follow_pte(vma, address, &ptep, &ptl); + if (ret) return ret; *pfn = pte_pfn(ptep_get(ptep)); pte_unmap_unlock(ptep, ptl); +#endif return 0; } diff --git a/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 b/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 index ea2c47c00ab90..e702269ad9e9e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 @@ -13,4 +13,22 @@ AC_DEFUN([AC_AMDGPU_FOLLOW_PFN], [ [follow_pfn() is available]) ]) ]) -]) \ No newline at end of file +]) + +dnl # +dnl # v6.11-rc6-389-g6da8e9634bb7 +dnl # mm: new follow_pfnmap API +dnl # +AC_DEFUN([AC_AMDGPU_FOLLOW_PFNMAP_START], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + follow_pfnmap_start(NULL); + ],[follow_pfnmap_start], [mm/memory.c],[ + AC_DEFINE(HAVE_FOLLOW_PFNMAP_START, 1, + [follow_pfnmap_start() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2699bc6743974..f3b91beec76b9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -251,6 +251,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_EDID_READ AC_AMDGPU_DRM_DP_CEC_ATTACH AC_AMDGPU_STRUCT_FILE_OPERATION + AC_AMDGPU_FOLLOW_PFNMAP_START AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 2070e4b6c3f49153bdfe893f2f6ad19a1c86d99b Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 5 Nov 2024 11:29:58 +0800 Subject: [PATCH 1334/2653] drm/amdkcl: wrap code under DEFINE_DEBUGFS_ATTRIBUTE It's caused by following commit: b8521b1a8e7d0b "drm/amdgpu: add amdgpu_gfx_sched_mask and amdgpu_compute_sched_mask debugfs" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index c80c8f5435321..e010155fd246b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -2388,9 +2388,15 @@ static int amdgpu_debugfs_gfx_sched_mask_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gfx_sched_mask_fops, amdgpu_debugfs_gfx_sched_mask_get, amdgpu_debugfs_gfx_sched_mask_set, "%llx\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_gfx_sched_mask_fops, + amdgpu_debugfs_gfx_sched_mask_get, + amdgpu_debugfs_gfx_sched_mask_set, "%llx\n"); +#endif #endif @@ -2459,9 +2465,15 @@ static int amdgpu_debugfs_compute_sched_mask_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_compute_sched_mask_fops, amdgpu_debugfs_compute_sched_mask_get, amdgpu_debugfs_compute_sched_mask_set, "%llx\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_compute_sched_mask_fops, + amdgpu_debugfs_compute_sched_mask_get, + amdgpu_debugfs_compute_sched_mask_set, "%llx\n"); +#endif #endif From 4b6fc33611e64d74b90ee4a3e20bfeb1a089d449 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 5 Nov 2024 12:03:51 +0800 Subject: [PATCH 1335/2653] drm/amdkcl: wrap code under DEFINE_DEBUGFS_ATTRIBUTE It's caused by following commit:9733f1d9355c3 "drm/amdgpu: add amdgpu_sdma_sched_mask debugfs" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index 8b8a04138711c..e3b9f48ad13f1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c @@ -434,9 +434,15 @@ static int amdgpu_debugfs_sdma_sched_mask_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_sdma_sched_mask_fops, amdgpu_debugfs_sdma_sched_mask_get, amdgpu_debugfs_sdma_sched_mask_set, "%llx\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_sdma_sched_mask_fops, + amdgpu_debugfs_sdma_sched_mask_get, + amdgpu_debugfs_sdma_sched_mask_set, "%llx\n"); +#endif #endif From 88fc35dd873ff9dffca7e38e188116e8ef4ef5b6 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 5 Nov 2024 15:19:59 +0800 Subject: [PATCH 1336/2653] drm/amdkcl: test whether str_read_write() is is available It's caused by following commit: 8a65a9cb5c "drm/amdgpu: use string choice helpers" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/str_read_write.m4 | 18 ++++++++++++++++++ include/kcl/kcl_string_helpers.h | 8 ++++++++ 4 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/str_read_write.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d84697b3220a6..9b99aa1cbfc05 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1032,6 +1032,9 @@ /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ +/* str_read_write() is defined */ +#define HAVE_STR_READ_WRITE 1 + /* str_yes_no() is defined */ #define HAVE_STR_YES_NO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f3b91beec76b9..602bfc6ab8137 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -184,6 +184,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_DEV_LTR_PATH AC_AMDGPU_DMA_FENCE_IS_CONTAINER AC_AMDGPU_STR_YES_NO + AC_AMDGPU_STR_READ_WRITE AC_AMDGPU_TOTALRAM_PAGES AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG diff --git a/drivers/gpu/drm/amd/dkms/m4/str_read_write.m4 b/drivers/gpu/drm/amd/dkms/m4/str_read_write.m4 new file mode 100644 index 0000000000000..df1463125da0d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/str_read_write.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 1f5d7ea73c4b630dbb2c90818cb9fc0be54d2fe3 +dnl # lib/string_helpers: Add str_read_write() helper +dnl # v6.0-rc1-122-g1f5d7ea73c4b +dnl # +AC_DEFUN([AC_AMDGPU_STR_READ_WRITE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + const char *str; + str = str_read_write(true); + ], [ + AC_DEFINE(HAVE_STR_READ_WRITE, 1, + [str_read_write() is defined]) + ]) + ]) +]) \ No newline at end of file diff --git a/include/kcl/kcl_string_helpers.h b/include/kcl/kcl_string_helpers.h index e02c0059b3ade..7d65d60fc2200 100644 --- a/include/kcl/kcl_string_helpers.h +++ b/include/kcl/kcl_string_helpers.h @@ -27,4 +27,12 @@ static inline const char *str_enabled_disabled(bool v) } #endif /* HAVE_STR_YES_NO */ + +#ifndef HAVE_STR_READ_WRITE +static inline const char *str_read_write(bool v) +{ + return v ? "read" : "write"; +} +#endif + #endif From 6b1f4427d70329c240b1a84129d674ee5210c039 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 7 Nov 2024 14:36:23 +0800 Subject: [PATCH 1337/2653] drm/amdkcl: move reservation_ww_class check to compile-time Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_reservation.c | 40 -------------------- drivers/gpu/drm/amd/amdkcl/main.c | 2 - drivers/gpu/drm/amd/dkms/Makefile | 4 ++ drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 10 +++++ 5 files changed, 15 insertions(+), 43 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_reservation.c diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index fd7c388cef2bf..a3fad367ae6aa 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -7,7 +7,7 @@ amdkcl-y += dma-buf/dma-resv.o kcl_dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_seq_file.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ - kcl_fence.o kcl_reservation.o kcl_drm_cache.o \ + kcl_fence.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_drm_edid.o\ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c deleted file mode 100644 index e1b018386c601..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2012-2014 Canonical Ltd (Maarten Lankhorst) - * - * Based on bo.c which bears the following copyright notice, - * but is dual licensed: - * - * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ -/* - * Authors: Thomas Hellstrom - */ -#include - -void amdkcl_reservation_init(void) -{ - amdkcl_fp_setup("reservation_ww_class", NULL); -} \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 7ede3a4fa2a6f..60f3a5987465a 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -5,7 +5,6 @@ extern void amdkcl_symbol_init(void); extern void amdkcl_dev_cgroup_init(void); extern void amdkcl_fence_init(void); -extern void amdkcl_reservation_init(void); extern void amdkcl_io_init(void); extern void amdkcl_mm_init(void); extern void amdkcl_suspend_init(void); @@ -19,7 +18,6 @@ int __init amdkcl_init(void) amdkcl_symbol_init(); amdkcl_dev_cgroup_init(); amdkcl_fence_init(); - amdkcl_reservation_init(); amdkcl_io_init(); amdkcl_mm_init(); amdkcl_suspend_init(); diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 0e41d5633a6f9..6153df061bcd8 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -52,6 +52,10 @@ ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) $(error dma_resv->seq is missing. exit...) endif +ifeq ($(call _is_kcl_macro_defined,HAVE_RESERVATION_WW_CLASS_BUG),y) +$(error reservation_ww_class is missing. exit...) +endif + DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index baeb0ee766979..8f83620935f38 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -56,6 +56,16 @@ AC_DEFUN([AC_AMDGPU_DMA_RESV_FENCES], [ ]) ]) +AC_DEFUN([AC_AMDGPU_DMA_RESV_RESERVATION_WW_CLASS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([reservation_ww_class],[drivers/dma-buf/dma-resv.c], + [],[ + AC_DEFINE(HAVE_RESERVATION_WW_CLASS_BUG, 1, [Reporting reservation_ww_class missing]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DMA_RESV], [ AC_AMDGPU_DMA_RESV_FENCES + AC_AMDGPU_DMA_RESV_RESERVATION_WW_CLASS ]) From 9b79085289da3ba2ad2efbd9938214ef3cb44b2e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 7 Nov 2024 14:40:44 +0800 Subject: [PATCH 1338/2653] drm/amdkcl: use kprobe for address resolution of unexported functions Replaces the usage of kallsyms_lookup_name with kprobe to obtain the addresses of kernel functions that are not exported. Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_common.c | 41 ++++++++++++------------- drivers/gpu/drm/amd/amdkcl/main.c | 2 -- 2 files changed, 20 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_common.c b/drivers/gpu/drm/amd/amdkcl/kcl_common.c index 5867b4d1a6c38..3d11e965887ea 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_common.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_common.c @@ -5,7 +5,26 @@ #include #include -unsigned long (*_kcl_kallsyms_lookup_name)(const char *name); +static unsigned long _kcl_kallsyms_lookup_name(const char *name) +{ + unsigned long addr = 0; +#ifndef HAVE_KALLSYMS_LOOKUP_NAME + struct kprobe kp; + int r; + + memset(&kp, 0, sizeof(kp)); + kp.symbol_name = name; + r = register_kprobe(&kp); + if (!r) { + addr = (unsigned long)kp.addr; + unregister_kprobe(&kp); + } +#else + addr = kallsyms_lookup_name(name); +#endif + + return addr; +} void *amdkcl_fp_setup(const char *symbol, void *dummy) { @@ -27,23 +46,3 @@ void *amdkcl_fp_setup(const char *symbol, void *dummy) return fp; } -void amdkcl_symbol_init(void) -{ -#ifndef HAVE_KALLSYMS_LOOKUP_NAME - struct kprobe kp; - int r; - - memset(&kp, 0, sizeof(kp)); - kp.symbol_name = "kallsyms_lookup_name"; - r = register_kprobe(&kp); - if (!r) { - _kcl_kallsyms_lookup_name = (void *)kp.addr; - unregister_kprobe(&kp); - } else { - pr_err("fail to get kallsyms_lookup_name, abort...\n"); - BUG(); - } -#else - _kcl_kallsyms_lookup_name = kallsyms_lookup_name; -#endif -} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 60f3a5987465a..8b80eceddcad5 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -2,7 +2,6 @@ #include #include -extern void amdkcl_symbol_init(void); extern void amdkcl_dev_cgroup_init(void); extern void amdkcl_fence_init(void); extern void amdkcl_io_init(void); @@ -15,7 +14,6 @@ extern void amdkcl_prime_init(void); int __init amdkcl_init(void) { - amdkcl_symbol_init(); amdkcl_dev_cgroup_init(); amdkcl_fence_init(); amdkcl_io_init(); From 4da69a1c6fb6cd1a17d959dc65fb9b5f9449c8a8 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 5 Nov 2024 12:30:25 +0800 Subject: [PATCH 1339/2653] drm/amdkcl: Implement new backlight_level_params structure on non-upstream code It's caused by following commit 6999dcd0bb61a2bb3378df8e45f0c8594018b15e "drm/amd/display: Implement new backlight_level_params structure" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6006ff1b13a68..1fc64a827caf9 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4983,7 +4983,11 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, / AMDGPU_MAX_BL_LEVEL + caps.min_input_signal * 0x101; - rc = dc_link_set_backlight_level(dm->backlight_link[bl_idx], brightness, 0); + struct set_backlight_level_params backlight_level_params = { 0 }; + + backlight_level_params.backlight_pwm_u16_16 = brightness; + backlight_level_params.transition_time_in_ms = 0; + rc = dc_link_set_backlight_level(dm->backlight_link[bl_idx], &backlight_level_params); if (!rc) DRM_ERROR("DM: Failed to update backlight on eDP[%d]\n", bl_idx); From 0da8b226bf0a3ccab527c01f28be89d5dbeafed1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 8 Nov 2024 14:43:26 +0800 Subject: [PATCH 1340/2653] drm/amdkcl: wrap code under macro AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT when AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT isn't defined, _kcl_fence_default_wait_cb isn't used. So avoid call the amdkcl_fp_setup. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index 6b962278954e6..e79e331222d00 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -50,9 +50,9 @@ struct default_wait_cb { struct task_struct *task; }; +#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT static void (*_kcl_fence_default_wait_cb)(struct dma_fence *fence, struct dma_fence_cb *cb); -#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT signed long _kcl_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) { @@ -238,7 +238,9 @@ EXPORT_SYMBOL(_kcl_fence_enable_signaling); */ void amdkcl_fence_init(void) { +#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT _kcl_fence_default_wait_cb = amdkcl_fp_setup("dma_fence_default_wait_cb", NULL); +#endif } #if !defined(HAVE_DMA_FENCE_DESCRIBE) From 7ab2bc0f7c1e9a9e4741739f15e1dd02134d39ab Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Sat, 9 Nov 2024 21:02:03 +0800 Subject: [PATCH 1341/2653] drm/amdkcl: clean macro HAVE_SCHED_SET_FIFO_LOW Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_sched.c | 30 ------------------- drivers/gpu/drm/amd/amdkcl/main.c | 2 -- drivers/gpu/drm/amd/dkms/config/config.h | 3 -- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 | 16 ---------- drivers/gpu/drm/scheduler/backport/backport.h | 1 - include/kcl/kcl_sched.h | 12 -------- 8 files changed, 1 insertion(+), 66 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_sched.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 delete mode 100644 include/kcl/kcl_sched.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index a3fad367ae6aa..5d1a6ec853128 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -6,7 +6,7 @@ amdkcl-y += dma-buf/dma-resv.o kcl_dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_seq_file.o \ - kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ + kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o \ kcl_fence.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_drm_edid.o\ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_sched.c b/drivers/gpu/drm/amd/amdkcl/kcl_sched.c deleted file mode 100644 index e57b29e7a7a73..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_sched.c +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * kernel/sched/core.c - * - * Core kernel scheduler code and related syscalls - * - * Copyright (C) 1991-2002 Linus Torvalds - */ - -#include - -/* Copied from kernel/sched/core.c and modified for KCL */ -#ifndef HAVE_SCHED_SET_FIFO_LOW -int (*_kcl_sched_setscheduler_nocheck)(struct task_struct *p, int policy, - const struct sched_param *param); -void sched_set_fifo_low(struct task_struct *p) -{ - struct sched_param sp = { .sched_priority = 1 }; - WARN_ON_ONCE(_kcl_sched_setscheduler_nocheck(p, SCHED_FIFO, &sp) != 0); -} -EXPORT_SYMBOL_GPL(sched_set_fifo_low); -#endif - -void amdkcl_sched_init(void) -{ -#ifndef HAVE_SCHED_SET_FIFO_LOW - _kcl_sched_setscheduler_nocheck = amdkcl_fp_setup("sched_setscheduler_nocheck", - NULL); -#endif -} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 8b80eceddcad5..e02c5db0eb328 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -7,7 +7,6 @@ extern void amdkcl_fence_init(void); extern void amdkcl_io_init(void); extern void amdkcl_mm_init(void); extern void amdkcl_suspend_init(void); -extern void amdkcl_sched_init(void); extern void amdkcl_numa_init(void); extern void amdkcl_workqueue_init(void); extern void amdkcl_prime_init(void); @@ -19,7 +18,6 @@ int __init amdkcl_init(void) amdkcl_io_init(); amdkcl_mm_init(); amdkcl_suspend_init(); - amdkcl_sched_init(); amdkcl_numa_init(); amdkcl_workqueue_init(); amdkcl_prime_init(); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9b99aa1cbfc05..4fdee1de1a7b6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -962,9 +962,6 @@ /* remove_conflicting_pci_framebuffers() wants p,p args */ /* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ -/* sched_set_fifo_low() is available */ -#define HAVE_SCHED_SET_FIFO_LOW 1 - /* seq_hex_dump() is available */ #define HAVE_SEQ_HEX_DUMP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 602bfc6ab8137..b93929176095d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -43,7 +43,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MMU_NOTIFIER_SYNCHRONIZE AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU AC_AMDGPU_MM_RELEASE_PAGES - AC_AMDGPU_SCHED_SET_FIFO_LOW AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_BUFFER_OBJECT AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION diff --git a/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 b/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 deleted file mode 100644 index 6a7fdf55ded70..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # v5.8-rc1-23-g7318d4cc14c8 -dnl # sched: Provide sched_set_fifo() -dnl # -AC_DEFUN([AC_AMDGPU_SCHED_SET_FIFO_LOW], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - sched_set_fifo_low(NULL); - ], [sched_set_fifo_low], [kernel/sched/core.c], [ - AC_DEFINE(HAVE_SCHED_SET_FIFO_LOW, 1, - [sched_set_fifo_low() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index ead9183b08d56..8f980b3fc2384 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/include/kcl/kcl_sched.h b/include/kcl/kcl_sched.h deleted file mode 100644 index 2ed8d6a01cd1f..0000000000000 --- a/include/kcl/kcl_sched.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _KCL_KCL_SCHED_H -#define _KCL_KCL_SCHED_H - -#include -#include - -#ifndef HAVE_SCHED_SET_FIFO_LOW -void sched_set_fifo_low(struct task_struct *p); -#endif - -#endif From bc7949a68d2425c69ccb050d697bd889d4df6b6d Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 4 Nov 2024 16:20:39 +0800 Subject: [PATCH 1342/2653] drm/amdkcl: fake the Macro definition drm_WARN_ON_ONCE It's caused by following commit a2529f67e20 "drm/amdgpu: Use drm_print_memory_stats helper from fdinfo" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- include/kcl/kcl_drm_print.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 0506b7a41f121..a4e435d18106e 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -54,6 +54,12 @@ dev_name((drm)->dev), ## arg) #endif +#ifndef drm_WARN_ON_ONCE +#define drm_WARN_ON_ONCE(drm, x) \ + drm_WARN_ONCE((drm), (x), "%s", \ + "drm_WARN_ON_ONCE(" __stringify(x) ")") +#endif + #ifndef drm_WARN #define drm_WARN(drm, condition, format, arg...) \ WARN(condition, "%s %s: " format, \ From 5bbd8469aab885c79cbd2d1426508bbadaf18a45 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 4 Nov 2024 13:41:58 +0800 Subject: [PATCH 1343/2653] drm/amdkcl: test whether drm_print_memory_stats() is available It's caused by following commit a2529f67e20 "drm/amdgpu: Use drm_print_memory_stats helper from fdinfo" Signed-off-by: chengjya Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 2 +- .../amd/backport/include/kcl/kcl_drm_file.h | 22 +++++++++++- drivers/gpu/drm/amd/backport/kcl_drm_file.c | 35 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/struct_drm_memoty_status.m4 | 23 ++++++++++++ include/kcl/kcl_drm_gem.h | 8 +++++ 7 files changed, 92 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 94639bcc8e4bc..658c1ef49e573 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -67,6 +67,7 @@ #include #include #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" @@ -112,7 +113,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h index a067b59578b6c..91ea254aa7434 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h @@ -1,8 +1,28 @@ #ifndef __AMDGPU_BACKPORT_KCL_DRM_DRV_H__ #define __AMDGPU_BACKPORT_KCL_DRM_DRV_H__ -#include +#include +#include +#include +#include #ifndef HAVE_DRM_SHOW_FDINFO void drm_show_fdinfo(struct seq_file *m, struct file *f); #endif + +#ifndef HAVE_DRM_PRINT_MEMORY_STATS +struct drm_memory_stats { + u64 shared; + u64 private; + u64 resident; + u64 purgeable; + u64 active; +}; + +void _kcl_drm_print_memory_stats(struct drm_printer *p, + const struct drm_memory_stats *stats, + enum drm_gem_object_status supported_status, + const char *region); +#define drm_print_memory_stats _kcl_drm_print_memory_stats; +#endif + #endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_file.c b/drivers/gpu/drm/amd/backport/kcl_drm_file.c index 5bc74f05d555e..a6d0cea48cecf 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_file.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_file.c @@ -67,4 +67,39 @@ void drm_show_fdinfo(struct seq_file *m, struct file *f) amdgpu_show_fdinfo(&p, file); } + +#ifndef HAVE_DRM_PRINT_MEMORY_STATS +static void print_size(struct drm_printer *p, const char *stat, + const char *region, u64 sz) +{ + const char *units[] = {"", " KiB", " MiB"}; + unsigned u; + + for (u = 0; u < ARRAY_SIZE(units) - 1; u++) { + if (sz == 0 || !IS_ALIGNED(sz, SZ_1K)) + break; + sz = div_u64(sz, SZ_1K); + } + + drm_printf(p, "drm-%s-%s:\t%llu%s\n", stat, region, sz, units[u]); +} + +void _kcl_drm_print_memory_stats(struct drm_printer *p, + const struct drm_memory_stats *stats, + enum drm_gem_object_status supported_status, + const char *region) +{ + print_size(p, "total", region, stats->private + stats->shared); + print_size(p, "shared", region, stats->shared); + print_size(p, "active", region, stats->active); + + if (supported_status & DRM_GEM_OBJECT_RESIDENT) + print_size(p, "resident", region, stats->resident); + + if (supported_status & DRM_GEM_OBJECT_PURGEABLE) + print_size(p, "purgeable", region, stats->purgeable); +} +EXPORT_SYMBOL(_kcl_drm_print_memory_stats); +#endif + #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4fdee1de1a7b6..c227c24fb56b0 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -617,6 +617,9 @@ /* drm_print_bits() has 4 args */ #define HAVE_DRM_PRINT_BITS_4ARGS 1 +/* drm_print_memory_stats() is available */ +#define HAVE_DRM_PRINT_MEMORY_STATS 1 + /* drm_show_fdinfo() is available */ #define HAVE_DRM_SHOW_FDINFO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b93929176095d..da411ef3e524f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -252,6 +252,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_CEC_ATTACH AC_AMDGPU_STRUCT_FILE_OPERATION AC_AMDGPU_FOLLOW_PFNMAP_START + AC_AMDGPU_DRM_FILE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 new file mode 100644 index 0000000000000..3e25ff65320cf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # commit v6.4-rc1-193-g686b21b5f6ca +dnl # drm: Add fdinfo memory stats +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRINT_MEMORY_STATS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ],[ + enum drm_gem_object_status res = 0; + res |= DRM_GEM_OBJECT_RESIDENT; + drm_print_memory_stats(NULL, NULL, res, NULL); + ],[drm_print_memory_stats], [drivers/gpu/drm/drm_file.c], [ + AC_DEFINE(HAVE_DRM_PRINT_MEMORY_STATS, 1, + [drm_print_memory_stats() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_FILE], [ + AC_AMDGPU_DRM_PRINT_MEMORY_STATS +]) diff --git a/include/kcl/kcl_drm_gem.h b/include/kcl/kcl_drm_gem.h index 73518a8a22f8b..cea563821fa86 100644 --- a/include/kcl/kcl_drm_gem.h +++ b/include/kcl/kcl_drm_gem.h @@ -35,6 +35,14 @@ #define __KCL_KCL_DRM_GEM_H__ #include + +#ifndef HAVE_DRM_PRINT_MEMORY_STATS +enum drm_gem_object_status { + DRM_GEM_OBJECT_RESIDENT = BIT(0), + DRM_GEM_OBJECT_PURGEABLE = BIT(1), +}; +#endif + #if defined(HAVE_DRM_GEM_OBJECT_PUT) #if defined(HAVE_DRM_GEM_OBJECT_PUT_SYMBOL) static inline void From b0feebfcb2fd5b43984440ff863872c65d3e8b7d Mon Sep 17 00:00:00 2001 From: chengjya Date: Wed, 6 Nov 2024 17:35:23 +0800 Subject: [PATCH 1344/2653] drm/amdkcl: test wether drm_dp_mst_topology_queue_probe() is available It's caused by following commit 7f6d4ea8399ad "drm/amd/display: Don't write DP_MSTM_CTRL after LT" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../drm/amd/amdkcl/kcl_drm_dp_mst_topology.c | 71 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../m4/drm_dp_mst_topology_queue_probe.m4 | 16 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../backport/kcl_drm_dp_mst_helper_backport.h | 5 ++ 6 files changed, 97 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_queue_probe.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 5d1a6ec853128..76f902e5c0ab2 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -15,7 +15,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o \ - kcl_drm_vblank.o + kcl_drm_vblank.o kcl_drm_dp_mst_topology.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c new file mode 100644 index 0000000000000..d6b4e9d0f77be --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c @@ -0,0 +1,71 @@ +/* + * Copyright © 2009 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#include +#include + +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE +static void _kcl_drm_dp_mst_queue_probe_work(struct drm_dp_mst_topology_mgr *mgr) +{ + queue_work(system_long_wq, &mgr->work); +} + +static void +_kcl_drm_dp_mst_topology_mgr_invalidate_mstb(struct drm_dp_mst_branch *mstb) +{ + struct drm_dp_mst_port *port; + + /* The link address will need to be re-sent on resume */ + mstb->link_address_sent = false; + + list_for_each_entry(port, &mstb->ports, next) + if (port->mstb) + _kcl_drm_dp_mst_topology_mgr_invalidate_mstb(port->mstb); +} + +/** + * drm_dp_mst_topology_queue_probe - Queue a topology probe + * @mgr: manager to probe + * + * Queue a work to probe the MST topology. Driver's should call this only to + * sync the topology's HW->SW state after the MST link's parameters have + * changed in a way the state could've become out-of-sync. This is the case + * for instance when the link rate between the source and first downstream + * branch device has switched between UHBR and non-UHBR rates. Except of those + * cases - for instance when a sink gets plugged/unplugged to a port - the SW + * state will get updated automatically via MST UP message notifications. + */ +void drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr) +{ + mutex_lock(&mgr->lock); + + if (drm_WARN_ON(mgr->dev, !mgr->mst_state || !mgr->mst_primary)) + goto out_unlock; + + _kcl_drm_dp_mst_topology_mgr_invalidate_mstb(mgr->mst_primary); + _kcl_drm_dp_mst_queue_probe_work(mgr); + +out_unlock: + mutex_unlock(&mgr->lock); +} +EXPORT_SYMBOL(_kcl_drm_dp_mst_topology_queue_probe); +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c227c24fb56b0..54fab733dad6a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -419,6 +419,9 @@ /* drm_dp_mst_topology_mgr_resume() wants 2 args */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS 1 +/* drm_dp_mst_topology_queue_probe() is available */ +#define HAVE_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE 1 + /* struct drm_dp_mst_topology_state has member payloads */ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_queue_probe.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_queue_probe.m4 new file mode 100644 index 0000000000000..1aace85d3c0f1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_queue_probe.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.10-3523-gb1c1c23eae66 +dnl # drm/dp_mst: Add a helper to queue a topology probe +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_mst_topology_queue_probe(NULL); + ], [drm_dp_mst_topology_queue_probe], [drivers/gpu/drm/display/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE, 1, + [drm_dp_mst_topology_queue_probe() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index da411ef3e524f..e8c8fb9b0539d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -253,6 +253,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_FILE_OPERATION AC_AMDGPU_FOLLOW_PFNMAP_START AC_AMDGPU_DRM_FILE + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index a84cd2ac22cc2..a6e237c081029 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -117,4 +117,9 @@ _kcl_drm_dp_add_payload_part2(struct drm_dp_mst_topology_mgr *mgr, #define drm_dp_add_payload_part2 _kcl_drm_dp_add_payload_part2 #endif +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE +void _kcl_drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr); +#define drm_dp_mst_topology_queue_probe _kcl_drm_dp_mst_topology_queue_probe +#endif + #endif From e9cf2259979a70f6008dda13f9e1bc1c6cbcde7a Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 8 Nov 2024 16:36:24 +0800 Subject: [PATCH 1345/2653] drm/amdkcl: wrap code under HAVE_DRM_GEM_OBJECT_RESV It's caused by following commit:fefc81edfd0ca40ef283 "drm/amdgpu: fix check in gmc_v9_0_get_vm_pte()" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- drivers/gpu/drm/ttm/ttm_bo.c | 2 +- drivers/gpu/drm/ttm/ttm_resource.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 860c23f8fde0b..75e0424131106 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -133,7 +133,7 @@ amdgpu_gem_update_bo_mapping(struct drm_file *filp, switch (operation) { case AMDGPU_VA_OP_MAP: case AMDGPU_VA_OP_REPLACE: - if (bo && (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)) + if (bo && (amdkcl_ttm_resvp(&bo->tbo) == amdkcl_ttm_resvp(&vm->root.bo->tbo))) last_update = vm->last_update; else last_update = bo_va->last_pt_update; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e12b833fa8989..0b347dd706498 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1117,7 +1117,7 @@ static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, bool snoop = false; bool is_local; - dma_resv_assert_held(bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&bo->tbo)); switch (gc_ip_version) { case IP_VERSION(9, 4, 1): diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index cc80fd302a192..b7d5bcb17b85f 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -1270,7 +1270,7 @@ int ttm_bo_populate(struct ttm_buffer_object *bo, bool swapped; int ret; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (!tt) return 0; diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c index af19a71571932..d617b3fb45069 100644 --- a/drivers/gpu/drm/ttm/ttm_resource.c +++ b/drivers/gpu/drm/ttm/ttm_resource.c @@ -267,7 +267,7 @@ static bool ttm_resource_is_swapped(struct ttm_resource *res, struct ttm_buffer_ if (bo->resource != res || !bo->ttm) return false; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); return ttm_tt_is_swapped(bo->ttm); } From d743a9a5b81f65dfa2221eb93a4f1f2ed2e876bd Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 13 Nov 2024 19:57:31 +0800 Subject: [PATCH 1346/2653] drm/amdkcl: define macro FOP_UNSIGNED_OFFSET It's caused by v6.11-rc4-29-g641bb4394f40 fs: move FMODE_UNSIGNED_OFFSET to fop_flags Signed-off-by: Asher Song --- include/kcl/kcl_fs.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_fs.h b/include/kcl/kcl_fs.h index 633a6edfd8f17..db6b6ad389abf 100644 --- a/include/kcl/kcl_fs.h +++ b/include/kcl/kcl_fs.h @@ -25,4 +25,10 @@ ssize_t _kcl_kernel_write(struct file *file, const void *buf, size_t count, loff_t *pos); #endif +#ifdef HAVE_FILE_OPERATION_FOP_FLAGS +#ifndef FOP_UNSIGNED_OFFSET +#define FOP_UNSIGNED_OFFSET ((__force fop_flags_t)(1 << 5)) +#endif +#endif + #endif From ed1f561cd26cec7a6fdb26a6220656a0e365e027 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 18 Nov 2024 14:45:44 +0800 Subject: [PATCH 1347/2653] drm/amdkcl: test whether drm_client_setup exists It's caused by v6.11-rc7-1514-gd07fdf922592 drm: Add client-agnostic setup helper v6.12-rc6-1222-gb86711c6d6e2 drm/client: Move public client header to clients/ subdirectory Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 15 ++++++++++- drivers/gpu/drm/amd/dkms/m4/drm-client.m4 | 25 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 12 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../kcl/header/drm/clients/drm_client_setup.h | 11 ++++++++ 5 files changed, 63 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-client.m4 create mode 100644 include/kcl/header/drm/clients/drm_client_setup.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 887091730dfe0..92a722370282c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2482,11 +2482,20 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, /* select 8 bpp console on low vram cards */ if (adev->gmc.real_vram_size <= (32*1024*1024)) +#if HAVE_DRM_CLIENT_SETUP format = drm_format_info(DRM_FORMAT_C8); +#else + drm_fbdev_ttm_setup(adev_to_drm(adev), 8); +#endif else +#if HAVE_DRM_CLIENT_SETUP format = NULL; - +#else + drm_fbdev_ttm_setup(adev_to_drm(adev), 32); +#endif +#if HAVE_DRM_CLIENT_SETUP drm_client_setup(adev_to_drm(adev), format); +#endif } ret = amdgpu_debugfs_init(adev); @@ -3149,7 +3158,9 @@ static struct drm_driver amdgpu_kms_driver = { .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), .dumb_create = amdgpu_mode_dumb_create, .dumb_map_offset = amdgpu_mode_dumb_mmap, +#ifdef DRM_FBDEV_TTM_DRIVER_OPS DRM_FBDEV_TTM_DRIVER_OPS, +#endif .fops = &amdgpu_driver_kms_fops, .release = &amdgpu_driver_release_kms, #ifdef HAVE_DRM_DRIVER_SHOW_FDINFO @@ -3207,7 +3218,9 @@ const struct drm_driver amdgpu_partition_driver = { .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), .dumb_create = amdgpu_mode_dumb_create, .dumb_map_offset = amdgpu_mode_dumb_mmap, +#ifdef DRM_FBDEV_TTM_DRIVER_OPS DRM_FBDEV_TTM_DRIVER_OPS, +#endif .fops = &amdgpu_driver_kms_fops, .release = &amdgpu_driver_release_kms, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 new file mode 100644 index 0000000000000..689086c18718e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 @@ -0,0 +1,25 @@ +dnl # +dnl # commit v6.11-rc7-1514-gd07fdf922592 +dnl # drm: Add client-agnostic setup helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CLIENT_SETUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRM_CLIENT_SETUP_H + #include + #endif + #ifdef HAVE_DRM_CLIENTS_DRM_CLIENT_SETUP_H + #include + #endif + ], [ + drm_client_setup(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_CLIENT_SETUP, 1, + [drm_client_setup() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_CLIENT], [ + AC_AMDGPU_DRM_CLIENT_SETUP +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index a8bcd262b8440..626d31bb54e40 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -122,4 +122,16 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # move asm/unaligned.h to linux/unaligned.h dnl # AC_KERNEL_CHECK_HEADERS([linux/unaligned.h]) + + dnl # + dnl # v6.11-rc7-1514-gd07fdf922592 + dnl # drm: Add client-agnostic setup helper + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_client_setup.h]) + + dnl # + dnl # v6.12-rc6-1222-gb86711c6d6e2 + dnl # drm/client: Move public client header to clients/ subdirectory + dnl # + AC_KERNEL_CHECK_HEADERS([drm/clients/drm_client_setup.h]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e8c8fb9b0539d..9b998deb7689a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -254,6 +254,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_FOLLOW_PFNMAP_START AC_AMDGPU_DRM_FILE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE + AC_AMDGPU_DRM_CLIENT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/header/drm/clients/drm_client_setup.h b/include/kcl/header/drm/clients/drm_client_setup.h new file mode 100644 index 0000000000000..58e21f2498f49 --- /dev/null +++ b/include/kcl/header/drm/clients/drm_client_setup.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_DRM_CLIENT_SETUP_H +#define _KCL_HEADER_DRM_DRM_CLIENT_SETUP_H + +#if defined(HAVE_DRM_CLIENTS_DRM_CLIENT_SETUP_H) +#include_next +#elif defined(HAVE_DRM_DRM_CLIENT_SETUP_H) +#include +#endif + +#endif From a2c6351f43b313dd36d095043743c0e760c04e83 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 11 Nov 2024 16:04:24 +0800 Subject: [PATCH 1348/2653] drm/amdkcl: test whether drm_syncobj_add_point() is available It's caused by following commit fa4672c7ce098741634e "drm/amdgpu: update userqueue BOs and PDs" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_syncobj.c | 73 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../drm/amd/dkms/m4/drm_syncobj_add_point.m4 | 16 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- include/kcl/kcl_drm_syncobj.h | 19 +++++ 7 files changed, 115 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_syncobj.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_syncobj_add_point.m4 create mode 100644 include/kcl/kcl_drm_syncobj.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 76f902e5c0ab2..8f1084844f1c1 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -15,7 +15,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o \ - kcl_drm_vblank.o kcl_drm_dp_mst_topology.o + kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_syncobj.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_syncobj.c new file mode 100644 index 0000000000000..20393f00b0a47 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_syncobj.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation. + * + * Authors: + * Ramalingam C + */ +#include +#include +#include + +#ifndef HAVE_DRM_SYNCOBJ_ADD_POINT +struct syncobj_wait_entry { + struct list_head node; + struct task_struct *task; + struct dma_fence *fence; + struct dma_fence_cb fence_cb; + u64 point; +}; + +static void _kcl_syncobj_wait_syncobj_func(struct drm_syncobj *syncobj, + struct syncobj_wait_entry *wait) +{ + struct dma_fence *fence; + + /* This happens inside the syncobj lock */ + fence = rcu_dereference_protected(syncobj->fence, + lockdep_is_held(&syncobj->lock)); + dma_fence_get(fence); + if (!fence || dma_fence_chain_find_seqno(&fence, wait->point)) { + dma_fence_put(fence); + return; + } else if (!fence) { + wait->fence = dma_fence_get_stub(); + } else { + wait->fence = fence; + } + + wake_up_process(wait->task); + list_del_init(&wait->node); +} + +void _kcl_drm_syncobj_add_point(struct drm_syncobj *syncobj, + struct dma_fence_chain *chain, + struct dma_fence *fence, + uint64_t point) +{ + struct syncobj_wait_entry *wait_cur, *wait_tmp; + struct dma_fence *prev; + + dma_fence_get(fence); + + spin_lock(&syncobj->lock); + + prev = drm_syncobj_fence_get(syncobj); + /* You are adding an unorder point to timeline, which could cause payload returned from query_ioctl is 0! */ + if (prev && prev->seqno >= point) + DRM_DEBUG("You are adding an unorder point to timeline!\n"); + dma_fence_chain_init(chain, prev, fence, point); + rcu_assign_pointer(syncobj->fence, &chain->base); + + list_for_each_entry_safe(wait_cur, wait_tmp, &syncobj->cb_list, node) + _kcl_syncobj_wait_syncobj_func(syncobj, wait_cur); + + spin_unlock(&syncobj->lock); + + /* Walk the chain once to trigger garbage collection */ + dma_fence_chain_for_each(fence, prev); + dma_fence_put(prev); +} +EXPORT_SYMBOL(_kcl_drm_syncobj_add_point); +#endif + diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 658c1ef49e573..c05bcf86362fb 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -132,4 +132,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 54fab733dad6a..5dcc06142e171 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -632,6 +632,9 @@ /* Has function drm_suballoc_manager_init() */ #define HAVE_DRM_SUBALLOC_MANAGER_INIT 1 +/* drm_syncobj_add_point() is available */ +#define HAVE_DRM_SYNCOBJ_ADD_POINT 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_syncobj_add_point.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_syncobj_add_point.m4 new file mode 100644 index 0000000000000..af363349cc643 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_syncobj_add_point.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.0-1332-g44f8a1396e83 +dnl # drm/syncobj: add new drm_syncobj_add_point interface v4 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_SYNCOBJ_ADD_POINT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_syncobj_add_point(NULL, NULL, NULL, 0); + ],[drm_syncobj_add_point], [drivers/gpu/drm/drm_syncobj.c], [ + AC_DEFINE(HAVE_DRM_SYNCOBJ_ADD_POINT, 1, + [drm_syncobj_add_point() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9b998deb7689a..229a4c9423da3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -255,7 +255,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FILE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE AC_AMDGPU_DRM_CLIENT - + AC_AMDGPU_DRM_SYNCOBJ_ADD_POINT + AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" diff --git a/include/kcl/kcl_drm_syncobj.h b/include/kcl/kcl_drm_syncobj.h new file mode 100644 index 0000000000000..9323b1a4f5387 --- /dev/null +++ b/include/kcl/kcl_drm_syncobj.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ + +#ifndef AMDKCL_DRM_SYNCOBJ_H +#define AMDKCL_DRM_SYNCOBJ_H + +#include +#include +#include + +#ifndef HAVE_DRM_SYNCOBJ_ADD_POINT +void _kcl_drm_syncobj_add_point(struct drm_syncobj *syncobj, + struct dma_fence_chain *chain, + struct dma_fence *fence, + uint64_t point); + +#define drm_syncobj_add_point _kcl_drm_syncobj_add_point +#endif + +#endif From 6ad6bb28e0dc10a73dfac30a2690ff82f3e54d92 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 11 Nov 2024 14:53:41 +0800 Subject: [PATCH 1349/2653] drm/amdkcl: fix the missing dam-fence-unwrap.h It's caused by following commit:d6c9f947 "drm/amdgpu: Add wait IOCTL timeline syncobj support" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/linux/dma-fence-unwrap.h | 9 +++++++++ 3 files changed, 17 insertions(+) create mode 100644 include/kcl/header/linux/dma-fence-unwrap.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5dcc06142e171..7ff3a0f01d69f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -812,6 +812,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_FENCE_CHAIN_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_FENCE_UNWRAP_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_MAP_OPS_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 4df530c27442c..e3f0b8cd28802 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -139,4 +139,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #include/linux/units.h: add helpers for kelvin to/from Celsius conversion dnl AC_KERNEL_CHECK_HEADERS([linux/units.h]) + + dnl #v5.17-rc6-1496-g64a8f92fd783 + dnl #dma-buf: add dma_fence_unwrap v2 + dnl + AC_KERNEL_CHECK_HEADERS([linux/dma-fence-unwrap.h]) ]) diff --git a/include/kcl/header/linux/dma-fence-unwrap.h b/include/kcl/header/linux/dma-fence-unwrap.h new file mode 100644 index 0000000000000..4564e22d18fb8 --- /dev/null +++ b/include/kcl/header/linux/dma-fence-unwrap.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__LINUX_DMA_FENCE_UNWRAP_H_H +#define _KCL_HEADER__LINUX_DMA_FENCE_UNWRAP_H_H + +#ifdef HAVE_LINUX_DMA_FENCE_UNWRAP_H +#include_next +#endif + +#endif \ No newline at end of file From 41abde4e22220a58f7ccc0b08920a936b512e9b5 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 25 Mar 2025 11:50:35 +0800 Subject: [PATCH 1350/2653] drm/amdkcl: fake drm_client_dev_{resume/suspend} It's caused by v6.12-rc2-587-gbf17766f1083 drm/client: Move suspend/resume into DRM client callbacks Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_drm_client_event.c | 16 ++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-client.m4 | 21 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ include/kcl/header/drm/drm_client_event.h | 9 ++++++++ include/kcl/kcl_drm_client_event.h | 12 +++++++++++ 7 files changed, 66 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_client_event.c create mode 100644 include/kcl/header/drm/drm_client_event.h create mode 100644 include/kcl/kcl_drm_client_event.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 8f1084844f1c1..41b8e669c70cd 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -15,7 +15,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o \ - kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o + kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_client_event.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_client_event.c new file mode 100644 index 0000000000000..f49f9e059e17b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_client_event.c @@ -0,0 +1,16 @@ +#include + +#ifndef HAVE_DRM_CLIENT_DEV_RESUME +void drm_client_dev_resume(struct drm_device *dev, bool holds_console_lock) +{ + drm_fb_helper_set_suspend_unlocked(dev->fb_helper, holds_console_lock); +} +EXPORT_SYMBOL(drm_client_dev_resume); + +void drm_client_dev_suspend(struct drm_device *dev, bool holds_console_lock) +{ + bool suspend = !holds_console_lock; + drm_fb_helper_set_suspend_unlocked(dev->fb_helper, suspend); +} +EXPORT_SYMBOL(drm_client_dev_suspend); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index c05bcf86362fb..14b7fc1827869 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -133,4 +133,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 index 689086c18718e..2c58adc325572 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 @@ -20,6 +20,27 @@ AC_DEFUN([AC_AMDGPU_DRM_CLIENT_SETUP], [ ]) ]) +dnl # +dnl # commit v6.12-rc2-587-gbf17766f1083 +dnl # drm/client: Move suspend/resume into DRM client callbacks +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CLIENT_DEV_RESUME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + drm_client_dev_resume(NULL, false); + ], [ + AC_DEFINE(HAVE_DRM_CLIENT_DEV_RESUME, 1, + [drm_client_dev_resume() is available]) + ]) + ]) +]) + + + AC_DEFUN([AC_AMDGPU_DRM_CLIENT], [ AC_AMDGPU_DRM_CLIENT_SETUP + AC_AMDGPU_DRM_CLIENT_DEV_RESUME ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 626d31bb54e40..ad0408625c199 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -134,4 +134,10 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/client: Move public client header to clients/ subdirectory dnl # AC_KERNEL_CHECK_HEADERS([drm/clients/drm_client_setup.h]) + + dnl # + dnl # v6.12-rc2-586-gdf7e8b522a60 + dnl # drm/client: Move client event handlers to drm_client_event.c + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_client_event.h]) ]) diff --git a/include/kcl/header/drm/drm_client_event.h b/include/kcl/header/drm/drm_client_event.h new file mode 100644 index 0000000000000..84269dac95e6a --- /dev/null +++ b/include/kcl/header/drm/drm_client_event.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_DRM_CLIENT_EVENT_H +#define _KCL_HEADER_DRM_DRM_CLIENT_EVENT_H + +#ifdef HAVE_DRM_DRM_CLIENT_EVENT_H +#include_next +#endif + +#endif diff --git a/include/kcl/kcl_drm_client_event.h b/include/kcl/kcl_drm_client_event.h new file mode 100644 index 0000000000000..52f3342a5e573 --- /dev/null +++ b/include/kcl/kcl_drm_client_event.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef KCL_KCL_DRM_CLIENT_EVENT_H +#define KCL_KCL_DRM_CLIENT_EVENT_H + +#include + +#ifndef HAVE_DRM_CLIENT_DEV_RESUME +void drm_client_dev_suspend(struct drm_device *dev, bool holds_console_lock); +void drm_client_dev_resume(struct drm_device *dev, bool holds_console_lock); +#endif + +#endif From 166e41721e38c48b89beece57084308c7b68d025 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Nov 2024 12:58:09 +0800 Subject: [PATCH 1351/2653] drm/amdkcl: fake aperture_remove_conflicting_pci_devices It's caused by 5.19-rc2-317-g7283f862bd99 drm: Implement DRM aperture helpers under video/ Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 2 +- drivers/gpu/drm/amd/backport/backport.h | 1 + ...ure-remove-conflicting-pci-framebuffers.m4 | 22 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 ++++ include/kcl/backport/kcl_linux_aperture.h | 25 +++++++++++++++++++ include/kcl/header/linux/aperture.h | 10 ++++++++ 7 files changed, 65 insertions(+), 2 deletions(-) create mode 100644 include/kcl/backport/kcl_linux_aperture.h create mode 100644 include/kcl/header/linux/aperture.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c index 91f2508079ff1..a5c85881e336b 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT -#ifndef HAVE_DRM_DRM_APERTURE_H +#if !defined(HAVE_DRM_DRM_APERTURE_H) && !defined(HAVE_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES) #include #include diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 14b7fc1827869..51dbf731d54aa 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -134,4 +134,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 index 50cfd872b53b3..0f644628eb68c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 @@ -16,3 +16,25 @@ AC_DEFUN([AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ ]) ]) ]) + +dnl # +dnl # v5.19-rc2-317-g7283f862bd99 +dnl # drm: Implement DRM aperture helpers under video/ +dnl # +AC_DEFUN([AC_AMDGPU_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + aperture_remove_conflicting_pci_devices(NULL, NULL); + ], [ + AC_DEFINE(HAVE_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES, 1, + [aperture_remove_conflicting_pci_device() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_APERTURE], [ + AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG + AC_AMDGPU_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 229a4c9423da3..e8391867adf60 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -161,7 +161,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG - AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG + AC_AMDGPU_DRM_APERTURE AC_AMDGPU_SYNCHRONIZE_SHRINKERS AC_AMDGPU_KREALLOC_ARRAY AC_AMDGPU_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index e3f0b8cd28802..661896d6ee4c2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -144,4 +144,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #dma-buf: add dma_fence_unwrap v2 dnl AC_KERNEL_CHECK_HEADERS([linux/dma-fence-unwrap.h]) + + dnl #5.19-rc2-317-g7283f862bd99 + dnl #drm: Implement DRM aperture helpers under video/ + dnl + AC_KERNEL_CHECK_HEADERS([linux/aperture.h]) ]) diff --git a/include/kcl/backport/kcl_linux_aperture.h b/include/kcl/backport/kcl_linux_aperture.h new file mode 100644 index 0000000000000..3aca24db4e3d2 --- /dev/null +++ b/include/kcl/backport/kcl_linux_aperture.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ + +#ifndef _KCL_BACKPORT_KCL_LINUX_APERTURE_H_ +#define _KCL_BACKPORT_KCL_LINUX_APERTURE_H_ + +#include + +struct pci_dev; + +#ifndef HAVE_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES +#include +static inline int _kcl_aperture_remove_conflicting_pci_devices(struct pci_dev *pdev, const char *name) +{ +#ifdef HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG + char *nonconst_name = (char *)name; + struct drm_driver *drm_driver = container_of(&nonconst_name, struct drm_driver, name); + return drm_aperture_remove_conflicting_pci_framebuffers(pdev, drm_driver); +#else + return drm_aperture_remove_conflicting_pci_framebuffers(pdev, name); +#endif +} +#define aperture_remove_conflicting_pci_devices _kcl_aperture_remove_conflicting_pci_devices +#endif + +#endif /* _KCL_BACKPORT_KCL_LINUX_APERTURE_H_ */ diff --git a/include/kcl/header/linux/aperture.h b/include/kcl/header/linux/aperture.h new file mode 100644 index 0000000000000..358ef946ab28e --- /dev/null +++ b/include/kcl/header/linux/aperture.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_APERTURE_H +#define _KCL_HEADER_LINUX_APERTURE_H + +#ifdef HAVE_LINUX_APERTURE_H +#include_next +#endif + +#endif + From 287577383c8ac92e8e6bac1f69477ef6fa3e1598 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Nov 2024 21:01:48 +0800 Subject: [PATCH 1352/2653] Bump AMDGPU version to 6.12.0 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 666a4766a10b2..808c3a42b1f99 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.5.0) +AC_INIT(amdgpu-dkms, 6.12.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From a3348889096b00e907f9b15cb9ea191a345e58fa Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Nov 2024 21:06:16 +0800 Subject: [PATCH 1353/2653] drm/amdkcl: update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 88 ++++++++++++++---------- 1 file changed, 52 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7ff3a0f01d69f..498186ee43d05 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -38,13 +38,16 @@ /* #undef HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 */ /* amd_iommu_pc_get_max_banks() declared */ -#define HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED 1 +/* #undef HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED */ /* amd_iommu_pc_get_max_banks() arg is unsigned int */ /* #undef HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_UINT */ /* amd_iommu_pc_supported() is available */ -#define HAVE_AMD_IOMMU_PC_SUPPORTED 1 +/* #undef HAVE_AMD_IOMMU_PC_SUPPORTED */ + +/* aperture_remove_conflicting_pci_device() is available */ +#define HAVE_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES 1 /* apple_gmux_detect() is available */ #define HAVE_APPLE_GMUX_DETECT 1 @@ -130,9 +133,6 @@ /* dma_fence_describe() is available */ #define HAVE_DMA_FENCE_DESCRIBE 1 -/* whether dma_fence_get_stub exits */ -#define HAVE_DMA_FENCE_GET_STUB 1 - /* dma_fence_is_container() is available */ #define HAVE_DMA_FENCE_IS_CONTAINER 1 @@ -180,7 +180,7 @@ /* drm_aperture_remove_conflicting_pci_framebuffers() second arg is drm_driver* */ -#define HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG 1 +/* #undef HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG */ /* drm_atomic_helper_calc_timestamping_constants() is available */ #define HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS 1 @@ -188,9 +188,19 @@ /* drm_atomic_plane_enabling() is available */ #define HAVE_DRM_ATOMIC_PLANE_ENABLING 1 + +/* drm_client_dev_resume() is available */ +#define HAVE_DRM_CLIENT_DEV_RESUME 1 + /* drm_client_register() is available */ #define HAVE_DRM_CLIENT_REGISTER 1 +/* drm_client_setup() is available */ +#define HAVE_DRM_CLIENT_SETUP 1 + +/* struct drm_color_ctm_3x4 is available */ +/* #undef HAVE_DRM_COLOR_CTM_3X4 */ + /* drm_connector_atomic_hdr_metadata_equal() is available */ #define HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL 1 @@ -217,15 +227,6 @@ /* drm_connector_init_with_ddc() is available */ #define HAVE_DRM_CONNECTOR_INIT_WITH_DDC 1 -/* connector property "max bpc" is available */ -#define HAVE_DRM_CONNECTOR_PROPERTY_MAX_BPC 1 - -/* drm_connector_put() is available */ -#define HAVE_DRM_CONNECTOR_PUT 1 - -/* connector reference counting is available */ -#define HAVE_DRM_CONNECTOR_REFERENCE_COUNTING_SUPPORTED 1 - /* drm_connector_set_panel_orientation_with_quirk() is available */ #define HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK 1 @@ -258,9 +259,6 @@ /* drm_debug_enabled() is available */ #define HAVE_DRM_DEBUG_ENABLED 1 -/* drm_device->filelist_mutex is available */ -#define HAVE_DRM_DEVICE_FILELIST_MUTEX 1 - /* drm_device->open_count is int */ /* #undef HAVE_DRM_DEVICE_OPEN_COUNT_INT */ @@ -295,9 +293,6 @@ /* display_info->edid_hdmi_rgb444_dc_modes is available */ #define HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES 1 -/* display_info->hdmi.scdc.scrambling are available */ -#define HAVE_DRM_DISPLAY_INFO_HDMI_SCDC_SCRAMBLING 1 - /* display_info->is_hdmi is available */ #define HAVE_DRM_DISPLAY_INFO_IS_HDMI 1 @@ -310,6 +305,9 @@ /* struct drm_display_info has monitor_range member */ #define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 +/* drm_dp_add_payload_part2 has three arguments */ +/* #undef HAVE_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS */ + /* drm_dp_atomic_find_time_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS 1 @@ -459,11 +457,17 @@ /* #undef HAVE_DRM_DRMP_H */ /* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_APERTURE_H 1 +/* #undef HAVE_DRM_DRM_APERTURE_H */ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRM_BACKPORT_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_CLIENT_EVENT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_CLIENT_SETUP_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_ELD_H 1 @@ -471,7 +475,10 @@ #define HAVE_DRM_DRM_EXEC_H 1 /* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_FBDEV_GENERIC_H 1 +/* #undef HAVE_DRM_DRM_FBDEV_GENERIC_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_FBDEV_TTM_H 1 /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_GEM_ATOMIC_HELPER_H 1 @@ -650,9 +657,15 @@ /* fault_flag_allow_retry_first() is available */ #define HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST 1 +/* file_operation->fop_flags is available */ +#define HAVE_FILE_OPERATION_FOP_FLAGS 1 + /* follow_pfn() is available */ /* #undef HAVE_FOLLOW_PFN */ +/* follow_pfnmap_start() is available */ +#define HAVE_FOLLOW_PFNMAP_START 1 + /* fsleep() is available */ #define HAVE_FSLEEP 1 @@ -719,9 +732,6 @@ /* io_mapping_map_local_wc() is available */ #define HAVE_IO_MAPPING_MAP_LOCAL_WC 1 -/* io_mapping_map_wc() has size argument */ -#define HAVE_IO_MAPPING_MAP_WC_HAS_SIZE_ARG 1 - /* io_mapping_unmap_local() is available */ #define HAVE_IO_MAPPING_UNMAP_LOCAL 1 @@ -774,11 +784,14 @@ /* #undef HAVE_KTIME_IS_UNION */ /* kvrealloc() is available */ -#define HAVE_KVREALLOC 1 +/* #undef HAVE_KVREALLOC */ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_ACPI_AMD_WBRF_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_APERTURE_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_APPLE_GMUX_H 1 @@ -848,6 +861,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_STDARG_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_UNALIGNED_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_UNITS_H 1 @@ -974,6 +990,9 @@ /* remove_conflicting_pci_framebuffers() wants p,p args */ /* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ +/* Reporting reservation_ww_class missing */ +/* #undef HAVE_RESERVATION_WW_CLASS_BUG */ + /* seq_hex_dump() is available */ #define HAVE_SEQ_HEX_DUMP 1 @@ -1016,12 +1035,6 @@ /* struct drm_crtc_state->async_flip is available */ #define HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP 1 -/* struct drm_crtc_state has flag for flip */ -#define HAVE_STRUCT_DRM_CRTC_STATE_FLIP_FLAG 1 - -/* struct drm_crtc_state->pageflip_flags is available */ -/* #undef HAVE_STRUCT_DRM_CRTC_STATE_PAGEFLIP_FLAGS */ - /* drm_gem_open_object is defined in struct drm_drv */ /* #undef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ @@ -1053,6 +1066,9 @@ /* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 +/* topology_num_cores_per_package is availablea */ +#define HAVE_TOPOLOGY_NUM_CORES_PER_PACKAGE 1 + /* totalram_pages() is available */ #define HAVE_TOTALRAM_PAGES 1 @@ -1062,7 +1078,7 @@ /* __poll_t is available */ #define HAVE_TYPE__POLL_T 1 -/* usleep_range_stat() is available */ +/* usleep_range_state() is available */ #define HAVE_USLEEP_RANGE_STATE 1 /* vga_client_register() don't pass a cookie */ @@ -1135,7 +1151,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 6.10.0" +#define PACKAGE_STRING "amdgpu-dkms 6.12.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1144,7 +1160,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "6.10.0" +#define PACKAGE_VERSION "6.12.0" #include "config-amd-chips.h" From 0861dbe78bc48e301dd3cf9a86833e8b09a2917a Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 30 Oct 2024 17:33:56 -0400 Subject: [PATCH 1354/2653] drm/amdkfd: fix hw stall issue When register RLC_SPM_PERFMON_CNTL/PERFMON_RING_MODE is set to 0x11,SPM HW fires warning interrupt when rptr reaches RLC_SPM_SEGMENT_THRESHOLD, and stalls when rptr reaches the end of ring buffer. But the HW bug causes that both stall and interrupt arise when rptr reaches RLC_SPM_SEGMENT_THRESHOLD, and this means unexpecetd data loss with early SPM HW stall arise when interrupt received. this fix uses polling mode instead to avoid expected SPM HW early stall. Signed-off-by: James Zhu Reviewed-by: Bing Ma Reviewed-by: Gang Ba --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 86 +++++++++++++++++++++++++- 5 files changed, 87 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 3a19ff380f3f2..e4b8970902201 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7866,7 +7866,7 @@ static void gfx_v10_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_RING_SIZE), size); gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, - SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_SEGMENT_THRESHOLD), 0xff); + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_SEGMENT_THRESHOLD), 0x1); gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index de5e273967848..e72d50d2ba1dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -5296,7 +5296,7 @@ static void gfx_v8_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, mmRLC_SPM_PERFMON_RING_SIZE, size); gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, - mmRLC_SPM_SEGMENT_THRESHOLD, 0xff); + mmRLC_SPM_SEGMENT_THRESHOLD, 0x1); gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, 0); } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 2d5c6089819f3..83f3ef150332a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4869,7 +4869,7 @@ static void gfx_v9_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, u64 gp gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_RING_SIZE), size); gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, - SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_SEGMENT_THRESHOLD), 0xff); + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_SEGMENT_THRESHOLD), 0x1); gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), 0); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 17df472bea593..c6057a41296b8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -348,6 +348,7 @@ struct kfd_node { /*spm process id */ unsigned int spm_pasid; + struct task_struct *spm_monitor_thread; /* Maximum process number mapped to HW scheduler */ unsigned int max_proc_per_quantum; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index d6a03240f36af..46d05c834ce76 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -48,11 +48,79 @@ struct kfd_spm_cntr { bool has_user_buf; bool is_user_buf_filled; bool is_spm_started; + u32 warned_ring_rptr; }; /* used to detect SPM overflow */ #define SPM_OVERFLOW_MAGIC 0xBEEFABCDDEADABCD +static int kfd_spm_monitor_thread(void *param) +{ + struct kfd_process_device *pdd = param; + struct kfd_node *node = pdd->dev; + + allow_signal(SIGKILL); + while (!kthread_should_stop() && + !signal_pending(node->spm_monitor_thread) && pdd->spm_cntr) { + struct kfd_spm_cntr *spm = pdd->spm_cntr; + bool need_schedule = false; + + usleep_range(1, 11); + + if (!mutex_trylock(&pdd->spm_cntr->spm_worker_mutex)) + continue; + + if (spm->is_spm_started) { + u32 warned_ring_rptr; + u32 ring_size; + u32 ring_rptr; + u32 ring_wptr; + + ring_size = spm->ring_size; + ring_rptr = spm->ring_rptr; + warned_ring_rptr = spm->warned_ring_rptr; + ring_wptr = READ_ONCE(spm->cpu_addr[0]); + + if (need_schedule || (ring_rptr != warned_ring_rptr && + (ring_size + ring_wptr - ring_rptr) % ring_size > + (ring_size >> 1))) { + spm->warned_ring_rptr = ring_rptr; + if (!need_schedule) { + dev_dbg(node->adev->dev, + "SPM soft interrupt rptr:0x%08x--wptr:0x%08x", + ring_rptr, ring_wptr); + need_schedule = true; + } + } + } + mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); + if (need_schedule) + schedule_work(&pdd->spm_work); + } + node->spm_monitor_thread = NULL; + return 0; +} + +static int kfd_spm_monitor_thread_start(struct kfd_process_device *pdd) +{ + struct kfd_node *node = pdd->dev; + char thread_name[16]; + int ret = 0; + + snprintf(thread_name, 16, "spm_%d", node->adev->ddev.render->index); + node->spm_monitor_thread = + kthread_run(kfd_spm_monitor_thread, pdd, thread_name); + + if (IS_ERR(node->spm_monitor_thread)) { + ret = PTR_ERR(node->spm_monitor_thread); + node->spm_monitor_thread = NULL; + dev_dbg(node->adev->dev, "Failed to create spm monitor thread %s with ret = %d.", + thread_name, ret); + } + + return ret; +} + static void kfd_spm_preset(struct kfd_process_device *pdd, u32 size) { uint64_t *overflow_ptr, *overflow_end_ptr; @@ -137,6 +205,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) if (spm->ring_rptr == ring_wptr) goto exit; + spm->warned_ring_rptr = spm->ring_rptr; if (ring_wptr > spm->ring_rptr) { size_to_copy = ring_wptr - spm->ring_rptr; ret = kfd_spm_data_copy(pdd, size_to_copy); @@ -258,6 +327,8 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device spin_lock_init(&pdd->spm_irq_lock); kfd_spm_preset(pdd, pdd->spm_overflow_reserved); + pdd->spm_cntr->warned_ring_rptr = ~0; + pdd->dev->spm_monitor_thread = NULL; goto out; @@ -283,6 +354,9 @@ int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) return -EINVAL; } + if (pdd->dev->spm_monitor_thread) + kthread_stop(pdd->dev->spm_monitor_thread); + spin_lock_irqsave(&pdd->spm_irq_lock, flags); pdd->spm_cntr->is_spm_started = false; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); @@ -413,7 +487,10 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev * Adjust rptr accordingly */ spm->ring_rptr = 0; + spm->warned_ring_rptr = ~0; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + if (!pdd->dev->spm_monitor_thread) + kfd_spm_monitor_thread_start(pdd); } else { /* If SPM was already started, there may already * be data in the ring-buffer that needs to be read. @@ -428,7 +505,10 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev * Adjust rptr accordingly */ spm->ring_rptr = 0; + spm->warned_ring_rptr = ~0; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + if (pdd->dev->spm_monitor_thread) + kthread_stop(pdd->dev->spm_monitor_thread); } mutex_unlock(&pdd->spm_mutex); @@ -480,7 +560,7 @@ void kgd2kfd_spm_interrupt(struct kfd_dev *kfd) unsigned long flags; if (!p) { - pr_debug("kfd_spm_interrupt p = %p\n", p); + dev_dbg(dev->adev->dev, "kfd_spm_interrupt p = %p\n", p); return; /* Presumably process exited. */ } @@ -489,11 +569,11 @@ void kgd2kfd_spm_interrupt(struct kfd_dev *kfd) return; spin_lock_irqsave(&pdd->spm_irq_lock, flags); - if (pdd->spm_cntr && pdd->spm_cntr->is_spm_started) - schedule_work(&pdd->spm_work); + pdd->spm_cntr->has_data_loss = true; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + dev_dbg(dev->adev->dev, "SPM ring buffer stall."); kfd_unref_process(p); } From b31c8657677c5ff725164759adaf2988c48f99f4 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 30 Oct 2024 17:37:04 -0400 Subject: [PATCH 1355/2653] drm/amdkfd: adding spm ring buffer overflow message to provide user space more information. Signed-off-by: James Zhu Reviewed-by: Bing Ma Reviewed-by: Gang Ba --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 46d05c834ce76..cdf38ad27100e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -220,6 +220,9 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) if (*overflow_ptr == SPM_OVERFLOW_MAGIC) break; } + if (overflow_size) + dev_dbg(pdd->dev->adev->dev, + "SPM ring buffer overflow size 0x%x", overflow_size); /* move overflow counters into ring buffer to avoid data loss */ memcpy(ring_start, ring_end, overflow_size); From 8ff5a156ac71416fd8543a6017cd4f7a1d254b23 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 9 Oct 2024 16:48:43 -0400 Subject: [PATCH 1356/2653] drm/amdkfd: add spm buffer header to send data back to user. Signed-off-by: James Zhu Reviewed-by: Bing Ma Reviewed-by: Gang Ba --- include/uapi/linux/kfd_ioctl.h | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index d0fbe5423e35d..2e4806afe8d14 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -615,9 +615,8 @@ enum kfd_ioctl_spm_op { * @buf_size[in]: size of the destination buffer * @timeout[in/out]: [in]: timeout in milliseconds, [out]: amount of time left * `in the timeout window - * @bytes_copied[out]: amount of data that was copied to the previous dest_buf - * @has_data_loss: boolean indicating whether data was lost - * (e.g. due to a ring-buffer overflow) + * @bytes_copied[out]: total amount of data that was copied to the previous dest_buf + * @has_data_loss: total count for sub-block which has data loss * * This ioctl performs different functions depending on the @op parameter. * @@ -667,6 +666,21 @@ struct kfd_ioctl_spm_args { __u32 has_data_loss; }; +/** + * kfd_ioctl_spm_buffer_header - SPM Buffer header for kfd_ioctl_spm_args->dest_buf + * + * @version [out]: spm versiom + * @bytes_copied [out]: amount of data for each sub-block + * @has_data_loss: [out]: boolean indicating whether data was lost for each sub-block + * (e.g. due to a ring-buffer overflow) + */ +struct kfd_ioctl_spm_buffer_header { + __u32 version; /* 0-23: minor 24-31: major */ + __u32 bytes_copied; + __u32 has_data_loss; + __u32 reserved[5]; +}; + /* * SVM event tracing via SMI system management interface * From 71b381643089af70100c2e6ba3618ac32102234b Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 10 Oct 2024 15:42:16 -0400 Subject: [PATCH 1357/2653] drm/amdkfd: implement spm buffer header on existing ASIC. Signed-off-by: James Zhu Reviewed-by: Bing Ma Reviewed-by: Gang Ba --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 61 ++++++++++++++++++++++++---- 1 file changed, 53 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index cdf38ad27100e..504f3f16eeedb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -29,6 +29,15 @@ #include // for use_mm() #include +/* + * SPM revision change log + * + * 0.1 - Initial revision + * 0.2 - add kfd_ioctl_spm_buffer_header + */ +#define KFD_IOCTL_SPM_MAJOR_VERSION 0 +#define KFD_IOCTL_SPM_MINOR_VERSION 2 + struct user_buf { uint64_t __user *user_addr; u32 ubufsize; @@ -379,25 +388,52 @@ int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) return 0; } -static void spm_update_dest_info(struct kfd_process_device *pdd, +static int spm_update_dest_info(struct kfd_process_device *pdd, struct kfd_ioctl_spm_args *user_spm_data) { struct kfd_spm_cntr *spm = pdd->spm_cntr; + int ret = 0; + mutex_lock(&pdd->spm_cntr->spm_worker_mutex); if (spm->has_user_buf) { - user_spm_data->bytes_copied = spm->size_copied; - user_spm_data->has_data_loss = spm->has_data_loss; + struct kfd_ioctl_spm_buffer_header spm_header; + uint64_t __user *user_address; + + user_spm_data->bytes_copied += spm->size_copied; + user_spm_data->has_data_loss += spm->has_data_loss; + + memset(&spm_header, 0, sizeof(spm_header)); + user_address = (uint64_t *)((uint64_t)spm->ubuf.user_addr - sizeof(spm_header)); + spm_header.version = KFD_IOCTL_SPM_MAJOR_VERSION << 24 | + KFD_IOCTL_SPM_MINOR_VERSION; + spm_header.bytes_copied = spm->size_copied; + spm_header.has_data_loss = spm->has_data_loss; spm->has_user_buf = false; + + ret = copy_to_user(user_address, &spm_header, sizeof(spm_header)); + if (ret) { + ret = -EFAULT; + goto out; + } } if (user_spm_data->dest_buf) { + user_spm_data->bytes_copied = 0; + user_spm_data->has_data_loss = 0; + spm->ubuf.user_addr = (uint64_t *)user_spm_data->dest_buf; spm->ubuf.ubufsize = user_spm_data->buf_size; + /* reserve space for kfd_ioctl_spm_buffer_header */ + spm->ubuf.user_addr = (uint64_t *)((uint64_t)spm->ubuf.user_addr + + sizeof(struct kfd_ioctl_spm_buffer_header)); + spm->ubuf.ubufsize -= sizeof(struct kfd_ioctl_spm_buffer_header); spm->has_data_loss = false; spm->size_copied = 0; spm->is_user_buf_filled = false; spm->has_user_buf = true; } +out: mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); + return ret; } static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm, @@ -441,6 +477,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev struct kfd_ioctl_spm_args *user_spm_data; struct kfd_spm_cntr *spm; unsigned long flags; + u32 ubufsize; int ret = 0; user_spm_data = (struct kfd_ioctl_spm_args *) data; @@ -449,8 +486,14 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev spm = pdd->spm_cntr; if (spm == NULL) { - mutex_unlock(&pdd->spm_mutex); - return -EINVAL; + ret = -EINVAL; + goto out; + } + + ubufsize = user_spm_data->buf_size; + if (ubufsize <= sizeof(struct kfd_ioctl_spm_buffer_header)) { + ret = -EINVAL; + goto out; } if (user_spm_data->timeout && spm->has_user_buf && @@ -464,8 +507,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev ret = 0; } else if (ret) { /* handle other errors normally, including -ERESTARTSYS */ - mutex_unlock(&pdd->spm_mutex); - return ret; + goto out; } } else if (!user_spm_data->timeout && spm->has_user_buf) { /* Copy (partial) data to user buffer */ @@ -477,7 +519,9 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev /* Get info about filled space in previous output buffer. * Setup new dest buf if provided. */ - spm_update_dest_info(pdd, user_spm_data); + ret = spm_update_dest_info(pdd, user_spm_data); + if (ret) + goto out; } if (user_spm_data->dest_buf) { @@ -514,6 +558,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev kthread_stop(pdd->dev->spm_monitor_thread); } +out: mutex_unlock(&pdd->spm_mutex); return ret; From 034232473642273b35db6589ec63b48053007d35 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 10 Oct 2024 17:53:04 -0400 Subject: [PATCH 1358/2653] drm/amdkfd: refactor kfd spm for later adding multiple xcc support Signed-off-by: James Zhu Reviewed-by: Bing Ma Reviewed-by: Gang Ba --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 192 +++++++++++++++-------- 3 files changed, 132 insertions(+), 64 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index c6057a41296b8..6f51f061681e9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1679,7 +1679,7 @@ int kfd_send_exception_to_runtime(struct kfd_process *p, bool kfd_is_locked(struct kfd_dev *kfd); void kfd_spm_init_process_device(struct kfd_process_device *pdd); -int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev); +void kfd_spm_release_process_device(struct kfd_process_device *pdd); int kfd_rlc_spm(struct kfd_process *p, void __user *data); /* PeerDirect support */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 274d18a4a5d45..50047fa9c79f5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1051,7 +1051,7 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) pdd->dev->id, p->lead_thread->pid); kfd_pc_sample_release(pdd); - kfd_release_spm(pdd, pdd->dev->adev); + kfd_spm_release_process_device(pdd); kfd_process_device_destroy_cwsr_dgpu(pdd); kfd_process_device_destroy_ib_mem(pdd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 504f3f16eeedb..da935d318e426 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -43,9 +43,8 @@ struct user_buf { u32 ubufsize; }; -struct kfd_spm_cntr { +struct kfd_spm_base { struct user_buf ubuf; - struct mutex spm_worker_mutex; u64 gpu_addr; u32 ring_size; u32 ring_rptr; @@ -53,16 +52,26 @@ struct kfd_spm_cntr { u32 has_data_loss; u32 *cpu_addr; void *spm_obj; - wait_queue_head_t spm_buf_wq; bool has_user_buf; bool is_user_buf_filled; bool is_spm_started; u32 warned_ring_rptr; }; +struct kfd_spm_cntr { + struct kfd_spm_base spm; + struct mutex spm_worker_mutex; + wait_queue_head_t spm_buf_wq; + u32 have_users_buf_cnt; + bool are_users_buf_filled; +}; + /* used to detect SPM overflow */ #define SPM_OVERFLOW_MAGIC 0xBEEFABCDDEADABCD +static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev); +static void _kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev); + static int kfd_spm_monitor_thread(void *param) { struct kfd_process_device *pdd = param; @@ -71,7 +80,7 @@ static int kfd_spm_monitor_thread(void *param) allow_signal(SIGKILL); while (!kthread_should_stop() && !signal_pending(node->spm_monitor_thread) && pdd->spm_cntr) { - struct kfd_spm_cntr *spm = pdd->spm_cntr; + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); bool need_schedule = false; usleep_range(1, 11); @@ -132,10 +141,11 @@ static int kfd_spm_monitor_thread_start(struct kfd_process_device *pdd) static void kfd_spm_preset(struct kfd_process_device *pdd, u32 size) { + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); uint64_t *overflow_ptr, *overflow_end_ptr; - overflow_ptr = (uint64_t *)((uint64_t)pdd->spm_cntr->cpu_addr - + pdd->spm_cntr->ring_size + 0x20); + overflow_ptr = (uint64_t *)((uint64_t)spm->cpu_addr + + spm->ring_size + 0x20); overflow_end_ptr = overflow_ptr + (size >> 3); /* SPM data filling is 0x20 alignment */ for ( ; overflow_ptr < overflow_end_ptr; overflow_ptr += 4) @@ -144,7 +154,7 @@ static void kfd_spm_preset(struct kfd_process_device *pdd, u32 size) static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) { - struct kfd_spm_cntr *spm = pdd->spm_cntr; + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); uint64_t __user *user_address; uint64_t *ring_buf; u32 user_buf_space_left; @@ -179,7 +189,8 @@ static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) spm->size_copied = spm->ubuf.ubufsize; spm->ring_rptr += user_buf_space_left; - WRITE_ONCE(spm->is_user_buf_filled, true); + spm->is_user_buf_filled = true; + WRITE_ONCE(pdd->spm_cntr->are_users_buf_filled, true); wake_up(&pdd->spm_cntr->spm_buf_wq); } @@ -188,7 +199,7 @@ static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) { - struct kfd_spm_cntr *spm = pdd->spm_cntr; + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); u32 overflow_size = 0; u32 size_to_copy; int ret = 0; @@ -208,6 +219,8 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) */ if (!spm->is_user_buf_filled) spm->is_user_buf_filled = true; + dev_dbg(pdd->dev->adev->dev, "[SPM] [%d|%d] rptr:0x%x--wptr:0x%x", + spm->has_user_buf, spm->is_user_buf_filled, spm->ring_rptr, ring_wptr); goto exit; } @@ -221,8 +234,8 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) } else { uint64_t *ring_start, *ring_end; - ring_start = (uint64_t *)((uint64_t)pdd->spm_cntr->cpu_addr + 0x20); - ring_end = ring_start + (pdd->spm_cntr->ring_size >> 3); + ring_start = (uint64_t *)((uint64_t)spm->cpu_addr + 0x20); + ring_end = ring_start + (spm->ring_size >> 3); for ( ; overflow_size < pdd->spm_overflow_reserved; overflow_size += 0x20) { uint64_t *overflow_ptr = ring_end + (overflow_size >> 3); @@ -268,7 +281,9 @@ static void kfd_spm_work(struct work_struct *work) kthread_use_mm(mm); { /* attach mm */ mutex_lock(&pdd->spm_cntr->spm_worker_mutex); + WRITE_ONCE(pdd->spm_cntr->are_users_buf_filled, false); kfd_spm_read_ring_buffer(pdd); + mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); } /* detach mm */ kthread_unuse_mm(mm); @@ -287,67 +302,90 @@ void kfd_spm_init_process_device(struct kfd_process_device *pdd) pdd->spm_cntr = NULL; } -static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +void kfd_spm_release_process_device(struct kfd_process_device *pdd) { - int ret = 0; + struct amdgpu_device *adev = pdd->dev->adev; - mutex_lock(&pdd->spm_mutex); - - if (pdd->spm_cntr) { - mutex_unlock(&pdd->spm_mutex); - return -EINVAL; - } + kfd_release_spm(pdd, adev); + mutex_destroy(&pdd->spm_mutex); +} - pdd->spm_cntr = kzalloc(sizeof(struct kfd_spm_cntr), GFP_KERNEL); - if (!pdd->spm_cntr) { - mutex_unlock(&pdd->spm_mutex); - return -ENOMEM; - } +static int _kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +{ + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); + int ret = 0; - /* git spm ring buffer 4M */ - pdd->spm_cntr->ring_size = order_base_2(4 * 1024 * 1024/4); - pdd->spm_cntr->ring_size = (1 << pdd->spm_cntr->ring_size) * 4; - pdd->spm_cntr->has_user_buf = false; + /* allocate 4M spm ring buffer */ + spm->ring_size = order_base_2(4 * 1024 * 1024/4); + spm->ring_size = (1 << spm->ring_size) * 4; ret = amdgpu_amdkfd_alloc_gtt_mem(adev, - pdd->spm_cntr->ring_size, &pdd->spm_cntr->spm_obj, - &pdd->spm_cntr->gpu_addr, (void *)&pdd->spm_cntr->cpu_addr, + spm->ring_size, &spm->spm_obj, + &spm->gpu_addr, (void *)&spm->cpu_addr, false, false); if (ret) - goto alloc_gtt_mem_failure; + goto out; /* reserve space to fix spm overflow */ - pdd->spm_cntr->ring_size -= pdd->spm_overflow_reserved; + spm->ring_size -= pdd->spm_overflow_reserved; ret = amdgpu_amdkfd_rlc_spm_acquire(adev, drm_priv_to_vm(pdd->drm_priv), - pdd->spm_cntr->gpu_addr, pdd->spm_cntr->ring_size); + spm->gpu_addr, spm->ring_size); /* * By definition, the last 8 DWs of the buffer are not part of the rings * and are instead part of the Meta data area. */ - pdd->spm_cntr->ring_size -= 0x20; + spm->ring_size -= 0x20; + if (ret) + goto rlc_spm_acquire_failure; + + kfd_spm_preset(pdd, pdd->spm_overflow_reserved); + spm->warned_ring_rptr = ~0; + goto out; + +rlc_spm_acquire_failure: + amdgpu_amdkfd_free_gtt_mem(adev, &spm->spm_obj); + memset(spm, 0, sizeof(*spm)); +out: + return ret; +} + +static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +{ + int ret = 0; + + mutex_lock(&pdd->spm_mutex); + + if (pdd->spm_cntr) { + ret = -EBUSY; + goto out; + } + + pdd->spm_cntr = kzalloc(sizeof(struct kfd_spm_cntr), GFP_KERNEL); + if (!pdd->spm_cntr) { + ret = -ENOMEM; + goto out; + } + + ret = _kfd_acquire_spm(pdd, adev); if (ret) goto acquire_spm_failure; + pdd->spm_cntr->have_users_buf_cnt = 0; mutex_init(&pdd->spm_cntr->spm_worker_mutex); init_waitqueue_head(&pdd->spm_cntr->spm_buf_wq); INIT_WORK(&pdd->spm_work, kfd_spm_work); spin_lock_init(&pdd->spm_irq_lock); - - kfd_spm_preset(pdd, pdd->spm_overflow_reserved); - pdd->spm_cntr->warned_ring_rptr = ~0; pdd->dev->spm_monitor_thread = NULL; goto out; acquire_spm_failure: - amdgpu_amdkfd_free_gtt_mem(adev, &pdd->spm_cntr->spm_obj); - -alloc_gtt_mem_failure: + _kfd_release_spm(pdd, adev); kfree(pdd->spm_cntr); pdd->spm_cntr = NULL; @@ -356,42 +394,61 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device return ret; } -int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +static void _kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +{ + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); + unsigned long flags; + + if (!spm->ring_size) + return; + amdgpu_amdkfd_rlc_spm_release(adev, drm_priv_to_vm(pdd->drm_priv)); + amdgpu_amdkfd_free_gtt_mem(adev, &(spm->spm_obj)); + + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + memset(spm, 0, sizeof(*spm)); + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + +} + +static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) { unsigned long flags; + int ret = 0; mutex_lock(&pdd->spm_mutex); if (!pdd->spm_cntr) { - mutex_unlock(&pdd->spm_mutex); - return -EINVAL; + ret = -EINVAL; + goto out; } if (pdd->dev->spm_monitor_thread) kthread_stop(pdd->dev->spm_monitor_thread); spin_lock_irqsave(&pdd->spm_irq_lock, flags); - pdd->spm_cntr->is_spm_started = false; + pdd->spm_cntr->spm.is_spm_started = false; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + amdgpu_amdkfd_rlc_spm_cntl(adev, 0); flush_work(&pdd->spm_work); wake_up_all(&pdd->spm_cntr->spm_buf_wq); - amdgpu_amdkfd_rlc_spm_release(adev, drm_priv_to_vm(pdd->drm_priv)); - amdgpu_amdkfd_free_gtt_mem(adev, &pdd->spm_cntr->spm_obj); + _kfd_release_spm(pdd, adev); spin_lock_irqsave(&pdd->spm_irq_lock, flags); + mutex_destroy(&(pdd->spm_cntr->spm_worker_mutex)); kfree(pdd->spm_cntr); pdd->spm_cntr = NULL; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); +out: mutex_unlock(&pdd->spm_mutex); - return 0; + return ret; } static int spm_update_dest_info(struct kfd_process_device *pdd, struct kfd_ioctl_spm_args *user_spm_data) { - struct kfd_spm_cntr *spm = pdd->spm_cntr; + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); int ret = 0; mutex_lock(&pdd->spm_cntr->spm_worker_mutex); @@ -409,6 +466,7 @@ static int spm_update_dest_info(struct kfd_process_device *pdd, spm_header.bytes_copied = spm->size_copied; spm_header.has_data_loss = spm->has_data_loss; spm->has_user_buf = false; + pdd->spm_cntr->have_users_buf_cnt--; ret = copy_to_user(user_address, &spm_header, sizeof(spm_header)); if (ret) { @@ -430,13 +488,15 @@ static int spm_update_dest_info(struct kfd_process_device *pdd, spm->size_copied = 0; spm->is_user_buf_filled = false; spm->has_user_buf = true; + pdd->spm_cntr->are_users_buf_filled = false; + pdd->spm_cntr->have_users_buf_cnt++; } out: mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); return ret; } -static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm, +static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm_cntr, struct kfd_ioctl_spm_args *user_spm_data) { int ret = 0; @@ -444,8 +504,8 @@ static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm, long timeout = msecs_to_jiffies(user_spm_data->timeout); long start_jiffies = jiffies; - ret = wait_event_interruptible_timeout(spm->spm_buf_wq, - (READ_ONCE(spm->is_user_buf_filled) == true), + ret = wait_event_interruptible_timeout(spm_cntr->spm_buf_wq, + (READ_ONCE(spm_cntr->are_users_buf_filled) == true), timeout); switch (ret) { @@ -475,17 +535,19 @@ static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm, static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_device *adev, void *data) { struct kfd_ioctl_spm_args *user_spm_data; - struct kfd_spm_cntr *spm; + struct kfd_spm_cntr *spm_cntr; + struct kfd_spm_base *spm; + bool need_schedule = false; unsigned long flags; u32 ubufsize; int ret = 0; user_spm_data = (struct kfd_ioctl_spm_args *) data; + dev_dbg(pdd->dev->adev->dev, "SPM start to set new destination buffer."); mutex_lock(&pdd->spm_mutex); - spm = pdd->spm_cntr; - - if (spm == NULL) { + spm_cntr = pdd->spm_cntr; + if (spm_cntr == NULL) { ret = -EINVAL; goto out; } @@ -496,9 +558,11 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev goto out; } - if (user_spm_data->timeout && spm->has_user_buf && - !READ_ONCE(spm->is_user_buf_filled)) { - ret = spm_wait_for_fill_awake(spm, user_spm_data); + if (user_spm_data->timeout && spm_cntr->have_users_buf_cnt && + !READ_ONCE(spm_cntr->are_users_buf_filled)) { + dev_dbg(pdd->dev->adev->dev, "SPM waiting for fill awake, timeout = %d ms.", + user_spm_data->timeout); + ret = spm_wait_for_fill_awake(spm_cntr, user_spm_data); if (ret == -ETIME) { /* Copy (partial) data to user buffer after a timeout */ schedule_work(&pdd->spm_work); @@ -509,12 +573,13 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev /* handle other errors normally, including -ERESTARTSYS */ goto out; } - } else if (!user_spm_data->timeout && spm->has_user_buf) { + } else if (!user_spm_data->timeout && spm_cntr->have_users_buf_cnt) { /* Copy (partial) data to user buffer */ schedule_work(&pdd->spm_work); flush_work(&pdd->spm_work); } + spm = &(spm_cntr->spm); if (spm->has_user_buf || user_spm_data->dest_buf) { /* Get info about filled space in previous output buffer. * Setup new dest buf if provided. @@ -542,7 +607,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev /* If SPM was already started, there may already * be data in the ring-buffer that needs to be read. */ - schedule_work(&pdd->spm_work); + need_schedule = true; } } else { amdgpu_amdkfd_rlc_spm_cntl(adev, 0); @@ -560,7 +625,10 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev out: mutex_unlock(&pdd->spm_mutex); + if (need_schedule) + schedule_work(&pdd->spm_work); + dev_dbg(pdd->dev->adev->dev, "SPM finish to set new destination buffer, ret = %d.", ret); return ret; } @@ -617,8 +685,8 @@ void kgd2kfd_spm_interrupt(struct kfd_dev *kfd) return; spin_lock_irqsave(&pdd->spm_irq_lock, flags); - if (pdd->spm_cntr && pdd->spm_cntr->is_spm_started) - pdd->spm_cntr->has_data_loss = true; + if (pdd->spm_cntr && pdd->spm_cntr->spm.is_spm_started) + pdd->spm_cntr->spm.has_data_loss = true; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); dev_dbg(dev->adev->dev, "SPM ring buffer stall."); From f71ccbbd2c307672a70bb3fb80954e779b58a46a Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 11 Oct 2024 13:40:42 -0400 Subject: [PATCH 1359/2653] drm/amdkfd: refactor rlc/gfx spm for later adding multiple xcc support. Signed-off-by: James Zhu Reviewed-by: Bing Ma Reviewed-by: Gang Ba --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 12 ++--- .../drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 51 ++++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 8 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 ++--- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 5 +- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 3 +- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 5 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 15 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 ++--- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 12 ++--- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 15 +++--- 13 files changed, 84 insertions(+), 74 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index db04d68a0bb3a..7eb4c7acd6345 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -455,12 +455,12 @@ void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) } #endif -void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, bool cntl); -int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, +void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, int xcc_id, bool cntl); +int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, int xcc_id, struct amdgpu_vm *vm, u64 gpu_addr, u32 size); -void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm *vm); -void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr); -void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev); +void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, int xcc_id, struct amdgpu_vm *vm); +void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr); +void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev, int xcc_id); #if IS_ENABLED(CONFIG_HSA_AMD_SVM) int kgd2kfd_init_zone_device(struct amdgpu_device *adev); @@ -473,7 +473,7 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev) #endif /* KGD2KFD callbacks */ -void kgd2kfd_spm_interrupt(struct kfd_dev *kfd); +void kgd2kfd_spm_interrupt(struct kfd_dev *kfd, int xcc_id); int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger); int kgd2kfd_resume_mm(struct mm_struct *mm); int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index 037e9aea2b691..5a8538691ebd1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -25,34 +25,35 @@ #include #include "amdgpu_ids.h" -void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, bool cntl) +void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, int xcc_id, bool cntl) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; - spin_lock(&adev->gfx.kiq[0].ring_lock); + spin_lock(&adev->gfx.kiq[xcc_id].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); if (cntl) - adev->gfx.spmfuncs->start(adev); + adev->gfx.spmfuncs->start(adev, xcc_id); else - adev->gfx.spmfuncs->stop(adev); + adev->gfx.spmfuncs->stop(adev, xcc_id); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq[0].ring_lock); + spin_unlock(&adev->gfx.kiq[xcc_id].ring_lock); } -void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) +void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; - spin_lock(&adev->gfx.kiq[0].ring_lock); + spin_lock(&adev->gfx.kiq[xcc_id].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); - adev->gfx.spmfuncs->set_rdptr(adev, rptr); + adev->gfx.spmfuncs->set_rdptr(adev, xcc_id, rptr); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq[0].ring_lock); + spin_unlock(&adev->gfx.kiq[xcc_id].ring_lock); } -int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm *vm, u64 gpu_addr, u32 size) +int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_vm *vm, u64 gpu_addr, u32 size) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; int r; if (!adev->gfx.rlc.funcs->update_spm_vmid) @@ -66,27 +67,27 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm * } /* init spm vmid with 0x0 */ - adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0); + adev->gfx.rlc.funcs->update_spm_vmid(adev, xcc_id, NULL, 0); /* set spm ring registers */ - spin_lock(&adev->gfx.kiq[0].ring_lock); + spin_lock(&adev->gfx.kiq[xcc_id].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); - adev->gfx.spmfuncs->set_spm_perfmon_ring_buf(adev, gpu_addr, size); + adev->gfx.spmfuncs->set_spm_perfmon_ring_buf(adev, xcc_id, gpu_addr, size); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq[0].ring_lock); + spin_unlock(&adev->gfx.kiq[xcc_id].ring_lock); return r; } -void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm *vm) +void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, int xcc_id, struct amdgpu_vm *vm) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; /* stop spm stream and interrupt */ - spin_lock(&adev->gfx.kiq[0].ring_lock); + spin_lock(&adev->gfx.kiq[xcc_id].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); - adev->gfx.spmfuncs->stop(adev); + adev->gfx.spmfuncs->stop(adev, xcc_id); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq[0].ring_lock); + spin_unlock(&adev->gfx.kiq[xcc_id].ring_lock); if (vm->reserved_vmid[AMDGPU_GFXHUB(0)]) { amdgpu_vmid_free_reserved(adev,AMDGPU_GFXHUB(0)); @@ -95,12 +96,12 @@ void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm /* revert spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); + adev->gfx.rlc.funcs->update_spm_vmid(adev, xcc_id, NULL, 0xf); } -void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev) +void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev, int xcc_id) { if (adev->kfd.dev) - kgd2kfd_spm_interrupt(adev->kfd.dev); + kgd2kfd_spm_interrupt(adev->kfd.dev, xcc_id); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index ca2b3bd4ee559..72e56a741c509 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -165,10 +165,10 @@ struct amdgpu_kiq { }; struct spm_funcs { - void (*start)(struct amdgpu_device *adev); - void (*stop)(struct amdgpu_device *adev); - void (*set_rdptr)(struct amdgpu_device *adev, u32 rptr); - void (*set_spm_perfmon_ring_buf)(struct amdgpu_device *adev, u64 gpu_rptr, u32 size); + void (*start)(struct amdgpu_device *adev, int xcc_id); + void (*stop)(struct amdgpu_device *adev, int xcc_id); + void (*set_rdptr)(struct amdgpu_device *adev, int xcc_id, u32 rptr); + void (*set_spm_perfmon_ring_buf)(struct amdgpu_device *adev, int xcc_id, u64 gpu_rptr, u32 size); /* Packet sizes */ int set_spm_config_size; }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h index c210625be2200..9aae8acd32bc0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h @@ -257,7 +257,8 @@ struct amdgpu_rlc_funcs { void (*stop)(struct amdgpu_device *adev); void (*reset)(struct amdgpu_device *adev); void (*start)(struct amdgpu_device *adev); - void (*update_spm_vmid)(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid); + void (*update_spm_vmid)(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_ring *ring, unsigned vmid); bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg); }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 23b300ed26c1d..2cddd37f45a12 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -832,7 +832,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid); if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, ring, job->vmid); + adev->gfx.rlc.funcs->update_spm_vmid(adev, ring->xcc_id, ring, job->vmid); if (ring->funcs->emit_gds_switch && gds_switch_needed) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index e4b8970902201..27b96459bcbee 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7797,7 +7797,7 @@ static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); } -static void gfx_v10_0_spm_start(struct amdgpu_device *adev) +static void gfx_v10_0_spm_start(struct amdgpu_device *adev, int xcc_id) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; @@ -7827,7 +7827,7 @@ static void gfx_v10_0_spm_start(struct amdgpu_device *adev) SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_INT_CNTL), 1); } -static void gfx_v10_0_spm_stop(struct amdgpu_device *adev) +static void gfx_v10_0_spm_stop(struct amdgpu_device *adev, int xcc_id) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; @@ -7843,7 +7843,7 @@ static void gfx_v10_0_spm_stop(struct amdgpu_device *adev) SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); } -static void gfx_v10_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) +static void gfx_v10_0_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; @@ -7852,7 +7852,7 @@ static void gfx_v10_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) } static void gfx_v10_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, - u64 gpu_addr, u32 size) + int xcc_id, u64 gpu_addr, u32 size) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; @@ -8421,7 +8421,8 @@ static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, } } -static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid) +static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_ring *ring, unsigned int vmid) { amdgpu_gfx_off_ctrl(adev, false); @@ -9967,7 +9968,7 @@ static int gfx_v10_0_spm_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - amdgpu_amdkfd_rlc_spm_interrupt(adev); + amdgpu_amdkfd_rlc_spm_interrupt(adev, 0); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 9dd49b1caa605..1f5aacc49d5a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -918,7 +918,7 @@ static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) /* init spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); return 0; } @@ -5553,7 +5553,8 @@ static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, return 0; } -static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) +static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_ring *ring, unsigned vmid) { u32 reg, pre_data, data; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 7905d646ea4cb..aa1cd043cf642 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -762,7 +762,7 @@ static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) /* init spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); return 0; } @@ -3957,6 +3957,7 @@ static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, } static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, + int xcc_id, struct amdgpu_ring *ring, unsigned vmid) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 2aa323dab34e3..1c1a7046a5b37 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -3245,7 +3245,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) /* init spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); return 0; } @@ -3471,7 +3471,8 @@ static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) return 0; } -static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) +static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_ring *ring, unsigned vmid) { u32 data; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index e72d50d2ba1dc..731d45a2ed713 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -1275,7 +1275,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) /* init spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); return 0; } @@ -5235,7 +5235,7 @@ static void gfx_v8_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, amdgpu_ring_write(ring, val); } -static void gfx_v8_0_spm_start(struct amdgpu_device *adev) +static void gfx_v8_0_spm_start(struct amdgpu_device *adev, int xcc_id) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; @@ -5260,7 +5260,7 @@ static void gfx_v8_0_spm_start(struct amdgpu_device *adev) gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_INT_CNTL, 1); } -static void gfx_v8_0_spm_stop(struct amdgpu_device *adev) +static void gfx_v8_0_spm_stop(struct amdgpu_device *adev, int xcc_id) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; @@ -5274,7 +5274,7 @@ static void gfx_v8_0_spm_stop(struct amdgpu_device *adev) gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, data); } -static void gfx_v8_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) +static void gfx_v8_0_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; @@ -5282,7 +5282,7 @@ static void gfx_v8_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) } static void gfx_v8_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, - u64 gpu_addr, u32 size) + int xcc_id, u64 gpu_addr, u32 size) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; @@ -5640,7 +5640,8 @@ static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) } } -static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) +static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_ring *ring, unsigned vmid) { u32 data; @@ -6881,7 +6882,7 @@ static int gfx_v8_0_spm_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - amdgpu_amdkfd_rlc_spm_interrupt(adev); + amdgpu_amdkfd_rlc_spm_interrupt(adev, 0); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 83f3ef150332a..949d543a97628 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4800,7 +4800,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) return r; } -static void gfx_v9_0_spm_start(struct amdgpu_device *adev) +static void gfx_v9_0_spm_start(struct amdgpu_device *adev, int xcc_id) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; @@ -4825,7 +4825,7 @@ static void gfx_v9_0_spm_start(struct amdgpu_device *adev) SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_INT_CNTL), 1); } -static void gfx_v9_0_spm_stop(struct amdgpu_device *adev) +static void gfx_v9_0_spm_stop(struct amdgpu_device *adev, int xcc_id) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; @@ -4847,7 +4847,7 @@ static void gfx_v9_0_spm_stop(struct amdgpu_device *adev) SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), 0); } -static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) +static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; @@ -4855,7 +4855,8 @@ static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), rptr); } -static void gfx_v9_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, u64 gpu_addr, u32 size) +static void gfx_v9_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, + int xcc_id, u64 gpu_addr, u32 size) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; @@ -5275,7 +5276,8 @@ static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev, WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); } -static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid) +static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_ring *ring, unsigned int vmid) { amdgpu_gfx_off_ctrl(adev, false); @@ -7225,7 +7227,7 @@ static int gfx_v9_0_spm_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - amdgpu_amdkfd_rlc_spm_interrupt(adev); + amdgpu_amdkfd_rlc_spm_interrupt(adev, 0); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 7314ad08fde31..a6b3c80f05dc9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -1453,7 +1453,7 @@ static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) { /* init spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); return 0; } @@ -1664,12 +1664,12 @@ static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) return 0; } -static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, - unsigned vmid) +static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, + int inst, struct amdgpu_ring *ring, unsigned int vmid) { u32 reg, pre_data, data; - reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); + reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL); if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) pre_data = RREG32_NO_KIQ(reg); else @@ -1680,9 +1680,9 @@ static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu if (pre_data != data) { if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { - WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); + WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data); } else - WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); + WREG32_SOC15(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data); } } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index da935d318e426..c81edfa086043 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -267,7 +267,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) exit: kfd_spm_preset(pdd, overflow_size); - amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->adev, spm->ring_rptr); + amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->adev, 0, spm->ring_rptr); return ret; } @@ -329,7 +329,7 @@ static int _kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device /* reserve space to fix spm overflow */ spm->ring_size -= pdd->spm_overflow_reserved; - ret = amdgpu_amdkfd_rlc_spm_acquire(adev, drm_priv_to_vm(pdd->drm_priv), + ret = amdgpu_amdkfd_rlc_spm_acquire(adev, 0, drm_priv_to_vm(pdd->drm_priv), spm->gpu_addr, spm->ring_size); /* @@ -401,7 +401,7 @@ static void _kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_devic if (!spm->ring_size) return; - amdgpu_amdkfd_rlc_spm_release(adev, drm_priv_to_vm(pdd->drm_priv)); + amdgpu_amdkfd_rlc_spm_release(adev, 0, drm_priv_to_vm(pdd->drm_priv)); amdgpu_amdkfd_free_gtt_mem(adev, &(spm->spm_obj)); spin_lock_irqsave(&pdd->spm_irq_lock, flags); @@ -428,7 +428,7 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device pdd->spm_cntr->spm.is_spm_started = false; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); - amdgpu_amdkfd_rlc_spm_cntl(adev, 0); + amdgpu_amdkfd_rlc_spm_cntl(adev, 0, 0); flush_work(&pdd->spm_work); wake_up_all(&pdd->spm_cntr->spm_buf_wq); @@ -591,8 +591,9 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev if (user_spm_data->dest_buf) { /* Start SPM if necessary*/ + if (spm->is_spm_started == false) { - amdgpu_amdkfd_rlc_spm_cntl(adev, 1); + amdgpu_amdkfd_rlc_spm_cntl(adev, 0, 1); spin_lock_irqsave(&pdd->spm_irq_lock, flags); spm->is_spm_started = true; /* amdgpu_amdkfd_rlc_spm_cntl() will reset SPM and wptr will become 0. @@ -610,7 +611,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev need_schedule = true; } } else { - amdgpu_amdkfd_rlc_spm_cntl(adev, 0); + amdgpu_amdkfd_rlc_spm_cntl(adev, 0, 0); spin_lock_irqsave(&pdd->spm_irq_lock, flags); spm->is_spm_started = false; /* amdgpu_amdkfd_rlc_spm_cntl() will reset SPM and wptr will become 0. @@ -666,7 +667,7 @@ int kfd_rlc_spm(struct kfd_process *p, void *data) return -EINVAL; } -void kgd2kfd_spm_interrupt(struct kfd_dev *kfd) +void kgd2kfd_spm_interrupt(struct kfd_dev *kfd, int xcc_id) { struct kfd_process_device *pdd; struct kfd_node *dev = kfd->nodes[0]; From 3dbd6e9d2cc268277cee5312275ef24b4ce560da Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 11 Oct 2024 21:11:21 -0400 Subject: [PATCH 1360/2653] drm/amdkfd: add general multiple xcc support on current kfd SPM. Signed-off-by: James Zhu Reviewed-by: Bing Ma Reviewed-by: Gang Ba --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 215 ++++++++++++++++----------- 1 file changed, 125 insertions(+), 90 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index c81edfa086043..06f328f53eaa4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -34,9 +34,10 @@ * * 0.1 - Initial revision * 0.2 - add kfd_ioctl_spm_buffer_header + * 0.3 - add multiple XCC support */ #define KFD_IOCTL_SPM_MAJOR_VERSION 0 -#define KFD_IOCTL_SPM_MINOR_VERSION 2 +#define KFD_IOCTL_SPM_MINOR_VERSION 3 struct user_buf { uint64_t __user *user_addr; @@ -59,7 +60,8 @@ struct kfd_spm_base { }; struct kfd_spm_cntr { - struct kfd_spm_base spm; + struct kfd_spm_base spm[MAX_XCP]; + int spm_use_cnt; struct mutex spm_worker_mutex; wait_queue_head_t spm_buf_wq; u32 have_users_buf_cnt; @@ -70,7 +72,7 @@ struct kfd_spm_cntr { #define SPM_OVERFLOW_MAGIC 0xBEEFABCDDEADABCD static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev); -static void _kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev); +static void _kfd_release_spm(struct kfd_process_device *pdd, int inst, struct amdgpu_device *adev); static int kfd_spm_monitor_thread(void *param) { @@ -80,20 +82,24 @@ static int kfd_spm_monitor_thread(void *param) allow_signal(SIGKILL); while (!kthread_should_stop() && !signal_pending(node->spm_monitor_thread) && pdd->spm_cntr) { - struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); bool need_schedule = false; + u32 inst; usleep_range(1, 11); if (!mutex_trylock(&pdd->spm_cntr->spm_worker_mutex)) continue; - if (spm->is_spm_started) { + for_each_inst(inst, node->xcc_mask) { + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); u32 warned_ring_rptr; u32 ring_size; u32 ring_rptr; u32 ring_wptr; + if (!spm->is_spm_started) + continue; + ring_size = spm->ring_size; ring_rptr = spm->ring_rptr; warned_ring_rptr = spm->warned_ring_rptr; @@ -105,8 +111,8 @@ static int kfd_spm_monitor_thread(void *param) spm->warned_ring_rptr = ring_rptr; if (!need_schedule) { dev_dbg(node->adev->dev, - "SPM soft interrupt rptr:0x%08x--wptr:0x%08x", - ring_rptr, ring_wptr); + "[SPM#%d] soft interrupt rptr:0x%08x--wptr:0x%08x", + inst, ring_rptr, ring_wptr); need_schedule = true; } } @@ -139,9 +145,8 @@ static int kfd_spm_monitor_thread_start(struct kfd_process_device *pdd) return ret; } -static void kfd_spm_preset(struct kfd_process_device *pdd, u32 size) +static void kfd_spm_preset(struct kfd_spm_base *spm, u32 size) { - struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); uint64_t *overflow_ptr, *overflow_end_ptr; overflow_ptr = (uint64_t *)((uint64_t)spm->cpu_addr @@ -152,9 +157,9 @@ static void kfd_spm_preset(struct kfd_process_device *pdd, u32 size) *overflow_ptr = SPM_OVERFLOW_MAGIC; } -static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) +static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy, int inst) { - struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); uint64_t __user *user_address; uint64_t *ring_buf; u32 user_buf_space_left; @@ -190,16 +195,14 @@ static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) spm->size_copied = spm->ubuf.ubufsize; spm->ring_rptr += user_buf_space_left; spm->is_user_buf_filled = true; - WRITE_ONCE(pdd->spm_cntr->are_users_buf_filled, true); - wake_up(&pdd->spm_cntr->spm_buf_wq); } return ret; } -static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) +static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd, int inst) { - struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); u32 overflow_size = 0; u32 size_to_copy; int ret = 0; @@ -219,7 +222,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) */ if (!spm->is_user_buf_filled) spm->is_user_buf_filled = true; - dev_dbg(pdd->dev->adev->dev, "[SPM] [%d|%d] rptr:0x%x--wptr:0x%x", + dev_dbg(pdd->dev->adev->dev, "[SPM#%d] [%d|%d] rptr:0x%x--wptr:0x%x", inst, spm->has_user_buf, spm->is_user_buf_filled, spm->ring_rptr, ring_wptr); goto exit; } @@ -230,7 +233,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) spm->warned_ring_rptr = spm->ring_rptr; if (ring_wptr > spm->ring_rptr) { size_to_copy = ring_wptr - spm->ring_rptr; - ret = kfd_spm_data_copy(pdd, size_to_copy); + ret = kfd_spm_data_copy(pdd, size_to_copy, inst); } else { uint64_t *ring_start, *ring_end; @@ -249,7 +252,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) memcpy(ring_start, ring_end, overflow_size); size_to_copy = spm->ring_size - spm->ring_rptr; - ret = kfd_spm_data_copy(pdd, size_to_copy); + ret = kfd_spm_data_copy(pdd, size_to_copy, inst); /* correct counter start point */ if (spm->ring_size == spm->ring_rptr) { @@ -261,13 +264,13 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) spm->ring_rptr = 0; size_to_copy = ring_wptr - spm->ring_rptr; if (!ret) - ret = kfd_spm_data_copy(pdd, size_to_copy); + ret = kfd_spm_data_copy(pdd, size_to_copy, inst); } } exit: - kfd_spm_preset(pdd, overflow_size); - amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->adev, 0, spm->ring_rptr); + kfd_spm_preset(spm, overflow_size); + amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->adev, inst, spm->ring_rptr); return ret; } @@ -280,10 +283,21 @@ static void kfd_spm_work(struct work_struct *work) if (mm) { kthread_use_mm(mm); { /* attach mm */ + int inst; + mutex_lock(&pdd->spm_cntr->spm_worker_mutex); WRITE_ONCE(pdd->spm_cntr->are_users_buf_filled, false); - kfd_spm_read_ring_buffer(pdd); + for_each_inst(inst, pdd->dev->xcc_mask) { + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); + kfd_spm_read_ring_buffer(pdd, inst); + if (spm->is_user_buf_filled) + WRITE_ONCE(pdd->spm_cntr->are_users_buf_filled, true); + } + if (READ_ONCE(pdd->spm_cntr->are_users_buf_filled)) { + pr_debug("SPM wake up buffer work queue."); + wake_up(&pdd->spm_cntr->spm_buf_wq); + } mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); } /* detach mm */ kthread_unuse_mm(mm); @@ -310,9 +324,9 @@ void kfd_spm_release_process_device(struct kfd_process_device *pdd) mutex_destroy(&pdd->spm_mutex); } -static int _kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +static int _kfd_acquire_spm(struct kfd_process_device *pdd, int inst, struct amdgpu_device *adev) { - struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); int ret = 0; /* allocate 4M spm ring buffer */ @@ -329,7 +343,7 @@ static int _kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device /* reserve space to fix spm overflow */ spm->ring_size -= pdd->spm_overflow_reserved; - ret = amdgpu_amdkfd_rlc_spm_acquire(adev, 0, drm_priv_to_vm(pdd->drm_priv), + ret = amdgpu_amdkfd_rlc_spm_acquire(adev, inst, drm_priv_to_vm(pdd->drm_priv), spm->gpu_addr, spm->ring_size); /* @@ -341,7 +355,7 @@ static int _kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device if (ret) goto rlc_spm_acquire_failure; - kfd_spm_preset(pdd, pdd->spm_overflow_reserved); + kfd_spm_preset(spm, pdd->spm_overflow_reserved); spm->warned_ring_rptr = ~0; goto out; @@ -355,6 +369,7 @@ static int _kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) { int ret = 0; + int inst; mutex_lock(&pdd->spm_mutex); @@ -369,9 +384,12 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device goto out; } - ret = _kfd_acquire_spm(pdd, adev); - if (ret) - goto acquire_spm_failure; + for_each_inst(inst, pdd->dev->xcc_mask) { + ret = _kfd_acquire_spm(pdd, inst, adev); + if (ret) + goto acquire_spm_failure; + pdd->spm_cntr->spm_use_cnt++; + } pdd->spm_cntr->have_users_buf_cnt = 0; mutex_init(&pdd->spm_cntr->spm_worker_mutex); @@ -385,7 +403,8 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device goto out; acquire_spm_failure: - _kfd_release_spm(pdd, adev); + for_each_inst(inst, pdd->dev->xcc_mask) + _kfd_release_spm(pdd, inst, adev); kfree(pdd->spm_cntr); pdd->spm_cntr = NULL; @@ -394,25 +413,27 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device return ret; } -static void _kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +static void _kfd_release_spm(struct kfd_process_device *pdd, int inst, struct amdgpu_device *adev) { - struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); unsigned long flags; if (!spm->ring_size) return; - amdgpu_amdkfd_rlc_spm_release(adev, 0, drm_priv_to_vm(pdd->drm_priv)); + amdgpu_amdkfd_rlc_spm_release(adev, inst, drm_priv_to_vm(pdd->drm_priv)); amdgpu_amdkfd_free_gtt_mem(adev, &(spm->spm_obj)); spin_lock_irqsave(&pdd->spm_irq_lock, flags); memset(spm, 0, sizeof(*spm)); spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + --pdd->spm_cntr->spm_use_cnt; } static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) { unsigned long flags; + int inst; int ret = 0; mutex_lock(&pdd->spm_mutex); @@ -424,15 +445,17 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device if (pdd->dev->spm_monitor_thread) kthread_stop(pdd->dev->spm_monitor_thread); - spin_lock_irqsave(&pdd->spm_irq_lock, flags); - pdd->spm_cntr->spm.is_spm_started = false; - spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); - - amdgpu_amdkfd_rlc_spm_cntl(adev, 0, 0); + for_each_inst(inst, pdd->dev->xcc_mask) { + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + pdd->spm_cntr->spm[inst].is_spm_started = false; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + amdgpu_amdkfd_rlc_spm_cntl(adev, inst, 0); + } flush_work(&pdd->spm_work); wake_up_all(&pdd->spm_cntr->spm_buf_wq); - _kfd_release_spm(pdd, adev); + for_each_inst(inst, pdd->dev->xcc_mask) + _kfd_release_spm(pdd, inst, adev); spin_lock_irqsave(&pdd->spm_irq_lock, flags); mutex_destroy(&(pdd->spm_cntr->spm_worker_mutex)); @@ -446,9 +469,9 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device } static int spm_update_dest_info(struct kfd_process_device *pdd, - struct kfd_ioctl_spm_args *user_spm_data) + int inst, struct kfd_ioctl_spm_args *user_spm_data) { - struct kfd_spm_base *spm = &(pdd->spm_cntr->spm); + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); int ret = 0; mutex_lock(&pdd->spm_cntr->spm_worker_mutex); @@ -534,15 +557,13 @@ static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm_cntr, static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_device *adev, void *data) { - struct kfd_ioctl_spm_args *user_spm_data; + struct kfd_ioctl_spm_args user_spm_data, *user_spm_ptr; struct kfd_spm_cntr *spm_cntr; - struct kfd_spm_base *spm; bool need_schedule = false; unsigned long flags; u32 ubufsize; int ret = 0; - - user_spm_data = (struct kfd_ioctl_spm_args *) data; + int inst; dev_dbg(pdd->dev->adev->dev, "SPM start to set new destination buffer."); mutex_lock(&pdd->spm_mutex); @@ -552,17 +573,22 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev goto out; } - ubufsize = user_spm_data->buf_size; + user_spm_ptr = (struct kfd_ioctl_spm_args *) data; + ubufsize = user_spm_ptr->buf_size / spm_cntr->spm_use_cnt; + ubufsize = rounddown(ubufsize, 32); + if (ubufsize <= sizeof(struct kfd_ioctl_spm_buffer_header)) { ret = -EINVAL; goto out; } - if (user_spm_data->timeout && spm_cntr->have_users_buf_cnt && + memcpy(&user_spm_data, user_spm_ptr, sizeof(user_spm_data)); + user_spm_data.buf_size = ubufsize; + if (user_spm_data.timeout && spm_cntr->have_users_buf_cnt && !READ_ONCE(spm_cntr->are_users_buf_filled)) { dev_dbg(pdd->dev->adev->dev, "SPM waiting for fill awake, timeout = %d ms.", - user_spm_data->timeout); - ret = spm_wait_for_fill_awake(spm_cntr, user_spm_data); + user_spm_data.timeout); + ret = spm_wait_for_fill_awake(spm_cntr, &user_spm_data); if (ret == -ETIME) { /* Copy (partial) data to user buffer after a timeout */ schedule_work(&pdd->spm_work); @@ -573,55 +599,58 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev /* handle other errors normally, including -ERESTARTSYS */ goto out; } - } else if (!user_spm_data->timeout && spm_cntr->have_users_buf_cnt) { + } else if (!user_spm_data.timeout && spm_cntr->have_users_buf_cnt) { /* Copy (partial) data to user buffer */ schedule_work(&pdd->spm_work); flush_work(&pdd->spm_work); } - spm = &(spm_cntr->spm); - if (spm->has_user_buf || user_spm_data->dest_buf) { - /* Get info about filled space in previous output buffer. - * Setup new dest buf if provided. - */ - ret = spm_update_dest_info(pdd, user_spm_data); - if (ret) - goto out; - } + for_each_inst(inst, pdd->dev->xcc_mask) { + struct kfd_spm_base *spm = &(spm_cntr->spm[inst]); - if (user_spm_data->dest_buf) { - /* Start SPM if necessary*/ + if (spm->has_user_buf || user_spm_data.dest_buf) { + /* Get info about filled space in previous output buffer. + * Setup new dest buf if provided. + */ + ret = spm_update_dest_info(pdd, inst, &user_spm_data); + if (ret) + goto out; + } - if (spm->is_spm_started == false) { - amdgpu_amdkfd_rlc_spm_cntl(adev, 0, 1); + if (user_spm_data.dest_buf) { + /* Start SPM if necessary*/ + if (spm->is_spm_started == false) { + amdgpu_amdkfd_rlc_spm_cntl(adev, inst, 1); + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + spm->is_spm_started = true; + /* amdgpu_amdkfd_rlc_spm_cntl() will reset SPM and + * wptr will become 0, adjust rptr accordingly. + */ + spm->ring_rptr = 0; + spm->warned_ring_rptr = ~0; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + if (!pdd->dev->spm_monitor_thread) + kfd_spm_monitor_thread_start(pdd); + } else { + /* If SPM was already started, there may already + * be data in the ring-buffer that needs to be read. + */ + need_schedule = true; + } + user_spm_data.dest_buf += ubufsize; + } else { + amdgpu_amdkfd_rlc_spm_cntl(adev, inst, 0); spin_lock_irqsave(&pdd->spm_irq_lock, flags); - spm->is_spm_started = true; + spm->is_spm_started = false; /* amdgpu_amdkfd_rlc_spm_cntl() will reset SPM and wptr will become 0. * Adjust rptr accordingly */ spm->ring_rptr = 0; spm->warned_ring_rptr = ~0; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); - if (!pdd->dev->spm_monitor_thread) - kfd_spm_monitor_thread_start(pdd); - } else { - /* If SPM was already started, there may already - * be data in the ring-buffer that needs to be read. - */ - need_schedule = true; + if (pdd->dev->spm_monitor_thread) + kthread_stop(pdd->dev->spm_monitor_thread); } - } else { - amdgpu_amdkfd_rlc_spm_cntl(adev, 0, 0); - spin_lock_irqsave(&pdd->spm_irq_lock, flags); - spm->is_spm_started = false; - /* amdgpu_amdkfd_rlc_spm_cntl() will reset SPM and wptr will become 0. - * Adjust rptr accordingly - */ - spm->ring_rptr = 0; - spm->warned_ring_rptr = ~0; - spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); - if (pdd->dev->spm_monitor_thread) - kthread_stop(pdd->dev->spm_monitor_thread); } out: @@ -670,12 +699,18 @@ int kfd_rlc_spm(struct kfd_process *p, void *data) void kgd2kfd_spm_interrupt(struct kfd_dev *kfd, int xcc_id) { struct kfd_process_device *pdd; - struct kfd_node *dev = kfd->nodes[0]; - uint16_t pasid = dev->spm_pasid; - - struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); + struct kfd_node *dev; + uint8_t xcp_id; + uint16_t pasid; + struct kfd_process *p; unsigned long flags; + xcp_id = kfd->adev->xcp_mgr ? + fls(amdgpu_xcp_get_partition(kfd->adev->xcp_mgr, AMDGPU_XCP_GFX, xcc_id)) - 1 : 0; + dev = kfd->nodes[xcp_id]; + pasid = dev->spm_pasid; + p = kfd_lookup_process_by_pasid(pasid); + if (!p) { dev_dbg(dev->adev->dev, "kfd_spm_interrupt p = %p\n", p); return; /* Presumably process exited. */ @@ -686,11 +721,11 @@ void kgd2kfd_spm_interrupt(struct kfd_dev *kfd, int xcc_id) return; spin_lock_irqsave(&pdd->spm_irq_lock, flags); - if (pdd->spm_cntr && pdd->spm_cntr->spm.is_spm_started) - pdd->spm_cntr->spm.has_data_loss = true; + if (pdd->spm_cntr && pdd->spm_cntr->spm[xcc_id].is_spm_started) + pdd->spm_cntr->spm[xcc_id].has_data_loss = true; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); - dev_dbg(dev->adev->dev, "SPM ring buffer stall."); + dev_dbg(pdd->dev->adev->dev, "[SPM#%d:%d] ring buffer stall.", xcp_id, xcc_id); kfd_unref_process(p); } From 7352822ea0301861f4aa1090bc3a99dd331d668d Mon Sep 17 00:00:00 2001 From: James Zhu Date: Sat, 12 Oct 2024 00:08:27 -0400 Subject: [PATCH 1361/2653] drm/amdkfd: add multiple xcc support on gfx_v9_4_3. Signed-off-by: James Zhu Reviewed-by: Bing Ma Reviewed-by: Gang Ba --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 194 ++++++++++++++++++++++-- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 3 +- 2 files changed, 185 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index a6b3c80f05dc9..5ae8f484608af 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -169,6 +169,8 @@ static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info); +static void gfx_v9_4_3_update_spm_vmid_internal(struct amdgpu_device *adev, + int xcc_id, unsigned int vmid); static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); @@ -1065,6 +1067,13 @@ static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) num_xcc = NUM_XCC(adev->gfx.xcc_mask); + /* SPM */ + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_RLC, + GFX_9_0__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT, + &adev->gfx.spm_irq); + if (r) + return r; + /* EOP Event */ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); if (r) @@ -1451,10 +1460,14 @@ static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) { - /* init spm vmid with 0xf */ - if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); + int i, num_xcc; + + if (amdgpu_sriov_vf(adev)) + return 0; + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) + adev->gfx.rlc.funcs->update_spm_vmid(adev, i, NULL, 0xf); return 0; } @@ -1629,14 +1642,15 @@ static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) { int r; + gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { - gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); /* legacy rlc firmware loading */ r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); if (r) return r; - gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); } + gfx_v9_4_3_update_spm_vmid_internal(adev, xcc_id, 0xf); + gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); /* disable CG */ @@ -1664,28 +1678,38 @@ static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) return 0; } -static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, - int inst, struct amdgpu_ring *ring, unsigned int vmid) +static void gfx_v9_4_3_update_spm_vmid_internal(struct amdgpu_device *adev, + int xcc_id, unsigned int vmid) { u32 reg, pre_data, data; - reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL); + reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL); if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) pre_data = RREG32_NO_KIQ(reg); else - pre_data = RREG32(reg); + pre_data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL); data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; if (pre_data != data) { if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { - WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data); + WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data); } else - WREG32_SOC15(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data); } } +static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_ring *ring, unsigned int vmid) +{ + amdgpu_gfx_off_ctrl(adev, false); + + gfx_v9_4_3_update_spm_vmid_internal(adev, xcc_id, vmid); + + amdgpu_gfx_off_ctrl(adev, true); +} + static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, @@ -2374,6 +2398,7 @@ static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) int i, num_xcc; amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.spm_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); @@ -2510,12 +2535,112 @@ static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); } +static void gfx_v9_4_3_spm_start(struct amdgpu_device *adev, int xcc_id) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; + uint32_t data = 0; + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_PERFMON_CNTL); + data |= RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK; + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_PERFMON_CNTL), data); + + /* When SPM is reset, RLC automatically resets wptr to 0. + * Manually reset rptr to match this. + */ + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_RING_RDPTR), 0); + + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_INT_CNTL), 1); + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL); + data |= RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK; + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL, data); +} + +static void gfx_v9_4_3_spm_stop(struct amdgpu_device *adev, int xcc_id) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; + uint32_t data = 0; + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL); + data &= (~RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL, data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_STOP_COUNTING); + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_PERFMON_CNTL), data); + + /* When SPM is reset, RLC automatically resets wptr to 0. + * Manually reset rptr to match this. + */ + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_RING_RDPTR), 0); +} + +static void gfx_v9_4_3_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; + + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_RING_RDPTR), rptr); +} + +static void gfx_v9_4_3_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, + int xcc_id, u64 gpu_addr, u32 size) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; + + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, + regRLC_SPM_PERFMON_RING_BASE_LO), lower_32_bits(gpu_addr)); + + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, + regRLC_SPM_PERFMON_RING_BASE_HI), upper_32_bits(gpu_addr)); + + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), + regRLC_SPM_PERFMON_RING_SIZE), size); + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), + regRLC_SPM_SEGMENT_THRESHOLD), 0x1); + + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_PERFMON_CNTL), 0); +} + +static const struct spm_funcs gfx_v9_4_3_spm_funcs = { + .start = &gfx_v9_4_3_spm_start, + .stop = &gfx_v9_4_3_spm_stop, + .set_rdptr = &gfx_v9_4_3_spm_set_rdptr, + .set_spm_perfmon_ring_buf = &gfx_v9_4_3_set_spm_perfmon_ring_buf, + .set_spm_config_size = 30, +}; + +static void gfx_v9_4_3_set_spm_funcs(struct amdgpu_device *adev) +{ + adev->gfx.spmfuncs = &gfx_v9_4_3_spm_funcs; +} + static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), AMDGPU_MAX_COMPUTE_RINGS); + gfx_v9_4_3_set_spm_funcs(adev); gfx_v9_4_3_set_kiq_pm4_funcs(adev); gfx_v9_4_3_set_ring_funcs(adev); gfx_v9_4_3_set_irq_funcs(adev); @@ -2537,6 +2662,10 @@ static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) if (r) return r; + r = amdgpu_irq_get(adev, &adev->gfx.spm_irq, 0); + if (r) + return r; + r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); if (r) return r; @@ -3407,6 +3536,41 @@ static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ } +static int gfx_v9_4_3_spm_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + int i, num_xcc; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) { + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + WREG32_SOC15(GC, GET_INST(GC, i), regRLC_SPM_INT_CNTL, 0); + break; + case AMDGPU_IRQ_STATE_ENABLE: + WREG32_SOC15(GC, GET_INST(GC, i), regRLC_SPM_INT_CNTL, 1); + break; + default: + break; + } + } + return 0; +} + +static int gfx_v9_4_3_spm_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + int xcc_id; + + xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); + + amdgpu_amdkfd_rlc_spm_interrupt(adev, xcc_id); + return 0; +} + static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, uint32_t pipe, bool enable) { @@ -4832,11 +4996,19 @@ static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { .process = gfx_v9_4_3_priv_inst_irq, }; +static const struct amdgpu_irq_src_funcs gfx_v9_4_3_spm_irq_funcs = { + .set = gfx_v9_4_3_spm_set_interrupt_state, + .process = gfx_v9_4_3_spm_irq, +}; + static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) { adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; + adev->gfx.spm_irq.num_types = 1; + adev->gfx.spm_irq.funcs = &gfx_v9_4_3_spm_irq_funcs; + adev->gfx.priv_reg_irq.num_types = 1; adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 06f328f53eaa4..fdf508e5e89c2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -35,9 +35,10 @@ * 0.1 - Initial revision * 0.2 - add kfd_ioctl_spm_buffer_header * 0.3 - add multiple XCC support + * 0.4 - add gfx_v9_4_3 SPM support */ #define KFD_IOCTL_SPM_MAJOR_VERSION 0 -#define KFD_IOCTL_SPM_MINOR_VERSION 3 +#define KFD_IOCTL_SPM_MINOR_VERSION 4 struct user_buf { uint64_t __user *user_addr; From d500fc504c213f3e62e7197cc32411d871a044ba Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 2 Oct 2024 09:49:37 -0400 Subject: [PATCH 1362/2653] drm/amdgpu: change xcp_id to xcc_id psp fw implementation needs xcc_mask as input actually. Signed-off-by: James Zhu Reviewed-by: Lijo Lazar Reviewed-by: Feifei Xu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 13 ++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 +- drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 2 +- 5 files changed, 9 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 510e836ddd36d..85dfc44679003 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -901,7 +901,7 @@ bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id) } /* Config CGTT_SQ_CLK_CTRL */ -int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, +int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcc_id, bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable) { int r; @@ -909,7 +909,7 @@ int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, if (!adev->kfd.init_complete) return 0; - r = psp_config_sq_perfmon(&adev->psp, xcp_id, core_override_enable, + r = psp_config_sq_perfmon(&adev->psp, xcc_id, core_override_enable, reg_override_enable, perfmon_override_enable); return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 7eb4c7acd6345..4ac58446a8143 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -278,7 +278,7 @@ int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off, u32 inst); int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id); int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id); -int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, +int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcc_id, bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index de8c01969e660..84e43f91a6495 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -4004,7 +4004,7 @@ int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) } int psp_config_sq_perfmon(struct psp_context *psp, - uint32_t xcp_id, bool core_override_enable, + uint32_t xcc_id, bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable) { int ret; @@ -4012,11 +4012,6 @@ int psp_config_sq_perfmon(struct psp_context *psp, if (amdgpu_sriov_vf(psp->adev)) return 0; - if (xcp_id > MAX_XCP) { - dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id); - return -EINVAL; - } - if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); @@ -4025,15 +4020,15 @@ int psp_config_sq_perfmon(struct psp_context *psp, struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON; - cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id); + cmd->cmd.config_sq_perfmon.gfx_xcc_mask = BIT_MASK(xcc_id); cmd->cmd.config_sq_perfmon.core_override = core_override_enable; cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable; cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable; ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); if (ret) - dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n", - xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable); + dev_warn(psp->adev->dev, "PSP failed to config sq: xcc%d core%d reg%d perfmon%d\n", + xcc_id, core_override_enable, reg_override_enable, perfmon_override_enable); release_psp_cmd_buf(psp); return ret; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 237b624aa51ca..022b70522d763 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -615,7 +615,7 @@ int is_psp_fw_valid(struct psp_bin_desc bin); int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev); bool amdgpu_psp_get_ras_capability(struct psp_context *psp); -int psp_config_sq_perfmon(struct psp_context *psp, uint32_t xcp_id, +int psp_config_sq_perfmon(struct psp_context *psp, uint32_t xcc_id, bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev); int amdgpu_psp_reg_program_no_ring(struct psp_context *psp, uint32_t val, diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h index 73f87131a7e9f..333d59f3eb119 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h +++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h @@ -359,7 +359,7 @@ struct psp_gfx_cmd_sriov_spatial_part { /*Structure for sq performance monitoring/profiling enable/disable*/ struct psp_gfx_cmd_config_sq_perfmon { - uint32_t gfx_xcp_mask; + uint32_t gfx_xcc_mask; uint8_t core_override; uint8_t reg_override; uint8_t perfmon_override; From 3c1dcf96fb760ca745cf7957cabf3cf42dfd7007 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 2 Oct 2024 10:08:39 -0400 Subject: [PATCH 1363/2653] drm/amdkfd: fix sq hang on gfx_v9_4_3 when running pc sampling host trap. -v2: use GET_INST and dev_dbg Signed-off-by: James Zhu Reviewed-by: Lijo Lazar Tested-by: Vladimir Indic --- .../drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 21 ++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 3 ++- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c index b9d226aa7b133..334ede86a48bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c @@ -520,6 +520,25 @@ static uint32_t kgd_gfx_v9_4_3_hqd_sdma_get_doorbell(struct amdgpu_device *adev, return is_active ? doorbell_off >> 2 : 0; } +void kgd_gfx_v9_4_3_override_core_cg(struct amdgpu_device *adev, + uint32_t value, + uint32_t inst) +{ + uint32_t sq_clk_ctrl; + + /* disable/enable SQ core override */ + amdgpu_amdkfd_config_sq_perfmon(adev, GET_INST(GC, inst), value, 0, 0); + + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + sq_clk_ctrl = RREG32_SOC15(GC, GET_INST(GC, inst), regCGTT_SQ_CLK_CTRL); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + mutex_unlock(&adev->grbm_idx_mutex); + + dev_dbg(adev->dev, "sq clock control on instance [%d]: 0x%x\n", + GET_INST(GC, inst), sq_clk_ctrl); +} + static uint32_t kgd_v9_4_3_trigger_pc_sample_trap(struct amdgpu_device *adev, uint32_t vmid, uint32_t *target_simd, @@ -568,5 +587,5 @@ const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .hqd_reset = kgd_gfx_v9_hqd_reset, .hqd_sdma_get_doorbell = kgd_gfx_v9_4_3_hqd_sdma_get_doorbell, .trigger_pc_sample_trap = kgd_v9_4_3_trigger_pc_sample_trap, - .override_core_cg = kgd_gfx_v9_override_core_cg + .override_core_cg = kgd_gfx_v9_4_3_override_core_cg }; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index c829676d631a6..603e557c986b4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -32,9 +32,10 @@ * * 0.1 - Initial revision * 0.2 - Support gfx9_4_3 Host Trap PC sampling + * 0.3 - Fix gfx9_4_3 SQ hang issue */ #define KFD_IOCTL_PCS_MAJOR_VERSION 0 -#define KFD_IOCTL_PCS_MINOR_VERSION 2 +#define KFD_IOCTL_PCS_MINOR_VERSION 3 struct supported_pc_sample_info { uint32_t ip_version; From 7d49a769e454fb4a5dbaf821bc12bfa0957e6e6b Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Fri, 15 Nov 2024 13:17:41 -0500 Subject: [PATCH 1364/2653] drm/amdgpu: Use SG helper for peer-direct sgtable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use SG helper functions to generate sgtable for peer-direct interface. This also improves performance since contiguous ranges are squashed into single scatterlist entry Suggested-by: Christian König Signed-off-by: Harish Kasiviswanathan Reviewed-by: Christian König --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 51 +++++-------------- 1 file changed, 13 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 1093bbd605868..dfe8bd126b64f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2519,13 +2519,11 @@ int amdgpu_amdkfd_gpuvm_get_sg_table(struct amdgpu_device *adev, struct sg_table **ret_sg) { struct sg_table *sg = NULL; - struct scatterlist *s; struct page **pages; uint64_t offset_in_page; unsigned int page_size; unsigned int cur_page; - unsigned int chunks; - unsigned int idx; + size_t max_segment = 0; int ret; /* Determine access does not cross memory boundary */ @@ -2555,52 +2553,29 @@ int amdgpu_amdkfd_gpuvm_get_sg_table(struct amdgpu_device *adev, /* Handle BO (type: ttm_bo_type_device) that is used to surface * memory resources from GPU's GART aperture. The allocation flag * of BO falls in GTT domain i.e. the physical backing memory is - * part of system memory. Construction of SG Table proceeds - * as follows: - * - * Allocate memory for SG Table - * Determine number of Scatterlist node in table - * Logic uses one Scatterlist node per PAGE_SIZE - * Allocate memory for Scatterlist nodes - * Initialize Scatterlist nodes to zero length - * Walk down system memory pointed by BO while - * Updating Scatterlist nodes with system memory info + * part of system memory */ sg = kmalloc(sizeof(*sg), GFP_KERNEL); - if (!sg) { - ret = -ENOMEM; - goto out; - } + if (!sg) + return -ENOMEM; page_size = PAGE_SIZE; offset_in_page = offset & (page_size - 1); - chunks = (size + offset_in_page + page_size - 1) - / page_size; - - ret = sg_alloc_table(sg, chunks, GFP_KERNEL); - if (unlikely(ret)) - goto out; - - for_each_sgtable_sg(sg, s, idx) - s->length = 0; pages = bo->tbo.ttm->pages; cur_page = offset / page_size; - for_each_sg(sg->sgl, s, sg->orig_nents, idx) { - uint64_t chunk_size, length; - - chunk_size = page_size - offset_in_page; - length = min(size, chunk_size); - sg_set_page(s, pages[cur_page], length, offset_in_page); - s->dma_address = page_to_phys(pages[cur_page]); - s->dma_length = length; + max_segment = dma_max_mapping_size(dma_dev); + if (!max_segment) + max_segment = UINT_MAX; - size -= length; - offset_in_page = 0; - cur_page++; - } + ret = sg_alloc_table_from_pages_segment(sg, &pages[cur_page], + bo->tbo.ttm->num_pages - cur_page, + offset_in_page, size, max_segment, + GFP_KERNEL); + if (ret) + goto out; if (dma_dev) { ret = dma_map_sgtable(dma_dev, sg, dir, DMA_ATTR_SKIP_CPU_SYNC); From 718f22d23f86dc728bdc048ac2fe0a4bd9f09334 Mon Sep 17 00:00:00 2001 From: chengjya Date: Wed, 20 Nov 2024 13:57:58 +0800 Subject: [PATCH 1365/2653] drm/amdkcl:test whether sg_alloc_table_from_pages_segment() is available It's caused by follow commit:166ea4a47bdfec1a789c98a6a5bab70274d58502 "drm/amdgpu: Use SG helper for peer-direct sgtable" Signed-off-by: chengjya --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 ++- drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c | 19 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../m4/sg_alloc_table_from_pages_segment.m4 | 17 +++++++++++++++++ include/kcl/kcl_scatterlist.h | 15 +++++++++++++++ 7 files changed, 58 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 create mode 100644 include/kcl/kcl_scatterlist.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 41b8e669c70cd..adea9fa2bbdda 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -15,7 +15,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o \ - kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o + kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ + kcl_scatterlist.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c b/drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c new file mode 100644 index 0000000000000..44a6951e306e8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2007 Jens Axboe + * + * Scatterlist handling helpers. + */ +#include + +#ifndef HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT +int _kcl_sg_alloc_table_from_pages_segment(struct sg_table *sgt, struct page **pages, + unsigned int n_pages, unsigned int offset, + unsigned long size, unsigned int max_segment, + gfp_t gfp_mask) +{ + return PTR_ERR_OR_ZERO(__sg_alloc_table_from_pages(sgt, pages, n_pages, + offset, size, max_segment, gfp_mask)); +} +EXPORT_SYMBOL(_kcl_sg_alloc_table_from_pages_segment); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 51dbf731d54aa..cc4624136cad1 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -135,4 +135,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 498186ee43d05..f260ad8192ba7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1005,6 +1005,9 @@ /* whether smca_get_bank_type(x, x) is available */ #define HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS 1 +/* whether sg_alloc_table_from_pages_segment() is available */ +#define HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT 1 + /* enum SMCA_UMC_V2 is available */ #define HAVE_SMCA_UMC_V2 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e8391867adf60..afba45e6ac52d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -256,6 +256,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE AC_AMDGPU_DRM_CLIENT AC_AMDGPU_DRM_SYNCOBJ_ADD_POINT + AC_AMDGPU_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 b/drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 new file mode 100644 index 0000000000000..e2c706d06e921 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 90e7a6de62781c27d6a111fccfb19b807f9b6887 +dnl # v5.14-rc6-1-g90e7a6de6278 +dnl # lib/scatterlist: Provide a dedicated function to support table append +dnl # +AC_DEFUN([AC_AMDGPU_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + sg_alloc_table_from_pages_segment(NULL,NULL,0,0,0,0,GFP_KERNEL); + ], [sg_alloc_table_from_pages_segment],[lib/scatterlist.c], [ + AC_DEFINE(HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT, 1, + [sg_alloc_table_from_pages_segment() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_scatterlist.h b/include/kcl/kcl_scatterlist.h new file mode 100644 index 0000000000000..d73af56137c72 --- /dev/null +++ b/include/kcl/kcl_scatterlist.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_LINUX_SCATTERLIST_H +#define _KCL_LINUX_SCATTERLIST_H + +#include + +#ifndef HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT +int _kcl_sg_alloc_table_from_pages_segment(struct sg_table *sgt, struct page **pages, + unsigned int n_pages, unsigned int offset, + unsigned long size, + unsigned int max_segment, gfp_t gfp_mask); +#define sg_alloc_table_from_pages_segment _kcl_sg_alloc_table_from_pages_segment +#endif + +#endif /* _LINUX_SCATTERLIST_H */ From 345d938add301380b71985fc4d81a09a399b538d Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 26 Nov 2024 10:20:56 +0800 Subject: [PATCH 1366/2653] drm/amdkcl: use the amdkcl_ttm_resvp to get resv It's caused by the commit:9d3d50f "drm/amdgpu: add gfx eviction fence helpers" commit:64b20409 "drm/amdgpu: resume gfx userqueues" v6.14-rc4-390-gf3bcfd04a52f drm/ttm: Add a macro to perform LRU iteration v6.14-rc1-243-gcb0de06d1b0a drm/amdgpu: remove all KFD fences from the BO on release Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c | 4 ++-- drivers/gpu/drm/ttm/ttm_bo_util.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index dfe8bd126b64f..093d83b47362c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -383,7 +383,7 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo, */ void amdgpu_amdkfd_remove_all_eviction_fences(struct amdgpu_bo *bo) { - struct dma_resv *resv = &bo->tbo.base._resv; + struct dma_resv *resv = &amdkcl_ttm_resv(&bo->tbo); struct dma_fence *fence, *stub; struct dma_resv_iter cursor; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c index 23d7d0b0d6252..aed29e3c0c4d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c @@ -198,7 +198,7 @@ int amdgpu_eviction_fence_attach(struct amdgpu_eviction_fence_mgr *evf_mgr, struct amdgpu_bo *bo) { struct amdgpu_eviction_fence *ev_fence; - struct dma_resv *resv = bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&bo->tbo); int ret; if (!resv) @@ -224,7 +224,7 @@ void amdgpu_eviction_fence_detach(struct amdgpu_eviction_fence_mgr *evf_mgr, { struct dma_fence *stub = dma_fence_get_stub(); - dma_resv_replace_fences(bo->tbo.base.resv, evf_mgr->ev_fence_ctx, + dma_resv_replace_fences(amdkcl_ttm_resvp(&bo->tbo), evf_mgr->ev_fence_ctx, stub, DMA_RESV_USAGE_BOOKKEEP); dma_fence_put(stub); } diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 0b51db4b1dc12..ccad3f82a2ec6 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -928,7 +928,7 @@ static void ttm_bo_lru_cursor_cleanup_bo(struct ttm_bo_lru_cursor *curs) if (bo) { if (curs->needs_unlock) - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); ttm_bo_put(bo); curs->bo = NULL; } @@ -1152,7 +1152,7 @@ bool ttm_bo_shrink_suitable(struct ttm_buffer_object *bo, struct ttm_operation_c { return bo->ttm && ttm_tt_is_populated(bo->ttm) && !bo->pin_count && (!ctx->no_wait_gpu || - dma_resv_test_signaled(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP)); + dma_resv_test_signaled(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP)); } EXPORT_SYMBOL(ttm_bo_shrink_suitable); From 422bc4674deb1fc4ec371f0e8e788cb8d1172736 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 26 Nov 2024 12:13:49 +0800 Subject: [PATCH 1367/2653] drm/amdkcl: Add 'static' to function to avoid Intree build compilation failure In the process of the Intree build, when the GCC compiler is invoked with the -Werror=missing-prototypes flag, the compilation was failing due to kgd_gfx_v9_4_3_override_core_cg() lacking a prior prototype declaration. Add 'static' ensures that during Intree build, the compilation can proceed smoothly without being halted by the missing prototype error. Signed-off-by: chengjya Reviewed-by: Bob Zhou Reviewed-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c index 334ede86a48bc..c1c184babcaf3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c @@ -520,7 +520,7 @@ static uint32_t kgd_gfx_v9_4_3_hqd_sdma_get_doorbell(struct amdgpu_device *adev, return is_active ? doorbell_off >> 2 : 0; } -void kgd_gfx_v9_4_3_override_core_cg(struct amdgpu_device *adev, +static void kgd_gfx_v9_4_3_override_core_cg(struct amdgpu_device *adev, uint32_t value, uint32_t inst) { From 2b12f0fbf16b672d465bd7eca260c85b7e336595 Mon Sep 17 00:00:00 2001 From: chengjya Date: Wed, 27 Nov 2024 10:06:00 +0800 Subject: [PATCH 1368/2653] drm/amdkcl: Move _kcl_drm_dp_mst_topology_queue_probe() declaration to proper header file Signed-off-by: chengjya Reviewed-by: Bob Zhou --- .../drm/amd/amdkcl/kcl_drm_dp_mst_topology.c | 4 +-- drivers/gpu/drm/amd/backport/backport.h | 1 + .../backport/kcl_drm_dp_mst_helper_backport.h | 5 --- include/kcl/kcl_drm_dp_mst_helper.h | 32 +++++++++++++++++++ 4 files changed, 35 insertions(+), 7 deletions(-) create mode 100644 include/kcl/kcl_drm_dp_mst_helper.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c index d6b4e9d0f77be..8b3f68cacab77 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c @@ -20,7 +20,7 @@ * OF THIS SOFTWARE. */ -#include +#include #include #ifndef HAVE_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE @@ -54,7 +54,7 @@ _kcl_drm_dp_mst_topology_mgr_invalidate_mstb(struct drm_dp_mst_branch *mstb) * cases - for instance when a sink gets plugged/unplugged to a port - the SW * state will get updated automatically via MST UP message notifications. */ -void drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr) +void _kcl_drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr) { mutex_lock(&mgr->lock); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index cc4624136cad1..0c78aacba53b5 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -136,4 +136,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index a6e237c081029..a84cd2ac22cc2 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -117,9 +117,4 @@ _kcl_drm_dp_add_payload_part2(struct drm_dp_mst_topology_mgr *mgr, #define drm_dp_add_payload_part2 _kcl_drm_dp_add_payload_part2 #endif -#ifndef HAVE_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE -void _kcl_drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr); -#define drm_dp_mst_topology_queue_probe _kcl_drm_dp_mst_topology_queue_probe -#endif - #endif diff --git a/include/kcl/kcl_drm_dp_mst_helper.h b/include/kcl/kcl_drm_dp_mst_helper.h new file mode 100644 index 0000000000000..69bb114300b58 --- /dev/null +++ b/include/kcl/kcl_drm_dp_mst_helper.h @@ -0,0 +1,32 @@ +/* + * Copyright © 2014 Red Hat. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ +#ifndef _KCL_DRM_DP_MST_HELPER_H_ +#define _KCL_DRM_DP_MST_HELPER_H_ + +#include + +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE +void _kcl_drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr); +#define drm_dp_mst_topology_queue_probe _kcl_drm_dp_mst_topology_queue_probe +#endif + +#endif From 50d8add01945fded357212eac698d8b430fc2733 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 28 Nov 2024 16:39:40 +0800 Subject: [PATCH 1369/2653] drm/amdkcl: wrap slab.h under HAVE_DMA_FENCE_CHAIN_ALLOC The dma_fence_chain_alloc includes kmalloc() and kfree(). the slab.h need the same mecro judge condition, so fix it. Signed-off-by: Bob Zhou Reviewed-by: chengjya --- include/kcl/kcl_dma_fence_chain.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/kcl/kcl_dma_fence_chain.h b/include/kcl/kcl_dma_fence_chain.h index 97900481479c5..57324eeca102e 100644 --- a/include/kcl/kcl_dma_fence_chain.h +++ b/include/kcl/kcl_dma_fence_chain.h @@ -13,10 +13,13 @@ #include #endif +#if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) || !defined(HAVE_DMA_FENCE_CHAIN_ALLOC) +#include +#endif + #if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) #include #include -#include /** * struct dma_fence_chain - fence to represent an node of a fence chain From 3a51b1415dd9163250d5b79077b1074e5580405e Mon Sep 17 00:00:00 2001 From: chengjya Date: Thu, 28 Nov 2024 17:32:37 +0800 Subject: [PATCH 1370/2653] drm/amdkcl: test __sg_alloc_table_from_pages() has 9 args It's caused by follow commit:166ea4a47bdfec1a789c98a6a5bab70274d58502 "drm/amdgpu: Use SG helper for peer-direct sgtable" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c | 8 +++++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../dkms/m4/sg_alloc_table_from_pages_segment.m4 | 14 ++++++++++++++ 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c b/drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c index 44a6951e306e8..bfa5ed0e16feb 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c @@ -12,8 +12,14 @@ int _kcl_sg_alloc_table_from_pages_segment(struct sg_table *sgt, struct page **p unsigned long size, unsigned int max_segment, gfp_t gfp_mask) { +#ifdef HAVE___SG_ALLOC_TABLE_FROM_PAGES_9ARGS return PTR_ERR_OR_ZERO(__sg_alloc_table_from_pages(sgt, pages, n_pages, - offset, size, max_segment, gfp_mask)); + offset, size, max_segment, + NULL, 0, gfp_mask)); +#else + return __sg_alloc_table_from_pages(sgt, pages, n_pages, offset, size, + max_segment, gfp_mask); +#endif } EXPORT_SYMBOL(_kcl_sg_alloc_table_from_pages_segment); #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f260ad8192ba7..643fefddf5166 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1147,6 +1147,9 @@ /* __kthread_should_park() is available */ /* #undef HAVE___KTHREAD_SHOULD_PARK */ +/* __sg_alloc_table_from_pages() has 9 args */ +/* #undef HAVE___SG_ALLOC_TABLE_FROM_PAGES_9ARGS */ + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" diff --git a/drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 b/drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 index e2c706d06e921..474a1baed1064 100644 --- a/drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 @@ -12,6 +12,20 @@ AC_DEFUN([AC_AMDGPU_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT], [ ], [sg_alloc_table_from_pages_segment],[lib/scatterlist.c], [ AC_DEFINE(HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT, 1, [sg_alloc_table_from_pages_segment() is available]) + ],[ + dnl # + dnl # commit 07da1223ec939982497db3caccd6215b55acc35c + dnl # v5.9-rc8-3-g07da1223ec93 + dnl # lib/scatterlist: Add support in dynamic allocation of SG table from pages + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + __sg_alloc_table_from_pages(NULL,NULL,0,0,0,0,NULL,0,GFP_KERNEL); + ], [__sg_alloc_table_from_pages],[lib/scatterlist.c], [ + AC_DEFINE(HAVE___SG_ALLOC_TABLE_FROM_PAGES_9ARGS, 1, + [__sg_alloc_table_from_pages() has 9 args]) + ]) ]) ]) ]) From 4bfc59c10d5b3961f4987556e618bf5b084e2062 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 3 Dec 2024 10:18:23 +0800 Subject: [PATCH 1371/2653] drm/amdkcl: wrap code under DEFINE_DEBUGFS_ATTRIBUTE It's caused by following commit: d1dfdec7 "drm/amdgpu: Add amdgpu_vcn_sched_mask debugfs" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index d799bc74936c0..d3ed944749f00 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -1409,10 +1409,15 @@ static int amdgpu_debugfs_vcn_sched_mask_get(void *data, u64 *val) *val = mask; return 0; } - +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_vcn_sched_mask_fops, amdgpu_debugfs_vcn_sched_mask_get, amdgpu_debugfs_vcn_sched_mask_set, "%llx\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_vcn_sched_mask_fops, + amdgpu_debugfs_vcn_sched_mask_get, + amdgpu_debugfs_vcn_sched_mask_set, "%llx\n"); +#endif #endif void amdgpu_debugfs_vcn_sched_mask_init(struct amdgpu_device *adev) From e72afc290307db020cf251f0a3c2e50a9db1fd03 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 3 Dec 2024 16:40:22 +0800 Subject: [PATCH 1372/2653] drm/amdkcl: relax unused-variable error for conftest Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index afba45e6ac52d..1080a8d1c756b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -473,7 +473,7 @@ AC_DEFUN([AC_KERNEL_COMPILE_MODULE_IFELSE], [ test "x$enable_linux_builtin" = xyes && kbuild_src_flag='KBUILD_SRC=' # override KBUILD_SRC test "x$enable_linux_builtin" = xyes && kbuild_workaround_flag='sub_make_done=' # override sub_make_done AS_IF( - [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag $kbuild_cc) >/dev/null && AC_TRY_COMMAND([$3])], + [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=unused-variable -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag $kbuild_cc) >/dev/null && AC_TRY_COMMAND([$3])], [$4], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] ) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index 91b36b22a7824..f8f51b0d19c7a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -13,6 +13,7 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ -e "s|-I\([[[a-z]]]*\)|-I${LINUX_OBJ}/\1|g" \ -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|g" \ -e "s|$PWD|\${PWD}|g") + CFLAGS=$(echo $CFLAGS | sed -E 's/-W(array-bounds|error=array-bounds|unused-variable|error=unused-variable|unused-.*-variable|error=unused-.*-variable)( |$)//g') CPPFLAGS=$(echo $CFLAGS | \ cut -d ';' -f 1 | \ From d237da6372419b3cfe51132e158a4756172aada1 Mon Sep 17 00:00:00 2001 From: chengjya Date: Wed, 4 Dec 2024 14:33:30 +0800 Subject: [PATCH 1373/2653] drm/amdkcl: test whether firmware_request_nowarn() is available It's caused by the following commit: 227d04b7 "drm/amd: Add the capability to mark certain firmware as "required"" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/firmware_request_nowarn.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_firmware.h | 11 +++++++++++ 5 files changed, 32 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/firmware_request_nowarn.m4 create mode 100644 include/kcl/kcl_firmware.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 0c78aacba53b5..d58fb8b5ea7a0 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -137,4 +137,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 643fefddf5166..dcaddb9ff9924 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -660,6 +660,9 @@ /* file_operation->fop_flags is available */ #define HAVE_FILE_OPERATION_FOP_FLAGS 1 +/* firmware_request_nowarn() is available */ +#define HAVE_FIRMWARE_REQUEST_NOWARN 1 + /* follow_pfn() is available */ /* #undef HAVE_FOLLOW_PFN */ diff --git a/drivers/gpu/drm/amd/dkms/m4/firmware_request_nowarn.m4 b/drivers/gpu/drm/amd/dkms/m4/firmware_request_nowarn.m4 new file mode 100644 index 0000000000000..48007b87ed9bf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/firmware_request_nowarn.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v4.17-rc3-12-g7dcc01343e48 +dnl # firmware: add firmware_request_nowarn() - load firmware without warnings +dnl # +AC_DEFUN([AC_AMDGPU_FIRMWARE_REQUEST_NOWARN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + firmware_request_nowarn(NULL, NULL, NULL); + ],[firmware_request_nowarn], [drivers/base/firmware_loader/main.c],[ + AC_DEFINE(HAVE_FIRMWARE_REQUEST_NOWARN, 1, + [firmware_request_nowarn() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1080a8d1c756b..5d724d7514674 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -257,6 +257,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CLIENT AC_AMDGPU_DRM_SYNCOBJ_ADD_POINT AC_AMDGPU_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT + AC_AMDGPU_FIRMWARE_REQUEST_NOWARN AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_firmware.h b/include/kcl/kcl_firmware.h new file mode 100644 index 0000000000000..45f145d35166b --- /dev/null +++ b/include/kcl/kcl_firmware.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_FIRMWARE_H +#define _KCL_FIRMWARE_H + +#include + +#ifndef HAVE_FIRMWARE_REQUEST_NOWARN +#define firmware_request_nowarn request_firmware +#endif + +#endif From 2bf2f17bd1af15e861067405bbe9765eb0182cbe Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 31 Oct 2024 16:22:53 -0400 Subject: [PATCH 1374/2653] drm/amdkcl: correct m4 file name Drop an extra space in the file name Change-Id: Ie876c8bc318eadd3cc94473458a3426cfb0c5522 Signed-off-by: Slava Grigorev --- .../m4/{drm_vblank_crtc_config .m4 => drm_vblank_crtc_config.m4} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename drivers/gpu/drm/amd/dkms/m4/{drm_vblank_crtc_config .m4 => drm_vblank_crtc_config.m4} (100%) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config .m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config.m4 similarity index 100% rename from drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config .m4 rename to drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config.m4 From 38449dcc113e3dbb82f89b81322066f7bc0bff07 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 4 Dec 2024 10:01:54 -0500 Subject: [PATCH 1375/2653] drm/kfd: copy back total spm data to user space copy back total spm data to user space. Signed-off-by: James Zhu Reviewed-by: Bing Ma Tested-by: Bing Ma --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index fdf508e5e89c2..8fd21ad6ee1fa 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -470,7 +470,8 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device } static int spm_update_dest_info(struct kfd_process_device *pdd, - int inst, struct kfd_ioctl_spm_args *user_spm_data) + int inst, struct kfd_ioctl_spm_args *user_spm_data, + struct kfd_ioctl_spm_args *user_spm_ptr) { struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); int ret = 0; @@ -480,8 +481,8 @@ static int spm_update_dest_info(struct kfd_process_device *pdd, struct kfd_ioctl_spm_buffer_header spm_header; uint64_t __user *user_address; - user_spm_data->bytes_copied += spm->size_copied; - user_spm_data->has_data_loss += spm->has_data_loss; + user_spm_ptr->bytes_copied += spm->size_copied; + user_spm_ptr->has_data_loss += spm->has_data_loss; memset(&spm_header, 0, sizeof(spm_header)); user_address = (uint64_t *)((uint64_t)spm->ubuf.user_addr - sizeof(spm_header)); @@ -499,9 +500,6 @@ static int spm_update_dest_info(struct kfd_process_device *pdd, } } if (user_spm_data->dest_buf) { - user_spm_data->bytes_copied = 0; - user_spm_data->has_data_loss = 0; - spm->ubuf.user_addr = (uint64_t *)user_spm_data->dest_buf; spm->ubuf.ubufsize = user_spm_data->buf_size; /* reserve space for kfd_ioctl_spm_buffer_header */ @@ -585,6 +583,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev memcpy(&user_spm_data, user_spm_ptr, sizeof(user_spm_data)); user_spm_data.buf_size = ubufsize; + if (user_spm_data.timeout && spm_cntr->have_users_buf_cnt && !READ_ONCE(spm_cntr->are_users_buf_filled)) { dev_dbg(pdd->dev->adev->dev, "SPM waiting for fill awake, timeout = %d ms.", @@ -606,6 +605,8 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev flush_work(&pdd->spm_work); } + user_spm_ptr->bytes_copied = 0; + user_spm_ptr->has_data_loss = 0; for_each_inst(inst, pdd->dev->xcc_mask) { struct kfd_spm_base *spm = &(spm_cntr->spm[inst]); @@ -613,7 +614,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev /* Get info about filled space in previous output buffer. * Setup new dest buf if provided. */ - ret = spm_update_dest_info(pdd, inst, &user_spm_data); + ret = spm_update_dest_info(pdd, inst, &user_spm_data, user_spm_ptr); if (ret) goto out; } From b53e4d123b67077aa6cd477b57e4864b71d134a1 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 17 Dec 2024 16:02:26 +0800 Subject: [PATCH 1376/2653] drm/amdkcl: fake the drm/drm_panic.h header It's caused by the following commits: 89e8d6fa("drm/amdgpu: add generic display panic helper code") Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ include/kcl/header/drm/drm_panic.h | 9 +++++++++ 3 files changed, 18 insertions(+) create mode 100644 include/kcl/header/drm/drm_panic.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index dcaddb9ff9924..31a21b87a25c9 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -486,6 +486,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_MANAGED_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_PANIC_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index ad0408625c199..81510494154aa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -111,6 +111,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_eld.h]) + dnl # + dnl # v6.9-rc2-212-ge2a1cda3e0c7 + dnl # drm/panic: Add drm panic locking + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_panic.h]) + dnl # dnl # v6.9-rc6-1436-gaae4682e5d66 dnl # drm/fbdev-generic: Convert to fbdev-ttm diff --git a/include/kcl/header/drm/drm_panic.h b/include/kcl/header/drm/drm_panic.h new file mode 100644 index 0000000000000..c64b615518416 --- /dev/null +++ b/include/kcl/header/drm/drm_panic.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_PANIC_H_H_ +#define _KCL_HEADER_DRM_PANIC_H_H_ + +#ifdef HAVE_DRM_DRM_PANIC_H +#include_next +#endif + +#endif From 054480dae5d5d0941e255ee9256fc62543390a5f Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 13 Dec 2024 11:25:39 +0800 Subject: [PATCH 1377/2653] drm/amdkcl: test struct drm_plane_helper_funcs->get_scanout_buffer() is available It's caused by the following commits: 89e8d6fa("drm/amdgpu: add generic display panic helper code") 3feb9568("drm/amd/display: add DC drm_panic support") 7d862fb7("drm/amd/display: add non-DC drm_panic support") Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 2 ++ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 ++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../dkms/m4/struct_drm_plane_helper_funcs.m4 | 20 +++++++++++++++++++ 9 files changed, 47 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index b43beaa406f82..2141622cb60f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1858,6 +1858,7 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev) */ static struct amdgpu_bo *panic_abo; +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER /* Use the indirect MMIO to write each pixel to the GPU VRAM, * This is a simplified version of amdgpu_device_mm_access() */ @@ -1932,3 +1933,4 @@ int amdgpu_display_get_scanout_buffer(struct drm_plane *plane, return 0; } +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h index dfa0d642ac161..4eaee10a1b7c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h @@ -51,7 +51,9 @@ amdgpu_lookup_format_info(u32 format, uint64_t modifier); int amdgpu_display_suspend_helper(struct amdgpu_device *adev); int amdgpu_display_resume_helper(struct amdgpu_device *adev); +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER int amdgpu_display_get_scanout_buffer(struct drm_plane *plane, struct drm_scanout_buffer *sb); +#endif #endif diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 8a9f84d22b57c..5257968894ad0 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2697,6 +2697,7 @@ static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = { #endif }; +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER static void dce_v10_0_panic_flush(struct drm_plane *plane) { struct drm_framebuffer *fb; @@ -2722,6 +2723,7 @@ static const struct drm_plane_helper_funcs dce_v10_0_drm_primary_plane_helper_fu .get_scanout_buffer = amdgpu_display_get_scanout_buffer, .panic_flush = dce_v10_0_panic_flush, }; +#endif static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) { @@ -2770,7 +2772,9 @@ static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) amdgpu_crtc->encoder = NULL; amdgpu_crtc->connector = NULL; drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs); +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v10_0_drm_primary_plane_helper_funcs); +#endif return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 84fa0f8902dc4..a3236cb8691b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2810,6 +2810,7 @@ static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = { #endif }; +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER static void dce_v11_0_panic_flush(struct drm_plane *plane) { struct drm_framebuffer *fb; @@ -2835,6 +2836,7 @@ static const struct drm_plane_helper_funcs dce_v11_0_drm_primary_plane_helper_fu .get_scanout_buffer = amdgpu_display_get_scanout_buffer, .panic_flush = dce_v11_0_panic_flush, }; +#endif static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) { @@ -2883,7 +2885,9 @@ static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) amdgpu_crtc->encoder = NULL; amdgpu_crtc->connector = NULL; drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v11_0_drm_primary_plane_helper_funcs); +#endif return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index c2ac8ef3b15cd..cc37c620ea074 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2664,6 +2664,7 @@ static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = { #endif }; +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER static void dce_v6_0_panic_flush(struct drm_plane *plane) { struct drm_framebuffer *fb; @@ -2689,6 +2690,7 @@ static const struct drm_plane_helper_funcs dce_v6_0_drm_primary_plane_helper_fun .get_scanout_buffer = amdgpu_display_get_scanout_buffer, .panic_flush = dce_v6_0_panic_flush, }; +#endif static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) { @@ -2717,7 +2719,9 @@ static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) amdgpu_crtc->encoder = NULL; amdgpu_crtc->connector = NULL; drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v6_0_drm_primary_plane_helper_funcs); +#endif return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 3364aa98e33bb..bd986a71868e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2622,6 +2622,7 @@ static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = { #endif }; +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER static void dce_v8_0_panic_flush(struct drm_plane *plane) { struct drm_framebuffer *fb; @@ -2646,6 +2647,7 @@ static const struct drm_plane_helper_funcs dce_v8_0_drm_primary_plane_helper_fun .get_scanout_buffer = amdgpu_display_get_scanout_buffer, .panic_flush = dce_v8_0_panic_flush, }; +#endif static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index) { @@ -2674,7 +2676,9 @@ static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index) amdgpu_crtc->encoder = NULL; amdgpu_crtc->connector = NULL; drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs); +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v8_0_drm_primary_plane_helper_funcs); +#endif return 0; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index e3b8c75f12216..bfcb1a9a82db1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1466,6 +1466,7 @@ static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane, amdgpu_dm_plane_handle_cursor_update(plane, old_state); } +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER static void amdgpu_dm_plane_panic_flush(struct drm_plane *plane) { struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane->state); @@ -1479,6 +1480,7 @@ static void amdgpu_dm_plane_panic_flush(struct drm_plane *plane) dc_plane_force_dcc_and_tiling_disable(dc_plane_state, fb->modifier ? true : false); } +#endif static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { .prepare_fb = amdgpu_dm_plane_helper_prepare_fb, @@ -1494,8 +1496,10 @@ static const struct drm_plane_helper_funcs dm_primary_plane_helper_funcs = { .atomic_check = amdgpu_dm_plane_atomic_check, .atomic_async_check = amdgpu_dm_plane_atomic_async_check, .atomic_async_update = amdgpu_dm_plane_atomic_async_update, +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER .get_scanout_buffer = amdgpu_display_get_scanout_buffer, .panic_flush = amdgpu_dm_plane_panic_flush, +#endif }; static void amdgpu_dm_plane_drm_plane_reset(struct drm_plane *plane) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 31a21b87a25c9..c2d82c62e52e1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1051,6 +1051,9 @@ arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 +/* struct drm_plane_helper_funcs->get_scanout_buffer is available */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER 1 + /* ide->idr_base is available */ #define HAVE_STRUCT_IDE_IDR_BASE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 index 495dd9ef97c12..fce9bda9696c0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 @@ -14,6 +14,26 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_ ]) ]) +dnl # +dnl # v6.9-rc2-213-gbf9fb17c6672 +dnl # drm/panic: Add a drm panic handler +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_plane_helper_funcs *ptr = NULL; + ptr->get_scanout_buffer(NULL, NULL); + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER, 1, + [struct drm_plane_helper_funcs->get_scanout_buffer is available]) + ]) + ]) +]) + + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS], [ AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER ]) From 9ef28a70c81831ad3d645958079f17aea0b10132 Mon Sep 17 00:00:00 2001 From: Benjamin Welton Date: Wed, 9 Oct 2024 21:32:55 -0700 Subject: [PATCH 1378/2653] Add kfd_ioctl_profiler to contain profiler kernel driver changes kfd_ioctl_profiler takes a similar approach to that of kfd_ioctl_dbg_trap (which contains debugger related IOCTL services) where kfd_ioctl_profiler will contain all profiler related IOCTL services. The IOCTL is designed to be expanded as needed to support additional profiler functionality. The current functionality of the IOCTL is to allow for profilers which need PMC counters from GPU devices to both signal to other profilers that may be on the system that the device has active PMC profiling taking place on it (multiple PMC profilers on the same device can result in corrupted counter data) and to setup the device to allow for the collection of SQ PMC data on all queues on the device. For PMC data for the SQ block (such as SQ_WAVES) to be available to a profiler, mmPERFCOUNT_ENABLE must be set on the queues. When profiling a single process, the profiler can inject PM4 packets into each queue to turn on PERFCOUNT_ENABLE. When profiling system wide, the profiler does not have this option and must have a way to turn on profiling for queues in which it cannot inject packets into directly. Accomplishing this requires a few steps: 1. Checking if the user has the necessary permissions to profile system wide on the device. This check uses the same check that linux perf uses to determine if a user has the necessary permissions to profile at this scope (primarily if the process has CAP_SYS_PERFMON or is root). 2. Locking the device for profiling. This is done by setting a lock bit on the device struct and storing the process that locked the device. 3. Iterating all queues on the device and issuing an MQD Update to enable perfcounting on the queues. 4. Actions to cleanup if the process exits or releases the lock. The IOCTL also contains a link to the existing PC Sampling IOCTL as well. This is per a suggestion that we should potentially remove the PC Sampling IOCTL to have it be a part of the profiler IOCTL. This is a future change. In addition, we do expect to expand the profiler IOCTL to include additional profiler functionality in the future (which necessitates the use of a version number). Signed-off-by: Benjamin Welton Acked-by: Kent Russell --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 84 +++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 + .../drm/amd/amdkfd/kfd_device_queue_manager.c | 25 ++++++ .../drm/amd/amdkfd/kfd_device_queue_manager.h | 2 + .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 16 +++- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 14 +++- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 8 +- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 15 +++- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 11 +++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 7 ++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 11 +++ include/uapi/linux/kfd_ioctl.h | 30 ++++++- 12 files changed, 218 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 7b2402dc318fa..a68ff45dfcd21 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -21,6 +21,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include #include #include #include @@ -3366,6 +3367,86 @@ static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, v return r; } +static inline uint32_t profile_lock_device(struct kfd_process *p, + uint32_t gpu_id, uint32_t op) +{ + struct kfd_process_device *pdd; + struct kfd_dev *kfd; + int status = -EINVAL; + + if (!p) + return -EINVAL; + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, gpu_id); + mutex_unlock(&p->mutex); + + if (!pdd || !pdd->dev || !pdd->dev->kfd) + return -EINVAL; + + kfd = pdd->dev->kfd; + + mutex_lock(&kfd->profiler_lock); + if (op == 1) { + if (!kfd->profiler_process) { + kfd->profiler_process = p; + status = 0; + } else if (kfd->profiler_process == p) { + status = -EALREADY; + } else { + status = -EBUSY; + } + } else if (op == 0 && kfd->profiler_process == p) { + kfd->profiler_process = NULL; + status = 0; + } + mutex_unlock(&kfd->profiler_lock); + + return status; +} + +static inline int kfd_profiler_pmc(struct kfd_process *p, + struct kfd_ioctl_pmc_settings *args) +{ + struct kfd_process_device *pdd; + struct device_queue_manager *dqm; + int status; + + /* Check if we have the correct permissions. */ + if (!perfmon_capable()) + return -EPERM; + + /* Lock/Unlock the device based on the parameter given in OP */ + status = profile_lock_device(p, args->gpu_id, args->lock); + if (status != 0) + return status; + + /* Enable/disable perfcount if requested */ + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + dqm = pdd->dev->dqm; + mutex_unlock(&p->mutex); + + dqm->ops.set_perfcount(dqm, args->perfcount_enable); + return status; +} + +static int kfd_ioctl_profiler(struct file *filep, struct kfd_process *p, void *data) +{ + struct kfd_ioctl_profiler_args *args = data; + + switch (args->op) { + case KFD_IOC_PROFILER_VERSION: + args->version = KFD_IOC_PROFILER_VERSION_NUM; + return 0; + case KFD_IOC_PROFILER_PC_SAMPLE: + return kfd_ioctl_pc_sample(filep, p, &args->pc_sample); + case KFD_IOC_PROFILER_PMC: + return kfd_profiler_pmc(p, &args->pmc); + } + return -EINVAL; +} + #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ .cmd_drv = 0, .name = #ioctl} @@ -3503,6 +3584,9 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { /* TODO: KFD_IOC_FLAG_PERFMON is not required for host-trap, disable first */ AMDKFD_IOCTL_DEF(AMDKFD_IOC_PC_SAMPLE, kfd_ioctl_pc_sample, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_PROFILER, + kfd_ioctl_profiler, 0), }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index d27e8bf3448e4..a26588ee9b6ec 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -945,6 +945,9 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, svm_range_set_max_pages(kfd->adev); + kfd->profiler_process = NULL; + mutex_init(&kfd->profiler_lock); + kfd->init_complete = true; dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, kfd->adev->pdev->device); @@ -980,6 +983,7 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd) ida_destroy(&kfd->doorbell_ida); kfd_gtt_sa_fini(kfd); amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); + mutex_destroy(&kfd->profiler_lock); } kfree(kfd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 488c8d81786f3..928bc08744877 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -326,6 +326,29 @@ static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, return r; } +static void set_perfcount(struct device_queue_manager *dqm, int enable) +{ + struct device_process_node *cur; + struct qcm_process_device *qpd; + struct queue *q; + struct mqd_update_info minfo = { 0 }; + + if (!dqm) + return; + + minfo.update_flag = (enable == 1 ? UPDATE_FLAG_PERFCOUNT_ENABLE : + UPDATE_FLAG_PERFCOUNT_DISABLE); + dqm_lock(dqm); + list_for_each_entry(cur, &dqm->queues, list) { + qpd = cur->qpd; + list_for_each_entry(q, &qpd->queues_list, list) { + pqm_update_mqd(qpd->pqm, q->properties.queue_id, + &minfo); + } + } + dqm_unlock(dqm); +} + static int remove_all_kfd_queues_mes(struct device_queue_manager *dqm) { struct device_process_node *cur; @@ -2979,6 +3002,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) dqm->ops.reset_queues = reset_queues_cpsch; dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; dqm->ops.checkpoint_mqd = checkpoint_mqd; + dqm->ops.set_perfcount = set_perfcount; break; case KFD_SCHED_POLICY_NO_HWS: /* initialize dqm for no cp scheduling */ @@ -2999,6 +3023,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) dqm->ops.get_wave_state = get_wave_state; dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; dqm->ops.checkpoint_mqd = checkpoint_mqd; + dqm->ops.set_perfcount = set_perfcount; break; default: dev_err(dev->adev->dev, "Invalid scheduling policy %d\n", dqm->sched_policy); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index f276024ff2337..47d06a89d0edb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -200,6 +200,8 @@ struct device_queue_manager_ops { const struct queue *q, void *mqd, void *ctl_stack); + void (*set_perfcount)(struct device_queue_manager *dqm, + int enable); }; struct device_queue_manager_asic_ops { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c index 1695dd78ede8e..ee0739142a2bc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -123,10 +123,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, */ m->cp_hqd_hq_scheduler0 = 1 << 14; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -141,6 +140,12 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -220,6 +225,13 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, if (mm->dev->kfd->cwsr_enabled) m->cp_hqd_ctx_save_control = 0; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } + update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c index 3c0ae28c5923b..547ac70820080 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -177,10 +177,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) m->cp_hqd_hq_status0 |= 1 << 29; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -195,6 +194,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -272,6 +276,12 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, } if (mm->dev->kfd->cwsr_enabled) m->cp_hqd_ctx_save_control = 0; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c index 565858b9044d4..4416cb7c6037b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c @@ -140,10 +140,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) m->cp_hqd_hq_status0 |= 1 << 29; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -158,6 +157,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index e1fa4ed32215d..6222cbd247951 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -247,10 +247,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - if (q->tba_addr) { + if (q->tba_addr) m->compute_pgm_rsrc2 |= (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); - } if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) { m->cp_hqd_persistent_state |= @@ -265,6 +264,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -350,6 +354,13 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) m->cp_hqd_ctx_save_control = 0; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } + if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3) && KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 4) && KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 5, 0)) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index 23669e908d504..752c41b17ad29 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -187,6 +187,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -271,6 +276,12 @@ static void __update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_ctx_save_control = atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT | mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 6f51f061681e9..9fdb869209e30 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -429,6 +429,11 @@ struct kfd_dev { /* for dynamic partitioning */ int kfd_dev_lock; + + /* Lock for profiler process */ + struct mutex profiler_lock; + /* Process currently holding the lock */ + struct kfd_process *profiler_process; }; struct kfd_ipc_obj; @@ -612,6 +617,8 @@ enum mqd_update_flag { UPDATE_FLAG_DBG_WA_ENABLE = 1, UPDATE_FLAG_DBG_WA_DISABLE = 2, UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ + UPDATE_FLAG_PERFCOUNT_ENABLE = 5, + UPDATE_FLAG_PERFCOUNT_DISABLE = 6, }; struct mqd_update_info { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 50047fa9c79f5..9ff4ea8264561 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1038,6 +1038,16 @@ static void kfd_process_free_outstanding_kfd_bos(struct kfd_process *p) kfd_process_device_free_bos(p->pdds[i]); } +static void kfd_process_profiler_release(struct kfd_process *p, struct kfd_process_device *pdd) +{ + mutex_lock(&pdd->dev->kfd->profiler_lock); + if (pdd->dev->kfd->profiler_process == p) { + pdd->qpd.dqm->ops.set_perfcount(pdd->qpd.dqm, 0); + pdd->dev->kfd->profiler_process = NULL; + } + mutex_unlock(&pdd->dev->kfd->profiler_lock); +} + static void kfd_process_destroy_pdds(struct kfd_process *p) { int i; @@ -1050,6 +1060,7 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) pr_debug("Releasing pdd (topology id %d, for pid %d)\n", pdd->dev->id, p->lead_thread->pid); + kfd_process_profiler_release(p, pdd); kfd_pc_sample_release(pdd); kfd_spm_release_process_device(pdd); diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 2e4806afe8d14..08a6d86666320 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1739,6 +1739,31 @@ struct kfd_ioctl_pc_sample_args { __u32 version; }; +#define KFD_IOC_PROFILER_VERSION_NUM 1 +enum kfd_profiler_ops { + KFD_IOC_PROFILER_PMC = 0, + KFD_IOC_PROFILER_PC_SAMPLE = 1, + KFD_IOC_PROFILER_VERSION = 2, +}; + +/** + * Enables/Disables GPU Specific profiler settings + */ +struct kfd_ioctl_pmc_settings { + __u32 gpu_id; /* This is the user_gpu_id */ + __u32 lock; /* Lock GPU for Profiling */ + __u32 perfcount_enable; /* Force Perfcount Enable for queues on GPU */ +}; + +struct kfd_ioctl_profiler_args { + __u32 op; /* kfd_profiler_op */ + union { + struct kfd_ioctl_pc_sample_args pc_sample; + struct kfd_ioctl_pmc_settings pmc; + __u32 version; /* KFD_IOC_PROFILER_VERSION_NUM */ + }; +}; + #define AMDKFD_IOCTL_BASE 'K' #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) @@ -1881,7 +1906,10 @@ struct kfd_ioctl_pc_sample_args { #define AMDKFD_IOC_PC_SAMPLE \ AMDKFD_IOWR(0x85, struct kfd_ioctl_pc_sample_args) +#define AMDKFD_IOC_PROFILER \ + AMDKFD_IOWR(0x86, struct kfd_ioctl_profiler_args) + #define AMDKFD_COMMAND_START_2 0x80 -#define AMDKFD_COMMAND_END_2 0x86 +#define AMDKFD_COMMAND_END_2 0x87 #endif From abc459a56f0d9181d6cd88015aec9c72f3adc47a Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 20 Dec 2024 12:03:51 +0800 Subject: [PATCH 1379/2653] drm/amdkcl: fix build error by adding missing arguments It's caused by the following commit: 907c32e5 "drm/amdkfd: fixed page fault when enable MES shader debugger" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c index aa2bc0dbe2888..6b61b9bab225b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c @@ -362,7 +362,7 @@ int kfd_dbg_set_mes_debug_mode(struct kfd_process_device *pdd, bool sq_trap_en) &pdd->proc_ctx_bo, &pdd->proc_ctx_gpu_addr, &pdd->proc_ctx_cpu_ptr, - false); + false, true); if (r) { dev_err(adev->dev, "failed to allocate process context bo\n"); From c371f003ce4030c6f8dbf6c4c3fa268225c49df0 Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 20 Dec 2024 15:04:08 +0800 Subject: [PATCH 1380/2653] drm/amdkcl: Test if kfifo_out_linear is available Backport this upstream patch and the functions needed to add kfifo_out_linear support for Redhat kernel. This is used in the following patch. commit 4edd7e96a1f1 ("kfifo: add kfifo_out_linear{,_ptr}()") Author: Jiri Slaby (SUSE) Date: Fri Apr 5 08:08:14 2024 +0200 Signed-off-by: Philip Yang Signed-off-by: Flora Cui Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c | 53 ++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/kfifo_out_linear.m4 | 18 ++++ include/kcl/kcl_kfifo.h | 96 +++++++++++++++++++ 7 files changed, 173 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/kfifo_out_linear.m4 create mode 100644 include/kcl/kcl_kfifo.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index adea9fa2bbdda..5f046048ad560 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -16,7 +16,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ - kcl_scatterlist.o + kcl_scatterlist.o kcl_kfifo.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c b/drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c new file mode 100644 index 0000000000000..fad3a2306bdad --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include + +#ifndef HAVE_KFIFO_OUT_LINEAR + +#define __KFIFO_PEEK(data, out, mask) \ + ((data)[(out) & (mask)]) +/* + * __kfifo_peek_n internal helper function for determinate the length of + * the next record in the fifo + */ +static unsigned int __kfifo_peek_n(struct __kfifo *fifo, size_t recsize) +{ + unsigned int l; + unsigned int mask = fifo->mask; + unsigned char *data = fifo->data; + + l = __KFIFO_PEEK(data, fifo->out, mask); + + if (--recsize) + l |= __KFIFO_PEEK(data, fifo->out + 1, mask) << 8; + + return l; +} + +unsigned int __kfifo_out_linear(struct __kfifo *fifo, + unsigned int *tail, unsigned int n) +{ + unsigned int size = fifo->mask + 1; + unsigned int off = fifo->out & fifo->mask; + + if (tail) + *tail = off; + + return min3(n, fifo->in - fifo->out, size - off); +} +EXPORT_SYMBOL(__kfifo_out_linear); + +unsigned int __kfifo_out_linear_r(struct __kfifo *fifo, + unsigned int *tail, unsigned int n, size_t recsize) +{ + if (fifo->in == fifo->out) + return 0; + + if (tail) + *tail = fifo->out + recsize; + + return min(n, __kfifo_peek_n(fifo, recsize)); +} +EXPORT_SYMBOL(__kfifo_out_linear_r); + +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index d58fb8b5ea7a0..3267585bb640a 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -136,6 +136,7 @@ #include #include #include +#include #include #include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c2d82c62e52e1..723a64ee7c2b3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -756,6 +756,9 @@ /* kernel_write() take arg type of position as pointer */ #define HAVE_KERNEL_WRITE_PPOS 1 +/* kfifo_out_linear() available */ +#define HAVE_KFIFO_OUT_LINEAR 1 + /* kfifo_put() have non pointer parameter */ #define HAVE_KFIFO_PUT_NON_POINTER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5d724d7514674..7c54b1951ac67 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -228,6 +228,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_BUF_IS_DYNAMIC AC_AMDGPU_RADIX_TREE_ITER_DELETE AC_AMDGPU_KFIFO_PUT + AC_AMDGPU_KFIFO_OUT_LINEAR AC_AMDGPU_DRM_CLIENT_REGISTER AC_AMDGPU_DRM_COLOR_CTM_3X4 AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP diff --git a/drivers/gpu/drm/amd/dkms/m4/kfifo_out_linear.m4 b/drivers/gpu/drm/amd/dkms/m4/kfifo_out_linear.m4 new file mode 100644 index 0000000000000..ad65e8605f268 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kfifo_out_linear.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v6.9-rc3-3-g4edd7e96a1f1 +dnl # kfifo: add kfifo_out_linear{,_ptr}() +dnl # +AC_DEFUN([AC_AMDGPU_KFIFO_OUT_LINEAR], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + static DEFINE_KFIFO(fifo, int, 2); + unsigned int ret = kfifo_out_linear(&fifo, 0, 0); + ],[ + AC_DEFINE(HAVE_KFIFO_OUT_LINEAR, 1, + [kfifo_out_linear() available]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_kfifo.h b/include/kcl/kcl_kfifo.h new file mode 100644 index 0000000000000..3be41b4d98708 --- /dev/null +++ b/include/kcl/kcl_kfifo.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef KCL_LINUX_KFIFO_H +#define KCL_LINUX_KFIFO_H + +#ifndef HAVE_KFIFO_OUT_LINEAR + +#include + +/** + * commit 4edd7e96a1f159f43bd1cb82616f81eaddd54262 + * Author: Jiri Slaby (SUSE) + * Date: Fri Apr 5 08:08:14 2024 +0200 + * + * kfifo: add kfifo_out_linear{,_ptr}() + */ + +/** + * kfifo_out_linear - gets a tail of/offset to available data + * @fifo: address of the fifo to be used + * @tail: pointer to an unsigned int to store the value of tail + * @n: max. number of elements to point at + * + * This macro obtains the offset (tail) to the available data in the fifo + * buffer and returns the + * numbers of elements available. It returns the available count till the end + * of data or till the end of the buffer. So that it can be used for linear + * data processing (like memcpy() of (@fifo->data + @tail) with count + * returned). + * + * Note that with only one concurrent reader and one concurrent + * writer, you don't need extra locking to use these macro. + */ +#define kfifo_out_linear(fifo, tail, n) \ +__kfifo_uint_must_check_helper( \ +({ \ + typeof((fifo) + 1) __tmp = (fifo); \ + unsigned int *__tail = (tail); \ + unsigned long __n = (n); \ + const size_t __recsize = sizeof(*__tmp->rectype); \ + struct __kfifo *__kfifo = &__tmp->kfifo; \ + (__recsize) ? \ + __kfifo_out_linear_r(__kfifo, __tail, __n, __recsize) : \ + __kfifo_out_linear(__kfifo, __tail, __n); \ +}) \ +) + +/** + * kfifo_out_linear_ptr - gets a pointer to the available data + * @fifo: address of the fifo to be used + * @ptr: pointer to data to store the pointer to tail + * @n: max. number of elements to point at + * + * Similarly to kfifo_out_linear(), this macro obtains the pointer to the + * available data in the fifo buffer and returns the numbers of elements + * available. It returns the available count till the end of available data or + * till the end of the buffer. So that it can be used for linear data + * processing (like memcpy() of @ptr with count returned). + * + * Note that with only one concurrent reader and one concurrent + * writer, you don't need extra locking to use these macro. + */ +#define kfifo_out_linear_ptr(fifo, ptr, n) \ +__kfifo_uint_must_check_helper( \ +({ \ + typeof((fifo) + 1) ___tmp = (fifo); \ + unsigned int ___tail; \ + unsigned int ___n = kfifo_out_linear(___tmp, &___tail, (n)); \ + *(ptr) = ___tmp->kfifo.data + ___tail * kfifo_esize(___tmp); \ + ___n; \ +}) \ +) + +extern unsigned int __kfifo_out_linear(struct __kfifo *fifo, + unsigned int *tail, unsigned int n); + +extern unsigned int __kfifo_out_linear_r(struct __kfifo *fifo, + unsigned int *tail, unsigned int n, size_t recsize); + +/** + * kfifo_skip_count - skip output data + * @fifo: address of the fifo to be used + * @count: count of data to skip + */ +#define kfifo_skip_count(fifo, count) do { \ + typeof((fifo) + 1) __tmp = (fifo); \ + const size_t __recsize = sizeof(*__tmp->rectype); \ + struct __kfifo *__kfifo = &__tmp->kfifo; \ + if (__recsize) \ + __kfifo_skip_r(__kfifo, __recsize); \ + else \ + __kfifo->out += (count); \ +} while (0) + +#endif +#endif From c0e795cff2e97a65c0a342ad522c09a6288c30c6 Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Mon, 23 Dec 2024 09:21:03 -0500 Subject: [PATCH 1381/2653] amdgpu: validate pointer before accessing its field Validate adev pointer before access its field in amdgpu_gem_object_free(), to avoid invalid memory access. Signed-off-by: Jiang Liu Signed-off-by: Kent Russell Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 75e0424131106..e9723049cde7e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -207,7 +207,7 @@ static void amdgpu_gem_object_free(struct drm_gem_object *gobj) #endif { struct amdgpu_bo *aobj = gem_to_amdgpu_bo(gobj); - struct amdgpu_device *adev = amdgpu_ttm_adev(aobj->tbo.bdev); + struct amdgpu_device *adev; if (aobj->flags & AMDGPU_GEM_CREATE_NO_EVICT) { if (!amdgpu_bo_reserve(aobj, false)) { @@ -216,6 +216,7 @@ static void amdgpu_gem_object_free(struct drm_gem_object *gobj) } } + adev = amdgpu_ttm_adev(aobj->tbo.bdev); if (aobj->tbo.resource && aobj->tbo.resource->mem_type == AMDGPU_PL_DGMA) atomic64_sub(amdgpu_bo_size(aobj), &adev->direct_gma.vram_usage); From ea05a2d70c9a3191b04909bbd78eac6e77cfda13 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 17 Dec 2024 19:48:01 +0800 Subject: [PATCH 1382/2653] drm/amdkcl: unify dkms & oot make cmd Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/Kbuild | 230 ++++++++++++++++ drivers/gpu/drm/amd/dkms/Makefile | 246 ++---------------- drivers/gpu/drm/amd/dkms/dkms.conf | 19 +- drivers/gpu/drm/amd/dkms/oot/Makefile.oot | 41 --- drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec | 2 +- drivers/gpu/drm/amd/dkms/oot/pre-build.sh | 91 ------- drivers/gpu/drm/amd/dkms/pre-build.sh | 11 +- 7 files changed, 266 insertions(+), 374 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/Kbuild delete mode 100644 drivers/gpu/drm/amd/dkms/oot/Makefile.oot delete mode 100644 drivers/gpu/drm/amd/dkms/oot/pre-build.sh diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild new file mode 100644 index 0000000000000..6153df061bcd8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -0,0 +1,230 @@ +ifeq ($(CC), gcc) +GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) +GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) +GCCPAT=$(shell echo __GNUC_PATCHLEVEL__ | $(CC) -E -x c - | tail -n 1) +# CONFIG_GCC_VERSION returns x.xx.xx as the version format +GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) + +KERNEL_MAJ=$(VERSION) +KERNEL_PATCHLEVEL=$(PATCHLEVEL) +KERNEL_SUBLEVEL=$(SUBLEVEL) +KERNEL_VER=$(shell printf "%d%02d%02d" $(KERNEL_MAJ) $(KERNEL_PATCHLEVEL) $(KERNEL_SUBLEVEL)) + +kernel-version = $(shell [ $(KERNEL_VER)0 $(1) $(2)000 ] && echo $(3) || echo $(4)) + +ifdef CONFIG_CC_IS_GCC +ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) +$(warning "Local GCC version $(GCCSTR) does not match kernel compiler GCC version $(CONFIG_GCC_VERSION)") +$(warning "This may cause unexpected and hard-to-isolate compiler-related issues") +endif +else +export CONFIG_CC_IS_GCC=y +export CONFIG_GCC_VERSION=$(GCCSTR) +$(warning "CONFIG_CC_IS_GCC is not defined. Let's export it with version $(CONFIG_GCC_VERSION)") +endif + +endif + +include $(src)/amd/dkms/Makefile.compiler + +# gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. +ifneq ($(call gcc-min-version, 40805), y) +ifeq ($(call kernel-version, -ge, 0504, y), y) +$(error "The GCC is too old for this kernel, please update the GCC to higher than 9.3") +endif +endif + +ifndef CONFIG_DRM +$(error CONFIG_DRM disabled, exit...) +endif + +ifeq (y,$(CONFIG_DRM_AMDGPU)) +$(error DRM_AMDGPU is built-in, exit...) +endif + +ifndef CONFIG_KALLSYMS +$(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) +endif + +_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") + +ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) +$(error dma_resv->seq is missing. exit...) +endif + +ifeq ($(call _is_kcl_macro_defined,HAVE_RESERVATION_WW_CLASS_BUG),y) +$(error reservation_ww_class is missing. exit...) +endif + +DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) +DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) +ifeq ($(DRM_VER),) +DRM_VER = $(VERSION) +DRM_PATCH = $(PATCHLEVEL) +endif + +subdir-ccflags-y += \ + -DDRM_VER=$(DRM_VER) \ + -DDRM_PATCH=$(DRM_PATCH) \ + -DDRM_SUB="0" + +define get_rhel_version +printf "#include \n$(1)" | $(CC) $(LINUXINCLUDE) -E -x c - | tail -n 1 | grep -v $(1) +endef +RHEL_MAJOR := $(shell $(call get_rhel_version,RHEL_MAJOR)) +RHEL_MINOR := $(shell $(call get_rhel_version,RHEL_MINOR)) + +ifneq (,$(RHEL_MAJOR)) +OS_NAME = "rhel" +OS_VERSION = "$(RHEL_MAJOR).$(RHEL_MINOR)" +else ifneq (,$(wildcard /etc/os-release)) +OS_NAME = "$(shell sed -n 's/^ID=\(.*\)/\1/p' /etc/os-release | tr -d '\"')" +# On CentOS/RHEL, users could have installed a kernel not distributed from RHEL +ifeq ("centos",$(OS_NAME)) +OS_NAME="custom-rhel" +else ifeq ("rhel",$(OS_NAME)) +OS_NAME="custom-rhel" +else ifeq ("linuxmint",$(OS_NAME)) +OS_NAME="ubuntu" +endif +OS_VERSION = $(shell sed -n 's/^VERSION_ID=\(.*\)/\1/p' /etc/os-release) +else +OS_NAME = "unknown" +OS_VERSION = "0.0" +endif + +OS_VERSION_STR = $(subst .,_,$(OS_VERSION)) + +ifeq ("ubuntu",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_UBUNTU +else ifeq ("rhel",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_RHEL +else ifeq ("steamos",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_STEAMOS +else ifeq ("sled",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_SLE +else ifeq ("sles",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_SLE +else ifeq ("amzn",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_AMZ +else ifeq ("debian",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_DEBIAN +else +subdir-ccflags-y += -DOS_NAME_UNKNOWN +endif + +subdir-ccflags-y += \ + -DOS_VERSION_MAJOR=$(shell echo $(OS_VERSION).0 | cut -d. -f1) \ + -DOS_VERSION_MINOR=$(shell echo $(OS_VERSION).0 | cut -d. -f2) + +ifeq ($(OS_NAME),"opensuse-leap") +subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"sled") +subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"sles") +subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"ubuntu") +OS_BUILD_NUM = $(shell echo $(KERNELRELEASE) | cut -d '-' -f 2) +subdir-ccflags-y += -DUBUNTU_BUILD_NUM=$(OS_BUILD_NUM) +OS_OEM = "$(shell echo $(KERNELRELEASE) | cut -d '-' -f 3)" +ifeq ($(OS_OEM),"oem") +subdir-ccflags-y += -DOS_NAME_UBUNTU_OEM +endif +subdir-ccflags-y += -DOS_NAME_UBUNTU_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"rhel") +subdir-ccflags-y += -DOS_NAME_RHEL_$(OS_VERSION_STR) + +ifeq ($(RHEL_MAJOR),7) +subdir-ccflags-y += -DOS_NAME_RHEL_7_X \ + -include /usr/src/kernels/$(KERNELRELEASE)/include/drm/drm_backport.h +else ifeq ($(RHEL_MAJOR),8) +subdir-ccflags-y += -DOS_NAME_RHEL_8_X +endif +endif + +export OS_NAME OS_VERSION + +_KCL_LINUXINCLUDE=$(subst -I ,-I,$(strip $(LINUXINCLUDE))) +LINUX_SRCTREE_INCLUDE := \ + $(filter-out -I%/uapi "-include %/kconfig.h",$(_KCL_LINUXINCLUDE)) +USER_INCLUDE := $(filter-out $(LINUX_SRCTREE_INCLUDE), $(_KCL_LINUXINCLUDE)) + +LINUXINCLUDE := \ + -I$(src)/include \ + -I$(src)/include/kcl/header \ + -include $(src)/include/kcl/kcl_version.h \ + -include $(src)/include/rename_symbol.h \ + -include $(src)/amd/dkms/config/config.h \ + $(LINUX_SRCTREE_INCLUDE) \ + -I$(src)/include/uapi \ + $(USER_INCLUDE) + +export CONFIG_HSA_AMD=y +export CONFIG_DRM_TTM=m +export CONFIG_DRM_TTM_DMA_PAGE_POOL=y +export CONFIG_DRM_AMDGPU=m +export CONFIG_DRM_SCHED=m +export CONFIG_DRM_AMDGPU_CIK=y +export CONFIG_DRM_AMDGPU_SI=y +export CONFIG_DRM_AMDGPU_USERPTR=y +export CONFIG_DRM_AMD_DC=y + +subdir-ccflags-y += -DCONFIG_HSA_AMD +subdir-ccflags-y += -DCONFIG_DRM_TTM_DMA_PAGE_POOL +subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK +subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI +subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC +subdir-ccflags-y += -Wno-error + +ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) +ifdef CONFIG_DEVICE_PRIVATE +export CONFIG_HSA_AMD_SVM=y +subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM +endif +endif + +export CONFIG_DRM_AMD_DC_HDCP=y +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP + +ifeq (y,$(CONFIG_PCI_P2PDMA)) + ifeq (y,$(CONFIG_DMABUF_MOVENOTIFY)) + export CONFIG_HSA_AMD_P2P=y + subdir-ccflags-y += -DCONFIG_HSA_AMD_P2P + endif +endif + +# Trying to enable DCN2/3 with core2 optimizations will result in +# older versions of GCC hanging during building/installing. Check +# if the compiler is using core2 optimizations and only build DCN2/3 +# if core2 isn't in the compiler flags +ifndef CONFIG_ARM64 +ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) +export CONFIG_DRM_AMD_DC_FP=y +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_FP +endif +endif + +# v5.17-rc4-3-ge8c07082a810 (Kbuild: move to -std=gnu11) +# Upstream patches now uses gnu11/gnu99 as the default C standard version. +# However, gcc in legacy OS still uses gnu89, which will introduce a standard +# build gap leading to a DKMS build failure possibly. So add below check to +# move gnu89 to gnu99 if KBUILD_CFLAGS still uses gnu89. +ifeq ($(findstring gnu89,$(KBUILD_CFLAGS)),gnu89) +KBUILD_CFLAGS := $(subst gnu89,gnu99,$(KBUILD_CFLAGS)) +$(warning "The local C standard(gnu89) doesn't match kernel default C standard(gnu11/gnu99)") +endif + +include $(src)/amd/dkms/Makefile.drm_ttm_helper + +include $(src)/amd/dkms/Makefile.drm_buddy + +obj-m += scheduler/ amd/amdgpu/ amd/amdxcp/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 6153df061bcd8..59d814c49e8e3 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -1,230 +1,40 @@ -ifeq ($(CC), gcc) -GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) -GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) -GCCPAT=$(shell echo __GNUC_PATCHLEVEL__ | $(CC) -E -x c - | tail -n 1) -# CONFIG_GCC_VERSION returns x.xx.xx as the version format -GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) - -KERNEL_MAJ=$(VERSION) -KERNEL_PATCHLEVEL=$(PATCHLEVEL) -KERNEL_SUBLEVEL=$(SUBLEVEL) -KERNEL_VER=$(shell printf "%d%02d%02d" $(KERNEL_MAJ) $(KERNEL_PATCHLEVEL) $(KERNEL_SUBLEVEL)) - -kernel-version = $(shell [ $(KERNEL_VER)0 $(1) $(2)000 ] && echo $(3) || echo $(4)) - -ifdef CONFIG_CC_IS_GCC -ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) -$(warning "Local GCC version $(GCCSTR) does not match kernel compiler GCC version $(CONFIG_GCC_VERSION)") -$(warning "This may cause unexpected and hard-to-isolate compiler-related issues") -endif -else -export CONFIG_CC_IS_GCC=y -export CONFIG_GCC_VERSION=$(GCCSTR) -$(warning "CONFIG_CC_IS_GCC is not defined. Let's export it with version $(CONFIG_GCC_VERSION)") -endif - -endif - -include $(src)/amd/dkms/Makefile.compiler - -# gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. -ifneq ($(call gcc-min-version, 40805), y) -ifeq ($(call kernel-version, -ge, 0504, y), y) -$(error "The GCC is too old for this kernel, please update the GCC to higher than 9.3") -endif -endif - -ifndef CONFIG_DRM -$(error CONFIG_DRM disabled, exit...) -endif - -ifeq (y,$(CONFIG_DRM_AMDGPU)) -$(error DRM_AMDGPU is built-in, exit...) -endif - -ifndef CONFIG_KALLSYMS -$(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) -endif - -_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") - -ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) -$(error dma_resv->seq is missing. exit...) -endif - -ifeq ($(call _is_kcl_macro_defined,HAVE_RESERVATION_WW_CLASS_BUG),y) -$(error reservation_ww_class is missing. exit...) -endif - -DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) -DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) -ifeq ($(DRM_VER),) -DRM_VER = $(VERSION) -DRM_PATCH = $(PATCHLEVEL) -endif - -subdir-ccflags-y += \ - -DDRM_VER=$(DRM_VER) \ - -DDRM_PATCH=$(DRM_PATCH) \ - -DDRM_SUB="0" - -define get_rhel_version -printf "#include \n$(1)" | $(CC) $(LINUXINCLUDE) -E -x c - | tail -n 1 | grep -v $(1) -endef -RHEL_MAJOR := $(shell $(call get_rhel_version,RHEL_MAJOR)) -RHEL_MINOR := $(shell $(call get_rhel_version,RHEL_MINOR)) - -ifneq (,$(RHEL_MAJOR)) -OS_NAME = "rhel" -OS_VERSION = "$(RHEL_MAJOR).$(RHEL_MINOR)" -else ifneq (,$(wildcard /etc/os-release)) -OS_NAME = "$(shell sed -n 's/^ID=\(.*\)/\1/p' /etc/os-release | tr -d '\"')" -# On CentOS/RHEL, users could have installed a kernel not distributed from RHEL -ifeq ("centos",$(OS_NAME)) -OS_NAME="custom-rhel" -else ifeq ("rhel",$(OS_NAME)) -OS_NAME="custom-rhel" -else ifeq ("linuxmint",$(OS_NAME)) -OS_NAME="ubuntu" -endif -OS_VERSION = $(shell sed -n 's/^VERSION_ID=\(.*\)/\1/p' /etc/os-release) +ifneq ($(KERNELRELEASE),) +include $(src)/amd/dkms/Kbuild else -OS_NAME = "unknown" -OS_VERSION = "0.0" -endif - -OS_VERSION_STR = $(subst .,_,$(OS_VERSION)) - -ifeq ("ubuntu",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_UBUNTU -else ifeq ("rhel",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_RHEL -else ifeq ("steamos",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_STEAMOS -else ifeq ("sled",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_SLE -else ifeq ("sles",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_SLE -else ifeq ("amzn",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_AMZ -else ifeq ("debian",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_DEBIAN -else -subdir-ccflags-y += -DOS_NAME_UNKNOWN -endif - -subdir-ccflags-y += \ - -DOS_VERSION_MAJOR=$(shell echo $(OS_VERSION).0 | cut -d. -f1) \ - -DOS_VERSION_MINOR=$(shell echo $(OS_VERSION).0 | cut -d. -f2) - -ifeq ($(OS_NAME),"opensuse-leap") -subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) -endif - -ifeq ($(OS_NAME),"sled") -subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) -endif - -ifeq ($(OS_NAME),"sles") -subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) -endif - -ifeq ($(OS_NAME),"ubuntu") -OS_BUILD_NUM = $(shell echo $(KERNELRELEASE) | cut -d '-' -f 2) -subdir-ccflags-y += -DUBUNTU_BUILD_NUM=$(OS_BUILD_NUM) -OS_OEM = "$(shell echo $(KERNELRELEASE) | cut -d '-' -f 3)" -ifeq ($(OS_OEM),"oem") -subdir-ccflags-y += -DOS_NAME_UBUNTU_OEM -endif -subdir-ccflags-y += -DOS_NAME_UBUNTU_$(OS_VERSION_STR) -endif +KERNELVER := $(shell uname -r) +kernel_build_dir := /lib/modules/$(KERNELVER)/build +module_src_dir := $(CURDIR) +module_build_dir := $(shell mktemp -ut amd.XXXXXXXX) +module_build_flags := +num_cpu_cores := $(shell which nproc > /dev/null && nproc || echo "1") +Q := @ -ifeq ($(OS_NAME),"rhel") -subdir-ccflags-y += -DOS_NAME_RHEL_$(OS_VERSION_STR) - -ifeq ($(RHEL_MAJOR),7) -subdir-ccflags-y += -DOS_NAME_RHEL_7_X \ - -include /usr/src/kernels/$(KERNELRELEASE)/include/drm/drm_backport.h -else ifeq ($(RHEL_MAJOR),8) -subdir-ccflags-y += -DOS_NAME_RHEL_8_X -endif +ifeq ($(wildcard $(kernel_build_dir)/include/config/auto.conf),) +$(error "invalid kernel obj dir, is kernel-devel installed?") endif -export OS_NAME OS_VERSION - -_KCL_LINUXINCLUDE=$(subst -I ,-I,$(strip $(LINUXINCLUDE))) -LINUX_SRCTREE_INCLUDE := \ - $(filter-out -I%/uapi "-include %/kconfig.h",$(_KCL_LINUXINCLUDE)) -USER_INCLUDE := $(filter-out $(LINUX_SRCTREE_INCLUDE), $(_KCL_LINUXINCLUDE)) - -LINUXINCLUDE := \ - -I$(src)/include \ - -I$(src)/include/kcl/header \ - -include $(src)/include/kcl/kcl_version.h \ - -include $(src)/include/rename_symbol.h \ - -include $(src)/amd/dkms/config/config.h \ - $(LINUX_SRCTREE_INCLUDE) \ - -I$(src)/include/uapi \ - $(USER_INCLUDE) - -export CONFIG_HSA_AMD=y -export CONFIG_DRM_TTM=m -export CONFIG_DRM_TTM_DMA_PAGE_POOL=y -export CONFIG_DRM_AMDGPU=m -export CONFIG_DRM_SCHED=m -export CONFIG_DRM_AMDGPU_CIK=y -export CONFIG_DRM_AMDGPU_SI=y -export CONFIG_DRM_AMDGPU_USERPTR=y -export CONFIG_DRM_AMD_DC=y +.PHONY: modules pre-build clean -subdir-ccflags-y += -DCONFIG_HSA_AMD -subdir-ccflags-y += -DCONFIG_DRM_TTM_DMA_PAGE_POOL -subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK -subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI -subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC -subdir-ccflags-y += -Wno-error +include $(kernel_build_dir)/include/config/auto.conf -ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) -ifdef CONFIG_DEVICE_PRIVATE -export CONFIG_HSA_AMD_SVM=y -subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM +ifneq ($(CONFIG_CC_IS_CLANG),) +module_build_flags += CC=clang endif +ifneq ($(CONFIG_LD_IS_LLD),) +module_build_flags += LD=ld.lld endif -export CONFIG_DRM_AMD_DC_HDCP=y -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP +modules:pre-build + $(Q)$(shell cat $(module_build_dir)/.env) make -j$(num_cpu_cores) \ + TTM_NAME=amdttm \ + SCHED_NAME=amd-sched \ + -C $(kernel_build_dir) \ + M=$(module_build_dir) $(module_build_flags) + $(Q)amd/dkms/post-build.sh $(module_build_dir) -ifeq (y,$(CONFIG_PCI_P2PDMA)) - ifeq (y,$(CONFIG_DMABUF_MOVENOTIFY)) - export CONFIG_HSA_AMD_P2P=y - subdir-ccflags-y += -DCONFIG_HSA_AMD_P2P - endif -endif - -# Trying to enable DCN2/3 with core2 optimizations will result in -# older versions of GCC hanging during building/installing. Check -# if the compiler is using core2 optimizations and only build DCN2/3 -# if core2 isn't in the compiler flags -ifndef CONFIG_ARM64 -ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) -export CONFIG_DRM_AMD_DC_FP=y -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_FP -endif -endif +pre-build: + $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(module_build_dir) -# v5.17-rc4-3-ge8c07082a810 (Kbuild: move to -std=gnu11) -# Upstream patches now uses gnu11/gnu99 as the default C standard version. -# However, gcc in legacy OS still uses gnu89, which will introduce a standard -# build gap leading to a DKMS build failure possibly. So add below check to -# move gnu89 to gnu99 if KBUILD_CFLAGS still uses gnu89. -ifeq ($(findstring gnu89,$(KBUILD_CFLAGS)),gnu89) -KBUILD_CFLAGS := $(subst gnu89,gnu99,$(KBUILD_CFLAGS)) -$(warning "The local C standard(gnu89) doesn't match kernel default C standard(gnu11/gnu99)") +clean: + $(Q)make -C $(kernel_build_dir) M=$(module_src_dir) clean endif - -include $(src)/amd/dkms/Makefile.drm_ttm_helper - -include $(src)/amd/dkms/Makefile.drm_buddy - -obj-m += scheduler/ amd/amdgpu/ amd/amdxcp/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index ceef7d15a7c26..7d262536848b6 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -1,9 +1,6 @@ PACKAGE_NAME="amdgpu" PACKAGE_VERSION="1.0" AUTOINSTALL="yes" -module_build_dir="$(mktemp -ut amd.XXXXXXXX)" -PRE_BUILD="amd/dkms/pre-build.sh $kernelver $dkms_tree $module $module_version $module_build_dir" -POST_BUILD="amd/dkms/post-build.sh $module_build_dir" # not all OS supports weak module updates NO_WEAK_MODULES="yes" @@ -38,17 +35,5 @@ BUILT_MODULE_NAME[6]="amdxcp" BUILT_MODULE_LOCATION[6]="amd/amdxcp" DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm/amd/amdxcp" -num_cpu_cores() -{ - if [ -x /usr/bin/nproc ]; then - nproc - else - echo "1" - fi -} - -MAKE[0]=". $module_build_dir/.env && make -j$(num_cpu_cores) KERNELRELEASE=$kernelver \ - TTM_NAME=${BUILT_MODULE_NAME[1]} \ - SCHED_NAME=${BUILT_MODULE_NAME[3]} \ - -C $kernel_source_dir \ - M=$module_build_dir" +MAKE[0]="'make' KERNELVER=$kernelver" + diff --git a/drivers/gpu/drm/amd/dkms/oot/Makefile.oot b/drivers/gpu/drm/amd/dkms/oot/Makefile.oot deleted file mode 100644 index 5c8c78df4e932..0000000000000 --- a/drivers/gpu/drm/amd/dkms/oot/Makefile.oot +++ /dev/null @@ -1,41 +0,0 @@ -ifneq ($(KERNELRELEASE),) -include $(src)/amd/dkms/Makefile -else -KERNELVER := $(shell uname -r) -kernel_build_dir := /lib/modules/$(KERNELVER)/build -PACKAGE_NAME := $(shell sed -n '/PACKAGE_NAME/s|.*=||p' amd/dkms/dkms.conf) -PACKAGE_VERSION := $(shell sed -n '/PACKAGE_VERSION/s|.*=||p' amd/dkms/dkms.conf) -module_src_dir := $(CURDIR) -module_build_dir := $(shell mktemp -ut amd.XXXXXXXX) -module_build_flags := -num_cpu_cores := $(shell nproc) -Q := @ - -ifeq ($(wildcard $(kernel_build_dir)/include/config/auto.conf),) -$(error "invalid kernel obj dir, is kernel-devel installed?") -endif - -.PHONY: modules pre-build - -include $(kernel_build_dir)/include/config/auto.conf - -ifneq ($(CONFIG_CC_IS_CLANG),) -module_build_flags += CC=clang -endif -ifneq ($(CONFIG_LD_IS_LLD),) -module_build_flags += LD=ld.lld -endif - -modules:pre-build - $(Q)make -j$(num_cpu_cores) KERNELRELEASE=$(KERNELVER) \ - TTM_NAME=amdttm \ - SCHED_NAME=amd-sched \ - -C $(kernel_build_dir) \ - M=$(module_build_dir) $(module_build_flags) - $(Q)unlink $(module_build_dir) - -pre-build: - $(Q)cp -f amd/dkms/oot/pre-build.sh amd/dkms - $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(PACKAGE_NAME) $(PACKAGE_VERSION) $(module_build_dir) - -endif diff --git a/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec index 5f00c10afe2db..79795b24bb7c8 100644 --- a/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec +++ b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec @@ -27,7 +27,7 @@ The AMD display driver kernel module in DKMS format for AMD graphics S/W %build pushd src -%{__make} -f amd/dkms/oot/Makefile.oot KERNELVER=%(uname -r) +%{__make} KERNELVER=%(uname -r) popd %install diff --git a/drivers/gpu/drm/amd/dkms/oot/pre-build.sh b/drivers/gpu/drm/amd/dkms/oot/pre-build.sh deleted file mode 100644 index 7cb58df401aa8..0000000000000 --- a/drivers/gpu/drm/amd/dkms/oot/pre-build.sh +++ /dev/null @@ -1,91 +0,0 @@ -#!/bin/bash - -KCL="amd/amdkcl" -INC="include" -SRC="amd/dkms" - -KERNELVER=$1 -DKMS_TREE=$2 -MODULE=$3 -MODULE_VERSION=$4 -MODULE_BUILD_DIR=$5 -KERNELVER_BASE=${KERNELVER%%-*} - -version_lt () { - newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) - [ "$KERNELVER_BASE" != "$newest" ] -} - -version_ge () { - newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) - [ "$KERNELVER_BASE" = "$newest" ] -} - -version_gt () { - oldest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | head -n1) - [ "$KERNELVER_BASE" != "$oldest" ] -} - -version_le () { - oldest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | head -n1) - [ "$KERNELVER_BASE" = "$oldest" ] -} - -source $KCL/files - -sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ - -e '/dma_resv_lockdep/,/subsys_initcall/d' \ - -e '1i\#ifdef HAVE_DMA_RESV_FENCES' \ - -e '$a\#endif' $KCL/dma-buf/dma-resv.c -sed -i -e '/extern struct ww_class reservation_ww_class/i #include ' \ - -e '/struct dma_resv {/, /}/d' \ - -e '/struct dma_resv_iter {/, /}/d' \ - -e '/enum dma_resv_usage {/, /}/d' $INC/linux/dma-resv.h - -# add amd prefix to exported symbols -for file in $FILES; do - awk -F'[()]' '/EXPORT_SYMBOL/ { - print "#define "$2" amd"$2" //"$0 - }' $file | sort -u >>$INC/rename_symbol.h -done - -# rename CONFIG_xxx to CONFIG_xxx_AMDKCL -# otherwise kernel config would override dkms package config -AMDGPU_CONFIG=$(find -name Kconfig -exec grep -h '^config' {} + | sed 's/ /_/' | tr 'a-z' 'A-Z') -TTM_CONFIG=$(awk '/CONFIG_DRM/{gsub(".*\\(CONFIG_DRM","CONFIG_DRM");gsub("\\).*","");print $0}' ttm/Makefile) -SCHED_CONFIG=$(awk '/CONFIG_DRM/{gsub(".*\\(CONFIG_DRM","CONFIG_DRM");gsub("\\).*","");print $0}' scheduler/Makefile) -for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do - for file in $(grep -rl $config ./); do - sed -i "s/\<$config\>/&_AMDKCL/" $file - done - sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile -done - -export KERNELVER -ln -s $DKMS_TREE $MODULE_BUILD_DIR - -# Enable gcc-toolset for kernels that are built with non-default compiler -# perform this check only when permissions allow -if [[ -d /opt/rh && `id -u` -eq 0 ]]; then - for f in $(find /opt/rh -type f -a -name gcc); do - [[ -f /boot/config-$KERNELVER ]] || continue - config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) - IFS='.' read -ra ver <<<$($f -dumpfullversion) - gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) - if [[ "$config_gcc_version" = "$gcc_version" ]]; then - . ${f%/*}/../../../enable - break - fi - done -fi -echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env - -(cd $SRC && ./configure) - -# rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o -# for kernel version < 5.3 -if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then - for file in $(grep -rl 'CFLAGS_' amd/display/); do - sed -i 's|\(CFLAGS_[A-Z_]*\)$(AMDDALPATH)/.*/\(.*\.o\)|\1\2|' $file - done -fi diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index ec0c41cd4411e..7f3e5f9323673 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -6,9 +6,7 @@ SRC="amd/dkms" KERNELVER=$1 DKMS_TREE=$2 -MODULE=$3 -MODULE_VERSION=$4 -MODULE_BUILD_DIR=$5 +MODULE_BUILD_DIR=$3 KERNELVER_BASE=${KERNELVER%%-*} version_lt () { @@ -58,14 +56,15 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do for file in $(grep -rl $config ./); do sed -i "s/\<$config\>/&_AMDKCL/" $file done - sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile + sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Kbuild done export KERNELVER -ln -s $DKMS_TREE/$MODULE/$MODULE_VERSION/build $MODULE_BUILD_DIR +ln -s $DKMS_TREE $MODULE_BUILD_DIR # Enable gcc-toolset for kernels that are built with non-default compiler -if [[ -d /opt/rh ]]; then +# perform this check only when permissions allow +if [[ -d /opt/rh && `id -u` -eq 0 ]]; then for f in $(find /opt/rh -type f -a -name gcc); do [[ -f /boot/config-$KERNELVER ]] || continue config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) From 8cff1279e436a764617adbd0bd5b110e33a0de5b Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 23 Dec 2024 11:01:06 +0800 Subject: [PATCH 1383/2653] drm/amdkcl: fake perfmon_capable() if not define macro CAP_PERFMON It's caused by the following commit:b58289f0 "Add kfd_ioctl_profiler to contain profiler kernel driver changes" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- include/kcl/kcl_capability.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_capability.h b/include/kcl/kcl_capability.h index 52448ad625f96..7373bcf3ac8f4 100644 --- a/include/kcl/kcl_capability.h +++ b/include/kcl/kcl_capability.h @@ -30,6 +30,11 @@ #ifndef CAP_PERFMON #define CAP_PERFMON 38 + +static inline bool perfmon_capable(void) +{ + return capable(CAP_PERFMON) || capable(CAP_SYS_ADMIN); +} #endif #endif From 3a7d374645dc52ca28997621d6c2484e7278c3ee Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 3 Dec 2024 13:55:07 +0800 Subject: [PATCH 1384/2653] drm/amdkcl: redefine KCL_DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 4 -- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 8 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 12 ------ drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 6 --- drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c | 4 -- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 4 -- drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 6 --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 7 +--- drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c | 2 +- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 26 ------------- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 39 ------------------- include/kcl/kcl_debugfs.h | 22 ++++++++++- 12 files changed, 22 insertions(+), 118 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c index d7c37124e932c..cbc40cad581b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c @@ -957,11 +957,7 @@ static const struct file_operations aca_ue_dump_debug_fops = { .release = single_release, }; -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(aca_debug_mode_fops, NULL, amdgpu_aca_smu_debug_mode_set, "%llu\n"); -#else -DEFINE_SIMPLE_ATTRIBUTE(aca_debug_mode_fops, NULL, amdgpu_aca_smu_debug_mode_set, "%llu\n"); -#endif #endif void amdgpu_aca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index e919ab95ace30..631780121a1e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -1827,14 +1827,12 @@ static int amdgpu_debugfs_vm_info_show(struct seq_file *m, void *unused) DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_test_ib); DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_vm_info); -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_vram_fops, amdgpu_debugfs_evict_vram, NULL, "%lld\n"); DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_gtt_fops, amdgpu_debugfs_evict_gtt, NULL, "%lld\n"); DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_benchmark_fops, NULL, amdgpu_debugfs_benchmark, "%lld\n"); -#endif static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring *ring, struct dma_fence **fences) @@ -2049,13 +2047,11 @@ static int amdgpu_debugfs_sclk_set(void *data, u64 val) return ret; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL, amdgpu_debugfs_ib_preempt, "%llu\n"); DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL, amdgpu_debugfs_sclk_set, "%llu\n"); -#endif int amdgpu_debugfs_init(struct amdgpu_device *adev) { @@ -2066,7 +2062,6 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) if (!debugfs_initialized()) return 0; -#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_x32("amdgpu_smu_debug", 0600, root, &adev->pm.smu_debug_mask); @@ -2083,7 +2078,6 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) DRM_ERROR("unable to create amdgpu_set_sclk debugsfs file\n"); return PTR_ERR(ent); } -#endif /* Register debugfs entries for amdgpu_ttm */ amdgpu_ttm_debugfs_init(adev); @@ -2140,14 +2134,12 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) amdgpu_fw_attestation_debugfs_init(adev); amdgpu_psp_debugfs_init(adev); -#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file("amdgpu_evict_vram", 0400, root, adev, &amdgpu_evict_vram_fops); debugfs_create_file("amdgpu_evict_gtt", 0400, root, adev, &amdgpu_evict_gtt_fops); debugfs_create_file("amdgpu_benchmark", 0200, root, adev, &amdgpu_benchmark_fops); -#endif debugfs_create_file("amdgpu_test_ib", 0400, root, adev, &amdgpu_debugfs_test_ib_fops); debugfs_create_file("amdgpu_vm_info", 0444, root, adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index e010155fd246b..c80c8f5435321 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -2388,15 +2388,9 @@ static int amdgpu_debugfs_gfx_sched_mask_get(void *data, u64 *val) return 0; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gfx_sched_mask_fops, amdgpu_debugfs_gfx_sched_mask_get, amdgpu_debugfs_gfx_sched_mask_set, "%llx\n"); -#else -DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_gfx_sched_mask_fops, - amdgpu_debugfs_gfx_sched_mask_get, - amdgpu_debugfs_gfx_sched_mask_set, "%llx\n"); -#endif #endif @@ -2465,15 +2459,9 @@ static int amdgpu_debugfs_compute_sched_mask_get(void *data, u64 *val) return 0; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_compute_sched_mask_fops, amdgpu_debugfs_compute_sched_mask_get, amdgpu_debugfs_compute_sched_mask_set, "%llx\n"); -#else -DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_compute_sched_mask_fops, - amdgpu_debugfs_compute_sched_mask_get, - amdgpu_debugfs_compute_sched_mask_set, "%llx\n"); -#endif #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c index b409c5ef5b734..82d58ac7afb01 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c @@ -399,15 +399,9 @@ static int amdgpu_debugfs_jpeg_sched_mask_get(void *data, u64 *val) return 0; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_jpeg_sched_mask_fops, amdgpu_debugfs_jpeg_sched_mask_get, amdgpu_debugfs_jpeg_sched_mask_set, "%llx\n"); -#else -DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_jpeg_sched_mask_fops, - amdgpu_debugfs_jpeg_sched_mask_get, - amdgpu_debugfs_jpeg_sched_mask_set, "%llx\n"); -#endif #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c index 78a89601e4e5e..3ca03b5e0f913 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c @@ -613,11 +613,7 @@ static const struct file_operations mca_ue_dump_debug_fops = { .release = single_release, }; -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_set, "%llu\n"); -#else -DEFINE_SIMPLE_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_set, "%llu\n"); -#endif #endif void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 69b0dce1fa6b0..a910a1c9d536c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -628,7 +628,6 @@ static const struct file_operations amdgpu_debugfs_mqd_fops = { .llseek = default_llseek }; -#ifdef DEFINE_DEBUGFS_ATTRIBUTE static int amdgpu_debugfs_ring_error(void *data, u64 val) { struct amdgpu_ring *ring = data; @@ -640,7 +639,6 @@ static int amdgpu_debugfs_ring_error(void *data, u64 val) DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(amdgpu_debugfs_error_fops, NULL, amdgpu_debugfs_ring_error, "%lld\n"); #endif -#endif void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring) @@ -667,12 +665,10 @@ void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, ring->mqd_size); } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE sprintf(name, "amdgpu_error_%s", ring->name); debugfs_create_file(name, 0200, root, ring, &amdgpu_debugfs_error_fops); #endif -#endif } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index e3b9f48ad13f1..8b8a04138711c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c @@ -434,15 +434,9 @@ static int amdgpu_debugfs_sdma_sched_mask_get(void *data, u64 *val) return 0; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_sdma_sched_mask_fops, amdgpu_debugfs_sdma_sched_mask_get, amdgpu_debugfs_sdma_sched_mask_set, "%llx\n"); -#else -DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_sdma_sched_mask_fops, - amdgpu_debugfs_sdma_sched_mask_get, - amdgpu_debugfs_sdma_sched_mask_set, "%llx\n"); -#endif #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index d3ed944749f00..d799bc74936c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -1409,15 +1409,10 @@ static int amdgpu_debugfs_vcn_sched_mask_get(void *data, u64 *val) *val = mask; return 0; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE + DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_vcn_sched_mask_fops, amdgpu_debugfs_vcn_sched_mask_get, amdgpu_debugfs_vcn_sched_mask_set, "%llx\n"); -#else -DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_vcn_sched_mask_fops, - amdgpu_debugfs_vcn_sched_mask_get, - amdgpu_debugfs_vcn_sched_mask_set, "%llx\n"); -#endif #endif void amdgpu_debugfs_vcn_sched_mask_init(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c b/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c index def9db4463a22..919f869e81857 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c @@ -14,7 +14,7 @@ #include #include -#ifdef KCL_FAKE_DEBUGFS_ATTRIBUTE_SIGNED +#ifdef KCL_FAKE_DEBUGFS_ATTRIBUTE_XSIGNED /* Copied from fs/libfs.c */ struct simple_attr { int (*get)(void *, u64 *); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 4a9866b7c7718..241e877a127cc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -572,7 +572,6 @@ static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, return result; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE static int dp_lttpr_status_show(struct seq_file *m, void *unused) { struct drm_connector *connector = m->private; @@ -607,7 +606,6 @@ static int dp_lttpr_status_show(struct seq_file *m, void *unused) seq_puts(m, "\n"); return 0; } -#endif static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, size_t size, loff_t *pos) @@ -2919,9 +2917,7 @@ static ssize_t hdmi_cec_state_write(struct file *f, const char __user *buf, DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); -#endif DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); DEFINE_SHOW_ATTRIBUTE(internal_display); DEFINE_SHOW_ATTRIBUTE(odm_combine_segments); @@ -3044,9 +3040,7 @@ static const struct { } dp_debugfs_entries[] = { {"link_settings", &dp_link_settings_debugfs_fops}, {"phy_settings", &dp_phy_settings_debugfs_fop}, -#ifdef DEFINE_DEBUGFS_ATTRIBUTE {"lttpr_status", &dp_lttpr_status_fops}, -#endif {"test_pattern", &dp_phy_test_pattern_fops}, {"hdcp_sink_capability", &hdcp_sink_capability_fops}, {"sdp_message", &sdp_message_fops}, @@ -3103,10 +3097,8 @@ static int force_yuv420_output_get(void *data, u64 *val) return 0; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, force_yuv420_output_set, "%llu\n"); -#endif /* * Read Replay state @@ -3369,7 +3361,6 @@ static int dmcub_trace_event_state_get(void *data, u64 *val) return 0; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, dmcub_trace_event_state_set, "%llu\n"); @@ -3387,7 +3378,6 @@ DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops, DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops, disallow_edp_enter_psr_get, disallow_edp_enter_psr_set, "%llu\n"); -#endif DEFINE_SHOW_ATTRIBUTE(current_backlight); DEFINE_SHOW_ATTRIBUTE(target_backlight); @@ -3397,9 +3387,7 @@ static const struct { char *name; const struct file_operations *fops; } connector_debugfs_entries[] = { -#ifdef DEFINE_DEBUGFS_ATTRIBUTE {"force_yuv420_output", &force_yuv420_output_fops}, -#endif {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, {"internal_display", &internal_display_fops}, {"odm_combine_segments", &odm_combine_segments_fops} @@ -3553,7 +3541,6 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) } } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { debugfs_create_file("replay_capability", 0444, dir, connector, &replay_capability_fops); @@ -3575,7 +3562,6 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector, &disallow_edp_enter_psr_fops); } -#endif for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { debugfs_create_file(connector_debugfs_entries[i].name, @@ -3895,7 +3881,6 @@ static int mst_topo_show(struct seq_file *m, void *unused) return 0; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE /* * Sets trigger hpd for MST topologies. * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. @@ -3969,7 +3954,6 @@ static int trigger_hpd_mst_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, trigger_hpd_mst_set, "%llu\n"); -#endif /* * Sets the force_timing_sync debug option from the given string. @@ -4000,13 +3984,9 @@ static int force_timing_sync_get(void *data, u64 *val) return 0; } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, force_timing_sync_set, "%llu\n"); -#endif - -#ifdef DEFINE_DEBUGFS_ATTRIBUTE /* * Disables all HPD and HPD RX interrupt handling in the * driver when set to 1. Default is 0. @@ -4036,7 +4016,6 @@ static int disable_hpd_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, disable_hpd_set, "%llu\n"); -#endif /* * Prints hardware capabilities. These are used for IGT testing. @@ -4146,11 +4125,9 @@ static int visual_confirm_get(void *data, u64 *val) } DEFINE_SHOW_ATTRIBUTE(mst_topo); -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, visual_confirm_set, "%llu\n"); - /* * Sets the DC skip_detection_link_training debug option from the given string. * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training @@ -4183,7 +4160,6 @@ static int skip_detection_link_training_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops, skip_detection_link_training_get, skip_detection_link_training_set, "%llu\n"); -#endif /* * Dumps the DCC_EN bit for each pipe. @@ -4271,7 +4247,6 @@ void dtn_debugfs_init(struct amdgpu_device *adev) debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, &dtn_log_fops); -#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, &dp_set_mst_en_for_sst_ops); debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, @@ -4309,5 +4284,4 @@ void dtn_debugfs_init(struct amdgpu_device *adev) if (adev->dm.dc->caps.ips_support) debugfs_create_file_unsafe("amdgpu_dm_ips_status", 0644, root, adev, &ips_status_fops); -#endif } diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index d36bbfd01daee..611ebb1fb145e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -4179,7 +4179,6 @@ static int smu_phase_det_debugfs_enable(void *data, u64 val) return smu_phase_det_enable(smu, !!val); } -#ifdef DEFINE_DEBUGFS_ATTRIBUTE #define DEBUGFS_PHASE_DET_FOPS(param) \ static int smu_phase_det_fops_##param##_get(void *data, u64 *val) \ { \ @@ -4206,34 +4205,6 @@ static int smu_phase_det_debugfs_enable(void *data, u64 val) DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_##param, \ smu_phase_det_fops_##param##_get, \ smu_phase_det_fops_##param##_set, "%llu\n") -#else -#define DEBUGFS_PHASE_DET_FOPS(param) \ - static int smu_phase_det_fops_##param##_get(void *data, u64 *val) \ - { \ - struct smu_context *smu = (struct smu_context *)data; \ - int r; \ - u32 v; \ - \ - r = smu_get_phase_det_param(smu, PP_PM_PHASE_DET_##param, &v); \ - *val = v; \ - return r; \ - } \ - \ - static int smu_phase_det_fops_##param##_set(void *data, u64 val) \ - { \ - struct smu_context *smu = (struct smu_context *)data; \ - struct amdgpu_device *adev = smu->adev; \ - \ - if (amdgpu_in_reset(adev) || adev->in_suspend) \ - return -EPERM; \ - \ - return smu_set_phase_det_param(smu, PP_PM_PHASE_DET_##param, \ - (u32)val); \ - } \ - DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_##param, \ - smu_phase_det_fops_##param##_get, \ - smu_phase_det_fops_##param##_set, "%llu\n") -#endif DEBUGFS_PHASE_DET_FOPS(LO_FREQ); DEBUGFS_PHASE_DET_FOPS(HI_FREQ); @@ -4241,21 +4212,11 @@ DEBUGFS_PHASE_DET_FOPS(THRESH); DEBUGFS_PHASE_DET_FOPS(ALPHA); DEBUGFS_PHASE_DET_FOPS(HYST); -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, smu_phase_det_debugfs_enable, "%llu\n"); -#else -DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, - smu_phase_det_debugfs_enable, "%llu\n"); -#endif -#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_res, smu_phase_det_debugfs_get_residency, NULL, "%llu\n"); -#else -DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_res, - smu_phase_det_debugfs_get_residency, NULL, "%llu\n"); -#endif #define DEBUGFS_CREATE_PHASE_DET_ATTR(name, param) \ debugfs_create_file(#name, 0644, dir, smu, &smu_phase_det_fops_##param) diff --git a/include/kcl/kcl_debugfs.h b/include/kcl/kcl_debugfs.h index ca6a8d391da78..75a68ada50ccc 100644 --- a/include/kcl/kcl_debugfs.h +++ b/include/kcl/kcl_debugfs.h @@ -19,8 +19,10 @@ #include #include -#if defined(DEFINE_DEBUGFS_ATTRIBUTE) && !defined(DEFINE_DEBUGFS_ATTRIBUTE_SIGNED) -#define KCL_FAKE_DEBUGFS_ATTRIBUTE_SIGNED +#if !defined(DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED) + +#ifdef DEFINE_DEBUGFS_ATTRIBUTE +#define KCL_FAKE_DEBUGFS_ATTRIBUTE_XSIGNED #define DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, __is_signed) \ static int __fops ## _open(struct inode *inode, struct file *file) \ { \ @@ -36,6 +38,10 @@ static const struct file_operations __fops = { \ .llseek = no_llseek, \ } +#undef DEFINE_DEBUGFS_ATTRIBUTE +#define DEFINE_DEBUGFS_ATTRIBUTE(__fops, __get, __set, __fmt) \ + DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, false) + #define DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(__fops, __get, __set, __fmt) \ DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, true) @@ -51,6 +57,18 @@ static inline ssize_t debugfs_attr_write_signed(struct file *file, } #endif /* CONFIG_DEBUG_FS */ +#else +#define DEFINE_DEBUGFS_ATTRIBUTE DEFINE_SIMPLE_ATTRIBUTE +#define DEFINE_DEBUGFS_ATTRIBUTE_SIGNED DEFINE_SIMPLE_ATTRIBUTE +static inline struct dentry *debugfs_create_file_unsafe(const char *name, + umode_t mode, struct dentry *parent, + void *data, + const struct file_operations *fops) +{ + return ERR_PTR(-ENODEV); +} +#endif /* DEFINE_DEBUGFS_ATTRIBUTE */ + #endif /* DEFINE_DEBUGFS_ATTRIBUTE_SIGNED */ #endif From 0f12417a39519f75708188e419e73294980a83a6 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 25 Dec 2024 15:25:04 +0800 Subject: [PATCH 1385/2653] drm/amdkcl: split previous sanity check to Makefile Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 12 ------------ drivers/gpu/drm/amd/dkms/Makefile | 12 ++++++++++++ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index 6153df061bcd8..5af98db3e5580 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -34,18 +34,6 @@ $(error "The GCC is too old for this kernel, please update the GCC to higher tha endif endif -ifndef CONFIG_DRM -$(error CONFIG_DRM disabled, exit...) -endif - -ifeq (y,$(CONFIG_DRM_AMDGPU)) -$(error DRM_AMDGPU is built-in, exit...) -endif - -ifndef CONFIG_KALLSYMS -$(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) -endif - _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 59d814c49e8e3..332b2796f0ff1 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -17,6 +17,18 @@ endif include $(kernel_build_dir)/include/config/auto.conf +ifndef CONFIG_DRM +$(error CONFIG_DRM disabled, exit...) +endif + +ifeq (y,$(CONFIG_DRM_AMDGPU_AMDKCL)) +$(error DRM_AMDGPU is built-in, exit...) +endif + +ifndef CONFIG_KALLSYMS +$(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) +endif + ifneq ($(CONFIG_CC_IS_CLANG),) module_build_flags += CC=clang endif From d8bb6963a589be5ddcca08754b9d0538be7c5b6e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 25 Dec 2024 15:25:58 +0800 Subject: [PATCH 1386/2653] drm/amdkcl: Set modules as default target Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 332b2796f0ff1..46c5694210b41 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -14,6 +14,7 @@ $(error "invalid kernel obj dir, is kernel-devel installed?") endif .PHONY: modules pre-build clean +modules: include $(kernel_build_dir)/include/config/auto.conf From 8b6f3cd68f45939d5cabeefa154c49141195a70a Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 30 Dec 2024 11:13:46 +0800 Subject: [PATCH 1387/2653] drm/amdkcl: Remove redundant DEFINE_DEBUGFS_ATTRIBUTE macro define The legacy definition of DEFINE_DEBUGFS_ATTRIBUTE is semantically equivalent to DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, false), so remove unnecessary redefinitions. Signed-off-by: chengjya Reviewed-by: Bob Zhou --- include/kcl/kcl_debugfs.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/kcl/kcl_debugfs.h b/include/kcl/kcl_debugfs.h index 75a68ada50ccc..f9444191d7cec 100644 --- a/include/kcl/kcl_debugfs.h +++ b/include/kcl/kcl_debugfs.h @@ -38,10 +38,6 @@ static const struct file_operations __fops = { \ .llseek = no_llseek, \ } -#undef DEFINE_DEBUGFS_ATTRIBUTE -#define DEFINE_DEBUGFS_ATTRIBUTE(__fops, __get, __set, __fmt) \ - DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, false) - #define DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(__fops, __get, __set, __fmt) \ DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, true) From d5d0e476a4e07f00a7be7914a1342ea953c2307a Mon Sep 17 00:00:00 2001 From: chengjya Date: Thu, 2 Jan 2025 11:57:32 +0800 Subject: [PATCH 1388/2653] Revert "drm/amdkfd: Improve signal event slow path" This reverts commit 5c3bfeb6e5bf1014cf9450edbf2d21c51fa67816. The reverted patche causes Jira issue SWDEV-506499. Signed-off-by: chengjya --- drivers/gpu/drm/amd/amdkfd/kfd_events.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index 766b061d9fd98..4be85487983a1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -760,16 +760,6 @@ void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, uint64_t *slots = page_slots(p->signal_page); uint32_t id; - /* - * If id is valid but slot is not signaled, GPU may signal the same event twice - * before driver have chance to process the first interrupt, then signal slot is - * auto-reset after set_event wakeup the user space, just drop the second event as - * the application only need wakeup once. - */ - if ((valid_id_bits > 31 || (1U << valid_id_bits) >= KFD_SIGNAL_EVENT_LIMIT) && - partial_id < KFD_SIGNAL_EVENT_LIMIT && slots[partial_id] == UNSIGNALED_EVENT_SLOT) - goto out_unlock; - if (valid_id_bits) pr_debug_ratelimited("Partial ID invalid: %u (%u valid bits)\n", partial_id, valid_id_bits); @@ -798,7 +788,6 @@ void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, } } -out_unlock: rcu_read_unlock(); kfd_unref_process(p); } From 36c7e000c6d27d7fd8e6a4db1cb778a23d29f704 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 30 Dec 2024 10:59:59 +0800 Subject: [PATCH 1389/2653] drm/amdkcl: split kcl config sanity check to Makefile Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 8 -------- drivers/gpu/drm/amd/dkms/Makefile | 11 +++++++++-- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index 5af98db3e5580..0821ba268d9a4 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -36,14 +36,6 @@ endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") -ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) -$(error dma_resv->seq is missing. exit...) -endif - -ifeq ($(call _is_kcl_macro_defined,HAVE_RESERVATION_WW_CLASS_BUG),y) -$(error reservation_ww_class is missing. exit...) -endif - DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 46c5694210b41..abb5fa4da4920 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -13,7 +13,7 @@ ifeq ($(wildcard $(kernel_build_dir)/include/config/auto.conf),) $(error "invalid kernel obj dir, is kernel-devel installed?") endif -.PHONY: modules pre-build clean +.PHONY: modules sanity-check pre-build clean modules: include $(kernel_build_dir)/include/config/auto.conf @@ -37,7 +37,10 @@ ifneq ($(CONFIG_LD_IS_LLD),) module_build_flags += LD=ld.lld endif -modules:pre-build +config-file ?= amd/dkms/config/config.h +KCL_MACRO_CHECK_COMMAND=$(shell grep $(1) $(config-file) | grep -q "define" && echo "y") + +modules: sanity-check $(Q)$(shell cat $(module_build_dir)/.env) make -j$(num_cpu_cores) \ TTM_NAME=amdttm \ SCHED_NAME=amd-sched \ @@ -45,6 +48,10 @@ modules:pre-build M=$(module_build_dir) $(module_build_flags) $(Q)amd/dkms/post-build.sh $(module_build_dir) +sanity-check: pre-build $(config-file) + $(if $(call KCL_MACRO_CHECK_COMMAND, HAVE_DMA_RESV_SEQ_BUG), $(error dma_resv->seq is missing. exit...)) + $(if $(call KCL_MACRO_CHECK_COMMAND, HAVE_RESERVATION_WW_CLASS_BUG), $(error reservation_ww_class is missing. exit...)) + pre-build: $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(module_build_dir) From 77cf7e0d14e7b6ef92ca2b94329f4834f23f2ee4 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 3 Jan 2025 15:27:59 +0800 Subject: [PATCH 1390/2653] drm/amdkcl: update config.h for unused-variable By relaxing unused-variable error, some m4 config need to update Signed-off-by: Bob Zhou Reviewed-by: chengjya --- drivers/gpu/drm/amd/dkms/config/config.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 723a64ee7c2b3..cf46698c2bc77 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -649,7 +649,7 @@ #define HAVE_DRM_TASK_BARRIER_H 1 /* drm_vblank_crtc_config is available */ -/* #undef HAVE_DRM_VBLANK_CRTC_CONFIG */ +#define HAVE_DRM_VBLANK_CRTC_CONFIG 1 /* struct drm_vma_offset_node has readonly field */ /* #undef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD */ @@ -1005,6 +1005,9 @@ /* seq_hex_dump() is available */ #define HAVE_SEQ_HEX_DUMP 1 +/* sg_alloc_table_from_pages_segment() is available */ +#define HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT 1 + /* shrinker_register() is available */ #define HAVE_SHRINKER_REGISTER 1 @@ -1014,9 +1017,6 @@ /* whether smca_get_bank_type(x, x) is available */ #define HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS 1 -/* whether sg_alloc_table_from_pages_segment() is available */ -#define HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT 1 - /* enum SMCA_UMC_V2 is available */ #define HAVE_SMCA_UMC_V2 1 From dd817bc128289ff969ef75d8aac550dd2081b4ba Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 3 Jan 2025 13:28:14 +0800 Subject: [PATCH 1391/2653] drm/amdkcl: update header macro to avoid repeat The macro is repeated by kcl/backport/kcl_drm_drv.h, so modify the header macro. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/backport/kcl_drm_fbdev_ttm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/kcl/backport/kcl_drm_fbdev_ttm.h b/include/kcl/backport/kcl_drm_fbdev_ttm.h index 03ddc7699ddb1..5d504414c4478 100644 --- a/include/kcl/backport/kcl_drm_fbdev_ttm.h +++ b/include/kcl/backport/kcl_drm_fbdev_ttm.h @@ -1,5 +1,5 @@ -#ifndef __KCL_BACKPORT_KCL_DRM_DRV_H_ -#define __KCL_BACKPORT_KCL_DRM_DRV_H__ +#ifndef __KCL_BACKPORT_KCL_DRM_FBDEV_TTM_H__ +#define __KCL_BACKPORT_KCL_DRM_FBDEV_TTM_H__ #include #include From a34c5512c1a443b654c5a1cff373ce0e0ea714c1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 3 Jan 2025 13:39:00 +0800 Subject: [PATCH 1392/2653] drm/amdkcl: initiate return result for non-upsteam In special case, uninitialized result will cause error, so fix it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index 5a8538691ebd1..52cc184613f21 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -54,15 +54,15 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, int xcc_id, struct amdgpu_vm *vm, u64 gpu_addr, u32 size) { struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; - int r; + int r = 0; if (!adev->gfx.rlc.funcs->update_spm_vmid) return -EINVAL; if (!vm->reserved_vmid[AMDGPU_GFXHUB(0)]) { r = amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0)); - if (r) - return r; + if (r) + return r; vm->reserved_vmid[AMDGPU_GFXHUB(0)] = true; } From 381636c1d12884f2b8777498552aa7081bcdfd17 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Tue, 17 Dec 2024 16:04:14 -0500 Subject: [PATCH 1393/2653] drm/kfd: use support format check flag kfd_pc_sample_info flag is for OUT only, so user input format flag should not be used to check condition. -v2: fix typo Signed-off-by: James Zhu Reviewed-by: Joseph Greathouse --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 603e557c986b4..80a185ba10b60 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -285,12 +285,6 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, return -EFAULT; } - if (user_info.flags & KFD_IOCTL_PCS_FLAG_POWER_OF_2 && - user_info.interval & (user_info.interval - 1)) { - pr_debug("Sampling interval's power is unmatched!"); - return -EINVAL; - } - for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version && user_info.method == supported_formats[i].sample_info->method @@ -308,6 +302,12 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, return -EOPNOTSUPP; } + if (supported_format->flags == KFD_IOCTL_PCS_FLAG_POWER_OF_2 && + user_info.interval & (user_info.interval - 1)) { + pr_debug("Sampling interval's power is unmatched!"); + return -EINVAL; + } + mutex_lock(&pdd->dev->pcs_data.mutex); if (pdd->dev->pcs_data.hosttrap_entry.base.use_count && memcmp(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, From 59fc07facabb3e249206b03ba349f31bdf5b6673 Mon Sep 17 00:00:00 2001 From: Benjamin Welton Date: Mon, 6 Jan 2025 10:30:01 -0800 Subject: [PATCH 1394/2653] amd/amdkfd: fix double lock aquisition in set_perfcount Seperates out locking from update_queue to allow updating of queues by code already holding the mqd lock. Fixes a hang in set_perfcount. This change was in the original mailing list commit for set_perfcount but was not included in gerrit. Fixes: b58289f0abf7 ("Add kfd_ioctl_profiler to contain profiler kernel driver changes") Signed-off-by: Benjamin Welton Acked-by: Kent Russell Change-Id: Ica4a5881c357a67dfe0922b39574e25f07718687 --- .../drm/amd/amdkfd/kfd_device_queue_manager.c | 74 ++++++++++--------- 1 file changed, 40 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 928bc08744877..223001cbea185 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -326,29 +326,6 @@ static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, return r; } -static void set_perfcount(struct device_queue_manager *dqm, int enable) -{ - struct device_process_node *cur; - struct qcm_process_device *qpd; - struct queue *q; - struct mqd_update_info minfo = { 0 }; - - if (!dqm) - return; - - minfo.update_flag = (enable == 1 ? UPDATE_FLAG_PERFCOUNT_ENABLE : - UPDATE_FLAG_PERFCOUNT_DISABLE); - dqm_lock(dqm); - list_for_each_entry(cur, &dqm->queues, list) { - qpd = cur->qpd; - list_for_each_entry(q, &qpd->queues_list, list) { - pqm_update_mqd(qpd->pqm, q->properties.queue_id, - &minfo); - } - } - dqm_unlock(dqm); -} - static int remove_all_kfd_queues_mes(struct device_queue_manager *dqm) { struct device_process_node *cur; @@ -989,7 +966,7 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm, return retval; } -static int update_queue(struct device_queue_manager *dqm, struct queue *q, +static int update_queue_locked(struct device_queue_manager *dqm, struct queue *q, struct mqd_update_info *minfo) { int retval = 0; @@ -998,11 +975,9 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q, struct kfd_process_device *pdd; bool prev_active = false; - dqm_lock(dqm); pdd = kfd_get_process_device_data(q->device, q->process); if (!pdd) { - retval = -ENODEV; - goto out_unlock; + return -ENODEV; } mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( q->properties.type)]; @@ -1020,13 +995,12 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q, /* queue is reset so inaccessable */ if (pdd->has_reset_queue) { - retval = -EACCES; - goto out_unlock; + return -EACCES; } if (retval) { dev_err(dev, "unmap queue failed\n"); - goto out_unlock; + return retval; } } else if (prev_active && (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || @@ -1035,7 +1009,7 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q, if (!dqm->sched_running) { WARN_ONCE(1, "Update non-HWS queue while stopped\n"); - goto out_unlock; + return retval; } retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, @@ -1045,7 +1019,7 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q, KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); if (retval) { dev_err(dev, "destroy mqd failed\n"); - goto out_unlock; + return retval; } } @@ -1093,11 +1067,43 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q, &q->properties, current->mm); } -out_unlock: - dqm_unlock(dqm); return retval; } +static int update_queue(struct device_queue_manager *dqm, struct queue *q, + struct mqd_update_info *minfo) +{ + int retval; + + dqm_lock(dqm); + retval = update_queue_locked(dqm, q, minfo); + dqm_unlock(dqm); + + return retval; +} + +static void set_perfcount(struct device_queue_manager *dqm, int enable) +{ + struct device_process_node *cur; + struct qcm_process_device *qpd; + struct queue *q; + struct mqd_update_info minfo = { 0 }; + + if (!dqm) + return; + + minfo.update_flag = (enable == 1 ? UPDATE_FLAG_PERFCOUNT_ENABLE : + UPDATE_FLAG_PERFCOUNT_DISABLE); + dqm_lock(dqm); + list_for_each_entry(cur, &dqm->queues, list) { + qpd = cur->qpd; + list_for_each_entry(q, &qpd->queues_list, list) { + update_queue_locked(dqm, q, &minfo); + } + } + dqm_unlock(dqm); +} + /* suspend_single_queue does not lock the dqm like the * evict_process_queues_cpsch or evict_process_queues_nocpsch. You should * lock the dqm before calling, and unlock after calling. From 201e5dbe691c5e10e5c8480842795d2a613838a3 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 25 Jul 2024 09:34:59 -0400 Subject: [PATCH 1395/2653] drm/amdkfd: refactor for adding stochastic PC sampling Share sampling_idr to support both Host Trap and Stochastic PC sampling running simultaneously. Signed-off-by: James Zhu Reviewed-by: Vladimir Indic Acked-by: Shweta Khatri --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 +-- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 32 ++++++++++---------- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 8 ++--- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index a26588ee9b6ec..00d37b89779a1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -619,12 +619,12 @@ static void kfd_smi_init(struct kfd_node *dev) static void kfd_pc_sampling_init(struct kfd_node *dev) { mutex_init(&dev->pcs_data.mutex); - idr_init_base(&dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, 1); + idr_init_base(&dev->pcs_data.sampling_idr, 1); } static void kfd_pc_sampling_exit(struct kfd_node *dev) { - idr_destroy(&dev->pcs_data.hosttrap_entry.base.pc_sampling_idr); + idr_destroy(&dev->pcs_data.sampling_idr); mutex_destroy(&dev->pcs_data.mutex); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 80a185ba10b60..7a78592fe450a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -85,14 +85,14 @@ static int kfd_pc_sample_thread(void *param) node->kfd2kgd->override_core_cg(adev, 1, inst); while (!kthread_should_stop() && - !signal_pending(node->pcs_data.hosttrap_entry.base.pc_sample_thread)) { + !signal_pending(node->pcs_data.hosttrap_entry.pc_sample_thread)) { if (!need_wait) { next_trap_time = ktime_add_us(ktime_get_raw(), timeout); for_each_inst(inst, node->xcc_mask) { node->kfd2kgd->trigger_pc_sample_trap(adev, node->vm_info.last_vmid_kfd, - &node->pcs_data.hosttrap_entry.base.target_simd, - &node->pcs_data.hosttrap_entry.base.target_wave_slot, + &node->pcs_data.hosttrap_entry.target_simd, + &node->pcs_data.hosttrap_entry.target_wave_slot, node->pcs_data.hosttrap_entry.base.pc_sample_info.method, inst); } @@ -118,9 +118,9 @@ static int kfd_pc_sample_thread(void *param) for_each_inst(inst, node->xcc_mask) node->kfd2kgd->override_core_cg(adev, 0, inst); - node->pcs_data.hosttrap_entry.base.target_simd = 0; - node->pcs_data.hosttrap_entry.base.target_wave_slot = 0; - node->pcs_data.hosttrap_entry.base.pc_sample_thread = NULL; + node->pcs_data.hosttrap_entry.target_simd = 0; + node->pcs_data.hosttrap_entry.target_wave_slot = 0; + node->pcs_data.hosttrap_entry.pc_sample_thread = NULL; return 0; } @@ -131,12 +131,12 @@ static int kfd_pc_sample_thread_start(struct kfd_node *node) int ret = 0; snprintf(thread_name, 16, "pcs_%d", node->adev->ddev.render->index); - node->pcs_data.hosttrap_entry.base.pc_sample_thread = + node->pcs_data.hosttrap_entry.pc_sample_thread = kthread_run(kfd_pc_sample_thread, node, thread_name); - if (IS_ERR(node->pcs_data.hosttrap_entry.base.pc_sample_thread)) { - ret = PTR_ERR(node->pcs_data.hosttrap_entry.base.pc_sample_thread); - node->pcs_data.hosttrap_entry.base.pc_sample_thread = NULL; + if (IS_ERR(node->pcs_data.hosttrap_entry.pc_sample_thread)) { + ret = PTR_ERR(node->pcs_data.hosttrap_entry.pc_sample_thread); + node->pcs_data.hosttrap_entry.pc_sample_thread = NULL; pr_debug("Failed to create pc sample thread for %s with ret = %d.", thread_name, ret); } @@ -231,7 +231,7 @@ static int kfd_pc_sample_start(struct kfd_process_device *pdd, while (pc_sampling_start) { /* true means pc_sample_thread stop is in progress */ - if (READ_ONCE(pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_thread)) { + if (READ_ONCE(pdd->dev->pcs_data.hosttrap_entry.pc_sample_thread)) { usleep_range(1000, 2000); } else { ret = kfd_pc_sample_thread_start(pdd->dev); @@ -261,7 +261,7 @@ static int kfd_pc_sample_stop(struct kfd_process_device *pdd, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); if (pc_sampling_stop) - kthread_stop(pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_thread); + kthread_stop(pdd->dev->pcs_data.hosttrap_entry.pc_sample_thread); return 0; } @@ -325,7 +325,7 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, return -ENOMEM; } - i = idr_alloc_cyclic(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, + i = idr_alloc_cyclic(&pdd->dev->pcs_data.sampling_idr, pcs_entry, 1, 0, GFP_KERNEL); if (i < 0) { mutex_unlock(&pdd->dev->pcs_data.mutex); @@ -364,7 +364,7 @@ static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_ pdd->process->pc_sampling_ref--; mutex_lock(&pdd->dev->pcs_data.mutex); pdd->dev->pcs_data.hosttrap_entry.base.use_count--; - idr_remove(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, trace_id); + idr_remove(&pdd->dev->pcs_data.sampling_idr, trace_id); if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) memset(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, 0x0, @@ -383,7 +383,7 @@ void kfd_pc_sample_release(struct kfd_process_device *pdd) uint32_t id; /* force to release all PC sampling task for this process */ - idp = &pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr; + idp = &pdd->dev->pcs_data.sampling_idr; do { pcs_entry = NULL; mutex_lock(&pdd->dev->pcs_data.mutex); @@ -410,7 +410,7 @@ int kfd_pc_sample(struct kfd_process_device *pdd, args->op != KFD_IOCTL_PCS_OP_CREATE) { mutex_lock(&pdd->dev->pcs_data.mutex); - pcs_entry = idr_find(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, + pcs_entry = idr_find(&pdd->dev->pcs_data.sampling_idr, args->trace_id); mutex_unlock(&pdd->dev->pcs_data.mutex); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 9fdb869209e30..2cf20597cb4b4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -289,20 +289,20 @@ struct kfd_dev; struct kfd_dev_pc_sampling_data { uint32_t use_count; /* Num of PC sampling sessions */ uint32_t active_count; /* Num of active sessions */ - uint32_t target_simd; /* target simd for trap */ - uint32_t target_wave_slot; /* target wave slot for trap */ - struct idr pc_sampling_idr; - struct task_struct *pc_sample_thread; struct kfd_pc_sample_info pc_sample_info; }; struct kfd_dev_pcs_hosttrap { struct kfd_dev_pc_sampling_data base; + uint32_t target_simd; /* target simd for trap */ + uint32_t target_wave_slot; /* target wave slot for trap */ + struct task_struct *pc_sample_thread; }; /* Per device PC Sampling data */ struct kfd_dev_pc_sampling { struct mutex mutex; + struct idr sampling_idr; struct kfd_dev_pcs_hosttrap hosttrap_entry; }; From f08fc47402110169e1659d1608aa452ac7cffb59 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 25 Jul 2024 09:49:45 -0400 Subject: [PATCH 1396/2653] drm/amdkfd: add interface setup_stoch_sampling To support gfx943 stochastic PC sampling. -v3: use compute_vmid_bitmap instead of hardcode -v7: move interval conversion into soc specified code Signed-off-by: James Zhu Reviewed-by: Vladimir Indic Reviewed-by: Shweta Khatri --- .../drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 27 ++++++++++++++++++- .../gpu/drm/amd/include/kgd_kfd_interface.h | 6 +++++ 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c index c1c184babcaf3..a577e1ff00401 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c @@ -550,6 +550,30 @@ static uint32_t kgd_v9_4_3_trigger_pc_sample_trap(struct amdgpu_device *adev, target_simd, target_wave_slot, method, inst); } +static uint32_t kgd_v9_4_3_setup_stoch_sampling(struct amdgpu_device *adev, + uint32_t compute_vmid_bitmap, + bool enable, + enum kfd_ioctl_pc_sample_type type, + uint64_t intval, + uint32_t inst) +{ + uint32_t value = 0; + + /* turn on all VMID for this instance */ + value = REG_SET_FIELD(value, SQ_PERF_SNAPSHOT_CTRL, VMID_MASK, compute_vmid_bitmap); + + value = REG_SET_FIELD(value, SQ_PERF_SNAPSHOT_CTRL, COUNT_INTVAL, ffs(intval >> 9)); + value = REG_SET_FIELD(value, SQ_PERF_SNAPSHOT_CTRL, COUNT_SEL, type - 1); + value = REG_SET_FIELD(value, SQ_PERF_SNAPSHOT_CTRL, ENABLE, enable); + + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + WREG32_SOC15(GC, GET_INST(GC, inst), regSQ_PERF_SNAPSHOT_CTRL, value); + mutex_unlock(&adev->grbm_idx_mutex); + + return 0; +} + const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_gfx_v9_4_3_set_pasid_vmid_mapping, @@ -587,5 +611,6 @@ const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .hqd_reset = kgd_gfx_v9_hqd_reset, .hqd_sdma_get_doorbell = kgd_gfx_v9_4_3_hqd_sdma_get_doorbell, .trigger_pc_sample_trap = kgd_v9_4_3_trigger_pc_sample_trap, - .override_core_cg = kgd_gfx_v9_4_3_override_core_cg + .override_core_cg = kgd_gfx_v9_4_3_override_core_cg, + .setup_stoch_sampling = kgd_v9_4_3_setup_stoch_sampling, }; diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 26f5a542877cc..df5b578a5e6b1 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -349,6 +349,12 @@ struct kfd2kgd_calls { void (*override_core_cg)(struct amdgpu_device *adev, uint32_t value, uint32_t inst); + uint32_t (*setup_stoch_sampling)(struct amdgpu_device *adev, + uint32_t compute_vmid_bitmap, + bool enable, + enum kfd_ioctl_pc_sample_type type, + uint64_t intval, + uint32_t inst); }; #endif /* KGD_KFD_INTERFACE_H_INCLUDED */ From 575047b4549b65f3edb15bd1f1da26d3083f4829 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 25 Jul 2024 13:01:57 -0400 Subject: [PATCH 1397/2653] drm/amdkfd: add stochastic PC sampling support Add stochastic PC sampling support. -v3: use compute_vmid_bitmap instead of hardcode -v4: use clock cycles instead of the exponent of clock cycle -v5: use KFD_IOCTL_PCS_FLAG_POWER_OF_2 subtract 8 before pass clock cycle exponent value to register -v6: use shift instead of subtract -v7: move interval conversion into soc specified code Signed-off-by: James Zhu Reviewed-by: Vladimir Indic Acked-by: Shweta Khatri --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 173 ++++++++++++++----- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 6 + 2 files changed, 137 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 7a78592fe450a..e8addf8817d9d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -27,6 +27,7 @@ #include "kfd_debug.h" #include "kfd_device_queue_manager.h" +#include /* * PC Sampling revision change log * @@ -45,6 +46,10 @@ struct supported_pc_sample_info { const struct kfd_pc_sample_info sample_info_hosttrap_9_0_0 = { 0, 1, ~0ULL, 0, KFD_IOCTL_PCS_METHOD_HOSTTRAP, KFD_IOCTL_PCS_TYPE_TIME_US }; +const struct kfd_pc_sample_info sample_info_stoch_cycle_9_4_3 = { + 0, 256, (1ULL << 31), KFD_IOCTL_PCS_FLAG_POWER_OF_2, + KFD_IOCTL_PCS_METHOD_STOCHASTIC, KFD_IOCTL_PCS_TYPE_CLOCK_CYCLES }; + struct supported_pc_sample_info supported_formats[] = { { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 4, 3), &sample_info_hosttrap_9_0_0 }, @@ -169,14 +174,30 @@ static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, ret = 0; mutex_lock(&pdd->dev->pcs_data.mutex); if (user_args->flags != KFD_IOCTL_PCS_QUERY_TYPE_FULL && - pdd->dev->pcs_data.hosttrap_entry.base.use_count) { + (pdd->dev->pcs_data.hosttrap_entry.base.use_count || + pdd->dev->pcs_data.stoch_entry.base.use_count)) { + user_args->num_sample_info = 0; + /* If we already have a session, restrict returned list to current method */ - user_args->num_sample_info = 1; + if (pdd->dev->pcs_data.stoch_entry.base.use_count) { + user_args->num_sample_info++; + if (user_args->sample_info_ptr && + user_args->num_sample_info <= user_num_sample_info) { + ret = copy_to_user((void __user *) user_args->sample_info_ptr, + &pdd->dev->pcs_data.stoch_entry.base.pc_sample_info, + sizeof(struct kfd_pc_sample_info)); + user_args->sample_info_ptr += sizeof(struct kfd_pc_sample_info); + } + } - if (user_args->sample_info_ptr) - ret = copy_to_user((void __user *) user_args->sample_info_ptr, - &pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, - sizeof(struct kfd_pc_sample_info)); + if (pdd->dev->pcs_data.hosttrap_entry.base.use_count) { + user_args->num_sample_info++; + if (user_args->sample_info_ptr && + user_args->num_sample_info <= user_num_sample_info) + ret |= copy_to_user((void __user *) user_args->sample_info_ptr, + &pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, + sizeof(struct kfd_pc_sample_info)); + } mutex_unlock(&pdd->dev->pcs_data.mutex); return ret ? -EFAULT : 0; } @@ -220,25 +241,47 @@ static int kfd_pc_sample_start(struct kfd_process_device *pdd, pcs_entry->enabled = true; mutex_lock(&pdd->dev->pcs_data.mutex); - kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, - pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info.method, true); + kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, pcs_entry->method, true); + + if (pcs_entry->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) + pc_sampling_start = true; - if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) - pc_sampling_start = true; + pdd->dev->pcs_data.hosttrap_entry.base.active_count++; + } else { /* KFD_IOCTL_PCS_METHOD_STOCHASTIC */ + if (!pdd->dev->pcs_data.stoch_entry.base.active_count) + pc_sampling_start = true; - pdd->dev->pcs_data.hosttrap_entry.base.active_count++; + pdd->dev->pcs_data.stoch_entry.base.active_count++; + } mutex_unlock(&pdd->dev->pcs_data.mutex); while (pc_sampling_start) { - /* true means pc_sample_thread stop is in progress */ - if (READ_ONCE(pdd->dev->pcs_data.hosttrap_entry.pc_sample_thread)) { - usleep_range(1000, 2000); - } else { - ret = kfd_pc_sample_thread_start(pdd->dev); + if (pcs_entry->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + /* true means pc_sample_thread stop is in progress */ + if (READ_ONCE(pdd->dev->pcs_data.hosttrap_entry.pc_sample_thread)) { + usleep_range(1000, 2000); + } else { + ret = kfd_pc_sample_thread_start(pdd->dev); + break; + } + } else {/* KFD_IOCTL_PCS_METHOD_STOCHASTIC */ + struct amdgpu_device *adev = pdd->dev->adev; + struct kfd_node *node = pdd->dev; + uint64_t interval; + uint32_t inst; + + interval = node->pcs_data.stoch_entry.base.pc_sample_info.interval; + if (pdd->dev->kfd2kgd->setup_stoch_sampling) + for_each_inst(inst, node->xcc_mask) + pdd->dev->kfd2kgd->setup_stoch_sampling(adev, + node->compute_vmid_bitmap, true, + node->pcs_data.stoch_entry.base.pc_sample_info.type, + interval, + inst); break; } } - return ret; } @@ -249,19 +292,38 @@ static int kfd_pc_sample_stop(struct kfd_process_device *pdd, pcs_entry->enabled = false; mutex_lock(&pdd->dev->pcs_data.mutex); - pdd->dev->pcs_data.hosttrap_entry.base.active_count--; - if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) - pc_sampling_stop = true; - + if (pcs_entry->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + pdd->dev->pcs_data.hosttrap_entry.base.active_count--; + if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) + pc_sampling_stop = true; + } else {/* KFD_IOCTL_PCS_METHOD_STOCHASTIC */ + pdd->dev->pcs_data.stoch_entry.base.active_count--; + if (!pdd->dev->pcs_data.stoch_entry.base.active_count) + pc_sampling_stop = true; + } mutex_unlock(&pdd->dev->pcs_data.mutex); - kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, - pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info.method, false); + kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, pcs_entry->method, false); remap_queue(pdd->dev->dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); - if (pc_sampling_stop) - kthread_stop(pdd->dev->pcs_data.hosttrap_entry.pc_sample_thread); + if (pc_sampling_stop) { + if (pcs_entry->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + kthread_stop(pdd->dev->pcs_data.hosttrap_entry.pc_sample_thread); + } else {/* KFD_IOCTL_PCS_METHOD_STOCHASTIC */ + struct amdgpu_device *adev = pdd->dev->adev; + struct kfd_node *node = pdd->dev; + uint32_t inst; + + if (pdd->dev->kfd2kgd->setup_stoch_sampling) { + for_each_inst(inst, node->xcc_mask) + pdd->dev->kfd2kgd->setup_stoch_sampling(adev, + node->compute_vmid_bitmap, false, + node->pcs_data.stoch_entry.base.pc_sample_info.type, + 0, inst); + } + } + } return 0; } @@ -309,14 +371,26 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, } mutex_lock(&pdd->dev->pcs_data.mutex); - if (pdd->dev->pcs_data.hosttrap_entry.base.use_count && - memcmp(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, - &user_info, sizeof(user_info))) { - ret = copy_to_user((void __user *) user_args->sample_info_ptr, - &pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, - sizeof(struct kfd_pc_sample_info)); - mutex_unlock(&pdd->dev->pcs_data.mutex); - return ret ? -EFAULT : -EEXIST; + if (supported_format->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + if (pdd->dev->pcs_data.hosttrap_entry.base.use_count && + memcmp(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, + &user_info, sizeof(user_info))) { + ret = copy_to_user((void __user *) user_args->sample_info_ptr, + &pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, + sizeof(struct kfd_pc_sample_info)); + mutex_unlock(&pdd->dev->pcs_data.mutex); + return ret ? -EFAULT : -EEXIST; + } + } else { /* KFD_IOCTL_PCS_METHOD_STOCHASTIC */ + if (pdd->dev->pcs_data.stoch_entry.base.use_count && + memcmp(&pdd->dev->pcs_data.stoch_entry.base.pc_sample_info, + &user_info, sizeof(user_info))) { + ret = copy_to_user((void __user *) user_args->sample_info_ptr, + &pdd->dev->pcs_data.stoch_entry.base.pc_sample_info, + sizeof(struct kfd_pc_sample_info)); + mutex_unlock(&pdd->dev->pcs_data.mutex); + return ret ? -EFAULT : -EEXIST; + } } pcs_entry = kzalloc(sizeof(*pcs_entry), GFP_KERNEL); @@ -333,13 +407,20 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, return i; } - if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) - pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info = user_info; + if (supported_format->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) + pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info = user_info; + pdd->dev->pcs_data.hosttrap_entry.base.use_count++; + } else if (supported_format->method == KFD_IOCTL_PCS_METHOD_STOCHASTIC) { + if (!pdd->dev->pcs_data.stoch_entry.base.use_count) + pdd->dev->pcs_data.stoch_entry.base.pc_sample_info = user_info; + pdd->dev->pcs_data.stoch_entry.base.use_count++; + } - pdd->dev->pcs_data.hosttrap_entry.base.use_count++; mutex_unlock(&pdd->dev->pcs_data.mutex); pcs_entry->pdd = pdd; + pcs_entry->method = supported_format->method; user_args->trace_id = (uint32_t)i; /* @@ -350,7 +431,8 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, kfd_dbg_enable_ttmp_setup(pdd->process); pdd->process->pc_sampling_ref++; - pr_debug("alloc pcs_entry = %p, trace_id = 0x%x on gpu 0x%x", pcs_entry, i, pdd->dev->id); + pr_debug("alloc pcs_entry = %p, trace_id = 0x%x method = %d on gpu 0x%x", + pcs_entry, i, pcs_entry->method, pdd->dev->id); return 0; } @@ -363,12 +445,19 @@ static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_ pdd->process->pc_sampling_ref--; mutex_lock(&pdd->dev->pcs_data.mutex); - pdd->dev->pcs_data.hosttrap_entry.base.use_count--; - idr_remove(&pdd->dev->pcs_data.sampling_idr, trace_id); + if (pcs_entry->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + pdd->dev->pcs_data.hosttrap_entry.base.use_count--; + if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) + memset(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, 0x0, + sizeof(struct kfd_pc_sample_info)); + } else { /* KFD_IOCTL_PCS_METHOD_STOCHASTIC */ + pdd->dev->pcs_data.stoch_entry.base.use_count--; + if (!pdd->dev->pcs_data.stoch_entry.base.use_count) + memset(&pdd->dev->pcs_data.stoch_entry.base.pc_sample_info, 0x0, + sizeof(struct kfd_pc_sample_info)); + } - if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) - memset(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, 0x0, - sizeof(struct kfd_pc_sample_info)); + idr_remove(&pdd->dev->pcs_data.sampling_idr, trace_id); mutex_unlock(&pdd->dev->pcs_data.mutex); kfree(pcs_entry); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 2cf20597cb4b4..9ef202e63d943 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -299,11 +299,16 @@ struct kfd_dev_pcs_hosttrap { struct task_struct *pc_sample_thread; }; +struct kfd_dev_stochastic { + struct kfd_dev_pc_sampling_data base; +}; + /* Per device PC Sampling data */ struct kfd_dev_pc_sampling { struct mutex mutex; struct idr sampling_idr; struct kfd_dev_pcs_hosttrap hosttrap_entry; + struct kfd_dev_stochastic stoch_entry; }; struct kfd_node { @@ -832,6 +837,7 @@ enum kfd_pdd_bound { struct pc_sampling_entry { bool enabled; + enum kfd_ioctl_pc_sample_method method; struct kfd_process_device *pdd; }; From 68f56ab1aac4dd7e3056d21e2c4e1b0082c6d3c8 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 25 Jul 2024 13:14:19 -0400 Subject: [PATCH 1398/2653] drm/amdkfd: enable stochastic PC sampling for gfx943 Enable stochastic PC sampling for gfx943 Signed-off-by: James Zhu Reviewed-by: Vladimir Indic Reviewed-by: Shweta Khatri --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index e8addf8817d9d..1cf02035d326d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -34,9 +34,10 @@ * 0.1 - Initial revision * 0.2 - Support gfx9_4_3 Host Trap PC sampling * 0.3 - Fix gfx9_4_3 SQ hang issue + * 1.1 - Support gfx9_4_3 Stochastic PC sampling */ -#define KFD_IOCTL_PCS_MAJOR_VERSION 0 -#define KFD_IOCTL_PCS_MINOR_VERSION 3 +#define KFD_IOCTL_PCS_MAJOR_VERSION 1 +#define KFD_IOCTL_PCS_MINOR_VERSION 1 struct supported_pc_sample_info { uint32_t ip_version; @@ -53,6 +54,7 @@ const struct kfd_pc_sample_info sample_info_stoch_cycle_9_4_3 = { struct supported_pc_sample_info supported_formats[] = { { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 4, 3), &sample_info_hosttrap_9_0_0 }, + { IP_VERSION(9, 4, 3), &sample_info_stoch_cycle_9_4_3 }, }; static int kfd_pc_sample_thread(void *param) From 2bfbde69fb42bdf1fc9f3c7a511e634af4a82a03 Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 10 Jan 2025 13:24:23 +0800 Subject: [PATCH 1399/2653] drm/amdkcl: test drm_display_info->source_physical_address is available It's caused by the following commit: d2143e3a "drm/amd/display: add CEC notifier to amdgpu driver" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +++- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/struct_drm_display_info.m4 | 17 +++++++++++++++++ 4 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_display_info.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1fc64a827caf9..ce8e2d2491b32 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2792,9 +2792,11 @@ void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector) if (!n) return; - + +#ifdef HAVE_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS cec_notifier_set_phys_addr(n, connector->display_info.source_physical_address); +#endif } static void s3_handle_hdmi_cec(struct drm_device *ddev, bool suspend) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index cf46698c2bc77..3c120903c4bbc 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -305,6 +305,9 @@ /* struct drm_display_info has monitor_range member */ #define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 +/* struct drm_display_info->source_physical_address is available */ +#define HAVE_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS 1 + /* drm_dp_add_payload_part2 has three arguments */ /* #undef HAVE_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7c54b1951ac67..ba546e966f8a9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -259,6 +259,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_SYNCOBJ_ADD_POINT AC_AMDGPU_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT AC_AMDGPU_FIRMWARE_REQUEST_NOWARN + AC_AMDGPU_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_display_info.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_display_info.m4 new file mode 100644 index 0000000000000..87a29c5cd5f4d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_display_info.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.5-rc2-871-g82b599ece3b8 +dnl # drm/edid: parse source physical address +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_display_info *info = NULL; + info->source_physical_address = 0; + ],[ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS, 1, + [struct drm_display_info->source_physical_address is available]) + ]) + ]) +]) From cead0a08a8ee7a2f07055aca1ff8aff40d7cc2ad Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 10 Jan 2025 14:20:35 +0800 Subject: [PATCH 1400/2653] drm/amdkcl: test cec_notifier_conn_register() is available It's caused by the following commit: d2143e3a "drm/amd/display: add CEC notifier to amdgpu driver" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 ++++- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/cec_notifier_conn_register.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/cec_notifier_conn_register.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ce8e2d2491b32..1703ee9ba1529 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7450,8 +7450,9 @@ static void amdgpu_dm_connector_unregister(struct drm_connector *connector) if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) sysfs_remove_group(&connector->kdev->kobj, &amdgpu_group); - +#ifdef HAVE_CEC_NOTIFIER_CONN_REGISTER cec_notifier_conn_unregister(amdgpu_dm_connector->notifier); +#endif drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); } static void amdgpu_dm_connector_destroy(struct drm_connector *connector) @@ -8909,12 +8910,14 @@ int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector) } cec_fill_conn_info_from_drm(&conn_info, &aconnector->base); +#ifdef HAVE_CEC_NOTIFIER_CONN_REGISTER aconnector->notifier = cec_notifier_conn_register(hdmi_dev, NULL, &conn_info); if (!aconnector->notifier) { drm_err(ddev, "Failed to create cec notifier\n"); return -ENOMEM; } +#endif return 0; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 241e877a127cc..c8d954411d0d2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -2907,7 +2907,9 @@ static ssize_t hdmi_cec_state_write(struct file *f, const char __user *buf, } else { if (!aconnector->notifier) return -EINVAL; +#ifdef HAVE_CEC_NOTIFIER_CONN_REGISTER cec_notifier_conn_unregister(aconnector->notifier); +#endif aconnector->notifier = NULL; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3c120903c4bbc..2070d0c08ecac 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -79,6 +79,9 @@ /* cancel_work() is available */ #define HAVE_CANCEL_WORK 1 +/* cec_notifier_conn_register() is available */ +#define HAVE_CEC_NOTIFIER_CONN_REGISTER 1 + /* whether CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL is defined */ #define HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/cec_notifier_conn_register.m4 b/drivers/gpu/drm/amd/dkms/m4/cec_notifier_conn_register.m4 new file mode 100644 index 0000000000000..b672c855b13f7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/cec_notifier_conn_register.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.2-rc5-393-gb48cb35c6a7b +dnl # media: cec-notifier: add new notifier functions +dnl # +AC_DEFUN([AC_AMDGPU_CEC_NOTIFIER_CONN_REGISTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + cec_notifier_conn_register(NULL, NULL, NULL); + ], [cec_notifier_conn_register], [drivers/media/cec/core/cec-notifier.c], [ + AC_DEFINE(HAVE_CEC_NOTIFIER_CONN_REGISTER, 1, + [cec_notifier_conn_register() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ba546e966f8a9..e4531a4c4cbc2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -260,6 +260,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT AC_AMDGPU_FIRMWARE_REQUEST_NOWARN AC_AMDGPU_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS + AC_AMDGPU_CEC_NOTIFIER_CONN_REGISTER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From e1e7ae765b321d9b21001f41c703061d85a0a20d Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 10 Jan 2025 17:23:33 +0800 Subject: [PATCH 1401/2653] drm/amdkcl: fake the macro define DEFINE_SHOW_STORE_ATTRIBUTE It's caused by the following commit: d2143e3a "drm/amd/display: add CEC notifier to amdgpu driver" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- include/kcl/kcl_seq_file.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/kcl/kcl_seq_file.h b/include/kcl/kcl_seq_file.h index b884645a14388..bc9d5c08ecfc1 100644 --- a/include/kcl/kcl_seq_file.h +++ b/include/kcl/kcl_seq_file.h @@ -21,6 +21,23 @@ static const struct file_operations __name ## _fops = { \ } #endif +#ifndef DEFINE_SHOW_STORE_ATTRIBUTE +#define DEFINE_SHOW_STORE_ATTRIBUTE(__name) \ +static int __name ## _open(struct inode *inode, struct file *file) \ +{ \ + return single_open(file, __name ## _show, inode->i_private); \ +} \ + \ +static const struct file_operations __name ## _fops = { \ + .owner = THIS_MODULE, \ + .open = __name ## _open, \ + .read = seq_read, \ + .write = __name ## _write, \ + .llseek = seq_lseek, \ + .release = single_release, \ +} +#endif + #ifndef HAVE_SEQ_HEX_DUMP void _kcl_seq_hex_dump(struct seq_file *m, const char *prefix_str, int prefix_type, int rowsize, int groupsize, const void *buf, size_t len, From e60379a30ee244f181cfd81b1b5d8dacc6b682ce Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 10 Jan 2025 15:01:04 +0800 Subject: [PATCH 1402/2653] drm/amdkcl: test struct cec_connector_info is available It's caused by the following commit: d2143e3a "drm/amd/display: add CEC notifier to amdgpu driver" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_cec_adap.c | 23 +++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../gpu/drm/amd/dkms/m4/cec_connector_info.m4 | 23 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_cec.h | 60 +++++++++++++++++++ 7 files changed, 112 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_cec_adap.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/cec_connector_info.m4 create mode 100644 include/kcl/kcl_cec.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 5f046048ad560..d0a382378b44c 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -16,7 +16,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ - kcl_scatterlist.o kcl_kfifo.o + kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_cec_adap.c b/drivers/gpu/drm/amd/amdkcl/kcl_cec_adap.c new file mode 100644 index 0000000000000..3a94597bac3a2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_cec_adap.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * cec-adap.c - HDMI Consumer Electronics Control framework - CEC adapter + * + * Copyright 2016 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + */ +#include +#include +#include +#include + +#if !defined(HAVE_CEC_CONNECTOR_INFO) +void _kcl_cec_fill_conn_info_from_drm(struct cec_connector_info *conn_info, + const struct drm_connector *connector) +{ + memset(conn_info, 0, sizeof(*conn_info)); + conn_info->type = CEC_CONNECTOR_TYPE_DRM; + conn_info->drm.card_no = connector->dev->primary->index; + conn_info->drm.connector_id = connector->base.id; +} +EXPORT_SYMBOL_GPL(_kcl_cec_fill_conn_info_from_drm); + +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 3267585bb640a..1c4e44625e8a9 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -139,4 +139,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2070d0c08ecac..ac68bc21e558e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -79,6 +79,9 @@ /* cancel_work() is available */ #define HAVE_CANCEL_WORK 1 +/* struct cec_connector_info is available */ +#define HAVE_CEC_CONNECTOR_INFO 1 + /* cec_notifier_conn_register() is available */ #define HAVE_CEC_NOTIFIER_CONN_REGISTER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/cec_connector_info.m4 b/drivers/gpu/drm/amd/dkms/m4/cec_connector_info.m4 new file mode 100644 index 0000000000000..112e9335801c9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/cec_connector_info.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # +dnl # v5.2-rc5-392-g32a847f9fa40 +dnl # media: cec: add struct cec_connector_info support +dnl # +dnl # v5.4-rc1-53-g9098c1c251ff +dnl # media: cec: expose the new connector info API +dnl # The structure cec_connector_info has been moved from the media/cec.h to the uapi/linux/cec.h +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_CEC_CONNECTOR_INFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct cec_connector_info conn_info; + memset(&conn_info, 0, sizeof(conn_info)); + ], [ + AC_DEFINE(HAVE_CEC_CONNECTOR_INFO, 1, + [struct cec_connector_info is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e4531a4c4cbc2..b9357a269f443 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -261,6 +261,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_FIRMWARE_REQUEST_NOWARN AC_AMDGPU_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS AC_AMDGPU_CEC_NOTIFIER_CONN_REGISTER + AC_AMDGPU_STRUCT_CEC_CONNECTOR_INFO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_cec.h b/include/kcl/kcl_cec.h new file mode 100644 index 0000000000000..da8ed4471095b --- /dev/null +++ b/include/kcl/kcl_cec.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */ +/* + * cec - HDMI Consumer Electronics Control public header + * + * Copyright 2016 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + */ + +#ifndef _KCL_CEC_UAPI_H +#define _KCL_CEC_UAPI_H + +#include +#include + +#if !defined(HAVE_CEC_CONNECTOR_INFO) +/** + * struct cec_drm_connector_info - tells which drm connector is + * associated with the CEC adapter. + * @card_no: drm card number + * @connector_id: drm connector ID + */ +struct cec_drm_connector_info { + __u32 card_no; + __u32 connector_id; +}; + +#define CEC_CONNECTOR_TYPE_NO_CONNECTOR 0 +#define CEC_CONNECTOR_TYPE_DRM 1 + +/** + * struct cec_connector_info - tells if and which connector is + * associated with the CEC adapter. + * @type: connector type (if any) + * @drm: drm connector info + * @raw: array to pad the union + */ +struct cec_connector_info { + __u32 type; + union { + struct cec_drm_connector_info drm; + __u32 raw[16]; + }; +}; + +#if IS_REACHABLE(CONFIG_CEC_CORE) +void _kcl_cec_fill_conn_info_from_drm(struct cec_connector_info *conn_info, + const struct drm_connector *connector); +#define cec_fill_conn_info_from_drm _kcl_cec_fill_conn_info_from_drm + +#else +static inline void +cec_fill_conn_info_from_drm(struct cec_connector_info *conn_info, + const struct drm_connector *connector) +{ + memset(conn_info, 0, sizeof(*conn_info)); +} +#endif + +#endif + +#endif From 9144b7d152cc8b0b11090df4f0b9d3c3c43cbf91 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 7 Jan 2025 15:43:54 +0800 Subject: [PATCH 1403/2653] drm/amdkcl: cleanup macro AMDKCL_AMDGPU_DMABUF_OPS These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Asher Song drm/amdgpu: Remove remaining AMDKCL_AMDGPU_DMABUF_OPS refs These were missed in the cleanup patch, so remove them to allow the kernel to compile again Fixes: 083e622bbba3 ("drm/amdkcl: cleanup macro AMDKCL_AMDGPU_DMABUF_OPS") Signed-off-by: Kent Russell Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 - drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 - .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 6 --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 51 ------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 5 -- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 --- include/kcl/backport/kcl_drm_backport.h | 4 -- 7 files changed, 76 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index e62be5cd1293e..3194a9162f855 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -440,9 +440,7 @@ struct amdgpu_clock { uint32_t max_pixel_clock; }; -#if defined(AMDKCL_AMDGPU_DMABUF_OPS) extern const struct dma_buf_ops amdgpu_dmabuf_ops; -#endif /* sub-allocation manager, it has to be protected by another lock. * By conception this is an helper for other part of the driver diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 85dfc44679003..81afd6c3edceb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -538,11 +538,9 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, if (IS_ERR(dma_buf)) return PTR_ERR(dma_buf); -#if defined(AMDKCL_AMDGPU_DMABUF_OPS) if (dma_buf->ops != &amdgpu_dmabuf_ops) /* Can't handle non-graphics buffers */ goto out_put; -#endif obj = dma_buf->priv; if (obj->dev->driver != adev_to_drm(adev)->driver) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 093d83b47362c..75ac800a4a443 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -833,7 +833,6 @@ static int kfd_mem_export_dmabuf(struct kgd_mem *mem) return 0; } -#ifdef AMDKCL_AMDGPU_DMABUF_OPS static int kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, struct amdgpu_bo **bo) @@ -854,7 +853,6 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, return 0; } -#endif /** * @kfd_mem_attach_vram_bo: Acquires the handle of a VRAM BO that could @@ -984,7 +982,6 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, bo[i] = mem->bo; drm_gem_object_get(&bo[i]->tbo.base); } -#ifdef AMDKCL_AMDGPU_DMABUF_OPS /* Enable acces to GTT BOs of peer devices */ } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT) { attachment[i]->type = KFD_MEM_ATT_DMABUF; @@ -992,7 +989,6 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, if (ret) goto unwind; pr_debug("Employ DMABUF mechanism to enable peer GPU access\n"); -#endif /* Enable peer acces to VRAM BO's */ } else if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM) { ret = kfd_mem_attach_vram_bo(adev, mem, @@ -1000,11 +996,9 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, if (ret) goto unwind; } else { -#ifdef AMDKCL_AMDGPU_DMABUF_OPS WARN_ONCE(true, "Handling invalid ATTACH request"); ret = -EINVAL; goto unwind; -#endif attachment[i]->type = KFD_MEM_ATT_SHARED; bo[i] = mem->bo; drm_gem_object_get(&bo[i]->tbo.base); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 8e990c2947585..3ea2a2d99c695 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -91,7 +91,6 @@ int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, } #endif -#if defined(AMDKCL_AMDGPU_DMABUF_OPS) #if defined(HAVE_DMA_BUF_OPS_LEGACY) static int __dma_resv_make_exclusive(struct dma_resv *obj) @@ -510,7 +509,6 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = { .vmap = drm_gem_dmabuf_vmap, .vunmap = drm_gem_dmabuf_vunmap, }; -#endif /** * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation @@ -547,9 +545,7 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, #ifdef AMDKCL_DMA_BUF_SHARE_ADDR_SPACE buf->file->f_mapping = gobj->dev->anon_inode->i_mapping; #endif -#if defined(AMDKCL_AMDGPU_DMABUF_OPS) buf->ops = &amdgpu_dmabuf_ops; -#endif } return buf; @@ -638,7 +634,6 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, return ERR_PTR(ret); } -#ifdef AMDKCL_AMDGPU_DMABUF_OPS /** * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation * @dev: DRM device @@ -669,7 +664,6 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, return drm_gem_prime_import(dev, dma_buf); } -#endif #else /** * amdgpu_dma_buf_create_obj - create BO for DMA-buf import @@ -849,49 +843,6 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, } #endif -#ifndef AMDKCL_AMDGPU_DMABUF_OPS -int amdgpu_gem_prime_pin(struct drm_gem_object *obj) -{ - struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); - long ret = 0; - - ret = amdgpu_bo_reserve(bo, false); - if (unlikely(ret != 0)) - return ret; - - /* - * Wait for all shared fences to complete before we switch to future - * use of exclusive fence on this prime shared bo. - */ - ret = dma_resv_wait_timeout(bo->tbo.resv, true, false, - MAX_SCHEDULE_TIMEOUT); - if (unlikely(ret < 0)) { - DRM_DEBUG_PRIME("Fence wait failed: %li\n", ret); - amdgpu_bo_unreserve(bo); - return ret; - } - - /* pin buffer into GTT */ - ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); - - amdgpu_bo_unreserve(bo); - return ret; -} - -void amdgpu_gem_prime_unpin(struct drm_gem_object *obj) -{ - struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); - int ret = 0; - - ret = amdgpu_bo_reserve(bo, true); - if (unlikely(ret != 0)) - return; - - amdgpu_bo_unpin(bo); - amdgpu_bo_unreserve(bo); -} -#endif - /** * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer * @@ -913,11 +864,9 @@ bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev, if (drm_gem_is_imported(obj)) { struct dma_buf *dma_buf = obj->dma_buf; -#if defined(AMDKCL_AMDGPU_DMABUF_OPS) if (dma_buf->ops != &amdgpu_dmabuf_ops) /* No XGMI with non AMD GPUs */ return false; -#endif gobj = dma_buf->priv; bo = gem_to_amdgpu_bo(gobj); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h index dbc9384febd43..9db5f1d2a29c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h @@ -41,13 +41,8 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, struct drm_gem_object *gobj, #endif int flags); -#if defined(AMDKCL_AMDGPU_DMABUF_OPS) struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, struct dma_buf *dma_buf); -#else -int amdgpu_gem_prime_pin(struct drm_gem_object *obj); -void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); -#endif bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev, struct amdgpu_bo *bo); #ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 92a722370282c..7dfd166944c29 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3174,13 +3174,7 @@ static struct drm_driver amdgpu_kms_driver = { .gem_prime_export = amdgpu_gem_prime_export, #endif -#if defined(AMDKCL_AMDGPU_DMABUF_OPS) .gem_prime_import = amdgpu_gem_prime_import, -#else - .gem_prime_import = drm_gem_prime_import, - .gem_prime_pin = amdgpu_gem_prime_pin, - .gem_prime_unpin = amdgpu_gem_prime_unpin, -#endif #ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ .gem_prime_res_obj = amdgpu_gem_prime_res_obj, #endif diff --git a/include/kcl/backport/kcl_drm_backport.h b/include/kcl/backport/kcl_drm_backport.h index c17c10af84c09..1aba914420638 100644 --- a/include/kcl/backport/kcl_drm_backport.h +++ b/include/kcl/backport/kcl_drm_backport.h @@ -10,10 +10,6 @@ #define AMDKCL_AMDGPU_DEBUGFS_CLEANUP #endif -#if DRM_VERSION_CODE >= DRM_VERSION(4, 17, 0) -#define AMDKCL_AMDGPU_DMABUF_OPS -#endif - /* * commit v5.4-rc4-1120-gb3fac52c5193 * drm: share address space for dma bufs From 2322b67fe05248070d9a767adc8abe4f371181cc Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 8 Jan 2025 14:35:12 +0800 Subject: [PATCH 1404/2653] drm/amdkcl: cleanup macro AMDKCL_DRM_CONNECTOR_FUNCS_DPMS_MANDATORY These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 21 --------------------- include/kcl/backport/kcl_drm_backport.h | 8 -------- 2 files changed, 29 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index e941d3a06b2f8..9a2cfe2133c54 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -207,33 +207,12 @@ static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, return ret; } -#ifdef AMDKCL_DRM_CONNECTOR_FUNCS_DPMS_MANDATORY -static int -amdgpu_vkms_connector_dpms(struct drm_connector *connector, int mode) -{ - return 0; -} - - -static int -amdgpu_vkms_connector_set_property(struct drm_connector *connector, - struct drm_property *property, - uint64_t val) -{ - return 0; -} -#endif - static const struct drm_connector_funcs amdgpu_vkms_connector_funcs = { .fill_modes = drm_helper_probe_single_connector_modes, .destroy = drm_connector_cleanup, .reset = drm_atomic_helper_connector_reset, .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -#ifdef AMDKCL_DRM_CONNECTOR_FUNCS_DPMS_MANDATORY - .set_property = amdgpu_vkms_connector_set_property, - .dpms = amdgpu_vkms_connector_dpms, -#endif }; static int amdgpu_vkms_conn_get_modes(struct drm_connector *connector) diff --git a/include/kcl/backport/kcl_drm_backport.h b/include/kcl/backport/kcl_drm_backport.h index 1aba914420638..135a5e5c499af 100644 --- a/include/kcl/backport/kcl_drm_backport.h +++ b/include/kcl/backport/kcl_drm_backport.h @@ -18,12 +18,4 @@ #define AMDKCL_DMA_BUF_SHARE_ADDR_SPACE #endif -/* - * commit v4.13-rc2-365-g144a7999d633 - * drm: Handle properties in the core for atomic drivers - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 14, 0) -#define AMDKCL_DRM_CONNECTOR_FUNCS_DPMS_MANDATORY -#endif - #endif/*AMDKCL_DRM_BACKPORT_H*/ From 407e1b4d36c9d62b739fa937368ee8dd05408c27 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 8 Jan 2025 14:39:57 +0800 Subject: [PATCH 1405/2653] drm/amdkcl: cleanup macro AMDKCL_AMDGPU_DEBUGFS_CLEANUP These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 19 ------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h | 5 ----- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ------ include/kcl/backport/kcl_drm_backport.h | 8 -------- 4 files changed, 38 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 631780121a1e6..53c0b75791ac7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -42,25 +42,6 @@ #if defined(CONFIG_DEBUG_FS) -#if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) -void amdgpu_debugfs_cleanup(struct drm_minor *minor) -{ - struct drm_info_node *node, *tmp; - - if (!&minor->debugfs_root) - return; - - mutex_lock(&minor->debugfs_lock); - list_for_each_entry_safe(node, tmp, - &minor->debugfs_list, list) { - debugfs_remove(node->dent); - list_del(&node->list); - kfree(node); - } - mutex_unlock(&minor->debugfs_lock); -} -#endif - /** * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h index 5696dcb7f3be4..aabfabbd5e3e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h @@ -25,11 +25,6 @@ /* * Debugfs */ -#if defined(CONFIG_DEBUG_FS) -#if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) -void amdgpu_debugfs_cleanup(struct drm_minor *minor); -#endif -#endif int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); int amdgpu_debugfs_init(struct amdgpu_device *adev); void amdgpu_debugfs_fini(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 7dfd166944c29..446c4504b01db 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3133,12 +3133,6 @@ static struct drm_driver amdgpu_kms_driver = { , .open = amdgpu_driver_open_kms, .postclose = amdgpu_driver_postclose_kms, -#if defined(CONFIG_DEBUG_FS) -#if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) - .debugfs_cleanup = amdgpu_debugfs_cleanup, -#endif -#endif - #ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = kcl_amdgpu_get_vblank_counter_kms, .enable_vblank = kcl_amdgpu_enable_vblank_kms, diff --git a/include/kcl/backport/kcl_drm_backport.h b/include/kcl/backport/kcl_drm_backport.h index 135a5e5c499af..56326c6a61e89 100644 --- a/include/kcl/backport/kcl_drm_backport.h +++ b/include/kcl/backport/kcl_drm_backport.h @@ -2,14 +2,6 @@ #ifndef AMDKCL_DRM_BACKPORT_H #define AMDKCL_DRM_BACKPORT_H -/* - * commit v4.10-rc3-539-g086f2e5cde74 - * drm: debugfs: Remove all files automatically on cleanup - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 11, 0) -#define AMDKCL_AMDGPU_DEBUGFS_CLEANUP -#endif - /* * commit v5.4-rc4-1120-gb3fac52c5193 * drm: share address space for dma bufs From ec7091533cbf5225f66f2b3dae3322ff03272028 Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 3 Jan 2025 16:48:10 +0800 Subject: [PATCH 1406/2653] drm/amdkcl: Replace drm_dp_mst_topology_mgr.base check with drm_private_obj.lock The check for the 'base' field in the struct drm_dp_mst_topology_mgr is no longer necessary.This patch removes the check for 'base' and replaces it with a check for the 'lock' field in struct drm_private_obj. And The base.lock was introduced in version 4.20, while the write lock was added in DRM version 5.4.0. Since RHEL 7.9 uses DRM version 5.0.10, write operations do not include locking. Consequently, read operations here also do not require locking. Signed-off-by: chengjya Reviewed-by: Bob Zhou --- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 26 ++++++++++--------- drivers/gpu/drm/amd/dkms/config/config.h | 6 ++--- .../amd/dkms/m4/drm_dp_mst_topology_mgr.m4 | 20 -------------- .../drm/amd/dkms/m4/drm_private_obj_lock.m4 | 19 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 5 files changed, 37 insertions(+), 36 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_private_obj_lock.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index c8d954411d0d2..8c8eeb5fb8606 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -341,7 +341,6 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, return size; } -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector) { bool is_end_device = false; @@ -352,11 +351,20 @@ static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector) mgr = &aconnector->mst_root->mst_mgr; port = aconnector->mst_output_port; + /* The base.lock was introduced in version 4.20, while the write + * lock was added in DRM version 5.4.0. Since RHEL 7.9 uses DRM version + * 5.0.10, write operations do not include locking. Consequently, read + * operations here also do not require locking. + */ +#ifdef HAVE_DRM_PRIVATE_OBJ_LOCK drm_modeset_lock(&mgr->base.lock, NULL); +#endif if (port->pdt == DP_PEER_DEVICE_SST_SINK || port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV) is_end_device = true; +#ifdef HAVE_DRM_PRIVATE_OBJ_LOCK drm_modeset_unlock(&mgr->base.lock); +#endif } return is_end_device; @@ -488,7 +496,6 @@ static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf, kfree(wr_buf); return size; } -#endif /* function: get current DP PHY settings: voltage swing, pre-emphasis, * post-cursor2 (defined by VESA DP specification) * @@ -2759,7 +2766,6 @@ static int target_backlight_show(struct seq_file *m, void *unused) * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector * */ -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE static int dp_is_mst_connector_show(struct seq_file *m, void *unused) { struct drm_connector *connector = m->private; @@ -2780,11 +2786,15 @@ static int dp_is_mst_connector_show(struct seq_file *m, void *unused) mgr = &aconnector->mst_root->mst_mgr; port = aconnector->mst_output_port; +#ifdef HAVE_DRM_PRIVATE_OBJ_LOCK drm_modeset_lock(&mgr->base.lock, NULL); +#endif if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING && port->mcs) role = "branch"; +#ifdef HAVE_DRM_PRIVATE_OBJ_LOCK drm_modeset_unlock(&mgr->base.lock); +#endif } else { role = "no"; @@ -2796,7 +2806,6 @@ static int dp_is_mst_connector_show(struct seq_file *m, void *unused) return 0; } -#endif /* * function description: Read out the mst progress status @@ -2925,9 +2934,7 @@ DEFINE_SHOW_ATTRIBUTE(internal_display); DEFINE_SHOW_ATTRIBUTE(odm_combine_segments); DEFINE_SHOW_ATTRIBUTE(replay_capability); DEFINE_SHOW_ATTRIBUTE(psr_capability); -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector); -#endif DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); DEFINE_SHOW_ATTRIBUTE(is_dpia_link); DEFINE_SHOW_STORE_ATTRIBUTE(hdmi_cec_state); @@ -3028,13 +3035,12 @@ static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { .write = dp_dsc_passthrough_set, .llseek = default_llseek }; -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE + static const struct file_operations dp_mst_link_settings_debugfs_fops = { .owner = THIS_MODULE, .write = dp_mst_link_setting, .llseek = default_llseek }; -#endif static const struct { char *name; @@ -3057,14 +3063,10 @@ static const struct { {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, {"max_bpc", &dp_max_bpc_debugfs_fops}, {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE {"is_mst_connector", &dp_is_mst_connector_fops}, -#endif {"mst_progress_status", &dp_mst_progress_status_fops}, {"is_dpia_link", &is_dpia_link_fops}, -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE {"mst_link_settings", &dp_mst_link_settings_debugfs_fops} -#endif }; static const struct { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ac68bc21e558e..0ad0f04ba3505 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -417,9 +417,6 @@ /* struct drm_dp_mst_topology_cbs->register_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR */ -/* struct drm_dp_mst_topology_mgr.base is available */ -#define HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE 1 - /* drm_dp_mst_topology_mgr_init() has max_lane_count and max_link_rate */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT */ @@ -642,6 +639,9 @@ /* drm_print_memory_stats() is available */ #define HAVE_DRM_PRINT_MEMORY_STATS 1 +/* struct drm_private_obj.lock is available */ +#define HAVE_DRM_PRIVATE_OBJ_LOCK 1 + /* drm_show_fdinfo() is available */ #define HAVE_DRM_SHOW_FDINFO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 deleted file mode 100644 index c674432e635f2..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 +++ /dev/null @@ -1,20 +0,0 @@ -dnl # -dnl # commit v4.14-rc1-a4370c7774 -dnl # drm/atomic: Make private objs proper objects -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - #include - ], [ - struct drm_dp_mst_topology_mgr *mst_mgr = 0; - int i = 0; - if ((&mst_mgr->base) && (&mst_mgr->base.lock)) - i++; - ], [ - AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE, 1, - [struct drm_dp_mst_topology_mgr.base is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_private_obj_lock.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_private_obj_lock.m4 new file mode 100644 index 0000000000000..79e2de01aed3f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_private_obj_lock.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit v4.20-rc4-945-gb962a12050a3 +dnl # drm/atomic: integrate modeset lock with private objects +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRIVATE_OBJ_LOCK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_private_obj *obj = NULL; + struct drm_modeset_lock lock = {}; + obj->lock = lock; + ], [ + AC_DEFINE(HAVE_DRM_PRIVATE_OBJ_LOCK, 1, + [struct drm_private_obj.lock is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b9357a269f443..5148f7563834d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -187,7 +187,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TOTALRAM_PAGES AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG - AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE + AC_AMDGPU_DRM_PRIVATE_OBJ_LOCK AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 AC_AMDGPU_DRM_DP_READ_DPCD_CAPS AC_AMDGPU_DRM_DP_REMOVE_RAYLOAD_PART From ac0bf3bac3e38875e5f98f93cefa5a6ee1005d72 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 15 Jan 2025 11:36:56 +0800 Subject: [PATCH 1407/2653] drm/amdkcl: include $CC condition to pre-build Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 4 +++- drivers/gpu/drm/amd/dkms/pre-build.sh | 29 +++++++++++++++------------ 2 files changed, 19 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index abb5fa4da4920..6c767056f76a8 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -7,6 +7,7 @@ module_src_dir := $(CURDIR) module_build_dir := $(shell mktemp -ut amd.XXXXXXXX) module_build_flags := num_cpu_cores := $(shell which nproc > /dev/null && nproc || echo "1") +CC := gcc Q := @ ifeq ($(wildcard $(kernel_build_dir)/include/config/auto.conf),) @@ -31,6 +32,7 @@ $(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) endif ifneq ($(CONFIG_CC_IS_CLANG),) +CC := clang module_build_flags += CC=clang endif ifneq ($(CONFIG_LD_IS_LLD),) @@ -53,7 +55,7 @@ sanity-check: pre-build $(config-file) $(if $(call KCL_MACRO_CHECK_COMMAND, HAVE_RESERVATION_WW_CLASS_BUG), $(error reservation_ww_class is missing. exit...)) pre-build: - $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(module_build_dir) + $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(module_build_dir) $(CC) clean: $(Q)make -C $(kernel_build_dir) M=$(module_src_dir) clean diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 7f3e5f9323673..b9fc82557aac6 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -7,6 +7,7 @@ SRC="amd/dkms" KERNELVER=$1 DKMS_TREE=$2 MODULE_BUILD_DIR=$3 +CC=$4 KERNELVER_BASE=${KERNELVER%%-*} version_lt () { @@ -62,19 +63,21 @@ done export KERNELVER ln -s $DKMS_TREE $MODULE_BUILD_DIR -# Enable gcc-toolset for kernels that are built with non-default compiler -# perform this check only when permissions allow -if [[ -d /opt/rh && `id -u` -eq 0 ]]; then - for f in $(find /opt/rh -type f -a -name gcc); do - [[ -f /boot/config-$KERNELVER ]] || continue - config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) - IFS='.' read -ra ver <<<$($f -dumpfullversion) - gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) - if [[ "$config_gcc_version" = "$gcc_version" ]]; then - . ${f%/*}/../../../enable - break - fi - done +if [ "$CC" == "gcc" ]; then + # Enable gcc-toolset for kernels that are built with non-default compiler + # perform this check only when permissions allow + if [[ -d /opt/rh && `id -u` -eq 0 ]]; then + for f in $(find /opt/rh -type f -a -name gcc); do + [[ -f /boot/config-$KERNELVER ]] || continue + config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) + IFS='.' read -ra ver <<<$($f -dumpfullversion) + gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) + if [[ "$config_gcc_version" = "$gcc_version" ]]; then + . ${f%/*}/../../../enable + break + fi + done + fi fi echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env From 1189b8513487d4b6e325a81e737938966627a720 Mon Sep 17 00:00:00 2001 From: chengjya Date: Fri, 17 Jan 2025 14:55:25 +0800 Subject: [PATCH 1408/2653] drm/amdkcl: test whether struct drm_connector_state->hdmi.broadcast_rgb is available It's caused by the commit: 0865e2aef5ca "drm/amd/display: Support "Broadcast RGB" drm property" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/struct_drm_connector_state.m4 | 21 ++++++++++++++++++- 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1703ee9ba1529..76400b75920c1 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6356,8 +6356,10 @@ get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, default: if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) { color_space = COLOR_SPACE_SRGB; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB if (connector_state->hdmi.broadcast_rgb == DRM_HDMI_BROADCAST_RGB_LIMITED) color_space = COLOR_SPACE_SRGB_LIMITED; +#endif /* * 27030khz is the separation point between HDTV and SDTV * according to HDMI spec, we use YCbCr709 and YCbCr601 @@ -8767,9 +8769,11 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, dm->ddev->mode_config.scaling_mode_property, DRM_MODE_SCALE_NONE); +#ifdef HAVE_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB if (connector_type == DRM_MODE_CONNECTOR_HDMIA || (connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root)) drm_connector_attach_broadcast_rgb_property(&aconnector->base); +#endif drm_object_attach_property(&aconnector->base.base, adev->mode_info.underscan_property, @@ -10625,10 +10629,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) scaling_changed = is_scaling_state_different(dm_new_con_state, dm_old_con_state); +#ifdef HAVE_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB if ((new_con_state->hdmi.broadcast_rgb != old_con_state->hdmi.broadcast_rgb) && (dm_old_crtc_state->stream->output_color_space != get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state))) output_color_space_changed = true; +#endif abm_changed = dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0ad0f04ba3505..567c55f0c2c83 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -242,6 +242,9 @@ /* struct drm_connector_state has hdcp_content_type member */ #define HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE 1 +/* drm_connector_state->hdmi.broadcast_rgb is available */ +#define HAVE_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB 1 + /* struct drm_connector_state has hdr_output_metadata member */ #define HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 index 845426d6fe7bf..fbcca17fe167a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 @@ -16,6 +16,25 @@ AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STATE_COLORSPACE], [ ]) ]) +dnl # +dnl # commit v6.10-rc1-219-gab52af4ba7c7 +dnl # drm/connector: hdmi: Add Broadcast RGB property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *connector_state = NULL; + connector_state->hdmi.broadcast_rgb = DRM_HDMI_BROADCAST_RGB_AUTO; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB, 1, + [drm_connector_state->hdmi.broadcast_rgb is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE], [ AC_AMDGPU_DRM_CONNECTOR_STATE_COLORSPACE -]) \ No newline at end of file + AC_AMDGPU_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB +]) From d08f50ff7e69829a5f7effe45166b9cc52472405 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 20 Jan 2025 18:01:47 +0800 Subject: [PATCH 1409/2653] drm/amdkcl: fix unused function amdgpu_vkms_early_init() The wrong merge to miss amdgpu_vkms_early_init(), so remerge it. Fixes: 1e30d5a2c81b("drm/amdgpu: Clean the functions pointer set as NULL") Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 9a2cfe2133c54..4251a77c11781 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -771,6 +771,9 @@ static int amdgpu_vkms_set_powergating_state(struct amdgpu_ip_block *ip_block, static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = { .name = "amdgpu_vkms", +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + .early_init = amdgpu_vkms_early_init, +#endif .sw_init = amdgpu_vkms_sw_init, .sw_fini = amdgpu_vkms_sw_fini, .hw_init = amdgpu_vkms_hw_init, From 9fc3053cf743c6fe79092c31df393615e30c9c7e Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Fri, 17 Jan 2025 16:32:20 +0800 Subject: [PATCH 1410/2653] drm/amdgpu: Fix parameter compatibility issue in amdgpu_vkms_early_init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit GCC raises a parameter compatibility error log for the amdgpu_vkms_early_init function because it previously accepted a generic `void *handle` parameter. This change updates the function signature to accept a specific `struct amdgpu_ip_block *` parameter instead. error log: /tmp/amd.fwXY79Rm/amd/amdgpu/amdgpu_vkms.c:805:16: error: initialization of ‘int (*)(struct amdgpu_ip_block *)’ from incompatible pointer type ‘int (*)(void *)’ [-Werror=incompatible-pointer-types] .early_init = amdgpu_vkms_early_init, Reviewed-by: Alex Deucher Acked-by: Yifan Zhang Signed-off-by: Perry Yuan --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 4251a77c11781..03aa0b8405733 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -596,9 +596,9 @@ static const struct amdgpu_irq_src_funcs amdgpu_vkms_crtc_irq_funcs = { .process = NULL, }; -static int amdgpu_vkms_early_init(void *handle) +static int amdgpu_vkms_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->crtc_irq.num_types = adev->mode_info.num_crtc; adev->crtc_irq.funcs = &amdgpu_vkms_crtc_irq_funcs; From e4438be7e704bf3a72f857f3e5ab40a1630f8735 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 21 Jan 2025 14:29:02 +0800 Subject: [PATCH 1411/2653] drm/amdkcl: Fix kfd->profiler_lock Initialization Order [Why] In GFX version < 11.0.0 (like navi22), the origin patch will cause kernel (version < 4.9) hangs due to Uninitialized mutex in kfd_init_node(). Since v4.9-rc2-42-g3ca0ff571b09 ("locking/mutex: Rework mutex::owner"), it has increased the tolerance of mutex locks, preventing the kernel hang. But it remains an incorrect usage. Here are the call paths: kgd2kfd_device_init() kfd_init_node() kfd_resume() start_cpsch() pm_init() kernel_queue_init() kq_initialize() init_mqd() mutex_lock(&mm->dev->kfd->profiler_lock) mutex_init(&kfd->profiler_lock) [How] Reorder the mutex_init() before kfd_init_node() to fix it. Fixes: b58289f0abf7 ("Add kfd_ioctl_profiler to contain profiler kernel driver changes") Signed-off-by: chengjya Signed-off-by: Bob Zhou Reviewed-by: Benjamin Welton --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 00d37b89779a1..418a9dbeeeefb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -873,6 +873,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", kfd->num_nodes); + kfd->profiler_process = NULL; + mutex_init(&kfd->profiler_lock); /* Allocate the KFD nodes */ for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); @@ -945,9 +947,6 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, svm_range_set_max_pages(kfd->adev); - kfd->profiler_process = NULL; - mutex_init(&kfd->profiler_lock); - kfd->init_complete = true; dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, kfd->adev->pdev->device); @@ -961,6 +960,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, node_alloc_error: kfd_cleanup_nodes(kfd, i); kfd_doorbell_fini(kfd); + mutex_destroy(&kfd->profiler_lock); kfd_doorbell_error: kfd_gtt_sa_fini(kfd); kfd_gtt_sa_init_error: From 4e332e33820aecb552ff77dcde45779ef4d195bd Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 20 Jan 2025 15:29:48 +0800 Subject: [PATCH 1412/2653] drm/amdkcl: fake the macro define ULL(x) It's caused by the commit: 9bb53d2c "drm/amd/pm: Add capability flags for SMU v13.0.6" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_const.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/kcl/kcl_const.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1c4e44625e8a9..bd8b1813803c7 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -140,4 +140,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_const.h b/include/kcl/kcl_const.h new file mode 100644 index 0000000000000..676de2be9f96a --- /dev/null +++ b/include/kcl/kcl_const.h @@ -0,0 +1,11 @@ +#ifndef _KCL_LINUX_CONST_H +#define _KCL_LINUX_CONST_H + +#include + +#ifndef _ULL +#define _ULL(x) (_AC(x, ULL)) +#define ULL(x) (_ULL(x)) +#endif + +#endif /* _KCL_LINUX_CONST_H */ From 3d722ca6c437574a3aaaf5185c3ad391938eb1d8 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Mon, 20 Jan 2025 16:00:12 -0500 Subject: [PATCH 1413/2653] drm/amdgpu: apply psp_config_sq_perfmon on gfx_9_5_0 which is with psp_13_0_12. Signed-off-by: James Zhu Reviewed-by: Lijo Lazar Reviewed-by: Vladimir Indic Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 84e43f91a6495..435e38befe7b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -4012,7 +4012,8 @@ int psp_config_sq_perfmon(struct psp_context *psp, if (amdgpu_sriov_vf(psp->adev)) return 0; - if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { + if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6) && + amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 12)) { dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); return -EINVAL; From 4f480b9c2f63a4a72694d53da98616210db25dbd Mon Sep 17 00:00:00 2001 From: James Zhu Date: Tue, 14 Jan 2025 14:12:21 -0500 Subject: [PATCH 1414/2653] drm/kfd: add Host Trap PC sampling support for gfx_9_5_0. Signed-off-by: James Zhu Reviewed-by: Lijo Lazar Reviewed-by: Vladimir Indic Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 1cf02035d326d..7573eb3f88cbe 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -35,6 +35,7 @@ * 0.2 - Support gfx9_4_3 Host Trap PC sampling * 0.3 - Fix gfx9_4_3 SQ hang issue * 1.1 - Support gfx9_4_3 Stochastic PC sampling + * 1.2 - Support gfx9_5_0 Host Trap PC sampling */ #define KFD_IOCTL_PCS_MAJOR_VERSION 1 #define KFD_IOCTL_PCS_MINOR_VERSION 1 @@ -55,6 +56,7 @@ struct supported_pc_sample_info supported_formats[] = { { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 4, 3), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 4, 3), &sample_info_stoch_cycle_9_4_3 }, + { IP_VERSION(9, 5, 0), &sample_info_hosttrap_9_0_0 }, }; static int kfd_pc_sample_thread(void *param) From a514589e954bd49a48072cc66a984cd9b5d6e92f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 17 Jan 2025 10:25:55 +0800 Subject: [PATCH 1415/2653] drm/amdkcl: Handle GCC change in advance Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/pre-build.sh | 34 +++++++++++++-------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index b9fc82557aac6..3dca4caa9855d 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -30,6 +30,23 @@ version_le () { [ "$KERNELVER_BASE" = "$oldest" ] } +if [ "$CC" == "gcc" ]; then + # Enable gcc-toolset for kernels that are built with non-default compiler + # perform this check only when permissions allow + if [[ -d /opt/rh && `id -u` -eq 0 ]]; then + for f in $(find /opt/rh -type f -a -name gcc); do + [[ -f /boot/config-$KERNELVER ]] || continue + config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) + IFS='.' read -ra ver <<<$($f -dumpfullversion) + gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) + if [[ "$config_gcc_version" = "$gcc_version" ]]; then + . ${f%/*}/../../../enable + break + fi + done + fi +fi + source $KCL/files sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ @@ -62,23 +79,6 @@ done export KERNELVER ln -s $DKMS_TREE $MODULE_BUILD_DIR - -if [ "$CC" == "gcc" ]; then - # Enable gcc-toolset for kernels that are built with non-default compiler - # perform this check only when permissions allow - if [[ -d /opt/rh && `id -u` -eq 0 ]]; then - for f in $(find /opt/rh -type f -a -name gcc); do - [[ -f /boot/config-$KERNELVER ]] || continue - config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) - IFS='.' read -ra ver <<<$($f -dumpfullversion) - gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) - if [[ "$config_gcc_version" = "$gcc_version" ]]; then - . ${f%/*}/../../../enable - break - fi - done - fi -fi echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env (cd $SRC && ./configure) From f00a8e4c851491c5ac5bc0eba8097efb6bed3d27 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 17 Jan 2025 10:41:27 +0800 Subject: [PATCH 1416/2653] drm/amdkcl: modify gcc check into pre-build.sh Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 8 -------- drivers/gpu/drm/amd/dkms/pre-build.sh | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index 0821ba268d9a4..df676cf4a33a7 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -25,14 +25,6 @@ endif endif -include $(src)/amd/dkms/Makefile.compiler - -# gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. -ifneq ($(call gcc-min-version, 40805), y) -ifeq ($(call kernel-version, -ge, 0504, y), y) -$(error "The GCC is too old for this kernel, please update the GCC to higher than 9.3") -endif -endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 3dca4caa9855d..f27b5d9204a3e 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -45,6 +45,14 @@ if [ "$CC" == "gcc" ]; then fi done fi + + gcc_version=$($CC -dumpfullversion | awk -F. '{printf "%d%02d%02d", $1, $2, $3}') + kernel_version=$(uname -r | awk -F. '{printf "%d%02d", $1, $2}') + # gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. + if [ "$gcc_version" -lt 40805 ] && [ "$kernel_version" -ge 0504 ]; then + echo "Error: The GCC is too old for this kernel, please update the GCC to higher than 9.3" + exit 1 + fi fi source $KCL/files From f3a6efbc0b7030e5617b88bc341fa7f07d36237b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 17 Jan 2025 13:12:18 +0800 Subject: [PATCH 1417/2653] drm/amdkcl: fix undefined CONFIG_GCC_VERSION When kernel < v4.17-6936-ga4353898980c(like rhel7.9), the CONFIG_GCC_VERSION isn't defined. So include the varb in vmlinuz. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/pre-build.sh | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index f27b5d9204a3e..7411801636c29 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -37,6 +37,10 @@ if [ "$CC" == "gcc" ]; then for f in $(find /opt/rh -type f -a -name gcc); do [[ -f /boot/config-$KERNELVER ]] || continue config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) + # CONFIG_GCC_VERSION is included in kernel v4.17-6936-ga4353898980c + if [ ! "$config_gcc_version" ]; then + config_gcc_version=$(strings /boot/vmlinuz-$KERNELVER | grep -F $KERNELVER | grep gcc | grep -oP 'gcc version \K[\d.]+') + fi IFS='.' read -ra ver <<<$($f -dumpfullversion) gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) if [[ "$config_gcc_version" = "$gcc_version" ]]; then From de5a2debbb9cc63fdc2ce58e98717633ecb8d7e1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 21 Jan 2025 11:15:40 +0800 Subject: [PATCH 1418/2653] drm/amdkcl: cleanup config CONFIG_DRM_TTM_DMA_PAGE_POOL Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index df676cf4a33a7..2b0db273109f1 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -141,7 +141,6 @@ LINUXINCLUDE := \ export CONFIG_HSA_AMD=y export CONFIG_DRM_TTM=m -export CONFIG_DRM_TTM_DMA_PAGE_POOL=y export CONFIG_DRM_AMDGPU=m export CONFIG_DRM_SCHED=m export CONFIG_DRM_AMDGPU_CIK=y @@ -150,7 +149,6 @@ export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y subdir-ccflags-y += -DCONFIG_HSA_AMD -subdir-ccflags-y += -DCONFIG_DRM_TTM_DMA_PAGE_POOL subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR From 30aac14ad84b2b68c873d53f5defe1fe8825dbf7 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 21 Jan 2025 11:20:47 +0800 Subject: [PATCH 1419/2653] drm/amdkcl: cleanup config CONFIG_DRM_AMD_DC_HDCP It's caused 1e88eb1b2c259994d034b0833cb489105a984ebb drm/amd/display: Drop CONFIG_DRM_AMD_DC_HDCP Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +-- drivers/gpu/drm/amd/dkms/Kbuild | 3 --- include/kcl/kcl_drm_hdcp.h | 2 -- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index d0a382378b44c..5542e6b032f17 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -16,9 +16,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ - kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o + kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o -amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o kcl_debugfs_file.o amdkcl-$(CONFIG_SYSFS) += kcl_sysfs_emit.o diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index 2b0db273109f1..2ff5206d47931 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -162,9 +162,6 @@ subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM endif endif -export CONFIG_DRM_AMD_DC_HDCP=y -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP - ifeq (y,$(CONFIG_PCI_P2PDMA)) ifeq (y,$(CONFIG_DMABUF_MOVENOTIFY)) export CONFIG_HSA_AMD_P2P=y diff --git a/include/kcl/kcl_drm_hdcp.h b/include/kcl/kcl_drm_hdcp.h index 76c7823fe6f88..7b6bb3b69a57a 100644 --- a/include/kcl/kcl_drm_hdcp.h +++ b/include/kcl/kcl_drm_hdcp.h @@ -8,7 +8,6 @@ #ifndef AMDKCL_DRM_HDCP_H #define AMDKCL_DRM_HDCP_H -#ifdef CONFIG_DRM_AMD_DC_HDCP #include #include @@ -318,6 +317,5 @@ void drm_hdcp_update_content_protection(struct drm_connector *connector, } #endif /* HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION */ -#endif /* CONFIG_DRM_AMD_DC_HDCP */ #endif /* AMDKCL_DRM_HDCP_H */ From ab78361dcc7072e0801065ae0bab70a89bf5c923 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 21 Jan 2025 11:38:57 +0800 Subject: [PATCH 1420/2653] drm/amdkcl: split dkms config to dkms-config.mk Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 13 ++------- drivers/gpu/drm/amd/dkms/Makefile | 6 +++- drivers/gpu/drm/amd/dkms/dkms-config.sh | 37 +++++++++++++++++++++++++ 3 files changed, 44 insertions(+), 12 deletions(-) create mode 100755 drivers/gpu/drm/amd/dkms/dkms-config.sh diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index 2ff5206d47931..d78b0c1265832 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -25,6 +25,7 @@ endif endif +include $(src)/amd/dkms/dkms-config.mk _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") @@ -139,20 +140,10 @@ LINUXINCLUDE := \ -I$(src)/include/uapi \ $(USER_INCLUDE) -export CONFIG_HSA_AMD=y export CONFIG_DRM_TTM=m export CONFIG_DRM_AMDGPU=m export CONFIG_DRM_SCHED=m -export CONFIG_DRM_AMDGPU_CIK=y -export CONFIG_DRM_AMDGPU_SI=y -export CONFIG_DRM_AMDGPU_USERPTR=y -export CONFIG_DRM_AMD_DC=y - -subdir-ccflags-y += -DCONFIG_HSA_AMD -subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK -subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI -subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC + subdir-ccflags-y += -Wno-error ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 6c767056f76a8..dcaaf349feece 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -39,10 +39,11 @@ ifneq ($(CONFIG_LD_IS_LLD),) module_build_flags += LD=ld.lld endif +dkms-config ?= amd/dkms/dkms-config.mk config-file ?= amd/dkms/config/config.h KCL_MACRO_CHECK_COMMAND=$(shell grep $(1) $(config-file) | grep -q "define" && echo "y") -modules: sanity-check +modules: sanity-check $(dkms-config) $(Q)$(shell cat $(module_build_dir)/.env) make -j$(num_cpu_cores) \ TTM_NAME=amdttm \ SCHED_NAME=amd-sched \ @@ -54,6 +55,9 @@ sanity-check: pre-build $(config-file) $(if $(call KCL_MACRO_CHECK_COMMAND, HAVE_DMA_RESV_SEQ_BUG), $(error dma_resv->seq is missing. exit...)) $(if $(call KCL_MACRO_CHECK_COMMAND, HAVE_RESERVATION_WW_CLASS_BUG), $(error reservation_ww_class is missing. exit...)) +$(dkms-config): pre-build + $(Q)amd/dkms/dkms-config.sh $@ $(KERNELVER) + pre-build: $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(module_build_dir) $(CC) diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh new file mode 100755 index 0000000000000..9b245874f09e1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -0,0 +1,37 @@ +#!/bin/bash + +local_config=$1 +KERNELVER=$2 +local_config_tmp=${local_config}.tmp +config_file="/lib/modules/$KERNELVER/build/include/config/auto.conf" + +rm -f ${local_config_tmp} + +append_mk () { + echo $1 >> ${local_config_tmp} +} + +export_macro_mk () { +cat <<_DKMS_CONFIG >> ${local_config_tmp} +export $1=y +subdir-ccflags-y += -D$1 + +_DKMS_CONFIG +} + +get_config() { + grep "^$1=" "${config_file}" | awk -F= '{print $2}' +} + +is_enabled() { + grep -q "^$1=\[ym]" "${config_file}" +} + +export_macro_mk CONFIG_HSA_AMD +export_macro_mk CONFIG_DRM_AMDGPU_CIK +export_macro_mk CONFIG_DRM_AMDGPU_SI +export_macro_mk CONFIG_DRM_AMDGPU_USERPTR +export_macro_mk CONFIG_DRM_AMD_DC + +cat ${local_config_tmp} +mv ${local_config_tmp} ${local_config} \ No newline at end of file From 6c79570920f959d1e9382ce5f58252870567f8d9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 11 Feb 2025 14:54:23 +0800 Subject: [PATCH 1421/2653] drm/amdkcl: Add cleanup of dkms-config and config-file in clean target Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index dcaaf349feece..b16e2e453fe3e 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -62,5 +62,7 @@ pre-build: $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(module_build_dir) $(CC) clean: + $(Q)echo "Cleaning build files..." $(Q)make -C $(kernel_build_dir) M=$(module_src_dir) clean + $(Q)rm -f $(dkms-config) $(config-file) endif From e06a62bd58d39c71f61c3d5c987da80360646018 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 11 Feb 2025 15:56:28 +0800 Subject: [PATCH 1422/2653] drm/amdkcl: modify CONFIG_HSA_AMD_P2P to dkms-config.sh Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 7 ------- drivers/gpu/drm/amd/dkms/dkms-config.sh | 8 +++++++- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index d78b0c1265832..ec9ed6319527a 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -153,13 +153,6 @@ subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM endif endif -ifeq (y,$(CONFIG_PCI_P2PDMA)) - ifeq (y,$(CONFIG_DMABUF_MOVENOTIFY)) - export CONFIG_HSA_AMD_P2P=y - subdir-ccflags-y += -DCONFIG_HSA_AMD_P2P - endif -endif - # Trying to enable DCN2/3 with core2 optimizations will result in # older versions of GCC hanging during building/installing. Check # if the compiler is using core2 optimizations and only build DCN2/3 diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index 9b245874f09e1..59a09af509429 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -27,6 +27,12 @@ is_enabled() { grep -q "^$1=\[ym]" "${config_file}" } +if [[ "$(get_config CONFIG_PCI_P2PDMA)" == "y" ]]; then + if [[ "$(get_config CONFIG_DMABUF_MOVENOTIFY)" == "y" ]]; then + export_macro_mk CONFIG_HSA_AMD_P2P + fi +fi + export_macro_mk CONFIG_HSA_AMD export_macro_mk CONFIG_DRM_AMDGPU_CIK export_macro_mk CONFIG_DRM_AMDGPU_SI @@ -34,4 +40,4 @@ export_macro_mk CONFIG_DRM_AMDGPU_USERPTR export_macro_mk CONFIG_DRM_AMD_DC cat ${local_config_tmp} -mv ${local_config_tmp} ${local_config} \ No newline at end of file +mv ${local_config_tmp} ${local_config} From 31177500ce8018bf5e5f2fb036971b8a273bd56e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 13 Feb 2025 11:27:55 +0800 Subject: [PATCH 1423/2653] drm/amdkcl: fix is_enabled judge for dkms_config.sh Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/dkms-config.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index 59a09af509429..01e2a91ce242f 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -24,7 +24,7 @@ get_config() { } is_enabled() { - grep -q "^$1=\[ym]" "${config_file}" + grep -q "^$1=" "${config_file}" } if [[ "$(get_config CONFIG_PCI_P2PDMA)" == "y" ]]; then From 9e2109b3d6f7491aec9d3b109c3b39514836ae8b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 12 Feb 2025 17:00:19 +0800 Subject: [PATCH 1424/2653] drm/amdkcl: modify CONFIG_HSA_AMD_SVM to dkms-config.sh Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 9 --------- drivers/gpu/drm/amd/dkms/dkms-config.sh | 12 ++++++++++++ 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index ec9ed6319527a..8ce585dc8463f 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -27,8 +27,6 @@ endif include $(src)/amd/dkms/dkms-config.mk -_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") - DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) @@ -146,13 +144,6 @@ export CONFIG_DRM_SCHED=m subdir-ccflags-y += -Wno-error -ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) -ifdef CONFIG_DEVICE_PRIVATE -export CONFIG_HSA_AMD_SVM=y -subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM -endif -endif - # Trying to enable DCN2/3 with core2 optimizations will result in # older versions of GCC hanging during building/installing. Check # if the compiler is using core2 optimizations and only build DCN2/3 diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index 01e2a91ce242f..e36cab0da0394 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -4,6 +4,7 @@ local_config=$1 KERNELVER=$2 local_config_tmp=${local_config}.tmp config_file="/lib/modules/$KERNELVER/build/include/config/auto.conf" +kcl_config_file="amd/dkms/config/config.h" rm -f ${local_config_tmp} @@ -27,12 +28,23 @@ is_enabled() { grep -q "^$1=" "${config_file}" } +is_kcl_macro_defined() { + grep -q "define $1" "${kcl_config_file}" && echo "y" || echo "n" +} + if [[ "$(get_config CONFIG_PCI_P2PDMA)" == "y" ]]; then if [[ "$(get_config CONFIG_DMABUF_MOVENOTIFY)" == "y" ]]; then export_macro_mk CONFIG_HSA_AMD_P2P fi fi +# Check for HMM mirror configuration +if [[ "$(is_kcl_macro_defined HAVE_AMDKCL_HMM_MIRROR_ENABLED)" == "y" ]]; then + if is_enabled CONFIG_DEVICE_PRIVATE; then + export_macro_mk CONFIG_HSA_AMD_SVM + fi +fi + export_macro_mk CONFIG_HSA_AMD export_macro_mk CONFIG_DRM_AMDGPU_CIK export_macro_mk CONFIG_DRM_AMDGPU_SI From b3e9be178c3f34faedbe868c12dd3079f52c8a11 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 12 Feb 2025 13:52:40 +0800 Subject: [PATCH 1425/2653] drm/amdkcl: move OS check to dkms-config.sh Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 84 ---------------------- drivers/gpu/drm/amd/dkms/Makefile | 2 +- drivers/gpu/drm/amd/dkms/dkms-config.sh | 96 +++++++++++++++++++++++++ 3 files changed, 97 insertions(+), 85 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index 8ce585dc8463f..b71d645dc6264 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -39,90 +39,6 @@ subdir-ccflags-y += \ -DDRM_PATCH=$(DRM_PATCH) \ -DDRM_SUB="0" -define get_rhel_version -printf "#include \n$(1)" | $(CC) $(LINUXINCLUDE) -E -x c - | tail -n 1 | grep -v $(1) -endef -RHEL_MAJOR := $(shell $(call get_rhel_version,RHEL_MAJOR)) -RHEL_MINOR := $(shell $(call get_rhel_version,RHEL_MINOR)) - -ifneq (,$(RHEL_MAJOR)) -OS_NAME = "rhel" -OS_VERSION = "$(RHEL_MAJOR).$(RHEL_MINOR)" -else ifneq (,$(wildcard /etc/os-release)) -OS_NAME = "$(shell sed -n 's/^ID=\(.*\)/\1/p' /etc/os-release | tr -d '\"')" -# On CentOS/RHEL, users could have installed a kernel not distributed from RHEL -ifeq ("centos",$(OS_NAME)) -OS_NAME="custom-rhel" -else ifeq ("rhel",$(OS_NAME)) -OS_NAME="custom-rhel" -else ifeq ("linuxmint",$(OS_NAME)) -OS_NAME="ubuntu" -endif -OS_VERSION = $(shell sed -n 's/^VERSION_ID=\(.*\)/\1/p' /etc/os-release) -else -OS_NAME = "unknown" -OS_VERSION = "0.0" -endif - -OS_VERSION_STR = $(subst .,_,$(OS_VERSION)) - -ifeq ("ubuntu",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_UBUNTU -else ifeq ("rhel",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_RHEL -else ifeq ("steamos",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_STEAMOS -else ifeq ("sled",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_SLE -else ifeq ("sles",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_SLE -else ifeq ("amzn",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_AMZ -else ifeq ("debian",$(OS_NAME)) -subdir-ccflags-y += -DOS_NAME_DEBIAN -else -subdir-ccflags-y += -DOS_NAME_UNKNOWN -endif - -subdir-ccflags-y += \ - -DOS_VERSION_MAJOR=$(shell echo $(OS_VERSION).0 | cut -d. -f1) \ - -DOS_VERSION_MINOR=$(shell echo $(OS_VERSION).0 | cut -d. -f2) - -ifeq ($(OS_NAME),"opensuse-leap") -subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) -endif - -ifeq ($(OS_NAME),"sled") -subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) -endif - -ifeq ($(OS_NAME),"sles") -subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) -endif - -ifeq ($(OS_NAME),"ubuntu") -OS_BUILD_NUM = $(shell echo $(KERNELRELEASE) | cut -d '-' -f 2) -subdir-ccflags-y += -DUBUNTU_BUILD_NUM=$(OS_BUILD_NUM) -OS_OEM = "$(shell echo $(KERNELRELEASE) | cut -d '-' -f 3)" -ifeq ($(OS_OEM),"oem") -subdir-ccflags-y += -DOS_NAME_UBUNTU_OEM -endif -subdir-ccflags-y += -DOS_NAME_UBUNTU_$(OS_VERSION_STR) -endif - -ifeq ($(OS_NAME),"rhel") -subdir-ccflags-y += -DOS_NAME_RHEL_$(OS_VERSION_STR) - -ifeq ($(RHEL_MAJOR),7) -subdir-ccflags-y += -DOS_NAME_RHEL_7_X \ - -include /usr/src/kernels/$(KERNELRELEASE)/include/drm/drm_backport.h -else ifeq ($(RHEL_MAJOR),8) -subdir-ccflags-y += -DOS_NAME_RHEL_8_X -endif -endif - -export OS_NAME OS_VERSION - _KCL_LINUXINCLUDE=$(subst -I ,-I,$(strip $(LINUXINCLUDE))) LINUX_SRCTREE_INCLUDE := \ $(filter-out -I%/uapi "-include %/kconfig.h",$(_KCL_LINUXINCLUDE)) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index b16e2e453fe3e..5f9b0ca95f2fd 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -56,7 +56,7 @@ sanity-check: pre-build $(config-file) $(if $(call KCL_MACRO_CHECK_COMMAND, HAVE_RESERVATION_WW_CLASS_BUG), $(error reservation_ww_class is missing. exit...)) $(dkms-config): pre-build - $(Q)amd/dkms/dkms-config.sh $@ $(KERNELVER) + $(Q)amd/dkms/dkms-config.sh $@ $(KERNELVER) $(CC) pre-build: $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(module_build_dir) $(CC) diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index e36cab0da0394..3aef516a11857 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -2,9 +2,11 @@ local_config=$1 KERNELVER=$2 +CC=$3 local_config_tmp=${local_config}.tmp config_file="/lib/modules/$KERNELVER/build/include/config/auto.conf" kcl_config_file="amd/dkms/config/config.h" +kernel_include="/lib/modules/$KERNELVER/build/include" rm -f ${local_config_tmp} @@ -32,6 +34,100 @@ is_kcl_macro_defined() { grep -q "define $1" "${kcl_config_file}" && echo "y" || echo "n" } +# Get RHEL version +get_rhel_version() { + printf "#include \n$1" | $CC -I${kernel_include} -E -x c - | tail -n 1 | grep -v "$1" +} + +# Get RHEL major and minor version +RHEL_MAJOR=$(get_rhel_version "RHEL_MAJOR") +RHEL_MINOR=$(get_rhel_version "RHEL_MINOR") + +# Determine OS name and version +if [[ -n "${RHEL_MAJOR}" ]]; then + OS_NAME="rhel" + OS_VERSION="${RHEL_MAJOR}.${RHEL_MINOR}" +elif [[ -f /etc/os-release ]]; then + OS_NAME=$(grep -oP '(?<=^ID=).+' /etc/os-release | tr -d '"') + + # Handle special cases + case "${OS_NAME}" in + "centos") + OS_NAME="custom-rhel" + ;; + "rhel") + OS_NAME="custom-rhel" + ;; + "linuxmint") + OS_NAME="ubuntu" + ;; + esac + OS_VERSION=$(grep -oP '(?<=^VERSION_ID=).+' /etc/os-release | tr -d '"') +else + OS_NAME="unknown" + OS_VERSION="0.0" +fi + +OS_VERSION_STR=${OS_VERSION//./_} + +# Add OS specific defines +case "${OS_NAME}" in + "ubuntu") + append_mk "subdir-ccflags-y += -DOS_NAME_UBUNTU" + ;; + "rhel") + append_mk "subdir-ccflags-y += -DOS_NAME_RHEL" + ;; + "steamos") + append_mk "subdir-ccflags-y += -DOS_NAME_STEAMOS" + ;; + "sled"|"sles") + append_mk "subdir-ccflags-y += -DOS_NAME_SLE" + ;; + "amzn") + append_mk "subdir-ccflags-y += -DOS_NAME_AMZ" + ;; + "debian") + append_mk "subdir-ccflags-y += -DOS_NAME_DEBIAN" + ;; + *) + append_mk "subdir-ccflags-y += -DOS_NAME_UNKNOWN" + ;; +esac + +# Add OS specific compile flags +append_mk "subdir-ccflags-y += -DOS_VERSION_MAJOR=$(echo ${OS_VERSION}.0 | cut -d. -f1)" +append_mk "subdir-ccflags-y += -DOS_VERSION_MINOR=$(echo ${OS_VERSION}.0 | cut -d. -f2)" + +# Add additional OS specific configurations +case "${OS_NAME}" in + "opensuse-leap"|"sled"|"sles") + append_mk "subdir-ccflags-y += -DOS_NAME_SUSE_${OS_VERSION_STR}" + ;; + "ubuntu") + OS_BUILD_NUM=$(echo "${KERNELVER}" | cut -d '-' -f 2) + append_mk "subdir-ccflags-y += -DUBUNTU_BUILD_NUM=${OS_BUILD_NUM}" + OS_OEM=$(echo "${KERNELVER}" | cut -d '-' -f 3) + if [[ "${OS_OEM}" == "oem" ]]; then + append_mk "subdir-ccflags-y += -DOS_NAME_UBUNTU_OEM" + fi + append_mk "subdir-ccflags-y += -DOS_NAME_UBUNTU_${OS_VERSION_STR}" + ;; + "rhel") + append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_${OS_VERSION_STR}" + if [[ "${RHEL_MAJOR}" == "7" ]]; then + append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_7_X" + append_mk "-include /usr/src/kernels/${KERNELVER}/include/drm/drm_backport.h" + elif [[ "${RHEL_MAJOR}" == "8" ]]; then + append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_8_X" + fi + ;; +esac + +# Export variables +append_mk "export OS_NAME=${OS_NAME}" +append_mk "export OS_VERSION=${OS_VERSION}" + if [[ "$(get_config CONFIG_PCI_P2PDMA)" == "y" ]]; then if [[ "$(get_config CONFIG_DMABUF_MOVENOTIFY)" == "y" ]]; then export_macro_mk CONFIG_HSA_AMD_P2P From beb652546cec9718f07151feed93cd85c3e91ac0 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 12 Feb 2025 15:52:24 +0800 Subject: [PATCH 1426/2653] drm/amdkcl: unify VERSION_MAJOR and VERSION_MINOR Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/dkms-config.sh | 28 +++++++------------------ 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index 3aef516a11857..ddefbf6bed8ae 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -6,7 +6,6 @@ CC=$3 local_config_tmp=${local_config}.tmp config_file="/lib/modules/$KERNELVER/build/include/config/auto.conf" kcl_config_file="amd/dkms/config/config.h" -kernel_include="/lib/modules/$KERNELVER/build/include" rm -f ${local_config_tmp} @@ -34,21 +33,9 @@ is_kcl_macro_defined() { grep -q "define $1" "${kcl_config_file}" && echo "y" || echo "n" } -# Get RHEL version -get_rhel_version() { - printf "#include \n$1" | $CC -I${kernel_include} -E -x c - | tail -n 1 | grep -v "$1" -} - -# Get RHEL major and minor version -RHEL_MAJOR=$(get_rhel_version "RHEL_MAJOR") -RHEL_MINOR=$(get_rhel_version "RHEL_MINOR") - -# Determine OS name and version -if [[ -n "${RHEL_MAJOR}" ]]; then - OS_NAME="rhel" - OS_VERSION="${RHEL_MAJOR}.${RHEL_MINOR}" -elif [[ -f /etc/os-release ]]; then +if [[ -f /etc/os-release ]]; then OS_NAME=$(grep -oP '(?<=^ID=).+' /etc/os-release | tr -d '"') + OS_VERSION=$(grep -oP '(?<=^VERSION_ID=).+' /etc/os-release | tr -d '"') # Handle special cases case "${OS_NAME}" in @@ -62,12 +49,13 @@ elif [[ -f /etc/os-release ]]; then OS_NAME="ubuntu" ;; esac - OS_VERSION=$(grep -oP '(?<=^VERSION_ID=).+' /etc/os-release | tr -d '"') else OS_NAME="unknown" OS_VERSION="0.0" fi +VERSION_MAJOR=$(echo ${OS_VERSION}.0 | cut -d. -f1) +VERSION_MINOR=$(echo ${OS_VERSION}.0 | cut -d. -f2) OS_VERSION_STR=${OS_VERSION//./_} # Add OS specific defines @@ -96,8 +84,8 @@ case "${OS_NAME}" in esac # Add OS specific compile flags -append_mk "subdir-ccflags-y += -DOS_VERSION_MAJOR=$(echo ${OS_VERSION}.0 | cut -d. -f1)" -append_mk "subdir-ccflags-y += -DOS_VERSION_MINOR=$(echo ${OS_VERSION}.0 | cut -d. -f2)" +append_mk "subdir-ccflags-y += -DOS_VERSION_MAJOR=${VERSION_MAJOR}" +append_mk "subdir-ccflags-y += -DOS_VERSION_MINOR=${VERSION_MINOR}" # Add additional OS specific configurations case "${OS_NAME}" in @@ -115,10 +103,10 @@ case "${OS_NAME}" in ;; "rhel") append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_${OS_VERSION_STR}" - if [[ "${RHEL_MAJOR}" == "7" ]]; then + if [[ "${VERSION_MAJOR}" == "7" ]]; then append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_7_X" append_mk "-include /usr/src/kernels/${KERNELVER}/include/drm/drm_backport.h" - elif [[ "${RHEL_MAJOR}" == "8" ]]; then + elif [[ "${VERSION_MAJOR}" == "8" ]]; then append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_8_X" fi ;; From e1fd929a2c6956514a2c0609d10ef504d31a2c9f Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 17 Feb 2025 11:07:38 +0800 Subject: [PATCH 1427/2653] drm/amdkcl: test time64_to_tm() is available It's caused by the commit: 705048fb "drm/amdgpu: Get timestamp from system time" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_timeconv.c | 144 ++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/time64_to_tm.m4 | 17 +++ include/kcl/kcl_time.h | 13 ++ 7 files changed, 180 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_timeconv.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/time64_to_tm.m4 create mode 100644 include/kcl/kcl_time.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 5542e6b032f17..9243f279303ef 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -16,7 +16,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ - kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o + kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o kcl_debugfs_file.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_timeconv.c b/drivers/gpu/drm/amd/amdkcl/kcl_timeconv.c new file mode 100644 index 0000000000000..a32d8dd1a0c6e --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_timeconv.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: LGPL-2.0+ +/* +* Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc. +* This file is part of the GNU C Library. +* Contributed by Paul Eggert (eggert@twinsun.com). +* +* The GNU C Library is free software; you can redistribute it and/or +* modify it under the terms of the GNU Library General Public License as +* published by the Free Software Foundation; either version 2 of the +* License, or (at your option) any later version. +* +* The GNU C Library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* Library General Public License for more details. +* +* You should have received a copy of the GNU Library General Public +* License along with the GNU C Library; see the file COPYING.LIB. If not, +* write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +* Boston, MA 02111-1307, USA. +*/ + +/* +* Converts the calendar time to broken-down time representation +* +* 2009-7-14: +* Moved from glibc-2.6 to kernel by Zhaolei +* 2021-06-02: +* Reimplemented by Cassio Neri +*/ + +#ifndef HAVE_TIME64_TO_TM +#include +#include +#include +#include + +#define SECS_PER_HOUR (60 * 60) +#define SECS_PER_DAY (SECS_PER_HOUR * 24) + +/** + * time64_to_tm - converts the calendar time to local broken-down time + * + * @totalsecs: the number of seconds elapsed since 00:00:00 on January 1, 1970, + * Coordinated Universal Time (UTC). +* @offset: offset seconds adding to totalsecs. +* @result: pointer to struct tm variable to receive broken-down time +*/ +void time64_to_tm(time64_t totalsecs, int offset, struct tm *result) +{ + u32 u32tmp, day_of_century, year_of_century, day_of_year, month, day; + u64 u64tmp, udays, century, year; + bool is_Jan_or_Feb, is_leap_year; + long days, rem; + int remainder; + + days = div_s64_rem(totalsecs, SECS_PER_DAY, &remainder); + rem = remainder; + rem += offset; + while (rem < 0) { + rem += SECS_PER_DAY; + --days; + } + while (rem >= SECS_PER_DAY) { + rem -= SECS_PER_DAY; + ++days; + } + + result->tm_hour = rem / SECS_PER_HOUR; + rem %= SECS_PER_HOUR; + result->tm_min = rem / 60; + result->tm_sec = rem % 60; + + /* January 1, 1970 was a Thursday. */ + result->tm_wday = (4 + days) % 7; + if (result->tm_wday < 0) + result->tm_wday += 7; + + /* + * The following algorithm is, basically, Proposition 6.3 of Neri + * and Schneider [1]. In a few words: it works on the computational + * (fictitious) calendar where the year starts in March, month = 2 + * (*), and finishes in February, month = 13. This calendar is + * mathematically convenient because the day of the year does not + * depend on whether the year is leap or not. For instance: + * + * March 1st 0-th day of the year; + * ... + * April 1st 31-st day of the year; + * ... + * January 1st 306-th day of the year; (Important!) + * ... + * February 28th 364-th day of the year; + * February 29th 365-th day of the year (if it exists). + * + * After having worked out the date in the computational calendar + * (using just arithmetics) it's easy to convert it to the + * corresponding date in the Gregorian calendar. + * + * [1] "Euclidean Affine Functions and Applications to Calendar + * Algorithms". https://arxiv.org/abs/2102.06959 + * + * (*) The numbering of months follows tm more closely and thus, + * is slightly different from [1]. + */ + + udays = ((u64) days) + 2305843009213814918ULL; + + u64tmp = 4 * udays + 3; + century = div64_u64_rem(u64tmp, 146097, &u64tmp); + day_of_century = (u32) (u64tmp / 4); + + u32tmp = 4 * day_of_century + 3; + u64tmp = 2939745ULL * u32tmp; + year_of_century = upper_32_bits(u64tmp); + day_of_year = lower_32_bits(u64tmp) / 2939745 / 4; + + year = 100 * century + year_of_century; + is_leap_year = year_of_century ? !(year_of_century % 4) : !(century % 4); + + u32tmp = 2141 * day_of_year + 132377; + month = u32tmp >> 16; + day = ((u16) u32tmp) / 2141; + + /* + * Recall that January 1st is the 306-th day of the year in the + * computational (not Gregorian) calendar. + */ + is_Jan_or_Feb = day_of_year >= 306; + + /* Convert to the Gregorian calendar and adjust to Unix time. */ + year = year + is_Jan_or_Feb - 6313183731940000ULL; + month = is_Jan_or_Feb ? month - 12 : month; + day = day + 1; + day_of_year += is_Jan_or_Feb ? -306 : 31 + 28 + is_leap_year; + + /* Convert to tm's format. */ + result->tm_year = (long) (year - 1900); + result->tm_mon = (int) month; + result->tm_mday = (int) day; + result->tm_yday = (int) day_of_year; +} +EXPORT_SYMBOL(time64_to_tm); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index bd8b1813803c7..731f7eff573ad 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -141,4 +141,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 567c55f0c2c83..a6f02399c6316 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1093,6 +1093,9 @@ /* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 +/* time64_to_tm() is available */ +#define HAVE_TIME64_TO_TM 1 + /* topology_num_cores_per_package is availablea */ #define HAVE_TOPOLOGY_NUM_CORES_PER_PACKAGE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5148f7563834d..755543c55b551 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -262,6 +262,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS AC_AMDGPU_CEC_NOTIFIER_CONN_REGISTER AC_AMDGPU_STRUCT_CEC_CONNECTOR_INFO + AC_AMDGPU_TIME64_TO_TM AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/time64_to_tm.m4 b/drivers/gpu/drm/amd/dkms/m4/time64_to_tm.m4 new file mode 100644 index 0000000000000..052fe9b7b541f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/time64_to_tm.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v4.7-rc2-4-ge6c2682a1da3 +dnl # time: Add time64_to_tm() +dnl # +AC_DEFUN([AC_AMDGPU_TIME64_TO_TM], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + time64_to_tm(0, 0, NULL); + ], [time64_to_tm],[kernel/time/timeconv.c], [ + AC_DEFINE(HAVE_TIME64_TO_TM, 1, + [time64_to_tm() is available]) + + ]) + ]) +]) diff --git a/include/kcl/kcl_time.h b/include/kcl/kcl_time.h new file mode 100644 index 0000000000000..89856adc192a5 --- /dev/null +++ b/include/kcl/kcl_time.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_TIME_H +#define _KCL_TIME_H + +#include +#include +#include + +#ifndef HAVE_TIME64_TO_TM +void time64_to_tm(time64_t totalsecs, int offset, struct tm *result); +#endif + +#endif /* _KCL_TIME_H */ From 712fd13522b1ee7dc2be18de97d7050a68dc5820 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 12 Feb 2025 16:04:52 +0800 Subject: [PATCH 1428/2653] drm/amdkcl: unify OS compile flags Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/dkms-config.sh | 48 ++++--------------------- 1 file changed, 7 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index ddefbf6bed8ae..df28038e77b55 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -33,55 +33,25 @@ is_kcl_macro_defined() { grep -q "define $1" "${kcl_config_file}" && echo "y" || echo "n" } +# Export OS variables if [[ -f /etc/os-release ]]; then OS_NAME=$(grep -oP '(?<=^ID=).+' /etc/os-release | tr -d '"') OS_VERSION=$(grep -oP '(?<=^VERSION_ID=).+' /etc/os-release | tr -d '"') - - # Handle special cases - case "${OS_NAME}" in - "centos") - OS_NAME="custom-rhel" - ;; - "rhel") - OS_NAME="custom-rhel" - ;; - "linuxmint") - OS_NAME="ubuntu" - ;; - esac else OS_NAME="unknown" OS_VERSION="0.0" fi +append_mk "export OS_NAME=${OS_NAME}" +append_mk "export OS_VERSION=${OS_VERSION}" VERSION_MAJOR=$(echo ${OS_VERSION}.0 | cut -d. -f1) VERSION_MINOR=$(echo ${OS_VERSION}.0 | cut -d. -f2) OS_VERSION_STR=${OS_VERSION//./_} +OS_NAME_STR=$(echo ${OS_NAME} | tr a-z A-Z) -# Add OS specific defines -case "${OS_NAME}" in - "ubuntu") - append_mk "subdir-ccflags-y += -DOS_NAME_UBUNTU" - ;; - "rhel") - append_mk "subdir-ccflags-y += -DOS_NAME_RHEL" - ;; - "steamos") - append_mk "subdir-ccflags-y += -DOS_NAME_STEAMOS" - ;; - "sled"|"sles") - append_mk "subdir-ccflags-y += -DOS_NAME_SLE" - ;; - "amzn") - append_mk "subdir-ccflags-y += -DOS_NAME_AMZ" - ;; - "debian") - append_mk "subdir-ccflags-y += -DOS_NAME_DEBIAN" - ;; - *) - append_mk "subdir-ccflags-y += -DOS_NAME_UNKNOWN" - ;; -esac +# Generate macros related to the operating system to support compilation. +# The OS name is converted to uppercase and appended as a flag, e.g., -DOS_NAME_UBUNTU, -DOS_NAME_RHEL. +append_mk "subdir-ccflags-y += -DOS_NAME_${OS_NAME_STR}" # Add OS specific compile flags append_mk "subdir-ccflags-y += -DOS_VERSION_MAJOR=${VERSION_MAJOR}" @@ -112,10 +82,6 @@ case "${OS_NAME}" in ;; esac -# Export variables -append_mk "export OS_NAME=${OS_NAME}" -append_mk "export OS_VERSION=${OS_VERSION}" - if [[ "$(get_config CONFIG_PCI_P2PDMA)" == "y" ]]; then if [[ "$(get_config CONFIG_DMABUF_MOVENOTIFY)" == "y" ]]; then export_macro_mk CONFIG_HSA_AMD_P2P From 0029feb7353bd14b062d5e2be267c15244d97bd0 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 18 Feb 2025 16:37:33 +0800 Subject: [PATCH 1429/2653] drm/amdkcl: fix the compiler error with not include drm_backport.h correctly in rhel7.9 Signed-off-by: chengjya reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/dkms-config.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index df28038e77b55..35cc0edc29944 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -75,7 +75,7 @@ case "${OS_NAME}" in append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_${OS_VERSION_STR}" if [[ "${VERSION_MAJOR}" == "7" ]]; then append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_7_X" - append_mk "-include /usr/src/kernels/${KERNELVER}/include/drm/drm_backport.h" + append_mk "subdir-ccflags-y += -include /usr/src/kernels/${KERNELVER}/include/drm/drm_backport.h" elif [[ "${VERSION_MAJOR}" == "8" ]]; then append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_8_X" fi From b7a4904a8bc155d72595c92579a141eb8da65a21 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 18 Feb 2025 14:15:30 +0800 Subject: [PATCH 1430/2653] drm/amdkcl: test the marco define umin is available It's caused by the commit: b4930d6c "drm/amdgpu: add data write function for CPER ring" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/linux/minmax.h | 12 ++++++++++++ include/kcl/kcl_minmax.h | 12 ++++++++++++ 5 files changed, 33 insertions(+) create mode 100644 include/kcl/header/linux/minmax.h create mode 100644 include/kcl/kcl_minmax.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 731f7eff573ad..b5d20adccce35 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -142,4 +142,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a6f02399c6316..4631c4463cd6f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -870,6 +870,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_MMAP_LOCK_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_MINMAX_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PCI_P2PDMA_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 661896d6ee4c2..1fc123af76d47 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -149,4 +149,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #drm: Implement DRM aperture helpers under video/ dnl AC_KERNEL_CHECK_HEADERS([linux/aperture.h]) + + dnl #v5.9-7812-gb296a6d53339 + dnl #kernel.h: split out min()/max() et al. helpers + dnl + AC_KERNEL_CHECK_HEADERS([linux/minmax.h]) ]) diff --git a/include/kcl/header/linux/minmax.h b/include/kcl/header/linux/minmax.h new file mode 100644 index 0000000000000..5bc1bc525e230 --- /dev/null +++ b/include/kcl/header/linux/minmax.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_MINMAX_H +#define _KCL_HEADER_LINUX_MINMAX_H + +#ifdef HAVE_LINUX_MINMAX_H +#include_next +#else +#include +#endif + +#endif + diff --git a/include/kcl/kcl_minmax.h b/include/kcl/kcl_minmax.h new file mode 100644 index 0000000000000..618e166564d98 --- /dev/null +++ b/include/kcl/kcl_minmax.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_MINMAX_H +#define _KCL_MINMAX_H + +#include + +#ifndef umin +#define umin(x, y) \ + min((x) + 0u + 0ul + 0ull, (y) + 0u + 0ul + 0ull) +#endif + +#endif /* _KCL_MINMAX_H */ From 463ad8d23d8a9a897bc8c5a06322265513f8a4e1 Mon Sep 17 00:00:00 2001 From: chengjya Date: Wed, 19 Feb 2025 18:08:18 +0800 Subject: [PATCH 1431/2653] drm/amdkcl: fix the range of macro define HAVE_DRM_SHOW_FDINFO Signed-off-by: chengjya --- drivers/gpu/drm/amd/backport/kcl_drm_file.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_file.c b/drivers/gpu/drm/amd/backport/kcl_drm_file.c index a6d0cea48cecf..1a0fb154a34c2 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_file.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_file.c @@ -67,6 +67,7 @@ void drm_show_fdinfo(struct seq_file *m, struct file *f) amdgpu_show_fdinfo(&p, file); } +#endif #ifndef HAVE_DRM_PRINT_MEMORY_STATS static void print_size(struct drm_printer *p, const char *stat, @@ -101,5 +102,3 @@ void _kcl_drm_print_memory_stats(struct drm_printer *p, } EXPORT_SYMBOL(_kcl_drm_print_memory_stats); #endif - -#endif From 0be88dac6e52b44eac350e8a1a4f0f6a78bf3fc5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 19 Feb 2025 15:21:42 +0800 Subject: [PATCH 1432/2653] drm/amdkcl: move drm check to dkms-config.sh Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 12 ------------ drivers/gpu/drm/amd/dkms/dkms-config.sh | 18 +++++++++++++++--- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index b71d645dc6264..9e50bcdaab092 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -27,18 +27,6 @@ endif include $(src)/amd/dkms/dkms-config.mk -DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) -DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) -ifeq ($(DRM_VER),) -DRM_VER = $(VERSION) -DRM_PATCH = $(PATCHLEVEL) -endif - -subdir-ccflags-y += \ - -DDRM_VER=$(DRM_VER) \ - -DDRM_PATCH=$(DRM_PATCH) \ - -DDRM_SUB="0" - _KCL_LINUXINCLUDE=$(subst -I ,-I,$(strip $(LINUXINCLUDE))) LINUX_SRCTREE_INCLUDE := \ $(filter-out -I%/uapi "-include %/kconfig.h",$(_KCL_LINUXINCLUDE)) diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index 35cc0edc29944..3c30f3d4735c6 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -4,7 +4,8 @@ local_config=$1 KERNELVER=$2 CC=$3 local_config_tmp=${local_config}.tmp -config_file="/lib/modules/$KERNELVER/build/include/config/auto.conf" +kernel_build_dir="/lib/modules/$KERNELVER/build" +kconfig_file="${kernel_build_dir}/include/config/auto.conf" kcl_config_file="amd/dkms/config/config.h" rm -f ${local_config_tmp} @@ -22,11 +23,11 @@ _DKMS_CONFIG } get_config() { - grep "^$1=" "${config_file}" | awk -F= '{print $2}' + grep "^$1=" "${kconfig_file}" | awk -F= '{print $2}' } is_enabled() { - grep -q "^$1=" "${config_file}" + grep -q "^$1=" "${kconfig_file}" } is_kcl_macro_defined() { @@ -82,6 +83,17 @@ case "${OS_NAME}" in ;; esac +# Extract DRM version and patch level from the main Makefile +DRM_VER=$(sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' ${kernel_build_dir}/Makefile) +DRM_PATCH=$(sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' ${kernel_build_dir}/Makefile) + +if [ -z "${DRM_VER}" ]; then + DRM_VER=$(echo ${KERNELVER} | cut -d. -f1) + DRM_PATCH=$(echo ${KERNELVER} | cut -d. -f2) +fi + +append_mk "subdir-ccflags-y += -DDRM_VER=${DRM_VER} -DDRM_PATCH=${DRM_PATCH} -DDRM_SUB=\"0\"" + if [[ "$(get_config CONFIG_PCI_P2PDMA)" == "y" ]]; then if [[ "$(get_config CONFIG_DMABUF_MOVENOTIFY)" == "y" ]]; then export_macro_mk CONFIG_HSA_AMD_P2P From a932d315596ae6c0dfa78228f268c1f86dcd40ee Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 21 Feb 2025 15:26:24 +0800 Subject: [PATCH 1433/2653] drm/amdkcl: fix macro _KCL_HEADER_DRM_ELD_H_H_ Signed-off-by: Bob Zhou Reviewed-by: Chengjun Yao --- include/kcl/header/drm/drm_eld.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/header/drm/drm_eld.h b/include/kcl/header/drm/drm_eld.h index e531edccae0d7..e9bd6120c7b93 100644 --- a/include/kcl/header/drm/drm_eld.h +++ b/include/kcl/header/drm/drm_eld.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: MIT */ #ifndef _KCL_HEADER_DRM_ELD_H_ -#define _KCL_HEADER_DRM_ELD_H_H_ +#define _KCL_HEADER_DRM_ELD_H_ #ifdef HAVE_DRM_DRM_ELD_H #include_next From 0604f1951db80e56a4cf60fcd4c8fb6bb18215ca Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 24 Feb 2025 11:25:39 +0800 Subject: [PATCH 1434/2653] drm/amdkcl: fix the redefinetion about the struct dc_link *dc_link It's caused by the following commit: 69b01ad9e "drm/amd/display: restore edid reading from a given i2c adapter" It re-defines 'dc_link' , will conflicts with its definition in KCL. Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 76400b75920c1..4b811766c7067 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7678,10 +7678,10 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector) .link = aconnector->dc_link, .sink_signal = SIGNAL_TYPE_VIRTUAL }; + struct i2c_adapter *ddc; #ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid; const struct edid *edid; - struct i2c_adapter *ddc; if (dc_link && dc_link->aux_mode) ddc = &aconnector->dm_dp_aux.aux.ddc; @@ -7692,9 +7692,7 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector) drm_edid_connector_update(connector, drm_edid); if (!drm_edid) { #else - struct dc_link *dc_link = aconnector->dc_link; struct edid *edid; - struct i2c_adapter *ddc; if (dc_link->aux_mode) ddc = &aconnector->dm_dp_aux.aux.ddc; From d798d43765defe9ce3c547aff0a33eda1c6eac36 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 24 Feb 2025 10:37:02 +0800 Subject: [PATCH 1435/2653] drm/amdkcl: Fix compilation error when CONFIG_PM is undefined When CONFIG_PM is not defined, pm_runtime_get_if_active() is not exported as a symbol but exists as an inline function. Remove the CONFIG_PM limitation in kcl_pm_runtime.h and simply include pm_runtime. Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 | 8 ++++---- include/kcl/kcl_pm_runtime.h | 2 -- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 index 9615da53282ad..f694f53991e2c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 @@ -4,19 +4,19 @@ dnl # PM: runtime: Add pm_runtime_get_if_active() dnl # AC_DEFUN([AC_AMDGPU_PM_RUNTIME_GET_IF_ACTIVE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ + AC_KERNEL_TRY_COMPILE([ #include ],[ pm_runtime_get_if_active(NULL); - ],[pm_runtime_get_if_active],[drivers\base\power\runtime.c],[ + ],[ AC_DEFINE(HAVE_PM_RUNTIME_GET_IF_ACTIVE_1ARGS, 1, [pm_runtime_get_if_active() has one parameters]) ],[ - AC_KERNEL_TRY_COMPILE_SYMBOL([ + AC_KERNEL_TRY_COMPILE([ #include ],[ pm_runtime_get_if_active(NULL, 0); - ],[pm_runtime_get_if_active],[drivers\base\power\runtime.c],[ + ],[ AC_DEFINE(HAVE_PM_RUNTIME_GET_IF_ACTIVE_2ARGS, 1, [pm_runtime_get_if_active() has two parameters]) ]) diff --git a/include/kcl/kcl_pm_runtime.h b/include/kcl/kcl_pm_runtime.h index 54df71e7b5b24..cf5a65586fc55 100644 --- a/include/kcl/kcl_pm_runtime.h +++ b/include/kcl/kcl_pm_runtime.h @@ -24,7 +24,6 @@ static inline int pm_runtime_resume_and_get(struct device *dev) } #endif -#ifdef CONFIG_PM #if defined(HAVE_PM_RUNTIME_GET_IF_ACTIVE_2ARGS) static inline int _kcl_pm_runtime_get_if_active(struct device *dev) { @@ -38,6 +37,5 @@ static inline int _kcl_pm_runtime_get_if_active(struct device *dev) } #define pm_runtime_get_if_active _kcl_pm_runtime_get_if_active #endif /* HAVE_PM_RUNTIME_GET_IF_ACTIVE_2ARGS */ -#endif /* CONFIG_PM */ #endif /* KCL_KCL_PM_RUNTIME_H */ \ No newline at end of file From f6752dc40dbbc0cca94e8c76345ec0451a20524b Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 24 Feb 2025 10:43:05 +0800 Subject: [PATCH 1436/2653] drm/amdkcl: Fix compilation error caused by assigning a pointer to a constant to a normal pointer Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4b811766c7067..2e99c1ae7b993 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3807,11 +3807,12 @@ void amdgpu_dm_update_connector_after_detect( drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); } } else { - const struct edid *edid = (const struct edid *)sink->dc_edid.raw_edid; #ifdef HAVE_DRM_DP_MST_EDID_READ + const struct edid *edid = (const struct edid *)sink->dc_edid.raw_edid; aconnector->drm_edid = drm_edid_alloc(edid, sink->dc_edid.length); drm_edid_connector_update(connector, aconnector->drm_edid); #else + struct edid *edid = (struct edid *)sink->dc_edid.raw_edid; aconnector->edid = edid; #endif From 800a4f7898f1e29e401bc915f4199cc84545b772 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 21 Feb 2025 15:21:47 +0800 Subject: [PATCH 1437/2653] drm/amdkcl: fix dml Makefile to support clang Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/dc/dml/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile index bfd2f14f57681..b12dee2ba122b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile @@ -49,9 +49,11 @@ endif include $(src)/../dkms/Makefile.compiler +ifdef CONFIG_CC_IS_GCC ifneq ($(call gcc-min-version, 70100),y) IS_OLD_GCC = 1 endif +endif ifdef CONFIG_X86 ifdef IS_OLD_GCC From 6f1ef3153781dd90e1b4007dc7e9aeefc92bf3c7 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 24 Feb 2025 11:29:43 +0800 Subject: [PATCH 1438/2653] drm/amdkcl: fix autoconf compiler CFLAGS for clang Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index f8f51b0d19c7a..4eb72d9844e0e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -13,7 +13,7 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ -e "s|-I\([[[a-z]]]*\)|-I${LINUX_OBJ}/\1|g" \ -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|g" \ -e "s|$PWD|\${PWD}|g") - CFLAGS=$(echo $CFLAGS | sed -E 's/-W(array-bounds|error=array-bounds|unused-variable|error=unused-variable|unused-.*-variable|error=unused-.*-variable)( |$)//g') + CFLAGS=$(echo $CFLAGS | sed -E 's/-W(array-bounds|error=array-bounds|unused-variable|error=unused-variable|unused-[^ ]*-variable|error=unused-[^ ]*-variable)( |$)//g') CPPFLAGS=$(echo $CFLAGS | \ cut -d ';' -f 1 | \ From 8106551404b736ac29e6117c04da41eccb31cb71 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 24 Feb 2025 18:11:57 +0800 Subject: [PATCH 1439/2653] drm/amdkcl: open CONFIG_DRM_AMD_DC_FP for clang compiler Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Kbuild | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index 9e50bcdaab092..d4ab165eeaf09 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -53,10 +53,13 @@ subdir-ccflags-y += -Wno-error # if the compiler is using core2 optimizations and only build DCN2/3 # if core2 isn't in the compiler flags ifndef CONFIG_ARM64 -ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) -export CONFIG_DRM_AMD_DC_FP=y -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_FP -endif + ifeq ($(CC), clang) + export CONFIG_DRM_AMD_DC_FP=y + subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_FP + else ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) + export CONFIG_DRM_AMD_DC_FP=y + subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_FP + endif endif # v5.17-rc4-3-ge8c07082a810 (Kbuild: move to -std=gnu11) From 57f4da26613ba860e5cbe8ce02e4cd79bb5d584e Mon Sep 17 00:00:00 2001 From: tiancyin Date: Thu, 27 Feb 2025 15:40:16 +0800 Subject: [PATCH 1440/2653] drm/amdgpu: [hybrid] disable dGMA when iommu is enabled and not in PT mode [why] In direct GMA(peer to peer vram access), the initiator GPU's PTE is populated with system physical address, which should be IOVA(from dma_map_page). Just disable the dGMA when IOMMU is enabled and not in pass through mode. Reviewed-by: Flora Cui Signed-off-by: tiancyin --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index dd4dbd0b29e74..57b1ef3712225 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2115,6 +2115,14 @@ static int amdgpu_direct_gma_init(struct amdgpu_device *adev) unsigned long size; int r; + if (amdgpu_direct_gma_size > 0) { + struct iommu_domain *dom = iommu_get_domain_for_dev(adev->dev); + if (dom && domain->type != IOMMU_DOMAIN_IDENTITY) { + DRM_INFO("IOMMU is enabled and not in pass through mode, disable direct GMA\n"); + amdgpu_direct_gma_size = 0; + } + } + if (amdgpu_direct_gma_size == 0) return 0; From 6f455980005751cfd5742662ffa1f43aa8f8a42b Mon Sep 17 00:00:00 2001 From: chengjya Date: Thu, 27 Feb 2025 18:18:26 +0800 Subject: [PATCH 1441/2653] drm/amdkcl : Corrected the usage of an incorrect variable name It's caused by the following commit: 3529abc32 "drm/amdgpu: [hybrid] disable dGMA when iommu is enabled and not in PT mode" Signed-off-by: chengjya --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 57b1ef3712225..c37cae6a51751 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2117,7 +2117,7 @@ static int amdgpu_direct_gma_init(struct amdgpu_device *adev) if (amdgpu_direct_gma_size > 0) { struct iommu_domain *dom = iommu_get_domain_for_dev(adev->dev); - if (dom && domain->type != IOMMU_DOMAIN_IDENTITY) { + if (dom && dom->type != IOMMU_DOMAIN_IDENTITY) { DRM_INFO("IOMMU is enabled and not in pass through mode, disable direct GMA\n"); amdgpu_direct_gma_size = 0; } From aff8bf33d6dd572e5ce79c95177b8831aa430d22 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Tue, 26 Nov 2024 11:08:02 -0500 Subject: [PATCH 1442/2653] drm/amdkfd: update cwsr trap handler to support both Host Trap and Stochastic PC sampling running simultaneously. -v2: read register HW_REG_TRAPSTS to check TRAPSTS_PERF_SNAPSHOT Co-developed-by: Lancelot SIX Co-developed-by: Joseph Greathouse Signed-off-by: James Zhu Reviewed-by: Shweta Khatri --- .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 2798 +++++++++-------- .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 71 +- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 3 +- 3 files changed, 1467 insertions(+), 1405 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index e0d44552b727c..5cb39cd646e8a 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -274,13 +274,13 @@ static const uint32_t cwsr_trap_gfx8_hex[] = { static const uint32_t cwsr_trap_gfx9_hex[] = { - 0xbf820001, 0xbf820267, + 0xbf820001, 0xbf820268, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840008, 0xbf0d986d, 0xbf850023, 0x866eff7b, - 0x00000400, 0xbf850065, + 0x00000400, 0xbf850066, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03800900, 0xbf850019, @@ -296,7 +296,7 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0x00000800, 0xbf850005, 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850046, 0xbeed1a9d, + 0xbf850047, 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8977ff77, 0xfc000000, @@ -309,230 +309,187 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, 0xbf8cc07f, 0x8e799779, - 0x8977ff77, 0x01800000, + 0x8977ff77, 0x03800000, 0x87777977, 0xbf0d986d, - 0xbf840009, 0xbf0d9877, - 0xbf850007, 0x896dff6d, - 0x01ff0000, 0xba7f0583, - 0x00000000, 0xbf0d9d6d, - 0xbeed189d, 0xbf840012, - 0xbef71898, 0xbeed189d, - 0x86ee6e6e, 0xbf840001, - 0xbe801d6e, 0x866eff6d, - 0x01ff0000, 0xbf850005, - 0x8778ff78, 0x00002000, - 0x80ec886c, 0x82ed806d, - 0xbf820005, 0x866eff6d, - 0x01000000, 0xbf850002, - 0x806c846c, 0x826d806d, - 0x866dff6d, 0x0000ffff, - 0x8f7a8b77, 0x867aff7a, - 0x001f8000, 0xb97af807, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e8378, 0xb96ee0c2, - 0xbf800002, 0xb9780002, - 0xbe801f6c, 0x866dff6d, - 0x0000ffff, 0xbefa0080, - 0xb97a0283, 0xb8faf807, + 0xbf840006, 0xbf0d9877, + 0xbf840002, 0xbeed1a9d, + 0xbf820002, 0x896dff6d, + 0x01ff0000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840013, + 0xbef71898, 0xbef71899, + 0xbeed189d, 0x86ee6e6e, + 0xbf840001, 0xbe801d6e, + 0x866eff6d, 0x01ff0000, + 0xbf850005, 0x8778ff78, + 0x00002000, 0x80ec886c, + 0x82ed806d, 0xbf820005, + 0x866eff6d, 0x01000000, + 0xbf850002, 0x806c846c, + 0x826d806d, 0x866dff6d, + 0x0000ffff, 0x8f7a8b77, 0x867aff7a, 0x001f8000, - 0x8e7a8b7a, 0x8977ff77, - 0xfc000000, 0x87777a77, - 0xba7ff807, 0x00000000, - 0xbeee007e, 0xbeef007f, - 0xbefe0180, 0xbf900004, - 0x877a8478, 0xb97af802, - 0xbf8e0002, 0xbf88fffe, - 0xb8fa2a05, 0x807a817a, - 0x8e7a8a7a, 0xb8fb1605, - 0x807b817b, 0x8e7b867b, - 0x807a7b7a, 0x807a7e7a, - 0x827b807f, 0x867bff7b, - 0x0000ffff, 0xc04b1c3d, - 0x00000050, 0xbf8cc07f, - 0xc04b1d3d, 0x00000060, - 0xbf8cc07f, 0xc0431e7d, - 0x00000074, 0xbf8cc07f, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0xbef1007c, 0xbef00080, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b3a, + 0xb97af807, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e8378, + 0xb96ee0c2, 0xbf800002, + 0xb9780002, 0xbe801f6c, + 0x866dff6d, 0x0000ffff, + 0xbefa0080, 0xb97a0283, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8977ff77, 0xfc000000, + 0x87777a77, 0xba7ff807, + 0x00000000, 0xbeee007e, + 0xbeef007f, 0xbefe0180, + 0xbf900004, 0x877a8478, + 0xb97af802, 0xbf8e0002, + 0xbf88fffe, 0xb8fa2a05, + 0x807a817a, 0x8e7a8a7a, + 0xb8fb1605, 0x807b817b, + 0x8e7b867b, 0x807a7b7a, + 0x807a7e7a, 0x827b807f, + 0x867bff7b, 0x0000ffff, + 0xc04b1c3d, 0x00000050, + 0xbf8cc07f, 0xc04b1d3d, + 0x00000060, 0xbf8cc07f, + 0xc0431e7d, 0x00000074, + 0xbf8cc07f, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0xbef1007c, + 0xbef00080, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611b7a, 0x0000007c, + 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bba, + 0xbefc0070, 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bfa, 0x0000007c, + 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611e3a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8fbf803, 0xbefe007c, - 0xbefc0070, 0xc0611efa, + 0xbefc0070, 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a3a, 0x0000007c, + 0xc0611e3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8fbf803, + 0xbefe007c, 0xbefc0070, + 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8f1f801, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, + 0xbefc0070, 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xbefe007c, 0xbefc0070, + 0xc0611a7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8f1f801, + 0xbefe007c, 0xbefc0070, + 0xc0611c7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf85004d, 0xbe840080, + 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840063, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf84005f, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850030, - 0x24040682, 0xd86e4000, - 0x00000002, 0xbf8cc07f, 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000200, - 0xd0c9006a, 0x0000f702, - 0xbf87ffd2, 0xbf820015, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbf87fff7, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2a05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, - 0x807bff7b, 0x00001000, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb4306, 0x867bc17b, + 0xbf840063, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf84005f, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, + 0xbf850030, 0x24040682, + 0xd86e4000, 0x00000002, + 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -551,145 +508,188 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x680404ff, + 0x00000200, 0xd0c9006a, + 0x0000f702, 0xbf87ffd2, + 0xbf820015, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbf87fff7, 0xbef70000, + 0xbef000ff, 0x00000400, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb2a05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850051, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0x807c847c, 0x8070ff70, - 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xbf8200c7, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf84001e, - 0xbefe00c1, 0xbeff00c1, - 0xb8ef4306, 0x866fc16f, - 0xbf840019, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82a05, 0x80788178, - 0x8e788a78, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0x807cff7c, 0x00000200, - 0x8078ff78, 0x00000200, - 0xbf0a6f7c, 0xbf85fff6, - 0xbefe00c1, 0xbeff00c1, - 0xbef600ff, 0x01000000, - 0xb8ef2a05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, - 0xbf11087c, 0xe0524000, - 0x781d0000, 0xe0524100, - 0x781d0100, 0xe0524200, - 0x781d0200, 0xe0524300, - 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0x807c847c, 0x8078ff78, - 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82a05, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xbf8200c7, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf84001e, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf840019, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82a05, 0x80788178, 0x8e788a78, 0xb8ee1605, 0x806e816e, 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, + 0x8078ff78, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0x807cff7c, + 0x00000200, 0x8078ff78, + 0x00000200, 0xbf0a6f7c, + 0xbf85fff6, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2a05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, 0xb8f82a05, 0x80788178, 0x8e788a78, 0xb8ee1605, 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82a05, + 0x80788178, 0x8e788a78, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2a05, 0x806e816e, - 0x8e6e8a6e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b77, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, -}; - -static const uint32_t cwsr_trap_nv1x_hex[] = { - 0xbf820001, 0xbf820393, - 0xb0804004, 0xb978f802, - 0x8a78ff78, 0x00020006, - 0xb97bf803, 0x876eff78, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2a05, + 0x806e816e, 0x8e6e8a6e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b77, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, +}; + +static const uint32_t cwsr_trap_nv1x_hex[] = { + 0xbf820001, 0xbf820393, + 0xb0804004, 0xb978f802, + 0x8a78ff78, 0x00020006, + 0xb97bf803, 0x876eff78, 0x00002000, 0xbf840009, 0x876eff6d, 0x00ff0000, 0xbf85001e, 0x876eff7b, @@ -1310,13 +1310,13 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { }; static const uint32_t cwsr_trap_arcturus_hex[] = { - 0xbf820001, 0xbf8202e3, + 0xbf820001, 0xbf8202e4, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840008, 0xbf0d986d, 0xbf850023, 0x866eff7b, - 0x00000400, 0xbf850065, + 0x00000400, 0xbf850066, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03800900, 0xbf850019, @@ -1332,7 +1332,7 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0x00000800, 0xbf850005, 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850046, 0xbeed1a9d, + 0xbf850047, 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8977ff77, 0xfc000000, @@ -1345,232 +1345,189 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, 0xbf8cc07f, 0x8e799779, - 0x8977ff77, 0x01800000, + 0x8977ff77, 0x03800000, 0x87777977, 0xbf0d986d, - 0xbf840009, 0xbf0d9877, - 0xbf850007, 0x896dff6d, - 0x01ff0000, 0xba7f0583, - 0x00000000, 0xbf0d9d6d, - 0xbeed189d, 0xbf840012, - 0xbef71898, 0xbeed189d, - 0x86ee6e6e, 0xbf840001, - 0xbe801d6e, 0x866eff6d, - 0x01ff0000, 0xbf850005, - 0x8778ff78, 0x00002000, - 0x80ec886c, 0x82ed806d, - 0xbf820005, 0x866eff6d, - 0x01000000, 0xbf850002, - 0x806c846c, 0x826d806d, - 0x866dff6d, 0x0000ffff, - 0x8f7a8b77, 0x867aff7a, - 0x001f8000, 0xb97af807, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e8378, 0xb96ee0c2, - 0xbf800002, 0xb9780002, - 0xbe801f6c, 0x866dff6d, - 0x0000ffff, 0xbefa0080, - 0xb97a0283, 0xb8faf807, + 0xbf840006, 0xbf0d9877, + 0xbf840002, 0xbeed1a9d, + 0xbf820002, 0x896dff6d, + 0x01ff0000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840013, + 0xbef71898, 0xbef71899, + 0xbeed189d, 0x86ee6e6e, + 0xbf840001, 0xbe801d6e, + 0x866eff6d, 0x01ff0000, + 0xbf850005, 0x8778ff78, + 0x00002000, 0x80ec886c, + 0x82ed806d, 0xbf820005, + 0x866eff6d, 0x01000000, + 0xbf850002, 0x806c846c, + 0x826d806d, 0x866dff6d, + 0x0000ffff, 0x8f7a8b77, 0x867aff7a, 0x001f8000, - 0x8e7a8b7a, 0x8977ff77, - 0xfc000000, 0x87777a77, - 0xba7ff807, 0x00000000, - 0xbeee007e, 0xbeef007f, - 0xbefe0180, 0xbf900004, - 0x877a8478, 0xb97af802, - 0xbf8e0002, 0xbf88fffe, - 0xb8fa2a05, 0x807a817a, - 0x8e7a8a7a, 0x8e7a817a, - 0xb8fb1605, 0x807b817b, - 0x8e7b867b, 0x807a7b7a, - 0x807a7e7a, 0x827b807f, - 0x867bff7b, 0x0000ffff, - 0xc04b1c3d, 0x00000050, - 0xbf8cc07f, 0xc04b1d3d, - 0x00000060, 0xbf8cc07f, - 0xc0431e7d, 0x00000074, - 0xbf8cc07f, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0xbef1007c, - 0xbef00080, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b3a, + 0xb97af807, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e8378, + 0xb96ee0c2, 0xbf800002, + 0xb9780002, 0xbe801f6c, + 0x866dff6d, 0x0000ffff, + 0xbefa0080, 0xb97a0283, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8977ff77, 0xfc000000, + 0x87777a77, 0xba7ff807, + 0x00000000, 0xbeee007e, + 0xbeef007f, 0xbefe0180, + 0xbf900004, 0x877a8478, + 0xb97af802, 0xbf8e0002, + 0xbf88fffe, 0xb8fa2a05, + 0x807a817a, 0x8e7a8a7a, + 0x8e7a817a, 0xb8fb1605, + 0x807b817b, 0x8e7b867b, + 0x807a7b7a, 0x807a7e7a, + 0x827b807f, 0x867bff7b, + 0x0000ffff, 0xc04b1c3d, + 0x00000050, 0xbf8cc07f, + 0xc04b1d3d, 0x00000060, + 0xbf8cc07f, 0xc0431e7d, + 0x00000074, 0xbf8cc07f, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0xbef1007c, 0xbef00080, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611b7a, 0x0000007c, + 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bba, + 0xbefc0070, 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bfa, 0x0000007c, + 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611e3a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8fbf803, 0xbefe007c, - 0xbefc0070, 0xc0611efa, + 0xbefc0070, 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a3a, 0x0000007c, + 0xc0611e3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8fbf803, + 0xbefe007c, 0xbefc0070, + 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8f1f801, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, + 0xbefc0070, 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, - 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, - 0xbef600ff, 0x01000000, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, + 0xbefe007c, 0xbefc0070, + 0xc0611a7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8f1f801, + 0xbefe007c, 0xbefc0070, + 0xc0611c7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85004d, 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb4306, 0x867bc17b, - 0xbf840064, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf840060, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850030, - 0x24040682, 0xd86e4000, - 0x00000002, 0xbf8cc07f, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000903, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000200, - 0xd0c9006a, 0x0000f702, - 0xbf87ffd2, 0xbf820015, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbf87fff7, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2a05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, - 0x807bff7b, 0x00001000, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb4306, + 0x867bc17b, 0xbf840064, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf840060, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, + 0xbf850030, 0x24040682, + 0xd86e4000, 0x00000002, + 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -1589,222 +1546,265 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x680404ff, + 0x00000200, 0xd0c9006a, + 0x0000f702, 0xbf87ffd2, + 0xbf820015, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbf87fff7, 0xbef70000, + 0xbef000ff, 0x00000400, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb2a05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850051, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0x807c847c, 0x8070ff70, - 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xbefc0080, 0xbf11017c, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf850059, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xbe840080, - 0xd2890000, 0x00000900, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, + 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffa9, - 0xbf9c0000, 0xbf820016, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0x807c847c, 0x8070ff70, - 0x00000400, 0xbf0a7b7c, - 0xbf85ffeb, 0xbf9c0000, - 0xbf8200e3, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf84001f, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf8200e3, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf84001f, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf84001a, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82a05, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, 0xbefe00c1, 0xbeff00c1, - 0xb8ef4306, 0x866fc16f, - 0xbf84001a, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82a05, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2a05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xbefc0080, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0xd3d94000, - 0x18000100, 0xd3d94001, - 0x18000101, 0xd3d94002, - 0x18000102, 0xd3d94003, - 0x18000103, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffea, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, - 0xb8f82a05, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, - 0xb8f82a05, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0xb8ef2a05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, + 0xbf11087c, 0xe0524000, + 0x781d0000, 0xe0524100, + 0x781d0100, 0xe0524200, + 0x781d0200, 0xe0524300, + 0x781d0300, 0xbf8c0f70, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0x807c847c, 0x8078ff78, + 0x00000400, 0xbf0a6f7c, + 0xbf85ffee, 0xbefc0080, + 0xbf11087c, 0xe0524000, + 0x781d0000, 0xe0524100, + 0x781d0100, 0xe0524200, + 0x781d0200, 0xe0524300, + 0x781d0300, 0xbf8c0f70, + 0xd3d94000, 0x18000100, + 0xd3d94001, 0x18000101, + 0xd3d94002, 0x18000102, + 0xd3d94003, 0x18000103, + 0x807c847c, 0x8078ff78, + 0x00000400, 0xbf0a6f7c, + 0xbf85ffea, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82a05, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, + 0xbef600ff, 0x01000000, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82a05, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2a05, - 0x806e816e, 0x8e6e8a6e, - 0x8e6e816e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b77, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2a05, 0x806e816e, + 0x8e6e8a6e, 0x8e6e816e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b77, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, }; static const uint32_t cwsr_trap_aldebaran_hex[] = { - 0xbf820001, 0xbf8202ee, + 0xbf820001, 0xbf8202ef, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840008, 0xbf0d986d, 0xbf850023, 0x866eff7b, - 0x00000400, 0xbf850065, + 0x00000400, 0xbf850066, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03800900, 0xbf850019, @@ -1820,7 +1820,7 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x00000800, 0xbf850005, 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850046, 0xbeed1a9d, + 0xbf850047, 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8977ff77, 0xfc000000, @@ -1833,188 +1833,126 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, 0xbf8cc07f, 0x8e799779, - 0x8977ff77, 0x01800000, + 0x8977ff77, 0x03800000, 0x87777977, 0xbf0d986d, - 0xbf840009, 0xbf0d9877, - 0xbf850007, 0x896dff6d, - 0x01ff0000, 0xba7f0583, - 0x00000000, 0xbf0d9d6d, - 0xbeed189d, 0xbf840012, - 0xbef71898, 0xbeed189d, - 0x86ee6e6e, 0xbf840001, - 0xbe801d6e, 0x866eff6d, - 0x01ff0000, 0xbf850005, - 0x8778ff78, 0x00002000, - 0x80ec886c, 0x82ed806d, - 0xbf820005, 0x866eff6d, - 0x01000000, 0xbf850002, - 0x806c846c, 0x826d806d, - 0x866dff6d, 0x0000ffff, - 0x8f7a8b77, 0x867aff7a, - 0x001f8000, 0xb97af807, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e8378, 0xb96ee0c2, - 0xbf800002, 0xb9780002, - 0xbe801f6c, 0x866dff6d, - 0x0000ffff, 0xbefa0080, - 0xb97a0283, 0xb8faf807, + 0xbf840006, 0xbf0d9877, + 0xbf840002, 0xbeed1a9d, + 0xbf820002, 0x896dff6d, + 0x01ff0000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840013, + 0xbef71898, 0xbef71899, + 0xbeed189d, 0x86ee6e6e, + 0xbf840001, 0xbe801d6e, + 0x866eff6d, 0x01ff0000, + 0xbf850005, 0x8778ff78, + 0x00002000, 0x80ec886c, + 0x82ed806d, 0xbf820005, + 0x866eff6d, 0x01000000, + 0xbf850002, 0x806c846c, + 0x826d806d, 0x866dff6d, + 0x0000ffff, 0x8f7a8b77, 0x867aff7a, 0x001f8000, - 0x8e7a8b7a, 0x8977ff77, - 0xfc000000, 0x87777a77, - 0xba7ff807, 0x00000000, - 0xbeee007e, 0xbeef007f, - 0xbefe0180, 0xbf900004, - 0x877a8478, 0xb97af802, - 0xbf8e0002, 0xbf88fffe, - 0xb8fa2985, 0x807a817a, - 0x8e7a8a7a, 0x8e7a817a, - 0xb8fb1605, 0x807b817b, - 0x8e7b867b, 0x807a7b7a, - 0x807a7e7a, 0x827b807f, - 0x867bff7b, 0x0000ffff, - 0xc04b1c3d, 0x00000050, - 0xbf8cc07f, 0xc04b1d3d, - 0x00000060, 0xbf8cc07f, - 0xc0431e7d, 0x00000074, - 0xbf8cc07f, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0xbef1007c, - 0xbef00080, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b3a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611b7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bba, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611bfa, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611e3a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8fbf803, 0xbefe007c, - 0xbefc0070, 0xc0611efa, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xbefe007c, 0xbefc0070, - 0xc0611a3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8f1f801, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, - 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, - 0xbef600ff, 0x01000000, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, - 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, - 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, - 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, - 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb4306, 0x867bc17b, - 0xbf840064, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf840060, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, + 0xb97af807, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e8378, + 0xb96ee0c2, 0xbf800002, + 0xb9780002, 0xbe801f6c, + 0x866dff6d, 0x0000ffff, + 0xbefa0080, 0xb97a0283, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8977ff77, 0xfc000000, + 0x87777a77, 0xba7ff807, + 0x00000000, 0xbeee007e, + 0xbeef007f, 0xbefe0180, + 0xbf900004, 0x877a8478, + 0xb97af802, 0xbf8e0002, + 0xbf88fffe, 0xb8fa2985, + 0x807a817a, 0x8e7a8a7a, + 0x8e7a817a, 0xb8fb1605, + 0x807b817b, 0x8e7b867b, + 0x807a7b7a, 0x807a7e7a, + 0x827b807f, 0x867bff7b, + 0x0000ffff, 0xc04b1c3d, + 0x00000050, 0xbf8cc07f, + 0xc04b1d3d, 0x00000060, + 0xbf8cc07f, 0xc0431e7d, + 0x00000074, 0xbf8cc07f, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0xbef1007c, 0xbef00080, 0xb8f02985, 0x80708170, 0x8e708a70, 0x8e708170, 0xb8fa1605, 0x807a817a, 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611b3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611b7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611bba, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611bfa, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611e3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8fbf803, + 0xbefe007c, 0xbefc0070, + 0xc0611efa, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xbefe007c, 0xbefc0070, + 0xc0611a7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8f1f801, + 0xbefe007c, 0xbefc0070, + 0xc0611c7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850030, - 0x24040682, 0xd86e4000, - 0x00000002, 0xbf8cc07f, + 0x10000000, 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -2034,31 +1972,50 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000200, - 0xd0c9006a, 0x0000f702, - 0xbf87ffd2, 0xbf820015, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbf87fff7, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2b05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, - 0x807bff7b, 0x00001000, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb4306, + 0x867bc17b, 0xbf840064, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf840060, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, + 0xbf850030, 0x24040682, + 0xd86e4000, 0x00000002, + 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -2077,51 +2034,31 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, - 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, - 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, - 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0x807c847c, 0x8070ff70, - 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xb8fb2985, 0x807b817b, - 0x8e7b837b, 0xb8fa2b05, - 0x807a817a, 0x8e7a827a, - 0x80fb7a7b, 0x867b7b7b, - 0xbf84007a, 0x807bff7b, - 0x00001000, 0xbefc0080, - 0xbf11017c, 0x867aff78, + 0xbf84ffee, 0x680404ff, + 0x00000200, 0xd0c9006a, + 0x0000f702, 0xbf87ffd2, + 0xbf820015, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbf87fff7, 0xbef70000, + 0xbef000ff, 0x00000400, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb2b05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850059, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0x10000000, 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -2161,139 +2098,202 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, 0xbf0a7b7c, - 0xbf85ffa9, 0xbf9c0000, - 0xbf820016, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xe0724000, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffeb, - 0xbf9c0000, 0xbf8200ee, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf84001f, 0xbefe00c1, - 0xbeff00c1, 0xb8ef4306, - 0x866fc16f, 0xbf84001a, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0x807cff7c, 0x00000200, - 0x8078ff78, 0x00000200, - 0xbf0a6f7c, 0xbf85fff6, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xb8fb2985, + 0x807b817b, 0x8e7b837b, + 0xb8fa2b05, 0x807a817a, + 0x8e7a827a, 0x80fb7a7b, + 0x867b7b7b, 0xbf84007a, + 0x807bff7b, 0x00001000, + 0xbefc0080, 0xbf11017c, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf850059, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, + 0x00000900, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, + 0x80048104, 0xd2890002, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000902, + 0x80048104, 0xd2890001, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, + 0x80048104, 0xd2890003, + 0x00000902, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffa9, + 0xbf9c0000, 0xbf820016, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffeb, 0xbf9c0000, + 0xbf8200ee, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf84001f, 0xbefe00c1, 0xbeff00c1, + 0xb8ef4306, 0x866fc16f, + 0xbf84001a, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xb8ef2b05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0x807cff7c, + 0x00000200, 0x8078ff78, + 0x00000200, 0xbf0a6f7c, + 0xbf85fff6, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2b05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xb8ef2985, 0x806f816f, + 0x8e6f836f, 0xb8f92b05, + 0x80798179, 0x8e798279, + 0x80ef796f, 0x866f6f6f, + 0xbf84001a, 0x806fff6f, + 0x00008000, 0xbefc0080, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, + 0xd3d94000, 0x18000100, + 0xd3d94001, 0x18000101, + 0xd3d94002, 0x18000102, + 0xd3d94003, 0x18000103, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xb8ef2985, - 0x806f816f, 0x8e6f836f, - 0xb8f92b05, 0x80798179, - 0x8e798279, 0x80ef796f, - 0x866f6f6f, 0xbf84001a, - 0x806fff6f, 0x00008000, - 0xbefc0080, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0xd3d94000, - 0x18000100, 0xd3d94001, - 0x18000101, 0xd3d94002, - 0x18000102, 0xd3d94003, - 0x18000103, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffea, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, - 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, - 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, - 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, - 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, - 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2985, - 0x806e816e, 0x8e6e8a6e, - 0x8e6e816e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b77, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, + 0xbf85ffea, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, + 0xbef600ff, 0x01000000, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, + 0x00000078, 0x80788478, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, + 0x00000078, 0x80788478, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, + 0x00000078, 0x80788478, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, + 0x00000078, 0x80788478, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, + 0x00000078, 0x80788478, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2985, 0x806e816e, + 0x8e6e8a6e, 0x8e6e816e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b77, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, }; static const uint32_t cwsr_trap_gfx10_hex[] = { @@ -3175,27 +3175,29 @@ static const uint32_t cwsr_trap_gfx11_hex[] = { }; static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { - 0xbf820001, 0xbf8202ea, + 0xbf820001, 0xbf8202fa, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, - 0xbf840008, 0xbf0d986d, - 0xbf85001f, 0x866eff7b, - 0x00000400, 0xbf850061, + 0xbf84000a, 0xbf0d986d, + 0xbf850023, 0xbf0d9a7b, + 0xbf850021, 0x866eff7b, + 0x00000400, 0xbf85006f, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, - 0x03800900, 0xbf850015, + 0x03800900, 0xbf850017, 0x866eff7b, 0x000071ff, 0xbf840008, 0x866fff7b, 0x00007080, 0xbf840001, 0xbeee1a87, 0xb8eff801, 0x8e6e8c6e, 0x866e6f6e, - 0xbf85000a, 0xbf0d986d, + 0xbf85000c, 0xbf0d986d, 0xbf850003, 0x866eff6d, - 0x00ff0000, 0xbf850005, - 0xbf0d986d, 0xbf850004, + 0x00ff0000, 0xbf850007, + 0xbf0d986d, 0xbf850006, + 0xbf0d9a7b, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850046, 0xbeed1a9d, + 0xbf850052, 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8979ff79, 0xfc000000, @@ -3208,14 +3210,20 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, 0xbf8cc07f, 0x8e739773, - 0x8979ff79, 0x01800000, + 0x8979ff79, 0x03800000, 0x87797379, 0xbf0d986d, - 0xbf840009, 0xbf0d9879, - 0xbf850007, 0x896dff6d, + 0xbf840008, 0xbf0d9879, + 0xbf840002, 0xbeed1a9d, + 0xbf820004, 0x896dff6d, 0x01ff0000, 0xba7f0583, - 0x00000000, 0xbf0d9d6d, - 0xbeed189d, 0xbf840012, - 0xbef91898, 0xbeed189d, + 0x00000000, 0xb8f3f803, + 0xbf0d9a73, 0xbf840006, + 0xbf0d9979, 0xbf840002, + 0xbeed1a9d, 0xbf820002, + 0xba7f0683, 0x00000000, + 0xbf0d9d6d, 0xbeed189d, + 0xbf840013, 0xbef91898, + 0xbef91899, 0xbeed189d, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, @@ -4200,25 +4208,29 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { }; static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { - 0xbf820001, 0xbf8202c9, + 0xbf820001, 0xbf8202e8, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001a, + 0xbf84000a, 0xbf0d986d, + 0xbf850023, 0xbf0d9a7b, + 0xbf850021, 0x866eff7b, + 0x00000400, 0xbf85006f, + 0xbf8e0010, 0xb8fbf803, + 0xbf82fffa, 0x866eff7b, + 0x03800900, 0xbf850017, + 0x866eff7b, 0x000071ff, + 0xbf840008, 0x866fff7b, + 0x00007080, 0xbf840001, + 0xbeee1a87, 0xb8eff801, + 0x8e6e8c6e, 0x866e6f6e, + 0xbf85000c, 0xbf0d986d, + 0xbf850003, 0x866eff6d, + 0x00ff0000, 0xbf850007, + 0xbf0d986d, 0xbf850006, + 0xbf0d9a7b, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850051, 0xbf8e0010, - 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf850011, 0x866eff7b, - 0x000071ff, 0xbf840008, - 0x866fff7b, 0x00007080, - 0xbf840001, 0xbeee1a87, - 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf850006, - 0x866eff6d, 0x00ff0000, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, + 0xbf850052, 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8979ff79, 0xfc000000, @@ -4227,187 +4239,136 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0xb8fbf813, 0x8efa887a, 0xbf0d8f7b, 0xbf840002, 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8979ff79, 0x00800000, - 0x87796e79, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, + 0xc0031cfd, 0x00000010, + 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, - 0xbf840001, 0xbe801d6e, - 0x866eff6d, 0x01ff0000, - 0xbf850005, 0x8778ff78, - 0x00002000, 0x80ec886c, - 0x82ed806d, 0xbf820005, - 0x866eff6d, 0x01000000, - 0xbf850002, 0x806c846c, - 0x826d806d, 0x866dff6d, - 0x0000ffff, 0x8f7a8b79, - 0x867aff7a, 0x001f8000, - 0xb97af807, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e8378, - 0xb96ee0c2, 0xbf800002, - 0xb9780002, 0xbe801f6c, + 0xbf8cc07f, 0x8e739773, + 0x8979ff79, 0x03800000, + 0x87797379, 0xbf0d986d, + 0xbf840008, 0xbf0d9879, + 0xbf840002, 0xbeed1a9d, + 0xbf820004, 0x896dff6d, + 0x01ff0000, 0xba7f0583, + 0x00000000, 0xb8f3f803, + 0xbf0d9a73, 0xbf840006, + 0xbf0d9979, 0xbf840002, + 0xbeed1a9d, 0xbf820002, + 0xba7f0683, 0x00000000, + 0xbf0d9d6d, 0xbeed189d, + 0xbf840013, 0xbef91898, + 0xbef91899, 0xbeed189d, + 0x86ee6e6e, 0xbf840001, + 0xbe801d6e, 0x866eff6d, + 0x01ff0000, 0xbf850005, + 0x8778ff78, 0x00002000, + 0x80ec886c, 0x82ed806d, + 0xbf820005, 0x866eff6d, + 0x01000000, 0xbf850002, + 0x806c846c, 0x826d806d, 0x866dff6d, 0x0000ffff, - 0xbefa0080, 0xb97a0283, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8979ff79, 0xfc000000, - 0x87797a79, 0xba7ff807, - 0x00000000, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbf900004, 0x877a8478, - 0xb97af802, 0xbf8e0002, - 0xbf88fffe, 0xb8fa2985, - 0x807a817a, 0x8e7a8a7a, - 0x8e7a817a, 0xb8fb1605, - 0x807b817b, 0x8e7b867b, - 0x807a7b7a, 0x807a7e7a, - 0x827b807f, 0x867bff7b, - 0x0000ffff, 0xc04b1c3d, - 0x00000050, 0xbf8cc07f, - 0xc04b1d3d, 0x00000060, - 0xbf8cc07f, 0xc0431e7d, - 0x00000074, 0xbf8cc07f, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0xbef1007c, 0xbef00080, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, + 0x8f7a8b79, 0x867aff7a, + 0x001f8000, 0xb97af807, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e8378, 0xb96ee0c2, + 0xbf800002, 0xb9780002, + 0xbe801f6c, 0x866dff6d, + 0x0000ffff, 0xbefa0080, + 0xb97a0283, 0xb8faf807, + 0x867aff7a, 0x001f8000, + 0x8e7a8b7a, 0x8979ff79, + 0xfc000000, 0x87797a79, + 0xba7ff807, 0x00000000, + 0xbeee007e, 0xbeef007f, + 0xbefe0180, 0xbf900004, + 0x877a8478, 0xb97af802, + 0xbf8e0002, 0xbf88fffe, + 0xb8fa2985, 0x807a817a, + 0x8e7a8a7a, 0x8e7a817a, + 0xb8fb1605, 0x807b817b, + 0x8e7b867b, 0x807a7b7a, + 0x807a7e7a, 0x827b807f, + 0x867bff7b, 0x0000ffff, + 0xc04b1c3d, 0x00000050, + 0xbf8cc07f, 0xc04b1d3d, + 0x00000060, 0xbf8cc07f, + 0xc0431e7d, 0x00000074, + 0xbf8cc07f, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0xbef1007c, + 0xbef00080, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0xbef60084, + 0xbef600ff, 0x01000000, 0xbefe007c, 0xbefc0070, - 0xc0611b3a, 0x0000007c, + 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b7a, + 0xbefc0070, 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bba, 0x0000007c, + 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bfa, + 0xbefc0070, 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611e3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8fbf803, - 0xbefe007c, 0xbefc0070, - 0xc0611efa, 0x0000007c, + 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a3a, + 0xbefc0070, 0xc0611e3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8fbf803, 0xbefe007c, + 0xbefc0070, 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8f1f801, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, + 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb5306, - 0x867bc17b, 0xbf840052, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf84004e, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8f1f801, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf85001d, 0x24040682, - 0xd86c0000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -4417,95 +4378,94 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000100, - 0xd0c9006a, 0x0000f702, - 0xbf87ffe5, 0xbf820016, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbefe016a, - 0xbf87fff6, 0xbef70000, - 0xbef000ff, 0x00000400, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb2b05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xb8fb2985, - 0x807b817b, 0x8e7b837b, - 0xb8fa2b05, 0x807a817a, - 0x8e7a827a, 0x80fb7a7b, - 0x867b7b7b, 0xbf84007a, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb5306, 0x867bc17b, + 0xbf840052, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf84004e, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85001d, + 0x24040682, 0xd86c0000, + 0x00000002, 0xbf8cc07f, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x680404ff, + 0x00000100, 0xd0c9006a, + 0x0000f702, 0xbf87ffe5, + 0xbf820016, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbefe016a, 0xbf87fff6, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2b05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, 0x807bff7b, 0x00001000, - 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850059, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -4544,140 +4504,204 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffa9, - 0xbf9c0000, 0xbf820016, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffeb, 0xbf9c0000, - 0xbf8200f4, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf840025, + 0xbf85ffef, 0xbf9c0000, + 0xb8fb2985, 0x807b817b, + 0x8e7b837b, 0xb8fa2b05, + 0x807a817a, 0x8e7a827a, + 0x80fb7a7b, 0x867b7b7b, + 0xbf84007a, 0x807bff7b, + 0x00001000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf8200f4, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf840025, 0xbefe00c1, + 0xbeff00c1, 0xb8ef5306, + 0x866fc16f, 0xbf840020, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0xe0510200, 0x781d0000, + 0xe0510300, 0x781d0000, + 0xe0510400, 0x781d0000, + 0x807cff7c, 0x00000500, + 0x8078ff78, 0x00000500, + 0xbf0a6f7c, 0xbf85fff0, 0xbefe00c1, 0xbeff00c1, - 0xb8ef5306, 0x866fc16f, - 0xbf840020, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0xe0510200, - 0x781d0000, 0xe0510300, - 0x781d0000, 0xe0510400, - 0x781d0000, 0x807cff7c, - 0x00000500, 0x8078ff78, - 0x00000500, 0xbf0a6f7c, - 0xbf85fff0, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2b05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xb8ef2985, 0x806f816f, - 0x8e6f836f, 0xb8f92b05, - 0x80798179, 0x8e798279, - 0x80ef796f, 0x866f6f6f, - 0xbf84001a, 0x806fff6f, - 0x00008000, 0xbefc0080, + 0xb8ef2b05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbf85ffee, 0xb8ef2985, + 0x806f816f, 0x8e6f836f, + 0xb8f92b05, 0x80798179, + 0x8e798279, 0x80ef796f, + 0x866f6f6f, 0xbf84001a, + 0x806fff6f, 0x00008000, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2985, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b79, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2985, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b79, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf9b0000, 0x00000000, }; diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index 8014b010654cf..96b80284ba386 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -113,6 +113,8 @@ var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 var SQ_WAVE_TRAPSTS_EXCP_HI_MASK = 0x7000 var SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK = 0x10000000 +var SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_MASK = 0x4000000 +var SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT = 26 var SQ_WAVE_MODE_EXCP_EN_SHIFT = 12 var SQ_WAVE_MODE_EXCP_EN_ADDR_WATCH_SHIFT = 19 @@ -129,7 +131,9 @@ var TTMP_DEBUG_TRAP_ENABLED_MASK = 0x800000 var TTMP_HOST_TRAP_ENABLED_SHIFT = 24 var TTMP_HOST_TRAP_ENABLED_MASK = 0x1000000 var TTMP_FEATURES_ENABLED_FLAGS_SHIFT = TTMP_DEBUG_TRAP_ENABLED_SHIFT -var TTMP_FEATURES_ENABLED_FLAGS_MASK = TTMP_DEBUG_TRAP_ENABLED_MASK | TTMP_HOST_TRAP_ENABLED_MASK +var TTMP_STOCHASTIC_TRAP_ENABLED_SHIFT = 25 +var TTMP_STOCHASTIC_TRAP_ENABLED_MASK = 0x2000000 +var TTMP_FEATURES_ENABLED_FLAGS_MASK = TTMP_DEBUG_TRAP_ENABLED_MASK | TTMP_HOST_TRAP_ENABLED_MASK | TTMP_STOCHASTIC_TRAP_ENABLED_MASK /* Save */ var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes @@ -137,10 +141,10 @@ var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT var S_SAVE_PC_HI_TRAP_ID_MASK = 0x00FF0000 var S_SAVE_PC_HI_HT_MASK = 0x01000000 var S_SAVE_PC_HI_HT_SHIFT = 24 -var S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP = 29 // Only used by the 1st level trap handler to remember if - // we saw a trap type that the driver could not mask, so that - // we can still go to the 2nd-level handler if we driver-mask another - // simultaneous trap. +var S_SAVE_PC_HI_NEED_2ND_LVL_TH = 29 // Only used by the 1st level trap handler to remember if + // we saw a trap type that the driver could not mask, or + // a maskable trap that should not be masked. This is + // indicates that we must go to the 2nd level trap handler. var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 @@ -245,6 +249,10 @@ L_HALTED: // Host trap may occur while wave is halted. s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT s_cbranch_scc1 L_FETCH_2ND_TRAP_DRIVER_MASKABLE +#if ASIC_FAMILY >= CHIP_GC_9_4_3 + s_bitcmp1_b32 s_save_trapsts, SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT + s_cbranch_scc1 L_FETCH_2ND_TRAP_DRIVER_MASKABLE +#endif L_CHECK_SAVE: s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save @@ -311,11 +319,17 @@ end s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT s_cbranch_scc1 L_FETCH_2ND_TRAP_DRIVER_MASKABLE +#if ASIC_FAMILY >= CHIP_GC_9_4_3 + // Check for perf snapshot + s_bitcmp1_b32 s_save_trapsts, SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT + s_cbranch_scc1 L_FETCH_2ND_TRAP_DRIVER_MASKABLE +#endif + s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK s_cbranch_scc1 L_SAVE L_FETCH_2ND_TRAP: - s_bitset1_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP + s_bitset1_b32 s_save_pc_hi, S_SAVE_PC_HI_NEED_2ND_LVL_TH L_FETCH_2ND_TRAP_DRIVER_MASKABLE: // Preserve and clear scalar XNACK state before issuing scalar reads. save_and_clear_ib_sts(ttmp14) @@ -336,8 +350,8 @@ L_NO_SIGN_EXTEND_TMA: s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA s_waitcnt lgkmcnt(0) - // Put debug enable bit and host trap bit into SAVE_IB_STS register, bits - // 23 and 24, respectively. + // Put debug enable bit, stochastic trap bit, and host trap bit into SAVE_IB_STS register, bits + // 23-25, respectively s_lshl_b32 s_tma_flags, s_tma_flags, TTMP_FEATURES_ENABLED_FLAGS_SHIFT s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_FEATURES_ENABLED_FLAGS_MASK s_or_b32 s_save_ib_sts, s_save_ib_sts, s_tma_flags @@ -345,28 +359,51 @@ L_NO_SIGN_EXTEND_TMA: // If not a host trap, then driver cannot mask this. Go to the 2nd-level // trap handler now. s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT - s_cbranch_scc0 L_GOTO_2ND_TRAP + s_cbranch_scc0 L_CHECK_STOC // If driver said host traps are OK, go to the 2nd-level handler now. s_bitcmp1_b32 s_save_ib_sts, TTMP_HOST_TRAP_ENABLED_SHIFT - s_cbranch_scc1 L_GOTO_2ND_TRAP + s_cbranch_scc0 L_MASKED_HT + s_bitset1_b32 s_save_pc_hi, S_SAVE_PC_HI_NEED_2ND_LVL_TH + s_branch L_CHECK_STOC +L_MASKED_HT: // The driver said host traps are masked, zero out host trap and trapID. s_andn2_b32 s_save_pc_hi, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) +#if ASIC_FAMILY >= CHIP_GC_9_4_3 s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT, 1), 0x0 +#endif + +L_CHECK_STOC: +#if ASIC_FAMILY >= CHIP_GC_9_4_3 + // If TRAPSTS says we did not have a stochastic sampling trap, then driver cannot mask this + s_getreg_b32 ttmp7, hwreg(HW_REG_TRAPSTS) + s_bitcmp1_b32 ttmp7, SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT + s_cbranch_scc0 L_CHECK_REMAINING_EXCP + // If stochastic sampling trap was requested, should it be masked by the driver? + s_bitcmp1_b32 s_save_ib_sts, TTMP_STOCHASTIC_TRAP_ENABLED_SHIFT + // If driver said stochastic traps are OK, allow the 2nd-level handler to take host trap + s_cbranch_scc0 L_MASKED_STOC + s_bitset1_b32 s_save_pc_hi, S_SAVE_PC_HI_NEED_2ND_LVL_TH + s_branch L_CHECK_REMAINING_EXCP + +L_MASKED_STOC: + // Otherwise, zero out TRAPSTS.stochastic_perf_snapshot bit, so possible 2nd level does not handle it + s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT, 1), 0x0 +#endif - // If there was another trap besides this masked host trap, go handle it in - // 2nd-level handler. - s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP - s_bitset0_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP // zero this out - s_cbranch_scc0 L_EXIT_TRAP // Otherwise, exit the trap handler +L_CHECK_REMAINING_EXCP: + // Check if we found any reason to go to the 2nd level trap handler. + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_NEED_2ND_LVL_TH + s_bitset0_b32 s_save_pc_hi, S_SAVE_PC_HI_NEED_2ND_LVL_TH // zero this out + s_cbranch_scc0 L_EXIT_TRAP // Otherwise, exit the trap handler L_GOTO_2ND_TRAP: // Reset bits used temporarily by 1st level trap handler so they do not // leak to the 2nd level trap handler. s_bitset0_b32 s_save_ib_sts, TTMP_HOST_TRAP_ENABLED_SHIFT - s_bitset0_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP - + s_bitset0_b32 s_save_ib_sts, TTMP_STOCHASTIC_TRAP_ENABLED_SHIFT + s_bitset0_b32 s_save_pc_hi, S_SAVE_PC_HI_NEED_2ND_LVL_TH s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 7573eb3f88cbe..1f6342ea5c547 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -36,9 +36,10 @@ * 0.3 - Fix gfx9_4_3 SQ hang issue * 1.1 - Support gfx9_4_3 Stochastic PC sampling * 1.2 - Support gfx9_5_0 Host Trap PC sampling + * 1.3 - Update 1st level trap handler for Stochastic PC sampling */ #define KFD_IOCTL_PCS_MAJOR_VERSION 1 -#define KFD_IOCTL_PCS_MINOR_VERSION 1 +#define KFD_IOCTL_PCS_MINOR_VERSION 3 struct supported_pc_sample_info { uint32_t ip_version; From a6060e0cbddfeaf30aff9e3ed4e669716d1922de Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 25 Feb 2025 12:42:15 +0800 Subject: [PATCH 1443/2653] drm/amdkcl: Optimize configuration management in dkms-config.sh Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/dkms-config.sh | 39 ++++++++++++++++++++----- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index 3c30f3d4735c6..efe7089df9c36 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -3,21 +3,32 @@ local_config=$1 KERNELVER=$2 CC=$3 -local_config_tmp=${local_config}.tmp kernel_build_dir="/lib/modules/$KERNELVER/build" kconfig_file="${kernel_build_dir}/include/config/auto.conf" kcl_config_file="amd/dkms/config/config.h" +local_config_tmp=${local_config}.tmp +disabled_config_tmp=${local_config}.disabled.tmp -rm -f ${local_config_tmp} +echo "" > ${local_config_tmp} +echo "" > ${disabled_config_tmp} append_mk () { echo $1 >> ${local_config_tmp} } -export_macro_mk () { -cat <<_DKMS_CONFIG >> ${local_config_tmp} -export $1=y -subdir-ccflags-y += -D$1 +export_macro_mk() { + local config_name=$1 + local enable=${2:-1} + + if [ "$enable" -eq 1 ]; then + output=${local_config_tmp} + else + output=${disabled_config_tmp} + fi + + cat <<_DKMS_CONFIG >> ${output} +export ${config_name}=y +subdir-ccflags-y += -D${config_name} _DKMS_CONFIG } @@ -94,18 +105,23 @@ fi append_mk "subdir-ccflags-y += -DDRM_VER=${DRM_VER} -DDRM_PATCH=${DRM_PATCH} -DDRM_SUB=\"0\"" +# Check for P2PDMA configuration +_enable=0 if [[ "$(get_config CONFIG_PCI_P2PDMA)" == "y" ]]; then if [[ "$(get_config CONFIG_DMABUF_MOVENOTIFY)" == "y" ]]; then - export_macro_mk CONFIG_HSA_AMD_P2P + _enable=1 fi fi +export_macro_mk CONFIG_HSA_AMD_P2P ${_enable} # Check for HMM mirror configuration +_enable=0 if [[ "$(is_kcl_macro_defined HAVE_AMDKCL_HMM_MIRROR_ENABLED)" == "y" ]]; then if is_enabled CONFIG_DEVICE_PRIVATE; then - export_macro_mk CONFIG_HSA_AMD_SVM + _enable=1 fi fi +export_macro_mk CONFIG_HSA_AMD_SVM ${_enable} export_macro_mk CONFIG_HSA_AMD export_macro_mk CONFIG_DRM_AMDGPU_CIK @@ -113,5 +129,12 @@ export_macro_mk CONFIG_DRM_AMDGPU_SI export_macro_mk CONFIG_DRM_AMDGPU_USERPTR export_macro_mk CONFIG_DRM_AMD_DC +echo "Enabled configurations:" cat ${local_config_tmp} +echo "****************" +echo "Disabled configurations:" +cat ${disabled_config_tmp} +echo "****************" + +rm -f ${disabled_config_tmp} mv ${local_config_tmp} ${local_config} From 5546e677481f90fc123bffc81d445f58444bd45e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 7 Mar 2025 22:06:54 +0800 Subject: [PATCH 1444/2653] drm/amdkcl: fake linux/cgroup_dmem.h It's caused by v6.13-rc6-1-gb168ed458dde kernel/cgroup: Add "dmem" memory accounting cgroup v6.13-rc6-3-g2b624a2c1865 drm/ttm: Handle cgroup based eviction in TTM Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 ++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/header/linux/cgroup_dmem.h | 10 ++++ include/kcl/kcl_cgroup_dmem.h | 51 ++++++++++++++++++++ 4 files changed, 67 insertions(+) create mode 100644 include/kcl/header/linux/cgroup_dmem.h create mode 100644 include/kcl/kcl_cgroup_dmem.h diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 1fc123af76d47..d7942c5fa0573 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -154,4 +154,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #kernel.h: split out min()/max() et al. helpers dnl AC_KERNEL_CHECK_HEADERS([linux/minmax.h]) + + dnl #v6.13-rc6-1-gb168ed458dde + dnl #kernel/cgroup: Add "dmem" memory accounting cgroup + dnl + AC_KERNEL_CHECK_HEADERS([linux/cgroup_dmem.h]) ]) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index f9e3e75824090..5e944f8950bbb 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -21,5 +21,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/header/linux/cgroup_dmem.h b/include/kcl/header/linux/cgroup_dmem.h new file mode 100644 index 0000000000000..11cbf3b03d712 --- /dev/null +++ b/include/kcl/header/linux/cgroup_dmem.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_CGROUP_DMEM_H +#define _KCL_HEADER_LINUX_CGROUP_DMEM_H + +#ifdef HAVE_LINUX_CGROUP_DMEM_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_cgroup_dmem.h b/include/kcl/kcl_cgroup_dmem.h new file mode 100644 index 0000000000000..772e06860ca11 --- /dev/null +++ b/include/kcl/kcl_cgroup_dmem.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * linux/ipc/util.c + * Copyright (C) 1992 Krishna Balasubramanian + * For kvmalloc/kvzalloc + */ +#ifndef AMDKCL_CGROUP_DMEM_H +#define AMDKCL_CGROUP_DMEM_H + +#ifndef HAVE_LINUX_CGROUP_DMEM_H +struct dmem_cgroup_pool_state; + +/* Opaque definition of a cgroup region, used internally */ +struct dmem_cgroup_region; +static inline __printf(2,3) struct dmem_cgroup_region * +dmem_cgroup_register_region(u64 size, const char *name_fmt, ...) +{ + return NULL; +} + +static inline void dmem_cgroup_unregister_region(struct dmem_cgroup_region *region) +{ } + +static inline int dmem_cgroup_try_charge(struct dmem_cgroup_region *region, u64 size, + struct dmem_cgroup_pool_state **ret_pool, + struct dmem_cgroup_pool_state **ret_limit_pool) +{ + *ret_pool = NULL; + + if (ret_limit_pool) + *ret_limit_pool = NULL; + + return 0; +} + +static inline void dmem_cgroup_uncharge(struct dmem_cgroup_pool_state *pool, u64 size) +{ } + +static inline +bool dmem_cgroup_state_evict_valuable(struct dmem_cgroup_pool_state *limit_pool, + struct dmem_cgroup_pool_state *test_pool, + bool ignore_low, bool *ret_hit_low) +{ + return true; +} + +static inline void dmem_cgroup_pool_state_put(struct dmem_cgroup_pool_state *pool) +{ } +#endif /*HAVE_LINUX_CGROUP_DMEM_H*/ + +#endif From e5b840cec97353f944694e196f2f92db2d7cf706 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 15 Mar 2025 15:47:19 +0800 Subject: [PATCH 1445/2653] drm/amdkcl: test whether drm_memory_stats_is_zero exits It's caused by v6.13-rc2-231-gfd265d9e0c33 drm: add drm_memory_stats_is_zero v6.13-rc2-235-g74ef9527bd87 drm/amdgpu: track bo memory stats at runtime Signed-off-by: Asher Song --- .../amd/backport/include/kcl/kcl_drm_file.h | 4 ++ drivers/gpu/drm/amd/backport/kcl_drm_file.c | 11 +++++ drivers/gpu/drm/amd/dkms/m4/drm-file.m4 | 42 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- 4 files changed, 59 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-file.m4 diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h index 91ea254aa7434..435dcf5ceea08 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h @@ -25,4 +25,8 @@ void _kcl_drm_print_memory_stats(struct drm_printer *p, #define drm_print_memory_stats _kcl_drm_print_memory_stats; #endif +#ifndef HAVE_DRM_MEMORY_STATS_IS_ZERO +int drm_memory_stats_is_zero(const struct drm_memory_stats *stats); +#endif + #endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_file.c b/drivers/gpu/drm/amd/backport/kcl_drm_file.c index 1a0fb154a34c2..e28ba0dd163d4 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_file.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_file.c @@ -102,3 +102,14 @@ void _kcl_drm_print_memory_stats(struct drm_printer *p, } EXPORT_SYMBOL(_kcl_drm_print_memory_stats); #endif + +#ifndef HAVE_DRM_MEMORY_STATS_IS_ZERO +int drm_memory_stats_is_zero(const struct drm_memory_stats *stats) +{ + return (stats->shared == 0 && + stats->private == 0 && + stats->resident == 0 && + stats->purgeable == 0 && + stats->active == 0); +} +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-file.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-file.m4 new file mode 100644 index 0000000000000..8e907a5616852 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-file.m4 @@ -0,0 +1,42 @@ +dnl # +dnl # commit fd265d9e0c3358e6 +dnl # drm: add drm_memory_stats_is_zero +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MEMORY_STATS_IS_ZERO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_memory_stats_is_zero(NULL); + ], [ + AC_DEFINE(HAVE_DRM_MEMORY_STATS_IS_ZERO, 1, + [drm_memory_stats_is_zero() is available]) + ]) + ]) +]) + +dnl # +dnl # commit fd265d9e0c3358e6 +dnl # drm: add drm_memory_stats_is_zero +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_MEMORY_STATS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_memory_stats *stats; + stats = NULL; + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_MEMORY_STATS, 1, + [struct drm_memory_stats is defined]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_MEMORY_STATS], [ + AC_AMDGPU_DRM_MEMORY_STATS_IS_ZERO + AC_AMDGPU_STRUCT_DRM_MEMORY_STATS +]) + + + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 755543c55b551..948900c23701e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -263,7 +263,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CEC_NOTIFIER_CONN_REGISTER AC_AMDGPU_STRUCT_CEC_CONNECTOR_INFO AC_AMDGPU_TIME64_TO_TM - + AC_AMDGPU_DRM_MEMORY_STATS + AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" From 2a7ace3c7ec72846ec29dcf72feeff13b4512153 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 9 Mar 2025 11:42:29 +0800 Subject: [PATCH 1446/2653] drm/amdkcl: test fd_empty whether exist It's caused by v6.11-rc1-2-g88a2f6468d01 struct fd: representation change v6.12-rc2-14-g6348be02eead fdget(), trivial conversions Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 | 20 ++++++++++++++++++++ include/kcl/kcl_file.h | 7 +++++++ 2 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 index 07011778633f9..f025643ea5b56 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 @@ -16,6 +16,26 @@ AC_DEFUN([AC_AMDGPU_FILE_OPERATION_FOP_FLAGS], [ ]) ]) +dnl # +dnl # commit v6.11-rc1-2-g88a2f6468d01 +dnl # struct fd: representation change +dnl # +AC_DEFUN([AC_AMDGPU_FD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct fd f; + f.word = 0; + fd_empty(f); + ],[ + AC_DEFINE(HAVE_FD_EMPTY, 1, + [fd_empty is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_FILE_OPERATION], [ AC_AMDGPU_FILE_OPERATION_FOP_FLAGS + AC_AMDGPU_FD ]) diff --git a/include/kcl/kcl_file.h b/include/kcl/kcl_file.h index 2b81dc3f31644..4c8a92d981141 100644 --- a/include/kcl/kcl_file.h +++ b/include/kcl/kcl_file.h @@ -8,4 +8,11 @@ #define fd_file(f) ((f).file) #endif +#ifndef HAVE_FD_EMPTY +static inline bool fd_empty(struct fd f) +{ + return !fd_file(f); +} +#endif + #endif From 77598eaf7c1437bd8a594949b4f172962e60ace0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 11 Mar 2025 13:48:19 +0800 Subject: [PATCH 1447/2653] drm/amdkcl: test the argument in attribut callback of bin_is_visible wether is constant It's caused by v6.12-rc6-16-gb626816fdd7f sysfs: treewide: constify attribute callback of bin_is_visible() Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 ++- .../drm/amd/dkms/m4/struct_attribute_group.m4 | 31 ++++++++++++++++++- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 435e38befe7b2..76b8f616aaa37 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -4304,7 +4304,10 @@ static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribu #ifdef HAVE_ATTRIBUTE_GROUP_IS_BIN_VISIBLE static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, - const struct bin_attribute *attr, +#ifdef HAVE_CONSTANT_ARGUMENT_IN_IS_BIN_VISIBLE + const +#endif + struct bin_attribute *attr, int idx) { struct device *dev = kobj_to_dev(kobj); diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 index 80990947459d3..df5844b1187b0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 @@ -1,3 +1,31 @@ +dnl # +dnl # commit v4.3-rc4-9-g7f5028cf6190 +dnl # sysfs: Support is_visible() on binary attributes +dnl # +AC_DEFUN([AC_AMDGPU_BIN_FLASH_ATTR_IS_VISIBLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + static umode_t amdgpu_bin_attr_is_visible(struct kobject *kobj, + const struct bin_attribute *attr, + int idx) + { + return 0; + } + struct attribute_group amdgpu_attr_group = { + .is_bin_visible = amdgpu_bin_attr_is_visible, + }; + + ],[ + (void)amdgpu_attr_group; + ],[ + AC_DEFINE(HAVE_CONSTANT_ARGUMENT_IN_IS_BIN_VISIBLE, 1, + [need a const argument in member func .is_bin_visible]) + ]) + ]) +]) + dnl # dnl # commit v4.3-rc4-9-g7f5028cf6190 dnl # sysfs: Support is_visible() on binary attributes @@ -12,6 +40,7 @@ AC_DEFUN([AC_AMDGPU_ATTRIBUTE_GROUP_IS_BIN_VISIBLE], [ ],[ AC_DEFINE(HAVE_ATTRIBUTE_GROUP_IS_BIN_VISIBLE, 1, [amdgpu_attr_group->is_bin_visible is available]) + AC_AMDGPU_BIN_FLASH_ATTR_IS_VISIBLE ]) ]) -]) \ No newline at end of file +]) From b7aeb3fc722bba96deb5972824930f2e398f79ea Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 11 Mar 2025 17:39:51 +0800 Subject: [PATCH 1448/2653] drm/amdkcl: test drm_connector_dynamic_init whether exits It's caused by v6.13-rc2-201-g1d985ddabbe0 drm/connector: Add a way to init/add a connector in separate steps Signed-off-by: Asher Song --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 8 ++++++++ drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 | 18 ++++++++++++++++-- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 ++- 3 files changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 2b537b9b3f4b8..a3d3462f633f4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -732,12 +732,20 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, amdgpu_dm_set_mst_status(&aconnector->mst_status, MST_PROBE, true); +#ifdef HAVE_DRM_CONNECTOR_DYNAMIC_INIT if (drm_connector_dynamic_init( +#else + if (drm_connector_init( +#endif dev, connector, &dm_dp_mst_connector_funcs, +#ifdef HAVE_DRM_CONNECTOR_DYNAMIC_INIT DRM_MODE_CONNECTOR_DisplayPort, NULL)) { +#else + DRM_MODE_CONNECTOR_DisplayPort)) { +#endif kfree(aconnector); return NULL; } diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 index 653c3e1e1ec98..34702411114b7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 @@ -16,5 +16,19 @@ AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE], [ ]) ]) - - +dnl # +dnl # v6.13-rc2-201-g1d985ddabbe0 +dnl # drm/connector: Add a way to init/add a connector in separate steps +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_DYNAMIC_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_connector_dynamic_init(NULL, NULL, NULL, 0, NULL); + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_DYNAMIC_INIT, 1, + [drm_connector_dynamic_init is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 948900c23701e..792fee285747a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -263,7 +263,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CEC_NOTIFIER_CONN_REGISTER AC_AMDGPU_STRUCT_CEC_CONNECTOR_INFO AC_AMDGPU_TIME64_TO_TM - AC_AMDGPU_DRM_MEMORY_STATS + AC_AMDGPU_DRM_MEMORY_STATS + AC_AMDGPU_DRM_CONNECTOR_DYNAMIC_INIT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From c09b3121d731af99ca5b787b8c6a882a0024a47f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 11 Mar 2025 18:19:59 +0800 Subject: [PATCH 1449/2653] drm/amdkcl: test drm_connector->eld_mutex whether exist It's caused by v6.13-rc2-179-gdf7c8e3dde37 drm/connector: add mutex to protect ELD from concurrent access Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++- drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 | 23 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 3 files changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2e99c1ae7b993..d36893f05d11d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1089,11 +1089,14 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, continue; *enabled = true; +#ifdef HAVE_DRM_CONNECTOR_ELD_MUTEX mutex_lock(&connector->eld_mutex); +#endif ret = drm_eld_size(connector->eld); memcpy(buf, connector->eld, min(max_bytes, ret)); +#ifdef HAVE_DRM_CONNECTOR_ELD_MUTEX mutex_unlock(&connector->eld_mutex); - +#endif break; } drm_connector_list_iter_end(&conn_iter); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 index 34702411114b7..01791b2a42e79 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 @@ -16,6 +16,29 @@ AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE], [ ]) ]) +dnl # +dnl # v6.13-rc2-179-gdf7c8e3dde37 +dnl # drm/connector: add mutex to protect ELD from concurrent access +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ELD_MUTEX], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector connector; + void *ptr = &connector.eld_mutex; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_ELD_MUTEX, 1, + [drm_connector->eld_mutex is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STRUCT_MEMBER], [ + AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE + AC_AMDGPU_DRM_CONNECTOR_ELD_MUTEX +]) + dnl # dnl # v6.13-rc2-201-g1d985ddabbe0 dnl # drm/connector: Add a way to init/add a connector in separate steps diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 792fee285747a..57dd1db5a856f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -96,7 +96,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS - AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE + AC_AMDGPU_DRM_CONNECTOR_STRUCT_MEMBER AC_AMDGPU_DRM_DP_MST_DETECT_PORT AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT From d3b55ca126ee58fc486429db6344e7f579fd9aa0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 11 Mar 2025 18:48:30 +0800 Subject: [PATCH 1450/2653] drm/amdkcl: test drm_get_panel_min_brightness_quirk whether exist It's caused by v6.12-rc6-1237-g22e5c7ae1214 drm: Add panel backlight quirks Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ .../dkms/m4/drm-get-panel-min-brightness-quirk.m4 | 14 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 19 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-get-panel-min-brightness-quirk.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d36893f05d11d..e06b17d574ab8 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3652,7 +3652,9 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) #ifdef HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE struct drm_luminance_range_info *luminance_range; #endif +#ifdef HAVE_DRM_GET_PANEL_MIN_BRIGHTNESS_QUIRK int min_input_signal_override; +#endif if (aconnector->bl_idx == -1 || aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP) @@ -3694,9 +3696,11 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) caps->aux_min_input_signal = 1; #endif +#ifdef HAVE_DRM_GET_PANEL_MIN_BRIGHTNESS_QUIRK min_input_signal_override = drm_get_panel_min_brightness_quirk(aconnector->drm_edid); if (min_input_signal_override >= 0) caps->min_input_signal = min_input_signal_override; +#endif } #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-get-panel-min-brightness-quirk.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-get-panel-min-brightness-quirk.m4 new file mode 100644 index 0000000000000..2a5b68a984203 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-get-panel-min-brightness-quirk.m4 @@ -0,0 +1,14 @@ +dnl # +dnl # v6.12-rc6-1237-g22e5c7ae1214 drm: Add panel backlight quirks +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GET_PANEL_MIN_BRIGHTNESS_QUIRK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_get_panel_min_brightness_quirk(NULL); + ],[drm_get_panel_min_brightness_quirk], [drivers/gpu/drm/drm_panel_backlight_quirks.c], [ + AC_DEFINE(HAVE_DRM_GET_PANEL_MIN_BRIGHTNESS_QUIRK, 1, [drm_get_panel_min_brightness_quirk() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 57dd1db5a856f..de58e09311e47 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -265,6 +265,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TIME64_TO_TM AC_AMDGPU_DRM_MEMORY_STATS AC_AMDGPU_DRM_CONNECTOR_DYNAMIC_INIT + AC_AMDGPU_DRM_GET_PANEL_MIN_BRIGHTNESS_QUIRK AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 80f05bceaf34a7178bec4d92417c95f715039210 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 25 Mar 2025 16:56:27 +0800 Subject: [PATCH 1451/2653] drm/amdkcl: test macro MODULE_IMPORT_NS whether need a string argument It's caused by v6.13-rc1-2-gcdd30ebb1b9f module: Convert symbol namespace to string literal Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/module_import_ns.m4 | 15 +++++++++++++++ 3 files changed, 20 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/module_import_ns.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index c37cae6a51751..81afeda39667d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -64,7 +64,11 @@ #include "amdgpu_res_cursor.h" #include "bif/bif_4_1_d.h" +#ifdef HAVE_MODULE_IMPORT_NS_NEED_A_STRING MODULE_IMPORT_NS("DMA_BUF"); +#else +MODULE_IMPORT_NS(DMA_BUF); +#endif #define AMDGPU_TTM_VRAM_MAX_DW_READ ((size_t)128) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index de58e09311e47..cfdcf57474ab4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -266,6 +266,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MEMORY_STATS AC_AMDGPU_DRM_CONNECTOR_DYNAMIC_INIT AC_AMDGPU_DRM_GET_PANEL_MIN_BRIGHTNESS_QUIRK + AC_AMDGPU_MODULE_IMPORT_NS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/module_import_ns.m4 b/drivers/gpu/drm/amd/dkms/m4/module_import_ns.m4 new file mode 100644 index 0000000000000..bdc84e5d287c9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/module_import_ns.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # v6.13-rc1-2-gcdd30ebb1b9f +dnl # module: Convert symbol namespace to string literal +dnl # +AC_DEFUN([AC_AMDGPU_MODULE_IMPORT_NS], [ + AC_KERNEL_DO_BACKGROUND([ + header_file_src=$LINUX/include/linux/module.h + AS_IF([test -f "$header_file_src"], [ + AS_IF([grep -qE '^#define MODULE_IMPORT_NS\(ns\)\s+MODULE_INFO\(import_ns, ns\)$' $header_file_src ], [ + AC_DEFINE(HAVE_MODULE_IMPORT_NS_NEED_A_STRING, 1, + [MODULE_IMPORT_NS() wants a string arguments]) + ]) + ]) + ]) +]) From f25cf71751d26e24b24f2ec99a56ce96c1c0957b Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 3 Mar 2025 16:32:35 +0800 Subject: [PATCH 1452/2653] drm/amdkcl: fake the macro defintion DP_EDP_MSO_LINK_CAPABILITIES It' caused by the following commit: 23746f2b6 "drm/amd/display: read mso dpcd caps" Signed-off-by: chengjya --- include/kcl/kcl_drm_dp.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_drm_dp.h b/include/kcl/kcl_drm_dp.h index 7f3607f89c6a4..80f2aecf50394 100644 --- a/include/kcl/kcl_drm_dp.h +++ b/include/kcl/kcl_drm_dp.h @@ -84,4 +84,8 @@ #define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */ #endif +#ifndef DP_EDP_MSO_LINK_CAPABILITIES +#define DP_EDP_MSO_LINK_CAPABILITIES 0x7a4 /* eDP 1.4 */ +#endif + #endif \ No newline at end of file From 566cc96b89532a284568f74d2220ef590adbf741 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 4 Mar 2025 13:41:43 +0800 Subject: [PATCH 1453/2653] drm/amdkcl: Avoid operating on copies of backlight caps on non-upstream code It's caused by the commit: 89879d1 "Avoid operating on copies of backlight caps" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e06b17d574ab8..0a5771aa7aae9 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4989,9 +4989,9 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, brightness = brightness * 0x101 - * (caps.max_input_signal - caps.min_input_signal) + * (caps->max_input_signal - caps->min_input_signal) / AMDGPU_MAX_BL_LEVEL - + caps.min_input_signal * 0x101; + + caps->min_input_signal * 0x101; struct set_backlight_level_params backlight_level_params = { 0 }; From e993c09ce6147393f094ca7b4b680eae2b0f4d14 Mon Sep 17 00:00:00 2001 From: Luca Bruni Date: Tue, 25 Feb 2025 14:08:47 -0500 Subject: [PATCH 1454/2653] drm/dkms: fix conflict with per-user temp directories setting of libpam-tmpdir package Signed-off-by: Luca Bruni Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/pre-build.sh | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 7411801636c29..6044697f8ac62 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -93,6 +93,10 @@ export KERNELVER ln -s $DKMS_TREE $MODULE_BUILD_DIR echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env +# unset TMPDIR in this shell +# otherwise conflicting package libpam-tmpdir incorrectly generates config +unset TMPDIR + (cd $SRC && ./configure) # rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o From a408ddd9fd0664d3514c41fc8f4a42eb105cc58b Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Thu, 27 Feb 2025 12:45:18 -0500 Subject: [PATCH 1455/2653] drm/amdkfd: remove non-upstream deprecated debug gws support definitions Definition of gws_debug_workaround was replaced by upstreamed kfd_dbg_has_gws_support a long time go so remove the definition. Signed-off-by: Jonathan Kim Reviewed-by: Amber Lin --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 418a9dbeeeefb..cca32792941c8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -594,19 +594,6 @@ static int kfd_gws_init(struct kfd_node *node) node->adev->gds.gws_size, &node->gws); } - if ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 0, 1) - && kfd->mec2_fw_version < 0x81b6) || - (KFD_GC_VERSION(kfd) >= IP_VERSION(9, 1, 0) - && KFD_GC_VERSION(kfd) <= IP_VERSION(9, 2, 2) - && kfd->mec2_fw_version < 0x1b6) || - (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 0) - && kfd->mec2_fw_version < 0x1b6) || - (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1) - && kfd->mec2_fw_version < 0x30) || - (KFD_GC_VERSION(kfd) >= IP_VERSION(11, 0, 0) && - KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0))) - node->gws_debug_workaround = true; - return ret; } From 9c6f575dbe142676098ce9ff898732c926ee0fb6 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 3 Mar 2025 10:08:54 +0800 Subject: [PATCH 1456/2653] drm/amdkcl: fake __cleanup() based infrastructure It's caused by the following commits: 8b9024152314 "drm/amd/display: Use _free() macro for amdgpu_dm_commit_zero_streams()" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/linux/cleanup.h | 12 ++++++++++++ include/kcl/kcl_cleanup.h | 15 +++++++++++++++ include/kcl/kcl_compiler_attributes.h | 8 ++++++++ include/kcl/kcl_slab.h | 5 +++++ 7 files changed, 49 insertions(+) create mode 100644 include/kcl/header/linux/cleanup.h create mode 100644 include/kcl/kcl_cleanup.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b5d20adccce35..6ebdcaf1d5365 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -143,4 +143,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4631c4463cd6f..a78a275b6d6c5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -828,6 +828,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_CC_PLATFORM_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_CLEANUP_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_COMPILER_ATTRIBUTES_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index d7942c5fa0573..303ac32f4e8e5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -159,4 +159,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #kernel/cgroup: Add "dmem" memory accounting cgroup dnl AC_KERNEL_CHECK_HEADERS([linux/cgroup_dmem.h]) + + dnl #v6.5-rc3-2-g85be6d842447 + dnl #locking: Introduce __cleanup() based infrastructure + dnl + AC_KERNEL_CHECK_HEADERS([linux/cleanup.h]) ]) diff --git a/include/kcl/header/linux/cleanup.h b/include/kcl/header/linux/cleanup.h new file mode 100644 index 0000000000000..2787010580598 --- /dev/null +++ b/include/kcl/header/linux/cleanup.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_CLEANUP_H +#define _KCL_HEADER_LINUX_CLEANUP_H + +#ifdef HAVE_LINUX_CLEANUP_H +#include_next +#else +#include +#endif + +#endif + diff --git a/include/kcl/kcl_cleanup.h b/include/kcl/kcl_cleanup.h new file mode 100644 index 0000000000000..ce4ba4cd69b0a --- /dev/null +++ b/include/kcl/kcl_cleanup.h @@ -0,0 +1,15 @@ +#ifndef _KCL_CLEANUP_H +#define _KCL_CLEANUP_H + +#include +#include + +#ifndef HAVE_LINUX_CLEANUP_H +#define DEFINE_FREE(_name, _type, _free) \ + static inline void __free_##_name(void *p) { _type _T = *(_type *)p; _free; } + +#define __free(_name) __cleanup(__free_##_name) + +#endif + +#endif /* KCL_CLEANUP_H_ */ diff --git a/include/kcl/kcl_compiler_attributes.h b/include/kcl/kcl_compiler_attributes.h index e844e68139479..9b21509fb3017 100644 --- a/include/kcl/kcl_compiler_attributes.h +++ b/include/kcl/kcl_compiler_attributes.h @@ -22,4 +22,12 @@ #endif #endif +#ifndef __cleanup +#ifdef __clang__ +#define __cleanup(func) __maybe_unused __attribute__((__cleanup__(func))) +#else +#define __cleanup(func) __attribute__((__cleanup__(func))) +#endif +#endif + #endif /* AMDKCL_COMPILER_ATTRIBUTES_H */ diff --git a/include/kcl/kcl_slab.h b/include/kcl/kcl_slab.h index 42faba605dcb6..8bff76afca13b 100644 --- a/include/kcl/kcl_slab.h +++ b/include/kcl/kcl_slab.h @@ -13,6 +13,7 @@ #include #include +#include #ifndef HAVE_KREALLOC_ARRAY /** @@ -42,4 +43,8 @@ size_t kmalloc_size_roundup(size_t size); extern void *kvrealloc(const void *p, size_t oldsize, size_t newsize, gfp_t flags); #endif +#ifndef HAVE_LINUX_CLEANUP_H +DEFINE_FREE(kfree, void *, if (_T) kfree(_T)) +#endif + #endif From eb3fb49dc9c8b4437a4531b971e6f874daa9182a Mon Sep 17 00:00:00 2001 From: chengjya Date: Wed, 5 Mar 2025 12:16:57 +0800 Subject: [PATCH 1457/2653] drm/amdkcl: fake the macro defintion scoped_guard It's caused by the commit: a0dbab7 "drm/amd/display: Use scoped guards for handle_hpd_irq_helper()" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_cleanup.h | 25 +++++++++++++++++++++++++ include/kcl/kcl_mutex.h | 21 +++++++++++++++++++++ 3 files changed, 47 insertions(+) create mode 100644 include/kcl/kcl_mutex.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6ebdcaf1d5365..3edbe1edffb80 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -144,4 +144,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_cleanup.h b/include/kcl/kcl_cleanup.h index ce4ba4cd69b0a..73ad9f618de67 100644 --- a/include/kcl/kcl_cleanup.h +++ b/include/kcl/kcl_cleanup.h @@ -10,6 +10,31 @@ #define __free(_name) __cleanup(__free_##_name) +#define DEFINE_CLASS(_name, _type, _exit, _init, _init_args...) \ +typedef _type class_##_name##_t; \ +static inline void class_##_name##_destructor(_type *p) \ +{ _type _T = *p; _exit; } \ +static inline _type class_##_name##_constructor(_init_args) \ +{ _type t = _init; return t; } + +#define DEFINE_GUARD(_name, _type, _lock, _unlock) \ + DEFINE_CLASS(_name, _type, if (_T) { _unlock; }, ({ _lock; _T; }), _type _T); \ + static inline void * class_##_name##_lock_ptr(class_##_name##_t *_T) \ + { return *_T; } + +#define CLASS(_name, var) \ + class_##_name##_t var __cleanup(class_##_name##_destructor) = \ + class_##_name##_constructor + +#define guard(_name) \ + CLASS(_name, __UNIQUE_ID(guard)) + +#define __guard_ptr(_name) class_##_name##_lock_ptr + +#define scoped_guard(_name, args...) \ + for (CLASS(_name, scope)(args), \ + *done = NULL; __guard_ptr(_name)(&scope) && !done; done = (void *)1) + #endif #endif /* KCL_CLEANUP_H_ */ diff --git a/include/kcl/kcl_mutex.h b/include/kcl/kcl_mutex.h new file mode 100644 index 0000000000000..4f04f50c91acd --- /dev/null +++ b/include/kcl/kcl_mutex.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Mutexes: blocking mutual exclusion locks + * + * started by Ingo Molnar: + * + * Copyright (C) 2004, 2005, 2006 Red Hat, Inc., Ingo Molnar + * + * This file contains the main data structure and API definitions. + */ +#ifndef __KCL_MUTEX_H +#define __KCL_MUTEX_H + +#include +#include + +#ifndef HAVE_LINUX_CLEANUP_H +DEFINE_GUARD(mutex, struct mutex *, mutex_lock(_T), mutex_unlock(_T)) +#endif + +#endif /* __LINUX_MUTEX_H */ From acb7baf0502bc4a90277ba94ae97842920c73332 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 24 Mar 2025 16:20:02 +0800 Subject: [PATCH 1458/2653] drm/amdkcl: add fd class definition It's caused by 6.4-3-g54da6a092431 locking: Introduce __cleanup() based infrastructure v6.12-rc2-14-g6348be02eead fdget(), trivial conversions Signed-off-by: Asher Song --- include/kcl/kcl_file.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_file.h b/include/kcl/kcl_file.h index 4c8a92d981141..f037be89b452c 100644 --- a/include/kcl/kcl_file.h +++ b/include/kcl/kcl_file.h @@ -15,4 +15,8 @@ static inline bool fd_empty(struct fd f) } #endif +#ifndef HAVE_LINUX_CLEANUP_H +DEFINE_CLASS(fd, struct fd, fdput(_T), fdget(fd), int fd) +#endif + #endif From 8ae14cacab4adba3de9c340c9a623394ea94e965 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Wed, 26 Feb 2025 11:12:19 -0500 Subject: [PATCH 1459/2653] drm/amdkfd: Limit use of USE_DEFAULT_GRACE_PERIOD Limit the use of macro USE_DEFAULT_GRACE_PERIOD to kfd_device_queue_manager.c. At this point it is not required outside this file. Signed-off-by: Harish Kasiviswanathan Reviewed-by: Amber Lin --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 5 ++--- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 3 +-- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 2 +- 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 223001cbea185..da063a8a03645 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -3706,12 +3706,11 @@ int debug_refresh_runlist(struct device_queue_manager *dqm) void remap_queue(struct device_queue_manager *dqm, enum kfd_unmap_queues_filter filter, - uint32_t filter_param, - uint32_t grace_period) + uint32_t filter_param) { dqm_lock(dqm); if (!dqm->dev->kfd->shared_resources.enable_mes) - execute_queues_cpsch(dqm, filter, filter_param, grace_period); + execute_queues_cpsch(dqm, filter, filter_param, USE_DEFAULT_GRACE_PERIOD); dqm_unlock(dqm); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 47d06a89d0edb..87d15d849d20f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -334,8 +334,7 @@ bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm, void remap_queue(struct device_queue_manager *dqm, enum kfd_unmap_queues_filter filter, - uint32_t filter_param, - uint32_t grace_period); + uint32_t filter_param); static inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 1f6342ea5c547..3af88cdd0d62b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -310,7 +310,7 @@ static int kfd_pc_sample_stop(struct kfd_process_device *pdd, kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, pcs_entry->method, false); remap_queue(pdd->dev->dqm, - KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); + KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0); if (pc_sampling_stop) { if (pcs_entry->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { From 576ebab3a89753fb3d22fab7cab071eb654230a0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 17 Mar 2025 12:29:48 +0800 Subject: [PATCH 1460/2653] drm/amdkcl: fake drm_dev_wedged_event It's caused by v6.14-rc1-238-gb7cf9f4ac1b8 drm: Introduce device wedged event Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c | 97 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../drm/amd/dkms/m4/drm-dev-wedged-event.m4 | 17 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_drv.h | 25 +++++ 6 files changed, 142 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 create mode 100644 include/kcl/kcl_drm_drv.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 9243f279303ef..c615b34b2e385 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -16,7 +16,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ - kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o + kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o kcl_drm_drv.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o kcl_debugfs_file.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c new file mode 100644 index 0000000000000..fcd6eab44d280 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c @@ -0,0 +1,97 @@ +/* + * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org + * + * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Author Rickard E. (Rik) Faith + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#ifndef HAVE_DRM_DEV_WEDGED_EVENT +/* + * Available recovery methods for wedged device. To be sent along with device + * wedged uevent. + */ +static const char *drm_get_wedge_recovery(unsigned int opt) +{ + switch (BIT(opt)) { + case DRM_WEDGE_RECOVERY_NONE: + return "none"; + case DRM_WEDGE_RECOVERY_REBIND: + return "rebind"; + case DRM_WEDGE_RECOVERY_BUS_RESET: + return "bus-reset"; + default: + return NULL; + } +} + +/** + * drm_dev_wedged_event - generate a device wedged uevent + * @dev: DRM device + * @method: method(s) to be used for recovery + * + * This generates a device wedged uevent for the DRM device specified by @dev. + * Recovery @method\(s) of choice will be sent in the uevent environment as + * ``WEDGED=[,..,]`` in order of less to more side-effects. + * If caller is unsure about recovery or @method is unknown (0), + * ``WEDGED=unknown`` will be sent instead. + * + * Refer to "Device Wedging" chapter in Documentation/gpu/drm-uapi.rst for more + * details. + * + * Returns: 0 on success, negative error code otherwise. + */ +int drm_dev_wedged_event(struct drm_device *dev, unsigned long method) +{ + const char *recovery = NULL; + unsigned int len, opt; + /* Event string length up to 28+ characters with available methods */ + char event_string[32]; + char *envp[] = { event_string, NULL }; + + len = scnprintf(event_string, sizeof(event_string), "%s", "WEDGED="); + + for_each_set_bit(opt, &method, BITS_PER_TYPE(method)) { + recovery = drm_get_wedge_recovery(opt); + if (drm_WARN_ONCE(dev, !recovery, "invalid recovery method %u\n", opt)) + break; + + len += scnprintf(event_string + len, sizeof(event_string), "%s,", recovery); + } + if (recovery) + /* Get rid of trailing comma */ + event_string[len - 1] = '\0'; + else + /* Caller is unsure about recovery, do the best we can at this point. */ + snprintf(event_string, sizeof(event_string), "%s", "WEDGED=unknown"); + + drm_info(dev, "device wedged, %s\n", method == DRM_WEDGE_RECOVERY_NONE ? + "but recovered through reset" : "needs recovery"); + + return kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, envp); +} +EXPORT_SYMBOL(drm_dev_wedged_event); + +#endif /* HAVE_DRM_DEV_WEDGED_EVENT */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 3edbe1edffb80..c0a2a626bacb4 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -145,4 +145,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 new file mode 100644 index 0000000000000..63ed3acc6c04c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.14-rc1-238-gb7cf9f4ac1b8 +dnl # drm: Introduce device wedged event +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEV_WEDGED_EVENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dev_wedged_event(NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_DEV_WEDGED_EVENT, 1, + [drm_dev_wedged_event() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cfdcf57474ab4..7d86ad7fad25b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -267,6 +267,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_DYNAMIC_INIT AC_AMDGPU_DRM_GET_PANEL_MIN_BRIGHTNESS_QUIRK AC_AMDGPU_MODULE_IMPORT_NS + AC_AMDGPU_DRM_DEV_WEDGED_EVENT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_drv.h b/include/kcl/kcl_drm_drv.h new file mode 100644 index 0000000000000..631e84df47a9e --- /dev/null +++ b/include/kcl/kcl_drm_drv.h @@ -0,0 +1,25 @@ + +#ifndef AMDKCL_DRM_DRV_H +#define AMDKCL_DRM_DRV_H + +#include +#include +#include +#include +#include + +#ifndef HAVE_DRM_DEV_WEDGED_EVENT +/* + * Recovery methods for wedged device in order of less to more side-effects. + * To be used with drm_dev_wedged_event() as recovery @method. Callers can + * use any one, multiple (or'd) or none depending on their needs. + */ +#define DRM_WEDGE_RECOVERY_NONE BIT(0) /* optional telemetry collection */ +#define DRM_WEDGE_RECOVERY_REBIND BIT(1) /* unbind + bind driver */ +#define DRM_WEDGE_RECOVERY_BUS_RESET BIT(2) /* unbind + reset bus device + bind */ + +int drm_dev_wedged_event(struct drm_device *dev, unsigned long method); +#endif /* HAVE_DRM_DEV_WEDGED_EVENT */ + +#endif /* AMDKCL_DRM_DRV_H */ + From 90e39653704a607f98e9538e6c81613f0692c045 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 17 Mar 2025 13:26:55 +0800 Subject: [PATCH 1461/2653] drm/amdkcl: Check Whether the argument is const in .mode_valid It's caused by v6.13-rc2-288-g26d6fd81916e drm/connector: make mode_valid take a const struct drm_display_mode Signed-off-by: Asher Song --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 18 ++++++++++++++++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 ++++ .../amd/dkms/m4/drm-connector-helper-funcs.m4 | 20 +++++++++++++++++++ 4 files changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 470ae8a879558..c8396f25856a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -715,7 +715,11 @@ static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) } static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT const struct drm_display_mode *mode) +#else + struct drm_display_mode *mode) +#endif { struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); @@ -880,7 +884,11 @@ static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) } static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT const struct drm_display_mode *mode) +#else + struct drm_display_mode *mode) +#endif { struct drm_device *dev = connector->dev; struct amdgpu_device *adev = drm_to_adev(dev); @@ -1255,7 +1263,11 @@ static void amdgpu_connector_dvi_force(struct drm_connector *connector) } static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT const struct drm_display_mode *mode) +#else + struct drm_display_mode *mode) +#endif { struct drm_device *dev = connector->dev; struct amdgpu_device *adev = drm_to_adev(dev); @@ -1541,7 +1553,11 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) } static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, - const struct drm_display_mode *mode) +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT + const struct drm_display_mode *mode) +#else + struct drm_display_mode *mode) +#endif { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0a5771aa7aae9..834c5e0bef9c7 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7904,7 +7904,11 @@ create_validate_stream_for_sink(struct drm_connector *connector, } enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT const struct drm_display_mode *mode) +#else + struct drm_display_mode *mode) +#endif { int result = MODE_ERROR; struct dc_sink *dc_sink; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index eaacdbd17e6cf..a5895226732eb 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -1017,7 +1017,11 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, int link_index); enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT const struct drm_display_mode *mode); +#else + struct drm_display_mode *mode); +#endif void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 index c31a4f9b86b56..b0930aa8e97cf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 @@ -36,7 +36,27 @@ AC_DEFUN([AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_ATOMIC_BEST_ENCODER], [ ]) ]) +dnl # +dnl # v6.13-rc2-288-g26d6fd81916e +dnl # drm/connector: make mode_valid take a const struct drm_display_mode +dnl # +AC_DEFUN([AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_MODE_VALID_CONST_ARGUMENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_connector_helper_funcs test_funcs = { + .mode_valid = (enum drm_mode_status (*)(struct drm_connector *, const struct drm_display_mode *))0 + }; + ], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT, 1, + [.mode_valid need a const drm_display_mode argument]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS], [ AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_ATOMIC_BEST_ENCODER + AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_MODE_VALID_CONST_ARGUMENT ]) From 8602b75ec3f8f7dc2ea473c7b96c8fa52224aab2 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 17 Mar 2025 14:06:23 +0800 Subject: [PATCH 1462/2653] drm/amdkcl: test .atomic_async_check in drm_plane_helper_funcs need three arguments It's caused by v6.14-rc1-243-gfd40a63c63a1 drm/atomic: Let drivers decide which planes to async flip Signed-off-by: Asher Song --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 16 ++++++++++++++-- .../amd/dkms/m4/struct_drm_plane_helper_funcs.m4 | 16 ++++++++++++++++ 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index bfcb1a9a82db1..a0ebaa2a3018f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1285,22 +1285,30 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, } static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, -#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS struct drm_atomic_state *state, bool flip) +#elif HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + struct drm_atomic_state *state) #else - struct drm_plane_state *state, bool flip) + struct drm_plane_state *state) #endif { struct drm_crtc_state *new_crtc_state; struct drm_plane_state *new_plane_state; struct dm_crtc_state *dm_new_crtc_state; +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS if (flip) { if (plane->type != DRM_PLANE_TYPE_OVERLAY) return -EINVAL; } else if (plane->type != DRM_PLANE_TYPE_CURSOR) { return -EINVAL; } +#else + /* Only support async updates on cursor planes. */ + if (plane->type != DRM_PLANE_TYPE_CURSOR) + return -EINVAL; +#endif #ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS new_plane_state = drm_atomic_get_new_plane_state(state, plane); @@ -1310,7 +1318,11 @@ static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, #endif dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); /* Reject overlay cursors for now*/ +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS if (!flip && dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) +#else + if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) +#endif return -EINVAL; return 0; diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 index fce9bda9696c0..eb9f77f9d6b37 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 @@ -32,8 +32,24 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER], [ ]) ]) +dnl # commit v6.14-rc1-243-gfd40a63c63a1 +dnl # drm/atomic: Let drivers decide which planes to async flip +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_plane_helper_funcs* funcs = NULL; + funcs->atomic_async_check(NULL, NULL, true); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS, 1, + [drm_plane_helper_funcs->atomic_async_check() have three arguments]) + ]) + ]) +]) AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS], [ AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER + AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS ]) From 37f16278b3d26aac81d94d3e4255227082d3ab37 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 24 Mar 2025 18:08:42 +0800 Subject: [PATCH 1463/2653] drm/amdkcl: test whether drm_driver->date exists It's caused by commit v6.13-rc1-117-gcb2e1c2136f7 drm: remove driver date from struct drm_driver and all drivers v4.9-rc4-834-g85e634bce01a drm: Extract drm_drv.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm-driver-date.m4 | 21 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 31 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-driver-date.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 446c4504b01db..705eff360f64a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3188,6 +3188,9 @@ static struct drm_driver amdgpu_kms_driver = { .name = DRIVER_NAME, .desc = DRIVER_DESC, +#ifdef HAVE_DRM_DRIVER_DATE + .date = DRIVER_DATE, +#endif .major = KMS_DRIVER_MAJOR, .minor = KMS_DRIVER_MINOR, .patchlevel = KMS_DRIVER_PATCHLEVEL, @@ -3221,6 +3224,9 @@ const struct drm_driver amdgpu_partition_driver = { .name = DRIVER_NAME, .desc = DRIVER_DESC, +#ifdef HAVE_DRM_DRIVER_DATE + .date = DRIVER_DATE, +#endif .major = KMS_DRIVER_MAJOR, .minor = KMS_DRIVER_MINOR, .patchlevel = KMS_DRIVER_PATCHLEVEL, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h index 2d86cc6f7f4dd..664f98371451f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h @@ -40,6 +40,9 @@ #define DRIVER_NAME "amdgpu" #define DRIVER_DESC "AMD GPU" +#ifdef HAVE_DRM_DRIVER_DATE +#define DRIVER_DATE "20150101" +#endif extern const struct drm_driver amdgpu_partition_driver; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-date.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-date.m4 new file mode 100644 index 0000000000000..b936fb17b95c8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-date.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v6.13-rc1-117-gcb2e1c2136f7 +dnl # drm: remove driver date from struct drm_driver and all drivers +dnl # +dnl # v4.9-rc4-834-g85e634bce01a +dnl # drm: Extract drm_drv.h +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_DATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + struct drm_driver *drm_driver = NULL; + drm_driver->date = NULL; + ],[ + AC_DEFINE(HAVE_DRM_DRIVER_DATE, 1, + [drm_driver->date is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7d86ad7fad25b..13c3d13c701dc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -268,6 +268,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GET_PANEL_MIN_BRIGHTNESS_QUIRK AC_AMDGPU_MODULE_IMPORT_NS AC_AMDGPU_DRM_DEV_WEDGED_EVENT + AC_AMDGPU_DRM_DRIVER_DATE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From dcc410d78e696a64d6ab6dd0590ff7b6cfaf1f00 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 25 Mar 2025 17:14:48 +0800 Subject: [PATCH 1464/2653] Bump AMDGPU version to 6.14.0 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 61 +++++++++++++++++++++--- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 2 files changed, 56 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a78a275b6d6c5..44dfce3afb5ba 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -91,6 +91,9 @@ /* compat_ptr_ioctl() is available */ #define HAVE_COMPAT_PTR_IOCTL 1 +/* need a const argument in member func .is_bin_visible */ +#define HAVE_CONSTANT_ARGUMENT_IN_IS_BIN_VISIBLE 1 + /* cpuinfo_x86.topo is available */ #define HAVE_CPUINFO_TOPOLOGY_IN_CPUINFO_X86_STRUCT 1 @@ -195,6 +198,10 @@ #define HAVE_DRM_ATOMIC_PLANE_ENABLING 1 +/* Define to 1 if you have the header file. + */ +#define HAVE_DRM_CLIENTS_DRM_CLIENT_SETUP_H 1 + /* drm_client_dev_resume() is available */ #define HAVE_DRM_CLIENT_DEV_RESUME 1 @@ -213,9 +220,15 @@ /* drm_connector_attach_hdr_output_metadata_property() is available */ #define HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY 1 +/* drm_connector_dynamic_init is available */ +#define HAVE_DRM_CONNECTOR_DYNAMIC_INIT 1 + /* drm_connector->edid_override is available */ #define HAVE_DRM_CONNECTOR_EDID_OVERRIDE 1 +/* drm_connector->eld_mutex is available */ +#define HAVE_DRM_CONNECTOR_ELD_MUTEX 1 + /* drm_connector_for_each_possible_encoder() wants 2 arguments */ #define HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS 1 @@ -227,6 +240,9 @@ arg */ #define HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE 1 +/* .mode_valid need a const drm_display_mode argument */ +#define HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT 1 + /* drm_connector_helper_funcs->prepare_writeback_job is available */ #define HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB 1 @@ -274,6 +290,9 @@ /* struct drm_device has pdev member */ /* #undef HAVE_DRM_DEVICE_PDEV */ +/* drm_dev_wedged_event() is available */ +#define HAVE_DRM_DEV_WEDGED_EVENT 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DISPLAY_DRM_DP_H 1 @@ -453,6 +472,9 @@ /* drm_dp_update_payload_part1() function has start_slot argument */ /* #undef HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG */ +/* drm_driver->date is available */ +/* #undef HAVE_DRM_DRIVER_DATE */ + /* drm_driver->gem_prime_mmap() is available */ /* #undef HAVE_DRM_DRIVER_GEM_PRIME_MMAP */ @@ -475,7 +497,7 @@ #define HAVE_DRM_DRM_CLIENT_EVENT_H 1 /* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_CLIENT_SETUP_H 1 +/* #undef HAVE_DRM_DRM_CLIENT_SETUP_H */ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_ELD_H 1 @@ -582,6 +604,9 @@ /* drm_gem_prime_handle_to_fd() is available */ #define HAVE_DRM_GEM_PRIME_HANDLE_TO_FD 1 +/* drm_get_panel_min_brightness_quirk() is available */ +#define HAVE_DRM_GET_PANEL_MIN_BRIGHTNESS_QUIRK 1 + /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 @@ -603,6 +628,9 @@ /* drm_memcpy_from_wc() is availablea and has struct iosys_map* arg */ #define HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG 1 +/* drm_memory_stats_is_zero() is available */ +#define HAVE_DRM_MEMORY_STATS_IS_ZERO 1 + /* drm_mode_config->dp_subconnector_property is available */ #define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 @@ -672,6 +700,9 @@ /* fault_flag_allow_retry_first() is available */ #define HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST 1 +/* fd_empty is available */ +#define HAVE_FD_EMPTY 1 + /* file_operation->fop_flags is available */ #define HAVE_FILE_OPERATION_FOP_FLAGS 1 @@ -804,6 +835,9 @@ /* ktime_t is union */ /* #undef HAVE_KTIME_IS_UNION */ +/* Define to 1 if you have the header file. */ +#define HAVE_KUNIT_TEST_BUG_H 1 + /* kvrealloc() is available */ /* #undef HAVE_KVREALLOC */ @@ -828,6 +862,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_CC_PLATFORM_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_CGROUP_DMEM_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_CLEANUP_H 1 @@ -870,12 +907,12 @@ /* local_try_cmpchg() is available */ #define HAVE_LINUX_LOCAL_TRY_CMPXCHG 1 -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_MMAP_LOCK_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_LINUX_MINMAX_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_MMAP_LOCK_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PCI_P2PDMA_H 1 @@ -945,6 +982,9 @@ /* release_pages() wants 2 args */ #define HAVE_MM_RELEASE_PAGES_2ARGS 1 +/* MODULE_IMPORT_NS() wants a string arguments */ +#define HAVE_MODULE_IMPORT_NS_NEED_A_STRING 1 + /* class_create has one argument */ #define HAVE_ONE_ARGUMENT_OF_CLASS_CREATE 1 @@ -1026,6 +1066,9 @@ /* sg_alloc_table_from_pages_segment() is available */ #define HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT 1 +/* shmem_read_folio() is available */ +#define HAVE_SHMEM_READ_FOLIO 1 + /* shrinker_register() is available */ #define HAVE_SHRINKER_REGISTER 1 @@ -1068,6 +1111,12 @@ /* drm_gem_open_object is defined in struct drm_drv */ /* #undef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ +/* struct drm_memory_stats is defined */ +#define HAVE_STRUCT_DRM_MEMORY_STATS 1 + +/* drm_plane_helper_funcs->atomic_async_check() have three arguments */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS 1 + /* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 @@ -1190,7 +1239,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 6.12.0" +#define PACKAGE_STRING "amdgpu-dkms 6.14.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1199,7 +1248,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "6.12.0" +#define PACKAGE_VERSION "6.14.0" #include "config-amd-chips.h" diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 808c3a42b1f99..8aeb6183e9faa 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.12.0) +AC_INIT(amdgpu-dkms, 6.14.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 3bff0d95f8b32754614127951d49dea16e4a9a57 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 14 Mar 2025 10:25:03 +0800 Subject: [PATCH 1465/2653] drm/amdkcl: fix drm_device release leak on legacy kernel Reviewed-by: Bob Zhou Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c index 8bc36f04b1b71..9281db9ae668a 100644 --- a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c +++ b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c @@ -25,6 +25,10 @@ #include #include #include +#ifndef HAVE_DRM_DRM_MANAGED_H +#include +#include +#endif #include @@ -96,6 +100,10 @@ void amdgpu_xcp_drv_release(void) devres_release_group(&pdev->dev, NULL); platform_device_unregister(pdev); +#ifndef HAVE_DRM_DRM_MANAGED_H + drm_dev_fini(&(xcp_dev[pdev_num]->drm)); + kfree(xcp_dev[pdev_num]); +#endif xcp_dev[pdev_num] = NULL; } pdev_num = 0; From d66262b7ec3ac5f032cbb8307acef91744b7c62e Mon Sep 17 00:00:00 2001 From: chengjya Date: Thu, 20 Mar 2025 10:39:03 +0800 Subject: [PATCH 1466/2653] drm/amdkcl: use GFP_NOWAIT for memory allocations on non-upstream code It's caused by the commit: 7d3a3a2 "drm/amdgpu: use GFP_NOWAIT for memory allocations" Signed-off-by: chengjya Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c index 432072b28f5ae..b418bfe412589 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c @@ -408,7 +408,7 @@ int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct drm_sched_entity *entity, mutex_lock(¢ity->sem_lock); list_for_each_entry_safe(dep, tmp, ¢ity->sem_dep_list, list) { - r = amdgpu_sync_fence(sync, dep->fence); + r = amdgpu_sync_fence(sync, dep->fence, GFP_KERNEL); if (r) goto err; dma_fence_put(dep->fence); From fb7a587207d97da3f5d1d0fa46c73292d891737c Mon Sep 17 00:00:00 2001 From: James Zhu Date: Tue, 18 Mar 2025 14:59:55 -0400 Subject: [PATCH 1467/2653] drm/kfd: add Stochastic PC sampling support for gfx9_5_0. Signed-off-by: James Zhu Reviewed-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 3af88cdd0d62b..b2fefc190db39 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -37,9 +37,10 @@ * 1.1 - Support gfx9_4_3 Stochastic PC sampling * 1.2 - Support gfx9_5_0 Host Trap PC sampling * 1.3 - Update 1st level trap handler for Stochastic PC sampling + * 1.4 - Support gfx9_5_0 Stochastic PC sampling */ #define KFD_IOCTL_PCS_MAJOR_VERSION 1 -#define KFD_IOCTL_PCS_MINOR_VERSION 3 +#define KFD_IOCTL_PCS_MINOR_VERSION 4 struct supported_pc_sample_info { uint32_t ip_version; @@ -58,6 +59,7 @@ struct supported_pc_sample_info supported_formats[] = { { IP_VERSION(9, 4, 3), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 4, 3), &sample_info_stoch_cycle_9_4_3 }, { IP_VERSION(9, 5, 0), &sample_info_hosttrap_9_0_0 }, + { IP_VERSION(9, 5, 0), &sample_info_stoch_cycle_9_4_3 }, }; static int kfd_pc_sample_thread(void *param) From 10185b4b9b350bd1089ce71167e7739787a6df7f Mon Sep 17 00:00:00 2001 From: chengjya Date: Thu, 20 Mar 2025 17:30:32 +0800 Subject: [PATCH 1468/2653] drm/amdkcl: test whether __assign_str() wants 1 arguments It's caused by 5c05f70f "drm/amdgpu: add cleaner shader trace point" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index d97e196023058..eb878eadf8461 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -479,7 +479,7 @@ TRACE_EVENT(amdgpu_cleaner_shader, ), TP_fast_assign( - __assign_str(ring); + __amdkcl_assign_str(ring, ring->name); __entry->seqno = fence->seqno; ), TP_printk("ring=%s, seqno=%Lu", __get_str(ring), __entry->seqno) From 46d127aee375ffe8d16de95f7af8da5295dfae4b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 27 Feb 2025 16:49:31 +0800 Subject: [PATCH 1469/2653] drm/amdkcl: spilt amdkcl_gem_resvp to kcl_drm_gem.h Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- include/kcl/kcl_drm_exec.h | 5 ----- include/kcl/kcl_drm_gem.h | 6 ++++++ 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/include/kcl/kcl_drm_exec.h b/include/kcl/kcl_drm_exec.h index 2ffba4ce2fef7..ef0feb3c69e28 100644 --- a/include/kcl/kcl_drm_exec.h +++ b/include/kcl/kcl_drm_exec.h @@ -6,11 +6,6 @@ #include #include -#ifdef HAVE_DRM_GEM_OBJECT_RESV -#define amdkcl_gem_resvp(bo) (bo->resv) -#else -#define amdkcl_gem_resvp(bo) (container_of(bo, struct ttm_buffer_object, base)->resv) -#endif #ifndef HAVE_DRM_DRM_EXEC_H #include #include diff --git a/include/kcl/kcl_drm_gem.h b/include/kcl/kcl_drm_gem.h index cea563821fa86..da5df184d9d58 100644 --- a/include/kcl/kcl_drm_gem.h +++ b/include/kcl/kcl_drm_gem.h @@ -36,6 +36,12 @@ #include +#ifdef HAVE_DRM_GEM_OBJECT_RESV +#define amdkcl_gem_resvp(bo) (bo->resv) +#else +#define amdkcl_gem_resvp(bo) (container_of(bo, struct ttm_buffer_object, base)->resv) +#endif + #ifndef HAVE_DRM_PRINT_MEMORY_STATS enum drm_gem_object_status { DRM_GEM_OBJECT_RESIDENT = BIT(0), From 0753281c7c02f3fea1b9a97fe754f683f0aef582 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 27 Feb 2025 16:47:33 +0800 Subject: [PATCH 1470/2653] Revert "drm/amdkcl: test drm_exec_init whether has three arguments" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 - drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/drm-exec.m4 | 20 -------------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/backport/kcl_drm_exec.h | 18 ------------------ 5 files changed, 43 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-exec.m4 delete mode 100644 include/kcl/backport/kcl_drm_exec.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index c0a2a626bacb4..7a2e836126694 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -123,7 +123,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 44dfce3afb5ba..98308a17a47f6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -559,9 +559,6 @@ /* drm_edid_valid() is available */ #define HAVE_DRM_EDID_VALID 1 -/* drm_exec() has 3 arguments */ -#define HAVE_DRM_EXEC_INIT_3_ARGUMENTS 1 - /* drm_fb_helper_fill_info() is available */ #define HAVE_DRM_FB_HELPER_FILL_INFO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-exec.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-exec.m4 deleted file mode 100644 index b481cf6b7945e..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-exec.m4 +++ /dev/null @@ -1,20 +0,0 @@ -dnl # -dnl # commit 05d249352f1ae909230c230767ca8f4e9fdf8e7b -dnl # drm/exec: Pass in initial # of objects -dnl # -AC_DEFUN([AC_AMDGPU_DRM_EXEC_INIT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - drm_exec_init(NULL, 0, 0); - ], [ - AC_DEFINE(HAVE_DRM_EXEC_INIT_3_ARGUMENTS, 1, - [drm_exec() has 3 arguments]) - ]) - ]) -]) - -AC_DEFUN([AC_AMDGPU_DRM_EXEC], [ - AC_AMDGPU_DRM_EXEC_INIT -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 13c3d13c701dc..f5bc69308ea24 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -238,7 +238,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CPUINFO_X86 AC_AMDGPU_DMA_FENCE_IS_LATER_OR_SAME AC_AMDGPU_WORKQUEUE - AC_AMDGPU_DRM_EXEC_INIT AC_AMDGPU_DRM_DBG_PRINTER AC_AMDGPU_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS AC_AMDGPU_DRM_DEBUG_CATEGORY diff --git a/include/kcl/backport/kcl_drm_exec.h b/include/kcl/backport/kcl_drm_exec.h deleted file mode 100644 index 0d86a455cabdc..0000000000000 --- a/include/kcl/backport/kcl_drm_exec.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef AMDKCL_BACKPORT_KCL_DRM_EXEC_H -#define AMDKCL_BACKPORT_KCL_DRM_EXEC_H - -#include -#include - -#ifndef HAVE_DRM_EXEC_INIT_3_ARGUMENTS -static inline -void _kcl_drm_exec_init(struct drm_exec *exec, uint32_t flags, unsigned nr) -{ - return drm_exec_init(exec, flags); -} - -#define drm_exec_init _kcl_drm_exec_init -#endif /* HAVE_DRM_EXEC_INIT_3_ARGUMENTS */ - -#endif From d22465401b52aeb667c46529eb319f1c80c9f0d7 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 27 Feb 2025 13:44:30 +0800 Subject: [PATCH 1471/2653] Revert "drm/amdkcl: fake drm_exec_*" This reverts commit 2f0607a1495eb8c17b069c028e9f08ab07628235. Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c | 335 ------------------ drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 18 - drivers/gpu/drm/amd/backport/backport.h | 1 - drivers/gpu/drm/amd/dkms/config/config.h | 6 - drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 - drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 | 21 -- include/kcl/header/drm/drm_exec.h | 9 - include/kcl/kcl_drm_exec.h | 127 ------- include/kcl/kcl_slab.h | 4 - 11 files changed, 1 insertion(+), 529 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c delete mode 100644 include/kcl/header/drm/drm_exec.h delete mode 100644 include/kcl/kcl_drm_exec.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index c615b34b2e385..e3c88238151e9 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o \ + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o kcl_drm_drv.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c deleted file mode 100644 index 1ce1651265c24..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c +++ /dev/null @@ -1,335 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT - -#include -#include -#include -#include -#include - -#ifndef HAVE_DRM_DRM_EXEC_H -/** - * DOC: Overview - * - * This component mainly abstracts the retry loop necessary for locking - * multiple GEM objects while preparing hardware operations (e.g. command - * submissions, page table updates etc..). - * - * If a contention is detected while locking a GEM object the cleanup procedure - * unlocks all previously locked GEM objects and locks the contended one first - * before locking any further objects. - * - * After an object is locked fences slots can optionally be reserved on the - * dma_resv object inside the GEM object. - * - * A typical usage pattern should look like this:: - * - * struct drm_gem_object *obj; - * struct drm_exec exec; - * unsigned long index; - * int ret; - * - * drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT); - * drm_exec_until_all_locked(&exec) { - * ret = drm_exec_prepare_obj(&exec, boA, 1); - * drm_exec_retry_on_contention(&exec); - * if (ret) - * goto error; - * - * ret = drm_exec_prepare_obj(&exec, boB, 1); - * drm_exec_retry_on_contention(&exec); - * if (ret) - * goto error; - * } - * - * drm_exec_for_each_locked_object(&exec, index, obj) { - * dma_resv_add_fence(obj->resv, fence, DMA_RESV_USAGE_READ); - * ... - * } - * drm_exec_fini(&exec); - * - * See struct dma_exec for more details. - */ - -/* Dummy value used to initially enter the retry loop */ -#define DRM_EXEC_DUMMY ((void *)~0) - -/* Unlock all objects and drop references */ -static void drm_exec_unlock_all(struct drm_exec *exec) -{ - struct drm_gem_object *obj; - unsigned long index; - - drm_exec_for_each_locked_object(exec, index, obj) { - dma_resv_unlock(amdkcl_gem_resvp(obj)); - drm_gem_object_put(obj); - } - - drm_gem_object_put(exec->prelocked); - exec->prelocked = NULL; -} - -/** - * drm_exec_init - initialize a drm_exec object - * @exec: the drm_exec object to initialize - * @flags: controls locking behavior, see DRM_EXEC_* defines - * - * Initialize the object and make sure that we can track locked objects. - */ -void drm_exec_init(struct drm_exec *exec, uint32_t flags) -{ - exec->flags = flags; - exec->objects = kmalloc(PAGE_SIZE, GFP_KERNEL); - - /* If allocation here fails, just delay that till the first use */ - exec->max_objects = exec->objects ? PAGE_SIZE / sizeof(void *) : 0; - exec->num_objects = 0; - exec->contended = DRM_EXEC_DUMMY; - exec->prelocked = NULL; -} -EXPORT_SYMBOL(drm_exec_init); - -/** - * drm_exec_fini - finalize a drm_exec object - * @exec: the drm_exec object to finalize - * - * Unlock all locked objects, drop the references to objects and free all memory - * used for tracking the state. - */ -void drm_exec_fini(struct drm_exec *exec) -{ - drm_exec_unlock_all(exec); - kvfree(exec->objects); - if (exec->contended != DRM_EXEC_DUMMY) { - drm_gem_object_put(exec->contended); - ww_acquire_fini(&exec->ticket); - } -} -EXPORT_SYMBOL(drm_exec_fini); - -/** - * drm_exec_cleanup - cleanup when contention is detected - * @exec: the drm_exec object to cleanup - * - * Cleanup the current state and return true if we should stay inside the retry - * loop, false if there wasn't any contention detected and we can keep the - * objects locked. - */ -bool drm_exec_cleanup(struct drm_exec *exec) -{ - if (likely(!exec->contended)) { - ww_acquire_done(&exec->ticket); - return false; - } - - if (likely(exec->contended == DRM_EXEC_DUMMY)) { - exec->contended = NULL; - ww_acquire_init(&exec->ticket, &reservation_ww_class); - return true; - } - - drm_exec_unlock_all(exec); - exec->num_objects = 0; - return true; -} -EXPORT_SYMBOL(drm_exec_cleanup); - -/* Track the locked object in the array */ -static int drm_exec_obj_locked(struct drm_exec *exec, - struct drm_gem_object *obj) -{ - if (unlikely(exec->num_objects == exec->max_objects)) { - size_t size = exec->max_objects * sizeof(void *); - void *tmp; - - tmp = kvrealloc(exec->objects, size, size + PAGE_SIZE, - GFP_KERNEL); - if (!tmp) - return -ENOMEM; - - exec->objects = tmp; - exec->max_objects += PAGE_SIZE / sizeof(void *); - } - drm_gem_object_get(obj); - exec->objects[exec->num_objects++] = obj; - - return 0; -} - -/* Make sure the contended object is locked first */ -static int drm_exec_lock_contended(struct drm_exec *exec) -{ - struct drm_gem_object *obj = exec->contended; - int ret; - - if (likely(!obj)) - return 0; - - /* Always cleanup the contention so that error handling can kick in */ - exec->contended = NULL; - if (exec->flags & DRM_EXEC_INTERRUPTIBLE_WAIT) { - ret = dma_resv_lock_slow_interruptible(amdkcl_gem_resvp(obj), - &exec->ticket); - if (unlikely(ret)) - goto error_dropref; - } else { - dma_resv_lock_slow(amdkcl_gem_resvp(obj), &exec->ticket); - } - - ret = drm_exec_obj_locked(exec, obj); - if (unlikely(ret)) - goto error_unlock; - - exec->prelocked = obj; - return 0; - -error_unlock: - dma_resv_unlock(amdkcl_gem_resvp(obj)); - -error_dropref: - drm_gem_object_put(obj); - return ret; -} - -/** - * drm_exec_lock_obj - lock a GEM object for use - * @exec: the drm_exec object with the state - * @obj: the GEM object to lock - * - * Lock a GEM object for use and grab a reference to it. - * - * Returns: -EDEADLK if a contention is detected, -EALREADY when object is - * already locked (can be suppressed by setting the DRM_EXEC_IGNORE_DUPLICATES - * flag), -ENOMEM when memory allocation failed and zero for success. - */ -int drm_exec_lock_obj(struct drm_exec *exec, struct drm_gem_object *obj) -{ - int ret; - - ret = drm_exec_lock_contended(exec); - if (unlikely(ret)) - return ret; - - if (exec->prelocked == obj) { - drm_gem_object_put(exec->prelocked); - exec->prelocked = NULL; - return 0; - } - - if (exec->flags & DRM_EXEC_INTERRUPTIBLE_WAIT) - ret = dma_resv_lock_interruptible(amdkcl_gem_resvp(obj), &exec->ticket); - else - ret = dma_resv_lock(amdkcl_gem_resvp(obj), &exec->ticket); - - if (unlikely(ret == -EDEADLK)) { - drm_gem_object_get(obj); - exec->contended = obj; - return -EDEADLK; - } - - if (unlikely(ret == -EALREADY) && - exec->flags & DRM_EXEC_IGNORE_DUPLICATES) - return 0; - - if (unlikely(ret)) - return ret; - - ret = drm_exec_obj_locked(exec, obj); - if (ret) - goto error_unlock; - - return 0; - -error_unlock: - dma_resv_unlock(amdkcl_gem_resvp(obj)); - return ret; -} -EXPORT_SYMBOL(drm_exec_lock_obj); - -/** - * drm_exec_unlock_obj - unlock a GEM object in this exec context - * @exec: the drm_exec object with the state - * @obj: the GEM object to unlock - * - * Unlock the GEM object and remove it from the collection of locked objects. - * Should only be used to unlock the most recently locked objects. It's not time - * efficient to unlock objects locked long ago. - */ -void drm_exec_unlock_obj(struct drm_exec *exec, struct drm_gem_object *obj) -{ - unsigned int i; - - for (i = exec->num_objects; i--;) { - if (exec->objects[i] == obj) { - dma_resv_unlock(amdkcl_gem_resvp(obj)); - for (++i; i < exec->num_objects; ++i) - exec->objects[i - 1] = exec->objects[i]; - --exec->num_objects; - drm_gem_object_put(obj); - return; - } - - } -} -EXPORT_SYMBOL(drm_exec_unlock_obj); - -/** - * drm_exec_prepare_obj - prepare a GEM object for use - * @exec: the drm_exec object with the state - * @obj: the GEM object to prepare - * @num_fences: how many fences to reserve - * - * Prepare a GEM object for use by locking it and reserving fence slots. - * - * Returns: -EDEADLK if a contention is detected, -EALREADY when object is - * already locked, -ENOMEM when memory allocation failed and zero for success. - */ -int drm_exec_prepare_obj(struct drm_exec *exec, struct drm_gem_object *obj, - unsigned int num_fences) -{ - int ret; - - ret = drm_exec_lock_obj(exec, obj); - if (ret) - return ret; - - ret = dma_resv_reserve_fences(amdkcl_gem_resvp(obj), num_fences); - if (ret) { - drm_exec_unlock_obj(exec, obj); - return ret; - } - - return 0; -} -EXPORT_SYMBOL(drm_exec_prepare_obj); - -/** - * drm_exec_prepare_array - helper to prepare an array of objects - * @exec: the drm_exec object with the state - * @objects: array of GEM object to prepare - * @num_objects: number of GEM objects in the array - * @num_fences: number of fences to reserve on each GEM object - * - * Prepares all GEM objects in an array, aborts on first error. - * Reserves @num_fences on each GEM object after locking it. - * - * Returns: -EDEADLOCK on contention, -EALREADY when object is already locked, - * -ENOMEM when memory allocation failed and zero for success. - */ -int drm_exec_prepare_array(struct drm_exec *exec, - struct drm_gem_object **objects, - unsigned int num_objects, - unsigned int num_fences) -{ - int ret; - - for (unsigned int i = 0; i < num_objects; ++i) { - ret = drm_exec_prepare_obj(exec, objects[i], num_fences); - if (unlikely(ret)) - return ret; - } - - return 0; -} -EXPORT_SYMBOL(drm_exec_prepare_array); - -#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index 06854f1c32809..36d00435c99d7 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -37,24 +37,6 @@ extern struct kmem_cache *(*_kcl_kmalloc_slab)(size_t size, gfp_t flags); #endif #endif /* HAVE_KMALLOC_SIZE_ROUNDUP */ -#if !defined(HAVE_KVREALLOC) && !defined(kvrealloc) -void *kvrealloc(const void *p, size_t oldsize, size_t newsize, gfp_t flags) -{ - void *newp; - - if (oldsize >= newsize) - return (void *)p; - newp = kvmalloc(newsize, flags); - if (!newp) - return NULL; - memcpy(newp, p, oldsize); - kvfree(p); - return newp; -} -EXPORT_SYMBOL(kvrealloc); -#endif - - void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7a2e836126694..f1bea2e997789 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -113,7 +113,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 98308a17a47f6..76d59188a1fe5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -502,9 +502,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_ELD_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_EXEC_H 1 - /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRM_FBDEV_GENERIC_H */ @@ -835,9 +832,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_KUNIT_TEST_BUG_H 1 -/* kvrealloc() is available */ -/* #undef HAVE_KVREALLOC */ - /* Define to 1 if you have the header file. */ #define HAVE_LINUX_ACPI_AMD_WBRF_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 81510494154aa..bca9e1778fa23 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -98,12 +98,6 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/suballoc: Extract amdgpu_sa.c as generic suballocation helper dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_suballoc.h]) - - dnl # - dnl # v6.4-rc7-2018-g09593216bff1 - dnl # drm: execution context for GEM buffers v7 - dnl # - AC_KERNEL_CHECK_HEADERS([drm/drm_exec.h]) dnl # dnl # v6.6-rc2-771-g8eb80946ab0c diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f5bc69308ea24..e0f266a77aa9e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -224,7 +224,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_AMDGPU_LINUX_DEVICE_CLASS - AC_AMDGPU_KVREALLOC AC_AMDGPU_DMA_BUF_IS_DYNAMIC AC_AMDGPU_RADIX_TREE_ITER_DELETE AC_AMDGPU_KFIFO_PUT diff --git a/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 b/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 index 0cd6663de85ce..07199f0827e93 100644 --- a/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 @@ -17,24 +17,3 @@ AC_DEFUN([AC_AMDGPU_KREALLOC_ARRAY], [ ]) ]) -dnl # -dnl # -dnl #v5.15-11-g8587ca6f3415 mm: move kvmalloc-related functions to slab.h -dnl #v5.14-rc4-23-gde2860f46362 mm: Add kvrealloc() -dnl # -AC_DEFUN([AC_AMDGPU_KVREALLOC], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - #include - #include - ], [ - void *p = NULL; - p = kvrealloc(NULL, 0, 0, GFP_KERNEL); - ], [ - AC_DEFINE(HAVE_KVREALLOC, 1, - [kvrealloc() is available]) - ]) - ]) -]) - diff --git a/include/kcl/header/drm/drm_exec.h b/include/kcl/header/drm/drm_exec.h deleted file mode 100644 index 62aff24d17425..0000000000000 --- a/include/kcl/header/drm/drm_exec.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER_DRM_EXEC_H_H_ -#define _KCL_HEADER_DRM_EXEC_H_H_ - -#ifdef HAVE_DRM_DRM_EXEC_H -#include_next -#endif - -#endif diff --git a/include/kcl/kcl_drm_exec.h b/include/kcl/kcl_drm_exec.h deleted file mode 100644 index ef0feb3c69e28..0000000000000 --- a/include/kcl/kcl_drm_exec.h +++ /dev/null @@ -1,127 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR MIT */ - -#ifndef AMDKCL_DRM_EXEC_H -#define AMDKCL_DRM_EXEC_H - -#include -#include - -#ifndef HAVE_DRM_DRM_EXEC_H -#include -#include -#include -#define DRM_EXEC_INTERRUPTIBLE_WAIT BIT(0) -#define DRM_EXEC_IGNORE_DUPLICATES BIT(1) - -struct drm_gem_object; - -/** - * struct drm_exec - Execution context - */ -struct drm_exec { - /** - * @flags: Flags to control locking behavior - */ - uint32_t flags; - - /** - * @ticket: WW ticket used for acquiring locks - */ - struct ww_acquire_ctx ticket; - - /** - * @num_objects: number of objects locked - */ - unsigned int num_objects; - - /** - * @max_objects: maximum objects in array - */ - unsigned int max_objects; - - /** - * @objects: array of the locked objects - */ - struct drm_gem_object **objects; - - /** - * @contended: contended GEM object we backed off for - */ - struct drm_gem_object *contended; - - /** - * @prelocked: already locked GEM object due to contention - */ - struct drm_gem_object *prelocked; -}; - -/** - * drm_exec_for_each_locked_object - iterate over all the locked objects - * @exec: drm_exec object - * @index: unsigned long index for the iteration - * @obj: the current GEM object - * - * Iterate over all the locked GEM objects inside the drm_exec object. - */ -#define drm_exec_for_each_locked_object(exec, index, obj) \ - for (index = 0, obj = (exec)->objects[0]; \ - index < (exec)->num_objects; \ - ++index, obj = (exec)->objects[index]) - -/** - * drm_exec_until_all_locked - loop until all GEM objects are locked - * @exec: drm_exec object - * - * Core functionality of the drm_exec object. Loops until all GEM objects are - * locked and no more contention exists. At the beginning of the loop it is - * guaranteed that no GEM object is locked. - * - * Since labels can't be defined local to the loops body we use a jump pointer - * to make sure that the retry is only used from within the loops body. - */ -#define drm_exec_until_all_locked(exec) \ -__PASTE(__drm_exec_, __LINE__): \ - for (void *__drm_exec_retry_ptr; ({ \ - __drm_exec_retry_ptr = &&__PASTE(__drm_exec_, __LINE__);\ - (void)__drm_exec_retry_ptr; \ - drm_exec_cleanup(exec); \ - });) - -/** - * drm_exec_retry_on_contention - restart the loop to grap all locks - * @exec: drm_exec object - * - * Control flow helper to continue when a contention was detected and we need to - * clean up and re-start the loop to prepare all GEM objects. - */ -#define drm_exec_retry_on_contention(exec) \ - do { \ - if (unlikely(drm_exec_is_contended(exec))) \ - goto *__drm_exec_retry_ptr; \ - } while (0) - -/** - * drm_exec_is_contended - check for contention - * @exec: drm_exec object - * - * Returns true if the drm_exec object has run into some contention while - * locking a GEM object and needs to clean up. - */ -static inline bool drm_exec_is_contended(struct drm_exec *exec) -{ - return !!exec->contended; -} - -void drm_exec_init(struct drm_exec *exec, uint32_t flags); -void drm_exec_fini(struct drm_exec *exec); -bool drm_exec_cleanup(struct drm_exec *exec); -int drm_exec_lock_obj(struct drm_exec *exec, struct drm_gem_object *obj); -void drm_exec_unlock_obj(struct drm_exec *exec, struct drm_gem_object *obj); -int drm_exec_prepare_obj(struct drm_exec *exec, struct drm_gem_object *obj, - unsigned int num_fences); -int drm_exec_prepare_array(struct drm_exec *exec, - struct drm_gem_object **objects, - unsigned int num_objects, - unsigned int num_fences); -#endif -#endif diff --git a/include/kcl/kcl_slab.h b/include/kcl/kcl_slab.h index 8bff76afca13b..bac4078a6e36a 100644 --- a/include/kcl/kcl_slab.h +++ b/include/kcl/kcl_slab.h @@ -39,10 +39,6 @@ krealloc_array(void *p, size_t new_n, size_t new_size, gfp_t flags) size_t kmalloc_size_roundup(size_t size); #endif -#if !defined(HAVE_KVREALLOC) && !defined(kvrealloc) -extern void *kvrealloc(const void *p, size_t oldsize, size_t newsize, gfp_t flags); -#endif - #ifndef HAVE_LINUX_CLEANUP_H DEFINE_FREE(kfree, void *, if (_T) kfree(_T)) #endif From 920052951edb1a07c93fe8307f79f5d405ed8376 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 28 Feb 2025 17:41:11 +0800 Subject: [PATCH 1472/2653] drm/amdkcl: include drm_exec.ko from kernel Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/files | 2 +- drivers/gpu/drm/amd/dkms/Kbuild | 2 +- drivers/gpu/drm/amd/dkms/Makefile.drm_exec | 6 ++++++ drivers/gpu/drm/amd/dkms/dkms.conf | 10 +++++++--- drivers/gpu/drm/amd/dkms/sources | 2 ++ 5 files changed, 17 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/Makefile.drm_exec diff --git a/drivers/gpu/drm/amd/amdkcl/files b/drivers/gpu/drm/amd/amdkcl/files index 20534a90dbb86..64e285805c292 100644 --- a/drivers/gpu/drm/amd/amdkcl/files +++ b/drivers/gpu/drm/amd/amdkcl/files @@ -1 +1 @@ -FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c drm_gem_ttm_helper.c drm_buddy.c" +FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c drm_gem_ttm_helper.c drm_exec.c drm_buddy.c" diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index d4ab165eeaf09..02fb141c1d995 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -73,7 +73,7 @@ $(warning "The local C standard(gnu89) doesn't match kernel default C standard(g endif include $(src)/amd/dkms/Makefile.drm_ttm_helper - +include $(src)/amd/dkms/Makefile.drm_exec include $(src)/amd/dkms/Makefile.drm_buddy obj-m += scheduler/ amd/amdgpu/ amd/amdxcp/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/Makefile.drm_exec b/drivers/gpu/drm/amd/dkms/Makefile.drm_exec new file mode 100644 index 0000000000000..3c01e88c56700 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.drm_exec @@ -0,0 +1,6 @@ +export CONFIG_DRM_EXEC=m + +subdir-ccflags-y += -DCONFIG_DRM_EXEC +CFLAGS_drm_exec.o += -include linux/module.h -DHAVE_CONFIG_H +amddrm_exec-y := drm_exec.o +obj-$(CONFIG_DRM_EXEC) += amddrm_exec.o diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 7d262536848b6..15287e5222ac3 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -31,9 +31,13 @@ BUILT_MODULE_NAME[5]="amddrm_buddy" BUILT_MODULE_LOCATION[5]="." DEST_MODULE_LOCATION[5]="/kernel/drivers/gpu/drm" -BUILT_MODULE_NAME[6]="amdxcp" -BUILT_MODULE_LOCATION[6]="amd/amdxcp" -DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm/amd/amdxcp" +BUILT_MODULE_NAME[6]="amddrm_exec" +BUILT_MODULE_LOCATION[6]="." +DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm" + +BUILT_MODULE_NAME[7]="amdxcp" +BUILT_MODULE_LOCATION[7]="amd/amdxcp" +DEST_MODULE_LOCATION[7]="/kernel/drivers/gpu/drm/amd/amdxcp" MAKE[0]="'make' KERNELVER=$kernelver" diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources index 373b38d0d2325..34f51478f5472 100644 --- a/drivers/gpu/drm/amd/dkms/sources +++ b/drivers/gpu/drm/amd/dkms/sources @@ -33,3 +33,5 @@ drivers/gpu/drm/drm_gem_ttm_helper.c . include/drm/drm_gem_ttm_helper.h include/drm/ drivers/gpu/drm/drm_buddy.c . include/drm/drm_buddy.h include/drm/ +drivers/gpu/drm/drm_exec.c . +include/drm/drm_exec.h include/drm/ From a6a1d9a1c26444bfcde13e2e8693a4667e0569e0 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 21 Mar 2025 15:25:51 +0800 Subject: [PATCH 1473/2653] drm/amdkcl: fake kvrealloc for drm_exec Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_memory.c | 18 ++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 9 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 | 34 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 10 ++++++ include/kcl/kcl_memory.h | 4 +++ 6 files changed, 76 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c index f5d947730e628..606ae29de54ae 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c @@ -29,6 +29,7 @@ * Authors: Thomas Hellstrom */ #include +#include /* Copied from drivers/gpu/drm/ttm/ttm_bo_vm.c and modified for KCL */ #ifndef HAVE_VMF_INSERT_MIXED_PROT @@ -71,3 +72,20 @@ vm_fault_t _kcl_vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long ad } EXPORT_SYMBOL(_kcl_vmf_insert_pfn_prot); #endif + +/* Copied from mm/util.c and modified for KCL */ +#ifdef HAVE_NO_KVREALLOC +void *kvrealloc(const void *p, size_t oldsize, size_t newsize, gfp_t flags) +{ + void *newp; + if (oldsize >= newsize) + return (void *)p; + newp = kvmalloc(newsize, flags); + if (!newp) + return NULL; + memcpy(newp, p, oldsize); + kvfree(p); + return newp; +} +EXPORT_SYMBOL(kvrealloc); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 76d59188a1fe5..50a7118a08a5f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -832,6 +832,12 @@ /* Define to 1 if you have the header file. */ #define HAVE_KUNIT_TEST_BUG_H 1 +/* kvrealloc() has 3 arguments */ +#define HAVE_KVREALLOC_3ARG 1 + +/* kvrealloc() has 4 arguments */ +/* #undef HAVE_KVREALLOC_4ARG */ + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_ACPI_AMD_WBRF_H 1 @@ -976,6 +982,9 @@ /* MODULE_IMPORT_NS() wants a string arguments */ #define HAVE_MODULE_IMPORT_NS_NEED_A_STRING 1 +/* kvrealloc() isn't available */ +/* #undef HAVE_NO_KVREALLOC */ + /* class_create has one argument */ #define HAVE_ONE_ARGUMENT_OF_CLASS_CREATE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e0f266a77aa9e..f5bc69308ea24 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -224,6 +224,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_AMDGPU_LINUX_DEVICE_CLASS + AC_AMDGPU_KVREALLOC AC_AMDGPU_DMA_BUF_IS_DYNAMIC AC_AMDGPU_RADIX_TREE_ITER_DELETE AC_AMDGPU_KFIFO_PUT diff --git a/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 b/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 index 07199f0827e93..98fd7ba684a15 100644 --- a/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 @@ -17,3 +17,37 @@ AC_DEFUN([AC_AMDGPU_KREALLOC_ARRAY], [ ]) ]) +dnl # +dnl #v6.11-rc6-3-g590b9d576cae mm: kvmalloc: align kvrealloc() with krealloc() +dnl #v6.9-rc4-85-g7bd230a26648 mm/slab: enable slab allocation tagging for kmalloc and friends +dnl #v5.15-11-g8587ca6f3415 mm: move kvmalloc-related functions to slab.h +dnl #v5.14-rc4-23-gde2860f46362 mm: Add kvrealloc() +dnl # +AC_DEFUN([AC_AMDGPU_KVREALLOC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + #include + ], [ + void *p = NULL; + p = kvrealloc(NULL, 0, GFP_KERNEL); + ], [ + AC_DEFINE(HAVE_KVREALLOC_3ARG, 1, [kvrealloc() has 3 arguments]) + ],[ + AC_KERNEL_TRY_COMPILE([ + #include + #include + #include + ], [ + void *p = NULL; + p = kvrealloc(NULL, 0, 0, GFP_KERNEL); + ], [ + AC_DEFINE(HAVE_KVREALLOC_4ARG, 1, [kvrealloc() has 4 arguments]) + ],[ + AC_DEFINE(HAVE_NO_KVREALLOC, 1, [kvrealloc() isn't available]) + ]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 6044697f8ac62..d9c0043de57cc 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -106,3 +106,13 @@ if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then sed -i 's|\(CFLAGS_[A-Z_]*\)$(AMDDALPATH)/.*/\(.*\.o\)|\1\2|' $file done fi + +# v6.11-rc6-3-g590b9d576cae mm: kvmalloc: align kvrealloc() with krealloc() +# Hardcoded modification for `drm_exec.c` to adapt `kvrealloc` function usage to four arguments. +# WARNING: Do NOT optimize this section. The change is essential to guarantee that if there are +# any semantic changes to 'size', it will trigger a DKMS installation failure. +# This ensures any changes to 'size' usage must be manually reviewed and addressed in this context. +if ! grep -q 'define HAVE_KVREALLOC_3ARG ' $SRC/config/config.h; then + sed -i -e 's/kvrealloc(exec->objects, size + PAGE_SIZE, GFP_KERNEL)/kvrealloc(exec->objects, size, size + PAGE_SIZE, GFP_KERNEL)/' \ + drm_exec.c +fi diff --git a/include/kcl/kcl_memory.h b/include/kcl/kcl_memory.h index e0dac3be04b47..aeebb157b0d57 100644 --- a/include/kcl/kcl_memory.h +++ b/include/kcl/kcl_memory.h @@ -58,4 +58,8 @@ vm_fault_t vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, } #endif /* HAVE_VMF_INSERT_PFN_PROT */ +#ifdef HAVE_NO_KVREALLOC +void *kvrealloc(const void *p, size_t oldsize, size_t newsize, gfp_t flags); +#endif + #endif From 780638f53d2630230d909cdc8c0ae8aaf2d6f7fc Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 25 Mar 2025 16:16:25 +0800 Subject: [PATCH 1474/2653] drm/amdkcl: wrap code under amdkcl_gem_resvp Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile.drm_exec | 3 ++- drivers/gpu/drm/amd/dkms/backport_drm_exec.h | 10 +++++++++ drivers/gpu/drm/drm_exec.c | 22 ++++++++++++-------- 3 files changed, 25 insertions(+), 10 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/backport_drm_exec.h diff --git a/drivers/gpu/drm/amd/dkms/Makefile.drm_exec b/drivers/gpu/drm/amd/dkms/Makefile.drm_exec index 3c01e88c56700..2177496115aa2 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile.drm_exec +++ b/drivers/gpu/drm/amd/dkms/Makefile.drm_exec @@ -1,6 +1,7 @@ export CONFIG_DRM_EXEC=m subdir-ccflags-y += -DCONFIG_DRM_EXEC -CFLAGS_drm_exec.o += -include linux/module.h -DHAVE_CONFIG_H +CFLAGS_drm_exec.o += -include $(src)/amd/dkms/backport_drm_exec.h \ + -include linux/module.h -DHAVE_CONFIG_H amddrm_exec-y := drm_exec.o obj-$(CONFIG_DRM_EXEC) += amddrm_exec.o diff --git a/drivers/gpu/drm/amd/dkms/backport_drm_exec.h b/drivers/gpu/drm/amd/dkms/backport_drm_exec.h new file mode 100644 index 0000000000000..3051f5460bd8c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/backport_drm_exec.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_BACKPORT_DRM_EXEC_H +#define _KCL_BACKPORT_DRM_EXEC_H + +#include +#include +#include +#include + +#endif diff --git a/drivers/gpu/drm/drm_exec.c b/drivers/gpu/drm/drm_exec.c index 8d06014001828..1f485faeb69ac 100644 --- a/drivers/gpu/drm/drm_exec.c +++ b/drivers/gpu/drm/drm_exec.c @@ -6,6 +6,10 @@ #include #include +#ifndef amdkcl_gem_resvp +#define amdkcl_gem_resvp(obj) ((obj)->resv) +#endif + /** * DOC: Overview * @@ -59,7 +63,7 @@ static void drm_exec_unlock_all(struct drm_exec *exec) unsigned long index; drm_exec_for_each_locked_object_reverse(exec, index, obj) { - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); drm_gem_object_put(obj); } @@ -172,12 +176,12 @@ static int drm_exec_lock_contended(struct drm_exec *exec) /* Always cleanup the contention so that error handling can kick in */ exec->contended = NULL; if (exec->flags & DRM_EXEC_INTERRUPTIBLE_WAIT) { - ret = dma_resv_lock_slow_interruptible(obj->resv, + ret = dma_resv_lock_slow_interruptible(amdkcl_gem_resvp(obj), &exec->ticket); if (unlikely(ret)) goto error_dropref; } else { - dma_resv_lock_slow(obj->resv, &exec->ticket); + dma_resv_lock_slow(amdkcl_gem_resvp(obj), &exec->ticket); } ret = drm_exec_obj_locked(exec, obj); @@ -188,7 +192,7 @@ static int drm_exec_lock_contended(struct drm_exec *exec) return 0; error_unlock: - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); error_dropref: drm_gem_object_put(obj); @@ -221,9 +225,9 @@ int drm_exec_lock_obj(struct drm_exec *exec, struct drm_gem_object *obj) } if (exec->flags & DRM_EXEC_INTERRUPTIBLE_WAIT) - ret = dma_resv_lock_interruptible(obj->resv, &exec->ticket); + ret = dma_resv_lock_interruptible(amdkcl_gem_resvp(obj), &exec->ticket); else - ret = dma_resv_lock(obj->resv, &exec->ticket); + ret = dma_resv_lock(amdkcl_gem_resvp(obj), &exec->ticket); if (unlikely(ret == -EDEADLK)) { drm_gem_object_get(obj); @@ -245,7 +249,7 @@ int drm_exec_lock_obj(struct drm_exec *exec, struct drm_gem_object *obj) return 0; error_unlock: - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); return ret; } EXPORT_SYMBOL(drm_exec_lock_obj); @@ -265,7 +269,7 @@ void drm_exec_unlock_obj(struct drm_exec *exec, struct drm_gem_object *obj) for (i = exec->num_objects; i--;) { if (exec->objects[i] == obj) { - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); for (++i; i < exec->num_objects; ++i) exec->objects[i - 1] = exec->objects[i]; --exec->num_objects; @@ -297,7 +301,7 @@ int drm_exec_prepare_obj(struct drm_exec *exec, struct drm_gem_object *obj, if (ret) return ret; - ret = dma_resv_reserve_fences(obj->resv, num_fences); + ret = dma_resv_reserve_fences(amdkcl_gem_resvp(obj), num_fences); if (ret) { drm_exec_unlock_obj(exec, obj); return ret; From 2586f5363f0f8e564530b532aea44cb4595fa8c5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 25 Mar 2025 16:27:12 +0800 Subject: [PATCH 1475/2653] drm/amdkcl: add fake kvrealloc support for drm_exec Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/backport_drm_exec.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/backport_drm_exec.h b/drivers/gpu/drm/amd/dkms/backport_drm_exec.h index 3051f5460bd8c..9e2b544d7ef73 100644 --- a/drivers/gpu/drm/amd/dkms/backport_drm_exec.h +++ b/drivers/gpu/drm/amd/dkms/backport_drm_exec.h @@ -6,5 +6,6 @@ #include #include #include +#include #endif From 569719a9aa66c30a8bd6981f630983e37450adac Mon Sep 17 00:00:00 2001 From: Jay Cornwall Date: Thu, 27 Mar 2025 23:02:08 -0500 Subject: [PATCH 1476/2653] Revert "drm/amdgpu: Increase KIQ invalidate_tlbs timeout" This reverts commit fdb90033846e2f23dfaaa01dc47fec7b94704d0e. Reportedly causing unknown issue in memory management code: [ 128.047288] amdgpu 0000:65:00.0: amdgpu: Failed to map peer:0000:46:00.0 mem_domain:2 [...] [ 137.815340] WARNING: CPU: 81 PID: 1006 at drivers/gpu/drm/ttm/ttm_bo.c:613 ttm_bo_unpin+0x7e/0x90 [ttm] Signed-off-by: Jay Cornwall Reviewed-by: Kent Russell --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 16 ++++------------ 2 files changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 3194a9162f855..0a8b38c04f332 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -358,6 +358,7 @@ enum amdgpu_kiq_irq { AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, AMDGPU_CP_KIQ_IRQ_LAST }; +#define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ #define MAX_KIQ_REG_TRY 1000 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 97b562a79ea8e..38d5b0cd42285 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -715,10 +715,12 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, uint32_t flush_type, bool all_hub, uint32_t inst) { + u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : + adev->usec_timeout; struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring; struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; unsigned int ndw; - int r, cnt = 0; + int r; uint32_t seq; /* @@ -775,17 +777,7 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, amdgpu_ring_commit(ring); spin_unlock(&adev->gfx.kiq[inst].ring_lock); - - r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); - - might_sleep(); - while (r < 1 && cnt++ < MAX_KIQ_REG_TRY && - !amdgpu_reset_pending(adev->reset_domain)) { - msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); - r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); - } - - if (cnt > MAX_KIQ_REG_TRY) { + if (amdgpu_fence_wait_polling(ring, seq, usec_timeout) < 1) { dev_err(adev->dev, "timeout waiting for kiq fence\n"); r = -ETIME; } else From 5d92911b822d4af1b6123ecbec7fc1df40886589 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 2 Apr 2025 17:29:42 +0800 Subject: [PATCH 1477/2653] drm/amdkcl: use TTM reference for vm mapping for old OS It's caused by the following patches: v6.13-rc1-107-g39b1acfddfd5 drm/ttm: use GEM references for VM mappings v5.9-rc5-1077-gd693def4fd1c drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver Since drm_gem_object.funs is null in some old OS, drm_gem_object_put can not be used to to reference drm_gem_object and release it. Signed-off-by: Asher Song Reviewed-by: Bob Zhou --- drivers/gpu/drm/ttm/ttm_bo_vm.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index d96202a8bf56b..95b722824f265 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -64,13 +64,21 @@ static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, if (vmf->flags & FAULT_FLAG_RETRY_NOWAIT) return VM_FAULT_RETRY; +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK drm_gem_object_get(&bo->base); +#else + ttm_bo_get(bo); +#endif mmap_read_unlock(vma->vm_mm); (void)dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_KERNEL, true, MAX_SCHEDULE_TIMEOUT); dma_resv_unlock(amdkcl_ttm_resvp(bo)); +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK drm_gem_object_put(&bo->base); +#else + ttm_bo_put(bo); +#endif return VM_FAULT_RETRY; } @@ -137,12 +145,20 @@ vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, */ if (fault_flag_allow_retry_first(vmf->flags)) { if (!(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) { +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK drm_gem_object_get(&bo->base); +#else + ttm_bo_get(bo); +#endif mmap_read_unlock(vma->vm_mm); if (!dma_resv_lock_interruptible(amdkcl_ttm_resvp(bo), NULL)) dma_resv_unlock(amdkcl_ttm_resvp(bo)); +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK drm_gem_object_put(&bo->base); +#else + ttm_bo_put(bo); +#endif } return VM_FAULT_RETRY; @@ -374,7 +390,11 @@ void ttm_bo_vm_open(struct vm_area_struct *vma) WARN_ON(bo->bdev->dev_mapping != vma->vm_file->f_mapping); +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK drm_gem_object_get(&bo->base); +#else + ttm_bo_get(bo); +#endif } EXPORT_SYMBOL(ttm_bo_vm_open); @@ -382,7 +402,11 @@ void ttm_bo_vm_close(struct vm_area_struct *vma) { struct ttm_buffer_object *bo = vma->vm_private_data; +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK drm_gem_object_put(&bo->base); +#else + ttm_bo_put(bo); +#endif vma->vm_private_data = NULL; } EXPORT_SYMBOL(ttm_bo_vm_close); @@ -584,7 +608,11 @@ int ttm_bo_mmap_obj(struct vm_area_struct *vma, struct ttm_buffer_object *bo) if (is_cow_mapping(vma->vm_flags)) return -EINVAL; +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK drm_gem_object_get(&bo->base); +#else + ttm_bo_get(bo); +#endif /* * Drivers may want to override the vm_ops field. Otherwise we From fe62b20a4e840e93f673713bbc3c59dbca84f5d7 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 3 Apr 2025 14:32:27 +0800 Subject: [PATCH 1478/2653] drm/amdkcl: update kmod-amdgpu.spec to support extra amddrm_exec.ko Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec index 79795b24bb7c8..b071bb677652a 100644 --- a/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec +++ b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec @@ -32,7 +32,7 @@ popd %install mkdir -p %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu -%{__install} -D -t %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu src/amddrm_buddy.ko src/amddrm_ttm_helper.ko src/scheduler/amd-sched.ko src/ttm/amdttm.ko src/amd/amdxcp/amdxcp.ko src/amd/amdgpu/amdgpu.ko src/amd/amdkcl/amdkcl.ko +%{__install} -D -t %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu src/amddrm_buddy.ko src/amddrm_ttm_helper.ko src/scheduler/amd-sched.ko src/ttm/amdttm.ko src/amd/amdxcp/amdxcp.ko src/amd/amdgpu/amdgpu.ko src/amd/amdkcl/amdkcl.ko src/amddrm_exec.ko # Make .ko objects temporarily executable for automatic stripping find %{buildroot}/lib/modules -type f -name \*.ko -exec chmod u+x \{\} \+ @@ -59,6 +59,7 @@ if [ -x "/usr/sbin/weak-modules" ]; then printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_ttm_helper.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_exec.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules fi dracut -f --kver %{kernel}.%{_arch} @@ -70,6 +71,7 @@ echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_buddy. echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_ttm_helper.ko" >> /var/run/rpm-%{pkg}-modules.list echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko" >> /var/run/rpm-%{pkg}-modules.list echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_exec.ko" >> /var/run/rpm-%{pkg}-modules.list %postun depmod -a > /dev/null 2>&1 @@ -89,6 +91,7 @@ dracut -f --kver %{kernel}.%{_arch} /lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_ttm_helper.ko /lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko /lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_exec.ko %defattr(644,root,root,755) %license licenses %config(noreplace) %{_sysconfdir}/depmod.d/%{pkg}.conf From be3d1f8c9563bfe138d678a80952518305cfba87 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 31 Mar 2025 16:22:40 +0800 Subject: [PATCH 1479/2653] drm/amdkcl: fake COUNT_ARGS() and CONCATENATE() macro definition It's caused by the commit:bdbabfe4 "drm/amdgpu: Replace deprecated function strcpy() with strscpy()" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 ++++ include/kcl/header/linux/args.h | 12 ++++++++++ include/kcl/kcl_args.h | 25 ++++++++++++++++++++ 4 files changed, 45 insertions(+) create mode 100644 include/kcl/header/linux/args.h create mode 100644 include/kcl/kcl_args.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 50a7118a08a5f..f286f77214ab2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -847,6 +847,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_APPLE_GMUX_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_ARGS_H 1 + /* atomic_long_try_cmpxchg() is available */ #define HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 303ac32f4e8e5..3c103aabdb1bc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -164,4 +164,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #locking: Introduce __cleanup() based infrastructure dnl AC_KERNEL_CHECK_HEADERS([linux/cleanup.h]) + + dnl #v6.5-rc4-31-gb229baa374db + dnl #kernel.h: split out COUNT_ARGS() and CONCATENATE() to args.h + dnl + AC_KERNEL_CHECK_HEADERS([linux/args.h]) ]) diff --git a/include/kcl/header/linux/args.h b/include/kcl/header/linux/args.h new file mode 100644 index 0000000000000..b0dc14d7351c2 --- /dev/null +++ b/include/kcl/header/linux/args.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_ARGS_H +#define _KCL_HEADER_LINUX_ARGS_H + +#ifdef HAVE_LINUX_ARGS_H +#include_next +#else +#include +#endif + +#endif + diff --git a/include/kcl/kcl_args.h b/include/kcl/kcl_args.h new file mode 100644 index 0000000000000..33ec593ff9b75 --- /dev/null +++ b/include/kcl/kcl_args.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _KCL_KCL_ARGS_H +#define _KCL_KCL_ARGS_H + +#include + +#ifndef __COUNT_ARGS +#define __COUNT_ARGS(_0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _n, X...) _n +#endif + +#ifndef COUNT_ARGS +#define COUNT_ARGS(X...) __COUNT_ARGS(, ##X, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) +#endif + +/* Concatenate two parameters, but allow them to be expanded beforehand. */ +#ifndef __CONCAT +#define __CONCAT(a, b) a ## b +#endif + +#ifndef CONCATENATE +#define CONCATENATE(a, b) __CONCAT(a, b) +#endif + +#endif /* _KCL_KCL_ARGS_H */ From 2097bd1150660fe572ba68098a2c853404daf0f4 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 31 Mar 2025 16:48:19 +0800 Subject: [PATCH 1480/2653] drm/amdkcl: fake the __annotated macro defintion It's caused by the commit:bdbabfe4 "drm/amdgpu: Replace deprecated function strcpy() with strscpy()" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 ++++ include/kcl/header/linux/compiler_types.h | 10 ++++++++ include/kcl/kcl_compiler_types.h | 24 ++++++++++++++++++++ 4 files changed, 42 insertions(+) create mode 100644 include/kcl/header/linux/compiler_types.h create mode 100644 include/kcl/kcl_compiler_types.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f286f77214ab2..13f07672984d5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -871,6 +871,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_COMPILER_ATTRIBUTES_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_COMPILER_TYPES_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_CONTAINER_OF_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 3c103aabdb1bc..7b6f715c04fa8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -169,4 +169,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #kernel.h: split out COUNT_ARGS() and CONCATENATE() to args.h dnl AC_KERNEL_CHECK_HEADERS([linux/args.h]) + + dnl #v4.14-rc6-20-gd15155824c50 + dnl #linux/compiler.h: Split into compiler.h and compiler_types.h + dnl + AC_KERNEL_CHECK_HEADERS([linux/compiler_types.h]) ]) diff --git a/include/kcl/header/linux/compiler_types.h b/include/kcl/header/linux/compiler_types.h new file mode 100644 index 0000000000000..a7e97e404c9e7 --- /dev/null +++ b/include/kcl/header/linux/compiler_types.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_COMPILER_TYPES_H +#define _KCL_HEADER_LINUX_COMPILER_TYPES_H + +#ifdef HAVE_LINUX_COMPILER_TYPES_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_compiler_types.h b/include/kcl/kcl_compiler_types.h new file mode 100644 index 0000000000000..09f2b603b68dd --- /dev/null +++ b/include/kcl/kcl_compiler_types.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_COMPILER_TYPES_H +#define _KCL_KCL_COMPILER_TYPES_H + +#include + +/* + * __has_builtin is supported on gcc >= 10, clang >= 3 and icc >= 21. + * In the meantime, to support gcc < 10, we implement __has_builtin + * by hand. + */ +#ifndef __has_builtin +#define __has_builtin(x) (0) +#endif + +#ifndef __annotated +#if __has_builtin(__builtin_has_attribute) +#define __annotated(var, attr) __builtin_has_attribute(var, attr) +#else +#define __annotated(var, attr) (false) +#endif +#endif + +#endif /* _KCL_KCL_COMPILER_TYPES_H */ \ No newline at end of file From 7feee72e8bf59b249338c62ed4ad2b6d8aaf45c8 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 31 Mar 2025 17:12:48 +0800 Subject: [PATCH 1481/2653] drm/amdkcl: fake __must_be_cstr macro defintion It's caused by the commit:bdbabfe4 "drm/amdgpu: Replace deprecated function strcpy() with strscpy()" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ include/kcl/kcl_compiler.h | 12 ++++++++++++ 2 files changed, 15 insertions(+) create mode 100644 include/kcl/kcl_compiler.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 13f07672984d5..4415ce8ff9abb 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -868,6 +868,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_CLEANUP_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_COMPILER_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_COMPILER_ATTRIBUTES_H 1 diff --git a/include/kcl/kcl_compiler.h b/include/kcl/kcl_compiler.h new file mode 100644 index 0000000000000..9fa1e4ff5d81a --- /dev/null +++ b/include/kcl/kcl_compiler.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_COMPILER_H +#define _KCL_KCL_COMPILER_H + +#include +#include + +#ifndef __must_be_cstr +#define __must_be_cstr(p) BUILD_BUG_ON_ZERO(__annotated(p, nonstring)) +#endif + +#endif /* _KCL_KCL_COMPILER_H */ \ No newline at end of file From bda5508510111c28eeb13d124bb8ad82e96e1fc4 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 31 Mar 2025 16:53:14 +0800 Subject: [PATCH 1482/2653] drm/amdkcl: drm/amdkcl: check whether strscpy allow 2 argument It's caused by the commit:bdbabfe4 "drm/amdgpu: Replace deprecated function strcpy() with strscpy()" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 ++- drivers/gpu/drm/amd/dkms/m4/strscpy.m4 | 18 ++++++++++++++++ include/kcl/kcl_string.h | 26 ++++++++++++++++++++++++ 5 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/strscpy.m4 create mode 100644 include/kcl/kcl_string.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index f1bea2e997789..0b37174366c7c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -144,4 +144,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4415ce8ff9abb..0b06dcd687ba0 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1090,6 +1090,9 @@ /* enum SMCA_UMC_V2 is available */ #define HAVE_SMCA_UMC_V2 1 +/* strscpy() allows two arguments */ +#define HAVE_STRSCPY_ALLOW_TWO_ARGUMENTS 1 + /* struct dma_buf_attach_ops->allow_peer2peer is available */ #define HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f5bc69308ea24..f0866fa7162a0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -268,7 +268,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MODULE_IMPORT_NS AC_AMDGPU_DRM_DEV_WEDGED_EVENT AC_AMDGPU_DRM_DRIVER_DATE - + AC_AMDGPU_STRSCPY_ALLOW_TWO_ARGUMENTS + AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" diff --git a/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 b/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 new file mode 100644 index 0000000000000..f3044c21f6b68 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v6.8-rc2-15-ge6584c3964f2 +dnl # string: Allow 2-argument strscpy() +dnl # +AC_DEFUN([AC_AMDGPU_STRSCPY_ALLOW_TWO_ARGUMENTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + char name[8]; + strscpy(name, "foo"); + ],[ + AC_DEFINE(HAVE_STRSCPY_ALLOW_TWO_ARGUMENTS, 1, + [strscpy() allows two arguments]) + ]) + ]) +]) diff --git a/include/kcl/kcl_string.h b/include/kcl/kcl_string.h new file mode 100644 index 0000000000000..bda61d800bf1f --- /dev/null +++ b/include/kcl/kcl_string.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_STRING_H +#define _KCL_KCL_STRING_H + +#include +#include +#include + +#ifndef HAVE_STRSCPY_ALLOW_TWO_ARGUMENTS +extern ssize_t real_kcl_strscpy(char *, const char *, size_t) __asm__("strscpy"); + +/* + * The 2 argument style can only be used when dst is an array with a + * known size. + */ +#define kcl_strscpy0(dst, src, ...) \ + real_kcl_strscpy(dst, src, sizeof(dst) + __must_be_array(dst) + \ + __must_be_cstr(dst) + __must_be_cstr(src)) +#define kcl_strscpy1(dst, src, size) \ + real_kcl_strscpy(dst, src, size + __must_be_cstr(dst) + __must_be_cstr(src)) + +#define strscpy(dst, src, ...) \ + CONCATENATE(kcl_strscpy, COUNT_ARGS(__VA_ARGS__))(dst, src, __VA_ARGS__) +#endif + +#endif /* _KCL_KCL_STRING_H */ From 5546d20c682b25c1a498f57c9465153bfd93e142 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 1 Apr 2025 16:03:17 +0800 Subject: [PATCH 1483/2653] drm/amdkcl: Use drm_gem_object_put_unlocked to avoid warnings on RHEL 7.9 Replace drm_gem_object_put with drm_gem_object_put_unlocked to prevent warnings on RHEL 7.9. Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/backport_drm_exec.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/backport_drm_exec.h b/drivers/gpu/drm/amd/dkms/backport_drm_exec.h index 9e2b544d7ef73..5a0c2434244c8 100644 --- a/drivers/gpu/drm/amd/dkms/backport_drm_exec.h +++ b/drivers/gpu/drm/amd/dkms/backport_drm_exec.h @@ -6,6 +6,7 @@ #include #include #include +#include #include #endif From bb42bfb556e0d10da309100894558628e554b0b0 Mon Sep 17 00:00:00 2001 From: chengjya Date: Wed, 9 Apr 2025 12:10:44 +0800 Subject: [PATCH 1484/2653] drm/amdkcl: wrap code under the HAVE_PM_SUSPEND_TARGET_STATE It's caused by the commit: fe01a75b042f "drm/amd: Forbid suspending into non-default suspend states" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 705eff360f64a..2cce5033d1942 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2661,6 +2661,7 @@ static int amdgpu_pmops_suspend(struct device *dev) else if (amdgpu_acpi_is_s3_active(adev)) adev->in_s3 = true; if (!adev->in_s0ix && !adev->in_s3) { +#ifdef HAVE_PM_SUSPEND_TARGET_STATE /* don't allow going deep first time followed by s2idle the next time */ if (adev->last_suspend_state != PM_SUSPEND_ON && adev->last_suspend_state != pm_suspend_target_state) { @@ -2668,11 +2669,14 @@ static int amdgpu_pmops_suspend(struct device *dev) pm_suspend_target_state); return -EINVAL; } +#endif return 0; } +#ifdef HAVE_PM_SUSPEND_TARGET_STATE /* cache the state last used for suspend */ adev->last_suspend_state = pm_suspend_target_state; +#endif return amdgpu_device_suspend(drm_dev, true); } From 3d185ba6f02f8bfeee1c9b89e09aee2512cbb23d Mon Sep 17 00:00:00 2001 From: chengjya Date: Wed, 9 Apr 2025 12:14:57 +0800 Subject: [PATCH 1485/2653] drm/amdkcl: fake the macro defintion drm_err_once It's caused by the commit: fe01a75b042f "drm/amd: Forbid suspending into non-default suspend states" Signed-off-by: chengjya Reviewed-by: Bob Zhou --- include/kcl/kcl_drm_print.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index a4e435d18106e..f650bc4988a84 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -108,6 +108,11 @@ void kcl_drm_err(const char *format, ...); dev_warn_once((drm)->dev, "[drm] " fmt, ##__VA_ARGS__) #endif /* drm_warn_once */ +#ifndef drm_err_once +#define drm_err_once(drm, fmt, ...) \ + __drm_printk((drm), err, _once, "*ERROR* " fmt, ##__VA_ARGS__) +#endif + #if !defined(DRM_UT_VBL) #define DRM_UT_VBL 0x20 #endif From 38150d2048ea72f2060ff0b1d6684ceeb39e46b7 Mon Sep 17 00:00:00 2001 From: chengjya Date: Tue, 1 Apr 2025 11:19:29 +0800 Subject: [PATCH 1486/2653] drm/amdkcl: fake __RENAME macro defintion Signed-off-by: chengjya Reviewed-by: Bob Zhou --- include/kcl/kcl_fortify_string.h | 10 ++++++++++ include/kcl/kcl_string.h | 3 ++- 2 files changed, 12 insertions(+), 1 deletion(-) create mode 100644 include/kcl/kcl_fortify_string.h diff --git a/include/kcl/kcl_fortify_string.h b/include/kcl/kcl_fortify_string.h new file mode 100644 index 0000000000000..9dc5b48ee77b9 --- /dev/null +++ b/include/kcl/kcl_fortify_string.h @@ -0,0 +1,10 @@ +#ifndef _KCL_KCL_FORTIFY_STRING_H_ +#define _KCL_KCL_FORTIFY_STRING_H_ + +#include + +#ifndef __RENAME +#define __RENAME(x) __asm__(#x) +#endif + +#endif /* _KCL_KCL_FORTIFY_STRING_H_ */ \ No newline at end of file diff --git a/include/kcl/kcl_string.h b/include/kcl/kcl_string.h index bda61d800bf1f..cb4416f1f99a9 100644 --- a/include/kcl/kcl_string.h +++ b/include/kcl/kcl_string.h @@ -3,11 +3,12 @@ #define _KCL_KCL_STRING_H #include +#include #include #include #ifndef HAVE_STRSCPY_ALLOW_TWO_ARGUMENTS -extern ssize_t real_kcl_strscpy(char *, const char *, size_t) __asm__("strscpy"); +extern ssize_t real_kcl_strscpy(char *, const char *, size_t) __RENAME(strscpy); /* * The 2 argument style can only be used when dst is an array with a From 5f31040eb1c9017096a716f688fe47b4097ecd33 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 10 Apr 2025 11:24:57 +0800 Subject: [PATCH 1487/2653] drm/amdkcl: fake macro VFM_MODEL It's caused by the commit:f4f55ab3 "drm/amd/amdgpu: disable ASPM in some situations" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_cpu_device_id.h | 27 +++++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 include/kcl/kcl_cpu_device_id.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 0b37174366c7c..90b263e1f827d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -145,4 +145,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_cpu_device_id.h b/include/kcl/kcl_cpu_device_id.h new file mode 100644 index 0000000000000..e08314fb54b9f --- /dev/null +++ b/include/kcl/kcl_cpu_device_id.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_CPU_DEVICE_ID_H +#define AMDKCL_CPU_DEVICE_ID_H + +#ifdef CONFIG_X86 + +#include +/* Copied froma arch/x86/include/asm/cpu_device_id.h*/ +#ifndef VFM_MODEL +#define VFM_MODEL_BIT 0 +#define VFM_FAMILY_BIT 8 +#define VFM_VENDOR_BIT 16 + +#define VFM_MODEL_MASK GENMASK(VFM_FAMILY_BIT - 1, VFM_MODEL_BIT) + +#define VFM_MODEL(vfm) (((vfm) & VFM_MODEL_MASK) >> VFM_MODEL_BIT) + +#define VFM_MAKE(_vendor, _family, _model) ( \ + ((_model) << VFM_MODEL_BIT) | \ + ((_family) << VFM_FAMILY_BIT) | \ + ((_vendor) << VFM_VENDOR_BIT) \ +) + +#endif + +#endif /* CONFIG_X86 */ +#endif From 4c08eae15021e60a352dd4ef261f16dbb747b103 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 10 Apr 2025 11:18:03 +0800 Subject: [PATCH 1488/2653] drm/amdkcl: fake macro INTEL_ALDERLAKE & INTEL_ROCKETLAKE It's caused by the commit:f4f55ab3 "drm/amd/amdgpu: disable ASPM in some situations" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- include/kcl/kcl_intel_family.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/kcl/kcl_intel_family.h b/include/kcl/kcl_intel_family.h index 90793a772861b..bc2516933d89c 100644 --- a/include/kcl/kcl_intel_family.h +++ b/include/kcl/kcl_intel_family.h @@ -5,6 +5,7 @@ #ifdef CONFIG_X86 #include +#include /* Copied froma asm/intel-family.h*/ #ifndef INTEL_FAM6_ROCKETLAKE #define INTEL_FAM6_ROCKETLAKE 0xA7 @@ -14,5 +15,20 @@ #define INTEL_FAM6_ALDERLAKE 0x97 /* Golden Cove / Gracemont */ #endif +#ifndef IFM +#define IFM(_fam, _model) VFM_MAKE(X86_VENDOR_INTEL, _fam, _model) +#endif + +#ifndef INTEL_ALDERLAKE +#define INTEL_ALDERLAKE IFM(6, 0x97) /* Golden Cove / Gracemont */ +#define INTEL_ALDERLAKE_L IFM(6, 0x9A) /* Golden Cove / Gracemont */ +#endif + +#ifndef INTEL_ROCKETLAKE +#define INTEL_RAPTORLAKE IFM(6, 0xB7) /* Raptor Cove / Enhanced Gracemont */ +#define INTEL_RAPTORLAKE_P IFM(6, 0xBA) +#define INTEL_RAPTORLAKE_S IFM(6, 0xBF) +#endif + #endif /* CONFIG_X86 */ #endif From 0ac6819284dfb9230182e593aac264b4adbc7f92 Mon Sep 17 00:00:00 2001 From: Ce Sun Date: Tue, 15 Apr 2025 11:14:15 +0800 Subject: [PATCH 1489/2653] drm/amdgpu: skip execution of already queued recovery jobs skip execution of already queued recovery jobs, if the device is already reset. [ 241.356426] BUG: unable to handle page fault for address: 000000001de37ef8 [ 241.364167] #PF: supervisor read access in kernel mode [ 241.369948] #PF: error_code(0x0000) - not-present page [ 241.375716] PGD 0 [ 241.377988] Oops: 0000 [#1] SMP NOPTI [ 241.382115] CPU: 19 PID: 1669 Comm: kworker/u448:1 Tainted: G OE 5.15.0-70-generic #77-Ubuntu [ 241.393066] Hardware name: Microsoft C278A/C278A, BIOS C2789.5.BS.1C23.AG.2 11/21/2024 [ 241.401953] Workqueue: amdgpu-reset-hive amdgpu_amdkfd_reset_work [amdgpu] [ 241.410280] RIP: 0010:amdgpu_reset_perform_reset+0x1d/0x70 [amdgpu] [ 241.417639] Code: f0 66 66 2e 0f 1f 84 00 00 00 00 00 90 0f 1f 44 00 00 55 48 89 e5 41 55 41 54 53 48 89 fb 48 8b bf 28 4f 05 00 48 85 ff 74 49 <48> 8b 47 58 49 89 f4 ff d0 0f 1f 00 49 89 c5 48 85 c0 74 35 48 8b [ 241.438732] RSP: 0018:ffa000001de37d40 EFLAGS: 00010206 [ 241.444598] RAX: ffa000001de37dd0 RBX: ffa000001dde2f68 RCX: ffa000001de37dd0 [ 241.452599] RDX: ff11000118aadf40 RSI: ffa000001de37e20 RDI: 000000001de37ea0 [ 241.460610] RBP: ffa000001de37d58 R08: 0000000000000003 R09: ffffffffffe6b508 [ 241.468621] R10: ffffffffffffffff R11: 0000000000000001 R12: ffa000001dde2f68 [ 241.476631] R13: ffa000001de37e20 R14: ff11000121800000 R15: ff11000100049400 [ 241.484634] FS: 0000000000000000(0000) GS:ff11007e7e8c0000(0000) knlGS:0000000000000000 [ 241.493730] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 241.500182] CR2: 000000001de37ef8 CR3: 0000000006810004 CR4: 0000000000771ee0 [ 241.508193] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 241.516202] DR3: 0000000000000000 DR6: 00000000fffe07f0 DR7: 0000000000000400 [ 241.524210] PKRU: 55555554 [ 241.527248] Call Trace: [ 241.529994] [ 241.532351] amdgpu_do_asic_reset+0x2b/0x190 [amdgpu] [ 241.538253] amdgpu_device_gpu_recover.cold+0x532/0xd92 [amdgpu] [ 241.545431] ? ttwu_queue_wakelist+0x131/0x1c0 [ 241.550437] amdgpu_amdkfd_reset_work+0x6f/0x90 [amdgpu] [ 241.556737] process_one_work+0x228/0x3d0 [ 241.561254] worker_thread+0x53/0x420 [ 241.565366] ? process_one_work+0x3d0/0x3d0 [ 241.570061] kthread+0x127/0x150 [ 241.573700] ? set_kthread_struct+0x50/0x50 [ 241.578404] ret_from_fork+0x1f/0x30 [ 241.582434] Fixes 76e3985a6c62("drm/amdgpu: refactor amdgpu_device_gpu_recover") Signed-off-by: Ce Sun Reviewed-by: Chengjun Yao --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 0c4c9855db58e..3ee8f1824c5aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6187,9 +6187,6 @@ static int amdgpu_device_recovery_prepare(struct amdgpu_device *adev, struct amdgpu_device *tmp_adev = NULL; int r; - if (amdgpu_reset_domain_in_drain_mode(adev->reset_domain)) - return 0; - /* * Build list of devices to reset. * In case we are in XGMI hive mode, resort the device list @@ -6466,6 +6463,9 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, int r = 0; bool need_emergency_restart = false; + if (amdgpu_reset_domain_in_drain_mode(adev->reset_domain)) + return 0; + /* * If it reaches here because of hang/timeout and a RAS error is * detected at the same time, let RAS recovery take care of it. From c262f74dc7bc37731aa99f9a465a27cf062e7bb7 Mon Sep 17 00:00:00 2001 From: Shane Xiao Date: Wed, 16 Apr 2025 16:39:26 +0800 Subject: [PATCH 1490/2653] drm/amdkfd: Ignore userptr bad address error in non-HMM path The userptr can be unmapped by app and still registered to driver. Pretend the -EFAULT bad address error as succeed without HMM support. If GPU tries to access it, it will fail with a VM fault. This patch specifically addresses the restore userptr stage from MMU notifier and corrects the non-HMM code path on DKMS branch. v2: Update the commit description (Felix) Signed-off-by: Shane Xiao Reviewed-by: Philip Yang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 75ac800a4a443..672ba6e251472 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2935,13 +2935,19 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages, NULL); if (ret) { mem->user_pages[0] = NULL; - pr_info("%s: Failed to get user pages: %d\n", + pr_debug("%s: Failed to get user pages: %d\n", __func__, ret); /* Pretend it succeeded. It will fail later * with a VM fault if the GPU tries to access * it. Better than hanging indefinitely with * stalled user mode queues. + * + * Return other error -EBUSY or -ENOMEM to retry restore */ + if (ret != -EFAULT) + return ret; + + ret = 0; } #endif mutex_lock(&process_info->notifier_lock); From 49fb4618c255f2b9d5a2fadcc96b1fc486d37bf0 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 21 Apr 2025 10:14:48 +0800 Subject: [PATCH 1491/2653] drm/amdkcl: update CPP variable for autoconf Autoconf will detect the CPP variale to handle AC_CHECK_HEADERS, so update it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index 4eb72d9844e0e..486bb816b43df 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -6,6 +6,7 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ _conftest_cmd=$(head -1 .conftest.o.cmd) CC=$(echo $_conftest_cmd | awk -F ' ' '{print $[3]}') + CPP="$CC -E" CFLAGS=$(echo $_conftest_cmd | \ cut -d ' ' -f 4- | \ @@ -27,6 +28,7 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ sed -e "s|nostdinc|nostdinc -I../tiny_wrapper/include|") AC_SUBST(CC) + AC_SUBST(CPP) AC_SUBST(CFLAGS) AC_SUBST(CPPFLAGS) ], [ From 5abbbb93bbf212eb97f69b5d647d9fca45641cc2 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 2 Apr 2025 13:33:43 +0800 Subject: [PATCH 1492/2653] drm/amdkcl: fix autoconf missing llvm series tool Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 3 +-- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- drivers/gpu/drm/amd/dkms/pre-build.sh | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 5f9b0ca95f2fd..9f4c9c123ccf8 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -34,9 +34,8 @@ endif ifneq ($(CONFIG_CC_IS_CLANG),) CC := clang module_build_flags += CC=clang -endif -ifneq ($(CONFIG_LD_IS_LLD),) module_build_flags += LD=ld.lld +module_build_flags += LLVM=1 endif dkms-config ?= amd/dkms/dkms-config.mk diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f0866fa7162a0..891e94c6ce9a0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -479,7 +479,7 @@ AC_DEFUN([AC_KERNEL_COMPILE_MODULE_IFELSE], [ kbuild_cc='' if test -s ${LINUX_OBJ}/.config; then if grep -q 'CONFIG_CC_IS_CLANG=y' "${LINUX_OBJ}/.config"; then - kbuild_cc='CC=clang' + kbuild_cc='CC=clang LD=ld.lld LLVM=1' fi fi test "x$enable_linux_builtin" = xyes && kbuild_src_flag='KBUILD_SRC=' # override KBUILD_SRC diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index d9c0043de57cc..ec589e5ad3d2b 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -97,7 +97,7 @@ echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env # otherwise conflicting package libpam-tmpdir incorrectly generates config unset TMPDIR -(cd $SRC && ./configure) +(cd $SRC && ./configure CC=${CC}) # rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o # for kernel version < 5.3 From ff84587198a95bda7343d718d872872dde749a43 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 24 Apr 2025 12:27:39 +0800 Subject: [PATCH 1493/2653] drm/amdkcl: wrap code under HAVE_DRM_GEM_OBJECT_RESV It's caused by following commit b75818d0d2 "drm/amdgpu: add the evf attached gem obj resv dump" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 15fd25f943fcc..ad8d2986aaf7c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1711,9 +1711,9 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID); amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC); /* Add the gem obj resv fence dump*/ - if (dma_resv_trylock(bo->tbo.base.resv)) { - dma_resv_describe(bo->tbo.base.resv, m); - dma_resv_unlock(bo->tbo.base.resv); + if (dma_resv_trylock(amdkcl_ttm_resvp(&bo->tbo))) { + dma_resv_describe(amdkcl_ttm_resvp(&bo->tbo), m); + dma_resv_unlock(amdkcl_ttm_resvp(&bo->tbo)); } seq_puts(m, "\n"); From 33d937d768d9af952d3098bf701f81b2675d874a Mon Sep 17 00:00:00 2001 From: Yang Su Date: Sun, 27 Apr 2025 12:24:36 +0800 Subject: [PATCH 1494/2653] Revert "drm/amdgpu: Fail DMABUF map of XGMI-accessible memory" This reverts commit 90a5538e4619abc08ab0335d1c0dbc87cb21243e. The reverted patch causes a jira issue SWDEV-529564 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 3ea2a2d99c695..9a0bce3ba24c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -388,11 +388,6 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, break; case TTM_PL_VRAM: - /* XGMI-accessible memory should never be DMA-mapped */ - if (WARN_ON(amdgpu_dmabuf_is_xgmi_accessible( - dma_buf_attach_adev(attach), bo))) - return ERR_PTR(-EINVAL); - r = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, 0, bo->tbo.base.size, attach->dev, dir, &sgt); From 2a3dd833343174e0b05a35eb4a020815ef9b36c9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 29 Apr 2025 16:10:42 +0800 Subject: [PATCH 1495/2653] drm/amdkcl: detect clang tools for autoconf Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 9f4c9c123ccf8..987ac180e8fbd 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -32,6 +32,13 @@ $(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) endif ifneq ($(CONFIG_CC_IS_CLANG),) +ifeq ($(shell command -v clang > /dev/null && echo "y"),) +$(error "clang is not installed, exit...") +endif +ifeq ($(shell command -v ld.lld > /dev/null && echo "y"),) +$(error "ld.lld is not installed, exit...") +endif + CC := clang module_build_flags += CC=clang module_build_flags += LD=ld.lld From ab04eb0f9a23600c05866fc56f6c180affe1f61a Mon Sep 17 00:00:00 2001 From: Yang Su Date: Wed, 30 Apr 2025 13:46:31 +0800 Subject: [PATCH 1496/2653] drm/amdkcl: test whether dma_fence_array_first() exist It's caused by 96d61ad387 "drm/amdgpu: remove DRM_AMDGPU_NAVI3X_USERQ config for UQ" Signed-off-by: Yang Su --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- .../gpu/drm/amd/amdkcl/kcl_dma_fence_array.c | 44 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 2 + drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../drm/amd/dkms/m4/dma_fence_array_first.m4 | 16 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma_fence_array.h | 27 ++++++++++++ 7 files changed, 95 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_array.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma_fence_array_first.m4 create mode 100644 include/kcl/kcl_dma_fence_array.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index e3c88238151e9..6e54ac1b9e97c 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -16,7 +16,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ - kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o kcl_drm_drv.o + kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o kcl_drm_drv.o \ + kcl_dma_fence_array.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o kcl_debugfs_file.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_array.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_array.c new file mode 100644 index 0000000000000..f4b4040005a68 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_array.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * dma-fence-array: aggregate fences to be waited together + * + * Copyright (C) 2016 Collabora Ltd + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * Authors: + * Gustavo Padovan + * Christian König + */ + +#ifndef HAVE_DMA_FENCE_ARRAY_FIRST +#include + +struct dma_fence *kcl_dma_fence_array_first(struct dma_fence *head) +{ + struct dma_fence_array *array; + + if (!head) + return NULL; + + array = to_dma_fence_array(head); + if (!array) + return head; + + if (!array->num_fences) + return NULL; + + return array->fences[0]; +} +EXPORT_SYMBOL(kcl_dma_fence_array_first); + +struct dma_fence *kcl_dma_fence_array_next(struct dma_fence *head, + unsigned int index) +{ + struct dma_fence_array *array = to_dma_fence_array(head); + + if (!array || index >= array->num_fences) + return NULL; + + return array->fences[index]; +} +EXPORT_SYMBOL(kcl_dma_fence_array_next); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 90b263e1f827d..06dfcc812b016 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -146,4 +146,6 @@ #include #include #include +#include + #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0b06dcd687ba0..8ffa44755237e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -133,6 +133,9 @@ /* dma_buf->dynamic_mapping is not available */ /* #undef HAVE_DMA_BUF_OPS_LEGACY */ +/* dma_fence_array_first() is available */ +#define HAVE_DMA_FENCE_ARRAY_FIRST 1 + /* dma_fence_chain_alloc() is available */ #define HAVE_DMA_FENCE_CHAIN_ALLOC 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_fence_array_first.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_fence_array_first.m4 new file mode 100644 index 0000000000000..47bf06c5e0b65 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_fence_array_first.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.17-rc6-1495-gcaaf2ae712b7 +dnl # dma-buf: Add dma_fence_array_for_each (v2) +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_ARRAY_FIRST], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + dma_fence_array_first(NULL); + ], [dma_fence_array_first], [drivers/dma-buf/dma-fence-array.c],[ + AC_DEFINE(HAVE_DMA_FENCE_ARRAY_FIRST, 1, + [dma_fence_array_first() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 891e94c6ce9a0..10099dbe14276 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -269,6 +269,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEV_WEDGED_EVENT AC_AMDGPU_DRM_DRIVER_DATE AC_AMDGPU_STRSCPY_ALLOW_TWO_ARGUMENTS + AC_AMDGPU_DMA_FENCE_ARRAY_FIRST AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_dma_fence_array.h b/include/kcl/kcl_dma_fence_array.h new file mode 100644 index 0000000000000..242812385623f --- /dev/null +++ b/include/kcl/kcl_dma_fence_array.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * fence-array: aggregates fence to be waited together + * + * Copyright (C) 2016 Collabora Ltd + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * Authors: + * Gustavo Padovan + * Christian König + */ + +#ifndef __KCL_LINUX_DMA_FENCE_ARRAY_H +#define __KCL_LINUX_DMA_FENCE_ARRAY_H + +#ifndef HAVE_DMA_FENCE_ARRAY_FIRST +#include +#include + +struct dma_fence *kcl_dma_fence_array_first(struct dma_fence *head); +#define dma_fence_array_first kcl_dma_fence_array_first + +struct dma_fence *kcl_dma_fence_array_next(struct dma_fence *head, + unsigned int index); +#define dma_fence_array_next kcl_dma_fence_array_next + +#endif +#endif From 765ef0ca84c9704819ec522b5c32ca90be3f0086 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Wed, 30 Apr 2025 11:29:17 +0800 Subject: [PATCH 1497/2653] drm/amdkcl: fake the macro defintion dma_fence_unwrap_for_each It's caused by the commit: 96d61ad387ab8 "drm/amdgpu: remove DRM_AMDGPU_NAVI3X_USERQ config for UQ" Signed-off-by: Yang Su --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_dma_fence_unwrap.h | 95 +++++++++++++++++++++++++ 2 files changed, 96 insertions(+) create mode 100644 include/kcl/kcl_dma_fence_unwrap.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 06dfcc812b016..db5ca27543aa3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -147,5 +147,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_dma_fence_unwrap.h b/include/kcl/kcl_dma_fence_unwrap.h new file mode 100644 index 0000000000000..0269bd945071a --- /dev/null +++ b/include/kcl/kcl_dma_fence_unwrap.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2022 Advanced Micro Devices, Inc. + * Authors: + * Christian König + */ + +#ifndef __KCL_LINUX_DMA_FENCE_UNWRAP_H +#define __KCL_LINUX_DMA_FENCE_UNWRAP_H + +#include +#include + +#ifndef HAVE_LINUX_DMA_FENCE_UNWRAP_H +/** + * struct dma_fence_unwrap - cursor into the container structure + * + * Should be used with dma_fence_unwrap_for_each() iterator macro. + */ +struct dma_fence_unwrap { + /** + * @chain: potential dma_fence_chain, but can be other fence as well + */ + struct dma_fence *chain; + /** + * @array: potential dma_fence_array, but can be other fence as well + */ + struct dma_fence *array; + /** + * @index: last returned index if @array is really a dma_fence_array + */ + unsigned int index; +}; + +/* Internal helper to start new array iteration, don't use directly */ +static inline struct dma_fence * +kcl__dma_fence_unwrap_array(struct dma_fence_unwrap * cursor) +{ + cursor->array = dma_fence_chain_contained(cursor->chain); + cursor->index = 0; + return dma_fence_array_first(cursor->array); +} + +/** + * dma_fence_unwrap_first - return the first fence from fence containers + * @head: the entrypoint into the containers + * @cursor: current position inside the containers + * + * Unwraps potential dma_fence_chain/dma_fence_array containers and return the + * first fence. + */ +static inline struct dma_fence * +kcl_dma_fence_unwrap_first(struct dma_fence *head, struct dma_fence_unwrap *cursor) +{ + cursor->chain = dma_fence_get(head); + return kcl__dma_fence_unwrap_array(cursor); +} + +/** + * dma_fence_unwrap_next - return the next fence from a fence containers + * @cursor: current position inside the containers + * + * Continue unwrapping the dma_fence_chain/dma_fence_array containers and return + * the next fence from them. + */ +static inline struct dma_fence * +kcl_dma_fence_unwrap_next(struct dma_fence_unwrap *cursor) +{ + struct dma_fence *tmp; + + ++cursor->index; + tmp = dma_fence_array_next(cursor->array, cursor->index); + if (tmp) + return tmp; + + cursor->chain = dma_fence_chain_walk(cursor->chain); + return kcl__dma_fence_unwrap_array(cursor); +} + +/** + * dma_fence_unwrap_for_each - iterate over all fences in containers + * @fence: current fence + * @cursor: current position inside the containers + * @head: starting point for the iterator + * + * Unwrap dma_fence_chain and dma_fence_array containers and deep dive into all + * potential fences in them. If @head is just a normal fence only that one is + * returned. + */ +#define dma_fence_unwrap_for_each(fence, cursor, head) \ + for (fence = kcl_dma_fence_unwrap_first(head, cursor); fence; \ + fence = kcl_dma_fence_unwrap_next(cursor)) + +#endif +#endif From f3e029c139d6f7f23a45cf175f9589c81b307f04 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 13:07:48 +0800 Subject: [PATCH 1498/2653] drm/amdkcl: enable KCL macro for dma-resv.c In intree build, HAVE_DMA_FENCE_OPS_SET_DEADLINE KCL macro should be enabled for dma-resv.c. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/dma-buf/dma-resv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c index 2e78a095eaaf6..76bcda500be45 100644 --- a/drivers/dma-buf/dma-resv.c +++ b/drivers/dma-buf/dma-resv.c @@ -40,6 +40,9 @@ #include #include #include +#ifndef HAVE_CONFIG_H +#define HAVE_DMA_FENCE_OPS_SET_DEADLINE +#endif /** * DOC: Reservation Object Overview From 73f25bd7edc16bc39809049e1cbd09cbd7e7d2e0 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 14 May 2025 13:58:18 +0800 Subject: [PATCH 1499/2653] drm/amdkcl: Correct macro definition syntax Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h index 435dcf5ceea08..381da116a67ac 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h @@ -22,7 +22,7 @@ void _kcl_drm_print_memory_stats(struct drm_printer *p, const struct drm_memory_stats *stats, enum drm_gem_object_status supported_status, const char *region); -#define drm_print_memory_stats _kcl_drm_print_memory_stats; +#define drm_print_memory_stats _kcl_drm_print_memory_stats #endif #ifndef HAVE_DRM_MEMORY_STATS_IS_ZERO From 4182795b2728f79685ad5f5f736d8da759c56699 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 13 May 2025 16:55:57 +0800 Subject: [PATCH 1500/2653] drm/amdkcl: fix warning about panic_abo not used Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 2141622cb60f6..e84be362b6ae1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1853,12 +1853,12 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev) return 0; } +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER /* panic_bo is set in amdgpu_dm_plane_get_scanout_buffer() and only used in amdgpu_dm_set_pixel() * they are called from the panic handler, and protected by the drm_panic spinlock. */ static struct amdgpu_bo *panic_abo; -#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER /* Use the indirect MMIO to write each pixel to the GPU VRAM, * This is a simplified version of amdgpu_device_mm_access() */ From 83190bab79dd24b82975cc036c75f0482db7cd75 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 14 May 2025 10:28:59 +0800 Subject: [PATCH 1501/2653] drm/amdkcl: Standardize the use of HAVE_DRM_CLIENT_SETUP macro Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 2cce5033d1942..dc3e67067eb1c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2478,23 +2478,20 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, */ if (adev->mode_info.mode_config_initialized && !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { +#ifdef HAVE_DRM_CLIENT_SETUP const struct drm_format_info *format; /* select 8 bpp console on low vram cards */ if (adev->gmc.real_vram_size <= (32*1024*1024)) -#if HAVE_DRM_CLIENT_SETUP format = drm_format_info(DRM_FORMAT_C8); -#else - drm_fbdev_ttm_setup(adev_to_drm(adev), 8); -#endif else -#if HAVE_DRM_CLIENT_SETUP format = NULL; + drm_client_setup(adev_to_drm(adev), format); #else + if (adev->gmc.real_vram_size <= (32*1024*1024)) + drm_fbdev_ttm_setup(adev_to_drm(adev), 8); + else drm_fbdev_ttm_setup(adev_to_drm(adev), 32); -#endif -#if HAVE_DRM_CLIENT_SETUP - drm_client_setup(adev_to_drm(adev), format); #endif } From 0779571e036f3280f7a45c2d190d6a8a593ed289 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 14 May 2025 13:27:42 +0800 Subject: [PATCH 1502/2653] drm/amdkcl: Include for missing declaration Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c | 3 +-- include/kcl/kcl_kfifo.h | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c b/drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c index fad3a2306bdad..86e0115437fbc 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c @@ -1,9 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-or-later -#include +#include #ifndef HAVE_KFIFO_OUT_LINEAR - #define __KFIFO_PEEK(data, out, mask) \ ((data)[(out) & (mask)]) /* diff --git a/include/kcl/kcl_kfifo.h b/include/kcl/kcl_kfifo.h index 3be41b4d98708..5e4da40bb35ee 100644 --- a/include/kcl/kcl_kfifo.h +++ b/include/kcl/kcl_kfifo.h @@ -3,10 +3,9 @@ #ifndef KCL_LINUX_KFIFO_H #define KCL_LINUX_KFIFO_H -#ifndef HAVE_KFIFO_OUT_LINEAR - #include +#ifndef HAVE_KFIFO_OUT_LINEAR /** * commit 4edd7e96a1f159f43bd1cb82616f81eaddd54262 * Author: Jiri Slaby (SUSE) From c42c344ea9648ab7ea82d1845f84e5a1a8ba0976 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 10:43:20 +0800 Subject: [PATCH 1503/2653] drm/amdkcl: fix return void warning Signed-off-by: Bob Zhou Reviewed-by: Chengjun Yao --- include/kcl/backport/kcl_drm_fbdev_ttm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/backport/kcl_drm_fbdev_ttm.h b/include/kcl/backport/kcl_drm_fbdev_ttm.h index 5d504414c4478..a00b1a6a17a80 100644 --- a/include/kcl/backport/kcl_drm_fbdev_ttm.h +++ b/include/kcl/backport/kcl_drm_fbdev_ttm.h @@ -8,7 +8,7 @@ static inline void _kcl_drm_fbdev_ttm_setup(struct drm_device *dev, unsigned int preferred_bpp) { - return drm_fbdev_generic_setup(dev, preferred_bpp); + drm_fbdev_generic_setup(dev, preferred_bpp); } #define drm_fbdev_ttm_setup _kcl_drm_fbdev_ttm_setup #endif From 94883efa4511f96688beb1c000d774dd07d21626 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 10:07:05 +0800 Subject: [PATCH 1504/2653] drm/amdkcl: cleanup _kcl_drm_atomic_helper_resume These autoconf fake function always is used, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- .../backport/kcl_drm_atomic_helper_backport.h | 27 ------------------- 1 file changed, 27 deletions(-) diff --git a/include/kcl/backport/kcl_drm_atomic_helper_backport.h b/include/kcl/backport/kcl_drm_atomic_helper_backport.h index eaa2464b77353..44ea7b0f771d3 100644 --- a/include/kcl/backport/kcl_drm_atomic_helper_backport.h +++ b/include/kcl/backport/kcl_drm_atomic_helper_backport.h @@ -30,33 +30,6 @@ #include -/* - * commit v4.14-rc4-1-g78279127253a - * drm/atomic: Unref duplicated drm_atomic_state in drm_atomic_helper_resume() - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 15, 0) -static inline -int _kcl_drm_atomic_helper_resume(struct drm_device *dev, - struct drm_atomic_state *state) -{ - unsigned int prev, after; - int ret; - - prev = kref_read(&state->ref); - - drm_atomic_state_get(state); - ret = drm_atomic_helper_resume(dev, state); - - after = kref_read(&state->ref); - drm_atomic_state_put(state); - if (prev != after) - drm_atomic_state_put(state); - - return ret; -} -#define drm_atomic_helper_resume _kcl_drm_atomic_helper_resume -#endif - #ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET #define __drm_atomic_helper_plane_reset _kcl__drm_atomic_helper_plane_reset #endif /* AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET */ From 28e328fb044f672a75e496209403622f2f583fef Mon Sep 17 00:00:00 2001 From: Yang Su Date: Wed, 14 May 2025 17:37:13 +0800 Subject: [PATCH 1505/2653] drm/amdkcl: test whether dma_fence_dedup_array() exist It's caused by 554f79d8cf32cd7a3352b "dma-fence: Add helper to sort and deduplicate dma_fence arrays" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_dma_fence_unwrap.c | 64 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../drm/amd/dkms/m4/dma_fence_dedup_array.m4 | 16 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma_fence_unwrap.h | 9 ++- 6 files changed, 93 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_unwrap.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 6e54ac1b9e97c..4e6e016e577ff 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -17,7 +17,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o kcl_drm_drv.o \ - kcl_dma_fence_array.o + kcl_dma_fence_array.o kcl_dma_fence_unwrap.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o kcl_debugfs_file.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_unwrap.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_unwrap.c new file mode 100644 index 0000000000000..cb179499f98e9 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_unwrap.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2007 Jens Axboe + * + * Scatterlist handling helpers. + */ +#include +#include + +#ifndef HAVE_DMA_FENCE_DEDUP_ARRAY +static int fence_cmp(const void *_a, const void *_b) +{ + struct dma_fence *a = *(struct dma_fence **)_a; + struct dma_fence *b = *(struct dma_fence **)_b; + + if (a->context < b->context) + return -1; + else if (a->context > b->context) + return 1; + + if (dma_fence_is_later(b, a)) + return 1; + else if (dma_fence_is_later(a, b)) + return -1; + + return 0; +} + +/** + * dma_fence_dedup_array - Sort and deduplicate an array of dma_fence pointers + * @fences: Array of dma_fence pointers to be deduplicated + * @num_fences: Number of entries in the @fences array + * + * Sorts the input array by context, then removes duplicate + * fences with the same context, keeping only the most recent one. + * + * The array is modified in-place and unreferenced duplicate fences are released + * via dma_fence_put(). The function returns the new number of fences after + * deduplication. + * + * Return: Number of unique fences remaining in the array. + */ +int kcl_dma_fence_dedup_array(struct dma_fence **fences, int num_fences) +{ + int i, j; + + sort(fences, num_fences, sizeof(*fences), fence_cmp, NULL); + + /* + * Only keep the most recent fence for each context. + */ + j = 0; + for (i = 1; i < num_fences; i++) { + if (fences[i]->context == fences[j]->context) + dma_fence_put(fences[i]); + else + fences[++j] = fences[i]; + } + + return ++j; +} +EXPORT_SYMBOL_GPL(kcl_dma_fence_dedup_array); + +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8ffa44755237e..0b2efa3ca190a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -142,6 +142,9 @@ /* dma_fence_chain_contained() is available */ #define HAVE_DMA_FENCE_CHAIN_CONTAINED 1 +/* dma_fence_dedup_array() is available */ +#define HAVE_DMA_FENCE_DEDUP_ARRAY 1 + /* dma_fence_describe() is available */ #define HAVE_DMA_FENCE_DESCRIBE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 new file mode 100644 index 0000000000000..6d00ba9d43f37 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.14-1919-g554f79d8cf32 +dnl # dma-buf: Add dma_fence_dedup_array +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_DEDUP_ARRAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + dma_fence_dedup_array(NULL, 0); + ], [dma_fence_dedup_array], [drivers/dma-buf/dma-fence-unwrap.c],[ + AC_DEFINE(HAVE_DMA_FENCE_DEDUP_ARRAY, 1, + [dma_fence_dedup_array() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 10099dbe14276..6ed26cb091c13 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -270,6 +270,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRIVER_DATE AC_AMDGPU_STRSCPY_ALLOW_TWO_ARGUMENTS AC_AMDGPU_DMA_FENCE_ARRAY_FIRST + AC_AMDGPU_DMA_FENCE_DEDUP_ARRAY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_dma_fence_unwrap.h b/include/kcl/kcl_dma_fence_unwrap.h index 0269bd945071a..7c7cac6616168 100644 --- a/include/kcl/kcl_dma_fence_unwrap.h +++ b/include/kcl/kcl_dma_fence_unwrap.h @@ -8,7 +8,8 @@ #ifndef __KCL_LINUX_DMA_FENCE_UNWRAP_H #define __KCL_LINUX_DMA_FENCE_UNWRAP_H -#include +#include +#include #include #ifndef HAVE_LINUX_DMA_FENCE_UNWRAP_H @@ -92,4 +93,10 @@ kcl_dma_fence_unwrap_next(struct dma_fence_unwrap *cursor) fence = kcl_dma_fence_unwrap_next(cursor)) #endif + +#ifndef HAVE_DMA_FENCE_DEDUP_ARRAY +int kcl_dma_fence_dedup_array(struct dma_fence **array, int num_fences); + +#define dma_fence_dedup_array kcl_dma_fence_dedup_array +#endif #endif From e2b9cb13795e6a00e50b65da4d6ab98238322bef Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 09:50:15 +0800 Subject: [PATCH 1506/2653] drm/amdkcl: cleanup macro AMDKCL_FENCE_WAIT_ANY_TIMEOUT These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 79 +---------------------- include/kcl/backport/kcl_fence_backport.h | 8 --- include/kcl/kcl_fence.h | 11 ---- 3 files changed, 1 insertion(+), 97 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index e79e331222d00..49b98dd78dfa1 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -26,7 +26,7 @@ #include "kcl_fence_trace.h" /* Copied from drivers/dma-buf/dma-fence.c */ -#if defined(AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT) || defined(AMDKCL_FENCE_WAIT_ANY_TIMEOUT) +#if defined(AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT) static bool dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count, uint32_t *idx) @@ -124,83 +124,6 @@ _kcl_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) EXPORT_SYMBOL(_kcl_fence_default_wait); #endif - -/* - * Modifications [2017-09-19] (c) [2017] - * Advanced Micro Devices, Inc. - */ -#ifdef AMDKCL_FENCE_WAIT_ANY_TIMEOUT -signed long -_kcl_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count, - bool intr, signed long timeout, uint32_t *idx) -{ - struct default_wait_cb *cb; - signed long ret = timeout; - unsigned i; - - if (WARN_ON(!fences || !count || timeout < 0)) - return -EINVAL; - - if (timeout == 0) { - for (i = 0; i < count; ++i) - if (dma_fence_is_signaled(fences[i])) { - if (idx) - *idx = i; - return 1; - } - - return 0; - } - - cb = kcalloc(count, sizeof(struct default_wait_cb), GFP_KERNEL); - if (cb == NULL) { - ret = -ENOMEM; - goto err_free_cb; - } - - for (i = 0; i < count; ++i) { - struct dma_fence *fence = fences[i]; - - - cb[i].task = current; - if (dma_fence_add_callback(fence, &cb[i].base, - _kcl_fence_default_wait_cb)) { - /* This fence is already signaled */ - if (idx) - *idx = i; - goto fence_rm_cb; - } - } - - while (ret > 0) { - if (intr) - set_current_state(TASK_INTERRUPTIBLE); - else - set_current_state(TASK_UNINTERRUPTIBLE); - - if (dma_fence_test_signaled_any(fences, count, idx)) - break; - - ret = schedule_timeout(ret); - - if (ret > 0 && intr && signal_pending(current)) - ret = -ERESTARTSYS; - } - - __set_current_state(TASK_RUNNING); - -fence_rm_cb: - while (i-- > 0) - dma_fence_remove_callback(fences[i], &cb[i].base); - -err_free_cb: - kfree(cb); - - return ret; -} -EXPORT_SYMBOL(_kcl_fence_wait_any_timeout); -#endif - #ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT signed long _kcl_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) diff --git a/include/kcl/backport/kcl_fence_backport.h b/include/kcl/backport/kcl_fence_backport.h index a29c3293c6c88..43d13b95da2be 100644 --- a/include/kcl/backport/kcl_fence_backport.h +++ b/include/kcl/backport/kcl_fence_backport.h @@ -4,14 +4,6 @@ #include #include -/* - * commit v4.18-rc2-533-g418cc6ca0607 - * dma-fence: Allow wait_any_timeout for all fences) - */ -#ifdef AMDKCL_FENCE_WAIT_ANY_TIMEOUT -#define dma_fence_wait_any_timeout _kcl_fence_wait_any_timeout -#endif - /* * commit v4.9-rc2-472-gbcc004b629d2 * dma-buf/fence: make timeout handling in fence_default_wait consistent (v2)) diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index a4a94e8a03e54..c96d716ce94b4 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -51,17 +51,6 @@ static inline bool __dma_fence_is_later(u64 f1, u64 f2, #endif #endif /* HAVE__DMA_FENCE_IS_LATER_2ARGS */ -/* - * commit v4.18-rc2-533-g418cc6ca0607 - * dma-fence: Allow wait_any_timeout for all fences) - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 19, 0) -#define AMDKCL_FENCE_WAIT_ANY_TIMEOUT -signed long -_kcl_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count, - bool intr, signed long timeout, uint32_t *idx); -#endif - /* * commit v4.9-rc2-472-gbcc004b629d2 * dma-buf/fence: make timeout handling in fence_default_wait consistent (v2)) From db0aa9c682b7cb491486e877d6486ee3fa4f0070 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Fri, 9 May 2025 13:28:48 +0800 Subject: [PATCH 1507/2653] drm/amdkcl: test whether drm_file_err() exist It's caused by ec0a2cc40756 "drm: add drm_file_err function to add process info" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- .../amd/backport/include/kcl/kcl_drm_file.h | 5 +++ drivers/gpu/drm/amd/backport/kcl_drm_file.c | 31 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 | 16 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 56 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h index 381da116a67ac..2472c61b0e26d 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h @@ -29,4 +29,9 @@ void _kcl_drm_print_memory_stats(struct drm_printer *p, int drm_memory_stats_is_zero(const struct drm_memory_stats *stats); #endif +#ifndef HAVE_DRM_FILE_ERR +void kcl_drm_file_err(struct drm_file *file_priv, const char *fmt, ...); +#define drm_file_err kcl_drm_file_err +#endif + #endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_file.c b/drivers/gpu/drm/amd/backport/kcl_drm_file.c index e28ba0dd163d4..70327a98cee90 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_file.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_file.c @@ -37,6 +37,7 @@ #include #include #include +#include #include "amdgpu_fdinfo.h" #ifndef HAVE_DRM_SHOW_FDINFO /** @@ -113,3 +114,33 @@ int drm_memory_stats_is_zero(const struct drm_memory_stats *stats) stats->active == 0); } #endif + +#ifndef HAVE_DRM_FILE_ERR +void kcl_drm_file_err(struct drm_file *file_priv, const char *fmt, ...) +{ + va_list args; + struct va_format vaf; + struct pid *pid; + struct task_struct *task; + struct drm_device *dev = file_priv->minor->dev; + + va_start(args, fmt); + vaf.fmt = fmt; + vaf.va = &args; + + rcu_read_lock(); + pid = rcu_dereference(file_priv->pid); + task = pid_task(pid, +#ifdef HAVE_PIDTYPE_TGID + PIDTYPE_TGID); +#else + PIDTYPE_PGID); +#endif + drm_err(dev, "comm: %s pid: %d client: %s ... %pV", task ? task->comm : "Unset", + task ? task->pid : 0, "Unset", &vaf); + + va_end(args); + rcu_read_unlock(); +} +EXPORT_SYMBOL(kcl_drm_file_err); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0b2efa3ca190a..1614ac9110c26 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -571,6 +571,9 @@ /* drm_fb_helper_init() has 3 args */ /* #undef HAVE_DRM_FB_HELPER_INIT_3ARGS */ +/* drm_file_err() is available */ +#define HAVE_DRM_FILE_ERR 1 + /* drm_firmware_drivers_only() is available */ #define HAVE_DRM_FIRMWARE_DRIVERS_ONLY 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 new file mode 100644 index 0000000000000..fd413cbd2300a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.14-1914-gec0a2cc40756 +dnl # dma-buf: Add drm_file_err (v1) +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FILE_ERR], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_file_err(NULL, NULL); + ], [drm_file_err], [drivers/gpu/drm/drm_file.c],[ + AC_DEFINE(HAVE_DRM_FILE_ERR, 1, + [drm_file_err() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6ed26cb091c13..cc84cb94206f7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -271,6 +271,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRSCPY_ALLOW_TWO_ARGUMENTS AC_AMDGPU_DMA_FENCE_ARRAY_FIRST AC_AMDGPU_DMA_FENCE_DEDUP_ARRAY + AC_AMDGPU_DRM_FILE_ERR AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From e6659cddc3e288f80b86a474d7d7346b1db5e2b0 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Fri, 16 May 2025 12:30:10 +0800 Subject: [PATCH 1508/2653] drm/amdkcl: test whether drm_file->client_name exist It's caused by 4c26d90bcd "drm: add DRM_SET_CLIENT_NAME ioctl" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/kcl_drm_file.c | 11 +++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm_file.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 31 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_file.m4 diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_file.c b/drivers/gpu/drm/amd/backport/kcl_drm_file.c index 70327a98cee90..24e3d0b5ffd00 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_file.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_file.c @@ -128,6 +128,9 @@ void kcl_drm_file_err(struct drm_file *file_priv, const char *fmt, ...) vaf.fmt = fmt; vaf.va = &args; +#ifdef HAVE_DRM_FILE_CLIENT_NAME + mutex_lock(&file_priv->client_name_lock); +#endif rcu_read_lock(); pid = rcu_dereference(file_priv->pid); task = pid_task(pid, @@ -136,11 +139,19 @@ void kcl_drm_file_err(struct drm_file *file_priv, const char *fmt, ...) #else PIDTYPE_PGID); #endif +#ifdef HAVE_DRM_FILE_CLIENT_NAME + drm_err(dev, "comm: %s pid: %d client: %s ... %pV", task ? task->comm : "Unset", + task ? task->pid : 0, file_priv->client_name ?: "Unset", &vaf); +#else drm_err(dev, "comm: %s pid: %d client: %s ... %pV", task ? task->comm : "Unset", task ? task->pid : 0, "Unset", &vaf); +#endif va_end(args); rcu_read_unlock(); +#ifdef HAVE_DRM_FILE_CLIENT_NAME + mutex_unlock(&file_priv->client_name_lock); +#endif } EXPORT_SYMBOL(kcl_drm_file_err); #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1614ac9110c26..9607e58597801 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -571,6 +571,9 @@ /* drm_fb_helper_init() has 3 args */ /* #undef HAVE_DRM_FB_HELPER_INIT_3ARGS */ +/* drm_file->client_name is available */ +#define HAVE_DRM_FILE_CLIENT_NAME 1 + /* drm_file_err() is available */ #define HAVE_DRM_FILE_ERR 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_file.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_file.m4 new file mode 100644 index 0000000000000..ad9fe77b06a05 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_file.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.12-rc1-309-g56c594d8df64 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FILE_CLIENT_NAME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct drm_file *filp = NULL; + filp->client_name = NULL; + ], [ + AC_DEFINE(HAVE_DRM_FILE_CLIENT_NAME, 1, + [struct drm_file->client_name is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cc84cb94206f7..57191472c4754 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -272,6 +272,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_ARRAY_FIRST AC_AMDGPU_DMA_FENCE_DEDUP_ARRAY AC_AMDGPU_DRM_FILE_ERR + AC_AMDGPU_DRM_FILE_CLIENT_NAME AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From e738a3359c64614032b905d75334ee91ff215221 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 10:04:57 +0800 Subject: [PATCH 1509/2653] drm/amdkcl: cleanup macro AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 133 ---------------------- drivers/gpu/drm/amd/amdkcl/main.c | 2 - include/kcl/backport/kcl_fence_backport.h | 17 --- include/kcl/kcl_fence.h | 15 --- 4 files changed, 167 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index 49b98dd78dfa1..ca679c5e1f165 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -25,129 +25,6 @@ #define CREATE_TRACE_POINTS #include "kcl_fence_trace.h" -/* Copied from drivers/dma-buf/dma-fence.c */ -#if defined(AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT) -static bool -dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count, - uint32_t *idx) -{ - int i; - - for (i = 0; i < count; ++i) { - struct dma_fence *fence = fences[i]; - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { - if (idx) - *idx = i; - return true; - } - } - return false; -} -#endif - -struct default_wait_cb { - struct dma_fence_cb base; - struct task_struct *task; -}; - -#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT -static void (*_kcl_fence_default_wait_cb)(struct dma_fence *fence, struct dma_fence_cb *cb); - -signed long -_kcl_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) -{ - struct default_wait_cb cb; - unsigned long flags; - signed long ret = timeout ? timeout : 1; - bool was_set; - - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) - return ret; - - spin_lock_irqsave(fence->lock, flags); - - if (intr && signal_pending(current)) { - ret = -ERESTARTSYS; - goto out; - } - - was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, - &fence->flags); - - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) - goto out; - - if (!was_set && fence->ops->enable_signaling) { - /* - * Modifications [2017-03-29] (c) [2017] - * Advanced Micro Devices, Inc. - */ - trace_kcl_fence_enable_signal(fence); - - if (!fence->ops->enable_signaling(fence)) { - dma_fence_signal_locked(fence); - goto out; - } - } - - if (!timeout) { - ret = 0; - goto out; - } - - cb.base.func = _kcl_fence_default_wait_cb; - cb.task = current; - list_add(&cb.base.node, &fence->cb_list); - - while (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags) && ret > 0) { - if (intr) - __set_current_state(TASK_INTERRUPTIBLE); - else - __set_current_state(TASK_UNINTERRUPTIBLE); - spin_unlock_irqrestore(fence->lock, flags); - - ret = schedule_timeout(ret); - - spin_lock_irqsave(fence->lock, flags); - if (ret > 0 && intr && signal_pending(current)) - ret = -ERESTARTSYS; - } - - if (!list_empty(&cb.base.node)) - list_del(&cb.base.node); - __set_current_state(TASK_RUNNING); - -out: - spin_unlock_irqrestore(fence->lock, flags); - return ret; -} -EXPORT_SYMBOL(_kcl_fence_default_wait); -#endif - -#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT -signed long -_kcl_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) -{ - signed long ret; - - if (WARN_ON(timeout < 0)) - return -EINVAL; - - /* - * Modifications [2017-03-29] (c) [2017] - * Advanced Micro Devices, Inc. - */ - trace_kcl_fence_wait_start(fence); - if (fence->ops->wait) - ret = fence->ops->wait(fence, intr, timeout); - else - ret = _kcl_fence_default_wait(fence, intr, timeout); - trace_kcl_fence_wait_end(fence); - return ret; -} -EXPORT_SYMBOL(_kcl_fence_wait_timeout); -#endif - #ifdef AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING bool _kcl_fence_enable_signaling(struct dma_fence *f) { @@ -155,16 +32,6 @@ bool _kcl_fence_enable_signaling(struct dma_fence *f) } EXPORT_SYMBOL(_kcl_fence_enable_signaling); #endif -/* - * Modifications [2016-12-23] (c) [2016] - * Advanced Micro Devices, Inc. - */ -void amdkcl_fence_init(void) -{ -#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT - _kcl_fence_default_wait_cb = amdkcl_fp_setup("dma_fence_default_wait_cb", NULL); -#endif -} #if !defined(HAVE_DMA_FENCE_DESCRIBE) /** diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index e02c5db0eb328..73fd6da35a4e0 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -3,7 +3,6 @@ #include extern void amdkcl_dev_cgroup_init(void); -extern void amdkcl_fence_init(void); extern void amdkcl_io_init(void); extern void amdkcl_mm_init(void); extern void amdkcl_suspend_init(void); @@ -14,7 +13,6 @@ extern void amdkcl_prime_init(void); int __init amdkcl_init(void) { amdkcl_dev_cgroup_init(); - amdkcl_fence_init(); amdkcl_io_init(); amdkcl_mm_init(); amdkcl_suspend_init(); diff --git a/include/kcl/backport/kcl_fence_backport.h b/include/kcl/backport/kcl_fence_backport.h index 43d13b95da2be..e70e8a809c228 100644 --- a/include/kcl/backport/kcl_fence_backport.h +++ b/include/kcl/backport/kcl_fence_backport.h @@ -4,23 +4,6 @@ #include #include -/* - * commit v4.9-rc2-472-gbcc004b629d2 - * dma-buf/fence: make timeout handling in fence_default_wait consistent (v2)) - * - * commit v4.9-rc2-473-g698c0f7ff216 - * dma-buf/fence: revert "don't wait when specified timeout is zero" (v2) - */ -#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT - -#ifdef dma_fence_default_wait -#undef dma_fence_default_wait -#endif - -#define dma_fence_default_wait _kcl_fence_default_wait -#define dma_fence_wait_timeout _kcl_fence_wait_timeout -#endif - /* * commit v4.14-rc3-601-g5f72db59160c * dma-buf/fence: Sparse wants __rcu on the object itself diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index c96d716ce94b4..04457fcb86e36 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -51,21 +51,6 @@ static inline bool __dma_fence_is_later(u64 f1, u64 f2, #endif #endif /* HAVE__DMA_FENCE_IS_LATER_2ARGS */ -/* - * commit v4.9-rc2-472-gbcc004b629d2 - * dma-buf/fence: make timeout handling in fence_default_wait consistent (v2)) - * - * commit v4.9-rc2-473-g698c0f7ff216 - * dma-buf/fence: revert "don't wait when specified timeout is zero" (v2) - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 10, 0) -#define AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT -signed long -_kcl_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout); -extern signed long _kcl_fence_wait_timeout(struct fence *fence, bool intr, - signed long timeout); -#endif - /* * commit v4.14-rc3-601-g5f72db59160c * dma-buf/fence: Sparse wants __rcu on the object itself From 8474d7a4cb1be4e43d510f29d4cd07f215192809 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 10:15:41 +0800 Subject: [PATCH 1510/2653] drm/amdkcl: cleanup macro AMDKCL_DRM_DP_CEC_XXX_CHECK_CB These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- .../kcl/backport/kcl_drm_dp_helper_backport.h | 10 ---- include/kcl/kcl_drm_dp_cec.h | 47 +------------------ 2 files changed, 1 insertion(+), 56 deletions(-) diff --git a/include/kcl/backport/kcl_drm_dp_helper_backport.h b/include/kcl/backport/kcl_drm_dp_helper_backport.h index 61b4a14bb0151..3955ccaa33951 100644 --- a/include/kcl/backport/kcl_drm_dp_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_helper_backport.h @@ -4,16 +4,6 @@ #include -/* - * commit v4.19-rc1-100-g5ce70c799ac2 - * drm_dp_cec: check that aux has a transfer function - */ -#if defined(AMDKCL_DRM_DP_CEC_XXX_CHECK_CB) -#define drm_dp_cec_irq _kcl_drm_dp_cec_irq -#define drm_dp_cec_set_edid _kcl_drm_dp_cec_set_edid -#define drm_dp_cec_unset_edid _kcl_drm_dp_cec_unset_edid -#endif - #if !defined(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP) #define drm_dp_cec_register_connector _kcl_drm_dp_cec_register_connector #endif diff --git a/include/kcl/kcl_drm_dp_cec.h b/include/kcl/kcl_drm_dp_cec.h index a50c290cc7248..6c5e559ca9f35 100644 --- a/include/kcl/kcl_drm_dp_cec.h +++ b/include/kcl/kcl_drm_dp_cec.h @@ -8,52 +8,7 @@ #ifndef __KCL_KCL_DRM_DP_CEC_H__ #define __KCL_KCL_DRM_DP_CEC_H__ -#include - -/* - * commit v4.19-rc1-100-g5ce70c799ac2 - * drm_dp_cec: check that aux has a transfer function - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 20, 0) -#define AMDKCL_DRM_DP_CEC_XXX_CHECK_CB -#endif - -/* Copied from gpu/drm/drm_dp_cec.c and modified for KCL */ -#if defined(AMDKCL_DRM_DP_CEC_XXX_CHECK_CB) -static inline void _kcl_drm_dp_cec_irq(struct drm_dp_aux *aux) -{ -#ifdef CONFIG_DRM_DP_CEC - /* No transfer function was set, so not a DP connector */ - if (!aux->transfer) - return; -#endif - - drm_dp_cec_irq(aux); -} - -static inline void _kcl_drm_dp_cec_set_edid(struct drm_dp_aux *aux, - const struct edid *edid) -{ -#ifdef CONFIG_DRM_DP_CEC - /* No transfer function was set, so not a DP connector */ - if (!aux->transfer) - return; -#endif - - drm_dp_cec_set_edid(aux, edid); -} - -static inline void _kcl_drm_dp_cec_unset_edid(struct drm_dp_aux *aux) -{ -#ifdef CONFIG_DRM_DP_CEC - /* No transfer function was set, so not a DP connector */ - if (!aux->transfer) - return; -#endif - - drm_dp_cec_unset_edid(aux); -} -#endif +#include #if !defined(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP) static inline void _kcl_drm_dp_cec_register_connector(struct drm_dp_aux *aux, From 8214ec8c526bff8ba8de6616135cf6c4d86e4ab9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 10:09:17 +0800 Subject: [PATCH 1511/2653] drm/amdkcl: cleanup macro AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou --- .../drm/amd/amdkcl/kcl_drm_atomic_helper.c | 20 ---------- drivers/gpu/drm/amd/backport/backport.h | 2 +- .../backport/kcl_drm_atomic_helper_backport.h | 37 ------------------- include/kcl/kcl_drm_atomic_helper.h | 10 ----- 4 files changed, 1 insertion(+), 68 deletions(-) delete mode 100644 include/kcl/backport/kcl_drm_atomic_helper_backport.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c index c0f145df309d3..0851d46f3a17e 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -29,26 +29,6 @@ #include #include -#ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET -/* Copied from drivers/gpu/drm/drm_atomic_state_helper.c and modified for KCL */ -void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, - struct drm_plane_state *state) -{ - state->plane = plane; - state->rotation = DRM_MODE_ROTATE_0; - -#ifdef DRM_BLEND_ALPHA_OPAQUE - state->alpha = DRM_BLEND_ALPHA_OPAQUE; -#endif -#ifdef DRM_MODE_BLEND_PREMULTI - state->pixel_blend_mode = DRM_MODE_BLEND_PREMULTI; -#endif - - plane->state = state; -} -EXPORT_SYMBOL(_kcl__drm_atomic_helper_plane_reset); -#endif - #ifndef HAVE___DRM_ATOMIC_HELPER_CRTC_RESET /* Copied from drivers/gpu/drm/drm_atomic_state_helper.c */ void diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index db5ca27543aa3..6a30f66c2f98b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -55,7 +55,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/include/kcl/backport/kcl_drm_atomic_helper_backport.h b/include/kcl/backport/kcl_drm_atomic_helper_backport.h deleted file mode 100644 index 44ea7b0f771d3..0000000000000 --- a/include/kcl/backport/kcl_drm_atomic_helper_backport.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2014 Red Hat - * Copyright (C) 2014 Intel Corp. - * Copyright (C) 2018 Intel Corp. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Rob Clark - * Daniel Vetter - */ -#ifndef AMDKCL_DRM_ATOMIC_HELPER_BACKPORT_H -#define AMDKCL_DRM_ATOMIC_HELPER_BACKPORT_H - -#include - -#ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET -#define __drm_atomic_helper_plane_reset _kcl__drm_atomic_helper_plane_reset -#endif /* AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET */ - -#endif diff --git a/include/kcl/kcl_drm_atomic_helper.h b/include/kcl/kcl_drm_atomic_helper.h index 3af6d075cbe99..98f936123fc5f 100644 --- a/include/kcl/kcl_drm_atomic_helper.h +++ b/include/kcl/kcl_drm_atomic_helper.h @@ -39,16 +39,6 @@ #define DRM_PLANE_NO_SCALING (1<<16) #endif -/* - * v4.19-rc1-206-ge267364a6e1b - * drm/atomic: Initialise planes with opaque alpha values - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 20, 0) -#define AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET -void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, - struct drm_plane_state *state); -#endif - #ifndef HAVE___DRM_ATOMIC_HELPER_CRTC_RESET void __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state); From e1c42f2a87d9de162696bdb94d31663774c8d530 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 10:49:26 +0800 Subject: [PATCH 1512/2653] drm/amdkcl: cleanup macro AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 -- drivers/gpu/drm/scheduler/sched_fence.c | 2 -- include/kcl/kcl_fence.h | 11 ----------- 4 files changed, 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c index 85e560df7f6b8..1ef758ac5076e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c @@ -184,6 +184,5 @@ static const struct dma_fence_ops amdkfd_fence_ops = { .get_driver_name = amdkfd_fence_get_driver_name, .get_timeline_name = amdkfd_fence_get_timeline_name, .enable_signaling = amdkfd_fence_enable_signaling, - AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = amdkfd_fence_release, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 779415d96e171..ddc5f28ab5f3c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -930,7 +930,6 @@ static const struct dma_fence_ops amdgpu_fence_ops = { .get_driver_name = amdgpu_fence_get_driver_name, .get_timeline_name = amdgpu_fence_get_timeline_name, .enable_signaling = amdgpu_fence_enable_signaling, - AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = amdgpu_fence_release, }; @@ -938,7 +937,6 @@ static const struct dma_fence_ops amdgpu_job_fence_ops = { .get_driver_name = amdgpu_fence_get_driver_name, .get_timeline_name = amdgpu_job_fence_get_timeline_name, .enable_signaling = amdgpu_job_fence_enable_signaling, - AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = amdgpu_job_fence_release, }; diff --git a/drivers/gpu/drm/scheduler/sched_fence.c b/drivers/gpu/drm/scheduler/sched_fence.c index 5cba4c3477a18..5ff1a309d9b1b 100644 --- a/drivers/gpu/drm/scheduler/sched_fence.c +++ b/drivers/gpu/drm/scheduler/sched_fence.c @@ -191,7 +191,6 @@ static const struct dma_fence_ops drm_sched_fence_ops_scheduled = { .get_driver_name = drm_sched_fence_get_driver_name, .get_timeline_name = drm_sched_fence_get_timeline_name, AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL - AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = drm_sched_fence_release_scheduled, }; @@ -199,7 +198,6 @@ static const struct dma_fence_ops drm_sched_fence_ops_finished = { .get_driver_name = drm_sched_fence_get_driver_name, .get_timeline_name = drm_sched_fence_get_timeline_name, AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL - AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = drm_sched_fence_release_finished, #ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE .set_deadline = drm_sched_fence_set_deadline_finished, diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index 04457fcb86e36..d8e22bae79a09 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -105,17 +105,6 @@ bool _kcl_fence_enable_signaling(struct dma_fence *f); #define AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL #endif -/* - * commit v4.18-rc2-533-g418cc6ca0607 - * dma-fence: Make ->wait callback optional - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 19, 0) -#define AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL \ - .wait = dma_fence_default_wait, -#else -#define AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL -#endif - #if !defined(HAVE_DMA_FENCE_DESCRIBE) void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq); #endif From 02f5e1dd31bd0dd1a3054b2e6320fea562fa7819 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 10:37:15 +0800 Subject: [PATCH 1513/2653] drm/amdkcl: cleanup macro AMDKCL_FENCE_GET_RCU_SAFE These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 3 +- drivers/gpu/drm/scheduler/backport/backport.h | 3 +- drivers/gpu/drm/ttm/backport/backport.h | 3 +- include/kcl/backport/kcl_fence_backport.h | 14 ------- include/kcl/kcl_dma-resv.h | 3 +- include/kcl/kcl_fence.h | 41 ------------------- 6 files changed, 8 insertions(+), 59 deletions(-) delete mode 100644 include/kcl/backport/kcl_fence_backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6a30f66c2f98b..a2ea8803ecf5e 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -34,7 +34,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 8f980b3fc2384..3b93fdff732d6 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -5,7 +5,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 5e944f8950bbb..2f31d6a8191f3 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -9,7 +9,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/include/kcl/backport/kcl_fence_backport.h b/include/kcl/backport/kcl_fence_backport.h deleted file mode 100644 index e70e8a809c228..0000000000000 --- a/include/kcl/backport/kcl_fence_backport.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef AMDKCL_FENCE_BACKPORT_H -#define AMDKCL_FENCE_BACKPORT_H -#include -#include - -/* - * commit v4.14-rc3-601-g5f72db59160c - * dma-buf/fence: Sparse wants __rcu on the object itself - */ -#ifdef AMDKCL_FENCE_GET_RCU_SAFE -#define dma_fence_get_rcu_safe _kcl_fence_get_rcu_safe -#endif -#endif diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 4c2b2576374ed..c183ea930a4d8 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -47,7 +47,8 @@ #define KCL_KCL_DMA_RESV_H #include -#include +#include +#include #include #include #include diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index d8e22bae79a09..bd158dc0f6907 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -51,47 +51,6 @@ static inline bool __dma_fence_is_later(u64 f1, u64 f2, #endif #endif /* HAVE__DMA_FENCE_IS_LATER_2ARGS */ -/* - * commit v4.14-rc3-601-g5f72db59160c - * dma-buf/fence: Sparse wants __rcu on the object itself - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 15, 0) -#define AMDKCL_FENCE_GET_RCU_SAFE -static inline struct dma_fence * -_kcl_fence_get_rcu_safe(struct dma_fence __rcu **fencep) -{ - do { - struct dma_fence *fence; - - fence = rcu_dereference(*fencep); - if (!fence) - return NULL; - - if (!dma_fence_get_rcu(fence)) - continue; - - /* The atomic_inc_not_zero() inside dma_fence_get_rcu() - * provides a full memory barrier upon success (such as now). - * This is paired with the write barrier from assigning - * to the __rcu protected fence pointer so that if that - * pointer still matches the current fence, we know we - * have successfully acquire a reference to it. If it no - * longer matches, we are holding a reference to some other - * reallocated pointer. This is possible if the allocator - * is using a freelist like SLAB_TYPESAFE_BY_RCU where the - * fence remains valid for the RCU grace period, but it - * may be reallocated. When using such allocators, we are - * responsible for ensuring the reference we get is to - * the right fence, as below. - */ - if (fence == rcu_access_pointer(*fencep)) - return rcu_pointer_handoff(fence); - - dma_fence_put(fence); - } while (1); -} -#endif - /* * commit v4.18-rc2-519-gc701317a3eb8 * dma-fence: Make ->enable_signaling optional From 2c6a114e2fc9b37a739cc546866ab0a9794a43d0 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 14 May 2025 14:21:33 +0800 Subject: [PATCH 1514/2653] drm/amdkcl: Include for missing declaration Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c | 1 + include/kcl/kcl_shrinker.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c b/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c index fb57e87ff981b..7175409637df9 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c @@ -10,6 +10,7 @@ * Multiqueue VM started 5.8.00, Rik van Riel. */ #include +#include #ifndef HAVE_SYNCHRONIZE_SHRINKERS static DECLARE_RWSEM(shrinker_rwsem); diff --git a/include/kcl/kcl_shrinker.h b/include/kcl/kcl_shrinker.h index ca93cd0197f9f..81270e3330cea 100644 --- a/include/kcl/kcl_shrinker.h +++ b/include/kcl/kcl_shrinker.h @@ -3,6 +3,8 @@ #ifndef AMDKCL_SHRINKER_H #define AMDKCL_SHRINKER_H +#include + #ifndef HAVE_SYNCHRONIZE_SHRINKERS extern void synchronize_shrinkers(void); #endif From edb9169ff5fac5bc6d4162933d7962ecb4e26a3d Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 15:55:53 +0800 Subject: [PATCH 1515/2653] drm/amdkcl: Fall back to dumpversion if dumpfullversion is unsupported Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/pre-build.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index ec589e5ad3d2b..f69be8865e1b8 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -50,7 +50,7 @@ if [ "$CC" == "gcc" ]; then done fi - gcc_version=$($CC -dumpfullversion | awk -F. '{printf "%d%02d%02d", $1, $2, $3}') + gcc_version=$(($CC -dumpfullversion 2>/dev/null || $CC -dumpversion) | awk -F. '{printf "%d%02d%02d", $1, $2, $3}') kernel_version=$(uname -r | awk -F. '{printf "%d%02d", $1, $2}') # gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. if [ "$gcc_version" -lt 40805 ] && [ "$kernel_version" -ge 0504 ]; then From 00dc5c80796eff86f368585c62aa7e49ddcf4474 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 16 May 2025 17:35:20 +0800 Subject: [PATCH 1516/2653] drm/amdkcl: initialize the rename_symbol.h Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 987ac180e8fbd..7a9682c51f0c8 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -47,6 +47,7 @@ endif dkms-config ?= amd/dkms/dkms-config.mk config-file ?= amd/dkms/config/config.h +rename_header ?= include/rename_symbol.h KCL_MACRO_CHECK_COMMAND=$(shell grep $(1) $(config-file) | grep -q "define" && echo "y") modules: sanity-check $(dkms-config) @@ -57,7 +58,7 @@ modules: sanity-check $(dkms-config) M=$(module_build_dir) $(module_build_flags) $(Q)amd/dkms/post-build.sh $(module_build_dir) -sanity-check: pre-build $(config-file) +sanity-check: pre-build $(config-file) $(rename_header) $(if $(call KCL_MACRO_CHECK_COMMAND, HAVE_DMA_RESV_SEQ_BUG), $(error dma_resv->seq is missing. exit...)) $(if $(call KCL_MACRO_CHECK_COMMAND, HAVE_RESERVATION_WW_CLASS_BUG), $(error reservation_ww_class is missing. exit...)) @@ -70,5 +71,5 @@ pre-build: clean: $(Q)echo "Cleaning build files..." $(Q)make -C $(kernel_build_dir) M=$(module_src_dir) clean - $(Q)rm -f $(dkms-config) $(config-file) + $(Q)rm -f $(dkms-config) $(config-file) $(rename_header) endif From ac3dfc8a1f7b4a383c2b51b672414186851b6db8 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 May 2025 10:56:19 +0800 Subject: [PATCH 1517/2653] drm/amdkcl: cleanup macro AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING These DRM version KCL macro always are disable, so clean it. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 8 -------- drivers/gpu/drm/scheduler/sched_fence.c | 2 -- include/kcl/kcl_fence.h | 13 ------------- 3 files changed, 23 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index ca679c5e1f165..1214d429aaf28 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -25,14 +25,6 @@ #define CREATE_TRACE_POINTS #include "kcl_fence_trace.h" -#ifdef AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING -bool _kcl_fence_enable_signaling(struct dma_fence *f) -{ - return true; -} -EXPORT_SYMBOL(_kcl_fence_enable_signaling); -#endif - #if !defined(HAVE_DMA_FENCE_DESCRIBE) /** * dma_fence_describe - Dump fence describtion into seq_file diff --git a/drivers/gpu/drm/scheduler/sched_fence.c b/drivers/gpu/drm/scheduler/sched_fence.c index 5ff1a309d9b1b..179c86488a5d4 100644 --- a/drivers/gpu/drm/scheduler/sched_fence.c +++ b/drivers/gpu/drm/scheduler/sched_fence.c @@ -190,14 +190,12 @@ static void drm_sched_fence_set_deadline_finished(struct dma_fence *f, static const struct dma_fence_ops drm_sched_fence_ops_scheduled = { .get_driver_name = drm_sched_fence_get_driver_name, .get_timeline_name = drm_sched_fence_get_timeline_name, - AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL .release = drm_sched_fence_release_scheduled, }; static const struct dma_fence_ops drm_sched_fence_ops_finished = { .get_driver_name = drm_sched_fence_get_driver_name, .get_timeline_name = drm_sched_fence_get_timeline_name, - AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL .release = drm_sched_fence_release_finished, #ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE .set_deadline = drm_sched_fence_set_deadline_finished, diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index bd158dc0f6907..525268df513de 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -51,19 +51,6 @@ static inline bool __dma_fence_is_later(u64 f1, u64 f2, #endif #endif /* HAVE__DMA_FENCE_IS_LATER_2ARGS */ -/* - * commit v4.18-rc2-519-gc701317a3eb8 - * dma-fence: Make ->enable_signaling optional - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 19, 0) -#define AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING -bool _kcl_fence_enable_signaling(struct dma_fence *f); -#define AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL \ - .enable_signaling = _kcl_fence_enable_signaling, -#else -#define AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL -#endif - #if !defined(HAVE_DMA_FENCE_DESCRIBE) void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq); #endif From bbcf64c9cf75008b581a33353c917c67a4b2adf4 Mon Sep 17 00:00:00 2001 From: chengjya Date: Mon, 2 Dec 2024 13:17:39 +0800 Subject: [PATCH 1518/2653] drm/amdkcl: wrap under code HAVE_STRUCT_XARRAY It's caused by the following commit:bf83e8c28 "drm/amdgpu: enable userqueue secure sem for GFX 12" Signed-off-by: chengjya Reviewed-by: Bob Zhou drm/amdkcl: wrap code under HAVE_STRUCT_XARRAY It's caused by following commit:6ec4ee09b510a880a1ba69529cab28b8e7550fc4 "drm/amdgpu: Implement userqueue signal/wait IOCTL " Signed-off-by: chengjya Reviewed-by: Bob Zhou drm/amdkcl: wrap under code HAVE_STRUCT_XARRAY It's caused byIt's caused by following commit 7a3b085cf7c1 "drm/amdgpu: Enable userq fence interrupt support" Signed-off-by: chengjya Reviewed-by: Bob Zhou drm/amdkcl: wrap code under HAVE_STRUCT_XARRAY It's caused by 65718b00d8291 "drm/amdgpu: remove DRM_AMDGPU_NAVI3X_USERQ config for UQ" Signed-off-by: Yang Su Reviewed-by: Bob Zhou drm/amdkcl: Replace xarray with idr in kernel < 4.20 Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 5 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 5 ++ .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 73 ++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 12 ++- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 12 ++- 7 files changed, 114 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 0a8b38c04f332..1bc0d6c906662 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1185,7 +1185,12 @@ struct amdgpu_device { * in the EOP interrupt handler to signal the particular user * queue fence. */ +#ifdef HAVE_STRUCT_XARRAY struct xarray userq_xa; +#else + struct idr userq_idr; + spinlock_t userq_lock; +#endif /* df */ struct amdgpu_df df; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 3ee8f1824c5aa..503db577bce0e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4467,7 +4467,12 @@ int amdgpu_device_init(struct amdgpu_device *adev, spin_lock_init(&adev->virt.rlcg_reg_lock); spin_lock_init(&adev->wb.lock); +#ifdef HAVE_STRUCT_XARRAY xa_init_flags(&adev->userq_xa, XA_FLAGS_LOCK_IRQ); +#else + idr_init(&adev->userq_idr); + spin_lock_init(&adev->userq_lock); +#endif INIT_LIST_HEAD(&adev->reset_list); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 492f1089316f9..2d6ebd238d73d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -475,7 +475,12 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) } queue->doorbell_index = index; +#ifdef HAVE_STRUCT_XARRAY xa_init_flags(&queue->fence_drv_xa, XA_FLAGS_ALLOC); +#else + idr_init(&queue->fence_drv_idr); + spin_lock_init(&queue->fence_drv_lock); +#endif r = amdgpu_userq_fence_driver_alloc(adev, queue); if (r) { drm_file_err(uq_mgr->file, "Failed to alloc fence driver\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index b1ca91b7cda4b..a6b61ce40f0db 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -60,7 +60,12 @@ struct amdgpu_usermode_queue { struct amdgpu_userq_obj db_obj; struct amdgpu_userq_obj fw_obj; struct amdgpu_userq_obj wptr_obj; +#ifdef HAVE_STRUCT_XARRAY struct xarray fence_drv_xa; +#else + struct idr fence_drv_idr; + spinlock_t fence_drv_lock; +#endif struct amdgpu_userq_fence_driver *fence_drv; struct dma_fence *last_fence; u32 xcp_id; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index c2a983ff23c95..cc2a128c1183b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -94,10 +94,17 @@ int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev, fence_drv->context = dma_fence_context_alloc(1); get_task_comm(fence_drv->timeline_name, current); +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->userq_xa, flags); r = xa_err(__xa_store(&adev->userq_xa, userq->doorbell_index, fence_drv, GFP_KERNEL)); xa_unlock_irqrestore(&adev->userq_xa, flags); +#else + spin_lock_irqsave(&adev->userq_lock, flags); + r = idr_alloc(&adev->userq_idr, fence_drv, userq->doorbell_index, + userq->doorbell_index + 1, GFP_KERNEL); + spin_unlock_irqrestore(&adev->userq_lock, flags); +#endif if (r) goto free_seq64; @@ -113,11 +120,16 @@ int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev, return r; } +#ifdef HAVE_STRUCT_XARRAY static void amdgpu_userq_walk_and_drop_fence_drv(struct xarray *xa) +#else +static void amdgpu_userq_walk_and_drop_fence_drv(struct idr *idr, spinlock_t *idr_lock) +#endif { struct amdgpu_userq_fence_driver *fence_drv; unsigned long index; +#ifdef HAVE_STRUCT_XARRAY if (xa_empty(xa)) return; @@ -128,13 +140,33 @@ static void amdgpu_userq_walk_and_drop_fence_drv(struct xarray *xa) } xa_unlock(xa); +#else + if (idr_is_empty(idr)) + return; + + spin_lock(idr_lock); + idr_for_each_entry(idr, fence_drv, index) { + idr_remove(idr, index); + amdgpu_userq_fence_driver_put(fence_drv); + } + + spin_unlock(idr_lock); +#endif } void amdgpu_userq_fence_driver_free(struct amdgpu_usermode_queue *userq) { +#ifdef HAVE_STRUCT_XARRAY amdgpu_userq_walk_and_drop_fence_drv(&userq->fence_drv_xa); xa_destroy(&userq->fence_drv_xa); +#else + unsigned long flags; + amdgpu_userq_walk_and_drop_fence_drv(&userq->fence_drv_idr, &userq->fence_drv_lock); + spin_lock_irqsave(&userq->fence_drv_lock, flags); + idr_destroy(&userq->fence_drv_idr); + spin_unlock_irqrestore(&userq->fence_drv_lock, flags); +#endif /* Drop the fence_drv reference held by user queue */ amdgpu_userq_fence_driver_put(userq->fence_drv); } @@ -177,7 +209,12 @@ void amdgpu_userq_fence_driver_destroy(struct kref *ref) struct amdgpu_userq_fence_driver *xa_fence_drv; struct amdgpu_device *adev = fence_drv->adev; struct amdgpu_userq_fence *fence, *tmp; +#ifdef HAVE_STRUCT_XARRAY struct xarray *xa = &adev->userq_xa; +#else + struct idr *idr = &adev->userq_idr; + struct spinlock *idr_lock = &adev->userq_lock; +#endif unsigned long index, flags; struct dma_fence *f; @@ -195,11 +232,19 @@ void amdgpu_userq_fence_driver_destroy(struct kref *ref) } spin_unlock_irqrestore(&fence_drv->fence_list_lock, flags); +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(xa, flags); xa_for_each(xa, index, xa_fence_drv) if (xa_fence_drv == fence_drv) __xa_erase(xa, index); xa_unlock_irqrestore(xa, flags); +#else + spin_lock_irqsave(idr_lock, flags); + idr_for_each_entry(idr, xa_fence_drv, index) + if (xa_fence_drv == fence_drv) + idr_remove(idr, index); + spin_unlock_irqrestore(idr_lock, flags); +#endif /* Free seq64 memory */ amdgpu_seq64_free(adev, fence_drv->va); @@ -245,13 +290,22 @@ static int amdgpu_userq_fence_create(struct amdgpu_usermode_queue *userq, amdgpu_userq_fence_driver_get(fence_drv); dma_fence_get(fence); +#ifdef HAVE_STRUCT_XARRAY if (!xa_empty(&userq->fence_drv_xa)) { +#else + if (!idr_is_empty(&userq->fence_drv_idr)) { +#endif struct amdgpu_userq_fence_driver *stored_fence_drv; unsigned long index, count = 0; int i = 0; +#ifdef HAVE_STRUCT_XARRAY xa_lock(&userq->fence_drv_xa); xa_for_each(&userq->fence_drv_xa, index, stored_fence_drv) +#else + spin_lock(&userq->fence_drv_lock); + idr_for_each_entry(&userq->fence_drv_idr, stored_fence_drv, index) +#endif count++; userq_fence->fence_drv_array = @@ -260,15 +314,25 @@ static int amdgpu_userq_fence_create(struct amdgpu_usermode_queue *userq, GFP_ATOMIC); if (userq_fence->fence_drv_array) { +#ifdef HAVE_STRUCT_XARRAY xa_for_each(&userq->fence_drv_xa, index, stored_fence_drv) { userq_fence->fence_drv_array[i] = stored_fence_drv; __xa_erase(&userq->fence_drv_xa, index); +#else + idr_for_each_entry(&userq->fence_drv_idr, stored_fence_drv, index) { + userq_fence->fence_drv_array[i] = stored_fence_drv; + idr_remove(&userq->fence_drv_idr, index); +#endif i++; } } userq_fence->fence_drv_array_count = i; +#ifdef HAVE_STRUCT_XARRAY xa_unlock(&userq->fence_drv_xa); +#else + spin_unlock(&userq->fence_drv_lock); +#endif } else { userq_fence->fence_drv_array = NULL; userq_fence->fence_drv_array_count = 0; @@ -323,7 +387,6 @@ static void amdgpu_userq_fence_free(struct rcu_head *rcu) /* Release the fence driver reference */ amdgpu_userq_fence_driver_put(fence_drv); - kvfree(userq_fence->fence_drv_array); kmem_cache_free(amdgpu_userq_fence_slab, userq_fence); } @@ -891,9 +954,17 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, * Otherwise, we would gather those references until we don't * have any more space left and crash. */ +#ifdef HAVE_STRUCT_XARRAY r = xa_alloc(&waitq->fence_drv_xa, &index, fence_drv, xa_limit_32b, GFP_KERNEL); if (r) +#else + spin_lock(&waitq->fence_drv_lock); + r = idr_alloc(&waitq->fence_drv_idr, fence_drv, 0, 0, GFP_KERNEL); + index = r; + spin_unlock(&waitq->fence_drv_lock); + if (r < 0) +#endif goto free_fences; amdgpu_userq_fence_driver_get(fence_drv); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 1f5aacc49d5a4..a1830f0472508 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6454,14 +6454,24 @@ static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, if (adev->enable_mes && doorbell_offset) { struct amdgpu_userq_fence_driver *fence_drv = NULL; - struct xarray *xa = &adev->userq_xa; unsigned long flags; +#ifdef HAVE_STRUCT_XARRAY + struct xarray *xa = &adev->userq_xa; xa_lock_irqsave(xa, flags); fence_drv = xa_load(xa, doorbell_offset); if (fence_drv) amdgpu_userq_fence_driver_process(fence_drv); xa_unlock_irqrestore(xa, flags); +#else + struct idr *idr = &adev->userq_idr; + + spin_lock_irqsave(&adev->userq_lock, flags); + fence_drv = idr_find(idr, doorbell_offset); + if (fence_drv) + amdgpu_userq_fence_driver_process(fence_drv); + spin_unlock_irqrestore(&adev->userq_lock, flags); +#endif } else { me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index aa1cd043cf642..dd855031dfc66 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -4857,14 +4857,24 @@ static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, if (adev->enable_mes && doorbell_offset) { struct amdgpu_userq_fence_driver *fence_drv = NULL; - struct xarray *xa = &adev->userq_xa; unsigned long flags; +#ifdef HAVE_STRUCT_XARRAY + struct xarray *xa = &adev->userq_xa; xa_lock_irqsave(xa, flags); fence_drv = xa_load(xa, doorbell_offset); if (fence_drv) amdgpu_userq_fence_driver_process(fence_drv); xa_unlock_irqrestore(xa, flags); +#else + struct idr *idr = &adev->userq_idr; + + spin_lock_irqsave(&adev->userq_lock, flags); + fence_drv = idr_find(idr, doorbell_offset); + if (fence_drv) + amdgpu_userq_fence_driver_process(fence_drv); + spin_unlock_irqrestore(&adev->userq_lock, flags); +#endif } else { me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; From 57de54591172f0b79d84d759763c8e28f9c7564d Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 16 May 2025 17:08:15 +0800 Subject: [PATCH 1519/2653] drm/amdkcl: wrap code under amdkcl_gem_resvp It's caused by the commit: 6a0f144be2 "drm/amdgpu: Add separate array of read and write for BO handles" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index cc2a128c1183b..c22630020057f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -608,18 +608,18 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, } for (i = 0; i < num_read_bo_handles; i++) { - if (!gobj_read || !gobj_read[i]->resv) + if (!gobj_read || !amdkcl_gem_resvp(gobj_read[i])) continue; - dma_resv_add_fence(gobj_read[i]->resv, fence, + dma_resv_add_fence(amdkcl_gem_resvp(gobj_read[i]), fence, DMA_RESV_USAGE_READ); } for (i = 0; i < num_write_bo_handles; i++) { - if (!gobj_write || !gobj_write[i]->resv) + if (!gobj_write || !amdkcl_gem_resvp(gobj_write[i])) continue; - dma_resv_add_fence(gobj_write[i]->resv, fence, + dma_resv_add_fence(amdkcl_gem_resvp(gobj_write[i]), fence, DMA_RESV_USAGE_WRITE); } @@ -798,7 +798,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, struct dma_resv_iter resv_cursor; struct dma_fence *fence; - dma_resv_for_each_fence(&resv_cursor, gobj_read[i]->resv, + dma_resv_for_each_fence(&resv_cursor, amdkcl_gem_resvp(gobj_read[i]), DMA_RESV_USAGE_READ, fence) num_fences++; } @@ -807,7 +807,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, struct dma_resv_iter resv_cursor; struct dma_fence *fence; - dma_resv_for_each_fence(&resv_cursor, gobj_write[i]->resv, + dma_resv_for_each_fence(&resv_cursor, amdkcl_gem_resvp(gobj_write[i]), DMA_RESV_USAGE_WRITE, fence) num_fences++; } @@ -839,7 +839,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, struct dma_resv_iter resv_cursor; struct dma_fence *fence; - dma_resv_for_each_fence(&resv_cursor, gobj_read[i]->resv, + dma_resv_for_each_fence(&resv_cursor, amdkcl_gem_resvp(gobj_read[i]), DMA_RESV_USAGE_READ, fence) { if (WARN_ON_ONCE(num_fences >= wait_info->num_fences)) { r = -EINVAL; @@ -856,7 +856,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, struct dma_resv_iter resv_cursor; struct dma_fence *fence; - dma_resv_for_each_fence(&resv_cursor, gobj_write[i]->resv, + dma_resv_for_each_fence(&resv_cursor, amdkcl_gem_resvp(gobj_write[i]), DMA_RESV_USAGE_WRITE, fence) { if (WARN_ON_ONCE(num_fences >= wait_info->num_fences)) { r = -EINVAL; From c38f564646b8d917570869ca1ec1250a2f6debd6 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 20 May 2025 18:07:36 +0800 Subject: [PATCH 1520/2653] drm/amdkcl: fake ttm_backup_backup_page Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/shmem-fs.m4 | 16 ++++++++++++++++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_folio_backport.h | 24 ++++++++++++++++++++++++ 4 files changed, 42 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/shmem-fs.m4 create mode 100644 include/kcl/kcl_folio_backport.h diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 57191472c4754..9021e9a0e922f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -267,6 +267,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GET_PANEL_MIN_BRIGHTNESS_QUIRK AC_AMDGPU_MODULE_IMPORT_NS AC_AMDGPU_DRM_DEV_WEDGED_EVENT + AC_AMDGPU_SHMEM_READ_FOLIO AC_AMDGPU_DRM_DRIVER_DATE AC_AMDGPU_STRSCPY_ALLOW_TWO_ARGUMENTS AC_AMDGPU_DMA_FENCE_ARRAY_FIRST diff --git a/drivers/gpu/drm/amd/dkms/m4/shmem-fs.m4 b/drivers/gpu/drm/amd/dkms/m4/shmem-fs.m4 new file mode 100644 index 0000000000000..fa41d75272979 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/shmem-fs.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.2-rc4-463-gf01b2b3ed873 +dnl # shmem: add shmem_read_folio() and shmem_read_folio_gfp() +dnl # +AC_DEFUN([AC_AMDGPU_SHMEM_READ_FOLIO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + shmem_read_folio(NULL, 0); + ], [ + AC_DEFINE(HAVE_SHMEM_READ_FOLIO, 1, + [shmem_read_folio() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 2f31d6a8191f3..031c823e94bcd 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -23,5 +23,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_folio_backport.h b/include/kcl/kcl_folio_backport.h new file mode 100644 index 0000000000000..d21357052755e --- /dev/null +++ b/include/kcl/kcl_folio_backport.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_FOLIO_BACKPORT_H +#define _KCL_FOLIO_BACKPORT_H +#include + +#ifndef HAVE_SHMEM_READ_FOLIO + +#define folio page +#define folio_file_page(p, i) p +#define shmem_read_folio shmem_read_mapping_page +#define shmem_read_folio_gfp shmem_read_mapping_page_gfp +#define folio_lock lock_page +#define folio_unlock unlock_page +#define folio_mark_accessed mark_page_accessed +#define folio_mark_dirty set_page_dirty +#define folio_mapped page_mapcount +#define folio_clear_dirty_for_io clear_page_dirty_for_io +#define folio_set_reclaim SetPageReclaim +#define folio_clear_reclaim ClearPageReclaim +#define folio_test_writeback PageWriteback +#define folio_put put_page +#endif + +#endif From b19a9eeabb42182f927642dddb590614cd19c1ff Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 27 May 2025 10:31:33 +0800 Subject: [PATCH 1521/2653] drm/amdkcl: wrap code under amdkcl_ttm_resvp It's cause by the commit: 70d645deac98 "drm/ttm: Add helpers for shrinking" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index ccad3f82a2ec6..a1fc97706b95e 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -1096,7 +1096,7 @@ long ttm_bo_shrink(struct ttm_operation_ctx *ctx, struct ttm_buffer_object *bo, struct ttm_tt *tt = bo->ttm; long lret; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (flags.allow_move && bo->resource->mem_type != TTM_PL_SYSTEM) { int ret = ttm_bo_validate(bo, &sys_placement, ctx); From 345e65f5365961b6036317198e74ef7fd01b7fb2 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 27 May 2025 11:30:46 +0800 Subject: [PATCH 1522/2653] drm/amdkcl: include writeback.h for pre-v4.2 kernels ttm_backup.c requires struct writeback_control, but pre-v4.2 kernels lack the memcontrol.h -> writeback.h include path. Directly include writeback.h in backport.h to fix this. Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/ttm/backport/backport.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 031c823e94bcd..b5c736e2211d9 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -3,6 +3,7 @@ #define AMDTTM_BACKPORT_H #include +#include #include #include #include From bac2c19b4d79d0c5db5c2e6ac2b23b1d24567915 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 27 May 2025 13:15:01 +0800 Subject: [PATCH 1523/2653] drm/amdkcl: wrap code under HAVE_STRUCT_XARRAY It's caused by the commit: 61a039d1757b "drm/amdgpu: add initial support for sdma v6.0" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index c08e9a6cf6827..264d525325c21 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1656,16 +1656,30 @@ static int sdma_v6_0_process_fence_irq(struct amdgpu_device *adev, if (adev->enable_mes && doorbell_offset) { struct amdgpu_userq_fence_driver *fence_drv = NULL; +#ifdef HAVE_STRUCT_XARRAY struct xarray *xa = &adev->userq_xa; +#else + struct idr *idr = &adev->userq_idr; + struct spinlock_t *idr_lock = &adev->userq_lock; +#endif unsigned long flags; doorbell_offset >>= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(xa, flags); fence_drv = xa_load(xa, doorbell_offset); +#else + spin_lock_irqsave(idr_lock, flags); + fence_drv = idr_find(idr, doorbell_offset); +#endif if (fence_drv) amdgpu_userq_fence_driver_process(fence_drv); +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(xa, flags); +#else + spin_unlock_irqrestore(idr_lock, flags); +#endif } return 0; From bee1d70391458056aceef8c384a4732f2b0d9365 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 28 May 2025 15:24:28 +0800 Subject: [PATCH 1524/2653] drm/amdkcl: fix module build to adapt for kbuild It's caused by v6.9-rc5-21-gb1992c3772e6 "kbuild: use $(src) instead of $(srctree)/$(src) for source directory" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 56c0a7b960b45..6c65806847cd5 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -23,7 +23,7 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -FULL_AMD_PATH := $(patsubst %/amdgpu,%,$(src)) +FULL_AMD_PATH := $(src)/.. DISPLAY_FOLDER_NAME := display FULL_AMD_DISPLAY_PATH := $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME) From 892d1e3cc862b30cd99608352eb91be64892fc63 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 27 May 2025 09:30:31 +0800 Subject: [PATCH 1525/2653] drm/amdkcl: string objtool from cflags for conftest objtool is unnecessary for conftest. Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index 486bb816b43df..122ed7720922c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -3,13 +3,13 @@ dnl # extract cc, cflags, cppflags dnl # AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ AS_IF([test -s .conftest.o.cmd], [ - _conftest_cmd=$(head -1 .conftest.o.cmd) + _conftest_cmd=$(head -1 .conftest.o.cmd | sed 's/.*:= //;s/;.*//;s/^[[[:space:]]]*//') - CC=$(echo $_conftest_cmd | awk -F ' ' '{print $[3]}') + CC=$(echo $_conftest_cmd | awk -F ' ' '{print $[1]}') CPP="$CC -E" CFLAGS=$(echo $_conftest_cmd | \ - cut -d ' ' -f 4- | \ + cut -d ' ' -f 2- | \ sed -e "s|\./|${LINUX_OBJ}/|g" \ -e "s|-I\([[[a-z]]]*\)|-I${LINUX_OBJ}/\1|g" \ -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|g" \ @@ -17,7 +17,6 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ CFLAGS=$(echo $CFLAGS | sed -E 's/-W(array-bounds|error=array-bounds|unused-variable|error=unused-variable|unused-[^ ]*-variable|error=unused-[^ ]*-variable)( |$)//g') CPPFLAGS=$(echo $CFLAGS | \ - cut -d ';' -f 1 | \ sed 's| -|\n&|g' | \ sed -n -e '/conftest/d' \ -e '/KBUILD/d' \ From a6fa2cc3a1ae622d72a55f57a87ae799d95cbbe7 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 23 Mar 2025 13:43:43 +0800 Subject: [PATCH 1526/2653] drm/amdkcl: fake kunit_fail_current_test It's caused by v5.12-rc2-4-g359a376081d4 kunit: support failure from dynamic analysis tools Signed-off-by: Asher Song Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/Makefile.drm_buddy | 3 ++- drivers/gpu/drm/amd/dkms/backport_drm_buddy.h | 7 +++++++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/kunit/test-bug.h | 9 +++++++++ include/kcl/kcl_test-bug.h | 18 ++++++++++++++++++ 5 files changed, 41 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/backport_drm_buddy.h create mode 100644 include/kcl/header/kunit/test-bug.h create mode 100644 include/kcl/kcl_test-bug.h diff --git a/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy b/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy index 208c05b48758d..6af49f111bc9c 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy +++ b/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy @@ -1,6 +1,7 @@ export CONFIG_DRM_BUDDY=m subdir-ccflags-y += -DCONFIG_DRM_BUDDY -CFLAGS_drm_buddy.o += -DHAVE_CONFIG_H +CFLAGS_drm_buddy.o += -include $(src)/amd/dkms/backport_drm_buddy.h \ + -DHAVE_CONFIG_H amddrm_buddy-y := drm_buddy.o obj-$(CONFIG_DRM_BUDDY) += amddrm_buddy.o diff --git a/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h b/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h new file mode 100644 index 0000000000000..c5ccbc3a8741c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_BACKPORT_DRM_BUDDY_H +#define _KCL_BACKPORT_DRM_BUDDY_H + +#include + +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 7b6f715c04fa8..bf27afe78e544 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -174,4 +174,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #linux/compiler.h: Split into compiler.h and compiler_types.h dnl AC_KERNEL_CHECK_HEADERS([linux/compiler_types.h]) + + dnl #v5.12-rc2-4-g359a376081d4 + dnl #kunit: support failure from dynamic analysis tools + dnl + AC_KERNEL_CHECK_HEADERS([kunit/test-bug.h]) ]) diff --git a/include/kcl/header/kunit/test-bug.h b/include/kcl/header/kunit/test-bug.h new file mode 100644 index 0000000000000..5f0fde68c25c6 --- /dev/null +++ b/include/kcl/header/kunit/test-bug.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _KCL_HEADER_KUNIT_TEST_BUG_H_H +#define _KCL_HEADER_KUNIT_TEST_BUG_H_H + +#ifdef HAVE_KUNIT_TEST_BUG_H +#include_next +#endif + +#endif diff --git a/include/kcl/kcl_test-bug.h b/include/kcl/kcl_test-bug.h new file mode 100644 index 0000000000000..dad04656f158b --- /dev/null +++ b/include/kcl/kcl_test-bug.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * KUnit API providing hooks for non-test code to interact with tests. + * + * Copyright (C) 2020, Google LLC. + * Author: Uriel Guajardo + */ + +#ifndef _KCL_KUNIT_TEST_BUG_H +#define _KCL_KUNIT_TEST_BUG_H + +#include +#include + +#ifndef kunit_fail_current_test +#define kunit_fail_current_test(fmt, ...) do {} while (0) +#endif +#endif From bd71269e92e0ecd3314684eed0e1733d8412a274 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Tue, 3 Jun 2025 17:07:11 +0800 Subject: [PATCH 1527/2653] drm/amdkcl: wrap code under HAVE_STRUCT_XARRAY It's caused by 96236ac46 "drm/amdgpu: Add userq fence support to SDMAv7.0" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index ba1f3e3b6eb61..d12a496f7378b 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1580,16 +1580,28 @@ static int sdma_v7_0_process_fence_irq(struct amdgpu_device *adev, if (adev->enable_mes && doorbell_offset) { struct amdgpu_userq_fence_driver *fence_drv = NULL; +#ifdef HAVE_STRUCT_XARRAY struct xarray *xa = &adev->userq_xa; +#else + struct idr *idr = &adev->userq_idr; +#endif unsigned long flags; doorbell_offset >>= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(xa, flags); fence_drv = xa_load(xa, doorbell_offset); if (fence_drv) amdgpu_userq_fence_driver_process(fence_drv); xa_unlock_irqrestore(xa, flags); +#else + spin_lock_irqsave(&adev->userq_lock, flags); + fence_drv = idr_find(idr, doorbell_offset); + if (fence_drv) + amdgpu_userq_fence_driver_process(fence_drv); + spin_unlock_irqrestore(&adev->userq_lock, flags); +#endif } return 0; From 718f8958ae23175ca457bfb70593b070e5329483 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Wed, 4 Jun 2025 14:46:14 +0800 Subject: [PATCH 1528/2653] drm/amdkcl: test whether size_mul() exist It's caused by c72e473642e23d "drm/amdgpu: Fix integer overflow issues in amdgpu_userq_fence.c" Signed-off-by: Yang Su --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/overflow.m4 | 16 ++++++++++++++++ include/kcl/kcl_overflow.h | 9 +++++++++ 5 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/overflow.m4 create mode 100644 include/kcl/kcl_overflow.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a2ea8803ecf5e..8befd40c38c2b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -149,5 +149,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9607e58597801..1562cdabffa28 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1096,6 +1096,9 @@ /* smca_get_bank_type(x) is available */ /* #undef HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT */ +/* size_mul() is available */ +#define HAVE_SIZE_MUL 1 + /* whether smca_get_bank_type(x, x) is available */ #define HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9021e9a0e922f..af6c855b32281 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -274,6 +274,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_DEDUP_ARRAY AC_AMDGPU_DRM_FILE_ERR AC_AMDGPU_DRM_FILE_CLIENT_NAME + AC_AMDGPU_SIZE_MUL AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/overflow.m4 b/drivers/gpu/drm/amd/dkms/m4/overflow.m4 new file mode 100644 index 0000000000000..1e56299b3693f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/overflow.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.17-rc3-2-ge1be43d9b5d0 +dnl # overflow: Implement size_t saturating arithmetic helpers +dnl # +AC_DEFUN([AC_AMDGPU_SIZE_MUL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + size_mul(NULL, NULL); + ], [ + AC_DEFINE(HAVE_SIZE_MUL, 1, + [size_mul() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/include/kcl/kcl_overflow.h b/include/kcl/kcl_overflow.h new file mode 100644 index 0000000000000..6a0403d4c05ec --- /dev/null +++ b/include/kcl/kcl_overflow.h @@ -0,0 +1,9 @@ +#ifndef __KCL_LINUX_OVERFLOW_H +#define __KCL_LINUX_OVERFLOW_H + +#include + +#ifndef HAVE_SIZE_MUL +#define size_mul array_size +#endif +#endif From 4c3b810a6bc4baa8c5e821f49e6e3c15187ef582 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Tue, 10 Jun 2025 10:59:14 +0800 Subject: [PATCH 1529/2653] drm/amdkcl: fix size_mul() unused cause m4 detect fail size_mul is declared with __attribute__((warn_unused_result)), but it's not being used. use a size_t variable to store the size_mul() return value. It's caused by f73fa446f6e "drm/amdkcl: test whether size_mul() exist" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/overflow.m4 | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/overflow.m4 b/drivers/gpu/drm/amd/dkms/m4/overflow.m4 index 1e56299b3693f..7ee5a99374193 100644 --- a/drivers/gpu/drm/amd/dkms/m4/overflow.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/overflow.m4 @@ -7,7 +7,8 @@ AC_DEFUN([AC_AMDGPU_SIZE_MUL], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - size_mul(NULL, NULL); + size_t offset; + offset = size_mul(0, 0); ], [ AC_DEFINE(HAVE_SIZE_MUL, 1, [size_mul() is available]) From 037ef1e29cece1ba41c3819e9cba9bbd14d6883a Mon Sep 17 00:00:00 2001 From: Yang Su Date: Mon, 9 Jun 2025 16:06:45 +0800 Subject: [PATCH 1530/2653] drm/amdkcl: enable function get_brightness_range() It's caused by 5dd398e1c "drm/amd/display: Add debugging message for brightness caps" Signed-off-by: Yang Su Reviewed-by: Mario Limonciello Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 834c5e0bef9c7..32f43ba32be1c 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4811,26 +4811,29 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, #endif } -#ifdef HAVE_HDR_SINK_METADATA static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, unsigned int *min, unsigned int *max) { if (!caps) return 0; - +#ifdef HAVE_HDR_SINK_METADATA if (caps->aux_support) { // Firmware limits are in nits, DC API wants millinits. *max = 1000 * caps->aux_max_input_signal; *min = 1000 * caps->aux_min_input_signal; } else { +#endif // Firmware limits are 8-bit, PWM control is 16-bit. *max = 0x101 * caps->max_input_signal; *min = 0x101 * caps->min_input_signal; +#ifdef HAVE_HDR_SINK_METADATA } +#endif return 1; } /* Rescale from [min..max] to [0..MAX_BACKLIGHT_LEVEL] */ +#ifdef HAVE_HDR_SINK_METADATA static inline u32 scale_input_to_fw(int min, int max, u64 input) { return DIV_ROUND_CLOSEST_ULL(input * MAX_BACKLIGHT_LEVEL, max - min); From 172fa51c620e687a34a482e275c4e6d93cb15d83 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 6 Jun 2025 14:04:21 +0800 Subject: [PATCH 1531/2653] drm/amdkcl: fix drm_edid_is_valid const warning drm_edid_is_valid() need the non const parm, so update kcl drm_edid->edid. Signed-off-by: Bob Zhou Reviewed-by: Chengjun Yao --- include/kcl/kcl_drm_edid.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h index 05afadb754485..b992c2f76a6c5 100644 --- a/include/kcl/kcl_drm_edid.h +++ b/include/kcl/kcl_drm_edid.h @@ -29,7 +29,7 @@ struct drm_edid { /* Size allocated for edid */ size_t size; - const struct edid *edid; + struct edid *edid; }; #endif From b626bb71dfad43dd52b7fd33109b7876786e9ab7 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 19 Jun 2025 10:55:38 +0800 Subject: [PATCH 1532/2653] drm/amdkcl:test whether drm_crtc_helper_mode_valid_fixed() is available It's caused by 216b9bbaeaea9 "drm/probe-helper: Add drm_crtc_helper_mode_valid_fixed()" Signed-off-by: Yang Su Reviewed-by: Chengjun Yao --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_drm_probe_helper.c | 27 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm_probe_helper.m4 | 16 +++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_probe_helper.h | 17 ++++++++++++ 7 files changed, 66 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_probe_helper.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_probe_helper.m4 create mode 100644 include/kcl/kcl_drm_probe_helper.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 4e6e016e577ff..af911c325e4b9 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -17,7 +17,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o kcl_drm_drv.o \ - kcl_dma_fence_array.o kcl_dma_fence_unwrap.o + kcl_dma_fence_array.o kcl_dma_fence_unwrap.o kcl_drm_probe_helper.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o kcl_debugfs_file.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_probe_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_probe_helper.c new file mode 100644 index 0000000000000..9af3a1dd37f26 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_probe_helper.c @@ -0,0 +1,27 @@ +#include + +#ifndef HAVE_DRM_CRTC_HELPER_MODE_VALID_FIXED +/** + * drm_crtc_helper_mode_valid_fixed - Validates a display mode + * @crtc: the crtc + * @mode: the mode to validate + * @fixed_mode: the display hardware's mode + * + * Returns: + * MODE_OK on success, or another mode-status code otherwise. + */ +enum drm_mode_status kcl_drm_crtc_helper_mode_valid_fixed(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + const struct drm_display_mode *fixed_mode) +{ + if (mode->hdisplay != fixed_mode->hdisplay && mode->vdisplay != fixed_mode->vdisplay) + return MODE_ONE_SIZE; + else if (mode->hdisplay != fixed_mode->hdisplay) + return MODE_ONE_WIDTH; + else if (mode->vdisplay != fixed_mode->vdisplay) + return MODE_ONE_HEIGHT; + + return MODE_OK; +} +EXPORT_SYMBOL(kcl_drm_crtc_helper_mode_valid_fixed); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 8befd40c38c2b..c7d56a9eed36e 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -150,5 +150,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1562cdabffa28..72d686290d609 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -281,6 +281,9 @@ drm_atomic_state arg */ #define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE 1 +/* drm_crtc_helper_mode_valid_fixed() is available */ +#define HAVE_DRM_CRTC_HELPER_MODE_VALID_FIXED 1 + /* drm_dbg_printer() is available */ #define HAVE_DRM_DBG_PRINTER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_probe_helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_probe_helper.m4 new file mode 100644 index 0000000000000..12aea115000fb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_probe_helper.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.19-rc6-1875-g216b9bbaeaea +dnl # drm/probe-helper: Add drm_crtc_helper_mode_valid_fixed() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_MODE_VALID_FIXED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_crtc_helper_mode_valid_fixed(NULL, NULL, NULL); + ], [drm_crtc_helper_mode_valid_fixed], [drivers/gpu/drm/drm_probe_helper.c],[ + AC_DEFINE(HAVE_DRM_CRTC_HELPER_MODE_VALID_FIXED, 1, + [drm_crtc_helper_mode_valid_fixed() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index af6c855b32281..4bfac15b84c7f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -275,6 +275,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FILE_ERR AC_AMDGPU_DRM_FILE_CLIENT_NAME AC_AMDGPU_SIZE_MUL + AC_AMDGPU_DRM_CRTC_HELPER_MODE_VALID_FIXED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_probe_helper.h b/include/kcl/kcl_drm_probe_helper.h new file mode 100644 index 0000000000000..0b2fdfbe04a08 --- /dev/null +++ b/include/kcl/kcl_drm_probe_helper.h @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT + +#ifndef __KCL_DRM_PROBE_HELPER_H__ +#define __KCL_DRM_PROBE_HELPER_H__ + +#ifndef HAVE_DRM_CRTC_HELPER_MODE_VALID_FIXED +#include +#include +#include + +enum drm_mode_status kcl_drm_crtc_helper_mode_valid_fixed(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + const struct drm_display_mode *fixed_mode); + +#define drm_crtc_helper_mode_valid_fixed kcl_drm_crtc_helper_mode_valid_fixed +#endif +#endif From 64c70a94bceb529ee2cf30c9007ce88a2491aa71 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Wed, 18 Jun 2025 22:14:00 -0400 Subject: [PATCH 1533/2653] drm/amdgpu: Set HDP_MMHUB_RO_OVERRIDE Set HDP_MMHUB_CNTL.HDP_MMHUB_RO_OVERRIDE = 0x0 for gfx943 dGPU. This is needed for enhanced RCCL performance v2: Set the register only if not already set Signed-off-by: Harish Kasiviswanathan Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c index e6c0d86d34865..239b3c8b1237b 100644 --- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c @@ -36,6 +36,9 @@ #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0 +#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_OVERRIDE_MASK 0x00000010L +#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_OVERRIDE__SHIFT 0x4 + static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) { @@ -136,6 +139,9 @@ static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev, static void hdp_v4_0_init_registers(struct amdgpu_device *adev) { + uint32_t aid_mask = adev->aid_mask; + u32 tmp, i; + switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { case IP_VERSION(4, 2, 1): WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1); @@ -152,6 +158,17 @@ static void hdp_v4_0_init_registers(struct amdgpu_device *adev) if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0)) WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2); + else if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2) && + !adev->gmc.is_app_apu) { + for_each_inst(i, aid_mask) { + tmp = RREG32_SOC15(HDP, GET_INST(HDP, i), mmHDP_MMHUB_CNTL); + if (tmp & HDP_MMHUB_CNTL__HDP_MMHUB_RO_OVERRIDE_MASK ) { + tmp = REG_SET_FIELD(tmp, HDP_MMHUB_CNTL, HDP_MMHUB_RO_OVERRIDE, 0); + WREG32_SOC15(HDP, GET_INST(HDP, i), mmHDP_MMHUB_CNTL, tmp); + } + } + + } WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); From 2d02f59331746196e3ada849587b5fae161ce39b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 24 Jun 2025 17:00:15 +0800 Subject: [PATCH 1534/2653] drm/amdkcl: fake macro funciton timer_container_of() It's caused by 41cb08555c4164996d67c78b3bf1c658075b75f1 "treewide, timers: Rename from_timer() to timer_container_of()" Signed-off-by: Bob Zhou --- include/kcl/kcl_time.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_time.h b/include/kcl/kcl_time.h index 89856adc192a5..cf6a011f8ffbb 100644 --- a/include/kcl/kcl_time.h +++ b/include/kcl/kcl_time.h @@ -10,4 +10,9 @@ void time64_to_tm(time64_t totalsecs, int offset, struct tm *result); #endif +#ifndef timer_container_of +#define timer_container_of(var, callback_timer, timer_fieldname) \ + container_of(callback_timer, typeof(*var), timer_fieldname) +#endif + #endif /* _KCL_TIME_H */ From 0d4f07f07e006bd68f9938e5e63e4d46a94043dd Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 25 Jun 2025 10:29:44 +0800 Subject: [PATCH 1535/2653] drm/amdkcl: detect bin_attribute.read is const args It's casued by v6.15-rc1-7-g97d06802d10a sysfs: constify bin_attribute argument of bin_attribute::read/write() Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 9 +++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++++ .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 8 ++++++++ .../drm/amd/dkms/m4/bin_attr_const_read.m4 | 20 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 6 files changed, 46 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/bin_attr_const_read.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 503db577bce0e..64bfc04d17cea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -249,7 +249,11 @@ static void amdgpu_device_attr_sysfs_fini(struct amdgpu_device *adev) } static ssize_t amdgpu_sysfs_reg_state_get(struct file *f, struct kobject *kobj, +#ifdef HAVE_BIN_ATTR_CONST_ARGS const struct bin_attribute *attr, char *buf, +#else + struct bin_attribute *attr, char *buf, +#endif loff_t ppos, size_t count) { struct device *dev = kobj_to_dev(kobj); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 76b8f616aaa37..a7cc90973d26c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -4160,8 +4160,13 @@ int is_psp_fw_valid(struct psp_bin_desc bin) } static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, +#ifdef HAVE_BIN_ATTR_CONST_ARGS const struct bin_attribute *bin_attr, +#else + struct bin_attribute *bin_attr, +#endif char *buffer, loff_t pos, size_t count) + { struct device *dev = kobj_to_dev(kobj); struct drm_device *ddev = dev_get_drvdata(dev); @@ -4196,7 +4201,11 @@ static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, } static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, +#ifdef HAVE_BIN_ATTR_CONST_ARGS const struct bin_attribute *bin_attr, char *buffer, +#else + struct bin_attribute *bin_attr, char *buffer, +#endif loff_t pos, size_t count) { struct device *dev = kobj_to_dev(kobj); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 2ed3059a92a58..7b20972058d1f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1796,7 +1796,11 @@ static char *amdgpu_ras_badpage_flags_str(unsigned int flags) */ static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, +#ifdef HAVE_BIN_ATTR_CONST_ARGS struct kobject *kobj, const struct bin_attribute *attr, +#else + struct kobject *kobj, struct bin_attribute *attr, +#endif char *buf, loff_t ppos, size_t count) { struct amdgpu_ras *con = diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index e4aa129d14b8d..c8934bdbd71a1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -648,7 +648,11 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) * incorrect/corrupted and we should correct our SRM by getting it from PSP */ static ssize_t srm_data_write(struct file *filp, struct kobject *kobj, +#ifdef HAVE_BIN_ATTR_CONST_ARGS const struct bin_attribute *bin_attr, char *buffer, +#else + struct bin_attribute *bin_attr, char *buffer, +#endif loff_t pos, size_t count) { struct hdcp_workqueue *work; @@ -672,7 +676,11 @@ static ssize_t srm_data_write(struct file *filp, struct kobject *kobj, } static ssize_t srm_data_read(struct file *filp, struct kobject *kobj, +#ifdef HAVE_BIN_ATTR_CONST_ARGS const struct bin_attribute *bin_attr, char *buffer, +#else + struct bin_attribute *bin_attr, char *buffer, +#endif loff_t pos, size_t count) { struct hdcp_workqueue *work; diff --git a/drivers/gpu/drm/amd/dkms/m4/bin_attr_const_read.m4 b/drivers/gpu/drm/amd/dkms/m4/bin_attr_const_read.m4 new file mode 100644 index 0000000000000..555b5b4729a0a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/bin_attr_const_read.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit v6.15-rc1-7-g97d06802d10a +dnl # sysfs: constify bin_attribute argument of bin_attribute::read/write() +dnl # +AC_DEFUN([AC_AMDGPU_BIN_ATTR_CONST_ARGS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ssize_t (*p)(struct file *, struct kobject *, const struct bin_attribute *, + char *, loff_t, size_t) = NULL; + + struct bin_attribute bin_attr; + bin_attr.read = p; + ], [ + AC_DEFINE(HAVE_BIN_ATTR_CONST_ARGS, 1, + [bin_attribute.read is const args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4bfac15b84c7f..b39ff7ab2921b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -276,6 +276,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FILE_CLIENT_NAME AC_AMDGPU_SIZE_MUL AC_AMDGPU_DRM_CRTC_HELPER_MODE_VALID_FIXED + AC_AMDGPU_BIN_ATTR_CONST_ARGS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 54bc1860735c00a8be56ae3d6d0b3b0a5a69a91a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 25 Jun 2025 11:07:12 +0800 Subject: [PATCH 1536/2653] drm/amdkcl: test if drmm_cgroup_register_region() is available It's caused by 1b5447d773d461b670f29af7c5a9091cff915259 "drm/amdgpu: Add cgroups implementation" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 2 ++ .../amd/dkms/m4/drmm_cgroup_register_region.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 19 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drmm_cgroup_register_region.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 168dea1eef0e5..16aef2da3b4df 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -976,9 +976,11 @@ int amdgpu_vram_mgr_init(struct amdgpu_device *adev) int ret; #endif +#ifdef HAVE_DRMM_CGROUP_REGISTER_REGION man->cg = drmm_cgroup_register_region(adev_to_drm(adev), "vram", adev->gmc.real_vram_size); if (IS_ERR(man->cg)) return PTR_ERR(man->cg); +#endif ttm_resource_manager_init(man, &adev->mman.bdev, adev->gmc.real_vram_size); diff --git a/drivers/gpu/drm/amd/dkms/m4/drmm_cgroup_register_region.m4 b/drivers/gpu/drm/amd/dkms/m4/drmm_cgroup_register_region.m4 new file mode 100644 index 0000000000000..37cc1db772586 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drmm_cgroup_register_region.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.13-rc6-2-g7b0af165e2d4 +dnl # drm/drv: Add drmm managed registration helper for dmem cgroups. +dnl # +AC_DEFUN([AC_AMDGPU_DRMM_CGROUP_REGISTER_REGION], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drmm_cgroup_register_region(NULL,NULL,0); + ],[drmm_cgroup_register_region], [drivers/gpu/drm/drm_drv.c],[ + AC_DEFINE(HAVE_DRMM_CGROUP_REGISTER_REGION, 1, + [drmm_cgroup_register_region() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b39ff7ab2921b..664da2fe07b4e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -277,6 +277,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SIZE_MUL AC_AMDGPU_DRM_CRTC_HELPER_MODE_VALID_FIXED AC_AMDGPU_BIN_ATTR_CONST_ARGS + AC_AMDGPU_DRMM_CGROUP_REGISTER_REGION AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 40a094dca9769e2d26865d2e5ac3a375e521dce7 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 25 Jun 2025 10:45:34 +0800 Subject: [PATCH 1537/2653] drm/amdkcl: test if attribute_group.bin_attrs_new is available It's caused by 2d0f5001b61c4831d413d12c10caed0e99d73b25 "drm/amdgpu: Constify 'struct bin_attribute'" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 8 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 8 ++++++++ .../dkms/m4/attribute-group-bin-attrs-new.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/attribute-group-bin-attrs-new.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index a7cc90973d26c..c32a32c6eb28f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -4288,7 +4288,11 @@ static ssize_t amdgpu_psp_vbflash_status(struct device *dev, } static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); +#ifdef HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW static const struct bin_attribute *const bin_flash_attrs[] = { +#else +static struct bin_attribute *bin_flash_attrs[] = { +#endif &psp_vbflash_bin_attr, NULL }; @@ -4329,7 +4333,11 @@ static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, const struct attribute_group amdgpu_flash_attr_group = { .attrs = flash_attrs, +#ifdef HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW .bin_attrs_new = bin_flash_attrs, +#else + .bin_attrs = bin_flash_attrs, +#endif #ifdef HAVE_ATTRIBUTE_GROUP_IS_BIN_VISIBLE .is_bin_visible = amdgpu_bin_flash_attr_is_visible, #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 7b20972058d1f..6abc3e59f933f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2158,7 +2158,11 @@ static int amdgpu_ras_fs_init(struct amdgpu_device *adev) &con->event_state_attr.attr, NULL }; +#ifdef HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW const struct bin_attribute *bin_attrs[] = { +#else + struct bin_attribute *bin_attrs[] = { +#endif NULL, NULL, }; @@ -2187,7 +2191,11 @@ static int amdgpu_ras_fs_init(struct amdgpu_device *adev) con->badpages_attr = bin_attr_gpu_vram_bad_pages; sysfs_bin_attr_init(&con->badpages_attr); bin_attrs[0] = &con->badpages_attr; +#ifdef HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW group.bin_attrs_new = bin_attrs; +#else + group.bin_attrs = bin_attrs; +#endif } r = sysfs_create_group(&adev->dev->kobj, &group); diff --git a/drivers/gpu/drm/amd/dkms/m4/attribute-group-bin-attrs-new.m4 b/drivers/gpu/drm/amd/dkms/m4/attribute-group-bin-attrs-new.m4 new file mode 100644 index 0000000000000..fea21d6061bb5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/attribute-group-bin-attrs-new.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.12-rc6-31-g906c508afdca +dnl # sysfs: attribute_group: allow registration of const bin_attribute +dnl # +AC_DEFUN([AC_AMDGPU_ATTRIBUTE_GROUP_BIN_ATTRS_NEW], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct attribute_group group; + group.bin_attrs_new = NULL; + ], [ + AC_DEFINE(HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW, 1, + [attribute_group.bin_attrs_new is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 664da2fe07b4e..72dda0f6fcb31 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -278,6 +278,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CRTC_HELPER_MODE_VALID_FIXED AC_AMDGPU_BIN_ATTR_CONST_ARGS AC_AMDGPU_DRMM_CGROUP_REGISTER_REGION + AC_AMDGPU_ATTRIBUTE_GROUP_BIN_ATTRS_NEW AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From e74b59abee374137308d93ecb6daaf8070aefb3d Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 25 Jun 2025 14:11:43 +0800 Subject: [PATCH 1538/2653] drm/amdkcl: test if bin_attribute.read_new is available It's caused by 2d0f5001b61c4831d413d12c10caed0e99d73b25 "drm/amdgpu: Constify 'struct bin_attribute'" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 9 +++++-- .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 9 +++++-- .../drm/amd/dkms/m4/bin_attr_const_read.m4 | 26 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 4 files changed, 41 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index c32a32c6eb28f..26be425de4351 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -4160,7 +4160,7 @@ int is_psp_fw_valid(struct psp_bin_desc bin) } static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, -#ifdef HAVE_BIN_ATTR_CONST_ARGS +#if defined(HAVE_BIN_ATTRIBUTE_READ_NEW) || defined(HAVE_BIN_ATTR_CONST_ARGS) const struct bin_attribute *bin_attr, #else struct bin_attribute *bin_attr, @@ -4201,7 +4201,7 @@ static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, } static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, -#ifdef HAVE_BIN_ATTR_CONST_ARGS +#if defined(HAVE_BIN_ATTRIBUTE_READ_NEW) || defined(HAVE_BIN_ATTR_CONST_ARGS) const struct bin_attribute *bin_attr, char *buffer, #else struct bin_attribute *bin_attr, char *buffer, @@ -4260,8 +4260,13 @@ static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, static const struct bin_attribute psp_vbflash_bin_attr = { .attr = {.name = "psp_vbflash", .mode = 0660}, .size = 0, +#ifdef HAVE_BIN_ATTRIBUTE_READ_NEW .write_new = amdgpu_psp_vbflash_write, .read_new = amdgpu_psp_vbflash_read, +#else + .write = amdgpu_psp_vbflash_write, + .read = amdgpu_psp_vbflash_read, +#endif }; /** diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index c8934bdbd71a1..9e3e2291afe8f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -648,7 +648,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) * incorrect/corrupted and we should correct our SRM by getting it from PSP */ static ssize_t srm_data_write(struct file *filp, struct kobject *kobj, -#ifdef HAVE_BIN_ATTR_CONST_ARGS +#if defined(HAVE_BIN_ATTRIBUTE_READ_NEW) || defined(HAVE_BIN_ATTR_CONST_ARGS) const struct bin_attribute *bin_attr, char *buffer, #else struct bin_attribute *bin_attr, char *buffer, @@ -676,7 +676,7 @@ static ssize_t srm_data_write(struct file *filp, struct kobject *kobj, } static ssize_t srm_data_read(struct file *filp, struct kobject *kobj, -#ifdef HAVE_BIN_ATTR_CONST_ARGS +#if defined(HAVE_BIN_ATTRIBUTE_READ_NEW) || defined(HAVE_BIN_ATTR_CONST_ARGS) const struct bin_attribute *bin_attr, char *buffer, #else struct bin_attribute *bin_attr, char *buffer, @@ -740,8 +740,13 @@ static ssize_t srm_data_read(struct file *filp, struct kobject *kobj, static const struct bin_attribute data_attr = { .attr = {.name = "hdcp_srm", .mode = 0664}, .size = PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE, /* Limit SRM size */ +#ifdef HAVE_BIN_ATTRIBUTE_READ_NEW .write_new = srm_data_write, .read_new = srm_data_read, +#else + .write = srm_data_write, + .read = srm_data_read, +#endif }; struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/dkms/m4/bin_attr_const_read.m4 b/drivers/gpu/drm/amd/dkms/m4/bin_attr_const_read.m4 index 555b5b4729a0a..85dc8be49b063 100644 --- a/drivers/gpu/drm/amd/dkms/m4/bin_attr_const_read.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/bin_attr_const_read.m4 @@ -18,3 +18,29 @@ AC_DEFUN([AC_AMDGPU_BIN_ATTR_CONST_ARGS], [ ]) ]) ]) + +dnl # +dnl # commit v6.12-rc6-20-geb2e6c3a8d66 +dnl # sysfs: bin_attribute: add const read/write callback variants +dnl # +AC_DEFUN([AC_AMDGPU_BIN_ATTRIBUTE_READ_NEW], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ssize_t (*p)(struct file *, struct kobject *, const struct bin_attribute *, + char *, loff_t, size_t) = NULL; + + struct bin_attribute bin_attr; + bin_attr.read_new = p; + ], [ + AC_DEFINE(HAVE_BIN_ATTRIBUTE_READ_NEW, 1, + [bin_attribute.read_new is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_BIN_ATTRIBUTE], [ + AC_AMDGPU_BIN_ATTR_CONST_ARGS + AC_AMDGPU_BIN_ATTRIBUTE_READ_NEW +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 72dda0f6fcb31..ceeb1bc965a50 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -276,7 +276,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FILE_CLIENT_NAME AC_AMDGPU_SIZE_MUL AC_AMDGPU_DRM_CRTC_HELPER_MODE_VALID_FIXED - AC_AMDGPU_BIN_ATTR_CONST_ARGS + AC_AMDGPU_BIN_ATTRIBUTE AC_AMDGPU_DRMM_CGROUP_REGISTER_REGION AC_AMDGPU_ATTRIBUTE_GROUP_BIN_ATTRS_NEW From d87d43dc3076a6db7540708a07dcd2494e141bdb Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 25 Jun 2025 14:27:16 +0800 Subject: [PATCH 1539/2653] drm/amdkcl: test if hrtimer_setup() is available It's caused by 690d59fee83cb0f45fae21ce3aed2b335c87c1c2 "drm/amdgpu: Switch to use hrtimer_setup()" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 5 +++++ drivers/gpu/drm/amd/dkms/m4/hrtimer_setup.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 22 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/hrtimer_setup.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 03aa0b8405733..24c1f8575298f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -201,8 +201,13 @@ static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, amdgpu_crtc->connector = NULL; amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE; +#ifdef HAVE_HRTIMER_SETUP hrtimer_setup(&amdgpu_crtc->vblank_timer, &amdgpu_vkms_vblank_simulate, CLOCK_MONOTONIC, HRTIMER_MODE_REL); +#else + hrtimer_init(&amdgpu_crtc->vblank_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + amdgpu_crtc->vblank_timer.function = &amdgpu_vkms_vblank_simulate; +#endif return ret; } diff --git a/drivers/gpu/drm/amd/dkms/m4/hrtimer_setup.m4 b/drivers/gpu/drm/amd/dkms/m4/hrtimer_setup.m4 new file mode 100644 index 0000000000000..456d238010a25 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/hrtimer_setup.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.12-rc1-119-g908a1d775422 +dnl # hrtimers: Introduce hrtimer_setup() to replace hrtimer_init() +dnl # +AC_DEFUN([AC_AMDGPU_HRTIMER_SETUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + hrtimer_setup(NULL,NULL,0,0); + ],[hrtimer_setup], [kernel/time/hrtimer.c],[ + AC_DEFINE(HAVE_HRTIMER_SETUP, 1, + [hrtimer_setup() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ceeb1bc965a50..099da0a36faff 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -279,6 +279,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_BIN_ATTRIBUTE AC_AMDGPU_DRMM_CGROUP_REGISTER_REGION AC_AMDGPU_ATTRIBUTE_GROUP_BIN_ATTRS_NEW + AC_AMDGPU_HRTIMER_SETUP AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 3b37f505cc15ada5db88c8e32d3d43cf737d9980 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 25 Jun 2025 15:23:46 +0800 Subject: [PATCH 1540/2653] drm/amdkcl: test if ratelimit_state_reset_interval() is available It's caused by c6f7f1b2c0ff46b9069a8fbc7d167c9ead66dfce "drm/amd/pm: Avoid open-coded use of ratelimit_state structure's internals" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../dkms/m4/ratelimit_state_reset_interval.m4 | 16 ++++++++++ include/kcl/kcl_ratelimit.h | 30 +++++++++++++++++++ 4 files changed, 48 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ratelimit_state_reset_interval.m4 create mode 100644 include/kcl/kcl_ratelimit.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index c7d56a9eed36e..731c215f4874b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -151,5 +151,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 099da0a36faff..5a0a50a76d130 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -280,6 +280,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRMM_CGROUP_REGISTER_REGION AC_AMDGPU_ATTRIBUTE_GROUP_BIN_ATTRS_NEW AC_AMDGPU_HRTIMER_SETUP + AC_AMDGPU_RATELIMIT_STATE_RESET_INTERVAL AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/ratelimit_state_reset_interval.m4 b/drivers/gpu/drm/amd/dkms/m4/ratelimit_state_reset_interval.m4 new file mode 100644 index 0000000000000..bc80daac823ac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ratelimit_state_reset_interval.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.15-rc1-1-g56a7b9f8b059 +dnl # ratelimit: Create functions to handle ratelimit_state internals +dnl # +AC_DEFUN([AC_AMDGPU_RATELIMIT_STATE_RESET_INTERVAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ratelimit_state_reset_interval(NULL,0); + ],[ + AC_DEFINE(HAVE_RATELIMIT_STATE_RESET_INTERVAL, 1, + [ratelimit_state_reset_interval() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_ratelimit.h b/include/kcl/kcl_ratelimit.h new file mode 100644 index 0000000000000..29a8aaf9885d6 --- /dev/null +++ b/include/kcl/kcl_ratelimit.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_RATELIMIT_H +#define AMDKCL_RATELIMIT_H + +#include + +#ifndef HAVE_RATELIMIT_STATE_RESET_INTERVAL + +static inline int ratelimit_state_reset_miss(struct ratelimit_state *rs) +{ + int ret = rs->missed; + + rs->missed = 0; + return ret; +} + +static inline void ratelimit_state_reset_interval(struct ratelimit_state *rs, int interval_init) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&rs->lock, flags); + rs->interval = interval_init; + rs->begin = 0; + rs->printed = 0; + ratelimit_state_reset_miss(rs); + raw_spin_unlock_irqrestore(&rs->lock, flags); +} +#endif + +#endif From 4ea58dfe4da91af11f9cb7f623137d072559dd1a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 25 Jun 2025 17:11:33 +0800 Subject: [PATCH 1541/2653] drm/amdkcl: wrap code out of HAVE_DRM_DP_MST_EDID_READ It's caused by 880ab14a4acace958eaaf780231ca3f60454f718 "drm/amd/display: convert more DRM_ERROR to drm_err" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 32f43ba32be1c..479ae6505c4be 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7602,10 +7602,10 @@ static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct dc_link *dc_link = aconnector->dc_link; struct dc_sink *dc_em_sink = aconnector->dc_em_sink; + struct drm_device *dev = connector->dev; #ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid; struct i2c_adapter *ddc; - struct drm_device *dev = connector->dev; if (dc_link && dc_link->aux_mode) ddc = &aconnector->dm_dp_aux.aux.ddc; From 42417a946c88104e7909537c9fef006b4775b3bb Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 26 Jun 2025 13:16:24 +0800 Subject: [PATCH 1542/2653] drm/amdkcl: wrap code under macro HAVE_STRUCT_XARRAY Introduce macro HAVE_STRUCT_XARRAY to wrap code related to struct xarray, improving modularity and compatibility with different kernel configurations. Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index 8ad81a9cd4ef1..bac31cbb07ebe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -54,7 +54,11 @@ static const guid_t amd_xcc_dsm_guid = GUID_INIT(0x8267f5d5, 0xa556, 0x44f2, #define AMD_XCC_MAX_HID 24 +#ifdef HAVE_STRUCT_XARRAY struct xarray numa_info_xa; +#else +struct idr numa_info_idr; +#endif /* Encapsulates the XCD acpi object information */ struct amdgpu_acpi_xcc_info { @@ -879,7 +883,11 @@ static struct amdgpu_numa_info *amdgpu_acpi_get_numa_info(uint32_t pxm) struct amdgpu_numa_info *numa_info; int nid; +#ifdef HAVE_STRUCT_XARRAY numa_info = xa_load(&numa_info_xa, pxm); +#else + numa_info = idr_find(&numa_info_idr, pxm); +#endif if (!numa_info) { struct sysinfo info; @@ -898,7 +906,11 @@ static struct amdgpu_numa_info *amdgpu_acpi_get_numa_info(uint32_t pxm) } else { numa_info->size = amdgpu_acpi_get_numa_size(nid); } +#ifdef HAVE_STRUCT_XARRAY xa_store(&numa_info_xa, numa_info->pxm, numa_info, GFP_KERNEL); +#else + idr_alloc(&numa_info_idr, numa_info, numa_info->pxm, numa_info->pxm + 1, GFP_KERNEL); +#endif } return numa_info; @@ -1100,8 +1112,11 @@ static int amdgpu_acpi_enumerate_xcc(void) u32 sbdf; INIT_LIST_HEAD(&amdgpu_acpi_dev_list); +#ifdef HAVE_STRUCT_XARRAY xa_init(&numa_info_xa); - +#else + idr_init(&numa_info_idr); +#endif for (id = 0; id < AMD_XCC_MAX_HID; id++) { sprintf(hid, "%s%d", "AMD", AMD_XCC_HID_START + id); acpi_dev = acpi_dev_get_first_match_dev(hid, NULL, -1); @@ -1461,10 +1476,17 @@ void amdgpu_acpi_release(void) struct amdgpu_numa_info *numa_info; unsigned long index; +#ifdef HAVE_STRUCT_XARRAY xa_for_each(&numa_info_xa, index, numa_info) { kfree(numa_info); xa_erase(&numa_info_xa, index); } +#else + idr_for_each_entry(&numa_info_idr, numa_info, index) { + kfree(numa_info); + idr_remove(&numa_info_idr, index); + } +#endif if (list_empty(&amdgpu_acpi_dev_list)) return; From a95b02781fcea48f8fe54425174469f4fd5b73b8 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 26 Jun 2025 13:20:10 +0800 Subject: [PATCH 1543/2653] drm/amdkcl: fake acpi_dev_put() Introduces a static inline function `acpi_dev_put` to handle ACPI device reference release. Signed-off-by: Bob Zhou --- include/kcl/kcl_acpi.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/kcl/kcl_acpi.h b/include/kcl/kcl_acpi.h index 4ad8d53bf3cec..9db57f1252d5b 100644 --- a/include/kcl/kcl_acpi.h +++ b/include/kcl/kcl_acpi.h @@ -29,6 +29,7 @@ acpi_dev_get_first_match_dev(const char *hid, const char *uid, s64 hrv) { return NULL; } +static inline void acpi_dev_put(struct acpi_device *adev) {} #endif #endif /* AMDKCL_ACPI_H */ From 08650e54c781e51996cdb08d3de707b8250a6401 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 26 Jun 2025 14:09:59 +0800 Subject: [PATCH 1544/2653] drm/amdkcl: rename timer_delete* to del_timer* It's caused by 8fa7292fee5c5240402371ea89ab285ec856c916 "treewide: Switch/rename to timer_delete[_sync]()" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/timer_delete.m4 | 16 ++++++++++++++++ include/kcl/kcl_time.h | 7 +++++++ 3 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/timer_delete.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5a0a50a76d130..5eb12cb6de022 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -281,6 +281,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ATTRIBUTE_GROUP_BIN_ATTRS_NEW AC_AMDGPU_HRTIMER_SETUP AC_AMDGPU_RATELIMIT_STATE_RESET_INTERVAL + AC_AMDGPU_TIMER_DELETE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/timer_delete.m4 b/drivers/gpu/drm/amd/dkms/m4/timer_delete.m4 new file mode 100644 index 0000000000000..9f9ba523b4a56 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/timer_delete.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.1-rc1-12-gbb663f0f3c39 +dnl # timers: Rename del_timer() to timer_delete() +dnl # +AC_DEFUN([AC_AMDGPU_TIMER_DELETE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + timer_delete(NULL); + ],[ + AC_DEFINE(HAVE_TIMER_DELETE, 1, + [timer_delete() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_time.h b/include/kcl/kcl_time.h index cf6a011f8ffbb..ec7f479add4cf 100644 --- a/include/kcl/kcl_time.h +++ b/include/kcl/kcl_time.h @@ -5,6 +5,7 @@ #include #include #include +#include #ifndef HAVE_TIME64_TO_TM void time64_to_tm(time64_t totalsecs, int offset, struct tm *result); @@ -15,4 +16,10 @@ void time64_to_tm(time64_t totalsecs, int offset, struct tm *result); container_of(callback_timer, typeof(*var), timer_fieldname) #endif +#ifndef HAVE_TIMER_DELETE +#define timer_delete del_timer +#define timer_delete_sync del_timer_sync +#endif + + #endif /* _KCL_TIME_H */ From a2739899da5767888de23a00ac03236726acad1e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 26 Jun 2025 14:35:49 +0800 Subject: [PATCH 1545/2653] drm/amdkcl: test if irq_domain_create_linear() is available It's caused by 493e1092676257b81be4c013405f1271497a0ed1 "gpu: Switch to irq_domain_create_linear()" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../drm/amd/dkms/m4/irq_domain_create_linear.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_irq.h | 12 ++++++++++++ 4 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/irq_domain_create_linear.m4 create mode 100644 include/kcl/kcl_irq.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 731c215f4874b..de90ff15e4c9e 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -152,5 +152,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/irq_domain_create_linear.m4 b/drivers/gpu/drm/amd/dkms/m4/irq_domain_create_linear.m4 new file mode 100644 index 0000000000000..5895d5df2f8f0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/irq_domain_create_linear.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v4.3-rc5-47-g1bf4ddc46c5d +dnl # irqdomain: Introduce irq_domain_create_{linear, tree} +dnl # +AC_DEFUN([AC_AMDGPU_IRQ_DOMAIN_CREATE_LINEAR], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + irq_domain_create_linear(NULL, 0, NULL, NULL); + ],[ + AC_DEFINE(HAVE_IRQ_DOMAIN_CREATE_LINEAR, 1, + [irq_domain_create_linear() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5eb12cb6de022..7068f87de8b48 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -282,6 +282,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_HRTIMER_SETUP AC_AMDGPU_RATELIMIT_STATE_RESET_INTERVAL AC_AMDGPU_TIMER_DELETE + AC_AMDGPU_IRQ_DOMAIN_CREATE_LINEAR AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_irq.h b/include/kcl/kcl_irq.h new file mode 100644 index 0000000000000..09c603eeb6611 --- /dev/null +++ b/include/kcl/kcl_irq.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMDKCL_IRQ_H +#define AMDKCL_IRQ_H + +#include + +#ifndef HAVE_IRQ_DOMAIN_CREATE_LINEAR +#define irq_domain_create_linear irq_domain_add_linear +#endif /* HAVE_IRQ_DOMAIN_CREATE_LINEAR */ + +#endif From 96be5259f4b5a352b4eb66559fdee01ff39c7f8f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 26 Jun 2025 14:47:18 +0800 Subject: [PATCH 1546/2653] drm/amdkcl: wrap code under amdkcl_ttm_resvp It's caused by 44cfdf368fb72c03e4137709803d58288a22cb06 "drm/amdgpu: resume gfx userqueues" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 2d6ebd238d73d..bceb284358aef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -674,7 +674,7 @@ amdgpu_userq_validate_bos(struct amdgpu_userq_mgr *uq_mgr) while (!list_empty(&vm->invalidated)) { bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, base.vm_status); - resv = bo_va->base.bo->tbo.base.resv; + resv = amdkcl_ttm_resvp(&bo_va->base.bo->tbo); spin_unlock(&vm->status_lock); bo = bo_va->base.bo; From be43991914e91cdef72550040fee34c83236802b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 26 Jun 2025 15:01:49 +0800 Subject: [PATCH 1547/2653] amd/amdkcl: test shmem_writeout() is available It's caused by fe75adffac33eeb167b378861d80c805b234495c "ttm: Call shmem_writeout() from ttm_backup_backup_page()" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 | 16 ++++++++++++++++ drivers/gpu/drm/ttm/ttm_backup.c | 4 ++++ 3 files changed, 21 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7068f87de8b48..ee24c1243d5d2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -283,6 +283,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_RATELIMIT_STATE_RESET_INTERVAL AC_AMDGPU_TIMER_DELETE AC_AMDGPU_IRQ_DOMAIN_CREATE_LINEAR + AC_AMDGPU_SHMEM_WRITEOUT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 b/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 new file mode 100644 index 0000000000000..92f9099fb34e0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.15-rc1-5-g7b73c12c6ebf +dnl # shmem: Add shmem_writeout() +dnl # +AC_DEFUN([AC_AMDGPU_SHMEM_WRITEOUT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + shmem_writeout(NULL, NULL); + ],[shmem_writeout], [mm/shmem.c],[ + AC_DEFINE(HAVE_SHMEM_WRITEOUT, 1, + [shmem_writeout() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/ttm_backup.c b/drivers/gpu/drm/ttm/ttm_backup.c index cb1b8e5dadf56..703fd1427423f 100644 --- a/drivers/gpu/drm/ttm/ttm_backup.c +++ b/drivers/gpu/drm/ttm/ttm_backup.c @@ -122,7 +122,11 @@ ttm_backup_backup_page(struct file *backup, struct page *page, .for_reclaim = 1, }; folio_set_reclaim(to_folio); +#ifdef HAVE_SHMEM_WRITEOUT ret = shmem_writeout(to_folio, &wbc); +#else + ret = mapping->a_ops->writepage(folio_file_page(to_folio, idx), &wbc); +#endif if (!folio_test_writeback(to_folio)) folio_clear_reclaim(to_folio); /* From bb6320f70d1f0fbbf72f9cf70517d67b7584e169 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 2 Jul 2025 17:09:04 +0800 Subject: [PATCH 1548/2653] drm/amdkcl: modify autoconf to check drm_client_setup symbol Some distro system disable drm_client_setup symbol, so that dev/fb0 file node will be close. Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/drm-client.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 index 2c58adc325572..8dcc7e1ef03ee 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 @@ -4,7 +4,7 @@ dnl # drm: Add client-agnostic setup helper dnl # AC_DEFUN([AC_AMDGPU_DRM_CLIENT_SETUP], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ #ifdef HAVE_DRM_DRM_CLIENT_SETUP_H #include #endif @@ -13,7 +13,7 @@ AC_DEFUN([AC_AMDGPU_DRM_CLIENT_SETUP], [ #endif ], [ drm_client_setup(NULL, NULL); - ], [ + ], [drm_client_setup],[drivers/gpu/drm/clients/drm_client_setup.c],[ AC_DEFINE(HAVE_DRM_CLIENT_SETUP, 1, [drm_client_setup() is available]) ]) From f7fcca52ce74ed6c20c362195858f415eab0f993 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 27 Jun 2025 15:46:08 +0800 Subject: [PATCH 1549/2653] drm/amdkcl: fix m4 include path to drm/drm_file.h Signed-off-by: Bob Zhou Reviewed-by: Yang Su --- drivers/gpu/drm/amd/dkms/m4/drm_file.m4 | 4 ++-- drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_file.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_file.m4 index ad9fe77b06a05..c4144b607fbb7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_file.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_file.m4 @@ -3,8 +3,8 @@ dnl # v6.12-rc1-309-g56c594d8df64 dnl # AC_DEFUN([AC_AMDGPU_DRM_FILE_CLIENT_NAME], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include + AC_KERNEL_TRY_COMPILE([ + #include ], [ struct drm_file *filp = NULL; filp->client_name = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 index fd413cbd2300a..5483d555b35eb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 @@ -5,7 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_FILE_ERR], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include + #include ], [ drm_file_err(NULL, NULL); ], [drm_file_err], [drivers/gpu/drm/drm_file.c],[ From 2c33833212bdee0c1d4f1d27770bf44c75079cf4 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 1 Jul 2025 14:44:32 +0800 Subject: [PATCH 1550/2653] drm/amdkcl: update check usleep_range_state() The usleep_range_state() move to sleep_timeout.c from timer.c now Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 b/drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 index 7540052fefc59..cac1023aef491 100644 --- a/drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 @@ -6,12 +6,12 @@ AC_DEFUN([AC_AMDGPU_USLEEP_RANGE_STATE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ #include - #include + #include ], [ - usleep_range_state(0, 0, TASK_UNINTERRUPTIBLE); - ], [usleep_range_state], [kernel/time/timer.c], [ - AC_DEFINE(HAVE_USLEEP_RANGE_STATE, 1, - [usleep_range_state() is available]) - ]) + usleep_range_state(0, 0, TASK_UNINTERRUPTIBLE); + ], [usleep_range_state], [kernel/time/timer.c kernel/time/sleep_timeout.c], [ + AC_DEFINE(HAVE_USLEEP_RANGE_STATE, 1, + [usleep_range_state() is available]) + ]) ]) ]) From d658b6188d0b1456a87314ac4c653695b960e232 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 27 Jun 2025 15:58:18 +0800 Subject: [PATCH 1551/2653] drm/amdkcl: fix m4 macro define for test_funcs.mode_valid Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 index b0930aa8e97cf..4495fbe5cb695 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 @@ -45,9 +45,10 @@ AC_DEFUN([AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_MODE_VALID_CONST_ARGUMENT], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - struct drm_connector_helper_funcs test_funcs = { - .mode_valid = (enum drm_mode_status (*)(struct drm_connector *, const struct drm_display_mode *))0 - }; + enum drm_mode_status (*p)(struct drm_connector *, const struct drm_display_mode *) = NULL; + + struct drm_connector_helper_funcs test_funcs; + test_funcs.mode_valid = p; ], [ AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT, 1, [.mode_valid need a const drm_display_mode argument]) From 8486b3ba529cd52e0170c7123473a8e1dc898084 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Fri, 9 Apr 2021 12:30:43 -0400 Subject: [PATCH 1552/2653] drm/amdkfd: CRIU implement gpu_id remapping v2 When doing a restore on a different node, the gpu_id's on the restore node may be different. But the user space application will still refer use the original gpu_id's in the ioctl calls. Adding code to create a gpu id mapping so that kfd can determine actual gpu_id during the user ioctl's. Reviewed-by: Felix Kuehling Signed-off-by: David Yat Sin Signed-off-by: Rajneesh Bhardwaj Change-Id: I89ca4a2f5e534391e0e13cbdaf58aafee2ba6021 --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index a68ff45dfcd21..3d614ccaf3308 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1661,14 +1661,16 @@ static int kfd_ioctl_ipc_export_handle(struct file *filep, void *data) { struct kfd_ioctl_ipc_export_handle_args *args = data; - struct kfd_dev *dev; + struct kfd_process_device *pdd; int r; - dev = kfd_device_by_id(args->gpu_id); - if (!dev) + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + mutex_unlock(&p->mutex); + if (!pdd) return -EINVAL; - r = kfd_ipc_export_as_handle(dev, p, args->handle, args->share_handle, + r = kfd_ipc_export_as_handle(pdd->dev, p, args->handle, args->share_handle, args->flags); if (r) pr_err("Failed to export IPC handle\n"); From 8e8020818db94f963170a8cfdd5236d8e843e3f6 Mon Sep 17 00:00:00 2001 From: Alex Sierra Date: Wed, 1 Apr 2020 16:35:06 -0500 Subject: [PATCH 1553/2653] drm/amdgpu: replace per_device_list by array v2 Remove per_device_list from kfd_process and replace it with a kfd_process_device pointers array of MAX_GPU_INSTANCES size. This helps to manage the kfd_process_devices binded to a specific kfd_process. Also, functions used by kfd_chardev to iterate over the list were removed, since they are not valid anymore. Instead, it was replaced by a local loop iterating the array. v2: This change aligns with 'commit 56096e4ac889 ("drm/amdgpu: replace per_device_list by array")' in amd-staging-drm-next. Signed-off-by: Alex Sierra Signed-off-by: Felix Kuehling Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 9ff4ea8264561..c9cbd1387e124 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -982,7 +982,6 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) * local memory object */ idr_for_each_entry(&pdd->alloc_idr, buf_obj, id) { - struct kfd_process_device *peer_pdd; for (i = 0; i < p->n_pdds; i++) { struct kfd_process_device *peer_pdd = p->pdds[i]; @@ -1700,6 +1699,7 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, pdd->sdma_past_activity_counter = 0; pdd->user_gpu_id = dev->id; atomic64_set(&pdd->evict_duration_counter, 0); + kfd_spm_init_process_device(pdd); p->pdds[p->n_pdds++] = pdd; if (kfd_dbg_is_per_vmid_supported(pdd->dev)) @@ -2163,24 +2163,24 @@ void kfd_process_schedule_restore(struct kfd_process *p) static void kfd_process_unmap_doorbells(struct kfd_process *p) { - struct kfd_process_device *pdd; struct mm_struct *mm = p->mm; + int i; mmap_write_lock(mm); - list_for_each_entry(pdd, &p->per_device_data, per_device_list) - kfd_doorbell_unmap(pdd); + for (i = 0; i < p->n_pdds; i++) + kfd_doorbell_unmap(p->pdds[i]); mmap_write_unlock(mm); } int kfd_process_remap_doorbells_locked(struct kfd_process *p) { - struct kfd_process_device *pdd; int ret = 0; + int i; - list_for_each_entry(pdd, &p->per_device_data, per_device_list) - ret = kfd_doorbell_remap(pdd); + for (i = 0; i < p->n_pdds; i++) + ret = kfd_doorbell_remap(p->pdds[i]); return ret; } @@ -2205,8 +2205,8 @@ static int kfd_process_remap_doorbells(struct kfd_process *p) */ static bool kfd_process_unmap_doorbells_if_idle(struct kfd_process *p) { - struct kfd_process_device *pdd; bool busy = false; + int i; if (!keep_idle_process_evicted) return false; @@ -2217,7 +2217,9 @@ static bool kfd_process_unmap_doorbells_if_idle(struct kfd_process *p) */ kfd_process_unmap_doorbells(p); - list_for_each_entry(pdd, &p->per_device_data, per_device_list) { + for (i = 0; i < p->n_pdds; i++) { + struct kfd_process_device *pdd = p->pdds[i]; + busy = check_if_queues_active(pdd->qpd.dqm, &pdd->qpd); if (busy) break; From 172ac60e5e09203dc02910cc9f08f11a37cc1ea5 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 16 Nov 2021 23:15:55 -0500 Subject: [PATCH 1554/2653] drm/amdkfd: Implement DMA buf fd export from KFD v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Exports a DMA buf fd of a given KFD buffer handle. This is intended for being able to import KFD BOs into GEM contexts to leverage the amdgpu_bo_va API for more flexible virtual address mappings. It will also be used for the new upstreamable RDMA solution coming to UCX and RCCL. The corresponding user mode change (Thunk API and kfdtest) is here: https://github.com/fxkamd/ROCT-Thunk-Interface/commits/fxkamd/dmabuf Signed-off-by: Felix Kuehling Acked-by: Christian König Reviewed-by: Xiaogang Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 672ba6e251472..4e60c68b66763 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2752,11 +2752,12 @@ int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, goto unlock_out; } - dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base, 0); - if (IS_ERR(dmabuf)) { - r = PTR_ERR(dmabuf); + r = kfd_mem_export_dmabuf(mem); + if (r) goto unlock_out; - } + + get_dma_buf(mem->dmabuf); + dmabuf = mem->dmabuf; r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj, flags, restore_handle); if (r) From 5443d22295e66e65ccd126723255fb56677481f9 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Tue, 1 Mar 2022 22:28:53 +0800 Subject: [PATCH 1555/2653] drm/amdgpu: convert code name to ip version for noretry set v2 Use IP version rather than codename for noretry set. Signed-off-by: Yifan Zhang Reviewed-by: Alex Deucher Change-Id: I171004a0b31f27903f2db30c66f21379294aba70 --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 38d5b0cd42285..682d37aa4376f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -934,6 +934,27 @@ void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) gmc->noretry = 1; else gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry; + + /* keep this for kfd test fail */ + switch (adev->asic_type) { + case CHIP_VEGA10: + case CHIP_NAVI10: + case CHIP_NAVI14: + case CHIP_SIENNA_CICHLID: + case CHIP_NAVY_FLOUNDER: + case CHIP_DIMGREY_CAVEFISH: + /* + * noretry = 0 will cause kfd page fault tests fail + * for some ASICs, so set default to 1 for these ASICs. + */ + if (amdgpu_noretry == -1) + gmc->noretry = 1; + else + gmc->noretry = amdgpu_noretry; + break; + default: + break; + } } void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, From a954ad366db498486547d04d212cdac9b5812edf Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 8 Jan 2025 16:11:42 -0500 Subject: [PATCH 1556/2653] drm/amdgpu/swsmu: set workload profile to bootup default v2 Now that we can select a workload profile dynamically when we submit work, it's best to default to the bootup default workload profile. Defaulting to other profiles prevents some power management features from kicking in during idle periods. Once all jobs have finished, the workload profile will automatically move back to default bootup for max power savings. Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 611ebb1fb145e..02c1448f090e7 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -1309,7 +1309,7 @@ static void smu_init_power_profile(struct smu_context *smu) if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN) smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; - smu_power_profile_mode_get(smu, smu->power_profile_mode); + } static int smu_sw_init(struct amdgpu_ip_block *ip_block) From 90e19b104b08b95a1a4a1e04b12438483d6bd8a5 Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Tue, 23 Apr 2024 15:42:41 -0400 Subject: [PATCH 1557/2653] drm/amdgpu: Fix VRAM memory accounting v2 Subtract the VRAM pinned memory when checking for available memory in amdgpu_amdkfd_reserve_mem_limit function since that memory is not available for use. Signed-off-by: Mukul Joshi Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 4e60c68b66763..1edd0f65739e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -223,7 +223,8 @@ int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, (kfd_mem_limit.ttm_mem_used + ttm_mem_needed > kfd_mem_limit.max_ttm_mem_limit) || (adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] + vram_needed > - vram_size - reserved_for_pt - reserved_for_ras - atomic64_read(&adev->vram_pin_size))) { + vram_size - reserved_for_pt - reserved_for_ras - atomic64_read(&adev->vram_pin_size) + + atomic64_read(&adev->kfd.vram_pinned))) { ret = -ENOMEM; goto release; } From 65a052ede3655cd28b606f9d5801263581478399 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 17 Apr 2024 23:19:25 -0400 Subject: [PATCH 1558/2653] drm/amdkfd: Run restore_workers on freezable WQs v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make restore workers freezable so we don't have to explicitly flush them in suspend and GPU reset code paths, and we don't accidentally try to restore BOs while the GPU is suspended. Not having to flush restore_work also helps avoid lock/fence dependencies in the GPU reset case where we're not allowed to wait for fences. A side effect of this is, that we can now have multiple concurrent threads trying to signal the same eviction fence. Rework eviction fence signaling and replacement to account for that. The GPU reset path can no longer rely on restore_process_worker to resume queues because evict/restore workers can run independently of it. Instead call a new restore_process_helper directly. v2: - Reworked eviction fence signaling - Introduced restore_process_helper v3: - Handle unsignaled eviction fences in restore_process_bos v4: - Ported to DKMS branch and squashed with "drm/amdkfd: Fix eviction fence handling" Signed-off-by: Felix Kuehling Acked-by: Christian König Tested-by: Emily Deng Signed-off-by: Alex Deucher Tested-by: Gang BA Reviewed-by: Gang BA Tested-by: Vitaly Prosyak --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index c9cbd1387e124..7ea168b25547f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -2143,7 +2143,6 @@ static int signal_eviction_fence(struct kfd_process *p) void kfd_process_schedule_restore(struct kfd_process *p) { - int ret; unsigned long evicted_jiffies; unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_RESTORE_TIME_MS); @@ -2156,9 +2155,8 @@ void kfd_process_schedule_restore(struct kfd_process *p) delay_jiffies = 0; pr_debug("Process %d schedule restore work\n", p->pasid); - ret = queue_delayed_work(kfd_restore_wq, &p->restore_work, - delay_jiffies); - WARN(!ret, "Schedule restore work failed\n"); + if (mod_delayed_work(kfd_restore_wq, &p->restore_work, delay_jiffies)) + kfd_process_restore_queues(p); } static void kfd_process_unmap_doorbells(struct kfd_process *p) @@ -2279,7 +2277,6 @@ static int restore_process_helper(struct kfd_process *p) } ret = kfd_process_restore_queues(p); - trace_kfd_restore_process_worker_end(p, ret ? "Failed" : "Success"); if (!ret) pr_debug("Finished restoring process pid %d\n", p->lead_thread->pid); @@ -2302,6 +2299,13 @@ static void restore_process_worker(struct work_struct *work) * lifetime of this thread, kfd_process p will be valid */ p = container_of(dwork, struct kfd_process, restore_work); + + if (kfd_process_unmap_doorbells_if_idle(p)) { + pr_debug("Process %d queues idle, doorbell unmapped\n", + p->pasid); + return; + } + pr_debug("Started restoring process pasid %d\n", (int)p->lead_thread->pid); trace_kfd_restore_process_worker_start(p); From 941817aff92ea9da3e39a860a0f4f101698add6e Mon Sep 17 00:00:00 2001 From: Jay Cornwall Date: Tue, 7 Jan 2025 21:59:06 -0600 Subject: [PATCH 1559/2653] drm/amdkfd: Clear MODE.VSKIP in gfx9 trap handler v2 If user shader issues S_SETVSKIP then this state will persist when executing the trap handler, causing vector instructions to be skipped. VSKIP state is already saved/restored through the MODE register. Signed-off-by: Jay Cornwall Reviewed-by: Lancelot Six --- .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 2635 +++++++++-------- .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 4 +- 2 files changed, 1322 insertions(+), 1317 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index 5cb39cd646e8a..75188c3b01996 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -274,7 +274,7 @@ static const uint32_t cwsr_trap_gfx8_hex[] = { static const uint32_t cwsr_trap_gfx9_hex[] = { - 0xbf820001, 0xbf820268, + 0xbf820001, 0xbf820269, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -398,141 +398,98 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0xbefe007c, 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, - 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, - 0xbef600ff, 0x01000000, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, + 0xbefc007e, 0xbf108080, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85004d, 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb4306, 0x867bc17b, - 0xbf840063, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf84005f, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, - 0xd2890000, 0x00000900, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, + 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, - 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb2a05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb4306, + 0x867bc17b, 0xbf840063, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf84005f, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -552,137 +509,181 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2a05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, + 0x807bff7b, 0x00001000, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf850051, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, + 0x00000900, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xbf8200c7, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf84001e, 0xbefe00c1, - 0xbeff00c1, 0xb8ef4306, - 0x866fc16f, 0xbf840019, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2a05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffef, 0xbf9c0000, + 0xbf8200c7, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf84001e, + 0xbefe00c1, 0xbeff00c1, + 0xb8ef4306, 0x866fc16f, + 0xbf840019, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, 0xb8f82a05, 0x80788178, 0x8e788a78, 0xb8ee1605, 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, + 0xbefe00c1, 0xbeff00c1, 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82a05, + 0xb8ef2a05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, + 0xbf11087c, 0xe0524000, + 0x781d0000, 0xe0524100, + 0x781d0100, 0xe0524200, + 0x781d0200, 0xe0524300, + 0x781d0300, 0xbf8c0f70, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0x807c847c, 0x8078ff78, + 0x00000400, 0xbf0a6f7c, + 0xbf85ffee, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82a05, 0x80788178, 0x8e788a78, 0xb8ee1605, 0x806e816e, 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2a05, - 0x806e816e, 0x8e6e8a6e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b77, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2a05, 0x806e816e, + 0x8e6e8a6e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b77, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_nv1x_hex[] = { @@ -1310,7 +1311,7 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { }; static const uint32_t cwsr_trap_arcturus_hex[] = { - 0xbf820001, 0xbf8202e4, + 0xbf820001, 0xbf8202e5, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -1435,99 +1436,143 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0xbefe007c, 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, + 0xbefc007e, 0xbf108080, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf85004d, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, + 0x80048104, 0xd2890002, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb4306, 0x867bc17b, + 0xbf840064, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf840060, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840064, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf840060, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2a05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, + 0x807bff7b, 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -1546,259 +1591,216 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb2a05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffef, 0xbf9c0000, + 0xbefc0080, 0xbf11017c, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf850059, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xbe840080, + 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, + 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xbefc0080, - 0xbf11017c, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850059, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffa9, 0xbf9c0000, - 0xbf820016, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffeb, - 0xbf9c0000, 0xbf8200e3, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf84001f, 0xbefe00c1, - 0xbeff00c1, 0xb8ef4306, - 0x866fc16f, 0xbf84001a, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0x807cff7c, 0x00000200, - 0x8078ff78, 0x00000200, - 0xbf0a6f7c, 0xbf85fff6, - 0xbefe00c1, 0xbeff00c1, - 0xbef600ff, 0x01000000, - 0xb8ef2a05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, - 0xbf11087c, 0xe0524000, - 0x781d0000, 0xe0524100, - 0x781d0100, 0xe0524200, - 0x781d0200, 0xe0524300, - 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0x807c847c, 0x8078ff78, - 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xbefc0080, - 0xbf11087c, 0xe0524000, - 0x781d0000, 0xe0524100, - 0x781d0100, 0xe0524200, - 0x781d0200, 0xe0524300, - 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, - 0x807c847c, 0x8078ff78, - 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffa9, + 0xbf9c0000, 0xbf820016, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffeb, 0xbf9c0000, + 0xbf8200e3, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf84001f, + 0xbefe00c1, 0xbeff00c1, + 0xb8ef4306, 0x866fc16f, + 0xbf84001a, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0x807cff7c, + 0x00000200, 0x8078ff78, + 0x00000200, 0xbf0a6f7c, + 0xbf85fff6, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2a05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2a05, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b77, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2a05, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b77, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_aldebaran_hex[] = { - 0xbf820001, 0xbf8202ef, + 0xbf820001, 0xbf8202f0, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -1923,99 +1925,37 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xbefe007c, 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840064, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf840060, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0xbefc007e, 0xbf108080, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -2034,31 +1974,50 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000902, + 0x80048104, 0xd2890001, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, + 0x80048104, 0xd2890003, + 0x00000902, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, 0xbefe00c1, 0xbeff00c1, - 0xb8fb2b05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, + 0xb8fb4306, 0x867bc17b, + 0xbf840064, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf840060, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -2078,51 +2037,31 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xb8fb2985, - 0x807b817b, 0x8e7b837b, - 0xb8fa2b05, 0x807a817a, - 0x8e7a827a, 0x80fb7a7b, - 0x867b7b7b, 0xbf84007a, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2b05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, 0x807bff7b, 0x00001000, - 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850059, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -2161,139 +2100,203 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffa9, - 0xbf9c0000, 0xbf820016, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffeb, 0xbf9c0000, - 0xbf8200ee, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf84001f, - 0xbefe00c1, 0xbeff00c1, - 0xb8ef4306, 0x866fc16f, - 0xbf84001a, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2b05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xb8ef2985, 0x806f816f, - 0x8e6f836f, 0xb8f92b05, - 0x80798179, 0x8e798279, - 0x80ef796f, 0x866f6f6f, - 0xbf84001a, 0x806fff6f, - 0x00008000, 0xbefc0080, - 0xbf11087c, 0xe0524000, - 0x781d0000, 0xe0524100, - 0x781d0100, 0xe0524200, - 0x781d0200, 0xe0524300, - 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, - 0x807c847c, 0x8078ff78, - 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82985, + 0xbf85ffef, 0xbf9c0000, + 0xb8fb2985, 0x807b817b, + 0x8e7b837b, 0xb8fa2b05, + 0x807a817a, 0x8e7a827a, + 0x80fb7a7b, 0x867b7b7b, + 0xbf84007a, 0x807bff7b, + 0x00001000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf8200ee, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf84001f, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf84001a, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82985, 0x80788178, 0x8e788a78, 0x8e788178, 0xb8ee1605, 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, + 0xbefe00c1, 0xbeff00c1, 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xb8ef2b05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, + 0xbf11087c, 0xe0524000, + 0x781d0000, 0xe0524100, + 0x781d0100, 0xe0524200, + 0x781d0200, 0xe0524300, + 0x781d0300, 0xbf8c0f70, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0x807c847c, 0x8078ff78, + 0x00000400, 0xbf0a6f7c, + 0xbf85ffee, 0xb8ef2985, + 0x806f816f, 0x8e6f836f, + 0xb8f92b05, 0x80798179, + 0x8e798279, 0x80ef796f, + 0x866f6f6f, 0xbf84001a, + 0x806fff6f, 0x00008000, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2985, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b77, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2985, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b77, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_gfx10_hex[] = { @@ -3175,7 +3178,7 @@ static const uint32_t cwsr_trap_gfx11_hex[] = { }; static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { - 0xbf820001, 0xbf8202fa, + 0xbf820001, 0xbf8202fb, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -3306,98 +3309,142 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, - 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, - 0xbef600ff, 0x01000000, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, + 0xbf108080, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85004d, + 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000903, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb4306, + 0x867bc17b, 0xbf840064, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf840060, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf850030, 0x24040682, + 0xd86e4000, 0x00000002, + 0xbf8cc07f, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, + 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, + 0xbf84ffee, 0x680404ff, + 0x00000200, 0xd0c9006a, + 0x0000f702, 0xbf87ffd2, + 0xbf820015, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbf87fff7, 0xbef70000, + 0xbef000ff, 0x00000400, 0xbefe00c1, 0xbeff00c1, - 0xb8fb4306, 0x867bc17b, - 0xbf840064, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf840060, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, + 0xb8fb2b05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850030, - 0x24040682, 0xd86e4000, - 0x00000002, 0xbf8cc07f, + 0x10000000, 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -3417,31 +3464,51 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000200, - 0xd0c9006a, 0x0000f702, - 0xbf87ffd2, 0xbf820015, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbf87fff7, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2b05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xb8fb2985, + 0x807b817b, 0x8e7b837b, + 0xb8fa2b05, 0x807a817a, + 0x8e7a827a, 0x80fb7a7b, + 0x867b7b7b, 0xbf84007a, 0x807bff7b, 0x00001000, + 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, + 0xbf850059, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -3480,203 +3547,139 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, + 0xbf0a7b7c, 0xbf85ffa9, + 0xbf9c0000, 0xbf820016, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xb8fb2985, 0x807b817b, - 0x8e7b837b, 0xb8fa2b05, - 0x807a817a, 0x8e7a827a, - 0x80fb7a7b, 0x867b7b7b, - 0xbf84007a, 0x807bff7b, - 0x00001000, 0xbefc0080, - 0xbf11017c, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850059, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffa9, 0xbf9c0000, - 0xbf820016, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffeb, - 0xbf9c0000, 0xbf8200ee, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf84001f, 0xbefe00c1, - 0xbeff00c1, 0xb8ef4306, - 0x866fc16f, 0xbf84001a, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0x807cff7c, 0x00000200, - 0x8078ff78, 0x00000200, - 0xbf0a6f7c, 0xbf85fff6, + 0xbf85ffeb, 0xbf9c0000, + 0xbf8200ee, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf84001f, 0xbefe00c1, 0xbeff00c1, + 0xb8ef4306, 0x866fc16f, + 0xbf84001a, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xb8ef2b05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0x807cff7c, + 0x00000200, 0x8078ff78, + 0x00000200, 0xbf0a6f7c, + 0xbf85fff6, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2b05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xb8ef2985, 0x806f816f, + 0x8e6f836f, 0xb8f92b05, + 0x80798179, 0x8e798279, + 0x80ef796f, 0x866f6f6f, + 0xbf84001a, 0x806fff6f, + 0x00008000, 0xbefc0080, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, + 0xd3d94000, 0x18000100, + 0xd3d94001, 0x18000101, + 0xd3d94002, 0x18000102, + 0xd3d94003, 0x18000103, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xb8ef2985, - 0x806f816f, 0x8e6f836f, - 0xb8f92b05, 0x80798179, - 0x8e798279, 0x80ef796f, - 0x866f6f6f, 0xbf84001a, - 0x806fff6f, 0x00008000, - 0xbefc0080, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0xd3d94000, - 0x18000100, 0xd3d94001, - 0x18000101, 0xd3d94002, - 0x18000102, 0xd3d94003, - 0x18000103, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffea, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0xbf85ffea, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, + 0xbef600ff, 0x01000000, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2985, - 0x806e816e, 0x8e6e8a6e, - 0x8e6e816e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b79, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2985, 0x806e816e, + 0x8e6e8a6e, 0x8e6e816e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b79, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, }; static const uint32_t cwsr_trap_gfx12_hex[] = { @@ -4208,7 +4211,7 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { }; static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { - 0xbf820001, 0xbf8202e8, + 0xbf820001, 0xbf8202e9, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, @@ -4339,98 +4342,133 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, - 0x867aff7f, 0x04000000, - 0xbeef0080, 0x876f6f7a, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, - 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, - 0xbef600ff, 0x01000000, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, + 0xbf108080, 0x867aff7f, + 0x04000000, 0xbeef0080, + 0x876f6f7a, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85004d, 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000902, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000902, 0x80048104, - 0xd2890002, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000902, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000903, 0x80048104, - 0xd2890001, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, 0x80048104, 0xd2890002, - 0x00000903, 0x80048104, - 0xd2890003, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, - 0xe0724000, 0x701d0000, - 0xe0724100, 0x701d0100, - 0xe0724200, 0x701d0200, - 0xe0724300, 0x701d0300, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb5306, + 0x867bc17b, 0xbf840052, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf84004e, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xd28c0002, 0x000100c1, + 0xd28d0003, 0x000204c1, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf85001d, 0x24040682, + 0xd86c0000, 0x00000002, + 0xbf8cc07f, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, + 0x00000900, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x680404ff, 0x00000100, + 0xd0c9006a, 0x0000f702, + 0xbf87ffe5, 0xbf820016, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbefe016a, + 0xbf87fff6, 0xbef70000, + 0xbef000ff, 0x00000400, 0xbefe00c1, 0xbeff00c1, - 0xb8fb5306, 0x867bc17b, - 0xbf840052, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf84004e, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xd28c0002, - 0x000100c1, 0xd28d0003, - 0x000204c1, 0x867aff78, + 0xb8fb2b05, 0x807b817b, + 0x8e7b827b, 0xbef600ff, + 0x01000000, 0xbefc0084, + 0xbf0a7b7c, 0xbf84006d, + 0xbf11017c, 0x807bff7b, + 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85001d, - 0x24040682, 0xd86c0000, - 0x00000002, 0xbf8cc07f, + 0x10000000, 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -4440,32 +4478,61 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000100, 0xd0c9006a, - 0x0000f702, 0xbf87ffe5, - 0xbf820016, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbefe016a, 0xbf87fff6, - 0xbef70000, 0xbef000ff, - 0x00000400, 0xbefe00c1, - 0xbeff00c1, 0xb8fb2b05, - 0x807b817b, 0x8e7b827b, - 0xbef600ff, 0x01000000, - 0xbefc0084, 0xbf0a7b7c, - 0xbf84006d, 0xbf11017c, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffb1, 0xbf9c0000, + 0xbf820012, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffef, + 0xbf9c0000, 0xb8fb2985, + 0x807b817b, 0x8e7b837b, + 0xb8fa2b05, 0x807a817a, + 0x8e7a827a, 0x80fb7a7b, + 0x867b7b7b, 0xbf84007a, 0x807bff7b, 0x00001000, + 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850051, 0xbe840080, + 0xbf850059, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -4504,204 +4571,140 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffb1, - 0xbf9c0000, 0xbf820012, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, + 0xbf0a7b7c, 0xbf85ffa9, + 0xbf9c0000, 0xbf820016, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffef, 0xbf9c0000, - 0xb8fb2985, 0x807b817b, - 0x8e7b837b, 0xb8fa2b05, - 0x807a817a, 0x8e7a827a, - 0x80fb7a7b, 0x867b7b7b, - 0xbf84007a, 0x807bff7b, - 0x00001000, 0xbefc0080, - 0xbf11017c, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850059, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffa9, 0xbf9c0000, - 0xbf820016, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffeb, - 0xbf9c0000, 0xbf8200f4, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf840025, 0xbefe00c1, - 0xbeff00c1, 0xb8ef5306, - 0x866fc16f, 0xbf840020, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0xe0510200, 0x781d0000, - 0xe0510300, 0x781d0000, - 0xe0510400, 0x781d0000, - 0x807cff7c, 0x00000500, - 0x8078ff78, 0x00000500, - 0xbf0a6f7c, 0xbf85fff0, + 0xbf85ffeb, 0xbf9c0000, + 0xbf8200f4, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf840025, 0xbefe00c1, 0xbeff00c1, + 0xb8ef5306, 0x866fc16f, + 0xbf840020, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xb8ef2b05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0xe0510200, + 0x781d0000, 0xe0510300, + 0x781d0000, 0xe0510400, + 0x781d0000, 0x807cff7c, + 0x00000500, 0x8078ff78, + 0x00000500, 0xbf0a6f7c, + 0xbf85fff0, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2b05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xb8ef2985, 0x806f816f, + 0x8e6f836f, 0xb8f92b05, + 0x80798179, 0x8e798279, + 0x80ef796f, 0x866f6f6f, + 0xbf84001a, 0x806fff6f, + 0x00008000, 0xbefc0080, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, + 0xd3d94000, 0x18000100, + 0xd3d94001, 0x18000101, + 0xd3d94002, 0x18000102, + 0xd3d94003, 0x18000103, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xb8ef2985, - 0x806f816f, 0x8e6f836f, - 0xb8f92b05, 0x80798179, - 0x8e798279, 0x80ef796f, - 0x866f6f6f, 0xbf84001a, - 0x806fff6f, 0x00008000, - 0xbefc0080, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0xd3d94000, - 0x18000100, 0xd3d94001, - 0x18000101, 0xd3d94002, - 0x18000102, 0xd3d94003, - 0x18000103, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffea, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x80f8c078, 0xb8ef1605, - 0x806f816f, 0x8e6f846f, - 0x8e76826f, 0xbef600ff, - 0x01000000, 0xbefc006f, - 0xc031003a, 0x00000078, - 0x80f8c078, 0xbf8cc07f, - 0x80fc907c, 0xbf800000, - 0xbe802d00, 0xbe822d02, - 0xbe842d04, 0xbe862d06, - 0xbe882d08, 0xbe8a2d0a, - 0xbe8c2d0c, 0xbe8e2d0e, - 0xbf06807c, 0xbf84fff0, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0xbf85ffea, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x80f8c078, + 0xb8ef1605, 0x806f816f, + 0x8e6f846f, 0x8e76826f, + 0xbef600ff, 0x01000000, + 0xbefc006f, 0xc031003a, + 0x00000078, 0x80f8c078, + 0xbf8cc07f, 0x80fc907c, + 0xbf800000, 0xbe802d00, + 0xbe822d02, 0xbe842d04, + 0xbe862d06, 0xbe882d08, + 0xbe8a2d0a, 0xbe8c2d0c, + 0xbe8e2d0e, 0xbf06807c, + 0xbf84fff0, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0xbef60084, + 0xbef600ff, 0x01000000, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2985, - 0x806e816e, 0x8e6e8a6e, - 0x8e6e816e, 0xb8ef1605, - 0x806f816f, 0x8e6f866f, - 0x806e6f6e, 0x806e746e, - 0x826f8075, 0x866fff6f, - 0x0000ffff, 0xc00b1c37, - 0x00000050, 0xc00b1d37, - 0x00000060, 0xc0031e77, - 0x00000074, 0xbf8cc07f, - 0x8f6e8b79, 0x866eff6e, - 0x001f8000, 0xb96ef807, - 0x866dff6d, 0x0000ffff, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e837a, 0xb96ee0c2, - 0xbf800002, 0xb97a0002, - 0xbf8a0000, 0xbe801f6c, - 0xbf9b0000, 0x00000000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2985, 0x806e816e, + 0x8e6e8a6e, 0x8e6e816e, + 0xb8ef1605, 0x806f816f, + 0x8e6f866f, 0x806e6f6e, + 0x806e746e, 0x826f8075, + 0x866fff6f, 0x0000ffff, + 0xc00b1c37, 0x00000050, + 0xc00b1d37, 0x00000060, + 0xc0031e77, 0x00000074, + 0xbf8cc07f, 0x8f6e8b79, + 0x866eff6e, 0x001f8000, + 0xb96ef807, 0x866dff6d, + 0x0000ffff, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e837a, + 0xb96ee0c2, 0xbf800002, + 0xb97a0002, 0xbf8a0000, + 0xbe801f6c, 0xbf9b0000, }; diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index 96b80284ba386..4d959e219c2b4 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -535,7 +535,9 @@ L_SAVE: s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) //MODE write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) - + // Clear VSKIP state now that MODE.VSKIP has been saved. + // If user shader set it then vector instructions would be skipped. + s_setvskip 0,0 /* the first wave in the threadgroup */ s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit From 3a843bc903914faf450359ae903fc9302d4a4a98 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 7 Dec 2023 10:39:06 +0800 Subject: [PATCH 1560/2653] drm/amdkfd: Import DMABufs for interop through DRM v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use drm_gem_prime_fd_to_handle to import DMABufs for interop. This ensures that a GEM handle is created on import and that obj->dma_buf will be set and remain set as long as the object is imported into KFD. Signed-off-by: Felix Kuehling Reviewed-by: Ramesh Errabolu Reviewed-by: Xiaogang.Chen Acked-by: Christian König Signed-off-by: Alex Deucher Signed-off-by: Bob Zhou drm/amdgpu: Remove remaining AMDKCL_AMDGPU_DMABUF_OPS refs These were missed in the cleanup patch, so remove them to allow the kernel to compile again Fixes: 083e622bbba3 ("drm/amdkcl: cleanup macro AMDKCL_AMDGPU_DMABUF_OPS") Signed-off-by: Kent Russell Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 35 +++++++++++++++++-- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 24 +------------ drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 4 --- 5 files changed, 36 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 4ac58446a8143..f176ac194e0e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -379,7 +379,7 @@ void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, struct device *dma_dev, enum dma_data_direction dir, struct sg_table *sg); -int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev, +int amdgpu_amdkfd_gpuvm_import_ipcobj(struct amdgpu_device *adev, struct dma_buf *dmabuf, struct kfd_ipc_obj *ipc_obj, uint64_t va, void *drm_priv, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 1edd0f65739e7..deb39e320b042 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2061,7 +2061,8 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( /* Free the BO*/ drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv); - drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle); + if (!mem->ipc_obj) + drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle); if (mem->dmabuf) { dma_buf_put(mem->dmabuf); mem->dmabuf = NULL; @@ -2651,7 +2652,6 @@ static int import_obj_create(struct amdgpu_device *adev, get_dma_buf(dma_buf); (*mem)->dmabuf = dma_buf; (*mem)->bo = bo; - (*mem)->ipc_obj = ipc_obj; (*mem)->va = va; (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) && !adev->apu_prefer_gtt ? @@ -2682,6 +2682,37 @@ static int import_obj_create(struct amdgpu_device *adev, return ret; } +int amdgpu_amdkfd_gpuvm_import_ipcobj(struct amdgpu_device *adev, + struct dma_buf *dma_buf, + struct kfd_ipc_obj *ipc_obj, + uint64_t va, void *drm_priv, + struct kgd_mem **mem, uint64_t *size, + uint64_t *mmap_offset) +{ + struct drm_gem_object *obj; + int ret; + + if (WARN_ON(!ipc_obj)) + return -EINVAL; + + obj = amdgpu_gem_prime_import(adev_to_drm(adev), dma_buf); + if (IS_ERR(obj)) + return PTR_ERR(obj); + + ret = import_obj_create(adev, dma_buf, obj, va, drm_priv, mem, size, + mmap_offset); + if (ret) + goto err_put_obj; + + (*mem)->ipc_obj = ipc_obj; + + return 0; + +err_put_obj: + drm_gem_object_put(obj); + return ret; +} + int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, uint64_t va, void *drm_priv, struct kgd_mem **mem, uint64_t *size, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 3d614ccaf3308..726869061292e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1650,7 +1650,7 @@ static int kfd_ioctl_import_dmabuf(struct file *filep, err_free: amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem, - pdd->drm_priv, NULL); + pdd->drm_priv, NULL); err_unlock: mutex_unlock(&p->mutex); return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index ab5769b0fe078..055a4c9364471 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -158,7 +158,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_node *dev, if (IS_ERR(pdd)) return PTR_ERR(pdd); - r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->adev, dmabuf, ipc_obj, + r = amdgpu_amdkfd_gpuvm_import_ipcobj(dev->adev, dmabuf, ipc_obj, va_addr, pdd->drm_priv, &mem, &size, mmap_offset); if (r) @@ -180,28 +180,6 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_node *dev, return r; } -int kfd_ipc_import_dmabuf(struct kfd_node *dev, - struct kfd_process *p, - uint32_t gpu_id, int dmabuf_fd, - uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset) -{ - int r; - struct dma_buf *dmabuf = dma_buf_get(dmabuf_fd); - - if (!dmabuf) - return -EINVAL; - - mutex_lock(&p->mutex); - - r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, dmabuf, NULL, - va_addr, handle, mmap_offset, false); - - mutex_unlock(&p->mutex); - dma_buf_put(dmabuf); - return r; -} - int kfd_ipc_import_handle(struct kfd_node *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h index 6e92cce265d9e..ade507630818d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -43,10 +43,6 @@ int kfd_ipc_import_handle(struct kfd_node *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, uint64_t *mmap_offset, uint32_t *pflags, bool restore); -int kfd_ipc_import_dmabuf(struct kfd_node *kfd, struct kfd_process *p, - uint32_t gpu_id, int dmabuf_fd, - uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset); int kfd_ipc_export_as_handle(struct kfd_node *dev, struct kfd_process *p, uint64_t handle, uint32_t *ipc_handle, uint32_t flags); From bc7fb306ac6c7fccbc03370791d791c37702554e Mon Sep 17 00:00:00 2001 From: chengjya Date: Thu, 16 Jan 2025 10:50:51 +0800 Subject: [PATCH 1561/2653] drm/amdkcl: Have kfd driver use same PASID values from graphic driver in non-upstream code It's caused by the following commit: 77b5e44 "drm/amdkfd: Have kfd driver use same PASID values from graphic driver" Signed-off-by: chengjya Reviewed-by: Xiaogang Chen Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 22 +++++----- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 8 ++-- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 10 ++--- drivers/gpu/drm/amd/amdkfd/kfd_trace.h | 50 +++++++++++------------ 4 files changed, 43 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index 99e0d445ff2d9..c171da2dba587 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -141,7 +141,7 @@ static int kfd_doorbell_vm_fault(struct vm_area_struct *vma, struct vm_fault *vm if (!pdd) return VM_FAULT_SIGBUS; - pr_debug("Process %d doorbell vm page fault\n", pdd->process->pasid); + pr_debug("Process pid %d doorbell vm page fault\n", pdd->process->lead_thread->pid); kfd_process_remap_doorbells_locked(pdd->process); @@ -171,8 +171,8 @@ static void kfd_doorbell_unmap_locked(struct kfd_process_device *pdd) return; } - pr_debug("Process %d unmapping doorbell 0x%lx\n", - process->pasid, vma->vm_start); + pr_debug("Process pid %d unmapping doorbell 0x%lx\n", + process->lead_thread->pid, vma->vm_start); size = kfd_doorbell_process_slice(pdd->dev->kfd); zap_vma_ptes(vma, vma->vm_start, size); @@ -203,13 +203,13 @@ int kfd_doorbell_remap(struct kfd_process_device *pdd) vma = pdd->qpd.doorbell_vma; size = kfd_doorbell_process_slice(pdd->dev->kfd); - pr_debug("Process %d remap doorbell 0x%lx\n", process->pasid, - vma->vm_start); + pr_debug("Process pid %d remap doorbell 0x%lx\n", + process->lead_thread->pid, vma->vm_start); ret = vm_iomap_memory(vma, address, size); if (ret) - pr_err("Process %d failed to remap doorbell 0x%lx\n", - process->pasid, vma->vm_start); + pr_err("Process pid %d failed to remap doorbell 0x%lx\n", + process->lead_thread->pid, vma->vm_start); out_unlock: pdd->qpd.doorbell_mapped = 1; @@ -245,12 +245,12 @@ int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); - pr_debug("Process %d mapping doorbell page\n" + pr_debug("Process pid %d mapping doorbell page\n" " target user address == 0x%08llX\n" " physical address == 0x%08llX\n" " vm_flags == 0x%04lX\n" " size == 0x%04lX\n", - process->pasid, (unsigned long long) vma->vm_start, + process->lead_thread->pid, (unsigned long long) vma->vm_start, address, vma->vm_flags, kfd_doorbell_process_slice(dev->kfd)); pdd = kfd_get_process_device_data(dev, process); @@ -275,8 +275,8 @@ int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, * doorbell is accessed the first time */ if (pdd->qpd.doorbell_mapped == -1) { - pr_debug("Process %d evicted, unmapping doorbell\n", - process->pasid); + pr_debug("Process pid %d evicted, unmapping doorbell\n", + process->lead_thread->pid); kfd_doorbell_unmap_locked(pdd); } else { pdd->qpd.doorbell_mapped = 1; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 7ea168b25547f..6700dbec94316 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -2154,7 +2154,7 @@ void kfd_process_schedule_restore(struct kfd_process *p) else delay_jiffies = 0; - pr_debug("Process %d schedule restore work\n", p->pasid); + pr_debug("Process pid %d schedule restore work\n", p->lead_thread->pid); if (mod_delayed_work(kfd_restore_wq, &p->restore_work, delay_jiffies)) kfd_process_restore_queues(p); } @@ -2301,12 +2301,12 @@ static void restore_process_worker(struct work_struct *work) p = container_of(dwork, struct kfd_process, restore_work); if (kfd_process_unmap_doorbells_if_idle(p)) { - pr_debug("Process %d queues idle, doorbell unmapped\n", - p->pasid); + pr_debug("Process pid %d queues idle, doorbell unmapped\n", + (int)p->lead_thread->pid); return; } - pr_debug("Started restoring process pasid %d\n", (int)p->lead_thread->pid); + pr_debug("Started restoring process pid %d\n", (int)p->lead_thread->pid); trace_kfd_restore_process_worker_start(p); /* Setting last_restore_timestamp before successful restoration. diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 8fd21ad6ee1fa..271bb1c57561b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -682,7 +682,7 @@ int kfd_rlc_spm(struct kfd_process *p, void *data) switch (args->op) { case KFD_IOCTL_SPM_OP_ACQUIRE: - dev->spm_pasid = p->pasid; + dev->spm_pasid = pdd->pasid; return kfd_acquire_spm(pdd, dev->adev); case KFD_IOCTL_SPM_OP_RELEASE: @@ -711,17 +711,13 @@ void kgd2kfd_spm_interrupt(struct kfd_dev *kfd, int xcc_id) fls(amdgpu_xcp_get_partition(kfd->adev->xcp_mgr, AMDGPU_XCP_GFX, xcc_id)) - 1 : 0; dev = kfd->nodes[xcp_id]; pasid = dev->spm_pasid; - p = kfd_lookup_process_by_pasid(pasid); + p = kfd_lookup_process_by_pasid(pasid, &pdd); - if (!p) { + if (!pdd) { dev_dbg(dev->adev->dev, "kfd_spm_interrupt p = %p\n", p); return; /* Presumably process exited. */ } - pdd = kfd_get_process_device_data(dev, p); - if (!pdd) - return; - spin_lock_irqsave(&pdd->spm_irq_lock, flags); if (pdd->spm_cntr && pdd->spm_cntr->spm[xcc_id].is_spm_started) pdd->spm_cntr->spm[xcc_id].has_data_loss = true; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_trace.h b/drivers/gpu/drm/amd/amdkfd/kfd_trace.h index 16470bec1c317..5265efb3728be 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_trace.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_trace.h @@ -41,12 +41,12 @@ TRACE_EVENT(kfd_map_memory_to_gpu_start, TP_PROTO(struct kfd_process *p), TP_ARGS(p), TP_STRUCT__entry( - __field(unsigned int, pasid) + __field(unsigned int, pid) ), TP_fast_assign( - __entry->pasid = p->pasid; + __entry->pid = p->lead_thread->pid; ), - TP_printk("pasid =%u", __entry->pasid) + TP_printk("Process pid =%u", __entry->pid) ); @@ -54,17 +54,17 @@ TRACE_EVENT(kfd_map_memory_to_gpu_end, TP_PROTO(struct kfd_process *p, u32 array_size, char *pStatusMsg), TP_ARGS(p, array_size, pStatusMsg), TP_STRUCT__entry( - __field(unsigned int, pasid) + __field(unsigned int, pid) __field(unsigned int, array_size) __string(pStatusMsg, pStatusMsg) ), TP_fast_assign( - __entry->pasid = p->pasid; + __entry->pid = p->lead_thread->pid; __entry->array_size = array_size; __amdkcl_assign_str(pStatusMsg, pStatusMsg); ), - TP_printk("pasid = %u, array_size = %u, StatusMsg=%s", - __entry->pasid, + TP_printk("Process pid = %u, array_size = %u, StatusMsg=%s", + __entry->pid, __entry->array_size, __get_str(pStatusMsg)) ); @@ -74,15 +74,15 @@ TRACE_EVENT(kfd_kgd2kfd_schedule_evict_and_restore_process, TP_PROTO(struct kfd_process *p, u32 delay_jiffies), TP_ARGS(p, delay_jiffies), TP_STRUCT__entry( - __field(unsigned int, pasid) + __field(unsigned int, pid) __field(unsigned int, delay_jiffies) ), TP_fast_assign( - __entry->pasid = p->pasid; + __entry->pid = p->lead_thread->pid; __entry->delay_jiffies = delay_jiffies; ), - TP_printk("pasid = %u, delay_jiffies = %u", - __entry->pasid, + TP_printk("Process pid = %u, delay_jiffies = %u", + __entry->pid, __entry->delay_jiffies) ); @@ -91,12 +91,12 @@ TRACE_EVENT(kfd_evict_process_worker_start, TP_PROTO(struct kfd_process *p), TP_ARGS(p), TP_STRUCT__entry( - __field(unsigned int, pasid) + __field(unsigned int, pid) ), TP_fast_assign( - __entry->pasid = p->pasid; + __entry->pid = p->lead_thread->pid; ), - TP_printk("pasid=%u", __entry->pasid) + TP_printk("Process pid=%u", __entry->pid) ); @@ -104,15 +104,15 @@ TRACE_EVENT(kfd_evict_process_worker_end, TP_PROTO(struct kfd_process *p, char *pStatusMsg), TP_ARGS(p, pStatusMsg), TP_STRUCT__entry( - __field(unsigned int, pasid) + __field(unsigned int, pid) __string(pStatusMsg, pStatusMsg) ), TP_fast_assign( - __entry->pasid = p->pasid; + __entry->pid = p->lead_thread->pid; __amdkcl_assign_str(pStatusMsg, pStatusMsg); ), - TP_printk("pasid=%u, StatusMsg=%s", - __entry->pasid, __get_str(pStatusMsg)) + TP_printk("Process pid=%u, StatusMsg=%s", + __entry->pid, __get_str(pStatusMsg)) ); @@ -120,27 +120,27 @@ TRACE_EVENT(kfd_restore_process_worker_start, TP_PROTO(struct kfd_process *p), TP_ARGS(p), TP_STRUCT__entry( - __field(unsigned int, pasid) + __field(unsigned int, pid) ), TP_fast_assign( - __entry->pasid = p->pasid; + __entry->pid = p->lead_thread->pid; ), - TP_printk("pasid=%u", __entry->pasid) + TP_printk("Process pid=%u", __entry->pid) ); TRACE_EVENT(kfd_restore_process_worker_end, TP_PROTO(struct kfd_process *p, char *pStatusMsg), TP_ARGS(p, pStatusMsg), TP_STRUCT__entry( - __field(unsigned int, pasid) + __field(unsigned int, pid) __string(pStatusMsg, pStatusMsg) ), TP_fast_assign( - entry->pasid = p->pasid; + entry->pid = p->lead_thread->pid; __amdkcl_assign_str(pStatusMsg, pStatusMsg); ), - TP_printk("pasid=%u, StatusMsg=%s", - __entry->pasid, __get_str(pStatusMsg)) + TP_printk("Process pid=%u, StatusMsg=%s", + __entry->pid, __get_str(pStatusMsg)) ); #endif From 3d00a69feb4acbc6c68f01483fa9188cb6d785a5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 21 Jul 2025 16:37:05 +0800 Subject: [PATCH 1562/2653] drm/amdkcl: update drm_dev_wedged_event to 3 args It's caused by a72002cb181f350734108228b24c5d10d358f95a "drm/amdgpu: Make use of drm_wedge_task_info" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c | 25 +++++++++++++------ drivers/gpu/drm/amd/backport/backport.h | 2 +- .../drm/amd/dkms/m4/drm-dev-wedged-event.m4 | 9 ++++--- include/kcl/kcl_drm_drv.h | 14 ++++++++++- 4 files changed, 38 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c index fcd6eab44d280..9f3cf9fbfb434 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c @@ -47,6 +47,10 @@ static const char *drm_get_wedge_recovery(unsigned int opt) } } +#define WEDGE_STR_LEN 32 +#define PID_STR_LEN 15 +#define COMM_STR_LEN (TASK_COMM_LEN + 5) + /** * drm_dev_wedged_event - generate a device wedged uevent * @dev: DRM device @@ -63,13 +67,13 @@ static const char *drm_get_wedge_recovery(unsigned int opt) * * Returns: 0 on success, negative error code otherwise. */ -int drm_dev_wedged_event(struct drm_device *dev, unsigned long method) +int kcl_drm_dev_wedged_event(struct drm_device *dev, unsigned long method, + struct drm_wedge_task_info *info) { - const char *recovery = NULL; - unsigned int len, opt; - /* Event string length up to 28+ characters with available methods */ - char event_string[32]; - char *envp[] = { event_string, NULL }; + char event_string[WEDGE_STR_LEN], pid_string[PID_STR_LEN], comm_string[COMM_STR_LEN]; + char *envp[] = { event_string, NULL, NULL, NULL }; + const char *recovery = NULL; + unsigned int len, opt; len = scnprintf(event_string, sizeof(event_string), "%s", "WEDGED="); @@ -90,8 +94,15 @@ int drm_dev_wedged_event(struct drm_device *dev, unsigned long method) drm_info(dev, "device wedged, %s\n", method == DRM_WEDGE_RECOVERY_NONE ? "but recovered through reset" : "needs recovery"); + if (info && (info->comm[0] != '\0') && (info->pid >= 0)) { + snprintf(pid_string, sizeof(pid_string), "PID=%u", info->pid); + snprintf(comm_string, sizeof(comm_string), "TASK=%s", info->comm); + envp[1] = pid_string; + envp[2] = comm_string; + } + return kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, envp); } -EXPORT_SYMBOL(drm_dev_wedged_event); +EXPORT_SYMBOL(kcl_drm_dev_wedged_event); #endif /* HAVE_DRM_DEV_WEDGED_EVENT */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index de90ff15e4c9e..7c1d32b57bb2f 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -69,6 +69,7 @@ #include #include #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" @@ -144,7 +145,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 index 63ed3acc6c04c..64e4926c74f1d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 @@ -1,14 +1,17 @@ dnl # +dnl # commit v6.16-rc1-333-g183bccafa176 +dnl # drm: Create a task info option for wedge events +dnl # dnl # commit v6.14-rc1-238-gb7cf9f4ac1b8 dnl # drm: Introduce device wedged event dnl # AC_DEFUN([AC_AMDGPU_DRM_DEV_WEDGED_EVENT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ #include ], [ - drm_dev_wedged_event(NULL, 0); - ], [ + drm_dev_wedged_event(NULL, 0, NULL); + ], [drm_dev_wedged_event], [drivers/gpu/drm/drm_drv.c], [ AC_DEFINE(HAVE_DRM_DEV_WEDGED_EVENT, 1, [drm_dev_wedged_event() is available]) ]) diff --git a/include/kcl/kcl_drm_drv.h b/include/kcl/kcl_drm_drv.h index 631e84df47a9e..6715dd046571a 100644 --- a/include/kcl/kcl_drm_drv.h +++ b/include/kcl/kcl_drm_drv.h @@ -7,8 +7,18 @@ #include #include #include +#include +#include #ifndef HAVE_DRM_DEV_WEDGED_EVENT +/** + * struct drm_wedge_task_info - information about the guilty task of a wedge dev + */ +struct drm_wedge_task_info { + pid_t pid; + char comm[TASK_COMM_LEN]; +}; + /* * Recovery methods for wedged device in order of less to more side-effects. * To be used with drm_dev_wedged_event() as recovery @method. Callers can @@ -18,7 +28,9 @@ #define DRM_WEDGE_RECOVERY_REBIND BIT(1) /* unbind + bind driver */ #define DRM_WEDGE_RECOVERY_BUS_RESET BIT(2) /* unbind + reset bus device + bind */ -int drm_dev_wedged_event(struct drm_device *dev, unsigned long method); +int kcl_drm_dev_wedged_event(struct drm_device *dev, unsigned long method, + struct drm_wedge_task_info *info); +#define drm_dev_wedged_event kcl_drm_dev_wedged_event #endif /* HAVE_DRM_DEV_WEDGED_EVENT */ #endif /* AMDKCL_DRM_DRV_H */ From 5d62eb79aaafe69602a4136205b8be35daeeeb3f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 21 Jul 2025 17:39:12 +0800 Subject: [PATCH 1563/2653] drm/amdkcl: test if kmap_local_page_try_from_panic() is available It's caused by 718370ff283284f191155a5eb9d4f376aaf93bb8 "drm/ttm: Add ttm_bo_kmap_try_from_panic()" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../dkms/m4/kmap_local_page_try_from_panic.m4 | 17 +++++++++++++++++ include/kcl/kcl_highmem-internal.h | 19 ++++++++++++++++++- 3 files changed, 36 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/kmap_local_page_try_from_panic.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ee24c1243d5d2..2293be29cf4e4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -284,6 +284,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TIMER_DELETE AC_AMDGPU_IRQ_DOMAIN_CREATE_LINEAR AC_AMDGPU_SHMEM_WRITEOUT + AC_AMDGPU_KMAP_LOCAL_PAGE_TRY_FROM_PANIC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/kmap_local_page_try_from_panic.m4 b/drivers/gpu/drm/amd/dkms/m4/kmap_local_page_try_from_panic.m4 new file mode 100644 index 0000000000000..d5e1f0fe49cab --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kmap_local_page_try_from_panic.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.15-rc1-272-g8702048bb831 +dnl # mm/kmap: Add kmap_local_page_try_from_panic() +dnl # +AC_DEFUN([AC_AMDGPU_KMAP_LOCAL_PAGE_TRY_FROM_PANIC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + kmap_local_page_try_from_panic(NULL); + ], [ + AC_DEFINE(HAVE_KMAP_LOCAL_PAGE_TRY_FROM_PANIC, 1, + [kmap_local_page_try_from_panic() is available]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_highmem-internal.h b/include/kcl/kcl_highmem-internal.h index 7304f188d7c2d..c5f1aa90b5c7d 100644 --- a/include/kcl/kcl_highmem-internal.h +++ b/include/kcl/kcl_highmem-internal.h @@ -36,6 +36,23 @@ do { \ } while (0) #endif /* kunmap_local */ - +#ifdef CONFIG_HIGHMEM +#ifndef HAVE_KMAP_LOCAL_PAGE_TRY_FROM_PANIC +static inline void *kmap_local_page_try_from_panic(struct page *page) +{ + if (!PageHighMem(page)) + return page_address(page); + /* If the page is in HighMem, it's not safe to kmap it.*/ + return NULL; +} +#endif +#else +#ifndef HAVE_KMAP_LOCAL_PAGE_TRY_FROM_PANIC +static inline void *kmap_local_page_try_from_panic(struct page *page) +{ + return page_address(page); +} +#endif +#endif #endif From 1560e8407cb94f6b0d863b56aea6b43a53fad85a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 22 Jul 2025 10:57:53 +0800 Subject: [PATCH 1564/2653] drm/amdkcl: test if pm_hibernate_is_recovering() is available It's caused by aba06c660d01fc8c8634d45cdb451439c4695d6c "drm/amdgpu: do not resume device in thaw for normal hibernation" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/pm_hibernate_is_recovering.m4 | 17 +++++++++++++++++ include/kcl/kcl_suspend.h | 10 ++++++++-- 4 files changed, 28 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pm_hibernate_is_recovering.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index dc3e67067eb1c..38fe48bdcb618 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2729,9 +2729,11 @@ static int amdgpu_pmops_thaw(struct device *dev) { struct drm_device *drm_dev = dev_get_drvdata(dev); +#if defined(HAVE_PM_HIBERNATE_IS_RECOVERING) || !defined(CONFIG_PM_SLEEP) /* do not resume device if it's normal hibernation */ if (!pm_hibernate_is_recovering()) return 0; +#endif return amdgpu_device_resume(drm_dev, true); } diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2293be29cf4e4..251ab364ed13f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -285,6 +285,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IRQ_DOMAIN_CREATE_LINEAR AC_AMDGPU_SHMEM_WRITEOUT AC_AMDGPU_KMAP_LOCAL_PAGE_TRY_FROM_PANIC + AC_AMDGPU_PM_HIBERNATE_IS_RECOVERING AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_hibernate_is_recovering.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_hibernate_is_recovering.m4 new file mode 100644 index 0000000000000..43400adb13498 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm_hibernate_is_recovering.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.16-rc6-1339-g9b934e465aaf +dnl # PM: hibernate: add new api pm_hibernate_is_recovering() +dnl # +AC_DEFUN([AC_AMDGPU_PM_HIBERNATE_IS_RECOVERING], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pm_hibernate_is_recovering(); + ], [ + AC_DEFINE(HAVE_PM_HIBERNATE_IS_RECOVERING, 1, + [pm_hibernate_is_recovering() is available]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_suspend.h b/include/kcl/kcl_suspend.h index e08385f9aedaa..ca37c821757b4 100644 --- a/include/kcl/kcl_suspend.h +++ b/include/kcl/kcl_suspend.h @@ -4,19 +4,25 @@ #include -#ifndef HAVE_KSYS_SYNC_HELPER #ifdef CONFIG_PM_SLEEP +#ifndef HAVE_KSYS_SYNC_HELPER extern void _kcl_ksys_sync_helper(void); static inline void ksys_sync_helper(void) { _kcl_ksys_sync_helper(); } +#endif /* HAVE_KSYS_SYNC_HELPER */ #else +#ifndef HAVE_KSYS_SYNC_HELPER static inline void ksys_sync_helper(void) {} -#endif /* CONFIG_PM_SLEEP */ #endif /* HAVE_KSYS_SYNC_HELPER */ +#ifndef HAVE_PM_HIBERNATE_IS_RECOVERING +static inline bool pm_hibernate_is_recovering(void) { return false; } +#endif +#endif /* CONFIG_PM_SLEEP */ + #ifndef HAVE_PM_SUSPEND_VIA_FIRMWARE static inline bool pm_suspend_via_firmware(void) { return false; } From b6b592af735581c3b2bdb46e9c04a479c8b77c75 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 26 Jun 2025 16:45:25 +0800 Subject: [PATCH 1565/2653] drm/amdkcl: test whether drm_gem_is_imported() is available It's caused by 5f8ab7454 "drm/amdgpu: Test for imported buffers with drm_gem_is_imported()" Signed-off-by: Yang Su Reviewed-by: Bob Zhou drm/amdkcl:fix dma_buf is NULL in amdgpu_dmabuf_is_xgmi_accessible The function drm_gem_is_imported() directly accesses obj->dma without first verifying its validity. Add a NULL check to prevent potential kernel crashes when handling imported objects without DMA buffers. Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm_gem.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_gem.h | 17 +++++++++++++++++ 4 files changed, 37 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_gem.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 72d686290d609..90ea626ba5aca 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -586,6 +586,9 @@ /* drm_format_info.block_w and rm_format_info.block_h is available */ #define HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED 1 +/* drm_gem_is_imported() is available */ +#define HAVE_DRM_GEM_IS_IMPORTED 1 + /* drm_gem_object_funcs->vmap() has 2 args */ #define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_gem.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_gem.m4 new file mode 100644 index 0000000000000..a8110c2b201b0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_gem.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.14-rc4-395-gb57aa47d39e9 +dnl # drm/gem: Test for imported GEM buffers with helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_IS_IMPORTED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_gem_is_imported(NULL); + ],[ + AC_DEFINE(HAVE_DRM_GEM_IS_IMPORTED, 1, + [drm_gem_is_imported() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 251ab364ed13f..0d65c69a52972 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -286,6 +286,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SHMEM_WRITEOUT AC_AMDGPU_KMAP_LOCAL_PAGE_TRY_FROM_PANIC AC_AMDGPU_PM_HIBERNATE_IS_RECOVERING + AC_AMDGPU_DRM_GEM_IS_IMPORTED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_gem.h b/include/kcl/kcl_drm_gem.h index da5df184d9d58..82485f6798b69 100644 --- a/include/kcl/kcl_drm_gem.h +++ b/include/kcl/kcl_drm_gem.h @@ -35,6 +35,9 @@ #define __KCL_KCL_DRM_GEM_H__ #include +#ifndef HAVE_DRM_GEM_IS_IMPORTED +#include +#endif #ifdef HAVE_DRM_GEM_OBJECT_RESV #define amdkcl_gem_resvp(bo) (bo->resv) @@ -79,4 +82,18 @@ static inline bool drm_gem_object_is_shared_for_memory_stats(struct drm_gem_obje } #endif /* HAVE_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS */ +#ifndef HAVE_DRM_GEM_IS_IMPORTED +/** + * drm_gem_is_imported() - Tests if GEM object's buffer has been imported + * @obj: the GEM object + * + * Returns: + * True if the GEM object's buffer has been imported, false otherwise + */ +static inline bool drm_gem_is_imported(const struct drm_gem_object *obj) +{ + /* The dma-buf's priv field points to the original GEM object. */ + return obj->dma_buf && (obj->dma_buf->priv != obj); +} +#endif #endif From 7d0ac177929d85f0eaadc769ad27ecd568e57884 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 22 Jul 2025 11:37:09 +0800 Subject: [PATCH 1566/2653] drm/amdkcl: test if dma_fence_init64() is available It's caused by bf33a0003d9e3b0546f2d7e91bebfd67af59f275 "dma-fence: Use a flag for 64-bit seqnos" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/dma_fence_init64.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma_fence.h | 4 ++++ 3 files changed, 22 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma_fence_init64.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_fence_init64.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_fence_init64.m4 new file mode 100644 index 0000000000000..d39fec01539a6 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_fence_init64.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.15-rc5-1889-gbf33a0003d9e +dnl # dma-fence: Use a flag for 64-bit seqnos +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_INIT64], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_init64(NULL, NULL, NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_INIT64, 1, + [dma_fence_init64() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0d65c69a52972..907f521c3ce76 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -287,6 +287,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KMAP_LOCAL_PAGE_TRY_FROM_PANIC AC_AMDGPU_PM_HIBERNATE_IS_RECOVERING AC_AMDGPU_DRM_GEM_IS_IMPORTED + AC_AMDGPU_DMA_FENCE_INIT64 AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_dma_fence.h b/include/kcl/kcl_dma_fence.h index a24278c214244..cd1f7814fceee 100644 --- a/include/kcl/kcl_dma_fence.h +++ b/include/kcl/kcl_dma_fence.h @@ -74,4 +74,8 @@ static inline bool dma_fence_is_later_or_same(struct dma_fence *f1, return f1 == f2 || dma_fence_is_later(f1, f2); } #endif /*HAVE_DMA_FENCE_IS_LATER_OR_SAME*/ + +#ifndef HAVE_DMA_FENCE_INIT64 +#define dma_fence_init64 dma_fence_init +#endif #endif From 2e4e18129ee425872b93c1756fbb0734ae746eed Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 22 Jul 2025 13:15:16 +0800 Subject: [PATCH 1567/2653] drm/amdkcl: test if drm_file->debugfs_client is available It's caused by c03ea34cbf88dd778197a929b3269003567def55 "drm/amdgpu: add support of debugfs for mqd information" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../dkms/m4/struct_drm_file_debugfs_client.m4 | 18 ++++++++++++++++++ 4 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_file_debugfs_client.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 53c0b75791ac7..518121e9e8754 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -2184,8 +2184,10 @@ static const struct file_operations amdgpu_pt_info_fops = { void amdgpu_debugfs_vm_init(struct drm_file *file) { +#ifdef STRUCT_DRM_FILE_DEBUGFS_CLIENT debugfs_create_file("vm_pagetable_info", 0444, file->debugfs_client, file, &amdgpu_pt_info_fops); +#endif } #else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index bceb284358aef..8c2cdbe2f7a78 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -525,6 +525,7 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) } } +#ifdef STRUCT_DRM_FILE_DEBUGFS_CLIENT queue_name = kasprintf(GFP_KERNEL, "queue-%d", qid); if (!queue_name) return -ENOMEM; @@ -535,6 +536,7 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) debugfs_create_file("mqd_info", 0444, queue->debugfs_queue, queue, &amdgpu_mqd_info_fops); #endif kfree(queue_name); +#endif args->out.queue_id = qid; diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 907f521c3ce76..0d4d1a68c73f3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -288,6 +288,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PM_HIBERNATE_IS_RECOVERING AC_AMDGPU_DRM_GEM_IS_IMPORTED AC_AMDGPU_DMA_FENCE_INIT64 + AC_AMDGPU_DRM_FILE_DEBUGFS_CLIENT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_file_debugfs_client.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_file_debugfs_client.m4 new file mode 100644 index 0000000000000..67e95bb8cf7a8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_file_debugfs_client.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v6.16-rc1-406-g1fd45bc21cec +dnl # drm: add debugfs support on per client-id basis +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FILE_DEBUGFS_CLIENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_file file; + file.debugfs_client = NULL; + ], [ + AC_DEFINE(STRUCT_DRM_FILE_DEBUGFS_CLIENT, 1, + [drm_file->debugfs_client is available]) + ]) + ]) +]) + From 7764a71f1bf2c66880e64c27052eef728a3a0c14 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 22 Jul 2025 17:34:03 +0800 Subject: [PATCH 1568/2653] drm/amdkcl: wrap code under __amdkcl_assign_str It's caused by d6b7b46232b78510a12e351b738f493021edf8c3 "drm/sched: Add device name to the drm_sched_process_job event" Signed-off-by: Bob Zhou --- drivers/gpu/drm/scheduler/gpu_scheduler_trace.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h b/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h index 0bd32514d54c4..6e1ce1fe8807f 100644 --- a/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h +++ b/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h @@ -72,7 +72,7 @@ DECLARE_EVENT_CLASS(drm_sched_job, __entry->job_count = spsc_queue_count(&entity->job_queue); __entry->hw_job_count = atomic_read( &sched_job->sched->credit_count); - __assign_str(dev); + __amdkcl_assign_str(dev, dev_name(sched_job->sched->dev)); __entry->fence_context = sched_job->s_fence->finished.context; __entry->fence_seqno = sched_job->s_fence->finished.seqno; __entry->client_id = sched_job->s_fence->drm_client_id; From 293a1b474491f6f7b0b0943a0e507f0ba5ab7e1d Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 23 Jul 2025 14:19:10 +0800 Subject: [PATCH 1569/2653] drm/amdkcl: test if drm_file->client_id is available It's caused by 2956554823cedb390b7ec4534afa898176317638 "drm/sched: Store the drm client_id in drm_sched_fence" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 +++++ .../amd/dkms/m4/struct_drm_memoty_status.m4 | 19 +++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 6b4b67a6cfcca..ad143e485ccfb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -297,9 +297,14 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p, } for (i = 0; i < p->gang_size; ++i) { +#ifdef HAVE_DRM_FILE_CLIENT_ID ret = amdgpu_job_alloc(p->adev, vm, p->entities[i], vm, num_ibs[i], &p->jobs[i], p->filp->client_id); +#else + ret = amdgpu_job_alloc(p->adev, vm, p->entities[i], vm, + num_ibs[i], &p->jobs[i], 0); +#endif if (ret) goto free_all_kdata; switch (p->adev->enforce_isolation[fpriv->xcp_id]) { diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 index 3e25ff65320cf..62c60fa842710 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 @@ -18,6 +18,25 @@ AC_DEFUN([AC_AMDGPU_DRM_PRINT_MEMORY_STATS], [ ]) ]) +dnl # +dnl # v6.4-rc1-190-g3f09a0cd4ea3 +dnl # drm: Add common fdinfo helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FILE_CLIENT_ID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_file *filp = NULL; + filp->client_id = 0; + ], [ + AC_DEFINE(HAVE_DRM_FILE_CLIENT_ID, 1, + [struct drm_file->client_id is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_FILE], [ AC_AMDGPU_DRM_PRINT_MEMORY_STATS + AC_AMDGPU_DRM_FILE_CLIENT_ID ]) From ba2824daea4a51ec91e629277480b24590fa49cb Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 16 Apr 2025 13:43:35 -0400 Subject: [PATCH 1570/2653] drm/amdgu: add host trap interface to support gfx12.0.* PC Sampling. Signed-off-by: James Zhu Reviewed-by: Vladimir Indic --- .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c | 72 ++++++++++++++++++- 1 file changed, 71 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c index 6f0dc23c901b8..2ffbf42e01c01 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c @@ -25,6 +25,8 @@ #include "gc/gc_12_0_0_offset.h" #include "gc/gc_12_0_0_sh_mask.h" #include "soc24.h" +#include "navi10_enum.h" + #include static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe, @@ -367,6 +369,73 @@ static uint32_t kgd_gfx_v12_hqd_sdma_get_doorbell(struct amdgpu_device *adev, return 0; } +static uint32_t kgd_gfx_v12_get_hosttrap_status(struct amdgpu_device *adev, + uint32_t inst) +{ + uint32_t sq_debug_hosttrap_status = 0x0; + int i, j; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { + amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, inst); + sq_debug_hosttrap_status = + RREG32_SOC15(GC, GET_INST(GC, inst), regSQ_DEBUG_HOST_TRAP_STATUS); + + if (sq_debug_hosttrap_status) + goto out; + } + } + +out: + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + mutex_unlock(&adev->grbm_idx_mutex); + + return sq_debug_hosttrap_status; +} + +/* + * gfx12 has no way to broadcast to all WGPs but only a single SIMD within + * that WGP. Here we broadcast to 1 wave-slot on all 4 SIMDs within all WGPs, + * so target_simd is not really used for gfx12. +*/ +static uint32_t kgd_v12_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t __always_unused *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) +{ + if (method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + uint32_t value = 0; + uint32_t sq_hosttrap_status = 0x0; + + sq_hosttrap_status = kgd_gfx_v12_get_hosttrap_status(adev, inst); + /* skip when last host trap request is still pending to complete */ + if (sq_hosttrap_status) + return 0; + + value = REG_SET_FIELD(value, SQ_CMD, CMD, SQ_IND_CMD_CMD_TRAP); + value = REG_SET_FIELD(value, SQ_CMD, MODE, SQ_IND_CMD_MODE_SINGLE); + + /* select *target_wave_slot */ + value = REG_SET_FIELD(value, SQ_CMD, WAVE_ID, (*target_wave_slot)++); + /* set TrapID 4 for HOSTTRAP */ + value = REG_SET_FIELD(value, SQ_CMD, DATA, 0x4); + + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + WREG32_SOC15(GC, GET_INST(GC, inst), regSQ_CMD, value); + mutex_unlock(&adev->grbm_idx_mutex); + + *target_wave_slot %= 16; + } else { + dev_dbg(adev->dev, "PC Sampling method %d not supported.", method); + return -EOPNOTSUPP; + } + return 0; +} + const struct kfd2kgd_calls gfx_v12_kfd2kgd = { .init_interrupts = init_interrupts_v12, .hqd_dump = hqd_dump_v12, @@ -380,5 +449,6 @@ const struct kfd2kgd_calls gfx_v12_kfd2kgd = { .set_wave_launch_mode = kgd_gfx_v12_set_wave_launch_mode, .set_address_watch = kgd_gfx_v12_set_address_watch, .clear_address_watch = kgd_gfx_v12_clear_address_watch, - .hqd_sdma_get_doorbell = kgd_gfx_v12_hqd_sdma_get_doorbell + .hqd_sdma_get_doorbell = kgd_gfx_v12_hqd_sdma_get_doorbell, + .trigger_pc_sample_trap = kgd_v12_trigger_pc_sample_trap, }; From 68a1f224a7a8c0f95842b78a7216ce779a1406a1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 24 Jul 2025 11:10:55 +0800 Subject: [PATCH 1571/2653] drm/amdkcl: wrap code under amdkcl_ttm_resv() It's caused by 97e000acf2e20a86a50a0ec8c2739f0846f37509 "drm/ttm: fix error handling in ttm_buffer_object_transfer" Signed-off-by: Bob Zhou --- drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index a1fc97706b95e..be7842a45512c 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -277,7 +277,7 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo, ret = dma_resv_trylock(&amdkcl_ttm_resv(&fbo->base)); WARN_ON(!ret); - ret = dma_resv_reserve_fences(&fbo->base.base._resv, 1); + ret = dma_resv_reserve_fences(&amdkcl_ttm_resv(&fbo->base), 1); if (ret) { dma_resv_unlock(&fbo->base.base._resv); kfree(fbo); From d434e1670fbc437d7638c7944e4a3329fe43a9d6 Mon Sep 17 00:00:00 2001 From: Lancelot SIX Date: Mon, 24 Mar 2025 10:59:10 +0000 Subject: [PATCH 1572/2653] drm/amdkfd: ignore sampling traps if SAVECTX also present in trap handler The trap handler can be entered for multiple reasons at the same time. It is possible to enter the trap handler to process both a context save and a sampling trap (host trap or stochastic sampling based). In that case, the general principle applies: jump to the 2nd level trap handler to let it handler the trap, and when the 2nd level trap handler calls s_rfe, the wave will re-enter the trap handler to handle the context save. However, it is possible that the sampling rate is too high, in which case a new sample trap might come in to the wave before re-entering for context save, effectively preventing the context save to succeed. This patch proposes to ignore sampling traps if a context save request is present. Signed-off-by: Lancelot SIX Reviewed-by: James Zhu Tested-by: James Zhu Reviewed-by: Jay Cornwall --- .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 1565 +++++++++-------- .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 22 + 2 files changed, 818 insertions(+), 769 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index 75188c3b01996..d8018f87d9146 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -274,9 +274,12 @@ static const uint32_t cwsr_trap_gfx8_hex[] = { static const uint32_t cwsr_trap_gfx9_hex[] = { - 0xbf820001, 0xbf820269, + 0xbf820001, 0xbf82026f, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, + 0xbf0c8a7b, 0xbf850004, + 0xbf0c986d, 0xbf850002, + 0x896dff6d, 0x01ff0000, 0x866eff78, 0x00002000, 0xbf840008, 0xbf0d986d, 0xbf850023, 0x866eff7b, @@ -1311,9 +1314,12 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { }; static const uint32_t cwsr_trap_arcturus_hex[] = { - 0xbf820001, 0xbf8202e5, + 0xbf820001, 0xbf8202eb, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, + 0xbf0c8a7b, 0xbf850004, + 0xbf0c986d, 0xbf850002, + 0x896dff6d, 0x01ff0000, 0x866eff78, 0x00002000, 0xbf840008, 0xbf0d986d, 0xbf850023, 0x866eff7b, @@ -1800,9 +1806,12 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { }; static const uint32_t cwsr_trap_aldebaran_hex[] = { - 0xbf820001, 0xbf8202f0, + 0xbf820001, 0xbf8202f6, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, + 0xbf0c8a7b, 0xbf850004, + 0xbf0c986d, 0xbf850002, + 0x896dff6d, 0x01ff0000, 0x866eff78, 0x00002000, 0xbf840008, 0xbf0d986d, 0xbf850023, 0x866eff7b, @@ -3178,230 +3187,176 @@ static const uint32_t cwsr_trap_gfx11_hex[] = { }; static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { - 0xbf820001, 0xbf8202fb, + 0xbf820001, 0xbf82030c, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, - 0x866eff78, 0x00002000, - 0xbf84000a, 0xbf0d986d, - 0xbf850023, 0xbf0d9a7b, - 0xbf850021, 0x866eff7b, - 0x00000400, 0xbf85006f, - 0xbf8e0010, 0xb8fbf803, - 0xbf82fffa, 0x866eff7b, - 0x03800900, 0xbf850017, - 0x866eff7b, 0x000071ff, - 0xbf840008, 0x866fff7b, - 0x00007080, 0xbf840001, - 0xbeee1a87, 0xb8eff801, - 0x8e6e8c6e, 0x866e6f6e, - 0xbf85000c, 0xbf0d986d, - 0xbf850003, 0x866eff6d, - 0x00ff0000, 0xbf850007, - 0xbf0d986d, 0xbf850006, - 0xbf0d9a7b, 0xbf850004, - 0x866eff7b, 0x00000400, - 0xbf850052, 0xbeed1a9d, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8979ff79, 0xfc000000, - 0x87797a79, 0xba7ff807, - 0x00000000, 0xb8faf812, - 0xb8fbf813, 0x8efa887a, - 0xbf0d8f7b, 0xbf840002, - 0x877bff7b, 0xffff0000, - 0xc0031cfd, 0x00000010, - 0xc0071bbd, 0x00000000, - 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x8e739773, - 0x8979ff79, 0x03800000, - 0x87797379, 0xbf0d986d, - 0xbf840008, 0xbf0d9879, - 0xbf840002, 0xbeed1a9d, - 0xbf820004, 0x896dff6d, - 0x01ff0000, 0xba7f0583, - 0x00000000, 0xb8f3f803, - 0xbf0d9a73, 0xbf840006, - 0xbf0d9979, 0xbf840002, - 0xbeed1a9d, 0xbf820002, + 0x866eff7b, 0x04000400, + 0xbf06ff6e, 0x04000400, + 0xbf840003, 0xbefb189a, 0xba7f0683, 0x00000000, - 0xbf0d9d6d, 0xbeed189d, - 0xbf840013, 0xbef91898, - 0xbef91899, 0xbeed189d, - 0x86ee6e6e, 0xbf840001, - 0xbe801d6e, 0x866eff6d, - 0x01ff0000, 0xbf850005, - 0x8778ff78, 0x00002000, - 0x80ec886c, 0x82ed806d, - 0xbf820005, 0x866eff6d, - 0x01000000, 0xbf850002, - 0x806c846c, 0x826d806d, - 0x866dff6d, 0x0000ffff, - 0x8f7a8b79, 0x867aff7a, - 0x001f8000, 0xb97af807, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e8378, 0xb96ee0c2, - 0xbf800002, 0xb9780002, - 0xbe801f6c, 0x866dff6d, - 0x0000ffff, 0xbefa0080, - 0xb97a0283, 0xb8faf807, + 0xbf0c8a7b, 0xbf850007, + 0xbf0c986d, 0xbf850005, + 0xbefb1896, 0xba7f0583, + 0x00000000, 0x896dff6d, + 0x01ff0000, 0x866eff78, + 0x00002000, 0xbf84000a, + 0xbf0d986d, 0xbf850023, + 0xbf0d9a7b, 0xbf850021, + 0x866eff7b, 0x00000400, + 0xbf85006f, 0xbf8e0010, + 0xb8fbf803, 0xbf82fffa, + 0x866eff7b, 0x03800900, + 0xbf850017, 0x866eff7b, + 0x000071ff, 0xbf840008, + 0x866fff7b, 0x00007080, + 0xbf840001, 0xbeee1a87, + 0xb8eff801, 0x8e6e8c6e, + 0x866e6f6e, 0xbf85000c, + 0xbf0d986d, 0xbf850003, + 0x866eff6d, 0x00ff0000, + 0xbf850007, 0xbf0d986d, + 0xbf850006, 0xbf0d9a7b, + 0xbf850004, 0x866eff7b, + 0x00000400, 0xbf850052, + 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8979ff79, 0xfc000000, 0x87797a79, 0xba7ff807, 0x00000000, - 0xbeee007e, 0xbeef007f, - 0xbefe0180, 0xbf900004, - 0x877a8478, 0xb97af802, - 0xbf8e0002, 0xbf88fffe, - 0xb8fa2985, 0x807a817a, - 0x8e7a8a7a, 0x8e7a817a, - 0xb8fb1605, 0x807b817b, - 0x8e7b867b, 0x807a7b7a, - 0x807a7e7a, 0x827b807f, - 0x867bff7b, 0x0000ffff, - 0xc04b1c3d, 0x00000050, - 0xbf8cc07f, 0xc04b1d3d, - 0x00000060, 0xbf8cc07f, - 0xc0431e7d, 0x00000074, - 0xbf8cc07f, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0xbef1007c, - 0xbef00080, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b3a, + 0xb8faf812, 0xb8fbf813, + 0x8efa887a, 0xbf0d8f7b, + 0xbf840002, 0x877bff7b, + 0xffff0000, 0xc0031cfd, + 0x00000010, 0xc0071bbd, + 0x00000000, 0xc0071ebd, + 0x00000008, 0xbf8cc07f, + 0x8e739773, 0x8979ff79, + 0x03800000, 0x87797379, + 0xbf0d986d, 0xbf840008, + 0xbf0d9879, 0xbf840002, + 0xbeed1a9d, 0xbf820004, + 0x896dff6d, 0x01ff0000, + 0xba7f0583, 0x00000000, + 0xb8f3f803, 0xbf0d9a73, + 0xbf840006, 0xbf0d9979, + 0xbf840002, 0xbeed1a9d, + 0xbf820002, 0xba7f0683, + 0x00000000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840013, + 0xbef91898, 0xbef91899, + 0xbeed189d, 0x86ee6e6e, + 0xbf840001, 0xbe801d6e, + 0x866eff6d, 0x01ff0000, + 0xbf850005, 0x8778ff78, + 0x00002000, 0x80ec886c, + 0x82ed806d, 0xbf820005, + 0x866eff6d, 0x01000000, + 0xbf850002, 0x806c846c, + 0x826d806d, 0x866dff6d, + 0x0000ffff, 0x8f7a8b79, + 0x867aff7a, 0x001f8000, + 0xb97af807, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e8378, + 0xb96ee0c2, 0xbf800002, + 0xb9780002, 0xbe801f6c, + 0x866dff6d, 0x0000ffff, + 0xbefa0080, 0xb97a0283, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8979ff79, 0xfc000000, + 0x87797a79, 0xba7ff807, + 0x00000000, 0xbeee007e, + 0xbeef007f, 0xbefe0180, + 0xbf900004, 0x877a8478, + 0xb97af802, 0xbf8e0002, + 0xbf88fffe, 0xb8fa2985, + 0x807a817a, 0x8e7a8a7a, + 0x8e7a817a, 0xb8fb1605, + 0x807b817b, 0x8e7b867b, + 0x807a7b7a, 0x807a7e7a, + 0x827b807f, 0x867bff7b, + 0x0000ffff, 0xc04b1c3d, + 0x00000050, 0xbf8cc07f, + 0xc04b1d3d, 0x00000060, + 0xbf8cc07f, 0xc0431e7d, + 0x00000074, 0xbf8cc07f, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0xbef1007c, 0xbef00080, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611b7a, 0x0000007c, + 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bba, + 0xbefc0070, 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bfa, 0x0000007c, + 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611e3a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8fbf803, 0xbefe007c, - 0xbefc0070, 0xc0611efa, + 0xbefc0070, 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a3a, 0x0000007c, + 0xc0611e3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8fbf803, + 0xbefe007c, 0xbefc0070, + 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8f1f801, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, + 0xbefc0070, 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, - 0xbf108080, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840064, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf840060, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0xbefe007c, 0xbefc0070, + 0xc0611a7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8f1f801, + 0xbefe007c, 0xbefc0070, + 0xc0611c7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbf108080, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -3420,95 +3375,94 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb2b05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb4306, 0x867bc17b, + 0xbf840064, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf840060, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, + 0xd2890000, 0x00000901, 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, + 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xb8fb2985, - 0x807b817b, 0x8e7b837b, - 0xb8fa2b05, 0x807a817a, - 0x8e7a827a, 0x80fb7a7b, - 0x867b7b7b, 0xbf84007a, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2b05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, 0x807bff7b, 0x00001000, - 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850059, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -3547,139 +3501,203 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffa9, - 0xbf9c0000, 0xbf820016, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffeb, 0xbf9c0000, - 0xbf8200ee, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf84001f, + 0xbf85ffef, 0xbf9c0000, + 0xb8fb2985, 0x807b817b, + 0x8e7b837b, 0xb8fa2b05, + 0x807a817a, 0x8e7a827a, + 0x80fb7a7b, 0x867b7b7b, + 0xbf84007a, 0x807bff7b, + 0x00001000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf8200ee, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf84001f, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf84001a, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, 0xbefe00c1, 0xbeff00c1, - 0xb8ef4306, 0x866fc16f, - 0xbf84001a, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2b05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xb8ef2985, 0x806f816f, - 0x8e6f836f, 0xb8f92b05, - 0x80798179, 0x8e798279, - 0x80ef796f, 0x866f6f6f, - 0xbf84001a, 0x806fff6f, - 0x00008000, 0xbefc0080, + 0xb8ef2b05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, - 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, - 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, - 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, - 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, - 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2985, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b79, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xbf85ffee, 0xb8ef2985, + 0x806f816f, 0x8e6f836f, + 0xb8f92b05, 0x80798179, + 0x8e798279, 0x80ef796f, + 0x866f6f6f, 0xbf84001a, + 0x806fff6f, 0x00008000, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, + 0x00000078, 0x80788478, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, + 0x00000078, 0x80788478, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, + 0x00000078, 0x80788478, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, + 0x00000078, 0x80788478, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, + 0x00000078, 0x80788478, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2985, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b79, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_gfx12_hex[] = { @@ -4211,230 +4229,176 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { }; static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { - 0xbf820001, 0xbf8202e9, + 0xbf820001, 0xbf8202fa, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, - 0x866eff78, 0x00002000, - 0xbf84000a, 0xbf0d986d, - 0xbf850023, 0xbf0d9a7b, - 0xbf850021, 0x866eff7b, - 0x00000400, 0xbf85006f, - 0xbf8e0010, 0xb8fbf803, - 0xbf82fffa, 0x866eff7b, - 0x03800900, 0xbf850017, - 0x866eff7b, 0x000071ff, - 0xbf840008, 0x866fff7b, - 0x00007080, 0xbf840001, - 0xbeee1a87, 0xb8eff801, - 0x8e6e8c6e, 0x866e6f6e, - 0xbf85000c, 0xbf0d986d, - 0xbf850003, 0x866eff6d, - 0x00ff0000, 0xbf850007, - 0xbf0d986d, 0xbf850006, - 0xbf0d9a7b, 0xbf850004, - 0x866eff7b, 0x00000400, - 0xbf850052, 0xbeed1a9d, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8979ff79, 0xfc000000, - 0x87797a79, 0xba7ff807, - 0x00000000, 0xb8faf812, - 0xb8fbf813, 0x8efa887a, - 0xbf0d8f7b, 0xbf840002, - 0x877bff7b, 0xffff0000, - 0xc0031cfd, 0x00000010, - 0xc0071bbd, 0x00000000, - 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x8e739773, - 0x8979ff79, 0x03800000, - 0x87797379, 0xbf0d986d, - 0xbf840008, 0xbf0d9879, - 0xbf840002, 0xbeed1a9d, - 0xbf820004, 0x896dff6d, - 0x01ff0000, 0xba7f0583, - 0x00000000, 0xb8f3f803, - 0xbf0d9a73, 0xbf840006, - 0xbf0d9979, 0xbf840002, - 0xbeed1a9d, 0xbf820002, + 0x866eff7b, 0x04000400, + 0xbf06ff6e, 0x04000400, + 0xbf840003, 0xbefb189a, 0xba7f0683, 0x00000000, - 0xbf0d9d6d, 0xbeed189d, - 0xbf840013, 0xbef91898, - 0xbef91899, 0xbeed189d, - 0x86ee6e6e, 0xbf840001, - 0xbe801d6e, 0x866eff6d, - 0x01ff0000, 0xbf850005, - 0x8778ff78, 0x00002000, - 0x80ec886c, 0x82ed806d, - 0xbf820005, 0x866eff6d, - 0x01000000, 0xbf850002, - 0x806c846c, 0x826d806d, - 0x866dff6d, 0x0000ffff, - 0x8f7a8b79, 0x867aff7a, - 0x001f8000, 0xb97af807, - 0x86fe7e7e, 0x86ea6a6a, - 0x8f6e8378, 0xb96ee0c2, - 0xbf800002, 0xb9780002, - 0xbe801f6c, 0x866dff6d, - 0x0000ffff, 0xbefa0080, - 0xb97a0283, 0xb8faf807, + 0xbf0c8a7b, 0xbf850007, + 0xbf0c986d, 0xbf850005, + 0xbefb1896, 0xba7f0583, + 0x00000000, 0x896dff6d, + 0x01ff0000, 0x866eff78, + 0x00002000, 0xbf84000a, + 0xbf0d986d, 0xbf850023, + 0xbf0d9a7b, 0xbf850021, + 0x866eff7b, 0x00000400, + 0xbf85006f, 0xbf8e0010, + 0xb8fbf803, 0xbf82fffa, + 0x866eff7b, 0x03800900, + 0xbf850017, 0x866eff7b, + 0x000071ff, 0xbf840008, + 0x866fff7b, 0x00007080, + 0xbf840001, 0xbeee1a87, + 0xb8eff801, 0x8e6e8c6e, + 0x866e6f6e, 0xbf85000c, + 0xbf0d986d, 0xbf850003, + 0x866eff6d, 0x00ff0000, + 0xbf850007, 0xbf0d986d, + 0xbf850006, 0xbf0d9a7b, + 0xbf850004, 0x866eff7b, + 0x00000400, 0xbf850052, + 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8979ff79, 0xfc000000, 0x87797a79, 0xba7ff807, 0x00000000, - 0xbeee007e, 0xbeef007f, - 0xbefe0180, 0xbf900004, - 0x877a8478, 0xb97af802, - 0xbf8e0002, 0xbf88fffe, - 0xb8fa2985, 0x807a817a, - 0x8e7a8a7a, 0x8e7a817a, - 0xb8fb1605, 0x807b817b, - 0x8e7b867b, 0x807a7b7a, - 0x807a7e7a, 0x827b807f, - 0x867bff7b, 0x0000ffff, - 0xc04b1c3d, 0x00000050, - 0xbf8cc07f, 0xc04b1d3d, - 0x00000060, 0xbf8cc07f, - 0xc0431e7d, 0x00000074, - 0xbf8cc07f, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0xbef1007c, - 0xbef00080, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b3a, + 0xb8faf812, 0xb8fbf813, + 0x8efa887a, 0xbf0d8f7b, + 0xbf840002, 0x877bff7b, + 0xffff0000, 0xc0031cfd, + 0x00000010, 0xc0071bbd, + 0x00000000, 0xc0071ebd, + 0x00000008, 0xbf8cc07f, + 0x8e739773, 0x8979ff79, + 0x03800000, 0x87797379, + 0xbf0d986d, 0xbf840008, + 0xbf0d9879, 0xbf840002, + 0xbeed1a9d, 0xbf820004, + 0x896dff6d, 0x01ff0000, + 0xba7f0583, 0x00000000, + 0xb8f3f803, 0xbf0d9a73, + 0xbf840006, 0xbf0d9979, + 0xbf840002, 0xbeed1a9d, + 0xbf820002, 0xba7f0683, + 0x00000000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840013, + 0xbef91898, 0xbef91899, + 0xbeed189d, 0x86ee6e6e, + 0xbf840001, 0xbe801d6e, + 0x866eff6d, 0x01ff0000, + 0xbf850005, 0x8778ff78, + 0x00002000, 0x80ec886c, + 0x82ed806d, 0xbf820005, + 0x866eff6d, 0x01000000, + 0xbf850002, 0x806c846c, + 0x826d806d, 0x866dff6d, + 0x0000ffff, 0x8f7a8b79, + 0x867aff7a, 0x001f8000, + 0xb97af807, 0x86fe7e7e, + 0x86ea6a6a, 0x8f6e8378, + 0xb96ee0c2, 0xbf800002, + 0xb9780002, 0xbe801f6c, + 0x866dff6d, 0x0000ffff, + 0xbefa0080, 0xb97a0283, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8979ff79, 0xfc000000, + 0x87797a79, 0xba7ff807, + 0x00000000, 0xbeee007e, + 0xbeef007f, 0xbefe0180, + 0xbf900004, 0x877a8478, + 0xb97af802, 0xbf8e0002, + 0xbf88fffe, 0xb8fa2985, + 0x807a817a, 0x8e7a8a7a, + 0x8e7a817a, 0xb8fb1605, + 0x807b817b, 0x8e7b867b, + 0x807a7b7a, 0x807a7e7a, + 0x827b807f, 0x867bff7b, + 0x0000ffff, 0xc04b1c3d, + 0x00000050, 0xbf8cc07f, + 0xc04b1d3d, 0x00000060, + 0xbf8cc07f, 0xc0431e7d, + 0x00000074, 0xbf8cc07f, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0xbef1007c, 0xbef00080, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611b7a, 0x0000007c, + 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bba, + 0xbefc0070, 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bfa, 0x0000007c, + 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611e3a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8fbf803, 0xbefe007c, - 0xbefc0070, 0xc0611efa, + 0xbefc0070, 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a3a, 0x0000007c, + 0xc0611e3a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8fbf803, + 0xbefe007c, 0xbefc0070, + 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, - 0xb8f1f801, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, + 0xbefc0070, 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, - 0xbf108080, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb5306, - 0x867bc17b, 0xbf840052, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf84004e, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0xbefe007c, 0xbefc0070, + 0xc0611a7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xb8f1f801, + 0xbefe007c, 0xbefc0070, + 0xc0611c7a, 0x0000007c, + 0xbf8cc07f, 0x80708470, + 0xbefc007e, 0xbf108080, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf85001d, 0x24040682, - 0xd86c0000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -4444,95 +4408,94 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x680404ff, 0x00000100, - 0xd0c9006a, 0x0000f702, - 0xbf87ffe5, 0xbf820016, - 0xd1060002, 0x00011103, - 0x7e0602ff, 0x00000200, - 0xbefc00ff, 0x00010000, - 0xbe800077, 0x8677ff77, - 0xff7fffff, 0x8777ff77, - 0x00058000, 0xd8ec0000, - 0x00000002, 0xbf8cc07f, - 0xe0765000, 0x701d0002, - 0x68040702, 0xd0c9006a, - 0x0000f702, 0xbefe016a, - 0xbf87fff6, 0xbef70000, - 0xbef000ff, 0x00000400, - 0xbefe00c1, 0xbeff00c1, - 0xb8fb2b05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xb8fb2985, - 0x807b817b, 0x8e7b837b, - 0xb8fa2b05, 0x807a817a, - 0x8e7a827a, 0x80fb7a7b, - 0x867b7b7b, 0xbf84007a, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0xbefe00c1, 0xbeff00c1, + 0xb8fb5306, 0x867bc17b, + 0xbf840052, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf84004e, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85001d, + 0x24040682, 0xd86c0000, + 0x00000002, 0xbf8cc07f, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x680404ff, + 0x00000100, 0xd0c9006a, + 0x0000f702, 0xbf87ffe5, + 0xbf820016, 0xd1060002, + 0x00011103, 0x7e0602ff, + 0x00000200, 0xbefc00ff, + 0x00010000, 0xbe800077, + 0x8677ff77, 0xff7fffff, + 0x8777ff77, 0x00058000, + 0xd8ec0000, 0x00000002, + 0xbf8cc07f, 0xe0765000, + 0x701d0002, 0x68040702, + 0xd0c9006a, 0x0000f702, + 0xbefe016a, 0xbf87fff6, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2b05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, 0x807bff7b, 0x00001000, - 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850059, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -4571,140 +4534,204 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffa9, - 0xbf9c0000, 0xbf820016, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffeb, 0xbf9c0000, - 0xbf8200f4, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf840025, + 0xbf85ffef, 0xbf9c0000, + 0xb8fb2985, 0x807b817b, + 0x8e7b837b, 0xb8fa2b05, + 0x807a817a, 0x8e7a827a, + 0x80fb7a7b, 0x867b7b7b, + 0xbf84007a, 0x807bff7b, + 0x00001000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf8200f4, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf840025, 0xbefe00c1, + 0xbeff00c1, 0xb8ef5306, + 0x866fc16f, 0xbf840020, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0xe0510200, 0x781d0000, + 0xe0510300, 0x781d0000, + 0xe0510400, 0x781d0000, + 0x807cff7c, 0x00000500, + 0x8078ff78, 0x00000500, + 0xbf0a6f7c, 0xbf85fff0, 0xbefe00c1, 0xbeff00c1, - 0xb8ef5306, 0x866fc16f, - 0xbf840020, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0xe0510200, - 0x781d0000, 0xe0510300, - 0x781d0000, 0xe0510400, - 0x781d0000, 0x807cff7c, - 0x00000500, 0x8078ff78, - 0x00000500, 0xbf0a6f7c, - 0xbf85fff0, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2b05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xb8ef2985, 0x806f816f, - 0x8e6f836f, 0xb8f92b05, - 0x80798179, 0x8e798279, - 0x80ef796f, 0x866f6f6f, - 0xbf84001a, 0x806fff6f, - 0x00008000, 0xbefc0080, + 0xb8ef2b05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbf85ffee, 0xb8ef2985, + 0x806f816f, 0x8e6f836f, + 0xb8f92b05, 0x80798179, + 0x8e798279, 0x80ef796f, + 0x866f6f6f, 0xbf84001a, + 0x806fff6f, 0x00008000, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2985, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b79, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2985, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b79, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf9b0000, 0x00000000, }; diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index 4d959e219c2b4..dd2d93f6824ee 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -242,6 +242,28 @@ L_SKIP_RESTORE: s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) +#if ASIC_FAMILY >= CHIP_GC_9_4_3 + // Ignore PERF_SNAPSHOT if SAVECTX is also present + s_and_b32 ttmp2, s_save_trapsts, (SQ_WAVE_TRAPSTS_SAVECTX_MASK | SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_MASK) + s_cmp_eq_u32 ttmp2, (SQ_WAVE_TRAPSTS_SAVECTX_MASK | SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_MASK) + s_cbranch_scc0 L_NO_SAVE_AND_PERF_SNAP + s_bitset0_b32 s_save_trapsts, SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT + s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT, 1), 0 +L_NO_SAVE_AND_PERF_SNAP: +#endif + + // Ignore Host Trap if SAVECTX is also present + s_bitcmp0_b32 s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT + s_cbranch_scc1 L_NO_SAVE_AND_HT + s_bitcmp0_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc1 L_NO_SAVE_AND_HT +#if ASIC_FAMILY >= CHIP_GC_9_4_3 + s_bitset0_b32 s_save_trapsts, SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT + s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT, 1), 0 +#endif + s_andn2_b32 s_save_pc_hi, s_save_pc_hi, (S_SAVE_PC_HI_HT_MASK | S_SAVE_PC_HI_TRAP_ID_MASK) +L_NO_SAVE_AND_HT: + s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK s_cbranch_scc0 L_NOT_HALTED From ccae3bbe4208ef958b9271a6b994f65b166d8e6d Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 16 Apr 2025 13:46:39 -0400 Subject: [PATCH 1573/2653] drm/amdkfd: enhance host trap process in 1st trap handler to support multiple processes, and process correctly when s_trap and context saving exception occur simultaneously. -v2: update comments advised from Lancelot -v3: update advised from Jay -v4: remove state bit S_SAVE_PC_HI_NEED_2ND_LVL_TH_SHIFT -v5: add STATUS.HALT handling Co-authored-by: Lancelot SIX Co-authored-by: Joseph Greathouse Signed-off-by: James Zhu Reviewed-by: Lancelot SIX Reviewed-by: Jay Cornwall --- .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 903 +++++++++--------- .../amd/amdkfd/cwsr_trap_handler_gfx12.asm | 78 +- 2 files changed, 529 insertions(+), 452 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index d8018f87d9146..d2f250d29d83b 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -3701,14 +3701,18 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { }; static const uint32_t cwsr_trap_gfx12_hex[] = { - 0xbfa00001, 0xbfa002a2, + 0xbfa00001, 0xbfa002b3, 0xb0804009, 0xb8f8f804, 0x9178ff78, 0x00008c00, - 0xb8fbf811, 0x8b6eff78, - 0x00004000, 0xbfa10008, - 0x8b6eff7b, 0x00000080, + 0xb8fbf811, 0xbf0c877b, + 0xbfa20002, 0x916dff6d, + 0xf0000000, 0xbf0c857b, + 0xbfa20003, 0xbefb1087, + 0xb98001d1, 0x00000000, + 0x8b6eff78, 0x00004000, + 0xbfa10007, 0xbf0d877b, 0xbfa20018, 0x8b6ea07b, - 0xbfa20042, 0xbf830010, + 0xbfa2004b, 0xbf830010, 0xb8fbf811, 0xbfa0fffb, 0x8b6eff7b, 0x00000bd0, 0xbfa20010, 0xb8eef812, @@ -3719,118 +3723,67 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { 0xf0000000, 0xbfa20005, 0x8b6fff6f, 0x00000200, 0xbfa20002, 0x8b6ea07b, - 0xbfa2002c, 0xbefa4d82, - 0xbf8a0000, 0x84fa887a, - 0xbf0d8f7b, 0xbfa10002, - 0x8c7bff7b, 0xffff0000, - 0xf4601bbd, 0xf8000010, - 0xbf8a0000, 0x846e976e, - 0x9177ff77, 0x00800000, - 0x8c776e77, 0xf4603bbd, - 0xf8000000, 0xbf8a0000, - 0xf4603ebd, 0xf8000008, - 0xbf8a0000, 0x8bee6e6e, - 0xbfa10001, 0xbe80486e, - 0x8b6eff6d, 0xf0000000, - 0xbfa20009, 0xb8eef811, - 0x8b6eff6e, 0x00000080, - 0xbfa20007, 0x8c78ff78, - 0x00004000, 0x80ec886c, - 0x82ed806d, 0xbfa00002, - 0x806c846c, 0x826d806d, + 0xbfa20035, 0xbeef007b, + 0xbefa4d82, 0xbf8a0000, + 0x84fa887a, 0xbf0d8f7b, + 0xbfa10002, 0x8c7bff7b, + 0xffff0000, 0xf4601bbd, + 0xf8000010, 0xbf8a0000, + 0x846e976e, 0x9177ff77, + 0x01800000, 0x8c776e77, + 0xbf0d876f, 0xbfa10006, + 0xbf0d8e78, 0xbfa20002, + 0xbf0d9877, 0xbfa20002, + 0xb98001d1, 0x00000000, + 0xf4603bbd, 0xf8000000, + 0xbf8a0000, 0xf4603ebd, + 0xf8000008, 0xbf8a0000, + 0x8bee6e6e, 0xbfa10001, + 0xbe80486e, 0x8b6eff6d, + 0xf0000000, 0xbfa20009, + 0xb8eef811, 0x8b6eff6e, + 0x00000080, 0xbfa20007, + 0x8c78ff78, 0x00004000, + 0x80ec886c, 0x82ed806d, + 0xbfa00002, 0x806c846c, + 0x826d806d, 0x8b6dff6d, + 0x0000ffff, 0x8bfe7e7e, + 0x8bea6a6a, 0x85788978, + 0xb9783244, 0xbe804a6c, + 0xb8faf802, 0xbf0d987a, + 0xbfa10001, 0xbfb00000, 0x8b6dff6d, 0x0000ffff, - 0x8bfe7e7e, 0x8bea6a6a, - 0x85788978, 0xb9783244, - 0xbe804a6c, 0xb8faf802, - 0xbf0d987a, 0xbfa10001, - 0xbfb00000, 0x8b6dff6d, - 0x0000ffff, 0xbefa0080, - 0xb97a0151, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbefe4d84, 0xbf8a0000, - 0x8b7aff7f, 0x04000000, - 0x847a857a, 0x8c6d7a6d, - 0xbefa007e, 0x8b7bff7f, - 0x0000ffff, 0xbefe00c1, - 0xbeff00c1, 0xee0a407a, - 0x000c0000, 0x00000000, - 0x7e000280, 0xbefe007a, - 0xbeff007b, 0xb8fb0742, - 0x847b997b, 0xb8fa3b05, - 0x807a817a, 0xbf0d997b, - 0xbfa20002, 0x847a897a, - 0xbfa00001, 0x847a8a7a, - 0xb8fb1e06, 0x847b8a7b, - 0x807a7b7a, 0x8b7bff7f, - 0x0000ffff, 0x807aff7a, - 0x00000200, 0x807a7e7a, - 0x827b807b, 0xd7610000, - 0x00010870, 0xd7610000, - 0x00010a71, 0xd7610000, - 0x00010c72, 0xd7610000, - 0x00010e73, 0xd7610000, - 0x00011074, 0xd7610000, - 0x00011275, 0xd7610000, - 0x00011476, 0xd7610000, - 0x00011677, 0xd7610000, - 0x00011a79, 0xd7610000, - 0x00011c7e, 0xd7610000, - 0x00011e7f, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xbefe00ff, - 0x00003fff, 0xbeff0080, + 0xbefa0080, 0xb97a0151, + 0xbeee007e, 0xbeef007f, + 0xbefe0180, 0xbefe4d84, + 0xbf8a0000, 0x8b7aff7f, + 0x04000000, 0x847a857a, + 0x8c6d7a6d, 0xbefa007e, + 0x8b7bff7f, 0x0000ffff, + 0xbefe00c1, 0xbeff00c1, 0xee0a407a, 0x000c0000, - 0x00004000, 0xd760007a, - 0x00011d00, 0xd760007b, - 0x00011f00, 0xbefe007a, - 0xbeff007b, 0xbef4007e, - 0x8b75ff7f, 0x0000ffff, - 0x8c75ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x10807fac, 0xbef1007d, - 0xbef00080, 0xb8f30742, - 0x84739973, 0xbefe00c1, - 0x857d9973, 0x8b7d817d, - 0xbf06817d, 0xbfa20002, - 0xbeff0080, 0xbfa00002, - 0xbeff00c1, 0xbfa0000c, - 0xbef600ff, 0x01000000, - 0xc4068070, 0x008ce801, - 0x00008000, 0xc4068070, - 0x008ce802, 0x00010000, - 0xc4068070, 0x008ce803, - 0x00018000, 0xbfa0000b, - 0xbef600ff, 0x01000000, - 0xc4068070, 0x008ce801, - 0x00010000, 0xc4068070, - 0x008ce802, 0x00020000, - 0xc4068070, 0x008ce803, - 0x00030000, 0xb8f03b05, - 0x80708170, 0xbf0d9973, - 0xbfa20002, 0x84708970, - 0xbfa00001, 0x84708a70, - 0xb8fa1e06, 0x847a8a7a, - 0x80707a70, 0x8070ff70, - 0x00000200, 0xbef600ff, - 0x01000000, 0x7e000280, - 0x7e020280, 0x7e040280, - 0xbe804ec2, 0xbf94fffe, - 0xb8faf804, 0x8b7a847a, - 0x91788478, 0x8c787a78, - 0x917aff6d, 0x80000000, - 0xd7610002, 0x00010071, - 0xd7610002, 0x0001026c, - 0xd7610002, 0x0001047a, - 0xd7610002, 0x0001066e, - 0xd7610002, 0x0001086f, - 0xd7610002, 0x00010a78, - 0xd7610002, 0x00010e7b, + 0x00000000, 0x7e000280, + 0xbefe007a, 0xbeff007b, + 0xb8fb0742, 0x847b997b, + 0xb8fa3b05, 0x807a817a, + 0xbf0d997b, 0xbfa20002, + 0x847a897a, 0xbfa00001, + 0x847a8a7a, 0xb8fb1e06, + 0x847b8a7b, 0x807a7b7a, + 0x8b7bff7f, 0x0000ffff, + 0x807aff7a, 0x00000200, + 0x807a7e7a, 0x827b807b, + 0xd7610000, 0x00010870, + 0xd7610000, 0x00010a71, + 0xd7610000, 0x00010c72, + 0xd7610000, 0x00010e73, + 0xd7610000, 0x00011074, + 0xd7610000, 0x00011275, + 0xd7610000, 0x00011476, + 0xd7610000, 0x00011677, + 0xd7610000, 0x00011a79, + 0xd7610000, 0x00011c7e, + 0xd7610000, 0x00011e7f, 0xd8500000, 0x00000000, 0xd8500000, 0x00000000, 0xd8500000, 0x00000000, @@ -3839,113 +3792,54 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { 0xd8500000, 0x00000000, 0xd8500000, 0x00000000, 0xd8500000, 0x00000000, - 0xb8faf811, 0xd7610002, - 0x00010c7a, 0xb8faf801, - 0xd7610002, 0x0001107a, - 0xb8faf814, 0xd7610002, - 0x0001127a, 0xb8faf815, - 0xd7610002, 0x0001147a, - 0xb8faf812, 0xd7610002, - 0x0001167a, 0xb8faf813, - 0xd7610002, 0x0001187a, - 0xb8faf802, 0xd7610002, - 0x00011a7a, 0xbefa50c1, - 0xbfc70000, 0xd7610002, - 0x00011c7a, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xbefe00ff, - 0x0000ffff, 0xbeff0080, + 0xbefe00ff, 0x00003fff, + 0xbeff0080, 0xee0a407a, + 0x000c0000, 0x00004000, + 0xd760007a, 0x00011d00, + 0xd760007b, 0x00011f00, + 0xbefe007a, 0xbeff007b, + 0xbef4007e, 0x8b75ff7f, + 0x0000ffff, 0x8c75ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x10807fac, + 0xbef1007d, 0xbef00080, + 0xb8f30742, 0x84739973, + 0xbefe00c1, 0x857d9973, + 0x8b7d817d, 0xbf06817d, + 0xbfa20002, 0xbeff0080, + 0xbfa00002, 0xbeff00c1, + 0xbfa0000c, 0xbef600ff, + 0x01000000, 0xc4068070, + 0x008ce801, 0x00008000, 0xc4068070, 0x008ce802, - 0x00000000, 0xbefe00c1, + 0x00010000, 0xc4068070, + 0x008ce803, 0x00018000, + 0xbfa0000b, 0xbef600ff, + 0x01000000, 0xc4068070, + 0x008ce801, 0x00010000, + 0xc4068070, 0x008ce802, + 0x00020000, 0xc4068070, + 0x008ce803, 0x00030000, 0xb8f03b05, 0x80708170, 0xbf0d9973, 0xbfa20002, 0x84708970, 0xbfa00001, 0x84708a70, 0xb8fa1e06, 0x847a8a7a, 0x80707a70, + 0x8070ff70, 0x00000200, 0xbef600ff, 0x01000000, - 0xbef90080, 0xbefd0080, - 0xbf800000, 0xbe804100, - 0xbe824102, 0xbe844104, - 0xbe864106, 0xbe884108, - 0xbe8a410a, 0xbe8c410c, - 0xbe8e410e, 0xbf068079, - 0xbfa10032, 0xd7610002, - 0x00010000, 0xd7610002, - 0x00010201, 0xd7610002, - 0x00010402, 0xd7610002, - 0x00010603, 0xd7610002, - 0x00010804, 0xd7610002, - 0x00010a05, 0xd7610002, - 0x00010c06, 0xd7610002, - 0x00010e07, 0xd7610002, - 0x00011008, 0xd7610002, - 0x00011209, 0xd7610002, - 0x0001140a, 0xd7610002, - 0x0001160b, 0xd7610002, - 0x0001180c, 0xd7610002, - 0x00011a0d, 0xd7610002, - 0x00011c0e, 0xd7610002, - 0x00011e0f, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0x80799079, - 0xbfa00038, 0xd7610002, - 0x00012000, 0xd7610002, - 0x00012201, 0xd7610002, - 0x00012402, 0xd7610002, - 0x00012603, 0xd7610002, - 0x00012804, 0xd7610002, - 0x00012a05, 0xd7610002, - 0x00012c06, 0xd7610002, - 0x00012e07, 0xd7610002, - 0x00013008, 0xd7610002, - 0x00013209, 0xd7610002, - 0x0001340a, 0xd7610002, - 0x0001360b, 0xd7610002, - 0x0001380c, 0xd7610002, - 0x00013a0d, 0xd7610002, - 0x00013c0e, 0xd7610002, - 0x00013e0f, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0x80799079, - 0xc4068070, 0x008ce802, - 0x00000000, 0x8070ff70, - 0x00000080, 0xbef90080, - 0x7e040280, 0x807d907d, - 0xbf0aff7d, 0x00000060, - 0xbfa2ff88, 0xbe804100, - 0xbe824102, 0xbe844104, - 0xbe864106, 0xbe884108, - 0xbe8a410a, 0xd7610002, - 0x00010000, 0xd7610002, - 0x00010201, 0xd7610002, - 0x00010402, 0xd7610002, - 0x00010603, 0xd7610002, - 0x00010804, 0xd7610002, - 0x00010a05, 0xd7610002, - 0x00010c06, 0xd7610002, - 0x00010e07, 0xd7610002, - 0x00011008, 0xd7610002, - 0x00011209, 0xd7610002, - 0x0001140a, 0xd7610002, - 0x0001160b, 0xd8500000, + 0x7e000280, 0x7e020280, + 0x7e040280, 0xbe804ec2, + 0xbf94fffe, 0xb8faf804, + 0x8b7a847a, 0x91788478, + 0x8c787a78, 0x917aff6d, + 0x80000000, 0xd7610002, + 0x00010071, 0xd7610002, + 0x0001026c, 0xd7610002, + 0x0001047a, 0xd7610002, + 0x0001066e, 0xd7610002, + 0x0001086f, 0xd7610002, + 0x00010a78, 0xd7610002, + 0x00010e7b, 0xd8500000, 0x00000000, 0xd8500000, 0x00000000, 0xd8500000, 0x00000000, 0xd8500000, @@ -3953,279 +3847,394 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { 0x00000000, 0xd8500000, 0x00000000, 0xd8500000, 0x00000000, 0xd8500000, - 0x00000000, 0xc4068070, + 0x00000000, 0xb8faf811, + 0xd7610002, 0x00010c7a, + 0xb8faf801, 0xd7610002, + 0x0001107a, 0xb8faf814, + 0xd7610002, 0x0001127a, + 0xb8faf815, 0xd7610002, + 0x0001147a, 0xb8faf812, + 0xd7610002, 0x0001167a, + 0xb8faf813, 0xd7610002, + 0x0001187a, 0xb8faf802, + 0xd7610002, 0x00011a7a, + 0xbefa50c1, 0xbfc70000, + 0xd7610002, 0x00011c7a, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xbefe00ff, 0x0000ffff, + 0xbeff0080, 0xc4068070, + 0x008ce802, 0x00000000, + 0xbefe00c1, 0xb8f03b05, + 0x80708170, 0xbf0d9973, + 0xbfa20002, 0x84708970, + 0xbfa00001, 0x84708a70, + 0xb8fa1e06, 0x847a8a7a, + 0x80707a70, 0xbef600ff, + 0x01000000, 0xbef90080, + 0xbefd0080, 0xbf800000, + 0xbe804100, 0xbe824102, + 0xbe844104, 0xbe864106, + 0xbe884108, 0xbe8a410a, + 0xbe8c410c, 0xbe8e410e, + 0xbf068079, 0xbfa10032, + 0xd7610002, 0x00010000, + 0xd7610002, 0x00010201, + 0xd7610002, 0x00010402, + 0xd7610002, 0x00010603, + 0xd7610002, 0x00010804, + 0xd7610002, 0x00010a05, + 0xd7610002, 0x00010c06, + 0xd7610002, 0x00010e07, + 0xd7610002, 0x00011008, + 0xd7610002, 0x00011209, + 0xd7610002, 0x0001140a, + 0xd7610002, 0x0001160b, + 0xd7610002, 0x0001180c, + 0xd7610002, 0x00011a0d, + 0xd7610002, 0x00011c0e, + 0xd7610002, 0x00011e0f, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0x80799079, 0xbfa00038, + 0xd7610002, 0x00012000, + 0xd7610002, 0x00012201, + 0xd7610002, 0x00012402, + 0xd7610002, 0x00012603, + 0xd7610002, 0x00012804, + 0xd7610002, 0x00012a05, + 0xd7610002, 0x00012c06, + 0xd7610002, 0x00012e07, + 0xd7610002, 0x00013008, + 0xd7610002, 0x00013209, + 0xd7610002, 0x0001340a, + 0xd7610002, 0x0001360b, + 0xd7610002, 0x0001380c, + 0xd7610002, 0x00013a0d, + 0xd7610002, 0x00013c0e, + 0xd7610002, 0x00013e0f, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0x80799079, 0xc4068070, 0x008ce802, 0x00000000, - 0xbefe00c1, 0x857d9973, - 0x8b7d817d, 0xbf06817d, - 0xbfa20002, 0xbeff0080, - 0xbfa00001, 0xbeff00c1, - 0xb8fb4306, 0x8b7bc17b, - 0xbfa10044, 0x8b7aff6d, - 0x80000000, 0xbfa10041, - 0x847b897b, 0xbef6007b, - 0xb8f03b05, 0x80708170, - 0xbf0d9973, 0xbfa20002, - 0x84708970, 0xbfa00001, - 0x84708a70, 0xb8fa1e06, - 0x847a8a7a, 0x80707a70, - 0x8070ff70, 0x00000200, 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, - 0xd71f0000, 0x000100c1, - 0xd7200000, 0x000200c1, - 0x16000084, 0x857d9973, - 0x8b7d817d, 0xbf06817d, - 0xbefd0080, 0xbfa20013, - 0xbe8300ff, 0x00000080, - 0xbf800000, 0xbf800000, - 0xbf800000, 0xd8d80000, - 0x01000000, 0xbf8a0000, - 0xc4068070, 0x008ce801, - 0x00000000, 0x807d037d, - 0x80700370, 0xd5250000, - 0x0001ff00, 0x00000080, - 0xbf0a7b7d, 0xbfa2fff3, - 0xbfa00012, 0xbe8300ff, - 0x00000100, 0xbf800000, + 0xbef90080, 0x7e040280, + 0x807d907d, 0xbf0aff7d, + 0x00000060, 0xbfa2ff88, + 0xbe804100, 0xbe824102, + 0xbe844104, 0xbe864106, + 0xbe884108, 0xbe8a410a, + 0xd7610002, 0x00010000, + 0xd7610002, 0x00010201, + 0xd7610002, 0x00010402, + 0xd7610002, 0x00010603, + 0xd7610002, 0x00010804, + 0xd7610002, 0x00010a05, + 0xd7610002, 0x00010c06, + 0xd7610002, 0x00010e07, + 0xd7610002, 0x00011008, + 0xd7610002, 0x00011209, + 0xd7610002, 0x0001140a, + 0xd7610002, 0x0001160b, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xd8500000, 0x00000000, + 0xc4068070, 0x008ce802, + 0x00000000, 0xbefe00c1, + 0x857d9973, 0x8b7d817d, + 0xbf06817d, 0xbfa20002, + 0xbeff0080, 0xbfa00001, + 0xbeff00c1, 0xb8fb4306, + 0x8b7bc17b, 0xbfa10044, + 0x8b7aff6d, 0x80000000, + 0xbfa10041, 0x847b897b, + 0xbef6007b, 0xb8f03b05, + 0x80708170, 0xbf0d9973, + 0xbfa20002, 0x84708970, + 0xbfa00001, 0x84708a70, + 0xb8fa1e06, 0x847a8a7a, + 0x80707a70, 0x8070ff70, + 0x00000200, 0x8070ff70, + 0x00000080, 0xbef600ff, + 0x01000000, 0xd71f0000, + 0x000100c1, 0xd7200000, + 0x000200c1, 0x16000084, + 0x857d9973, 0x8b7d817d, + 0xbf06817d, 0xbefd0080, + 0xbfa20013, 0xbe8300ff, + 0x00000080, 0xbf800000, 0xbf800000, 0xbf800000, 0xd8d80000, 0x01000000, 0xbf8a0000, 0xc4068070, 0x008ce801, 0x00000000, 0x807d037d, 0x80700370, 0xd5250000, 0x0001ff00, - 0x00000100, 0xbf0a7b7d, - 0xbfa2fff3, 0xbefe00c1, - 0x857d9973, 0x8b7d817d, - 0xbf06817d, 0xbfa20004, - 0xbef000ff, 0x00000200, - 0xbeff0080, 0xbfa00003, - 0xbef000ff, 0x00000400, - 0xbeff00c1, 0xb8fb3b05, - 0x807b817b, 0x847b827b, - 0x857d9973, 0x8b7d817d, - 0xbf06817d, 0xbfa2001b, - 0xbef600ff, 0x01000000, - 0xbefd0084, 0xbf0a7b7d, - 0xbfa10040, 0x7e008700, - 0x7e028701, 0x7e048702, - 0x7e068703, 0xc4068070, - 0x008ce800, 0x00000000, + 0x00000080, 0xbf0a7b7d, + 0xbfa2fff3, 0xbfa00012, + 0xbe8300ff, 0x00000100, + 0xbf800000, 0xbf800000, + 0xbf800000, 0xd8d80000, + 0x01000000, 0xbf8a0000, 0xc4068070, 0x008ce801, - 0x00008000, 0xc4068070, - 0x008ce802, 0x00010000, - 0xc4068070, 0x008ce803, - 0x00018000, 0x807d847d, - 0x8070ff70, 0x00000200, - 0xbf0a7b7d, 0xbfa2ffeb, - 0xbfa0002a, 0xbef600ff, + 0x00000000, 0x807d037d, + 0x80700370, 0xd5250000, + 0x0001ff00, 0x00000100, + 0xbf0a7b7d, 0xbfa2fff3, + 0xbefe00c1, 0x857d9973, + 0x8b7d817d, 0xbf06817d, + 0xbfa20004, 0xbef000ff, + 0x00000200, 0xbeff0080, + 0xbfa00003, 0xbef000ff, + 0x00000400, 0xbeff00c1, + 0xb8fb3b05, 0x807b817b, + 0x847b827b, 0x857d9973, + 0x8b7d817d, 0xbf06817d, + 0xbfa2001b, 0xbef600ff, 0x01000000, 0xbefd0084, - 0xbf0a7b7d, 0xbfa10015, + 0xbf0a7b7d, 0xbfa10040, 0x7e008700, 0x7e028701, 0x7e048702, 0x7e068703, 0xc4068070, 0x008ce800, 0x00000000, 0xc4068070, - 0x008ce801, 0x00010000, + 0x008ce801, 0x00008000, 0xc4068070, 0x008ce802, - 0x00020000, 0xc4068070, - 0x008ce803, 0x00030000, + 0x00010000, 0xc4068070, + 0x008ce803, 0x00018000, 0x807d847d, 0x8070ff70, - 0x00000400, 0xbf0a7b7d, - 0xbfa2ffeb, 0xb8fb1e06, - 0x8b7bc17b, 0xbfa1000d, - 0x847b837b, 0x807b7d7b, - 0xbefe00c1, 0xbeff0080, - 0x7e008700, 0xc4068070, - 0x008ce800, 0x00000000, - 0x807d817d, 0x8070ff70, - 0x00000080, 0xbf0a7b7d, - 0xbfa2fff7, 0xbfa0016e, - 0xbef4007e, 0x8b75ff7f, - 0x0000ffff, 0x8c75ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x10807fac, - 0xbef1007f, 0xb8f20742, - 0x84729972, 0x8b6eff7f, - 0x04000000, 0xbfa1003b, - 0xbefe00c1, 0x857d9972, - 0x8b7d817d, 0xbf06817d, - 0xbfa20002, 0xbeff0080, - 0xbfa00001, 0xbeff00c1, - 0xb8ef4306, 0x8b6fc16f, - 0xbfa10030, 0x846f896f, - 0xbef6006f, 0xb8f83b05, - 0x80788178, 0xbf0d9972, - 0xbfa20002, 0x84788978, - 0xbfa00001, 0x84788a78, - 0xb8ee1e06, 0x846e8a6e, - 0x80786e78, 0x8078ff78, - 0x00000200, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0x857d9972, - 0x8b7d817d, 0xbf06817d, - 0xbefd0080, 0xbfa2000d, - 0xc4050078, 0x0080e800, - 0x00000000, 0xbf8a0000, - 0xdac00000, 0x00000000, - 0x807dff7d, 0x00000080, - 0x8078ff78, 0x00000080, - 0xbf0a6f7d, 0xbfa2fff4, - 0xbfa0000c, 0xc4050078, - 0x0080e800, 0x00000000, - 0xbf8a0000, 0xdac00000, - 0x00000000, 0x807dff7d, - 0x00000100, 0x8078ff78, - 0x00000100, 0xbf0a6f7d, - 0xbfa2fff4, 0xbef80080, - 0xbefe00c1, 0x857d9972, - 0x8b7d817d, 0xbf06817d, - 0xbfa20002, 0xbeff0080, - 0xbfa00001, 0xbeff00c1, - 0xb8ef3b05, 0x806f816f, - 0x846f826f, 0x857d9972, - 0x8b7d817d, 0xbf06817d, - 0xbfa2002c, 0xbef600ff, - 0x01000000, 0xbeee0078, - 0x8078ff78, 0x00000200, - 0xbefd0084, 0xbf0a6f7d, - 0xbfa10061, 0xc4050078, - 0x008ce800, 0x00000000, - 0xc4050078, 0x008ce801, - 0x00008000, 0xc4050078, - 0x008ce802, 0x00010000, - 0xc4050078, 0x008ce803, - 0x00018000, 0xbf8a0000, - 0x7e008500, 0x7e028501, - 0x7e048502, 0x7e068503, - 0x807d847d, 0x8078ff78, - 0x00000200, 0xbf0a6f7d, - 0xbfa2ffea, 0xc405006e, - 0x008ce800, 0x00000000, - 0xc405006e, 0x008ce801, - 0x00008000, 0xc405006e, - 0x008ce802, 0x00010000, - 0xc405006e, 0x008ce803, - 0x00018000, 0xbf8a0000, - 0xbfa0003d, 0xbef600ff, - 0x01000000, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefd0084, 0xbf0a6f7d, - 0xbfa10016, 0xc4050078, - 0x008ce800, 0x00000000, - 0xc4050078, 0x008ce801, - 0x00010000, 0xc4050078, - 0x008ce802, 0x00020000, - 0xc4050078, 0x008ce803, - 0x00030000, 0xbf8a0000, - 0x7e008500, 0x7e028501, - 0x7e048502, 0x7e068503, - 0x807d847d, 0x8078ff78, - 0x00000400, 0xbf0a6f7d, - 0xbfa2ffea, 0xb8ef1e06, - 0x8b6fc16f, 0xbfa1000f, - 0x846f836f, 0x806f7d6f, - 0xbefe00c1, 0xbeff0080, - 0xc4050078, 0x008ce800, - 0x00000000, 0xbf8a0000, - 0x7e008500, 0x807d817d, - 0x8078ff78, 0x00000080, - 0xbf0a6f7d, 0xbfa2fff6, - 0xbeff00c1, 0xc405006e, + 0x00000200, 0xbf0a7b7d, + 0xbfa2ffeb, 0xbfa0002a, + 0xbef600ff, 0x01000000, + 0xbefd0084, 0xbf0a7b7d, + 0xbfa10015, 0x7e008700, + 0x7e028701, 0x7e048702, + 0x7e068703, 0xc4068070, 0x008ce800, 0x00000000, - 0xc405006e, 0x008ce801, - 0x00010000, 0xc405006e, + 0xc4068070, 0x008ce801, + 0x00010000, 0xc4068070, 0x008ce802, 0x00020000, - 0xc405006e, 0x008ce803, - 0x00030000, 0xbf8a0000, + 0xc4068070, 0x008ce803, + 0x00030000, 0x807d847d, + 0x8070ff70, 0x00000400, + 0xbf0a7b7d, 0xbfa2ffeb, + 0xb8fb1e06, 0x8b7bc17b, + 0xbfa1000d, 0x847b837b, + 0x807b7d7b, 0xbefe00c1, + 0xbeff0080, 0x7e008700, + 0xc4068070, 0x008ce800, + 0x00000000, 0x807d817d, + 0x8070ff70, 0x00000080, + 0xbf0a7b7d, 0xbfa2fff7, + 0xbfa0016e, 0xbef4007e, + 0x8b75ff7f, 0x0000ffff, + 0x8c75ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x10807fac, 0xbef1007f, + 0xb8f20742, 0x84729972, + 0x8b6eff7f, 0x04000000, + 0xbfa1003b, 0xbefe00c1, + 0x857d9972, 0x8b7d817d, + 0xbf06817d, 0xbfa20002, + 0xbeff0080, 0xbfa00001, + 0xbeff00c1, 0xb8ef4306, + 0x8b6fc16f, 0xbfa10030, + 0x846f896f, 0xbef6006f, 0xb8f83b05, 0x80788178, 0xbf0d9972, 0xbfa20002, 0x84788978, 0xbfa00001, 0x84788a78, 0xb8ee1e06, 0x846e8a6e, 0x80786e78, 0x8078ff78, 0x00000200, - 0x80f8ff78, 0x00000050, + 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xbefd00ff, 0x0000006c, - 0x80f89078, 0xf462403a, - 0xf0000000, 0xbf8a0000, - 0x80fd847d, 0xbf800000, - 0xbe804300, 0xbe824302, - 0x80f8a078, 0xf462603a, - 0xf0000000, 0xbf8a0000, - 0x80fd887d, 0xbf800000, - 0xbe804300, 0xbe824302, - 0xbe844304, 0xbe864306, - 0x80f8c078, 0xf462803a, - 0xf0000000, 0xbf8a0000, - 0x80fd907d, 0xbf800000, - 0xbe804300, 0xbe824302, - 0xbe844304, 0xbe864306, - 0xbe884308, 0xbe8a430a, - 0xbe8c430c, 0xbe8e430e, - 0xbf06807d, 0xbfa1fff0, - 0xb980f801, 0x00000000, - 0xb8f83b05, 0x80788178, - 0xbf0d9972, 0xbfa20002, - 0x84788978, 0xbfa00001, - 0x84788a78, 0xb8ee1e06, - 0x846e8a6e, 0x80786e78, + 0x857d9972, 0x8b7d817d, + 0xbf06817d, 0xbefd0080, + 0xbfa2000d, 0xc4050078, + 0x0080e800, 0x00000000, + 0xbf8a0000, 0xdac00000, + 0x00000000, 0x807dff7d, + 0x00000080, 0x8078ff78, + 0x00000080, 0xbf0a6f7d, + 0xbfa2fff4, 0xbfa0000c, + 0xc4050078, 0x0080e800, + 0x00000000, 0xbf8a0000, + 0xdac00000, 0x00000000, + 0x807dff7d, 0x00000100, + 0x8078ff78, 0x00000100, + 0xbf0a6f7d, 0xbfa2fff4, + 0xbef80080, 0xbefe00c1, + 0x857d9972, 0x8b7d817d, + 0xbf06817d, 0xbfa20002, + 0xbeff0080, 0xbfa00001, + 0xbeff00c1, 0xb8ef3b05, + 0x806f816f, 0x846f826f, + 0x857d9972, 0x8b7d817d, + 0xbf06817d, 0xbfa2002c, + 0xbef600ff, 0x01000000, + 0xbeee0078, 0x8078ff78, + 0x00000200, 0xbefd0084, + 0xbf0a6f7d, 0xbfa10061, + 0xc4050078, 0x008ce800, + 0x00000000, 0xc4050078, + 0x008ce801, 0x00008000, + 0xc4050078, 0x008ce802, + 0x00010000, 0xc4050078, + 0x008ce803, 0x00018000, + 0xbf8a0000, 0x7e008500, + 0x7e028501, 0x7e048502, + 0x7e068503, 0x807d847d, 0x8078ff78, 0x00000200, + 0xbf0a6f7d, 0xbfa2ffea, + 0xc405006e, 0x008ce800, + 0x00000000, 0xc405006e, + 0x008ce801, 0x00008000, + 0xc405006e, 0x008ce802, + 0x00010000, 0xc405006e, + 0x008ce803, 0x00018000, + 0xbf8a0000, 0xbfa0003d, 0xbef600ff, 0x01000000, - 0xbeff0071, 0xf4621bfa, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefd0084, + 0xbf0a6f7d, 0xbfa10016, + 0xc4050078, 0x008ce800, + 0x00000000, 0xc4050078, + 0x008ce801, 0x00010000, + 0xc4050078, 0x008ce802, + 0x00020000, 0xc4050078, + 0x008ce803, 0x00030000, + 0xbf8a0000, 0x7e008500, + 0x7e028501, 0x7e048502, + 0x7e068503, 0x807d847d, + 0x8078ff78, 0x00000400, + 0xbf0a6f7d, 0xbfa2ffea, + 0xb8ef1e06, 0x8b6fc16f, + 0xbfa1000f, 0x846f836f, + 0x806f7d6f, 0xbefe00c1, + 0xbeff0080, 0xc4050078, + 0x008ce800, 0x00000000, + 0xbf8a0000, 0x7e008500, + 0x807d817d, 0x8078ff78, + 0x00000080, 0xbf0a6f7d, + 0xbfa2fff6, 0xbeff00c1, + 0xc405006e, 0x008ce800, + 0x00000000, 0xc405006e, + 0x008ce801, 0x00010000, + 0xc405006e, 0x008ce802, + 0x00020000, 0xc405006e, + 0x008ce803, 0x00030000, + 0xbf8a0000, 0xb8f83b05, + 0x80788178, 0xbf0d9972, + 0xbfa20002, 0x84788978, + 0xbfa00001, 0x84788a78, + 0xb8ee1e06, 0x846e8a6e, + 0x80786e78, 0x8078ff78, + 0x00000200, 0x80f8ff78, + 0x00000050, 0xbef600ff, + 0x01000000, 0xbefd00ff, + 0x0000006c, 0x80f89078, + 0xf462403a, 0xf0000000, + 0xbf8a0000, 0x80fd847d, + 0xbf800000, 0xbe804300, + 0xbe824302, 0x80f8a078, + 0xf462603a, 0xf0000000, + 0xbf8a0000, 0x80fd887d, + 0xbf800000, 0xbe804300, + 0xbe824302, 0xbe844304, + 0xbe864306, 0x80f8c078, + 0xf462803a, 0xf0000000, + 0xbf8a0000, 0x80fd907d, + 0xbf800000, 0xbe804300, + 0xbe824302, 0xbe844304, + 0xbe864306, 0xbe884308, + 0xbe8a430a, 0xbe8c430c, + 0xbe8e430e, 0xbf06807d, + 0xbfa1fff0, 0xb980f801, + 0x00000000, 0xb8f83b05, + 0x80788178, 0xbf0d9972, + 0xbfa20002, 0x84788978, + 0xbfa00001, 0x84788a78, + 0xb8ee1e06, 0x846e8a6e, + 0x80786e78, 0x8078ff78, + 0x00000200, 0xbef600ff, + 0x01000000, 0xbeff0071, + 0xf4621bfa, 0xf0000000, + 0x80788478, 0xf4621b3a, 0xf0000000, 0x80788478, - 0xf4621b3a, 0xf0000000, - 0x80788478, 0xf4621b7a, + 0xf4621b7a, 0xf0000000, + 0x80788478, 0xf4621c3a, 0xf0000000, 0x80788478, - 0xf4621c3a, 0xf0000000, - 0x80788478, 0xf4621c7a, + 0xf4621c7a, 0xf0000000, + 0x80788478, 0xf4621eba, 0xf0000000, 0x80788478, - 0xf4621eba, 0xf0000000, - 0x80788478, 0xf4621efa, + 0xf4621efa, 0xf0000000, + 0x80788478, 0xf4621e7a, 0xf0000000, 0x80788478, - 0xf4621e7a, 0xf0000000, - 0x80788478, 0xf4621cfa, + 0xf4621cfa, 0xf0000000, + 0x80788478, 0xf4621bba, 0xf0000000, 0x80788478, + 0xbf8a0000, 0xb96ef814, 0xf4621bba, 0xf0000000, 0x80788478, 0xbf8a0000, - 0xb96ef814, 0xf4621bba, + 0xb96ef815, 0xf4621bba, 0xf0000000, 0x80788478, - 0xbf8a0000, 0xb96ef815, + 0xbf8a0000, 0xb96ef812, 0xf4621bba, 0xf0000000, 0x80788478, 0xbf8a0000, - 0xb96ef812, 0xf4621bba, + 0xb96ef813, 0x8b6eff7f, + 0x04000000, 0xbfa1000d, + 0x80788478, 0xf4621bba, 0xf0000000, 0x80788478, - 0xbf8a0000, 0xb96ef813, - 0x8b6eff7f, 0x04000000, - 0xbfa1000d, 0x80788478, - 0xf4621bba, 0xf0000000, - 0x80788478, 0xbf8a0000, - 0xbf0d806e, 0xbfa10006, - 0x856e906e, 0x8b6e6e6e, - 0xbfa10003, 0xbe804ec1, - 0x816ec16e, 0xbfa0fffb, - 0xbefd006f, 0xbefe0070, - 0xbeff0071, 0xb97b2011, - 0x857b867b, 0xb97b0191, - 0x857b827b, 0xb97bba11, - 0xb973f801, 0xb8ee3b05, - 0x806e816e, 0xbf0d9972, - 0xbfa20002, 0x846e896e, - 0xbfa00001, 0x846e8a6e, - 0xb8ef1e06, 0x846f8a6f, - 0x806e6f6e, 0x806eff6e, - 0x00000200, 0x806e746e, - 0x826f8075, 0x8b6fff6f, - 0x0000ffff, 0xf4605c37, - 0xf8000050, 0xf4605d37, - 0xf8000060, 0xf4601e77, - 0xf8000074, 0xbf8a0000, - 0x8b6dff6d, 0x0000ffff, - 0x8bfe7e7e, 0x8bea6a6a, - 0xb97af804, 0xbe804ec2, - 0xbf94fffe, 0xbe804a6c, + 0xbf8a0000, 0xbf0d806e, + 0xbfa10006, 0x856e906e, + 0x8b6e6e6e, 0xbfa10003, + 0xbe804ec1, 0x816ec16e, + 0xbfa0fffb, 0xbefd006f, + 0xbefe0070, 0xbeff0071, + 0xb97b2011, 0x857b867b, + 0xb97b0191, 0x857b827b, + 0xb97bba11, 0xb973f801, + 0xb8ee3b05, 0x806e816e, + 0xbf0d9972, 0xbfa20002, + 0x846e896e, 0xbfa00001, + 0x846e8a6e, 0xb8ef1e06, + 0x846f8a6f, 0x806e6f6e, + 0x806eff6e, 0x00000200, + 0x806e746e, 0x826f8075, + 0x8b6fff6f, 0x0000ffff, + 0xf4605c37, 0xf8000050, + 0xf4605d37, 0xf8000060, + 0xf4601e77, 0xf8000074, + 0xbf8a0000, 0x8b6dff6d, + 0x0000ffff, 0x8bfe7e7e, + 0x8bea6a6a, 0xb97af804, 0xbe804ec2, 0xbf94fffe, - 0xbfb10000, 0xbf9f0000, + 0xbe804a6c, 0xbe804ec2, + 0xbf94fffe, 0xbfb10000, 0xbf9f0000, 0xbf9f0000, 0xbf9f0000, 0xbf9f0000, + 0xbf9f0000, 0x00000000, }; static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm index 5a1a1b1f897fe..999967b754285 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm @@ -31,6 +31,7 @@ #define SINGLE_STEP_MISSED_WORKAROUND 1 //workaround for lost TRAP_AFTER_INST exception when SAVECTX raised #define HAVE_VALU_SGPR_HAZARD (ASIC_FAMILY == CHIP_GFX12) +#define HAVE_HT_TRAP_ID_WA (ASIC_FAMILY == CHIP_GFX12) var SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK = 0x4 var SQ_WAVE_STATE_PRIV_SCC_SHIFT = 9 @@ -41,6 +42,7 @@ var SQ_WAVE_STATE_PRIV_POISON_ERR_SHIFT = 15 var SQ_WAVE_STATUS_WAVE64_SHIFT = 29 var SQ_WAVE_STATUS_WAVE64_SIZE = 1 var SQ_WAVE_STATUS_NO_VGPRS_SHIFT = 24 +var SQ_WAVE_STATUS_HALT_SHIFT = 14 var SQ_WAVE_STATE_PRIV_ALWAYS_CLEAR_MASK = SQ_WAVE_STATE_PRIV_SYS_PRIO_MASK|SQ_WAVE_STATE_PRIV_POISON_ERR_MASK var S_SAVE_PC_HI_TRAP_ID_MASK = 0xF0000000 @@ -84,6 +86,12 @@ var BARRIER_STATE_VALID_OFFSET = 0 var TTMP11_DEBUG_TRAP_ENABLED_SHIFT = 23 var TTMP11_DEBUG_TRAP_ENABLED_MASK = 0x800000 +var TTMP11_HOST_TRAP_ENABLED_SHIFT = 24 +var TTMP11_HOST_TRAP_ENABLED_MASK = (1 << TTMP11_HOST_TRAP_ENABLED_SHIFT) + +var TTMP11_FEATURES_ENABLED_FLAGS_SHIFT = TTMP11_DEBUG_TRAP_ENABLED_SHIFT +var TTMP11_FEATURES_ENABLED_FLAGS_MASK = TTMP11_DEBUG_TRAP_ENABLED_MASK | TTMP11_HOST_TRAP_ENABLED_MASK + // SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] // when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 @@ -168,12 +176,52 @@ L_SKIP_RESTORE: s_getreg_b32 s_save_excp_flag_priv, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) +#if HAVE_HT_TRAP_ID_WA + // If we have both TRAP_ID (ttmp1[31:28]) != 0, and + // EXCP_FLAG_PRIV.HOST_TRAP == 1, we cannot reliably know if we entered + // the trap handler for an s_trap or a host trap. + // + // In both cases, if we see HOST_TRAP == 1, we can clear the TRAP_ID + // bits: + // - If this was a host trap, all good, those bits should have been 0 + // anyway, so they can be cleared. + // - If this was an s_trap, ttmp[0:1] still points to the s_trap + // instruction, and it will be the first to be executed after s_rfe. + // We do not change the behavior of the program, by not handling the + // trap just yet, assume this was just a host trap and deal with the + // s_trap on next entry. + s_bitcmp0_b32 s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT + s_cbranch_scc1 L_NOT_HOST_TRAP_WA + s_andn2_b32 s_save_pc_hi, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK + +L_NOT_HOST_TRAP_WA: + // From now on in the trap handler, if we see TTMP1.TRAP_ID != 0, then it has + // to be because of a s_trap. If the second level trap handler sees + // both TRAP_ID != 0 and EXCP_FLAG_PRIV.HOST_TRAP == 1, it is because + // a HOST_TRAP was received while we were in the trap handler, future host + // trap can't influence ttmp1. So both the s_trap and host_trap can be handled + // in one go. +#endif + + // Ignore Host Trap if SAVECTX is also present. + // Usually s_trap has a higher priority than context_save, HAVE_HT_TRAP_ID_WA + // will reverse these priority's order when s_trap, host_trap and context save + // are raised at the same time. We will end-up ignoring the s_trap (because of + // the ambiguity with the host trap), ignoring the host trap (to be sure high + // frequency sampling cannot prevent CWSR) and directly doing the context save. + // The s_trap will be re-executed after context save/restore. + s_bitcmp0_b32 s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT + s_cbranch_scc1 L_NO_SAVE_AND_HT + s_bitset0_b32 s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT + s_setreg_imm32_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT, 1), 0 + +L_NO_SAVE_AND_HT: s_and_b32 ttmp2, s_save_state_priv, SQ_WAVE_STATE_PRIV_HALT_MASK s_cbranch_scc0 L_NOT_HALTED L_HALTED: // Host trap may occur while wave is halted. - s_and_b32 ttmp2, s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK + s_bitcmp1_b32 s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT s_cbranch_scc1 L_FETCH_2ND_TRAP L_CHECK_SAVE: @@ -230,6 +278,7 @@ L_FETCH_2ND_TRAP: // Read second-level TBA/TMA from first-level TMA and jump if available. // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) // ttmp12 holds SQ_WAVE_STATUS + s_mov_b32 ttmp3, s_save_excp_flag_priv s_sendmsg_rtn_b64 [ttmp14, ttmp15], sendmsg(MSG_RTN_GET_TMA) s_wait_idle s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 @@ -238,13 +287,32 @@ L_FETCH_2ND_TRAP: s_cbranch_scc0 L_NO_SIGN_EXTEND_TMA s_or_b32 ttmp15, ttmp15, 0xFFFF0000 L_NO_SIGN_EXTEND_TMA: - - s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 scope:SCOPE_SYS // debug trap enabled flag + s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 scope:SCOPE_SYS // trap enabled flag s_wait_idle - s_lshl_b32 ttmp2, ttmp2, TTMP11_DEBUG_TRAP_ENABLED_SHIFT - s_andn2_b32 ttmp11, ttmp11, TTMP11_DEBUG_TRAP_ENABLED_MASK + s_lshl_b32 ttmp2, ttmp2, TTMP11_FEATURES_ENABLED_FLAGS_SHIFT + s_andn2_b32 ttmp11, ttmp11, TTMP11_FEATURES_ENABLED_FLAGS_MASK s_or_b32 ttmp11, ttmp11, ttmp2 + // If not a host trap, then driver cannot mask this + s_bitcmp1_b32 ttmp3, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT + s_cbranch_scc0 L_NO_EXCEPTION_MASKING + + s_bitcmp1_b32 s_save_state_priv, SQ_WAVE_STATUS_HALT_SHIFT + s_cbranch_scc1 L_MASK_HOST_TRAP + + // Handle masking host traps if requested by the driver. + s_bitcmp1_b32 ttmp11, TTMP11_HOST_TRAP_ENABLED_SHIFT + + // We got here because of either a non-maskable exception or a maskable + // one (HT). The driver said the maskable HT should not be masked, so + // we can directly carry on to the 2nd level trap handler. + s_cbranch_scc1 L_NO_EXCEPTION_MASKING + +L_MASK_HOST_TRAP: + // The driver asked to mask the HT, be sure to do so. + s_setreg_imm32_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT, 1), 0x0 + +L_NO_EXCEPTION_MASKING: s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 scope:SCOPE_SYS // second-level TBA s_wait_idle s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 scope:SCOPE_SYS // second-level TMA From c2770f16f5092b9073929bb4277360651a8ba437 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 25 Jul 2025 14:41:16 +0800 Subject: [PATCH 1574/2653] drm/amdkcl: cleanup macro HAVE_HDR_SINK_METADATA Signed-off-by: Bob Zhou --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 61 ++----------------- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 -- .../drm/amd/dkms/m4/drm-hdr-sink-metadata.m4 | 20 ------ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 4 files changed, 4 insertions(+), 82 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-hdr-sink-metadata.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 479ae6505c4be..ad36abcacebd5 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3643,7 +3643,6 @@ static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { #endif }; -#ifdef HAVE_HDR_SINK_METADATA static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) { struct amdgpu_dm_backlight_caps *caps; @@ -3702,7 +3701,6 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) caps->min_input_signal = min_input_signal_override; #endif } -#endif DEFINE_FREE(sink_release, struct dc_sink *, if (_T) dc_sink_release(_T)) @@ -3846,9 +3844,7 @@ void amdgpu_dm_update_connector_after_detect( #else amdgpu_dm_update_freesync_caps(connector, aconnector->edid); #endif -#ifdef HAVE_HDR_SINK_METADATA update_connector_ext_caps(aconnector); -#endif } else { hdmi_cec_unset_edid(aconnector); drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); @@ -4765,9 +4761,7 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 #define AMDGPU_DM_MIN_SPREAD ((AMDGPU_DM_DEFAULT_MAX_BACKLIGHT - AMDGPU_DM_DEFAULT_MIN_BACKLIGHT) / 2) -#ifdef HAVE_HDR_SINK_METADATA #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 -#endif static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, int bl_idx) @@ -4800,10 +4794,8 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, caps->caps_valid = true; } #else -#ifdef HAVE_HDR_SINK_METADATA if (caps->aux_support) return; -#endif caps->min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; caps->max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; @@ -4816,24 +4808,20 @@ static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, { if (!caps) return 0; -#ifdef HAVE_HDR_SINK_METADATA if (caps->aux_support) { // Firmware limits are in nits, DC API wants millinits. *max = 1000 * caps->aux_max_input_signal; *min = 1000 * caps->aux_min_input_signal; } else { -#endif // Firmware limits are 8-bit, PWM control is 16-bit. *max = 0x101 * caps->max_input_signal; *min = 0x101 * caps->min_input_signal; -#ifdef HAVE_HDR_SINK_METADATA } -#endif + return 1; } /* Rescale from [min..max] to [0..MAX_BACKLIGHT_LEVEL] */ -#ifdef HAVE_HDR_SINK_METADATA static inline u32 scale_input_to_fw(int min, int max, u64 input) { return DIV_ROUND_CLOSEST_ULL(input * MAX_BACKLIGHT_LEVEL, max - min); @@ -4915,25 +4903,19 @@ static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *cap return DIV_ROUND_CLOSEST_ULL((u64)max * (brightness - min), max - min); } -#endif static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, int bl_idx, u32 user_brightness) { struct amdgpu_dm_backlight_caps *caps; -#ifdef HAVE_HDR_SINK_METADATA struct dc_link *link; u32 brightness; -#else - uint32_t brightness = user_brightness; -#endif bool rc, reallow_idle = false; amdgpu_dm_update_backlight_caps(dm, bl_idx); caps = &dm->backlight_caps[bl_idx]; -#ifdef HAVE_HDR_SINK_METADATA dm->brightness[bl_idx] = user_brightness; /* update scratch register */ if (bl_idx == 0) @@ -4979,34 +4961,7 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, if (rc) dm->actual_brightness[bl_idx] = user_brightness; -#else - /* - * The brightness input is in the range 0-255 - * It needs to be rescaled to be between the - * requested min and max input signal - * - * It also needs to be scaled up by 0x101 to - * match the DC interface which has a range of - * 0 to 0xffff - */ - brightness = - brightness - * 0x101 - * (caps->max_input_signal - caps->min_input_signal) - / AMDGPU_MAX_BL_LEVEL - + caps->min_input_signal * 0x101; - - struct set_backlight_level_params backlight_level_params = { 0 }; - - backlight_level_params.backlight_pwm_u16_16 = brightness; - backlight_level_params.transition_time_in_ms = 0; - rc = dc_link_set_backlight_level(dm->backlight_link[bl_idx], &backlight_level_params); - - if (!rc) - DRM_ERROR("DM: Failed to update backlight on eDP[%d]\n", bl_idx); - if (rc) - dm->actual_brightness[bl_idx] = user_brightness; -#endif + } static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) @@ -5035,7 +4990,7 @@ static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, amdgpu_dm_update_backlight_caps(dm, bl_idx); caps = dm->backlight_caps[bl_idx]; -#ifdef HAVE_HDR_SINK_METADATA + if (caps.aux_support) { u32 avg, peak; @@ -5043,18 +4998,13 @@ static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, return dm->brightness[bl_idx]; return convert_brightness_to_user(&caps, avg); } -#endif ret = dc_link_get_backlight_level(link); if (ret == DC_ERROR_UNEXPECTED) return dm->brightness[bl_idx]; -#ifdef HAVE_HDR_SINK_METADATA return convert_brightness_to_user(&caps, ret); -#else - return ret; -#endif } static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) @@ -5192,9 +5142,8 @@ static void setup_backlight_device(struct amdgpu_display_manager *dm, amdgpu_dm_update_backlight_caps(dm, bl_idx); dm->backlight_link[bl_idx] = link; dm->num_of_edps++; -#ifdef HAVE_HDR_SINK_METADATA + update_connector_ext_caps(aconnector); -#endif } static void amdgpu_set_panel_orientation(struct drm_connector *connector); @@ -7441,7 +7390,6 @@ amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector) if (amdgpu_dm_connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) return false; -#ifdef HAVE_HDR_SINK_METADATA /* check for OLED panels */ if (amdgpu_dm_connector->bl_idx >= 0) { struct drm_device *drm = amdgpu_dm_connector->base.dev; @@ -7452,7 +7400,6 @@ amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector) if (caps->aux_support) return false; } -#endif return true; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index a5895226732eb..46852eaec41c1 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -171,7 +171,6 @@ struct amdgpu_dm_luminance_data { * Describe the backlight support for ACPI or eDP AUX. */ struct amdgpu_dm_backlight_caps { -#ifdef HAVE_HDR_SINK_METADATA /** * @ext_caps: Keep the data struct with all the information about the * display support for HDR. @@ -186,7 +185,6 @@ struct amdgpu_dm_backlight_caps { * in nits. */ u32 aux_max_input_signal; -#endif /** * @min_input_signal: minimum possible input in range 0-255. */ @@ -202,9 +200,7 @@ struct amdgpu_dm_backlight_caps { /** * @aux_support: Describes if the display supports AUX backlight. */ -#ifdef HAVE_HDR_SINK_METADATA bool aux_support; -#endif /** * @ac_level: the default brightness if booted on AC */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdr-sink-metadata.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdr-sink-metadata.m4 deleted file mode 100644 index 31c75e5910a4e..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-hdr-sink-metadata.m4 +++ /dev/null @@ -1,20 +0,0 @@ -dnl # -dnl # commit fbb5d0353c62d10c3699ec844d2d015a762952d7 -dnl # drm: Add HDR source metadata property -dnl # - -AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HAVE_HDR_SINK_METADATA], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - struct drm_connector *dc = NULL; - struct hdr_sink_metadata *p = NULL; - - p = &dc->hdr_sink_metadata; - ],[ - AC_DEFINE(HAVE_HDR_SINK_METADATA, 1, - [drm_connector_hdr_sink_metadata() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0d4d1a68c73f3..d0b38a34e0ebf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -101,7 +101,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS - AC_AMDGPU_DRM_CONNECTOR_HAVE_HDR_SINK_METADATA AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_AMDGPU_DRM_MODE_CONFIG AC_AMDGPU_DRM_VBLANK_CRTC_CONFIG From ef188252b6b1bd196165ad1681ac10fa8d178ef8 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 25 Jul 2025 14:41:59 +0800 Subject: [PATCH 1575/2653] drm/amdkcl: test if __dma_fence_is_later() has fence args It's caused v6.15-rc5-762-g549810e91815 "dma-fence: Change signature of __dma_fence_is_later" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 | 14 ++++++++++++++ include/kcl/kcl_fence.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 index 0523264d08807..d7dea8e24310d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 @@ -24,6 +24,20 @@ AC_DEFUN([AC_AMDGPU__DMA_FENCE_IS_LATER], [ ], [ AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_2ARGS, 1, [__dma_fence_is_later() is available and has 2 args]) + ],[ + dnl # + dnl # v6.15-rc5-762-g549810e91815 + dnl # dma-fence: Change signature of __dma_fence_is_later + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_fence *fence = NULL; + __dma_fence_is_later(fence, 0, 0); + ], [ + AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_WITH_FENCE_ARG, 1, + [__dma_fence_is_later() is available and has fence args]) + ]) ]) ]) ]) diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index 525268df513de..971500bce8566 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -16,6 +16,7 @@ #include #include +#ifndef HAVE__DMA_FENCE_IS_LATER_WITH_FENCE_ARG #if !defined(HAVE__DMA_FENCE_IS_LATER_2ARGS) #if !defined(HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO) @@ -50,6 +51,7 @@ static inline bool __dma_fence_is_later(u64 f1, u64 f2, #endif #endif /* HAVE__DMA_FENCE_IS_LATER_2ARGS */ +#endif /* HAVE__DMA_FENCE_IS_LATER_WITH_FENCE_ARG */ #if !defined(HAVE_DMA_FENCE_DESCRIBE) void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq); From 10c7ade005110440d8b247f7fabeb6e6bdbbe881 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 25 Jul 2025 14:51:42 +0800 Subject: [PATCH 1576/2653] drm/amdkcl: fix m4 detect issue Update CFLAGS and add NULL support for m4 detect Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 | 1 + .../dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 index 6d00ba9d43f37..17b182f9f186a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 @@ -6,6 +6,7 @@ AC_DEFUN([AC_AMDGPU_DMA_FENCE_DEDUP_ARRAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ #include + #include ], [ dma_fence_dedup_array(NULL, 0); ], [dma_fence_dedup_array], [drivers/dma-buf/dma-fence-unwrap.c],[ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 index 0f644628eb68c..8596ee2770a7f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 @@ -6,6 +6,7 @@ AC_DEFUN([AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ #include + #include struct drm_driver; ], [ const struct drm_driver *drv = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index 122ed7720922c..6c1a805826365 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -15,7 +15,7 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|g" \ -e "s|$PWD|\${PWD}|g") CFLAGS=$(echo $CFLAGS | sed -E 's/-W(array-bounds|error=array-bounds|unused-variable|error=unused-variable|unused-[^ ]*-variable|error=unused-[^ ]*-variable)( |$)//g') - + CFLAGS=$(echo $CFLAGS | sed -E "s/-Wunused/-Wno-unused/g") CPPFLAGS=$(echo $CFLAGS | \ sed 's| -|\n&|g' | \ sed -n -e '/conftest/d' \ From a84c2440e616eb0909c615a5e737f2b21d2bbad9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 25 Jul 2025 14:54:11 +0800 Subject: [PATCH 1577/2653] Bump AMDGPU version to 6.16.0 Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 70 ++++++++++++++++++------ drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 2 files changed, 55 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 90ea626ba5aca..3e9e04d6dbb13 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -64,12 +64,21 @@ /* __assign_str() wants 1 arguments */ #define HAVE_ASSIGN_STR_ONE_ARGUMENT 1 +/* attribute_group.bin_attrs_new is available */ +#define HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW 1 + /* amdgpu_attr_group->is_bin_visible is available */ #define HAVE_ATTRIBUTE_GROUP_IS_BIN_VISIBLE 1 /* backlight_device_set_brightness() is available */ #define HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS 1 +/* bin_attribute.read_new is available */ +#define HAVE_BIN_ATTRIBUTE_READ_NEW 1 + +/* bin_attribute.read is const args */ +#define HAVE_BIN_ATTR_CONST_ARGS 1 + /* bitmap_free(),bitmap_alloc(),bitmap_zalloc is available */ #define HAVE_BITMAP_FUNCS 1 @@ -148,6 +157,9 @@ /* dma_fence_describe() is available */ #define HAVE_DMA_FENCE_DESCRIBE 1 +/* dma_fence_init64() is available */ +#define HAVE_DMA_FENCE_INIT64 1 + /* dma_fence_is_container() is available */ #define HAVE_DMA_FENCE_IS_CONTAINER 1 @@ -158,7 +170,7 @@ #define HAVE_DMA_FENCE_OPS_SET_DEADLINE 1 /* struct dma_fence_ops has use_64bit_seqno field */ -#define HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO 1 +/* #undef HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO */ /* dma_fence_TIMESTAMP() is available */ #define HAVE_DMA_FENCE_TIMESTAMP 1 @@ -184,6 +196,9 @@ /* down_write_killable() is available */ #define HAVE_DOWN_WRITE_KILLABLE 1 +/* drmm_cgroup_register_region() is available */ +#define HAVE_DRMM_CGROUP_REGISTER_REGION 1 + /* drm_add_override_edid_modes() is available */ /* #undef HAVE_DRM_ADD_OVERRIDE_EDID_MODES */ @@ -203,7 +218,6 @@ /* drm_atomic_plane_enabling() is available */ #define HAVE_DRM_ATOMIC_PLANE_ENABLING 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_CLIENTS_DRM_CLIENT_SETUP_H 1 @@ -574,7 +588,10 @@ /* drm_fb_helper_init() has 3 args */ /* #undef HAVE_DRM_FB_HELPER_INIT_3ARGS */ -/* drm_file->client_name is available */ +/* struct drm_file->client_id is available */ +#define HAVE_DRM_FILE_CLIENT_ID 1 + +/* struct drm_file->client_name is available */ #define HAVE_DRM_FILE_CLIENT_NAME 1 /* drm_file_err() is available */ @@ -760,15 +777,15 @@ /* get_user_pages() remove vmas argument */ #define HAVE_GET_USER_PAGES_REMOVE_VMAS 1 -/* drm_connector_hdr_sink_metadata() is available */ -#define HAVE_HDR_SINK_METADATA 1 - /* hmm remove the customizable pfn format */ #define HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT 1 /* hmm_range_fault() wants 1 arg */ #define HAVE_HMM_RANGE_FAULT_1ARG 1 +/* hrtimer_setup() is available */ +#define HAVE_HRTIMER_SETUP 1 + /* hypervisor_is_type() is available */ #define HAVE_HYPERVISOR_IS_TYPE 1 @@ -796,6 +813,9 @@ /* io_mapping_unmap_local() is available */ #define HAVE_IO_MAPPING_UNMAP_LOCAL 1 +/* irq_domain_create_linear() is available */ +#define HAVE_IRQ_DOMAIN_CREATE_LINEAR 1 + /* is_cow_mapping() is available */ #define HAVE_IS_COW_MAPPING 1 @@ -823,6 +843,9 @@ /* kmap_local_* is available */ #define HAVE_KMAP_LOCAL 1 +/* kmap_local_page_try_from_panic() is available */ +#define HAVE_KMAP_LOCAL_PAGE_TRY_FROM_PANIC 1 + /* krealloc_array() is available */ #define HAVE_KREALLOC_ARRAY 1 @@ -886,9 +909,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_CLEANUP_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_COMPILER_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_LINUX_COMPILER_ATTRIBUTES_H 1 @@ -986,7 +1006,7 @@ #define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 /* mmap_assert_write_locked() is available */ -#define HAVE_MMAP_ASSERT_WRITE_LOCKED 1 +/* #undef HAVE_MMAP_ASSERT_WRITE_LOCKED */ /* mmput_async() is available */ #define HAVE_MMPUT_ASYNC 1 @@ -1051,6 +1071,9 @@ /* PIDTYPE is availablea */ #define HAVE_PIDTYPE_TGID 1 +/* pm_hibernate_is_recovering() is available */ +#define HAVE_PM_HIBERNATE_IS_RECOVERING 1 + /* pm_runtime_get_if_active() has one parameters */ #define HAVE_PM_RUNTIME_GET_IF_ACTIVE_1ARGS 1 @@ -1075,6 +1098,9 @@ /* radix_tree_iter_delete() is available */ #define HAVE_RADIX_TREE_ITER_DELETE 1 +/* ratelimit_state_reset_interval() is available */ +#define HAVE_RATELIMIT_STATE_RESET_INTERVAL 1 + /* rb_add_cached is available */ #define HAVE_RB_ADD_CACHED 1 @@ -1096,15 +1122,18 @@ /* shmem_read_folio() is available */ #define HAVE_SHMEM_READ_FOLIO 1 +/* shmem_writeout() is available */ +#define HAVE_SHMEM_WRITEOUT 1 + /* shrinker_register() is available */ #define HAVE_SHRINKER_REGISTER 1 -/* smca_get_bank_type(x) is available */ -/* #undef HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT */ - /* size_mul() is available */ #define HAVE_SIZE_MUL 1 +/* smca_get_bank_type(x) is available */ +/* #undef HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT */ + /* whether smca_get_bank_type(x, x) is available */ #define HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS 1 @@ -1184,6 +1213,9 @@ /* time64_to_tm() is available */ #define HAVE_TIME64_TO_TM 1 +/* timer_delete() is available */ +#define HAVE_TIMER_DELETE 1 + /* topology_num_cores_per_package is availablea */ #define HAVE_TOPOLOGY_NUM_CORES_PER_PACKAGE 1 @@ -1253,8 +1285,11 @@ /* __dma_fence_is_later() is available and has 2 args */ /* #undef HAVE__DMA_FENCE_IS_LATER_2ARGS */ +/* __dma_fence_is_later() is available and has fence args */ +#define HAVE__DMA_FENCE_IS_LATER_WITH_FENCE_ARG 1 + /* __dma_fence_is_later() is available and has ops arg */ -#define HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG 1 +/* #undef HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG */ /* __drm_atomic_helper_crtc_reset() is available */ #define HAVE___DRM_ATOMIC_HELPER_CRTC_RESET 1 @@ -1272,7 +1307,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 6.14.0" +#define PACKAGE_STRING "amdgpu-dkms 6.16.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1281,7 +1316,10 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "6.14.0" +#define PACKAGE_VERSION "6.16.0" + +/* drm_file->debugfs_client is available */ +#define STRUCT_DRM_FILE_DEBUGFS_CLIENT 1 #include "config-amd-chips.h" diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 8aeb6183e9faa..4f884d6bc20f6 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.14.0) +AC_INIT(amdgpu-dkms, 6.16.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 0a411ba495a96556bccce6351358f01ca834ae94 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 4 Aug 2025 10:15:28 +0800 Subject: [PATCH 1578/2653] drm/amdkcl: fix intree build detect issue for __dma_fence_is_later Signed-off-by: Bob Zhou --- .../gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 | 50 +++++++++---------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 index d7dea8e24310d..deb282b53858e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 @@ -1,43 +1,43 @@ dnl # -dnl # v5.1-rc2-1115-g5e498abf1485 -dnl # dma-buf: explicitely note that dma-fence-chains use 64bit seqno +dnl # v6.15-rc5-762-g549810e91815 +dnl # dma-fence: Change signature of __dma_fence_is_later dnl # AC_DEFUN([AC_AMDGPU__DMA_FENCE_IS_LATER], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - const struct dma_fence_ops *ops = NULL; - __dma_fence_is_later(0, 0, ops); - ], [ - AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG, 1, - [__dma_fence_is_later() is available and has ops arg]) - ], [ - dnl # - dnl # v4.20-rc4-931-gb312d8ca3a7c - dnl # dma-buf: make fence sequence numbers 64 bit v2 - dnl # AC_KERNEL_TRY_COMPILE([ #include ], [ - __dma_fence_is_later(0, 0); + struct dma_fence *fence = NULL; + __dma_fence_is_later(fence, 0, 0); ], [ - AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_2ARGS, 1, - [__dma_fence_is_later() is available and has 2 args]) + AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_WITH_FENCE_ARG, 1, + [__dma_fence_is_later() is available and has fence args]) ],[ dnl # - dnl # v6.15-rc5-762-g549810e91815 - dnl # dma-fence: Change signature of __dma_fence_is_later + dnl # v5.1-rc2-1115-g5e498abf1485 + dnl # dma-buf: explicitely note that dma-fence-chains use 64bit seqno dnl # AC_KERNEL_TRY_COMPILE([ #include ], [ - struct dma_fence *fence = NULL; - __dma_fence_is_later(fence, 0, 0); + const struct dma_fence_ops *ops = NULL; + __dma_fence_is_later(0, 0, ops); ], [ - AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_WITH_FENCE_ARG, 1, - [__dma_fence_is_later() is available and has fence args]) - ]) + AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG, 1, + [__dma_fence_is_later() is available and has ops arg]) + ], [ + dnl # + dnl # v4.20-rc4-931-gb312d8ca3a7c + dnl # dma-buf: make fence sequence numbers 64 bit v2 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + __dma_fence_is_later(0, 0); + ], [ + AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_2ARGS, 1, + [__dma_fence_is_later() is available and has 2 args]) + ]) ]) ]) ]) From f2263ab7deb8ba08c8464b80936e81007ab61634 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 16 Apr 2025 13:53:05 -0400 Subject: [PATCH 1579/2653] drm/amdkfd: enable host trap PC Sampling on gfx12 Signed-off-by: James Zhu Reviewed-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index b2fefc190db39..7e21b69f635bb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -38,9 +38,10 @@ * 1.2 - Support gfx9_5_0 Host Trap PC sampling * 1.3 - Update 1st level trap handler for Stochastic PC sampling * 1.4 - Support gfx9_5_0 Stochastic PC sampling + * 1.5 - Support gfx12_0_0 and gfx12_0_1 Host Trap PC sampling */ #define KFD_IOCTL_PCS_MAJOR_VERSION 1 -#define KFD_IOCTL_PCS_MINOR_VERSION 4 +#define KFD_IOCTL_PCS_MINOR_VERSION 5 struct supported_pc_sample_info { uint32_t ip_version; @@ -60,6 +61,8 @@ struct supported_pc_sample_info supported_formats[] = { { IP_VERSION(9, 4, 3), &sample_info_stoch_cycle_9_4_3 }, { IP_VERSION(9, 5, 0), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 5, 0), &sample_info_stoch_cycle_9_4_3 }, + { IP_VERSION(12, 0, 0), &sample_info_hosttrap_9_0_0 }, + { IP_VERSION(12, 0, 1), &sample_info_hosttrap_9_0_0 }, }; static int kfd_pc_sample_thread(void *param) From d73d1732d68b031d38112265c9793bc497a766c7 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Wed, 4 Dec 2024 17:49:08 -0500 Subject: [PATCH 1580/2653] drm/amdkfd: Improve signal event slow path If event slot is not signaled, kfd_signal_event_interrupt goes to slow path to scan all event slots to find the signaled event, this is needed for old ASICs that don't have the event ID or the event IDs are incorrect in the IH payload. There is case that GPU signal the same event twice, then driver process the first event interrupt, set_event and event slot is auto-reset, then for the second event interrupt, KFD goes to slow path as event is not signaled, just drop the second event interrupt because the application only need wakeup once. Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_events.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index 4be85487983a1..766b061d9fd98 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -760,6 +760,16 @@ void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, uint64_t *slots = page_slots(p->signal_page); uint32_t id; + /* + * If id is valid but slot is not signaled, GPU may signal the same event twice + * before driver have chance to process the first interrupt, then signal slot is + * auto-reset after set_event wakeup the user space, just drop the second event as + * the application only need wakeup once. + */ + if ((valid_id_bits > 31 || (1U << valid_id_bits) >= KFD_SIGNAL_EVENT_LIMIT) && + partial_id < KFD_SIGNAL_EVENT_LIMIT && slots[partial_id] == UNSIGNALED_EVENT_SLOT) + goto out_unlock; + if (valid_id_bits) pr_debug_ratelimited("Partial ID invalid: %u (%u valid bits)\n", partial_id, valid_id_bits); @@ -788,6 +798,7 @@ void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, } } +out_unlock: rcu_read_unlock(); kfd_unref_process(p); } From 44c4a635aa1adec5a46f3ab328f5963e2884088f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 6 Aug 2025 13:27:04 +0800 Subject: [PATCH 1581/2653] drm/amdkcl: wrap code under HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW It's caused by 2d0f5001b61c4831d413d12c10caed0e99d73b25 "drm/amdgpu: Constify 'struct bin_attribute'" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 26be425de4351..c8e8bf192b014 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -4257,7 +4257,11 @@ static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, * Writing to this file will stage an IFWI for update. Reading from this file * will trigger the update process. */ +#ifdef HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW static const struct bin_attribute psp_vbflash_bin_attr = { +#else +static struct bin_attribute psp_vbflash_bin_attr = { +#endif .attr = {.name = "psp_vbflash", .mode = 0660}, .size = 0, #ifdef HAVE_BIN_ATTRIBUTE_READ_NEW From 8a5f87954988c9b227e1f837a34dfa0283dfa000 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 7 Aug 2025 13:26:31 +0800 Subject: [PATCH 1582/2653] drm/amdkcl: add ttm_bo_internal.h support for ttm_bo_vm.c It's caused by 9ec1ac835e489b9ab2776c0cbbb1b1ca813923a2 "drm/ttm: make ttm_bo_get internal" som old kernel need ttm_bo_get() that has been moved into ttm_bo_internal.h Signed-off-by: Bob Zhou --- drivers/gpu/drm/ttm/ttm_bo_vm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 95b722824f265..02cd28a42f3da 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -42,6 +42,9 @@ #include #include +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +#include "ttm_bo_internal.h" +#endif static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, struct vm_fault *vmf, From 60e6f8027370a91310e1fc700da838c124475bef Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Mon, 28 Jul 2025 18:27:06 +0530 Subject: [PATCH 1583/2653] drm/amdgpu: Fix unintended error log in VCN5_0_0 The error log is supposed to be gaurded under if failure condition. Fixes: 29ef09ead572 ("drm/amdgpu: Check vcn sram load return value") Signed-off-by: Sathishkumar S Reviewed-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index d74832f28b106..1b60aacbe9bc5 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -769,9 +769,10 @@ static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, if (indirect) { ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); - dev_err(adev->dev, "%s: vcn sram load failed %d\n", __func__, ret); - if (ret) + if (ret) { + dev_err(adev->dev, "%s: vcn sram load failed %d\n", __func__, ret); return ret; + } } ring = &adev->vcn.inst[inst_idx].ring_enc[0]; From e5bfeecb77eca1abaf47ebe0e41bdea966be4c36 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 27 May 2025 23:19:29 -0400 Subject: [PATCH 1584/2653] drm/amdgpu/gfx9: re-emit unprocessed state on kcq reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Re-emit the unprocessed state after resetting the queue. Reviewed-by: Jesse Zhang Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 949d543a97628..dea25030d57a9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -7321,7 +7321,7 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring, if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; - drm_sched_wqueue_stop(&ring->sched); + amdgpu_ring_reset_helper_begin(ring, timedout_fence); spin_lock_irqsave(&kiq->ring_lock, flags); @@ -7378,13 +7378,7 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring, DRM_ERROR("fail to remap queue\n"); return r; } - - r = amdgpu_ring_test_ring(ring); - if (r) - return r; - amdgpu_fence_driver_force_completion(ring); - drm_sched_wqueue_start(&ring->sched); - return 0; + return amdgpu_ring_reset_helper_end(ring, timedout_fence); } static void gfx_v9_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) From 04a5b872fb21a4dc4afb287ce95f5ae19a5e9a8c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 27 May 2025 23:23:53 -0400 Subject: [PATCH 1585/2653] drm/amdgpu/gfx9.4.3: re-emit unprocessed state on kcq reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Re-emit the unprocessed state after resetting the queue. Reviewed-by: Jesse Zhang Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 5ae8f484608af..6abb88cbfd6f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -3735,7 +3735,7 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; - drm_sched_wqueue_stop(&ring->sched); + amdgpu_ring_reset_helper_begin(ring, timedout_fence); spin_lock_irqsave(&kiq->ring_lock, flags); @@ -3792,12 +3792,7 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, return r; } - r = amdgpu_ring_test_ring(ring); - if (r) - return r; - amdgpu_fence_driver_force_completion(ring); - drm_sched_wqueue_start(&ring->sched); - return 0; + return amdgpu_ring_reset_helper_end(ring, timedout_fence); } enum amdgpu_gfx_cp_ras_mem_id { From b845b430911df89fc60927cd80f8b7a77b6e7446 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 23 May 2025 00:33:04 -0400 Subject: [PATCH 1586/2653] drm/amdgpu/gfx10: re-emit unprocessed state on ring reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Re-emit the unprocessed state after resetting the queue. Drop the soft_recovery callbacks as the queue reset replaces it. Reviewed-by: Jesse Zhang Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 35 +++----------------------- 1 file changed, 4 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 27b96459bcbee..c9cb64260cd1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -9156,21 +9156,6 @@ static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, ref, mask); } -static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, - unsigned int vmid) -{ - struct amdgpu_device *adev = ring->adev; - uint32_t value = 0; - - value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); - value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); - value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); - value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); - amdgpu_gfx_rlc_enter_safe_mode(adev, 0); - WREG32_SOC15(GC, 0, mmSQ_CMD, value); - amdgpu_gfx_rlc_exit_safe_mode(adev, 0); -} - static void gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, uint32_t me, uint32_t pipe, @@ -9650,7 +9635,7 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; - drm_sched_wqueue_stop(&ring->sched); + amdgpu_ring_reset_helper_begin(ring, timedout_fence); spin_lock_irqsave(&kiq->ring_lock, flags); @@ -9699,12 +9684,7 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, if (r) return r; - r = amdgpu_ring_test_ring(ring); - if (r) - return r; - amdgpu_fence_driver_force_completion(ring); - drm_sched_wqueue_start(&ring->sched); - return 0; + return amdgpu_ring_reset_helper_end(ring, timedout_fence); } static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, @@ -9723,7 +9703,7 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; - drm_sched_wqueue_stop(&ring->sched); + amdgpu_ring_reset_helper_begin(ring, timedout_fence); spin_lock_irqsave(&kiq->ring_lock, flags); @@ -9777,12 +9757,7 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, if (r) return r; - r = amdgpu_ring_test_ring(ring); - if (r) - return r; - amdgpu_fence_driver_force_completion(ring); - drm_sched_wqueue_start(&ring->sched); - return 0; + return amdgpu_ring_reset_helper_end(ring, timedout_fence); } static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) @@ -10043,7 +10018,6 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { .emit_wreg = gfx_v10_0_ring_emit_wreg, .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, - .soft_recovery = gfx_v10_0_ring_soft_recovery, .emit_mem_sync = gfx_v10_0_emit_mem_sync, .reset = gfx_v10_0_reset_kgq, .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader, @@ -10084,7 +10058,6 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { .emit_wreg = gfx_v10_0_ring_emit_wreg, .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, - .soft_recovery = gfx_v10_0_ring_soft_recovery, .emit_mem_sync = gfx_v10_0_emit_mem_sync, .reset = gfx_v10_0_reset_kcq, .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader, From 4c014da8e3b0fb677a8c26736ba8c8dea3b6857e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 27 May 2025 22:05:13 -0400 Subject: [PATCH 1587/2653] drm/amdgpu/gfx11: re-emit unprocessed state on ring reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Re-emit the unprocessed state after resetting the queue. Drop the soft_recovery callbacks as the queue reset replaces it. Reviewed-by: Jesse Zhang Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 35 +++----------------------- 1 file changed, 4 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index a1830f0472508..63e4f5b57c059 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6293,21 +6293,6 @@ static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, ref, mask, 0x20); } -static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, - unsigned vmid) -{ - struct amdgpu_device *adev = ring->adev; - uint32_t value = 0; - - value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); - value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); - value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); - value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); - amdgpu_gfx_rlc_enter_safe_mode(adev, 0); - WREG32_SOC15(GC, 0, regSQ_CMD, value); - amdgpu_gfx_rlc_exit_safe_mode(adev, 0); -} - static void gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, uint32_t me, uint32_t pipe, @@ -6841,7 +6826,7 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, if (!(adev->gfx.gfx_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) return -EOPNOTSUPP; - drm_sched_wqueue_stop(&ring->sched); + amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); if (r) { @@ -6864,12 +6849,7 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, return r; } - r = amdgpu_ring_test_ring(ring); - if (r) - return r; - amdgpu_fence_driver_force_completion(ring); - drm_sched_wqueue_start(&ring->sched); - return 0; + return amdgpu_ring_reset_helper_end(ring, timedout_fence); } static int gfx_v11_0_reset_compute_pipe(struct amdgpu_ring *ring) @@ -7012,7 +6992,7 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) return -EOPNOTSUPP; - drm_sched_wqueue_stop(&ring->sched); + amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); if (r) { @@ -7033,12 +7013,7 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, return r; } - r = amdgpu_ring_test_ring(ring); - if (r) - return r; - amdgpu_fence_driver_force_completion(ring); - drm_sched_wqueue_start(&ring->sched); - return 0; + return amdgpu_ring_reset_helper_end(ring, timedout_fence); } static void gfx_v11_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) @@ -7274,7 +7249,6 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { .emit_wreg = gfx_v11_0_ring_emit_wreg, .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, - .soft_recovery = gfx_v11_0_ring_soft_recovery, .emit_mem_sync = gfx_v11_0_emit_mem_sync, .reset = gfx_v11_0_reset_kgq, .emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader, @@ -7316,7 +7290,6 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { .emit_wreg = gfx_v11_0_ring_emit_wreg, .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, - .soft_recovery = gfx_v11_0_ring_soft_recovery, .emit_mem_sync = gfx_v11_0_emit_mem_sync, .reset = gfx_v11_0_reset_kcq, .emit_cleaner_shader = gfx_v11_0_ring_emit_cleaner_shader, From e78775a07c8d7701ee1d111e838b40834ab082c8 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 27 May 2025 22:29:31 -0400 Subject: [PATCH 1588/2653] drm/amdgpu/gfx12: re-emit unprocessed state on ring reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Re-emit the unprocessed state after resetting the queue. Drop the soft_recovery callbacks as the queue reset replaces it. Reviewed-by: Jesse Zhang Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 35 +++----------------------- 1 file changed, 4 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index dd855031dfc66..97bd15e59bb87 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -4705,21 +4705,6 @@ static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, ref, mask, 0x20); } -static void gfx_v12_0_ring_soft_recovery(struct amdgpu_ring *ring, - unsigned vmid) -{ - struct amdgpu_device *adev = ring->adev; - uint32_t value = 0; - - value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); - value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); - value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); - value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); - amdgpu_gfx_rlc_enter_safe_mode(adev, 0); - WREG32_SOC15(GC, 0, regSQ_CMD, value); - amdgpu_gfx_rlc_exit_safe_mode(adev, 0); -} - static void gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, uint32_t me, uint32_t pipe, @@ -5342,7 +5327,7 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, if (!(adev->gfx.gfx_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) return -EOPNOTSUPP; - drm_sched_wqueue_stop(&ring->sched); + amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); if (r) { @@ -5364,12 +5349,7 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, return r; } - r = amdgpu_ring_test_ring(ring); - if (r) - return r; - amdgpu_fence_driver_force_completion(ring); - drm_sched_wqueue_start(&ring->sched); - return 0; + return amdgpu_ring_reset_helper_end(ring, timedout_fence); } static int gfx_v12_0_reset_compute_pipe(struct amdgpu_ring *ring) @@ -5465,7 +5445,7 @@ static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) return -EOPNOTSUPP; - drm_sched_wqueue_stop(&ring->sched); + amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); if (r) { @@ -5486,12 +5466,7 @@ static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, return r; } - r = amdgpu_ring_test_ring(ring); - if (r) - return r; - amdgpu_fence_driver_force_completion(ring); - drm_sched_wqueue_start(&ring->sched); - return 0; + return amdgpu_ring_reset_helper_end(ring, timedout_fence); } static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring) @@ -5569,7 +5544,6 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { .emit_wreg = gfx_v12_0_ring_emit_wreg, .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, - .soft_recovery = gfx_v12_0_ring_soft_recovery, .emit_mem_sync = gfx_v12_0_emit_mem_sync, .reset = gfx_v12_0_reset_kgq, .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, @@ -5608,7 +5582,6 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { .emit_wreg = gfx_v12_0_ring_emit_wreg, .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, - .soft_recovery = gfx_v12_0_ring_soft_recovery, .emit_mem_sync = gfx_v12_0_emit_mem_sync, .reset = gfx_v12_0_reset_kcq, .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader, From 0a0cc327cebc1b72dd8543f6cdd471d9ebbb1854 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 26 Jun 2025 09:52:55 -0400 Subject: [PATCH 1589/2653] drm/amdgpu/sdma5: re-emit unprocessed state on ring reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Re-emit the unprocessed state after resetting the queue. Reviewed-by: Jesse Zhang Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 999705e7b2641..d8c19601dd2e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1555,11 +1555,15 @@ static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring, return -EINVAL; } + amdgpu_ring_reset_helper_begin(ring, timedout_fence); + amdgpu_amdkfd_suspend(adev, true); - r = amdgpu_sdma_reset_engine(adev, ring->me, false); + r = amdgpu_sdma_reset_engine(adev, ring->me, true); amdgpu_amdkfd_resume(adev, true); + if (r) + return r; - return r; + return amdgpu_ring_reset_helper_end(ring, timedout_fence); } static int sdma_v5_0_stop_queue(struct amdgpu_ring *ring) From ac854545b9a49ce46fd4c1bd049bcf8d0a31fdeb Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Fri, 25 Jul 2025 17:34:30 -0400 Subject: [PATCH 1590/2653] drm/amdgpu: Fix incorrect PTE flags gfx12 NV10 mask used for gfx12. Fix it. Put back DCC flag and default mtype to MTYPE_NC. Fixes: b8c76c59987a ("drm/amdgpu: rework how PTE flags are generated") Suggested-by: Felix Kuehling Co-authored-by: Harish Kasiviswanathan Signed-off-by: David Yat Sin Signed-off-by: Harish Kasiviswanathan Tested-by: Mark Broadworth Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 5e9aeaa69d284..a0a5367f9dc40 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -511,10 +511,11 @@ static void gmc_v12_0_get_vm_pte(struct amdgpu_device *adev, *flags &= ~AMDGPU_PTE_VALID; } - if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | - AMDGPU_GEM_CREATE_EXT_COHERENT | - AMDGPU_GEM_CREATE_UNCACHED)) - *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC); + if (bo && bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC) + *flags |= AMDGPU_PTE_DCC; + + if (bo && bo->flags & AMDGPU_GEM_CREATE_UNCACHED) + *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC); } static unsigned gmc_v12_0_get_vbios_fb_size(struct amdgpu_device *adev) From b2736260e328c400a40a1cf0e6117161c4253657 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 24 Jul 2025 22:12:21 -0500 Subject: [PATCH 1591/2653] drm/amd: Restore cached power limit during resume The power limit will be cached in smu->current_power_limit but if the ASIC goes into S3 this value won't be restored. Restore the value during SMU resume. Acked-by: Alex Deucher Link: https://lore.kernel.org/r/20250725031222.3015095-2-superm1@kernel.org Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 02c1448f090e7..a594cc72547ad 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2226,6 +2226,12 @@ static int smu_resume(struct amdgpu_ip_block *ip_block) adev->pm.dpm_enabled = true; + if (smu->current_power_limit) { + ret = smu_set_power_limit(smu, smu->current_power_limit); + if (ret && ret != -EOPNOTSUPP) + return ret; + } + dev_info(adev->dev, "SMU is resumed successfully!\n"); return 0; From d5fd7455c65e02b5616068ccf70c14d46a20346b Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Wed, 16 Jul 2025 22:04:28 +0000 Subject: [PATCH 1592/2653] drm/amdkfd: Fix checkpoint-restore on multi-xcc GPUs with multi-xcc have multiple MQDs per queue. This patch saves and restores all the MQDs within the partition. Signed-off-by: David Yat Sin Reviewed-by: Felix Kuehling --- .../drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 61 ++++++++++++++++--- .../amd/amdkfd/kfd_process_queue_manager.c | 20 ++++-- 3 files changed, 67 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index da063a8a03645..b11c1e9c873da 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -2779,7 +2779,7 @@ static void get_queue_checkpoint_info(struct device_queue_manager *dqm, dqm_lock(dqm); mqd_mgr = dqm->mqd_mgrs[mqd_type]; - *mqd_size = mqd_mgr->mqd_size; + *mqd_size = mqd_mgr->mqd_size * NUM_XCC(mqd_mgr->dev->xcc_mask); *ctl_stack_size = 0; if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE && mqd_mgr->get_checkpoint_info) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index 6222cbd247951..4ebb1c2c4fe88 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -430,7 +430,7 @@ static void get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stac { struct v9_mqd *m = get_mqd(mqd); - *ctl_stack_size = m->cp_hqd_cntl_stack_size; + *ctl_stack_size = m->cp_hqd_cntl_stack_size * NUM_XCC(mm->dev->xcc_mask); } static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) @@ -445,6 +445,24 @@ static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, voi memcpy(ctl_stack_dst, ctl_stack, m->cp_hqd_cntl_stack_size); } +static void checkpoint_mqd_v9_4_3(struct mqd_manager *mm, + void *mqd, + void *mqd_dst, + void *ctl_stack_dst) +{ + struct v9_mqd *m; + int xcc; + uint64_t size = get_mqd(mqd)->cp_mqd_stride_size; + + for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { + m = get_mqd(mqd + size * xcc); + + checkpoint_mqd(mm, m, + (uint8_t *)mqd_dst + sizeof(*m) * xcc, + (uint8_t *)ctl_stack_dst + m->cp_hqd_cntl_stack_size * xcc); + } +} + static void restore_mqd(struct mqd_manager *mm, void **mqd, struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, struct queue_properties *qp, @@ -821,13 +839,35 @@ static void restore_mqd_v9_4_3(struct mqd_manager *mm, void **mqd, const void *mqd_src, const void *ctl_stack_src, u32 ctl_stack_size) { - restore_mqd(mm, mqd, mqd_mem_obj, gart_addr, qp, mqd_src, ctl_stack_src, ctl_stack_size); - if (amdgpu_sriov_multi_vf_mode(mm->dev->adev)) { - struct v9_mqd *m; + struct kfd_mem_obj xcc_mqd_mem_obj; + u32 mqd_ctl_stack_size; + struct v9_mqd *m; + u32 num_xcc; + int xcc; - m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; - m->cp_hqd_pq_doorbell_control |= 1 << - CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT; + uint64_t offset = mm->mqd_stride(mm, qp); + + mm->dev->dqm->current_logical_xcc_start++; + + num_xcc = NUM_XCC(mm->dev->xcc_mask); + mqd_ctl_stack_size = ctl_stack_size / num_xcc; + + memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj)); + + /* Set the MQD pointer and gart address to XCC0 MQD */ + *mqd = mqd_mem_obj->cpu_ptr; + if (gart_addr) + *gart_addr = mqd_mem_obj->gpu_addr; + + for (xcc = 0; xcc < num_xcc; xcc++) { + get_xcc_mqd(mqd_mem_obj, &xcc_mqd_mem_obj, offset * xcc); + restore_mqd(mm, (void **)&m, + &xcc_mqd_mem_obj, + NULL, + qp, + (uint8_t *)mqd_src + xcc * sizeof(*m), + (uint8_t *)ctl_stack_src + xcc * mqd_ctl_stack_size, + mqd_ctl_stack_size); } } static int destroy_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, @@ -964,7 +1004,6 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, mqd->is_occupied = kfd_is_occupied_cp; mqd->check_queue_active = check_queue_active; mqd->get_checkpoint_info = get_checkpoint_info; - mqd->checkpoint_mqd = checkpoint_mqd; mqd->mqd_size = sizeof(struct v9_mqd); mqd->mqd_stride = mqd_stride_v9; #if defined(CONFIG_DEBUG_FS) @@ -976,16 +1015,18 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, mqd->init_mqd = init_mqd_v9_4_3; mqd->load_mqd = load_mqd_v9_4_3; mqd->update_mqd = update_mqd_v9_4_3; - mqd->restore_mqd = restore_mqd_v9_4_3; mqd->destroy_mqd = destroy_mqd_v9_4_3; mqd->get_wave_state = get_wave_state_v9_4_3; + mqd->checkpoint_mqd = checkpoint_mqd_v9_4_3; + mqd->restore_mqd = restore_mqd_v9_4_3; } else { mqd->init_mqd = init_mqd; mqd->load_mqd = load_mqd; mqd->update_mqd = update_mqd; - mqd->restore_mqd = restore_mqd; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->get_wave_state = get_wave_state; + mqd->checkpoint_mqd = checkpoint_mqd; + mqd->restore_mqd = restore_mqd; } break; case KFD_MQD_TYPE_HIQ: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 81b4f9c82b51a..d91b0e498fc9d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -918,7 +918,10 @@ static int criu_checkpoint_queues_device(struct kfd_process_device *pdd, q_data = (struct kfd_criu_queue_priv_data *)q_private_data; - /* data stored in this order: priv_data, mqd, ctl_stack */ + /* + * data stored in this order: + * priv_data, mqd[xcc0], mqd[xcc1],..., ctl_stack[xcc0], ctl_stack[xcc1]... + */ q_data->mqd_size = mqd_size; q_data->ctl_stack_size = ctl_stack_size; @@ -967,7 +970,7 @@ int kfd_criu_checkpoint_queues(struct kfd_process *p, } static void set_queue_properties_from_criu(struct queue_properties *qp, - struct kfd_criu_queue_priv_data *q_data) + struct kfd_criu_queue_priv_data *q_data, uint32_t num_xcc) { qp->is_interop = false; qp->queue_percent = q_data->q_percent; @@ -980,7 +983,11 @@ static void set_queue_properties_from_criu(struct queue_properties *qp, qp->eop_ring_buffer_size = q_data->eop_ring_buffer_size; qp->ctx_save_restore_area_address = q_data->ctx_save_restore_area_address; qp->ctx_save_restore_area_size = q_data->ctx_save_restore_area_size; - qp->ctl_stack_size = q_data->ctl_stack_size; + if (q_data->type == KFD_QUEUE_TYPE_COMPUTE) + qp->ctl_stack_size = q_data->ctl_stack_size / num_xcc; + else + qp->ctl_stack_size = q_data->ctl_stack_size; + qp->type = q_data->type; qp->format = q_data->format; } @@ -1040,12 +1047,15 @@ int kfd_criu_restore_queue(struct kfd_process *p, goto exit; } - /* data stored in this order: mqd, ctl_stack */ + /* + * data stored in this order: + * mqd[xcc0], mqd[xcc1],..., ctl_stack[xcc0], ctl_stack[xcc1]... + */ mqd = q_extra_data; ctl_stack = mqd + q_data->mqd_size; memset(&qp, 0, sizeof(qp)); - set_queue_properties_from_criu(&qp, q_data); + set_queue_properties_from_criu(&qp, q_data, NUM_XCC(pdd->dev->adev->gfx.xcc_mask)); print_queue_properties(&qp); From 7445eb0d3b9423a99a47e0be99e3763a72611b43 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Mon, 21 Jul 2025 19:04:34 +0530 Subject: [PATCH 1593/2653] drm/amdgpu: Fix kdoc style in amdgpu_fence.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The initial comment block before amdgpu_fence_driver_guilty_force_completion() incorrectly used '/**' but is not a kernel-doc comment, causing build warnings. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:742: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Kernel queue reset handling Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index ddc5f28ab5f3c..d9516d2a1c66a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -737,7 +737,7 @@ void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) } -/** +/* * Kernel queue reset handling * * The driver can reset individual queues for most engines, but those queues From aac3f7e79282d8b7fd1f9a15d2a5d4935470fc4b Mon Sep 17 00:00:00 2001 From: Xiang Liu Date: Wed, 23 Jul 2025 14:28:35 +0800 Subject: [PATCH 1594/2653] drm/amdgpu: Update IPID value for bad page threshold CPER Update the IPID register value for bad page threshold CPER according to the latest definition. Signed-off-by: Xiang Liu Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c index 25252231a68a9..6c266f18c5981 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c @@ -206,6 +206,7 @@ int amdgpu_cper_entry_fill_bad_page_threshold_section(struct amdgpu_device *adev { struct cper_sec_desc *section_desc; struct cper_sec_nonstd_err *section; + uint32_t socket_id; section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx)); section = (struct cper_sec_nonstd_err *)((uint8_t *)hdr + @@ -224,6 +225,9 @@ int amdgpu_cper_entry_fill_bad_page_threshold_section(struct amdgpu_device *adev section->ctx.reg_arr_size = sizeof(section->ctx.reg_dump); /* Hardcoded Reg dump for bad page threshold CPER */ + socket_id = (adev->smuio.funcs && adev->smuio.funcs->get_socket_id) ? + adev->smuio.funcs->get_socket_id(adev) : + 0; section->ctx.reg_dump[CPER_ACA_REG_CTL_LO] = 0x1; section->ctx.reg_dump[CPER_ACA_REG_CTL_HI] = 0x0; section->ctx.reg_dump[CPER_ACA_REG_STATUS_LO] = 0x137; @@ -234,8 +238,8 @@ int amdgpu_cper_entry_fill_bad_page_threshold_section(struct amdgpu_device *adev section->ctx.reg_dump[CPER_ACA_REG_MISC0_HI] = 0x0; section->ctx.reg_dump[CPER_ACA_REG_CONFIG_LO] = 0x2; section->ctx.reg_dump[CPER_ACA_REG_CONFIG_HI] = 0x1ff; - section->ctx.reg_dump[CPER_ACA_REG_IPID_LO] = 0x0; - section->ctx.reg_dump[CPER_ACA_REG_IPID_HI] = 0x96; + section->ctx.reg_dump[CPER_ACA_REG_IPID_LO] = (socket_id / 4) & 0x01; + section->ctx.reg_dump[CPER_ACA_REG_IPID_HI] = 0x096 | (((socket_id % 4) & 0x3) << 12); section->ctx.reg_dump[CPER_ACA_REG_SYND_LO] = 0x0; section->ctx.reg_dump[CPER_ACA_REG_SYND_HI] = 0x0; From d3f0369eb9e6bf3a421fd130c7096b699dba8916 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 24 Jul 2025 22:12:22 -0500 Subject: [PATCH 1595/2653] drm/amd: Restore cached manual clock settings during resume If the SCLK limits have been set before S3 they will not be restored. The limits are however cached in the driver and so they can be restored by running a commit sequence during resume. Acked-by: Alex Deucher Link: https://lore.kernel.org/r/20250725031222.3015095-3-superm1@kernel.org Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index a594cc72547ad..c9a9bc64cfa15 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -77,6 +77,9 @@ static void smu_power_profile_mode_get(struct smu_context *smu, static void smu_power_profile_mode_put(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile_mode); static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type); +static int smu_od_edit_dpm_table(void *handle, + enum PP_OD_DPM_TABLE_COMMAND type, + long *input, uint32_t size); static int smu_sys_get_pp_feature_mask(void *handle, char *buf) @@ -2195,6 +2198,7 @@ static int smu_resume(struct amdgpu_ip_block *ip_block) int ret; struct amdgpu_device *adev = ip_block->adev; struct smu_context *smu = adev->powerplay.pp_handle; + struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); if (amdgpu_sriov_multi_vf_mode(adev)) return 0; @@ -2232,6 +2236,12 @@ static int smu_resume(struct amdgpu_ip_block *ip_block) return ret; } + if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { + ret = smu_od_edit_dpm_table(smu, PP_OD_COMMIT_DPM_TABLE, NULL, 0); + if (ret) + return ret; + } + dev_info(adev->dev, "SMU is resumed successfully!\n"); return 0; From 7dc5ea6f7a9877c5cf21fa08a3af63e4d26fd95b Mon Sep 17 00:00:00 2001 From: Ce Sun Date: Sun, 27 Jul 2025 12:06:55 +0800 Subject: [PATCH 1596/2653] drm/amdgpu: Avoid rma causes GPU duplicate reset Try to ensure poison creation handle is completed in time to set device rma value. Signed-off-by: Ce Sun Signed-off-by: Stanley.Yang Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 17 ++++++++++------- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 1 + 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 6abc3e59f933f..af23953cce4fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3381,7 +3381,6 @@ static void amdgpu_ras_do_page_retirement(struct work_struct *work) page_retirement_dwork.work); struct amdgpu_device *adev = con->adev; struct ras_err_data err_data; - unsigned long err_cnt; /* If gpu reset is ongoing, delay retiring the bad pages */ if (amdgpu_in_reset(adev) || amdgpu_ras_in_recovery(adev)) { @@ -3393,13 +3392,9 @@ static void amdgpu_ras_do_page_retirement(struct work_struct *work) amdgpu_ras_error_data_init(&err_data); amdgpu_umc_handle_bad_pages(adev, &err_data); - err_cnt = err_data.err_addr_cnt; amdgpu_ras_error_data_fini(&err_data); - if (err_cnt && amdgpu_ras_is_rma(adev)) - amdgpu_ras_reset_gpu(adev); - amdgpu_ras_schedule_retirement_dwork(con, AMDGPU_RAS_RETIRE_PAGE_INTERVAL); } @@ -3453,6 +3448,9 @@ static int amdgpu_ras_poison_creation_handler(struct amdgpu_device *adev, if (total_detect_count) schedule_delayed_work(&ras->page_retirement_dwork, 0); + if (amdgpu_ras_is_rma(adev) && atomic_cmpxchg(&ras->rma_in_recovery, 0, 1) == 0) + amdgpu_ras_reset_gpu(adev); + return 0; } @@ -3489,6 +3487,12 @@ static int amdgpu_ras_poison_consumption_handler(struct amdgpu_device *adev, reset_flags |= msg.reset; } + /* + * Try to ensure poison creation handler is completed first + * to set rma if bad page exceed threshold. + */ + flush_delayed_work(&con->page_retirement_dwork); + /* for RMA, amdgpu_ras_poison_creation_handler will trigger gpu reset */ if (reset_flags && !amdgpu_ras_is_rma(adev)) { if (reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) @@ -3498,8 +3502,6 @@ static int amdgpu_ras_poison_consumption_handler(struct amdgpu_device *adev, else reset = reset_flags; - flush_delayed_work(&con->page_retirement_dwork); - con->gpu_reset_flags |= reset; amdgpu_ras_reset_gpu(adev); @@ -3670,6 +3672,7 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info) mutex_init(&con->recovery_lock); INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); atomic_set(&con->in_recovery, 0); + atomic_set(&con->rma_in_recovery, 0); con->eeprom_control.bad_channel_bitmap = 0; max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index 434e23c84962e..ff63020f9c6c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -522,6 +522,7 @@ struct amdgpu_ras { /* gpu recovery */ struct work_struct recovery_work; atomic_t in_recovery; + atomic_t rma_in_recovery; struct amdgpu_device *adev; /* error handler data */ struct ras_err_handler_data *eh_data; From 2c7b37aca5b29bda4ad3703438996877fb52ba50 Mon Sep 17 00:00:00 2001 From: Ce Sun Date: Sat, 26 Jul 2025 20:16:24 +0800 Subject: [PATCH 1597/2653] drm/amdgpu: Effective health check before reset Move amdgpu_device_health_check into amdgpu_device_gpu_recover to ensure that if the device is present can be checked before reset The reason is: 1.During the dpc event, the device where the dpc event occurs is not present on the bus 2.When both dpc event and ATHUB event occur simultaneously,the dpc thread holds the reset domain lock when detecting error,and the gpu recover thread acquires the hive lock.The device is simultaneously in the states of amdgpu_ras_in_recovery and occurs_dpc,so gpu recover thread will not go to amdgpu_device_health_check.It waits for the reset domain lock held by the dpc thread, but dpc thread has not released the reset domain lock.In the dpc callback slot_reset,to obtain the hive lock, the hive lock is held by the gpu recover thread at this time.So a deadlock occurred Signed-off-by: Ce Sun Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 26 +++++++--------------- 1 file changed, 8 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 64bfc04d17cea..b22e4ebf8efa2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6189,12 +6189,11 @@ static int amdgpu_device_health_check(struct list_head *device_list_handle) return ret; } -static int amdgpu_device_recovery_prepare(struct amdgpu_device *adev, +static void amdgpu_device_recovery_prepare(struct amdgpu_device *adev, struct list_head *device_list, struct amdgpu_hive_info *hive) { struct amdgpu_device *tmp_adev = NULL; - int r; /* * Build list of devices to reset. @@ -6214,14 +6213,6 @@ static int amdgpu_device_recovery_prepare(struct amdgpu_device *adev, } else { list_add_tail(&adev->reset_list, device_list); } - - if (!amdgpu_sriov_vf(adev) && (!adev->pcie_reset_ctx.occurs_dpc)) { - r = amdgpu_device_health_check(device_list); - if (r) - return r; - } - - return 0; } static void amdgpu_device_recovery_get_reset_lock(struct amdgpu_device *adev, @@ -6517,8 +6508,13 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, reset_context->hive = hive; INIT_LIST_HEAD(&device_list); - if (amdgpu_device_recovery_prepare(adev, &device_list, hive)) - goto end_reset; + amdgpu_device_recovery_prepare(adev, &device_list, hive); + + if (!amdgpu_sriov_vf(adev)) { + r = amdgpu_device_health_check(&device_list); + if (r) + goto end_reset; + } /* We need to lock reset domain only once both for XGMI and single device */ amdgpu_device_recovery_get_reset_lock(adev, &device_list); @@ -7031,12 +7027,6 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) int r = 0, i; u32 memsize; - /* PCI error slot reset should be skipped During RAS recovery */ - if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || - amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) && - amdgpu_ras_in_recovery(adev)) - return PCI_ERS_RESULT_RECOVERED; - dev_info(adev->dev, "PCI error: slot reset callback!!\n"); memset(&reset_context, 0, sizeof(reset_context)); From 48ddb3af2910476ea17648ee8a27e73b1c8099a8 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 29 May 2025 13:11:54 -0400 Subject: [PATCH 1598/2653] drm/amdgpu/sdma6: re-emit unprocessed state on ring reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Re-emit the unprocessed state after resetting the queue. Reviewed-by: Jesse Zhang Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 264d525325c21..d92a71c3f2f78 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1586,7 +1586,7 @@ static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring, return -EINVAL; } - drm_sched_wqueue_stop(&ring->sched); + amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true); if (r) @@ -1595,9 +1595,8 @@ static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring, r = sdma_v6_0_gfx_resume_instance(adev, ring->me, true); if (r) return r; - amdgpu_fence_driver_force_completion(ring); - drm_sched_wqueue_start(&ring->sched); - return 0; + + return amdgpu_ring_reset_helper_end(ring, timedout_fence); } static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev, From 5adc454af110eac84181e60319e4255d16088bb8 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 29 May 2025 13:12:35 -0400 Subject: [PATCH 1599/2653] drm/amdgpu/sdma7: re-emit unprocessed state on ring reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Re-emit the unprocessed state after resetting the queue. Reviewed-by: Jesse Zhang Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index d12a496f7378b..bfebdc0c3c615 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -817,7 +817,7 @@ static int sdma_v7_0_reset_queue(struct amdgpu_ring *ring, return -EINVAL; } - drm_sched_wqueue_stop(&ring->sched); + amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true); if (r) @@ -826,9 +826,8 @@ static int sdma_v7_0_reset_queue(struct amdgpu_ring *ring, r = sdma_v7_0_gfx_resume_instance(adev, ring->me, true); if (r) return r; - amdgpu_fence_driver_force_completion(ring); - drm_sched_wqueue_start(&ring->sched); - return 0; + + return amdgpu_ring_reset_helper_end(ring, timedout_fence); } /** From 25da771fca78fed60c1bd7c5dcdcb43d90bc5167 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Tue, 22 Jul 2025 17:58:29 +0200 Subject: [PATCH 1600/2653] drm/amd/display: Don't overwrite dce60_clk_mgr MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit dc_clk_mgr_create accidentally overwrites the dce60_clk_mgr with the dce_clk_mgr, causing incorrect behaviour on DCE6. Fix it by removing the extra dce_clk_mgr_construct. Fixes: 62eab49faae7 ("drm/amd/display: hide VGH asic specific structs") Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index 33b9d36619ff8..4071851f9e86d 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -158,7 +158,6 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p return NULL; } dce60_clk_mgr_construct(ctx, clk_mgr); - dce_clk_mgr_construct(ctx, clk_mgr); return &clk_mgr->base; } #endif From 758ec147a2f9eec87197beb75f50043ae32f6def Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Tue, 22 Jul 2025 17:58:30 +0200 Subject: [PATCH 1601/2653] drm/amd/display: Fix DCE 6.0 and 6.4 PLL programming. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Apparently, both DCE 6.0 and 6.4 have 3 PLLs, but PLL0 can only be used for DP. Make sure to initialize the correct amount of PLLs in DC for these DCE versions and use PLL0 only for DP. Also, on DCE 6.0 and 6.4, the PLL0 needs to be powered on at initialization as opposed to DCE 6.1 and 7.x which use a different clock source for DFS. The following functions were used as reference from the old radeon driver implementation of DCE 6.x: - radeon_atom_pick_pll - atombios_crtc_set_disp_eng_pll Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- .../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 5 +++ .../dc/resource/dce60/dce60_resource.c | 34 +++++++++++-------- 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index 26feefbb8990a..f5ad0a1770388 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -245,6 +245,11 @@ int dce_set_clock( pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10; pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; + /* DCE 6.0, DCE 6.4: engine clock is the same as PLL0 */ + if (clk_mgr_base->ctx->dce_version == DCE_VERSION_6_0 || + clk_mgr_base->ctx->dce_version == DCE_VERSION_6_4) + pxl_clk_params.pll_id = CLOCK_SOURCE_ID_PLL0; + if (clk_mgr_dce->dfs_bypass_active) pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS = true; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c index 58b59d52dc9d3..53b60044653f8 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c @@ -373,7 +373,7 @@ static const struct resource_caps res_cap = { .num_timing_generator = 6, .num_audio = 6, .num_stream_encoder = 6, - .num_pll = 2, + .num_pll = 3, .num_ddc = 6, }; @@ -389,7 +389,7 @@ static const struct resource_caps res_cap_64 = { .num_timing_generator = 2, .num_audio = 2, .num_stream_encoder = 2, - .num_pll = 2, + .num_pll = 3, .num_ddc = 2, }; @@ -973,21 +973,24 @@ static bool dce60_construct( if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { pool->base.dp_clock_source = - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); + /* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it here. */ pool->base.clock_sources[0] = - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); pool->base.clock_sources[1] = - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); pool->base.clk_src_count = 2; } else { pool->base.dp_clock_source = - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); pool->base.clock_sources[0] = - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); - pool->base.clk_src_count = 1; + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); + pool->base.clock_sources[1] = + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); + pool->base.clk_src_count = 2; } if (pool->base.dp_clock_source == NULL) { @@ -1365,21 +1368,24 @@ static bool dce64_construct( if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) { pool->base.dp_clock_source = - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); + /* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it here. */ pool->base.clock_sources[0] = - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); pool->base.clock_sources[1] = - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); pool->base.clk_src_count = 2; } else { pool->base.dp_clock_source = - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true); + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); pool->base.clock_sources[0] = - dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); - pool->base.clk_src_count = 1; + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); + pool->base.clock_sources[1] = + dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); + pool->base.clk_src_count = 2; } if (pool->base.dp_clock_source == NULL) { From acbd00157171772600c722cccc60d62a5e918280 Mon Sep 17 00:00:00 2001 From: Yunshui Jiang Date: Thu, 24 Jul 2025 09:37:53 +0800 Subject: [PATCH 1602/2653] drm/amdgpu: use kmalloc_array() instead of kmalloc() Use kmalloc_array() instead of kmalloc() with multiplication. kmalloc_array() is a safer way because of its multiply overflow check. Signed-off-by: Yunshui Jiang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index af23953cce4fb..4ea1e3287a739 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2636,7 +2636,7 @@ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, goto out; } - *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); + *bps = kmalloc_array(data->count, sizeof(struct ras_badpage), GFP_KERNEL); if (!*bps) { ret = -ENOMEM; goto out; @@ -2800,7 +2800,7 @@ static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, unsigned int old_space = data->count + data->space_left; unsigned int new_space = old_space + pages; unsigned int align_space = ALIGN(new_space, 512); - void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); + void *bps = kmalloc_array(align_space, sizeof(*data->bps), GFP_KERNEL); if (!bps) { return -ENOMEM; From c79e0a89ab65d237dfd565aa6efbabb54c0bf24a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 26 Jun 2025 09:53:18 -0400 Subject: [PATCH 1603/2653] drm/amdgpu/sdma5.2: re-emit unprocessed state on ring reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Re-emit the unprocessed state after resetting the queue. Reviewed-by: Jesse Zhang Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index e542195972dd4..5d56029e88a62 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1469,11 +1469,15 @@ static int sdma_v5_2_reset_queue(struct amdgpu_ring *ring, return -EINVAL; } + amdgpu_ring_reset_helper_begin(ring, timedout_fence); + amdgpu_amdkfd_suspend(adev, true); - r = amdgpu_sdma_reset_engine(adev, ring->me, false); + r = amdgpu_sdma_reset_engine(adev, ring->me, true); amdgpu_amdkfd_resume(adev, true); + if (r) + return r; - return r; + return amdgpu_ring_reset_helper_end(ring, timedout_fence); } static int sdma_v5_2_stop_queue(struct amdgpu_ring *ring) From 2fa4260b1be4c4cc2a09e6bc37479e9eeb9c02fe Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 15 Jul 2025 11:55:05 -0400 Subject: [PATCH 1604/2653] drm/amdgpu: move reset support type checks into the caller Rather than checking in the callbacks, check if the reset type is supported in the caller. Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 5 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 31 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 3 --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 ----- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 ----- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 6 ----- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 3 --- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 3 --- drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 3 --- drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 3 --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 3 --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 3 --- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 3 --- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c | 3 --- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 3 --- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 3 --- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 3 --- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 3 --- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 3 --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 3 --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 6 ----- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 3 --- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 3 --- 25 files changed, 37 insertions(+), 79 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 5cb7bf9420f70..32a08529307d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -112,6 +112,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) amdgpu_job_core_dump(adev, job); if (amdgpu_gpu_recovery && + amdgpu_ring_is_reset_type_supported(ring, AMDGPU_RESET_TYPE_SOFT_RESET) && amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { dev_err(adev->dev, "ring %s timeout, but soft recovered\n", s_job->sched->name); @@ -131,7 +132,9 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) /* attempt a per ring reset */ if (unlikely(adev->debug_disable_gpu_ring_reset)) { dev_err(adev->dev, "Ring reset disabled by debug mask\n"); - } else if (amdgpu_gpu_recovery && ring->funcs->reset) { + } else if (amdgpu_gpu_recovery && + amdgpu_ring_is_reset_type_supported(ring, AMDGPU_RESET_TYPE_PER_QUEUE) && + ring->funcs->reset) { dev_err(adev->dev, "Starting %s ring reset\n", s_job->sched->name); r = amdgpu_ring_reset(ring, job->vmid, &job->hw_fence); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index a910a1c9d536c..f26002b25de4f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -824,3 +824,34 @@ int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring, drm_sched_wqueue_start(&ring->sched); return 0; } + +bool amdgpu_ring_is_reset_type_supported(struct amdgpu_ring *ring, + u32 reset_type) +{ + switch (ring->funcs->type) { + case AMDGPU_RING_TYPE_GFX: + if (ring->adev->gfx.gfx_supported_reset & reset_type) + return true; + break; + case AMDGPU_RING_TYPE_COMPUTE: + if (ring->adev->gfx.compute_supported_reset & reset_type) + return true; + break; + case AMDGPU_RING_TYPE_SDMA: + if (ring->adev->sdma.supported_reset & reset_type) + return true; + break; + case AMDGPU_RING_TYPE_VCN_DEC: + case AMDGPU_RING_TYPE_VCN_ENC: + if (ring->adev->vcn.supported_reset & reset_type) + return true; + break; + case AMDGPU_RING_TYPE_VCN_JPEG: + if (ring->adev->jpeg.supported_reset & reset_type) + return true; + break; + default: + break; + } + return false; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 309e7bb6001bd..7670f5d82b9e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -568,4 +568,6 @@ void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring, struct amdgpu_fence *guilty_fence); int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring, struct amdgpu_fence *guilty_fence); +bool amdgpu_ring_is_reset_type_supported(struct amdgpu_ring *ring, + u32 reset_type); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index d799bc74936c0..f1f67521c29ca 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -1522,9 +1522,6 @@ int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring, { struct amdgpu_device *adev = ring->adev; - if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - if (adev->vcn.inst[ring->me].using_unified_queue) return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index c9cb64260cd1b..018346c6217a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -9629,9 +9629,6 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, u64 addr; int r; - if (!(adev->gfx.gfx_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; @@ -9697,9 +9694,6 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, unsigned long flags; int i, r; - if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 63e4f5b57c059..7780fb6118674 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6823,9 +6823,6 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, struct amdgpu_device *adev = ring->adev; int r; - if (!(adev->gfx.gfx_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); @@ -6989,9 +6986,6 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, struct amdgpu_device *adev = ring->adev; int r = 0; - if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 97bd15e59bb87..456aec15ada3a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -5324,9 +5324,6 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, struct amdgpu_device *adev = ring->adev; int r; - if (!(adev->gfx.gfx_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); @@ -5442,9 +5439,6 @@ static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, struct amdgpu_device *adev = ring->adev; int r; - if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index dea25030d57a9..de4a2f4158dbd 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -7315,9 +7315,6 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring, unsigned long flags; int i, r; - if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 6abb88cbfd6f6..50fe23a14c84c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -3729,9 +3729,6 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, unsigned long flags; int r; - if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c index b93d6af8f6e54..58239c405fda5 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c @@ -773,9 +773,6 @@ static int jpeg_v2_0_ring_reset(struct amdgpu_ring *ring, { int r; - if (!(ring->adev->jpeg.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = jpeg_v2_0_stop(ring->adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c index b6d5ba0bdc143..3e2c389242dbe 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c @@ -650,9 +650,6 @@ static int jpeg_v2_5_ring_reset(struct amdgpu_ring *ring, unsigned int vmid, struct amdgpu_fence *timedout_fence) { - if (!(ring->adev->jpeg.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - amdgpu_ring_reset_helper_begin(ring, timedout_fence); jpeg_v2_5_stop_inst(ring->adev, ring->me); jpeg_v2_5_start_inst(ring->adev, ring->me); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c index a229d7eb900c9..a44eb2667664b 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c @@ -564,9 +564,6 @@ static int jpeg_v3_0_ring_reset(struct amdgpu_ring *ring, { int r; - if (!(ring->adev->jpeg.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = jpeg_v3_0_stop(ring->adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c index f3a9073b8b243..da3ee69f1a3ba 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c @@ -729,9 +729,6 @@ static int jpeg_v4_0_ring_reset(struct amdgpu_ring *ring, { int r; - if (!(ring->adev->jpeg.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = jpeg_v4_0_stop(ring->adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c index 1892c278ea3c4..481d1a2dbe5aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c @@ -774,9 +774,6 @@ static int jpeg_v4_0_5_ring_reset(struct amdgpu_ring *ring, { int r; - if (!(ring->adev->jpeg.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = jpeg_v4_0_5_stop(ring->adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c index 0b4de0c6476ae..e0a71909252be 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c @@ -650,9 +650,6 @@ static int jpeg_v5_0_0_ring_reset(struct amdgpu_ring *ring, { int r; - if (!(ring->adev->jpeg.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = jpeg_v5_0_0_stop(ring->adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c index e622db1f818bf..54523dc1f7026 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c @@ -836,9 +836,6 @@ static int jpeg_v5_0_1_ring_reset(struct amdgpu_ring *ring, unsigned int vmid, struct amdgpu_fence *timedout_fence) { - if (amdgpu_sriov_vf(ring->adev)) - return -EOPNOTSUPP; - amdgpu_ring_reset_helper_begin(ring, timedout_fence); jpeg_v5_0_1_core_stall_reset(ring); jpeg_v5_0_1_init_jrbc(ring); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index 20fad2525969b..36b1ca73c2ed3 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1664,9 +1664,6 @@ static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring, u32 id = ring->me; int r; - if (!(adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - amdgpu_amdkfd_suspend(adev, true); r = amdgpu_sdma_reset_engine(adev, id, false); amdgpu_amdkfd_resume(adev, true); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index d8c19601dd2e6..7dc67a22a7a01 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1547,9 +1547,6 @@ static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring, struct amdgpu_device *adev = ring->adev; int r; - if (!(adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - if (ring->me >= adev->sdma.num_instances) { dev_err(adev->dev, "sdma instance not found\n"); return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 5d56029e88a62..3bd44c24f692d 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1461,9 +1461,6 @@ static int sdma_v5_2_reset_queue(struct amdgpu_ring *ring, struct amdgpu_device *adev = ring->adev; int r; - if (!(adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - if (ring->me >= adev->sdma.num_instances) { dev_err(adev->dev, "sdma instance not found\n"); return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index d92a71c3f2f78..e9f9e44f75032 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1578,9 +1578,6 @@ static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring, struct amdgpu_device *adev = ring->adev; int r; - if (!(adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - if (ring->me >= adev->sdma.num_instances) { dev_err(adev->dev, "sdma instance not found\n"); return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index bfebdc0c3c615..5d0f6f8d506fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -809,9 +809,6 @@ static int sdma_v7_0_reset_queue(struct amdgpu_ring *ring, struct amdgpu_device *adev = ring->adev; int r; - if (!(adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - if (ring->me >= adev->sdma.num_instances) { dev_err(adev->dev, "sdma instance not found\n"); return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index bf7d8c2e3d50a..e9f9cb1690348 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -1982,9 +1982,6 @@ static int vcn_v4_0_ring_reset(struct amdgpu_ring *ring, struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; int r; - if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = vcn_v4_0_stop(vinst); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 6c4523d000532..b904afc358ae2 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -1608,12 +1608,6 @@ static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, struct amdgpu_device *adev = ring->adev; struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; - if (amdgpu_sriov_vf(ring->adev)) - return -EOPNOTSUPP; - - if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - amdgpu_ring_reset_helper_begin(ring, timedout_fence); vcn_inst = GET_INST(VCN, ring->me); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index 5ab607962e799..ed57e6431d4b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -1480,9 +1480,6 @@ static int vcn_v4_0_5_ring_reset(struct amdgpu_ring *ring, struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; int r; - if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = vcn_v4_0_5_stop(vinst); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index 1b60aacbe9bc5..f9dbd2757d836 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -1207,9 +1207,6 @@ static int vcn_v5_0_0_ring_reset(struct amdgpu_ring *ring, struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; int r; - if (!(adev->vcn.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)) - return -EOPNOTSUPP; - amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = vcn_v5_0_0_stop(vinst); if (r) From d25520611e882a7ec8020f523c95a29ec8e844a3 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Tue, 15 Jul 2025 16:24:20 -0500 Subject: [PATCH 1605/2653] drm/amd: Use drm_*() macros instead of DRM_*() for amdgpu_cs Some of the IOCTL messages can be called for different GPUs and it might not be obvious which one called them from a problem. Using the drm_*() macros the correct device will be shown in the messages. Reviewed-by: Alex Deucher Link: https://lore.kernel.org/r/20250715212420.2254925-1-superm1@kernel.org Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index ad143e485ccfb..e6488927909c5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -406,7 +406,7 @@ static int amdgpu_cs_p2_ib(struct amdgpu_cs_parser *p, chunk_ib->ib_bytes : 0, AMDGPU_IB_POOL_DELAYED, ib); if (r) { - DRM_ERROR("Failed to get ib !\n"); + drm_err(adev_to_drm(p->adev), "Failed to get ib !\n"); return r; } @@ -477,7 +477,7 @@ static int amdgpu_syncobj_lookup_and_add(struct amdgpu_cs_parser *p, r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence); if (r) { - DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n", + drm_err(adev_to_drm(p->adev), "syncobj %u failed to find fence @ %llu (%d)!\n", handle, point, r); return r; } @@ -927,7 +927,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, sizeof(struct page *), GFP_KERNEL); if (!e->user_pages) { - DRM_ERROR("kvmalloc_array failure\n"); + drm_err(adev_to_drm(p->adev), "kvmalloc_array failure\n"); r = -ENOMEM; goto out_free_user_pages; } @@ -1097,7 +1097,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, r = amdgpu_vm_validate(p->adev, &fpriv->vm, NULL, amdgpu_cs_bo_validate, p); if (r) { - DRM_ERROR("amdgpu_vm_validate() failed.\n"); + drm_err(adev_to_drm(p->adev), "amdgpu_vm_validate() failed.\n"); goto out_free_user_pages; } @@ -1188,13 +1188,13 @@ static int amdgpu_cs_patch_ibs(struct amdgpu_cs_parser *p, va_start = ib->gpu_addr & AMDGPU_GMC_HOLE_MASK; r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m); if (r) { - DRM_ERROR("IB va_start is invalid\n"); + drm_err(adev_to_drm(p->adev), "IB va_start is invalid\n"); return r; } if ((va_start + ib->length_dw * 4) > (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) { - DRM_ERROR("IB va_start+ib_bytes is invalid\n"); + drm_err(adev_to_drm(p->adev), "IB va_start+ib_bytes is invalid\n"); return -EINVAL; } @@ -1362,7 +1362,7 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) r = amdgpu_ctx_wait_prev_fence(p->ctx, p->entities[p->gang_leader_idx]); if (r) { if (r != -ERESTARTSYS) - DRM_ERROR("amdgpu_ctx_wait_prev_fence failed.\n"); + drm_err(adev_to_drm(p->adev), "amdgpu_ctx_wait_prev_fence failed.\n"); return r; } @@ -1602,7 +1602,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) r = amdgpu_cs_parser_init(&parser, adev, filp, data); if (r) { - DRM_ERROR_RATELIMITED("Failed to initialize parser %d!\n", r); + drm_err_ratelimited(dev, "Failed to initialize parser %d!\n", r); return r; } @@ -1617,9 +1617,9 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) r = amdgpu_cs_parser_bos(&parser, data); if (r) { if (r == -ENOMEM) - DRM_ERROR("Not enough memory for command submission!\n"); + drm_err(dev, "Not enough memory for command submission!\n"); else if (r != -ERESTARTSYS && r != -EAGAIN) - DRM_DEBUG("Failed to process the buffer list %d!\n", r); + drm_dbg(dev, "Failed to process the buffer list %d!\n", r); goto error_fini; } From 08725e6aa544d060f64ff964d0cb56689ca56f25 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 7 Aug 2025 16:34:22 +0800 Subject: [PATCH 1606/2653] drm/amdkcl: test whether drm_err_ratelimited() exist It's caused by dfc4b4c439b22da891b7e092e7be53bc62f47c5a "drm/amd: Use drm_*() macros instead of DRM_*() for amdgpu_cs" Signed-off-by: Yang Su Reviewed-by: Chengjun Yao --- include/kcl/kcl_drm_print.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index f650bc4988a84..5a270ea5fafdb 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -218,4 +218,8 @@ enum drm_debug_category { __drm_printk((drm), info, _once, fmt, ##__VA_ARGS__) #endif +#ifndef drm_err_ratelimited +#define drm_err_ratelimited(drm, fmt, ...) \ + __drm_printk((drm), err, _ratelimited, "*ERROR* " fmt, ##__VA_ARGS__) +#endif #endif From 289b0dfdd0c016d6c83cf66f33c54b1f58b1aa58 Mon Sep 17 00:00:00 2001 From: YuanShang Date: Wed, 23 Jul 2025 16:44:49 +0800 Subject: [PATCH 1607/2653] drm/amdgpu: Retain job->vm in amdgpu_job_prepare_job The field job->vm is used in function amdgpu_job_run to get the page table re-generation counter and decide whether the job should be skipped. Specifically, function amdgpu_vm_generation checks if the VM is valid for this job to use. For instance, if a gfx job depends on a cancelled sdma job from entity vm->delayed, then the gfx job should be skipped. Signed-off-by: YuanShang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 32a08529307d5..172620880cada 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -366,13 +366,6 @@ amdgpu_job_prepare_job(struct drm_sched_job *sched_job, dev_err(ring->adev->dev, "Error getting VM ID (%d)\n", r); goto error; } - /* - * The VM structure might be released after the VMID is - * assigned, we had multiple problems with people trying to use - * the VM pointer so better set it to NULL. - */ - if (!fence) - job->vm = NULL; return fence; } From f8773c88846c51ded487131eb99500044c6254b6 Mon Sep 17 00:00:00 2001 From: Meng Li Date: Fri, 9 May 2025 13:44:24 +0800 Subject: [PATCH 1608/2653] drm/amd/amdgpu: Release xcp drm memory after unplug Add a new API amdgpu_xcp_drm_dev_free(). After unplug xcp device, need to release xcp drm memory etc. Co-developed-by: Jiang Liu Signed-off-by: Jiang Liu Signed-off-by: Meng Li Acked-by: Alex Deucher Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 1 + drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c | 55 +++++++++++++++++---- drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.h | 1 + 3 files changed, 48 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c index 2017c321cdcb2..3f196ff6b066c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c @@ -406,6 +406,7 @@ void amdgpu_xcp_dev_unplug(struct amdgpu_device *adev) p_ddev->primary->dev = adev->xcp_mgr->xcp[i].pdev; p_ddev->driver = adev->xcp_mgr->xcp[i].driver; p_ddev->vma_offset_manager = adev->xcp_mgr->xcp[i].vma_offset_manager; + amdgpu_xcp_drm_dev_free(p_ddev); } } diff --git a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c index 9281db9ae668a..90ba91f6c9620 100644 --- a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c +++ b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c @@ -50,18 +50,29 @@ static const struct drm_driver amdgpu_xcp_driver = { static int8_t pdev_num; static struct xcp_device *xcp_dev[MAX_XCP_PLATFORM_DEVICE]; +static DEFINE_MUTEX(xcp_mutex); int amdgpu_xcp_drm_dev_alloc(struct drm_device **ddev) { struct platform_device *pdev; struct xcp_device *pxcp_dev; char dev_name[20]; - int ret; + int ret, i; + + guard(mutex)(&xcp_mutex); if (pdev_num >= MAX_XCP_PLATFORM_DEVICE) return -ENODEV; - snprintf(dev_name, sizeof(dev_name), "amdgpu_xcp_%d", pdev_num); + for (i = 0; i < MAX_XCP_PLATFORM_DEVICE; i++) { + if (!xcp_dev[i]) + break; + } + + if (i >= MAX_XCP_PLATFORM_DEVICE) + return -ENODEV; + + snprintf(dev_name, sizeof(dev_name), "amdgpu_xcp_%d", i); pdev = platform_device_register_simple(dev_name, -1, NULL, 0); if (IS_ERR(pdev)) return PTR_ERR(pdev); @@ -77,8 +88,8 @@ int amdgpu_xcp_drm_dev_alloc(struct drm_device **ddev) goto out_devres; } - xcp_dev[pdev_num] = pxcp_dev; - xcp_dev[pdev_num]->pdev = pdev; + xcp_dev[i] = pxcp_dev; + xcp_dev[i]->pdev = pdev; *ddev = &pxcp_dev->drm; pdev_num++; @@ -93,10 +104,10 @@ int amdgpu_xcp_drm_dev_alloc(struct drm_device **ddev) } EXPORT_SYMBOL(amdgpu_xcp_drm_dev_alloc); -void amdgpu_xcp_drv_release(void) +static void free_xcp_dev(int8_t index) { - for (--pdev_num; pdev_num >= 0; --pdev_num) { - struct platform_device *pdev = xcp_dev[pdev_num]->pdev; + if ((index < MAX_XCP_PLATFORM_DEVICE) && (xcp_dev[index])) { + struct platform_device *pdev = xcp_dev[index]->pdev; devres_release_group(&pdev->dev, NULL); platform_device_unregister(pdev); @@ -104,9 +115,35 @@ void amdgpu_xcp_drv_release(void) drm_dev_fini(&(xcp_dev[pdev_num]->drm)); kfree(xcp_dev[pdev_num]); #endif - xcp_dev[pdev_num] = NULL; + xcp_dev[index] = NULL; + pdev_num--; + } +} + +void amdgpu_xcp_drm_dev_free(struct drm_device *ddev) +{ + int8_t i; + + guard(mutex)(&xcp_mutex); + + for (i = 0; i < MAX_XCP_PLATFORM_DEVICE; i++) { + if ((xcp_dev[i]) && (&xcp_dev[i]->drm == ddev)) { + free_xcp_dev(i); + break; + } + } +} +EXPORT_SYMBOL(amdgpu_xcp_drm_dev_free); + +void amdgpu_xcp_drv_release(void) +{ + int8_t i; + + guard(mutex)(&xcp_mutex); + + for (i = 0; pdev_num && i < MAX_XCP_PLATFORM_DEVICE; i++) { + free_xcp_dev(i); } - pdev_num = 0; } EXPORT_SYMBOL(amdgpu_xcp_drv_release); diff --git a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.h b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.h index c1c4b679bf95c..580a1602c8e36 100644 --- a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.h +++ b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.h @@ -25,5 +25,6 @@ #define _AMDGPU_XCP_DRV_H_ int amdgpu_xcp_drm_dev_alloc(struct drm_device **ddev); +void amdgpu_xcp_drm_dev_free(struct drm_device *ddev); void amdgpu_xcp_drv_release(void); #endif /* _AMDGPU_XCP_DRV_H_ */ From 3b126c1b80e47c570a00f69990e5c662e3098b62 Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Thu, 17 Jul 2025 11:30:52 +0530 Subject: [PATCH 1609/2653] drm/amdgpu/vcn: Add regdump helper functions Add generic helper functions for vcn devcoredump support which can be re-used for all vcn versions. Signed-off-by: Sathishkumar S Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 87 +++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 8 +++ 2 files changed, 95 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index f1f67521c29ca..b497a67141384 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -92,6 +92,7 @@ MODULE_FIRMWARE(FIRMWARE_VCN5_0_0); MODULE_FIRMWARE(FIRMWARE_VCN5_0_1); static void amdgpu_vcn_idle_work_handler(struct work_struct *work); +static void amdgpu_vcn_reg_dump_fini(struct amdgpu_device *adev); int amdgpu_vcn_early_init(struct amdgpu_device *adev, int i) { @@ -285,6 +286,10 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int i) amdgpu_ucode_release(&adev->vcn.inst[0].fw); adev->vcn.inst[i].fw = NULL; } + + if (adev->vcn.reg_list) + amdgpu_vcn_reg_dump_fini(adev); + mutex_destroy(&adev->vcn.inst[i].vcn_pg_lock); mutex_destroy(&adev->vcn.inst[i].vcn1_jpeg1_workaround); @@ -1527,3 +1532,85 @@ int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring, return amdgpu_vcn_reset_engine(adev, ring->me); } + +int amdgpu_vcn_reg_dump_init(struct amdgpu_device *adev, + const struct amdgpu_hwip_reg_entry *reg, u32 count) +{ + adev->vcn.ip_dump = kcalloc(adev->vcn.num_vcn_inst * count, + sizeof(uint32_t), GFP_KERNEL); + if (!adev->vcn.ip_dump) + return -ENOMEM; + adev->vcn.reg_list = reg; + adev->vcn.reg_count = count; + + return 0; +} + +static void amdgpu_vcn_reg_dump_fini(struct amdgpu_device *adev) +{ + kfree(adev->vcn.ip_dump); + adev->vcn.reg_list = NULL; + adev->vcn.reg_count = 0; +} + +void amdgpu_vcn_dump_ip_state(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int i, j; + bool is_powered; + u32 inst_off; + + if (!adev->vcn.ip_dump) + return; + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) + continue; + + inst_off = i * adev->vcn.reg_count; + /* mmUVD_POWER_STATUS is always readable and is the first in reg_list */ + adev->vcn.ip_dump[inst_off] = + RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->vcn.reg_list[0], i)); + is_powered = (adev->vcn.ip_dump[inst_off] & + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF) != + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; + + if (is_powered) + for (j = 1; j < adev->vcn.reg_count; j++) + adev->vcn.ip_dump[inst_off + j] = + RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->vcn.reg_list[j], i)); + } +} + +void amdgpu_vcn_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) +{ + struct amdgpu_device *adev = ip_block->adev; + int i, j; + bool is_powered; + u32 inst_off; + + if (!adev->vcn.ip_dump) + return; + + drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) { + drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); + continue; + } + + inst_off = i * adev->vcn.reg_count; + is_powered = (adev->vcn.ip_dump[inst_off] & + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF) != + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; + + if (is_powered) { + drm_printf(p, "\nActive Instance:VCN%d\n", i); + for (j = 0; j < adev->vcn.reg_count; j++) + drm_printf(p, "%-50s \t 0x%08x\n", adev->vcn.reg_list[j].reg_name, + adev->vcn.ip_dump[inst_off + j]); + } else { + drm_printf(p, "\nInactive Instance:VCN%d\n", i); + } + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index 0bc0a94d7cf0f..b3fb1d0e43fc9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -237,6 +237,8 @@ #define AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING 2 +struct amdgpu_hwip_reg_entry; + enum amdgpu_vcn_caps { AMDGPU_VCN_RRMT_ENABLED, }; @@ -362,6 +364,8 @@ struct amdgpu_vcn { bool workload_profile_active; struct mutex workload_profile_mutex; + u32 reg_count; + const struct amdgpu_hwip_reg_entry *reg_list; }; struct amdgpu_fw_shared_rb_ptrs_struct { @@ -557,4 +561,8 @@ int vcn_set_powergating_state(struct amdgpu_ip_block *ip_block, int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring, unsigned int vmid, struct amdgpu_fence *guilty_fence); +int amdgpu_vcn_reg_dump_init(struct amdgpu_device *adev, + const struct amdgpu_hwip_reg_entry *reg, u32 count); +void amdgpu_vcn_dump_ip_state(struct amdgpu_ip_block *ip_block); +void amdgpu_vcn_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p); #endif From cfa52ff35583e9429ddbb516c6d61802351716fc Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Mon, 28 Jul 2025 19:33:50 +0800 Subject: [PATCH 1610/2653] drm/amdgpu: Fix vcn v5.0.1 poison irq call trace Why: [13014.890792] Call Trace: [13014.890793] [13014.890795] ? show_trace_log_lvl+0x1d6/0x2ea [13014.890799] ? show_trace_log_lvl+0x1d6/0x2ea [13014.890800] ? vcn_v5_0_1_hw_fini+0xe9/0x110 [amdgpu] [13014.890872] ? show_regs.part.0+0x23/0x29 [13014.890873] ? show_regs.cold+0x8/0xd [13014.890874] ? amdgpu_irq_put+0xc6/0xe0 [amdgpu] [13014.890934] ? __warn+0x8c/0x100 [13014.890936] ? amdgpu_irq_put+0xc6/0xe0 [amdgpu] [13014.890995] ? report_bug+0xa4/0xd0 [13014.890999] ? handle_bug+0x39/0x90 [13014.891001] ? exc_invalid_op+0x19/0x70 [13014.891003] ? asm_exc_invalid_op+0x1b/0x20 [13014.891005] ? amdgpu_irq_put+0xc6/0xe0 [amdgpu] [13014.891065] ? amdgpu_irq_put+0x63/0xe0 [amdgpu] [13014.891124] vcn_v5_0_1_hw_fini+0xe9/0x110 [amdgpu] [13014.891189] amdgpu_ip_block_hw_fini+0x3b/0x78 [amdgpu] [13014.891309] amdgpu_device_fini_hw+0x3c1/0x479 [amdgpu] How: Add omitted vcn poison irq get call. Signed-off-by: Stanley.Yang Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 7 +++++++ 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c index 54523dc1f7026..03ec4b741d194 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c @@ -1058,6 +1058,11 @@ static int jpeg_v5_0_1_ras_late_init(struct amdgpu_device *adev, struct ras_comm if (r) return r; + r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__JPEG, + &jpeg_v5_0_1_aca_info, NULL); + if (r) + goto late_fini; + if (amdgpu_ras_is_supported(adev, ras_block->block) && adev->jpeg.inst->ras_poison_irq.funcs) { r = amdgpu_irq_get(adev, &adev->jpeg.inst->ras_poison_irq, 0); @@ -1065,11 +1070,6 @@ static int jpeg_v5_0_1_ras_late_init(struct amdgpu_device *adev, struct ras_comm goto late_fini; } - r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__JPEG, - &jpeg_v5_0_1_aca_info, NULL); - if (r) - goto late_fini; - return 0; late_fini: diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c index d8bbb93767318..cb560d64da08c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c @@ -1608,6 +1608,13 @@ static int vcn_v5_0_1_ras_late_init(struct amdgpu_device *adev, struct ras_commo if (r) goto late_fini; + if (amdgpu_ras_is_supported(adev, ras_block->block) && + adev->vcn.inst->ras_poison_irq.funcs) { + r = amdgpu_irq_get(adev, &adev->vcn.inst->ras_poison_irq, 0); + if (r) + goto late_fini; + } + return 0; late_fini: From 5ec1859ae285d477d2f4c9695d46371e9fb27f73 Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Fri, 18 Jul 2025 00:27:50 +0530 Subject: [PATCH 1611/2653] drm/amdgpu/vcn: Register dump cleanup in VCN5 Use generic vcn devcoredump helper functions for VCN5 Signed-off-by: Sathishkumar S Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 86 ++----------------------- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.h | 5 -- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 44 +++++++++++-- 3 files changed, 44 insertions(+), 91 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index f9dbd2757d836..455f829b8bb99 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -115,21 +115,6 @@ static int vcn_v5_0_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -void vcn_v5_0_0_alloc_ip_dump(struct amdgpu_device *adev) -{ - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0); - uint32_t *ptr; - - /* Allocate memory for VCN IP Dump buffer */ - ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); - if (!ptr) { - DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); - adev->vcn.ip_dump = NULL; - } else { - adev->vcn.ip_dump = ptr; - } -} - /** * vcn_v5_0_0_sw_init - sw init for VCN block * @@ -201,7 +186,9 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block) if (!amdgpu_sriov_vf(adev)) adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; - vcn_v5_0_0_alloc_ip_dump(adev); + r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_5_0, ARRAY_SIZE(vcn_reg_list_5_0)); + if (r) + return r; r = amdgpu_vcn_sysfs_reset_mask_init(adev); if (r) @@ -251,8 +238,6 @@ static int vcn_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block) return r; } - kfree(adev->vcn.ip_dump); - return 0; } @@ -1434,67 +1419,6 @@ static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev) } } -void vcn_v5_0_0_print_ip_state(struct amdgpu_ip_block *ip_block, - struct drm_printer *p) -{ - struct amdgpu_device *adev = ip_block->adev; - int i, j; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0); - uint32_t inst_off, is_powered; - - if (!adev->vcn.ip_dump) - return; - - drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - if (adev->vcn.harvest_config & (1 << i)) { - drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); - continue; - } - - inst_off = i * reg_count; - is_powered = (adev->vcn.ip_dump[inst_off] & - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; - - if (is_powered) { - drm_printf(p, "\nActive Instance:VCN%d\n", i); - for (j = 0; j < reg_count; j++) - drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_5_0[j].reg_name, - adev->vcn.ip_dump[inst_off + j]); - } else { - drm_printf(p, "\nInactive Instance:VCN%d\n", i); - } - } -} - -void vcn_v5_0_0_dump_ip_state(struct amdgpu_ip_block *ip_block) -{ - struct amdgpu_device *adev = ip_block->adev; - int i, j; - bool is_powered; - uint32_t inst_off; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0); - - if (!adev->vcn.ip_dump) - return; - - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - if (adev->vcn.harvest_config & (1 << i)) - continue; - - inst_off = i * reg_count; - /* mmUVD_POWER_STATUS is always readable and is first element of the array */ - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS); - is_powered = (adev->vcn.ip_dump[inst_off] & - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; - - if (is_powered) - for (j = 1; j < reg_count; j++) - adev->vcn.ip_dump[inst_off + j] = - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], i)); - } -} - static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = { .name = "vcn_v5_0_0", .early_init = vcn_v5_0_0_early_init, @@ -1508,8 +1432,8 @@ static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = { .wait_for_idle = vcn_v5_0_0_wait_for_idle, .set_clockgating_state = vcn_v5_0_0_set_clockgating_state, .set_powergating_state = vcn_set_powergating_state, - .dump_ip_state = vcn_v5_0_0_dump_ip_state, - .print_ip_state = vcn_v5_0_0_print_ip_state, + .dump_ip_state = amdgpu_vcn_dump_ip_state, + .print_ip_state = amdgpu_vcn_print_ip_state, }; const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block = { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.h b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.h index b8927652bc50c..51bbccd4360ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.h +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.h @@ -32,11 +32,6 @@ #define VCN_VID_IP_ADDRESS 0x0 #define VCN_AON_IP_ADDRESS 0x30000 -void vcn_v5_0_0_alloc_ip_dump(struct amdgpu_device *adev); -void vcn_v5_0_0_print_ip_state(struct amdgpu_ip_block *ip_block, - struct drm_printer *p); -void vcn_v5_0_0_dump_ip_state(struct amdgpu_ip_block *ip_block); - extern const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block; #endif /* __VCN_V5_0_0_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c index cb560d64da08c..553ffad0888a9 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c @@ -40,6 +40,40 @@ #include +static const struct amdgpu_hwip_reg_entry vcn_reg_list_5_0_1[] = { + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) +}; + static int vcn_v5_0_1_start_sriov(struct amdgpu_device *adev); static void vcn_v5_0_1_set_unified_ring_funcs(struct amdgpu_device *adev); static void vcn_v5_0_1_set_irq_funcs(struct amdgpu_device *adev); @@ -163,7 +197,9 @@ static int vcn_v5_0_1_sw_init(struct amdgpu_ip_block *ip_block) return r; } - vcn_v5_0_0_alloc_ip_dump(adev); + r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_5_0_1, ARRAY_SIZE(vcn_reg_list_5_0_1)); + if (r) + return r; return amdgpu_vcn_sysfs_reset_mask_init(adev); } @@ -209,8 +245,6 @@ static int vcn_v5_0_1_sw_fini(struct amdgpu_ip_block *ip_block) amdgpu_vcn_sysfs_reset_mask_fini(adev); - kfree(adev->vcn.ip_dump); - return 0; } @@ -1480,8 +1514,8 @@ static const struct amd_ip_funcs vcn_v5_0_1_ip_funcs = { .post_soft_reset = NULL, .set_clockgating_state = vcn_v5_0_1_set_clockgating_state, .set_powergating_state = vcn_set_powergating_state, - .dump_ip_state = vcn_v5_0_0_dump_ip_state, - .print_ip_state = vcn_v5_0_0_print_ip_state, + .dump_ip_state = amdgpu_vcn_dump_ip_state, + .print_ip_state = amdgpu_vcn_print_ip_state, }; const struct amdgpu_ip_block_version vcn_v5_0_1_ip_block = { From eff3fb89e08cfb960667a27ab3acbeee8fe7b2bf Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Fri, 18 Jul 2025 12:18:30 +0530 Subject: [PATCH 1612/2653] drm/amdgpu/vcn: Register dump cleanup in VCN4_0_0 Use generic vcn devcoredump helper functions for VCN4_0_0 Signed-off-by: Sathishkumar S Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 80 ++------------------------- 1 file changed, 5 insertions(+), 75 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index e9f9cb1690348..1785786a72f8e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -183,8 +183,6 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block) struct amdgpu_ring *ring; struct amdgpu_device *adev = ip_block->adev; int i, r; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0); - uint32_t *ptr; for (i = 0; i < adev->vcn.num_vcn_inst; i++) { if (adev->vcn.harvest_config & (1 << i)) @@ -255,14 +253,9 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block) if (r) return r; - /* Allocate memory for VCN IP Dump buffer */ - ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); - if (!ptr) { - DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); - adev->vcn.ip_dump = NULL; - } else { - adev->vcn.ip_dump = ptr; - } + r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_4_0, ARRAY_SIZE(vcn_reg_list_4_0)); + if (r) + return r; r = amdgpu_vcn_sysfs_reset_mask_init(adev); if (r) @@ -315,8 +308,6 @@ static int vcn_v4_0_sw_fini(struct amdgpu_ip_block *ip_block) return r; } - kfree(adev->vcn.ip_dump); - return 0; } @@ -2252,67 +2243,6 @@ static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev) } } -static void vcn_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) -{ - struct amdgpu_device *adev = ip_block->adev; - int i, j; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0); - uint32_t inst_off, is_powered; - - if (!adev->vcn.ip_dump) - return; - - drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - if (adev->vcn.harvest_config & (1 << i)) { - drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); - continue; - } - - inst_off = i * reg_count; - is_powered = (adev->vcn.ip_dump[inst_off] & - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; - - if (is_powered) { - drm_printf(p, "\nActive Instance:VCN%d\n", i); - for (j = 0; j < reg_count; j++) - drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0[j].reg_name, - adev->vcn.ip_dump[inst_off + j]); - } else { - drm_printf(p, "\nInactive Instance:VCN%d\n", i); - } - } -} - -static void vcn_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block) -{ - struct amdgpu_device *adev = ip_block->adev; - int i, j; - bool is_powered; - uint32_t inst_off; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0); - - if (!adev->vcn.ip_dump) - return; - - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - if (adev->vcn.harvest_config & (1 << i)) - continue; - - inst_off = i * reg_count; - /* mmUVD_POWER_STATUS is always readable and is first element of the array */ - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS); - is_powered = (adev->vcn.ip_dump[inst_off] & - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; - - if (is_powered) - for (j = 1; j < reg_count; j++) - adev->vcn.ip_dump[inst_off + j] = - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j], - i)); - } -} - static const struct amd_ip_funcs vcn_v4_0_ip_funcs = { .name = "vcn_v4_0", .early_init = vcn_v4_0_early_init, @@ -2326,8 +2256,8 @@ static const struct amd_ip_funcs vcn_v4_0_ip_funcs = { .wait_for_idle = vcn_v4_0_wait_for_idle, .set_clockgating_state = vcn_v4_0_set_clockgating_state, .set_powergating_state = vcn_set_powergating_state, - .dump_ip_state = vcn_v4_0_dump_ip_state, - .print_ip_state = vcn_v4_0_print_ip_state, + .dump_ip_state = amdgpu_vcn_dump_ip_state, + .print_ip_state = amdgpu_vcn_print_ip_state, }; const struct amdgpu_ip_block_version vcn_v4_0_ip_block = { From 44d0e62024a7c2cc58d6d0c8c57b01e9d469a0e6 Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Fri, 18 Jul 2025 12:38:49 +0530 Subject: [PATCH 1613/2653] drm/amdgpu/vcn: Register dump cleanup in VCN4_0_5 Use generic vcn devcoredump helper functions for VCN4_0_5 Signed-off-by: Sathishkumar S Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 80 ++----------------------- 1 file changed, 5 insertions(+), 75 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index ed57e6431d4b5..f785467370d9a 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -147,9 +147,6 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block) struct amdgpu_ring *ring; struct amdgpu_device *adev = ip_block->adev; int i, r; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); - uint32_t *ptr; - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { volatile struct amdgpu_vcn4_fw_shared *fw_shared; @@ -233,15 +230,9 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block) return r; } - /* Allocate memory for VCN IP Dump buffer */ - ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); - if (!ptr) { - DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); - adev->vcn.ip_dump = NULL; - } else { - adev->vcn.ip_dump = ptr; - } - return 0; + r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_4_0_5, ARRAY_SIZE(vcn_reg_list_4_0_5)); + + return r; } /** @@ -1710,67 +1701,6 @@ static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev) } } -static void vcn_v4_0_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) -{ - struct amdgpu_device *adev = ip_block->adev; - int i, j; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); - uint32_t inst_off, is_powered; - - if (!adev->vcn.ip_dump) - return; - - drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - if (adev->vcn.harvest_config & (1 << i)) { - drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); - continue; - } - - inst_off = i * reg_count; - is_powered = (adev->vcn.ip_dump[inst_off] & - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; - - if (is_powered) { - drm_printf(p, "\nActive Instance:VCN%d\n", i); - for (j = 0; j < reg_count; j++) - drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_5[j].reg_name, - adev->vcn.ip_dump[inst_off + j]); - } else { - drm_printf(p, "\nInactive Instance:VCN%d\n", i); - } - } -} - -static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block) -{ - struct amdgpu_device *adev = ip_block->adev; - int i, j; - bool is_powered; - uint32_t inst_off; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); - - if (!adev->vcn.ip_dump) - return; - - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - if (adev->vcn.harvest_config & (1 << i)) - continue; - - inst_off = i * reg_count; - /* mmUVD_POWER_STATUS is always readable and is first element of the array */ - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS); - is_powered = (adev->vcn.ip_dump[inst_off] & - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; - - if (is_powered) - for (j = 1; j < reg_count; j++) - adev->vcn.ip_dump[inst_off + j] = - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j], - i)); - } -} - static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = { .name = "vcn_v4_0_5", .early_init = vcn_v4_0_5_early_init, @@ -1784,8 +1714,8 @@ static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = { .wait_for_idle = vcn_v4_0_5_wait_for_idle, .set_clockgating_state = vcn_v4_0_5_set_clockgating_state, .set_powergating_state = vcn_set_powergating_state, - .dump_ip_state = vcn_v4_0_5_dump_ip_state, - .print_ip_state = vcn_v4_0_5_print_ip_state, + .dump_ip_state = amdgpu_vcn_dump_ip_state, + .print_ip_state = amdgpu_vcn_print_ip_state, }; const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = { From f8b281265f98fcf598dd52c115e44f8850df87ce Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Fri, 18 Jul 2025 12:57:04 +0530 Subject: [PATCH 1614/2653] drm/amdgpu/vcn: Register dump cleanup in VCN4_0_3 Use generic vcn devcoredump helper functions for VCN4_0_3 Signed-off-by: Sathishkumar S Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 79 ++----------------------- 1 file changed, 5 insertions(+), 74 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index b904afc358ae2..c51dc401226a2 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -160,8 +160,6 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int i, r, vcn_inst; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); - uint32_t *ptr; /* VCN DEC TRAP */ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, @@ -231,14 +229,9 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) } } - /* Allocate memory for VCN IP Dump buffer */ - ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); - if (!ptr) { - DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); - adev->vcn.ip_dump = NULL; - } else { - adev->vcn.ip_dump = ptr; - } + r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_4_0_3, ARRAY_SIZE(vcn_reg_list_4_0_3)); + if (r) + return r; r = amdgpu_vcn_sysfs_reset_mask_init(adev); if (r) @@ -1877,68 +1870,6 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) adev->vcn.inst->ras_poison_irq.funcs = &vcn_v4_0_3_ras_irq_funcs; } -static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) -{ - struct amdgpu_device *adev = ip_block->adev; - int i, j; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); - uint32_t inst_off, is_powered; - - if (!adev->vcn.ip_dump) - return; - - drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - if (adev->vcn.harvest_config & (1 << i)) { - drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); - continue; - } - - inst_off = i * reg_count; - is_powered = (adev->vcn.ip_dump[inst_off] & - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; - - if (is_powered) { - drm_printf(p, "\nActive Instance:VCN%d\n", i); - for (j = 0; j < reg_count; j++) - drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_3[j].reg_name, - adev->vcn.ip_dump[inst_off + j]); - } else { - drm_printf(p, "\nInactive Instance:VCN%d\n", i); - } - } -} - -static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block) -{ - struct amdgpu_device *adev = ip_block->adev; - int i, j; - bool is_powered; - uint32_t inst_off, inst_id; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); - - if (!adev->vcn.ip_dump) - return; - - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - if (adev->vcn.harvest_config & (1 << i)) - continue; - - inst_id = GET_INST(VCN, i); - inst_off = i * reg_count; - /* mmUVD_POWER_STATUS is always readable and is first element of the array */ - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS); - is_powered = (adev->vcn.ip_dump[inst_off] & - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; - - if (is_powered) - for (j = 1; j < reg_count; j++) - adev->vcn.ip_dump[inst_off + j] = - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j], - inst_id)); - } -} - static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = { .name = "vcn_v4_0_3", .early_init = vcn_v4_0_3_early_init, @@ -1952,8 +1883,8 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = { .wait_for_idle = vcn_v4_0_3_wait_for_idle, .set_clockgating_state = vcn_v4_0_3_set_clockgating_state, .set_powergating_state = vcn_set_powergating_state, - .dump_ip_state = vcn_v4_0_3_dump_ip_state, - .print_ip_state = vcn_v4_0_3_print_ip_state, + .dump_ip_state = amdgpu_vcn_dump_ip_state, + .print_ip_state = amdgpu_vcn_print_ip_state, }; const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = { From c75b0a2e1c91dbcc71b8c4e100391903ac24fbe7 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 18 Jul 2025 15:52:04 -0400 Subject: [PATCH 1615/2653] drm/amdgpu: update mmhub 3.0.1 client id mappings Update the client id mapping so the correct clients get printed when there is a mmhub page fault. Reviewed-by: David (Ming Qiang) Wu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c | 57 +++++++++++++---------- 1 file changed, 32 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c index 134c4ec108878..910337dc28d10 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c @@ -36,40 +36,47 @@ static const char *mmhub_client_ids_v3_0_1[][2] = { [0][0] = "VMC", + [1][0] = "ISPXT", + [2][0] = "ISPIXT", [4][0] = "DCEDMC", [5][0] = "DCEVGA", [6][0] = "MP0", [7][0] = "MP1", - [8][0] = "MPIO", - [16][0] = "HDP", - [17][0] = "LSDMA", - [18][0] = "JPEG", - [19][0] = "VCNU0", - [21][0] = "VSCH", - [22][0] = "VCNU1", - [23][0] = "VCN1", - [32+20][0] = "VCN0", - [2][1] = "DBGUNBIO", + [8][0] = "MPM", + [12][0] = "ISPTNR", + [14][0] = "ISPCRD0", + [15][0] = "ISPCRD1", + [16][0] = "ISPCRD2", + [22][0] = "HDP", + [23][0] = "LSDMA", + [24][0] = "JPEG", + [27][0] = "VSCH", + [28][0] = "VCNU", + [29][0] = "VCN", + [1][1] = "ISPXT", + [2][1] = "ISPIXT", [3][1] = "DCEDWB", [4][1] = "DCEDMC", [5][1] = "DCEVGA", [6][1] = "MP0", [7][1] = "MP1", - [8][1] = "MPIO", - [10][1] = "DBGU0", - [11][1] = "DBGU1", - [12][1] = "DBGU2", - [13][1] = "DBGU3", - [14][1] = "XDP", - [15][1] = "OSSSYS", - [16][1] = "HDP", - [17][1] = "LSDMA", - [18][1] = "JPEG", - [19][1] = "VCNU0", - [20][1] = "VCN0", - [21][1] = "VSCH", - [22][1] = "VCNU1", - [23][1] = "VCN1", + [8][1] = "MPM", + [10][1] = "ISPMWR0", + [11][1] = "ISPMWR1", + [12][1] = "ISPTNR", + [13][1] = "ISPSWR", + [14][1] = "ISPCWR0", + [15][1] = "ISPCWR1", + [16][1] = "ISPCWR2", + [17][1] = "ISPCWR3", + [18][1] = "XDP", + [21][1] = "OSSSYS", + [22][1] = "HDP", + [23][1] = "LSDMA", + [24][1] = "JPEG", + [27][1] = "VSCH", + [28][1] = "VCNU", + [29][1] = "VCN", }; static uint32_t mmhub_v3_0_1_get_invalidate_req(unsigned int vmid, From 588febfb21a61eb703c4de04f073517611a6020b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 18 Jul 2025 15:53:21 -0400 Subject: [PATCH 1616/2653] drm/amdgpu: update mmhub 3.3 client id mappings Update the client id mapping so the correct clients get printed when there is a mmhub page fault. v2: fix typos spotted by David Wu. v3: fix additional typo spotted by David. Reviewed-by: David (Ming Qiang) Wu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c | 105 +++++++++++++++++++++++- 1 file changed, 104 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c index bc3d6c2fc87a4..f6fc9778bc305 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c @@ -40,30 +40,129 @@ static const char *mmhub_client_ids_v3_3[][2] = { [0][0] = "VMC", + [1][0] = "ISPXT", + [2][0] = "ISPIXT", [4][0] = "DCEDMC", [6][0] = "MP0", [7][0] = "MP1", [8][0] = "MPM", + [9][0] = "ISPPDPRD", + [10][0] = "ISPCSTATRD", + [11][0] = "ISPBYRPRD", + [12][0] = "ISPRGBPRD", + [13][0] = "ISPMCFPRD", + [14][0] = "ISPMCFPRD1", + [15][0] = "ISPYUVPRD", + [16][0] = "ISPMCSCRD", + [17][0] = "ISPGDCRD", + [18][0] = "ISPLMERD", + [22][0] = "ISPXT1", + [23][0] = "ISPIXT1", [24][0] = "HDP", [25][0] = "LSDMA", [26][0] = "JPEG", [27][0] = "VPE", + [28][0] = "VSCH", [29][0] = "VCNU", [30][0] = "VCN", + [1][1] = "ISPXT", + [2][1] = "ISPIXT", [3][1] = "DCEDWB", [4][1] = "DCEDMC", + [5][1] = "ISPCSISWR", [6][1] = "MP0", [7][1] = "MP1", [8][1] = "MPM", + [9][1] = "ISPPDPWR", + [10][1] = "ISPCSTATWR", + [11][1] = "ISPBYRPWR", + [12][1] = "ISPRGBPWR", + [13][1] = "ISPMCFPWR", + [14][1] = "ISPMWR0", + [15][1] = "ISPYUVPWR", + [16][1] = "ISPMCSCWR", + [17][1] = "ISPGDCWR", + [18][1] = "ISPLMEWR", + [20][1] = "ISPMWR2", [21][1] = "OSSSYS", + [22][1] = "ISPXT1", + [23][1] = "ISPIXT1", [24][1] = "HDP", [25][1] = "LSDMA", [26][1] = "JPEG", [27][1] = "VPE", + [28][1] = "VSCH", [29][1] = "VCNU", [30][1] = "VCN", }; +static const char *mmhub_client_ids_v3_3_1[][2] = { + [0][0] = "VMC", + [4][0] = "DCEDMC", + [6][0] = "MP0", + [7][0] = "MP1", + [8][0] = "MPM", + [24][0] = "HDP", + [25][0] = "LSDMA", + [26][0] = "JPEG0", + [27][0] = "VPE0", + [28][0] = "VSCH", + [29][0] = "VCNU0", + [30][0] = "VCN0", + [32+1][0] = "ISPXT", + [32+2][0] = "ISPIXT", + [32+9][0] = "ISPPDPRD", + [32+10][0] = "ISPCSTATRD", + [32+11][0] = "ISPBYRPRD", + [32+12][0] = "ISPRGBPRD", + [32+13][0] = "ISPMCFPRD", + [32+14][0] = "ISPMCFPRD1", + [32+15][0] = "ISPYUVPRD", + [32+16][0] = "ISPMCSCRD", + [32+17][0] = "ISPGDCRD", + [32+18][0] = "ISPLMERD", + [32+22][0] = "ISPXT1", + [32+23][0] = "ISPIXT1", + [32+26][0] = "JPEG1", + [32+27][0] = "VPE1", + [32+29][0] = "VCNU1", + [32+30][0] = "VCN1", + [3][1] = "DCEDWB", + [4][1] = "DCEDMC", + [6][1] = "MP0", + [7][1] = "MP1", + [8][1] = "MPM", + [21][1] = "OSSSYS", + [24][1] = "HDP", + [25][1] = "LSDMA", + [26][1] = "JPEG0", + [27][1] = "VPE0", + [28][1] = "VSCH", + [29][1] = "VCNU0", + [30][1] = "VCN0", + [32+1][1] = "ISPXT", + [32+2][1] = "ISPIXT", + [32+5][1] = "ISPCSISWR", + [32+9][1] = "ISPPDPWR", + [32+10][1] = "ISPCSTATWR", + [32+11][1] = "ISPBYRPWR", + [32+12][1] = "ISPRGBPWR", + [32+13][1] = "ISPMCFPWR", + [32+14][1] = "ISPMWR0", + [32+15][1] = "ISPYUVPWR", + [32+16][1] = "ISPMCSCWR", + [32+17][1] = "ISPGDCWR", + [32+18][1] = "ISPLMEWR", + [32+19][1] = "ISPMWR1", + [32+20][1] = "ISPMWR2", + [32+22][1] = "ISPXT1", + [32+23][1] = "ISPIXT1", + [32+26][1] = "JPEG1", + [32+27][1] = "VPE1", + [32+29][1] = "VCNU1", + [32+30][1] = "VCN1", +}; + static uint32_t mmhub_v3_3_get_invalidate_req(unsigned int vmid, uint32_t flush_type) { @@ -102,12 +201,16 @@ mmhub_v3_3_print_l2_protection_fault_status(struct amdgpu_device *adev, switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { case IP_VERSION(3, 3, 0): - case IP_VERSION(3, 3, 1): case IP_VERSION(3, 3, 2): mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_3) ? mmhub_client_ids_v3_3[cid][rw] : cid == 0x140 ? "UMSCH" : NULL; break; + case IP_VERSION(3, 3, 1): + mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_3_1) ? + mmhub_client_ids_v3_3_1[cid][rw] : + cid == 0x140 ? "UMSCH" : NULL; + break; default: mmhub_cid = NULL; break; From 1d49988d615e26a227a9b02365010606e1274fe0 Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Fri, 18 Jul 2025 13:08:00 +0530 Subject: [PATCH 1617/2653] drm/amdgpu/vcn: Register dump cleanup in VCN3_0 Use generic vcn devcoredump helper functions for VCN3_0 Signed-off-by: Sathishkumar S Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 78 ++------------------------- 1 file changed, 5 insertions(+), 73 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index a89662c97c9ea..ff2a85619f232 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -175,8 +175,6 @@ static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block) struct amdgpu_ring *ring; int i, j, r; int vcn_doorbell_index = 0; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0); - uint32_t *ptr; struct amdgpu_device *adev = ip_block->adev; /* @@ -304,14 +302,9 @@ static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block) return r; } - /* Allocate memory for VCN IP Dump buffer */ - ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); - if (ptr == NULL) { - DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); - adev->vcn.ip_dump = NULL; - } else { - adev->vcn.ip_dump = ptr; - } + r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_3_0, ARRAY_SIZE(vcn_reg_list_3_0)); + if (r) + return r; r = amdgpu_vcn_sysfs_reset_mask_init(adev); if (r) @@ -2348,67 +2341,6 @@ static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) } } -static void vcn_v3_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) -{ - struct amdgpu_device *adev = ip_block->adev; - int i, j; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0); - uint32_t inst_off; - bool is_powered; - - if (!adev->vcn.ip_dump) - return; - - drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - if (adev->vcn.harvest_config & (1 << i)) { - drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); - continue; - } - - inst_off = i * reg_count; - is_powered = (adev->vcn.ip_dump[inst_off] & - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; - - if (is_powered) { - drm_printf(p, "\nActive Instance:VCN%d\n", i); - for (j = 0; j < reg_count; j++) - drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_3_0[j].reg_name, - adev->vcn.ip_dump[inst_off + j]); - } else { - drm_printf(p, "\nInactive Instance:VCN%d\n", i); - } - } -} - -static void vcn_v3_0_dump_ip_state(struct amdgpu_ip_block *ip_block) -{ - struct amdgpu_device *adev = ip_block->adev; - int i, j; - bool is_powered; - uint32_t inst_off; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0); - - if (!adev->vcn.ip_dump) - return; - - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - if (adev->vcn.harvest_config & (1 << i)) - continue; - - inst_off = i * reg_count; - /* mmUVD_POWER_STATUS is always readable and is first element of the array */ - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS); - is_powered = (adev->vcn.ip_dump[inst_off] & - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; - - if (is_powered) - for (j = 1; j < reg_count; j++) - adev->vcn.ip_dump[inst_off + j] = - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_3_0[j], i)); - } -} - static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { .name = "vcn_v3_0", .early_init = vcn_v3_0_early_init, @@ -2422,8 +2354,8 @@ static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { .wait_for_idle = vcn_v3_0_wait_for_idle, .set_clockgating_state = vcn_v3_0_set_clockgating_state, .set_powergating_state = vcn_set_powergating_state, - .dump_ip_state = vcn_v3_0_dump_ip_state, - .print_ip_state = vcn_v3_0_print_ip_state, + .dump_ip_state = amdgpu_vcn_dump_ip_state, + .print_ip_state = amdgpu_vcn_print_ip_state, }; const struct amdgpu_ip_block_version vcn_v3_0_ip_block = { From 6b574a0ef66269c514b5674ae55ff1f7ce853e90 Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Fri, 18 Jul 2025 13:15:00 +0530 Subject: [PATCH 1618/2653] drm/amdgpu/vcn: Register dump cleanup in VCN2_0_0 Use generic vcn devcoredump helper functions for VCN2_0_0 Signed-off-by: Sathishkumar S Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 79 ++------------------------- 1 file changed, 5 insertions(+), 74 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index d1481e6d57ecd..b115137ab2d69 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -136,8 +136,6 @@ static int vcn_v2_0_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int i, r; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0); - uint32_t *ptr; struct amdgpu_device *adev = ip_block->adev; volatile struct amdgpu_fw_shared *fw_shared; @@ -232,14 +230,9 @@ static int vcn_v2_0_sw_init(struct amdgpu_ip_block *ip_block) if (amdgpu_vcnfw_log) amdgpu_vcn_fwlog_init(adev->vcn.inst); - /* Allocate memory for VCN IP Dump buffer */ - ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); - if (!ptr) { - DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); - adev->vcn.ip_dump = NULL; - } else { - adev->vcn.ip_dump = ptr; - } + r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_2_0, ARRAY_SIZE(vcn_reg_list_2_0)); + if (r) + return r; r = amdgpu_vcn_sysfs_reset_mask_init(adev); if (r) @@ -276,8 +269,6 @@ static int vcn_v2_0_sw_fini(struct amdgpu_ip_block *ip_block) r = amdgpu_vcn_sw_fini(adev, 0); - kfree(adev->vcn.ip_dump); - return r; } @@ -2101,66 +2092,6 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev) return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table); } -static void vcn_v2_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) -{ - struct amdgpu_device *adev = ip_block->adev; - int i, j; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0); - uint32_t inst_off, is_powered; - - if (!adev->vcn.ip_dump) - return; - - drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - if (adev->vcn.harvest_config & (1 << i)) { - drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); - continue; - } - - inst_off = i * reg_count; - is_powered = (adev->vcn.ip_dump[inst_off] & - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; - - if (is_powered) { - drm_printf(p, "\nActive Instance:VCN%d\n", i); - for (j = 0; j < reg_count; j++) - drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_0[j].reg_name, - adev->vcn.ip_dump[inst_off + j]); - } else { - drm_printf(p, "\nInactive Instance:VCN%d\n", i); - } - } -} - -static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block) -{ - struct amdgpu_device *adev = ip_block->adev; - int i, j; - bool is_powered; - uint32_t inst_off; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0); - - if (!adev->vcn.ip_dump) - return; - - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - if (adev->vcn.harvest_config & (1 << i)) - continue; - - inst_off = i * reg_count; - /* mmUVD_POWER_STATUS is always readable and is first element of the array */ - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS); - is_powered = (adev->vcn.ip_dump[inst_off] & - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; - - if (is_powered) - for (j = 1; j < reg_count; j++) - adev->vcn.ip_dump[inst_off + j] = - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], i)); - } -} - static const struct amd_ip_funcs vcn_v2_0_ip_funcs = { .name = "vcn_v2_0", .early_init = vcn_v2_0_early_init, @@ -2174,8 +2105,8 @@ static const struct amd_ip_funcs vcn_v2_0_ip_funcs = { .wait_for_idle = vcn_v2_0_wait_for_idle, .set_clockgating_state = vcn_v2_0_set_clockgating_state, .set_powergating_state = vcn_set_powergating_state, - .dump_ip_state = vcn_v2_0_dump_ip_state, - .print_ip_state = vcn_v2_0_print_ip_state, + .dump_ip_state = amdgpu_vcn_dump_ip_state, + .print_ip_state = amdgpu_vcn_print_ip_state, }; static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { From ce826873e468ed1fa85feedeecd50b99236c3b08 Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Fri, 18 Jul 2025 13:23:53 +0530 Subject: [PATCH 1619/2653] drm/amdgpu/vcn: Register dump cleanup in VCN2_5 Use generic vcn devcoredump helper functions for VCN2_5 and VCN2_6 Signed-off-by: Sathishkumar S Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 83 +++------------------------ 1 file changed, 7 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index d7b2668ab0d94..3a7c137a83efb 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -297,8 +297,6 @@ static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int i, j, r; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5); - uint32_t *ptr; struct amdgpu_device *adev = ip_block->adev; for (j = 0; j < adev->vcn.num_vcn_inst; j++) { @@ -423,14 +421,9 @@ static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block) if (r) return r; - /* Allocate memory for VCN IP Dump buffer */ - ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); - if (!ptr) { - DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); - adev->vcn.ip_dump = NULL; - } else { - adev->vcn.ip_dump = ptr; - } + r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_2_5, ARRAY_SIZE(vcn_reg_list_2_5)); + if (r) + return r; r = amdgpu_vcn_sysfs_reset_mask_init(adev); if (r) @@ -477,8 +470,6 @@ static int vcn_v2_5_sw_fini(struct amdgpu_ip_block *ip_block) return r; } - kfree(adev->vcn.ip_dump); - return 0; } @@ -2133,66 +2124,6 @@ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev) } } -static void vcn_v2_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) -{ - struct amdgpu_device *adev = ip_block->adev; - int i, j; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5); - uint32_t inst_off, is_powered; - - if (!adev->vcn.ip_dump) - return; - - drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - if (adev->vcn.harvest_config & (1 << i)) { - drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); - continue; - } - - inst_off = i * reg_count; - is_powered = (adev->vcn.ip_dump[inst_off] & - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; - - if (is_powered) { - drm_printf(p, "\nActive Instance:VCN%d\n", i); - for (j = 0; j < reg_count; j++) - drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_5[j].reg_name, - adev->vcn.ip_dump[inst_off + j]); - } else { - drm_printf(p, "\nInactive Instance:VCN%d\n", i); - } - } -} - -static void vcn_v2_5_dump_ip_state(struct amdgpu_ip_block *ip_block) -{ - struct amdgpu_device *adev = ip_block->adev; - int i, j; - bool is_powered; - uint32_t inst_off; - uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5); - - if (!adev->vcn.ip_dump) - return; - - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - if (adev->vcn.harvest_config & (1 << i)) - continue; - - inst_off = i * reg_count; - /* mmUVD_POWER_STATUS is always readable and is first element of the array */ - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS); - is_powered = (adev->vcn.ip_dump[inst_off] & - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; - - if (is_powered) - for (j = 1; j < reg_count; j++) - adev->vcn.ip_dump[inst_off + j] = - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], i)); - } -} - static const struct amd_ip_funcs vcn_v2_5_ip_funcs = { .name = "vcn_v2_5", .early_init = vcn_v2_5_early_init, @@ -2206,8 +2137,8 @@ static const struct amd_ip_funcs vcn_v2_5_ip_funcs = { .wait_for_idle = vcn_v2_5_wait_for_idle, .set_clockgating_state = vcn_v2_5_set_clockgating_state, .set_powergating_state = vcn_set_powergating_state, - .dump_ip_state = vcn_v2_5_dump_ip_state, - .print_ip_state = vcn_v2_5_print_ip_state, + .dump_ip_state = amdgpu_vcn_dump_ip_state, + .print_ip_state = amdgpu_vcn_print_ip_state, }; static const struct amd_ip_funcs vcn_v2_6_ip_funcs = { @@ -2223,8 +2154,8 @@ static const struct amd_ip_funcs vcn_v2_6_ip_funcs = { .wait_for_idle = vcn_v2_5_wait_for_idle, .set_clockgating_state = vcn_v2_5_set_clockgating_state, .set_powergating_state = vcn_set_powergating_state, - .dump_ip_state = vcn_v2_5_dump_ip_state, - .print_ip_state = vcn_v2_5_print_ip_state, + .dump_ip_state = amdgpu_vcn_dump_ip_state, + .print_ip_state = amdgpu_vcn_print_ip_state, }; const struct amdgpu_ip_block_version vcn_v2_5_ip_block = From 3fde320e43bf8c55fcfe9e295c21cde0746ec597 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 27 Jun 2025 10:10:31 -0400 Subject: [PATCH 1620/2653] drm/amd/display: add more cyan skillfish devices Add PCI IDs to support display probe for cyan skillfish family of SOCs. Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 8 +++++++- drivers/gpu/drm/amd/display/include/dal_asic_id.h | 5 +++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 4d6181e7c612b..d712548b1927d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -165,7 +165,13 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) case FAMILY_NV: dc_version = DCN_VERSION_2_0; - if (asic_id.chip_id == DEVICE_ID_NV_13FE || asic_id.chip_id == DEVICE_ID_NV_143F) { + if (asic_id.chip_id == DEVICE_ID_NV_13FE || + asic_id.chip_id == DEVICE_ID_NV_143F || + asic_id.chip_id == DEVICE_ID_NV_13F9 || + asic_id.chip_id == DEVICE_ID_NV_13FA || + asic_id.chip_id == DEVICE_ID_NV_13FB || + asic_id.chip_id == DEVICE_ID_NV_13FC || + asic_id.chip_id == DEVICE_ID_NV_13DB) { dc_version = DCN_VERSION_2_01; break; } diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index 5fc29164e4b45..8aea50aa95330 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -213,6 +213,11 @@ enum { #endif #define DEVICE_ID_NV_13FE 0x13FE // CYAN_SKILLFISH #define DEVICE_ID_NV_143F 0x143F +#define DEVICE_ID_NV_13F9 0x13F9 +#define DEVICE_ID_NV_13FA 0x13FA +#define DEVICE_ID_NV_13FB 0x13FB +#define DEVICE_ID_NV_13FC 0x13FC +#define DEVICE_ID_NV_13DB 0x13DB #define FAMILY_VGH 144 #define DEVICE_ID_VGH_163F 0x163F #define DEVICE_ID_VGH_1435 0x1435 From c6f9cce16f79c19113317c342afe9a4c0b57690b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 14 Jul 2025 10:16:25 +0200 Subject: [PATCH 1621/2653] drm/amdgpu: fix link error for !PM_SLEEP When power management is not enabled in the kernel build, the newly added hibernation changes cause a link failure: arm-linux-gnueabi-ld: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.o: in function `amdgpu_pmops_thaw': amdgpu_drv.c:(.text+0x1514): undefined reference to `pm_hibernate_is_recovering' Make the power management code in this driver conditional on CONFIG_PM and CONFIG_PM_SLEEP Fixes: 530694f54dd5 ("drm/amdgpu: do not resume device in thaw for normal hibernation") Signed-off-by: Arnd Bergmann Reviewed-by: Mario Limonciello Link: https://lore.kernel.org/r/20250714081635.4071570-1-arnd@kernel.org Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 38fe48bdcb618..e16a384466c9d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3031,15 +3031,15 @@ long amdgpu_drm_ioctl(struct file *filp, } static const struct dev_pm_ops amdgpu_pm_ops = { - .prepare = amdgpu_pmops_prepare, - .complete = amdgpu_pmops_complete, - .suspend = amdgpu_pmops_suspend, - .suspend_noirq = amdgpu_pmops_suspend_noirq, - .resume = amdgpu_pmops_resume, - .freeze = amdgpu_pmops_freeze, - .thaw = amdgpu_pmops_thaw, - .poweroff = amdgpu_pmops_poweroff, - .restore = amdgpu_pmops_restore, + .prepare = pm_sleep_ptr(amdgpu_pmops_prepare), + .complete = pm_sleep_ptr(amdgpu_pmops_complete), + .suspend = pm_sleep_ptr(amdgpu_pmops_suspend), + .suspend_noirq = pm_sleep_ptr(amdgpu_pmops_suspend_noirq), + .resume = pm_sleep_ptr(amdgpu_pmops_resume), + .freeze = pm_sleep_ptr(amdgpu_pmops_freeze), + .thaw = pm_sleep_ptr(amdgpu_pmops_thaw), + .poweroff = pm_sleep_ptr(amdgpu_pmops_poweroff), + .restore = pm_sleep_ptr(amdgpu_pmops_restore), .runtime_suspend = amdgpu_pmops_runtime_suspend, .runtime_resume = amdgpu_pmops_runtime_resume, .runtime_idle = amdgpu_pmops_runtime_idle, @@ -3257,7 +3257,7 @@ static struct pci_driver amdgpu_kms_pci_driver = { .probe = amdgpu_pci_probe, .remove = amdgpu_pci_remove, .shutdown = amdgpu_pci_shutdown, - .driver.pm = &amdgpu_pm_ops, + .driver.pm = pm_ptr(&amdgpu_pm_ops), .err_handler = &amdgpu_pci_err_handler, #ifdef HAVE_PCI_DRIVER_DEV_GROUPS .dev_groups = amdgpu_sysfs_groups, From 57466087946ed5ebeb4820c990a87879a6c81016 Mon Sep 17 00:00:00 2001 From: Xiang Liu Date: Wed, 30 Jul 2025 11:07:43 +0800 Subject: [PATCH 1622/2653] drm/amdgpu: Skip poison aca bank from UE channel Avoid GFX poison consumption errors logged when fatal error occurs. Signed-off-by: Xiang Liu Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 51 +++++++++++++++---------- 1 file changed, 30 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c index cbc40cad581b4..d1e431818212d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c @@ -130,6 +130,27 @@ static void aca_smu_bank_dump(struct amdgpu_device *adev, int idx, int total, st RAS_EVENT_LOG(adev, event_id, HW_ERR "hardware error logged by the scrubber\n"); } +static bool aca_bank_hwip_is_matched(struct aca_bank *bank, enum aca_hwip_type type) +{ + + struct aca_hwip *hwip; + int hwid, mcatype; + u64 ipid; + + if (!bank || type == ACA_HWIP_TYPE_UNKNOW) + return false; + + hwip = &aca_hwid_mcatypes[type]; + if (!hwip->hwid) + return false; + + ipid = bank->regs[ACA_REG_IDX_IPID]; + hwid = ACA_REG__IPID__HARDWAREID(ipid); + mcatype = ACA_REG__IPID__MCATYPE(ipid); + + return hwip->hwid == hwid && hwip->mcatype == mcatype; +} + static int aca_smu_get_valid_aca_banks(struct amdgpu_device *adev, enum aca_smu_type type, int start, int count, struct aca_banks *banks, struct ras_query_context *qctx) @@ -168,6 +189,15 @@ static int aca_smu_get_valid_aca_banks(struct amdgpu_device *adev, enum aca_smu_ bank.smu_err_type = type; + /* + * Poison being consumed when injecting a UE while running background workloads, + * which are unexpected. + */ + if (type == ACA_SMU_TYPE_UE && + ACA_REG__STATUS__POISON(bank.regs[ACA_REG_IDX_STATUS]) && + !aca_bank_hwip_is_matched(&bank, ACA_HWIP_TYPE_UMC)) + continue; + aca_smu_bank_dump(adev, i, count, &bank, qctx); ret = aca_banks_add_bank(banks, &bank); @@ -178,27 +208,6 @@ static int aca_smu_get_valid_aca_banks(struct amdgpu_device *adev, enum aca_smu_ return 0; } -static bool aca_bank_hwip_is_matched(struct aca_bank *bank, enum aca_hwip_type type) -{ - - struct aca_hwip *hwip; - int hwid, mcatype; - u64 ipid; - - if (!bank || type == ACA_HWIP_TYPE_UNKNOW) - return false; - - hwip = &aca_hwid_mcatypes[type]; - if (!hwip->hwid) - return false; - - ipid = bank->regs[ACA_REG_IDX_IPID]; - hwid = ACA_REG__IPID__HARDWAREID(ipid); - mcatype = ACA_REG__IPID__MCATYPE(ipid); - - return hwip->hwid == hwid && hwip->mcatype == mcatype; -} - static bool aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type) { const struct aca_bank_ops *bank_ops = handle->bank_ops; From 7e2393b8a5b052ccccb8073c28a1c6c87e85d4b4 Mon Sep 17 00:00:00 2001 From: Mangesh Gadre Date: Tue, 22 Jul 2025 00:27:52 +0800 Subject: [PATCH 1623/2653] drm/amdgpu: Initialize jpeg v5_0_1 ras function Initialize jpeg v5_0_1 ras function Signed-off-by: Mangesh Gadre Reviewed-by: Stanley.Yang Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c index 03ec4b741d194..8d74455dab1e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c @@ -196,6 +196,14 @@ static int jpeg_v5_0_1_sw_init(struct amdgpu_ip_block *ip_block) } } + if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { + r = amdgpu_jpeg_ras_sw_init(adev); + if (r) { + dev_err(adev->dev, "Failed to initialize jpeg ras block!\n"); + return r; + } + } + r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_5_0_1, ARRAY_SIZE(jpeg_reg_list_5_0_1)); if (r) return r; From d245204fa37f89e43e6a15ecfff334243ec2bf19 Mon Sep 17 00:00:00 2001 From: Yunxiang Li Date: Fri, 25 Jul 2025 12:56:35 -0400 Subject: [PATCH 1624/2653] drm/amdgpu: skip mgpu fan boost for multi-vf On multi-vf setup if the VM have two vf assigned, perhaps from two different gpus, mgpu fan boost will fail. Signed-off-by: Yunxiang Li Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index b22e4ebf8efa2..39cf5d19bffc0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3414,7 +3414,7 @@ static int amdgpu_device_enable_mgpu_fan_boost(void) for (i = 0; i < mgpu_info.num_dgpu; i++) { gpu_ins = &(mgpu_info.gpu_ins[i]); adev = gpu_ins->adev; - if (!(adev->flags & AMD_IS_APU) && + if (!(adev->flags & AMD_IS_APU || amdgpu_sriov_multi_vf_mode(adev)) && !gpu_ins->mgpu_fan_enabled) { ret = amdgpu_dpm_enable_mgpu_fan_boost(adev); if (ret) From 6f26071b896b4dc6dd36f18d27a8a5c670d6fece Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Wed, 30 Jul 2025 10:09:02 +0200 Subject: [PATCH 1625/2653] drm/amd/display: Add primary plane to commits for correct VRR handling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit amdgpu_dm_commit_planes calls update_freesync_state_on_stream only for the primary plane. If a commit affects a CRTC but not its primary plane, it would previously not trigger a refresh cycle or affect LFC, violating current UAPI semantics. Fixes e.g. atomic commits affecting only the cursor plane being limited to the minimum refresh rate. Don't do this for the legacy cursor ioctls though, it would break the UAPI semantics for those. Suggested-by: Xaver Hugl Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3034 Signed-off-by: Michel Dänzer Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index b9abdd6ca06c7..4c9d1d41ac8b7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -676,6 +676,15 @@ static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, return -EINVAL; } + if (!state->legacy_cursor_update && amdgpu_dm_crtc_vrr_active(dm_crtc_state)) { + struct drm_plane_state *primary_state; + + /* Pull in primary plane for correct VRR handling */ + primary_state = drm_atomic_get_plane_state(state, crtc->primary); + if (IS_ERR(primary_state)) + return PTR_ERR(primary_state); + } + /* In some use cases, like reset, no stream is attached */ if (!dm_crtc_state->stream) return 0; From fba9a094fce03cbc937b1daf8267d34971382c42 Mon Sep 17 00:00:00 2001 From: Mangesh Gadre Date: Mon, 21 Jul 2025 23:32:34 +0800 Subject: [PATCH 1626/2653] drm/amdgpu: Initialize vcn v5_0_1 ras function Initialize vcn v5_0_1 ras function Signed-off-by: Mangesh Gadre Reviewed-by: Stanley.Yang Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c index 553ffad0888a9..60739be6db27f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c @@ -197,6 +197,14 @@ static int vcn_v5_0_1_sw_init(struct amdgpu_ip_block *ip_block) return r; } + if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { + r = amdgpu_vcn_ras_sw_init(adev); + if (r) { + dev_err(adev->dev, "Failed to initialize vcn ras block!\n"); + return r; + } + } + r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_5_0_1, ARRAY_SIZE(vcn_reg_list_5_0_1)); if (r) return r; From e3d77ea2d0239872bb9051d0cab5c3c6f5949c25 Mon Sep 17 00:00:00 2001 From: Siyang Liu Date: Fri, 4 Jul 2025 11:16:22 +0800 Subject: [PATCH 1627/2653] drm/amd/display: fix a Null pointer dereference vulnerability [Why] A null pointer dereference vulnerability exists in the AMD display driver's (DC module) cleanup function dc_destruct(). When display control context (dc->ctx) construction fails (due to memory allocation failure), this pointer remains NULL. During subsequent error handling when dc_destruct() is called, there's no NULL check before dereferencing the perf_trace member (dc->ctx->perf_trace), causing a kernel null pointer dereference crash. [How] Check if dc->ctx is non-NULL before dereferencing. Link: https://lore.kernel.org/r/tencent_54FF4252EDFB6533090A491A25EEF3EDBF06@qq.com Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello (Updated commit text and removed unnecessary error message) Signed-off-by: Siyang Liu Signed-off-by: Roman Li Reviewed-by: Alex Hung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 8229abc65670a..b9d9ba1706628 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -940,17 +940,18 @@ static void dc_destruct(struct dc *dc) if (dc->link_srv) link_destroy_link_service(&dc->link_srv); - if (dc->ctx->gpio_service) - dal_gpio_service_destroy(&dc->ctx->gpio_service); + if (dc->ctx) { + if (dc->ctx->gpio_service) + dal_gpio_service_destroy(&dc->ctx->gpio_service); - if (dc->ctx->created_bios) - dal_bios_parser_destroy(&dc->ctx->dc_bios); + if (dc->ctx->created_bios) + dal_bios_parser_destroy(&dc->ctx->dc_bios); + kfree(dc->ctx->logger); + dc_perf_trace_destroy(&dc->ctx->perf_trace); - kfree(dc->ctx->logger); - dc_perf_trace_destroy(&dc->ctx->perf_trace); - - kfree(dc->ctx); - dc->ctx = NULL; + kfree(dc->ctx); + dc->ctx = NULL; + } kfree(dc->bw_vbios); dc->bw_vbios = NULL; From a67a92cceab9e8c6efc56c03b39883885fba0759 Mon Sep 17 00:00:00 2001 From: Duncan Ma Date: Tue, 22 Jul 2025 12:22:15 -0400 Subject: [PATCH 1628/2653] drm/amd/display: Adjust AUX-less ALPM setting [Why & How] Change ACDS period to support LTTPR. Reviewed-by: Charlene Liu Signed-off-by: Duncan Ma Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/link/protocols/link_edp_panel_control.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index be714cbf66155..2c3e2945124a9 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -1046,7 +1046,7 @@ bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream if (link->replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) { alpm_config.bits.ALPM_MODE_SEL = 1; - alpm_config.bits.ACDS_PERIOD_DURATION = 1; + alpm_config.bits.ACDS_PERIOD_DURATION = 0; } dm_helpers_dp_write_dpcd( From 45f59178e36df3df7b3c54b77e09c8afab63a605 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Mon, 21 Jul 2025 11:03:39 -0400 Subject: [PATCH 1629/2653] drm/amd/display: fix dmub access race condition Accessing DC from amdgpu_dm is usually preceded by acquisition of dc_lock mutex. Most of the DC API that DM calls are under a DC lock. However, there are a few that are not. Some DC API called from interrupt context end up sending DMUB commands via a DC API, while other threads were using DMUB. This was apparent from a race between calls for setting idle optimization enable/disable and the DC API to set vmin/vmax. Offload the call to dc_stream_adjust_vmin_vmax() to a thread instead of directly calling them from the interrupt handler such that it waits for dc_lock. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Aurabindo Pillai Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 54 ++++++++++++++++--- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 14 +++++ 2 files changed, 62 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ad36abcacebd5..50fd6ef95aa1c 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -537,6 +537,49 @@ static inline ktime_t get_drm_vblank_crtc_time(struct drm_vblank_crtc *vblank) return kcl_amdgpu_get_vblank_time_ns(vblank); } #endif +static void dm_handle_vmin_vmax_update(struct work_struct *offload_work) +{ + struct vupdate_offload_work *work = container_of(offload_work, struct vupdate_offload_work, work); + struct amdgpu_device *adev = work->adev; + struct dc_stream_state *stream = work->stream; + struct dc_crtc_timing_adjust *adjust = work->adjust; + + mutex_lock(&adev->dm.dc_lock); + dc_stream_adjust_vmin_vmax(adev->dm.dc, stream, adjust); + mutex_unlock(&adev->dm.dc_lock); + + dc_stream_release(stream); + kfree(work->adjust); + kfree(work); +} + +static void schedule_dc_vmin_vmax(struct amdgpu_device *adev, + struct dc_stream_state *stream, + struct dc_crtc_timing_adjust *adjust) +{ + struct vupdate_offload_work *offload_work = kzalloc(sizeof(*offload_work), GFP_KERNEL); + if (!offload_work) { + drm_dbg_driver(adev_to_drm(adev), "Failed to allocate vupdate_offload_work\n"); + return; + } + + struct dc_crtc_timing_adjust *adjust_copy = kzalloc(sizeof(*adjust_copy), GFP_KERNEL); + if (!adjust_copy) { + drm_dbg_driver(adev_to_drm(adev), "Failed to allocate adjust_copy\n"); + kfree(offload_work); + return; + } + + dc_stream_retain(stream); + memcpy(adjust_copy, adjust, sizeof(*adjust_copy)); + + INIT_WORK(&offload_work->work, dm_handle_vmin_vmax_update); + offload_work->adev = adev; + offload_work->stream = stream; + offload_work->adjust = adjust_copy; + + queue_work(system_wq, &offload_work->work); +} static void dm_vupdate_high_irq(void *interrupt_params) { @@ -592,10 +635,9 @@ static void dm_vupdate_high_irq(void *interrupt_params) acrtc->dm_irq_params.stream, &acrtc->dm_irq_params.vrr_params); - dc_stream_adjust_vmin_vmax( - adev->dm.dc, - acrtc->dm_irq_params.stream, - &acrtc->dm_irq_params.vrr_params.adjust); + schedule_dc_vmin_vmax(adev, + acrtc->dm_irq_params.stream, + &acrtc->dm_irq_params.vrr_params.adjust); spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); } } @@ -685,8 +727,8 @@ static void dm_crtc_high_irq(void *interrupt_params) acrtc->dm_irq_params.stream, &acrtc->dm_irq_params.vrr_params); - dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, - &acrtc->dm_irq_params.vrr_params.adjust); + schedule_dc_vmin_vmax(adev, acrtc->dm_irq_params.stream, + &acrtc->dm_irq_params.vrr_params.adjust); } /* diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 46852eaec41c1..91d82f25d1e52 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -153,6 +153,20 @@ struct idle_workqueue { bool running; }; +/** + * struct dm_vupdate_work - Work data for periodic action in idle + * @work: Kernel work data for the work event + * @adev: amdgpu_device back pointer + * @stream: DC stream associated with the crtc + * @adjust: DC CRTC timing adjust to be applied to the crtc + */ +struct vupdate_offload_work { + struct work_struct work; + struct amdgpu_device *adev; + struct dc_stream_state *stream; + struct dc_crtc_timing_adjust *adjust; +}; + #define MAX_LUMINANCE_DATA_POINTS 99 /** From ebe62d77dfa6879aaceb36fb3028a854e0dc15e6 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Wed, 16 Apr 2025 11:26:54 -0400 Subject: [PATCH 1630/2653] drm/amd/display: more liberal vmin/vmax update for freesync [Why] FAMS2 expects vmin/vmax to be updated in the case when freesync is off, but supported. But we only update it when freesync is enabled. [How] Change the vsync handler such that dc_stream_adjust_vmin_vmax() its called irrespective of whether freesync is enabled. If freesync is supported, then there is no harm in updating vmin/vmax registers. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3546 Reviewed-by: Nicholas Kazlauskas Signed-off-by: Aurabindo Pillai Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Roman Li Reviewed-by: ChiaHsuan Chung Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 28 +++++++++++++------ 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 50fd6ef95aa1c..ab3a8071a165e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -624,6 +624,11 @@ static void dm_vupdate_high_irq(void *interrupt_params) * if a pageflip happened inside front-porch. */ if (vrr_active) { + bool replay_en = acrtc->dm_irq_params.stream->link->replay_settings.replay_feature_enabled; + bool psr_en = acrtc->dm_irq_params.stream->link->psr_settings.psr_feature_enabled; + bool fs_active_var_en = acrtc->dm_irq_params.freesync_config.state + == VRR_STATE_ACTIVE_VARIABLE; + amdgpu_dm_crtc_handle_vblank(acrtc); /* BTR processing for pre-DCE12 ASICs */ @@ -635,9 +640,11 @@ static void dm_vupdate_high_irq(void *interrupt_params) acrtc->dm_irq_params.stream, &acrtc->dm_irq_params.vrr_params); - schedule_dc_vmin_vmax(adev, - acrtc->dm_irq_params.stream, - &acrtc->dm_irq_params.vrr_params.adjust); + if (fs_active_var_en || (!fs_active_var_en && !replay_en && !psr_en)) { + schedule_dc_vmin_vmax(adev, + acrtc->dm_irq_params.stream, + &acrtc->dm_irq_params.vrr_params.adjust); + } spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); } } @@ -720,15 +727,20 @@ static void dm_crtc_high_irq(void *interrupt_params) spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); if (acrtc->dm_irq_params.stream && - acrtc->dm_irq_params.vrr_params.supported && - acrtc->dm_irq_params.freesync_config.state == - VRR_STATE_ACTIVE_VARIABLE) { + acrtc->dm_irq_params.vrr_params.supported) { + bool replay_en = acrtc->dm_irq_params.stream->link->replay_settings.replay_feature_enabled; + bool psr_en = acrtc->dm_irq_params.stream->link->psr_settings.psr_feature_enabled; + bool fs_active_var_en = acrtc->dm_irq_params.freesync_config.state == VRR_STATE_ACTIVE_VARIABLE; + mod_freesync_handle_v_update(adev->dm.freesync_module, acrtc->dm_irq_params.stream, &acrtc->dm_irq_params.vrr_params); - schedule_dc_vmin_vmax(adev, acrtc->dm_irq_params.stream, - &acrtc->dm_irq_params.vrr_params.adjust); + /* update vmin_vmax only if freesync is enabled, or only if PSR and REPLAY are disabled */ + if (fs_active_var_en || (!fs_active_var_en && !replay_en && !psr_en)) { + schedule_dc_vmin_vmax(adev, acrtc->dm_irq_params.stream, + &acrtc->dm_irq_params.vrr_params.adjust); + } } /* From 39d86dd9ef511a8e093d1f326079be0c006005b9 Mon Sep 17 00:00:00 2001 From: Paul Hsieh Date: Wed, 23 Jul 2025 11:51:42 +0800 Subject: [PATCH 1631/2653] drm/amd/display: update dpp/disp clock from smu clock table [Why] The reason some high-resolution monitors fail to display properly is that this platform does not support sufficiently high DPP and DISP clock frequencies [How] Update DISP and DPP clocks from the smu clock table then DML can filter these mode if not support. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Paul Hsieh Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- .../display/dc/clk_mgr/dcn301/vg_clk_mgr.c | 16 +++++++++++++++ .../amd/display/dc/dml/dcn301/dcn301_fpu.c | 20 ++++++++++++++++--- 2 files changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c index 9e2ef0e724fcf..7aee02d562923 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c @@ -563,6 +563,7 @@ static void vg_clk_mgr_helper_populate_bw_params( { int i, j; struct clk_bw_params *bw_params = clk_mgr->base.bw_params; + uint32_t max_dispclk = 0, max_dppclk = 0; j = -1; @@ -584,6 +585,15 @@ static void vg_clk_mgr_helper_populate_bw_params( return; } + /* dispclk and dppclk can be max at any voltage, same number of levels for both */ + if (clock_table->NumDispClkLevelsEnabled <= VG_NUM_DISPCLK_DPM_LEVELS && + clock_table->NumDispClkLevelsEnabled <= VG_NUM_DPPCLK_DPM_LEVELS) { + max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); + max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); + } else { + ASSERT(0); + } + bw_params->clk_table.num_entries = j + 1; for (i = 0; i < bw_params->clk_table.num_entries - 1; i++, j--) { @@ -591,11 +601,17 @@ static void vg_clk_mgr_helper_populate_bw_params( bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk; bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage; bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfPstateTable[j].voltage); + + /* Now update clocks we do read */ + bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; + bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; } bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk; bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage; bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, VG_NUM_DCFCLK_DPM_LEVELS); + bw_params->clk_table.entries[i].dispclk_mhz = find_max_clk_value(clock_table->DispClocks, VG_NUM_DISPCLK_DPM_LEVELS); + bw_params->clk_table.entries[i].dppclk_mhz = find_max_clk_value(clock_table->DppClocks, VG_NUM_DPPCLK_DPM_LEVELS); bw_params->vram_type = bios_info->memory_type; bw_params->num_channels = bios_info->ma_channel_number; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c index 0c0b2d67c9cd9..2066a65c69bbc 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c @@ -326,7 +326,7 @@ void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool); struct clk_limit_table *clk_table = &bw_params->clk_table; unsigned int i, closest_clk_lvl; - int j; + int j = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0; dc_assert_fp_enabled(); @@ -338,6 +338,15 @@ void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p dcn3_01_soc.num_chans = bw_params->num_channels; ASSERT(clk_table->num_entries); + + /* Prepass to find max clocks independent of voltage level. */ + for (i = 0; i < clk_table->num_entries; ++i) { + if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) + max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; + if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) + max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; + } + for (i = 0; i < clk_table->num_entries; i++) { /* loop backwards*/ for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) { @@ -353,8 +362,13 @@ void dcn301_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p s[i].socclk_mhz = clk_table->entries[i].socclk_mhz; s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; - s[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz; - s[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz; + /* Clocks independent of voltage level. */ + s[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : + dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz; + + s[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz : + dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz; + s[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; s[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz; From 765055984c8e734e5f73eb425c842f288cb0341f Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Sun, 20 Jul 2025 23:39:41 -0500 Subject: [PATCH 1632/2653] drm/amd/display: Revert "drm/amd/display: Fix AMDGPU_MAX_BL_LEVEL value" This reverts commit 66abb996999de0d440a02583a6e70c2c24deab45. This broke custom brightness curves but it wasn't obvious because of other related changes. Custom brightness curves are always from a 0-255 input signal. The correct fix was to fix the default value which was done by [1]. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4412 Cc: stable@vger.kernel.org Link: https://lore.kernel.org/amd-gfx/0f094c4b-d2a3-42cd-824c-dc2858a5618d@kernel.org/T/#m69f875a7e69aa22df3370b3e3a9e69f4a61fdaf2 Reviewed-by: Alex Hung Signed-off-by: Mario Limonciello Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ab3a8071a165e..13cd73964291f 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4875,16 +4875,16 @@ static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, return 1; } -/* Rescale from [min..max] to [0..MAX_BACKLIGHT_LEVEL] */ +/* Rescale from [min..max] to [0..AMDGPU_MAX_BL_LEVEL] */ static inline u32 scale_input_to_fw(int min, int max, u64 input) { - return DIV_ROUND_CLOSEST_ULL(input * MAX_BACKLIGHT_LEVEL, max - min); + return DIV_ROUND_CLOSEST_ULL(input * AMDGPU_MAX_BL_LEVEL, max - min); } -/* Rescale from [0..MAX_BACKLIGHT_LEVEL] to [min..max] */ +/* Rescale from [0..AMDGPU_MAX_BL_LEVEL] to [min..max] */ static inline u32 scale_fw_to_input(int min, int max, u64 input) { - return min + DIV_ROUND_CLOSEST_ULL(input * (max - min), MAX_BACKLIGHT_LEVEL); + return min + DIV_ROUND_CLOSEST_ULL(input * (max - min), AMDGPU_MAX_BL_LEVEL); } static void convert_custom_brightness(const struct amdgpu_dm_backlight_caps *caps, From ff2b562462f1688f605fbd9555417cde99c5af2e Mon Sep 17 00:00:00 2001 From: Fangzhi Zuo Date: Wed, 9 Jul 2025 21:42:54 -0400 Subject: [PATCH 1633/2653] drm/amd/display: Avoid Read Remote DPCD Many Times Reading remote dpcd is time consuming. Instead of reading each byte one by one, read 16 bytes together. Reviewed-by: ChiaHsuan (Tom) Chung Signed-off-by: Fangzhi Zuo Signed-off-by: Wayne Lin Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index a3d3462f633f4..d563e55bbf515 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -2047,14 +2047,17 @@ static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_lin union lane_count_set lane_count; u8 dp_link_encoding; u8 link_bw_set = 0; + u8 data[16] = {0}; *cur_link_bw = 0; - if (drm_dp_dpcd_read(aux, DP_MAIN_LINK_CHANNEL_CODING_SET, &dp_link_encoding, 1) != 1 || - drm_dp_dpcd_read(aux, DP_LANE_COUNT_SET, &lane_count.raw, 1) != 1 || - drm_dp_dpcd_read(aux, DP_LINK_BW_SET, &link_bw_set, 1) != 1) + if (drm_dp_dpcd_read(aux, DP_LINK_BW_SET, data, 16) != 16) return false; + dp_link_encoding = data[DP_MAIN_LINK_CHANNEL_CODING_SET - DP_LINK_BW_SET]; + link_bw_set = data[DP_LINK_BW_SET - DP_LINK_BW_SET]; + lane_count.raw = data[DP_LANE_COUNT_SET - DP_LINK_BW_SET]; + switch (dp_link_encoding) { case DP_8b_10b_ENCODING: link_rate = link_bw_set; From 26b9c77466124168c88e552a5c449673ffd5431d Mon Sep 17 00:00:00 2001 From: Jingwen Zhu Date: Mon, 14 Jul 2025 16:18:19 +0800 Subject: [PATCH 1634/2653] drm/amd/display: limited pll vco w/a v2 [Why/How] The w/a will cause reboot black screen issue. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Jingwen Zhu Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 + drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 ++- drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index 0bafb67107618..87b761ac3135d 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -316,6 +316,7 @@ struct dmub_srv_hw_params { bool disable_sldo_opt; bool enable_non_transparent_setconfig; bool lower_hbr3_phy_ssc; + bool override_hbr3_pll_vco; }; /** diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index dcae768c2cf44..79b5b1bb9b93c 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -843,7 +843,8 @@ union dmub_fw_boot_options { uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ - uint32_t reserved : 6; /**< reserved */ + uint32_t override_hbr3_pll_vco: 1; /**< 1 to override the hbr3 pll vco to 0 */ + uint32_t reserved : 5; /**< reserved */ } bits; /**< boot bits */ uint32_t all; /**< 32-bit access to bits */ }; diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c index 3f38db752b844..4777c7203b2c2 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c @@ -377,6 +377,7 @@ void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported; boot_options.bits.power_optimization = params->power_optimization; boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc; + boot_options.bits.override_hbr3_pll_vco = params->override_hbr3_pll_vco; boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic == DMUB_ASIC_DCN31B) ? 1 : 0; From eb7c1ed6469bec172b7b369c79ba964a4f942640 Mon Sep 17 00:00:00 2001 From: Reza Amini Date: Mon, 14 Jul 2025 16:22:38 -0400 Subject: [PATCH 1635/2653] drm/amd/display: Fixing hubp programming of 3dlut fast load [why] HUBP needs to know the size of the lut's destination in MPC. This is currently defaulted to 17, and needs to be set for specific lut size. [how] Define and apply the missing hubp field. Taking this opportunity to consolidate the programming of 3dlut into a hubp and mpc function. Reviewed-by: Krunoslav Kovac Signed-off-by: Reza Amini Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 26 ++++++++ .../amd/display/dc/hubp/dcn10/dcn10_hubp.h | 1 + .../amd/display/dc/hubp/dcn20/dcn20_hubp.h | 1 + .../amd/display/dc/hubp/dcn401/dcn401_hubp.c | 38 +++++++++++ .../amd/display/dc/hubp/dcn401/dcn401_hubp.h | 4 ++ .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 63 ++++++++++++++----- drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 19 +++++- drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 11 ++++ 8 files changed, 148 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 4c194aa91488c..e1f0f5ba69eb7 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1314,6 +1314,32 @@ union dc_3dlut_state { }; +#define MATRIX_9C__DIM_128_ALIGNED_LEN 16 // 9+8 : 9 * 8 + 7 * 8 = 72 + 56 = 128 % 128 = 0 +#define MATRIX_17C__DIM_128_ALIGNED_LEN 32 //17+15: 17 * 8 + 15 * 8 = 136 + 120 = 256 % 128 = 0 +#define MATRIX_33C__DIM_128_ALIGNED_LEN 64 //17+47: 17 * 8 + 47 * 8 = 136 + 376 = 512 % 128 = 0 + +struct lut_rgb { + uint16_t b; + uint16_t g; + uint16_t r; + uint16_t padding; +}; + +//this structure maps directly to how the lut will read it from memory +struct lut_mem_mapping { + union { + //NATIVE MODE 1, 2 + //RGB layout [b][g][r] //red is 128 byte aligned + //BGR layout [r][g][b] //blue is 128 byte aligned + struct lut_rgb rgb_17c[17][17][MATRIX_17C__DIM_128_ALIGNED_LEN]; + struct lut_rgb rgb_33c[33][33][MATRIX_33C__DIM_128_ALIGNED_LEN]; + + //TRANSFORMED + uint16_t linear_rgb[(33*33*33*4/128+1)*128]; + }; + uint16_t size; +}; + struct dc_rmcm_3dlut { bool isInUse; const struct dc_stream_state *stream; diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h index f8f991785d4f8..0b7547d5b4882 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h @@ -671,6 +671,7 @@ struct dcn_fl_regs_st { uint32_t lut_done; uint32_t lut_addr_mode; uint32_t lut_width; + uint32_t lut_mpc_width; uint32_t lut_tmz; uint32_t lut_crossbar_sel_r; uint32_t lut_crossbar_sel_g; diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h index 62369be070eab..f325db555102b 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h @@ -264,6 +264,7 @@ type HUBP_3DLUT_DONE;\ type HUBP_3DLUT_ADDRESSING_MODE;\ type HUBP_3DLUT_WIDTH;\ + type HUBP_3DLUT_MPC_WIDTH;\ type HUBP_3DLUT_TMZ;\ type HUBP_3DLUT_CROSSBAR_SELECT_Y_G;\ type HUBP_3DLUT_CROSSBAR_SELECT_CB_B;\ diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c index 705b98b1b6cc2..5028180ad80af 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c @@ -127,6 +127,43 @@ void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_forma REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_FORMAT, format); } +void hubp401_program_3dlut_fl_config( + struct hubp *hubp, + struct hubp_fl_3dlut_config *cfg) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + uint32_t mpc_width = {(cfg->width == 17) ? 0 : 1}; + uint32_t width = {cfg->width}; + + if (cfg->layout == DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR) + width = (cfg->width == 17) ? 4916 : 35940; + + REG_UPDATE_2(_3DLUT_FL_CONFIG, + HUBP0_3DLUT_FL_MODE, cfg->mode, + HUBP0_3DLUT_FL_FORMAT, cfg->format); + + REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE, + HUBP0_3DLUT_FL_BIAS, cfg->bias, + HUBP0_3DLUT_FL_SCALE, cfg->scale); + + REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, + HUBP_3DLUT_ADDRESS_HIGH, cfg->address.lut3d.addr.high_part); + REG_UPDATE(HUBP_3DLUT_ADDRESS_LOW, + HUBP_3DLUT_ADDRESS_LOW, cfg->address.lut3d.addr.low_part); + + //cross bar + REG_UPDATE_8(HUBP_3DLUT_CONTROL, + HUBP_3DLUT_MPC_WIDTH, mpc_width, + HUBP_3DLUT_WIDTH, width, + HUBP_3DLUT_CROSSBAR_SELECT_CR_R, cfg->crossbar_bit_slice_cr_r, + HUBP_3DLUT_CROSSBAR_SELECT_Y_G, cfg->crossbar_bit_slice_y_g, + HUBP_3DLUT_CROSSBAR_SELECT_CB_B, cfg->crossbar_bit_slice_cb_b, + HUBP_3DLUT_ADDRESSING_MODE, cfg->addr_mode, + HUBP_3DLUT_TMZ, cfg->protection_bits, + HUBP_3DLUT_ENABLE, cfg->enabled ? 1 : 0); +} + void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); @@ -1033,6 +1070,7 @@ static struct hubp_funcs dcn401_hubp_funcs = { .hubp_program_3dlut_fl_crossbar = hubp401_program_3dlut_fl_crossbar, .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done, .hubp_clear_tiling = hubp401_clear_tiling, + .hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config, }; bool hubp401_construct( diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h index 608e6153fa68e..887b479ed1d79 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h @@ -349,6 +349,10 @@ void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_forma void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode); +void hubp401_program_3dlut_fl_config( + struct hubp *hubp, + struct hubp_fl_3dlut_config *cfg); + void hubp401_clear_tiling(struct hubp *hubp); void hubp401_vready_at_or_After_vsync(struct hubp *hubp, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 39910f73ecd06..79c9bea78c478 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -328,19 +328,25 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx) } DTN_INFO("\n=======HUBP FL======\n"); - DTN_INFO( - "HUBP FL: Enabled Done adr_mode width tmz xbar_sel_R xbar_sel_G xbar_sel_B adr_hi adr_low REFCYC Bias Scale Mode Format\n"); + char pLabels[18][50] = { + "inst", "Enabled ", "Done ", "adr_mode ", "width ", "mpc_width ", + "tmz", "xbar_sel_R", "xbar_sel_G", "xbar_sel_B", "adr_hi ", + "adr_low", "REFCYC", "Bias", "Scale", "Mode", + "Format", "prefetch"}; + for (i = 0; i < pool->pipe_count; i++) { struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state); struct dcn_fl_regs_st *fl_regs = &s->fl_regs; + struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr; if (!s->blank_en) { - DTN_INFO("[%2d]: %5xh %6xh %5d %6d %8xh %2xh %6xh %6d %8d %8d %7d %8xh %5x %5x %5x", + uint32_t values[] = { pool->hubps[i]->inst, fl_regs->lut_enable, fl_regs->lut_done, fl_regs->lut_addr_mode, fl_regs->lut_width, + fl_regs->lut_mpc_width, fl_regs->lut_tmz, fl_regs->lut_crossbar_sel_r, fl_regs->lut_crossbar_sel_g, @@ -351,8 +357,13 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx) fl_regs->lut_fl_bias, fl_regs->lut_fl_scale, fl_regs->lut_fl_mode, - fl_regs->lut_fl_format); - DTN_INFO("\n"); + fl_regs->lut_fl_format, + dlg_regs->dst_y_prefetch}; + + int num_elements = 18; + + for (int j = 0; j < num_elements; j++) + DTN_INFO("%s \t %8xh\n", pLabels[j], values[j]); } } @@ -541,19 +552,43 @@ static void dcn10_log_color_state(struct dc *dc, dc->caps.color.mpc.ogam_ram, dc->caps.color.mpc.ocsc); DTN_INFO("===== MPC RMCM 3DLUT =====\n"); - DTN_INFO("MPCC: SIZE MODE MODE_CUR RD_SEL 30BIT_EN WR_EN_MASK RAM_SEL OUT_NORM_FACTOR FL_SEL OUT_OFFSET OUT_SCALE FL_DONE SOFT_UNDERFLOW HARD_UNDERFLOW MEM_PWR_ST FORCE DIS MODE\n"); + char pLabels[19][50] = { + "MPCC", "SIZE", "MODE", "MODE_CUR", "RD_SEL", + "30BIT_EN", "WR_EN_MASK", "RAM_SEL", "OUT_NORM_FACTOR", "FL_SEL", + "OUT_OFFSET", "OUT_SCALE", "FL_DONE", "SOFT_UNDERFLOW", "HARD_UNDERFLOW", + "MEM_PWR_ST", "FORCE", "DIS", "MODE"}; + for (i = 0; i < pool->mpcc_count; i++) { struct mpcc_state s = {0}; pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s); - if (s.opp_id != 0xf) - DTN_INFO("[%2d]: %4xh %4xh %6xh %4x %4x %4x %4x %4x %4xh %4xh %6xh %4x %4x %4x %4x %4x %4x %4x\n", - i, s.rmcm_regs.rmcm_3dlut_size, s.rmcm_regs.rmcm_3dlut_mode, s.rmcm_regs.rmcm_3dlut_mode_cur, - s.rmcm_regs.rmcm_3dlut_read_sel, s.rmcm_regs.rmcm_3dlut_30bit_en, s.rmcm_regs.rmcm_3dlut_wr_en_mask, - s.rmcm_regs.rmcm_3dlut_ram_sel, s.rmcm_regs.rmcm_3dlut_out_norm_factor, s.rmcm_regs.rmcm_3dlut_fl_sel, - s.rmcm_regs.rmcm_3dlut_out_offset_r, s.rmcm_regs.rmcm_3dlut_out_scale_r, s.rmcm_regs.rmcm_3dlut_fl_done, - s.rmcm_regs.rmcm_3dlut_fl_soft_underflow, s.rmcm_regs.rmcm_3dlut_fl_hard_underflow, s.rmcm_regs.rmcm_3dlut_mem_pwr_state, - s.rmcm_regs.rmcm_3dlut_mem_pwr_force, s.rmcm_regs.rmcm_3dlut_mem_pwr_dis, s.rmcm_regs.rmcm_3dlut_mem_pwr_mode); + if (s.opp_id != 0xf) { + uint32_t values[] = { + i, + s.rmcm_regs.rmcm_3dlut_size, + s.rmcm_regs.rmcm_3dlut_mode, + s.rmcm_regs.rmcm_3dlut_mode_cur, + s.rmcm_regs.rmcm_3dlut_read_sel, + s.rmcm_regs.rmcm_3dlut_30bit_en, + s.rmcm_regs.rmcm_3dlut_wr_en_mask, + s.rmcm_regs.rmcm_3dlut_ram_sel, + s.rmcm_regs.rmcm_3dlut_out_norm_factor, + s.rmcm_regs.rmcm_3dlut_fl_sel, + s.rmcm_regs.rmcm_3dlut_out_offset_r, + s.rmcm_regs.rmcm_3dlut_out_scale_r, + s.rmcm_regs.rmcm_3dlut_fl_done, + s.rmcm_regs.rmcm_3dlut_fl_soft_underflow, + s.rmcm_regs.rmcm_3dlut_fl_hard_underflow, + s.rmcm_regs.rmcm_3dlut_mem_pwr_state, + s.rmcm_regs.rmcm_3dlut_mem_pwr_force, + s.rmcm_regs.rmcm_3dlut_mem_pwr_dis, + s.rmcm_regs.rmcm_3dlut_mem_pwr_mode}; + + int num_elements = 19; + + for (int j = 0; j < num_elements; j++) + DTN_INFO("%s \t %8xh\n", pLabels[j], values[j]); + } } DTN_INFO("\n"); DTN_INFO("===== MPC RMCM Shaper =====\n"); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index cee29e89ec5ce..198a28bd8e28d 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -89,7 +89,7 @@ enum hubp_3dlut_fl_addressing_mode { enum hubp_3dlut_fl_width { hubp_3dlut_fl_width_17 = 17, hubp_3dlut_fl_width_33 = 33, - hubp_3dlut_fl_width_transformed = 4916 + hubp_3dlut_fl_width_transformed = 4916, //mpc default }; enum hubp_3dlut_fl_crossbar_bit_slice { @@ -99,6 +99,22 @@ enum hubp_3dlut_fl_crossbar_bit_slice { hubp_3dlut_fl_crossbar_bit_slice_48_63 = 3 }; +struct hubp_fl_3dlut_config { + bool enabled; + enum hubp_3dlut_fl_width width; + enum hubp_3dlut_fl_mode mode; + enum hubp_3dlut_fl_format format; + uint16_t bias; + uint16_t scale; + struct dc_plane_address address; + enum hubp_3dlut_fl_addressing_mode addr_mode; + enum dc_cm2_gpu_mem_layout layout; + uint8_t protection_bits; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b; + enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r; +}; + struct hubp { const struct hubp_funcs *funcs; struct dc_context *ctx; @@ -288,6 +304,7 @@ struct hubp_funcs { enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r); int (*hubp_get_3dlut_fl_done)(struct hubp *hubp); + void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg); void (*hubp_clear_tiling)(struct hubp *hubp); }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index 7641439f6ca06..14f0304e3eb96 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -115,6 +115,16 @@ enum MCM_LUT_ID { MCM_LUT_SHAPER }; +struct mpc_fl_3dlut_config { + bool enabled; + uint16_t width; + bool select_lut_bank_a; + uint16_t bit_depth; + int hubp_index; + uint16_t bias; + uint16_t scale; +}; + union mcm_lut_params { const struct pwl_params *pwl; const struct tetrahedral_params *lut3d; @@ -1098,6 +1108,7 @@ struct mpc_funcs { * MPC RMCM new HW sequential programming functions */ struct { + void (*fl_3dlut_configure)(struct mpc *mpc, struct mpc_fl_3dlut_config *cfg, int mpcc_id); void (*enable_3dlut_fl)(struct mpc *mpc, bool enable, int mpcc_id); void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, From bc717a988bae36d6d5391ac70fe7f1a418c97000 Mon Sep 17 00:00:00 2001 From: Ryan Seto Date: Thu, 24 Jul 2025 14:57:52 -0400 Subject: [PATCH 1636/2653] drm/amd/display: Toggle for Disable Force Pstate Allow on Disable [Why & How] In theory, driver should be able to support disabling force pstate allow after hardware release however this behavior is not tested yet. Introducing a new toggle to disable the force on the fly. Reviewed-by: Dillon Varone Signed-off-by: Ryan Seto Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 36 +++++++++++-------- .../dc/resource/dcn401/dcn401_resource.c | 1 + 3 files changed, 24 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e1f0f5ba69eb7..5029ad8e84e09 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1073,6 +1073,7 @@ struct dc_debug_options { unsigned int force_mall_ss_num_ways; bool alloc_extra_way_for_cursor; uint32_t subvp_extra_lines; + bool disable_force_pstate_allow_on_hw_release; bool force_usr_allow; /* uses value at boot and disables switch */ bool disable_dtb_ref_clk_switch; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index fb949aeb12443..d5b5e2ce6ff63 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1621,20 +1621,28 @@ void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, void dcn401_hardware_release(struct dc *dc) { - dc_dmub_srv_fams2_update_config(dc, dc->current_state, false); - - /* If pstate unsupported, or still supported - * by firmware, force it supported by dcn - */ - if (dc->current_state) { - if ((!dc->clk_mgr->clks.p_state_change_support || - dc->current_state->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) && - dc->res_pool->hubbub->funcs->force_pstate_change_control) - dc->res_pool->hubbub->funcs->force_pstate_change_control( - dc->res_pool->hubbub, true, true); - - dc->current_state->bw_ctx.bw.dcn.clk.p_state_change_support = true; - dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, dc->current_state, true); + if (!dc->debug.disable_force_pstate_allow_on_hw_release) { + dc_dmub_srv_fams2_update_config(dc, dc->current_state, false); + + /* If pstate unsupported, or still supported + * by firmware, force it supported by dcn + */ + if (dc->current_state) { + if ((!dc->clk_mgr->clks.p_state_change_support || + dc->current_state->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) && + dc->res_pool->hubbub->funcs->force_pstate_change_control) + dc->res_pool->hubbub->funcs->force_pstate_change_control( + dc->res_pool->hubbub, true, true); + + dc->current_state->bw_ctx.bw.dcn.clk.p_state_change_support = true; + dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, dc->current_state, true); + } + } else { + if (dc->current_state) { + dc->clk_mgr->clks.p_state_change_support = false; + dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, dc->current_state, true); + } + dc_dmub_srv_fams2_update_config(dc, dc->current_state, false); } } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index b3988e38d0a63..068c123ea8a8a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -708,6 +708,7 @@ static const struct dc_debug_options debug_defaults_drv = { }, .use_max_lb = true, .force_disable_subvp = false, + .disable_force_pstate_allow_on_hw_release = false, .exit_idle_opt_for_cursor_updates = true, .using_dml2 = true, .using_dml21 = true, From 319c6110f4d77300e6a0053b31f6a258ddfd317d Mon Sep 17 00:00:00 2001 From: Muhammad Ahmed Date: Thu, 24 Jul 2025 21:50:25 -0400 Subject: [PATCH 1637/2653] drm/amd/display: Adding interface to log hw state when underflow happens [why] Will help us better debug underflow issues. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Muhammad Ahmed Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 18 +++++++ drivers/gpu/drm/amd/display/dc/dc.h | 30 ++++++++++++ .../display/dc/hubbub/dcn30/dcn30_hubbub.c | 31 ++++++++++++ .../display/dc/hubbub/dcn30/dcn30_hubbub.h | 6 +++ .../display/dc/hubbub/dcn31/dcn31_hubbub.c | 2 + .../display/dc/hubbub/dcn32/dcn32_hubbub.c | 2 + .../display/dc/hubbub/dcn35/dcn35_hubbub.c | 2 + .../display/dc/hubbub/dcn401/dcn401_hubbub.c | 2 + .../amd/display/dc/hubp/dcn10/dcn10_hubp.h | 8 +++- .../amd/display/dc/hubp/dcn30/dcn30_hubp.c | 26 ++++++++++ .../amd/display/dc/hubp/dcn30/dcn30_hubp.h | 8 +++- .../amd/display/dc/hubp/dcn31/dcn31_hubp.c | 15 ++++++ .../amd/display/dc/hubp/dcn31/dcn31_hubp.h | 6 ++- .../amd/display/dc/hubp/dcn32/dcn32_hubp.c | 3 ++ .../amd/display/dc/hubp/dcn35/dcn35_hubp.c | 3 ++ .../amd/display/dc/hubp/dcn401/dcn401_hubp.c | 3 ++ .../amd/display/dc/hubp/dcn401/dcn401_hubp.h | 4 +- .../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 48 +++++++++++++++++++ .../amd/display/dc/hwss/dcn30/dcn30_hwseq.h | 5 ++ .../amd/display/dc/hwss/dcn30/dcn30_init.c | 1 + .../amd/display/dc/hwss/dcn31/dcn31_init.c | 1 + .../amd/display/dc/hwss/dcn314/dcn314_init.c | 1 + .../amd/display/dc/hwss/dcn32/dcn32_init.c | 1 + .../amd/display/dc/hwss/dcn35/dcn35_init.c | 1 + .../amd/display/dc/hwss/dcn351/dcn351_init.c | 1 + .../amd/display/dc/hwss/dcn401/dcn401_init.c | 1 + .../drm/amd/display/dc/hwss/hw_sequencer.h | 4 ++ .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 2 + drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 2 + .../dc/resource/dcn32/dcn32_resource.h | 3 +- .../dc/resource/dcn401/dcn401_resource.h | 3 +- 31 files changed, 236 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index b9d9ba1706628..afafcdc9e53d9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -6340,3 +6340,21 @@ bool dc_can_clear_cursor_limit(struct dc *dc) return false; } + +void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, + struct dc_underflow_debug_data *out_data) +{ + struct timing_generator *tg = NULL; + + for (int i = 0; i < MAX_PIPES; i++) { + if (dc->res_pool->timing_generators[i] && + dc->res_pool->timing_generators[i]->inst == primary_otg_inst) { + tg = dc->res_pool->timing_generators[i]; + break; + } + } + + dc_exit_ips_for_hw_access(dc); + if (dc->hwss.get_underflow_debug_data) + dc->hwss.get_underflow_debug_data(dc, tg, out_data); +} diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5029ad8e84e09..87c93b18f930e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1822,6 +1822,23 @@ struct dc_surface_update { struct dc_bias_and_scale bias_and_scale; }; +struct dc_underflow_debug_data { + uint32_t otg_inst; + uint32_t otg_underflow; + uint32_t h_position; + uint32_t v_position; + uint32_t otg_frame_count; + struct dc_underflow_per_hubp_debug_data { + uint32_t hubp_underflow; + uint32_t hubp_in_blank; + uint32_t hubp_readline; + uint32_t det_config_error; + } hubps[MAX_PIPES]; + uint32_t curr_det_sizes[MAX_PIPES]; + uint32_t target_det_sizes[MAX_PIPES]; + uint32_t compbuf_config_error; +}; + /* * Create a new surface with default parameters; */ @@ -2716,4 +2733,17 @@ bool dc_is_timing_changed(struct dc_stream_state *cur_stream, bool dc_is_cursor_limit_pending(struct dc *dc); bool dc_can_clear_cursor_limit(struct dc *dc); +/** + * dc_get_underflow_debug_data_for_otg() - Retrieve underflow debug data. + * + * @dc: Pointer to the display core context. + * @primary_otg_inst: Instance index of the primary OTG that underflowed. + * @out_data: Pointer to a dc_underflow_debug_data struct to be filled with debug information. + * + * This function collects and logs underflow-related HW states when underflow happens, + * including OTG underflow status, current read positions, frame count, and per-HUBP debug data. + * The results are stored in the provided out_data structure for further analysis or logging. + */ +void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data); + #endif /* DC_INTERFACE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c index d347bb06577ac..e7e5f6d4778e0 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c @@ -440,6 +440,35 @@ void hubbub3_init_watermarks(struct hubbub *hubbub) REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, reg); } +void hubbub3_get_det_sizes(struct hubbub *hubbub, uint32_t *curr_det_sizes, uint32_t *target_det_sizes) +{ + struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); + + REG_GET_2(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, &curr_det_sizes[0], + DET0_SIZE, &target_det_sizes[0]); + + REG_GET_2(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, &curr_det_sizes[1], + DET1_SIZE, &target_det_sizes[1]); + + REG_GET_2(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, &curr_det_sizes[2], + DET2_SIZE, &target_det_sizes[2]); + + REG_GET_2(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, &curr_det_sizes[3], + DET3_SIZE, &target_det_sizes[3]); + +} + +uint32_t hubbub3_compbuf_config_error(struct hubbub *hubbub) +{ + struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); + uint32_t compbuf_config_error = 0; + + REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, + &compbuf_config_error); + + return compbuf_config_error; +} + static const struct hubbub_funcs hubbub30_funcs = { .update_dchub = hubbub2_update_dchub, .init_dchub_sys_ctx = hubbub3_init_dchub_sys_ctx, @@ -457,6 +486,8 @@ static const struct hubbub_funcs hubbub30_funcs = { .force_pstate_change_control = hubbub3_force_pstate_change_control, .init_watermarks = hubbub3_init_watermarks, .hubbub_read_state = hubbub2_read_state, + .get_det_sizes = hubbub3_get_det_sizes, + .compbuf_config_error = hubbub3_compbuf_config_error, }; void hubbub3_construct(struct dcn20_hubbub *hubbub3, diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h index ca6233e8f1f44..49a469969d361 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h @@ -133,4 +133,10 @@ void hubbub3_force_pstate_change_control(struct hubbub *hubbub, void hubbub3_init_watermarks(struct hubbub *hubbub); +void hubbub3_get_det_sizes(struct hubbub *hubbub, + uint32_t *curr_det_sizes, + uint32_t *target_det_sizes); + +uint32_t hubbub3_compbuf_config_error(struct hubbub *hubbub); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c index b98505b240a79..cdb20251a1549 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c @@ -1071,6 +1071,8 @@ static const struct hubbub_funcs hubbub31_funcs = { .program_compbuf_size = dcn31_program_compbuf_size, .init_crb = dcn31_init_crb, .hubbub_read_state = hubbub2_read_state, + .get_det_sizes = hubbub3_get_det_sizes, + .compbuf_config_error = hubbub3_compbuf_config_error, }; void hubbub31_construct(struct dcn20_hubbub *hubbub31, diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c index 32a6be543105c..92957398ac0a6 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c @@ -1009,6 +1009,8 @@ static const struct hubbub_funcs hubbub32_funcs = { .force_usr_retraining_allow = hubbub32_force_usr_retraining_allow, .set_request_limit = hubbub32_set_request_limit, .get_mall_en = hubbub32_get_mall_en, + .get_det_sizes = hubbub3_get_det_sizes, + .compbuf_config_error = hubbub3_compbuf_config_error, }; void hubbub32_construct(struct dcn20_hubbub *hubbub2, diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c index 6d41953011f52..a443722a8632c 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c @@ -589,6 +589,8 @@ static const struct hubbub_funcs hubbub35_funcs = { .hubbub_read_state = hubbub2_read_state, .force_usr_retraining_allow = hubbub32_force_usr_retraining_allow, .dchubbub_init = hubbub35_init, + .get_det_sizes = hubbub3_get_det_sizes, + .compbuf_config_error = hubbub3_compbuf_config_error, }; void hubbub35_construct(struct dcn20_hubbub *hubbub2, diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c index 92fab471b1836..a36273a528808 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c @@ -1247,6 +1247,8 @@ static const struct hubbub_funcs hubbub4_01_funcs = { .program_compbuf_segments = dcn401_program_compbuf_segments, .wait_for_det_update = dcn401_wait_for_det_update, .program_arbiter = dcn401_program_arbiter, + .get_det_sizes = hubbub3_get_det_sizes, + .compbuf_config_error = hubbub3_compbuf_config_error, }; void hubbub401_construct(struct dcn20_hubbub *hubbub2, diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h index 0b7547d5b4882..cf2eb9793008d 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h @@ -104,7 +104,8 @@ SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\ SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\ SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\ - SRI(HUBP_CLK_CNTL, HUBP, id) + SRI(HUBP_CLK_CNTL, HUBP, id),\ + SRI(HUBPRET_READ_LINE_VALUE, HUBPRET, id) /* Register address initialization macro for ASICs with VM */ #define HUBP_REG_LIST_DCN_VM(id)\ @@ -249,7 +250,8 @@ uint32_t CURSOR_POSITION; \ uint32_t CURSOR_HOT_SPOT; \ uint32_t CURSOR_DST_OFFSET; \ - uint32_t HUBP_CLK_CNTL + uint32_t HUBP_CLK_CNTL; \ + uint32_t HUBPRET_READ_LINE_VALUE #define HUBP_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -622,6 +624,8 @@ type DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\ type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\ type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\ + type PIPE_READ_LINE;\ + type HUBP_SEG_ALLOC_ERR_STATUS;\ /* todo: get these from GVM instead of reading registers ourselves */\ type PAGE_DIRECTORY_ENTRY_HI32;\ type PAGE_DIRECTORY_ENTRY_LO32;\ diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c index 0da70b50e86d4..556214b2227da 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c @@ -505,6 +505,30 @@ void hubp3_init(struct hubp *hubp) hubp_reset(hubp); } +uint32_t hubp3_get_current_read_line(struct hubp *hubp) +{ + uint32_t read_line = 0; + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_GET(HUBPRET_READ_LINE_VALUE, + PIPE_READ_LINE, + &read_line); + + return read_line; +} + +unsigned int hubp3_get_underflow_status(struct hubp *hubp) +{ + uint32_t hubp_underflow = 0; + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_GET(DCHUBP_CNTL, + HUBP_UNDERFLOW_STATUS, + &hubp_underflow); + + return hubp_underflow; +} + static struct hubp_funcs dcn30_hubp_funcs = { .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, @@ -534,6 +558,8 @@ static struct hubp_funcs dcn30_hubp_funcs = { .hubp_soft_reset = hubp1_soft_reset, .hubp_set_flip_int = hubp1_set_flip_int, .hubp_clear_tiling = hubp3_clear_tiling, + .hubp_get_underflow_status = hubp3_get_underflow_status, + .hubp_get_current_read_line = hubp3_get_current_read_line, }; bool hubp3_construct( diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h index b7d7adf0b58cd..842f4eb72cc82 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h @@ -243,7 +243,8 @@ HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\ HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\ HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh) + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh),\ + HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_VALUE, PIPE_READ_LINE, mask_sh) bool hubp3_construct( struct dcn20_hubp *hubp2, @@ -299,6 +300,11 @@ void hubp3_init(struct hubp *hubp); void hubp3_clear_tiling(struct hubp *hubp); +uint32_t hubp3_get_current_read_line(struct hubp *hubp); + +uint32_t hubp3_get_underflow_status(struct hubp *hubp); + + #endif /* __DC_HUBP_DCN30_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c index 7fd582a8a4ba9..47101847c2b7b 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c @@ -68,6 +68,18 @@ void hubp31_program_extended_blank_value( hubp31_program_extended_blank(hubp, min_dst_y_next_start_optimized); } +uint32_t hubp31_get_det_config_error(struct hubp *hubp) +{ + uint32_t config_error = 0; + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_GET(DCHUBP_CNTL, + HUBP_SEG_ALLOC_ERR_STATUS, + &config_error); + + return config_error; +} + static struct hubp_funcs dcn31_hubp_funcs = { .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, @@ -98,6 +110,9 @@ static struct hubp_funcs dcn31_hubp_funcs = { .hubp_in_blank = hubp1_in_blank, .program_extended_blank = hubp31_program_extended_blank, .hubp_clear_tiling = hubp3_clear_tiling, + .hubp_get_underflow_status = hubp3_get_underflow_status, + .hubp_get_current_read_line = hubp3_get_current_read_line, + .hubp_get_det_config_error = hubp31_get_det_config_error, }; bool hubp31_construct( diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h index d688db79b750f..5952c46715076 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.h @@ -228,7 +228,9 @@ HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\ HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\ HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh) + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh),\ + HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_VALUE, PIPE_READ_LINE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SEG_ALLOC_ERR_STATUS, mask_sh) bool hubp31_construct( @@ -246,4 +248,6 @@ void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable); void hubp31_program_extended_blank_value( struct hubp *hubp, unsigned int min_dst_y_next_start_optimized); +uint32_t hubp31_get_det_config_error(struct hubp *hubp); + #endif /* __DC_HUBP_DCN31_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c index f3a21c623f441..a5f23bb2a76a1 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c @@ -206,6 +206,9 @@ static struct hubp_funcs dcn32_hubp_funcs = { .hubp_update_mall_sel = hubp32_update_mall_sel, .hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering, .hubp_clear_tiling = hubp3_clear_tiling, + .hubp_get_underflow_status = hubp3_get_underflow_status, + .hubp_get_current_read_line = hubp3_get_current_read_line, + .hubp_get_det_config_error = hubp31_get_det_config_error, }; bool hubp32_construct( diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c index 6d060ba12da81..b140808f21aff 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c @@ -218,6 +218,9 @@ static struct hubp_funcs dcn35_hubp_funcs = { .hubp_in_blank = hubp1_in_blank, .program_extended_blank = hubp31_program_extended_blank_value, .hubp_clear_tiling = hubp3_clear_tiling, + .hubp_get_underflow_status = hubp3_get_underflow_status, + .hubp_get_current_read_line = hubp3_get_current_read_line, + .hubp_get_det_config_error = hubp31_get_det_config_error, }; bool hubp35_construct( diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c index 5028180ad80af..0fcbc6a35be67 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c @@ -1071,6 +1071,9 @@ static struct hubp_funcs dcn401_hubp_funcs = { .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done, .hubp_clear_tiling = hubp401_clear_tiling, .hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config, + .hubp_get_underflow_status = hubp3_get_underflow_status, + .hubp_get_current_read_line = hubp3_get_current_read_line, + .hubp_get_det_config_error = hubp31_get_det_config_error, }; bool hubp401_construct( diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h index 887b479ed1d79..fdabbeec8ffa3 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h @@ -252,7 +252,9 @@ HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_1H_P0, mask_sh),\ HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_2H_P0, mask_sh),\ HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_1H_P1, mask_sh),\ - HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_2H_P1, mask_sh) + HUBP_SF(HUBP0_DCHUBP_MCACHEID_CONFIG, MCACHEID_MALL_PREF_2H_P1, mask_sh),\ + HUBP_SF(HUBPRET0_HUBPRET_READ_LINE_VALUE, PIPE_READ_LINE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SEG_ALLOC_ERR_STATUS, mask_sh) void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index 37a239219dfe0..139a63101488d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -1228,3 +1228,51 @@ void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx) } } } + +void dcn30_get_underflow_debug_data(const struct dc *dc, + struct timing_generator *tg, + struct dc_underflow_debug_data *out_data) +{ + struct hubbub *hubbub = dc->res_pool->hubbub; + + if (tg) { + uint32_t v_blank_start = 0, v_blank_end = 0; + + out_data->otg_inst = tg->inst; + + tg->funcs->get_scanoutpos(tg, + &v_blank_start, + &v_blank_end, + &out_data->h_position, + &out_data->v_position); + + out_data->otg_frame_count = tg->funcs->get_frame_count(tg); + + out_data->otg_underflow = tg->funcs->is_optc_underflow_occurred(tg); + } + + for (int i = 0; i < MAX_PIPES; i++) { + struct hubp *hubp = dc->res_pool->hubps[i]; + + if (hubp) { + if (hubp->funcs->hubp_get_underflow_status) + out_data->hubps[i].hubp_underflow = hubp->funcs->hubp_get_underflow_status(hubp); + + if (hubp->funcs->hubp_in_blank) + out_data->hubps[i].hubp_in_blank = hubp->funcs->hubp_in_blank(hubp); + + if (hubp->funcs->hubp_get_current_read_line) + out_data->hubps[i].hubp_readline = hubp->funcs->hubp_get_current_read_line(hubp); + + if (hubp->funcs->hubp_get_det_config_error) + out_data->hubps[i].det_config_error = hubp->funcs->hubp_get_det_config_error(hubp); + } + } + + if (hubbub->funcs->get_det_sizes) + hubbub->funcs->get_det_sizes(hubbub, out_data->curr_det_sizes, out_data->target_det_sizes); + + if (hubbub->funcs->compbuf_config_error) + out_data->compbuf_config_error = hubbub->funcs->compbuf_config_error(hubbub); + +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h index 4b90b781c4f2d..40afbbfb5b9c3 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h @@ -29,6 +29,7 @@ #include "hw_sequencer_private.h" struct dc; +struct dc_underflow_debug_data; void dcn30_init_hw(struct dc *dc); void dcn30_program_all_writeback_pipes_in_tree( @@ -98,4 +99,8 @@ void dcn30_prepare_bandwidth(struct dc *dc, void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx); +void dcn30_get_underflow_debug_data(const struct dc *dc, + struct timing_generator *tg, + struct dc_underflow_debug_data *out_data); + #endif /* __DC_HWSS_DCN30_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c index 2ac5d54d16269..d7ff55669bac0 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c @@ -110,6 +110,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = { .update_visual_confirm_color = dcn10_update_visual_confirm_color, .is_abm_supported = dcn21_is_abm_supported, .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, + .get_underflow_debug_data = dcn30_get_underflow_debug_data, }; static const struct hwseq_private_funcs dcn30_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c index 556f4fe57eda7..5a6a459da224a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c @@ -112,6 +112,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = { .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, .update_visual_confirm_color = dcn10_update_visual_confirm_color, .setup_hpo_hw_control = dcn31_setup_hpo_hw_control, + .get_underflow_debug_data = dcn30_get_underflow_debug_data, }; static const struct hwseq_private_funcs dcn31_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c index f5112742edf9b..a99145a302306 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c @@ -115,6 +115,7 @@ static const struct hw_sequencer_funcs dcn314_funcs = { .update_visual_confirm_color = dcn10_update_visual_confirm_color, .calculate_pix_rate_divider = dcn314_calculate_pix_rate_divider, .setup_hpo_hw_control = dcn31_setup_hpo_hw_control, + .get_underflow_debug_data = dcn30_get_underflow_debug_data, }; static const struct hwseq_private_funcs dcn314_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c index b971356d30b18..c19ef075c8823 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c @@ -121,6 +121,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = { .calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider, .program_outstanding_updates = dcn32_program_outstanding_updates, .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, + .get_underflow_debug_data = dcn30_get_underflow_debug_data, }; static const struct hwseq_private_funcs dcn32_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c index a3ccf805bd16a..52cc488416ac1 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c @@ -128,6 +128,7 @@ static const struct hw_sequencer_funcs dcn35_funcs = { .enable_plane = dcn20_enable_plane, .update_dchubp_dpp = dcn20_update_dchubp_dpp, .post_unlock_reset_opp = dcn20_post_unlock_reset_opp, + .get_underflow_debug_data = dcn30_get_underflow_debug_data, }; static const struct hwseq_private_funcs dcn35_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c index 58f2be2a326b8..e34efcb7bde5e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c @@ -123,6 +123,7 @@ static const struct hw_sequencer_funcs dcn351_funcs = { .set_long_vtotal = dcn35_set_long_vblank, .calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider, .setup_hpo_hw_control = dcn35_setup_hpo_hw_control, + .get_underflow_debug_data = dcn30_get_underflow_debug_data, }; static const struct hwseq_private_funcs dcn351_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c index fe7aceb2f5104..d6e11b7e4fcef 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c @@ -104,6 +104,7 @@ static const struct hw_sequencer_funcs dcn401_funcs = { .enable_plane = dcn20_enable_plane, .update_dchubp_dpp = dcn20_update_dchubp_dpp, .post_unlock_reset_opp = dcn20_post_unlock_reset_opp, + .get_underflow_debug_data = dcn30_get_underflow_debug_data, }; static const struct hwseq_private_funcs dcn401_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index 9df8030e37f79..1723bbcf2c46a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -47,6 +47,7 @@ struct link_resource; struct dc_dmub_cmd; struct pg_block_update; struct drr_params; +struct dc_underflow_debug_data; struct subvp_pipe_control_lock_fast_params { struct dc *dc; @@ -475,6 +476,9 @@ struct hw_sequencer_funcs { struct dc_state *context); void (*post_unlock_reset_opp)(struct dc *dc, struct pipe_ctx *opp_head); + void (*get_underflow_debug_data)(const struct dc *dc, + struct timing_generator *tg, + struct dc_underflow_debug_data *out_data); }; void color_space_to_black_color( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h index 52b745667ef75..9bee45b36629d 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h @@ -229,6 +229,8 @@ struct hubbub_funcs { void (*program_compbuf_segments)(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase); void (*wait_for_det_update)(struct hubbub *hubbub, int hubp_inst); bool (*program_arbiter)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower); + void (*get_det_sizes)(struct hubbub *hubbub, uint32_t *curr_det_sizes, uint32_t *target_det_sizes); + uint32_t (*compbuf_config_error)(struct hubbub *hubbub); }; struct hubbub { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index 198a28bd8e28d..2b874d2cc61c5 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -306,6 +306,8 @@ struct hubp_funcs { int (*hubp_get_3dlut_fl_done)(struct hubp *hubp); void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg); void (*hubp_clear_tiling)(struct hubp *hubp); + uint32_t (*hubp_get_current_read_line)(struct hubp *hubp); + uint32_t (*hubp_get_det_config_error)(struct hubp *hubp); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h index 82f966cf4ed27..20d7145960212 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h @@ -1141,7 +1141,8 @@ unsigned int dcn32_get_max_hw_cursor_size(const struct dc *dc, SRI_ARR(DCN_SURF1_TTU_CNTL1, HUBPREQ, id), \ SRI_ARR(DCN_CUR0_TTU_CNTL0, HUBPREQ, id), \ SRI_ARR(DCN_CUR0_TTU_CNTL1, HUBPREQ, id), \ - SRI_ARR(HUBP_CLK_CNTL, HUBP, id) + SRI_ARR(HUBP_CLK_CNTL, HUBP, id), \ + SRI_ARR(HUBPRET_READ_LINE_VALUE, HUBPRET, id) #define HUBP_REG_LIST_DCN2_COMMON_RI(id) \ HUBP_REG_LIST_DCN_RI(id), HUBP_REG_LIST_DCN_VM_RI(id), \ SRI_ARR(PREFETCH_SETTINGS, HUBPREQ, id), \ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h index 2ae6831c31eff..0fc66487d8007 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h @@ -140,7 +140,8 @@ void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context); SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id), \ HUBP_3DLUT_FL_REG_LIST_DCN401(id), \ SRI_ARR(DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, HUBP, id), \ - SRI_ARR(DCHUBP_MCACHEID_CONFIG, HUBP, id) + SRI_ARR(DCHUBP_MCACHEID_CONFIG, HUBP, id), \ + SRI_ARR(HUBPRET_READ_LINE_VALUE, HUBPRET, id) /* ABM */ #define ABM_DCN401_REG_LIST_RI(id) \ From 15f6153e684354ac34819f3b89e7260932124188 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 25 Jul 2025 17:14:58 -0500 Subject: [PATCH 1638/2653] drm/amd/display: Promote DC to 3.2.344 Summary: * Add interface to log hw state when underflow happens * Fix hubp programming of 3dlut fast load * Avoid Read Remote DPCD Many Times * More liberal vmin/vmax update for freesync * Fix dmub access race condition Acked-by: Sun peng (Leo) Li Signed-off-by: Taimur Hassan Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 87c93b18f930e..f4b5c1ff47671 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.343" +#define DC_VER "3.2.344" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From 2a5df84fdf57c68ecc1ea052ffea205c5dcfe2be Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 18 Jul 2025 09:25:21 +0530 Subject: [PATCH 1639/2653] drm/amdgpu: Add NULL check for asic_funcs If driver load fails too early, asic_funcs pointer remains unassigned. Add NULL check to sanitize unwind path. Signed-off-by: Lijo Lazar Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c index e56ba93a8df64..a974265837f0d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c @@ -55,7 +55,8 @@ u64 amdgpu_nbio_get_pcie_replay_count(struct amdgpu_device *adev) bool amdgpu_nbio_is_replay_cnt_supported(struct amdgpu_device *adev) { - if (amdgpu_sriov_vf(adev) || !adev->asic_funcs->get_pcie_replay_count || + if (amdgpu_sriov_vf(adev) || !adev->asic_funcs || + !adev->asic_funcs->get_pcie_replay_count || (!adev->nbio.funcs || !adev->nbio.funcs->get_pcie_replay_count)) return false; From 3cd271a01b82aa9768bb3a9734c02b5aa69c40c0 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 11 Jul 2025 12:15:45 +0530 Subject: [PATCH 1640/2653] drm/amd/pm: Use cached metrics data on aldebaran Cached metrics data validity is 1ms on aldebaran. It's not reasonable for any client to query gpu_metrics at a faster rate and constantly interrupt PMFW. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index c63d2e28954d0..b067147b7c41f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -1781,7 +1781,7 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, ret = smu_cmn_get_metrics_table(smu, &metrics, - true); + false); if (ret) return ret; From 2365dfbddff8317d0eb809807f3f953e98594de0 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 11 Jul 2025 12:18:04 +0530 Subject: [PATCH 1641/2653] drm/amd/pm: Use cached metrics data on arcturus Cached metrics data validity is 1ms on arcturus. It's not reasonable for any client to query gpu_metrics at a faster rate and constantly interrupt PMFW. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c index 9ad46f545d15c..599eddb5a67d5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c @@ -1897,7 +1897,7 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, ret = smu_cmn_get_metrics_table(smu, &metrics, - true); + false); if (ret) return ret; From 8283525c58dd80dbc87c2d00df366cb8f5d1df32 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Mon, 4 Aug 2025 14:50:28 +0800 Subject: [PATCH 1642/2653] drm/amdkcl: add kcl_cleanup support to amdgpu_xcp module it's caused by ef49fe639b "drm/amd/amdgpu: Release xcp drm memory after unplug" Signed-off-by: Yang Su Reviewed-by: Chengjun Yao --- drivers/gpu/drm/amd/amdxcp/backport/backport.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdxcp/backport/backport.h b/drivers/gpu/drm/amd/amdxcp/backport/backport.h index 155f55d669456..d23a4e6be9d11 100644 --- a/drivers/gpu/drm/amd/amdxcp/backport/backport.h +++ b/drivers/gpu/drm/amd/amdxcp/backport/backport.h @@ -1 +1,3 @@ #include "kcl/kcl_amdgpu_drm_drv.h" +#include "kcl/kcl_cleanup.h" +#include "kcl/kcl_mutex.h" From 36df3bbfd05592c64634b9f6f6cde96cc88618fa Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Mon, 4 Aug 2025 08:43:15 +0800 Subject: [PATCH 1643/2653] drm/amdgpu: Update SDMA firmware version check for user queue support This commit fixes a firmware version check for enabling user queue support in SDMA v7.0. The previous version check (7836028) was incorrect and could lead to issues with PROTECTED_FENCE_SIGNAL commands causing register conflicts between MCU_DBG0 and MCU_DBG1. Fixes: 71f82efdc1ad ("drm/amdgpu/sdma7: add ucode version checks for userq support") Reviewed-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index 5d0f6f8d506fc..64139cbe8fd2d 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1353,7 +1353,7 @@ static int sdma_v7_0_sw_init(struct amdgpu_ip_block *ip_block) switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { case IP_VERSION(7, 0, 0): case IP_VERSION(7, 0, 1): - if ((adev->sdma.instance[0].fw_version >= 7836028) && !adev->sdma.disable_uq) + if ((adev->sdma.instance[0].fw_version >= 7966358) && !adev->sdma.disable_uq) adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; break; default: From 3c9a947015c91ba0f7575863343621b23dd42440 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 7 Jul 2025 10:45:28 +0800 Subject: [PATCH 1644/2653] drm/amdgpu: Fix build error when CONFIG_SUSPEND is disabled The variable `pm_suspend_target_state` is conditionally defined only when `CONFIG_SUSPEND` is enabled (see `include/linux/suspend.h`). Directly referencing it without guarding by `#ifdef CONFIG_SUSPEND` causes build failures when suspend functionality is disabled (e.g., `CONFIG_SUSPEND=n`). Reviewed-by: Lijo Lazar Signed-off-by: Perry Yuan --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index e16a384466c9d..19036ea36fe8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2659,6 +2659,7 @@ static int amdgpu_pmops_suspend(struct device *dev) adev->in_s3 = true; if (!adev->in_s0ix && !adev->in_s3) { #ifdef HAVE_PM_SUSPEND_TARGET_STATE +#if IS_ENABLED(CONFIG_SUSPEND) /* don't allow going deep first time followed by s2idle the next time */ if (adev->last_suspend_state != PM_SUSPEND_ON && adev->last_suspend_state != pm_suspend_target_state) { @@ -2666,13 +2667,16 @@ static int amdgpu_pmops_suspend(struct device *dev) pm_suspend_target_state); return -EINVAL; } +#endif #endif return 0; } #ifdef HAVE_PM_SUSPEND_TARGET_STATE +#if IS_ENABLED(CONFIG_SUSPEND) /* cache the state last used for suspend */ adev->last_suspend_state = pm_suspend_target_state; +#endif #endif return amdgpu_device_suspend(drm_dev, true); From a580179892f3e8f0d6d6917a8be20c7d232b1353 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 1 Aug 2025 23:42:01 +0530 Subject: [PATCH 1645/2653] drm/amd/pm: Allow static metrics table query in VF Allow statics metrics table to be queried on SMUv13.0.6 SOCs in VF mode. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index aa5f285184c55..dd04fe4177172 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -185,6 +185,7 @@ static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COU MSG_MAP(SetPhsDetWRbwAlpha, PPSMC_MSG_SetPhsDetWRbwAlpha, 0), MSG_MAP(SetPhsDetOnOff, PPSMC_MSG_SetPhsDetOnOff, 0), MSG_MAP(GetPhsDetResidency, PPSMC_MSG_GetPhsDetResidency, 0), + MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 1), }; // clang-format on From 607e781ab2c649c51e896c1892f08f22cde7dc30 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 24 Jul 2025 12:52:56 +0530 Subject: [PATCH 1646/2653] drm/amdgpu: Add wrapper function for dpc state Use wrapper functions to set/indicate dpc status. Signed-off-by: Lijo Lazar Reviewed-by: Ce Sun --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 17 ++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 11 +++++++++++ 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 39cf5d19bffc0..02bcdc6a7635b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5752,7 +5752,7 @@ int amdgpu_device_link_reset(struct amdgpu_device *adev) dev_info(adev->dev, "GPU link reset\n"); - if (!adev->pcie_reset_ctx.occurs_dpc) + if (!amdgpu_reset_in_dpc(adev)) ret = amdgpu_dpm_link_reset(adev); if (ret) @@ -6205,7 +6205,7 @@ static void amdgpu_device_recovery_prepare(struct amdgpu_device *adev, list_add_tail(&tmp_adev->reset_list, device_list); if (adev->shutdown) tmp_adev->shutdown = true; - if (adev->pcie_reset_ctx.occurs_dpc) + if (amdgpu_reset_in_dpc(adev)) tmp_adev->pcie_reset_ctx.in_link_reset = true; } if (!list_is_first(&adev->reset_list, device_list)) @@ -6281,9 +6281,8 @@ static void amdgpu_device_halt_activities(struct amdgpu_device *adev, drm_client_dev_suspend(adev_to_drm(tmp_adev), false); /* disable ras on ALL IPs */ - if (!need_emergency_restart && - (!adev->pcie_reset_ctx.occurs_dpc) && - amdgpu_device_ip_need_full_reset(tmp_adev)) + if (!need_emergency_restart && !amdgpu_reset_in_dpc(adev) && + amdgpu_device_ip_need_full_reset(tmp_adev)) amdgpu_ras_suspend(tmp_adev); for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { @@ -6311,10 +6310,10 @@ static int amdgpu_device_asic_reset(struct amdgpu_device *adev, retry: /* Rest of adevs pre asic reset from XGMI hive. */ list_for_each_entry(tmp_adev, device_list, reset_list) { - if (adev->pcie_reset_ctx.occurs_dpc) + if (amdgpu_reset_in_dpc(adev)) tmp_adev->no_hw_access = true; r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context); - if (adev->pcie_reset_ctx.occurs_dpc) + if (amdgpu_reset_in_dpc(adev)) tmp_adev->no_hw_access = false; /*TODO Should we stop ?*/ if (r) { @@ -6965,7 +6964,7 @@ pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_sta if (hive) mutex_lock(&hive->hive_lock); - adev->pcie_reset_ctx.occurs_dpc = true; + amdgpu_reset_set_dpc_status(adev, true); memset(&reset_context, 0, sizeof(reset_context)); INIT_LIST_HEAD(&device_list); @@ -7128,7 +7127,7 @@ void amdgpu_pci_resume(struct pci_dev *pdev) amdgpu_device_sched_resume(&device_list, NULL, NULL); amdgpu_device_gpu_resume(adev, &device_list, false); amdgpu_device_recovery_put_reset_lock(adev, &device_list); - adev->pcie_reset_ctx.occurs_dpc = false; + amdgpu_reset_set_dpc_status(adev, false); if (hive) { mutex_unlock(&hive->hive_lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h index 5ae71c0d5aecd..0f7e5ed50c144 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h @@ -176,4 +176,15 @@ int amdgpu_reset_do_xgmi_reset_on_init( bool amdgpu_reset_in_recovery(struct amdgpu_device *adev); +static inline void amdgpu_reset_set_dpc_status(struct amdgpu_device *adev, + bool status) +{ + adev->pcie_reset_ctx.occurs_dpc = status; +} + +static inline bool amdgpu_reset_in_dpc(struct amdgpu_device *adev) +{ + return adev->pcie_reset_ctx.occurs_dpc; +} + #endif From 74d15b47468bd37f92458014ac9cf3d4ade4f3d5 Mon Sep 17 00:00:00 2001 From: Xiang Liu Date: Thu, 31 Jul 2025 14:28:26 +0800 Subject: [PATCH 1647/2653] drm/amdgpu: Fix jpeg v4.0.3 poison irq call trace on sriov guest Sriov guest side doesn't init ras feature hence the poison irq shouldn't be put during hw fini. Fixes: 810a6a2de64d ("drm/amdgpu: Register aqua vanjaram jpeg poison irq") [25209.467154] Call Trace: [25209.467156] [25209.467158] ? srso_alias_return_thunk+0x5/0x7f [25209.467162] ? show_trace_log_lvl+0x28e/0x2ea [25209.467166] ? show_trace_log_lvl+0x28e/0x2ea [25209.467171] ? jpeg_v4_0_3_hw_fini+0x6f/0x90 [amdgpu] [25209.467300] ? show_regs.part.0+0x23/0x29 [25209.467303] ? show_regs.cold+0x8/0xd [25209.467304] ? amdgpu_irq_put+0x9e/0xc0 [amdgpu] [25209.467403] ? __warn+0x8c/0x100 [25209.467407] ? amdgpu_irq_put+0x9e/0xc0 [amdgpu] [25209.467503] ? report_bug+0xa4/0xd0 [25209.467508] ? handle_bug+0x39/0x90 [25209.467511] ? exc_invalid_op+0x19/0x70 [25209.467513] ? asm_exc_invalid_op+0x1b/0x20 [25209.467518] ? amdgpu_irq_put+0x9e/0xc0 [amdgpu] [25209.467613] ? amdgpu_irq_put+0x5f/0xc0 [amdgpu] [25209.467709] jpeg_v4_0_3_hw_fini+0x6f/0x90 [amdgpu] [25209.467805] amdgpu_ip_block_hw_fini+0x34/0x61 [amdgpu] [25209.467971] amdgpu_device_fini_hw+0x3b3/0x467 [amdgpu] Signed-off-by: Xiang Liu Reviewed-by: Stanley.Yang --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index b86288a69e7b7..a78144773fabb 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -444,7 +444,7 @@ static int jpeg_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) ret = jpeg_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE); } - if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) + if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG) && !amdgpu_sriov_vf(adev)) amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0); return ret; From 2e208815cb382f5c65b612b2e04d5e411c36c8e7 Mon Sep 17 00:00:00 2001 From: Xiang Liu Date: Thu, 31 Jul 2025 14:54:50 +0800 Subject: [PATCH 1648/2653] drm/amdgpu: Fix vcn v4.0.3 poison irq call trace on sriov guest Sriov guest side doesn't init ras feature hence the poison irq shouldn't be put during hw fini. Fixes: d260e486d34d ("drm/amdgpu: Register aqua vanjaram vcn poison irq") [25209.468816] Call Trace: [25209.468817] [25209.468818] ? srso_alias_return_thunk+0x5/0x7f [25209.468820] ? show_trace_log_lvl+0x28e/0x2ea [25209.468822] ? show_trace_log_lvl+0x28e/0x2ea [25209.468825] ? vcn_v4_0_3_hw_fini+0xaf/0xe0 [amdgpu] [25209.468936] ? show_regs.part.0+0x23/0x29 [25209.468939] ? show_regs.cold+0x8/0xd [25209.468940] ? amdgpu_irq_put+0x9e/0xc0 [amdgpu] [25209.469038] ? __warn+0x8c/0x100 [25209.469040] ? amdgpu_irq_put+0x9e/0xc0 [amdgpu] [25209.469135] ? report_bug+0xa4/0xd0 [25209.469138] ? handle_bug+0x39/0x90 [25209.469140] ? exc_invalid_op+0x19/0x70 [25209.469142] ? asm_exc_invalid_op+0x1b/0x20 [25209.469146] ? amdgpu_irq_put+0x9e/0xc0 [amdgpu] [25209.469241] vcn_v4_0_3_hw_fini+0xaf/0xe0 [amdgpu] [25209.469343] amdgpu_ip_block_hw_fini+0x34/0x61 [amdgpu] [25209.469511] amdgpu_device_fini_hw+0x3b3/0x467 [amdgpu] Signed-off-by: Xiang Liu Reviewed-by: Stanley.Yang --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index c51dc401226a2..c6450ed65c12d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -384,7 +384,7 @@ static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); } - if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) + if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN) && !amdgpu_sriov_vf(adev)) amdgpu_irq_put(adev, &adev->vcn.inst->ras_poison_irq, 0); return 0; From ff7242085e938afa71554e707dcad04e2f3fb3d1 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 4 Aug 2025 10:34:06 +0530 Subject: [PATCH 1649/2653] drm/amd/pm: Make static table support conditional Add PMFW version check for static table support on SMU v13.0.6 VFs. Signed-off-by: Lijo Lazar Reviewed-by: Yang Wang --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 28 ++++++++++++++----- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index dd04fe4177172..184d94fa7223d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -410,14 +410,28 @@ static void smu_v13_0_6_init_caps(struct smu_context *smu) if ((pgm == 7 && fw_ver >= 0x7550E00) || (pgm == 0 && fw_ver >= 0x00557E00)) smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS)); - if ((pgm == 0 && fw_ver >= 0x00557F01) || - (pgm == 7 && fw_ver >= 0x7551000)) { - smu_v13_0_6_cap_set(smu, SMU_CAP(STATIC_METRICS)); - smu_v13_0_6_cap_set(smu, SMU_CAP(BOARD_VOLTAGE)); + + if (amdgpu_sriov_vf(adev)) { + if ((pgm == 0 && fw_ver >= 0x00558000) || + (pgm == 7 && fw_ver >= 0x7551000)) { + smu_v13_0_6_cap_set(smu, + SMU_CAP(STATIC_METRICS)); + smu_v13_0_6_cap_set(smu, + SMU_CAP(BOARD_VOLTAGE)); + smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION)); + } + } else { + if ((pgm == 0 && fw_ver >= 0x00557F01) || + (pgm == 7 && fw_ver >= 0x7551000)) { + smu_v13_0_6_cap_set(smu, + SMU_CAP(STATIC_METRICS)); + smu_v13_0_6_cap_set(smu, + SMU_CAP(BOARD_VOLTAGE)); + } + if ((pgm == 0 && fw_ver >= 0x00558000) || + (pgm == 7 && fw_ver >= 0x7551000)) + smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION)); } - if ((pgm == 0 && fw_ver >= 0x00558000) || - (pgm == 7 && fw_ver >= 0x7551000)) - smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION)); } if (((pgm == 7) && (fw_ver >= 0x7550700)) || ((pgm == 0) && (fw_ver >= 0x00557900)) || From 6e40369c409d3505f8dbc088299da9a6ba9fbcb5 Mon Sep 17 00:00:00 2001 From: Xaver Hugl Date: Fri, 1 Aug 2025 00:49:51 +0200 Subject: [PATCH 1650/2653] amdgpu/amdgpu_discovery: increase timeout limit for IFWI init With a timeout of only 1 second, my rx 5700XT fails to initialize, so this increases the timeout to 2s. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3697 Signed-off-by: Xaver Hugl Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 63a6586403c7e..bcff16cb94f3c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -276,7 +276,7 @@ static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, u32 msg; if (!amdgpu_sriov_vf(adev)) { - /* It can take up to a second for IFWI init to complete on some dGPUs, + /* It can take up to two second for IFWI init to complete on some dGPUs, * but generally it should be in the 60-100ms range. Normally this starts * as soon as the device gets power so by the time the OS loads this has long * completed. However, when a card is hotplugged via e.g., USB4, we need to @@ -284,7 +284,7 @@ static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, * continue. */ - for (i = 0; i < 1000; i++) { + for (i = 0; i < 2000; i++) { msg = RREG32(mmMP0_SMN_C2PMSG_33); if (msg & 0x80000000) break; From 4f3fa07d50a46274b7261554dbb94559fb03b2fd Mon Sep 17 00:00:00 2001 From: Ethan Carter Edwards Date: Fri, 1 Aug 2025 21:41:42 -0400 Subject: [PATCH 1651/2653] drm/amdgpu/gfx10: remove redundant repeated nested 0 check The repeated checks on grbm_soft_reset are unnecessary. Remove them. Signed-off-by: Ethan Carter Edwards Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 018346c6217a0..7956f94c6cc61 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7676,19 +7676,17 @@ static int gfx_v10_0_soft_reset(struct amdgpu_ip_block *ip_block) /* Disable MEC parsing/prefetching */ gfx_v10_0_cp_compute_enable(adev, false); - if (grbm_soft_reset) { - tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); - tmp |= grbm_soft_reset; - dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); - WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); - tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); - - udelay(50); - - tmp &= ~grbm_soft_reset; - WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); - tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); - } + tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); + tmp |= grbm_soft_reset; + dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); + tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~grbm_soft_reset; + WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); + tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); /* Wait a little for things to settle down */ udelay(50); From 7a8a58652039b79f64ae73a17cf7b929521ff4d3 Mon Sep 17 00:00:00 2001 From: Ethan Carter Edwards Date: Fri, 1 Aug 2025 21:45:41 -0400 Subject: [PATCH 1652/2653] drm/amdgpu/gfx9: remove redundant repeated nested 0 check The repeated checks on grbm_soft_reset are unnecessary. Remove them. Signed-off-by: Ethan Carter Edwards Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index de4a2f4158dbd..4cec3a8925746 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4183,19 +4183,17 @@ static int gfx_v9_0_soft_reset(struct amdgpu_ip_block *ip_block) /* Disable MEC parsing/prefetching */ gfx_v9_0_cp_compute_enable(adev, false); - if (grbm_soft_reset) { - tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); - tmp |= grbm_soft_reset; - dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); - WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); - tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); - - udelay(50); - - tmp &= ~grbm_soft_reset; - WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); - tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); - } + tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); + tmp |= grbm_soft_reset; + dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); + tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~grbm_soft_reset; + WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); + tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); /* Wait a little for things to settle down */ udelay(50); From 6d415473ae65c80bb4438bad46b4bcaaea52bd3e Mon Sep 17 00:00:00 2001 From: Ethan Carter Edwards Date: Fri, 1 Aug 2025 21:38:16 -0400 Subject: [PATCH 1653/2653] drm/amdgpu/gfx9.4.3: remove redundant repeated nested 0 check The repeated checks on grbm_soft_reset are unnecessary. Remove them. Signed-off-by: Ethan Carter Edwards Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 50fe23a14c84c..8967f5253d432 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2486,19 +2486,17 @@ static int gfx_v9_4_3_soft_reset(struct amdgpu_ip_block *ip_block) /* Disable MEC parsing/prefetching */ gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); - if (grbm_soft_reset) { - tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); - tmp |= grbm_soft_reset; - dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); - WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); - tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); - - udelay(50); - - tmp &= ~grbm_soft_reset; - WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); - tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); - } + tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); + tmp |= grbm_soft_reset; + dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); + tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~grbm_soft_reset; + WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); + tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); /* Wait a little for things to settle down */ udelay(50); From be51480aea4c188f82090e66519ff83d485db614 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 18 Jul 2025 18:50:58 +0530 Subject: [PATCH 1654/2653] drm/amdgpu: Wait for bootloader after PSPv11 reset Some PSPv11 SOCs take a longer time for PSP based mode-1 reset. Instead of checking for C2PMSG_33 status, add the callback wait_for_bootloader. Wait for bootloader to be back to steady state is already part of the generic mode-1 reset flow. Increase the retry count for bootloader wait and also fix the mask to prevent fake pass. Signed-off-by: Lijo Lazar Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c index 6cc05d36e3594..64b240b51f1aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c @@ -149,12 +149,12 @@ static int psp_v11_0_wait_for_bootloader(struct psp_context *psp) int ret; int retry_loop; - for (retry_loop = 0; retry_loop < 10; retry_loop++) { + for (retry_loop = 0; retry_loop < 20; retry_loop++) { /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ ret = psp_wait_for( psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), - 0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE); + 0x80000000, 0x8000FFFF, PSP_WAITREG_NOVERBOSE); if (ret == 0) return 0; @@ -397,18 +397,6 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp) msleep(500); - offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); - - ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, - 0); - - if (ret) { - DRM_INFO("psp mode 1 reset failed!\n"); - return -EINVAL; - } - - DRM_INFO("psp mode1 reset succeed \n"); - return 0; } @@ -665,7 +653,8 @@ static const struct psp_funcs psp_v11_0_funcs = { .ring_get_wptr = psp_v11_0_ring_get_wptr, .ring_set_wptr = psp_v11_0_ring_set_wptr, .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw, - .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw + .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw, + .wait_for_bootloader = psp_v11_0_wait_for_bootloader }; void psp_v11_0_set_psp_funcs(struct psp_context *psp) From 53dc20d33485c1a4fd5e3d75d4a1a114e81dc6c9 Mon Sep 17 00:00:00 2001 From: Amber Lin Date: Thu, 31 Jul 2025 20:45:00 -0400 Subject: [PATCH 1655/2653] drm/amdkfd: Destroy KFD debugfs after destroy KFD wq Since KFD proc content was moved to kernel debugfs, we can't destroy KFD debugfs before kfd_process_destroy_wq. Move kfd_process_destroy_wq prior to kfd_debugfs_fini to fix a kernel NULL pointer problem. It happens when /sys/kernel/debug/kfd was already destroyed in kfd_debugfs_fini but kfd_process_destroy_wq calls kfd_debugfs_remove_process. This line debugfs_remove_recursive(entry->proc_dentry); tries to remove /sys/kernel/debug/kfd/proc/ while /sys/kernel/debug/kfd is already gone. It hangs the kernel by kernel NULL pointer. Signed-off-by: Amber Lin Reviewed-by: Eric Huang --- drivers/gpu/drm/amd/amdkfd/kfd_module.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index 5f8093e03d340..2434619cddc1c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -85,9 +85,9 @@ static int kfd_init(void) static void kfd_exit(void) { kfd_cleanup_processes(); - kfd_debugfs_fini(); kfd_close_peer_direct(); kfd_process_destroy_wq(); + kfd_debugfs_fini(); kfd_procfs_shutdown(); kfd_topology_shutdown(); kfd_chardev_exit(); From 4198853ee942bcd19c2cd100d0aaf73dc58435f5 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 24 Jul 2025 12:58:10 +0530 Subject: [PATCH 1656/2653] drm/amdgpu: Set dpc status appropriately Set the dpc status based on hardware stae. Also, clear the status before reinitialization after a successful reset. Signed-off-by: Lijo Lazar Reviewed-by: Ce Sun --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 24 ++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 02bcdc6a7635b..01a46256ebdd2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5881,6 +5881,7 @@ int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context) amdgpu_set_init_level(tmp_adev, init_level); if (full_reset) { /* post card */ + amdgpu_reset_set_dpc_status(tmp_adev, false); amdgpu_ras_clear_err_state(tmp_adev); r = amdgpu_device_asic_init(tmp_adev); if (r) { @@ -6947,11 +6948,6 @@ pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_sta dev_info(adev->dev, "PCI error: detected callback!!\n"); - if (!amdgpu_dpm_is_link_reset_supported(adev)) { - dev_warn(adev->dev, "No support for XGMI hive yet...\n"); - return PCI_ERS_RESULT_DISCONNECT; - } - adev->pci_channel_state = state; switch (state) { @@ -6961,10 +6957,23 @@ pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_sta case pci_channel_io_frozen: /* Fatal error, prepare for slot reset */ dev_info(adev->dev, "pci_channel_io_frozen: state(%d)!!\n", state); + if (hive) { + /* Hive devices should be able to support FW based + * link reset on other devices, if not return. + */ + if (!amdgpu_dpm_is_link_reset_supported(adev)) { + dev_warn(adev->dev, + "No support for XGMI hive yet...\n"); + return PCI_ERS_RESULT_DISCONNECT; + } + /* Set dpc status only if device is part of hive + * Non-hive devices should be able to recover after + * link reset. + */ + amdgpu_reset_set_dpc_status(adev, true); - if (hive) mutex_lock(&hive->hive_lock); - amdgpu_reset_set_dpc_status(adev, true); + } memset(&reset_context, 0, sizeof(reset_context)); INIT_LIST_HEAD(&device_list); @@ -7127,7 +7136,6 @@ void amdgpu_pci_resume(struct pci_dev *pdev) amdgpu_device_sched_resume(&device_list, NULL, NULL); amdgpu_device_gpu_resume(adev, &device_list, false); amdgpu_device_recovery_put_reset_lock(adev, &device_list); - amdgpu_reset_set_dpc_status(adev, false); if (hive) { mutex_unlock(&hive->hive_lock); From 5fc6b0dee79b02a6197424e967cee73caa6565d0 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 24 Jul 2025 11:13:27 +0530 Subject: [PATCH 1657/2653] drm/amd/pm: Add priority messages for SMU v13.0.6 Certain messages will processed with high priority by PMFW even if it hasn't responded to a previous message. Send the priority message regardless of the success/fail status of the previous message. Add support on SMUv13.0.6 and SMUv13.0.12 Signed-off-by: Lijo Lazar Reviewed-by: Yang Wang --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 1 + .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 2 +- .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 14 +++++++++----- 4 files changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h index 53207317c09ce..93a938ed64fdf 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -476,6 +476,7 @@ enum smu_feature_mask { /* Message category flags */ #define SMU_MSG_VF_FLAG (1U << 0) #define SMU_MSG_RAS_PRI (1U << 1) +#define SMU_MSG_NO_PRECHECK (1U << 2) /* Firmware capability flags */ #define SMU_FW_CAP_RAS_PRI (1U << 0) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index 02a455a31c259..476b7f062a245 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -106,7 +106,7 @@ const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[SMU_MSG_MAX_COUNT] = MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), - MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI), + MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI | SMU_MSG_NO_PRECHECK), MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 184d94fa7223d..b2e5e53c80bb3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -145,7 +145,7 @@ static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COU MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), - MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI), + MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI | SMU_MSG_NO_PRECHECK), MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 1fbcee82a17b3..f4d32f0c072f0 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -256,11 +256,12 @@ static int __smu_cmn_ras_filter_msg(struct smu_context *smu, { struct amdgpu_device *adev = smu->adev; uint32_t flags, resp; - bool fed_status; + bool fed_status, pri; flags = __smu_cmn_get_msg_flags(smu, msg); *poll = true; + pri = !!(flags & SMU_MSG_NO_PRECHECK); /* When there is RAS fatal error, FW won't process non-RAS priority * messages. Don't allow any messages other than RAS priority messages. */ @@ -272,15 +273,18 @@ static int __smu_cmn_ras_filter_msg(struct smu_context *smu, smu_get_message_name(smu, msg)); return -EACCES; } + } + if (pri || fed_status) { /* FW will ignore non-priority messages when a RAS fatal error - * is detected. Hence it is possible that a previous message - * wouldn't have got response. Allow to continue without polling - * for response status for priority messages. + * or reset condition is detected. Hence it is possible that a + * previous message wouldn't have got response. Allow to + * continue without polling for response status for priority + * messages. */ resp = RREG32(smu->resp_reg); dev_dbg(adev->dev, - "Sending RAS priority message %s response status: %x", + "Sending priority message %s response status: %x", smu_get_message_name(smu, msg), resp); if (resp == 0) *poll = false; From 3d9a4ddf862bcf04ad3f6be575932c73cd7b3e90 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 28 May 2025 11:51:18 -0400 Subject: [PATCH 1658/2653] drm/amdkfd: remove unused code upages is assigned under cpages = 0, so it isn't really used in this function. Signed-off-by: James Zhu Reviewed-by: Philip.Yang --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index f58d070c9cc88..b6f61d133ed7d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -759,7 +759,6 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, if (!cpages) { pr_debug("failed collect migrate device pages [0x%lx 0x%lx]\n", prange->start, prange->last); - upages = svm_migrate_unsuccessful_pages(&migrate); goto out_free; } if (cpages != npages) From 37ecbdfca54bfaf51011f28cac616e36958d388a Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 28 May 2025 12:38:58 -0400 Subject: [PATCH 1659/2653] drm/amdkfd: return migration pages from copy function dst MIGRATE_PFN_VALID bit and src MIGRATE_PFN_MIGRATE bit should always be set when migration success. cpage includes src MIGRATE_PFN_MIGRATE bit set and MIGRATE_PFN_VALID bit unset pages for both ram and vram when memory is only allocated without being populated before migration, those ram pages should be counted as migrate pages and those vram pages should not be counted as migrate pages. Here migration pages refer to how many vram pages invloved. -v2 use dst to check MIGRATE_PFN_VALID bit (suggested-by Philip) -v3 add warning when vram pages is less than migration pages return migration pages directly from copy function -v4 correct comments and copy function return mpage (suggested-by Felix) Signed-off-by: James Zhu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 72 ++++++++++++------------ 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index b6f61d133ed7d..690905d7551da 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -269,20 +269,7 @@ static void svm_migrate_put_sys_page(unsigned long addr) put_page(page); } -static unsigned long svm_migrate_unsuccessful_pages(struct migrate_vma *migrate) -{ - unsigned long upages = 0; - unsigned long i; - - for (i = 0; i < migrate->npages; i++) { - if (migrate->src[i] & MIGRATE_PFN_VALID && - !(migrate->src[i] & MIGRATE_PFN_MIGRATE)) - upages++; - } - return upages; -} - -static int +static long svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, struct migrate_vma *migrate, struct dma_fence **mfence, dma_addr_t *scratch, uint64_t ttm_res_offset) @@ -291,7 +278,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, struct amdgpu_device *adev = node->adev; struct device *dev = adev->dev; struct amdgpu_res_cursor cursor; - uint64_t mpages = 0; + long mpages; dma_addr_t *src; uint64_t *dst; uint64_t i, j; @@ -305,6 +292,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, amdgpu_res_first(prange->ttm_res, ttm_res_offset, npages << PAGE_SHIFT, &cursor); + mpages = 0; for (i = j = 0; (i < npages) && (mpages < migrate->cpages); i++) { struct page *spage; @@ -366,13 +354,14 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, out_free_vram_pages: if (r) { pr_debug("failed %d to copy memory to vram\n", r); - for (i = 0; i < npages && mpages; i++) { + while (i-- && mpages) { if (!dst[i]) continue; svm_migrate_put_vram_page(adev, dst[i]); migrate->dst[i] = 0; mpages--; } + mpages = r; } #ifdef DEBUG_FORCE_MIXED_DOMAINS @@ -390,7 +379,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, } #endif - return r; + return mpages; } static long @@ -405,7 +394,7 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange, struct dma_fence *mfence = NULL; struct migrate_vma migrate = { 0 }; unsigned long cpages = 0; - unsigned long mpages = 0; + long mpages = 0; dma_addr_t *scratch; void *buf; int r = -ENOMEM; @@ -455,15 +444,17 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange, else pr_debug("0x%lx pages collected\n", cpages); - r = svm_migrate_copy_to_vram(node, prange, &migrate, &mfence, scratch, ttm_res_offset); + mpages = svm_migrate_copy_to_vram(node, prange, &migrate, &mfence, scratch, ttm_res_offset); migrate_vma_pages(&migrate); svm_migrate_copy_done(adev, mfence); migrate_vma_finalize(&migrate); - mpages = cpages - svm_migrate_unsuccessful_pages(&migrate); - pr_debug("successful/cpages/npages 0x%lx/0x%lx/0x%lx\n", + if (mpages >= 0) + pr_debug("migrated/collected/requested 0x%lx/0x%lx/0x%lx\n", mpages, cpages, migrate.npages); + else + r = mpages; svm_range_dma_unmap_dev(adev->dev, scratch, 0, npages); @@ -473,14 +464,13 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange, start >> PAGE_SHIFT, end >> PAGE_SHIFT, 0, node->id, trigger, r); out: - if (!r && mpages) { + if (!r && mpages > 0) { pdd = svm_range_get_pdd_by_node(prange, node); if (pdd) WRITE_ONCE(pdd->page_in, pdd->page_in + mpages); - - return mpages; } - return r; + + return r ? r : mpages; } /** @@ -591,7 +581,7 @@ static void svm_migrate_page_free(struct page *page) } } -static int +static long svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, struct migrate_vma *migrate, struct dma_fence **mfence, dma_addr_t *scratch, uint64_t npages) @@ -600,6 +590,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, uint64_t *src; dma_addr_t *dst; struct page *dpage; + long mpages; uint64_t i = 0, j; uint64_t addr; int r = 0; @@ -612,6 +603,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, src = (uint64_t *)(scratch + npages); dst = scratch; + mpages = 0; for (i = 0, j = 0; i < npages; i++, addr += PAGE_SIZE) { struct page *spage; @@ -661,6 +653,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, migrate->dst[i] = migrate_pfn(page_to_pfn(dpage)); migrate->dst[i] |= MIGRATE_PFN_LOCKED; + mpages++; j++; } @@ -670,13 +663,17 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, out_oom: if (r) { pr_debug("failed %d copy to ram\n", r); - while (i--) { + while (i-- && mpages) { + if (!migrate->dst[i]) + continue; svm_migrate_put_sys_page(dst[i]); migrate->dst[i] = 0; + mpages--; } + mpages = r; } - return r; + return mpages; } /** @@ -703,9 +700,8 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, { struct kfd_process *p = container_of(prange->svms, struct kfd_process, svms); uint64_t npages = (end - start) >> PAGE_SHIFT; - unsigned long upages = npages; unsigned long cpages = 0; - unsigned long mpages = 0; + long mpages = 0; struct amdgpu_device *adev = node->adev; struct kfd_process_device *pdd; struct dma_fence *mfence = NULL; @@ -767,13 +763,15 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, else pr_debug("0x%lx pages collected\n", cpages); - r = svm_migrate_copy_to_ram(adev, prange, &migrate, &mfence, + mpages = svm_migrate_copy_to_ram(adev, prange, &migrate, &mfence, scratch, npages); migrate_vma_pages(&migrate); - upages = svm_migrate_unsuccessful_pages(&migrate); - pr_debug("unsuccessful/cpages/npages 0x%lx/0x%lx/0x%lx\n", - upages, cpages, migrate.npages); + if (mpages >= 0) + pr_debug("migrated/collected/requested 0x%lx/0x%lx/0x%lx\n", + mpages, cpages, migrate.npages); + else + r = mpages; svm_migrate_copy_done(adev, mfence); migrate_vma_finalize(&migrate); @@ -786,8 +784,7 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, start >> PAGE_SHIFT, end >> PAGE_SHIFT, node->id, 0, trigger, r); out: - if (!r && cpages) { - mpages = cpages - upages; + if (!r && mpages > 0) { pdd = svm_range_get_pdd_by_node(prange, node); if (pdd) WRITE_ONCE(pdd->page_out, pdd->page_out + mpages); @@ -870,6 +867,9 @@ int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm, } if (r >= 0) { + WARN_ONCE(prange->vram_pages < mpages, + "Recorded vram pages(0x%llx) should not be less than migration pages(0x%lx).", + prange->vram_pages, mpages); prange->vram_pages -= mpages; /* prange does not have vram page set its actual_loc to system From 3aef576e5a962bb999e3e76129186b3fd6106b17 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Tue, 5 Aug 2025 10:02:07 -0400 Subject: [PATCH 1660/2653] drm/amd/display: Fix vupdate_offload_work doc Fix the following warning in struct documentation: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:168: warning: expecting prototype for struct dm_vupdate_work. Prototype was for struct vupdate_offload_work instead Fixes: c210b757b400 ("drm/amd/display: fix dmub access race condition") Reported-by: Stephen Rothwell Signed-off-by: Aurabindo Pillai Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 91d82f25d1e52..a91725db4bcf6 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -154,7 +154,7 @@ struct idle_workqueue { }; /** - * struct dm_vupdate_work - Work data for periodic action in idle + * struct vupdate_offload_work - Work data for offloading task from vupdate handler * @work: Kernel work data for the work event * @adev: amdgpu_device back pointer * @stream: DC stream associated with the crtc From a253fd281b9e9883f8e8b47efeaf787e1a6e6554 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Sat, 2 Aug 2025 01:48:09 +0800 Subject: [PATCH 1661/2653] drm/amd/pm: Add dpm interface for temp metrics Add dpm interface to get gpuboard/baseboard temperature metrics v2: Add temperature metrics support check(Lijo) v3: Return error code in case of operation not supported(Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- .../gpu/drm/amd/include/kgd_pp_interface.h | 81 +++++++++++++++++++ drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 60 ++++++++++++++ drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 4 + 3 files changed, 145 insertions(+) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index 5a2ccc9df4a5b..8d562b0a401c9 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -30,6 +30,12 @@ extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; +enum smu_temp_metric_type { + SMU_TEMP_METRIC_BASEBOARD, + SMU_TEMP_METRIC_GPUBOARD, + SMU_TEMP_METRIC_MAX, +}; + enum smu_event_type { SMU_EVENT_RESET_COMPLETE = 0, }; @@ -505,6 +511,8 @@ struct amd_pm_funcs { int (*set_df_cstate)(void *handle, enum pp_df_cstate state); int (*set_xgmi_pstate)(void *handle, uint32_t pstate); ssize_t (*get_gpu_metrics)(void *handle, void **table); + ssize_t (*get_temp_metrics)(void *handle, enum smu_temp_metric_type type, void *table); + bool (*temp_metrics_is_supported)(void *handle, enum smu_temp_metric_type type); ssize_t (*get_xcp_metrics)(void *handle, int xcp_id, void *table); ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size); int (*set_watermarks_for_clock_ranges)(void *handle, @@ -1604,6 +1612,79 @@ struct amdgpu_pm_metrics { uint8_t data[]; }; +enum amdgpu_vr_temp { + AMDGPU_VDDCR_VDD0_TEMP, + AMDGPU_VDDCR_VDD1_TEMP, + AMDGPU_VDDCR_VDD2_TEMP, + AMDGPU_VDDCR_VDD3_TEMP, + AMDGPU_VDDCR_SOC_A_TEMP, + AMDGPU_VDDCR_SOC_C_TEMP, + AMDGPU_VDDCR_SOCIO_A_TEMP, + AMDGPU_VDDCR_SOCIO_C_TEMP, + AMDGPU_VDD_085_HBM_TEMP, + AMDGPU_VDDCR_11_HBM_B_TEMP, + AMDGPU_VDDCR_11_HBM_D_TEMP, + AMDGPU_VDD_USR_TEMP, + AMDGPU_VDDIO_11_E32_TEMP, + AMDGPU_VR_MAX_TEMP_ENTRIES, +}; + +enum amdgpu_system_temp { + AMDGPU_UBB_FPGA_TEMP, + AMDGPU_UBB_FRONT_TEMP, + AMDGPU_UBB_BACK_TEMP, + AMDGPU_UBB_OAM7_TEMP, + AMDGPU_UBB_IBC_TEMP, + AMDGPU_UBB_UFPGA_TEMP, + AMDGPU_UBB_OAM1_TEMP, + AMDGPU_OAM_0_1_HSC_TEMP, + AMDGPU_OAM_2_3_HSC_TEMP, + AMDGPU_OAM_4_5_HSC_TEMP, + AMDGPU_OAM_6_7_HSC_TEMP, + AMDGPU_UBB_FPGA_0V72_VR_TEMP, + AMDGPU_UBB_FPGA_3V3_VR_TEMP, + AMDGPU_RETIMER_0_1_2_3_1V2_VR_TEMP, + AMDGPU_RETIMER_4_5_6_7_1V2_VR_TEMP, + AMDGPU_RETIMER_0_1_0V9_VR_TEMP, + AMDGPU_RETIMER_4_5_0V9_VR_TEMP, + AMDGPU_RETIMER_2_3_0V9_VR_TEMP, + AMDGPU_RETIMER_6_7_0V9_VR_TEMP, + AMDGPU_OAM_0_1_2_3_3V3_VR_TEMP, + AMDGPU_OAM_4_5_6_7_3V3_VR_TEMP, + AMDGPU_IBC_HSC_TEMP, + AMDGPU_IBC_TEMP, + AMDGPU_SYSTEM_MAX_TEMP_ENTRIES = 32, +}; + +enum amdgpu_node_temp { + AMDGPU_RETIMER_X_TEMP, + AMDGPU_OAM_X_IBC_TEMP, + AMDGPU_OAM_X_IBC_2_TEMP, + AMDGPU_OAM_X_VDD18_VR_TEMP, + AMDGPU_OAM_X_04_HBM_B_VR_TEMP, + AMDGPU_OAM_X_04_HBM_D_VR_TEMP, + AMDGPU_NODE_MAX_TEMP_ENTRIES = 12, +}; + +struct amdgpu_gpuboard_temp_metrics_v1_0 { + struct metrics_table_header common_header; + uint16_t label_version; + uint16_t node_id; + uint64_t accumulation_counter; + /* Encoded temperature in Celcius, 24:31 is sensor id 0:23 is temp value */ + uint32_t node_temp[AMDGPU_NODE_MAX_TEMP_ENTRIES]; + uint32_t vr_temp[AMDGPU_VR_MAX_TEMP_ENTRIES]; +}; + +struct amdgpu_baseboard_temp_metrics_v1_0 { + struct metrics_table_header common_header; + uint16_t label_version; + uint16_t node_id; + uint64_t accumulation_counter; + /* Encoded temperature in Celcius, 24:31 is sensor id 0:23 is temp value */ + uint32_t system_temp[AMDGPU_SYSTEM_MAX_TEMP_ENTRIES]; +}; + struct amdgpu_partition_metrics_v1_0 { struct metrics_table_header common_header; /* Current clocks (Mhz) */ diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index 597e62ff3d541..e2bf4006fc28a 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -2037,6 +2037,66 @@ int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, return ret; } +/** + * amdgpu_dpm_get_temp_metrics - Retrieve metrics for a specific compute + * partition + * @adev: Pointer to the device. + * @type: Identifier for the temperature type metrics to be fetched. + * @table: Pointer to a buffer where the metrics will be stored. If NULL, the + * function returns the size of the metrics structure. + * + * This function retrieves metrics for a specific temperature type, If the + * table parameter is NULL, the function returns the size of the metrics + * structure without populating it. + * + * Return: Size of the metrics structure on success, or a negative error code on failure. + */ +ssize_t amdgpu_dpm_get_temp_metrics(struct amdgpu_device *adev, + enum smu_temp_metric_type type, void *table) +{ + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; + int ret; + + if (!pp_funcs->get_temp_metrics || + !amdgpu_dpm_is_temp_metrics_supported(adev, type)) + return -EOPNOTSUPP; + + mutex_lock(&adev->pm.mutex); + ret = pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); + mutex_unlock(&adev->pm.mutex); + + return ret; +} + +/** + * amdgpu_dpm_is_temp_metrics_supported - Return if specific temperature metrics support + * is available + * @adev: Pointer to the device. + * @type: Identifier for the temperature type metrics to be fetched. + * + * This function returns metrics if specific temperature metrics type is supported or not. + * + * Return: True in case of metrics type supported else false. + */ +bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev, + enum smu_temp_metric_type type) +{ + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; + bool support_temp_metrics = false; + + if (!pp_funcs->temp_metrics_is_supported) + return support_temp_metrics; + + if (is_support_sw_smu(adev)) { + mutex_lock(&adev->pm.mutex); + support_temp_metrics = + pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); + mutex_unlock(&adev->pm.mutex); + } + + return support_temp_metrics; +} + /** * amdgpu_dpm_get_xcp_metrics - Retrieve metrics for a specific compute * partition diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h index 37934716e972a..18c53e1fbeb39 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h @@ -526,6 +526,8 @@ int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table); ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id, void *table); +ssize_t amdgpu_dpm_get_temp_metrics(struct amdgpu_device *adev, + enum smu_temp_metric_type type, void *table); /** * @get_pm_metrics: Get one snapshot of power management metrics from PMFW. The @@ -614,5 +616,7 @@ int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask); bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev); void amdgpu_dpm_phase_det_debugfs_init(struct amdgpu_device *adev); int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask); +bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev, + enum smu_temp_metric_type type); #endif From f8bced7931ecc83e70efc0ea438f81ead0754665 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Sat, 2 Aug 2025 02:10:12 +0800 Subject: [PATCH 1662/2653] drm/amd/pm: Add smu interface for temp metrics Add smu interface to get baseboard/gpuboard temperature metrics v2: Rename is_support to is_supported(Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 29 +++++++++++++++++++ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 27 +++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index c9a9bc64cfa15..bea14bf4fdb1e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -3831,6 +3831,33 @@ int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, return ret; } +static ssize_t smu_sys_get_temp_metrics(void *handle, enum smu_temp_metric_type type, void *table) +{ + struct smu_context *smu = handle; + + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) + return -EOPNOTSUPP; + + if (!smu->smu_temp.temp_funcs || !smu->smu_temp.temp_funcs->get_temp_metrics) + return -EOPNOTSUPP; + + return smu->smu_temp.temp_funcs->get_temp_metrics(smu, type, table); +} + +static bool smu_temp_metrics_is_supported(void *handle, enum smu_temp_metric_type type) +{ + struct smu_context *smu = handle; + bool ret = false; + + if (!smu->pm_enabled) + return false; + + if (smu->smu_temp.temp_funcs && smu->smu_temp.temp_funcs->temp_metrics_is_supported) + ret = smu->smu_temp.temp_funcs->temp_metrics_is_supported(smu, type); + + return ret; +} + static ssize_t smu_sys_get_xcp_metrics(void *handle, int xcp_id, void *table) { struct smu_context *smu = handle; @@ -3903,6 +3930,8 @@ static const struct amd_pm_funcs swsmu_pm_funcs = { .get_dpm_clock_table = smu_get_dpm_clock_table, .get_smu_prv_buf_details = smu_get_prv_buffer_details, .get_xcp_metrics = smu_sys_get_xcp_metrics, + .get_temp_metrics = smu_sys_get_temp_metrics, + .temp_metrics_is_supported = smu_temp_metrics_is_supported, }; int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index af7485ff8bd72..fad6783674ad6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -427,6 +427,10 @@ struct smu_dpm_context { struct smu_phase_det_ctl *pd_ctl; }; +struct smu_temp_context { + const struct smu_temp_funcs *temp_funcs; +}; + struct smu_power_gate { bool uvd_gated; bool vce_gated; @@ -560,6 +564,7 @@ struct smu_context { struct smu_table_context smu_table; struct smu_dpm_context smu_dpm; struct smu_power_context smu_power; + struct smu_temp_context smu_temp; struct smu_feature smu_feature; struct amd_pp_display_configuration *display_config; struct smu_baco_context smu_baco; @@ -654,6 +659,28 @@ struct smu_context { struct i2c_adapter; +/** + * struct smu_temp_funcs - Callbacks used to get temperature data. + */ +struct smu_temp_funcs { + /** + * @get_temp_metrics: Calibrate voltage/frequency curve to fit the system's + * power delivery and voltage margins. Required for adaptive + * @type Temperature metrics type(baseboard/gpuboard) + * Return: Size of &table + */ + ssize_t (*get_temp_metrics)(struct smu_context *smu, + enum smu_temp_metric_type type, void *table); + + /** + * @temp_metrics_is_support: Get if specific temperature metrics is supported + * @type Temperature metrics type(baseboard/gpuboard) + * Return: true if supported else false + */ + bool (*temp_metrics_is_supported)(struct smu_context *smu, enum smu_temp_metric_type type); + +}; + /** * struct pptable_funcs - Callbacks used to interact with the SMU. */ From 8f0d82ee8dd555eff0031aaf5b6737289df69a26 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Sat, 2 Aug 2025 02:41:50 +0800 Subject: [PATCH 1663/2653] drm/amd/pm: Update pmfw header for smu_v13_0_12 Update pmfw header for smu_v13_0_12 with system temperature metrics table Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- .../pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h | 74 ++++++++++++++++++- .../pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h | 6 +- 2 files changed, 78 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h index 0a2ca544f4e38..1c407a8e96ee3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h @@ -135,7 +135,63 @@ typedef enum { GFX_DVM_MARGIN_COUNT } GFX_DVM_MARGIN_e; -#define SMU_METRICS_TABLE_VERSION 0x13 +typedef enum{ + SYSTEM_TEMP_UBB_FPGA, + SYSTEM_TEMP_UBB_FRONT, + SYSTEM_TEMP_UBB_BACK, + SYSTEM_TEMP_UBB_OAM7, + SYSTEM_TEMP_UBB_IBC, + SYSTEM_TEMP_UBB_UFPGA, + SYSTEM_TEMP_UBB_OAM1, + SYSTEM_TEMP_OAM_0_1_HSC, + SYSTEM_TEMP_OAM_2_3_HSC, + SYSTEM_TEMP_OAM_4_5_HSC, + SYSTEM_TEMP_OAM_6_7_HSC, + SYSTEM_TEMP_UBB_FPGA_0V72_VR, + SYSTEM_TEMP_UBB_FPGA_3V3_VR, + SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR, + SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR, + SYSTEM_TEMP_RETIMER_0_1_0V9_VR, + SYSTEM_TEMP_RETIMER_4_5_0V9_VR, + SYSTEM_TEMP_RETIMER_2_3_0V9_VR, + SYSTEM_TEMP_RETIMER_6_7_0V9_VR, + SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR, + SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR, + SYSTEM_TEMP_IBC_HSC, + SYSTEM_TEMP_IBC, + SYSTEM_TEMP_MAX_ENTRIES = 32 +} SYSTEM_TEMP_e; + +typedef enum{ + NODE_TEMP_RETIMER, + NODE_TEMP_IBC_TEMP, + NODE_TEMP_IBC_2_TEMP, + NODE_TEMP_VDD18_VR_TEMP, + NODE_TEMP_04_HBM_B_VR_TEMP, + NODE_TEMP_04_HBM_D_VR_TEMP, + NODE_TEMP_MAX_TEMP_ENTRIES = 12 +} NODE_TEMP_e; + +typedef enum { + SVI_VDDCR_VDD0_TEMP, + SVI_VDDCR_VDD1_TEMP, + SVI_VDDCR_VDD2_TEMP, + SVI_VDDCR_VDD3_TEMP, + SVI_VDDCR_SOC_A_TEMP, + SVI_VDDCR_SOC_C_TEMP, + SVI_VDDCR_SOCIO_A_TEMP, + SVI_VDDCR_SOCIO_C_TEMP, + SVI_VDD_085_HBM_TEMP, + SVI_VDDCR_11_HBM_B_TEMP, + SVI_VDDCR_11_HBM_D_TEMP, + SVI_VDD_USR_TEMP, + SVI_VDDIO_11_E32_TEMP, + SVI_MAX_TEMP_ENTRIES, // 13 +} SVI_TEMP_e; + +#define SMU_METRICS_TABLE_VERSION 0x14 + +#define SMU_SYSTEM_METRICS_TABLE_VERSION 0x0 typedef struct __attribute__((packed, aligned(4))) { uint64_t AccumulationCounter; @@ -231,11 +287,27 @@ typedef struct __attribute__((packed, aligned(4))) { uint64_t GfxclkBelowHostLimitThmAcc[8]; uint64_t GfxclkBelowHostLimitTotalAcc[8]; uint64_t GfxclkLowUtilizationAcc[8]; + + uint32_t AidTemperature[4]; + uint32_t XcdTemperature[8]; + uint32_t HbmTemperature[8]; } MetricsTable_t; #define SMU_VF_METRICS_TABLE_MASK (1 << 31) #define SMU_VF_METRICS_TABLE_VERSION (0x6 | SMU_VF_METRICS_TABLE_MASK) +#pragma pack(push, 4) +typedef struct { + uint64_t AccumulationCounter; // Last update timestamp + uint16_t LabelVersion; // Defaults to 0. + uint16_t NodeIdentifier; // Unique identifier to each node on system. + int16_t SystemTemperatures[SYSTEM_TEMP_MAX_ENTRIES]; // Signed integer temperature value in Celsius, unused fields are set to 0xFFFF + int16_t NodeTemperatures[NODE_TEMP_MAX_TEMP_ENTRIES]; // Signed integer temperature value in Celsius, unused fields are set to 0xFFFF + int16_t VrTemperatures[SVI_MAX_TEMP_ENTRIES]; // Signed integer temperature value in Celsius + int16_t spare[3]; +} SystemMetricsTable_t; +#pragma pack(pop) + typedef struct __attribute__((packed, aligned(4))) { uint32_t AccumulationCounter; uint32_t InstGfxclk_TargFreq; diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h index e1f490b6ce64f..aff2776a8b6f4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h @@ -116,7 +116,11 @@ #define PPSMC_MSG_DumpErrorRecord 0x57 #define PPSMC_MSG_EraseRasTable 0x58 #define PPSMC_MSG_GetStaticMetricsTable 0x59 -#define PPSMC_Message_Count 0x5A +#define PPSMC_MSG_ResetVfArbitersByIndex 0x5A +#define PPSMC_MSG_GetBadPageSeverity 0x5B +#define PPSMC_MSG_GetSystemMetricsTable 0x5C +#define PPSMC_MSG_GetSystemMetricsVersion 0x5D +#define PPSMC_Message_Count 0x5E //PPSMC Reset Types for driver msg argument #define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET 0x1 From e3a825617f6f1e38383ea35d4ca415c31afe096b Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Sat, 2 Aug 2025 04:26:13 +0800 Subject: [PATCH 1664/2653] drm/amd/pm: Fetch and fill temperature metrics Fetch system metrics table to fill gpuboard/baseboard temperature metrics data for smu_v13_0_12 v2: Remove unnecessary checks, used separate metrics time for temperature metrics table(Lijo) v3: Use cached values for back to back system metrics query(Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 + drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 + drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 +- .../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 248 +++++++++++++++++- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 6 + .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 3 + drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 26 ++ 7 files changed, 287 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index bea14bf4fdb1e..cd8d44c8e1811 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -766,6 +766,7 @@ static int smu_set_funcs(struct amdgpu_device *adev) case IP_VERSION(13, 0, 14): case IP_VERSION(13, 0, 12): smu_v13_0_6_set_ppt_funcs(smu); + smu_v13_0_6_set_temp_funcs(smu); /* Enable pp_od_clk_voltage node */ smu->od_enabled = true; break; diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index fad6783674ad6..06dffc89b3f2c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -257,6 +257,7 @@ struct smu_table { void *cpu_addr; struct amdgpu_bo *bo; uint32_t version; + unsigned long metrics_time; }; enum smu_perf_level_designation { @@ -322,6 +323,7 @@ enum smu_table_id { SMU_TABLE_ECCINFO, SMU_TABLE_COMBO_PPTABLE, SMU_TABLE_WIFIBAND, + SMU_TABLE_TEMP_METRICS, SMU_TABLE_COUNT, }; diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h index 93a938ed64fdf..71e8b6f52a042 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -285,7 +285,8 @@ __SMU_DUMMY_MAP(GetPhsDetResidency), \ __SMU_DUMMY_MAP(ResetSDMA), \ __SMU_DUMMY_MAP(ResetVCN), \ - __SMU_DUMMY_MAP(GetStaticMetricsTable), + __SMU_DUMMY_MAP(GetStaticMetricsTable), \ + __SMU_DUMMY_MAP(GetSystemMetricsTable), #undef __SMU_DUMMY_MAP #define __SMU_DUMMY_MAP(type) SMU_MSG_##type diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index 476b7f062a245..920f60da9c5c7 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -138,6 +138,7 @@ const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[SMU_MSG_MAX_COUNT] = MSG_MAP(SetThrottlingPolicy, PPSMC_MSG_SetThrottlingPolicy, 0), MSG_MAP(ResetSDMA, PPSMC_MSG_ResetSDMA, 0), MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 1), + MSG_MAP(GetSystemMetricsTable, PPSMC_MSG_GetSystemMetricsTable, 0), }; static int smu_v13_0_12_get_enabled_mask(struct smu_context *smu, @@ -184,7 +185,8 @@ static int smu_v13_0_12_fru_get_product_info(struct smu_context *smu, int smu_v13_0_12_get_max_metrics_size(void) { - return max(sizeof(StaticMetricsTable_t), sizeof(MetricsTable_t)); + return max3(sizeof(StaticMetricsTable_t), sizeof(MetricsTable_t), + sizeof(SystemMetricsTable_t)); } static void smu_v13_0_12_init_xgmi_data(struct smu_context *smu, @@ -359,6 +361,245 @@ int smu_v13_0_12_get_smu_metrics_data(struct smu_context *smu, return 0; } +static int smu_v13_0_12_get_system_metrics_table(struct smu_context *smu, void *metrics_table, + bool bypass_cache) +{ + struct smu_table_context *smu_table = &smu->smu_table; + uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size; + struct smu_table *table = &smu_table->driver_table; + int ret; + + if (bypass_cache || !smu_table->tables[SMU_TABLE_TEMP_METRICS].metrics_time || + time_after(jiffies, + smu_table->tables[SMU_TABLE_TEMP_METRICS].metrics_time + + msecs_to_jiffies(1))) { + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSystemMetricsTable, NULL); + if (ret) { + dev_info(smu->adev->dev, + "Failed to export system metrics table!\n"); + return ret; + } + + amdgpu_asic_invalidate_hdp(smu->adev, NULL); + memcpy(smu_table->metrics_table, table->cpu_addr, table_size); + + smu_table->tables[SMU_TABLE_TEMP_METRICS].metrics_time = jiffies; + } + + if (metrics_table) + memcpy(metrics_table, smu_table->metrics_table, sizeof(SystemMetricsTable_t)); + + return 0; +} + +static enum amdgpu_node_temp smu_v13_0_12_get_node_sensor_type(NODE_TEMP_e type) +{ + switch (type) { + case NODE_TEMP_RETIMER: + return AMDGPU_RETIMER_X_TEMP; + case NODE_TEMP_IBC_TEMP: + return AMDGPU_OAM_X_IBC_TEMP; + case NODE_TEMP_IBC_2_TEMP: + return AMDGPU_OAM_X_IBC_2_TEMP; + case NODE_TEMP_VDD18_VR_TEMP: + return AMDGPU_OAM_X_VDD18_VR_TEMP; + case NODE_TEMP_04_HBM_B_VR_TEMP: + return AMDGPU_OAM_X_04_HBM_B_VR_TEMP; + case NODE_TEMP_04_HBM_D_VR_TEMP: + return AMDGPU_OAM_X_04_HBM_D_VR_TEMP; + default: + return -EINVAL; + } +} + +static enum amdgpu_vr_temp smu_v13_0_12_get_vr_sensor_type(SVI_TEMP_e type) +{ + switch (type) { + case SVI_VDDCR_VDD0_TEMP: + return AMDGPU_VDDCR_VDD0_TEMP; + case SVI_VDDCR_VDD1_TEMP: + return AMDGPU_VDDCR_VDD1_TEMP; + case SVI_VDDCR_VDD2_TEMP: + return AMDGPU_VDDCR_VDD2_TEMP; + case SVI_VDDCR_VDD3_TEMP: + return AMDGPU_VDDCR_VDD3_TEMP; + case SVI_VDDCR_SOC_A_TEMP: + return AMDGPU_VDDCR_SOC_A_TEMP; + case SVI_VDDCR_SOC_C_TEMP: + return AMDGPU_VDDCR_SOC_C_TEMP; + case SVI_VDDCR_SOCIO_A_TEMP: + return AMDGPU_VDDCR_SOCIO_A_TEMP; + case SVI_VDDCR_SOCIO_C_TEMP: + return AMDGPU_VDDCR_SOCIO_C_TEMP; + case SVI_VDD_085_HBM_TEMP: + return AMDGPU_VDD_085_HBM_TEMP; + case SVI_VDDCR_11_HBM_B_TEMP: + return AMDGPU_VDDCR_11_HBM_B_TEMP; + case SVI_VDDCR_11_HBM_D_TEMP: + return AMDGPU_VDDCR_11_HBM_D_TEMP; + case SVI_VDD_USR_TEMP: + return AMDGPU_VDD_USR_TEMP; + case SVI_VDDIO_11_E32_TEMP: + return AMDGPU_VDDIO_11_E32_TEMP; + default: + return -EINVAL; + } +} + +static enum amdgpu_system_temp smu_v13_0_12_get_system_sensor_type(SYSTEM_TEMP_e type) +{ + switch (type) { + case SYSTEM_TEMP_UBB_FPGA: + return AMDGPU_UBB_FPGA_TEMP; + case SYSTEM_TEMP_UBB_FRONT: + return AMDGPU_UBB_FRONT_TEMP; + case SYSTEM_TEMP_UBB_BACK: + return AMDGPU_UBB_BACK_TEMP; + case SYSTEM_TEMP_UBB_OAM7: + return AMDGPU_UBB_OAM7_TEMP; + case SYSTEM_TEMP_UBB_IBC: + return AMDGPU_UBB_IBC_TEMP; + case SYSTEM_TEMP_UBB_UFPGA: + return AMDGPU_UBB_UFPGA_TEMP; + case SYSTEM_TEMP_UBB_OAM1: + return AMDGPU_UBB_OAM1_TEMP; + case SYSTEM_TEMP_OAM_0_1_HSC: + return AMDGPU_OAM_0_1_HSC_TEMP; + case SYSTEM_TEMP_OAM_2_3_HSC: + return AMDGPU_OAM_2_3_HSC_TEMP; + case SYSTEM_TEMP_OAM_4_5_HSC: + return AMDGPU_OAM_4_5_HSC_TEMP; + case SYSTEM_TEMP_OAM_6_7_HSC: + return AMDGPU_OAM_6_7_HSC_TEMP; + case SYSTEM_TEMP_UBB_FPGA_0V72_VR: + return AMDGPU_UBB_FPGA_0V72_VR_TEMP; + case SYSTEM_TEMP_UBB_FPGA_3V3_VR: + return AMDGPU_UBB_FPGA_3V3_VR_TEMP; + case SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR: + return AMDGPU_RETIMER_0_1_2_3_1V2_VR_TEMP; + case SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR: + return AMDGPU_RETIMER_4_5_6_7_1V2_VR_TEMP; + case SYSTEM_TEMP_RETIMER_0_1_0V9_VR: + return AMDGPU_RETIMER_0_1_0V9_VR_TEMP; + case SYSTEM_TEMP_RETIMER_4_5_0V9_VR: + return AMDGPU_RETIMER_4_5_0V9_VR_TEMP; + case SYSTEM_TEMP_RETIMER_2_3_0V9_VR: + return AMDGPU_RETIMER_2_3_0V9_VR_TEMP; + case SYSTEM_TEMP_RETIMER_6_7_0V9_VR: + return AMDGPU_RETIMER_6_7_0V9_VR_TEMP; + case SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR: + return AMDGPU_OAM_0_1_2_3_3V3_VR_TEMP; + case SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR: + return AMDGPU_OAM_4_5_6_7_3V3_VR_TEMP; + case SYSTEM_TEMP_IBC_HSC: + return AMDGPU_IBC_HSC_TEMP; + case SYSTEM_TEMP_IBC: + return AMDGPU_IBC_TEMP; + default: + return -EINVAL; + } +} + +static bool smu_v13_0_12_is_temp_metrics_supported(struct smu_context *smu, + enum smu_temp_metric_type type) +{ + switch (type) { + case SMU_TEMP_METRIC_BASEBOARD: + if (smu->adev->gmc.xgmi.physical_node_id == 0 && + smu->adev->gmc.xgmi.num_physical_nodes > 1 && + smu_v13_0_6_cap_supported(smu, SMU_CAP(TEMP_METRICS))) + return true; + break; + case SMU_TEMP_METRIC_GPUBOARD: + return smu_v13_0_6_cap_supported(smu, SMU_CAP(TEMP_METRICS)); + default: + break; + } + + return false; +} + +static ssize_t smu_v13_0_12_get_temp_metrics(struct smu_context *smu, + enum smu_temp_metric_type type, void *table) +{ + struct amdgpu_gpuboard_temp_metrics_v1_0 *gpuboard_temp_metrics; + struct amdgpu_baseboard_temp_metrics_v1_0 *baseboard_temp_metrics; + SystemMetricsTable_t *metrics; + int ret, sensor_type; + u32 idx, sensors; + ssize_t size; + + size = (type == SMU_TEMP_METRIC_GPUBOARD) ? + sizeof(*gpuboard_temp_metrics) : sizeof(*baseboard_temp_metrics); + + if (!table) + goto out; + metrics = kzalloc(sizeof(SystemMetricsTable_t), GFP_KERNEL); + if (!metrics) + return -ENOMEM; + gpuboard_temp_metrics = (struct amdgpu_gpuboard_temp_metrics_v1_0 *)table; + baseboard_temp_metrics = (struct amdgpu_baseboard_temp_metrics_v1_0 *)table; + if (type == SMU_TEMP_METRIC_GPUBOARD) + smu_cmn_init_gpuboard_temp_metrics(gpuboard_temp_metrics, 1, 0); + else if (type == SMU_TEMP_METRIC_BASEBOARD) + smu_cmn_init_baseboard_temp_metrics(baseboard_temp_metrics, 1, 0); + + ret = smu_v13_0_12_get_system_metrics_table(smu, metrics, false); + if (ret) { + kfree(metrics); + return ret; + } + + if (type == SMU_TEMP_METRIC_GPUBOARD) { + gpuboard_temp_metrics->accumulation_counter = metrics->AccumulationCounter; + gpuboard_temp_metrics->label_version = metrics->LabelVersion; + gpuboard_temp_metrics->node_id = metrics->NodeIdentifier; + + idx = 0; + for (sensors = 0; sensors < NODE_TEMP_MAX_TEMP_ENTRIES; sensors++) { + if (metrics->NodeTemperatures[sensors] != -1) { + sensor_type = smu_v13_0_12_get_node_sensor_type(sensors); + gpuboard_temp_metrics->node_temp[idx] = + ((int)metrics->NodeTemperatures[sensors]) & 0xFFFFFF; + gpuboard_temp_metrics->node_temp[idx] |= (sensor_type << 24); + idx++; + } + } + + idx = 0; + + for (sensors = 0; sensors < SVI_MAX_TEMP_ENTRIES; sensors++) { + if (metrics->VrTemperatures[sensors] != -1) { + sensor_type = smu_v13_0_12_get_vr_sensor_type(sensors); + gpuboard_temp_metrics->vr_temp[idx] = + ((int)metrics->VrTemperatures[sensors]) & 0xFFFFFF; + gpuboard_temp_metrics->vr_temp[idx] |= (sensor_type << 24); + idx++; + } + } + } else if (type == SMU_TEMP_METRIC_BASEBOARD) { + baseboard_temp_metrics->accumulation_counter = metrics->AccumulationCounter; + baseboard_temp_metrics->label_version = metrics->LabelVersion; + baseboard_temp_metrics->node_id = metrics->NodeIdentifier; + + idx = 0; + for (sensors = 0; sensors < SYSTEM_TEMP_MAX_ENTRIES; sensors++) { + if (metrics->SystemTemperatures[sensors] != -1) { + sensor_type = smu_v13_0_12_get_system_sensor_type(sensors); + baseboard_temp_metrics->system_temp[idx] = + ((int)metrics->SystemTemperatures[sensors]) & 0xFFFFFF; + baseboard_temp_metrics->system_temp[idx] |= (sensor_type << 24); + idx++; + } + } + } + + kfree(metrics); + +out: + return size; +} + ssize_t smu_v13_0_12_get_xcp_metrics(struct smu_context *smu, struct amdgpu_xcp *xcp, void *table, void *smu_metrics) { const u8 num_jpeg_rings = NUM_JPEG_RINGS_FW; @@ -572,3 +813,8 @@ ssize_t smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, void return sizeof(*gpu_metrics); } + +const struct smu_temp_funcs smu_v13_0_12_temp_funcs = { + .temp_metrics_is_supported = smu_v13_0_12_is_temp_metrics_supported, + .get_temp_metrics = smu_v13_0_12_get_temp_metrics, +}; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index b2e5e53c80bb3..491da2131e968 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -4047,3 +4047,9 @@ void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu) amdgpu_mca_smu_init_funcs(smu->adev, &smu_v13_0_6_mca_smu_funcs); amdgpu_aca_set_smu_funcs(smu->adev, &smu_v13_0_6_aca_smu_funcs); } + +void smu_v13_0_6_set_temp_funcs(struct smu_context *smu) +{ + smu->smu_temp.temp_funcs = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) + == IP_VERSION(13, 0, 12)) ? &smu_v13_0_12_temp_funcs : NULL; +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h index 67b30674fd319..ece04ad724fb0 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h @@ -68,10 +68,12 @@ enum smu_v13_0_6_caps { SMU_CAP(HST_LIMIT_METRICS), SMU_CAP(BOARD_VOLTAGE), SMU_CAP(PLDM_VERSION), + SMU_CAP(TEMP_METRICS), SMU_CAP(ALL), }; extern void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu); +extern void smu_v13_0_6_set_temp_funcs(struct smu_context *smu); bool smu_v13_0_6_cap_supported(struct smu_context *smu, enum smu_v13_0_6_caps cap); int smu_v13_0_6_get_static_metrics_table(struct smu_context *smu); int smu_v13_0_6_get_metrics_table(struct smu_context *smu, void *metrics_table, @@ -88,4 +90,5 @@ ssize_t smu_v13_0_12_get_xcp_metrics(struct smu_context *smu, void *smu_metrics); extern const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[]; extern const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[]; +extern const struct smu_temp_funcs smu_v13_0_12_temp_funcs; #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h index a608cdbdada4c..d588f74b98de3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h @@ -65,6 +65,32 @@ header->structure_size = sizeof(*tmp); \ } while (0) +#define smu_cmn_init_baseboard_temp_metrics(ptr, fr, cr) \ + do { \ + typecheck(struct amdgpu_baseboard_temp_metrics_v##fr##_##cr *, \ + (ptr)); \ + struct amdgpu_baseboard_temp_metrics_v##fr##_##cr *tmp = (ptr); \ + struct metrics_table_header *header = \ + (struct metrics_table_header *)tmp; \ + memset(header, 0xFF, sizeof(*tmp)); \ + header->format_revision = fr; \ + header->content_revision = cr; \ + header->structure_size = sizeof(*tmp); \ + } while (0) + +#define smu_cmn_init_gpuboard_temp_metrics(ptr, fr, cr) \ + do { \ + typecheck(struct amdgpu_gpuboard_temp_metrics_v##fr##_##cr *, \ + (ptr)); \ + struct amdgpu_gpuboard_temp_metrics_v##fr##_##cr *tmp = (ptr); \ + struct metrics_table_header *header = \ + (struct metrics_table_header *)tmp; \ + memset(header, 0xFF, sizeof(*tmp)); \ + header->format_revision = fr; \ + header->content_revision = cr; \ + header->structure_size = sizeof(*tmp); \ + } while (0) + extern const int link_speed[]; /* Helper to Convert from PCIE Gen 1/2/3/4/5/6 to 0.1 GT/s speed units */ From 3cb8e3a9dac7bc8244d479d856938b0e5e44f864 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Sat, 2 Aug 2025 04:29:06 +0800 Subject: [PATCH 1665/2653] drm/amd/pm: Add temperature metrics sysfs entry Add temperature metrics sysfs entry to expose gpuboard/baseboard temperature metrics v2: Removed unused function, rename functions(Lijo) v3: Remove unnecessary initialization Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 135 +++++++++++++++++++++++++++++ 1 file changed, 135 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index dbaebe1415e25..c5b8bc0d130a7 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -2073,6 +2073,134 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd return 0; } +/** + * DOC: board + * + * Certain SOCs can support various board attributes reporting. This is useful + * for user application to monitor various board reated attributes. + * + * The amdgpu driver provides a sysfs API for reporting board attributes. Presently, + * only two types of attributes are reported, baseboard temperature and + * gpu board temperature. Both of them are reported as binary files. + * + * * .. code-block:: console + * + * hexdump /sys/bus/pci/devices/.../board/baseboard_temp + * + * hexdump /sys/bus/pci/devices/.../board/gpuboard_temp + * + */ + +/** + * DOC: baseboard_temp + * + * The amdgpu driver provides a sysfs API for retrieving current baseboard + * temperature metrics data. The file baseboard_temp is used for this. + * Reading the file will dump all the current baseboard temperature metrics data. + */ +static ssize_t amdgpu_get_baseboard_temp_metrics(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + ssize_t size; + int ret; + + ret = amdgpu_pm_get_access_if_active(adev); + if (ret) + return ret; + + size = amdgpu_dpm_get_temp_metrics(adev, SMU_TEMP_METRIC_BASEBOARD, NULL); + if (size <= 0) + goto out; + if (size >= PAGE_SIZE) { + ret = -ENOSPC; + goto out; + } + + amdgpu_dpm_get_temp_metrics(adev, SMU_TEMP_METRIC_BASEBOARD, buf); + +out: + amdgpu_pm_put_access(adev); + + if (ret) + return ret; + + return size; +} + +/** + * DOC: gpuboard_temp + * + * The amdgpu driver provides a sysfs API for retrieving current gpuboard + * temperature metrics data. The file gpuboard_temp is used for this. + * Reading the file will dump all the current gpuboard temperature metrics data. + */ +static ssize_t amdgpu_get_gpuboard_temp_metrics(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + ssize_t size; + int ret; + + ret = amdgpu_pm_get_access_if_active(adev); + if (ret) + return ret; + + size = amdgpu_dpm_get_temp_metrics(adev, SMU_TEMP_METRIC_GPUBOARD, NULL); + if (size <= 0) + goto out; + if (size >= PAGE_SIZE) { + ret = -ENOSPC; + goto out; + } + + amdgpu_dpm_get_temp_metrics(adev, SMU_TEMP_METRIC_GPUBOARD, buf); + +out: + amdgpu_pm_put_access(adev); + + if (ret) + return ret; + + return size; +} + +static DEVICE_ATTR(baseboard_temp, 0444, amdgpu_get_baseboard_temp_metrics, NULL); +static DEVICE_ATTR(gpuboard_temp, 0444, amdgpu_get_gpuboard_temp_metrics, NULL); + +static struct attribute *board_attrs[] = { + &dev_attr_baseboard_temp.attr, + &dev_attr_gpuboard_temp.attr, + NULL +}; + +static umode_t amdgpu_board_attr_visible(struct kobject *kobj, struct attribute *attr, int n) +{ + struct device *dev = kobj_to_dev(kobj); + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + + if (attr == &dev_attr_baseboard_temp.attr) { + if (!amdgpu_dpm_is_temp_metrics_supported(adev, SMU_TEMP_METRIC_BASEBOARD)) + return 0; + } + + if (attr == &dev_attr_gpuboard_temp.attr) { + if (!amdgpu_dpm_is_temp_metrics_supported(adev, SMU_TEMP_METRIC_GPUBOARD)) + return 0; + } + + return attr->mode; +} + +const struct attribute_group amdgpu_board_attr_group = { + .name = "board", + .attrs = board_attrs, + .is_visible = amdgpu_board_attr_visible, +}; + /* pm policy attributes */ struct amdgpu_pm_policy_attr { struct device_attribute dev_attr; @@ -4463,6 +4591,13 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) } #endif + if (amdgpu_dpm_is_temp_metrics_supported(adev, SMU_TEMP_METRIC_GPUBOARD)) { + ret = devm_device_add_group(adev->dev, + &amdgpu_board_attr_group); + if (ret) + goto err_out0; + } + adev->pm.sysfs_initialized = true; return 0; From 88134ee3c24c77a889099a558ccd636e8ac27e48 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Sat, 2 Aug 2025 04:32:29 +0800 Subject: [PATCH 1666/2653] drm/amd/pm: Enable temperature metrics caps Enable temperature metrics caps for smu_v13_0_12 Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 491da2131e968..083e6e9290ba6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -358,6 +358,11 @@ static void smu_v13_0_12_init_caps(struct smu_context *smu) smu_v13_0_6_cap_set(smu, SMU_CAP(BOARD_VOLTAGE)); smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION)); } + + if (fw_ver >= 0x04560700) { + if (!amdgpu_sriov_vf(smu->adev)) + smu_v13_0_6_cap_set(smu, SMU_CAP(TEMP_METRICS)); + } } static void smu_v13_0_6_init_caps(struct smu_context *smu) From 11fe437e7cc9785658e318f254196471c5acdb5e Mon Sep 17 00:00:00 2001 From: Yang Su Date: Tue, 5 Aug 2025 15:01:39 +0800 Subject: [PATCH 1667/2653] drm/amdkcl: test whether pm_sleep_ptr() exist It's caused by d96437e2b14 "drm/amdgpu: fix link error for !PM_SLEEP" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- include/kcl/kcl_pm.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/kcl/kcl_pm.h b/include/kcl/kcl_pm.h index 37c761718589e..05350df61dafc 100644 --- a/include/kcl/kcl_pm.h +++ b/include/kcl/kcl_pm.h @@ -35,4 +35,11 @@ #define DPM_FLAG_MAY_SKIP_RESUME BIT(3) #endif +/* + * v5.16-rc5-3-g1a3c7bb08826 + * PM: core: Add new *_PM_OPS macros, deprecate old ones + */ +#ifndef pm_sleep_ptr +#define pm_sleep_ptr(_ptr) PTR_IF(IS_ENABLED(CONFIG_PM_SLEEP), (_ptr)) +#endif #endif From 6741d4a515a4b2564f5cc99c2d29ef5924b767c7 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 6 Aug 2025 11:49:59 +0530 Subject: [PATCH 1668/2653] drm/amd/pm: Remove cache logic from SMUv13.0.12 Remove caching logic of temperature metrics from SMUv13.0.12. The caching logic needs to be moved to a higher level. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 30 +++++++------------ 1 file changed, 11 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index 920f60da9c5c7..aa427fa8ddd22 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -83,7 +83,6 @@ const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[SMU_FEATURE_COUNT] = SMU_13_0_12_FEA_MAP(SMU_FEATURE_PIT_BIT, FEATURE_PIT), }; -// clang-format off const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), @@ -361,31 +360,24 @@ int smu_v13_0_12_get_smu_metrics_data(struct smu_context *smu, return 0; } -static int smu_v13_0_12_get_system_metrics_table(struct smu_context *smu, void *metrics_table, - bool bypass_cache) +static int smu_v13_0_12_get_system_metrics_table(struct smu_context *smu, + void *metrics_table) { struct smu_table_context *smu_table = &smu->smu_table; uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size; struct smu_table *table = &smu_table->driver_table; int ret; - if (bypass_cache || !smu_table->tables[SMU_TABLE_TEMP_METRICS].metrics_time || - time_after(jiffies, - smu_table->tables[SMU_TABLE_TEMP_METRICS].metrics_time + - msecs_to_jiffies(1))) { - ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSystemMetricsTable, NULL); - if (ret) { - dev_info(smu->adev->dev, - "Failed to export system metrics table!\n"); - return ret; - } - - amdgpu_asic_invalidate_hdp(smu->adev, NULL); - memcpy(smu_table->metrics_table, table->cpu_addr, table_size); - - smu_table->tables[SMU_TABLE_TEMP_METRICS].metrics_time = jiffies; + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSystemMetricsTable, NULL); + if (ret) { + dev_info(smu->adev->dev, + "Failed to export system metrics table!\n"); + return ret; } + amdgpu_asic_invalidate_hdp(smu->adev, NULL); + memcpy(smu_table->metrics_table, table->cpu_addr, table_size); + if (metrics_table) memcpy(metrics_table, smu_table->metrics_table, sizeof(SystemMetricsTable_t)); @@ -544,7 +536,7 @@ static ssize_t smu_v13_0_12_get_temp_metrics(struct smu_context *smu, else if (type == SMU_TEMP_METRIC_BASEBOARD) smu_cmn_init_baseboard_temp_metrics(baseboard_temp_metrics, 1, 0); - ret = smu_v13_0_12_get_system_metrics_table(smu, metrics, false); + ret = smu_v13_0_12_get_system_metrics_table(smu, metrics); if (ret) { kfree(metrics); return ret; From 11ad0ba9a43accd79d20a81fd231dd22a97b5b98 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 6 Aug 2025 12:52:47 +0530 Subject: [PATCH 1669/2653] drm/amd/pm: Add cache logic for temperature metric Add caching logic for baseboard and gpuboard temperature metrics tables. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 18 +++++ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 78 ++++++++++++++++++- 2 files changed, 94 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index cd8d44c8e1811..813aa00bbe55a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -3835,6 +3835,9 @@ int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, static ssize_t smu_sys_get_temp_metrics(void *handle, enum smu_temp_metric_type type, void *table) { struct smu_context *smu = handle; + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *tables = smu_table->tables; + enum smu_table_id table_id; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) return -EOPNOTSUPP; @@ -3842,6 +3845,21 @@ static ssize_t smu_sys_get_temp_metrics(void *handle, enum smu_temp_metric_type if (!smu->smu_temp.temp_funcs || !smu->smu_temp.temp_funcs->get_temp_metrics) return -EOPNOTSUPP; + table_id = smu_metrics_get_temp_table_id(type); + + if (table_id == SMU_TABLE_COUNT) + return -EINVAL; + + /* If the request is to get size alone, return the cached table size */ + if (!table && tables[table_id].cache.size) + return tables[table_id].cache.size; + + if (smu_table_cache_is_valid(&tables[table_id])) { + memcpy(table, tables[table_id].cache.buffer, + tables[table_id].cache.size); + return tables[table_id].cache.size; + } + return smu->smu_temp.temp_funcs->get_temp_metrics(smu, type, table); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 06dffc89b3f2c..d36f803d83b49 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -249,6 +249,14 @@ struct smu_user_dpm_profile { tables[table_id].domain = d; \ } while (0) +struct smu_table_cache { + void *buffer; + size_t size; + /* interval in ms*/ + uint32_t interval; + unsigned long last_cache_time; +}; + struct smu_table { uint64_t size; uint32_t align; @@ -257,7 +265,7 @@ struct smu_table { void *cpu_addr; struct amdgpu_bo *bo; uint32_t version; - unsigned long metrics_time; + struct smu_table_cache cache; }; enum smu_perf_level_designation { @@ -323,7 +331,8 @@ enum smu_table_id { SMU_TABLE_ECCINFO, SMU_TABLE_COMBO_PPTABLE, SMU_TABLE_WIFIBAND, - SMU_TABLE_TEMP_METRICS, + SMU_TABLE_GPUBOARD_TEMP_METRICS, + SMU_TABLE_BASEBOARD_TEMP_METRICS, SMU_TABLE_COUNT, }; @@ -1682,6 +1691,71 @@ typedef struct { struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type); +static inline enum smu_table_id +smu_metrics_get_temp_table_id(enum smu_temp_metric_type type) +{ + switch (type) { + case SMU_TEMP_METRIC_BASEBOARD: + return SMU_TABLE_BASEBOARD_TEMP_METRICS; + case SMU_TEMP_METRIC_GPUBOARD: + return SMU_TABLE_GPUBOARD_TEMP_METRICS; + default: + return SMU_TABLE_COUNT; + } + + return SMU_TABLE_COUNT; +} + +static inline void smu_table_cache_update_time(struct smu_table *table, + unsigned long time) +{ + table->cache.last_cache_time = time; +} + +static inline bool smu_table_cache_is_valid(struct smu_table *table) +{ + if (!table->cache.buffer || !table->cache.last_cache_time || + !table->cache.interval || !table->cache.size || + time_after(jiffies, + table->cache.last_cache_time + + msecs_to_jiffies(table->cache.interval))) + return false; + + return true; +} + +static inline int smu_table_cache_init(struct smu_context *smu, + enum smu_table_id table_id, size_t size, + uint32_t cache_interval) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *tables = smu_table->tables; + + tables[table_id].cache.buffer = kzalloc(size, GFP_KERNEL); + if (!tables[table_id].cache.buffer) + return -ENOMEM; + + tables[table_id].cache.last_cache_time = 0; + tables[table_id].cache.interval = cache_interval; + tables[table_id].cache.size = size; + + return 0; +} + +static inline void smu_table_cache_fini(struct smu_context *smu, + enum smu_table_id table_id) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *tables = smu_table->tables; + + if (tables[table_id].cache.buffer) { + kfree(tables[table_id].cache.buffer); + tables[table_id].cache.buffer = NULL; + tables[table_id].cache.last_cache_time = 0; + tables[table_id].cache.interval = 0; + } +} + #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) int smu_get_power_limit(void *handle, uint32_t *limit, From 216071220eceee1fdd80aca632c3a5fb97b71727 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 6 Aug 2025 14:29:41 +0530 Subject: [PATCH 1670/2653] drm/amd/pm: Add caching to SMUv13.0.12 temp metric Add table caching logic to temperature metrics tables in SMUv13.0.12 Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 87 ++++++++++++++----- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 14 ++- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 2 + 3 files changed, 79 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index aa427fa8ddd22..fd06dcc2b81d5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -140,6 +140,42 @@ const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[SMU_MSG_MAX_COUNT] = MSG_MAP(GetSystemMetricsTable, PPSMC_MSG_GetSystemMetricsTable, 0), }; +int smu_v13_0_12_tables_init(struct smu_context *smu) +{ + struct amdgpu_baseboard_temp_metrics_v1_0 *baseboard_temp_metrics; + struct amdgpu_gpuboard_temp_metrics_v1_0 *gpuboard_temp_metrics; + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *tables = smu_table->tables; + struct smu_table_cache *cache; + int ret; + + ret = smu_table_cache_init(smu, SMU_TABLE_BASEBOARD_TEMP_METRICS, + sizeof(*baseboard_temp_metrics), 50); + if (ret) + return ret; + /* Initialize base board temperature metrics */ + cache = &(tables[SMU_TABLE_BASEBOARD_TEMP_METRICS].cache); + baseboard_temp_metrics = + (struct amdgpu_baseboard_temp_metrics_v1_0 *) cache->buffer; + smu_cmn_init_baseboard_temp_metrics(baseboard_temp_metrics, 1, 0); + /* Initialize GPU board temperature metrics */ + ret = smu_table_cache_init(smu, SMU_TABLE_GPUBOARD_TEMP_METRICS, + sizeof(*gpuboard_temp_metrics), 50); + if (ret) + return ret; + cache = &(tables[SMU_TABLE_GPUBOARD_TEMP_METRICS].cache); + gpuboard_temp_metrics = (struct amdgpu_gpuboard_temp_metrics_v1_0 *)cache->buffer; + smu_cmn_init_gpuboard_temp_metrics(gpuboard_temp_metrics, 1, 0); + + return 0; +} + +void smu_v13_0_12_tables_fini(struct smu_context *smu) +{ + smu_table_cache_fini(smu, SMU_TABLE_BASEBOARD_TEMP_METRICS); + smu_table_cache_fini(smu, SMU_TABLE_GPUBOARD_TEMP_METRICS); +} + static int smu_v13_0_12_get_enabled_mask(struct smu_context *smu, uint64_t *feature_mask) { @@ -514,34 +550,40 @@ static bool smu_v13_0_12_is_temp_metrics_supported(struct smu_context *smu, static ssize_t smu_v13_0_12_get_temp_metrics(struct smu_context *smu, enum smu_temp_metric_type type, void *table) { - struct amdgpu_gpuboard_temp_metrics_v1_0 *gpuboard_temp_metrics; struct amdgpu_baseboard_temp_metrics_v1_0 *baseboard_temp_metrics; - SystemMetricsTable_t *metrics; + struct amdgpu_gpuboard_temp_metrics_v1_0 *gpuboard_temp_metrics; + struct smu_table_context *smu_table = &smu->smu_table; + SystemMetricsTable_t *metrics = + (SystemMetricsTable_t *)smu_table->metrics_table; + + struct smu_table *data_table; int ret, sensor_type; u32 idx, sensors; ssize_t size; - size = (type == SMU_TEMP_METRIC_GPUBOARD) ? - sizeof(*gpuboard_temp_metrics) : sizeof(*baseboard_temp_metrics); - - if (!table) - goto out; - metrics = kzalloc(sizeof(SystemMetricsTable_t), GFP_KERNEL); - if (!metrics) - return -ENOMEM; - gpuboard_temp_metrics = (struct amdgpu_gpuboard_temp_metrics_v1_0 *)table; - baseboard_temp_metrics = (struct amdgpu_baseboard_temp_metrics_v1_0 *)table; - if (type == SMU_TEMP_METRIC_GPUBOARD) - smu_cmn_init_gpuboard_temp_metrics(gpuboard_temp_metrics, 1, 0); - else if (type == SMU_TEMP_METRIC_BASEBOARD) - smu_cmn_init_baseboard_temp_metrics(baseboard_temp_metrics, 1, 0); - - ret = smu_v13_0_12_get_system_metrics_table(smu, metrics); - if (ret) { - kfree(metrics); - return ret; + if (type == SMU_TEMP_METRIC_BASEBOARD) { + /* Initialize base board temperature metrics */ + data_table = + &smu->smu_table.tables[SMU_TABLE_BASEBOARD_TEMP_METRICS]; + baseboard_temp_metrics = + (struct amdgpu_baseboard_temp_metrics_v1_0 *) + data_table->cache.buffer; + size = sizeof(*baseboard_temp_metrics); + } else { + data_table = + &smu->smu_table.tables[SMU_TABLE_GPUBOARD_TEMP_METRICS]; + gpuboard_temp_metrics = + (struct amdgpu_gpuboard_temp_metrics_v1_0 *) + data_table->cache.buffer; + size = sizeof(*baseboard_temp_metrics); } + ret = smu_v13_0_12_get_system_metrics_table(smu, NULL); + if (ret) + return ret; + + smu_table_cache_update_time(data_table, jiffies); + if (type == SMU_TEMP_METRIC_GPUBOARD) { gpuboard_temp_metrics->accumulation_counter = metrics->AccumulationCounter; gpuboard_temp_metrics->label_version = metrics->LabelVersion; @@ -586,9 +628,8 @@ static ssize_t smu_v13_0_12_get_temp_metrics(struct smu_context *smu, } } - kfree(metrics); + memcpy(table, data_table->cache.buffer, size); -out: return size; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 083e6e9290ba6..d6d8d2c39ef71 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -362,6 +362,8 @@ static void smu_v13_0_12_init_caps(struct smu_context *smu) if (fw_ver >= 0x04560700) { if (!amdgpu_sriov_vf(smu->adev)) smu_v13_0_6_cap_set(smu, SMU_CAP(TEMP_METRICS)); + } else { + smu_v13_0_12_tables_fini(smu); } } @@ -576,6 +578,9 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu) return -ENOMEM; } + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) + return smu_v13_0_12_tables_init(smu); + return 0; } @@ -846,6 +851,13 @@ static int smu_v13_0_6_init_smc_tables(struct smu_context *smu) return ret; } +static int smu_v13_0_6_fini_smc_tables(struct smu_context *smu) +{ + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) + smu_v13_0_12_tables_fini(smu); + return smu_v13_0_fini_smc_tables(smu); +} + static int smu_v13_0_6_get_allowed_feature_mask(struct smu_context *smu, uint32_t *feature_mask, uint32_t num) @@ -3991,7 +4003,7 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { .init_microcode = smu_v13_0_6_init_microcode, .fini_microcode = smu_v13_0_fini_microcode, .init_smc_tables = smu_v13_0_6_init_smc_tables, - .fini_smc_tables = smu_v13_0_fini_smc_tables, + .fini_smc_tables = smu_v13_0_6_fini_smc_tables, .init_power = smu_v13_0_init_power, .fini_power = smu_v13_0_fini_power, .check_fw_status = smu_v13_0_6_check_fw_status, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h index ece04ad724fb0..f39dbfdd7a2f2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h @@ -88,6 +88,8 @@ ssize_t smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, void ssize_t smu_v13_0_12_get_xcp_metrics(struct smu_context *smu, struct amdgpu_xcp *xcp, void *table, void *smu_metrics); +int smu_v13_0_12_tables_init(struct smu_context *smu); +void smu_v13_0_12_tables_fini(struct smu_context *smu); extern const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[]; extern const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[]; extern const struct smu_temp_funcs smu_v13_0_12_temp_funcs; From e1655bb1b3e3f251530f507e832acd19afdc2fe0 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 7 Aug 2025 15:14:42 +0800 Subject: [PATCH 1671/2653] drm/amdkcl: test whether PTR_IF() exist It's caused by d96437e2b14 "drm/amdgpu: fix link error for !PM_SLEEP" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- include/kcl/kcl_kernel.h | 4 ++++ include/kcl/kcl_pm.h | 1 + 2 files changed, 5 insertions(+) diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index 47e8853f7e144..64e242971f3dc 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -34,4 +34,8 @@ #define TAINT_CPU_OUT_OF_SPEC TAINT_UNSAFE_SMP #endif +#ifndef PTR_IF +#define PTR_IF(cond, ptr) ((cond) ? (ptr) : NULL) +#endif + #endif /* AMDKCL_KERNEL_H */ diff --git a/include/kcl/kcl_pm.h b/include/kcl/kcl_pm.h index 05350df61dafc..f3279a503a8ed 100644 --- a/include/kcl/kcl_pm.h +++ b/include/kcl/kcl_pm.h @@ -9,6 +9,7 @@ #include #include +#include /* * v5.7-rc2-7-ge07515563d01 From 6b029665150ee64dda1b0e5e6838fc646151c3e7 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 7 Aug 2025 15:16:25 +0800 Subject: [PATCH 1672/2653] drm/amdkcl: wrap code under HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE it's caused by 192650eee "drm/amd/display: Add primary plane to commits for correct VRR handling" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 4c9d1d41ac8b7..4ce37a42f929c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -676,6 +676,7 @@ static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, return -EINVAL; } +#ifdef HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE if (!state->legacy_cursor_update && amdgpu_dm_crtc_vrr_active(dm_crtc_state)) { struct drm_plane_state *primary_state; @@ -684,6 +685,7 @@ static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, if (IS_ERR(primary_state)) return PTR_ERR(primary_state); } +#endif /* In some use cases, like reset, no stream is attached */ if (!dm_crtc_state->stream) From 6922bbd568e5ae543a9ed392d6ddd5b24b16bb9e Mon Sep 17 00:00:00 2001 From: Xiang Liu Date: Mon, 4 Aug 2025 22:46:30 +0800 Subject: [PATCH 1673/2653] drm/amdgpu: Generate BP threshold exceed CPER once threshold exceeded The bad pages threshold exceed CPER should be generated once threshold exceeded, no matter the bad_page_threshold setted or not. Signed-off-by: Xiang Liu Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 4 ++++ drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index c3c908cc08595..e3e6b32e48308 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -765,6 +765,10 @@ amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) dev_warn(adev->dev, "Saved bad pages %d reaches threshold value %d\n", control->ras_num_bad_pages, ras->bad_page_cnt_threshold); + + if (adev->cper.enabled && amdgpu_cper_generate_bp_threshold_record(adev)) + dev_warn(adev->dev, "fail to generate bad page threshold cper records\n"); + if ((amdgpu_bad_page_threshold != -1) && (amdgpu_bad_page_threshold != -2)) { control->tbl_hdr.header = RAS_TABLE_HDR_BAD; diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index e2bf4006fc28a..26449930216f8 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -764,10 +764,6 @@ int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) ret = smu_send_rma_reason(smu); mutex_unlock(&adev->pm.mutex); - if (adev->cper.enabled) - if (amdgpu_cper_generate_bp_threshold_record(adev)) - dev_warn(adev->dev, "fail to generate bad page threshold cper records\n"); - return ret; } From 02dcdcfc0249e90a22599e0f29cf5fa149b4584a Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 23 Jul 2025 10:43:00 +0530 Subject: [PATCH 1674/2653] drm/amdgpu: Log reset source during recovery To get more context, add reset source to identify the source of gpu recovery - job timeout, RAS, HWS hang etc. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 01a46256ebdd2..7ea7cb184a608 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6496,8 +6496,9 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, emergency_restart(); } - dev_info(adev->dev, "GPU %s begin!\n", - need_emergency_restart ? "jobs stop":"reset"); + dev_info(adev->dev, "GPU %s begin!. Source: %d\n", + need_emergency_restart ? "jobs stop" : "reset", + reset_context->src); if (!amdgpu_sriov_vf(adev)) hive = amdgpu_get_xgmi_hive(adev); From d9c5a6ed7f0d38e45a9f3e80d6a4a99b26869f9d Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 5 Aug 2025 17:40:09 +0530 Subject: [PATCH 1675/2653] drm/amdgpu/vcn: Fix double-free of vcn dump buffer The buffer is already freed as part of amdgpu_vcn_reg_dump_fini(). The issue is introduced by below patch series. Fixes: 699853ae00ca ("drm/amdgpu/vcn: Add regdump helper functions") Signed-off-by: Lijo Lazar Reviewed-by: Sathishkumar S --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 1 + drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 1 - drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 2 -- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 2 -- 4 files changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index b497a67141384..050a5411aae54 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -1549,6 +1549,7 @@ int amdgpu_vcn_reg_dump_init(struct amdgpu_device *adev, static void amdgpu_vcn_reg_dump_fini(struct amdgpu_device *adev) { kfree(adev->vcn.ip_dump); + adev->vcn.ip_dump = NULL; adev->vcn.reg_list = NULL; adev->vcn.reg_count = 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index ff2a85619f232..95173156f956a 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -354,7 +354,6 @@ static int vcn_v3_0_sw_fini(struct amdgpu_ip_block *ip_block) return r; } - kfree(adev->vcn.ip_dump); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index c6450ed65c12d..019bd362edb22 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -280,8 +280,6 @@ static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) return r; } - kfree(adev->vcn.ip_dump); - return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index f785467370d9a..75c884a8f556b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -275,8 +275,6 @@ static int vcn_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block) return r; } - kfree(adev->vcn.ip_dump); - return 0; } From 107fc4ef4df8c91da8648baafa0f6e855a0f4ef6 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 24 Jul 2025 13:05:12 +0530 Subject: [PATCH 1676/2653] drm/amdgpu: Prevent hardware access in dpc state Don't allow hardware access while in dpc state. Signed-off-by: Lijo Lazar Reviewed-by: Ce Sun --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 1 + 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 7ea7cb184a608..2c8259c5b8811 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6311,11 +6311,7 @@ static int amdgpu_device_asic_reset(struct amdgpu_device *adev, retry: /* Rest of adevs pre asic reset from XGMI hive. */ list_for_each_entry(tmp_adev, device_list, reset_list) { - if (amdgpu_reset_in_dpc(adev)) - tmp_adev->no_hw_access = true; r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context); - if (amdgpu_reset_in_dpc(adev)) - tmp_adev->no_hw_access = false; /*TODO Should we stop ?*/ if (r) { dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h index 0f7e5ed50c144..6b9f550cb0c24 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h @@ -180,6 +180,7 @@ static inline void amdgpu_reset_set_dpc_status(struct amdgpu_device *adev, bool status) { adev->pcie_reset_ctx.occurs_dpc = status; + adev->no_hw_access = status; } static inline bool amdgpu_reset_in_dpc(struct amdgpu_device *adev) From ecbb240acdb81e06168c62ae79670313491ed02a Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 4 Aug 2025 13:13:06 +0530 Subject: [PATCH 1677/2653] drm/amdgpu: Add helpers to set/get unique ids Add a struct to store unique id information for each type. Add helper to fetch the unique id. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 20 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 71 ++++++++++++++++++++++ 2 files changed, 91 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 1bc0d6c906662..ec8532688ef41 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -836,6 +836,20 @@ struct amdgpu_ip_map_info { uint32_t mask); }; +enum amdgpu_uid_type { + AMDGPU_UID_TYPE_XCD, + AMDGPU_UID_TYPE_AID, + AMDGPU_UID_TYPE_SOC, + AMDGPU_UID_TYPE_MAX +}; + +#define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ + +struct amdgpu_uid { + uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; + struct amdgpu_device *adev; +}; + struct amd_powerplay { void *pp_handle; const struct amd_pm_funcs *pp_funcs; @@ -1330,6 +1344,7 @@ struct amdgpu_device { struct list_head userq_mgr_list; struct mutex userq_mutex; bool userq_halt_for_enforce_isolation; + struct amdgpu_uid *uid_info; }; static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, @@ -1821,4 +1836,9 @@ static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev) return 0; } +void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, + enum amdgpu_uid_type type, uint8_t inst, + uint64_t uid); +uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, + enum amdgpu_uid_type type, uint8_t inst); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2c8259c5b8811..af101e6870566 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2700,6 +2700,24 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) return err; } +static void amdgpu_uid_init(struct amdgpu_device *adev) +{ + /* Initialize the UID for the device */ + adev->uid_info = kzalloc(sizeof(struct amdgpu_uid), GFP_KERNEL); + if (!adev->uid_info) { + dev_warn(adev->dev, "Failed to allocate memory for UID\n"); + return; + } + adev->uid_info->adev = adev; +} + +static void amdgpu_uid_fini(struct amdgpu_device *adev) +{ + /* Free the UID memory */ + kfree(adev->uid_info); + adev->uid_info = NULL; +} + /** * amdgpu_device_ip_early_init - run early init for hardware IPs * @@ -2883,6 +2901,8 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) if (adev->gmc.xgmi.supported) amdgpu_xgmi_early_init(adev); + if (amdgpu_is_multi_aid(adev)) + amdgpu_uid_init(adev); ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); if (ip_block->status.valid != false) amdgpu_amdkfd_device_probe(adev); @@ -3673,6 +3693,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev) } amdgpu_ras_fini(adev); + amdgpu_uid_fini(adev); return 0; } @@ -7550,3 +7571,53 @@ ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset) size += sysfs_emit_at(buf, size, "\n"); return size; } + +void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, + enum amdgpu_uid_type type, uint8_t inst, + uint64_t uid) +{ + if (!uid_info) + return; + + if (type >= AMDGPU_UID_TYPE_MAX) { + dev_err_once(uid_info->adev->dev, "Invalid UID type %d\n", + type); + return; + } + + if (inst >= AMDGPU_UID_INST_MAX) { + dev_err_once(uid_info->adev->dev, "Invalid UID instance %d\n", + inst); + return; + } + + if (uid_info->uid[type][inst] != 0) { + dev_warn_once( + uid_info->adev->dev, + "Overwriting existing UID %llu for type %d instance %d\n", + uid_info->uid[type][inst], type, inst); + } + + uid_info->uid[type][inst] = uid; +} + +u64 amdgpu_device_get_uid(struct amdgpu_uid *uid_info, + enum amdgpu_uid_type type, uint8_t inst) +{ + if (!uid_info) + return 0; + + if (type >= AMDGPU_UID_TYPE_MAX) { + dev_err_once(uid_info->adev->dev, "Invalid UID type %d\n", + type); + return 0; + } + + if (inst >= AMDGPU_UID_INST_MAX) { + dev_err_once(uid_info->adev->dev, "Invalid UID instance %d\n", + inst); + return 0; + } + + return uid_info->uid[type][inst]; +} \ No newline at end of file From 3354271b65cc4f98d08f7f865b29c6721de13fbf Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 4 Aug 2025 13:29:05 +0530 Subject: [PATCH 1678/2653] drm/amd/pm: Add unique ids for SMUv13.0.6 SOCs Fetch and store the unique ids for AIDs/XCDs in SMUv13.0.6 SOCs. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index d6d8d2c39ef71..bc4900774a035 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -984,7 +984,7 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu) struct PPTable_t *pptable = (struct PPTable_t *)smu_table->driver_pptable; int version = smu_v13_0_6_get_metrics_version(smu); - int ret, i, retry = 100; + int ret, i, retry = 100, n; uint32_t table_version; uint16_t max_speed; uint8_t max_width; @@ -1046,6 +1046,23 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu) pptable->PublicSerialNumber_AID = GET_METRIC_FIELD(PublicSerialNumber_AID, version)[0]; + amdgpu_device_set_uid(smu->adev->uid_info, AMDGPU_UID_TYPE_SOC, + 0, pptable->PublicSerialNumber_AID); + n = ARRAY_SIZE(metrics_v0->PublicSerialNumber_AID); + for (i = 0; i < n; i++) { + amdgpu_device_set_uid( + smu->adev->uid_info, AMDGPU_UID_TYPE_AID, i, + GET_METRIC_FIELD(PublicSerialNumber_AID, + version)[i]); + } + n = ARRAY_SIZE(metrics_v0->PublicSerialNumber_XCD); + for (i = 0; i < n; i++) { + amdgpu_device_set_uid( + smu->adev->uid_info, AMDGPU_UID_TYPE_XCD, i, + GET_METRIC_FIELD(PublicSerialNumber_XCD, + version)[i]); + } + pptable->Init = true; if (smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) { ret = smu_v13_0_6_get_static_metrics_table(smu); From bad03faf2e5a0c36cf17312089dd5ae1b8a7a514 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 6 Aug 2025 18:15:22 +0530 Subject: [PATCH 1679/2653] drm/amd/display: Add NULL check for stream before dereference in 'dm_vupdate_high_irq' Add a NULL check for acrtc->dm_irq_params.stream before accessing its members. Fixes below: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:623 dm_vupdate_high_irq() warn: variable dereferenced before check 'acrtc->dm_irq_params.stream' (see line 615) 614 if (vrr_active) { 615 bool replay_en = acrtc->dm_irq_params.stream->link->replay_settings.replay_feature_enabled; ^^^^^^^^^^^^^^^^^^^^^^^^^^^ 616 bool psr_en = acrtc->dm_irq_params.stream->link->psr_settings.psr_feature_enabled; ^^^^^^^^^^^^^^^^^^^^^^^^^^^ New dereferences 617 bool fs_active_var_en = acrtc->dm_irq_params.freesync_config.state 618 == VRR_STATE_ACTIVE_VARIABLE; 619 620 amdgpu_dm_crtc_handle_vblank(acrtc); 621 622 /* BTR processing for pre-DCE12 ASICs */ 623 if (acrtc->dm_irq_params.stream && ^^^^^^^^^^^^^^^^^^^^^^^^^^^ But the existing code assumed it could be NULL. Someone is wrong. 624 adev->family < AMDGPU_FAMILY_AI) { 625 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 'Fixes: 7a586ce03c42 ("drm/amd/display: more liberal vmin/vmax update for freesync")' Reported-by: Dan Carpenter Cc: Alex Hung Cc: Aurabindo Pillai Cc: Roman Li Cc: ChiaHsuan Chung Cc: Harry Wentland Cc: Ray Wu Cc: Daniel Wheeler Cc: Nicholas Kazlauskas Signed-off-by: Srinivasan Shanmugam Reviewed-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 13cd73964291f..cfc1e5f62b468 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -623,7 +623,7 @@ static void dm_vupdate_high_irq(void *interrupt_params) * page-flip completion events that have been queued to us * if a pageflip happened inside front-porch. */ - if (vrr_active) { + if (vrr_active && acrtc->dm_irq_params.stream) { bool replay_en = acrtc->dm_irq_params.stream->link->replay_settings.replay_feature_enabled; bool psr_en = acrtc->dm_irq_params.stream->link->psr_settings.psr_feature_enabled; bool fs_active_var_en = acrtc->dm_irq_params.freesync_config.state @@ -632,8 +632,7 @@ static void dm_vupdate_high_irq(void *interrupt_params) amdgpu_dm_crtc_handle_vblank(acrtc); /* BTR processing for pre-DCE12 ASICs */ - if (acrtc->dm_irq_params.stream && - adev->family < AMDGPU_FAMILY_AI) { + if (adev->family < AMDGPU_FAMILY_AI) { spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); mod_freesync_handle_v_update( adev->dm.freesync_module, From 4fcd0f21722c55fe5aee02917ce89a33158db2ff Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 30 Jul 2025 11:16:05 -0400 Subject: [PATCH 1680/2653] drm/amdgpu/discovery: fix fw based ip discovery We only need the fw based discovery table for sysfs. No need to parse it. Additionally parsing some of the board specific tables may result in incorrect data on some boards. just load the binary and don't parse it on those boards. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4441 Fixes: 80a0e8282933 ("drm/amdgpu/discovery: optionally use fw based ip discovery") Cc: stable@vger.kernel.org Reviewed-by: Mario Limonciello (AMD) Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 72 ++++++++++--------- 2 files changed, 41 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index af101e6870566..95b4831983cc0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2595,9 +2595,6 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) adev->firmware.gpu_info_fw = NULL; - if (adev->mman.discovery_bin) - return 0; - switch (adev->asic_type) { default: return 0; @@ -2619,6 +2616,8 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) chip_name = "arcturus"; break; case CHIP_NAVI12: + if (adev->mman.discovery_bin) + return 0; chip_name = "navi12"; break; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index bcff16cb94f3c..322a989aca334 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -2571,40 +2571,11 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_VEGA10: - case CHIP_VEGA12: - case CHIP_RAVEN: - case CHIP_VEGA20: - case CHIP_ARCTURUS: - case CHIP_ALDEBARAN: - /* this is not fatal. We have a fallback below - * if the new firmwares are not present. some of - * this will be overridden below to keep things - * consistent with the current behavior. + /* This is not fatal. We only need the discovery + * binary for sysfs. We don't need it for a + * functional system. */ - r = amdgpu_discovery_reg_base_init(adev); - if (!r) { - amdgpu_discovery_harvest_ip(adev); - amdgpu_discovery_get_gfx_info(adev); - amdgpu_discovery_get_mall_info(adev); - amdgpu_discovery_get_vcn_info(adev); - } - break; - default: - r = amdgpu_discovery_reg_base_init(adev); - if (r) { - drm_err(&adev->ddev, "discovery failed: %d\n", r); - return r; - } - - amdgpu_discovery_harvest_ip(adev); - amdgpu_discovery_get_gfx_info(adev); - amdgpu_discovery_get_mall_info(adev); - amdgpu_discovery_get_vcn_info(adev); - break; - } - - switch (adev->asic_type) { - case CHIP_VEGA10: + amdgpu_discovery_init(adev); vega10_reg_base_init(adev); adev->sdma.num_instances = 2; adev->gmc.num_umc = 4; @@ -2627,6 +2598,11 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); break; case CHIP_VEGA12: + /* This is not fatal. We only need the discovery + * binary for sysfs. We don't need it for a + * functional system. + */ + amdgpu_discovery_init(adev); vega10_reg_base_init(adev); adev->sdma.num_instances = 2; adev->gmc.num_umc = 4; @@ -2649,6 +2625,11 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); break; case CHIP_RAVEN: + /* This is not fatal. We only need the discovery + * binary for sysfs. We don't need it for a + * functional system. + */ + amdgpu_discovery_init(adev); vega10_reg_base_init(adev); adev->sdma.num_instances = 1; adev->vcn.num_vcn_inst = 1; @@ -2690,6 +2671,11 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) } break; case CHIP_VEGA20: + /* This is not fatal. We only need the discovery + * binary for sysfs. We don't need it for a + * functional system. + */ + amdgpu_discovery_init(adev); vega20_reg_base_init(adev); adev->sdma.num_instances = 2; adev->gmc.num_umc = 8; @@ -2713,6 +2699,11 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); break; case CHIP_ARCTURUS: + /* This is not fatal. We only need the discovery + * binary for sysfs. We don't need it for a + * functional system. + */ + amdgpu_discovery_init(adev); arct_reg_base_init(adev); adev->sdma.num_instances = 8; adev->vcn.num_vcn_inst = 2; @@ -2741,6 +2732,11 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); break; case CHIP_ALDEBARAN: + /* This is not fatal. We only need the discovery + * binary for sysfs. We don't need it for a + * functional system. + */ + amdgpu_discovery_init(adev); aldebaran_reg_base_init(adev); adev->sdma.num_instances = 5; adev->vcn.num_vcn_inst = 2; @@ -2767,6 +2763,16 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); break; default: + r = amdgpu_discovery_reg_base_init(adev); + if (r) { + drm_err(&adev->ddev, "discovery failed: %d\n", r); + return r; + } + + amdgpu_discovery_harvest_ip(adev); + amdgpu_discovery_get_gfx_info(adev); + amdgpu_discovery_get_mall_info(adev); + amdgpu_discovery_get_vcn_info(adev); break; } From 91a1de8acad13a947da21716b832e9bc50a9415a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 4 Aug 2025 11:40:20 -0400 Subject: [PATCH 1681/2653] drm/amdgpu: add missing vram lost check for LEGACY RESET Legacy resets reset the memory controllers so VRAM contents may be unreliable after reset. Reviewed-by: Hawking Zhang Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 95b4831983cc0..847b28b78f4cf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3315,6 +3315,7 @@ static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev) * always assumed to be lost. */ switch (amdgpu_asic_reset_method(adev)) { + case AMD_RESET_METHOD_LEGACY: case AMD_RESET_METHOD_LINK: case AMD_RESET_METHOD_BACO: case AMD_RESET_METHOD_MODE1: From ebb7952c8366fc9d1a5de98fcab8b5a0ab295ca8 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 4 Aug 2025 13:36:52 +0530 Subject: [PATCH 1682/2653] drm/amd/pm: Add unique ids for SMUv13.0.12 SOCs Fetch and store the unique ids for AIDs/XCDs in SMUv13.0.12 SOCs. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index fd06dcc2b81d5..ea2682f9d579d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -257,7 +257,7 @@ int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu) struct PPTable_t *pptable = (struct PPTable_t *)smu_table->driver_pptable; uint32_t table_version; - int ret, i; + int ret, i, n; if (!pptable->Init) { ret = smu_v13_0_6_get_static_metrics_table(smu); @@ -296,6 +296,22 @@ int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu) /* use AID0 serial number by default */ pptable->PublicSerialNumber_AID = static_metrics->PublicSerialNumber_AID[0]; + + amdgpu_device_set_uid(smu->adev->uid_info, AMDGPU_UID_TYPE_SOC, + 0, pptable->PublicSerialNumber_AID); + n = ARRAY_SIZE(static_metrics->PublicSerialNumber_AID); + for (i = 0; i < n; i++) { + amdgpu_device_set_uid( + smu->adev->uid_info, AMDGPU_UID_TYPE_AID, i, + static_metrics->PublicSerialNumber_AID[i]); + } + n = ARRAY_SIZE(static_metrics->PublicSerialNumber_XCD); + for (i = 0; i < n; i++) { + amdgpu_device_set_uid( + smu->adev->uid_info, AMDGPU_UID_TYPE_XCD, i, + static_metrics->PublicSerialNumber_XCD[i]); + } + ret = smu_v13_0_12_fru_get_product_info(smu, static_metrics); if (ret) return ret; From bf2a5bfcf0f92180f4b9d67b5cc25a23d0d9ab6e Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 4 Aug 2025 13:53:21 +0530 Subject: [PATCH 1683/2653] drm/amdgpu: Assign unique id to compute partition Assign unique id to compute partition. This is the unique id of the first XCD instance belonging to the partition. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 20 ++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h | 1 + 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c index 3f196ff6b066c..6b375665507db 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c @@ -120,6 +120,25 @@ static void __amdgpu_xcp_add_block(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, xcp->valid = true; } +static void __amdgpu_xcp_set_unique_id(struct amdgpu_xcp_mgr *xcp_mgr, + int xcp_id) +{ + struct amdgpu_xcp *xcp = &xcp_mgr->xcp[xcp_id]; + struct amdgpu_device *adev = xcp_mgr->adev; + uint32_t inst_mask; + uint64_t uid; + int i; + + if (!amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask) && + inst_mask) { + i = GET_INST(GC, (ffs(inst_mask) - 1)); + uid = amdgpu_device_get_uid(xcp_mgr->adev->uid_info, + AMDGPU_UID_TYPE_XCD, i); + if (uid) + xcp->unique_id = uid; + } +} + int amdgpu_xcp_init(struct amdgpu_xcp_mgr *xcp_mgr, int num_xcps, int mode) { struct amdgpu_device *adev = xcp_mgr->adev; @@ -158,6 +177,7 @@ int amdgpu_xcp_init(struct amdgpu_xcp_mgr *xcp_mgr, int num_xcps, int mode) else xcp_mgr->xcp[i].mem_id = mem_id; } + __amdgpu_xcp_set_unique_id(xcp_mgr, i); } xcp_mgr->num_xcps = num_xcps; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h index 70a0f8400b578..1928d9e224fca 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h @@ -112,6 +112,7 @@ struct amdgpu_xcp { struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; struct amdgpu_xcp_mgr *xcp_mgr; struct kobject kobj; + uint64_t unique_id; }; struct amdgpu_xcp_mgr { From 370d082f377c9d212919208a50e9c2374bf87652 Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Tue, 5 Aug 2025 21:28:25 +0530 Subject: [PATCH 1684/2653] drm/amdgpu/jpeg: Hold pg_lock before jpeg poweroff Acquire jpeg_pg_lock before changes to jpeg power state and release it after power off from idle work handler. Signed-off-by: Sathishkumar S Reviewed-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c index 82d58ac7afb01..5d5e9ee83a5d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c @@ -121,10 +121,12 @@ static void amdgpu_jpeg_idle_work_handler(struct work_struct *work) fences += amdgpu_fence_count_emitted(&adev->jpeg.inst[i].ring_dec[j]); } - if (!fences && !atomic_read(&adev->jpeg.total_submission_cnt)) + if (!fences && !atomic_read(&adev->jpeg.total_submission_cnt)) { + mutex_lock(&adev->jpeg.jpeg_pg_lock); amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, AMD_PG_STATE_GATE); - else + mutex_unlock(&adev->jpeg.jpeg_pg_lock); + } else schedule_delayed_work(&adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT); } From 764f96d56886e1ca16a21d1c1457fe081d109868 Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Tue, 5 Aug 2025 21:35:10 +0530 Subject: [PATCH 1685/2653] drm/amdgpu/vcn: Hold pg_lock before vcn power off Acquire vcn_pg_lock before changes to vcn power state and release it after power off in idle work handler. Signed-off-by: Sathishkumar S Reviewed-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 050a5411aae54..9a76e11d1c184 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -443,7 +443,9 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work) fences += fence[i]; if (!fences && !atomic_read(&vcn_inst->total_submission_cnt)) { + mutex_lock(&vcn_inst->vcn_pg_lock); vcn_inst->set_pg_state(vcn_inst, AMD_PG_STATE_GATE); + mutex_unlock(&vcn_inst->vcn_pg_lock); mutex_lock(&adev->vcn.workload_profile_mutex); if (adev->vcn.workload_profile_active) { r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, From 576ae7416261c81fb1018f6a342c42fe94206a91 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 7 Aug 2025 16:34:09 +0800 Subject: [PATCH 1686/2653] drm/amdkcl: test whether pm_ptr() exist It's caused by d96437e2b14f621ba4cb8ec96cccd0c60a6ef7d9 "drm/amdgpu: fix link error for !PM_SLEEP" Signed-off-by: Yang Su --- include/kcl/kcl_pm.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/kcl/kcl_pm.h b/include/kcl/kcl_pm.h index f3279a503a8ed..57795e4497d0c 100644 --- a/include/kcl/kcl_pm.h +++ b/include/kcl/kcl_pm.h @@ -43,4 +43,12 @@ #ifndef pm_sleep_ptr #define pm_sleep_ptr(_ptr) PTR_IF(IS_ENABLED(CONFIG_PM_SLEEP), (_ptr)) #endif + +/* + * v5.8-rc7-1-g7a82e97a11b9 + * PM: core: introduce pm_ptr() macro + */ +#ifndef pm_ptr +#define pm_ptr(_ptr) PTR_IF(IS_ENABLED(CONFIG_PM), (_ptr)) #endif +#endif \ No newline at end of file From 0d2ee530e00c316786d38a8db8b09093cb8b6fba Mon Sep 17 00:00:00 2001 From: Yang Su Date: Fri, 8 Aug 2025 10:45:58 +0800 Subject: [PATCH 1687/2653] drm/amdkcl: Fix atomic state access in crtc_helper_atomic_check When HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE is not enabled, the atomic check helper lacks direct access to the drm_atomic_state Signed-off-by: Yang Su --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 4ce37a42f929c..d6eacb03b6e29 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -632,6 +632,7 @@ static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, #else struct drm_crtc_state *crtc_state) { + struct drm_atomic_state *state = crtc_state->state; #endif struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct dc *dc = adev->dm.dc; @@ -676,7 +677,6 @@ static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, return -EINVAL; } -#ifdef HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE if (!state->legacy_cursor_update && amdgpu_dm_crtc_vrr_active(dm_crtc_state)) { struct drm_plane_state *primary_state; @@ -685,7 +685,6 @@ static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, if (IS_ERR(primary_state)) return PTR_ERR(primary_state); } -#endif /* In some use cases, like reset, no stream is attached */ if (!dm_crtc_state->stream) From 1f3cdb940035fb2e9b388e84cde7c3bfdede484b Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Sat, 28 Jun 2025 10:50:25 +0530 Subject: [PATCH 1688/2653] drm/amdgpu: Save and restore switch state During a DPC error kernel waits for the link to be active before notifying downstream devices. On certain platforms with Broadcom switch in synthetiic mode, switch responds with values even though the link is not fully ready. The config space restoration done by pcie port driver for SWUS/DS of dGPU is thus not effective as the switch is still doing internal enumeration. As a workaround, save state of SWUS/DS device in driver. Add additional check to see if link is active and restore the values during DPC error callbacks. Signed-off-by: Lijo Lazar Reviewed-by: Yang Wang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 85 ++++++++++++++++++++-- 2 files changed, 83 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index ec8532688ef41..db83103e531be 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -927,6 +927,9 @@ struct amdgpu_pcie_reset_ctx { bool in_link_reset; bool occurs_dpc; bool audio_suspended; + struct pci_dev *swus; + struct pci_saved_state *swus_pcistate; + struct pci_saved_state *swds_pcistate; }; /* diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 847b28b78f4cf..5ae0ebd6da45f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -180,6 +180,8 @@ struct amdgpu_init_level amdgpu_init_minimal_xgmi = { BIT(AMD_IP_BLOCK_TYPE_PSP) }; +static void amdgpu_device_load_switch_state(struct amdgpu_device *adev); + static inline bool amdgpu_ip_member_of_hwini(struct amdgpu_device *adev, enum amd_ip_block_type block) { @@ -5064,7 +5066,8 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev) adev->reset_domain = NULL; kfree(adev->pci_state); - + kfree(adev->pcie_reset_ctx.swds_pcistate); + kfree(adev->pcie_reset_ctx.swus_pcistate); } /** @@ -7050,16 +7053,34 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) struct amdgpu_device *tmp_adev; struct amdgpu_hive_info *hive; struct list_head device_list; - int r = 0, i; + struct pci_dev *link_dev; + int r = 0, i, timeout; u32 memsize; + u16 status; dev_info(adev->dev, "PCI error: slot reset callback!!\n"); memset(&reset_context, 0, sizeof(reset_context)); - /* wait for asic to come out of reset */ - msleep(700); + if (adev->pcie_reset_ctx.swus) + link_dev = adev->pcie_reset_ctx.swus; + else + link_dev = adev->pdev; + /* wait for asic to come out of reset, timeout = 10s */ + timeout = 10000; + do { + usleep_range(10000, 10500); + r = pci_read_config_word(link_dev, PCI_VENDOR_ID, &status); + timeout -= 10; + } while (timeout > 0 && (status != PCI_VENDOR_ID_ATI) && + (status != PCI_VENDOR_ID_AMD)); + if ((status != PCI_VENDOR_ID_ATI) && (status != PCI_VENDOR_ID_AMD)) { + r = -ETIME; + goto out; + } + + amdgpu_device_load_switch_state(adev); /* Restore PCI confspace */ amdgpu_device_load_pci_state(pdev); @@ -7161,6 +7182,58 @@ void amdgpu_pci_resume(struct pci_dev *pdev) } } +static void amdgpu_device_cache_switch_state(struct amdgpu_device *adev) +{ + struct pci_dev *parent = pci_upstream_bridge(adev->pdev); + int r; + + if (parent->vendor != PCI_VENDOR_ID_ATI) + return; + + /* If already saved, return */ + if (adev->pcie_reset_ctx.swus) + return; + /* Upstream bridge is ATI, assume it's SWUS/DS architecture */ + r = pci_save_state(parent); + if (r) + return; + adev->pcie_reset_ctx.swds_pcistate = pci_store_saved_state(parent); + + parent = pci_upstream_bridge(parent); + r = pci_save_state(parent); + if (r) + return; + adev->pcie_reset_ctx.swus_pcistate = pci_store_saved_state(parent); + + adev->pcie_reset_ctx.swus = parent; +} + +static void amdgpu_device_load_switch_state(struct amdgpu_device *adev) +{ + struct pci_dev *pdev; + int r; + + if (!adev->pcie_reset_ctx.swds_pcistate || + !adev->pcie_reset_ctx.swus_pcistate) + return; + + pdev = adev->pcie_reset_ctx.swus; + r = pci_load_saved_state(pdev, adev->pcie_reset_ctx.swus_pcistate); + if (!r) { + pci_restore_state(pdev); + } else { + dev_warn(adev->dev, "Failed to load SWUS state, err:%d\n", r); + return; + } + + pdev = pci_upstream_bridge(adev->pdev); + r = pci_load_saved_state(pdev, adev->pcie_reset_ctx.swds_pcistate); + if (!r) + pci_restore_state(pdev); + else + dev_warn(adev->dev, "Failed to load SWDS state, err:%d\n", r); +} + bool amdgpu_device_cache_pci_state(struct pci_dev *pdev) { struct drm_device *dev = pci_get_drvdata(pdev); @@ -7185,6 +7258,8 @@ bool amdgpu_device_cache_pci_state(struct pci_dev *pdev) return false; } + amdgpu_device_cache_switch_state(adev); + return true; } @@ -7620,4 +7695,4 @@ u64 amdgpu_device_get_uid(struct amdgpu_uid *uid_info, } return uid_info->uid[type][inst]; -} \ No newline at end of file +} From 8b3252d898f78c7a9db14959ce7367b694e025e6 Mon Sep 17 00:00:00 2001 From: Vitaly Prosyak Date: Thu, 7 Aug 2025 16:37:25 -0400 Subject: [PATCH 1689/2653] drm/amdgpu: add to custom amdgpu_drm_release drm_dev_enter/exit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit User queues are disabled before GEM objects are released (protecting against user app crashes). No races with PCI hot-unplug (because drm_dev_enter prevents cleanup if iewdevice is being removed). Cc: Christian König Cc: Alex Deucher Reviewed-by: Christian König Signed-off-by: Vitaly Prosyak --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 19036ea36fe8c..9b3c75446a68d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3004,11 +3004,14 @@ static int amdgpu_drm_release(struct inode *inode, struct file *filp) { struct drm_file *file_priv = filp->private_data; struct amdgpu_fpriv *fpriv = file_priv->driver_priv; + struct drm_device *dev = file_priv->minor->dev; + int idx; - if (fpriv) { + if (fpriv && drm_dev_enter(dev, &idx)) { fpriv->evf_mgr.fd_closing = true; amdgpu_eviction_fence_destroy(&fpriv->evf_mgr); amdgpu_userq_mgr_fini(&fpriv->userq_mgr); + drm_dev_exit(idx); } return drm_release(inode, filp); From b6c4ba58a45d7f1859a3da084c1e4a8b4e9867e7 Mon Sep 17 00:00:00 2001 From: TungYu Lu Date: Tue, 15 Jul 2025 16:56:59 +0800 Subject: [PATCH 1690/2653] drm/amd/display: Wait until OTG enable state is cleared [Why] Customer reported an issue that OS starts and stops device multiple times during driver installation. Frequently disabling and enabling OTG may prevent OTG from being safely disabled and cause incorrect configuration upon the next enablement. [How] Add a wait until OTG_CURRENT_MASTER_EN_STATE is cleared as a short term solution. Reviewed-by: Dillon Varone Signed-off-by: TungYu Lu Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c index ff79c38287df1..5af13706e6014 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c @@ -226,6 +226,11 @@ bool optc401_disable_crtc(struct timing_generator *optc) REG_UPDATE(CONTROL, VTG0_ENABLE, 0); + // wait until CRTC_CURRENT_MASTER_EN_STATE == 0 + REG_WAIT(OTG_CONTROL, + OTG_CURRENT_MASTER_EN_STATE, + 0, 10, 15000); + /* CRTC disabled, so disable clock. */ REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, From 31ddbbc539da88ed2dc2d50ba21d82a8ac5ed6f3 Mon Sep 17 00:00:00 2001 From: Danny Wang Date: Thu, 24 Jul 2025 13:58:21 +0800 Subject: [PATCH 1691/2653] drm/amd/display: Reset apply_eamless_boot_optimization when dpms_off MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [WHY&HOW] The user closed the lid while the system was powering on and opened it again before the “apply_seamless_boot_optimization” was set to false, resulting in the eDP remaining blank. Reset the “apply_seamless_boot_optimization” to false when dpms off. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Danny Wang Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index afafcdc9e53d9..59e18acbac8a2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3392,7 +3392,7 @@ static void update_seamless_boot_flags(struct dc *dc, int surface_count, struct dc_stream_state *stream) { - if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) { + if (get_seamless_boot_stream_count(context) > 0 && (surface_count > 0 || stream->dpms_off)) { /* Optimize seamless boot flag keeps clocks and watermarks high until * first flip. After first flip, optimization is required to lower * bandwidth. Important to note that it is expected UEFI will From e02881d135fea78f7db38b51fed5096f681e2034 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Sun, 3 Aug 2025 16:12:50 -0400 Subject: [PATCH 1692/2653] drm/amd/display: [FW Promotion] Release 0.1.22.0 Add a new command for Panel Replay. Acked-by: Wayne Lin Signed-off-by: Taimur Hassan Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 79b5b1bb9b93c..52295efdba636 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -4019,6 +4019,10 @@ enum dmub_cmd_replay_type { * Set adaptive sync sdp enabled */ DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, + /** + * Set version + */ + DMUB_CMD__REPLAY_SET_VERSION = 9, /** * Set Replay General command. */ @@ -4143,6 +4147,63 @@ struct dmub_cmd_replay_copy_settings_data { uint8_t pad[2]; }; + +/** + * Replay versions. + */ +enum replay_version { + /** + * FreeSync Replay + */ + REPLAY_VERSION_FREESYNC_REPLAY = 0, + /** + * Panel Replay + */ + REPLAY_VERSION_PANEL_REPLAY = 1, + /** + * Replay not supported. + */ + REPLAY_VERSION_UNSUPPORTED = 0xFF, +}; + +/** + * Data passed from driver to FW in a DMUB_CMD___SET_REPLAY_VERSION command. + */ +struct dmub_cmd_replay_set_version_data { + /** + * PSR version that FW should implement. + */ + enum replay_version version; + /** + * PSR control version. + */ + uint8_t cmd_version; + /** + * Panel Instance. + * Panel instance to identify which psr_state to use + * Currently the support is only for 0 or 1 + */ + uint8_t panel_inst; + /** + * Explicit padding to 4 byte boundary. + */ + uint8_t pad[2]; +}; + +/** + * Definition of a DMUB_CMD__REPLAY_SET_VERSION command. + */ +struct dmub_rb_cmd_replay_set_version { + /** + * Command header. + */ + struct dmub_cmd_header header; + /** + * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_VERSION command. + */ + struct dmub_cmd_replay_set_version_data replay_set_version_data; +}; + /** * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. */ @@ -4506,6 +4567,10 @@ union dmub_replay_cmd_set { * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. */ struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; + /** + * Definition of DMUB_CMD__REPLAY_SET_VERSION command data. + */ + struct dmub_cmd_replay_set_version_data version_data; /** * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. */ @@ -6265,6 +6330,10 @@ union dmub_rb_cmd { * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. */ struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; + /** + * Definition of a DMUB_CMD__REPLAY_SET_VERSION command. + */ + struct dmub_rb_cmd_replay_set_version replay_set_version; /* * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. */ From ec425111424486c34bf69fa9fd025ba75528b1ef Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Sun, 3 Aug 2025 18:38:31 -0500 Subject: [PATCH 1693/2653] drm/amd/display: Promote DC to 3.2.345 This version brings along following update: -Fix close and open lid may cause eDP remaining blank -Fix frequently disabling/enabling OTG may cause incorrect configuration of OTG Acked-by: Wayne Lin Signed-off-by: Taimur Hassan Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f4b5c1ff47671..dc017411c07e3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.344" +#define DC_VER "3.2.345" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From f38786f7339c55667132c26a37ab0e10d969d328 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 7 Aug 2025 11:33:57 -0500 Subject: [PATCH 1694/2653] PM: hibernate: add new api pm_hibernate_is_recovering() dev_pm_ops.thaw() is called in following cases: * normal case: after hibernation image has been created. * error case 1: creation of a hibernation image has failed. * error case 2: restoration from a hibernation image has failed. For normal case, it is called mainly for resume storage devices for saving the hibernation image. Other devices that are not involved in the image saving do not need to resume the device. But since there's no api to know which case thaw() is called, device drivers can't conditionally resume device in thaw(). The new pm_hibernate_is_recovering() is such a api to query if thaw() is called in normal case. Signed-off-by: Samuel Zhang Acked-by: Rafael J. Wysocki Link: https://lore.kernel.org/r/20250710062313.3226149-5-guoqing.zhang@amd.com Signed-off-by: Mario Limonciello (cherry picked from commit c2aaddbd2deded9d3301f1bafed242a0f71baba8) --- include/linux/suspend.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/suspend.h b/include/linux/suspend.h index 317ae31e89b37..a2af3bbe49337 100644 --- a/include/linux/suspend.h +++ b/include/linux/suspend.h @@ -426,6 +426,8 @@ int is_hibernate_resume_dev(dev_t dev); static inline int is_hibernate_resume_dev(dev_t dev) { return 0; } #endif +bool pm_hibernate_is_recovering(void); + /* Hibernation and suspend events */ #define PM_HIBERNATION_PREPARE 0x0001 /* Going to hibernate */ #define PM_POST_HIBERNATION 0x0002 /* Hibernation finished */ From a15aed64cc48561eccafc118c0e6aa62107fa69d Mon Sep 17 00:00:00 2001 From: Yang Su Date: Mon, 11 Aug 2025 12:05:05 +0800 Subject: [PATCH 1695/2653] drm/amdkcl: test whether pm_hibernate_is_recovering() exist It's caused by 23994a6f084303b "PM: hibernate: add new api pm_hibernate_is_recovering()" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_suspend.c | 19 +++++++++++++++++++ include/kcl/kcl_suspend.h | 5 +++++ 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c b/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c index c7f1086ebabd3..c0f5232d77a17 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c @@ -8,6 +8,10 @@ #include #include +#ifndef HAVE_PM_HIBERNATE_IS_RECOVERING +static pm_message_t pm_transition; +#endif + #ifndef HAVE_KSYS_SYNC_HELPER /* Copied from kernel/power/main.c */ #ifdef CONFIG_PM_SLEEP @@ -49,3 +53,18 @@ void amdkcl_suspend_init(void) #endif /* HAVE_KSYS_SYNC_HELPER */ } +#ifndef HAVE_PM_HIBERNATE_IS_RECOVERING +/** + * pm_hibernate_is_recovering - if recovering from hibernate due to error. + * + * Used to query if dev_pm_ops.thaw() is called for normal hibernation case or + * recovering from some error. + * + * Return: true for error case, false for normal case. + */ +bool kcl_pm_hibernate_is_recovering(void) +{ + return pm_transition.event == PM_EVENT_RECOVER; +} +EXPORT_SYMBOL_GPL(kcl_pm_hibernate_is_recovering); +#endif diff --git a/include/kcl/kcl_suspend.h b/include/kcl/kcl_suspend.h index ca37c821757b4..1a8f021650b54 100644 --- a/include/kcl/kcl_suspend.h +++ b/include/kcl/kcl_suspend.h @@ -29,4 +29,9 @@ static inline bool pm_suspend_via_firmware(void) { return false; } static inline bool pm_resume_via_firmware(void) { return false; } #endif /* HAVE_PM_SUSPEND_VIA_FIRMWARE */ +#ifndef HAVE_PM_HIBERNATE_IS_RECOVERING +bool kcl_pm_hibernate_is_recovering(void); + +#define pm_hibernate_is_recovering kcl_pm_hibernate_is_recovering +#endif #endif /* AMDKCL_SUSPEND_H */ From 3f2020a51ce8da605f222cb9e0d958406c7d6a20 Mon Sep 17 00:00:00 2001 From: Cryolitia PukNgae Date: Wed, 6 Aug 2025 11:34:18 +0800 Subject: [PATCH 1696/2653] drm/amdgpu: fix incorrect comment format MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Comments should not have a leading plus sign. Acked-by: Christian König Signed-off-by: Cryolitia PukNgae Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c index dceacf3f0d512..5504beb0c429a 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c @@ -151,9 +151,9 @@ static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instan * BIF_SDMA0_DOORBELL_RANGE: 0x3bc0 * BIF_SDMA1_DOORBELL_RANGE: 0x3bc4 * BIF_SDMA2_DOORBELL_RANGE: 0x3bd8 -+ * BIF_SDMA4_DOORBELL_RANGE: -+ * ARCTURUS: 0x3be0 -+ * ALDEBARAN: 0x3be4 + * BIF_SDMA4_DOORBELL_RANGE: + * ARCTURUS: 0x3be0 + * ALDEBARAN: 0x3be4 */ if (adev->asic_type == CHIP_ALDEBARAN && instance == 4) reg = instance + 0x4 + 0x1 + From 0376eab83e02af724bfcd35cc6ea354a138e96d3 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 17 Jul 2025 16:35:29 +0530 Subject: [PATCH 1697/2653] drm/amdgpu: Add description for partition commands Add string description for partition commands. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index c8e8bf192b014..1938b08f15b3e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -666,6 +666,10 @@ static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) return "FB_FW_RESERV_ADDR"; case GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR: return "FB_FW_RESERV_EXT_ADDR"; + case GFX_CMD_ID_SRIOV_SPATIAL_PART: + return "SPATIAL_PARTITION"; + case GFX_CMD_ID_FB_NPS_MODE: + return "NPS_MODE_CHANGE"; default: return "UNKNOWN CMD"; } From cf093d726c500dc28e3b651464ad5c8c00fc900d Mon Sep 17 00:00:00 2001 From: Matt Ezell Date: Thu, 31 Jul 2025 17:44:39 -0400 Subject: [PATCH 1698/2653] drm/amdgpu: Propagate amd_acquire errors in rdma_get_pages amd_acquire returns 1 on success and 0 on failure. rdma_get_pages needs to return non-zero if amd_acquire fails. Originally found by Chuck Fossen from HPE Signed-off-by: Matt Ezell Signed-off-by: Kent Russell Reviewed-by: Amber Lin --- drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index ed93247d83caa..09461f004377e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -557,6 +557,7 @@ static int rdma_get_pages(uint64_t address, uint64_t length, struct pid *pid, kfd_unref_process(p); if (r == 0) { pr_debug("acquire failed: %d\n", r); + r = -EINVAL; goto err_acquire; } From 22613639335f029a61e45e09b93269496c02ac45 Mon Sep 17 00:00:00 2001 From: Frank Min Date: Tue, 5 Aug 2025 22:30:54 +0800 Subject: [PATCH 1699/2653] drm/amdgpu: Add PSP fw version check for fw reserve GFX command The fw reserved GFX command is only supported starting from PSP fw version 0x3a0e14 and 0x3b0e0d. Older versions do not support this command. Add a version guard to ensure the command is only used when the running PSP fw meets the minimum version requirement. This ensures backward compatibility and safe operation across fw revisions. Signed-off-by: Frank Min Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 1938b08f15b3e..df4458f6f0061 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1043,15 +1043,28 @@ int psp_update_fw_reservation(struct psp_context *psp) { int ret; uint64_t reserv_addr, reserv_addr_ext; - uint32_t reserv_size, reserv_size_ext; + uint32_t reserv_size, reserv_size_ext, mp0_ip_ver; struct amdgpu_device *adev = psp->adev; + mp0_ip_ver = amdgpu_ip_version(adev, MP0_HWIP, 0); + if (amdgpu_sriov_vf(psp->adev)) return 0; - if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(14, 0, 2)) && - (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(14, 0, 3))) + switch (mp0_ip_ver) { + case IP_VERSION(14, 0, 2): + if (adev->psp.sos.fw_version < 0x3b0e0d) + return 0; + break; + + case IP_VERSION(14, 0, 3): + if (adev->psp.sos.fw_version < 0x3a0e14) + return 0; + break; + + default: return 0; + } ret = psp_get_fw_reservation_info(psp, GFX_CMD_ID_FB_FW_RESERV_ADDR, &reserv_addr, &reserv_size); if (ret) From 39bba204b12ba1ee42e7c902189164656a399aa3 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Tue, 12 Aug 2025 09:17:58 +0800 Subject: [PATCH 1700/2653] drm/amdgpu: fix vram reservation issue The vram block allocation flag must be cleared before making vram reservation, otherwise reserving addresses within the currently freed memory range will always fail. Signed-off-by: YiPeng Chai Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 16aef2da3b4df..96ef7f1edb03f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -691,9 +691,8 @@ static void amdgpu_vram_mgr_del(struct ttm_resource_manager *man, list_for_each_entry(block, &vres->blocks, link) vis_usage += amdgpu_vram_mgr_vis_size(adev, block); - amdgpu_vram_mgr_do_reserve(man); - drm_buddy_free_list(mm, &vres->blocks, vres->flags); + amdgpu_vram_mgr_do_reserve(man); mutex_unlock(&mgr->lock); atomic64_sub(vis_usage, &mgr->vis_usage); From 36c0a84333faadc449da408f8842752cff244175 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Mon, 11 Aug 2025 15:20:55 +0800 Subject: [PATCH 1701/2653] drm/amdgpu: fix incorrect vm flags to map bo It should use vm flags instead of pte flags to specify bo vm attributes. Signed-off-by: Jack Xiao Reviewed-by: Likun Gao --- drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c index a096fe34a8a16..aa580f7677126 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c @@ -92,8 +92,8 @@ int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm, } r = amdgpu_vm_bo_map(adev, *bo_va, csa_addr, 0, size, - AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | - AMDGPU_PTE_EXECUTABLE); + AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | + AMDGPU_VM_PAGE_EXECUTABLE); if (r) { DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r); From e59ce4cf3f9f61024dddfb0eb1f210458e8cd155 Mon Sep 17 00:00:00 2001 From: Liu01 Tong Date: Mon, 11 Aug 2025 14:52:37 +0800 Subject: [PATCH 1702/2653] drm/amdgpu: fix task hang from failed job submission during process kill MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit During process kill, drm_sched_entity_flush() will kill the vm entities. The following job submissions of this process will fail, and the resources of these jobs have not been released, nor have the fences been signalled, causing tasks to hang and timeout. Fix by check entity status in amdgpu_vm_ready() and avoid submit jobs to stopped entity. v2: add amdgpu_vm_ready() check before amdgpu_vm_clear_freed() in function amdgpu_cs_vm_handling(). Signed-off-by: Liu01 Tong Signed-off-by: Lin.Cao Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 15 +++++++++++---- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index e6488927909c5..cbafb27aed285 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1266,6 +1266,9 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p) } } + if (!amdgpu_vm_ready(vm)) + return -EINVAL; + r = amdgpu_vm_clear_freed(adev, vm, NULL); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 2cddd37f45a12..5c4ccf64c131c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -669,11 +669,10 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, * Check if all VM PDs/PTs are ready for updates * * Returns: - * True if VM is not evicting. + * True if VM is not evicting and all VM entities are not stopped */ bool amdgpu_vm_ready(struct amdgpu_vm *vm) { - bool empty; bool ret; amdgpu_vm_eviction_lock(vm); @@ -681,10 +680,18 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm) amdgpu_vm_eviction_unlock(vm); spin_lock(&vm->status_lock); - empty = list_empty(&vm->evicted); + ret &= list_empty(&vm->evicted); spin_unlock(&vm->status_lock); - return ret && empty; + spin_lock(&vm->immediate.lock); + ret &= !vm->immediate.stopped; + spin_unlock(&vm->immediate.lock); + + spin_lock(&vm->delayed.lock); + ret &= !vm->delayed.stopped; + spin_unlock(&vm->delayed.lock); + + return ret; } /** From 88e896c5bebf4febcaeeb1041f53ef71a477c55b Mon Sep 17 00:00:00 2001 From: Xichao Zhao Date: Tue, 12 Aug 2025 11:16:03 +0800 Subject: [PATCH 1703/2653] drm/radeon: replace min/max nesting with clamp() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The clamp() macro explicitly expresses the intent of constraining a value within bounds.Therefore, replacing min(max(a, b), c) and max(min(a,b),c) with clamp(val, lo, hi) can improve code readability. Reviewed-by: Christian König Signed-off-by: Xichao Zhao Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 8f5f8abcb1b47..79cbd0c71d5d4 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -926,10 +926,10 @@ static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, unsigned *fb_div, unsigned *ref_div) { /* limit reference * post divider to a maximum */ - ref_div_max = max(min(100 / post_div, ref_div_max), 1u); + ref_div_max = clamp(100 / post_div, 1u, ref_div_max); /* get matching reference and feedback divider */ - *ref_div = min(max(den/post_div, 1u), ref_div_max); + *ref_div = clamp(den / post_div, 1u, ref_div_max); *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); /* limit fb divider to its maximum */ From 1f42601a1f50f83865d9f7d4b87fb2266da06707 Mon Sep 17 00:00:00 2001 From: Liao Yuanhong Date: Tue, 12 Aug 2025 15:50:14 +0800 Subject: [PATCH 1704/2653] drm/amd/display: Remove redundant semicolons Remove unnecessary semicolons. Fixes: dda4fb85e433 ("drm/amd/display: DML changes for DCN32/321") Signed-off-by: Liao Yuanhong Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c index 9ba6cb67655f4..6c75aa82327ac 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c @@ -139,7 +139,6 @@ void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs, if (dual_plane) { unsigned int p1_pte_row_height_linear = get_dpte_row_height_linear_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); - ; if (src->sw_mode == dm_sw_linear) ASSERT(p1_pte_row_height_linear >= 8); From 90c2609ad5f848212406372c3a323ef29aea2288 Mon Sep 17 00:00:00 2001 From: Qianfeng Rong Date: Tue, 12 Aug 2025 16:31:49 +0800 Subject: [PATCH 1705/2653] drm/amd/display: Use boolean context for pointer null checks Replace "out == 0" with "!out" for pointer comparison to improve code readability and conform to coding style. Signed-off-by: Qianfeng Rong Signed-off-by: Alex Deucher --- .../amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c | 2 +- .../amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c | 2 +- .../amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c | 2 +- .../amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c index 28394de028855..640087e862f84 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c @@ -10,7 +10,7 @@ bool dml2_core_create(enum dml2_project_id project_id, struct dml2_core_instance { bool result = false; - if (out == 0) + if (!out) return false; memset(out, 0, sizeof(struct dml2_core_instance)); diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c index 3861bc6c96219..dfd01440737df 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c @@ -20,7 +20,7 @@ bool dml2_dpmm_create(enum dml2_project_id project_id, struct dml2_dpmm_instance { bool result = false; - if (out == 0) + if (!out) return false; memset(out, 0, sizeof(struct dml2_dpmm_instance)); diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c index cd3fbc0591d82..c60b8fe90819d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c @@ -15,7 +15,7 @@ bool dml2_mcg_create(enum dml2_project_id project_id, struct dml2_mcg_instance * { bool result = false; - if (out == 0) + if (!out) return false; memset(out, 0, sizeof(struct dml2_mcg_instance)); diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c index 7ed0242a4b331..55d2464365d04 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c @@ -26,7 +26,7 @@ bool dml2_pmo_create(enum dml2_project_id project_id, struct dml2_pmo_instance * { bool result = false; - if (out == 0) + if (!out) return false; memset(out, 0, sizeof(struct dml2_pmo_instance)); From 6c146de620786a32aeaa8d50b30b3c8c74bd73ee Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Thu, 7 Aug 2025 14:23:11 -0400 Subject: [PATCH 1706/2653] drm/amdkfd: set uuid for each partition in topology Currently each kfd compute partition/node is sharing the same uuid of AID, which doen't meet the CUDA spec for visible device, so corresponding XCD id for each partition in smu has been assigned to xcp, and exposed to kfd topology. v2: add NULL check (Lijo) Signed-off-by: Eric Huang Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index df47004cb69ba..ac688f1aa5009 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -546,6 +546,8 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr, sysfs_show_32bit_prop(buffer, offs, "sdma_fw_version", dev->gpu->kfd->sdma_fw_version); sysfs_show_64bit_prop(buffer, offs, "unique_id", + dev->gpu->xcp ? + dev->gpu->xcp->unique_id : dev->gpu->adev->unique_id); sysfs_show_32bit_prop(buffer, offs, "num_xcc", NUM_XCC(dev->gpu->xcc_mask)); From 21d4bc8f6a310af38e362417fba79f86957e8367 Mon Sep 17 00:00:00 2001 From: Geoffrey McRae Date: Tue, 8 Jul 2025 13:53:40 +1000 Subject: [PATCH 1707/2653] drm/amdkfd: return -ENOTTY for unsupported IOCTLs Some kfd ioctls may not be available depending on the kernel version the user is running, as such we need to report -ENOTTY so userland can determine the cause of the ioctl failure. Signed-off-by: Geoffrey McRae Acked-by: Alex Deucher Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 726869061292e..a0a846ff8ce43 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -3615,8 +3615,10 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) asize = amdkfd_size; cmd = ioctl->cmd; - } else + } else { + retcode = -ENOTTY; goto err_i1; + } dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg); From bd76e41686b8aada56288e45d1473c22f3ab2662 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 13 Aug 2025 18:25:30 +0800 Subject: [PATCH 1708/2653] Revert "drm/amdkfd: return migration pages from copy function" This reverts commit 44fa38dfa20d9966beeb6c61fd8639756e7ca5f3. It cause the Jira ticket: SWDEV-548954, temporarily revert it. Signed-off-by: Chengjun Yao --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 72 ++++++++++++------------ 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 690905d7551da..b6f61d133ed7d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -269,7 +269,20 @@ static void svm_migrate_put_sys_page(unsigned long addr) put_page(page); } -static long +static unsigned long svm_migrate_unsuccessful_pages(struct migrate_vma *migrate) +{ + unsigned long upages = 0; + unsigned long i; + + for (i = 0; i < migrate->npages; i++) { + if (migrate->src[i] & MIGRATE_PFN_VALID && + !(migrate->src[i] & MIGRATE_PFN_MIGRATE)) + upages++; + } + return upages; +} + +static int svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, struct migrate_vma *migrate, struct dma_fence **mfence, dma_addr_t *scratch, uint64_t ttm_res_offset) @@ -278,7 +291,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, struct amdgpu_device *adev = node->adev; struct device *dev = adev->dev; struct amdgpu_res_cursor cursor; - long mpages; + uint64_t mpages = 0; dma_addr_t *src; uint64_t *dst; uint64_t i, j; @@ -292,7 +305,6 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, amdgpu_res_first(prange->ttm_res, ttm_res_offset, npages << PAGE_SHIFT, &cursor); - mpages = 0; for (i = j = 0; (i < npages) && (mpages < migrate->cpages); i++) { struct page *spage; @@ -354,14 +366,13 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, out_free_vram_pages: if (r) { pr_debug("failed %d to copy memory to vram\n", r); - while (i-- && mpages) { + for (i = 0; i < npages && mpages; i++) { if (!dst[i]) continue; svm_migrate_put_vram_page(adev, dst[i]); migrate->dst[i] = 0; mpages--; } - mpages = r; } #ifdef DEBUG_FORCE_MIXED_DOMAINS @@ -379,7 +390,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, } #endif - return mpages; + return r; } static long @@ -394,7 +405,7 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange, struct dma_fence *mfence = NULL; struct migrate_vma migrate = { 0 }; unsigned long cpages = 0; - long mpages = 0; + unsigned long mpages = 0; dma_addr_t *scratch; void *buf; int r = -ENOMEM; @@ -444,17 +455,15 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange, else pr_debug("0x%lx pages collected\n", cpages); - mpages = svm_migrate_copy_to_vram(node, prange, &migrate, &mfence, scratch, ttm_res_offset); + r = svm_migrate_copy_to_vram(node, prange, &migrate, &mfence, scratch, ttm_res_offset); migrate_vma_pages(&migrate); svm_migrate_copy_done(adev, mfence); migrate_vma_finalize(&migrate); - if (mpages >= 0) - pr_debug("migrated/collected/requested 0x%lx/0x%lx/0x%lx\n", + mpages = cpages - svm_migrate_unsuccessful_pages(&migrate); + pr_debug("successful/cpages/npages 0x%lx/0x%lx/0x%lx\n", mpages, cpages, migrate.npages); - else - r = mpages; svm_range_dma_unmap_dev(adev->dev, scratch, 0, npages); @@ -464,13 +473,14 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange, start >> PAGE_SHIFT, end >> PAGE_SHIFT, 0, node->id, trigger, r); out: - if (!r && mpages > 0) { + if (!r && mpages) { pdd = svm_range_get_pdd_by_node(prange, node); if (pdd) WRITE_ONCE(pdd->page_in, pdd->page_in + mpages); - } - return r ? r : mpages; + return mpages; + } + return r; } /** @@ -581,7 +591,7 @@ static void svm_migrate_page_free(struct page *page) } } -static long +static int svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, struct migrate_vma *migrate, struct dma_fence **mfence, dma_addr_t *scratch, uint64_t npages) @@ -590,7 +600,6 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, uint64_t *src; dma_addr_t *dst; struct page *dpage; - long mpages; uint64_t i = 0, j; uint64_t addr; int r = 0; @@ -603,7 +612,6 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, src = (uint64_t *)(scratch + npages); dst = scratch; - mpages = 0; for (i = 0, j = 0; i < npages; i++, addr += PAGE_SIZE) { struct page *spage; @@ -653,7 +661,6 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, migrate->dst[i] = migrate_pfn(page_to_pfn(dpage)); migrate->dst[i] |= MIGRATE_PFN_LOCKED; - mpages++; j++; } @@ -663,17 +670,13 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, out_oom: if (r) { pr_debug("failed %d copy to ram\n", r); - while (i-- && mpages) { - if (!migrate->dst[i]) - continue; + while (i--) { svm_migrate_put_sys_page(dst[i]); migrate->dst[i] = 0; - mpages--; } - mpages = r; } - return mpages; + return r; } /** @@ -700,8 +703,9 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, { struct kfd_process *p = container_of(prange->svms, struct kfd_process, svms); uint64_t npages = (end - start) >> PAGE_SHIFT; + unsigned long upages = npages; unsigned long cpages = 0; - long mpages = 0; + unsigned long mpages = 0; struct amdgpu_device *adev = node->adev; struct kfd_process_device *pdd; struct dma_fence *mfence = NULL; @@ -763,15 +767,13 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, else pr_debug("0x%lx pages collected\n", cpages); - mpages = svm_migrate_copy_to_ram(adev, prange, &migrate, &mfence, + r = svm_migrate_copy_to_ram(adev, prange, &migrate, &mfence, scratch, npages); migrate_vma_pages(&migrate); - if (mpages >= 0) - pr_debug("migrated/collected/requested 0x%lx/0x%lx/0x%lx\n", - mpages, cpages, migrate.npages); - else - r = mpages; + upages = svm_migrate_unsuccessful_pages(&migrate); + pr_debug("unsuccessful/cpages/npages 0x%lx/0x%lx/0x%lx\n", + upages, cpages, migrate.npages); svm_migrate_copy_done(adev, mfence); migrate_vma_finalize(&migrate); @@ -784,7 +786,8 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, start >> PAGE_SHIFT, end >> PAGE_SHIFT, node->id, 0, trigger, r); out: - if (!r && mpages > 0) { + if (!r && cpages) { + mpages = cpages - upages; pdd = svm_range_get_pdd_by_node(prange, node); if (pdd) WRITE_ONCE(pdd->page_out, pdd->page_out + mpages); @@ -867,9 +870,6 @@ int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm, } if (r >= 0) { - WARN_ONCE(prange->vram_pages < mpages, - "Recorded vram pages(0x%llx) should not be less than migration pages(0x%lx).", - prange->vram_pages, mpages); prange->vram_pages -= mpages; /* prange does not have vram page set its actual_loc to system From f6696da0b661d25040a5d7da090e692a0f1ef1c6 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Mon, 28 Jul 2025 19:49:24 +0800 Subject: [PATCH 1709/2653] drm/amdgpu: Add new error code for VCN/JPEG new chain Add VIDS and JPEG8/9 S|D chain error code for VCN/JPEG v5.0.1. Change-Id: Ib0131561875202d1ec63c95fd9c53daa3651795b Signed-off-by: Stanley.Yang Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c index 8d74455dab1e2..a2d781898767e 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c @@ -1024,8 +1024,9 @@ static int jpeg_v5_0_1_aca_bank_parser(struct aca_handle *handle, struct aca_ban /* reference to smu driver if header file */ static int jpeg_v5_0_1_err_codes[] = { - 16, 17, 18, 19, 20, 21, 22, 23, /* JPEG[0-7][S|D] */ - 24, 25, 26, 27, 28, 29, 30, 31 + 16, 17, 18, 19, 20, 21, 22, 23, /* JPEG[0-9][S|D] */ + 24, 25, 26, 27, 28, 29, 30, 31, + 48, 49, 50, 51, }; static bool jpeg_v5_0_1_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c index 60739be6db27f..7cb21e2b4eb0e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c @@ -1604,7 +1604,7 @@ static int vcn_v5_0_1_aca_bank_parser(struct aca_handle *handle, struct aca_bank /* reference to smu driver if header file */ static int vcn_v5_0_1_err_codes[] = { - 14, 15, /* VCN */ + 14, 15, 47, /* VCN [D|V|S] */ }; static bool vcn_v5_0_1_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, From 1ed4f66afdc61455618b18bdf48ad8527fe2ebef Mon Sep 17 00:00:00 2001 From: Heng Zhou Date: Wed, 13 Aug 2025 11:18:04 +0800 Subject: [PATCH 1710/2653] drm/amdgpu: fix nullptr err of vm_handle_moved If a amdgpu_bo_va is fpriv->prt_va, the bo of this one is always NULL. So, such kind of amdgpu_bo_va should be updated separately before amdgpu_vm_handle_moved. Signed-off-by: Heng Zhou Reviewed-by: Kasiviswanathan, Harish Change-Id: I6ec72826b657e7f89f7416ef52548113dba0ab85 --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index deb39e320b042..7231e57cd9984 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -3404,9 +3404,22 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu * struct amdgpu_device *adev = amdgpu_ttm_adev( peer_vm->root.bo->tbo.bdev); + struct amdgpu_fpriv *fpriv = + container_of(peer_vm, struct amdgpu_fpriv, vm); + + ret = amdgpu_vm_bo_update(adev, fpriv->prt_va, false); + if (ret) { + dev_dbg(adev->dev, + "Memory eviction: handle PRT moved failed, pid %8d. Try again.\n", + pid_nr(process_info->pid)); + goto validate_map_fail; + } + ret = amdgpu_vm_handle_moved(adev, peer_vm, &exec.ticket); if (ret) { - pr_debug("Memory eviction: handle moved failed. Try again\n"); + dev_dbg(adev->dev, + "Memory eviction: handle moved failed, pid %8d. Try again.\n", + pid_nr(process_info->pid)); goto validate_map_fail; } } From 56347991062014d2b3d23a2ed3beb48849f93853 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Wed, 13 Aug 2025 10:36:58 +0800 Subject: [PATCH 1711/2653] drm/amd/pm: Add VCN reset support check capability This change introduces infrastructure to check whether VCN reset is supported by the SMU firmware. Key changes include: 1. Added new functions to query VCN reset support: - amdgpu_dpm_reset_vcn_is_supported() - smu_reset_vcn_is_supported() - pptable_funcs.reset_vcn_is_supported callback 2. Implemented proper locking in the DPM layer with mutex protection 3. Maintained consistency with existing SDMA reset support checks The new capability allows callers to check for VCN reset support before attempting the operation, preventing unnecessary attempts on unsupported platforms. v2: clean up debug info(Alex) Suggested-by: Alex Deucher Signed-off-by: Ruili Ji Signed-off-by: Jesse Zhang Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 15 +++++++++++++++ drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 1 + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 9 +++++++++ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 5 +++++ 4 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index 26449930216f8..f3a5777c67c3c 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -820,6 +820,21 @@ int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask) return ret; } +bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev) +{ + struct smu_context *smu = adev->powerplay.pp_handle; + bool ret; + + if (!is_support_sw_smu(adev)) + return false; + + mutex_lock(&adev->pm.mutex); + ret = smu_reset_vcn_is_supported(smu); + mutex_unlock(&adev->pm.mutex); + + return ret; +} + int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t *min, diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h index 18c53e1fbeb39..31c0b6ea041af 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h @@ -616,6 +616,7 @@ int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask); bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev); void amdgpu_dpm_phase_det_debugfs_init(struct amdgpu_device *adev); int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask); +bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev); bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev, enum smu_temp_metric_type type); diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 813aa00bbe55a..4698f5a785920 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -4319,3 +4319,12 @@ void amdgpu_smu_phase_det_debugfs_init(struct amdgpu_device *adev) #endif } +bool smu_reset_vcn_is_supported(struct smu_context *smu) +{ + bool ret = false; + + if (smu->ppt_funcs && smu->ppt_funcs->reset_vcn_is_supported) + ret = smu->ppt_funcs->reset_vcn_is_supported(smu); + + return ret; +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index d36f803d83b49..8ae1a3b714c74 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -1466,6 +1466,10 @@ struct pptable_funcs { * @reset_vcn: message SMU to soft reset vcn instance. */ int (*dpm_reset_vcn)(struct smu_context *smu, uint32_t inst_mask); + /** + * @reset_vcn_is_supported: Check if support resets vcn. + */ + bool (*reset_vcn_is_supported)(struct smu_context *smu); /** * @get_ecc_table: message SMU to get ECC INFO table. @@ -1807,6 +1811,7 @@ int smu_send_rma_reason(struct smu_context *smu); int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask); bool smu_reset_sdma_is_supported(struct smu_context *smu); int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask); +bool smu_reset_vcn_is_supported(struct smu_context *smu); int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, int level); ssize_t smu_get_pm_policy_info(struct smu_context *smu, From d9dcd961a5aa6e64cc2c49cd7d0f622764c19c5d Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Wed, 13 Aug 2025 10:40:18 +0800 Subject: [PATCH 1712/2653] drm/amd/pm: Add VCN reset support for SMU v13.0.6 This commit implements VCN reset capability for SMU v13.0.6 with the following changes: 1. Added new PPSMC message ID (0x5B) for VCN reset in SMU firmware interface 2. Extended SMU capabilities to include VCN_RESET support 3. Implemented VCN reset support check: - Added smu_v13_0_6_reset_vcn_is_supported() function 4. Updated SMU v13.0.6 PPT functions to include VCN reset operations v2: clean up debug info (Alex) v3: remove unsupported message and split smu v13.0.6 changes to a separate patch (Lijo) v4: simply the function (smu_v13_0_6_reset_vcn_is_supported) (Lijo) Suggested-by: Alex Deucher Signed-off-by: Ruili Ji Signed-off-by: Jesse Zhang Reviewed-by: Lijo Lazar --- .../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 4 ++-- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 9 +++++++++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 1 + 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h index 373d994cad496..8a87ff43cbb2d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h @@ -101,9 +101,9 @@ #define PPSMC_MSG_SetPhsDetOnOff 0x4A #define PPSMC_MSG_GetPhsDetResidency 0x4B #define PPSMC_MSG_ResetSDMA 0x4D -#define PPSMC_MSG_ResetVCN 0x4E #define PPSMC_MSG_GetStaticMetricsTable 0x59 -#define PPSMC_Message_Count 0x5A +#define PPSMC_MSG_ResetVCN 0x5B +#define PPSMC_Message_Count 0x5C //PPSMC Reset Types for driver msg argument #define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET 0x1 diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index bc4900774a035..9bd6ea5ae711a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -444,6 +444,9 @@ static void smu_v13_0_6_init_caps(struct smu_context *smu) ((pgm == 0) && (fw_ver >= 0x00557900)) || ((pgm == 4) && (fw_ver >= 0x4557000))) smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET)); + + if ((pgm == 4) && (fw_ver >= 0x04557100)) + smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET)); } static void smu_v13_0_x_init_caps(struct smu_context *smu) @@ -3376,6 +3379,11 @@ static int smu_v13_0_6_post_init(struct smu_context *smu) return 0; } +static bool smu_v13_0_6_reset_vcn_is_supported(struct smu_context *smu) +{ + return smu_v13_0_6_cap_supported(smu, SMU_CAP(VCN_RESET)); +} + static int smu_v13_0_6_reset_vcn(struct smu_context *smu, uint32_t inst_mask) { int ret = 0; @@ -4064,6 +4072,7 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { .reset_sdma_is_supported = smu_v13_0_6_reset_sdma_is_supported, .post_init = smu_v13_0_6_post_init, .dpm_reset_vcn = smu_v13_0_6_reset_vcn, + .reset_vcn_is_supported = smu_v13_0_6_reset_vcn_is_supported, }; void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h index f39dbfdd7a2f2..bcb8246c08042 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h @@ -64,6 +64,7 @@ enum smu_v13_0_6_caps { SMU_CAP(RMA_MSG), SMU_CAP(ACA_SYND), SMU_CAP(SDMA_RESET), + SMU_CAP(VCN_RESET), SMU_CAP(STATIC_METRICS), SMU_CAP(HST_LIMIT_METRICS), SMU_CAP(BOARD_VOLTAGE), From 35d3aa5bc886f7e37ffd44c5251c6232b2b6b0d9 Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Mon, 21 Jul 2025 14:06:36 -0400 Subject: [PATCH 1713/2653] drm/amdkfd: Handle lack of READ permissions in SVM mapping HMM assumes that pages have READ permissions by default. Inside svm_range_validate_and_map, we add READ permissions then add WRITE permissions if the VMA isn't read-only. This will conflict with regions that only have PROT_WRITE or have PROT_NONE. When that happens, svm_range_restore_work will continue to retry, silently, giving the impression of a hang if pr_debug isn't enabled to show the retries.. If pages don't have READ permissions, simply unmap them and continue. If they weren't mapped in the first place, this would be a no-op. Since x86 doesn't support write-only, and PROT_NONE doesn't allow reads or writes anyways, this will allow the svm range validation to continue without getting stuck in a loop forever on mappings we can't use with HMM. Signed-off-by: Kent Russell Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 744e0b8df16b7..7b7dbab6f999d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1717,6 +1717,29 @@ static int svm_range_validate_and_map(struct mm_struct *mm, next = min(vma->vm_end, end); npages = (next - addr) >> PAGE_SHIFT; + /* HMM requires at least READ permissions. If provided with PROT_NONE, + * unmap the memory. If it's not already mapped, this is a no-op + * If PROT_WRITE is provided without READ, warn first then unmap + */ + if (!(vma->vm_flags & VM_READ)) { + unsigned long e, s; + + svm_range_lock(prange); + if (vma->vm_flags & VM_WRITE) + pr_debug("VM_WRITE without VM_READ is not supported"); + s = max(start, prange->start); + e = min(end, prange->last); + if (e >= s) + r = svm_range_unmap_from_gpus(prange, s, e, + KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU); + svm_range_unlock(prange); + /* If unmap returns non-zero, we'll bail on the next for loop + * iteration, so just leave r and continue + */ + addr = next; + continue; + } + WRITE_ONCE(p->svms.faulting_task, current); r = amdgpu_hmm_range_get_pages(&prange->notifier, addr, npages, readonly, owner, NULL, From 87131c884dbecb7d4ecf28dd077052903703d815 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Wed, 13 Aug 2025 10:55:44 +0800 Subject: [PATCH 1714/2653] drm/amd/vcn: Add late_init callback for VCN v4.0.3 reset handling This change reorganizes VCN reset capability detection by: 1. Moving reset mask configuration from sw_init to new late_init phase 2. Adding vcn_v4_0_3_late_init() to properly check for per-queue reset support 3. Only setting soft full reset mask as fallback when per-queue reset isn't supported 4. Removing TODO comment now that queue reset support is implemented V2: Removed unrelated changes. Keep amdgpu_get_soft_full_reset_mask in place and remove TODO comment. (Alex) v3: set the flags at one place (all in late_init) (Lijo) Suggested-by: Alex Deucher Signed-off-by: Ruili Ji Signed-off-by: Jesse Zhang Reviewed-by: Alex Deucher Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 019bd362edb22..a63a1e3435ab6 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -134,6 +134,19 @@ static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) return 0; } +static int vcn_v4_0_3_late_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + + adev->vcn.supported_reset = + amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); + + if (amdgpu_dpm_reset_vcn_is_supported(adev)) + adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; + + return 0; +} + static int vcn_v4_0_3_fw_shared_init(struct amdgpu_device *adev, int inst_idx) { struct amdgpu_vcn4_fw_shared *fw_shared; @@ -211,10 +224,6 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode; } - /* TODO: Add queue reset mask when FW fully supports it */ - adev->vcn.supported_reset = - amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); - if (amdgpu_sriov_vf(adev)) { r = amdgpu_virt_alloc_mm_table(adev); if (r) @@ -1871,6 +1880,7 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = { .name = "vcn_v4_0_3", .early_init = vcn_v4_0_3_early_init, + .late_init = vcn_v4_0_3_late_init, .sw_init = vcn_v4_0_3_sw_init, .sw_fini = vcn_v4_0_3_sw_fini, .hw_init = vcn_v4_0_3_hw_init, From 2916a8faaebee5b96d786fb08a960b369fa21ecc Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 12 Aug 2025 13:21:49 +0530 Subject: [PATCH 1715/2653] drm/amd/pm: Free SMUv13.0.6 resources on failure Free the resources allocated if smu_v13_0_12_tables_init fails. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang Fixes: 22ef8851997f ("drm/amd/pm: Add caching to SMUv13.0.12 temp metric") --- .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 4 +++- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 12 ++++++++++-- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index ea2682f9d579d..32fd0be05cffb 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -161,8 +161,10 @@ int smu_v13_0_12_tables_init(struct smu_context *smu) /* Initialize GPU board temperature metrics */ ret = smu_table_cache_init(smu, SMU_TABLE_GPUBOARD_TEMP_METRICS, sizeof(*gpuboard_temp_metrics), 50); - if (ret) + if (ret) { + smu_table_cache_fini(smu, SMU_TABLE_BASEBOARD_TEMP_METRICS); return ret; + } cache = &(tables[SMU_TABLE_GPUBOARD_TEMP_METRICS].cache); gpuboard_temp_metrics = (struct amdgpu_gpuboard_temp_metrics_v1_0 *)cache->buffer; smu_cmn_init_gpuboard_temp_metrics(gpuboard_temp_metrics, 1, 0); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 9bd6ea5ae711a..367ce834a7498 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -545,6 +545,7 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu) struct smu_table *tables = smu_table->tables; struct amdgpu_device *adev = smu->adev; int gpu_metrcs_size = METRICS_TABLE_SIZE; + int ret; if (!(adev->flags & AMD_IS_APU)) SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE, @@ -581,8 +582,15 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu) return -ENOMEM; } - if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) - return smu_v13_0_12_tables_init(smu); + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == + IP_VERSION(13, 0, 12)) { + ret = smu_v13_0_12_tables_init(smu); + if (ret) { + kfree(smu_table->metrics_table); + kfree(smu_table->gpu_metrics_table); + return ret; + } + } return 0; } From 0f937182feb2415a2fc1c8e5077c45e0c5fa8ed6 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 8 Aug 2025 13:12:07 -0400 Subject: [PATCH 1716/2653] drm/amdgpu/swm14: Update power limit logic Take into account the limits from the vbios. Ported from the SMU13 code. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4352 Reviewed-by: Jesse Zhang Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 30 +++++++++++++++---- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index 3aea32baea3da..f32474af90b34 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -1697,9 +1697,11 @@ static int smu_v14_0_2_get_power_limit(struct smu_context *smu, uint32_t *min_power_limit) { struct smu_table_context *table_context = &smu->smu_table; + struct smu_14_0_2_powerplay_table *powerplay_table = + table_context->power_play_table; PPTable_t *pptable = table_context->driver_pptable; CustomSkuTable_t *skutable = &pptable->CustomSkuTable; - uint32_t power_limit; + uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0; uint32_t msg_limit = pptable->SkuTable.MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC]; if (smu_v14_0_get_current_power_limit(smu, &power_limit)) @@ -1712,11 +1714,29 @@ static int smu_v14_0_2_get_power_limit(struct smu_context *smu, if (default_power_limit) *default_power_limit = power_limit; - if (max_power_limit) - *max_power_limit = msg_limit; + if (powerplay_table) { + if (smu->od_enabled && + smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) { + od_percent_upper = pptable->SkuTable.OverDriveLimitsBasicMax.Ppt; + od_percent_lower = pptable->SkuTable.OverDriveLimitsBasicMin.Ppt; + } else if (smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) { + od_percent_upper = 0; + od_percent_lower = pptable->SkuTable.OverDriveLimitsBasicMin.Ppt; + } + } + + dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n", + od_percent_upper, od_percent_lower, power_limit); + + if (max_power_limit) { + *max_power_limit = msg_limit * (100 + od_percent_upper); + *max_power_limit /= 100; + } - if (min_power_limit) - *min_power_limit = 0; + if (min_power_limit) { + *min_power_limit = power_limit * (100 + od_percent_lower); + *min_power_limit /= 100; + } return 0; } From 008bac226be47fe359dd162a088645b6e4dd3c49 Mon Sep 17 00:00:00 2001 From: Alexandre Demers Date: Tue, 12 Aug 2025 20:46:25 -0400 Subject: [PATCH 1717/2653] drm/radeon: fix typos Various small typos found around. Signed-off-by: Alexandre Demers Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_device.c | 4 ++-- drivers/gpu/drm/radeon/radeon_test.c | 4 ++-- drivers/gpu/drm/radeon/radeon_vce.c | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index 7a3e510327b79..9e35b14e2bf0e 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -554,7 +554,7 @@ int radeon_wb_init(struct radeon_device *rdev) * cover the whole aperture even if VRAM size is inferior to aperture size * Novell bug 204882 + along with lots of ubuntu ones * - * Note 3: when limiting vram it's safe to overwritte real_vram_size because + * Note 3: when limiting vram it's safe to overwrite real_vram_size because * we are not in case where real_vram_size is inferior to mc_vram_size (ie * not affected by bogus hw of Novell bug 204882 + along with lots of ubuntu * ones) @@ -562,7 +562,7 @@ int radeon_wb_init(struct radeon_device *rdev) * Note 4: IGP TOM addr should be the same as the aperture addr, we don't * explicitly check for that thought. * - * FIXME: when reducing VRAM size align new size on power of 2. + * FIXME: when reducing VRAM size, align new size on power of 2. */ void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) { diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c index c9fef9b61ced6..818554e605379 100644 --- a/drivers/gpu/drm/radeon/radeon_test.c +++ b/drivers/gpu/drm/radeon/radeon_test.c @@ -455,7 +455,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev, r = radeon_ring_lock(rdev, ringC, 64); if (r) { - DRM_ERROR("Failed to lock ring B %p\n", ringC); + DRM_ERROR("Failed to lock ring C %p\n", ringC); goto out_cleanup; } radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore); @@ -481,7 +481,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev, r = radeon_ring_lock(rdev, ringC, 64); if (r) { - DRM_ERROR("Failed to lock ring B %p\n", ringC); + DRM_ERROR("Failed to lock ring C %p\n", ringC); goto out_cleanup; } radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore); diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c index 2355a78e1b69d..bdbc1bbe8a9b5 100644 --- a/drivers/gpu/drm/radeon/radeon_vce.c +++ b/drivers/gpu/drm/radeon/radeon_vce.c @@ -86,7 +86,7 @@ int radeon_vce_init(struct radeon_device *rdev) r = request_firmware(&rdev->vce_fw, fw_name, rdev->dev); if (r) { - dev_err(rdev->dev, "radeon_vce: Can't load firmware \"%s\"\n", + dev_err(rdev->dev, "radeon_vce: can't load firmware \"%s\"\n", fw_name); return r; } @@ -126,7 +126,7 @@ int radeon_vce_init(struct radeon_device *rdev) rdev->vce.fw_version = (start << 24) | (mid << 16) | (end << 8); - /* we can only work with this fw version for now */ + /* we can only work with these fw versions for now */ if ((rdev->vce.fw_version != ((40 << 24) | (2 << 16) | (2 << 8))) && (rdev->vce.fw_version != ((50 << 24) | (0 << 16) | (1 << 8))) && (rdev->vce.fw_version != ((50 << 24) | (1 << 16) | (2 << 8)))) @@ -281,7 +281,7 @@ static void radeon_vce_idle_work_handler(struct work_struct *work) * * @rdev: radeon_device pointer * - * Make sure VCE is powerd up when we want to use it + * Make sure VCE is powered up when we want to use it */ void radeon_vce_note_usage(struct radeon_device *rdev) { From e70ceefeee7902e81f3ea3c972b955d92f7d78b3 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 13 Aug 2025 12:14:01 +0530 Subject: [PATCH 1718/2653] drm/amd/display: Add NULL pointer checks in dc_stream cursor attribute functions The function dc_stream_set_cursor_attributes() currently dereferences the `stream` pointer and nested members `stream->ctx->dc->current_state` without checking for NULL. All callers of these functions, such as in `dcn30_apply_idle_power_optimizations()` and `amdgpu_dm_plane_handle_cursor_update()`, already perform NULL checks before calling these functions. Fixes below: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:336 dc_stream_program_cursor_attributes() error: we previously assumed 'stream' could be null (see line 334) drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c 327 bool dc_stream_program_cursor_attributes( 328 struct dc_stream_state *stream, 329 const struct dc_cursor_attributes *attributes) 330 { 331 struct dc *dc; 332 bool reset_idle_optimizations = false; 333 334 dc = stream ? stream->ctx->dc : NULL; ^^^^^^ The old code assumed stream could be NULL. 335 --> 336 if (dc_stream_set_cursor_attributes(stream, attributes)) { ^^^^^^ The refactor added an unchecked dereference. drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c 313 bool dc_stream_set_cursor_attributes( 314 struct dc_stream_state *stream, 315 const struct dc_cursor_attributes *attributes) 316 { 317 bool result = false; 318 319 if (dc_stream_check_cursor_attributes(stream, stream->ctx->dc->current_state, attributes)) { ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Here. This function used to check for if stream as NULL and return false at the start. Probably we should add that back. 'Fixes: 4465dd0e41e8 ("drm/amd/display: Refactor SubVP cursor limiting logic")' Reported-by: Dan Carpenter Cc: Alex Hung Cc: Alvin Lee Cc: Ray Wu Cc: Dillon Varone Cc: Aurabindo Pillai Cc: Roman Li Cc: ChiaHsuan Chung Cc: Harry Wentland Cc: Daniel Wheeler Cc: Tom Chung Cc: Wenjing Liu Cc: Jun Lei Signed-off-by: Srinivasan Shanmugam Reviewed-by: Dillon Varone --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 4d6bc9fd4faa8..9ac2d41f8fcae 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -316,6 +316,9 @@ bool dc_stream_set_cursor_attributes( { bool result = false; + if (!stream) + return false; + if (dc_stream_check_cursor_attributes(stream, stream->ctx->dc->current_state, attributes)) { stream->cursor_attributes = *attributes; result = true; @@ -331,7 +334,10 @@ bool dc_stream_program_cursor_attributes( struct dc *dc; bool reset_idle_optimizations = false; - dc = stream ? stream->ctx->dc : NULL; + if (!stream) + return false; + + dc = stream->ctx->dc; if (dc_stream_set_cursor_attributes(stream, attributes)) { dc_z10_restore(dc); From 636816caf0d961bfd41b9e7dace32dbf3548b4a6 Mon Sep 17 00:00:00 2001 From: Qiang Liu Date: Tue, 12 Aug 2025 20:30:21 +0800 Subject: [PATCH 1719/2653] drm/amdgpu: remove duplicated argument wptr_va The duplicate judgment of wptr_va could be removed to simplify the logic Signed-off-by: Qiang Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 8c2cdbe2f7a78..57435312470cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -572,7 +572,6 @@ int amdgpu_userq_ioctl(struct drm_device *dev, void *data, args->in.queue_size || args->in.rptr_va || args->in.wptr_va || - args->in.wptr_va || args->in.mqd || args->in.mqd_size) return -EINVAL; From 0236ebd4d8023e09e5ed7c9620c2f99937fe81f0 Mon Sep 17 00:00:00 2001 From: Chenglei Xie Date: Thu, 7 Aug 2025 16:52:34 -0400 Subject: [PATCH 1720/2653] drm/amdgpu: refactor bad_page_work for corner case handling When a poison is consumed on the guest before the guest receives the host's poison creation msg, a corner case may occur to have poison_handler complete processing earlier than it should to cause the guest to hang waiting for the req_bad_pages reply during a VF FLR, resulting in the VM becoming inaccessible in stress tests. To fix this issue, this patch refactored the mailbox sequence by seperating the bad_page_work into two parts req_bad_pages_work and handle_bad_pages_work. Old sequence: 1.Stop data exchange work 2.Guest sends MB_REQ_RAS_BAD_PAGES to host and keep polling for IDH_RAS_BAD_PAGES_READY 3.If the IDH_RAS_BAD_PAGES_READY arrives within timeout limit, re-init the data exchange region for updated bad page info else timeout with error message New sequence: req_bad_pages_work: 1.Stop data exhange work 2.Guest sends MB_REQ_RAS_BAD_PAGES to host Once Guest receives IDH_RAS_BAD_PAGES_READY event handle_bad_pages_work: 3.re-init the data exchange region for updated bad page info Signed-off-by: Chenglei Xie Reviewed-by: Shravan Kumar Gande --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 3 +- drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 32 +++++++++++++++++++--- drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 35 +++++++++++++++++++----- drivers/gpu/drm/amd/amdgpu/soc15.c | 1 - 4 files changed, 58 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 3da3ebb1d9a13..58accf2259b38 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -267,7 +267,8 @@ struct amdgpu_virt { struct amdgpu_irq_src rcv_irq; struct work_struct flr_work; - struct work_struct bad_pages_work; + struct work_struct req_bad_pages_work; + struct work_struct handle_bad_pages_work; struct amdgpu_mm_table mm_table; const struct amdgpu_virt_ops *ops; diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c index 48101a34e049f..9a40107a0869d 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -292,14 +292,32 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work) } } -static void xgpu_ai_mailbox_bad_pages_work(struct work_struct *work) +static void xgpu_ai_mailbox_req_bad_pages_work(struct work_struct *work) { - struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, bad_pages_work); + struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, req_bad_pages_work); struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt); if (down_read_trylock(&adev->reset_domain->sem)) { amdgpu_virt_fini_data_exchange(adev); amdgpu_virt_request_bad_pages(adev); + up_read(&adev->reset_domain->sem); + } +} + +/** + * xgpu_ai_mailbox_handle_bad_pages_work - Reinitialize the data exchange region to get fresh bad page information + * @work: pointer to the work_struct + * + * This work handler is triggered when bad pages are ready, and it reinitializes + * the data exchange region to retrieve updated bad page information from the host. + */ +static void xgpu_ai_mailbox_handle_bad_pages_work(struct work_struct *work) +{ + struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, handle_bad_pages_work); + struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt); + + if (down_read_trylock(&adev->reset_domain->sem)) { + amdgpu_virt_fini_data_exchange(adev); amdgpu_virt_init_data_exchange(adev); up_read(&adev->reset_domain->sem); } @@ -327,10 +345,15 @@ static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev, struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); switch (event) { + case IDH_RAS_BAD_PAGES_READY: + xgpu_ai_mailbox_send_ack(adev); + if (amdgpu_sriov_runtime(adev)) + schedule_work(&adev->virt.handle_bad_pages_work); + break; case IDH_RAS_BAD_PAGES_NOTIFICATION: xgpu_ai_mailbox_send_ack(adev); if (amdgpu_sriov_runtime(adev)) - schedule_work(&adev->virt.bad_pages_work); + schedule_work(&adev->virt.req_bad_pages_work); break; case IDH_UNRECOV_ERR_NOTIFICATION: xgpu_ai_mailbox_send_ack(adev); @@ -415,7 +438,8 @@ int xgpu_ai_mailbox_get_irq(struct amdgpu_device *adev) } INIT_WORK(&adev->virt.flr_work, xgpu_ai_mailbox_flr_work); - INIT_WORK(&adev->virt.bad_pages_work, xgpu_ai_mailbox_bad_pages_work); + INIT_WORK(&adev->virt.req_bad_pages_work, xgpu_ai_mailbox_req_bad_pages_work); + INIT_WORK(&adev->virt.handle_bad_pages_work, xgpu_ai_mailbox_handle_bad_pages_work); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c index f6d8597452ed0..457972aa56324 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c @@ -202,9 +202,6 @@ static int xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev, case IDH_REQ_RAS_CPER_DUMP: event = IDH_RAS_CPER_DUMP_READY; break; - case IDH_REQ_RAS_BAD_PAGES: - event = IDH_RAS_BAD_PAGES_READY; - break; default: break; } @@ -359,14 +356,32 @@ static void xgpu_nv_mailbox_flr_work(struct work_struct *work) } } -static void xgpu_nv_mailbox_bad_pages_work(struct work_struct *work) +static void xgpu_nv_mailbox_req_bad_pages_work(struct work_struct *work) { - struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, bad_pages_work); + struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, req_bad_pages_work); struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt); if (down_read_trylock(&adev->reset_domain->sem)) { amdgpu_virt_fini_data_exchange(adev); amdgpu_virt_request_bad_pages(adev); + up_read(&adev->reset_domain->sem); + } +} + +/** + * xgpu_nv_mailbox_handle_bad_pages_work - Reinitialize the data exchange region to get fresh bad page information + * @work: pointer to the work_struct + * + * This work handler is triggered when bad pages are ready, and it reinitializes + * the data exchange region to retrieve updated bad page information from the host. + */ +static void xgpu_nv_mailbox_handle_bad_pages_work(struct work_struct *work) +{ + struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, handle_bad_pages_work); + struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt); + + if (down_read_trylock(&adev->reset_domain->sem)) { + amdgpu_virt_fini_data_exchange(adev); amdgpu_virt_init_data_exchange(adev); up_read(&adev->reset_domain->sem); } @@ -397,10 +412,15 @@ static int xgpu_nv_mailbox_rcv_irq(struct amdgpu_device *adev, struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); switch (event) { + case IDH_RAS_BAD_PAGES_READY: + xgpu_nv_mailbox_send_ack(adev); + if (amdgpu_sriov_runtime(adev)) + schedule_work(&adev->virt.handle_bad_pages_work); + break; case IDH_RAS_BAD_PAGES_NOTIFICATION: xgpu_nv_mailbox_send_ack(adev); if (amdgpu_sriov_runtime(adev)) - schedule_work(&adev->virt.bad_pages_work); + schedule_work(&adev->virt.req_bad_pages_work); break; case IDH_UNRECOV_ERR_NOTIFICATION: xgpu_nv_mailbox_send_ack(adev); @@ -485,7 +505,8 @@ int xgpu_nv_mailbox_get_irq(struct amdgpu_device *adev) } INIT_WORK(&adev->virt.flr_work, xgpu_nv_mailbox_flr_work); - INIT_WORK(&adev->virt.bad_pages_work, xgpu_nv_mailbox_bad_pages_work); + INIT_WORK(&adev->virt.req_bad_pages_work, xgpu_nv_mailbox_req_bad_pages_work); + INIT_WORK(&adev->virt.handle_bad_pages_work, xgpu_nv_mailbox_handle_bad_pages_work); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 9e74c9822e622..9785fada4fa79 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -741,7 +741,6 @@ static void soc15_reg_base_init(struct amdgpu_device *adev) void soc15_set_virt_ops(struct amdgpu_device *adev) { adev->virt.ops = &xgpu_ai_virt_ops; - /* init soc15 reg base early enough so we can * request request full access for sriov before * set_ip_blocks. */ From d569b1b949ae580d396bd033b0659ea23b9ba70c Mon Sep 17 00:00:00 2001 From: Rafal Ostrowski Date: Fri, 11 Jul 2025 13:13:27 +0200 Subject: [PATCH 1721/2653] drm/amd/display: Add LSDMA Linear Sub Window Copy support [WHAT] Add support for LSDMA Linear Sub Window Copy command. Reviewed-by: Alvin Lee Signed-off-by: Rafal Ostrowski Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 58 ++++++++++++++++++-- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 36 +++++++++++- 2 files changed, 88 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index 714c468c010d3..55b3621966127 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -2010,11 +2010,12 @@ bool dmub_lsdma_init(struct dc_dmub_srv *dc_dmub_srv) return result; } -bool dmub_lsdma_send_linear_copy_packet( +bool dmub_lsdma_send_linear_copy_command( struct dc_dmub_srv *dc_dmub_srv, uint64_t src_addr, uint64_t dst_addr, - uint32_t count) + uint32_t count +) { struct dc_context *dc_ctx = dc_dmub_srv->ctx; union dmub_rb_cmd cmd; @@ -2042,9 +2043,54 @@ bool dmub_lsdma_send_linear_copy_packet( return result; } +bool dmub_lsdma_send_linear_sub_window_copy_command( + struct dc_dmub_srv *dc_dmub_srv, + struct lsdma_linear_sub_window_copy_params copy_data +) +{ + struct dc_context *dc_ctx = dc_dmub_srv->ctx; + union dmub_rb_cmd cmd; + enum dm_dmub_wait_type wait_type; + struct dmub_cmd_lsdma_data *lsdma_data = &cmd.lsdma.lsdma_data; + bool result; + + memset(&cmd, 0, sizeof(cmd)); + + cmd.cmd_common.header.type = DMUB_CMD__LSDMA; + cmd.cmd_common.header.sub_type = DMUB_CMD__LSDMA_LINEAR_SUB_WINDOW_COPY; + wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT; + + lsdma_data->u.linear_sub_window_copy_data.tmz = copy_data.tmz; + lsdma_data->u.linear_sub_window_copy_data.element_size = copy_data.element_size; + lsdma_data->u.linear_sub_window_copy_data.src_lo = copy_data.src_lo; + lsdma_data->u.linear_sub_window_copy_data.src_hi = copy_data.src_hi; + lsdma_data->u.linear_sub_window_copy_data.src_x = copy_data.src_x; + lsdma_data->u.linear_sub_window_copy_data.src_y = copy_data.src_y; + lsdma_data->u.linear_sub_window_copy_data.src_pitch = copy_data.src_pitch - 1; + lsdma_data->u.linear_sub_window_copy_data.src_slice_pitch = copy_data.src_slice_pitch - 1; + lsdma_data->u.linear_sub_window_copy_data.dst_lo = copy_data.dst_lo; + lsdma_data->u.linear_sub_window_copy_data.dst_hi = copy_data.dst_hi; + lsdma_data->u.linear_sub_window_copy_data.dst_x = copy_data.dst_x; + lsdma_data->u.linear_sub_window_copy_data.dst_y = copy_data.dst_y; + lsdma_data->u.linear_sub_window_copy_data.dst_pitch = copy_data.dst_pitch - 1; + lsdma_data->u.linear_sub_window_copy_data.dst_slice_pitch = copy_data.dst_slice_pitch - 1; + lsdma_data->u.linear_sub_window_copy_data.rect_x = copy_data.rect_x - 1; + lsdma_data->u.linear_sub_window_copy_data.rect_y = copy_data.rect_y - 1; + lsdma_data->u.linear_sub_window_copy_data.src_cache_policy = copy_data.src_cache_policy; + lsdma_data->u.linear_sub_window_copy_data.dst_cache_policy = copy_data.dst_cache_policy; + + result = dc_wake_and_execute_dmub_cmd(dc_ctx, &cmd, wait_type); + + if (!result) + DC_ERROR("LSDMA Linear Sub Window Copy failed in DMUB"); + + return result; +} + bool dmub_lsdma_send_tiled_to_tiled_copy_command( struct dc_dmub_srv *dc_dmub_srv, - struct lsdma_send_tiled_to_tiled_copy_command_params params) + struct lsdma_send_tiled_to_tiled_copy_command_params params +) { struct dc_context *dc_ctx = dc_dmub_srv->ctx; union dmub_rb_cmd cmd; @@ -2097,7 +2143,8 @@ bool dmub_lsdma_send_pio_copy_command( uint64_t src_addr, uint64_t dst_addr, uint32_t byte_count, - uint32_t overlap_disable) + uint32_t overlap_disable +) { struct dc_context *dc_ctx = dc_dmub_srv->ctx; union dmub_rb_cmd cmd; @@ -2130,7 +2177,8 @@ bool dmub_lsdma_send_pio_constfill_command( struct dc_dmub_srv *dc_dmub_srv, uint64_t dst_addr, uint32_t byte_count, - uint32_t data) + uint32_t data +) { struct dc_context *dc_ctx = dc_dmub_srv->ctx; union dmub_rb_cmd cmd; diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h index 8ea320f212699..7ef93444ef3cf 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h @@ -211,11 +211,45 @@ void dc_dmub_srv_fams2_passthrough_flip( int surface_count); bool dmub_lsdma_init(struct dc_dmub_srv *dc_dmub_srv); -bool dmub_lsdma_send_linear_copy_packet( +bool dmub_lsdma_send_linear_copy_command( struct dc_dmub_srv *dc_dmub_srv, uint64_t src_addr, uint64_t dst_addr, uint32_t count); + +struct lsdma_linear_sub_window_copy_params { + uint32_t src_lo; + uint32_t src_hi; + + uint32_t dst_lo; + uint32_t dst_hi; + + uint32_t src_x : 16; + uint32_t src_y : 16; + + uint32_t dst_x : 16; + uint32_t dst_y : 16; + + uint32_t rect_x : 16; + uint32_t rect_y : 16; + + uint32_t src_pitch : 16; + uint32_t dst_pitch : 16; + + uint32_t src_slice_pitch; + uint32_t dst_slice_pitch; + + uint32_t tmz : 1; + uint32_t element_size : 3; + uint32_t src_cache_policy : 3; + uint32_t dst_cache_policy : 3; + uint32_t padding : 22; +}; + +bool dmub_lsdma_send_linear_sub_window_copy_command( + struct dc_dmub_srv *dc_dmub_srv, + struct lsdma_linear_sub_window_copy_params copy_data +); bool dmub_lsdma_send_pio_copy_command( struct dc_dmub_srv *dc_dmub_srv, uint64_t src_addr, From fc16ee5bead4d81cd046c262d812c08b1bc8b2b3 Mon Sep 17 00:00:00 2001 From: Lohita Mudimela Date: Thu, 17 Jul 2025 16:43:36 +0530 Subject: [PATCH 1722/2653] drm/amd/display: Refactor DPP enum for backwards compatibility [WHY] Conflict for enum type in DPP source files. [HOW] Refactor DPP source files to resolve the enum conflicts. Reviewed-by: Ilya Bakoulin Reviewed-by: Martin Leung Signed-off-by: Lohita Mudimela Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../amd/display/dc/dpp/dcn401/dcn401_dpp.h | 10 ++++++ .../display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 36 +++++++------------ 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h index 5a6a861402b3c..5f6b431ec3980 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h @@ -673,6 +673,16 @@ struct dcn401_dpp { struct pwl_params pwl_data; }; +enum dcn401_dscl_mode_sel { + DCN401_DSCL_MODE_SCALING_444_BYPASS = 0, + DCN401_DSCL_MODE_SCALING_444_RGB_ENABLE = 1, + DCN401_DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2, + DCN401_DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3, + DCN401_DSCL_MODE_SCALING_420_LUMA_BYPASS = 4, + DCN401_DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5, + DCN401_DSCL_MODE_DSCL_BYPASS = 6 +}; + bool dpp401_construct(struct dcn401_dpp *dpp401, struct dc_context *ctx, uint32_t inst, diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c index 2f92e7d4981ba..6df3419f825f4 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c @@ -78,16 +78,6 @@ enum dscl_autocal_mode { AUTOCAL_MODE_AUTOREPLICATE = 3 }; -enum dscl_mode_sel { - DSCL_MODE_SCALING_444_BYPASS = 0, - DSCL_MODE_SCALING_444_RGB_ENABLE = 1, - DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2, - DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3, - DSCL_MODE_SCALING_420_LUMA_BYPASS = 4, - DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5, - DSCL_MODE_DSCL_BYPASS = 6 -}; - static int dpp401_dscl_get_pixel_depth_val(enum lb_pixel_depth depth) { if (depth == LB_PIXEL_DEPTH_30BPP) @@ -122,7 +112,7 @@ static bool dpp401_dscl_is_420_format(enum pixel_format format) return false; } -static enum dscl_mode_sel dpp401_dscl_get_dscl_mode( +static enum dcn401_dscl_mode_sel dpp401_dscl_get_dscl_mode( struct dpp *dpp_base, const struct scaler_data *data, bool dbg_always_scale) @@ -132,7 +122,7 @@ static enum dscl_mode_sel dpp401_dscl_get_dscl_mode( if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { /* DSCL is processing data in fixed format */ if (data->format == PIXEL_FORMAT_FP16) - return DSCL_MODE_DSCL_BYPASS; + return DCN401_DSCL_MODE_DSCL_BYPASS; } if (data->ratios.horz.value == one @@ -140,20 +130,20 @@ static enum dscl_mode_sel dpp401_dscl_get_dscl_mode( && data->ratios.horz_c.value == one && data->ratios.vert_c.value == one && !dbg_always_scale) - return DSCL_MODE_SCALING_444_BYPASS; + return DCN401_DSCL_MODE_SCALING_444_BYPASS; if (!dpp401_dscl_is_420_format(data->format)) { if (dpp401_dscl_is_video_format(data->format)) - return DSCL_MODE_SCALING_444_YCBCR_ENABLE; + return DCN401_DSCL_MODE_SCALING_444_YCBCR_ENABLE; else - return DSCL_MODE_SCALING_444_RGB_ENABLE; + return DCN401_DSCL_MODE_SCALING_444_RGB_ENABLE; } if (data->ratios.horz.value == one && data->ratios.vert.value == one) - return DSCL_MODE_SCALING_420_LUMA_BYPASS; + return DCN401_DSCL_MODE_SCALING_420_LUMA_BYPASS; if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one) - return DSCL_MODE_SCALING_420_CHROMA_BYPASS; + return DCN401_DSCL_MODE_SCALING_420_CHROMA_BYPASS; - return DSCL_MODE_SCALING_420_YCBCR_ENABLE; + return DCN401_DSCL_MODE_SCALING_420_YCBCR_ENABLE; } static void dpp401_power_on_dscl( @@ -1071,7 +1061,7 @@ void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base, uint32_t v_num_taps_c = scl_data->taps.v_taps_c - 1; uint32_t h_num_taps = scl_data->taps.h_taps - 1; uint32_t h_num_taps_c = scl_data->taps.h_taps_c - 1; - enum dscl_mode_sel dscl_mode = dpp401_dscl_get_dscl_mode( + enum dcn401_dscl_mode_sel dscl_mode = dpp401_dscl_get_dscl_mode( dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN && scl_data->format <= PIXEL_FORMAT_VIDEO_END; @@ -1102,7 +1092,7 @@ void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base, dpp->scl_data = *scl_data; if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) { - dscl_mode = (enum dscl_mode_sel) scl_data->dscl_prog_data.dscl_mode; + dscl_mode = (enum dcn401_dscl_mode_sel) scl_data->dscl_prog_data.dscl_mode; rect = (struct rect *)&scl_data->dscl_prog_data.recout; mpc_width = scl_data->dscl_prog_data.mpc_size.width; mpc_height = scl_data->dscl_prog_data.mpc_size.height; @@ -1112,7 +1102,7 @@ void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base, h_num_taps_c = scl_data->dscl_prog_data.taps.h_taps_c; } if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) { - if (dscl_mode != DSCL_MODE_DSCL_BYPASS) + if (dscl_mode != DCN401_DSCL_MODE_DSCL_BYPASS) dpp401_power_on_dscl(dpp_base, true); } @@ -1139,7 +1129,7 @@ void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base, /* SCL mode */ REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode); - if (dscl_mode == DSCL_MODE_DSCL_BYPASS) { + if (dscl_mode == DCN401_DSCL_MODE_DSCL_BYPASS) { if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) dpp401_power_on_dscl(dpp_base, false); return; @@ -1149,7 +1139,7 @@ void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base, lb_config = dpp401_dscl_find_lb_memory_config(dpp, scl_data); dpp401_dscl_set_lb(dpp, &scl_data->lb_params, lb_config); - if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS) { + if (dscl_mode == DCN401_DSCL_MODE_SCALING_444_BYPASS) { if (dpp->base.ctx->dc->config.prefer_easf) dpp401_dscl_disable_easf(dpp_base, scl_data); dpp401_dscl_program_isharp(dpp_base, scl_data, program_isharp_1dlut, &bs_coeffs_updated); From fa561da4128dc5c3bc5517045aeaec159ef3c216 Mon Sep 17 00:00:00 2001 From: Clay King Date: Wed, 30 Jul 2025 10:23:19 -0400 Subject: [PATCH 1723/2653] drm/amd/display: Delete unused functions [WHAT] Removing unused code Reviewed-by: Joshua Aberback Signed-off-by: Clay King Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 15 --------------- .../drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c | 8 -------- .../drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h | 5 ----- 3 files changed, 28 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index 14f0304e3eb96..22960ee03dee4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -1069,21 +1069,6 @@ struct mpc_funcs { */ void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const enum MCM_LUT_XABLE xable, bool lut_bank_a, int mpcc_id); - /** - * @program_3dlut_size: - * - * Program 3D LUT size. - * - * Parameters: - * - [in/out] mpc - MPC context. - * - [in] is_17x17x17 - is 3dlut 17x17x17 - * - [in] mpcc_id - * - * Return: - * - * void - */ - void (*program_3dlut_size)(struct mpc *mpc, bool is_17x17x17, int mpcc_id); /** * @mcm: diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c index f3fb3fe137577..e1a0308dee57a 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c @@ -287,13 +287,6 @@ void mpc401_program_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_I } } -void mpc401_program_3dlut_size(struct mpc *mpc, bool is_17x17x17, int mpcc_id) -{ - struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); - - REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, is_17x17x17 ? 0 : 1); -} - void mpc_program_gamut_remap( struct mpc *mpc, unsigned int mpcc_id, @@ -611,7 +604,6 @@ static const struct mpc_funcs dcn401_mpc_funcs = { .populate_lut = mpc401_populate_lut, .program_lut_read_write_control = mpc401_program_lut_read_write_control, .program_lut_mode = mpc401_program_lut_mode, - .program_3dlut_size = mpc401_program_3dlut_size, }; diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h index eb0c68d0b0c76..fdc42f8ab3ff5 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h @@ -221,11 +221,6 @@ void mpc401_program_lut_read_write_control( bool lut_bank_a, int mpcc_id); -void mpc401_program_3dlut_size( - struct mpc *mpc, - bool is_17x17x17, - int mpcc_id); - void mpc401_set_gamut_remap( struct mpc *mpc, int mpcc_id, From 7e0297ef97eb8f3e1ad1fd9263fba9e59b0aa1d9 Mon Sep 17 00:00:00 2001 From: Rafal Ostrowski Date: Tue, 5 Aug 2025 14:53:37 +0200 Subject: [PATCH 1724/2653] drm/amd/display: Align LSDMA commands fields [WHY] DC LSDMA functions had to remember to extract 1 from several fields to be compliant with DMUB LSDMA commands interface. Now this logic is moved to DMUB. [HOW] Moved extraction by 1 in several fields of LSDMA commands to DMUB. Changed DC to not do it. Reviewed-by: Alvin Lee Signed-off-by: Rafal Ostrowski Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 24 ++++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index 55b3621966127..53a088ebddefe 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -2066,16 +2066,16 @@ bool dmub_lsdma_send_linear_sub_window_copy_command( lsdma_data->u.linear_sub_window_copy_data.src_hi = copy_data.src_hi; lsdma_data->u.linear_sub_window_copy_data.src_x = copy_data.src_x; lsdma_data->u.linear_sub_window_copy_data.src_y = copy_data.src_y; - lsdma_data->u.linear_sub_window_copy_data.src_pitch = copy_data.src_pitch - 1; - lsdma_data->u.linear_sub_window_copy_data.src_slice_pitch = copy_data.src_slice_pitch - 1; + lsdma_data->u.linear_sub_window_copy_data.src_pitch = copy_data.src_pitch; + lsdma_data->u.linear_sub_window_copy_data.src_slice_pitch = copy_data.src_slice_pitch; lsdma_data->u.linear_sub_window_copy_data.dst_lo = copy_data.dst_lo; lsdma_data->u.linear_sub_window_copy_data.dst_hi = copy_data.dst_hi; lsdma_data->u.linear_sub_window_copy_data.dst_x = copy_data.dst_x; lsdma_data->u.linear_sub_window_copy_data.dst_y = copy_data.dst_y; - lsdma_data->u.linear_sub_window_copy_data.dst_pitch = copy_data.dst_pitch - 1; - lsdma_data->u.linear_sub_window_copy_data.dst_slice_pitch = copy_data.dst_slice_pitch - 1; - lsdma_data->u.linear_sub_window_copy_data.rect_x = copy_data.rect_x - 1; - lsdma_data->u.linear_sub_window_copy_data.rect_y = copy_data.rect_y - 1; + lsdma_data->u.linear_sub_window_copy_data.dst_pitch = copy_data.dst_pitch; + lsdma_data->u.linear_sub_window_copy_data.dst_slice_pitch = copy_data.dst_slice_pitch; + lsdma_data->u.linear_sub_window_copy_data.rect_x = copy_data.rect_x; + lsdma_data->u.linear_sub_window_copy_data.rect_y = copy_data.rect_y; lsdma_data->u.linear_sub_window_copy_data.src_cache_policy = copy_data.src_cache_policy; lsdma_data->u.linear_sub_window_copy_data.dst_cache_policy = copy_data.dst_cache_policy; @@ -2112,20 +2112,20 @@ bool dmub_lsdma_send_tiled_to_tiled_copy_command( lsdma_data->u.tiled_copy_data.src_y = params.src_y; lsdma_data->u.tiled_copy_data.dst_x = params.dst_x; lsdma_data->u.tiled_copy_data.dst_y = params.dst_y; - lsdma_data->u.tiled_copy_data.src_width = params.src_width - 1; // LSDMA controller expects width -1 - lsdma_data->u.tiled_copy_data.dst_width = params.dst_width - 1; // LSDMA controller expects width -1 + lsdma_data->u.tiled_copy_data.src_width = params.src_width; + lsdma_data->u.tiled_copy_data.dst_width = params.dst_width; lsdma_data->u.tiled_copy_data.src_swizzle_mode = params.swizzle_mode; lsdma_data->u.tiled_copy_data.dst_swizzle_mode = params.swizzle_mode; lsdma_data->u.tiled_copy_data.src_element_size = params.element_size; lsdma_data->u.tiled_copy_data.dst_element_size = params.element_size; - lsdma_data->u.tiled_copy_data.rect_x = params.rect_x - 1; - lsdma_data->u.tiled_copy_data.rect_y = params.rect_y - 1; + lsdma_data->u.tiled_copy_data.rect_x = params.rect_x; + lsdma_data->u.tiled_copy_data.rect_y = params.rect_y; lsdma_data->u.tiled_copy_data.dcc = params.dcc; lsdma_data->u.tiled_copy_data.tmz = params.tmz; lsdma_data->u.tiled_copy_data.read_compress = params.read_compress; lsdma_data->u.tiled_copy_data.write_compress = params.write_compress; - lsdma_data->u.tiled_copy_data.src_height = params.src_height - 1; // LSDMA controller expects height -1 - lsdma_data->u.tiled_copy_data.dst_height = params.dst_height - 1; // LSDMA controller expects height -1 + lsdma_data->u.tiled_copy_data.src_height = params.src_height; + lsdma_data->u.tiled_copy_data.dst_height = params.dst_height; lsdma_data->u.tiled_copy_data.data_format = params.data_format; lsdma_data->u.tiled_copy_data.max_com = params.max_com; lsdma_data->u.tiled_copy_data.max_uncom = params.max_uncom; From 1a7bccc1d2bf6dd34f8344c9cbc913754ba325ab Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Tue, 5 Aug 2025 15:18:02 -0400 Subject: [PATCH 1725/2653] drm/amd/display: Setup Second Stutter Watermark Implementation [WHY & HOW] Setup initial changes required to program another set of watermarks for a 2nd stutter mode. The 2nd stutter mode will be lower power but have higher enter/exit latencies. PMFW to choose which stutter mode to use based on stutter efficiences to see if original stutter (LP1) or low power stutter (LP2) will result in better power savings. Reviewed-by: Alvin Lee Signed-off-by: Austin Zheng Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 9 +++++++++ .../display/dc/dml2/dml21/dml21_translation_helper.c | 2 ++ .../dc/dml2/dml21/inc/dml_top_dchub_registers.h | 2 ++ .../dc/dml2/dml21/inc/dml_top_soc_parameter_types.h | 2 ++ .../amd/display/dc/dml2/dml21/inc/dml_top_types.h | 2 ++ .../dml21/src/dml2_core/dml2_core_shared_types.h | 12 ++++++++++++ 6 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index dc017411c07e3..4e9abd823ecf4 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -694,6 +694,15 @@ struct dc_clocks { int idle_fclk_khz; int subvp_prefetch_dramclk_khz; int subvp_prefetch_fclk_khz; + + /* Stutter efficiency is technically not clock values + * but stored here so the values are part of the update_clocks call similar to num_ways + * Efficiencies are stored as percentage (0-100) + */ + struct { + uint8_t base_efficiency; //LP1 + uint8_t low_power_efficiency; //LP2 + } stutter_efficiency; }; struct dc_bw_validation_profile { diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c index a06217a9eef60..23fdb17f851a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c @@ -1165,6 +1165,8 @@ void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state context->bw_ctx.bw.dcn.clk.socclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.socclk_khz; context->bw_ctx.bw.dcn.clk.subvp_prefetch_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.uclk_khz; context->bw_ctx.bw.dcn.clk.subvp_prefetch_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz; + context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency; + context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency; } static struct dml2_dchub_watermark_regs *wm_set_index_to_dc_wm_set(union dcn_watermark_set *watermarks, const enum dml2_dchub_watermark_reg_set_index wm_index) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h index b05030926ce85..91955bbe24b86 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h @@ -159,6 +159,8 @@ struct dml2_dchub_watermark_regs { uint32_t sr_exit; uint32_t sr_enter_z8; uint32_t sr_exit_z8; + uint32_t sr_enter_low_power; + uint32_t sr_exit_low_power; uint32_t uclk_pstate; uint32_t fclk_pstate; uint32_t temp_read_or_ppt; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h index 8c9f414aa6bf9..176f559476644 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h @@ -96,6 +96,8 @@ struct dml2_soc_power_management_parameters { double g7_temperature_read_blackout_us; double stutter_enter_plus_exit_latency_us; double stutter_exit_latency_us; + double low_power_stutter_enter_plus_exit_latency_us; + double low_power_stutter_exit_latency_us; double z8_stutter_enter_plus_exit_latency_us; double z8_stutter_exit_latency_us; double z8_min_idle_time; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h index 98c0234e2f474..7de10a95cfdb1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h @@ -417,6 +417,8 @@ struct dml2_display_cfg_programming { struct { bool supported_in_blank; // Changing to configurations where this is false requires stutter to be disabled during the transition + uint8_t base_percent_efficiency; //LP1 + uint8_t low_power_percent_efficiency; //LP2 } stutter; struct { diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h index 28687565ac222..ffb8c09f37a5c 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h @@ -201,6 +201,8 @@ struct dml2_core_internal_watermarks { double WritebackFCLKChangeWatermark; double StutterExitWatermark; double StutterEnterPlusExitWatermark; + double LowPowerStutterExitWatermark; + double LowPowerStutterEnterPlusExitWatermark; double Z8StutterExitWatermark; double Z8StutterEnterPlusExitWatermark; double USRRetrainingWatermark; @@ -877,6 +879,9 @@ struct dml2_core_internal_mode_program { double Z8StutterEfficiency; unsigned int Z8NumberOfStutterBurstsPerFrame; double Z8StutterEfficiencyNotIncludingVBlank; + double LowPowerStutterEfficiency; + double LowPowerStutterEfficiencyNotIncludingVBlank; + unsigned int LowPowerNumberOfStutterBurstsPerFrame; double StutterPeriod; double Z8StutterEfficiencyBestCase; unsigned int Z8NumberOfStutterBurstsPerFrameBestCase; @@ -1016,6 +1021,8 @@ struct dml2_core_internal_SOCParametersList { double FCLKChangeLatency; double SRExitTime; double SREnterPlusExitTime; + double SRExitTimeLowPower; + double SREnterPlusExitTimeLowPower; double SRExitZ8Time; double SREnterPlusExitZ8Time; double USRRetrainingLatency; @@ -1851,9 +1858,11 @@ struct dml2_core_calcs_CalculateStutterEfficiency_params { unsigned int CompbufReservedSpaceZs; bool hw_debug5; double SRExitTime; + double SRExitTimeLowPower; double SRExitZ8Time; bool SynchronizeTimings; double StutterEnterPlusExitWatermark; + double LowPowerStutterEnterPlusExitWatermark; double Z8StutterEnterPlusExitWatermark; bool ProgressiveToInterlaceUnitInOPP; double *MinTTUVBlank; @@ -1879,7 +1888,10 @@ struct dml2_core_calcs_CalculateStutterEfficiency_params { // output double *StutterEfficiencyNotIncludingVBlank; double *StutterEfficiency; + double *LowPowerStutterEfficiencyNotIncludingVBlank; + double *LowPowerStutterEfficiency; unsigned int *NumberOfStutterBurstsPerFrame; + unsigned int *LowPowerNumberOfStutterBurstsPerFrame; double *Z8StutterEfficiencyNotIncludingVBlank; double *Z8StutterEfficiency; unsigned int *Z8NumberOfStutterBurstsPerFrame; From ddda1c6b28254d2809eb48dbad7ed7ef41369dc0 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 24 Jul 2025 15:00:43 -0500 Subject: [PATCH 1726/2653] drm/amd/display: Avoid a NULL pointer dereference [WHY] Although unlikely drm_atomic_get_new_connector_state() or drm_atomic_get_old_connector_state() can return NULL. [HOW] Check returns before dereference. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Harry Wentland Signed-off-by: Mario Limonciello Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index cfc1e5f62b468..1d79da7af83dd 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8044,6 +8044,9 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, #endif int ret; + if (WARN_ON(unlikely(!old_con_state || !new_con_state))) + return -EINVAL; + trace_amdgpu_dm_connector_atomic_check(new_con_state); if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { From 058c1b76ed4ce46247611528c500bbb50212a499 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 8 Aug 2025 17:25:15 -0400 Subject: [PATCH 1727/2653] drm/amd/display: [FW Promotion] Release 0.1.23.0 1. Fix loop counter. 2. Check whether rb->capacity is 0. Acked-by: Sun peng (Leo) Li Signed-off-by: Taimur Hassan Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 21 ++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 52295efdba636..d7008d84c1ec1 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -6542,15 +6542,18 @@ static inline bool dmub_rb_full(struct dmub_rb *rb) static inline bool dmub_rb_push_front(struct dmub_rb *rb, const union dmub_rb_cmd *cmd) { - uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); - const uint64_t *src = (const uint64_t *)cmd; + uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; + const uint8_t *src = (const uint8_t *)cmd; uint8_t i; + if (rb->capacity == 0) + return false; + if (dmub_rb_full(rb)) return false; // copying data - for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) + for (i = 0; i < DMUB_RB_CMD_SIZE; i++) *dst++ = *src++; rb->wrpt += DMUB_RB_CMD_SIZE; @@ -6575,6 +6578,9 @@ static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; const uint8_t *src = (const uint8_t *)cmd; + if (rb->capacity == 0) + return false; + if (dmub_rb_full(rb)) return false; @@ -6620,6 +6626,9 @@ static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, uint32_t num_cmds, uint32_t *next_rptr) { + if (rb->capacity == 0) + return; + *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; if (*next_rptr >= rb->capacity) @@ -6683,6 +6692,9 @@ static inline bool dmub_rb_out_front(struct dmub_rb *rb, */ static inline bool dmub_rb_pop_front(struct dmub_rb *rb) { + if (rb->capacity == 0) + return false; + if (dmub_rb_empty(rb)) return false; @@ -6707,6 +6719,9 @@ static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) uint32_t rptr = rb->rptr; uint32_t wptr = rb->wrpt; + if (rb->capacity == 0) + return; + while (rptr != wptr) { uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); uint8_t i; From 8980c0b15a36828425df9df3550824510d6fd1c5 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 8 Aug 2025 17:25:32 -0500 Subject: [PATCH 1728/2653] drm/amd/display: Promote DC to 3.2.346 This version brings along following updates: - Fix Xorg desktop unresponsive on Replay panel - [FW Promotion] Release 0.1.23.0 - Avoid a NULL pointer dereference - Attach privacy screen to DRM connector - Setup Second Stutter Watermark Implementation - Align LSDMA commands fields - Delete unused functions - Optimize amdgpu_dm_atomic_commit_tail() - Add primary plane to commits for correct VRR handling - Refactor DPP enum for backwards compatibility. - Add LSDMA Linear Sub Window Copy support Acked-by: Sun peng (Leo) Li Signed-off-by: Taimur Hassan Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 4e9abd823ecf4..927fbdc4cf9ef 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.345" +#define DC_VER "3.2.346" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From 3b82656e0c0a17e5dbe8fdfcba2edff718287c6e Mon Sep 17 00:00:00 2001 From: Chenyuan Yang Date: Wed, 23 Jul 2025 21:36:41 -0500 Subject: [PATCH 1729/2653] drm/amd/display: Add null pointer check in mod_hdcp_hdcp1_create_session() The function mod_hdcp_hdcp1_create_session() calls the function get_first_active_display(), but does not check its return value. The return value is a null pointer if the display list is empty. This will lead to a null pointer dereference. Add a null pointer check for get_first_active_display() and return MOD_HDCP_STATUS_DISPLAY_NOT_FOUND if the function return null. This is similar to the commit c3e9826a2202 ("drm/amd/display: Add null pointer check for get_first_active_display()"). Fixes: 2deade5ede56 ("drm/amd/display: Remove hdcp display state with mst fix") Signed-off-by: Chenyuan Yang Reviewed-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c index e58e7b93810be..6b7db8ec9a53b 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c @@ -260,6 +260,9 @@ enum mod_hdcp_status mod_hdcp_hdcp1_create_session(struct mod_hdcp *hdcp) return MOD_HDCP_STATUS_FAILURE; } + if (!display) + return MOD_HDCP_STATUS_DISPLAY_NOT_FOUND; + hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf; mutex_lock(&psp->hdcp_context.mutex); From 26c982eefc29f07a7d8ba367f1d62a9f5bba9282 Mon Sep 17 00:00:00 2001 From: Xichao Zhao Date: Thu, 31 Jul 2025 15:54:50 +0800 Subject: [PATCH 1730/2653] drm/amd/display: Clean up coding style Adjust whitespace around operators to improve code readability and comply with kernel coding style guidelines. These changes are purely stylistic and introduce no functional modifications. Signed-off-by: Xichao Zhao Reviewed-by: Alex Hung Tested-by: Dan Wheeler --- .../amd/display/dc/link/protocols/link_dp_capability.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 9e24ae6e9c93c..7ff8b27db1e34 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -1526,8 +1526,8 @@ bool read_is_mst_supported(struct dc_link *link) return false; } - rev.raw = 0; - cap.raw = 0; + rev.raw = 0; + cap.raw = 0; st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw, sizeof(rev)); @@ -2126,13 +2126,13 @@ void detect_edp_sink_caps(struct dc_link *link) &backlight_adj_cap, sizeof(backlight_adj_cap)); link->dpcd_caps.dynamic_backlight_capable_edp = - (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false; + (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true : false; core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_1, &general_edp_cap, sizeof(general_edp_cap)); link->dpcd_caps.set_power_state_capable_edp = - (general_edp_cap & DP_EDP_SET_POWER_CAP) ? true:false; + (general_edp_cap & DP_EDP_SET_POWER_CAP) ? true : false; set_default_brightness_aux(link); From b513136550ca2aefe1f7ed54d2b07c27294f4db6 Mon Sep 17 00:00:00 2001 From: Liao Yuanhong Date: Wed, 6 Aug 2025 20:41:20 +0800 Subject: [PATCH 1731/2653] drm/amd/display: Use swap() to simplify code Replace the original swapping logic with swap() to improve readability and remove temporary variables Signed-off-by: Liao Yuanhong Reviewed-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c index 5f1b49a500495..4cfe64aa84927 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c @@ -473,7 +473,6 @@ static void sort_pipes_for_splitting(struct dc_plane_pipe_pool *pipes) { bool sorted, swapped; unsigned int cur_index; - unsigned int temp; int odm_slice_index; for (odm_slice_index = 0; odm_slice_index < pipes->num_pipes_assigned_to_plane_for_odm_combine; odm_slice_index++) { @@ -489,9 +488,8 @@ static void sort_pipes_for_splitting(struct dc_plane_pipe_pool *pipes) swapped = false; while (!sorted) { if (pipes->pipes_assigned_to_plane[odm_slice_index][cur_index] > pipes->pipes_assigned_to_plane[odm_slice_index][cur_index + 1]) { - temp = pipes->pipes_assigned_to_plane[odm_slice_index][cur_index]; - pipes->pipes_assigned_to_plane[odm_slice_index][cur_index] = pipes->pipes_assigned_to_plane[odm_slice_index][cur_index + 1]; - pipes->pipes_assigned_to_plane[odm_slice_index][cur_index + 1] = temp; + swap(pipes->pipes_assigned_to_plane[odm_slice_index][cur_index + 1], + pipes->pipes_assigned_to_plane[odm_slice_index][cur_index]); swapped = true; } From 5d28951364b702f1486827331e59107dcc026b39 Mon Sep 17 00:00:00 2001 From: Xichao Zhao Date: Fri, 8 Aug 2025 10:52:09 +0800 Subject: [PATCH 1732/2653] drm/amd/display: replace min/max nesting with clamp() The clamp() macro explicitly expresses the intent of constraining a value within bounds.Therefore, replacing min(max(a, b), c) with clamp(val, lo, hi) can improve code readability. Signed-off-by: Xichao Zhao Reviewed-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c index 2066a65c69bbc..1aaa77265eede 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c @@ -449,12 +449,12 @@ void dcn301_fpu_calculate_wm_and_dlg(struct dc *dc, &context->bw_ctx.dml, pipes, pipe_cnt); /* WM Set C */ table_entry = &bw_params->wm_table.entries[WM_C]; - vlevel = min(max(vlevel_req, 2), vlevel_max); + vlevel = clamp(vlevel_req, 2, vlevel_max); calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, &context->bw_ctx.dml, pipes, pipe_cnt); /* WM Set B */ table_entry = &bw_params->wm_table.entries[WM_B]; - vlevel = min(max(vlevel_req, 1), vlevel_max); + vlevel = clamp(vlevel_req, 1, vlevel_max); calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, &context->bw_ctx.dml, pipes, pipe_cnt); From d0514ecf2f55dcd2464bfc084216159902650a8b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 31 Jul 2025 11:43:46 +0200 Subject: [PATCH 1733/2653] drm/amd/display: Don't overclock DCE 6 by 15% MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The extra 15% clock was added as a workaround for a Polaris issue which uses DCE 11, and should not have been used on DCE 6 which is already hardcoded to the highest possible display clock. Unfortunately, the extra 15% was mistakenly copied and kept even on code paths which don't affect Polaris. This commit fixes that and also adds a check to make sure not to exceed the maximum DCE 6 display clock. Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris") Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific") Fixes: 3ecb3b794e2c ("drm/amd/display: dc/clk_mgr: add support for SI parts (v2)") Signed-off-by: Timur Kristóf Acked-by: Alex Deucher Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Hung --- .../gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c index 0267644717b27..cfd7309f2c6ac 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c @@ -123,11 +123,9 @@ static void dce60_update_clocks(struct clk_mgr *clk_mgr_base, { struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); struct dm_pp_power_level_change_request level_change_req; - int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; - - /*TODO: W/A for dal3 linux, investigate why this works */ - if (!clk_mgr_dce->dfs_bypass_active) - patched_disp_clk = patched_disp_clk * 115 / 100; + const int max_disp_clk = + clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz; + int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz); level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); /* get max clock state from PPLIB */ From 9088b177474675e50ea2f475a48292d0c8cc855e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 31 Jul 2025 11:43:48 +0200 Subject: [PATCH 1734/2653] drm/amd/display: Find first CRTC and its line time in dce110_fill_display_configs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit dce110_fill_display_configs is shared between DCE 6-11, and finding the first CRTC and its line time is relevant to DCE 6 too. Move the code to find it from DCE 11 specific code. Signed-off-by: Timur Kristóf Acked-by: Alex Deucher Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Hung --- .../dc/clk_mgr/dce110/dce110_clk_mgr.c | 30 ++++++++++++------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c index f8409453434c1..baeac8f1c04f2 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c @@ -120,9 +120,12 @@ void dce110_fill_display_configs( const struct dc_state *context, struct dm_pp_display_configuration *pp_display_cfg) { + struct dc *dc = context->clk_mgr->ctx->dc; int j; int num_cfgs = 0; + pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator; + for (j = 0; j < context->stream_count; j++) { int k; @@ -164,6 +167,23 @@ void dce110_fill_display_configs( cfg->v_refresh /= stream->timing.h_total; cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) / stream->timing.v_total; + + /* Find first CRTC index and calculate its line time. + * This is necessary for DPM on SI GPUs. + */ + if (cfg->pipe_idx < pp_display_cfg->crtc_index) { + const struct dc_crtc_timing *timing = + &context->streams[0]->timing; + + pp_display_cfg->crtc_index = cfg->pipe_idx; + pp_display_cfg->line_time_in_us = + timing->h_total * 10000 / timing->pix_clk_100hz; + } + } + + if (!num_cfgs) { + pp_display_cfg->crtc_index = 0; + pp_display_cfg->line_time_in_us = 0; } pp_display_cfg->display_count = num_cfgs; @@ -232,16 +252,6 @@ void dce11_pplib_apply_display_requirements( dce110_fill_display_configs(context, pp_display_cfg); - /* TODO: is this still applicable?*/ - if (pp_display_cfg->display_count == 1) { - const struct dc_crtc_timing *timing = - &context->streams[0]->timing; - - pp_display_cfg->crtc_index = - pp_display_cfg->disp_configs[0].pipe_idx; - pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz; - } - if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); } From d2f4140c0ed924720c42bf0bb2e856931fd726ff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 31 Jul 2025 11:43:49 +0200 Subject: [PATCH 1735/2653] drm/amd/display: Fill display clock and vblank time in dce110_fill_display_configs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Also needed by DCE 6. This way the code that gathers this info can be shared between different DCE versions and doesn't have to be repeated. Signed-off-by: Timur Kristóf Acked-by: Alex Deucher Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Hung --- .../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 2 -- .../drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 10 +++------- .../drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 2 -- 3 files changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index f5ad0a1770388..e846e49203939 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -391,8 +391,6 @@ static void dce_pplib_apply_display_requirements( { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; - pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); - dce110_fill_display_configs(context, pp_display_cfg); if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c index baeac8f1c04f2..13cf415e38e50 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c @@ -124,6 +124,9 @@ void dce110_fill_display_configs( int j; int num_cfgs = 0; + pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); + pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz; + pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator; for (j = 0; j < context->stream_count; j++) { @@ -243,13 +246,6 @@ void dce11_pplib_apply_display_requirements( pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; - pp_display_cfg->avail_mclk_switch_time_us = - dce110_get_min_vblank_time_us(context); - /* TODO: dce11.2*/ - pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; - - pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz; - dce110_fill_display_configs(context, pp_display_cfg); if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c index cfd7309f2c6ac..7044b437fe9d9 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c @@ -109,8 +109,6 @@ static void dce60_pplib_apply_display_requirements( { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; - pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); - dce110_fill_display_configs(context, pp_display_cfg); if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) From 8eaaa599afea6ba891fdeb5a5231c254df456c79 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 31 Jul 2025 11:43:50 +0200 Subject: [PATCH 1736/2653] drm/amd/display: Don't warn when missing DCE encoder caps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On some GPUs the VBIOS just doesn't have encoder caps, or maybe not for every encoder. This isn't really a problem and it's handled well, so let's not litter the logs with it. Signed-off-by: Timur Kristóf Acked-by: Alex Deucher Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 4a9d07c31bc5b..0c50fe266c8a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -896,13 +896,13 @@ void dce110_link_encoder_construct( enc110->base.id, &bp_cap_info); /* Override features with DCE-specific values */ - if (BP_RESULT_OK == result) { + if (result == BP_RESULT_OK) { enc110->base.features.flags.bits.IS_HBR2_CAPABLE = bp_cap_info.DP_HBR2_EN; enc110->base.features.flags.bits.IS_HBR3_CAPABLE = bp_cap_info.DP_HBR3_EN; enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; - } else { + } else if (result != BP_RESULT_NORECORD) { DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", __func__, result); @@ -1798,13 +1798,13 @@ void dce60_link_encoder_construct( enc110->base.id, &bp_cap_info); /* Override features with DCE-specific values */ - if (BP_RESULT_OK == result) { + if (result == BP_RESULT_OK) { enc110->base.features.flags.bits.IS_HBR2_CAPABLE = bp_cap_info.DP_HBR2_EN; enc110->base.features.flags.bits.IS_HBR3_CAPABLE = bp_cap_info.DP_HBR3_EN; enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; - } else { + } else if (result != BP_RESULT_NORECORD) { DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", __func__, result); From 3575f2bdb328ba4cc2bf3ad586f237555a524061 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 31 Jul 2025 11:43:51 +0200 Subject: [PATCH 1737/2653] drm/amd/display: Don't print errors for nonexistent connectors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When getting the number of connectors, the VBIOS reports the number of valid indices, but it doesn't say which indices are valid, and not every valid index has an actual connector. If we don't find a connector on an index, that is not an error. Considering these are not actual errors, don't litter the logs. Fixes: 60df5628144b ("drm/amd/display: handle invalid connector indices") Signed-off-by: Timur Kristóf Acked-by: Alex Deucher Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 5 +---- drivers/gpu/drm/amd/display/dc/core/dc.c | 15 ++++++++++++++- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index 67f08495b7e6e..154fd2c18e884 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -174,11 +174,8 @@ static struct graphics_object_id bios_parser_get_connector_id( return object_id; } - if (tbl->ucNumberOfObjects <= i) { - dm_error("Can't find connector id %d in connector table of size %d.\n", - i, tbl->ucNumberOfObjects); + if (tbl->ucNumberOfObjects <= i) return object_id; - } id = le16_to_cpu(tbl->asObjects[i].usObjectID); object_id = object_id_from_bios_object_id(id); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 59e18acbac8a2..39e5a2136ee78 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -217,11 +217,24 @@ static bool create_links( connectors_num, num_virtual_links); - // condition loop on link_count to allow skipping invalid indices + /* When getting the number of connectors, the VBIOS reports the number of valid indices, + * but it doesn't say which indices are valid, and not every index has an actual connector. + * So, if we don't find a connector on an index, that is not an error. + * + * - There is no guarantee that the first N indices will be valid + * - VBIOS may report a higher amount of valid indices than there are actual connectors + * - Some VBIOS have valid configurations for more connectors than there actually are + * on the card. This may be because the manufacturer used the same VBIOS for different + * variants of the same card. + */ for (i = 0; dc->link_count < connectors_num && i < MAX_LINKS; i++) { + struct graphics_object_id connector_id = bios->funcs->get_connector_id(bios, i); struct link_init_data link_init_params = {0}; struct dc_link *link; + if (connector_id.id == CONNECTOR_ID_UNKNOWN) + continue; + DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count); link_init_params.ctx = dc->ctx; From 485cd41b3c0f9af48afb60a561501ee644663d9d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 31 Jul 2025 11:43:52 +0200 Subject: [PATCH 1738/2653] drm/amd/display: Fix fractional fb divider in set_pixel_clock_v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For later VBIOS versions, the fractional feedback divider is calculated as the remainder of dividing the feedback divider by a factor, which is set to 1000000. For reference, see: - calculate_fb_and_fractional_fb_divider - calc_pll_max_vco_construct However, in case of old VBIOS versions that have set_pixel_clock_v3, they only have 1 byte available for the fractional feedback divider, and it's expected to be set to the remainder from dividing the feedback divider by 10. For reference see the legacy display code: - amdgpu_pll_compute - amdgpu_atombios_crtc_program_pll This commit fixes set_pixel_clock_v3 by dividing the fractional feedback divider passed to the function by 100000. Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by: Timur Kristóf Acked-by: Alex Deucher Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/bios/command_table.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c index 2bcae0643e61d..58e88778da7ff 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c @@ -993,7 +993,7 @@ static enum bp_result set_pixel_clock_v3( allocation.sPCLKInput.usFbDiv = cpu_to_le16((uint16_t)bp_params->feedback_divider); allocation.sPCLKInput.ucFracFbDiv = - (uint8_t)bp_params->fractional_feedback_divider; + (uint8_t)(bp_params->fractional_feedback_divider / 100000); allocation.sPCLKInput.ucPostDiv = (uint8_t)bp_params->pixel_clock_post_divider; From f56b466ef6b9d6eef39ad885d43e240886850854 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Sat, 16 Aug 2025 10:27:27 -0600 Subject: [PATCH 1739/2653] drm/amdgpu/vcn: Remove unnecessary check The function amdgpu_vcn_sysfs_reset_mask_init already returns 0, which makes the check of the result unnecessary in the vcn_v4_0_3_sw_init(). Just return the amdgpu_vcn_sysfs_reset_mask_init directly. Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index a63a1e3435ab6..7b93a275ec4f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -242,11 +242,7 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) if (r) return r; - r = amdgpu_vcn_sysfs_reset_mask_init(adev); - if (r) - return r; - - return 0; + return amdgpu_vcn_sysfs_reset_mask_init(adev); } /** From f3e0c542eaf90d351ee392285fa2323d74d6e8cb Mon Sep 17 00:00:00 2001 From: Qianfeng Rong Date: Sat, 16 Aug 2025 22:37:51 +0800 Subject: [PATCH 1740/2653] drm/radeon: Use vmalloc_array and vcalloc to simplify code Use vcalloc() and vmalloc_array() to simplify the functions radeon_gart_init(). vmalloc_array() is also optimized better, resulting in less instructions being used. Signed-off-by: Qianfeng Rong Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_gart.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c index 4bb242437ff60..acd89a20f2724 100644 --- a/drivers/gpu/drm/radeon/radeon_gart.c +++ b/drivers/gpu/drm/radeon/radeon_gart.c @@ -346,14 +346,14 @@ int radeon_gart_init(struct radeon_device *rdev) DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages); /* Allocate pages table */ - rdev->gart.pages = vzalloc(array_size(sizeof(void *), - rdev->gart.num_cpu_pages)); + rdev->gart.pages = vcalloc(rdev->gart.num_cpu_pages, + sizeof(void *)); if (rdev->gart.pages == NULL) { radeon_gart_fini(rdev); return -ENOMEM; } - rdev->gart.pages_entry = vmalloc(array_size(sizeof(uint64_t), - rdev->gart.num_gpu_pages)); + rdev->gart.pages_entry = vmalloc_array(rdev->gart.num_gpu_pages, + sizeof(uint64_t)); if (rdev->gart.pages_entry == NULL) { radeon_gart_fini(rdev); return -ENOMEM; From c03175861711c0b7349f4ec92edd71bf78a94f07 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Sat, 2 Aug 2025 17:51:53 +0200 Subject: [PATCH 1741/2653] drm/amd/display: Fix DP audio DTO1 clock source on DCE 6. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On DCE 6, DP audio was not working. However, it worked when an HDMI monitor was also plugged in. Looking at dce_aud_wall_dto_setup it seems that the main difference is that we use DTO1 when only DP is plugged in. When programming DTO1, it uses audio_dto_source_clock_in_khz which is set from get_dp_ref_freq_khz The dce60_get_dp_ref_freq_khz implementation looks incorrect, because DENTIST_DISPCLK_CNTL seems to be always zero on DCE 6, so it isn't usable. I compared dce60_get_dp_ref_freq_khz to the legacy display code, specifically dce_v6_0_audio_set_dto, and it turns out that in case of DCE 6, it needs to use the display clock. With that, DP audio started working on Pitcairn, Oland and Cape Verde. However, it still didn't work on Tahiti. Despite having the same DCE version, Tahiti seems to have a different audio device. After some trial and error I realized that it works with the default display clock as reported by the VBIOS, not the current display clock. The patch was tested on all four SI GPUs: * Pitcairn (DCE 6.0) * Oland (DCE 6.4) * Cape Verde (DCE 6.0) * Tahiti (DCE 6.0 but different) The testing was done on Samsung Odyssey G7 LS28BG700EPXEN on each of the above GPUs, at the following settings: * 4K 60 Hz * 1080p 60 Hz * 1080p 144 Hz Acked-by: Alex Deucher Reviewed-by: Rodrigo Siqueira Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- .../display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 21 ++++++------------- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c index 7044b437fe9d9..a39641a0ff09e 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c @@ -83,22 +83,13 @@ static const struct state_dependent_clocks dce60_max_clks_by_state[] = { static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) { struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); - int dprefclk_wdivider; - int dp_ref_clk_khz; - int target_div; + struct dc_context *ctx = clk_mgr_base->ctx; + int dp_ref_clk_khz = 0; - /* DCE6 has no DPREFCLK_CNTL to read DP Reference Clock source */ - - /* Read the mmDENTIST_DISPCLK_CNTL to get the currently - * programmed DID DENTIST_DPREFCLK_WDIVIDER*/ - REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider); - - /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/ - target_div = dentist_get_divider_from_did(dprefclk_wdivider); - - /* Calculate the current DFS clock, in kHz.*/ - dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR - * clk_mgr->base.dentist_vco_freq_khz) / target_div; + if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev)) + dp_ref_clk_khz = ctx->dc_bios->fw_info.default_display_engine_pll_frequency; + else + dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz; return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz); } From 65d1d1b0f1418509432a520f4f3fcd3da2c334bf Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Tue, 19 Aug 2025 16:21:02 +0800 Subject: [PATCH 1742/2653] drm/amdgpu: Allocate psp fw private buffer in vram It's not necessarily to allocate psp firmware private buffer in different memory domain in sriov and bare metal environment Signed-off-by: Hawking Zhang Reviewed-by: Le Ma --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index df4458f6f0061..e7a9c6f19891e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -506,8 +506,7 @@ static int psp_sw_init(struct amdgpu_ip_block *ip_block) } ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, - (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? - AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, + AMDGPU_GEM_DOMAIN_VRAM, &psp->fw_pri_bo, &psp->fw_pri_mc_addr, &psp->fw_pri_buf); From bffcde2bed325eed2c95dbf5c2506d073bebd5e2 Mon Sep 17 00:00:00 2001 From: Liao Yuanhong Date: Tue, 19 Aug 2025 16:25:21 +0800 Subject: [PATCH 1743/2653] drm/amdgpu/fence: Remove redundant 0 value initialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The amdgpu_fence struct is already zeroed by kzalloc(). It's redundant to initialize am_fence->context to 0. Reviewed-by: Christian König Signed-off-by: Liao Yuanhong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index d9516d2a1c66a..bb17c1a0a4438 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -120,7 +120,6 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, am_fence = kzalloc(sizeof(*am_fence), GFP_KERNEL); if (!am_fence) return -ENOMEM; - am_fence->context = 0; } else { am_fence = af; } From 64857f311eab9e7f3764f648efd030555d8c08d2 Mon Sep 17 00:00:00 2001 From: Liao Yuanhong Date: Tue, 19 Aug 2025 22:24:50 +0800 Subject: [PATCH 1744/2653] drm/amd/display: Remove redundant header files The header file "dc_stream.h" is already included on line 1507. Remove the redundant include. This is because the header file was initially included towards the latter part of the code. Subsequent commits had to include the header file again earlier in the code. In my opinion, this doesn't count as a fix; it just requires removing the redundant header inclusion. Signed-off-by: Liao Yuanhong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 927fbdc4cf9ef..0cfd5bcc1fa9b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1866,8 +1866,6 @@ void dc_3dlut_func_retain(struct dc_3dlut *lut); void dc_post_update_surfaces_to_stream( struct dc *dc); -#include "dc_stream.h" - /** * struct dc_validation_set - Struct to store surface/stream associations for validation */ From 3abdbf6e423765ef696ad845cc2609038159c7d1 Mon Sep 17 00:00:00 2001 From: Ce Sun Date: Tue, 19 Aug 2025 14:47:05 +0800 Subject: [PATCH 1745/2653] drm/amdgpu: Add a mutex lock to protect poison injection When poison is triggered multiple times, competition will occur. Add a mutex lock to protect poison injection Signed-off-by: Ce Sun Reviewed-by: Yang Wang Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 4ea1e3287a739..e8e856dfb78b7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3532,6 +3532,7 @@ static int amdgpu_ras_page_retirement_thread(void *param) if (kthread_should_stop()) break; + mutex_lock(&con->poison_lock); gpu_reset = 0; do { @@ -3589,6 +3590,7 @@ static int amdgpu_ras_page_retirement_thread(void *param) /* Wake up work to save bad pages to eeprom */ schedule_delayed_work(&con->page_retirement_dwork, 0); } + mutex_unlock(&con->poison_lock); #endif } @@ -3670,6 +3672,7 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info) } mutex_init(&con->recovery_lock); + mutex_init(&con->poison_lock); INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); atomic_set(&con->in_recovery, 0); atomic_set(&con->rma_in_recovery, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index ff63020f9c6c9..2a70782b07bfd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -587,6 +587,8 @@ struct amdgpu_ras { struct list_head critical_region_head; struct mutex critical_region_lock; + /* Protect poison injection */ + struct mutex poison_lock; }; struct ras_fs_data { From bb1797f664cffe70f894074d552d6c29c94d8b76 Mon Sep 17 00:00:00 2001 From: Ce Sun Date: Wed, 20 Aug 2025 17:18:57 +0800 Subject: [PATCH 1746/2653] drm/amdgpu: Correct the loss of aca bank reg info By polling, poll ACA bank count to ensure that valid ACA bank reg info can be obtained v2: add corresponding delay before send msg to SMU to query mca bank info (Stanley) v3: the loop cannot exit. (Thomas) v4: remove amdgpu_aca_clear_bank_count. (Kevin) v5: continuously inject ce. If a creation interruption occurs at this time, bank reg info will be lost. (Thomas) v5: each cycle is delayed by 100ms. (Tao) Signed-off-by: Ce Sun Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 50 +++++++++++-------------- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 5 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 1 + drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 5 ++- 4 files changed, 29 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index e8e856dfb78b7..53b8e3fc41683 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -122,7 +122,7 @@ const char *get_ras_block_str(struct ras_common_if *ras_block) /* typical ECC bad page rate is 1 bad page per 100MB VRAM */ #define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL) -#define MAX_UMC_POISON_POLLING_TIME_ASYNC 300 //ms +#define MAX_UMC_POISON_POLLING_TIME_ASYNC 10 #define AMDGPU_RAS_RETIRE_PAGE_INTERVAL 100 //ms @@ -3334,7 +3334,7 @@ static void amdgpu_ras_ecc_log_init(struct ras_ecc_log_info *ecc_log) INIT_RADIX_TREE(&ecc_log->de_page_tree, GFP_KERNEL); ecc_log->de_queried_count = 0; - ecc_log->prev_de_queried_count = 0; + ecc_log->consumption_q_count = 0; } static void amdgpu_ras_ecc_log_fini(struct ras_ecc_log_info *ecc_log) @@ -3354,7 +3354,7 @@ static void amdgpu_ras_ecc_log_fini(struct ras_ecc_log_info *ecc_log) mutex_destroy(&ecc_log->lock); ecc_log->de_queried_count = 0; - ecc_log->prev_de_queried_count = 0; + ecc_log->consumption_q_count = 0; } #endif @@ -3405,47 +3405,34 @@ static int amdgpu_ras_poison_creation_handler(struct amdgpu_device *adev, int ret = 0; struct ras_ecc_log_info *ecc_log; struct ras_query_if info; - uint32_t timeout = 0; + u32 timeout = MAX_UMC_POISON_POLLING_TIME_ASYNC; struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); - uint64_t de_queried_count; - uint32_t new_detect_count, total_detect_count; - uint32_t need_query_count = poison_creation_count; + u64 de_queried_count; + u64 consumption_q_count; enum ras_event_type type = RAS_EVENT_TYPE_POISON_CREATION; memset(&info, 0, sizeof(info)); info.head.block = AMDGPU_RAS_BLOCK__UMC; ecc_log = &ras->umc_ecc_log; - total_detect_count = 0; + ecc_log->de_queried_count = 0; + ecc_log->consumption_q_count = 0; + do { ret = amdgpu_ras_query_error_status_with_event(adev, &info, type); if (ret) return ret; de_queried_count = ecc_log->de_queried_count; - if (de_queried_count > ecc_log->prev_de_queried_count) { - new_detect_count = de_queried_count - ecc_log->prev_de_queried_count; - ecc_log->prev_de_queried_count = de_queried_count; - timeout = 0; - } else { - new_detect_count = 0; - } + consumption_q_count = ecc_log->consumption_q_count; - if (new_detect_count) { - total_detect_count += new_detect_count; - } else { - if (!timeout && need_query_count) - timeout = MAX_UMC_POISON_POLLING_TIME_ASYNC; + if (de_queried_count && consumption_q_count) + break; - if (timeout) { - if (!--timeout) - break; - msleep(1); - } - } - } while (total_detect_count < need_query_count); + msleep(100); + } while (--timeout); - if (total_detect_count) + if (de_queried_count) schedule_delayed_work(&ras->page_retirement_dwork, 0); if (amdgpu_ras_is_rma(adev) && atomic_cmpxchg(&ras->rma_in_recovery, 0, 1) == 0) @@ -3545,7 +3532,8 @@ static int amdgpu_ras_page_retirement_thread(void *param) atomic_sub(poison_creation_count, &con->poison_creation_count); atomic_sub(poison_creation_count, &con->page_retirement_req_cnt); } - } while (atomic_read(&con->poison_creation_count)); + } while (atomic_read(&con->poison_creation_count) && + !atomic_read(&con->poison_consumption_count)); #ifdef HAVE_KFIFO_PUT_NON_POINTER if (ret != -EIO) { @@ -3563,6 +3551,7 @@ static int amdgpu_ras_page_retirement_thread(void *param) /* gpu mode-1 reset is ongoing or just completed ras mode-1 reset */ /* Clear poison creation request */ atomic_set(&con->poison_creation_count, 0); + atomic_set(&con->poison_consumption_count, 0); /* Clear poison fifo */ amdgpu_ras_clear_poison_fifo(adev); @@ -3587,6 +3576,8 @@ static int amdgpu_ras_page_retirement_thread(void *param) atomic_sub(msg_count, &con->page_retirement_req_cnt); } + atomic_set(&con->poison_consumption_count, 0); + /* Wake up work to save bad pages to eeprom */ schedule_delayed_work(&con->page_retirement_dwork, 0); } @@ -3693,6 +3684,7 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info) init_waitqueue_head(&con->page_retirement_wq); atomic_set(&con->page_retirement_req_cnt, 0); atomic_set(&con->poison_creation_count, 0); + atomic_set(&con->poison_consumption_count, 0); con->page_retirement_thread = kthread_run(amdgpu_ras_page_retirement_thread, adev, "umc_page_retirement"); if (IS_ERR(con->page_retirement_thread)) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index 2a70782b07bfd..6cf0dfd38be8b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -492,8 +492,8 @@ struct ras_ecc_err { struct ras_ecc_log_info { struct mutex lock; struct radix_tree_root de_page_tree; - uint64_t de_queried_count; - uint64_t prev_de_queried_count; + uint64_t de_queried_count; + uint64_t consumption_q_count; }; struct ras_critical_region { @@ -565,6 +565,7 @@ struct amdgpu_ras { struct mutex page_retirement_lock; atomic_t page_retirement_req_cnt; atomic_t poison_creation_count; + atomic_t poison_consumption_count; struct mutex page_rsv_lock; DECLARE_KFIFO(poison_fifo, struct ras_poison_msg, 128); struct ras_ecc_log_info umc_ecc_log; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c index bfc86f1e84e59..983a428eddd4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c @@ -254,6 +254,7 @@ int amdgpu_umc_pasid_poison_handler(struct amdgpu_device *adev, if (!ret) { #endif atomic_inc(&con->page_retirement_req_cnt); + atomic_inc(&con->poison_consumption_count); wake_up(&con->page_retirement_wq); #ifdef HAVE_KFIFO_PUT_NON_POINTER } diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c index e590cbdd8de96..8dc32787d6250 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c @@ -536,8 +536,11 @@ static int umc_v12_0_update_ecc_status(struct amdgpu_device *adev, hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID); mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType); - if ((hwid != MCA_UMC_HWID_V12_0) || (mcatype != MCA_UMC_MCATYPE_V12_0)) + /* The IP block decode of consumption is SMU */ + if (hwid != MCA_UMC_HWID_V12_0 || mcatype != MCA_UMC_MCATYPE_V12_0) { + con->umc_ecc_log.consumption_q_count++; return 0; + } if (!status) return 0; From 90610f3de6f6fc5009b23b03cc6f0065bc20344c Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Tue, 29 Jul 2025 18:08:24 +0530 Subject: [PATCH 1747/2653] drm/amd/display: Optimize amdgpu_dm_atomic_commit_tail() [WHY] The first two loops of for_each_oldnew_connector_in_state() both operate on an HDCP queue. If one isn't setup then each connector is iterated but skipped TWICE. This is wasteful for the majority of cases. [HOW] Combine the two HDCP related loops of for_each_oldnew_connector_in_state() and check for the HDCP workqueue before even running either of them. This should avoid running the functions in most cases, and if HDCP is setup only run once. Reviewed-by: Alex Hung Signed-off-by: Mario Limonciello Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 120 +++++++++--------- 1 file changed, 57 insertions(+), 63 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1d79da7af83dd..5c7baf8e2fbfd 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10446,71 +10446,40 @@ static void dm_set_writeback(struct amdgpu_display_manager *dm, drm_writeback_queue_job(wb_conn, new_con_state); } -/** - * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. - * @state: The atomic state to commit - * - * This will tell DC to commit the constructed DC state from atomic_check, - * programming the hardware. Any failures here implies a hardware failure, since - * atomic check should have filtered anything non-kosher. - */ -static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) +static void amdgpu_dm_update_hdcp(struct drm_atomic_state *state) { + struct drm_connector_state *old_con_state, *new_con_state; struct drm_device *dev = state->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_display_manager *dm = &adev->dm; - struct dm_atomic_state *dm_state; - struct dc_state *dc_state = NULL; - u32 i, j; - struct drm_crtc *crtc; - struct drm_crtc_state *old_crtc_state, *new_crtc_state; - unsigned long flags; - bool wait_for_vblank = true; struct drm_connector *connector; - struct drm_connector_state *old_con_state, *new_con_state; - struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; - int crtc_disable_count = 0; - - trace_amdgpu_dm_atomic_commit_tail_begin(state); - - drm_atomic_helper_update_legacy_modeset_state(dev, state); -#ifdef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES - drm_dp_mst_atomic_wait_for_dependencies(state); -#endif + struct amdgpu_device *adev = drm_to_adev(dev); + int i; - dm_state = dm_atomic_get_new_state(state); - if (dm_state && dm_state->context) { - dc_state = dm_state->context; - amdgpu_dm_commit_streams(state, dc_state); - } + if (!adev->dm.hdcp_workqueue) + return; for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); + struct drm_crtc_state *old_crtc_state, *new_crtc_state; + struct dm_crtc_state *dm_new_crtc_state; struct amdgpu_dm_connector *aconnector; - if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) + if (!connector || connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; aconnector = to_amdgpu_dm_connector(connector); - if (!adev->dm.hdcp_workqueue) - continue; - - pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i); - - if (!connector) - continue; + drm_dbg(dev, "[HDCP_DM] -------------- i : %x ----------\n", i); - pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", + drm_dbg(dev, "[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", connector->index, connector->status, connector->dpms); - pr_debug("[HDCP_DM] state protection old: %x new: %x\n", + drm_dbg(dev, "[HDCP_DM] state protection old: %x new: %x\n", old_con_state->content_protection, new_con_state->content_protection); if (aconnector->dc_sink) { if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { - pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n", + drm_dbg(dev, "[HDCP_DM] pipe_ctx dispname=%s\n", aconnector->dc_sink->edid_caps.display_name); } } @@ -10524,7 +10493,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) } if (old_crtc_state) - pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", + drm_dbg(dev, "old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", old_crtc_state->enable, old_crtc_state->active, old_crtc_state->mode_changed, @@ -10532,29 +10501,13 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) old_crtc_state->connectors_changed); if (new_crtc_state) - pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", + drm_dbg(dev, "NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", new_crtc_state->enable, new_crtc_state->active, new_crtc_state->mode_changed, new_crtc_state->active_changed, new_crtc_state->connectors_changed); - } - for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { - struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); - struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); - - if (!adev->dm.hdcp_workqueue) - continue; - - new_crtc_state = NULL; - old_crtc_state = NULL; - - if (acrtc) { - new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); - old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); - } dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); @@ -10600,7 +10553,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) enable_encryption = true; - drm_info(adev_to_drm(adev), "[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); + drm_info(dev, "[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); if (aconnector->dc_link) hdcp_update_display( @@ -10613,6 +10566,47 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) enable_encryption); } } +} + +/** + * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. + * @state: The atomic state to commit + * + * This will tell DC to commit the constructed DC state from atomic_check, + * programming the hardware. Any failures here implies a hardware failure, since + * atomic check should have filtered anything non-kosher. + */ +static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) +{ + struct drm_device *dev = state->dev; + struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_display_manager *dm = &adev->dm; + struct dm_atomic_state *dm_state; + struct dc_state *dc_state = NULL; + u32 i, j; + struct drm_crtc *crtc; + struct drm_crtc_state *old_crtc_state, *new_crtc_state; + unsigned long flags; + bool wait_for_vblank = true; + struct drm_connector *connector; + struct drm_connector_state *old_con_state, *new_con_state; + struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; + int crtc_disable_count = 0; + + trace_amdgpu_dm_atomic_commit_tail_begin(state); + + drm_atomic_helper_update_legacy_modeset_state(dev, state); +#ifdef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES + drm_dp_mst_atomic_wait_for_dependencies(state); +#endif + + dm_state = dm_atomic_get_new_state(state); + if (dm_state && dm_state->context) { + dc_state = dm_state->context; + amdgpu_dm_commit_streams(state, dc_state); + } + + amdgpu_dm_update_hdcp(state); /* Handle connector state changes */ for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { From e5abde1a3edca439bc007605cb8ffa69379963c1 Mon Sep 17 00:00:00 2001 From: Ce Sun Date: Thu, 7 Aug 2025 12:36:05 +0800 Subject: [PATCH 1748/2653] drm/amdgpu: Correct the counts of nr_banks and nr_errors Correct the counts of nr_banks and nr_errors Signed-off-by: Ce Sun Reviewed-by: Yang Wang Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c index d1e431818212d..9b31804491500 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c @@ -76,6 +76,7 @@ static void aca_banks_release(struct aca_banks *banks) list_for_each_entry_safe(node, tmp, &banks->list, node) { list_del(&node->node); kvfree(node); + banks->nr_banks--; } } @@ -238,6 +239,7 @@ static struct aca_bank_error *new_bank_error(struct aca_error *aerr, struct aca_ mutex_lock(&aerr->lock); list_add_tail(&bank_error->node, &aerr->list); + aerr->nr_errors++; mutex_unlock(&aerr->lock); return bank_error; From df25e3ebf2215b86d3a189a3d8cc20788e8246dd Mon Sep 17 00:00:00 2001 From: Ce Sun Date: Thu, 21 Aug 2025 10:59:23 +0800 Subject: [PATCH 1749/2653] drm/amdgpu: Add support for dpc to a series of products Add support for dpc to a series of products Signed-off-by: Ce Sun Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 367ce834a7498..b360a9f5f2d39 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -3294,7 +3294,7 @@ static inline bool smu_v13_0_6_is_link_reset_supported(struct smu_context *smu) struct amdgpu_device *adev = smu->adev; int var = (adev->pdev->device & 0xF); - if (var == 0x1) + if (var == 0x1 || var == 0x0) return true; return false; From 00118d606d2e3a440c4d16832f19ed060e0177c6 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 20 Aug 2025 14:55:41 +0800 Subject: [PATCH 1750/2653] drm/amdgpu: remove redundant AMDGPU_HAS_VRAM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit AMDGPU_HAS_VRAM is redundant with is_app_apu, as both refer to APUs with no carve-out. Since AMDGPU_HAS_VRAM only occurs once, remove AMDGPU_HAS_VRAM definition. The tmr allocation can be covered with AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM in both vram and non vram ASICs. Signed-off-by: Yifan Zhang Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ------ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 +--- 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index db83103e531be..312e51b528eb3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -963,12 +963,6 @@ enum amdgpu_enforce_isolation_mode { AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3, }; - -/* - * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. - */ -#define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) - struct amdgpu_device { struct device *dev; struct pci_dev *pdev; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index e7a9c6f19891e..cf763862da502 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -880,9 +880,7 @@ static int psp_tmr_init(struct psp_context *psp) pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT, - AMDGPU_HAS_VRAM(psp->adev) ? - AMDGPU_GEM_DOMAIN_VRAM : - AMDGPU_GEM_DOMAIN_GTT, + AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM, &psp->tmr_bo, &psp->tmr_mc_addr, pptr); } From 5545f31086123fe7250fef2f119937aa3e8eee69 Mon Sep 17 00:00:00 2001 From: Ce Sun Date: Thu, 21 Aug 2025 16:27:57 +0800 Subject: [PATCH 1751/2653] drm/amdgpu: Add support for dpc to the product Add support for dpc to the product Signed-off-by: Ce Sun Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index b360a9f5f2d39..f3e2b75c1f970 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -3294,7 +3294,7 @@ static inline bool smu_v13_0_6_is_link_reset_supported(struct smu_context *smu) struct amdgpu_device *adev = smu->adev; int var = (adev->pdev->device & 0xF); - if (var == 0x1 || var == 0x0) + if (var == 0x0 || var == 0x1 || var == 0x3) return true; return false; From f93adb86253b62d0bfeffb18cea98793d4912c80 Mon Sep 17 00:00:00 2001 From: Brahmajit Das Date: Thu, 21 Aug 2025 17:31:33 +0530 Subject: [PATCH 1752/2653] drm/amd/display: clean-up dead code in dml2_mall_phantom MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit pipe_idx in funtion dml2_svp_validate_static_schedulabilit, although set is never actually used. While building with GCC 16 this gives a warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml2_mall_phantom.c: In function ‘set_phantom_stream_timing’: drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml2_mall_phantom.c:657:25: warning: variable ‘pipe_idx’ set but not used [-Wunused-but-set-variable=] 657 | unsigned int i, pipe_idx; | ^~~~~~~~ Signed-off-by: Brahmajit Das Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c index a56e75cdf7123..c59f825cfae96 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c @@ -654,14 +654,14 @@ static void set_phantom_stream_timing(struct dml2_context *ctx, struct dc_state unsigned int svp_height, unsigned int svp_vstartup) { - unsigned int i, pipe_idx; + unsigned int i; double line_time, fp_and_sync_width_time; struct pipe_ctx *pipe; uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines; static const double cvt_rb_vblank_max = ((double) 460 / (1000 * 1000)); // Find DML pipe index (pipe_idx) using dc_pipe_idx - for (i = 0, pipe_idx = 0; i < ctx->config.dcn_pipe_count; i++) { + for (i = 0; i < ctx->config.dcn_pipe_count; i++) { pipe = &state->res_ctx.pipe_ctx[i]; if (!pipe->stream) @@ -669,8 +669,6 @@ static void set_phantom_stream_timing(struct dml2_context *ctx, struct dc_state if (i == dc_pipe_idx) break; - - pipe_idx++; } // Calculate lines required for pstate allow width and FW processing delays From c24fae0696e3d8f35d2d0affda7bf9605df95d47 Mon Sep 17 00:00:00 2001 From: Rakuram Eswaran Date: Thu, 21 Aug 2025 08:29:55 +0530 Subject: [PATCH 1753/2653] docs: gpu: amdgpu: Fix spelling in amdgpu documentation Fixed following typos reported by Codespell 1. propogated ==> propagated aperatures ==> apertures In Documentation/gpu/amdgpu/debugfs.rst 2. parition ==> partition In Documentation/gpu/amdgpu/process-isolation.rst 3. conections ==> connections In Documentation/gpu/amdgpu/display/programming-model-dcn.rst In addition to above, Fixed wrong bit-partition naming in gpu/amdgpu/process-isolation.rst from "fourth" partition to "third" partition. Reviewed-by: Randy Dunlap Suggested-by: Randy Dunlap Suggested-by: Alexander Deucher Signed-off-by: Rakuram Eswaran Signed-off-by: Alex Deucher --- Documentation/gpu/amdgpu/debugfs.rst | 4 ++-- Documentation/gpu/amdgpu/display/programming-model-dcn.rst | 2 +- Documentation/gpu/amdgpu/process-isolation.rst | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/gpu/amdgpu/debugfs.rst b/Documentation/gpu/amdgpu/debugfs.rst index 5150d0a956581..151d8bfc79e24 100644 --- a/Documentation/gpu/amdgpu/debugfs.rst +++ b/Documentation/gpu/amdgpu/debugfs.rst @@ -94,7 +94,7 @@ amdgpu_error_ ------------------- Provides an interface to set an error code on the dma fences associated with -ring . The error code specified is propogated to all fences associated +ring . The error code specified is propagated to all fences associated with the ring. Use this to inject a fence error into a ring. amdgpu_pm_info @@ -165,7 +165,7 @@ GTT memory. amdgpu_regs_* ------------- -Provides direct access to various register aperatures on the GPU. Used +Provides direct access to various register apertures on the GPU. Used by tools like UMR to access GPU registers. amdgpu_regs2 diff --git a/Documentation/gpu/amdgpu/display/programming-model-dcn.rst b/Documentation/gpu/amdgpu/display/programming-model-dcn.rst index c1b48d49fb0ba..bc7de97a746f4 100644 --- a/Documentation/gpu/amdgpu/display/programming-model-dcn.rst +++ b/Documentation/gpu/amdgpu/display/programming-model-dcn.rst @@ -100,7 +100,7 @@ represents the connected display. For historical reasons, we used the name `dc_link`, which gives the wrong impression that this abstraction only deals with physical connections that the developer can easily manipulate. However, this also covers - conections like eDP or cases where the output is connected to other devices. + connections like eDP or cases where the output is connected to other devices. There are two structs that are not represented in the diagram since they were elaborated in the DCN overview page (check the DCN block diagram :ref:`Display diff --git a/Documentation/gpu/amdgpu/process-isolation.rst b/Documentation/gpu/amdgpu/process-isolation.rst index 6b6d70e357a75..25b06ffefc33a 100644 --- a/Documentation/gpu/amdgpu/process-isolation.rst +++ b/Documentation/gpu/amdgpu/process-isolation.rst @@ -26,7 +26,7 @@ Example of enabling enforce isolation on a GPU with multiple partitions: $ cat /sys/class/drm/card0/device/enforce_isolation 1 0 1 0 -The output indicates that enforce isolation is enabled on zeroth and second parition and disabled on first and fourth parition. +The output indicates that enforce isolation is enabled on zeroth and second partition and disabled on first and third partition. For devices with a single partition or those that do not support partitions, there will be only one element: From fc53bd4e6ccb1b8daa127f82bd9a4ba4b06b626b Mon Sep 17 00:00:00 2001 From: Sunday Clement Date: Fri, 30 May 2025 10:58:08 -0400 Subject: [PATCH 1754/2653] drm/amdkfd: Allow device error to be logged The addition of a WARN_ON() check in order to return early in the kq_initialize function retroactively causes the default case in the following switch statement to never be executed, preventing dev_err from logging device errors in the kernel. Both logs are now checked in the default case. Signed-off-by: Sunday Clement Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c index 2b0a830f5b294..fb3129883a4ca 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c @@ -46,11 +46,7 @@ static bool kq_initialize(struct kernel_queue *kq, struct kfd_node *dev, int retval; union PM4_MES_TYPE_3_HEADER nop; - if (WARN_ON(type != KFD_QUEUE_TYPE_DIQ && type != KFD_QUEUE_TYPE_HIQ)) - return false; - - pr_debug("Initializing queue type %d size %d\n", KFD_QUEUE_TYPE_HIQ, - queue_size); + pr_debug("Initializing queue type %d size %d\n", type, queue_size); memset(&prop, 0, sizeof(prop)); memset(&nop, 0, sizeof(nop)); @@ -69,6 +65,7 @@ static bool kq_initialize(struct kernel_queue *kq, struct kfd_node *dev, kq->mqd_mgr = dev->dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]; break; default: + WARN(1, "Invalid queue type %d\n", type); dev_err(dev->adev->dev, "Invalid queue type %d\n", type); return false; } From 42f5f24d36a7976f2b2406338f560f903f0189ff Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Mon, 18 Aug 2025 14:22:53 -0400 Subject: [PATCH 1755/2653] drm/amdkfd: fix vram allocation failure for a special case When it only allocates vram without va, which is 0, and a SVM range allocated stays in this range, the vram allocation returns failure. It should be skipped for this case from SVM usage check. Signed-off-by: Eric Huang Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index a0a846ff8ce43..97bb679fe9638 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1078,7 +1078,12 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, svm_range_list_lock_and_flush_work(&p->svms, current->mm); mutex_lock(&p->svms.lock); mmap_write_unlock(current->mm); - if (interval_tree_iter_first(&p->svms.objects, + + /* Skip a special case that allocates VRAM without VA, + * VA will be invalid of 0. + */ + if (!(!args->va_addr && (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM)) && + interval_tree_iter_first(&p->svms.objects, args->va_addr >> PAGE_SHIFT, (args->va_addr + args->size - 1) >> PAGE_SHIFT)) { pr_err("Address: 0x%llx already allocated by SVM\n", From 383fc6f95d36cac6f6930f56ee83f300caef617c Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Tue, 19 Aug 2025 09:46:04 +0800 Subject: [PATCH 1756/2653] drm/amd/pm: Update SMU v13.0.6 PPT caps initialization Update the conditions for setting the SMU vcn reset caps in the SMU v13.0.6 PPT initialization function. Specifically: - Add support for VCN reset capability for firmware versions 0x00558200 and above when the program version is 0. - Add support for VCN reset capability for firmware versions 0x05551800 and above when the program version is 5. v2: correct the smu mp1 version for program 5 (Lijo) Suggested-by: Lijo Lazar Signed-off-by: Jesse Zhang Acked-by: Alex Deucher Reviewed-by: Yang Wang --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index f3e2b75c1f970..d59e406748913 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -320,6 +320,8 @@ static void smu_v13_0_14_init_caps(struct smu_context *smu) smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS)); if (fw_ver >= 0x5551200) smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET)); + if (fw_ver >= 0x5551800) + smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET)); if (fw_ver >= 0x5551600) { smu_v13_0_6_cap_set(smu, SMU_CAP(STATIC_METRICS)); smu_v13_0_6_cap_set(smu, SMU_CAP(BOARD_VOLTAGE)); @@ -445,7 +447,8 @@ static void smu_v13_0_6_init_caps(struct smu_context *smu) ((pgm == 4) && (fw_ver >= 0x4557000))) smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET)); - if ((pgm == 4) && (fw_ver >= 0x04557100)) + if (((pgm == 0) && (fw_ver >= 0x00558200)) || + ((pgm == 4) && (fw_ver >= 0x04557100))) smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET)); } From 45173ba422df55513a0959259e5a02b99d48cd88 Mon Sep 17 00:00:00 2001 From: Amber Lin Date: Fri, 15 Aug 2025 14:04:15 -0400 Subject: [PATCH 1757/2653] drm/amdkfd: Tie UNMAP_LATENCY to queue_preemption When KFD asks CP to preempt queues, other than preempt CP queues, CP also requests SDMA to preempt SDMA queues with UNMAP_LATENCY timeout. Currently queue_preemption_timeout_ms is 9000 ms by default but can be configured via module parameter. KFD_UNMAP_LATENCY_MS is hard coded as 4000 ms though. This patch ties KFD_UNMAP_LATENCY_MS to queue_preemption_timeout_ms so in a slow system such as emulator, both CP and SDMA slowness are taken into account. Signed-off-by: Amber Lin Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 9ef202e63d943..8a291d0d7312f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -116,7 +116,14 @@ #define KFD_KERNEL_QUEUE_SIZE 2048 -#define KFD_UNMAP_LATENCY_MS (4000) +/* KFD_UNMAP_LATENCY_MS is the timeout CP waiting for SDMA preemption. One XCC + * can be associated to 2 SDMA engines. queue_preemption_timeout_ms is the time + * driver waiting for CP returning the UNMAP_QUEUE fence. Thus the math is + * queue_preemption_timeout_ms = sdma_preemption_time * 2 + cp workload + * The format here makes CP workload 10% of total timeout + */ +#define KFD_UNMAP_LATENCY_MS \ + ((queue_preemption_timeout_ms - queue_preemption_timeout_ms / 10) >> 1) #define KFD_MAX_SDMA_QUEUES 128 From 02814c8cd7b8a863cab8358b8ecb1d1bc0f6f722 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 13 Aug 2025 14:53:50 -0400 Subject: [PATCH 1758/2653] drm/amdgpu/vcn: drop extra cancel_delayed_work_sync() We already call this in the hw_fini() methods for all VCN instances, so no need to call it again in amdgpu_vcn_suspend(). Tested-by: David (Ming Qiang) Wu Reviewed-by: Leo Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 9a76e11d1c184..fd8ebf4b5a824 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -357,8 +357,6 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev, int i) if (adev->vcn.harvest_config & (1 << i)) return 0; - cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work); - /* err_event_athub and dpc recovery will corrupt VCPU buffer, so we need to * restore fw data and clear buffer in amdgpu_vcn_resume() */ if (in_ras_intr || adev->pcie_reset_ctx.in_link_reset) From f230eefea7a819551c53597d3946014395743ef4 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 18 Aug 2025 15:19:47 -0400 Subject: [PATCH 1759/2653] drm/amdgpu/vpe: add ring reset support Implement ring reset for VPE. Similar to VCN and JPEG, just powergate the the IP to reset it. v2: Properly set per queue reset flag Reviewed-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c index 121ee17b522bd..86573c8d9b91e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c @@ -379,9 +379,10 @@ static int vpe_sw_init(struct amdgpu_ip_block *ip_block) if (ret) goto out; - /* TODO: Add queue reset mask when FW fully supports it */ adev->vpe.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->vpe.ring); + if (!amdgpu_sriov_vf(adev)) + adev->vpe.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; ret = amdgpu_vpe_sysfs_reset_mask_init(adev); if (ret) goto out; @@ -874,6 +875,27 @@ static void vpe_ring_end_use(struct amdgpu_ring *ring) schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT); } +static int vpe_ring_reset(struct amdgpu_ring *ring, + unsigned int vmid, + struct amdgpu_fence *timedout_fence) +{ + struct amdgpu_device *adev = ring->adev; + int r; + + amdgpu_ring_reset_helper_begin(ring, timedout_fence); + + r = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, + AMD_PG_STATE_GATE); + if (r) + return r; + r = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, + AMD_PG_STATE_UNGATE); + if (r) + return r; + + return amdgpu_ring_reset_helper_end(ring, timedout_fence); +} + static ssize_t amdgpu_get_vpe_reset_mask(struct device *dev, struct device_attribute *attr, char *buf) @@ -942,6 +964,7 @@ static const struct amdgpu_ring_funcs vpe_ring_funcs = { .preempt_ib = vpe_ring_preempt_ib, .begin_use = vpe_ring_begin_use, .end_use = vpe_ring_end_use, + .reset = vpe_ring_reset, }; static void vpe_set_ring_funcs(struct amdgpu_device *adev) From 8e8175fc1970b956c883d4f9be7ee9c36deb6bb6 Mon Sep 17 00:00:00 2001 From: Karthi Kandasamy Date: Mon, 7 Jul 2025 13:28:12 +0200 Subject: [PATCH 1760/2653] drm/amd/display: Add control flags to force PSR / replay To change PSR/Replay behavior based on OS preferences, add some config options. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Karthi Kandasamy Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc_types.h | 4 ++++ drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 1 + .../amd/display/dc/link/protocols/link_edp_panel_control.c | 4 ++++ 4 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 2e2dea21b3321..619834a328a37 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -628,6 +628,7 @@ struct psr_config { unsigned int line_time_in_us; uint8_t rate_control_caps; uint16_t dsc_slice_height; + bool os_request_force_ffu; }; union dmcu_psr_level { @@ -740,6 +741,7 @@ struct psr_context { unsigned int line_time_in_us; uint8_t rate_control_caps; uint16_t dsc_slice_height; + bool os_request_force_ffu; }; struct colorspace_transform { @@ -1151,6 +1153,8 @@ struct replay_config { bool replay_video_conferencing_optimization_enabled; /* Replay alpm mode */ enum dc_alpm_mode alpm_mode; + /* Replay full screen only */ + bool os_request_force_ffu; }; /* Replay feature flags*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index 4482609dce2d3..d672231495ef5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -390,7 +390,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, sizeof(DP_SINK_DEVICE_STR_ID_1))) link->psr_settings.force_ffu_mode = 1; - copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode; + copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode || psr_context->os_request_force_ffu; if (((link->dpcd_caps.fec_cap.bits.FEC_CAPABLE && !link->dc->debug.disable_fec) && diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 938737a828331..b3f486a4d7819 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -683,6 +683,7 @@ struct replay_context { /* Controller Id used for Dig Fe source select */ enum controller_id controllerId; unsigned int line_time_in_ns; + bool os_request_force_ffu; }; enum dc_replay_enable { diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 2c3e2945124a9..8b7b87b21c2e9 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -870,6 +870,8 @@ bool edp_setup_psr(struct dc_link *link, psr_context->dsc_slice_height = psr_config->dsc_slice_height; + psr_context->os_request_force_ffu = psr_config->os_request_force_ffu; + if (psr) { link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr, link, psr_context, panel_inst); @@ -1029,6 +1031,8 @@ bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream replay_context.line_time_in_ns = lineTimeInNs; + replay_context.os_request_force_ffu = link->replay_settings.config.os_request_force_ffu; + link->replay_settings.replay_feature_enabled = replay->funcs->replay_copy_settings(replay, link, &replay_context, panel_inst); if (link->replay_settings.replay_feature_enabled) { From b4c84b5a94684a5e8e21b5c1d26bfd707e90a3ae Mon Sep 17 00:00:00 2001 From: Cruise Hung Date: Mon, 11 Aug 2025 21:03:13 +0800 Subject: [PATCH 1761/2653] drm/amd/display: Reserve instance index notified by DMUB [Why] Reserve instance index notified by DMUB. [How] Add new variable for instance index. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Cruise Hung Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc_stat.c | 2 +- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 2 ++ drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c | 8 ++++---- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stat.c b/drivers/gpu/drm/amd/display/dc/core/dc_stat.c index fe9f99f1bdf9f..f976ffd6d4669 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stat.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stat.c @@ -65,7 +65,7 @@ void dc_stat_get_dmub_notification(const struct dc *dc, struct dmub_notification notify->type == DMUB_NOTIFICATION_DPIA_NOTIFICATION || notify->type == DMUB_NOTIFICATION_SET_CONFIG_REPLY) { notify->link_index = - get_link_index_from_dpia_port_index(dc, notify->link_index); + get_link_index_from_dpia_port_index(dc, notify->instance); } } diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index 87b761ac3135d..7abf7d0fd02b1 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -598,6 +598,8 @@ struct dmub_notification { enum dmub_notification_type type; uint8_t link_index; uint8_t result; + /* notify instance from DMUB */ + uint8_t instance; bool pending_notification; union { struct aux_reply_data aux_reply; diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c index 567c5b1aeb7ae..e7a58b140388b 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c @@ -71,7 +71,7 @@ enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub, switch (cmd.cmd_common.header.type) { case DMUB_OUT_CMD__DP_AUX_REPLY: notify->type = DMUB_NOTIFICATION_AUX_REPLY; - notify->link_index = cmd.dp_aux_reply.control.instance; + notify->instance = cmd.dp_aux_reply.control.instance; notify->result = cmd.dp_aux_reply.control.result; dmub_memcpy((void *)¬ify->aux_reply, (void *)&cmd.dp_aux_reply.reply_data, sizeof(struct aux_reply_data)); @@ -84,17 +84,17 @@ enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub, notify->type = DMUB_NOTIFICATION_HPD_IRQ; } - notify->link_index = cmd.dp_hpd_notify.hpd_data.instance; + notify->instance = cmd.dp_hpd_notify.hpd_data.instance; notify->result = AUX_RET_SUCCESS; break; case DMUB_OUT_CMD__SET_CONFIG_REPLY: notify->type = DMUB_NOTIFICATION_SET_CONFIG_REPLY; - notify->link_index = cmd.set_config_reply.set_config_reply_control.instance; + notify->instance = cmd.set_config_reply.set_config_reply_control.instance; notify->sc_status = cmd.set_config_reply.set_config_reply_control.status; break; case DMUB_OUT_CMD__DPIA_NOTIFICATION: notify->type = DMUB_NOTIFICATION_DPIA_NOTIFICATION; - notify->link_index = cmd.dpia_notification.payload.header.instance; + notify->instance = cmd.dpia_notification.payload.header.instance; break; case DMUB_OUT_CMD__HPD_SENSE_NOTIFY: notify->type = DMUB_NOTIFICATION_HPD_SENSE_NOTIFY; From 5d68e7f5d32f0c146c7c6bec4c1dc510fdb149a5 Mon Sep 17 00:00:00 2001 From: Ausef Yousof Date: Wed, 30 Jul 2025 16:08:10 -0400 Subject: [PATCH 1762/2653] drm/amd/display: track dpia support [why&how] initialize a flag to track if we previously supported dpia and write that to boot options Reviewed-by: Nicholas Kazlauskas Reviewed-by: Meenakshikumar Somasundaram Signed-off-by: Ausef Yousof Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 + drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 7 ++++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index 7abf7d0fd02b1..338fdc651f2cf 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -568,6 +568,7 @@ struct dmub_srv { bool sw_init; bool hw_init; + bool dpia_supported; uint64_t fb_base; uint64_t fb_offset; diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c index 2228d62adc7e4..834e5434ccb88 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c @@ -400,13 +400,14 @@ union dmub_fw_boot_options dmub_dcn35_get_fw_boot_option(struct dmub_srv *dmub) void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params) { union dmub_fw_boot_options boot_options = {0}; - union dmub_fw_boot_options cur_boot_options = {0}; - cur_boot_options = dmub_dcn35_get_fw_boot_option(dmub); + if (!dmub->dpia_supported) { + dmub->dpia_supported = dmub_dcn35_get_fw_boot_option(dmub).bits.enable_dpia; + } boot_options.bits.z10_disable = params->disable_z10; boot_options.bits.dpia_supported = params->dpia_supported; - boot_options.bits.enable_dpia = cur_boot_options.bits.enable_dpia && !params->disable_dpia; + boot_options.bits.enable_dpia = dmub->dpia_supported && !params->disable_dpia; boot_options.bits.usb4_cm_version = params->usb4_cm_version; boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported; boot_options.bits.power_optimization = params->power_optimization; From 9231cb6cca68aa77c4d9b02b031cf7863948611a Mon Sep 17 00:00:00 2001 From: Reza Amini Date: Tue, 12 Aug 2025 10:02:45 -0400 Subject: [PATCH 1763/2653] drm/amd/display: Decrease stack size in logging path [why] Reducing stack size can avoid stack over flow [how] Make local variables const and static so they are not on the stack. Reviewed-by: Dillon Varone Signed-off-by: Reza Amini Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 79c9bea78c478..d633033c98f29 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -328,7 +328,7 @@ static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx) } DTN_INFO("\n=======HUBP FL======\n"); - char pLabels[18][50] = { + static const char * const pLabels[] = { "inst", "Enabled ", "Done ", "adr_mode ", "width ", "mpc_width ", "tmz", "xbar_sel_R", "xbar_sel_G", "xbar_sel_B", "adr_hi ", "adr_low", "REFCYC", "Bias", "Scale", "Mode", @@ -552,7 +552,7 @@ static void dcn10_log_color_state(struct dc *dc, dc->caps.color.mpc.ogam_ram, dc->caps.color.mpc.ocsc); DTN_INFO("===== MPC RMCM 3DLUT =====\n"); - char pLabels[19][50] = { + static const char * const pLabels[] = { "MPCC", "SIZE", "MODE", "MODE_CUR", "RD_SEL", "30BIT_EN", "WR_EN_MASK", "RAM_SEL", "OUT_NORM_FACTOR", "FL_SEL", "OUT_OFFSET", "OUT_SCALE", "FL_DONE", "SOFT_UNDERFLOW", "HARD_UNDERFLOW", From 5089f0d204e3c77c165d30015c7178a18df89348 Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Thu, 7 Aug 2025 09:45:26 -0400 Subject: [PATCH 1764/2653] drm/amd/display: Support HW cursor 180 rot for any number of pipe splits [Why] For the HW cursor, its current position in the pipe_ctx->stream struct is not affected by the 180 rotation, i. e. the top left corner is still at 0,0. However, the DPP & HUBP set_cursor_position functions require rotated position. The current approach is hard-coded for ODM 2:1, thus it's failing for ODM 4:1, resulting in a double cursor. [How] Instead of calculating the new cursor position relatively to the viewports, we calculate it using a viewavable clip_rect of each plane. The clip_rects are first offset and scaled to the same space as the src_rect, i. e. Stream space -> Plane space. In case of a pipe split, which divides the plane into 2 or more viewports, the clip_rect is the union of all the viewports of the given plane. With the assumption that the viewports in HUBP's set_cursor_position are in the Plane space as well, it should produce a correct cursor position for any number of pipe splits. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Ivan Lipski Signed-off-by: Leo Li Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler --- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 73 +++++++------------ 1 file changed, 27 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index d633033c98f29..506c3bbbf221c 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -3663,6 +3663,8 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) int y_plane = pipe_ctx->plane_state->dst_rect.y; int x_pos = pos_cpy.x; int y_pos = pos_cpy.y; + int clip_x = pipe_ctx->plane_state->clip_rect.x; + int clip_width = pipe_ctx->plane_state->clip_rect.width; if ((pipe_ctx->top_pipe != NULL) || (pipe_ctx->bottom_pipe != NULL)) { if ((pipe_ctx->plane_state->src_rect.width != pipe_ctx->plane_res.scl_data.viewport.width) || @@ -3681,7 +3683,7 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) */ /** - * Translate cursor from stream space to plane space. + * Translate cursor and clip offset from stream space to plane space. * * If the cursor is scaled then we need to scale the position * to be in the approximately correct place. We can't do anything @@ -3698,6 +3700,10 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) pipe_ctx->plane_state->dst_rect.width; y_pos = (y_pos - y_plane) * pipe_ctx->plane_state->src_rect.height / pipe_ctx->plane_state->dst_rect.height; + clip_x = (clip_x - x_plane) * pipe_ctx->plane_state->src_rect.width / + pipe_ctx->plane_state->dst_rect.width; + clip_width = clip_width * pipe_ctx->plane_state->src_rect.width / + pipe_ctx->plane_state->dst_rect.width; } /** @@ -3744,30 +3750,18 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) if (param.rotation == ROTATION_ANGLE_0) { - int viewport_width = - pipe_ctx->plane_res.scl_data.viewport.width; - int viewport_x = - pipe_ctx->plane_res.scl_data.viewport.x; if (param.mirror) { - if (pipe_split_on || odm_combine_on) { - if (pos_cpy.x >= viewport_width + viewport_x) { - pos_cpy.x = 2 * viewport_width - - pos_cpy.x + 2 * viewport_x; - } else { - uint32_t temp_x = pos_cpy.x; - - pos_cpy.x = 2 * viewport_x - pos_cpy.x; - if (temp_x >= viewport_x + - (int)hubp->curs_attr.width || pos_cpy.x - <= (int)hubp->curs_attr.width + - pipe_ctx->plane_state->src_rect.x) { - pos_cpy.x = 2 * viewport_width - temp_x; - } - } - } else { - pos_cpy.x = viewport_width - pos_cpy.x + 2 * viewport_x; - } + /* + * The plane is split into multiple viewports. + * The combination of all viewports span the + * entirety of the clip rect. + * + * For no pipe_split, viewport_width is represents + * the full width of the clip_rect, so we can just + * mirror it. + */ + pos_cpy.x = clip_width - pos_cpy.x + 2 * clip_x; } } // Swap axis and mirror horizontally @@ -3837,30 +3831,17 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) } // Mirror horizontally and vertically else if (param.rotation == ROTATION_ANGLE_180) { - int viewport_width = - pipe_ctx->plane_res.scl_data.viewport.width; - int viewport_x = - pipe_ctx->plane_res.scl_data.viewport.x; - if (!param.mirror) { - if (pipe_split_on || odm_combine_on) { - if (pos_cpy.x >= viewport_width + viewport_x) { - pos_cpy.x = 2 * viewport_width - - pos_cpy.x + 2 * viewport_x; - } else { - uint32_t temp_x = pos_cpy.x; - - pos_cpy.x = 2 * viewport_x - pos_cpy.x; - if (temp_x >= viewport_x + - (int)hubp->curs_attr.width || pos_cpy.x - <= (int)hubp->curs_attr.width + - pipe_ctx->plane_state->src_rect.x) { - pos_cpy.x = temp_x + viewport_width; - } - } - } else { - pos_cpy.x = viewport_width - pos_cpy.x + 2 * viewport_x; - } + /* + * The plane is split into multiple viewports. + * The combination of all viewports span the + * entirety of the clip rect. + * + * For no pipe_split, viewport_width is represents + * the full width of the clip_rect, so we can just + * mirror it. + */ + pos_cpy.x = clip_width - pos_cpy.x + 2 * clip_x; } /** From b7bd3537b4aefa054b97741bd386e8b2544223a6 Mon Sep 17 00:00:00 2001 From: Clay King Date: Thu, 14 Aug 2025 16:58:15 -0400 Subject: [PATCH 1765/2653] drm/amd/display: Multiplication result converted to larger type Consolidating multiple CodeQL Fixes for alerts with rule id: cpp/integer-multiplication-cast-to-long Reviewed-by: Joshua Aberback Signed-off-by: Clay King Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c | 2 +- drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c | 2 +- drivers/gpu/drm/amd/display/dc/basics/vector.c | 6 +++--- drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +- .../amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c | 2 +- .../amd/display/dc/resource/dce112/dce112_resource.c | 12 ++++++------ .../amd/display/dc/resource/dce120/dce120_resource.c | 6 +++--- 7 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c index d897f8a30edee..4da5adab799ce 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c @@ -1136,7 +1136,7 @@ static void calculate_bandwidth( } } } - data->total_dmifmc_urgent_trips = bw_ceil2(bw_div(data->total_requests_for_adjusted_dmif_size, (bw_add(dceip->dmif_request_buffer_size, bw_int_to_fixed(vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel * data->number_of_dram_channels)))), bw_int_to_fixed(1)); + data->total_dmifmc_urgent_trips = bw_ceil2(bw_div(data->total_requests_for_adjusted_dmif_size, (bw_add(dceip->dmif_request_buffer_size, bw_int_to_fixed((uint64_t)vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel * data->number_of_dram_channels)))), bw_int_to_fixed(1)); data->total_dmifmc_urgent_latency = bw_mul(vbios->dmifmc_urgent_latency, data->total_dmifmc_urgent_trips); data->total_display_reads_required_data = bw_int_to_fixed(0); data->total_display_reads_required_dram_access_data = bw_int_to_fixed(0); diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c index 452206b5095eb..6073cadde76c7 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c +++ b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c @@ -284,7 +284,7 @@ struct fixed31_32 dc_fixpt_cos(struct fixed31_32 arg) dc_fixpt_mul( square, res), - n * (n - 1))); + (long long)n * (n - 1))); n -= 2; } while (n != 0); diff --git a/drivers/gpu/drm/amd/display/dc/basics/vector.c b/drivers/gpu/drm/amd/display/dc/basics/vector.c index 6d2924114a3e8..b413a672c2c0f 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/vector.c +++ b/drivers/gpu/drm/amd/display/dc/basics/vector.c @@ -170,7 +170,7 @@ bool dal_vector_remove_at_index( memmove( vector->container + (index * vector->struct_size), vector->container + ((index + 1) * vector->struct_size), - (vector->count - index - 1) * vector->struct_size); + (size_t)(vector->count - index - 1) * vector->struct_size); vector->count -= 1; return true; @@ -219,7 +219,7 @@ bool dal_vector_insert_at( memmove( insert_address + vector->struct_size, insert_address, - vector->struct_size * (vector->count - position)); + (size_t)vector->struct_size * (vector->count - position)); memmove( insert_address, @@ -271,7 +271,7 @@ struct vector *dal_vector_clone( /* copy vector's data */ memmove(vec_cloned->container, vector->container, - vec_cloned->struct_size * vec_cloned->capacity); + (size_t)vec_cloned->struct_size * vec_cloned->capacity); return vec_cloned; } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index 6160952245b43..7cd7bddea4236 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -3401,7 +3401,7 @@ bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe) uint32_t height = subvp_active_margin_list.res[i].height; refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 + - pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1); + (uint64_t)pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1); refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total); refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total); diff --git a/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c index 259a98e4ee2c2..2a422e223bf2a 100644 --- a/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c +++ b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c @@ -284,7 +284,7 @@ void mcifwb2_dump_frame(struct mcif_wb *mcif_wb, REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0xf); - memcpy(dest_luma_buffer, luma_buffer, mcif_params->luma_pitch * dest_height); + memcpy(dest_luma_buffer, luma_buffer, (size_t)mcif_params->luma_pitch * dest_height); memcpy(dest_chroma_buffer, chroma_buffer, mcif_params->chroma_pitch * dest_height / 2); REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0x0); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c index 164ba796f64ce..869a8e515fc09 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c @@ -1111,12 +1111,12 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc) &clks); dc->bw_vbios->low_yclk = bw_frc_to_fixed( - clks.clocks_in_khz[0] * memory_type_multiplier, 1000); + (int64_t)clks.clocks_in_khz[0] * memory_type_multiplier, 1000); dc->bw_vbios->mid_yclk = bw_frc_to_fixed( - clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier, + (int64_t)clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier, 1000); dc->bw_vbios->high_yclk = bw_frc_to_fixed( - clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier, + (int64_t)clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier, 1000); return; @@ -1152,12 +1152,12 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc) * YCLK = UMACLK*m_memoryTypeMultiplier */ dc->bw_vbios->low_yclk = bw_frc_to_fixed( - mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000); + (int64_t)mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000); dc->bw_vbios->mid_yclk = bw_frc_to_fixed( - mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier, + (int64_t)mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier, 1000); dc->bw_vbios->high_yclk = bw_frc_to_fixed( - mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier, + (int64_t)mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier, 1000); /* Now notify PPLib/SMU about which Watermarks sets they should select diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c index eb1e158d34361..2f23cc6df5711 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c @@ -990,12 +990,12 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc) memory_type_multiplier = MEMORY_TYPE_HBM; dc->bw_vbios->low_yclk = bw_frc_to_fixed( - mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000); + (int64_t)mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000); dc->bw_vbios->mid_yclk = bw_frc_to_fixed( - mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier, + (int64_t)mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier, 1000); dc->bw_vbios->high_yclk = bw_frc_to_fixed( - mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier, + (int64_t)mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier, 1000); /* Now notify PPLib/SMU about which Watermarks sets they should select From c5901dcf4017785aec05db2ae4b5bf06c99ec6a6 Mon Sep 17 00:00:00 2001 From: Clay King Date: Thu, 14 Aug 2025 17:02:45 -0400 Subject: [PATCH 1766/2653] drm/amd/display: Incorrect 'not' operator usage Consolidating multiple CodeQL Fixes for alerts with rule id: cpp/incorrect-not-operator-usage Reviewed-by: Joshua Aberback Signed-off-by: Clay King Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c | 2 +- .../gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c | 2 +- .../gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c | 2 +- .../gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c | 2 +- .../gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c | 2 +- .../gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c | 2 +- .../gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c index 0421b267a0b5f..365dd2e37aea6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c @@ -591,7 +591,7 @@ static bool dce_i2c_hw_engine_submit_payload(struct dce_i2c_hw *dce_i2c_hw, DCE_I2C_TRANSACTION_ACTION_I2C_WRITE; - request.address = (uint8_t) ((payload->address << 1) | !payload->write); + request.address = (uint8_t) ((payload->address << 1) | (payload->write ? 0 : 1)); request.length = payload->length; request.data = payload->data; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c index e188447c8156b..2d73b94c515ca 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c @@ -451,7 +451,7 @@ static bool dce_i2c_sw_engine_submit_payload(struct dce_i2c_sw *engine, DCE_I2C_TRANSACTION_ACTION_I2C_WRITE_MOT : DCE_I2C_TRANSACTION_ACTION_I2C_WRITE; - request.address = (uint8_t) ((payload->address << 1) | !payload->write); + request.address = (uint8_t) ((payload->address << 1) | (payload->write ? 0 : 1)); request.length = payload->length; request.data = payload->data; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c index 390c1a77fda6a..9c58ff1069d6b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c @@ -646,7 +646,7 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, // the dpte_group_bytes is reduced for the specific case of vertical // access of a tile surface that has dpte request of 8x1 ptes. - if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group + if (!surf_linear && (log2_dpte_req_height_ptes == 0) && surf_vert) //reduced, in this case, will have page fault within a group rq_sizing_param->dpte_group_bytes = 512; else //full size diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c index 843d6004258ce..570e6e39eb455 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c @@ -646,7 +646,7 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, // the dpte_group_bytes is reduced for the specific case of vertical // access of a tile surface that has dpte request of 8x1 ptes. - if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group + if (!surf_linear && (log2_dpte_req_height_ptes == 0) && surf_vert) //reduced, in this case, will have page fault within a group rq_sizing_param->dpte_group_bytes = 512; else //full size diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c index 5718000627b08..f549da082c014 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c @@ -652,7 +652,7 @@ static void get_meta_and_pte_attr( if (hostvm_enable) rq_sizing_param->dpte_group_bytes = 512; else { - if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group + if (!surf_linear && (log2_dpte_req_height_ptes == 0) && surf_vert) //reduced, in this case, will have page fault within a group rq_sizing_param->dpte_group_bytes = 512; else //full size diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c index 8d4873f80df02..4fb37df54d59f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c @@ -620,7 +620,7 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, if (hostvm_enable) rq_sizing_param->dpte_group_bytes = 512; else { - if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group + if (!surf_linear && (log2_dpte_req_height_ptes == 0) && surf_vert) //reduced, in this case, will have page fault within a group rq_sizing_param->dpte_group_bytes = 512; else rq_sizing_param->dpte_group_bytes = 2048; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c index c46bda2141acd..bfeb01477f0c4 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c @@ -615,7 +615,7 @@ static void get_meta_and_pte_attr( if (hostvm_enable) rq_sizing_param->dpte_group_bytes = 512; else { - if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group + if (!surf_linear && (log2_dpte_req_height_ptes == 0) && surf_vert) //reduced, in this case, will have page fault within a group rq_sizing_param->dpte_group_bytes = 512; else rq_sizing_param->dpte_group_bytes = 2048; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c index b7d2a0caec11b..04df263ff65ed 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c @@ -703,7 +703,7 @@ static void get_meta_and_pte_attr( if (hostvm_enable) rq_sizing_param->dpte_group_bytes = 512; else { - if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group + if (!surf_linear && (log2_dpte_req_height_ptes == 0) && surf_vert) //reduced, in this case, will have page fault within a group rq_sizing_param->dpte_group_bytes = 512; else rq_sizing_param->dpte_group_bytes = 2048; From f9c11e0916b1c6521effba80a37f88f2a5c139ef Mon Sep 17 00:00:00 2001 From: Yihan Zhu Date: Wed, 13 Aug 2025 16:05:10 -0400 Subject: [PATCH 1767/2653] drm/amd/display: wait for otg update pending latch before clock optimization [WHY & HOW] OTG pending update unlatched will cause system fail, wait OTG fully disabled to avoid this error. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Yihan Zhu Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler --- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 2 ++ .../amd/display/dc/inc/hw/timing_generator.h | 1 + .../drm/amd/display/dc/optc/dcn32/dcn32_optc.h | 1 + .../drm/amd/display/dc/optc/dcn35/dcn35_optc.c | 18 ++++++++++++++++++ 4 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index ec4e80e5b6eb2..d82b1cb467f4b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -1177,6 +1177,8 @@ void hwss_wait_for_odm_update_pending_complete(struct dc *dc, struct dc_state *c tg = otg_master->stream_res.tg; if (tg->funcs->wait_odm_doublebuffer_pending_clear) tg->funcs->wait_odm_doublebuffer_pending_clear(tg); + if (tg->funcs->wait_otg_disable) + tg->funcs->wait_otg_disable(tg); } /* ODM update may require to reprogram blank pattern for each OPP */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 267ace4eef8a3..f2de2cf23859e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -374,6 +374,7 @@ struct timing_generator_funcs { void (*wait_drr_doublebuffer_pending_clear)(struct timing_generator *tg); void (*set_long_vtotal)(struct timing_generator *optc, const struct long_vtotal_params *params); void (*wait_odm_doublebuffer_pending_clear)(struct timing_generator *tg); + void (*wait_otg_disable)(struct timing_generator *optc); bool (*get_optc_double_buffer_pending)(struct timing_generator *tg); bool (*get_otg_double_buffer_pending)(struct timing_generator *tg); bool (*get_pipe_update_pending)(struct timing_generator *tg); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h index d159e3ed3bb3c..ead92ad78a234 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h @@ -62,6 +62,7 @@ SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\ SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\ SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, mask_sh),\ SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\ SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\ SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c index 72bff94cb57da..52d5ea98c86b1 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c @@ -162,6 +162,8 @@ static bool optc35_disable_crtc(struct timing_generator *optc) REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); + REG_WAIT(OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, 0, 1, 100000); + optc1_clear_optc_underflow(optc); return true; @@ -428,6 +430,21 @@ static void optc35_set_long_vtotal( } } +static void optc35_wait_otg_disable(struct timing_generator *optc) +{ + struct optc *optc1; + uint32_t is_master_en; + + if (!optc || !optc->ctx) + return; + + optc1 = DCN10TG_FROM_TG(optc); + + REG_GET(OTG_CONTROL, OTG_MASTER_EN, &is_master_en); + if (!is_master_en) + REG_WAIT(OTG_CLOCK_CONTROL, OTG_CURRENT_MASTER_EN_STATE, 0, 1, 100000); +} + static const struct timing_generator_funcs dcn35_tg_funcs = { .validate_timing = optc1_validate_timing, .program_timing = optc1_program_timing, @@ -479,6 +496,7 @@ static const struct timing_generator_funcs dcn35_tg_funcs = { .set_odm_bypass = optc32_set_odm_bypass, .set_odm_combine = optc35_set_odm_combine, .get_optc_source = optc2_get_optc_source, + .wait_otg_disable = optc35_wait_otg_disable, .set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode, .set_out_mux = optc3_set_out_mux, .set_drr_trigger_window = optc3_set_drr_trigger_window, From 90bd21a3e54e2cd3567fd3563b3e72d125eadc98 Mon Sep 17 00:00:00 2001 From: Clay King Date: Thu, 14 Aug 2025 17:01:04 -0400 Subject: [PATCH 1768/2653] drm/amd/display: Array offset used before range check Consolidating multiple CodeQL Fixes for alerts with rule id: cpp/offset-use-before-range-check Reviewed-by: Joshua Aberback Signed-off-by: Clay King Signed-off-by: Aurabindo Pillai Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c | 2 +- drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c | 2 +- drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +- drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c | 2 +- drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c index 8da97a96b1ceb..8d7c59ec701dc 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c @@ -280,7 +280,7 @@ void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p j = 0; /* create the final dcfclk and uclk table */ while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { - if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { + if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; } else { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c index e968870a4b810..b5d3fd4c3694e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c @@ -285,7 +285,7 @@ void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_p j = 0; /* create the final dcfclk and uclk table */ while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { - if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { + if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; } else { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index 7cd7bddea4236..18388fb00be8c 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -3229,7 +3229,7 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa j = 0; // create the final dcfclk and uclk table while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { - if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { + if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; } else { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c index 8839faf42207b..e0a1dc89ce43f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c @@ -779,7 +779,7 @@ void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p j = 0; // create the final dcfclk and uclk table while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { - if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { + if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; } else { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c index 895349d9ca07c..201ed863b69eb 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c @@ -2192,7 +2192,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params j = 0; // create the final dcfclk and uclk table while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { - if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { + if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; } else { From cf06f7fafaea9fa72f2e7afe1bd5c50c03237d2c Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Thu, 14 Aug 2025 12:01:15 -0400 Subject: [PATCH 1769/2653] drm/amd/display: Consider sink max slice width limitation for dsc [WHY&HOW] The sink max slice width limitation should be considered for DSC, but was removed in "refactor DSC cap calculations". This patch adds it back and takes the valid minimum between the sink and source. Signed-off-by: Dillon Varone Signed-off-by: Aurabindo Pillai Reviewed-by: Wenjing Liu Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 1f53a9f0c0ac3..e4144b2443324 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -1157,6 +1157,11 @@ static bool setup_dsc_config( if (!is_dsc_possible) goto done; + /* increase miniumum slice count to meet sink slice width limitations */ + min_slices_h = dc_fixpt_ceil(dc_fixpt_max( + dc_fixpt_div_int(dc_fixpt_from_int(pic_width), dsc_common_caps.max_slice_width), // sink min + dc_fixpt_from_int(min_slices_h))); // source min + min_slices_h = fit_num_slices_up(dsc_common_caps.slice_caps, min_slices_h); /* increase minimum slice count to meet sink throughput limitations */ From 0cadfcd1316dd1f1132473654e1dcc18104d0944 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 15 Aug 2025 19:23:50 -0400 Subject: [PATCH 1770/2653] drm/amd/display: [FW Promotion] Release 0.1.24.0 Add two new IPS residency data modes. Signed-off-by: Taimur Hassan Signed-off-by: Aurabindo Pillai Reviewed-by: Leo Li Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index d7008d84c1ec1..b7d49a117fa7c 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -6021,6 +6021,8 @@ enum ips_residency_mode { IPS_RESIDENCY__IPS1_RCG, IPS_RESIDENCY__IPS1_ONO2_ON, IPS_RESIDENCY__IPS1_Z8_RETENTION, + IPS_RESIDENCY__PG_ONO_LAST_SEEN_IN_IPS, + IPS_RESIDENCY__PG_ONO_CURRENT_STATE }; #define NUM_IPS_HISTOGRAM_BUCKETS 16 @@ -6034,6 +6036,8 @@ struct dmub_ips_residency_info { uint32_t histogram[NUM_IPS_HISTOGRAM_BUCKETS]; uint64_t total_time_us; uint64_t total_inactive_time_us; + uint32_t ono_pg_state_at_collection; + uint32_t ono_pg_state_last_seen_in_ips; }; /** From ad94bf51d67b96647b0e513a877950fe1019e6f0 Mon Sep 17 00:00:00 2001 From: Nicholas Carbones Date: Fri, 15 Aug 2025 20:45:14 -0400 Subject: [PATCH 1771/2653] drm/amd/display: DC v3.2.347 DC Release v3.2.347 * Firmware releases for multiple asics * CodeQL fixes * Fix for double cursor with 180 degree rotation on large resolutions * Misc bug fixes for DSC, PSR/Replay, DPIA etc. Signed-off-by: Nicholas Carbones Signed-off-by: Aurabindo Pillai Reviewed-by: Leo Li Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 0cfd5bcc1fa9b..673e3c5a5257c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.346" +#define DC_VER "3.2.347" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From 1a1334ac3515ffe857b8c94a20e9c4858e7df50d Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Sat, 23 Aug 2025 15:00:06 +0800 Subject: [PATCH 1772/2653] drm/amdgpu: fix shift-out-of-bounds in amdgpu_debugfs_jpeg_sched_mask_set Fix a UBSAN shift-out-of-bounds warning in amdgpu_debugfs_jpeg_sched_mask_set when the shift exponent reaches or exceeds 32 bits. The issue occurred because a 32-bit integer '1' was being shifted by up to 32 bits, which is undefined behavior. Replace '1' with '1ULL' to ensure 64-bit arithmetic, matching the u64 type of 'val' and preventing the shift overflow. This is consistent with the existing mask calculation that already uses 1ULL. The error manifested as: UBSAN: shift-out-of-bounds in drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c:373:17 shift exponent 32 is too large for 32-bit type 'int' v2: remove debug log Reviewed-by: Lijo Lazar Suggested-by: Lijo Lazar Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c index 5d5e9ee83a5d6..f0d7e2487237c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c @@ -370,7 +370,7 @@ static int amdgpu_debugfs_jpeg_sched_mask_set(void *data, u64 val) for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { ring = &adev->jpeg.inst[i].ring_dec[j]; - if (val & (1 << ((i * adev->jpeg.num_jpeg_rings) + j))) + if (val & (BIT_ULL(1) << ((i * adev->jpeg.num_jpeg_rings) + j))) ring->sched.ready = true; else ring->sched.ready = false; From baf6a73245b83eb12bcadf898a95ff557fbe7d18 Mon Sep 17 00:00:00 2001 From: Shaoyun Liu Date: Fri, 4 Jul 2025 12:30:10 -0400 Subject: [PATCH 1773/2653] drm/amd/include : Update MES v12 API header(INV_TLBS) The requirement from driver side is to have an API that can do the tlb invalidation on dedicate pasid since driver don't know the vmid and process mapping. Make the API generic to support different tlb invalidation related request. Driver can specify pasid, vmid, hub_id and vm address range need to be invalidated. With this API the old INV_GART in MISC Op can be deprecated. Signed-off-by: Shaoyun Liu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/include/mes_v12_api_def.h | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/gpu/drm/amd/include/mes_v12_api_def.h b/drivers/gpu/drm/amd/include/mes_v12_api_def.h index d85ffab2aff9d..c04bd351b2505 100644 --- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h +++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h @@ -66,6 +66,7 @@ enum MES_SCH_API_OPCODE { MES_SCH_API_SET_SE_MODE = 17, MES_SCH_API_SET_GANG_SUBMIT = 18, MES_SCH_API_SET_HW_RSRC_1 = 19, + MES_SCH_API_INV_TLBS = 20, MES_SCH_API_MAX = 0xFF }; @@ -870,6 +871,35 @@ union MESAPI__SET_GANG_SUBMIT { uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; }; +/* + * @inv_sel 0-select pasid as input to do the invalidation , 1-select vmid + * @flush_type 0-old style, 1-light weight, 2-heavyweight, 3-heavyweight2 + * @inv_sel_id specific pasid when inv_sel is 0 and specific vmid if inv_sel is 1 + * @hub_id 0-gc_hub, 1-mm_hub + */ +struct INV_TLBS { + uint8_t inv_sel; + uint8_t flush_type; + uint16_t inv_sel_id; + uint32_t hub_id; + /* If following two inv_range setting are all 0 , whole VM will be invalidated, + * otherwise only required range be invalidated + */ + uint64_t inv_range_va_start; + uint64_t inv_range_size; + uint64_t reserved; +}; + +union MESAPI__INV_TLBS { + struct { + union MES_API_HEADER header; + struct MES_API_STATUS api_status; + struct INV_TLBS invalidate_tlbs; + }; + + uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; +}; + #pragma pack(pop) #endif From 9c4ee796853189a1c2b8f3095d14123bee53e723 Mon Sep 17 00:00:00 2001 From: Shaoyun Liu Date: Thu, 10 Jul 2025 21:42:16 -0400 Subject: [PATCH 1774/2653] drm/amd/amdgpu : Use the MES INV_TLBS API for tlb invalidation on gfx12 From MES version 0x81, it provide the new API INV_TLBS that support invalidate tlbs with PASID. Signed-off-by: Shaoyun Liu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 10 ++++++ drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 16 ++++++++++ drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 42 +++++++++++++++++++++++++ 3 files changed, 68 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index c0d2c195fe2ed..489a4a0f06105 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -280,6 +280,13 @@ struct mes_reset_queue_input { bool is_kq; }; +struct mes_inv_tlbs_pasid_input { + uint32_t xcc_id; + uint16_t pasid; + uint8_t hub_id; + uint8_t flush_type; +}; + enum mes_misc_opcode { MES_MISC_OP_WRITE_REG, MES_MISC_OP_READ_REG, @@ -367,6 +374,9 @@ struct amdgpu_mes_funcs { int (*reset_hw_queue)(struct amdgpu_mes *mes, struct mes_reset_queue_input *input); + + int (*invalidate_tlbs_pasid)(struct amdgpu_mes *mes, + struct mes_inv_tlbs_pasid_input *input); }; #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index a0a5367f9dc40..9ba055ddc00f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -336,6 +336,22 @@ static void gmc_v12_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t queried; int vmid, i; + if (adev->enable_uni_mes && adev->mes.ring[AMDGPU_MES_SCHED_PIPE].sched.ready && + (adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x81) { + struct mes_inv_tlbs_pasid_input input = {0}; + input.pasid = pasid; + input.flush_type = flush_type; + input.hub_id = AMDGPU_GFXHUB(0); + /* MES will invalidate all gc_hub for the device from master */ + adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); + if (all_hub) { + /* Only need to invalidate mm_hub now, gfx12 only support one mmhub */ + input.hub_id = AMDGPU_MMHUB0(0); + adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); + } + return; + } + for (vmid = 1; vmid < 16; vmid++) { bool valid; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index 6b222630f3fa1..cd5c966cee957 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -108,6 +108,7 @@ static const char *mes_v12_0_opcodes[] = { "SET_SE_MODE", "SET_GANG_SUBMIT", "SET_HW_RSRC_1", + "INVALIDATE_TLBS", }; static const char *mes_v12_0_misc_opcodes[] = { @@ -879,6 +880,46 @@ static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes, offsetof(union MESAPI__RESET, api_status)); } +static int mes_v12_inv_tlb_convert_hub_id(uint8_t id) +{ + /* + * MES doesn't support invalidate gc_hub on slave xcc individually + * master xcc will invalidate all gc_hub for the partition + */ + if (AMDGPU_IS_GFXHUB(id)) + return 0; + else if (AMDGPU_IS_MMHUB0(id)) + return 1; + else + return -EINVAL; + +} + +static int mes_v12_0_inv_tlbs_pasid(struct amdgpu_mes *mes, + struct mes_inv_tlbs_pasid_input *input) +{ + union MESAPI__INV_TLBS mes_inv_tlbs; + + memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs)); + + mes_inv_tlbs.header.type = MES_API_TYPE_SCHEDULER; + mes_inv_tlbs.header.opcode = MES_SCH_API_INV_TLBS; + mes_inv_tlbs.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_inv_tlbs.invalidate_tlbs.inv_sel = 0; + mes_inv_tlbs.invalidate_tlbs.flush_type = input->flush_type; + mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input->pasid; + + /*convert amdgpu_mes_hub_id to mes expected hub_id */ + mes_inv_tlbs.invalidate_tlbs.hub_id = mes_v12_inv_tlb_convert_hub_id(input->hub_id); + if (mes_inv_tlbs.invalidate_tlbs.hub_id < 0) + return -EINVAL; + return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_KIQ_PIPE, + &mes_inv_tlbs, sizeof(mes_inv_tlbs), + offsetof(union MESAPI__INV_TLBS, api_status)); + +} + static const struct amdgpu_mes_funcs mes_v12_0_funcs = { .add_hw_queue = mes_v12_0_add_hw_queue, .remove_hw_queue = mes_v12_0_remove_hw_queue, @@ -888,6 +929,7 @@ static const struct amdgpu_mes_funcs mes_v12_0_funcs = { .resume_gang = mes_v12_0_resume_gang, .misc_op = mes_v12_0_misc_op, .reset_hw_queue = mes_v12_0_reset_hw_queue, + .invalidate_tlbs_pasid = mes_v12_0_inv_tlbs_pasid, }; static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, From 0d2c351ab76c3c10ca7215d2ba03f9e21d693d69 Mon Sep 17 00:00:00 2001 From: "David (Ming Qiang) Wu" Date: Mon, 25 Aug 2025 15:12:18 -0400 Subject: [PATCH 1775/2653] drm/amdgpu/vcn: remove unused code in vcn_v1_0.c Reviewed-by: Alex Deucher Signed-off-by: David (Ming Qiang) Wu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index c74947705d778..1e89ba153d9d3 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -1338,7 +1338,6 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); - ring = &adev->vcn.inst->ring_dec; WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, @@ -1399,7 +1398,6 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); - ring = &adev->vcn.inst->ring_dec; WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, From 9ba7de2bf4497685f6a139273eb00dc358f546c0 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 25 Aug 2025 09:35:07 -0400 Subject: [PATCH 1776/2653] drm/amdgpu/vpe: cancel delayed work in hw_fini We need to cancel any outstanding work at both suspend and driver teardown. Move the cancel to hw_fini which gets called in both cases. Reviewed-by: David (Ming Qiang) Wu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c index 86573c8d9b91e..474bfe36c0c2f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c @@ -436,6 +436,8 @@ static int vpe_hw_fini(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; struct amdgpu_vpe *vpe = &adev->vpe; + cancel_delayed_work_sync(&adev->vpe.idle_work); + vpe_ring_stop(vpe); /* Power off VPE */ @@ -446,10 +448,6 @@ static int vpe_hw_fini(struct amdgpu_ip_block *ip_block) static int vpe_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - cancel_delayed_work_sync(&adev->vpe.idle_work); - return vpe_hw_fini(ip_block); } From 58cd151e7fc8bb493c338fc8172966540036eb3c Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Mon, 25 Aug 2025 12:54:01 +0800 Subject: [PATCH 1777/2653] drm/amd/amdgpu: disable hwmon power1_cap* for gfx 11.0.3 on vf mode the PPSMC_MSG_GetPptLimit msg is not valid for gfx 11.0.3 on vf mode, so skiped to create power1_cap* hwmon sysfs node. Signed-off-by: Yang Wang Reviewed-by: Asad Kamal Acked-by: Alex Deucher --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index c5b8bc0d130a7..c59bdd15e0e5c 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -3586,14 +3586,16 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, effective_mode &= ~S_IWUSR; /* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */ - if (((adev->family == AMDGPU_FAMILY_SI) || - ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) && - (gc_ver != IP_VERSION(9, 4, 3) && gc_ver != IP_VERSION(9, 4, 4)))) && - (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || - attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr || - attr == &sensor_dev_attr_power1_cap.dev_attr.attr || - attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr)) - return 0; + if (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || + attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr || + attr == &sensor_dev_attr_power1_cap.dev_attr.attr || + attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr) { + if (adev->family == AMDGPU_FAMILY_SI || + ((adev->flags & AMD_IS_APU) && gc_ver != IP_VERSION(10, 3, 1) && + (gc_ver != IP_VERSION(9, 4, 3) && gc_ver != IP_VERSION(9, 4, 4))) || + (amdgpu_sriov_vf(adev) && gc_ver == IP_VERSION(11, 0, 3))) + return 0; + } /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */ if (((adev->family == AMDGPU_FAMILY_SI) || From adfd2e43b314810b436a661ed818cbb005e20508 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 31 Jul 2025 11:43:47 +0200 Subject: [PATCH 1778/2653] drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15% MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adjust the nominal (and performance) clocks for DCE 8-10, and set them to 625 MHz, which is the value used by the legacy display code in amdgpu_atombios_get_clock_info. This was tested with Hawaii, Tonga and Fiji. These GPUs can output 4K 60Hz (10-bit depth) at 625 MHz. The extra 15% clock was added as a workaround for a Polaris issue which uses DCE 11, and should not have been used on DCE 8-10 which are already hardcoded to the highest possible display clock. Unfortunately, the extra 15% was mistakenly copied and kept even on code paths which don't affect Polaris. This commit fixes that and also adds a check to make sure not to exceed the maximum DCE 8-10 display clock. Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris") Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific") Signed-off-by: Timur Kristóf Acked-by: Alex Deucher Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Hung --- .../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index e846e49203939..dbd6ef1b60a0b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -72,9 +72,9 @@ static const struct state_dependent_clocks dce80_max_clks_by_state[] = { /* ClocksStateLow */ { .display_clk_khz = 352000, .pixel_clk_khz = 330000}, /* ClocksStateNominal */ -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 }, +{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 }, /* ClocksStatePerformance */ -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } }; +{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 } }; int dentist_get_divider_from_did(int did) { @@ -403,11 +403,9 @@ static void dce_update_clocks(struct clk_mgr *clk_mgr_base, { struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); struct dm_pp_power_level_change_request level_change_req; - int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; - - /*TODO: W/A for dal3 linux, investigate why this works */ - if (!clk_mgr_dce->dfs_bypass_active) - patched_disp_clk = patched_disp_clk * 115 / 100; + const int max_disp_clk = + clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz; + int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz); level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); /* get max clock state from PPLIB */ From fd6fd231013c263fd7525f69bbdb167b97901497 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 21 Aug 2025 11:13:31 +0800 Subject: [PATCH 1779/2653] drm/amdkcl: test whether MIN() exist it's caused by 3a02acd7ed124c9 "drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15%" Signed-off-by: Yang Su --- include/kcl/kcl_minmax.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/kcl/kcl_minmax.h b/include/kcl/kcl_minmax.h index 618e166564d98..208a5a940b92e 100644 --- a/include/kcl/kcl_minmax.h +++ b/include/kcl/kcl_minmax.h @@ -9,4 +9,12 @@ min((x) + 0u + 0ul + 0ull, (y) + 0u + 0ul + 0ull) #endif +#ifndef MIN +#define __cmp_op_min < + +#define __cmp(op, x, y) ((x) __cmp_op_##op (y) ? (x) : (y)) + +#define MIN(a, b) __cmp(min, a, b) +#endif + #endif /* _KCL_MINMAX_H */ From ed1f8e15fd930eb163269448ad3e3ecf6fcf4fd3 Mon Sep 17 00:00:00 2001 From: Tom Chung Date: Fri, 18 Jul 2025 18:25:08 +0800 Subject: [PATCH 1780/2653] drm/amd/display: Fix Xorg desktop unresponsive on Replay panel [WHY & HOW] IPS & self-fresh feature can cause vblank counter resets between vblank disable and enable. It may cause system stuck due to wait the vblank counter. Call the drm_crtc_vblank_restore() during vblank enable to estimate missed vblanks by using timestamps and update the vblank counter in DRM. It can make the vblank counter increase smoothly and resolve this issue. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Sun peng (Leo) Li Signed-off-by: Tom Chung Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index d6eacb03b6e29..a59e0aef467c0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -299,6 +299,25 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); if (enable) { + struct dc *dc = adev->dm.dc; + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); + struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; + struct replay_settings *pr = &acrtc_state->stream->link->replay_settings; + bool sr_supported = (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED) || + pr->config.replay_supported; + + /* + * IPS & self-refresh feature can cause vblank counter resets between + * vblank disable and enable. + * It may cause system stuck due to waiting for the vblank counter. + * Call this function to estimate missed vblanks by using timestamps and + * update the vblank counter in DRM. + */ + if (dc->caps.ips_support && + dc->config.disable_ips != DMUB_IPS_DISABLE_ALL && + sr_supported && vblank->config.disable_immediate) + drm_crtc_vblank_restore(crtc); + /* vblank irq on -> Only need vupdate irq in vrr mode */ if (amdgpu_dm_crtc_vrr_active(acrtc_state)) rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true); From bdbc6d5986c791978afb7811b8a1cfdff8be4587 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Wed, 20 Aug 2025 17:36:45 +0800 Subject: [PATCH 1781/2653] drm/amdkcl: wrap code under HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG in the old kernel version, struct drm_vblank_crtc doesn't have member "config". so bypass in the code. it's cuased by 142fc1c2ce2684 "drm/amd/display: Fix Xorg desktop unresponsive on Replay panel" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 3 ++- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 23 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index a59e0aef467c0..5c8944bc92183 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -299,6 +299,7 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); if (enable) { +#ifdef HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG struct dc *dc = adev->dm.dc; struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; @@ -317,7 +318,7 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) dc->config.disable_ips != DMUB_IPS_DISABLE_ALL && sr_supported && vblank->config.disable_immediate) drm_crtc_vblank_restore(crtc); - +#endif /* vblank irq on -> Only need vupdate irq in vrr mode */ if (amdgpu_dm_crtc_vrr_active(acrtc_state)) rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3e9e04d6dbb13..68564156959b9 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -720,6 +720,9 @@ /* drm_vblank_crtc_config is available */ #define HAVE_DRM_VBLANK_CRTC_CONFIG 1 +/* struct vblank->config is available */ +#define HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG 1 + /* struct drm_vma_offset_node has readonly field */ /* #undef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 new file mode 100644 index 0000000000000..f7f9216f54f2e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v6.10-rc1-595-g0d5040e406d2 +dnl # drm/vblank: add dynamic per-crtc vblank configuration support +dnl # +AC_DEFUN([AC_AMDGPU_DRM_VBLANK_CRTC_STRUCT_CONFIG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_vblank_crtc *vblank = NULL; + vblank->config = NULL; + ],[ + AC_DEFINE(HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG, 1, + [struct vblank->config is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d0b38a34e0ebf..353d0722b9a52 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -288,6 +288,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_IS_IMPORTED AC_AMDGPU_DMA_FENCE_INIT64 AC_AMDGPU_DRM_FILE_DEBUGFS_CLIENT + AC_AMDGPU_DRM_VBLANK_CRTC_STRUCT_CONFIG AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From a8c463feade8c319af48f86888a228bbfdf98999 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 24 Jul 2025 13:01:09 -0500 Subject: [PATCH 1782/2653] drm/amd/display: Attach privacy screen to DRM connector [WHY] If a system has a privacy screen advertised by a driver it should be included in the DRM connector for the eDP panel. [HOW] Detect statically declared privacy screens when creating eDP connector and attach privacy screen DRM properties. Reviewed-by: Harry Wentland Signed-off-by: Mario Limonciello Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 25 ++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5c7baf8e2fbfd..dcbd403108299 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -81,6 +81,7 @@ #include #include +#include #include #include #include @@ -8060,6 +8061,14 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, if (!crtc) return 0; + if (new_con_state->privacy_screen_sw_state != old_con_state->privacy_screen_sw_state) { + new_crtc_state = drm_atomic_get_crtc_state(state, crtc); + if (IS_ERR(new_crtc_state)) + return PTR_ERR(new_crtc_state); + + new_crtc_state->mode_changed = true; + } + if (new_con_state->colorspace != old_con_state->colorspace) { new_crtc_state = drm_atomic_get_crtc_state(state, crtc); if (IS_ERR(new_crtc_state)) @@ -8837,6 +8846,18 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, drm_connector_attach_content_protection_property(&aconnector->base); #endif } + + if (connector_type == DRM_MODE_CONNECTOR_eDP) { + struct drm_privacy_screen *privacy_screen; + + privacy_screen = drm_privacy_screen_get(adev_to_drm(adev)->dev, NULL); + if (!IS_ERR(privacy_screen)) { + drm_connector_attach_privacy_screen_provider(&aconnector->base, + privacy_screen); + } else if (PTR_ERR(privacy_screen) != -ENODEV) { + drm_warn(adev_to_drm(adev), "Error getting privacy-screen\n"); + } + } } static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, @@ -10589,7 +10610,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) unsigned long flags; bool wait_for_vblank = true; struct drm_connector *connector; - struct drm_connector_state *old_con_state, *new_con_state; + struct drm_connector_state *old_con_state = NULL, *new_con_state = NULL; struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; int crtc_disable_count = 0; @@ -10722,6 +10743,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) &stream_update); mutex_unlock(&dm->dc_lock); kfree(dummy_updates); + + drm_connector_update_privacy_screen(new_con_state); } /** From fb071bd864daa156d5331c2c4ccd0fe73035099f Mon Sep 17 00:00:00 2001 From: Yang Su Date: Wed, 27 Aug 2025 17:42:16 +0800 Subject: [PATCH 1783/2653] Revert "drm/amd/display: Attach privacy screen to DRM connector" This reverts commit a8c463feade8c319af48f86888a228bbfdf98999. --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 25 +------------------ 1 file changed, 1 insertion(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index dcbd403108299..5c7baf8e2fbfd 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -81,7 +81,6 @@ #include #include -#include #include #include #include @@ -8061,14 +8060,6 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, if (!crtc) return 0; - if (new_con_state->privacy_screen_sw_state != old_con_state->privacy_screen_sw_state) { - new_crtc_state = drm_atomic_get_crtc_state(state, crtc); - if (IS_ERR(new_crtc_state)) - return PTR_ERR(new_crtc_state); - - new_crtc_state->mode_changed = true; - } - if (new_con_state->colorspace != old_con_state->colorspace) { new_crtc_state = drm_atomic_get_crtc_state(state, crtc); if (IS_ERR(new_crtc_state)) @@ -8846,18 +8837,6 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, drm_connector_attach_content_protection_property(&aconnector->base); #endif } - - if (connector_type == DRM_MODE_CONNECTOR_eDP) { - struct drm_privacy_screen *privacy_screen; - - privacy_screen = drm_privacy_screen_get(adev_to_drm(adev)->dev, NULL); - if (!IS_ERR(privacy_screen)) { - drm_connector_attach_privacy_screen_provider(&aconnector->base, - privacy_screen); - } else if (PTR_ERR(privacy_screen) != -ENODEV) { - drm_warn(adev_to_drm(adev), "Error getting privacy-screen\n"); - } - } } static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, @@ -10610,7 +10589,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) unsigned long flags; bool wait_for_vblank = true; struct drm_connector *connector; - struct drm_connector_state *old_con_state = NULL, *new_con_state = NULL; + struct drm_connector_state *old_con_state, *new_con_state; struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; int crtc_disable_count = 0; @@ -10743,8 +10722,6 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) &stream_update); mutex_unlock(&dm->dc_lock); kfree(dummy_updates); - - drm_connector_update_privacy_screen(new_con_state); } /** From 07951d2540d50633525516a63033875cdcaf1a5e Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 28 Aug 2025 13:20:09 +0800 Subject: [PATCH 1784/2653] Bump AMDGPU version to 6.16.1 Signed-off-by: Chengjun Yao --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 4f884d6bc20f6..a3fca23de87f2 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.16.0) +AC_INIT(amdgpu-dkms, 6.16.1) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From b07c9a2122dea04f955280605d771a0088a64eee Mon Sep 17 00:00:00 2001 From: Xiang Liu Date: Wed, 27 Aug 2025 09:40:27 +0800 Subject: [PATCH 1785/2653] drm/amdgpu: Notify pmfw bad page threshold exceeded Notify pmfw when bad page threshold is exceeded, no matter the module parameter 'bad_page_threshold' is set or not. Signed-off-by: Xiang Liu Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index e3e6b32e48308..3eb3fb55ccb05 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -777,9 +777,10 @@ amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) control->tbl_rai.health_percent = 0; } ras->is_rma = true; - /* ignore the -ENOTSUPP return value */ - amdgpu_dpm_send_rma_reason(adev); } + + /* ignore the -ENOTSUPP return value */ + amdgpu_dpm_send_rma_reason(adev); } if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) From 84a7262e3242a99ef6d37865600e071a85551854 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 22 Aug 2025 12:12:37 -0400 Subject: [PATCH 1786/2653] drm/amdgpu/userq: fix error handling of invalid doorbell If the doorbell is invalid, be sure to set the r to an error state so the function returns an error. Reviewed-by: David (Ming Qiang) Wu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 57435312470cb..7cf51a00411a2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -471,6 +471,7 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) if (index == (uint64_t)-EINVAL) { drm_file_err(uq_mgr->file, "Failed to get doorbell for queue\n"); kfree(queue); + r = -EINVAL; goto unlock; } From c1f590a6ef774cf726060eded7a825fd0e8c95a0 Mon Sep 17 00:00:00 2001 From: David Francis Date: Tue, 12 Aug 2025 14:19:18 -0400 Subject: [PATCH 1787/2653] drm/amdgpu: Allow more flags to be set on gem create. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The GEM create flag AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE specifies that gem memory contains sensitive information and should be cleared to prevent snooping. The COHERENT and UNCACHED gem create flags enable memory features related to sharing memory across devices. For CRIU we need to re-create KFD BOs through the GEM_CREATE IOCTL, so allow those KFD specific flags here as well. This will also aid us in the future and allows to move the KFD components over using the render node for allocations. Signed-off-by: David Francis Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 11 +---------- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index e9723049cde7e..dcc1b51e324b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -514,16 +514,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, int r; /* reject invalid gem flags */ - if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | - AMDGPU_GEM_CREATE_NO_CPU_ACCESS | - AMDGPU_GEM_CREATE_CPU_GTT_USWC | - AMDGPU_GEM_CREATE_VRAM_CLEARED | - AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | - AMDGPU_GEM_CREATE_EXPLICIT_SYNC | - AMDGPU_GEM_CREATE_ENCRYPTED | - AMDGPU_GEM_CREATE_GFX12_DCC | - AMDGPU_GEM_CREATE_NO_EVICT | - AMDGPU_GEM_CREATE_DISCARDABLE)) + if (flags & ~AMDGPU_GEM_CREATE_SETTABLE_MASK) return -EINVAL; /* reject invalid gem domains */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h index 1ddfc7f4f5e3b..6c45de02f4c7f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h @@ -73,4 +73,18 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); +#define AMDGPU_GEM_CREATE_SETTABLE_MASK (AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | \ + AMDGPU_GEM_CREATE_NO_CPU_ACCESS | \ + AMDGPU_GEM_CREATE_CPU_GTT_USWC | \ + AMDGPU_GEM_CREATE_VRAM_CLEARED | \ + AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | \ + AMDGPU_GEM_CREATE_EXPLICIT_SYNC | \ + AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE | \ + AMDGPU_GEM_CREATE_ENCRYPTED | \ + AMDGPU_GEM_CREATE_GFX12_DCC | \ + AMDGPU_GEM_CREATE_DISCARDABLE | \ + AMDGPU_GEM_CREATE_COHERENT | \ + AMDGPU_GEM_CREATE_UNCACHED | \ + AMDGPU_GEM_CREATE_EXT_COHERENT) + #endif From 93a19e70acbfa24891cf01e07205a8fe01538500 Mon Sep 17 00:00:00 2001 From: Yugansh Mittal Date: Sun, 24 Aug 2025 17:20:51 +0530 Subject: [PATCH 1788/2653] atomfirmware.h: fix multiple spelling mistakes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch corrects several typographical errors in atomfirmware.h. The fixes improve readability and maintain consistency in the codebase. No functional changes are introduced. Corrected terms include: - aligment → alignment - Offest → Offset - defintion → definition - swithing → switching - calcualted → calculated - compability → compatibility - intenal → internal - sequece → sequence - indiate → indicate - stucture → structure - regiser → register Signed-off-by: Yugansh Mittal Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/atomfirmware.h | 30 +++++++++++----------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index 5c86423c2e92f..3d083010e734a 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -211,7 +211,7 @@ atom_bios_string = "ATOM" }; */ -#pragma pack(1) /* BIOS data must use byte aligment*/ +#pragma pack(1) /* BIOS data must use byte alignment*/ enum atombios_image_offset{ OFFSET_TO_ATOM_ROM_HEADER_POINTER = 0x00000048, @@ -255,8 +255,8 @@ struct atom_rom_header_v2_2 uint16_t subsystem_vendor_id; uint16_t subsystem_id; uint16_t pci_info_offset; - uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position - uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position + uint16_t masterhwfunction_offset; //Offset for SW to get all command function offsets, Don't change the position + uint16_t masterdatatable_offset; //Offset for SW to get all data table offsets, Don't change the position uint16_t reserved; uint32_t pspdirtableoffset; }; @@ -453,7 +453,7 @@ struct atom_dtd_format uint8_t refreshrate; }; -/* atom_dtd_format.modemiscinfo defintion */ +/* atom_dtd_format.modemiscinfo definition */ enum atom_dtd_format_modemiscinfo{ ATOM_HSYNC_POLARITY = 0x0002, ATOM_VSYNC_POLARITY = 0x0004, @@ -678,7 +678,7 @@ struct lcd_info_v2_1 uint32_t reserved1[8]; }; -/* lcd_info_v2_1.panel_misc defintion */ +/* lcd_info_v2_1.panel_misc definition */ enum atom_lcd_info_panel_misc{ ATOM_PANEL_MISC_FPDI =0x0002, }; @@ -716,7 +716,7 @@ enum atom_gpio_pin_assignment_gpio_id { /* gpio_id pre-define id for multiple usage */ /* GPIO use to control PCIE_VDDC in certain SLT board */ PCIE_VDDC_CONTROL_GPIO_PINID = 56, - /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */ + /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC switching feature is enable */ PP_AC_DC_SWITCH_GPIO_PINID = 60, /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */ VDDC_VRHOT_GPIO_PINID = 61, @@ -734,7 +734,7 @@ enum atom_gpio_pin_assignment_gpio_id { struct atom_gpio_pin_lut_v2_1 { struct atom_common_table_header table_header; - /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */ + /*the real number of this included in the structure is calculated by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */ struct atom_gpio_pin_assignment gpio_pin[]; }; @@ -997,7 +997,7 @@ enum atom_connector_layout_info_mini_type_def { enum atom_display_device_tag_def{ ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display - ATOM_DISPLAY_LCD2_SUPPORT = 0x0020, //second edp device tag 0x0020 for backward compability + ATOM_DISPLAY_LCD2_SUPPORT = 0x0020, //second edp device tag 0x0020 for backward compatibility ATOM_DISPLAY_DFP1_SUPPORT = 0x0008, ATOM_DISPLAY_DFP2_SUPPORT = 0x0080, ATOM_DISPLAY_DFP3_SUPPORT = 0x0200, @@ -1011,7 +1011,7 @@ struct atom_display_object_path_v2 { uint16_t display_objid; //Connector Object ID or Misc Object ID uint16_t disp_recordoffset; - uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder + uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or internal encoder uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view; uint16_t encoder_recordoffset; uint16_t extencoder_recordoffset; @@ -1023,7 +1023,7 @@ struct atom_display_object_path_v2 struct atom_display_object_path_v3 { uint16_t display_objid; //Connector Object ID or Misc Object ID uint16_t disp_recordoffset; - uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder + uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or internal encoder uint16_t reserved1; //only on USBC case, otherwise always = 0 uint16_t reserved2; //reserved and always = 0 uint16_t reserved3; //reserved and always = 0 @@ -3547,7 +3547,7 @@ struct atom_voltage_object_header_v4{ enum atom_voltage_object_mode { VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4 - VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4 + VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequence through I2C -> atom_i2c_voltage_object_v4 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4 VOLTAGE_OBJ_EVV = 8, @@ -3585,7 +3585,7 @@ struct atom_gpio_voltage_object_v4 { struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode - uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table + uint8_t gpio_entry_num; // indicate the entry numbers of Votlage/Gpio value Look up table uint8_t phase_delay_us; // phase delay in unit of micro second uint8_t reserved; uint32_t gpio_mask_val; // GPIO Mask value @@ -4507,8 +4507,8 @@ struct amd_acpi_description_header{ struct uefi_acpi_vfct{ struct amd_acpi_description_header sheader; uint8_t tableUUID[16]; //0x24 - uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. - uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. + uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the structure. + uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the structure. uint32_t reserved[4]; //0x3C }; @@ -4540,7 +4540,7 @@ struct gop_lib1_content { /* *************************************************************************** Scratch Register definitions - Each number below indicates which scratch regiser request, Active and + Each number below indicates which scratch register request, Active and Connect all share the same definitions as display_device_tag defines *************************************************************************** */ From 8f751e9376f56ab28e3a68d1abac9fd52d19bcef Mon Sep 17 00:00:00 2001 From: "Kavithesh A.S" Date: Sun, 24 Aug 2025 01:55:40 +0530 Subject: [PATCH 1789/2653] drm/amd/display: Document num_rmcm_3dluts in mpc_color_caps Fix a kernel-doc warning by documenting the num_rmcm_3dluts member of struct mpc_color_caps. v2: improve comment (Melissa) Signed-off-by: Kavithesh A.S Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 673e3c5a5257c..c8e3dbf37be34 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -234,6 +234,7 @@ struct lut3d_caps { * @ogam_ram: programmable out gamma LUT * @ocsc: output color space conversion matrix * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT + * @num_rmcm_3dluts: number of RMCM 3D LUTS; always assumes a preceding shaper LUT * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single * instance * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT From cd2e1e94a4999a926225fb8329b809b167239b41 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 24 Jul 2025 13:01:09 -0500 Subject: [PATCH 1790/2653] drm/amd/display: Attach privacy screen to DRM connector [WHY] If a system has a privacy screen advertised by a driver it should be included in the DRM connector for the eDP panel. [HOW] Detect statically declared privacy screens when creating eDP connector and attach privacy screen DRM properties. Reviewed-by: Harry Wentland Signed-off-by: Mario Limonciello Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 25 ++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5c7baf8e2fbfd..dcbd403108299 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -81,6 +81,7 @@ #include #include +#include #include #include #include @@ -8060,6 +8061,14 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, if (!crtc) return 0; + if (new_con_state->privacy_screen_sw_state != old_con_state->privacy_screen_sw_state) { + new_crtc_state = drm_atomic_get_crtc_state(state, crtc); + if (IS_ERR(new_crtc_state)) + return PTR_ERR(new_crtc_state); + + new_crtc_state->mode_changed = true; + } + if (new_con_state->colorspace != old_con_state->colorspace) { new_crtc_state = drm_atomic_get_crtc_state(state, crtc); if (IS_ERR(new_crtc_state)) @@ -8837,6 +8846,18 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, drm_connector_attach_content_protection_property(&aconnector->base); #endif } + + if (connector_type == DRM_MODE_CONNECTOR_eDP) { + struct drm_privacy_screen *privacy_screen; + + privacy_screen = drm_privacy_screen_get(adev_to_drm(adev)->dev, NULL); + if (!IS_ERR(privacy_screen)) { + drm_connector_attach_privacy_screen_provider(&aconnector->base, + privacy_screen); + } else if (PTR_ERR(privacy_screen) != -ENODEV) { + drm_warn(adev_to_drm(adev), "Error getting privacy-screen\n"); + } + } } static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, @@ -10589,7 +10610,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) unsigned long flags; bool wait_for_vblank = true; struct drm_connector *connector; - struct drm_connector_state *old_con_state, *new_con_state; + struct drm_connector_state *old_con_state = NULL, *new_con_state = NULL; struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; int crtc_disable_count = 0; @@ -10722,6 +10743,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) &stream_update); mutex_unlock(&dm->dc_lock); kfree(dummy_updates); + + drm_connector_update_privacy_screen(new_con_state); } /** From 1d5a1381fe4537a5f56d9849fa16f427377cb5ad Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 21 Aug 2025 13:48:49 +0800 Subject: [PATCH 1791/2653] drm/amdkcl: fake the drm/drm_privacy_screen_consumer.h header it's caused by b5a33ca93 "drm/amd/display: Attach privacy screen to DRM connector" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ include/kcl/header/drm/drm_privacy_screen_consumer.h | 9 +++++++++ 3 files changed, 18 insertions(+) create mode 100644 include/kcl/header/drm/drm_privacy_screen_consumer.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 68564156959b9..3a2dbf42612e4 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -399,6 +399,9 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DP_DRM_DP_MST_HELPER_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_PRIVACY_SCREEN_CONSUMER_H 1 + /* drm_dp_link_train_channel_eq_delay() has 2 args */ #define HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index bca9e1778fa23..3f4ae2301335a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -44,6 +44,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_aperture.h]) + dnl # + dnl # v5.15-rc1-290-ga1a98689301b + dnl # drm: Add privacy-screen class (v4) + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_privacy_screen_consumer.h]) + dnl # dnl # v5.16-rc5-872-g5b529e8d9c38 dnl # drm/dp: Move public DisplayPort headers into dp/ diff --git a/include/kcl/header/drm/drm_privacy_screen_consumer.h b/include/kcl/header/drm/drm_privacy_screen_consumer.h new file mode 100644 index 0000000000000..aa456f80dd3c6 --- /dev/null +++ b/include/kcl/header/drm/drm_privacy_screen_consumer.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_PRIVACY_SCREEN_CONSUMER_H_H_ +#define _KCL_HEADER_DRM_PRIVACY_SCREEN_CONSUMER_H_H_ + +#ifdef HAVE_DRM_DRM_PRIVACY_SCREEN_CONSUMER_H +#include_next +#endif + +#endif From 7a8a56941c537360b5a79084021a1d6429186a4d Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 21 Aug 2025 15:54:41 +0800 Subject: [PATCH 1792/2653] drm/amdkcl: wrap code under HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN old kernel doesn't enable CONFIG_DRM_PRIVACY_SCREEN, so bypass this feature by HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN it's caused by b5a33ca934120fdc "drm/amd/display: Attach privacy screen to DRM connector" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++++++---- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm_privacy_screen.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 27 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_privacy_screen.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index dcbd403108299..cf560b9505ce0 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8060,7 +8060,7 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, if (!crtc) return 0; - +#ifdef HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN if (new_con_state->privacy_screen_sw_state != old_con_state->privacy_screen_sw_state) { new_crtc_state = drm_atomic_get_crtc_state(state, crtc); if (IS_ERR(new_crtc_state)) @@ -8068,7 +8068,7 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, new_crtc_state->mode_changed = true; } - +#endif if (new_con_state->colorspace != old_con_state->colorspace) { new_crtc_state = drm_atomic_get_crtc_state(state, crtc); if (IS_ERR(new_crtc_state)) @@ -8846,7 +8846,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, drm_connector_attach_content_protection_property(&aconnector->base); #endif } - +#ifdef HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN if (connector_type == DRM_MODE_CONNECTOR_eDP) { struct drm_privacy_screen *privacy_screen; @@ -8858,6 +8858,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, drm_warn(adev_to_drm(adev), "Error getting privacy-screen\n"); } } +#endif } static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, @@ -10743,8 +10744,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) &stream_update); mutex_unlock(&dm->dc_lock); kfree(dummy_updates); - +#ifdef HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN drm_connector_update_privacy_screen(new_con_state); +#endif } /** diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3a2dbf42612e4..a7a6673c64457 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -284,6 +284,9 @@ /* struct drm_connector_state has hdr_output_metadata member */ #define HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA 1 +/* drm_connector_update_privacy_screen() is available */ +#define HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN 1 + /* drm_connector_attach_colorspace_property() is available */ #define HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_privacy_screen.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_privacy_screen.m4 new file mode 100644 index 0000000000000..8636cef864a78 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_privacy_screen.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.15-rc1-293-g334f74ee85dc +dnl # drm/connector: Add a drm_connector privacy-screen helper functions (v2) +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_connector_state *drm_con_state = NULL; + drm_connector_update_privacy_screen(drm_con_state); + ], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN, 1, + [drm_connector_update_privacy_screen() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 353d0722b9a52..de6d794e90432 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -289,6 +289,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_INIT64 AC_AMDGPU_DRM_FILE_DEBUGFS_CLIENT AC_AMDGPU_DRM_VBLANK_CRTC_STRUCT_CONFIG + AC_AMDGPU_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 7f69d6dcabf1f548d54a5f5a68d5c934f16e3023 Mon Sep 17 00:00:00 2001 From: Qianfeng Rong Date: Sat, 16 Aug 2025 22:23:05 +0800 Subject: [PATCH 1793/2653] drm/amd/display: use max() to improve code Use max() to reduce the code and improve readability. No functional changes. Signed-off-by: Qianfeng Rong Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 7 ++----- .../gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 6 +----- .../amd/display/dc/dml2/dml21/dml21_translation_helper.c | 6 +----- 3 files changed, 4 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 084994c650c4c..8376e2b0e73dd 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -1047,11 +1047,8 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) &num_entries_per_clk->num_fclk_levels); clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK); - if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) { - num_levels = num_entries_per_clk->num_memclk_levels; - } else { - num_levels = num_entries_per_clk->num_fclk_levels; - } + num_levels = max(num_entries_per_clk->num_memclk_levels, num_entries_per_clk->num_fclk_levels); + clk_mgr_base->bw_params->max_memclk_mhz = clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz; clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1; diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c index b597034671288..47ff4c965d767 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c @@ -1404,11 +1404,7 @@ static void dcn401_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_fclk_levels - 1].fclk_mhz) clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = 0; - if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) { - num_levels = num_entries_per_clk->num_memclk_levels; - } else { - num_levels = num_entries_per_clk->num_fclk_levels; - } + num_levels = max(num_entries_per_clk->num_memclk_levels, num_entries_per_clk->num_fclk_levels); clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c index 23fdb17f851a3..d6c77d96e4f70 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c @@ -463,11 +463,7 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf (stream->timing.h_total * (long long)calc_max_hardware_v_total(stream))); } - if (stream->timing.min_refresh_in_uhz > min_hardware_refresh_in_uhz) { - timing->drr_config.min_refresh_uhz = stream->timing.min_refresh_in_uhz; - } else { - timing->drr_config.min_refresh_uhz = min_hardware_refresh_in_uhz; - } + timing->drr_config.min_refresh_uhz = max(stream->timing.min_refresh_in_uhz, min_hardware_refresh_in_uhz); if (dml_ctx->config.callbacks.get_max_flickerless_instant_vtotal_increase && stream->ctx->dc->config.enable_fpo_flicker_detection == 1) From e6fbeb9615d83927b0df522635b185b749bb32df Mon Sep 17 00:00:00 2001 From: "David (Ming Qiang) Wu" Date: Mon, 25 Aug 2025 15:15:42 -0400 Subject: [PATCH 1794/2653] drm/amdgpu/vcn: remove unused code in vcn_v4_0.c Reviewed-by: Alex Deucher Signed-off-by: David (Ming Qiang) Wu --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 1785786a72f8e..d0d27790b73b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -1621,7 +1621,6 @@ static int vcn_v4_0_stop(struct amdgpu_vcn_inst *vinst) if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { vcn_v4_0_stop_dpg_mode(vinst); - r = 0; goto done; } From 7c5845654db4322799fac9fcc4eda53cf0e14a7c Mon Sep 17 00:00:00 2001 From: "David (Ming Qiang) Wu" Date: Mon, 25 Aug 2025 15:42:23 -0400 Subject: [PATCH 1795/2653] drm/amdgpu/vcn: add instance number to VCN version message For multiple VCN instances case we get multiple lines of the same message like below: amdgpu 0000:43:00.0: amdgpu: Found VCN firmware Version ENC: 1.24 DEC: 9 VEP: 0 Revision: 11 amdgpu 0000:43:00.0: amdgpu: Found VCN firmware Version ENC: 1.24 DEC: 9 VEP: 0 Revision: 11 By adding instance number to the log message for multiple VCN instances, each line will clearly indicate which VCN instance it refers to. Reviewed-by: Alex Deucher Signed-off-by: David (Ming Qiang) Wu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index fd8ebf4b5a824..5a90abcea0ac1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -185,16 +185,16 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int i) dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf; vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf; dev_info(adev->dev, - "Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", - enc_major, enc_minor, dec_ver, vep, fw_rev); + "[VCN instance %d] Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n", + i, enc_major, enc_minor, dec_ver, vep, fw_rev); } else { unsigned int version_major, version_minor, family_id; family_id = le32_to_cpu(hdr->ucode_version) & 0xff; version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; - dev_info(adev->dev, "Found VCN firmware Version: %u.%u Family ID: %u\n", - version_major, version_minor, family_id); + dev_info(adev->dev, "[VCN instance %d] Found VCN firmware Version: %u.%u Family ID: %u\n", + i, version_major, version_minor, family_id); } bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; From c67690048f235779bd18fc74a3f25b6d54cfc3a7 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Mon, 25 Aug 2025 09:38:32 +0800 Subject: [PATCH 1796/2653] drm/amd/amdgpu: unified amdgpu ip block name v1: 1. Unified amdgpu ip block name print with format "{ip_type}_v{major}_{minor}_{rev}" 2. Avoid IP block name conflicts for SMU/PSP ip block v2: Update IP block print format to keep legacy IP block name (Alex) "{ip_type}_v{major}_{minor}_{rev} ({funcs->name})" Signed-off-by: Yang Wang Reviewed-by: Asad Kamal Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 36 ++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 5ae0ebd6da45f..0194b8e661838 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2472,6 +2472,33 @@ int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, return 1; } +static const char *ip_block_names[] = { + [AMD_IP_BLOCK_TYPE_COMMON] = "common", + [AMD_IP_BLOCK_TYPE_GMC] = "gmc", + [AMD_IP_BLOCK_TYPE_IH] = "ih", + [AMD_IP_BLOCK_TYPE_SMC] = "smu", + [AMD_IP_BLOCK_TYPE_PSP] = "psp", + [AMD_IP_BLOCK_TYPE_DCE] = "dce", + [AMD_IP_BLOCK_TYPE_GFX] = "gfx", + [AMD_IP_BLOCK_TYPE_SDMA] = "sdma", + [AMD_IP_BLOCK_TYPE_UVD] = "uvd", + [AMD_IP_BLOCK_TYPE_VCE] = "vce", + [AMD_IP_BLOCK_TYPE_ACP] = "acp", + [AMD_IP_BLOCK_TYPE_VCN] = "vcn", + [AMD_IP_BLOCK_TYPE_MES] = "mes", + [AMD_IP_BLOCK_TYPE_JPEG] = "jpeg", + [AMD_IP_BLOCK_TYPE_VPE] = "vpe", + [AMD_IP_BLOCK_TYPE_UMSCH_MM] = "umsch_mm", + [AMD_IP_BLOCK_TYPE_ISP] = "isp", +}; + +static const char *ip_block_name(struct amdgpu_device *adev, enum amd_ip_block_type type) +{ + int idx = (int)type; + + return idx < ARRAY_SIZE(ip_block_names) ? ip_block_names[idx] : "unknown"; +} + /** * amdgpu_device_ip_block_add * @@ -2500,8 +2527,13 @@ int amdgpu_device_ip_block_add(struct amdgpu_device *adev, break; } - dev_info(adev->dev, "detected ip block number %d <%s>\n", - adev->num_ip_blocks, ip_block_version->funcs->name); + dev_info(adev->dev, "detected ip block number %d <%s_v%d_%d_%d> (%s)\n", + adev->num_ip_blocks, + ip_block_name(adev, ip_block_version->type), + ip_block_version->major, + ip_block_version->minor, + ip_block_version->rev, + ip_block_version->funcs->name); adev->ip_blocks[adev->num_ip_blocks].adev = adev; From 3f390b130410b2f834b3759ef49ad7565eeb3aa5 Mon Sep 17 00:00:00 2001 From: Mangesh Gadre Date: Mon, 25 Aug 2025 21:18:42 +0800 Subject: [PATCH 1797/2653] drm/amdgpu: Avoid jpeg v5.0.1 poison irq call trace on sriov guest Sriov guest side doesn't init ras feature hence the poison irq shouldn't be put during hw fini Signed-off-by: Mangesh Gadre Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c index a2d781898767e..47bde62b39099 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c @@ -315,7 +315,7 @@ static int jpeg_v5_0_1_hw_fini(struct amdgpu_ip_block *ip_block) ret = jpeg_v5_0_1_set_powergating_state(ip_block, AMD_PG_STATE_GATE); } - if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) + if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG) && !amdgpu_sriov_vf(adev)) amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0); return ret; From 5905294ac32fc3a9082158bd5e9e57f862ada8f2 Mon Sep 17 00:00:00 2001 From: Mangesh Gadre Date: Mon, 25 Aug 2025 21:22:30 +0800 Subject: [PATCH 1798/2653] drm/amdgpu: Avoid vcn v5.0.1 poison irq call trace on sriov guest Sriov guest side doesn't init ras feature hence the poison irq shouldn't be put during hw fini Signed-off-by: Mangesh Gadre Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c index 7cb21e2b4eb0e..4b01e35ad7ef5 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c @@ -326,7 +326,7 @@ static int vcn_v5_0_1_hw_fini(struct amdgpu_ip_block *ip_block) vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); } - if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) + if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN) && !amdgpu_sriov_vf(adev)) amdgpu_irq_put(adev, &adev->vcn.inst->ras_poison_irq, 0); return 0; From 11bc4ebeb1da93a782457ac959f1e08d97719199 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 14 Aug 2025 13:52:50 +0530 Subject: [PATCH 1799/2653] drm/amdgpu: Check vcn state before profile switch The patch uses power state of VCN instances for requesting video profile. In idle worker of a vcn instance, when there is no outstanding submisssion or fence, the instance is put to power gated state. When all instances are powered off that means video profile is no longer required. A request is made to turn off video profile. A job submission starts with begin_use of ring, and at that time vcn instance state is changed to power on. Subsequently a check is made for active video profile, and if not active, a request is made. Signed-off-by: Lijo Lazar Reviewed-by: Sathishkumar S Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 80 ++++++++++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 3 + drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 27 +-------- 3 files changed, 56 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 5a90abcea0ac1..ad415203d245d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -408,6 +408,54 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev, int i) return 0; } +void amdgpu_vcn_get_profile(struct amdgpu_device *adev) +{ + int r; + + mutex_lock(&adev->vcn.workload_profile_mutex); + + if (adev->vcn.workload_profile_active) { + mutex_unlock(&adev->vcn.workload_profile_mutex); + return; + } + r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, + true); + if (r) + dev_warn(adev->dev, + "(%d) failed to enable video power profile mode\n", r); + else + adev->vcn.workload_profile_active = true; + mutex_unlock(&adev->vcn.workload_profile_mutex); +} + +void amdgpu_vcn_put_profile(struct amdgpu_device *adev) +{ + bool pg = true; + int r, i; + + mutex_lock(&adev->vcn.workload_profile_mutex); + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.inst[i].cur_state != AMD_PG_STATE_GATE) { + pg = false; + break; + } + } + + if (pg) { + r = amdgpu_dpm_switch_power_profile( + adev, PP_SMC_POWER_PROFILE_VIDEO, false); + if (r) + dev_warn( + adev->dev, + "(%d) failed to disable video power profile mode\n", + r); + else + adev->vcn.workload_profile_active = false; + } + + mutex_unlock(&adev->vcn.workload_profile_mutex); +} + static void amdgpu_vcn_idle_work_handler(struct work_struct *work) { struct amdgpu_vcn_inst *vcn_inst = @@ -415,7 +463,6 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work) struct amdgpu_device *adev = vcn_inst->adev; unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; unsigned int i = vcn_inst->inst, j; - int r = 0; if (adev->vcn.harvest_config & (1 << i)) return; @@ -444,15 +491,8 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work) mutex_lock(&vcn_inst->vcn_pg_lock); vcn_inst->set_pg_state(vcn_inst, AMD_PG_STATE_GATE); mutex_unlock(&vcn_inst->vcn_pg_lock); - mutex_lock(&adev->vcn.workload_profile_mutex); - if (adev->vcn.workload_profile_active) { - r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, - false); - if (r) - dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); - adev->vcn.workload_profile_active = false; - } - mutex_unlock(&adev->vcn.workload_profile_mutex); + amdgpu_vcn_put_profile(adev); + } else { schedule_delayed_work(&vcn_inst->idle_work, VCN_IDLE_TIMEOUT); } @@ -462,30 +502,11 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; struct amdgpu_vcn_inst *vcn_inst = &adev->vcn.inst[ring->me]; - int r = 0; atomic_inc(&vcn_inst->total_submission_cnt); cancel_delayed_work_sync(&vcn_inst->idle_work); - /* We can safely return early here because we've cancelled the - * the delayed work so there is no one else to set it to false - * and we don't care if someone else sets it to true. - */ - if (adev->vcn.workload_profile_active) - goto pg_lock; - - mutex_lock(&adev->vcn.workload_profile_mutex); - if (!adev->vcn.workload_profile_active) { - r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, - true); - if (r) - dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); - adev->vcn.workload_profile_active = true; - } - mutex_unlock(&adev->vcn.workload_profile_mutex); - -pg_lock: mutex_lock(&vcn_inst->vcn_pg_lock); vcn_inst->set_pg_state(vcn_inst, AMD_PG_STATE_UNGATE); @@ -513,6 +534,7 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) vcn_inst->pause_dpg_mode(vcn_inst, &new_state); } mutex_unlock(&vcn_inst->vcn_pg_lock); + amdgpu_vcn_get_profile(adev); } void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index b3fb1d0e43fc9..6d9acd36041d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -565,4 +565,7 @@ int amdgpu_vcn_reg_dump_init(struct amdgpu_device *adev, const struct amdgpu_hwip_reg_entry *reg, u32 count); void amdgpu_vcn_dump_ip_state(struct amdgpu_ip_block *ip_block); void amdgpu_vcn_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p); +void amdgpu_vcn_get_profile(struct amdgpu_device *adev); +void amdgpu_vcn_put_profile(struct amdgpu_device *adev); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index 3a7c137a83efb..904b94bc8693c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -116,7 +116,6 @@ static void vcn_v2_5_idle_work_handler(struct work_struct *work) struct amdgpu_device *adev = vcn_inst->adev; unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; unsigned int i, j; - int r = 0; for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { struct amdgpu_vcn_inst *v = &adev->vcn.inst[i]; @@ -149,15 +148,7 @@ static void vcn_v2_5_idle_work_handler(struct work_struct *work) if (!fences && !atomic_read(&adev->vcn.inst[0].total_submission_cnt)) { amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, AMD_PG_STATE_GATE); - mutex_lock(&adev->vcn.workload_profile_mutex); - if (adev->vcn.workload_profile_active) { - r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, - false); - if (r) - dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); - adev->vcn.workload_profile_active = false; - } - mutex_unlock(&adev->vcn.workload_profile_mutex); + amdgpu_vcn_put_profile(adev); } else { schedule_delayed_work(&adev->vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT); } @@ -167,7 +158,6 @@ static void vcn_v2_5_ring_begin_use(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; struct amdgpu_vcn_inst *v = &adev->vcn.inst[ring->me]; - int r = 0; atomic_inc(&adev->vcn.inst[0].total_submission_cnt); @@ -177,20 +167,6 @@ static void vcn_v2_5_ring_begin_use(struct amdgpu_ring *ring) * the delayed work so there is no one else to set it to false * and we don't care if someone else sets it to true. */ - if (adev->vcn.workload_profile_active) - goto pg_lock; - - mutex_lock(&adev->vcn.workload_profile_mutex); - if (!adev->vcn.workload_profile_active) { - r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, - true); - if (r) - dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); - adev->vcn.workload_profile_active = true; - } - mutex_unlock(&adev->vcn.workload_profile_mutex); - -pg_lock: mutex_lock(&adev->vcn.inst[0].vcn_pg_lock); amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, AMD_PG_STATE_UNGATE); @@ -218,6 +194,7 @@ static void vcn_v2_5_ring_begin_use(struct amdgpu_ring *ring) v->pause_dpg_mode(v, &new_state); } mutex_unlock(&adev->vcn.inst[0].vcn_pg_lock); + amdgpu_vcn_get_profile(adev); } static void vcn_v2_5_ring_end_use(struct amdgpu_ring *ring) From af6f837d59a5b23077f01ee7179b9c228f707ffb Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 18 Aug 2025 11:44:28 +0530 Subject: [PATCH 1800/2653] drm/amd/pm: Make use of __free for cleanup Use __free(kfree) for memory alloc cleanups in SMUv13.0.6 Signed-off-by: Lijo Lazar Reviewed-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 63 ++++++++----------- 1 file changed, 25 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index d59e406748913..ff197134fafe8 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -546,6 +546,9 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; + void *gpu_metrics_table __free(kfree) = NULL; + void *driver_pptable __free(kfree) = NULL; + void *metrics_table __free(kfree) = NULL; struct amdgpu_device *adev = smu->adev; int gpu_metrcs_size = METRICS_TABLE_SIZE; int ret; @@ -564,37 +567,32 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu) PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT); - smu_table->metrics_table = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL); - if (!smu_table->metrics_table) + metrics_table = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL); + if (!metrics_table) return -ENOMEM; smu_table->metrics_time = 0; smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_8); - smu_table->gpu_metrics_table = + gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); - if (!smu_table->gpu_metrics_table) { - kfree(smu_table->metrics_table); + if (!gpu_metrics_table) return -ENOMEM; - } - smu_table->driver_pptable = - kzalloc(sizeof(struct PPTable_t), GFP_KERNEL); - if (!smu_table->driver_pptable) { - kfree(smu_table->metrics_table); - kfree(smu_table->gpu_metrics_table); + driver_pptable = kzalloc(sizeof(struct PPTable_t), GFP_KERNEL); + if (!driver_pptable) return -ENOMEM; - } if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) { ret = smu_v13_0_12_tables_init(smu); - if (ret) { - kfree(smu_table->metrics_table); - kfree(smu_table->gpu_metrics_table); + if (ret) return ret; - } } + smu_table->gpu_metrics_table = no_free_ptr(gpu_metrics_table); + smu_table->metrics_table = no_free_ptr(metrics_table); + smu_table->driver_pptable = no_free_ptr(driver_pptable); + return 0; } @@ -2781,9 +2779,9 @@ static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id, const u8 num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3; int version = smu_v13_0_6_get_metrics_version(smu); struct amdgpu_partition_metrics_v1_0 *xcp_metrics; + MetricsTableV0_t *metrics_v0 __free(kfree) = NULL; struct amdgpu_device *adev = smu->adev; int ret, inst, i, j, k, idx; - MetricsTableV0_t *metrics_v0; MetricsTableV1_t *metrics_v1; MetricsTableV2_t *metrics_v2; struct amdgpu_xcp *xcp; @@ -2808,17 +2806,14 @@ static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id, return -ENOMEM; ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, false); - if (ret) { - kfree(metrics_v0); + if (ret) return ret; - } if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) && - smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) { - ret = smu_v13_0_12_get_xcp_metrics(smu, xcp, table, metrics_v0); - goto out; - } + smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) + return smu_v13_0_12_get_xcp_metrics(smu, xcp, table, + metrics_v0); metrics_v1 = (MetricsTableV1_t *)metrics_v0; metrics_v2 = (MetricsTableV2_t *)metrics_v0; @@ -2889,8 +2884,6 @@ static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id, idx++; } } -out: - kfree(metrics_v0); return sizeof(*xcp_metrics); } @@ -2901,31 +2894,26 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table struct gpu_metrics_v1_8 *gpu_metrics = (struct gpu_metrics_v1_8 *)smu_table->gpu_metrics_table; int version = smu_v13_0_6_get_metrics_version(smu); + MetricsTableV0_t *metrics_v0 __free(kfree) = NULL; int ret = 0, xcc_id, inst, i, j, k, idx; struct amdgpu_device *adev = smu->adev; - MetricsTableV0_t *metrics_v0; MetricsTableV1_t *metrics_v1; MetricsTableV2_t *metrics_v2; struct amdgpu_xcp *xcp; u16 link_width_level; - ssize_t num_bytes; u8 num_jpeg_rings; u32 inst_mask; bool per_inst; metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL); ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, false); - if (ret) { - kfree(metrics_v0); + if (ret) return ret; - } - if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) && - smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) { - num_bytes = smu_v13_0_12_get_gpu_metrics(smu, table, metrics_v0); - kfree(metrics_v0); - return num_bytes; - } + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == + IP_VERSION(13, 0, 12) && + smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) + return smu_v13_0_12_get_gpu_metrics(smu, table, metrics_v0); metrics_v1 = (MetricsTableV1_t *)metrics_v0; metrics_v2 = (MetricsTableV2_t *)metrics_v0; @@ -3111,7 +3099,6 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, version); *table = (void *)gpu_metrics; - kfree(metrics_v0); return sizeof(*gpu_metrics); } From 4bee7edbadb96359a98c272f1bcd2925865b2fd2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 27 Aug 2025 14:24:31 -0400 Subject: [PATCH 1801/2653] drm/amdgpu/mes11: make MES_MISC_OP_CHANGE_CONFIG failure non-fatal If the firmware is too old, just warn and return success. Fixes: 27b791514789 ("drm/amdgpu/mes: keep enforce isolation up to date") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4414 Cc: shaoyun.Liu@amd.com Reviewed-by: Shaoyun.liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 28eb846280dd4..3f6a828cad8ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -641,8 +641,9 @@ static int mes_v11_0_misc_op(struct amdgpu_mes *mes, break; case MES_MISC_OP_CHANGE_CONFIG: if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) < 0x63) { - dev_err(mes->adev->dev, "MES FW version must be larger than 0x63 to support limit single process feature.\n"); - return -EINVAL; + dev_warn_once(mes->adev->dev, + "MES FW version must be larger than 0x63 to support limit single process feature.\n"); + return 0; } misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; misc_pkt.change_config.opcode = From 5089ea63cfb0c2b1d91aa99aa2a28990cec8c142 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 28 Aug 2025 09:37:05 -0500 Subject: [PATCH 1802/2653] drm/amd: Re-enable common modes for eDP and LVDS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [Why] Although compositors will add their own modes, Xorg won't use it's own modes and will only stick to modes advertised by the driver. This mean a user that used to pick 1024x768 could no longer access it unless the panel's native resolution was 1024x768. [How] Revert commit 6d396e7ac1ce3 ("drm/amd/display: Disable common modes for LVDS") and commit 7948afb46af92 ("drm/amd/display: Disable common modes for eDP"). The panel will still use scaling for any non-native modes due to commit 978fa2f6d0b12 ("drm/amd/display: Use scaling for non-native resolutions on eDP") Reported-by: Marek Marczykowski-Górecki Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4538 Acked-by: Alex Deucher Link: https://lore.kernel.org/r/20250828140856.2887993-1-superm1@kernel.org Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index cf560b9505ce0..bda7e79ece062 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8715,8 +8715,7 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) #else amdgpu_dm_connector_ddc_get_modes(connector, edid); #endif - if (encoder && (connector->connector_type != DRM_MODE_CONNECTOR_eDP) && - (connector->connector_type != DRM_MODE_CONNECTOR_LVDS)) + if (encoder) amdgpu_dm_connector_add_common_modes(encoder, connector); #ifdef HAVE_DRM_DP_MST_EDID_READ amdgpu_dm_connector_add_freesync_modes(connector, drm_edid); From c09d2f3fff8910e9fce802a837a562e77038b648 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 6 Aug 2025 10:47:50 -0400 Subject: [PATCH 1803/2653] drm/amdgpu: drop hw access in non-DC audio fini We already disable the audio pins in hw_fini so there is no need to do it again in sw_fini. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4481 Cc: stable@vger.kernel.org Cc: oushixiong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 5 ----- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 5 ----- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 5 ----- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 5 ----- 4 files changed, 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 5257968894ad0..6cd4a619a2dce 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -1462,17 +1462,12 @@ static int dce_v10_0_audio_init(struct amdgpu_device *adev) static void dce_v10_0_audio_fini(struct amdgpu_device *adev) { - int i; - if (!amdgpu_audio) return; if (!adev->mode_info.audio.enabled) return; - for (i = 0; i < adev->mode_info.audio.num_pins; i++) - dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); - adev->mode_info.audio.enabled = false; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index a3236cb8691b2..577c10c1ad635 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -1511,17 +1511,12 @@ static int dce_v11_0_audio_init(struct amdgpu_device *adev) static void dce_v11_0_audio_fini(struct amdgpu_device *adev) { - int i; - if (!amdgpu_audio) return; if (!adev->mode_info.audio.enabled) return; - for (i = 0; i < adev->mode_info.audio.num_pins; i++) - dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); - adev->mode_info.audio.enabled = false; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index cc37c620ea074..4f0dee3f014b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -1451,17 +1451,12 @@ static int dce_v6_0_audio_init(struct amdgpu_device *adev) static void dce_v6_0_audio_fini(struct amdgpu_device *adev) { - int i; - if (!amdgpu_audio) return; if (!adev->mode_info.audio.enabled) return; - for (i = 0; i < adev->mode_info.audio.num_pins; i++) - dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); - adev->mode_info.audio.enabled = false; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index bd986a71868e4..201b9139bb583 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -1442,17 +1442,12 @@ static int dce_v8_0_audio_init(struct amdgpu_device *adev) static void dce_v8_0_audio_fini(struct amdgpu_device *adev) { - int i; - if (!amdgpu_audio) return; if (!adev->mode_info.audio.enabled) return; - for (i = 0; i < adev->mode_info.audio.num_pins; i++) - dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); - adev->mode_info.audio.enabled = false; } From 8d5d0d2219ee4db1a72715e34f249f632e31a995 Mon Sep 17 00:00:00 2001 From: Relja Vojvodic Date: Thu, 14 Aug 2025 11:33:22 -0400 Subject: [PATCH 1804/2653] drm/amd/display: Increase minimum clock for TMDS 420 with pipe splitting [Why] -Pipe splitting allows for clocks to be reduced, but when using TMDS 420, reduced clocks lead to missed clocks cycles on clock resyncing [How] -Impose a minimum clock when using TMDS 420 Reviewed-by: Chris Park Signed-off-by: Relja Vojvodic Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../src/dml2_core/dml2_core_dcn4_calcs.c | 28 +++++++++++++------ 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index b9cff21985110..bf62d42b3f78b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -1238,18 +1238,27 @@ static void CalculateDETBufferSize( static double CalculateRequiredDispclk( enum dml2_odm_mode ODMMode, - double PixelClock) + double PixelClock, + bool isTMDS420) { + double DispClk; if (ODMMode == dml2_odm_mode_combine_4to1) { - return PixelClock / 4.0; + DispClk = PixelClock / 4.0; } else if (ODMMode == dml2_odm_mode_combine_3to1) { - return PixelClock / 3.0; + DispClk = PixelClock / 3.0; } else if (ODMMode == dml2_odm_mode_combine_2to1) { - return PixelClock / 2.0; + DispClk = PixelClock / 2.0; } else { - return PixelClock; + DispClk = PixelClock; + } + + if (isTMDS420) { + double TMDS420MinPixClock = PixelClock / 2.0; + DispClk = math_max2(DispClk, TMDS420MinPixClock); } + + return DispClk; } static double TruncToValidBPP( @@ -4122,11 +4131,12 @@ static noinline_for_stack void CalculateODMMode( bool success; bool UseDSC = DSCEnable && (NumberOfDSCSlices > 0); enum dml2_odm_mode DecidedODMMode; + bool isTMDS420 = (OutFormat == dml2_420 && Output == dml2_hdmi); - SurfaceRequiredDISPCLKWithoutODMCombine = CalculateRequiredDispclk(dml2_odm_mode_bypass, PixelClock); - SurfaceRequiredDISPCLKWithODMCombineTwoToOne = CalculateRequiredDispclk(dml2_odm_mode_combine_2to1, PixelClock); - SurfaceRequiredDISPCLKWithODMCombineThreeToOne = CalculateRequiredDispclk(dml2_odm_mode_combine_3to1, PixelClock); - SurfaceRequiredDISPCLKWithODMCombineFourToOne = CalculateRequiredDispclk(dml2_odm_mode_combine_4to1, PixelClock); + SurfaceRequiredDISPCLKWithoutODMCombine = CalculateRequiredDispclk(dml2_odm_mode_bypass, PixelClock, isTMDS420); + SurfaceRequiredDISPCLKWithODMCombineTwoToOne = CalculateRequiredDispclk(dml2_odm_mode_combine_2to1, PixelClock, isTMDS420); + SurfaceRequiredDISPCLKWithODMCombineThreeToOne = CalculateRequiredDispclk(dml2_odm_mode_combine_3to1, PixelClock, isTMDS420); + SurfaceRequiredDISPCLKWithODMCombineFourToOne = CalculateRequiredDispclk(dml2_odm_mode_combine_4to1, PixelClock, isTMDS420); #ifdef __DML_VBA_DEBUG__ DML_LOG_VERBOSE("DML::%s: ODMUse = %d\n", __func__, ODMUse); DML_LOG_VERBOSE("DML::%s: Output = %d\n", __func__, Output); From e0b663285125f076f8fdfcfa69401f4f4adab4cd Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Tue, 19 Aug 2025 11:29:05 -0500 Subject: [PATCH 1805/2653] drm/amd/display: Optimize custom brightness curve interpolation [Why] Custom brightness curve works by walking through all data points one by one. When the brightness value is at either extreme this is a lot of data points to walk. This is especially noticeable when moving a brightness slider around how it can lag. [How] Bisect the data points to find the closest for interpolation. Reviewed-by: Alex Hung Signed-off-by: Mario Limonciello Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 64 +++++++++++-------- 1 file changed, 38 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index bda7e79ece062..eb54c6aa8582f 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4892,8 +4892,8 @@ static void convert_custom_brightness(const struct amdgpu_dm_backlight_caps *cap uint32_t *user_brightness) { u32 brightness = scale_input_to_fw(min, max, *user_brightness); - u8 prev_signal = 0, prev_lum = 0; - int i = 0; + u8 lower_signal, upper_signal, upper_lum, lower_lum, lum; + int left, right; if (amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE) return; @@ -4901,32 +4901,44 @@ static void convert_custom_brightness(const struct amdgpu_dm_backlight_caps *cap if (!caps->data_points) return; - /* choose start to run less interpolation steps */ - if (caps->luminance_data[caps->data_points/2].input_signal > brightness) - i = caps->data_points/2; - do { - u8 signal = caps->luminance_data[i].input_signal; - u8 lum = caps->luminance_data[i].luminance; + left = 0; + right = caps->data_points - 1; + while (left <= right) { + int mid = left + (right - left) / 2; + u8 signal = caps->luminance_data[mid].input_signal; - /* - * brightness == signal: luminance is percent numerator - * brightness < signal: interpolate between previous and current luminance numerator - * brightness > signal: find next data point - */ - if (brightness > signal) { - prev_signal = signal; - prev_lum = lum; - i++; - continue; + /* Exact match found */ + if (signal == brightness) { + lum = caps->luminance_data[mid].luminance; + goto scale; } - if (brightness < signal) - lum = prev_lum + DIV_ROUND_CLOSEST((lum - prev_lum) * - (brightness - prev_signal), - signal - prev_signal); - *user_brightness = scale_fw_to_input(min, max, - DIV_ROUND_CLOSEST(lum * brightness, 101)); - return; - } while (i < caps->data_points); + + if (signal < brightness) + left = mid + 1; + else + right = mid - 1; + } + + /* verify bound */ + if (left >= caps->data_points) + left = caps->data_points - 1; + + /* At this point, left > right */ + lower_signal = caps->luminance_data[right].input_signal; + upper_signal = caps->luminance_data[left].input_signal; + lower_lum = caps->luminance_data[right].luminance; + upper_lum = caps->luminance_data[left].luminance; + + /* interpolate */ + if (right == left || !lower_lum) + lum = upper_lum; + else + lum = lower_lum + DIV_ROUND_CLOSEST((upper_lum - lower_lum) * + (brightness - lower_signal), + upper_signal - lower_signal); +scale: + *user_brightness = scale_fw_to_input(min, max, + DIV_ROUND_CLOSEST(lum * brightness, 101)); } static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, From 120e8b47db61ad4e95cf3871a5ac13bed6266dad Mon Sep 17 00:00:00 2001 From: Clay King Date: Wed, 20 Aug 2025 15:04:29 -0400 Subject: [PATCH 1806/2653] drm/amd/display: incorrect conditions for failing dto calculations [Why & How] Previously, when calculating dto phase, we would incorrectly fail when phase <=0 without additionally checking for the integer value. This meant that calculations would incorrectly fail when the desired pixel clock was an exact multiple of the reference clock. Reviewed-by: Dillon Varone Signed-off-by: Clay King Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c index 668ee2d405fdf..0b8ed9b94d3c5 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c @@ -619,7 +619,7 @@ void dccg401_set_dp_dto( dto_integer = div_u64(params->pixclk_hz, dto_modulo_hz); dto_phase_hz = params->pixclk_hz - dto_integer * dto_modulo_hz; - if (dto_phase_hz <= 0) { + if (dto_phase_hz <= 0 && dto_integer <= 0) { /* negative pixel rate should never happen */ BREAK_TO_DEBUGGER(); return; From c23ea03de5b6b22024cc75e07b415255702ea61d Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Wed, 20 Aug 2025 15:46:52 -0400 Subject: [PATCH 1807/2653] drm/amd/display: Clear the CUR_ENABLE register on DCN314 w/out DPP PG [Why&How] ON DCN314, clearing DPP SW structure without power gating it can cause a double cursor in full screen with non-native scaling. A W/A that clears CURSOR0_CONTROL cursor_enable flag if dcn10_plane_atomic_power_down is called and DPP power gating is disabled. Reviewed-by: Sun peng (Leo) Li Signed-off-by: Ivan Lipski Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c | 9 +++ .../drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h | 2 + .../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 1 + .../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 72 +++++++++++++++++++ .../amd/display/dc/hwss/dcn314/dcn314_hwseq.h | 2 + .../amd/display/dc/hwss/dcn314/dcn314_init.c | 1 + drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 3 + 7 files changed, 90 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c index 75fb77bca83ba..01480a04f85ef 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c @@ -520,6 +520,15 @@ void dpp1_dppclk_control( REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0); } +void dpp_force_disable_cursor(struct dpp *dpp_base) +{ + struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); + + /* Force disable cursor */ + REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, 0); + dpp_base->pos.cur0_ctl.bits.cur0_enable = 0; +} + static const struct dpp_funcs dcn10_dpp_funcs = { .dpp_read_state = dpp_read_state, .dpp_reset = dpp_reset, diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h index c48139bed11f5..f466182963f75 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h @@ -1525,4 +1525,6 @@ void dpp1_construct(struct dcn10_dpp *dpp1, void dpp1_cm_get_gamut_remap(struct dpp *dpp_base, struct dpp_grph_csc_adjustment *adjust); +void dpp_force_disable_cursor(struct dpp *dpp_base); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c index 2d70586cef402..09be2a90cc79d 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c @@ -1494,6 +1494,7 @@ static struct dpp_funcs dcn30_dpp_funcs = { .dpp_dppclk_control = dpp1_dppclk_control, .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier, .dpp_get_gamut_remap = dpp3_cm_get_gamut_remap, + .dpp_force_disable_cursor = dpp_force_disable_cursor, }; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c index e68f21fd5f0fb..5609845339505 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c @@ -528,3 +528,75 @@ void dcn314_disable_link_output(struct dc_link *link, apply_symclk_on_tx_off_wa(link); } + +/** + * dcn314_dpp_pg_control - DPP power gate control. + * + * @hws: dce_hwseq reference. + * @dpp_inst: DPP instance reference. + * @power_on: true if we want to enable power gate, false otherwise. + * + * Enable or disable power gate in the specific DPP instance. + * If power gating is disabled, will force disable cursor in the DPP instance. + */ +void dcn314_dpp_pg_control( + struct dce_hwseq *hws, + unsigned int dpp_inst, + bool power_on) +{ + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + + + if (hws->ctx->dc->debug.disable_dpp_power_gate) { + /* Workaround for DCN314 with disabled power gating */ + if (!power_on) { + + /* Force disable cursor if power gating is disabled */ + struct dpp *dpp = hws->ctx->dc->res_pool->dpps[dpp_inst]; + if (dpp && dpp->funcs->dpp_force_disable_cursor) + dpp->funcs->dpp_force_disable_cursor(dpp); + } + return; + } + if (REG(DOMAIN1_PG_CONFIG) == 0) + return; + + switch (dpp_inst) { + case 0: /* DPP0 */ + REG_UPDATE(DOMAIN1_PG_CONFIG, + DOMAIN1_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN1_PG_STATUS, + DOMAIN1_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 1: /* DPP1 */ + REG_UPDATE(DOMAIN3_PG_CONFIG, + DOMAIN3_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN3_PG_STATUS, + DOMAIN3_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 2: /* DPP2 */ + REG_UPDATE(DOMAIN5_PG_CONFIG, + DOMAIN5_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN5_PG_STATUS, + DOMAIN5_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 3: /* DPP3 */ + REG_UPDATE(DOMAIN7_PG_CONFIG, + DOMAIN7_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN7_PG_STATUS, + DOMAIN7_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h index 2305ad282f218..6c072d0274ea3 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.h @@ -47,4 +47,6 @@ void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, void dcn314_disable_link_output(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal); +void dcn314_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on); + #endif /* __DC_HWSS_DCN314_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c index a99145a302306..79faab1125d40 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c @@ -142,6 +142,7 @@ static const struct hwseq_private_funcs dcn314_private_funcs = { .enable_power_gating_plane = dcn314_enable_power_gating_plane, .dpp_root_clock_control = dcn314_dpp_root_clock_control, .hubp_pg_control = dcn31_hubp_pg_control, + .dpp_pg_control = dcn314_dpp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn314_update_odm, .dsc_pg_control = dcn314_dsc_pg_control, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h index 0c5675d1c5936..1b7c085dc2cc1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h @@ -349,6 +349,9 @@ struct dpp_funcs { struct dpp *dpp_base, enum dc_color_space color_space, struct dc_csc_transform cursor_csc_color_matrix); + + void (*dpp_force_disable_cursor)(struct dpp *dpp_base); + }; From 540bb15535b8349e1d6aa2e9595e50833294ac3f Mon Sep 17 00:00:00 2001 From: Fangzhi Zuo Date: Thu, 14 Aug 2025 14:41:44 -0400 Subject: [PATCH 1808/2653] drm/amd/display: Skip Check Runtime Link Setting for Specific Branch Device [why] Read link setting inside mode validation is not always the final downlink setting. It is found true in Synaptics branch device. At bootup, the preferred mode being set right after 1080p is set. It occurred before graphic load. That modeset switch in a short period of time makes the branch device switch back and forth from lower and higher link rate, observed at Synaptics branch device. DP2 RTK hub on the other hand, sticks to highest available downlink rate after bootup. Existing check of runtime downlink setting in mode validation shows asynchronous at branch device link switch, i.e., downlink switch to higher link rate not yet complete when the mode validation tries to probe the downlink setting. That makes mode validation checking downlink setting making wrong decision by pruning modes that should pass the validation after the downlink setting switch is complete. [how] If Synaptics is found at the last branch, skip checking downlink setting at mode validation. Reviewed-by: Wayne Lin Signed-off-by: Fangzhi Zuo Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 3 ++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 40 ++++++++++++++++++- 2 files changed, 41 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index a91725db4bcf6..90315bc290cd5 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -779,6 +779,9 @@ struct amdgpu_dm_connector { uint16_t vc_full_pbn; struct mutex handle_mst_msg_ready; + /* branch device specific data */ + uint32_t branch_ieee_oui; + /* TODO see if we can merge with ddc_bus or make a dm_connector */ struct amdgpu_i2c_adapter *i2c; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index d563e55bbf515..18b7ffe84ef1a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -370,6 +370,34 @@ static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnect return true; } +static bool retrieve_branch_specific_data(struct amdgpu_dm_connector *aconnector) +{ + struct drm_connector *connector = &aconnector->base; + struct drm_dp_mst_port *port = aconnector->mst_output_port; + struct drm_dp_mst_port *port_parent; + struct drm_dp_aux *immediate_upstream_aux; + struct drm_dp_desc branch_desc; + + if (!port->parent) + return false; + + port_parent = port->parent->port_parent; + + immediate_upstream_aux = port_parent ? &port_parent->aux : port->mgr->aux; + + if (drm_dp_read_desc(immediate_upstream_aux, &branch_desc, true)) + return false; + + aconnector->branch_ieee_oui = (branch_desc.ident.oui[0] << 16) + + (branch_desc.ident.oui[1] << 8) + + (branch_desc.ident.oui[2]); + + drm_dbg_dp(port->aux.drm_dev, "MST branch oui 0x%x detected at %s\n", + aconnector->branch_ieee_oui, connector->name); + + return true; +} + static int dm_dp_mst_get_modes(struct drm_connector *connector) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); @@ -787,6 +815,9 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, #endif drm_connector_set_path_property(connector, pathprop); + if (!retrieve_branch_specific_data(aconnector)) + aconnector->branch_ieee_oui = 0; + /* * Initialize connector state before adding the connectror to drm and * framebuffer lists @@ -2058,6 +2089,9 @@ static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_lin link_bw_set = data[DP_LINK_BW_SET - DP_LINK_BW_SET]; lane_count.raw = data[DP_LANE_COUNT_SET - DP_LINK_BW_SET]; + drm_dbg_dp(aux->drm_dev, "MST_DSC downlink setting: %d, 0x%x x %d\n", + dp_link_encoding, link_bw_set, lane_count.bits.LANE_COUNT_SET); + switch (dp_link_encoding) { case DP_8b_10b_ENCODING: link_rate = link_bw_set; @@ -2155,8 +2189,10 @@ enum dc_status dm_dp_mst_is_port_support_mode( end_link_bw = aconnector->mst_local_bw; } - if (end_link_bw > 0 && stream_kbps > end_link_bw) { - DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link." + if (end_link_bw > 0 && + stream_kbps > end_link_bw && + aconnector->branch_ieee_oui != DP_BRANCH_DEVICE_ID_90CC24) { + DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link. " "Mode required bw can't fit into last link\n"); return DC_FAIL_BANDWIDTH_VALIDATE; } From da5d73b170b0850c21d58a8ad0b8502116280f7f Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 22 Aug 2025 16:13:17 -0400 Subject: [PATCH 1809/2653] drm/amd/display: [FW Promotion] Release 0.1.25.0 Signed-off-by: Taimur Hassan Signed-off-by: Alex Hung Reviewed-by: Aurabindo Pillai Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index b7d49a117fa7c..02a4a20e35601 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -2364,6 +2364,7 @@ struct dmub_cmd_fams2_global_config { union dmub_fams2_global_feature_config features; uint32_t recovery_timeout_us; uint32_t hwfq_flip_programming_delay_us; + uint32_t max_allow_to_target_delta_us; // how early DCN could assert P-State allow compared to the P-State target }; union dmub_cmd_fams2_config { @@ -4170,6 +4171,12 @@ enum replay_version { * Data passed from driver to FW in a DMUB_CMD___SET_REPLAY_VERSION command. */ struct dmub_cmd_replay_set_version_data { + /** + * Panel Instance. + * Panel instance to identify which psr_state to use + * Currently the support is only for 0 or 1 + */ + uint8_t panel_inst; /** * PSR version that FW should implement. */ @@ -4178,12 +4185,6 @@ struct dmub_cmd_replay_set_version_data { * PSR control version. */ uint8_t cmd_version; - /** - * Panel Instance. - * Panel instance to identify which psr_state to use - * Currently the support is only for 0 or 1 - */ - uint8_t panel_inst; /** * Explicit padding to 4 byte boundary. */ From bb2b9db7f8842e0be7357b3f5074b2f0b72f5e41 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 22 Aug 2025 16:17:11 -0500 Subject: [PATCH 1810/2653] drm/amd/display: Promote DC to 3.2.348 Summary: * Refactor bounding box values handling * Fix incorrect condition to fail dto clk calculation * Skip check downlink setting for a certain MST branch device * Fix double cursor issue on dcn314 Signed-off-by: Taimur Hassan Signed-off-by: Alex Hung Reviewed-by: Aurabindo Pillai Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index c8e3dbf37be34..8b2767bb40950 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.347" +#define DC_VER "3.2.348" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From abddec743cddb951910760b05cfaf6a2472d5a40 Mon Sep 17 00:00:00 2001 From: David Francis Date: Mon, 16 Jun 2025 09:47:42 -0400 Subject: [PATCH 1811/2653] drm/amdgpu: Add ioctl to get all gem handles for a process MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add new ioctl DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES. This ioctl returns a list of bos with their handles, sizes, and flags and domains. This ioctl is meant to be used during CRIU checkpoint and provide information needed to reconstruct the bos in CRIU restore. Userspace for this and the next change can be found at https://github.com/checkpoint-restore/criu/pull/2613 Signed-off-by: David Francis Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 79 +++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h | 2 + include/uapi/drm/amdgpu_drm.h | 34 +++++++++++ 4 files changed, 117 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 9b3c75446a68d..dbe59db44853c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3121,7 +3121,8 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_DGMA, amdgpu_gem_dgma_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) + DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), }; static struct drm_driver amdgpu_kms_driver = { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index dcc1b51e324b1..e9f1b8c0bbd21 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -1186,6 +1186,85 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, return r; } +/** + * drm_amdgpu_gem_list_handles_ioctl - get information about a process' buffer objects + * + * @dev: drm device pointer + * @data: drm_amdgpu_gem_list_handles + * @filp: drm file pointer + * + * num_entries is set as an input to the size of the entries array. + * num_entries is sent back as output as the number of bos in the process. + * If that number is larger than the size of the array, the ioctl must + * be retried. + * + * Returns: + * 0 for success, -errno for errors. + */ +int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + struct drm_amdgpu_gem_list_handles *args = data; + struct drm_amdgpu_gem_list_handles_entry *bo_entries; + struct drm_gem_object *gobj; + int id, ret = 0; + int bo_index = 0; + int num_bos = 0; + + spin_lock(&filp->table_lock); + idr_for_each_entry(&filp->object_idr, gobj, id) + num_bos += 1; + spin_unlock(&filp->table_lock); + + if (args->num_entries < num_bos) { + args->num_entries = num_bos; + return 0; + } + + if (num_bos == 0) { + args->num_entries = 0; + return 0; + } + + bo_entries = kvcalloc(num_bos, sizeof(*bo_entries), GFP_KERNEL); + if (!bo_entries) + return -ENOMEM; + + spin_lock(&filp->table_lock); + idr_for_each_entry(&filp->object_idr, gobj, id) { + struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); + struct drm_amdgpu_gem_list_handles_entry *bo_entry; + + if (bo_index >= num_bos) { + ret = -EAGAIN; + break; + } + + bo_entry = &bo_entries[bo_index]; + + bo_entry->size = amdgpu_bo_size(bo); + bo_entry->alloc_flags = bo->flags & AMDGPU_GEM_CREATE_SETTABLE_MASK; + bo_entry->preferred_domains = bo->preferred_domains; + bo_entry->gem_handle = id; + bo_entry->alignment = bo->tbo.page_alignment; + + if (bo->tbo.base.import_attach) + bo_entry->flags |= AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT; + + bo_index += 1; + } + spin_unlock(&filp->table_lock); + + args->num_entries = bo_index; + + if (!ret) + ret = copy_to_user(u64_to_user_ptr(args->entries), bo_entries, num_bos * sizeof(*bo_entries)); + + kvfree(bo_entries); + + return ret; +} + static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, int width, int cpp, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h index 6c45de02f4c7f..244e7935dcfd9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h @@ -69,6 +69,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); +int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index c188896a31ec8..b72228c0a9ad9 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -57,6 +57,7 @@ extern "C" { #define DRM_AMDGPU_USERQ 0x16 #define DRM_AMDGPU_USERQ_SIGNAL 0x17 #define DRM_AMDGPU_USERQ_WAIT 0x18 +#define DRM_AMDGPU_GEM_LIST_HANDLES 0x19 /* not upstream */ #define DRM_AMDGPU_GEM_DGMA 0x5c @@ -82,6 +83,7 @@ extern "C" { #define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq) #define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal) #define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait) +#define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles) #define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma) @@ -871,6 +873,38 @@ struct drm_amdgpu_gem_op { __u64 value; }; +#define AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT (1 << 0) + +struct drm_amdgpu_gem_list_handles { + /* User pointer to array of drm_amdgpu_gem_bo_info_entry */ + __u64 entries; + + /* Size of entries buffer / Number of handles in process (if larger than size of buffer, must retry) */ + __u32 num_entries; + + __u32 padding; +}; + +struct drm_amdgpu_gem_list_handles_entry { + /* gem handle of buffer object */ + __u32 gem_handle; + + /* Currently just one flag: IS_IMPORT */ + __u32 flags; + + /* Size of bo */ + __u64 size; + + /* Preferred domains for GEM_CREATE */ + __u64 preferred_domains; + + /* GEM_CREATE flags for re-creation of buffer */ + __u64 alloc_flags; + + /* physical start_addr alignment in bytes for some HW requirements */ + __u64 alignment; +}; + #define AMDGPU_VA_OP_MAP 1 #define AMDGPU_VA_OP_UNMAP 2 #define AMDGPU_VA_OP_CLEAR 3 From c7b1fa0eeb724ec488f7cf664b19012749976e21 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Wed, 27 Aug 2025 13:29:17 +0800 Subject: [PATCH 1812/2653] drm/amdgpu/sdma: bump firmware version checks for user queue support Using the previous firmware could lead to problems with PROTECTED_FENCE_SIGNAL commands, specifically causing register conflicts between MCU_DBG0 and MCU_DBG1. The updated firmware versions ensure proper alignment and unification of the SDMA_SUBOP_PROTECTED_FENCE_SIGNAL value with SDMA 7.x, resolving these hardware coordination issues Fixes: 604d44879707 ("drm/amdgpu/sdma6: add ucode version checks for userq support") Acked-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index e9f9e44f75032..0e2f8cd0b5ceb 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1377,7 +1377,7 @@ static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block) switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { case IP_VERSION(6, 0, 0): - if ((adev->sdma.instance[0].fw_version >= 24) && !adev->sdma.disable_uq) + if ((adev->sdma.instance[0].fw_version >= 27) && !adev->sdma.disable_uq) adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; break; case IP_VERSION(6, 0, 1): @@ -1385,11 +1385,11 @@ static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block) adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; break; case IP_VERSION(6, 0, 2): - if ((adev->sdma.instance[0].fw_version >= 21) && !adev->sdma.disable_uq) + if ((adev->sdma.instance[0].fw_version >= 23) && !adev->sdma.disable_uq) adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; break; case IP_VERSION(6, 0, 3): - if ((adev->sdma.instance[0].fw_version >= 25) && !adev->sdma.disable_uq) + if ((adev->sdma.instance[0].fw_version >= 27) && !adev->sdma.disable_uq) adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; break; case IP_VERSION(6, 1, 0): From 95fe06aa40cb313079bed5886ce56b04b0e181ea Mon Sep 17 00:00:00 2001 From: Yang Su Date: Mon, 1 Sep 2025 12:18:56 +0800 Subject: [PATCH 1813/2653] drm/amdkcl: fix conflict of the __cmp macro function The __cmp function varies significantly across different kernel versions, so rename to __kcl_cmp to avoid conflicts. Signed-off-by: Yang Su Reviewed-by: Chengjun Yao --- include/kcl/kcl_minmax.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/kcl/kcl_minmax.h b/include/kcl/kcl_minmax.h index 208a5a940b92e..21b3450c40efb 100644 --- a/include/kcl/kcl_minmax.h +++ b/include/kcl/kcl_minmax.h @@ -10,11 +10,11 @@ #endif #ifndef MIN -#define __cmp_op_min < +#define __kcl_cmp_op_min < -#define __cmp(op, x, y) ((x) __cmp_op_##op (y) ? (x) : (y)) +#define __kcl_cmp(op, x, y) ((x) __kcl_cmp_op_##op (y) ? (x) : (y)) -#define MIN(a, b) __cmp(min, a, b) +#define MIN(a, b) __kcl_cmp(min, a, b) #endif #endif /* _KCL_MINMAX_H */ From 6433ab5d3553d220355cff94a449489779113484 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Mon, 1 Sep 2025 12:22:43 +0800 Subject: [PATCH 1814/2653] drm/amdkcl: test whether no_free_ptr exist it's caused by 6614cce880 "drm/amd/pm: Make use of __free for cleanup" Signed-off-by: Yang Su Reviewed-by: Chengjun Yao --- include/kcl/kcl_cleanup.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/kcl/kcl_cleanup.h b/include/kcl/kcl_cleanup.h index 73ad9f618de67..2f62410fe1932 100644 --- a/include/kcl/kcl_cleanup.h +++ b/include/kcl/kcl_cleanup.h @@ -35,6 +35,23 @@ static inline _type class_##_name##_constructor(_init_args) \ for (CLASS(_name, scope)(args), \ *done = NULL; __guard_ptr(_name)(&scope) && !done; done = (void *)1) +#ifndef no_free_ptr +#define __get_and_null(p, nullvalue) \ + ({ \ + __auto_type __ptr = &(p); \ + __auto_type __val = *__ptr; \ + *__ptr = nullvalue; \ + __val; \ + }) + +static inline __must_check +const volatile void * __must_check_fn(const volatile void *val) +{ return val; } + +#define no_free_ptr(p) \ + ((typeof(p)) __must_check_fn((__force const volatile void *)__get_and_null(p, NULL))) +#endif + #endif #endif /* KCL_CLEANUP_H_ */ From f071338979e1fa830d54720de219bce39811917b Mon Sep 17 00:00:00 2001 From: Yang Su Date: Mon, 1 Sep 2025 15:07:59 +0800 Subject: [PATCH 1815/2653] drm/amdkcl: wrap code under HAVE_DRM_DP_AUX_DRM_DEV it's caused by 540bb15535b834 "drm/amd/display: Skip Check Runtime Link Setting for Specific Branch Device" Signed-off-by: Yang Su Reviewed-by: Chengjun Yao --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 18b7ffe84ef1a..d0143d3a5b280 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -392,8 +392,13 @@ static bool retrieve_branch_specific_data(struct amdgpu_dm_connector *aconnector (branch_desc.ident.oui[1] << 8) + (branch_desc.ident.oui[2]); +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(port->aux.drm_dev, "MST branch oui 0x%x detected at %s\n", aconnector->branch_ieee_oui, connector->name); +#else + DRM_DEBUG_KMS("MST branch oui 0x%x detected at %s\n", + aconnector->branch_ieee_oui, connector->name); +#endif return true; } @@ -2088,9 +2093,13 @@ static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_lin dp_link_encoding = data[DP_MAIN_LINK_CHANNEL_CODING_SET - DP_LINK_BW_SET]; link_bw_set = data[DP_LINK_BW_SET - DP_LINK_BW_SET]; lane_count.raw = data[DP_LANE_COUNT_SET - DP_LINK_BW_SET]; - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "MST_DSC downlink setting: %d, 0x%x x %d\n", dp_link_encoding, link_bw_set, lane_count.bits.LANE_COUNT_SET); +#else + DRM_DEBUG_KMS("MST_DSC downlink setting: %d, 0x%x x %d\n", + dp_link_encoding, link_bw_set, lane_count.bits.LANE_COUNT_SET); +#endif switch (dp_link_encoding) { case DP_8b_10b_ENCODING: From 60d4e349a3c27ae1b74e4e0b94139b344aed7740 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Tue, 2 Sep 2025 14:51:33 +0800 Subject: [PATCH 1816/2653] Revert "PM: hibernate: add new api pm_hibernate_is_recovering()" This reverts commit f38786f7339c55667132c26a37ab0e10d969d328. --- include/linux/suspend.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/linux/suspend.h b/include/linux/suspend.h index a2af3bbe49337..317ae31e89b37 100644 --- a/include/linux/suspend.h +++ b/include/linux/suspend.h @@ -426,8 +426,6 @@ int is_hibernate_resume_dev(dev_t dev); static inline int is_hibernate_resume_dev(dev_t dev) { return 0; } #endif -bool pm_hibernate_is_recovering(void); - /* Hibernation and suspend events */ #define PM_HIBERNATION_PREPARE 0x0001 /* Going to hibernate */ #define PM_POST_HIBERNATION 0x0002 /* Hibernation finished */ From f56eb918c855eeda38106a60681b27e02e0cd7bc Mon Sep 17 00:00:00 2001 From: Yang Su Date: Tue, 2 Sep 2025 14:51:42 +0800 Subject: [PATCH 1817/2653] Revert "drm/amdkcl: test whether pm_hibernate_is_recovering() exist" This reverts commit a15aed64cc48561eccafc118c0e6aa62107fa69d. --- drivers/gpu/drm/amd/amdkcl/kcl_suspend.c | 19 ------------------- include/kcl/kcl_suspend.h | 5 ----- 2 files changed, 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c b/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c index c0f5232d77a17..c7f1086ebabd3 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c @@ -8,10 +8,6 @@ #include #include -#ifndef HAVE_PM_HIBERNATE_IS_RECOVERING -static pm_message_t pm_transition; -#endif - #ifndef HAVE_KSYS_SYNC_HELPER /* Copied from kernel/power/main.c */ #ifdef CONFIG_PM_SLEEP @@ -53,18 +49,3 @@ void amdkcl_suspend_init(void) #endif /* HAVE_KSYS_SYNC_HELPER */ } -#ifndef HAVE_PM_HIBERNATE_IS_RECOVERING -/** - * pm_hibernate_is_recovering - if recovering from hibernate due to error. - * - * Used to query if dev_pm_ops.thaw() is called for normal hibernation case or - * recovering from some error. - * - * Return: true for error case, false for normal case. - */ -bool kcl_pm_hibernate_is_recovering(void) -{ - return pm_transition.event == PM_EVENT_RECOVER; -} -EXPORT_SYMBOL_GPL(kcl_pm_hibernate_is_recovering); -#endif diff --git a/include/kcl/kcl_suspend.h b/include/kcl/kcl_suspend.h index 1a8f021650b54..ca37c821757b4 100644 --- a/include/kcl/kcl_suspend.h +++ b/include/kcl/kcl_suspend.h @@ -29,9 +29,4 @@ static inline bool pm_suspend_via_firmware(void) { return false; } static inline bool pm_resume_via_firmware(void) { return false; } #endif /* HAVE_PM_SUSPEND_VIA_FIRMWARE */ -#ifndef HAVE_PM_HIBERNATE_IS_RECOVERING -bool kcl_pm_hibernate_is_recovering(void); - -#define pm_hibernate_is_recovering kcl_pm_hibernate_is_recovering -#endif #endif /* AMDKCL_SUSPEND_H */ From edbbe69249aae1214aefbaca664a38ccb9232638 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 28 Aug 2025 16:50:36 +0200 Subject: [PATCH 1818/2653] drm/amdgpu: Respect max pixel clock for HDMI and DVI-D (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the legacy (non-DC) display code to respect the maximum pixel clock for HDMI and DVI-D. Reject modes that would require a higher pixel clock than can be supported. Also update the maximum supported HDMI clock value depending on the ASIC type. For reference, see the DC code: check max_hdmi_pixel_clock in dce*_resource.c v2: Fix maximum clocks for DVI-D and DVI/HDMI adapters. Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 59 ++++++++++++++----- 1 file changed, 45 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index c8396f25856a7..69ec4489bec25 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -1262,6 +1262,23 @@ static void amdgpu_connector_dvi_force(struct drm_connector *connector) amdgpu_connector->use_digital = true; } +/** + * Returns the maximum supported HDMI (TMDS) pixel clock in KHz. + */ +static int amdgpu_max_hdmi_pixel_clock(const struct amdgpu_device *adev) +{ + if (adev->asic_type >= CHIP_POLARIS10) + return 600000; + else if (adev->asic_type >= CHIP_TONGA) + return 300000; + else + return 297000; +} + +/** + * Validates the given display mode on DVI and HDMI connectors, + * including analog signals on DVI-I. + */ static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, #ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT const struct drm_display_mode *mode) @@ -1272,27 +1289,41 @@ static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector struct drm_device *dev = connector->dev; struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + const int max_hdmi_pixel_clock = amdgpu_max_hdmi_pixel_clock(adev); + const int max_dvi_single_link_pixel_clock = 165000; + int max_digital_pixel_clock_khz; /* XXX check mode bandwidth */ - if (amdgpu_connector->use_digital && (mode->clock > 165000)) { - if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || - (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || - (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { - return MODE_OK; + if (amdgpu_connector->use_digital) { + switch (amdgpu_connector->connector_object_id) { + case CONNECTOR_OBJECT_ID_HDMI_TYPE_A: + max_digital_pixel_clock_khz = max_hdmi_pixel_clock; + break; + case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I: + case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D: + max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock; + break; + case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I: + case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D: + case CONNECTOR_OBJECT_ID_HDMI_TYPE_B: + max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock * 2; + break; + } + + /* When the display EDID claims that it's an HDMI display, + * we use the HDMI encoder mode of the display HW, + * so we should verify against the max HDMI clock here. + */ #if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) - } else if (connector->display_info.is_hdmi) { + if (connector->display_info.is_hdmi) #else - } else if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) #endif - /* HDMI 1.3+ supports max clock of 340 Mhz */ - if (mode->clock > 340000) - return MODE_CLOCK_HIGH; - else - return MODE_OK; - } else { + max_digital_pixel_clock_khz = max_hdmi_pixel_clock; + + if (mode->clock > max_digital_pixel_clock_khz) return MODE_CLOCK_HIGH; - } } /* check against the max pixel clock */ From 9661a52ef65c15cb5394aaa6764c99a0f8a3f00a Mon Sep 17 00:00:00 2001 From: David Francis Date: Mon, 16 Jun 2025 09:49:33 -0400 Subject: [PATCH 1819/2653] drm/amdgpu: Add mapping info option for GEM_OP ioctl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add new GEM_OP_IOCTL option GET_MAPPING_INFO, which returns a list of mappings associated with a given bo, along with their positions and offsets. Userspace for this and the previous change can be found at https://github.com/checkpoint-restore/criu/pull/2613 Signed-off-by: David Francis Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 88 +++++++++++++++++++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 ++ include/uapi/drm/amdgpu_drm.h | 21 +++++- 3 files changed, 99 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index e9f1b8c0bbd21..d4760b0e90d9f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -1117,17 +1117,34 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, struct drm_gem_object *gobj; struct amdgpu_vm_bo_base *base; struct amdgpu_bo *robj; + struct drm_exec exec; + struct amdgpu_fpriv *fpriv = filp->driver_priv; int r; + if (args->padding) + return -EINVAL; + gobj = drm_gem_object_lookup(filp, args->handle); if (!gobj) return -ENOENT; robj = gem_to_amdgpu_bo(gobj); - r = amdgpu_bo_reserve(robj, false); - if (unlikely(r)) - goto out; + drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT | + DRM_EXEC_IGNORE_DUPLICATES, 0); + drm_exec_until_all_locked(&exec) { + r = drm_exec_lock_obj(&exec, gobj); + drm_exec_retry_on_contention(&exec); + if (r) + goto out_exec; + + if (args->op == AMDGPU_GEM_OP_GET_MAPPING_INFO) { + r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 0); + drm_exec_retry_on_contention(&exec); + if (r) + goto out_exec; + } + } switch (args->op) { case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { @@ -1138,7 +1155,7 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, info.alignment = robj->tbo.page_alignment << PAGE_SHIFT; info.domains = robj->preferred_domains; info.domain_flags = robj->flags; - amdgpu_bo_unreserve(robj); + drm_exec_fini(&exec); if (copy_to_user(out, &info, sizeof(info))) r = -EFAULT; break; @@ -1147,20 +1164,17 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, if (drm_gem_is_imported(&robj->tbo.base) && args->value & AMDGPU_GEM_DOMAIN_VRAM) { r = -EINVAL; - amdgpu_bo_unreserve(robj); - break; + goto out_exec; } if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { r = -EPERM; - amdgpu_bo_unreserve(robj); - break; + goto out_exec; } for (base = robj->vm_bo; base; base = base->next) if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev), amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) { r = -EINVAL; - amdgpu_bo_unreserve(robj); - goto out; + goto out_exec; } @@ -1173,15 +1187,63 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) amdgpu_vm_bo_invalidate(robj, true); + drm_exec_fini(&exec); + break; + case AMDGPU_GEM_OP_GET_MAPPING_INFO: { + struct amdgpu_bo_va *bo_va = amdgpu_vm_bo_find(&fpriv->vm, robj); + struct drm_amdgpu_gem_vm_entry *vm_entries; + struct amdgpu_bo_va_mapping *mapping; + int num_mappings = 0; + /* + * num_entries is set as an input to the size of the user-allocated array of + * drm_amdgpu_gem_vm_entry stored at args->value. + * num_entries is sent back as output as the number of mappings the bo has. + * If that number is larger than the size of the array, the ioctl must + * be retried. + */ + vm_entries = kvcalloc(args->num_entries, sizeof(*vm_entries), GFP_KERNEL); + if (!vm_entries) + return -ENOMEM; + + amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) { + if (num_mappings < args->num_entries) { + vm_entries[num_mappings].addr = mapping->start * AMDGPU_GPU_PAGE_SIZE; + vm_entries[num_mappings].size = (mapping->last - mapping->start + 1) * AMDGPU_GPU_PAGE_SIZE; + vm_entries[num_mappings].offset = mapping->offset; + vm_entries[num_mappings].flags = mapping->flags; + } + num_mappings += 1; + } + + amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) { + if (num_mappings < args->num_entries) { + vm_entries[num_mappings].addr = mapping->start * AMDGPU_GPU_PAGE_SIZE; + vm_entries[num_mappings].size = (mapping->last - mapping->start + 1) * AMDGPU_GPU_PAGE_SIZE; + vm_entries[num_mappings].offset = mapping->offset; + vm_entries[num_mappings].flags = mapping->flags; + } + num_mappings += 1; + } - amdgpu_bo_unreserve(robj); + drm_exec_fini(&exec); + + if (num_mappings > 0 && num_mappings <= args->num_entries) + r = copy_to_user(u64_to_user_ptr(args->value), vm_entries, num_mappings * sizeof(*vm_entries)); + + args->num_entries = num_mappings; + + kvfree(vm_entries); break; + } default: - amdgpu_bo_unreserve(robj); + drm_exec_fini(&exec); r = -EINVAL; } -out: + drm_gem_object_put(gobj); + return r; +out_exec: + drm_exec_fini(&exec); drm_gem_object_put(gobj); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 081e485a7677b..7f318955f66eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -679,5 +679,9 @@ void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, void amdgpu_vm_print_task_info(struct amdgpu_device *adev, struct amdgpu_task_info *task_info); +#define amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) \ + list_for_each_entry(mapping, &(bo_va)->valids, list) +#define amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) \ + list_for_each_entry(mapping, &(bo_va)->invalids, list) #endif diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index b72228c0a9ad9..e1b2ee2cd1e19 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -862,6 +862,21 @@ union drm_amdgpu_wait_fences { #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 +#define AMDGPU_GEM_OP_GET_MAPPING_INFO 2 + +struct drm_amdgpu_gem_vm_entry { + /* Start of mapping (in bytes) */ + __u64 addr; + + /* Size of mapping (in bytes) */ + __u64 size; + + /* Mapping offset */ + __u64 offset; + + /* flags needed to recreate mapping */ + __u64 flags; +}; /* Sets or returns a value associated with a buffer. */ struct drm_amdgpu_gem_op { @@ -869,8 +884,12 @@ struct drm_amdgpu_gem_op { __u32 handle; /** AMDGPU_GEM_OP_* */ __u32 op; - /** Input or return value */ + /** Input or return value. For MAPPING_INFO op: pointer to array of struct drm_amdgpu_gem_vm_entry */ __u64 value; + /** For MAPPING_INFO op: number of mappings (in/out) */ + __u32 num_entries; + + __u32 padding; }; #define AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT (1 << 0) From e1810a516e5b9f908c11314352fc9f0e2e858683 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 28 Aug 2025 17:11:03 +0200 Subject: [PATCH 1820/2653] drm/amdgpu: Power up UVD 3 for FW validation (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Unlike later versions, UVD 3 has firmware validation. For this to work, the UVD should be powered up correctly. When DPM is enabled and the display clock is off, the SMU may choose a power state which doesn't power the UVD, which can result in failure to initialize UVD. v2: Add code comments to explain about the UVD power state and how UVD clock is turned on/off. Fixes: b38f3e80ecec ("drm amdgpu: SI UVD v3_1 (v2)") Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 29 +++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c index 5dbaebb592b30..2e79a3afc7748 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c @@ -623,7 +623,22 @@ static void uvd_v3_1_enable_mgcg(struct amdgpu_device *adev, * * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. * - * Initialize the hardware, boot up the VCPU and do some testing + * Initialize the hardware, boot up the VCPU and do some testing. + * + * On SI, the UVD is meant to be used in a specific power state, + * or alternatively the driver can manually enable its clock. + * In amdgpu we use the dedicated UVD power state when DPM is enabled. + * Calling amdgpu_dpm_enable_uvd makes DPM select the UVD power state + * for the SMU and afterwards enables the UVD clock. + * This is automatically done by amdgpu_uvd_ring_begin_use when work + * is submitted to the UVD ring. Here, we have to call it manually + * in order to power up UVD before firmware validation. + * + * Note that we must not disable the UVD clock here, as that would + * cause the ring test to fail. However, UVD is powered off + * automatically after the ring test: amdgpu_uvd_ring_end_use calls + * the UVD idle work handler which will disable the UVD clock when + * all fences are signalled. */ static int uvd_v3_1_hw_init(struct amdgpu_ip_block *ip_block) { @@ -633,6 +648,15 @@ static int uvd_v3_1_hw_init(struct amdgpu_ip_block *ip_block) int r; uvd_v3_1_mc_resume(adev); + uvd_v3_1_enable_mgcg(adev, true); + + /* Make sure UVD is powered during FW validation. + * It's going to be automatically powered off after the ring test. + */ + if (adev->pm.dpm_enabled) + amdgpu_dpm_enable_uvd(adev, true); + else + amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); r = uvd_v3_1_fw_validate(adev); if (r) { @@ -640,9 +664,6 @@ static int uvd_v3_1_hw_init(struct amdgpu_ip_block *ip_block) return r; } - uvd_v3_1_enable_mgcg(adev, true); - amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); - uvd_v3_1_start(adev); r = amdgpu_ring_test_helper(ring); From 7792f7849571688385fccc753fc3540f648c2f68 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 28 Aug 2025 17:11:04 +0200 Subject: [PATCH 1821/2653] drm/amd/pm: Disable ULV even if unsupported (v3) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Always send PPSMC_MSG_DisableULV to the SMC, even if ULV mode is unsupported, to make sure it is properly turned off. v3: Simplify si_disable_ulv further. Always check the return value of amdgpu_si_send_msg_to_smc. Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 52e732be59e36..e71070a23b915 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -5637,14 +5637,10 @@ static int si_populate_smc_t(struct amdgpu_device *adev, static int si_disable_ulv(struct amdgpu_device *adev) { - struct si_power_info *si_pi = si_get_pi(adev); - struct si_ulv_param *ulv = &si_pi->ulv; + PPSMC_Result r; - if (ulv->supported) - return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? - 0 : -EINVAL; - - return 0; + r = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV); + return (r == PPSMC_Result_OK) ? 0 : -EINVAL; } static bool si_is_state_ulv_compatible(struct amdgpu_device *adev, From 4a9a76170a045b10cb6d8b308b9658d8d17648be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 28 Aug 2025 17:11:05 +0200 Subject: [PATCH 1822/2653] drm/amd/pm: Increase SMC timeout on SI and warn (v3) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SMC can take an excessive amount of time to process some messages under some conditions. Background: Sending a message to the SMC works by writing the message into the mmSMC_MESSAGE_0 register and its optional parameter into the mmSMC_SCRATCH0, and then polling mmSMC_RESP_0. Previously the timeout was AMDGPU_MAX_USEC_TIMEOUT, ie. 100 ms. Increase the timeout to 200 ms for all messages and to 1 sec for a few messages which I've observed to be especially slow: PPSMC_MSG_NoForcedLevel PPSMC_MSG_SetEnabledLevels PPSMC_MSG_SetForcedLevels PPSMC_MSG_DisableULV PPSMC_MSG_SwitchToSwState This fixes the following problems on Tahiti when switching from a lower clock power state to a higher clock state, such as when DC turns on a display which was previously turned off. * si_restrict_performance_levels_before_switch would fail (if the user previously forced high clocks using sysfs) * si_set_sw_state would fail (always) It turns out that both of those failures were SMC timeouts and that the SMC actually didn't fail or hang, just needs more time to process those. Add a warning when there is an SMC timeout to make it easier to identify this type of problem in the future. Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c | 26 ++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c index 4e65ab9e931c9..281a5e377aee4 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c @@ -172,20 +172,42 @@ PPSMC_Result amdgpu_si_send_msg_to_smc(struct amdgpu_device *adev, { u32 tmp; int i; + int usec_timeout; + + /* SMC seems to process some messages exceptionally slowly. */ + switch (msg) { + case PPSMC_MSG_NoForcedLevel: + case PPSMC_MSG_SetEnabledLevels: + case PPSMC_MSG_SetForcedLevels: + case PPSMC_MSG_DisableULV: + case PPSMC_MSG_SwitchToSwState: + usec_timeout = 1000000; /* 1 sec */ + break; + default: + usec_timeout = 200000; /* 200 ms */ + break; + } if (!amdgpu_si_is_smc_running(adev)) return PPSMC_Result_Failed; WREG32(mmSMC_MESSAGE_0, msg); - for (i = 0; i < adev->usec_timeout; i++) { + for (i = 0; i < usec_timeout; i++) { tmp = RREG32(mmSMC_RESP_0); if (tmp != 0) break; udelay(1); } - return (PPSMC_Result)RREG32(mmSMC_RESP_0); + tmp = RREG32(mmSMC_RESP_0); + if (tmp == 0) { + drm_warn(adev_to_drm(adev), + "%s timeout on message: %x (SMC_SCRATCH0: %x)\n", + __func__, msg, RREG32(mmSMC_SCRATCH0)); + } + + return (PPSMC_Result)tmp; } PPSMC_Result amdgpu_si_wait_for_smc_inactive(struct amdgpu_device *adev) From 33f20c0fe19a446a3f4e324d6bc1b4217152a8e3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 28 Aug 2025 17:11:06 +0200 Subject: [PATCH 1823/2653] drm/amd/pm: Fix si_upload_smc_data (v3) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The si_upload_smc_data function uses si_write_smc_soft_register to set some register values in the SMC, and expects the result to be PPSMC_Result_OK which is 1. The PPSMC_Result_OK / PPSMC_Result_Failed values are used for checking the result of a command sent to the SMC. However, the si_write_smc_soft_register actually doesn't send any commands to the SMC and returns zero on success, so this check was incorrect. Fix that by not checking the return value, just like other calls to si_write_smc_soft_register. v3: Additionally, when no display is plugged in, there is no need to restrict MCLK switching, so program the registers to zero. Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 43 ++++++++++++---------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index e71070a23b915..6736c592dfdc6 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -5813,9 +5813,9 @@ static int si_upload_smc_data(struct amdgpu_device *adev) { struct amdgpu_crtc *amdgpu_crtc = NULL; int i; - - if (adev->pm.dpm.new_active_crtc_count == 0) - return 0; + u32 crtc_index = 0; + u32 mclk_change_block_cp_min = 0; + u32 mclk_change_block_cp_max = 0; for (i = 0; i < adev->mode_info.num_crtc; i++) { if (adev->pm.dpm.new_active_crtcs & (1 << i)) { @@ -5824,26 +5824,31 @@ static int si_upload_smc_data(struct amdgpu_device *adev) } } - if (amdgpu_crtc == NULL) - return 0; + /* When a display is plugged in, program these so that the SMC + * performs MCLK switching when it doesn't cause flickering. + * When no display is plugged in, there is no need to restrict + * MCLK switching, so program them to zero. + */ + if (adev->pm.dpm.new_active_crtc_count && amdgpu_crtc) { + crtc_index = amdgpu_crtc->crtc_id; - if (amdgpu_crtc->line_time <= 0) - return 0; + if (amdgpu_crtc->line_time) { + mclk_change_block_cp_min = amdgpu_crtc->wm_high / amdgpu_crtc->line_time; + mclk_change_block_cp_max = amdgpu_crtc->wm_low / amdgpu_crtc->line_time; + } + } - if (si_write_smc_soft_register(adev, - SI_SMC_SOFT_REGISTER_crtc_index, - amdgpu_crtc->crtc_id) != PPSMC_Result_OK) - return 0; + si_write_smc_soft_register(adev, + SI_SMC_SOFT_REGISTER_crtc_index, + crtc_index); - if (si_write_smc_soft_register(adev, - SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, - amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK) - return 0; + si_write_smc_soft_register(adev, + SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, + mclk_change_block_cp_min); - if (si_write_smc_soft_register(adev, - SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, - amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK) - return 0; + si_write_smc_soft_register(adev, + SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, + mclk_change_block_cp_max); return 0; } From ca800de02166205639bb606977c676b69b40c927 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 28 Aug 2025 17:11:07 +0200 Subject: [PATCH 1824/2653] drm/amd/pm: Adjust si_upload_smc_data register programming (v3) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Based on some comments in dm_pp_display_configuration above the crtc_index and line_time fields, these values are programmed to the SMC to work around an SMC hang when it switches MCLK. According to Alex, the Windows driver programs them to: mclk_change_block_cp_min = 200 / line_time mclk_change_block_cp_max = 100 / line_time Let's use the same for the sake of consistency. Previously we used the watermark values, but it seemed buggy as the code was mixing up low/high and A/B watermarks, and was not saving a low watermark value on DCE 6, so mclk_change_block_cp_max would be always zero previously. Split this change off from the previous si_upload_smc_data to make it easier to bisect, in case it causes any issues. Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 6736c592dfdc6..fb008c5980d67 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -5833,8 +5833,8 @@ static int si_upload_smc_data(struct amdgpu_device *adev) crtc_index = amdgpu_crtc->crtc_id; if (amdgpu_crtc->line_time) { - mclk_change_block_cp_min = amdgpu_crtc->wm_high / amdgpu_crtc->line_time; - mclk_change_block_cp_max = amdgpu_crtc->wm_low / amdgpu_crtc->line_time; + mclk_change_block_cp_min = 200 / amdgpu_crtc->line_time; + mclk_change_block_cp_max = 100 / amdgpu_crtc->line_time; } } From 952088e76ddc3f6416fa4d81f5817db828b4c36e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 28 Aug 2025 17:11:08 +0200 Subject: [PATCH 1825/2653] drm/amd/pm: Treat zero vblank time as too short in si_dpm (v3) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some parts of the code base expect that MCLK switching is turned off when the vblank time is set to zero. According to pp_pm_compute_clocks the non-DC code has issues with MCLK switching with refresh rates over 120 Hz. v3: Add code comment to explain this better. Add an if statement instead of changing the switch_limit. Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index fb008c5980d67..c11c4cc111df5 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -3085,7 +3085,13 @@ static bool si_dpm_vblank_too_short(void *handle) /* we never hit the non-gddr5 limit so disable it */ u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0; - if (vblank_time < switch_limit) + /* Consider zero vblank time too short and disable MCLK switching. + * Note that the vblank time is set to maximum when no displays are attached, + * so we'll still enable MCLK switching in that case. + */ + if (vblank_time == 0) + return true; + else if (vblank_time < switch_limit) return true; else return false; From ac431352b68c9c129bdfe8f4e953ef7404eb3d51 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 28 Aug 2025 17:11:09 +0200 Subject: [PATCH 1826/2653] drm/amd/pm: Disable MCLK switching with non-DC at 120 Hz+ (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to pp_pm_compute_clocks the non-DC display code has "issues with mclk switching with refresh rates over 120 hz". The workaround is to disable MCLK switching in this case. Do the same for legacy DPM. Fixes: 6ddbd37f1074 ("drm/amd/pm: optimize the amdgpu_pm_compute_clocks() implementations") Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c index 42efe838fa85c..2d2d2d5e67634 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c @@ -66,6 +66,13 @@ u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev) (amdgpu_crtc->v_border * 2)); vblank_time_us = vblank_in_pixels * 1000 / amdgpu_crtc->hw_mode.clock; + + /* we have issues with mclk switching with + * refresh rates over 120 hz on the non-DC code. + */ + if (drm_mode_vrefresh(&amdgpu_crtc->hw_mode) > 120) + vblank_time_us = 0; + break; } } From 182932ebbe5325bfc92bba70a4360d33f28a9c36 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 28 Aug 2025 17:11:10 +0200 Subject: [PATCH 1827/2653] drm/amd/pm: Disable SCLK switching on Oland with high pixel clocks (v3) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Port of commit 227545b9a08c ("drm/radeon/dpm: Disable sclk switching on Oland when two 4K 60Hz monitors are connected") This is an ad-hoc DPM fix, necessary because we don't have proper bandwidth calculation for DCE 6. We define "high pixelclock" for SI as higher than necessary for 4K 30Hz. For example, 4K 60Hz and 1080p 144Hz fall into this category. When two high pixel clock displays are connected to Oland, additionally disable shader clock switching, which results in a higher voltage, thereby addressing some visible flickering. v2: Add more comments. v3: Split into two commits for easier review. Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)") Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index c11c4cc111df5..4236700fc1ad1 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -3449,12 +3449,14 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev, { struct si_ps *ps = si_get_ps(rps); struct amdgpu_clock_and_voltage_limits *max_limits; + struct amdgpu_connector *conn; bool disable_mclk_switching = false; bool disable_sclk_switching = false; u32 mclk, sclk; u16 vddc, vddci, min_vce_voltage = 0; u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; u32 max_sclk = 0, max_mclk = 0; + u32 high_pixelclock_count = 0; int i; if (adev->asic_type == CHIP_HAINAN) { @@ -3482,6 +3484,35 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev, } } + /* We define "high pixelclock" for SI as higher than necessary for 4K 30Hz. + * For example, 4K 60Hz and 1080p 144Hz fall into this category. + * Find number of such displays connected. + */ + for (i = 0; i < adev->mode_info.num_crtc; i++) { + if (!(adev->pm.dpm.new_active_crtcs & (1 << i)) || + !adev->mode_info.crtcs[i]->enabled) + continue; + + conn = to_amdgpu_connector(adev->mode_info.crtcs[i]->connector); + + if (conn->pixelclock_for_modeset > 297000) + high_pixelclock_count++; + } + + /* These are some ad-hoc fixes to some issues observed with SI GPUs. + * They are necessary because we don't have something like dce_calcs + * for these GPUs to calculate bandwidth requirements. + */ + if (high_pixelclock_count) { + /* On Oland, we observe some flickering when two 4K 60Hz + * displays are connected, possibly because voltage is too low. + * Raise the voltage by requiring a higher SCLK. + * (Voltage cannot be adjusted independently without also SCLK.) + */ + if (high_pixelclock_count > 1 && adev->asic_type == CHIP_OLAND) + disable_sclk_switching = true; + } + if (rps->vce_active) { rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; From bb7e79c49139d6c4023a7676669bd1298f99ff84 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 28 Aug 2025 17:11:11 +0200 Subject: [PATCH 1828/2653] drm/amd/pm: Remove wm_low and wm_high fields from amdgpu_crtc (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These fields were only used by si_dpm and are not necessary anymore. They also may have been incorrect because: - wm_high was set to the LOW_WATERMARK field of watermark A. - wm_low was not set on DCE 6 and was always zero. Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 -- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 3 +-- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 3 +-- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 1 - drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 3 +-- 5 files changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index df3749664f675..cef3774efa98c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -496,8 +496,6 @@ struct amdgpu_crtc { struct drm_connector *connector; /* for dpm */ u32 line_time; - u32 wm_low; - u32 wm_high; u32 lb_vblank_lead_lines; struct drm_display_mode hw_mode; /* for virtual dce */ diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 6cd4a619a2dce..eb5a66f2ee682 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -1141,8 +1141,7 @@ static void dce_v10_0_program_watermarks(struct amdgpu_device *adev, /* save values for DPM */ amdgpu_crtc->line_time = line_time; - amdgpu_crtc->wm_high = latency_watermark_a; - amdgpu_crtc->wm_low = latency_watermark_b; + /* Save number of lines the linebuffer leads before the scanout */ amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 577c10c1ad635..7a02e1b5d29ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -1173,8 +1173,7 @@ static void dce_v11_0_program_watermarks(struct amdgpu_device *adev, /* save values for DPM */ amdgpu_crtc->line_time = line_time; - amdgpu_crtc->wm_high = latency_watermark_a; - amdgpu_crtc->wm_low = latency_watermark_b; + /* Save number of lines the linebuffer leads before the scanout */ amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 4f0dee3f014b2..c3cda983e12c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -1034,7 +1034,6 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev, /* save values for DPM */ amdgpu_crtc->line_time = line_time; - amdgpu_crtc->wm_high = latency_watermark_a; /* Save number of lines the linebuffer leads before the scanout */ amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 201b9139bb583..fbd83659d1acd 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -1095,8 +1095,7 @@ static void dce_v8_0_program_watermarks(struct amdgpu_device *adev, /* save values for DPM */ amdgpu_crtc->line_time = line_time; - amdgpu_crtc->wm_high = latency_watermark_a; - amdgpu_crtc->wm_low = latency_watermark_b; + /* Save number of lines the linebuffer leads before the scanout */ amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; } From 8fd75ba579613d57248187ff5235c0aef75e2a01 Mon Sep 17 00:00:00 2001 From: David Francis Date: Wed, 19 Feb 2025 10:01:32 -0500 Subject: [PATCH 1829/2653] drm/amdgpu: Allow kfd CRIU with no buffer objects The kfd CRIU checkpoint ioctl would return an error if trying to checkpoint a process with no kfd buffer objects. This is a normal case and should not be an error. Reviewed-by: Felix Kuehling Signed-off-by: David Francis --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 97bb679fe9638..77c21c6e09b30 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2834,8 +2834,8 @@ static int criu_restore(struct file *filep, pr_debug("CRIU restore (num_devices:%u num_bos:%u num_objects:%u priv_data_size:%llu)\n", args->num_devices, args->num_bos, args->num_objects, args->priv_data_size); - if (!args->bos || !args->devices || !args->priv_data || !args->priv_data_size || - !args->num_devices || !args->num_bos) + if ((args->num_bos > 0 && !args->bos) || !args->devices || !args->priv_data || + !args->priv_data_size || !args->num_devices) return -EINVAL; mutex_lock(&p->mutex); From 3f6e0be6378b504c7c69e5eeb6f98248adf232c0 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Tue, 2 Sep 2025 13:40:50 +0100 Subject: [PATCH 1830/2653] drm/amd/amdgpu: Fix missing error return on kzalloc failure Currently the kzalloc failure check just sets reports the failure and sets the variable ret to -ENOMEM, which is not checked later for this specific error. Fix this by just returning -ENOMEM rather than setting ret. Fixes: 4fb930715468 ("drm/amd/amdgpu: remove redundant host to psp cmd buf allocations") Signed-off-by: Colin Ian King Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index cf763862da502..9e7ea7a11475e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -448,7 +448,7 @@ static int psp_sw_init(struct amdgpu_ip_block *ip_block) psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); if (!psp->cmd) { dev_err(adev->dev, "Failed to allocate memory to command buffer!\n"); - ret = -ENOMEM; + return -ENOMEM; } adev->psp.xgmi_context.supports_extended_data = From aa7285687f605ad5b5e60f4acaef5913d7736848 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Fri, 29 Aug 2025 11:58:21 +0200 Subject: [PATCH 1831/2653] drm/amdgpu/amdkfd: Avoid a couple hundred -Wflex-array-member-not-at-end warnings -Wflex-array-member-not-at-end was introduced in GCC-14, and we are getting ready to enable it, globally. Move the conflicting declarations to the end of the corresponding structures. Notice that `struct dev_pagemap` is a flexible structure, this is a structure that contains a flexible-array member. struct dev_pagemap always has room for at least one range. amdgpu only uses a single range. Therefore no change are needed to the allocation of struct amdgpu_device. Fix 283 of the following type of warnings: 283 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h:111:28: warning: structure containing a flexible array member is not at the end of another structure [-Wflex-array-member-not-at-end] Signed-off-by: Gustavo A. R. Silva Signed-off-by: Felix Kuehling Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 +++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 8 +++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 312e51b528eb3..724c99bbc6797 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1170,9 +1170,6 @@ struct amdgpu_device { /* for userq and VM fences */ struct amdgpu_seq64 seq64; - /* KFD */ - struct amdgpu_kfd_dev kfd; - /* UMC */ struct amdgpu_umc umc; @@ -1342,6 +1339,11 @@ struct amdgpu_device { struct mutex userq_mutex; bool userq_halt_for_enforce_isolation; struct amdgpu_uid *uid_info; + + /* KFD + * Must be last --ends in a flexible-array member. + */ + struct amdgpu_kfd_dev kfd; }; static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index f176ac194e0e6..81885165b1f28 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -113,11 +113,13 @@ struct amdgpu_kfd_dev { bool init_complete; struct work_struct reset_work; - /* HMM page migration MEMORY_DEVICE_PRIVATE mapping */ - struct dev_pagemap pgmap; - /* Client for KFD BO GEM handle allocations */ struct drm_client_dev client; + + /* HMM page migration MEMORY_DEVICE_PRIVATE mapping + * Must be last --ends in a flexible-array member. + */ + struct dev_pagemap pgmap; }; enum kgd_engine_type { From b3b15b655c103a74f4cab9684bf9399c7a85b0e2 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 4 Sep 2025 10:32:48 +0800 Subject: [PATCH 1832/2653] Revert "drm/amd/amdgpu : Use the MES INV_TLBS API for tlb invalidation on gfx12" This reverts commit 9c4ee796853189a1c2b8f3095d14123bee53e723. It cause the Jira ticket: SWDEV-552791, temporarily revert it. Signed-off-by: Chengjun Yao --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 10 ------ drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 16 ---------- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 42 ------------------------- 3 files changed, 68 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 489a4a0f06105..c0d2c195fe2ed 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -280,13 +280,6 @@ struct mes_reset_queue_input { bool is_kq; }; -struct mes_inv_tlbs_pasid_input { - uint32_t xcc_id; - uint16_t pasid; - uint8_t hub_id; - uint8_t flush_type; -}; - enum mes_misc_opcode { MES_MISC_OP_WRITE_REG, MES_MISC_OP_READ_REG, @@ -374,9 +367,6 @@ struct amdgpu_mes_funcs { int (*reset_hw_queue)(struct amdgpu_mes *mes, struct mes_reset_queue_input *input); - - int (*invalidate_tlbs_pasid)(struct amdgpu_mes *mes, - struct mes_inv_tlbs_pasid_input *input); }; #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 9ba055ddc00f6..a0a5367f9dc40 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -336,22 +336,6 @@ static void gmc_v12_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t queried; int vmid, i; - if (adev->enable_uni_mes && adev->mes.ring[AMDGPU_MES_SCHED_PIPE].sched.ready && - (adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x81) { - struct mes_inv_tlbs_pasid_input input = {0}; - input.pasid = pasid; - input.flush_type = flush_type; - input.hub_id = AMDGPU_GFXHUB(0); - /* MES will invalidate all gc_hub for the device from master */ - adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); - if (all_hub) { - /* Only need to invalidate mm_hub now, gfx12 only support one mmhub */ - input.hub_id = AMDGPU_MMHUB0(0); - adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); - } - return; - } - for (vmid = 1; vmid < 16; vmid++) { bool valid; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index cd5c966cee957..6b222630f3fa1 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -108,7 +108,6 @@ static const char *mes_v12_0_opcodes[] = { "SET_SE_MODE", "SET_GANG_SUBMIT", "SET_HW_RSRC_1", - "INVALIDATE_TLBS", }; static const char *mes_v12_0_misc_opcodes[] = { @@ -880,46 +879,6 @@ static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes, offsetof(union MESAPI__RESET, api_status)); } -static int mes_v12_inv_tlb_convert_hub_id(uint8_t id) -{ - /* - * MES doesn't support invalidate gc_hub on slave xcc individually - * master xcc will invalidate all gc_hub for the partition - */ - if (AMDGPU_IS_GFXHUB(id)) - return 0; - else if (AMDGPU_IS_MMHUB0(id)) - return 1; - else - return -EINVAL; - -} - -static int mes_v12_0_inv_tlbs_pasid(struct amdgpu_mes *mes, - struct mes_inv_tlbs_pasid_input *input) -{ - union MESAPI__INV_TLBS mes_inv_tlbs; - - memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs)); - - mes_inv_tlbs.header.type = MES_API_TYPE_SCHEDULER; - mes_inv_tlbs.header.opcode = MES_SCH_API_INV_TLBS; - mes_inv_tlbs.header.dwsize = API_FRAME_SIZE_IN_DWORDS; - - mes_inv_tlbs.invalidate_tlbs.inv_sel = 0; - mes_inv_tlbs.invalidate_tlbs.flush_type = input->flush_type; - mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input->pasid; - - /*convert amdgpu_mes_hub_id to mes expected hub_id */ - mes_inv_tlbs.invalidate_tlbs.hub_id = mes_v12_inv_tlb_convert_hub_id(input->hub_id); - if (mes_inv_tlbs.invalidate_tlbs.hub_id < 0) - return -EINVAL; - return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_KIQ_PIPE, - &mes_inv_tlbs, sizeof(mes_inv_tlbs), - offsetof(union MESAPI__INV_TLBS, api_status)); - -} - static const struct amdgpu_mes_funcs mes_v12_0_funcs = { .add_hw_queue = mes_v12_0_add_hw_queue, .remove_hw_queue = mes_v12_0_remove_hw_queue, @@ -929,7 +888,6 @@ static const struct amdgpu_mes_funcs mes_v12_0_funcs = { .resume_gang = mes_v12_0_resume_gang, .misc_op = mes_v12_0_misc_op, .reset_hw_queue = mes_v12_0_reset_hw_queue, - .invalidate_tlbs_pasid = mes_v12_0_inv_tlbs_pasid, }; static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, From b353638322f211eab824b8b82f97d295991cf7a1 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Tue, 26 Aug 2025 17:30:58 +0800 Subject: [PATCH 1833/2653] drm/amdgpu: update firmware version checks for user queue support The minimum firmware versions required for user queue functionality have been increased to address an issue where the queue privilege state was lost during queue connect operations. The problem occurred because the privilege state was being restored to its initial value at the beginning of the function, overwriting the state that was properly set during the queue connect case. This commit updates the minimum version requirements: - ME firmware from 2390 to 2420 - PFP firmware from 2530 to 2580 - MEC firmware from 2600 to 2650 - MES firmware remains at 120 These updated firmware versions contain the necessary fixes to properly maintain queue privilege state throughout connect operations. Fixes: d84f90e2bcec ("drm/amdgpu: Add fw minimum version check for usermode queue") Acked-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 7780fb6118674..0ad6115651bcc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -1612,9 +1612,9 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block) case IP_VERSION(11, 0, 2): case IP_VERSION(11, 0, 3): if (!adev->gfx.disable_uq && - adev->gfx.me_fw_version >= 2390 && - adev->gfx.pfp_fw_version >= 2530 && - adev->gfx.mec_fw_version >= 2600 && + adev->gfx.me_fw_version >= 2420 && + adev->gfx.pfp_fw_version >= 2580 && + adev->gfx.mec_fw_version >= 2650 && adev->mes.fw_version[0] >= 120) { adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs; adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs; From 1a43b51624b40d6e3ebd083d328d2c62b2696aab Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 4 Sep 2025 10:32:48 +0800 Subject: [PATCH 1834/2653] Revert "drm/amd/amdgpu : Use the MES INV_TLBS API for tlb invalidation on gfx12" This reverts commit 9c4ee796853189a1c2b8f3095d14123bee53e723. It cause the Jira ticket: SWDEV-552791, temporarily revert it. Signed-off-by: Chengjun Yao --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 10 ------ drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 16 ---------- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 42 ------------------------- 3 files changed, 68 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 489a4a0f06105..c0d2c195fe2ed 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -280,13 +280,6 @@ struct mes_reset_queue_input { bool is_kq; }; -struct mes_inv_tlbs_pasid_input { - uint32_t xcc_id; - uint16_t pasid; - uint8_t hub_id; - uint8_t flush_type; -}; - enum mes_misc_opcode { MES_MISC_OP_WRITE_REG, MES_MISC_OP_READ_REG, @@ -374,9 +367,6 @@ struct amdgpu_mes_funcs { int (*reset_hw_queue)(struct amdgpu_mes *mes, struct mes_reset_queue_input *input); - - int (*invalidate_tlbs_pasid)(struct amdgpu_mes *mes, - struct mes_inv_tlbs_pasid_input *input); }; #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 9ba055ddc00f6..a0a5367f9dc40 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -336,22 +336,6 @@ static void gmc_v12_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t queried; int vmid, i; - if (adev->enable_uni_mes && adev->mes.ring[AMDGPU_MES_SCHED_PIPE].sched.ready && - (adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x81) { - struct mes_inv_tlbs_pasid_input input = {0}; - input.pasid = pasid; - input.flush_type = flush_type; - input.hub_id = AMDGPU_GFXHUB(0); - /* MES will invalidate all gc_hub for the device from master */ - adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); - if (all_hub) { - /* Only need to invalidate mm_hub now, gfx12 only support one mmhub */ - input.hub_id = AMDGPU_MMHUB0(0); - adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); - } - return; - } - for (vmid = 1; vmid < 16; vmid++) { bool valid; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index cd5c966cee957..6b222630f3fa1 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -108,7 +108,6 @@ static const char *mes_v12_0_opcodes[] = { "SET_SE_MODE", "SET_GANG_SUBMIT", "SET_HW_RSRC_1", - "INVALIDATE_TLBS", }; static const char *mes_v12_0_misc_opcodes[] = { @@ -880,46 +879,6 @@ static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes, offsetof(union MESAPI__RESET, api_status)); } -static int mes_v12_inv_tlb_convert_hub_id(uint8_t id) -{ - /* - * MES doesn't support invalidate gc_hub on slave xcc individually - * master xcc will invalidate all gc_hub for the partition - */ - if (AMDGPU_IS_GFXHUB(id)) - return 0; - else if (AMDGPU_IS_MMHUB0(id)) - return 1; - else - return -EINVAL; - -} - -static int mes_v12_0_inv_tlbs_pasid(struct amdgpu_mes *mes, - struct mes_inv_tlbs_pasid_input *input) -{ - union MESAPI__INV_TLBS mes_inv_tlbs; - - memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs)); - - mes_inv_tlbs.header.type = MES_API_TYPE_SCHEDULER; - mes_inv_tlbs.header.opcode = MES_SCH_API_INV_TLBS; - mes_inv_tlbs.header.dwsize = API_FRAME_SIZE_IN_DWORDS; - - mes_inv_tlbs.invalidate_tlbs.inv_sel = 0; - mes_inv_tlbs.invalidate_tlbs.flush_type = input->flush_type; - mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input->pasid; - - /*convert amdgpu_mes_hub_id to mes expected hub_id */ - mes_inv_tlbs.invalidate_tlbs.hub_id = mes_v12_inv_tlb_convert_hub_id(input->hub_id); - if (mes_inv_tlbs.invalidate_tlbs.hub_id < 0) - return -EINVAL; - return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_KIQ_PIPE, - &mes_inv_tlbs, sizeof(mes_inv_tlbs), - offsetof(union MESAPI__INV_TLBS, api_status)); - -} - static const struct amdgpu_mes_funcs mes_v12_0_funcs = { .add_hw_queue = mes_v12_0_add_hw_queue, .remove_hw_queue = mes_v12_0_remove_hw_queue, @@ -929,7 +888,6 @@ static const struct amdgpu_mes_funcs mes_v12_0_funcs = { .resume_gang = mes_v12_0_resume_gang, .misc_op = mes_v12_0_misc_op, .reset_hw_queue = mes_v12_0_reset_hw_queue, - .invalidate_tlbs_pasid = mes_v12_0_inv_tlbs_pasid, }; static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, From ecdee85d3041ee535cc057576c28c6de08c03d4f Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 5 Sep 2025 13:14:29 +0800 Subject: [PATCH 1835/2653] Bump AMDGPU version to 6.16.2 Signed-off-by: Chengjun Yao --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index a3fca23de87f2..8be0ae489f762 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.16.1) +AC_INIT(amdgpu-dkms, 6.16.2) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From c6fc9078a11033a2906ba36ed9df3acba3fff827 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 28 Aug 2025 17:11:12 +0200 Subject: [PATCH 1836/2653] drm/amd/pm: Print VCE clocks too in si_dpm (v3) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit They are part of a power state too and should be printed alongside the rest of the data from the power state. Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 4236700fc1ad1..6595a611ce6e5 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -7992,6 +7992,7 @@ static void si_dpm_print_power_state(void *handle, amdgpu_dpm_dbg_print_class_info(adev, rps->class, rps->class2); amdgpu_dpm_dbg_print_cap_info(adev, rps->caps); drm_dbg(adev_to_drm(adev), "\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); + drm_dbg(adev_to_drm(adev), "\tvce evclk: %d ecclk: %d\n", rps->evclk, rps->ecclk); for (i = 0; i < ps->performance_level_count; i++) { pl = &ps->performance_levels[i]; drm_dbg(adev_to_drm(adev), "\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", From 3264866725498d04d9d2ff3b861361da537d0011 Mon Sep 17 00:00:00 2001 From: Liao Yuanhong Date: Wed, 3 Sep 2025 20:03:45 +0800 Subject: [PATCH 1837/2653] drm/amdgpu/amdgpu_cper: Remove redundant ternary operators MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For ternary operators in the form of "a ? false : true", if 'a' itself returns a boolean result, the ternary operator can be omitted. Remove redundant ternary operators to clean up the code. Reviewed-by: Christian König Signed-off-by: Liao Yuanhong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c index 6c266f18c5981..c4590ec35cadd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c @@ -174,7 +174,7 @@ int amdgpu_cper_entry_fill_runtime_section(struct amdgpu_device *adev, struct cper_sec_nonstd_err *section; bool poison; - poison = (sev == CPER_SEV_NON_FATAL_CORRECTED) ? false : true; + poison = sev != CPER_SEV_NON_FATAL_CORRECTED; section_desc = (struct cper_sec_desc *)((uint8_t *)hdr + SEC_DESC_OFFSET(idx)); section = (struct cper_sec_nonstd_err *)((uint8_t *)hdr + NONSTD_SEC_OFFSET(hdr->sec_cnt, idx)); From 419515c4ecbf8f4ec679debcaa63cb5f73c83040 Mon Sep 17 00:00:00 2001 From: Liao Yuanhong Date: Wed, 3 Sep 2025 20:03:46 +0800 Subject: [PATCH 1838/2653] drm/amdgpu/gfx: Remove redundant ternary operators MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For ternary operators in the form of "a ? false : true", if 'a' itself returns a boolean result, the ternary operator can be omitted. Remove redundant ternary operators to clean up the code. Reviewed-by: Christian König Signed-off-by: Liao Yuanhong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 3 +-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 0ad6115651bcc..76cb4092a60a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4643,8 +4643,7 @@ static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev) amdgpu_device_flush_hdp(adev, NULL); - value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? - false : true; + value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; adev->gfxhub.funcs->set_fault_enable_default(adev, value); /* TODO investigate why this and the hdp flush above is needed, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 456aec15ada3a..c1703f64fb882 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -3524,8 +3524,7 @@ static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev) amdgpu_device_flush_hdp(adev, NULL); - value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? - false : true; + value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; adev->gfxhub.funcs->set_fault_enable_default(adev, value); /* TODO investigate why this and the hdp flush above is needed, From 87d9548469bffe4c33c974388c43d56f10b860ac Mon Sep 17 00:00:00 2001 From: Liao Yuanhong Date: Wed, 3 Sep 2025 20:03:47 +0800 Subject: [PATCH 1839/2653] drm/amdgpu/gmc: Remove redundant ternary operators MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For ternary operators in the form of "a ? false : true", if 'a' itself returns a boolean result, the ternary operator can be omitted. Remove redundant ternary operators to clean up the code. Reviewed-by: Christian König Signed-off-by: Liao Yuanhong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 +-- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 3 +-- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 3 +-- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 68be789c0d493..3243f225a4b6a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -961,8 +961,7 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) /* Flush HDP after it is initialized */ amdgpu_device_flush_hdp(adev, NULL); - value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? - false : true; + value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; if (!adev->in_s0ix) adev->gfxhub.funcs->set_fault_enable_default(adev, value); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 7db0048d2294b..a1f8141f28c90 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -903,8 +903,7 @@ static int gmc_v11_0_gart_enable(struct amdgpu_device *adev) /* Flush HDP after it is initialized */ amdgpu_device_flush_hdp(adev, NULL); - value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? - false : true; + value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; adev->mmhub.funcs->set_fault_enable_default(adev, value); gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index a0a5367f9dc40..48f676126a6b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -877,8 +877,7 @@ static int gmc_v12_0_gart_enable(struct amdgpu_device *adev) /* Flush HDP after it is initialized */ amdgpu_device_flush_hdp(adev, NULL); - value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? - false : true; + value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; adev->mmhub.funcs->set_fault_enable_default(adev, value); gmc_v12_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); From 5ea57c5471e2cf03bb005e1e1fae9a58e511cf69 Mon Sep 17 00:00:00 2001 From: Liao Yuanhong Date: Wed, 3 Sep 2025 20:03:48 +0800 Subject: [PATCH 1840/2653] drm/amdgpu/ih: Remove redundant ternary operators MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For ternary operators in the form of "a ? false : true", if 'a' itself returns a boolean result, the ternary operator can be omitted. Remove redundant ternary operators to clean up the code. Reviewed-by: Christian König Signed-off-by: Liao Yuanhong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 3 +-- drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 3 +-- drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 3 +-- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c index 5900b560b7dee..333e9c30c091d 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c @@ -587,8 +587,7 @@ static int ih_v6_0_sw_init(struct amdgpu_ip_block *ip_block) /* use gpu virtual address for ih ring * until ih_checken is programmed to allow * use bus address for ih ring by psp bl */ - use_bus_addr = - (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true; + use_bus_addr = adev->firmware.load_type != AMDGPU_FW_LOAD_PSP; r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c index 068ed849dbada..95b3f4e55ec3d 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c @@ -562,8 +562,7 @@ static int ih_v6_1_sw_init(struct amdgpu_ip_block *ip_block) /* use gpu virtual address for ih ring * until ih_checken is programmed to allow * use bus address for ih ring by psp bl */ - use_bus_addr = - (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true; + use_bus_addr = adev->firmware.load_type != AMDGPU_FW_LOAD_PSP; r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c index 40a3530e04539..b32ea4129c616 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c @@ -552,8 +552,7 @@ static int ih_v7_0_sw_init(struct amdgpu_ip_block *ip_block) /* use gpu virtual address for ih ring * until ih_checken is programmed to allow * use bus address for ih ring by psp bl */ - use_bus_addr = - (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true; + use_bus_addr = adev->firmware.load_type != AMDGPU_FW_LOAD_PSP; r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); if (r) return r; From 9ecd0f652ad5dda0c3ea7c57ff3f47c0cff64a26 Mon Sep 17 00:00:00 2001 From: Liao Yuanhong Date: Wed, 3 Sep 2025 20:03:49 +0800 Subject: [PATCH 1841/2653] drm/amdgpu/jpeg: Remove redundant ternary operators MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For ternary operators in the form of "a ? true : false", if 'a' itself returns a boolean result, the ternary operator can be omitted. Remove redundant ternary operators to clean up the code. Reviewed-by: Christian König Signed-off-by: Liao Yuanhong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 2 +- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c index 481d1a2dbe5aa..5d86e1d846eb0 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c @@ -686,7 +686,7 @@ static int jpeg_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block, enum amd_clockgating_state state) { struct amdgpu_device *adev = ip_block->adev; - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; + bool enable = state == AMD_CG_STATE_GATE; int i; for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c index e0a71909252be..34c70270ea1db 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c @@ -584,7 +584,7 @@ static int jpeg_v5_0_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, enum amd_clockgating_state state) { struct amdgpu_device *adev = ip_block->adev; - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; + bool enable = state == AMD_CG_STATE_GATE; if (enable) { if (!jpeg_v5_0_0_is_idle(ip_block)) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c index 47bde62b39099..baf097d2e1ac9 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c @@ -697,7 +697,7 @@ static int jpeg_v5_0_1_set_clockgating_state(struct amdgpu_ip_block *ip_block, enum amd_clockgating_state state) { struct amdgpu_device *adev = ip_block->adev; - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; + bool enable = state == AMD_CG_STATE_GATE; int i; From d447ca24f3e34c06b8b738966c7fe7940b873f09 Mon Sep 17 00:00:00 2001 From: Liao Yuanhong Date: Wed, 3 Sep 2025 20:03:50 +0800 Subject: [PATCH 1842/2653] drm/amdgpu/vcn: Remove redundant ternary operators MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For ternary operators in the form of "a ? true : false", if 'a' itself returns a boolean result, the ternary operator can be omitted. Remove redundant ternary operators to clean up the code. Reviewed-by: Christian König Signed-off-by: Liao Yuanhong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index 75c884a8f556b..6dbf33b26ee27 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -1591,7 +1591,7 @@ static int vcn_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block, enum amd_clockgating_state state) { struct amdgpu_device *adev = ip_block->adev; - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; + bool enable = state == AMD_CG_STATE_GATE; int i; for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index 455f829b8bb99..536f06b817061 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -1311,7 +1311,7 @@ static int vcn_v5_0_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, enum amd_clockgating_state state) { struct amdgpu_device *adev = ip_block->adev; - bool enable = (state == AMD_CG_STATE_GATE) ? true : false; + bool enable = state == AMD_CG_STATE_GATE; int i; for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { From 3c4e17f91f53f1ace9b3f9ebca1f074adffa9017 Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Mon, 25 Aug 2025 09:50:49 -0400 Subject: [PATCH 1843/2653] drm/amdkfd: fix p2p links bug in topology When creating p2p links, KFD needs to check XGMI link with two conditions, hive_id and is_sharing_enabled, but it is missing to check is_sharing_enabled, so add it to fix the error. Signed-off-by: Eric Huang Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index ac688f1aa5009..8644039777b85 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1659,7 +1659,8 @@ static int kfd_dev_create_p2p_links(void) break; if (!dev->gpu || !dev->gpu->adev || (dev->gpu->kfd->hive_id && - dev->gpu->kfd->hive_id == new_dev->gpu->kfd->hive_id)) + dev->gpu->kfd->hive_id == new_dev->gpu->kfd->hive_id && + amdgpu_xgmi_get_is_sharing_enabled(dev->gpu->adev, new_dev->gpu->adev))) goto next; /* check if node(s) is/are peer accessible in one direction or bi-direction */ From a6c686f859d560abc4172057c5ab3e6fb25c03c8 Mon Sep 17 00:00:00 2001 From: Xiang Liu Date: Tue, 2 Sep 2025 22:13:44 +0800 Subject: [PATCH 1844/2653] drm/amdgpu: Correct info field of bad page threshold exceed CPER Correct valid_bits and ms_chk_bits of section info field for bad page threshold exceed CPER to match OOB's behavior. Signed-off-by: Xiang Liu Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c index c4590ec35cadd..ef996493115fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c @@ -68,7 +68,6 @@ void amdgpu_cper_entry_fill_hdr(struct amdgpu_device *adev, hdr->error_severity = sev; hdr->valid_bits.platform_id = 1; - hdr->valid_bits.partition_id = 1; hdr->valid_bits.timestamp = 1; amdgpu_cper_get_timestamp(&hdr->timestamp); @@ -220,7 +219,10 @@ int amdgpu_cper_entry_fill_bad_page_threshold_section(struct amdgpu_device *adev section->hdr.valid_bits.err_context_cnt = 1; section->info.error_type = RUNTIME; + section->info.valid_bits.ms_chk = 1; section->info.ms_chk_bits.err_type_valid = 1; + section->info.ms_chk_bits.err_type = 1; + section->info.ms_chk_bits.pcc = 1; section->ctx.reg_ctx_type = CPER_CTX_TYPE_CRASH; section->ctx.reg_arr_size = sizeof(section->ctx.reg_dump); From f120a542cef11e81293fd72f4de7cd18d182611c Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 14 Aug 2025 13:23:32 +0530 Subject: [PATCH 1845/2653] drm/amdgpu: add more information in debugfs to pagetable dump MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add more information in the debugfs which is needed to dump a pagetable correctly for userqueues where vmid is not known in the kernel. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 518121e9e8754..39ba6790999da 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -2144,12 +2144,14 @@ static int amdgpu_pt_info_read(struct seq_file *m, void *unused) struct drm_file *file; struct amdgpu_fpriv *fpriv; struct amdgpu_bo *root_bo; + struct amdgpu_device *adev; int r; file = m->private; if (!file) return -EINVAL; + adev = drm_to_adev(file->minor->dev); fpriv = file->driver_priv; if (!fpriv || !fpriv->vm.root.bo) return -ENODEV; @@ -2162,6 +2164,10 @@ static int amdgpu_pt_info_read(struct seq_file *m, void *unused) } seq_printf(m, "gpu_address: 0x%llx\n", amdgpu_bo_gpu_offset(fpriv->vm.root.bo)); + seq_printf(m, "max_pfn: 0x%llx\n", adev->vm_manager.max_pfn); + seq_printf(m, "num_level: 0x%x\n", adev->vm_manager.num_level); + seq_printf(m, "block_size: 0x%x\n", adev->vm_manager.block_size); + seq_printf(m, "fragment_size: 0x%x\n", adev->vm_manager.fragment_size); amdgpu_bo_unreserve(root_bo); amdgpu_bo_unref(&root_bo); From 06b7c6778388cd132ff6cdf8e5a6607d8778d28f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 27 Jun 2025 10:09:06 -0400 Subject: [PATCH 1846/2653] drm/amd: add more cyan skillfish PCI ids Add additional PCI IDs to the cyan skillfish family. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index dbe59db44853c..9a6ff1464c75e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2192,6 +2192,11 @@ static const struct pci_device_id pciidlist[] = { {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, /* CYAN_SKILLFISH */ + {0x1002, 0x13DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, + {0x1002, 0x13F9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, + {0x1002, 0x13FA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, + {0x1002, 0x13FB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, + {0x1002, 0x13FC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, From f6016ca0d17f9a1fbd5d728ed6794a1cb0dadee0 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 14 Aug 2025 13:29:04 +0530 Subject: [PATCH 1847/2653] drm/amdgpu: fix the formating for debugfs print MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix the format of debugfs print in the mqd. Need to add a colon so parser can parse it properly. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 7cf51a00411a2..ff52c582f6c4e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -364,7 +364,7 @@ static int amdgpu_mqd_info_read(struct seq_file *m, void *unused) return -EINVAL; } - seq_printf(m, "queue_type %d\n", queue->queue_type); + seq_printf(m, "queue_type: %d\n", queue->queue_type); seq_printf(m, "mqd_gpu_address: 0x%llx\n", amdgpu_bo_gpu_offset(queue->mqd.obj)); amdgpu_bo_unreserve(bo); From 50cd83cf5b3d9e1650f3e1ac50227410cfb80274 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Tue, 5 Aug 2025 11:26:15 +0800 Subject: [PATCH 1848/2653] drm/amdgpu: Add preempt and restore callbacks to userq funcs Add two new function pointers to struct amdgpu_userq_funcs: - preempt: To handle preemption of user mode queues - restore: To restore preempted user mode queues These callbacks will allow the driver to properly manage queue preemption and restoration when needed, such as during context switching or priority changes. Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index a6b61ce40f0db..5c87704331dec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -83,6 +83,10 @@ struct amdgpu_userq_funcs { struct amdgpu_usermode_queue *queue); int (*map)(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_queue *queue); + int (*preempt)(struct amdgpu_userq_mgr *uq_mgr, + struct amdgpu_usermode_queue *queue); + int (*restore)(struct amdgpu_userq_mgr *uq_mgr, + struct amdgpu_usermode_queue *queue); }; /* Usermode queues for gfx */ From 4346112c9fcba08227c47d6cc7892ef0a375b922 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Sun, 3 Aug 2025 21:21:42 +0800 Subject: [PATCH 1849/2653] drm/amd/amdgpu: Implement MES suspend/resume gang functionality for v12 This commit implements the actual MES (Micro Engine Scheduler) suspend and resume gang operations for version 12 hardware. Previously these functions were just stubs returning success. v2: Always use AMDGPU_MES_SCHED_PIPE Signed-off-by: Alex Deucher Signed-off-by: Jesse Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 32 ++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index 6b222630f3fa1..24c61239b25da 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -567,13 +567,41 @@ static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes, static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes, struct mes_suspend_gang_input *input) { - return 0; + union MESAPI__SUSPEND mes_suspend_gang_pkt; + + memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); + + mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; + mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; + mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; + mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; + mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; + + return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, + &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), + offsetof(union MESAPI__SUSPEND, api_status)); } static int mes_v12_0_resume_gang(struct amdgpu_mes *mes, struct mes_resume_gang_input *input) { - return 0; + union MESAPI__RESUME mes_resume_gang_pkt; + + memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); + + mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; + mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; + mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; + + return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, + &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), + offsetof(union MESAPI__RESUME, api_status)); } static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes, int pipe) From d5a86c2095d2aeb8d6cdf07e36dcc029b8bb1d89 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Thu, 4 Sep 2025 09:39:34 +0800 Subject: [PATCH 1850/2653] drm/amdgpu/mes: add front end for detect and reset hung queue Helper function to detect and reset hung queues. MES will return an array of doorbell indices of which queues are hung and were optionally reset. v2: Clear the doorbell array before detection Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 65 +++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 21 ++++++++ 2 files changed, 86 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 135598502c8d0..5bf9be073cddf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -191,6 +191,20 @@ int amdgpu_mes_init(struct amdgpu_device *adev) if (r) goto error_doorbell; + if (adev->mes.hung_queue_db_array_size) { + r = amdgpu_bo_create_kernel(adev, + adev->mes.hung_queue_db_array_size * sizeof(u32), + PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, + &adev->mes.hung_queue_db_array_gpu_obj, + &adev->mes.hung_queue_db_array_gpu_addr, + &adev->mes.hung_queue_db_array_cpu_addr); + if (r) { + dev_warn(adev->dev, "failed to create MES hung db array buffer (%d)", r); + goto error_doorbell; + } + } + return 0; error_doorbell: @@ -216,6 +230,10 @@ void amdgpu_mes_fini(struct amdgpu_device *adev) { int i; + amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj, + &adev->mes.hung_queue_db_array_gpu_addr, + &adev->mes.hung_queue_db_array_cpu_addr); + amdgpu_bo_free_kernel(&adev->mes.event_log_gpu_obj, &adev->mes.event_log_gpu_addr, &adev->mes.event_log_cpu_addr); @@ -366,6 +384,53 @@ int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, return r; } +int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev) +{ + return adev->mes.hung_queue_db_array_size; +} + +int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, + int queue_type, + bool detect_only, + unsigned int *hung_db_num, + u32 *hung_db_array) + +{ + struct mes_detect_and_reset_queue_input input; + u32 *db_array = adev->mes.hung_queue_db_array_cpu_addr; + int r, i; + + if (!hung_db_num || !hung_db_array) + return -EINVAL; + + if ((queue_type != AMDGPU_RING_TYPE_GFX) && + (queue_type != AMDGPU_RING_TYPE_COMPUTE) && + (queue_type != AMDGPU_RING_TYPE_SDMA)) + return -EINVAL; + + /* Clear the doorbell array before detection */ + memset(adev->mes.hung_queue_db_array_cpu_addr, 0, + adev->mes.hung_queue_db_array_size * sizeof(u32)); + input.queue_type = queue_type; + input.detect_only = detect_only; + + r = adev->mes.funcs->detect_and_reset_hung_queues(&adev->mes, + &input); + if (r) { + dev_err(adev->dev, "failed to detect and reset\n"); + } else { + *hung_db_num = 0; + for (i = 0; i < adev->mes.hung_queue_db_array_size; i++) { + if (db_array[i] != AMDGPU_MES_INVALID_DB_OFFSET) { + hung_db_array[i] = db_array[i]; + *hung_db_num += 1; + } + } + } + + return r; +} + uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg) { struct mes_misc_op_input op_input; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index c0d2c195fe2ed..98e77aa01f277 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -41,6 +41,7 @@ #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 #define AMDGPU_MES_MSCRATCH_SIZE 0x40000 +#define AMDGPU_MES_INVALID_DB_OFFSET 0xffffffff enum amdgpu_mes_priority_level { AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, @@ -147,6 +148,10 @@ struct amdgpu_mes { uint64_t resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES]; void *resource_1_addr[AMDGPU_MAX_MES_PIPES]; + int hung_queue_db_array_size; + struct amdgpu_bo *hung_queue_db_array_gpu_obj; + uint64_t hung_queue_db_array_gpu_addr; + void *hung_queue_db_array_cpu_addr; }; struct amdgpu_mes_gang { @@ -280,6 +285,11 @@ struct mes_reset_queue_input { bool is_kq; }; +struct mes_detect_and_reset_queue_input { + uint32_t queue_type; + bool detect_only; +}; + enum mes_misc_opcode { MES_MISC_OP_WRITE_REG, MES_MISC_OP_READ_REG, @@ -367,6 +377,10 @@ struct amdgpu_mes_funcs { int (*reset_hw_queue)(struct amdgpu_mes *mes, struct mes_reset_queue_input *input); + + int (*detect_and_reset_hung_queues)(struct amdgpu_mes *mes, + struct mes_detect_and_reset_queue_input *input); + }; #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) @@ -390,6 +404,13 @@ int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, unsigned int vmid, bool use_mmio); +int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev); +int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, + int queue_type, + bool detect_only, + unsigned int *hung_db_num, + u32 *hung_db_array); + uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg); int amdgpu_mes_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t val); From 1cf8e03a43dec2520f78414c5e9482fc906ba05e Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Thu, 4 Sep 2025 09:44:51 +0800 Subject: [PATCH 1851/2653] drm/amdgpu/mes11: implement detect and reset callback Implement support for the hung queue detect and reset functionality. Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 31 ++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 3f6a828cad8ad..3b91ea601add4 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -66,6 +66,8 @@ static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); #define GFX_MES_DRAM_SIZE 0x80000 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE) +#define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 4 + static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -784,6 +786,32 @@ static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, offsetof(union MESAPI__RESET, api_status)); } +static int mes_v11_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, + struct mes_detect_and_reset_queue_input *input) +{ + union MESAPI__RESET mes_reset_queue_pkt; + + memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); + + mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; + mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_reset_queue_pkt.queue_type = + convert_to_mes_queue_type(input->queue_type); + mes_reset_queue_pkt.doorbell_offset_addr = + mes->hung_queue_db_array_gpu_addr; + + if (input->detect_only) + mes_reset_queue_pkt.hang_detect_only = 1; + else + mes_reset_queue_pkt.hang_detect_then_reset = 1; + + return mes_v11_0_submit_pkt_and_poll_completion(mes, + &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), + offsetof(union MESAPI__RESET, api_status)); +} + static const struct amdgpu_mes_funcs mes_v11_0_funcs = { .add_hw_queue = mes_v11_0_add_hw_queue, .remove_hw_queue = mes_v11_0_remove_hw_queue, @@ -793,6 +821,7 @@ static const struct amdgpu_mes_funcs mes_v11_0_funcs = { .resume_gang = mes_v11_0_resume_gang, .misc_op = mes_v11_0_misc_op, .reset_hw_queue = mes_v11_0_reset_hw_queue, + .detect_and_reset_hung_queues = mes_v11_0_detect_and_reset_hung_queues, }; static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, @@ -1685,6 +1714,8 @@ static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; int pipe, r; + adev->mes.hung_queue_db_array_size = + MES11_HUNG_DB_OFFSET_ARRAY_SIZE; for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) continue; From ae1d46184f07aeeacf9fe8c5974ff7d557f1502b Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Thu, 4 Sep 2025 09:50:00 +0800 Subject: [PATCH 1852/2653] drm/amdgpu/mes12: implement detect and reset callback Implement support for the hung queue detect and reset functionality. v2: Always use AMDGPU_MES_SCHED_PIPE Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 31 ++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index 24c61239b25da..ca06046c5d68d 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -47,6 +47,8 @@ static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev); #define MES_EOP_SIZE 2048 +#define MES12_HUNG_DB_OFFSET_ARRAY_SIZE 4 + static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -907,6 +909,32 @@ static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes, offsetof(union MESAPI__RESET, api_status)); } +static int mes_v12_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, + struct mes_detect_and_reset_queue_input *input) +{ + union MESAPI__RESET mes_reset_queue_pkt; + + memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); + + mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; + mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_reset_queue_pkt.queue_type = + convert_to_mes_queue_type(input->queue_type); + mes_reset_queue_pkt.doorbell_offset_addr = + mes->hung_queue_db_array_gpu_addr; + + if (input->detect_only) + mes_reset_queue_pkt.hang_detect_only = 1; + else + mes_reset_queue_pkt.hang_detect_then_reset = 1; + + return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, + &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), + offsetof(union MESAPI__RESET, api_status)); +} + static const struct amdgpu_mes_funcs mes_v12_0_funcs = { .add_hw_queue = mes_v12_0_add_hw_queue, .remove_hw_queue = mes_v12_0_remove_hw_queue, @@ -916,6 +944,7 @@ static const struct amdgpu_mes_funcs mes_v12_0_funcs = { .resume_gang = mes_v12_0_resume_gang, .misc_op = mes_v12_0_misc_op, .reset_hw_queue = mes_v12_0_reset_hw_queue, + .detect_and_reset_hung_queues = mes_v12_0_detect_and_reset_hung_queues, }; static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, @@ -1821,6 +1850,8 @@ static int mes_v12_0_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; int pipe, r; + adev->mes.hung_queue_db_array_size = + MES12_HUNG_DB_OFFSET_ARRAY_SIZE; for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { r = amdgpu_mes_init_microcode(adev, pipe); if (r) From 57c0bdc0e5fa144bd623a45bcd9d7b8b5534b493 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 16 Apr 2025 13:12:40 -0400 Subject: [PATCH 1853/2653] drm/amdgpu: add user queue reset source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Track resets from user queues. Signed-off-by: Alex Deucher Reviewed-by: Christian König Reviewed-by: Sunil Khatri --- drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 3 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c index 7eb3c81fe75a5..4c50530e7c327 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c @@ -349,6 +349,9 @@ void amdgpu_reset_get_desc(struct amdgpu_reset_context *rst_ctxt, char *buf, case AMDGPU_RESET_SRC_USER: strscpy(buf, "user trigger", len); break; + case AMDGPU_RESET_SRC_USERQ: + strscpy(buf, "user queue trigger", len); + break; default: strscpy(buf, "unknown", len); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h index 6b9f550cb0c24..fbf5e95dbd16e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h @@ -43,6 +43,7 @@ enum AMDGPU_RESET_SRCS { AMDGPU_RESET_SRC_MES, AMDGPU_RESET_SRC_HWS, AMDGPU_RESET_SRC_USER, + AMDGPU_RESET_SRC_USERQ, }; struct amdgpu_reset_context { From 25326a9c173e8ce1bdbaf844bdf352c9dbbd9f1c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 18 Apr 2025 11:35:49 -0400 Subject: [PATCH 1854/2653] drm/amdgpu/userq: add force completion helpers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for forcing completion of userq fences. This is needed for userq resets and asic resets so that we can set the error on the fence and force completion. Signed-off-by: Alex Deucher Reviewed-by: Christian König --- .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 42 +++++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.h | 1 + 2 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index c22630020057f..90d79cfe21146 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -67,6 +67,14 @@ static u64 amdgpu_userq_fence_read(struct amdgpu_userq_fence_driver *fence_drv) return le64_to_cpu(*fence_drv->cpu_addr); } +static void +amdgpu_userq_fence_write(struct amdgpu_userq_fence_driver *fence_drv, + u64 seq) +{ + if (fence_drv->cpu_addr) + *fence_drv->cpu_addr = cpu_to_le64(seq); +} + int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev, struct amdgpu_usermode_queue *userq) { @@ -471,6 +479,40 @@ static void amdgpu_userq_fence_cleanup(struct dma_fence *fence) dma_fence_put(fence); } +static void +amdgpu_userq_fence_driver_set_error(struct amdgpu_userq_fence *fence, + int error) +{ + struct amdgpu_userq_fence_driver *fence_drv = fence->fence_drv; + unsigned long flags; + struct dma_fence *f; + + spin_lock_irqsave(&fence_drv->fence_list_lock, flags); + + f = rcu_dereference_protected(&fence->base, + lockdep_is_held(&fence_drv->fence_list_lock)); + if (f && !dma_fence_is_signaled_locked(f)) + dma_fence_set_error(f, error); + spin_unlock_irqrestore(&fence_drv->fence_list_lock, flags); +} + +void +amdgpu_userq_fence_driver_force_completion(struct amdgpu_usermode_queue *userq) +{ + struct dma_fence *f = userq->last_fence; + + if (f) { + struct amdgpu_userq_fence *fence = to_amdgpu_userq_fence(f); + struct amdgpu_userq_fence_driver *fence_drv = fence->fence_drv; + u64 wptr = fence->base.seqno; + + amdgpu_userq_fence_driver_set_error(fence, -ECANCELED); + amdgpu_userq_fence_write(fence_drv, wptr); + amdgpu_userq_fence_driver_process(fence_drv); + + } +} + int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h index 97a125ab8a786..d76add2afc774 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h @@ -67,6 +67,7 @@ int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev, struct amdgpu_usermode_queue *userq); void amdgpu_userq_fence_driver_free(struct amdgpu_usermode_queue *userq); void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_drv); +void amdgpu_userq_fence_driver_force_completion(struct amdgpu_usermode_queue *userq); void amdgpu_userq_fence_driver_destroy(struct kref *ref); int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); From 81088e5ba0025de3c1bf3d0ce2a32c3b868abc79 Mon Sep 17 00:00:00 2001 From: Geoffrey McRae Date: Thu, 28 Aug 2025 22:26:22 +1000 Subject: [PATCH 1855/2653] drm/amd/display: remove oem i2c adapter on finish Fixes a bug where unbinding of the GPU would leave the oem i2c adapter registered resulting in a null pointer dereference when applications try to access the invalid device. Fixes: 3d5470c97314 ("drm/amd/display/dm: add support for OEM i2c bus") Cc: Harry Wentland Reviewed-by: Alex Deucher Signed-off-by: Geoffrey McRae Change-Id: I9466b489859c3963653976e54818254596b5a13b --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index eb54c6aa8582f..b2078b67a6452 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2996,6 +2996,17 @@ static int dm_oem_i2c_hw_init(struct amdgpu_device *adev) return 0; } +static void dm_oem_i2c_hw_fini(struct amdgpu_device *adev) +{ + struct amdgpu_display_manager *dm = &adev->dm; + + if (dm->oem_i2c) { + i2c_del_adapter(&dm->oem_i2c->base); + kfree(dm->oem_i2c); + dm->oem_i2c = NULL; + } +} + /** * dm_hw_init() - Initialize DC device * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. @@ -3046,7 +3057,7 @@ static int dm_hw_fini(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; - kfree(adev->dm.oem_i2c); + dm_oem_i2c_hw_fini(adev); amdgpu_dm_hpd_fini(adev); From 8ddc1ed75d91c044a24510eea20d6a31e06416a2 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Sun, 31 Aug 2025 15:29:56 +0530 Subject: [PATCH 1856/2653] drm/amdgpu: Fix function header names in amdgpu_connectors.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Align the function headers for `amdgpu_max_hdmi_pixel_clock` and `amdgpu_connector_dvi_mode_valid` with the function implementations so they match the expected kdoc style. Fixes the below: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1199: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Returns the maximum supported HDMI (TMDS) pixel clock in KHz. drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1212: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Validates the given display mode on DVI and HDMI connectors. Fixes: b80998750589 ("drm/amdgpu: Respect max pixel clock for HDMI and DVI-D (v2)") Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 69ec4489bec25..b636bc98a8177 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -1263,7 +1263,10 @@ static void amdgpu_connector_dvi_force(struct drm_connector *connector) } /** - * Returns the maximum supported HDMI (TMDS) pixel clock in KHz. + * amdgpu_max_hdmi_pixel_clock - Return max supported HDMI (TMDS) pixel clock + * @adev: pointer to amdgpu_device + * + * Return: maximum supported HDMI (TMDS) pixel clock in KHz. */ static int amdgpu_max_hdmi_pixel_clock(const struct amdgpu_device *adev) { @@ -1276,8 +1279,14 @@ static int amdgpu_max_hdmi_pixel_clock(const struct amdgpu_device *adev) } /** - * Validates the given display mode on DVI and HDMI connectors, - * including analog signals on DVI-I. + * amdgpu_connector_dvi_mode_valid - Validate a mode on DVI/HDMI connectors + * @connector: DRM connector to validate the mode on + * @mode: display mode to validate + * + * Validate the given display mode on DVI and HDMI connectors, including + * analog signals on DVI-I. + * + * Return: drm_mode_status indicating whether the mode is valid. */ static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, #ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT From 67de4ddecf4d32533c132536608152b2f6c3c8c0 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 27 Jun 2025 10:12:36 -0400 Subject: [PATCH 1857/2653] drm/amdgpu: add ip offset support for cyan skillfish For chips that don't have IP discovery tables. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/Makefile | 3 +- .../drm/amd/amdgpu/cyan_skillfish_reg_init.c | 56 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/nv.h | 1 + 3 files changed, 59 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 6c65806847cd5..7fe67d0e1cd60 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -84,7 +84,8 @@ amdgpu-y += \ vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o mxgpu_nv.o \ nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o soc24.o \ sienna_cichlid.o smu_v13_0_10.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o \ - nbio_v7_9.o aqua_vanjaram.o nbio_v7_11.o lsdma_v7_0.o hdp_v7_0.o nbif_v6_3_1.o + nbio_v7_9.o aqua_vanjaram.o nbio_v7_11.o lsdma_v7_0.o hdp_v7_0.o nbif_v6_3_1.o \ + cyan_skillfish_reg_init.o # add DF block amdgpu-y += \ diff --git a/drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c b/drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c new file mode 100644 index 0000000000000..96616a865aac7 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "nv.h" + +#include "soc15_common.h" +#include "soc15_hw_ip.h" +#include "cyan_skillfish_ip_offset.h" + +int cyan_skillfish_reg_base_init(struct amdgpu_device *adev) +{ + /* HW has more IP blocks, only initialized the blocke needed by driver */ + uint32_t i; + + adev->gfx.xcc_mask = 1; + for (i = 0 ; i < MAX_INSTANCE ; ++i) { + adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); + adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); + adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); + adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); + adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); + adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); + adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); + adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i])); + adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); + adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i])); + adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); + adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); + adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); + adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); + adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); + adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); + } + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h index 83e9782aef39d..8f4817404f10d 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.h +++ b/drivers/gpu/drm/amd/amdgpu/nv.h @@ -31,5 +31,6 @@ extern const struct amdgpu_ip_block_version nv_common_ip_block; void nv_grbm_select(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue, u32 vmid); void nv_set_virt_ops(struct amdgpu_device *adev); +int cyan_skillfish_reg_base_init(struct amdgpu_device *adev); #endif From af7d47226b77f74383315e5ea03d036b52f87d94 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 27 Jun 2025 10:18:46 -0400 Subject: [PATCH 1858/2653] drm/amdgpu: add support for cyan skillfish without IP discovery For platforms without an IP discovery table. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 322a989aca334..7dc50cd1c3443 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -2762,6 +2762,36 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); break; + case CHIP_CYAN_SKILLFISH: + if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { + r = amdgpu_discovery_reg_base_init(adev); + if (r) + return -EINVAL; + + amdgpu_discovery_harvest_ip(adev); + amdgpu_discovery_get_gfx_info(adev); + amdgpu_discovery_get_mall_info(adev); + amdgpu_discovery_get_vcn_info(adev); + } else { + cyan_skillfish_reg_base_init(adev); + adev->sdma.num_instances = 2; + adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3); + adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3); + adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1); + adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1); + adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1); + adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1); + adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0); + adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1); + adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1); + adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8); + adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8); + adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1); + adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8); + adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3); + adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3); + } + break; default: r = amdgpu_discovery_reg_base_init(adev); if (r) { From f2f22d8cfd78ec7f87ca723efedf61ee6b00cda5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 27 Jun 2025 10:21:16 -0400 Subject: [PATCH 1859/2653] drm/amdgpu: add support for cyan skillfish gpu_info Some SOCs which are part of the cyan skillfish family rely on an explicit firmware for IP discovery. Add support for the gpu_info firmware. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 0194b8e661838..05f4fe618ea51 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -97,6 +97,7 @@ MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin"); MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin"); MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin"); MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); +MODULE_FIRMWARE("amdgpu/cyan_skillfish_gpu_info.bin"); #define AMDGPU_RESUME_MS 2000 #define AMDGPU_MAX_RETRY_LIMIT 2 @@ -2654,6 +2655,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) return 0; chip_name = "navi12"; break; + case CHIP_CYAN_SKILLFISH: + chip_name = "cyan_skillfish"; + break; } err = amdgpu_ucode_request(adev, &adev->firmware.gpu_info_fw, From 634dbf0e70d2e7075fbc9dc711133800f13bdc56 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 27 Jun 2025 10:25:09 -0400 Subject: [PATCH 1860/2653] drm/amdgpu: don't enable SMU on cyan skillfish Cyan skillfish uses different SMU firmware. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 7dc50cd1c3443..bc5327b98e162 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -2140,7 +2140,6 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(11, 0, 5): case IP_VERSION(11, 0, 9): case IP_VERSION(11, 0, 7): - case IP_VERSION(11, 0, 8): case IP_VERSION(11, 0, 11): case IP_VERSION(11, 0, 12): case IP_VERSION(11, 0, 13): @@ -2148,6 +2147,10 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(11, 5, 2): amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); break; + case IP_VERSION(11, 0, 8): + if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) + amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); + break; case IP_VERSION(12, 0, 0): case IP_VERSION(12, 0, 1): amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); From 30c42db004c95ebd9b226f222689ae1dfbb5b5c7 Mon Sep 17 00:00:00 2001 From: Qianfeng Rong Date: Thu, 4 Sep 2025 20:36:46 +0800 Subject: [PATCH 1861/2653] drm/amdkfd: Fix error code sign for EINVAL in svm_ioctl() Use negative error code -EINVAL instead of positive EINVAL in the default case of svm_ioctl() to conform to Linux kernel error code conventions. Fixes: 42de677f7999 ("drm/amdkfd: register svm range") Signed-off-by: Qianfeng Rong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 7b7dbab6f999d..b7babbf9b963a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -4265,7 +4265,7 @@ svm_ioctl(struct kfd_process *p, enum kfd_ioctl_svm_op op, uint64_t start, r = svm_range_get_attr(p, mm, start, size, nattrs, attrs); break; default: - r = EINVAL; + r = -EINVAL; break; } From bc573d133c2185a8d77599a45dceb2408d433591 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Thu, 4 Sep 2025 09:54:36 +0800 Subject: [PATCH 1862/2653] drm/amdgpu/userq: add a detect and reset callback Add a detect and reset callback and add the implementation for mes. The callback will detect all hung queues of a particular ip type (e.g., GFX or compute or SDMA) and reset them. v2: increase reset counter and set fence force completion v3: Removed userq_mutex in mes_userq_detect_and_reset since the driver holds it when calling Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 2 + drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 49 ++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index 5c87704331dec..5e36e44223933 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -87,6 +87,8 @@ struct amdgpu_userq_funcs { struct amdgpu_usermode_queue *queue); int (*restore)(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_queue *queue); + int (*detect_and_reset)(struct amdgpu_device *adev, + int queue_type); }; /* Usermode queues for gfx */ diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index d6f50b13e2ba0..aee26f80bd530 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -21,6 +21,7 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ +#include #include "amdgpu.h" #include "amdgpu_gfx.h" #include "mes_userqueue.h" @@ -198,6 +199,53 @@ static int mes_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr, return 0; } +static int mes_userq_detect_and_reset(struct amdgpu_device *adev, + int queue_type) +{ + int db_array_size = amdgpu_mes_get_hung_queue_db_array_size(adev); + struct mes_detect_and_reset_queue_input input; + struct amdgpu_usermode_queue *queue; + struct amdgpu_userq_mgr *uqm, *tmp; + unsigned int hung_db_num = 0; + int queue_id, r, i; + u32 db_array[4]; + + if (db_array_size > 4) { + dev_err(adev->dev, "DB array size (%d vs 4) too small\n", + db_array_size); + return -EINVAL; + } + + memset(&input, 0x0, sizeof(struct mes_detect_and_reset_queue_input)); + + input.queue_type = queue_type; + + amdgpu_mes_lock(&adev->mes); + r = amdgpu_mes_detect_and_reset_hung_queues(adev, queue_type, false, + &hung_db_num, db_array); + amdgpu_mes_unlock(&adev->mes); + if (r) { + dev_err(adev->dev, "Failed to detect and reset queues, err (%d)\n", r); + } else if (hung_db_num) { + list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { + idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { + if (queue->queue_type == queue_type) { + for (i = 0; i < hung_db_num; i++) { + if (queue->doorbell_index == db_array[i]) { + queue->state = AMDGPU_USERQ_STATE_HUNG; + atomic_inc(&adev->gpu_reset_counter); + amdgpu_userq_fence_driver_force_completion(queue); + drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, NULL); + } + } + } + } + } + } + + return r; +} + static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, struct drm_amdgpu_userq_in *args_in, struct amdgpu_usermode_queue *queue) @@ -352,4 +400,5 @@ const struct amdgpu_userq_funcs userq_mes_funcs = { .mqd_destroy = mes_userq_mqd_destroy, .unmap = mes_userq_unmap, .map = mes_userq_map, + .detect_and_reset = mes_userq_detect_and_reset, }; From 15c06b3ab681140ed59549ed9a248593d1ff8176 Mon Sep 17 00:00:00 2001 From: Liao Yuanhong Date: Thu, 4 Sep 2025 15:10:15 +0800 Subject: [PATCH 1863/2653] drm/amd/display: Remove redundant ternary operators For ternary operators in the form of "a ? true : false" or "a ? false : true", if 'a' itself returns a boolean result, the ternary operator can be omitted. Remove redundant ternary operators to clean up the code. Signed-off-by: Liao Yuanhong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c | 2 +- .../drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c | 2 +- drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c | 2 +- drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c | 3 +-- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 4 ++-- 5 files changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c index e0558a78b11c2..1c12281164877 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c @@ -812,7 +812,7 @@ bool dcn10_link_encoder_validate_output_with_stream( enc10, &stream->timing); break; case SIGNAL_TYPE_EDP: - is_valid = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? true : false; + is_valid = stream->timing.pixel_encoding == PIXEL_ENCODING_RGB; break; case SIGNAL_TYPE_VIRTUAL: is_valid = true; diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c index 6ab2a218b7694..6f30b6cc3c761 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c @@ -397,7 +397,7 @@ static bool enc35_is_fifo_enabled(struct stream_encoder *enc) uint32_t reset_val; REG_GET(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, &reset_val); - return (reset_val == 0) ? false : true; + return reset_val != 0; } void enc35_disable_fifo(struct stream_encoder *enc) { diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c index 0318260370edf..9deb03a18ccc8 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c @@ -535,7 +535,7 @@ static bool dml2_validate_only(struct dc_state *context, enum dc_validate_mode v if (result) result = does_configuration_meet_sw_policies(dml2, &dml2->v20.scratch.cur_display_config, &dml2->v20.scratch.mode_support_info); - return (result == 1) ? true : false; + return result == 1; } static void dml2_apply_debug_options(const struct dc *dc, struct dml2_context *dml2) diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c index b68bcc9fca0a5..892907991f912 100644 --- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c +++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c @@ -138,8 +138,7 @@ void setup_dio_stream_attribute(struct pipe_ctx *pipe_ctx) stream_encoder->funcs->dvi_set_stream_attribute( stream_encoder, &stream->timing, - (stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? - true : false); + stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK); else if (dc_is_lvds_signal(stream->signal)) stream_encoder->funcs->lvds_set_stream_attribute( stream_encoder, diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 71efd2770c99c..ce421bcddcb08 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -226,8 +226,8 @@ static void update_v_total_for_static_ramp( unsigned int target_duration_in_us = calc_duration_in_us_from_refresh_in_uhz( in_out_vrr->fixed.target_refresh_in_uhz); - bool ramp_direction_is_up = (current_duration_in_us > - target_duration_in_us) ? true : false; + bool ramp_direction_is_up = current_duration_in_us > + target_duration_in_us; /* Calculate ratio between new and current frame duration with 3 digit */ unsigned int frame_duration_ratio = div64_u64(1000000, From 0217ac202add67f2591cbee64bc14323ce83eb06 Mon Sep 17 00:00:00 2001 From: Liao Yuanhong Date: Thu, 4 Sep 2025 16:21:11 +0800 Subject: [PATCH 1864/2653] amdgpu/pm/legacy: remove redundant ternary operators For ternary operators in the form of "a ? true : false", if 'a' itself returns a boolean result, the ternary operator can be omitted. Remove redundant ternary operators to clean up the code. Signed-off-by: Liao Yuanhong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c index ea3ace882a10a..52dbf6d0469df 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c @@ -771,8 +771,7 @@ static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev, int i; struct amdgpu_ps *ps; u32 ui_class; - bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ? - true : false; + bool single_display = adev->pm.dpm.new_active_crtc_count < 2; /* check if the vblank period is too short to adjust the mclk */ if (single_display && adev->powerplay.pp_funcs->vblank_too_short) { From 461a1f950d063e8ca58ca8c261cdbb57598f94d6 Mon Sep 17 00:00:00 2001 From: Liao Yuanhong Date: Thu, 4 Sep 2025 16:21:12 +0800 Subject: [PATCH 1865/2653] drm/amd/pm/powerplay/hwmgr/ppatomctrl: Remove redundant ternary operators For ternary operators in the form of "a ? true : false", if 'a' itself returns a boolean result, the ternary operator can be omitted. Remove redundant ternary operators to clean up the code. Swap variable positions on either side of '!=' to enhance readability. Signed-off-by: Liao Yuanhong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c index 8d40ed0f0e838..ce166a7f8e420 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c @@ -563,8 +563,8 @@ bool atomctrl_is_voltage_controlled_by_gpio_v3( PP_ASSERT_WITH_CODE((NULL != voltage_info), "Could not find Voltage Table in BIOS.", return false;); - ret = (NULL != atomctrl_lookup_voltage_type_v3 - (voltage_info, voltage_type, voltage_mode)) ? true : false; + ret = atomctrl_lookup_voltage_type_v3 + (voltage_info, voltage_type, voltage_mode) != NULL; return ret; } From 5be3c252d884e866da69e183c3a181829a335512 Mon Sep 17 00:00:00 2001 From: Liao Yuanhong Date: Thu, 4 Sep 2025 16:21:13 +0800 Subject: [PATCH 1866/2653] drm/amd/pm/powerplay/smumgr: remove redundant ternary operators For ternary operators in the form of "a ? true : false", if 'a' itself returns a boolean result, the ternary operator can be omitted. Remove redundant ternary operators to clean up the code. Swap variable positions on either side of '==' to enhance readability. Signed-off-by: Liao Yuanhong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c | 5 ++--- drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c | 5 ++--- drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c | 5 ++--- drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c | 5 ++--- 4 files changed, 8 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c index 5e43ad2b29564..d2dbd90bb427e 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c @@ -2540,9 +2540,8 @@ static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr) { - return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device, - CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON)) - ? true : false; + return PHM_READ_INDIRECT_FIELD(hwmgr->device, + CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) == 1; } static int fiji_update_dpm_settings(struct pp_hwmgr *hwmgr, diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c index 17d2f5bff4a7e..1f50f1e74c487 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c @@ -2655,9 +2655,8 @@ static int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) static bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr) { - return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device, - CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON)) - ? true : false; + return PHM_READ_INDIRECT_FIELD(hwmgr->device, + CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) == 1; } const struct pp_smumgr_func iceland_smu_funcs = { diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c index ff6b563ecbf51..bf6d09572cfc2 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c @@ -2578,9 +2578,8 @@ static int polaris10_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr) { - return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device, - CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON)) - ? true : false; + return PHM_READ_INDIRECT_FIELD(hwmgr->device, + CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) == 1; } static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr, diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c index 6fe6e6abb5d81..2e21f9d066cb0 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c @@ -3139,9 +3139,8 @@ static int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) static bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr) { - return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device, - CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON)) - ? true : false; + return PHM_READ_INDIRECT_FIELD(hwmgr->device, + CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) == 1; } static int tonga_update_dpm_settings(struct pp_hwmgr *hwmgr, From c7db68a44597ec0ce5db7ca1c9e91ffaec034164 Mon Sep 17 00:00:00 2001 From: Qianfeng Rong Date: Thu, 4 Sep 2025 22:58:00 +0800 Subject: [PATCH 1867/2653] drm/amd/pm: use int type to store negative error codes Use int instead of uint32_t for 'ret' variable to store negative error codes or zero returned by other functions. Storing the negative error codes in unsigned type, doesn't cause an issue at runtime but can be confusing. Additionally, assigning negative error codes to unsigned type may trigger a GCC warning when the -Wsign-conversion flag is enabled. No effect on runtime. Signed-off-by: Qianfeng Rong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 2 +- drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c index 9a821563bc8e9..14ccd743ca1d0 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c @@ -1032,7 +1032,7 @@ static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr, data->clock_vol_info.vdd_dep_on_fclk; uint32_t i, now, size = 0; uint32_t min_freq, max_freq = 0; - uint32_t ret = 0; + int ret = 0; switch (type) { case PP_SCLK: diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c index baf51cd82a350..0d4cbe4113a08 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/smu7_smumgr.c @@ -401,7 +401,7 @@ int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr) int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type) { struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); - uint32_t ret; + int ret; ret = phm_wait_on_indirect_register(hwmgr, mmSMC_IND_INDEX_11, smu_data->soft_regs_start + smum_get_offsetof(hwmgr, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c index e97b0cf19197e..3baf20f4c3736 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c @@ -470,7 +470,7 @@ static int renoir_od_edit_dpm_table(struct smu_context *smu, static int renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) { uint32_t min = 0, max = 0; - uint32_t ret = 0; + int ret = 0; ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinGfxclkFrequency, From cf17928b7cfda47422a9a71a77ce52170190ee75 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Wed, 3 Sep 2025 14:29:12 +0800 Subject: [PATCH 1868/2653] drm/amd/pm: refine amdgpu pm sysfs node error code v1: Returns different error codes based on the scenario to help the user app understand the AMDGPU device status when an exception occurs. v2: change -NODEV to -EBUSY. Signed-off-by: Yang Wang Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index c59bdd15e0e5c..0e6535df66cb8 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -110,9 +110,10 @@ static int amdgpu_pm_dev_state_check(struct amdgpu_device *adev, bool runpm) bool runpm_check = runpm ? adev->in_runpm : false; if (amdgpu_in_reset(adev)) - return -EPERM; + return -EBUSY; + if (adev->in_suspend && !runpm_check) - return -EPERM; + return -EBUSY; return 0; } From b728eda4ac3e4867b5db7ec206b5225da7f0fcb7 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 28 Aug 2025 10:02:35 +0530 Subject: [PATCH 1869/2653] drm/amd/pm: Add caching for SystemMetrics table Implement caching separately for SystemMetrics table from PMFW. The same table could be used for multiple interfaces. Hence, cache it internally to avoid multiple queries to the firmware. For SystemMetrics table, 5ms cache interval is sufficient. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 1 + .../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 43 +++++++++++++------ .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 4 ++ .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 1 + 4 files changed, 36 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 8ae1a3b714c74..be2edb3daa4b1 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -333,6 +333,7 @@ enum smu_table_id { SMU_TABLE_WIFIBAND, SMU_TABLE_GPUBOARD_TEMP_METRICS, SMU_TABLE_BASEBOARD_TEMP_METRICS, + SMU_TABLE_PMFW_SYSTEM_METRICS, SMU_TABLE_COUNT, }; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index 32fd0be05cffb..0bec12b348ced 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -149,6 +149,12 @@ int smu_v13_0_12_tables_init(struct smu_context *smu) struct smu_table_cache *cache; int ret; + ret = smu_table_cache_init(smu, SMU_TABLE_PMFW_SYSTEM_METRICS, + smu_v13_0_12_get_system_metrics_size(), 5); + + if (ret) + return ret; + ret = smu_table_cache_init(smu, SMU_TABLE_BASEBOARD_TEMP_METRICS, sizeof(*baseboard_temp_metrics), 50); if (ret) @@ -162,6 +168,7 @@ int smu_v13_0_12_tables_init(struct smu_context *smu) ret = smu_table_cache_init(smu, SMU_TABLE_GPUBOARD_TEMP_METRICS, sizeof(*gpuboard_temp_metrics), 50); if (ret) { + smu_table_cache_fini(smu, SMU_TABLE_PMFW_SYSTEM_METRICS); smu_table_cache_fini(smu, SMU_TABLE_BASEBOARD_TEMP_METRICS); return ret; } @@ -176,6 +183,7 @@ void smu_v13_0_12_tables_fini(struct smu_context *smu) { smu_table_cache_fini(smu, SMU_TABLE_BASEBOARD_TEMP_METRICS); smu_table_cache_fini(smu, SMU_TABLE_GPUBOARD_TEMP_METRICS); + smu_table_cache_fini(smu, SMU_TABLE_PMFW_SYSTEM_METRICS); } static int smu_v13_0_12_get_enabled_mask(struct smu_context *smu, @@ -222,8 +230,12 @@ static int smu_v13_0_12_fru_get_product_info(struct smu_context *smu, int smu_v13_0_12_get_max_metrics_size(void) { - return max3(sizeof(StaticMetricsTable_t), sizeof(MetricsTable_t), - sizeof(SystemMetricsTable_t)); + return max(sizeof(StaticMetricsTable_t), sizeof(MetricsTable_t)); +} + +size_t smu_v13_0_12_get_system_metrics_size(void) +{ + return sizeof(SystemMetricsTable_t); } static void smu_v13_0_12_init_xgmi_data(struct smu_context *smu, @@ -414,14 +426,18 @@ int smu_v13_0_12_get_smu_metrics_data(struct smu_context *smu, return 0; } -static int smu_v13_0_12_get_system_metrics_table(struct smu_context *smu, - void *metrics_table) +static int smu_v13_0_12_get_system_metrics_table(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; - uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size; struct smu_table *table = &smu_table->driver_table; + struct smu_table *tables = smu_table->tables; + struct smu_table *sys_table; int ret; + sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; + if (smu_table_cache_is_valid(sys_table)) + return 0; + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSystemMetricsTable, NULL); if (ret) { dev_info(smu->adev->dev, @@ -430,10 +446,9 @@ static int smu_v13_0_12_get_system_metrics_table(struct smu_context *smu, } amdgpu_asic_invalidate_hdp(smu->adev, NULL); - memcpy(smu_table->metrics_table, table->cpu_addr, table_size); - - if (metrics_table) - memcpy(metrics_table, smu_table->metrics_table, sizeof(SystemMetricsTable_t)); + smu_table_cache_update_time(sys_table, jiffies); + memcpy(sys_table->cache.buffer, table->cpu_addr, + smu_v13_0_12_get_system_metrics_size()); return 0; } @@ -571,10 +586,10 @@ static ssize_t smu_v13_0_12_get_temp_metrics(struct smu_context *smu, struct amdgpu_baseboard_temp_metrics_v1_0 *baseboard_temp_metrics; struct amdgpu_gpuboard_temp_metrics_v1_0 *gpuboard_temp_metrics; struct smu_table_context *smu_table = &smu->smu_table; - SystemMetricsTable_t *metrics = - (SystemMetricsTable_t *)smu_table->metrics_table; - + struct smu_table *tables = smu_table->tables; + SystemMetricsTable_t *metrics; struct smu_table *data_table; + struct smu_table *sys_table; int ret, sensor_type; u32 idx, sensors; ssize_t size; @@ -596,10 +611,12 @@ static ssize_t smu_v13_0_12_get_temp_metrics(struct smu_context *smu, size = sizeof(*baseboard_temp_metrics); } - ret = smu_v13_0_12_get_system_metrics_table(smu, NULL); + ret = smu_v13_0_12_get_system_metrics_table(smu); if (ret) return ret; + sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; + metrics = (SystemMetricsTable_t *)sys_table->cache.buffer; smu_table_cache_update_time(data_table, jiffies); if (type == SMU_TEMP_METRIC_GPUBOARD) { diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index ff197134fafe8..bc09867f87d5a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -567,6 +567,10 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu) PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT); + SMU_TABLE_INIT(tables, SMU_TABLE_PMFW_SYSTEM_METRICS, + smu_v13_0_12_get_system_metrics_size(), PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT); + metrics_table = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL); if (!metrics_table) return -ENOMEM; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h index bcb8246c08042..aae9a546a67e8 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h @@ -82,6 +82,7 @@ int smu_v13_0_6_get_metrics_table(struct smu_context *smu, void *metrics_table, bool smu_v13_0_12_is_dpm_running(struct smu_context *smu); int smu_v13_0_12_get_max_metrics_size(void); +size_t smu_v13_0_12_get_system_metrics_size(void); int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu); int smu_v13_0_12_get_smu_metrics_data(struct smu_context *smu, MetricsMember_t member, uint32_t *value); From 6d9b25b4ef3e090a1e52cab92dae5990f2a19858 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 28 Aug 2025 12:50:09 +0530 Subject: [PATCH 1870/2653] drm/amdgpu: Add vbios build number interface Fetch VBIOS build number from atom rom image. Add a sysfs interface to read the build number. Signed-off-by: Lijo Lazar Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 33 ++++++++++++++++++-- drivers/gpu/drm/amd/amdgpu/atom.c | 22 +++++++++++++ drivers/gpu/drm/amd/amdgpu/atom.h | 2 ++ 3 files changed, 54 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index ab48a0f960f6b..f137194b5db21 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -1816,17 +1816,44 @@ static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev, return sysfs_emit(buf, "%s\n", ctx->vbios_pn); } +static ssize_t amdgpu_atombios_get_vbios_build(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + struct atom_context *ctx = adev->mode_info.atom_context; + + return sysfs_emit(buf, "%s\n", ctx->build_num); +} + static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version, NULL); +static DEVICE_ATTR(vbios_build, 0444, amdgpu_atombios_get_vbios_build, NULL); #ifdef HAVE_PCI_DRIVER_DEV_GROUPS static struct attribute *amdgpu_vbios_version_attrs[] = { - &dev_attr_vbios_version.attr, - NULL + &dev_attr_vbios_version.attr, &dev_attr_vbios_build.attr, NULL }; +static umode_t amdgpu_vbios_version_attrs_is_visible(struct kobject *kobj, + struct attribute *attr, + int index) +{ + struct device *dev = kobj_to_dev(kobj); + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + struct atom_context *ctx = adev->mode_info.atom_context; + + if (attr == &dev_attr_vbios_build.attr && !strlen(ctx->build_num)) + return 0; + + return attr->mode; +} + const struct attribute_group amdgpu_vbios_version_attr_group = { - .attrs = amdgpu_vbios_version_attrs + .attrs = amdgpu_vbios_version_attrs, + .is_visible = amdgpu_vbios_version_attrs_is_visible, }; int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c index 427b073de2fc1..1c994d0cc50b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.c +++ b/drivers/gpu/drm/amd/amdgpu/atom.c @@ -1494,6 +1494,27 @@ static void atom_get_vbios_version(struct atom_context *ctx) } } +static void atom_get_vbios_build(struct atom_context *ctx) +{ + unsigned char *atom_rom_hdr; + unsigned char *str; + uint16_t base; + + base = CU16(ATOM_ROM_TABLE_PTR); + atom_rom_hdr = CSTR(base); + + str = CSTR(CU16(base + ATOM_ROM_CFG_PTR)); + /* Skip config string */ + while (str < atom_rom_hdr && *str++) + ; + /* Skip change list string */ + while (str < atom_rom_hdr && *str++) + ; + + if ((str + STRLEN_NORMAL) < atom_rom_hdr) + strscpy(ctx->build_num, str, STRLEN_NORMAL); +} + struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) { int base; @@ -1554,6 +1575,7 @@ struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) atom_get_vbios_pn(ctx); atom_get_vbios_date(ctx); atom_get_vbios_version(ctx); + atom_get_vbios_build(ctx); return ctx; } diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h b/drivers/gpu/drm/amd/amdgpu/atom.h index b807f6639a4c6..825ff28731f52 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.h +++ b/drivers/gpu/drm/amd/amdgpu/atom.h @@ -37,6 +37,7 @@ struct drm_device; #define ATOM_ROM_MAGIC "ATOM" #define ATOM_ROM_MAGIC_PTR 4 +#define ATOM_ROM_CFG_PTR 0xC #define ATOM_ROM_MSG_PTR 0x10 #define ATOM_ROM_CMD_PTR 0x1E #define ATOM_ROM_DATA_PTR 0x20 @@ -151,6 +152,7 @@ struct atom_context { uint32_t version; uint8_t vbios_ver_str[STRLEN_NORMAL]; uint8_t date[STRLEN_NORMAL]; + uint8_t build_num[STRLEN_NORMAL]; }; extern int amdgpu_atom_debug; From 5a2412023b777cb44511891ae874723f603586f5 Mon Sep 17 00:00:00 2001 From: Oleh Kuzhylnyi Date: Mon, 18 Aug 2025 13:19:29 +0200 Subject: [PATCH 1871/2653] drm/amd/display: Add HDCP policy control [Why] DM should be able to control HDCP retry limit via configurable parameter. [How] Expose a retry_limit parameter for controlling the maximum number of retries and lift the hardcode out to DM. Reviewed-by: Nicholas Kazlauskas Reviewed-by: Aric Cyr Signed-off-by: Oleh Kuzhylnyi Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 2 ++ drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c | 5 +++-- drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h | 1 + 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index 9e3e2291afe8f..0b9262f94cd9b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -223,6 +223,7 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_work, display_adjust.disable = MOD_HDCP_DISPLAY_NOT_DISABLE; link_adjust.auth_delay = 2; + link_adjust.retry_limit = MAX_NUM_OF_ATTEMPTS; if (content_type == DRM_MODE_HDCP_CONTENT_TYPE0) { link_adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0; @@ -578,6 +579,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) link->dp.usb4_enabled = config->usb4_enabled; display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION; link->adjust.auth_delay = 2; + link->adjust.retry_limit = MAX_NUM_OF_ATTEMPTS; link->adjust.hdcp1.disable = 0; hdcp_w->encryption_status[display->index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c index 5e01c6e24cbc8..c760216a62405 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c @@ -29,6 +29,7 @@ static void push_error_status(struct mod_hdcp *hdcp, enum mod_hdcp_status status) { struct mod_hdcp_trace *trace = &hdcp->connection.trace; + const uint8_t retry_limit = hdcp->connection.link.adjust.retry_limit; if (trace->error_count < MAX_NUM_OF_ERROR_TRACE) { trace->errors[trace->error_count].status = status; @@ -39,11 +40,11 @@ static void push_error_status(struct mod_hdcp *hdcp, if (is_hdcp1(hdcp)) { hdcp->connection.hdcp1_retry_count++; - if (hdcp->connection.hdcp1_retry_count == MAX_NUM_OF_ATTEMPTS) + if (hdcp->connection.hdcp1_retry_count == retry_limit) hdcp->connection.link.adjust.hdcp1.disable = 1; } else if (is_hdcp2(hdcp)) { hdcp->connection.hdcp2_retry_count++; - if (hdcp->connection.hdcp2_retry_count == MAX_NUM_OF_ATTEMPTS) + if (hdcp->connection.hdcp2_retry_count == retry_limit) hdcp->connection.link.adjust.hdcp2.disable = 1; } } diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h index c42468bb70ac7..b51ddf2846df8 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h @@ -220,6 +220,7 @@ struct mod_hdcp_link_adjustment_hdcp2 { struct mod_hdcp_link_adjustment { uint8_t auth_delay; + uint8_t retry_limit; struct mod_hdcp_link_adjustment_hdcp1 hdcp1; struct mod_hdcp_link_adjustment_hdcp2 hdcp2; }; From e42c557e22904a7b1acf22894aea335a7aa60ece Mon Sep 17 00:00:00 2001 From: Cruise Hung Date: Fri, 22 Aug 2025 15:45:03 +0800 Subject: [PATCH 1872/2653] drm/amd/display: Add link index in AUX and dpms [Why & How] Add the link index in DP AUX transfer and DPMS functions. Reviewed-by: Wenjing Liu Signed-off-by: Cruise Hung Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 17 +++++++++++++---- .../drm/amd/display/dc/link/link_detection.c | 2 +- drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 9 +++++---- 3 files changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c index bb4ac5042c803..673bb87d2c172 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c @@ -725,14 +725,18 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc, for (i = 0; i < AUX_MAX_RETRIES; i++) { DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION, LOG_FLAG_I2cAux_DceAux, - "dce_aux_transfer_with_retries: link_index=%u: START: retry %d of %d: address=0x%04x length=%u write=%d mot=%d", + "dce_aux_transfer_with_retries: link_index=%u: START: retry %d of %d: " + "address=0x%04x length=%u write=%d mot=%d is_i2c=%d is_dpia=%d ddc_hw_inst=%d", ddc && ddc->link ? ddc->link->link_index : UINT_MAX, i + 1, (int)AUX_MAX_RETRIES, payload->address, payload->length, (unsigned int) payload->write, - (unsigned int) payload->mot); + (unsigned int) payload->mot, + payload->i2c_over_aux, + (ddc->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? true : false, + ddc->link->ddc_hw_inst); if (payload->write) dce_aux_log_payload(" write", payload->data, payload->length, 16); @@ -746,7 +750,9 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc, DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION, LOG_FLAG_I2cAux_DceAux, - "dce_aux_transfer_with_retries: link_index=%u: END: retry %d of %d: address=0x%04x length=%u write=%d mot=%d: ret=%d operation_result=%d payload->reply=%u", + "dce_aux_transfer_with_retries: link_index=%u: END: retry %d of %d: " + "address=0x%04x length=%u write=%d mot=%d: ret=%d operation_result=%d " + "payload->reply=%u is_i2c=%d is_dpia=%d ddc_hw_inst=%d", ddc && ddc->link ? ddc->link->link_index : UINT_MAX, i + 1, (int)AUX_MAX_RETRIES, @@ -756,7 +762,10 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc, (unsigned int) payload->mot, ret, (int)operation_result, - (unsigned int) *payload->reply); + (unsigned int) *payload->reply, + payload->i2c_over_aux, + (ddc->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? true : false, + ddc->link->ddc_hw_inst); if (!payload->write) dce_aux_log_payload(" read", payload->data, ret > 0 ? ret : 0, 16); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index 827b630daf49a..b717e430051a0 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -656,7 +656,7 @@ static bool wait_for_entering_dp_alt_mode(struct dc_link *link) return true; is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc); - DC_LOG_DC("DP Alt mode state on HPD: %d\n", is_in_alt_mode); + DC_LOG_DC("DP Alt mode state on HPD: %d Link=%d\n", is_in_alt_mode, link->link_index); if (is_in_alt_mode) return true; diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index eff53d945f4ea..cc78710cc8078 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -2440,9 +2440,9 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx) if (pipe_ctx->stream->sink) { if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { - DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, + DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d\n", __func__, pipe_ctx->stream->sink->edid_caps.display_name, - pipe_ctx->stream->signal); + pipe_ctx->stream->signal, link->link_index); } } @@ -2555,9 +2555,10 @@ void link_set_dpms_on( if (pipe_ctx->stream->sink) { if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { - DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, + DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d\n", __func__, pipe_ctx->stream->sink->edid_caps.display_name, - pipe_ctx->stream->signal); + pipe_ctx->stream->signal, + link->link_index); } } From eca235c8dd8c2035b52b42b7a5d521b99237f030 Mon Sep 17 00:00:00 2001 From: Ausef Yousof Date: Thu, 21 Aug 2025 18:11:54 -0400 Subject: [PATCH 1873/2653] drm/amd/display: dont wait for pipe update during medupdate/highirq [why&how] control flag for the wait during pipe update wait for vupdate should be set if update type is not fast or med to prevent an invalid sleep operation Reviewed-by: Alvin Lee Signed-off-by: Ausef Yousof Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 39e5a2136ee78..8d30deba6724d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -4164,7 +4164,7 @@ static void commit_planes_for_stream(struct dc *dc, } if (dc->hwseq->funcs.wait_for_pipe_update_if_needed) - dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, top_pipe_to_program, update_type == UPDATE_TYPE_FAST); + dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, top_pipe_to_program, update_type < UPDATE_TYPE_FULL); if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) { if (dc->hwss.subvp_pipe_control_lock) From a580c4097d54707a048f11ab3142cc5270274926 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Sun, 24 Aug 2025 15:20:58 -0500 Subject: [PATCH 1874/2653] drm/amd/display: Indicate when custom brightness curves are in use [Why] There is a `scale` sysfs attribute that can be used to indicate when non-linear brightness scaling is in use. As Custom brightness curves work by linear interpolation of points the scale is no longer linear. [How] Indicate non-linear scaling when custom brightness curves in use and linear scaling otherwise. Reviewed-by: Alex Hung Signed-off-by: Mario Limonciello Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b2078b67a6452..b0d3677bfa435 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5139,8 +5139,11 @@ amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) } else props.brightness = props.max_brightness = MAX_BACKLIGHT_LEVEL; - if (caps->data_points && !(amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE)) + if (caps->data_points && !(amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE)) { drm_info(drm, "Using custom brightness curve\n"); + props.scale = BACKLIGHT_SCALE_NON_LINEAR; + } else + props.scale = BACKLIGHT_SCALE_LINEAR; props.type = BACKLIGHT_RAW; snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", From 152c16888412075d3d04201f918bac24681aa78b Mon Sep 17 00:00:00 2001 From: Allen Li Date: Mon, 25 Aug 2025 14:23:14 +0800 Subject: [PATCH 1875/2653] drm/amd/display: Read DPCD to obtain eDP capability information. [Why & How] Extend to read eDP general capability 2 in detect_edp_sink_caps(). Reviewed-by: Robin Chen Reviewed-by: Wenjing Liu Signed-off-by: Allen Li Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 1 + .../drm/amd/display/dc/link/protocols/link_dp_capability.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index 3a3ec38cdf8be..db669ccb1d587 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -1284,6 +1284,7 @@ struct dpcd_caps { union dp_receive_port0_cap receive_port0_cap; /* Indicates the number of SST links supported by MSO (Multi-Stream Output) */ uint8_t mso_cap_sst_links_supported; + uint8_t dp_edp_general_cap_2; }; union dpcd_sink_ext_caps { diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 7ff8b27db1e34..92ca475ca2d6c 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -2196,6 +2196,12 @@ void detect_edp_sink_caps(struct dc_link *link) DP_EDP_MSO_LINK_CAPABILITIES, (uint8_t *)&link->dpcd_caps.mso_cap_sst_links_supported, sizeof(link->dpcd_caps.mso_cap_sst_links_supported)); + /* + * Read eDP general capability 2 + */ + core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_2, + (uint8_t *)&link->dpcd_caps.dp_edp_general_cap_2, + sizeof(link->dpcd_caps.dp_edp_general_cap_2)); } bool dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap) From b7e2274c85df3aaaf9a4bbe5cdec34d8843b1a46 Mon Sep 17 00:00:00 2001 From: Wenjing Liu Date: Wed, 13 Aug 2025 16:18:53 -0400 Subject: [PATCH 1876/2653] drm/amd/display: Update dchubbub.h for hubbub perfmon support [why] dchubbub supports performance monitoring for hubbub. The interfaces define the performance monitoring events and their attributes. Reviewed-by: Alvin Lee Signed-off-by: Wenjing Liu Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h index 9bee45b36629d..843a18287c83f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h @@ -137,6 +137,19 @@ struct dcn_hubbub_state { uint32_t dram_state_cntl; }; +struct hubbub_system_latencies { + uint32_t max_latency_ns; + uint32_t avg_latency_ns; + uint32_t min_latency_ns; +}; + +struct hubbub_urgent_latency_params { + uint32_t refclk_mhz; + uint32_t t_win_ns; + uint32_t bandwidth_mbps; + uint32_t bw_factor_x1000; +}; + struct hubbub_funcs { void (*update_dchub)( struct hubbub *hubbub, @@ -231,6 +244,15 @@ struct hubbub_funcs { bool (*program_arbiter)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower); void (*get_det_sizes)(struct hubbub *hubbub, uint32_t *curr_det_sizes, uint32_t *target_det_sizes); uint32_t (*compbuf_config_error)(struct hubbub *hubbub); + struct hubbub_perfmon_funcs{ + void (*start_system_latency_measurement)(struct hubbub *hubbub); + void (*get_system_latency_result)(struct hubbub *hubbub, uint32_t refclk_mhz, struct hubbub_system_latencies *latencies); + void (*start_in_order_bandwidth_measurement)(struct hubbub *hubbub); + void (*get_in_order_bandwidth_result)(struct hubbub *hubbub, uint32_t refclk_mhz, uint32_t *bandwidth_mbps); + void (*start_urgent_ramp_latency_measurement)(struct hubbub *hubbub, const struct hubbub_urgent_latency_params *params); + void (*get_urgent_ramp_latency_result)(struct hubbub *hubbub, uint32_t refclk_mhz, uint32_t *latency_ns); + void (*reset)(struct hubbub *hubbub); + } perfmon; }; struct hubbub { From 09a5e8a3cbdae9647bb57aab9e685ee75f5bae03 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Thu, 21 Aug 2025 15:43:31 -0400 Subject: [PATCH 1877/2653] drm/amd/display: Refine error message for vblank init failure [Why] The error message "failed to initialize sw for display support" is used for both DRM device and vblank initialization failures, making it difficult to identify the specific failure during troubleshooting. [How] Update the vblank initialization error message to "failed to initialize vblank for display support" to distinguish it from the DRM device init failure. Reviewed-by: Aurabindo Pillai Signed-off-by: Roman Li Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b0d3677bfa435..80236677301fa 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2220,7 +2220,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { drm_err(adev_to_drm(adev), - "failed to initialize sw for display support.\n"); + "failed to initialize vblank for display support.\n"); goto error; } From 0cbc548855d7f2446ad198ee67aefc47e3427c67 Mon Sep 17 00:00:00 2001 From: Ovidiu Bunea Date: Mon, 25 Aug 2025 14:45:33 -0400 Subject: [PATCH 1878/2653] drm/amd/display: Correct sequences and delays for DCN35 PG & RCG [why] The current PG & RCG programming in driver has some gaps and incorrect sequences. [how] Added delays after ungating clocks to allow ramp up, increased polling to allow more time for power up, and removed the incorrect sequences. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Charlene Liu Signed-off-by: Ovidiu Bunea Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../amd/display/dc/dccg/dcn35/dcn35_dccg.c | 74 +++++------ .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 115 +++--------------- .../amd/display/dc/hwss/dcn35/dcn35_init.c | 3 - .../amd/display/dc/hwss/dcn351/dcn351_init.c | 3 - .../gpu/drm/amd/display/dc/inc/hw/pg_cntl.h | 1 + .../amd/display/dc/pg/dcn35/dcn35_pg_cntl.c | 78 +++++++----- 7 files changed, 111 insertions(+), 164 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 8b2767bb40950..47f7855678dc6 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1165,6 +1165,7 @@ struct dc_debug_options { unsigned int auxless_alpm_lfps_silence_ns; unsigned int auxless_alpm_lfps_t1t2_us; short auxless_alpm_lfps_t1t2_offset_us; + bool enable_pg_cntl_debug_logs; }; diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index 58c84f555c0fb..0ce9489ac6b72 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -133,30 +133,34 @@ enum dsc_clk_source { }; -static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool enable) +static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool allow_rcg) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && enable) + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && allow_rcg) return; switch (inst) { case 0: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, enable ? 0 : 1); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); break; case 1: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, enable ? 0 : 1); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); break; case 2: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, enable ? 0 : 1); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); break; case 3: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, enable ? 0 : 1); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); break; default: BREAK_TO_DEBUGGER(); return; } + + /* Wait for clock to ramp */ + if (!allow_rcg) + udelay(10); } static void dccg35_set_symclk32_se_rcg( @@ -385,35 +389,34 @@ static void dccg35_set_dtbclk_p_rcg(struct dccg *dccg, int inst, bool enable) } } -static void dccg35_set_dppclk_rcg(struct dccg *dccg, - int inst, bool enable) +static void dccg35_set_dppclk_rcg(struct dccg *dccg, int inst, bool allow_rcg) { - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable) + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && allow_rcg) return; switch (inst) { case 0: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, enable ? 0 : 1); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); break; case 1: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, enable ? 0 : 1); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); break; case 2: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, enable ? 0 : 1); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); break; case 3: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, enable ? 0 : 1); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, allow_rcg ? 0 : 1); break; default: BREAK_TO_DEBUGGER(); break; } - //DC_LOG_DEBUG("%s: inst(%d) DPPCLK rcg_disable: %d\n", __func__, inst, enable ? 0 : 1); + /* Wait for clock to ramp */ + if (!allow_rcg) + udelay(10); } static void dccg35_set_dpstreamclk_rcg( @@ -1177,32 +1180,34 @@ static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, } static void dccg35_set_dppclk_root_clock_gating(struct dccg *dccg, - uint32_t dpp_inst, uint32_t enable) + uint32_t dpp_inst, uint32_t disallow_rcg) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && !disallow_rcg) return; switch (dpp_inst) { case 0: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, enable); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, disallow_rcg); break; case 1: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, enable); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, disallow_rcg); break; case 2: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, enable); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, disallow_rcg); break; case 3: - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, enable); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, disallow_rcg); break; default: break; } - //DC_LOG_DEBUG("%s: dpp_inst(%d) rcg: %d\n", __func__, dpp_inst, enable); + /* Wait for clock to ramp */ + if (disallow_rcg) + udelay(10); } static void dccg35_get_pixel_rate_div( @@ -1782,8 +1787,7 @@ static void dccg35_enable_dscclk(struct dccg *dccg, int inst) //Disable DTO switch (inst) { case 0: - if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, 1); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, 1); REG_UPDATE_2(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, 0, @@ -1791,8 +1795,7 @@ static void dccg35_enable_dscclk(struct dccg *dccg, int inst) REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, 1); break; case 1: - if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, 1); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, 1); REG_UPDATE_2(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, 0, @@ -1800,8 +1803,7 @@ static void dccg35_enable_dscclk(struct dccg *dccg, int inst) REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 1); break; case 2: - if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, 1); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, 1); REG_UPDATE_2(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, 0, @@ -1809,8 +1811,7 @@ static void dccg35_enable_dscclk(struct dccg *dccg, int inst) REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 1); break; case 3: - if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) - REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, 1); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, 1); REG_UPDATE_2(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_PHASE, 0, @@ -1821,6 +1822,9 @@ static void dccg35_enable_dscclk(struct dccg *dccg, int inst) BREAK_TO_DEBUGGER(); return; } + + /* Wait for clock to ramp */ + udelay(10); } static void dccg35_disable_dscclk(struct dccg *dccg, @@ -1864,6 +1868,9 @@ static void dccg35_disable_dscclk(struct dccg *dccg, default: return; } + + /* Wait for clock ramp */ + udelay(10); } static void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) @@ -2349,10 +2356,7 @@ static void dccg35_disable_symclk_se_cb( void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating) { - - if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) { - dccg35_set_dppclk_root_clock_gating(dccg, pipe_idx, disable_clock_gating); - } + dccg35_set_dppclk_root_clock_gating(dccg, pipe_idx, disable_clock_gating); } static const struct dccg_funcs dccg35_funcs_new = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index a267f574b6193..764eff6a4ec6b 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -113,6 +113,14 @@ static void enable_memory_low_power(struct dc *dc) } #endif +static void print_pg_status(struct dc *dc, const char *debug_func, const char *debug_log) +{ + if (dc->debug.enable_pg_cntl_debug_logs && dc->res_pool->pg_cntl) { + if (dc->res_pool->pg_cntl->funcs->print_pg_status) + dc->res_pool->pg_cntl->funcs->print_pg_status(dc->res_pool->pg_cntl, debug_func, debug_log); + } +} + void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable) { REG_UPDATE_3(DMU_CLK_CNTL, @@ -137,6 +145,8 @@ void dcn35_init_hw(struct dc *dc) uint32_t user_level = MAX_BACKLIGHT_LEVEL; int i; + print_pg_status(dc, __func__, ": start"); + if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); @@ -200,10 +210,7 @@ void dcn35_init_hw(struct dc *dc) /* we want to turn off all dp displays before doing detection */ dc->link_srv->blank_all_dp_displays(dc); -/* - if (hws->funcs.enable_power_gating_plane) - hws->funcs.enable_power_gating_plane(dc->hwseq, true); -*/ + if (res_pool->hubbub && res_pool->hubbub->funcs->dchubbub_init) res_pool->hubbub->funcs->dchubbub_init(dc->res_pool->hubbub); /* If taking control over from VBIOS, we may want to optimize our first @@ -236,6 +243,8 @@ void dcn35_init_hw(struct dc *dc) } hws->funcs.init_pipes(dc, dc->current_state); + print_pg_status(dc, __func__, ": after init_pipes"); + if (dc->res_pool->hubbub->funcs->allow_self_refresh_control && !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter) dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, @@ -312,6 +321,7 @@ void dcn35_init_hw(struct dc *dc) if (dc->res_pool->pg_cntl->funcs->init_pg_status) dc->res_pool->pg_cntl->funcs->init_pg_status(dc->res_pool->pg_cntl); } + print_pg_status(dc, __func__, ": after init_pg_status"); } static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) @@ -500,97 +510,6 @@ void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_ } } -void dcn35_dsc_pg_control( - struct dce_hwseq *hws, - unsigned int dsc_inst, - bool power_on) -{ - uint32_t power_gate = power_on ? 0 : 1; - uint32_t pwr_status = power_on ? 0 : 2; - uint32_t org_ip_request_cntl = 0; - - if (hws->ctx->dc->debug.disable_dsc_power_gate) - return; - if (hws->ctx->dc->debug.ignore_pg) - return; - REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); - if (org_ip_request_cntl == 0) - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); - - switch (dsc_inst) { - case 0: /* DSC0 */ - REG_UPDATE(DOMAIN16_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); - - REG_WAIT(DOMAIN16_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - case 1: /* DSC1 */ - REG_UPDATE(DOMAIN17_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); - - REG_WAIT(DOMAIN17_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - case 2: /* DSC2 */ - REG_UPDATE(DOMAIN18_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); - - REG_WAIT(DOMAIN18_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - case 3: /* DSC3 */ - REG_UPDATE(DOMAIN19_PG_CONFIG, - DOMAIN_POWER_GATE, power_gate); - - REG_WAIT(DOMAIN19_PG_STATUS, - DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); - break; - default: - BREAK_TO_DEBUGGER(); - break; - } - - if (org_ip_request_cntl == 0) - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); -} - -void dcn35_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) -{ - bool force_on = true; /* disable power gating */ - uint32_t org_ip_request_cntl = 0; - - if (hws->ctx->dc->debug.disable_hubp_power_gate) - return; - if (hws->ctx->dc->debug.ignore_pg) - return; - REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); - if (org_ip_request_cntl == 0) - REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); - /* DCHUBP0/1/2/3/4/5 */ - REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); - REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); - /* DPP0/1/2/3/4/5 */ - REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); - REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); - - force_on = true; /* disable power gating */ - if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) - force_on = false; - - /* DCS0/1/2/3/4 */ - REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); - REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); - REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); - REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); - - -} - /* In headless boot cases, DIG may be turned * on which causes HW/SW discrepancies. * To avoid this, power down hardware on boot @@ -1453,6 +1372,8 @@ void dcn35_prepare_bandwidth( } dcn20_prepare_bandwidth(dc, context); + + print_pg_status(dc, __func__, ": after rcg and power up"); } void dcn35_optimize_bandwidth( @@ -1461,6 +1382,8 @@ void dcn35_optimize_bandwidth( { struct pg_block_update pg_update_state; + print_pg_status(dc, __func__, ": before rcg and power up"); + dcn20_optimize_bandwidth(dc, context); if (dc->hwss.calc_blocks_to_gate) { @@ -1472,6 +1395,8 @@ void dcn35_optimize_bandwidth( if (dc->hwss.root_clock_control) dc->hwss.root_clock_control(dc, &pg_update_state, false); } + + print_pg_status(dc, __func__, ": after rcg and power up"); } void dcn35_set_drr(struct pipe_ctx **pipe_ctx, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c index 52cc488416ac1..f2f16a0bdb4f3 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c @@ -115,7 +115,6 @@ static const struct hw_sequencer_funcs dcn35_funcs = { .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, .update_visual_confirm_color = dcn10_update_visual_confirm_color, .apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations, - .update_dsc_pg = dcn32_update_dsc_pg, .calc_blocks_to_gate = dcn35_calc_blocks_to_gate, .calc_blocks_to_ungate = dcn35_calc_blocks_to_ungate, .hw_block_power_up = dcn35_hw_block_power_up, @@ -151,7 +150,6 @@ static const struct hwseq_private_funcs dcn35_private_funcs = { .plane_atomic_disable = dcn35_plane_atomic_disable, //.plane_atomic_disable = dcn20_plane_atomic_disable,/*todo*/ //.hubp_pg_control = dcn35_hubp_pg_control, - .enable_power_gating_plane = dcn35_enable_power_gating_plane, .dpp_root_clock_control = dcn35_dpp_root_clock_control, .dpstream_root_clock_control = dcn35_dpstream_root_clock_control, .physymclk_root_clock_control = dcn35_physymclk_root_clock_control, @@ -166,7 +164,6 @@ static const struct hwseq_private_funcs dcn35_private_funcs = { .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values, .resync_fifo_dccg_dio = dcn314_resync_fifo_dccg_dio, .is_dp_dig_pixel_rate_div_policy = dcn35_is_dp_dig_pixel_rate_div_policy, - .dsc_pg_control = dcn35_dsc_pg_control, .dsc_pg_status = dcn32_dsc_pg_status, .enable_plane = dcn35_enable_plane, .wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c index e34efcb7bde5e..09e60158f0b5a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c @@ -114,7 +114,6 @@ static const struct hw_sequencer_funcs dcn351_funcs = { .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, .update_visual_confirm_color = dcn10_update_visual_confirm_color, .apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations, - .update_dsc_pg = dcn32_update_dsc_pg, .calc_blocks_to_gate = dcn351_calc_blocks_to_gate, .calc_blocks_to_ungate = dcn351_calc_blocks_to_ungate, .hw_block_power_up = dcn351_hw_block_power_up, @@ -146,7 +145,6 @@ static const struct hwseq_private_funcs dcn351_private_funcs = { .plane_atomic_disable = dcn35_plane_atomic_disable, //.plane_atomic_disable = dcn20_plane_atomic_disable,/*todo*/ //.hubp_pg_control = dcn35_hubp_pg_control, - .enable_power_gating_plane = dcn35_enable_power_gating_plane, .dpp_root_clock_control = dcn35_dpp_root_clock_control, .dpstream_root_clock_control = dcn35_dpstream_root_clock_control, .physymclk_root_clock_control = dcn35_physymclk_root_clock_control, @@ -160,7 +158,6 @@ static const struct hwseq_private_funcs dcn351_private_funcs = { .setup_hpo_hw_control = dcn35_setup_hpo_hw_control, .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values, .is_dp_dig_pixel_rate_div_policy = dcn35_is_dp_dig_pixel_rate_div_policy, - .dsc_pg_control = dcn35_dsc_pg_control, .dsc_pg_status = dcn32_dsc_pg_status, .enable_plane = dcn35_enable_plane, .wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h b/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h index 44f86cc2d1d68..227e3f8d7e5f5 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h @@ -49,6 +49,7 @@ struct pg_cntl_funcs { void (*mem_pg_control)(struct pg_cntl *pg_cntl, bool power_on); void (*dio_pg_control)(struct pg_cntl *pg_cntl, bool power_on); void (*init_pg_status)(struct pg_cntl *pg_cntl); + void (*print_pg_status)(struct pg_cntl *pg_cntl, const char *debug_func, const char *debug_log); }; #endif //__DC_PG_CNTL_H__ diff --git a/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c index af21c0a27f865..72bd43f9bbe28 100644 --- a/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c +++ b/drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c @@ -79,16 +79,12 @@ void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bo uint32_t power_gate = power_on ? 0 : 1; uint32_t pwr_status = power_on ? 0 : 2; uint32_t org_ip_request_cntl = 0; - bool block_enabled; - - /*need to enable dscclk regardless DSC_PG*/ - if (pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc && power_on) - pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc( - pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); + bool block_enabled = false; + bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->debug.disable_dsc_power_gate || + pg_cntl->ctx->dc->idle_optimizations_allowed; - if (pg_cntl->ctx->dc->debug.ignore_pg || - pg_cntl->ctx->dc->debug.disable_dsc_power_gate || - pg_cntl->ctx->dc->idle_optimizations_allowed) + if (skip_pg && !power_on) return; block_enabled = pg_cntl35_dsc_pg_status(pg_cntl, dsc_inst); @@ -111,7 +107,7 @@ void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bo REG_WAIT(DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); + 1, 10000); break; case 1: /* DSC1 */ REG_UPDATE(DOMAIN17_PG_CONFIG, @@ -119,7 +115,7 @@ void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bo REG_WAIT(DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); + 1, 10000); break; case 2: /* DSC2 */ REG_UPDATE(DOMAIN18_PG_CONFIG, @@ -127,7 +123,7 @@ void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bo REG_WAIT(DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); + 1, 10000); break; case 3: /* DSC3 */ REG_UPDATE(DOMAIN19_PG_CONFIG, @@ -135,7 +131,7 @@ void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bo REG_WAIT(DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, - 1, 1000); + 1, 10000); break; default: BREAK_TO_DEBUGGER(); @@ -144,12 +140,6 @@ void pg_cntl35_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bo if (dsc_inst < MAX_PIPES) pg_cntl->pg_pipe_res_enable[PG_DSC][dsc_inst] = power_on; - - if (pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) { - /*this is to disable dscclk*/ - pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc( - pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); - } } static bool pg_cntl35_hubp_dpp_pg_status(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst) @@ -189,11 +179,12 @@ void pg_cntl35_hubp_dpp_pg_control(struct pg_cntl *pg_cntl, unsigned int hubp_dp uint32_t pwr_status = power_on ? 0 : 2; uint32_t org_ip_request_cntl; bool block_enabled; + bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->debug.disable_hubp_power_gate || + pg_cntl->ctx->dc->debug.disable_dpp_power_gate || + pg_cntl->ctx->dc->idle_optimizations_allowed; - if (pg_cntl->ctx->dc->debug.ignore_pg || - pg_cntl->ctx->dc->debug.disable_hubp_power_gate || - pg_cntl->ctx->dc->debug.disable_dpp_power_gate || - pg_cntl->ctx->dc->idle_optimizations_allowed) + if (skip_pg && !power_on) return; block_enabled = pg_cntl35_hubp_dpp_pg_status(pg_cntl, hubp_dpp_inst); @@ -213,22 +204,22 @@ void pg_cntl35_hubp_dpp_pg_control(struct pg_cntl *pg_cntl, unsigned int hubp_dp case 0: /* DPP0 & HUBP0 */ REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000); break; case 1: /* DPP1 & HUBP1 */ REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000); break; case 2: /* DPP2 & HUBP2 */ REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000); break; case 3: /* DPP3 & HUBP3 */ REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); - REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 10000); break; default: BREAK_TO_DEBUGGER(); @@ -501,6 +492,36 @@ void pg_cntl35_init_pg_status(struct pg_cntl *pg_cntl) pg_cntl->pg_res_enable[PG_DWB] = block_enabled; } +static void pg_cntl35_print_pg_status(struct pg_cntl *pg_cntl, const char *debug_func, const char *debug_log) +{ + int i = 0; + bool block_enabled = false; + + DC_LOG_DEBUG("%s: %s", debug_func, debug_log); + + DC_LOG_DEBUG("PG_CNTL status:\n"); + + block_enabled = pg_cntl35_io_clk_status(pg_cntl); + DC_LOG_DEBUG("ONO0=%d (DCCG, DIO, DCIO)\n", block_enabled ? 1 : 0); + + block_enabled = pg_cntl35_mem_status(pg_cntl); + DC_LOG_DEBUG("ONO1=%d (DCHUBBUB, DCHVM, DCHUBBUBMEM)\n", block_enabled ? 1 : 0); + + block_enabled = pg_cntl35_plane_otg_status(pg_cntl); + DC_LOG_DEBUG("ONO2=%d (MPC, OPP, OPTC, DWB)\n", block_enabled ? 1 : 0); + + block_enabled = pg_cntl35_hpo_pg_status(pg_cntl); + DC_LOG_DEBUG("ONO3=%d (HPO)\n", block_enabled ? 1 : 0); + + for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { + block_enabled = pg_cntl35_hubp_dpp_pg_status(pg_cntl, i); + DC_LOG_DEBUG("ONO%d=%d (DCHUBP%d, DPP%d)\n", 4 + i * 2, block_enabled ? 1 : 0, i, i); + + block_enabled = pg_cntl35_dsc_pg_status(pg_cntl, i); + DC_LOG_DEBUG("ONO%d=%d (DSC%d)\n", 5 + i * 2, block_enabled ? 1 : 0, i); + } +} + static const struct pg_cntl_funcs pg_cntl35_funcs = { .init_pg_status = pg_cntl35_init_pg_status, .dsc_pg_control = pg_cntl35_dsc_pg_control, @@ -511,7 +532,8 @@ static const struct pg_cntl_funcs pg_cntl35_funcs = { .mpcc_pg_control = pg_cntl35_mpcc_pg_control, .opp_pg_control = pg_cntl35_opp_pg_control, .optc_pg_control = pg_cntl35_optc_pg_control, - .dwb_pg_control = pg_cntl35_dwb_pg_control + .dwb_pg_control = pg_cntl35_dwb_pg_control, + .print_pg_status = pg_cntl35_print_pg_status }; struct pg_cntl *pg_cntl35_create( From e8528517b2ea89740c003d624513313c89d21ee5 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 29 Aug 2025 09:45:27 -0500 Subject: [PATCH 1879/2653] drm/amd/display: Promote DC to 3.2.349 This version brings along following updates: - Disable stutter when programming watermarks on dcn32 - Fix pbn_div Calculation Error - Correct sequences and delays for DCN35 PG & RCG - Define interfaces for hubbub perfmance monitoring support - Extend to read eDP general capability 2 - Indicate when custom brightness curves are in use - Dont wait for pipe update during medupdate/highirq - Add HDCP retry_limit control parameter Acked-by: Tom Chung Signed-off-by: Taimur Hassan Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 47f7855678dc6..6fa5b6b547b34 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.348" +#define DC_VER "3.2.349" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From 284967915fd3ad42f726e4940ba23889d53c34fe Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 18 Aug 2025 12:51:25 +0530 Subject: [PATCH 1880/2653] drm/amdgpu: print root PD address in PDE format instead of GPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Print PD address of VM root instead of GPU address in the debugfs. On modern GPU's this is what UMR tool expects in the registers as well. Fixes: 719b378d ("drm/amdgpu: add debugfs support for VM pagetable per client") Signed-off-by: Sunil Khatri Reviewed-by: Alex Deucher Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 39ba6790999da..6fdcd9c783247 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -2163,7 +2163,7 @@ static int amdgpu_pt_info_read(struct seq_file *m, void *unused) return -EINVAL; } - seq_printf(m, "gpu_address: 0x%llx\n", amdgpu_bo_gpu_offset(fpriv->vm.root.bo)); + seq_printf(m, "pd_address: 0x%llx\n", amdgpu_gmc_pd_addr(fpriv->vm.root.bo)); seq_printf(m, "max_pfn: 0x%llx\n", adev->vm_manager.max_pfn); seq_printf(m, "num_level: 0x%x\n", adev->vm_manager.num_level); seq_printf(m, "block_size: 0x%x\n", adev->vm_manager.block_size); From 9fd288b658f42d5946e2bae3f2d19c99b8cec1d5 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Sun, 31 Aug 2025 15:16:04 +0530 Subject: [PATCH 1881/2653] drm/amdgpu: Correct misnamed function in amdgpu_gem.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The header comment above amdgpu_gem_list_handles_ioctl referenced drm_amdgpu_gem_list_handles_ioctl. Update the comment to reflect the actual function identifier to avoid misleading prototype warnings. Fixes the below: drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c:1106: warning: expecting prototype for drm_amdgpu_gem_list_handles_ioctl(). Prototype was for amdgpu_gem_list_handles_ioctl() instead Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index d4760b0e90d9f..1e07f3cb9db28 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -1249,7 +1249,7 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, } /** - * drm_amdgpu_gem_list_handles_ioctl - get information about a process' buffer objects + * amdgpu_gem_list_handles_ioctl - get information about a process' buffer objects * * @dev: drm device pointer * @data: drm_amdgpu_gem_list_handles From fd7896a6d83a20a18db3062254c3e921d5d79a77 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 4 Sep 2025 21:58:49 +0300 Subject: [PATCH 1882/2653] drm/amdgpu: Fix error codes if copy_to_user() fails The copy_to_user() function returns the number of bytes that it wasn't able to copy, but we should return -EFAULT to the user. Fixes: 4d82724f7f2b ("drm/amdgpu: Add mapping info option for GEM_OP ioctl") Fixes: f9db1fc52ceb ("drm/amdgpu: Add ioctl to get all gem handles for a process") Reviewed-By: David Francis Signed-off-by: Dan Carpenter Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 1e07f3cb9db28..e0a4332b82204 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -1228,7 +1228,8 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, drm_exec_fini(&exec); if (num_mappings > 0 && num_mappings <= args->num_entries) - r = copy_to_user(u64_to_user_ptr(args->value), vm_entries, num_mappings * sizeof(*vm_entries)); + if (copy_to_user(u64_to_user_ptr(args->value), vm_entries, num_mappings * sizeof(*vm_entries))) + r = -EFAULT; args->num_entries = num_mappings; @@ -1320,7 +1321,8 @@ int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data, args->num_entries = bo_index; if (!ret) - ret = copy_to_user(u64_to_user_ptr(args->entries), bo_entries, num_bos * sizeof(*bo_entries)); + if (copy_to_user(u64_to_user_ptr(args->entries), bo_entries, num_bos * sizeof(*bo_entries))) + ret = -EFAULT; kvfree(bo_entries); From b17c9426f9bfbade94d82f14fc0545080413485b Mon Sep 17 00:00:00 2001 From: "Mario Limonciello (AMD)" Date: Fri, 5 Sep 2025 10:36:27 -0500 Subject: [PATCH 1883/2653] drm/amd/display: Drop dm_prepare_suspend() and dm_complete() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [Why] dm_prepare_suspend() was added in commit 50e0bae34fa6b ("drm/amd/display: Add and use new dm_prepare_suspend() callback") to allow display to turn off earlier in the suspend sequence. This caused a regression that HDMI audio sometimes didn't work properly after resume unless audio was playing during suspend. [How] Drop dm_prepare_suspend() callback. All code in it will still run during dm_suspend(). Also drop unnecessary dm_complete() callback. dm_complete() was used for failed prepare and also for any case of successful resume. The code in it already runs in dm_resume(). This change will introduce more time that the display is turned on during suspend sequence. The compositor can turn it off sooner if desired. Cc: Harry Wentland Reported-by: Przemysław Kopa Closes: https://lore.kernel.org/amd-gfx/1cea0d56-7739-4ad9-bf8e-c9330faea2bb@kernel.org/T/#m383d9c08397043a271b36c32b64bb80e524e4b0f Reported-by: Kalvin Closes: https://github.com/alsa-project/alsa-lib/issues/465 Closes: https://gitlab.freedesktop.org/pipewire/pipewire/-/issues/4809 Cc: stable@vger.kernel.org Fixes: 50e0bae34fa6b ("drm/amd/display: Add and use new dm_prepare_suspend() callback") Signed-off-by: Mario Limonciello Acked-by: Alex Deucher --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 21 ------------------- 1 file changed, 21 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 80236677301fa..7cfc2da439b8e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3221,25 +3221,6 @@ static void dm_destroy_cached_state(struct amdgpu_device *adev) dm->cached_state = NULL; } -static void dm_complete(struct amdgpu_ip_block *ip_block) -{ - struct amdgpu_device *adev = ip_block->adev; - - dm_destroy_cached_state(adev); -} - -static int dm_prepare_suspend(struct amdgpu_ip_block *ip_block) -{ - struct amdgpu_device *adev = ip_block->adev; - - if (amdgpu_in_reset(adev)) - return 0; - - WARN_ON(adev->dm.cached_state); - - return dm_cache_state(adev); -} - static int dm_suspend(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -3665,10 +3646,8 @@ static const struct amd_ip_funcs amdgpu_dm_funcs = { .early_fini = amdgpu_dm_early_fini, .hw_init = dm_hw_init, .hw_fini = dm_hw_fini, - .prepare_suspend = dm_prepare_suspend, .suspend = dm_suspend, .resume = dm_resume, - .complete = dm_complete, .is_idle = dm_is_idle, .wait_for_idle = dm_wait_for_idle, .check_soft_reset = dm_check_soft_reset, From 23af7462cc497bc903c458d86a0d34826b10d001 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 4 Sep 2025 12:35:05 -0400 Subject: [PATCH 1884/2653] drm/amdgpu: fix a memory leak in fence cleanup when unloading MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit b61badd20b44 ("drm/amdgpu: fix usage slab after free") reordered when amdgpu_fence_driver_sw_fini() was called after that patch, amdgpu_fence_driver_sw_fini() effectively became a no-op as the sched entities we never freed because the ring pointers were already set to NULL. Remove the NULL setting. Reported-by: Lin.Cao Cc: Vitaly Prosyak Cc: Christian König Fixes: b61badd20b44 ("drm/amdgpu: fix usage slab after free") Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index f26002b25de4f..22e69a8f63afb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -421,8 +421,6 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring) dma_fence_put(ring->vmid_wait); ring->vmid_wait = NULL; ring->me = 0; - - ring->adev->rings[ring->idx] = NULL; } /** From b3adf028625ac7e5d2d0b8e889f7328b2c68b6a0 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Mon, 8 Sep 2025 14:05:50 +0800 Subject: [PATCH 1885/2653] drm/amdkcl: Fix HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG not generated correctly Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 index f7f9216f54f2e..c034421d9cdd7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 @@ -8,7 +8,8 @@ AC_DEFUN([AC_AMDGPU_DRM_VBLANK_CRTC_STRUCT_CONFIG], [ #include ],[ struct drm_vblank_crtc *vblank = NULL; - vblank->config = NULL; + struct drm_vblank_crtc_config config; + vblank->config = config; ],[ AC_DEFINE(HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG, 1, [struct vblank->config is available]) From 6d8523e6823ba5bd161d4289f4263e5d84bb50e3 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Mon, 8 Sep 2025 14:21:18 +0800 Subject: [PATCH 1886/2653] drm/amdkcl: Update dkms/config/config.h Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a7a6673c64457..86ab8b21b2c45 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -402,9 +402,6 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DP_DRM_DP_MST_HELPER_H */ -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_PRIVACY_SCREEN_CONSUMER_H 1 - /* drm_dp_link_train_channel_eq_delay() has 2 args */ #define HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS 1 @@ -546,6 +543,10 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PANIC_H 1 +/* Define to 1 if you have the header + file. */ +#define HAVE_DRM_DRM_PRIVACY_SCREEN_CONSUMER_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 From a9106cacd7c46f0bf9d806abadaec7cc3a4dcf72 Mon Sep 17 00:00:00 2001 From: Fangzhi Zuo Date: Thu, 4 Sep 2025 15:13:51 -0400 Subject: [PATCH 1887/2653] drm/amd/display: Disable DPCD Probe Quirk Disable dpcd probe quirk to native aux. Cc: stable@vger.kernel.org # 6.16.y: 5281cbe0b55a Cc: stable@vger.kernel.org # 6.16.y: 0b4aa85e8981 Cc: stable@vger.kernel.org # 6.16.y: b87ed522b364 Cc: stable@vger.kernel.org # 6.16.y Signed-off-by: Fangzhi Zuo Reviewed-by: Imre Deak Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4500 Reviewed-by: Mario Limonciello Link: https://lore.kernel.org/r/20250904191351.746707-1-Jerry.Zuo@amd.com Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index d0143d3a5b280..fba805b0eca10 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1053,6 +1053,7 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, drm_dp_aux_init(&aconnector->dm_dp_aux.aux); drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux, &aconnector->base); + drm_dp_dpcd_set_probe(&aconnector->dm_dp_aux.aux, false); if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP) return; From 4b4e8acb7bbd71b87be18b0f96068b27452e8dea Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Mon, 8 Sep 2025 13:39:23 +0800 Subject: [PATCH 1888/2653] drm/amdkcl: Test whether drm_dp_aux->dpcd_probe_disabled is available It's caused by the commit:aef403b "drm/amd/display: Disable DPCD Probe Quirk" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../dkms/m4/drm_dp_aux_dpcd_probe_disabled.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_aux_dpcd_probe_disabled.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index fba805b0eca10..2a783e6397039 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1053,7 +1053,9 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, drm_dp_aux_init(&aconnector->dm_dp_aux.aux); drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux, &aconnector->base); +#ifdef HAVE_DRM_DP_AUX_DPCD_PROBE_DISABLED drm_dp_dpcd_set_probe(&aconnector->dm_dp_aux.aux, false); +#endif if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP) return; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 86ab8b21b2c45..8ce7c0eccbaa7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -384,6 +384,9 @@ /* drm_dp_mst_atomic_wait_for_dependencies() is available */ #define HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES 1 +/* drm_dp_aux->dpcd_probe_disabled is available */ +#define HAVE_DRM_DP_AUX_DPCD_PROBE_DISABLED 1 + /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_aux_dpcd_probe_disabled.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_aux_dpcd_probe_disabled.m4 new file mode 100644 index 0000000000000..ab697ac5c5a3b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_aux_dpcd_probe_disabled.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.16-rc1-124-gb87ed522b364 +dnl # drm/dp: Add an EDID quirk for the DPCD register access probe +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_AUX_DPCD_PROBE_DISABLED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_aux *aux = NULL; + aux->dpcd_probe_disabled = false; + ], [ + AC_DEFINE(HAVE_DRM_DP_AUX_DPCD_PROBE_DISABLED, 1, + [drm_dp_aux->dpcd_probe_disabled is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index de6d794e90432..6679a0ec52939 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -290,6 +290,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FILE_DEBUGFS_CLIENT AC_AMDGPU_DRM_VBLANK_CRTC_STRUCT_CONFIG AC_AMDGPU_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN + AC_AMDGPU_DRM_DP_AUX_DPCD_PROBE_DISABLED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From c3d3881c52fbeb2f16d230f76f392a098e820b99 Mon Sep 17 00:00:00 2001 From: John Olender Date: Fri, 5 Sep 2025 06:11:28 -0400 Subject: [PATCH 1889/2653] drm/amdgpu: Fix NULL ptr deref in amdgpu_device_cache_switch_state() Kaveri has no upstream bridge, therefore parent is NULL. $ lspci -PP ... 00:01.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Kaveri [Radeon R7 Graphics] (rev d4) For comparison, Raphael: $ lspci -PP ... 00:08.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Raphael/Granite Ridge Internal GPP Bridge to Bus [C:A] ... 00:08.1/0e:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Raphael (rev c5) Fixes: 1dd2fa0e00f1 ("drm/amdgpu: Save and restore switch state") Link: https://lore.kernel.org/amd-gfx/38fe6513-f8a9-4669-8e86-89c54c465611@gmail.com/ Reviewed-by: Candice Li Reviewed-by: Yang Wang Signed-off-by: John Olender Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 05f4fe618ea51..312ce41c1440f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -7223,7 +7223,7 @@ static void amdgpu_device_cache_switch_state(struct amdgpu_device *adev) struct pci_dev *parent = pci_upstream_bridge(adev->pdev); int r; - if (parent->vendor != PCI_VENDOR_ID_ATI) + if (!parent || parent->vendor != PCI_VENDOR_ID_ATI) return; /* If already saved, return */ From e06b3b7f9c6652aba4c1ce3e1471971b6fe4125a Mon Sep 17 00:00:00 2001 From: Fangzhi Zuo Date: Tue, 8 Apr 2025 15:11:43 -0400 Subject: [PATCH 1890/2653] drm/amd/display: Fix pbn_div Calculation Error [Why] dm_mst_get_pbn_divider() returns value integer coming from the cast from fixed point, but the casted integer will then be used in dfixed_const to be multiplied by 4096. The cast from fixed point to integer causes the calculation error becomes bigger when multiplied by 4096. That makes the calculated pbn_div value becomes smaller than it should be, which leads to the req_slot number becomes bigger. Such error is getting reflected in 8k30 timing, where the correct and incorrect calculated req_slot 62.9 Vs 63.1. That makes the wrong calculation failed to light up 8k30 after a dock under HBR3 x 4. [How] Restore the accuracy by keeping the fraction part calculated for the left shift operation. Reviewed-by: Aurabindo Pillai Signed-off-by: Fangzhi Zuo Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 13 ++++++++++--- .../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h | 2 +- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7cfc2da439b8e..1913874738578 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8228,7 +8228,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, if (IS_ERR(mst_state)) return PTR_ERR(mst_state); #ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION - mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link)); + mst_state->pbn_div.full = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); #else mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 2a783e6397039..c7220b6197d58 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1073,13 +1073,20 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, drm_connector_attach_dp_subconnector_property(&aconnector->base); } -int dm_mst_get_pbn_divider(struct dc_link *link) +uint32_t dm_mst_get_pbn_divider(struct dc_link *link) { + uint32_t pbn_div_x100; + uint64_t dividend, divisor; + if (!link) return 0; - return dc_link_bandwidth_kbps(link, - dc_link_get_link_cap(link)) / (8 * 1000 * 54); + dividend = (uint64_t)dc_link_bandwidth_kbps(link, dc_link_get_link_cap(link)) * 100; + divisor = 8 * 1000 * 54; + + pbn_div_x100 = div64_u64(dividend, divisor); + + return dfixed_const(pbn_div_x100) / 100; } #if defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h index 65f76a7d00dbf..6f7ea684b555f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h @@ -60,7 +60,7 @@ enum mst_msg_ready_type { struct amdgpu_display_manager; struct amdgpu_dm_connector; -int dm_mst_get_pbn_divider(struct dc_link *link); +uint32_t dm_mst_get_pbn_divider(struct dc_link *link); void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, struct amdgpu_dm_connector *aconnector, From 8fc577f1b1d816a5fd8e362ea55b13edb239c2f5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 3 Sep 2025 09:11:12 -0400 Subject: [PATCH 1891/2653] drm/amd/display: use udelay rather than fsleep This function can be called from an atomic context so we can't use fsleep(). Fixes: 01f60348d8fb ("drm/amd/display: Fix 'failed to blank crtc!'") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4549 Cc: Wen Chen Cc: Fangzhi Zuo Cc: Nicholas Kazlauskas Cc: Harry Wentland Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 7d24fa1517bf1..cc377fcda6ff9 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -955,7 +955,7 @@ enum dc_status dcn20_enable_stream_timing( return DC_ERROR_UNEXPECTED; } - fsleep(stream->timing.v_total * (stream->timing.h_total * 10000u / stream->timing.pix_clk_100hz)); + udelay(stream->timing.v_total * (stream->timing.h_total * 10000u / stream->timing.pix_clk_100hz)); params.vertical_total_min = stream->adjust.v_total_min; params.vertical_total_max = stream->adjust.v_total_max; From 67796f3959e3776981903606bddb9e348aa6a691 Mon Sep 17 00:00:00 2001 From: Pratap Nirujogi Date: Wed, 3 Sep 2025 16:00:24 -0400 Subject: [PATCH 1892/2653] drm/amd/amdgpu: Declare isp firmware binary file Declare isp firmware file isp_4_1_1.bin required by isp4.1.1 device. Suggested-by: Alexey Zagorodnikov Reviewed-by: Mario Limonciello Signed-off-by: Pratap Nirujogi --- drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c index a887df5204140..4258d3e0b706c 100644 --- a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c +++ b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c @@ -29,6 +29,8 @@ #include "amdgpu.h" #include "isp_v4_1_1.h" +MODULE_FIRMWARE("amdgpu/isp_4_1_1.bin"); + #define ISP_PERFORMANCE_STATE_LOW 0 #define ISP_PERFORMANCE_STATE_HIGH 1 From abeaa14762c2c036f806d260b9adfa3dfed2de47 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Tue, 26 Aug 2025 15:49:20 +0530 Subject: [PATCH 1893/2653] drm/ttm: Bump TTM_NUM_MEM_TYPES to 9 (Prep for AMDGPU_PL_MMIO_REMAP) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Increase TTM_NUM_MEM_TYPES from 8 to 9 to accommodate the upcoming AMDGPU_PL_MMIO_REMAP placement. Cc: Alex Deucher Suggested-by: Christian König Signed-off-by: Srinivasan Shanmugam Reviewed-by: Christian König Reviewed-by: Alex Deucher --- include/drm/ttm/ttm_resource.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h index b873be9597e2e..bc6ceb3b4f602 100644 --- a/include/drm/ttm/ttm_resource.h +++ b/include/drm/ttm/ttm_resource.h @@ -36,7 +36,7 @@ #include #define TTM_MAX_BO_PRIORITY 4U -#define TTM_NUM_MEM_TYPES 12 +#define TTM_NUM_MEM_TYPES 13 struct dmem_cgroup_device; struct ttm_device; From 79bae3af8766cdb05f1ef00e543f3621eaded4da Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 20 Aug 2025 12:33:29 +0530 Subject: [PATCH 1894/2653] drm/amdgpu/uapi: Introduce AMDGPU_GEM_DOMAIN_MMIO_REMAP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a new GEM domain bit AMDGPU_GEM_DOMAIN_MMIO_REMAP to allow userspace to request the MMIO remap (HDP flush) page via GEM_CREATE. - include/uapi/drm/amdgpu_drm.h: * define AMDGPU_GEM_DOMAIN_MMIO_REMAP * include the bit in AMDGPU_GEM_DOMAIN_MASK v2: Add early reject in amdgpu_gem_create_ioctl() (Alex). Cc: Christian König Suggested-by: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Christian König Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 +++ include/uapi/drm/amdgpu_drm.h | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index e0a4332b82204..cbeb2527c8aa0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -529,6 +529,9 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, /* always clear VRAM */ flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; + if (args->in.domains & AMDGPU_GEM_DOMAIN_MMIO_REMAP) + return -EINVAL; + /* create a gem object to contain this object in */ if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index e1b2ee2cd1e19..4c2de75b15374 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -112,6 +112,8 @@ extern "C" { * * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for * signalling user mode queues. + * + * %AMDGPU_GEM_DOMAIN_MMIO_REMAP MMIO remap page (special mapping for HDP flushing). */ /* hybrid specific ioctls */ #define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem) @@ -123,8 +125,10 @@ extern "C" { #define AMDGPU_GEM_DOMAIN_GWS 0x10 #define AMDGPU_GEM_DOMAIN_OA 0x20 #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 +#define AMDGPU_GEM_DOMAIN_MMIO_REMAP 0x80 #define AMDGPU_GEM_DOMAIN_DGMA 0x400 #define AMDGPU_GEM_DOMAIN_DGMA_IMPORT 0x800 + #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ AMDGPU_GEM_DOMAIN_GTT | \ AMDGPU_GEM_DOMAIN_VRAM | \ @@ -132,6 +136,7 @@ extern "C" { AMDGPU_GEM_DOMAIN_GWS | \ AMDGPU_GEM_DOMAIN_OA |\ AMDGPU_GEM_DOMAIN_DOORBELL |\ + AMDGPU_GEM_DOMAIN_MMIO_REMAP |\ AMDGPU_GEM_DOMAIN_DGMA |\ AMDGPU_GEM_DOMAIN_DGMA_IMPORT) From c1458d5961b94cd9e49bf0ed21670855c6e7e55f Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Wed, 14 May 2025 12:43:57 +0800 Subject: [PATCH 1895/2653] drm/amdgpu: validate userq input args This will help on validating the userq input args, and rejecting for the invalid userq request at the IOCTLs first place. Signed-off-by: Prike Liang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 81 +++++++++++++++------- drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 7 -- 2 files changed, 56 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index ff52c582f6c4e..881e90787182d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -404,27 +404,10 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) (args->in.flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK) >> AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT; - /* Usermode queues are only supported for GFX IP as of now */ - if (args->in.ip_type != AMDGPU_HW_IP_GFX && - args->in.ip_type != AMDGPU_HW_IP_DMA && - args->in.ip_type != AMDGPU_HW_IP_COMPUTE) { - drm_file_err(uq_mgr->file, "Usermode queue doesn't support IP type %u\n", - args->in.ip_type); - return -EINVAL; - } - r = amdgpu_userq_priority_permit(filp, priority); if (r) return r; - if ((args->in.flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE) && - (args->in.ip_type != AMDGPU_HW_IP_GFX) && - (args->in.ip_type != AMDGPU_HW_IP_COMPUTE) && - !amdgpu_is_tmz(adev)) { - drm_file_err(uq_mgr->file, "Secure only supported on GFX/Compute queues\n"); - return -EINVAL; - } - r = pm_runtime_get_sync(adev_to_drm(adev)->dev); if (r < 0) { drm_file_err(uq_mgr->file, "pm_runtime_get_sync() failed for userqueue create\n"); @@ -548,22 +531,45 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) return r; } -int amdgpu_userq_ioctl(struct drm_device *dev, void *data, - struct drm_file *filp) +static int amdgpu_userq_input_args_validate(struct drm_device *dev, + union drm_amdgpu_userq *args, + struct drm_file *filp) { - union drm_amdgpu_userq *args = data; - int r; + struct amdgpu_device *adev = drm_to_adev(dev); switch (args->in.op) { case AMDGPU_USERQ_OP_CREATE: if (args->in.flags & ~(AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK | AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE)) return -EINVAL; - r = amdgpu_userq_create(filp, args); - if (r) - drm_file_err(filp, "Failed to create usermode queue\n"); - break; + /* Usermode queues are only supported for GFX IP as of now */ + if (args->in.ip_type != AMDGPU_HW_IP_GFX && + args->in.ip_type != AMDGPU_HW_IP_DMA && + args->in.ip_type != AMDGPU_HW_IP_COMPUTE) { + drm_file_err(filp, "Usermode queue doesn't support IP type %u\n", + args->in.ip_type); + return -EINVAL; + } + + if ((args->in.flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE) && + (args->in.ip_type != AMDGPU_HW_IP_GFX) && + (args->in.ip_type != AMDGPU_HW_IP_COMPUTE) && + !amdgpu_is_tmz(adev)) { + drm_file_err(filp, "Secure only supported on GFX/Compute queues\n"); + return -EINVAL; + } + if (args->in.queue_va == AMDGPU_BO_INVALID_OFFSET || + args->in.queue_va == 0 || + args->in.queue_size == 0) { + drm_file_err(filp, "invalidate userq queue va or size\n"); + return -EINVAL; + } + if (!args->in.wptr_va || !args->in.rptr_va) { + drm_file_err(filp, "invalidate userq queue rptr or wptr\n"); + return -EINVAL; + } + break; case AMDGPU_USERQ_OP_FREE: if (args->in.ip_type || args->in.doorbell_handle || @@ -576,6 +582,31 @@ int amdgpu_userq_ioctl(struct drm_device *dev, void *data, args->in.mqd || args->in.mqd_size) return -EINVAL; + break; + default: + return -EINVAL; + } + + return 0; +} + +int amdgpu_userq_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + union drm_amdgpu_userq *args = data; + int r; + + if (amdgpu_userq_input_args_validate(dev, args, filp) < 0) + return -EINVAL; + + switch (args->in.op) { + case AMDGPU_USERQ_OP_CREATE: + r = amdgpu_userq_create(filp, args); + if (r) + drm_file_err(filp, "Failed to create usermode queue\n"); + break; + + case AMDGPU_USERQ_OP_FREE: r = amdgpu_userq_destroy(filp, args->in.queue_id); if (r) drm_file_err(filp, "Failed to destroy usermode queue\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index aee26f80bd530..66467f41294c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -263,13 +263,6 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, return -ENOMEM; } - if (!mqd_user->wptr_va || !mqd_user->rptr_va || - !mqd_user->queue_va || mqd_user->queue_size == 0) { - DRM_ERROR("Invalid MQD parameters for userqueue\n"); - r = -EINVAL; - goto free_props; - } - r = amdgpu_userq_create_object(uq_mgr, &queue->mqd, mqd_hw_default->mqd_size); if (r) { DRM_ERROR("Failed to create MQD object for userqueue\n"); From 1640323bb9bcebce5265ae883ba5ac7e629be0ca Mon Sep 17 00:00:00 2001 From: Ray Wu Date: Mon, 8 Sep 2025 17:21:27 +0800 Subject: [PATCH 1896/2653] drm/amd/display: Remove duplicated code [Why&How] Remove duplicated code Reviewed-by: Alex Deucher Reviewed-by: Tom Chung Signed-off-by: Ray Wu --- drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 3 --- .../gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c | 3 --- drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c | 3 --- 3 files changed, 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c index 8475c6eec547b..1d1a002f6d54f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c @@ -1900,9 +1900,6 @@ static bool dcn35_resource_construct( dc->caps.num_of_host_routers = 2; dc->caps.num_of_dpias_per_host_router = 2; - dc->caps.num_of_host_routers = 2; - dc->caps.num_of_dpias_per_host_router = 2; - /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order * to provide some margin. * It's expected for furture ASIC to have equal or higher value, in order to diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c index 0971c0f741865..47912e0861a2b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c @@ -1872,9 +1872,6 @@ static bool dcn351_resource_construct( dc->caps.num_of_host_routers = 2; dc->caps.num_of_dpias_per_host_router = 2; - dc->caps.num_of_host_routers = 2; - dc->caps.num_of_dpias_per_host_router = 2; - /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order * to provide some margin. * It's expected for furture ASIC to have equal or higher value, in order to diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c index 8bae7fcedc22d..9ba91e214ddaa 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c @@ -1873,9 +1873,6 @@ static bool dcn36_resource_construct( dc->caps.num_of_host_routers = 2; dc->caps.num_of_dpias_per_host_router = 2; - dc->caps.num_of_host_routers = 2; - dc->caps.num_of_dpias_per_host_router = 2; - /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order * to provide some margin. * It's expected for furture ASIC to have equal or higher value, in order to From e230231352766d7ef3dec1b3c0a3c57dd5f305c1 Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Thu, 14 Aug 2025 09:54:45 -0400 Subject: [PATCH 1897/2653] drm/amd/display: Add Component To Handle Bounding Box Values and IP Caps [Why] Bounding box values can be stored in multiple locations. (e.g. PMFW, VBIOS, DMUB). The source and interpretation of these values can vary with DCN revision so there should be a component that can gather these values and translate them accordingly [How] Have component start with the statically defined values as a base. Then update them as needed with DCN-specific logic Guard this component with FPU flags since values need to be in float point. Reviewed-by: Jun Lei Signed-off-by: Austin Zheng Signed-off-by: Alex Hung Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/Makefile | 1 + drivers/gpu/drm/amd/display/dc/Makefile | 1 + drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- .../dc/dml2/dml21/dml21_translation_helper.c | 368 +----------------- .../amd/display/dc/dml2/dml21/dml21_wrapper.c | 2 +- .../display/dc/inc/soc_and_ip_translator.h | 24 ++ .../display/dc/soc_and_ip_translator/Makefile | 19 + .../dcn401/dcn401_soc_and_ip_translator.c | 304 +++++++++++++++ .../dcn401/dcn401_soc_and_ip_translator.h | 22 ++ .../dcn42/dcn42_soc_and_ip_translator.c | 27 ++ .../dcn42/dcn42_soc_and_ip_translator.h | 16 + .../soc_and_ip_translator.c | 37 ++ 13 files changed, 475 insertions(+), 356 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h create mode 100644 drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile create mode 100644 drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c create mode 100644 drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h create mode 100644 drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c create mode 100644 drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h create mode 100644 drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/soc_and_ip_translator.c diff --git a/drivers/gpu/drm/amd/display/Makefile b/drivers/gpu/drm/amd/display/Makefile index 89d605de05955..0084a8d552545 100644 --- a/drivers/gpu/drm/amd/display/Makefile +++ b/drivers/gpu/drm/amd/display/Makefile @@ -44,6 +44,7 @@ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/mmhubbub subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/mpc subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/opp subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/pg +subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/soc_and_ip_translator subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/inc subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/freesync subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/modules/color diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index 3c9ecea7eebc7..dc943abd6dba3 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -37,6 +37,7 @@ DC_LIBS += dcn301 DC_LIBS += dcn31 DC_LIBS += dml DC_LIBS += dml2 +DC_LIBS += soc_and_ip_translator endif DC_LIBS += dce120 diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 8d30deba6724d..957544bd04fb4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -84,6 +84,7 @@ #if defined(CONFIG_DRM_AMD_DC_FP) #include "dml2/dml2_internal_types.h" +#include "soc_and_ip_translator.h" #endif #include "dce/dmub_outbox.h" @@ -949,7 +950,9 @@ static void dc_destruct(struct dc *dc) } dc_destroy_resource_pool(dc); - +#ifdef CONFIG_DRM_AMD_DC_FP + dc_destroy_soc_and_ip_translator(&dc->soc_and_ip_translator); +#endif if (dc->link_srv) link_destroy_link_service(&dc->link_srv); @@ -1153,6 +1156,9 @@ static bool dc_construct(struct dc *dc, dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); DC_FP_END(); } + dc->soc_and_ip_translator = dc_create_soc_and_ip_translator(dc_ctx->dce_version); + if (!dc->soc_and_ip_translator) + goto fail; #endif if (!create_links(dc, init_params->num_virtual_links)) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 6fa5b6b547b34..2e497877977bc 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1780,7 +1780,7 @@ struct dc { struct dml2_configuration_options dml2_options; struct dml2_configuration_options dml2_dc_power_options; enum dc_acpi_cm_power_state power_state; - + struct soc_and_ip_translator *soc_and_ip_translator; }; struct dc_scaling_info { diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c index d6c77d96e4f70..f6879e6222710 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c @@ -8,7 +8,7 @@ #include "dml2_internal_types.h" #include "dml21_utils.h" #include "dml21_translation_helper.h" -#include "bounding_boxes/dcn4_soc_bb.h" +#include "soc_and_ip_translator.h" static void dml21_populate_pmo_options(struct dml2_pmo_options *pmo_options, const struct dc *in_dc, @@ -38,375 +38,37 @@ static void dml21_populate_pmo_options(struct dml2_pmo_options *pmo_options, pmo_options->disable_drr_clamped_when_var_active = in_dc->debug.disable_fams_gaming == INGAME_FAMS_DISABLE; } -/* - * Populate dml_init based on default static values in soc bb. The default - * values are for reference and support at least minimal operation of current - * SoC and DCN hardware. The values could be modifed by subsequent override - * functions to reflect our true hardware capability. - */ -static void populate_default_dml_init_params(struct dml2_initialize_instance_in_out *dml_init, - const struct dml2_configuration_options *config, - const struct dc *in_dc) +static enum dml2_project_id dml21_dcn_revision_to_dml2_project_id(enum dce_version dcn_version) { - switch (in_dc->ctx->dce_version) { + enum dml2_project_id project_id; + switch (dcn_version) { case DCN_VERSION_4_01: - dml_init->options.project_id = dml2_project_dcn4x_stage2_auto_drr_svp; - dml21_populate_pmo_options(&dml_init->options.pmo_options, in_dc, config); - dml_init->soc_bb = dml2_socbb_dcn401; - dml_init->soc_bb.qos_parameters = dml_dcn4_variant_a_soc_qos_params; - dml_init->ip_caps = dml2_dcn401_max_ip_caps; + project_id = dml2_project_dcn4x_stage2_auto_drr_svp; break; default: - memset(dml_init, 0, sizeof(*dml_init)); + project_id = dml2_project_invalid; DC_ERR("unsupported dcn version for DML21!"); - return; - } -} - -static void override_dml_init_with_values_from_hardware_default(struct dml2_initialize_instance_in_out *dml_init, - const struct dml2_configuration_options *config, - const struct dc *in_dc) -{ - dml_init->soc_bb.dchub_refclk_mhz = in_dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; - dml_init->soc_bb.dprefclk_mhz = in_dc->clk_mgr->dprefclk_khz / 1000; - dml_init->soc_bb.dispclk_dppclk_vco_speed_mhz = in_dc->clk_mgr->dentist_vco_freq_khz / 1000.0; -} - -/* - * SMU stands for System Management Unit. It is a power management processor. - * It owns the initialization of dc's clock table and programming of clock values - * based on dc's requests. - * Our clock values in base soc bb is a dummy placeholder. The real clock values - * are retrieved from SMU firmware to dc clock table at runtime. - * This function overrides our dummy placeholder values with real values in dc - * clock table. - */ -static void override_dml_init_with_values_from_smu( - struct dml2_initialize_instance_in_out *dml_init, - const struct dml2_configuration_options *config, - const struct dc *in_dc) -{ - int i; - const struct clk_bw_params *dc_bw_params = in_dc->clk_mgr->bw_params; - const struct clk_limit_table *dc_clk_table = &dc_bw_params->clk_table; - struct dml2_soc_state_table *dml_clk_table = &dml_init->soc_bb.clk_table; - - if (!in_dc->clk_mgr->funcs->is_smu_present || - !in_dc->clk_mgr->funcs->is_smu_present(in_dc->clk_mgr)) - /* skip if smu is not present */ - return; - - /* dcfclk */ - if (dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { - dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; - for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { - if (i < dml_clk_table->dcfclk.num_clk_values) { - if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dcfclk_mhz && - dc_clk_table->entries[i].dcfclk_mhz > dc_bw_params->dc_mode_limit.dcfclk_mhz) { - if (i == 0 || dc_clk_table->entries[i-1].dcfclk_mhz < dc_bw_params->dc_mode_limit.dcfclk_mhz) { - dml_clk_table->dcfclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dcfclk_mhz * 1000; - dml_clk_table->dcfclk.num_clk_values = i + 1; - } else { - dml_clk_table->dcfclk.clk_values_khz[i] = 0; - dml_clk_table->dcfclk.num_clk_values = i; - } - } else { - dml_clk_table->dcfclk.clk_values_khz[i] = dc_clk_table->entries[i].dcfclk_mhz * 1000; - } - } else { - dml_clk_table->dcfclk.clk_values_khz[i] = 0; - } - } - } - - /* fclk */ - if (dc_clk_table->num_entries_per_clk.num_fclk_levels) { - dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_fclk_levels; - for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { - if (i < dml_clk_table->fclk.num_clk_values) { - if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.fclk_mhz && - dc_clk_table->entries[i].fclk_mhz > dc_bw_params->dc_mode_limit.fclk_mhz) { - if (i == 0 || dc_clk_table->entries[i-1].fclk_mhz < dc_bw_params->dc_mode_limit.fclk_mhz) { - dml_clk_table->fclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.fclk_mhz * 1000; - dml_clk_table->fclk.num_clk_values = i + 1; - } else { - dml_clk_table->fclk.clk_values_khz[i] = 0; - dml_clk_table->fclk.num_clk_values = i; - } - } else { - dml_clk_table->fclk.clk_values_khz[i] = dc_clk_table->entries[i].fclk_mhz * 1000; - } - } else { - dml_clk_table->fclk.clk_values_khz[i] = 0; - } - } - } - - /* uclk */ - if (dc_clk_table->num_entries_per_clk.num_memclk_levels) { - dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels; - for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { - if (i < dml_clk_table->uclk.num_clk_values) { - if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.memclk_mhz && - dc_clk_table->entries[i].memclk_mhz > dc_bw_params->dc_mode_limit.memclk_mhz) { - if (i == 0 || dc_clk_table->entries[i-1].memclk_mhz < dc_bw_params->dc_mode_limit.memclk_mhz) { - dml_clk_table->uclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.memclk_mhz * 1000; - dml_clk_table->uclk.num_clk_values = i + 1; - } else { - dml_clk_table->uclk.clk_values_khz[i] = 0; - dml_clk_table->uclk.num_clk_values = i; - } - } else { - dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000; - } - } else { - dml_clk_table->uclk.clk_values_khz[i] = 0; - } - } - } - - /* dispclk */ - if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) { - dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels; - for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { - if (i < dml_clk_table->dispclk.num_clk_values) { - if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dispclk_mhz && - dc_clk_table->entries[i].dispclk_mhz > dc_bw_params->dc_mode_limit.dispclk_mhz) { - if (i == 0 || dc_clk_table->entries[i-1].dispclk_mhz < dc_bw_params->dc_mode_limit.dispclk_mhz) { - dml_clk_table->dispclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dispclk_mhz * 1000; - dml_clk_table->dispclk.num_clk_values = i + 1; - } else { - dml_clk_table->dispclk.clk_values_khz[i] = 0; - dml_clk_table->dispclk.num_clk_values = i; - } - } else { - dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000; - } - } else { - dml_clk_table->dispclk.clk_values_khz[i] = 0; - } - } - } - - /* dppclk */ - if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) { - dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels; - for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { - if (i < dml_clk_table->dppclk.num_clk_values) { - if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dppclk_mhz && - dc_clk_table->entries[i].dppclk_mhz > dc_bw_params->dc_mode_limit.dppclk_mhz) { - if (i == 0 || dc_clk_table->entries[i-1].dppclk_mhz < dc_bw_params->dc_mode_limit.dppclk_mhz) { - dml_clk_table->dppclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dppclk_mhz * 1000; - dml_clk_table->dppclk.num_clk_values = i + 1; - } else { - dml_clk_table->dppclk.clk_values_khz[i] = 0; - dml_clk_table->dppclk.num_clk_values = i; - } - } else { - dml_clk_table->dppclk.clk_values_khz[i] = dc_clk_table->entries[i].dppclk_mhz * 1000; - } - } else { - dml_clk_table->dppclk.clk_values_khz[i] = 0; - } - } - } - - /* dtbclk */ - if (dc_clk_table->num_entries_per_clk.num_dtbclk_levels) { - dml_clk_table->dtbclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dtbclk_levels; - for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { - if (i < dml_clk_table->dtbclk.num_clk_values) { - if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dtbclk_mhz && - dc_clk_table->entries[i].dtbclk_mhz > dc_bw_params->dc_mode_limit.dtbclk_mhz) { - if (i == 0 || dc_clk_table->entries[i-1].dtbclk_mhz < dc_bw_params->dc_mode_limit.dtbclk_mhz) { - dml_clk_table->dtbclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dtbclk_mhz * 1000; - dml_clk_table->dtbclk.num_clk_values = i + 1; - } else { - dml_clk_table->dtbclk.clk_values_khz[i] = 0; - dml_clk_table->dtbclk.num_clk_values = i; - } - } else { - dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000; - } - } else { - dml_clk_table->dtbclk.clk_values_khz[i] = 0; - } - } + break; } - /* socclk */ - if (dc_clk_table->num_entries_per_clk.num_socclk_levels) { - dml_clk_table->socclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_socclk_levels; - for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { - if (i < dml_clk_table->socclk.num_clk_values) { - if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.socclk_mhz && - dc_clk_table->entries[i].socclk_mhz > dc_bw_params->dc_mode_limit.socclk_mhz) { - if (i == 0 || dc_clk_table->entries[i-1].socclk_mhz < dc_bw_params->dc_mode_limit.socclk_mhz) { - dml_clk_table->socclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.socclk_mhz * 1000; - dml_clk_table->socclk.num_clk_values = i + 1; - } else { - dml_clk_table->socclk.clk_values_khz[i] = 0; - dml_clk_table->socclk.num_clk_values = i; - } - } else { - dml_clk_table->socclk.clk_values_khz[i] = dc_clk_table->entries[i].socclk_mhz * 1000; - } - } else { - dml_clk_table->socclk.clk_values_khz[i] = 0; - } - } - } + return project_id; } -static void override_dml_init_with_values_from_vbios( - struct dml2_initialize_instance_in_out *dml_init, +void dml21_populate_dml_init_params(struct dml2_initialize_instance_in_out *dml_init, const struct dml2_configuration_options *config, const struct dc *in_dc) { - const struct clk_bw_params *dc_bw_params = in_dc->clk_mgr->bw_params; - struct dml2_soc_bb *dml_soc_bb = &dml_init->soc_bb; - struct dml2_soc_state_table *dml_clk_table = &dml_init->soc_bb.clk_table; - - if (in_dc->ctx->dc_bios->bb_info.dram_clock_change_latency_100ns > 0) - dml_soc_bb->power_management_parameters.dram_clk_change_blackout_us = - (in_dc->ctx->dc_bios->bb_info.dram_clock_change_latency_100ns + 9) / 10; - - if (in_dc->ctx->dc_bios->bb_info.dram_sr_enter_exit_latency_100ns > 0) - dml_soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us = - (in_dc->ctx->dc_bios->bb_info.dram_sr_enter_exit_latency_100ns + 9) / 10; - - if (in_dc->ctx->dc_bios->bb_info.dram_sr_exit_latency_100ns > 0) - dml_soc_bb->power_management_parameters.stutter_exit_latency_us = - (in_dc->ctx->dc_bios->bb_info.dram_sr_exit_latency_100ns + 9) / 10; - - if (dc_bw_params->num_channels) { - dml_clk_table->dram_config.channel_count = dc_bw_params->num_channels; - dml_soc_bb->mall_allocated_for_dcn_mbytes = in_dc->caps.mall_size_total / 1048576; - } else if (in_dc->ctx->dc_bios->vram_info.num_chans) { - dml_clk_table->dram_config.channel_count = in_dc->ctx->dc_bios->vram_info.num_chans; - dml_soc_bb->mall_allocated_for_dcn_mbytes = in_dc->caps.mall_size_total / 1048576; - } - - if (dc_bw_params->dram_channel_width_bytes) { - dml_clk_table->dram_config.channel_width_bytes = dc_bw_params->dram_channel_width_bytes; - } else if (in_dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) { - dml_clk_table->dram_config.channel_width_bytes = in_dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; - } - - dml_init->soc_bb.xtalclk_mhz = in_dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000; -} + dml_init->options.project_id = dml21_dcn_revision_to_dml2_project_id(in_dc->ctx->dce_version); - -static void override_dml_init_with_values_from_dmub(struct dml2_initialize_instance_in_out *dml_init, - const struct dml2_configuration_options *config, - const struct dc *in_dc) -{ - /* - * TODO - There seems to be overlaps between the values overriden from - * dmub and vbios. Investigate and identify the values that DMUB needs - * to own. - */ -// const struct dmub_soc_bb_params *dmub_bb_params = -// (const struct dmub_soc_bb_params *)config->bb_from_dmub; - -// if (dmub_bb_params == NULL) -// return; - -// if (dmub_bb_params->dram_clk_change_blackout_ns > 0) -// dml_init->soc_bb.power_management_parameters.dram_clk_change_blackout_us = -// (double) dmub_bb_params->dram_clk_change_blackout_ns / 1000.0; -// if (dmub_bb_params->dram_clk_change_read_only_ns > 0) -// dml_init->soc_bb.power_management_parameters.dram_clk_change_read_only_us = -// (double) dmub_bb_params->dram_clk_change_read_only_ns / 1000.0; -// if (dmub_bb_params->dram_clk_change_write_only_ns > 0) -// dml_init->soc_bb.power_management_parameters.dram_clk_change_write_only_us = -// (double) dmub_bb_params->dram_clk_change_write_only_ns / 1000.0; -// if (dmub_bb_params->fclk_change_blackout_ns > 0) -// dml_init->soc_bb.power_management_parameters.fclk_change_blackout_us = -// (double) dmub_bb_params->fclk_change_blackout_ns / 1000.0; -// if (dmub_bb_params->g7_ppt_blackout_ns > 0) -// dml_init->soc_bb.power_management_parameters.g7_ppt_blackout_us = -// (double) dmub_bb_params->g7_ppt_blackout_ns / 1000.0; -// if (dmub_bb_params->stutter_enter_plus_exit_latency_ns > 0) -// dml_init->soc_bb.power_management_parameters.stutter_enter_plus_exit_latency_us = -// (double) dmub_bb_params->stutter_enter_plus_exit_latency_ns / 1000.0; -// if (dmub_bb_params->stutter_exit_latency_ns > 0) -// dml_init->soc_bb.power_management_parameters.stutter_exit_latency_us = -// (double) dmub_bb_params->stutter_exit_latency_ns / 1000.0; -// if (dmub_bb_params->z8_stutter_enter_plus_exit_latency_ns > 0) -// dml_init->soc_bb.power_management_parameters.z8_stutter_enter_plus_exit_latency_us = -// (double) dmub_bb_params->z8_stutter_enter_plus_exit_latency_ns / 1000.0; -// if (dmub_bb_params->z8_stutter_exit_latency_ns > 0) -// dml_init->soc_bb.power_management_parameters.z8_stutter_exit_latency_us = -// (double) dmub_bb_params->z8_stutter_exit_latency_ns / 1000.0; -// if (dmub_bb_params->z8_min_idle_time_ns > 0) -// dml_init->soc_bb.power_management_parameters.z8_min_idle_time = -// (double) dmub_bb_params->z8_min_idle_time_ns / 1000.0; -// #ifndef TRIM_DML2_DCN6B_IP_SENSITIVE -// if (dmub_bb_params->type_b_dram_clk_change_blackout_ns > 0) -// dml_init->soc_bb.power_management_parameters.lpddr5_dram_clk_change_blackout_us = -// (double) dmub_bb_params->type_b_dram_clk_change_blackout_ns / 1000.0; -// if (dmub_bb_params->type_b_ppt_blackout_ns > 0) -// dml_init->soc_bb.power_management_parameters.lpddr5_ppt_blackout_us = -// (double) dmub_bb_params->type_b_ppt_blackout_ns / 1000.0; -// #else -// if (dmub_bb_params->type_b_dram_clk_change_blackout_ns > 0) -// dml_init->soc_bb.power_management_parameters.type_b_dram_clk_change_blackout_us = -// (double) dmub_bb_params->type_b_dram_clk_change_blackout_ns / 1000.0; -// if (dmub_bb_params->type_b_ppt_blackout_ns > 0) -// dml_init->soc_bb.power_management_parameters.type_b_ppt_blackout_us = -// (double) dmub_bb_params->type_b_ppt_blackout_ns / 1000.0; -// #endif -// if (dmub_bb_params->vmin_limit_dispclk_khz > 0) -// dml_init->soc_bb.vmin_limit.dispclk_khz = dmub_bb_params->vmin_limit_dispclk_khz; -// if (dmub_bb_params->vmin_limit_dcfclk_khz > 0) -// dml_init->soc_bb.vmin_limit.dcfclk_khz = dmub_bb_params->vmin_limit_dcfclk_khz; -// if (dmub_bb_params->g7_temperature_read_blackout_ns > 0) -// dml_init->soc_bb.power_management_parameters.g7_temperature_read_blackout_us = -// (double) dmub_bb_params->g7_temperature_read_blackout_ns / 1000.0; -} - -static void override_dml_init_with_values_from_software_policy(struct dml2_initialize_instance_in_out *dml_init, - const struct dml2_configuration_options *config, - const struct dc *in_dc) -{ - if (!config->use_native_soc_bb_construction) { + if (config->use_native_soc_bb_construction) { + in_dc->soc_and_ip_translator->translator_funcs->get_soc_bb(&dml_init->soc_bb, in_dc, config); + in_dc->soc_and_ip_translator->translator_funcs->get_ip_caps(&dml_init->ip_caps); + } else { dml_init->soc_bb = config->external_socbb_ip_params->soc_bb; dml_init->ip_caps = config->external_socbb_ip_params->ip_params; } - if (in_dc->bb_overrides.sr_exit_time_ns) - dml_init->soc_bb.power_management_parameters.stutter_exit_latency_us = - in_dc->bb_overrides.sr_exit_time_ns / 1000.0; - - if (in_dc->bb_overrides.sr_enter_plus_exit_time_ns) - dml_init->soc_bb.power_management_parameters.stutter_enter_plus_exit_latency_us = - in_dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; - - if (in_dc->bb_overrides.dram_clock_change_latency_ns) - dml_init->soc_bb.power_management_parameters.dram_clk_change_blackout_us = - in_dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; - - if (in_dc->bb_overrides.fclk_clock_change_latency_ns) - dml_init->soc_bb.power_management_parameters.fclk_change_blackout_us = - in_dc->bb_overrides.fclk_clock_change_latency_ns / 1000.0; -} - -void dml21_populate_dml_init_params(struct dml2_initialize_instance_in_out *dml_init, - const struct dml2_configuration_options *config, - const struct dc *in_dc) -{ - populate_default_dml_init_params(dml_init, config, in_dc); - - override_dml_init_with_values_from_hardware_default(dml_init, config, in_dc); - - override_dml_init_with_values_from_smu(dml_init, config, in_dc); - - override_dml_init_with_values_from_vbios(dml_init, config, in_dc); - - override_dml_init_with_values_from_dmub(dml_init, config, in_dc); - - override_dml_init_with_values_from_software_policy(dml_init, config, in_dc); + dml21_populate_pmo_options(&dml_init->options.pmo_options, in_dc, config); } static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stream) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c index 03de3cf06ae59..798abb2b2e676 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c @@ -60,7 +60,7 @@ static void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, con DC_FP_START(); - dml21_populate_dml_init_params(&dml_ctx->v21.dml_init, config, in_dc); + dml21_populate_dml_init_params(&dml_ctx->v21.dml_init, &dml_ctx->config, in_dc); dml2_initialize_instance(&dml_ctx->v21.dml_init); diff --git a/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h b/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h new file mode 100644 index 0000000000000..23daf98b8aa88 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/soc_and_ip_translator.h @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2025 Advanced Micro Devices, Inc. + +#ifndef __SOC_AND_IP_TRANSLATOR_H__ +#define __SOC_AND_IP_TRANSLATOR_H__ + +#include "dc.h" +#include "dml_top_soc_parameter_types.h" + +struct soc_and_ip_translator_funcs { + void (*get_soc_bb)(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config); + void (*get_ip_caps)(struct dml2_ip_capabilities *dml_ip_caps); +}; + +struct soc_and_ip_translator { + const struct soc_and_ip_translator_funcs *translator_funcs; +}; + +struct soc_and_ip_translator *dc_create_soc_and_ip_translator(enum dce_version dc_version); +void dc_destroy_soc_and_ip_translator(struct soc_and_ip_translator **soc_and_ip_translator); + + +#endif // __SOC_AND_IP_TRANSLATOR_H__ diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile new file mode 100644 index 0000000000000..bc93356a0b5b9 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: MIT +# +# Copyright 2025 Advanced Micro Devices, Inc. +# Makefile for bounding box component. +# Floating point required due to nature of bounding box values + +soc_and_ip_translator_ccflags := $(CC_FLAGS_FPU) +soc_and_ip_translator_rcflags := $(CC_FLAGS_NO_FPU) + +CFLAGS_$(AMDDALPATH)/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.o := $(soc_and_ip_translator_ccflags) + +CFLAGS_REMOVE_$(AMDDALPATH)/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.o := $(soc_and_ip_translator_rcflags) + +soc_and_ip_translator := soc_and_ip_translator.o +soc_and_ip_translator += dcn401/dcn401_soc_and_ip_translator.o + +AMD_DAL_soc_and_ip_translator := $(addprefix $(AMDDALPATH)/dc/soc_and_ip_translator/, $(soc_and_ip_translator)) + +AMD_DISPLAY_FILES += $(AMD_DAL_soc_and_ip_translator) diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c new file mode 100644 index 0000000000000..3190c76eb4820 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2025 Advanced Micro Devices, Inc. + +#include "dcn401_soc_and_ip_translator.h" +#include "bounding_boxes/dcn4_soc_bb.h" + +/* soc_and_ip_translator component used to get up-to-date values for bounding box. + * Bounding box values are stored in several locations and locations can vary with DCN revision. + * This component provides an interface to get DCN-specific bounding box values. + */ + +static void get_default_soc_bb(struct dml2_soc_bb *soc_bb) +{ + memcpy(soc_bb, &dml2_socbb_dcn401, sizeof(struct dml2_soc_bb)); + memcpy(&soc_bb->qos_parameters, &dml_dcn4_variant_a_soc_qos_params, sizeof(struct dml2_soc_qos_parameters)); +} + +/* + * DC clock table is obtained from SMU during runtime. + * SMU stands for System Management Unit. It is a power management processor. + * It owns the initialization of dc's clock table and programming of clock values + * based on dc's requests. + * Our clock values in base soc bb is a dummy placeholder. The real clock values + * are retrieved from SMU firmware to dc clock table at runtime. + * This function overrides our dummy placeholder values with real values in dc + * clock table. + */ +static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table( + struct dml2_soc_state_table *dml_clk_table, + const struct clk_bw_params *dc_bw_params, + bool use_clock_dc_limits) +{ + int i; + const struct clk_limit_table *dc_clk_table; + + if (dc_bw_params == NULL) + /* skip if bw params could not be obtained from smu */ + return; + + dc_clk_table = &dc_bw_params->clk_table; + + /* dcfclk */ + if (dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { + dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dml_clk_table->dcfclk.num_clk_values) { + if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dcfclk_mhz && + dc_clk_table->entries[i].dcfclk_mhz > dc_bw_params->dc_mode_limit.dcfclk_mhz) { + if (i == 0 || dc_clk_table->entries[i-1].dcfclk_mhz < dc_bw_params->dc_mode_limit.dcfclk_mhz) { + dml_clk_table->dcfclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dcfclk_mhz * 1000; + dml_clk_table->dcfclk.num_clk_values = i + 1; + } else { + dml_clk_table->dcfclk.clk_values_khz[i] = 0; + dml_clk_table->dcfclk.num_clk_values = i; + } + } else { + dml_clk_table->dcfclk.clk_values_khz[i] = dc_clk_table->entries[i].dcfclk_mhz * 1000; + } + } else { + dml_clk_table->dcfclk.clk_values_khz[i] = 0; + } + } + } + + /* fclk */ + if (dc_clk_table->num_entries_per_clk.num_fclk_levels) { + dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_fclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dml_clk_table->fclk.num_clk_values) { + if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.fclk_mhz && + dc_clk_table->entries[i].fclk_mhz > dc_bw_params->dc_mode_limit.fclk_mhz) { + if (i == 0 || dc_clk_table->entries[i-1].fclk_mhz < dc_bw_params->dc_mode_limit.fclk_mhz) { + dml_clk_table->fclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.fclk_mhz * 1000; + dml_clk_table->fclk.num_clk_values = i + 1; + } else { + dml_clk_table->fclk.clk_values_khz[i] = 0; + dml_clk_table->fclk.num_clk_values = i; + } + } else { + dml_clk_table->fclk.clk_values_khz[i] = dc_clk_table->entries[i].fclk_mhz * 1000; + } + } else { + dml_clk_table->fclk.clk_values_khz[i] = 0; + } + } + } + + /* uclk */ + if (dc_clk_table->num_entries_per_clk.num_memclk_levels) { + dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dml_clk_table->uclk.num_clk_values) { + if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.memclk_mhz && + dc_clk_table->entries[i].memclk_mhz > dc_bw_params->dc_mode_limit.memclk_mhz) { + if (i == 0 || dc_clk_table->entries[i-1].memclk_mhz < dc_bw_params->dc_mode_limit.memclk_mhz) { + dml_clk_table->uclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.memclk_mhz * 1000; + dml_clk_table->uclk.num_clk_values = i + 1; + } else { + dml_clk_table->uclk.clk_values_khz[i] = 0; + dml_clk_table->uclk.num_clk_values = i; + } + } else { + dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000; + } + } else { + dml_clk_table->uclk.clk_values_khz[i] = 0; + } + } + } + + /* dispclk */ + if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) { + dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dml_clk_table->dispclk.num_clk_values) { + if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dispclk_mhz && + dc_clk_table->entries[i].dispclk_mhz > dc_bw_params->dc_mode_limit.dispclk_mhz) { + if (i == 0 || dc_clk_table->entries[i-1].dispclk_mhz < dc_bw_params->dc_mode_limit.dispclk_mhz) { + dml_clk_table->dispclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dispclk_mhz * 1000; + dml_clk_table->dispclk.num_clk_values = i + 1; + } else { + dml_clk_table->dispclk.clk_values_khz[i] = 0; + dml_clk_table->dispclk.num_clk_values = i; + } + } else { + dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000; + } + } else { + dml_clk_table->dispclk.clk_values_khz[i] = 0; + } + } + } + + /* dppclk */ + if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) { + dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dml_clk_table->dppclk.num_clk_values) { + if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dppclk_mhz && + dc_clk_table->entries[i].dppclk_mhz > dc_bw_params->dc_mode_limit.dppclk_mhz) { + if (i == 0 || dc_clk_table->entries[i-1].dppclk_mhz < dc_bw_params->dc_mode_limit.dppclk_mhz) { + dml_clk_table->dppclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dppclk_mhz * 1000; + dml_clk_table->dppclk.num_clk_values = i + 1; + } else { + dml_clk_table->dppclk.clk_values_khz[i] = 0; + dml_clk_table->dppclk.num_clk_values = i; + } + } else { + dml_clk_table->dppclk.clk_values_khz[i] = dc_clk_table->entries[i].dppclk_mhz * 1000; + } + } else { + dml_clk_table->dppclk.clk_values_khz[i] = 0; + } + } + } + + /* dtbclk */ + if (dc_clk_table->num_entries_per_clk.num_dtbclk_levels) { + dml_clk_table->dtbclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dtbclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dml_clk_table->dtbclk.num_clk_values) { + if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dtbclk_mhz && + dc_clk_table->entries[i].dtbclk_mhz > dc_bw_params->dc_mode_limit.dtbclk_mhz) { + if (i == 0 || dc_clk_table->entries[i-1].dtbclk_mhz < dc_bw_params->dc_mode_limit.dtbclk_mhz) { + dml_clk_table->dtbclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dtbclk_mhz * 1000; + dml_clk_table->dtbclk.num_clk_values = i + 1; + } else { + dml_clk_table->dtbclk.clk_values_khz[i] = 0; + dml_clk_table->dtbclk.num_clk_values = i; + } + } else { + dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000; + } + } else { + dml_clk_table->dtbclk.clk_values_khz[i] = 0; + } + } + } + + /* socclk */ + if (dc_clk_table->num_entries_per_clk.num_socclk_levels) { + dml_clk_table->socclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_socclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dml_clk_table->socclk.num_clk_values) { + if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.socclk_mhz && + dc_clk_table->entries[i].socclk_mhz > dc_bw_params->dc_mode_limit.socclk_mhz) { + if (i == 0 || dc_clk_table->entries[i-1].socclk_mhz < dc_bw_params->dc_mode_limit.socclk_mhz) { + dml_clk_table->socclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.socclk_mhz * 1000; + dml_clk_table->socclk.num_clk_values = i + 1; + } else { + dml_clk_table->socclk.clk_values_khz[i] = 0; + dml_clk_table->socclk.num_clk_values = i; + } + } else { + dml_clk_table->socclk.clk_values_khz[i] = dc_clk_table->entries[i].socclk_mhz * 1000; + } + } else { + dml_clk_table->socclk.clk_values_khz[i] = 0; + } + } + } + + /* dram config */ + dml_clk_table->dram_config.channel_count = dc_bw_params->num_channels; + dml_clk_table->dram_config.channel_width_bytes = dc_bw_params->dram_channel_width_bytes; +} + +void dcn401_update_soc_bb_with_values_from_clk_mgr(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config) +{ + soc_bb->dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000; + soc_bb->dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; + soc_bb->mall_allocated_for_dcn_mbytes = dc->caps.mall_size_total / (1024 * 1024); + + if (dc->clk_mgr->funcs->is_smu_present && + dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr)) { + dcn401_convert_dc_clock_table_to_soc_bb_clock_table(&soc_bb->clk_table, + dc->clk_mgr->bw_params, + config->use_clock_dc_limits); + } +} + +void dcn401_update_soc_bb_with_values_from_vbios(struct dml2_soc_bb *soc_bb, const struct dc *dc) +{ + soc_bb->dchub_refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; + soc_bb->xtalclk_mhz = dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency / 1000; + + /* latencies in vbios are platform specific and should be used if provided */ + if (dc->ctx->dc_bios->bb_info.dram_clock_change_latency_100ns) + soc_bb->power_management_parameters.dram_clk_change_blackout_us = + dc->ctx->dc_bios->bb_info.dram_clock_change_latency_100ns / 10.0; + + if (dc->ctx->dc_bios->bb_info.dram_sr_enter_exit_latency_100ns) + soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us = + dc->ctx->dc_bios->bb_info.dram_sr_enter_exit_latency_100ns / 10.0; + + if (dc->ctx->dc_bios->bb_info.dram_sr_exit_latency_100ns) + soc_bb->power_management_parameters.stutter_exit_latency_us = + dc->ctx->dc_bios->bb_info.dram_sr_exit_latency_100ns / 10.0; +} + +void dcn401_update_soc_bb_with_values_from_software_policy(struct dml2_soc_bb *soc_bb, const struct dc *dc) +{ + /* set if the value is provided */ + if (dc->bb_overrides.sr_exit_time_ns) + soc_bb->power_management_parameters.stutter_exit_latency_us = + dc->bb_overrides.sr_exit_time_ns / 1000.0; + + if (dc->bb_overrides.sr_enter_plus_exit_time_ns) + soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us = + dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; + + if (dc->bb_overrides.dram_clock_change_latency_ns) + soc_bb->power_management_parameters.dram_clk_change_blackout_us = + dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; + + if (dc->bb_overrides.fclk_clock_change_latency_ns) + soc_bb->power_management_parameters.fclk_change_blackout_us = + dc->bb_overrides.fclk_clock_change_latency_ns / 1000.0; + + //Z8 values not expected nor used on DCN401 but still added for completeness + if (dc->bb_overrides.sr_exit_z8_time_ns) + soc_bb->power_management_parameters.z8_stutter_exit_latency_us = + dc->bb_overrides.sr_exit_z8_time_ns / 1000.0; + + if (dc->bb_overrides.sr_enter_plus_exit_z8_time_ns) + soc_bb->power_management_parameters.z8_stutter_enter_plus_exit_latency_us = + dc->bb_overrides.sr_enter_plus_exit_z8_time_ns / 1000.0; +} + +static void apply_soc_bb_updates(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config) +{ + /* Individual modification can be overwritten even if it was obtained by a previous function. + * Modifications are acquired in order of priority (lowest to highest). + */ + dc_assert_fp_enabled(); + + dcn401_update_soc_bb_with_values_from_clk_mgr(soc_bb, dc, config); + dcn401_update_soc_bb_with_values_from_vbios(soc_bb, dc); + dcn401_update_soc_bb_with_values_from_software_policy(soc_bb, dc); +} + +void dcn401_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config) +{ + //get default soc_bb with static values + get_default_soc_bb(soc_bb); + //update soc_bb values with more accurate values + apply_soc_bb_updates(soc_bb, dc, config); +} + +static void dcn401_get_ip_caps(struct dml2_ip_capabilities *ip_caps) +{ + *ip_caps = dml2_dcn401_max_ip_caps; +} + +static struct soc_and_ip_translator_funcs dcn401_translator_funcs = { + .get_soc_bb = dcn401_get_soc_bb, + .get_ip_caps = dcn401_get_ip_caps, +}; + +void dcn401_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc_and_ip_translator) +{ + soc_and_ip_translator->translator_funcs = &dcn401_translator_funcs; +} diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h new file mode 100644 index 0000000000000..21d8428576011 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2025 Advanced Micro Devices, Inc. + +#ifndef _DCN401_SOC_AND_IP_TRANSLATOR_H_ +#define _DCN401_SOC_AND_IP_TRANSLATOR_H_ + +#include "core_types.h" +#include "dc.h" +#include "clk_mgr.h" +#include "soc_and_ip_translator.h" +#include "dml2/dml21/inc/dml_top_soc_parameter_types.h" + +void dcn401_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc_and_ip_translator); + +/* Functions that can be re-used by higher DCN revisions of this component */ +void dcn401_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config); +void dcn401_update_soc_bb_with_values_from_clk_mgr(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config); +void dcn401_update_soc_bb_with_values_from_vbios(struct dml2_soc_bb *soc_bb, const struct dc *dc); +void dcn401_update_soc_bb_with_values_from_software_policy(struct dml2_soc_bb *soc_bb, const struct dc *dc); + +#endif /* _DCN401_SOC_AND_IP_TRANSLATOR_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c new file mode 100644 index 0000000000000..c9e224d262c90 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2025 Advanced Micro Devices, Inc. + +#include "dcn42_soc_and_ip_translator.h" +#include "soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h" +#include "bounding_boxes/dcn42_soc_bb.h" + +/* soc_and_ip_translator component used to get up-to-date values for bounding box. + * Bounding box values are stored in several locations and locations can vary with DCN revision. + * This component provides an interface to get DCN-specific bounding box values. + */ + +static void dcn42_get_ip_caps(struct dml2_ip_capabilities *ip_caps) +{ + *ip_caps = dml2_dcn42_max_ip_caps; +} + +static struct soc_and_ip_translator_funcs dcn42_translator_funcs = { + .get_soc_bb = dcn401_get_soc_bb, + .get_ip_caps = dcn42_get_ip_caps, +}; + +void dcn42_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc_and_ip_translator) +{ + soc_and_ip_translator->translator_funcs = &dcn42_translator_funcs; +} diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h new file mode 100644 index 0000000000000..914dcbb369a75 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2025 Advanced Micro Devices, Inc. + +#ifndef _DCN42_SOC_AND_IP_TRANSLATOR_H_ +#define _DCN42_SOC_AND_IP_TRANSLATOR_H_ + +#include "core_types.h" +#include "dc.h" +#include "clk_mgr.h" +#include "dml_top_soc_parameter_types.h" +#include "soc_and_ip_translator.h" + +void dcn42_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc_and_ip_translator); + +#endif /* _DCN42_SOC_AND_IP_TRANSLATOR_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/soc_and_ip_translator.c new file mode 100644 index 0000000000000..0fc0e5a6c171c --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/soc_and_ip_translator.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2025 Advanced Micro Devices, Inc. + +#include "soc_and_ip_translator.h" +#include "soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h" + +static void dc_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc_and_ip_translator, + enum dce_version dc_version) +{ + switch (dc_version) { + case DCN_VERSION_4_01: + dcn401_construct_soc_and_ip_translator(soc_and_ip_translator); + break; + default: + break; + } +} + +struct soc_and_ip_translator *dc_create_soc_and_ip_translator(enum dce_version dc_version) +{ + struct soc_and_ip_translator *soc_and_ip_translator; + + soc_and_ip_translator = kzalloc(sizeof(*soc_and_ip_translator), GFP_KERNEL); + if (!soc_and_ip_translator) + return NULL; + + dc_construct_soc_and_ip_translator(soc_and_ip_translator, dc_version); + + return soc_and_ip_translator; +} + +void dc_destroy_soc_and_ip_translator(struct soc_and_ip_translator **soc_and_ip_translator) +{ + kfree(*soc_and_ip_translator); + *soc_and_ip_translator = NULL; +} From e766f6a37a90ef011c15937d50a2755463b42f52 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 9 Sep 2025 13:45:27 +0800 Subject: [PATCH 1898/2653] drm/amdkcl: modify the makefile for dc/soc_and_ip_translator It's cauesd by the commit: f833377 "drm/amd/display: Add Component To Handle Bounding Box Values and IP Caps" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- .../display/dc/soc_and_ip_translator/Makefile | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile index bc93356a0b5b9..897a5e3f14663 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile @@ -4,8 +4,46 @@ # Makefile for bounding box component. # Floating point required due to nature of bounding box values +ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT soc_and_ip_translator_ccflags := $(CC_FLAGS_FPU) soc_and_ip_translator_rcflags := $(CC_FLAGS_NO_FPU) +else +ifdef CONFIG_X86 +soc_and_ip_translator_ccflags-$(CONFIG_CC_IS_GCC) := -mhard-float +soc_and_ip_translator_ccflags := $(soc_and_ip_translator_ccflags-y) -msse +endif + +ifdef CONFIG_PPC64 +soc_and_ip_translator_ccflags := -mhard-float -maltivec +endif + +ifdef CONFIG_ARM64 +soc_and_ip_translator_rcflags := -mgeneral-regs-only +endif + +ifdef CONFIG_LOONGARCH +soc_and_ip_translator_ccflags := -mfpu=64 +soc_and_ip_translator_rcflags := -msoft-float +endif + +ifdef CONFIG_CC_IS_GCC +ifneq ($(call gcc-min-version, 70100),y) +IS_OLD_GCC = 1 +endif +endif + +ifdef CONFIG_X86 +ifdef IS_OLD_GCC +# Stack alignment mismatch, proceed with caution. +# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 +# (8B stack alignment). +soc_and_ip_translator_ccflags += -mpreferred-stack-boundary=4 +else +soc_and_ip_translator_ccflags += -msse2 +endif +endif + +endif #CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT CFLAGS_$(AMDDALPATH)/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.o := $(soc_and_ip_translator_ccflags) From 93b1fa80b5979cdae26a47b616438ee103bf6ee2 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 20 Aug 2025 16:10:51 +0800 Subject: [PATCH 1899/2653] amd/amdkfd: correct mem limit calculation for small APUs Current mem limit check leaks some GTT memory (reserved_for_pt reserved_for_ras + adev->vram_pin_size) for small APUs. Since carveout VRAM is tunable on APUs, there are three case regarding the carveout VRAM size relative to GTT: 1. 0 < carveout < gtt apu_prefer_gtt = true, is_app_apu = false 2. carveout > gtt / 2 apu_prefer_gtt = false, is_app_apu = false 3. 0 = carveout apu_prefer_gtt = true, is_app_apu = true It doesn't make sense to check below limitation in case 1 (default case, small carveout) because the values in the below expression are mixed with carveout and gtt. adev->kfd.vram_used[xcp_id] + vram_needed > vram_size - reserved_for_pt - reserved_for_ras - atomic64_read(&adev->vram_pin_size) gtt: kfd.vram_used, vram_needed, vram_size carveout: reserved_for_pt, reserved_for_ras, adev->vram_pin_size In case 1, vram allocation will go to gtt domain, skip vram check since ttm_mem_limit check already cover this allocation. Signed-off-by: Yifan Zhang Reviewed-by: Mario Limonciello --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 48 +++++++++++++------ 1 file changed, 34 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 7231e57cd9984..02450d129db8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -215,20 +215,36 @@ int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, spin_lock(&kfd_mem_limit.mem_limit_lock); if (kfd_mem_limit.system_mem_used + system_mem_needed > - kfd_mem_limit.max_system_mem_limit) + kfd_mem_limit.max_system_mem_limit) { pr_debug("Set no_system_mem_limit=1 if using shared memory\n"); + if (!no_system_mem_limit) { + ret = -ENOMEM; + goto release; + } + } - if ((kfd_mem_limit.system_mem_used + system_mem_needed > - kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) || - (kfd_mem_limit.ttm_mem_used + ttm_mem_needed > - kfd_mem_limit.max_ttm_mem_limit) || - (adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] + vram_needed > - vram_size - reserved_for_pt - reserved_for_ras - atomic64_read(&adev->vram_pin_size) + - atomic64_read(&adev->kfd.vram_pinned))) { + if (kfd_mem_limit.ttm_mem_used + ttm_mem_needed > + kfd_mem_limit.max_ttm_mem_limit) { ret = -ENOMEM; goto release; } + /*if is_app_apu is false and apu_prefer_gtt is true, it is an APU with + * carve out < gtt. In that case, VRAM allocation will go to gtt domain, skip + * VRAM check since ttm_mem_limit check already cover this allocation + */ + + if (adev && xcp_id >= 0 && (!adev->apu_prefer_gtt || adev->gmc.is_app_apu)) { + uint64_t vram_available = + vram_size - reserved_for_pt - reserved_for_ras - + atomic64_read(&adev->vram_pin_size) + + atomic64_read(&adev->kfd.vram_pinned); + if (adev->kfd.vram_used[xcp_id] + vram_needed > vram_available) { + ret = -ENOMEM; + goto release; + } + } + /* Update memory accounting by decreasing available system * memory, TTM memory and GPU memory as computed above */ @@ -1732,12 +1748,16 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, uint64_t vram_available, system_mem_available, ttm_mem_available; spin_lock(&kfd_mem_limit.mem_limit_lock); - vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id) - - adev->kfd.vram_used_aligned[xcp_id] - - atomic64_read(&adev->vram_pin_size) - + atomic64_read(&adev->kfd.vram_pinned) - - reserved_for_pt - - reserved_for_ras; + if (adev->apu_prefer_gtt && !adev->gmc.is_app_apu) + vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id) + - adev->kfd.vram_used_aligned[xcp_id]; + else + vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id) + - adev->kfd.vram_used_aligned[xcp_id] + - atomic64_read(&adev->vram_pin_size) + + atomic64_read(&adev->kfd.vram_pinned) + - reserved_for_pt + - reserved_for_ras; if (adev->apu_prefer_gtt) { system_mem_available = no_system_mem_limit ? From f9d30b2e8d91dddf265785534e2bbe6d5cf03618 Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Tue, 19 Aug 2025 16:11:01 +0530 Subject: [PATCH 1900/2653] drm/amdgpu/jpeg: Move parse_cs to amdgpu_jpeg.c Rename jpeg_v2_dec_ring_parse_cs to amdgpu_jpeg_dec_parse_cs and move it to amdgpu_jpeg.c as it is shared among jpeg versions. Signed-off-by: Sathishkumar S Reviewed-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 65 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 10 ++++ drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 58 +-------------------- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h | 6 --- drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 4 +- drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 2 +- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 2 +- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 2 +- 10 files changed, 83 insertions(+), 70 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c index f0d7e2487237c..e7b4b768f7d21 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c @@ -539,3 +539,68 @@ void amdgpu_jpeg_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_pri drm_printf(p, "\nInactive Instance:JPEG%d\n", i); } } + +static inline bool amdgpu_jpeg_reg_valid(u32 reg) +{ + if (reg < JPEG_REG_RANGE_START || reg > JPEG_REG_RANGE_END || + (reg >= JPEG_ATOMIC_RANGE_START && reg <= JPEG_ATOMIC_RANGE_END)) + return false; + else + return true; +} + +/** + * amdgpu_jpeg_dec_parse_cs - command submission parser + * + * @parser: Command submission parser context + * @job: the job to parse + * @ib: the IB to parse + * + * Parse the command stream, return -EINVAL for invalid packet, + * 0 otherwise + */ + +int amdgpu_jpeg_dec_parse_cs(struct amdgpu_cs_parser *parser, + struct amdgpu_job *job, + struct amdgpu_ib *ib) +{ + u32 i, reg, res, cond, type; + struct amdgpu_device *adev = parser->adev; + + for (i = 0; i < ib->length_dw ; i += 2) { + reg = CP_PACKETJ_GET_REG(ib->ptr[i]); + res = CP_PACKETJ_GET_RES(ib->ptr[i]); + cond = CP_PACKETJ_GET_COND(ib->ptr[i]); + type = CP_PACKETJ_GET_TYPE(ib->ptr[i]); + + if (res) /* only support 0 at the moment */ + return -EINVAL; + + switch (type) { + case PACKETJ_TYPE0: + if (cond != PACKETJ_CONDITION_CHECK0 || + !amdgpu_jpeg_reg_valid(reg)) { + dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); + return -EINVAL; + } + break; + case PACKETJ_TYPE3: + if (cond != PACKETJ_CONDITION_CHECK3 || + !amdgpu_jpeg_reg_valid(reg)) { + dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); + return -EINVAL; + } + break; + case PACKETJ_TYPE6: + if (ib->ptr[i] == CP_PACKETJ_NOP) + continue; + dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); + return -EINVAL; + default: + dev_err(adev->dev, "Unknown packet type %d !\n", type); + return -EINVAL; + } + } + + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h index 4f0775e39b543..346ae0ab09d33 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h @@ -25,11 +25,18 @@ #define __AMDGPU_JPEG_H__ #include "amdgpu_ras.h" +#include "amdgpu_cs.h" #define AMDGPU_MAX_JPEG_INSTANCES 4 #define AMDGPU_MAX_JPEG_RINGS 10 #define AMDGPU_MAX_JPEG_RINGS_4_0_3 8 +#define JPEG_REG_RANGE_START 0x4000 +#define JPEG_REG_RANGE_END 0x41c2 +#define JPEG_ATOMIC_RANGE_START 0x4120 +#define JPEG_ATOMIC_RANGE_END 0x412A + + #define AMDGPU_JPEG_HARVEST_JPEG0 (1 << 0) #define AMDGPU_JPEG_HARVEST_JPEG1 (1 << 1) @@ -170,5 +177,8 @@ int amdgpu_jpeg_reg_dump_init(struct amdgpu_device *adev, const struct amdgpu_hwip_reg_entry *reg, u32 count); void amdgpu_jpeg_dump_ip_state(struct amdgpu_ip_block *ip_block); void amdgpu_jpeg_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p); +int amdgpu_jpeg_dec_parse_cs(struct amdgpu_cs_parser *parser, + struct amdgpu_job *job, + struct amdgpu_ib *ib); #endif /*__AMDGPU_JPEG_H__*/ diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c index 58239c405fda5..27c76bd424cfb 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c @@ -23,7 +23,6 @@ #include "amdgpu.h" #include "amdgpu_jpeg.h" -#include "amdgpu_cs.h" #include "amdgpu_pm.h" #include "soc15.h" #include "soc15d.h" @@ -806,7 +805,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = { .get_rptr = jpeg_v2_0_dec_ring_get_rptr, .get_wptr = jpeg_v2_0_dec_ring_get_wptr, .set_wptr = jpeg_v2_0_dec_ring_set_wptr, - .parse_cs = jpeg_v2_dec_ring_parse_cs, + .parse_cs = amdgpu_jpeg_dec_parse_cs, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + @@ -854,58 +853,3 @@ const struct amdgpu_ip_block_version jpeg_v2_0_ip_block = { .rev = 0, .funcs = &jpeg_v2_0_ip_funcs, }; - -/** - * jpeg_v2_dec_ring_parse_cs - command submission parser - * - * @parser: Command submission parser context - * @job: the job to parse - * @ib: the IB to parse - * - * Parse the command stream, return -EINVAL for invalid packet, - * 0 otherwise - */ -int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser, - struct amdgpu_job *job, - struct amdgpu_ib *ib) -{ - u32 i, reg, res, cond, type; - struct amdgpu_device *adev = parser->adev; - - for (i = 0; i < ib->length_dw ; i += 2) { - reg = CP_PACKETJ_GET_REG(ib->ptr[i]); - res = CP_PACKETJ_GET_RES(ib->ptr[i]); - cond = CP_PACKETJ_GET_COND(ib->ptr[i]); - type = CP_PACKETJ_GET_TYPE(ib->ptr[i]); - - if (res) /* only support 0 at the moment */ - return -EINVAL; - - switch (type) { - case PACKETJ_TYPE0: - if (cond != PACKETJ_CONDITION_CHECK0 || reg < JPEG_REG_RANGE_START || - reg > JPEG_REG_RANGE_END) { - dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); - return -EINVAL; - } - break; - case PACKETJ_TYPE3: - if (cond != PACKETJ_CONDITION_CHECK3 || reg < JPEG_REG_RANGE_START || - reg > JPEG_REG_RANGE_END) { - dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); - return -EINVAL; - } - break; - case PACKETJ_TYPE6: - if (ib->ptr[i] == CP_PACKETJ_NOP) - continue; - dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); - return -EINVAL; - default: - dev_err(adev->dev, "Unknown packet type %d !\n", type); - return -EINVAL; - } - } - - return 0; -} diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h index 63fadda7a6733..654e43e83e2c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h @@ -45,9 +45,6 @@ #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000 -#define JPEG_REG_RANGE_START 0x4000 -#define JPEG_REG_RANGE_END 0x41c2 - void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring); void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring); void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, @@ -60,9 +57,6 @@ void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vmid, uint64_t pd_addr); void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count); -int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser, - struct amdgpu_job *job, - struct amdgpu_ib *ib); extern const struct amdgpu_ip_block_version jpeg_v2_0_ip_block; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c index 3e2c389242dbe..20983f126b490 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c @@ -696,7 +696,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = { .get_rptr = jpeg_v2_5_dec_ring_get_rptr, .get_wptr = jpeg_v2_5_dec_ring_get_wptr, .set_wptr = jpeg_v2_5_dec_ring_set_wptr, - .parse_cs = jpeg_v2_dec_ring_parse_cs, + .parse_cs = amdgpu_jpeg_dec_parse_cs, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + @@ -727,7 +727,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = { .get_rptr = jpeg_v2_5_dec_ring_get_rptr, .get_wptr = jpeg_v2_5_dec_ring_get_wptr, .set_wptr = jpeg_v2_5_dec_ring_set_wptr, - .parse_cs = jpeg_v2_dec_ring_parse_cs, + .parse_cs = amdgpu_jpeg_dec_parse_cs, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c index a44eb2667664b..d1a011c40ba23 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c @@ -597,7 +597,7 @@ static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = { .get_rptr = jpeg_v3_0_dec_ring_get_rptr, .get_wptr = jpeg_v3_0_dec_ring_get_wptr, .set_wptr = jpeg_v3_0_dec_ring_set_wptr, - .parse_cs = jpeg_v2_dec_ring_parse_cs, + .parse_cs = amdgpu_jpeg_dec_parse_cs, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c index da3ee69f1a3ba..33db2c1ae6cca 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c @@ -762,7 +762,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = { .get_rptr = jpeg_v4_0_dec_ring_get_rptr, .get_wptr = jpeg_v4_0_dec_ring_get_wptr, .set_wptr = jpeg_v4_0_dec_ring_set_wptr, - .parse_cs = jpeg_v2_dec_ring_parse_cs, + .parse_cs = amdgpu_jpeg_dec_parse_cs, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index a78144773fabb..aae7328973d18 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -1177,7 +1177,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = { .get_rptr = jpeg_v4_0_3_dec_ring_get_rptr, .get_wptr = jpeg_v4_0_3_dec_ring_get_wptr, .set_wptr = jpeg_v4_0_3_dec_ring_set_wptr, - .parse_cs = jpeg_v2_dec_ring_parse_cs, + .parse_cs = amdgpu_jpeg_dec_parse_cs, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c index 5d86e1d846eb0..54fd9c800c40a 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c @@ -807,7 +807,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = { .get_rptr = jpeg_v4_0_5_dec_ring_get_rptr, .get_wptr = jpeg_v4_0_5_dec_ring_get_wptr, .set_wptr = jpeg_v4_0_5_dec_ring_set_wptr, - .parse_cs = jpeg_v2_dec_ring_parse_cs, + .parse_cs = amdgpu_jpeg_dec_parse_cs, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c index 34c70270ea1db..46bf15dce2bd0 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c @@ -683,7 +683,7 @@ static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = { .get_rptr = jpeg_v5_0_0_dec_ring_get_rptr, .get_wptr = jpeg_v5_0_0_dec_ring_get_wptr, .set_wptr = jpeg_v5_0_0_dec_ring_set_wptr, - .parse_cs = jpeg_v2_dec_ring_parse_cs, + .parse_cs = amdgpu_jpeg_dec_parse_cs, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + From 398f5611f73edbafdbf5a5ff71b6ad009ae2a17b Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Tue, 17 Jun 2025 15:37:31 +0800 Subject: [PATCH 1901/2653] drm/amdgpu: clean up the amdgpu_userq_active() This is no invocation for amdgpu_userq_active(). Signed-off-by: Prike Liang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 16 ---------------- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 2 -- 2 files changed, 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 881e90787182d..df472c5e49b69 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -112,22 +112,6 @@ amdgpu_userq_cleanup(struct amdgpu_userq_mgr *uq_mgr, kfree(queue); } -int -amdgpu_userq_active(struct amdgpu_userq_mgr *uq_mgr) -{ - struct amdgpu_usermode_queue *queue; - int queue_id; - int ret = 0; - - mutex_lock(&uq_mgr->userq_mutex); - /* Resume all the queues for this process */ - idr_for_each_entry(&uq_mgr->userq_idr, queue, queue_id) - ret += queue->state == AMDGPU_USERQ_STATE_MAPPED; - - mutex_unlock(&uq_mgr->userq_mutex); - return ret; -} - static struct amdgpu_usermode_queue * amdgpu_userq_find(struct amdgpu_userq_mgr *uq_mgr, int qid) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index 5e36e44223933..bc683763627fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -125,8 +125,6 @@ void amdgpu_userq_destroy_object(struct amdgpu_userq_mgr *uq_mgr, void amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_eviction_fence *ev_fence); -int amdgpu_userq_active(struct amdgpu_userq_mgr *uq_mgr); - void amdgpu_userq_ensure_ev_fence(struct amdgpu_userq_mgr *userq_mgr, struct amdgpu_eviction_fence_mgr *evf_mgr); From 06316d603ec652f7a61c4b3d7c651a3adc372d6b Mon Sep 17 00:00:00 2001 From: David Rosca Date: Mon, 18 Aug 2025 09:06:58 +0200 Subject: [PATCH 1902/2653] drm/amdgpu/vcn4: Fix IB parsing with multiple engine info packages There can be multiple engine info packages in one IB and the first one may be common engine, not decode/encode. We need to parse the entire IB instead of stopping after finding first engine info. Signed-off-by: David Rosca Reviewed-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 52 +++++++++++---------------- 1 file changed, 21 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index d0d27790b73b1..8d20ae5bdb86d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -1903,22 +1903,16 @@ static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, #define RADEON_VCN_ENGINE_TYPE_ENCODE (0x00000002) #define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003) - #define RADEON_VCN_ENGINE_INFO (0x30000001) -#define RADEON_VCN_ENGINE_INFO_MAX_OFFSET 16 - #define RENCODE_ENCODE_STANDARD_AV1 2 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003 -#define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET 64 -/* return the offset in ib if id is found, -1 otherwise - * to speed up the searching we only search upto max_offset - */ -static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset) +/* return the offset in ib if id is found, -1 otherwise */ +static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int start) { int i; - for (i = 0; i < ib->length_dw && i < max_offset && ib->ptr[i] >= 8; i += ib->ptr[i]/4) { + for (i = start; i < ib->length_dw && ib->ptr[i] >= 8; i += ib->ptr[i] / 4) { if (ib->ptr[i + 1] == id) return i; } @@ -1933,33 +1927,29 @@ static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, struct amdgpu_vcn_decode_buffer *decode_buffer; uint64_t addr; uint32_t val; - int idx; + int idx = 0, sidx; /* The first instance can decode anything */ if (!ring->me) return 0; - /* RADEON_VCN_ENGINE_INFO is at the top of ib block */ - idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO, - RADEON_VCN_ENGINE_INFO_MAX_OFFSET); - if (idx < 0) /* engine info is missing */ - return 0; - - val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */ - if (val == RADEON_VCN_ENGINE_TYPE_DECODE) { - decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6]; - - if (!(decode_buffer->valid_buf_flag & 0x1)) - return 0; - - addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 | - decode_buffer->msg_buffer_address_lo; - return vcn_v4_0_dec_msg(p, job, addr); - } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) { - idx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT, - RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET); - if (idx >= 0 && ib->ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1) - return vcn_v4_0_limit_sched(p, job); + while ((idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO, idx)) >= 0) { + val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */ + if (val == RADEON_VCN_ENGINE_TYPE_DECODE) { + decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6]; + + if (!(decode_buffer->valid_buf_flag & 0x1)) + return 0; + + addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 | + decode_buffer->msg_buffer_address_lo; + return vcn_v4_0_dec_msg(p, job, addr); + } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) { + sidx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT, idx); + if (sidx >= 0 && ib->ptr[sidx + 2] == RENCODE_ENCODE_STANDARD_AV1) + return vcn_v4_0_limit_sched(p, job); + } + idx += ib->ptr[idx] / 4; } return 0; } From 7a0acba7c615189874219e9496b99dcdad73a387 Mon Sep 17 00:00:00 2001 From: David Rosca Date: Mon, 18 Aug 2025 09:18:37 +0200 Subject: [PATCH 1903/2653] drm/amdgpu/vcn: Allow limiting ctx to instance 0 for AV1 at any time There is no reason to require this to happen on first submitted IB only. We need to wait for the queue to be idle, but it can be done at any time (including when there are multiple video sessions active). Signed-off-by: David Rosca Reviewed-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 12 ++++++++---- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 12 ++++++++---- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 95173156f956a..f3085137ba08b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -1886,15 +1886,19 @@ static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p, struct amdgpu_job *job) { struct drm_gpu_scheduler **scheds; - - /* The create msg must be in the first IB submitted */ - if (atomic_read(&job->base.entity->fence_seq)) - return -EINVAL; + struct dma_fence *fence; /* if VCN0 is harvested, we can't support AV1 */ if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) return -EINVAL; + /* wait for all jobs to finish before switching to instance 0 */ + fence = amdgpu_ctx_get_fence(p->ctx, job->base.entity, ~0ull); + if (fence) { + dma_fence_wait(fence, false); + dma_fence_put(fence); + } + scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC] [AMDGPU_RING_PRIO_DEFAULT].sched; drm_sched_entity_modify_sched(job->base.entity, scheds, 1); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 8d20ae5bdb86d..bc9dfe5ffea71 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -1804,15 +1804,19 @@ static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p, struct amdgpu_job *job) { struct drm_gpu_scheduler **scheds; - - /* The create msg must be in the first IB submitted */ - if (atomic_read(&job->base.entity->fence_seq)) - return -EINVAL; + struct dma_fence *fence; /* if VCN0 is harvested, we can't support AV1 */ if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) return -EINVAL; + /* wait for all jobs to finish before switching to instance 0 */ + fence = amdgpu_ctx_get_fence(p->ctx, job->base.entity, ~0ull); + if (fence) { + dma_fence_wait(fence, false); + dma_fence_put(fence); + } + scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC] [AMDGPU_RING_PRIO_0].sched; drm_sched_entity_modify_sched(job->base.entity, scheds, 1); From ceea00ede6cd0ed0429e5472e5cfc0ea33a0159e Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Fri, 16 May 2025 16:20:54 +0800 Subject: [PATCH 1904/2653] drm/amdgpu: validate userq hw unmap status for destroying userq Before destroying the userq buffer object, it requires validating the userq HW unmap status and ensuring the userq is unmapped from hardware. If the user HW unmap failed, then it needs to reset the queue for reusing. Signed-off-by: Prike Liang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index df472c5e49b69..aa5531bfeb574 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -307,6 +307,11 @@ amdgpu_userq_destroy(struct drm_file *filp, int queue_id) debugfs_remove_recursive(queue->debugfs_queue); #endif r = amdgpu_userq_unmap_helper(uq_mgr, queue); + /*TODO: It requires a reset for userq hw unmap error*/ + if (unlikely(r != AMDGPU_USERQ_STATE_UNMAPPED)) { + drm_warn(adev_to_drm(uq_mgr->adev), "trying to destroy a HW mapping userq\n"); + queue->state = AMDGPU_USERQ_STATE_HUNG; + } amdgpu_userq_cleanup(uq_mgr, queue, queue_id); mutex_unlock(&uq_mgr->userq_mutex); From c27cd2b4b92afa29e04d28ba30dc5b129a4a2542 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Sun, 24 Aug 2025 18:46:40 -0600 Subject: [PATCH 1905/2653] drm/amdgpu/vcn: Document IRQ per-instance irq behavior for VCN 4.0.3 When examining the VCN function init, it is common to find a loop that initializes VCN rings, which uses one IRQ per instance. However, VCN 4.0.3 deviates from this pattern, as it includes a distinct field to differentiate instances, which results in a slightly different ring init. This commit makes this difference explicit by using a fixed index when initializing the ring buffer and also adds a comment. Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 7b93a275ec4f9..bae1ad4484ede 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -212,7 +212,11 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); - r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, + + /* There are no per-instance irq source IDs on 4.0.3, the IH + * packets use a separate field to differentiate instances. + */ + r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[0].irq, 0, AMDGPU_RING_PRIO_DEFAULT, &adev->vcn.inst[i].sched_score); if (r) From 6621d4739435da1a56a415f91d44f223a86f5985 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Sun, 24 Aug 2025 18:46:41 -0600 Subject: [PATCH 1906/2653] drm/amdgpu/vcn: Change amdgpu_vcn_sw_fini return to void The function amdgpu_vcn_sw_fini() returns an integer, but this number is always 0. This commit changes the amdgpu_vcn_sw_fini() return to void, and eliminates all checks to this return across different VCNs. Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 6 ++---- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 +--- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 +--- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 7 ++----- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 7 ++----- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 4 +--- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 7 ++----- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 9 +++------ 11 files changed, 19 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index ad415203d245d..c2f69369bda67 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -257,12 +257,12 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int i) return 0; } -int amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int i) +void amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int i) { int j; if (adev->vcn.harvest_config & (1 << i)) - return 0; + return; amdgpu_bo_free_kernel( &adev->vcn.inst[i].dpg_sram_bo, @@ -292,8 +292,6 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int i) mutex_destroy(&adev->vcn.inst[i].vcn_pg_lock); mutex_destroy(&adev->vcn.inst[i].vcn1_jpeg1_workaround); - - return 0; } bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index 6d9acd36041d0..bebfc2b34afe6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -516,7 +516,7 @@ enum vcn_ring_type { int amdgpu_vcn_early_init(struct amdgpu_device *adev, int i); int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int i); -int amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int i); +void amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int i); int amdgpu_vcn_suspend(struct amdgpu_device *adev, int i); int amdgpu_vcn_resume(struct amdgpu_device *adev, int i); void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 1e89ba153d9d3..3c1c844c5fdee 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -230,11 +230,11 @@ static int vcn_v1_0_sw_fini(struct amdgpu_ip_block *ip_block) jpeg_v1_0_sw_fini(ip_block); - r = amdgpu_vcn_sw_fini(adev, 0); + amdgpu_vcn_sw_fini(adev, 0); kfree(adev->vcn.ip_dump); - return r; + return 0; } /** diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index b115137ab2d69..c4e2659f89333 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -267,9 +267,9 @@ static int vcn_v2_0_sw_fini(struct amdgpu_ip_block *ip_block) amdgpu_vcn_sysfs_reset_mask_fini(adev); - r = amdgpu_vcn_sw_fini(adev, 0); + amdgpu_vcn_sw_fini(adev, 0); - return r; + return 0; } /** diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index 904b94bc8693c..0505f09553244 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -442,9 +442,7 @@ static int vcn_v2_5_sw_fini(struct amdgpu_ip_block *ip_block) r = amdgpu_vcn_suspend(adev, i); if (r) return r; - r = amdgpu_vcn_sw_fini(adev, i); - if (r) - return r; + amdgpu_vcn_sw_fini(adev, i); } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index f3085137ba08b..77a8373444df3 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -349,9 +349,7 @@ static int vcn_v3_0_sw_fini(struct amdgpu_ip_block *ip_block) if (r) return r; - r = amdgpu_vcn_sw_fini(adev, i); - if (r) - return r; + amdgpu_vcn_sw_fini(adev, i); } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index bc9dfe5ffea71..870c563415af3 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -302,11 +302,8 @@ static int vcn_v4_0_sw_fini(struct amdgpu_ip_block *ip_block) amdgpu_vcn_sysfs_reset_mask_fini(adev); - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - r = amdgpu_vcn_sw_fini(adev, i); - if (r) - return r; - } + for (i = 0; i < adev->vcn.num_vcn_inst; i++) + amdgpu_vcn_sw_fini(adev, i); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index bae1ad4484ede..5fbd755fc24c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -283,11 +283,8 @@ static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) amdgpu_vcn_sysfs_reset_mask_fini(adev); - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - r = amdgpu_vcn_sw_fini(adev, i); - if (r) - return r; - } + for (i = 0; i < adev->vcn.num_vcn_inst; i++) + amdgpu_vcn_sw_fini(adev, i); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index 6dbf33b26ee27..732d4a78ab527 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -270,9 +270,7 @@ static int vcn_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block) if (r) return r; - r = amdgpu_vcn_sw_fini(adev, i); - if (r) - return r; + amdgpu_vcn_sw_fini(adev, i); } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index 536f06b817061..680df5d48c7a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -232,11 +232,8 @@ static int vcn_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block) amdgpu_vcn_sysfs_reset_mask_fini(adev); - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - r = amdgpu_vcn_sw_fini(adev, i); - if (r) - return r; - } + for (i = 0; i < adev->vcn.num_vcn_inst; i++) + amdgpu_vcn_sw_fini(adev, i); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c index 4b01e35ad7ef5..09e2e28041c0d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c @@ -245,14 +245,11 @@ static int vcn_v5_0_1_sw_fini(struct amdgpu_ip_block *ip_block) return r; } - for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - r = amdgpu_vcn_sw_fini(adev, i); - if (r) - return r; - } - amdgpu_vcn_sysfs_reset_mask_fini(adev); + for (i = 0; i < adev->vcn.num_vcn_inst; i++) + amdgpu_vcn_sw_fini(adev, i); + return 0; } From 4214675e6a1ef050c3a26a46ffb3dd1ad32fc53e Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Mon, 8 Sep 2025 17:15:36 -0600 Subject: [PATCH 1907/2653] drm/amdgpu: Remove volatile from CSB functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The CSB buffer manipulation occurs in memory where the BO is mapped during initialization, and some references to this buffer are handled with volatile, which is incorrect in this scenario. There are a few cases where the use of volatile is accepted, but none of them align with CSB operations. Therefore, this commit removes all the volatile variables associated with the CSB code. Reviewed-by: Christian König Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 6 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +-- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 3 +-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 3 +-- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 7 +++---- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 5 ++--- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 3 +-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 +-- 10 files changed, 18 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index c80c8f5435321..89fc1015d3a68 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -2279,7 +2279,7 @@ void amdgpu_gfx_profile_ring_end_use(struct amdgpu_ring *ring) * Return: * return the latest index. */ -u32 amdgpu_gfx_csb_preamble_start(volatile u32 *buffer) +u32 amdgpu_gfx_csb_preamble_start(u32 *buffer) { u32 count = 0; @@ -2303,7 +2303,7 @@ u32 amdgpu_gfx_csb_preamble_start(volatile u32 *buffer) * Return: * return the latest index. */ -u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, volatile u32 *buffer, u32 count) +u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, u32 *buffer, u32 count) { const struct cs_section_def *sect = NULL; const struct cs_extent_def *ext = NULL; @@ -2330,7 +2330,7 @@ u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, volatile u32 *buffer, * @buffer: This is an output variable that gets the PACKET3 preamble end. * @count: Index to start set the preemble end. */ -void amdgpu_gfx_csb_preamble_end(volatile u32 *buffer, u32 count) +void amdgpu_gfx_csb_preamble_end(u32 *buffer, u32 count) { buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 72e56a741c509..57e75a8078464 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -653,9 +653,9 @@ void amdgpu_gfx_enforce_isolation_ring_end_use(struct amdgpu_ring *ring); void amdgpu_gfx_profile_idle_work_handler(struct work_struct *work); void amdgpu_gfx_profile_ring_begin_use(struct amdgpu_ring *ring); void amdgpu_gfx_profile_ring_end_use(struct amdgpu_ring *ring); -u32 amdgpu_gfx_csb_preamble_start(volatile u32 *buffer); -u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, volatile u32 *buffer, u32 count); -void amdgpu_gfx_csb_preamble_end(volatile u32 *buffer, u32 count); +u32 amdgpu_gfx_csb_preamble_start(u32 *buffer); +u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, u32 *buffer, u32 count); +void amdgpu_gfx_csb_preamble_end(u32 *buffer, u32 count); void amdgpu_debugfs_gfx_sched_mask_init(struct amdgpu_device *adev); void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h index 9aae8acd32bc0..0c45fc012bb33 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h @@ -251,7 +251,7 @@ struct amdgpu_rlc_funcs { * and it also provides a pointer to it which is used by the firmware * to load the clear state in some cases. */ - void (*get_csb_buffer)(struct amdgpu_device *adev, volatile u32 *buffer); + void (*get_csb_buffer)(struct amdgpu_device *adev, u32 *buffer); int (*get_cp_table_num)(struct amdgpu_device *adev); int (*resume)(struct amdgpu_device *adev); void (*stop)(struct amdgpu_device *adev); @@ -282,7 +282,7 @@ struct amdgpu_rlc { /* for clear state */ struct amdgpu_bo *clear_state_obj; uint64_t clear_state_gpu_addr; - volatile uint32_t *cs_ptr; + uint32_t *cs_ptr; const struct cs_section_def *cs_data; u32 clear_state_size; /* for cp tables */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 7956f94c6cc61..f44e64e80ac28 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4322,8 +4322,7 @@ static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) return count; } -static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, - volatile u32 *buffer) +static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) { u32 count = 0; int ctx_reg_offset; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 76cb4092a60a1..380beb7683404 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -850,8 +850,7 @@ static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) return count; } -static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, - volatile u32 *buffer) +static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) { u32 count = 0; int ctx_reg_offset; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index c1703f64fb882..1571df5569bc8 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -685,8 +685,7 @@ static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev) return count; } -static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, - volatile u32 *buffer) +static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) { u32 count = 0, clustercount = 0, i; const struct cs_section_def *sect = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 70d7a1f434c4b..7693b79534267 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -86,7 +86,7 @@ MODULE_FIRMWARE("amdgpu/hainan_ce.bin"); MODULE_FIRMWARE("amdgpu/hainan_rlc.bin"); static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev); -static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); +static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer); //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); static void gfx_v6_0_init_pg(struct amdgpu_device *adev); @@ -2354,7 +2354,7 @@ static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) { const u32 *src_ptr; - volatile u32 *dst_ptr; + u32 *dst_ptr; u32 dws; u64 reg_list_mc_addr; const struct cs_section_def *cs_data; @@ -2855,8 +2855,7 @@ static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev) return count; } -static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, - volatile u32 *buffer) +static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) { u32 count = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 1c1a7046a5b37..00eb3ded8c27f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -883,7 +883,7 @@ static const u32 kalindi_rlc_save_restore_register_list[] = { }; static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev); -static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); +static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer); static void gfx_v7_0_init_pg(struct amdgpu_device *adev); static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev); @@ -3883,8 +3883,7 @@ static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev) return count; } -static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, - volatile u32 *buffer) +static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) { u32 count = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 731d45a2ed713..7f740daf7415e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -1220,8 +1220,7 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) return err; } -static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, - volatile u32 *buffer) +static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) { u32 count = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 4cec3a8925746..63ccded25aa46 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1648,8 +1648,7 @@ static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) return count; } -static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, - volatile u32 *buffer) +static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) { u32 count = 0; From aebeba7ab899deff262432708172ad5f646069a3 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Mon, 8 Sep 2025 17:15:37 -0600 Subject: [PATCH 1908/2653] drm/amdgpu: Remove volatile from RLC files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The RLC uses volatile with some pointers that are not directly related to any of the situations where volatile is advised to be used [1]. For this reason, this commit removes all the volatile occurrences associated with RLC. 1. https://docs.kernel.org/process/volatile-considered-harmful.html Reviewed-by: Christian König Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c index db5791e1a7cef..5aa830a02d80b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c @@ -89,7 +89,7 @@ void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev, int xcc_id) int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws) { const u32 *src_ptr; - volatile u32 *dst_ptr; + u32 *dst_ptr; u32 i; int r; @@ -189,7 +189,7 @@ int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev) void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev) { const __le32 *fw_data; - volatile u32 *dst_ptr; + u32 *dst_ptr; int me, i, max_me; u32 bo_offset = 0; u32 table_offset, table_size; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h index 0c45fc012bb33..3e2d2e333907d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h @@ -276,7 +276,7 @@ struct amdgpu_rlc { /* for power gating */ struct amdgpu_bo *save_restore_obj; uint64_t save_restore_gpu_addr; - volatile uint32_t *sr_ptr; + uint32_t *sr_ptr; const u32 *reg_list; u32 reg_list_size; /* for clear state */ @@ -288,7 +288,7 @@ struct amdgpu_rlc { /* for cp tables */ struct amdgpu_bo *cp_table_obj; uint64_t cp_table_gpu_addr; - volatile uint32_t *cp_table_ptr; + uint32_t *cp_table_ptr; u32 cp_table_size; /* safe mode for updating CG/PG state */ From ebbd33d7e67eabce11e122d2126e3857cd0ae82e Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Mon, 8 Sep 2025 17:15:38 -0600 Subject: [PATCH 1909/2653] drm/amdgpu: Remove volatile from ring manipulation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit None of the pointer operations handled by the ring file requires volatile, for this reason, this commit removes all occurrences of volatile associated with rings. Reviewed-by: Christian König Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 12 ++++++------ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 2 +- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 724c99bbc6797..7ec0f0ed55690 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -551,7 +551,7 @@ struct amdgpu_wb { * this value can be accessed directly by using the offset as an index. * For the GPU address, it is necessary to use gpu_addr and the offset. */ - volatile uint32_t *wb; + uint32_t *wb; /** * @gpu_addr: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 7670f5d82b9e4..80b85547c810b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -114,7 +114,7 @@ struct amdgpu_sched { */ struct amdgpu_fence_driver { uint64_t gpu_addr; - volatile uint32_t *cpu_addr; + uint32_t *cpu_addr; /* sync_seq is protected by ring emission lock */ uint32_t sync_seq; atomic_t last_seq; @@ -298,7 +298,7 @@ struct amdgpu_ring { unsigned int ring_backup_entries_to_copy; unsigned rptr_offs; u64 rptr_gpu_addr; - volatile u32 *rptr_cpu_addr; + u32 *rptr_cpu_addr; /** * @wptr: @@ -378,19 +378,19 @@ struct amdgpu_ring { * This is the CPU address pointer in the writeback slot. This is used * to commit changes to the GPU. */ - volatile u32 *wptr_cpu_addr; + u32 *wptr_cpu_addr; unsigned fence_offs; u64 fence_gpu_addr; - volatile u32 *fence_cpu_addr; + u32 *fence_cpu_addr; uint64_t current_ctx; char name[16]; u32 trail_seq; unsigned trail_fence_offs; u64 trail_fence_gpu_addr; - volatile u32 *trail_fence_cpu_addr; + u32 *trail_fence_cpu_addr; unsigned cond_exe_offs; u64 cond_exe_gpu_addr; - volatile u32 *cond_exe_cpu_addr; + u32 *cond_exe_cpu_addr; unsigned int set_q_mode_offs; u32 *set_q_mode_ptr; u64 set_q_mode_token; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index f44e64e80ac28..279be67679994 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4075,7 +4075,7 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) struct dma_fence *f = NULL; unsigned int index; uint64_t gpu_addr; - volatile uint32_t *cpu_ptr; + uint32_t *cpu_ptr; long r; memset(&ib, 0, sizeof(ib)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 380beb7683404..2d600218aa60b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -603,7 +603,7 @@ static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) struct dma_fence *f = NULL; unsigned index; uint64_t gpu_addr; - volatile uint32_t *cpu_ptr; + uint32_t *cpu_ptr; long r; /* MES KIQ fw hasn't indirect buffer support for now */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 1571df5569bc8..c95d907f1faa1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -497,7 +497,7 @@ static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) struct dma_fence *f = NULL; unsigned index; uint64_t gpu_addr; - volatile uint32_t *cpu_ptr; + uint32_t *cpu_ptr; long r; /* MES KIQ fw hasn't indirect buffer support for now */ From dbae8f60c248c0c9198ae423c609e47515e02fa5 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Mon, 8 Sep 2025 17:15:39 -0600 Subject: [PATCH 1910/2653] drm/amdgpu: Remove volatile from amdgpu and amdgpu_ih headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the unnecessary use of volatile in some of the amdgpu.h and amdgpu_ih.h headers. Reviewed-by: Christian König Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 7ec0f0ed55690..66fefd2e1a0fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -730,7 +730,7 @@ int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data, /* VRAM scratch page for HDP bug, default vram page */ struct amdgpu_mem_scratch { struct amdgpu_bo *robj; - volatile uint32_t *ptr; + uint32_t *ptr; u64 gpu_addr; }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h index 7f7ea046e2097..f58b6be7fccc0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h @@ -56,14 +56,14 @@ struct amdgpu_ih_ring { bool use_bus_addr; struct amdgpu_bo *ring_obj; - volatile uint32_t *ring; + uint32_t *ring; uint64_t gpu_addr; uint64_t wptr_addr; - volatile uint32_t *wptr_cpu; + uint32_t *wptr_cpu; uint64_t rptr_addr; - volatile uint32_t *rptr_cpu; + uint32_t *rptr_cpu; bool enabled; unsigned rptr; From 4363010a0c341955809632a812d19cbf5259bf31 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Mon, 8 Sep 2025 17:15:40 -0600 Subject: [PATCH 1911/2653] drm/amdgpu: Remove volatile references from VCN MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Christian König Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 12 ++++++------ drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 14 +++++++------- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 12 ++++++------ drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 12 ++++++------ 10 files changed, 51 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index c2f69369bda67..5ae7cc0d5f57a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -1157,7 +1157,7 @@ static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf, { struct amdgpu_vcn_inst *vcn; void *log_buf; - volatile struct amdgpu_vcn_fwlog *plog; + struct amdgpu_vcn_fwlog *plog; unsigned int read_pos, write_pos, available, i, read_bytes = 0; unsigned int read_num[2] = {0}; @@ -1170,7 +1170,7 @@ static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf, log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; - plog = (volatile struct amdgpu_vcn_fwlog *)log_buf; + plog = (struct amdgpu_vcn_fwlog *)log_buf; read_pos = plog->rptr; write_pos = plog->wptr; @@ -1237,11 +1237,11 @@ void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i, void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn) { #if defined(CONFIG_DEBUG_FS) - volatile uint32_t *flag = vcn->fw_shared.cpu_addr; + uint32_t *flag = vcn->fw_shared.cpu_addr; void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size; - volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr; - volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr + struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr; + struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr + vcn->fw_shared.log_offset; *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG); fw_log->is_enabled = 1; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 3c1c844c5fdee..a316797875a8f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -193,7 +193,7 @@ static int vcn_v1_0_sw_init(struct amdgpu_ip_block *ip_block) adev->vcn.inst[0].pause_dpg_mode = vcn_v1_0_pause_dpg_mode; if (amdgpu_vcnfw_log) { - volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; + struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; fw_shared->present_flag_0 = 0; amdgpu_vcn_fwlog_init(adev->vcn.inst); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index c4e2659f89333..8897dcc9c1a0a 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -137,7 +137,7 @@ static int vcn_v2_0_sw_init(struct amdgpu_ip_block *ip_block) struct amdgpu_ring *ring; int i, r; struct amdgpu_device *adev = ip_block->adev; - volatile struct amdgpu_fw_shared *fw_shared; + struct amdgpu_fw_shared *fw_shared; /* VCN DEC TRAP */ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, @@ -252,7 +252,7 @@ static int vcn_v2_0_sw_fini(struct amdgpu_ip_block *ip_block) { int r, idx; struct amdgpu_device *adev = ip_block->adev; - volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; + struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; if (drm_dev_enter(adev_to_drm(adev), &idx)) { fw_shared->present_flag_0 = 0; @@ -853,7 +853,7 @@ static void vcn_v2_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst) static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) { struct amdgpu_device *adev = vinst->adev; - volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; + struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; uint32_t rb_bufsz, tmp; int ret; @@ -1001,7 +1001,7 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) static int vcn_v2_0_start(struct amdgpu_vcn_inst *vinst) { struct amdgpu_device *adev = vinst->adev; - volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; + struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; uint32_t rb_bufsz, tmp; uint32_t lmi_swap_cntl; @@ -1308,7 +1308,7 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); if (!ret_code) { - volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; + struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; /* pause DPG */ reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index 0505f09553244..cebee453871c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -277,7 +277,7 @@ static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; for (j = 0; j < adev->vcn.num_vcn_inst; j++) { - volatile struct amdgpu_fw_shared *fw_shared; + struct amdgpu_fw_shared *fw_shared; if (adev->vcn.harvest_config & (1 << j)) continue; @@ -420,7 +420,7 @@ static int vcn_v2_5_sw_fini(struct amdgpu_ip_block *ip_block) { int i, r, idx; struct amdgpu_device *adev = ip_block->adev; - volatile struct amdgpu_fw_shared *fw_shared; + struct amdgpu_fw_shared *fw_shared; if (drm_dev_enter(adev_to_drm(adev), &idx)) { for (i = 0; i < adev->vcn.num_vcn_inst; i++) { @@ -998,7 +998,7 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) { struct amdgpu_device *adev = vinst->adev; int inst_idx = vinst->inst; - volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; + struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; struct amdgpu_ring *ring; uint32_t rb_bufsz, tmp; int ret; @@ -1155,7 +1155,7 @@ static int vcn_v2_5_start(struct amdgpu_vcn_inst *vinst) { struct amdgpu_device *adev = vinst->adev; int i = vinst->inst; - volatile struct amdgpu_fw_shared *fw_shared = + struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; struct amdgpu_ring *ring; uint32_t rb_bufsz, tmp; @@ -1667,7 +1667,7 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); if (!ret_code) { - volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; + struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; /* pause DPG */ reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 77a8373444df3..d9cf8f0feeb3e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -191,7 +191,7 @@ static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block) } for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - volatile struct amdgpu_fw_shared *fw_shared; + struct amdgpu_fw_shared *fw_shared; if (adev->vcn.harvest_config & (1 << i)) continue; @@ -327,7 +327,7 @@ static int vcn_v3_0_sw_fini(struct amdgpu_ip_block *ip_block) if (drm_dev_enter(adev_to_drm(adev), &idx)) { for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - volatile struct amdgpu_fw_shared *fw_shared; + struct amdgpu_fw_shared *fw_shared; if (adev->vcn.harvest_config & (1 << i)) continue; @@ -1029,7 +1029,7 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) { struct amdgpu_device *adev = vinst->adev; int inst_idx = vinst->inst; - volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; + struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; struct amdgpu_ring *ring; uint32_t rb_bufsz, tmp; int ret; @@ -1194,7 +1194,7 @@ static int vcn_v3_0_start(struct amdgpu_vcn_inst *vinst) { struct amdgpu_device *adev = vinst->adev; int i = vinst->inst; - volatile struct amdgpu_fw_shared *fw_shared; + struct amdgpu_fw_shared *fw_shared; struct amdgpu_ring *ring; uint32_t rb_bufsz, tmp; int j, k, r; @@ -1715,7 +1715,7 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, { struct amdgpu_device *adev = vinst->adev; int inst_idx = vinst->inst; - volatile struct amdgpu_fw_shared *fw_shared; + struct amdgpu_fw_shared *fw_shared; struct amdgpu_ring *ring; uint32_t reg_data = 0; int ret_code; @@ -1834,7 +1834,7 @@ static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - volatile struct amdgpu_fw_shared *fw_shared; + struct amdgpu_fw_shared *fw_shared; if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */ diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 870c563415af3..8d3f18b55fc26 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -148,7 +148,7 @@ static int vcn_v4_0_early_init(struct amdgpu_ip_block *ip_block) static int vcn_v4_0_fw_shared_init(struct amdgpu_device *adev, int inst_idx) { - volatile struct amdgpu_vcn4_fw_shared *fw_shared; + struct amdgpu_vcn4_fw_shared *fw_shared; fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); @@ -278,7 +278,7 @@ static int vcn_v4_0_sw_fini(struct amdgpu_ip_block *ip_block) if (drm_dev_enter(adev_to_drm(adev), &idx)) { for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - volatile struct amdgpu_vcn4_fw_shared *fw_shared; + struct amdgpu_vcn4_fw_shared *fw_shared; if (adev->vcn.harvest_config & (1 << i)) continue; @@ -997,7 +997,7 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) { struct amdgpu_device *adev = vinst->adev; int inst_idx = vinst->inst; - volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; + struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; struct amdgpu_ring *ring; uint32_t tmp; int ret; @@ -1137,7 +1137,7 @@ static int vcn_v4_0_start(struct amdgpu_vcn_inst *vinst) { struct amdgpu_device *adev = vinst->adev; int i = vinst->inst; - volatile struct amdgpu_vcn4_fw_shared *fw_shared; + struct amdgpu_vcn4_fw_shared *fw_shared; struct amdgpu_ring *ring; uint32_t tmp; int j, k, r; @@ -1354,8 +1354,8 @@ static int vcn_v4_0_start_sriov(struct amdgpu_device *adev) struct mmsch_v4_0_cmd_end end = { {0} }; struct mmsch_v4_0_init_header header; - volatile struct amdgpu_vcn4_fw_shared *fw_shared; - volatile struct amdgpu_fw_shared_rb_setup *rb_setup; + struct amdgpu_vcn4_fw_shared *fw_shared; + struct amdgpu_fw_shared_rb_setup *rb_setup; direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; @@ -1606,7 +1606,7 @@ static int vcn_v4_0_stop(struct amdgpu_vcn_inst *vinst) { struct amdgpu_device *adev = vinst->adev; int i = vinst->inst; - volatile struct amdgpu_vcn4_fw_shared *fw_shared; + struct amdgpu_vcn4_fw_shared *fw_shared; uint32_t tmp; int r = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 5fbd755fc24c0..eacf4e93ba2fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -263,7 +263,7 @@ static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) if (drm_dev_enter(&adev->ddev, &idx)) { for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - volatile struct amdgpu_vcn4_fw_shared *fw_shared; + struct amdgpu_vcn4_fw_shared *fw_shared; fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; fw_shared->present_flag_0 = 0; @@ -845,7 +845,7 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_vcn_inst *vinst, { struct amdgpu_device *adev = vinst->adev; int inst_idx = vinst->inst; - volatile struct amdgpu_vcn4_fw_shared *fw_shared = + struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; struct amdgpu_ring *ring; int vcn_inst, ret; @@ -1012,8 +1012,8 @@ static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev) struct mmsch_v4_0_cmd_end end = { {0} }; struct mmsch_v4_0_3_init_header header; - volatile struct amdgpu_vcn4_fw_shared *fw_shared; - volatile struct amdgpu_fw_shared_rb_setup *rb_setup; + struct amdgpu_vcn4_fw_shared *fw_shared; + struct amdgpu_fw_shared_rb_setup *rb_setup; direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; @@ -1187,7 +1187,7 @@ static int vcn_v4_0_3_start(struct amdgpu_vcn_inst *vinst) { struct amdgpu_device *adev = vinst->adev; int i = vinst->inst; - volatile struct amdgpu_vcn4_fw_shared *fw_shared; + struct amdgpu_vcn4_fw_shared *fw_shared; struct amdgpu_ring *ring; int j, k, r, vcn_inst; uint32_t tmp; @@ -1397,7 +1397,7 @@ static int vcn_v4_0_3_stop(struct amdgpu_vcn_inst *vinst) { struct amdgpu_device *adev = vinst->adev; int i = vinst->inst; - volatile struct amdgpu_vcn4_fw_shared *fw_shared; + struct amdgpu_vcn4_fw_shared *fw_shared; int r = 0, vcn_inst; uint32_t tmp; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index 732d4a78ab527..b107ee80e4728 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -149,7 +149,7 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block) int i, r; for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - volatile struct amdgpu_vcn4_fw_shared *fw_shared; + struct amdgpu_vcn4_fw_shared *fw_shared; if (adev->vcn.harvest_config & (1 << i)) continue; @@ -249,7 +249,7 @@ static int vcn_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block) if (drm_dev_enter(adev_to_drm(adev), &idx)) { for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - volatile struct amdgpu_vcn4_fw_shared *fw_shared; + struct amdgpu_vcn4_fw_shared *fw_shared; if (adev->vcn.harvest_config & (1 << i)) continue; @@ -910,7 +910,7 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, { struct amdgpu_device *adev = vinst->adev; int inst_idx = vinst->inst; - volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; + struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; struct amdgpu_ring *ring; uint32_t tmp; int ret; @@ -1047,7 +1047,7 @@ static int vcn_v4_0_5_start(struct amdgpu_vcn_inst *vinst) { struct amdgpu_device *adev = vinst->adev; int i = vinst->inst; - volatile struct amdgpu_vcn4_fw_shared *fw_shared; + struct amdgpu_vcn4_fw_shared *fw_shared; struct amdgpu_ring *ring; uint32_t tmp; int j, k, r; @@ -1266,7 +1266,7 @@ static int vcn_v4_0_5_stop(struct amdgpu_vcn_inst *vinst) { struct amdgpu_device *adev = vinst->adev; int i = vinst->inst; - volatile struct amdgpu_vcn4_fw_shared *fw_shared; + struct amdgpu_vcn4_fw_shared *fw_shared; uint32_t tmp; int r = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index 680df5d48c7a0..0202df5db1e12 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -129,7 +129,7 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block) int i, r; for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - volatile struct amdgpu_vcn5_fw_shared *fw_shared; + struct amdgpu_vcn5_fw_shared *fw_shared; if (adev->vcn.harvest_config & (1 << i)) continue; @@ -211,7 +211,7 @@ static int vcn_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block) if (drm_dev_enter(adev_to_drm(adev), &idx)) { for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - volatile struct amdgpu_vcn5_fw_shared *fw_shared; + struct amdgpu_vcn5_fw_shared *fw_shared; if (adev->vcn.harvest_config & (1 << i)) continue; @@ -692,7 +692,7 @@ static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, { struct amdgpu_device *adev = vinst->adev; int inst_idx = vinst->inst; - volatile struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; + struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; struct amdgpu_ring *ring; uint32_t tmp; int ret; @@ -802,7 +802,7 @@ static int vcn_v5_0_0_start(struct amdgpu_vcn_inst *vinst) { struct amdgpu_device *adev = vinst->adev; int i = vinst->inst; - volatile struct amdgpu_vcn5_fw_shared *fw_shared; + struct amdgpu_vcn5_fw_shared *fw_shared; struct amdgpu_ring *ring; uint32_t tmp; int j, k, r; @@ -995,7 +995,7 @@ static int vcn_v5_0_0_stop(struct amdgpu_vcn_inst *vinst) { struct amdgpu_device *adev = vinst->adev; int i = vinst->inst; - volatile struct amdgpu_vcn5_fw_shared *fw_shared; + struct amdgpu_vcn5_fw_shared *fw_shared; uint32_t tmp; int r = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c index 09e2e28041c0d..9c281ba6bcedc 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c @@ -226,7 +226,7 @@ static int vcn_v5_0_1_sw_fini(struct amdgpu_ip_block *ip_block) if (drm_dev_enter(adev_to_drm(adev), &idx)) { for (i = 0; i < adev->vcn.num_vcn_inst; i++) { - volatile struct amdgpu_vcn5_fw_shared *fw_shared; + struct amdgpu_vcn5_fw_shared *fw_shared; fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; fw_shared->present_flag_0 = 0; @@ -640,7 +640,7 @@ static int vcn_v5_0_1_start_dpg_mode(struct amdgpu_vcn_inst *vinst, { struct amdgpu_device *adev = vinst->adev; int inst_idx = vinst->inst; - volatile struct amdgpu_vcn5_fw_shared *fw_shared = + struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; struct amdgpu_ring *ring; struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__PAUSE}; @@ -776,8 +776,8 @@ static int vcn_v5_0_1_start_sriov(struct amdgpu_device *adev) struct mmsch_v5_0_cmd_end end = { {0} }; struct mmsch_v5_0_init_header header; - volatile struct amdgpu_vcn5_fw_shared *fw_shared; - volatile struct amdgpu_fw_shared_rb_setup *rb_setup; + struct amdgpu_vcn5_fw_shared *fw_shared; + struct amdgpu_fw_shared_rb_setup *rb_setup; direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; @@ -951,7 +951,7 @@ static int vcn_v5_0_1_start(struct amdgpu_vcn_inst *vinst) { struct amdgpu_device *adev = vinst->adev; int i = vinst->inst; - volatile struct amdgpu_vcn5_fw_shared *fw_shared; + struct amdgpu_vcn5_fw_shared *fw_shared; struct amdgpu_ring *ring; uint32_t tmp; int j, k, r, vcn_inst; @@ -1143,7 +1143,7 @@ static int vcn_v5_0_1_stop(struct amdgpu_vcn_inst *vinst) { struct amdgpu_device *adev = vinst->adev; int i = vinst->inst; - volatile struct amdgpu_vcn5_fw_shared *fw_shared; + struct amdgpu_vcn5_fw_shared *fw_shared; uint32_t tmp; int r = 0, vcn_inst; From b70e506746def9ea22e307c6f7f58ee9e29427f2 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Tue, 22 Jul 2025 16:24:17 -0400 Subject: [PATCH 1912/2653] drm/amdkfd: Add AMD Infinity Storage (AIS) support Init: Driver during load calls pci_p2pdma_add_resource which creates struct MEMORY_DEVICE_PCI_P2PDMA pages for the whole VRAM region. Operation: Add ioctl AMDKFD_IOC_AIS_OP that provides support for transferring data directly from GPU VRAM to storage device. The storage device has to backed by a PCI device capable of carrying out P2P. Driver (amdgpu) fills in block I/O vector bio_vec with VRAM P2P pages and requests the block device to carry-out out direct DMA. Current support is limited to dGPUs with large BAR v2: Add in/out ioctl arguments to provide more status information to user space. Signed-off-by: Harish Kasiviswanathan Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/Makefile | 3 +- drivers/gpu/drm/amd/amdkfd/kfd_ais.c | 265 +++++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 94 ++++++++ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 3 + drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 9 + include/uapi/linux/kfd_ioctl.h | 66 +++++- 6 files changed, 438 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_ais.c diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 826fe822b61d2..02cc2fd663955 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -63,7 +63,8 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_trace.o \ $(AMDKFD_PATH)/kfd_spm.o \ $(AMDKFD_PATH)/kfd_debug.o \ - $(AMDKFD_PATH)/kfd_pc_sampling.o + $(AMDKFD_PATH)/kfd_pc_sampling.o \ + $(AMDKFD_PATH)/kfd_ais.o ifneq ($(CONFIG_DEBUG_FS),) AMDKFD_FILES += $(AMDKFD_PATH)/kfd_debugfs.o diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c new file mode 100644 index 0000000000000..03e76626535c3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "kfd_priv.h" +#include "amdgpu_amdkfd.h" +#include +#include +#include +#include +#include + +/* Each VRAM page uses sizeof(struct page) on system memory */ +#define AIS_P2P_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) + +/* + * get_pci_dev_from_file - Get the PCI device that is hosting the file. + * For e.g., the NVME PCI device that is hosting the file. + * + * @file: The file pointer from which to derive the PCI device. + * Returns: Pointer to the PCI device if found, NULL otherwise. + */ +static struct pci_dev *get_pci_dev_from_file(struct file *file) +{ + struct device *dev; + struct pci_dev *pdev = NULL; + + if (!file->f_path.mnt || !file->f_path.mnt->mnt_sb || + !file->f_path.mnt->mnt_sb->s_bdev) { + pr_err("Invalid file path or mount point\n"); + return NULL; + } + + dev = file->f_path.mnt->mnt_sb->s_bdev->bd_device.parent; + if (!dev) { + pr_debug("No parent device found for the file\n"); + return NULL; + } + + /* Traverse up the device hierarchy to find a PCI device */ + while (dev && !dev_is_pci(dev)) + dev = dev->parent; + + if (dev && dev_is_pci(dev)) + pdev = to_pci_dev(dev); + + + return pdev; +} + +static struct bio_vec *amdgpu_init_bvec(struct sg_table *sgt, uint64_t size, + unsigned int *nr_segs) +{ + struct scatterlist *sg; + struct bio_vec *bvec; + uint64_t sg_len; + int64_t sg_offset = 0; + struct page *page; + unsigned int i, k = 0; + + bvec = kvcalloc(sgt->nents, sizeof(*bvec), GFP_KERNEL); + if (!bvec) + return NULL; + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + page = pfn_to_page(PHYS_PFN(sg_dma_address(sg))); + if (!page || !is_pci_p2pdma_page(page)) { + /* If the page is not PCI P2P, we cannot use it */ + pr_err("Invalid PCI P2P page!\n"); + kvfree(bvec); + return NULL; + } + sg_offset = sg_dma_address(sg) - __pfn_to_phys(page_to_pfn(page)); + if (sg_offset < 0 || sg_offset >= sg->length) { + pr_err("Invalid sg_offset: %lld\n", sg_offset); + kvfree(bvec); + return NULL; + } + + sg_len = min(sg->length, size); + pr_debug("sg[%d] offset:%llx, size:%llx\n", i, sg_offset, sg_len); + + bvec[k].bv_page = page; + bvec[k].bv_len = sg_len; + bvec[k].bv_offset = sg_offset; + k++; + + size -= sg_len; + if ((int64_t)size <= 0) + break; + } + + *nr_segs = k; + return bvec; +} + +/* Each VRAM page uses sizeof(struct page) on system memory */ +#define AIS_P2P_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) + +int kfd_ais_init(struct amdgpu_device *adev) +{ +#ifdef CONFIG_PCI_P2PDMA + int ret; + unsigned long size = ALIGN(adev->gmc.real_vram_size, 2ULL << 20); + bool is_large_bar = adev->gmc.visible_vram_size && + adev->gmc.real_vram_size == adev->gmc.visible_vram_size; + + /* AIS support limited to large BAR dGPUs */ + if (adev->flags & AMD_IS_APU || adev->gmc.xgmi.connected_to_cpu || !is_large_bar) { + dev_dbg(adev->dev, "AIS: only supported for large BAR dGPU\n"); + return 0; + } + + ret = pci_p2pdma_add_resource(adev->pdev, 0 /*bar*/, 0 /*whole VRAM*/, + 0 /*offset*/); + if (ret) { + dev_dbg(adev->dev, "AIS: Failed to add PCI P2PDMA resource for VRAM %d\n", ret); + return 0; + } + dev_dbg(adev->dev, "AIS: reserve %ldMB system memory for VRAM (P2P) pages struct\n", + AIS_P2P_PAGE_STRUCT_SIZE(size) >> 20); + + amdgpu_amdkfd_reserve_system_mem(AIS_P2P_PAGE_STRUCT_SIZE(size)); + dev_info(adev->dev, "AIS: registered %ldMB device memory\n", size >> 20); + + adev->kfd.dev->ais_initialized = true; +#else + dev_dbg(adev->dev, "AIS: not supported. Check CONFIG_PCI_P2PDMA\n"); +#endif + return 0; +} + +void kfd_ais_deinit(struct amdgpu_device *adev) +{ + if (adev->kfd.dev->ais_initialized) { + unsigned long pci_start_pfn = PHYS_PFN(pci_resource_start(adev->pdev, 0)); + struct page *p2p_page = NULL; + + if (pfn_valid(pci_start_pfn)) { + p2p_page = pfn_to_page(pci_start_pfn); + if (p2p_page && is_pci_p2pdma_page(p2p_page) && + page_pgmap(p2p_page)) + devm_memunmap_pages(&adev->pdev->dev, page_pgmap(p2p_page)); + } + adev->kfd.dev->ais_initialized = false; + } +} + +int kfd_ais_rw_file(struct amdgpu_device *adev, struct amdgpu_bo *bo, + struct kfd_ais_in_args *in, uint64_t *size_copied) +{ + struct file *filep; + struct pci_dev *pdev; + struct sg_table *sgt; + int nr_segs = 0, retry = 3; + struct iov_iter iter; + struct kiocb kiocb; + struct bio_vec *bvec; + loff_t cur_pos; + int ret = 0; + bool is_read = (in->op == KFD_IOC_AIS_READ); + + /* For now support only page-aligned offsets and sizes. It could be + * improved to fs block size in the future + */ + if (!PAGE_ALIGNED(in->file_offset) || !PAGE_ALIGNED(in->size)) + return -EINVAL; + + filep = fget((unsigned int)in->fd); + if (!filep) + return -EBADF; + + pdev = get_pci_dev_from_file(filep); + if (!pdev) { + ret = -ENODEV; + goto out; + } + + if (pci_p2pdma_distance(pdev, adev->dev, false) < 0) { + dev_info(adev->dev, "DMA-BUF p2p not accessible!\n"); + ret = -ENODEV; + goto out; + } + + if (WARN_ON(bo->preferred_domains != AMDGPU_GEM_DOMAIN_VRAM)) { + ret = -EINVAL; + goto out; + } + /* Use NULL instead of peer pdev. This is deliberate so that + * sg_dma_address is set to physical address instead of dma mapped + * address. This helps in getting struct p2p_page that bvec needs. + * This should work irrespective of iommu + */ + ret = amdgpu_amdkfd_gpuvm_get_sg_table(adev, bo, 0, in->handle_offset, + in->size, NULL, DMA_BIDIRECTIONAL, &sgt); + if (ret) { + dev_err(adev->dev, "AIS: failed to get SG table\n"); + goto out; + } + + bvec = amdgpu_init_bvec(sgt, in->size, &nr_segs); + if (!bvec) { + ret = -ENOMEM; + goto put_sg; + } + + iov_iter_bvec(&iter, is_read ? ITER_DEST : ITER_SOURCE, bvec, nr_segs, in->size); + init_sync_kiocb(&kiocb, filep); + kiocb.ki_pos = cur_pos = in->file_offset; + if (filep->f_flags & O_DIRECT) + kiocb.ki_flags |= IOCB_DIRECT; + + *size_copied = 0; + while (kiocb.ki_pos < in->file_offset + in->size) { + if (is_read) + ret = vfs_iocb_iter_read(filep, &kiocb, &iter); + else + ret = vfs_iocb_iter_write(filep, &kiocb, &iter); + if (ret <= 0) { + dev_err(adev->dev, "AIS: vfs transfer failed %d\n", ret); + break; + } else if (cur_pos == kiocb.ki_pos) { + /* No progress made, retry */ + if (retry-- > 0) { + dev_warn(adev->dev, "AIS: vfs transfer stalled, retrying...\n"); + continue; + } + dev_err(adev->dev, "AIS: vfs transfer stalled, giving up\n"); + ret = -EIO; + break; + } + cur_pos = kiocb.ki_pos; + *size_copied += ret; + } + + if (ret > 0) + dev_dbg(adev->dev, "AIS: vfs transfer %llu bytes\n", *size_copied); + + kvfree(bvec); +put_sg: + amdgpu_amdkfd_gpuvm_put_sg_table(bo, NULL, DMA_BIDIRECTIONAL, sgt); +out: + fput(filep); + return ret < 0 ? ret : 0; + +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 77c21c6e09b30..4900ccf9c7940 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -3454,6 +3454,97 @@ static int kfd_ioctl_profiler(struct file *filep, struct kfd_process *p, void *d return -EINVAL; } +static int kfd_ioctl_ais(struct file *filep, struct kfd_process *p, void *data) +{ + struct kfd_ioctl_ais_args *args = data; + struct kfd_ais_in_args *in = &args->in; + struct kfd_ais_out_args __user *out = &args->out, out_args = {0}; + struct kfd_process_device *pdd; + struct kfd_node *dev; + struct kfd_bo *buf_obj; + struct amdgpu_bo *bo; + int err; + + if (in->op != KFD_IOC_AIS_READ && in->op != KFD_IOC_AIS_WRITE) { + pr_debug("AIS: Invalid operation: %d\n", in->op); + err = -EINVAL; + goto err_inval; + } + + if (in->fd < 0) { + pr_debug("AIS: fd: %d\n", in->fd); + err = -EINVAL; + goto err_inval; + } + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(in->handle)); + if (!pdd) { + pr_debug("AIS: Could not find gpu id 0x%llx\n", GET_GPU_ID(in->handle)); + err = -EINVAL; + goto err_pdd; + } + dev = pdd->dev; + if (!dev->kfd->ais_initialized) { + dev_dbg(dev->adev->dev, "AIS: is not initialized for device\n"); + err = -ENODEV; + goto err_pdd; + } + + pdd = kfd_bind_process_to_device(dev, p); + if (IS_ERR(pdd)) { + err = -ESRCH; + goto err_bind_process; + } + + buf_obj = kfd_process_device_find_bo(pdd, GET_IDR_HANDLE(in->handle)); + if (!buf_obj) { + err = -EINVAL; + goto err_bind_process; + } + bo = ((struct kgd_mem *)buf_obj->mem)->bo; + + /* Only VRAM BOs are supported */ + if (((struct kgd_mem *)buf_obj->mem)->domain != AMDGPU_GEM_DOMAIN_VRAM) { + dev_dbg(dev->adev->dev, "AIS: BO not in VRAM, but in %d\n", + ((struct kgd_mem *)buf_obj)->domain); + err = -EINVAL; + goto err_bind_process; + } + + /* + * Concurrent data transfers on the same buffer is allowed. Pin it before + * releasing the lock. This ensures that BO remains valid when file system + * is accessing it + */ + err = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_VRAM); + if (err) { + pr_err("Pinning of buffer failed.\n"); + goto err_bind_process; + } + + mutex_unlock(&p->mutex); + + err = kfd_ais_rw_file(dev->adev, bo, in, &out_args.size_copied); + if (err) { + pr_err("Failed to %s AIS file: %d\n", + in->op == KFD_IOC_AIS_READ ? "read" : "write", err); + out_args.status = err; + } + + amdgpu_amdkfd_gpuvm_unpin_bo(bo); + memcpy(out, &out_args, sizeof(out_args)); + return err; + +err_pdd: +err_bind_process: + mutex_unlock(&p->mutex); +err_inval: + out_args.status = err; + memcpy(out, &out_args, sizeof(out_args)); + return err; +} + #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ .cmd_drv = 0, .name = #ioctl} @@ -3594,6 +3685,9 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_PROFILER, kfd_ioctl_profiler, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_AIS_OP, + kfd_ioctl_ais, 0), }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index cca32792941c8..e4982e7721d5b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -934,6 +934,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, svm_range_set_max_pages(kfd->adev); + kfd_ais_init(kfd->adev); + kfd->init_complete = true; dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, kfd->adev->pdev->device); @@ -963,6 +965,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, void kgd2kfd_device_exit(struct kfd_dev *kfd) { if (kfd->init_complete) { + kfd_ais_deinit(kfd->adev); /* Cleanup KFD nodes */ kfd_cleanup_nodes(kfd, kfd->num_nodes); /* Cleanup common/shared resources */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 8a291d0d7312f..6189d62d48625 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -446,6 +446,9 @@ struct kfd_dev { struct mutex profiler_lock; /* Process currently holding the lock */ struct kfd_process *profiler_process; + + /* flag for AIS */ + bool ais_initialized; }; struct kfd_ipc_obj; @@ -1738,6 +1741,12 @@ static inline bool kfd_is_first_node(struct kfd_node *node) return (node == node->kfd->nodes[0]); } +/* AIS Support */ +int kfd_ais_init(struct amdgpu_device *adev); +void kfd_ais_deinit(struct amdgpu_device *adev); +int kfd_ais_rw_file(struct amdgpu_device *adev, struct amdgpu_bo *bo, + struct kfd_ais_in_args *in, uint64_t *size_copied); + /* Debugfs */ #if defined(CONFIG_DEBUG_FS) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 08a6d86666320..bdeebc8caebff 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1764,6 +1764,67 @@ struct kfd_ioctl_profiler_args { }; }; +/** + * kfd_ais_ops - AIS ioctl operations + * + * @KFD_IOC_AIS_READ: Direct IO read from a file into VRAM + * @KFD_IOC_AIS_WRITE: Direct IO write into a file into VRAM + */ +enum kfd_ais_ops { + KFD_IOC_AIS_READ = 1, + KFD_IOC_AIS_WRITE = 2, +}; + +/** + * kfd_ais_in_args + * + * Arguments for AMDKFD_IOC_AIS_OP + * AIS (AMD Infinity Storage) operations. + * + * @op (IN) - kfd_ais_ops + * @fd (IN) - file descriptor of the file to read/write + * @handle (IN) - memory handle returned by alloc. Should be mapped to + * the GPU with AMDKFD_IOC_MAP_MEMORY_TO_GPU. + * @handle_offset (IN) - offset into the allocated memory to read/write + * @file_offset (IN) - offset from the beginning of the file to read/write + * @size (IN) - size in bytes to read/write + */ + +struct kfd_ais_in_args { + __u64 handle; /* to KFD */ + __u64 handle_offset; /* to KFD */ + __s64 file_offset; /* to KFD */ + __u64 size; /* to KFD */ + __u32 op; /* to KFD */ + __s32 fd; /* to KFD */ +}; + +/** + * kfd_ais_out_args + * + * @size_copied (OUT) KFD returns number of bytes transferred + * @status (OUT) 0 for success and -ve error values if failure + */ +struct kfd_ais_out_args { + __u64 size_copied; /* from KFD */ + __s32 status; /* from KFD */ + __s32 pad; /* unused */ +}; + +/** + * Arguments for AMDKFD_IOC_AIS_OP + * AIS (AMD Infinity Storage) operations. + * See @kfd_ais_in_args and @kfd_ais_out_args + */ + +struct kfd_ioctl_ais_args { + union { + struct kfd_ais_in_args in; + struct kfd_ais_out_args out; + }; +}; + + #define AMDKFD_IOCTL_BASE 'K' #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) @@ -1909,7 +1970,10 @@ struct kfd_ioctl_profiler_args { #define AMDKFD_IOC_PROFILER \ AMDKFD_IOWR(0x86, struct kfd_ioctl_profiler_args) +#define AMDKFD_IOC_AIS_OP \ + AMDKFD_IOWR(0x87, struct kfd_ioctl_ais_args) + #define AMDKFD_COMMAND_START_2 0x80 -#define AMDKFD_COMMAND_END_2 0x87 +#define AMDKFD_COMMAND_END_2 0x88 #endif From b1462562be59154dd399423e911f7780322d2614 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Wed, 3 Sep 2025 17:24:54 +0800 Subject: [PATCH 1913/2653] drm/amdkcl: wrap code under HAVE_BLOCK_DEVICE_BD_DEVICE it's caused by 7f12d388fc290 "drm/amdkfd: Add AMD Infinity Storage (AIS) support" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkfd/kfd_ais.c | 7 +++++-- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/blk_types.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 26 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/blk_types.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c index 03e76626535c3..73d50ecf184f7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c @@ -28,7 +28,7 @@ #include #include #include - +#include /* Each VRAM page uses sizeof(struct page) on system memory */ #define AIS_P2P_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) @@ -49,8 +49,11 @@ static struct pci_dev *get_pci_dev_from_file(struct file *file) pr_err("Invalid file path or mount point\n"); return NULL; } - +#ifdef HAVE_BLOCK_DEVICE_BD_DEVICE dev = file->f_path.mnt->mnt_sb->s_bdev->bd_device.parent; +#else + dev = disk_to_dev(file->f_path.mnt->mnt_sb->s_bdev->bd_disk)->parent; +#endif if (!dev) { pr_debug("No parent device found for the file\n"); return NULL; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8ce7c0eccbaa7..9d14e76694b06 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -85,6 +85,9 @@ /* bitmap_to_arr32() is available */ #define HAVE_BITMAP_TO_ARR32 1 +/* struct block_device has member named 'bd_device' */ +#define HAVE_BLOCK_DEVICE_BD_DEVICE 1 + /* cancel_work() is available */ #define HAVE_CANCEL_WORK 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/blk_types.m4 b/drivers/gpu/drm/amd/dkms/m4/blk_types.m4 new file mode 100644 index 0000000000000..6c92962c97e00 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/blk_types.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.10-rc4-97-g0d02129e76ed +dnl # block: merge struct block_device and struct hd_struct +dnl # +AC_DEFUN([AC_AMDGPU_BLOCK_DEVICE_BD_DEVICE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct block_device *device; + device.bd_device = NULL; + ], [],[],[ + AC_DEFINE(HAVE_BLOCK_DEVICE_BD_DEVICE, 1, + [struct block_device has member named 'bd_device']) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6679a0ec52939..dd94dafd440af 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -291,6 +291,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_VBLANK_CRTC_STRUCT_CONFIG AC_AMDGPU_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN AC_AMDGPU_DRM_DP_AUX_DPCD_PROBE_DISABLED + AC_AMDGPU_BLOCK_DEVICE_BD_DEVICE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 5d12919eeed71bb7979b6dfce475423305617ea7 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 4 Sep 2025 11:09:27 +0800 Subject: [PATCH 1914/2653] drm/amdkcl: wrap code under HAVE_PAGE_PGMAP it's caused by 7f12d388fc290 "drm/amdkfd: Add AMD Infinity Storage (AIS) support" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkfd/kfd_ais.c | 8 +++++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/page_flag.m4 | 16 ++++++++++++++++ 4 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/page_flag.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c index 73d50ecf184f7..f4dd34909cfd4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c @@ -160,10 +160,16 @@ void kfd_ais_deinit(struct amdgpu_device *adev) if (pfn_valid(pci_start_pfn)) { p2p_page = pfn_to_page(pci_start_pfn); +#ifdef HAVE_PAGE_PGMAP if (p2p_page && is_pci_p2pdma_page(p2p_page) && page_pgmap(p2p_page)) devm_memunmap_pages(&adev->pdev->dev, page_pgmap(p2p_page)); - } +#else + if (p2p_page && is_pci_p2pdma_page(p2p_page) && + p2p_page->pgmap) + devm_memunmap_pages(&adev->pdev->dev, p2p_page->pgmap); +#endif + } adev->kfd.dev->ais_initialized = false; } } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9d14e76694b06..a26a1b4fe8ef5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1051,6 +1051,9 @@ /* class_create has one argument */ #define HAVE_ONE_ARGUMENT_OF_CLASS_CREATE 1 +/* page_pgmap() is available */ +#define HAVE_PAGE_PGMAP 1 + /* pcie_aspm_enabled() is available */ #define HAVE_PCIE_ASPM_ENABLED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index dd94dafd440af..44885579aa2e3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -292,6 +292,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN AC_AMDGPU_DRM_DP_AUX_DPCD_PROBE_DISABLED AC_AMDGPU_BLOCK_DEVICE_BD_DEVICE + AC_AMDGPU_PAGE_PGMAP AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/page_flag.m4 b/drivers/gpu/drm/amd/dkms/m4/page_flag.m4 new file mode 100644 index 0000000000000..411f154c31e59 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/page_flag.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.14-rc6-302-g82ba975e4c43 +dnl # mm: allow compound zone device pages +dnl # +AC_DEFUN([AC_AMDGPU_PAGE_PGMAP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + page_pgmap(NULL); + ], [ + AC_DEFINE(HAVE_PAGE_PGMAP, 1, + [page_pgmap() is available]) + ]) + ]) +]) From 6f76d4ce9ac7da392a141756ded4ab7b6f374d0b Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 4 Sep 2025 11:10:13 +0800 Subject: [PATCH 1915/2653] drm/amdkcl: test if ITER_SOURCE/ITER_DEST exist it's caused by 7f12d388fc290 "drm/amdkfd: Add AMD Infinity Storage (AIS) support" Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_uio.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/kcl/kcl_uio.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7c1d32b57bb2f..f84f71ab7f7f3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -153,5 +153,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_uio.h b/include/kcl/kcl_uio.h new file mode 100644 index 0000000000000..79c013014604f --- /dev/null +++ b/include/kcl/kcl_uio.h @@ -0,0 +1,11 @@ +#ifndef _KCL_UIO_H_ +#define _KCL_UIO_H_ + +#include + +#ifndef ITER_SOURCE +#define ITER_SOURCE 1 // == WRITE +#define ITER_DEST 0 // == READ +#endif + +#endif From 76e28d1fefdf65ef230dd1cd0b2be7e2d37450ab Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 10 Sep 2025 14:14:44 +0800 Subject: [PATCH 1916/2653] drm/amdkcl: test whether vmemdup_array_user() exist It's caused by the commit: 93b0be48 "drm/amdgpu: Use vmemdup_array_user in amdgpu_bo_create_list_entry_array" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- .../gpu/drm/amd/dkms/m4/vmemdup_array_user.m4 | 16 +++++++ include/kcl/kcl_string.h | 47 +++++++++++++++++++ 4 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/vmemdup_array_user.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a26a1b4fe8ef5..601b987fc18f7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1262,6 +1262,9 @@ /* vma_lookup() is available */ #define HAVE_VMA_LOOKUP 1 +/* vmemdup_array_user() is available */ +#define HAVE_VMEMDUP_ARRAY_USER 1 + /* vmf_insert_*() are available */ #define HAVE_VMF_INSERT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 44885579aa2e3..194d3cb2b3298 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -293,7 +293,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_AUX_DPCD_PROBE_DISABLED AC_AMDGPU_BLOCK_DEVICE_BD_DEVICE AC_AMDGPU_PAGE_PGMAP - + AC_AMDGPU_VMEMDUP_ARRAY_USER + AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" diff --git a/drivers/gpu/drm/amd/dkms/m4/vmemdup_array_user.m4 b/drivers/gpu/drm/amd/dkms/m4/vmemdup_array_user.m4 new file mode 100644 index 0000000000000..90161018d5bac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vmemdup_array_user.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.6-rc5-1-g313ebe47d755 +dnl # kernel: string.h: add array-wrappers for (v)memdup_user() +dnl # +AC_DEFUN([AC_AMDGPU_VMEMDUP_ARRAY_USER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vmemdup_array_user(NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_VMEMDUP_ARRAY_USER, 1, + [vmemdup_array_user() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_string.h b/include/kcl/kcl_string.h index cb4416f1f99a9..7ba4ffbe1be37 100644 --- a/include/kcl/kcl_string.h +++ b/include/kcl/kcl_string.h @@ -24,4 +24,51 @@ extern ssize_t real_kcl_strscpy(char *, const char *, size_t) __RENAME(strscpy); CONCATENATE(kcl_strscpy, COUNT_ARGS(__VA_ARGS__))(dst, src, __VA_ARGS__) #endif +#ifndef HAVE_VMEMDUP_ARRAY_USER +#ifndef __realloc_size +#define __realloc_size(x, y) +#endif +/** + * memdup_array_user - duplicate array from user space + * @src: source address in user space + * @n: number of array members to copy + * @size: size of one array member + * + * Return: an ERR_PTR() on failure. Result is physically + * contiguous, to be freed by kfree(). + */ +static inline __realloc_size(2, 3) +void *kcl_memdup_array_user(const void __user *src, size_t n, size_t size) +{ + size_t nbytes; + + if (check_mul_overflow(n, size, &nbytes)) + return ERR_PTR(-EOVERFLOW); + + return memdup_user(src, nbytes); +} +#define memdup_array_user kcl_memdup_array_user + +/** + * vmemdup_array_user - duplicate array from user space + * @src: source address in user space + * @n: number of array members to copy + * @size: size of one array member + * + * Return: an ERR_PTR() on failure. Result may be not + * physically contiguous. Use kvfree() to free. + */ +static inline __realloc_size(2, 3) +void *kcl_vmemdup_array_user(const void __user *src, size_t n, size_t size) +{ + size_t nbytes; + + if (check_mul_overflow(n, size, &nbytes)) + return ERR_PTR(-EOVERFLOW); + + return vmemdup_user(src, nbytes); +} +#define vmemdup_array_user kcl_vmemdup_array_user +#endif /* HAVE_VMEMDUP_ARRAY_USER */ + #endif /* _KCL_KCL_STRING_H */ From 5d11431c8f2250c4a8102a22a5c5ebdd06089bdd Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Thu, 12 Jun 2025 11:44:26 +0100 Subject: [PATCH 1917/2653] drm/amdgpu: Use vmemdup_array_user in amdgpu_bo_create_list_entry_array Replace kvmalloc_array() + copy_from_user() with vmemdup_array_user() on the fast path. This shrinks the source code and improves separation between the kernel and userspace slabs. Signed-off-by: Tvrtko Ursulin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 41 +++++++++------------ 1 file changed, 17 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c index 702f6610d0243..66fb37b643882 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c @@ -184,43 +184,36 @@ void amdgpu_bo_list_put(struct amdgpu_bo_list *list) int amdgpu_bo_create_list_entry_array(struct drm_amdgpu_bo_list_in *in, struct drm_amdgpu_bo_list_entry **info_param) { - const void __user *uptr = u64_to_user_ptr(in->bo_info_ptr); const uint32_t info_size = sizeof(struct drm_amdgpu_bo_list_entry); + const void __user *uptr = u64_to_user_ptr(in->bo_info_ptr); + const uint32_t bo_info_size = in->bo_info_size; + const uint32_t bo_number = in->bo_number; struct drm_amdgpu_bo_list_entry *info; - int r; - - info = kvmalloc_array(in->bo_number, info_size, GFP_KERNEL); - if (!info) - return -ENOMEM; /* copy the handle array from userspace to a kernel buffer */ - r = -EFAULT; - if (likely(info_size == in->bo_info_size)) { - unsigned long bytes = in->bo_number * - in->bo_info_size; - - if (copy_from_user(info, uptr, bytes)) - goto error_free; - + if (likely(info_size == bo_info_size)) { + info = vmemdup_array_user(uptr, bo_number, info_size); + if (IS_ERR(info)) + return PTR_ERR(info); } else { - unsigned long bytes = min(in->bo_info_size, info_size); + const uint32_t bytes = min(bo_info_size, info_size); unsigned i; - memset(info, 0, in->bo_number * info_size); - for (i = 0; i < in->bo_number; ++i) { - if (copy_from_user(&info[i], uptr, bytes)) - goto error_free; + info = kvmalloc_array(bo_number, info_size, GFP_KERNEL); + if (!info) + return -ENOMEM; - uptr += in->bo_info_size; + memset(info, 0, bo_number * info_size); + for (i = 0; i < bo_number; ++i, uptr += bo_info_size) { + if (copy_from_user(&info[i], uptr, bytes)) { + kvfree(info); + return -EFAULT; + } } } *info_param = info; return 0; - -error_free: - kvfree(info); - return r; } int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, From dfcdef3d670576098318ffe94ac4b0838daafc25 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Thu, 12 Jun 2025 11:44:27 +0100 Subject: [PATCH 1918/2653] drm/amdgpu: Use memdup_array_user in amdgpu_cs_wait_fences_ioctl Replace kmalloc_array() + copy_from_user() with memdup_array_user(). This shrinks the source code and improves separation between the kernel and userspace slabs. Signed-off-by: Tvrtko Ursulin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index cbafb27aed285..33a7f1d456d51 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1921,30 +1921,21 @@ int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, { struct amdgpu_device *adev = drm_to_adev(dev); union drm_amdgpu_wait_fences *wait = data; - uint32_t fence_count = wait->in.fence_count; - struct drm_amdgpu_fence *fences_user; struct drm_amdgpu_fence *fences; int r; /* Get the fences from userspace */ - fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence), - GFP_KERNEL); - if (fences == NULL) - return -ENOMEM; - - fences_user = u64_to_user_ptr(wait->in.fences); - if (copy_from_user(fences, fences_user, - sizeof(struct drm_amdgpu_fence) * fence_count)) { - r = -EFAULT; - goto err_free_fences; - } + fences = memdup_array_user(u64_to_user_ptr(wait->in.fences), + wait->in.fence_count, + sizeof(struct drm_amdgpu_fence)); + if (IS_ERR(fences)) + return PTR_ERR(fences); if (wait->in.wait_all) r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences); else r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences); -err_free_fences: kfree(fences); return r; From 0be8f92159c71e2a229836f910c0f4f4cbfd5943 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Thu, 12 Jun 2025 11:44:28 +0100 Subject: [PATCH 1919/2653] drm/amdgpu: Use (v)memdup_array_user in amdgpu_cs_pass1 Replace k(v)malloc_array() + copy_from_user() with (v)memdup_array_user(). This shrinks the source code and improves separation between the kernel and userspace slabs. Signed-off-by: Tvrtko Ursulin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 33 ++++++++------------------ 1 file changed, 10 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 33a7f1d456d51..a8c74aed69f63 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -180,25 +180,17 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p, struct amdgpu_fpriv *fpriv = p->filp->driver_priv; unsigned int num_ibs[AMDGPU_CS_GANG_SIZE] = { }; struct amdgpu_vm *vm = &fpriv->vm; - uint64_t *chunk_array_user; uint64_t *chunk_array; uint32_t uf_offset = 0; size_t size; int ret; int i; - chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t), - GFP_KERNEL); - if (!chunk_array) - return -ENOMEM; - - /* get chunks */ - chunk_array_user = u64_to_user_ptr(cs->in.chunks); - if (copy_from_user(chunk_array, chunk_array_user, - sizeof(uint64_t)*cs->in.num_chunks)) { - ret = -EFAULT; - goto free_chunk; - } + chunk_array = memdup_array_user(u64_to_user_ptr(cs->in.chunks), + cs->in.num_chunks, + sizeof(uint64_t)); + if (IS_ERR(chunk_array)) + return PTR_ERR(chunk_array); p->nchunks = cs->in.num_chunks; p->chunks = kvmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk), @@ -211,7 +203,6 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p, for (i = 0; i < p->nchunks; i++) { struct drm_amdgpu_cs_chunk __user *chunk_ptr = NULL; struct drm_amdgpu_cs_chunk user_chunk; - uint32_t __user *cdata; chunk_ptr = u64_to_user_ptr(chunk_array[i]); if (copy_from_user(&user_chunk, chunk_ptr, @@ -224,20 +215,16 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p, p->chunks[i].length_dw = user_chunk.length_dw; size = p->chunks[i].length_dw; - cdata = u64_to_user_ptr(user_chunk.chunk_data); - p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), - GFP_KERNEL); - if (p->chunks[i].kdata == NULL) { - ret = -ENOMEM; + p->chunks[i].kdata = vmemdup_array_user(u64_to_user_ptr(user_chunk.chunk_data), + size, + sizeof(uint32_t)); + if (IS_ERR(p->chunks[i].kdata)) { + ret = PTR_ERR(p->chunks[i].kdata); i--; goto free_partial_kdata; } size *= sizeof(uint32_t); - if (copy_from_user(p->chunks[i].kdata, cdata, size)) { - ret = -EFAULT; - goto free_partial_kdata; - } /* Assume the worst on the following checks */ ret = -EINVAL; From c8cbf5f625948f00b31b2704ae88c4da6b884e5f Mon Sep 17 00:00:00 2001 From: Thorsten Blum Date: Mon, 8 Sep 2025 23:31:56 +0200 Subject: [PATCH 1920/2653] drm/amdkfd: Replace kzalloc + copy_from_user with memdup_user Replace kzalloc() followed by copy_from_user() with memdup_user() to improve and simplify kfd_ioctl_set_cu_mask(). Return early if an error occurs and remove the obsolete 'out' label. No functional changes intended. Signed-off-by: Thorsten Blum Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 4900ccf9c7940..2ddb83ae6f578 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -526,15 +526,10 @@ static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p, cu_mask_size = sizeof(uint32_t) * (max_num_cus/32); } - minfo.cu_mask.ptr = kzalloc(cu_mask_size, GFP_KERNEL); - if (!minfo.cu_mask.ptr) - return -ENOMEM; - - retval = copy_from_user(minfo.cu_mask.ptr, cu_mask_ptr, cu_mask_size); - if (retval) { + minfo.cu_mask.ptr = memdup_user(cu_mask_ptr, cu_mask_size); + if (IS_ERR(minfo.cu_mask.ptr)) { pr_debug("Could not copy CU mask from userspace"); - retval = -EFAULT; - goto out; + return PTR_ERR(minfo.cu_mask.ptr); } mutex_lock(&p->mutex); @@ -543,7 +538,6 @@ static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p, mutex_unlock(&p->mutex); -out: kfree(minfo.cu_mask.ptr); return retval; } From e2f6e2dabe01114378d951a688ddf048cd81fccf Mon Sep 17 00:00:00 2001 From: Thorsten Blum Date: Mon, 8 Sep 2025 23:15:54 +0200 Subject: [PATCH 1921/2653] drm/amdgpu: Replace kzalloc + copy_from_user with memdup_user Replace kzalloc() followed by copy_from_user() with memdup_user() to improve and simplify ta_if_load_debugfs_write() and ta_if_invoke_debugfs_write(). No functional changes intended. Reviewed-by: Tvrtko Ursulin Signed-off-by: Thorsten Blum Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c index 38face981c3e3..6e8aad91bcd30 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c @@ -171,13 +171,9 @@ static ssize_t ta_if_load_debugfs_write(struct file *fp, const char *buf, size_t copy_pos += sizeof(uint32_t); - ta_bin = kzalloc(ta_bin_len, GFP_KERNEL); - if (!ta_bin) - return -ENOMEM; - if (copy_from_user((void *)ta_bin, &buf[copy_pos], ta_bin_len)) { - ret = -EFAULT; - goto err_free_bin; - } + ta_bin = memdup_user(&buf[copy_pos], ta_bin_len); + if (IS_ERR(ta_bin)) + return PTR_ERR(ta_bin); /* Set TA context and functions */ set_ta_context_funcs(psp, ta_type, &context); @@ -327,13 +323,9 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, const char *buf, size return -EFAULT; copy_pos += sizeof(uint32_t); - shared_buf = kzalloc(shared_buf_len, GFP_KERNEL); - if (!shared_buf) - return -ENOMEM; - if (copy_from_user((void *)shared_buf, &buf[copy_pos], shared_buf_len)) { - ret = -EFAULT; - goto err_free_shared_buf; - } + shared_buf = memdup_user(&buf[copy_pos], shared_buf_len); + if (IS_ERR(shared_buf)) + return PTR_ERR(shared_buf); set_ta_context_funcs(psp, ta_type, &context); From 9bbeb956ee26a65946d0bd917b05759c4c48e71e Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 20 Aug 2025 12:48:50 +0530 Subject: [PATCH 1922/2653] drm/amdgpu/ttm: Add New AMDGPU_PL_MMIO_REMAP Placement MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce a kernel-internal TTM placement type AMDGPU_PL_MMIO_REMAP for the HDP flush MMIO remap page Plumbing added: - amdgpu_res_cursor.{first,next}: treat MMIO_REMAP like DOORBELL - amdgpu_ttm_io_mem_reserve(): return BAR bus address + offset for MMIO_REMAP, mark as uncached I/O - amdgpu_ttm_io_mem_pfn(): PFN from register BAR - amdgpu_res_cpu_visible(): visible to CPU - amdgpu_evict_flags()/amdgpu_bo_move(): non-migratable - amdgpu_ttm_tt_pde_flags(): map as SYSTEM - amdgpu_bo_mem_stats_placement(): report AMDGPU_PL_MMIO_REMAP - amdgpu_fdinfo: print “mmioremap” bucket label Cc: Alex Deucher Suggested-by: Christian König Signed-off-by: Srinivasan Shanmugam Reviewed-by: Alex Deucher Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 747c9669069a7..2a81a7dd10f43 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -34,8 +34,8 @@ #define AMDGPU_PL_OA (TTM_PL_PRIV + 2) #define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3) #define AMDGPU_PL_DOORBELL (TTM_PL_PRIV + 4) -#define __AMDGPU_PL_LAST (TTM_PL_PRIV + 4) -#define __AMDGPU_PL_NUM (TTM_PL_PRIV + 5) +#define AMDGPU_PL_MMIO_REMAP (TTM_PL_PRIV + 5) +#define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6) #define AMDGPU_PL_DGMA (TTM_PL_PRIV + 7) #define AMDGPU_PL_DGMA_IMPORT (TTM_PL_PRIV + 8) From 4710e581d43ef2080c3cdd7ce63562c6e11ace11 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 20 Aug 2025 16:17:52 +0530 Subject: [PATCH 1923/2653] drm/amdgpu: Wire up MMIO_REMAP placement and User-visible strings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Wire up the conversions and strings for the new MMIO_REMAP placement: * amdgpu_mem_type_to_domain() maps AMDGPU_PL_MMIO_REMAP -> domain * amdgpu_bo_placement_from_domain() accepts the new domain * amdgpu_bo_mem_stats_placement() and amdgpu_bo_print_info() report it * res cursor supports the new placement * fdinfo prints "mmioremap" for the new placement Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Christian König Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 13 +++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h | 2 ++ 4 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c index ff1e1d8a3a2ff..e6bc424d5debd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c @@ -70,6 +70,7 @@ void amdgpu_show_fdinfo(struct drm_printer *p, struct drm_file *file) [AMDGPU_PL_GWS] = "gws", [AMDGPU_PL_OA] = "oa", [AMDGPU_PL_DOORBELL] = "doorbell", + [AMDGPU_PL_MMIO_REMAP] = "mmioremap", }; unsigned int hw_ip, i; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index ad8d2986aaf7c..fe1d38ec3398a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -171,6 +171,14 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) c++; } + if (domain & AMDGPU_GEM_DOMAIN_MMIO_REMAP) { + places[c].fpfn = 0; + places[c].lpfn = 0; + places[c].mem_type = AMDGPU_PL_MMIO_REMAP; + places[c].flags = 0; + c++; + } + if (domain & AMDGPU_GEM_DOMAIN_GTT) { places[c].fpfn = 0; places[c].lpfn = 0; @@ -1587,6 +1595,8 @@ uint32_t amdgpu_bo_mem_stats_placement(struct amdgpu_bo *bo) return AMDGPU_PL_OA; case AMDGPU_GEM_DOMAIN_DOORBELL: return AMDGPU_PL_DOORBELL; + case AMDGPU_GEM_DOMAIN_MMIO_REMAP: + return AMDGPU_PL_MMIO_REMAP; default: return TTM_PL_SYSTEM; } @@ -1676,6 +1686,9 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) case AMDGPU_PL_DOORBELL: placement = "DOORBELL"; break; + case AMDGPU_PL_MMIO_REMAP: + placement = "MMIO REMAP"; + break; case TTM_PL_SYSTEM: default: placement = "CPU"; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index ccb818fb115c1..6abb7d6e6532e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -179,6 +179,8 @@ static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type) return AMDGPU_GEM_DOMAIN_OA; case AMDGPU_PL_DOORBELL: return AMDGPU_GEM_DOMAIN_DOORBELL; + case AMDGPU_PL_MMIO_REMAP: + return AMDGPU_GEM_DOMAIN_MMIO_REMAP; case AMDGPU_PL_DGMA: return AMDGPU_GEM_DOMAIN_DGMA; case AMDGPU_PL_DGMA_IMPORT: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h index 50fcd86e1033b..be2e56ce1355e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h @@ -91,6 +91,7 @@ static inline void amdgpu_res_first(struct ttm_resource *res, break; case TTM_PL_TT: case AMDGPU_PL_DOORBELL: + case AMDGPU_PL_MMIO_REMAP: node = to_ttm_range_mgr_node(res)->mm_nodes; while (start >= node->size << PAGE_SHIFT) start -= node++->size << PAGE_SHIFT; @@ -153,6 +154,7 @@ static inline void amdgpu_res_next(struct amdgpu_res_cursor *cur, uint64_t size) break; case TTM_PL_TT: case AMDGPU_PL_DOORBELL: + case AMDGPU_PL_MMIO_REMAP: node = cur->node; cur->node = ++node; From a3f2a9af16cd1cb8a26c81b2982d3c1347268bc5 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 20 Aug 2025 16:21:16 +0530 Subject: [PATCH 1924/2653] drm/amdgpu: Implement TTM handling for MMIO_REMAP placement MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement TTM-level behavior for AMDGPU_PL_MMIO_REMAP so it behaves as a CPU-visible IO page: * amdgpu_evict_flags(): mark as unmovable * amdgpu_res_cpu_visible(): consider CPU-visible * amdgpu_bo_move(): use null move when src/dst is MMIO_REMAP * amdgpu_ttm_io_mem_reserve(): program base/is_iomem/caching using the device's mmio_remap_* metadata * amdgpu_ttm_io_mem_pfn(): return PFN for the remapped HDP page * amdgpu_ttm_tt_pde_flags(): set AMDGPU_PTE_SYSTEM for this mem type v2: - Drop HDP-specific comment; keep generic remap (Alex). v3: - Fix indentation in amdgpu_res_cpu_visible (Christian). - Use adev->rmmio_remap.bus_addr for MMIO_REMAP bus/PFN calculations (Alex). v4: - Drop unnecessary (resource_size_t) casts in MMIO_REMAP io-mem paths (Alex) Cc: Christian König Suggested-by: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Alex Deucher Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 81afeda39667d..42752bc357dbb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -130,6 +130,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, case AMDGPU_PL_GWS: case AMDGPU_PL_OA: case AMDGPU_PL_DOORBELL: + case AMDGPU_PL_MMIO_REMAP: placement->num_placement = 0; return; @@ -477,7 +478,8 @@ bool amdgpu_res_cpu_visible(struct amdgpu_device *adev, return false; if (res->mem_type == TTM_PL_SYSTEM || res->mem_type == TTM_PL_TT || - res->mem_type == AMDGPU_PL_PREEMPT || res->mem_type == AMDGPU_PL_DOORBELL) + res->mem_type == AMDGPU_PL_PREEMPT || res->mem_type == AMDGPU_PL_DOORBELL || + res->mem_type == AMDGPU_PL_MMIO_REMAP) return true; if (res->mem_type != TTM_PL_VRAM) @@ -573,10 +575,12 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, old_mem->mem_type == AMDGPU_PL_GWS || old_mem->mem_type == AMDGPU_PL_OA || old_mem->mem_type == AMDGPU_PL_DOORBELL || + old_mem->mem_type == AMDGPU_PL_MMIO_REMAP || new_mem->mem_type == AMDGPU_PL_GDS || new_mem->mem_type == AMDGPU_PL_GWS || new_mem->mem_type == AMDGPU_PL_OA || - new_mem->mem_type == AMDGPU_PL_DOORBELL) { + new_mem->mem_type == AMDGPU_PL_DOORBELL || + new_mem->mem_type == AMDGPU_PL_MMIO_REMAP) { /* Nothing to save here */ amdgpu_bo_move_notify(bo, evict, new_mem); ttm_bo_move_null(bo, new_mem); @@ -667,6 +671,12 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, mem->bus.is_iomem = true; mem->bus.caching = ttm_uncached; break; + case AMDGPU_PL_MMIO_REMAP: + mem->bus.offset = mem->start << PAGE_SHIFT; + mem->bus.offset += adev->rmmio_remap.bus_addr; + mem->bus.is_iomem = true; + mem->bus.caching = ttm_uncached; + break; case AMDGPU_PL_DGMA_IMPORT: { struct amdgpu_bo *abo; @@ -678,6 +688,7 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, mem->bus.caching = ttm_write_combined; break; } + default: return -EINVAL; } @@ -699,6 +710,8 @@ static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, if (bo->resource->mem_type == AMDGPU_PL_DOORBELL) return ((uint64_t)(adev->doorbell.base + cursor.start)) >> PAGE_SHIFT; + else if (bo->resource->mem_type == AMDGPU_PL_MMIO_REMAP) + return ((uint64_t)(adev->rmmio_remap.bus_addr + cursor.start)) >> PAGE_SHIFT; return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; } @@ -1655,7 +1668,8 @@ uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) if (mem && (mem->mem_type == TTM_PL_TT || mem->mem_type == AMDGPU_PL_DOORBELL || - mem->mem_type == AMDGPU_PL_PREEMPT)) { + mem->mem_type == AMDGPU_PL_PREEMPT || + mem->mem_type == AMDGPU_PL_MMIO_REMAP)) { flags |= AMDGPU_PTE_SYSTEM; if (ttm->caching == ttm_cached) From 7407922f77810f740ad375e866096a04e9414c33 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 20 Aug 2025 16:39:38 +0530 Subject: [PATCH 1925/2653] drm/amdgpu/ttm: Initialize AMDGPU_PL_MMIO_REMAP Heap MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a one-page TTM range manager for AMDGPU_PL_MMIO_REMAP via amdgpu_ttm_init_on_chip(). This only registers the placement with TTM; no BO is allocated in this patch. The singleton 4K remap BO is created and freed in the following patch. This split follows to separate heap bring-up from BO allocation. Cc: Christian König Suggested-by: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Alex Deucher Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 42752bc357dbb..f941e2317c56c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2439,6 +2439,13 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) return r; } + /* Initialize MMIO-remap pool (single page 4K) */ + r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_MMIO_REMAP, 1); + if (r) { + dev_err(adev->dev, "Failed initializing MMIO-remap heap.\n"); + return r; + } + /* Initialize preemptible memory pool */ r = amdgpu_preempt_mgr_init(adev); if (r) { @@ -2501,6 +2508,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) } amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL, &adev->mman.sdma_access_ptr); + amdgpu_ttm_fw_reserve_vram_fini(adev); amdgpu_ttm_drv_reserve_vram_fini(adev); @@ -2524,6 +2532,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DOORBELL); + ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_MMIO_REMAP); ttm_device_fini(&adev->mman.bdev); adev->mman.initialized = false; dev_info(adev->dev, "amdgpu: ttm finalized\n"); From 8164d69a0dcbf37a2102427ef75d270d10239832 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Tue, 9 Sep 2025 10:10:40 +0800 Subject: [PATCH 1926/2653] drm/amd/pm: make smu_set_temp_funcs() smu specific for smu v13.0.6 move smu_set_temp_funcs() into smu_v13.0.6 ppt.c file to keep same code layer in amdgpu_smu.c. (only set_ppt func in amdgpu_smu.c) Signed-off-by: Yang Wang Reviewed-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 - drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 12 +++++++----- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 1 - 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 4698f5a785920..1d5f9466b3956 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -766,7 +766,6 @@ static int smu_set_funcs(struct amdgpu_device *adev) case IP_VERSION(13, 0, 14): case IP_VERSION(13, 0, 12): smu_v13_0_6_set_ppt_funcs(smu); - smu_v13_0_6_set_temp_funcs(smu); /* Enable pp_od_clk_voltage node */ smu->od_enabled = true; break; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index bc09867f87d5a..1cb8089063ee9 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -4014,6 +4014,12 @@ static const struct aca_smu_funcs smu_v13_0_6_aca_smu_funcs = { .parse_error_code = aca_smu_parse_error_code, }; +static void smu_v13_0_6_set_temp_funcs(struct smu_context *smu) +{ + smu->smu_temp.temp_funcs = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) + == IP_VERSION(13, 0, 12)) ? &smu_v13_0_12_temp_funcs : NULL; +} + static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { /* init dpm */ .get_allowed_feature_mask = smu_v13_0_6_get_allowed_feature_mask, @@ -4089,12 +4095,8 @@ void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu) smu->smc_driver_if_version = SMU13_0_6_DRIVER_IF_VERSION; smu->smc_fw_caps |= SMU_FW_CAP_RAS_PRI; smu_v13_0_set_smu_mailbox_registers(smu); + smu_v13_0_6_set_temp_funcs(smu); amdgpu_mca_smu_init_funcs(smu->adev, &smu_v13_0_6_mca_smu_funcs); amdgpu_aca_set_smu_funcs(smu->adev, &smu_v13_0_6_aca_smu_funcs); } -void smu_v13_0_6_set_temp_funcs(struct smu_context *smu) -{ - smu->smu_temp.temp_funcs = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) - == IP_VERSION(13, 0, 12)) ? &smu_v13_0_12_temp_funcs : NULL; -} diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h index aae9a546a67e8..4652fcd5e0683 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h @@ -74,7 +74,6 @@ enum smu_v13_0_6_caps { }; extern void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu); -extern void smu_v13_0_6_set_temp_funcs(struct smu_context *smu); bool smu_v13_0_6_cap_supported(struct smu_context *smu, enum smu_v13_0_6_caps cap); int smu_v13_0_6_get_static_metrics_table(struct smu_context *smu); int smu_v13_0_6_get_metrics_table(struct smu_context *smu, void *metrics_table, From 4e1b4dd027c6c055a14a8199eb5a229cd0fe2c06 Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Mon, 23 Jun 2025 16:29:38 +0800 Subject: [PATCH 1927/2653] drm/amdgpu: validate userq buffer virtual address and size It needs to validate the userq object virtual address to determine whether it is residented in a valid vm mapping. Signed-off-by: Prike Liang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 40 ++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 2 ++ drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 16 +++++++++ 3 files changed, 58 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index aa5531bfeb574..5661bb678c301 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -44,6 +44,38 @@ u32 amdgpu_userq_get_supported_ip_mask(struct amdgpu_device *adev) return userq_ip_mask; } +int amdgpu_userq_input_va_validate(struct amdgpu_vm *vm, u64 addr, + u64 expected_size) +{ + struct amdgpu_bo_va_mapping *va_map; + u64 user_addr; + u64 size; + int r = 0; + + user_addr = (addr & AMDGPU_GMC_HOLE_MASK) >> AMDGPU_GPU_PAGE_SHIFT; + size = expected_size >> AMDGPU_GPU_PAGE_SHIFT; + + r = amdgpu_bo_reserve(vm->root.bo, false); + if (r) + return r; + + va_map = amdgpu_vm_bo_lookup_mapping(vm, user_addr); + if (!va_map) { + r = -EINVAL; + goto out_err; + } + /* Only validate the userq whether resident in the VM mapping range */ + if (user_addr >= va_map->start && + va_map->last - user_addr + 1 >= size) { + amdgpu_bo_unreserve(vm->root.bo); + return 0; + } + +out_err: + amdgpu_bo_unreserve(vm->root.bo); + return r; +} + static int amdgpu_userq_unmap_helper(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_queue *queue) @@ -428,6 +460,14 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) r = -ENOMEM; goto unlock; } + + /* Validate the userq virtual address.*/ + if (amdgpu_userq_input_va_validate(&fpriv->vm, args->in.queue_va, args->in.queue_size) || + amdgpu_userq_input_va_validate(&fpriv->vm, args->in.rptr_va, AMDGPU_GPU_PAGE_SIZE) || + amdgpu_userq_input_va_validate(&fpriv->vm, args->in.wptr_va, AMDGPU_GPU_PAGE_SIZE)) { + kfree(queue); + goto unlock; + } queue->doorbell_handle = args->in.doorbell_handle; queue->queue_type = args->in.ip_type; queue->vm = &fpriv->vm; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index bc683763627fc..70895c10276d3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -142,4 +142,6 @@ int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev, int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev, u32 idx); +int amdgpu_userq_input_va_validate(struct amdgpu_vm *vm, u64 addr, + u64 expected_size); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index 66467f41294c1..3a4fd6de08ce7 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -254,6 +254,7 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_mqd *mqd_hw_default = &adev->mqds[queue->queue_type]; struct drm_amdgpu_userq_in *mqd_user = args_in; struct amdgpu_mqd_prop *userq_props; + struct amdgpu_gfx_shadow_info shadow_info; int r; /* Structure to initialize MQD for userqueue using generic MQD init function */ @@ -279,6 +280,8 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, userq_props->doorbell_index = queue->doorbell_index; userq_props->fence_address = queue->fence_drv->gpu_addr; + if (adev->gfx.funcs->get_gfx_shadow_info) + adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow_info, true); if (queue->queue_type == AMDGPU_HW_IP_COMPUTE) { struct drm_amdgpu_userq_mqd_compute_gfx11 *compute_mqd; @@ -295,6 +298,10 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, goto free_mqd; } + if (amdgpu_userq_input_va_validate(queue->vm, compute_mqd->eop_va, + max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE))) + goto free_mqd; + userq_props->eop_gpu_addr = compute_mqd->eop_va; userq_props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL; userq_props->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM; @@ -322,6 +329,11 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, userq_props->csa_addr = mqd_gfx_v11->csa_va; userq_props->tmz_queue = mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; + + if (amdgpu_userq_input_va_validate(queue->vm, mqd_gfx_v11->shadow_va, + shadow_info.shadow_size)) + goto free_mqd; + kfree(mqd_gfx_v11); } else if (queue->queue_type == AMDGPU_HW_IP_DMA) { struct drm_amdgpu_userq_mqd_sdma_gfx11 *mqd_sdma_v11; @@ -339,6 +351,10 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, goto free_mqd; } + if (amdgpu_userq_input_va_validate(queue->vm, mqd_sdma_v11->csa_va, + shadow_info.csa_size)) + goto free_mqd; + userq_props->csa_addr = mqd_sdma_v11->csa_va; kfree(mqd_sdma_v11); } From 8a50a73b7f6b86abf0954f1007c5c894791bc3cf Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Thu, 28 Aug 2025 19:18:49 +0530 Subject: [PATCH 1928/2653] drm/amdgpu/ttm: Allocate/Free 4K MMIO_REMAP Singleton MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add mmio_remap bookkeeping to amdgpu_device and introduce amdgpu_ttm_mmio_remap_bo_init()/fini() to manage a kernel-owned, one-page (4K) BO in AMDGPU_GEM_DOMAIN_MMIO_REMAP. Bookkeeping: - adev->rmmio_remap.bo : kernel-owned singleton BO The BO is allocated during TTM init when a remap bus address is available (adev->rmmio_remap.bus_addr) and PAGE_SIZE <= AMDGPU_GPU_PAGE_SIZE (4K), and freed during TTM fini. v2: - Check mmio_remap bus address (adev->rmmio_remap.bus_addr) instead of rmmio_base. (Alex) - Skip quietly if PAGE_SIZE > AMDGPU_GPU_PAGE_SIZE or no bus address (no warn). (Alex) - Use `amdgpu_bo_create()` (not *_kernel) - Only with this The object is stored in adev->mmio_remap.bo and will later be exposed to userspace via a GEM handle. (Christian) v3: - Remove obvious comment before amdgpu_ttm_mmio_remap_bo_fini() call. (Alex) v4: - Squash bookkeeping into this patch (Christian) Suggested-by: Christian König Suggested-by: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 59 +++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 66fefd2e1a0fa..c715cf5972b3e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -761,6 +761,7 @@ typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, u struct amdgpu_mmio_remap { u32 reg_offset; resource_size_t bus_addr; + struct amdgpu_bo *bo; }; /* Define the HW IP blocks will be used in driver , add more if necessary */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index f941e2317c56c..8a29165344f43 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2256,6 +2256,59 @@ static void amdgpu_ttm_pools_fini(struct amdgpu_device *adev) adev->mman.ttm_pools = NULL; } +/** + * amdgpu_ttm_mmio_remap_bo_init - Allocate the singleton 4K MMIO_REMAP BO + * @adev: amdgpu device + * + * Allocates a one-page (4K) GEM BO in AMDGPU_GEM_DOMAIN_MMIO_REMAP when the + * hardware exposes a remap base (adev->rmmio_remap.bus_addr) and the host + * PAGE_SIZE is <= AMDGPU_GPU_PAGE_SIZE (4K). The BO is created as a regular + * GEM object (amdgpu_bo_create). + * + * Return: + * * 0 on success or intentional skip (feature not present/unsupported) + * * negative errno on allocation failure + */ +static int amdgpu_ttm_mmio_remap_bo_init(struct amdgpu_device *adev) +{ + struct amdgpu_bo_param bp; + int r; + + /* Skip if HW doesn't expose remap, or if PAGE_SIZE > AMDGPU_GPU_PAGE_SIZE (4K). */ + if (!adev->rmmio_remap.bus_addr || PAGE_SIZE > AMDGPU_GPU_PAGE_SIZE) + return 0; + + memset(&bp, 0, sizeof(bp)); + + /* Create exactly one GEM BO in the MMIO_REMAP domain. */ + bp.type = ttm_bo_type_device; /* userspace-mappable GEM */ + bp.size = AMDGPU_GPU_PAGE_SIZE; /* 4K */ + bp.byte_align = AMDGPU_GPU_PAGE_SIZE; + bp.domain = AMDGPU_GEM_DOMAIN_MMIO_REMAP; + bp.flags = 0; + bp.resv = NULL; + bp.bo_ptr_size = sizeof(struct amdgpu_bo); + + r = amdgpu_bo_create(adev, &bp, &adev->rmmio_remap.bo); + if (r) + return r; + + return 0; +} + +/** + * amdgpu_ttm_mmio_remap_bo_fini - Free the singleton MMIO_REMAP BO + * @adev: amdgpu device + * + * Frees the kernel-owned MMIO_REMAP BO if it was allocated by + * amdgpu_ttm_mmio_remap_bo_init(). + */ +static void amdgpu_ttm_mmio_remap_bo_fini(struct amdgpu_device *adev) +{ + amdgpu_bo_unref(&adev->rmmio_remap.bo); + adev->rmmio_remap.bo = NULL; +} + /* * amdgpu_ttm_init - Init the memory management (ttm) as well as various * gtt/vram related fields. @@ -2446,6 +2499,11 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) return r; } + /* Allocate the singleton MMIO_REMAP BO (4K) if supported */ + r = amdgpu_ttm_mmio_remap_bo_init(adev); + if (r) + return r; + /* Initialize preemptible memory pool */ r = amdgpu_preempt_mgr_init(adev); if (r) { @@ -2509,6 +2567,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL, &adev->mman.sdma_access_ptr); + amdgpu_ttm_mmio_remap_bo_fini(adev); amdgpu_ttm_fw_reserve_vram_fini(adev); amdgpu_ttm_drv_reserve_vram_fini(adev); From 7ad609ee564f7f478b232197d4852268aa7ea61a Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 2 Sep 2025 11:37:37 +0530 Subject: [PATCH 1929/2653] drm/amdgpu: Release hive reference properly xgmi hive reference is taken on function entry, but not released correctly for all paths. Use __free() to release reference properly. Signed-off-by: Lijo Lazar Reviewed-by: Ce Sun --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++---- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h | 4 ++++ 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 312ce41c1440f..d8acd623272f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6999,7 +6999,8 @@ pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_sta { struct drm_device *dev = pci_get_drvdata(pdev); struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); + struct amdgpu_hive_info *hive __free(xgmi_put_hive) = + amdgpu_get_xgmi_hive(adev); struct amdgpu_reset_context reset_context; struct list_head device_list; @@ -7038,10 +7039,8 @@ pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_sta amdgpu_device_recovery_get_reset_lock(adev, &device_list); amdgpu_device_halt_activities(adev, NULL, &reset_context, &device_list, hive, false); - if (hive) { + if (hive) mutex_unlock(&hive->hive_lock); - amdgpu_put_xgmi_hive(hive); - } return PCI_ERS_RESULT_NEED_RESET; case pci_channel_io_perm_failure: /* Permanent error, prepare for device removal */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h index bba0b26fee8f1..5f36aff17e79e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h @@ -126,4 +126,8 @@ uint32_t amdgpu_xgmi_get_max_bandwidth(struct amdgpu_device *adev); void amgpu_xgmi_set_max_speed_width(struct amdgpu_device *adev, uint16_t max_speed, uint8_t max_width); + +/* Cleanup macro for use with __free(xgmi_put_hive) */ +DEFINE_FREE(xgmi_put_hive, struct amdgpu_hive_info *, if (_T) amdgpu_put_xgmi_hive(_T)) + #endif From f1a7f175b19e05dc0bbbfaca912a4d7744284a5a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Tue, 9 Sep 2025 16:17:50 +0200 Subject: [PATCH 1930/2653] drm/amd/display: Add pixel_clock to amd_pp_display_configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds the pixel_clock field to the display config struct so that power management (DPM) can use it. We currently don't have a proper bandwidth calculation on old GPUs with DCE 6-10 because dce_calcs only supports DCE 11+. So the power management (DPM) on these GPUs may need to make ad-hoc decisions for display based on the pixel clock. Also rename sym_clock to pixel_clock in dm_pp_single_disp_config to avoid confusion with other code where the sym_clock refers to the DisplayPort symbol clock. Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 1 + drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 2 +- drivers/gpu/drm/amd/display/dc/dm_services_types.h | 2 +- drivers/gpu/drm/amd/include/dm_pp_interface.h | 1 + 4 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c index e5771f490f2e3..11b2ea6edf953 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c @@ -98,6 +98,7 @@ bool dm_pp_apply_display_requirements( const struct dm_pp_single_disp_config *dc_cfg = &pp_display_cfg->disp_configs[i]; adev->pm.pm_display_cfg.displays[i].controller_id = dc_cfg->pipe_idx + 1; + adev->pm.pm_display_cfg.displays[i].pixel_clock = dc_cfg->pixel_clock; } amdgpu_dpm_display_configuration_change(adev, &adev->pm.pm_display_cfg); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c index 13cf415e38e50..d50b9440210e4 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c @@ -164,7 +164,7 @@ void dce110_fill_display_configs( stream->link->cur_link_settings.link_rate; cfg->link_settings.link_spread = stream->link->cur_link_settings.link_spread; - cfg->sym_clock = stream->phy_pix_clk; + cfg->pixel_clock = stream->phy_pix_clk; /* Round v_refresh*/ cfg->v_refresh = stream->timing.pix_clk_100hz * 100; cfg->v_refresh /= stream->timing.h_total; diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h index bf63da266a18c..3b093b8699abd 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h @@ -127,7 +127,7 @@ struct dm_pp_single_disp_config { uint32_t src_height; uint32_t src_width; uint32_t v_refresh; - uint32_t sym_clock; /* HDMI only */ + uint32_t pixel_clock; /* Pixel clock in KHz (for HDMI only: normalized) */ struct dc_link_settings link_settings; /* DP only */ }; diff --git a/drivers/gpu/drm/amd/include/dm_pp_interface.h b/drivers/gpu/drm/amd/include/dm_pp_interface.h index acd1cef61b7c5..349544504c93c 100644 --- a/drivers/gpu/drm/amd/include/dm_pp_interface.h +++ b/drivers/gpu/drm/amd/include/dm_pp_interface.h @@ -65,6 +65,7 @@ struct single_display_configuration { uint32_t view_resolution_cy; enum amd_pp_display_config_type displayconfigtype; uint32_t vertical_refresh; /* for active display */ + uint32_t pixel_clock; /* Pixel clock in KHz (for HDMI only: normalized) */ }; #define MAX_NUM_DISPLAY 32 From b07154e9bcca99e5ef6ae2c338575c4f408b288d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Tue, 9 Sep 2025 16:17:51 +0200 Subject: [PATCH 1931/2653] drm/amd/pm: Use pm_display_cfg in legacy DPM (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit is necessary for DC to function well with chips that use the legacy power management code, ie. SI and KV. Communicate display information from DC to the legacy PM code. Currently DC uses pm_display_cfg to communicate power management requirements from the display code to the DPM code. However, the legacy (non-DC) code path used different fields and therefore could not take into account anything from DC. Change the legacy display code to fill the same pm_display_cfg struct as DC and use the same in the legacy DPM code. To ease review and reduce churn, this commit does not yet delete the now unneeded code, that is done in the next commit. v2: Rebase. Fix single_display in amdgpu_dpm_pick_power_state. Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c | 67 +++++++++++++++++++ .../gpu/drm/amd/pm/inc/amdgpu_dpm_internal.h | 2 + drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 4 +- .../gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c | 5 +- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 65 ++++++------------ .../gpu/drm/amd/pm/powerplay/amd_powerplay.c | 11 +-- 6 files changed, 97 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c index 2d2d2d5e67634..9ef965e4a92ed 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c @@ -100,3 +100,70 @@ u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev) return vrefresh; } + +void amdgpu_dpm_get_display_cfg(struct amdgpu_device *adev) +{ + struct drm_device *ddev = adev_to_drm(adev); + struct amd_pp_display_configuration *cfg = &adev->pm.pm_display_cfg; + struct single_display_configuration *display_cfg; + struct drm_crtc *crtc; + struct amdgpu_crtc *amdgpu_crtc; + struct amdgpu_connector *conn; + int num_crtcs = 0; + int vrefresh; + u32 vblank_in_pixels, vblank_time_us; + + cfg->min_vblank_time = 0xffffffff; /* if the displays are off, vblank time is max */ + + if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { + list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { + amdgpu_crtc = to_amdgpu_crtc(crtc); + + /* The array should only contain active displays. */ + if (!amdgpu_crtc->enabled) + continue; + + conn = to_amdgpu_connector(amdgpu_crtc->connector); + display_cfg = &adev->pm.pm_display_cfg.displays[num_crtcs++]; + + if (amdgpu_crtc->hw_mode.clock) { + vrefresh = drm_mode_vrefresh(&amdgpu_crtc->hw_mode); + + vblank_in_pixels = + amdgpu_crtc->hw_mode.crtc_htotal * + (amdgpu_crtc->hw_mode.crtc_vblank_end - + amdgpu_crtc->hw_mode.crtc_vdisplay + + (amdgpu_crtc->v_border * 2)); + + vblank_time_us = + vblank_in_pixels * 1000 / amdgpu_crtc->hw_mode.clock; + + /* The legacy (non-DC) code has issues with mclk switching + * with refresh rates over 120 Hz. Disable mclk switching. + */ + if (vrefresh > 120) + vblank_time_us = 0; + + /* Find minimum vblank time. */ + if (vblank_time_us < cfg->min_vblank_time) + cfg->min_vblank_time = vblank_time_us; + + /* Find vertical refresh rate of first active display. */ + if (!cfg->vrefresh) + cfg->vrefresh = vrefresh; + } + + if (amdgpu_crtc->crtc_id < cfg->crtc_index) { + /* Find first active CRTC and its line time. */ + cfg->crtc_index = amdgpu_crtc->crtc_id; + cfg->line_time_in_us = amdgpu_crtc->line_time; + } + + display_cfg->controller_id = amdgpu_crtc->crtc_id; + display_cfg->pixel_clock = conn->pixelclock_for_modeset; + } + } + + cfg->display_clk = adev->clock.default_dispclk; + cfg->num_display = num_crtcs; +} diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm_internal.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm_internal.h index 5c2a89f0d5d5d..8be11510cd923 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm_internal.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm_internal.h @@ -29,4 +29,6 @@ u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev); u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev); +void amdgpu_dpm_get_display_cfg(struct amdgpu_device *adev); + #endif diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c index 307ebf7e32267..33eb85dd68e9c 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c @@ -2299,7 +2299,7 @@ static void kv_apply_state_adjust_rules(struct amdgpu_device *adev, if (pi->sys_info.nb_dpm_enable) { force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) || - pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) || + pi->video_start || (adev->pm.pm_display_cfg.num_display >= 3) || pi->disable_nb_ps3_in_battery; ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3; ps->dpm0_pg_nb_ps_hi = 0x2; @@ -2358,7 +2358,7 @@ static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev) return 0; force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) || - (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); + (adev->pm.pm_display_cfg.num_display >= 3) || pi->video_start); if (force_high) { for (i = pi->lowest_valid; i <= pi->highest_valid; i++) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c index 52dbf6d0469df..6ebe3d0f5b877 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c @@ -771,7 +771,7 @@ static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev, int i; struct amdgpu_ps *ps; u32 ui_class; - bool single_display = adev->pm.dpm.new_active_crtc_count < 2; + bool single_display = adev->pm.pm_display_cfg.num_display < 2; /* check if the vblank period is too short to adjust the mclk */ if (single_display && adev->powerplay.pp_funcs->vblank_too_short) { @@ -967,7 +967,8 @@ void amdgpu_legacy_dpm_compute_clocks(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - amdgpu_dpm_get_active_displays(adev); + if (!adev->dc_enabled) + amdgpu_dpm_get_display_cfg(adev); amdgpu_dpm_change_power_state_locked(adev); } diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 6595a611ce6e5..cf9932e68055f 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -3081,7 +3081,7 @@ static int si_get_vce_clock_voltage(struct amdgpu_device *adev, static bool si_dpm_vblank_too_short(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); + u32 vblank_time = adev->pm.pm_display_cfg.min_vblank_time; /* we never hit the non-gddr5 limit so disable it */ u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0; @@ -3447,9 +3447,10 @@ static void rv770_get_engine_memory_ss(struct amdgpu_device *adev) static void si_apply_state_adjust_rules(struct amdgpu_device *adev, struct amdgpu_ps *rps) { + const struct amd_pp_display_configuration *display_cfg = + &adev->pm.pm_display_cfg; struct si_ps *ps = si_get_ps(rps); struct amdgpu_clock_and_voltage_limits *max_limits; - struct amdgpu_connector *conn; bool disable_mclk_switching = false; bool disable_sclk_switching = false; u32 mclk, sclk; @@ -3488,14 +3489,9 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev, * For example, 4K 60Hz and 1080p 144Hz fall into this category. * Find number of such displays connected. */ - for (i = 0; i < adev->mode_info.num_crtc; i++) { - if (!(adev->pm.dpm.new_active_crtcs & (1 << i)) || - !adev->mode_info.crtcs[i]->enabled) - continue; - - conn = to_amdgpu_connector(adev->mode_info.crtcs[i]->connector); - - if (conn->pixelclock_for_modeset > 297000) + for (i = 0; i < display_cfg->num_display; i++) { + /* The array only contains active displays. */ + if (display_cfg->displays[i].pixel_clock > 297000) high_pixelclock_count++; } @@ -3523,7 +3519,7 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev, rps->ecclk = 0; } - if ((adev->pm.dpm.new_active_crtc_count > 1) || + if ((adev->pm.pm_display_cfg.num_display > 1) || si_dpm_vblank_too_short(adev)) disable_mclk_switching = true; @@ -3671,7 +3667,7 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev, ps->performance_levels[i].mclk, max_limits->vddc, &ps->performance_levels[i].vddc); btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, - adev->clock.current_dispclk, + display_cfg->display_clk, max_limits->vddc, &ps->performance_levels[i].vddc); } @@ -4196,16 +4192,16 @@ static void si_program_ds_registers(struct amdgpu_device *adev) static void si_program_display_gap(struct amdgpu_device *adev) { + const struct amd_pp_display_configuration *cfg = &adev->pm.pm_display_cfg; u32 tmp, pipe; - int i; tmp = RREG32(mmCG_DISPLAY_GAP_CNTL) & ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK); - if (adev->pm.dpm.new_active_crtc_count > 0) + if (cfg->num_display > 0) tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT; else tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT; - if (adev->pm.dpm.new_active_crtc_count > 1) + if (cfg->num_display > 1) tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT; else tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT; @@ -4215,17 +4211,8 @@ static void si_program_display_gap(struct amdgpu_device *adev) tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; - if ((adev->pm.dpm.new_active_crtc_count > 0) && - (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) { - /* find the first active crtc */ - for (i = 0; i < adev->mode_info.num_crtc; i++) { - if (adev->pm.dpm.new_active_crtcs & (1 << i)) - break; - } - if (i == adev->mode_info.num_crtc) - pipe = 0; - else - pipe = i; + if (cfg->num_display > 0 && pipe != cfg->crtc_index) { + pipe = cfg->crtc_index; tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; tmp |= DCCG_DISP1_SLOW_SELECT(pipe); @@ -4236,7 +4223,7 @@ static void si_program_display_gap(struct amdgpu_device *adev) * This can be a problem on PowerXpress systems or if you want to use the card * for offscreen rendering or compute if there are no crtcs enabled. */ - si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0); + si_notify_smc_display_change(adev, cfg->num_display > 0); } static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable) @@ -5545,7 +5532,7 @@ static int si_convert_power_level_to_smc(struct amdgpu_device *adev, (pl->mclk <= pi->mclk_stutter_mode_threshold) && !eg_pi->uvd_enabled && (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) && - (adev->pm.dpm.new_active_crtc_count <= 2)) { + (adev->pm.pm_display_cfg.num_display <= 2)) { level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; } @@ -5694,7 +5681,7 @@ static bool si_is_state_ulv_compatible(struct amdgpu_device *adev, /* XXX validate against display requirements! */ for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { - if (adev->clock.current_dispclk <= + if (adev->pm.pm_display_cfg.display_clk <= adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { if (ulv->pl.vddc < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) @@ -5848,30 +5835,22 @@ static int si_upload_ulv_state(struct amdgpu_device *adev) static int si_upload_smc_data(struct amdgpu_device *adev) { - struct amdgpu_crtc *amdgpu_crtc = NULL; - int i; + const struct amd_pp_display_configuration *cfg = &adev->pm.pm_display_cfg; u32 crtc_index = 0; u32 mclk_change_block_cp_min = 0; u32 mclk_change_block_cp_max = 0; - for (i = 0; i < adev->mode_info.num_crtc; i++) { - if (adev->pm.dpm.new_active_crtcs & (1 << i)) { - amdgpu_crtc = adev->mode_info.crtcs[i]; - break; - } - } - /* When a display is plugged in, program these so that the SMC * performs MCLK switching when it doesn't cause flickering. * When no display is plugged in, there is no need to restrict * MCLK switching, so program them to zero. */ - if (adev->pm.dpm.new_active_crtc_count && amdgpu_crtc) { - crtc_index = amdgpu_crtc->crtc_id; + if (cfg->num_display) { + crtc_index = cfg->crtc_index; - if (amdgpu_crtc->line_time) { - mclk_change_block_cp_min = 200 / amdgpu_crtc->line_time; - mclk_change_block_cp_max = 100 / amdgpu_crtc->line_time; + if (cfg->line_time_in_us) { + mclk_change_block_cp_min = 200 / cfg->line_time_in_us; + mclk_change_block_cp_max = 100 / cfg->line_time_in_us; } } diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index b48a031cbba08..554492dfa3c00 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -1554,16 +1554,7 @@ static void pp_pm_compute_clocks(void *handle) struct amdgpu_device *adev = hwmgr->adev; if (!adev->dc_enabled) { - amdgpu_dpm_get_active_displays(adev); - adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count; - adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev); - adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev); - /* we have issues with mclk switching with - * refresh rates over 120 hz on the non-DC code. - */ - if (adev->pm.pm_display_cfg.vrefresh > 120) - adev->pm.pm_display_cfg.min_vblank_time = 0; - + amdgpu_dpm_get_display_cfg(adev); pp_display_configuration_change(handle, &adev->pm.pm_display_cfg); } From 12c861238b16e12ff5bd8df210f972a6180eedbd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Tue, 9 Sep 2025 16:17:52 +0200 Subject: [PATCH 1932/2653] drm/amd/pm: Remove unneeded legacy DPM related code. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This code isn't needed anymore as we collect the same information into pm_display_cfg instead. Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 1 - drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c | 74 ------------------- drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 4 - .../gpu/drm/amd/pm/inc/amdgpu_dpm_internal.h | 6 -- .../gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c | 3 - 6 files changed, 89 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index c715cf5972b3e..7e5dad3b9e93a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -436,7 +436,6 @@ struct amdgpu_clock { uint32_t default_mclk; uint32_t default_sclk; uint32_t default_dispclk; - uint32_t current_dispclk; uint32_t dp_extclk; uint32_t max_pixel_clock; }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index f137194b5db21..00de8677cf278 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -706,7 +706,6 @@ int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev) } adev->clock.dp_extclk = le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); - adev->clock.current_dispclk = adev->clock.default_dispclk; adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); if (adev->clock.max_pixel_clock == 0) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c index 9ef965e4a92ed..b5e9c3ecf7032 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm_internal.c @@ -27,80 +27,6 @@ #include "amdgpu_smu.h" #include "amdgpu_dpm_internal.h" -void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev) -{ - struct drm_device *ddev = adev_to_drm(adev); - struct drm_crtc *crtc; - struct amdgpu_crtc *amdgpu_crtc; - - adev->pm.dpm.new_active_crtcs = 0; - adev->pm.dpm.new_active_crtc_count = 0; - if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { - list_for_each_entry(crtc, - &ddev->mode_config.crtc_list, head) { - amdgpu_crtc = to_amdgpu_crtc(crtc); - if (amdgpu_crtc->enabled) { - adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id); - adev->pm.dpm.new_active_crtc_count++; - } - } - } -} - -u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev) -{ - struct drm_device *dev = adev_to_drm(adev); - struct drm_crtc *crtc; - struct amdgpu_crtc *amdgpu_crtc; - u32 vblank_in_pixels; - u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */ - - if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - amdgpu_crtc = to_amdgpu_crtc(crtc); - if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) { - vblank_in_pixels = - amdgpu_crtc->hw_mode.crtc_htotal * - (amdgpu_crtc->hw_mode.crtc_vblank_end - - amdgpu_crtc->hw_mode.crtc_vdisplay + - (amdgpu_crtc->v_border * 2)); - - vblank_time_us = vblank_in_pixels * 1000 / amdgpu_crtc->hw_mode.clock; - - /* we have issues with mclk switching with - * refresh rates over 120 hz on the non-DC code. - */ - if (drm_mode_vrefresh(&amdgpu_crtc->hw_mode) > 120) - vblank_time_us = 0; - - break; - } - } - } - - return vblank_time_us; -} - -u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev) -{ - struct drm_device *dev = adev_to_drm(adev); - struct drm_crtc *crtc; - struct amdgpu_crtc *amdgpu_crtc; - u32 vrefresh = 0; - - if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - amdgpu_crtc = to_amdgpu_crtc(crtc); - if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) { - vrefresh = drm_mode_vrefresh(&amdgpu_crtc->hw_mode); - break; - } - } - } - - return vrefresh; -} - void amdgpu_dpm_get_display_cfg(struct amdgpu_device *adev) { struct drm_device *ddev = adev_to_drm(adev); diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h index 31c0b6ea041af..cda2d7f77c015 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h @@ -263,10 +263,6 @@ struct amdgpu_dpm { u32 voltage_response_time; u32 backbias_response_time; void *priv; - u32 new_active_crtcs; - int new_active_crtc_count; - u32 current_active_crtcs; - int current_active_crtc_count; struct amdgpu_dpm_dynamic_state dyn_state; struct amdgpu_dpm_fan fan; u32 tdp_limit; diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm_internal.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm_internal.h index 8be11510cd923..cc6d7ba040e98 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm_internal.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm_internal.h @@ -23,12 +23,6 @@ #ifndef __AMDGPU_DPM_INTERNAL_H__ #define __AMDGPU_DPM_INTERNAL_H__ -void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev); - -u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev); - -u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev); - void amdgpu_dpm_get_display_cfg(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c index 6ebe3d0f5b877..c7ed0b4571293 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/legacy_dpm.c @@ -944,9 +944,6 @@ static int amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) amdgpu_dpm_post_set_power_state(adev); - adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; - adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; - if (pp_funcs->force_performance_level) { if (adev->pm.dpm.thermal_active) { enum amd_dpm_forced_level level = adev->pm.dpm.forced_level; From afd7984b0d6c948ba37769f402bffc8da23bed29 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Tue, 9 Sep 2025 16:49:35 +0200 Subject: [PATCH 1933/2653] drm/amdgpu: Fix allocating extra dwords for rings (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename extra_dw to extra_bytes and document what it's for. The value is already used as if it were bytes in vcn_v4_0.c and in amdgpu_ring_init. Just adjust the dword count in jpeg_v1_0.c so that it becomes a byte count. v2: Rename extra_dw to extra_bytes as discussed during review. Fixes: c8c1a1d2ef04 ("drm/amdgpu: define and add extra dword for jpeg ring") Signed-off-by: Timur Kristóf Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 13 ++++++++++++- drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 2 +- 4 files changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 22e69a8f63afb..0137f45c6cd43 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -364,7 +364,8 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, /* Allocate ring buffer */ if (ring->ring_obj == NULL) { - r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE, + r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_bytes, + PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, &ring->ring_obj, &ring->gpu_addr, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 80b85547c810b..4116dfb034999 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -211,7 +211,18 @@ struct amdgpu_ring_funcs { bool support_64bit_ptrs; bool no_user_fence; bool secure_submission_supported; - unsigned extra_dw; + + /** + * @extra_bytes: + * + * Optional extra space in bytes that is added to the ring size + * when allocating the BO that holds the contents of the ring. + * This space isn't used for command submission to the ring, + * but is just there to satisfy some hardware requirements or + * implement workarounds. It's up to the implementation of each + * specific ring to initialize this space. + */ + unsigned extra_bytes; /* ring read/write ptr handling */ u64 (*get_rptr)(struct amdgpu_ring *ring); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c index 9e428e669ada6..b5bb7f4d607c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c @@ -557,7 +557,7 @@ static const struct amdgpu_ring_funcs jpeg_v1_0_decode_ring_vm_funcs = { .nop = PACKET0(0x81ff, 0), .support_64bit_ptrs = false, .no_user_fence = true, - .extra_dw = 64, + .extra_bytes = 256, .get_rptr = jpeg_v1_0_decode_ring_get_rptr, .get_wptr = jpeg_v1_0_decode_ring_get_wptr, .set_wptr = jpeg_v1_0_decode_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 8d3f18b55fc26..3ae666522d570 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -1977,7 +1977,7 @@ static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, - .extra_dw = sizeof(struct amdgpu_vcn_rb_metadata), + .extra_bytes = sizeof(struct amdgpu_vcn_rb_metadata), .get_rptr = vcn_v4_0_unified_ring_get_rptr, .get_wptr = vcn_v4_0_unified_ring_get_wptr, .set_wptr = vcn_v4_0_unified_ring_set_wptr, From da50b790d3d27301e0d4d4d63d94660c907e4b9b Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Tue, 9 Sep 2025 16:49:37 +0200 Subject: [PATCH 1934/2653] drm/amdgpu: Use memset32 for ring clearing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use memset32 instead of open coding it, just because it is a tiny bit nicer. Reviewed-by: Christian König Signed-off-by: Tvrtko Ursulin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 4116dfb034999..b6b6491797761 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -481,10 +481,7 @@ static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring, static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) { - int i = 0; - while (i <= ring->buf_mask) - ring->ring[i++] = ring->funcs->nop; - + memset32(ring->ring, ring->funcs->nop, ring->buf_mask + 1); } static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) From 6543a32e78e0cc52b3cd794be6cfb35508747699 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 11 Sep 2025 14:59:27 +0800 Subject: [PATCH 1935/2653] Revert "drm/amdgpu: Allocate psp fw private buffer in vram" This reverts commit 65d1d1b0f1418509432a520f4f3fcd3da2c334bf. It's caused the Jira ticket: SWDEV-554459, so revert it temporarily. Signed-off-by: Chengjun Yao --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 9e7ea7a11475e..5e6040d901bd3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -506,7 +506,8 @@ static int psp_sw_init(struct amdgpu_ip_block *ip_block) } ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, - AMDGPU_GEM_DOMAIN_VRAM, + (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? + AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, &psp->fw_pri_bo, &psp->fw_pri_mc_addr, &psp->fw_pri_buf); From d080ddcb1d390459a873a6b2d64c337b6b94df31 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 11 Sep 2025 14:59:27 +0800 Subject: [PATCH 1936/2653] Revert "drm/amdgpu: Allocate psp fw private buffer in vram" This reverts commit 65d1d1b0f1418509432a520f4f3fcd3da2c334bf. It's caused the Jira ticket: SWDEV-554459, so revert it temporarily. Signed-off-by: Chengjun Yao --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index cf763862da502..4d1719066d350 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -506,7 +506,8 @@ static int psp_sw_init(struct amdgpu_ip_block *ip_block) } ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, - AMDGPU_GEM_DOMAIN_VRAM, + (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? + AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, &psp->fw_pri_bo, &psp->fw_pri_mc_addr, &psp->fw_pri_buf); From aec9e0de17f148f96a4bfde04da6eb7b8634d386 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Thu, 11 Sep 2025 15:38:36 +0800 Subject: [PATCH 1937/2653] drm/amdkcl: Add CONFIG_DRM_SUBALLOC_HELPER check in drm_suballoc.m4 Introduces a preprocessor check for the CONFIG_DRM_SUBALLOC_HELPER configuration option in the drm_suballoc.m4 file. It will fix driver build failure while the kernel config has no drm_suballoc built. Reviewed-by: Bob Zhou Signed-off-by: Perry Yuan --- drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 index bcb026ad2c36d..46363385a7097 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 @@ -7,7 +7,11 @@ AC_DEFUN([AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT], [ AC_KERNEL_TRY_COMPILE([ #include ], [ + #ifdef CONFIG_DRM_SUBALLOC_HELPER drm_suballoc_manager_init(NULL, 0, 0); + #else + #error CONFIG_DRM_SUBALLOC_HELPER is not enabled + #endif ], [ AC_DEFINE(HAVE_DRM_SUBALLOC_MANAGER_INIT, 1, [Has function drm_suballoc_manager_init()]) From 8d256d0b0efa9ac1b8a026a6eed5cf687fb3a4c2 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 12 Sep 2025 10:08:33 +0800 Subject: [PATCH 1938/2653] drm/amdkcl: test whether bitmap_read() available It's caused by the commit: a80bb1c0 "drm/amdgpu: Add generic capability class" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 3 + drivers/gpu/drm/amd/dkms/m4/bitmap_read.m4 | 16 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_bitmap.h | 82 ++++++++++++++++++++++ 5 files changed, 103 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/bitmap_read.m4 diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index f84f71ab7f7f3..be369146360ab 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -66,6 +66,7 @@ #include #include #include +#include #include #include #include @@ -82,7 +83,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 601b987fc18f7..0eb49c6ea9986 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -82,6 +82,9 @@ /* bitmap_free(),bitmap_alloc(),bitmap_zalloc is available */ #define HAVE_BITMAP_FUNCS 1 +/* bitmap_read() is available */ +#define HAVE_BITMAP_READ 1 + /* bitmap_to_arr32() is available */ #define HAVE_BITMAP_TO_ARR32 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/bitmap_read.m4 b/drivers/gpu/drm/amd/dkms/m4/bitmap_read.m4 new file mode 100644 index 0000000000000..233756077854c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/bitmap_read.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.9-rc1-324-g63c15822b8dd +dnl # lib/bitmap: add bitmap_{read,write}() +dnl # +AC_DEFUN([AC_AMDGPU_BITMAP_READ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + bitmap_read(NULL, 0, 0); + ],[ + AC_DEFINE(HAVE_BITMAP_READ, 1, + [bitmap_read() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 194d3cb2b3298..680456b007ce4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -294,6 +294,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_BLOCK_DEVICE_BD_DEVICE AC_AMDGPU_PAGE_PGMAP AC_AMDGPU_VMEMDUP_ARRAY_USER + AC_AMDGPU_BITMAP_READ AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_bitmap.h b/include/kcl/kcl_bitmap.h index f2c0863b7b7d8..1d23536e1cd17 100644 --- a/include/kcl/kcl_bitmap.h +++ b/include/kcl/kcl_bitmap.h @@ -22,6 +22,9 @@ #ifndef KCL_BITMAP_H #define KCL_BITMAP_H +#ifndef __ASSEMBLY__ +#include + #ifndef HAVE_BITMAP_FUNCS /* Copied from include/linux/bitmap.h*/ @@ -51,4 +54,83 @@ void kcl_bitmap_to_arr32(u32 *buf, const unsigned long *bitmap, #endif #endif /* HAVE_BITMAP_TO_ARR32 */ +#ifndef HAVE_BITMAP_READ + +/** + * bitmap_read - read a value of n-bits from the memory region + * @map: address to the bitmap memory region + * @start: bit offset of the n-bit value + * @nbits: size of value in bits, nonzero, up to BITS_PER_LONG + * + * Returns: value of @nbits bits located at the @start bit offset within the + * @map memory region. For @nbits = 0 and @nbits > BITS_PER_LONG the return + * value is undefined. + */ +static inline unsigned long kcl_bitmap_read(const unsigned long *map, + unsigned long start, + unsigned long nbits) +{ + size_t index = BIT_WORD(start); + unsigned long offset = start % BITS_PER_LONG; + unsigned long space = BITS_PER_LONG - offset; + unsigned long value_low, value_high; + + if (unlikely(!nbits || nbits > BITS_PER_LONG)) + return 0; + + if (space >= nbits) + return (map[index] >> offset) & BITMAP_LAST_WORD_MASK(nbits); + + value_low = map[index] & BITMAP_FIRST_WORD_MASK(start); + value_high = map[index + 1] & BITMAP_LAST_WORD_MASK(start + nbits); + return (value_low >> offset) | (value_high << space); +} +#define bitmap_read kcl_bitmap_read + +/** + * bitmap_write - write n-bit value within a memory region + * @map: address to the bitmap memory region + * @value: value to write, clamped to nbits + * @start: bit offset of the n-bit value + * @nbits: size of value in bits, nonzero, up to BITS_PER_LONG. + * + * bitmap_write() behaves as-if implemented as @nbits calls of __assign_bit(), + * i.e. bits beyond @nbits are ignored: + * + * for (bit = 0; bit < nbits; bit++) + * __assign_bit(start + bit, bitmap, val & BIT(bit)); + * + * For @nbits == 0 and @nbits > BITS_PER_LONG no writes are performed. + */ +static inline void kcl_bitmap_write(unsigned long *map, unsigned long value, + unsigned long start, unsigned long nbits) +{ + size_t index; + unsigned long offset; + unsigned long space; + unsigned long mask; + bool fit; + + if (unlikely(!nbits || nbits > BITS_PER_LONG)) + return; + + mask = BITMAP_LAST_WORD_MASK(nbits); + value &= mask; + offset = start % BITS_PER_LONG; + space = BITS_PER_LONG - offset; + fit = space >= nbits; + index = BIT_WORD(start); + + map[index] &= (fit ? (~(mask << offset)) : ~BITMAP_FIRST_WORD_MASK(start)); + map[index] |= value << offset; + if (fit) + return; + + map[index + 1] &= BITMAP_FIRST_WORD_MASK(start + nbits); + map[index + 1] |= (value >> space); +} +#define bitmap_write kcl_bitmap_write +#endif + +#endif /* __ASSEMBLY__ */ #endif /* KCL_BITMAP_H */ From 48b8e1e497522e211ed0c5de6f3761a6773dec3c Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 4 Sep 2025 17:43:44 +0530 Subject: [PATCH 1939/2653] drm/amdgpu: Add generic capability class Define a utility macro for defining capabilities and their attributes. Capability attributes are read-only, write-only, read-write. Signed-off-by: Lijo Lazar Acked-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h | 91 +++++++++++++++++++++++ 2 files changed, 92 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 7e5dad3b9e93a..7ef0bc4c1cc91 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -63,6 +63,7 @@ #include "kgd_pp_interface.h" #include "amd_shared.h" +#include "amdgpu_utils.h" #include "amdgpu_mode.h" #include "amdgpu_ih.h" #include "amdgpu_irq.h" diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h new file mode 100644 index 0000000000000..1e40ca3b15846 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef AMDGPU_UTILS_H_ +#define AMDGPU_UTILS_H_ + +/* ---------- Generic 2‑bit capability attribute encoding ---------- + * 00 INVALID, 01 RO, 10 WO, 11 RW + */ +enum amdgpu_cap_attr { + AMDGPU_CAP_ATTR_INVALID = 0, + AMDGPU_CAP_ATTR_RO = 1 << 0, + AMDGPU_CAP_ATTR_WO = 1 << 1, + AMDGPU_CAP_ATTR_RW = (AMDGPU_CAP_ATTR_RO | AMDGPU_CAP_ATTR_WO), +}; + +#define AMDGPU_CAP_ATTR_BITS 2 +#define AMDGPU_CAP_ATTR_MAX ((1U << AMDGPU_CAP_ATTR_BITS) - 1) + +/* Internal helper to build helpers for a given enum NAME */ +#define DECLARE_ATTR_CAP_CLASS_HELPERS(NAME) \ +enum { NAME##_BITMAP_BITS = NAME##_COUNT * AMDGPU_CAP_ATTR_BITS }; \ +struct NAME##_caps { \ + DECLARE_BITMAP(bmap, NAME##_BITMAP_BITS); \ +}; \ +static inline unsigned int NAME##_ATTR_START(enum NAME##_cap_id cap) \ +{ return (unsigned int)cap * AMDGPU_CAP_ATTR_BITS; } \ +static inline void NAME##_attr_init(struct NAME##_caps *c) \ +{ if (c) bitmap_zero(c->bmap, NAME##_BITMAP_BITS); } \ +static inline int NAME##_attr_set(struct NAME##_caps *c, \ + enum NAME##_cap_id cap, enum amdgpu_cap_attr attr) \ +{ \ + if (!c) \ + return -EINVAL; \ + if (cap >= NAME##_COUNT) \ + return -EINVAL; \ + if ((unsigned int)attr > AMDGPU_CAP_ATTR_MAX) \ + return -EINVAL; \ + bitmap_write(c->bmap, (unsigned long)attr, \ + NAME##_ATTR_START(cap), AMDGPU_CAP_ATTR_BITS); \ + return 0; \ +} \ +static inline int NAME##_attr_get(const struct NAME##_caps *c, \ + enum NAME##_cap_id cap, enum amdgpu_cap_attr *out) \ +{ \ + unsigned long v; \ + if (!c || !out) \ + return -EINVAL; \ + if (cap >= NAME##_COUNT) \ + return -EINVAL; \ + v = bitmap_read(c->bmap, NAME##_ATTR_START(cap), AMDGPU_CAP_ATTR_BITS); \ + *out = (enum amdgpu_cap_attr)v; \ + return 0; \ +} \ +static inline bool NAME##_cap_is_ro(const struct NAME##_caps *c, enum NAME##_cap_id id) \ +{ enum amdgpu_cap_attr a; return !NAME##_attr_get(c, id, &a) && a == AMDGPU_CAP_ATTR_RO; } \ +static inline bool NAME##_cap_is_wo(const struct NAME##_caps *c, enum NAME##_cap_id id) \ +{ enum amdgpu_cap_attr a; return !NAME##_attr_get(c, id, &a) && a == AMDGPU_CAP_ATTR_WO; } \ +static inline bool NAME##_cap_is_rw(const struct NAME##_caps *c, enum NAME##_cap_id id) \ +{ enum amdgpu_cap_attr a; return !NAME##_attr_get(c, id, &a) && a == AMDGPU_CAP_ATTR_RW; } + +/* Element expander for enum creation */ +#define _CAP_ENUM_ELEM(x) x, + +/* Public macro: declare enum + helpers from an X‑macro list */ +#define DECLARE_ATTR_CAP_CLASS(NAME, LIST_MACRO) \ + enum NAME##_cap_id { LIST_MACRO(_CAP_ENUM_ELEM) NAME##_COUNT }; \ + DECLARE_ATTR_CAP_CLASS_HELPERS(NAME) + +#endif /* AMDGPU_UTILS_H_ */ From 36cce302de4eb79b729492005676e1e145a475c0 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 4 Sep 2025 17:47:20 +0530 Subject: [PATCH 1940/2653] drm/amdgpu: Add virtual device capabilities Add a member to define the capabilities of virtual device. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 58accf2259b38..3afbdf7b487a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -256,6 +256,10 @@ struct amdgpu_virt_ras { uint64_t cper_rptr; }; +#define AMDGPU_VIRT_CAPS_LIST(X) X(AMDGPU_VIRT_CAP_POWER_LIMIT) + +DECLARE_ATTR_CAP_CLASS(amdgpu_virt, AMDGPU_VIRT_CAPS_LIST); + /* GPU virtualization */ struct amdgpu_virt { uint32_t caps; @@ -274,6 +278,7 @@ struct amdgpu_virt { const struct amdgpu_virt_ops *ops; struct amdgpu_vf_error_buffer vf_errors; struct amdgpu_virt_fw_reserve fw_reserve; + struct amdgpu_virt_caps virt_caps; uint32_t gim_feature; uint32_t reg_access_mode; int req_init_data_ver; From 8acd219f328066177b3d7f441d149b6525609852 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Tue, 26 Aug 2025 00:33:53 +0800 Subject: [PATCH 1941/2653] drm/amd/pm: Allow to set power cap in vf mode Allow setting power cap for smu_v13_0_6 in 1vf mode Signed-off-by: Asad Kamal Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 7 ++++--- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 6 +++++- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 0e6535df66cb8..028c63c561683 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -3254,9 +3254,6 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, int err; u32 value; - if (amdgpu_sriov_vf(adev)) - return -EINVAL; - err = kstrtou32(buf, 10, &value); if (err) return err; @@ -3598,6 +3595,10 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, return 0; } + if (attr == &sensor_dev_attr_power1_cap.dev_attr.attr && + amdgpu_virt_cap_is_rw(&adev->virt.virt_caps, AMDGPU_VIRT_CAP_POWER_LIMIT)) + effective_mode |= S_IWUSR; + /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */ if (((adev->family == AMDGPU_FAMILY_SI) || ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) && diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 1cb8089063ee9..eee27d605b38d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -143,7 +143,7 @@ static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COU MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), - MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), + MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 1), MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI | SMU_MSG_NO_PRECHECK), MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), @@ -421,6 +421,10 @@ static void smu_v13_0_6_init_caps(struct smu_context *smu) smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS)); if (amdgpu_sriov_vf(adev)) { + if (fw_ver >= 0x00558200) + amdgpu_virt_attr_set(&adev->virt.virt_caps, + AMDGPU_VIRT_CAP_POWER_LIMIT, + AMDGPU_CAP_ATTR_RW); if ((pgm == 0 && fw_ver >= 0x00558000) || (pgm == 7 && fw_ver >= 0x7551000)) { smu_v13_0_6_cap_set(smu, From 7f6963bcde24407b1b682df7796747d9cf054c66 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 10 Sep 2025 11:38:08 +0530 Subject: [PATCH 1942/2653] drm/amdgpu: Read memory vendor information Read VRAM vendor information from scratch register for GC v9.4.3 and GC v9.5.0 SOCs. Signed-off-by: Lijo Lazar Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 0b347dd706498..2041737a5fbe0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1832,11 +1832,19 @@ static void gmc_v9_0_save_registers(struct amdgpu_device *adev) static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) { + static const u32 regBIF_BIOS_SCRATCH_4 = 0x50; + u32 vram_info; + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; adev->gmc.vram_width = 128 * 64; if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; + + if (!(adev->flags & AMD_IS_APU) && !amdgpu_sriov_vf(adev)) { + vram_info = RREG32(regBIF_BIOS_SCRATCH_4); + adev->gmc.vram_vendor = vram_info & 0xF; + } } static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block) From 72c1331019ba41112837a928c209f93c1de09ec0 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 28 Aug 2025 12:50:09 +0530 Subject: [PATCH 1943/2653] drm/amdgpu: Add vbios build number interface Fetch VBIOS build number from atom rom image. Add a sysfs interface to read the build number. Signed-off-by: Lijo Lazar Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 33 ++++++++++++++++++-- drivers/gpu/drm/amd/amdgpu/atom.c | 22 +++++++++++++ drivers/gpu/drm/amd/amdgpu/atom.h | 2 ++ 3 files changed, 54 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index ab48a0f960f6b..f137194b5db21 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -1816,17 +1816,44 @@ static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev, return sysfs_emit(buf, "%s\n", ctx->vbios_pn); } +static ssize_t amdgpu_atombios_get_vbios_build(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + struct atom_context *ctx = adev->mode_info.atom_context; + + return sysfs_emit(buf, "%s\n", ctx->build_num); +} + static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version, NULL); +static DEVICE_ATTR(vbios_build, 0444, amdgpu_atombios_get_vbios_build, NULL); #ifdef HAVE_PCI_DRIVER_DEV_GROUPS static struct attribute *amdgpu_vbios_version_attrs[] = { - &dev_attr_vbios_version.attr, - NULL + &dev_attr_vbios_version.attr, &dev_attr_vbios_build.attr, NULL }; +static umode_t amdgpu_vbios_version_attrs_is_visible(struct kobject *kobj, + struct attribute *attr, + int index) +{ + struct device *dev = kobj_to_dev(kobj); + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + struct atom_context *ctx = adev->mode_info.atom_context; + + if (attr == &dev_attr_vbios_build.attr && !strlen(ctx->build_num)) + return 0; + + return attr->mode; +} + const struct attribute_group amdgpu_vbios_version_attr_group = { - .attrs = amdgpu_vbios_version_attrs + .attrs = amdgpu_vbios_version_attrs, + .is_visible = amdgpu_vbios_version_attrs_is_visible, }; int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c index 427b073de2fc1..1c994d0cc50b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.c +++ b/drivers/gpu/drm/amd/amdgpu/atom.c @@ -1494,6 +1494,27 @@ static void atom_get_vbios_version(struct atom_context *ctx) } } +static void atom_get_vbios_build(struct atom_context *ctx) +{ + unsigned char *atom_rom_hdr; + unsigned char *str; + uint16_t base; + + base = CU16(ATOM_ROM_TABLE_PTR); + atom_rom_hdr = CSTR(base); + + str = CSTR(CU16(base + ATOM_ROM_CFG_PTR)); + /* Skip config string */ + while (str < atom_rom_hdr && *str++) + ; + /* Skip change list string */ + while (str < atom_rom_hdr && *str++) + ; + + if ((str + STRLEN_NORMAL) < atom_rom_hdr) + strscpy(ctx->build_num, str, STRLEN_NORMAL); +} + struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) { int base; @@ -1554,6 +1575,7 @@ struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) atom_get_vbios_pn(ctx); atom_get_vbios_date(ctx); atom_get_vbios_version(ctx); + atom_get_vbios_build(ctx); return ctx; } diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h b/drivers/gpu/drm/amd/amdgpu/atom.h index b807f6639a4c6..825ff28731f52 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.h +++ b/drivers/gpu/drm/amd/amdgpu/atom.h @@ -37,6 +37,7 @@ struct drm_device; #define ATOM_ROM_MAGIC "ATOM" #define ATOM_ROM_MAGIC_PTR 4 +#define ATOM_ROM_CFG_PTR 0xC #define ATOM_ROM_MSG_PTR 0x10 #define ATOM_ROM_CMD_PTR 0x1E #define ATOM_ROM_DATA_PTR 0x20 @@ -151,6 +152,7 @@ struct atom_context { uint32_t version; uint8_t vbios_ver_str[STRLEN_NORMAL]; uint8_t date[STRLEN_NORMAL]; + uint8_t build_num[STRLEN_NORMAL]; }; extern int amdgpu_atom_debug; From 95dc6e52735d8217b2b2a7e2cbcb57d201ecabef Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 12 Sep 2025 10:08:33 +0800 Subject: [PATCH 1944/2653] drm/amdkcl: test whether bitmap_read() available It's caused by the commit: a80bb1c0 "drm/amdgpu: Add generic capability class" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 3 + drivers/gpu/drm/amd/dkms/m4/bitmap_read.m4 | 16 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- include/kcl/kcl_bitmap.h | 82 ++++++++++++++++++++++ 5 files changed, 104 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/bitmap_read.m4 diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7c1d32b57bb2f..e1cdfe0312c7d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -66,6 +66,7 @@ #include #include #include +#include #include #include #include @@ -82,7 +83,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a7a6673c64457..b82cd9975a8b6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -82,6 +82,9 @@ /* bitmap_free(),bitmap_alloc(),bitmap_zalloc is available */ #define HAVE_BITMAP_FUNCS 1 +/* bitmap_read() is available */ +#define HAVE_BITMAP_READ 1 + /* bitmap_to_arr32() is available */ #define HAVE_BITMAP_TO_ARR32 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/bitmap_read.m4 b/drivers/gpu/drm/amd/dkms/m4/bitmap_read.m4 new file mode 100644 index 0000000000000..233756077854c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/bitmap_read.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.9-rc1-324-g63c15822b8dd +dnl # lib/bitmap: add bitmap_{read,write}() +dnl # +AC_DEFUN([AC_AMDGPU_BITMAP_READ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + bitmap_read(NULL, 0, 0); + ],[ + AC_DEFINE(HAVE_BITMAP_READ, 1, + [bitmap_read() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index de6d794e90432..7984ed0576724 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -290,7 +290,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FILE_DEBUGFS_CLIENT AC_AMDGPU_DRM_VBLANK_CRTC_STRUCT_CONFIG AC_AMDGPU_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN - + AC_AMDGPU_BITMAP_READ + AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" diff --git a/include/kcl/kcl_bitmap.h b/include/kcl/kcl_bitmap.h index f2c0863b7b7d8..1d23536e1cd17 100644 --- a/include/kcl/kcl_bitmap.h +++ b/include/kcl/kcl_bitmap.h @@ -22,6 +22,9 @@ #ifndef KCL_BITMAP_H #define KCL_BITMAP_H +#ifndef __ASSEMBLY__ +#include + #ifndef HAVE_BITMAP_FUNCS /* Copied from include/linux/bitmap.h*/ @@ -51,4 +54,83 @@ void kcl_bitmap_to_arr32(u32 *buf, const unsigned long *bitmap, #endif #endif /* HAVE_BITMAP_TO_ARR32 */ +#ifndef HAVE_BITMAP_READ + +/** + * bitmap_read - read a value of n-bits from the memory region + * @map: address to the bitmap memory region + * @start: bit offset of the n-bit value + * @nbits: size of value in bits, nonzero, up to BITS_PER_LONG + * + * Returns: value of @nbits bits located at the @start bit offset within the + * @map memory region. For @nbits = 0 and @nbits > BITS_PER_LONG the return + * value is undefined. + */ +static inline unsigned long kcl_bitmap_read(const unsigned long *map, + unsigned long start, + unsigned long nbits) +{ + size_t index = BIT_WORD(start); + unsigned long offset = start % BITS_PER_LONG; + unsigned long space = BITS_PER_LONG - offset; + unsigned long value_low, value_high; + + if (unlikely(!nbits || nbits > BITS_PER_LONG)) + return 0; + + if (space >= nbits) + return (map[index] >> offset) & BITMAP_LAST_WORD_MASK(nbits); + + value_low = map[index] & BITMAP_FIRST_WORD_MASK(start); + value_high = map[index + 1] & BITMAP_LAST_WORD_MASK(start + nbits); + return (value_low >> offset) | (value_high << space); +} +#define bitmap_read kcl_bitmap_read + +/** + * bitmap_write - write n-bit value within a memory region + * @map: address to the bitmap memory region + * @value: value to write, clamped to nbits + * @start: bit offset of the n-bit value + * @nbits: size of value in bits, nonzero, up to BITS_PER_LONG. + * + * bitmap_write() behaves as-if implemented as @nbits calls of __assign_bit(), + * i.e. bits beyond @nbits are ignored: + * + * for (bit = 0; bit < nbits; bit++) + * __assign_bit(start + bit, bitmap, val & BIT(bit)); + * + * For @nbits == 0 and @nbits > BITS_PER_LONG no writes are performed. + */ +static inline void kcl_bitmap_write(unsigned long *map, unsigned long value, + unsigned long start, unsigned long nbits) +{ + size_t index; + unsigned long offset; + unsigned long space; + unsigned long mask; + bool fit; + + if (unlikely(!nbits || nbits > BITS_PER_LONG)) + return; + + mask = BITMAP_LAST_WORD_MASK(nbits); + value &= mask; + offset = start % BITS_PER_LONG; + space = BITS_PER_LONG - offset; + fit = space >= nbits; + index = BIT_WORD(start); + + map[index] &= (fit ? (~(mask << offset)) : ~BITMAP_FIRST_WORD_MASK(start)); + map[index] |= value << offset; + if (fit) + return; + + map[index + 1] &= BITMAP_FIRST_WORD_MASK(start + nbits); + map[index + 1] |= (value >> space); +} +#define bitmap_write kcl_bitmap_write +#endif + +#endif /* __ASSEMBLY__ */ #endif /* KCL_BITMAP_H */ From 3da05cc9fa0fb28a7079b2b8ff19f9e4f1640c20 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 4 Sep 2025 17:43:44 +0530 Subject: [PATCH 1945/2653] drm/amdgpu: Add generic capability class Define a utility macro for defining capabilities and their attributes. Capability attributes are read-only, write-only, read-write. Signed-off-by: Lijo Lazar Acked-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h | 91 +++++++++++++++++++++++ 2 files changed, 92 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 724c99bbc6797..9cf70b8d5cb3d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -63,6 +63,7 @@ #include "kgd_pp_interface.h" #include "amd_shared.h" +#include "amdgpu_utils.h" #include "amdgpu_mode.h" #include "amdgpu_ih.h" #include "amdgpu_irq.h" diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h new file mode 100644 index 0000000000000..1e40ca3b15846 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_utils.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef AMDGPU_UTILS_H_ +#define AMDGPU_UTILS_H_ + +/* ---------- Generic 2‑bit capability attribute encoding ---------- + * 00 INVALID, 01 RO, 10 WO, 11 RW + */ +enum amdgpu_cap_attr { + AMDGPU_CAP_ATTR_INVALID = 0, + AMDGPU_CAP_ATTR_RO = 1 << 0, + AMDGPU_CAP_ATTR_WO = 1 << 1, + AMDGPU_CAP_ATTR_RW = (AMDGPU_CAP_ATTR_RO | AMDGPU_CAP_ATTR_WO), +}; + +#define AMDGPU_CAP_ATTR_BITS 2 +#define AMDGPU_CAP_ATTR_MAX ((1U << AMDGPU_CAP_ATTR_BITS) - 1) + +/* Internal helper to build helpers for a given enum NAME */ +#define DECLARE_ATTR_CAP_CLASS_HELPERS(NAME) \ +enum { NAME##_BITMAP_BITS = NAME##_COUNT * AMDGPU_CAP_ATTR_BITS }; \ +struct NAME##_caps { \ + DECLARE_BITMAP(bmap, NAME##_BITMAP_BITS); \ +}; \ +static inline unsigned int NAME##_ATTR_START(enum NAME##_cap_id cap) \ +{ return (unsigned int)cap * AMDGPU_CAP_ATTR_BITS; } \ +static inline void NAME##_attr_init(struct NAME##_caps *c) \ +{ if (c) bitmap_zero(c->bmap, NAME##_BITMAP_BITS); } \ +static inline int NAME##_attr_set(struct NAME##_caps *c, \ + enum NAME##_cap_id cap, enum amdgpu_cap_attr attr) \ +{ \ + if (!c) \ + return -EINVAL; \ + if (cap >= NAME##_COUNT) \ + return -EINVAL; \ + if ((unsigned int)attr > AMDGPU_CAP_ATTR_MAX) \ + return -EINVAL; \ + bitmap_write(c->bmap, (unsigned long)attr, \ + NAME##_ATTR_START(cap), AMDGPU_CAP_ATTR_BITS); \ + return 0; \ +} \ +static inline int NAME##_attr_get(const struct NAME##_caps *c, \ + enum NAME##_cap_id cap, enum amdgpu_cap_attr *out) \ +{ \ + unsigned long v; \ + if (!c || !out) \ + return -EINVAL; \ + if (cap >= NAME##_COUNT) \ + return -EINVAL; \ + v = bitmap_read(c->bmap, NAME##_ATTR_START(cap), AMDGPU_CAP_ATTR_BITS); \ + *out = (enum amdgpu_cap_attr)v; \ + return 0; \ +} \ +static inline bool NAME##_cap_is_ro(const struct NAME##_caps *c, enum NAME##_cap_id id) \ +{ enum amdgpu_cap_attr a; return !NAME##_attr_get(c, id, &a) && a == AMDGPU_CAP_ATTR_RO; } \ +static inline bool NAME##_cap_is_wo(const struct NAME##_caps *c, enum NAME##_cap_id id) \ +{ enum amdgpu_cap_attr a; return !NAME##_attr_get(c, id, &a) && a == AMDGPU_CAP_ATTR_WO; } \ +static inline bool NAME##_cap_is_rw(const struct NAME##_caps *c, enum NAME##_cap_id id) \ +{ enum amdgpu_cap_attr a; return !NAME##_attr_get(c, id, &a) && a == AMDGPU_CAP_ATTR_RW; } + +/* Element expander for enum creation */ +#define _CAP_ENUM_ELEM(x) x, + +/* Public macro: declare enum + helpers from an X‑macro list */ +#define DECLARE_ATTR_CAP_CLASS(NAME, LIST_MACRO) \ + enum NAME##_cap_id { LIST_MACRO(_CAP_ENUM_ELEM) NAME##_COUNT }; \ + DECLARE_ATTR_CAP_CLASS_HELPERS(NAME) + +#endif /* AMDGPU_UTILS_H_ */ From 3972ebfcfab91d1bca6503ff3e54efa16f1c42d0 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 4 Sep 2025 17:47:20 +0530 Subject: [PATCH 1946/2653] drm/amdgpu: Add virtual device capabilities Add a member to define the capabilities of virtual device. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 58accf2259b38..3afbdf7b487a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -256,6 +256,10 @@ struct amdgpu_virt_ras { uint64_t cper_rptr; }; +#define AMDGPU_VIRT_CAPS_LIST(X) X(AMDGPU_VIRT_CAP_POWER_LIMIT) + +DECLARE_ATTR_CAP_CLASS(amdgpu_virt, AMDGPU_VIRT_CAPS_LIST); + /* GPU virtualization */ struct amdgpu_virt { uint32_t caps; @@ -274,6 +278,7 @@ struct amdgpu_virt { const struct amdgpu_virt_ops *ops; struct amdgpu_vf_error_buffer vf_errors; struct amdgpu_virt_fw_reserve fw_reserve; + struct amdgpu_virt_caps virt_caps; uint32_t gim_feature; uint32_t reg_access_mode; int req_init_data_ver; From 68d320ecc1a3754e4bfdec416b8b4d72a1287d39 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Tue, 26 Aug 2025 00:33:53 +0800 Subject: [PATCH 1947/2653] drm/amd/pm: Allow to set power cap in vf mode Allow setting power cap for smu_v13_0_6 in 1vf mode Signed-off-by: Asad Kamal Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 7 ++++--- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 6 +++++- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index c59bdd15e0e5c..0521295d91b5a 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -3253,9 +3253,6 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, int err; u32 value; - if (amdgpu_sriov_vf(adev)) - return -EINVAL; - err = kstrtou32(buf, 10, &value); if (err) return err; @@ -3597,6 +3594,10 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, return 0; } + if (attr == &sensor_dev_attr_power1_cap.dev_attr.attr && + amdgpu_virt_cap_is_rw(&adev->virt.virt_caps, AMDGPU_VIRT_CAP_POWER_LIMIT)) + effective_mode |= S_IWUSR; + /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */ if (((adev->family == AMDGPU_FAMILY_SI) || ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) && diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index ff197134fafe8..3aca0b6868016 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -143,7 +143,7 @@ static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COU MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1), MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1), MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), - MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), + MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 1), MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI | SMU_MSG_NO_PRECHECK), MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), @@ -421,6 +421,10 @@ static void smu_v13_0_6_init_caps(struct smu_context *smu) smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS)); if (amdgpu_sriov_vf(adev)) { + if (fw_ver >= 0x00558200) + amdgpu_virt_attr_set(&adev->virt.virt_caps, + AMDGPU_VIRT_CAP_POWER_LIMIT, + AMDGPU_CAP_ATTR_RW); if ((pgm == 0 && fw_ver >= 0x00558000) || (pgm == 7 && fw_ver >= 0x7551000)) { smu_v13_0_6_cap_set(smu, From ca04df6e52c11db9ecd9539505afcfc04bf3780d Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 10 Sep 2025 11:38:08 +0530 Subject: [PATCH 1948/2653] drm/amdgpu: Read memory vendor information Read VRAM vendor information from scratch register for GC v9.4.3 and GC v9.5.0 SOCs. Signed-off-by: Lijo Lazar Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 0b347dd706498..2041737a5fbe0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1832,11 +1832,19 @@ static void gmc_v9_0_save_registers(struct amdgpu_device *adev) static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) { + static const u32 regBIF_BIOS_SCRATCH_4 = 0x50; + u32 vram_info; + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; adev->gmc.vram_width = 128 * 64; if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; + + if (!(adev->flags & AMD_IS_APU) && !amdgpu_sriov_vf(adev)) { + vram_info = RREG32(regBIF_BIOS_SCRATCH_4); + adev->gmc.vram_vendor = vram_info & 0xF; + } } static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block) From 6d4ed9049254a1379611ef696e2069e2629fc99e Mon Sep 17 00:00:00 2001 From: Yang Su Date: Fri, 12 Sep 2025 16:13:43 +0800 Subject: [PATCH 1949/2653] Bump AMDGPU version to 6.16.3 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 8be0ae489f762..68f9689b5315d 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.16.2) +AC_INIT(amdgpu-dkms, 6.16.3) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 77059a9a31ff032d80105273fc30bcd441d53d8b Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Thu, 4 Sep 2025 08:52:53 +0800 Subject: [PATCH 1950/2653] drm/amd/pm: unified smu feature cap interface add a unified interface to provide smu feature cap set. Signed-off-by: Yang Wang Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 29 +++++++++++++++++++ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 12 ++++++++ 2 files changed, 41 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 1d5f9466b3956..aa51124d4b84e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -1315,6 +1315,33 @@ static void smu_init_power_profile(struct smu_context *smu) } +void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id) +{ + struct smu_feature_cap *fea_cap = &smu->fea_cap; + + if (fea_id >= SMU_FEATURE_CAP_ID__COUNT) + return; + + set_bit(fea_id, fea_cap->cap_map); +} + +bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id) +{ + struct smu_feature_cap *fea_cap = &smu->fea_cap; + + if (fea_id >= SMU_FEATURE_CAP_ID__COUNT) + return false; + + return test_bit(fea_id, fea_cap->cap_map); +} + +static void smu_feature_cap_init(struct smu_context *smu) +{ + struct smu_feature_cap *fea_cap = &smu->fea_cap; + + bitmap_zero(fea_cap->cap_map, SMU_FEATURE_CAP_ID__COUNT); +} + static int smu_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -1347,6 +1374,8 @@ static int smu_sw_init(struct amdgpu_ip_block *ip_block) INIT_DELAYED_WORK(&smu->swctf_delayed_work, smu_swctf_delayed_work_handler); + smu_feature_cap_init(smu); + ret = smu_smc_table_sw_init(smu); if (ret) { dev_err(adev->dev, "Failed to sw init smc table!\n"); diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index be2edb3daa4b1..e9f1c00c0f74c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -559,6 +559,14 @@ enum smu_fw_status { */ #define SMU_WBRF_EVENT_HANDLING_PACE 10 +enum smu_feature_cap_id { + SMU_FEATURE_CAP_ID__COUNT, +}; + +struct smu_feature_cap { + DECLARE_BITMAP(cap_map, SMU_FEATURE_CAP_ID__COUNT); +}; + struct smu_context { struct amdgpu_device *adev; struct amdgpu_irq_src irq_source; @@ -581,6 +589,7 @@ struct smu_context { struct amd_pp_display_configuration *display_config; struct smu_baco_context smu_baco; struct smu_temperature_range thermal_range; + struct smu_feature_cap fea_cap; void *od_settings; struct smu_umd_pstate_table pstate_table; @@ -1826,4 +1835,7 @@ int smu_phase_det_enable(struct smu_context *smu, bool enable); void amdgpu_smu_phase_det_debugfs_init(struct amdgpu_device *adev); #endif + +void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id); +bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id); #endif From 8304dbf1e03d09594ffe52ca3240bc623a943f1c Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Wed, 10 Sep 2025 13:40:30 -0500 Subject: [PATCH 1951/2653] drm/amd: Duplicate DC_FEATURE_MASK and DC_DEBUG_MASK enum values into kdoc [Why] When kernel documentation is generated the enum values themselves don't end up in the documentation. This makes browsing them in HTML a lot less useful. [How] Copy DC_DEBUG_MASK and DC_FEATURE_MASK enum values into matching kdoc comments. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- Documentation/gpu/amdgpu/driver-core.rst | 2 +- drivers/gpu/drm/amd/include/amd_shared.h | 98 ++++++++++++++++-------- 2 files changed, 67 insertions(+), 33 deletions(-) diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst index 81256318e93cf..30f6389613759 100644 --- a/Documentation/gpu/amdgpu/driver-core.rst +++ b/Documentation/gpu/amdgpu/driver-core.rst @@ -210,4 +210,4 @@ IP Blocks :doc: IP Blocks .. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h - :identifiers: amd_ip_block_type amd_ip_funcs DC_DEBUG_MASK + :identifiers: amd_ip_block_type amd_ip_funcs DC_FEATURE_MASK DC_DEBUG_MASK diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index bfb446736ca8c..75efda2969cfb 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -239,18 +239,51 @@ enum amd_harvest_ip_mask { AMD_HARVEST_IP_DMU_MASK = 0x4, }; +/** + * enum DC_FEATURE_MASK - Bits that control DC feature defaults + */ enum DC_FEATURE_MASK { //Default value can be found at "uint amdgpu_dc_feature_mask" - DC_FBC_MASK = (1 << 0), //0x1, disabled by default - DC_MULTI_MON_PP_MCLK_SWITCH_MASK = (1 << 1), //0x2, enabled by default - DC_DISABLE_FRACTIONAL_PWM_MASK = (1 << 2), //0x4, disabled by default - DC_PSR_MASK = (1 << 3), //0x8, disabled by default for dcn < 3.1 - DC_EDP_NO_POWER_SEQUENCING = (1 << 4), //0x10, disabled by default - DC_DISABLE_LTTPR_DP1_4A = (1 << 5), //0x20, disabled by default - DC_DISABLE_LTTPR_DP2_0 = (1 << 6), //0x40, disabled by default - DC_PSR_ALLOW_SMU_OPT = (1 << 7), //0x80, disabled by default - DC_PSR_ALLOW_MULTI_DISP_OPT = (1 << 8), //0x100, disabled by default - DC_REPLAY_MASK = (1 << 9), //0x200, disabled by default for dcn < 3.1.4 + /** + * @DC_FBC_MASK: (0x1) disabled by default + */ + DC_FBC_MASK = (1 << 0), + /** + * @DC_MULTI_MON_PP_MCLK_SWITCH_MASK: (0x2) enabled by default + */ + DC_MULTI_MON_PP_MCLK_SWITCH_MASK = (1 << 1), + /** + * @DC_DISABLE_FRACTIONAL_PWM_MASK: (0x4) disabled by default + */ + DC_DISABLE_FRACTIONAL_PWM_MASK = (1 << 2), + /** + * @DC_PSR_MASK: (0x8) disabled by default for DCN < 3.1 + */ + DC_PSR_MASK = (1 << 3), + /** + * @DC_EDP_NO_POWER_SEQUENCING: (0x10) disabled by default + */ + DC_EDP_NO_POWER_SEQUENCING = (1 << 4), + /** + * @DC_DISABLE_LTTPR_DP1_4A: (0x20) disabled by default + */ + DC_DISABLE_LTTPR_DP1_4A = (1 << 5), + /** + * @DC_DISABLE_LTTPR_DP2_0: (0x40) disabled by default + */ + DC_DISABLE_LTTPR_DP2_0 = (1 << 6), + /** + * @DC_PSR_ALLOW_SMU_OPT: (0x80) disabled by default + */ + DC_PSR_ALLOW_SMU_OPT = (1 << 7), + /** + * @DC_PSR_ALLOW_MULTI_DISP_OPT: (0x100) disabled by default + */ + DC_PSR_ALLOW_MULTI_DISP_OPT = (1 << 8), + /** + * @DC_REPLAY_MASK: (0x200) disabled by default for DCN < 3.1.4 + */ + DC_REPLAY_MASK = (1 << 9), }; /** @@ -258,64 +291,64 @@ enum DC_FEATURE_MASK { */ enum DC_DEBUG_MASK { /** - * @DC_DISABLE_PIPE_SPLIT: If set, disable pipe-splitting + * @DC_DISABLE_PIPE_SPLIT: (0x1) If set, disable pipe-splitting */ DC_DISABLE_PIPE_SPLIT = 0x1, /** - * @DC_DISABLE_STUTTER: If set, disable memory stutter mode + * @DC_DISABLE_STUTTER: (0x2) If set, disable memory stutter mode */ DC_DISABLE_STUTTER = 0x2, /** - * @DC_DISABLE_DSC: If set, disable display stream compression + * @DC_DISABLE_DSC: (0x4) If set, disable display stream compression */ DC_DISABLE_DSC = 0x4, /** - * @DC_DISABLE_CLOCK_GATING: If set, disable clock gating optimizations + * @DC_DISABLE_CLOCK_GATING: (0x8) If set, disable clock gating optimizations */ DC_DISABLE_CLOCK_GATING = 0x8, /** - * @DC_DISABLE_PSR: If set, disable Panel self refresh v1 and PSR-SU + * @DC_DISABLE_PSR: (0x10) If set, disable Panel self refresh v1 and PSR-SU */ DC_DISABLE_PSR = 0x10, /** - * @DC_FORCE_SUBVP_MCLK_SWITCH: If set, force mclk switch in subvp, even + * @DC_FORCE_SUBVP_MCLK_SWITCH: (0x20) If set, force mclk switch in subvp, even * if mclk switch in vblank is possible */ DC_FORCE_SUBVP_MCLK_SWITCH = 0x20, /** - * @DC_DISABLE_MPO: If set, disable multi-plane offloading + * @DC_DISABLE_MPO: (0x40) If set, disable multi-plane offloading */ DC_DISABLE_MPO = 0x40, /** - * @DC_ENABLE_DPIA_TRACE: If set, enable trace logging for DPIA + * @DC_ENABLE_DPIA_TRACE: (0x80) If set, enable trace logging for DPIA */ DC_ENABLE_DPIA_TRACE = 0x80, /** - * @DC_ENABLE_DML2: If set, force usage of DML2, even if the DCN version + * @DC_ENABLE_DML2: (0x100) If set, force usage of DML2, even if the DCN version * does not default to it. */ DC_ENABLE_DML2 = 0x100, /** - * @DC_DISABLE_PSR_SU: If set, disable PSR SU + * @DC_DISABLE_PSR_SU: (0x200) If set, disable PSR SU */ DC_DISABLE_PSR_SU = 0x200, /** - * @DC_DISABLE_REPLAY: If set, disable Panel Replay + * @DC_DISABLE_REPLAY: (0x400) If set, disable Panel Replay */ DC_DISABLE_REPLAY = 0x400, /** - * @DC_DISABLE_IPS: If set, disable all Idle Power States, all the time. + * @DC_DISABLE_IPS: (0x800) If set, disable all Idle Power States, all the time. * If more than one IPS debug bit is set, the lowest bit takes * precedence. For example, if DC_FORCE_IPS_ENABLE and * DC_DISABLE_IPS_DYNAMIC are set, then DC_DISABLE_IPS_DYNAMIC takes @@ -324,56 +357,57 @@ enum DC_DEBUG_MASK { DC_DISABLE_IPS = 0x800, /** - * @DC_DISABLE_IPS_DYNAMIC: If set, disable all IPS, all the time, + * @DC_DISABLE_IPS_DYNAMIC: (0x1000) If set, disable all IPS, all the time, * *except* when driver goes into suspend. */ DC_DISABLE_IPS_DYNAMIC = 0x1000, /** - * @DC_DISABLE_IPS2_DYNAMIC: If set, disable IPS2 (IPS1 allowed) if + * @DC_DISABLE_IPS2_DYNAMIC: (0x2000) If set, disable IPS2 (IPS1 allowed) if * there is an enabled display. Otherwise, enable all IPS. */ DC_DISABLE_IPS2_DYNAMIC = 0x2000, /** - * @DC_FORCE_IPS_ENABLE: If set, force enable all IPS, all the time. + * @DC_FORCE_IPS_ENABLE: (0x4000) If set, force enable all IPS, all the time. */ DC_FORCE_IPS_ENABLE = 0x4000, /** - * @DC_DISABLE_ACPI_EDID: If set, don't attempt to fetch EDID for + * @DC_DISABLE_ACPI_EDID: (0x8000) If set, don't attempt to fetch EDID for * eDP display from ACPI _DDC method. */ DC_DISABLE_ACPI_EDID = 0x8000, /** - * @DC_DISABLE_HDMI_CEC: If set, disable HDMI-CEC feature in amdgpu driver. + * @DC_DISABLE_HDMI_CEC: (0x10000) If set, disable HDMI-CEC feature in amdgpu driver. */ DC_DISABLE_HDMI_CEC = 0x10000, /** - * @DC_DISABLE_SUBVP_FAMS: If set, disable DCN Sub-Viewport & Firmware Assisted + * @DC_DISABLE_SUBVP_FAMS: (0x20000) If set, disable DCN Sub-Viewport & Firmware Assisted * Memory Clock Switching (FAMS) feature in amdgpu driver. */ DC_DISABLE_SUBVP_FAMS = 0x20000, /** - * @DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE: If set, disable support for custom brightness curves + * @DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE: (0x40000) If set, disable support for custom + * brightness curves */ DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE = 0x40000, /** - * @DC_HDCP_LC_FORCE_FW_ENABLE: If set, use HDCP Locality Check FW + * @DC_HDCP_LC_FORCE_FW_ENABLE: (0x80000) If set, use HDCP Locality Check FW * path regardless of reported HW capabilities. */ DC_HDCP_LC_FORCE_FW_ENABLE = 0x80000, /** - * @DC_HDCP_LC_ENABLE_SW_FALLBACK: If set, upon HDCP Locality Check FW + * @DC_HDCP_LC_ENABLE_SW_FALLBACK: (0x100000) If set, upon HDCP Locality Check FW * path failure, retry using legacy SW path. */ DC_HDCP_LC_ENABLE_SW_FALLBACK = 0x100000, /** - * @DC_SKIP_DETECTION_LT: If set, skip detection link training + * @DC_SKIP_DETECTION_LT: (0x200000) If set, skip detection link training */ DC_SKIP_DETECTION_LT = 0x200000, }; From bcb732763607739dccb8783f4dfbc70e3c6a086d Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 10 Sep 2025 12:27:05 +0530 Subject: [PATCH 1952/2653] drm/amdgpu/gfx11: Add Cleaner Shader Support for GFX11.0.1/11.0.4 GPUs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the cleaner shader for additional GFX11.0.1/11.0.4 series GPUs to ensure data isolation among GPU tasks. The cleaner shader is tasked with clearing the Local Data Store (LDS), Vector General Purpose Registers (VGPRs), and Scalar General Purpose Registers (SGPRs), which helps avoid data leakage and guarantees the accuracy of computational results. This update extends cleaner shader support to GFX11.0.1/11.0.4 GPUs, previously available for GFX11.0.3. It enhances security by clearing GPU memory between processes and maintains a consistent GPU state across KGD and KFD workloads. Cc: Wasee Alam Cc: Mario Sopena-Novales Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 2d600218aa60b..39e8cbb2b5034 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -1653,6 +1653,21 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block) } } break; + case IP_VERSION(11, 0, 1): + case IP_VERSION(11, 0, 4): + adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; + adev->gfx.cleaner_shader_size = sizeof(gfx_11_0_3_cleaner_shader_hex); + if (adev->gfx.pfp_fw_version >= 102 && + adev->gfx.mec_fw_version >= 66 && + adev->mes.fw_version[0] >= 128) { + adev->gfx.enable_cleaner_shader = true; + r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); + if (r) { + adev->gfx.enable_cleaner_shader = false; + dev_err(adev->dev, "Failed to initialize cleaner shader\n"); + } + } + break; case IP_VERSION(11, 5, 0): case IP_VERSION(11, 5, 1): adev->gfx.cleaner_shader_ptr = gfx_11_0_3_cleaner_shader_hex; From 65cc5ea7614209c2874e7b3365b2f6b17e7abc41 Mon Sep 17 00:00:00 2001 From: Thorsten Blum Date: Tue, 9 Sep 2025 17:11:46 +0200 Subject: [PATCH 1953/2653] drm/amdkfd: Replace kmalloc + copy_from_user with memdup_user Replace kmalloc() followed by copy_from_user() with memdup_user() to improve and simplify kfd_criu_restore_queue(). No functional changes intended. Signed-off-by: Thorsten Blum Signed-off-by: Alex Deucher --- .../amd/amdkfd/kfd_process_queue_manager.c | 22 +++++-------------- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index d91b0e498fc9d..6f64e7217d490 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -1008,13 +1008,9 @@ int kfd_criu_restore_queue(struct kfd_process *p, if (*priv_data_offset + sizeof(*q_data) > max_priv_data_size) return -EINVAL; - q_data = kmalloc(sizeof(*q_data), GFP_KERNEL); - if (!q_data) - return -ENOMEM; - - ret = copy_from_user(q_data, user_priv_ptr + *priv_data_offset, sizeof(*q_data)); - if (ret) { - ret = -EFAULT; + q_data = memdup_user(user_priv_ptr + *priv_data_offset, sizeof(*q_data)); + if (IS_ERR(q_data)) { + ret = PTR_ERR(q_data); goto exit; } @@ -1026,15 +1022,9 @@ int kfd_criu_restore_queue(struct kfd_process *p, goto exit; } - q_extra_data = kmalloc(q_extra_data_size, GFP_KERNEL); - if (!q_extra_data) { - ret = -ENOMEM; - goto exit; - } - - ret = copy_from_user(q_extra_data, user_priv_ptr + *priv_data_offset, q_extra_data_size); - if (ret) { - ret = -EFAULT; + q_extra_data = memdup_user(user_priv_ptr + *priv_data_offset, q_extra_data_size); + if (IS_ERR(q_extra_data)) { + ret = PTR_ERR(q_extra_data); goto exit; } From 7da519a0eefaaa5a0779727d1c082fe2912e6fd5 Mon Sep 17 00:00:00 2001 From: Zhikai Zhai Date: Tue, 29 Jul 2025 17:39:54 +0800 Subject: [PATCH 1954/2653] drm/amd/display: Modify the link training policy [Why&How] Currently fallback to low link rate if the link training fails once on USB4. It may cause the bandwidth couldn't satisfy the requirement of streams. Modify the policy to do training retry in the previous few times, only do fallback at the last time. Reviewed-by: Meenakshikumar Somasundaram Signed-off-by: Zhikai Zhai Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/link/protocols/link_dp_training.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c index fce83f4f94482..2af51afef82ab 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c @@ -1730,6 +1730,15 @@ bool perform_link_training_with_retries( break; } + if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && + stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST && + !link->dc->config.enable_dpia_pre_training) { + if (j == (attempts - 1)) + do_fallback = true; + else + do_fallback = false; + } + if (j == (attempts - 1)) { DC_LOG_WARNING( "%s: Link(%d) training attempt %u of %d failed @ rate(%d) x lane(%d) @ spread = %x : fail reason:(%d)\n", From 02d9bae7cd816d21cc71c58eb88a7981fc1827fb Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Wed, 11 Jun 2025 16:51:21 -0400 Subject: [PATCH 1955/2653] drm/amd/display: prepare dml 2.1 for new asic [Why&How] prepare dml 2.1 for new asic Acked-by: Wayne Lin Signed-off-by: Dmytro Laktyushkin Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc_state.c | 2 +- .../gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h | 6 +++--- drivers/gpu/drm/amd/display/dc/inc/resource.h | 1 + 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c index 883054bb18e76..c61300a7cb1c9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c @@ -211,7 +211,7 @@ struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *p return NULL; } - if (!dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source)) { + if (dc->caps.dcmode_power_limits_present && !dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source)) { dc_state_release(state); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h index 7de10a95cfdb1..41adb1104d0fd 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h @@ -16,9 +16,9 @@ struct dml2_instance; enum dml2_project_id { dml2_project_invalid = 0, - dml2_project_dcn4x_stage1 = 1, - dml2_project_dcn4x_stage2 = 2, - dml2_project_dcn4x_stage2_auto_drr_svp = 3, + dml2_project_dcn4x_stage1, + dml2_project_dcn4x_stage2, + dml2_project_dcn4x_stage2_auto_drr_svp, }; enum dml2_pstate_change_support { diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index a890f581f4e89..4e26a16a8743f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -45,6 +45,7 @@ enum dce_version resource_parse_asic_id( struct resource_caps { int num_timing_generator; int num_opp; + int num_dpp; int num_video_plane; int num_audio; int num_stream_encoder; From 7a66f61bed1037ec736fcdc61bb6f54aa2334b56 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Fri, 8 Aug 2025 10:26:22 -0400 Subject: [PATCH 1956/2653] drm/amd/display: Fix DMCUB loading sequence for DCN3.2 [Why] New sequence from HW for reset and firmware reloading has been provided that aims to stabilize the reload sequence in the case the firmware is hung or has outstanding requests. [How] Update the sequence to remove the DMUIF reset and the redundant writes in the release. Reviewed-by: Sreeja Golui Signed-off-by: Nicholas Kazlauskas Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 53 ++++++++++--------- .../gpu/drm/amd/display/dmub/src/dmub_dcn32.h | 8 ++- 2 files changed, 35 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c index e7056205b0506..ce041f6239dc7 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c @@ -89,44 +89,50 @@ static inline void dmub_dcn32_translate_addr(const union dmub_addr *addr_in, void dmub_dcn32_reset(struct dmub_srv *dmub) { union dmub_gpint_data_register cmd; - const uint32_t timeout = 30; - uint32_t in_reset, scratch, i; + const uint32_t timeout = 100000; + uint32_t in_reset, is_enabled, scratch, i, pwait_mode; REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); + REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled); - if (in_reset == 0) { + if (in_reset == 0 && is_enabled != 0) { cmd.bits.status = 1; cmd.bits.command_code = DMUB_GPINT__STOP_FW; cmd.bits.param = 0; dmub->hw_funcs.set_gpint(dmub, cmd); - /** - * Timeout covers both the ACK and the wait - * for remaining work to finish. - * - * This is mostly bound by the PHY disable sequence. - * Each register check will be greater than 1us, so - * don't bother using udelay. - */ - for (i = 0; i < timeout; ++i) { if (dmub->hw_funcs.is_gpint_acked(dmub, cmd)) break; + + udelay(1); } for (i = 0; i < timeout; ++i) { - scratch = dmub->hw_funcs.get_gpint_response(dmub); + scratch = REG_READ(DMCUB_SCRATCH7); if (scratch == DMUB_GPINT__STOP_FW_RESPONSE) break; + + udelay(1); } + for (i = 0; i < timeout; ++i) { + REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode); + if (pwait_mode & (1 << 0)) + break; + + udelay(1); + } /* Force reset in case we timed out, DMCUB is likely hung. */ } - REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1); - REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); - REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1); + if (is_enabled) { + REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1); + udelay(1); + REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); + } + REG_WRITE(DMCUB_INBOX1_RPTR, 0); REG_WRITE(DMCUB_INBOX1_WPTR, 0); REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); @@ -135,7 +141,7 @@ void dmub_dcn32_reset(struct dmub_srv *dmub) REG_WRITE(DMCUB_OUTBOX0_WPTR, 0); REG_WRITE(DMCUB_SCRATCH0, 0); - /* Clear the GPINT command manually so we don't reset again. */ + /* Clear the GPINT command manually so we don't send anything during boot. */ cmd.all = 0; dmub->hw_funcs.set_gpint(dmub, cmd); } @@ -419,8 +425,8 @@ uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub) void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub) { - uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset; - uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled; + uint32_t is_dmub_enabled, is_soft_reset, is_pwait; + uint32_t is_traceport_enabled, is_cw6_enabled; struct dmub_timeout_info timeout = {0}; if (!dmub) @@ -470,18 +476,15 @@ void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub) REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); dmub->debug.is_dmcub_enabled = is_dmub_enabled; + REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait); + dmub->debug.is_pwait = is_pwait; + REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); dmub->debug.is_dmcub_soft_reset = is_soft_reset; - REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); - dmub->debug.is_dmcub_secure_reset = is_sec_reset; - REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); dmub->debug.is_traceport_en = is_traceport_enabled; - REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); - dmub->debug.is_cw0_enabled = is_cw0_enabled; - REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); dmub->debug.is_cw6_enabled = is_cw6_enabled; diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h index 1a229450c53db..daf81027d6631 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h @@ -89,6 +89,9 @@ struct dmub_srv; DMUB_SR(DMCUB_REGION5_OFFSET) \ DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \ DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \ + DMUB_SR(DMCUB_REGION6_OFFSET) \ + DMUB_SR(DMCUB_REGION6_OFFSET_HIGH) \ + DMUB_SR(DMCUB_REGION6_TOP_ADDRESS) \ DMUB_SR(DMCUB_SCRATCH0) \ DMUB_SR(DMCUB_SCRATCH1) \ DMUB_SR(DMCUB_SCRATCH2) \ @@ -155,6 +158,8 @@ struct dmub_srv; DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \ DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \ DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \ + DMUB_SF(DMCUB_REGION6_TOP_ADDRESS, DMCUB_REGION6_TOP_ADDRESS) \ + DMUB_SF(DMCUB_REGION6_TOP_ADDRESS, DMCUB_REGION6_ENABLE) \ DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \ DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \ DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \ @@ -162,7 +167,8 @@ struct dmub_srv; DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR) \ DMUB_SF(DMCUB_REGION3_TMR_AXI_SPACE, DMCUB_REGION3_TMR_AXI_SPACE) \ DMUB_SF(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN) \ - DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK) + DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK) \ + DMUB_SF(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS) struct dmub_srv_dcn32_reg_offset { #define DMUB_SR(reg) uint32_t reg; From 6f5d2c0691568394a2b6bb855e779e585e6f1c1f Mon Sep 17 00:00:00 2001 From: Wesley Chalmers Date: Tue, 2 Sep 2025 21:47:39 -0400 Subject: [PATCH 1957/2653] drm/amd/display: Rename header file link.h to link_service.h [WHY] Header file name "link.h" collides with system header when dc is compiled as a user-mode library [WHAT] Rename link.h to link_service.h to avoid name collision Reviewed-by: Alvin Lee Signed-off-by: Wesley Chalmers Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c | 2 +- drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 2 +- .../gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 2 +- .../gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c | 2 +- .../gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 2 +- .../gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c | 2 +- .../gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +- .../gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 2 +- .../gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c | 3 ++- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c | 2 +- .../gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c | 2 +- .../gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c | 2 +- .../drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c | 2 +- .../amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c | 2 +- .../drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c | 2 +- .../drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c | 2 +- .../amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c | 2 +- drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 3 +-- drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +- drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 2 +- drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c | 2 +- drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c | 2 +- drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 2 +- .../gpu/drm/amd/display/dc/inc/{link.h => link_service.h} | 6 +++--- .../gpu/drm/amd/display/dc/link/accessories/link_dp_cts.h | 2 +- .../gpu/drm/amd/display/dc/link/accessories/link_dp_trace.h | 2 +- drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h | 2 +- .../dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h | 2 +- drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h | 2 +- .../dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h | 2 +- drivers/gpu/drm/amd/display/dc/link/link_detection.h | 2 +- drivers/gpu/drm/amd/display/dc/link/link_dpms.h | 2 +- drivers/gpu/drm/amd/display/dc/link/link_factory.h | 2 +- drivers/gpu/drm/amd/display/dc/link/link_resource.h | 2 +- drivers/gpu/drm/amd/display/dc/link/link_validation.h | 2 +- drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h | 2 +- .../drm/amd/display/dc/link/protocols/link_dp_capability.h | 2 +- .../gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.h | 2 +- .../gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h | 2 +- .../drm/amd/display/dc/link/protocols/link_dp_irq_handler.h | 2 +- drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h | 2 +- .../drm/amd/display/dc/link/protocols/link_dp_training.h | 2 +- drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.h | 2 +- .../amd/display/dc/link/protocols/link_edp_panel_control.h | 2 +- drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.h | 2 +- .../drm/amd/display/dc/resource/dce120/dce120_resource.c | 2 +- .../gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 2 +- .../gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c | 2 +- .../drm/amd/display/dc/resource/dcn302/dcn302_resource.c | 3 ++- .../drm/amd/display/dc/resource/dcn303/dcn303_resource.c | 2 +- .../gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c | 2 +- .../drm/amd/display/dc/resource/dcn321/dcn321_resource.c | 2 +- .../gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 2 +- .../drm/amd/display/dc/resource/dcn351/dcn351_resource.c | 2 +- .../gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c | 2 +- .../drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 2 +- 69 files changed, 73 insertions(+), 72 deletions(-) rename drivers/gpu/drm/amd/display/dc/inc/{link.h => link_service.h} (98%) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c index 82ea3fe5e764f..80704d709e44a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c @@ -31,7 +31,7 @@ #include "amdgpu_dm.h" #include "modules/power/power_helpers.h" #include "dmub/inc/dmub_cmd.h" -#include "dc/inc/link.h" +#include "dc/inc/link_service.h" /* * amdgpu_dm_link_supports_replay() - check if the link supports replay diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index 4071851f9e86d..15cf13ec53026 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -28,7 +28,7 @@ #include "dccg.h" #include "clk_mgr_internal.h" #include "dc_state_priv.h" -#include "link.h" +#include "link_service.h" #include "dce100/dce_clk_mgr.h" #include "dce110/dce110_clk_mgr.h" diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c index bc123f1884da3..051052bd10c96 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c @@ -47,7 +47,7 @@ #include "dcn30/dcn30_clk_mgr.h" #include "dc_dmub_srv.h" -#include "link.h" +#include "link_service.h" #include "logger_types.h" diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c index 91d872d6d392b..790bbd8235b14 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c @@ -48,7 +48,7 @@ #include "dcn31/dcn31_clk_mgr.h" #include "dc_dmub_srv.h" -#include "link.h" +#include "link_service.h" #include "dcn314_smu.h" diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c index e4d22f74f9869..b315ed91e010b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c @@ -46,7 +46,7 @@ #define DC_LOGGER \ clk_mgr->base.base.ctx->logger -#include "link.h" +#include "link_service.h" #define TO_CLK_MGR_DCN315(clk_mgr)\ container_of(clk_mgr, struct clk_mgr_dcn315, base) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c index 49efea0c8fcff..1769b1f26e757 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c @@ -39,7 +39,7 @@ #include "dcn316_smu.h" #include "dm_helpers.h" #include "dc_dmub_srv.h" -#include "link.h" +#include "link_service.h" // DCN316 this is CLK1 instance #define MAX_INSTANCE 7 diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 8376e2b0e73dd..7da7b41bd0925 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -33,7 +33,7 @@ #include "reg_helper.h" #include "core_types.h" #include "dm_helpers.h" -#include "link.h" +#include "link_service.h" #include "dc_state_priv.h" #include "atomfirmware.h" #include "dcn32_smu13_driver_if.h" diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index bb1ac12a2b095..86edf11b8c5a8 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -44,7 +44,7 @@ #include "dcn31/dcn31_clk_mgr.h" #include "dc_dmub_srv.h" -#include "link.h" +#include "link_service.h" #include "logger_types.h" #undef DC_LOGGER diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c index 47ff4c965d767..47461f249e83b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c @@ -13,7 +13,7 @@ #include "reg_helper.h" #include "core_types.h" #include "dm_helpers.h" -#include "link.h" +#include "link_service.h" #include "dc_state_priv.h" #include "atomfirmware.h" diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 957544bd04fb4..ff01d36e06630 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -60,7 +60,7 @@ #include "link_encoder.h" #include "link_enc_cfg.h" -#include "link.h" +#include "link_service.h" #include "dm_helpers.h" #include "mem_input.h" diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c index 814f68d76257a..a180f68f711c2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c @@ -24,7 +24,7 @@ #include "link_enc_cfg.h" #include "resource.h" -#include "link.h" +#include "link_service.h" #define DC_LOGGER dc->ctx->logger diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c index b7a5de4ecb61e..9acd300197173 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c @@ -33,8 +33,9 @@ * dc.h with detail interface documentation, then add function implementation * in this file which calls link functions. */ -#include "link.h" +#include "link_service.h" #include "dce/dce_i2c.h" + struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index) { if (link_index >= MAX_LINKS) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index d712548b1927d..89c805457ed89 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -40,7 +40,7 @@ #include "virtual/virtual_stream_encoder.h" #include "dpcd_defs.h" #include "link_enc_cfg.h" -#include "link.h" +#include "link_service.h" #include "clk_mgr.h" #include "dc_state_priv.h" #include "dc_stream_priv.h" diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c index 65b979617b0cf..9e2a473a88521 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c @@ -3,7 +3,7 @@ // Copyright 2024 Advanced Micro Devices, Inc. #include "dc.h" -#include "link.h" +#include "link_service.h" #include "dc_dmub_srv.h" #include "dmub/dmub_srv.h" #include "core_types.h" diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c index 22e66b375a7fe..d928b4dcf6b81 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c @@ -28,7 +28,7 @@ #include "dcn10_stream_encoder.h" #include "reg_helper.h" #include "hw_shared.h" -#include "link.h" +#include "link_service.h" #include "dpcd_defs.h" #include "dcn30/dcn30_afmt.h" diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c index 1953c56367d32..c29c8f33d2167 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c @@ -29,7 +29,7 @@ #include "dcn20_stream_encoder.h" #include "reg_helper.h" #include "hw_shared.h" -#include "link.h" +#include "link_service.h" #include "dpcd_defs.h" #define DC_LOGGER \ diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c index 9a92f73d5b7fe..84cc2ddc52fe8 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c @@ -37,7 +37,7 @@ #include "link_enc_cfg.h" #include "dc_dmub_srv.h" #include "dal_asic_id.h" -#include "link.h" +#include "link_service.h" #define CTX \ enc10->base.ctx diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c index 1153caa60d5b7..20fbddf074c50 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c @@ -30,7 +30,7 @@ #include "dcn314_dio_stream_encoder.h" #include "reg_helper.h" #include "hw_shared.h" -#include "link.h" +#include "link_service.h" #include "dpcd_defs.h" #define DC_LOGGER \ diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c index 1a9bb614c41e0..3523d1cdc1a35 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c @@ -29,7 +29,7 @@ #include "dcn32_dio_stream_encoder.h" #include "reg_helper.h" #include "hw_shared.h" -#include "link.h" +#include "link_service.h" #include "dpcd_defs.h" #define DC_LOGGER \ diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c index 6f30b6cc3c761..fd5d1dbf9dc6c 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c @@ -29,7 +29,7 @@ #include "dcn35_dio_stream_encoder.h" #include "reg_helper.h" #include "hw_shared.h" -#include "link.h" +#include "link_service.h" #include "dpcd_defs.h" #define DC_LOGGER \ diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c index d5fa551dd3c96..99aab70ef3e11 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c @@ -32,7 +32,7 @@ #include "dcn401_dio_stream_encoder.h" #include "reg_helper.h" #include "hw_shared.h" -#include "link.h" +#include "link_service.h" #include "dpcd_defs.h" #define DC_LOGGER \ diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index 2a2eaf6adf26c..7aaf13bbd4e4c 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -30,8 +30,7 @@ #include "dcn20/dcn20_resource.h" #include "dcn21/dcn21_resource.h" #include "clk_mgr/dcn21/rn_clk_mgr.h" - -#include "link.h" +#include "link_service.h" #include "dcn20_fpu.h" #include "dc_state_priv.h" diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index 18388fb00be8c..8a0f128722b05 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -31,7 +31,7 @@ // We need this includes for WATERMARKS_* defines #include "clk_mgr/dcn32/dcn32_smu13_driver_if.h" #include "dcn30/dcn30_resource.h" -#include "link.h" +#include "link_service.h" #include "dc_state_priv.h" #define DC_LOGGER_INIT(logger) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c index 5d73efa2f0c90..c9dd920744c92 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c @@ -31,7 +31,7 @@ #include "dml/dcn31/dcn31_fpu.h" #include "dml/dml_inline_defs.h" -#include "link.h" +#include "link_service.h" #define DC_LOGGER_INIT(logger) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c index 6f516af829564..8cda18ce1a760 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c @@ -10,7 +10,7 @@ #include "dml/dcn35/dcn35_fpu.h" #include "dml/dml_inline_defs.h" -#include "link.h" +#include "link_service.h" #define DC_LOGGER_INIT(logger) diff --git a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c index 1313a7c5d87bf..73a1e6a037192 100644 --- a/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c +++ b/drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c @@ -28,7 +28,7 @@ #include "include/hdcp_msg_types.h" #include "include/signal_types.h" #include "core_types.h" -#include "link.h" +#include "link_service.h" #include "link_hwss.h" #include "link/protocols/link_dpcd.h" diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 153d68375fa3a..ea904d52af208 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -48,7 +48,7 @@ #include "link_encoder.h" #include "link_enc_cfg.h" #include "link_hwss.h" -#include "link.h" +#include "link_service.h" #include "dccg.h" #include "clock_source.h" #include "clk_mgr.h" diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 506c3bbbf221c..74f5e05f9cb43 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -55,7 +55,7 @@ #include "dce/dmub_hw_lock_mgr.h" #include "dc_trace.h" #include "dce/dmub_outbox.h" -#include "link.h" +#include "link_service.h" #include "dc_state_priv.h" #define DC_LOGGER \ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index cc377fcda6ff9..417f2679723ee 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -54,7 +54,7 @@ #include "dpcd_defs.h" #include "inc/link_enc_cfg.h" #include "link_hwss.h" -#include "link.h" +#include "link_service.h" #include "dc_state_priv.h" #define DC_LOGGER \ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c index 61efb15572ff0..e2269211553ce 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c @@ -35,7 +35,7 @@ #include "hw/clk_mgr.h" #include "dc_dmub_srv.h" #include "abm.h" -#include "link.h" +#include "link_service.h" #define DC_LOGGER_INIT(logger) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index 139a63101488d..e47ed5571dfdd 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -50,7 +50,7 @@ #include "dpcd_defs.h" #include "dcn20/dcn20_hwseq.h" #include "dcn30/dcn30_resource.h" -#include "link.h" +#include "link_service.h" #include "dc_state_priv.h" diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index 71d04e6015808..7b85a2b9fefa9 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -45,7 +45,7 @@ #include "link_hwss.h" #include "dpcd_defs.h" #include "dce/dmub_outbox.h" -#include "link.h" +#include "link_service.h" #include "dcn10/dcn10_hwseq.h" #include "dcn21/dcn21_hwseq.h" #include "inc/link_enc_cfg.h" diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c index 5609845339505..f925f669f2a4d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c @@ -46,7 +46,7 @@ #include "link_hwss.h" #include "dpcd_defs.h" #include "dce/dmub_outbox.h" -#include "link.h" +#include "link_service.h" #include "dcn10/dcn10_hwseq.h" #include "inc/link_enc_cfg.h" #include "dcn30/dcn30_vpg.h" diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index 52a8d928458a5..3e34d24edcebf 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -49,7 +49,7 @@ #include "dcn20/dcn20_optc.h" #include "dce/dmub_hw_lock_mgr.h" #include "dcn32/dcn32_resource.h" -#include "link.h" +#include "link_service.h" #include "../dcn20/dcn20_hwseq.h" #include "dc_state_priv.h" diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 764eff6a4ec6b..05011061822cf 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -46,7 +46,7 @@ #include "link_hwss.h" #include "dpcd_defs.h" #include "dce/dmub_outbox.h" -#include "link.h" +#include "link_service.h" #include "dcn10/dcn10_hwseq.h" #include "inc/link_enc_cfg.h" #include "dcn30/dcn30_vpg.h" diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index d5b5e2ce6ff63..9956145e3d184 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -25,7 +25,7 @@ #include "dpcd_defs.h" #include "clk_mgr.h" #include "dsc.h" -#include "link.h" +#include "link_service.h" #include "dce/dmub_hw_lock_mgr.h" #include "dcn10/dcn10_cm_common.h" diff --git a/drivers/gpu/drm/amd/display/dc/inc/link.h b/drivers/gpu/drm/amd/display/dc/inc/link_service.h similarity index 98% rename from drivers/gpu/drm/amd/display/dc/inc/link.h rename to drivers/gpu/drm/amd/display/dc/inc/link_service.h index c51665f34074d..140812c637b92 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/link.h +++ b/drivers/gpu/drm/amd/display/dc/inc/link_service.h @@ -42,8 +42,8 @@ * dc_link_exports.c or other dc files implement dc.h * * DC to Link: - * dc_link_exports.c or other dc files include link.h - * link_factory.c implements link.h + * dc_link_exports.c or other dc files include link_service.h + * link_factory.c implements link_service.h * * Link sub-component to Link sub-component: * link_factory.c includes --> link_xxx.h @@ -73,7 +73,7 @@ * 2. Implement your function in the suitable link_xxx.c file. * 3. Assign the function to link_service in link_factory.c * 4. NEVER include link_xxx.h headers outside link component. - * 5. NEVER include link.h on DM side. + * 5. NEVER include link_service.h on DM side. */ #include "core_types.h" diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.h b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.h index eae23ea7f6eca..033650cdb8116 100644 --- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.h +++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.h @@ -24,7 +24,7 @@ */ #ifndef __LINK_DP_CTS_H__ #define __LINK_DP_CTS_H__ -#include "link.h" +#include "link_service.h" void dp_handle_automated_test(struct dc_link *link); bool dp_set_test_pattern( struct dc_link *link, diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.h b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.h index ab437a0c9101e..9ff4a6c46a2b7 100644 --- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.h +++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_trace.h @@ -24,7 +24,7 @@ */ #ifndef __LINK_DP_TRACE_H__ #define __LINK_DP_TRACE_H__ -#include "link.h" +#include "link_service.h" void dp_trace_init(struct dc_link *link); void dp_trace_reset(struct dc_link *link); diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h index 45f0e091fcb01..4a25210a344fd 100644 --- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h +++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.h @@ -27,7 +27,7 @@ #define __LINK_HWSS_DIO_H__ #include "link_hwss.h" -#include "link.h" +#include "link_service.h" const struct link_hwss *get_dio_link_hwss(void); bool can_use_dio_link_hwss(const struct dc_link *link, diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h index 9ac08a3325402..cf578a8662a48 100644 --- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h +++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h @@ -25,7 +25,7 @@ #ifndef __LINK_HWSS_DIO_FIXED_VS_PE_RETIMER_H__ #define __LINK_HWSS_DIO_FIXED_VS_PE_RETIMER_H__ -#include "link.h" +#include "link_service.h" uint32_t dp_dio_fixed_vs_pe_retimer_get_lttpr_write_address(struct dc_link *link); uint8_t dp_dio_fixed_vs_pe_retimer_lane_cfg_to_hw_cfg(struct dc_link *link); diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h index 1d3ed8ca83b55..7c9005bc25874 100644 --- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h +++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.h @@ -26,7 +26,7 @@ #define __LINK_HWSS_HPO_DP_H__ #include "link_hwss.h" -#include "link.h" +#include "link_service.h" void set_hpo_dp_throttled_vcp_size(struct pipe_ctx *pipe_ctx, struct fixed31_32 throttled_vcp_size); diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h index 82301187bc7cf..8bf36827ecfb2 100644 --- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h +++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h @@ -25,7 +25,7 @@ #ifndef __LINK_HWSS_HPO_FIXED_VS_PE_RETIMER_DP_H__ #define __LINK_HWSS_HPO_FIXED_VS_PE_RETIMER_DP_H__ -#include "link.h" +#include "link_service.h" bool requires_fixed_vs_pe_retimer_hpo_link_hwss(const struct dc_link *link); const struct link_hwss *get_hpo_fixed_vs_pe_retimer_dp_link_hwss(void); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.h b/drivers/gpu/drm/amd/display/dc/link/link_detection.h index 7da05078721ef..1ab29476060b2 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.h +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.h @@ -25,7 +25,7 @@ #ifndef __DC_LINK_DETECTION_H__ #define __DC_LINK_DETECTION_H__ -#include "link.h" +#include "link_service.h" bool link_detect(struct dc_link *link, enum dc_detect_reason reason); bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type *type); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.h b/drivers/gpu/drm/amd/display/dc/link/link_dpms.h index 9398f9c1666a0..bd6fc63064a3b 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.h +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.h @@ -26,7 +26,7 @@ #ifndef __DC_LINK_DPMS_H__ #define __DC_LINK_DPMS_H__ -#include "link.h" +#include "link_service.h" void link_set_dpms_on( struct dc_state *state, struct pipe_ctx *pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.h b/drivers/gpu/drm/amd/display/dc/link/link_factory.h index e96220d48d03b..aad36ca1a31c4 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.h +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.h @@ -24,7 +24,7 @@ */ #ifndef __LINK_FACTORY_H__ #define __LINK_FACTORY_H__ -#include "link.h" +#include "link_service.h" struct dc_link *link_create(const struct link_init_data *init_params); void link_destroy(struct dc_link **link); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_resource.h b/drivers/gpu/drm/amd/display/dc/link/link_resource.h index 1907bda3cb6ee..f7aa3bc3a93ad 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_resource.h +++ b/drivers/gpu/drm/amd/display/dc/link/link_resource.h @@ -24,7 +24,7 @@ */ #ifndef __LINK_RESOURCE_H__ #define __LINK_RESOURCE_H__ -#include "link.h" +#include "link_service.h" void link_get_cur_res_map(const struct dc *dc, uint32_t *map); void link_restore_res_map(const struct dc *dc, uint32_t *map); void link_get_cur_link_res(const struct dc_link *link, diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.h b/drivers/gpu/drm/amd/display/dc/link/link_validation.h index 9553c81053fe1..595774e764536 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_validation.h +++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.h @@ -24,7 +24,7 @@ */ #ifndef __LINK_VALIDATION_H__ #define __LINK_VALIDATION_H__ -#include "link.h" +#include "link_service.h" enum dc_status link_validate_mode_timing( const struct dc_stream_state *stream, diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h index a3e25e55bed65..d3e6f01a6a90d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.h @@ -26,7 +26,7 @@ #ifndef __DAL_DDC_SERVICE_H__ #define __DAL_DDC_SERVICE_H__ -#include "link.h" +#include "link_service.h" #define AUX_POWER_UP_WA_DELAY 500 #define I2C_OVER_AUX_DEFER_WA_DELAY 70 diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h index 7170db5a1c13e..6e17f72a752f3 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h @@ -26,7 +26,7 @@ #ifndef __DC_LINK_DP_CAPABILITY_H__ #define __DC_LINK_DP_CAPABILITY_H__ -#include "link.h" +#include "link_service.h" bool detect_dp_sink_caps(struct dc_link *link); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.h index a61edfc9ca7aa..7cd03fa4892b3 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.h @@ -27,7 +27,7 @@ #ifndef __DC_LINK_DPIA_H__ #define __DC_LINK_DPIA_H__ -#include "link.h" +#include "link_service.h" /* Read tunneling device capability from DPCD and update link capability * accordingly. diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h index 41efcb3e44e2e..30cd8e2b9d355 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h @@ -26,7 +26,7 @@ #ifndef DC_INC_LINK_DP_DPIA_BW_H_ #define DC_INC_LINK_DP_DPIA_BW_H_ -#include "link.h" +#include "link_service.h" /* diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.h index ac33730fedd4c..87516fb3b45ae 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.h @@ -26,7 +26,7 @@ #ifndef __DC_LINK_DP_IRQ_HANDLER_H__ #define __DC_LINK_DP_IRQ_HANDLER_H__ -#include "link.h" +#include "link_service.h" bool dp_parse_link_loss_status( struct dc_link *link, union hpd_irq_data *hpd_irq_dpcd_data); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h index e3cbaf6726713..3d70e9bd4a81d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h @@ -26,7 +26,7 @@ #ifndef __DC_LINK_DP_PHY_H__ #define __DC_LINK_DP_PHY_H__ -#include "link.h" +#include "link_service.h" void dp_enable_link_phy( struct dc_link *link, const struct link_resource *link_res, diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h index 574b083e09369..ce52de22ab7a7 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h @@ -26,7 +26,7 @@ #ifndef __DC_LINK_DP_TRAINING_H__ #define __DC_LINK_DP_TRAINING_H__ -#include "link.h" +#include "link_service.h" bool perform_link_training_with_retries( const struct dc_link_settings *link_setting, diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.h index 08d787a1e4517..c2717c678c725 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dpcd.h @@ -25,7 +25,7 @@ #ifndef __LINK_DPCD_H__ #define __LINK_DPCD_H__ -#include "link.h" +#include "link_service.h" #include "dpcd_defs.h" enum dc_status core_link_read_dpcd( diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h index 4a475d5b9dde7..62a6344e613e3 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h @@ -25,7 +25,7 @@ #ifndef __DC_LINK_EDP_PANEL_CONTROL_H__ #define __DC_LINK_EDP_PANEL_CONTROL_H__ -#include "link.h" +#include "link_service.h" enum dp_panel_mode dp_get_panel_mode(struct dc_link *link); void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.h index 4fb526b264f97..af529328ba177 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.h @@ -26,7 +26,7 @@ #ifndef __DC_LINK_HPD_H__ #define __DC_LINK_HPD_H__ -#include "link.h" +#include "link_service.h" enum hpd_source_id get_hpd_line(struct dc_link *link); /* diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c index 2f23cc6df5711..540e04ec1e2d9 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c @@ -67,7 +67,7 @@ #include "reg_helper.h" #include "dce100/dce100_resource.h" -#include "link.h" +#include "link_service.h" #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index cce06057e9e7c..ac37088285464 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -85,7 +85,7 @@ #include "vm_helper.h" #include "link_enc_cfg.h" -#include "link.h" +#include "link_service.h" #define DC_LOGGER_INIT(logger) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c index 201ed863b69eb..ff63f59ff928a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c @@ -60,7 +60,7 @@ #include "dml/display_mode_vba.h" #include "dcn30/dcn30_dccg.h" #include "dcn10/dcn10_resource.h" -#include "link.h" +#include "link_service.h" #include "dce/dce_panel_cntl.h" #include "dcn30/dcn30_dwb.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c index 3345068a878c1..61623cb518d9c 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c @@ -47,7 +47,8 @@ #include "dcn10/dcn10_resource.h" -#include "link.h" +#include "link_service.h" + #include "dce/dce_abm.h" #include "dce/dce_audio.h" #include "dce/dce_aux.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c index 3479e1eab4cd7..02b9a84f2db3b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c @@ -47,7 +47,7 @@ #include "dcn10/dcn10_resource.h" -#include "link.h" +#include "link_service.h" #include "dce/dce_abm.h" #include "dce/dce_audio.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index 9917b366f00c6..4acd97b3e4c94 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -69,7 +69,7 @@ #include "dml/display_mode_vba.h" #include "dcn32/dcn32_dccg.h" #include "dcn10/dcn10_resource.h" -#include "link.h" +#include "link_service.h" #include "dcn31/dcn31_panel_cntl.h" #include "dcn30/dcn30_dwb.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c index 8d4b37265e725..b8410724a156c 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c @@ -72,7 +72,7 @@ #include "dml/display_mode_vba.h" #include "dcn32/dcn32_dccg.h" #include "dcn10/dcn10_resource.h" -#include "link.h" +#include "link_service.h" #include "dcn31/dcn31_panel_cntl.h" #include "dcn30/dcn30_dwb.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c index 1d1a002f6d54f..07552445e424f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c @@ -61,7 +61,7 @@ #include "dcn31/dcn31_hpo_dp_stream_encoder.h" #include "dcn31/dcn31_hpo_dp_link_encoder.h" #include "dcn32/dcn32_hpo_dp_link_encoder.h" -#include "link.h" +#include "link_service.h" #include "dcn31/dcn31_apg.h" #include "dcn32/dcn32_dio_link_encoder.h" #include "dcn31/dcn31_vpg.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c index 47912e0861a2b..cb0478a9a34da 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c @@ -40,7 +40,7 @@ #include "dcn31/dcn31_hpo_dp_stream_encoder.h" #include "dcn31/dcn31_hpo_dp_link_encoder.h" #include "dcn32/dcn32_hpo_dp_link_encoder.h" -#include "link.h" +#include "link_service.h" #include "dcn31/dcn31_apg.h" #include "dcn32/dcn32_dio_link_encoder.h" #include "dcn31/dcn31_vpg.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c index 9ba91e214ddaa..126090c9bb8a8 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c @@ -40,7 +40,7 @@ #include "dcn31/dcn31_hpo_dp_stream_encoder.h" #include "dcn31/dcn31_hpo_dp_link_encoder.h" #include "dcn32/dcn32_hpo_dp_link_encoder.h" -#include "link.h" +#include "link_service.h" #include "dcn31/dcn31_apg.h" #include "dcn32/dcn32_dio_link_encoder.h" #include "dcn31/dcn31_vpg.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 068c123ea8a8a..d498c0983d74f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -50,7 +50,7 @@ #include "dml/display_mode_vba.h" #include "dcn401/dcn401_dccg.h" #include "dcn10/dcn10_resource.h" -#include "link.h" +#include "link_service.h" #include "link_enc_cfg.h" #include "dcn31/dcn31_panel_cntl.h" From 46cd9c9016c31fd0795c54d571994ecf5547e5be Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Wed, 3 Sep 2025 15:00:22 -0400 Subject: [PATCH 1958/2653] drm/amd/display: limit one non-related log to dGPU [Why&How] some log are for dGPU only. Added check to limit log. Reviewed-by: Chris Park Signed-off-by: Charlene Liu Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index ff01d36e06630..8cab7cf900b18 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -5623,8 +5623,8 @@ void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, char const subvp_pipe_type[i] = dc_state_get_pipe_subvp_type(context, pipe); } } - - DC_LOG_DC("%s: allow_idle=%d\n HardMinUClk_Khz=%d HardMinDramclk_Khz=%d\n Pipe_0=%d Pipe_1=%d Pipe_2=%d Pipe_3=%d Pipe_4=%d Pipe_5=%d (caller=%s)\n", + if (!dc->caps.is_apu) + DC_LOG_DC("%s: allow_idle=%d\n HardMinUClk_Khz=%d HardMinDramclk_Khz=%d\n Pipe_0=%d Pipe_1=%d Pipe_2=%d Pipe_3=%d Pipe_4=%d Pipe_5=%d (caller=%s)\n", __func__, allow, idle_fclk_khz, idle_dramclk_khz, subvp_pipe_type[0], subvp_pipe_type[1], subvp_pipe_type[2], subvp_pipe_type[3], subvp_pipe_type[4], subvp_pipe_type[5], caller_name); From 3f3c992f7dcf981f318d14b488a1a59fc09c5dd3 Mon Sep 17 00:00:00 2001 From: Ausef Yousof Date: Tue, 2 Sep 2025 12:10:18 -0400 Subject: [PATCH 1959/2653] drm/amd/display: fix dml ms order of operations [why&how] small error in order of operations in immediateflipbytes calculation on dml ms side that can result in dml ms and mp mismatch immediateflip support for a given pipe and thus an invalid hw state, correct the order to align with mp. Reviewed-by: Leo Chen Signed-off-by: Ausef Yousof Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c index 715f9019a33e2..4b9b2e84d3811 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c @@ -6529,7 +6529,7 @@ static noinline_for_stack void dml_prefetch_check(struct display_mode_lib_st *mo mode_lib->ms.TotImmediateFlipBytes = 0; for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) { if (!(mode_lib->ms.policy.ImmediateFlipRequirement[k] == dml_immediate_flip_not_required)) { - mode_lib->ms.TotImmediateFlipBytes = mode_lib->ms.TotImmediateFlipBytes + mode_lib->ms.NoOfDPP[j][k] * mode_lib->ms.PDEAndMetaPTEBytesPerFrame[j][k] + mode_lib->ms.MetaRowBytes[j][k]; + mode_lib->ms.TotImmediateFlipBytes = mode_lib->ms.TotImmediateFlipBytes + mode_lib->ms.NoOfDPP[j][k] * (mode_lib->ms.PDEAndMetaPTEBytesPerFrame[j][k] + mode_lib->ms.MetaRowBytes[j][k]); if (mode_lib->ms.use_one_row_for_frame_flip[j][k]) { mode_lib->ms.TotImmediateFlipBytes = mode_lib->ms.TotImmediateFlipBytes + mode_lib->ms.NoOfDPP[j][k] * (2 * mode_lib->ms.DPTEBytesPerRow[j][k]); } else { From e553896e84f93b7c58c7464658db743a7e8b9346 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Tue, 26 Aug 2025 20:18:22 -0500 Subject: [PATCH 1960/2653] drm/amd/display: Set up pixel encoding for YCBCR422 [Why] fill_stream_properties_from_drm_display_mode() will not configure pixel encoding to YCBCR422 when the DRM color format supports YCBCR422 but not YCBCR420 or YCBCR4444. Instead it will fallback to RGB. [How] Add support for YCBCR422 in pixel encoding mapping. Suggested-by: Mauri Carvalho Reviewed-by: Wayne Lin Signed-off-by: Mario Limonciello Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1913874738578..26df31b233a2e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6536,6 +6536,9 @@ static void fill_stream_properties_from_drm_display_mode( && aconnector && aconnector->force_yuv420_output) timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; + else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR422) + && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) + timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR422; else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444) && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; From 69dccc7cb02cb4397666e4269610439bf338d880 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Wed, 27 Aug 2025 12:17:19 -0500 Subject: [PATCH 1961/2653] drm/amd/display: Add fallback path for YCBCR422 [Why] DP validation may fail with multiple displays and higher color depths. The sink may support others though. [How] When DP bandwidth validation fails, progressively fallback through: - YUV422 8bpc (bandwidth efficient) - YUV422 6bpc (reduced color depth) - YUV420 (last resort) This resolves cases where displays would show no image due to insufficient DP link bandwidth for the requested RGB mode. Suggested-by: Mauri Carvalho Reviewed-by: Wayne Lin Signed-off-by: Mario Limonciello Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 45 +++++++++++++++---- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + 2 files changed, 37 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 26df31b233a2e..3205e31b121ee 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6537,7 +6537,8 @@ static void fill_stream_properties_from_drm_display_mode( && aconnector->force_yuv420_output) timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR422) - && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) + && aconnector + && aconnector->force_yuv422_output) timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR422; else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444) && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) @@ -7865,6 +7866,7 @@ create_validate_stream_for_sink(struct drm_connector *connector, bpc_limit = 8; do { + drm_dbg_kms(connector->dev, "Trying with %d bpc\n", requested_bpc); stream = create_stream_for_sink(connector, drm_mode, dm_state, old_stream, requested_bpc); @@ -7900,16 +7902,41 @@ create_validate_stream_for_sink(struct drm_connector *connector, } while (stream == NULL && requested_bpc >= bpc_limit); - if ((dc_result == DC_FAIL_ENC_VALIDATE || - dc_result == DC_EXCEED_DONGLE_CAP) && - !aconnector->force_yuv420_output) { - DRM_DEBUG_KMS("%s:%d Retry forcing yuv420 encoding\n", - __func__, __LINE__); - - aconnector->force_yuv420_output = true; + switch (dc_result) { + /* + * If we failed to validate DP bandwidth stream with the requested RGB color depth, + * we try to fallback and configure in order: + * YUV422 (8bpc, 6bpc) + * YUV420 (8bpc, 6bpc) + */ + case DC_FAIL_ENC_VALIDATE: + case DC_EXCEED_DONGLE_CAP: + case DC_NO_DP_LINK_BANDWIDTH: + /* recursively entered twice and already tried both YUV422 and YUV420 */ + if (aconnector->force_yuv422_output && aconnector->force_yuv420_output) + break; + /* first failure; try YUV422 */ + if (!aconnector->force_yuv422_output) { + drm_dbg_kms(connector->dev, "%s:%d Validation failed with %d, retrying w/ YUV422\n", + __func__, __LINE__, dc_result); + aconnector->force_yuv422_output = true; + /* recursively entered and YUV422 failed, try YUV420 */ + } else if (!aconnector->force_yuv420_output) { + drm_dbg_kms(connector->dev, "%s:%d Validation failed with %d, retrying w/ YUV420\n", + __func__, __LINE__, dc_result); + aconnector->force_yuv420_output = true; + } stream = create_validate_stream_for_sink(connector, drm_mode, - dm_state, old_stream); + dm_state, old_stream); + aconnector->force_yuv422_output = false; aconnector->force_yuv420_output = false; + break; + case DC_OK: + break; + default: + drm_dbg_kms(connector->dev, "%s:%d Unhandled validation failure %d\n", + __func__, __LINE__, dc_result); + break; } return stream; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 90315bc290cd5..f975c163a79f8 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -805,6 +805,7 @@ struct amdgpu_dm_connector { bool fake_enable; bool force_yuv420_output; + bool force_yuv422_output; struct dsc_preferred_settings dsc_settings; union dp_downstream_port_present mst_downstream_port_present; /* Cached display modes */ From ed0c9e79c43ed8416265c80eef865be27b138cc1 Mon Sep 17 00:00:00 2001 From: Relja Vojvodic Date: Thu, 4 Sep 2025 15:38:24 -0400 Subject: [PATCH 1962/2653] drm/amd/display: Add DSC padding for OVT Support [Why] -Certain OVT timings require DSC configurations which divide the horizontal active unevenly across DSC slices -DSC slices must be even, so padding needs to be added to the active to make this possible -The pixel clock of the HW now needs to be increased to accommodate the extra padded pixels -To keep the line time the same, the blank of the HW timing needs to be increased as well [How] -Calculate h_active padding, h_total padding, and pixel clock based off of the original OVT timing and DSC calculations -Store these values in the pipe and program HW with these modifications -Added general support for cases where DSC slice config does not evenly split the horizontal active by fixing some slice width calculations -Updated PPS calculations for these cases Reviewed-by: Chris Park Reviewed-by: Wenjing Liu Signed-off-by: Relja Vojvodic Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dc/core/dc_resource.c | 35 +++++++--------- .../gpu/drm/amd/display/dc/dc_spl_translate.c | 2 +- .../dc/dml2/dml21/dml21_translation_helper.c | 41 ++++++++----------- .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 3 +- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 2 +- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 9 ++-- .../gpu/drm/amd/display/dc/inc/core_types.h | 10 ++++- .../gpu/drm/amd/display/dc/link/link_dpms.c | 2 +- .../dc/resource/dcn32/dcn32_resource.c | 2 +- .../dc/resource/dcn401/dcn401_resource.c | 3 ++ 10 files changed, 55 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 89c805457ed89..cbca3c67f439a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -95,7 +95,6 @@ #define DC_LOGGER \ dc->ctx->logger #define DC_LOGGER_INIT(logger) - #include "dml2/dml2_wrapper.h" #define UNABLE_TO_SPLIT -1 @@ -2149,7 +2148,7 @@ int resource_get_odm_slice_dst_width(struct pipe_ctx *otg_master, h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right + - otg_master->hblank_borrow; + otg_master->dsc_padding_params.dsc_hactive_padding; width = h_active / count; if (otg_master->stream_res.tg) @@ -4267,39 +4266,33 @@ enum dc_status dc_validate_with_context(struct dc *dc, return res; } +#if defined(CONFIG_DRM_AMD_DC_FP) +#endif /* CONFIG_DRM_AMD_DC_FP */ + /** - * decide_hblank_borrow - Decides the horizontal blanking borrow value for a given pipe context. + * calculate_timing_params_for_dsc_with_padding - Calculates timing parameters for DSC with padding. * @pipe_ctx: Pointer to the pipe context structure. * - * This function calculates the horizontal blanking borrow value for a given pipe context based on the + * This function calculates the timing parameters for a given pipe context based on the * display stream compression (DSC) configuration. If the horizontal active pixels (hactive) are less - * than the total width of the DSC slices, it sets the hblank_borrow value to the difference. If the - * total horizontal timing minus the hblank_borrow value is less than 32, it resets the hblank_borrow + * than the total width of the DSC slices, it sets the dsc_hactive_padding value to the difference. If the + * total horizontal timing minus the dsc_hactive_padding value is less than 32, it resets the dsc_hactive_padding * value to 0. */ -static void decide_hblank_borrow(struct pipe_ctx *pipe_ctx) +static void calculate_timing_params_for_dsc_with_padding(struct pipe_ctx *pipe_ctx) { - uint32_t hactive; - uint32_t ceil_slice_width; struct dc_stream_state *stream = NULL; if (!pipe_ctx) return; stream = pipe_ctx->stream; + pipe_ctx->dsc_padding_params.dsc_hactive_padding = 0; + pipe_ctx->dsc_padding_params.dsc_htotal_padding = 0; - if (stream->timing.flags.DSC) { - hactive = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; + if (stream) + pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz = stream->timing.pix_clk_100hz; - /* Assume if determined slices does not divide Hactive evenly, Hborrow is needed for padding*/ - if (hactive % stream->timing.dsc_cfg.num_slices_h != 0) { - ceil_slice_width = (hactive / stream->timing.dsc_cfg.num_slices_h) + 1; - pipe_ctx->hblank_borrow = ceil_slice_width * stream->timing.dsc_cfg.num_slices_h - hactive; - - if (stream->timing.h_total - hactive - pipe_ctx->hblank_borrow < 32) - pipe_ctx->hblank_borrow = 0; - } - } } /** @@ -4342,7 +4335,7 @@ enum dc_status dc_validate_global_state( /* Decide whether hblank borrow is needed and save it in pipe_ctx */ if (dc->debug.enable_hblank_borrow) - decide_hblank_borrow(pipe_ctx); + calculate_timing_params_for_dsc_with_padding(pipe_ctx); if (dc->res_pool->funcs->patch_unknown_plane_state && pipe_ctx->plane_state && diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c index 7f57661433eb5..55704d4457ef1 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c @@ -128,7 +128,7 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl spl_in->odm_slice_index = resource_get_odm_slice_index(pipe_ctx); // Make spl input basic out info output_size width point to stream h active spl_in->basic_out.output_size.width = - stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->hblank_borrow; + stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding; // Make spl input basic out info output_size height point to v active spl_in->basic_out.output_size.height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c index f6879e6222710..bf5e7f4e04167 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c @@ -84,25 +84,29 @@ static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stre static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cfg *timing, struct dc_stream_state *stream, + struct pipe_ctx *pipe_ctx, struct dml2_context *dml_ctx) { unsigned int hblank_start, vblank_start, min_hardware_refresh_in_uhz; + uint32_t pix_clk_100hz; - timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; + timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding; timing->v_active = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; timing->h_front_porch = stream->timing.h_front_porch; timing->v_front_porch = stream->timing.v_front_porch; timing->pixel_clock_khz = stream->timing.pix_clk_100hz / 10; + if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0) + timing->pixel_clock_khz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz / 10; if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) timing->pixel_clock_khz *= 2; - timing->h_total = stream->timing.h_total; + timing->h_total = stream->timing.h_total + pipe_ctx->dsc_padding_params.dsc_htotal_padding; timing->v_total = stream->timing.v_total; timing->h_sync_width = stream->timing.h_sync_width; timing->interlaced = stream->timing.flags.INTERLACE; hblank_start = stream->timing.h_total - stream->timing.h_front_porch; - timing->h_blank_end = hblank_start - stream->timing.h_addressable + timing->h_blank_end = hblank_start - stream->timing.h_addressable - pipe_ctx->dsc_padding_params.dsc_hactive_padding - stream->timing.h_border_left - stream->timing.h_border_right; if (hblank_start < stream->timing.h_addressable) @@ -121,8 +125,13 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf /* limit min refresh rate to DC cap */ min_hardware_refresh_in_uhz = stream->timing.min_refresh_in_uhz; if (stream->ctx->dc->caps.max_v_total != 0) { - min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL), - (stream->timing.h_total * (long long)calc_max_hardware_v_total(stream))); + if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0) { + pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz; + } else { + pix_clk_100hz = stream->timing.pix_clk_100hz; + } + min_hardware_refresh_in_uhz = div64_u64((pix_clk_100hz * 100000000ULL), + (timing->h_total * (long long)calc_max_hardware_v_total(stream))); } timing->drr_config.min_refresh_uhz = max(stream->timing.min_refresh_in_uhz, min_hardware_refresh_in_uhz); @@ -173,21 +182,6 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf timing->vblank_nom = timing->v_total - timing->v_active; } -/** - * adjust_dml21_hblank_timing_config_from_pipe_ctx - Adjusts the horizontal blanking timing configuration - * based on the pipe context. - * @timing: Pointer to the dml2_timing_cfg structure to be adjusted. - * @pipe: Pointer to the pipe_ctx structure containing the horizontal blanking borrow value. - * - * This function modifies the horizontal active and blank end timings by adding and subtracting - * the horizontal blanking borrow value from the pipe context, respectively. - */ -static void adjust_dml21_hblank_timing_config_from_pipe_ctx(struct dml2_timing_cfg *timing, struct pipe_ctx *pipe) -{ - timing->h_active += pipe->hblank_borrow; - timing->h_blank_end -= pipe->hblank_borrow; -} - static void populate_dml21_output_config_from_stream_state(struct dml2_link_output_cfg *output, struct dc_stream_state *stream, const struct pipe_ctx *pipe) { @@ -487,7 +481,9 @@ static const struct scaler_data *get_scaler_data_for_plane( temp_pipe->plane_state = pipe->plane_state; temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps; temp_pipe->stream_res = pipe->stream_res; - temp_pipe->hblank_borrow = pipe->hblank_borrow; + temp_pipe->dsc_padding_params.dsc_hactive_padding = pipe->dsc_padding_params.dsc_hactive_padding; + temp_pipe->dsc_padding_params.dsc_htotal_padding = pipe->dsc_padding_params.dsc_htotal_padding; + temp_pipe->dsc_padding_params.dsc_pix_clk_100hz = pipe->dsc_padding_params.dsc_pix_clk_100hz; dml_ctx->config.callbacks.build_scaling_params(temp_pipe); break; } @@ -755,8 +751,7 @@ bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_s disp_cfg_stream_location = dml_dispcfg->num_streams++; ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__); - populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index], dml_ctx); - adjust_dml21_hblank_timing_config_from_pipe_ctx(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, &context->res_ctx.pipe_ctx[stream_index]); + populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index], dml_ctx); populate_dml21_output_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].output, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index]); populate_dml21_stream_overrides_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location], context->streams[stream_index], &context->stream_status[stream_index]); diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c index 58f44309058eb..b7495777c58de 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c @@ -408,9 +408,10 @@ bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1; dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0; + // Need to find the ceiling value for the slice width + dsc_reg_vals->pps.slice_width = (dsc_cfg->pic_width + dsc_cfg->dc_dsc_cfg.num_slices_h - 1) / dsc_cfg->dc_dsc_cfg.num_slices_h; // TODO: in addition to validating slice height (pic height must be divisible by slice height), // see what happens when the same condition doesn't apply for slice_width/pic_width. - dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index 3e34d24edcebf..d4d8d03efbd64 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -1051,7 +1051,7 @@ void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) } /* Enable DSC hw block */ - dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->hblank_borrow + + dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 9956145e3d184..1b0b772fc5dd9 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -810,9 +810,12 @@ enum dc_status dcn401_enable_stream_timing( if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); - /* if we are borrowing from hblank, h_addressable needs to be adjusted */ - if (dc->debug.enable_hblank_borrow) - patched_crtc_timing.h_addressable = patched_crtc_timing.h_addressable + pipe_ctx->hblank_borrow; + /* if we are padding, h_addressable needs to be adjusted */ + if (dc->debug.enable_hblank_borrow) { + patched_crtc_timing.h_addressable = patched_crtc_timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding; + patched_crtc_timing.h_total = patched_crtc_timing.h_total + pipe_ctx->dsc_padding_params.dsc_htotal_padding; + patched_crtc_timing.pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz; + } pipe_ctx->stream_res.tg->funcs->program_timing( pipe_ctx->stream_res.tg, diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index b3f486a4d7819..4673697f01dcd 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -436,6 +436,13 @@ enum p_state_switch_method { P_STATE_V_BLANK_SUB_VP, }; +struct dsc_padding_params { + /* pixels borrowed from hblank to hactive */ + uint8_t dsc_hactive_padding; + uint32_t dsc_htotal_padding; + uint32_t dsc_pix_clk_100hz; +}; + struct pipe_ctx { struct dc_plane_state *plane_state; struct dc_stream_state *stream; @@ -493,8 +500,7 @@ struct pipe_ctx { /* subvp_index: only valid if the pipe is a SUBVP_MAIN*/ uint8_t subvp_index; struct pixel_rate_divider pixel_rate_divider; - /* pixels borrowed from hblank to hactive */ - uint8_t hblank_borrow; + struct dsc_padding_params dsc_padding_params; /* next vupdate */ uint32_t next_vupdate; uint32_t wait_frame_count; diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index cc78710cc8078..5ff6a0849c4d8 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -832,7 +832,7 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) enum optc_dsc_mode optc_dsc_mode; /* Enable DSC hw block */ - dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->hblank_borrow + + dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index 4acd97b3e4c94..8f80ccb846d76 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -2852,7 +2852,7 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head( free_pipe->plane_res.xfm = pool->transforms[free_pipe_idx]; free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx]; free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst; - free_pipe->hblank_borrow = otg_master->hblank_borrow; + free_pipe->dsc_padding_params = otg_master->dsc_padding_params; if (free_pipe->stream->timing.flags.DSC == 1) { dcn20_acquire_dsc(free_pipe->stream->ctx->dc, &new_ctx->res_ctx, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index d498c0983d74f..1d18807e47495 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -1699,6 +1699,9 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; + if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0) + pixel_clk_params->requested_pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz; + if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment) link_enc = link_enc_cfg_get_link_enc(link); if (link_enc) From 2d2964cec65c853e749a7b19faf798907e3f5313 Mon Sep 17 00:00:00 2001 From: Martin Leung Date: Wed, 6 Aug 2025 17:40:55 -0400 Subject: [PATCH 1963/2653] Revert "drm/amd/display: Reduce Stack Usage by moving 'audio_output' into 'stream_res' v4" This reverts commit 571662266db3 ("drm/amd/display: Reduce Stack Usage by moving 'audio_output' into 'stream_res' v4") Reason for revert: Causes DP compliance errors Acked-by: Wayne Lin Signed-off-by: Martin Leung Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 32 +++++++++++-------- .../gpu/drm/amd/display/dc/inc/core_types.h | 5 ++- .../display/dc/link/accessories/link_dp_cts.c | 13 ++++---- .../dc/resource/dcn31/dcn31_resource.c | 5 +-- .../dc/resource/dcn31/dcn31_resource.h | 3 +- 5 files changed, 31 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index ea904d52af208..7b4a04704312d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -1601,17 +1601,19 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw( } if (pipe_ctx->stream_res.audio != NULL) { - build_audio_output(context, pipe_ctx, &pipe_ctx->stream_res.audio_output); + struct audio_output audio_output = {0}; - link_hwss->setup_audio_output(pipe_ctx, &pipe_ctx->stream_res.audio_output, + build_audio_output(context, pipe_ctx, &audio_output); + + link_hwss->setup_audio_output(pipe_ctx, &audio_output, pipe_ctx->stream_res.audio->inst); pipe_ctx->stream_res.audio->funcs->az_configure( pipe_ctx->stream_res.audio, pipe_ctx->stream->signal, - &pipe_ctx->stream_res.audio_output.crtc_info, + &audio_output.crtc_info, &pipe_ctx->stream->audio_info, - &pipe_ctx->stream_res.audio_output.dp_link_info); + &audio_output.dp_link_info); if (dc->config.disable_hbr_audio_dp2) if (pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio && @@ -2385,7 +2387,9 @@ static void dce110_setup_audio_dto( if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) continue; if (pipe_ctx->stream_res.audio != NULL) { - build_audio_output(context, pipe_ctx, &pipe_ctx->stream_res.audio_output); + struct audio_output audio_output; + + build_audio_output(context, pipe_ctx, &audio_output); if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { struct dtbclk_dto_params dto_params = {0}; @@ -2396,14 +2400,14 @@ static void dce110_setup_audio_dto( pipe_ctx->stream_res.audio->funcs->wall_dto_setup( pipe_ctx->stream_res.audio, pipe_ctx->stream->signal, - &pipe_ctx->stream_res.audio_output.crtc_info, - &pipe_ctx->stream_res.audio_output.pll_info); + &audio_output.crtc_info, + &audio_output.pll_info); } else pipe_ctx->stream_res.audio->funcs->wall_dto_setup( pipe_ctx->stream_res.audio, pipe_ctx->stream->signal, - &pipe_ctx->stream_res.audio_output.crtc_info, - &pipe_ctx->stream_res.audio_output.pll_info); + &audio_output.crtc_info, + &audio_output.pll_info); break; } } @@ -2423,15 +2427,15 @@ static void dce110_setup_audio_dto( continue; if (pipe_ctx->stream_res.audio != NULL) { - build_audio_output(context, - pipe_ctx, - &pipe_ctx->stream_res.audio_output); + struct audio_output audio_output = {0}; + + build_audio_output(context, pipe_ctx, &audio_output); pipe_ctx->stream_res.audio->funcs->wall_dto_setup( pipe_ctx->stream_res.audio, pipe_ctx->stream->signal, - &pipe_ctx->stream_res.audio_output.crtc_info, - &pipe_ctx->stream_res.audio_output.pll_info); + &audio_output.crtc_info, + &audio_output.pll_info); break; } } diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 4673697f01dcd..a74d753dce819 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -227,7 +227,8 @@ struct resource_funcs { enum dc_status (*update_dc_state_for_encoder_switch)(struct dc_link *link, struct dc_link_settings *link_setting, uint8_t pipe_count, - struct pipe_ctx *pipes); + struct pipe_ctx *pipes, + struct audio_output *audio_output); }; struct audio_support{ @@ -359,8 +360,6 @@ struct stream_resource { uint8_t gsl_group; struct test_pattern_params test_pattern_params; - - struct audio_output audio_output; }; struct plane_resource { diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c index 23f41c99fa38c..9e33bf937a692 100644 --- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c +++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c @@ -75,7 +75,7 @@ static void dp_retrain_link_dp_test(struct dc_link *link, bool is_hpo_acquired; uint8_t count; int i; - + struct audio_output audio_output[MAX_PIPES]; struct dc_stream_state *streams_on_link[MAX_PIPES]; int num_streams_on_link = 0; @@ -101,7 +101,7 @@ static void dp_retrain_link_dp_test(struct dc_link *link, if (needs_divider_update && link->dc->res_pool->funcs->update_dc_state_for_encoder_switch) { link->dc->res_pool->funcs->update_dc_state_for_encoder_switch(link, link_setting, count, - *pipes); + *pipes, &audio_output[0]); for (i = 0; i < count; i++) { pipes[i]->clock_source->funcs->program_pix_clk( pipes[i]->clock_source, @@ -113,16 +113,15 @@ static void dp_retrain_link_dp_test(struct dc_link *link, const struct link_hwss *link_hwss = get_link_hwss( link, &pipes[i]->link_res); - link_hwss->setup_audio_output(pipes[i], - &pipes[i]->stream_res.audio_output, - pipes[i]->stream_res.audio->inst); + link_hwss->setup_audio_output(pipes[i], &audio_output[i], + pipes[i]->stream_res.audio->inst); pipes[i]->stream_res.audio->funcs->az_configure( pipes[i]->stream_res.audio, pipes[i]->stream->signal, - &pipes[i]->stream_res.audio_output.crtc_info, + &audio_output[i].crtc_info, &pipes[i]->stream->audio_info, - &pipes[i]->stream_res.audio_output.dp_link_info); + &audio_output[i].dp_link_info); if (link->dc->config.disable_hbr_audio_dp2 && pipes[i]->stream_res.audio->funcs->az_disable_hbr_audio && diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c index ca17e5d8fdc2a..3ed7f50554e21 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c @@ -2239,7 +2239,8 @@ struct resource_pool *dcn31_create_resource_pool( enum dc_status dcn31_update_dc_state_for_encoder_switch(struct dc_link *link, struct dc_link_settings *link_setting, uint8_t pipe_count, - struct pipe_ctx *pipes) + struct pipe_ctx *pipes, + struct audio_output *audio_output) { struct dc_state *state = link->dc->current_state; int i; @@ -2254,7 +2255,7 @@ enum dc_status dcn31_update_dc_state_for_encoder_switch(struct dc_link *link, // Setup audio if (pipes[i].stream_res.audio != NULL) - build_audio_output(state, &pipes[i], &pipes[i].stream_res.audio_output); + build_audio_output(state, &pipes[i], &audio_output[i]); } #else /* This DCN requires rate divider updates and audio reprogramming to allow DP1<-->DP2 link rate switching, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h index 7e8fde65528f1..c32c85ef0ba47 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h @@ -69,7 +69,8 @@ unsigned int dcn31_get_det_buffer_size( enum dc_status dcn31_update_dc_state_for_encoder_switch(struct dc_link *link, struct dc_link_settings *link_setting, uint8_t pipe_count, - struct pipe_ctx *pipes); + struct pipe_ctx *pipes, + struct audio_output *audio_output); /*temp: B0 specific before switch to dcn313 headers*/ #ifndef regPHYPLLF_PIXCLK_RESYNC_CNTL From dcbdfce9f1897a53c898809789f8de30a1b9e177 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Sun, 7 Sep 2025 18:55:39 -0400 Subject: [PATCH 1964/2653] drm/amd/display: Promote DC to 3.2.350 This version brings along following updates: - Add DSC padding for OVT support - Setup pixel encoding for YCBCR422 - Fix dml ms order - Rename header file link.h to link_service.h - Fix DMUB loading sequence - Modify link training policy Signed-off-by: Taimur Hassan Acked-by: Wayne Lin Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 2e497877977bc..6d3eec3adb3db 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.349" +#define DC_VER "3.2.350" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From 89c4cc50a5529891d713fa777612a03edacb4805 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Thu, 21 Aug 2025 16:05:42 +0800 Subject: [PATCH 1965/2653] drm/amdgpu: wait pmfw polling mca bank info done wait 500ms to ensure pmfw polling mca bank info done. Signed-off-by: Stanley.Yang Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 53b8e3fc41683..3ea11b945fc0b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2716,6 +2716,7 @@ static void amdgpu_ras_do_recovery(struct work_struct *work) struct amdgpu_device *adev = ras->adev; struct list_head device_list, *device_list_handle = NULL; struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); + unsigned int error_query_mode; enum ras_event_type type; if (hive) { @@ -2744,6 +2745,13 @@ static void amdgpu_ras_do_recovery(struct work_struct *work) device_list_handle = &device_list; } + if (amdgpu_ras_get_error_query_mode(adev, &error_query_mode)) { + if (error_query_mode == AMDGPU_RAS_FIRMWARE_ERROR_QUERY) { + /* wait 500ms to ensure pmfw polling mca bank info done */ + msleep(500); + } + } + type = amdgpu_ras_get_fatal_error_event(adev); list_for_each_entry(remote_adev, device_list_handle, gmc.xgmi.head) { From b91ea6e6a0157248093d617060f31d5960853e55 Mon Sep 17 00:00:00 2001 From: Shaoyun Liu Date: Thu, 10 Jul 2025 21:42:16 -0400 Subject: [PATCH 1966/2653] drm/amd/amdgpu : Use the MES INV_TLBS API for tlb invalidation on gfx12 From MES version 0x81, it provide the new API INV_TLBS that support invalidate tlbs with PASID. Signed-off-by: Shaoyun Liu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 9 ++++++ drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 16 ++++++++++ drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 42 +++++++++++++++++++++++++ 3 files changed, 67 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 98e77aa01f277..49942a1cb8f52 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -290,6 +290,13 @@ struct mes_detect_and_reset_queue_input { bool detect_only; }; +struct mes_inv_tlbs_pasid_input { + uint32_t xcc_id; + uint16_t pasid; + uint8_t hub_id; + uint8_t flush_type; +}; + enum mes_misc_opcode { MES_MISC_OP_WRITE_REG, MES_MISC_OP_READ_REG, @@ -381,6 +388,8 @@ struct amdgpu_mes_funcs { int (*detect_and_reset_hung_queues)(struct amdgpu_mes *mes, struct mes_detect_and_reset_queue_input *input); + int (*invalidate_tlbs_pasid)(struct amdgpu_mes *mes, + struct mes_inv_tlbs_pasid_input *input); }; #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 48f676126a6b6..76d3c40735b0b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -336,6 +336,22 @@ static void gmc_v12_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t queried; int vmid, i; + if (adev->enable_uni_mes && adev->mes.ring[AMDGPU_MES_SCHED_PIPE].sched.ready && + (adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x81) { + struct mes_inv_tlbs_pasid_input input = {0}; + input.pasid = pasid; + input.flush_type = flush_type; + input.hub_id = AMDGPU_GFXHUB(0); + /* MES will invalidate all gc_hub for the device from master */ + adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); + if (all_hub) { + /* Only need to invalidate mm_hub now, gfx12 only support one mmhub */ + input.hub_id = AMDGPU_MMHUB0(0); + adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); + } + return; + } + for (vmid = 1; vmid < 16; vmid++) { bool valid; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index ca06046c5d68d..14981e3c1f9e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -110,6 +110,7 @@ static const char *mes_v12_0_opcodes[] = { "SET_SE_MODE", "SET_GANG_SUBMIT", "SET_HW_RSRC_1", + "INVALIDATE_TLBS", }; static const char *mes_v12_0_misc_opcodes[] = { @@ -935,6 +936,46 @@ static int mes_v12_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, offsetof(union MESAPI__RESET, api_status)); } +static int mes_v12_inv_tlb_convert_hub_id(uint8_t id) +{ + /* + * MES doesn't support invalidate gc_hub on slave xcc individually + * master xcc will invalidate all gc_hub for the partition + */ + if (AMDGPU_IS_GFXHUB(id)) + return 0; + else if (AMDGPU_IS_MMHUB0(id)) + return 1; + else + return -EINVAL; + +} + +static int mes_v12_0_inv_tlbs_pasid(struct amdgpu_mes *mes, + struct mes_inv_tlbs_pasid_input *input) +{ + union MESAPI__INV_TLBS mes_inv_tlbs; + + memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs)); + + mes_inv_tlbs.header.type = MES_API_TYPE_SCHEDULER; + mes_inv_tlbs.header.opcode = MES_SCH_API_INV_TLBS; + mes_inv_tlbs.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_inv_tlbs.invalidate_tlbs.inv_sel = 0; + mes_inv_tlbs.invalidate_tlbs.flush_type = input->flush_type; + mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input->pasid; + + /*convert amdgpu_mes_hub_id to mes expected hub_id */ + mes_inv_tlbs.invalidate_tlbs.hub_id = mes_v12_inv_tlb_convert_hub_id(input->hub_id); + if (mes_inv_tlbs.invalidate_tlbs.hub_id < 0) + return -EINVAL; + return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_KIQ_PIPE, + &mes_inv_tlbs, sizeof(mes_inv_tlbs), + offsetof(union MESAPI__INV_TLBS, api_status)); + +} + static const struct amdgpu_mes_funcs mes_v12_0_funcs = { .add_hw_queue = mes_v12_0_add_hw_queue, .remove_hw_queue = mes_v12_0_remove_hw_queue, @@ -945,6 +986,7 @@ static const struct amdgpu_mes_funcs mes_v12_0_funcs = { .misc_op = mes_v12_0_misc_op, .reset_hw_queue = mes_v12_0_reset_hw_queue, .detect_and_reset_hung_queues = mes_v12_0_detect_and_reset_hung_queues, + .invalidate_tlbs_pasid = mes_v12_0_inv_tlbs_pasid, }; static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, From 6dc44f22d59cc37cb528ef58980779c81142bc83 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Wed, 3 Sep 2025 09:20:18 +0100 Subject: [PATCH 1967/2653] drm/amd/amdgpu: Fix a less than zero check on a uint32_t struct field Currently the error check from the call to mes_v12_inv_tlb_convert_hub_id is always false because a uint32_t struct field hub_id is being used to to perform the less than zero error check. Fix this by using the int variable ret to perform the check. Fixes: 87e65052616c ("drm/amd/amdgpu : Use the MES INV_TLBS API for tlb invalidation on gfx12") Reviewed-by: Dan Carpenter Signed-off-by: Colin Ian King Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index 14981e3c1f9e9..81d24365d831f 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -955,6 +955,7 @@ static int mes_v12_0_inv_tlbs_pasid(struct amdgpu_mes *mes, struct mes_inv_tlbs_pasid_input *input) { union MESAPI__INV_TLBS mes_inv_tlbs; + int ret; memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs)); @@ -967,9 +968,10 @@ static int mes_v12_0_inv_tlbs_pasid(struct amdgpu_mes *mes, mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input->pasid; /*convert amdgpu_mes_hub_id to mes expected hub_id */ - mes_inv_tlbs.invalidate_tlbs.hub_id = mes_v12_inv_tlb_convert_hub_id(input->hub_id); - if (mes_inv_tlbs.invalidate_tlbs.hub_id < 0) + ret = mes_v12_inv_tlb_convert_hub_id(input->hub_id); + if (ret < 0) return -EINVAL; + mes_inv_tlbs.invalidate_tlbs.hub_id = ret; return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_KIQ_PIPE, &mes_inv_tlbs, sizeof(mes_inv_tlbs), offsetof(union MESAPI__INV_TLBS, api_status)); From 35bae03cf8593c425fafe2296d54ab53ab47a69e Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Thu, 4 Sep 2025 16:30:08 +0800 Subject: [PATCH 1968/2653] drm/amdgpu: adjust MES API used for suspend and resume Use the suspend and resume API rather than remove queue and add queue API. The former just preempts the queue while the latter remove it from the scheduler completely. There is no need to do that, we only need preemption in this case. V2: replace queue_active with queue state v3: set the suspend_fence_addr v4: allocate another per queue buffer for the suspend fence, and set the sequence number. also wait for the suspend fence. (Alex) v5: use a wb slot (Alex) v6: Change the timeout period. For MES, the default timeout is 2100000; /* 2100 ms */ (Alex) Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index 3a4fd6de08ce7..2db9b2c63693d 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -404,10 +404,82 @@ mes_userq_mqd_destroy(struct amdgpu_userq_mgr *uq_mgr, amdgpu_userq_destroy_object(uq_mgr, &queue->mqd); } +static int mes_userq_preempt(struct amdgpu_userq_mgr *uq_mgr, + struct amdgpu_usermode_queue *queue) +{ + struct amdgpu_device *adev = uq_mgr->adev; + struct mes_suspend_gang_input queue_input; + struct amdgpu_userq_obj *ctx = &queue->fw_obj; + signed long timeout = 2100000; /* 2100 ms */ + u64 fence_gpu_addr; + u32 fence_offset; + u64 *fence_ptr; + int i, r; + + if (queue->state != AMDGPU_USERQ_STATE_MAPPED) + return 0; + r = amdgpu_device_wb_get(adev, &fence_offset); + if (r) + return r; + + fence_gpu_addr = adev->wb.gpu_addr + (fence_offset * 4); + fence_ptr = (u64 *)&adev->wb.wb[fence_offset]; + *fence_ptr = 0; + + memset(&queue_input, 0x0, sizeof(struct mes_suspend_gang_input)); + queue_input.gang_context_addr = ctx->gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ; + queue_input.suspend_fence_addr = fence_gpu_addr; + queue_input.suspend_fence_value = 1; + amdgpu_mes_lock(&adev->mes); + r = adev->mes.funcs->suspend_gang(&adev->mes, &queue_input); + amdgpu_mes_unlock(&adev->mes); + if (r) { + DRM_ERROR("Failed to suspend gang: %d\n", r); + goto out; + } + + for (i = 0; i < timeout; i++) { + if (*fence_ptr == 1) + goto out; + udelay(1); + } + r = -ETIMEDOUT; + +out: + amdgpu_device_wb_free(adev, fence_offset); + return r; +} + +static int mes_userq_restore(struct amdgpu_userq_mgr *uq_mgr, + struct amdgpu_usermode_queue *queue) +{ + struct amdgpu_device *adev = uq_mgr->adev; + struct mes_resume_gang_input queue_input; + struct amdgpu_userq_obj *ctx = &queue->fw_obj; + int r; + + if (queue->state == AMDGPU_USERQ_STATE_HUNG) + return -EINVAL; + if (queue->state != AMDGPU_USERQ_STATE_PREEMPTED) + return 0; + + memset(&queue_input, 0x0, sizeof(struct mes_resume_gang_input)); + queue_input.gang_context_addr = ctx->gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ; + + amdgpu_mes_lock(&adev->mes); + r = adev->mes.funcs->resume_gang(&adev->mes, &queue_input); + amdgpu_mes_unlock(&adev->mes); + if (r) + dev_err(adev->dev, "Failed to resume queue, err (%d)\n", r); + return r; +} + const struct amdgpu_userq_funcs userq_mes_funcs = { .mqd_create = mes_userq_mqd_create, .mqd_destroy = mes_userq_mqd_destroy, .unmap = mes_userq_unmap, .map = mes_userq_map, .detect_and_reset = mes_userq_detect_and_reset, + .preempt = mes_userq_preempt, + .restore = mes_userq_restore, }; From 1892107777377590e85f0c1fc842e0a6b4d3c662 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Tue, 5 Aug 2025 12:23:18 +0800 Subject: [PATCH 1969/2653] drm/amdgpu: Switch user queues to use preempt/restore for eviction This patch modifies the user queue management to use preempt/restore operations instead of full map/unmap for queue eviction scenarios where applicable. The changes include: 1. Introduces new helper functions: - amdgpu_userqueue_preempt_helper() - amdgpu_userqueue_restore_helper() 2. Updates queue state management to track PREEMPTED state 3. Modifies eviction handling to use preempt instead of unmap: - amdgpu_userq_evict_all() now uses preempt_helper - amdgpu_userq_restore_all() now uses restore_helper The preempt/restore approach provides better performance during queue eviction by avoiding the overhead of full queue teardown and setup. Full map/unmap operations are still used for initial setup/teardown and system suspend scenarios. v2: rename amdgpu_userqueue_restore_helper/amdgpu_userqueue_preempt_helper to amdgpu_userq_restore_helper/amdgpu_userq_preempt_helper for consistency. (Alex) v3: amdgpu_userq_stop_sched_for_enforce_isolation() and amdgpu_userq_start_sched_for_enforce_isolation() should use preempt and restore (Alex) Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 53 ++++++++++++++++++++--- 1 file changed, 48 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 5661bb678c301..d28dfc752677b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -77,7 +77,7 @@ int amdgpu_userq_input_va_validate(struct amdgpu_vm *vm, u64 addr, } static int -amdgpu_userq_unmap_helper(struct amdgpu_userq_mgr *uq_mgr, +amdgpu_userq_preempt_helper(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_queue *queue) { struct amdgpu_device *adev = uq_mgr->adev; @@ -86,6 +86,49 @@ amdgpu_userq_unmap_helper(struct amdgpu_userq_mgr *uq_mgr, int r = 0; if (queue->state == AMDGPU_USERQ_STATE_MAPPED) { + r = userq_funcs->preempt(uq_mgr, queue); + if (r) { + queue->state = AMDGPU_USERQ_STATE_HUNG; + } else { + queue->state = AMDGPU_USERQ_STATE_PREEMPTED; + } + } + + return r; +} + +static int +amdgpu_userq_restore_helper(struct amdgpu_userq_mgr *uq_mgr, + struct amdgpu_usermode_queue *queue) +{ + struct amdgpu_device *adev = uq_mgr->adev; + const struct amdgpu_userq_funcs *userq_funcs = + adev->userq_funcs[queue->queue_type]; + int r = 0; + + if (queue->state == AMDGPU_USERQ_STATE_PREEMPTED) { + r = userq_funcs->restore(uq_mgr, queue); + if (r) { + queue->state = AMDGPU_USERQ_STATE_HUNG; + } else { + queue->state = AMDGPU_USERQ_STATE_MAPPED; + } + } + + return r; +} + +static int +amdgpu_userq_unmap_helper(struct amdgpu_userq_mgr *uq_mgr, + struct amdgpu_usermode_queue *queue) +{ + struct amdgpu_device *adev = uq_mgr->adev; + const struct amdgpu_userq_funcs *userq_funcs = + adev->userq_funcs[queue->queue_type]; + int r = 0; + + if ((queue->state == AMDGPU_USERQ_STATE_MAPPED) || + (queue->state == AMDGPU_USERQ_STATE_PREEMPTED)) { r = userq_funcs->unmap(uq_mgr, queue); if (r) queue->state = AMDGPU_USERQ_STATE_HUNG; @@ -658,7 +701,7 @@ amdgpu_userq_restore_all(struct amdgpu_userq_mgr *uq_mgr) /* Resume all the queues for this process */ idr_for_each_entry(&uq_mgr->userq_idr, queue, queue_id) { - r = amdgpu_userq_map_helper(uq_mgr, queue); + r = amdgpu_userq_restore_helper(uq_mgr, queue); if (r) ret = r; } @@ -815,7 +858,7 @@ amdgpu_userq_evict_all(struct amdgpu_userq_mgr *uq_mgr) /* Try to unmap all the queues in this process ctx */ idr_for_each_entry(&uq_mgr->userq_idr, queue, queue_id) { - r = amdgpu_userq_unmap_helper(uq_mgr, queue); + r = amdgpu_userq_preempt_helper(uq_mgr, queue); if (r) ret = r; } @@ -1000,7 +1043,7 @@ int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev, if (((queue->queue_type == AMDGPU_HW_IP_GFX) || (queue->queue_type == AMDGPU_HW_IP_COMPUTE)) && (queue->xcp_id == idx)) { - r = amdgpu_userq_unmap_helper(uqm, queue); + r = amdgpu_userq_preempt_helper(uqm, queue); if (r) ret = r; } @@ -1034,7 +1077,7 @@ int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev, if (((queue->queue_type == AMDGPU_HW_IP_GFX) || (queue->queue_type == AMDGPU_HW_IP_COMPUTE)) && (queue->xcp_id == idx)) { - r = amdgpu_userq_map_helper(uqm, queue); + r = amdgpu_userq_restore_helper(uqm, queue); if (r) ret = r; } From 19f9771d12d17824967ebfa9c5f6f9b892b45783 Mon Sep 17 00:00:00 2001 From: Alexander Deucher Date: Fri, 12 Sep 2025 09:05:22 -0400 Subject: [PATCH 1970/2653] Revert "drm/amdkfd: Replace kmalloc + copy_from_user with memdup_user" This reverts commit 14a277ac11a467f21ab0c70476a9595684e7b890. Reason for revert: Can't call kfree() on an error pointer. Change-Id: Id5f8344f45d43894bbf77c2e0a852fb19f9dfd3b --- .../amd/amdkfd/kfd_process_queue_manager.c | 22 ++++++++++++++----- 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 6f64e7217d490..d91b0e498fc9d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -1008,9 +1008,13 @@ int kfd_criu_restore_queue(struct kfd_process *p, if (*priv_data_offset + sizeof(*q_data) > max_priv_data_size) return -EINVAL; - q_data = memdup_user(user_priv_ptr + *priv_data_offset, sizeof(*q_data)); - if (IS_ERR(q_data)) { - ret = PTR_ERR(q_data); + q_data = kmalloc(sizeof(*q_data), GFP_KERNEL); + if (!q_data) + return -ENOMEM; + + ret = copy_from_user(q_data, user_priv_ptr + *priv_data_offset, sizeof(*q_data)); + if (ret) { + ret = -EFAULT; goto exit; } @@ -1022,9 +1026,15 @@ int kfd_criu_restore_queue(struct kfd_process *p, goto exit; } - q_extra_data = memdup_user(user_priv_ptr + *priv_data_offset, q_extra_data_size); - if (IS_ERR(q_extra_data)) { - ret = PTR_ERR(q_extra_data); + q_extra_data = kmalloc(q_extra_data_size, GFP_KERNEL); + if (!q_extra_data) { + ret = -ENOMEM; + goto exit; + } + + ret = copy_from_user(q_extra_data, user_priv_ptr + *priv_data_offset, q_extra_data_size); + if (ret) { + ret = -EFAULT; goto exit; } From 3ed0aeacd404679cddf03d7b2015c778a3eb36ee Mon Sep 17 00:00:00 2001 From: "Mario Limonciello (AMD)" Date: Mon, 11 Aug 2025 12:00:06 -0500 Subject: [PATCH 1971/2653] drm/amd: Avoid evicting resources at S5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Normally resources are evicted on dGPUs at suspend or hibernate and on APUs at hibernate. These steps are unnecessary when using the S4 callbacks to put the system into S5. Cc: AceLan Kao Cc: Kai-Heng Feng Cc: Mark Pearson Cc: Denis Benato Cc: Merthan Karakaş Tested-by: Eric Naim Acked-by: Alex Deucher Signed-off-by: Mario Limonciello (AMD) --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index d8acd623272f3..53b94074c359b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5123,6 +5123,10 @@ static int amdgpu_device_evict_resources(struct amdgpu_device *adev) if (!adev->in_s4 && (adev->flags & AMD_IS_APU)) return 0; + /* No need to evict when going to S5 through S4 callbacks */ + if (system_state == SYSTEM_POWER_OFF) + return 0; + ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM); if (ret) { dev_warn(adev->dev, "evicting device resources failed\n"); From 19863a49bbfed460a3b4907e1d2ff769304678ff Mon Sep 17 00:00:00 2001 From: Shaoyun Liu Date: Thu, 11 Sep 2025 12:59:00 -0400 Subject: [PATCH 1972/2653] drm/amd/amdgpu: Fix the mes version that support inv_tlbs MES pipe0 will do VM invalidation with engine set 5 when assign VMID to a process, driver will submit inv_tlb package to mes pipe1. It might run into race condition if both pipes use the same invalidate engine set. From MES version 0x83 it will use invalidate engine set 6 for pipe1 to fix the issue Signed-off-by: Shaoyun Liu Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 76d3c40735b0b..7cc16af1868b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -337,7 +337,7 @@ static void gmc_v12_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, int vmid, i; if (adev->enable_uni_mes && adev->mes.ring[AMDGPU_MES_SCHED_PIPE].sched.ready && - (adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x81) { + (adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x83) { struct mes_inv_tlbs_pasid_input input = {0}; input.pasid = pasid; input.flush_type = flush_type; From a6e6f00421d13e2f2d008059d0b8dfc6c7bb6c4b Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 22 Aug 2025 15:38:00 -0400 Subject: [PATCH 1973/2653] Revert "drm/amdkfd: return migration pages from copy function" This reverts commit cab1cec78c8fd52e014546739875a81150f11080. migrate_vma_pages can fail if a CPU thread faults on the same page. However, the page table is locked and only one of the new pages will be inserted. The device driver will see that the MIGRATE_PFN_MIGRATE bit is cleared if it loses the race. Signed-off-by: James Zhu Reviewed-by: Philip Yang --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 60 ++++++++++++------------ 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index b6f61d133ed7d..7607c2fb26c68 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -39,22 +39,22 @@ #endif #define dev_fmt(fmt) "kfd_migrate: " fmt -static uint64_t -svm_migrate_direct_mapping_addr(struct amdgpu_device *adev, uint64_t addr) +static u64 +svm_migrate_direct_mapping_addr(struct amdgpu_device *adev, u64 addr) { return addr + amdgpu_ttm_domain_start(adev, TTM_PL_VRAM); } static int -svm_migrate_gart_map(struct amdgpu_ring *ring, uint64_t npages, - dma_addr_t *addr, uint64_t *gart_addr, uint64_t flags) +svm_migrate_gart_map(struct amdgpu_ring *ring, u64 npages, + dma_addr_t *addr, u64 *gart_addr, u64 flags) { struct amdgpu_device *adev = ring->adev; struct amdgpu_job *job; unsigned int num_dw, num_bytes; struct dma_fence *fence; - uint64_t src_addr, dst_addr; - uint64_t pte_flags; + u64 src_addr, dst_addr; + u64 pte_flags; void *cpu_addr; int r; @@ -122,15 +122,15 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, uint64_t npages, static int svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys, - uint64_t *vram, uint64_t npages, + u64 *vram, u64 npages, enum MIGRATION_COPY_DIR direction, struct dma_fence **mfence) { - const uint64_t GTT_MAX_PAGES = AMDGPU_GTT_MAX_TRANSFER_SIZE; + const u64 GTT_MAX_PAGES = AMDGPU_GTT_MAX_TRANSFER_SIZE; struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; - uint64_t gart_s, gart_d; + u64 gart_s, gart_d; struct dma_fence *next; - uint64_t size; + u64 size; int r; mutex_lock(&adev->mman.gtt_window_lock); @@ -285,23 +285,23 @@ static unsigned long svm_migrate_unsuccessful_pages(struct migrate_vma *migrate) static int svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, struct migrate_vma *migrate, struct dma_fence **mfence, - dma_addr_t *scratch, uint64_t ttm_res_offset) + dma_addr_t *scratch, u64 ttm_res_offset) { - uint64_t npages = migrate->npages; + u64 npages = migrate->npages; struct amdgpu_device *adev = node->adev; struct device *dev = adev->dev; struct amdgpu_res_cursor cursor; - uint64_t mpages = 0; + u64 mpages = 0; dma_addr_t *src; - uint64_t *dst; - uint64_t i, j; + u64 *dst; + u64 i, j; int r; pr_debug("svms 0x%p [0x%lx 0x%lx 0x%llx]\n", prange->svms, prange->start, prange->last, ttm_res_offset); src = scratch; - dst = (uint64_t *)(scratch + npages); + dst = (u64 *)(scratch + npages); amdgpu_res_first(prange->ttm_res, ttm_res_offset, npages << PAGE_SHIFT, &cursor); @@ -395,11 +395,11 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, static long svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange, - struct vm_area_struct *vma, uint64_t start, - uint64_t end, uint32_t trigger, uint64_t ttm_res_offset) + struct vm_area_struct *vma, u64 start, + u64 end, uint32_t trigger, u64 ttm_res_offset) { struct kfd_process *p = container_of(prange->svms, struct kfd_process, svms); - uint64_t npages = (end - start) >> PAGE_SHIFT; + u64 npages = (end - start) >> PAGE_SHIFT; struct amdgpu_device *adev = node->adev; struct kfd_process_device *pdd; struct dma_fence *mfence = NULL; @@ -422,7 +422,7 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange, #endif buf = kvcalloc(npages, - 2 * sizeof(*migrate.src) + sizeof(uint64_t) + sizeof(dma_addr_t), + 2 * sizeof(*migrate.src) + sizeof(u64) + sizeof(dma_addr_t), GFP_KERNEL); if (!buf) goto out; @@ -463,7 +463,7 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange, mpages = cpages - svm_migrate_unsuccessful_pages(&migrate); pr_debug("successful/cpages/npages 0x%lx/0x%lx/0x%lx\n", - mpages, cpages, migrate.npages); + mpages, cpages, migrate.npages); svm_range_dma_unmap_dev(adev->dev, scratch, 0, npages); @@ -504,7 +504,7 @@ svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc, { unsigned long addr, start, end; struct vm_area_struct *vma; - uint64_t ttm_res_offset; + u64 ttm_res_offset; struct kfd_node *node; unsigned long mpages = 0; long r = 0; @@ -594,14 +594,14 @@ static void svm_migrate_page_free(struct page *page) static int svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, struct migrate_vma *migrate, struct dma_fence **mfence, - dma_addr_t *scratch, uint64_t npages) + dma_addr_t *scratch, u64 npages) { struct device *dev = adev->dev; - uint64_t *src; + u64 *src; dma_addr_t *dst; struct page *dpage; - uint64_t i = 0, j; - uint64_t addr; + u64 i = 0, j; + u64 addr; int r = 0; pr_debug("svms 0x%p [0x%lx 0x%lx]\n", prange->svms, prange->start, @@ -609,7 +609,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, addr = migrate->start; - src = (uint64_t *)(scratch + npages); + src = (u64 *)(scratch + npages); dst = scratch; for (i = 0, j = 0; i < npages; i++, addr += PAGE_SIZE) { @@ -698,11 +698,11 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, */ static long svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, - struct vm_area_struct *vma, uint64_t start, uint64_t end, + struct vm_area_struct *vma, u64 start, u64 end, uint32_t trigger, struct page *fault_page) { struct kfd_process *p = container_of(prange->svms, struct kfd_process, svms); - uint64_t npages = (end - start) >> PAGE_SHIFT; + u64 npages = (end - start) >> PAGE_SHIFT; unsigned long upages = npages; unsigned long cpages = 0; unsigned long mpages = 0; @@ -731,7 +731,7 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, #endif buf = kvcalloc(npages, - 2 * sizeof(*migrate.src) + sizeof(uint64_t) + sizeof(dma_addr_t), + 2 * sizeof(*migrate.src) + sizeof(u64) + sizeof(dma_addr_t), GFP_KERNEL); if (!buf) goto out; From 4600407203e85d2b71dd3e51129c2353aa7a66b9 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 22 Aug 2025 15:38:01 -0400 Subject: [PATCH 1974/2653] drm/amdkfd: add function svm_migrate_successful_pages to get migration pages. dst MIGRATE_PFN_VALID bit and src MIGRATE_PFN_MIGRATE bit should always be set when migration success. cpage includes src MIGRATE_PFN_MIGRATE bit set and MIGRATE_PFN_VALID bit unset pages for both RAM and VRAM when memory is only allocated without being populated before migration, those ram pages should be counted as migrated pages and those vram pages should not be counted as migrated pages. Here migration pages refer to how many vram pages invloved. Current svm_migrate_unsuccessful_pages only covers the unsuccessful case that source is on RAM. So far, we only see two unsuccessful migration cases. Since we can clearly identify successful migration cases through dst MIGRATE_PFN_VALID bit and src MIGRATE_PFN_MIGRATE bit within this prange, also eventually successful migration pages will be used, so we can use function svm_migrate_successful_pages to replace function svm_migrate_unsuccessful_pages. Signed-off-by: James Zhu Reviewed-by: Philip Yang --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 29 ++++++++++++------------ 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 7607c2fb26c68..a35b3b0c0d2ff 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -269,17 +269,17 @@ static void svm_migrate_put_sys_page(unsigned long addr) put_page(page); } -static unsigned long svm_migrate_unsuccessful_pages(struct migrate_vma *migrate) +static unsigned long svm_migrate_successful_pages(struct migrate_vma *migrate) { - unsigned long upages = 0; + unsigned long mpages = 0; unsigned long i; for (i = 0; i < migrate->npages; i++) { - if (migrate->src[i] & MIGRATE_PFN_VALID && - !(migrate->src[i] & MIGRATE_PFN_MIGRATE)) - upages++; + if (migrate->dst[i] & MIGRATE_PFN_VALID && + migrate->src[i] & MIGRATE_PFN_MIGRATE) + mpages++; } - return upages; + return mpages; } static int @@ -461,8 +461,8 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange, svm_migrate_copy_done(adev, mfence); migrate_vma_finalize(&migrate); - mpages = cpages - svm_migrate_unsuccessful_pages(&migrate); - pr_debug("successful/cpages/npages 0x%lx/0x%lx/0x%lx\n", + mpages = svm_migrate_successful_pages(&migrate); + pr_debug("migrated/collected/requested 0x%lx/0x%lx/0x%lx\n", mpages, cpages, migrate.npages); svm_range_dma_unmap_dev(adev->dev, scratch, 0, npages); @@ -703,7 +703,6 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, { struct kfd_process *p = container_of(prange->svms, struct kfd_process, svms); u64 npages = (end - start) >> PAGE_SHIFT; - unsigned long upages = npages; unsigned long cpages = 0; unsigned long mpages = 0; struct amdgpu_device *adev = node->adev; @@ -771,9 +770,9 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, scratch, npages); migrate_vma_pages(&migrate); - upages = svm_migrate_unsuccessful_pages(&migrate); - pr_debug("unsuccessful/cpages/npages 0x%lx/0x%lx/0x%lx\n", - upages, cpages, migrate.npages); + mpages = svm_migrate_successful_pages(&migrate); + pr_debug("migrated/collected/requested 0x%lx/0x%lx/0x%lx\n", + mpages, cpages, migrate.npages); svm_migrate_copy_done(adev, mfence); migrate_vma_finalize(&migrate); @@ -786,8 +785,7 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, start >> PAGE_SHIFT, end >> PAGE_SHIFT, node->id, 0, trigger, r); out: - if (!r && cpages) { - mpages = cpages - upages; + if (!r && mpages) { pdd = svm_range_get_pdd_by_node(prange, node); if (pdd) WRITE_ONCE(pdd->page_out, pdd->page_out + mpages); @@ -870,6 +868,9 @@ int svm_migrate_vram_to_ram(struct svm_range *prange, struct mm_struct *mm, } if (r >= 0) { + WARN_ONCE(prange->vram_pages < mpages, + "Recorded vram pages(0x%llx) should not be less than migration pages(0x%lx).", + prange->vram_pages, mpages); prange->vram_pages -= mpages; /* prange does not have vram page set its actual_loc to system From 707606cb666efa52695a91965e0d182e687ce536 Mon Sep 17 00:00:00 2001 From: John Olender Date: Fri, 5 Sep 2025 06:11:28 -0400 Subject: [PATCH 1975/2653] drm/amdgpu: Fix NULL ptr deref in amdgpu_device_cache_switch_state() Kaveri has no upstream bridge, therefore parent is NULL. $ lspci -PP ... 00:01.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Kaveri [Radeon R7 Graphics] (rev d4) For comparison, Raphael: $ lspci -PP ... 00:08.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Raphael/Granite Ridge Internal GPP Bridge to Bus [C:A] ... 00:08.1/0e:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Raphael (rev c5) Fixes: 1dd2fa0e00f1 ("drm/amdgpu: Save and restore switch state") Link: https://lore.kernel.org/amd-gfx/38fe6513-f8a9-4669-8e86-89c54c465611@gmail.com/ Reviewed-by: Candice Li Reviewed-by: Yang Wang Signed-off-by: John Olender Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 0194b8e661838..aaf1f7c99c705 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -7219,7 +7219,7 @@ static void amdgpu_device_cache_switch_state(struct amdgpu_device *adev) struct pci_dev *parent = pci_upstream_bridge(adev->pdev); int r; - if (parent->vendor != PCI_VENDOR_ID_ATI) + if (!parent || parent->vendor != PCI_VENDOR_ID_ATI) return; /* If already saved, return */ From 0f06af647c8db2285a73d8e42e7b657718a6fde3 Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Tue, 2 Sep 2025 16:20:09 -0400 Subject: [PATCH 1976/2653] drm/amd/display: Allow RX6xxx & RX7700 to invoke amdgpu_irq_get/put [Why&How] As reported on https://gitlab.freedesktop.org/drm/amd/-/issues/3936, SMU hang can occur if the interrupts are not enabled appropriately, causing a vblank timeout. This patch reverts "5009628d8509 drm/amd/display: Remove unnecessary amdgpu_irq_get/put", but only for RX6xxx & RX7700 GPUs, on which the issue was observed. This will re-enable interrupts regardless of whether the user space needed it or not. Fixes: 5009628d8509 ("drm/amd/display: Remove unnecessary amdgpu_irq_get/put") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3936 Suggested-by: Sun peng Li Reviewed-by: Sun peng Li Signed-off-by: Ivan Lipski Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 49 ++++++++++++++++--- 1 file changed, 42 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3205e31b121ee..e8c1cd5056fd8 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9122,7 +9122,16 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev, static void manage_dm_interrupts(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc, struct dm_crtc_state *acrtc_state) -{ +{ /* + * We cannot be sure that the frontend index maps to the same + * backend index - some even map to more than one. + * So we have to go through the CRTC to find the right IRQ. + */ + int irq_type = amdgpu_display_crtc_idx_to_irq_type( + adev, + acrtc->crtc_id); + struct drm_device *dev = adev_to_drm(adev); + #ifdef HAVE_DRM_VBLANK_CRTC_CONFIG struct drm_vblank_crtc_config config = {0}; struct dc_crtc_timing *timing; @@ -9176,15 +9185,41 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, drm_crtc_vblank_on_config(&acrtc->base, &config); - } else { - drm_crtc_vblank_off(&acrtc->base); - } #else - if (acrtc_state) + if (acrtc_state) { drm_crtc_vblank_on(&acrtc->base); - else - drm_crtc_vblank_off(&acrtc->base); #endif + /* Allow RX6xxx, RX7700, RX7800 GPUs to call amdgpu_irq_get.*/ + switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { + case IP_VERSION(3, 0, 0): + case IP_VERSION(3, 0, 2): + case IP_VERSION(3, 0, 3): + case IP_VERSION(3, 2, 0): + if (amdgpu_irq_get(adev, &adev->pageflip_irq, irq_type)) + drm_err(dev, "DM_IRQ: Cannot get pageflip irq!\n"); +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) + if (amdgpu_irq_get(adev, &adev->vline0_irq, irq_type)) + drm_err(dev, "DM_IRQ: Cannot get vline0 irq!\n"); +#endif + } + + } else { + /* Allow RX6xxx, RX7700, RX7800 GPUs to call amdgpu_irq_put.*/ + switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { + case IP_VERSION(3, 0, 0): + case IP_VERSION(3, 0, 2): + case IP_VERSION(3, 0, 3): + case IP_VERSION(3, 2, 0): +#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) + if (amdgpu_irq_put(adev, &adev->vline0_irq, irq_type)) + drm_err(dev, "DM_IRQ: Cannot put vline0 irq!\n"); +#endif + if (amdgpu_irq_put(adev, &adev->pageflip_irq, irq_type)) + drm_err(dev, "DM_IRQ: Cannot put pageflip irq!\n"); + } + + drm_crtc_vblank_off(&acrtc->base); + } } static void dm_update_pflip_irq_state(struct amdgpu_device *adev, From 3e9e784dcc34dcc4539718a5481e17c265b6d657 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Thu, 4 Sep 2025 09:48:00 +0800 Subject: [PATCH 1977/2653] drm/amd/pm: unified smu feature cap for link reset unified link reset smu feature cap Signed-off-by: Yang Wang Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 7 +--- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 6 +-- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 40 ++++++++++--------- 3 files changed, 23 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index aa51124d4b84e..6a99f9654f003 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -3536,15 +3536,10 @@ bool smu_mode1_reset_is_support(struct smu_context *smu) bool smu_link_reset_is_support(struct smu_context *smu) { - bool ret = false; - if (!smu->pm_enabled) return false; - if (smu->ppt_funcs && smu->ppt_funcs->link_reset_is_support) - ret = smu->ppt_funcs->link_reset_is_support(smu); - - return ret; + return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__LINK_RESET); } int smu_mode1_reset(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index e9f1c00c0f74c..75eee8f4998a0 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -560,6 +560,7 @@ enum smu_fw_status { #define SMU_WBRF_EVENT_HANDLING_PACE 10 enum smu_feature_cap_id { + SMU_FEATURE_CAP_ID__LINK_RESET = 0, SMU_FEATURE_CAP_ID__COUNT, }; @@ -1312,11 +1313,6 @@ struct pptable_funcs { */ bool (*mode1_reset_is_support)(struct smu_context *smu); - /** - * @link_reset_is_support: Check if GPU supports link reset. - */ - bool (*link_reset_is_support)(struct smu_context *smu); - /** * @mode1_reset: Perform mode1 reset. * diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index eee27d605b38d..944bd095d30c6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -3368,23 +3368,6 @@ static int smu_v13_0_6_reset_sdma(struct smu_context *smu, uint32_t inst_mask) return ret; } -static int smu_v13_0_6_post_init(struct smu_context *smu) -{ - struct smu_dpm_context *smu_dpm = &smu->smu_dpm; - struct smu_phase_det_ctl *pd_ctl; - bool enable; - - pd_ctl = smu_dpm->pd_ctl; - - if (!pd_ctl || pd_ctl->status == SMU_PHASE_DET_DISABLED) - return 0; - - enable = (pd_ctl->status == SMU_PHASE_DET_ON) ? true : false; - smu_v13_0_6_phase_det_enable(smu, enable); - - return 0; -} - static bool smu_v13_0_6_reset_vcn_is_supported(struct smu_context *smu) { return smu_v13_0_6_cap_supported(smu, SMU_CAP(VCN_RESET)); @@ -3402,6 +3385,26 @@ static int smu_v13_0_6_reset_vcn(struct smu_context *smu, uint32_t inst_mask) return ret; } +static int smu_v13_0_6_post_init(struct smu_context *smu) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + bool enable; + + if (smu_v13_0_6_is_link_reset_supported(smu)) + smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__LINK_RESET); + + pd_ctl = smu_dpm->pd_ctl; + + if (!pd_ctl || pd_ctl->status == SMU_PHASE_DET_DISABLED) + return 0; + + enable = (pd_ctl->status == SMU_PHASE_DET_ON) ? true : false; + smu_v13_0_6_phase_det_enable(smu, enable); + + return 0; +} + static int mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable) { struct smu_context *smu = adev->powerplay.pp_handle; @@ -4071,7 +4074,6 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { .get_xcp_metrics = smu_v13_0_6_get_xcp_metrics, .get_thermal_temperature_range = smu_v13_0_6_get_thermal_temperature_range, .mode1_reset_is_support = smu_v13_0_6_is_mode1_reset_supported, - .link_reset_is_support = smu_v13_0_6_is_link_reset_supported, .mode1_reset = smu_v13_0_6_mode1_reset, .mode2_reset = smu_v13_0_6_mode2_reset, .link_reset = smu_v13_0_6_link_reset, @@ -4082,9 +4084,9 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { .send_rma_reason = smu_v13_0_6_send_rma_reason, .reset_sdma = smu_v13_0_6_reset_sdma, .reset_sdma_is_supported = smu_v13_0_6_reset_sdma_is_supported, - .post_init = smu_v13_0_6_post_init, .dpm_reset_vcn = smu_v13_0_6_reset_vcn, .reset_vcn_is_supported = smu_v13_0_6_reset_vcn_is_supported, + .post_init = smu_v13_0_6_post_init, }; void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu) From d016715de7c461487778a669e120d27f2018ab13 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Thu, 4 Sep 2025 09:53:43 +0800 Subject: [PATCH 1978/2653] drm/amd/pm: unified smu feature cap for sdma reset unified sdma reset smu feature cap Signed-off-by: Yang Wang Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 7 +------ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 5 +---- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 4 +++- 3 files changed, 5 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 6a99f9654f003..a4a5f8858aa30 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -4129,12 +4129,7 @@ int smu_send_rma_reason(struct smu_context *smu) */ bool smu_reset_sdma_is_supported(struct smu_context *smu) { - bool ret = false; - - if (smu->ppt_funcs && smu->ppt_funcs->reset_sdma_is_supported) - ret = smu->ppt_funcs->reset_sdma_is_supported(smu); - - return ret; + return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__SDMA_RESET); } int smu_reset_sdma(struct smu_context *smu, uint32_t inst_mask) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 75eee8f4998a0..bd7b2dc1fbc54 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -561,6 +561,7 @@ enum smu_fw_status { enum smu_feature_cap_id { SMU_FEATURE_CAP_ID__LINK_RESET = 0, + SMU_FEATURE_CAP_ID__SDMA_RESET, SMU_FEATURE_CAP_ID__COUNT, }; @@ -1463,10 +1464,6 @@ struct pptable_funcs { * @reset_sdma: message SMU to soft reset sdma instance. */ int (*reset_sdma)(struct smu_context *smu, uint32_t inst_mask); - /** - * @reset_sdma_is_supported: Check if support resets the SDMA engine. - */ - bool (*reset_sdma_is_supported)(struct smu_context *smu); /** * @reset_vcn: message SMU to soft reset vcn instance. diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 944bd095d30c6..0aa999b2dda69 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -3394,6 +3394,9 @@ static int smu_v13_0_6_post_init(struct smu_context *smu) if (smu_v13_0_6_is_link_reset_supported(smu)) smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__LINK_RESET); + if (smu_v13_0_6_reset_sdma_is_supported(smu)) + smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__SDMA_RESET); + pd_ctl = smu_dpm->pd_ctl; if (!pd_ctl || pd_ctl->status == SMU_PHASE_DET_DISABLED) @@ -4083,7 +4086,6 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { .send_hbm_bad_pages_num = smu_v13_0_6_smu_send_hbm_bad_page_num, .send_rma_reason = smu_v13_0_6_send_rma_reason, .reset_sdma = smu_v13_0_6_reset_sdma, - .reset_sdma_is_supported = smu_v13_0_6_reset_sdma_is_supported, .dpm_reset_vcn = smu_v13_0_6_reset_vcn, .reset_vcn_is_supported = smu_v13_0_6_reset_vcn_is_supported, .post_init = smu_v13_0_6_post_init, From 50301b2dfd1ff07127582f3b4d864eac4e6153de Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Thu, 4 Sep 2025 09:57:25 +0800 Subject: [PATCH 1979/2653] drm/amd/pm: unified smu feature cap for vcn reset unified vcn reset smu feature cap Signed-off-by: Yang Wang Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 7 +------ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 5 +---- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 4 +++- 3 files changed, 5 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index a4a5f8858aa30..151e036b7e212 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -4339,10 +4339,5 @@ void amdgpu_smu_phase_det_debugfs_init(struct amdgpu_device *adev) } bool smu_reset_vcn_is_supported(struct smu_context *smu) { - bool ret = false; - - if (smu->ppt_funcs && smu->ppt_funcs->reset_vcn_is_supported) - ret = smu->ppt_funcs->reset_vcn_is_supported(smu); - - return ret; + return smu_feature_cap_test(smu, SMU_FEATURE_CAP_ID__VCN_RESET); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index bd7b2dc1fbc54..148153b3025b7 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -562,6 +562,7 @@ enum smu_fw_status { enum smu_feature_cap_id { SMU_FEATURE_CAP_ID__LINK_RESET = 0, SMU_FEATURE_CAP_ID__SDMA_RESET, + SMU_FEATURE_CAP_ID__VCN_RESET, SMU_FEATURE_CAP_ID__COUNT, }; @@ -1469,10 +1470,6 @@ struct pptable_funcs { * @reset_vcn: message SMU to soft reset vcn instance. */ int (*dpm_reset_vcn)(struct smu_context *smu, uint32_t inst_mask); - /** - * @reset_vcn_is_supported: Check if support resets vcn. - */ - bool (*reset_vcn_is_supported)(struct smu_context *smu); /** * @get_ecc_table: message SMU to get ECC INFO table. diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 0aa999b2dda69..d6a0005a509cd 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -3397,6 +3397,9 @@ static int smu_v13_0_6_post_init(struct smu_context *smu) if (smu_v13_0_6_reset_sdma_is_supported(smu)) smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__SDMA_RESET); + if (smu_v13_0_6_reset_vcn_is_supported(smu)) + smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__VCN_RESET); + pd_ctl = smu_dpm->pd_ctl; if (!pd_ctl || pd_ctl->status == SMU_PHASE_DET_DISABLED) @@ -4087,7 +4090,6 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { .send_rma_reason = smu_v13_0_6_send_rma_reason, .reset_sdma = smu_v13_0_6_reset_sdma, .dpm_reset_vcn = smu_v13_0_6_reset_vcn, - .reset_vcn_is_supported = smu_v13_0_6_reset_vcn_is_supported, .post_init = smu_v13_0_6_post_init, }; From 3c480ead5a4889c459f02cd3e21deaa1297b8b41 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 16 Sep 2025 14:47:27 +0800 Subject: [PATCH 1980/2653] drm/amdkcl: remove unnecessary vm_insert_mixed & vmf_insert_mixed_prot() check Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_memory.c | 14 ------ drivers/gpu/drm/amd/dkms/config/config.h | 6 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 | 14 ------ .../drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 | 20 --------- include/kcl/kcl_memory.h | 45 ------------------- 6 files changed, 100 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c index 606ae29de54ae..b835dd0f0e28b 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c @@ -31,20 +31,6 @@ #include #include -/* Copied from drivers/gpu/drm/ttm/ttm_bo_vm.c and modified for KCL */ -#ifndef HAVE_VMF_INSERT_MIXED_PROT -vm_fault_t _kcl_vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, - pfn_t pfn, pgprot_t pgprot) -{ - struct vm_area_struct cvma = *vma; - - cvma.vm_page_prot = pgprot; - - return vmf_insert_mixed(&cvma, addr, pfn); -} -EXPORT_SYMBOL(_kcl_vmf_insert_mixed_prot); -#endif - #ifndef HAVE_VMF_INSERT_PFN_PROT #ifndef HAVE_VM_INSERT_PFN_PROT int vm_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0eb49c6ea9986..8549c86fc7d4b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1087,9 +1087,6 @@ /* pfn_t is defined */ #define HAVE_PFN_T 1 -/* vm_insert_mixed() wants pfn_t arg */ -/* #undef HAVE_PFN_T_VM_INSERT_MIXED */ - /* PIDTYPE is availablea */ #define HAVE_PIDTYPE_TGID 1 @@ -1271,9 +1268,6 @@ /* vmf_insert_*() are available */ #define HAVE_VMF_INSERT 1 -/* vmf_insert_mixed_prot() is available */ -/* #undef HAVE_VMF_INSERT_MIXED_PROT */ - /* vmf_insert_pfn_prot() is available */ #define HAVE_VMF_INSERT_PFN_PROT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 680456b007ce4..419db3248d7d4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -36,7 +36,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_FSLEEP AC_AMDGPU_USLEEP_RANGE_STATE AC_AMDGPU_VMF_INSERT - AC_AMDGPU_VMF_INSERT_MIXED_PROT AC_AMDGPU_VMF_INSERT_PFN_PROT AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT AC_AMDGPU_MMU_NOTIFIER diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 index 89789fd059839..eb41c2919fae8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 @@ -25,20 +25,6 @@ AC_DEFUN([AC_AMDGPU_VMF_INSERT], [ ], [ AC_DEFINE(HAVE_VMF_INSERT, 1, [vmf_insert_*() are available]) - ], [ - dnl # - dnl # commit v4.4-6475-g01c8f1c44b83 - dnl # mm, dax, gpu: convert vm_insert_mixed to pfn_t - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - pfn_t pfn = {}; - vm_insert_mixed(NULL, 0, pfn); - ], [vm_insert_mixed], [mm/memory.c], [ - AC_DEFINE(HAVE_PFN_T_VM_INSERT_MIXED, 1, - [vm_insert_mixed() wants pfn_t arg]) - ]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 deleted file mode 100644 index 53da9747196ea..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 +++ /dev/null @@ -1,20 +0,0 @@ -dnl # -dnl # 5379e4dd3220 mm, drm/ttm: Fix vm page protection handling -dnl # 574c5b3d0e4c mm: Add a vmf_insert_mixed_prot() function -dnl # -AC_DEFUN([AC_AMDGPU_VMF_INSERT_MIXED_PROT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - #include - ],[ - pfn_t pfn; - pgprot_t prot; - vmf_insert_mixed_prot(NULL, 0, pfn, prot); - ],[vmf_insert_mixed_prot],[mm/memory.c],[ - AC_DEFINE(HAVE_VMF_INSERT_MIXED_PROT, - 1, - [vmf_insert_mixed_prot() is available]) - ]) - ]) -]) diff --git a/include/kcl/kcl_memory.h b/include/kcl/kcl_memory.h index aeebb157b0d57..571c570dd2c42 100644 --- a/include/kcl/kcl_memory.h +++ b/include/kcl/kcl_memory.h @@ -2,51 +2,6 @@ #ifndef _KCL_KCL_MEMORY_H #define _KCL_KCL_MEMORY_H -#ifndef HAVE_VMF_INSERT -static inline vm_fault_t vmf_insert_mixed(struct vm_area_struct *vma, - unsigned long addr, - pfn_t pfn) -{ - int err; -#if !defined(HAVE_PFN_T_VM_INSERT_MIXED) - err = vm_insert_mixed(vma, addr, pfn_t_to_pfn(pfn)); -#else - err = vm_insert_mixed(vma, addr, pfn); -#endif - if (err == -ENOMEM) - return VM_FAULT_OOM; - if (err < 0 && err != -EBUSY) - return VM_FAULT_SIGBUS; - - return VM_FAULT_NOPAGE; -} - -static inline vm_fault_t vmf_insert_pfn(struct vm_area_struct *vma, - unsigned long addr, unsigned long pfn) -{ - int err = vm_insert_pfn(vma, addr, pfn); - - if (err == -ENOMEM) - return VM_FAULT_OOM; - if (err < 0 && err != -EBUSY) - return VM_FAULT_SIGBUS; - - return VM_FAULT_NOPAGE; -} - -#endif /* HAVE_VMF_INSERT */ - -#ifndef HAVE_VMF_INSERT_MIXED_PROT -vm_fault_t _kcl_vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, - pfn_t pfn, pgprot_t pgprot); -static inline -vm_fault_t vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, - pfn_t pfn, pgprot_t pgprot) -{ - return _kcl_vmf_insert_mixed_prot(vma, addr, pfn, pgprot); -} -#endif /* HAVE_VMF_INSERT_MIXED_PROT */ - #ifndef HAVE_VMF_INSERT_PFN_PROT vm_fault_t _kcl_vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn, pgprot_t pgprot); From a5768ad0c2f753d3cf6e552b525ceabaa646a7f7 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 16 Sep 2025 14:51:23 +0800 Subject: [PATCH 1981/2653] drm/amdkcl: test whether vmf_insert_mixed_mkwrite() has long pfn arg Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 | 17 +++++++++++++++++ include/kcl/kcl_mm_types.h | 3 +-- 4 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8549c86fc7d4b..dcb998941d215 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1268,6 +1268,9 @@ /* vmf_insert_*() are available */ #define HAVE_VMF_INSERT 1 +/* vmf_insert_mixed_mkwrite() has long pfn arg */ +/* #undef HAVE_VMF_INSERT_MIXED_MKWRITE_LONG_PFN */ + /* vmf_insert_pfn_prot() is available */ #define HAVE_VMF_INSERT_PFN_PROT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 419db3248d7d4..6720f4cf0ef8c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -294,6 +294,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PAGE_PGMAP AC_AMDGPU_VMEMDUP_ARRAY_USER AC_AMDGPU_BITMAP_READ + AC_AMDGPU_VMF_INSERT_MIXED_MKWRITE_LONG_PFN AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 index eb41c2919fae8..cd07c76959799 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 @@ -29,3 +29,20 @@ AC_DEFUN([AC_AMDGPU_VMF_INSERT], [ ]) ]) ]) + +dnl # +dnl # commit v6.16-rc5-105-g21aa65bf82a7 +dnl # mm: remove callers of pfn_t functionality +dnl # +AC_DEFUN([AC_AMDGPU_VMF_INSERT_MIXED_MKWRITE_LONG_PFN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + vmf_insert_mixed_mkwrite(NULL, 0, 0); + ],[ + AC_DEFINE(HAVE_VMF_INSERT_MIXED_MKWRITE_LONG_PFN, 1, + [vmf_insert_mixed_mkwrite() has long pfn arg]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm_types.h b/include/kcl/kcl_mm_types.h index 6cf223e559d02..a180469fd2508 100644 --- a/include/kcl/kcl_mm_types.h +++ b/include/kcl/kcl_mm_types.h @@ -31,9 +31,8 @@ static inline unsigned long pfn_t_to_pfn(pfn_t pfn) } #endif -#ifndef HAVE_VMF_INSERT +#if !defined(HAVE_VMF_INSERT) && !defined(HAVE_VMF_INSERT_MIXED_MKWRITE_LONG_PFN) typedef int vm_fault_t; #endif #endif /* AMDKCL_MM_TYPES_H */ - From 0346165cf78520a7dcafff6a67b5b9247bf6d2d7 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 12 Sep 2025 16:51:55 +0800 Subject: [PATCH 1982/2653] drm/amdkcl: test shmem_writeout want 3 args Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 | 13 +++++++++++++ drivers/gpu/drm/ttm/ttm_backup.c | 4 ++++ 3 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index dcb998941d215..373785218c605 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1144,6 +1144,9 @@ /* shmem_writeout() is available */ #define HAVE_SHMEM_WRITEOUT 1 +/* shmem_writeout() wants 3 arguments */ +/* #undef HAVE_SHMEM_WRITEOUT_WANT_3_ARGS */ + /* shrinker_register() is available */ #define HAVE_SHRINKER_REGISTER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 b/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 index 92f9099fb34e0..1becbe3ee7c21 100644 --- a/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 @@ -11,6 +11,19 @@ AC_DEFUN([AC_AMDGPU_SHMEM_WRITEOUT], [ ],[shmem_writeout], [mm/shmem.c],[ AC_DEFINE(HAVE_SHMEM_WRITEOUT, 1, [shmem_writeout() is available]) + ],[ + dnl # + dnl # commit v6.16-rc5-20-g44b1b073eb36 + dnl # mm: stop passing a writeback_control structure to shmem_writeout + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + shmem_writeout(NULL, NULL,NULL); + ],[shmem_writeout], [mm/shmem.c],[ + AC_DEFINE(HAVE_SHMEM_WRITEOUT_WANT_3_ARGS, 1, + [shmem_writeout() wants 3 arguments]) + ]) ]) ]) ]) diff --git a/drivers/gpu/drm/ttm/ttm_backup.c b/drivers/gpu/drm/ttm/ttm_backup.c index 703fd1427423f..a7e28d7ec1fff 100644 --- a/drivers/gpu/drm/ttm/ttm_backup.c +++ b/drivers/gpu/drm/ttm/ttm_backup.c @@ -114,6 +114,7 @@ ttm_backup_backup_page(struct file *backup, struct page *page, if (writeback && !folio_mapped(to_folio) && folio_clear_dirty_for_io(to_folio)) { +#ifndef HAVE_SHMEM_WRITEOUT_WANT_3_ARGS struct writeback_control wbc = { .sync_mode = WB_SYNC_NONE, .nr_to_write = SWAP_CLUSTER_MAX, @@ -121,9 +122,12 @@ ttm_backup_backup_page(struct file *backup, struct page *page, .range_end = LLONG_MAX, .for_reclaim = 1, }; +#endif folio_set_reclaim(to_folio); #ifdef HAVE_SHMEM_WRITEOUT ret = shmem_writeout(to_folio, &wbc); +#elif defined(HAVE_SHMEM_WRITEOUT_WANT_3_ARGS) + ret = shmem_writeout(to_folio, NULL, NULL); #else ret = mapping->a_ops->writepage(folio_file_page(to_folio, idx), &wbc); #endif From b5c75581bbe643dcf1f2daf6a5cba1c915eaeaf9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 1 Jul 2025 12:07:04 +0300 Subject: [PATCH 1983/2653] drm: Pass pixel_format+modifier to .get_format_info() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Decouple .get_format_info() from struct drm_mode_fb_cmd2 and just pass the pixel format+modifier combo in by hand. We may want to use .get_format_info() outside of the normal addfb paths where we won't have a struct drm_mode_fb_cmd2, and creating a temporary one just for this seems silly. v2: Fix intel_fb_get_format_info() docs (Laurent) Cc: Harry Wentland Cc: Leo Li Cc: Rodrigo Siqueira Cc: Alex Deucher Cc: amd-gfx@lists.freedesktop.org Cc: Laurent Pinchart Reviewed-by: Thomas Zimmermann Reviewed-by: Laurent Pinchart Acked-by: Alex Deucher Acked-by: Rodrigo Vivi Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250701090722.13645-2-ville.syrjala@linux.intel.com --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++-- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h | 2 +- drivers/gpu/drm/drm_fourcc.c | 3 ++- drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++----- drivers/gpu/drm/i915/display/intel_fb.h | 2 +- include/drm/drm_mode_config.h | 2 +- 6 files changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index a0ebaa2a3018f..a3f062c72d49d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -95,9 +95,9 @@ enum dm_micro_swizzle { }; #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED -const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd) +const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier) { - return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]); + return amdgpu_lookup_format_info(pixel_format, modifier); } #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h index 615d2ab2b8034..ea2619b507db7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h @@ -58,7 +58,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, unsigned long possible_crtcs, const struct dc_plane_cap *plane_cap); -const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd); +const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier); void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, bool *per_pixel_alpha, bool *pre_multiplied_alpha, diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c index 2890e889dd151..4b4444f6d5041 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@ -430,7 +430,8 @@ drm_get_format_info(struct drm_device *dev, const struct drm_format_info *info = NULL; if (dev->mode_config.funcs->get_format_info) - info = dev->mode_config.funcs->get_format_info(mode_cmd); + info = dev->mode_config.funcs->get_format_info(mode_cmd->pixel_format, + mode_cmd->modifier[0]); if (!info) info = drm_format_info(mode_cmd->pixel_format); diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 79811f998e385..e221db072de23 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -422,21 +422,22 @@ unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) /** * intel_fb_get_format_info: Get a modifier specific format information - * @cmd: FB add command structure + * @pixel_format: pixel format + * @modifier: modifier * * Returns: - * Returns the format information for @cmd->pixel_format specific to @cmd->modifier[0], + * Returns the format information for @pixel_format specific to @modifier, * or %NULL if the modifier doesn't override the format. */ const struct drm_format_info * -intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd) +intel_fb_get_format_info(u32 pixel_format, u64 modifier) { - const struct intel_modifier_desc *md = lookup_modifier_or_null(cmd->modifier[0]); + const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier); if (!md || !md->formats) return NULL; - return lookup_format_info(md->formats, md->format_count, cmd->pixel_format); + return lookup_format_info(md->formats, md->format_count, pixel_format); } static bool plane_caps_contain_any(u8 caps, u8 mask) diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index bdd76b3729578..7d1267fbeee26 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -47,7 +47,7 @@ u64 *intel_fb_plane_get_modifiers(struct intel_display *display, bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier); const struct drm_format_info * -intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd); +intel_fb_get_format_info(u32 pixel_format, u64 modifier); bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h index 9e524b51a0018..e971e1b8a850c 100644 --- a/include/drm/drm_mode_config.h +++ b/include/drm/drm_mode_config.h @@ -95,7 +95,7 @@ struct drm_mode_config_funcs { * The format information specific to the given fb metadata, or * NULL if none is found. */ - const struct drm_format_info *(*get_format_info)(const struct drm_mode_fb_cmd2 *mode_cmd); + const struct drm_format_info *(*get_format_info)(u32 pixel_format, u64 modifier); /** * @mode_valid: From 5de3d61a56191ed121499b95bf7e958f675abea0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 1 Jul 2025 12:07:05 +0300 Subject: [PATCH 1984/2653] drm: Pass pixel_format+modifier directly to drm_get_format_info() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Decouple drm_get_format_info() from struct drm_mode_fb_cmd2 and just pass the pixel format+modifier combo in by hand. We may want to use drm_get_format_info() outside of the normal addfb paths where we won't have a struct drm_mode_fb_cmd2, and creating a temporary one just for this seems silly. Done with cocci: @@ identifier dev, mode_cmd; @@ struct drm_format_info * drm_get_format_info(struct drm_device *dev, - const struct drm_mode_fb_cmd2 *mode_cmd + u32 pixel_format, u64 modifier ) { <... ( - mode_cmd->pixel_format + pixel_format | - mode_cmd->modifier[0] + modifier ) ...> } @@ identifier dev, mode_cmd; @@ struct drm_format_info * drm_get_format_info(struct drm_device *dev, - const struct drm_mode_fb_cmd2 *mode_cmd + u32 pixel_format, u64 modifier ); @@ expression dev, mode_cmd; @@ - drm_get_format_info(dev, mode_cmd) + drm_get_format_info(dev, mode_cmd->pixel_format, mode_cmd->modifier[0]) v2: Fix kernel docs (Laurent) Drop drm_mode_fb_cmd2 forward declaration (Thomas) Cc: Liviu Dudau Cc: Russell King Cc: Inki Dae Cc: Seung-Woo Kim Cc: Kyungmin Park Cc: Patrik Jakobsson Cc: Chun-Kuang Hu Cc: Philipp Zabel Cc: Rob Clark Cc: Abhinav Kumar Cc: Dmitry Baryshkov Cc: Sean Paul Cc: Marijn Suijten Cc: Marek Vasut Cc: Stefan Agner Cc: Lyude Paul Cc: Danilo Krummrich Cc: Tomi Valkeinen Cc: Alex Deucher Cc: Sandy Huang Cc: "Heiko Stübner" Cc: Andy Yan Cc: Thierry Reding Cc: Mikko Perttunen Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Cc: nouveau@lists.freedesktop.org Cc: amd-gfx@lists.freedesktop.org Cc: linux-tegra@vger.kernel.org Reviewed-by: Thomas Zimmermann Reviewed-by: Laurent Pinchart Reviewed-by: Liviu Dudau Acked-by: Alex Deucher Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250701090722.13645-3-ville.syrjala@linux.intel.com --- drivers/gpu/drm/arm/malidp_drv.c | 3 ++- drivers/gpu/drm/armada/armada_fb.c | 4 +++- drivers/gpu/drm/drm_fourcc.c | 11 ++++++----- drivers/gpu/drm/drm_framebuffer.c | 2 +- drivers/gpu/drm/drm_gem_framebuffer_helper.c | 9 ++++++--- drivers/gpu/drm/drm_modeset_helper.c | 3 ++- drivers/gpu/drm/exynos/exynos_drm_fb.c | 4 +++- drivers/gpu/drm/gma500/framebuffer.c | 3 ++- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +++- drivers/gpu/drm/msm/msm_fb.c | 6 ++++-- drivers/gpu/drm/mxsfb/mxsfb_drv.c | 3 ++- drivers/gpu/drm/nouveau/nouveau_display.c | 3 ++- drivers/gpu/drm/omapdrm/omap_fb.c | 6 ++++-- drivers/gpu/drm/radeon/radeon_fbdev.c | 3 ++- drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 3 ++- drivers/gpu/drm/tegra/fb.c | 4 +++- include/drm/drm_fourcc.h | 3 +-- 17 files changed, 48 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index e083021e9e99c..558e44a7e6278 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -325,7 +325,8 @@ malidp_verify_afbc_framebuffer_size(struct drm_device *dev, return false; } - info = drm_get_format_info(dev, mode_cmd); + info = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); n_superblocks = (mode_cmd->width / afbc_superblock_width) * (mode_cmd->height / afbc_superblock_height); diff --git a/drivers/gpu/drm/armada/armada_fb.c b/drivers/gpu/drm/armada/armada_fb.c index cf2e88218dc0b..85fc2cb505449 100644 --- a/drivers/gpu/drm/armada/armada_fb.c +++ b/drivers/gpu/drm/armada/armada_fb.c @@ -86,7 +86,9 @@ struct armada_framebuffer *armada_framebuffer_create(struct drm_device *dev, struct drm_framebuffer *armada_fb_create(struct drm_device *dev, struct drm_file *dfile, const struct drm_mode_fb_cmd2 *mode) { - const struct drm_format_info *info = drm_get_format_info(dev, mode); + const struct drm_format_info *info = drm_get_format_info(dev, + mode->pixel_format, + mode->modifier[0]); struct armada_gem_object *obj; struct armada_framebuffer *dfb; int ret; diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c index 4b4444f6d5041..e0d5336110404 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@ -417,7 +417,8 @@ EXPORT_SYMBOL(drm_format_info); /** * drm_get_format_info - query information for a given framebuffer configuration * @dev: DRM device - * @mode_cmd: metadata from the userspace fb creation request + * @pixel_format: pixel format (DRM_FORMAT_*) + * @modifier: modifier * * Returns: * The instance of struct drm_format_info that describes the pixel format, or @@ -425,16 +426,16 @@ EXPORT_SYMBOL(drm_format_info); */ const struct drm_format_info * drm_get_format_info(struct drm_device *dev, - const struct drm_mode_fb_cmd2 *mode_cmd) + u32 pixel_format, u64 modifier) { const struct drm_format_info *info = NULL; if (dev->mode_config.funcs->get_format_info) - info = dev->mode_config.funcs->get_format_info(mode_cmd->pixel_format, - mode_cmd->modifier[0]); + info = dev->mode_config.funcs->get_format_info(pixel_format, + modifier); if (!info) - info = drm_format_info(mode_cmd->pixel_format); + info = drm_format_info(pixel_format); return info; } diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c index 63a70f285ccea..c952552916009 100644 --- a/drivers/gpu/drm/drm_framebuffer.c +++ b/drivers/gpu/drm/drm_framebuffer.c @@ -176,7 +176,7 @@ static int framebuffer_check(struct drm_device *dev, } /* now let the driver pick its own format info */ - info = drm_get_format_info(dev, r); + info = drm_get_format_info(dev, r->pixel_format, r->modifier[0]); for (i = 0; i < info->num_planes; i++) { unsigned int width = drm_format_info_plane_width(info, r->width, i); diff --git a/drivers/gpu/drm/drm_gem_framebuffer_helper.c b/drivers/gpu/drm/drm_gem_framebuffer_helper.c index fefb2a0f6b405..3af2b1ec87fb8 100644 --- a/drivers/gpu/drm/drm_gem_framebuffer_helper.c +++ b/drivers/gpu/drm/drm_gem_framebuffer_helper.c @@ -160,7 +160,8 @@ int drm_gem_fb_init_with_funcs(struct drm_device *dev, unsigned int i; int ret; - info = drm_get_format_info(dev, mode_cmd); + info = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); if (!info) { drm_dbg_kms(dev, "Failed to get FB format info\n"); return -EINVAL; @@ -506,7 +507,8 @@ static __u32 drm_gem_afbc_get_bpp(struct drm_device *dev, { const struct drm_format_info *info; - info = drm_get_format_info(dev, mode_cmd); + info = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); switch (info->format) { case DRM_FORMAT_YUV420_8BIT: @@ -604,7 +606,8 @@ int drm_gem_fb_afbc_init(struct drm_device *dev, int ret; objs = afbc_fb->base.obj; - info = drm_get_format_info(dev, mode_cmd); + info = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); if (!info) return -EINVAL; diff --git a/drivers/gpu/drm/drm_modeset_helper.c b/drivers/gpu/drm/drm_modeset_helper.c index ef32f6af10d4c..3fed2d5ab1d63 100644 --- a/drivers/gpu/drm/drm_modeset_helper.c +++ b/drivers/gpu/drm/drm_modeset_helper.c @@ -86,7 +86,8 @@ void drm_helper_mode_fill_fb_struct(struct drm_device *dev, int i; fb->dev = dev; - fb->format = drm_get_format_info(dev, mode_cmd); + fb->format = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); fb->width = mode_cmd->width; fb->height = mode_cmd->height; for (i = 0; i < 4; i++) { diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c b/drivers/gpu/drm/exynos/exynos_drm_fb.c index fc1c5608db96f..bcf7b534d1f7e 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fb.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c @@ -96,7 +96,9 @@ static struct drm_framebuffer * exynos_user_fb_create(struct drm_device *dev, struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd) { - const struct drm_format_info *info = drm_get_format_info(dev, mode_cmd); + const struct drm_format_info *info = drm_get_format_info(dev, + mode_cmd->pixel_format, + mode_cmd->modifier[0]); struct exynos_drm_gem *exynos_gem[MAX_FB_BUFFER]; struct drm_framebuffer *fb; int i; diff --git a/drivers/gpu/drm/gma500/framebuffer.c b/drivers/gpu/drm/gma500/framebuffer.c index 1a374702b6960..c82e623a20718 100644 --- a/drivers/gpu/drm/gma500/framebuffer.c +++ b/drivers/gpu/drm/gma500/framebuffer.c @@ -39,7 +39,8 @@ static int psb_framebuffer_init(struct drm_device *dev, * Reject unknown formats, YUV formats, and formats with more than * 4 bytes per pixel. */ - info = drm_get_format_info(dev, mode_cmd); + info = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); if (!info || !info->depth || info->cpp[0] > 4) return -EINVAL; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 7c0c12dde4885..0ebcfcbc258bc 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -45,7 +45,9 @@ mtk_drm_mode_fb_create(struct drm_device *dev, struct drm_file *file, const struct drm_mode_fb_cmd2 *cmd) { - const struct drm_format_info *info = drm_get_format_info(dev, cmd); + const struct drm_format_info *info = drm_get_format_info(dev, + cmd->pixel_format, + cmd->modifier[0]); if (info->num_planes != 1) return ERR_PTR(-EINVAL); diff --git a/drivers/gpu/drm/msm/msm_fb.c b/drivers/gpu/drm/msm/msm_fb.c index bc7c2bb8f01e6..d8a7ac4595bc2 100644 --- a/drivers/gpu/drm/msm/msm_fb.c +++ b/drivers/gpu/drm/msm/msm_fb.c @@ -142,7 +142,8 @@ struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd) { const struct drm_format_info *info = drm_get_format_info(dev, - mode_cmd); + mode_cmd->pixel_format, + mode_cmd->modifier[0]); struct drm_gem_object *bos[4] = {0}; struct drm_framebuffer *fb; int ret, i, n = info->num_planes; @@ -173,7 +174,8 @@ static struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos) { const struct drm_format_info *info = drm_get_format_info(dev, - mode_cmd); + mode_cmd->pixel_format, + mode_cmd->modifier[0]); struct msm_drm_private *priv = dev->dev_private; struct msm_kms *kms = priv->kms; struct msm_framebuffer *msm_fb = NULL; diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c index c183b1112bc4e..09329af9b01ea 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c @@ -95,7 +95,8 @@ mxsfb_fb_create(struct drm_device *dev, struct drm_file *file_priv, { const struct drm_format_info *info; - info = drm_get_format_info(dev, mode_cmd); + info = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); if (!info) return ERR_PTR(-EINVAL); diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index c50ec347b30a9..bd9a85f4b4fcb 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -295,7 +295,8 @@ nouveau_framebuffer_new(struct drm_device *dev, kind = nvbo->kind; } - info = drm_get_format_info(dev, mode_cmd); + info = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); for (i = 0; i < info->num_planes; i++) { height = drm_format_info_plane_height(info, diff --git a/drivers/gpu/drm/omapdrm/omap_fb.c b/drivers/gpu/drm/omapdrm/omap_fb.c index 449d521c78fed..e18878068c578 100644 --- a/drivers/gpu/drm/omapdrm/omap_fb.c +++ b/drivers/gpu/drm/omapdrm/omap_fb.c @@ -338,7 +338,8 @@ struct drm_framebuffer *omap_framebuffer_create(struct drm_device *dev, struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd) { const struct drm_format_info *info = drm_get_format_info(dev, - mode_cmd); + mode_cmd->pixel_format, + mode_cmd->modifier[0]); unsigned int num_planes = info->num_planes; struct drm_gem_object *bos[4]; struct drm_framebuffer *fb; @@ -378,7 +379,8 @@ struct drm_framebuffer *omap_framebuffer_init(struct drm_device *dev, dev, mode_cmd, mode_cmd->width, mode_cmd->height, (char *)&mode_cmd->pixel_format); - format = drm_get_format_info(dev, mode_cmd); + format = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); for (i = 0; i < ARRAY_SIZE(formats); i++) { if (formats[i] == mode_cmd->pixel_format) diff --git a/drivers/gpu/drm/radeon/radeon_fbdev.c b/drivers/gpu/drm/radeon/radeon_fbdev.c index d4a58bd679dbc..e3a481bbee7b6 100644 --- a/drivers/gpu/drm/radeon/radeon_fbdev.c +++ b/drivers/gpu/drm/radeon/radeon_fbdev.c @@ -67,7 +67,8 @@ static int radeon_fbdev_create_pinned_object(struct drm_fb_helper *fb_helper, int height = mode_cmd->height; u32 cpp; - info = drm_get_format_info(rdev_to_drm(rdev), mode_cmd); + info = drm_get_format_info(rdev_to_drm(rdev), mode_cmd->pixel_format, + mode_cmd->modifier[0]); cpp = info->cpp[0]; /* need to align pitch with crtc limits */ diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c index 5829ee061c61b..66762ca54a98e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c @@ -36,7 +36,8 @@ rockchip_fb_create(struct drm_device *dev, struct drm_file *file, const struct drm_format_info *info; int ret; - info = drm_get_format_info(dev, mode_cmd); + info = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); if (!info) return ERR_PTR(-ENOMEM); diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c index 46170753699dc..634c6346d947f 100644 --- a/drivers/gpu/drm/tegra/fb.c +++ b/drivers/gpu/drm/tegra/fb.c @@ -134,7 +134,9 @@ struct drm_framebuffer *tegra_fb_create(struct drm_device *drm, struct drm_file *file, const struct drm_mode_fb_cmd2 *cmd) { - const struct drm_format_info *info = drm_get_format_info(drm, cmd); + const struct drm_format_info *info = drm_get_format_info(drm, + cmd->pixel_format, + cmd->modifier[0]); struct tegra_bo *planes[4]; struct drm_gem_object *gem; struct drm_framebuffer *fb; diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h index c3f4405d66629..4717844268573 100644 --- a/include/drm/drm_fourcc.h +++ b/include/drm/drm_fourcc.h @@ -54,7 +54,6 @@ #endif struct drm_device; -struct drm_mode_fb_cmd2; /** * struct drm_format_info - information about a DRM format @@ -309,7 +308,7 @@ const struct drm_format_info *__drm_format_info(u32 format); const struct drm_format_info *drm_format_info(u32 format); const struct drm_format_info * drm_get_format_info(struct drm_device *dev, - const struct drm_mode_fb_cmd2 *mode_cmd); + u32 pixel_format, u64 modifier); uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t depth); uint32_t drm_driver_legacy_fb_format(struct drm_device *dev, uint32_t bpp, uint32_t depth); From 6b50355612c0d43dd040377bf2f8950a4209fa83 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 1 Jul 2025 12:07:06 +0300 Subject: [PATCH 1985/2653] drm: Look up the format info earlier MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Look up the format info already in drm_internal_framebuffer_create() so that we can later pass it along to .fb_create(). Currently various drivers are doing additional lookups in their .fb_create() implementations, and these lookups are rather expensive now (given how many different pixel formats we have). v2: Fix commit msg (Thomas) Reviewed-by: Thomas Zimmermann Reviewed-by: Laurent Pinchart Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250701090722.13645-4-ville.syrjala@linux.intel.com --- drivers/gpu/drm/drm_framebuffer.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c index c952552916009..1f286087ba307 100644 --- a/drivers/gpu/drm/drm_framebuffer.c +++ b/drivers/gpu/drm/drm_framebuffer.c @@ -153,18 +153,11 @@ int drm_mode_addfb_ioctl(struct drm_device *dev, } static int framebuffer_check(struct drm_device *dev, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *r) { - const struct drm_format_info *info; int i; - /* check if the format is supported at all */ - if (!__drm_format_info(r->pixel_format)) { - drm_dbg_kms(dev, "bad framebuffer format %p4cc\n", - &r->pixel_format); - return -EINVAL; - } - if (r->width == 0) { drm_dbg_kms(dev, "bad framebuffer width %u\n", r->width); return -EINVAL; @@ -175,9 +168,6 @@ static int framebuffer_check(struct drm_device *dev, return -EINVAL; } - /* now let the driver pick its own format info */ - info = drm_get_format_info(dev, r->pixel_format, r->modifier[0]); - for (i = 0; i < info->num_planes; i++) { unsigned int width = drm_format_info_plane_width(info, r->width, i); unsigned int height = drm_format_info_plane_height(info, r->height, i); @@ -272,6 +262,7 @@ drm_internal_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv) { struct drm_mode_config *config = &dev->mode_config; + const struct drm_format_info *info; struct drm_framebuffer *fb; int ret; @@ -297,7 +288,17 @@ drm_internal_framebuffer_create(struct drm_device *dev, return ERR_PTR(-EINVAL); } - ret = framebuffer_check(dev, r); + /* check if the format is supported at all */ + if (!__drm_format_info(r->pixel_format)) { + drm_dbg_kms(dev, "bad framebuffer format %p4cc\n", + &r->pixel_format); + return ERR_PTR(-EINVAL); + } + + /* now let the driver pick its own format info */ + info = drm_get_format_info(dev, r->pixel_format, r->modifier[0]); + + ret = framebuffer_check(dev, info, r); if (ret) return ERR_PTR(ret); From d3fa9976395e7714efa784c370199ff2d8c2274c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 1 Jul 2025 12:07:07 +0300 Subject: [PATCH 1986/2653] drm: Pass the format info to .fb_create() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pass along the format information from the top to .fb_create() so that we can avoid redundant (and somewhat expensive) lookups in the drivers. Done with cocci (with some manual fixups): @@ identifier func =~ ".*create.*"; identifier dev, file, mode_cmd; @@ struct drm_framebuffer *func( struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { ... ( - const struct drm_format_info *info = drm_get_format_info(...); | - const struct drm_format_info *info; ... - info = drm_get_format_info(...); ) <... - if (!info) - return ...; ...> } @@ identifier func =~ ".*create.*"; identifier dev, file, mode_cmd; @@ struct drm_framebuffer *func( struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { ... } @find@ identifier fb_create_func =~ ".*create.*"; identifier dev, file, mode_cmd; @@ struct drm_framebuffer *fb_create_func( struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd); @@ identifier find.fb_create_func; expression dev, file, mode_cmd; @@ fb_create_func(dev, file + ,info ,mode_cmd) @@ expression dev, file, mode_cmd; @@ drm_gem_fb_create(dev, file + ,info ,mode_cmd) @@ expression dev, file, mode_cmd; @@ drm_gem_fb_create_with_dirty(dev, file + ,info ,mode_cmd) @@ expression dev, file_priv, mode_cmd; identifier info, fb; @@ info = drm_get_format_info(...); ... fb = dev->mode_config.funcs->fb_create(dev, file_priv + ,info ,mode_cmd); @@ identifier dev, file_priv, mode_cmd; @@ struct drm_mode_config_funcs { ... struct drm_framebuffer *(*fb_create)(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd); ... }; v2: Fix kernel docs (Laurent) Fix commit msg (Geert) Cc: Alex Deucher Cc: Liviu Dudau Cc: Maxime Ripard Cc: Russell King Cc: Inki Dae Cc: Seung-Woo Kim Cc: Kyungmin Park Cc: Patrik Jakobsson Cc: Chun-Kuang Hu Cc: Philipp Zabel Cc: Rob Clark Cc: Abhinav Kumar Cc: Dmitry Baryshkov Cc: Sean Paul Cc: Marijn Suijten Cc: Marek Vasut Cc: Stefan Agner Cc: Lyude Paul Cc: Danilo Krummrich Cc: Tomi Valkeinen Cc: Dave Airlie Cc: Gerd Hoffmann Cc: Kieran Bingham Cc: Biju Das Cc: Sandy Huang Cc: "Heiko Stübner" Cc: Andy Yan Cc: Thierry Reding Cc: Mikko Perttunen Cc: Dave Stevenson Cc: "Maíra Canal" Cc: Raspberry Pi Kernel Maintenance Cc: Dmitry Osipenko Cc: Gurchetan Singh Cc: Chia-I Wu Cc: Zack Rusin Cc: Broadcom internal kernel review list Cc: Oleksandr Andrushchenko Cc: amd-gfx@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Cc: nouveau@lists.freedesktop.org Cc: virtualization@lists.linux.dev Cc: spice-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Reviewed-by: Thomas Zimmermann Reviewed-by: Dmitry Baryshkov Acked-by: Liviu Dudau Reviewed-by: Laurent Pinchart Acked-by: Alex Deucher Acked-by: Rodrigo Vivi Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250701090722.13645-5-ville.syrjala@linux.intel.com --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 1 + .../gpu/drm/arm/display/komeda/komeda_framebuffer.c | 1 + .../gpu/drm/arm/display/komeda/komeda_framebuffer.h | 1 + drivers/gpu/drm/arm/malidp_drv.c | 3 ++- drivers/gpu/drm/armada/armada_fb.c | 6 ++---- drivers/gpu/drm/armada/armada_fb.h | 3 ++- drivers/gpu/drm/drm_framebuffer.c | 2 +- drivers/gpu/drm/drm_gem_framebuffer_helper.c | 4 ++++ drivers/gpu/drm/exynos/exynos_drm_fb.c | 4 +--- drivers/gpu/drm/gma500/framebuffer.c | 1 + drivers/gpu/drm/i915/display/intel_fb.c | 1 + drivers/gpu/drm/i915/display/intel_fb.h | 1 + drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 5 +++-- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 7 ++----- drivers/gpu/drm/msm/msm_drv.h | 3 ++- drivers/gpu/drm/msm/msm_fb.c | 6 ++---- drivers/gpu/drm/mxsfb/mxsfb_drv.c | 10 ++-------- drivers/gpu/drm/nouveau/nouveau_display.c | 1 + drivers/gpu/drm/nouveau/nouveau_display.h | 1 + drivers/gpu/drm/omapdrm/omap_fb.c | 6 ++---- drivers/gpu/drm/omapdrm/omap_fb.h | 3 ++- drivers/gpu/drm/qxl/qxl_display.c | 1 + drivers/gpu/drm/radeon/radeon_display.c | 1 + drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c | 3 ++- drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c | 3 ++- drivers/gpu/drm/renesas/shmobile/shmob_drm_kms.c | 3 ++- drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 7 +------ drivers/gpu/drm/tegra/drm.h | 1 + drivers/gpu/drm/tegra/fb.c | 4 +--- drivers/gpu/drm/tests/drm_framebuffer_test.c | 1 + drivers/gpu/drm/vc4/vc4_kms.c | 3 ++- drivers/gpu/drm/virtio/virtgpu_display.c | 1 + drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 1 + drivers/gpu/drm/xen/xen_drm_front_kms.c | 1 + drivers/gpu/drm/xlnx/zynqmp_kms.c | 3 ++- include/drm/drm_gem_framebuffer_helper.h | 3 +++ include/drm/drm_mode_config.h | 1 + 38 files changed, 59 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index e84be362b6ae1..11aa38d8e9ffc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1345,6 +1345,7 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, struct drm_framebuffer * amdgpu_display_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct amdgpu_framebuffer *amdgpu_fb; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h index 4eaee10a1b7c0..4309b0e0849e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h @@ -44,6 +44,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, struct drm_framebuffer * amdgpu_display_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd); const struct drm_format_info * amdgpu_lookup_format_info(u32 format, uint64_t modifier); diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c b/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c index df5da5a447555..29b05482f713f 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c @@ -157,6 +157,7 @@ komeda_fb_none_afbc_size_check(struct komeda_dev *mdev, struct komeda_fb *kfb, struct drm_framebuffer * komeda_fb_create(struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct komeda_dev *mdev = dev->dev_private; diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.h b/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.h index c61ca98a3a637..02b2b8ae482ae 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.h @@ -37,6 +37,7 @@ struct komeda_fb { struct drm_framebuffer * komeda_fb_create(struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd); int komeda_fb_check_src_coords(const struct komeda_fb *kfb, u32 src_x, u32 src_y, u32 src_w, u32 src_h); diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index 558e44a7e6278..8b920566f2e89 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -377,6 +377,7 @@ malidp_verify_afbc_framebuffer(struct drm_device *dev, struct drm_file *file, static struct drm_framebuffer * malidp_fb_create(struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { if (mode_cmd->modifier[0]) { @@ -384,7 +385,7 @@ malidp_fb_create(struct drm_device *dev, struct drm_file *file, return ERR_PTR(-EINVAL); } - return drm_gem_fb_create(dev, file, mode_cmd); + return drm_gem_fb_create(dev, file, info, mode_cmd); } static const struct drm_mode_config_funcs malidp_mode_config_funcs = { diff --git a/drivers/gpu/drm/armada/armada_fb.c b/drivers/gpu/drm/armada/armada_fb.c index 85fc2cb505449..597720e229c26 100644 --- a/drivers/gpu/drm/armada/armada_fb.c +++ b/drivers/gpu/drm/armada/armada_fb.c @@ -84,11 +84,9 @@ struct armada_framebuffer *armada_framebuffer_create(struct drm_device *dev, } struct drm_framebuffer *armada_fb_create(struct drm_device *dev, - struct drm_file *dfile, const struct drm_mode_fb_cmd2 *mode) + struct drm_file *dfile, const struct drm_format_info *info, + const struct drm_mode_fb_cmd2 *mode) { - const struct drm_format_info *info = drm_get_format_info(dev, - mode->pixel_format, - mode->modifier[0]); struct armada_gem_object *obj; struct armada_framebuffer *dfb; int ret; diff --git a/drivers/gpu/drm/armada/armada_fb.h b/drivers/gpu/drm/armada/armada_fb.h index c5bc53d7e0c4c..41ba76dd80d6f 100644 --- a/drivers/gpu/drm/armada/armada_fb.h +++ b/drivers/gpu/drm/armada/armada_fb.h @@ -19,5 +19,6 @@ struct armada_framebuffer { struct armada_framebuffer *armada_framebuffer_create(struct drm_device *, const struct drm_mode_fb_cmd2 *, struct armada_gem_object *); struct drm_framebuffer *armada_fb_create(struct drm_device *dev, - struct drm_file *dfile, const struct drm_mode_fb_cmd2 *mode); + struct drm_file *dfile, const struct drm_format_info *info, + const struct drm_mode_fb_cmd2 *mode); #endif diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c index 1f286087ba307..adbb73f00d68b 100644 --- a/drivers/gpu/drm/drm_framebuffer.c +++ b/drivers/gpu/drm/drm_framebuffer.c @@ -302,7 +302,7 @@ drm_internal_framebuffer_create(struct drm_device *dev, if (ret) return ERR_PTR(ret); - fb = dev->mode_config.funcs->fb_create(dev, file_priv, r); + fb = dev->mode_config.funcs->fb_create(dev, file_priv, info, r); if (IS_ERR(fb)) { drm_dbg_kms(dev, "could not create framebuffer\n"); return fb; diff --git a/drivers/gpu/drm/drm_gem_framebuffer_helper.c b/drivers/gpu/drm/drm_gem_framebuffer_helper.c index 3af2b1ec87fb8..982f7abd5eb57 100644 --- a/drivers/gpu/drm/drm_gem_framebuffer_helper.c +++ b/drivers/gpu/drm/drm_gem_framebuffer_helper.c @@ -264,6 +264,7 @@ static const struct drm_framebuffer_funcs drm_gem_fb_funcs = { * &drm_mode_config_funcs.fb_create callback * @dev: DRM device * @file: DRM file that holds the GEM handle(s) backing the framebuffer + * @info: pixel format information * @mode_cmd: Metadata from the userspace framebuffer creation request * * This function creates a new framebuffer object described by @@ -283,6 +284,7 @@ static const struct drm_framebuffer_funcs drm_gem_fb_funcs = { */ struct drm_framebuffer * drm_gem_fb_create(struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { return drm_gem_fb_create_with_funcs(dev, file, mode_cmd, @@ -301,6 +303,7 @@ static const struct drm_framebuffer_funcs drm_gem_fb_funcs_dirtyfb = { * &drm_mode_config_funcs.fb_create callback * @dev: DRM device * @file: DRM file that holds the GEM handle(s) backing the framebuffer + * @info: pixel format information * @mode_cmd: Metadata from the userspace framebuffer creation request * * This function creates a new framebuffer object described by @@ -321,6 +324,7 @@ static const struct drm_framebuffer_funcs drm_gem_fb_funcs_dirtyfb = { */ struct drm_framebuffer * drm_gem_fb_create_with_dirty(struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { return drm_gem_fb_create_with_funcs(dev, file, mode_cmd, diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c b/drivers/gpu/drm/exynos/exynos_drm_fb.c index bcf7b534d1f7e..9ae526825726c 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fb.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c @@ -94,11 +94,9 @@ exynos_drm_framebuffer_init(struct drm_device *dev, static struct drm_framebuffer * exynos_user_fb_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { - const struct drm_format_info *info = drm_get_format_info(dev, - mode_cmd->pixel_format, - mode_cmd->modifier[0]); struct exynos_drm_gem *exynos_gem[MAX_FB_BUFFER]; struct drm_framebuffer *fb; int i; diff --git a/drivers/gpu/drm/gma500/framebuffer.c b/drivers/gpu/drm/gma500/framebuffer.c index c82e623a20718..a4a18ec2dd566 100644 --- a/drivers/gpu/drm/gma500/framebuffer.c +++ b/drivers/gpu/drm/gma500/framebuffer.c @@ -97,6 +97,7 @@ struct drm_framebuffer *psb_framebuffer_create(struct drm_device *dev, */ static struct drm_framebuffer *psb_user_framebuffer_create (struct drm_device *dev, struct drm_file *filp, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *cmd) { struct drm_gem_object *obj; diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index e221db072de23..96edc791c33bb 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -2324,6 +2324,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, struct drm_framebuffer * intel_user_framebuffer_create(struct drm_device *dev, struct drm_file *filp, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *user_mode_cmd) { struct drm_framebuffer *fb; diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index 7d1267fbeee26..00181c4a67dc8 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -109,6 +109,7 @@ intel_framebuffer_create(struct drm_gem_object *obj, struct drm_framebuffer * intel_user_framebuffer_create(struct drm_device *dev, struct drm_file *filp, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *user_mode_cmd); bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier); diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c index f851e9ffdb280..9db1ceaed5188 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c @@ -901,14 +901,15 @@ static void ingenic_drm_disable_vblank(struct drm_crtc *crtc) static struct drm_framebuffer * ingenic_drm_gem_fb_create(struct drm_device *drm, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct ingenic_drm *priv = drm_device_get_priv(drm); if (priv->soc_info->map_noncoherent) - return drm_gem_fb_create_with_dirty(drm, file, mode_cmd); + return drm_gem_fb_create_with_dirty(drm, file, info, mode_cmd); - return drm_gem_fb_create(drm, file, mode_cmd); + return drm_gem_fb_create(drm, file, info, mode_cmd); } static struct drm_gem_object * diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 0ebcfcbc258bc..d5e6bab364143 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -43,16 +43,13 @@ static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = { static struct drm_framebuffer * mtk_drm_mode_fb_create(struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *cmd) { - const struct drm_format_info *info = drm_get_format_info(dev, - cmd->pixel_format, - cmd->modifier[0]); - if (info->num_planes != 1) return ERR_PTR(-EINVAL); - return drm_gem_fb_create(dev, file, cmd); + return drm_gem_fb_create(dev, file, info, cmd); } static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 9875ca62e9adb..985db9febd98e 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -260,7 +260,8 @@ uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int plane); struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, - struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); + struct drm_file *file, const struct drm_format_info *info, + const struct drm_mode_fb_cmd2 *mode_cmd); struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, int w, int h, int p, uint32_t format); diff --git a/drivers/gpu/drm/msm/msm_fb.c b/drivers/gpu/drm/msm/msm_fb.c index d8a7ac4595bc2..f151244e8cfb3 100644 --- a/drivers/gpu/drm/msm/msm_fb.c +++ b/drivers/gpu/drm/msm/msm_fb.c @@ -139,11 +139,9 @@ const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb) } struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, - struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd) + struct drm_file *file, const struct drm_format_info *info, + const struct drm_mode_fb_cmd2 *mode_cmd) { - const struct drm_format_info *info = drm_get_format_info(dev, - mode_cmd->pixel_format, - mode_cmd->modifier[0]); struct drm_gem_object *bos[4] = {0}; struct drm_framebuffer *fb; int ret, i, n = info->num_planes; diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c index 09329af9b01ea..0b756da2fec22 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c @@ -91,21 +91,15 @@ void mxsfb_disable_axi_clk(struct mxsfb_drm_private *mxsfb) static struct drm_framebuffer * mxsfb_fb_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { - const struct drm_format_info *info; - - info = drm_get_format_info(dev, mode_cmd->pixel_format, - mode_cmd->modifier[0]); - if (!info) - return ERR_PTR(-EINVAL); - if (mode_cmd->width * info->cpp[0] != mode_cmd->pitches[0]) { dev_dbg(dev->dev, "Invalid pitch: fb width must match pitch\n"); return ERR_PTR(-EINVAL); } - return drm_gem_fb_create(dev, file_priv, mode_cmd); + return drm_gem_fb_create(dev, file_priv, info, mode_cmd); } static const struct drm_mode_config_funcs mxsfb_mode_config_funcs = { diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index bd9a85f4b4fcb..1ddd929015262 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -333,6 +333,7 @@ nouveau_framebuffer_new(struct drm_device *dev, struct drm_framebuffer * nouveau_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct drm_framebuffer *fb; diff --git a/drivers/gpu/drm/nouveau/nouveau_display.h b/drivers/gpu/drm/nouveau/nouveau_display.h index 1f506f8b289c9..e45f211501f61 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.h +++ b/drivers/gpu/drm/nouveau/nouveau_display.h @@ -67,5 +67,6 @@ nouveau_framebuffer_get_layout(struct drm_framebuffer *fb, uint32_t *tile_mode, struct drm_framebuffer * nouveau_user_framebuffer_create(struct drm_device *, struct drm_file *, + const struct drm_format_info *, const struct drm_mode_fb_cmd2 *); #endif diff --git a/drivers/gpu/drm/omapdrm/omap_fb.c b/drivers/gpu/drm/omapdrm/omap_fb.c index e18878068c578..36afcd1c1fd74 100644 --- a/drivers/gpu/drm/omapdrm/omap_fb.c +++ b/drivers/gpu/drm/omapdrm/omap_fb.c @@ -335,11 +335,9 @@ void omap_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m) #endif struct drm_framebuffer *omap_framebuffer_create(struct drm_device *dev, - struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd) + struct drm_file *file, const struct drm_format_info *info, + const struct drm_mode_fb_cmd2 *mode_cmd) { - const struct drm_format_info *info = drm_get_format_info(dev, - mode_cmd->pixel_format, - mode_cmd->modifier[0]); unsigned int num_planes = info->num_planes; struct drm_gem_object *bos[4]; struct drm_framebuffer *fb; diff --git a/drivers/gpu/drm/omapdrm/omap_fb.h b/drivers/gpu/drm/omapdrm/omap_fb.h index b75f0b5ef1d8c..0873f953cf1d1 100644 --- a/drivers/gpu/drm/omapdrm/omap_fb.h +++ b/drivers/gpu/drm/omapdrm/omap_fb.h @@ -20,7 +20,8 @@ struct omap_overlay_info; struct seq_file; struct drm_framebuffer *omap_framebuffer_create(struct drm_device *dev, - struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); + struct drm_file *file, const struct drm_format_info *info, + const struct drm_mode_fb_cmd2 *mode_cmd); struct drm_framebuffer *omap_framebuffer_init(struct drm_device *dev, const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); int omap_framebuffer_pin(struct drm_framebuffer *fb); diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c index 70aff64ced87a..f7bc83f2d4893 100644 --- a/drivers/gpu/drm/qxl/qxl_display.c +++ b/drivers/gpu/drm/qxl/qxl_display.c @@ -1176,6 +1176,7 @@ static int qdev_output_init(struct drm_device *dev, int num_output) static struct drm_framebuffer * qxl_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { return drm_gem_fb_create_with_funcs(dev, file_priv, mode_cmd, diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 79cbd0c71d5d4..b4aa2bc51bfd5 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -1314,6 +1314,7 @@ radeon_framebuffer_init(struct drm_device *dev, static struct drm_framebuffer * radeon_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct drm_gem_object *obj; diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c index 4c8fe83dd6101..216219accfd9d 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c @@ -426,6 +426,7 @@ int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev, static struct drm_framebuffer * rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct rcar_du_device *rcdu = to_rcar_du_device(dev); @@ -490,7 +491,7 @@ rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv, } } - return drm_gem_fb_create(dev, file_priv, mode_cmd); + return drm_gem_fb_create(dev, file_priv, info, mode_cmd); } /* ----------------------------------------------------------------------------- diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c index 55a97691e9b25..87f171145a230 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c @@ -191,6 +191,7 @@ int rzg2l_du_dumb_create(struct drm_file *file, struct drm_device *dev, static struct drm_framebuffer * rzg2l_du_fb_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { const struct rzg2l_du_format_info *format; @@ -214,7 +215,7 @@ rzg2l_du_fb_create(struct drm_device *dev, struct drm_file *file_priv, return ERR_PTR(-EINVAL); } - return drm_gem_fb_create(dev, file_priv, mode_cmd); + return drm_gem_fb_create(dev, file_priv, info, mode_cmd); } /* ----------------------------------------------------------------------------- diff --git a/drivers/gpu/drm/renesas/shmobile/shmob_drm_kms.c b/drivers/gpu/drm/renesas/shmobile/shmob_drm_kms.c index 4202ab00fb0cf..fd9460da1789b 100644 --- a/drivers/gpu/drm/renesas/shmobile/shmob_drm_kms.c +++ b/drivers/gpu/drm/renesas/shmobile/shmob_drm_kms.c @@ -117,6 +117,7 @@ const struct shmob_drm_format_info *shmob_drm_format_info(u32 fourcc) static struct drm_framebuffer * shmob_drm_fb_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { const struct shmob_drm_format_info *format; @@ -144,7 +145,7 @@ shmob_drm_fb_create(struct drm_device *dev, struct drm_file *file_priv, } } - return drm_gem_fb_create(dev, file_priv, mode_cmd); + return drm_gem_fb_create(dev, file_priv, info, mode_cmd); } static const struct drm_mode_config_funcs shmob_drm_mode_config_funcs = { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c index 66762ca54a98e..f19113e5ae8fa 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c @@ -30,17 +30,12 @@ static const struct drm_mode_config_helper_funcs rockchip_mode_config_helpers = static struct drm_framebuffer * rockchip_fb_create(struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct drm_afbc_framebuffer *afbc_fb; - const struct drm_format_info *info; int ret; - info = drm_get_format_info(dev, mode_cmd->pixel_format, - mode_cmd->modifier[0]); - if (!info) - return ERR_PTR(-ENOMEM); - afbc_fb = kzalloc(sizeof(*afbc_fb), GFP_KERNEL); if (!afbc_fb) return ERR_PTR(-ENOMEM); diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index 0b65e69f3a8ad..77e520c43f72c 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h @@ -190,6 +190,7 @@ struct drm_framebuffer *tegra_fb_alloc(struct drm_device *drm, unsigned int num_planes); struct drm_framebuffer *tegra_fb_create(struct drm_device *drm, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *cmd); #ifdef CONFIG_DRM_FBDEV_EMULATION diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c index 634c6346d947f..24907573e758d 100644 --- a/drivers/gpu/drm/tegra/fb.c +++ b/drivers/gpu/drm/tegra/fb.c @@ -132,11 +132,9 @@ struct drm_framebuffer *tegra_fb_alloc(struct drm_device *drm, struct drm_framebuffer *tegra_fb_create(struct drm_device *drm, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *cmd) { - const struct drm_format_info *info = drm_get_format_info(drm, - cmd->pixel_format, - cmd->modifier[0]); struct tegra_bo *planes[4]; struct drm_gem_object *gem; struct drm_framebuffer *fb; diff --git a/drivers/gpu/drm/tests/drm_framebuffer_test.c b/drivers/gpu/drm/tests/drm_framebuffer_test.c index 6ea04cc8f3241..9b8e01e8cd91b 100644 --- a/drivers/gpu/drm/tests/drm_framebuffer_test.c +++ b/drivers/gpu/drm/tests/drm_framebuffer_test.c @@ -363,6 +363,7 @@ struct drm_framebuffer_test_priv { static struct drm_framebuffer *fb_create_mock(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct drm_framebuffer_test_priv *priv = container_of(dev, typeof(*priv), dev); diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c index f5b1674174289..8f983edb81ff0 100644 --- a/drivers/gpu/drm/vc4/vc4_kms.c +++ b/drivers/gpu/drm/vc4/vc4_kms.c @@ -530,6 +530,7 @@ static int vc4_atomic_commit_setup(struct drm_atomic_state *state) static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct vc4_dev *vc4 = to_vc4_dev(dev); @@ -568,7 +569,7 @@ static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev, mode_cmd = &mode_cmd_local; } - return drm_gem_fb_create(dev, file_priv, mode_cmd); + return drm_gem_fb_create(dev, file_priv, info, mode_cmd); } /* Our CTM has some peculiar limitations: we can only enable it for one CRTC diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c b/drivers/gpu/drm/virtio/virtgpu_display.c index 59a45e74a6412..f9a98fbbabd1a 100644 --- a/drivers/gpu/drm/virtio/virtgpu_display.c +++ b/drivers/gpu/drm/virtio/virtgpu_display.c @@ -293,6 +293,7 @@ static int vgdev_output_init(struct virtio_gpu_device *vgdev, int index) static struct drm_framebuffer * virtio_gpu_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct drm_gem_object *obj = NULL; diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c index 05b1c54a070cb..2d48a28cda9c0 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c @@ -712,6 +712,7 @@ vmw_kms_new_framebuffer(struct vmw_private *dev_priv, static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct vmw_private *dev_priv = vmw_priv(dev); diff --git a/drivers/gpu/drm/xen/xen_drm_front_kms.c b/drivers/gpu/drm/xen/xen_drm_front_kms.c index dfa78a49a6d95..a360003bee471 100644 --- a/drivers/gpu/drm/xen/xen_drm_front_kms.c +++ b/drivers/gpu/drm/xen/xen_drm_front_kms.c @@ -54,6 +54,7 @@ static const struct drm_framebuffer_funcs fb_funcs = { static struct drm_framebuffer * fb_create(struct drm_device *dev, struct drm_file *filp, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct xen_drm_front_drm_info *drm_info = dev->dev_private; diff --git a/drivers/gpu/drm/xlnx/zynqmp_kms.c b/drivers/gpu/drm/xlnx/zynqmp_kms.c index b474634734728..2bee0a2275ede 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_kms.c +++ b/drivers/gpu/drm/xlnx/zynqmp_kms.c @@ -373,6 +373,7 @@ static int zynqmp_dpsub_dumb_create(struct drm_file *file_priv, static struct drm_framebuffer * zynqmp_dpsub_fb_create(struct drm_device *drm, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct zynqmp_dpsub *dpsub = to_zynqmp_dpsub(drm); @@ -383,7 +384,7 @@ zynqmp_dpsub_fb_create(struct drm_device *drm, struct drm_file *file_priv, for (i = 0; i < ARRAY_SIZE(cmd.pitches); ++i) cmd.pitches[i] = ALIGN(cmd.pitches[i], dpsub->dma_align); - return drm_gem_fb_create(drm, file_priv, &cmd); + return drm_gem_fb_create(drm, file_priv, info, &cmd); } static const struct drm_mode_config_funcs zynqmp_dpsub_mode_config_funcs = { diff --git a/include/drm/drm_gem_framebuffer_helper.h b/include/drm/drm_gem_framebuffer_helper.h index d302521f3dd48..4fdf9d3d18638 100644 --- a/include/drm/drm_gem_framebuffer_helper.h +++ b/include/drm/drm_gem_framebuffer_helper.h @@ -8,6 +8,7 @@ struct drm_afbc_framebuffer; struct drm_device; struct drm_fb_helper_surface_size; struct drm_file; +struct drm_format_info; struct drm_framebuffer; struct drm_framebuffer_funcs; struct drm_gem_object; @@ -32,9 +33,11 @@ drm_gem_fb_create_with_funcs(struct drm_device *dev, struct drm_file *file, const struct drm_framebuffer_funcs *funcs); struct drm_framebuffer * drm_gem_fb_create(struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd); struct drm_framebuffer * drm_gem_fb_create_with_dirty(struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd); int drm_gem_fb_vmap(struct drm_framebuffer *fb, struct iosys_map *map, diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h index e971e1b8a850c..2e848b8162185 100644 --- a/include/drm/drm_mode_config.h +++ b/include/drm/drm_mode_config.h @@ -82,6 +82,7 @@ struct drm_mode_config_funcs { */ struct drm_framebuffer *(*fb_create)(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd); /** From befa117f5667992c4202281cb6c86d93a4dd1a16 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 1 Jul 2025 12:07:08 +0300 Subject: [PATCH 1987/2653] drm: Allow the caller to pass in the format info to drm_helper_mode_fill_fb_struct() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Soon all drivers should have the format info already available in the places where they call drm_helper_mode_fill_fb_struct(). Allow it to be passed along into drm_helper_mode_fill_fb_struct() instead of doing yet another redundant lookup. Start by always passing in NULL and still doing the extra lookup. The actual changes to avoid the lookup will follow. Done with cocci (with some manual fixups): @@ identifier dev, fb, mode_cmd; expression get_format_info; @@ void drm_helper_mode_fill_fb_struct(struct drm_device *dev, struct drm_framebuffer *fb, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { ... - fb->format = get_format_info; + fb->format = info ?: get_format_info; ... } @@ identifier dev, fb, mode_cmd; @@ void drm_helper_mode_fill_fb_struct(struct drm_device *dev, struct drm_framebuffer *fb, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd); @@ expression dev, fb, mode_cmd; @@ drm_helper_mode_fill_fb_struct(dev, fb + ,NULL ,mode_cmd); Cc: Alex Deucher Cc: Liviu Dudau Cc: Russell King Cc: Inki Dae Cc: Seung-Woo Kim Cc: Kyungmin Park Cc: Patrik Jakobsson Cc: Rob Clark Cc: Abhinav Kumar Cc: Dmitry Baryshkov Cc: Sean Paul Cc: Marijn Suijten Cc: Lyude Paul Cc: Danilo Krummrich Cc: Tomi Valkeinen Cc: Thierry Reding Cc: Mikko Perttunen Cc: Gerd Hoffmann Cc: Dmitry Osipenko Cc: Gurchetan Singh Cc: Chia-I Wu Cc: Zack Rusin Cc: Broadcom internal kernel review list Cc: amd-gfx@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Cc: nouveau@lists.freedesktop.org Cc: linux-tegra@vger.kernel.org Cc: virtualization@lists.linux.dev Reviewed-by: Thomas Zimmermann Reviewed-by: Laurent Pinchart Reviewed-by: Dmitry Baryshkov Reviewed-by: Liviu Dudau Acked-by: Alex Deucher Acked-by: Rodrigo Vivi Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250701090722.13645-6-ville.syrjala@linux.intel.com --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 3 +-- drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c | 2 +- drivers/gpu/drm/armada/armada_fb.c | 2 +- drivers/gpu/drm/drm_gem_framebuffer_helper.c | 2 +- drivers/gpu/drm/drm_modeset_helper.c | 6 ++++-- drivers/gpu/drm/exynos/exynos_drm_fb.c | 2 +- drivers/gpu/drm/gma500/framebuffer.c | 2 +- drivers/gpu/drm/i915/display/intel_fb.c | 2 +- drivers/gpu/drm/msm/msm_fb.c | 2 +- drivers/gpu/drm/nouveau/nouveau_display.c | 2 +- drivers/gpu/drm/omapdrm/omap_fb.c | 2 +- drivers/gpu/drm/radeon/radeon_display.c | 2 +- drivers/gpu/drm/tegra/fb.c | 2 +- drivers/gpu/drm/virtio/virtgpu_display.c | 2 +- drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 4 ++-- include/drm/drm_modeset_helper.h | 2 ++ 16 files changed, 21 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 11aa38d8e9ffc..ec30425cd68e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1235,8 +1235,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, int ret; rfb->base.obj[0] = obj; - drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); - + drm_helper_mode_fill_fb_struct(dev, &rfb->base, NULL, mode_cmd); #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED /* Verify that the modifier is supported. */ if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c b/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c index 29b05482f713f..acd8e505ebc71 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c @@ -178,7 +178,7 @@ komeda_fb_create(struct drm_device *dev, struct drm_file *file, return ERR_PTR(-EINVAL); } - drm_helper_mode_fill_fb_struct(dev, &kfb->base, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, &kfb->base, NULL, mode_cmd); if (kfb->base.modifier) ret = komeda_fb_afbc_size_check(kfb, file, mode_cmd); diff --git a/drivers/gpu/drm/armada/armada_fb.c b/drivers/gpu/drm/armada/armada_fb.c index 597720e229c26..7e94ec5bd4f4e 100644 --- a/drivers/gpu/drm/armada/armada_fb.c +++ b/drivers/gpu/drm/armada/armada_fb.c @@ -64,7 +64,7 @@ struct armada_framebuffer *armada_framebuffer_create(struct drm_device *dev, dfb->mod = config; dfb->fb.obj[0] = &obj->obj; - drm_helper_mode_fill_fb_struct(dev, &dfb->fb, mode); + drm_helper_mode_fill_fb_struct(dev, &dfb->fb, NULL, mode); ret = drm_framebuffer_init(dev, &dfb->fb, &armada_fb_funcs); if (ret) { diff --git a/drivers/gpu/drm/drm_gem_framebuffer_helper.c b/drivers/gpu/drm/drm_gem_framebuffer_helper.c index 982f7abd5eb57..6811ba13533f9 100644 --- a/drivers/gpu/drm/drm_gem_framebuffer_helper.c +++ b/drivers/gpu/drm/drm_gem_framebuffer_helper.c @@ -75,7 +75,7 @@ drm_gem_fb_init(struct drm_device *dev, unsigned int i; int ret; - drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, fb, NULL, mode_cmd); for (i = 0; i < num_planes; i++) fb->obj[i] = obj[i]; diff --git a/drivers/gpu/drm/drm_modeset_helper.c b/drivers/gpu/drm/drm_modeset_helper.c index 3fed2d5ab1d63..89ba999707354 100644 --- a/drivers/gpu/drm/drm_modeset_helper.c +++ b/drivers/gpu/drm/drm_modeset_helper.c @@ -74,6 +74,7 @@ EXPORT_SYMBOL(drm_helper_move_panel_connectors_to_head); * drm_helper_mode_fill_fb_struct - fill out framebuffer metadata * @dev: DRM device * @fb: drm_framebuffer object to fill out + * @info: pixel format information * @mode_cmd: metadata from the userspace fb creation request * * This helper can be used in a drivers fb_create callback to pre-fill the fb's @@ -81,13 +82,14 @@ EXPORT_SYMBOL(drm_helper_move_panel_connectors_to_head); */ void drm_helper_mode_fill_fb_struct(struct drm_device *dev, struct drm_framebuffer *fb, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { int i; fb->dev = dev; - fb->format = drm_get_format_info(dev, mode_cmd->pixel_format, - mode_cmd->modifier[0]); + fb->format = info ? : drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); fb->width = mode_cmd->width; fb->height = mode_cmd->height; for (i = 0; i < 4; i++) { diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c b/drivers/gpu/drm/exynos/exynos_drm_fb.c index 9ae526825726c..7091d31835ec4 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fb.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c @@ -76,7 +76,7 @@ exynos_drm_framebuffer_init(struct drm_device *dev, fb->obj[i] = &exynos_gem[i]->base; } - drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, fb, NULL, mode_cmd); ret = drm_framebuffer_init(dev, fb, &exynos_drm_fb_funcs); if (ret < 0) { diff --git a/drivers/gpu/drm/gma500/framebuffer.c b/drivers/gpu/drm/gma500/framebuffer.c index a4a18ec2dd566..f9ade83613548 100644 --- a/drivers/gpu/drm/gma500/framebuffer.c +++ b/drivers/gpu/drm/gma500/framebuffer.c @@ -47,7 +47,7 @@ static int psb_framebuffer_init(struct drm_device *dev, if (mode_cmd->pitches[0] & 63) return -EINVAL; - drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, fb, NULL, mode_cmd); fb->obj[0] = obj; ret = drm_framebuffer_init(dev, fb, &psb_fb_funcs); if (ret) { diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 96edc791c33bb..1f5f8c2e9d315 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -2254,7 +2254,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, goto err_frontbuffer_put; } - drm_helper_mode_fill_fb_struct(display->drm, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(display->drm, fb, NULL, mode_cmd); for (i = 0; i < fb->format->num_planes; i++) { unsigned int stride_alignment; diff --git a/drivers/gpu/drm/msm/msm_fb.c b/drivers/gpu/drm/msm/msm_fb.c index f151244e8cfb3..a82a657169752 100644 --- a/drivers/gpu/drm/msm/msm_fb.c +++ b/drivers/gpu/drm/msm/msm_fb.c @@ -227,7 +227,7 @@ static struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, msm_fb->base.obj[i] = bos[i]; } - drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, fb, NULL, mode_cmd); ret = drm_framebuffer_init(dev, fb, &msm_framebuffer_funcs); if (ret) { diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 1ddd929015262..e1e5421263103 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -321,7 +321,7 @@ nouveau_framebuffer_new(struct drm_device *dev, if (!(fb = *pfb = kzalloc(sizeof(*fb), GFP_KERNEL))) return -ENOMEM; - drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, fb, NULL, mode_cmd); fb->obj[0] = gem; ret = drm_framebuffer_init(dev, fb, &nouveau_framebuffer_funcs); diff --git a/drivers/gpu/drm/omapdrm/omap_fb.c b/drivers/gpu/drm/omapdrm/omap_fb.c index 36afcd1c1fd74..30c81e2e5d6b3 100644 --- a/drivers/gpu/drm/omapdrm/omap_fb.c +++ b/drivers/gpu/drm/omapdrm/omap_fb.c @@ -440,7 +440,7 @@ struct drm_framebuffer *omap_framebuffer_init(struct drm_device *dev, plane->dma_addr = 0; } - drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, fb, NULL, mode_cmd); ret = drm_framebuffer_init(dev, fb, &omap_framebuffer_funcs); if (ret) { diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index b4aa2bc51bfd5..d66c1a30df951 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -1302,7 +1302,7 @@ radeon_framebuffer_init(struct drm_device *dev, { int ret; fb->obj[0] = obj; - drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, fb, NULL, mode_cmd); ret = drm_framebuffer_init(dev, fb, &radeon_fb_funcs); if (ret) { fb->obj[0] = NULL; diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c index 24907573e758d..d359683f5ce62 100644 --- a/drivers/gpu/drm/tegra/fb.c +++ b/drivers/gpu/drm/tegra/fb.c @@ -114,7 +114,7 @@ struct drm_framebuffer *tegra_fb_alloc(struct drm_device *drm, if (!fb) return ERR_PTR(-ENOMEM); - drm_helper_mode_fill_fb_struct(drm, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(drm, fb, NULL, mode_cmd); for (i = 0; i < fb->format->num_planes; i++) fb->obj[i] = &planes[i]->gem; diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c b/drivers/gpu/drm/virtio/virtgpu_display.c index f9a98fbbabd1a..93763b91bab56 100644 --- a/drivers/gpu/drm/virtio/virtgpu_display.c +++ b/drivers/gpu/drm/virtio/virtgpu_display.c @@ -73,7 +73,7 @@ virtio_gpu_framebuffer_init(struct drm_device *dev, vgfb->base.obj[0] = obj; - drm_helper_mode_fill_fb_struct(dev, &vgfb->base, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, &vgfb->base, NULL, mode_cmd); ret = drm_framebuffer_init(dev, &vgfb->base, &virtio_gpu_fb_funcs); if (ret) { diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c index 2d48a28cda9c0..35965e29e4080 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c @@ -548,7 +548,7 @@ static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv, goto out_err1; } - drm_helper_mode_fill_fb_struct(dev, &vfbs->base.base, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, &vfbs->base.base, NULL, mode_cmd); memcpy(&vfbs->uo, uo, sizeof(vfbs->uo)); vmw_user_object_ref(&vfbs->uo); @@ -634,7 +634,7 @@ static int vmw_kms_new_framebuffer_bo(struct vmw_private *dev_priv, } vfbd->base.base.obj[0] = &bo->tbo.base; - drm_helper_mode_fill_fb_struct(dev, &vfbd->base.base, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, &vfbd->base.base, NULL, mode_cmd); vfbd->base.bo = true; vfbd->buffer = vmw_bo_reference(bo); *out = &vfbd->base; diff --git a/include/drm/drm_modeset_helper.h b/include/drm/drm_modeset_helper.h index 995fd981cab03..7e3d4c5a7f66d 100644 --- a/include/drm/drm_modeset_helper.h +++ b/include/drm/drm_modeset_helper.h @@ -26,6 +26,7 @@ struct drm_crtc; struct drm_crtc_funcs; struct drm_device; +struct drm_format_info; struct drm_framebuffer; struct drm_mode_fb_cmd2; @@ -33,6 +34,7 @@ void drm_helper_move_panel_connectors_to_head(struct drm_device *); void drm_helper_mode_fill_fb_struct(struct drm_device *dev, struct drm_framebuffer *fb, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd); int drm_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, From a82a88c9ee0ccb97693a1f06ef0a6b537dbeadc9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 1 Jul 2025 12:07:12 +0300 Subject: [PATCH 1988/2653] drm/amdgpu: Pass along the format info from .fb_create() to drm_helper_mode_fill_fb_struct() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Plumb the format info from .fb_create() all the way to drm_helper_mode_fill_fb_struct() to avoid the redundant lookup. Cc: Alex Deucher Cc: amd-gfx@lists.freedesktop.org Reviewed-by: Thomas Zimmermann Acked-by: Alex Deucher Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250701090722.13645-10-ville.syrjala@linux.intel.com --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index ec30425cd68e7..74554cafe6c72 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1229,13 +1229,14 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev, static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, struct amdgpu_framebuffer *rfb, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object *obj) { int ret; rfb->base.obj[0] = obj; - drm_helper_mode_fill_fb_struct(dev, &rfb->base, NULL, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, &rfb->base, info, mode_cmd); #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED /* Verify that the modifier is supported. */ if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, @@ -1382,7 +1383,7 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, } ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv, - mode_cmd, obj); + info, mode_cmd, obj); if (ret) { kfree(amdgpu_fb); #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED From 2c728ae89ef054a9f8f8cc418d0eeb75666faf50 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 12 Sep 2025 17:09:43 +0800 Subject: [PATCH 1989/2653] drm/amdkcl: test drm_helper_mode_fill_fb_struct() wants 4 arguments Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 12 ++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../dkms/m4/drm_helper_mode_fill_fb_struct.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 33 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 74554cafe6c72..23673a6add864 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1209,7 +1209,12 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev, { int ret; rfb->base.obj[0] = obj; + +#ifdef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_4_ARGS + drm_helper_mode_fill_fb_struct(dev, &rfb->base, NULL, mode_cmd); +#else drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); +#endif ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); if (ret) @@ -1236,7 +1241,14 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, int ret; rfb->base.obj[0] = obj; + +#ifdef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_4_ARGS drm_helper_mode_fill_fb_struct(dev, &rfb->base, info, mode_cmd); +#else + drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); +#endif + + #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED /* Verify that the modifier is supported. */ if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 373785218c605..f338cae9fe40d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -664,6 +664,9 @@ /* drm_helper_force_disable_all() is available */ #define HAVE_DRM_HELPER_FORCE_DISABLE_ALL 1 +/* drm_helper_mode_fill_fb_struct() wants 4 arguments */ +#define HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_4_ARGS 1 + /* drm_kms_helper_connector_hotplug_event() function is available */ #define HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 new file mode 100644 index 0000000000000..e1e4dc10eb1ed --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.16-rc2-1239-ga34cc7bf1034 +dnl # drm: Allow the caller to pass in the format info to drm_helper_mode_fill_fb_struct() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ],[ + drm_helper_mode_fill_fb_struct(NULL, NULL, NULL, NULL); + ],[drm_helper_mode_fill_fb_struct], [drivers/gpu/drm/drm_modeset_helper.c],[ + AC_DEFINE(HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_4_ARGS, 1, + [drm_helper_mode_fill_fb_struct() wants 4 arguments]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6720f4cf0ef8c..fbe807154c899 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -295,6 +295,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMEMDUP_ARRAY_USER AC_AMDGPU_BITMAP_READ AC_AMDGPU_VMF_INSERT_MIXED_MKWRITE_LONG_PFN + AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 746ed46ebdd66161ac1dd8968f16582a0cdb97eb Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 12 Sep 2025 17:32:56 +0800 Subject: [PATCH 1990/2653] drm/amdkcl: test whether fb_create has const struct drm_format_info * parameter Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 8 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm_fb_create_format_info.m4 | 27 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 41 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_fb_create_format_info.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 23673a6add864..5c15ecfa80d7b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1234,7 +1234,9 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev, static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, struct amdgpu_framebuffer *rfb, struct drm_file *file_priv, +#ifdef HAVE_DRM_FB_CREATE_FORMAT_INFO const struct drm_format_info *info, +#endif const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object *obj) { @@ -1357,7 +1359,9 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, struct drm_framebuffer * amdgpu_display_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, +#ifdef HAVE_DRM_FB_CREATE_FORMAT_INFO const struct drm_format_info *info, +#endif const struct drm_mode_fb_cmd2 *mode_cmd) { struct amdgpu_framebuffer *amdgpu_fb; @@ -1395,7 +1399,11 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, } ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv, +#ifdef HAVE_DRM_FB_CREATE_FORMAT_INFO info, mode_cmd, obj); +#else + mode_cmd, obj); +#endif if (ret) { kfree(amdgpu_fb); #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h index 4309b0e0849e9..c999addc3e939 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h @@ -44,7 +44,9 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, struct drm_framebuffer * amdgpu_display_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, +#ifdef HAVE_DRM_FB_CREATE_FORMAT_INFO const struct drm_format_info *info, +#endif const struct drm_mode_fb_cmd2 *mode_cmd); const struct drm_format_info * amdgpu_lookup_format_info(u32 format, uint64_t modifier); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f338cae9fe40d..82f11e89d86dd 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -595,6 +595,9 @@ /* drm_edid_valid() is available */ #define HAVE_DRM_EDID_VALID 1 +/* fb_create has const struct drm_format_info * parameter */ +#define HAVE_DRM_FB_CREATE_FORMAT_INFO 1 + /* drm_fb_helper_fill_info() is available */ #define HAVE_DRM_FB_HELPER_FILL_INFO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_fb_create_format_info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_fb_create_format_info.m4 new file mode 100644 index 0000000000000..25f464b720203 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_fb_create_format_info.m4 @@ -0,0 +1,27 @@ +dnl # +dnl # commit v6.16-rc2-1238-g81112eaac559 +dnl # drm: Pass the format info to .fb_create() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_CREATE_FORMAT_INFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_framebuffer *test_fb_create_new( + struct drm_device *dev, + struct drm_file *file_priv, + const struct drm_format_info *info, + const struct drm_mode_fb_cmd2 *mode_cmd) { + return NULL; + } + + struct drm_mode_config_funcs funcs = { + .fb_create = test_fb_create_new, + }; + ], [ + AC_DEFINE(HAVE_DRM_FB_CREATE_FORMAT_INFO, 1, + [fb_create has const struct drm_format_info * parameter]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fbe807154c899..f222ded393b14 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -296,6 +296,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_BITMAP_READ AC_AMDGPU_VMF_INSERT_MIXED_MKWRITE_LONG_PFN AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT + AC_AMDGPU_DRM_FB_CREATE_FORMAT_INFO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 0af0c6216b001913e4d4315d9a1bc21177809713 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 12 Sep 2025 18:43:18 +0800 Subject: [PATCH 1991/2653] drm/amdkcl: get_format_info uses pixel_format and modifier parameters Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 7 ++++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.h | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../dkms/m4/drm_get_format_info_signature.m4 | 24 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 39 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_get_format_info_signature.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index a3f062c72d49d..9f8fe4f41245b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -95,10 +95,17 @@ enum dm_micro_swizzle { }; #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED +#ifdef HAVE_DRM_GET_FORMAT_INFO_TWO_ARGS const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier) { return amdgpu_lookup_format_info(pixel_format, modifier); } +#else +const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd) +{ + return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]); +} +#endif #endif void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h index ea2619b507db7..3b583bbca535a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h @@ -58,7 +58,11 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, unsigned long possible_crtcs, const struct dc_plane_cap *plane_cap); +#ifdef HAVE_DRM_GET_FORMAT_INFO_TWO_ARGS const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier); +#else +const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd); +#endif void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, bool *per_pixel_alpha, bool *pre_multiplied_alpha, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 82f11e89d86dd..da81baa20ab3d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -652,6 +652,9 @@ /* drm_gem_prime_handle_to_fd() is available */ #define HAVE_DRM_GEM_PRIME_HANDLE_TO_FD 1 +/* get_format_info uses pixel_format and modifier parameters */ +#define HAVE_DRM_GET_FORMAT_INFO_TWO_ARGS 1 + /* drm_get_panel_min_brightness_quirk() is available */ #define HAVE_DRM_GET_PANEL_MIN_BRIGHTNESS_QUIRK 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_get_format_info_signature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_get_format_info_signature.m4 new file mode 100644 index 0000000000000..71d0f4e7eb9d4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_get_format_info_signature.m4 @@ -0,0 +1,24 @@ +dnl # +dnl # v6.16-rc2-1235-g0389e4256eb2 +dnl # drm: Pass pixel_format+modifier to .get_format_info() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GET_FORMAT_INFO_2_ARGS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + const struct drm_format_info *test_get_format_info_new( + u32 pixel_format, u64 modifier) { + return NULL; + } + + struct drm_mode_config_funcs funcs = { + .get_format_info = test_get_format_info_new, + }; + ], [ + AC_DEFINE(HAVE_DRM_GET_FORMAT_INFO_TWO_ARGS, 1, + [get_format_info uses pixel_format and modifier parameters]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f222ded393b14..6dbc197220238 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -297,6 +297,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMF_INSERT_MIXED_MKWRITE_LONG_PFN AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_FB_CREATE_FORMAT_INFO + AC_AMDGPU_DRM_GET_FORMAT_INFO_2_ARGS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 607aa7349222068913ebcf24272583c16a96438e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 25 Aug 2025 23:33:33 +0200 Subject: [PATCH 1992/2653] drm/amd/display: Fix DVI-D/HDMI adapters MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When the EDID has the HDMI bit, we should simply select the HDMI signal type even on DVI ports. For reference see, the legacy amdgpu display code: amdgpu_atombios_encoder_get_encoder_mode which selects ATOM_ENCODER_MODE_HDMI for the same case. This commit fixes DVI connectors to work with DVI-D/HDMI adapters so that they can now produce output over these connectors for HDMI monitors with higher bandwidth modes. With this change, even HDMI audio works through DVI. For testing, I used a CAA-DMDHFD3 DVI-D/HDMI adapter with the following GPUs: Tahiti (DCE 6) - DC can now output 4K 30 Hz over DVI Polaris 10 (DCE 11.2) - DC can now output 4K 60 Hz over DVI Signed-off-by: Timur Kristóf Acked-by: Alex Deucher Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/link/link_detection.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index b717e430051a0..85303167a5531 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -1140,6 +1140,10 @@ static bool detect_link_and_local_sink(struct dc_link *link, if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A && !sink->edid_caps.edid_hdmi) sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK; + else if (dc_is_dvi_signal(sink->sink_signal) && + aud_support->hdmi_audio_native && + sink->edid_caps.edid_hdmi) + sink->sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; if (link->local_sink && dc_is_dp_signal(sink_caps.signal)) dp_trace_init(link); From 42cc99c61512166f9f2795fc86f3227077e05a20 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 25 Aug 2025 23:56:28 +0200 Subject: [PATCH 1993/2653] drm/amd/display: Keep PLL0 running on DCE 6.0 and 6.4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DC can turn off the display clock when no displays are connected or when all displays are off, for reference see: - dce*_validate_bandwidth DC also assumes that the DP clock is always on and never powers it down, for reference see: - dce110_clock_source_power_down In case of DCE 6.0 and 6.4, PLL0 is the clock source for both the engine clock and DP clock, for reference see: - radeon_atom_pick_pll - atombios_crtc_set_disp_eng_pll Therefore, PLL0 should be always kept running on DCE 6.0 and 6.4. This commit achieves that by ensuring that by setting the display clock to the corresponding value in low power state instead of zero. This fixes a page flip timeout on SI with DC which happens when all connected displays are blanked. Signed-off-by: Timur Kristóf Reviewed-by: Alex Deucher Reviewed-by: Alex Hung --- .../amd/display/dc/resource/dce60/dce60_resource.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c index 53b60044653f8..c164d2500c2a4 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c @@ -881,7 +881,16 @@ static enum dc_status dce60_validate_bandwidth( context->bw_ctx.bw.dce.dispclk_khz = 681000; context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; } else { - context->bw_ctx.bw.dce.dispclk_khz = 0; + /* On DCE 6.0 and 6.4 the PLL0 is both the display engine clock and + * the DP clock, and shouldn't be turned off. Just select the display + * clock value from its low power mode. + */ + if (dc->ctx->dce_version == DCE_VERSION_6_0 || + dc->ctx->dce_version == DCE_VERSION_6_4) + context->bw_ctx.bw.dce.dispclk_khz = 352000; + else + context->bw_ctx.bw.dce.dispclk_khz = 0; + context->bw_ctx.bw.dce.yclk_khz = 0; } From aa975b8793fa7e7f4d68c4581f6c8cd9eeb5b68f Mon Sep 17 00:00:00 2001 From: Xi Ruoyao Date: Mon, 25 Aug 2025 16:52:11 +0800 Subject: [PATCH 1994/2653] drm/amd/display/dml2: Guard dml21_map_dc_state_into_dml_display_cfg with DC_FP_START dml21_map_dc_state_into_dml_display_cfg calls (the call is usually inlined by the compiler) populate_dml21_surface_config_from_plane_state and populate_dml21_plane_config_from_plane_state which may use FPU. In a x86-64 build: $ objdump --disassemble=dml21_map_dc_state_into_dml_display_cfg \ > drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.o | > grep %xmm -c 63 Thus it needs to be guarded with DC_FP_START. But we must note that the current code quality of the in-kernel FPU use in AMD dml2 is very much problematic: we are actually calling DC_FP_START in dml21_wrapper.c here, and this translation unit is built with CC_FLAGS_FPU. Strictly speaking this does not make any sense: with CC_FLAGS_FPU the compiler is allowed to generate FPU uses anywhere in the translated code, perhaps out of the DC_FP_START guard. This problematic pattern also occurs in at least dml2_wrapper.c, dcn35_fpu.c, and dcn351_fpu.c. Thus we really need a careful audit and refactor for the in-kernel FPU uses, and this patch is simply whacking a mole. However per the reporter, whacking this mole is enough to make a 9060XT "just work." Reported-by: Asiacn <710187964@qq.com> Closes: https://github.com/loongson-community/discussions/issues/102 Tested-by: Asiacn <710187964@qq.com> Signed-off-by: Xi Ruoyao Reviewed-by: Huacai Chen Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c index 798abb2b2e676..08f7f03b10231 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c @@ -224,7 +224,9 @@ static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_s dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); /* Populate stream, plane mappings and other fields in display config. */ + DC_FP_START(); result = dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); + DC_FP_END(); if (!result) return false; @@ -279,7 +281,9 @@ static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *co dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); mode_support->dml2_instance = dml_init->dml2_instance; + DC_FP_START(); dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); + DC_FP_END(); dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.programming; DC_FP_START(); is_supported = dml2_check_mode_supported(mode_support); From a92381f61e0e82049f35a332a6dddaaf5244a52f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 25 Aug 2025 23:56:29 +0200 Subject: [PATCH 1995/2653] drm/amd/display: Disable fastboot on DCE 6 too MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It already didn't work on DCE 8, so there is no reason to assume it would on DCE 6. Signed-off-by: Timur Kristóf Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Deucher Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 7b4a04704312d..24184b4eb3529 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -1925,10 +1925,8 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) get_edp_streams(context, edp_streams, &edp_stream_num); - // Check fastboot support, disable on DCE8 because of blank screens - if (edp_num && edp_stream_num && dc->ctx->dce_version != DCE_VERSION_8_0 && - dc->ctx->dce_version != DCE_VERSION_8_1 && - dc->ctx->dce_version != DCE_VERSION_8_3) { + /* Check fastboot support, disable on DCE 6-8 because of blank screens */ + if (edp_num && edp_stream_num && dc->ctx->dce_version < DCE_VERSION_10_0) { for (i = 0; i < edp_num; i++) { edp_link = edp_links[i]; if (edp_link != edp_streams[0]->link) From edb933159a4471066d9eb2d35fce325f4e3c5679 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 25 Aug 2025 23:56:30 +0200 Subject: [PATCH 1996/2653] drm/amd/display: Disable VRR on DCE 6 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DCE 6 was not advertised as being able to support VRR, so let's mark it as unsupported for now. The VRR implementation in amdgpu_dm depends on the VUPDATE interrupt which is not registered for DCE 6. Signed-off-by: Timur Kristóf Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Deucher Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +++- drivers/gpu/drm/amd/display/dc/dc_helper.c | 5 +++++ drivers/gpu/drm/amd/display/dc/dm_services.h | 2 ++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e8c1cd5056fd8..ad3a03ae99556 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11174,6 +11174,8 @@ static void get_freesync_config_for_crtc( } else { config.state = VRR_STATE_INACTIVE; } + } else { + config.state = VRR_STATE_UNSUPPORTED; } out: new_crtc_state->freesync_config = config; @@ -13121,7 +13123,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, dm_con_state = to_dm_connector_state(connector->state); - if (!adev->dm.freesync_module) + if (!adev->dm.freesync_module || !dc_supports_vrr(sink->ctx->dce_version)) goto update; #ifdef HAVE_DRM_DP_MST_EDID_READ diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index d36c71bfd8279..bd1069f2c23b9 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -753,3 +753,8 @@ char *dce_version_to_string(const int version) return "Unknown"; } } + +bool dc_supports_vrr(const enum dce_version v) +{ + return v >= DCE_VERSION_8_0; +} diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index 7b9c22c45453d..7b398d4f44398 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -311,4 +311,6 @@ void dm_dtn_log_end(struct dc_context *ctx, char *dce_version_to_string(const int version); +bool dc_supports_vrr(const enum dce_version v); + #endif /* __DM_SERVICES_H__ */ From dd2895da077ca3ba3fd61e94357ad80c3ae398f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Fri, 5 Sep 2025 14:45:39 +0200 Subject: [PATCH 1997/2653] drm/amdgpu: add AMDGPU_IDS_FLAGS_GANG_SUBMIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a UAPI flag indicating if gang submit is supported or not. Signed-off-by: Christian König Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 ++++ include/uapi/drm/amdgpu_drm.h | 9 +++++---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 73637f7d035ad..517583e17875c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -957,6 +957,10 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) if (adev->gfx.config.ta_cntl2_truncate_coord_mode) dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD; + /* Gang submit is not supported under SRIOV currently */ + if (!amdgpu_sriov_vf(adev)) + dev_info->ids_flags |= AMDGPU_IDS_FLAGS_GANG_SUBMIT; + if (amdgpu_passthrough(adev)) dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_PT << AMDGPU_IDS_FLAGS_MODE_SHIFT) & diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 4c2de75b15374..bf67fe9e6a427 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -1149,10 +1149,11 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU * */ -#define AMDGPU_IDS_FLAGS_FUSION 0x1 -#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 -#define AMDGPU_IDS_FLAGS_TMZ 0x4 -#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 +#define AMDGPU_IDS_FLAGS_FUSION 0x01 +#define AMDGPU_IDS_FLAGS_PREEMPTION 0x02 +#define AMDGPU_IDS_FLAGS_TMZ 0x04 +#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x08 +#define AMDGPU_IDS_FLAGS_GANG_SUBMIT 0x10 /* * Query h/w info: Flag identifying VF/PF/PT mode From 464f37da17c418fa8c7852d56a51b6a64c4e1c0b Mon Sep 17 00:00:00 2001 From: "Mario Limonciello (AMD)" Date: Fri, 12 Sep 2025 12:59:33 -0500 Subject: [PATCH 1998/2653] drm/amd: Drop unnecessary calls to smu_dpm_set_vpe_enable() smu_hw_init() and smu_hw_fini() call smu_dpm_set_vpe_enable() for APUs as part of startup and teardown. These calls however are not necessary because vpe_hw_init()/vpe_hw_fini() will call at init/fini: ``` vpe_hw_init() / vpe_hw_fini() amdgpu_device_ip_set_powergating_state() vpe_set_powergating_state() amdgpu_dpm_enable_vpe() amdgpu_dpm_set_powergating_by_smu() smu_dpm_set_power_gate() smu_dpm_set_vpe_enable() ``` Drop the extra calls. Signed-off-by: Mario Limonciello (AMD) Reviewed-by: Yang Wang Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 151e036b7e212..804cae7af9dfa 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -1925,7 +1925,6 @@ static int smu_hw_init(struct amdgpu_ip_block *ip_block) for (i = 0; i < adev->vcn.num_vcn_inst; i++) smu_dpm_set_vcn_enable(smu, true, i); smu_dpm_set_jpeg_enable(smu, true); - smu_dpm_set_vpe_enable(smu, true); smu_dpm_set_umsch_mm_enable(smu, true); smu_set_mall_enable(smu); smu_set_gfx_cgpg(smu, true); @@ -2133,7 +2132,6 @@ static int smu_hw_fini(struct amdgpu_ip_block *ip_block) } smu_dpm_set_jpeg_enable(smu, false); adev->jpeg.cur_state = AMD_PG_STATE_GATE; - smu_dpm_set_vpe_enable(smu, false); smu_dpm_set_umsch_mm_enable(smu, false); if (!smu->pm_enabled) From f02785245a54123417ea57d47f6256c7b790fa41 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 27 Aug 2025 13:14:43 +0200 Subject: [PATCH 1999/2653] drm/amdgpu: reject gang submissions under SRIOV MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Gang submission means that the kernel driver guarantees that multiple submissions are executed on the HW at the same time on different engines. Background is that those submissions then depend on each other and each can't finish stand alone. SRIOV now uses world switch to preempt submissions on the engines to allow sharing the HW resources between multiple VFs. The problem is now that the SRIOV world switch can't know about such inter dependencies and will cause a timeout if it waits for a partially running gang submission. To conclude SRIOV and gang submissions are fundamentally incompatible at the moment. For now just disable them. Signed-off-by: Christian König Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index a8c74aed69f63..a3daf201929b7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -278,7 +278,7 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p, } } - if (!p->gang_size) { + if (!p->gang_size || (amdgpu_sriov_vf(p->adev) && p->gang_size > 1)) { ret = -EINVAL; goto free_all_kdata; } From 4c38ba2d4dac552bec56756d5ba70af35e6e1f1d Mon Sep 17 00:00:00 2001 From: James Flowers Date: Fri, 12 Sep 2025 22:19:52 -0700 Subject: [PATCH 2000/2653] drm/amd/display: Use kmalloc_array() instead of kmalloc() Documentation/process/deprecated.rst recommends against the use of kmalloc with dynamic size calculations due to the risk of overflow and smaller allocation being made than the caller was expecting. This could lead to buffer overflow in code similar to the memcpy in amdgpu_dm_plane_add_modifier(). Signed-off-by: James Flowers Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 9f8fe4f41245b..8b7325d1cabec 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -157,7 +157,7 @@ static void amdgpu_dm_plane_add_modifier(uint64_t **mods, uint64_t *size, uint64 if (*cap - *size < 1) { uint64_t new_cap = *cap * 2; - uint64_t *new_mods = kmalloc(new_cap * sizeof(uint64_t), GFP_KERNEL); + uint64_t *new_mods = kmalloc_array(new_cap, sizeof(uint64_t), GFP_KERNEL); if (!new_mods) { kfree(*mods); @@ -745,7 +745,7 @@ static int amdgpu_dm_plane_get_plane_modifiers(struct amdgpu_device *adev, unsig if (adev->family < AMDGPU_FAMILY_AI) return 0; - *mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL); + *mods = kmalloc_array(capacity, sizeof(uint64_t), GFP_KERNEL); if (plane_type == DRM_PLANE_TYPE_CURSOR) { amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR); From dadafa5ff198a6c3571df9ba996e9007229ebf52 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 25 Aug 2025 23:56:31 +0200 Subject: [PATCH 2001/2653] drm/amd/display: Don't use non-registered VUPDATE on DCE 6 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The VUPDATE interrupt isn't registered on DCE 6, so don't try to use that. This fixes a page flip timeout after sleep/resume on DCE 6. Signed-off-by: Timur Kristóf Reviewed-by: Rodrigo Siqueira Reviewed-by: Alex Deucher Reviewed-by: Alex Hung --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 22 ++++++++++++------- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 17 +++++++++----- 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ad3a03ae99556..ed9f373db5083 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3086,14 +3086,20 @@ static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, drm_warn(adev_to_drm(adev), "Failed to %s pflip interrupts\n", enable ? "enable" : "disable"); - if (enable) { - if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state))) - rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true); - } else - rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false); - - if (rc) - drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n", enable ? "en" : "dis"); + if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) { + if (enable) { + if (amdgpu_dm_crtc_vrr_active( + to_dm_crtc_state(acrtc->base.state))) + rc = amdgpu_dm_crtc_set_vupdate_irq( + &acrtc->base, true); + } else + rc = amdgpu_dm_crtc_set_vupdate_irq( + &acrtc->base, false); + + if (rc) + drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n", + enable ? "en" : "dis"); + } irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; /* During gpu-reset we disable and then enable vblank irq, so diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 5c8944bc92183..67c96a85880b0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -319,12 +319,17 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) sr_supported && vblank->config.disable_immediate) drm_crtc_vblank_restore(crtc); #endif - /* vblank irq on -> Only need vupdate irq in vrr mode */ - if (amdgpu_dm_crtc_vrr_active(acrtc_state)) - rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true); - } else { - /* vblank irq off -> vupdate irq off */ - rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false); + } + + if (dc_supports_vrr(dm->dc->ctx->dce_version)) { + if (enable) { + /* vblank irq on -> Only need vupdate irq in vrr mode */ + if (amdgpu_dm_crtc_vrr_active(acrtc_state)) + rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true); + } else { + /* vblank irq off -> vupdate irq off */ + rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false); + } } if (rc) From a34fd14b5604679f1372f9db7e136b16df563df3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Fri, 6 Jun 2025 14:53:54 +0200 Subject: [PATCH 2002/2653] drm/amdgpu: revert "Implement new dummy vram manager" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is should be unnecessary since a VRAM manager isn't mandatory in the first place. It could be that we have some missing checks inside AMDGPU or TTM but those should then be fixed instead of worked around like that. Signed-off-by: Christian König Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 15 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 61 ++------------------ 2 files changed, 13 insertions(+), 63 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 8a29165344f43..29555bbbf9bcd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2358,11 +2358,13 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) } adev->mman.initialized = true; - /* Initialize VRAM pool with all of VRAM divided into pages */ - r = amdgpu_vram_mgr_init(adev); - if (r) { - dev_err(adev->dev, "Failed initializing VRAM heap.\n"); - return r; + if (!adev->gmc.is_app_apu) { + /* Initialize VRAM pool with all of VRAM divided into pages */ + r = amdgpu_vram_mgr_init(adev); + if (r) { + dev_err(adev->dev, "Failed initializing VRAM heap.\n"); + return r; + } } /* Change the size here instead of the init above so only lpfn is affected */ @@ -2582,7 +2584,8 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) drain_workqueue(adev->mman.bdev.wq); amdgpu_direct_gma_fini(adev); - amdgpu_vram_mgr_fini(adev); + if (!adev->gmc.is_app_apu) + amdgpu_vram_mgr_fini(adev); amdgpu_gtt_mgr_fini(adev); amdgpu_preempt_mgr_fini(adev); amdgpu_doorbell_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 96ef7f1edb03f..02cbf9aaa2c60 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -431,45 +431,6 @@ int amdgpu_vram_mgr_query_address_block_info(struct amdgpu_vram_mgr *mgr, return ret; } -static void amdgpu_dummy_vram_mgr_debug(struct ttm_resource_manager *man, - struct drm_printer *printer) -{ - DRM_DEBUG_DRIVER("Dummy vram mgr debug\n"); -} - -static bool amdgpu_dummy_vram_mgr_compatible(struct ttm_resource_manager *man, - struct ttm_resource *res, - const struct ttm_place *place, - size_t size) -{ - DRM_DEBUG_DRIVER("Dummy vram mgr compatible\n"); - return false; -} - -static bool amdgpu_dummy_vram_mgr_intersects(struct ttm_resource_manager *man, - struct ttm_resource *res, - const struct ttm_place *place, - size_t size) -{ - DRM_DEBUG_DRIVER("Dummy vram mgr intersects\n"); - return true; -} - -static void amdgpu_dummy_vram_mgr_del(struct ttm_resource_manager *man, - struct ttm_resource *res) -{ - DRM_DEBUG_DRIVER("Dummy vram mgr deleted\n"); -} - -static int amdgpu_dummy_vram_mgr_new(struct ttm_resource_manager *man, - struct ttm_buffer_object *tbo, - const struct ttm_place *place, - struct ttm_resource **res) -{ - DRM_DEBUG_DRIVER("Dummy vram mgr new\n"); - return -ENOSPC; -} - /** * amdgpu_vram_mgr_new - allocate new ranges * @@ -943,14 +904,6 @@ static void amdgpu_vram_mgr_debug(struct ttm_resource_manager *man, mutex_unlock(&mgr->lock); } -static const struct ttm_resource_manager_func amdgpu_dummy_vram_mgr_func = { - .alloc = amdgpu_dummy_vram_mgr_new, - .free = amdgpu_dummy_vram_mgr_del, - .intersects = amdgpu_dummy_vram_mgr_intersects, - .compatible = amdgpu_dummy_vram_mgr_compatible, - .debug = amdgpu_dummy_vram_mgr_debug -}; - static const struct ttm_resource_manager_func amdgpu_vram_mgr_func = { .alloc = amdgpu_vram_mgr_new, .free = amdgpu_vram_mgr_del, @@ -995,16 +948,10 @@ int amdgpu_vram_mgr_init(struct amdgpu_device *adev) DRM_ERROR("Failed to register sysfs\n"); #endif - if (!adev->gmc.is_app_apu) { - man->func = &amdgpu_vram_mgr_func; - - err = drm_buddy_init(&mgr->mm, man->size, PAGE_SIZE); - if (err) - return err; - } else { - man->func = &amdgpu_dummy_vram_mgr_func; - DRM_INFO("Setup dummy vram mgr\n"); - } + man->func = &amdgpu_vram_mgr_func; + err = drm_buddy_init(&mgr->mm, man->size, PAGE_SIZE); + if (err) + return err; ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_VRAM, &mgr->manager); ttm_resource_manager_set_used(man, true); From 7fc75f668aeed2e5d6973b98b84bdb60bf5dd53b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 27 Aug 2025 09:28:40 +0200 Subject: [PATCH 2003/2653] drm/amdgpu: fix userq VM validation v4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit That was actually complete nonsense and not validating the BOs at all. The code just cleared all VM areas were it couldn't grab the lock for a BO. Try to fix this. Only compile tested at the moment. v2: fix fence slot reservation as well as pointed out by Sunil. also validate PDs, PTs, per VM BOs and update PDEs v3: grab the status_lock while working with the done list. v4: rename functions, add some comments, fix waiting for updates to complete. v4: rename amdgpu_vm_lock_done_list(), add some more comments Signed-off-by: Christian König Reviewed-by: Sunil Khatri Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 148 +++++++++++----------- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 35 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 + 3 files changed, 110 insertions(+), 75 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index d28dfc752677b..442f69979e579 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -711,108 +711,106 @@ amdgpu_userq_restore_all(struct amdgpu_userq_mgr *uq_mgr) return ret; } +static int amdgpu_userq_validate_vm(void *param, struct amdgpu_bo *bo) +{ + struct ttm_operation_ctx ctx = { false, false }; + + amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); + return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); +} + +/* Handle all BOs on the invalidated list, validate them and update the PTs */ static int -amdgpu_userq_validate_vm_bo(void *_unused, struct amdgpu_bo *bo) +amdgpu_userq_bo_validate(struct amdgpu_device *adev, struct drm_exec *exec, + struct amdgpu_vm *vm) { struct ttm_operation_ctx ctx = { false, false }; + struct amdgpu_bo_va *bo_va; + struct amdgpu_bo *bo; int ret; - amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); + spin_lock(&vm->status_lock); + while (!list_empty(&vm->invalidated)) { + bo_va = list_first_entry(&vm->invalidated, + struct amdgpu_bo_va, + base.vm_status); + spin_unlock(&vm->status_lock); - ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); - if (ret) - DRM_ERROR("Fail to validate\n"); + bo = bo_va->base.bo; + ret = drm_exec_prepare_obj(exec, &bo->tbo.base, 2); + if (unlikely(ret)) + return ret; - return ret; + amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); + ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); + if (ret) + return ret; + + /* This moves the bo_va to the done list */ + ret = amdgpu_vm_bo_update(adev, bo_va, false); + if (ret) + return ret; + + spin_lock(&vm->status_lock); + } + spin_unlock(&vm->status_lock); + + return 0; } +/* Make sure the whole VM is ready to be used */ static int -amdgpu_userq_validate_bos(struct amdgpu_userq_mgr *uq_mgr) +amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) { struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr); - struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_device *adev = uq_mgr->adev; + struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_va *bo_va; - struct ww_acquire_ctx *ticket; struct drm_exec exec; - struct amdgpu_bo *bo; - struct dma_resv *resv; - bool clear, unlock; - int ret = 0; + int ret; drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); drm_exec_until_all_locked(&exec) { - ret = amdgpu_vm_lock_pd(vm, &exec, 2); + ret = amdgpu_vm_lock_pd(vm, &exec, 1); drm_exec_retry_on_contention(&exec); - if (unlikely(ret)) { - drm_file_err(uq_mgr->file, "Failed to lock PD\n"); + if (unlikely(ret)) goto unlock_all; - } - - /* Lock the done list */ - list_for_each_entry(bo_va, &vm->done, base.vm_status) { - bo = bo_va->base.bo; - if (!bo) - continue; - ret = drm_exec_lock_obj(&exec, &bo->tbo.base); - drm_exec_retry_on_contention(&exec); - if (unlikely(ret)) - goto unlock_all; - } - } - - spin_lock(&vm->status_lock); - while (!list_empty(&vm->moved)) { - bo_va = list_first_entry(&vm->moved, struct amdgpu_bo_va, - base.vm_status); - spin_unlock(&vm->status_lock); - - /* Per VM BOs never need to bo cleared in the page tables */ - ret = amdgpu_vm_bo_update(adev, bo_va, false); - if (ret) + ret = amdgpu_vm_lock_done_list(vm, &exec, 1); + drm_exec_retry_on_contention(&exec); + if (unlikely(ret)) goto unlock_all; - spin_lock(&vm->status_lock); - } - - ticket = &exec.ticket; - while (!list_empty(&vm->invalidated)) { - bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, - base.vm_status); - resv = amdkcl_ttm_resvp(&bo_va->base.bo->tbo); - spin_unlock(&vm->status_lock); - bo = bo_va->base.bo; - ret = amdgpu_userq_validate_vm_bo(NULL, bo); - if (ret) { - drm_file_err(uq_mgr->file, "Failed to validate BO\n"); + /* This validates PDs, PTs and per VM BOs */ + ret = amdgpu_vm_validate(adev, vm, NULL, + amdgpu_userq_validate_vm, + NULL); + if (unlikely(ret)) goto unlock_all; - } - /* Try to reserve the BO to avoid clearing its ptes */ - if (!adev->debug_vm && dma_resv_trylock(resv)) { - clear = false; - unlock = true; - /* The caller is already holding the reservation lock */ - } else if (dma_resv_locking_ctx(resv) == ticket) { - clear = false; - unlock = false; - /* Somebody else is using the BO right now */ - } else { - clear = true; - unlock = false; - } + /* This locks and validates the remaining evicted BOs */ + ret = amdgpu_userq_bo_validate(adev, &exec, vm); + drm_exec_retry_on_contention(&exec); + if (unlikely(ret)) + goto unlock_all; + } - ret = amdgpu_vm_bo_update(adev, bo_va, clear); + ret = amdgpu_vm_handle_moved(adev, vm, NULL); + if (ret) + goto unlock_all; - if (unlock) - dma_resv_unlock(resv); - if (ret) - goto unlock_all; + ret = amdgpu_vm_update_pdes(adev, vm, false); + if (ret) + goto unlock_all; - spin_lock(&vm->status_lock); - } - spin_unlock(&vm->status_lock); + /* + * We need to wait for all VM updates to finish before restarting the + * queues. Using the done list like that is now ok since everything is + * locked in place. + */ + list_for_each_entry(bo_va, &vm->done, base.vm_status) + dma_fence_wait(bo_va->last_pt_update, false); + dma_fence_wait(vm->last_update, false); ret = amdgpu_eviction_fence_replace_fence(&fpriv->evf_mgr, &exec); if (ret) @@ -833,7 +831,7 @@ static void amdgpu_userq_restore_worker(struct work_struct *work) mutex_lock(&uq_mgr->userq_mutex); - ret = amdgpu_userq_validate_bos(uq_mgr); + ret = amdgpu_userq_vm_validate(uq_mgr); if (ret) { drm_file_err(uq_mgr->file, "Failed to validate BOs to restore\n"); goto unlock; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 5c4ccf64c131c..49ff847ab30e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -499,6 +499,41 @@ int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, 2 + num_fences); } +/** + * amdgpu_vm_lock_done_list - lock all BOs on the done list + * @exec: drm execution context + * @num_fences: number of extra fences to reserve + * + * Lock the BOs on the done list in the DRM execution context. + */ +int amdgpu_vm_lock_done_list(struct amdgpu_vm *vm, struct drm_exec *exec, + unsigned int num_fences) +{ + struct list_head *prev = &vm->done; + struct amdgpu_bo_va *bo_va; + struct amdgpu_bo *bo; + int ret; + + /* We can only trust prev->next while holding the lock */ + spin_lock(&vm->status_lock); + while (!list_is_head(prev->next, &vm->done)) { + bo_va = list_entry(prev->next, typeof(*bo_va), base.vm_status); + spin_unlock(&vm->status_lock); + + bo = bo_va->base.bo; + if (bo) { + ret = drm_exec_prepare_obj(exec, &bo->tbo.base, 1); + if (unlikely(ret)) + return ret; + } + spin_lock(&vm->status_lock); + prev = prev->next; + } + spin_unlock(&vm->status_lock); + + return 0; +} + /** * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 7f318955f66eb..8d2474bf4f9c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -500,6 +500,8 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, unsigned int num_fences); +int amdgpu_vm_lock_done_list(struct amdgpu_vm *vm, struct drm_exec *exec, + unsigned int num_fences); bool amdgpu_vm_ready(struct amdgpu_vm *vm); uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm); int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, From 90a7a4d02630f708ff8c841a9fcbe92b1ca141f2 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Mon, 15 Sep 2025 15:59:23 +0800 Subject: [PATCH 2004/2653] drm/amdkcl: test vfs_iocb_iter_read() is available It's caused by the commit: b70e506 "drm/amdkfd: Add AMD Infinity Storage (AIS) support" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_fs_read_write.c | 90 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/kcl_security.c | 24 +++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/dkms/config/config.h | 3 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/vfs_iocb_iter_read.m4 | 16 ++++ include/kcl/kcl_fs.h | 9 ++ 8 files changed, 146 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_security.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/vfs_iocb_iter_read.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index af911c325e4b9..ac6ff97260bb0 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -5,7 +5,7 @@ amdkcl-y += kcl_kernel_params.o amdkcl-y += dma-buf/dma-resv.o kcl_dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ - kcl_kthread.o kcl_io.o kcl_seq_file.o \ + kcl_kthread.o kcl_io.o kcl_seq_file.o kcl_security.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o \ kcl_fence.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_drm_edid.o\ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c b/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c index e45c10eabc006..622d2c40eece3 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c @@ -5,6 +5,9 @@ */ #include #include +#include +#include +#include /* Copied from v4.13-rc7-6-ge13ec939e96b:fs/read_write.c */ #ifndef HAVE_KERNEL_WRITE_PPOS @@ -25,3 +28,90 @@ ssize_t _kcl_kernel_write(struct file *file, const void *buf, size_t count, EXPORT_SYMBOL(_kcl_kernel_write); #endif +#ifndef HAVE_VFS_IOCB_ITER_READ +int kcl_security_file_permission(struct file *file, int mask); + +static inline bool kcl_unsigned_offsets(struct file *file) +{ + return file->f_mode & FMODE_UNSIGNED_OFFSET; +} + +int kcl_rw_verify_area(int read_write, struct file *file, const loff_t *ppos, size_t count) +{ + if (unlikely((ssize_t) count < 0)) + return -EINVAL; + + if (ppos) { + loff_t pos = *ppos; + + if (unlikely(pos < 0)) { + if (!kcl_unsigned_offsets(file)) + return -EINVAL; + if (count >= -pos) /* both values are in 0..LLONG_MAX */ + return -EOVERFLOW; + } else if (unlikely((loff_t) (pos + count) < 0)) { + if (!kcl_unsigned_offsets(file)) + return -EINVAL; + } + } + + return kcl_security_file_permission(file, + read_write == READ ? MAY_READ : MAY_WRITE); +} + +ssize_t kcl_vfs_iocb_iter_read(struct file *file, struct kiocb *iocb, + struct iov_iter *iter) +{ + size_t tot_len; + ssize_t ret = 0; + + if (!file->f_op->read_iter) + return -EINVAL; + if (!(file->f_mode & FMODE_READ)) + return -EBADF; + if (!(file->f_mode & FMODE_CAN_READ)) + return -EINVAL; + + tot_len = iov_iter_count(iter); + if (!tot_len) + goto out; + ret = kcl_rw_verify_area(READ, file, &iocb->ki_pos, tot_len); + if (ret < 0) + return ret; + + ret = call_read_iter(file, iocb, iter); +out: + if (ret >= 0) + fsnotify_access(file); + return ret; +} +EXPORT_SYMBOL(kcl_vfs_iocb_iter_read); + +ssize_t kcl_vfs_iocb_iter_write(struct file *file, struct kiocb *iocb, + struct iov_iter *iter) +{ + size_t tot_len; + ssize_t ret = 0; + + if (!file->f_op->write_iter) + return -EINVAL; + if (!(file->f_mode & FMODE_WRITE)) + return -EBADF; + if (!(file->f_mode & FMODE_CAN_WRITE)) + return -EINVAL; + + tot_len = iov_iter_count(iter); + if (!tot_len) + return 0; + ret = kcl_rw_verify_area(WRITE, file, &iocb->ki_pos, tot_len); + if (ret < 0) + return ret; + + ret = call_write_iter(file, iocb, iter); + if (ret > 0) + fsnotify_modify(file); + + return ret; +} +EXPORT_SYMBOL(kcl_vfs_iocb_iter_write); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_security.c b/drivers/gpu/drm/amd/amdkcl/kcl_security.c new file mode 100644 index 0000000000000..6ba63cf49ef7a --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_security.c @@ -0,0 +1,24 @@ +#include +#ifdef CONFIG_SECURITY +#include +#endif +#include "kcl_common.h" + +#ifndef HAVE_VFS_IOCB_ITER_READ +struct file; // Forward declaration + +int (*kcl_security_file_permission)(struct file *file, int mask); + +int _kcl_security_file_permission(struct file *file, int mask) +{ + pr_warn_once("This kernel version not support API: security_file_permission !\n"); + return 0; +} +#endif + +void amdkcl_security_init(void) +{ +#ifndef HAVE_VFS_IOCB_ITER_READ + kcl_security_file_permission = amdkcl_fp_setup("security_file_permission", _kcl_security_file_permission); +#endif +} \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 73fd6da35a4e0..d7956a35cae96 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -9,6 +9,7 @@ extern void amdkcl_suspend_init(void); extern void amdkcl_numa_init(void); extern void amdkcl_workqueue_init(void); extern void amdkcl_prime_init(void); +extern void amdkcl_security_init(void); int __init amdkcl_init(void) { @@ -19,6 +20,7 @@ int __init amdkcl_init(void) amdkcl_numa_init(); amdkcl_workqueue_init(); amdkcl_prime_init(); + amdkcl_security_init(); return 0; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index da81baa20ab3d..ce8d0f56eca0a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1262,6 +1262,9 @@ /* usleep_range_state() is available */ #define HAVE_USLEEP_RANGE_STATE 1 +/* vfs_iocb_iter_read() is available */ +#define HAVE_VFS_IOCB_ITER_READ 1 + /* vga_client_register() don't pass a cookie */ #define HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6dbc197220238..fad1368258470 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -298,6 +298,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_FB_CREATE_FORMAT_INFO AC_AMDGPU_DRM_GET_FORMAT_INFO_2_ARGS + AC_AMDGPU_VFS_IOCB_ITER_READ AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/vfs_iocb_iter_read.m4 b/drivers/gpu/drm/amd/dkms/m4/vfs_iocb_iter_read.m4 new file mode 100644 index 0000000000000..5c70d0482dc09 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vfs_iocb_iter_read.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit: v5.5-rc7-11-g5dcdc43e24a1 +dnl # vfs: add vfs_iocb_iter_[read|write] helper functions +dnl # +AC_DEFUN([AC_AMDGPU_VFS_IOCB_ITER_READ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + vfs_iocb_iter_read(NULL, NULL, NULL); + ],[vfs_iocb_iter_read],[fs/read_write.c], [ + AC_DEFINE(HAVE_VFS_IOCB_ITER_READ, 1, + [vfs_iocb_iter_read() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_fs.h b/include/kcl/kcl_fs.h index db6b6ad389abf..ec3e04940e701 100644 --- a/include/kcl/kcl_fs.h +++ b/include/kcl/kcl_fs.h @@ -31,4 +31,13 @@ ssize_t _kcl_kernel_write(struct file *file, const void *buf, size_t count, #endif #endif +#ifndef HAVE_VFS_IOCB_ITER_READ +ssize_t kcl_vfs_iocb_iter_read(struct file *file, struct kiocb *iocb, + struct iov_iter *iter); +ssize_t kcl_vfs_iocb_iter_write(struct file *file, struct kiocb *iocb, + struct iov_iter *iter); +#define vfs_iocb_iter_read kcl_vfs_iocb_iter_read +#define vfs_iocb_iter_write kcl_vfs_iocb_iter_write +#endif + #endif From fee3bb29040cb6e8d4d79c6e312dcf17c1559828 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 17 Sep 2025 15:49:37 +0800 Subject: [PATCH 2005/2653] drm/amdkcl: test list_is_head() is available It's caused by the commit: feb3191 "drm/amdgpu: fix userq VM validation v4" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/list_is_head.m4 | 16 ++++++++++++++++ include/kcl/kcl_list.h | 7 +++++++ 4 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/list_is_head.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ce8d0f56eca0a..d3694ad6ec415 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1012,6 +1012,9 @@ /* list_is_first() is available */ #define HAVE_LIST_IS_FIRST 1 +/* list_is_head() is available */ +#define HAVE_LIST_IS_HEAD 1 + /* list_rotate_to_front() is available */ #define HAVE_LIST_ROTATE_TO_FRONT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fad1368258470..cf820a500bfdb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -299,6 +299,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_CREATE_FORMAT_INFO AC_AMDGPU_DRM_GET_FORMAT_INFO_2_ARGS AC_AMDGPU_VFS_IOCB_ITER_READ + AC_AMDGPU_LIST_IS_HEAD AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/list_is_head.m4 b/drivers/gpu/drm/amd/dkms/m4/list_is_head.m4 new file mode 100644 index 0000000000000..81db7cc617a1d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/list_is_head.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.16-23-g0425473037db +dnl # list: introduce list_is_head() helper and re-use it in list.h +dnl # +AC_DEFUN([AC_AMDGPU_LIST_IS_HEAD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + list_is_head(NULL, NULL); + ], [ + AC_DEFINE(HAVE_LIST_IS_HEAD, 1, + [list_is_head() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_list.h b/include/kcl/kcl_list.h index 20e2bee6bef61..a4790734f86c9 100644 --- a/include/kcl/kcl_list.h +++ b/include/kcl/kcl_list.h @@ -21,4 +21,11 @@ static inline int list_is_first(const struct list_head *list, } #endif +#if !defined(HAVE_LIST_IS_HEAD) +static inline int list_is_head(const struct list_head *list, const struct list_head *head) +{ + return list == head; +} +#endif + #endif /*AMDKCL_LIST_H*/ From c133ed624a62499f2e476dea59f191ce748f8a6d Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 17 Sep 2025 14:05:28 +0800 Subject: [PATCH 2006/2653] drm/amdkcl: test whether devm_i2c_add_adapter() is available It's caused by the commit: 379acbb3 "drm/amd/display: Use devm_i2c_add_adapter to simplify i2c cleanup logic" Signed-off-by: Chengjun Yao --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_i2c_core_base.c | 30 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../drm/amd/dkms/m4/devm_i2c_add_adapter.m4 | 16 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_i2c.h | 4 +++ 6 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_i2c_core_base.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/devm_i2c_add_adapter.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index ac6ff97260bb0..54408a4967250 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -17,7 +17,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o kcl_drm_drv.o \ - kcl_dma_fence_array.o kcl_dma_fence_unwrap.o kcl_drm_probe_helper.o + kcl_dma_fence_array.o kcl_dma_fence_unwrap.o kcl_drm_probe_helper.o kcl_i2c_core_base.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o kcl_debugfs_file.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_i2c_core_base.c b/drivers/gpu/drm/amd/amdkcl/kcl_i2c_core_base.c new file mode 100644 index 0000000000000..5f6690633f9ef --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_i2c_core_base.c @@ -0,0 +1,30 @@ +/* + * i2c-core-base.c - a device driver for the i2c bus interface + * Copyright (C) 1995-2000 Simon G. Vogl + * Copyright (C) 2013-2019 Wolfram Sang + * + * With some changes from Kyösti Mälkki and + * Frodo Looijaard + */ + +#include +#include + +#ifndef HAVE_DEVM_I2C_ADD_ADAPTER +static void kcl_devm_i2c_del_adapter(void *adapter) +{ + i2c_del_adapter(adapter); +} + +int kcl_devm_i2c_add_adapter(struct device *dev, struct i2c_adapter *adapter) +{ + int ret; + + ret = i2c_add_adapter(adapter); + if (ret) + return ret; + + return devm_add_action_or_reset(dev, kcl_devm_i2c_del_adapter, adapter); +} +EXPORT_SYMBOL_GPL(kcl_devm_i2c_add_adapter); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d3694ad6ec415..ebdae68c26743 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -127,6 +127,9 @@ /* MEMORY_DEVICE_COHERENT is availablea */ #define HAVE_DEVICE_COHERENT 1 +/* devm_i2c_add_adapter() is available */ +#define HAVE_DEVM_I2C_ADD_ADAPTER 1 + /* dev_is_removable() is available */ #define HAVE_DEV_IS_REMOVABLE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/devm_i2c_add_adapter.m4 b/drivers/gpu/drm/amd/dkms/m4/devm_i2c_add_adapter.m4 new file mode 100644 index 0000000000000..372c0904e731a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/devm_i2c_add_adapter.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.12-rc6-34-g07740c92ae57 +dnl # i2c: core: add managed function for adding i2c adapters +dnl # +AC_DEFUN([AC_AMDGPU_DEVM_I2C_ADD_ADAPTER], [ +AC_KERNEL_DO_BACKGROUND([ +AC_KERNEL_TRY_COMPILE_SYMBOL([ +#include + ], [ + devm_i2c_add_adapter(NULL, NULL); + ],[devm_i2c_add_adapter], [drivers/i2c/i2c-core-base.c],[ + AC_DEFINE(HAVE_DEVM_I2C_ADD_ADAPTER, 1, + [devm_i2c_add_adapter() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cf820a500bfdb..7d8b00ac6905f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -300,6 +300,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GET_FORMAT_INFO_2_ARGS AC_AMDGPU_VFS_IOCB_ITER_READ AC_AMDGPU_LIST_IS_HEAD + AC_AMDGPU_DEVM_I2C_ADD_ADAPTER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_i2c.h b/include/kcl/kcl_i2c.h index 2e7f36acdeadc..064fa63c6d2d6 100644 --- a/include/kcl/kcl_i2c.h +++ b/include/kcl/kcl_i2c.h @@ -29,5 +29,9 @@ i2c_new_client_device(struct i2c_adapter *adap, struct i2c_board_info const *inf #define I2C_AQ_NO_ZERO_LEN (I2C_AQ_NO_ZERO_LEN_READ | I2C_AQ_NO_ZERO_LEN_WRITE) #endif +#ifndef HAVE_DEVM_I2C_ADD_ADAPTER +extern int kcl_devm_i2c_add_adapter(struct device *dev, struct i2c_adapter *adapter); +#define devm_i2c_add_adapter kcl_devm_i2c_add_adapter +#endif #endif From 89d0f8e64d0eda2c7d6ee34c854954b9a0d15a99 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 10 Sep 2025 11:39:34 -0600 Subject: [PATCH 2007/2653] drm/amd/display: Use devm_i2c_add_adapter to simplify i2c cleanup logic This commit replaces the utilization of i2c_add/del_adapter() with devm_i2c_add_adapter() to reduce the amount of boilerplate. Using devm_i2c_add_adapter() has the advantage of removing the manual manipulation of the I2C adapter. Suggested-by: Robert Beckett Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 21 ++----------------- 1 file changed, 2 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ed9f373db5083..de4ccdc30fe2e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2984,7 +2984,7 @@ static int dm_oem_i2c_hw_init(struct amdgpu_device *adev) return -ENOMEM; } - r = i2c_add_adapter(&oem_i2c->base); + r = devm_i2c_add_adapter(adev->dev, &oem_i2c->base); if (r) { drm_info(adev_to_drm(adev), "Failed to register oem i2c\n"); kfree(oem_i2c); @@ -2996,17 +2996,6 @@ static int dm_oem_i2c_hw_init(struct amdgpu_device *adev) return 0; } -static void dm_oem_i2c_hw_fini(struct amdgpu_device *adev) -{ - struct amdgpu_display_manager *dm = &adev->dm; - - if (dm->oem_i2c) { - i2c_del_adapter(&dm->oem_i2c->base); - kfree(dm->oem_i2c); - dm->oem_i2c = NULL; - } -} - /** * dm_hw_init() - Initialize DC device * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. @@ -3057,8 +3046,6 @@ static int dm_hw_fini(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; - dm_oem_i2c_hw_fini(adev); - amdgpu_dm_hpd_fini(adev); amdgpu_dm_irq_fini(adev); @@ -7512,10 +7499,6 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector) drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); drm_connector_unregister(connector); drm_connector_cleanup(connector); - if (aconnector->i2c) { - i2c_del_adapter(&aconnector->i2c->base); - kfree(aconnector->i2c); - } kfree(aconnector->dm_dp_aux.aux.name); kfree(connector); } @@ -9030,7 +9013,7 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, } aconnector->i2c = i2c; - res = i2c_add_adapter(&i2c->base); + res = devm_i2c_add_adapter(dm->adev->dev, &i2c->base); if (res) { drm_err(adev_to_drm(dm->adev), "Failed to register hw i2c %d\n", link->link_index); From 10c43cd650735b01d4f3d99bfc63c05ab20b0f9f Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 10 Sep 2025 11:39:35 -0600 Subject: [PATCH 2008/2653] drm/amdgpu/amdgpu_i2c: Use devm_i2c_add_adapter instead of i2c_add_adapter This commit replaces i2c_add_adapter() with devm_i2c_add_adapter() and removes part of the cleanup logic since the new function handles the i2c removal. Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c index 57101d24422f2..9cb72f0c52773 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c @@ -184,7 +184,7 @@ struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev, snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), "AMDGPU i2c hw bus %s", name); i2c->adapter.algo = &amdgpu_atombios_i2c_algo; - ret = i2c_add_adapter(&i2c->adapter); + ret = devm_i2c_add_adapter(dev->dev, &i2c->adapter); if (ret) goto out_free; } else { @@ -215,15 +215,6 @@ struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev, } -void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c) -{ - if (!i2c) - return; - WARN_ON(i2c->has_aux); - i2c_del_adapter(&i2c->adapter); - kfree(i2c); -} - void amdgpu_i2c_init(struct amdgpu_device *adev) { if (!adev->is_atom_fw) { @@ -248,12 +239,9 @@ void amdgpu_i2c_fini(struct amdgpu_device *adev) { int i; - for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { - if (adev->i2c_bus[i]) { - amdgpu_i2c_destroy(adev->i2c_bus[i]); + for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) + if (adev->i2c_bus[i]) adev->i2c_bus[i] = NULL; - } - } } /* looks up bus based on id */ From 964d7950b24b7d64cd4270443ce3ada16dc9b8a1 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 10 Sep 2025 11:39:36 -0600 Subject: [PATCH 2009/2653] drm/amdgpu: Use devm_i2c_add_adapter() in SMU V11 Instead of using i2c_add_adapter() and i2c_del_adapter() in the SMU V11, use devm_i2c_add_adapter() to simplify the code path. Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c index 2de46087444c7..49552e88d1368 100644 --- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c +++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c @@ -755,7 +755,7 @@ int smu_v11_0_i2c_control_init(struct amdgpu_device *adev) adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; - res = i2c_add_adapter(control); + res = devm_i2c_add_adapter(adev->dev, control); if (res) DRM_ERROR("Failed to register hw i2c, err: %d\n", res); @@ -764,9 +764,6 @@ int smu_v11_0_i2c_control_init(struct amdgpu_device *adev) void smu_v11_0_i2c_control_fini(struct amdgpu_device *adev) { - struct i2c_adapter *control = adev->pm.ras_eeprom_i2c_bus; - - i2c_del_adapter(control); adev->pm.ras_eeprom_i2c_bus = NULL; adev->pm.fru_eeprom_i2c_bus = NULL; } From 042764bef731cc328399d702274ff7b82f5c0686 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 10 Sep 2025 11:39:37 -0600 Subject: [PATCH 2010/2653] drm/amd/pm: Use devm_i2c_add_adapter() in the i2c init Instead of using i2c_add_adapter() and i2c_del_adapter(), replace them with devm_i2c_add_adapter() to simplify the i2c logic. Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- .../gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index b067147b7c41f..18d5d07045098 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -1641,33 +1641,22 @@ static int aldebaran_i2c_control_init(struct smu_context *smu) control->quirks = &aldebaran_i2c_control_quirks; i2c_set_adapdata(control, smu_i2c); - res = i2c_add_adapter(control); + res = devm_i2c_add_adapter(adev->dev, control); if (res) { DRM_ERROR("Failed to register hw i2c, err: %d\n", res); - goto Out_err; + return res; } adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; return 0; -Out_err: - i2c_del_adapter(control); - - return res; } static void aldebaran_i2c_control_fini(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - int i; - - for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { - struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; - struct i2c_adapter *control = &smu_i2c->adapter; - i2c_del_adapter(control); - } adev->pm.ras_eeprom_i2c_bus = NULL; adev->pm.fru_eeprom_i2c_bus = NULL; } From c08297de62bbfe4137286cdf6d35ab11f0b635d1 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 10 Sep 2025 11:39:38 -0600 Subject: [PATCH 2011/2653] drm/amd/pm: Use devm_i2c_add_adapter() in the Arcturus smu The I2C init for Arcturus uses i2c_add_adapter() and i2c_del_adapter(), this commit replaces the use of these two functions with devm_i2c_add_adapter(). Notice that Arcturus init initializes multiple I2C buses in a loop; if something goes wrong, the previous adapters are removed, and the amdgpu load is interrupted. Since I2C init is required for the correct load of amdgpu, it is safe to rely on devm_i2c_add_adapter() to handle any previously initialized I2C adapter. Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c index 599eddb5a67d5..4fff78da81ff8 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c @@ -1745,10 +1745,10 @@ static int arcturus_i2c_control_init(struct smu_context *smu) snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); i2c_set_adapdata(control, smu_i2c); - res = i2c_add_adapter(control); + res = devm_i2c_add_adapter(adev->dev, control); if (res) { DRM_ERROR("Failed to register hw i2c, err: %d\n", res); - goto Out_err; + return res; } } @@ -1756,27 +1756,12 @@ static int arcturus_i2c_control_init(struct smu_context *smu) adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; return 0; -Out_err: - for ( ; i >= 0; i--) { - struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; - struct i2c_adapter *control = &smu_i2c->adapter; - - i2c_del_adapter(control); - } - return res; } static void arcturus_i2c_control_fini(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - int i; - for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { - struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; - struct i2c_adapter *control = &smu_i2c->adapter; - - i2c_del_adapter(control); - } adev->pm.ras_eeprom_i2c_bus = NULL; adev->pm.fru_eeprom_i2c_bus = NULL; } From c48cc30fd97d3c6b2d358086c7ff172b232f1a58 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 10 Sep 2025 11:39:39 -0600 Subject: [PATCH 2012/2653] drm/amd/pm: Use devm_i2c_add_adapter() in the Navi10 smu The I2C init for Navi10 uses i2c_add_adapter() and i2c_del_adapter(), this commit replaces the use of these two functions with devm_i2c_add_adapter(). Notice that Navi10 init initializes multiple I2C buses in a loop; if something goes wrong, the previous adapters are removed, and the amdgpu load is interrupted. Since I2C init is required for the correct load of amdgpu, it is safe to rely on devm_i2c_add_adapter() to handle any previously initialized I2C adapter. Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index aac202d0c30e5..0028f10ead423 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -3145,10 +3145,10 @@ static int navi10_i2c_control_init(struct smu_context *smu) control->quirks = &navi10_i2c_control_quirks; i2c_set_adapdata(control, smu_i2c); - res = i2c_add_adapter(control); + res = devm_i2c_add_adapter(adev->dev, control); if (res) { DRM_ERROR("Failed to register hw i2c, err: %d\n", res); - goto Out_err; + return res; } } @@ -3156,27 +3156,12 @@ static int navi10_i2c_control_init(struct smu_context *smu) adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; return 0; -Out_err: - for ( ; i >= 0; i--) { - struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; - struct i2c_adapter *control = &smu_i2c->adapter; - - i2c_del_adapter(control); - } - return res; } static void navi10_i2c_control_fini(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - int i; - for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { - struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; - struct i2c_adapter *control = &smu_i2c->adapter; - - i2c_del_adapter(control); - } adev->pm.ras_eeprom_i2c_bus = NULL; adev->pm.fru_eeprom_i2c_bus = NULL; } From 4405308b8c327e7d93d71938164f9d88a90866ee Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 10 Sep 2025 11:39:40 -0600 Subject: [PATCH 2013/2653] drm/amd/pm: Use devm_i2c_add_adapter() in the Sienna smu The I2C init for Sienna Cichlid uses i2c_add_adapter() and i2c_del_adapter(), this commit replaces the use of these two functions with devm_i2c_add_adapter(). Notice that Sienna Cichlid init initializes multiple I2C buses in a loop; if something goes wrong, the previous adapters are removed, and the amdgpu load is interrupted. Since I2C init is required for the correct load of amdgpu, it is safe to rely on devm_i2c_add_adapter() to handle any previously initialized I2C adapter. Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 29090d3dba2ea..4ce4c1fbe09fa 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -2648,10 +2648,10 @@ static int sienna_cichlid_i2c_control_init(struct smu_context *smu) control->quirks = &sienna_cichlid_i2c_control_quirks; i2c_set_adapdata(control, smu_i2c); - res = i2c_add_adapter(control); + res = devm_i2c_add_adapter(adev->dev, control); if (res) { DRM_ERROR("Failed to register hw i2c, err: %d\n", res); - goto Out_err; + return res; } } /* assign the buses used for the FRU EEPROM and RAS EEPROM */ @@ -2660,27 +2660,12 @@ static int sienna_cichlid_i2c_control_init(struct smu_context *smu) adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; return 0; -Out_err: - for ( ; i >= 0; i--) { - struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; - struct i2c_adapter *control = &smu_i2c->adapter; - - i2c_del_adapter(control); - } - return res; } static void sienna_cichlid_i2c_control_fini(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - int i; - for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { - struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; - struct i2c_adapter *control = &smu_i2c->adapter; - - i2c_del_adapter(control); - } adev->pm.ras_eeprom_i2c_bus = NULL; adev->pm.fru_eeprom_i2c_bus = NULL; } From a8cfd043d5316c36a211d37ed5afa075136416e4 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 10 Sep 2025 11:39:41 -0600 Subject: [PATCH 2014/2653] drm/amd/pm: Use devm_i2c_add_adapter() in the V13 smu The I2C init for SMU_V13 uses i2c_add_adapter() and i2c_del_adapter(), this commit replaces the use of these two functions with devm_i2c_add_adapter(). Notice that SMU_V13 init initializes multiple I2C buses in a loop; if something goes wrong, the previous adapters are removed, and the amdgpu load is interrupted. Since I2C init is required for the correct load of amdgpu, it is safe to rely on devm_i2c_add_adapter() to handle any previously initialized I2C adapter. Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index 7902fc4cd3bc5..3cea7dc733f4b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -2825,10 +2825,10 @@ static int smu_v13_0_0_i2c_control_init(struct smu_context *smu) control->quirks = &smu_v13_0_0_i2c_control_quirks; i2c_set_adapdata(control, smu_i2c); - res = i2c_add_adapter(control); + res = devm_i2c_add_adapter(adev->dev, control); if (res) { DRM_ERROR("Failed to register hw i2c, err: %d\n", res); - goto Out_err; + return res; } } @@ -2838,27 +2838,12 @@ static int smu_v13_0_0_i2c_control_init(struct smu_context *smu) adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; return 0; -Out_err: - for ( ; i >= 0; i--) { - struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; - struct i2c_adapter *control = &smu_i2c->adapter; - - i2c_del_adapter(control); - } - return res; } static void smu_v13_0_0_i2c_control_fini(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - int i; - for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { - struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; - struct i2c_adapter *control = &smu_i2c->adapter; - - i2c_del_adapter(control); - } adev->pm.ras_eeprom_i2c_bus = NULL; adev->pm.fru_eeprom_i2c_bus = NULL; } From 2b282bf59119fb82ca78626c039d7bdb8e41170a Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 10 Sep 2025 11:39:42 -0600 Subject: [PATCH 2015/2653] drm/amd/pm: Use devm_i2c_add_adapter() in the V13_0_6 smu The I2C init for V13_0_6 uses i2c_add_adapter() and i2c_del_adapter(), this commit replaces the use of these two functions with devm_i2c_add_adapter(). Notice that V13_0_6 init initializes multiple I2C buses in a loop; if something goes wrong, the previous adapters are removed, and the amdgpu load is interrupted. Since I2C init is required for the correct load of amdgpu, it is safe to rely on devm_i2c_add_adapter() to handle any previously initialized I2C adapter. Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index d6a0005a509cd..945d72cd7232e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -2653,10 +2653,10 @@ static int smu_v13_0_6_i2c_control_init(struct smu_context *smu) control->quirks = &smu_v13_0_6_i2c_control_quirks; i2c_set_adapdata(control, smu_i2c); - res = i2c_add_adapter(control); + res = devm_i2c_add_adapter(adev->dev, control); if (res) { DRM_ERROR("Failed to register hw i2c, err: %d\n", res); - goto Out_err; + return res; } } @@ -2664,27 +2664,12 @@ static int smu_v13_0_6_i2c_control_init(struct smu_context *smu) adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; return 0; -Out_err: - for ( ; i >= 0; i--) { - struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; - struct i2c_adapter *control = &smu_i2c->adapter; - - i2c_del_adapter(control); - } - return res; } static void smu_v13_0_6_i2c_control_fini(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - int i; - for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { - struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; - struct i2c_adapter *control = &smu_i2c->adapter; - - i2c_del_adapter(control); - } adev->pm.ras_eeprom_i2c_bus = NULL; adev->pm.fru_eeprom_i2c_bus = NULL; } From 14c82b857f2d9c02c41f014b93eb0a957a9b2771 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 10 Sep 2025 11:39:43 -0600 Subject: [PATCH 2016/2653] drm/amd/pm: Use devm_i2c_add_adapter() in the V14_0_2 smu The I2C init for V14_0_2 uses i2c_add_adapter() and i2c_del_adapter(), this commit replaces the use of these two functions with devm_i2c_add_adapter(). Notice that V14_0_2 init initializes multiple I2C buses in a loop; if something goes wrong, the previous adapters are removed, and the amdgpu load is interrupted. Since I2C init is required for the correct load of amdgpu, it is safe to rely on devm_i2c_add_adapter() to handle any previously initialized I2C adapter. Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index f32474af90b34..086501cc5213b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -2087,10 +2087,10 @@ static int smu_v14_0_2_i2c_control_init(struct smu_context *smu) control->quirks = &smu_v14_0_2_i2c_control_quirks; i2c_set_adapdata(control, smu_i2c); - res = i2c_add_adapter(control); + res = devm_i2c_add_adapter(adev->dev, control); if (res) { DRM_ERROR("Failed to register hw i2c, err: %d\n", res); - goto Out_err; + return res; } } @@ -2100,27 +2100,12 @@ static int smu_v14_0_2_i2c_control_init(struct smu_context *smu) adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; return 0; -Out_err: - for ( ; i >= 0; i--) { - struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; - struct i2c_adapter *control = &smu_i2c->adapter; - - i2c_del_adapter(control); - } - return res; } static void smu_v14_0_2_i2c_control_fini(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - int i; - for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { - struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; - struct i2c_adapter *control = &smu_i2c->adapter; - - i2c_del_adapter(control); - } adev->pm.ras_eeprom_i2c_bus = NULL; adev->pm.fru_eeprom_i2c_bus = NULL; } From c48ccdaf5fbafa48d39de4f245ce4fbc8e62ec10 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Mon, 15 Sep 2025 20:59:02 -0500 Subject: [PATCH 2017/2653] drm/amd: Only restore cached manual clock settings in restore if OD enabled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If OD is not enabled then restoring cached clock settings doesn't make sense and actually leads to errors in resume. Check if enabled before restoring settings. Fixes: 796ff8a7e01bd ("drm/amd: Restore cached manual clock settings during resume") Cc: stable@vger.kernel.org Reported-by: Jérôme Lécuyer Closes: https://lore.kernel.org/amd-gfx/0ffe2692-7bfa-4821-856e-dd0f18e2c32b@amd.com/T/#me6db8ddb192626360c462b7570ed7eba0c6c9733 Suggested-by: Jérôme Lécuyer Acked-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 804cae7af9dfa..91e112491dec2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2263,7 +2263,7 @@ static int smu_resume(struct amdgpu_ip_block *ip_block) return ret; } - if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { + if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL && smu->od_enabled) { ret = smu_od_edit_dpm_table(smu, PP_OD_COMMIT_DPM_TABLE, NULL, 0); if (ret) return ret; From f753f1cbd189ba0f6c0583cafd66ee9082524df3 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Mon, 15 Sep 2025 17:42:44 +0800 Subject: [PATCH 2018/2653] drm/amd/pm: Rename amdgpu_hwmon_get_sensor_generic Rename amdgpu_hwmon_get_sensor_generic to use for generic pm interfaces Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Reviewed-by: Yang Wang --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 76 +++++++++++++++--------------- 1 file changed, 39 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 028c63c561683..7ef4058db7f8d 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -1421,9 +1421,9 @@ static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev, return -EINVAL; } -static int amdgpu_hwmon_get_sensor_generic(struct amdgpu_device *adev, - enum amd_pp_sensors sensor, - void *query) +static int amdgpu_pm_get_sensor_generic(struct amdgpu_device *adev, + enum amd_pp_sensors sensor, + void *query) { int r, size = sizeof(uint32_t); @@ -1456,7 +1456,7 @@ static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev, unsigned int value; int r; - r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value); + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value); if (r) return r; @@ -1480,7 +1480,7 @@ static ssize_t amdgpu_get_mem_busy_percent(struct device *dev, unsigned int value; int r; - r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_LOAD, &value); + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_LOAD, &value); if (r) return r; @@ -1504,7 +1504,7 @@ static ssize_t amdgpu_get_vcn_busy_percent(struct device *dev, unsigned int value; int r; - r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VCN_LOAD, &value); + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VCN_LOAD, &value); if (r) return r; @@ -1783,7 +1783,7 @@ static int amdgpu_show_powershift_percent(struct device *dev, uint32_t ss_power; int r = 0, i; - r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power); + r = amdgpu_pm_get_sensor_generic(adev, sensor, (void *)&ss_power); if (r == -EOPNOTSUPP) { /* sensor not available on dGPU, try to read from APU */ adev = NULL; @@ -1796,7 +1796,7 @@ static int amdgpu_show_powershift_percent(struct device *dev, } mutex_unlock(&mgpu_info.mutex); if (adev) - r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power); + r = amdgpu_pm_get_sensor_generic(adev, sensor, (void *)&ss_power); } if (r) @@ -1906,11 +1906,11 @@ static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ if (!amdgpu_device_supports_smart_shift(adev)) *states = ATTR_STATE_UNSUPPORTED; - else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE, - (void *)&ss_power)) + else if (amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE, + (void *)&ss_power)) *states = ATTR_STATE_UNSUPPORTED; - else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE, - (void *)&ss_power)) + else if (amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE, + (void *)&ss_power)) *states = ATTR_STATE_UNSUPPORTED; return 0; @@ -2636,18 +2636,18 @@ static ssize_t amdgpu_hwmon_show_temp(struct device *dev, switch (channel) { case PP_TEMP_JUNCTION: /* get current junction temperature */ - r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP, - (void *)&temp); + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP, + (void *)&temp); break; case PP_TEMP_EDGE: /* get current edge temperature */ - r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_EDGE_TEMP, - (void *)&temp); + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_EDGE_TEMP, + (void *)&temp); break; case PP_TEMP_MEM: /* get current memory temperature */ - r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_TEMP, - (void *)&temp); + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_TEMP, + (void *)&temp); break; default: r = -EINVAL; @@ -2909,8 +2909,8 @@ static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev, u32 min_rpm = 0; int r; - r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM, - (void *)&min_rpm); + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM, + (void *)&min_rpm); if (r) return r; @@ -2926,8 +2926,8 @@ static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev, u32 max_rpm = 0; int r; - r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM, - (void *)&max_rpm); + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM, + (void *)&max_rpm); if (r) return r; @@ -3060,8 +3060,8 @@ static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev, int r; /* get the voltage */ - r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDGFX, - (void *)&vddgfx); + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDGFX, + (void *)&vddgfx); if (r) return r; @@ -3077,8 +3077,8 @@ static ssize_t amdgpu_hwmon_show_vddboard(struct device *dev, int r; /* get the voltage */ - r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDBOARD, - (void *)&vddboard); + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDBOARD, + (void *)&vddboard); if (r) return r; @@ -3111,8 +3111,8 @@ static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev, return -EINVAL; /* get the voltage */ - r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDNB, - (void *)&vddnb); + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDNB, + (void *)&vddnb); if (r) return r; @@ -3134,7 +3134,7 @@ static int amdgpu_hwmon_get_power(struct device *dev, u32 query = 0; int r; - r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&query); + r = amdgpu_pm_get_sensor_generic(adev, sensor, (void *)&query); if (r) return r; @@ -3284,8 +3284,8 @@ static ssize_t amdgpu_hwmon_show_sclk(struct device *dev, int r; /* get the sclk */ - r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_SCLK, - (void *)&sclk); + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_SCLK, + (void *)&sclk); if (r) return r; @@ -3308,8 +3308,8 @@ static ssize_t amdgpu_hwmon_show_mclk(struct device *dev, int r; /* get the sclk */ - r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_MCLK, - (void *)&mclk); + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_MCLK, + (void *)&mclk); if (r) return r; @@ -3607,10 +3607,12 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, /* not all products support both average and instantaneous */ if (attr == &sensor_dev_attr_power1_average.dev_attr.attr && - amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&tmp) == -EOPNOTSUPP) + amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, + (void *)&tmp) == -EOPNOTSUPP) return 0; if (attr == &sensor_dev_attr_power1_input.dev_attr.attr && - amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&tmp) == -EOPNOTSUPP) + amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, + (void *)&tmp) == -EOPNOTSUPP) return 0; /* hide max/min values if we can't both query and manage the fan */ @@ -3649,8 +3651,8 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, /* only few boards support vddboard */ if ((attr == &sensor_dev_attr_in2_input.dev_attr.attr || attr == &sensor_dev_attr_in2_label.dev_attr.attr) && - amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDBOARD, - (void *)&tmp) == -EOPNOTSUPP) + amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDBOARD, + (void *)&tmp) == -EOPNOTSUPP) return 0; /* no mclk on APUs other than gc 9,4,3*/ From 0b5bf2dc55f9074f1226f21a17b3f72c178bbe5f Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Wed, 27 Aug 2025 18:19:13 +0800 Subject: [PATCH 2019/2653] drm/amd/pm: Update pmfw headers for smu_v13_0_12 Update pmfw headers for smu_v13_0_12 to include node power limit Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Reviewed-by: Yang Wang --- .../drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h index 1c407a8e96ee3..bf6aa9620911b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h @@ -191,7 +191,7 @@ typedef enum { #define SMU_METRICS_TABLE_VERSION 0x14 -#define SMU_SYSTEM_METRICS_TABLE_VERSION 0x0 +#define SMU_SYSTEM_METRICS_TABLE_VERSION 0x1 typedef struct __attribute__((packed, aligned(4))) { uint64_t AccumulationCounter; @@ -304,7 +304,12 @@ typedef struct { int16_t SystemTemperatures[SYSTEM_TEMP_MAX_ENTRIES]; // Signed integer temperature value in Celsius, unused fields are set to 0xFFFF int16_t NodeTemperatures[NODE_TEMP_MAX_TEMP_ENTRIES]; // Signed integer temperature value in Celsius, unused fields are set to 0xFFFF int16_t VrTemperatures[SVI_MAX_TEMP_ENTRIES]; // Signed integer temperature value in Celsius - int16_t spare[3]; + int16_t spare[7]; + + //NPM: NODE POWER MANAGEMENT + uint32_t NodePowerLimit; + uint32_t NodePower; + uint32_t GlobalPPTResidencyAcc; } SystemMetricsTable_t; #pragma pack(pop) @@ -359,6 +364,9 @@ typedef struct { // General info uint32_t pldmVersion[2]; + + //Node Power Limit + uint32_t MaxNodePowerLimit; } StaticMetricsTable_t; #pragma pack(pop) From 76b5219ed8f5a45bb82ea446b059ab20e7f78aef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 27 Aug 2025 10:17:48 +0200 Subject: [PATCH 2020/2653] drm/amdgpu: remove check for BO reservation add assert instead MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We should leave such checks to lockdep and not implement something manually. Signed-off-by: Christian König Acked-by: Sunil Khatri Reviewed-by: Prike Liang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 49ff847ab30e8..2d1dc89ed11e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -666,18 +666,7 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, spin_unlock(&vm->status_lock); bo = bo_base->bo; - - if (dma_resv_locking_ctx(amdkcl_ttm_resvp(&bo->tbo)) != ticket) { - struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm); - - pr_warn_ratelimited("Evicted user BO is not reserved\n"); - if (ti) { - pr_warn_ratelimited("pid %d\n", ti->task.pid); - amdgpu_vm_put_task_info(ti); - } - - return -EINVAL; - } + dma_resv_assert_held(bo->tbo.base.resv); r = validate(param, bo); if (r) From 5b1dedfbad37d1e1229784498f72a2c6867fcfae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 27 Aug 2025 11:45:45 +0200 Subject: [PATCH 2021/2653] drm/amdgpu: re-order and document VM code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Re-order fields in the VM structure and try to improve the documentation a bit. Signed-off-by: Christian König Reviewed-by: Sunil Khatri Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 30 ++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 8d2474bf4f9c6..3fba271c1676f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -353,12 +353,16 @@ struct amdgpu_vm { /* Memory statistics for this vm, protected by status_lock */ struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM]; + /* + * The following lists contain amdgpu_vm_bo_base objects for either + * PDs, PTs or per VM BOs. The state transits are: + * + * evicted -> relocated (PDs, PTs) or moved (per VM BOs) -> idle + */ + /* Per-VM and PT BOs who needs a validation */ struct list_head evicted; - /* BOs for user mode queues that need a validation */ - struct list_head evicted_user; - /* PT BOs which relocated and their parent need an update */ struct list_head relocated; @@ -368,15 +372,29 @@ struct amdgpu_vm { /* All BOs of this VM not currently in the state machine */ struct list_head idle; + /* + * The following lists contain amdgpu_vm_bo_base objects for BOs which + * have their own dma_resv object and not depend on the root PD. Their + * state transits are: + * + * evicted_user or invalidated -> done + */ + + /* BOs for user mode queues that need a validation */ + struct list_head evicted_user; + /* regular invalidated BOs, but not yet updated in the PT */ struct list_head invalidated; - /* BO mappings freed, but not yet updated in the PT */ - struct list_head freed; - /* BOs which are invalidated, has been updated in the PTs */ struct list_head done; + /* + * This list contains amdgpu_bo_va_mapping objects which have been freed + * but not updated in the PTs + */ + struct list_head freed; + /* contains the page directory */ struct amdgpu_vm_bo_base root; struct dma_fence *last_update; From bd5179340402acb4bc4ad2413d4d5759ace244ed Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Mon, 15 Sep 2025 17:53:19 +0800 Subject: [PATCH 2022/2653] drm/amd/pm: Allow system metrics table in 1vf mode Allow fetching system metrics table in 1VF mode Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Reviewed-by: Yang Wang --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index 0bec12b348ced..f10228de416c6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -137,7 +137,7 @@ const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[SMU_MSG_MAX_COUNT] = MSG_MAP(SetThrottlingPolicy, PPSMC_MSG_SetThrottlingPolicy, 0), MSG_MAP(ResetSDMA, PPSMC_MSG_ResetSDMA, 0), MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 1), - MSG_MAP(GetSystemMetricsTable, PPSMC_MSG_GetSystemMetricsTable, 0), + MSG_MAP(GetSystemMetricsTable, PPSMC_MSG_GetSystemMetricsTable, 1), }; int smu_v13_0_12_tables_init(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 945d72cd7232e..7de4f5b2fa716 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -364,6 +364,8 @@ static void smu_v13_0_12_init_caps(struct smu_context *smu) if (fw_ver >= 0x04560700) { if (!amdgpu_sriov_vf(smu->adev)) smu_v13_0_6_cap_set(smu, SMU_CAP(TEMP_METRICS)); + else if (fw_ver >= 0x04560900) + smu_v13_0_6_cap_set(smu, SMU_CAP(TEMP_METRICS)); } else { smu_v13_0_12_tables_fini(smu); } From 6dda59dad9ce4bcca9f1f524212388175d3ef675 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Wed, 27 Aug 2025 21:22:13 +0800 Subject: [PATCH 2023/2653] drm/amd/pm: Add sysfs node for node power Add sysfs node to expose node power limit for smu_v13_0_12 v2: Remove support check from visible function (Kevin) v3: Update comments (Kevin) Remove sysfs remove file, change format specifier for sysfs_emit, use attribute_group.name (Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Reviewed-by: Yang Wang --- .../gpu/drm/amd/include/kgd_pp_interface.h | 4 + drivers/gpu/drm/amd/pm/amdgpu_pm.c | 151 +++++++++++++++++- 2 files changed, 153 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index 8d562b0a401c9..e23a10157f506 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -162,6 +162,10 @@ enum amd_pp_sensors { AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, AMDGPU_PP_SENSOR_VCN_LOAD, + AMDGPU_PP_SENSOR_NODEPOWERLIMIT, + AMDGPU_PP_SENSOR_NODEPOWER, + AMDGPU_PP_SENSOR_GPPTRESIDENCY, + AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT, }; enum amd_pp_task { diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 7ef4058db7f8d..0b621a8265cfb 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -2081,8 +2081,9 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd * for user application to monitor various board reated attributes. * * The amdgpu driver provides a sysfs API for reporting board attributes. Presently, - * only two types of attributes are reported, baseboard temperature and - * gpu board temperature. Both of them are reported as binary files. + * seven types of attributes are reported. Baseboard temperature and + * gpu board temperature are reported as binary files. Npm status, current node power limit, + * max node power limit, node power and global ppt residency is reported as ASCII text file. * * * .. code-block:: console * @@ -2090,6 +2091,15 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd * * hexdump /sys/bus/pci/devices/.../board/gpuboard_temp * + * hexdump /sys/bus/pci/devices/.../board/npm_status + * + * hexdump /sys/bus/pci/devices/.../board/cur_node_power_limit + * + * hexdump /sys/bus/pci/devices/.../board/max_node_power_limit + * + * hexdump /sys/bus/pci/devices/.../board/node_power + * + * hexdump /sys/bus/pci/devices/.../board/global_ppt_resid */ /** @@ -2168,8 +2178,129 @@ static ssize_t amdgpu_get_gpuboard_temp_metrics(struct device *dev, return size; } +/** + * DOC: cur_node_power_limit + * + * The amdgpu driver provides a sysfs API for retrieving current node power limit. + * The file cur_node_power_limit is used for this. + */ +static ssize_t amdgpu_show_cur_node_power_limit(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + u32 nplimit; + int r; + + /* get the current node power limit */ + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_NODEPOWERLIMIT, + (void *)&nplimit); + if (r) + return r; + + return sysfs_emit(buf, "%u\n", nplimit); +} + +/** + * DOC: node_power + * + * The amdgpu driver provides a sysfs API for retrieving current node power. + * The file node_power is used for this. + */ +static ssize_t amdgpu_show_node_power(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + u32 npower; + int r; + + /* get the node power */ + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_NODEPOWER, + (void *)&npower); + if (r) + return r; + + return sysfs_emit(buf, "%u\n", npower); +} + +/** + * DOC: npm_status + * + * The amdgpu driver provides a sysfs API for retrieving current node power management status. + * The file npm_status is used for this. It shows the status as enabled or disabled based on + * current node power value. If node power is zero, status is disabled else enabled. + */ +static ssize_t amdgpu_show_npm_status(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + u32 npower; + int r; + + /* get the node power */ + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_NODEPOWER, + (void *)&npower); + if (r) + return r; + + return sysfs_emit(buf, "%s\n", npower ? "enabled" : "disabled"); +} + +/** + * DOC: global_ppt_resid + * + * The amdgpu driver provides a sysfs API for retrieving global ppt residency. + * The file global_ppt_resid is used for this. + */ +static ssize_t amdgpu_show_global_ppt_resid(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + u32 gpptresid; + int r; + + /* get the global ppt residency */ + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPPTRESIDENCY, + (void *)&gpptresid); + if (r) + return r; + + return sysfs_emit(buf, "%u\n", gpptresid); +} + +/** + * DOC: max_node_power_limit + * + * The amdgpu driver provides a sysfs API for retrieving maximum node power limit. + * The file max_node_power_limit is used for this. + */ +static ssize_t amdgpu_show_max_node_power_limit(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + u32 max_nplimit; + int r; + + /* get the max node power limit */ + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT, + (void *)&max_nplimit); + if (r) + return r; + + return sysfs_emit(buf, "%u\n", max_nplimit); +} + static DEVICE_ATTR(baseboard_temp, 0444, amdgpu_get_baseboard_temp_metrics, NULL); static DEVICE_ATTR(gpuboard_temp, 0444, amdgpu_get_gpuboard_temp_metrics, NULL); +static DEVICE_ATTR(cur_node_power_limit, 0444, amdgpu_show_cur_node_power_limit, NULL); +static DEVICE_ATTR(node_power, 0444, amdgpu_show_node_power, NULL); +static DEVICE_ATTR(global_ppt_resid, 0444, amdgpu_show_global_ppt_resid, NULL); +static DEVICE_ATTR(max_node_power_limit, 0444, amdgpu_show_max_node_power_limit, NULL); +static DEVICE_ATTR(npm_status, 0444, amdgpu_show_npm_status, NULL); static struct attribute *board_attrs[] = { &dev_attr_baseboard_temp.attr, @@ -4534,6 +4665,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) { enum amdgpu_sriov_vf_mode mode; uint32_t mask = 0; + uint32_t tmp; int ret; if (adev->pm.sysfs_initialized) @@ -4602,6 +4734,21 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) &amdgpu_board_attr_group); if (ret) goto err_out0; + if (amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT, + (void *)&tmp) != -EOPNOTSUPP) { + sysfs_add_file_to_group(&adev->dev->kobj, + &dev_attr_cur_node_power_limit.attr, + amdgpu_board_attr_group.name); + sysfs_add_file_to_group(&adev->dev->kobj, &dev_attr_node_power.attr, + amdgpu_board_attr_group.name); + sysfs_add_file_to_group(&adev->dev->kobj, &dev_attr_global_ppt_resid.attr, + amdgpu_board_attr_group.name); + sysfs_add_file_to_group(&adev->dev->kobj, + &dev_attr_max_node_power_limit.attr, + amdgpu_board_attr_group.name); + sysfs_add_file_to_group(&adev->dev->kobj, &dev_attr_npm_status.attr, + amdgpu_board_attr_group.name); + } } adev->pm.sysfs_initialized = true; From 505789d752cf5e5d784bfd5f20d21c9dac00a032 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Fri, 29 Aug 2025 12:25:54 +0800 Subject: [PATCH 2024/2653] drm/amd/pm: Fetch npm data from system metrics table Fetch npm data from system metrics table for smu_v13_0_12 v3: Remove intermittent type for npm data, remove node id check, move npm caps check to npm_get_data function (Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Reviewed-by: Yang Wang --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 47 +++++++++++++++++++ .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 9 ++++ .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 5 ++ 3 files changed, 61 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index f10228de416c6..1842a33b2bce7 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -341,6 +341,9 @@ int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu) static_metrics->pldmVersion[0] != 0xFFFFFFFF) smu->adev->firmware.pldm_version = static_metrics->pldmVersion[0]; + if (smu_v13_0_6_cap_supported(smu, SMU_CAP(NPM_METRICS))) + pptable->MaxNodePowerLimit = + SMUQ10_ROUND(static_metrics->MaxNodePowerLimit); smu_v13_0_12_init_xgmi_data(smu, static_metrics); pptable->Init = true; } @@ -580,6 +583,50 @@ static bool smu_v13_0_12_is_temp_metrics_supported(struct smu_context *smu, return false; } +int smu_v13_0_12_get_npm_data(struct smu_context *smu, + enum amd_pp_sensors sensor, + uint32_t *value) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct PPTable_t *pptable = + (struct PPTable_t *)smu_table->driver_pptable; + struct smu_table *tables = smu_table->tables; + SystemMetricsTable_t *metrics; + struct smu_table *sys_table; + int ret; + + if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(NPM_METRICS))) + return -EOPNOTSUPP; + + if (sensor == AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT) { + *value = pptable->MaxNodePowerLimit; + return 0; + } + + ret = smu_v13_0_12_get_system_metrics_table(smu); + if (ret) + return ret; + + sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; + metrics = (SystemMetricsTable_t *)sys_table->cache.buffer; + + switch (sensor) { + case AMDGPU_PP_SENSOR_NODEPOWERLIMIT: + *value = SMUQ10_ROUND(metrics->NodePowerLimit); + break; + case AMDGPU_PP_SENSOR_NODEPOWER: + *value = SMUQ10_ROUND(metrics->NodePower); + break; + case AMDGPU_PP_SENSOR_GPPTRESIDENCY: + *value = SMUQ10_ROUND(metrics->GlobalPPTResidencyAcc); + break; + default: + return -EINVAL; + } + + return ret; +} + static ssize_t smu_v13_0_12_get_temp_metrics(struct smu_context *smu, enum smu_temp_metric_type type, void *table) { diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 7de4f5b2fa716..b879a7a700152 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -1960,6 +1960,15 @@ static int smu_v13_0_6_read_sensor(struct smu_context *smu, ret = -EOPNOTSUPP; break; } + case AMDGPU_PP_SENSOR_NODEPOWERLIMIT: + case AMDGPU_PP_SENSOR_NODEPOWER: + case AMDGPU_PP_SENSOR_GPPTRESIDENCY: + case AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT: + ret = smu_v13_0_12_get_npm_data(smu, sensor, (uint32_t *)data); + if (ret) + return ret; + *size = 4; + break; case AMDGPU_PP_SENSOR_GPU_AVG_POWER: default: ret = -EOPNOTSUPP; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h index 4652fcd5e0683..7ef5f3e66c273 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h @@ -49,6 +49,7 @@ struct PPTable_t { uint32_t MaxLclkDpmRange; uint32_t MinLclkDpmRange; uint64_t PublicSerialNumber_AID; + uint32_t MaxNodePowerLimit; bool Init; }; @@ -70,6 +71,7 @@ enum smu_v13_0_6_caps { SMU_CAP(BOARD_VOLTAGE), SMU_CAP(PLDM_VERSION), SMU_CAP(TEMP_METRICS), + SMU_CAP(NPM_METRICS), SMU_CAP(ALL), }; @@ -91,6 +93,9 @@ ssize_t smu_v13_0_12_get_xcp_metrics(struct smu_context *smu, void *smu_metrics); int smu_v13_0_12_tables_init(struct smu_context *smu); void smu_v13_0_12_tables_fini(struct smu_context *smu); +int smu_v13_0_12_get_npm_data(struct smu_context *smu, + enum amd_pp_sensors sensor, + uint32_t *value); extern const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[]; extern const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[]; extern const struct smu_temp_funcs smu_v13_0_12_temp_funcs; From 80b088180abb15ae4abae9f2842e856e4fee6740 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Mon, 15 Sep 2025 20:28:49 +0800 Subject: [PATCH 2025/2653] drm/amd/pm: Enable npm metrics data Enable npm metrics data for smu_v13_0_12 v3: Add node id check for setting NPM_CAPS (Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Reviewed-by: Yang Wang --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index b879a7a700152..c74db0ec2b450 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -362,9 +362,11 @@ static void smu_v13_0_12_init_caps(struct smu_context *smu) } if (fw_ver >= 0x04560700) { - if (!amdgpu_sriov_vf(smu->adev)) + if (fw_ver >= 0x04560900) { smu_v13_0_6_cap_set(smu, SMU_CAP(TEMP_METRICS)); - else if (fw_ver >= 0x04560900) + if (smu->adev->gmc.xgmi.physical_node_id == 0) + smu_v13_0_6_cap_set(smu, SMU_CAP(NPM_METRICS)); + } else if (!amdgpu_sriov_vf(smu->adev)) smu_v13_0_6_cap_set(smu, SMU_CAP(TEMP_METRICS)); } else { smu_v13_0_12_tables_fini(smu); From 2be72225aebfad5fe2407f6ced88c419cec99f9d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 20 Aug 2025 16:04:18 -0400 Subject: [PATCH 2026/2653] drm/amdgpu: remove non-DC DCE 11 code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DC has been the default for ~8 years now and supports many things that the non-DC code does not (audio, DP MST, etc.). No DCE 11.x IPs ever supported analog encoders so that is not an issue. Finally drop this code. Acked-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/Makefile | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 8 - drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 3833 ---------------------- drivers/gpu/drm/amd/amdgpu/dce_v11_0.h | 32 - drivers/gpu/drm/amd/amdgpu/vi.c | 7 - 5 files changed, 3881 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c delete mode 100644 drivers/gpu/drm/amd/amdgpu/dce_v11_0.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 7fe67d0e1cd60..273daa144480f 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -138,7 +138,6 @@ amdgpu-y += \ # add DCE block amdgpu-y += \ dce_v10_0.o \ - dce_v11_0.o \ amdgpu_vkms.o # add GFX block diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 24c1f8575298f..9beb0de8ce3d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -14,7 +14,6 @@ #include "dce_v8_0.h" #endif #include "dce_v10_0.h" -#include "dce_v11_0.h" #include "ivsrcid/ivsrcid_vislands30.h" #include "amdgpu_vkms.h" #include "amdgpu_display.h" @@ -711,13 +710,6 @@ static int amdgpu_vkms_hw_init(struct amdgpu_ip_block *ip_block) case CHIP_TONGA: dce_v10_0_disable_dce(adev); break; - case CHIP_CARRIZO: - case CHIP_STONEY: - case CHIP_POLARIS10: - case CHIP_POLARIS11: - case CHIP_VEGAM: - dce_v11_0_disable_dce(adev); - break; case CHIP_TOPAZ: #ifdef CONFIG_DRM_AMDGPU_SI case CHIP_HAINAN: diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c deleted file mode 100644 index 7a02e1b5d29ec..0000000000000 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ /dev/null @@ -1,3833 +0,0 @@ -/* - * Copyright 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include -#include -#include -#include -#include - -#include "amdgpu.h" -#include "amdgpu_pm.h" -#include "amdgpu_i2c.h" -#include "vid.h" -#include "atom.h" -#include "amdgpu_atombios.h" -#include "atombios_crtc.h" -#include "atombios_encoders.h" -#include "amdgpu_pll.h" -#include "amdgpu_connectors.h" -#include "amdgpu_display.h" -#include "dce_v11_0.h" - -#include "dce/dce_11_0_d.h" -#include "dce/dce_11_0_sh_mask.h" -#include "dce/dce_11_0_enum.h" -#include "oss/oss_3_0_d.h" -#include "oss/oss_3_0_sh_mask.h" -#include "gmc/gmc_8_1_d.h" -#include "gmc/gmc_8_1_sh_mask.h" - -#include "ivsrcid/ivsrcid_vislands30.h" - -static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev); -static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev); -static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, int hpd); - -static const u32 crtc_offsets[] = -{ - CRTC0_REGISTER_OFFSET, - CRTC1_REGISTER_OFFSET, - CRTC2_REGISTER_OFFSET, - CRTC3_REGISTER_OFFSET, - CRTC4_REGISTER_OFFSET, - CRTC5_REGISTER_OFFSET, - CRTC6_REGISTER_OFFSET -}; - -static const u32 hpd_offsets[] = -{ - HPD0_REGISTER_OFFSET, - HPD1_REGISTER_OFFSET, - HPD2_REGISTER_OFFSET, - HPD3_REGISTER_OFFSET, - HPD4_REGISTER_OFFSET, - HPD5_REGISTER_OFFSET -}; - -static const uint32_t dig_offsets[] = { - DIG0_REGISTER_OFFSET, - DIG1_REGISTER_OFFSET, - DIG2_REGISTER_OFFSET, - DIG3_REGISTER_OFFSET, - DIG4_REGISTER_OFFSET, - DIG5_REGISTER_OFFSET, - DIG6_REGISTER_OFFSET, - DIG7_REGISTER_OFFSET, - DIG8_REGISTER_OFFSET -}; - -static const struct { - uint32_t reg; - uint32_t vblank; - uint32_t vline; - uint32_t hpd; - -} interrupt_status_offsets[] = { { - .reg = mmDISP_INTERRUPT_STATUS, - .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, - .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, - .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK -}, { - .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, - .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, - .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, - .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK -}, { - .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, - .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, - .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, - .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK -}, { - .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, - .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, - .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, - .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK -}, { - .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, - .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, - .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, - .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK -}, { - .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, - .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, - .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, - .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK -} }; - -static const u32 cz_golden_settings_a11[] = -{ - mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, - mmFBC_MISC, 0x1f311fff, 0x14300000, -}; - -static const u32 cz_mgcg_cgcg_init[] = -{ - mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, - mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, -}; - -static const u32 stoney_golden_settings_a11[] = -{ - mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, - mmFBC_MISC, 0x1f311fff, 0x14302000, -}; - -static const u32 polaris11_golden_settings_a11[] = -{ - mmDCI_CLK_CNTL, 0x00000080, 0x00000000, - mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, - mmFBC_DEBUG1, 0xffffffff, 0x00000008, - mmFBC_MISC, 0x9f313fff, 0x14302008, - mmHDMI_CONTROL, 0x313f031f, 0x00000011, -}; - -static const u32 polaris10_golden_settings_a11[] = -{ - mmDCI_CLK_CNTL, 0x00000080, 0x00000000, - mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, - mmFBC_MISC, 0x9f313fff, 0x14302008, - mmHDMI_CONTROL, 0x313f031f, 0x00000011, -}; - -static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) -{ - switch (adev->asic_type) { - case CHIP_CARRIZO: - amdgpu_device_program_register_sequence(adev, - cz_mgcg_cgcg_init, - ARRAY_SIZE(cz_mgcg_cgcg_init)); - amdgpu_device_program_register_sequence(adev, - cz_golden_settings_a11, - ARRAY_SIZE(cz_golden_settings_a11)); - break; - case CHIP_STONEY: - amdgpu_device_program_register_sequence(adev, - stoney_golden_settings_a11, - ARRAY_SIZE(stoney_golden_settings_a11)); - break; - case CHIP_POLARIS11: - case CHIP_POLARIS12: - amdgpu_device_program_register_sequence(adev, - polaris11_golden_settings_a11, - ARRAY_SIZE(polaris11_golden_settings_a11)); - break; - case CHIP_POLARIS10: - case CHIP_VEGAM: - amdgpu_device_program_register_sequence(adev, - polaris10_golden_settings_a11, - ARRAY_SIZE(polaris10_golden_settings_a11)); - break; - default: - break; - } -} - -static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev, - u32 block_offset, u32 reg) -{ - unsigned long flags; - u32 r; - - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); - WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); - r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); - - return r; -} - -static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev, - u32 block_offset, u32 reg, u32 v) -{ - unsigned long flags; - - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); - WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); - WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); -} - -static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) -{ - if (crtc < 0 || crtc >= adev->mode_info.num_crtc) - return 0; - else - return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); -} - -static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev) -{ - unsigned i; - - /* Enable pflip interrupts */ - for (i = 0; i < adev->mode_info.num_crtc; i++) - amdgpu_irq_get(adev, &adev->pageflip_irq, i); -} - -static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev) -{ - unsigned i; - - /* Disable pflip interrupts */ - for (i = 0; i < adev->mode_info.num_crtc; i++) - amdgpu_irq_put(adev, &adev->pageflip_irq, i); -} - -/** - * dce_v11_0_page_flip - pageflip callback. - * - * @adev: amdgpu_device pointer - * @crtc_id: crtc to cleanup pageflip on - * @crtc_base: new address of the crtc (GPU MC address) - * @async: asynchronous flip - * - * Triggers the actual pageflip by updating the primary - * surface base address. - */ -static void dce_v11_0_page_flip(struct amdgpu_device *adev, - int crtc_id, u64 crtc_base, bool async) -{ - struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; - struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; - u32 tmp; - - /* flip immediate for async, default is vsync */ - tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); - tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, - GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0); - WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); - /* update pitch */ - WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, - fb->pitches[0] / fb->format->cpp[0]); - /* update the scanout addresses */ - WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, - upper_32_bits(crtc_base)); - /* writing to the low address triggers the update */ - WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, - lower_32_bits(crtc_base)); - /* post the write */ - RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); -} - -static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, - u32 *vbl, u32 *position) -{ - if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) - return -EINVAL; - - *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); - *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); - - return 0; -} - -/** - * dce_v11_0_hpd_sense - hpd sense callback. - * - * @adev: amdgpu_device pointer - * @hpd: hpd (hotplug detect) pin - * - * Checks if a digital monitor is connected (evergreen+). - * Returns true if connected, false if not connected. - */ -static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev, - enum amdgpu_hpd_id hpd) -{ - bool connected = false; - - if (hpd >= adev->mode_info.num_hpd) - return connected; - - if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & - DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) - connected = true; - - return connected; -} - -/** - * dce_v11_0_hpd_set_polarity - hpd set polarity callback. - * - * @adev: amdgpu_device pointer - * @hpd: hpd (hotplug detect) pin - * - * Set the polarity of the hpd pin (evergreen+). - */ -static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev, - enum amdgpu_hpd_id hpd) -{ - u32 tmp; - bool connected = dce_v11_0_hpd_sense(adev, hpd); - - if (hpd >= adev->mode_info.num_hpd) - return; - - tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); - if (connected) - tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); - else - tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); - WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); -} - -/** - * dce_v11_0_hpd_init - hpd setup callback. - * - * @adev: amdgpu_device pointer - * - * Setup the hpd pins used by the card (evergreen+). - * Enable the pin, set the polarity, and enable the hpd interrupts. - */ -static void dce_v11_0_hpd_init(struct amdgpu_device *adev) -{ - struct drm_device *dev = adev_to_drm(adev); - struct drm_connector *connector; - struct drm_connector_list_iter iter; - u32 tmp; - - drm_connector_list_iter_begin(dev, &iter); - drm_for_each_connector_iter(connector, &iter) { - struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - - if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) - continue; - - if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || - connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { - /* don't try to enable hpd on eDP or LVDS avoid breaking the - * aux dp channel on imac and help (but not completely fix) - * https://bugzilla.redhat.com/show_bug.cgi?id=726143 - * also avoid interrupt storms during dpms. - */ - tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); - tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); - WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); - continue; - } - - tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); - tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); - WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); - - tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); - tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, - DC_HPD_CONNECT_INT_DELAY, - AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); - tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, - DC_HPD_DISCONNECT_INT_DELAY, - AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); - WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); - - dce_v11_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); - dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); - amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); - } - drm_connector_list_iter_end(&iter); -} - -/** - * dce_v11_0_hpd_fini - hpd tear down callback. - * - * @adev: amdgpu_device pointer - * - * Tear down the hpd pins used by the card (evergreen+). - * Disable the hpd interrupts. - */ -static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) -{ - struct drm_device *dev = adev_to_drm(adev); - struct drm_connector *connector; - struct drm_connector_list_iter iter; - u32 tmp; - - drm_connector_list_iter_begin(dev, &iter); - drm_for_each_connector_iter(connector, &iter) { - struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - - if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) - continue; - - tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); - tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); - WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); - - amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); - } - drm_connector_list_iter_end(&iter); -} - -static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev) -{ - return mmDC_GPIO_HPD_A; -} - -static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev) -{ - u32 crtc_hung = 0; - u32 crtc_status[6]; - u32 i, j, tmp; - - for (i = 0; i < adev->mode_info.num_crtc; i++) { - tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); - if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { - crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); - crtc_hung |= (1 << i); - } - } - - for (j = 0; j < 10; j++) { - for (i = 0; i < adev->mode_info.num_crtc; i++) { - if (crtc_hung & (1 << i)) { - tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); - if (tmp != crtc_status[i]) - crtc_hung &= ~(1 << i); - } - } - if (crtc_hung == 0) - return false; - udelay(100); - } - - return true; -} - -static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev, - bool render) -{ - u32 tmp; - - /* Lockout access through VGA aperture*/ - tmp = RREG32(mmVGA_HDP_CONTROL); - if (render) - tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); - else - tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); - WREG32(mmVGA_HDP_CONTROL, tmp); - - /* disable VGA render */ - tmp = RREG32(mmVGA_RENDER_CONTROL); - if (render) - tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); - else - tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); - WREG32(mmVGA_RENDER_CONTROL, tmp); -} - -static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev) -{ - int num_crtc = 0; - - switch (adev->asic_type) { - case CHIP_CARRIZO: - num_crtc = 3; - break; - case CHIP_STONEY: - num_crtc = 2; - break; - case CHIP_POLARIS10: - case CHIP_VEGAM: - num_crtc = 6; - break; - case CHIP_POLARIS11: - case CHIP_POLARIS12: - num_crtc = 5; - break; - default: - num_crtc = 0; - } - return num_crtc; -} - -void dce_v11_0_disable_dce(struct amdgpu_device *adev) -{ - /*Disable VGA render and enabled crtc, if has DCE engine*/ - if (amdgpu_atombios_has_dce_engine_info(adev)) { - u32 tmp; - int crtc_enabled, i; - - dce_v11_0_set_vga_render_state(adev, false); - - /*Disable crtc*/ - for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) { - crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), - CRTC_CONTROL, CRTC_MASTER_EN); - if (crtc_enabled) { - WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); - tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); - tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); - WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); - WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); - } - } - } -} - -static void dce_v11_0_program_fmt(struct drm_encoder *encoder) -{ - struct drm_device *dev = encoder->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); - struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); - int bpc = 0; - u32 tmp = 0; - enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; - - if (connector) { - struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - bpc = amdgpu_connector_get_monitor_bpc(connector); - dither = amdgpu_connector->dither; - } - - /* LVDS/eDP FMT is set up by atom */ - if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) - return; - - /* not needed for analog */ - if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || - (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) - return; - - if (bpc == 0) - return; - - switch (bpc) { - case 6: - if (dither == AMDGPU_FMT_DITHER_ENABLE) { - /* XXX sort out optimal dither settings */ - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); - } else { - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); - } - break; - case 8: - if (dither == AMDGPU_FMT_DITHER_ENABLE) { - /* XXX sort out optimal dither settings */ - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); - } else { - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); - } - break; - case 10: - if (dither == AMDGPU_FMT_DITHER_ENABLE) { - /* XXX sort out optimal dither settings */ - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); - } else { - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); - tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); - } - break; - default: - /* not needed */ - break; - } - - WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); -} - - -/* display watermark setup */ -/** - * dce_v11_0_line_buffer_adjust - Set up the line buffer - * - * @adev: amdgpu_device pointer - * @amdgpu_crtc: the selected display controller - * @mode: the current display mode on the selected display - * controller - * - * Setup up the line buffer allocation for - * the selected display controller (CIK). - * Returns the line buffer size in pixels. - */ -static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev, - struct amdgpu_crtc *amdgpu_crtc, - struct drm_display_mode *mode) -{ - u32 tmp, buffer_alloc, i, mem_cfg; - u32 pipe_offset = amdgpu_crtc->crtc_id; - /* - * Line Buffer Setup - * There are 6 line buffers, one for each display controllers. - * There are 3 partitions per LB. Select the number of partitions - * to enable based on the display width. For display widths larger - * than 4096, you need use to use 2 display controllers and combine - * them using the stereo blender. - */ - if (amdgpu_crtc->base.enabled && mode) { - if (mode->crtc_hdisplay < 1920) { - mem_cfg = 1; - buffer_alloc = 2; - } else if (mode->crtc_hdisplay < 2560) { - mem_cfg = 2; - buffer_alloc = 2; - } else if (mode->crtc_hdisplay < 4096) { - mem_cfg = 0; - buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; - } else { - DRM_DEBUG_KMS("Mode too big for LB!\n"); - mem_cfg = 0; - buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; - } - } else { - mem_cfg = 1; - buffer_alloc = 0; - } - - tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); - tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); - WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); - - tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); - tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); - WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); - - for (i = 0; i < adev->usec_timeout; i++) { - tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); - if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) - break; - udelay(1); - } - - if (amdgpu_crtc->base.enabled && mode) { - switch (mem_cfg) { - case 0: - default: - return 4096 * 2; - case 1: - return 1920 * 2; - case 2: - return 2560 * 2; - } - } - - /* controller not enabled, so no lb used */ - return 0; -} - -/** - * cik_get_number_of_dram_channels - get the number of dram channels - * - * @adev: amdgpu_device pointer - * - * Look up the number of video ram channels (CIK). - * Used for display watermark bandwidth calculations - * Returns the number of dram channels - */ -static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) -{ - u32 tmp = RREG32(mmMC_SHARED_CHMAP); - - switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { - case 0: - default: - return 1; - case 1: - return 2; - case 2: - return 4; - case 3: - return 8; - case 4: - return 3; - case 5: - return 6; - case 6: - return 10; - case 7: - return 12; - case 8: - return 16; - } -} - -struct dce10_wm_params { - u32 dram_channels; /* number of dram channels */ - u32 yclk; /* bandwidth per dram data pin in kHz */ - u32 sclk; /* engine clock in kHz */ - u32 disp_clk; /* display clock in kHz */ - u32 src_width; /* viewport width */ - u32 active_time; /* active display time in ns */ - u32 blank_time; /* blank time in ns */ - bool interlaced; /* mode is interlaced */ - fixed20_12 vsc; /* vertical scale ratio */ - u32 num_heads; /* number of active crtcs */ - u32 bytes_per_pixel; /* bytes per pixel display + overlay */ - u32 lb_size; /* line buffer allocated to pipe */ - u32 vtaps; /* vertical scaler taps */ -}; - -/** - * dce_v11_0_dram_bandwidth - get the dram bandwidth - * - * @wm: watermark calculation data - * - * Calculate the raw dram bandwidth (CIK). - * Used for display watermark bandwidth calculations - * Returns the dram bandwidth in MBytes/s - */ -static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm) -{ - /* Calculate raw DRAM Bandwidth */ - fixed20_12 dram_efficiency; /* 0.7 */ - fixed20_12 yclk, dram_channels, bandwidth; - fixed20_12 a; - - a.full = dfixed_const(1000); - yclk.full = dfixed_const(wm->yclk); - yclk.full = dfixed_div(yclk, a); - dram_channels.full = dfixed_const(wm->dram_channels * 4); - a.full = dfixed_const(10); - dram_efficiency.full = dfixed_const(7); - dram_efficiency.full = dfixed_div(dram_efficiency, a); - bandwidth.full = dfixed_mul(dram_channels, yclk); - bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); - - return dfixed_trunc(bandwidth); -} - -/** - * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display - * - * @wm: watermark calculation data - * - * Calculate the dram bandwidth used for display (CIK). - * Used for display watermark bandwidth calculations - * Returns the dram bandwidth for display in MBytes/s - */ -static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) -{ - /* Calculate DRAM Bandwidth and the part allocated to display. */ - fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ - fixed20_12 yclk, dram_channels, bandwidth; - fixed20_12 a; - - a.full = dfixed_const(1000); - yclk.full = dfixed_const(wm->yclk); - yclk.full = dfixed_div(yclk, a); - dram_channels.full = dfixed_const(wm->dram_channels * 4); - a.full = dfixed_const(10); - disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ - disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); - bandwidth.full = dfixed_mul(dram_channels, yclk); - bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); - - return dfixed_trunc(bandwidth); -} - -/** - * dce_v11_0_data_return_bandwidth - get the data return bandwidth - * - * @wm: watermark calculation data - * - * Calculate the data return bandwidth used for display (CIK). - * Used for display watermark bandwidth calculations - * Returns the data return bandwidth in MBytes/s - */ -static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm) -{ - /* Calculate the display Data return Bandwidth */ - fixed20_12 return_efficiency; /* 0.8 */ - fixed20_12 sclk, bandwidth; - fixed20_12 a; - - a.full = dfixed_const(1000); - sclk.full = dfixed_const(wm->sclk); - sclk.full = dfixed_div(sclk, a); - a.full = dfixed_const(10); - return_efficiency.full = dfixed_const(8); - return_efficiency.full = dfixed_div(return_efficiency, a); - a.full = dfixed_const(32); - bandwidth.full = dfixed_mul(a, sclk); - bandwidth.full = dfixed_mul(bandwidth, return_efficiency); - - return dfixed_trunc(bandwidth); -} - -/** - * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth - * - * @wm: watermark calculation data - * - * Calculate the dmif bandwidth used for display (CIK). - * Used for display watermark bandwidth calculations - * Returns the dmif bandwidth in MBytes/s - */ -static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm) -{ - /* Calculate the DMIF Request Bandwidth */ - fixed20_12 disp_clk_request_efficiency; /* 0.8 */ - fixed20_12 disp_clk, bandwidth; - fixed20_12 a, b; - - a.full = dfixed_const(1000); - disp_clk.full = dfixed_const(wm->disp_clk); - disp_clk.full = dfixed_div(disp_clk, a); - a.full = dfixed_const(32); - b.full = dfixed_mul(a, disp_clk); - - a.full = dfixed_const(10); - disp_clk_request_efficiency.full = dfixed_const(8); - disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); - - bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); - - return dfixed_trunc(bandwidth); -} - -/** - * dce_v11_0_available_bandwidth - get the min available bandwidth - * - * @wm: watermark calculation data - * - * Calculate the min available bandwidth used for display (CIK). - * Used for display watermark bandwidth calculations - * Returns the min available bandwidth in MBytes/s - */ -static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm) -{ - /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ - u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm); - u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm); - u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm); - - return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); -} - -/** - * dce_v11_0_average_bandwidth - get the average available bandwidth - * - * @wm: watermark calculation data - * - * Calculate the average available bandwidth used for display (CIK). - * Used for display watermark bandwidth calculations - * Returns the average available bandwidth in MBytes/s - */ -static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm) -{ - /* Calculate the display mode Average Bandwidth - * DisplayMode should contain the source and destination dimensions, - * timing, etc. - */ - fixed20_12 bpp; - fixed20_12 line_time; - fixed20_12 src_width; - fixed20_12 bandwidth; - fixed20_12 a; - - a.full = dfixed_const(1000); - line_time.full = dfixed_const(wm->active_time + wm->blank_time); - line_time.full = dfixed_div(line_time, a); - bpp.full = dfixed_const(wm->bytes_per_pixel); - src_width.full = dfixed_const(wm->src_width); - bandwidth.full = dfixed_mul(src_width, bpp); - bandwidth.full = dfixed_mul(bandwidth, wm->vsc); - bandwidth.full = dfixed_div(bandwidth, line_time); - - return dfixed_trunc(bandwidth); -} - -/** - * dce_v11_0_latency_watermark - get the latency watermark - * - * @wm: watermark calculation data - * - * Calculate the latency watermark (CIK). - * Used for display watermark bandwidth calculations - * Returns the latency watermark in ns - */ -static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm) -{ - /* First calculate the latency in ns */ - u32 mc_latency = 2000; /* 2000 ns. */ - u32 available_bandwidth = dce_v11_0_available_bandwidth(wm); - u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; - u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; - u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ - u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + - (wm->num_heads * cursor_line_pair_return_time); - u32 latency = mc_latency + other_heads_data_return_time + dc_latency; - u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; - u32 tmp, dmif_size = 12288; - fixed20_12 a, b, c; - - if (wm->num_heads == 0) - return 0; - - a.full = dfixed_const(2); - b.full = dfixed_const(1); - if ((wm->vsc.full > a.full) || - ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || - (wm->vtaps >= 5) || - ((wm->vsc.full >= a.full) && wm->interlaced)) - max_src_lines_per_dst_line = 4; - else - max_src_lines_per_dst_line = 2; - - a.full = dfixed_const(available_bandwidth); - b.full = dfixed_const(wm->num_heads); - a.full = dfixed_div(a, b); - tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); - tmp = min(dfixed_trunc(a), tmp); - - lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); - - a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); - b.full = dfixed_const(1000); - c.full = dfixed_const(lb_fill_bw); - b.full = dfixed_div(c, b); - a.full = dfixed_div(a, b); - line_fill_time = dfixed_trunc(a); - - if (line_fill_time < wm->active_time) - return latency; - else - return latency + (line_fill_time - wm->active_time); - -} - -/** - * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check - * average and available dram bandwidth - * - * @wm: watermark calculation data - * - * Check if the display average bandwidth fits in the display - * dram bandwidth (CIK). - * Used for display watermark bandwidth calculations - * Returns true if the display fits, false if not. - */ -static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) -{ - if (dce_v11_0_average_bandwidth(wm) <= - (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) - return true; - else - return false; -} - -/** - * dce_v11_0_average_bandwidth_vs_available_bandwidth - check - * average and available bandwidth - * - * @wm: watermark calculation data - * - * Check if the display average bandwidth fits in the display - * available bandwidth (CIK). - * Used for display watermark bandwidth calculations - * Returns true if the display fits, false if not. - */ -static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) -{ - if (dce_v11_0_average_bandwidth(wm) <= - (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) - return true; - else - return false; -} - -/** - * dce_v11_0_check_latency_hiding - check latency hiding - * - * @wm: watermark calculation data - * - * Check latency hiding (CIK). - * Used for display watermark bandwidth calculations - * Returns true if the display fits, false if not. - */ -static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm) -{ - u32 lb_partitions = wm->lb_size / wm->src_width; - u32 line_time = wm->active_time + wm->blank_time; - u32 latency_tolerant_lines; - u32 latency_hiding; - fixed20_12 a; - - a.full = dfixed_const(1); - if (wm->vsc.full > a.full) - latency_tolerant_lines = 1; - else { - if (lb_partitions <= (wm->vtaps + 1)) - latency_tolerant_lines = 1; - else - latency_tolerant_lines = 2; - } - - latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); - - if (dce_v11_0_latency_watermark(wm) <= latency_hiding) - return true; - else - return false; -} - -/** - * dce_v11_0_program_watermarks - program display watermarks - * - * @adev: amdgpu_device pointer - * @amdgpu_crtc: the selected display controller - * @lb_size: line buffer size - * @num_heads: number of display controllers in use - * - * Calculate and program the display watermarks for the - * selected display controller (CIK). - */ -static void dce_v11_0_program_watermarks(struct amdgpu_device *adev, - struct amdgpu_crtc *amdgpu_crtc, - u32 lb_size, u32 num_heads) -{ - struct drm_display_mode *mode = &amdgpu_crtc->base.mode; - struct dce10_wm_params wm_low, wm_high; - u32 active_time; - u32 line_time = 0; - u32 latency_watermark_a = 0, latency_watermark_b = 0; - u32 tmp, wm_mask, lb_vblank_lead_lines = 0; - - if (amdgpu_crtc->base.enabled && num_heads && mode) { - active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, - (u32)mode->clock); - line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, - (u32)mode->clock); - line_time = min_t(u32, line_time, 65535); - - /* watermark for high clocks */ - if (adev->pm.dpm_enabled) { - wm_high.yclk = - amdgpu_dpm_get_mclk(adev, false) * 10; - wm_high.sclk = - amdgpu_dpm_get_sclk(adev, false) * 10; - } else { - wm_high.yclk = adev->pm.current_mclk * 10; - wm_high.sclk = adev->pm.current_sclk * 10; - } - - wm_high.disp_clk = mode->clock; - wm_high.src_width = mode->crtc_hdisplay; - wm_high.active_time = active_time; - wm_high.blank_time = line_time - wm_high.active_time; - wm_high.interlaced = false; - if (mode->flags & DRM_MODE_FLAG_INTERLACE) - wm_high.interlaced = true; - wm_high.vsc = amdgpu_crtc->vsc; - wm_high.vtaps = 1; - if (amdgpu_crtc->rmx_type != RMX_OFF) - wm_high.vtaps = 2; - wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ - wm_high.lb_size = lb_size; - wm_high.dram_channels = cik_get_number_of_dram_channels(adev); - wm_high.num_heads = num_heads; - - /* set for high clocks */ - latency_watermark_a = min_t(u32, dce_v11_0_latency_watermark(&wm_high), 65535); - - /* possibly force display priority to high */ - /* should really do this at mode validation time... */ - if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || - !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) || - !dce_v11_0_check_latency_hiding(&wm_high) || - (adev->mode_info.disp_priority == 2)) { - DRM_DEBUG_KMS("force priority to high\n"); - } - - /* watermark for low clocks */ - if (adev->pm.dpm_enabled) { - wm_low.yclk = - amdgpu_dpm_get_mclk(adev, true) * 10; - wm_low.sclk = - amdgpu_dpm_get_sclk(adev, true) * 10; - } else { - wm_low.yclk = adev->pm.current_mclk * 10; - wm_low.sclk = adev->pm.current_sclk * 10; - } - - wm_low.disp_clk = mode->clock; - wm_low.src_width = mode->crtc_hdisplay; - wm_low.active_time = active_time; - wm_low.blank_time = line_time - wm_low.active_time; - wm_low.interlaced = false; - if (mode->flags & DRM_MODE_FLAG_INTERLACE) - wm_low.interlaced = true; - wm_low.vsc = amdgpu_crtc->vsc; - wm_low.vtaps = 1; - if (amdgpu_crtc->rmx_type != RMX_OFF) - wm_low.vtaps = 2; - wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ - wm_low.lb_size = lb_size; - wm_low.dram_channels = cik_get_number_of_dram_channels(adev); - wm_low.num_heads = num_heads; - - /* set for low clocks */ - latency_watermark_b = min_t(u32, dce_v11_0_latency_watermark(&wm_low), 65535); - - /* possibly force display priority to high */ - /* should really do this at mode validation time... */ - if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || - !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) || - !dce_v11_0_check_latency_hiding(&wm_low) || - (adev->mode_info.disp_priority == 2)) { - DRM_DEBUG_KMS("force priority to high\n"); - } - lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); - } - - /* select wm A */ - wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); - tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); - WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); - tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); - tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); - tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); - WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); - /* select wm B */ - tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); - WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); - tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); - tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); - tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); - WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); - /* restore original selection */ - WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); - - /* save values for DPM */ - amdgpu_crtc->line_time = line_time; - - /* Save number of lines the linebuffer leads before the scanout */ - amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; -} - -/** - * dce_v11_0_bandwidth_update - program display watermarks - * - * @adev: amdgpu_device pointer - * - * Calculate and program the display watermarks and line - * buffer allocation (CIK). - */ -static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev) -{ - struct drm_display_mode *mode = NULL; - u32 num_heads = 0, lb_size; - int i; - - amdgpu_display_update_priority(adev); - - for (i = 0; i < adev->mode_info.num_crtc; i++) { - if (adev->mode_info.crtcs[i]->base.enabled) - num_heads++; - } - for (i = 0; i < adev->mode_info.num_crtc; i++) { - mode = &adev->mode_info.crtcs[i]->base.mode; - lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); - dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], - lb_size, num_heads); - } -} - -static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev) -{ - int i; - u32 offset, tmp; - - for (i = 0; i < adev->mode_info.audio.num_pins; i++) { - offset = adev->mode_info.audio.pin[i].offset; - tmp = RREG32_AUDIO_ENDPT(offset, - ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); - if (((tmp & - AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> - AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) - adev->mode_info.audio.pin[i].connected = false; - else - adev->mode_info.audio.pin[i].connected = true; - } -} - -static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev) -{ - int i; - - dce_v11_0_audio_get_connected_pins(adev); - - for (i = 0; i < adev->mode_info.audio.num_pins; i++) { - if (adev->mode_info.audio.pin[i].connected) - return &adev->mode_info.audio.pin[i]; - } - DRM_ERROR("No connected audio pins found!\n"); - return NULL; -} - -static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder) -{ - struct amdgpu_device *adev = drm_to_adev(encoder->dev); - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; - u32 tmp; - - if (!dig || !dig->afmt || !dig->afmt->pin) - return; - - tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); - tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); - WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); -} - -static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, - struct drm_display_mode *mode) -{ - struct drm_device *dev = encoder->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; - struct drm_connector *connector; - struct drm_connector_list_iter iter; - struct amdgpu_connector *amdgpu_connector = NULL; - u32 tmp; - int interlace = 0; - - if (!dig || !dig->afmt || !dig->afmt->pin) - return; - - drm_connector_list_iter_begin(dev, &iter); - drm_for_each_connector_iter(connector, &iter) { - if (connector->encoder == encoder) { - amdgpu_connector = to_amdgpu_connector(connector); - break; - } - } - drm_connector_list_iter_end(&iter); - - if (!amdgpu_connector) { - DRM_ERROR("Couldn't find encoder's connector\n"); - return; - } - - if (mode->flags & DRM_MODE_FLAG_INTERLACE) - interlace = 1; - if (connector->latency_present[interlace]) { - tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, - VIDEO_LIPSYNC, connector->video_latency[interlace]); - tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, - AUDIO_LIPSYNC, connector->audio_latency[interlace]); - } else { - tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, - VIDEO_LIPSYNC, 0); - tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, - AUDIO_LIPSYNC, 0); - } - WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, - ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); -} - -static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder) -{ - struct drm_device *dev = encoder->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; - struct drm_connector *connector; - struct drm_connector_list_iter iter; - struct amdgpu_connector *amdgpu_connector = NULL; - u32 tmp; - u8 *sadb = NULL; - int sad_count; - - if (!dig || !dig->afmt || !dig->afmt->pin) - return; - - drm_connector_list_iter_begin(dev, &iter); - drm_for_each_connector_iter(connector, &iter) { - if (connector->encoder == encoder) { - amdgpu_connector = to_amdgpu_connector(connector); - break; - } - } - drm_connector_list_iter_end(&iter); - - if (!amdgpu_connector) { - DRM_ERROR("Couldn't find encoder's connector\n"); - return; - } - - sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); - if (sad_count < 0) { - DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); - sad_count = 0; - } - - /* program the speaker allocation */ - tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, - ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); - tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, - DP_CONNECTION, 0); - /* set HDMI mode */ - tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, - HDMI_CONNECTION, 1); - if (sad_count) - tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, - SPEAKER_ALLOCATION, sadb[0]); - else - tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, - SPEAKER_ALLOCATION, 5); /* stereo */ - WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, - ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); - - kfree(sadb); -} - -static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) -{ - struct drm_device *dev = encoder->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; - struct drm_connector *connector; - struct drm_connector_list_iter iter; - struct amdgpu_connector *amdgpu_connector = NULL; - struct cea_sad *sads; - int i, sad_count; - - static const u16 eld_reg_to_type[][2] = { - { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, - { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, - { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, - { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, - { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, - { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, - { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, - { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, - { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, - { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, - { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, - { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, - }; - - if (!dig || !dig->afmt || !dig->afmt->pin) - return; - - drm_connector_list_iter_begin(dev, &iter); - drm_for_each_connector_iter(connector, &iter) { - if (connector->encoder == encoder) { - amdgpu_connector = to_amdgpu_connector(connector); - break; - } - } - drm_connector_list_iter_end(&iter); - - if (!amdgpu_connector) { - DRM_ERROR("Couldn't find encoder's connector\n"); - return; - } - - sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); - if (sad_count < 0) - DRM_ERROR("Couldn't read SADs: %d\n", sad_count); - if (sad_count <= 0) - return; - BUG_ON(!sads); - - for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { - u32 tmp = 0; - u8 stereo_freqs = 0; - int max_channels = -1; - int j; - - for (j = 0; j < sad_count; j++) { - struct cea_sad *sad = &sads[j]; - - if (sad->format == eld_reg_to_type[i][1]) { - if (sad->channels > max_channels) { - tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, - MAX_CHANNELS, sad->channels); - tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, - DESCRIPTOR_BYTE_2, sad->byte2); - tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, - SUPPORTED_FREQUENCIES, sad->freq); - max_channels = sad->channels; - } - - if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) - stereo_freqs |= sad->freq; - else - break; - } - } - - tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, - SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); - WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); - } - - kfree(sads); -} - -static void dce_v11_0_audio_enable(struct amdgpu_device *adev, - struct amdgpu_audio_pin *pin, - bool enable) -{ - if (!pin) - return; - - WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, - enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); -} - -static const u32 pin_offsets[] = -{ - AUD0_REGISTER_OFFSET, - AUD1_REGISTER_OFFSET, - AUD2_REGISTER_OFFSET, - AUD3_REGISTER_OFFSET, - AUD4_REGISTER_OFFSET, - AUD5_REGISTER_OFFSET, - AUD6_REGISTER_OFFSET, - AUD7_REGISTER_OFFSET, -}; - -static int dce_v11_0_audio_init(struct amdgpu_device *adev) -{ - int i; - - if (!amdgpu_audio) - return 0; - - adev->mode_info.audio.enabled = true; - - switch (adev->asic_type) { - case CHIP_CARRIZO: - case CHIP_STONEY: - adev->mode_info.audio.num_pins = 7; - break; - case CHIP_POLARIS10: - case CHIP_VEGAM: - adev->mode_info.audio.num_pins = 8; - break; - case CHIP_POLARIS11: - case CHIP_POLARIS12: - adev->mode_info.audio.num_pins = 6; - break; - default: - return -EINVAL; - } - - for (i = 0; i < adev->mode_info.audio.num_pins; i++) { - adev->mode_info.audio.pin[i].channels = -1; - adev->mode_info.audio.pin[i].rate = -1; - adev->mode_info.audio.pin[i].bits_per_sample = -1; - adev->mode_info.audio.pin[i].status_bits = 0; - adev->mode_info.audio.pin[i].category_code = 0; - adev->mode_info.audio.pin[i].connected = false; - adev->mode_info.audio.pin[i].offset = pin_offsets[i]; - adev->mode_info.audio.pin[i].id = i; - /* disable audio. it will be set up later */ - /* XXX remove once we switch to ip funcs */ - dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); - } - - return 0; -} - -static void dce_v11_0_audio_fini(struct amdgpu_device *adev) -{ - if (!amdgpu_audio) - return; - - if (!adev->mode_info.audio.enabled) - return; - - adev->mode_info.audio.enabled = false; -} - -/* - * update the N and CTS parameters for a given pixel clock rate - */ -static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) -{ - struct drm_device *dev = encoder->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; - u32 tmp; - - tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); - tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); - WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); - tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); - tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); - WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); - - tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); - tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); - WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); - tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); - tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); - WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); - - tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); - tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); - WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); - tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); - tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); - WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); - -} - -/* - * build a HDMI Video Info Frame - */ -static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, - void *buffer, size_t size) -{ - struct drm_device *dev = encoder->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; - uint8_t *frame = buffer + 3; - uint8_t *header = buffer; - - WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, - frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); - WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, - frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); - WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, - frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); - WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, - frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); -} - -static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) -{ - struct drm_device *dev = encoder->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); - u32 dto_phase = 24 * 1000; - u32 dto_modulo = clock; - u32 tmp; - - if (!dig || !dig->afmt) - return; - - /* XXX two dtos; generally use dto0 for hdmi */ - /* Express [24MHz / target pixel clock] as an exact rational - * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE - * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator - */ - tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); - tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, - amdgpu_crtc->crtc_id); - WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); - WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); - WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); -} - -/* - * update the info frames with the data from the current display mode - */ -static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder, - struct drm_display_mode *mode) -{ - struct drm_device *dev = encoder->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; - struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); - u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; - struct hdmi_avi_infoframe frame; - ssize_t err; - u32 tmp; - int bpc = 8; - - if (!dig || !dig->afmt) - return; - - /* Silent, r600_hdmi_enable will raise WARN for us */ - if (!dig->afmt->enabled) - return; - - /* hdmi deep color mode general control packets setup, if bpc > 8 */ - if (encoder->crtc) { - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); - bpc = amdgpu_crtc->bpc; - } - - /* disable audio prior to setting up hw */ - dig->afmt->pin = dce_v11_0_audio_get_pin(adev); - dce_v11_0_audio_enable(adev, dig->afmt->pin, false); - - dce_v11_0_audio_set_dto(encoder, mode->clock); - - tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); - tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); - WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ - - WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); - - tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); - switch (bpc) { - case 0: - case 6: - case 8: - case 16: - default: - tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); - tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); - DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", - connector->name, bpc); - break; - case 10: - tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); - tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); - DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", - connector->name); - break; - case 12: - tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); - tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); - DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", - connector->name); - break; - } - WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); - - tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); - tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ - tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ - tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ - WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); - - tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); - /* enable audio info frames (frames won't be set until audio is enabled) */ - tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); - /* required for audio info values to be updated */ - tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); - WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); - - tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); - /* required for audio info values to be updated */ - tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); - WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); - - tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); - /* anything other than 0 */ - tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); - WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); - - WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ - - tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); - /* set the default audio delay */ - tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); - /* should be suffient for all audio modes and small enough for all hblanks */ - tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); - WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); - - tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); - /* allow 60958 channel status fields to be updated */ - tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); - WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); - - tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); - if (bpc > 8) - /* clear SW CTS value */ - tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); - else - /* select SW CTS value */ - tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); - /* allow hw to sent ACR packets when required */ - tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); - WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); - - dce_v11_0_afmt_update_ACR(encoder, mode->clock); - - tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); - tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); - WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); - - tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); - tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); - WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); - - tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); - tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); - tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); - tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); - tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); - tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); - tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); - WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); - - dce_v11_0_audio_write_speaker_allocation(encoder); - - WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, - (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); - - dce_v11_0_afmt_audio_select_pin(encoder); - dce_v11_0_audio_write_sad_regs(encoder); - dce_v11_0_audio_write_latency_fields(encoder, mode); - -#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) - err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); -#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) - err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); -#else - err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); -#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ - if (err < 0) { - DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); - return; - } - - err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); - if (err < 0) { - DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); - return; - } - - dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); - - tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); - /* enable AVI info frames */ - tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); - /* required for audio info values to be updated */ - tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); - WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); - - tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); - tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); - WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); - - tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); - /* send audio packets */ - tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); - WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); - - WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); - WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); - WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); - WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); - - /* enable audio after to setting up hw */ - dce_v11_0_audio_enable(adev, dig->afmt->pin, true); -} - -static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable) -{ - struct drm_device *dev = encoder->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; - - if (!dig || !dig->afmt) - return; - - /* Silent, r600_hdmi_enable will raise WARN for us */ - if (enable && dig->afmt->enabled) - return; - if (!enable && !dig->afmt->enabled) - return; - - if (!enable && dig->afmt->pin) { - dce_v11_0_audio_enable(adev, dig->afmt->pin, false); - dig->afmt->pin = NULL; - } - - dig->afmt->enabled = enable; - - DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", - enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); -} - -static int dce_v11_0_afmt_init(struct amdgpu_device *adev) -{ - int i; - - for (i = 0; i < adev->mode_info.num_dig; i++) - adev->mode_info.afmt[i] = NULL; - - /* DCE11 has audio blocks tied to DIG encoders */ - for (i = 0; i < adev->mode_info.num_dig; i++) { - adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); - if (adev->mode_info.afmt[i]) { - adev->mode_info.afmt[i]->offset = dig_offsets[i]; - adev->mode_info.afmt[i]->id = i; - } else { - int j; - for (j = 0; j < i; j++) { - kfree(adev->mode_info.afmt[j]); - adev->mode_info.afmt[j] = NULL; - } - return -ENOMEM; - } - } - return 0; -} - -static void dce_v11_0_afmt_fini(struct amdgpu_device *adev) -{ - int i; - - for (i = 0; i < adev->mode_info.num_dig; i++) { - kfree(adev->mode_info.afmt[i]); - adev->mode_info.afmt[i] = NULL; - } -} - -static const u32 vga_control_regs[6] = -{ - mmD1VGA_CONTROL, - mmD2VGA_CONTROL, - mmD3VGA_CONTROL, - mmD4VGA_CONTROL, - mmD5VGA_CONTROL, - mmD6VGA_CONTROL, -}; - -static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - struct drm_device *dev = crtc->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - u32 vga_control; - - vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; - if (enable) - WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); - else - WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); -} - -static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - struct drm_device *dev = crtc->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - - if (enable) - WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); - else - WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); -} - -static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - int x, int y, int atomic) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - struct drm_device *dev = crtc->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct drm_framebuffer *target_fb; - struct drm_gem_object *obj; - struct amdgpu_bo *abo; - uint64_t fb_location, tiling_flags; - uint32_t fb_format, fb_pitch_pixels; - u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); - u32 pipe_config; - u32 tmp, viewport_w, viewport_h; - int r; - bool bypass_lut = false; - - /* no fb bound */ - if (!atomic && !crtc->primary->fb) { - DRM_DEBUG_KMS("No FB bound\n"); - return 0; - } - - if (atomic) - target_fb = fb; - else - target_fb = crtc->primary->fb; - - /* If atomic, assume fb object is pinned & idle & fenced and - * just update base pointers - */ - obj = drm_gem_fb_get_obj(target_fb, 0); - abo = gem_to_amdgpu_bo(obj); - r = amdgpu_bo_reserve(abo, false); - if (unlikely(r != 0)) - return r; - - if (!atomic) { - abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; - r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); - if (unlikely(r != 0)) { - amdgpu_bo_unreserve(abo); - return -EINVAL; - } - } - fb_location = amdgpu_bo_gpu_offset(abo); - - amdgpu_bo_get_tiling_flags(abo, &tiling_flags); - amdgpu_bo_unreserve(abo); - - pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); - - switch (target_fb->format->format) { - case DRM_FORMAT_C8: - fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); - fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); - break; - case DRM_FORMAT_XRGB4444: - case DRM_FORMAT_ARGB4444: - fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); - fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); -#ifdef __BIG_ENDIAN - fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, - ENDIAN_8IN16); -#endif - break; - case DRM_FORMAT_XRGB1555: - case DRM_FORMAT_ARGB1555: - fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); - fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); -#ifdef __BIG_ENDIAN - fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, - ENDIAN_8IN16); -#endif - break; - case DRM_FORMAT_BGRX5551: - case DRM_FORMAT_BGRA5551: - fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); - fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); -#ifdef __BIG_ENDIAN - fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, - ENDIAN_8IN16); -#endif - break; - case DRM_FORMAT_RGB565: - fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); - fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); -#ifdef __BIG_ENDIAN - fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, - ENDIAN_8IN16); -#endif - break; - case DRM_FORMAT_XRGB8888: - case DRM_FORMAT_ARGB8888: - fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); - fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); -#ifdef __BIG_ENDIAN - fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, - ENDIAN_8IN32); -#endif - break; - case DRM_FORMAT_XRGB2101010: - case DRM_FORMAT_ARGB2101010: - fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); - fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); -#ifdef __BIG_ENDIAN - fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, - ENDIAN_8IN32); -#endif - /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ - bypass_lut = true; - break; - case DRM_FORMAT_BGRX1010102: - case DRM_FORMAT_BGRA1010102: - fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); - fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); -#ifdef __BIG_ENDIAN - fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, - ENDIAN_8IN32); -#endif - /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ - bypass_lut = true; - break; - case DRM_FORMAT_XBGR8888: - case DRM_FORMAT_ABGR8888: - fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); - fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); - fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2); - fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2); -#ifdef __BIG_ENDIAN - fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, - ENDIAN_8IN32); -#endif - break; - default: - DRM_ERROR("Unsupported screen format %p4cc\n", - &target_fb->format->format); - return -EINVAL; - } - - if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { - unsigned bankw, bankh, mtaspect, tile_split, num_banks; - - bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); - bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); - mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); - tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); - num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); - - fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); - fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, - ARRAY_2D_TILED_THIN1); - fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, - tile_split); - fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); - fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); - fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, - mtaspect); - fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, - ADDR_SURF_MICRO_TILING_DISPLAY); - } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { - fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, - ARRAY_1D_TILED_THIN1); - } - - fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, - pipe_config); - - dce_v11_0_vga_enable(crtc, false); - - /* Make sure surface address is updated at vertical blank rather than - * horizontal blank - */ - tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); - tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, - GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); - WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); - - WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, - upper_32_bits(fb_location)); - WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, - upper_32_bits(fb_location)); - WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, - (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); - WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, - (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); - WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); - WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); - - /* - * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT - * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to - * retain the full precision throughout the pipeline. - */ - tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); - if (bypass_lut) - tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); - else - tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); - WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); - - if (bypass_lut) - DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); - - WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); - WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); - WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); - WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); - WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); - WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); - - fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; - WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); - - dce_v11_0_grph_enable(crtc, true); - - WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, - target_fb->height); - - x &= ~3; - y &= ~1; - WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, - (x << 16) | y); - viewport_w = crtc->mode.hdisplay; - viewport_h = (crtc->mode.vdisplay + 1) & ~1; - WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, - (viewport_w << 16) | viewport_h); - - /* set pageflip to happen anywhere in vblank interval */ - WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); - - if (!atomic && fb && fb != crtc->primary->fb) { - abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); - r = amdgpu_bo_reserve(abo, true); - if (unlikely(r != 0)) - return r; - amdgpu_bo_unpin(abo); - amdgpu_bo_unreserve(abo); - } - - /* Bytes per pixel may have changed */ - dce_v11_0_bandwidth_update(adev); - - return 0; -} - -static void dce_v11_0_set_interleave(struct drm_crtc *crtc, - struct drm_display_mode *mode) -{ - struct drm_device *dev = crtc->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - u32 tmp; - - tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); - if (mode->flags & DRM_MODE_FLAG_INTERLACE) - tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); - else - tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); - WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); -} - -static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - struct drm_device *dev = crtc->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - u16 *r, *g, *b; - int i; - u32 tmp; - - DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); - - tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); - tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); - WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); - - tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); - tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); - WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); - - tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); - tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); - WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); - - WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); - - WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); - WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); - WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); - - WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); - WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); - WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); - - WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); - WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); - - WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); - r = crtc->gamma_store; - g = r + crtc->gamma_size; - b = g + crtc->gamma_size; - for (i = 0; i < 256; i++) { - WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, - ((*r++ & 0xffc0) << 14) | - ((*g++ & 0xffc0) << 4) | - (*b++ >> 6)); - } - - tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); - tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); - tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); - tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0); - WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); - - tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); - tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); - WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); - - tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); - tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); - WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); - - tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); - tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); - WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); - - /* XXX match this to the depth of the crtc fmt block, move to modeset? */ - WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); - /* XXX this only needs to be programmed once per crtc at startup, - * not sure where the best place for it is - */ - tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); - tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); - WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); -} - -static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder) -{ - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; - - switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - if (dig->linkb) - return 1; - else - return 0; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - if (dig->linkb) - return 3; - else - return 2; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - if (dig->linkb) - return 5; - else - return 4; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: - return 6; - default: - DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); - return 0; - } -} - -/** - * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc. - * - * @crtc: drm crtc - * - * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors - * a single PPLL can be used for all DP crtcs/encoders. For non-DP - * monitors a dedicated PPLL must be used. If a particular board has - * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming - * as there is no need to program the PLL itself. If we are not able to - * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to - * avoid messing up an existing monitor. - * - * Asic specific PLL information - * - * DCE 10.x - * Tonga - * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) - * CI - * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC - * - */ -static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - struct drm_device *dev = crtc->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - u32 pll_in_use; - int pll; - - if ((adev->asic_type == CHIP_POLARIS10) || - (adev->asic_type == CHIP_POLARIS11) || - (adev->asic_type == CHIP_POLARIS12) || - (adev->asic_type == CHIP_VEGAM)) { - struct amdgpu_encoder *amdgpu_encoder = - to_amdgpu_encoder(amdgpu_crtc->encoder); - struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; - - if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) - return ATOM_DP_DTO; - - switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - if (dig->linkb) - return ATOM_COMBOPHY_PLL1; - else - return ATOM_COMBOPHY_PLL0; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - if (dig->linkb) - return ATOM_COMBOPHY_PLL3; - else - return ATOM_COMBOPHY_PLL2; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - if (dig->linkb) - return ATOM_COMBOPHY_PLL5; - else - return ATOM_COMBOPHY_PLL4; - default: - DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); - return ATOM_PPLL_INVALID; - } - } - - if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { - if (adev->clock.dp_extclk) - /* skip PPLL programming if using ext clock */ - return ATOM_PPLL_INVALID; - else { - /* use the same PPLL for all DP monitors */ - pll = amdgpu_pll_get_shared_dp_ppll(crtc); - if (pll != ATOM_PPLL_INVALID) - return pll; - } - } else { - /* use the same PPLL for all monitors with the same clock */ - pll = amdgpu_pll_get_shared_nondp_ppll(crtc); - if (pll != ATOM_PPLL_INVALID) - return pll; - } - - /* XXX need to determine what plls are available on each DCE11 part */ - pll_in_use = amdgpu_pll_get_use_mask(crtc); - if (adev->flags & AMD_IS_APU) { - if (!(pll_in_use & (1 << ATOM_PPLL1))) - return ATOM_PPLL1; - if (!(pll_in_use & (1 << ATOM_PPLL0))) - return ATOM_PPLL0; - DRM_ERROR("unable to allocate a PPLL\n"); - return ATOM_PPLL_INVALID; - } else { - if (!(pll_in_use & (1 << ATOM_PPLL2))) - return ATOM_PPLL2; - if (!(pll_in_use & (1 << ATOM_PPLL1))) - return ATOM_PPLL1; - if (!(pll_in_use & (1 << ATOM_PPLL0))) - return ATOM_PPLL0; - DRM_ERROR("unable to allocate a PPLL\n"); - return ATOM_PPLL_INVALID; - } - return ATOM_PPLL_INVALID; -} - -static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock) -{ - struct amdgpu_device *adev = drm_to_adev(crtc->dev); - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - uint32_t cur_lock; - - cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); - if (lock) - cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); - else - cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); - WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); -} - -static void dce_v11_0_hide_cursor(struct drm_crtc *crtc) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - struct amdgpu_device *adev = drm_to_adev(crtc->dev); - u32 tmp; - - tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); - tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); - WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); -} - -static void dce_v11_0_show_cursor(struct drm_crtc *crtc) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - struct amdgpu_device *adev = drm_to_adev(crtc->dev); - u32 tmp; - - WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, - upper_32_bits(amdgpu_crtc->cursor_addr)); - WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, - lower_32_bits(amdgpu_crtc->cursor_addr)); - - tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); - tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); - tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); - WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); -} - -static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc, - int x, int y) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - struct amdgpu_device *adev = drm_to_adev(crtc->dev); - int xorigin = 0, yorigin = 0; - - amdgpu_crtc->cursor_x = x; - amdgpu_crtc->cursor_y = y; - - /* avivo cursor are offset into the total surface */ - x += crtc->x; - y += crtc->y; - DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); - - if (x < 0) { - xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); - x = 0; - } - if (y < 0) { - yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); - y = 0; - } - - WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); - WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); - WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, - ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); - - return 0; -} - -static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc, - int x, int y) -{ - int ret; - - dce_v11_0_lock_cursor(crtc, true); - ret = dce_v11_0_cursor_move_locked(crtc, x, y); - dce_v11_0_lock_cursor(crtc, false); - - return ret; -} - -static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, - struct drm_file *file_priv, - uint32_t handle, - uint32_t width, - uint32_t height, - int32_t hot_x, - int32_t hot_y) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - struct drm_gem_object *obj; - struct amdgpu_bo *aobj; - int ret; - - if (!handle) { - /* turn off cursor */ - dce_v11_0_hide_cursor(crtc); - obj = NULL; - goto unpin; - } - - if ((width > amdgpu_crtc->max_cursor_width) || - (height > amdgpu_crtc->max_cursor_height)) { - DRM_ERROR("bad cursor width or height %d x %d\n", width, height); - return -EINVAL; - } - - obj = drm_gem_object_lookup(file_priv, handle); - if (!obj) { - DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); - return -ENOENT; - } - - aobj = gem_to_amdgpu_bo(obj); - ret = amdgpu_bo_reserve(aobj, false); - if (ret != 0) { - drm_gem_object_put(obj); - return ret; - } - - aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; - ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); - amdgpu_bo_unreserve(aobj); - if (ret) { - DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); - drm_gem_object_put(obj); - return ret; - } - amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); - - dce_v11_0_lock_cursor(crtc, true); - - if (width != amdgpu_crtc->cursor_width || - height != amdgpu_crtc->cursor_height || - hot_x != amdgpu_crtc->cursor_hot_x || - hot_y != amdgpu_crtc->cursor_hot_y) { - int x, y; - - x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; - y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; - - dce_v11_0_cursor_move_locked(crtc, x, y); - - amdgpu_crtc->cursor_width = width; - amdgpu_crtc->cursor_height = height; - amdgpu_crtc->cursor_hot_x = hot_x; - amdgpu_crtc->cursor_hot_y = hot_y; - } - - dce_v11_0_show_cursor(crtc); - dce_v11_0_lock_cursor(crtc, false); - -unpin: - if (amdgpu_crtc->cursor_bo) { - struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); - ret = amdgpu_bo_reserve(aobj, true); - if (likely(ret == 0)) { - amdgpu_bo_unpin(aobj); - amdgpu_bo_unreserve(aobj); - } - drm_gem_object_put(amdgpu_crtc->cursor_bo); - } - - amdgpu_crtc->cursor_bo = obj; - return 0; -} - -static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - - if (amdgpu_crtc->cursor_bo) { - dce_v11_0_lock_cursor(crtc, true); - - dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, - amdgpu_crtc->cursor_y); - - dce_v11_0_show_cursor(crtc); - - dce_v11_0_lock_cursor(crtc, false); - } -} - -static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t size, - struct drm_modeset_acquire_ctx *ctx) -{ - dce_v11_0_crtc_load_lut(crtc); - - return 0; -} - -static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - - drm_crtc_cleanup(crtc); - kfree(amdgpu_crtc); -} - -static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { - .cursor_set2 = dce_v11_0_crtc_cursor_set2, - .cursor_move = dce_v11_0_crtc_cursor_move, - .gamma_set = dce_v11_0_crtc_gamma_set, - .set_config = amdgpu_display_crtc_set_config, - .destroy = dce_v11_0_crtc_destroy, - .page_flip_target = amdgpu_display_crtc_page_flip_target, -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP - .get_vblank_counter = amdgpu_get_vblank_counter_kms, - .enable_vblank = amdgpu_enable_vblank_kms, - .disable_vblank = amdgpu_disable_vblank_kms, - .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, -#endif -}; - -static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode) -{ - struct drm_device *dev = crtc->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - unsigned type; - - switch (mode) { - case DRM_MODE_DPMS_ON: - amdgpu_crtc->enabled = true; - amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); - dce_v11_0_vga_enable(crtc, true); - amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); - dce_v11_0_vga_enable(crtc, false); - /* Make sure VBLANK and PFLIP interrupts are still enabled */ - type = amdgpu_display_crtc_idx_to_irq_type(adev, - amdgpu_crtc->crtc_id); - amdgpu_irq_update(adev, &adev->crtc_irq, type); - amdgpu_irq_update(adev, &adev->pageflip_irq, type); - drm_crtc_vblank_on(crtc); - dce_v11_0_crtc_load_lut(crtc); - break; - case DRM_MODE_DPMS_STANDBY: - case DRM_MODE_DPMS_SUSPEND: - case DRM_MODE_DPMS_OFF: - drm_crtc_vblank_off(crtc); - if (amdgpu_crtc->enabled) { - dce_v11_0_vga_enable(crtc, true); - amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); - dce_v11_0_vga_enable(crtc, false); - } - amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); - amdgpu_crtc->enabled = false; - break; - } - /* adjust pm to dpms */ - amdgpu_dpm_compute_clocks(adev); -} - -static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc) -{ - /* disable crtc pair power gating before programming */ - amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); - amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); - dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); -} - -static void dce_v11_0_crtc_commit(struct drm_crtc *crtc) -{ - dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); - amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); -} - -static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - struct drm_device *dev = crtc->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_atom_ss ss; - int i; - - dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); - if (crtc->primary->fb) { - int r; - struct amdgpu_bo *abo; - - abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(crtc->primary->fb, 0)); - r = amdgpu_bo_reserve(abo, true); - if (unlikely(r)) - DRM_ERROR("failed to reserve abo before unpin\n"); - else { - amdgpu_bo_unpin(abo); - amdgpu_bo_unreserve(abo); - } - } - /* disable the GRPH */ - dce_v11_0_grph_enable(crtc, false); - - amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); - - for (i = 0; i < adev->mode_info.num_crtc; i++) { - if (adev->mode_info.crtcs[i] && - adev->mode_info.crtcs[i]->enabled && - i != amdgpu_crtc->crtc_id && - amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { - /* one other crtc is using this pll don't turn - * off the pll - */ - goto done; - } - } - - switch (amdgpu_crtc->pll_id) { - case ATOM_PPLL0: - case ATOM_PPLL1: - case ATOM_PPLL2: - /* disable the ppll */ - amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, - 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); - break; - case ATOM_COMBOPHY_PLL0: - case ATOM_COMBOPHY_PLL1: - case ATOM_COMBOPHY_PLL2: - case ATOM_COMBOPHY_PLL3: - case ATOM_COMBOPHY_PLL4: - case ATOM_COMBOPHY_PLL5: - /* disable the ppll */ - amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id, - 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); - break; - default: - break; - } -done: - amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; - amdgpu_crtc->adjusted_clock = 0; - amdgpu_crtc->encoder = NULL; - amdgpu_crtc->connector = NULL; -} - -static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode, - int x, int y, struct drm_framebuffer *old_fb) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - struct drm_device *dev = crtc->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - - if (!amdgpu_crtc->adjusted_clock) - return -EINVAL; - - if ((adev->asic_type == CHIP_POLARIS10) || - (adev->asic_type == CHIP_POLARIS11) || - (adev->asic_type == CHIP_POLARIS12) || - (adev->asic_type == CHIP_VEGAM)) { - struct amdgpu_encoder *amdgpu_encoder = - to_amdgpu_encoder(amdgpu_crtc->encoder); - int encoder_mode = - amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); - - /* SetPixelClock calculates the plls and ss values now */ - amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, - amdgpu_crtc->pll_id, - encoder_mode, amdgpu_encoder->encoder_id, - adjusted_mode->clock, 0, 0, 0, 0, - amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); - } else { - amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); - } - amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); - dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); - amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); - amdgpu_atombios_crtc_scaler_setup(crtc); - dce_v11_0_cursor_reset(crtc); - /* update the hw version fpr dpm */ - amdgpu_crtc->hw_mode = *adjusted_mode; - - return 0; -} - -static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - struct drm_device *dev = crtc->dev; - struct drm_encoder *encoder; - - /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - if (encoder->crtc == crtc) { - amdgpu_crtc->encoder = encoder; - amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); - break; - } - } - if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { - amdgpu_crtc->encoder = NULL; - amdgpu_crtc->connector = NULL; - return false; - } - if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) - return false; - if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) - return false; - /* pick pll */ - amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc); - /* if we can't get a PPLL for a non-DP encoder, fail */ - if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && - !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) - return false; - - return true; -} - -static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, - struct drm_framebuffer *old_fb) -{ - return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); -} - -static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - int x, int y, enum mode_set_atomic state) -{ - return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1); -} - -static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = { - .dpms = dce_v11_0_crtc_dpms, - .mode_fixup = dce_v11_0_crtc_mode_fixup, - .mode_set = dce_v11_0_crtc_mode_set, - .mode_set_base = dce_v11_0_crtc_set_base, - .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic, - .prepare = dce_v11_0_crtc_prepare, - .commit = dce_v11_0_crtc_commit, - .disable = dce_v11_0_crtc_disable, -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP - .get_scanout_position = amdgpu_crtc_get_scanout_position, -#endif -}; - -#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER -static void dce_v11_0_panic_flush(struct drm_plane *plane) -{ - struct drm_framebuffer *fb; - struct amdgpu_crtc *amdgpu_crtc; - struct amdgpu_device *adev; - uint32_t fb_format; - - if (!plane->fb) - return; - - fb = plane->fb; - amdgpu_crtc = to_amdgpu_crtc(plane->crtc); - adev = drm_to_adev(fb->dev); - - /* Disable DC tiling */ - fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); - fb_format &= ~GRPH_CONTROL__GRPH_ARRAY_MODE_MASK; - WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); - -} - -static const struct drm_plane_helper_funcs dce_v11_0_drm_primary_plane_helper_funcs = { - .get_scanout_buffer = amdgpu_display_get_scanout_buffer, - .panic_flush = dce_v11_0_panic_flush, -}; -#endif - -static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) -{ - struct amdgpu_crtc *amdgpu_crtc; - - amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + - (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); - if (amdgpu_crtc == NULL) - return -ENOMEM; - - drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); - - drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); - amdgpu_crtc->crtc_id = index; - adev->mode_info.crtcs[index] = amdgpu_crtc; - - amdgpu_crtc->max_cursor_width = 128; - amdgpu_crtc->max_cursor_height = 128; - adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; - adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; - - switch (amdgpu_crtc->crtc_id) { - case 0: - default: - amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; - break; - case 1: - amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; - break; - case 2: - amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; - break; - case 3: - amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; - break; - case 4: - amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; - break; - case 5: - amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; - break; - } - - amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; - amdgpu_crtc->adjusted_clock = 0; - amdgpu_crtc->encoder = NULL; - amdgpu_crtc->connector = NULL; - drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); -#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER - drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v11_0_drm_primary_plane_helper_funcs); -#endif - - return 0; -} - -static int dce_v11_0_early_init(struct amdgpu_ip_block *ip_block) -{ - struct amdgpu_device *adev = ip_block->adev; - - adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; - adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; - - dce_v11_0_set_display_funcs(adev); - - adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev); - - switch (adev->asic_type) { - case CHIP_CARRIZO: - adev->mode_info.num_hpd = 6; - adev->mode_info.num_dig = 9; - break; - case CHIP_STONEY: - adev->mode_info.num_hpd = 6; - adev->mode_info.num_dig = 9; - break; - case CHIP_POLARIS10: - case CHIP_VEGAM: - adev->mode_info.num_hpd = 6; - adev->mode_info.num_dig = 6; - break; - case CHIP_POLARIS11: - case CHIP_POLARIS12: - adev->mode_info.num_hpd = 5; - adev->mode_info.num_dig = 5; - break; - default: - /* FIXME: not supported yet */ - return -EINVAL; - } - - dce_v11_0_set_irq_funcs(adev); - - return 0; -} - -static int dce_v11_0_sw_init(struct amdgpu_ip_block *ip_block) -{ - int r, i; - struct amdgpu_device *adev = ip_block->adev; - - for (i = 0; i < adev->mode_info.num_crtc; i++) { - r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); - if (r) - return r; - } - - for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) { - r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); - if (r) - return r; - } - - /* HPD hotplug */ - r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); - if (r) - return r; - - adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; - - adev_to_drm(adev)->mode_config.async_page_flip = true; - - adev_to_drm(adev)->mode_config.max_width = 16384; - adev_to_drm(adev)->mode_config.max_height = 16384; - - adev_to_drm(adev)->mode_config.preferred_depth = 24; - adev_to_drm(adev)->mode_config.prefer_shadow = 1; - -#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED - adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; -#endif - - r = amdgpu_display_modeset_create_props(adev); - if (r) - return r; - - adev_to_drm(adev)->mode_config.max_width = 16384; - adev_to_drm(adev)->mode_config.max_height = 16384; - - - /* allocate crtcs */ - for (i = 0; i < adev->mode_info.num_crtc; i++) { - r = dce_v11_0_crtc_init(adev, i); - if (r) - return r; - } - - if (amdgpu_atombios_get_connector_info_from_object_table(adev)) - amdgpu_display_print_display_setup(adev_to_drm(adev)); - else - return -EINVAL; - - /* setup afmt */ - r = dce_v11_0_afmt_init(adev); - if (r) - return r; - - r = dce_v11_0_audio_init(adev); - if (r) - return r; - - /* Disable vblank IRQs aggressively for power-saving */ - /* XXX: can this be enabled for DC? */ - adev_to_drm(adev)->vblank_disable_immediate = true; - - r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); - if (r) - return r; - - INIT_DELAYED_WORK(&adev->hotplug_work, - amdgpu_display_hotplug_work_func); - - drm_kms_helper_poll_init(adev_to_drm(adev)); - - adev->mode_info.mode_config_initialized = true; - return 0; -} - -static int dce_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) -{ - struct amdgpu_device *adev = ip_block->adev; - - drm_edid_free(adev->mode_info.bios_hardcoded_edid); - - drm_kms_helper_poll_fini(adev_to_drm(adev)); - - dce_v11_0_audio_fini(adev); - - dce_v11_0_afmt_fini(adev); - - drm_mode_config_cleanup(adev_to_drm(adev)); - adev->mode_info.mode_config_initialized = false; - - return 0; -} - -static int dce_v11_0_hw_init(struct amdgpu_ip_block *ip_block) -{ - int i; - struct amdgpu_device *adev = ip_block->adev; - - dce_v11_0_init_golden_registers(adev); - - /* disable vga render */ - dce_v11_0_set_vga_render_state(adev, false); - /* init dig PHYs, disp eng pll */ - amdgpu_atombios_crtc_powergate_init(adev); - amdgpu_atombios_encoder_init_dig(adev); - if ((adev->asic_type == CHIP_POLARIS10) || - (adev->asic_type == CHIP_POLARIS11) || - (adev->asic_type == CHIP_POLARIS12) || - (adev->asic_type == CHIP_VEGAM)) { - amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk, - DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS); - amdgpu_atombios_crtc_set_dce_clock(adev, 0, - DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS); - } else { - amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); - } - - /* initialize hpd */ - dce_v11_0_hpd_init(adev); - - for (i = 0; i < adev->mode_info.audio.num_pins; i++) { - dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); - } - - dce_v11_0_pageflip_interrupt_init(adev); - - return 0; -} - -static int dce_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) -{ - int i; - struct amdgpu_device *adev = ip_block->adev; - - dce_v11_0_hpd_fini(adev); - - for (i = 0; i < adev->mode_info.audio.num_pins; i++) { - dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); - } - - dce_v11_0_pageflip_interrupt_fini(adev); - - flush_delayed_work(&adev->hotplug_work); - - return 0; -} - -static int dce_v11_0_suspend(struct amdgpu_ip_block *ip_block) -{ - struct amdgpu_device *adev = ip_block->adev; - int r; - - r = amdgpu_display_suspend_helper(adev); - if (r) - return r; - - adev->mode_info.bl_level = - amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); - - return dce_v11_0_hw_fini(ip_block); -} - -static int dce_v11_0_resume(struct amdgpu_ip_block *ip_block) -{ - struct amdgpu_device *adev = ip_block->adev; - int ret; - - amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, - adev->mode_info.bl_level); - - ret = dce_v11_0_hw_init(ip_block); - - /* turn on the BL */ - if (adev->mode_info.bl_encoder) { - u8 bl_level = amdgpu_display_backlight_get_level(adev, - adev->mode_info.bl_encoder); - amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, - bl_level); - } - if (ret) - return ret; - - return amdgpu_display_resume_helper(adev); -} - -static bool dce_v11_0_is_idle(struct amdgpu_ip_block *ip_block) -{ - return true; -} - -static int dce_v11_0_soft_reset(struct amdgpu_ip_block *ip_block) -{ - u32 srbm_soft_reset = 0, tmp; - struct amdgpu_device *adev = ip_block->adev; - - if (dce_v11_0_is_display_hung(adev)) - srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; - - if (srbm_soft_reset) { - tmp = RREG32(mmSRBM_SOFT_RESET); - tmp |= srbm_soft_reset; - dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); - WREG32(mmSRBM_SOFT_RESET, tmp); - tmp = RREG32(mmSRBM_SOFT_RESET); - - udelay(50); - - tmp &= ~srbm_soft_reset; - WREG32(mmSRBM_SOFT_RESET, tmp); - tmp = RREG32(mmSRBM_SOFT_RESET); - - /* Wait a little for things to settle down */ - udelay(50); - } - return 0; -} - -static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, - int crtc, - enum amdgpu_interrupt_state state) -{ - u32 lb_interrupt_mask; - - if (crtc >= adev->mode_info.num_crtc) { - DRM_DEBUG("invalid crtc %d\n", crtc); - return; - } - - switch (state) { - case AMDGPU_IRQ_STATE_DISABLE: - lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); - lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, - VBLANK_INTERRUPT_MASK, 0); - WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); - break; - case AMDGPU_IRQ_STATE_ENABLE: - lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); - lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, - VBLANK_INTERRUPT_MASK, 1); - WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); - break; - default: - break; - } -} - -static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, - int crtc, - enum amdgpu_interrupt_state state) -{ - u32 lb_interrupt_mask; - - if (crtc >= adev->mode_info.num_crtc) { - DRM_DEBUG("invalid crtc %d\n", crtc); - return; - } - - switch (state) { - case AMDGPU_IRQ_STATE_DISABLE: - lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); - lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, - VLINE_INTERRUPT_MASK, 0); - WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); - break; - case AMDGPU_IRQ_STATE_ENABLE: - lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); - lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, - VLINE_INTERRUPT_MASK, 1); - WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); - break; - default: - break; - } -} - -static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev, - struct amdgpu_irq_src *source, - unsigned hpd, - enum amdgpu_interrupt_state state) -{ - u32 tmp; - - if (hpd >= adev->mode_info.num_hpd) { - DRM_DEBUG("invalid hpd %d\n", hpd); - return 0; - } - - switch (state) { - case AMDGPU_IRQ_STATE_DISABLE: - tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); - tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); - WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); - break; - case AMDGPU_IRQ_STATE_ENABLE: - tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); - tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); - WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); - break; - default: - break; - } - - return 0; -} - -static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev, - struct amdgpu_irq_src *source, - unsigned type, - enum amdgpu_interrupt_state state) -{ - switch (type) { - case AMDGPU_CRTC_IRQ_VBLANK1: - dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state); - break; - case AMDGPU_CRTC_IRQ_VBLANK2: - dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state); - break; - case AMDGPU_CRTC_IRQ_VBLANK3: - dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state); - break; - case AMDGPU_CRTC_IRQ_VBLANK4: - dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state); - break; - case AMDGPU_CRTC_IRQ_VBLANK5: - dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state); - break; - case AMDGPU_CRTC_IRQ_VBLANK6: - dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state); - break; - case AMDGPU_CRTC_IRQ_VLINE1: - dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state); - break; - case AMDGPU_CRTC_IRQ_VLINE2: - dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state); - break; - case AMDGPU_CRTC_IRQ_VLINE3: - dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state); - break; - case AMDGPU_CRTC_IRQ_VLINE4: - dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state); - break; - case AMDGPU_CRTC_IRQ_VLINE5: - dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state); - break; - case AMDGPU_CRTC_IRQ_VLINE6: - dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state); - break; - default: - break; - } - return 0; -} - -static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev, - struct amdgpu_irq_src *src, - unsigned type, - enum amdgpu_interrupt_state state) -{ - u32 reg; - - if (type >= adev->mode_info.num_crtc) { - DRM_ERROR("invalid pageflip crtc %d\n", type); - return -EINVAL; - } - - reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); - if (state == AMDGPU_IRQ_STATE_DISABLE) - WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], - reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); - else - WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], - reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); - - return 0; -} - -static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, - struct amdgpu_irq_src *source, - struct amdgpu_iv_entry *entry) -{ - unsigned long flags; - unsigned crtc_id; - struct amdgpu_crtc *amdgpu_crtc; - struct amdgpu_flip_work *works; - - crtc_id = (entry->src_id - 8) >> 1; - amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; - - if (crtc_id >= adev->mode_info.num_crtc) { - DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); - return -EINVAL; - } - - if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & - GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) - WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], - GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); - - /* IRQ could occur when in initial stage */ - if(amdgpu_crtc == NULL) - return 0; - - spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); - works = amdgpu_crtc->pflip_works; - if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ - DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " - "AMDGPU_FLIP_SUBMITTED(%d)\n", - amdgpu_crtc->pflip_status, - AMDGPU_FLIP_SUBMITTED); - spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); - return 0; - } - - /* page flip completed. clean up */ - amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; - amdgpu_crtc->pflip_works = NULL; - - /* wakeup usersapce */ - if(works->event) - drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); - - spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); - - drm_crtc_vblank_put(&amdgpu_crtc->base); - schedule_work(&works->unpin_work); - - return 0; -} - -static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, - int hpd) -{ - u32 tmp; - - if (hpd >= adev->mode_info.num_hpd) { - DRM_DEBUG("invalid hpd %d\n", hpd); - return; - } - - tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); - tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); - WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); -} - -static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev, - int crtc) -{ - u32 tmp; - - if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { - DRM_DEBUG("invalid crtc %d\n", crtc); - return; - } - - tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); - tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); - WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); -} - -static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev, - int crtc) -{ - u32 tmp; - - if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { - DRM_DEBUG("invalid crtc %d\n", crtc); - return; - } - - tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); - tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); - WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); -} - -static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, - struct amdgpu_irq_src *source, - struct amdgpu_iv_entry *entry) -{ - unsigned crtc = entry->src_id - 1; - uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); - unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, - crtc); - - switch (entry->src_data[0]) { - case 0: /* vblank */ - if (disp_int & interrupt_status_offsets[crtc].vblank) - dce_v11_0_crtc_vblank_int_ack(adev, crtc); - else - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - if (amdgpu_irq_enabled(adev, source, irq_type)) { - drm_handle_vblank(adev_to_drm(adev), crtc); - } - DRM_DEBUG("IH: D%d vblank\n", crtc + 1); - - break; - case 1: /* vline */ - if (disp_int & interrupt_status_offsets[crtc].vline) - dce_v11_0_crtc_vline_int_ack(adev, crtc); - else - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - DRM_DEBUG("IH: D%d vline\n", crtc + 1); - - break; - default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); - break; - } - - return 0; -} - -static int dce_v11_0_hpd_irq(struct amdgpu_device *adev, - struct amdgpu_irq_src *source, - struct amdgpu_iv_entry *entry) -{ - uint32_t disp_int, mask; - unsigned hpd; - - if (entry->src_data[0] >= adev->mode_info.num_hpd) { - DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); - return 0; - } - - hpd = entry->src_data[0]; - disp_int = RREG32(interrupt_status_offsets[hpd].reg); - mask = interrupt_status_offsets[hpd].hpd; - - if (disp_int & mask) { - dce_v11_0_hpd_int_ack(adev, hpd); - schedule_delayed_work(&adev->hotplug_work, 0); - DRM_DEBUG("IH: HPD%d\n", hpd + 1); - } - - return 0; -} - -static int dce_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, - enum amd_clockgating_state state) -{ - return 0; -} - -static int dce_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block, - enum amd_powergating_state state) -{ - return 0; -} - -static const struct amd_ip_funcs dce_v11_0_ip_funcs = { - .name = "dce_v11_0", - .early_init = dce_v11_0_early_init, - .sw_init = dce_v11_0_sw_init, - .sw_fini = dce_v11_0_sw_fini, - .hw_init = dce_v11_0_hw_init, - .hw_fini = dce_v11_0_hw_fini, - .suspend = dce_v11_0_suspend, - .resume = dce_v11_0_resume, - .is_idle = dce_v11_0_is_idle, - .soft_reset = dce_v11_0_soft_reset, - .set_clockgating_state = dce_v11_0_set_clockgating_state, - .set_powergating_state = dce_v11_0_set_powergating_state, -}; - -static void dce_v11_0_encoder_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - - amdgpu_encoder->pixel_clock = adjusted_mode->clock; - - /* need to call this here rather than in prepare() since we need some crtc info */ - amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); - - /* set scaler clears this on some chips */ - dce_v11_0_set_interleave(encoder->crtc, mode); - - if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { - dce_v11_0_afmt_enable(encoder, true); - dce_v11_0_afmt_setmode(encoder, adjusted_mode); - } -} - -static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder) -{ - struct amdgpu_device *adev = drm_to_adev(encoder->dev); - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); - - if ((amdgpu_encoder->active_device & - (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || - (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != - ENCODER_OBJECT_ID_NONE)) { - struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; - if (dig) { - dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder); - if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) - dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; - } - } - - amdgpu_atombios_scratch_regs_lock(adev, true); - - if (connector) { - struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - - /* select the clock/data port if it uses a router */ - if (amdgpu_connector->router.cd_valid) - amdgpu_i2c_router_select_cd_port(amdgpu_connector); - - /* turn eDP panel on for mode set */ - if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) - amdgpu_atombios_encoder_set_edp_panel_power(connector, - ATOM_TRANSMITTER_ACTION_POWER_ON); - } - - /* this is needed for the pll/ss setup to work correctly in some cases */ - amdgpu_atombios_encoder_set_crtc_source(encoder); - /* set up the FMT blocks */ - dce_v11_0_program_fmt(encoder); -} - -static void dce_v11_0_encoder_commit(struct drm_encoder *encoder) -{ - struct drm_device *dev = encoder->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - - /* need to call this here as we need the crtc set up */ - amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); - amdgpu_atombios_scratch_regs_lock(adev, false); -} - -static void dce_v11_0_encoder_disable(struct drm_encoder *encoder) -{ - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - struct amdgpu_encoder_atom_dig *dig; - - amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); - - if (amdgpu_atombios_encoder_is_digital(encoder)) { - if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) - dce_v11_0_afmt_enable(encoder, false); - dig = amdgpu_encoder->enc_priv; - dig->dig_encoder = -1; - } - amdgpu_encoder->active_device = 0; -} - -/* these are handled by the primary encoders */ -static void dce_v11_0_ext_prepare(struct drm_encoder *encoder) -{ - -} - -static void dce_v11_0_ext_commit(struct drm_encoder *encoder) -{ - -} - -static void -dce_v11_0_ext_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - -} - -static void dce_v11_0_ext_disable(struct drm_encoder *encoder) -{ - -} - -static void -dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode) -{ - -} - -static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = { - .dpms = dce_v11_0_ext_dpms, - .prepare = dce_v11_0_ext_prepare, - .mode_set = dce_v11_0_ext_mode_set, - .commit = dce_v11_0_ext_commit, - .disable = dce_v11_0_ext_disable, - /* no detect for TMDS/LVDS yet */ -}; - -static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = { - .dpms = amdgpu_atombios_encoder_dpms, - .mode_fixup = amdgpu_atombios_encoder_mode_fixup, - .prepare = dce_v11_0_encoder_prepare, - .mode_set = dce_v11_0_encoder_mode_set, - .commit = dce_v11_0_encoder_commit, - .disable = dce_v11_0_encoder_disable, - .detect = amdgpu_atombios_encoder_dig_detect, -}; - -static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = { - .dpms = amdgpu_atombios_encoder_dpms, - .mode_fixup = amdgpu_atombios_encoder_mode_fixup, - .prepare = dce_v11_0_encoder_prepare, - .mode_set = dce_v11_0_encoder_mode_set, - .commit = dce_v11_0_encoder_commit, - .detect = amdgpu_atombios_encoder_dac_detect, -}; - -static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder) -{ - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) - amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); - kfree(amdgpu_encoder->enc_priv); - drm_encoder_cleanup(encoder); - kfree(amdgpu_encoder); -} - -static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = { - .destroy = dce_v11_0_encoder_destroy, -}; - -static void dce_v11_0_encoder_add(struct amdgpu_device *adev, - uint32_t encoder_enum, - uint32_t supported_device, - u16 caps) -{ - struct drm_device *dev = adev_to_drm(adev); - struct drm_encoder *encoder; - struct amdgpu_encoder *amdgpu_encoder; - - /* see if we already added it */ - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - amdgpu_encoder = to_amdgpu_encoder(encoder); - if (amdgpu_encoder->encoder_enum == encoder_enum) { - amdgpu_encoder->devices |= supported_device; - return; - } - - } - - /* add a new one */ - amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); - if (!amdgpu_encoder) - return; - - encoder = &amdgpu_encoder->base; - switch (adev->mode_info.num_crtc) { - case 1: - encoder->possible_crtcs = 0x1; - break; - case 2: - default: - encoder->possible_crtcs = 0x3; - break; - case 3: - encoder->possible_crtcs = 0x7; - break; - case 4: - encoder->possible_crtcs = 0xf; - break; - case 5: - encoder->possible_crtcs = 0x1f; - break; - case 6: - encoder->possible_crtcs = 0x3f; - break; - } - - amdgpu_encoder->enc_priv = NULL; - - amdgpu_encoder->encoder_enum = encoder_enum; - amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; - amdgpu_encoder->devices = supported_device; - amdgpu_encoder->rmx_type = RMX_OFF; - amdgpu_encoder->underscan_type = UNDERSCAN_OFF; - amdgpu_encoder->is_ext_encoder = false; - amdgpu_encoder->caps = caps; - - switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: - drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, - DRM_MODE_ENCODER_DAC, NULL); - drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs); - break; - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: - if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { - amdgpu_encoder->rmx_type = RMX_FULL; - drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, - DRM_MODE_ENCODER_LVDS, NULL); - amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); - } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { - drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, - DRM_MODE_ENCODER_DAC, NULL); - amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); - } else { - drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, - DRM_MODE_ENCODER_TMDS, NULL); - amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); - } - drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs); - break; - case ENCODER_OBJECT_ID_SI170B: - case ENCODER_OBJECT_ID_CH7303: - case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: - case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: - case ENCODER_OBJECT_ID_TITFP513: - case ENCODER_OBJECT_ID_VT1623: - case ENCODER_OBJECT_ID_HDMI_SI1930: - case ENCODER_OBJECT_ID_TRAVIS: - case ENCODER_OBJECT_ID_NUTMEG: - /* these are handled by the primary encoders */ - amdgpu_encoder->is_ext_encoder = true; - if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) - drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, - DRM_MODE_ENCODER_LVDS, NULL); - else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) - drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, - DRM_MODE_ENCODER_DAC, NULL); - else - drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, - DRM_MODE_ENCODER_TMDS, NULL); - drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs); - break; - } -} - -static const struct amdgpu_display_funcs dce_v11_0_display_funcs = { - .bandwidth_update = &dce_v11_0_bandwidth_update, - .vblank_get_counter = &dce_v11_0_vblank_get_counter, - .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, - .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, - .hpd_sense = &dce_v11_0_hpd_sense, - .hpd_set_polarity = &dce_v11_0_hpd_set_polarity, - .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg, - .page_flip = &dce_v11_0_page_flip, - .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos, - .add_encoder = &dce_v11_0_encoder_add, - .add_connector = &amdgpu_connector_add, -}; - -static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev) -{ - adev->mode_info.funcs = &dce_v11_0_display_funcs; -} - -static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = { - .set = dce_v11_0_set_crtc_irq_state, - .process = dce_v11_0_crtc_irq, -}; - -static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = { - .set = dce_v11_0_set_pageflip_irq_state, - .process = dce_v11_0_pageflip_irq, -}; - -static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = { - .set = dce_v11_0_set_hpd_irq_state, - .process = dce_v11_0_hpd_irq, -}; - -static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev) -{ - if (adev->mode_info.num_crtc > 0) - adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; - else - adev->crtc_irq.num_types = 0; - adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; - - adev->pageflip_irq.num_types = adev->mode_info.num_crtc; - adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; - - adev->hpd_irq.num_types = adev->mode_info.num_hpd; - adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; -} - -const struct amdgpu_ip_block_version dce_v11_0_ip_block = -{ - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 11, - .minor = 0, - .rev = 0, - .funcs = &dce_v11_0_ip_funcs, -}; - -const struct amdgpu_ip_block_version dce_v11_2_ip_block = -{ - .type = AMD_IP_BLOCK_TYPE_DCE, - .major = 11, - .minor = 2, - .rev = 0, - .funcs = &dce_v11_0_ip_funcs, -}; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h deleted file mode 100644 index 0d878ca3acbab..0000000000000 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef __DCE_V11_0_H__ -#define __DCE_V11_0_H__ - -extern const struct amdgpu_ip_block_version dce_v11_0_ip_block; -extern const struct amdgpu_ip_block_version dce_v11_2_ip_block; - -void dce_v11_0_disable_dce(struct amdgpu_device *adev); - -#endif diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 9b3510e531127..a611a73451250 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -67,7 +67,6 @@ #include "sdma_v2_4.h" #include "sdma_v3_0.h" #include "dce_v10_0.h" -#include "dce_v11_0.h" #include "iceland_ih.h" #include "tonga_ih.h" #include "cz_ih.h" @@ -2124,8 +2123,6 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) else if (amdgpu_device_has_dc_support(adev)) amdgpu_device_ip_block_add(adev, &dm_ip_block); #endif - else - amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block); amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block); amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); break; @@ -2142,8 +2139,6 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) else if (amdgpu_device_has_dc_support(adev)) amdgpu_device_ip_block_add(adev, &dm_ip_block); #endif - else - amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block); #if defined(CONFIG_DRM_AMD_ACP) @@ -2163,8 +2158,6 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) else if (amdgpu_device_has_dc_support(adev)) amdgpu_device_ip_block_add(adev, &dm_ip_block); #endif - else - amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block); amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); #if defined(CONFIG_DRM_AMD_ACP) From 47e545a6b3e92e9fee1d90bbd1b344362c20535e Mon Sep 17 00:00:00 2001 From: Xiang Liu Date: Tue, 19 Aug 2025 12:51:28 +0800 Subject: [PATCH 2027/2653] drm/amdgpu: Introduce VF critical region check for RAS poison injection The SRIOV guest send requet to host to check whether the poison injection address is in VF critical region or not via mabox. Signed-off-by: Xiang Liu Reviewed-by: Shravan Kumar Gande --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 55 +++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 3 ++ drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 5 ++ drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 14 ++++++ drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h | 2 + 5 files changed, 79 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 13f0cdeb59c46..3328ab63376bb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -828,11 +828,14 @@ static void amdgpu_virt_init_ras(struct amdgpu_device *adev) { ratelimit_state_init(&adev->virt.ras.ras_error_cnt_rs, 5 * HZ, 1); ratelimit_state_init(&adev->virt.ras.ras_cper_dump_rs, 5 * HZ, 1); + ratelimit_state_init(&adev->virt.ras.ras_chk_criti_rs, 5 * HZ, 1); ratelimit_set_flags(&adev->virt.ras.ras_error_cnt_rs, RATELIMIT_MSG_ON_RELEASE); ratelimit_set_flags(&adev->virt.ras.ras_cper_dump_rs, RATELIMIT_MSG_ON_RELEASE); + ratelimit_set_flags(&adev->virt.ras.ras_chk_criti_rs, + RATELIMIT_MSG_ON_RELEASE); mutex_init(&adev->virt.ras.ras_telemetry_mutex); @@ -1501,3 +1504,55 @@ void amdgpu_virt_request_bad_pages(struct amdgpu_device *adev) if (virt->ops && virt->ops->req_bad_pages) virt->ops->req_bad_pages(adev); } + +static int amdgpu_virt_cache_chk_criti_hit(struct amdgpu_device *adev, + struct amdsriov_ras_telemetry *host_telemetry, + bool *hit) +{ + struct amd_sriov_ras_chk_criti *tmp = NULL; + uint32_t checksum, used_size; + + checksum = host_telemetry->header.checksum; + used_size = host_telemetry->header.used_size; + + if (used_size > (AMD_SRIOV_RAS_TELEMETRY_SIZE_KB << 10)) + return 0; + + tmp = kmemdup(&host_telemetry->body.chk_criti, used_size, GFP_KERNEL); + if (!tmp) + return -ENOMEM; + + if (checksum != amd_sriov_msg_checksum(tmp, used_size, 0, 0)) + goto out; + + if (hit) + *hit = tmp->hit ? true : false; + +out: + kfree(tmp); + + return 0; +} + +int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, bool *hit) +{ + struct amdgpu_virt *virt = &adev->virt; + int r = -EPERM; + + if (!virt->ops || !virt->ops->req_ras_chk_criti) + return -EOPNOTSUPP; + + /* Host allows 15 ras telemetry requests per 60 seconds. Afterwhich, the Host + * will ignore incoming guest messages. Ratelimit the guest messages to + * prevent guest self DOS. + */ + if (__ratelimit(&virt->ras.ras_chk_criti_rs)) { + mutex_lock(&virt->ras.ras_telemetry_mutex); + if (!virt->ops->req_ras_chk_criti(adev, addr)) + r = amdgpu_virt_cache_chk_criti_hit( + adev, virt->fw_reserve.ras_telemetry, hit); + mutex_unlock(&virt->ras.ras_telemetry_mutex); + } + + return r; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 3afbdf7b487a1..d1172c8e58c47 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -98,6 +98,7 @@ struct amdgpu_virt_ops { int (*req_ras_err_count)(struct amdgpu_device *adev); int (*req_ras_cper_dump)(struct amdgpu_device *adev, u64 vf_rptr); int (*req_bad_pages)(struct amdgpu_device *adev); + int (*req_ras_chk_criti)(struct amdgpu_device *adev, u64 addr); }; /* @@ -252,6 +253,7 @@ struct amdgpu_virt_ras_err_handler_data { struct amdgpu_virt_ras { struct ratelimit_state ras_error_cnt_rs; struct ratelimit_state ras_cper_dump_rs; + struct ratelimit_state ras_chk_criti_rs; struct mutex ras_telemetry_mutex; uint64_t cper_rptr; }; @@ -453,4 +455,5 @@ int amdgpu_virt_ras_telemetry_post_reset(struct amdgpu_device *adev); bool amdgpu_virt_ras_telemetry_block_en(struct amdgpu_device *adev, enum amdgpu_ras_block block); void amdgpu_virt_request_bad_pages(struct amdgpu_device *adev); +int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, bool *hit); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h index 33edad1f9dcd6..3a79ed7d8031e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h @@ -405,12 +405,17 @@ struct amd_sriov_ras_cper_dump { uint32_t buf[]; }; +struct amd_sriov_ras_chk_criti { + uint32_t hit; +}; + struct amdsriov_ras_telemetry { struct amd_sriov_ras_telemetry_header header; union { struct amd_sriov_ras_telemetry_error_count error_count; struct amd_sriov_ras_cper_dump cper_dump; + struct amd_sriov_ras_chk_criti chk_criti; } body; }; diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c index 457972aa56324..e5282a5d05d95 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c @@ -202,6 +202,9 @@ static int xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev, case IDH_REQ_RAS_CPER_DUMP: event = IDH_RAS_CPER_DUMP_READY; break; + case IDH_REQ_RAS_CHK_CRITI: + event = IDH_REQ_RAS_CHK_CRITI_READY; + break; default: break; } @@ -556,6 +559,16 @@ static int xgpu_nv_req_ras_bad_pages(struct amdgpu_device *adev) return xgpu_nv_send_access_requests(adev, IDH_REQ_RAS_BAD_PAGES); } +static int xgpu_nv_check_vf_critical_region(struct amdgpu_device *adev, u64 addr) +{ + uint32_t addr_hi, addr_lo; + + addr_hi = (uint32_t)(addr >> 32); + addr_lo = (uint32_t)(addr & 0xFFFFFFFF); + return xgpu_nv_send_access_requests_with_param( + adev, IDH_REQ_RAS_CHK_CRITI, addr_hi, addr_lo, 0); +} + const struct amdgpu_virt_ops xgpu_nv_virt_ops = { .req_full_gpu = xgpu_nv_request_full_gpu_access, .rel_full_gpu = xgpu_nv_release_full_gpu_access, @@ -569,4 +582,5 @@ const struct amdgpu_virt_ops xgpu_nv_virt_ops = { .req_ras_err_count = xgpu_nv_req_ras_err_count, .req_ras_cper_dump = xgpu_nv_req_ras_cper_dump, .req_bad_pages = xgpu_nv_req_ras_bad_pages, + .req_ras_chk_criti = xgpu_nv_check_vf_critical_region }; diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h index 5808689562ccb..c1083e5e41e02 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h @@ -43,6 +43,7 @@ enum idh_request { IDH_REQ_RAS_ERROR_COUNT = 203, IDH_REQ_RAS_CPER_DUMP = 204, IDH_REQ_RAS_BAD_PAGES = 205, + IDH_REQ_RAS_CHK_CRITI = 206 }; enum idh_event { @@ -62,6 +63,7 @@ enum idh_event { IDH_RAS_BAD_PAGES_READY = 15, IDH_RAS_BAD_PAGES_NOTIFICATION = 16, IDH_UNRECOV_ERR_NOTIFICATION = 17, + IDH_REQ_RAS_CHK_CRITI_READY = 18, IDH_TEXT_MESSAGE = 255, }; From fb20ff08e7b5ab17db67cff37bb595ab04ad697a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 17 Sep 2025 12:42:09 -0400 Subject: [PATCH 2028/2653] drm/amdkfd: add proper handling for S0ix When in S0i3, the GFX state is retained, so all we need to do is stop the runlist so GFX can enter gfxoff. Reviewed-by: Mario Limonciello (AMD) Tested-By: David Perry Signed-off-by: Alex Deucher --- Change-Id: I2a70026d365a9fcd7642ce882771cfd872cd1158 --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 16 +++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 12 ++++++++ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 36 ++++++++++++++++++++++ 3 files changed, 60 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 81afd6c3edceb..70f5334775a6f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -251,16 +251,24 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc) { - if (adev->kfd.dev) - kgd2kfd_suspend(adev->kfd.dev, suspend_proc, true); + if (adev->kfd.dev) { + if (adev->in_s0ix) + kgd2kfd_stop_sched_all_nodes(adev->kfd.dev); + else + kgd2kfd_suspend(adev->kfd.dev, suspend_proc, true); + } } int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc) { int r = 0; - if (adev->kfd.dev) - r = kgd2kfd_resume(adev->kfd.dev, resume_proc); + if (adev->kfd.dev) { + if (adev->in_s0ix) + r = kgd2kfd_start_sched_all_nodes(adev->kfd.dev); + else + r = kgd2kfd_resume(adev->kfd.dev, resume_proc); + } return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 81885165b1f28..bcdafcf91c272 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -500,7 +500,9 @@ void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask); int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd); void kgd2kfd_unlock_kfd(struct kfd_dev *kfd); int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id); +int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd); int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id); +int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd); bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id); bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, bool retry_fault); @@ -590,11 +592,21 @@ static inline int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id) return 0; } +static inline int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd) +{ + return 0; +} + static inline int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) { return 0; } +static inline int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd) +{ + return 0; +} + static inline bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) { return false; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index e4982e7721d5b..944e8372e9e9b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -1572,6 +1572,25 @@ int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id) return ret; } +int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd) +{ + struct kfd_node *node; + int i, r; + + if (!kfd->init_complete) + return 0; + + for (i = 0; i < kfd->num_nodes; i++) { + node = kfd->nodes[i]; + r = node->dqm->ops.unhalt(node->dqm); + if (r) { + dev_err(kfd_device, "Error in starting scheduler\n"); + return r; + } + } + return 0; +} + int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) { struct kfd_node *node; @@ -1589,6 +1608,23 @@ int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) return node->dqm->ops.halt(node->dqm); } +int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd) +{ + struct kfd_node *node; + int i, r; + + if (!kfd->init_complete) + return 0; + + for (i = 0; i < kfd->num_nodes; i++) { + node = kfd->nodes[i]; + r = node->dqm->ops.halt(node->dqm); + if (r) + return r; + } + return 0; +} + bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) { struct kfd_node *node; From 2e948e25e52d257a72ff9d5b5796ba61f34ea062 Mon Sep 17 00:00:00 2001 From: Xiang Liu Date: Tue, 19 Aug 2025 13:06:24 +0800 Subject: [PATCH 2029/2653] drm/amdgpu: Check VF critical region before RAS poison injection Check VF critical region before RAS poison injection to ensure that the poison injection will not hit the VF critical region. Signed-off-by: Xiang Liu Reviewed-by: Shravan Kumar Gande --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 3ea11b945fc0b..c6f3a327108b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -219,10 +219,17 @@ static int amdgpu_check_address_validity(struct amdgpu_device *adev, struct amdgpu_vram_block_info blk_info; uint64_t page_pfns[32] = {0}; int i, ret, count; + bool hit = false; if (amdgpu_ip_version(adev, UMC_HWIP, 0) < IP_VERSION(12, 0, 0)) return 0; + if (amdgpu_sriov_vf(adev)) { + if (amdgpu_virt_check_vf_critical_region(adev, address, &hit)) + return -EPERM; + return hit ? -EACCES : 0; + } + if ((address >= adev->gmc.mc_vram_size) || (address >= RAS_UMC_INJECT_ADDR_LIMIT)) return -EFAULT; From 4410c772984e1ff857954a388b4c271cc1751136 Mon Sep 17 00:00:00 2001 From: "Joe.Wang" Date: Wed, 17 Sep 2025 14:58:49 +0800 Subject: [PATCH 2030/2653] drm/amdgpu: Fix PRT flag for gfx12 AMDGPU_PTE_PRT_GFX12 flag is missed during pageTable rework, add it back. Fixes: 6716a823d18d ("drm/amdgpu: rework how PTE flags are generated v3") Signed-off-by: Joe Wang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 7cc16af1868b3..404cc8c2ff2c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -521,6 +521,7 @@ static void gmc_v12_0_get_vm_pte(struct amdgpu_device *adev, *flags &= ~AMDGPU_PTE_NOALLOC; if (vm_flags & AMDGPU_VM_PAGE_PRT) { + *flags |= AMDGPU_PTE_PRT_GFX12; *flags |= AMDGPU_PTE_SNOOPED; *flags |= AMDGPU_PTE_SYSTEM; *flags |= AMDGPU_PTE_IS_PTE; From 029cb464c6576ab674019ed05702690199921b5b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 17 Sep 2025 12:42:10 -0400 Subject: [PATCH 2031/2653] drm/amdgpu/userq: Optimize S0ix handling In S0i3, GFX state is retained, so it's preferrable to preempt queues rather than unmapping them as the overhead is lower. Reviewed-by: Mario Limonciello (AMD) Tested-By: David Perry Signed-off-by: Alex Deucher --- Change-Id: I1c0b75dc369e93dcca7261bb3a6adcd4fda1b844 --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 442f69979e579..b6885548e727a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -982,7 +982,10 @@ int amdgpu_userq_suspend(struct amdgpu_device *adev) cancel_delayed_work_sync(&uqm->resume_work); mutex_lock(&uqm->userq_mutex); idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { - r = amdgpu_userq_unmap_helper(uqm, queue); + if (adev->in_s0ix) + r = amdgpu_userq_preempt_helper(uqm, queue); + else + r = amdgpu_userq_unmap_helper(uqm, queue); if (r) ret = r; } @@ -1007,7 +1010,10 @@ int amdgpu_userq_resume(struct amdgpu_device *adev) list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { mutex_lock(&uqm->userq_mutex); idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { - r = amdgpu_userq_map_helper(uqm, queue); + if (adev->in_s0ix) + r = amdgpu_userq_restore_helper(uqm, queue); + else + r = amdgpu_userq_map_helper(uqm, queue); if (r) ret = r; } From c48aa6cdf03fac0dbcd239c3116aff4b388e5c40 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 17 Sep 2025 12:42:11 -0400 Subject: [PATCH 2032/2653] drm/amdgpu: suspend KFD and KGD user queues for S0ix We need to make sure the user queues are preempted so GFX can enter gfxoff. Reviewed-by: Mario Limonciello (AMD) Tested-By: David Perry Signed-off-by: Alex Deucher --- Change-Id: I9175aa1c4187bf8301e0c7f3f91925ccdf1d5d01 --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 24 +++++++++------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 53b94074c359b..5f075ac74d611 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5251,7 +5251,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients) adev->in_suspend = true; if (amdgpu_sriov_vf(adev)) { - if (!adev->in_s0ix && !adev->in_runpm) + if (!adev->in_runpm) amdgpu_amdkfd_suspend_process(adev); amdgpu_virt_fini_data_exchange(adev); r = amdgpu_virt_request_full_gpu(adev, false); @@ -5271,10 +5271,8 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients) amdgpu_device_ip_suspend_phase1(adev); - if (!adev->in_s0ix) { - amdgpu_amdkfd_suspend(adev, !amdgpu_sriov_vf(adev) && !adev->in_runpm); - amdgpu_userq_suspend(adev); - } + amdgpu_amdkfd_suspend(adev, !amdgpu_sriov_vf(adev) && !adev->in_runpm); + amdgpu_userq_suspend(adev); r = amdgpu_device_evict_resources(adev); if (r) @@ -5369,15 +5367,13 @@ int amdgpu_device_resume(struct drm_device *dev, bool notify_clients) goto exit; } - if (!adev->in_s0ix) { - r = amdgpu_amdkfd_resume(adev, !amdgpu_sriov_vf(adev) && !adev->in_runpm); - if (r) - goto exit; + r = amdgpu_amdkfd_resume(adev, !amdgpu_sriov_vf(adev) && !adev->in_runpm); + if (r) + goto exit; - r = amdgpu_userq_resume(adev); - if (r) - goto exit; - } + r = amdgpu_userq_resume(adev); + if (r) + goto exit; r = amdgpu_device_ip_late_init(adev); if (r) @@ -5390,7 +5386,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool notify_clients) amdgpu_virt_init_data_exchange(adev); amdgpu_virt_release_full_gpu(adev, true); - if (!adev->in_s0ix && !r && !adev->in_runpm) + if (!r && !adev->in_runpm) r = amdgpu_amdkfd_resume_process(adev); } From bfcea5c38ca0ff7a21c60974e4b0d524bed6bb1f Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 3 Sep 2025 15:51:24 +0800 Subject: [PATCH 2033/2653] drm/amdkcl: fix NULL pointer dereference during module unload The free_xcp_dev() function incorrectly uses the global pdev_num variable to index into the xcp_dev array. Since pdev_num is decremented during the loop, it can lead to accessing an incorrect index during concurrent unloads or error conditions, resulting in a NULL pointer dereference. Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c index 90ba91f6c9620..c7b3de2def021 100644 --- a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c +++ b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c @@ -112,8 +112,8 @@ static void free_xcp_dev(int8_t index) devres_release_group(&pdev->dev, NULL); platform_device_unregister(pdev); #ifndef HAVE_DRM_DRM_MANAGED_H - drm_dev_fini(&(xcp_dev[pdev_num]->drm)); - kfree(xcp_dev[pdev_num]); + drm_dev_fini(&(xcp_dev[index]->drm)); + kfree(xcp_dev[index]); #endif xcp_dev[index] = NULL; pdev_num--; From 72740669c152b64acfa5d4f75a18a7ff82bae9b8 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 18 Sep 2025 17:38:17 +0800 Subject: [PATCH 2034/2653] drm/amdkcl: fix check struct block_device has member named 'bd_device' Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/blk_types.m4 | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/blk_types.m4 b/drivers/gpu/drm/amd/dkms/m4/blk_types.m4 index 6c92962c97e00..d6d3e21a7efea 100644 --- a/drivers/gpu/drm/amd/dkms/m4/blk_types.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/blk_types.m4 @@ -4,12 +4,14 @@ dnl # block: merge struct block_device and struct hd_struct dnl # AC_DEFUN([AC_AMDGPU_BLOCK_DEVICE_BD_DEVICE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct block_device *device = NULL; + struct device dev = {}; + device->bd_device = dev; ], [ - struct block_device *device; - device.bd_device = NULL; - ], [],[],[ AC_DEFINE(HAVE_BLOCK_DEVICE_BD_DEVICE, 1, [struct block_device has member named 'bd_device']) ]) From 94b52c158e2905475bbb1a7e7762b444a5885220 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Fri, 19 Sep 2025 15:00:25 +0800 Subject: [PATCH 2035/2653] Bump AMDGPU version to 6.16.4 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 68f9689b5315d..b4639482f6eb3 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.16.3) +AC_INIT(amdgpu-dkms, 6.16.4) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 51513e993fc1b72e168ddd602d58955f6a80d4af Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Mon, 15 Sep 2025 15:59:23 +0800 Subject: [PATCH 2036/2653] drm/amdkcl: test vfs_iocb_iter_read() is available It's caused by the commit: b70e506 "drm/amdkfd: Add AMD Infinity Storage (AIS) support" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_fs_read_write.c | 90 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/kcl_security.c | 24 +++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/dkms/config/config.h | 3 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/vfs_iocb_iter_read.m4 | 16 ++++ include/kcl/kcl_fs.h | 9 ++ 8 files changed, 146 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_security.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/vfs_iocb_iter_read.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index af911c325e4b9..ac6ff97260bb0 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -5,7 +5,7 @@ amdkcl-y += kcl_kernel_params.o amdkcl-y += dma-buf/dma-resv.o kcl_dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ - kcl_kthread.o kcl_io.o kcl_seq_file.o \ + kcl_kthread.o kcl_io.o kcl_seq_file.o kcl_security.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o \ kcl_fence.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_drm_edid.o\ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c b/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c index e45c10eabc006..622d2c40eece3 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c @@ -5,6 +5,9 @@ */ #include #include +#include +#include +#include /* Copied from v4.13-rc7-6-ge13ec939e96b:fs/read_write.c */ #ifndef HAVE_KERNEL_WRITE_PPOS @@ -25,3 +28,90 @@ ssize_t _kcl_kernel_write(struct file *file, const void *buf, size_t count, EXPORT_SYMBOL(_kcl_kernel_write); #endif +#ifndef HAVE_VFS_IOCB_ITER_READ +int kcl_security_file_permission(struct file *file, int mask); + +static inline bool kcl_unsigned_offsets(struct file *file) +{ + return file->f_mode & FMODE_UNSIGNED_OFFSET; +} + +int kcl_rw_verify_area(int read_write, struct file *file, const loff_t *ppos, size_t count) +{ + if (unlikely((ssize_t) count < 0)) + return -EINVAL; + + if (ppos) { + loff_t pos = *ppos; + + if (unlikely(pos < 0)) { + if (!kcl_unsigned_offsets(file)) + return -EINVAL; + if (count >= -pos) /* both values are in 0..LLONG_MAX */ + return -EOVERFLOW; + } else if (unlikely((loff_t) (pos + count) < 0)) { + if (!kcl_unsigned_offsets(file)) + return -EINVAL; + } + } + + return kcl_security_file_permission(file, + read_write == READ ? MAY_READ : MAY_WRITE); +} + +ssize_t kcl_vfs_iocb_iter_read(struct file *file, struct kiocb *iocb, + struct iov_iter *iter) +{ + size_t tot_len; + ssize_t ret = 0; + + if (!file->f_op->read_iter) + return -EINVAL; + if (!(file->f_mode & FMODE_READ)) + return -EBADF; + if (!(file->f_mode & FMODE_CAN_READ)) + return -EINVAL; + + tot_len = iov_iter_count(iter); + if (!tot_len) + goto out; + ret = kcl_rw_verify_area(READ, file, &iocb->ki_pos, tot_len); + if (ret < 0) + return ret; + + ret = call_read_iter(file, iocb, iter); +out: + if (ret >= 0) + fsnotify_access(file); + return ret; +} +EXPORT_SYMBOL(kcl_vfs_iocb_iter_read); + +ssize_t kcl_vfs_iocb_iter_write(struct file *file, struct kiocb *iocb, + struct iov_iter *iter) +{ + size_t tot_len; + ssize_t ret = 0; + + if (!file->f_op->write_iter) + return -EINVAL; + if (!(file->f_mode & FMODE_WRITE)) + return -EBADF; + if (!(file->f_mode & FMODE_CAN_WRITE)) + return -EINVAL; + + tot_len = iov_iter_count(iter); + if (!tot_len) + return 0; + ret = kcl_rw_verify_area(WRITE, file, &iocb->ki_pos, tot_len); + if (ret < 0) + return ret; + + ret = call_write_iter(file, iocb, iter); + if (ret > 0) + fsnotify_modify(file); + + return ret; +} +EXPORT_SYMBOL(kcl_vfs_iocb_iter_write); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_security.c b/drivers/gpu/drm/amd/amdkcl/kcl_security.c new file mode 100644 index 0000000000000..6ba63cf49ef7a --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_security.c @@ -0,0 +1,24 @@ +#include +#ifdef CONFIG_SECURITY +#include +#endif +#include "kcl_common.h" + +#ifndef HAVE_VFS_IOCB_ITER_READ +struct file; // Forward declaration + +int (*kcl_security_file_permission)(struct file *file, int mask); + +int _kcl_security_file_permission(struct file *file, int mask) +{ + pr_warn_once("This kernel version not support API: security_file_permission !\n"); + return 0; +} +#endif + +void amdkcl_security_init(void) +{ +#ifndef HAVE_VFS_IOCB_ITER_READ + kcl_security_file_permission = amdkcl_fp_setup("security_file_permission", _kcl_security_file_permission); +#endif +} \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 73fd6da35a4e0..d7956a35cae96 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -9,6 +9,7 @@ extern void amdkcl_suspend_init(void); extern void amdkcl_numa_init(void); extern void amdkcl_workqueue_init(void); extern void amdkcl_prime_init(void); +extern void amdkcl_security_init(void); int __init amdkcl_init(void) { @@ -19,6 +20,7 @@ int __init amdkcl_init(void) amdkcl_numa_init(); amdkcl_workqueue_init(); amdkcl_prime_init(); + amdkcl_security_init(); return 0; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0eb49c6ea9986..61f38b2c6fbff 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1253,6 +1253,9 @@ /* usleep_range_state() is available */ #define HAVE_USLEEP_RANGE_STATE 1 +/* vfs_iocb_iter_read() is available */ +#define HAVE_VFS_IOCB_ITER_READ 1 + /* vga_client_register() don't pass a cookie */ #define HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 680456b007ce4..6f32089a5b0e9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -295,6 +295,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PAGE_PGMAP AC_AMDGPU_VMEMDUP_ARRAY_USER AC_AMDGPU_BITMAP_READ + AC_AMDGPU_VFS_IOCB_ITER_READ AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/vfs_iocb_iter_read.m4 b/drivers/gpu/drm/amd/dkms/m4/vfs_iocb_iter_read.m4 new file mode 100644 index 0000000000000..5c70d0482dc09 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vfs_iocb_iter_read.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit: v5.5-rc7-11-g5dcdc43e24a1 +dnl # vfs: add vfs_iocb_iter_[read|write] helper functions +dnl # +AC_DEFUN([AC_AMDGPU_VFS_IOCB_ITER_READ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + vfs_iocb_iter_read(NULL, NULL, NULL); + ],[vfs_iocb_iter_read],[fs/read_write.c], [ + AC_DEFINE(HAVE_VFS_IOCB_ITER_READ, 1, + [vfs_iocb_iter_read() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_fs.h b/include/kcl/kcl_fs.h index db6b6ad389abf..ec3e04940e701 100644 --- a/include/kcl/kcl_fs.h +++ b/include/kcl/kcl_fs.h @@ -31,4 +31,13 @@ ssize_t _kcl_kernel_write(struct file *file, const void *buf, size_t count, #endif #endif +#ifndef HAVE_VFS_IOCB_ITER_READ +ssize_t kcl_vfs_iocb_iter_read(struct file *file, struct kiocb *iocb, + struct iov_iter *iter); +ssize_t kcl_vfs_iocb_iter_write(struct file *file, struct kiocb *iocb, + struct iov_iter *iter); +#define vfs_iocb_iter_read kcl_vfs_iocb_iter_read +#define vfs_iocb_iter_write kcl_vfs_iocb_iter_write +#endif + #endif From 0d75bc2a656ed5be906e2f235d83a99a3c162e19 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 18 Sep 2025 09:33:51 +0530 Subject: [PATCH 2037/2653] drm/amdgpu: add missing comment for the new argument MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In function 'amdgpu_vm_lock_done_list' update the comment for the new argument 'vm'. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202509180211.UAqME0zj-lkp@intel.com/ Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 2d1dc89ed11e1..034cec00bc4cf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -501,6 +501,7 @@ int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, /** * amdgpu_vm_lock_done_list - lock all BOs on the done list + * @vm: vm providing the BOs * @exec: drm execution context * @num_fences: number of extra fences to reserve * From 8fbaf22c7acb9da12e3063318f98293b7d59c199 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 27 Aug 2025 11:45:45 +0200 Subject: [PATCH 2038/2653] drm/amdgpu: revert to old status lock handling v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It turned out that protecting the status of each bo_va with a spinlock was just hiding problems instead of solving them. Revert the whole approach, add a separate stats_lock and lockdep assertions that the correct reservation lock is held all over the place. This not only allows for better checks if a state transition is properly protected by a lock, but also switching back to using list macros to iterate over the state of lists protected by the dma_resv lock of the root PD. v2: re-add missing check v3: split into two patches Signed-off-by: Christian König Acked-by: Sunil Khatri Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 168 +++++++++++----------- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 15 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 4 - 4 files changed, 93 insertions(+), 102 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index b6885548e727a..11857daf6ac02 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -729,12 +729,12 @@ amdgpu_userq_bo_validate(struct amdgpu_device *adev, struct drm_exec *exec, struct amdgpu_bo *bo; int ret; - spin_lock(&vm->status_lock); + spin_lock(&vm->invalidated_lock); while (!list_empty(&vm->invalidated)) { bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, base.vm_status); - spin_unlock(&vm->status_lock); + spin_unlock(&vm->invalidated_lock); bo = bo_va->base.bo; ret = drm_exec_prepare_obj(exec, &bo->tbo.base, 2); @@ -751,9 +751,9 @@ amdgpu_userq_bo_validate(struct amdgpu_device *adev, struct drm_exec *exec, if (ret) return ret; - spin_lock(&vm->status_lock); + spin_lock(&vm->invalidated_lock); } - spin_unlock(&vm->status_lock); + spin_unlock(&vm->invalidated_lock); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 034cec00bc4cf..5f0aa7336828b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -127,6 +127,17 @@ struct amdgpu_vm_tlb_seq_struct { struct dma_fence_cb cb; }; +/** + * amdgpu_vm_assert_locked - check if VM is correctly locked + * @vm: the VM which schould be tested + * + * Asserts that the VM root PD is locked. + */ +static void amdgpu_vm_assert_locked(struct amdgpu_vm *vm) +{ + dma_resv_assert_held(vm->root.bo->tbo.base.resv); +} + /** * amdgpu_vm_set_pasid - manage pasid and vm ptr mapping * @@ -143,6 +154,8 @@ int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, { int r = 0; + amdgpu_vm_assert_locked(vm); + #ifdef HAVE_STRUCT_XARRAY if (vm->pasid == pasid) return 0; @@ -196,12 +209,11 @@ static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo) struct amdgpu_bo *bo = vm_bo->bo; vm_bo->moved = true; - spin_lock(&vm_bo->vm->status_lock); + amdgpu_vm_assert_locked(vm); if (bo->tbo.type == ttm_bo_type_kernel) list_move(&vm_bo->vm_status, &vm->evicted); else list_move_tail(&vm_bo->vm_status, &vm->evicted); - spin_unlock(&vm_bo->vm->status_lock); } /** * amdgpu_vm_bo_moved - vm_bo is moved @@ -213,9 +225,8 @@ static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo) */ static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo) { - spin_lock(&vm_bo->vm->status_lock); + amdgpu_vm_assert_locked(vm_bo->vm); list_move(&vm_bo->vm_status, &vm_bo->vm->moved); - spin_unlock(&vm_bo->vm->status_lock); } /** @@ -228,9 +239,8 @@ static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo) */ static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo) { - spin_lock(&vm_bo->vm->status_lock); + amdgpu_vm_assert_locked(vm_bo->vm); list_move(&vm_bo->vm_status, &vm_bo->vm->idle); - spin_unlock(&vm_bo->vm->status_lock); vm_bo->moved = false; } @@ -244,9 +254,9 @@ static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo) */ static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo) { - spin_lock(&vm_bo->vm->status_lock); + spin_lock(&vm_bo->vm->invalidated_lock); list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated); - spin_unlock(&vm_bo->vm->status_lock); + spin_unlock(&vm_bo->vm->invalidated_lock); } /** @@ -259,10 +269,9 @@ static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo) */ static void amdgpu_vm_bo_evicted_user(struct amdgpu_vm_bo_base *vm_bo) { + amdgpu_vm_assert_locked(vm_bo->vm); vm_bo->moved = true; - spin_lock(&vm_bo->vm->status_lock); list_move(&vm_bo->vm_status, &vm_bo->vm->evicted_user); - spin_unlock(&vm_bo->vm->status_lock); } /** @@ -275,13 +284,11 @@ static void amdgpu_vm_bo_evicted_user(struct amdgpu_vm_bo_base *vm_bo) */ static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo) { - if (vm_bo->bo->parent) { - spin_lock(&vm_bo->vm->status_lock); + amdgpu_vm_assert_locked(vm_bo->vm); + if (vm_bo->bo->parent) list_move(&vm_bo->vm_status, &vm_bo->vm->relocated); - spin_unlock(&vm_bo->vm->status_lock); - } else { + else amdgpu_vm_bo_idle(vm_bo); - } } /** @@ -294,9 +301,8 @@ static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo) */ static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo) { - spin_lock(&vm_bo->vm->status_lock); + amdgpu_vm_assert_locked(vm_bo->vm); list_move(&vm_bo->vm_status, &vm_bo->vm->done); - spin_unlock(&vm_bo->vm->status_lock); } /** @@ -310,10 +316,13 @@ static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm) { struct amdgpu_vm_bo_base *vm_bo, *tmp; - spin_lock(&vm->status_lock); + spin_lock(&vm->invalidated_lock); list_splice_init(&vm->done, &vm->invalidated); list_for_each_entry(vm_bo, &vm->invalidated, vm_status) vm_bo->moved = true; + spin_unlock(&vm->invalidated_lock); + + amdgpu_vm_assert_locked(vm_bo->vm); list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) { struct amdgpu_bo *bo = vm_bo->bo; @@ -323,14 +332,13 @@ static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm) else if (bo->parent) list_move(&vm_bo->vm_status, &vm_bo->vm->relocated); } - spin_unlock(&vm->status_lock); } /** * amdgpu_vm_update_shared - helper to update shared memory stat * @base: base structure for tracking BO usage in a VM * - * Takes the vm status_lock and updates the shared memory stat. If the basic + * Takes the vm stats_lock and updates the shared memory stat. If the basic * stat changed (e.g. buffer was moved) amdgpu_vm_update_stats need to be called * as well. */ @@ -342,7 +350,8 @@ static void amdgpu_vm_update_shared(struct amdgpu_vm_bo_base *base) uint32_t bo_memtype = amdgpu_bo_mem_stats_placement(bo); bool shared; - spin_lock(&vm->status_lock); + dma_resv_assert_held(bo->tbo.base.resv); + spin_lock(&vm->stats_lock); shared = drm_gem_object_is_shared_for_memory_stats(&bo->tbo.base); if (base->shared != shared) { base->shared = shared; @@ -354,7 +363,7 @@ static void amdgpu_vm_update_shared(struct amdgpu_vm_bo_base *base) vm->stats[bo_memtype].drm.private += size; } } - spin_unlock(&vm->status_lock); + spin_unlock(&vm->stats_lock); } /** @@ -379,11 +388,11 @@ void amdgpu_vm_bo_update_shared(struct amdgpu_bo *bo) * be bo->tbo.resource * @sign: if we should add (+1) or subtract (-1) from the stat * - * Caller need to have the vm status_lock held. Useful for when multiple update + * Caller need to have the vm stats_lock held. Useful for when multiple update * need to happen at the same time. */ static void amdgpu_vm_update_stats_locked(struct amdgpu_vm_bo_base *base, - struct ttm_resource *res, int sign) + struct ttm_resource *res, int sign) { struct amdgpu_vm *vm = base->vm; struct amdgpu_bo *bo = base->bo; @@ -407,7 +416,8 @@ static void amdgpu_vm_update_stats_locked(struct amdgpu_vm_bo_base *base, */ if (bo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) vm->stats[res_memtype].drm.purgeable += size; - if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(res_memtype))) + if (!(bo->preferred_domains & + amdgpu_mem_type_to_domain(res_memtype))) vm->stats[bo_memtype].evicted += size; } } @@ -426,9 +436,9 @@ void amdgpu_vm_update_stats(struct amdgpu_vm_bo_base *base, { struct amdgpu_vm *vm = base->vm; - spin_lock(&vm->status_lock); + spin_lock(&vm->stats_lock); amdgpu_vm_update_stats_locked(base, res, sign); - spin_unlock(&vm->status_lock); + spin_unlock(&vm->stats_lock); } /** @@ -454,10 +464,10 @@ void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, base->next = bo->vm_bo; bo->vm_bo = base; - spin_lock(&vm->status_lock); + spin_lock(&vm->stats_lock); base->shared = drm_gem_object_is_shared_for_memory_stats(&bo->tbo.base); amdgpu_vm_update_stats_locked(base, bo->tbo.resource, +1); - spin_unlock(&vm->status_lock); + spin_unlock(&vm->stats_lock); if (!amdgpu_vm_is_bo_always_valid(vm, bo)) return; @@ -516,10 +526,10 @@ int amdgpu_vm_lock_done_list(struct amdgpu_vm *vm, struct drm_exec *exec, int ret; /* We can only trust prev->next while holding the lock */ - spin_lock(&vm->status_lock); + spin_lock(&vm->invalidated_lock); while (!list_is_head(prev->next, &vm->done)) { bo_va = list_entry(prev->next, typeof(*bo_va), base.vm_status); - spin_unlock(&vm->status_lock); + spin_unlock(&vm->invalidated_lock); bo = bo_va->base.bo; if (bo) { @@ -527,10 +537,10 @@ int amdgpu_vm_lock_done_list(struct amdgpu_vm *vm, struct drm_exec *exec, if (unlikely(ret)) return ret; } - spin_lock(&vm->status_lock); + spin_lock(&vm->invalidated_lock); prev = prev->next; } - spin_unlock(&vm->status_lock); + spin_unlock(&vm->invalidated_lock); return 0; } @@ -626,7 +636,7 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, void *param) { uint64_t new_vm_generation = amdgpu_vm_generation(adev, vm); - struct amdgpu_vm_bo_base *bo_base; + struct amdgpu_vm_bo_base *bo_base, *tmp; struct amdgpu_bo *bo; int r; @@ -639,13 +649,7 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, return r; } - spin_lock(&vm->status_lock); - while (!list_empty(&vm->evicted)) { - bo_base = list_first_entry(&vm->evicted, - struct amdgpu_vm_bo_base, - vm_status); - spin_unlock(&vm->status_lock); - + list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) { bo = bo_base->bo; r = validate(param, bo); @@ -658,26 +662,21 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, vm->update_funcs->map_table(to_amdgpu_bo_vm(bo)); amdgpu_vm_bo_relocated(bo_base); } - spin_lock(&vm->status_lock); } - while (ticket && !list_empty(&vm->evicted_user)) { - bo_base = list_first_entry(&vm->evicted_user, - struct amdgpu_vm_bo_base, - vm_status); - spin_unlock(&vm->status_lock); - bo = bo_base->bo; - dma_resv_assert_held(bo->tbo.base.resv); + if (ticket) { + list_for_each_entry_safe(bo_base, tmp, &vm->evicted_user, + vm_status) { + bo = bo_base->bo; + dma_resv_assert_held(bo->tbo.base.resv); - r = validate(param, bo); - if (r) - return r; - - amdgpu_vm_bo_invalidated(bo_base); + r = validate(param, bo); + if (r) + return r; - spin_lock(&vm->status_lock); + amdgpu_vm_bo_invalidated(bo_base); + } } - spin_unlock(&vm->status_lock); amdgpu_vm_eviction_lock(vm); vm->evicting = false; @@ -700,13 +699,13 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm) { bool ret; + amdgpu_vm_assert_locked(vm); + amdgpu_vm_eviction_lock(vm); ret = !vm->evicting; amdgpu_vm_eviction_unlock(vm); - spin_lock(&vm->status_lock); ret &= list_empty(&vm->evicted); - spin_unlock(&vm->status_lock); spin_lock(&vm->immediate.lock); ret &= !vm->immediate.stopped; @@ -997,16 +996,13 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev, struct amdgpu_vm *vm, bool immediate) { struct amdgpu_vm_update_params params; - struct amdgpu_vm_bo_base *entry; + struct amdgpu_vm_bo_base *entry, *tmp; bool flush_tlb_needed = false; - LIST_HEAD(relocated); int r, idx; - spin_lock(&vm->status_lock); - list_splice_init(&vm->relocated, &relocated); - spin_unlock(&vm->status_lock); + amdgpu_vm_assert_locked(vm); - if (list_empty(&relocated)) + if (list_empty(&vm->relocated)) return 0; if (!drm_dev_enter(adev_to_drm(adev), &idx)) @@ -1021,7 +1017,7 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev, if (r) goto error; - list_for_each_entry(entry, &relocated, vm_status) { + list_for_each_entry(entry, &vm->relocated, vm_status) { /* vm_flush_needed after updating moved PDEs */ flush_tlb_needed |= entry->moved; @@ -1037,9 +1033,7 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev, if (flush_tlb_needed) atomic64_inc(&vm->tlb_seq); - while (!list_empty(&relocated)) { - entry = list_first_entry(&relocated, struct amdgpu_vm_bo_base, - vm_status); + list_for_each_entry_safe(entry, tmp, &vm->relocated, vm_status) { amdgpu_vm_bo_idle(entry); } @@ -1279,9 +1273,9 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, void amdgpu_vm_get_memory(struct amdgpu_vm *vm, struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM]) { - spin_lock(&vm->status_lock); + spin_lock(&vm->stats_lock); memcpy(stats, vm->stats, sizeof(*stats) * __AMDGPU_PL_NUM); - spin_unlock(&vm->status_lock); + spin_unlock(&vm->stats_lock); } /** @@ -1661,29 +1655,24 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket) { - struct amdgpu_bo_va *bo_va; + struct amdgpu_bo_va *bo_va, *tmp; struct dma_resv *resv; bool clear, unlock; int r; - spin_lock(&vm->status_lock); - while (!list_empty(&vm->moved)) { - bo_va = list_first_entry(&vm->moved, struct amdgpu_bo_va, - base.vm_status); - spin_unlock(&vm->status_lock); - + list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) { /* Per VM BOs never need to bo cleared in the page tables */ r = amdgpu_vm_bo_update(adev, bo_va, false); if (r) return r; - spin_lock(&vm->status_lock); } + spin_lock(&vm->invalidated_lock); while (!list_empty(&vm->invalidated)) { bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, base.vm_status); resv = amdkcl_ttm_resvp(&bo_va->base.bo->tbo); - spin_unlock(&vm->status_lock); + spin_unlock(&vm->invalidated_lock); /* Try to reserve the BO to avoid clearing its ptes */ if (!adev->debug_vm && dma_resv_trylock(resv)) { @@ -1715,9 +1704,9 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev, bo_va->base.bo->tbo.resource->mem_type == TTM_PL_SYSTEM)) amdgpu_vm_bo_evicted_user(&bo_va->base); - spin_lock(&vm->status_lock); + spin_lock(&vm->invalidated_lock); } - spin_unlock(&vm->status_lock); + spin_unlock(&vm->invalidated_lock); return 0; } @@ -2246,9 +2235,9 @@ void amdgpu_vm_bo_del(struct amdgpu_device *adev, } } - spin_lock(&vm->status_lock); + spin_lock(&vm->invalidated_lock); list_del(&bo_va->base.vm_status); - spin_unlock(&vm->status_lock); + spin_unlock(&vm->invalidated_lock); list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { list_del(&mapping->list); @@ -2356,10 +2345,10 @@ void amdgpu_vm_bo_move(struct amdgpu_bo *bo, struct ttm_resource *new_mem, for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { struct amdgpu_vm *vm = bo_base->vm; - spin_lock(&vm->status_lock); + spin_lock(&vm->stats_lock); amdgpu_vm_update_stats_locked(bo_base, bo->tbo.resource, -1); amdgpu_vm_update_stats_locked(bo_base, new_mem, +1); - spin_unlock(&vm->status_lock); + spin_unlock(&vm->stats_lock); } amdgpu_vm_bo_invalidate(bo, evicted); @@ -2636,11 +2625,12 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, INIT_LIST_HEAD(&vm->relocated); INIT_LIST_HEAD(&vm->moved); INIT_LIST_HEAD(&vm->idle); + spin_lock_init(&vm->invalidated_lock); INIT_LIST_HEAD(&vm->invalidated); - spin_lock_init(&vm->status_lock); INIT_LIST_HEAD(&vm->freed); INIT_LIST_HEAD(&vm->done); INIT_KFIFO(vm->faults); + spin_lock_init(&vm->stats_lock); r = amdgpu_vm_init_entities(adev, vm); if (r) @@ -3141,7 +3131,8 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m) unsigned int total_done_objs = 0; unsigned int id = 0; - spin_lock(&vm->status_lock); + amdgpu_vm_assert_locked(vm); + seq_puts(m, "\tIdle BOs:\n"); list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) { if (!bo_va->base.bo) @@ -3179,11 +3170,13 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m) id = 0; seq_puts(m, "\tInvalidated BOs:\n"); + spin_lock(&vm->invalidated_lock); list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) { if (!bo_va->base.bo) continue; total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m); } + spin_unlock(&vm->invalidated_lock); total_invalidated_objs = id; id = 0; @@ -3193,7 +3186,6 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m) continue; total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m); } - spin_unlock(&vm->status_lock); total_done_objs = id; seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 3fba271c1676f..060650b0602de 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -203,11 +203,11 @@ struct amdgpu_vm_bo_base { /* protected by bo being reserved */ struct amdgpu_vm_bo_base *next; - /* protected by vm status_lock */ + /* protected by vm reservation and invalidated_lock */ struct list_head vm_status; /* if the bo is counted as shared in mem stats - * protected by vm status_lock */ + * protected by vm BO being reserved */ bool shared; /* protected by the BO being reserved */ @@ -347,10 +347,8 @@ struct amdgpu_vm { bool evicting; unsigned int saved_flags; - /* Lock to protect vm_bo add/del/move on all lists of vm */ - spinlock_t status_lock; - - /* Memory statistics for this vm, protected by status_lock */ + /* Memory statistics for this vm, protected by stats_lock */ + spinlock_t stats_lock; struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM]; /* @@ -358,6 +356,8 @@ struct amdgpu_vm { * PDs, PTs or per VM BOs. The state transits are: * * evicted -> relocated (PDs, PTs) or moved (per VM BOs) -> idle + * + * Lists are protected by the root PD dma_resv lock. */ /* Per-VM and PT BOs who needs a validation */ @@ -378,7 +378,10 @@ struct amdgpu_vm { * state transits are: * * evicted_user or invalidated -> done + * + * Lists are protected by the invalidated_lock. */ + spinlock_t invalidated_lock; /* BOs for user mode queues that need a validation */ struct list_head evicted_user; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c index 10f31d6bd6a46..528c5a100716b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c @@ -541,9 +541,7 @@ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry) entry->bo->vm_bo = NULL; ttm_bo_set_bulk_move(&entry->bo->tbo, NULL); - spin_lock(&entry->vm->status_lock); list_del(&entry->vm_status); - spin_unlock(&entry->vm->status_lock); amdgpu_bo_unref(&entry->bo); } @@ -587,7 +585,6 @@ static void amdgpu_vm_pt_add_list(struct amdgpu_vm_update_params *params, struct amdgpu_vm_pt_cursor seek; struct amdgpu_vm_bo_base *entry; - spin_lock(¶ms->vm->status_lock); for_each_amdgpu_vm_pt_dfs_safe(params->adev, params->vm, cursor, seek, entry) { if (entry && entry->bo) list_move(&entry->vm_status, ¶ms->tlb_flush_waitlist); @@ -595,7 +592,6 @@ static void amdgpu_vm_pt_add_list(struct amdgpu_vm_update_params *params, /* enter start node now */ list_move(&cursor->entry->vm_status, ¶ms->tlb_flush_waitlist); - spin_unlock(¶ms->vm->status_lock); } /** From 79792fcefdc61379c90d7e5867d26a0e16ad11f2 Mon Sep 17 00:00:00 2001 From: Guangshuo Li Date: Thu, 18 Sep 2025 18:57:05 +0800 Subject: [PATCH 2039/2653] drm/amdgpu/atom: Check kcalloc() for WS buffer in amdgpu_atom_execute_table_locked() kcalloc() may fail. When WS is non-zero and allocation fails, ectx.ws remains NULL while ectx.ws_size is set, leading to a potential NULL pointer dereference in atom_get_src_int() when accessing WS entries. Return -ENOMEM on allocation failure to avoid the NULL dereference. Signed-off-by: Guangshuo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/atom.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c index 1c994d0cc50b5..be5d67c2c7a15 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.c +++ b/drivers/gpu/drm/amd/amdgpu/atom.c @@ -1246,6 +1246,10 @@ static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, ectx.last_jump_jiffies = 0; if (ws) { ectx.ws = kcalloc(4, ws, GFP_KERNEL); + if (!ectx.ws) { + ret = -ENOMEM; + goto free; + } ectx.ws_size = ws; } else { ectx.ws = NULL; From 209fa4e31da833852e678e596703519db9398979 Mon Sep 17 00:00:00 2001 From: Matthew Schwartz Date: Thu, 11 Sep 2025 10:48:51 -0700 Subject: [PATCH 2040/2653] drm/amd/display: Only restore backlight after amdgpu_dm_init or dm_resume On clients that utilize AMD_PRIVATE_COLOR properties for HDR support, brightness sliders can include a hardware controlled portion and a gamma-based portion. This is the case on the Steam Deck OLED when using gamescope with Steam as a client. When a user sets a brightness level while HDR is active, the gamma-based portion and/or hardware portion are adjusted to achieve the desired brightness. However, when a modeset takes place while the gamma-based portion is in-use, restoring the hardware brightness level overrides the user's overall brightness level and results in a mismatch between what the slider reports and the display's current brightness. To avoid overriding gamma-based brightness, only restore HW backlight level after boot or resume. This ensures that the backlight level is set correctly after the DC layer resets it while avoiding interference with subsequent modesets. Fixes: 7875afafba84 ("drm/amd/display: Fix brightness level not retained over reboot") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4551 Signed-off-by: Matthew Schwartz Reviewed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ++++++++---- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 7 +++++++ 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index de4ccdc30fe2e..ec8000b541e14 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2115,6 +2115,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) dc_hardware_init(adev->dm.dc); + adev->dm.restore_backlight = true; + adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev); if (!adev->dm.hpd_rx_offload_wq) { drm_err(adev_to_drm(adev), "failed to create hpd rx offload workqueue.\n"); @@ -3475,6 +3477,7 @@ static int dm_resume(struct amdgpu_ip_block *ip_block) dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); dc_resume(dm->dc); + adev->dm.restore_backlight = true; amdgpu_dm_irq_resume_early(adev); @@ -10240,7 +10243,6 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, bool mode_set_reset_required = false; u32 i; struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count}; - bool set_backlight_level = false; /* Disable writeback */ for_each_old_connector_in_state(state, connector, old_con_state, i) { @@ -10360,7 +10362,6 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, acrtc->hw_mode = new_crtc_state->mode; crtc->hwmode = new_crtc_state->mode; mode_set_reset_required = true; - set_backlight_level = true; } else if (modereset_required(new_crtc_state)) { drm_dbg_atomic(dev, "Atomic commit: RESET. crtc id %d:[%p]\n", @@ -10417,13 +10418,16 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, * to fix a flicker issue. * It will cause the dm->actual_brightness is not the current panel brightness * level. (the dm->brightness is the correct panel level) - * So we set the backlight level with dm->brightness value after set mode + * So we set the backlight level with dm->brightness value after initial + * set mode. Use restore_backlight flag to avoid setting backlight level + * for every subsequent mode set. */ - if (set_backlight_level) { + if (dm->restore_backlight) { for (i = 0; i < dm->num_of_edps; i++) { if (dm->backlight_dev[i]) amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); } + dm->restore_backlight = false; } } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index f975c163a79f8..0a8b4b6aa5b52 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -632,6 +632,13 @@ struct amdgpu_display_manager { */ u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; + /** + * @restore_backlight: + * + * Flag to indicate whether to restore backlight after modeset. + */ + bool restore_backlight; + /** * @aux_hpd_discon_quirk: * From 9f16a867205b757831cb4859967c174795b715f7 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 18 Sep 2025 17:52:04 +0530 Subject: [PATCH 2041/2653] drm/amdgpu: Fix vbios build number parsing logic It's not necessary that the build string and atom header section has a difference of 32 bytes. Use the remaining bytes in the section as copy limit. Signed-off-by: Lijo Lazar Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/atom.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c index be5d67c2c7a15..7a063e44d4298 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.c +++ b/drivers/gpu/drm/amd/amdgpu/atom.c @@ -1502,7 +1502,7 @@ static void atom_get_vbios_build(struct atom_context *ctx) { unsigned char *atom_rom_hdr; unsigned char *str; - uint16_t base; + uint16_t base, len; base = CU16(ATOM_ROM_TABLE_PTR); atom_rom_hdr = CSTR(base); @@ -1515,8 +1515,9 @@ static void atom_get_vbios_build(struct atom_context *ctx) while (str < atom_rom_hdr && *str++) ; - if ((str + STRLEN_NORMAL) < atom_rom_hdr) - strscpy(ctx->build_num, str, STRLEN_NORMAL); + len = min(atom_rom_hdr - str, STRLEN_NORMAL); + if (len) + strscpy(ctx->build_num, str, len); } struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) From cb29b1fd9d5c68d1988ea63d4fe9b6e5a6a3aed9 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 18 Sep 2025 19:48:00 -0500 Subject: [PATCH 2042/2653] drm/amdgpu: Enable MES lr_compute_wa by default The MES set resources packet has an optional bit 'lr_compute_wa' which can be used for preventing MES hangs on long compute jobs. Set this bit by default. Co-developed-by: Yifan Zhang Signed-off-by: Yifan Zhang Acked-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 5 +++++ drivers/gpu/drm/amd/include/mes_v11_api_def.h | 3 ++- drivers/gpu/drm/amd/include/mes_v12_api_def.h | 3 ++- 4 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 3b91ea601add4..e82188431f796 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -713,6 +713,12 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) mes_set_hw_res_pkt.enable_reg_active_poll = 1; mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; mes_set_hw_res_pkt.oversubscription_timer = 50; + if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x7f) + mes_set_hw_res_pkt.enable_lr_compute_wa = 1; + else + dev_info_once(mes->adev->dev, + "MES FW version must be >= 0x7f to enable LR compute workaround.\n"); + if (amdgpu_mes_log_enable) { mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index 81d24365d831f..ca6134265b5e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -769,6 +769,11 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) mes_set_hw_res_pkt.use_different_vmid_compute = 1; mes_set_hw_res_pkt.enable_reg_active_poll = 1; mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; + if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x82) + mes_set_hw_res_pkt.enable_lr_compute_wa = 1; + else + dev_info_once(adev->dev, + "MES FW version must be >= 0x82 to enable LR compute workaround.\n"); /* * Keep oversubscribe timer for sdma . When we have unmapped doorbell diff --git a/drivers/gpu/drm/amd/include/mes_v11_api_def.h b/drivers/gpu/drm/amd/include/mes_v11_api_def.h index 15680c3f49704..ab1cfc92dbeb1 100644 --- a/drivers/gpu/drm/amd/include/mes_v11_api_def.h +++ b/drivers/gpu/drm/amd/include/mes_v11_api_def.h @@ -238,7 +238,8 @@ union MESAPI_SET_HW_RESOURCES { uint32_t enable_mes_sch_stb_log : 1; uint32_t limit_single_process : 1; uint32_t is_strix_tmz_wa_enabled :1; - uint32_t reserved : 13; + uint32_t enable_lr_compute_wa : 1; + uint32_t reserved : 12; }; uint32_t uint32_t_all; }; diff --git a/drivers/gpu/drm/amd/include/mes_v12_api_def.h b/drivers/gpu/drm/amd/include/mes_v12_api_def.h index c04bd351b2505..69611c7e30e35 100644 --- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h +++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h @@ -287,7 +287,8 @@ union MESAPI_SET_HW_RESOURCES { uint32_t limit_single_process : 1; uint32_t unmapped_doorbell_handling: 2; uint32_t enable_mes_fence_int: 1; - uint32_t reserved : 10; + uint32_t enable_lr_compute_wa : 1; + uint32_t reserved : 9; }; uint32_t uint32_all; }; From ccc758b41edc3806123430344f7f43b76d90d214 Mon Sep 17 00:00:00 2001 From: Sonny Jiang Date: Thu, 18 Sep 2025 12:34:48 -0400 Subject: [PATCH 2043/2653] drm/amdgpu: Update amdgpu_vcn5_fw_shared for vcn_5_0_1 Align vcn5_fw_shared structure with FW Signed-off-by: Sonny Jiang Reviewed-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index bebfc2b34afe6..dc8a17bcc3c8d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -501,7 +501,7 @@ struct amdgpu_vcn5_fw_shared { struct amdgpu_fw_shared_rb_setup rb_setup; struct amdgpu_fw_shared_smu_interface_info smu_dpm_interface; struct amdgpu_fw_shared_drm_key_wa drm_key_wa; - uint8_t pad3[9]; + uint8_t pad3[404]; }; #define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80 From cc1d31dd78457ebdd515f7eb03f3a10f7c239117 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Mon, 15 Sep 2025 11:22:52 -0400 Subject: [PATCH 2044/2653] drm/amd/display: Disable stutter when programming watermarks on dcn32 [WHY&HOW] Reprogramming watermarks with stutter allowed can cause instability on some ASICs. Disable it prior to raising watermarks (prepare bandwidth), then re-enable after lowering (optimize bandwidth). Reviewed-by: Alvin Lee Signed-off-by: Dillon Varone Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../display/dc/hubbub/dcn32/dcn32_hubbub.c | 37 ++++++++++++++++--- .../dc/resource/dcn32/dcn32_resource.c | 1 + .../dc/resource/dcn32/dcn32_resource.h | 3 +- 4 files changed, 36 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 6d3eec3adb3db..d80de2f4d171f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1166,6 +1166,7 @@ struct dc_debug_options { unsigned int auxless_alpm_lfps_t1t2_us; short auxless_alpm_lfps_t1t2_offset_us; bool enable_pg_cntl_debug_logs; + bool disable_stutter_for_wm_program; }; diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c index 92957398ac0a6..3b71bfaca2914 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c @@ -28,6 +28,7 @@ #include "dcn32_hubbub.h" #include "dm_services.h" #include "reg_helper.h" +#include "dal_asic_id.h" #define CTX \ @@ -72,6 +73,14 @@ static void dcn32_init_crb(struct hubbub *hubbub) REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x47F); } +static void hubbub32_set_sdp_control(struct hubbub *hubbub, bool dc_control) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + + REG_UPDATE(DCHUBBUB_SDPIF_CFG0, + SDPIF_PORT_CONTROL, dc_control); +} + void hubbub32_set_request_limit(struct hubbub *hubbub, int memory_channel_count, int words_per_channel) { struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); @@ -754,8 +763,17 @@ static bool hubbub32_program_watermarks( unsigned int refclk_mhz, bool safe_to_lower) { + struct dc *dc = hubbub->ctx->dc; bool wm_pending = false; + if (!safe_to_lower && dc->debug.disable_stutter_for_wm_program && + (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev) || + ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev))) { + /* before raising watermarks, SDP control give to DF, stutter must be disabled */ + hubbub32_set_sdp_control(hubbub, false); + hubbub1_allow_self_refresh_control(hubbub, false); + } + if (hubbub32_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) wm_pending = true; @@ -786,10 +804,20 @@ static bool hubbub32_program_watermarks( REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);*/ - if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter) - hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); + if (safe_to_lower) { + /* after lowering watermarks, stutter setting is restored, SDP control given to DC */ + hubbub1_allow_self_refresh_control(hubbub, !dc->debug.disable_stutter); + + if (dc->debug.disable_stutter_for_wm_program && + (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev) || + ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev))) { + hubbub32_set_sdp_control(hubbub, true); + } + } else if (dc->debug.disable_stutter) { + hubbub1_allow_self_refresh_control(hubbub, !dc->debug.disable_stutter); + } - hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow); + hubbub32_force_usr_retraining_allow(hubbub, dc->debug.force_usr_allow); return wm_pending; } @@ -974,8 +1002,7 @@ void hubbub32_init(struct hubbub *hubbub) ignore the "df_pre_cstate_req" from the SDP port control. only the DCN will determine when to connect the SDP port */ - REG_UPDATE(DCHUBBUB_SDPIF_CFG0, - SDPIF_PORT_CONTROL, 1); + hubbub32_set_sdp_control(hubbub, true); /*Set SDP's max outstanding request to 512 must set the register back to 0 (max outstanding = 256) in zero frame buffer mode*/ REG_UPDATE(DCHUBBUB_SDPIF_CFG1, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index 8f80ccb846d76..3965a7f1b64b7 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -739,6 +739,7 @@ static const struct dc_debug_options debug_defaults_drv = { .fpo_vactive_min_active_margin_us = 200, .fpo_vactive_max_blank_us = 1000, .enable_legacy_fast_update = false, + .disable_stutter_for_wm_program = true }; static struct dce_aux *dcn32_aux_engine_create( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h index 20d7145960212..99f0432288b44 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h @@ -1230,7 +1230,8 @@ unsigned int dcn32_get_max_hw_cursor_size(const struct dc *dc, SR(DCHUBBUB_ARB_MALL_CNTL), \ SR(DCN_VM_FAULT_ADDR_MSB), SR(DCN_VM_FAULT_ADDR_LSB), \ SR(DCN_VM_FAULT_CNTL), SR(DCN_VM_FAULT_STATUS), \ - SR(SDPIF_REQUEST_RATE_LIMIT) + SR(SDPIF_REQUEST_RATE_LIMIT), \ + SR(DCHUBBUB_SDPIF_CFG0) /* DCCG */ From 0b1e4dcf50635695b197d5d0c7d79d0ae42e0ea0 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Mon, 15 Sep 2025 11:35:37 -0400 Subject: [PATCH 2045/2653] drm/amd/display: Add missing post flip calls [WHY&HOW] dc_post_update_surfaces_to_stream needs to be called after a full update completes in order to optimize clocks and watermarks for power. Add missing calls before idle entry is requested to ensure optimal power. Reviewed-by: Aurabindo Pillai Signed-off-by: Dillon Varone Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 8 ++++++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ec8000b541e14..6f3517eaf829a 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -418,8 +418,7 @@ static inline bool update_planes_and_stream_adapter(struct dc *dc, /* * Previous frame finished and HW is ready for optimization. */ - if (update_type == UPDATE_TYPE_FAST) - dc_post_update_surfaces_to_stream(dc); + dc_post_update_surfaces_to_stream(dc); return dc_update_planes_and_stream(dc, array_of_surface_update, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 67c96a85880b0..0aafee3f8f20b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -218,8 +218,10 @@ static void amdgpu_dm_idle_worker(struct work_struct *work) break; } - if (idle_work->enable) + if (idle_work->enable) { + dc_post_update_surfaces_to_stream(idle_work->dm->dc); dc_allow_idle_optimizations(idle_work->dm->dc, true); + } mutex_unlock(&idle_work->dm->dc_lock); } idle_work->dm->idle_workqueue->running = false; @@ -273,8 +275,10 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work) vblank_work->acrtc->dm_irq_params.allow_sr_entry); } - if (dm->active_vblank_irq_count == 0) + if (dm->active_vblank_irq_count == 0) { + dc_post_update_surfaces_to_stream(dm->dc); dc_allow_idle_optimizations(dm->dc, true); + } mutex_unlock(&dm->dc_lock); From 5d285eedc567936272562a1c3e5d690bc28b9e14 Mon Sep 17 00:00:00 2001 From: Karthi Kandasamy Date: Wed, 3 Sep 2025 14:16:27 +0200 Subject: [PATCH 2046/2653] drm/amd/display: Add AVI infoframe copy in copy_stream_update_to_stream [WHY] Ensure AVI infoframe updates from stream updates are applied to the active stream so OS overrides are not lost. [HOW] Copy avi_infopacket to stream when valid flag is set. Follow existing infopacket copy pattern and perform a basic validity check before assignment. Reviewed-by: Aric Cyr Signed-off-by: Karthi Kandasamy Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++++++- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 ++++++ drivers/gpu/drm/amd/display/dc/dc_stream.h | 3 +++ 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 8cab7cf900b18..c35ec2bc582a4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3313,6 +3313,9 @@ static void copy_stream_update_to_stream(struct dc *dc, if (update->adaptive_sync_infopacket) stream->adaptive_sync_infopacket = *update->adaptive_sync_infopacket; + if (update->avi_infopacket) + stream->avi_infopacket = *update->avi_infopacket; + if (update->dither_option) stream->dither_option = *update->dither_option; @@ -3608,7 +3611,8 @@ static void commit_planes_do_stream_update(struct dc *dc, stream_update->vsp_infopacket || stream_update->hfvsif_infopacket || stream_update->adaptive_sync_infopacket || - stream_update->vtem_infopacket) { + stream_update->vtem_infopacket || + stream_update->avi_infopacket) { resource_build_info_frame(pipe_ctx); dc->hwss.update_info_frame(pipe_ctx); @@ -5080,6 +5084,7 @@ static bool full_update_required(struct dc *dc, stream_update->hfvsif_infopacket || stream_update->vtem_infopacket || stream_update->adaptive_sync_infopacket || + stream_update->avi_infopacket || stream_update->dpms_off || stream_update->allow_freesync || stream_update->vrr_active_variable || diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index cbca3c67f439a..bc5dedf5f60c3 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -4410,8 +4410,14 @@ static void set_avi_info_frame( unsigned int fr_ind = pipe_ctx->stream->timing.fr_index; enum dc_timing_3d_format format; + if (stream->avi_infopacket.valid) { + *info_packet = stream->avi_infopacket; + return; + } + memset(&hdmi_info, 0, sizeof(union hdmi_info_packet)); + color_space = pipe_ctx->stream->output_color_space; if (color_space == COLOR_SPACE_UNKNOWN) color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 5fc6fea211de3..76cf9fdedab0e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -203,6 +203,7 @@ struct dc_stream_state { struct dc_info_packet hfvsif_infopacket; struct dc_info_packet vtem_infopacket; struct dc_info_packet adaptive_sync_infopacket; + struct dc_info_packet avi_infopacket; uint8_t dsc_packed_pps[128]; struct rect src; /* composition area */ struct rect dst; /* stream addressable area */ @@ -335,6 +336,8 @@ struct dc_stream_update { struct dc_info_packet *hfvsif_infopacket; struct dc_info_packet *vtem_infopacket; struct dc_info_packet *adaptive_sync_infopacket; + struct dc_info_packet *avi_infopacket; + bool *dpms_off; bool integer_scaling_update; bool *allow_freesync; From 13947473b1642ef9e7238a285cc1e431c9991cdc Mon Sep 17 00:00:00 2001 From: Paul Hsieh Date: Fri, 5 Sep 2025 11:38:21 +0800 Subject: [PATCH 2047/2653] drm/amd/display: Add monitor patch to read psr cap again MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [Why & How] According to the vendor’s requirement, after each OUI write, the PSR cap must be read; otherwise, the vendor will default to using PSRSU. But its PSR cap indicates that it only supports PSR1. Reviewed-by: Wenjing Liu Signed-off-by: Paul Hsieh Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc_types.h | 1 + .../dc/link/protocols/link_edp_panel_control.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 619834a328a37..b5aa03a3e39cf 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -1217,6 +1217,7 @@ struct dc_panel_config { bool rc_disable; bool rc_allow_static_screen; bool rc_allow_fullscreen_VPB; + bool read_psrcap_again; unsigned int replay_enable_option; } psr; /* ABM */ diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 8b7b87b21c2e9..5e806edbb9f61 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -703,6 +703,20 @@ bool edp_setup_psr(struct dc_link *link, if (!link) return false; + /* This is a workaround: some vendors require the source to + * read the PSR cap; otherwise, the vendor's PSR feature will + * fall back to its default behavior, causing a misconfiguration + * of this feature. + */ + if (link->panel_config.psr.read_psrcap_again) { + dm_helpers_dp_read_dpcd( + link->ctx, + link, + DP_PSR_SUPPORT, + &link->dpcd_caps.psr_info.psr_version, + sizeof(link->dpcd_caps.psr_info.psr_version)); + } + //Clear PSR cfg memset(&psr_configuration, 0, sizeof(psr_configuration)); dm_helpers_dp_write_dpcd( From 03f8a726bc45f042adf647f01de18947404a01bf Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 4 Sep 2025 13:49:35 -0500 Subject: [PATCH 2048/2653] drm/amd/display: Handle interpolation for first data point [Why] If the first data point for a custom brightness curve is not 0% luminance then the first few luminance values will be ignored. [How] Check signal is below first data point and if so do linear interpolation to 0 instead. Reviewed-by: Alex Hung Signed-off-by: Mario Limonciello Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6f3517eaf829a..cf71dd27498de 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4886,6 +4886,16 @@ static void convert_custom_brightness(const struct amdgpu_dm_backlight_caps *cap if (!caps->data_points) return; + /* + * Handle the case where brightness is below the first data point + * Interpolate between (0,0) and (first_signal, first_lum) + */ + if (brightness < caps->luminance_data[0].input_signal) { + lum = DIV_ROUND_CLOSEST(caps->luminance_data[0].luminance * brightness, + caps->luminance_data[0].input_signal); + goto scale; + } + left = 0; right = caps->data_points - 1; while (left <= right) { From 2d963ddcac850ea559d59a5211ac143358ad6d89 Mon Sep 17 00:00:00 2001 From: Lo-an Chen Date: Mon, 25 Aug 2025 18:16:24 +0800 Subject: [PATCH 2049/2653] drm/amd/display: Init dispclk from bootup clock for DCN314 [Why] Driver does not pick up and save vbios's clocks during init clocks, the dispclk in clk_mgr will keep 0 until the first update clocks. In some cases, OS changes the timing in the second set mode (lower the pixel clock), causing the driver to lower the dispclk in prepare bandwidth, which is illegal and causes grey screen. [How] 1. Dump and save the vbios's clocks, and init the dispclk in dcn314_init_clocks. 2. Fix the condition in dcn314_update_clocks, regarding a 0kHz value. Reviewed-by: Charlene Liu Signed-off-by: Lo-an Chen Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- .../dc/clk_mgr/dcn314/dcn314_clk_mgr.c | 142 +++++++++++++++++- .../dc/clk_mgr/dcn314/dcn314_clk_mgr.h | 5 + .../dc/resource/dcn314/dcn314_resource.c | 1 + 3 files changed, 143 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c index 790bbd8235b14..9e63fa72101cc 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c @@ -77,6 +77,7 @@ static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, #undef DC_LOGGER #define DC_LOGGER \ clk_mgr->base.base.ctx->logger + #define regCLK1_CLK_PLL_REQ 0x0237 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0 @@ -87,8 +88,70 @@ static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L +#define regCLK1_CLK0_DFS_CNTL 0x0269 +#define regCLK1_CLK0_DFS_CNTL_BASE_IDX 0 +#define regCLK1_CLK1_DFS_CNTL 0x026c +#define regCLK1_CLK1_DFS_CNTL_BASE_IDX 0 +#define regCLK1_CLK2_DFS_CNTL 0x026f +#define regCLK1_CLK2_DFS_CNTL_BASE_IDX 0 +#define regCLK1_CLK3_DFS_CNTL 0x0272 +#define regCLK1_CLK3_DFS_CNTL_BASE_IDX 0 +#define regCLK1_CLK4_DFS_CNTL 0x0275 +#define regCLK1_CLK4_DFS_CNTL_BASE_IDX 0 +#define regCLK1_CLK5_DFS_CNTL 0x0278 +#define regCLK1_CLK5_DFS_CNTL_BASE_IDX 0 + +#define regCLK1_CLK0_CURRENT_CNT 0x02fb +#define regCLK1_CLK0_CURRENT_CNT_BASE_IDX 0 +#define regCLK1_CLK1_CURRENT_CNT 0x02fc +#define regCLK1_CLK1_CURRENT_CNT_BASE_IDX 0 +#define regCLK1_CLK2_CURRENT_CNT 0x02fd +#define regCLK1_CLK2_CURRENT_CNT_BASE_IDX 0 +#define regCLK1_CLK3_CURRENT_CNT 0x02fe +#define regCLK1_CLK3_CURRENT_CNT_BASE_IDX 0 +#define regCLK1_CLK4_CURRENT_CNT 0x02ff +#define regCLK1_CLK4_CURRENT_CNT_BASE_IDX 0 +#define regCLK1_CLK5_CURRENT_CNT 0x0300 +#define regCLK1_CLK5_CURRENT_CNT_BASE_IDX 0 + +#define regCLK1_CLK0_BYPASS_CNTL 0x028a +#define regCLK1_CLK0_BYPASS_CNTL_BASE_IDX 0 +#define regCLK1_CLK1_BYPASS_CNTL 0x0293 +#define regCLK1_CLK1_BYPASS_CNTL_BASE_IDX 0 #define regCLK1_CLK2_BYPASS_CNTL 0x029c #define regCLK1_CLK2_BYPASS_CNTL_BASE_IDX 0 +#define regCLK1_CLK3_BYPASS_CNTL 0x02a5 +#define regCLK1_CLK3_BYPASS_CNTL_BASE_IDX 0 +#define regCLK1_CLK4_BYPASS_CNTL 0x02ae +#define regCLK1_CLK4_BYPASS_CNTL_BASE_IDX 0 +#define regCLK1_CLK5_BYPASS_CNTL 0x02b7 +#define regCLK1_CLK5_BYPASS_CNTL_BASE_IDX 0 + +#define regCLK1_CLK0_DS_CNTL 0x0283 +#define regCLK1_CLK0_DS_CNTL_BASE_IDX 0 +#define regCLK1_CLK1_DS_CNTL 0x028c +#define regCLK1_CLK1_DS_CNTL_BASE_IDX 0 +#define regCLK1_CLK2_DS_CNTL 0x0295 +#define regCLK1_CLK2_DS_CNTL_BASE_IDX 0 +#define regCLK1_CLK3_DS_CNTL 0x029e +#define regCLK1_CLK3_DS_CNTL_BASE_IDX 0 +#define regCLK1_CLK4_DS_CNTL 0x02a7 +#define regCLK1_CLK4_DS_CNTL_BASE_IDX 0 +#define regCLK1_CLK5_DS_CNTL 0x02b0 +#define regCLK1_CLK5_DS_CNTL_BASE_IDX 0 + +#define regCLK1_CLK0_ALLOW_DS 0x0284 +#define regCLK1_CLK0_ALLOW_DS_BASE_IDX 0 +#define regCLK1_CLK1_ALLOW_DS 0x028d +#define regCLK1_CLK1_ALLOW_DS_BASE_IDX 0 +#define regCLK1_CLK2_ALLOW_DS 0x0296 +#define regCLK1_CLK2_ALLOW_DS_BASE_IDX 0 +#define regCLK1_CLK3_ALLOW_DS 0x029f +#define regCLK1_CLK3_ALLOW_DS_BASE_IDX 0 +#define regCLK1_CLK4_ALLOW_DS 0x02a8 +#define regCLK1_CLK4_ALLOW_DS_BASE_IDX 0 +#define regCLK1_CLK5_ALLOW_DS 0x02b1 +#define regCLK1_CLK5_ALLOW_DS_BASE_IDX 0 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT 0x10 @@ -185,6 +248,8 @@ void dcn314_init_clocks(struct clk_mgr *clk_mgr) { struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr); uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; + struct clk_mgr_dcn314 *clk_mgr_dcn314 = TO_CLK_MGR_DCN314(clk_mgr_int); + struct clk_log_info log_info = {0}; memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); // Assumption is that boot state always supports pstate @@ -200,6 +265,9 @@ void dcn314_init_clocks(struct clk_mgr *clk_mgr) dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr->dprefclk_khz); else clk_mgr->dp_dto_source_clock_in_khz = clk_mgr->dprefclk_khz; + + dcn314_dump_clk_registers(&clk_mgr->boot_snapshot, &clk_mgr_dcn314->base.base, &log_info); + clk_mgr->clks.dispclk_khz = clk_mgr->boot_snapshot.dispclk * 1000; } void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, @@ -218,6 +286,8 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, if (dc->work_arounds.skip_clock_update) return; + display_count = dcn314_get_active_display_cnt_wa(dc, context); + /* * if it is safe to lower, but we are already in the lower state, we don't have to do anything * also if safe to lower is false, we just go in the higher state @@ -236,7 +306,6 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, } /* check that we're not already in lower */ if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { - display_count = dcn314_get_active_display_cnt_wa(dc, context); /* if we can go lower, go lower */ if (display_count == 0) { union display_idle_optimization_u idle_info = { 0 }; @@ -293,11 +362,19 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, update_dppclk = true; } - if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { + if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) && + (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) { + int requested_dispclk_khz = new_clocks->dispclk_khz; + dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); + /* Clamp the requested clock to PMFW based on their limit. */ + if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz) + requested_dispclk_khz = dc->debug.min_disp_clk_khz; + + dcn314_smu_set_dispclk(clk_mgr, requested_dispclk_khz); clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; - dcn314_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); + dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false); update_dispclk = true; @@ -385,10 +462,65 @@ bool dcn314_are_clock_states_equal(struct dc_clocks *a, return true; } -static void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, + +static void dcn314_dump_clk_registers_internal(struct dcn35_clk_internal *internal, struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + + // read dtbclk + internal->CLK1_CLK4_CURRENT_CNT = REG_READ(CLK1_CLK4_CURRENT_CNT); + internal->CLK1_CLK4_BYPASS_CNTL = REG_READ(CLK1_CLK4_BYPASS_CNTL); + + // read dcfclk + internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT); + internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL); + + // read dcf deep sleep divider + internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); + internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS); + + // read dppclk + internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT); + internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL); + + // read dprefclk + internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT); + internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL); + + // read dispclk + internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT); + internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL); +} + +void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) { - return; + + struct dcn35_clk_internal internal = {0}; + + dcn314_dump_clk_registers_internal(&internal, clk_mgr_base); + + regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; + regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10; + regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS; + regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10; + regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10; + regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; + regs_and_bypass->dtbclk = internal.CLK1_CLK4_CURRENT_CNT / 10; + + regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007; + if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4) + regs_and_bypass->dppclk_bypass = 0; + regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007; + if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4) + regs_and_bypass->dcfclk_bypass = 0; + regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007; + if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4) + regs_and_bypass->dispclk_bypass = 0; + regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007; + if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4) + regs_and_bypass->dprefclk_bypass = 0; + } static struct clk_bw_params dcn314_bw_params = { diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h index 002c28e807208..0577eb527bc36 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h @@ -65,4 +65,9 @@ void dcn314_clk_mgr_construct(struct dc_context *ctx, void dcn314_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int); + +void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, + struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info); + + #endif //__DCN314_CLK_MGR_H__ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c index 663c49cce4aa3..d4917a35b991a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c @@ -927,6 +927,7 @@ static const struct dc_debug_options debug_defaults_drv = { .enable_legacy_fast_update = true, .using_dml2 = false, .disable_dsc_power_gate = true, + .min_disp_clk_khz = 100000, }; static const struct dc_panel_config panel_config_defaults = { From a9c015c22028a77b58c2068ffc22f56f4eb96198 Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Tue, 9 Sep 2025 14:15:05 -0400 Subject: [PATCH 2050/2653] drm/amd/display: Enable DTM v3 on dGPUs with DCN 3.1+ [Why&How] Right now, only selected APUs have enabled DTM v3, which allows to use newer firmware for content protection. We want to enable it on the dGPUs starting with DCN 3.2 Reviewed-by: Aurabindo Pillai Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index 0b9262f94cd9b..9601dfa1651a0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -789,14 +789,18 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct mod_hdcp_ddc_funcs *ddc_funcs = &config->ddc.funcs; config->psp.handle = &adev->psp; - if (dc->ctx->dce_version == DCN_VERSION_3_1 || + if (dc->ctx->dce_version == DCN_VERSION_3_1 || dc->ctx->dce_version == DCN_VERSION_3_14 || dc->ctx->dce_version == DCN_VERSION_3_15 || - dc->ctx->dce_version == DCN_VERSION_3_5 || + dc->ctx->dce_version == DCN_VERSION_3_16 || + dc->ctx->dce_version == DCN_VERSION_3_2 || + dc->ctx->dce_version == DCN_VERSION_3_21 || + dc->ctx->dce_version == DCN_VERSION_3_5 || dc->ctx->dce_version == DCN_VERSION_3_51 || - dc->ctx->dce_version == DCN_VERSION_3_6 || - dc->ctx->dce_version == DCN_VERSION_3_16) + dc->ctx->dce_version == DCN_VERSION_3_6 || + dc->ctx->dce_version == DCN_VERSION_4_01) config->psp.caps.dtm_v3_supported = 1; + config->ddc.handle = dc_get_link_at_index(dc, i); ddc_funcs->write_i2c = lp_write_i2c; From 787a67cc100de174601ad085893538b80ce8bd92 Mon Sep 17 00:00:00 2001 From: Sridevi Arvindekar Date: Wed, 10 Sep 2025 11:04:07 -0400 Subject: [PATCH 2051/2653] drm/amd/display: Fix for test crash due to power gating [Why/How] Call power gating routine only if it is defined. Reviewed-by: Alvin Lee Signed-off-by: Sridevi Arvindekar Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 417f2679723ee..95af58cbb92a5 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -3131,7 +3131,8 @@ void dcn20_fpga_init_hw(struct dc *dc) res_pool->dccg->funcs->dccg_init(res_pool->dccg); //Enable ability to power gate / don't force power on permanently - hws->funcs.enable_power_gating_plane(hws, true); + if (hws->funcs.enable_power_gating_plane) + hws->funcs.enable_power_gating_plane(hws, true); // Specific to FPGA dccg and registers REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); From 79da33414c583b961e851e7c416d123b639429b0 Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Tue, 9 Sep 2025 16:03:08 -0400 Subject: [PATCH 2052/2653] drm/amd/display: Use mpc.preblend flag to indicate preblend [Description] Modifications in per asic capability means mpc.preblend flag should be used to indicate preblend. Update relevant paths to use this flag. Reviewed-by: Dillon Varone Signed-off-by: Alvin Lee Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index c7387af725d6a..b0ef157f13339 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -821,7 +821,7 @@ int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state); const struct drm_color_lut *shaper = NULL, *lut3d = NULL; uint32_t exp_size, size, dim_size = MAX_COLOR_3DLUT_SIZE; - bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut; + bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend; /* shaper LUT is only available if 3D LUT color caps */ exp_size = has_3dlut ? MAX_COLOR_LUT_ENTRIES : 0; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 8b7325d1cabec..e246c1081c71b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1699,7 +1699,7 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, drm_object_attach_property(&plane->base, dm->adev->mode_info.plane_ctm_property, 0); - if (dpp_color_caps.hw_3d_lut) { + if (dpp_color_caps.hw_3d_lut || dm->dc->caps.color.mpc.preblend) { drm_object_attach_property(&plane->base, mode_info.plane_shaper_lut_property, 0); drm_object_attach_property(&plane->base, From a5a50a217b575fb17524a14bc9019f5cbf275dc0 Mon Sep 17 00:00:00 2001 From: Allen Li Date: Fri, 5 Sep 2025 16:58:38 +0800 Subject: [PATCH 2053/2653] drm/amd/display: Add fast sync field in ultra sleep more for DMUB [Why&How] We need to inform DMUB whether fast sync in ultra sleep mode is supported, so that it can disable desync error detection when the it is not enabled. This helps prevent unexpected desync errors when transitioning out of ultra sleep mode. Add fast sync in ultra sleep mode field in replay copy setting command. Reviewed-by: Robin Chen Reviewed-by: Nicholas Kazlauskas Signed-off-by: Allen Li Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c | 1 + drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c index 9e2a473a88521..f9542edff14bb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c @@ -169,6 +169,7 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub, copy_settings_data->max_deviation_line = link->dpcd_caps.pr_info.max_deviation_line; copy_settings_data->smu_optimizations_en = link->replay_settings.replay_smu_opt_enable; copy_settings_data->replay_timing_sync_supported = link->replay_settings.config.replay_timing_sync_supported; + copy_settings_data->replay_support_fast_resync_in_ultra_sleep_mode = link->replay_settings.config.replay_support_fast_resync_in_ultra_sleep_mode; copy_settings_data->debug.bitfields.enable_ips_visual_confirm = dc->dc->debug.enable_ips_visual_confirm; diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 02a4a20e35601..ef8510bab32c3 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -4142,10 +4142,14 @@ struct dmub_cmd_replay_copy_settings_data { * @hpo_link_enc_inst: HPO link encoder instance */ uint8_t hpo_link_enc_inst; + /** + * Determines if fast sync in ultra sleep mode is enabled/disabled. + */ + uint8_t replay_support_fast_resync_in_ultra_sleep_mode; /** * @pad: Align structure to 4 byte boundary. */ - uint8_t pad[2]; + uint8_t pad[1]; }; From 9baadd3028956f903d83ba35468b1f3608250272 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Fri, 22 Aug 2025 13:23:18 -0400 Subject: [PATCH 2054/2653] drm/amd/display: Isolate dcn401 SMU functions [WHY&HOW] SMU interfaces are not backwards and forwards compatible, so they should be isolated per version. Reviewed-by: Alvin Lee Signed-off-by: Dillon Varone Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- .../dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 26 ++-- .../clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c | 118 ++++++++++++++++++ .../clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h | 10 +- 3 files changed, 140 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c index 47461f249e83b..306016c1f109c 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c @@ -162,7 +162,7 @@ static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e c unsigned int i; char *entry_i = (char *)entry_0; - uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF); + uint32_t ret = dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF); if (ret & (1 << 31)) /* fine-grained, only min and max */ @@ -174,7 +174,7 @@ static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e c /* if the initial message failed, num_levels will be 0 */ for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) { - *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF); + *((unsigned int *)entry_i) = (dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF); entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); } } @@ -231,20 +231,20 @@ void dcn401_init_clocks(struct clk_mgr *clk_mgr_base) clk_mgr->smu_present = false; clk_mgr->dpm_present = false; - if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver)) + if (!clk_mgr_base->force_smu_not_present && dcn401_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver)) clk_mgr->smu_present = true; if (!clk_mgr->smu_present) return; - dcn30_smu_check_driver_if_version(clk_mgr); - dcn30_smu_check_msg_header_version(clk_mgr); + dcn401_smu_check_driver_if_version(clk_mgr); + dcn401_smu_check_msg_header_version(clk_mgr); /* DCFCLK */ dcn401_init_single_clock(clk_mgr, PPCLK_DCFCLK, &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, &num_entries_per_clk->num_dcfclk_levels); - clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK); + clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK); if (num_entries_per_clk->num_dcfclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz == clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dcfclk_levels - 1].dcfclk_mhz) clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = 0; @@ -253,7 +253,7 @@ void dcn401_init_clocks(struct clk_mgr *clk_mgr_base) dcn401_init_single_clock(clk_mgr, PPCLK_SOCCLK, &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, &num_entries_per_clk->num_socclk_levels); - clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK); + clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK); if (num_entries_per_clk->num_socclk_levels && clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz == clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_socclk_levels - 1].socclk_mhz) clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = 0; @@ -263,7 +263,7 @@ void dcn401_init_clocks(struct clk_mgr *clk_mgr_base) dcn401_init_single_clock(clk_mgr, PPCLK_DTBCLK, &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, &num_entries_per_clk->num_dtbclk_levels); - clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DTBCLK); + clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DTBCLK); if (num_entries_per_clk->num_dtbclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz == clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dtbclk_levels - 1].dtbclk_mhz) clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = 0; @@ -273,7 +273,7 @@ void dcn401_init_clocks(struct clk_mgr *clk_mgr_base) dcn401_init_single_clock(clk_mgr, PPCLK_DISPCLK, &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, &num_entries_per_clk->num_dispclk_levels); - clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK); + clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK); if (num_entries_per_clk->num_dispclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz == clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dispclk_levels - 1].dispclk_mhz) clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 0; @@ -1318,8 +1318,8 @@ static void dcn401_notify_wm_ranges(struct clk_mgr *clk_mgr_base) table->Watermarks.WatermarkRow[i].WmSetting = i; table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type; } - dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32); - dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF); + dcn401_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32); + dcn401_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF); dcn401_smu_transfer_wm_table_dram_2_smu(clk_mgr); } @@ -1390,7 +1390,7 @@ static void dcn401_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz; } - clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK); + clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK); if (num_entries_per_clk->num_memclk_levels && clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz == clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz) clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = 0; @@ -1399,7 +1399,7 @@ static void dcn401_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) dcn401_init_single_clock(clk_mgr, PPCLK_FCLK, &clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz, &num_entries_per_clk->num_fclk_levels); - clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK); + clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn401_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK); if (num_entries_per_clk->num_fclk_levels && clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz == clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_fclk_levels - 1].fclk_mhz) clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = 0; diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c index 21c35528f61f3..347a0d66d653f 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c @@ -139,6 +139,59 @@ static bool dcn401_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mg return false; } +bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version) +{ + smu_print("SMU Get SMU version\n"); + + if (dcn401_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_GetSmuVersion, 0, version)) { + + smu_print("SMU version: %d\n", *version); + + return true; + } + + return false; +} + +/* Message output should match SMU11_DRIVER_IF_VERSION in smu11_driver_if.h */ +bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr) +{ + uint32_t response = 0; + + smu_print("SMU Check driver if version\n"); + + if (dcn401_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_GetDriverIfVersion, 0, &response)) { + + smu_print("SMU driver if version: %d\n", response); + + if (response == SMU14_DRIVER_IF_VERSION) + return true; + } + + return false; +} + +/* Message output should match DALSMC_VERSION in dalsmc.h */ +bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr) +{ + uint32_t response = 0; + + smu_print("SMU Check msg header version\n"); + + if (dcn401_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_GetMsgHeaderVersion, 0, &response)) { + + smu_print("SMU msg header version: %d\n", response); + + if (response == DALSMC_VERSION) + return true; + } + + return false; +} + void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support) { smu_print("FCLK P-state support value is : %d\n", support); @@ -163,6 +216,22 @@ void dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsi smu_print("Numways for SubVP : %d\n", num_ways); } +void dcn401_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high) +{ + smu_print("SMU Set DRAM addr high: %d\n", addr_high); + + dcn401_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_SetDalDramAddrHigh, addr_high, NULL); +} + +void dcn401_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low) +{ + smu_print("SMU Set DRAM addr low: %d\n", addr_low); + + dcn401_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_SetDalDramAddrLow, addr_low, NULL); +} + void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) { smu_print("SMU Transfer WM table DRAM 2 SMU\n"); @@ -348,3 +417,52 @@ unsigned int dcn401_smu_get_num_of_umc_channels(struct clk_mgr_internal *clk_mgr return response; } + +/* + * Frequency in MHz returned in lower 16 bits for valid DPM level + * + * Call with dpm_level = 0xFF to query features, return value will be: + * Bits 7:0 - number of DPM levels + * Bit 28 - 1 = auto DPM on + * Bit 29 - 1 = sweep DPM on + * Bit 30 - 1 = forced DPM on + * Bit 31 - 0 = discrete, 1 = fine-grained + * + * With fine-grained DPM, only min and max frequencies will be reported + * + * Returns 0 on failure + */ +unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level) +{ + uint32_t response = 0; + + /* bits 23:16 for clock type, lower 8 bits for DPM level */ + uint32_t param = (clk << 16) | dpm_level; + + smu_print("SMU Get dpm freq by index: clk = %d, dpm_level = %d\n", clk, dpm_level); + + dcn401_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_GetDpmFreqByIndex, param, &response); + + smu_print("SMU dpm freq: %d MHz\n", response); + + return response; +} + +/* Returns the max DPM frequency in DC mode in MHz, 0 on failure */ +unsigned int dcn401_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk) +{ + uint32_t response = 0; + + /* bits 23:16 for clock type */ + uint32_t param = clk << 16; + + smu_print("SMU Get DC mode max DPM freq: clk = %d\n", clk); + + dcn401_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_GetDcModeMaxDpmFreq, param, &response); + + smu_print("SMU DC mode max DMP freq: %d MHz\n", response); + + return response; +} diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h index e02eb1294b378..4f5ac603e8223 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h @@ -7,11 +7,17 @@ #include "os_types.h" #include "core_types.h" -#include "dcn32/dcn32_clk_mgr_smu_msg.h" +struct clk_mgr_internal; + +bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version); +bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr); +bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr); void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support); void dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support); void dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways); +void dcn401_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high); +void dcn401_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low); void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); void dcn401_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr); unsigned int dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz); @@ -29,5 +35,7 @@ bool dcn401_smu_set_subvp_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr, void dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz); void dcn401_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays); unsigned int dcn401_smu_get_num_of_umc_channels(struct clk_mgr_internal *clk_mgr); +unsigned int dcn401_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk); +unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level); #endif /* __DCN401_CLK_MGR_SMU_MSG_H_ */ From fbdafc66dac2cb9ece683a85e39d19ad1460cb79 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Wed, 10 Sep 2025 10:55:48 -0400 Subject: [PATCH 2055/2653] drm/amd/display: Refactor SMU tracing [WHY&HOW] Add new tracing and performance measurements for SMU messaging. Reviewed-by: Alvin Lee Signed-off-by: Dillon Varone Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 4 ++-- .../display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c | 2 +- .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c | 5 +++-- .../dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c | 12 ++++++++---- drivers/gpu/drm/amd/display/dc/dm_services.h | 11 ++++++----- 5 files changed, 20 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c index 132de4071efd4..8550d5e8b7530 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c @@ -53,11 +53,11 @@ void dm_perf_trace_timestamp(const char *func_name, unsigned int line, struct dc func_name, line); } -void dm_trace_smu_msg(uint32_t msg_id, uint32_t param_in, struct dc_context *ctx) +void dm_trace_smu_enter(uint32_t msg_id, uint32_t param_in, unsigned int delay, struct dc_context *ctx) { } -void dm_trace_smu_delay(uint32_t delay, struct dc_context *ctx) +void dm_trace_smu_exit(bool success, uint32_t response, struct dc_context *ctx) { } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c index 3253115a153dd..827bc2431d5d8 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c @@ -69,7 +69,7 @@ static uint32_t dcn30_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, un /* handle DALSMC_Result_CmdRejectedBusy? */ - TRACE_SMU_DELAY(delay_us * (initial_max_retries - max_retries), clk_mgr->base.ctx); + TRACE_SMU_MSG_DELAY(0, 0, delay_us * (initial_max_retries - max_retries), clk_mgr->base.ctx); return reg; } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c index cf2d35363e8b9..5d80fdf63ffcd 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c @@ -63,7 +63,8 @@ static uint32_t dcn32_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, un udelay(delay_us); } while (max_retries--); - TRACE_SMU_DELAY(delay_us * (initial_max_retries - max_retries), clk_mgr->base.ctx); + TRACE_SMU_MSG_DELAY(0, 0, delay_us * (initial_max_retries - max_retries), clk_mgr->base.ctx); + return reg; } @@ -120,7 +121,7 @@ static uint32_t dcn32_smu_wait_for_response_delay(struct clk_mgr_internal *clk_m *total_delay_us += delay_us; } while (max_retries--); - TRACE_SMU_DELAY(*total_delay_us, clk_mgr->base.ctx); + TRACE_SMU_MSG_DELAY(0, 0, *total_delay_us, clk_mgr->base.ctx); return reg; } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c index 347a0d66d653f..3a263840893e3 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c @@ -57,6 +57,8 @@ static bool dcn401_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uin /* Wait for response register to be ready */ dcn401_smu_wait_for_response(clk_mgr, 10, 200000); + TRACE_SMU_MSG_ENTER(msg_id, param_in, clk_mgr->base.ctx); + /* Clear response register */ REG_WRITE(DAL_RESP_REG, 0); @@ -71,9 +73,11 @@ static bool dcn401_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uin if (param_out) *param_out = REG_READ(DAL_ARG_REG); + TRACE_SMU_MSG_EXIT(true, param_out ? *param_out : 0, clk_mgr->base.ctx); return true; } + TRACE_SMU_MSG_EXIT(false, 0, clk_mgr->base.ctx); return false; } @@ -102,8 +106,6 @@ static uint32_t dcn401_smu_wait_for_response_delay(struct clk_mgr_internal *clk_ *total_delay_us += delay_us; } while (max_retries--); - TRACE_SMU_DELAY(*total_delay_us, clk_mgr->base.ctx); - return reg; } @@ -115,6 +117,8 @@ static bool dcn401_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mg /* Wait for response register to be ready */ dcn401_smu_wait_for_response_delay(clk_mgr, 10, 200000, &delay1_us); + TRACE_SMU_MSG_ENTER(msg_id, param_in, clk_mgr->base.ctx); + /* Clear response register */ REG_WRITE(DAL_RESP_REG, 0); @@ -124,18 +128,18 @@ static bool dcn401_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mg /* Trigger the message transaction by writing the message ID */ REG_WRITE(DAL_MSG_REG, msg_id); - TRACE_SMU_MSG(msg_id, param_in, clk_mgr->base.ctx); - /* Wait for response */ if (dcn401_smu_wait_for_response_delay(clk_mgr, 10, 200000, &delay2_us) == DALSMC_Result_OK) { if (param_out) *param_out = REG_READ(DAL_ARG_REG); *total_delay_us = delay1_us + delay2_us; + TRACE_SMU_MSG_EXIT(true, param_out ? *param_out : 0, clk_mgr->base.ctx); return true; } *total_delay_us = delay1_us + 2000000; + TRACE_SMU_MSG_EXIT(false, 0, clk_mgr->base.ctx); return false; } diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index 7b398d4f44398..fbbf9c757b3c3 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -277,12 +277,13 @@ void dm_perf_trace_timestamp(const char *func_name, unsigned int line, struct dc /* * SMU message tracing */ -void dm_trace_smu_msg(uint32_t msg_id, uint32_t param_in, struct dc_context *ctx); -void dm_trace_smu_delay(uint32_t delay, struct dc_context *ctx); - -#define TRACE_SMU_MSG(msg_id, param_in, ctx) dm_trace_smu_msg(msg_id, param_in, ctx) -#define TRACE_SMU_DELAY(response_delay, ctx) dm_trace_smu_delay(response_delay, ctx) +void dm_trace_smu_enter(uint32_t msg_id, uint32_t param_in, unsigned int delay, struct dc_context *ctx); +void dm_trace_smu_exit(bool success, uint32_t response, struct dc_context *ctx); +#define TRACE_SMU_MSG_DELAY(msg_id, param_in, delay, ctx) dm_trace_smu_enter(msg_id, param_in, delay, ctx) +#define TRACE_SMU_MSG(msg_id, param_in, ctx) dm_trace_smu_enter(msg_id, param_in, 0, ctx) +#define TRACE_SMU_MSG_ENTER(msg_id, param_in, ctx) dm_trace_smu_enter(msg_id, param_in, 0, ctx) +#define TRACE_SMU_MSG_EXIT(success, response, ctx) dm_trace_smu_exit(success, response, ctx) /* * DMUB Interfaces From 07003b05e43c58db17c9e0fb7ad44bf383fc1e02 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Wed, 10 Sep 2025 16:55:23 -0400 Subject: [PATCH 2056/2653] drm/amd/display: Set wm_pending when disable stutter w/a used [WHY&HOW] When stutter is disabled prior to watermark programming due to a w/a, wm_pending should be returned as true. Reviewed-by: Nicholas Kazlauskas Reviewed-by: Aurabindo Pillai Signed-off-by: Dillon Varone Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c index 3b71bfaca2914..4d4ca6d77bbda 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c @@ -770,6 +770,7 @@ static bool hubbub32_program_watermarks( (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev) || ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev))) { /* before raising watermarks, SDP control give to DF, stutter must be disabled */ + wm_pending = true; hubbub32_set_sdp_control(hubbub, false); hubbub1_allow_self_refresh_control(hubbub, false); } From 3ab170523df3604e94469f23d77638803e66841f Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Thu, 11 Sep 2025 13:52:52 -0400 Subject: [PATCH 2057/2653] drm/amd/display: Remove wm_optimized_required [WHY&HOW] This is a redundant field that is identically to optimized_required, so just replace it. Reviewed-by: Nicholas Kazlauskas Reviewed-by: Aurabindo Pillai Signed-off-by: Dillon Varone Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +---- drivers/gpu/drm/amd/display/dc/dc.h | 1 - drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 8 ++++---- drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 8 ++++---- 5 files changed, 10 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index c35ec2bc582a4..3e86283675780 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -460,7 +460,7 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, * avoid conflicting with firmware updates. */ if (dc->ctx->dce_version > DCE_VERSION_MAX) { - if ((dc->optimized_required || dc->wm_optimized_required) && + if (dc->optimized_required && (stream->adjust.v_total_max != adjust->v_total_max || stream->adjust.v_total_min != adjust->v_total_min)) { stream->adjust.timing_adjust_pending = true; @@ -2577,7 +2577,6 @@ void dc_post_update_surfaces_to_stream(struct dc *dc) } dc->optimized_required = false; - dc->wm_optimized_required = false; } bool dc_set_generic_gpio_for_stereo(bool enable, @@ -3056,8 +3055,6 @@ enum surface_update_type dc_check_update_surfaces_for_stream( } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) { dc->optimized_required = true; } - - dc->optimized_required |= dc->wm_optimized_required; } return type; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d80de2f4d171f..2a20b7a5b9347 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1739,7 +1739,6 @@ struct dc { /* Require to optimize clocks and bandwidth for added/removed planes */ bool optimized_required; - bool wm_optimized_required; bool idle_optimizations_allowed; bool enable_c20_dtm_b0; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 74f5e05f9cb43..e9fe97f0c4ea8 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -3347,7 +3347,7 @@ void dcn10_prepare_bandwidth( context, false); - dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub, + dc->optimized_required = hubbub->funcs->program_watermarks(hubbub, &context->bw_ctx.bw.dcn.watermarks, dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, true); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 95af58cbb92a5..717d2c4daa88a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -2390,10 +2390,10 @@ void dcn20_prepare_bandwidth( } /* program dchubbub watermarks: - * For assigning wm_optimized_required, use |= operator since we don't want + * For assigning optimized_required, use |= operator since we don't want * to clear the value if the optimize has not happened yet */ - dc->wm_optimized_required |= hubbub->funcs->program_watermarks(hubbub, + dc->optimized_required |= hubbub->funcs->program_watermarks(hubbub, &context->bw_ctx.bw.dcn.watermarks, dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, false); @@ -2406,10 +2406,10 @@ void dcn20_prepare_bandwidth( if (hubbub->funcs->program_compbuf_size) { if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) { compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes; - dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.dml.ip.min_comp_buffer_size_kbytes); + dc->optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.dml.ip.min_comp_buffer_size_kbytes); } else { compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb; - dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb); + dc->optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb); } hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 1b0b772fc5dd9..625653ce55565 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1383,22 +1383,22 @@ void dcn401_prepare_bandwidth(struct dc *dc, false); /* program dchubbub watermarks: - * For assigning wm_optimized_required, use |= operator since we don't want + * For assigning optimized_required, use |= operator since we don't want * to clear the value if the optimize has not happened yet */ - dc->wm_optimized_required |= hubbub->funcs->program_watermarks(hubbub, + dc->optimized_required |= hubbub->funcs->program_watermarks(hubbub, &context->bw_ctx.bw.dcn.watermarks, dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, false); /* update timeout thresholds */ if (hubbub->funcs->program_arbiter) { - dc->wm_optimized_required |= hubbub->funcs->program_arbiter(hubbub, &context->bw_ctx.bw.dcn.arb_regs, false); + dc->optimized_required |= hubbub->funcs->program_arbiter(hubbub, &context->bw_ctx.bw.dcn.arb_regs, false); } /* decrease compbuf size */ if (hubbub->funcs->program_compbuf_segments) { compbuf_size = context->bw_ctx.bw.dcn.arb_regs.compbuf_size; - dc->wm_optimized_required |= (compbuf_size != dc->current_state->bw_ctx.bw.dcn.arb_regs.compbuf_size); + dc->optimized_required |= (compbuf_size != dc->current_state->bw_ctx.bw.dcn.arb_regs.compbuf_size); hubbub->funcs->program_compbuf_segments(hubbub, compbuf_size, false); } From 472b3dc1f0b80e645c63340eefec56f9f1ea4abf Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Thu, 11 Sep 2025 17:52:11 -0400 Subject: [PATCH 2058/2653] drm/amd/display: Insert dccg log for easy debug [why] Log for sequence tracking Reviewed-by: Ovidiu (Ovi) Bunea Reviewed-by: Yihan Zhu Signed-off-by: Charlene Liu Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- .../amd/display/dc/dccg/dcn35/dcn35_dccg.c | 24 ++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index 0ce9489ac6b72..de6d62401362e 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -39,6 +39,7 @@ #define CTX \ dccg_dcn->base.ctx +#include "logger_types.h" #define DC_LOGGER \ dccg->ctx->logger @@ -1136,7 +1137,7 @@ static void dcn35_set_dppclk_enable(struct dccg *dccg, default: break; } - //DC_LOG_DEBUG("%s: dpp_inst(%d) DPPCLK_EN = %d\n", __func__, dpp_inst, enable); + DC_LOG_DEBUG("%s: dpp_inst(%d) DPPCLK_EN = %d\n", __func__, dpp_inst, enable); } @@ -1406,6 +1407,10 @@ static void dccg35_set_dtbclk_dto( * PIPEx_DTO_SRC_SEL should not be programmed during DTBCLK update since OTG may still be on, and the * programming is handled in program_pix_clk() regardless, so it can be removed from here. */ + DC_LOG_DEBUG("%s: OTG%d DTBCLK DTO enabled: pixclk_khz=%d, ref_dtbclk_khz=%d, req_dtbclk_khz=%d, phase=%d, modulo=%d\n", + __func__, params->otg_inst, params->pixclk_khz, + params->ref_dtbclk_khz, req_dtbclk_khz, phase, modulo); + } else { switch (params->otg_inst) { case 0: @@ -1431,6 +1436,8 @@ static void dccg35_set_dtbclk_dto( REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0); REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0); + + DC_LOG_DEBUG("%s: OTG%d DTBCLK DTO disabled\n", __func__, params->otg_inst); } } @@ -1475,6 +1482,8 @@ static void dccg35_set_dpstreamclk( BREAK_TO_DEBUGGER(); return; } + DC_LOG_DEBUG("%s: dp_hpo_inst(%d) DPSTREAMCLK_EN = %d, DPSTREAMCLK_SRC_SEL = %d\n", + __func__, dp_hpo_inst, (src == REFCLK) ? 0 : 1, otg_inst); } @@ -1514,6 +1523,8 @@ static void dccg35_set_dpstreamclk_root_clock_gating( BREAK_TO_DEBUGGER(); return; } + DC_LOG_DEBUG("%s: dp_hpo_inst(%d) DPSTREAMCLK_ROOT_GATE_DISABLE = %d\n", + __func__, dp_hpo_inst, enable ? 1 : 0); } @@ -1553,7 +1564,7 @@ static void dccg35_set_physymclk_root_clock_gating( BREAK_TO_DEBUGGER(); return; } - //DC_LOG_DEBUG("%s: dpp_inst(%d) PHYESYMCLK_ROOT_GATE_DISABLE:\n", __func__, phy_inst, enable ? 0 : 1); + DC_LOG_DEBUG("%s: dpp_inst(%d) PHYESYMCLK_ROOT_GATE_DISABLE: %d\n", __func__, phy_inst, enable ? 0 : 1); } @@ -1626,6 +1637,8 @@ static void dccg35_set_physymclk( BREAK_TO_DEBUGGER(); return; } + DC_LOG_DEBUG("%s: phy_inst(%d) PHYxSYMCLK_EN = %d, PHYxSYMCLK_SRC_SEL = %d\n", + __func__, phy_inst, force_enable ? 1 : 0, clk_src); } static void dccg35_set_valid_pixel_rate( @@ -1673,6 +1686,7 @@ static void dccg35_dpp_root_clock_control( } dccg->dpp_clock_gated[dpp_inst] = !clock_on; + DC_LOG_DEBUG("%s: dpp_inst(%d) clock_on = %d\n", __func__, dpp_inst, clock_on); } static void dccg35_disable_symclk32_se( @@ -1731,6 +1745,7 @@ static void dccg35_disable_symclk32_se( BREAK_TO_DEBUGGER(); return; } + } static void dccg35_init_cb(struct dccg *dccg) @@ -1738,7 +1753,6 @@ static void dccg35_init_cb(struct dccg *dccg) (void)dccg; /* Any RCG should be done when driver enter low power mode*/ } - void dccg35_init(struct dccg *dccg) { int otg_inst; @@ -1753,6 +1767,8 @@ void dccg35_init(struct dccg *dccg) for (otg_inst = 0; otg_inst < 2; otg_inst++) { dccg31_disable_symclk32_le(dccg, otg_inst); dccg31_set_symclk32_le_root_clock_gating(dccg, otg_inst, false); + DC_LOG_DEBUG("%s: OTG%d SYMCLK32_LE disabled and root clock gating disabled\n", + __func__, otg_inst); } // if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) @@ -1765,6 +1781,8 @@ void dccg35_init(struct dccg *dccg) dccg35_set_dpstreamclk(dccg, REFCLK, otg_inst, otg_inst); dccg35_set_dpstreamclk_root_clock_gating(dccg, otg_inst, false); + DC_LOG_DEBUG("%s: OTG%d DPSTREAMCLK disabled and root clock gating disabled\n", + __func__, otg_inst); } /* From 2b9678d92190815318dd5574fa1e13bc4e49df03 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Thu, 11 Sep 2025 19:20:45 -0400 Subject: [PATCH 2059/2653] drm/amd/display: Correct sw cache timing to ensure dispclk ramping [why] Current driver will cache the dispclk right after send cmd to pmfw, but actual clock not reached yet. Change to only cache the dispclk setting after HW reached to the real clock. Also give some range as it might be in bypass clock setting. Reviewed-by: Yihan Zhu Signed-off-by: Charlene Liu Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- .../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 30 +++++++++++++------ 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index 86edf11b8c5a8..6fc8a74916849 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -387,6 +387,7 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, bool update_dispclk = false; bool dpp_clock_lowered = false; int all_active_disps = 0; + int actual_dppclk = 0; if (dc->work_arounds.skip_clock_update) return; @@ -472,14 +473,13 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) dpp_clock_lowered = true; - clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; update_dppclk = true; } if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) && (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) { int requested_dispclk_khz = new_clocks->dispclk_khz; - + int actual_dispclk; dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); /* Clamp the requested clock to PMFW based on their limit. */ @@ -487,7 +487,11 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, requested_dispclk_khz = dc->debug.min_disp_clk_khz; dcn35_smu_set_dispclk(clk_mgr, requested_dispclk_khz); - clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; + actual_dispclk = REG_READ(CLK1_CLK0_CURRENT_CNT); + + /*pmfw might set bypass clock which is higher than hardmin*/ + if (actual_dispclk >= new_clocks->dispclk_khz) + clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false); @@ -505,13 +509,20 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, if (dpp_clock_lowered) { // increase per DPP DTO before lowering global dppclk dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); - dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); + dcn35_smu_set_dppclk(clk_mgr, new_clocks->dppclk_khz); } else { // increase global DPPCLK before lowering per DPP DTO if (update_dppclk || update_dispclk) - dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); + dcn35_smu_set_dppclk(clk_mgr, new_clocks->dppclk_khz); dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); } + if (update_dppclk) { + actual_dppclk = REG_READ(CLK1_CLK1_CURRENT_CNT); + + /*pmfw might set bypass clock which is higher than hardmin*/ + if (actual_dppclk >= new_clocks->dppclk_khz) + clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; + } // notify PMFW of bandwidth per DPIA tunnel if (dc->debug.notify_dpia_hr_bw) @@ -551,7 +562,7 @@ static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) * since fractional part is only 16 bit in register definition but is 32 bit * in our fix point definiton, need to shift left by 16 to obtain correct value */ - pll_req.value |= fbmult_frac_val << 16; + pll_req.value |= (long long) fbmult_frac_val << 16; /* multiply by REFCLK period */ pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); @@ -778,7 +789,8 @@ static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; /* Modify previous watermark range to cover up to max */ - table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; + if (num_valid_sets > 0) + table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; } num_valid_sets++; } @@ -939,8 +951,8 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk is_valid_clock_value(min_dram_speed_mts)); /* dispclk and dppclk can be max at any voltage, same number of levels for both */ - if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && - clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { + if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS) { + /*numDispclk is the same as numDPPclk*/ max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); max_dppclk = find_max_clk_value(clock_table->DppClocks, From dacc7d3da7d4f2ace9cbf0b2318d64503d9e952e Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Fri, 12 Sep 2025 12:37:30 -0400 Subject: [PATCH 2060/2653] drm/amd/display: Revert "correct sw cache timing to ensure dispclk ramping" [why] Need consider SSC enabled case This reverts commit b0552a6de4727ffe9604b662d90bcdbc866af16f. Reviewed-by: Ovidiu (Ovi) Bunea Reviewed-by: Chris Park Signed-off-by: Charlene Liu Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- .../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 30 ++++++------------- 1 file changed, 9 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index 6fc8a74916849..86edf11b8c5a8 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -387,7 +387,6 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, bool update_dispclk = false; bool dpp_clock_lowered = false; int all_active_disps = 0; - int actual_dppclk = 0; if (dc->work_arounds.skip_clock_update) return; @@ -473,13 +472,14 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) dpp_clock_lowered = true; + clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; update_dppclk = true; } if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) && (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) { int requested_dispclk_khz = new_clocks->dispclk_khz; - int actual_dispclk; + dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); /* Clamp the requested clock to PMFW based on their limit. */ @@ -487,11 +487,7 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, requested_dispclk_khz = dc->debug.min_disp_clk_khz; dcn35_smu_set_dispclk(clk_mgr, requested_dispclk_khz); - actual_dispclk = REG_READ(CLK1_CLK0_CURRENT_CNT); - - /*pmfw might set bypass clock which is higher than hardmin*/ - if (actual_dispclk >= new_clocks->dispclk_khz) - clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; + clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false); @@ -509,20 +505,13 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, if (dpp_clock_lowered) { // increase per DPP DTO before lowering global dppclk dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); - dcn35_smu_set_dppclk(clk_mgr, new_clocks->dppclk_khz); + dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); } else { // increase global DPPCLK before lowering per DPP DTO if (update_dppclk || update_dispclk) - dcn35_smu_set_dppclk(clk_mgr, new_clocks->dppclk_khz); + dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); } - if (update_dppclk) { - actual_dppclk = REG_READ(CLK1_CLK1_CURRENT_CNT); - - /*pmfw might set bypass clock which is higher than hardmin*/ - if (actual_dppclk >= new_clocks->dppclk_khz) - clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; - } // notify PMFW of bandwidth per DPIA tunnel if (dc->debug.notify_dpia_hr_bw) @@ -562,7 +551,7 @@ static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) * since fractional part is only 16 bit in register definition but is 32 bit * in our fix point definiton, need to shift left by 16 to obtain correct value */ - pll_req.value |= (long long) fbmult_frac_val << 16; + pll_req.value |= fbmult_frac_val << 16; /* multiply by REFCLK period */ pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); @@ -789,8 +778,7 @@ static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; /* Modify previous watermark range to cover up to max */ - if (num_valid_sets > 0) - table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; + table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; } num_valid_sets++; } @@ -951,8 +939,8 @@ static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk is_valid_clock_value(min_dram_speed_mts)); /* dispclk and dppclk can be max at any voltage, same number of levels for both */ - if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS) { - /*numDispclk is the same as numDPPclk*/ + if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && + clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); max_dppclk = find_max_clk_value(clock_table->DppClocks, From 9ed5ee114765a6ee150b4936ea0332722c80fe82 Mon Sep 17 00:00:00 2001 From: Leo Li Date: Fri, 12 Sep 2025 11:01:50 -0400 Subject: [PATCH 2061/2653] drm/amd/display: Init DCN35 clocks from pre-os HW values [Why] We did not initialize dc clocks with boot-time hw values during init. This lead to incorrect clock values in dc, causing `dcn35_update_clocks` to make incorrect updates. [How] Correctly initialize DC with pre-os clk values from HW. s/dump/save/ as that accurately reflects the purpose of the functions. Fixes: 8774029f76b9 ("drm/amd/display: Add DCN35 CLK_MGR") Reviewed-by: Aurabindo Pillai Signed-off-by: Leo Li Signed-off-by: Fangzhi Zuo Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- .../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 121 +++++++++++++++++- 1 file changed, 119 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index 86edf11b8c5a8..b11383fba35f1 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -587,9 +587,118 @@ bool dcn35_are_clock_states_equal(struct dc_clocks *a, return true; } -static void dcn35_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, +static void dcn35_save_clk_registers_internal(struct dcn35_clk_internal *internal, struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + + // read dtbclk + internal->CLK1_CLK4_CURRENT_CNT = REG_READ(CLK1_CLK4_CURRENT_CNT); + internal->CLK1_CLK4_BYPASS_CNTL = REG_READ(CLK1_CLK4_BYPASS_CNTL); + + // read dcfclk + internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT); + internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL); + + // read dcf deep sleep divider + internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); + internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS); + + // read dppclk + internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT); + internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL); + + // read dprefclk + internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT); + internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL); + + // read dispclk + internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT); + internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL); +} + +static void dcn35_save_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, struct clk_mgr_dcn35 *clk_mgr) { + struct dcn35_clk_internal internal = {0}; + char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"}; + + dcn35_save_clk_registers_internal(&internal, &clk_mgr->base.base); + + regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; + regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10; + regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS; + regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10; + regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10; + regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; + regs_and_bypass->dtbclk = internal.CLK1_CLK4_CURRENT_CNT / 10; + + regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007; + if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4) + regs_and_bypass->dppclk_bypass = 0; + regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007; + if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4) + regs_and_bypass->dcfclk_bypass = 0; + regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007; + if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4) + regs_and_bypass->dispclk_bypass = 0; + regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007; + if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4) + regs_and_bypass->dprefclk_bypass = 0; + + if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) { + DC_LOG_SMU("clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n"); + + DC_LOG_SMU("dcfclk,%d,%d,%d,%s\n", + regs_and_bypass->dcfclk, + regs_and_bypass->dcf_deep_sleep_divider, + regs_and_bypass->dcf_deep_sleep_allow, + bypass_clks[(int) regs_and_bypass->dcfclk_bypass]); + + DC_LOG_SMU("dprefclk,%d,N/A,N/A,%s\n", + regs_and_bypass->dprefclk, + bypass_clks[(int) regs_and_bypass->dprefclk_bypass]); + + DC_LOG_SMU("dispclk,%d,N/A,N/A,%s\n", + regs_and_bypass->dispclk, + bypass_clks[(int) regs_and_bypass->dispclk_bypass]); + + // REGISTER VALUES + DC_LOG_SMU("reg_name,value,clk_type"); + + DC_LOG_SMU("CLK1_CLK3_CURRENT_CNT,%d,dcfclk", + internal.CLK1_CLK3_CURRENT_CNT); + + DC_LOG_SMU("CLK1_CLK4_CURRENT_CNT,%d,dtbclk", + internal.CLK1_CLK4_CURRENT_CNT); + + DC_LOG_SMU("CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider", + internal.CLK1_CLK3_DS_CNTL); + + DC_LOG_SMU("CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow", + internal.CLK1_CLK3_ALLOW_DS); + + DC_LOG_SMU("CLK1_CLK2_CURRENT_CNT,%d,dprefclk", + internal.CLK1_CLK2_CURRENT_CNT); + + DC_LOG_SMU("CLK1_CLK0_CURRENT_CNT,%d,dispclk", + internal.CLK1_CLK0_CURRENT_CNT); + + DC_LOG_SMU("CLK1_CLK1_CURRENT_CNT,%d,dppclk", + internal.CLK1_CLK1_CURRENT_CNT); + + DC_LOG_SMU("CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass", + internal.CLK1_CLK3_BYPASS_CNTL); + + DC_LOG_SMU("CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass", + internal.CLK1_CLK2_BYPASS_CNTL); + + DC_LOG_SMU("CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass", + internal.CLK1_CLK0_BYPASS_CNTL); + + DC_LOG_SMU("CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass", + internal.CLK1_CLK1_BYPASS_CNTL); + + } } static bool dcn35_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base) @@ -623,6 +732,7 @@ static void init_clk_states(struct clk_mgr *clk_mgr) void dcn35_init_clocks(struct clk_mgr *clk_mgr) { struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr); + struct clk_mgr_dcn35 *clk_mgr_dcn35 = TO_CLK_MGR_DCN35(clk_mgr_int); init_clk_states(clk_mgr); @@ -633,6 +743,13 @@ void dcn35_init_clocks(struct clk_mgr *clk_mgr) else clk_mgr->dp_dto_source_clock_in_khz = clk_mgr->dprefclk_khz; + dcn35_save_clk_registers(&clk_mgr->boot_snapshot, clk_mgr_dcn35); + + clk_mgr->clks.ref_dtbclk_khz = clk_mgr->boot_snapshot.dtbclk * 10; + if (clk_mgr->boot_snapshot.dtbclk > 59000) { + /*dtbclk enabled based on */ + clk_mgr->clks.dtbclk_en = true; + } } static struct clk_bw_params dcn35_bw_params = { .vram_type = Ddr4MemType, @@ -1323,7 +1440,7 @@ void dcn35_clk_mgr_construct( dcn35_bw_params.wm_table = ddr5_wm_table; } /* Saved clocks configured at boot for debug purposes */ - dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr); + dcn35_save_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr); clk_mgr->base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&clk_mgr->base); clk_mgr->base.base.clks.ref_dtbclk_khz = 600000; From 1aaf448956b8ad5020156e9f6f0b1371c035d73a Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 12 Sep 2025 16:15:44 -0400 Subject: [PATCH 2062/2653] drm/amd/display: [FW Promotion] Release 0.1.28.0 Reviewed-by: Aurabindo Pillai Signed-off-by: Taimur Hassan Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index ef8510bab32c3..4e6290f19fe7c 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -4143,7 +4143,7 @@ struct dmub_cmd_replay_copy_settings_data { */ uint8_t hpo_link_enc_inst; /** - * Determines if fast sync in ultra sleep mode is enabled/disabled. + * Determines if fast resync in ultra sleep mode is enabled/disabled. */ uint8_t replay_support_fast_resync_in_ultra_sleep_mode; /** From 3550ae12e84ac5171395e21a487ee9e3d91959f6 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 12 Sep 2025 18:23:48 -0500 Subject: [PATCH 2063/2653] drm/amd/display: Promote DC to 3.2.351 - Disable stutter when programming watermarks on dcn32 - Improve brightness calculations - Fix saving vbios clocks during init for DCN314 - Enable DTM 3 on DCN3.1+ dGPUs - Add new ultra sleep field in DMUB - Isolate DCN401 SMU functions - Refactor and add logging of SMU functions. - Add dccg logging - Fix DCN35 clocks initialization Reviewed-by: Aurabindo Pillai Signed-off-by: Taimur Hassan Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 2a20b7a5b9347..de935f0c274af 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.350" +#define DC_VER "3.2.351" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From cb5f18948bc8f32d5190e016a2df8757a14e234a Mon Sep 17 00:00:00 2001 From: Rahul Kumar Date: Thu, 18 Sep 2025 12:42:00 +0530 Subject: [PATCH 2064/2653] drm/amdgpu: Use kmalloc_array() instead of kmalloc() Documentation/process/deprecated.rst recommends against the use of kmalloc with dynamic size calculations due to the risk of overflow and smaller allocation being made than the caller was expecting. Replace kmalloc() with kmalloc_array() in amdgpu_amdkfd_gfx_v10.c, amdgpu_amdkfd_gfx_v10_3.c, amdgpu_amdkfd_gfx_v11.c and amdgpu_amdkfd_gfx_v12.c to make the intended allocation size clearer and avoid potential overflow issues. Suggested-by: Felix Kuehling Signed-off-by: Rahul Kumar Signed-off-by: Felix Kuehling Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c index 04ef0ca105414..0239114fb6c4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c @@ -352,7 +352,7 @@ static int kgd_hqd_dump(struct amdgpu_device *adev, (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \ } while (0) - *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); + *dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL); if (*dump == NULL) return -ENOMEM; @@ -449,7 +449,7 @@ static int kgd_hqd_sdma_dump(struct amdgpu_device *adev, #undef HQD_N_REGS #define HQD_N_REGS (19+6+7+10) - *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); + *dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL); if (*dump == NULL) return -ENOMEM; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c index 6d08bc2781a39..f2278a0937ff0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c @@ -338,7 +338,7 @@ static int hqd_dump_v10_3(struct amdgpu_device *adev, (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \ } while (0) - *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); + *dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL); if (*dump == NULL) return -ENOMEM; @@ -435,7 +435,7 @@ static int hqd_sdma_dump_v10_3(struct amdgpu_device *adev, #undef HQD_N_REGS #define HQD_N_REGS (19+6+7+12) - *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); + *dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL); if (*dump == NULL) return -ENOMEM; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c index e0e6a6a49d900..aaccf0b9947d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c @@ -323,7 +323,7 @@ static int hqd_dump_v11(struct amdgpu_device *adev, (*dump)[i++][1] = RREG32(addr); \ } while (0) - *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); + *dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL); if (*dump == NULL) return -ENOMEM; @@ -420,7 +420,7 @@ static int hqd_sdma_dump_v11(struct amdgpu_device *adev, #undef HQD_N_REGS #define HQD_N_REGS (7+11+1+12+12) - *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); + *dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL); if (*dump == NULL) return -ENOMEM; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c index 2ffbf42e01c01..3396a5bf31147 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c @@ -117,7 +117,7 @@ static int hqd_dump_v12(struct amdgpu_device *adev, (*dump)[i++][1] = RREG32(addr); \ } while (0) - *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); + *dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL); if (*dump == NULL) return -ENOMEM; @@ -148,7 +148,7 @@ static int hqd_sdma_dump_v12(struct amdgpu_device *adev, #undef HQD_N_REGS #define HQD_N_REGS (last_reg - first_reg + 1) - *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); + *dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL); if (*dump == NULL) return -ENOMEM; From bd8bec27430b76835bbaa5d0e0cdb77e9ea3b709 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Fri, 19 Sep 2025 09:44:25 +0800 Subject: [PATCH 2065/2653] drm/amd/pm: place the smu 13.0.0 pptable header into the correct folder Place the smu 13.0.0 pptable header in the correct folder Signed-off-by: Yang Wang Reviewed-by: Mangesh Gadre --- drivers/gpu/drm/amd/pm/{ => swsmu}/inc/smu_v13_0_0_pptable.h | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename drivers/gpu/drm/amd/pm/{ => swsmu}/inc/smu_v13_0_0_pptable.h (100%) diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h similarity index 100% rename from drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h rename to drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_0_pptable.h From 142c60ce27d97b3f436d5724ea08e65c00b6324d Mon Sep 17 00:00:00 2001 From: Melissa Wen Date: Thu, 11 Sep 2025 14:21:19 -0300 Subject: [PATCH 2066/2653] drm/amd/display: update color on atomic commit time Use `atomic_commit_setup` to change the DC stream state. It's a preparation to remove from `atomic_check` changes in CRTC color components of DC stream state and prevent DC to commit TEST_ONLY changes. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/4444 Reviewed-by: Harry Wentland Signed-off-by: Melissa Wen --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 40 ++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index cf71dd27498de..1d32f6212ff0f 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -234,6 +234,9 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev, static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); +#ifdef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT +static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state); +#endif static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); static int amdgpu_dm_atomic_check(struct drm_device *dev, @@ -3678,7 +3681,7 @@ static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, #ifdef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT - .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, + .atomic_commit_setup = amdgpu_dm_atomic_setup_commit, #endif }; @@ -10661,6 +10664,41 @@ static void amdgpu_dm_update_hdcp(struct drm_atomic_state *state) } } +#ifdef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT +static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state) +{ + struct drm_crtc *crtc; + struct drm_crtc_state *old_crtc_state, *new_crtc_state; + struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; + int i, ret; + + ret = drm_dp_mst_atomic_setup_commit(state); + if (ret) + return ret; + + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + /* + * Color management settings. We also update color properties + * when a modeset is needed, to ensure it gets reprogrammed. + */ + if (dm_new_crtc_state->base.active && dm_new_crtc_state->stream && + (dm_new_crtc_state->base.color_mgmt_changed || + dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || + drm_atomic_crtc_needs_modeset(new_crtc_state))) { + ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); + if (ret) { + drm_dbg_atomic(state->dev, "Failed to update color state\n"); + return ret; + } + } + } + + return 0; +} +#endif + /** * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. * @state: The atomic state to commit From d29fd1943efd7d2906e9a3ac3c7f92cfbbe80141 Mon Sep 17 00:00:00 2001 From: Melissa Wen Date: Thu, 11 Sep 2025 14:21:20 -0300 Subject: [PATCH 2067/2653] drm/amd/display: change dc stream color settings only in atomic commit Don't update DC stream color components during atomic check. The driver will continue validating the new CRTC color state but will not change DC stream color components. The DC stream color state will only be programmed at commit time in the `atomic_setup_commit` stage. It fixes gamma LUT loss reported by KDE users when changing brightness quickly or changing Display settings (such as overscan) with nightlight on and HDR. As KWin can do a test commit with color settings different from those that should be applied in a non-test-only commit, if the driver changes DC stream color state in atomic check, this state can be eventually HW programmed in commit tail, instead of the respective state set by the non-blocking commit. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4444 Reported-by: Xaver Hugl Signed-off-by: Melissa Wen Reviewed-by: Harry Wentland --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 + .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 86 ++++++++++++++----- 3 files changed, 66 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1d32f6212ff0f..9ae0025d78029 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11535,7 +11535,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, if (dm_new_crtc_state->base.color_mgmt_changed || dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || drm_atomic_crtc_needs_modeset(new_crtc_state)) { - ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); + ret = amdgpu_dm_check_crtc_color_mgmt(dm_new_crtc_state, true); if (ret) goto fail; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 0a8b4b6aa5b52..96b8ce00ac4cb 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -1070,6 +1070,8 @@ void amdgpu_dm_init_color_mod(void); int amdgpu_dm_create_color_properties(struct amdgpu_device *adev); int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); +int amdgpu_dm_check_crtc_color_mgmt(struct dm_crtc_state *crtc, + bool check_only); int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index b0ef157f13339..a4ac6d442278e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -566,12 +566,11 @@ static int __set_output_tf(struct dc_transfer_func *func, return res ? 0 : -ENOMEM; } -static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream, +static int amdgpu_dm_set_atomic_regamma(struct dc_transfer_func *out_tf, const struct drm_color_lut *regamma_lut, uint32_t regamma_size, bool has_rom, enum dc_transfer_func_predefined tf) { - struct dc_transfer_func *out_tf = &stream->out_transfer_func; int ret = 0; if (regamma_size || tf != TRANSFER_FUNCTION_LINEAR) { @@ -885,33 +884,33 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state) } /** - * amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC stream. + * amdgpu_dm_check_crtc_color_mgmt: Check if DRM color props are programmable by DC. * @crtc: amdgpu_dm crtc state + * @check_only: only check color state without update dc stream * - * With no plane level color management properties we're free to use any - * of the HW blocks as long as the CRTC CTM always comes before the - * CRTC RGM and after the CRTC DGM. - * - * - The CRTC RGM block will be placed in the RGM LUT block if it is non-linear. - * - The CRTC DGM block will be placed in the DGM LUT block if it is non-linear. - * - The CRTC CTM will be placed in the gamut remap block if it is non-linear. + * This function just verifies CRTC LUT sizes, if there is enough space for + * output transfer function and if its parameters can be calculated by AMD + * color module. It also adjusts some settings for programming CRTC degamma at + * plane stage, using plane DGM block. * * The RGM block is typically more fully featured and accurate across * all ASICs - DCE can't support a custom non-linear CRTC DGM. * * For supporting both plane level color management and CRTC level color - * management at once we have to either restrict the usage of CRTC properties - * or blend adjustments together. + * management at once we have to either restrict the usage of some CRTC + * properties or blend adjustments together. * * Returns: - * 0 on success. Error code if setup fails. + * 0 on success. Error code if validation fails. */ -int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) + +int amdgpu_dm_check_crtc_color_mgmt(struct dm_crtc_state *crtc, + bool check_only) { struct dc_stream_state *stream = crtc->stream; struct amdgpu_device *adev = drm_to_adev(crtc->base.state->dev); bool has_rom = adev->asic_type <= CHIP_RAVEN; - struct drm_color_ctm *ctm = NULL; + struct dc_transfer_func *out_tf; const struct drm_color_lut *degamma_lut, *regamma_lut; uint32_t degamma_size, regamma_size; bool has_regamma, has_degamma; @@ -940,6 +939,14 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) crtc->cm_has_degamma = false; crtc->cm_is_degamma_srgb = false; + if (check_only) { + out_tf = kvzalloc(sizeof(*out_tf), GFP_KERNEL); + if (!out_tf) + return -ENOMEM; + } else { + out_tf = &stream->out_transfer_func; + } + /* Setup regamma and degamma. */ if (is_legacy) { /* @@ -954,8 +961,8 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) * inverse color ramp in legacy userspace. */ crtc->cm_is_degamma_srgb = true; - stream->out_transfer_func.type = TF_TYPE_DISTRIBUTED_POINTS; - stream->out_transfer_func.tf = TRANSFER_FUNCTION_SRGB; + out_tf->type = TF_TYPE_DISTRIBUTED_POINTS; + out_tf->tf = TRANSFER_FUNCTION_SRGB; /* * Note: although we pass has_rom as parameter here, we never * actually use ROM because the color module only takes the ROM @@ -963,16 +970,12 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) * * See more in mod_color_calculate_regamma_params() */ - r = __set_legacy_tf(&stream->out_transfer_func, regamma_lut, + r = __set_legacy_tf(out_tf, regamma_lut, regamma_size, has_rom); - if (r) - return r; } else { regamma_size = has_regamma ? regamma_size : 0; - r = amdgpu_dm_set_atomic_regamma(stream, regamma_lut, + r = amdgpu_dm_set_atomic_regamma(out_tf, regamma_lut, regamma_size, has_rom, tf); - if (r) - return r; } /* @@ -981,6 +984,43 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) * have to place the CTM in the OCSC in that case. */ crtc->cm_has_degamma = has_degamma; + if (check_only) + kvfree(out_tf); + + return r; +} + +/** + * amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC stream. + * @crtc: amdgpu_dm crtc state + * + * With no plane level color management properties we're free to use any + * of the HW blocks as long as the CRTC CTM always comes before the + * CRTC RGM and after the CRTC DGM. + * + * - The CRTC RGM block will be placed in the RGM LUT block if it is non-linear. + * - The CRTC DGM block will be placed in the DGM LUT block if it is non-linear. + * - The CRTC CTM will be placed in the gamut remap block if it is non-linear. + * + * The RGM block is typically more fully featured and accurate across + * all ASICs - DCE can't support a custom non-linear CRTC DGM. + * + * For supporting both plane level color management and CRTC level color + * management at once we have to either restrict the usage of CRTC properties + * or blend adjustments together. + * + * Returns: + * 0 on success. Error code if setup fails. + */ +int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) +{ + struct dc_stream_state *stream = crtc->stream; + struct drm_color_ctm *ctm = NULL; + int ret; + + ret = amdgpu_dm_check_crtc_color_mgmt(crtc, false); + if (ret) + return ret; /* Setup CRTC CTM. */ if (crtc->base.ctm) { From 5357a8aca05d7af2c689cc2693f4abd9d74b3816 Mon Sep 17 00:00:00 2001 From: Kuan-Wei Chiu Date: Tue, 9 Sep 2025 17:20:57 +0800 Subject: [PATCH 2068/2653] drm/amd/display: Optimize remove_duplicates() from O(N^2) to O(N) Replace the previous O(N^2) implementation of remove_duplicates() with a O(N) version using a fast/slow pointer approach. The new version keeps only the first occurrence of each element and compacts the array in place, improving efficiency without changing functionality. Signed-off-by: Kuan-Wei Chiu Reviewed-by: Alex Hung --- .../dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c | 21 ++++++++++--------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c index e763c8e45da81..1b9579a32ff28 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c @@ -48,18 +48,19 @@ static void set_reserved_time_on_all_planes_with_stream_index(struct display_con static void remove_duplicates(double *list_a, int *list_a_size) { - int cur_element = 0; - // For all elements b[i] in list_b[] - while (cur_element < *list_a_size - 1) { - if (list_a[cur_element] == list_a[cur_element + 1]) { - for (int j = cur_element + 1; j < *list_a_size - 1; j++) { - list_a[j] = list_a[j + 1]; - } - *list_a_size = *list_a_size - 1; - } else { - cur_element++; + int j = 0; + + if (*list_a_size == 0) + return; + + for (int i = 1; i < *list_a_size; i++) { + if (list_a[j] != list_a[i]) { + j++; + list_a[j] = list_a[i]; } } + + *list_a_size = j + 1; } static bool increase_mpc_combine_factor(unsigned int *mpc_combine_factor, unsigned int limit) From a30f4262be335e7eab534fd2d2a57d58697da193 Mon Sep 17 00:00:00 2001 From: Melissa Wen Date: Mon, 1 Sep 2025 18:51:05 -0300 Subject: [PATCH 2069/2653] drm/amd/display: remove output_tf_change flag Remove this flag as the driver stopped managing it individually since commit a4056c2a6344 ("drm/amd/display: use HW hdr mult for brightness boost"). After some back and forth it was reintroduced as a condition to `set_output_transfer_func()` in [1]. Without direct management, this flag only changes value when all surface update flags are set true on UPDATE_TYPE_FULL with no output TF status meaning. Fixes: bb622e0c0044 ("drm/amd/display: program output tf when required") [1] Signed-off-by: Melissa Wen Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/dc.h | 1 - drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 6 ++---- drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 6 ++---- 3 files changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index de935f0c274af..5d7eeca78c02f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1395,7 +1395,6 @@ union surface_update_flags { uint32_t in_transfer_func_change:1; uint32_t input_csc_change:1; uint32_t coeff_reduction_change:1; - uint32_t output_tf_change:1; uint32_t pixel_format_change:1; uint32_t plane_size_change:1; uint32_t gamut_remap_change:1; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 717d2c4daa88a..9477c9f9e1963 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -1982,10 +1982,8 @@ static void dcn20_program_pipe( * updating on slave planes */ if (pipe_ctx->update_flags.bits.enable || - pipe_ctx->update_flags.bits.plane_changed || - pipe_ctx->stream->update_flags.bits.out_tf || - (pipe_ctx->plane_state && - pipe_ctx->plane_state->update_flags.bits.output_tf_change)) + pipe_ctx->update_flags.bits.plane_changed || + pipe_ctx->stream->update_flags.bits.out_tf) hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); /* If the pipe has been enabled or has a different opp, we diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 625653ce55565..7c276c3190867 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -2032,10 +2032,8 @@ void dcn401_program_pipe( * updating on slave planes */ if (pipe_ctx->update_flags.bits.enable || - pipe_ctx->update_flags.bits.plane_changed || - pipe_ctx->stream->update_flags.bits.out_tf || - (pipe_ctx->plane_state && - pipe_ctx->plane_state->update_flags.bits.output_tf_change)) + pipe_ctx->update_flags.bits.plane_changed || + pipe_ctx->stream->update_flags.bits.out_tf) hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); /* If the pipe has been enabled or has a different opp, we From 4bfbc0cf43470e582d80a7586cba532bc9bd2638 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 2 May 2025 16:22:45 -0400 Subject: [PATCH 2070/2653] Documentation: add initial documenation for user queues Add an initial documentation page for user mode queues. Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- Documentation/gpu/amdgpu/index.rst | 1 + Documentation/gpu/amdgpu/userq.rst | 203 +++++++++++++++++++++++++++++ 2 files changed, 204 insertions(+) create mode 100644 Documentation/gpu/amdgpu/userq.rst diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst index bb2894b5edaf2..45523e9860fc5 100644 --- a/Documentation/gpu/amdgpu/index.rst +++ b/Documentation/gpu/amdgpu/index.rst @@ -12,6 +12,7 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures. module-parameters gc/index display/index + userq flashing xgmi ras diff --git a/Documentation/gpu/amdgpu/userq.rst b/Documentation/gpu/amdgpu/userq.rst new file mode 100644 index 0000000000000..ca3ea71f7888b --- /dev/null +++ b/Documentation/gpu/amdgpu/userq.rst @@ -0,0 +1,203 @@ +================== + User Mode Queues +================== + +Introduction +============ + +Similar to the KFD, GPU engine queues move into userspace. The idea is to let +user processes manage their submissions to the GPU engines directly, bypassing +IOCTL calls to the driver to submit work. This reduces overhead and also allows +the GPU to submit work to itself. Applications can set up work graphs of jobs +across multiple GPU engines without needing trips through the CPU. + +UMDs directly interface with firmware via per application shared memory areas. +The main vehicle for this is queue. A queue is a ring buffer with a read +pointer (rptr) and a write pointer (wptr). The UMD writes IP specific packets +into the queue and the firmware processes those packets, kicking off work on the +GPU engines. The CPU in the application (or another queue or device) updates +the wptr to tell the firmware how far into the ring buffer to process packets +and the rtpr provides feedback to the UMD on how far the firmware has progressed +in executing those packets. When the wptr and the rptr are equal, the queue is +idle. + +Theory of Operation +=================== + +The various engines on modern AMD GPUs support multiple queues per engine with a +scheduling firmware which handles dynamically scheduling user queues on the +available hardware queue slots. When the number of user queues outnumbers the +available hardware queue slots, the scheduling firmware dynamically maps and +unmaps queues based on priority and time quanta. The state of each user queue +is managed in the kernel driver in an MQD (Memory Queue Descriptor). This is a +buffer in GPU accessible memory that stores the state of a user queue. The +scheduling firmware uses the MQD to load the queue state into an HQD (Hardware +Queue Descriptor) when a user queue is mapped. Each user queue requires a +number of additional buffers which represent the ring buffer and any metadata +needed by the engine for runtime operation. On most engines this consists of +the ring buffer itself, a rptr buffer (where the firmware will shadow the rptr +to userspace), a wptr buffer (where the application will write the wptr for the +firmware to fetch it), and a doorbell. A doorbell is a piece of one of the +device's MMIO BARs which can be mapped to specific user queues. When the +application writes to the doorbell, it will signal the firmware to take some +action. Writing to the doorbell wakes the firmware and causes it to fetch the +wptr and start processing the packets in the queue. Each 4K page of the doorbell +BAR supports specific offset ranges for specific engines. The doorbell of a +queue must be mapped into the aperture aligned to the IP used by the queue +(e.g., GFX, VCN, SDMA, etc.). These doorbell apertures are set up via NBIO +registers. Doorbells are 32 bit or 64 bit (depending on the engine) chunks of +the doorbell BAR. A 4K doorbell page provides 512 64-bit doorbells for up to +512 user queues. A subset of each page is reserved for each IP type supported +on the device. The user can query the doorbell ranges for each IP via the INFO +IOCTL. See the IOCTL Interfaces section for more information. + +When an application wants to create a user queue, it allocates the necessary +buffers for the queue (ring buffer, wptr and rptr, context save areas, etc.). +These can be separate buffers or all part of one larger buffer. The application +would map the buffer(s) into its GPUVM and use the GPU virtual addresses of for +the areas of memory they want to use for the user queue. They would also +allocate a doorbell page for the doorbells used by the user queues. The +application would then populate the MQD in the USERQ IOCTL structure with the +GPU virtual addresses and doorbell index they want to use. The user can also +specify the attributes for the user queue (priority, whether the queue is secure +for protected content, etc.). The application would then call the USERQ +CREATE IOCTL to create the queue using the specified MQD details in the IOCTL. +The kernel driver then validates the MQD provided by the application and +translates the MQD into the engine specific MQD format for the IP. The IP +specific MQD would be allocated and the queue would be added to the run list +maintained by the scheduling firmware. Once the queue has been created, the +application can write packets directly into the queue, update the wptr, and +write to the doorbell offset to kick off work in the user queue. + +When the application is done with the user queue, it would call the USERQ +FREE IOCTL to destroy it. The kernel driver would preempt the queue and +remove it from the scheduling firmware's run list. Then the IP specific MQD +would be freed and the user queue state would be cleaned up. + +Some engines may require the aggregated doorbell too if the engine does not +support doorbells from unmapped queues. The aggregated doorbell is a special +page of doorbell space which wakes the scheduler. In cases where the engine may +be oversubscribed, some queues may not be mapped. If the doorbell is rung when +the queue is not mapped, the engine firmware may miss the request. Some +scheduling firmware may work around this by polling wptr shadows when the +hardware is oversubscribed, other engines may support doorbell updates from +unmapped queues. In the event that one of these options is not available, the +kernel driver will map a page of aggregated doorbell space into each GPUVM +space. The UMD will then update the doorbell and wptr as normal and then write +to the aggregated doorbell as well. + +Special Packets +--------------- + +In order to support legacy implicit synchronization, as well as mixed user and +kernel queues, we need a synchronization mechanism that is secure. Because +kernel queues or memory management tasks depend on kernel fences, we need a way +for user queues to update memory that the kernel can use for a fence, that can't +be messed with by a bad actor. To support this, we've added a protected fence +packet. This packet works by writing a monotonically increasing value to +a memory location that only privileged clients have write access to. User +queues only have read access. When this packet is executed, the memory location +is updated and other queues (kernel or user) can see the results. The +user application would submit this packet in their command stream. The actual +packet format varies from IP to IP (GFX/Compute, SDMA, VCN, etc.), but the +behavior is the same. The packet submission is handled in userspace. The +kernel driver sets up the privileged memory used for each user queue when it +sets the queues up when the application creates them. + + +Memory Management +================= + +It is assumed that all buffers mapped into the GPUVM space for the process are +valid when engines on the GPU are running. The kernel driver will only allow +user queues to run when all buffers are mapped. If there is a memory event that +requires buffer migration, the kernel driver will preempt the user queues, +migrate buffers to where they need to be, update the GPUVM page tables and +invaldidate the TLB, and then resume the user queues. + +Interaction with Kernel Queues +============================== + +Depending on the IP and the scheduling firmware, you can enable kernel queues +and user queues at the same time, however, you are limited by the HQD slots. +Kernel queues are always mapped so any work that goes into kernel queues will +take priority. This limits the available HQD slots for user queues. + +Not all IPs will support user queues on all GPUs. As such, UMDs will need to +support both user queues and kernel queues depending on the IP. For example, a +GPU may support user queues for GFX, compute, and SDMA, but not for VCN, JPEG, +and VPE. UMDs need to support both. The kernel driver provides a way to +determine if user queues and kernel queues are supported on a per IP basis. +UMDs can query this information via the INFO IOCTL and determine whether to use +kernel queues or user queues for each IP. + +Queue Resets +============ + +For most engines, queues can be reset individually. GFX, compute, and SDMA +queues can be reset individually. When a hung queue is detected, it can be +reset either via the scheduling firmware or MMIO. Since there are no kernel +fences for most user queues, they will usually only be detected when some other +event happens; e.g., a memory event which requires migration of buffers. When +the queues are preempted, if the queue is hung, the preemption will fail. +Driver will then look up the queues that failed to preempt and reset them and +record which queues are hung. + +On the UMD side, we will add a USERQ QUERY_STATUS IOCTL to query the queue +status. UMD will provide the queue id in the IOCTL and the kernel driver +will check if it has already recorded the queue as hung (e.g., due to failed +peemption) and report back the status. + +IOCTL Interfaces +================ + +GPU virtual addresses used for queues and related data (rptrs, wptrs, context +save areas, etc.) should be validated by the kernel mode driver to prevent the +user from specifying invalid GPU virtual addresses. If the user provides +invalid GPU virtual addresses or doorbell indicies, the IOCTL should return an +error message. These buffers should also be tracked in the kernel driver so +that if the user attempts to unmap the buffer(s) from the GPUVM, the umap call +would return an error. + +INFO +---- +There are several new INFO queries related to user queues in order to query the +size of user queue meta data needed for a user queue (e.g., context save areas +or shadow buffers), whether kernel or user queues or both are supported +for each IP type, and the offsets for each IP type in each doorbell page. + +USERQ +----- +The USERQ IOCTL is used for creating, freeing, and querying the status of user +queues. It supports 3 opcodes: + +1. CREATE - Create a user queue. The application provides an MQD-like structure + that defines the type of queue and associated metadata and flags for that + queue type. Returns the queue id. +2. FREE - Free a user queue. +3. QUERY_STATUS - Query that status of a queue. Used to check if the queue is + healthy or not. E.g., if the queue has been reset. (WIP) + +USERQ_SIGNAL +------------ +The USERQ_SIGNAL IOCTL is used to provide a list of sync objects to be signaled. + +USERQ_WAIT +---------- +The USERQ_WAIT IOCTL is used to provide a list of sync object to be waited on. + +Kernel and User Queues +====================== + +In order to properly validate and test performance, we have a driver option to +select what type of queues are enabled (kernel queues, user queues or both). +The user_queue driver parameter allows you to enable kernel queues only (0), +user queues and kernel queues (1), and user queues only (2). Enabling user +queues only will free up static queue assignments that would otherwise be used +by kernel queues for use by the scheduling firmware. Some kernel queues are +required for kernel driver operation and they will always be created. When the +kernel queues are not enabled, they are not registered with the drm scheduler +and the CS IOCTL will reject any incoming command submissions which target those +queue types. Kernel queues only mirrors the behavior on all existing GPUs. +Enabling both queues allows for backwards compatibility with old userspace while +still supporting user queues. From 39b02289c58277e6633f6cc92c7f818d5513fb05 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Wed, 6 Aug 2025 16:03:13 +0800 Subject: [PATCH 2071/2653] drm/amdgpu: Refactor VCN v5.0.1 HW init into separate instance function Split the per-instance initialization code from vcn_v5_0_1_hw_init() into a new vcn_v5_0_1_hw_init_inst() function. This improves code organization by: 1. Separating the instance-specific initialization logic 2. Making the main init function more readable 3. Following the pattern used in queue reset The SR-IOV specific initialization remains in the main function since it has different requirements. Reviewed-by: Sonny Jiang Signed-off-by: Jesse Zhang Signed-off-by: Ruili Ji --- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 27 +++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c index 9c281ba6bcedc..3677ea9ffa436 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c @@ -253,6 +253,23 @@ static int vcn_v5_0_1_sw_fini(struct amdgpu_ip_block *ip_block) return 0; } +static int vcn_v5_0_1_hw_init_inst(struct amdgpu_device *adev, int i) +{ + struct amdgpu_ring *ring; + int vcn_inst; + + vcn_inst = GET_INST(VCN, i); + ring = &adev->vcn.inst[i].ring_enc[0]; + + if (ring->use_doorbell) + adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, + ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + + 11 * vcn_inst), + adev->vcn.inst[i].aid_id); + + return 0; +} + /** * vcn_v5_0_1_hw_init - start and test VCN block * @@ -264,7 +281,7 @@ static int vcn_v5_0_1_hw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; - int i, r, vcn_inst; + int i, r; if (amdgpu_sriov_vf(adev)) { r = vcn_v5_0_1_start_sriov(adev); @@ -282,14 +299,8 @@ static int vcn_v5_0_1_hw_init(struct amdgpu_ip_block *ip_block) if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100) adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { - vcn_inst = GET_INST(VCN, i); ring = &adev->vcn.inst[i].ring_enc[0]; - - if (ring->use_doorbell) - adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, - ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + - 11 * vcn_inst), - adev->vcn.inst[i].aid_id); + vcn_v5_0_1_hw_init_inst(adev, i); /* Re-init fw_shared, if required */ vcn_v5_0_1_fw_shared_init(adev, i); From d8aca1d1f47794070692b1578c98f52b421dcc96 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Wed, 6 Aug 2025 16:20:28 +0800 Subject: [PATCH 2072/2653] drm/amdgpu: Add ring reset support for VCN v5.0.1 Implement the ring reset callback for VCN v5.0.1 to properly handle hardware recovery when encountering GPU hangs. The new functionality: 1. Adds vcn_v5_0_1_ring_reset() function that: - Prepares for reset using amdgpu_ring_reset_helper_begin() - Performs VCN instance reset via amdgpu_dpm_reset_vcn() - Re-initializes hardware through vcn_v5_0_1_hw_init_inst() - Restarts DPG mode with vcn_v5_0_1_start_dpg_mode() - Completes reset with amdgpu_ring_reset_helper_end() 2. Hooks the reset function into the unified ring functions via: - Adding .reset = vcn_v5_0_1_ring_reset to vcn_v5_0_1_unified_ring_vm_funcs 3. Maintains existing behavior for SR-IOV VF cases by checking RRMT status This provides proper hardware recovery capabilities for VCN 5.0.1 IP block during fault conditions, matching functionality available in other VCN versions. v2: Remove the RRMT_ENABLED cap setting in the reset function and replace adev->vcn.inst[ring->me].indirect_sram with vinst->indirect_sram (Lijo) Reviewed-by: Sonny Jiang Suggested-by: Lijo Lazar Signed-off-by: Jesse Zhang Signed-off-by: Ruili Ji --- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 26 +++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c index 3677ea9ffa436..11b931153ea1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c @@ -1284,6 +1284,31 @@ static void vcn_v5_0_1_unified_ring_set_wptr(struct amdgpu_ring *ring) } } +static int vcn_v5_0_1_ring_reset(struct amdgpu_ring *ring, + unsigned int vmid, + struct amdgpu_fence *timedout_fence) +{ + int r = 0; + int vcn_inst; + struct amdgpu_device *adev = ring->adev; + struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; + + amdgpu_ring_reset_helper_begin(ring, timedout_fence); + + vcn_inst = GET_INST(VCN, ring->me); + r = amdgpu_dpm_reset_vcn(adev, 1 << vcn_inst); + + if (r) { + DRM_DEV_ERROR(adev->dev, "VCN reset fail : %d\n", r); + return r; + } + + vcn_v5_0_1_hw_init_inst(adev, ring->me); + vcn_v5_0_1_start_dpg_mode(vinst, vinst->indirect_sram); + + return amdgpu_ring_reset_helper_end(ring, timedout_fence); +} + static const struct amdgpu_ring_funcs vcn_v5_0_1_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, @@ -1312,6 +1337,7 @@ static const struct amdgpu_ring_funcs vcn_v5_0_1_unified_ring_vm_funcs = { .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg, .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait, .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, + .reset = vcn_v5_0_1_ring_reset, }; /** From f9fb0b23cc49f87547bc3ae3cfa4c4b0ec4dc952 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Fri, 15 Aug 2025 23:44:11 +0800 Subject: [PATCH 2073/2653] drm/amdgpu: Move VCN reset mask setup to late_init for VCN 5.0.1 This patch moves the initialization of the VCN supported_reset mask from sw_init to a new late_init function for VCN 5.0.1. The change ensures that all necessary hardware and firmware initialization is complete before determining the supported reset types. Key changes: - Added vcn_v5_0_1_late_init() function to handle late initialization - Moved supported_reset mask setup from sw_init to late_init - Added check for per-queue reset support via amdgpu_dpm_reset_vcn_is_supported() - Updated ip_funcs to use the new late_init function This change helps ensure proper reset behavior by waiting until all dependencies are initialized before determining available reset types. Reviewed-by: Sonny Jiang Signed-off-by: Jesse Zhang Signed-off-by: Ruili Ji --- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c index 11b931153ea1b..714350cabf2fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c @@ -113,6 +113,25 @@ static int vcn_v5_0_1_early_init(struct amdgpu_ip_block *ip_block) return 0; } +static int vcn_v5_0_1_late_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + + adev->vcn.supported_reset = + amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); + + switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { + case IP_VERSION(13, 0, 12): + if ((adev->psp.sos.fw_version >= 0x00450025) && amdgpu_dpm_reset_vcn_is_supported(adev)) + adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; + break; + default: + break; + } + + return 0; +} + static void vcn_v5_0_1_fw_shared_init(struct amdgpu_device *adev, int inst_idx) { struct amdgpu_vcn5_fw_shared *fw_shared; @@ -187,10 +206,6 @@ static int vcn_v5_0_1_sw_init(struct amdgpu_ip_block *ip_block) vcn_v5_0_1_fw_shared_init(adev, i); } - /* TODO: Add queue reset mask when FW fully supports it */ - adev->vcn.supported_reset = - amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); - if (amdgpu_sriov_vf(adev)) { r = amdgpu_virt_alloc_mm_table(adev); if (r) @@ -1541,7 +1556,7 @@ static void vcn_v5_0_1_set_irq_funcs(struct amdgpu_device *adev) static const struct amd_ip_funcs vcn_v5_0_1_ip_funcs = { .name = "vcn_v5_0_1", .early_init = vcn_v5_0_1_early_init, - .late_init = NULL, + .late_init = vcn_v5_0_1_late_init, .sw_init = vcn_v5_0_1_sw_init, .sw_fini = vcn_v5_0_1_sw_fini, .hw_init = vcn_v5_0_1_hw_init, From d186948aedb5ad93cd9a33a87062c6680d5eaf33 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Mon, 22 Sep 2025 09:40:51 +0800 Subject: [PATCH 2074/2653] drm/amd/pm: Add VCN reset message support for SMU v13.0.12 This commit adds support for VCN reset functionality in SMU v13.0.12 by: 1. Adding two new PPSMC messages in smu_v13_0_12_ppsmc.h: - PPSMC_MSG_ResetVCN (0x5E) - Updates PPSMC_Message_Count to 0x5F to account for new messages 2. Adding message mapping for ResetVCN in smu_v13_0_12_ppt.c: - Maps SMU_MSG_ResetVCN to PPSMC_MSG_ResetVCN These changes enable proper VCN reset handling through the SMU firmware interface for compatible AMD GPUs. v2: Added fw version check to support vcn queue reset. Acked-by: Alex Deucher Reviewed-by: Yang Wang Reviewed-by: Sonny Jiang Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h | 3 ++- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 1 + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 3 +++ 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h index aff2776a8b6f4..4b066c42e0ec9 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h @@ -120,7 +120,8 @@ #define PPSMC_MSG_GetBadPageSeverity 0x5B #define PPSMC_MSG_GetSystemMetricsTable 0x5C #define PPSMC_MSG_GetSystemMetricsVersion 0x5D -#define PPSMC_Message_Count 0x5E +#define PPSMC_MSG_ResetVCN 0x5E +#define PPSMC_Message_Count 0x5F //PPSMC Reset Types for driver msg argument #define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET 0x1 diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index 1842a33b2bce7..cb3fea9e8cf31 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -136,6 +136,7 @@ const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[SMU_MSG_MAX_COUNT] = MSG_MAP(RmaDueToBadPageThreshold, PPSMC_MSG_RmaDueToBadPageThreshold, 0), MSG_MAP(SetThrottlingPolicy, PPSMC_MSG_SetThrottlingPolicy, 0), MSG_MAP(ResetSDMA, PPSMC_MSG_ResetSDMA, 0), + MSG_MAP(ResetVCN, PPSMC_MSG_ResetVCN, 0), MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 1), MSG_MAP(GetSystemMetricsTable, PPSMC_MSG_GetSystemMetricsTable, 1), }; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index c74db0ec2b450..c2bb578150fbf 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -361,6 +361,9 @@ static void smu_v13_0_12_init_caps(struct smu_context *smu) smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION)); } + if (fw_ver > 0x04560900) + smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET)); + if (fw_ver >= 0x04560700) { if (fw_ver >= 0x04560900) { smu_v13_0_6_cap_set(smu, SMU_CAP(TEMP_METRICS)); From 1308c7de34b5979fe71270c3f58bdf0af3fdf943 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Tue, 16 Sep 2025 13:11:06 +0800 Subject: [PATCH 2075/2653] drm/amdgpu: Add fallback to pipe reset if KCQ ring reset fails Add a fallback mechanism to attempt pipe reset when KCQ reset fails to recover the ring. After performing the KCQ reset and queue remapping, test the ring functionality. If the ring test fails, initiate a pipe reset as an additional recovery step. v2: fix the typo (Lijo) v3: try pipeline reset when kiq mapping fails (Lijo) Reviewed-by: Alex Deucher Signed-off-by: Lijo Lazar Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 8967f5253d432..59cba26049f17 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -3724,6 +3724,7 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, struct amdgpu_device *adev = ring->adev; struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id]; struct amdgpu_ring *kiq_ring = &kiq->ring; + int reset_mode = AMDGPU_RESET_TYPE_PER_QUEUE; unsigned long flags; int r; @@ -3761,6 +3762,7 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_PIPE)) return -EOPNOTSUPP; r = gfx_v9_4_3_reset_hw_pipe(ring); + reset_mode = AMDGPU_RESET_TYPE_PER_PIPE; dev_info(adev->dev, "ring: %s pipe reset :%s\n", ring->name, r ? "failed" : "successfully"); if (r) @@ -3783,10 +3785,20 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, r = amdgpu_ring_test_ring(kiq_ring); spin_unlock_irqrestore(&kiq->ring_lock, flags); if (r) { + if (reset_mode == AMDGPU_RESET_TYPE_PER_QUEUE) + goto pipe_reset; + dev_err(adev->dev, "fail to remap queue\n"); return r; } + if (reset_mode == AMDGPU_RESET_TYPE_PER_QUEUE) { + r = amdgpu_ring_test_ring(ring); + if (r) + goto pipe_reset; + } + + return amdgpu_ring_reset_helper_end(ring, timedout_fence); } From dd3d962a8efcdb43207ea893003d601ed7c9a37d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Tue, 16 Sep 2025 16:07:35 +0200 Subject: [PATCH 2076/2653] drm/amdgpu: remove leftover from enforcing isolation by VMID MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Initially we enforced isolation by reserving a VMID, but that practice was now removed. Signed-off-by: Christian König Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c index 5dd78a9cb12dd..cbdf108612d2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c @@ -594,11 +594,6 @@ void amdgpu_vmid_mgr_init(struct amdgpu_device *adev) list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru); } } - /* alloc a default reserved vmid to enforce isolation */ - for (i = 0; i < (adev->xcp_mgr ? adev->xcp_mgr->num_xcps : 1); i++) { - if (adev->enforce_isolation[i] != AMDGPU_ENFORCE_ISOLATION_DISABLE) - amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(i)); - } } /** From 9f7641297917c2b808a51ee2eb9a8c4f1dbcf83a Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Wed, 17 Sep 2025 20:12:43 +0530 Subject: [PATCH 2077/2653] drm/amdgpu: use hmm_pfns instead of array of pages MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit we dont need to allocate local array of pages to hold the pages returned by the hmm, instead we could use the hmm_range structure itself to get to hmm_pfn and get the required pages directly. This avoids call to alloc/free quite a lot. Signed-off-by: Sunil Khatri Suggested-by: Christian König Reviewed-by: Christian König Acked-by: Felix Kuehling --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 10 +++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 30 ++++--------------- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 5 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 23 +------------- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 5 ++-- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 2 +- 9 files changed, 25 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 02450d129db8c..ee518a5ef598a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1153,7 +1153,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, } #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &range); + ret = amdgpu_ttm_tt_get_user_pages(bo, &range); if (ret) { if (ret == -EAGAIN) pr_debug("Failed to get user pages, try again\n"); @@ -1190,6 +1190,9 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, pr_err("%s: Failed to reserve BO\n", __func__); goto release_out; } + + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, range); + amdgpu_bo_placement_from_domain(bo, mem->domain); ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (ret) @@ -2940,8 +2943,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* Get updated user pages */ - ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, - &mem->range); + ret = amdgpu_ttm_tt_get_user_pages(bo, &mem->range); if (ret) { pr_debug("Failed %d to get user pages\n", ret); @@ -2969,6 +2971,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, ret = 0; } + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, mem->range); #else if (!mem->user_pages) { mem->user_pages = @@ -3003,6 +3006,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, ret = 0; } #endif + mutex_lock(&process_info->notifier_lock); /* Mark the BO as valid unless it was invalidated * again concurrently. diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h index 47734741388fa..3df27ac1b56c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h @@ -39,7 +39,6 @@ struct amdgpu_bo_list_entry { struct amdgpu_bo *bo; struct amdgpu_bo_va *bo_va; uint32_t priority; - struct page **user_pages; struct hmm_range *range; #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool user_invalidated; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index a3daf201929b7..a097d4a50a05c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -910,24 +911,12 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, struct amdgpu_bo *bo = e->bo; int i; - e->user_pages = kvcalloc(bo->tbo.ttm->num_pages, - sizeof(struct page *), - GFP_KERNEL); - if (!e->user_pages) { - drm_err(adev_to_drm(p->adev), "kvmalloc_array failure\n"); - r = -ENOMEM; - goto out_free_user_pages; - } - - r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages, &e->range); - if (r) { - kvfree(e->user_pages); - e->user_pages = NULL; + r = amdgpu_ttm_tt_get_user_pages(bo, &e->range); + if (r) goto out_free_user_pages; - } for (i = 0; i < bo->tbo.ttm->num_pages; i++) { - if (bo->tbo.ttm->pages[i] != e->user_pages[i]) { + if (bo->tbo.ttm->pages[i] != hmm_pfn_to_page(e->range->hmm_pfns[i])) { userpage_invalidated = true; break; } @@ -970,7 +959,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, } if (amdgpu_ttm_tt_is_userptr(e->bo->tbo.ttm) && - e->user_invalidated && e->user_pages) { + e->user_invalidated) { amdgpu_bo_placement_from_domain(e->bo, AMDGPU_GEM_DOMAIN_CPU); r = ttm_bo_validate(&e->bo->tbo, &e->bo->placement, @@ -979,11 +968,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto out_free_user_pages; amdgpu_ttm_tt_set_user_pages(e->bo->tbo.ttm, - e->user_pages); + e->range); } - - kvfree(e->user_pages); - e->user_pages = NULL; } #else while (1) { @@ -1117,11 +1103,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { struct amdgpu_bo *bo = e->bo; - if (!e->user_pages) - continue; amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, e->range); - kvfree(e->user_pages); - e->user_pages = NULL; e->range = NULL; } #else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index cbeb2527c8aa0..eac5004cd99a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -643,8 +643,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, goto release_object; if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { - r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, - &range); + r = amdgpu_ttm_tt_get_user_pages(bo, &range); if (r) goto release_object; @@ -652,6 +651,8 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, if (r) goto user_pages_done; + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, range); + amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); amdgpu_bo_unreserve(bo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index ca7304e7f45b0..f13a169a26dbb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -842,13 +842,12 @@ const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, - void *owner, struct page **pages, + void *owner, struct hmm_range **phmm_range) { struct hmm_range *hmm_range; unsigned long end; unsigned long timeout; - unsigned long i; unsigned long *pfns; int r = 0; @@ -915,26 +914,6 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, hmm_range->start = start; hmm_range->hmm_pfns = pfns; - /* - * Due to default_flags, all pages are HMM_PFN_VALID or - * hmm_range_fault() fails. FIXME: The pages cannot be touched outside - * the notifier_lock, and mmu_interval_read_retry() must be done first. - */ - for (i = 0; pages && i < npages; i++) { -#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT - pages[i] = hmm_device_entry_to_page(hmm_range, pfns[i]); - if (unlikely(!pages[i])) { - pr_err("Page fault failed for pfn[%lu] = 0x%llx\n", - i, pfns[i]); - r = -ENOMEM; - - goto out_free_pfns; - } -#else - pages[i] = hmm_pfn_to_page(pfns[i]); -#endif - } - *phmm_range = hmm_range; return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index 38492d5c4d72b..bce7baa1adcb2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -85,7 +85,7 @@ static inline struct page *hmm_pfn_to_page(unsigned long hmm_pfn) int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, - void *owner, struct page **pages, + void *owner, struct hmm_range **phmm_range); bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 29555bbbf9bcd..d58b15803e372 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -781,7 +781,7 @@ struct amdgpu_ttm_tt { * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only * once afterwards to stop HMM tracking */ -int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct hmm_range **range) { struct ttm_tt *ttm = bo->tbo.ttm; @@ -818,7 +818,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, readonly = amdgpu_ttm_tt_is_readonly(ttm); r = amdgpu_hmm_range_get_pages(&bo->notifier, start, ttm->num_pages, - readonly, NULL, pages, range); + readonly, NULL, range); out_unlock: mmap_read_unlock(mm); if (r) @@ -958,12 +958,12 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, * that backs user memory and will ultimately be mapped into the device * address space. */ -void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) +void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct hmm_range *range) { unsigned long i; for (i = 0; i < ttm->num_pages; ++i) - ttm->pages[i] = pages ? pages[i] : NULL; + ttm->pages[i] = range ? hmm_pfn_to_page(range->hmm_pfns[i]) : NULL; } #else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 2a81a7dd10f43..46cb1ffe7f783 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -204,7 +204,7 @@ void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) -int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct hmm_range **range); void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, struct hmm_range *range); @@ -212,7 +212,6 @@ bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, struct hmm_range *range); #else static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, - struct page **pages, struct hmm_range **range) { return -EPERM; @@ -228,7 +227,7 @@ static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, } #endif -void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages); +void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct hmm_range *range); int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, uint64_t *user_addr); int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index b7babbf9b963a..ba1633781a711 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1742,7 +1742,7 @@ static int svm_range_validate_and_map(struct mm_struct *mm, WRITE_ONCE(p->svms.faulting_task, current); r = amdgpu_hmm_range_get_pages(&prange->notifier, addr, npages, - readonly, owner, NULL, + readonly, owner, &hmm_range); WRITE_ONCE(p->svms.faulting_task, NULL); if (r) From 949e3d0c458ba3270a7fd29a093968e6230015ad Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 19 Sep 2025 13:29:23 +0800 Subject: [PATCH 2078/2653] drm/amdkcl: Move pgmap to amdgpu_kfd_dev structure It's caused by the commit: 610dab11 "drm/amdkfd: Move pgmap to amdgpu_kfd_dev structure" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index a35b3b0c0d2ff..d0bb8ecf3045e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -209,7 +209,7 @@ svm_migrate_addr_to_pfn(struct amdgpu_device *adev, unsigned long addr) #ifdef HAVE_DEV_PAGEMAP_RANGE return (addr + adev->kfd.pgmap.range.start) >> PAGE_SHIFT; #else - return (addr + adev->kfd.dev->pgmap.res.start) >> PAGE_SHIFT; + return (addr + adev->kfd.pgmap.res.start) >> PAGE_SHIFT; #endif } @@ -243,7 +243,7 @@ svm_migrate_addr(struct amdgpu_device *adev, struct page *page) #ifdef HAVE_DEV_PAGEMAP_RANGE return (addr - adev->kfd.pgmap.range.start); #else - return (addr - adev->kfd.dev->pgmap.res.start); + return (addr - adev->kfd.pgmap.res.start); #endif } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index ba1633781a711..cd8f2e5b7410b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -187,7 +187,7 @@ svm_range_dma_map_dev(struct amdgpu_device *adev, struct svm_range *prange, #ifdef HAVE_DEV_PAGEMAP_RANGE bo_adev->kfd.pgmap.range.start; #else - bo_adev->kfd.dev->pgmap.res.start; + bo_adev->kfd.pgmap.res.start; #endif addr[i] |= SVM_RANGE_VRAM_DOMAIN; pr_debug_ratelimited("vram address: 0x%llx\n", addr[i]); From 8b2a767e3486764a573fe971b96edb4fe0b08925 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 23 Sep 2025 11:38:03 +0800 Subject: [PATCH 2079/2653] drm/amdkcl: wrap code under macro define HAVE_AMDKCL_HMM_MIRROR_ENABLED It's caused by the commit: 88eaa016 "drm/amdgpu: use hmm_pfns instead of array of pages Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 7 +++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 17 +++++++++++++++++ 4 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index ee518a5ef598a..66c44cc4fffdc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1191,7 +1191,9 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, goto release_out; } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, range); +#endif amdgpu_bo_placement_from_domain(bo, mem->domain); ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h index 3df27ac1b56c4..e3f75a65fcb6b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h @@ -43,6 +43,7 @@ struct amdgpu_bo_list_entry { #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool user_invalidated; #else + struct page **user_pages; int user_invalidated; struct ttm_validate_buffer tv; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index eac5004cd99a4..f6c79cb9aa3d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -643,7 +643,12 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, goto release_object; if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED r = amdgpu_ttm_tt_get_user_pages(bo, &range); +#else + r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, + &range); +#endif if (r) goto release_object; @@ -651,7 +656,9 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, if (r) goto user_pages_done; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, range); +#endif amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 46cb1ffe7f783..5d6affae526fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -204,18 +204,31 @@ void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct hmm_range **range); +#else +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, + struct hmm_range **range); +#endif void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, struct hmm_range *range); bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, struct hmm_range *range); #else +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct hmm_range **range) { return -EPERM; } +#else +static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, + struct hmm_range **range) +{ + return -EPERM; +} +#endif static inline void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, struct hmm_range *range) { @@ -227,7 +240,11 @@ static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, } #endif +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct hmm_range *range); +#else +void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages); +#endif int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, uint64_t *user_addr); int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, From 0719f5cbe5342261f041b93cd8e4a9dd81c3d35a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Fri, 19 Sep 2025 09:27:03 +0200 Subject: [PATCH 2080/2653] drm/amdgpu: revert "rework reserved VMID handling" v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit e44a0fe630c58b0a87d8281f5c1077a3479e5fce. Initially we used VMID reservation to enforce isolation between processes. That has now been replaced by proper fence handling. Both OpenGL, RADV and ROCm developers requested a way to reserve a VMID for SPM, so restore that approach by reverting back to only allowing a single process to use the reserved VMID. Only compile tested for now. v2: use -ENOENT instead of -EINVAL if VMID is not available Signed-off-by: Christian König Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 61 ++++++++++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h | 11 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 ++----- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +- 4 files changed, 50 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c index cbdf108612d2c..3ef5bc95642ca 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c @@ -275,13 +275,12 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm, { struct amdgpu_device *adev = ring->adev; unsigned vmhub = ring->vm_hub; - struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; uint64_t fence_context = adev->fence_context + ring->idx; bool needs_flush = vm->use_cpu_for_update; uint64_t updates = amdgpu_vm_tlb_seq(vm); int r; - *id = id_mgr->reserved; + *id = vm->reserved_vmid[vmhub]; if ((*id)->owner != vm->immediate.fence_context || !amdgpu_vmid_compatible(*id, job) || (*id)->flushed_updates < updates || @@ -474,40 +473,61 @@ bool amdgpu_vmid_uses_reserved(struct amdgpu_vm *vm, unsigned int vmhub) return vm->reserved_vmid[vmhub]; } -int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev, +/* + * amdgpu_vmid_alloc_reserved - reserve a specific VMID for this vm + * @adev: amdgpu device structure + * @vm: the VM to reserve an ID for + * @vmhub: the VMHUB which should be used + * + * Mostly used to have a reserved VMID for debugging and SPM. + * + * Returns: 0 for success, -ENOENT if an ID is already reserved. + */ +int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned vmhub) { struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; + struct amdgpu_vmid *id; + int r = 0; mutex_lock(&id_mgr->lock); - - ++id_mgr->reserved_use_count; - if (!id_mgr->reserved) { - struct amdgpu_vmid *id; - - id = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vmid, - list); - /* Remove from normal round robin handling */ - list_del_init(&id->list); - id_mgr->reserved = id; + if (vm->reserved_vmid[vmhub]) + goto unlock; + if (id_mgr->reserved_vmid) { + r = -ENOENT; + goto unlock; } - + /* Remove from normal round robin handling */ + id = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vmid, list); + list_del_init(&id->list); + vm->reserved_vmid[vmhub] = id; + id_mgr->reserved_vmid = true; mutex_unlock(&id_mgr->lock); + return 0; +unlock: + mutex_unlock(&id_mgr->lock); + return r; } -void amdgpu_vmid_free_reserved(struct amdgpu_device *adev, +/* + * amdgpu_vmid_free_reserved - free up a reserved VMID again + * @adev: amdgpu device structure + * @vm: the VM with the reserved ID + * @vmhub: the VMHUB which should be used + */ +void amdgpu_vmid_free_reserved(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned vmhub) { struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; mutex_lock(&id_mgr->lock); - if (!--id_mgr->reserved_use_count) { - /* give the reserved ID back to normal round robin */ - list_add(&id_mgr->reserved->list, &id_mgr->ids_lru); - id_mgr->reserved = NULL; + if (vm->reserved_vmid[vmhub]) { + list_add(&vm->reserved_vmid[vmhub]->list, + &id_mgr->ids_lru); + vm->reserved_vmid[vmhub] = NULL; + id_mgr->reserved_vmid = false; } - mutex_unlock(&id_mgr->lock); } @@ -574,7 +594,6 @@ void amdgpu_vmid_mgr_init(struct amdgpu_device *adev) mutex_init(&id_mgr->lock); INIT_LIST_HEAD(&id_mgr->ids_lru); - id_mgr->reserved_use_count = 0; /* for GC <10, SDMA uses MMHUB so use first_kfd_vmid for both GC and MM */ if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 0, 0)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h index 240fa67512602..b3649cd3af569 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h @@ -67,8 +67,7 @@ struct amdgpu_vmid_mgr { unsigned num_ids; struct list_head ids_lru; struct amdgpu_vmid ids[AMDGPU_NUM_VMID]; - struct amdgpu_vmid *reserved; - unsigned int reserved_use_count; + bool reserved_vmid; }; int amdgpu_pasid_alloc(unsigned int bits); @@ -79,10 +78,10 @@ void amdgpu_pasid_free_delayed(struct dma_resv *resv, bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev, struct amdgpu_vmid *id); bool amdgpu_vmid_uses_reserved(struct amdgpu_vm *vm, unsigned int vmhub); -int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev, - unsigned vmhub); -void amdgpu_vmid_free_reserved(struct amdgpu_device *adev, - unsigned vmhub); +int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev, struct amdgpu_vm *vm, + unsigned vmhub); +void amdgpu_vmid_free_reserved(struct amdgpu_device *adev, struct amdgpu_vm *vm, + unsigned vmhub); int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring, struct amdgpu_job *job, struct dma_fence **fence); void amdgpu_vmid_reset(struct amdgpu_device *adev, unsigned vmhub, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 5f0aa7336828b..5112168a8caa7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2848,10 +2848,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) dma_fence_put(vm->last_update); for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) { - if (vm->reserved_vmid[i]) { - amdgpu_vmid_free_reserved(adev, i); - vm->reserved_vmid[i] = false; - } + amdgpu_vmid_free_reserved(adev, vm, i); } ttm_lru_bulk_move_fini(&adev->mman.bdev, &vm->lru_bulk_move); @@ -2957,6 +2954,7 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) union drm_amdgpu_vm *args = data; struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct amdgpu_vm *vm = &fpriv->vm; /* No valid flags defined yet */ if (args->in.flags) @@ -2965,17 +2963,10 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) switch (args->in.op) { case AMDGPU_VM_OP_RESERVE_VMID: /* We only have requirement to reserve vmid from gfxhub */ - if (!fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) { - amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0)); - fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = true; - } - + amdgpu_vmid_alloc_reserved(adev, vm, AMDGPU_GFXHUB(0)); break; case AMDGPU_VM_OP_UNRESERVE_VMID: - if (fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) { - amdgpu_vmid_free_reserved(adev, AMDGPU_GFXHUB(0)); - fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = false; - } + amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB(0)); break; default: return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 060650b0602de..a4461753a4844 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -419,7 +419,7 @@ struct amdgpu_vm { struct dma_fence *last_unlocked; unsigned int pasid; - bool reserved_vmid[AMDGPU_MAX_VMHUBS]; + struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS]; /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ bool use_cpu_for_update; From e2f2ea553428afc8942dbe623cea2b2adad622e2 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 24 Sep 2025 10:44:48 +0800 Subject: [PATCH 2081/2653] drm/amdkcl: revert "rework reserved VMID handling" v2 on non-upstream code It's caused by the commit: c2e6ff53 "drm/amdgpu: revert "rework reserved VMID handling" v2" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index 52cc184613f21..3d60abcad5861 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -59,12 +59,9 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, int xcc_id, if (!adev->gfx.rlc.funcs->update_spm_vmid) return -EINVAL; - if (!vm->reserved_vmid[AMDGPU_GFXHUB(0)]) { - r = amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0)); + r = amdgpu_vmid_alloc_reserved(adev, vm, AMDGPU_GFXHUB(0)); if (r) return r; - vm->reserved_vmid[AMDGPU_GFXHUB(0)] = true; - } /* init spm vmid with 0x0 */ adev->gfx.rlc.funcs->update_spm_vmid(adev, xcc_id, NULL, 0); @@ -89,10 +86,7 @@ void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, int xcc_id, struc amdgpu_ring_commit(kiq_ring); spin_unlock(&adev->gfx.kiq[xcc_id].ring_lock); - if (vm->reserved_vmid[AMDGPU_GFXHUB(0)]) { - amdgpu_vmid_free_reserved(adev,AMDGPU_GFXHUB(0)); - vm->reserved_vmid[AMDGPU_GFXHUB(0)] = false; - } + amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB(0)); /* revert spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) From 3e03de2ce280016995971d301a2ca99a0937d560 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 24 Mar 2025 15:10:44 +0800 Subject: [PATCH 2082/2653] drm/amd/ras: Add rascore status definition Add rascore status definition. V5: Merge the previous empty files. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/ras/rascore/Makefile | 0 .../gpu/drm/amd/ras/rascore/ras_core_status.h | 37 +++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/Makefile create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_core_status.h diff --git a/drivers/gpu/drm/amd/ras/rascore/Makefile b/drivers/gpu/drm/amd/ras/rascore/Makefile new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core_status.h b/drivers/gpu/drm/amd/ras/rascore/ras_core_status.h new file mode 100644 index 0000000000000..144fbe4ceb9a0 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core_status.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __RAS_CORE_STATUS_H__ +#define __RAS_CORE_STATUS_H__ + +#define RAS_CORE_OK 0 +#define RAS_CORE_NOT_SUPPORTED 248 +#define RAS_CORE_FAIL_ERROR_QUERY 249 +#define RAS_CORE_FAIL_ERROR_INJECTION 250 +#define RAS_CORE_FAIL_FATAL_RECOVERY 251 +#define RAS_CORE_FAIL_POISON_CONSUMPTION 252 +#define RAS_CORE_FAIL_POISON_CREATION 253 +#define RAS_CORE_FAIL_NO_VALID_BANKS 254 +#define RAS_CORE_GPU_IN_MODE1_RESET 255 +#endif From ade9ad1e7862f0ab40ba5a707be2c341e59f55d6 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 17:16:54 +0800 Subject: [PATCH 2083/2653] drm/amd/ras: Add ras aca parser v1.0 Add ras aca parser v1.0. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/ras/rascore/ras_aca_v1_0.c | 379 ++++++++++++++++++ .../gpu/drm/amd/ras/rascore/ras_aca_v1_0.h | 71 ++++ 2 files changed, 450 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.h diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c b/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c new file mode 100644 index 0000000000000..29df98948703b --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c @@ -0,0 +1,379 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "ras.h" +#include "ras_aca.h" +#include "ras_core_status.h" +#include "ras_aca_v1_0.h" + +struct ras_aca_hwip { + int hwid; + int mcatype; +}; + +static struct ras_aca_hwip aca_hwid_mcatypes[ACA_ECC_HWIP_COUNT] = { + [ACA_ECC_HWIP__SMU] = {0x01, 0x01}, + [ACA_ECC_HWIP__PCS_XGMI] = {0x50, 0x00}, + [ACA_ECC_HWIP__UMC] = {0x96, 0x00}, +}; + +static int aca_decode_bank_info(struct aca_block *aca_blk, + struct aca_bank_reg *bank, struct aca_ecc_info *info) +{ + u64 ipid; + u32 instidhi, instidlo; + + ipid = bank->regs[ACA_REG_IDX__IPID]; + info->hwid = ACA_REG_IPID_HARDWAREID(ipid); + info->mcatype = ACA_REG_IPID_MCATYPE(ipid); + /* + * Unified DieID Format: SAASS. A:AID, S:Socket. + * Unified DieID[4:4] = InstanceId[0:0] + * Unified DieID[0:3] = InstanceIdHi[0:3] + */ + instidhi = ACA_REG_IPID_INSTANCEIDHI(ipid); + instidlo = ACA_REG_IPID_INSTANCEIDLO(ipid); + info->die_id = ((instidhi >> 2) & 0x03); + info->socket_id = ((instidlo & 0x1) << 2) | (instidhi & 0x03); + + if ((aca_blk->blk_info->hwip == ACA_ECC_HWIP__SMU) && + (aca_blk->blk_info->ras_block_id == RAS_BLOCK_ID__GFX)) + info->xcd_id = + ((instidlo & GENMASK_ULL(31, 1)) == mmSMNAID_XCD0_MCA_SMU) ? 0 : 1; + + return 0; +} + +static bool aca_check_bank_hwip(struct aca_bank_reg *bank, enum aca_ecc_hwip type) +{ + struct ras_aca_hwip *hwip; + int hwid, mcatype; + u64 ipid; + + if (!bank || (type == ACA_ECC_HWIP__UNKNOWN)) + return false; + + hwip = &aca_hwid_mcatypes[type]; + if (!hwip->hwid) + return false; + + ipid = bank->regs[ACA_REG_IDX__IPID]; + hwid = ACA_REG_IPID_HARDWAREID(ipid); + mcatype = ACA_REG_IPID_MCATYPE(ipid); + + return hwip->hwid == hwid && hwip->mcatype == mcatype; +} + +static bool aca_match_bank_default(struct aca_block *aca_blk, void *data) +{ + return aca_check_bank_hwip((struct aca_bank_reg *)data, aca_blk->blk_info->hwip); +} + +static bool aca_match_gfx_bank(struct aca_block *aca_blk, void *data) +{ + struct aca_bank_reg *bank = (struct aca_bank_reg *)data; + u32 instlo; + + if (!aca_check_bank_hwip(bank, aca_blk->blk_info->hwip)) + return false; + + instlo = ACA_REG_IPID_INSTANCEIDLO(bank->regs[ACA_REG_IDX__IPID]); + instlo &= GENMASK_ULL(31, 1); + switch (instlo) { + case mmSMNAID_XCD0_MCA_SMU: + case mmSMNAID_XCD1_MCA_SMU: + case mmSMNXCD_XCD0_MCA_SMU: + return true; + default: + break; + } + + return false; +} + +static bool aca_match_sdma_bank(struct aca_block *aca_blk, void *data) +{ + struct aca_bank_reg *bank = (struct aca_bank_reg *)data; + /* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */ + static int sdma_err_codes[] = { 33, 34, 35, 36 }; + u32 instlo; + int errcode, i; + + if (!aca_check_bank_hwip(bank, aca_blk->blk_info->hwip)) + return false; + + instlo = ACA_REG_IPID_INSTANCEIDLO(bank->regs[ACA_REG_IDX__IPID]); + instlo &= GENMASK_ULL(31, 1); + if (instlo != mmSMNAID_AID0_MCA_SMU) + return false; + + errcode = ACA_REG_SYND_ERRORINFORMATION(bank->regs[ACA_REG_IDX__SYND]); + errcode &= 0xff; + + /* Check SDMA error codes */ + for (i = 0; i < ARRAY_SIZE(sdma_err_codes); i++) { + if (errcode == sdma_err_codes[i]) + return true; + } + + return false; +} + +static bool aca_match_mmhub_bank(struct aca_block *aca_blk, void *data) +{ + struct aca_bank_reg *bank = (struct aca_bank_reg *)data; + /* reference to smu driver if header file */ + const int mmhub_err_codes[] = { + 0, 1, 2, 3, 4, /* CODE_DAGB0 - 4 */ + 5, 6, 7, 8, 9, /* CODE_EA0 - 4 */ + 10, /* CODE_UTCL2_ROUTER */ + 11, /* CODE_VML2 */ + 12, /* CODE_VML2_WALKER */ + 13, /* CODE_MMCANE */ + }; + u32 instlo; + int errcode, i; + + if (!aca_check_bank_hwip(bank, aca_blk->blk_info->hwip)) + return false; + + instlo = ACA_REG_IPID_INSTANCEIDLO(bank->regs[ACA_REG_IDX__IPID]); + instlo &= GENMASK_ULL(31, 1); + if (instlo != mmSMNAID_AID0_MCA_SMU) + return false; + + errcode = ACA_REG_SYND_ERRORINFORMATION(bank->regs[ACA_REG_IDX__SYND]); + errcode &= 0xff; + + /* Check MMHUB error codes */ + for (i = 0; i < ARRAY_SIZE(mmhub_err_codes); i++) { + if (errcode == mmhub_err_codes[i]) + return true; + } + + return false; +} + +static bool aca_check_umc_de(struct ras_core_context *ras_core, uint64_t mc_umc_status) +{ + return (ras_core->poison_supported && + ACA_REG_STATUS_VAL(mc_umc_status) && + ACA_REG_STATUS_DEFERRED(mc_umc_status)); +} + +static bool aca_check_umc_ue(struct ras_core_context *ras_core, uint64_t mc_umc_status) +{ + if (aca_check_umc_de(ras_core, mc_umc_status)) + return false; + + return (ACA_REG_STATUS_VAL(mc_umc_status) && + (ACA_REG_STATUS_PCC(mc_umc_status) || + ACA_REG_STATUS_UC(mc_umc_status) || + ACA_REG_STATUS_TCC(mc_umc_status))); +} + +static bool aca_check_umc_ce(struct ras_core_context *ras_core, uint64_t mc_umc_status) +{ + if (aca_check_umc_de(ras_core, mc_umc_status)) + return false; + + return (ACA_REG_STATUS_VAL(mc_umc_status) && + (ACA_REG_STATUS_CECC(mc_umc_status) || + (ACA_REG_STATUS_UECC(mc_umc_status) && + ACA_REG_STATUS_UC(mc_umc_status) == 0) || + /* Identify data parity error in replay mode */ + ((ACA_REG_STATUS_ERRORCODEEXT(mc_umc_status) == 0x5 || + ACA_REG_STATUS_ERRORCODEEXT(mc_umc_status) == 0xb) && + !(aca_check_umc_ue(ras_core, mc_umc_status))))); +} + +static int aca_parse_umc_bank(struct ras_core_context *ras_core, + struct aca_block *ras_blk, void *data, void *buf) +{ + struct aca_bank_reg *bank = (struct aca_bank_reg *)data; + struct aca_bank_ecc *ecc = (struct aca_bank_ecc *)buf; + struct aca_ecc_info bank_info; + uint32_t ext_error_code; + uint64_t status0; + + status0 = bank->regs[ACA_REG_IDX__STATUS]; + if (!ACA_REG_STATUS_VAL(status0)) + return 0; + + memset(&bank_info, 0, sizeof(bank_info)); + aca_decode_bank_info(ras_blk, bank, &bank_info); + memcpy(&ecc->bank_info, &bank_info, sizeof(bank_info)); + ecc->bank_info.status = bank->regs[ACA_REG_IDX__STATUS]; + ecc->bank_info.ipid = bank->regs[ACA_REG_IDX__IPID]; + ecc->bank_info.addr = bank->regs[ACA_REG_IDX__ADDR]; + + ext_error_code = ACA_REG_STATUS_ERRORCODEEXT(status0); + + if (aca_check_umc_de(ras_core, status0)) + ecc->de_count = 1; + else if (aca_check_umc_ue(ras_core, status0)) + ecc->ue_count = ext_error_code ? + 1 : ACA_REG_MISC0_ERRCNT(bank->regs[ACA_REG_IDX__MISC0]); + else if (aca_check_umc_ce(ras_core, status0)) + ecc->ce_count = ext_error_code ? + 1 : ACA_REG_MISC0_ERRCNT(bank->regs[ACA_REG_IDX__MISC0]); + + return 0; +} + +static bool aca_check_bank_is_de(struct ras_core_context *ras_core, + uint64_t status) +{ + return (ACA_REG_STATUS_POISON(status) || + ACA_REG_STATUS_DEFERRED(status)); +} + +static int aca_parse_bank_default(struct ras_core_context *ras_core, + struct aca_block *ras_blk, + void *data, void *buf) +{ + struct aca_bank_reg *bank = (struct aca_bank_reg *)data; + struct aca_bank_ecc *ecc = (struct aca_bank_ecc *)buf; + struct aca_ecc_info bank_info; + u64 misc0 = bank->regs[ACA_REG_IDX__MISC0]; + u64 status = bank->regs[ACA_REG_IDX__STATUS]; + + memset(&bank_info, 0, sizeof(bank_info)); + aca_decode_bank_info(ras_blk, bank, &bank_info); + memcpy(&ecc->bank_info, &bank_info, sizeof(bank_info)); + ecc->bank_info.status = status; + ecc->bank_info.ipid = bank->regs[ACA_REG_IDX__IPID]; + ecc->bank_info.addr = bank->regs[ACA_REG_IDX__ADDR]; + + if (aca_check_bank_is_de(ras_core, status)) { + ecc->de_count = 1; + } else { + if (bank->ecc_type == RAS_ERR_TYPE__UE) + ecc->ue_count = 1; + else if (bank->ecc_type == RAS_ERR_TYPE__CE) + ecc->ce_count = ACA_REG_MISC0_ERRCNT(misc0); + } + + return 0; +} + +static int aca_parse_xgmi_bank(struct ras_core_context *ras_core, + struct aca_block *ras_blk, + void *data, void *buf) +{ + struct aca_bank_reg *bank = (struct aca_bank_reg *)data; + struct aca_bank_ecc *ecc = (struct aca_bank_ecc *)buf; + struct aca_ecc_info bank_info; + u64 status, count; + int ext_error_code; + + memset(&bank_info, 0, sizeof(bank_info)); + aca_decode_bank_info(ras_blk, bank, &bank_info); + memcpy(&ecc->bank_info, &bank_info, sizeof(bank_info)); + ecc->bank_info.status = bank->regs[ACA_REG_IDX__STATUS]; + ecc->bank_info.ipid = bank->regs[ACA_REG_IDX__IPID]; + ecc->bank_info.addr = bank->regs[ACA_REG_IDX__ADDR]; + + status = bank->regs[ACA_REG_IDX__STATUS]; + ext_error_code = ACA_REG_STATUS_ERRORCODEEXT(status); + + count = ACA_REG_MISC0_ERRCNT(bank->regs[ACA_REG_IDX__MISC0]); + if (bank->ecc_type == RAS_ERR_TYPE__UE) { + if (ext_error_code != 0 && ext_error_code != 9) + count = 0ULL; + ecc->ue_count = count; + } else if (bank->ecc_type == RAS_ERR_TYPE__CE) { + count = ext_error_code == 6 ? count : 0ULL; + ecc->ce_count = count; + } + + return 0; +} + +static const struct aca_block_info aca_v1_0_umc = { + .name = "umc", + .ras_block_id = RAS_BLOCK_ID__UMC, + .hwip = ACA_ECC_HWIP__UMC, + .mask = ACA_ERROR__UE_MASK | ACA_ERROR__CE_MASK | ACA_ERROR__DE_MASK, + .bank_ops = { + .bank_match = aca_match_bank_default, + .bank_parse = aca_parse_umc_bank, + }, +}; + +static const struct aca_block_info aca_v1_0_gfx = { + .name = "gfx", + .ras_block_id = RAS_BLOCK_ID__GFX, + .hwip = ACA_ECC_HWIP__SMU, + .mask = ACA_ERROR__UE_MASK | ACA_ERROR__CE_MASK, + .bank_ops = { + .bank_match = aca_match_gfx_bank, + .bank_parse = aca_parse_bank_default, + }, +}; + +static const struct aca_block_info aca_v1_0_sdma = { + .name = "sdma", + .ras_block_id = RAS_BLOCK_ID__SDMA, + .hwip = ACA_ECC_HWIP__SMU, + .mask = ACA_ERROR__UE_MASK, + .bank_ops = { + .bank_match = aca_match_sdma_bank, + .bank_parse = aca_parse_bank_default, + }, +}; + +static const struct aca_block_info aca_v1_0_mmhub = { + .name = "mmhub", + .ras_block_id = RAS_BLOCK_ID__MMHUB, + .hwip = ACA_ECC_HWIP__SMU, + .mask = ACA_ERROR__UE_MASK, + .bank_ops = { + .bank_match = aca_match_mmhub_bank, + .bank_parse = aca_parse_bank_default, + }, +}; + +static const struct aca_block_info aca_v1_0_xgmi = { + .name = "xgmi", + .ras_block_id = RAS_BLOCK_ID__XGMI_WAFL, + .hwip = ACA_ECC_HWIP__PCS_XGMI, + .mask = ACA_ERROR__UE_MASK | ACA_ERROR__CE_MASK, + .bank_ops = { + .bank_match = aca_match_bank_default, + .bank_parse = aca_parse_xgmi_bank, + }, +}; + +static const struct aca_block_info *aca_block_info_v1_0[] = { + &aca_v1_0_umc, + &aca_v1_0_gfx, + &aca_v1_0_sdma, + &aca_v1_0_mmhub, + &aca_v1_0_xgmi, +}; + +const struct ras_aca_ip_func ras_aca_func_v1_0 = { + .block_num = ARRAY_SIZE(aca_block_info_v1_0), + .block_info = aca_block_info_v1_0, +}; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.h b/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.h new file mode 100644 index 0000000000000..40e5d94b037fe --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __RAS_ACA_V1_0_H__ +#define __RAS_ACA_V1_0_H__ +#include "ras.h" + +#define ACA__REG__FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> l) +#define ACA_REG_STATUS_VAL(x) ACA__REG__FIELD(x, 63, 63) +#define ACA_REG_STATUS_OVERFLOW(x) ACA__REG__FIELD(x, 62, 62) +#define ACA_REG_STATUS_UC(x) ACA__REG__FIELD(x, 61, 61) +#define ACA_REG_STATUS_EN(x) ACA__REG__FIELD(x, 60, 60) +#define ACA_REG_STATUS_MISCV(x) ACA__REG__FIELD(x, 59, 59) +#define ACA_REG_STATUS_ADDRV(x) ACA__REG__FIELD(x, 58, 58) +#define ACA_REG_STATUS_PCC(x) ACA__REG__FIELD(x, 57, 57) +#define ACA_REG_STATUS_ERRCOREIDVAL(x) ACA__REG__FIELD(x, 56, 56) +#define ACA_REG_STATUS_TCC(x) ACA__REG__FIELD(x, 55, 55) +#define ACA_REG_STATUS_SYNDV(x) ACA__REG__FIELD(x, 53, 53) +#define ACA_REG_STATUS_CECC(x) ACA__REG__FIELD(x, 46, 46) +#define ACA_REG_STATUS_UECC(x) ACA__REG__FIELD(x, 45, 45) +#define ACA_REG_STATUS_DEFERRED(x) ACA__REG__FIELD(x, 44, 44) +#define ACA_REG_STATUS_POISON(x) ACA__REG__FIELD(x, 43, 43) +#define ACA_REG_STATUS_SCRUB(x) ACA__REG__FIELD(x, 40, 40) +#define ACA_REG_STATUS_ERRCOREID(x) ACA__REG__FIELD(x, 37, 32) +#define ACA_REG_STATUS_ADDRLSB(x) ACA__REG__FIELD(x, 29, 24) +#define ACA_REG_STATUS_ERRORCODEEXT(x) ACA__REG__FIELD(x, 21, 16) +#define ACA_REG_STATUS_ERRORCODE(x) ACA__REG__FIELD(x, 15, 0) + +#define ACA_REG_IPID_MCATYPE(x) ACA__REG__FIELD(x, 63, 48) +#define ACA_REG_IPID_INSTANCEIDHI(x) ACA__REG__FIELD(x, 47, 44) +#define ACA_REG_IPID_HARDWAREID(x) ACA__REG__FIELD(x, 43, 32) +#define ACA_REG_IPID_INSTANCEIDLO(x) ACA__REG__FIELD(x, 31, 0) + +#define ACA_REG_MISC0_VALID(x) ACA__REG__FIELD(x, 63, 63) +#define ACA_REG_MISC0_OVRFLW(x) ACA__REG__FIELD(x, 48, 48) +#define ACA_REG_MISC0_ERRCNT(x) ACA__REG__FIELD(x, 43, 32) + +#define ACA_REG_SYND_ERRORINFORMATION(x) ACA__REG__FIELD(x, 17, 0) + +/* NOTE: The following codes refers to the smu header file */ +#define ACA_EXTERROR_CODE_CE 0x3a +#define ACA_EXTERROR_CODE_FAULT 0x3b + +#define mmSMNAID_XCD0_MCA_SMU 0x36430400 /* SMN AID XCD0 */ +#define mmSMNAID_XCD1_MCA_SMU 0x38430400 /* SMN AID XCD1 */ +#define mmSMNXCD_XCD0_MCA_SMU 0x40430400 /* SMN XCD XCD0 */ +#define mmSMNAID_AID0_MCA_SMU 0x03b30400 /* SMN AID AID0 */ + +extern const struct ras_aca_ip_func ras_aca_func_v1_0; +#endif From 2373adca26959bed1ed352b97c67424f872af405 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 17:15:59 +0800 Subject: [PATCH 2084/2653] drm/amd/ras: Add aca common ras functions Add aca common ras functions: 1. Aca hw init/fini. 2. Get ecc count of each ras block. 3. Update query ecc count from mp1. 4. Clear ras block ecc count. V3: Update the calling function. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/ras/rascore/ras_aca.c | 672 ++++++++++++++++++++++ drivers/gpu/drm/amd/ras/rascore/ras_aca.h | 164 ++++++ 2 files changed, 836 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_aca.c create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_aca.h diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_aca.c b/drivers/gpu/drm/amd/ras/rascore/ras_aca.c new file mode 100644 index 0000000000000..f9b8a1fa4f1fc --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_aca.c @@ -0,0 +1,672 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "ras.h" +#include "ras_aca.h" +#include "ras_aca_v1_0.h" +#include "ras_mp1_v13_0.h" + +#define ACA_MARK_FATAL_FLAG 0x100 +#define ACA_MARK_UE_READ_FLAG 0x1 + +#define blk_name(block_id) ras_core_get_ras_block_name(block_id) + +static struct aca_regs_dump { + const char *name; + int reg_idx; +} aca_regs[] = { + {"CONTROL", ACA_REG_IDX__CTL}, + {"STATUS", ACA_REG_IDX__STATUS}, + {"ADDR", ACA_REG_IDX__ADDR}, + {"MISC", ACA_REG_IDX__MISC0}, + {"CONFIG", ACA_REG_IDX__CONFG}, + {"IPID", ACA_REG_IDX__IPID}, + {"SYND", ACA_REG_IDX__SYND}, + {"DESTAT", ACA_REG_IDX__DESTAT}, + {"DEADDR", ACA_REG_IDX__DEADDR}, + {"CONTROL_MASK", ACA_REG_IDX__CTL_MASK}, +}; + + +static void aca_report_ecc_info(struct ras_core_context *ras_core, + u64 seq_no, u32 blk, u32 skt, u32 aid, + struct aca_aid_ecc *aid_ecc, + struct aca_bank_ecc *new_ecc) +{ + struct aca_ecc_count ecc_count = {0}; + + ecc_count.new_ue_count = new_ecc->ue_count; + ecc_count.new_de_count = new_ecc->de_count; + ecc_count.new_ce_count = new_ecc->ce_count; + if (blk == RAS_BLOCK_ID__GFX) { + struct aca_ecc_count *xcd_ecc; + int xcd_id; + + for (xcd_id = 0; xcd_id < aid_ecc->xcd.xcd_num; xcd_id++) { + xcd_ecc = &aid_ecc->xcd.xcd[xcd_id].ecc_err; + ecc_count.total_ue_count += xcd_ecc->total_ue_count; + ecc_count.total_de_count += xcd_ecc->total_de_count; + ecc_count.total_ce_count += xcd_ecc->total_ce_count; + } + } else { + ecc_count.total_ue_count = aid_ecc->ecc_err.total_ue_count; + ecc_count.total_de_count = aid_ecc->ecc_err.total_de_count; + ecc_count.total_ce_count = aid_ecc->ecc_err.total_ce_count; + } + + if (ecc_count.new_ue_count) { + RAS_DEV_INFO(ras_core->dev, + "{%llu} socket: %d, die: %d, %u new uncorrectable hardware errors detected in %s block\n", + seq_no, skt, aid, ecc_count.new_ue_count, blk_name(blk)); + RAS_DEV_INFO(ras_core->dev, + "{%llu} socket: %d, die: %d, %u uncorrectable hardware errors detected in total in %s block\n", + seq_no, skt, aid, ecc_count.total_ue_count, blk_name(blk)); + } + + if (ecc_count.new_de_count) { + RAS_DEV_INFO(ras_core->dev, + "{%llu} socket: %d, die: %d, %u new %s detected in %s block\n", + seq_no, skt, aid, ecc_count.new_de_count, + (blk == RAS_BLOCK_ID__UMC) ? + "deferred hardware errors" : "poison consumption", + blk_name(blk)); + RAS_DEV_INFO(ras_core->dev, + "{%llu} socket: %d, die: %d, %u %s detected in total in %s block\n", + seq_no, skt, aid, ecc_count.total_de_count, + (blk == RAS_BLOCK_ID__UMC) ? + "deferred hardware errors" : "poison consumption", + blk_name(blk)); + } + + if (ecc_count.new_ce_count) { + RAS_DEV_INFO(ras_core->dev, + "{%llu} socket: %d, die: %d, %u new correctable hardware errors detected in %s block\n", + seq_no, skt, aid, ecc_count.new_ce_count, blk_name(blk)); + RAS_DEV_INFO(ras_core->dev, + "{%llu} socket: %d, die: %d, %u correctable hardware errors detected in total in %s block\n", + seq_no, skt, aid, ecc_count.total_ce_count, blk_name(blk)); + } +} + +static void aca_bank_log(struct ras_core_context *ras_core, + int idx, int total, struct aca_bank_reg *bank, + struct aca_bank_ecc *bank_ecc) +{ + int i; + + RAS_DEV_INFO(ras_core->dev, + "{%llu}" RAS_HW_ERR "Accelerator Check Architecture events logged\n", + bank->seq_no); + /* plus 1 for output format, e.g: ACA[08/08]: xxxx */ + for (i = 0; i < ARRAY_SIZE(aca_regs); i++) + RAS_DEV_INFO(ras_core->dev, + "{%llu}" RAS_HW_ERR "ACA[%02d/%02d].%s=0x%016llx\n", + bank->seq_no, idx + 1, total, + aca_regs[i].name, bank->regs[aca_regs[i].reg_idx]); +} + +static void aca_log_bank_data(struct ras_core_context *ras_core, + struct aca_bank_reg *bank, struct aca_bank_ecc *bank_ecc, + struct ras_log_batch_tag *batch) +{ + if (bank_ecc->ue_count) + ras_log_ring_add_log_event(ras_core, RAS_LOG_EVENT_UE, bank->regs, batch); + else if (bank_ecc->de_count) + ras_log_ring_add_log_event(ras_core, RAS_LOG_EVENT_DE, bank->regs, batch); + else + ras_log_ring_add_log_event(ras_core, RAS_LOG_EVENT_CE, bank->regs, batch); +} + +static int aca_get_bank_count(struct ras_core_context *ras_core, + enum ras_err_type type, u32 *count) +{ + return ras_mp1_get_bank_count(ras_core, type, count); +} + +static bool aca_match_bank(struct aca_block *aca_blk, struct aca_bank_reg *bank) +{ + const struct aca_bank_hw_ops *bank_ops; + + if (!aca_blk->blk_info) + return false; + + bank_ops = &aca_blk->blk_info->bank_ops; + if (!bank_ops->bank_match) + return false; + + return bank_ops->bank_match(aca_blk, bank); +} + +static int aca_parse_bank(struct ras_core_context *ras_core, + struct aca_block *aca_blk, + struct aca_bank_reg *bank, + struct aca_bank_ecc *ecc) +{ + const struct aca_bank_hw_ops *bank_ops = &aca_blk->blk_info->bank_ops; + + if (!bank_ops || !bank_ops->bank_parse) + return -RAS_CORE_NOT_SUPPORTED; + + return bank_ops->bank_parse(ras_core, aca_blk, bank, ecc); +} + +static int aca_check_block_ecc_info(struct ras_core_context *ras_core, + struct aca_block *aca_blk, struct aca_ecc_info *info) +{ + if (info->socket_id >= aca_blk->ecc.socket_num_per_hive) { + RAS_DEV_ERR(ras_core->dev, + "Socket id (%d) is out of config! max:%u\n", + info->socket_id, aca_blk->ecc.socket_num_per_hive); + return -ENODATA; + } + + if (info->die_id >= aca_blk->ecc.socket[info->socket_id].aid_num) { + RAS_DEV_ERR(ras_core->dev, + "Die id (%d) is out of config! max:%u\n", + info->die_id, aca_blk->ecc.socket[info->socket_id].aid_num); + return -ENODATA; + } + + if ((aca_blk->blk_info->ras_block_id == RAS_BLOCK_ID__GFX) && + (info->xcd_id >= + aca_blk->ecc.socket[info->socket_id].aid[info->die_id].xcd.xcd_num)) { + RAS_DEV_ERR(ras_core->dev, + "Xcd id (%d) is out of config! max:%u\n", + info->xcd_id, + aca_blk->ecc.socket[info->socket_id].aid[info->die_id].xcd.xcd_num); + return -ENODATA; + } + + return 0; +} + +static int aca_log_bad_bank(struct ras_core_context *ras_core, + struct aca_block *aca_blk, struct aca_bank_reg *bank, + struct aca_bank_ecc *bank_ecc) +{ + struct aca_ecc_info *info; + struct aca_ecc_count *ecc_err; + struct aca_aid_ecc *aid_ecc; + int ret; + + info = &bank_ecc->bank_info; + + ret = aca_check_block_ecc_info(ras_core, aca_blk, info); + if (ret) + return ret; + + mutex_lock(&ras_core->ras_aca.aca_lock); + aid_ecc = &aca_blk->ecc.socket[info->socket_id].aid[info->die_id]; + if (aca_blk->blk_info->ras_block_id == RAS_BLOCK_ID__GFX) + ecc_err = &aid_ecc->xcd.xcd[info->xcd_id].ecc_err; + else + ecc_err = &aid_ecc->ecc_err; + + ecc_err->new_ce_count += bank_ecc->ce_count; + ecc_err->total_ce_count += bank_ecc->ce_count; + ecc_err->new_ue_count += bank_ecc->ue_count; + ecc_err->total_ue_count += bank_ecc->ue_count; + ecc_err->new_de_count += bank_ecc->de_count; + ecc_err->total_de_count += bank_ecc->de_count; + mutex_unlock(&ras_core->ras_aca.aca_lock); + + if ((aca_blk->blk_info->ras_block_id == RAS_BLOCK_ID__UMC) && + bank_ecc->de_count) { + struct ras_bank_ecc ras_ecc = {0}; + + ras_ecc.nps = ras_core_get_curr_nps_mode(ras_core); + ras_ecc.addr = bank_ecc->bank_info.addr; + ras_ecc.ipid = bank_ecc->bank_info.ipid; + ras_ecc.status = bank_ecc->bank_info.status; + ras_ecc.seq_no = bank->seq_no; + + if (ras_core_gpu_in_reset(ras_core)) + ras_umc_log_bad_bank_pending(ras_core, &ras_ecc); + else + ras_umc_log_bad_bank(ras_core, &ras_ecc); + } + + aca_report_ecc_info(ras_core, + bank->seq_no, aca_blk->blk_info->ras_block_id, info->socket_id, info->die_id, + &aca_blk->ecc.socket[info->socket_id].aid[info->die_id], bank_ecc); + + return 0; +} + +static struct aca_block *aca_get_bank_aca_block(struct ras_core_context *ras_core, + struct aca_bank_reg *bank) +{ + int i = 0; + + for (i = 0; i < RAS_BLOCK_ID__LAST; i++) + if (aca_match_bank(&ras_core->ras_aca.aca_blk[i], bank)) + return &ras_core->ras_aca.aca_blk[i]; + + return NULL; +} + +static int aca_dump_bank(struct ras_core_context *ras_core, u32 ecc_type, + int idx, void *data) +{ + struct aca_bank_reg *bank = (struct aca_bank_reg *)data; + int i, ret, reg_cnt; + + reg_cnt = min_t(int, 16, ARRAY_SIZE(bank->regs)); + for (i = 0; i < reg_cnt; i++) { + ret = ras_mp1_dump_bank(ras_core, ecc_type, idx, i, &bank->regs[i]); + if (ret) + return ret; + } + + return 0; +} + +static uint64_t aca_get_bank_seqno(struct ras_core_context *ras_core, + enum ras_err_type err_type, struct aca_block *aca_blk, + struct aca_bank_ecc *bank_ecc) +{ + uint64_t seq_no = 0; + + if (bank_ecc->de_count) { + if (aca_blk->blk_info->ras_block_id == RAS_BLOCK_ID__UMC) + seq_no = ras_core_get_seqno(ras_core, RAS_SEQNO_TYPE_DE, true); + else + seq_no = ras_core_get_seqno(ras_core, + RAS_SEQNO_TYPE_POISON_CONSUMPTION, true); + } else if (bank_ecc->ue_count) { + seq_no = ras_core_get_seqno(ras_core, RAS_SEQNO_TYPE_UE, true); + } else { + seq_no = ras_core_get_seqno(ras_core, RAS_SEQNO_TYPE_CE, true); + } + + return seq_no; +} + +static bool aca_dup_update_ue_in_fatal(struct ras_core_context *ras_core, + u32 ecc_type) +{ + struct ras_aca *aca = &ras_core->ras_aca; + + if (ecc_type != RAS_ERR_TYPE__UE) + return false; + + if (aca->ue_updated_mark & ACA_MARK_FATAL_FLAG) { + if (aca->ue_updated_mark & ACA_MARK_UE_READ_FLAG) + return true; + + aca->ue_updated_mark |= ACA_MARK_UE_READ_FLAG; + } + + return false; +} + +void ras_aca_mark_fatal_flag(struct ras_core_context *ras_core) +{ + struct ras_aca *aca = &ras_core->ras_aca; + + if (!aca) + return; + + aca->ue_updated_mark |= ACA_MARK_FATAL_FLAG; +} + +void ras_aca_clear_fatal_flag(struct ras_core_context *ras_core) +{ + struct ras_aca *aca = &ras_core->ras_aca; + + if (!aca) + return; + + if ((aca->ue_updated_mark & ACA_MARK_FATAL_FLAG) && + (aca->ue_updated_mark & ACA_MARK_UE_READ_FLAG)) + aca->ue_updated_mark = 0; +} + +static int aca_banks_update(struct ras_core_context *ras_core, + u32 ecc_type, void *data) +{ + struct aca_bank_reg bank; + struct aca_block *aca_blk; + struct aca_bank_ecc bank_ecc; + struct ras_log_batch_tag *batch_tag = NULL; + u32 count = 0; + int ret; + int i; + + mutex_lock(&ras_core->ras_aca.bank_op_lock); + + if (aca_dup_update_ue_in_fatal(ras_core, ecc_type)) + goto out; + + ret = aca_get_bank_count(ras_core, ecc_type, &count); + if (ret) + goto out; + + if (!count) + goto out; + + batch_tag = ras_log_ring_create_batch_tag(ras_core); + for (i = 0; i < count; i++) { + memset(&bank, 0, sizeof(bank)); + ret = aca_dump_bank(ras_core, ecc_type, i, &bank); + if (ret) + break; + + bank.ecc_type = ecc_type; + + memset(&bank_ecc, 0, sizeof(bank_ecc)); + aca_blk = aca_get_bank_aca_block(ras_core, &bank); + if (aca_blk) + ret = aca_parse_bank(ras_core, aca_blk, &bank, &bank_ecc); + + bank.seq_no = aca_get_bank_seqno(ras_core, ecc_type, aca_blk, &bank_ecc); + + aca_log_bank_data(ras_core, &bank, &bank_ecc, batch_tag); + aca_bank_log(ras_core, i, count, &bank, &bank_ecc); + + if (!ret && aca_blk) + ret = aca_log_bad_bank(ras_core, aca_blk, &bank, &bank_ecc); + + if (ret) + break; + } + ras_log_ring_destroy_batch_tag(ras_core, batch_tag); + +out: + mutex_unlock(&ras_core->ras_aca.bank_op_lock); + return ret; +} + +int ras_aca_update_ecc(struct ras_core_context *ras_core, u32 type, void *data) +{ + /* Update aca bank to aca source error_cache first */ + return aca_banks_update(ras_core, type, data); +} + +static struct aca_block *ras_aca_get_block_handle(struct ras_core_context *ras_core, uint32_t blk) +{ + return &ras_core->ras_aca.aca_blk[blk]; +} + +static int ras_aca_clear_block_ecc_count(struct ras_core_context *ras_core, u32 blk) +{ + struct aca_block *aca_blk; + struct aca_aid_ecc *aid_ecc; + int skt, aid, xcd; + + mutex_lock(&ras_core->ras_aca.aca_lock); + aca_blk = ras_aca_get_block_handle(ras_core, blk); + for (skt = 0; skt < aca_blk->ecc.socket_num_per_hive; skt++) { + for (aid = 0; aid < aca_blk->ecc.socket[skt].aid_num; aid++) { + aid_ecc = &aca_blk->ecc.socket[skt].aid[aid]; + if (blk == RAS_BLOCK_ID__GFX) { + for (xcd = 0; xcd < aid_ecc->xcd.xcd_num; xcd++) + memset(&aid_ecc->xcd.xcd[xcd], + 0, sizeof(struct aca_xcd_ecc)); + } else { + memset(&aid_ecc->ecc_err, 0, sizeof(aid_ecc->ecc_err)); + } + } + } + mutex_unlock(&ras_core->ras_aca.aca_lock); + + return 0; +} + +int ras_aca_clear_all_blocks_ecc_count(struct ras_core_context *ras_core) +{ + enum ras_block_id blk; + int ret; + + for (blk = RAS_BLOCK_ID__UMC; blk < RAS_BLOCK_ID__LAST; blk++) { + ret = ras_aca_clear_block_ecc_count(ras_core, blk); + if (ret) + break; + } + + return ret; +} + +int ras_aca_clear_block_new_ecc_count(struct ras_core_context *ras_core, u32 blk) +{ + struct aca_block *aca_blk; + int skt, aid, xcd; + struct aca_ecc_count *ecc_err; + struct aca_aid_ecc *aid_ecc; + + mutex_lock(&ras_core->ras_aca.aca_lock); + aca_blk = ras_aca_get_block_handle(ras_core, blk); + for (skt = 0; skt < aca_blk->ecc.socket_num_per_hive; skt++) { + for (aid = 0; aid < aca_blk->ecc.socket[skt].aid_num; aid++) { + aid_ecc = &aca_blk->ecc.socket[skt].aid[aid]; + if (blk == RAS_BLOCK_ID__GFX) { + for (xcd = 0; xcd < aid_ecc->xcd.xcd_num; xcd++) { + ecc_err = &aid_ecc->xcd.xcd[xcd].ecc_err; + ecc_err->new_ce_count = 0; + ecc_err->new_ue_count = 0; + ecc_err->new_de_count = 0; + } + } else { + ecc_err = &aid_ecc->ecc_err; + ecc_err->new_ce_count = 0; + ecc_err->new_ue_count = 0; + ecc_err->new_de_count = 0; + } + } + } + mutex_unlock(&ras_core->ras_aca.aca_lock); + + return 0; +} + +static int ras_aca_get_block_each_aid_ecc_count(struct ras_core_context *ras_core, + u32 blk, u32 skt, u32 aid, u32 xcd, + struct aca_ecc_count *ecc_count) +{ + struct aca_block *aca_blk; + struct aca_ecc_count *ecc_err; + + aca_blk = ras_aca_get_block_handle(ras_core, blk); + if (blk == RAS_BLOCK_ID__GFX) + ecc_err = &aca_blk->ecc.socket[skt].aid[aid].xcd.xcd[xcd].ecc_err; + else + ecc_err = &aca_blk->ecc.socket[skt].aid[aid].ecc_err; + + ecc_count->new_ce_count = ecc_err->new_ce_count; + ecc_count->total_ce_count = ecc_err->total_ce_count; + ecc_count->new_ue_count = ecc_err->new_ue_count; + ecc_count->total_ue_count = ecc_err->total_ue_count; + ecc_count->new_de_count = ecc_err->new_de_count; + ecc_count->total_de_count = ecc_err->total_de_count; + + return 0; +} + +static inline void _add_ecc_count(struct aca_ecc_count *des, struct aca_ecc_count *src) +{ + des->new_ce_count += src->new_ce_count; + des->total_ce_count += src->total_ce_count; + des->new_ue_count += src->new_ue_count; + des->total_ue_count += src->total_ue_count; + des->new_de_count += src->new_de_count; + des->total_de_count += src->total_de_count; +} + +static const struct ras_aca_ip_func *aca_get_ip_func( + struct ras_core_context *ras_core, uint32_t ip_version) +{ + switch (ip_version) { + case IP_VERSION(1, 0, 0): + return &ras_aca_func_v1_0; + default: + RAS_DEV_ERR(ras_core->dev, + "ACA ip version(0x%x) is not supported!\n", ip_version); + break; + } + + return NULL; +} + +int ras_aca_get_block_ecc_count(struct ras_core_context *ras_core, + u32 blk, void *data) +{ + struct ras_ecc_count *err_data = (struct ras_ecc_count *)data; + struct aca_block *aca_blk; + int skt, aid, xcd; + struct aca_ecc_count ecc_xcd; + struct aca_ecc_count ecc_aid; + struct aca_ecc_count ecc; + + if (blk >= RAS_BLOCK_ID__LAST) + return -EINVAL; + + if (!err_data) + return -EINVAL; + + aca_blk = ras_aca_get_block_handle(ras_core, blk); + memset(&ecc, 0, sizeof(ecc)); + + mutex_lock(&ras_core->ras_aca.aca_lock); + if (blk == RAS_BLOCK_ID__GFX) { + for (skt = 0; skt < aca_blk->ecc.socket_num_per_hive; skt++) { + for (aid = 0; aid < aca_blk->ecc.socket[skt].aid_num; aid++) { + memset(&ecc_aid, 0, sizeof(ecc_aid)); + for (xcd = 0; + xcd < aca_blk->ecc.socket[skt].aid[aid].xcd.xcd_num; + xcd++) { + memset(&ecc_xcd, 0, sizeof(ecc_xcd)); + if (ras_aca_get_block_each_aid_ecc_count(ras_core, + blk, skt, aid, xcd, &ecc_xcd)) + continue; + _add_ecc_count(&ecc_aid, &ecc_xcd); + } + _add_ecc_count(&ecc, &ecc_aid); + } + } + } else { + for (skt = 0; skt < aca_blk->ecc.socket_num_per_hive; skt++) { + for (aid = 0; aid < aca_blk->ecc.socket[skt].aid_num; aid++) { + memset(&ecc_aid, 0, sizeof(ecc_aid)); + if (ras_aca_get_block_each_aid_ecc_count(ras_core, + blk, skt, aid, 0, &ecc_aid)) + continue; + _add_ecc_count(&ecc, &ecc_aid); + } + } + } + + err_data->new_ce_count = ecc.new_ce_count; + err_data->total_ce_count = ecc.total_ce_count; + err_data->new_ue_count = ecc.new_ue_count; + err_data->total_ue_count = ecc.total_ue_count; + err_data->new_de_count = ecc.new_de_count; + err_data->total_de_count = ecc.total_de_count; + mutex_unlock(&ras_core->ras_aca.aca_lock); + + return 0; +} + +int ras_aca_sw_init(struct ras_core_context *ras_core) +{ + struct ras_aca *ras_aca = &ras_core->ras_aca; + struct ras_aca_config *aca_cfg = &ras_core->config->aca_cfg; + struct aca_block *aca_blk; + uint32_t socket_num_per_hive; + uint32_t aid_num_per_socket; + uint32_t xcd_num_per_aid; + int blk, skt, aid; + + socket_num_per_hive = aca_cfg->socket_num_per_hive; + aid_num_per_socket = aca_cfg->aid_num_per_socket; + xcd_num_per_aid = aca_cfg->xcd_num_per_aid; + + if (!xcd_num_per_aid || !aid_num_per_socket || + (socket_num_per_hive > MAX_SOCKET_NUM_PER_HIVE) || + (aid_num_per_socket > MAX_AID_NUM_PER_SOCKET) || + (xcd_num_per_aid > MAX_XCD_NUM_PER_AID)) { + RAS_DEV_ERR(ras_core->dev, "Invalid ACA system configuration: %d, %d, %d\n", + socket_num_per_hive, aid_num_per_socket, xcd_num_per_aid); + return -EINVAL; + } + + memset(ras_aca, 0, sizeof(*ras_aca)); + + for (blk = 0; blk < RAS_BLOCK_ID__LAST; blk++) { + aca_blk = &ras_aca->aca_blk[blk]; + aca_blk->ecc.socket_num_per_hive = socket_num_per_hive; + for (skt = 0; skt < aca_blk->ecc.socket_num_per_hive; skt++) { + aca_blk->ecc.socket[skt].aid_num = aid_num_per_socket; + if (blk == RAS_BLOCK_ID__GFX) { + for (aid = 0; aid < aca_blk->ecc.socket[skt].aid_num; aid++) + aca_blk->ecc.socket[skt].aid[aid].xcd.xcd_num = + xcd_num_per_aid; + } + } + } + + mutex_init(&ras_aca->aca_lock); + mutex_init(&ras_aca->bank_op_lock); + + return 0; +} + +int ras_aca_sw_fini(struct ras_core_context *ras_core) +{ + struct ras_aca *ras_aca = &ras_core->ras_aca; + + mutex_destroy(&ras_aca->aca_lock); + mutex_destroy(&ras_aca->bank_op_lock); + + return 0; +} + +int ras_aca_hw_init(struct ras_core_context *ras_core) +{ + struct ras_aca *ras_aca = &ras_core->ras_aca; + struct aca_block *aca_blk; + const struct ras_aca_ip_func *ip_func; + int i; + + ras_aca->aca_ip_version = ras_core->config->aca_ip_version; + ip_func = aca_get_ip_func(ras_core, ras_aca->aca_ip_version); + if (!ip_func) + return -EINVAL; + + for (i = 0; i < ip_func->block_num; i++) { + aca_blk = &ras_aca->aca_blk[ip_func->block_info[i]->ras_block_id]; + aca_blk->blk_info = ip_func->block_info[i]; + } + + ras_aca->ue_updated_mark = 0; + + return 0; +} + +int ras_aca_hw_fini(struct ras_core_context *ras_core) +{ + struct ras_aca *ras_aca = &ras_core->ras_aca; + + ras_aca->ue_updated_mark = 0; + + return 0; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_aca.h b/drivers/gpu/drm/amd/ras/rascore/ras_aca.h new file mode 100644 index 0000000000000..f61b02a5f0fc3 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_aca.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __RAS_ACA_H__ +#define __RAS_ACA_H__ +#include "ras.h" + +#define MAX_SOCKET_NUM_PER_HIVE 8 +#define MAX_AID_NUM_PER_SOCKET 4 +#define MAX_XCD_NUM_PER_AID 2 +#define MAX_ACA_RAS_BLOCK 20 + +#define ACA_ERROR__UE_MASK (0x1 << RAS_ERR_TYPE__UE) +#define ACA_ERROR__CE_MASK (0x1 << RAS_ERR_TYPE__CE) +#define ACA_ERROR__DE_MASK (0x1 << RAS_ERR_TYPE__DE) + +enum ras_aca_reg_idx { + ACA_REG_IDX__CTL = 0, + ACA_REG_IDX__STATUS = 1, + ACA_REG_IDX__ADDR = 2, + ACA_REG_IDX__MISC0 = 3, + ACA_REG_IDX__CONFG = 4, + ACA_REG_IDX__IPID = 5, + ACA_REG_IDX__SYND = 6, + ACA_REG_IDX__DESTAT = 8, + ACA_REG_IDX__DEADDR = 9, + ACA_REG_IDX__CTL_MASK = 10, + ACA_REG_MAX_COUNT = 16, +}; + +struct ras_core_context; +struct aca_block; + +struct aca_bank_reg { + u32 ecc_type; + u64 seq_no; + u64 regs[ACA_REG_MAX_COUNT]; +}; + +enum aca_ecc_hwip { + ACA_ECC_HWIP__UNKNOWN = -1, + ACA_ECC_HWIP__PSP = 0, + ACA_ECC_HWIP__UMC, + ACA_ECC_HWIP__SMU, + ACA_ECC_HWIP__PCS_XGMI, + ACA_ECC_HWIP_COUNT, +}; + +struct aca_ecc_info { + int die_id; + int socket_id; + int xcd_id; + int hwid; + int mcatype; + uint64_t status; + uint64_t ipid; + uint64_t addr; +}; + +struct aca_bank_ecc { + struct aca_ecc_info bank_info; + u32 ce_count; + u32 ue_count; + u32 de_count; +}; + +struct aca_ecc_count { + u32 new_ce_count; + u32 total_ce_count; + u32 new_ue_count; + u32 total_ue_count; + u32 new_de_count; + u32 total_de_count; +}; + +struct aca_xcd_ecc { + struct aca_ecc_count ecc_err; +}; + +struct aca_aid_ecc { + union { + struct aca_xcd { + struct aca_xcd_ecc xcd[MAX_XCD_NUM_PER_AID]; + u32 xcd_num; + } xcd; + struct aca_ecc_count ecc_err; + }; +}; + +struct aca_socket_ecc { + struct aca_aid_ecc aid[MAX_AID_NUM_PER_SOCKET]; + u32 aid_num; +}; + +struct aca_block_ecc { + struct aca_socket_ecc socket[MAX_SOCKET_NUM_PER_HIVE]; + u32 socket_num_per_hive; +}; + +struct aca_bank_hw_ops { + bool (*bank_match)(struct aca_block *ras_blk, void *data); + int (*bank_parse)(struct ras_core_context *ras_core, + struct aca_block *aca_blk, void *data, void *buf); +}; + +struct aca_block_info { + char name[32]; + u32 ras_block_id; + enum aca_ecc_hwip hwip; + struct aca_bank_hw_ops bank_ops; + u32 mask; +}; + +struct aca_block { + const struct aca_block_info *blk_info; + struct aca_block_ecc ecc; +}; + +struct ras_aca_ip_func { + uint32_t block_num; + const struct aca_block_info **block_info; +}; + +struct ras_aca { + uint32_t aca_ip_version; + const struct ras_aca_ip_func *ip_func; + struct mutex aca_lock; + struct mutex bank_op_lock; + struct aca_block aca_blk[MAX_ACA_RAS_BLOCK]; + uint32_t ue_updated_mark; +}; + +int ras_aca_sw_init(struct ras_core_context *ras_core); +int ras_aca_sw_fini(struct ras_core_context *ras_core); +int ras_aca_hw_init(struct ras_core_context *ras_core); +int ras_aca_hw_fini(struct ras_core_context *ras_core); +int ras_aca_get_block_ecc_count(struct ras_core_context *ras_core, u32 blk, void *data); +int ras_aca_clear_block_new_ecc_count(struct ras_core_context *ras_core, u32 blk); +int ras_aca_clear_all_blocks_ecc_count(struct ras_core_context *ras_core); +int ras_aca_update_ecc(struct ras_core_context *ras_core, u32 ecc_type, void *data); +void ras_aca_mark_fatal_flag(struct ras_core_context *ras_core); +void ras_aca_clear_fatal_flag(struct ras_core_context *ras_core); +#endif From fd2a8d53fa1765cdfe52e505742080896a113d95 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 17:21:41 +0800 Subject: [PATCH 2085/2653] drm/amd/ras: Add mp1 v13_0 ras functions Add mp1 v13_0 ras functions. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/ras/rascore/ras_mp1_v13_0.c | 105 ++++++++++++++++++ .../gpu/drm/amd/ras/rascore/ras_mp1_v13_0.h | 30 +++++ 2 files changed, 135 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_mp1_v13_0.c create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_mp1_v13_0.h diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_mp1_v13_0.c b/drivers/gpu/drm/amd/ras/rascore/ras_mp1_v13_0.c new file mode 100644 index 0000000000000..310d39fc816bf --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_mp1_v13_0.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "ras.h" +#include "ras_mp1.h" +#include "ras_core_status.h" +#include "ras_mp1_v13_0.h" + +#define RAS_MP1_MSG_QueryValidMcaCount 0x36 +#define RAS_MP1_MSG_McaBankDumpDW 0x37 +#define RAS_MP1_MSG_ClearMcaOnRead 0x39 +#define RAS_MP1_MSG_QueryValidMcaCeCount 0x3A +#define RAS_MP1_MSG_McaBankCeDumpDW 0x3B + +#define MAX_UE_BANKS_PER_QUERY 12 +#define MAX_CE_BANKS_PER_QUERY 12 + +static int mp1_v13_0_get_bank_count(struct ras_core_context *ras_core, + enum ras_err_type type, u32 *count) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + const struct ras_mp1_sys_func *sys_func = mp1->sys_func; + uint32_t bank_count = 0; + u32 msg; + int ret; + + if (!count) + return -EINVAL; + + if (!sys_func || !sys_func->mp1_get_valid_bank_count) + return -RAS_CORE_NOT_SUPPORTED; + + switch (type) { + case RAS_ERR_TYPE__UE: + msg = RAS_MP1_MSG_QueryValidMcaCount; + break; + case RAS_ERR_TYPE__CE: + case RAS_ERR_TYPE__DE: + msg = RAS_MP1_MSG_QueryValidMcaCeCount; + break; + default: + return -EINVAL; + } + + ret = sys_func->mp1_get_valid_bank_count(ras_core, msg, &bank_count); + if (!ret) { + if (((type == RAS_ERR_TYPE__UE) && (bank_count >= MAX_UE_BANKS_PER_QUERY)) || + ((type == RAS_ERR_TYPE__CE) && (bank_count >= MAX_CE_BANKS_PER_QUERY))) + return -EINVAL; + + *count = bank_count; + } + + return ret; +} + +static int mp1_v13_0_dump_bank(struct ras_core_context *ras_core, + enum ras_err_type type, u32 idx, u32 reg_idx, u64 *val) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + const struct ras_mp1_sys_func *sys_func = mp1->sys_func; + u32 msg; + + if (!sys_func || !sys_func->mp1_dump_valid_bank) + return -RAS_CORE_NOT_SUPPORTED; + + switch (type) { + case RAS_ERR_TYPE__UE: + msg = RAS_MP1_MSG_McaBankDumpDW; + break; + case RAS_ERR_TYPE__CE: + case RAS_ERR_TYPE__DE: + msg = RAS_MP1_MSG_McaBankCeDumpDW; + break; + default: + return -EINVAL; + } + + return sys_func->mp1_dump_valid_bank(ras_core, msg, idx, reg_idx, val); +} + +const struct ras_mp1_ip_func mp1_ras_func_v13_0 = { + .get_valid_bank_count = mp1_v13_0_get_bank_count, + .dump_valid_bank = mp1_v13_0_dump_bank, +}; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_mp1_v13_0.h b/drivers/gpu/drm/amd/ras/rascore/ras_mp1_v13_0.h new file mode 100644 index 0000000000000..2edfdb5f6a75b --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_mp1_v13_0.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __RAS_MP1_V13_0_H__ +#define __RAS_MP1_V13_0_H__ +#include "ras_mp1.h" + +extern const struct ras_mp1_ip_func mp1_ras_func_v13_0; + +#endif From 0cb168e0abda0f8d95f8bcf615e846909cc3037b Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 17:20:28 +0800 Subject: [PATCH 2086/2653] drm/amd/ras: Add mp1 common ras functions Add mp1 common ras functions. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/ras/rascore/ras_mp1.c | 81 +++++++++++++++++++++++ drivers/gpu/drm/amd/ras/rascore/ras_mp1.h | 50 ++++++++++++++ 2 files changed, 131 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_mp1.c create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_mp1.h diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_mp1.c b/drivers/gpu/drm/amd/ras/rascore/ras_mp1.c new file mode 100644 index 0000000000000..92f250e2466d5 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_mp1.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "ras.h" +#include "ras_mp1.h" +#include "ras_mp1_v13_0.h" + +static const struct ras_mp1_ip_func *ras_mp1_get_ip_funcs( + struct ras_core_context *ras_core, uint32_t ip_version) +{ + switch (ip_version) { + case IP_VERSION(13, 0, 6): + case IP_VERSION(13, 0, 14): + case IP_VERSION(13, 0, 12): + return &mp1_ras_func_v13_0; + default: + RAS_DEV_ERR(ras_core->dev, + "MP1 ip version(0x%x) is not supported!\n", ip_version); + break; + } + + return NULL; +} + +int ras_mp1_get_bank_count(struct ras_core_context *ras_core, + enum ras_err_type type, u32 *count) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + + return mp1->ip_func->get_valid_bank_count(ras_core, type, count); +} + +int ras_mp1_dump_bank(struct ras_core_context *ras_core, + enum ras_err_type type, u32 idx, u32 reg_idx, u64 *val) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + + return mp1->ip_func->dump_valid_bank(ras_core, type, idx, reg_idx, val); +} + +int ras_mp1_hw_init(struct ras_core_context *ras_core) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + + mp1->mp1_ip_version = ras_core->config->mp1_ip_version; + mp1->sys_func = ras_core->config->mp1_cfg.mp1_sys_fn; + if (!mp1->sys_func) { + RAS_DEV_ERR(ras_core->dev, "RAS mp1 sys function not configured!\n"); + return -EINVAL; + } + + mp1->ip_func = ras_mp1_get_ip_funcs(ras_core, mp1->mp1_ip_version); + + return mp1->ip_func ? RAS_CORE_OK : -EINVAL; +} + +int ras_mp1_hw_fini(struct ras_core_context *ras_core) +{ + return 0; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_mp1.h b/drivers/gpu/drm/amd/ras/rascore/ras_mp1.h new file mode 100644 index 0000000000000..de1d08286f418 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_mp1.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __RAS_MP1_H__ +#define __RAS_MP1_H__ +#include "ras.h" + +enum ras_err_type; +struct ras_mp1_ip_func { + int (*get_valid_bank_count)(struct ras_core_context *ras_core, + enum ras_err_type type, u32 *count); + int (*dump_valid_bank)(struct ras_core_context *ras_core, + enum ras_err_type type, u32 idx, u32 reg_idx, u64 *val); +}; + +struct ras_mp1 { + uint32_t mp1_ip_version; + const struct ras_mp1_ip_func *ip_func; + const struct ras_mp1_sys_func *sys_func; +}; + +int ras_mp1_hw_init(struct ras_core_context *ras_core); +int ras_mp1_hw_fini(struct ras_core_context *ras_core); + +int ras_mp1_get_bank_count(struct ras_core_context *ras_core, + enum ras_err_type type, u32 *count); + +int ras_mp1_dump_bank(struct ras_core_context *ras_core, + u32 ecc_type, u32 idx, u32 reg_idx, u64 *val); +#endif From 8d91d075ad8180e4bebe17e6bfb342e12d60a894 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 17:25:59 +0800 Subject: [PATCH 2087/2653] drm/amd/ras: Add nbio v7_9 ras functions Add nbio v7_9 ras functions. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/ras/rascore/ras_nbio_v7_9.c | 123 ++++++++++++++++++ .../gpu/drm/amd/ras/rascore/ras_nbio_v7_9.h | 31 +++++ 2 files changed, 154 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_nbio_v7_9.c create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_nbio_v7_9.h diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_nbio_v7_9.c b/drivers/gpu/drm/amd/ras/rascore/ras_nbio_v7_9.c new file mode 100644 index 0000000000000..f17d708ec6681 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_nbio_v7_9.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "ras.h" +#include "ras_nbio_v7_9.h" + +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L + +#define regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_DOORBELL_INT_CNTL 0x00fe + +#define regBIF_BX0_BIF_INTR_CNTL 0x0101 +#define regBIF_BX0_BIF_INTR_CNTL_BASE_IDX 2 + +/* BIF_BX0_BIF_INTR_CNTL */ +#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0 +#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L + +#define regBIF_BX_PF0_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_PF0_PARTITION_MEM_STATUS_BASE_IDX 2 +/* BIF_BX_PF0_PARTITION_MEM_STATUS */ +#define BIF_BX_PF0_PARTITION_MEM_STATUS__CHANGE_STATUE__SHIFT 0x0 +#define BIF_BX_PF0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_PF0_PARTITION_MEM_STATUS__CHANGE_STATUE_MASK 0x0000000FL +#define BIF_BX_PF0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +static int nbio_v7_9_handle_ras_controller_intr_no_bifring(struct ras_core_context *ras_core) +{ + uint32_t bif_doorbell_intr_cntl = 0; + + bif_doorbell_intr_cntl = + RAS_DEV_RREG32_SOC15(ras_core->dev, NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); + + if (REG_GET_FIELD(bif_doorbell_intr_cntl, + BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) { + /* driver has to clear the interrupt status when bif ring is disabled */ + bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, + BIF_BX0_BIF_DOORBELL_INT_CNTL, + RAS_CNTLR_INTERRUPT_CLEAR, 1); + + RAS_DEV_WREG32_SOC15(ras_core->dev, + NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); + + /* TODO: handle ras controller interrupt */ + } + + return 0; +} + +static int nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring(struct ras_core_context *ras_core) +{ + uint32_t bif_doorbell_intr_cntl = 0; + int ret = 0; + + bif_doorbell_intr_cntl = + RAS_DEV_RREG32_SOC15(ras_core->dev, NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); + + if (REG_GET_FIELD(bif_doorbell_intr_cntl, + BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) { + /* driver has to clear the interrupt status when bif ring is disabled */ + bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, + BIF_BX0_BIF_DOORBELL_INT_CNTL, + RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1); + + RAS_DEV_WREG32_SOC15(ras_core->dev, + NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); + + ret = ras_core_handle_fatal_error(ras_core); + } + + return ret; +} + +static uint32_t nbio_v7_9_get_memory_partition_mode(struct ras_core_context *ras_core) +{ + uint32_t mem_status; + uint32_t mem_mode; + + mem_status = + RAS_DEV_RREG32_SOC15(ras_core->dev, NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS); + + /* Each bit represents a mode 1-8*/ + mem_mode = REG_GET_FIELD(mem_status, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE); + + return ffs(mem_mode); +} + +const struct ras_nbio_ip_func ras_nbio_v7_9 = { + .handle_ras_controller_intr_no_bifring = + nbio_v7_9_handle_ras_controller_intr_no_bifring, + .handle_ras_err_event_athub_intr_no_bifring = + nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring, + .get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode, +}; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_nbio_v7_9.h b/drivers/gpu/drm/amd/ras/rascore/ras_nbio_v7_9.h new file mode 100644 index 0000000000000..8711c82a927f7 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_nbio_v7_9.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __RAS_NBIO_V7_9_H__ +#define __RAS_NBIO_V7_9_H__ +#include "ras_nbio.h" + +extern const struct ras_nbio_ip_func ras_nbio_v7_9; + +#endif From 8abb4d4f1892cf7db498f77afb66f5c779fc0450 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 17:25:04 +0800 Subject: [PATCH 2088/2653] drm/amd/ras: Add nbio common ras functions Add nbio common ras functions. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/ras/rascore/ras_nbio.c | 95 ++++++++++++++++++++++ drivers/gpu/drm/amd/ras/rascore/ras_nbio.h | 46 +++++++++++ 2 files changed, 141 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_nbio.c create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_nbio.h diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_nbio.c b/drivers/gpu/drm/amd/ras/rascore/ras_nbio.c new file mode 100644 index 0000000000000..8bf1f35d595e6 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_nbio.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "ras.h" +#include "ras_nbio.h" +#include "ras_nbio_v7_9.h" + +static const struct ras_nbio_ip_func *ras_nbio_get_ip_funcs( + struct ras_core_context *ras_core, uint32_t ip_version) +{ + switch (ip_version) { + case IP_VERSION(7, 9, 0): + return &ras_nbio_v7_9; + default: + RAS_DEV_ERR(ras_core->dev, + "NBIO ip version(0x%x) is not supported!\n", ip_version); + break; + } + + return NULL; +} + +int ras_nbio_hw_init(struct ras_core_context *ras_core) +{ + struct ras_nbio *nbio = &ras_core->ras_nbio; + + nbio->nbio_ip_version = ras_core->config->nbio_ip_version; + nbio->sys_func = ras_core->config->nbio_cfg.nbio_sys_fn; + if (!nbio->sys_func) { + RAS_DEV_ERR(ras_core->dev, "RAS nbio sys function not configured!\n"); + return -EINVAL; + } + + nbio->ip_func = ras_nbio_get_ip_funcs(ras_core, nbio->nbio_ip_version); + if (!nbio->ip_func) + return -EINVAL; + + if (nbio->sys_func) { + if (nbio->sys_func->set_ras_controller_irq_state) + nbio->sys_func->set_ras_controller_irq_state(ras_core, true); + if (nbio->sys_func->set_ras_err_event_athub_irq_state) + nbio->sys_func->set_ras_err_event_athub_irq_state(ras_core, true); + } + + return 0; +} + +int ras_nbio_hw_fini(struct ras_core_context *ras_core) +{ + struct ras_nbio *nbio = &ras_core->ras_nbio; + + if (nbio->sys_func) { + if (nbio->sys_func->set_ras_controller_irq_state) + nbio->sys_func->set_ras_controller_irq_state(ras_core, false); + if (nbio->sys_func->set_ras_err_event_athub_irq_state) + nbio->sys_func->set_ras_err_event_athub_irq_state(ras_core, false); + } + + return 0; +} + +bool ras_nbio_handle_irq_error(struct ras_core_context *ras_core, void *data) +{ + struct ras_nbio *nbio = &ras_core->ras_nbio; + + if (nbio->ip_func) { + if (nbio->ip_func->handle_ras_controller_intr_no_bifring) + nbio->ip_func->handle_ras_controller_intr_no_bifring(ras_core); + if (nbio->ip_func->handle_ras_err_event_athub_intr_no_bifring) + nbio->ip_func->handle_ras_err_event_athub_intr_no_bifring(ras_core); + } + + return true; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_nbio.h b/drivers/gpu/drm/amd/ras/rascore/ras_nbio.h new file mode 100644 index 0000000000000..0a1313e59a026 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_nbio.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __RAS_NBIO_H__ +#define __RAS_NBIO_H__ +#include "ras.h" + +struct ras_core_context; + +struct ras_nbio_ip_func { + int (*handle_ras_controller_intr_no_bifring)(struct ras_core_context *ras_core); + int (*handle_ras_err_event_athub_intr_no_bifring)(struct ras_core_context *ras_core); + uint32_t (*get_memory_partition_mode)(struct ras_core_context *ras_core); +}; + +struct ras_nbio { + uint32_t nbio_ip_version; + const struct ras_nbio_ip_func *ip_func; + const struct ras_nbio_sys_func *sys_func; +}; + +int ras_nbio_hw_init(struct ras_core_context *ras_core); +int ras_nbio_hw_fini(struct ras_core_context *ras_core); +bool ras_nbio_handle_irq_error(struct ras_core_context *ras_core, void *data); +#endif From 380ed58be1652bbde2b045953f451134cef652f6 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 17:27:44 +0800 Subject: [PATCH 2089/2653] drm/amd/ras: Add umc v12_0 ras functions Add umc v12_0 ras functions. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/ras/rascore/ras_umc_v12_0.c | 511 ++++++++++++++++++ .../gpu/drm/amd/ras/rascore/ras_umc_v12_0.h | 314 +++++++++++ 2 files changed, 825 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.h diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c new file mode 100644 index 0000000000000..5d9a11c17a864 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c @@ -0,0 +1,511 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "ras.h" +#include "ras_umc.h" +#include "ras_core_status.h" +#include "ras_umc_v12_0.h" + +#define NumDieInterleaved 4 + +static const uint32_t umc_v12_0_channel_idx_tbl[] + [UMC_V12_0_UMC_INSTANCE_NUM][UMC_V12_0_CHANNEL_INSTANCE_NUM] = { + {{3, 7, 11, 15, 2, 6, 10, 14}, {1, 5, 9, 13, 0, 4, 8, 12}, + {19, 23, 27, 31, 18, 22, 26, 30}, {17, 21, 25, 29, 16, 20, 24, 28}}, + {{47, 43, 39, 35, 46, 42, 38, 34}, {45, 41, 37, 33, 44, 40, 36, 32}, + {63, 59, 55, 51, 62, 58, 54, 50}, {61, 57, 53, 49, 60, 56, 52, 48}}, + {{79, 75, 71, 67, 78, 74, 70, 66}, {77, 73, 69, 65, 76, 72, 68, 64}, + {95, 91, 87, 83, 94, 90, 86, 82}, {93, 89, 85, 81, 92, 88, 84, 80}}, + {{99, 103, 107, 111, 98, 102, 106, 110}, {97, 101, 105, 109, 96, 100, 104, 108}, + {115, 119, 123, 127, 114, 118, 122, 126}, {113, 117, 121, 125, 112, 116, 120, 124}} +}; + +/* mapping of MCA error address to normalized address */ +static const uint32_t umc_v12_0_ma2na_mapping[] = { + 0, 5, 6, 8, 9, 14, 12, 13, + 10, 11, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 24, 25, 26, 27, 28, + 24, 7, 29, 30, +}; + +static bool umc_v12_0_bit_wise_xor(uint32_t val) +{ + bool result = 0; + int i; + + for (i = 0; i < 32; i++) + result = result ^ ((val >> i) & 0x1); + + return result; +} + +static void __get_nps_pa_flip_bits(struct ras_core_context *ras_core, + enum umc_memory_partition_mode nps, + struct umc_flip_bits *flip_bits) +{ + uint32_t vram_type = ras_core->ras_umc.umc_vram_type; + + /* default setting */ + flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_C2_BIT; + flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C3_BIT; + flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_C4_BIT; + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R13_BIT; + flip_bits->flip_row_bit = 13; + flip_bits->bit_num = 4; + flip_bits->r13_in_pa = UMC_V12_0_PA_R13_BIT; + + if (nps == UMC_MEMORY_PARTITION_MODE_NPS2) { + flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT; + flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT; + flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT; + flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT; + } else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4) { + flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT; + flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT; + flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT; + flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT; + } + + switch (vram_type) { + case UMC_VRAM_TYPE_HBM: + /* other nps modes are taken as nps1 */ + if (nps == UMC_MEMORY_PARTITION_MODE_NPS2) + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT; + else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4) + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; + + break; + case UMC_VRAM_TYPE_HBM3E: + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT; + flip_bits->flip_row_bit = 12; + + if (nps == UMC_MEMORY_PARTITION_MODE_NPS2) + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; + else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4) + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT; + + break; + default: + RAS_DEV_WARN(ras_core->dev, + "Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n"); + break; + } +} + +static uint64_t convert_nps_pa_to_row_pa(struct ras_core_context *ras_core, + uint64_t pa, enum umc_memory_partition_mode nps, bool zero_pfn_ok) +{ + struct umc_flip_bits flip_bits = {0}; + uint64_t row_pa; + int i; + + __get_nps_pa_flip_bits(ras_core, nps, &flip_bits); + + row_pa = pa; + /* clear loop bits in soc physical address */ + for (i = 0; i < flip_bits.bit_num; i++) + row_pa &= ~BIT_ULL(flip_bits.flip_bits_in_pa[i]); + + if (!zero_pfn_ok && !RAS_ADDR_TO_PFN(row_pa)) + row_pa |= BIT_ULL(flip_bits.flip_bits_in_pa[2]); + + return row_pa; +} + +static int lookup_bad_pages_in_a_row(struct ras_core_context *ras_core, + struct eeprom_umc_record *record, uint32_t nps, + uint64_t *pfns, uint32_t num, + uint64_t seq_no, bool dump) +{ + uint32_t col, col_lower, row, row_lower, idx, row_high; + uint64_t soc_pa, row_pa, column, err_addr; + uint64_t retired_addr = RAS_PFN_TO_ADDR(record->cur_nps_retired_row_pfn); + struct umc_flip_bits flip_bits = {0}; + uint32_t retire_unit; + uint32_t i; + + __get_nps_pa_flip_bits(ras_core, nps, &flip_bits); + + row_pa = convert_nps_pa_to_row_pa(ras_core, retired_addr, nps, true); + + err_addr = record->address; + /* get column bit 0 and 1 in mca address */ + col_lower = (err_addr >> 1) & 0x3ULL; + /* MA_R13_BIT will be handled later */ + row_lower = (err_addr >> UMC_V12_0_MCA_R0_BIT) & 0x1fffULL; + row_lower &= ~BIT_ULL(flip_bits.flip_row_bit); + + if (ras_core->ras_gfx.gfx_ip_version >= IP_VERSION(9, 5, 0)) { + row_high = (row_pa >> flip_bits.r13_in_pa) & 0x3ULL; + /* it's 2.25GB in each channel, from MCA address to PA + * [R14 R13] is converted if the two bits value are 0x3, + * get them from PA instead of MCA address. + */ + row_lower |= (row_high << 13); + } + + idx = 0; + row = 0; + retire_unit = 0x1 << flip_bits.bit_num; + /* loop for all possibilities of retire bits */ + for (column = 0; column < retire_unit; column++) { + soc_pa = row_pa; + for (i = 0; i < flip_bits.bit_num; i++) + soc_pa |= (((column >> i) & 0x1ULL) << flip_bits.flip_bits_in_pa[i]); + + col = ((column & 0x7) << 2) | col_lower; + + /* add row bit 13 */ + if (flip_bits.bit_num == UMC_PA_FLIP_BITS_NUM) + row = ((column >> 3) << flip_bits.flip_row_bit) | row_lower; + + if (dump) + RAS_DEV_INFO(ras_core->dev, + "{%llu} Error Address(PA):0x%-10llx Row:0x%-4x Col:0x%-2x Bank:0x%x Channel:0x%x\n", + seq_no, soc_pa, row, col, + record->cur_nps_bank, record->mem_channel); + + + if (pfns && (idx < num)) + pfns[idx++] = RAS_ADDR_TO_PFN(soc_pa); + } + + return idx; +} + +static int umc_v12_convert_ma_to_pa(struct ras_core_context *ras_core, + struct umc_mca_addr *addr_in, struct umc_phy_addr *addr_out, + uint32_t nps) +{ + uint32_t i, na_shift; + uint64_t soc_pa, na, na_nps; + uint32_t bank_hash0, bank_hash1, bank_hash2, bank_hash3, col, row; + uint32_t bank0, bank1, bank2, bank3, bank; + uint32_t ch_inst = addr_in->ch_inst; + uint32_t umc_inst = addr_in->umc_inst; + uint32_t node_inst = addr_in->node_inst; + uint32_t socket_id = addr_in->socket_id; + uint32_t channel_index; + uint64_t err_addr = addr_in->err_addr; + + if (node_inst != UMC_INV_AID_NODE) { + if (ch_inst >= UMC_V12_0_CHANNEL_INSTANCE_NUM || + umc_inst >= UMC_V12_0_UMC_INSTANCE_NUM || + node_inst >= UMC_V12_0_AID_NUM_MAX || + socket_id >= UMC_V12_0_SOCKET_NUM_MAX) + return -EINVAL; + } else { + if (socket_id >= UMC_V12_0_SOCKET_NUM_MAX || + ch_inst >= UMC_V12_0_TOTAL_CHANNEL_NUM) + return -EINVAL; + } + + bank_hash0 = (err_addr >> UMC_V12_0_MCA_B0_BIT) & 0x1ULL; + bank_hash1 = (err_addr >> UMC_V12_0_MCA_B1_BIT) & 0x1ULL; + bank_hash2 = (err_addr >> UMC_V12_0_MCA_B2_BIT) & 0x1ULL; + bank_hash3 = (err_addr >> UMC_V12_0_MCA_B3_BIT) & 0x1ULL; + col = (err_addr >> 1) & 0x1fULL; + row = (err_addr >> 10) & 0x3fffULL; + + /* apply bank hash algorithm */ + bank0 = + bank_hash0 ^ (UMC_V12_0_XOR_EN0 & + (umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR0) ^ + (umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR0)))); + bank1 = + bank_hash1 ^ (UMC_V12_0_XOR_EN1 & + (umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR1) ^ + (umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR1)))); + bank2 = + bank_hash2 ^ (UMC_V12_0_XOR_EN2 & + (umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR2) ^ + (umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR2)))); + bank3 = + bank_hash3 ^ (UMC_V12_0_XOR_EN3 & + (umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR3) ^ + (umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR3)))); + + bank = bank0 | (bank1 << 1) | (bank2 << 2) | (bank3 << 3); + err_addr &= ~0x3c0ULL; + err_addr |= (bank << UMC_V12_0_MCA_B0_BIT); + + na_nps = 0x0; + /* convert mca error address to normalized address */ + for (i = 1; i < ARRAY_SIZE(umc_v12_0_ma2na_mapping); i++) + na_nps |= ((err_addr >> i) & 0x1ULL) << umc_v12_0_ma2na_mapping[i]; + + if (nps == UMC_MEMORY_PARTITION_MODE_NPS1) + na_shift = 8; + else if (nps == UMC_MEMORY_PARTITION_MODE_NPS2) + na_shift = 9; + else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4) + na_shift = 10; + else if (nps == UMC_MEMORY_PARTITION_MODE_NPS8) + na_shift = 11; + else + return -EINVAL; + + na = ((na_nps >> na_shift) << 8) | (na_nps & 0xff); + + if (node_inst != UMC_INV_AID_NODE) + channel_index = + umc_v12_0_channel_idx_tbl[node_inst][umc_inst][ch_inst]; + else { + channel_index = ch_inst; + node_inst = channel_index / + (UMC_V12_0_UMC_INSTANCE_NUM * UMC_V12_0_CHANNEL_INSTANCE_NUM); + } + + /* translate umc channel address to soc pa, 3 parts are included */ + soc_pa = ADDR_OF_32KB_BLOCK(na) | + ADDR_OF_256B_BLOCK(channel_index) | + OFFSET_IN_256B_BLOCK(na); + + /* calc channel hash based on absolute address */ + soc_pa += socket_id * SOCKET_LFB_SIZE; + /* the umc channel bits are not original values, they are hashed */ + UMC_V12_0_SET_CHANNEL_HASH(channel_index, soc_pa); + /* restore pa */ + soc_pa -= socket_id * SOCKET_LFB_SIZE; + + /* get some channel bits from na_nps directly and + * add nps section offset + */ + if (nps == UMC_MEMORY_PARTITION_MODE_NPS2) { + soc_pa &= ~(0x1ULL << UMC_V12_0_PA_CH5_BIT); + soc_pa |= ((na_nps & 0x100) << 5); + soc_pa += (node_inst >> 1) * (SOCKET_LFB_SIZE >> 1); + } else if (nps == UMC_MEMORY_PARTITION_MODE_NPS4) { + soc_pa &= ~(0x3ULL << UMC_V12_0_PA_CH4_BIT); + soc_pa |= ((na_nps & 0x300) << 4); + soc_pa += node_inst * (SOCKET_LFB_SIZE >> 2); + } else if (nps == UMC_MEMORY_PARTITION_MODE_NPS8) { + soc_pa &= ~(0x7ULL << UMC_V12_0_PA_CH4_BIT); + soc_pa |= ((na_nps & 0x700) << 4); + soc_pa += node_inst * (SOCKET_LFB_SIZE >> 2) + + (channel_index >> 4) * (SOCKET_LFB_SIZE >> 3); + } + + addr_out->pa = soc_pa; + addr_out->bank = bank; + addr_out->channel_idx = channel_index; + + return 0; +} + +static int convert_ma_to_pa(struct ras_core_context *ras_core, + struct umc_mca_addr *addr_in, struct umc_phy_addr *addr_out, + uint32_t nps) +{ + int ret; + + if (ras_psp_check_supported_cmd(ras_core, RAS_TA_CMD_ID__QUERY_ADDRESS)) + ret = ras_umc_psp_convert_ma_to_pa(ras_core, + addr_in, addr_out, nps); + else + ret = umc_v12_convert_ma_to_pa(ras_core, + addr_in, addr_out, nps); + + return ret; +} + +static int convert_bank_to_nps_addr(struct ras_core_context *ras_core, + struct ras_bank_ecc *bank, struct umc_phy_addr *pa_addr, uint32_t nps) +{ + struct umc_mca_addr addr_in; + struct umc_phy_addr addr_out; + int ret; + + memset(&addr_in, 0, sizeof(addr_in)); + memset(&addr_out, 0, sizeof(addr_out)); + + addr_in.err_addr = ACA_ADDR_2_ERR_ADDR(bank->addr); + addr_in.ch_inst = ACA_IPID_2_UMC_CH(bank->ipid); + addr_in.umc_inst = ACA_IPID_2_UMC_INST(bank->ipid); + addr_in.node_inst = ACA_IPID_2_DIE_ID(bank->ipid); + addr_in.socket_id = ACA_IPID_2_SOCKET_ID(bank->ipid); + + ret = convert_ma_to_pa(ras_core, &addr_in, &addr_out, nps); + if (!ret) { + pa_addr->pa = + convert_nps_pa_to_row_pa(ras_core, addr_out.pa, nps, false); + pa_addr->channel_idx = addr_out.channel_idx; + pa_addr->bank = addr_out.bank; + } + + return ret; +} + +static int umc_v12_0_bank_to_eeprom_record(struct ras_core_context *ras_core, + struct ras_bank_ecc *bank, struct eeprom_umc_record *record) +{ + struct umc_phy_addr nps_addr; + int ret; + + memset(&nps_addr, 0, sizeof(nps_addr)); + + ret = convert_bank_to_nps_addr(ras_core, bank, + &nps_addr, bank->nps); + if (ret) + return ret; + + ras_umc_fill_eeprom_record(ras_core, + ACA_ADDR_2_ERR_ADDR(bank->addr), ACA_IPID_2_UMC_INST(bank->ipid), + &nps_addr, bank->nps, record); + + lookup_bad_pages_in_a_row(ras_core, record, + bank->nps, NULL, 0, bank->seq_no, true); + + return 0; +} + +static int convert_eeprom_record_to_nps_addr(struct ras_core_context *ras_core, + struct eeprom_umc_record *record, uint64_t *pa, uint32_t nps) +{ + struct device_system_info dev_info = {0}; + struct umc_mca_addr addr_in; + struct umc_phy_addr addr_out; + int ret; + + memset(&addr_in, 0, sizeof(addr_in)); + memset(&addr_out, 0, sizeof(addr_out)); + + ras_core_get_device_system_info(ras_core, &dev_info); + + addr_in.err_addr = record->address; + addr_in.ch_inst = record->mem_channel; + addr_in.umc_inst = record->mcumc_id; + addr_in.node_inst = UMC_INV_AID_NODE; + addr_in.socket_id = dev_info.socket_id; + + ret = convert_ma_to_pa(ras_core, &addr_in, &addr_out, nps); + if (ret) + return ret; + + *pa = convert_nps_pa_to_row_pa(ras_core, addr_out.pa, nps, false); + + return 0; +} + +static int umc_v12_0_eeprom_record_to_nps_record(struct ras_core_context *ras_core, + struct eeprom_umc_record *record, uint32_t nps) +{ + uint64_t pa = 0; + int ret = 0; + + if (nps == EEPROM_RECORD_UMC_NPS_MODE(record)) { + record->cur_nps_retired_row_pfn = EEPROM_RECORD_UMC_ADDR_PFN(record); + } else { + ret = convert_eeprom_record_to_nps_addr(ras_core, + record, &pa, nps); + if (!ret) + record->cur_nps_retired_row_pfn = RAS_ADDR_TO_PFN(pa); + } + + record->cur_nps = nps; + + return ret; +} + +static int umc_v12_0_eeprom_record_to_nps_pages(struct ras_core_context *ras_core, + struct eeprom_umc_record *record, uint32_t nps, + uint64_t *pfns, uint32_t num) +{ + return lookup_bad_pages_in_a_row(ras_core, + record, nps, pfns, num, 0, false); +} + +static int umc_12_0_soc_pa_to_bank(struct ras_core_context *ras_core, + uint64_t soc_pa, + struct umc_bank_addr *bank_addr) +{ + + int channel_hashed = 0; + int channel_real = 0; + int channel_reversed = 0; + int i = 0; + + bank_addr->stack_id = UMC_V12_0_SOC_PA_TO_SID(soc_pa); + bank_addr->bank_group = 0; /* This is a combination of SID & Bank. Needed?? */ + bank_addr->bank = UMC_V12_0_SOC_PA_TO_BANK(soc_pa); + bank_addr->row = UMC_V12_0_SOC_PA_TO_ROW(soc_pa); + bank_addr->column = UMC_V12_0_SOC_PA_TO_COL(soc_pa); + + /* Channel bits 4-6 are hashed. Bruteforce reverse the hash */ + channel_hashed = (soc_pa >> UMC_V12_0_PA_CH4_BIT) & 0x7; + + for (i = 0; i < 8; i++) { + channel_reversed = 0; + channel_reversed |= UMC_V12_0_CHANNEL_HASH_CH4((i << 4), soc_pa); + channel_reversed |= (UMC_V12_0_CHANNEL_HASH_CH5((i << 4), soc_pa) << 1); + channel_reversed |= (UMC_V12_0_CHANNEL_HASH_CH6((i << 4), soc_pa) << 2); + if (channel_reversed == channel_hashed) + channel_real = ((i << 4)) | ((soc_pa >> UMC_V12_0_PA_CH0_BIT) & 0xf); + } + + bank_addr->channel = channel_real; + bank_addr->subchannel = UMC_V12_0_SOC_PA_TO_PC(soc_pa); + + return 0; +} + +static int umc_12_0_bank_to_soc_pa(struct ras_core_context *ras_core, + struct umc_bank_addr bank_addr, + uint64_t *soc_pa) +{ + uint64_t na = 0; + uint64_t tmp_pa = 0; + *soc_pa = 0; + + tmp_pa |= UMC_V12_0_SOC_SID_TO_PA(bank_addr.stack_id); + tmp_pa |= UMC_V12_0_SOC_BANK_TO_PA(bank_addr.bank); + tmp_pa |= UMC_V12_0_SOC_ROW_TO_PA(bank_addr.row); + tmp_pa |= UMC_V12_0_SOC_COL_TO_PA(bank_addr.column); + tmp_pa |= UMC_V12_0_SOC_CH_TO_PA(bank_addr.channel); + tmp_pa |= UMC_V12_0_SOC_PC_TO_PA(bank_addr.subchannel); + + /* Get the NA */ + na = ((tmp_pa >> UMC_V12_0_PA_C2_BIT) << UMC_V12_0_NA_C2_BIT); + na |= tmp_pa & 0xff; + + /* translate umc channel address to soc pa, 3 parts are included */ + tmp_pa = ADDR_OF_32KB_BLOCK(na) | + ADDR_OF_256B_BLOCK(bank_addr.channel) | + OFFSET_IN_256B_BLOCK(na); + + /* the umc channel bits are not original values, they are hashed */ + UMC_V12_0_SET_CHANNEL_HASH(bank_addr.channel, tmp_pa); + + *soc_pa = tmp_pa; + + return 0; +} + +const struct ras_umc_ip_func ras_umc_func_v12_0 = { + .bank_to_eeprom_record = umc_v12_0_bank_to_eeprom_record, + .eeprom_record_to_nps_record = umc_v12_0_eeprom_record_to_nps_record, + .eeprom_record_to_nps_pages = umc_v12_0_eeprom_record_to_nps_pages, + .bank_to_soc_pa = umc_12_0_bank_to_soc_pa, + .soc_pa_to_bank = umc_12_0_soc_pa_to_bank, +}; + diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.h b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.h new file mode 100644 index 0000000000000..8a35ad856165c --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.h @@ -0,0 +1,314 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __RAS_UMC_V12_0_H__ +#define __RAS_UMC_V12_0_H__ +#include "ras.h" + +/* MCA_UMC_UMC0_MCUMC_ADDRT0 */ +#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT 0x0 +#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT 0x38 +#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK 0x00FFFFFFFFFFFFFFL +#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved_MASK 0xFF00000000000000L + +/* MCMP1_IPIDT0 */ +#define MCMP1_IPIDT0__InstanceIdLo__SHIFT 0x0 +#define MCMP1_IPIDT0__HardwareID__SHIFT 0x20 +#define MCMP1_IPIDT0__InstanceIdHi__SHIFT 0x2c +#define MCMP1_IPIDT0__McaType__SHIFT 0x30 + +#define MCMP1_IPIDT0__InstanceIdLo_MASK 0x00000000FFFFFFFFL +#define MCMP1_IPIDT0__HardwareID_MASK 0x00000FFF00000000L +#define MCMP1_IPIDT0__InstanceIdHi_MASK 0x0000F00000000000L +#define MCMP1_IPIDT0__McaType_MASK 0xFFFF000000000000L + +/* number of umc channel instance with memory map register access */ +#define UMC_V12_0_CHANNEL_INSTANCE_NUM 8 +/* number of umc instance with memory map register access */ +#define UMC_V12_0_UMC_INSTANCE_NUM 4 + +/* one piece of normalized address is mapped to 8 pieces of physical address */ +#define UMC_V12_0_NA_MAP_PA_NUM 8 + +/* bank bits in MCA error address */ +#define UMC_V12_0_MCA_B0_BIT 6 +#define UMC_V12_0_MCA_B1_BIT 7 +#define UMC_V12_0_MCA_B2_BIT 8 +#define UMC_V12_0_MCA_B3_BIT 9 + +/* row bits in MCA address */ +#define UMC_V12_0_MCA_R0_BIT 10 + +/* Stack ID bits in SOC physical address */ +#define UMC_V12_0_PA_SID1_BIT 37 +#define UMC_V12_0_PA_SID0_BIT 36 + +/* bank bits in SOC physical address */ +#define UMC_V12_0_PA_B3_BIT 18 +#define UMC_V12_0_PA_B2_BIT 17 +#define UMC_V12_0_PA_B1_BIT 20 +#define UMC_V12_0_PA_B0_BIT 19 + +/* row bits in SOC physical address */ +#define UMC_V12_0_PA_R13_BIT 35 +#define UMC_V12_0_PA_R12_BIT 34 +#define UMC_V12_0_PA_R11_BIT 33 +#define UMC_V12_0_PA_R10_BIT 32 +#define UMC_V12_0_PA_R9_BIT 31 +#define UMC_V12_0_PA_R8_BIT 30 +#define UMC_V12_0_PA_R7_BIT 29 +#define UMC_V12_0_PA_R6_BIT 28 +#define UMC_V12_0_PA_R5_BIT 27 +#define UMC_V12_0_PA_R4_BIT 26 +#define UMC_V12_0_PA_R3_BIT 25 +#define UMC_V12_0_PA_R2_BIT 24 +#define UMC_V12_0_PA_R1_BIT 23 +#define UMC_V12_0_PA_R0_BIT 22 + +/* column bits in SOC physical address */ +#define UMC_V12_0_PA_C4_BIT 21 +#define UMC_V12_0_PA_C3_BIT 16 +#define UMC_V12_0_PA_C2_BIT 15 +#define UMC_V12_0_PA_C1_BIT 6 +#define UMC_V12_0_PA_C0_BIT 5 + +/* channel index bits in SOC physical address */ +#define UMC_V12_0_PA_CH6_BIT 14 +#define UMC_V12_0_PA_CH5_BIT 13 +#define UMC_V12_0_PA_CH4_BIT 12 +#define UMC_V12_0_PA_CH3_BIT 11 +#define UMC_V12_0_PA_CH2_BIT 10 +#define UMC_V12_0_PA_CH1_BIT 9 +#define UMC_V12_0_PA_CH0_BIT 8 + +/* Pseudochannel index bits in SOC physical address */ +#define UMC_V12_0_PA_PC0_BIT 7 + +#define UMC_V12_0_NA_C2_BIT 8 + +#define UMC_V12_0_SOC_PA_TO_SID(pa) \ + ((((pa >> UMC_V12_0_PA_SID0_BIT) & 0x1ULL) << 0ULL) | \ + (((pa >> UMC_V12_0_PA_SID1_BIT) & 0x1ULL) << 1ULL)) + +#define UMC_V12_0_SOC_PA_TO_BANK(pa) \ + ((((pa >> UMC_V12_0_PA_B0_BIT) & 0x1ULL) << 0ULL) | \ + (((pa >> UMC_V12_0_PA_B1_BIT) & 0x1ULL) << 1ULL) | \ + (((pa >> UMC_V12_0_PA_B2_BIT) & 0x1ULL) << 2ULL) | \ + (((pa >> UMC_V12_0_PA_B3_BIT) & 0x1ULL) << 3ULL)) + +#define UMC_V12_0_SOC_PA_TO_ROW(pa) \ + ((((pa >> UMC_V12_0_PA_R0_BIT) & 0x1ULL) << 0ULL) | \ + (((pa >> UMC_V12_0_PA_R1_BIT) & 0x1ULL) << 1ULL) | \ + (((pa >> UMC_V12_0_PA_R2_BIT) & 0x1ULL) << 2ULL) | \ + (((pa >> UMC_V12_0_PA_R3_BIT) & 0x1ULL) << 3ULL) | \ + (((pa >> UMC_V12_0_PA_R4_BIT) & 0x1ULL) << 4ULL) | \ + (((pa >> UMC_V12_0_PA_R5_BIT) & 0x1ULL) << 5ULL) | \ + (((pa >> UMC_V12_0_PA_R6_BIT) & 0x1ULL) << 6ULL) | \ + (((pa >> UMC_V12_0_PA_R7_BIT) & 0x1ULL) << 7ULL) | \ + (((pa >> UMC_V12_0_PA_R8_BIT) & 0x1ULL) << 8ULL) | \ + (((pa >> UMC_V12_0_PA_R9_BIT) & 0x1ULL) << 9ULL) | \ + (((pa >> UMC_V12_0_PA_R10_BIT) & 0x1ULL) << 10ULL) | \ + (((pa >> UMC_V12_0_PA_R11_BIT) & 0x1ULL) << 11ULL) | \ + (((pa >> UMC_V12_0_PA_R12_BIT) & 0x1ULL) << 12ULL) | \ + (((pa >> UMC_V12_0_PA_R13_BIT) & 0x1ULL) << 13ULL)) + +#define UMC_V12_0_SOC_PA_TO_COL(pa) \ + ((((pa >> UMC_V12_0_PA_C0_BIT) & 0x1ULL) << 0ULL) | \ + (((pa >> UMC_V12_0_PA_C1_BIT) & 0x1ULL) << 1ULL) | \ + (((pa >> UMC_V12_0_PA_C2_BIT) & 0x1ULL) << 2ULL) | \ + (((pa >> UMC_V12_0_PA_C3_BIT) & 0x1ULL) << 3ULL) | \ + (((pa >> UMC_V12_0_PA_C4_BIT) & 0x1ULL) << 4ULL)) + +#define UMC_V12_0_SOC_PA_TO_CH(pa) \ + ((((pa >> UMC_V12_0_PA_CH0_BIT) & 0x1ULL) << 0ULL) | \ + (((pa >> UMC_V12_0_PA_CH1_BIT) & 0x1ULL) << 1ULL) | \ + (((pa >> UMC_V12_0_PA_CH2_BIT) & 0x1ULL) << 2ULL) | \ + (((pa >> UMC_V12_0_PA_CH3_BIT) & 0x1ULL) << 3ULL) | \ + (((pa >> UMC_V12_0_PA_CH4_BIT) & 0x1ULL) << 4ULL) | \ + (((pa >> UMC_V12_0_PA_CH5_BIT) & 0x1ULL) << 5ULL) | \ + (((pa >> UMC_V12_0_PA_CH6_BIT) & 0x1ULL) << 6ULL)) + +#define UMC_V12_0_SOC_PA_TO_PC(pa) (((pa >> UMC_V12_0_PA_PC0_BIT) & 0x1ULL) << 0ULL) + +#define UMC_V12_0_SOC_SID_TO_PA(sid) \ + ((((sid >> 0ULL) & 0x1ULL) << UMC_V12_0_PA_SID0_BIT) | \ + (((sid >> 1ULL) & 0x1ULL) << UMC_V12_0_PA_SID1_BIT)) + +#define UMC_V12_0_SOC_BANK_TO_PA(bank) \ + ((((bank >> 0ULL) & 0x1ULL) << UMC_V12_0_PA_B0_BIT) | \ + (((bank >> 1ULL) & 0x1ULL) << UMC_V12_0_PA_B1_BIT) | \ + (((bank >> 2ULL) & 0x1ULL) << UMC_V12_0_PA_B2_BIT) | \ + (((bank >> 3ULL) & 0x1ULL) << UMC_V12_0_PA_B3_BIT)) + +#define UMC_V12_0_SOC_ROW_TO_PA(row) \ + ((((row >> 0ULL) & 0x1ULL) << UMC_V12_0_PA_R0_BIT) | \ + (((row >> 1ULL) & 0x1ULL) << UMC_V12_0_PA_R1_BIT) | \ + (((row >> 2ULL) & 0x1ULL) << UMC_V12_0_PA_R2_BIT) | \ + (((row >> 3ULL) & 0x1ULL) << UMC_V12_0_PA_R3_BIT) | \ + (((row >> 4ULL) & 0x1ULL) << UMC_V12_0_PA_R4_BIT) | \ + (((row >> 5ULL) & 0x1ULL) << UMC_V12_0_PA_R5_BIT) | \ + (((row >> 6ULL) & 0x1ULL) << UMC_V12_0_PA_R6_BIT) | \ + (((row >> 7ULL) & 0x1ULL) << UMC_V12_0_PA_R7_BIT) | \ + (((row >> 8ULL) & 0x1ULL) << UMC_V12_0_PA_R8_BIT) | \ + (((row >> 9ULL) & 0x1ULL) << UMC_V12_0_PA_R9_BIT) | \ + (((row >> 10ULL) & 0x1ULL) << UMC_V12_0_PA_R10_BIT) | \ + (((row >> 11ULL) & 0x1ULL) << UMC_V12_0_PA_R11_BIT) | \ + (((row >> 12ULL) & 0x1ULL) << UMC_V12_0_PA_R12_BIT) | \ + (((row >> 13ULL) & 0x1ULL) << UMC_V12_0_PA_R13_BIT)) + +#define UMC_V12_0_SOC_COL_TO_PA(col) \ + ((((col >> 0ULL) & 0x1ULL) << UMC_V12_0_PA_C0_BIT) | \ + (((col >> 1ULL) & 0x1ULL) << UMC_V12_0_PA_C1_BIT) | \ + (((col >> 2ULL) & 0x1ULL) << UMC_V12_0_PA_C2_BIT) | \ + (((col >> 3ULL) & 0x1ULL) << UMC_V12_0_PA_C3_BIT) | \ + (((col >> 4ULL) & 0x1ULL) << UMC_V12_0_PA_C4_BIT)) + +#define UMC_V12_0_SOC_CH_TO_PA(ch) \ + ((((ch >> 0ULL) & 0x1ULL) << UMC_V12_0_PA_CH0_BIT) | \ + (((ch >> 1ULL) & 0x1ULL) << UMC_V12_0_PA_CH1_BIT) | \ + (((ch >> 2ULL) & 0x1ULL) << UMC_V12_0_PA_CH2_BIT) | \ + (((ch >> 3ULL) & 0x1ULL) << UMC_V12_0_PA_CH3_BIT) | \ + (((ch >> 4ULL) & 0x1ULL) << UMC_V12_0_PA_CH4_BIT) | \ + (((ch >> 5ULL) & 0x1ULL) << UMC_V12_0_PA_CH5_BIT) | \ + (((ch >> 6ULL) & 0x1ULL) << UMC_V12_0_PA_CH6_BIT)) + +#define UMC_V12_0_SOC_PC_TO_PA(pc) (((pc >> 0ULL) & 0x1ULL) << UMC_V12_0_PA_PC0_BIT) + +/* bank hash settings */ +#define UMC_V12_0_XOR_EN0 1 +#define UMC_V12_0_XOR_EN1 1 +#define UMC_V12_0_XOR_EN2 1 +#define UMC_V12_0_XOR_EN3 1 +#define UMC_V12_0_COL_XOR0 0x0 +#define UMC_V12_0_COL_XOR1 0x0 +#define UMC_V12_0_COL_XOR2 0x800 +#define UMC_V12_0_COL_XOR3 0x1000 +#define UMC_V12_0_ROW_XOR0 0x11111 +#define UMC_V12_0_ROW_XOR1 0x22222 +#define UMC_V12_0_ROW_XOR2 0x4444 +#define UMC_V12_0_ROW_XOR3 0x8888 + +/* channel hash settings */ +#define UMC_V12_0_HASH_4K 0 +#define UMC_V12_0_HASH_64K 1 +#define UMC_V12_0_HASH_2M 1 +#define UMC_V12_0_HASH_1G 1 +#define UMC_V12_0_HASH_1T 1 + +/* XOR some bits of PA into CH4~CH6 bits (bits 12~14 of PA), + * hash bit is only effective when related setting is enabled + */ +#define UMC_V12_0_CHANNEL_HASH_CH4(channel_idx, pa) ((((channel_idx) >> 5) & 0x1) ^ \ + (((pa) >> 20) & 0x1ULL & UMC_V12_0_HASH_64K) ^ \ + (((pa) >> 27) & 0x1ULL & UMC_V12_0_HASH_2M) ^ \ + (((pa) >> 34) & 0x1ULL & UMC_V12_0_HASH_1G) ^ \ + (((pa) >> 41) & 0x1ULL & UMC_V12_0_HASH_1T)) +#define UMC_V12_0_CHANNEL_HASH_CH5(channel_idx, pa) ((((channel_idx) >> 6) & 0x1) ^ \ + (((pa) >> 21) & 0x1ULL & UMC_V12_0_HASH_64K) ^ \ + (((pa) >> 28) & 0x1ULL & UMC_V12_0_HASH_2M) ^ \ + (((pa) >> 35) & 0x1ULL & UMC_V12_0_HASH_1G) ^ \ + (((pa) >> 42) & 0x1ULL & UMC_V12_0_HASH_1T)) +#define UMC_V12_0_CHANNEL_HASH_CH6(channel_idx, pa) ((((channel_idx) >> 4) & 0x1) ^ \ + (((pa) >> 19) & 0x1ULL & UMC_V12_0_HASH_64K) ^ \ + (((pa) >> 26) & 0x1ULL & UMC_V12_0_HASH_2M) ^ \ + (((pa) >> 33) & 0x1ULL & UMC_V12_0_HASH_1G) ^ \ + (((pa) >> 40) & 0x1ULL & UMC_V12_0_HASH_1T) ^ \ + (((pa) >> 47) & 0x1ULL & UMC_V12_0_HASH_1T)) +#define UMC_V12_0_SET_CHANNEL_HASH(channel_idx, pa) do { \ + (pa) &= ~(0x7ULL << UMC_V12_0_PA_CH4_BIT); \ + (pa) |= (UMC_V12_0_CHANNEL_HASH_CH4(channel_idx, pa) << UMC_V12_0_PA_CH4_BIT); \ + (pa) |= (UMC_V12_0_CHANNEL_HASH_CH5(channel_idx, pa) << UMC_V12_0_PA_CH5_BIT); \ + (pa) |= (UMC_V12_0_CHANNEL_HASH_CH6(channel_idx, pa) << UMC_V12_0_PA_CH6_BIT); \ + } while (0) + + +/* + * (addr / 256) * 4096, the higher 26 bits in ErrorAddr + * is the index of 4KB block + */ +#define ADDR_OF_4KB_BLOCK(addr) (((addr) & ~0xffULL) << 4) +/* + * (addr / 256) * 8192, the higher 26 bits in ErrorAddr + * is the index of 8KB block + */ +#define ADDR_OF_8KB_BLOCK(addr) (((addr) & ~0xffULL) << 5) +/* + * (addr / 256) * 32768, the higher 26 bits in ErrorAddr + * is the index of 8KB block + */ +#define ADDR_OF_32KB_BLOCK(addr) (((addr) & ~0xffULL) << 7) +/* channel index is the index of 256B block */ +#define ADDR_OF_256B_BLOCK(channel_index) ((channel_index) << 8) +/* offset in 256B block */ +#define OFFSET_IN_256B_BLOCK(addr) ((addr) & 0xffULL) + + +#define UMC_V12_ADDR_MASK_BAD_COLS(addr) \ + ((addr) & ~((0x3ULL << UMC_V12_0_PA_C2_BIT) | \ + (0x1ULL << UMC_V12_0_PA_C4_BIT) | \ + (0x1ULL << UMC_V12_0_PA_R13_BIT))) + +#define ACA_IPID_HI_2_UMC_AID(_ipid_hi) (((_ipid_hi) >> 2) & 0x3) +#define ACA_IPID_LO_2_UMC_CH(_ipid_lo) \ + (((((_ipid_lo) >> 20) & 0x1) * 4) + (((_ipid_lo) >> 12) & 0xF)) +#define ACA_IPID_LO_2_UMC_INST(_ipid_lo) (((_ipid_lo) >> 21) & 0x7) + +#define ACA_IPID_2_DIE_ID(ipid) ((REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi) >> 2) & 0x03) +#define ACA_IPID_2_UMC_CH(ipid) \ + (ACA_IPID_LO_2_UMC_CH(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo))) + +#define ACA_IPID_2_UMC_INST(ipid) \ + (ACA_IPID_LO_2_UMC_INST(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo))) + +#define ACA_IPID_2_SOCKET_ID(ipid) \ + (((REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo) & 0x1) << 2) | \ + (REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi) & 0x03)) + +#define ACA_ADDR_2_ERR_ADDR(addr) \ + REG_GET_FIELD(addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr) + +/* R13 bit shift should be considered, double the number */ +#define UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL (UMC_V12_0_NA_MAP_PA_NUM * 2) + + +/* C2, C3, C4, R13, four MCA bits are looped in page retirement */ +#define UMC_V12_0_RETIRE_LOOP_BITS 4 + +/* invalid node instance value */ +#define UMC_INV_AID_NODE 0xffff + +#define UMC_V12_0_AID_NUM_MAX 4 +#define UMC_V12_0_SOCKET_NUM_MAX 8 + +#define UMC_V12_0_TOTAL_CHANNEL_NUM \ + (UMC_V12_0_AID_NUM_MAX * UMC_V12_0_UMC_INSTANCE_NUM * UMC_V12_0_CHANNEL_INSTANCE_NUM) + +/* one device has 192GB HBM */ +#define SOCKET_LFB_SIZE 0x3000000000ULL + +extern const struct ras_umc_ip_func ras_umc_func_v12_0; + +int ras_umc_get_badpage_count(struct ras_core_context *ras_core); +int ras_umc_get_badpage_record(struct ras_core_context *ras_core, uint32_t index, void *record); +#endif + From eb7ffe30bf81b95daef41d91e7a3d0203947ffc8 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 17:26:49 +0800 Subject: [PATCH 2090/2653] drm/amd/ras: Add umc common ras functions Add umc common ras functions. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/ras/rascore/ras_umc.c | 706 ++++++++++++++++++++++ drivers/gpu/drm/amd/ras/rascore/ras_umc.h | 166 +++++ 2 files changed, 872 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_umc.c create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_umc.h diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c new file mode 100644 index 0000000000000..4067359bb2993 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c @@ -0,0 +1,706 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "ras.h" +#include "ras_umc.h" +#include "ras_umc_v12_0.h" + +#define MAX_ECC_NUM_PER_RETIREMENT 16 + +/* bad page timestamp format + * yy[31:27] mm[26:23] day[22:17] hh[16:12] mm[11:6] ss[5:0] + */ +#define EEPROM_TIMESTAMP_MINUTE 6 +#define EEPROM_TIMESTAMP_HOUR 12 +#define EEPROM_TIMESTAMP_DAY 17 +#define EEPROM_TIMESTAMP_MONTH 23 +#define EEPROM_TIMESTAMP_YEAR 27 + +static uint64_t ras_umc_get_eeprom_timestamp(struct ras_core_context *ras_core) +{ + struct ras_time tm = {0}; + uint64_t utc_timestamp = 0; + uint64_t eeprom_timestamp = 0; + + utc_timestamp = ras_core_get_utc_second_timestamp(ras_core); + if (!utc_timestamp) + return utc_timestamp; + + ras_core_convert_timestamp_to_time(ras_core, utc_timestamp, &tm); + + /* the year range is 2000 ~ 2031, set the year if not in the range */ + if (tm.tm_year < 2000) + tm.tm_year = 2000; + if (tm.tm_year > 2031) + tm.tm_year = 2031; + + tm.tm_year -= 2000; + + eeprom_timestamp = tm.tm_sec + (tm.tm_min << EEPROM_TIMESTAMP_MINUTE) + + (tm.tm_hour << EEPROM_TIMESTAMP_HOUR) + + (tm.tm_mday << EEPROM_TIMESTAMP_DAY) + + (tm.tm_mon << EEPROM_TIMESTAMP_MONTH) + + (tm.tm_year << EEPROM_TIMESTAMP_YEAR); + eeprom_timestamp &= 0xffffffff; + + return eeprom_timestamp; +} + +static const struct ras_umc_ip_func *ras_umc_get_ip_func( + struct ras_core_context *ras_core, uint32_t ip_version) +{ + switch (ip_version) { + case IP_VERSION(12, 0, 0): + return &ras_umc_func_v12_0; + default: + RAS_DEV_ERR(ras_core->dev, + "UMC ip version(0x%x) is not supported!\n", ip_version); + break; + } + + return NULL; +} + +int ras_umc_psp_convert_ma_to_pa(struct ras_core_context *ras_core, + struct umc_mca_addr *in, struct umc_phy_addr *out, + uint32_t nps) +{ + struct ras_ta_query_address_input addr_in; + struct ras_ta_query_address_output addr_out; + int ret; + + if (!in) + return -EINVAL; + + memset(&addr_in, 0, sizeof(addr_in)); + memset(&addr_out, 0, sizeof(addr_out)); + + addr_in.ma.err_addr = in->err_addr; + addr_in.ma.ch_inst = in->ch_inst; + addr_in.ma.umc_inst = in->umc_inst; + addr_in.ma.node_inst = in->node_inst; + addr_in.ma.socket_id = in->socket_id; + + addr_in.addr_type = RAS_TA_MCA_TO_PA; + + ret = ras_psp_query_address(ras_core, &addr_in, &addr_out); + if (ret) { + RAS_DEV_WARN(ras_core->dev, + "Failed to query RAS physical address for 0x%llx, ret:%d", + in->err_addr, ret); + return -EREMOTEIO; + } + + if (out) { + out->pa = addr_out.pa.pa; + out->bank = addr_out.pa.bank; + out->channel_idx = addr_out.pa.channel_idx; + } + + return 0; +} + +static int ras_umc_log_ecc(struct ras_core_context *ras_core, + unsigned long idx, void *data) +{ + struct ras_umc *ras_umc = &ras_core->ras_umc; + int ret; + + mutex_lock(&ras_umc->tree_lock); + ret = radix_tree_insert(&ras_umc->root, idx, data); + if (!ret) + radix_tree_tag_set(&ras_umc->root, idx, UMC_ECC_NEW_DETECTED_TAG); + mutex_unlock(&ras_umc->tree_lock); + + return ret; +} + +int ras_umc_clear_logged_ecc(struct ras_core_context *ras_core) +{ + struct ras_umc *ras_umc = &ras_core->ras_umc; + uint64_t buf[8] = {0}; + void **slot; + void *data; + void *iter = buf; + + mutex_lock(&ras_umc->tree_lock); + radix_tree_for_each_slot(slot, &ras_umc->root, iter, 0) { + data = ras_radix_tree_delete_iter(&ras_umc->root, iter); + kfree(data); + } + mutex_unlock(&ras_umc->tree_lock); + + return 0; +} + +static void ras_umc_reserve_eeprom_record(struct ras_core_context *ras_core, + struct eeprom_umc_record *record) +{ + struct ras_umc *ras_umc = &ras_core->ras_umc; + uint64_t page_pfn[16]; + int count = 0, i; + + memset(page_pfn, 0, sizeof(page_pfn)); + if (ras_umc->ip_func && ras_umc->ip_func->eeprom_record_to_nps_pages) { + count = ras_umc->ip_func->eeprom_record_to_nps_pages(ras_core, + record, record->cur_nps, page_pfn, ARRAY_SIZE(page_pfn)); + if (count <= 0) { + RAS_DEV_ERR(ras_core->dev, + "Fail to convert error address! count:%d\n", count); + return; + } + } + + /* Reserve memory */ + for (i = 0; i < count; i++) + ras_core_event_notify(ras_core, + RAS_EVENT_ID__RESERVE_BAD_PAGE, &page_pfn[i]); +} + +/* When gpu reset is ongoing, ecc logging operations will be pended. + */ +int ras_umc_log_bad_bank_pending(struct ras_core_context *ras_core, struct ras_bank_ecc *bank) +{ + struct ras_umc *ras_umc = &ras_core->ras_umc; + struct ras_bank_ecc_node *ecc_node; + + ecc_node = kzalloc(sizeof(*ecc_node), GFP_KERNEL); + if (!ecc_node) + return -ENOMEM; + + memcpy(&ecc_node->ecc, bank, sizeof(ecc_node->ecc)); + + mutex_lock(&ras_umc->pending_ecc_lock); + list_add_tail(&ecc_node->node, &ras_umc->pending_ecc_list); + mutex_unlock(&ras_umc->pending_ecc_lock); + + return 0; +} + +/* After gpu reset is complete, re-log the pending error banks. + */ +int ras_umc_log_pending_bad_bank(struct ras_core_context *ras_core) +{ + struct ras_umc *ras_umc = &ras_core->ras_umc; + struct ras_bank_ecc_node *ecc_node, *tmp; + + mutex_lock(&ras_umc->pending_ecc_lock); + list_for_each_entry_safe(ecc_node, + tmp, &ras_umc->pending_ecc_list, node){ + if (ecc_node && !ras_umc_log_bad_bank(ras_core, &ecc_node->ecc)) { + list_del(&ecc_node->node); + kfree(ecc_node); + } + } + mutex_unlock(&ras_umc->pending_ecc_lock); + + return 0; +} + +int ras_umc_log_bad_bank(struct ras_core_context *ras_core, struct ras_bank_ecc *bank) +{ + struct ras_umc *ras_umc = &ras_core->ras_umc; + struct eeprom_umc_record umc_rec; + struct eeprom_umc_record *err_rec; + int ret; + + memset(&umc_rec, 0, sizeof(umc_rec)); + + mutex_lock(&ras_umc->bank_log_lock); + ret = ras_umc->ip_func->bank_to_eeprom_record(ras_core, bank, &umc_rec); + if (ret) + goto out; + + err_rec = kzalloc(sizeof(*err_rec), GFP_KERNEL); + if (!err_rec) { + ret = -ENOMEM; + goto out; + } + + memcpy(err_rec, &umc_rec, sizeof(umc_rec)); + ret = ras_umc_log_ecc(ras_core, err_rec->cur_nps_retired_row_pfn, err_rec); + if (ret) { + if (ret == -EEXIST) { + RAS_DEV_INFO(ras_core->dev, "The bad pages have been logged before.\n"); + ret = 0; + } + + kfree(err_rec); + goto out; + } + + ras_umc_reserve_eeprom_record(ras_core, err_rec); + + ret = ras_core_event_notify(ras_core, + RAS_EVENT_ID__BAD_PAGE_DETECTED, NULL); + +out: + mutex_unlock(&ras_umc->bank_log_lock); + return ret; +} + +static int ras_umc_get_new_records(struct ras_core_context *ras_core, + struct eeprom_umc_record *records, u32 num) +{ + struct ras_umc *ras_umc = &ras_core->ras_umc; + struct eeprom_umc_record *entries[MAX_ECC_NUM_PER_RETIREMENT]; + u32 entry_num = num < MAX_ECC_NUM_PER_RETIREMENT ? num : MAX_ECC_NUM_PER_RETIREMENT; + int count = 0; + int new_detected, i; + + mutex_lock(&ras_umc->tree_lock); + new_detected = radix_tree_gang_lookup_tag(&ras_umc->root, (void **)entries, + 0, entry_num, UMC_ECC_NEW_DETECTED_TAG); + for (i = 0; i < new_detected; i++) { + if (!entries[i]) + continue; + + memcpy(&records[i], entries[i], sizeof(struct eeprom_umc_record)); + count++; + radix_tree_tag_clear(&ras_umc->root, + entries[i]->cur_nps_retired_row_pfn, UMC_ECC_NEW_DETECTED_TAG); + } + mutex_unlock(&ras_umc->tree_lock); + + return count; +} + +static bool ras_umc_check_retired_record(struct ras_core_context *ras_core, + struct eeprom_umc_record *record, bool from_eeprom) +{ + struct ras_umc *ras_umc = &ras_core->ras_umc; + struct eeprom_store_record *data = &ras_umc->umc_err_data.rom_data; + uint32_t nps = 0; + int i, ret; + + if (from_eeprom) { + nps = ras_umc->umc_err_data.umc_nps_mode; + if (ras_umc->ip_func && ras_umc->ip_func->eeprom_record_to_nps_record) { + ret = ras_umc->ip_func->eeprom_record_to_nps_record(ras_core, record, nps); + if (ret) + RAS_DEV_WARN(ras_core->dev, + "Failed to adjust eeprom record, ret:%d", ret); + } + return false; + } + + for (i = 0; i < data->count; i++) { + if ((data->bps[i].retired_row_pfn == record->retired_row_pfn) && + (data->bps[i].cur_nps_retired_row_pfn == record->cur_nps_retired_row_pfn)) + return true; + } + + return false; +} + +/* alloc/realloc bps array */ +static int ras_umc_realloc_err_data_space(struct ras_core_context *ras_core, + struct eeprom_store_record *data, int pages) +{ + unsigned int old_space = data->count + data->space_left; + unsigned int new_space = old_space + pages; + unsigned int align_space = ALIGN(new_space, 512); + void *bps = kzalloc(align_space * sizeof(*data->bps), GFP_KERNEL); + + if (!bps) + return -ENOMEM; + + if (data->bps) { + memcpy(bps, data->bps, + data->count * sizeof(*data->bps)); + kfree(data->bps); + } + + data->bps = bps; + data->space_left += align_space - old_space; + return 0; +} + +static int ras_umc_update_eeprom_rom_data(struct ras_core_context *ras_core, + struct eeprom_umc_record *bps) +{ + struct eeprom_store_record *data = &ras_core->ras_umc.umc_err_data.rom_data; + + if (!data->space_left && + ras_umc_realloc_err_data_space(ras_core, data, 256)) { + return -ENOMEM; + } + + memcpy(&data->bps[data->count], bps, sizeof(*data->bps)); + data->count++; + data->space_left--; + return 0; +} + +static int ras_umc_update_eeprom_ram_data(struct ras_core_context *ras_core, + struct eeprom_umc_record *bps) +{ + struct ras_umc *ras_umc = &ras_core->ras_umc; + struct eeprom_store_record *data = &ras_umc->umc_err_data.ram_data; + uint64_t page_pfn[16]; + int count = 0, j; + + if (!data->space_left && + ras_umc_realloc_err_data_space(ras_core, data, 256)) { + return -ENOMEM; + } + + memset(page_pfn, 0, sizeof(page_pfn)); + if (ras_umc->ip_func && ras_umc->ip_func->eeprom_record_to_nps_pages) + count = ras_umc->ip_func->eeprom_record_to_nps_pages(ras_core, + bps, bps->cur_nps, page_pfn, ARRAY_SIZE(page_pfn)); + + if (count > 0) { + for (j = 0; j < count; j++) { + bps->cur_nps_retired_row_pfn = page_pfn[j]; + memcpy(&data->bps[data->count], bps, sizeof(*data->bps)); + data->count++; + data->space_left--; + } + } else { + memcpy(&data->bps[data->count], bps, sizeof(*data->bps)); + data->count++; + data->space_left--; + } + + return 0; +} + +/* it deal with vram only. */ +static int ras_umc_add_bad_pages(struct ras_core_context *ras_core, + struct eeprom_umc_record *bps, + int pages, bool from_eeprom) +{ + struct ras_umc *ras_umc = &ras_core->ras_umc; + struct ras_umc_err_data *data = &ras_umc->umc_err_data; + int i, ret = 0; + + if (!bps || pages <= 0) + return 0; + + mutex_lock(&ras_umc->umc_lock); + for (i = 0; i < pages; i++) { + if (ras_umc_check_retired_record(ras_core, &bps[i], from_eeprom)) + continue; + + ret = ras_umc_update_eeprom_rom_data(ras_core, &bps[i]); + if (ret) + goto out; + + if (data->last_retired_pfn == bps[i].cur_nps_retired_row_pfn) + continue; + + data->last_retired_pfn = bps[i].cur_nps_retired_row_pfn; + + if (from_eeprom) + ras_umc_reserve_eeprom_record(ras_core, &bps[i]); + + ret = ras_umc_update_eeprom_ram_data(ras_core, &bps[i]); + if (ret) + goto out; + } +out: + mutex_unlock(&ras_umc->umc_lock); + + return ret; +} + +/* + * read error record array in eeprom and reserve enough space for + * storing new bad pages + */ +int ras_umc_load_bad_pages(struct ras_core_context *ras_core) +{ + struct eeprom_umc_record *bps; + uint32_t ras_num_recs; + int ret; + + ras_num_recs = ras_eeprom_get_record_count(ras_core); + /* no bad page record, skip eeprom access */ + if (!ras_num_recs || + ras_core->ras_eeprom.record_threshold_config == DISABLE_RETIRE_PAGE) + return 0; + + bps = kcalloc(ras_num_recs, sizeof(*bps), GFP_KERNEL); + if (!bps) + return -ENOMEM; + + ret = ras_eeprom_read(ras_core, bps, ras_num_recs); + if (ret) { + RAS_DEV_ERR(ras_core->dev, "Failed to load EEPROM table records!"); + } else { + ras_core->ras_umc.umc_err_data.last_retired_pfn = UMC_INV_MEM_PFN; + ret = ras_umc_add_bad_pages(ras_core, bps, ras_num_recs, true); + } + + kfree(bps); + return ret; +} + +/* + * write error record array to eeprom, the function should be + * protected by recovery_lock + * new_cnt: new added UE count, excluding reserved bad pages, can be NULL + */ +static int ras_umc_save_bad_pages(struct ras_core_context *ras_core) +{ + struct ras_umc *ras_umc = &ras_core->ras_umc; + struct eeprom_store_record *data = &ras_umc->umc_err_data.rom_data; + uint32_t eeprom_record_num; + int save_count; + int ret = 0; + + if (!data->bps) + return 0; + + eeprom_record_num = ras_eeprom_get_record_count(ras_core); + mutex_lock(&ras_umc->umc_lock); + save_count = data->count - eeprom_record_num; + /* only new entries are saved */ + if (save_count > 0) { + if (ras_eeprom_append(ras_core, + &data->bps[eeprom_record_num], + save_count)) { + RAS_DEV_ERR(ras_core->dev, "Failed to save EEPROM table data!"); + ret = -EIO; + goto exit; + } + + RAS_DEV_INFO(ras_core->dev, "Saved %d pages to EEPROM table.\n", save_count); + } + +exit: + mutex_unlock(&ras_umc->umc_lock); + return ret; +} + +int ras_umc_handle_bad_pages(struct ras_core_context *ras_core, void *data) +{ + struct eeprom_umc_record records[MAX_ECC_NUM_PER_RETIREMENT]; + int count, ret; + + memset(records, 0, sizeof(records)); + count = ras_umc_get_new_records(ras_core, records, ARRAY_SIZE(records)); + if (count <= 0) + return -ENODATA; + + ret = ras_umc_add_bad_pages(ras_core, records, count, false); + if (ret) { + RAS_DEV_ERR(ras_core->dev, "Failed to add ras bad page!\n"); + return -EINVAL; + } + + ret = ras_umc_save_bad_pages(ras_core); + if (ret) { + RAS_DEV_ERR(ras_core->dev, "Failed to save ras bad page\n"); + return -EINVAL; + } + + return 0; +} + +int ras_umc_sw_init(struct ras_core_context *ras_core) +{ + struct ras_umc *ras_umc = &ras_core->ras_umc; + + memset(ras_umc, 0, sizeof(*ras_umc)); + + INIT_LIST_HEAD(&ras_umc->pending_ecc_list); + + INIT_RADIX_TREE(&ras_umc->root, GFP_KERNEL); + + mutex_init(&ras_umc->tree_lock); + mutex_init(&ras_umc->pending_ecc_lock); + mutex_init(&ras_umc->umc_lock); + mutex_init(&ras_umc->bank_log_lock); + + return 0; +} + +int ras_umc_sw_fini(struct ras_core_context *ras_core) +{ + struct ras_umc *ras_umc = &ras_core->ras_umc; + struct ras_umc_err_data *umc_err_data = &ras_umc->umc_err_data; + struct ras_bank_ecc_node *ecc_node, *tmp; + + mutex_destroy(&ras_umc->umc_lock); + mutex_destroy(&ras_umc->bank_log_lock); + + if (umc_err_data->rom_data.bps) { + umc_err_data->rom_data.count = 0; + kfree(umc_err_data->rom_data.bps); + umc_err_data->rom_data.bps = NULL; + umc_err_data->rom_data.space_left = 0; + } + + if (umc_err_data->ram_data.bps) { + umc_err_data->ram_data.count = 0; + kfree(umc_err_data->ram_data.bps); + umc_err_data->ram_data.bps = NULL; + umc_err_data->ram_data.space_left = 0; + } + + ras_umc_clear_logged_ecc(ras_core); + + mutex_lock(&ras_umc->pending_ecc_lock); + list_for_each_entry_safe(ecc_node, + tmp, &ras_umc->pending_ecc_list, node){ + list_del(&ecc_node->node); + kfree(ecc_node); + } + mutex_unlock(&ras_umc->pending_ecc_lock); + + mutex_destroy(&ras_umc->tree_lock); + mutex_destroy(&ras_umc->pending_ecc_lock); + + return 0; +} + +int ras_umc_hw_init(struct ras_core_context *ras_core) +{ + struct ras_umc *ras_umc = &ras_core->ras_umc; + uint32_t nps; + + nps = ras_core_get_curr_nps_mode(ras_core); + + if (!nps || (nps >= UMC_MEMORY_PARTITION_MODE_UNKNOWN)) { + RAS_DEV_ERR(ras_core->dev, "Invalid memory NPS mode: %u!\n", nps); + return -ENODATA; + } + + ras_umc->umc_err_data.umc_nps_mode = nps; + + ras_umc->umc_vram_type = ras_core->config->umc_cfg.umc_vram_type; + if (!ras_umc->umc_vram_type) { + RAS_DEV_ERR(ras_core->dev, "Invalid UMC VRAM Type: %u!\n", + ras_umc->umc_vram_type); + return -ENODATA; + } + + ras_umc->umc_ip_version = ras_core->config->umc_ip_version; + ras_umc->ip_func = ras_umc_get_ip_func(ras_core, ras_umc->umc_ip_version); + if (!ras_umc->ip_func) + return -EINVAL; + + return 0; +} + +int ras_umc_hw_fini(struct ras_core_context *ras_core) +{ + return 0; +} + +int ras_umc_clean_badpage_data(struct ras_core_context *ras_core) +{ + struct ras_umc_err_data *data = &ras_core->ras_umc.umc_err_data; + + mutex_lock(&ras_core->ras_umc.umc_lock); + + kfree(data->rom_data.bps); + kfree(data->ram_data.bps); + + memset(data, 0, sizeof(*data)); + mutex_unlock(&ras_core->ras_umc.umc_lock); + + return 0; +} + +int ras_umc_fill_eeprom_record(struct ras_core_context *ras_core, + uint64_t err_addr, uint32_t umc_inst, struct umc_phy_addr *cur_nps_addr, + enum umc_memory_partition_mode cur_nps, struct eeprom_umc_record *record) +{ + struct eeprom_umc_record *err_rec = record; + + /* Set bad page pfn and nps mode */ + EEPROM_RECORD_SETUP_UMC_ADDR_AND_NPS(err_rec, + RAS_ADDR_TO_PFN(cur_nps_addr->pa), cur_nps); + + err_rec->address = err_addr; + err_rec->ts = ras_umc_get_eeprom_timestamp(ras_core); + err_rec->err_type = RAS_EEPROM_ERR_NON_RECOVERABLE; + err_rec->cu = 0; + err_rec->mem_channel = cur_nps_addr->channel_idx; + err_rec->mcumc_id = umc_inst; + err_rec->cur_nps_retired_row_pfn = RAS_ADDR_TO_PFN(cur_nps_addr->pa); + err_rec->cur_nps_bank = cur_nps_addr->bank; + err_rec->cur_nps = cur_nps; + return 0; +} + +int ras_umc_get_saved_eeprom_count(struct ras_core_context *ras_core) +{ + struct ras_umc_err_data *err_data = &ras_core->ras_umc.umc_err_data; + + return err_data->rom_data.count; +} + +int ras_umc_get_badpage_count(struct ras_core_context *ras_core) +{ + struct eeprom_store_record *data = &ras_core->ras_umc.umc_err_data.ram_data; + + return data->count; +} + +int ras_umc_get_badpage_record(struct ras_core_context *ras_core, uint32_t index, void *record) +{ + struct eeprom_store_record *data = &ras_core->ras_umc.umc_err_data.ram_data; + + if (index >= data->count) + return -EINVAL; + + memcpy(record, &data->bps[index], sizeof(struct eeprom_umc_record)); + return 0; +} + +bool ras_umc_check_retired_addr(struct ras_core_context *ras_core, uint64_t addr) +{ + struct ras_umc *ras_umc = &ras_core->ras_umc; + struct eeprom_store_record *data = &ras_umc->umc_err_data.ram_data; + uint64_t page_pfn = RAS_ADDR_TO_PFN(addr); + int i, ret = false; + + mutex_lock(&ras_umc->umc_lock); + for (i = 0; i < data->count; i++) { + if (data->bps[i].cur_nps_retired_row_pfn == page_pfn) { + ret = true; + break; + } + } + mutex_unlock(&ras_umc->umc_lock); + + return ret; +} + +int ras_umc_translate_soc_pa_and_bank(struct ras_core_context *ras_core, + uint64_t *soc_pa, struct umc_bank_addr *bank_addr, bool bank_to_pa) +{ + struct ras_umc *ras_umc = &ras_core->ras_umc; + int ret = 0; + + if (bank_to_pa) + ret = ras_umc->ip_func->bank_to_soc_pa(ras_core, *bank_addr, soc_pa); + else + ret = ras_umc->ip_func->soc_pa_to_bank(ras_core, *soc_pa, bank_addr); + + return ret; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.h b/drivers/gpu/drm/amd/ras/rascore/ras_umc.h new file mode 100644 index 0000000000000..7d9e779d8c4c6 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.h @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __RAS_UMC_H__ +#define __RAS_UMC_H__ +#include "ras.h" +#include "ras_eeprom.h" +#include "ras_cmd.h" + +#define UMC_VRAM_TYPE_UNKNOWN 0 +#define UMC_VRAM_TYPE_GDDR1 1 +#define UMC_VRAM_TYPE_DDR2 2 +#define UMC_VRAM_TYPE_GDDR3 3 +#define UMC_VRAM_TYPE_GDDR4 4 +#define UMC_VRAM_TYPE_GDDR5 5 +#define UMC_VRAM_TYPE_HBM 6 +#define UMC_VRAM_TYPE_DDR3 7 +#define UMC_VRAM_TYPE_DDR4 8 +#define UMC_VRAM_TYPE_GDDR6 9 +#define UMC_VRAM_TYPE_DDR5 10 +#define UMC_VRAM_TYPE_LPDDR4 11 +#define UMC_VRAM_TYPE_LPDDR5 12 +#define UMC_VRAM_TYPE_HBM3E 13 + +#define UMC_ECC_NEW_DETECTED_TAG 0x1 +#define UMC_INV_MEM_PFN (0xFFFFFFFFFFFFFFFF) + +/* three column bits and one row bit in MCA address flip + * in bad page retirement + */ +#define UMC_PA_FLIP_BITS_NUM 4 + +enum umc_memory_partition_mode { + UMC_MEMORY_PARTITION_MODE_NONE = 0, + UMC_MEMORY_PARTITION_MODE_NPS1 = 1, + UMC_MEMORY_PARTITION_MODE_NPS2 = 2, + UMC_MEMORY_PARTITION_MODE_NPS3 = 3, + UMC_MEMORY_PARTITION_MODE_NPS4 = 4, + UMC_MEMORY_PARTITION_MODE_NPS6 = 6, + UMC_MEMORY_PARTITION_MODE_NPS8 = 8, + UMC_MEMORY_PARTITION_MODE_UNKNOWN +}; + +struct ras_core_context; +struct ras_bank_ecc; + +struct umc_flip_bits { + uint32_t flip_bits_in_pa[UMC_PA_FLIP_BITS_NUM]; + uint32_t flip_row_bit; + uint32_t r13_in_pa; + uint32_t bit_num; +}; + +struct umc_mca_addr { + uint64_t err_addr; + uint32_t ch_inst; + uint32_t umc_inst; + uint32_t node_inst; + uint32_t socket_id; +}; + +struct umc_phy_addr { + uint64_t pa; + uint32_t bank; + uint32_t channel_idx; +}; + +struct umc_bank_addr { + uint32_t stack_id; /* SID */ + uint32_t bank_group; + uint32_t bank; + uint32_t row; + uint32_t column; + uint32_t channel; + uint32_t subchannel; /* Also called Pseudochannel (PC) */ +}; + +struct ras_umc_ip_func { + int (*bank_to_eeprom_record)(struct ras_core_context *ras_core, + struct ras_bank_ecc *bank, struct eeprom_umc_record *record); + int (*eeprom_record_to_nps_record)(struct ras_core_context *ras_core, + struct eeprom_umc_record *record, uint32_t nps); + int (*eeprom_record_to_nps_pages)(struct ras_core_context *ras_core, + struct eeprom_umc_record *record, uint32_t nps, + uint64_t *pfns, uint32_t num); + int (*bank_to_soc_pa)(struct ras_core_context *ras_core, + struct umc_bank_addr bank_addr, uint64_t *soc_pa); + int (*soc_pa_to_bank)(struct ras_core_context *ras_core, + uint64_t soc_pa, struct umc_bank_addr *bank_addr); +}; + +struct eeprom_store_record { + /* point to data records array */ + struct eeprom_umc_record *bps; + /* the count of entries */ + int count; + /* the space can place new entries */ + int space_left; +}; + +struct ras_umc_err_data { + struct eeprom_store_record rom_data; + struct eeprom_store_record ram_data; + enum umc_memory_partition_mode umc_nps_mode; + uint64_t last_retired_pfn; +}; + +struct ras_umc { + u32 umc_ip_version; + u32 umc_vram_type; + const struct ras_umc_ip_func *ip_func; + struct radix_tree_root root; + struct mutex tree_lock; + struct mutex umc_lock; + struct mutex bank_log_lock; + struct mutex pending_ecc_lock; + struct ras_umc_err_data umc_err_data; + struct list_head pending_ecc_list; +}; + +int ras_umc_sw_init(struct ras_core_context *ras); +int ras_umc_sw_fini(struct ras_core_context *ras); +int ras_umc_hw_init(struct ras_core_context *ras); +int ras_umc_hw_fini(struct ras_core_context *ras); +int ras_umc_psp_convert_ma_to_pa(struct ras_core_context *ras_core, + struct umc_mca_addr *in, struct umc_phy_addr *out, + uint32_t nps); +int ras_umc_handle_bad_pages(struct ras_core_context *ras_core, void *data); +int ras_umc_log_bad_bank(struct ras_core_context *ras, struct ras_bank_ecc *bank); +int ras_umc_log_bad_bank_pending(struct ras_core_context *ras_core, struct ras_bank_ecc *bank); +int ras_umc_log_pending_bad_bank(struct ras_core_context *ras_core); +int ras_umc_clear_logged_ecc(struct ras_core_context *ras_core); +int ras_umc_load_bad_pages(struct ras_core_context *ras_core); +int ras_umc_get_saved_eeprom_count(struct ras_core_context *ras_core); +int ras_umc_clean_badpage_data(struct ras_core_context *ras_core); +int ras_umc_fill_eeprom_record(struct ras_core_context *ras_core, + uint64_t err_addr, uint32_t umc_inst, struct umc_phy_addr *cur_nps_addr, + enum umc_memory_partition_mode cur_nps, struct eeprom_umc_record *record); + +int ras_umc_get_badpage_count(struct ras_core_context *ras_core); +int ras_umc_get_badpage_record(struct ras_core_context *ras_core, uint32_t index, void *record); +bool ras_umc_check_retired_addr(struct ras_core_context *ras_core, uint64_t addr); +int ras_umc_translate_soc_pa_and_bank(struct ras_core_context *ras_core, + uint64_t *soc_pa, struct umc_bank_addr *bank_addr, bool bank_to_pa); +#endif From e10f5d61b1209fdbd828468c62a15b57650ee176 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 17:29:02 +0800 Subject: [PATCH 2091/2653] drm/amd/ras: Add gfx v9_0 ras functions Add gfx v9_0 ras functions. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/ras/rascore/ras_gfx_v9_0.c | 426 ++++++++++++++++++ .../gpu/drm/amd/ras/rascore/ras_gfx_v9_0.h | 259 +++++++++++ 2 files changed, 685 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_gfx_v9_0.c create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_gfx_v9_0.h diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_gfx_v9_0.c b/drivers/gpu/drm/amd/ras/rascore/ras_gfx_v9_0.c new file mode 100644 index 0000000000000..6213d3f125be6 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_gfx_v9_0.c @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "ras.h" +#include "ras_gfx_v9_0.h" +#include "ras_core_status.h" + +enum ta_gfx_v9_subblock { + /*CPC*/ + TA_GFX_V9__GFX_CPC_INDEX_START = 0, + TA_GFX_V9__GFX_CPC_SCRATCH = TA_GFX_V9__GFX_CPC_INDEX_START, + TA_GFX_V9__GFX_CPC_UCODE, + TA_GFX_V9__GFX_DC_STATE_ME1, + TA_GFX_V9__GFX_DC_CSINVOC_ME1, + TA_GFX_V9__GFX_DC_RESTORE_ME1, + TA_GFX_V9__GFX_DC_STATE_ME2, + TA_GFX_V9__GFX_DC_CSINVOC_ME2, + TA_GFX_V9__GFX_DC_RESTORE_ME2, + TA_GFX_V9__GFX_CPC_INDEX_END = TA_GFX_V9__GFX_DC_RESTORE_ME2, + /* CPF*/ + TA_GFX_V9__GFX_CPF_INDEX_START, + TA_GFX_V9__GFX_CPF_ROQ_ME2 = TA_GFX_V9__GFX_CPF_INDEX_START, + TA_GFX_V9__GFX_CPF_ROQ_ME1, + TA_GFX_V9__GFX_CPF_TAG, + TA_GFX_V9__GFX_CPF_INDEX_END = TA_GFX_V9__GFX_CPF_TAG, + /* CPG*/ + TA_GFX_V9__GFX_CPG_INDEX_START, + TA_GFX_V9__GFX_CPG_DMA_ROQ = TA_GFX_V9__GFX_CPG_INDEX_START, + TA_GFX_V9__GFX_CPG_DMA_TAG, + TA_GFX_V9__GFX_CPG_TAG, + TA_GFX_V9__GFX_CPG_INDEX_END = TA_GFX_V9__GFX_CPG_TAG, + /* GDS*/ + TA_GFX_V9__GFX_GDS_INDEX_START, + TA_GFX_V9__GFX_GDS_MEM = TA_GFX_V9__GFX_GDS_INDEX_START, + TA_GFX_V9__GFX_GDS_INPUT_QUEUE, + TA_GFX_V9__GFX_GDS_OA_PHY_CMD_RAM_MEM, + TA_GFX_V9__GFX_GDS_OA_PHY_DATA_RAM_MEM, + TA_GFX_V9__GFX_GDS_OA_PIPE_MEM, + TA_GFX_V9__GFX_GDS_INDEX_END = TA_GFX_V9__GFX_GDS_OA_PIPE_MEM, + /* SPI*/ + TA_GFX_V9__GFX_SPI_SR_MEM, + /* SQ*/ + TA_GFX_V9__GFX_SQ_INDEX_START, + TA_GFX_V9__GFX_SQ_SGPR = TA_GFX_V9__GFX_SQ_INDEX_START, + TA_GFX_V9__GFX_SQ_LDS_D, + TA_GFX_V9__GFX_SQ_LDS_I, + TA_GFX_V9__GFX_SQ_VGPR, /* VGPR = SP*/ + TA_GFX_V9__GFX_SQ_INDEX_END = TA_GFX_V9__GFX_SQ_VGPR, + /* SQC (3 ranges)*/ + TA_GFX_V9__GFX_SQC_INDEX_START, + /* SQC range 0*/ + TA_GFX_V9__GFX_SQC_INDEX0_START = TA_GFX_V9__GFX_SQC_INDEX_START, + TA_GFX_V9__GFX_SQC_INST_UTCL1_LFIFO = + TA_GFX_V9__GFX_SQC_INDEX0_START, + TA_GFX_V9__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, + TA_GFX_V9__GFX_SQC_DATA_CU0_UTCL1_LFIFO, + TA_GFX_V9__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, + TA_GFX_V9__GFX_SQC_DATA_CU1_UTCL1_LFIFO, + TA_GFX_V9__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, + TA_GFX_V9__GFX_SQC_DATA_CU2_UTCL1_LFIFO, + TA_GFX_V9__GFX_SQC_INDEX0_END = + TA_GFX_V9__GFX_SQC_DATA_CU2_UTCL1_LFIFO, + /* SQC range 1*/ + TA_GFX_V9__GFX_SQC_INDEX1_START, + TA_GFX_V9__GFX_SQC_INST_BANKA_TAG_RAM = + TA_GFX_V9__GFX_SQC_INDEX1_START, + TA_GFX_V9__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, + TA_GFX_V9__GFX_SQC_INST_BANKA_MISS_FIFO, + TA_GFX_V9__GFX_SQC_INST_BANKA_BANK_RAM, + TA_GFX_V9__GFX_SQC_DATA_BANKA_TAG_RAM, + TA_GFX_V9__GFX_SQC_DATA_BANKA_HIT_FIFO, + TA_GFX_V9__GFX_SQC_DATA_BANKA_MISS_FIFO, + TA_GFX_V9__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, + TA_GFX_V9__GFX_SQC_DATA_BANKA_BANK_RAM, + TA_GFX_V9__GFX_SQC_INDEX1_END = + TA_GFX_V9__GFX_SQC_DATA_BANKA_BANK_RAM, + /* SQC range 2*/ + TA_GFX_V9__GFX_SQC_INDEX2_START, + TA_GFX_V9__GFX_SQC_INST_BANKB_TAG_RAM = + TA_GFX_V9__GFX_SQC_INDEX2_START, + TA_GFX_V9__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, + TA_GFX_V9__GFX_SQC_INST_BANKB_MISS_FIFO, + TA_GFX_V9__GFX_SQC_INST_BANKB_BANK_RAM, + TA_GFX_V9__GFX_SQC_DATA_BANKB_TAG_RAM, + TA_GFX_V9__GFX_SQC_DATA_BANKB_HIT_FIFO, + TA_GFX_V9__GFX_SQC_DATA_BANKB_MISS_FIFO, + TA_GFX_V9__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, + TA_GFX_V9__GFX_SQC_DATA_BANKB_BANK_RAM, + TA_GFX_V9__GFX_SQC_INDEX2_END = + TA_GFX_V9__GFX_SQC_DATA_BANKB_BANK_RAM, + TA_GFX_V9__GFX_SQC_INDEX_END = TA_GFX_V9__GFX_SQC_INDEX2_END, + /* TA*/ + TA_GFX_V9__GFX_TA_INDEX_START, + TA_GFX_V9__GFX_TA_FS_DFIFO = TA_GFX_V9__GFX_TA_INDEX_START, + TA_GFX_V9__GFX_TA_FS_AFIFO, + TA_GFX_V9__GFX_TA_FL_LFIFO, + TA_GFX_V9__GFX_TA_FX_LFIFO, + TA_GFX_V9__GFX_TA_FS_CFIFO, + TA_GFX_V9__GFX_TA_INDEX_END = TA_GFX_V9__GFX_TA_FS_CFIFO, + /* TCA*/ + TA_GFX_V9__GFX_TCA_INDEX_START, + TA_GFX_V9__GFX_TCA_HOLE_FIFO = TA_GFX_V9__GFX_TCA_INDEX_START, + TA_GFX_V9__GFX_TCA_REQ_FIFO, + TA_GFX_V9__GFX_TCA_INDEX_END = TA_GFX_V9__GFX_TCA_REQ_FIFO, + /* TCC (5 sub-ranges)*/ + TA_GFX_V9__GFX_TCC_INDEX_START, + /* TCC range 0*/ + TA_GFX_V9__GFX_TCC_INDEX0_START = TA_GFX_V9__GFX_TCC_INDEX_START, + TA_GFX_V9__GFX_TCC_CACHE_DATA = TA_GFX_V9__GFX_TCC_INDEX0_START, + TA_GFX_V9__GFX_TCC_CACHE_DATA_BANK_0_1, + TA_GFX_V9__GFX_TCC_CACHE_DATA_BANK_1_0, + TA_GFX_V9__GFX_TCC_CACHE_DATA_BANK_1_1, + TA_GFX_V9__GFX_TCC_CACHE_DIRTY_BANK_0, + TA_GFX_V9__GFX_TCC_CACHE_DIRTY_BANK_1, + TA_GFX_V9__GFX_TCC_HIGH_RATE_TAG, + TA_GFX_V9__GFX_TCC_LOW_RATE_TAG, + TA_GFX_V9__GFX_TCC_INDEX0_END = TA_GFX_V9__GFX_TCC_LOW_RATE_TAG, + /* TCC range 1*/ + TA_GFX_V9__GFX_TCC_INDEX1_START, + TA_GFX_V9__GFX_TCC_IN_USE_DEC = TA_GFX_V9__GFX_TCC_INDEX1_START, + TA_GFX_V9__GFX_TCC_IN_USE_TRANSFER, + TA_GFX_V9__GFX_TCC_INDEX1_END = + TA_GFX_V9__GFX_TCC_IN_USE_TRANSFER, + /* TCC range 2*/ + TA_GFX_V9__GFX_TCC_INDEX2_START, + TA_GFX_V9__GFX_TCC_RETURN_DATA = TA_GFX_V9__GFX_TCC_INDEX2_START, + TA_GFX_V9__GFX_TCC_RETURN_CONTROL, + TA_GFX_V9__GFX_TCC_UC_ATOMIC_FIFO, + TA_GFX_V9__GFX_TCC_WRITE_RETURN, + TA_GFX_V9__GFX_TCC_WRITE_CACHE_READ, + TA_GFX_V9__GFX_TCC_SRC_FIFO, + TA_GFX_V9__GFX_TCC_SRC_FIFO_NEXT_RAM, + TA_GFX_V9__GFX_TCC_CACHE_TAG_PROBE_FIFO, + TA_GFX_V9__GFX_TCC_INDEX2_END = + TA_GFX_V9__GFX_TCC_CACHE_TAG_PROBE_FIFO, + /* TCC range 3*/ + TA_GFX_V9__GFX_TCC_INDEX3_START, + TA_GFX_V9__GFX_TCC_LATENCY_FIFO = TA_GFX_V9__GFX_TCC_INDEX3_START, + TA_GFX_V9__GFX_TCC_LATENCY_FIFO_NEXT_RAM, + TA_GFX_V9__GFX_TCC_INDEX3_END = + TA_GFX_V9__GFX_TCC_LATENCY_FIFO_NEXT_RAM, + /* TCC range 4*/ + TA_GFX_V9__GFX_TCC_INDEX4_START, + TA_GFX_V9__GFX_TCC_WRRET_TAG_WRITE_RETURN = + TA_GFX_V9__GFX_TCC_INDEX4_START, + TA_GFX_V9__GFX_TCC_ATOMIC_RETURN_BUFFER, + TA_GFX_V9__GFX_TCC_INDEX4_END = + TA_GFX_V9__GFX_TCC_ATOMIC_RETURN_BUFFER, + TA_GFX_V9__GFX_TCC_INDEX_END = TA_GFX_V9__GFX_TCC_INDEX4_END, + /* TCI*/ + TA_GFX_V9__GFX_TCI_WRITE_RAM, + /* TCP*/ + TA_GFX_V9__GFX_TCP_INDEX_START, + TA_GFX_V9__GFX_TCP_CACHE_RAM = TA_GFX_V9__GFX_TCP_INDEX_START, + TA_GFX_V9__GFX_TCP_LFIFO_RAM, + TA_GFX_V9__GFX_TCP_CMD_FIFO, + TA_GFX_V9__GFX_TCP_VM_FIFO, + TA_GFX_V9__GFX_TCP_DB_RAM, + TA_GFX_V9__GFX_TCP_UTCL1_LFIFO0, + TA_GFX_V9__GFX_TCP_UTCL1_LFIFO1, + TA_GFX_V9__GFX_TCP_INDEX_END = TA_GFX_V9__GFX_TCP_UTCL1_LFIFO1, + /* TD*/ + TA_GFX_V9__GFX_TD_INDEX_START, + TA_GFX_V9__GFX_TD_SS_FIFO_LO = TA_GFX_V9__GFX_TD_INDEX_START, + TA_GFX_V9__GFX_TD_SS_FIFO_HI, + TA_GFX_V9__GFX_TD_CS_FIFO, + TA_GFX_V9__GFX_TD_INDEX_END = TA_GFX_V9__GFX_TD_CS_FIFO, + /* EA (3 sub-ranges)*/ + TA_GFX_V9__GFX_EA_INDEX_START, + /* EA range 0*/ + TA_GFX_V9__GFX_EA_INDEX0_START = TA_GFX_V9__GFX_EA_INDEX_START, + TA_GFX_V9__GFX_EA_DRAMRD_CMDMEM = TA_GFX_V9__GFX_EA_INDEX0_START, + TA_GFX_V9__GFX_EA_DRAMWR_CMDMEM, + TA_GFX_V9__GFX_EA_DRAMWR_DATAMEM, + TA_GFX_V9__GFX_EA_RRET_TAGMEM, + TA_GFX_V9__GFX_EA_WRET_TAGMEM, + TA_GFX_V9__GFX_EA_GMIRD_CMDMEM, + TA_GFX_V9__GFX_EA_GMIWR_CMDMEM, + TA_GFX_V9__GFX_EA_GMIWR_DATAMEM, + TA_GFX_V9__GFX_EA_INDEX0_END = TA_GFX_V9__GFX_EA_GMIWR_DATAMEM, + /* EA range 1*/ + TA_GFX_V9__GFX_EA_INDEX1_START, + TA_GFX_V9__GFX_EA_DRAMRD_PAGEMEM = TA_GFX_V9__GFX_EA_INDEX1_START, + TA_GFX_V9__GFX_EA_DRAMWR_PAGEMEM, + TA_GFX_V9__GFX_EA_IORD_CMDMEM, + TA_GFX_V9__GFX_EA_IOWR_CMDMEM, + TA_GFX_V9__GFX_EA_IOWR_DATAMEM, + TA_GFX_V9__GFX_EA_GMIRD_PAGEMEM, + TA_GFX_V9__GFX_EA_GMIWR_PAGEMEM, + TA_GFX_V9__GFX_EA_INDEX1_END = TA_GFX_V9__GFX_EA_GMIWR_PAGEMEM, + /* EA range 2*/ + TA_GFX_V9__GFX_EA_INDEX2_START, + TA_GFX_V9__GFX_EA_MAM_D0MEM = TA_GFX_V9__GFX_EA_INDEX2_START, + TA_GFX_V9__GFX_EA_MAM_D1MEM, + TA_GFX_V9__GFX_EA_MAM_D2MEM, + TA_GFX_V9__GFX_EA_MAM_D3MEM, + TA_GFX_V9__GFX_EA_INDEX2_END = TA_GFX_V9__GFX_EA_MAM_D3MEM, + TA_GFX_V9__GFX_EA_INDEX_END = TA_GFX_V9__GFX_EA_INDEX2_END, + /* UTC VM L2 bank*/ + TA_GFX_V9__UTC_VML2_BANK_CACHE, + /* UTC VM walker*/ + TA_GFX_V9__UTC_VML2_WALKER, + /* UTC ATC L2 2MB cache*/ + TA_GFX_V9__UTC_ATCL2_CACHE_2M_BANK, + /* UTC ATC L2 4KB cache*/ + TA_GFX_V9__UTC_ATCL2_CACHE_4K_BANK, + TA_GFX_V9__GFX_MAX +}; + +struct ras_gfx_subblock_t { + unsigned char *name; + int ta_subblock; + int hw_supported_error_type; + int sw_supported_error_type; +}; + +#define RAS_GFX_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h) \ + [RAS_GFX_V9__##subblock] = { \ + #subblock, \ + TA_GFX_V9__##subblock, \ + ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)), \ + (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)), \ + } + +const struct ras_gfx_subblock_t ras_gfx_v9_0_subblocks[] = { + RAS_GFX_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1), + RAS_GFX_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1), + RAS_GFX_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0), + RAS_GFX_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0), + RAS_GFX_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1), + RAS_GFX_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0), + RAS_GFX_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1), + RAS_GFX_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1), + RAS_GFX_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1), + RAS_GFX_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1), + RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, + 0, 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, + 0, 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, + 0, 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, + 1), + RAS_GFX_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, + 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, + 0, 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, + 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, + 0, 0), + RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1), + RAS_GFX_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0), + RAS_GFX_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1), + RAS_GFX_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0, + 1), + RAS_GFX_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0, + 1), + RAS_GFX_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0, + 1), + RAS_GFX_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0), + RAS_GFX_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0), + RAS_GFX_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0, + 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0, + 0), + RAS_GFX_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1), + RAS_GFX_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1), + RAS_GFX_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1), + RAS_GFX_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0), + RAS_GFX_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0), +}; + +static int gfx_v9_0_get_ta_subblock(struct ras_core_context *ras_core, + uint32_t error_type, uint32_t subblock, uint32_t *ta_subblock) +{ + const struct ras_gfx_subblock_t *gfx_subblock; + + if (subblock >= ARRAY_SIZE(ras_gfx_v9_0_subblocks)) + return -EINVAL; + + gfx_subblock = &ras_gfx_v9_0_subblocks[subblock]; + if (!gfx_subblock->name) + return -EPERM; + + if (!(gfx_subblock->hw_supported_error_type & error_type)) { + RAS_DEV_ERR(ras_core->dev, "GFX Subblock %s, hardware do not support type 0x%x\n", + gfx_subblock->name, error_type); + return -EPERM; + } + + if (!(gfx_subblock->sw_supported_error_type & error_type)) { + RAS_DEV_ERR(ras_core->dev, "GFX Subblock %s, driver do not support type 0x%x\n", + gfx_subblock->name, error_type); + return -EPERM; + } + + *ta_subblock = gfx_subblock->ta_subblock; + + return 0; +} + +const struct ras_gfx_ip_func gfx_ras_func_v9_0 = { + .get_ta_subblock = gfx_v9_0_get_ta_subblock, +}; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_gfx_v9_0.h b/drivers/gpu/drm/amd/ras/rascore/ras_gfx_v9_0.h new file mode 100644 index 0000000000000..659b566197470 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_gfx_v9_0.h @@ -0,0 +1,259 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __RAS_GFX_V9_0_H__ +#define __RAS_GFX_V9_0_H__ + +enum ras_gfx_v9_subblock { + /* CPC */ + RAS_GFX_V9__GFX_CPC_INDEX_START = 0, + RAS_GFX_V9__GFX_CPC_SCRATCH = + RAS_GFX_V9__GFX_CPC_INDEX_START, + RAS_GFX_V9__GFX_CPC_UCODE, + RAS_GFX_V9__GFX_DC_STATE_ME1, + RAS_GFX_V9__GFX_DC_CSINVOC_ME1, + RAS_GFX_V9__GFX_DC_RESTORE_ME1, + RAS_GFX_V9__GFX_DC_STATE_ME2, + RAS_GFX_V9__GFX_DC_CSINVOC_ME2, + RAS_GFX_V9__GFX_DC_RESTORE_ME2, + RAS_GFX_V9__GFX_CPC_INDEX_END = + RAS_GFX_V9__GFX_DC_RESTORE_ME2, + /* CPF */ + RAS_GFX_V9__GFX_CPF_INDEX_START, + RAS_GFX_V9__GFX_CPF_ROQ_ME2 = + RAS_GFX_V9__GFX_CPF_INDEX_START, + RAS_GFX_V9__GFX_CPF_ROQ_ME1, + RAS_GFX_V9__GFX_CPF_TAG, + RAS_GFX_V9__GFX_CPF_INDEX_END = RAS_GFX_V9__GFX_CPF_TAG, + /* CPG */ + RAS_GFX_V9__GFX_CPG_INDEX_START, + RAS_GFX_V9__GFX_CPG_DMA_ROQ = + RAS_GFX_V9__GFX_CPG_INDEX_START, + RAS_GFX_V9__GFX_CPG_DMA_TAG, + RAS_GFX_V9__GFX_CPG_TAG, + RAS_GFX_V9__GFX_CPG_INDEX_END = RAS_GFX_V9__GFX_CPG_TAG, + /* GDS */ + RAS_GFX_V9__GFX_GDS_INDEX_START, + RAS_GFX_V9__GFX_GDS_MEM = RAS_GFX_V9__GFX_GDS_INDEX_START, + RAS_GFX_V9__GFX_GDS_INPUT_QUEUE, + RAS_GFX_V9__GFX_GDS_OA_PHY_CMD_RAM_MEM, + RAS_GFX_V9__GFX_GDS_OA_PHY_DATA_RAM_MEM, + RAS_GFX_V9__GFX_GDS_OA_PIPE_MEM, + RAS_GFX_V9__GFX_GDS_INDEX_END = + RAS_GFX_V9__GFX_GDS_OA_PIPE_MEM, + /* SPI */ + RAS_GFX_V9__GFX_SPI_SR_MEM, + /* SQ */ + RAS_GFX_V9__GFX_SQ_INDEX_START, + RAS_GFX_V9__GFX_SQ_SGPR = RAS_GFX_V9__GFX_SQ_INDEX_START, + RAS_GFX_V9__GFX_SQ_LDS_D, + RAS_GFX_V9__GFX_SQ_LDS_I, + RAS_GFX_V9__GFX_SQ_VGPR, + RAS_GFX_V9__GFX_SQ_INDEX_END = RAS_GFX_V9__GFX_SQ_VGPR, + /* SQC (3 ranges) */ + RAS_GFX_V9__GFX_SQC_INDEX_START, + /* SQC range 0 */ + RAS_GFX_V9__GFX_SQC_INDEX0_START = + RAS_GFX_V9__GFX_SQC_INDEX_START, + RAS_GFX_V9__GFX_SQC_INST_UTCL1_LFIFO = + RAS_GFX_V9__GFX_SQC_INDEX0_START, + RAS_GFX_V9__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, + RAS_GFX_V9__GFX_SQC_DATA_CU0_UTCL1_LFIFO, + RAS_GFX_V9__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, + RAS_GFX_V9__GFX_SQC_DATA_CU1_UTCL1_LFIFO, + RAS_GFX_V9__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, + RAS_GFX_V9__GFX_SQC_DATA_CU2_UTCL1_LFIFO, + RAS_GFX_V9__GFX_SQC_INDEX0_END = + RAS_GFX_V9__GFX_SQC_DATA_CU2_UTCL1_LFIFO, + /* SQC range 1 */ + RAS_GFX_V9__GFX_SQC_INDEX1_START, + RAS_GFX_V9__GFX_SQC_INST_BANKA_TAG_RAM = + RAS_GFX_V9__GFX_SQC_INDEX1_START, + RAS_GFX_V9__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, + RAS_GFX_V9__GFX_SQC_INST_BANKA_MISS_FIFO, + RAS_GFX_V9__GFX_SQC_INST_BANKA_BANK_RAM, + RAS_GFX_V9__GFX_SQC_DATA_BANKA_TAG_RAM, + RAS_GFX_V9__GFX_SQC_DATA_BANKA_HIT_FIFO, + RAS_GFX_V9__GFX_SQC_DATA_BANKA_MISS_FIFO, + RAS_GFX_V9__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, + RAS_GFX_V9__GFX_SQC_DATA_BANKA_BANK_RAM, + RAS_GFX_V9__GFX_SQC_INDEX1_END = + RAS_GFX_V9__GFX_SQC_DATA_BANKA_BANK_RAM, + /* SQC range 2 */ + RAS_GFX_V9__GFX_SQC_INDEX2_START, + RAS_GFX_V9__GFX_SQC_INST_BANKB_TAG_RAM = + RAS_GFX_V9__GFX_SQC_INDEX2_START, + RAS_GFX_V9__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, + RAS_GFX_V9__GFX_SQC_INST_BANKB_MISS_FIFO, + RAS_GFX_V9__GFX_SQC_INST_BANKB_BANK_RAM, + RAS_GFX_V9__GFX_SQC_DATA_BANKB_TAG_RAM, + RAS_GFX_V9__GFX_SQC_DATA_BANKB_HIT_FIFO, + RAS_GFX_V9__GFX_SQC_DATA_BANKB_MISS_FIFO, + RAS_GFX_V9__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, + RAS_GFX_V9__GFX_SQC_DATA_BANKB_BANK_RAM, + RAS_GFX_V9__GFX_SQC_INDEX2_END = + RAS_GFX_V9__GFX_SQC_DATA_BANKB_BANK_RAM, + RAS_GFX_V9__GFX_SQC_INDEX_END = + RAS_GFX_V9__GFX_SQC_INDEX2_END, + /* TA */ + RAS_GFX_V9__GFX_TA_INDEX_START, + RAS_GFX_V9__GFX_TA_FS_DFIFO = + RAS_GFX_V9__GFX_TA_INDEX_START, + RAS_GFX_V9__GFX_TA_FS_AFIFO, + RAS_GFX_V9__GFX_TA_FL_LFIFO, + RAS_GFX_V9__GFX_TA_FX_LFIFO, + RAS_GFX_V9__GFX_TA_FS_CFIFO, + RAS_GFX_V9__GFX_TA_INDEX_END = RAS_GFX_V9__GFX_TA_FS_CFIFO, + /* TCA */ + RAS_GFX_V9__GFX_TCA_INDEX_START, + RAS_GFX_V9__GFX_TCA_HOLE_FIFO = + RAS_GFX_V9__GFX_TCA_INDEX_START, + RAS_GFX_V9__GFX_TCA_REQ_FIFO, + RAS_GFX_V9__GFX_TCA_INDEX_END = + RAS_GFX_V9__GFX_TCA_REQ_FIFO, + /* TCC (5 sub-ranges) */ + RAS_GFX_V9__GFX_TCC_INDEX_START, + /* TCC range 0 */ + RAS_GFX_V9__GFX_TCC_INDEX0_START = + RAS_GFX_V9__GFX_TCC_INDEX_START, + RAS_GFX_V9__GFX_TCC_CACHE_DATA = + RAS_GFX_V9__GFX_TCC_INDEX0_START, + RAS_GFX_V9__GFX_TCC_CACHE_DATA_BANK_0_1, + RAS_GFX_V9__GFX_TCC_CACHE_DATA_BANK_1_0, + RAS_GFX_V9__GFX_TCC_CACHE_DATA_BANK_1_1, + RAS_GFX_V9__GFX_TCC_CACHE_DIRTY_BANK_0, + RAS_GFX_V9__GFX_TCC_CACHE_DIRTY_BANK_1, + RAS_GFX_V9__GFX_TCC_HIGH_RATE_TAG, + RAS_GFX_V9__GFX_TCC_LOW_RATE_TAG, + RAS_GFX_V9__GFX_TCC_INDEX0_END = + RAS_GFX_V9__GFX_TCC_LOW_RATE_TAG, + /* TCC range 1 */ + RAS_GFX_V9__GFX_TCC_INDEX1_START, + RAS_GFX_V9__GFX_TCC_IN_USE_DEC = + RAS_GFX_V9__GFX_TCC_INDEX1_START, + RAS_GFX_V9__GFX_TCC_IN_USE_TRANSFER, + RAS_GFX_V9__GFX_TCC_INDEX1_END = + RAS_GFX_V9__GFX_TCC_IN_USE_TRANSFER, + /* TCC range 2 */ + RAS_GFX_V9__GFX_TCC_INDEX2_START, + RAS_GFX_V9__GFX_TCC_RETURN_DATA = + RAS_GFX_V9__GFX_TCC_INDEX2_START, + RAS_GFX_V9__GFX_TCC_RETURN_CONTROL, + RAS_GFX_V9__GFX_TCC_UC_ATOMIC_FIFO, + RAS_GFX_V9__GFX_TCC_WRITE_RETURN, + RAS_GFX_V9__GFX_TCC_WRITE_CACHE_READ, + RAS_GFX_V9__GFX_TCC_SRC_FIFO, + RAS_GFX_V9__GFX_TCC_SRC_FIFO_NEXT_RAM, + RAS_GFX_V9__GFX_TCC_CACHE_TAG_PROBE_FIFO, + RAS_GFX_V9__GFX_TCC_INDEX2_END = + RAS_GFX_V9__GFX_TCC_CACHE_TAG_PROBE_FIFO, + /* TCC range 3 */ + RAS_GFX_V9__GFX_TCC_INDEX3_START, + RAS_GFX_V9__GFX_TCC_LATENCY_FIFO = + RAS_GFX_V9__GFX_TCC_INDEX3_START, + RAS_GFX_V9__GFX_TCC_LATENCY_FIFO_NEXT_RAM, + RAS_GFX_V9__GFX_TCC_INDEX3_END = + RAS_GFX_V9__GFX_TCC_LATENCY_FIFO_NEXT_RAM, + /* TCC range 4 */ + RAS_GFX_V9__GFX_TCC_INDEX4_START, + RAS_GFX_V9__GFX_TCC_WRRET_TAG_WRITE_RETURN = + RAS_GFX_V9__GFX_TCC_INDEX4_START, + RAS_GFX_V9__GFX_TCC_ATOMIC_RETURN_BUFFER, + RAS_GFX_V9__GFX_TCC_INDEX4_END = + RAS_GFX_V9__GFX_TCC_ATOMIC_RETURN_BUFFER, + RAS_GFX_V9__GFX_TCC_INDEX_END = + RAS_GFX_V9__GFX_TCC_INDEX4_END, + /* TCI */ + RAS_GFX_V9__GFX_TCI_WRITE_RAM, + /* TCP */ + RAS_GFX_V9__GFX_TCP_INDEX_START, + RAS_GFX_V9__GFX_TCP_CACHE_RAM = + RAS_GFX_V9__GFX_TCP_INDEX_START, + RAS_GFX_V9__GFX_TCP_LFIFO_RAM, + RAS_GFX_V9__GFX_TCP_CMD_FIFO, + RAS_GFX_V9__GFX_TCP_VM_FIFO, + RAS_GFX_V9__GFX_TCP_DB_RAM, + RAS_GFX_V9__GFX_TCP_UTCL1_LFIFO0, + RAS_GFX_V9__GFX_TCP_UTCL1_LFIFO1, + RAS_GFX_V9__GFX_TCP_INDEX_END = + RAS_GFX_V9__GFX_TCP_UTCL1_LFIFO1, + /* TD */ + RAS_GFX_V9__GFX_TD_INDEX_START, + RAS_GFX_V9__GFX_TD_SS_FIFO_LO = + RAS_GFX_V9__GFX_TD_INDEX_START, + RAS_GFX_V9__GFX_TD_SS_FIFO_HI, + RAS_GFX_V9__GFX_TD_CS_FIFO, + RAS_GFX_V9__GFX_TD_INDEX_END = RAS_GFX_V9__GFX_TD_CS_FIFO, + /* EA (3 sub-ranges) */ + RAS_GFX_V9__GFX_EA_INDEX_START, + /* EA range 0 */ + RAS_GFX_V9__GFX_EA_INDEX0_START = + RAS_GFX_V9__GFX_EA_INDEX_START, + RAS_GFX_V9__GFX_EA_DRAMRD_CMDMEM = + RAS_GFX_V9__GFX_EA_INDEX0_START, + RAS_GFX_V9__GFX_EA_DRAMWR_CMDMEM, + RAS_GFX_V9__GFX_EA_DRAMWR_DATAMEM, + RAS_GFX_V9__GFX_EA_RRET_TAGMEM, + RAS_GFX_V9__GFX_EA_WRET_TAGMEM, + RAS_GFX_V9__GFX_EA_GMIRD_CMDMEM, + RAS_GFX_V9__GFX_EA_GMIWR_CMDMEM, + RAS_GFX_V9__GFX_EA_GMIWR_DATAMEM, + RAS_GFX_V9__GFX_EA_INDEX0_END = + RAS_GFX_V9__GFX_EA_GMIWR_DATAMEM, + /* EA range 1 */ + RAS_GFX_V9__GFX_EA_INDEX1_START, + RAS_GFX_V9__GFX_EA_DRAMRD_PAGEMEM = + RAS_GFX_V9__GFX_EA_INDEX1_START, + RAS_GFX_V9__GFX_EA_DRAMWR_PAGEMEM, + RAS_GFX_V9__GFX_EA_IORD_CMDMEM, + RAS_GFX_V9__GFX_EA_IOWR_CMDMEM, + RAS_GFX_V9__GFX_EA_IOWR_DATAMEM, + RAS_GFX_V9__GFX_EA_GMIRD_PAGEMEM, + RAS_GFX_V9__GFX_EA_GMIWR_PAGEMEM, + RAS_GFX_V9__GFX_EA_INDEX1_END = + RAS_GFX_V9__GFX_EA_GMIWR_PAGEMEM, + /* EA range 2 */ + RAS_GFX_V9__GFX_EA_INDEX2_START, + RAS_GFX_V9__GFX_EA_MAM_D0MEM = + RAS_GFX_V9__GFX_EA_INDEX2_START, + RAS_GFX_V9__GFX_EA_MAM_D1MEM, + RAS_GFX_V9__GFX_EA_MAM_D2MEM, + RAS_GFX_V9__GFX_EA_MAM_D3MEM, + RAS_GFX_V9__GFX_EA_INDEX2_END = + RAS_GFX_V9__GFX_EA_MAM_D3MEM, + RAS_GFX_V9__GFX_EA_INDEX_END = + RAS_GFX_V9__GFX_EA_INDEX2_END, + /* UTC VM L2 bank */ + RAS_GFX_V9__UTC_VML2_BANK_CACHE, + /* UTC VM walker */ + RAS_GFX_V9__UTC_VML2_WALKER, + /* UTC ATC L2 2MB cache */ + RAS_GFX_V9__UTC_ATCL2_CACHE_2M_BANK, + /* UTC ATC L2 4KB cache */ + RAS_GFX_V9__UTC_ATCL2_CACHE_4K_BANK, + RAS_GFX_V9__GFX_MAX +}; + +extern const struct ras_gfx_ip_func gfx_ras_func_v9_0; + +#endif From 87609a497ac00f7d6fcbf571de06cb0477ad0373 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 17:28:14 +0800 Subject: [PATCH 2092/2653] drm/amd/ras: Add gfx common ras functions Add gfx common ras functions. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/ras/rascore/ras_gfx.c | 70 +++++++++++++++++++++++ drivers/gpu/drm/amd/ras/rascore/ras_gfx.h | 43 ++++++++++++++ 2 files changed, 113 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_gfx.c create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_gfx.h diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_gfx.c b/drivers/gpu/drm/amd/ras/rascore/ras_gfx.c new file mode 100644 index 0000000000000..f5ce28777705d --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_gfx.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "ras.h" +#include "ras_gfx_v9_0.h" +#include "ras_gfx.h" +#include "ras_core_status.h" + +static const struct ras_gfx_ip_func *ras_gfx_get_ip_funcs( + struct ras_core_context *ras_core, uint32_t ip_version) +{ + switch (ip_version) { + case IP_VERSION(9, 4, 3): + case IP_VERSION(9, 4, 4): + case IP_VERSION(9, 5, 0): + return &gfx_ras_func_v9_0; + default: + RAS_DEV_ERR(ras_core->dev, + "GFX ip version(0x%x) is not supported!\n", ip_version); + break; + } + + return NULL; +} + +int ras_gfx_get_ta_subblock(struct ras_core_context *ras_core, + uint32_t error_type, uint32_t subblock, uint32_t *ta_subblock) +{ + struct ras_gfx *gfx = &ras_core->ras_gfx; + + return gfx->ip_func->get_ta_subblock(ras_core, + error_type, subblock, ta_subblock); +} + +int ras_gfx_hw_init(struct ras_core_context *ras_core) +{ + struct ras_gfx *gfx = &ras_core->ras_gfx; + + gfx->gfx_ip_version = ras_core->config->gfx_ip_version; + + gfx->ip_func = ras_gfx_get_ip_funcs(ras_core, gfx->gfx_ip_version); + + return gfx->ip_func ? RAS_CORE_OK : -EINVAL; +} + +int ras_gfx_hw_fini(struct ras_core_context *ras_core) +{ + return 0; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_gfx.h b/drivers/gpu/drm/amd/ras/rascore/ras_gfx.h new file mode 100644 index 0000000000000..8a42d69fb0ad4 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_gfx.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __RAS_GFX_H__ +#define __RAS_GFX_H__ + +struct ras_gfx_ip_func { + int (*get_ta_subblock)(struct ras_core_context *ras_core, + uint32_t error_type, uint32_t subblock, uint32_t *ta_subblock); +}; + +struct ras_gfx { + uint32_t gfx_ip_version; + const struct ras_gfx_ip_func *ip_func; +}; + +int ras_gfx_hw_init(struct ras_core_context *ras_core); +int ras_gfx_hw_fini(struct ras_core_context *ras_core); + +int ras_gfx_get_ta_subblock(struct ras_core_context *ras_core, + uint32_t error_type, uint32_t subblock, uint32_t *ta_subblock); + +#endif From 89eecf774523bac2c57884500a022601a2a4d7fb Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 17:30:48 +0800 Subject: [PATCH 2093/2653] drm/amd/ras: Add eeprom ras functions Add eeprom ras functions. V5: Remove duplicate data structure definition. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c | 1368 ++++++++++++++++++ drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h | 197 +++ 2 files changed, 1565 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c new file mode 100644 index 0000000000000..9e0a4f605db06 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c @@ -0,0 +1,1368 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "ras_eeprom.h" +#include "ras.h" + +/* These are memory addresses as would be seen by one or more EEPROM + * chips strung on the I2C bus, usually by manipulating pins 1-3 of a + * set of EEPROM devices. They form a continuous memory space. + * + * The I2C device address includes the device type identifier, 1010b, + * which is a reserved value and indicates that this is an I2C EEPROM + * device. It also includes the top 3 bits of the 19 bit EEPROM memory + * address, namely bits 18, 17, and 16. This makes up the 7 bit + * address sent on the I2C bus with bit 0 being the direction bit, + * which is not represented here, and sent by the hardware directly. + * + * For instance, + * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. + * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. + * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. + * Depending on the size of the I2C EEPROM device(s), bits 18:16 may + * address memory in a device or a device on the I2C bus, depending on + * the status of pins 1-3. + * + * The RAS table lives either at address 0 or address 40000h of EEPROM. + */ +#define EEPROM_I2C_MADDR_0 0x0 +#define EEPROM_I2C_MADDR_4 0x40000 + +#define EEPROM_PAGE_BITS 8 +#define EEPROM_PAGE_SIZE (1U << EEPROM_PAGE_BITS) +#define EEPROM_PAGE_MASK (EEPROM_PAGE_SIZE - 1) + +#define EEPROM_OFFSET_SIZE 2 +#define MAKE_I2C_ADDR(_aa) ((0xA << 3) | (((_aa) >> 16) & 0xF)) + +/* + * The 2 macros bellow represent the actual size in bytes that + * those entities occupy in the EEPROM memory. + * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_umc_record) which + * uses uint64 to store 6b fields such as retired_page. + */ +#define RAS_TABLE_HEADER_SIZE 20 +#define RAS_TABLE_RECORD_SIZE 24 + +/* Table hdr is 'AMDR' */ +#define RAS_TABLE_HDR_VAL 0x414d4452 + +/* Bad GPU tag ‘BADG’ */ +#define RAS_TABLE_HDR_BAD 0x42414447 + +/* + * EEPROM Table structure v1 + * --------------------------------- + * | | + * | EEPROM TABLE HEADER | + * | ( size 20 Bytes ) | + * | | + * --------------------------------- + * | | + * | BAD PAGE RECORD AREA | + * | | + * --------------------------------- + */ + +/* Assume 2-Mbit size EEPROM and take up the whole space. */ +#define RAS_TBL_SIZE_BYTES (256 * 1024) +#define RAS_TABLE_START 0 +#define RAS_HDR_START RAS_TABLE_START +#define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE) +#define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \ + / RAS_TABLE_RECORD_SIZE) + +/* + * EEPROM Table structrue v2.1 + * --------------------------------- + * | | + * | EEPROM TABLE HEADER | + * | ( size 20 Bytes ) | + * | | + * --------------------------------- + * | | + * | EEPROM TABLE RAS INFO | + * | (available info size 4 Bytes) | + * | ( reserved size 252 Bytes ) | + * | | + * --------------------------------- + * | | + * | BAD PAGE RECORD AREA | + * | | + * --------------------------------- + */ + +/* EEPROM Table V2_1 */ +#define RAS_TABLE_V2_1_INFO_SIZE 256 +#define RAS_TABLE_V2_1_INFO_START RAS_TABLE_HEADER_SIZE +#define RAS_RECORD_START_V2_1 (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \ + RAS_TABLE_V2_1_INFO_SIZE) +#define RAS_MAX_RECORD_COUNT_V2_1 ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \ + RAS_TABLE_V2_1_INFO_SIZE) \ + / RAS_TABLE_RECORD_SIZE) + +/* Given a zero-based index of an EEPROM RAS record, yields the EEPROM + * offset off of RAS_TABLE_START. That is, this is something you can + * add to control->i2c_address, and then tell I2C layer to read + * from/write to there. _N is the so called absolute index, + * because it starts right after the table header. + */ +#define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \ + (_N) * RAS_TABLE_RECORD_SIZE) + +#define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \ + (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE) + +/* Given a 0-based relative record index, 0, 1, 2, ..., etc., off + * of "fri", return the absolute record index off of the end of + * the table header. + */ +#define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \ + (_C)->ras_max_record_count) + +#define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ + RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE) + +#define RAS_NUM_RECS_V2_1(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ + RAS_TABLE_HEADER_SIZE - \ + RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE) + +#define to_ras_core_context(x) (container_of(x, struct ras_core_context, ras_eeprom)) + +static bool __is_ras_eeprom_supported(struct ras_core_context *ras_core) +{ + return ras_core->ras_eeprom_supported; +} + +static bool __get_eeprom_i2c_addr(struct ras_core_context *ras_core, + struct ras_eeprom_control *control) +{ + int ret = -EINVAL; + + if (control->sys_func && + control->sys_func->update_eeprom_i2c_config) + ret = control->sys_func->update_eeprom_i2c_config(ras_core); + else + RAS_DEV_WARN(ras_core->dev, + "No eeprom i2c system config!\n"); + + return !ret ? true : false; +} + +static int __ras_eeprom_xfer(struct ras_core_context *ras_core, u32 eeprom_addr, + u8 *eeprom_buf, u32 buf_size, bool read) +{ + struct ras_eeprom_control *control = &ras_core->ras_eeprom; + int ret; + + if (control->sys_func && control->sys_func->eeprom_i2c_xfer) { + ret = control->sys_func->eeprom_i2c_xfer(ras_core, + eeprom_addr, eeprom_buf, buf_size, read); + + if ((ret > 0) && !read) { + /* According to EEPROM specs the length of the + * self-writing cycle, tWR (tW), is 10 ms. + * + * TODO: Use polling on ACK, aka Acknowledge + * Polling, to minimize waiting for the + * internal write cycle to complete, as it is + * usually smaller than tWR (tW). + */ + msleep(10); + } + + return ret; + } + + RAS_DEV_ERR(ras_core->dev, "Error: No eeprom i2c system xfer function!\n"); + return -EINVAL; +} + + +/** + * __eeprom_xfer -- Read/write from/to an I2C EEPROM device + * @i2c_adap: pointer to the I2C adapter to use + * @eeprom_addr: EEPROM address from which to read/write + * @eeprom_buf: pointer to data buffer to read into/write from + * @buf_size: the size of @eeprom_buf + * @read: True if reading from the EEPROM, false if writing + * + * Returns the number of bytes read/written; -errno on error. + */ +static int __eeprom_xfer(struct ras_core_context *ras_core, u32 eeprom_addr, + u8 *eeprom_buf, u32 buf_size, bool read) +{ + u16 limit; + u16 ps; /* Partial size */ + int res = 0, r; + + if (read) + limit = ras_core->ras_eeprom.max_read_len; + else + limit = ras_core->ras_eeprom.max_write_len; + + if (limit && (limit <= EEPROM_OFFSET_SIZE)) { + RAS_DEV_ERR(ras_core->dev, + "maddr:0x%04X size:0x%02X:quirk max_%s_len must be > %d", + eeprom_addr, buf_size, + read ? "read" : "write", EEPROM_OFFSET_SIZE); + return -EINVAL; + } + + ras_core_down_gpu_reset_lock(ras_core); + + if (limit == 0) { + res = __ras_eeprom_xfer(ras_core, eeprom_addr, + eeprom_buf, buf_size, read); + } else { + /* The "limit" includes all data bytes sent/received, + * which would include the EEPROM_OFFSET_SIZE bytes. + * Account for them here. + */ + limit -= EEPROM_OFFSET_SIZE; + for ( ; buf_size > 0; + buf_size -= ps, eeprom_addr += ps, eeprom_buf += ps) { + ps = (buf_size < limit) ? buf_size : limit; + + r = __ras_eeprom_xfer(ras_core, eeprom_addr, + eeprom_buf, ps, read); + if (r < 0) + break; + + res += r; + } + } + + ras_core_up_gpu_reset_lock(ras_core); + + return res; +} + +static int __eeprom_read(struct ras_core_context *ras_core, + u32 eeprom_addr, u8 *eeprom_buf, u32 bytes) +{ + return __eeprom_xfer(ras_core, eeprom_addr, + eeprom_buf, bytes, true); +} + +static int __eeprom_write(struct ras_core_context *ras_core, + u32 eeprom_addr, u8 *eeprom_buf, u32 bytes) +{ + return __eeprom_xfer(ras_core, eeprom_addr, + eeprom_buf, bytes, false); +} + +static void +__encode_table_header_to_buf(struct ras_eeprom_table_header *hdr, + unsigned char *buf) +{ + u32 *pp = (uint32_t *)buf; + + pp[0] = cpu_to_le32(hdr->header); + pp[1] = cpu_to_le32(hdr->version); + pp[2] = cpu_to_le32(hdr->first_rec_offset); + pp[3] = cpu_to_le32(hdr->tbl_size); + pp[4] = cpu_to_le32(hdr->checksum); +} + +static void +__decode_table_header_from_buf(struct ras_eeprom_table_header *hdr, + unsigned char *buf) +{ + u32 *pp = (uint32_t *)buf; + + hdr->header = le32_to_cpu(pp[0]); + hdr->version = le32_to_cpu(pp[1]); + hdr->first_rec_offset = le32_to_cpu(pp[2]); + hdr->tbl_size = le32_to_cpu(pp[3]); + hdr->checksum = le32_to_cpu(pp[4]); +} + +static int __write_table_header(struct ras_eeprom_control *control) +{ + u8 buf[RAS_TABLE_HEADER_SIZE]; + struct ras_core_context *ras_core = to_ras_core_context(control); + int res; + + memset(buf, 0, sizeof(buf)); + __encode_table_header_to_buf(&control->tbl_hdr, buf); + + /* i2c may be unstable in gpu reset */ + res = __eeprom_write(ras_core, + control->i2c_address + + control->ras_header_offset, + buf, RAS_TABLE_HEADER_SIZE); + + if (res < 0) { + RAS_DEV_ERR(ras_core->dev, + "Failed to write EEPROM table header:%d\n", res); + } else if (res < RAS_TABLE_HEADER_SIZE) { + RAS_DEV_ERR(ras_core->dev, + "Short write:%d out of %d\n", res, RAS_TABLE_HEADER_SIZE); + res = -EIO; + } else { + res = 0; + } + + return res; +} + +static void +__encode_table_ras_info_to_buf(struct ras_eeprom_table_ras_info *rai, + unsigned char *buf) +{ + u32 *pp = (uint32_t *)buf; + u32 tmp; + + tmp = ((uint32_t)(rai->rma_status) & 0xFF) | + (((uint32_t)(rai->health_percent) << 8) & 0xFF00) | + (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000); + pp[0] = cpu_to_le32(tmp); +} + +static void +__decode_table_ras_info_from_buf(struct ras_eeprom_table_ras_info *rai, + unsigned char *buf) +{ + u32 *pp = (uint32_t *)buf; + u32 tmp; + + tmp = le32_to_cpu(pp[0]); + rai->rma_status = tmp & 0xFF; + rai->health_percent = (tmp >> 8) & 0xFF; + rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF; +} + +static int __write_table_ras_info(struct ras_eeprom_control *control) +{ + struct ras_core_context *ras_core = to_ras_core_context(control); + u8 *buf; + int res; + + buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); + if (!buf) { + RAS_DEV_ERR(ras_core->dev, + "Failed to alloc buf to write table ras info\n"); + return -ENOMEM; + } + + __encode_table_ras_info_to_buf(&control->tbl_rai, buf); + + /* i2c may be unstable in gpu reset */ + res = __eeprom_write(ras_core, + control->i2c_address + + control->ras_info_offset, + buf, RAS_TABLE_V2_1_INFO_SIZE); + + if (res < 0) { + RAS_DEV_ERR(ras_core->dev, + "Failed to write EEPROM table ras info:%d\n", res); + } else if (res < RAS_TABLE_V2_1_INFO_SIZE) { + RAS_DEV_ERR(ras_core->dev, + "Short write:%d out of %d\n", res, RAS_TABLE_V2_1_INFO_SIZE); + res = -EIO; + } else { + res = 0; + } + + kfree(buf); + + return res; +} + +static u8 __calc_hdr_byte_sum(const struct ras_eeprom_control *control) +{ + int ii; + u8 *pp, csum; + u32 sz; + + /* Header checksum, skip checksum field in the calculation */ + sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); + pp = (u8 *) &control->tbl_hdr; + csum = 0; + for (ii = 0; ii < sz; ii++, pp++) + csum += *pp; + + return csum; +} + +static u8 __calc_ras_info_byte_sum(const struct ras_eeprom_control *control) +{ + int ii; + u8 *pp, csum; + u32 sz; + + sz = sizeof(control->tbl_rai); + pp = (u8 *) &control->tbl_rai; + csum = 0; + for (ii = 0; ii < sz; ii++, pp++) + csum += *pp; + + return csum; +} + +static int ras_eeprom_correct_header_tag( + struct ras_eeprom_control *control, + uint32_t header) +{ + struct ras_eeprom_table_header *hdr = &control->tbl_hdr; + u8 *hh; + int res; + u8 csum; + + csum = -hdr->checksum; + + hh = (void *) &hdr->header; + csum -= (hh[0] + hh[1] + hh[2] + hh[3]); + hh = (void *) &header; + csum += hh[0] + hh[1] + hh[2] + hh[3]; + csum = -csum; + mutex_lock(&control->ras_tbl_mutex); + hdr->header = header; + hdr->checksum = csum; + res = __write_table_header(control); + mutex_unlock(&control->ras_tbl_mutex); + + return res; +} + +static void ras_set_eeprom_table_version(struct ras_eeprom_control *control) +{ + struct ras_eeprom_table_header *hdr = &control->tbl_hdr; + + hdr->version = RAS_TABLE_VER_V3; +} + +/** + * ras_eeprom_reset_table -- Reset the RAS EEPROM table + * @control: pointer to control structure + * + * Reset the contents of the header of the RAS EEPROM table. + * Return 0 on success, -errno on error. + */ +int ras_eeprom_reset_table(struct ras_core_context *ras_core) +{ + struct ras_eeprom_control *control = &ras_core->ras_eeprom; + struct ras_eeprom_table_header *hdr = &control->tbl_hdr; + struct ras_eeprom_table_ras_info *rai = &control->tbl_rai; + u8 csum; + int res; + + mutex_lock(&control->ras_tbl_mutex); + + hdr->header = RAS_TABLE_HDR_VAL; + ras_set_eeprom_table_version(control); + + if (hdr->version >= RAS_TABLE_VER_V2_1) { + hdr->first_rec_offset = RAS_RECORD_START_V2_1; + hdr->tbl_size = RAS_TABLE_HEADER_SIZE + + RAS_TABLE_V2_1_INFO_SIZE; + rai->rma_status = RAS_GPU_HEALTH_USABLE; + /** + * GPU health represented as a percentage. + * 0 means worst health, 100 means fully health. + */ + rai->health_percent = 100; + /* ecc_page_threshold = 0 means disable bad page retirement */ + rai->ecc_page_threshold = control->record_threshold_count; + } else { + hdr->first_rec_offset = RAS_RECORD_START; + hdr->tbl_size = RAS_TABLE_HEADER_SIZE; + } + + csum = __calc_hdr_byte_sum(control); + if (hdr->version >= RAS_TABLE_VER_V2_1) + csum += __calc_ras_info_byte_sum(control); + csum = -csum; + hdr->checksum = csum; + res = __write_table_header(control); + if (!res && hdr->version > RAS_TABLE_VER_V1) + res = __write_table_ras_info(control); + + control->ras_num_recs = 0; + control->ras_fri = 0; + + control->bad_channel_bitmap = 0; + ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM, + &control->ras_num_recs); + ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP, + &control->bad_channel_bitmap); + control->update_channel_flag = false; + + mutex_unlock(&control->ras_tbl_mutex); + + return res; +} + +static void +__encode_table_record_to_buf(struct ras_eeprom_control *control, + struct eeprom_umc_record *record, + unsigned char *buf) +{ + __le64 tmp = 0; + int i = 0; + + /* Next are all record fields according to EEPROM page spec in LE foramt */ + buf[i++] = record->err_type; + + buf[i++] = record->bank; + + tmp = cpu_to_le64(record->ts); + memcpy(buf + i, &tmp, 8); + i += 8; + + tmp = cpu_to_le64((record->offset & 0xffffffffffff)); + memcpy(buf + i, &tmp, 6); + i += 6; + + buf[i++] = record->mem_channel; + buf[i++] = record->mcumc_id; + + tmp = cpu_to_le64((record->retired_row_pfn & 0xffffffffffff)); + memcpy(buf + i, &tmp, 6); +} + +static void +__decode_table_record_from_buf(struct ras_eeprom_control *control, + struct eeprom_umc_record *record, + unsigned char *buf) +{ + __le64 tmp = 0; + int i = 0; + + /* Next are all record fields according to EEPROM page spec in LE foramt */ + record->err_type = buf[i++]; + + record->bank = buf[i++]; + + memcpy(&tmp, buf + i, 8); + record->ts = le64_to_cpu(tmp); + i += 8; + + memcpy(&tmp, buf + i, 6); + record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); + i += 6; + + record->mem_channel = buf[i++]; + record->mcumc_id = buf[i++]; + + memcpy(&tmp, buf + i, 6); + record->retired_row_pfn = (le64_to_cpu(tmp) & 0xffffffffffff); +} + +bool ras_eeprom_check_safety_watermark(struct ras_core_context *ras_core) +{ + struct ras_eeprom_control *control = &ras_core->ras_eeprom; + bool ret = false; + int bad_page_count; + + if (!__is_ras_eeprom_supported(ras_core) || + !control->record_threshold_config) + return false; + + bad_page_count = ras_umc_get_badpage_count(ras_core); + if (control->tbl_hdr.header == RAS_TABLE_HDR_BAD) { + if (bad_page_count > control->record_threshold_count) + RAS_DEV_WARN(ras_core->dev, "RAS records:%d exceed threshold:%d", + bad_page_count, control->record_threshold_count); + + if ((control->record_threshold_config == WARN_NONSTOP_OVER_THRESHOLD) || + (control->record_threshold_config == NONSTOP_OVER_THRESHOLD)) { + RAS_DEV_WARN(ras_core->dev, + "Please consult AMD Service Action Guide (SAG) for appropriate service procedures.\n"); + ret = false; + } else { + ras_core->is_rma = true; + RAS_DEV_WARN(ras_core->dev, + "Please consider adjusting the customized threshold.\n"); + ret = true; + } + } + + return ret; +} + +/** + * __ras_eeprom_write -- write indexed from buffer to EEPROM + * @control: pointer to control structure + * @buf: pointer to buffer containing data to write + * @fri: start writing at this index + * @num: number of records to write + * + * The caller must hold the table mutex in @control. + * Return 0 on success, -errno otherwise. + */ +static int __ras_eeprom_write(struct ras_eeprom_control *control, + u8 *buf, const u32 fri, const u32 num) +{ + struct ras_core_context *ras_core = to_ras_core_context(control); + u32 buf_size; + int res; + + /* i2c may be unstable in gpu reset */ + buf_size = num * RAS_TABLE_RECORD_SIZE; + res = __eeprom_write(ras_core, + control->i2c_address + RAS_INDEX_TO_OFFSET(control, fri), + buf, buf_size); + if (res < 0) { + RAS_DEV_ERR(ras_core->dev, + "Writing %d EEPROM table records error:%d\n", num, res); + } else if (res < buf_size) { + /* Short write, return error.*/ + RAS_DEV_ERR(ras_core->dev, + "Wrote %d records out of %d\n", + (res/RAS_TABLE_RECORD_SIZE), num); + res = -EIO; + } else { + res = 0; + } + + return res; +} + +static int ras_eeprom_append_table(struct ras_eeprom_control *control, + struct eeprom_umc_record *record, + const u32 num) +{ + u32 a, b, i; + u8 *buf, *pp; + int res; + + buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + /* Encode all of them in one go. + */ + pp = buf; + for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { + __encode_table_record_to_buf(control, &record[i], pp); + + /* update bad channel bitmap */ + if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && + !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { + control->bad_channel_bitmap |= 1 << record[i].mem_channel; + control->update_channel_flag = true; + } + } + + /* a, first record index to write into. + * b, last record index to write into. + * a = first index to read (fri) + number of records in the table, + * b = a + @num - 1. + * Let N = control->ras_max_num_record_count, then we have, + * case 0: 0 <= a <= b < N, + * just append @num records starting at a; + * case 1: 0 <= a < N <= b, + * append (N - a) records starting at a, and + * append the remainder, b % N + 1, starting at 0. + * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases, + * case 2a: 0 <= a <= b < N + * append num records starting at a; and fix fri if b overwrote it, + * and since a <= b, if b overwrote it then a must've also, + * and if b didn't overwrite it, then a didn't also. + * case 2b: 0 <= b < a < N + * write num records starting at a, which wraps around 0=N + * and overwrite fri unconditionally. Now from case 2a, + * this means that b eclipsed fri to overwrite it and wrap + * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally + * set fri = b + 1 (mod N). + * Now, since fri is updated in every case, except the trivial case 0, + * the number of records present in the table after writing, is, + * num_recs - 1 = b - fri (mod N), and we take the positive value, + * by adding an arbitrary multiple of N before taking the modulo N + * as shown below. + */ + a = control->ras_fri + control->ras_num_recs; + b = a + num - 1; + if (b < control->ras_max_record_count) { + res = __ras_eeprom_write(control, buf, a, num); + } else if (a < control->ras_max_record_count) { + u32 g0, g1; + + g0 = control->ras_max_record_count - a; + g1 = b % control->ras_max_record_count + 1; + res = __ras_eeprom_write(control, buf, a, g0); + if (res) + goto Out; + res = __ras_eeprom_write(control, + buf + g0 * RAS_TABLE_RECORD_SIZE, + 0, g1); + if (res) + goto Out; + if (g1 > control->ras_fri) + control->ras_fri = g1 % control->ras_max_record_count; + } else { + a %= control->ras_max_record_count; + b %= control->ras_max_record_count; + + if (a <= b) { + /* Note that, b - a + 1 = num. */ + res = __ras_eeprom_write(control, buf, a, num); + if (res) + goto Out; + if (b >= control->ras_fri) + control->ras_fri = (b + 1) % control->ras_max_record_count; + } else { + u32 g0, g1; + + /* b < a, which means, we write from + * a to the end of the table, and from + * the start of the table to b. + */ + g0 = control->ras_max_record_count - a; + g1 = b + 1; + res = __ras_eeprom_write(control, buf, a, g0); + if (res) + goto Out; + res = __ras_eeprom_write(control, + buf + g0 * RAS_TABLE_RECORD_SIZE, 0, g1); + if (res) + goto Out; + control->ras_fri = g1 % control->ras_max_record_count; + } + } + control->ras_num_recs = 1 + + (control->ras_max_record_count + b - control->ras_fri) + % control->ras_max_record_count; +Out: + kfree(buf); + return res; +} + +static int ras_eeprom_update_header(struct ras_eeprom_control *control) +{ + struct ras_core_context *ras_core = to_ras_core_context(control); + int threshold_config = control->record_threshold_config; + u8 *buf, *pp, csum; + u32 buf_size; + int bad_page_count; + int res; + + bad_page_count = ras_umc_get_badpage_count(ras_core); + /* Modify the header if it exceeds. + */ + if (threshold_config != 0 && + bad_page_count > control->record_threshold_count) { + RAS_DEV_WARN(ras_core->dev, + "Saved bad pages %d reaches threshold value %d\n", + bad_page_count, control->record_threshold_count); + control->tbl_hdr.header = RAS_TABLE_HDR_BAD; + if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) { + control->tbl_rai.rma_status = RAS_GPU_RETIRED__ECC_REACH_THRESHOLD; + control->tbl_rai.health_percent = 0; + } + + if ((threshold_config != WARN_NONSTOP_OVER_THRESHOLD) && + (threshold_config != NONSTOP_OVER_THRESHOLD)) + ras_core->is_rma = true; + + /* ignore the -ENOTSUPP return value */ + ras_core_event_notify(ras_core, RAS_EVENT_ID__DEVICE_RMA, NULL); + } + + if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) + control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + + RAS_TABLE_V2_1_INFO_SIZE + + control->ras_num_recs * RAS_TABLE_RECORD_SIZE; + else + control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + + control->ras_num_recs * RAS_TABLE_RECORD_SIZE; + control->tbl_hdr.checksum = 0; + + buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; + buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); + if (!buf) { + RAS_DEV_ERR(ras_core->dev, + "allocating memory for table of size %d bytes failed\n", + control->tbl_hdr.tbl_size); + res = -ENOMEM; + goto Out; + } + + res = __eeprom_read(ras_core, + control->i2c_address + + control->ras_record_offset, + buf, buf_size); + if (res < 0) { + RAS_DEV_ERR(ras_core->dev, + "EEPROM failed reading records:%d\n", res); + goto Out; + } else if (res < buf_size) { + RAS_DEV_ERR(ras_core->dev, + "EEPROM read %d out of %d bytes\n", res, buf_size); + res = -EIO; + goto Out; + } + + /** + * bad page records have been stored in eeprom, + * now calculate gpu health percent + */ + if (threshold_config != 0 && + control->tbl_hdr.version >= RAS_TABLE_VER_V2_1 && + bad_page_count <= control->record_threshold_count) + control->tbl_rai.health_percent = ((control->record_threshold_count - + bad_page_count) * 100) / control->record_threshold_count; + + /* Recalc the checksum. + */ + csum = 0; + for (pp = buf; pp < buf + buf_size; pp++) + csum += *pp; + + csum += __calc_hdr_byte_sum(control); + if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) + csum += __calc_ras_info_byte_sum(control); + /* avoid sign extension when assigning to "checksum" */ + csum = -csum; + control->tbl_hdr.checksum = csum; + res = __write_table_header(control); + if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) + res = __write_table_ras_info(control); +Out: + kfree(buf); + return res; +} + +/** + * ras_core_eeprom_append -- append records to the EEPROM RAS table + * @control: pointer to control structure + * @record: array of records to append + * @num: number of records in @record array + * + * Append @num records to the table, calculate the checksum and write + * the table back to EEPROM. The maximum number of records that + * can be appended is between 1 and control->ras_max_record_count, + * regardless of how many records are already stored in the table. + * + * Return 0 on success or if EEPROM is not supported, -errno on error. + */ +int ras_eeprom_append(struct ras_core_context *ras_core, + struct eeprom_umc_record *record, const u32 num) +{ + struct ras_eeprom_control *control = &ras_core->ras_eeprom; + int res; + + if (!__is_ras_eeprom_supported(ras_core)) + return 0; + + if (num == 0) { + RAS_DEV_ERR(ras_core->dev, "will not append 0 records\n"); + return -EINVAL; + } else if ((num + control->ras_num_recs) > control->ras_max_record_count) { + RAS_DEV_ERR(ras_core->dev, + "cannot append %d records than the size of table %d\n", + num, control->ras_max_record_count); + return -EINVAL; + } + + mutex_lock(&control->ras_tbl_mutex); + res = ras_eeprom_append_table(control, record, num); + if (!res) + res = ras_eeprom_update_header(control); + + mutex_unlock(&control->ras_tbl_mutex); + + return res; +} + +/** + * __ras_eeprom_read -- read indexed from EEPROM into buffer + * @control: pointer to control structure + * @buf: pointer to buffer to read into + * @fri: first record index, start reading at this index, absolute index + * @num: number of records to read + * + * The caller must hold the table mutex in @control. + * Return 0 on success, -errno otherwise. + */ +static int __ras_eeprom_read(struct ras_eeprom_control *control, + u8 *buf, const u32 fri, const u32 num) +{ + struct ras_core_context *ras_core = to_ras_core_context(control); + u32 buf_size; + int res; + + /* i2c may be unstable in gpu reset */ + buf_size = num * RAS_TABLE_RECORD_SIZE; + res = __eeprom_read(ras_core, + control->i2c_address + + RAS_INDEX_TO_OFFSET(control, fri), + buf, buf_size); + if (res < 0) { + RAS_DEV_ERR(ras_core->dev, + "Reading %d EEPROM table records error:%d\n", num, res); + } else if (res < buf_size) { + /* Short read, return error. + */ + RAS_DEV_ERR(ras_core->dev, + "Read %d records out of %d\n", + (res/RAS_TABLE_RECORD_SIZE), num); + res = -EIO; + } else { + res = 0; + } + + return res; +} + +/** + * ras_eeprom_read -- read EEPROM + * @control: pointer to control structure + * @record: array of records to read into + * @num: number of records in @record + * + * Reads num records from the RAS table in EEPROM and + * writes the data into @record array. + * + * Returns 0 on success, -errno on error. + */ +int ras_eeprom_read(struct ras_core_context *ras_core, + struct eeprom_umc_record *record, const u32 num) +{ + struct ras_eeprom_control *control = &ras_core->ras_eeprom; + int i, res; + u8 *buf, *pp; + u32 g0, g1; + + if (!__is_ras_eeprom_supported(ras_core)) + return 0; + + if (num == 0) { + RAS_DEV_ERR(ras_core->dev, "will not read 0 records\n"); + return -EINVAL; + } else if (num > control->ras_num_recs) { + RAS_DEV_ERR(ras_core->dev, + "too many records to read:%d available:%d\n", + num, control->ras_num_recs); + return -EINVAL; + } + + buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + /* Determine how many records to read, from the first record + * index, fri, to the end of the table, and from the beginning + * of the table, such that the total number of records is + * @num, and we handle wrap around when fri > 0 and + * fri + num > RAS_MAX_RECORD_COUNT. + * + * First we compute the index of the last element + * which would be fetched from each region, + * g0 is in [fri, fri + num - 1], and + * g1 is in [0, RAS_MAX_RECORD_COUNT - 1]. + * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of + * the last element to fetch, we set g0 to _the number_ + * of elements to fetch, @num, since we know that the last + * indexed to be fetched does not exceed the table. + * + * If, however, g0 >= RAS_MAX_RECORD_COUNT, then + * we set g0 to the number of elements to read + * until the end of the table, and g1 to the number of + * elements to read from the beginning of the table. + */ + g0 = control->ras_fri + num - 1; + g1 = g0 % control->ras_max_record_count; + if (g0 < control->ras_max_record_count) { + g0 = num; + g1 = 0; + } else { + g0 = control->ras_max_record_count - control->ras_fri; + g1 += 1; + } + + mutex_lock(&control->ras_tbl_mutex); + res = __ras_eeprom_read(control, buf, control->ras_fri, g0); + if (res) + goto Out; + if (g1) { + res = __ras_eeprom_read(control, + buf + g0 * RAS_TABLE_RECORD_SIZE, 0, g1); + if (res) + goto Out; + } + + res = 0; + + /* Read up everything? Then transform. + */ + pp = buf; + for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { + __decode_table_record_from_buf(control, &record[i], pp); + + /* update bad channel bitmap */ + if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && + !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { + control->bad_channel_bitmap |= 1 << record[i].mem_channel; + control->update_channel_flag = true; + } + } +Out: + kfree(buf); + mutex_unlock(&control->ras_tbl_mutex); + + return res; +} + +uint32_t ras_eeprom_max_record_count(struct ras_core_context *ras_core) +{ + struct ras_eeprom_control *control = &ras_core->ras_eeprom; + + /* get available eeprom table version first before eeprom table init */ + ras_set_eeprom_table_version(control); + + if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) + return RAS_MAX_RECORD_COUNT_V2_1; + else + return RAS_MAX_RECORD_COUNT; +} + +/** + * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum + * @control: pointer to control structure + * + * Check the checksum of the stored in EEPROM RAS table. + * + * Return 0 if the checksum is correct, + * positive if it is not correct, and + * -errno on I/O error. + */ +static int __verify_ras_table_checksum(struct ras_eeprom_control *control) +{ + struct ras_core_context *ras_core = to_ras_core_context(control); + int buf_size, res; + u8 csum, *buf, *pp; + + if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) + buf_size = RAS_TABLE_HEADER_SIZE + + RAS_TABLE_V2_1_INFO_SIZE + + control->ras_num_recs * RAS_TABLE_RECORD_SIZE; + else + buf_size = RAS_TABLE_HEADER_SIZE + + control->ras_num_recs * RAS_TABLE_RECORD_SIZE; + + buf = kzalloc(buf_size, GFP_KERNEL); + if (!buf) { + RAS_DEV_ERR(ras_core->dev, + "Out of memory checking RAS table checksum.\n"); + return -ENOMEM; + } + + res = __eeprom_read(ras_core, + control->i2c_address + + control->ras_header_offset, + buf, buf_size); + if (res < buf_size) { + RAS_DEV_ERR(ras_core->dev, + "Partial read for checksum, res:%d\n", res); + /* On partial reads, return -EIO. + */ + if (res >= 0) + res = -EIO; + goto Out; + } + + csum = 0; + for (pp = buf; pp < buf + buf_size; pp++) + csum += *pp; +Out: + kfree(buf); + return res < 0 ? res : csum; +} + +static int __read_table_ras_info(struct ras_eeprom_control *control) +{ + struct ras_eeprom_table_ras_info *rai = &control->tbl_rai; + struct ras_core_context *ras_core = to_ras_core_context(control); + unsigned char *buf; + int res; + + buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL); + if (!buf) { + RAS_DEV_ERR(ras_core->dev, + "Failed to alloc buf to read EEPROM table ras info\n"); + return -ENOMEM; + } + + /** + * EEPROM table V2_1 supports ras info, + * read EEPROM table ras info + */ + res = __eeprom_read(ras_core, + control->i2c_address + control->ras_info_offset, + buf, RAS_TABLE_V2_1_INFO_SIZE); + if (res < RAS_TABLE_V2_1_INFO_SIZE) { + RAS_DEV_ERR(ras_core->dev, + "Failed to read EEPROM table ras info, res:%d\n", res); + res = res >= 0 ? -EIO : res; + goto Out; + } + + __decode_table_ras_info_from_buf(rai, buf); + +Out: + kfree(buf); + return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res; +} + +static int __check_ras_table_status(struct ras_core_context *ras_core) +{ + struct ras_eeprom_control *control = &ras_core->ras_eeprom; + unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; + struct ras_eeprom_table_header *hdr; + int res; + + hdr = &control->tbl_hdr; + + if (!__is_ras_eeprom_supported(ras_core)) + return 0; + + if (!__get_eeprom_i2c_addr(ras_core, control)) + return -EINVAL; + + control->ras_header_offset = RAS_HDR_START; + control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; + mutex_init(&control->ras_tbl_mutex); + + /* Read the table header from EEPROM address */ + res = __eeprom_read(ras_core, + control->i2c_address + control->ras_header_offset, + buf, RAS_TABLE_HEADER_SIZE); + if (res < RAS_TABLE_HEADER_SIZE) { + RAS_DEV_ERR(ras_core->dev, + "Failed to read EEPROM table header, res:%d\n", res); + return res >= 0 ? -EIO : res; + } + + __decode_table_header_from_buf(hdr, buf); + + if (hdr->header != RAS_TABLE_HDR_VAL && + hdr->header != RAS_TABLE_HDR_BAD) { + RAS_DEV_INFO(ras_core->dev, "Creating a new EEPROM table"); + return ras_eeprom_reset_table(ras_core); + } + + switch (hdr->version) { + case RAS_TABLE_VER_V2_1: + case RAS_TABLE_VER_V3: + control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); + control->ras_record_offset = RAS_RECORD_START_V2_1; + control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; + break; + case RAS_TABLE_VER_V1: + control->ras_num_recs = RAS_NUM_RECS(hdr); + control->ras_record_offset = RAS_RECORD_START; + control->ras_max_record_count = RAS_MAX_RECORD_COUNT; + break; + default: + RAS_DEV_ERR(ras_core->dev, + "RAS header invalid, unsupported version: %u", + hdr->version); + return -EINVAL; + } + + if (control->ras_num_recs > control->ras_max_record_count) { + RAS_DEV_ERR(ras_core->dev, + "RAS header invalid, records in header: %u max allowed :%u", + control->ras_num_recs, control->ras_max_record_count); + return -EINVAL; + } + + control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); + + return 0; +} + +int ras_eeprom_check_storage_status(struct ras_core_context *ras_core) +{ + struct ras_eeprom_control *control = &ras_core->ras_eeprom; + struct ras_eeprom_table_header *hdr; + int bad_page_count; + int res = 0; + + if (!__is_ras_eeprom_supported(ras_core)) + return 0; + + if (!__get_eeprom_i2c_addr(ras_core, control)) + return -EINVAL; + + hdr = &control->tbl_hdr; + + bad_page_count = ras_umc_get_badpage_count(ras_core); + if (hdr->header == RAS_TABLE_HDR_VAL) { + RAS_DEV_INFO(ras_core->dev, + "Found existing EEPROM table with %d records\n", + bad_page_count); + + if (hdr->version >= RAS_TABLE_VER_V2_1) { + res = __read_table_ras_info(control); + if (res) + return res; + } + + res = __verify_ras_table_checksum(control); + if (res) + RAS_DEV_ERR(ras_core->dev, + "RAS table incorrect checksum or error:%d\n", res); + + /* Warn if we are at 90% of the threshold or above + */ + if (10 * bad_page_count >= 9 * control->record_threshold_count) + RAS_DEV_WARN(ras_core->dev, + "RAS records:%u exceeds 90%% of threshold:%d\n", + bad_page_count, + control->record_threshold_count); + + } else if (hdr->header == RAS_TABLE_HDR_BAD && + control->record_threshold_config != 0) { + if (hdr->version >= RAS_TABLE_VER_V2_1) { + res = __read_table_ras_info(control); + if (res) + return res; + } + + res = __verify_ras_table_checksum(control); + if (res) + RAS_DEV_ERR(ras_core->dev, + "RAS Table incorrect checksum or error:%d\n", res); + + if (control->record_threshold_count >= bad_page_count) { + /* This means that, the threshold was increased since + * the last time the system was booted, and now, + * ras->record_threshold_count - control->num_recs > 0, + * so that at least one more record can be saved, + * before the page count threshold is reached. + */ + RAS_DEV_INFO(ras_core->dev, + "records:%d threshold:%d, resetting RAS table header signature", + bad_page_count, + control->record_threshold_count); + res = ras_eeprom_correct_header_tag(control, RAS_TABLE_HDR_VAL); + } else { + RAS_DEV_ERR(ras_core->dev, "RAS records:%d exceed threshold:%d", + bad_page_count, control->record_threshold_count); + if ((control->record_threshold_config == WARN_NONSTOP_OVER_THRESHOLD) || + (control->record_threshold_config == NONSTOP_OVER_THRESHOLD)) { + RAS_DEV_WARN(ras_core->dev, + "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n"); + res = 0; + } else { + ras_core->is_rma = true; + RAS_DEV_ERR(ras_core->dev, + "User defined threshold is set, runtime service will be halt when threshold is reached\n"); + } + } + } + + return res < 0 ? res : 0; +} + +int ras_eeprom_hw_init(struct ras_core_context *ras_core) +{ + struct ras_eeprom_control *control; + struct ras_eeprom_config *eeprom_cfg; + + if (!ras_core) + return -EINVAL; + + ras_core->is_rma = false; + + control = &ras_core->ras_eeprom; + + memset(control, 0, sizeof(*control)); + + eeprom_cfg = &ras_core->config->eeprom_cfg; + control->record_threshold_config = + eeprom_cfg->eeprom_record_threshold_config; + + control->record_threshold_count = ras_eeprom_max_record_count(ras_core); + if (eeprom_cfg->eeprom_record_threshold_count < + control->record_threshold_count) + control->record_threshold_count = + eeprom_cfg->eeprom_record_threshold_count; + + control->sys_func = eeprom_cfg->eeprom_sys_fn; + control->max_read_len = eeprom_cfg->max_i2c_read_len; + control->max_write_len = eeprom_cfg->max_i2c_write_len; + control->i2c_adapter = eeprom_cfg->eeprom_i2c_adapter; + control->i2c_port = eeprom_cfg->eeprom_i2c_port; + control->i2c_address = eeprom_cfg->eeprom_i2c_addr; + + control->update_channel_flag = false; + + return __check_ras_table_status(ras_core); +} + +int ras_eeprom_hw_fini(struct ras_core_context *ras_core) +{ + struct ras_eeprom_control *control; + + if (!ras_core) + return -EINVAL; + + control = &ras_core->ras_eeprom; + mutex_destroy(&control->ras_tbl_mutex); + + return 0; +} + +uint32_t ras_eeprom_get_record_count(struct ras_core_context *ras_core) +{ + if (!ras_core) + return 0; + + return ras_core->ras_eeprom.ras_num_recs; +} + +void ras_eeprom_sync_info(struct ras_core_context *ras_core) +{ + struct ras_eeprom_control *control; + + if (!ras_core) + return; + + control = &ras_core->ras_eeprom; + ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM, + &control->ras_num_recs); + ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP, + &control->bad_channel_bitmap); +} + +enum ras_gpu_health_status + ras_eeprom_check_gpu_status(struct ras_core_context *ras_core) +{ + struct ras_eeprom_control *control = &ras_core->ras_eeprom; + struct ras_eeprom_table_ras_info *rai = &control->tbl_rai; + + if (!__is_ras_eeprom_supported(ras_core) || + !control->record_threshold_config) + return RAS_GPU_HEALTH_NONE; + + if (control->tbl_hdr.header == RAS_TABLE_HDR_BAD) + return RAS_GPU_IN_BAD_STATUS; + + return rai->rma_status; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h new file mode 100644 index 0000000000000..2abe566c18b67 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __RAS_EEPROM_H__ +#define __RAS_EEPROM_H__ +#include "ras_sys.h" + +#define RAS_TABLE_VER_V1 0x00010000 +#define RAS_TABLE_VER_V2_1 0x00021000 +#define RAS_TABLE_VER_V3 0x00030000 + +#define NONSTOP_OVER_THRESHOLD -2 +#define WARN_NONSTOP_OVER_THRESHOLD -1 +#define DISABLE_RETIRE_PAGE 0 + +/* + * Bad address pfn : eeprom_umc_record.retired_row_pfn[39:0], + * nps mode: eeprom_umc_record.retired_row_pfn[47:40] + */ +#define EEPROM_RECORD_UMC_ADDR_MASK 0xFFFFFFFFFFULL +#define EEPROM_RECORD_UMC_NPS_MASK 0xFF0000000000ULL +#define EEPROM_RECORD_UMC_NPS_SHIFT 40 + +#define EEPROM_RECORD_UMC_NPS_MODE(RECORD) \ + (((RECORD)->retired_row_pfn & EEPROM_RECORD_UMC_NPS_MASK) >> \ + EEPROM_RECORD_UMC_NPS_SHIFT) + +#define EEPROM_RECORD_UMC_ADDR_PFN(RECORD) \ + ((RECORD)->retired_row_pfn & EEPROM_RECORD_UMC_ADDR_MASK) + +#define EEPROM_RECORD_SETUP_UMC_ADDR_AND_NPS(RECORD, ADDR, NPS) \ +do { \ + uint64_t tmp = (NPS); \ + tmp = ((tmp << EEPROM_RECORD_UMC_NPS_SHIFT) & EEPROM_RECORD_UMC_NPS_MASK); \ + tmp |= (ADDR) & EEPROM_RECORD_UMC_ADDR_MASK; \ + (RECORD)->retired_row_pfn = tmp; \ +} while (0) + +enum ras_gpu_health_status { + RAS_GPU_HEALTH_NONE = 0, + RAS_GPU_HEALTH_USABLE = 1, + RAS_GPU_RETIRED__ECC_REACH_THRESHOLD = 2, + RAS_GPU_IN_BAD_STATUS = 3, +}; + +enum ras_eeprom_err_type { + RAS_EEPROM_ERR_NA, + RAS_EEPROM_ERR_RECOVERABLE, + RAS_EEPROM_ERR_NON_RECOVERABLE, + RAS_EEPROM_ERR_COUNT, +}; + +struct ras_eeprom_table_header { + uint32_t header; + uint32_t version; + uint32_t first_rec_offset; + uint32_t tbl_size; + uint32_t checksum; +} __packed; + +struct ras_eeprom_table_ras_info { + u8 rma_status; + u8 health_percent; + u16 ecc_page_threshold; + u32 padding[64 - 1]; +} __packed; + +struct ras_eeprom_control { + struct ras_eeprom_table_header tbl_hdr; + struct ras_eeprom_table_ras_info tbl_rai; + + /* record threshold */ + int record_threshold_config; + uint32_t record_threshold_count; + bool update_channel_flag; + + const struct ras_eeprom_sys_func *sys_func; + void *i2c_adapter; + u32 i2c_port; + u16 max_read_len; + u16 max_write_len; + + /* Base I2C EEPPROM 19-bit memory address, + * where the table is located. For more information, + * see top of amdgpu_eeprom.c. + */ + u32 i2c_address; + + /* The byte offset off of @i2c_address + * where the table header is found, + * and where the records start--always + * right after the header. + */ + u32 ras_header_offset; + u32 ras_info_offset; + u32 ras_record_offset; + + /* Number of records in the table. + */ + u32 ras_num_recs; + + /* First record index to read, 0-based. + * Range is [0, num_recs-1]. This is + * an absolute index, starting right after + * the table header. + */ + u32 ras_fri; + + /* Maximum possible number of records + * we could store, i.e. the maximum capacity + * of the table. + */ + u32 ras_max_record_count; + + /* Protect table access via this mutex. + */ + struct mutex ras_tbl_mutex; + + /* Record channel info which occurred bad pages + */ + u32 bad_channel_bitmap; +}; + +/* + * Represents single table record. Packed to be easily serialized into byte + * stream. + */ +struct eeprom_umc_record { + + union { + uint64_t address; + uint64_t offset; + }; + + uint64_t retired_row_pfn; + uint64_t ts; + + enum ras_eeprom_err_type err_type; + + union { + unsigned char bank; + unsigned char cu; + }; + + unsigned char mem_channel; + unsigned char mcumc_id; + + /* The following variables will not be saved to eeprom. + */ + uint64_t cur_nps_retired_row_pfn; + uint32_t cur_nps_bank; + uint32_t cur_nps; +}; + +struct ras_core_context; +int ras_eeprom_hw_init(struct ras_core_context *ras_core); +int ras_eeprom_hw_fini(struct ras_core_context *ras_core); + +int ras_eeprom_reset_table(struct ras_core_context *ras_core); + +bool ras_eeprom_check_safety_watermark(struct ras_core_context *ras_core); + +int ras_eeprom_read(struct ras_core_context *ras_core, + struct eeprom_umc_record *records, const u32 num); + +int ras_eeprom_append(struct ras_core_context *ras_core, + struct eeprom_umc_record *records, const u32 num); + +uint32_t ras_eeprom_max_record_count(struct ras_core_context *ras_core); +uint32_t ras_eeprom_get_record_count(struct ras_core_context *ras_core); +void ras_eeprom_sync_info(struct ras_core_context *ras_core); + +int ras_eeprom_check_storage_status(struct ras_core_context *ras_core); +enum ras_gpu_health_status + ras_eeprom_check_gpu_status(struct ras_core_context *ras_core); +#endif From 8fa4f1f906aaa87441438b0e63aeca60f3a3bcd2 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Thu, 5 Jun 2025 17:46:08 +0800 Subject: [PATCH 2094/2653] drm/amd/ras: Add psp v13_0 ras functions Add psp v13_0 ras functions. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/ras/rascore/ras_psp_v13_0.c | 46 +++++++++++++++++++ .../gpu/drm/amd/ras/rascore/ras_psp_v13_0.h | 31 +++++++++++++ 2 files changed, 77 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_psp_v13_0.c create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_psp_v13_0.h diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_psp_v13_0.c b/drivers/gpu/drm/amd/ras/rascore/ras_psp_v13_0.c new file mode 100644 index 0000000000000..626cf39b75acf --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_psp_v13_0.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "ras.h" +#include "ras_psp_v13_0.h" + +#define regMP0_SMN_C2PMSG_67 0x0083 +#define regMP0_SMN_C2PMSG_67_BASE_IDX 0 + +static uint32_t ras_psp_v13_0_ring_wptr_get(struct ras_core_context *ras_core) +{ + return RAS_DEV_RREG32_SOC15(ras_core->dev, MP0, 0, regMP0_SMN_C2PMSG_67); +} + +static int ras_psp_v13_0_ring_wptr_set(struct ras_core_context *ras_core, uint32_t value) +{ + RAS_DEV_WREG32_SOC15(ras_core->dev, MP0, 0, regMP0_SMN_C2PMSG_67, value); + + return 0; +} + +const struct ras_psp_ip_func ras_psp_v13_0 = { + .psp_ras_ring_wptr_get = ras_psp_v13_0_ring_wptr_get, + .psp_ras_ring_wptr_set = ras_psp_v13_0_ring_wptr_set, +}; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_psp_v13_0.h b/drivers/gpu/drm/amd/ras/rascore/ras_psp_v13_0.h new file mode 100644 index 0000000000000..b705ffe38a124 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_psp_v13_0.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __RAS_PSP_V13_0_H__ +#define __RAS_PSP_V13_0_H__ +#include "ras_psp.h" + +extern const struct ras_psp_ip_func ras_psp_v13_0; + +#endif From 18ca3e841b6576819754d1bdd1238a9931099107 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Thu, 5 Jun 2025 17:46:51 +0800 Subject: [PATCH 2095/2653] drm/amd/ras: Add psp ras common functions Add psp ras common functions. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/ras/rascore/ras_psp.c | 750 ++++++++++++++++++++ drivers/gpu/drm/amd/ras/rascore/ras_psp.h | 145 ++++ drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h | 231 ++++++ 3 files changed, 1126 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_psp.c create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_psp.h create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_psp.c b/drivers/gpu/drm/amd/ras/rascore/ras_psp.c new file mode 100644 index 0000000000000..c94effd4b1140 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_psp.c @@ -0,0 +1,750 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "ras.h" +#include "ras_ta_if.h" +#include "ras_psp.h" +#include "ras_psp_v13_0.h" + +/* position of instance value in sub_block_index of + * ta_ras_trigger_error_input, the sub block uses lower 12 bits + */ +#define RAS_TA_INST_MASK 0xfffff000 +#define RAS_TA_INST_SHIFT 0xc + +static const struct ras_psp_ip_func *ras_psp_get_ip_funcs( + struct ras_core_context *ras_core, uint32_t ip_version) +{ + switch (ip_version) { + case IP_VERSION(13, 0, 6): + case IP_VERSION(13, 0, 14): + case IP_VERSION(13, 0, 12): + return &ras_psp_v13_0; + default: + RAS_DEV_ERR(ras_core->dev, + "psp ip version(0x%x) is not supported!\n", ip_version); + break; + } + + return NULL; +} + +static int ras_psp_sync_system_ras_psp_status(struct ras_core_context *ras_core) +{ + struct ras_psp *psp = &ras_core->ras_psp; + struct ras_ta_ctx *ta_ctx = &ras_core->ras_psp.ta_ctx; + struct ras_psp_ctx *psp_ctx = &ras_core->ras_psp.psp_ctx; + struct ras_psp_sys_status status = {0}; + int ret; + + if (psp->sys_func && psp->sys_func->get_ras_psp_system_status) { + ret = psp->sys_func->get_ras_psp_system_status(ras_core, &status); + if (ret) + return ret; + + if (status.initialized) { + ta_ctx->preload_ras_ta_enabled = true; + ta_ctx->ras_ta_initialized = status.initialized; + ta_ctx->session_id = status.session_id; + } + + psp_ctx->external_mutex = status.psp_cmd_mutex; + } + + return 0; +} + +static int ras_psp_get_ras_ta_init_param(struct ras_core_context *ras_core, + struct ras_ta_init_param *ras_ta_param) +{ + struct ras_psp *psp = &ras_core->ras_psp; + + if (psp->sys_func && psp->sys_func->get_ras_ta_init_param) + return psp->sys_func->get_ras_ta_init_param(ras_core, ras_ta_param); + + RAS_DEV_ERR(ras_core->dev, "Not config get_ras_ta_init_param API!!\n"); + return -EACCES; +} + +static struct gpu_mem_block *ras_psp_get_gpu_mem(struct ras_core_context *ras_core, + enum gpu_mem_type mem_type) +{ + struct ras_psp *psp = &ras_core->ras_psp; + struct gpu_mem_block *gpu_mem = NULL; + int ret; + + switch (mem_type) { + case GPU_MEM_TYPE_RAS_PSP_RING: + gpu_mem = &psp->psp_ring.ras_ring_gpu_mem; + break; + case GPU_MEM_TYPE_RAS_PSP_CMD: + gpu_mem = &psp->psp_ctx.psp_cmd_gpu_mem; + break; + case GPU_MEM_TYPE_RAS_PSP_FENCE: + gpu_mem = &psp->psp_ctx.out_fence_gpu_mem; + break; + case GPU_MEM_TYPE_RAS_TA_FW: + gpu_mem = &psp->ta_ctx.fw_gpu_mem; + break; + case GPU_MEM_TYPE_RAS_TA_CMD: + gpu_mem = &psp->ta_ctx.cmd_gpu_mem; + break; + default: + return NULL; + } + + if (!gpu_mem->ref_count) { + ret = ras_core_get_gpu_mem(ras_core, mem_type, gpu_mem); + if (ret) + return NULL; + gpu_mem->mem_type = mem_type; + } + + gpu_mem->ref_count++; + + return gpu_mem; +} + +static int ras_psp_put_gpu_mem(struct ras_core_context *ras_core, + struct gpu_mem_block *gpu_mem) +{ + if (!gpu_mem) + return 0; + + gpu_mem->ref_count--; + + if (gpu_mem->ref_count > 0) { + return 0; + } else if (gpu_mem->ref_count < 0) { + RAS_DEV_WARN(ras_core->dev, + "Duplicate free gpu memory %u\n", gpu_mem->mem_type); + } else { + ras_core_put_gpu_mem(ras_core, gpu_mem->mem_type, gpu_mem); + memset(gpu_mem, 0, sizeof(*gpu_mem)); + } + + return 0; +} + +static void __acquire_psp_cmd_lock(struct ras_core_context *ras_core) +{ + struct ras_psp_ctx *psp_ctx = &ras_core->ras_psp.psp_ctx; + + if (psp_ctx->external_mutex) + mutex_lock(psp_ctx->external_mutex); + else + mutex_lock(&psp_ctx->internal_mutex); +} + +static void __release_psp_cmd_lock(struct ras_core_context *ras_core) +{ + struct ras_psp_ctx *psp_ctx = &ras_core->ras_psp.psp_ctx; + + if (psp_ctx->external_mutex) + mutex_unlock(psp_ctx->external_mutex); + else + mutex_unlock(&psp_ctx->internal_mutex); +} + +static uint32_t __get_ring_frame_slot(struct ras_core_context *ras_core) +{ + struct ras_psp *psp = &ras_core->ras_psp; + uint32_t ras_ring_wptr_dw; + + ras_ring_wptr_dw = psp->ip_func->psp_ras_ring_wptr_get(ras_core); + + return (ras_ring_wptr_dw << 2) / sizeof(struct psp_gfx_rb_frame); +} + +static int __set_ring_frame_slot(struct ras_core_context *ras_core, + uint32_t slot) +{ + struct ras_psp *psp = &ras_core->ras_psp; + + return psp->ip_func->psp_ras_ring_wptr_set(ras_core, + (slot * sizeof(struct psp_gfx_rb_frame)) >> 2); +} + +static int write_frame_to_ras_psp_ring(struct ras_core_context *ras_core, + struct psp_gfx_rb_frame *frame) +{ + struct gpu_mem_block *ring_mem; + struct psp_gfx_rb_frame *rb_frame; + uint32_t max_frame_slot; + uint32_t slot_idx; + uint32_t write_flush_read_back = 0; + int ret = 0; + + ring_mem = ras_psp_get_gpu_mem(ras_core, GPU_MEM_TYPE_RAS_PSP_RING); + if (!ring_mem) + return -ENOMEM; + + max_frame_slot = + ring_mem->mem_size / sizeof(struct psp_gfx_rb_frame); + + rb_frame = + (struct psp_gfx_rb_frame *)ring_mem->mem_cpu_addr; + + slot_idx = __get_ring_frame_slot(ras_core); + if (slot_idx >= max_frame_slot) + slot_idx = 0; + + memcpy(&rb_frame[slot_idx], frame, sizeof(*frame)); + + /* Do a read to force the write of the frame before writing + * write pointer. + */ + write_flush_read_back = rb_frame[slot_idx].fence_value; + if (write_flush_read_back != frame->fence_value) { + RAS_DEV_ERR(ras_core->dev, + "Failed to submit ring cmd! cmd:0x%x:0x%x, fence:0x%x:0x%x value:%u, expected:%u\n", + rb_frame[slot_idx].cmd_buf_addr_hi, + rb_frame[slot_idx].cmd_buf_addr_lo, + rb_frame[slot_idx].fence_addr_hi, + rb_frame[slot_idx].fence_addr_lo, + write_flush_read_back, frame->fence_value); + ret = -EACCES; + goto err; + } + + slot_idx++; + + if (slot_idx >= max_frame_slot) + slot_idx = 0; + + __set_ring_frame_slot(ras_core, slot_idx); + +err: + ras_psp_put_gpu_mem(ras_core, ring_mem); + return ret; +} + +static int send_psp_cmd(struct ras_core_context *ras_core, + enum psp_gfx_cmd_id gfx_cmd_id, void *cmd_data, + uint32_t cmd_size, struct psp_cmd_resp *resp) +{ + struct ras_psp_ctx *psp_ctx = &ras_core->ras_psp.psp_ctx; + struct gpu_mem_block *psp_cmd_buf = NULL; + struct gpu_mem_block *psp_fence_buf = NULL; + struct psp_gfx_cmd_resp *gfx_cmd; + struct psp_gfx_rb_frame rb_frame; + int ret = 0; + int timeout = 1000; + + if (!cmd_data || (cmd_size > sizeof(union psp_gfx_commands)) || !resp) { + RAS_DEV_ERR(ras_core->dev, "Invalid RAS PSP command, id: %u\n", gfx_cmd_id); + return -EINVAL; + } + + __acquire_psp_cmd_lock(ras_core); + + psp_cmd_buf = ras_psp_get_gpu_mem(ras_core, GPU_MEM_TYPE_RAS_PSP_CMD); + if (!psp_cmd_buf) { + ret = -ENOMEM; + goto exit; + } + + psp_fence_buf = ras_psp_get_gpu_mem(ras_core, GPU_MEM_TYPE_RAS_PSP_FENCE); + if (!psp_fence_buf) { + ret = -ENOMEM; + goto exit; + } + + gfx_cmd = (struct psp_gfx_cmd_resp *)psp_cmd_buf->mem_cpu_addr; + memset(gfx_cmd, 0, sizeof(*gfx_cmd)); + gfx_cmd->cmd_id = gfx_cmd_id; + memcpy(&gfx_cmd->cmd, cmd_data, cmd_size); + + psp_ctx->in_fence_value++; + + memset(&rb_frame, 0, sizeof(rb_frame)); + rb_frame.cmd_buf_addr_hi = upper_32_bits(psp_cmd_buf->mem_mc_addr); + rb_frame.cmd_buf_addr_lo = lower_32_bits(psp_cmd_buf->mem_mc_addr); + rb_frame.fence_addr_hi = upper_32_bits(psp_fence_buf->mem_mc_addr); + rb_frame.fence_addr_lo = lower_32_bits(psp_fence_buf->mem_mc_addr); + rb_frame.fence_value = psp_ctx->in_fence_value; + + ret = write_frame_to_ras_psp_ring(ras_core, &rb_frame); + if (ret) { + psp_ctx->in_fence_value--; + goto exit; + } + + while (*((uint64_t *)psp_fence_buf->mem_cpu_addr) != + psp_ctx->in_fence_value) { + if (--timeout == 0) + break; + /* + * Shouldn't wait for timeout when err_event_athub occurs, + * because gpu reset thread triggered and lock resource should + * be released for psp resume sequence. + */ + if (ras_core_ras_interrupt_detected(ras_core)) + break; + + msleep(2); + } + + resp->status = gfx_cmd->resp.status; + resp->session_id = gfx_cmd->resp.session_id; + +exit: + ras_psp_put_gpu_mem(ras_core, psp_cmd_buf); + ras_psp_put_gpu_mem(ras_core, psp_fence_buf); + + __release_psp_cmd_lock(ras_core); + + return ret; +} + +static void __check_ras_ta_cmd_resp(struct ras_core_context *ras_core, + struct ras_ta_cmd *ras_cmd) +{ + + if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { + RAS_DEV_WARN(ras_core->dev, "ECC switch disabled\n"); + ras_cmd->ras_status = RAS_TA_STATUS__ERROR_RAS_NOT_AVAILABLE; + } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) + RAS_DEV_WARN(ras_core->dev, "RAS internal register access blocked\n"); + + switch (ras_cmd->ras_status) { + case RAS_TA_STATUS__ERROR_UNSUPPORTED_IP: + RAS_DEV_WARN(ras_core->dev, + "RAS WARNING: cmd failed due to unsupported ip\n"); + break; + case RAS_TA_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: + RAS_DEV_WARN(ras_core->dev, + "RAS WARNING: cmd failed due to unsupported error injection\n"); + break; + case RAS_TA_STATUS__SUCCESS: + break; + case RAS_TA_STATUS__TEE_ERROR_ACCESS_DENIED: + if (ras_cmd->cmd_id == RAS_TA_CMD_ID__TRIGGER_ERROR) + RAS_DEV_WARN(ras_core->dev, + "RAS WARNING: Inject error to critical region is not allowed\n"); + break; + default: + RAS_DEV_WARN(ras_core->dev, + "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); + break; + } +} + +static int send_ras_ta_runtime_cmd(struct ras_core_context *ras_core, + enum ras_ta_cmd_id cmd_id, void *in, uint32_t in_size, + void *out, uint32_t out_size) +{ + struct ras_ta_ctx *ta_ctx = &ras_core->ras_psp.ta_ctx; + struct gpu_mem_block *cmd_mem; + struct ras_ta_cmd *ras_cmd; + struct psp_gfx_cmd_invoke_cmd invoke_cmd = {0}; + struct psp_cmd_resp resp = {0}; + int ret = 0; + + if (!in || (in_size > sizeof(union ras_ta_cmd_input)) || + (cmd_id >= MAX_RAS_TA_CMD_ID)) { + RAS_DEV_ERR(ras_core->dev, "Invalid RAS TA command, id: %u\n", cmd_id); + return -EINVAL; + } + + ras_psp_sync_system_ras_psp_status(ras_core); + + cmd_mem = ras_psp_get_gpu_mem(ras_core, GPU_MEM_TYPE_RAS_TA_CMD); + if (!cmd_mem) + return -ENOMEM; + + if (!ras_core_down_trylock_gpu_reset_lock(ras_core)) { + ret = -EACCES; + goto out; + } + + ras_cmd = (struct ras_ta_cmd *)cmd_mem->mem_cpu_addr; + + mutex_lock(&ta_ctx->ta_mutex); + + memset(ras_cmd, 0, sizeof(*ras_cmd)); + ras_cmd->cmd_id = cmd_id; + memcpy(&ras_cmd->ras_in_message, in, in_size); + + invoke_cmd.ta_cmd_id = cmd_id; + invoke_cmd.session_id = ta_ctx->session_id; + + ret = send_psp_cmd(ras_core, GFX_CMD_ID_INVOKE_CMD, + &invoke_cmd, sizeof(invoke_cmd), &resp); + + /* If err_event_athub occurs error inject was successful, however + * return status from TA is no long reliable + */ + if (ras_core_ras_interrupt_detected(ras_core)) { + ret = 0; + goto unlock; + } + + if (ret || resp.status) { + RAS_DEV_ERR(ras_core->dev, + "RAS: Failed to send psp cmd! ret:%d, status:%u\n", + ret, resp.status); + ret = -ESTRPIPE; + goto unlock; + } + + if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) { + RAS_DEV_WARN(ras_core->dev, "RAS: Unsupported Interface\n"); + ret = -EINVAL; + goto unlock; + } + + if (!ras_cmd->ras_status && out && out_size) + memcpy(out, &ras_cmd->ras_out_message, out_size); + + __check_ras_ta_cmd_resp(ras_core, ras_cmd); + +unlock: + mutex_unlock(&ta_ctx->ta_mutex); + ras_core_up_gpu_reset_lock(ras_core); +out: + ras_psp_put_gpu_mem(ras_core, cmd_mem); + return ret; +} + +static int trigger_ras_ta_error(struct ras_core_context *ras_core, + struct ras_ta_trigger_error_input *info, uint32_t instance_mask) +{ + uint32_t dev_mask = 0; + + switch (info->block_id) { + case RAS_TA_BLOCK__GFX: + if (ras_gfx_get_ta_subblock(ras_core, info->inject_error_type, + info->sub_block_index, &info->sub_block_index)) + return -EINVAL; + + dev_mask = RAS_GET_MASK(ras_core->dev, GC, instance_mask); + break; + case RAS_TA_BLOCK__SDMA: + dev_mask = RAS_GET_MASK(ras_core->dev, SDMA0, instance_mask); + break; + case RAS_TA_BLOCK__VCN: + case RAS_TA_BLOCK__JPEG: + dev_mask = RAS_GET_MASK(ras_core->dev, VCN, instance_mask); + break; + default: + dev_mask = instance_mask; + break; + } + + /* reuse sub_block_index for backward compatibility */ + dev_mask <<= RAS_TA_INST_SHIFT; + dev_mask &= RAS_TA_INST_MASK; + info->sub_block_index |= dev_mask; + + return send_ras_ta_runtime_cmd(ras_core, RAS_TA_CMD_ID__TRIGGER_ERROR, + info, sizeof(*info), NULL, 0); +} + +static int send_load_ta_fw_cmd(struct ras_core_context *ras_core, + struct ras_ta_ctx *ta_ctx) +{ + struct ras_ta_fw_bin *fw_bin = &ta_ctx->fw_bin; + struct gpu_mem_block *fw_mem; + struct gpu_mem_block *cmd_mem; + struct ras_ta_cmd *ta_cmd; + struct ras_ta_init_flags *ta_init_flags; + struct psp_gfx_cmd_load_ta psp_load_ta_cmd; + struct psp_cmd_resp resp = {0}; + struct ras_ta_image_header *fw_hdr = NULL; + int ret; + + fw_mem = ras_psp_get_gpu_mem(ras_core, GPU_MEM_TYPE_RAS_TA_FW); + if (!fw_mem) + return -ENOMEM; + + cmd_mem = ras_psp_get_gpu_mem(ras_core, GPU_MEM_TYPE_RAS_TA_CMD); + if (!cmd_mem) { + ret = -ENOMEM; + goto err; + } + + ret = ras_psp_get_ras_ta_init_param(ras_core, &ta_ctx->init_param); + if (ret) + goto err; + + if (!ras_core_down_trylock_gpu_reset_lock(ras_core)) { + ret = -EACCES; + goto err; + } + + /* copy ras ta binary to shared gpu memory */ + memcpy(fw_mem->mem_cpu_addr, fw_bin->bin_addr, fw_bin->bin_size); + fw_mem->mem_size = fw_bin->bin_size; + + /* Initialize ras ta startup parameter */ + ta_cmd = (struct ras_ta_cmd *)cmd_mem->mem_cpu_addr; + ta_init_flags = &ta_cmd->ras_in_message.init_flags; + + ta_init_flags->poison_mode_en = ta_ctx->init_param.poison_mode_en; + ta_init_flags->dgpu_mode = ta_ctx->init_param.dgpu_mode; + ta_init_flags->xcc_mask = ta_ctx->init_param.xcc_mask; + ta_init_flags->channel_dis_num = ta_ctx->init_param.channel_dis_num; + ta_init_flags->nps_mode = ta_ctx->init_param.nps_mode; + ta_init_flags->active_umc_mask = ta_ctx->init_param.active_umc_mask; + + /* Setup load ras ta command */ + memset(&psp_load_ta_cmd, 0, sizeof(psp_load_ta_cmd)); + psp_load_ta_cmd.app_phy_addr_lo = lower_32_bits(fw_mem->mem_mc_addr); + psp_load_ta_cmd.app_phy_addr_hi = upper_32_bits(fw_mem->mem_mc_addr); + psp_load_ta_cmd.app_len = fw_mem->mem_size; + psp_load_ta_cmd.cmd_buf_phy_addr_lo = lower_32_bits(cmd_mem->mem_mc_addr); + psp_load_ta_cmd.cmd_buf_phy_addr_hi = upper_32_bits(cmd_mem->mem_mc_addr); + psp_load_ta_cmd.cmd_buf_len = cmd_mem->mem_size; + + ret = send_psp_cmd(ras_core, GFX_CMD_ID_LOAD_TA, + &psp_load_ta_cmd, sizeof(psp_load_ta_cmd), &resp); + if (!ret && !resp.status) { + /* Read TA version at FW offset 0x60 if TA version not found*/ + fw_hdr = (struct ras_ta_image_header *)fw_bin->bin_addr; + RAS_DEV_INFO(ras_core->dev, "PSP: RAS TA(version:%X.%X.%X.%X) is loaded.\n", + (fw_hdr->image_version >> 24) & 0xFF, (fw_hdr->image_version >> 16) & 0xFF, + (fw_hdr->image_version >> 8) & 0xFF, fw_hdr->image_version & 0xFF); + ta_ctx->ta_version = fw_hdr->image_version; + ta_ctx->session_id = resp.session_id; + ta_ctx->ras_ta_initialized = true; + } else { + RAS_DEV_ERR(ras_core->dev, + "Failed to load RAS TA! ret:%d, status:%d\n", ret, resp.status); + } + + ras_core_up_gpu_reset_lock(ras_core); + +err: + ras_psp_put_gpu_mem(ras_core, fw_mem); + ras_psp_put_gpu_mem(ras_core, cmd_mem); + return ret; +} + +static int load_ras_ta_firmware(struct ras_core_context *ras_core, + struct ras_psp_ta_load *ras_ta_load) +{ + struct ras_ta_ctx *ta_ctx = &ras_core->ras_psp.ta_ctx; + struct ras_ta_fw_bin *fw_bin = &ta_ctx->fw_bin; + int ret; + + fw_bin->bin_addr = ras_ta_load->bin_addr; + fw_bin->bin_size = ras_ta_load->bin_size; + fw_bin->fw_version = ras_ta_load->fw_version; + fw_bin->feature_version = ras_ta_load->feature_version; + + ret = send_load_ta_fw_cmd(ras_core, ta_ctx); + if (!ret) { + ras_ta_load->out_session_id = ta_ctx->session_id; + ras_ta_load->out_loaded_ta_version = ta_ctx->ta_version; + } + + return ret; +} + +static int unload_ras_ta_firmware(struct ras_core_context *ras_core, + struct ras_psp_ta_unload *ras_ta_unload) +{ + struct ras_ta_ctx *ta_ctx = &ras_core->ras_psp.ta_ctx; + struct psp_gfx_cmd_unload_ta cmd_unload_ta = {0}; + struct psp_cmd_resp resp = {0}; + int ret; + + if (!ras_core_down_trylock_gpu_reset_lock(ras_core)) + return -EACCES; + + cmd_unload_ta.session_id = ta_ctx->session_id; + ret = send_psp_cmd(ras_core, GFX_CMD_ID_UNLOAD_TA, + &cmd_unload_ta, sizeof(cmd_unload_ta), &resp); + if (ret || resp.status) { + RAS_DEV_ERR(ras_core->dev, + "Failed to unload RAS TA! ret:%d, status:%u\n", + ret, resp.status); + goto unlock; + } + + kfree(ta_ctx->fw_bin.bin_addr); + memset(&ta_ctx->fw_bin, 0, sizeof(ta_ctx->fw_bin)); + ta_ctx->ta_version = 0; + ta_ctx->ras_ta_initialized = false; + ta_ctx->session_id = 0; + +unlock: + ras_core_up_gpu_reset_lock(ras_core); + + return ret; +} + +int ras_psp_load_firmware(struct ras_core_context *ras_core, + struct ras_psp_ta_load *ras_ta_load) +{ + struct ras_ta_ctx *ta_ctx = &ras_core->ras_psp.ta_ctx; + struct ras_psp_ta_unload ras_ta_unload = {0}; + int ret; + + if (ta_ctx->preload_ras_ta_enabled) + return 0; + + if (!ras_ta_load) + return -EINVAL; + + if (ta_ctx->ras_ta_initialized) { + ras_ta_unload.ras_session_id = ta_ctx->session_id; + ret = unload_ras_ta_firmware(ras_core, &ras_ta_unload); + if (ret) + return ret; + } + + return load_ras_ta_firmware(ras_core, ras_ta_load); +} + +int ras_psp_unload_firmware(struct ras_core_context *ras_core, + struct ras_psp_ta_unload *ras_ta_unload) +{ + struct ras_ta_ctx *ta_ctx = &ras_core->ras_psp.ta_ctx; + + if (ta_ctx->preload_ras_ta_enabled) + return 0; + + if ((!ras_ta_unload) || + (ras_ta_unload->ras_session_id != ta_ctx->session_id)) + return -EINVAL; + + return unload_ras_ta_firmware(ras_core, ras_ta_unload); +} + +int ras_psp_trigger_error(struct ras_core_context *ras_core, + struct ras_ta_trigger_error_input *info, uint32_t instance_mask) +{ + struct ras_ta_ctx *ta_ctx = &ras_core->ras_psp.ta_ctx; + + if (!ta_ctx->preload_ras_ta_enabled && !ta_ctx->ras_ta_initialized) { + RAS_DEV_ERR(ras_core->dev, "RAS: ras firmware not initialized!"); + return -ENOEXEC; + } + + if (!info) + return -EINVAL; + + return trigger_ras_ta_error(ras_core, info, instance_mask); +} + +int ras_psp_query_address(struct ras_core_context *ras_core, + struct ras_ta_query_address_input *addr_in, + struct ras_ta_query_address_output *addr_out) +{ + struct ras_ta_ctx *ta_ctx = &ras_core->ras_psp.ta_ctx; + + if (!ta_ctx->preload_ras_ta_enabled && + !ta_ctx->ras_ta_initialized) { + RAS_DEV_ERR(ras_core->dev, "RAS: ras firmware not initialized!"); + return -ENOEXEC; + } + + if (!addr_in || !addr_out) + return -EINVAL; + + return send_ras_ta_runtime_cmd(ras_core, RAS_TA_CMD_ID__QUERY_ADDRESS, + addr_in, sizeof(*addr_in), addr_out, sizeof(*addr_out)); +} + +int ras_psp_sw_init(struct ras_core_context *ras_core) +{ + struct ras_psp *psp = &ras_core->ras_psp; + + memset(psp, 0, sizeof(*psp)); + + psp->sys_func = ras_core->config->psp_cfg.psp_sys_fn; + if (!psp->sys_func) { + RAS_DEV_ERR(ras_core->dev, "RAS psp sys function not configured!\n"); + return -EINVAL; + } + + mutex_init(&psp->psp_ctx.internal_mutex); + mutex_init(&psp->ta_ctx.ta_mutex); + + return 0; +} + +int ras_psp_sw_fini(struct ras_core_context *ras_core) +{ + struct ras_psp *psp = &ras_core->ras_psp; + + mutex_destroy(&psp->psp_ctx.internal_mutex); + mutex_destroy(&psp->ta_ctx.ta_mutex); + + memset(psp, 0, sizeof(*psp)); + + return 0; +} + +int ras_psp_hw_init(struct ras_core_context *ras_core) +{ + struct ras_psp *psp = &ras_core->ras_psp; + + psp->psp_ip_version = ras_core->config->psp_ip_version; + + psp->ip_func = ras_psp_get_ip_funcs(ras_core, psp->psp_ip_version); + if (!psp->ip_func) + return -EINVAL; + + /* After GPU reset, the system RAS PSP status may change. + * therefore, it is necessary to synchronize the system status again. + */ + ras_psp_sync_system_ras_psp_status(ras_core); + + return 0; +} + +int ras_psp_hw_fini(struct ras_core_context *ras_core) +{ + return 0; +} + +bool ras_psp_check_supported_cmd(struct ras_core_context *ras_core, + enum ras_ta_cmd_id cmd_id) +{ + struct ras_ta_ctx *ta_ctx = &ras_core->ras_psp.ta_ctx; + bool ret = false; + + if (!ta_ctx->preload_ras_ta_enabled && !ta_ctx->ras_ta_initialized) + return false; + + switch (cmd_id) { + case RAS_TA_CMD_ID__QUERY_ADDRESS: + /* Currently, querying the address from RAS TA is only supported + * when the RAS TA firmware is loaded during driver installation. + */ + if (ta_ctx->preload_ras_ta_enabled) + ret = true; + break; + case RAS_TA_CMD_ID__TRIGGER_ERROR: + ret = true; + break; + default: + ret = false; + break; + } + + return ret; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_psp.h b/drivers/gpu/drm/amd/ras/rascore/ras_psp.h new file mode 100644 index 0000000000000..71776fecfd664 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_psp.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __RAS_PSP_H__ +#define __RAS_PSP_H__ +#include "ras.h" +#include "ras_ta_if.h" + +struct ras_core_context; +struct ras_ta_trigger_error_input; +struct ras_ta_query_address_input; +struct ras_ta_query_address_output; +enum ras_ta_cmd_id; + +struct ras_ta_image_header { + uint32_t reserved1[24]; + uint32_t image_version; /* [0x60] Off Chip Firmware Version */ + uint32_t reserved2[39]; +}; + +struct ras_psp_sys_status { + bool initialized; + uint32_t session_id; + void *psp_cmd_mutex; +}; + +struct ras_ta_init_param { + uint8_t poison_mode_en; + uint8_t dgpu_mode; + uint16_t xcc_mask; + uint8_t channel_dis_num; + uint8_t nps_mode; + uint32_t active_umc_mask; +}; + +struct gpu_mem_block { + uint32_t mem_type; + void *mem_bo; + uint64_t mem_mc_addr; + void *mem_cpu_addr; + uint32_t mem_size; + int ref_count; + void *private; +}; + +struct ras_psp_ip_func { + uint32_t (*psp_ras_ring_wptr_get)(struct ras_core_context *ras_core); + int (*psp_ras_ring_wptr_set)(struct ras_core_context *ras_core, uint32_t wptr); +}; + +struct ras_psp_ring { + struct gpu_mem_block ras_ring_gpu_mem; +}; + +struct psp_cmd_resp { + uint32_t status; + uint32_t session_id; +}; + +struct ras_psp_ctx { + void *external_mutex; + struct mutex internal_mutex; + uint64_t in_fence_value; + struct gpu_mem_block psp_cmd_gpu_mem; + struct gpu_mem_block out_fence_gpu_mem; +}; + +struct ras_ta_fw_bin { + uint32_t fw_version; + uint32_t feature_version; + uint32_t bin_size; + uint8_t *bin_addr; +}; + +struct ras_ta_ctx { + bool preload_ras_ta_enabled; + bool ras_ta_initialized; + uint32_t session_id; + uint32_t resp_status; + uint32_t ta_version; + struct mutex ta_mutex; + struct ras_ta_fw_bin fw_bin; + struct ras_ta_init_param init_param; + struct gpu_mem_block fw_gpu_mem; + struct gpu_mem_block cmd_gpu_mem; +}; + +struct ras_psp { + uint32_t psp_ip_version; + struct ras_psp_ring psp_ring; + struct ras_psp_ctx psp_ctx; + struct ras_ta_ctx ta_ctx; + const struct ras_psp_ip_func *ip_func; + const struct ras_psp_sys_func *sys_func; +}; + +struct ras_psp_ta_load { + uint32_t fw_version; + uint32_t feature_version; + uint32_t bin_size; + uint8_t *bin_addr; + uint64_t out_session_id; + uint32_t out_loaded_ta_version; +}; + +struct ras_psp_ta_unload { + uint64_t ras_session_id; +}; + +int ras_psp_sw_init(struct ras_core_context *ras_core); +int ras_psp_sw_fini(struct ras_core_context *ras_core); +int ras_psp_hw_init(struct ras_core_context *ras_core); +int ras_psp_hw_fini(struct ras_core_context *ras_core); +int ras_psp_load_firmware(struct ras_core_context *ras_core, + struct ras_psp_ta_load *ras_ta_load); +int ras_psp_unload_firmware(struct ras_core_context *ras_core, + struct ras_psp_ta_unload *ras_ta_unload); +int ras_psp_trigger_error(struct ras_core_context *ras_core, + struct ras_ta_trigger_error_input *info, uint32_t instance_mask); +int ras_psp_query_address(struct ras_core_context *ras_core, + struct ras_ta_query_address_input *addr_in, + struct ras_ta_query_address_output *addr_out); +bool ras_psp_check_supported_cmd(struct ras_core_context *ras_core, + enum ras_ta_cmd_id cmd_id); +#endif diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h b/drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h new file mode 100644 index 0000000000000..0921e36d3274e --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h @@ -0,0 +1,231 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _RAS_TA_IF_H +#define _RAS_TA_IF_H +#include "ras.h" + +#define RAS_TA_HOST_IF_VER 0 + +/* Responses have bit 31 set */ +#define RSP_ID_MASK (1U << 31) +#define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK) + +/* invalid node instance value */ +#define RAS_TA_INV_NODE 0xffff + +/* RAS related enumerations */ +/**********************************************************/ +enum ras_ta_cmd_id { + RAS_TA_CMD_ID__ENABLE_FEATURES = 0, + RAS_TA_CMD_ID__DISABLE_FEATURES, + RAS_TA_CMD_ID__TRIGGER_ERROR, + RAS_TA_CMD_ID__QUERY_BLOCK_INFO, + RAS_TA_CMD_ID__QUERY_SUB_BLOCK_INFO, + RAS_TA_CMD_ID__QUERY_ADDRESS, + MAX_RAS_TA_CMD_ID +}; + +enum ras_ta_status { + RAS_TA_STATUS__SUCCESS = 0x0000, + RAS_TA_STATUS__RESET_NEEDED = 0xA001, + RAS_TA_STATUS__ERROR_INVALID_PARAMETER = 0xA002, + RAS_TA_STATUS__ERROR_RAS_NOT_AVAILABLE = 0xA003, + RAS_TA_STATUS__ERROR_RAS_DUPLICATE_CMD = 0xA004, + RAS_TA_STATUS__ERROR_INJECTION_FAILED = 0xA005, + RAS_TA_STATUS__ERROR_ASD_READ_WRITE = 0xA006, + RAS_TA_STATUS__ERROR_TOGGLE_DF_CSTATE = 0xA007, + RAS_TA_STATUS__ERROR_TIMEOUT = 0xA008, + RAS_TA_STATUS__ERROR_BLOCK_DISABLED = 0XA009, + RAS_TA_STATUS__ERROR_GENERIC = 0xA00A, + RAS_TA_STATUS__ERROR_RAS_MMHUB_INIT = 0xA00B, + RAS_TA_STATUS__ERROR_GET_DEV_INFO = 0xA00C, + RAS_TA_STATUS__ERROR_UNSUPPORTED_DEV = 0xA00D, + RAS_TA_STATUS__ERROR_NOT_INITIALIZED = 0xA00E, + RAS_TA_STATUS__ERROR_TEE_INTERNAL = 0xA00F, + RAS_TA_STATUS__ERROR_UNSUPPORTED_FUNCTION = 0xA010, + RAS_TA_STATUS__ERROR_SYS_DRV_REG_ACCESS = 0xA011, + RAS_TA_STATUS__ERROR_RAS_READ_WRITE = 0xA012, + RAS_TA_STATUS__ERROR_NULL_PTR = 0xA013, + RAS_TA_STATUS__ERROR_UNSUPPORTED_IP = 0xA014, + RAS_TA_STATUS__ERROR_PCS_STATE_QUIET = 0xA015, + RAS_TA_STATUS__ERROR_PCS_STATE_ERROR = 0xA016, + RAS_TA_STATUS__ERROR_PCS_STATE_HANG = 0xA017, + RAS_TA_STATUS__ERROR_PCS_STATE_UNKNOWN = 0xA018, + RAS_TA_STATUS__ERROR_UNSUPPORTED_ERROR_INJ = 0xA019, + RAS_TA_STATUS__TEE_ERROR_ACCESS_DENIED = 0xA01A +}; + +enum ras_ta_block { + RAS_TA_BLOCK__UMC = 0, + RAS_TA_BLOCK__SDMA, + RAS_TA_BLOCK__GFX, + RAS_TA_BLOCK__MMHUB, + RAS_TA_BLOCK__ATHUB, + RAS_TA_BLOCK__PCIE_BIF, + RAS_TA_BLOCK__HDP, + RAS_TA_BLOCK__XGMI_WAFL, + RAS_TA_BLOCK__DF, + RAS_TA_BLOCK__SMN, + RAS_TA_BLOCK__SEM, + RAS_TA_BLOCK__MP0, + RAS_TA_BLOCK__MP1, + RAS_TA_BLOCK__FUSE, + RAS_TA_BLOCK__MCA, + RAS_TA_BLOCK__VCN, + RAS_TA_BLOCK__JPEG, + RAS_TA_BLOCK__IH, + RAS_TA_BLOCK__MPIO, + RAS_TA_BLOCK__MMSCH, + RAS_TA_NUM_BLOCK_MAX +}; + +enum ras_ta_mca_block { + RAS_TA_MCA_BLOCK__MP0 = 0, + RAS_TA_MCA_BLOCK__MP1 = 1, + RAS_TA_MCA_BLOCK__MPIO = 2, + RAS_TA_MCA_BLOCK__IOHC = 3, + RAS_TA_MCA_NUM_BLOCK_MAX +}; + +enum ras_ta_error_type { + RAS_TA_ERROR__NONE = 0, + RAS_TA_ERROR__PARITY = 1, + RAS_TA_ERROR__SINGLE_CORRECTABLE = 2, + RAS_TA_ERROR__MULTI_UNCORRECTABLE = 4, + RAS_TA_ERROR__POISON = 8, +}; + +enum ras_ta_address_type { + RAS_TA_MCA_TO_PA, + RAS_TA_PA_TO_MCA, +}; + +enum ras_ta_nps_mode { + RAS_TA_UNKNOWN_MODE = 0, + RAS_TA_NPS1_MODE = 1, + RAS_TA_NPS2_MODE = 2, + RAS_TA_NPS4_MODE = 4, + RAS_TA_NPS8_MODE = 8, +}; + +/* Input/output structures for RAS commands */ +/**********************************************************/ + +struct ras_ta_enable_features_input { + enum ras_ta_block block_id; + enum ras_ta_error_type error_type; +}; + +struct ras_ta_disable_features_input { + enum ras_ta_block block_id; + enum ras_ta_error_type error_type; +}; + +struct ras_ta_trigger_error_input { + /* ras-block. i.e. umc, gfx */ + enum ras_ta_block block_id; + + /* type of error. i.e. single_correctable */ + enum ras_ta_error_type inject_error_type; + + /* mem block. i.e. hbm, sram etc. */ + uint32_t sub_block_index; + + /* explicit address of error */ + uint64_t address; + + /* method if error injection. i.e persistent, coherent etc. */ + uint64_t value; +}; + +struct ras_ta_init_flags { + uint8_t poison_mode_en; + uint8_t dgpu_mode; + uint16_t xcc_mask; + uint8_t channel_dis_num; + uint8_t nps_mode; + uint32_t active_umc_mask; +}; + +struct ras_ta_mca_addr { + uint64_t err_addr; + uint32_t ch_inst; + uint32_t umc_inst; + uint32_t node_inst; + uint32_t socket_id; +}; + +struct ras_ta_phy_addr { + uint64_t pa; + uint32_t bank; + uint32_t channel_idx; +}; + +struct ras_ta_query_address_input { + enum ras_ta_address_type addr_type; + struct ras_ta_mca_addr ma; + struct ras_ta_phy_addr pa; +}; + +struct ras_ta_output_flags { + uint8_t ras_init_success_flag; + uint8_t err_inject_switch_disable_flag; + uint8_t reg_access_failure_flag; +}; + +struct ras_ta_query_address_output { + /* don't use the flags here */ + struct ras_ta_output_flags flags; + struct ras_ta_mca_addr ma; + struct ras_ta_phy_addr pa; +}; + +/* Common input structure for RAS callbacks */ +/**********************************************************/ +union ras_ta_cmd_input { + struct ras_ta_init_flags init_flags; + struct ras_ta_enable_features_input enable_features; + struct ras_ta_disable_features_input disable_features; + struct ras_ta_trigger_error_input trigger_error; + struct ras_ta_query_address_input address; + uint32_t reserve_pad[256]; +}; + +union ras_ta_cmd_output { + struct ras_ta_output_flags flags; + struct ras_ta_query_address_output address; + uint32_t reserve_pad[256]; +}; + +struct ras_ta_cmd { + uint32_t cmd_id; + uint32_t resp_id; + uint32_t ras_status; + uint32_t if_version; + union ras_ta_cmd_input ras_in_message; + union ras_ta_cmd_output ras_out_message; +}; + +#endif From fcce966b15876d59a4262a347e41a5245d0d859f Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 17:31:24 +0800 Subject: [PATCH 2096/2653] drm/amd/ras: Add ras ioctl command handler Add ras ioctl command handler. V2: Remove ras global device list. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/ras/rascore/ras_cmd.c | 527 ++++++++++++++++++++++ drivers/gpu/drm/amd/ras/rascore/ras_cmd.h | 425 +++++++++++++++++ 2 files changed, 952 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_cmd.c create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_cmd.h diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c new file mode 100644 index 0000000000000..697619b30ea27 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c @@ -0,0 +1,527 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "ras.h" +#include "ras_cmd.h" + +#define RAS_CMD_MAJOR_VERSION 6 +#define RAS_CMD_MINOR_VERSION 0 +#define RAS_CMD_VERSION (((RAS_CMD_MAJOR_VERSION) << 10) | (RAS_CMD_MINOR_VERSION)) + +static int ras_cmd_add_device(struct ras_core_context *ras_core) +{ + INIT_LIST_HEAD(&ras_core->ras_cmd.head); + ras_core->ras_cmd.ras_core = ras_core; + ras_core->ras_cmd.dev_handle = (uint64_t)ras_core ^ RAS_CMD_DEV_HANDLE_MAGIC; + return 0; +} + +static int ras_cmd_remove_device(struct ras_core_context *ras_core) +{ + memset(&ras_core->ras_cmd, 0, sizeof(ras_core->ras_cmd)); + return 0; +} + +static int ras_get_block_ecc_info(struct ras_core_context *ras_core, + struct ras_cmd_ioctl *cmd, void *data) +{ + struct ras_cmd_block_ecc_info_req *input_data = + (struct ras_cmd_block_ecc_info_req *)cmd->input_buff_raw; + struct ras_cmd_block_ecc_info_rsp *output_data = + (struct ras_cmd_block_ecc_info_rsp *)cmd->output_buff_raw; + struct ras_ecc_count err_data; + int ret; + + if (cmd->input_size != sizeof(struct ras_cmd_block_ecc_info_req)) + return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + + memset(&err_data, 0, sizeof(err_data)); + ret = ras_aca_get_block_ecc_count(ras_core, input_data->block_id, &err_data); + if (ret) + return RAS_CMD__ERROR_GENERIC; + + output_data->ce_count = err_data.total_ce_count; + output_data->ue_count = err_data.total_ue_count; + output_data->de_count = err_data.total_de_count; + + cmd->output_size = sizeof(struct ras_cmd_block_ecc_info_rsp); + return RAS_CMD__SUCCESS; +} + +static void ras_cmd_update_bad_page_info(struct ras_cmd_bad_page_record *ras_cmd_record, + struct eeprom_umc_record *record) +{ + ras_cmd_record->retired_page = record->cur_nps_retired_row_pfn; + ras_cmd_record->ts = record->ts; + ras_cmd_record->err_type = record->err_type; + ras_cmd_record->mem_channel = record->mem_channel; + ras_cmd_record->mcumc_id = record->mcumc_id; + ras_cmd_record->address = record->address; + ras_cmd_record->bank = record->bank; + ras_cmd_record->valid = 1; +} + +static int ras_cmd_get_group_bad_pages(struct ras_core_context *ras_core, + uint32_t group_index, struct ras_cmd_bad_pages_info_rsp *output_data) +{ + struct eeprom_umc_record record; + struct ras_cmd_bad_page_record *ras_cmd_record; + uint32_t i = 0, bp_cnt = 0, group_cnt = 0; + + output_data->bp_in_group = 0; + output_data->group_index = 0; + + bp_cnt = ras_umc_get_badpage_count(ras_core); + if (bp_cnt) { + output_data->group_index = group_index; + group_cnt = bp_cnt / RAS_CMD_MAX_BAD_PAGES_PER_GROUP + + ((bp_cnt % RAS_CMD_MAX_BAD_PAGES_PER_GROUP) ? 1 : 0); + + if (group_index >= group_cnt) + return RAS_CMD__ERROR_INVALID_INPUT_DATA; + + i = group_index * RAS_CMD_MAX_BAD_PAGES_PER_GROUP; + for (; + i < bp_cnt && output_data->bp_in_group < RAS_CMD_MAX_BAD_PAGES_PER_GROUP; + i++) { + if (ras_umc_get_badpage_record(ras_core, i, &record)) + return RAS_CMD__ERROR_GENERIC; + + ras_cmd_record = &output_data->records[i % RAS_CMD_MAX_BAD_PAGES_PER_GROUP]; + + memset(ras_cmd_record, 0, sizeof(*ras_cmd_record)); + ras_cmd_update_bad_page_info(ras_cmd_record, &record); + output_data->bp_in_group++; + } + } + output_data->bp_total_cnt = bp_cnt; + return RAS_CMD__SUCCESS; +} + +static int ras_cmd_get_bad_pages(struct ras_core_context *ras_core, + struct ras_cmd_ioctl *cmd, void *data) +{ + struct ras_cmd_bad_pages_info_req *input_data = + (struct ras_cmd_bad_pages_info_req *)cmd->input_buff_raw; + struct ras_cmd_bad_pages_info_rsp *output_data = + (struct ras_cmd_bad_pages_info_rsp *)cmd->output_buff_raw; + int ret; + + if (cmd->input_size != sizeof(struct ras_cmd_bad_pages_info_req)) + return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + + ret = ras_cmd_get_group_bad_pages(ras_core, input_data->group_index, output_data); + if (ret) + return RAS_CMD__ERROR_GENERIC; + + output_data->version = 0; + + cmd->output_size = sizeof(struct ras_cmd_bad_pages_info_rsp); + return RAS_CMD__SUCCESS; +} + +static int ras_cmd_clear_bad_page_info(struct ras_core_context *ras_core, + struct ras_cmd_ioctl *cmd, void *data) +{ + if (cmd->input_size != sizeof(struct ras_cmd_dev_handle)) + return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + + if (ras_eeprom_reset_table(ras_core)) + return RAS_CMD__ERROR_GENERIC; + + if (ras_umc_clean_badpage_data(ras_core)) + return RAS_CMD__ERROR_GENERIC; + + return RAS_CMD__SUCCESS; +} + +static int ras_cmd_reset_all_error_counts(struct ras_core_context *ras_core, + struct ras_cmd_ioctl *cmd, void *data) +{ + if (cmd->input_size != sizeof(struct ras_cmd_dev_handle)) + return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + + if (ras_aca_clear_all_blocks_ecc_count(ras_core)) + return RAS_CMD__ERROR_GENERIC; + + if (ras_umc_clear_logged_ecc(ras_core)) + return RAS_CMD__ERROR_GENERIC; + + return RAS_CMD__SUCCESS; +} + +static int ras_cmd_get_cper_snapshot(struct ras_core_context *ras_core, + struct ras_cmd_ioctl *cmd, void *data) +{ + struct ras_cmd_cper_snapshot_rsp *output_data = + (struct ras_cmd_cper_snapshot_rsp *)cmd->output_buff_raw; + struct ras_log_batch_overview overview; + + if (cmd->input_size != sizeof(struct ras_cmd_cper_snapshot_req)) + return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + + ras_log_ring_get_batch_overview(ras_core, &overview); + + output_data->total_cper_num = overview.logged_batch_count; + output_data->start_cper_id = overview.first_batch_id; + output_data->latest_cper_id = overview.last_batch_id; + + output_data->version = 0; + + cmd->output_size = sizeof(struct ras_cmd_cper_snapshot_rsp); + return RAS_CMD__SUCCESS; +} + +static int ras_cmd_get_cper_records(struct ras_core_context *ras_core, + struct ras_cmd_ioctl *cmd, void *data) +{ + struct ras_cmd_cper_record_req *req = + (struct ras_cmd_cper_record_req *)cmd->input_buff_raw; + struct ras_cmd_cper_record_rsp *rsp = + (struct ras_cmd_cper_record_rsp *)cmd->output_buff_raw; + struct ras_log_info *trace[MAX_RECORD_PER_BATCH] = {0}; + struct ras_log_batch_overview overview; + uint32_t offset = 0, real_data_len = 0; + uint64_t batch_id; + uint8_t *buffer; + int ret = 0, i, count; + + if (cmd->input_size != sizeof(struct ras_cmd_cper_record_req)) + return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + + if (!req->buf_size || !req->buf_ptr || !req->cper_num) + return RAS_CMD__ERROR_INVALID_INPUT_DATA; + + if (!access_ok((void *)req->buf_ptr, req->buf_size)) { + RAS_DEV_ERR(ras_core->dev, "Invalid cper buffer memory!\n"); + return RAS_CMD__ERROR_INVALID_INPUT_DATA; + } + + buffer = kzalloc(req->buf_size, GFP_KERNEL); + if (!buffer) + return RAS_CMD__ERROR_GENERIC; + + ras_log_ring_get_batch_overview(ras_core, &overview); + for (i = 0; i < req->cper_num; i++) { + batch_id = req->cper_start_id + i; + if (batch_id >= overview.last_batch_id) + break; + + count = ras_log_ring_get_batch_records(ras_core, batch_id, trace, + ARRAY_SIZE(trace)); + if (count > 0) { + ret = ras_cper_generate_cper(ras_core, trace, count, + &buffer[offset], req->buf_size - offset, &real_data_len); + if (ret) + break; + + offset += real_data_len; + } + } + + if ((ret && (ret != -ENOMEM)) || + copy_to_user((void *)req->buf_ptr, buffer, offset)) { + kfree(buffer); + return RAS_CMD__ERROR_GENERIC; + } + + rsp->real_data_size = offset; + rsp->real_cper_num = i; + rsp->remain_num = (ret == -ENOMEM) ? (req->cper_num - i) : 0; + rsp->version = 0; + + cmd->output_size = sizeof(struct ras_cmd_cper_record_rsp); + + kfree(buffer); + + return RAS_CMD__SUCCESS; +} + +static int ras_cmd_get_batch_trace_snapshot(struct ras_core_context *ras_core, + struct ras_cmd_ioctl *cmd, void *data) +{ + struct ras_cmd_batch_trace_snapshot_rsp *rsp = + (struct ras_cmd_batch_trace_snapshot_rsp *)cmd->output_buff_raw; + struct ras_log_batch_overview overview; + + + if (cmd->input_size != sizeof(struct ras_cmd_batch_trace_snapshot_req)) + return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + + ras_log_ring_get_batch_overview(ras_core, &overview); + + rsp->total_batch_num = overview.logged_batch_count; + rsp->start_batch_id = overview.first_batch_id; + rsp->latest_batch_id = overview.last_batch_id; + rsp->version = 0; + + cmd->output_size = sizeof(struct ras_cmd_batch_trace_snapshot_rsp); + return RAS_CMD__SUCCESS; +} + +static int ras_cmd_get_batch_trace_records(struct ras_core_context *ras_core, + struct ras_cmd_ioctl *cmd, void *data) +{ + struct ras_cmd_batch_trace_record_req *input_data = + (struct ras_cmd_batch_trace_record_req *)cmd->input_buff_raw; + struct ras_cmd_batch_trace_record_rsp *output_data = + (struct ras_cmd_batch_trace_record_rsp *)cmd->output_buff_raw; + struct ras_log_batch_overview overview; + struct ras_log_info *trace_arry[MAX_RECORD_PER_BATCH] = {0}; + struct ras_log_info *record; + int i, j, count = 0, offset = 0; + uint64_t id; + bool completed = false; + + if (cmd->input_size != sizeof(struct ras_cmd_batch_trace_record_req)) + return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + + if ((!input_data->batch_num) || (input_data->batch_num > RAS_CMD_MAX_BATCH_NUM)) + return RAS_CMD__ERROR_INVALID_INPUT_DATA; + + ras_log_ring_get_batch_overview(ras_core, &overview); + if ((input_data->start_batch_id < overview.first_batch_id) || + (input_data->start_batch_id >= overview.last_batch_id)) + return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + + for (i = 0; i < input_data->batch_num; i++) { + id = input_data->start_batch_id + i; + if (id >= overview.last_batch_id) { + completed = true; + break; + } + + count = ras_log_ring_get_batch_records(ras_core, + id, trace_arry, ARRAY_SIZE(trace_arry)); + if (count > 0) { + if ((offset + count) > RAS_CMD_MAX_TRACE_NUM) + break; + for (j = 0; j < count; j++) { + record = &output_data->records[offset + j]; + record->seqno = trace_arry[j]->seqno; + record->timestamp = trace_arry[j]->timestamp; + record->event = trace_arry[j]->event; + memcpy(&record->aca_reg, + &trace_arry[j]->aca_reg, sizeof(trace_arry[j]->aca_reg)); + } + } else { + count = 0; + } + + output_data->batchs[i].batch_id = id; + output_data->batchs[i].offset = offset; + output_data->batchs[i].trace_num = count; + offset += count; + } + + output_data->start_batch_id = input_data->start_batch_id; + output_data->real_batch_num = i; + output_data->remain_num = completed ? 0 : (input_data->batch_num - i); + output_data->version = 0; + + cmd->output_size = sizeof(struct ras_cmd_batch_trace_record_rsp); + + return RAS_CMD__SUCCESS; +} + +static enum ras_ta_block __get_ras_ta_block(enum ras_block_id block) +{ + switch (block) { + case RAS_BLOCK_ID__UMC: + return RAS_TA_BLOCK__UMC; + case RAS_BLOCK_ID__SDMA: + return RAS_TA_BLOCK__SDMA; + case RAS_BLOCK_ID__GFX: + return RAS_TA_BLOCK__GFX; + case RAS_BLOCK_ID__MMHUB: + return RAS_TA_BLOCK__MMHUB; + case RAS_BLOCK_ID__ATHUB: + return RAS_TA_BLOCK__ATHUB; + case RAS_BLOCK_ID__PCIE_BIF: + return RAS_TA_BLOCK__PCIE_BIF; + case RAS_BLOCK_ID__HDP: + return RAS_TA_BLOCK__HDP; + case RAS_BLOCK_ID__XGMI_WAFL: + return RAS_TA_BLOCK__XGMI_WAFL; + case RAS_BLOCK_ID__DF: + return RAS_TA_BLOCK__DF; + case RAS_BLOCK_ID__SMN: + return RAS_TA_BLOCK__SMN; + case RAS_BLOCK_ID__SEM: + return RAS_TA_BLOCK__SEM; + case RAS_BLOCK_ID__MP0: + return RAS_TA_BLOCK__MP0; + case RAS_BLOCK_ID__MP1: + return RAS_TA_BLOCK__MP1; + case RAS_BLOCK_ID__FUSE: + return RAS_TA_BLOCK__FUSE; + case RAS_BLOCK_ID__MCA: + return RAS_TA_BLOCK__MCA; + case RAS_BLOCK_ID__VCN: + return RAS_TA_BLOCK__VCN; + case RAS_BLOCK_ID__JPEG: + return RAS_TA_BLOCK__JPEG; + default: + return RAS_TA_BLOCK__UMC; + } +} + +static enum ras_ta_error_type __get_ras_ta_err_type(enum ras_ecc_err_type error) +{ + switch (error) { + case RAS_ECC_ERR__NONE: + return RAS_TA_ERROR__NONE; + case RAS_ECC_ERR__PARITY: + return RAS_TA_ERROR__PARITY; + case RAS_ECC_ERR__SINGLE_CORRECTABLE: + return RAS_TA_ERROR__SINGLE_CORRECTABLE; + case RAS_ECC_ERR__MULTI_UNCORRECTABLE: + return RAS_TA_ERROR__MULTI_UNCORRECTABLE; + case RAS_ECC_ERR__POISON: + return RAS_TA_ERROR__POISON; + default: + return RAS_TA_ERROR__NONE; + } +} + +static int ras_cmd_inject_error(struct ras_core_context *ras_core, + struct ras_cmd_ioctl *cmd, void *data) +{ + struct ras_cmd_inject_error_req *req = + (struct ras_cmd_inject_error_req *)cmd->input_buff_raw; + struct ras_cmd_inject_error_rsp *output_data = + (struct ras_cmd_inject_error_rsp *)cmd->output_buff_raw; + int ret = 0; + struct ras_ta_trigger_error_input block_info = { + .block_id = __get_ras_ta_block(req->block_id), + .sub_block_index = req->subblock_id, + .inject_error_type = __get_ras_ta_err_type(req->error_type), + .address = req->address, + .value = req->method, + }; + + ret = ras_psp_trigger_error(ras_core, &block_info, req->instance_mask); + if (!ret) { + output_data->version = 0; + output_data->address = block_info.address; + cmd->output_size = sizeof(struct ras_cmd_inject_error_rsp); + } else { + RAS_DEV_ERR(ras_core->dev, "ras inject block %u failed %d\n", req->block_id, ret); + ret = RAS_CMD__ERROR_ACCESS_DENIED; + } + + return ret; +} + +static struct ras_cmd_func_map ras_cmd_maps[] = { + {RAS_CMD__INJECT_ERROR, ras_cmd_inject_error}, + {RAS_CMD__GET_BLOCK_ECC_STATUS, ras_get_block_ecc_info}, + {RAS_CMD__GET_BAD_PAGES, ras_cmd_get_bad_pages}, + {RAS_CMD__CLEAR_BAD_PAGE_INFO, ras_cmd_clear_bad_page_info}, + {RAS_CMD__RESET_ALL_ERROR_COUNTS, ras_cmd_reset_all_error_counts}, + {RAS_CMD__GET_CPER_SNAPSHOT, ras_cmd_get_cper_snapshot}, + {RAS_CMD__GET_CPER_RECORD, ras_cmd_get_cper_records}, + {RAS_CMD__GET_BATCH_TRACE_SNAPSHOT, ras_cmd_get_batch_trace_snapshot}, + {RAS_CMD__GET_BATCH_TRACE_RECORD, ras_cmd_get_batch_trace_records}, +}; + +int rascore_handle_cmd(struct ras_core_context *ras_core, + struct ras_cmd_ioctl *cmd, void *data) +{ + struct ras_cmd_func_map *ras_cmd = NULL; + int i; + + for (i = 0; i < ARRAY_SIZE(ras_cmd_maps); i++) { + if (cmd->cmd_id == ras_cmd_maps[i].cmd_id) { + ras_cmd = &ras_cmd_maps[i]; + break; + } + } + + if (!ras_cmd) + return RAS_CMD__ERROR_UKNOWN_CMD; + + return ras_cmd->func(ras_core, cmd, data); +} + +int ras_cmd_init(struct ras_core_context *ras_core) +{ + return ras_cmd_add_device(ras_core); +} + +int ras_cmd_fini(struct ras_core_context *ras_core) +{ + ras_cmd_remove_device(ras_core); + return 0; +} + +int ras_cmd_query_interface_info(struct ras_core_context *ras_core, + struct ras_query_interface_info_rsp *rsp) +{ + rsp->ras_cmd_major_ver = RAS_CMD_MAJOR_VERSION; + rsp->ras_cmd_minor_ver = RAS_CMD_MINOR_VERSION; + + return 0; +} + +int ras_cmd_translate_soc_pa_to_bank(struct ras_core_context *ras_core, + uint64_t soc_pa, struct ras_fb_bank_addr *bank_addr) +{ + struct umc_bank_addr umc_bank = {0}; + int ret; + + ret = ras_umc_translate_soc_pa_and_bank(ras_core, &soc_pa, &umc_bank, false); + if (ret) + return RAS_CMD__ERROR_GENERIC; + + bank_addr->stack_id = umc_bank.stack_id; + bank_addr->bank_group = umc_bank.bank_group; + bank_addr->bank = umc_bank.bank; + bank_addr->row = umc_bank.row; + bank_addr->column = umc_bank.column; + bank_addr->channel = umc_bank.channel; + bank_addr->subchannel = umc_bank.subchannel; + + return 0; +} + +int ras_cmd_translate_bank_to_soc_pa(struct ras_core_context *ras_core, + struct ras_fb_bank_addr bank_addr, uint64_t *soc_pa) +{ + struct umc_bank_addr umc_bank = {0}; + + umc_bank.stack_id = bank_addr.stack_id; + umc_bank.bank_group = bank_addr.bank_group; + umc_bank.bank = bank_addr.bank; + umc_bank.row = bank_addr.row; + umc_bank.column = bank_addr.column; + umc_bank.channel = bank_addr.channel; + umc_bank.subchannel = bank_addr.subchannel; + + return ras_umc_translate_soc_pa_and_bank(ras_core, soc_pa, &umc_bank, true); +} + +uint64_t ras_cmd_get_dev_handle(struct ras_core_context *ras_core) +{ + return ras_core->ras_cmd.dev_handle; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h new file mode 100644 index 0000000000000..6df8c70f5ad83 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h @@ -0,0 +1,425 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __RAS_CMD_H__ +#define __RAS_CMD_H__ +#include "ras.h" +#include "ras_eeprom.h" +#include "ras_log_ring.h" +#include "ras_cper.h" + +#define RAS_CMD_DEV_HANDLE_MAGIC 0xFEEDAD00UL + +#define RAS_CMD_MAX_IN_SIZE 256 +#define RAS_CMD_MAX_GPU_NUM 32 +#define RAS_CMD_MAX_BAD_PAGES_PER_GROUP 32 + +/* position of instance value in sub_block_index of + * ta_ras_trigger_error_input, the sub block uses lower 12 bits + */ +#define RAS_TA_INST_MASK 0xfffff000 +#define RAS_TA_INST_SHIFT 0xc + +enum ras_cmd_interface_type { + RAS_CMD_INTERFACE_TYPE_NONE, + RAS_CMD_INTERFACE_TYPE_AMDGPU, + RAS_CMD_INTERFACE_TYPE_VF, + RAS_CMD_INTERFACE_TYPE_PF, +}; + +enum ras_cmd_id_range { + RAS_CMD_ID_COMMON_START = 0, + RAS_CMD_ID_COMMON_END = 0x10000, + RAS_CMD_ID_AMDGPU_START = RAS_CMD_ID_COMMON_END, + RAS_CMD_ID_AMDGPU_END = 0x20000, + RAS_CMD_ID_MXGPU_START = RAS_CMD_ID_AMDGPU_END, + RAS_CMD_ID_MXGPU_END = 0x30000, + RAS_CMD_ID_MXGPU_VF_START = RAS_CMD_ID_MXGPU_END, + RAS_CMD_ID_MXGPU_VF_END = 0x40000, +}; + +enum ras_cmd_id { + RAS_CMD__BEGIN = RAS_CMD_ID_COMMON_START, + RAS_CMD__QUERY_INTERFACE_INFO, + RAS_CMD__GET_DEVICES_INFO, + RAS_CMD__GET_BLOCK_ECC_STATUS, + RAS_CMD__INJECT_ERROR, + RAS_CMD__GET_BAD_PAGES, + RAS_CMD__CLEAR_BAD_PAGE_INFO, + RAS_CMD__RESET_ALL_ERROR_COUNTS, + RAS_CMD__GET_SAFE_FB_ADDRESS_RANGES, + RAS_CMD__TRANSLATE_FB_ADDRESS, + RAS_CMD__GET_LINK_TOPOLOGY, + RAS_CMD__GET_CPER_SNAPSHOT, + RAS_CMD__GET_CPER_RECORD, + RAS_CMD__GET_BATCH_TRACE_SNAPSHOT, + RAS_CMD__GET_BATCH_TRACE_RECORD, + RAS_CMD__SUPPORTED_MAX = RAS_CMD_ID_COMMON_END, +}; + +enum ras_cmd_response { + RAS_CMD__SUCCESS = 0, + RAS_CMD__SUCCESS_EXEED_BUFFER, + RAS_CMD__ERROR_UKNOWN_CMD, + RAS_CMD__ERROR_INVALID_CMD, + RAS_CMD__ERROR_VERSION, + RAS_CMD__ERROR_INVALID_INPUT_SIZE, + RAS_CMD__ERROR_INVALID_INPUT_DATA, + RAS_CMD__ERROR_DRV_INIT_FAIL, + RAS_CMD__ERROR_ACCESS_DENIED, + RAS_CMD__ERROR_GENERIC, + RAS_CMD__ERROR_TIMEOUT, +}; + +enum ras_error_type { + RAS_TYPE_ERROR__NONE = 0, + RAS_TYPE_ERROR__PARITY = 1, + RAS_TYPE_ERROR__SINGLE_CORRECTABLE = 2, + RAS_TYPE_ERROR__MULTI_UNCORRECTABLE = 4, + RAS_TYPE_ERROR__POISON = 8, +}; + +struct ras_core_context; +struct ras_cmd_ioctl; + +struct ras_cmd_mgr { + struct list_head head; + struct ras_core_context *ras_core; + uint64_t dev_handle; +}; + +struct ras_cmd_func_map { + uint32_t cmd_id; + int (*func)(struct ras_core_context *ras_core, + struct ras_cmd_ioctl *cmd, void *data); +}; + +struct ras_device_bdf { + union { + struct { + uint32_t function : 3; + uint32_t device : 5; + uint32_t bus : 8; + uint32_t domain : 16; + }; + uint32_t u32_all; + }; +}; + +struct ras_cmd_param { + uint32_t idx_vf; + void *data; +}; + +#pragma pack(push, 8) +struct ras_cmd_ioctl { + uint32_t magic; + union { + struct { + uint16_t ras_cmd_minor_ver : 10; + uint16_t ras_cmd_major_ver : 6; + }; + uint16_t ras_cmd_ver; + }; + union { + struct { + uint16_t plat_major_ver : 10; + uint16_t plat_minor_ver : 6; + }; + uint16_t plat_ver; + }; + uint32_t cmd_id; + uint32_t cmd_res; + uint32_t input_size; + uint32_t output_size; + uint32_t reserved[6]; + uint8_t input_buff_raw[RAS_CMD_MAX_IN_SIZE]; + uint8_t output_buff_raw[]; +}; + +struct ras_cmd_dev_handle { + uint64_t dev_handle; +}; + +struct ras_cmd_block_ecc_info_req { + struct ras_cmd_dev_handle dev; + uint32_t block_id; + uint32_t subblock_id; + uint32_t reserved[4]; +}; + +struct ras_cmd_block_ecc_info_rsp { + uint32_t version; + uint32_t ce_count; + uint32_t ue_count; + uint32_t de_count; + uint32_t reserved[6]; +}; + +struct ras_cmd_inject_error_req { + struct ras_cmd_dev_handle dev; + uint32_t block_id; + uint32_t subblock_id; + uint64_t address; + uint32_t error_type; + uint32_t instance_mask; + union { + struct { + /* vf index */ + uint64_t vf_idx : 6; + /* method of error injection. i.e persistent, coherent etc */ + uint64_t method : 10; + uint64_t rsv : 48; + }; + uint64_t value; + }; + uint32_t reserved[8]; +}; + +struct ras_cmd_inject_error_rsp { + uint32_t version; + uint32_t reserved[5]; + uint64_t address; +}; + +struct ras_cmd_dev_info { + uint64_t dev_handle; + uint32_t location_id; + uint32_t ecc_enabled; + uint32_t ecc_supported; + uint32_t vf_num; + uint32_t asic_type; + uint32_t oam_id; + uint32_t reserved[8]; +}; + +struct ras_cmd_devices_info_rsp { + uint32_t version; + uint32_t dev_num; + uint32_t reserved[6]; + struct ras_cmd_dev_info devs[RAS_CMD_MAX_GPU_NUM]; +}; + +struct ras_cmd_bad_page_record { + union { + uint64_t address; + uint64_t offset; + }; + uint64_t retired_page; + uint64_t ts; + + uint32_t err_type; + + union { + unsigned char bank; + unsigned char cu; + }; + + unsigned char mem_channel; + unsigned char mcumc_id; + + unsigned char valid; + unsigned char reserved[8]; +}; + +struct ras_cmd_bad_pages_info_req { + struct ras_cmd_dev_handle device; + uint32_t group_index; + uint32_t reserved[5]; +}; + +struct ras_cmd_bad_pages_info_rsp { + uint32_t version; + uint32_t group_index; + uint32_t bp_in_group; + uint32_t bp_total_cnt; + uint32_t reserved[4]; + struct ras_cmd_bad_page_record records[RAS_CMD_MAX_BAD_PAGES_PER_GROUP]; +}; + +struct ras_query_interface_info_req { + uint32_t reserved[8]; +}; + +struct ras_query_interface_info_rsp { + uint32_t version; + uint32_t ras_cmd_major_ver; + uint32_t ras_cmd_minor_ver; + uint32_t plat_major_ver; + uint32_t plat_minor_ver; + uint8_t interface_type; + uint8_t rsv[3]; + uint32_t reserved[8]; +}; + +#define RAS_MAX_NUM_SAFE_RANGES 64 +struct ras_cmd_ras_safe_fb_address_ranges_rsp { + uint32_t version; + uint32_t num_ranges; + uint32_t reserved[4]; + struct { + uint64_t start; + uint64_t size; + uint32_t idx; + uint32_t reserved[3]; + } range[RAS_MAX_NUM_SAFE_RANGES]; +}; + +enum ras_fb_addr_type { + RAS_FB_ADDR_SOC_PHY, /* SPA */ + RAS_FB_ADDR_BANK, + RAS_FB_ADDR_VF_PHY, /* GPA */ + RAS_FB_ADDR_UNKNOWN +}; + +struct ras_fb_bank_addr { + uint32_t stack_id; /* SID */ + uint32_t bank_group; + uint32_t bank; + uint32_t row; + uint32_t column; + uint32_t channel; + uint32_t subchannel; /* Also called Pseudochannel (PC) */ + uint32_t reserved[3]; +}; + +struct ras_fb_vf_phy_addr { + uint32_t vf_idx; + uint32_t reserved; + uint64_t addr; +}; + +union ras_translate_fb_address { + struct ras_fb_bank_addr bank_addr; + uint64_t soc_phy_addr; + struct ras_fb_vf_phy_addr vf_phy_addr; +}; + +struct ras_cmd_translate_fb_address_req { + struct ras_cmd_dev_handle dev; + enum ras_fb_addr_type src_addr_type; + enum ras_fb_addr_type dest_addr_type; + union ras_translate_fb_address trans_addr; +}; + +struct ras_cmd_translate_fb_address_rsp { + uint32_t version; + uint32_t reserved[5]; + union ras_translate_fb_address trans_addr; +}; + +struct ras_dev_link_topology_req { + struct ras_cmd_dev_handle src; + struct ras_cmd_dev_handle dst; +}; + +struct ras_dev_link_topology_rsp { + uint32_t version; + uint32_t link_status; /* HW status of the link */ + uint32_t link_type; /* type of the link */ + uint32_t num_hops; /* number of hops */ + uint32_t reserved[8]; +}; + +struct ras_cmd_cper_snapshot_req { + struct ras_cmd_dev_handle dev; +}; + +struct ras_cmd_cper_snapshot_rsp { + uint32_t version; + uint32_t reserved[4]; + uint32_t total_cper_num; + uint64_t start_cper_id; + uint64_t latest_cper_id; +}; + +struct ras_cmd_cper_record_req { + struct ras_cmd_dev_handle dev; + uint64_t cper_start_id; + uint32_t cper_num; + uint32_t buf_size; + uint64_t buf_ptr; + uint32_t reserved[4]; +}; + +struct ras_cmd_cper_record_rsp { + uint32_t version; + uint32_t real_data_size; + uint32_t real_cper_num; + uint32_t remain_num; + uint32_t reserved[4]; +}; + +struct ras_cmd_batch_trace_snapshot_req { + struct ras_cmd_dev_handle dev; +}; + +struct ras_cmd_batch_trace_snapshot_rsp { + uint32_t version; + uint32_t reserved[4]; + uint32_t total_batch_num; + uint64_t start_batch_id; + uint64_t latest_batch_id; +}; + +struct ras_cmd_batch_trace_record_req { + struct ras_cmd_dev_handle dev; + uint64_t start_batch_id; + uint32_t batch_num; + uint32_t reserved[5]; +}; + +struct batch_ras_trace_info { + uint64_t batch_id; + uint16_t offset; + uint8_t trace_num; + uint8_t rsv; + uint32_t reserved; +}; + +#define RAS_CMD_MAX_BATCH_NUM 300 +#define RAS_CMD_MAX_TRACE_NUM 300 +struct ras_cmd_batch_trace_record_rsp { + uint32_t version; + uint16_t real_batch_num; + uint16_t remain_num; + uint64_t start_batch_id; + uint32_t reserved[2]; + struct batch_ras_trace_info batchs[RAS_CMD_MAX_BATCH_NUM]; + struct ras_log_info records[RAS_CMD_MAX_TRACE_NUM]; +}; + +#pragma pack(pop) + +int ras_cmd_init(struct ras_core_context *ras_core); +int ras_cmd_fini(struct ras_core_context *ras_core); +int rascore_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ioctl *cmd, void *data); +uint64_t ras_cmd_get_dev_handle(struct ras_core_context *ras_core); +int ras_cmd_query_interface_info(struct ras_core_context *ras_core, + struct ras_query_interface_info_rsp *rsp); +int ras_cmd_translate_soc_pa_to_bank(struct ras_core_context *ras_core, + uint64_t soc_pa, struct ras_fb_bank_addr *bank_addr); +int ras_cmd_translate_bank_to_soc_pa(struct ras_core_context *ras_core, + struct ras_fb_bank_addr bank_addr, uint64_t *soc_pa); +#endif From 8401cad0ed5719d5cd6323142a516d83b3d4e7be Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 17:33:58 +0800 Subject: [PATCH 2097/2653] drm/amd/ras: Add thread to handle ras events Add thread to handle ras events. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/ras/rascore/ras_process.c | 315 ++++++++++++++++++ drivers/gpu/drm/amd/ras/rascore/ras_process.h | 53 +++ 2 files changed, 368 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_process.c create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_process.h diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_process.c b/drivers/gpu/drm/amd/ras/rascore/ras_process.c new file mode 100644 index 0000000000000..02f0657f78a39 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_process.c @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "ras.h" +#include "ras_process.h" + +#define RAS_EVENT_FIFO_SIZE (128 * sizeof(struct ras_event_req)) + +#define RAS_POLLING_ECC_TIMEOUT 300 + +static int ras_process_put_event(struct ras_core_context *ras_core, + struct ras_event_req *req) +{ + struct ras_process *ras_proc = &ras_core->ras_proc; + int ret; + + ret = kfifo_in_spinlocked(&ras_proc->event_fifo, + req, sizeof(*req), &ras_proc->fifo_spinlock); + if (!ret) { + RAS_DEV_ERR(ras_core->dev, "Poison message fifo is full!\n"); + return -ENOSPC; + } + + return 0; +} + +static int ras_process_add_reset_gpu_event(struct ras_core_context *ras_core, + uint32_t reset_cause) +{ + struct ras_event_req req = {0}; + + req.reset = reset_cause; + + return ras_process_put_event(ras_core, &req); +} + +static int ras_process_get_event(struct ras_core_context *ras_core, + struct ras_event_req *req) +{ + struct ras_process *ras_proc = &ras_core->ras_proc; + + return kfifo_out_spinlocked(&ras_proc->event_fifo, + req, sizeof(*req), &ras_proc->fifo_spinlock); +} + +static void ras_process_clear_event_fifo(struct ras_core_context *ras_core) +{ + struct ras_event_req req; + int ret; + + do { + ret = ras_process_get_event(ras_core, &req); + } while (ret); +} + +#define AMDGPU_RAS_WAITING_DATA_READY 200 +static int ras_process_umc_event(struct ras_core_context *ras_core, + uint32_t event_count) +{ + struct ras_ecc_count ecc_data; + int ret = 0; + uint32_t timeout = 0; + uint32_t detected_de_count = 0; + + do { + memset(&ecc_data, 0, sizeof(ecc_data)); + ret = ras_core_update_ecc_info(ras_core); + if (ret) + return ret; + + ret = ras_core_query_block_ecc_data(ras_core, RAS_BLOCK_ID__UMC, &ecc_data); + if (ret) + return ret; + + if (ecc_data.new_de_count) { + detected_de_count += ecc_data.new_de_count; + timeout = 0; + } else { + if (!timeout && event_count) + timeout = AMDGPU_RAS_WAITING_DATA_READY; + + if (timeout) { + if (!--timeout) + break; + + msleep(1); + } + } + } while (detected_de_count < event_count); + + if (detected_de_count && ras_core_gpu_is_rma(ras_core)) + ras_process_add_reset_gpu_event(ras_core, GPU_RESET_CAUSE_RMA); + + return 0; +} + +static int ras_process_non_umc_event(struct ras_core_context *ras_core) +{ + struct ras_process *ras_proc = &ras_core->ras_proc; + struct ras_event_req req; + uint32_t event_count = kfifo_len(&ras_proc->event_fifo); + uint32_t reset_flags = 0; + int ret = 0, i; + + for (i = 0; i < event_count; i++) { + memset(&req, 0, sizeof(req)); + ret = ras_process_get_event(ras_core, &req); + if (!ret) + continue; + + ras_core_event_notify(ras_core, + RAS_EVENT_ID__POISON_CONSUMPTION, &req); + + reset_flags |= req.reset; + + if (req.reset == GPU_RESET_CAUSE_RMA) + continue; + + if (req.reset) + RAS_DEV_INFO(ras_core->dev, + "{%llu} GPU reset for %s RAS poison consumption is issued!\n", + req.seqno, ras_core_get_ras_block_name(req.block)); + else + RAS_DEV_INFO(ras_core->dev, + "{%llu} %s RAS poison consumption is issued!\n", + req.seqno, ras_core_get_ras_block_name(req.block)); + } + + if (reset_flags) { + ret = ras_core_event_notify(ras_core, + RAS_EVENT_ID__RESET_GPU, &reset_flags); + if (!ret && (reset_flags & GPU_RESET_CAUSE_RMA)) + return -RAS_CORE_GPU_IN_MODE1_RESET; + } + + return ret; +} + +int ras_process_handle_ras_event(struct ras_core_context *ras_core) +{ + struct ras_process *ras_proc = &ras_core->ras_proc; + uint32_t umc_event_count; + int ret; + + ras_aca_clear_fatal_flag(ras_core); + ras_umc_log_pending_bad_bank(ras_core); + + do { + umc_event_count = atomic_read(&ras_proc->umc_interrupt_count); + ret = ras_process_umc_event(ras_core, umc_event_count); + if (ret == -RAS_CORE_GPU_IN_MODE1_RESET) + break; + + if (umc_event_count) + atomic_sub(umc_event_count, &ras_proc->umc_interrupt_count); + } while (atomic_read(&ras_proc->umc_interrupt_count)); + + if ((ret != -RAS_CORE_GPU_IN_MODE1_RESET) && + (kfifo_len(&ras_proc->event_fifo))) + ret = ras_process_non_umc_event(ras_core); + + if (ret == -RAS_CORE_GPU_IN_MODE1_RESET) { + /* Clear poison fifo */ + ras_process_clear_event_fifo(ras_core); + atomic_set(&ras_proc->umc_interrupt_count, 0); + } + + return ret; +} + +static int thread_wait_condition(void *param) +{ + struct ras_process *ras_proc = (struct ras_process *)param; + + return (kthread_should_stop() || + atomic_read(&ras_proc->ras_interrupt_req)); +} + +static int ras_process_thread(void *context) +{ + struct ras_core_context *ras_core = (struct ras_core_context *)context; + struct ras_process *ras_proc = &ras_core->ras_proc; + + while (!kthread_should_stop()) { + ras_wait_event_interruptible_timeout(&ras_proc->ras_process_wq, + thread_wait_condition, ras_proc, + msecs_to_jiffies(RAS_POLLING_ECC_TIMEOUT)); + + if (kthread_should_stop()) + break; + + if (!ras_core->is_initialized) + continue; + + atomic_set(&ras_proc->ras_interrupt_req, 0); + + if (ras_core_gpu_in_reset(ras_core)) + continue; + + if (ras_core->sys_fn && ras_core->sys_fn->async_handle_ras_event) + ras_core->sys_fn->async_handle_ras_event(ras_core, NULL); + else + ras_process_handle_ras_event(ras_core); + } + + return 0; +} + +int ras_process_init(struct ras_core_context *ras_core) +{ + struct ras_process *ras_proc = &ras_core->ras_proc; + int ret; + + ret = kfifo_alloc(&ras_proc->event_fifo, RAS_EVENT_FIFO_SIZE, GFP_KERNEL); + if (ret) + return ret; + + spin_lock_init(&ras_proc->fifo_spinlock); + + init_waitqueue_head(&ras_proc->ras_process_wq); + + ras_proc->ras_process_thread = kthread_run(ras_process_thread, + (void *)ras_core, "ras_process_thread"); + if (!ras_proc->ras_process_thread) { + RAS_DEV_ERR(ras_core->dev, "Failed to create ras_process_thread.\n"); + ret = -ENOMEM; + goto err; + } + + return 0; + +err: + ras_process_fini(ras_core); + return ret; +} + +int ras_process_fini(struct ras_core_context *ras_core) +{ + struct ras_process *ras_proc = &ras_core->ras_proc; + + if (ras_proc->ras_process_thread) { + kthread_stop(ras_proc->ras_process_thread); + ras_proc->ras_process_thread = NULL; + } + + kfifo_free(&ras_proc->event_fifo); + + return 0; +} + +static int ras_process_add_umc_interrupt_req(struct ras_core_context *ras_core, + struct ras_event_req *req) +{ + struct ras_process *ras_proc = &ras_core->ras_proc; + + atomic_inc(&ras_proc->umc_interrupt_count); + atomic_inc(&ras_proc->ras_interrupt_req); + + wake_up(&ras_proc->ras_process_wq); + return 0; +} + +static int ras_process_add_non_umc_interrupt_req(struct ras_core_context *ras_core, + struct ras_event_req *req) +{ + struct ras_process *ras_proc = &ras_core->ras_proc; + int ret; + + ret = ras_process_put_event(ras_core, req); + if (!ret) { + atomic_inc(&ras_proc->ras_interrupt_req); + wake_up(&ras_proc->ras_process_wq); + } + + return ret; +} + +int ras_process_add_interrupt_req(struct ras_core_context *ras_core, + struct ras_event_req *req, bool is_umc) +{ + int ret; + + if (!ras_core) + return -EINVAL; + + if (!ras_core->is_initialized) + return -EPERM; + + if (is_umc) + ret = ras_process_add_umc_interrupt_req(ras_core, req); + else + ret = ras_process_add_non_umc_interrupt_req(ras_core, req); + + return ret; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_process.h b/drivers/gpu/drm/amd/ras/rascore/ras_process.h new file mode 100644 index 0000000000000..28458b50510e6 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_process.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __RAS_PROCESS_H__ +#define __RAS_PROCESS_H__ + +struct ras_event_req { + uint64_t seqno; + uint32_t idx_vf; + uint32_t block; + uint16_t pasid; + uint32_t reset; + void *pasid_fn; + void *data; +}; + +struct ras_process { + void *dev; + void *ras_process_thread; + wait_queue_head_t ras_process_wq; + atomic_t ras_interrupt_req; + atomic_t umc_interrupt_count; + struct kfifo event_fifo; + spinlock_t fifo_spinlock; +}; + +struct ras_core_context; +int ras_process_init(struct ras_core_context *ras_core); +int ras_process_fini(struct ras_core_context *ras_core); +int ras_process_handle_ras_event(struct ras_core_context *ras_core); +int ras_process_add_interrupt_req(struct ras_core_context *ras_core, + struct ras_event_req *req, bool is_umc); +#endif From 0d5cdd74c2ebd1b91d07cf86b86db359d9eedc9b Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 17:37:35 +0800 Subject: [PATCH 2098/2653] drm/amd/ras: Use ring buffer to record ras ecc data Use ring buffer to record ras ecc data. V3: Change commit message and rename the file and function names. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/ras/rascore/ras_log_ring.c | 310 ++++++++++++++++++ .../gpu/drm/amd/ras/rascore/ras_log_ring.h | 93 ++++++ 2 files changed, 403 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_log_ring.h diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c b/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c new file mode 100644 index 0000000000000..bca094058f91f --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "ras.h" +#include "ras_core_status.h" +#include "ras_log_ring.h" + +#define RAS_LOG_MAX_QUERY_SIZE 0xC000 +#define RAS_LOG_MEM_TEMP_SIZE 0x200 +#define RAS_LOG_MEMPOOL_SIZE \ + (RAS_LOG_MAX_QUERY_SIZE + RAS_LOG_MEM_TEMP_SIZE) + +#define BATCH_IDX_TO_TREE_IDX(batch_idx, sn) (((batch_idx) << 8) | (sn)) + +static const uint64_t ras_rma_aca_reg[ACA_REG_MAX_COUNT] = { + [ACA_REG_IDX__CTL] = 0x1, + [ACA_REG_IDX__STATUS] = 0xB000000000000137, + [ACA_REG_IDX__ADDR] = 0x0, + [ACA_REG_IDX__MISC0] = 0x0, + [ACA_REG_IDX__CONFG] = 0x1ff00000002, + [ACA_REG_IDX__IPID] = 0x9600000000, + [ACA_REG_IDX__SYND] = 0x0, +}; + +static uint64_t ras_log_ring_get_logged_ecc_count(struct ras_core_context *ras_core) +{ + struct ras_log_ring *log_ring = &ras_core->ras_log_ring; + uint64_t count = 0; + + if (log_ring->logged_ecc_count < 0) { + RAS_DEV_WARN(ras_core->dev, + "Error: the logged ras count should not less than 0!\n"); + count = 0; + } else { + count = log_ring->logged_ecc_count; + } + + if (count > RAS_LOG_MEMPOOL_SIZE) + RAS_DEV_WARN(ras_core->dev, + "Error: the logged ras count is out of range!\n"); + + return count; +} + +static int ras_log_ring_add_data(struct ras_core_context *ras_core, + struct ras_log_info *log, struct ras_log_batch_tag *batch_tag) +{ + struct ras_log_ring *log_ring = &ras_core->ras_log_ring; + unsigned long flags = 0; + int ret; + + if (batch_tag && (batch_tag->sub_seqno >= MAX_RECORD_PER_BATCH)) { + RAS_DEV_ERR(ras_core->dev, + "Invalid batch sub seqno:%d, batch:0x%llx\n", + batch_tag->sub_seqno, batch_tag->batch_id); + return -EINVAL; + } + + spin_lock_irqsave(&log_ring->spin_lock, flags); + if (batch_tag) { + log->seqno = + BATCH_IDX_TO_TREE_IDX(batch_tag->batch_id, batch_tag->sub_seqno); + batch_tag->sub_seqno++; + } else { + log->seqno = BATCH_IDX_TO_TREE_IDX(log_ring->mono_upward_batch_id, 0); + log_ring->mono_upward_batch_id++; + } + ret = radix_tree_insert(&log_ring->ras_log_root, log->seqno, log); + if (!ret) + log_ring->logged_ecc_count++; + spin_unlock_irqrestore(&log_ring->spin_lock, flags); + + if (ret) { + RAS_DEV_ERR(ras_core->dev, + "Failed to add ras log! seqno:0x%llx, ret:%d\n", + log->seqno, ret); + mempool_free(log, log_ring->ras_log_mempool); + } + + return ret; +} + +static int ras_log_ring_delete_data(struct ras_core_context *ras_core, uint32_t count) +{ + struct ras_log_ring *log_ring = &ras_core->ras_log_ring; + unsigned long flags = 0; + uint32_t i = 0, j = 0; + uint64_t batch_id, idx; + void *data; + int ret = -ENODATA; + + if (count > ras_log_ring_get_logged_ecc_count(ras_core)) + return -EINVAL; + + spin_lock_irqsave(&log_ring->spin_lock, flags); + batch_id = log_ring->last_del_batch_id; + while (batch_id < log_ring->mono_upward_batch_id) { + for (j = 0; j < MAX_RECORD_PER_BATCH; j++) { + idx = BATCH_IDX_TO_TREE_IDX(batch_id, j); + data = radix_tree_delete(&log_ring->ras_log_root, idx); + if (data) { + mempool_free(data, log_ring->ras_log_mempool); + log_ring->logged_ecc_count--; + i++; + } + } + batch_id = ++log_ring->last_del_batch_id; + if (i >= count) { + ret = 0; + break; + } + } + spin_unlock_irqrestore(&log_ring->spin_lock, flags); + + return ret; +} + +static void ras_log_ring_clear_log_tree(struct ras_core_context *ras_core) +{ + struct ras_log_ring *log_ring = &ras_core->ras_log_ring; + uint64_t batch_id, idx; + unsigned long flags = 0; + void *data; + int j; + + if ((log_ring->mono_upward_batch_id <= log_ring->last_del_batch_id) && + !log_ring->logged_ecc_count) + return; + + spin_lock_irqsave(&log_ring->spin_lock, flags); + batch_id = log_ring->last_del_batch_id; + while (batch_id < log_ring->mono_upward_batch_id) { + for (j = 0; j < MAX_RECORD_PER_BATCH; j++) { + idx = BATCH_IDX_TO_TREE_IDX(batch_id, j); + data = radix_tree_delete(&log_ring->ras_log_root, idx); + if (data) { + mempool_free(data, log_ring->ras_log_mempool); + log_ring->logged_ecc_count--; + } + } + batch_id++; + } + spin_unlock_irqrestore(&log_ring->spin_lock, flags); + +} + +int ras_log_ring_sw_init(struct ras_core_context *ras_core) +{ + struct ras_log_ring *log_ring = &ras_core->ras_log_ring; + + memset(log_ring, 0, sizeof(*log_ring)); + + log_ring->ras_log_mempool = mempool_create_kmalloc_pool( + RAS_LOG_MEMPOOL_SIZE, sizeof(struct ras_log_info)); + if (!log_ring->ras_log_mempool) + return -ENOMEM; + + INIT_RADIX_TREE(&log_ring->ras_log_root, GFP_KERNEL); + + spin_lock_init(&log_ring->spin_lock); + + return 0; +} + +int ras_log_ring_sw_fini(struct ras_core_context *ras_core) +{ + struct ras_log_ring *log_ring = &ras_core->ras_log_ring; + + ras_log_ring_clear_log_tree(ras_core); + log_ring->logged_ecc_count = 0; + log_ring->last_del_batch_id = 0; + log_ring->mono_upward_batch_id = 0; + + mempool_destroy(log_ring->ras_log_mempool); + + return 0; +} + +struct ras_log_batch_tag *ras_log_ring_create_batch_tag(struct ras_core_context *ras_core) +{ + struct ras_log_ring *log_ring = &ras_core->ras_log_ring; + struct ras_log_batch_tag *batch_tag; + unsigned long flags; + + batch_tag = kzalloc(sizeof(*batch_tag), GFP_KERNEL); + if (!batch_tag) + return NULL; + + spin_lock_irqsave(&log_ring->spin_lock, flags); + batch_tag->batch_id = log_ring->mono_upward_batch_id; + log_ring->mono_upward_batch_id++; + spin_unlock_irqrestore(&log_ring->spin_lock, flags); + + batch_tag->sub_seqno = 0; + batch_tag->timestamp = ras_core_get_utc_second_timestamp(ras_core); + return batch_tag; +} + +void ras_log_ring_destroy_batch_tag(struct ras_core_context *ras_core, + struct ras_log_batch_tag *batch_tag) +{ + kfree(batch_tag); +} + +void ras_log_ring_add_log_event(struct ras_core_context *ras_core, + enum ras_log_event event, void *data, struct ras_log_batch_tag *batch_tag) +{ + struct ras_log_ring *log_ring = &ras_core->ras_log_ring; + struct ras_log_info *log; + void *obj; + + obj = mempool_alloc_preallocated(log_ring->ras_log_mempool); + if (!obj || + (ras_log_ring_get_logged_ecc_count(ras_core) >= RAS_LOG_MEMPOOL_SIZE)) { + ras_log_ring_delete_data(ras_core, RAS_LOG_MEM_TEMP_SIZE); + if (!obj) + obj = mempool_alloc_preallocated(log_ring->ras_log_mempool); + } + + if (!obj) { + RAS_DEV_ERR(ras_core->dev, "ERROR: Failed to alloc ras log buffer!\n"); + return; + } + + log = (struct ras_log_info *)obj; + + memset(log, 0, sizeof(*log)); + log->timestamp = + batch_tag ? batch_tag->timestamp : ras_core_get_utc_second_timestamp(ras_core); + log->event = event; + + if (data) + memcpy(&log->aca_reg, data, sizeof(log->aca_reg)); + + if (event == RAS_LOG_EVENT_RMA) + memcpy(&log->aca_reg, ras_rma_aca_reg, sizeof(log->aca_reg)); + + ras_log_ring_add_data(ras_core, log, batch_tag); +} + +static struct ras_log_info *ras_log_ring_lookup_data(struct ras_core_context *ras_core, + uint64_t idx) +{ + struct ras_log_ring *log_ring = &ras_core->ras_log_ring; + unsigned long flags = 0; + void *data; + + spin_lock_irqsave(&log_ring->spin_lock, flags); + data = radix_tree_lookup(&log_ring->ras_log_root, idx); + spin_unlock_irqrestore(&log_ring->spin_lock, flags); + + return (struct ras_log_info *)data; +} + +int ras_log_ring_get_batch_records(struct ras_core_context *ras_core, uint64_t batch_id, + struct ras_log_info **log_arr, uint32_t arr_num) +{ + struct ras_log_ring *log_ring = &ras_core->ras_log_ring; + uint32_t i, idx, count = 0; + void *data; + + if ((batch_id >= log_ring->mono_upward_batch_id) || + (batch_id < log_ring->last_del_batch_id)) + return -EINVAL; + + for (i = 0; i < MAX_RECORD_PER_BATCH; i++) { + idx = BATCH_IDX_TO_TREE_IDX(batch_id, i); + data = ras_log_ring_lookup_data(ras_core, idx); + if (data) { + log_arr[count++] = data; + if (count >= arr_num) + break; + } + } + + return count; +} + +int ras_log_ring_get_batch_overview(struct ras_core_context *ras_core, + struct ras_log_batch_overview *overview) +{ + struct ras_log_ring *log_ring = &ras_core->ras_log_ring; + + overview->logged_batch_count = + log_ring->mono_upward_batch_id - log_ring->last_del_batch_id; + overview->last_batch_id = log_ring->mono_upward_batch_id; + overview->first_batch_id = log_ring->last_del_batch_id; + + return 0; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.h b/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.h new file mode 100644 index 0000000000000..0ff6cc35678dd --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __RAS_LOG_RING_H__ +#define __RAS_LOG_RING_H__ +#include "ras_aca.h" + +#define MAX_RECORD_PER_BATCH 32 + +#define RAS_LOG_SEQNO_TO_BATCH_IDX(seqno) ((seqno) >> 8) + +enum ras_log_event { + RAS_LOG_EVENT_NONE, + RAS_LOG_EVENT_UE, + RAS_LOG_EVENT_DE, + RAS_LOG_EVENT_CE, + RAS_LOG_EVENT_POISON_CREATION, + RAS_LOG_EVENT_POISON_CONSUMPTION, + RAS_LOG_EVENT_RMA, + RAS_LOG_EVENT_COUNT_MAX, +}; + +struct ras_aca_reg { + uint64_t regs[ACA_REG_MAX_COUNT]; +}; + +struct ras_log_info { + uint64_t seqno; + uint64_t timestamp; + enum ras_log_event event; + union { + struct ras_aca_reg aca_reg; + }; +}; + +struct ras_log_batch_tag { + uint64_t batch_id; + uint64_t timestamp; + uint32_t sub_seqno; +}; + +struct ras_log_ring { + void *ras_log_mempool; + struct radix_tree_root ras_log_root; + spinlock_t spin_lock; + uint64_t mono_upward_batch_id; + uint64_t last_del_batch_id; + int logged_ecc_count; +}; + +struct ras_log_batch_overview { + uint64_t first_batch_id; + uint64_t last_batch_id; + uint32_t logged_batch_count; +}; + +struct ras_core_context; + +int ras_log_ring_sw_init(struct ras_core_context *ras_core); +int ras_log_ring_sw_fini(struct ras_core_context *ras_core); + +struct ras_log_batch_tag *ras_log_ring_create_batch_tag(struct ras_core_context *ras_core); +void ras_log_ring_destroy_batch_tag(struct ras_core_context *ras_core, + struct ras_log_batch_tag *tag); +void ras_log_ring_add_log_event(struct ras_core_context *ras_core, + enum ras_log_event event, void *data, struct ras_log_batch_tag *tag); + +int ras_log_ring_get_batch_records(struct ras_core_context *ras_core, uint64_t batch_idx, + struct ras_log_info **log_arr, uint32_t arr_num); + +int ras_log_ring_get_batch_overview(struct ras_core_context *ras_core, + struct ras_log_batch_overview *overview); +#endif From a12b995f801a456bcba7fd7a7997bd022ed137db Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 17:42:17 +0800 Subject: [PATCH 2099/2653] drm/amd/ras: Add cper conversion function Add cper conversion function. V3: Change commit message and update the calling function. Signed-off-by: YiPeng Chai Signed-off-by: Xiang Liu Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/ras/rascore/ras_cper.c | 310 +++++++++++++++++++++ drivers/gpu/drm/amd/ras/rascore/ras_cper.h | 304 ++++++++++++++++++++ 2 files changed, 614 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_cper.c create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_cper.h diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cper.c b/drivers/gpu/drm/amd/ras/rascore/ras_cper.c new file mode 100644 index 0000000000000..2343991adccf3 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cper.c @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "ras.h" +#include "ras_core_status.h" +#include "ras_log_ring.h" +#include "ras_cper.h" + +static const struct ras_cper_guid MCE = CPER_NOTIFY__MCE; +static const struct ras_cper_guid CMC = CPER_NOTIFY__CMC; +static const struct ras_cper_guid BOOT = BOOT__TYPE; + +static const struct ras_cper_guid CRASHDUMP = GPU__CRASHDUMP; +static const struct ras_cper_guid RUNTIME = GPU__NONSTANDARD_ERROR; + +static void cper_get_timestamp(struct ras_core_context *ras_core, + struct ras_cper_timestamp *timestamp, uint64_t utc_second_timestamp) +{ + struct ras_time tm = {0}; + + ras_core_convert_timestamp_to_time(ras_core, utc_second_timestamp, &tm); + timestamp->seconds = tm.tm_sec; + timestamp->minutes = tm.tm_min; + timestamp->hours = tm.tm_hour; + timestamp->flag = 0; + timestamp->day = tm.tm_mday; + timestamp->month = tm.tm_mon; + timestamp->year = tm.tm_year % 100; + timestamp->century = tm.tm_year / 100; +} + +static void fill_section_hdr(struct ras_core_context *ras_core, + struct cper_section_hdr *hdr, enum ras_cper_type type, + enum ras_cper_severity sev, struct ras_log_info *trace) +{ + struct device_system_info dev_info = {0}; + char record_id[16]; + + hdr->signature[0] = 'C'; + hdr->signature[1] = 'P'; + hdr->signature[2] = 'E'; + hdr->signature[3] = 'R'; + hdr->revision = CPER_HDR__REV_1; + hdr->signature_end = 0xFFFFFFFF; + hdr->error_severity = sev; + + hdr->valid_bits.platform_id = 1; + hdr->valid_bits.partition_id = 1; + hdr->valid_bits.timestamp = 1; + + ras_core_get_device_system_info(ras_core, &dev_info); + + cper_get_timestamp(ras_core, &hdr->timestamp, trace->timestamp); + + snprintf(record_id, 9, "%d:%llX", dev_info.socket_id, + RAS_LOG_SEQNO_TO_BATCH_IDX(trace->seqno)); + memcpy(hdr->record_id, record_id, 8); + + snprintf(hdr->platform_id, 16, "0x%04X:0x%04X", + dev_info.vendor_id, dev_info.device_id); + /* pmfw version should be part of creator_id according to CPER spec */ + snprintf(hdr->creator_id, 16, "%s", CPER_CREATOR_ID__AMDGPU); + + switch (type) { + case RAS_CPER_TYPE_BOOT: + hdr->notify_type = BOOT; + break; + case RAS_CPER_TYPE_FATAL: + case RAS_CPER_TYPE_RMA: + hdr->notify_type = MCE; + break; + case RAS_CPER_TYPE_RUNTIME: + if (sev == RAS_CPER_SEV_NON_FATAL_CE) + hdr->notify_type = CMC; + else + hdr->notify_type = MCE; + break; + default: + RAS_DEV_ERR(ras_core->dev, "Unknown CPER Type\n"); + break; + } +} + +static int fill_section_descriptor(struct ras_core_context *ras_core, + struct cper_section_descriptor *descriptor, + enum ras_cper_severity sev, + struct ras_cper_guid sec_type, + uint32_t section_offset, + uint32_t section_length) +{ + struct device_system_info dev_info = {0}; + + descriptor->revision_minor = CPER_SEC__MINOR_REV_1; + descriptor->revision_major = CPER_SEC__MAJOR_REV_22; + descriptor->sec_offset = section_offset; + descriptor->sec_length = section_length; + descriptor->valid_bits.fru_text = 1; + descriptor->flag_bits.primary = 1; + descriptor->severity = sev; + descriptor->sec_type = sec_type; + + ras_core_get_device_system_info(ras_core, &dev_info); + + snprintf(descriptor->fru_text, 20, "OAM%d", dev_info.socket_id); + + if (sev == RAS_CPER_SEV_RMA) + descriptor->flag_bits.exceed_err_threshold = 1; + + if (sev == RAS_CPER_SEV_NON_FATAL_UE) + descriptor->flag_bits.latent_err = 1; + + return 0; +} + +static int fill_section_fatal(struct ras_core_context *ras_core, + struct cper_section_fatal *fatal, struct ras_log_info *trace) +{ + fatal->data.reg_ctx_type = CPER_CTX_TYPE__CRASH; + fatal->data.reg_arr_size = sizeof(fatal->data.reg); + + fatal->data.reg.status = trace->aca_reg.regs[RAS_CPER_ACA_REG_STATUS]; + fatal->data.reg.addr = trace->aca_reg.regs[RAS_CPER_ACA_REG_ADDR]; + fatal->data.reg.ipid = trace->aca_reg.regs[RAS_CPER_ACA_REG_IPID]; + fatal->data.reg.synd = trace->aca_reg.regs[RAS_CPER_ACA_REG_SYND]; + + return 0; +} + +static int fill_section_runtime(struct ras_core_context *ras_core, + struct cper_section_runtime *runtime, struct ras_log_info *trace) +{ + runtime->hdr.valid_bits.err_info_cnt = 1; + runtime->hdr.valid_bits.err_context_cnt = 1; + + runtime->descriptor.error_type = RUNTIME; + runtime->descriptor.ms_chk_bits.err_type_valid = 1; + + runtime->reg.reg_ctx_type = CPER_CTX_TYPE__CRASH; + runtime->reg.reg_arr_size = sizeof(runtime->reg.reg_dump); + + runtime->reg.reg_dump[RAS_CPER_ACA_REG_CTL] = trace->aca_reg.regs[ACA_REG_IDX__CTL]; + runtime->reg.reg_dump[RAS_CPER_ACA_REG_STATUS] = trace->aca_reg.regs[ACA_REG_IDX__STATUS]; + runtime->reg.reg_dump[RAS_CPER_ACA_REG_ADDR] = trace->aca_reg.regs[ACA_REG_IDX__ADDR]; + runtime->reg.reg_dump[RAS_CPER_ACA_REG_MISC0] = trace->aca_reg.regs[ACA_REG_IDX__MISC0]; + runtime->reg.reg_dump[RAS_CPER_ACA_REG_CONFIG] = trace->aca_reg.regs[ACA_REG_IDX__CONFG]; + runtime->reg.reg_dump[RAS_CPER_ACA_REG_IPID] = trace->aca_reg.regs[ACA_REG_IDX__IPID]; + runtime->reg.reg_dump[RAS_CPER_ACA_REG_SYND] = trace->aca_reg.regs[ACA_REG_IDX__SYND]; + + return 0; +} + +static int cper_generate_runtime_record(struct ras_core_context *ras_core, + struct cper_section_hdr *hdr, struct ras_log_info **trace_arr, uint32_t arr_num, + enum ras_cper_severity sev) +{ + struct cper_section_descriptor *descriptor; + struct cper_section_runtime *runtime; + int i; + + fill_section_hdr(ras_core, hdr, RAS_CPER_TYPE_RUNTIME, sev, trace_arr[0]); + hdr->record_length = RAS_HDR_LEN + ((RAS_SEC_DESC_LEN + RAS_NONSTD_SEC_LEN) * arr_num); + hdr->sec_cnt = arr_num; + for (i = 0; i < arr_num; i++) { + descriptor = (struct cper_section_descriptor *)((uint8_t *)hdr + + RAS_SEC_DESC_OFFSET(i)); + runtime = (struct cper_section_runtime *)((uint8_t *)hdr + + RAS_NONSTD_SEC_OFFSET(hdr->sec_cnt, i)); + + fill_section_descriptor(ras_core, descriptor, sev, RUNTIME, + RAS_NONSTD_SEC_OFFSET(hdr->sec_cnt, i), + sizeof(struct cper_section_runtime)); + fill_section_runtime(ras_core, runtime, trace_arr[i]); + } + + return 0; +} + +static int cper_generate_fatal_record(struct ras_core_context *ras_core, + uint8_t *buffer, struct ras_log_info **trace_arr, uint32_t arr_num) +{ + struct ras_cper_fatal_record record = {0}; + int i = 0; + + for (i = 0; i < arr_num; i++) { + fill_section_hdr(ras_core, &record.hdr, RAS_CPER_TYPE_FATAL, + RAS_CPER_SEV_FATAL_UE, trace_arr[i]); + record.hdr.record_length = RAS_HDR_LEN + RAS_SEC_DESC_LEN + RAS_FATAL_SEC_LEN; + record.hdr.sec_cnt = 1; + + fill_section_descriptor(ras_core, &record.descriptor, RAS_CPER_SEV_FATAL_UE, + CRASHDUMP, offsetof(struct ras_cper_fatal_record, fatal), + sizeof(struct cper_section_fatal)); + + fill_section_fatal(ras_core, &record.fatal, trace_arr[i]); + + memcpy(buffer + (i * record.hdr.record_length), + &record, record.hdr.record_length); + } + + return 0; +} + +static int cper_get_record_size(enum ras_cper_type type, uint16_t section_count) +{ + int size = 0; + + size += RAS_HDR_LEN; + size += (RAS_SEC_DESC_LEN * section_count); + + switch (type) { + case RAS_CPER_TYPE_RUNTIME: + case RAS_CPER_TYPE_RMA: + size += (RAS_NONSTD_SEC_LEN * section_count); + break; + case RAS_CPER_TYPE_FATAL: + size += (RAS_FATAL_SEC_LEN * section_count); + size += (RAS_HDR_LEN * (section_count - 1)); + break; + case RAS_CPER_TYPE_BOOT: + size += (RAS_BOOT_SEC_LEN * section_count); + break; + default: + /* should never reach here */ + break; + } + + return size; +} + +static enum ras_cper_type cper_ras_log_event_to_cper_type(enum ras_log_event event) +{ + switch (event) { + case RAS_LOG_EVENT_UE: + return RAS_CPER_TYPE_FATAL; + case RAS_LOG_EVENT_DE: + case RAS_LOG_EVENT_CE: + case RAS_LOG_EVENT_POISON_CREATION: + case RAS_LOG_EVENT_POISON_CONSUMPTION: + return RAS_CPER_TYPE_RUNTIME; + case RAS_LOG_EVENT_RMA: + return RAS_CPER_TYPE_RMA; + default: + /* should never reach here */ + return RAS_CPER_TYPE_RUNTIME; + } +} + +int ras_cper_generate_cper(struct ras_core_context *ras_core, + struct ras_log_info **trace_list, uint32_t count, + uint8_t *buf, uint32_t buf_len, uint32_t *real_data_len) +{ + uint8_t *buffer = buf; + uint64_t buf_size = buf_len; + int record_size, saved_size = 0; + struct cper_section_hdr *hdr; + + /* All the batch traces share the same event */ + record_size = cper_get_record_size( + cper_ras_log_event_to_cper_type(trace_list[0]->event), count); + + if ((record_size + saved_size) > buf_size) + return -ENOMEM; + + hdr = (struct cper_section_hdr *)(buffer + saved_size); + + switch (trace_list[0]->event) { + case RAS_LOG_EVENT_RMA: + cper_generate_runtime_record(ras_core, hdr, trace_list, count, RAS_CPER_SEV_RMA); + break; + case RAS_LOG_EVENT_DE: + cper_generate_runtime_record(ras_core, + hdr, trace_list, count, RAS_CPER_SEV_NON_FATAL_UE); + break; + case RAS_LOG_EVENT_CE: + cper_generate_runtime_record(ras_core, + hdr, trace_list, count, RAS_CPER_SEV_NON_FATAL_CE); + break; + case RAS_LOG_EVENT_UE: + cper_generate_fatal_record(ras_core, buffer + saved_size, trace_list, count); + break; + default: + RAS_DEV_WARN(ras_core->dev, "Unprocessed trace event: %d\n", trace_list[0]->event); + break; + } + + saved_size += record_size; + + *real_data_len = saved_size; + return 0; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cper.h b/drivers/gpu/drm/amd/ras/rascore/ras_cper.h new file mode 100644 index 0000000000000..076c1883c1ce4 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cper.h @@ -0,0 +1,304 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __RAS_CPER_H__ +#define __RAS_CPER_H__ + +#define CPER_UUID_MAX_SIZE 16 +struct ras_cper_guid { + uint8_t b[CPER_UUID_MAX_SIZE]; +}; + +#define CPER_GUID__INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ + ((struct ras_cper_guid) \ + {{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \ + (b) & 0xff, ((b) >> 8) & 0xff, \ + (c) & 0xff, ((c) >> 8) & 0xff, \ + (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }}) + +#define CPER_HDR__REV_1 (0x100) +#define CPER_SEC__MINOR_REV_1 (0x01) +#define CPER_SEC__MAJOR_REV_22 (0x22) +#define CPER_OAM_MAX_COUNT (8) + +#define CPER_CTX_TYPE__CRASH (1) +#define CPER_CTX_TYPE__BOOT (9) + +#define CPER_CREATOR_ID__AMDGPU "amdgpu" + +#define CPER_NOTIFY__MCE \ + CPER_GUID__INIT(0xE8F56FFE, 0x919C, 0x4cc5, 0xBA, 0x88, 0x65, 0xAB, \ + 0xE1, 0x49, 0x13, 0xBB) +#define CPER_NOTIFY__CMC \ + CPER_GUID__INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4, \ + 0xEB, 0xD4, 0xF8, 0x90) +#define BOOT__TYPE \ + CPER_GUID__INIT(0x3D61A466, 0xAB40, 0x409a, 0xA6, 0x98, 0xF3, 0x62, \ + 0xD4, 0x64, 0xB3, 0x8F) + +#define GPU__CRASHDUMP \ + CPER_GUID__INIT(0x32AC0C78, 0x2623, 0x48F6, 0xB0, 0xD0, 0x73, 0x65, \ + 0x72, 0x5F, 0xD6, 0xAE) +#define GPU__NONSTANDARD_ERROR \ + CPER_GUID__INIT(0x32AC0C78, 0x2623, 0x48F6, 0x81, 0xA2, 0xAC, 0x69, \ + 0x17, 0x80, 0x55, 0x1D) +#define PROC_ERR__SECTION_TYPE \ + CPER_GUID__INIT(0xDC3EA0B0, 0xA144, 0x4797, 0xB9, 0x5B, 0x53, 0xFA, \ + 0x24, 0x2B, 0x6E, 0x1D) + +enum ras_cper_type { + RAS_CPER_TYPE_RUNTIME, + RAS_CPER_TYPE_FATAL, + RAS_CPER_TYPE_BOOT, + RAS_CPER_TYPE_RMA, +}; + +enum ras_cper_severity { + RAS_CPER_SEV_NON_FATAL_UE = 0, + RAS_CPER_SEV_FATAL_UE = 1, + RAS_CPER_SEV_NON_FATAL_CE = 2, + RAS_CPER_SEV_RMA = 3, + + RAS_CPER_SEV_UNUSED = 10, +}; + +enum ras_cper_aca_reg { + RAS_CPER_ACA_REG_CTL = 0, + RAS_CPER_ACA_REG_STATUS = 1, + RAS_CPER_ACA_REG_ADDR = 2, + RAS_CPER_ACA_REG_MISC0 = 3, + RAS_CPER_ACA_REG_CONFIG = 4, + RAS_CPER_ACA_REG_IPID = 5, + RAS_CPER_ACA_REG_SYND = 6, + RAS_CPER_ACA_REG_DESTAT = 8, + RAS_CPER_ACA_REG_DEADDR = 9, + RAS_CPER_ACA_REG_MASK = 10, + + RAS_CPER_ACA_REG_COUNT = 16, +}; + +#pragma pack(push, 1) + +struct ras_cper_timestamp { + uint8_t seconds; + uint8_t minutes; + uint8_t hours; + uint8_t flag; + uint8_t day; + uint8_t month; + uint8_t year; + uint8_t century; +}; + +struct cper_section_hdr { + char signature[4]; /* "CPER" */ + uint16_t revision; + uint32_t signature_end; /* 0xFFFFFFFF */ + uint16_t sec_cnt; + enum ras_cper_severity error_severity; + union { + struct { + uint32_t platform_id : 1; + uint32_t timestamp : 1; + uint32_t partition_id : 1; + uint32_t reserved : 29; + } valid_bits; + uint32_t valid_mask; + }; + uint32_t record_length; /* Total size of CPER Entry */ + struct ras_cper_timestamp timestamp; + char platform_id[16]; + struct ras_cper_guid partition_id; /* Reserved */ + char creator_id[16]; + struct ras_cper_guid notify_type; /* CMC, MCE */ + char record_id[8]; /* Unique CPER Entry ID */ + uint32_t flags; /* Reserved */ + uint64_t persistence_info; /* Reserved */ + uint8_t reserved[12]; /* Reserved */ +}; + +struct cper_section_descriptor { + uint32_t sec_offset; /* Offset from the start of CPER entry */ + uint32_t sec_length; + uint8_t revision_minor; /* CPER_SEC_MINOR_REV_1 */ + uint8_t revision_major; /* CPER_SEC_MAJOR_REV_22 */ + union { + struct { + uint8_t fru_id : 1; + uint8_t fru_text : 1; + uint8_t reserved : 6; + } valid_bits; + uint8_t valid_mask; + }; + uint8_t reserved; + union { + struct { + uint32_t primary : 1; + uint32_t reserved1 : 2; + uint32_t exceed_err_threshold : 1; + uint32_t latent_err : 1; + uint32_t reserved2 : 27; + } flag_bits; + uint32_t flag_mask; + }; + struct ras_cper_guid sec_type; + char fru_id[16]; + enum ras_cper_severity severity; + char fru_text[20]; +}; + +struct runtime_hdr { + union { + struct { + uint64_t apic_id : 1; + uint64_t fw_id : 1; + uint64_t err_info_cnt : 6; + uint64_t err_context_cnt : 6; + } valid_bits; + uint64_t valid_mask; + }; + uint64_t apic_id; + char fw_id[48]; +}; + +struct runtime_descriptor { + struct ras_cper_guid error_type; + union { + struct { + uint64_t ms_chk : 1; + uint64_t target_addr_id : 1; + uint64_t req_id : 1; + uint64_t resp_id : 1; + uint64_t instr_ptr : 1; + uint64_t reserved : 59; + } valid_bits; + uint64_t valid_mask; + }; + union { + struct { + uint64_t err_type_valid : 1; + uint64_t pcc_valid : 1; + uint64_t uncorr_valid : 1; + uint64_t precise_ip_valid : 1; + uint64_t restartable_ip_valid : 1; + uint64_t overflow_valid : 1; + uint64_t reserved1 : 10; + uint64_t err_type : 2; + uint64_t pcc : 1; + uint64_t uncorr : 1; + uint64_t precised_ip : 1; + uint64_t restartable_ip : 1; + uint64_t overflow : 1; + uint64_t reserved2 : 41; + } ms_chk_bits; + uint64_t ms_chk_mask; + }; + uint64_t target_addr_id; + uint64_t req_id; + uint64_t resp_id; + uint64_t instr_ptr; +}; + +struct runtime_error_reg { + uint16_t reg_ctx_type; + uint16_t reg_arr_size; + uint32_t msr_addr; + uint64_t mm_reg_addr; + uint64_t reg_dump[RAS_CPER_ACA_REG_COUNT]; +}; + +struct cper_section_runtime { + struct runtime_hdr hdr; + struct runtime_descriptor descriptor; + struct runtime_error_reg reg; +}; + +struct crashdump_hdr { + uint64_t reserved1; + uint64_t reserved2; + char fw_id[48]; + uint64_t reserved3[8]; +}; + +struct fatal_reg_info { + uint64_t status; + uint64_t addr; + uint64_t ipid; + uint64_t synd; +}; + +struct crashdump_fatal { + uint16_t reg_ctx_type; + uint16_t reg_arr_size; + uint32_t reserved1; + uint64_t reserved2; + struct fatal_reg_info reg; +}; + +struct crashdump_boot { + uint16_t reg_ctx_type; + uint16_t reg_arr_size; + uint32_t reserved1; + uint64_t reserved2; + uint64_t msg[CPER_OAM_MAX_COUNT]; +}; + +struct cper_section_fatal { + struct crashdump_hdr hdr; + struct crashdump_fatal data; +}; + +struct cper_section_boot { + struct crashdump_hdr hdr; + struct crashdump_boot data; +}; + +struct ras_cper_fatal_record { + struct cper_section_hdr hdr; + struct cper_section_descriptor descriptor; + struct cper_section_fatal fatal; +}; +#pragma pack(pop) + +#define RAS_HDR_LEN (sizeof(struct cper_section_hdr)) +#define RAS_SEC_DESC_LEN (sizeof(struct cper_sec_desc)) + +#define RAS_BOOT_SEC_LEN (sizeof(struct cper_sec_crashdump_boot)) +#define RAS_FATAL_SEC_LEN (sizeof(struct cper_sec_crashdump_fatal)) +#define RAS_NONSTD_SEC_LEN (sizeof(struct cper_sec_nonstd_err)) + +#define RAS_SEC_DESC_OFFSET(idx) (RAS_HDR_LEN + (RAS_SEC_DESC_LEN * idx)) + +#define RAS_BOOT_SEC_OFFSET(count, idx) \ + (RAS_HDR_LEN + (RAS_SEC_DESC_LEN * count) + (RAS_BOOT_SEC_LEN * idx)) +#define RAS_FATAL_SEC_OFFSET(count, idx) \ + (RAS_HDR_LEN + (RAS_SEC_DESC_LEN * count) + (RAS_FATAL_SEC_LEN * idx)) +#define RAS_NONSTD_SEC_OFFSET(count, idx) \ + (RAS_HDR_LEN + (RAS_SEC_DESC_LEN * count) + (RAS_NONSTD_SEC_LEN * idx)) + +struct ras_core_context; +struct ras_log_info; +int ras_cper_generate_cper(struct ras_core_context *ras_core, + struct ras_log_info **trace_list, uint32_t count, + uint8_t *buf, uint32_t buf_len, uint32_t *real_data_len); +#endif From 416c8d1df463dc284caeee7ef6d23449f00e738c Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 17:13:19 +0800 Subject: [PATCH 2100/2653] drm/amd/ras: Add rascore unified interface function 1. Complete the initialization call of all sub-functions. 2. Export common interfaces. V2: Remove the use of typedef to define function pointer. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/ras/rascore/ras.h | 368 +++++++++++++ drivers/gpu/drm/amd/ras/rascore/ras_core.c | 603 +++++++++++++++++++++ 2 files changed, 971 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras.h create mode 100644 drivers/gpu/drm/amd/ras/rascore/ras_core.c diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h new file mode 100644 index 0000000000000..fa224b36e3f2d --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras.h @@ -0,0 +1,368 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __RAS_H__ +#define __RAS_H__ +#include "ras_sys.h" +#include "ras_umc.h" +#include "ras_aca.h" +#include "ras_eeprom.h" +#include "ras_core_status.h" +#include "ras_process.h" +#include "ras_gfx.h" +#include "ras_cmd.h" +#include "ras_nbio.h" +#include "ras_mp1.h" +#include "ras_psp.h" +#include "ras_log_ring.h" + +#define RAS_HW_ERR "[Hardware Error]: " + +#define RAS_GPU_PAGE_SHIFT 12 +#define RAS_ADDR_TO_PFN(addr) ((addr) >> RAS_GPU_PAGE_SHIFT) +#define RAS_PFN_TO_ADDR(pfn) ((pfn) << RAS_GPU_PAGE_SHIFT) + +#define RAS_CORE_RESET_GPU 0x10000 + +#define GPU_RESET_CAUSE_POISON (RAS_CORE_RESET_GPU | 0x0001) +#define GPU_RESET_CAUSE_FATAL (RAS_CORE_RESET_GPU | 0x0002) +#define GPU_RESET_CAUSE_RMA (RAS_CORE_RESET_GPU | 0x0004) + +enum ras_block_id { + RAS_BLOCK_ID__UMC = 0, + RAS_BLOCK_ID__SDMA, + RAS_BLOCK_ID__GFX, + RAS_BLOCK_ID__MMHUB, + RAS_BLOCK_ID__ATHUB, + RAS_BLOCK_ID__PCIE_BIF, + RAS_BLOCK_ID__HDP, + RAS_BLOCK_ID__XGMI_WAFL, + RAS_BLOCK_ID__DF, + RAS_BLOCK_ID__SMN, + RAS_BLOCK_ID__SEM, + RAS_BLOCK_ID__MP0, + RAS_BLOCK_ID__MP1, + RAS_BLOCK_ID__FUSE, + RAS_BLOCK_ID__MCA, + RAS_BLOCK_ID__VCN, + RAS_BLOCK_ID__JPEG, + RAS_BLOCK_ID__IH, + RAS_BLOCK_ID__MPIO, + + RAS_BLOCK_ID__LAST +}; + +enum ras_ecc_err_type { + RAS_ECC_ERR__NONE = 0, + RAS_ECC_ERR__PARITY = 1, + RAS_ECC_ERR__SINGLE_CORRECTABLE = 2, + RAS_ECC_ERR__MULTI_UNCORRECTABLE = 4, + RAS_ECC_ERR__POISON = 8, +}; + +enum ras_err_type { + RAS_ERR_TYPE__UE = 0, + RAS_ERR_TYPE__CE, + RAS_ERR_TYPE__DE, + RAS_ERR_TYPE__LAST +}; + +enum ras_seqno_type { + RAS_SEQNO_TYPE_INVALID = 0, + RAS_SEQNO_TYPE_UE, + RAS_SEQNO_TYPE_CE, + RAS_SEQNO_TYPE_DE, + RAS_SEQNO_TYPE_POISON_CONSUMPTION, + RAS_SEQNO_TYPE_COUNT_MAX, +}; + +enum ras_seqno_fifo { + SEQNO_FIFO_INVALID = 0, + SEQNO_FIFO_POISON_CREATION, + SEQNO_FIFO_POISON_CONSUMPTION, + SEQNO_FIFO_COUNT_MAX +}; + +enum ras_notify_event { + RAS_EVENT_ID__NONE, + RAS_EVENT_ID__BAD_PAGE_DETECTED, + RAS_EVENT_ID__POISON_CONSUMPTION, + RAS_EVENT_ID__RESERVE_BAD_PAGE, + RAS_EVENT_ID__DEVICE_RMA, + RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM, + RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP, + RAS_EVENT_ID__FATAL_ERROR_DETECTED, + RAS_EVENT_ID__RESET_GPU, + RAS_EVENT_ID__RESET_VF, +}; + +enum ras_gpu_status { + RAS_GPU_STATUS__NOT_READY = 0, + RAS_GPU_STATUS__READY = 0x1, + RAS_GPU_STATUS__IN_RESET = 0x2, + RAS_GPU_STATUS__IS_RMA = 0x4, + RAS_GPU_STATUS__IS_VF = 0x8, +}; + +struct ras_core_context; +struct ras_bank_ecc; +struct ras_umc; +struct ras_aca; +struct ras_process; +struct ras_nbio; +struct ras_log_ring; +struct ras_psp; + +struct ras_mp1_sys_func { + int (*mp1_get_valid_bank_count)(struct ras_core_context *ras_core, + u32 msg, u32 *count); + int (*mp1_dump_valid_bank)(struct ras_core_context *ras_core, + u32 msg, u32 idx, u32 reg_idx, u64 *val); +}; + +struct ras_eeprom_sys_func { + int (*eeprom_i2c_xfer)(struct ras_core_context *ras_core, + u32 eeprom_addr, u8 *eeprom_buf, u32 buf_size, bool read); + int (*update_eeprom_i2c_config)(struct ras_core_context *ras_core); +}; + +struct ras_nbio_sys_func { + int (*set_ras_controller_irq_state)(struct ras_core_context *ras_core, + bool state); + int (*set_ras_err_event_athub_irq_state)(struct ras_core_context *ras_core, + bool state); +}; + +struct ras_time { + int tm_sec; + int tm_min; + int tm_hour; + int tm_mday; + int tm_mon; + long tm_year; +}; + +struct device_system_info { + uint32_t device_id; + uint32_t vendor_id; + uint32_t socket_id; +}; + +enum gpu_mem_type { + GPU_MEM_TYPE_DEFAULT, + GPU_MEM_TYPE_RAS_PSP_RING, + GPU_MEM_TYPE_RAS_PSP_CMD, + GPU_MEM_TYPE_RAS_PSP_FENCE, + GPU_MEM_TYPE_RAS_TA_FW, + GPU_MEM_TYPE_RAS_TA_CMD, +}; + +struct ras_psp_sys_func { + int (*get_ras_psp_system_status)(struct ras_core_context *ras_core, + struct ras_psp_sys_status *status); + int (*get_ras_ta_init_param)(struct ras_core_context *ras_core, + struct ras_ta_init_param *ras_ta_param); +}; + +struct ras_sys_func { + int (*gpu_reset_lock)(struct ras_core_context *ras_core, + bool down, bool try); + int (*check_gpu_status)(struct ras_core_context *ras_core, + uint32_t *status); + int (*gen_seqno)(struct ras_core_context *ras_core, + enum ras_seqno_type seqno_type, uint64_t *seqno); + int (*async_handle_ras_event)(struct ras_core_context *ras_core, void *data); + int (*ras_notifier)(struct ras_core_context *ras_core, + enum ras_notify_event event_id, void *data); + u64 (*get_utc_second_timestamp)(struct ras_core_context *ras_core); + int (*get_device_system_info)(struct ras_core_context *ras_core, + struct device_system_info *dev_info); + bool (*detect_ras_interrupt)(struct ras_core_context *ras_core); + int (*get_gpu_mem)(struct ras_core_context *ras_core, + enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem); + int (*put_gpu_mem)(struct ras_core_context *ras_core, + enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem); +}; + +struct ras_ecc_count { + uint64_t new_ce_count; + uint64_t total_ce_count; + uint64_t new_ue_count; + uint64_t total_ue_count; + uint64_t new_de_count; + uint64_t total_de_count; +}; + +struct ras_bank_ecc { + uint32_t nps; + uint64_t seq_no; + uint64_t status; + uint64_t ipid; + uint64_t addr; +}; + +struct ras_bank_ecc_node { + struct list_head node; + struct ras_bank_ecc ecc; +}; + +struct ras_aca_config { + u32 socket_num_per_hive; + u32 aid_num_per_socket; + u32 xcd_num_per_aid; +}; + +struct ras_mp1_config { + const struct ras_mp1_sys_func *mp1_sys_fn; +}; + +struct ras_nbio_config { + const struct ras_nbio_sys_func *nbio_sys_fn; +}; + +struct ras_psp_config { + const struct ras_psp_sys_func *psp_sys_fn; +}; + +struct ras_umc_config { + uint32_t umc_vram_type; +}; + +struct ras_eeprom_config { + const struct ras_eeprom_sys_func *eeprom_sys_fn; + int eeprom_record_threshold_config; + uint32_t eeprom_record_threshold_count; + void *eeprom_i2c_adapter; + u32 eeprom_i2c_addr; + u32 eeprom_i2c_port; + u16 max_i2c_read_len; + u16 max_i2c_write_len; +}; + +struct ras_core_config { + u32 aca_ip_version; + u32 umc_ip_version; + u32 mp1_ip_version; + u32 gfx_ip_version; + u32 nbio_ip_version; + u32 psp_ip_version; + + bool poison_supported; + bool ras_eeprom_supported; + const struct ras_sys_func *sys_fn; + + struct ras_aca_config aca_cfg; + struct ras_mp1_config mp1_cfg; + struct ras_nbio_config nbio_cfg; + struct ras_psp_config psp_cfg; + struct ras_eeprom_config eeprom_cfg; + struct ras_umc_config umc_cfg; +}; + +struct ras_core_context { + void *dev; + struct ras_core_config *config; + u32 socket_num_per_hive; + u32 aid_num_per_socket; + u32 xcd_num_per_aid; + int max_ue_banks_per_query; + int max_ce_banks_per_query; + struct ras_aca ras_aca; + + bool ras_eeprom_supported; + struct ras_eeprom_control ras_eeprom; + + struct ras_psp ras_psp; + struct ras_umc ras_umc; + struct ras_nbio ras_nbio; + struct ras_gfx ras_gfx; + struct ras_mp1 ras_mp1; + struct ras_process ras_proc; + struct ras_cmd_mgr ras_cmd; + struct ras_log_ring ras_log_ring; + + const struct ras_sys_func *sys_fn; + + /* is poison mode supported */ + bool poison_supported; + + bool is_rma; + bool is_initialized; + + struct kfifo de_seqno_fifo; + struct kfifo consumption_seqno_fifo; + spinlock_t seqno_lock; + + bool ras_core_enabled; +}; + +struct ras_core_context *ras_core_create(struct ras_core_config *init_config); +void ras_core_destroy(struct ras_core_context *ras_core); +int ras_core_sw_init(struct ras_core_context *ras_core); +int ras_core_sw_fini(struct ras_core_context *ras_core); +int ras_core_hw_init(struct ras_core_context *ras_core); +int ras_core_hw_fini(struct ras_core_context *ras_core); +bool ras_core_is_ready(struct ras_core_context *ras_core); +uint64_t ras_core_gen_seqno(struct ras_core_context *ras_core, + enum ras_seqno_type seqno_type); +uint64_t ras_core_get_seqno(struct ras_core_context *ras_core, + enum ras_seqno_type seqno_type, bool pop); + +int ras_core_put_seqno(struct ras_core_context *ras_core, + enum ras_seqno_type seqno_type, uint64_t seqno); + +int ras_core_update_ecc_info(struct ras_core_context *ras_core); +int ras_core_query_block_ecc_data(struct ras_core_context *ras_core, + enum ras_block_id block, struct ras_ecc_count *ecc_count); + +bool ras_core_gpu_in_reset(struct ras_core_context *ras_core); +bool ras_core_gpu_is_rma(struct ras_core_context *ras_core); +bool ras_core_gpu_is_vf(struct ras_core_context *ras_core); +bool ras_core_handle_nbio_irq(struct ras_core_context *ras_core, void *data); +int ras_core_handle_fatal_error(struct ras_core_context *ras_core); + +uint32_t ras_core_get_curr_nps_mode(struct ras_core_context *ras_core); +const char *ras_core_get_ras_block_name(enum ras_block_id block_id); +int ras_core_convert_timestamp_to_time(struct ras_core_context *ras_core, + uint64_t timestamp, struct ras_time *tm); + +int ras_core_set_status(struct ras_core_context *ras_core, bool enable); +bool ras_core_is_enabled(struct ras_core_context *ras_core); +uint64_t ras_core_get_utc_second_timestamp(struct ras_core_context *ras_core); +int ras_core_translate_soc_pa_and_bank(struct ras_core_context *ras_core, + uint64_t *soc_pa, struct umc_bank_addr *bank_addr, bool bank_to_pa); +bool ras_core_ras_interrupt_detected(struct ras_core_context *ras_core); +int ras_core_get_gpu_mem(struct ras_core_context *ras_core, + enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem); +int ras_core_put_gpu_mem(struct ras_core_context *ras_core, + enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem); +bool ras_core_check_safety_watermark(struct ras_core_context *ras_core); +int ras_core_down_trylock_gpu_reset_lock(struct ras_core_context *ras_core); +void ras_core_down_gpu_reset_lock(struct ras_core_context *ras_core); +void ras_core_up_gpu_reset_lock(struct ras_core_context *ras_core); +int ras_core_event_notify(struct ras_core_context *ras_core, + enum ras_notify_event event_id, void *data); +int ras_core_get_device_system_info(struct ras_core_context *ras_core, + struct device_system_info *dev_info); +#endif diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c new file mode 100644 index 0000000000000..41fc9f0d84e4f --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c @@ -0,0 +1,603 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "ras.h" +#include "ras_core_status.h" + +#define RAS_SEQNO_FIFO_SIZE (128 * sizeof(uint64_t)) + +#define IS_LEAP_YEAR(x) ((x % 4 == 0 && x % 100 != 0) || x % 400 == 0) + +static const char * const ras_block_name[] = { + "umc", + "sdma", + "gfx", + "mmhub", + "athub", + "pcie_bif", + "hdp", + "xgmi_wafl", + "df", + "smn", + "sem", + "mp0", + "mp1", + "fuse", + "mca", + "vcn", + "jpeg", + "ih", + "mpio", +}; + +const char *ras_core_get_ras_block_name(enum ras_block_id block_id) +{ + if (block_id >= ARRAY_SIZE(ras_block_name)) + return ""; + + return ras_block_name[block_id]; +} + +int ras_core_convert_timestamp_to_time(struct ras_core_context *ras_core, + uint64_t timestamp, struct ras_time *tm) +{ + int days_in_month[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + uint64_t year = 0, month = 0, day = 0, hour = 0, minute = 0, second = 0; + int seconds_per_day = 24 * 60 * 60; + int seconds_per_hour = 60 * 60; + int seconds_per_minute = 60; + int days, remaining_seconds; + + days = timestamp / seconds_per_day; + remaining_seconds = timestamp % seconds_per_day; + + /* utc_timestamp follows the Unix epoch */ + year = 1970; + while (days >= 365) { + if (IS_LEAP_YEAR(year)) { + if (days < 366) + break; + days -= 366; + } else { + days -= 365; + } + year++; + } + + days_in_month[1] += IS_LEAP_YEAR(year); + + month = 0; + while (days >= days_in_month[month]) { + days -= days_in_month[month]; + month++; + } + month++; + day = days + 1; + + if (remaining_seconds) { + hour = remaining_seconds / seconds_per_hour; + minute = (remaining_seconds % seconds_per_hour) / seconds_per_minute; + second = remaining_seconds % seconds_per_minute; + } + + tm->tm_year = year; + tm->tm_mon = month; + tm->tm_mday = day; + tm->tm_hour = hour; + tm->tm_min = minute; + tm->tm_sec = second; + + return 0; +} + +bool ras_core_gpu_in_reset(struct ras_core_context *ras_core) +{ + uint32_t status = 0; + + if (ras_core->sys_fn && + ras_core->sys_fn->check_gpu_status) + ras_core->sys_fn->check_gpu_status(ras_core, &status); + + return (status & RAS_GPU_STATUS__IN_RESET) ? true : false; +} + +bool ras_core_gpu_is_vf(struct ras_core_context *ras_core) +{ + uint32_t status = 0; + + if (ras_core->sys_fn && + ras_core->sys_fn->check_gpu_status) + ras_core->sys_fn->check_gpu_status(ras_core, &status); + + return (status & RAS_GPU_STATUS__IS_VF) ? true : false; +} + +bool ras_core_gpu_is_rma(struct ras_core_context *ras_core) +{ + if (!ras_core) + return false; + + return ras_core->is_rma; +} + +static int ras_core_seqno_fifo_write(struct ras_core_context *ras_core, + enum ras_seqno_fifo fifo_type, uint64_t seqno) +{ + int ret = 0; + struct kfifo *seqno_fifo = NULL; + + if (fifo_type == SEQNO_FIFO_POISON_CREATION) + seqno_fifo = &ras_core->de_seqno_fifo; + else if (fifo_type == SEQNO_FIFO_POISON_CONSUMPTION) + seqno_fifo = &ras_core->consumption_seqno_fifo; + + if (seqno_fifo) + ret = kfifo_in_spinlocked(seqno_fifo, + &seqno, sizeof(seqno), &ras_core->seqno_lock); + + return ret ? 0 : -EINVAL; +} + +static int ras_core_seqno_fifo_read(struct ras_core_context *ras_core, + enum ras_seqno_fifo fifo_type, uint64_t *seqno, bool pop) +{ + int ret = 0; + struct kfifo *seqno_fifo = NULL; + + if (fifo_type == SEQNO_FIFO_POISON_CREATION) + seqno_fifo = &ras_core->de_seqno_fifo; + else if (fifo_type == SEQNO_FIFO_POISON_CONSUMPTION) + seqno_fifo = &ras_core->consumption_seqno_fifo; + + if (seqno_fifo) { + if (pop) + ret = kfifo_out_spinlocked(seqno_fifo, + seqno, sizeof(*seqno), &ras_core->seqno_lock); + else + ret = kfifo_out_peek(seqno_fifo, seqno, sizeof(*seqno)); + } + + return ret ? 0 : -EINVAL; +} + +uint64_t ras_core_gen_seqno(struct ras_core_context *ras_core, + enum ras_seqno_type type) +{ + uint64_t seqno = 0; + + if (ras_core->sys_fn && + ras_core->sys_fn->gen_seqno) + ras_core->sys_fn->gen_seqno(ras_core, type, &seqno); + + return seqno; +} + +int ras_core_put_seqno(struct ras_core_context *ras_core, + enum ras_seqno_type seqno_type, uint64_t seqno) +{ + int ret = 0; + + if (seqno_type >= RAS_SEQNO_TYPE_COUNT_MAX) + return -EINVAL; + + if (seqno_type == RAS_SEQNO_TYPE_DE) + ret = ras_core_seqno_fifo_write(ras_core, + SEQNO_FIFO_POISON_CREATION, seqno); + else if (seqno_type == RAS_SEQNO_TYPE_POISON_CONSUMPTION) + ret = ras_core_seqno_fifo_write(ras_core, + SEQNO_FIFO_POISON_CONSUMPTION, seqno); + else + ret = -EINVAL; + + return ret; +} + +uint64_t ras_core_get_seqno(struct ras_core_context *ras_core, + enum ras_seqno_type seqno_type, bool pop) +{ + uint64_t seq_no; + int ret = -ENODATA; + + if (seqno_type >= RAS_SEQNO_TYPE_COUNT_MAX) + return 0; + + if (seqno_type == RAS_SEQNO_TYPE_DE) + ret = ras_core_seqno_fifo_read(ras_core, + SEQNO_FIFO_POISON_CREATION, &seq_no, pop); + else if (seqno_type == RAS_SEQNO_TYPE_POISON_CONSUMPTION) + ret = ras_core_seqno_fifo_read(ras_core, + SEQNO_FIFO_POISON_CONSUMPTION, &seq_no, pop); + + if (ret) + seq_no = ras_core_gen_seqno(ras_core, seqno_type); + + return seq_no; +} + +static int ras_core_eeprom_recovery(struct ras_core_context *ras_core) +{ + int count; + int ret; + + count = ras_eeprom_get_record_count(ras_core); + if (!count) + return 0; + + /* Avoid bad page to be loaded again after gpu reset */ + if (ras_umc_get_saved_eeprom_count(ras_core) >= count) + return 0; + + ret = ras_umc_load_bad_pages(ras_core); + if (ret) { + RAS_DEV_ERR(ras_core->dev, "ras_umc_load_bad_pages failed: %d\n", ret); + return ret; + } + + ras_eeprom_sync_info(ras_core); + + return ret; +} + +struct ras_core_context *ras_core_create(struct ras_core_config *init_config) +{ + struct ras_core_context *ras_core; + struct ras_core_config *config; + + ras_core = kzalloc(sizeof(*ras_core), GFP_KERNEL); + if (!ras_core) + return NULL; + + config = kzalloc(sizeof(*config), GFP_KERNEL); + if (!config) { + kfree(ras_core); + return NULL; + } + + memcpy(config, init_config, sizeof(*config)); + ras_core->config = config; + + return ras_core; +} + +void ras_core_destroy(struct ras_core_context *ras_core) +{ + if (ras_core) + kfree(ras_core->config); + + kfree(ras_core); +} + +int ras_core_sw_init(struct ras_core_context *ras_core) +{ + int ret; + + if (!ras_core->config) { + RAS_DEV_ERR(ras_core->dev, "No ras core config!\n"); + return -EINVAL; + } + + ras_core->sys_fn = ras_core->config->sys_fn; + if (!ras_core->sys_fn) + return -EINVAL; + + ret = kfifo_alloc(&ras_core->de_seqno_fifo, + RAS_SEQNO_FIFO_SIZE, GFP_KERNEL); + if (ret) + return ret; + + ret = kfifo_alloc(&ras_core->consumption_seqno_fifo, + RAS_SEQNO_FIFO_SIZE, GFP_KERNEL); + if (ret) + return ret; + + spin_lock_init(&ras_core->seqno_lock); + + ret = ras_aca_sw_init(ras_core); + if (ret) + return ret; + + ret = ras_umc_sw_init(ras_core); + if (ret) + return ret; + + ret = ras_cmd_init(ras_core); + if (ret) + return ret; + + ret = ras_log_ring_sw_init(ras_core); + if (ret) + return ret; + + ret = ras_psp_sw_init(ras_core); + if (ret) + return ret; + + return 0; +} + +int ras_core_sw_fini(struct ras_core_context *ras_core) +{ + kfifo_free(&ras_core->de_seqno_fifo); + kfifo_free(&ras_core->consumption_seqno_fifo); + + ras_psp_sw_fini(ras_core); + ras_log_ring_sw_fini(ras_core); + ras_cmd_fini(ras_core); + ras_umc_sw_fini(ras_core); + ras_aca_sw_fini(ras_core); + + return 0; +} + +int ras_core_hw_init(struct ras_core_context *ras_core) +{ + int ret; + + ras_core->ras_eeprom_supported = + ras_core->config->ras_eeprom_supported; + + ras_core->poison_supported = ras_core->config->poison_supported; + + ret = ras_psp_hw_init(ras_core); + if (ret) + return ret; + + ret = ras_aca_hw_init(ras_core); + if (ret) + goto init_err1; + + ret = ras_mp1_hw_init(ras_core); + if (ret) + goto init_err2; + + ret = ras_nbio_hw_init(ras_core); + if (ret) + goto init_err3; + + ret = ras_umc_hw_init(ras_core); + if (ret) + goto init_err4; + + ret = ras_gfx_hw_init(ras_core); + if (ret) + goto init_err5; + + ret = ras_eeprom_hw_init(ras_core); + if (ret) + goto init_err6; + + ret = ras_core_eeprom_recovery(ras_core); + if (ret) { + RAS_DEV_ERR(ras_core->dev, + "Failed to recovery ras core, ret:%d\n", ret); + goto init_err6; + } + + ret = ras_eeprom_check_storage_status(ras_core); + if (ret) + goto init_err6; + + ret = ras_process_init(ras_core); + if (ret) + goto init_err7; + + ras_core->is_initialized = true; + + return 0; + +init_err7: + ras_eeprom_hw_fini(ras_core); +init_err6: + ras_gfx_hw_fini(ras_core); +init_err5: + ras_umc_hw_fini(ras_core); +init_err4: + ras_nbio_hw_fini(ras_core); +init_err3: + ras_mp1_hw_fini(ras_core); +init_err2: + ras_aca_hw_fini(ras_core); +init_err1: + ras_psp_hw_fini(ras_core); + return ret; +} + +int ras_core_hw_fini(struct ras_core_context *ras_core) +{ + ras_core->is_initialized = false; + + ras_process_fini(ras_core); + ras_eeprom_hw_fini(ras_core); + ras_gfx_hw_fini(ras_core); + ras_nbio_hw_fini(ras_core); + ras_umc_hw_fini(ras_core); + ras_mp1_hw_fini(ras_core); + ras_aca_hw_fini(ras_core); + ras_psp_hw_fini(ras_core); + + return 0; +} + +bool ras_core_handle_nbio_irq(struct ras_core_context *ras_core, void *data) +{ + return ras_nbio_handle_irq_error(ras_core, data); +} + +int ras_core_handle_fatal_error(struct ras_core_context *ras_core) +{ + int ret = 0; + + ras_aca_mark_fatal_flag(ras_core); + + ret = ras_core_event_notify(ras_core, + RAS_EVENT_ID__FATAL_ERROR_DETECTED, NULL); + + return ret; +} + +uint32_t ras_core_get_curr_nps_mode(struct ras_core_context *ras_core) +{ + if (ras_core->ras_nbio.ip_func && + ras_core->ras_nbio.ip_func->get_memory_partition_mode) + return ras_core->ras_nbio.ip_func->get_memory_partition_mode(ras_core); + + RAS_DEV_ERR(ras_core->dev, "Failed to get gpu memory nps mode!\n"); + return 0; +} + +int ras_core_update_ecc_info(struct ras_core_context *ras_core) +{ + int ret; + + ret = ras_aca_update_ecc(ras_core, RAS_ERR_TYPE__CE, NULL); + if (!ret) + ret = ras_aca_update_ecc(ras_core, RAS_ERR_TYPE__UE, NULL); + + return ret; +} + +int ras_core_query_block_ecc_data(struct ras_core_context *ras_core, + enum ras_block_id block, struct ras_ecc_count *ecc_count) +{ + int ret; + + if (!ecc_count || (block >= RAS_BLOCK_ID__LAST) || !ras_core) + return -EINVAL; + + ret = ras_aca_get_block_ecc_count(ras_core, block, ecc_count); + if (!ret) + ras_aca_clear_block_new_ecc_count(ras_core, block); + + return ret; +} + +int ras_core_set_status(struct ras_core_context *ras_core, bool enable) +{ + ras_core->ras_core_enabled = enable; + + return 0; +} + +bool ras_core_is_enabled(struct ras_core_context *ras_core) +{ + return ras_core->ras_core_enabled; +} + +uint64_t ras_core_get_utc_second_timestamp(struct ras_core_context *ras_core) +{ + if (ras_core && ras_core->sys_fn && + ras_core->sys_fn->get_utc_second_timestamp) + return ras_core->sys_fn->get_utc_second_timestamp(ras_core); + + RAS_DEV_ERR(ras_core->dev, "Failed to get system timestamp!\n"); + return 0; +} + +int ras_core_translate_soc_pa_and_bank(struct ras_core_context *ras_core, + uint64_t *soc_pa, struct umc_bank_addr *bank_addr, bool bank_to_pa) +{ + if (!ras_core || !soc_pa || !bank_addr) + return -EINVAL; + + return ras_umc_translate_soc_pa_and_bank(ras_core, soc_pa, bank_addr, bank_to_pa); +} + +bool ras_core_ras_interrupt_detected(struct ras_core_context *ras_core) +{ + if (ras_core && ras_core->sys_fn && + ras_core->sys_fn->detect_ras_interrupt) + return ras_core->sys_fn->detect_ras_interrupt(ras_core); + + RAS_DEV_ERR(ras_core->dev, "Failed to detect ras interrupt!\n"); + return false; +} + +int ras_core_get_gpu_mem(struct ras_core_context *ras_core, + enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem) +{ + if (ras_core->sys_fn && ras_core->sys_fn->get_gpu_mem) + return ras_core->sys_fn->get_gpu_mem(ras_core, mem_type, gpu_mem); + + RAS_DEV_ERR(ras_core->dev, "Not config get gpu memory API!\n"); + return -EACCES; +} + +int ras_core_put_gpu_mem(struct ras_core_context *ras_core, + enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem) +{ + if (ras_core->sys_fn && ras_core->sys_fn->put_gpu_mem) + return ras_core->sys_fn->put_gpu_mem(ras_core, mem_type, gpu_mem); + + RAS_DEV_ERR(ras_core->dev, "Not config put gpu memory API!!\n"); + return -EACCES; +} + +bool ras_core_is_ready(struct ras_core_context *ras_core) +{ + return ras_core ? ras_core->is_initialized : false; +} + +bool ras_core_check_safety_watermark(struct ras_core_context *ras_core) +{ + return ras_eeprom_check_safety_watermark(ras_core); +} + +int ras_core_down_trylock_gpu_reset_lock(struct ras_core_context *ras_core) +{ + if (ras_core->sys_fn && ras_core->sys_fn->gpu_reset_lock) + return ras_core->sys_fn->gpu_reset_lock(ras_core, true, true); + + return 1; +} + +void ras_core_down_gpu_reset_lock(struct ras_core_context *ras_core) +{ + if (ras_core->sys_fn && ras_core->sys_fn->gpu_reset_lock) + ras_core->sys_fn->gpu_reset_lock(ras_core, true, false); +} + +void ras_core_up_gpu_reset_lock(struct ras_core_context *ras_core) +{ + if (ras_core->sys_fn && ras_core->sys_fn->gpu_reset_lock) + ras_core->sys_fn->gpu_reset_lock(ras_core, false, false); +} + +int ras_core_event_notify(struct ras_core_context *ras_core, + enum ras_notify_event event_id, void *data) +{ + if (ras_core && ras_core->sys_fn && + ras_core->sys_fn->ras_notifier) + return ras_core->sys_fn->ras_notifier(ras_core, event_id, data); + + return -RAS_CORE_NOT_SUPPORTED; +} + +int ras_core_get_device_system_info(struct ras_core_context *ras_core, + struct device_system_info *dev_info) +{ + if (ras_core && ras_core->sys_fn && + ras_core->sys_fn->get_device_system_info) + return ras_core->sys_fn->get_device_system_info(ras_core, dev_info); + + return -RAS_CORE_NOT_SUPPORTED; +} From 8b378f8b4e8660b8eb6be3432fc2a8f972d55b97 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 17:55:37 +0800 Subject: [PATCH 2101/2653] drm/amd/ras: Add files to ras core Makefile Add files to ras core Makefile. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/ras/rascore/Makefile | 44 ++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/amd/ras/rascore/Makefile b/drivers/gpu/drm/amd/ras/rascore/Makefile index e69de29bb2d1d..e826a1f86424c 100644 --- a/drivers/gpu/drm/amd/ras/rascore/Makefile +++ b/drivers/gpu/drm/amd/ras/rascore/Makefile @@ -0,0 +1,44 @@ +# +# Copyright 2025 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +RAS_CORE_FILES = ras_core.o \ + ras_mp1.o \ + ras_mp1_v13_0.o \ + ras_aca.o \ + ras_aca_v1_0.o \ + ras_eeprom.o \ + ras_umc.o \ + ras_umc_v12_0.o \ + ras_cmd.o \ + ras_gfx.o \ + ras_gfx_v9_0.o \ + ras_process.o \ + ras_nbio.o \ + ras_nbio_v7_9.o \ + ras_log_ring.o \ + ras_cper.o \ + ras_psp.o \ + ras_psp_v13_0.o + + +RAS_CORE = $(addprefix $(AMD_GPU_RAS_PATH)/rascore/,$(RAS_CORE_FILES)) + +AMD_GPU_RAS_FILES += $(RAS_CORE) From c4e7fd3c433e1d8e92bf54f04be3e5d74ee3a6bf Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Fri, 19 Sep 2025 14:31:50 +0800 Subject: [PATCH 2102/2653] drm/amdgpu/userq: assign an error code for invalid userq va It should return an error code if userq VA validation fails. Fixes: 9e46b8bb0539 ("drm/amdgpu: validate userq buffer virtual address and size") Signed-off-by: Prike Liang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 11857daf6ac02..7ba1ad907e2dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -71,6 +71,7 @@ int amdgpu_userq_input_va_validate(struct amdgpu_vm *vm, u64 addr, return 0; } + r = -EINVAL; out_err: amdgpu_bo_unreserve(vm->root.bo); return r; @@ -508,6 +509,7 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) if (amdgpu_userq_input_va_validate(&fpriv->vm, args->in.queue_va, args->in.queue_size) || amdgpu_userq_input_va_validate(&fpriv->vm, args->in.rptr_va, AMDGPU_GPU_PAGE_SIZE) || amdgpu_userq_input_va_validate(&fpriv->vm, args->in.wptr_va, AMDGPU_GPU_PAGE_SIZE)) { + r = -EINVAL; kfree(queue); goto unlock; } From 39d02a132342d09aab2787554aadfc0927e3bb5e Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 24 Sep 2025 13:36:49 +0800 Subject: [PATCH 2103/2653] =?UTF-8?q?drm/amdkcl=EF=BC=9AAdd=20kcl=5F=20pre?= =?UTF-8?q?fix=20to=20fake=20drm=5Fsuballoc=5F*=20functions=20for=20avoid?= =?UTF-8?q?=20symbol=20conflict?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit KCL's fake drm_suballoc_* implementations may conflict with upstream DRM symbols,causing module loading issues Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c | 72 +++++++++---------- include/kcl/kcl_drm_suballoc.h | 29 +++++--- 2 files changed, 56 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c index 8ad6e3d9b60eb..c0dcc45d0666f 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c @@ -50,8 +50,8 @@ #include #ifndef HAVE_DRM_SUBALLOC_MANAGER_INIT -static void drm_suballoc_remove_locked(struct drm_suballoc *sa); -static void drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager); +static void kcl_drm_suballoc_remove_locked(struct drm_suballoc *sa); +static void kcl_drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager); /** * drm_suballoc_manager_init() - Initialise the drm_suballoc_manager @@ -61,7 +61,7 @@ static void drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager); * * Prepares the suballocation manager for suballocations. */ -void drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, +void kcl_drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, size_t size, size_t align) { unsigned int i; @@ -83,7 +83,7 @@ void drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) INIT_LIST_HEAD(&sa_manager->flist[i]); } -EXPORT_SYMBOL(drm_suballoc_manager_init); +EXPORT_SYMBOL(kcl_drm_suballoc_manager_init); /** * drm_suballoc_manager_fini() - Destroy the drm_suballoc_manager @@ -93,7 +93,7 @@ EXPORT_SYMBOL(drm_suballoc_manager_init); * with drm_suballoc_free() must be signaled, or we cannot clean up * the entire manager. */ -void drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager) +void kcl_drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager) { struct drm_suballoc *sa, *tmp; @@ -102,19 +102,19 @@ void drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager) if (!list_empty(&sa_manager->olist)) { sa_manager->hole = &sa_manager->olist; - drm_suballoc_try_free(sa_manager); + kcl_drm_suballoc_try_free(sa_manager); if (!list_empty(&sa_manager->olist)) DRM_ERROR("sa_manager is not empty, clearing anyway\n"); } list_for_each_entry_safe(sa, tmp, &sa_manager->olist, olist) { - drm_suballoc_remove_locked(sa); + kcl_drm_suballoc_remove_locked(sa); } sa_manager->size = 0; } -EXPORT_SYMBOL(drm_suballoc_manager_fini); +EXPORT_SYMBOL(kcl_drm_suballoc_manager_fini); -static void drm_suballoc_remove_locked(struct drm_suballoc *sa) +static void kcl_drm_suballoc_remove_locked(struct drm_suballoc *sa) { struct drm_suballoc_manager *sa_manager = sa->manager; @@ -127,7 +127,7 @@ static void drm_suballoc_remove_locked(struct drm_suballoc *sa) kfree(sa); } -static void drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager) +static void kcl_drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager) { struct drm_suballoc *sa, *tmp; @@ -139,11 +139,11 @@ static void drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager) if (!sa->fence || !dma_fence_is_signaled(sa->fence)) return; - drm_suballoc_remove_locked(sa); + kcl_drm_suballoc_remove_locked(sa); } } -static size_t drm_suballoc_hole_soffset(struct drm_suballoc_manager *sa_manager) +static size_t kcl_drm_suballoc_hole_soffset(struct drm_suballoc_manager *sa_manager) { struct list_head *hole = sa_manager->hole; @@ -153,7 +153,7 @@ static size_t drm_suballoc_hole_soffset(struct drm_suballoc_manager *sa_manager) return 0; } -static size_t drm_suballoc_hole_eoffset(struct drm_suballoc_manager *sa_manager) +static size_t kcl_drm_suballoc_hole_eoffset(struct drm_suballoc_manager *sa_manager) { struct list_head *hole = sa_manager->hole; @@ -162,14 +162,14 @@ static size_t drm_suballoc_hole_eoffset(struct drm_suballoc_manager *sa_manager) return sa_manager->size; } -static bool drm_suballoc_try_alloc(struct drm_suballoc_manager *sa_manager, +static bool kcl_drm_suballoc_try_alloc(struct drm_suballoc_manager *sa_manager, struct drm_suballoc *sa, size_t size, size_t align) { size_t soffset, eoffset, wasted; - soffset = drm_suballoc_hole_soffset(sa_manager); - eoffset = drm_suballoc_hole_eoffset(sa_manager); + soffset = kcl_drm_suballoc_hole_soffset(sa_manager); + eoffset = kcl_drm_suballoc_hole_eoffset(sa_manager); wasted = round_up(soffset, align) - soffset; if ((eoffset - soffset) >= (size + wasted)) { @@ -186,7 +186,7 @@ static bool drm_suballoc_try_alloc(struct drm_suballoc_manager *sa_manager, return false; } -static bool __drm_suballoc_event(struct drm_suballoc_manager *sa_manager, +static bool kcl___drm_suballoc_event(struct drm_suballoc_manager *sa_manager, size_t size, size_t align) { size_t soffset, eoffset, wasted; @@ -196,8 +196,8 @@ static bool __drm_suballoc_event(struct drm_suballoc_manager *sa_manager, if (!list_empty(&sa_manager->flist[i])) return true; - soffset = drm_suballoc_hole_soffset(sa_manager); - eoffset = drm_suballoc_hole_eoffset(sa_manager); + soffset = kcl_drm_suballoc_hole_soffset(sa_manager); + eoffset = kcl_drm_suballoc_hole_eoffset(sa_manager); wasted = round_up(soffset, align) - soffset; return ((eoffset - soffset) >= (size + wasted)); @@ -213,18 +213,18 @@ static bool __drm_suballoc_event(struct drm_suballoc_manager *sa_manager, * enough free memory to satisfy the allocation directly. * false otherwise. */ -static bool drm_suballoc_event(struct drm_suballoc_manager *sa_manager, +static bool kcl_drm_suballoc_event(struct drm_suballoc_manager *sa_manager, size_t size, size_t align) { bool ret; spin_lock(&sa_manager->wq.lock); - ret = __drm_suballoc_event(sa_manager, size, align); + ret = kcl___drm_suballoc_event(sa_manager, size, align); spin_unlock(&sa_manager->wq.lock); return ret; } -static bool drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, +static bool kcl_drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, struct dma_fence **fences, unsigned int *tries) { @@ -239,7 +239,7 @@ static bool drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, return true; } - soffset = drm_suballoc_hole_soffset(sa_manager); + soffset = kcl_drm_suballoc_hole_soffset(sa_manager); /* to handle wrap around we add sa_manager->size */ best = sa_manager->size * 2; /* go over all fence list and try to find the closest sa @@ -287,7 +287,7 @@ static bool drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, * We know that this one is signaled, * so it's safe to remove it. */ - drm_suballoc_remove_locked(best_bo); + kcl_drm_suballoc_remove_locked(best_bo); return true; } return false; @@ -313,7 +313,7 @@ static bool drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, * Return: a new suballocated bo, or an ERR_PTR. */ struct drm_suballoc * -drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, +kcl_drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, gfp_t gfp, bool intr, size_t align) { struct dma_fence *fences[DRM_SUBALLOC_MAX_QUEUES]; @@ -344,16 +344,16 @@ drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, tries[i] = 0; do { - drm_suballoc_try_free(sa_manager); + kcl_drm_suballoc_try_free(sa_manager); - if (drm_suballoc_try_alloc(sa_manager, sa, + if (kcl_drm_suballoc_try_alloc(sa_manager, sa, size, align)) { spin_unlock(&sa_manager->wq.lock); return sa; } /* see if we can skip over some allocations */ - } while (drm_suballoc_next_hole(sa_manager, fences, tries)); + } while (kcl_drm_suballoc_next_hole(sa_manager, fences, tries)); for (i = 0, count = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) if (fences[i]) @@ -375,11 +375,11 @@ drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, /* if we have nothing to wait for block */ r = wait_event_interruptible_locked (sa_manager->wq, - __drm_suballoc_event(sa_manager, size, align)); + kcl___drm_suballoc_event(sa_manager, size, align)); } else { spin_unlock(&sa_manager->wq.lock); wait_event(sa_manager->wq, - drm_suballoc_event(sa_manager, size, align)); + kcl_drm_suballoc_event(sa_manager, size, align)); r = 0; spin_lock(&sa_manager->wq.lock); } @@ -389,7 +389,7 @@ drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, kfree(sa); return ERR_PTR(r); } -EXPORT_SYMBOL(drm_suballoc_new); +EXPORT_SYMBOL(kcl_drm_suballoc_new); /** * drm_suballoc_free - Free a suballocation @@ -398,7 +398,7 @@ EXPORT_SYMBOL(drm_suballoc_new); * * Free the suballocation. The suballocation can be re-used after @fence signals. */ -void drm_suballoc_free(struct drm_suballoc *suballoc, +void kcl_drm_suballoc_free(struct drm_suballoc *suballoc, struct dma_fence *fence) { struct drm_suballoc_manager *sa_manager; @@ -416,15 +416,15 @@ void drm_suballoc_free(struct drm_suballoc *suballoc, idx = fence->context & (DRM_SUBALLOC_MAX_QUEUES - 1); list_add_tail(&suballoc->flist, &sa_manager->flist[idx]); } else { - drm_suballoc_remove_locked(suballoc); + kcl_drm_suballoc_remove_locked(suballoc); } wake_up_all_locked(&sa_manager->wq); spin_unlock(&sa_manager->wq.lock); } -EXPORT_SYMBOL(drm_suballoc_free); +EXPORT_SYMBOL(kcl_drm_suballoc_free); #ifdef CONFIG_DEBUG_FS -void drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, +void kcl_drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, struct drm_printer *p, unsigned long long suballoc_base) { @@ -453,7 +453,7 @@ void drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, } spin_unlock(&sa_manager->wq.lock); } -EXPORT_SYMBOL(drm_suballoc_dump_debug_info); +EXPORT_SYMBOL(kcl_drm_suballoc_dump_debug_info); #endif MODULE_AUTHOR("Multiple"); MODULE_DESCRIPTION("Range suballocator helper"); diff --git a/include/kcl/kcl_drm_suballoc.h b/include/kcl/kcl_drm_suballoc.h index 46c61883e392f..7629274cc4a0a 100644 --- a/include/kcl/kcl_drm_suballoc.h +++ b/include/kcl/kcl_drm_suballoc.h @@ -52,16 +52,21 @@ struct drm_suballoc { struct dma_fence *fence; }; -void drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, +#ifndef HAVE_DRM_SUBALLOC_MANAGER_INIT +void kcl_drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, size_t size, size_t align); +#define drm_suballoc_manager_init kcl_drm_suballoc_manager_init -void drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager); +void kcl_drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager); +#define drm_suballoc_manager_fini kcl_drm_suballoc_manager_fini struct drm_suballoc * -drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, +kcl_drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, gfp_t gfp, bool intr, size_t align); +#define drm_suballoc_new kcl_drm_suballoc_new -void drm_suballoc_free(struct drm_suballoc *sa, struct dma_fence *fence); +void kcl_drm_suballoc_free(struct drm_suballoc *sa, struct dma_fence *fence); +#define drm_suballoc_free kcl_drm_suballoc_free /** * drm_suballoc_soffset - Range start. @@ -69,10 +74,11 @@ void drm_suballoc_free(struct drm_suballoc *sa, struct dma_fence *fence); * * Return: The start of the allocated range. */ -static inline size_t drm_suballoc_soffset(struct drm_suballoc *sa) +static inline size_t kcl_drm_suballoc_soffset(struct drm_suballoc *sa) { return sa->soffset; } +#define drm_suballoc_soffset kcl_drm_suballoc_soffset /** * drm_suballoc_eoffset - Range end. @@ -80,10 +86,11 @@ static inline size_t drm_suballoc_soffset(struct drm_suballoc *sa) * * Return: The end of the allocated range + 1. */ -static inline size_t drm_suballoc_eoffset(struct drm_suballoc *sa) +static inline size_t kcl_drm_suballoc_eoffset(struct drm_suballoc *sa) { return sa->eoffset; } +#define drm_suballoc_eoffset kcl_drm_suballoc_eoffset /** * drm_suballoc_size - Range size. @@ -91,23 +98,27 @@ static inline size_t drm_suballoc_eoffset(struct drm_suballoc *sa) * * Return: The size of the allocated range. */ -static inline size_t drm_suballoc_size(struct drm_suballoc *sa) +static inline size_t kcl_drm_suballoc_size(struct drm_suballoc *sa) { return sa->eoffset - sa->soffset; } +#define drm_suballoc_size kcl_drm_suballoc_size #ifdef CONFIG_DEBUG_FS -void drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, +void kcl_drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, struct drm_printer *p, unsigned long long suballoc_base); #else static inline void -drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, +kcl_drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, struct drm_printer *p, unsigned long long suballoc_base) { } #endif +#define drm_suballoc_dump_debug_info kcl_drm_suballoc_dump_debug_info +#endif /* HAVE_DRM_SUBALLOC_MANAGER_INIT */ + #endif /*HAVE_DRM_DRM_SUBALLOC_H*/ #endif /* _KCL_DRM_SUBALLOC_H_ */ From b7c334e4f3606fdfeb79991887758b2e487044a0 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 23 Sep 2025 19:25:31 +0800 Subject: [PATCH 2104/2653] drm/amdkcl: fix detection of built-in drm_suballoc_helper The autoconf test added to probe for the presence of CONFIG_DRM_SUBALLOC_HELPER uses #ifdef, which is not visible to built-in code when the helper is configured as a module. As a result HAVE_DRM_SUBALLOC_MANAGER_INIT is never defined and amdgpu keeps its own duplicate implementation even when the kernel already provides one. Replace the #ifdef with IS_ENABLED() so that the test passes whenever the helper is enabled (y or m) and the KCL wrapper is dropped as intended. Reviewed-by: Bob Zhou Signed-off-by: Perry Yuan --- drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 index 46363385a7097..e735965113377 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 @@ -7,7 +7,7 @@ AC_DEFUN([AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - #ifdef CONFIG_DRM_SUBALLOC_HELPER + #if IS_ENABLED(CONFIG_DRM_SUBALLOC_HELPER) drm_suballoc_manager_init(NULL, 0, 0); #else #error CONFIG_DRM_SUBALLOC_HELPER is not enabled From 6f6e732aba0d8a488081c00ec9794bd681b92e13 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 23 Sep 2025 19:25:31 +0800 Subject: [PATCH 2105/2653] drm/amdkcl: fix detection of built-in drm_suballoc_helper The autoconf test added to probe for the presence of CONFIG_DRM_SUBALLOC_HELPER uses #ifdef, which is not visible to built-in code when the helper is configured as a module. As a result HAVE_DRM_SUBALLOC_MANAGER_INIT is never defined and amdgpu keeps its own duplicate implementation even when the kernel already provides one. Replace the #ifdef with IS_ENABLED() so that the test passes whenever the helper is enabled (y or m) and the KCL wrapper is dropped as intended. Reviewed-by: Bob Zhou Signed-off-by: Perry Yuan --- drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 index 46363385a7097..e735965113377 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 @@ -7,7 +7,7 @@ AC_DEFUN([AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - #ifdef CONFIG_DRM_SUBALLOC_HELPER + #if IS_ENABLED(CONFIG_DRM_SUBALLOC_HELPER) drm_suballoc_manager_init(NULL, 0, 0); #else #error CONFIG_DRM_SUBALLOC_HELPER is not enabled From 98a79e6ed868d84f81c19827e4af7512a3e84596 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 24 Sep 2025 13:36:49 +0800 Subject: [PATCH 2106/2653] =?UTF-8?q?drm/amdkcl=EF=BC=9AAdd=20kcl=5F=20pre?= =?UTF-8?q?fix=20to=20fake=20drm=5Fsuballoc=5F*=20functions=20for=20avoid?= =?UTF-8?q?=20symbol=20conflict?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit KCL's fake drm_suballoc_* implementations may conflict with upstream DRM symbols,causing module loading issues Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c | 72 +++++++++---------- include/kcl/kcl_drm_suballoc.h | 29 +++++--- 2 files changed, 56 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c index 8ad6e3d9b60eb..c0dcc45d0666f 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c @@ -50,8 +50,8 @@ #include #ifndef HAVE_DRM_SUBALLOC_MANAGER_INIT -static void drm_suballoc_remove_locked(struct drm_suballoc *sa); -static void drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager); +static void kcl_drm_suballoc_remove_locked(struct drm_suballoc *sa); +static void kcl_drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager); /** * drm_suballoc_manager_init() - Initialise the drm_suballoc_manager @@ -61,7 +61,7 @@ static void drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager); * * Prepares the suballocation manager for suballocations. */ -void drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, +void kcl_drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, size_t size, size_t align) { unsigned int i; @@ -83,7 +83,7 @@ void drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) INIT_LIST_HEAD(&sa_manager->flist[i]); } -EXPORT_SYMBOL(drm_suballoc_manager_init); +EXPORT_SYMBOL(kcl_drm_suballoc_manager_init); /** * drm_suballoc_manager_fini() - Destroy the drm_suballoc_manager @@ -93,7 +93,7 @@ EXPORT_SYMBOL(drm_suballoc_manager_init); * with drm_suballoc_free() must be signaled, or we cannot clean up * the entire manager. */ -void drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager) +void kcl_drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager) { struct drm_suballoc *sa, *tmp; @@ -102,19 +102,19 @@ void drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager) if (!list_empty(&sa_manager->olist)) { sa_manager->hole = &sa_manager->olist; - drm_suballoc_try_free(sa_manager); + kcl_drm_suballoc_try_free(sa_manager); if (!list_empty(&sa_manager->olist)) DRM_ERROR("sa_manager is not empty, clearing anyway\n"); } list_for_each_entry_safe(sa, tmp, &sa_manager->olist, olist) { - drm_suballoc_remove_locked(sa); + kcl_drm_suballoc_remove_locked(sa); } sa_manager->size = 0; } -EXPORT_SYMBOL(drm_suballoc_manager_fini); +EXPORT_SYMBOL(kcl_drm_suballoc_manager_fini); -static void drm_suballoc_remove_locked(struct drm_suballoc *sa) +static void kcl_drm_suballoc_remove_locked(struct drm_suballoc *sa) { struct drm_suballoc_manager *sa_manager = sa->manager; @@ -127,7 +127,7 @@ static void drm_suballoc_remove_locked(struct drm_suballoc *sa) kfree(sa); } -static void drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager) +static void kcl_drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager) { struct drm_suballoc *sa, *tmp; @@ -139,11 +139,11 @@ static void drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager) if (!sa->fence || !dma_fence_is_signaled(sa->fence)) return; - drm_suballoc_remove_locked(sa); + kcl_drm_suballoc_remove_locked(sa); } } -static size_t drm_suballoc_hole_soffset(struct drm_suballoc_manager *sa_manager) +static size_t kcl_drm_suballoc_hole_soffset(struct drm_suballoc_manager *sa_manager) { struct list_head *hole = sa_manager->hole; @@ -153,7 +153,7 @@ static size_t drm_suballoc_hole_soffset(struct drm_suballoc_manager *sa_manager) return 0; } -static size_t drm_suballoc_hole_eoffset(struct drm_suballoc_manager *sa_manager) +static size_t kcl_drm_suballoc_hole_eoffset(struct drm_suballoc_manager *sa_manager) { struct list_head *hole = sa_manager->hole; @@ -162,14 +162,14 @@ static size_t drm_suballoc_hole_eoffset(struct drm_suballoc_manager *sa_manager) return sa_manager->size; } -static bool drm_suballoc_try_alloc(struct drm_suballoc_manager *sa_manager, +static bool kcl_drm_suballoc_try_alloc(struct drm_suballoc_manager *sa_manager, struct drm_suballoc *sa, size_t size, size_t align) { size_t soffset, eoffset, wasted; - soffset = drm_suballoc_hole_soffset(sa_manager); - eoffset = drm_suballoc_hole_eoffset(sa_manager); + soffset = kcl_drm_suballoc_hole_soffset(sa_manager); + eoffset = kcl_drm_suballoc_hole_eoffset(sa_manager); wasted = round_up(soffset, align) - soffset; if ((eoffset - soffset) >= (size + wasted)) { @@ -186,7 +186,7 @@ static bool drm_suballoc_try_alloc(struct drm_suballoc_manager *sa_manager, return false; } -static bool __drm_suballoc_event(struct drm_suballoc_manager *sa_manager, +static bool kcl___drm_suballoc_event(struct drm_suballoc_manager *sa_manager, size_t size, size_t align) { size_t soffset, eoffset, wasted; @@ -196,8 +196,8 @@ static bool __drm_suballoc_event(struct drm_suballoc_manager *sa_manager, if (!list_empty(&sa_manager->flist[i])) return true; - soffset = drm_suballoc_hole_soffset(sa_manager); - eoffset = drm_suballoc_hole_eoffset(sa_manager); + soffset = kcl_drm_suballoc_hole_soffset(sa_manager); + eoffset = kcl_drm_suballoc_hole_eoffset(sa_manager); wasted = round_up(soffset, align) - soffset; return ((eoffset - soffset) >= (size + wasted)); @@ -213,18 +213,18 @@ static bool __drm_suballoc_event(struct drm_suballoc_manager *sa_manager, * enough free memory to satisfy the allocation directly. * false otherwise. */ -static bool drm_suballoc_event(struct drm_suballoc_manager *sa_manager, +static bool kcl_drm_suballoc_event(struct drm_suballoc_manager *sa_manager, size_t size, size_t align) { bool ret; spin_lock(&sa_manager->wq.lock); - ret = __drm_suballoc_event(sa_manager, size, align); + ret = kcl___drm_suballoc_event(sa_manager, size, align); spin_unlock(&sa_manager->wq.lock); return ret; } -static bool drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, +static bool kcl_drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, struct dma_fence **fences, unsigned int *tries) { @@ -239,7 +239,7 @@ static bool drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, return true; } - soffset = drm_suballoc_hole_soffset(sa_manager); + soffset = kcl_drm_suballoc_hole_soffset(sa_manager); /* to handle wrap around we add sa_manager->size */ best = sa_manager->size * 2; /* go over all fence list and try to find the closest sa @@ -287,7 +287,7 @@ static bool drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, * We know that this one is signaled, * so it's safe to remove it. */ - drm_suballoc_remove_locked(best_bo); + kcl_drm_suballoc_remove_locked(best_bo); return true; } return false; @@ -313,7 +313,7 @@ static bool drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, * Return: a new suballocated bo, or an ERR_PTR. */ struct drm_suballoc * -drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, +kcl_drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, gfp_t gfp, bool intr, size_t align) { struct dma_fence *fences[DRM_SUBALLOC_MAX_QUEUES]; @@ -344,16 +344,16 @@ drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, tries[i] = 0; do { - drm_suballoc_try_free(sa_manager); + kcl_drm_suballoc_try_free(sa_manager); - if (drm_suballoc_try_alloc(sa_manager, sa, + if (kcl_drm_suballoc_try_alloc(sa_manager, sa, size, align)) { spin_unlock(&sa_manager->wq.lock); return sa; } /* see if we can skip over some allocations */ - } while (drm_suballoc_next_hole(sa_manager, fences, tries)); + } while (kcl_drm_suballoc_next_hole(sa_manager, fences, tries)); for (i = 0, count = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) if (fences[i]) @@ -375,11 +375,11 @@ drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, /* if we have nothing to wait for block */ r = wait_event_interruptible_locked (sa_manager->wq, - __drm_suballoc_event(sa_manager, size, align)); + kcl___drm_suballoc_event(sa_manager, size, align)); } else { spin_unlock(&sa_manager->wq.lock); wait_event(sa_manager->wq, - drm_suballoc_event(sa_manager, size, align)); + kcl_drm_suballoc_event(sa_manager, size, align)); r = 0; spin_lock(&sa_manager->wq.lock); } @@ -389,7 +389,7 @@ drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, kfree(sa); return ERR_PTR(r); } -EXPORT_SYMBOL(drm_suballoc_new); +EXPORT_SYMBOL(kcl_drm_suballoc_new); /** * drm_suballoc_free - Free a suballocation @@ -398,7 +398,7 @@ EXPORT_SYMBOL(drm_suballoc_new); * * Free the suballocation. The suballocation can be re-used after @fence signals. */ -void drm_suballoc_free(struct drm_suballoc *suballoc, +void kcl_drm_suballoc_free(struct drm_suballoc *suballoc, struct dma_fence *fence) { struct drm_suballoc_manager *sa_manager; @@ -416,15 +416,15 @@ void drm_suballoc_free(struct drm_suballoc *suballoc, idx = fence->context & (DRM_SUBALLOC_MAX_QUEUES - 1); list_add_tail(&suballoc->flist, &sa_manager->flist[idx]); } else { - drm_suballoc_remove_locked(suballoc); + kcl_drm_suballoc_remove_locked(suballoc); } wake_up_all_locked(&sa_manager->wq); spin_unlock(&sa_manager->wq.lock); } -EXPORT_SYMBOL(drm_suballoc_free); +EXPORT_SYMBOL(kcl_drm_suballoc_free); #ifdef CONFIG_DEBUG_FS -void drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, +void kcl_drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, struct drm_printer *p, unsigned long long suballoc_base) { @@ -453,7 +453,7 @@ void drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, } spin_unlock(&sa_manager->wq.lock); } -EXPORT_SYMBOL(drm_suballoc_dump_debug_info); +EXPORT_SYMBOL(kcl_drm_suballoc_dump_debug_info); #endif MODULE_AUTHOR("Multiple"); MODULE_DESCRIPTION("Range suballocator helper"); diff --git a/include/kcl/kcl_drm_suballoc.h b/include/kcl/kcl_drm_suballoc.h index 46c61883e392f..7629274cc4a0a 100644 --- a/include/kcl/kcl_drm_suballoc.h +++ b/include/kcl/kcl_drm_suballoc.h @@ -52,16 +52,21 @@ struct drm_suballoc { struct dma_fence *fence; }; -void drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, +#ifndef HAVE_DRM_SUBALLOC_MANAGER_INIT +void kcl_drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, size_t size, size_t align); +#define drm_suballoc_manager_init kcl_drm_suballoc_manager_init -void drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager); +void kcl_drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager); +#define drm_suballoc_manager_fini kcl_drm_suballoc_manager_fini struct drm_suballoc * -drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, +kcl_drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, gfp_t gfp, bool intr, size_t align); +#define drm_suballoc_new kcl_drm_suballoc_new -void drm_suballoc_free(struct drm_suballoc *sa, struct dma_fence *fence); +void kcl_drm_suballoc_free(struct drm_suballoc *sa, struct dma_fence *fence); +#define drm_suballoc_free kcl_drm_suballoc_free /** * drm_suballoc_soffset - Range start. @@ -69,10 +74,11 @@ void drm_suballoc_free(struct drm_suballoc *sa, struct dma_fence *fence); * * Return: The start of the allocated range. */ -static inline size_t drm_suballoc_soffset(struct drm_suballoc *sa) +static inline size_t kcl_drm_suballoc_soffset(struct drm_suballoc *sa) { return sa->soffset; } +#define drm_suballoc_soffset kcl_drm_suballoc_soffset /** * drm_suballoc_eoffset - Range end. @@ -80,10 +86,11 @@ static inline size_t drm_suballoc_soffset(struct drm_suballoc *sa) * * Return: The end of the allocated range + 1. */ -static inline size_t drm_suballoc_eoffset(struct drm_suballoc *sa) +static inline size_t kcl_drm_suballoc_eoffset(struct drm_suballoc *sa) { return sa->eoffset; } +#define drm_suballoc_eoffset kcl_drm_suballoc_eoffset /** * drm_suballoc_size - Range size. @@ -91,23 +98,27 @@ static inline size_t drm_suballoc_eoffset(struct drm_suballoc *sa) * * Return: The size of the allocated range. */ -static inline size_t drm_suballoc_size(struct drm_suballoc *sa) +static inline size_t kcl_drm_suballoc_size(struct drm_suballoc *sa) { return sa->eoffset - sa->soffset; } +#define drm_suballoc_size kcl_drm_suballoc_size #ifdef CONFIG_DEBUG_FS -void drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, +void kcl_drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, struct drm_printer *p, unsigned long long suballoc_base); #else static inline void -drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, +kcl_drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, struct drm_printer *p, unsigned long long suballoc_base) { } #endif +#define drm_suballoc_dump_debug_info kcl_drm_suballoc_dump_debug_info +#endif /* HAVE_DRM_SUBALLOC_MANAGER_INIT */ + #endif /*HAVE_DRM_DRM_SUBALLOC_H*/ #endif /* _KCL_DRM_SUBALLOC_H_ */ From 29aa76941995181bda84617ee83fe0bac6e0f7e9 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Tue, 16 Sep 2025 21:21:15 +0800 Subject: [PATCH 2107/2653] amd/amdkfd: resolve a race in amdgpu_amdkfd_device_fini_sw There is race in amdgpu_amdkfd_device_fini_sw and interrupt. if amdgpu_amdkfd_device_fini_sw run in b/w kfd_cleanup_nodes and kfree(kfd), and KGD interrupt generated. kernel panic log: BUG: kernel NULL pointer dereference, address: 0000000000000098 amdgpu 0000:c8:00.0: amdgpu: Requesting 4 partitions through PSP PGD d78c68067 P4D d78c68067 kfd kfd: amdgpu: Allocated 3969056 bytes on gart PUD 1465b8067 PMD @ Oops: @002 [#1] SMP NOPTI kfd kfd: amdgpu: Total number of KFD nodes to be created: 4 CPU: 115 PID: @ Comm: swapper/115 Kdump: loaded Tainted: G S W OE K RIP: 0010:_raw_spin_lock_irqsave+0x12/0x40 Code: 89 e@ 41 5c c3 cc cc cc cc 66 66 2e Of 1f 84 00 00 00 00 00 OF 1f 40 00 Of 1f 44% 00 00 41 54 9c 41 5c fa 31 cO ba 01 00 00 00 OF b1 17 75 Ba 4c 89 e@ 41 Sc 89 c6 e8 07 38 5d RSP: 0018: ffffc90@1a6b0e28 EFLAGS: 00010046 RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000018 0000000000000001 RSI: ffff8883bb623e00 RDI: 0000000000000098 ffff8883bb000000 RO8: ffff888100055020 ROO: ffff888100055020 0000000000000000 R11: 0000000000000000 R12: 0900000000000002 ffff888F2b97da0@ R14: @000000000000098 R15: ffff8883babdfo00 CS: 010 DS: 0000 ES: 0000 CRO: 0000000080050033 CR2: 0000000000000098 CR3: 0000000e7cae2006 CR4: 0000000002770ce0 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 0000000000000000 DR6: 00000000fffeO7FO DR7: 0000000000000400 PKRU: 55555554 Call Trace: kgd2kfd_interrupt+@x6b/0x1f@ [amdgpu] ? amdgpu_fence_process+0xa4/0x150 [amdgpu] kfd kfd: amdgpu: Node: 0, interrupt_bitmap: 3 YcpxFl Rant tErace amdgpu_irq_dispatch+0x165/0x210 [amdgpu] amdgpu_ih_process+0x80/0x100 [amdgpu] amdgpu: Virtual CRAT table created for GPU amdgpu_irq_handler+0x1f/@x60 [amdgpu] __handle_irq_event_percpu+0x3d/0x170 amdgpu: Topology: Add dGPU node [0x74a2:0x1002] handle_irq_event+0x5a/@xcO handle_edge_irq+0x93/0x240 kfd kfd: amdgpu: KFD node 1 partition @ size 49148M asm_call_irq_on_stack+0xf/@x20 common_interrupt+0xb3/0x130 asm_common_interrupt+0x1le/0x40 5.10.134-010.a1i5000.a18.x86_64 #1 Signed-off-by: Yifan Zhang Reviewed-by: Philip Yang --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 944e8372e9e9b..d1803abbd5f6d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -1155,7 +1155,15 @@ void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) } for (i = 0; i < kfd->num_nodes; i++) { - node = kfd->nodes[i]; + /* Race if another thread in b/w + * kfd_cleanup_nodes and kfree(kfd), + * when kfd->nodes[i] = NULL + */ + if (kfd->nodes[i]) + node = kfd->nodes[i]; + else + return; + spin_lock_irqsave(&node->interrupt_lock, flags); if (node->interrupts_active From e9ae609b13a8932a30060e414707a209e24125b6 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 24 Mar 2025 15:12:07 +0800 Subject: [PATCH 2108/2653] drm/amd/ras: Add amdgpu nbio v7_9 configuration function Add amdgpu nbio v7_9 configuration function. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/ras/ras_mgr/Makefile | 0 .../amd/ras/ras_mgr/amdgpu_ras_nbio_v7_9.c | 125 ++++++++++++++++++ .../amd/ras/ras_mgr/amdgpu_ras_nbio_v7_9.h | 30 +++++ 3 files changed, 155 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/Makefile create mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_nbio_v7_9.c create mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_nbio_v7_9.h diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/Makefile b/drivers/gpu/drm/amd/ras/ras_mgr/Makefile new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_nbio_v7_9.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_nbio_v7_9.c new file mode 100644 index 0000000000000..2783f5875c7c1 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_nbio_v7_9.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "amdgpu_ras_mgr.h" +#include "amdgpu_ras_nbio_v7_9.h" +#include "nbio/nbio_7_9_0_offset.h" +#include "nbio/nbio_7_9_0_sh_mask.h" +#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" + +static int nbio_v7_9_set_ras_controller_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + /* Dummy function, there is no initialization operation in driver */ + + return 0; +} + +static int nbio_v7_9_process_ras_controller_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + /* By design, the ih cookie for ras_controller_irq should be written + * to BIFring instead of general iv ring. However, due to known bif ring + * hw bug, it has to be disabled. There is no chance the process function + * will be involked. Just left it as a dummy one. + */ + return 0; +} + +static int nbio_v7_9_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + /* Dummy function, there is no initialization operation in driver */ + + return 0; +} + +static int nbio_v7_9_process_err_event_athub_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + /* By design, the ih cookie for err_event_athub_irq should be written + * to BIFring instead of general iv ring. However, due to known bif ring + * hw bug, it has to be disabled. There is no chance the process function + * will be involked. Just left it as a dummy one. + */ + return 0; +} + +static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_controller_irq_funcs = { + .set = nbio_v7_9_set_ras_controller_irq_state, + .process = nbio_v7_9_process_ras_controller_irq, +}; + +static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_err_event_athub_irq_funcs = { + .set = nbio_v7_9_set_ras_err_event_athub_irq_state, + .process = nbio_v7_9_process_err_event_athub_irq, +}; + +static int nbio_v7_9_init_ras_controller_interrupt(struct ras_core_context *ras_core, bool state) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + int r; + + /* init the irq funcs */ + adev->nbio.ras_controller_irq.funcs = + &nbio_v7_9_ras_controller_irq_funcs; + adev->nbio.ras_controller_irq.num_types = 1; + + /* register ras controller interrupt */ + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, + NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT, + &adev->nbio.ras_controller_irq); + + return r; +} + +static int nbio_v7_9_init_ras_err_event_athub_interrupt(struct ras_core_context *ras_core, + bool state) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + int r; + + /* init the irq funcs */ + adev->nbio.ras_err_event_athub_irq.funcs = + &nbio_v7_9_ras_err_event_athub_irq_funcs; + adev->nbio.ras_err_event_athub_irq.num_types = 1; + + /* register ras err event athub interrupt */ + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, + NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT, + &adev->nbio.ras_err_event_athub_irq); + + return r; +} + +const struct ras_nbio_sys_func amdgpu_ras_nbio_sys_func_v7_9 = { + .set_ras_controller_irq_state = nbio_v7_9_init_ras_controller_interrupt, + .set_ras_err_event_athub_irq_state = nbio_v7_9_init_ras_err_event_athub_interrupt, +}; diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_nbio_v7_9.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_nbio_v7_9.h new file mode 100644 index 0000000000000..272259e9a0e75 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_nbio_v7_9.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __AMDGPU_RAS_NBIO_V7_9_H__ +#define __AMDGPU_RAS_NBIO_V7_9_H__ + +extern const struct ras_nbio_sys_func amdgpu_ras_nbio_sys_func_v7_9; + +#endif From cb0bf341d24fc061e3d26326b93a14218f4a0853 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 17:59:25 +0800 Subject: [PATCH 2109/2653] drm/amd/ras: Add amdgpu mp1 v13_0 configuration function Add amdgpu mp1 v13_0 configuration function. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- .../amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c | 94 +++++++++++++++++++ .../amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.h | 30 ++++++ 2 files changed, 124 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c create mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.h diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c new file mode 100644 index 0000000000000..79a51b1603ac1 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu_smu.h" +#include "amdgpu_reset.h" +#include "amdgpu_ras_mp1_v13_0.h" + +#define RAS_MP1_MSG_QueryValidMcaCeCount 0x3A +#define RAS_MP1_MSG_McaBankCeDumpDW 0x3B + +static int mp1_v13_0_get_valid_bank_count(struct ras_core_context *ras_core, + u32 msg, u32 *count) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + u32 smu_msg; + int ret = 0; + + if (!count) + return -EINVAL; + + smu_msg = (msg == RAS_MP1_MSG_QueryValidMcaCeCount) ? + SMU_MSG_QueryValidMcaCeCount : SMU_MSG_QueryValidMcaCount; + + if (down_read_trylock(&adev->reset_domain->sem)) { + ret = amdgpu_smu_ras_send_msg(adev, smu_msg, 0, count); + up_read(&adev->reset_domain->sem); + } else { + ret = -RAS_CORE_GPU_IN_MODE1_RESET; + } + + if (ret) + *count = 0; + + return ret; +} + +static int mp1_v13_0_dump_valid_bank(struct ras_core_context *ras_core, + u32 msg, u32 idx, u32 reg_idx, u64 *val) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + uint32_t data[2] = {0, 0}; + uint32_t param; + int ret = 0; + int i, offset; + u32 smu_msg = (msg == RAS_MP1_MSG_McaBankCeDumpDW) ? + SMU_MSG_McaBankCeDumpDW : SMU_MSG_McaBankDumpDW; + + if (down_read_trylock(&adev->reset_domain->sem)) { + offset = reg_idx * 8; + for (i = 0; i < ARRAY_SIZE(data); i++) { + param = ((idx & 0xffff) << 16) | ((offset + (i << 2)) & 0xfffc); + ret = amdgpu_smu_ras_send_msg(adev, smu_msg, param, &data[i]); + if (ret) { + RAS_DEV_ERR(adev, "ACA failed to read register[%d], offset:0x%x\n", + reg_idx, offset); + break; + } + } + up_read(&adev->reset_domain->sem); + + if (!ret) + *val = (uint64_t)data[1] << 32 | data[0]; + } else { + ret = -RAS_CORE_GPU_IN_MODE1_RESET; + } + + return ret; +} + +const struct ras_mp1_sys_func amdgpu_ras_mp1_sys_func_v13_0 = { + .mp1_get_valid_bank_count = mp1_v13_0_get_valid_bank_count, + .mp1_dump_valid_bank = mp1_v13_0_dump_valid_bank, +}; + diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.h new file mode 100644 index 0000000000000..71c614ae1ae45 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __AMDGPU_RAS_MP1_V13_0_H__ +#define __AMDGPU_RAS_MP1_V13_0_H__ +#include "ras.h" + +extern const struct ras_mp1_sys_func amdgpu_ras_mp1_sys_func_v13_0; + +#endif From a072a682f7b7bf959de47986f3fc0c8ab066dbd1 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 18:00:48 +0800 Subject: [PATCH 2110/2653] drm/amd/ras: Add amdgpu eeprom i2c configuration function Add amdgpu eeprom i2c configuration function. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- .../amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.c | 181 ++++++++++++++++++ .../amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.h | 27 +++ 2 files changed, 208 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.c create mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.h diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.c new file mode 100644 index 0000000000000..1bb7b7001ec7e --- /dev/null +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.c @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "amdgpu.h" +#include "amdgpu_atomfirmware.h" +#include "amdgpu_ras_eeprom.h" +#include "amdgpu_ras_mgr.h" +#include "amdgpu_ras_eeprom_i2c.h" +#include "ras_eeprom.h" + +/* These are memory addresses as would be seen by one or more EEPROM + * chips strung on the I2C bus, usually by manipulating pins 1-3 of a + * set of EEPROM devices. They form a continuous memory space. + * + * The I2C device address includes the device type identifier, 1010b, + * which is a reserved value and indicates that this is an I2C EEPROM + * device. It also includes the top 3 bits of the 19 bit EEPROM memory + * address, namely bits 18, 17, and 16. This makes up the 7 bit + * address sent on the I2C bus with bit 0 being the direction bit, + * which is not represented here, and sent by the hardware directly. + * + * For instance, + * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. + * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. + * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. + * Depending on the size of the I2C EEPROM device(s), bits 18:16 may + * address memory in a device or a device on the I2C bus, depending on + * the status of pins 1-3. See top of amdgpu_eeprom.c. + * + * The RAS table lives either at address 0 or address 40000h of EEPROM. + */ +#define EEPROM_I2C_MADDR_0 0x0 +#define EEPROM_I2C_MADDR_4 0x40000 + +#define MAKE_I2C_ADDR(_aa) ((0xA << 3) | (((_aa) >> 16) & 0xF)) +#define to_amdgpu_ras(x) (container_of(x, struct amdgpu_ras, eeprom_control)) + +#define EEPROM_PAGE_BITS 8 +#define EEPROM_PAGE_SIZE (1U << EEPROM_PAGE_BITS) +#define EEPROM_PAGE_MASK (EEPROM_PAGE_SIZE - 1) + +#define EEPROM_OFFSET_SIZE 2 + +static int ras_eeprom_i2c_config(struct ras_core_context *ras_core) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + struct ras_eeprom_control *control = &ras_core->ras_eeprom; + u8 i2c_addr; + + if (amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) { + /* The address given by VBIOS is an 8-bit, wire-format + * address, i.e. the most significant byte. + * + * Normalize it to a 19-bit EEPROM address. Remove the + * device type identifier and make it a 7-bit address; + * then make it a 19-bit EEPROM address. See top of + * amdgpu_eeprom.c. + */ + i2c_addr = (i2c_addr & 0x0F) >> 1; + control->i2c_address = ((u32) i2c_addr) << 16; + return 0; + } + + switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { + case IP_VERSION(13, 0, 5): + case IP_VERSION(13, 0, 6): + case IP_VERSION(13, 0, 10): + case IP_VERSION(13, 0, 14): + control->i2c_address = EEPROM_I2C_MADDR_4; + return 0; + default: + return -ENODATA; + } + return -ENODATA; +} + +static int ras_eeprom_i2c_xfer(struct ras_core_context *ras_core, u32 eeprom_addr, + u8 *eeprom_buf, u32 buf_size, bool read) +{ + struct i2c_adapter *i2c_adap = ras_core->ras_eeprom.i2c_adapter; + u8 eeprom_offset_buf[EEPROM_OFFSET_SIZE]; + struct i2c_msg msgs[] = { + { + .flags = 0, + .len = EEPROM_OFFSET_SIZE, + .buf = eeprom_offset_buf, + }, + { + .flags = read ? I2C_M_RD : 0, + }, + }; + const u8 *p = eeprom_buf; + int r; + u16 len; + + for (r = 0; buf_size > 0; + buf_size -= len, eeprom_addr += len, eeprom_buf += len) { + /* Set the EEPROM address we want to write to/read from. + */ + msgs[0].addr = MAKE_I2C_ADDR(eeprom_addr); + msgs[1].addr = msgs[0].addr; + msgs[0].buf[0] = (eeprom_addr >> 8) & 0xff; + msgs[0].buf[1] = eeprom_addr & 0xff; + + if (!read) { + /* Write the maximum amount of data, without + * crossing the device's page boundary, as per + * its spec. Partial page writes are allowed, + * starting at any location within the page, + * so long as the page boundary isn't crossed + * over (actually the page pointer rolls + * over). + * + * As per the AT24CM02 EEPROM spec, after + * writing into a page, the I2C driver should + * terminate the transfer, i.e. in + * "i2c_transfer()" below, with a STOP + * condition, so that the self-timed write + * cycle begins. This is implied for the + * "i2c_transfer()" abstraction. + */ + len = min(EEPROM_PAGE_SIZE - (eeprom_addr & EEPROM_PAGE_MASK), + buf_size); + } else { + /* Reading from the EEPROM has no limitation + * on the number of bytes read from the EEPROM + * device--they are simply sequenced out. + * Keep in mind that i2c_msg.len is u16 type. + */ + len = min(U16_MAX, buf_size); + } + msgs[1].len = len; + msgs[1].buf = eeprom_buf; + + + /* This constitutes a START-STOP transaction. + */ + r = i2c_transfer(i2c_adap, msgs, ARRAY_SIZE(msgs)); + if (r != ARRAY_SIZE(msgs)) + break; + + if (!read) { + /* According to EEPROM specs the length of the + * self-writing cycle, tWR (tW), is 10 ms. + * + * TODO: Use polling on ACK, aka Acknowledge + * Polling, to minimize waiting for the + * internal write cycle to complete, as it is + * usually smaller than tWR (tW). + */ + msleep(10); + } + } + + return r < 0 ? r : eeprom_buf - p; +} + +const struct ras_eeprom_sys_func amdgpu_ras_eeprom_i2c_sys_func = { + .eeprom_i2c_xfer = ras_eeprom_i2c_xfer, + .update_eeprom_i2c_config = ras_eeprom_i2c_config, +}; diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.h new file mode 100644 index 0000000000000..3b58786054115 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDGPU_RAS_EEPROM_I2C_H__ +#define __AMDGPU_RAS_EEPROM_I2C_H__ +#include "ras.h" + +extern const struct ras_eeprom_sys_func amdgpu_ras_eeprom_i2c_sys_func; +#endif From cc2a837b5872e69f775e9c481021d17342842607 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 18:02:13 +0800 Subject: [PATCH 2111/2653] drm/amd/ras: Amdgpu handle ras ioctl command Amdgpu handle ras ioctl command. V2: Remove non-standard device information. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c | 363 ++++++++++++++++++ .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h | 55 +++ 2 files changed, 418 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c create mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c new file mode 100644 index 0000000000000..195ca51a96d5a --- /dev/null +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c @@ -0,0 +1,363 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include "amdgpu.h" +#include "amdgpu_ras.h" +#include "ras_sys.h" +#include "amdgpu_ras_cmd.h" +#include "amdgpu_ras_mgr.h" + +/* inject address is 52 bits */ +#define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) + +#define AMDGPU_RAS_TYPE_RASCORE 0x1 +#define AMDGPU_RAS_TYPE_AMDGPU 0x2 +#define AMDGPU_RAS_TYPE_VF 0x3 + +static int amdgpu_ras_query_interface_info(struct ras_core_context *ras_core, + struct ras_cmd_ioctl *cmd) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + struct ras_query_interface_info_rsp *output_data = + (struct ras_query_interface_info_rsp *)cmd->output_buff_raw; + int ret; + + if (cmd->input_size != sizeof(struct ras_query_interface_info_req)) + return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + + ret = ras_cmd_query_interface_info(ras_core, output_data); + if (!ret) { + output_data->plat_major_ver = 0; + output_data->plat_minor_ver = 0; + + output_data->interface_type = amdgpu_sriov_vf(adev) ? + RAS_CMD_INTERFACE_TYPE_VF : RAS_CMD_INTERFACE_TYPE_AMDGPU; + + cmd->output_size = sizeof(struct ras_query_interface_info_rsp); + } + + return ret; +} + +static struct ras_core_context *ras_cmd_get_ras_core(uint64_t dev_handle) +{ + struct ras_core_context *ras_core; + + if (!dev_handle || (dev_handle == RAS_CMD_DEV_HANDLE_MAGIC)) + return NULL; + + ras_core = (struct ras_core_context *)(dev_handle ^ RAS_CMD_DEV_HANDLE_MAGIC); + + if (ras_cmd_get_dev_handle(ras_core) == dev_handle) + return ras_core; + + return NULL; +} + +static int amdgpu_ras_get_devices_info(struct ras_core_context *ras_core, + struct ras_cmd_ioctl *cmd) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + struct ras_cmd_devices_info_rsp *output_data = + (struct ras_cmd_devices_info_rsp *)cmd->output_buff_raw; + struct ras_cmd_dev_info *dev_info; + + dev_info = &output_data->devs[0]; + dev_info->dev_handle = ras_cmd_get_dev_handle(ras_core); + dev_info->oam_id = adev->smuio.funcs->get_socket_id(adev); + dev_info->ecc_enabled = 1; + dev_info->ecc_supported = 1; + + output_data->dev_num = 1; + output_data->version = 0; + cmd->output_size = sizeof(struct ras_cmd_devices_info_rsp); + + return 0; +} + +static int amdgpu_ras_trigger_error_prepare(struct ras_core_context *ras_core, + struct ras_cmd_inject_error_req *block_info) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + int ret; + + if (block_info->block_id == TA_RAS_BLOCK__XGMI_WAFL) { + if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) + RAS_DEV_WARN(adev, "Failed to disallow df cstate"); + + ret = amdgpu_dpm_set_pm_policy(adev, PP_PM_POLICY_XGMI_PLPD, XGMI_PLPD_DISALLOW); + if (ret && (ret != -EOPNOTSUPP)) + RAS_DEV_WARN(adev, "Failed to disallow XGMI power down"); + } + + return 0; +} + +static int amdgpu_ras_trigger_error_end(struct ras_core_context *ras_core, + struct ras_cmd_inject_error_req *block_info) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + int ret; + + if (block_info->block_id == TA_RAS_BLOCK__XGMI_WAFL) { + if (amdgpu_ras_intr_triggered()) + return 0; + + ret = amdgpu_dpm_set_pm_policy(adev, PP_PM_POLICY_XGMI_PLPD, XGMI_PLPD_DEFAULT); + if (ret && (ret != -EOPNOTSUPP)) + RAS_DEV_WARN(adev, "Failed to allow XGMI power down"); + + if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW)) + RAS_DEV_WARN(adev, "Failed to allow df cstate"); + } + + return 0; +} + +static uint64_t local_addr_to_xgmi_global_addr(struct ras_core_context *ras_core, + uint64_t addr) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + struct amdgpu_xgmi *xgmi = &adev->gmc.xgmi; + + return (addr + xgmi->physical_node_id * xgmi->node_segment_size); +} + +static int amdgpu_ras_inject_error(struct ras_core_context *ras_core, + struct ras_cmd_ioctl *cmd, void *data) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + struct ras_cmd_inject_error_req *req = + (struct ras_cmd_inject_error_req *)cmd->input_buff_raw; + int ret = RAS_CMD__ERROR_GENERIC; + + if (req->block_id == RAS_BLOCK_ID__UMC) { + if (amdgpu_ras_mgr_check_retired_addr(adev, req->address)) { + RAS_DEV_WARN(ras_core->dev, + "RAS WARN: inject: 0x%llx has already been marked as bad!\n", + req->address); + return RAS_CMD__ERROR_ACCESS_DENIED; + } + + if ((req->address >= adev->gmc.mc_vram_size && + adev->gmc.mc_vram_size) || + (req->address >= RAS_UMC_INJECT_ADDR_LIMIT)) { + RAS_DEV_WARN(adev, "RAS WARN: input address 0x%llx is invalid.", + req->address); + return RAS_CMD__ERROR_INVALID_INPUT_DATA; + } + + /* Calculate XGMI relative offset */ + if (adev->gmc.xgmi.num_physical_nodes > 1 && + req->block_id != RAS_BLOCK_ID__GFX) { + req->address = local_addr_to_xgmi_global_addr(ras_core, req->address); + } + } + + amdgpu_ras_trigger_error_prepare(ras_core, req); + ret = rascore_handle_cmd(ras_core, cmd, data); + amdgpu_ras_trigger_error_end(ras_core, req); + if (ret) { + RAS_DEV_ERR(adev, "ras inject block %u failed %d\n", req->block_id, ret); + ret = RAS_CMD__ERROR_ACCESS_DENIED; + } + + + return ret; +} + +static int amdgpu_ras_get_ras_safe_fb_addr_ranges(struct ras_core_context *ras_core, + struct ras_cmd_ioctl *cmd, void *data) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + struct ras_cmd_dev_handle *input_data = + (struct ras_cmd_dev_handle *)cmd->input_buff_raw; + struct ras_cmd_ras_safe_fb_address_ranges_rsp *ranges = + (struct ras_cmd_ras_safe_fb_address_ranges_rsp *)cmd->output_buff_raw; + struct amdgpu_mem_partition_info *mem_ranges; + uint32_t i = 0; + + if (cmd->input_size != sizeof(*input_data)) + return RAS_CMD__ERROR_INVALID_INPUT_DATA; + + mem_ranges = adev->gmc.mem_partitions; + for (i = 0; i < adev->gmc.num_mem_partitions; i++) { + ranges->range[i].start = mem_ranges[i].range.fpfn << AMDGPU_GPU_PAGE_SHIFT; + ranges->range[i].size = mem_ranges[i].size; + ranges->range[i].idx = i; + } + + ranges->num_ranges = adev->gmc.num_mem_partitions; + + ranges->version = 0; + cmd->output_size = sizeof(struct ras_cmd_ras_safe_fb_address_ranges_rsp); + + return RAS_CMD__SUCCESS; +} + +static int ras_translate_fb_address(struct ras_core_context *ras_core, + enum ras_fb_addr_type src_type, + enum ras_fb_addr_type dest_type, + union ras_translate_fb_address *src_addr, + union ras_translate_fb_address *dest_addr) +{ + uint64_t soc_phy_addr; + int ret = RAS_CMD__SUCCESS; + + /* Does not need to be queued as event as this is a SW translation */ + switch (src_type) { + case RAS_FB_ADDR_SOC_PHY: + soc_phy_addr = src_addr->soc_phy_addr; + break; + case RAS_FB_ADDR_BANK: + ret = ras_cmd_translate_bank_to_soc_pa(ras_core, + src_addr->bank_addr, &soc_phy_addr); + if (ret) + return RAS_CMD__ERROR_GENERIC; + break; + default: + return RAS_CMD__ERROR_INVALID_CMD; + } + + switch (dest_type) { + case RAS_FB_ADDR_SOC_PHY: + dest_addr->soc_phy_addr = soc_phy_addr; + break; + case RAS_FB_ADDR_BANK: + ret = ras_cmd_translate_soc_pa_to_bank(ras_core, + soc_phy_addr, &dest_addr->bank_addr); + if (ret) + return RAS_CMD__ERROR_GENERIC; + break; + default: + return RAS_CMD__ERROR_INVALID_CMD; + } + + return ret; +} + +static int amdgpu_ras_translate_fb_address(struct ras_core_context *ras_core, + struct ras_cmd_ioctl *cmd, void *data) +{ + struct ras_cmd_translate_fb_address_req *req_buff = + (struct ras_cmd_translate_fb_address_req *)cmd->input_buff_raw; + struct ras_cmd_translate_fb_address_rsp *rsp_buff = + (struct ras_cmd_translate_fb_address_rsp *)cmd->output_buff_raw; + int ret = RAS_CMD__ERROR_GENERIC; + + if (cmd->input_size != sizeof(struct ras_cmd_translate_fb_address_req)) + return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + + if ((req_buff->src_addr_type >= RAS_FB_ADDR_UNKNOWN) || + (req_buff->dest_addr_type >= RAS_FB_ADDR_UNKNOWN)) + return RAS_CMD__ERROR_INVALID_INPUT_DATA; + + ret = ras_translate_fb_address(ras_core, req_buff->src_addr_type, + req_buff->dest_addr_type, &req_buff->trans_addr, &rsp_buff->trans_addr); + if (ret) + return RAS_CMD__ERROR_GENERIC; + + rsp_buff->version = 0; + cmd->output_size = sizeof(struct ras_cmd_translate_fb_address_rsp); + + return RAS_CMD__SUCCESS; +} + +static struct ras_cmd_func_map amdgpu_ras_cmd_maps[] = { + {RAS_CMD__INJECT_ERROR, amdgpu_ras_inject_error}, + {RAS_CMD__GET_SAFE_FB_ADDRESS_RANGES, amdgpu_ras_get_ras_safe_fb_addr_ranges}, + {RAS_CMD__TRANSLATE_FB_ADDRESS, amdgpu_ras_translate_fb_address}, +}; + +int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ioctl *cmd, void *data) +{ + struct ras_cmd_func_map *ras_cmd = NULL; + int i, res; + + for (i = 0; i < ARRAY_SIZE(amdgpu_ras_cmd_maps); i++) { + if (cmd->cmd_id == amdgpu_ras_cmd_maps[i].cmd_id) { + ras_cmd = &amdgpu_ras_cmd_maps[i]; + break; + } + } + + if (ras_cmd) + res = ras_cmd->func(ras_core, cmd, NULL); + else + res = RAS_CMD__ERROR_UKNOWN_CMD; + + return res; +} + +int amdgpu_ras_cmd_ioctl_handler(struct ras_core_context *ras_core, + uint8_t *cmd_buf, uint32_t buf_size) +{ + struct ras_cmd_ioctl *cmd = (struct ras_cmd_ioctl *)cmd_buf; + struct ras_core_context *cmd_core = NULL; + struct ras_cmd_dev_handle *cmd_handle = NULL; + int timeout = 60; + int res; + + cmd->cmd_res = RAS_CMD__ERROR_INVALID_CMD; + cmd->output_size = 0; + + if (!ras_core_is_enabled(ras_core)) + return RAS_CMD__ERROR_ACCESS_DENIED; + + if (cmd->cmd_id == RAS_CMD__QUERY_INTERFACE_INFO) { + cmd->cmd_res = amdgpu_ras_query_interface_info(ras_core, cmd); + } else if (cmd->cmd_id == RAS_CMD__GET_DEVICES_INFO) { + cmd->cmd_res = amdgpu_ras_get_devices_info(ras_core, cmd); + } else { + cmd_handle = (struct ras_cmd_dev_handle *)cmd->input_buff_raw; + cmd_core = ras_cmd_get_ras_core(cmd_handle->dev_handle); + if (!cmd_core) + return RAS_CMD__ERROR_INVALID_INPUT_DATA; + + while (ras_core_gpu_in_reset(cmd_core)) { + msleep(1000); + if (!timeout--) + return RAS_CMD__ERROR_TIMEOUT; + } + + + if (!ras_core_is_enabled(cmd_core)) + return RAS_CMD__ERROR_ACCESS_DENIED; + + res = amdgpu_ras_handle_cmd(cmd_core, cmd, NULL); + if (res == RAS_CMD__ERROR_UKNOWN_CMD) + res = rascore_handle_cmd(cmd_core, cmd, NULL); + + cmd->cmd_res = res; + } + + if ((cmd->cmd_res == RAS_CMD__SUCCESS) && + ((cmd->output_size + sizeof(*cmd)) > buf_size)) { + RAS_INFO("Insufficient command buffer size 0x%x!\n", buf_size); + return RAS_CMD__SUCCESS_EXEED_BUFFER; + } + + return RAS_CMD__SUCCESS; +} diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h new file mode 100644 index 0000000000000..7017198f1bac2 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __AMDGPU_RAS_CMD_H__ +#define __AMDGPU_RAS_CMD_H__ +#include "ras.h" + +enum amdgpu_ras_cmd_id { + RAS_CMD__AMDGPU_BEGIN = RAS_CMD_ID_AMDGPU_START, + RAS_CMD__TRANSLATE_MEMORY_FD, + RAS_CMD__AMDGPU_SUPPORTED_MAX = RAS_CMD_ID_AMDGPU_END, +}; + +struct ras_cmd_translate_memory_fd_req { + struct ras_cmd_dev_handle dev; + uint32_t type; + uint32_t fd; + uint64_t address; + uint32_t reserved[4]; +}; + +struct ras_cmd_translate_memory_fd_rsp { + uint32_t version; + uint32_t padding; + uint64_t start; + uint64_t size; + uint32_t reserved[2]; +}; + +int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core, + struct ras_cmd_ioctl *cmd, void *data); +int amdgpu_ras_cmd_ioctl_handler(struct ras_core_context *ras_core, + uint8_t *cmd_buf, uint32_t buf_size); + +#endif From 19da884319d7f70e3fb3a571ee3d497dbf45a31d Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 24 Mar 2025 18:44:11 +0800 Subject: [PATCH 2112/2653] drm/amd/ras: Add amdgpu ras system functions Add amdgpu ras system functions. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c | 268 ++++++++++++++++++ drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h | 109 +++++++ 2 files changed, 377 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c create mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c new file mode 100644 index 0000000000000..40071b8763336 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "ras_sys.h" +#include "amdgpu_ras_mgr.h" +#include "amdgpu_ras.h" +#include "amdgpu_reset.h" + +static int amdgpu_ras_sys_detect_fatal_event(struct ras_core_context *ras_core, void *data) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + uint64_t seq_no; + + seq_no = amdgpu_ras_mgr_gen_ras_event_seqno(adev, RAS_SEQNO_TYPE_UE); + RAS_DEV_INFO(adev, + "{%llu} Uncorrectable hardware error(ERREVENT_ATHUB_INTERRUPT) detected!\n", + seq_no); + + return amdgpu_ras_process_handle_unexpected_interrupt(adev, data); +} + +static int amdgpu_ras_sys_poison_consumption_event(struct ras_core_context *ras_core, + void *data) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + struct ras_event_req *req = (struct ras_event_req *)data; + pasid_notify pasid_fn; + + if (!req) + return -EINVAL; + + if (req->pasid_fn) { + pasid_fn = (pasid_notify)req->pasid_fn; + pasid_fn(adev, req->pasid, req->data); + } + + return 0; +} + +static int amdgpu_ras_sys_gen_seqno(struct ras_core_context *ras_core, + enum ras_seqno_type seqno_type, uint64_t *seqno) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + struct ras_event_manager *event_mgr; + struct ras_event_state *event_state; + struct amdgpu_hive_info *hive; + enum ras_event_type event_type; + uint64_t seq_no; + + if (!ras_mgr || !seqno || + (seqno_type >= RAS_SEQNO_TYPE_COUNT_MAX)) + return -EINVAL; + + switch (seqno_type) { + case RAS_SEQNO_TYPE_UE: + event_type = RAS_EVENT_TYPE_FATAL; + break; + case RAS_SEQNO_TYPE_CE: + case RAS_SEQNO_TYPE_DE: + event_type = RAS_EVENT_TYPE_POISON_CREATION; + break; + case RAS_SEQNO_TYPE_POISON_CONSUMPTION: + event_type = RAS_EVENT_TYPE_POISON_CONSUMPTION; + break; + default: + event_type = RAS_EVENT_TYPE_INVALID; + break; + } + + hive = amdgpu_get_xgmi_hive(adev); + event_mgr = hive ? &hive->event_mgr : &ras_mgr->ras_event_mgr; + event_state = &event_mgr->event_state[event_type]; + if ((event_type == RAS_EVENT_TYPE_FATAL) && amdgpu_ras_in_recovery(adev)) { + seq_no = event_state->last_seqno; + } else { + seq_no = atomic64_inc_return(&event_mgr->seqno); + event_state->last_seqno = seq_no; + atomic64_inc(&event_state->count); + } + amdgpu_put_xgmi_hive(hive); + + *seqno = seq_no; + return 0; + +} + +static int amdgpu_ras_sys_event_notifier(struct ras_core_context *ras_core, + enum ras_notify_event event_id, void *data) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(ras_core->dev); + int ret = 0; + + switch (event_id) { + case RAS_EVENT_ID__BAD_PAGE_DETECTED: + schedule_delayed_work(&ras_mgr->retire_page_dwork, 0); + break; + case RAS_EVENT_ID__POISON_CONSUMPTION: + amdgpu_ras_sys_poison_consumption_event(ras_core, data); + break; + case RAS_EVENT_ID__RESERVE_BAD_PAGE: + ret = amdgpu_ras_reserve_page(ras_core->dev, *(uint64_t *)data); + break; + case RAS_EVENT_ID__FATAL_ERROR_DETECTED: + ret = amdgpu_ras_sys_detect_fatal_event(ras_core, data); + break; + case RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM: + ret = amdgpu_dpm_send_hbm_bad_pages_num(ras_core->dev, *(uint32_t *)data); + break; + case RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP: + ret = amdgpu_dpm_send_hbm_bad_channel_flag(ras_core->dev, *(uint32_t *)data); + break; + case RAS_EVENT_ID__DEVICE_RMA: + ras_log_ring_add_log_event(ras_core, RAS_LOG_EVENT_RMA, NULL, NULL); + ret = amdgpu_dpm_send_rma_reason(ras_core->dev); + break; + case RAS_EVENT_ID__RESET_GPU: + ret = amdgpu_ras_mgr_reset_gpu(ras_core->dev, *(uint32_t *)data); + break; + default: + RAS_DEV_WARN(ras_core->dev, "Invalid ras notify event:%d\n", event_id); + break; + } + + return ret; +} + +static u64 amdgpu_ras_sys_get_utc_second_timestamp(struct ras_core_context *ras_core) +{ + return ktime_get_real_seconds(); +} + +static int amdgpu_ras_sys_check_gpu_status(struct ras_core_context *ras_core, + uint32_t *status) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + uint32_t gpu_status = 0; + + if (amdgpu_in_reset(adev) || amdgpu_ras_in_recovery(adev)) + gpu_status |= RAS_GPU_STATUS__IN_RESET; + + if (amdgpu_sriov_vf(adev)) + gpu_status |= RAS_GPU_STATUS__IS_VF; + + *status = gpu_status; + + return 0; +} + +static int amdgpu_ras_sys_get_device_system_info(struct ras_core_context *ras_core, + struct device_system_info *dev_info) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + + dev_info->device_id = adev->pdev->device; + dev_info->vendor_id = adev->pdev->vendor; + dev_info->socket_id = adev->smuio.funcs->get_socket_id(adev); + + return 0; +} + +static int amdgpu_ras_sys_gpu_reset_lock(struct ras_core_context *ras_core, + bool down, bool try) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + int ret = 0; + + if (down && try) + ret = down_read_trylock(&adev->reset_domain->sem); + else if (down) + down_read(&adev->reset_domain->sem); + else + up_read(&adev->reset_domain->sem); + + return ret; +} + +static bool amdgpu_ras_sys_detect_ras_interrupt(struct ras_core_context *ras_core) +{ + return !!atomic_read(&amdgpu_ras_in_intr); +} + +static int amdgpu_ras_sys_get_gpu_mem(struct ras_core_context *ras_core, + enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + struct psp_context *psp = &adev->psp; + struct psp_ring *psp_ring; + struct ta_mem_context *mem_ctx; + + if (mem_type == GPU_MEM_TYPE_RAS_PSP_RING) { + psp_ring = &psp->km_ring; + gpu_mem->mem_bo = adev->firmware.rbuf; + gpu_mem->mem_size = psp_ring->ring_size; + gpu_mem->mem_mc_addr = psp_ring->ring_mem_mc_addr; + gpu_mem->mem_cpu_addr = psp_ring->ring_mem; + } else if (mem_type == GPU_MEM_TYPE_RAS_PSP_CMD) { + gpu_mem->mem_bo = psp->cmd_buf_bo; + gpu_mem->mem_size = PSP_CMD_BUFFER_SIZE; + gpu_mem->mem_mc_addr = psp->cmd_buf_mc_addr; + gpu_mem->mem_cpu_addr = psp->cmd_buf_mem; + } else if (mem_type == GPU_MEM_TYPE_RAS_PSP_FENCE) { + gpu_mem->mem_bo = psp->fence_buf_bo; + gpu_mem->mem_size = PSP_FENCE_BUFFER_SIZE; + gpu_mem->mem_mc_addr = psp->fence_buf_mc_addr; + gpu_mem->mem_cpu_addr = psp->fence_buf; + } else if (mem_type == GPU_MEM_TYPE_RAS_TA_FW) { + gpu_mem->mem_bo = psp->fw_pri_bo; + gpu_mem->mem_size = PSP_1_MEG; + gpu_mem->mem_mc_addr = psp->fw_pri_mc_addr; + gpu_mem->mem_cpu_addr = psp->fw_pri_buf; + } else if (mem_type == GPU_MEM_TYPE_RAS_TA_CMD) { + mem_ctx = &psp->ras_context.context.mem_context; + gpu_mem->mem_bo = mem_ctx->shared_bo; + gpu_mem->mem_size = mem_ctx->shared_mem_size; + gpu_mem->mem_mc_addr = mem_ctx->shared_mc_addr; + gpu_mem->mem_cpu_addr = mem_ctx->shared_buf; + } else { + return -EINVAL; + } + + if (!gpu_mem->mem_bo || !gpu_mem->mem_size || + !gpu_mem->mem_mc_addr || !gpu_mem->mem_cpu_addr) { + RAS_DEV_ERR(ras_core->dev, "The ras psp gpu memory is invalid!\n"); + return -ENOMEM; + } + + return 0; +} + +static int amdgpu_ras_sys_put_gpu_mem(struct ras_core_context *ras_core, + enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem) +{ + + return 0; +} + +const struct ras_sys_func amdgpu_ras_sys_fn = { + .ras_notifier = amdgpu_ras_sys_event_notifier, + .get_utc_second_timestamp = amdgpu_ras_sys_get_utc_second_timestamp, + .gen_seqno = amdgpu_ras_sys_gen_seqno, + .check_gpu_status = amdgpu_ras_sys_check_gpu_status, + .get_device_system_info = amdgpu_ras_sys_get_device_system_info, + .gpu_reset_lock = amdgpu_ras_sys_gpu_reset_lock, + .detect_ras_interrupt = amdgpu_ras_sys_detect_ras_interrupt, + .get_gpu_mem = amdgpu_ras_sys_get_gpu_mem, + .put_gpu_mem = amdgpu_ras_sys_put_gpu_mem, +}; diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h b/drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h new file mode 100644 index 0000000000000..c48ff26525d6e --- /dev/null +++ b/drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __RAS_SYS_H__ +#define __RAS_SYS_H__ +#include +#include +#include +#include "amdgpu.h" + +#define RAS_DEV_ERR(device, fmt, ...) \ + do { \ + if (device) \ + dev_err(((struct amdgpu_device *)device)->dev, fmt, ##__VA_ARGS__); \ + else \ + printk(KERN_ERR fmt, ##__VA_ARGS__); \ + } while (0) + +#define RAS_DEV_WARN(device, fmt, ...) \ + do { \ + if (device) \ + dev_warn(((struct amdgpu_device *)device)->dev, fmt, ##__VA_ARGS__); \ + else \ + printk(KERN_WARNING fmt, ##__VA_ARGS__); \ + } while (0) + +#define RAS_DEV_INFO(device, fmt, ...) \ + do { \ + if (device) \ + dev_info(((struct amdgpu_device *)device)->dev, fmt, ##__VA_ARGS__); \ + else \ + printk(KERN_INFO fmt, ##__VA_ARGS__); \ + } while (0) + +#define RAS_DEV_DBG(device, fmt, ...) \ + do { \ + if (device) \ + dev_dbg(((struct amdgpu_device *)device)->dev, fmt, ##__VA_ARGS__); \ + else \ + printk(KERN_DEBUG fmt, ##__VA_ARGS__); \ + } while (0) + +#define RAS_INFO(fmt, ...) printk(KERN_INFO fmt, ##__VA_ARGS__) + +#define RAS_DEV_RREG32_SOC15(dev, ip, inst, reg) \ +({ \ + struct amdgpu_device *adev = (struct amdgpu_device *)dev; \ + __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ + 0, ip##_HWIP, inst); \ +}) + +#define RAS_DEV_WREG32_SOC15(dev, ip, inst, reg, value) \ +({ \ + struct amdgpu_device *adev = (struct amdgpu_device *)dev; \ + __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \ + value, 0, ip##_HWIP, inst); \ +}) + +/* GET_INST returns the physical instance corresponding to a logical instance */ +#define RAS_GET_INST(dev, ip, inst) \ +({ \ + struct amdgpu_device *adev = (struct amdgpu_device *)dev; \ + adev->ip_map.logical_to_dev_inst ? \ + adev->ip_map.logical_to_dev_inst(adev, ip##_HWIP, inst) : inst; \ +}) + +#define RAS_GET_MASK(dev, ip, mask) \ +({ \ + struct amdgpu_device *adev = (struct amdgpu_device *)dev; \ + (adev->ip_map.logical_to_dev_mask ? \ + adev->ip_map.logical_to_dev_mask(adev, ip##_HWIP, mask) : mask); \ +}) + +static inline void *ras_radix_tree_delete_iter(struct radix_tree_root *root, void *iter) +{ + return radix_tree_delete(root, ((struct radix_tree_iter *)iter)->index); +} + +static inline long ras_wait_event_interruptible_timeout(void *wq_head, + int (*condition)(void *param), void *param, unsigned int timeout) +{ + return wait_event_interruptible_timeout(*(wait_queue_head_t *)wq_head, + condition(param), timeout); +} + +extern const struct ras_sys_func amdgpu_ras_sys_fn; + +#endif From 987b6d3ce06af97b4a9e180f78302a1208ba85ed Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 24 Mar 2025 18:46:06 +0800 Subject: [PATCH 2113/2653] drm/amd/ras: Amdgpu preprocesses ras interrupts Amdgpu preprocesses ras interrupts. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- .../drm/amd/ras/ras_mgr/amdgpu_ras_process.c | 126 ++++++++++++++++++ .../drm/amd/ras/ras_mgr/amdgpu_ras_process.h | 37 +++++ 2 files changed, 163 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c create mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.h diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c new file mode 100644 index 0000000000000..6727fc9a2b9b7 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "amdgpu.h" +#include "amdgpu_reset.h" +#include "amdgpu_xgmi.h" +#include "ras_sys.h" +#include "amdgpu_ras_mgr.h" +#include "amdgpu_ras_process.h" + +#define RAS_MGR_RETIRE_PAGE_INTERVAL 100 + +static void ras_process_retire_page_dwork(struct work_struct *work) +{ + struct amdgpu_ras_mgr *ras_mgr = + container_of(work, struct amdgpu_ras_mgr, retire_page_dwork.work); + struct amdgpu_device *adev = ras_mgr->adev; + int ret; + + if (amdgpu_ras_is_rma(adev)) + return; + + /* If gpu reset is ongoing, delay retiring the bad pages */ + if (amdgpu_in_reset(adev) || amdgpu_ras_in_recovery(adev)) { + schedule_delayed_work(&ras_mgr->retire_page_dwork, + msecs_to_jiffies(RAS_MGR_RETIRE_PAGE_INTERVAL * 3)); + return; + } + + ret = ras_umc_handle_bad_pages(ras_mgr->ras_core, NULL); + if (!ret) + schedule_delayed_work(&ras_mgr->retire_page_dwork, + msecs_to_jiffies(RAS_MGR_RETIRE_PAGE_INTERVAL)); +} + +int amdgpu_ras_process_init(struct amdgpu_device *adev) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + + INIT_DELAYED_WORK(&ras_mgr->retire_page_dwork, ras_process_retire_page_dwork); + + return 0; +} + +int amdgpu_ras_process_fini(struct amdgpu_device *adev) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + + /* Save all cached bad pages to eeprom */ + flush_delayed_work(&ras_mgr->retire_page_dwork); + cancel_delayed_work_sync(&ras_mgr->retire_page_dwork); + return 0; +} + +int amdgpu_ras_process_handle_umc_interrupt(struct amdgpu_device *adev, void *data) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + + if (!ras_mgr->ras_core) + return -EINVAL; + + return ras_process_add_interrupt_req(ras_mgr->ras_core, NULL, true); +} + +int amdgpu_ras_process_handle_unexpected_interrupt(struct amdgpu_device *adev, void *data) +{ + amdgpu_ras_set_fed(adev, true); + return amdgpu_ras_mgr_reset_gpu(adev, AMDGPU_RAS_GPU_RESET_MODE1_RESET); +} + +int amdgpu_ras_process_handle_consumption_interrupt(struct amdgpu_device *adev, void *data) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + struct ras_ih_info *ih_info = (struct ras_ih_info *)data; + struct ras_event_req req; + uint64_t seqno; + + if (!ih_info) + return -EINVAL; + + memset(&req, 0, sizeof(req)); + req.block = ih_info->block; + req.data = ih_info->data; + req.pasid = ih_info->pasid; + req.pasid_fn = ih_info->pasid_fn; + req.reset = ih_info->reset; + + seqno = ras_core_get_seqno(ras_mgr->ras_core, + RAS_SEQNO_TYPE_POISON_CONSUMPTION, false); + + /* When the ACA register cannot be read from FW, the poison + * consumption seqno in the fifo will not pop up, so it is + * necessary to check whether the seqno is the previous seqno. + */ + if (seqno == ras_mgr->last_poison_consumption_seqno) { + /* Pop and discard the previous seqno */ + ras_core_get_seqno(ras_mgr->ras_core, + RAS_SEQNO_TYPE_POISON_CONSUMPTION, true); + seqno = ras_core_get_seqno(ras_mgr->ras_core, + RAS_SEQNO_TYPE_POISON_CONSUMPTION, false); + } + ras_mgr->last_poison_consumption_seqno = seqno; + req.seqno = seqno; + + return ras_process_add_interrupt_req(ras_mgr->ras_core, &req, false); +} diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.h new file mode 100644 index 0000000000000..b9502bd21bebe --- /dev/null +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (c) 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef __AMDGPU_RAS_PROCESS_H__ +#define __AMDGPU_RAS_PROCESS_H__ +#include "ras_process.h" +#include "amdgpu_ras_mgr.h" + +enum ras_ih_type; +int amdgpu_ras_process_init(struct amdgpu_device *adev); +int amdgpu_ras_process_fini(struct amdgpu_device *adev); +int amdgpu_ras_process_handle_umc_interrupt(struct amdgpu_device *adev, + void *data); +int amdgpu_ras_process_handle_unexpected_interrupt(struct amdgpu_device *adev, + void *data); +int amdgpu_ras_process_handle_consumption_interrupt(struct amdgpu_device *adev, + void *data); +#endif From b5bae0f01786d426e1497db6f77d0ade82bbedc1 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 18:03:28 +0800 Subject: [PATCH 2114/2653] drm/amd/ras: Add amdgpu ras management function. Add amdgpu system configuration parameters and functions needed by rascore. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 560 ++++++++++++++++++ .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h | 73 +++ 2 files changed, 633 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c create mode 100644 drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c new file mode 100644 index 0000000000000..a038c87c045d8 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -0,0 +1,560 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "amdgpu_reset.h" +#include "amdgpu_xgmi.h" +#include "ras_sys.h" +#include "amdgpu_ras_mgr.h" +#include "amdgpu_ras_cmd.h" +#include "amdgpu_ras_process.h" +#include "amdgpu_ras_eeprom_i2c.h" +#include "amdgpu_ras_mp1_v13_0.h" +#include "amdgpu_ras_nbio_v7_9.h" + +#define MAX_SOCKET_NUM_PER_HIVE 8 +#define MAX_AID_NUM_PER_SOCKET 4 +#define MAX_XCD_NUM_PER_AID 2 + +/* typical ECC bad page rate is 1 bad page per 100MB VRAM */ +#define ESTIMATE_BAD_PAGE_THRESHOLD(size) ((size)/(100 * 1024 * 1024ULL)) + +#define COUNT_BAD_PAGE_THRESHOLD(size) (((size) >> 21) << 4) + +/* Reserve 8 physical dram row for possible retirement. + * In worst cases, it will lose 8 * 2MB memory in vram domain + */ +#define RAS_RESERVED_VRAM_SIZE_DEFAULT (16ULL << 20) + + +static void ras_mgr_init_event_mgr(struct ras_event_manager *mgr) +{ + struct ras_event_state *event_state; + int i; + + memset(mgr, 0, sizeof(*mgr)); + atomic64_set(&mgr->seqno, 0); + + for (i = 0; i < ARRAY_SIZE(mgr->event_state); i++) { + event_state = &mgr->event_state[i]; + event_state->last_seqno = RAS_EVENT_INVALID_ID; + atomic64_set(&event_state->count, 0); + } +} + +static void amdgpu_ras_mgr_init_event_mgr(struct ras_core_context *ras_core) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + struct ras_event_manager *event_mgr; + struct amdgpu_hive_info *hive; + + hive = amdgpu_get_xgmi_hive(adev); + event_mgr = hive ? &hive->event_mgr : &ras_mgr->ras_event_mgr; + + /* init event manager with node 0 on xgmi system */ + if (!amdgpu_reset_in_recovery(adev)) { + if (!hive || adev->gmc.xgmi.node_id == 0) + ras_mgr_init_event_mgr(event_mgr); + } + + if (hive) + amdgpu_put_xgmi_hive(hive); +} + +static int amdgpu_ras_mgr_init_aca_config(struct amdgpu_device *adev, + struct ras_core_config *config) +{ + struct ras_aca_config *aca_cfg = &config->aca_cfg; + + aca_cfg->socket_num_per_hive = MAX_SOCKET_NUM_PER_HIVE; + aca_cfg->aid_num_per_socket = MAX_AID_NUM_PER_SOCKET; + aca_cfg->xcd_num_per_aid = MAX_XCD_NUM_PER_AID; + + return 0; +} + +static int amdgpu_ras_mgr_init_eeprom_config(struct amdgpu_device *adev, + struct ras_core_config *config) +{ + struct ras_eeprom_config *eeprom_cfg = &config->eeprom_cfg; + + eeprom_cfg->eeprom_sys_fn = &amdgpu_ras_eeprom_i2c_sys_func; + eeprom_cfg->eeprom_i2c_adapter = adev->pm.ras_eeprom_i2c_bus; + if (eeprom_cfg->eeprom_i2c_adapter) { + const struct i2c_adapter_quirks *quirks = + ((struct i2c_adapter *)eeprom_cfg->eeprom_i2c_adapter)->quirks; + + if (quirks) { + eeprom_cfg->max_i2c_read_len = quirks->max_read_len; + eeprom_cfg->max_i2c_write_len = quirks->max_write_len; + } + } + + /* + * amdgpu_bad_page_threshold is used to config + * the threshold for the number of bad pages. + * -1: Threshold is set to default value + * Driver will issue a warning message when threshold is reached + * and continue runtime services. + * 0: Disable bad page retirement + * Driver will not retire bad pages + * which is intended for debugging purpose. + * -2: Threshold is determined by a formula + * that assumes 1 bad page per 100M of local memory. + * Driver will continue runtime services when threhold is reached. + * 0 < threshold < max number of bad page records in EEPROM, + * A user-defined threshold is set + * Driver will halt runtime services when this custom threshold is reached. + */ + if (amdgpu_bad_page_threshold == NONSTOP_OVER_THRESHOLD) + eeprom_cfg->eeprom_record_threshold_count = + ESTIMATE_BAD_PAGE_THRESHOLD(adev->gmc.mc_vram_size); + else if (amdgpu_bad_page_threshold == WARN_NONSTOP_OVER_THRESHOLD) + eeprom_cfg->eeprom_record_threshold_count = + COUNT_BAD_PAGE_THRESHOLD(RAS_RESERVED_VRAM_SIZE_DEFAULT); + else + eeprom_cfg->eeprom_record_threshold_count = amdgpu_bad_page_threshold; + + eeprom_cfg->eeprom_record_threshold_config = amdgpu_bad_page_threshold; + + return 0; +} + +static int amdgpu_ras_mgr_init_mp1_config(struct amdgpu_device *adev, + struct ras_core_config *config) +{ + struct ras_mp1_config *mp1_cfg = &config->mp1_cfg; + int ret = 0; + + switch (config->mp1_ip_version) { + case IP_VERSION(13, 0, 6): + case IP_VERSION(13, 0, 14): + case IP_VERSION(13, 0, 12): + mp1_cfg->mp1_sys_fn = &amdgpu_ras_mp1_sys_func_v13_0; + break; + default: + RAS_DEV_ERR(adev, + "The mp1(0x%x) ras config is not right!\n", + config->mp1_ip_version); + ret = -EINVAL; + break; + } + + return ret; +} + +static int amdgpu_ras_mgr_init_nbio_config(struct amdgpu_device *adev, + struct ras_core_config *config) +{ + struct ras_nbio_config *nbio_cfg = &config->nbio_cfg; + int ret = 0; + + switch (config->nbio_ip_version) { + case IP_VERSION(7, 9, 0): + nbio_cfg->nbio_sys_fn = &amdgpu_ras_nbio_sys_func_v7_9; + break; + default: + RAS_DEV_ERR(adev, + "The nbio(0x%x) ras config is not right!\n", + config->mp1_ip_version); + ret = -EINVAL; + break; + } + + return ret; +} + +static int amdgpu_ras_mgr_get_ras_psp_system_status(struct ras_core_context *ras_core, + struct ras_psp_sys_status *status) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + struct ta_context *context = &adev->psp.ras_context.context; + + status->initialized = context->initialized; + status->session_id = context->session_id; + status->psp_cmd_mutex = &adev->psp.mutex; + + return 0; +} + +static int amdgpu_ras_mgr_get_ras_ta_init_param(struct ras_core_context *ras_core, + struct ras_ta_init_param *ras_ta_param) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + uint32_t nps_mode; + + if (amdgpu_ras_is_poison_mode_supported(adev)) + ras_ta_param->poison_mode_en = 1; + + if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) + ras_ta_param->dgpu_mode = 1; + + ras_ta_param->xcc_mask = adev->gfx.xcc_mask; + ras_ta_param->channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; + + ras_ta_param->active_umc_mask = adev->umc.active_mask; + + if (!amdgpu_ras_mgr_get_curr_nps_mode(adev, &nps_mode)) + ras_ta_param->nps_mode = nps_mode; + + return 0; +} + +const struct ras_psp_sys_func amdgpu_ras_psp_sys_func = { + .get_ras_psp_system_status = amdgpu_ras_mgr_get_ras_psp_system_status, + .get_ras_ta_init_param = amdgpu_ras_mgr_get_ras_ta_init_param, +}; + +static int amdgpu_ras_mgr_init_psp_config(struct amdgpu_device *adev, + struct ras_core_config *config) +{ + struct ras_psp_config *psp_cfg = &config->psp_cfg; + + psp_cfg->psp_sys_fn = &amdgpu_ras_psp_sys_func; + + return 0; +} + +static int amdgpu_ras_mgr_init_umc_config(struct amdgpu_device *adev, + struct ras_core_config *config) +{ + struct ras_umc_config *umc_cfg = &config->umc_cfg; + + umc_cfg->umc_vram_type = adev->gmc.vram_type; + + return 0; +} + +static struct ras_core_context *amdgpu_ras_mgr_create_ras_core(struct amdgpu_device *adev) +{ + struct ras_core_config init_config; + + memset(&init_config, 0, sizeof(init_config)); + + init_config.umc_ip_version = amdgpu_ip_version(adev, UMC_HWIP, 0); + init_config.mp1_ip_version = amdgpu_ip_version(adev, MP1_HWIP, 0); + init_config.gfx_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); + init_config.nbio_ip_version = amdgpu_ip_version(adev, NBIO_HWIP, 0); + init_config.psp_ip_version = amdgpu_ip_version(adev, MP1_HWIP, 0); + + if (init_config.umc_ip_version == IP_VERSION(12, 0, 0)) + init_config.aca_ip_version = IP_VERSION(1, 0, 0); + + init_config.sys_fn = &amdgpu_ras_sys_fn; + init_config.ras_eeprom_supported = true; + init_config.poison_supported = + amdgpu_ras_is_poison_mode_supported(adev); + + amdgpu_ras_mgr_init_aca_config(adev, &init_config); + amdgpu_ras_mgr_init_eeprom_config(adev, &init_config); + amdgpu_ras_mgr_init_mp1_config(adev, &init_config); + amdgpu_ras_mgr_init_nbio_config(adev, &init_config); + amdgpu_ras_mgr_init_psp_config(adev, &init_config); + amdgpu_ras_mgr_init_umc_config(adev, &init_config); + + return ras_core_create(&init_config); +} + +static int amdgpu_ras_mgr_sw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + struct amdgpu_ras_mgr *ras_mgr; + int ret = 0; + + ras_mgr = kzalloc(sizeof(*ras_mgr), GFP_KERNEL); + if (!ras_mgr) + return -EINVAL; + + con->ras_mgr = ras_mgr; + ras_mgr->adev = adev; + + ras_mgr->ras_core = amdgpu_ras_mgr_create_ras_core(adev); + if (!ras_mgr->ras_core) { + RAS_DEV_ERR(adev, "Failed to create ras core!\n"); + ret = -EINVAL; + goto err; + } + + ras_mgr->ras_core->dev = adev; + + amdgpu_ras_process_init(adev); + ras_core_sw_init(ras_mgr->ras_core); + amdgpu_ras_mgr_init_event_mgr(ras_mgr->ras_core); + return 0; + +err: + kfree(ras_mgr); + return ret; +} + +static int amdgpu_ras_mgr_sw_fini(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + struct amdgpu_ras_mgr *ras_mgr = (struct amdgpu_ras_mgr *)con->ras_mgr; + + if (!ras_mgr) + return 0; + + amdgpu_ras_process_fini(adev); + ras_core_sw_fini(ras_mgr->ras_core); + ras_core_destroy(ras_mgr->ras_core); + ras_mgr->ras_core = NULL; + + kfree(con->ras_mgr); + con->ras_mgr = NULL; + + return 0; +} + +static int amdgpu_ras_mgr_hw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + int ret; + + if (!ras_mgr || !ras_mgr->ras_core) + return -EINVAL; + + ret = ras_core_hw_init(ras_mgr->ras_core); + if (ret) { + RAS_DEV_ERR(adev, "Failed to initialize ras core!\n"); + return ret; + } + + ras_mgr->ras_is_ready = true; + + RAS_DEV_INFO(adev, "AMDGPU RAS Is Ready.\n"); + return 0; +} + +static int amdgpu_ras_mgr_hw_fini(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + + if (!ras_mgr || !ras_mgr->ras_core) + return -EINVAL; + + ras_core_hw_fini(ras_mgr->ras_core); + + ras_mgr->ras_is_ready = false; + + return 0; +} + +struct amdgpu_ras_mgr *amdgpu_ras_mgr_get_context(struct amdgpu_device *adev) +{ + if (!adev || !adev->psp.ras_context.ras) + return NULL; + + return (struct amdgpu_ras_mgr *)adev->psp.ras_context.ras->ras_mgr; +} + +static const struct amd_ip_funcs ras_v1_0_ip_funcs = { + .name = "ras_v1_0", + .sw_init = amdgpu_ras_mgr_sw_init, + .sw_fini = amdgpu_ras_mgr_sw_fini, + .hw_init = amdgpu_ras_mgr_hw_init, + .hw_fini = amdgpu_ras_mgr_hw_fini, +}; + +int amdgpu_enable_unified_ras(struct amdgpu_device *adev, bool enable) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + + if (!ras_mgr || !ras_mgr->ras_core) + return -EPERM; + + if (amdgpu_sriov_vf(adev)) + return -EPERM; + + RAS_DEV_INFO(adev, "Enable amdgpu unified ras!"); + return ras_core_set_status(ras_mgr->ras_core, enable); +} + +bool amdgpu_unified_ras_enabled(struct amdgpu_device *adev) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + + if (!ras_mgr || !ras_mgr->ras_core) + return false; + + if (amdgpu_sriov_vf(adev)) + return false; + + return ras_core_is_enabled(ras_mgr->ras_core); +} + +static bool amdgpu_ras_mgr_is_ready(struct amdgpu_device *adev) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + + if (ras_mgr && ras_mgr->ras_core && ras_mgr->ras_is_ready && + ras_core_is_ready(ras_mgr->ras_core)) + return true; + + return false; +} + +int amdgpu_ras_mgr_handle_fatal_interrupt(struct amdgpu_device *adev, void *data) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + + if (!amdgpu_ras_mgr_is_ready(adev)) + return -EPERM; + + return ras_core_handle_nbio_irq(ras_mgr->ras_core, data); +} + +uint64_t amdgpu_ras_mgr_gen_ras_event_seqno(struct amdgpu_device *adev, + enum ras_seqno_type seqno_type) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + int ret; + uint64_t seq_no; + + if (!amdgpu_ras_mgr_is_ready(adev) || + (seqno_type >= RAS_SEQNO_TYPE_COUNT_MAX)) + return 0; + + seq_no = ras_core_gen_seqno(ras_mgr->ras_core, seqno_type); + + if ((seqno_type == RAS_SEQNO_TYPE_DE) || + (seqno_type == RAS_SEQNO_TYPE_POISON_CONSUMPTION)) { + ret = ras_core_put_seqno(ras_mgr->ras_core, seqno_type, seq_no); + if (ret) + RAS_DEV_WARN(adev, "There are too many ras interrupts!"); + } + + return seq_no; +} + +int amdgpu_ras_mgr_handle_controller_interrupt(struct amdgpu_device *adev, void *data) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + struct ras_ih_info *ih_info = (struct ras_ih_info *)data; + uint64_t seq_no = 0; + int ret = 0; + + if (!amdgpu_ras_mgr_is_ready(adev)) + return -EPERM; + + if (ih_info && (ih_info->block == AMDGPU_RAS_BLOCK__UMC)) { + if (ras_mgr->ras_core->poison_supported) { + seq_no = amdgpu_ras_mgr_gen_ras_event_seqno(adev, RAS_SEQNO_TYPE_DE); + RAS_DEV_INFO(adev, + "{%llu} RAS poison is created, no user action is needed.\n", + seq_no); + } + + ret = amdgpu_ras_process_handle_umc_interrupt(adev, ih_info); + } else if (ras_mgr->ras_core->poison_supported) { + ret = amdgpu_ras_process_handle_unexpected_interrupt(adev, ih_info); + } else { + RAS_DEV_WARN(adev, + "No RAS interrupt handler for non-UMC block with poison disabled.\n"); + } + + return ret; +} + +int amdgpu_ras_mgr_handle_consumer_interrupt(struct amdgpu_device *adev, void *data) +{ + if (!amdgpu_ras_mgr_is_ready(adev)) + return -EPERM; + + return amdgpu_ras_process_handle_consumption_interrupt(adev, data); +} + +int amdgpu_ras_mgr_update_ras_ecc(struct amdgpu_device *adev) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + + if (!amdgpu_ras_mgr_is_ready(adev)) + return -EPERM; + + return ras_core_update_ecc_info(ras_mgr->ras_core); +} + +int amdgpu_ras_mgr_reset_gpu(struct amdgpu_device *adev, uint32_t flags) +{ + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + + if (!amdgpu_ras_mgr_is_ready(adev)) + return -EPERM; + + con->gpu_reset_flags |= flags; + return amdgpu_ras_reset_gpu(adev); +} + +bool amdgpu_ras_mgr_check_eeprom_safety_watermark(struct amdgpu_device *adev) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + + if (!amdgpu_ras_mgr_is_ready(adev)) + return false; + + return ras_eeprom_check_safety_watermark(ras_mgr->ras_core); +} + +int amdgpu_ras_mgr_get_curr_nps_mode(struct amdgpu_device *adev, + uint32_t *nps_mode) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + uint32_t mode; + + if (!amdgpu_ras_mgr_is_ready(adev)) + return -EINVAL; + + mode = ras_core_get_curr_nps_mode(ras_mgr->ras_core); + if (!mode || mode > AMDGPU_NPS8_PARTITION_MODE) + return -EINVAL; + + *nps_mode = mode; + + return 0; +} + +bool amdgpu_ras_mgr_check_retired_addr(struct amdgpu_device *adev, + uint64_t addr) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + + if (!amdgpu_ras_mgr_is_ready(adev)) + return false; + + return ras_umc_check_retired_addr(ras_mgr->ras_core, addr); +} + +bool amdgpu_ras_mgr_is_rma(struct amdgpu_device *adev) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + + if (!ras_mgr || !ras_mgr->ras_core || !ras_mgr->ras_is_ready) + return false; + + return ras_core_gpu_is_rma(ras_mgr->ras_core); +} diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h new file mode 100644 index 0000000000000..fa761de381c19 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (c) 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef __AMDGPU_RAS_MGR_H__ +#define __AMDGPU_RAS_MGR_H__ +#include "ras.h" +#include "amdgpu_ras_process.h" + +enum ras_ih_type { + RAS_IH_NONE, + RAS_IH_FROM_BLOCK_CONTROLLER, + RAS_IH_FROM_CONSUMER_CLIENT, + RAS_IH_FROM_FATAL_ERROR, +}; + +struct ras_ih_info { + uint32_t block; + union { + struct amdgpu_iv_entry iv_entry; + struct { + uint16_t pasid; + uint32_t reset; + pasid_notify pasid_fn; + void *data; + }; + }; +}; + +struct amdgpu_ras_mgr { + struct amdgpu_device *adev; + struct ras_core_context *ras_core; + struct delayed_work retire_page_dwork; + struct ras_event_manager ras_event_mgr; + uint64_t last_poison_consumption_seqno; + bool ras_is_ready; +}; + +struct amdgpu_ras_mgr *amdgpu_ras_mgr_get_context( + struct amdgpu_device *adev); +int amdgpu_enable_unified_ras(struct amdgpu_device *adev, bool enable); +bool amdgpu_unified_ras_enabled(struct amdgpu_device *adev); +int amdgpu_ras_mgr_handle_fatal_interrupt(struct amdgpu_device *adev, void *data); +int amdgpu_ras_mgr_handle_controller_interrupt(struct amdgpu_device *adev, void *data); +int amdgpu_ras_mgr_handle_consumer_interrupt(struct amdgpu_device *adev, void *data); +int amdgpu_ras_mgr_update_ras_ecc(struct amdgpu_device *adev); +int amdgpu_ras_mgr_reset_gpu(struct amdgpu_device *adev, uint32_t flags); +uint64_t amdgpu_ras_mgr_gen_ras_event_seqno(struct amdgpu_device *adev, + enum ras_seqno_type seqno_type); +bool amdgpu_ras_mgr_check_eeprom_safety_watermark(struct amdgpu_device *adev); +int amdgpu_ras_mgr_get_curr_nps_mode(struct amdgpu_device *adev, uint32_t *nps_mode); +bool amdgpu_ras_mgr_check_retired_addr(struct amdgpu_device *adev, + uint64_t addr); +bool amdgpu_ras_mgr_is_rma(struct amdgpu_device *adev); +#endif From 866cbb0c374ec6b9b06108b05341ae3b64c1ae0c Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 17 Mar 2025 18:04:10 +0800 Subject: [PATCH 2115/2653] drm/amd/ras: Add files to amdgpu ras manager makefile Add files to amdgpu ras manager makefile. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/ras/ras_mgr/Makefile | 33 ++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/Makefile b/drivers/gpu/drm/amd/ras/ras_mgr/Makefile index e69de29bb2d1d..5e5a2cfa40688 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/Makefile +++ b/drivers/gpu/drm/amd/ras/ras_mgr/Makefile @@ -0,0 +1,33 @@ +# Copyright 2025 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. + +RAS_MGR_FILES = amdgpu_ras_sys.o \ + amdgpu_ras_mgr.o \ + amdgpu_ras_eeprom_i2c.o \ + amdgpu_ras_mp1_v13_0.o \ + amdgpu_ras_cmd.o \ + amdgpu_ras_process.o \ + amdgpu_ras_nbio_v7_9.o + + +RAS_MGR = $(addprefix $(AMD_GPU_RAS_PATH)/ras_mgr/, $(RAS_MGR_FILES)) + +AMD_GPU_RAS_FILES += $(RAS_MGR) + From 97ce636398a23d3557b90db9153411a6ebd8251d Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 24 Mar 2025 15:13:20 +0800 Subject: [PATCH 2116/2653] drm/amd/ras: Add unified ras module top-level makefile Add unified ras module top-level makefile. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/ras/Makefile | 34 ++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/ras/Makefile diff --git a/drivers/gpu/drm/amd/ras/Makefile b/drivers/gpu/drm/amd/ras/Makefile new file mode 100644 index 0000000000000..bbdaba811d342 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/Makefile @@ -0,0 +1,34 @@ +# +# Copyright (c) 2025 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +ifeq ($(AMD_GPU_RAS_MGR),) + AMD_GPU_RAS_MGR := ras_mgr +endif + +subdir-ccflags-y += -I$(AMD_GPU_RAS_FULL_PATH)/rascore +subdir-ccflags-y += -I$(AMD_GPU_RAS_FULL_PATH)/$(AMD_GPU_RAS_MGR) + +RAS_LIBS = $(AMD_GPU_RAS_MGR) rascore + +AMD_RAS = $(addsuffix /Makefile, $(addprefix $(AMD_GPU_RAS_FULL_PATH)/,$(RAS_LIBS))) + +include $(AMD_RAS) + From 3ce02346f61c7938022f812612492c144a75548c Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Wed, 24 Sep 2025 11:16:20 -0500 Subject: [PATCH 2117/2653] drm/amd/display: Only enable common modes for eDP and LVDS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [Why] The main reason common modes are added is for compatibility with clone mode when a laptop is connected to a projector or external monitor. Since commit 978fa2f6d0b12 ("drm/amd/display: Use scaling for non-native resolutions on eDP") when non-native modes are picked for eDP the GPU scalar will be used. This is because it is inconsistent whether eDP panels have the capability to actually drive non-native resolutions. With panels connected to other connectors this limitation generally doesn't exist as we the EDID will advertise support for a number of resolutions and monitors will use built in scaling hardware. Comparing DC and non-DC code paths the non-DC code path only adds common modes for LVDS and eDP whereas the DC codepath does it for all connector types. In the past there was an experiment done to disable common mode adding for eDP and LVDS from commit 6d396e7ac1ce3 ("drm/amd/display: Disable common modes for LVDS") and commit 7948afb46af92 ("drm/amd/display: Disable common modes for eDP") but this was reverted in commit a8b79b09185de ("drm/amd: Re-enable common modes for eDP and LVDS") because it caused problems with Xorg. [How] Only add common modes for eDP and LVDS for DC, matching the behavior of non-DC. Suggested-by: Timur Kristóf Reviewed-by: Harry Wentland Reviewed-by: Timur Kristóf Reviewed-by: Alex Deucher Link: https://lore.kernel.org/r/20250924161624.1975819-2-mario.limonciello@amd.com Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9ae0025d78029..76289a68809b2 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8495,6 +8495,10 @@ static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, {"1920x1200", 1920, 1200} }; + if ((connector->connector_type != DRM_MODE_CONNECTOR_eDP) && + (connector->connector_type != DRM_MODE_CONNECTOR_LVDS)) + return; + n = ARRAY_SIZE(common_modes); for (i = 0; i < n; i++) { From bbe3eb358e631f871e58f252986cc1aa4f6662f9 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Wed, 24 Sep 2025 11:16:21 -0500 Subject: [PATCH 2118/2653] drm/amd: Drop unnecessary check in amdgpu_connector_add_common_modes() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [Why] amdgpu_connector_add_common_modes() has a check for the width and height of common modes being too small, but the array of common_modes[] has fixed values. The check is dead code. [How] Drop unnecessary check. Cc: Timur Kristóf Reviewed-by: Timur Kristóf Reviewed-by: Alex Deucher Link: https://lore.kernel.org/r/20250924161624.1975819-3-mario.limonciello@amd.com Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index b636bc98a8177..051025d6e3c67 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -475,8 +475,6 @@ static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, common_modes[i].h == native_mode->vdisplay)) continue; } - if (common_modes[i].w < 320 || common_modes[i].h < 200) - continue; mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); if (!mode) From 8030c28d454887c9518762349dd674eb741007aa Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 3 Sep 2025 15:51:24 +0800 Subject: [PATCH 2119/2653] drm/amdkcl: fix NULL pointer dereference during module unload The free_xcp_dev() function incorrectly uses the global pdev_num variable to index into the xcp_dev array. Since pdev_num is decremented during the loop, it can lead to accessing an incorrect index during concurrent unloads or error conditions, resulting in a NULL pointer dereference. Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c index 90ba91f6c9620..c7b3de2def021 100644 --- a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c +++ b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c @@ -112,8 +112,8 @@ static void free_xcp_dev(int8_t index) devres_release_group(&pdev->dev, NULL); platform_device_unregister(pdev); #ifndef HAVE_DRM_DRM_MANAGED_H - drm_dev_fini(&(xcp_dev[pdev_num]->drm)); - kfree(xcp_dev[pdev_num]); + drm_dev_fini(&(xcp_dev[index]->drm)); + kfree(xcp_dev[index]); #endif xcp_dev[index] = NULL; pdev_num--; From b1dd6cf79fb8d622b65db1b121fd7f87c5d6c29c Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 18 Sep 2025 17:38:17 +0800 Subject: [PATCH 2120/2653] drm/amdkcl: fix check struct block_device has member named 'bd_device' Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/blk_types.m4 | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/blk_types.m4 b/drivers/gpu/drm/amd/dkms/m4/blk_types.m4 index 6c92962c97e00..d6d3e21a7efea 100644 --- a/drivers/gpu/drm/amd/dkms/m4/blk_types.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/blk_types.m4 @@ -4,12 +4,14 @@ dnl # block: merge struct block_device and struct hd_struct dnl # AC_DEFUN([AC_AMDGPU_BLOCK_DEVICE_BD_DEVICE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct block_device *device = NULL; + struct device dev = {}; + device->bd_device = dev; ], [ - struct block_device *device; - device.bd_device = NULL; - ], [],[],[ AC_DEFINE(HAVE_BLOCK_DEVICE_BD_DEVICE, 1, [struct block_device has member named 'bd_device']) ]) From 73b22985335a3e1efff5852e32f1c455674ddf1e Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 16 Sep 2025 14:47:27 +0800 Subject: [PATCH 2121/2653] drm/amdkcl: remove unnecessary vm_insert_mixed & vmf_insert_mixed_prot() check Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_memory.c | 14 ------ drivers/gpu/drm/amd/dkms/config/config.h | 6 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 | 14 ------ .../drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 | 20 --------- include/kcl/kcl_memory.h | 45 ------------------- 6 files changed, 100 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c index 606ae29de54ae..b835dd0f0e28b 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c @@ -31,20 +31,6 @@ #include #include -/* Copied from drivers/gpu/drm/ttm/ttm_bo_vm.c and modified for KCL */ -#ifndef HAVE_VMF_INSERT_MIXED_PROT -vm_fault_t _kcl_vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, - pfn_t pfn, pgprot_t pgprot) -{ - struct vm_area_struct cvma = *vma; - - cvma.vm_page_prot = pgprot; - - return vmf_insert_mixed(&cvma, addr, pfn); -} -EXPORT_SYMBOL(_kcl_vmf_insert_mixed_prot); -#endif - #ifndef HAVE_VMF_INSERT_PFN_PROT #ifndef HAVE_VM_INSERT_PFN_PROT int vm_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 61f38b2c6fbff..a21f06412b7d1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1087,9 +1087,6 @@ /* pfn_t is defined */ #define HAVE_PFN_T 1 -/* vm_insert_mixed() wants pfn_t arg */ -/* #undef HAVE_PFN_T_VM_INSERT_MIXED */ - /* PIDTYPE is availablea */ #define HAVE_PIDTYPE_TGID 1 @@ -1274,9 +1271,6 @@ /* vmf_insert_*() are available */ #define HAVE_VMF_INSERT 1 -/* vmf_insert_mixed_prot() is available */ -/* #undef HAVE_VMF_INSERT_MIXED_PROT */ - /* vmf_insert_pfn_prot() is available */ #define HAVE_VMF_INSERT_PFN_PROT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6f32089a5b0e9..636f23799f9b6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -36,7 +36,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_FSLEEP AC_AMDGPU_USLEEP_RANGE_STATE AC_AMDGPU_VMF_INSERT - AC_AMDGPU_VMF_INSERT_MIXED_PROT AC_AMDGPU_VMF_INSERT_PFN_PROT AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT AC_AMDGPU_MMU_NOTIFIER diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 index 89789fd059839..eb41c2919fae8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 @@ -25,20 +25,6 @@ AC_DEFUN([AC_AMDGPU_VMF_INSERT], [ ], [ AC_DEFINE(HAVE_VMF_INSERT, 1, [vmf_insert_*() are available]) - ], [ - dnl # - dnl # commit v4.4-6475-g01c8f1c44b83 - dnl # mm, dax, gpu: convert vm_insert_mixed to pfn_t - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - pfn_t pfn = {}; - vm_insert_mixed(NULL, 0, pfn); - ], [vm_insert_mixed], [mm/memory.c], [ - AC_DEFINE(HAVE_PFN_T_VM_INSERT_MIXED, 1, - [vm_insert_mixed() wants pfn_t arg]) - ]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 deleted file mode 100644 index 53da9747196ea..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 +++ /dev/null @@ -1,20 +0,0 @@ -dnl # -dnl # 5379e4dd3220 mm, drm/ttm: Fix vm page protection handling -dnl # 574c5b3d0e4c mm: Add a vmf_insert_mixed_prot() function -dnl # -AC_DEFUN([AC_AMDGPU_VMF_INSERT_MIXED_PROT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - #include - ],[ - pfn_t pfn; - pgprot_t prot; - vmf_insert_mixed_prot(NULL, 0, pfn, prot); - ],[vmf_insert_mixed_prot],[mm/memory.c],[ - AC_DEFINE(HAVE_VMF_INSERT_MIXED_PROT, - 1, - [vmf_insert_mixed_prot() is available]) - ]) - ]) -]) diff --git a/include/kcl/kcl_memory.h b/include/kcl/kcl_memory.h index aeebb157b0d57..571c570dd2c42 100644 --- a/include/kcl/kcl_memory.h +++ b/include/kcl/kcl_memory.h @@ -2,51 +2,6 @@ #ifndef _KCL_KCL_MEMORY_H #define _KCL_KCL_MEMORY_H -#ifndef HAVE_VMF_INSERT -static inline vm_fault_t vmf_insert_mixed(struct vm_area_struct *vma, - unsigned long addr, - pfn_t pfn) -{ - int err; -#if !defined(HAVE_PFN_T_VM_INSERT_MIXED) - err = vm_insert_mixed(vma, addr, pfn_t_to_pfn(pfn)); -#else - err = vm_insert_mixed(vma, addr, pfn); -#endif - if (err == -ENOMEM) - return VM_FAULT_OOM; - if (err < 0 && err != -EBUSY) - return VM_FAULT_SIGBUS; - - return VM_FAULT_NOPAGE; -} - -static inline vm_fault_t vmf_insert_pfn(struct vm_area_struct *vma, - unsigned long addr, unsigned long pfn) -{ - int err = vm_insert_pfn(vma, addr, pfn); - - if (err == -ENOMEM) - return VM_FAULT_OOM; - if (err < 0 && err != -EBUSY) - return VM_FAULT_SIGBUS; - - return VM_FAULT_NOPAGE; -} - -#endif /* HAVE_VMF_INSERT */ - -#ifndef HAVE_VMF_INSERT_MIXED_PROT -vm_fault_t _kcl_vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, - pfn_t pfn, pgprot_t pgprot); -static inline -vm_fault_t vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, - pfn_t pfn, pgprot_t pgprot) -{ - return _kcl_vmf_insert_mixed_prot(vma, addr, pfn, pgprot); -} -#endif /* HAVE_VMF_INSERT_MIXED_PROT */ - #ifndef HAVE_VMF_INSERT_PFN_PROT vm_fault_t _kcl_vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn, pgprot_t pgprot); From 988412002eaa174fdcb40552552c4c3fa56af419 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 16 Sep 2025 14:51:23 +0800 Subject: [PATCH 2122/2653] drm/amdkcl: test whether vmf_insert_mixed_mkwrite() has long pfn arg Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 | 17 +++++++++++++++++ include/kcl/kcl_mm_types.h | 3 +-- 4 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a21f06412b7d1..4cf1bb375d235 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1271,6 +1271,9 @@ /* vmf_insert_*() are available */ #define HAVE_VMF_INSERT 1 +/* vmf_insert_mixed_mkwrite() has long pfn arg */ +/* #undef HAVE_VMF_INSERT_MIXED_MKWRITE_LONG_PFN */ + /* vmf_insert_pfn_prot() is available */ #define HAVE_VMF_INSERT_PFN_PROT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 636f23799f9b6..ba5902455b52a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -295,6 +295,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMEMDUP_ARRAY_USER AC_AMDGPU_BITMAP_READ AC_AMDGPU_VFS_IOCB_ITER_READ + AC_AMDGPU_VMF_INSERT_MIXED_MKWRITE_LONG_PFN AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 index eb41c2919fae8..cd07c76959799 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 @@ -29,3 +29,20 @@ AC_DEFUN([AC_AMDGPU_VMF_INSERT], [ ]) ]) ]) + +dnl # +dnl # commit v6.16-rc5-105-g21aa65bf82a7 +dnl # mm: remove callers of pfn_t functionality +dnl # +AC_DEFUN([AC_AMDGPU_VMF_INSERT_MIXED_MKWRITE_LONG_PFN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + vmf_insert_mixed_mkwrite(NULL, 0, 0); + ],[ + AC_DEFINE(HAVE_VMF_INSERT_MIXED_MKWRITE_LONG_PFN, 1, + [vmf_insert_mixed_mkwrite() has long pfn arg]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm_types.h b/include/kcl/kcl_mm_types.h index 6cf223e559d02..a180469fd2508 100644 --- a/include/kcl/kcl_mm_types.h +++ b/include/kcl/kcl_mm_types.h @@ -31,9 +31,8 @@ static inline unsigned long pfn_t_to_pfn(pfn_t pfn) } #endif -#ifndef HAVE_VMF_INSERT +#if !defined(HAVE_VMF_INSERT) && !defined(HAVE_VMF_INSERT_MIXED_MKWRITE_LONG_PFN) typedef int vm_fault_t; #endif #endif /* AMDKCL_MM_TYPES_H */ - From 26f4b4cd903debd109c73078b4802f8c3f8a339a Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 12 Sep 2025 16:51:55 +0800 Subject: [PATCH 2123/2653] drm/amdkcl: test shmem_writeout want 3 args Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 | 13 +++++++++++++ drivers/gpu/drm/ttm/ttm_backup.c | 4 ++++ 3 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4cf1bb375d235..c37208d8ce9ff 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1144,6 +1144,9 @@ /* shmem_writeout() is available */ #define HAVE_SHMEM_WRITEOUT 1 +/* shmem_writeout() wants 3 arguments */ +/* #undef HAVE_SHMEM_WRITEOUT_WANT_3_ARGS */ + /* shrinker_register() is available */ #define HAVE_SHRINKER_REGISTER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 b/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 index 92f9099fb34e0..1becbe3ee7c21 100644 --- a/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 @@ -11,6 +11,19 @@ AC_DEFUN([AC_AMDGPU_SHMEM_WRITEOUT], [ ],[shmem_writeout], [mm/shmem.c],[ AC_DEFINE(HAVE_SHMEM_WRITEOUT, 1, [shmem_writeout() is available]) + ],[ + dnl # + dnl # commit v6.16-rc5-20-g44b1b073eb36 + dnl # mm: stop passing a writeback_control structure to shmem_writeout + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + shmem_writeout(NULL, NULL,NULL); + ],[shmem_writeout], [mm/shmem.c],[ + AC_DEFINE(HAVE_SHMEM_WRITEOUT_WANT_3_ARGS, 1, + [shmem_writeout() wants 3 arguments]) + ]) ]) ]) ]) diff --git a/drivers/gpu/drm/ttm/ttm_backup.c b/drivers/gpu/drm/ttm/ttm_backup.c index 703fd1427423f..a7e28d7ec1fff 100644 --- a/drivers/gpu/drm/ttm/ttm_backup.c +++ b/drivers/gpu/drm/ttm/ttm_backup.c @@ -114,6 +114,7 @@ ttm_backup_backup_page(struct file *backup, struct page *page, if (writeback && !folio_mapped(to_folio) && folio_clear_dirty_for_io(to_folio)) { +#ifndef HAVE_SHMEM_WRITEOUT_WANT_3_ARGS struct writeback_control wbc = { .sync_mode = WB_SYNC_NONE, .nr_to_write = SWAP_CLUSTER_MAX, @@ -121,9 +122,12 @@ ttm_backup_backup_page(struct file *backup, struct page *page, .range_end = LLONG_MAX, .for_reclaim = 1, }; +#endif folio_set_reclaim(to_folio); #ifdef HAVE_SHMEM_WRITEOUT ret = shmem_writeout(to_folio, &wbc); +#elif defined(HAVE_SHMEM_WRITEOUT_WANT_3_ARGS) + ret = shmem_writeout(to_folio, NULL, NULL); #else ret = mapping->a_ops->writepage(folio_file_page(to_folio, idx), &wbc); #endif From c9274357a025d50a46a8638d7dbc0cd7dc3cfa54 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 1 Jul 2025 12:07:04 +0300 Subject: [PATCH 2124/2653] drm: Pass pixel_format+modifier to .get_format_info() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Decouple .get_format_info() from struct drm_mode_fb_cmd2 and just pass the pixel format+modifier combo in by hand. We may want to use .get_format_info() outside of the normal addfb paths where we won't have a struct drm_mode_fb_cmd2, and creating a temporary one just for this seems silly. v2: Fix intel_fb_get_format_info() docs (Laurent) Cc: Harry Wentland Cc: Leo Li Cc: Rodrigo Siqueira Cc: Alex Deucher Cc: amd-gfx@lists.freedesktop.org Cc: Laurent Pinchart Reviewed-by: Thomas Zimmermann Reviewed-by: Laurent Pinchart Acked-by: Alex Deucher Acked-by: Rodrigo Vivi Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250701090722.13645-2-ville.syrjala@linux.intel.com --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++-- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h | 2 +- drivers/gpu/drm/drm_fourcc.c | 3 ++- drivers/gpu/drm/i915/display/intel_fb.c | 11 ++++++----- drivers/gpu/drm/i915/display/intel_fb.h | 2 +- include/drm/drm_mode_config.h | 2 +- 6 files changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index a0ebaa2a3018f..a3f062c72d49d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -95,9 +95,9 @@ enum dm_micro_swizzle { }; #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED -const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd) +const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier) { - return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]); + return amdgpu_lookup_format_info(pixel_format, modifier); } #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h index 615d2ab2b8034..ea2619b507db7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h @@ -58,7 +58,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, unsigned long possible_crtcs, const struct dc_plane_cap *plane_cap); -const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd); +const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier); void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, bool *per_pixel_alpha, bool *pre_multiplied_alpha, diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c index 2890e889dd151..4b4444f6d5041 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@ -430,7 +430,8 @@ drm_get_format_info(struct drm_device *dev, const struct drm_format_info *info = NULL; if (dev->mode_config.funcs->get_format_info) - info = dev->mode_config.funcs->get_format_info(mode_cmd); + info = dev->mode_config.funcs->get_format_info(mode_cmd->pixel_format, + mode_cmd->modifier[0]); if (!info) info = drm_format_info(mode_cmd->pixel_format); diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 79811f998e385..e221db072de23 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -422,21 +422,22 @@ unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) /** * intel_fb_get_format_info: Get a modifier specific format information - * @cmd: FB add command structure + * @pixel_format: pixel format + * @modifier: modifier * * Returns: - * Returns the format information for @cmd->pixel_format specific to @cmd->modifier[0], + * Returns the format information for @pixel_format specific to @modifier, * or %NULL if the modifier doesn't override the format. */ const struct drm_format_info * -intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd) +intel_fb_get_format_info(u32 pixel_format, u64 modifier) { - const struct intel_modifier_desc *md = lookup_modifier_or_null(cmd->modifier[0]); + const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier); if (!md || !md->formats) return NULL; - return lookup_format_info(md->formats, md->format_count, cmd->pixel_format); + return lookup_format_info(md->formats, md->format_count, pixel_format); } static bool plane_caps_contain_any(u8 caps, u8 mask) diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index bdd76b3729578..7d1267fbeee26 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -47,7 +47,7 @@ u64 *intel_fb_plane_get_modifiers(struct intel_display *display, bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier); const struct drm_format_info * -intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd); +intel_fb_get_format_info(u32 pixel_format, u64 modifier); bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h index 9e524b51a0018..e971e1b8a850c 100644 --- a/include/drm/drm_mode_config.h +++ b/include/drm/drm_mode_config.h @@ -95,7 +95,7 @@ struct drm_mode_config_funcs { * The format information specific to the given fb metadata, or * NULL if none is found. */ - const struct drm_format_info *(*get_format_info)(const struct drm_mode_fb_cmd2 *mode_cmd); + const struct drm_format_info *(*get_format_info)(u32 pixel_format, u64 modifier); /** * @mode_valid: From 9aa3460693e86718e7f700d71667ae4439d7b2d4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 1 Jul 2025 12:07:05 +0300 Subject: [PATCH 2125/2653] drm: Pass pixel_format+modifier directly to drm_get_format_info() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Decouple drm_get_format_info() from struct drm_mode_fb_cmd2 and just pass the pixel format+modifier combo in by hand. We may want to use drm_get_format_info() outside of the normal addfb paths where we won't have a struct drm_mode_fb_cmd2, and creating a temporary one just for this seems silly. Done with cocci: @@ identifier dev, mode_cmd; @@ struct drm_format_info * drm_get_format_info(struct drm_device *dev, - const struct drm_mode_fb_cmd2 *mode_cmd + u32 pixel_format, u64 modifier ) { <... ( - mode_cmd->pixel_format + pixel_format | - mode_cmd->modifier[0] + modifier ) ...> } @@ identifier dev, mode_cmd; @@ struct drm_format_info * drm_get_format_info(struct drm_device *dev, - const struct drm_mode_fb_cmd2 *mode_cmd + u32 pixel_format, u64 modifier ); @@ expression dev, mode_cmd; @@ - drm_get_format_info(dev, mode_cmd) + drm_get_format_info(dev, mode_cmd->pixel_format, mode_cmd->modifier[0]) v2: Fix kernel docs (Laurent) Drop drm_mode_fb_cmd2 forward declaration (Thomas) Cc: Liviu Dudau Cc: Russell King Cc: Inki Dae Cc: Seung-Woo Kim Cc: Kyungmin Park Cc: Patrik Jakobsson Cc: Chun-Kuang Hu Cc: Philipp Zabel Cc: Rob Clark Cc: Abhinav Kumar Cc: Dmitry Baryshkov Cc: Sean Paul Cc: Marijn Suijten Cc: Marek Vasut Cc: Stefan Agner Cc: Lyude Paul Cc: Danilo Krummrich Cc: Tomi Valkeinen Cc: Alex Deucher Cc: Sandy Huang Cc: "Heiko Stübner" Cc: Andy Yan Cc: Thierry Reding Cc: Mikko Perttunen Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Cc: nouveau@lists.freedesktop.org Cc: amd-gfx@lists.freedesktop.org Cc: linux-tegra@vger.kernel.org Reviewed-by: Thomas Zimmermann Reviewed-by: Laurent Pinchart Reviewed-by: Liviu Dudau Acked-by: Alex Deucher Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250701090722.13645-3-ville.syrjala@linux.intel.com --- drivers/gpu/drm/arm/malidp_drv.c | 3 ++- drivers/gpu/drm/armada/armada_fb.c | 4 +++- drivers/gpu/drm/drm_fourcc.c | 11 ++++++----- drivers/gpu/drm/drm_framebuffer.c | 2 +- drivers/gpu/drm/drm_gem_framebuffer_helper.c | 9 ++++++--- drivers/gpu/drm/drm_modeset_helper.c | 3 ++- drivers/gpu/drm/exynos/exynos_drm_fb.c | 4 +++- drivers/gpu/drm/gma500/framebuffer.c | 3 ++- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +++- drivers/gpu/drm/msm/msm_fb.c | 6 ++++-- drivers/gpu/drm/mxsfb/mxsfb_drv.c | 3 ++- drivers/gpu/drm/nouveau/nouveau_display.c | 3 ++- drivers/gpu/drm/omapdrm/omap_fb.c | 6 ++++-- drivers/gpu/drm/radeon/radeon_fbdev.c | 3 ++- drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 3 ++- drivers/gpu/drm/tegra/fb.c | 4 +++- include/drm/drm_fourcc.h | 3 +-- 17 files changed, 48 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index e083021e9e99c..558e44a7e6278 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -325,7 +325,8 @@ malidp_verify_afbc_framebuffer_size(struct drm_device *dev, return false; } - info = drm_get_format_info(dev, mode_cmd); + info = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); n_superblocks = (mode_cmd->width / afbc_superblock_width) * (mode_cmd->height / afbc_superblock_height); diff --git a/drivers/gpu/drm/armada/armada_fb.c b/drivers/gpu/drm/armada/armada_fb.c index cf2e88218dc0b..85fc2cb505449 100644 --- a/drivers/gpu/drm/armada/armada_fb.c +++ b/drivers/gpu/drm/armada/armada_fb.c @@ -86,7 +86,9 @@ struct armada_framebuffer *armada_framebuffer_create(struct drm_device *dev, struct drm_framebuffer *armada_fb_create(struct drm_device *dev, struct drm_file *dfile, const struct drm_mode_fb_cmd2 *mode) { - const struct drm_format_info *info = drm_get_format_info(dev, mode); + const struct drm_format_info *info = drm_get_format_info(dev, + mode->pixel_format, + mode->modifier[0]); struct armada_gem_object *obj; struct armada_framebuffer *dfb; int ret; diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c index 4b4444f6d5041..e0d5336110404 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@ -417,7 +417,8 @@ EXPORT_SYMBOL(drm_format_info); /** * drm_get_format_info - query information for a given framebuffer configuration * @dev: DRM device - * @mode_cmd: metadata from the userspace fb creation request + * @pixel_format: pixel format (DRM_FORMAT_*) + * @modifier: modifier * * Returns: * The instance of struct drm_format_info that describes the pixel format, or @@ -425,16 +426,16 @@ EXPORT_SYMBOL(drm_format_info); */ const struct drm_format_info * drm_get_format_info(struct drm_device *dev, - const struct drm_mode_fb_cmd2 *mode_cmd) + u32 pixel_format, u64 modifier) { const struct drm_format_info *info = NULL; if (dev->mode_config.funcs->get_format_info) - info = dev->mode_config.funcs->get_format_info(mode_cmd->pixel_format, - mode_cmd->modifier[0]); + info = dev->mode_config.funcs->get_format_info(pixel_format, + modifier); if (!info) - info = drm_format_info(mode_cmd->pixel_format); + info = drm_format_info(pixel_format); return info; } diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c index 63a70f285ccea..c952552916009 100644 --- a/drivers/gpu/drm/drm_framebuffer.c +++ b/drivers/gpu/drm/drm_framebuffer.c @@ -176,7 +176,7 @@ static int framebuffer_check(struct drm_device *dev, } /* now let the driver pick its own format info */ - info = drm_get_format_info(dev, r); + info = drm_get_format_info(dev, r->pixel_format, r->modifier[0]); for (i = 0; i < info->num_planes; i++) { unsigned int width = drm_format_info_plane_width(info, r->width, i); diff --git a/drivers/gpu/drm/drm_gem_framebuffer_helper.c b/drivers/gpu/drm/drm_gem_framebuffer_helper.c index fefb2a0f6b405..3af2b1ec87fb8 100644 --- a/drivers/gpu/drm/drm_gem_framebuffer_helper.c +++ b/drivers/gpu/drm/drm_gem_framebuffer_helper.c @@ -160,7 +160,8 @@ int drm_gem_fb_init_with_funcs(struct drm_device *dev, unsigned int i; int ret; - info = drm_get_format_info(dev, mode_cmd); + info = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); if (!info) { drm_dbg_kms(dev, "Failed to get FB format info\n"); return -EINVAL; @@ -506,7 +507,8 @@ static __u32 drm_gem_afbc_get_bpp(struct drm_device *dev, { const struct drm_format_info *info; - info = drm_get_format_info(dev, mode_cmd); + info = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); switch (info->format) { case DRM_FORMAT_YUV420_8BIT: @@ -604,7 +606,8 @@ int drm_gem_fb_afbc_init(struct drm_device *dev, int ret; objs = afbc_fb->base.obj; - info = drm_get_format_info(dev, mode_cmd); + info = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); if (!info) return -EINVAL; diff --git a/drivers/gpu/drm/drm_modeset_helper.c b/drivers/gpu/drm/drm_modeset_helper.c index ef32f6af10d4c..3fed2d5ab1d63 100644 --- a/drivers/gpu/drm/drm_modeset_helper.c +++ b/drivers/gpu/drm/drm_modeset_helper.c @@ -86,7 +86,8 @@ void drm_helper_mode_fill_fb_struct(struct drm_device *dev, int i; fb->dev = dev; - fb->format = drm_get_format_info(dev, mode_cmd); + fb->format = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); fb->width = mode_cmd->width; fb->height = mode_cmd->height; for (i = 0; i < 4; i++) { diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c b/drivers/gpu/drm/exynos/exynos_drm_fb.c index fc1c5608db96f..bcf7b534d1f7e 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fb.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c @@ -96,7 +96,9 @@ static struct drm_framebuffer * exynos_user_fb_create(struct drm_device *dev, struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd) { - const struct drm_format_info *info = drm_get_format_info(dev, mode_cmd); + const struct drm_format_info *info = drm_get_format_info(dev, + mode_cmd->pixel_format, + mode_cmd->modifier[0]); struct exynos_drm_gem *exynos_gem[MAX_FB_BUFFER]; struct drm_framebuffer *fb; int i; diff --git a/drivers/gpu/drm/gma500/framebuffer.c b/drivers/gpu/drm/gma500/framebuffer.c index 1a374702b6960..c82e623a20718 100644 --- a/drivers/gpu/drm/gma500/framebuffer.c +++ b/drivers/gpu/drm/gma500/framebuffer.c @@ -39,7 +39,8 @@ static int psb_framebuffer_init(struct drm_device *dev, * Reject unknown formats, YUV formats, and formats with more than * 4 bytes per pixel. */ - info = drm_get_format_info(dev, mode_cmd); + info = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); if (!info || !info->depth || info->cpp[0] > 4) return -EINVAL; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 7c0c12dde4885..0ebcfcbc258bc 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -45,7 +45,9 @@ mtk_drm_mode_fb_create(struct drm_device *dev, struct drm_file *file, const struct drm_mode_fb_cmd2 *cmd) { - const struct drm_format_info *info = drm_get_format_info(dev, cmd); + const struct drm_format_info *info = drm_get_format_info(dev, + cmd->pixel_format, + cmd->modifier[0]); if (info->num_planes != 1) return ERR_PTR(-EINVAL); diff --git a/drivers/gpu/drm/msm/msm_fb.c b/drivers/gpu/drm/msm/msm_fb.c index bc7c2bb8f01e6..d8a7ac4595bc2 100644 --- a/drivers/gpu/drm/msm/msm_fb.c +++ b/drivers/gpu/drm/msm/msm_fb.c @@ -142,7 +142,8 @@ struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd) { const struct drm_format_info *info = drm_get_format_info(dev, - mode_cmd); + mode_cmd->pixel_format, + mode_cmd->modifier[0]); struct drm_gem_object *bos[4] = {0}; struct drm_framebuffer *fb; int ret, i, n = info->num_planes; @@ -173,7 +174,8 @@ static struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos) { const struct drm_format_info *info = drm_get_format_info(dev, - mode_cmd); + mode_cmd->pixel_format, + mode_cmd->modifier[0]); struct msm_drm_private *priv = dev->dev_private; struct msm_kms *kms = priv->kms; struct msm_framebuffer *msm_fb = NULL; diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c index c183b1112bc4e..09329af9b01ea 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c @@ -95,7 +95,8 @@ mxsfb_fb_create(struct drm_device *dev, struct drm_file *file_priv, { const struct drm_format_info *info; - info = drm_get_format_info(dev, mode_cmd); + info = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); if (!info) return ERR_PTR(-EINVAL); diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index c50ec347b30a9..bd9a85f4b4fcb 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -295,7 +295,8 @@ nouveau_framebuffer_new(struct drm_device *dev, kind = nvbo->kind; } - info = drm_get_format_info(dev, mode_cmd); + info = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); for (i = 0; i < info->num_planes; i++) { height = drm_format_info_plane_height(info, diff --git a/drivers/gpu/drm/omapdrm/omap_fb.c b/drivers/gpu/drm/omapdrm/omap_fb.c index 449d521c78fed..e18878068c578 100644 --- a/drivers/gpu/drm/omapdrm/omap_fb.c +++ b/drivers/gpu/drm/omapdrm/omap_fb.c @@ -338,7 +338,8 @@ struct drm_framebuffer *omap_framebuffer_create(struct drm_device *dev, struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd) { const struct drm_format_info *info = drm_get_format_info(dev, - mode_cmd); + mode_cmd->pixel_format, + mode_cmd->modifier[0]); unsigned int num_planes = info->num_planes; struct drm_gem_object *bos[4]; struct drm_framebuffer *fb; @@ -378,7 +379,8 @@ struct drm_framebuffer *omap_framebuffer_init(struct drm_device *dev, dev, mode_cmd, mode_cmd->width, mode_cmd->height, (char *)&mode_cmd->pixel_format); - format = drm_get_format_info(dev, mode_cmd); + format = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); for (i = 0; i < ARRAY_SIZE(formats); i++) { if (formats[i] == mode_cmd->pixel_format) diff --git a/drivers/gpu/drm/radeon/radeon_fbdev.c b/drivers/gpu/drm/radeon/radeon_fbdev.c index d4a58bd679dbc..e3a481bbee7b6 100644 --- a/drivers/gpu/drm/radeon/radeon_fbdev.c +++ b/drivers/gpu/drm/radeon/radeon_fbdev.c @@ -67,7 +67,8 @@ static int radeon_fbdev_create_pinned_object(struct drm_fb_helper *fb_helper, int height = mode_cmd->height; u32 cpp; - info = drm_get_format_info(rdev_to_drm(rdev), mode_cmd); + info = drm_get_format_info(rdev_to_drm(rdev), mode_cmd->pixel_format, + mode_cmd->modifier[0]); cpp = info->cpp[0]; /* need to align pitch with crtc limits */ diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c index 5829ee061c61b..66762ca54a98e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c @@ -36,7 +36,8 @@ rockchip_fb_create(struct drm_device *dev, struct drm_file *file, const struct drm_format_info *info; int ret; - info = drm_get_format_info(dev, mode_cmd); + info = drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); if (!info) return ERR_PTR(-ENOMEM); diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c index 46170753699dc..634c6346d947f 100644 --- a/drivers/gpu/drm/tegra/fb.c +++ b/drivers/gpu/drm/tegra/fb.c @@ -134,7 +134,9 @@ struct drm_framebuffer *tegra_fb_create(struct drm_device *drm, struct drm_file *file, const struct drm_mode_fb_cmd2 *cmd) { - const struct drm_format_info *info = drm_get_format_info(drm, cmd); + const struct drm_format_info *info = drm_get_format_info(drm, + cmd->pixel_format, + cmd->modifier[0]); struct tegra_bo *planes[4]; struct drm_gem_object *gem; struct drm_framebuffer *fb; diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h index c3f4405d66629..4717844268573 100644 --- a/include/drm/drm_fourcc.h +++ b/include/drm/drm_fourcc.h @@ -54,7 +54,6 @@ #endif struct drm_device; -struct drm_mode_fb_cmd2; /** * struct drm_format_info - information about a DRM format @@ -309,7 +308,7 @@ const struct drm_format_info *__drm_format_info(u32 format); const struct drm_format_info *drm_format_info(u32 format); const struct drm_format_info * drm_get_format_info(struct drm_device *dev, - const struct drm_mode_fb_cmd2 *mode_cmd); + u32 pixel_format, u64 modifier); uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t depth); uint32_t drm_driver_legacy_fb_format(struct drm_device *dev, uint32_t bpp, uint32_t depth); From 9af65705f11c46808be4c3239dcf05b8064ca563 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 1 Jul 2025 12:07:06 +0300 Subject: [PATCH 2126/2653] drm: Look up the format info earlier MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Look up the format info already in drm_internal_framebuffer_create() so that we can later pass it along to .fb_create(). Currently various drivers are doing additional lookups in their .fb_create() implementations, and these lookups are rather expensive now (given how many different pixel formats we have). v2: Fix commit msg (Thomas) Reviewed-by: Thomas Zimmermann Reviewed-by: Laurent Pinchart Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250701090722.13645-4-ville.syrjala@linux.intel.com --- drivers/gpu/drm/drm_framebuffer.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c index c952552916009..1f286087ba307 100644 --- a/drivers/gpu/drm/drm_framebuffer.c +++ b/drivers/gpu/drm/drm_framebuffer.c @@ -153,18 +153,11 @@ int drm_mode_addfb_ioctl(struct drm_device *dev, } static int framebuffer_check(struct drm_device *dev, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *r) { - const struct drm_format_info *info; int i; - /* check if the format is supported at all */ - if (!__drm_format_info(r->pixel_format)) { - drm_dbg_kms(dev, "bad framebuffer format %p4cc\n", - &r->pixel_format); - return -EINVAL; - } - if (r->width == 0) { drm_dbg_kms(dev, "bad framebuffer width %u\n", r->width); return -EINVAL; @@ -175,9 +168,6 @@ static int framebuffer_check(struct drm_device *dev, return -EINVAL; } - /* now let the driver pick its own format info */ - info = drm_get_format_info(dev, r->pixel_format, r->modifier[0]); - for (i = 0; i < info->num_planes; i++) { unsigned int width = drm_format_info_plane_width(info, r->width, i); unsigned int height = drm_format_info_plane_height(info, r->height, i); @@ -272,6 +262,7 @@ drm_internal_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv) { struct drm_mode_config *config = &dev->mode_config; + const struct drm_format_info *info; struct drm_framebuffer *fb; int ret; @@ -297,7 +288,17 @@ drm_internal_framebuffer_create(struct drm_device *dev, return ERR_PTR(-EINVAL); } - ret = framebuffer_check(dev, r); + /* check if the format is supported at all */ + if (!__drm_format_info(r->pixel_format)) { + drm_dbg_kms(dev, "bad framebuffer format %p4cc\n", + &r->pixel_format); + return ERR_PTR(-EINVAL); + } + + /* now let the driver pick its own format info */ + info = drm_get_format_info(dev, r->pixel_format, r->modifier[0]); + + ret = framebuffer_check(dev, info, r); if (ret) return ERR_PTR(ret); From a85b824db5aaf9d479d26c49baf94b4263084dc5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 1 Jul 2025 12:07:07 +0300 Subject: [PATCH 2127/2653] drm: Pass the format info to .fb_create() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pass along the format information from the top to .fb_create() so that we can avoid redundant (and somewhat expensive) lookups in the drivers. Done with cocci (with some manual fixups): @@ identifier func =~ ".*create.*"; identifier dev, file, mode_cmd; @@ struct drm_framebuffer *func( struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { ... ( - const struct drm_format_info *info = drm_get_format_info(...); | - const struct drm_format_info *info; ... - info = drm_get_format_info(...); ) <... - if (!info) - return ...; ...> } @@ identifier func =~ ".*create.*"; identifier dev, file, mode_cmd; @@ struct drm_framebuffer *func( struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { ... } @find@ identifier fb_create_func =~ ".*create.*"; identifier dev, file, mode_cmd; @@ struct drm_framebuffer *fb_create_func( struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd); @@ identifier find.fb_create_func; expression dev, file, mode_cmd; @@ fb_create_func(dev, file + ,info ,mode_cmd) @@ expression dev, file, mode_cmd; @@ drm_gem_fb_create(dev, file + ,info ,mode_cmd) @@ expression dev, file, mode_cmd; @@ drm_gem_fb_create_with_dirty(dev, file + ,info ,mode_cmd) @@ expression dev, file_priv, mode_cmd; identifier info, fb; @@ info = drm_get_format_info(...); ... fb = dev->mode_config.funcs->fb_create(dev, file_priv + ,info ,mode_cmd); @@ identifier dev, file_priv, mode_cmd; @@ struct drm_mode_config_funcs { ... struct drm_framebuffer *(*fb_create)(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd); ... }; v2: Fix kernel docs (Laurent) Fix commit msg (Geert) Cc: Alex Deucher Cc: Liviu Dudau Cc: Maxime Ripard Cc: Russell King Cc: Inki Dae Cc: Seung-Woo Kim Cc: Kyungmin Park Cc: Patrik Jakobsson Cc: Chun-Kuang Hu Cc: Philipp Zabel Cc: Rob Clark Cc: Abhinav Kumar Cc: Dmitry Baryshkov Cc: Sean Paul Cc: Marijn Suijten Cc: Marek Vasut Cc: Stefan Agner Cc: Lyude Paul Cc: Danilo Krummrich Cc: Tomi Valkeinen Cc: Dave Airlie Cc: Gerd Hoffmann Cc: Kieran Bingham Cc: Biju Das Cc: Sandy Huang Cc: "Heiko Stübner" Cc: Andy Yan Cc: Thierry Reding Cc: Mikko Perttunen Cc: Dave Stevenson Cc: "Maíra Canal" Cc: Raspberry Pi Kernel Maintenance Cc: Dmitry Osipenko Cc: Gurchetan Singh Cc: Chia-I Wu Cc: Zack Rusin Cc: Broadcom internal kernel review list Cc: Oleksandr Andrushchenko Cc: amd-gfx@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Cc: nouveau@lists.freedesktop.org Cc: virtualization@lists.linux.dev Cc: spice-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Reviewed-by: Thomas Zimmermann Reviewed-by: Dmitry Baryshkov Acked-by: Liviu Dudau Reviewed-by: Laurent Pinchart Acked-by: Alex Deucher Acked-by: Rodrigo Vivi Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250701090722.13645-5-ville.syrjala@linux.intel.com --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 1 + .../gpu/drm/arm/display/komeda/komeda_framebuffer.c | 1 + .../gpu/drm/arm/display/komeda/komeda_framebuffer.h | 1 + drivers/gpu/drm/arm/malidp_drv.c | 3 ++- drivers/gpu/drm/armada/armada_fb.c | 6 ++---- drivers/gpu/drm/armada/armada_fb.h | 3 ++- drivers/gpu/drm/drm_framebuffer.c | 2 +- drivers/gpu/drm/drm_gem_framebuffer_helper.c | 4 ++++ drivers/gpu/drm/exynos/exynos_drm_fb.c | 4 +--- drivers/gpu/drm/gma500/framebuffer.c | 1 + drivers/gpu/drm/i915/display/intel_fb.c | 1 + drivers/gpu/drm/i915/display/intel_fb.h | 1 + drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 5 +++-- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 7 ++----- drivers/gpu/drm/msm/msm_drv.h | 3 ++- drivers/gpu/drm/msm/msm_fb.c | 6 ++---- drivers/gpu/drm/mxsfb/mxsfb_drv.c | 10 ++-------- drivers/gpu/drm/nouveau/nouveau_display.c | 1 + drivers/gpu/drm/nouveau/nouveau_display.h | 1 + drivers/gpu/drm/omapdrm/omap_fb.c | 6 ++---- drivers/gpu/drm/omapdrm/omap_fb.h | 3 ++- drivers/gpu/drm/qxl/qxl_display.c | 1 + drivers/gpu/drm/radeon/radeon_display.c | 1 + drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c | 3 ++- drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c | 3 ++- drivers/gpu/drm/renesas/shmobile/shmob_drm_kms.c | 3 ++- drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 7 +------ drivers/gpu/drm/tegra/drm.h | 1 + drivers/gpu/drm/tegra/fb.c | 4 +--- drivers/gpu/drm/tests/drm_framebuffer_test.c | 1 + drivers/gpu/drm/vc4/vc4_kms.c | 3 ++- drivers/gpu/drm/virtio/virtgpu_display.c | 1 + drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 1 + drivers/gpu/drm/xen/xen_drm_front_kms.c | 1 + drivers/gpu/drm/xlnx/zynqmp_kms.c | 3 ++- include/drm/drm_gem_framebuffer_helper.h | 3 +++ include/drm/drm_mode_config.h | 1 + 38 files changed, 59 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index e84be362b6ae1..11aa38d8e9ffc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1345,6 +1345,7 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, struct drm_framebuffer * amdgpu_display_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct amdgpu_framebuffer *amdgpu_fb; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h index 4eaee10a1b7c0..4309b0e0849e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h @@ -44,6 +44,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, struct drm_framebuffer * amdgpu_display_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd); const struct drm_format_info * amdgpu_lookup_format_info(u32 format, uint64_t modifier); diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c b/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c index df5da5a447555..29b05482f713f 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c @@ -157,6 +157,7 @@ komeda_fb_none_afbc_size_check(struct komeda_dev *mdev, struct komeda_fb *kfb, struct drm_framebuffer * komeda_fb_create(struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct komeda_dev *mdev = dev->dev_private; diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.h b/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.h index c61ca98a3a637..02b2b8ae482ae 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.h +++ b/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.h @@ -37,6 +37,7 @@ struct komeda_fb { struct drm_framebuffer * komeda_fb_create(struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd); int komeda_fb_check_src_coords(const struct komeda_fb *kfb, u32 src_x, u32 src_y, u32 src_w, u32 src_h); diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index 558e44a7e6278..8b920566f2e89 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -377,6 +377,7 @@ malidp_verify_afbc_framebuffer(struct drm_device *dev, struct drm_file *file, static struct drm_framebuffer * malidp_fb_create(struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { if (mode_cmd->modifier[0]) { @@ -384,7 +385,7 @@ malidp_fb_create(struct drm_device *dev, struct drm_file *file, return ERR_PTR(-EINVAL); } - return drm_gem_fb_create(dev, file, mode_cmd); + return drm_gem_fb_create(dev, file, info, mode_cmd); } static const struct drm_mode_config_funcs malidp_mode_config_funcs = { diff --git a/drivers/gpu/drm/armada/armada_fb.c b/drivers/gpu/drm/armada/armada_fb.c index 85fc2cb505449..597720e229c26 100644 --- a/drivers/gpu/drm/armada/armada_fb.c +++ b/drivers/gpu/drm/armada/armada_fb.c @@ -84,11 +84,9 @@ struct armada_framebuffer *armada_framebuffer_create(struct drm_device *dev, } struct drm_framebuffer *armada_fb_create(struct drm_device *dev, - struct drm_file *dfile, const struct drm_mode_fb_cmd2 *mode) + struct drm_file *dfile, const struct drm_format_info *info, + const struct drm_mode_fb_cmd2 *mode) { - const struct drm_format_info *info = drm_get_format_info(dev, - mode->pixel_format, - mode->modifier[0]); struct armada_gem_object *obj; struct armada_framebuffer *dfb; int ret; diff --git a/drivers/gpu/drm/armada/armada_fb.h b/drivers/gpu/drm/armada/armada_fb.h index c5bc53d7e0c4c..41ba76dd80d6f 100644 --- a/drivers/gpu/drm/armada/armada_fb.h +++ b/drivers/gpu/drm/armada/armada_fb.h @@ -19,5 +19,6 @@ struct armada_framebuffer { struct armada_framebuffer *armada_framebuffer_create(struct drm_device *, const struct drm_mode_fb_cmd2 *, struct armada_gem_object *); struct drm_framebuffer *armada_fb_create(struct drm_device *dev, - struct drm_file *dfile, const struct drm_mode_fb_cmd2 *mode); + struct drm_file *dfile, const struct drm_format_info *info, + const struct drm_mode_fb_cmd2 *mode); #endif diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c index 1f286087ba307..adbb73f00d68b 100644 --- a/drivers/gpu/drm/drm_framebuffer.c +++ b/drivers/gpu/drm/drm_framebuffer.c @@ -302,7 +302,7 @@ drm_internal_framebuffer_create(struct drm_device *dev, if (ret) return ERR_PTR(ret); - fb = dev->mode_config.funcs->fb_create(dev, file_priv, r); + fb = dev->mode_config.funcs->fb_create(dev, file_priv, info, r); if (IS_ERR(fb)) { drm_dbg_kms(dev, "could not create framebuffer\n"); return fb; diff --git a/drivers/gpu/drm/drm_gem_framebuffer_helper.c b/drivers/gpu/drm/drm_gem_framebuffer_helper.c index 3af2b1ec87fb8..982f7abd5eb57 100644 --- a/drivers/gpu/drm/drm_gem_framebuffer_helper.c +++ b/drivers/gpu/drm/drm_gem_framebuffer_helper.c @@ -264,6 +264,7 @@ static const struct drm_framebuffer_funcs drm_gem_fb_funcs = { * &drm_mode_config_funcs.fb_create callback * @dev: DRM device * @file: DRM file that holds the GEM handle(s) backing the framebuffer + * @info: pixel format information * @mode_cmd: Metadata from the userspace framebuffer creation request * * This function creates a new framebuffer object described by @@ -283,6 +284,7 @@ static const struct drm_framebuffer_funcs drm_gem_fb_funcs = { */ struct drm_framebuffer * drm_gem_fb_create(struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { return drm_gem_fb_create_with_funcs(dev, file, mode_cmd, @@ -301,6 +303,7 @@ static const struct drm_framebuffer_funcs drm_gem_fb_funcs_dirtyfb = { * &drm_mode_config_funcs.fb_create callback * @dev: DRM device * @file: DRM file that holds the GEM handle(s) backing the framebuffer + * @info: pixel format information * @mode_cmd: Metadata from the userspace framebuffer creation request * * This function creates a new framebuffer object described by @@ -321,6 +324,7 @@ static const struct drm_framebuffer_funcs drm_gem_fb_funcs_dirtyfb = { */ struct drm_framebuffer * drm_gem_fb_create_with_dirty(struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { return drm_gem_fb_create_with_funcs(dev, file, mode_cmd, diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c b/drivers/gpu/drm/exynos/exynos_drm_fb.c index bcf7b534d1f7e..9ae526825726c 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fb.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c @@ -94,11 +94,9 @@ exynos_drm_framebuffer_init(struct drm_device *dev, static struct drm_framebuffer * exynos_user_fb_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { - const struct drm_format_info *info = drm_get_format_info(dev, - mode_cmd->pixel_format, - mode_cmd->modifier[0]); struct exynos_drm_gem *exynos_gem[MAX_FB_BUFFER]; struct drm_framebuffer *fb; int i; diff --git a/drivers/gpu/drm/gma500/framebuffer.c b/drivers/gpu/drm/gma500/framebuffer.c index c82e623a20718..a4a18ec2dd566 100644 --- a/drivers/gpu/drm/gma500/framebuffer.c +++ b/drivers/gpu/drm/gma500/framebuffer.c @@ -97,6 +97,7 @@ struct drm_framebuffer *psb_framebuffer_create(struct drm_device *dev, */ static struct drm_framebuffer *psb_user_framebuffer_create (struct drm_device *dev, struct drm_file *filp, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *cmd) { struct drm_gem_object *obj; diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index e221db072de23..96edc791c33bb 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -2324,6 +2324,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, struct drm_framebuffer * intel_user_framebuffer_create(struct drm_device *dev, struct drm_file *filp, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *user_mode_cmd) { struct drm_framebuffer *fb; diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index 7d1267fbeee26..00181c4a67dc8 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -109,6 +109,7 @@ intel_framebuffer_create(struct drm_gem_object *obj, struct drm_framebuffer * intel_user_framebuffer_create(struct drm_device *dev, struct drm_file *filp, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *user_mode_cmd); bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier); diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c index f851e9ffdb280..9db1ceaed5188 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c @@ -901,14 +901,15 @@ static void ingenic_drm_disable_vblank(struct drm_crtc *crtc) static struct drm_framebuffer * ingenic_drm_gem_fb_create(struct drm_device *drm, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct ingenic_drm *priv = drm_device_get_priv(drm); if (priv->soc_info->map_noncoherent) - return drm_gem_fb_create_with_dirty(drm, file, mode_cmd); + return drm_gem_fb_create_with_dirty(drm, file, info, mode_cmd); - return drm_gem_fb_create(drm, file, mode_cmd); + return drm_gem_fb_create(drm, file, info, mode_cmd); } static struct drm_gem_object * diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 0ebcfcbc258bc..d5e6bab364143 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -43,16 +43,13 @@ static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = { static struct drm_framebuffer * mtk_drm_mode_fb_create(struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *cmd) { - const struct drm_format_info *info = drm_get_format_info(dev, - cmd->pixel_format, - cmd->modifier[0]); - if (info->num_planes != 1) return ERR_PTR(-EINVAL); - return drm_gem_fb_create(dev, file, cmd); + return drm_gem_fb_create(dev, file, info, cmd); } static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 9875ca62e9adb..985db9febd98e 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -260,7 +260,8 @@ uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int plane); struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, - struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); + struct drm_file *file, const struct drm_format_info *info, + const struct drm_mode_fb_cmd2 *mode_cmd); struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, int w, int h, int p, uint32_t format); diff --git a/drivers/gpu/drm/msm/msm_fb.c b/drivers/gpu/drm/msm/msm_fb.c index d8a7ac4595bc2..f151244e8cfb3 100644 --- a/drivers/gpu/drm/msm/msm_fb.c +++ b/drivers/gpu/drm/msm/msm_fb.c @@ -139,11 +139,9 @@ const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb) } struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, - struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd) + struct drm_file *file, const struct drm_format_info *info, + const struct drm_mode_fb_cmd2 *mode_cmd) { - const struct drm_format_info *info = drm_get_format_info(dev, - mode_cmd->pixel_format, - mode_cmd->modifier[0]); struct drm_gem_object *bos[4] = {0}; struct drm_framebuffer *fb; int ret, i, n = info->num_planes; diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c index 09329af9b01ea..0b756da2fec22 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c @@ -91,21 +91,15 @@ void mxsfb_disable_axi_clk(struct mxsfb_drm_private *mxsfb) static struct drm_framebuffer * mxsfb_fb_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { - const struct drm_format_info *info; - - info = drm_get_format_info(dev, mode_cmd->pixel_format, - mode_cmd->modifier[0]); - if (!info) - return ERR_PTR(-EINVAL); - if (mode_cmd->width * info->cpp[0] != mode_cmd->pitches[0]) { dev_dbg(dev->dev, "Invalid pitch: fb width must match pitch\n"); return ERR_PTR(-EINVAL); } - return drm_gem_fb_create(dev, file_priv, mode_cmd); + return drm_gem_fb_create(dev, file_priv, info, mode_cmd); } static const struct drm_mode_config_funcs mxsfb_mode_config_funcs = { diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index bd9a85f4b4fcb..1ddd929015262 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -333,6 +333,7 @@ nouveau_framebuffer_new(struct drm_device *dev, struct drm_framebuffer * nouveau_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct drm_framebuffer *fb; diff --git a/drivers/gpu/drm/nouveau/nouveau_display.h b/drivers/gpu/drm/nouveau/nouveau_display.h index 1f506f8b289c9..e45f211501f61 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.h +++ b/drivers/gpu/drm/nouveau/nouveau_display.h @@ -67,5 +67,6 @@ nouveau_framebuffer_get_layout(struct drm_framebuffer *fb, uint32_t *tile_mode, struct drm_framebuffer * nouveau_user_framebuffer_create(struct drm_device *, struct drm_file *, + const struct drm_format_info *, const struct drm_mode_fb_cmd2 *); #endif diff --git a/drivers/gpu/drm/omapdrm/omap_fb.c b/drivers/gpu/drm/omapdrm/omap_fb.c index e18878068c578..36afcd1c1fd74 100644 --- a/drivers/gpu/drm/omapdrm/omap_fb.c +++ b/drivers/gpu/drm/omapdrm/omap_fb.c @@ -335,11 +335,9 @@ void omap_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m) #endif struct drm_framebuffer *omap_framebuffer_create(struct drm_device *dev, - struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd) + struct drm_file *file, const struct drm_format_info *info, + const struct drm_mode_fb_cmd2 *mode_cmd) { - const struct drm_format_info *info = drm_get_format_info(dev, - mode_cmd->pixel_format, - mode_cmd->modifier[0]); unsigned int num_planes = info->num_planes; struct drm_gem_object *bos[4]; struct drm_framebuffer *fb; diff --git a/drivers/gpu/drm/omapdrm/omap_fb.h b/drivers/gpu/drm/omapdrm/omap_fb.h index b75f0b5ef1d8c..0873f953cf1d1 100644 --- a/drivers/gpu/drm/omapdrm/omap_fb.h +++ b/drivers/gpu/drm/omapdrm/omap_fb.h @@ -20,7 +20,8 @@ struct omap_overlay_info; struct seq_file; struct drm_framebuffer *omap_framebuffer_create(struct drm_device *dev, - struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); + struct drm_file *file, const struct drm_format_info *info, + const struct drm_mode_fb_cmd2 *mode_cmd); struct drm_framebuffer *omap_framebuffer_init(struct drm_device *dev, const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); int omap_framebuffer_pin(struct drm_framebuffer *fb); diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c index 70aff64ced87a..f7bc83f2d4893 100644 --- a/drivers/gpu/drm/qxl/qxl_display.c +++ b/drivers/gpu/drm/qxl/qxl_display.c @@ -1176,6 +1176,7 @@ static int qdev_output_init(struct drm_device *dev, int num_output) static struct drm_framebuffer * qxl_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { return drm_gem_fb_create_with_funcs(dev, file_priv, mode_cmd, diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 79cbd0c71d5d4..b4aa2bc51bfd5 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -1314,6 +1314,7 @@ radeon_framebuffer_init(struct drm_device *dev, static struct drm_framebuffer * radeon_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct drm_gem_object *obj; diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c index 4c8fe83dd6101..216219accfd9d 100644 --- a/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c @@ -426,6 +426,7 @@ int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev, static struct drm_framebuffer * rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct rcar_du_device *rcdu = to_rcar_du_device(dev); @@ -490,7 +491,7 @@ rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv, } } - return drm_gem_fb_create(dev, file_priv, mode_cmd); + return drm_gem_fb_create(dev, file_priv, info, mode_cmd); } /* ----------------------------------------------------------------------------- diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c index 55a97691e9b25..87f171145a230 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c @@ -191,6 +191,7 @@ int rzg2l_du_dumb_create(struct drm_file *file, struct drm_device *dev, static struct drm_framebuffer * rzg2l_du_fb_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { const struct rzg2l_du_format_info *format; @@ -214,7 +215,7 @@ rzg2l_du_fb_create(struct drm_device *dev, struct drm_file *file_priv, return ERR_PTR(-EINVAL); } - return drm_gem_fb_create(dev, file_priv, mode_cmd); + return drm_gem_fb_create(dev, file_priv, info, mode_cmd); } /* ----------------------------------------------------------------------------- diff --git a/drivers/gpu/drm/renesas/shmobile/shmob_drm_kms.c b/drivers/gpu/drm/renesas/shmobile/shmob_drm_kms.c index 4202ab00fb0cf..fd9460da1789b 100644 --- a/drivers/gpu/drm/renesas/shmobile/shmob_drm_kms.c +++ b/drivers/gpu/drm/renesas/shmobile/shmob_drm_kms.c @@ -117,6 +117,7 @@ const struct shmob_drm_format_info *shmob_drm_format_info(u32 fourcc) static struct drm_framebuffer * shmob_drm_fb_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { const struct shmob_drm_format_info *format; @@ -144,7 +145,7 @@ shmob_drm_fb_create(struct drm_device *dev, struct drm_file *file_priv, } } - return drm_gem_fb_create(dev, file_priv, mode_cmd); + return drm_gem_fb_create(dev, file_priv, info, mode_cmd); } static const struct drm_mode_config_funcs shmob_drm_mode_config_funcs = { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c index 66762ca54a98e..f19113e5ae8fa 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c @@ -30,17 +30,12 @@ static const struct drm_mode_config_helper_funcs rockchip_mode_config_helpers = static struct drm_framebuffer * rockchip_fb_create(struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct drm_afbc_framebuffer *afbc_fb; - const struct drm_format_info *info; int ret; - info = drm_get_format_info(dev, mode_cmd->pixel_format, - mode_cmd->modifier[0]); - if (!info) - return ERR_PTR(-ENOMEM); - afbc_fb = kzalloc(sizeof(*afbc_fb), GFP_KERNEL); if (!afbc_fb) return ERR_PTR(-ENOMEM); diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h index 0b65e69f3a8ad..77e520c43f72c 100644 --- a/drivers/gpu/drm/tegra/drm.h +++ b/drivers/gpu/drm/tegra/drm.h @@ -190,6 +190,7 @@ struct drm_framebuffer *tegra_fb_alloc(struct drm_device *drm, unsigned int num_planes); struct drm_framebuffer *tegra_fb_create(struct drm_device *drm, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *cmd); #ifdef CONFIG_DRM_FBDEV_EMULATION diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c index 634c6346d947f..24907573e758d 100644 --- a/drivers/gpu/drm/tegra/fb.c +++ b/drivers/gpu/drm/tegra/fb.c @@ -132,11 +132,9 @@ struct drm_framebuffer *tegra_fb_alloc(struct drm_device *drm, struct drm_framebuffer *tegra_fb_create(struct drm_device *drm, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *cmd) { - const struct drm_format_info *info = drm_get_format_info(drm, - cmd->pixel_format, - cmd->modifier[0]); struct tegra_bo *planes[4]; struct drm_gem_object *gem; struct drm_framebuffer *fb; diff --git a/drivers/gpu/drm/tests/drm_framebuffer_test.c b/drivers/gpu/drm/tests/drm_framebuffer_test.c index 6ea04cc8f3241..9b8e01e8cd91b 100644 --- a/drivers/gpu/drm/tests/drm_framebuffer_test.c +++ b/drivers/gpu/drm/tests/drm_framebuffer_test.c @@ -363,6 +363,7 @@ struct drm_framebuffer_test_priv { static struct drm_framebuffer *fb_create_mock(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct drm_framebuffer_test_priv *priv = container_of(dev, typeof(*priv), dev); diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c index f5b1674174289..8f983edb81ff0 100644 --- a/drivers/gpu/drm/vc4/vc4_kms.c +++ b/drivers/gpu/drm/vc4/vc4_kms.c @@ -530,6 +530,7 @@ static int vc4_atomic_commit_setup(struct drm_atomic_state *state) static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct vc4_dev *vc4 = to_vc4_dev(dev); @@ -568,7 +569,7 @@ static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev, mode_cmd = &mode_cmd_local; } - return drm_gem_fb_create(dev, file_priv, mode_cmd); + return drm_gem_fb_create(dev, file_priv, info, mode_cmd); } /* Our CTM has some peculiar limitations: we can only enable it for one CRTC diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c b/drivers/gpu/drm/virtio/virtgpu_display.c index 59a45e74a6412..f9a98fbbabd1a 100644 --- a/drivers/gpu/drm/virtio/virtgpu_display.c +++ b/drivers/gpu/drm/virtio/virtgpu_display.c @@ -293,6 +293,7 @@ static int vgdev_output_init(struct virtio_gpu_device *vgdev, int index) static struct drm_framebuffer * virtio_gpu_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct drm_gem_object *obj = NULL; diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c index 05b1c54a070cb..2d48a28cda9c0 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c @@ -712,6 +712,7 @@ vmw_kms_new_framebuffer(struct vmw_private *dev_priv, static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct vmw_private *dev_priv = vmw_priv(dev); diff --git a/drivers/gpu/drm/xen/xen_drm_front_kms.c b/drivers/gpu/drm/xen/xen_drm_front_kms.c index dfa78a49a6d95..a360003bee471 100644 --- a/drivers/gpu/drm/xen/xen_drm_front_kms.c +++ b/drivers/gpu/drm/xen/xen_drm_front_kms.c @@ -54,6 +54,7 @@ static const struct drm_framebuffer_funcs fb_funcs = { static struct drm_framebuffer * fb_create(struct drm_device *dev, struct drm_file *filp, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct xen_drm_front_drm_info *drm_info = dev->dev_private; diff --git a/drivers/gpu/drm/xlnx/zynqmp_kms.c b/drivers/gpu/drm/xlnx/zynqmp_kms.c index b474634734728..2bee0a2275ede 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_kms.c +++ b/drivers/gpu/drm/xlnx/zynqmp_kms.c @@ -373,6 +373,7 @@ static int zynqmp_dpsub_dumb_create(struct drm_file *file_priv, static struct drm_framebuffer * zynqmp_dpsub_fb_create(struct drm_device *drm, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { struct zynqmp_dpsub *dpsub = to_zynqmp_dpsub(drm); @@ -383,7 +384,7 @@ zynqmp_dpsub_fb_create(struct drm_device *drm, struct drm_file *file_priv, for (i = 0; i < ARRAY_SIZE(cmd.pitches); ++i) cmd.pitches[i] = ALIGN(cmd.pitches[i], dpsub->dma_align); - return drm_gem_fb_create(drm, file_priv, &cmd); + return drm_gem_fb_create(drm, file_priv, info, &cmd); } static const struct drm_mode_config_funcs zynqmp_dpsub_mode_config_funcs = { diff --git a/include/drm/drm_gem_framebuffer_helper.h b/include/drm/drm_gem_framebuffer_helper.h index d302521f3dd48..4fdf9d3d18638 100644 --- a/include/drm/drm_gem_framebuffer_helper.h +++ b/include/drm/drm_gem_framebuffer_helper.h @@ -8,6 +8,7 @@ struct drm_afbc_framebuffer; struct drm_device; struct drm_fb_helper_surface_size; struct drm_file; +struct drm_format_info; struct drm_framebuffer; struct drm_framebuffer_funcs; struct drm_gem_object; @@ -32,9 +33,11 @@ drm_gem_fb_create_with_funcs(struct drm_device *dev, struct drm_file *file, const struct drm_framebuffer_funcs *funcs); struct drm_framebuffer * drm_gem_fb_create(struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd); struct drm_framebuffer * drm_gem_fb_create_with_dirty(struct drm_device *dev, struct drm_file *file, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd); int drm_gem_fb_vmap(struct drm_framebuffer *fb, struct iosys_map *map, diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h index e971e1b8a850c..2e848b8162185 100644 --- a/include/drm/drm_mode_config.h +++ b/include/drm/drm_mode_config.h @@ -82,6 +82,7 @@ struct drm_mode_config_funcs { */ struct drm_framebuffer *(*fb_create)(struct drm_device *dev, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd); /** From 4eff94bb6e0db2791ab96eacfa95473426692a38 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 1 Jul 2025 12:07:08 +0300 Subject: [PATCH 2128/2653] drm: Allow the caller to pass in the format info to drm_helper_mode_fill_fb_struct() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Soon all drivers should have the format info already available in the places where they call drm_helper_mode_fill_fb_struct(). Allow it to be passed along into drm_helper_mode_fill_fb_struct() instead of doing yet another redundant lookup. Start by always passing in NULL and still doing the extra lookup. The actual changes to avoid the lookup will follow. Done with cocci (with some manual fixups): @@ identifier dev, fb, mode_cmd; expression get_format_info; @@ void drm_helper_mode_fill_fb_struct(struct drm_device *dev, struct drm_framebuffer *fb, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { ... - fb->format = get_format_info; + fb->format = info ?: get_format_info; ... } @@ identifier dev, fb, mode_cmd; @@ void drm_helper_mode_fill_fb_struct(struct drm_device *dev, struct drm_framebuffer *fb, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd); @@ expression dev, fb, mode_cmd; @@ drm_helper_mode_fill_fb_struct(dev, fb + ,NULL ,mode_cmd); Cc: Alex Deucher Cc: Liviu Dudau Cc: Russell King Cc: Inki Dae Cc: Seung-Woo Kim Cc: Kyungmin Park Cc: Patrik Jakobsson Cc: Rob Clark Cc: Abhinav Kumar Cc: Dmitry Baryshkov Cc: Sean Paul Cc: Marijn Suijten Cc: Lyude Paul Cc: Danilo Krummrich Cc: Tomi Valkeinen Cc: Thierry Reding Cc: Mikko Perttunen Cc: Gerd Hoffmann Cc: Dmitry Osipenko Cc: Gurchetan Singh Cc: Chia-I Wu Cc: Zack Rusin Cc: Broadcom internal kernel review list Cc: amd-gfx@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Cc: nouveau@lists.freedesktop.org Cc: linux-tegra@vger.kernel.org Cc: virtualization@lists.linux.dev Reviewed-by: Thomas Zimmermann Reviewed-by: Laurent Pinchart Reviewed-by: Dmitry Baryshkov Reviewed-by: Liviu Dudau Acked-by: Alex Deucher Acked-by: Rodrigo Vivi Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250701090722.13645-6-ville.syrjala@linux.intel.com --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 3 +-- drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c | 2 +- drivers/gpu/drm/armada/armada_fb.c | 2 +- drivers/gpu/drm/drm_gem_framebuffer_helper.c | 2 +- drivers/gpu/drm/drm_modeset_helper.c | 6 ++++-- drivers/gpu/drm/exynos/exynos_drm_fb.c | 2 +- drivers/gpu/drm/gma500/framebuffer.c | 2 +- drivers/gpu/drm/i915/display/intel_fb.c | 2 +- drivers/gpu/drm/msm/msm_fb.c | 2 +- drivers/gpu/drm/nouveau/nouveau_display.c | 2 +- drivers/gpu/drm/omapdrm/omap_fb.c | 2 +- drivers/gpu/drm/radeon/radeon_display.c | 2 +- drivers/gpu/drm/tegra/fb.c | 2 +- drivers/gpu/drm/virtio/virtgpu_display.c | 2 +- drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 4 ++-- include/drm/drm_modeset_helper.h | 2 ++ 16 files changed, 21 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 11aa38d8e9ffc..ec30425cd68e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1235,8 +1235,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, int ret; rfb->base.obj[0] = obj; - drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); - + drm_helper_mode_fill_fb_struct(dev, &rfb->base, NULL, mode_cmd); #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED /* Verify that the modifier is supported. */ if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c b/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c index 29b05482f713f..acd8e505ebc71 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_framebuffer.c @@ -178,7 +178,7 @@ komeda_fb_create(struct drm_device *dev, struct drm_file *file, return ERR_PTR(-EINVAL); } - drm_helper_mode_fill_fb_struct(dev, &kfb->base, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, &kfb->base, NULL, mode_cmd); if (kfb->base.modifier) ret = komeda_fb_afbc_size_check(kfb, file, mode_cmd); diff --git a/drivers/gpu/drm/armada/armada_fb.c b/drivers/gpu/drm/armada/armada_fb.c index 597720e229c26..7e94ec5bd4f4e 100644 --- a/drivers/gpu/drm/armada/armada_fb.c +++ b/drivers/gpu/drm/armada/armada_fb.c @@ -64,7 +64,7 @@ struct armada_framebuffer *armada_framebuffer_create(struct drm_device *dev, dfb->mod = config; dfb->fb.obj[0] = &obj->obj; - drm_helper_mode_fill_fb_struct(dev, &dfb->fb, mode); + drm_helper_mode_fill_fb_struct(dev, &dfb->fb, NULL, mode); ret = drm_framebuffer_init(dev, &dfb->fb, &armada_fb_funcs); if (ret) { diff --git a/drivers/gpu/drm/drm_gem_framebuffer_helper.c b/drivers/gpu/drm/drm_gem_framebuffer_helper.c index 982f7abd5eb57..6811ba13533f9 100644 --- a/drivers/gpu/drm/drm_gem_framebuffer_helper.c +++ b/drivers/gpu/drm/drm_gem_framebuffer_helper.c @@ -75,7 +75,7 @@ drm_gem_fb_init(struct drm_device *dev, unsigned int i; int ret; - drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, fb, NULL, mode_cmd); for (i = 0; i < num_planes; i++) fb->obj[i] = obj[i]; diff --git a/drivers/gpu/drm/drm_modeset_helper.c b/drivers/gpu/drm/drm_modeset_helper.c index 3fed2d5ab1d63..89ba999707354 100644 --- a/drivers/gpu/drm/drm_modeset_helper.c +++ b/drivers/gpu/drm/drm_modeset_helper.c @@ -74,6 +74,7 @@ EXPORT_SYMBOL(drm_helper_move_panel_connectors_to_head); * drm_helper_mode_fill_fb_struct - fill out framebuffer metadata * @dev: DRM device * @fb: drm_framebuffer object to fill out + * @info: pixel format information * @mode_cmd: metadata from the userspace fb creation request * * This helper can be used in a drivers fb_create callback to pre-fill the fb's @@ -81,13 +82,14 @@ EXPORT_SYMBOL(drm_helper_move_panel_connectors_to_head); */ void drm_helper_mode_fill_fb_struct(struct drm_device *dev, struct drm_framebuffer *fb, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd) { int i; fb->dev = dev; - fb->format = drm_get_format_info(dev, mode_cmd->pixel_format, - mode_cmd->modifier[0]); + fb->format = info ? : drm_get_format_info(dev, mode_cmd->pixel_format, + mode_cmd->modifier[0]); fb->width = mode_cmd->width; fb->height = mode_cmd->height; for (i = 0; i < 4; i++) { diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c b/drivers/gpu/drm/exynos/exynos_drm_fb.c index 9ae526825726c..7091d31835ec4 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fb.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c @@ -76,7 +76,7 @@ exynos_drm_framebuffer_init(struct drm_device *dev, fb->obj[i] = &exynos_gem[i]->base; } - drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, fb, NULL, mode_cmd); ret = drm_framebuffer_init(dev, fb, &exynos_drm_fb_funcs); if (ret < 0) { diff --git a/drivers/gpu/drm/gma500/framebuffer.c b/drivers/gpu/drm/gma500/framebuffer.c index a4a18ec2dd566..f9ade83613548 100644 --- a/drivers/gpu/drm/gma500/framebuffer.c +++ b/drivers/gpu/drm/gma500/framebuffer.c @@ -47,7 +47,7 @@ static int psb_framebuffer_init(struct drm_device *dev, if (mode_cmd->pitches[0] & 63) return -EINVAL; - drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, fb, NULL, mode_cmd); fb->obj[0] = obj; ret = drm_framebuffer_init(dev, fb, &psb_fb_funcs); if (ret) { diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 96edc791c33bb..1f5f8c2e9d315 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -2254,7 +2254,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, goto err_frontbuffer_put; } - drm_helper_mode_fill_fb_struct(display->drm, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(display->drm, fb, NULL, mode_cmd); for (i = 0; i < fb->format->num_planes; i++) { unsigned int stride_alignment; diff --git a/drivers/gpu/drm/msm/msm_fb.c b/drivers/gpu/drm/msm/msm_fb.c index f151244e8cfb3..a82a657169752 100644 --- a/drivers/gpu/drm/msm/msm_fb.c +++ b/drivers/gpu/drm/msm/msm_fb.c @@ -227,7 +227,7 @@ static struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, msm_fb->base.obj[i] = bos[i]; } - drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, fb, NULL, mode_cmd); ret = drm_framebuffer_init(dev, fb, &msm_framebuffer_funcs); if (ret) { diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 1ddd929015262..e1e5421263103 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -321,7 +321,7 @@ nouveau_framebuffer_new(struct drm_device *dev, if (!(fb = *pfb = kzalloc(sizeof(*fb), GFP_KERNEL))) return -ENOMEM; - drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, fb, NULL, mode_cmd); fb->obj[0] = gem; ret = drm_framebuffer_init(dev, fb, &nouveau_framebuffer_funcs); diff --git a/drivers/gpu/drm/omapdrm/omap_fb.c b/drivers/gpu/drm/omapdrm/omap_fb.c index 36afcd1c1fd74..30c81e2e5d6b3 100644 --- a/drivers/gpu/drm/omapdrm/omap_fb.c +++ b/drivers/gpu/drm/omapdrm/omap_fb.c @@ -440,7 +440,7 @@ struct drm_framebuffer *omap_framebuffer_init(struct drm_device *dev, plane->dma_addr = 0; } - drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, fb, NULL, mode_cmd); ret = drm_framebuffer_init(dev, fb, &omap_framebuffer_funcs); if (ret) { diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index b4aa2bc51bfd5..d66c1a30df951 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -1302,7 +1302,7 @@ radeon_framebuffer_init(struct drm_device *dev, { int ret; fb->obj[0] = obj; - drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, fb, NULL, mode_cmd); ret = drm_framebuffer_init(dev, fb, &radeon_fb_funcs); if (ret) { fb->obj[0] = NULL; diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c index 24907573e758d..d359683f5ce62 100644 --- a/drivers/gpu/drm/tegra/fb.c +++ b/drivers/gpu/drm/tegra/fb.c @@ -114,7 +114,7 @@ struct drm_framebuffer *tegra_fb_alloc(struct drm_device *drm, if (!fb) return ERR_PTR(-ENOMEM); - drm_helper_mode_fill_fb_struct(drm, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(drm, fb, NULL, mode_cmd); for (i = 0; i < fb->format->num_planes; i++) fb->obj[i] = &planes[i]->gem; diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c b/drivers/gpu/drm/virtio/virtgpu_display.c index f9a98fbbabd1a..93763b91bab56 100644 --- a/drivers/gpu/drm/virtio/virtgpu_display.c +++ b/drivers/gpu/drm/virtio/virtgpu_display.c @@ -73,7 +73,7 @@ virtio_gpu_framebuffer_init(struct drm_device *dev, vgfb->base.obj[0] = obj; - drm_helper_mode_fill_fb_struct(dev, &vgfb->base, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, &vgfb->base, NULL, mode_cmd); ret = drm_framebuffer_init(dev, &vgfb->base, &virtio_gpu_fb_funcs); if (ret) { diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c index 2d48a28cda9c0..35965e29e4080 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c @@ -548,7 +548,7 @@ static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv, goto out_err1; } - drm_helper_mode_fill_fb_struct(dev, &vfbs->base.base, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, &vfbs->base.base, NULL, mode_cmd); memcpy(&vfbs->uo, uo, sizeof(vfbs->uo)); vmw_user_object_ref(&vfbs->uo); @@ -634,7 +634,7 @@ static int vmw_kms_new_framebuffer_bo(struct vmw_private *dev_priv, } vfbd->base.base.obj[0] = &bo->tbo.base; - drm_helper_mode_fill_fb_struct(dev, &vfbd->base.base, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, &vfbd->base.base, NULL, mode_cmd); vfbd->base.bo = true; vfbd->buffer = vmw_bo_reference(bo); *out = &vfbd->base; diff --git a/include/drm/drm_modeset_helper.h b/include/drm/drm_modeset_helper.h index 995fd981cab03..7e3d4c5a7f66d 100644 --- a/include/drm/drm_modeset_helper.h +++ b/include/drm/drm_modeset_helper.h @@ -26,6 +26,7 @@ struct drm_crtc; struct drm_crtc_funcs; struct drm_device; +struct drm_format_info; struct drm_framebuffer; struct drm_mode_fb_cmd2; @@ -33,6 +34,7 @@ void drm_helper_move_panel_connectors_to_head(struct drm_device *); void drm_helper_mode_fill_fb_struct(struct drm_device *dev, struct drm_framebuffer *fb, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd); int drm_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, From 23c98df86a81140f0a61a8098118683d08736f06 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 1 Jul 2025 12:07:12 +0300 Subject: [PATCH 2129/2653] drm/amdgpu: Pass along the format info from .fb_create() to drm_helper_mode_fill_fb_struct() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Plumb the format info from .fb_create() all the way to drm_helper_mode_fill_fb_struct() to avoid the redundant lookup. Cc: Alex Deucher Cc: amd-gfx@lists.freedesktop.org Reviewed-by: Thomas Zimmermann Acked-by: Alex Deucher Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250701090722.13645-10-ville.syrjala@linux.intel.com --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index ec30425cd68e7..74554cafe6c72 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1229,13 +1229,14 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev, static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, struct amdgpu_framebuffer *rfb, struct drm_file *file_priv, + const struct drm_format_info *info, const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object *obj) { int ret; rfb->base.obj[0] = obj; - drm_helper_mode_fill_fb_struct(dev, &rfb->base, NULL, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, &rfb->base, info, mode_cmd); #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED /* Verify that the modifier is supported. */ if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, @@ -1382,7 +1383,7 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, } ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv, - mode_cmd, obj); + info, mode_cmd, obj); if (ret) { kfree(amdgpu_fb); #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED From f10fa32d9f1b3e764b2b4bc1903f2b4a2fa06356 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 12 Sep 2025 17:09:43 +0800 Subject: [PATCH 2130/2653] drm/amdkcl: test drm_helper_mode_fill_fb_struct() wants 4 arguments Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 12 ++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../dkms/m4/drm_helper_mode_fill_fb_struct.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 33 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 74554cafe6c72..23673a6add864 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1209,7 +1209,12 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev, { int ret; rfb->base.obj[0] = obj; + +#ifdef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_4_ARGS + drm_helper_mode_fill_fb_struct(dev, &rfb->base, NULL, mode_cmd); +#else drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); +#endif ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); if (ret) @@ -1236,7 +1241,14 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, int ret; rfb->base.obj[0] = obj; + +#ifdef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_4_ARGS drm_helper_mode_fill_fb_struct(dev, &rfb->base, info, mode_cmd); +#else + drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); +#endif + + #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED /* Verify that the modifier is supported. */ if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c37208d8ce9ff..a4cb3b6d1324d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -664,6 +664,9 @@ /* drm_helper_force_disable_all() is available */ #define HAVE_DRM_HELPER_FORCE_DISABLE_ALL 1 +/* drm_helper_mode_fill_fb_struct() wants 4 arguments */ +#define HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_4_ARGS 1 + /* drm_kms_helper_connector_hotplug_event() function is available */ #define HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 new file mode 100644 index 0000000000000..e1e4dc10eb1ed --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.16-rc2-1239-ga34cc7bf1034 +dnl # drm: Allow the caller to pass in the format info to drm_helper_mode_fill_fb_struct() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ],[ + drm_helper_mode_fill_fb_struct(NULL, NULL, NULL, NULL); + ],[drm_helper_mode_fill_fb_struct], [drivers/gpu/drm/drm_modeset_helper.c],[ + AC_DEFINE(HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_4_ARGS, 1, + [drm_helper_mode_fill_fb_struct() wants 4 arguments]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ba5902455b52a..cb563855dbd4c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -296,6 +296,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_BITMAP_READ AC_AMDGPU_VFS_IOCB_ITER_READ AC_AMDGPU_VMF_INSERT_MIXED_MKWRITE_LONG_PFN + AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From e1bbfe2364fe21296753529a91e44044f7b84a13 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 12 Sep 2025 17:32:56 +0800 Subject: [PATCH 2131/2653] drm/amdkcl: test whether fb_create has const struct drm_format_info * parameter Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 8 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm_fb_create_format_info.m4 | 27 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 41 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_fb_create_format_info.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 23673a6add864..5c15ecfa80d7b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1234,7 +1234,9 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev, static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, struct amdgpu_framebuffer *rfb, struct drm_file *file_priv, +#ifdef HAVE_DRM_FB_CREATE_FORMAT_INFO const struct drm_format_info *info, +#endif const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object *obj) { @@ -1357,7 +1359,9 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, struct drm_framebuffer * amdgpu_display_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, +#ifdef HAVE_DRM_FB_CREATE_FORMAT_INFO const struct drm_format_info *info, +#endif const struct drm_mode_fb_cmd2 *mode_cmd) { struct amdgpu_framebuffer *amdgpu_fb; @@ -1395,7 +1399,11 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, } ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv, +#ifdef HAVE_DRM_FB_CREATE_FORMAT_INFO info, mode_cmd, obj); +#else + mode_cmd, obj); +#endif if (ret) { kfree(amdgpu_fb); #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h index 4309b0e0849e9..c999addc3e939 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h @@ -44,7 +44,9 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, struct drm_framebuffer * amdgpu_display_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, +#ifdef HAVE_DRM_FB_CREATE_FORMAT_INFO const struct drm_format_info *info, +#endif const struct drm_mode_fb_cmd2 *mode_cmd); const struct drm_format_info * amdgpu_lookup_format_info(u32 format, uint64_t modifier); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a4cb3b6d1324d..6618d51a496c6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -595,6 +595,9 @@ /* drm_edid_valid() is available */ #define HAVE_DRM_EDID_VALID 1 +/* fb_create has const struct drm_format_info * parameter */ +#define HAVE_DRM_FB_CREATE_FORMAT_INFO 1 + /* drm_fb_helper_fill_info() is available */ #define HAVE_DRM_FB_HELPER_FILL_INFO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_fb_create_format_info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_fb_create_format_info.m4 new file mode 100644 index 0000000000000..25f464b720203 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_fb_create_format_info.m4 @@ -0,0 +1,27 @@ +dnl # +dnl # commit v6.16-rc2-1238-g81112eaac559 +dnl # drm: Pass the format info to .fb_create() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_CREATE_FORMAT_INFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_framebuffer *test_fb_create_new( + struct drm_device *dev, + struct drm_file *file_priv, + const struct drm_format_info *info, + const struct drm_mode_fb_cmd2 *mode_cmd) { + return NULL; + } + + struct drm_mode_config_funcs funcs = { + .fb_create = test_fb_create_new, + }; + ], [ + AC_DEFINE(HAVE_DRM_FB_CREATE_FORMAT_INFO, 1, + [fb_create has const struct drm_format_info * parameter]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cb563855dbd4c..325d7911fb6c3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -297,6 +297,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VFS_IOCB_ITER_READ AC_AMDGPU_VMF_INSERT_MIXED_MKWRITE_LONG_PFN AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT + AC_AMDGPU_DRM_FB_CREATE_FORMAT_INFO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 2e12bbcf38e326a415dd36e2cd329ee975b30804 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 12 Sep 2025 18:43:18 +0800 Subject: [PATCH 2132/2653] drm/amdkcl: get_format_info uses pixel_format and modifier parameters Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 7 ++++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.h | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../dkms/m4/drm_get_format_info_signature.m4 | 24 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 39 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_get_format_info_signature.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index a3f062c72d49d..9f8fe4f41245b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -95,10 +95,17 @@ enum dm_micro_swizzle { }; #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED +#ifdef HAVE_DRM_GET_FORMAT_INFO_TWO_ARGS const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier) { return amdgpu_lookup_format_info(pixel_format, modifier); } +#else +const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd) +{ + return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]); +} +#endif #endif void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h index ea2619b507db7..3b583bbca535a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h @@ -58,7 +58,11 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, unsigned long possible_crtcs, const struct dc_plane_cap *plane_cap); +#ifdef HAVE_DRM_GET_FORMAT_INFO_TWO_ARGS const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier); +#else +const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd); +#endif void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, bool *per_pixel_alpha, bool *pre_multiplied_alpha, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6618d51a496c6..ce8d0f56eca0a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -652,6 +652,9 @@ /* drm_gem_prime_handle_to_fd() is available */ #define HAVE_DRM_GEM_PRIME_HANDLE_TO_FD 1 +/* get_format_info uses pixel_format and modifier parameters */ +#define HAVE_DRM_GET_FORMAT_INFO_TWO_ARGS 1 + /* drm_get_panel_min_brightness_quirk() is available */ #define HAVE_DRM_GET_PANEL_MIN_BRIGHTNESS_QUIRK 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_get_format_info_signature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_get_format_info_signature.m4 new file mode 100644 index 0000000000000..71d0f4e7eb9d4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_get_format_info_signature.m4 @@ -0,0 +1,24 @@ +dnl # +dnl # v6.16-rc2-1235-g0389e4256eb2 +dnl # drm: Pass pixel_format+modifier to .get_format_info() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GET_FORMAT_INFO_2_ARGS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + const struct drm_format_info *test_get_format_info_new( + u32 pixel_format, u64 modifier) { + return NULL; + } + + struct drm_mode_config_funcs funcs = { + .get_format_info = test_get_format_info_new, + }; + ], [ + AC_DEFINE(HAVE_DRM_GET_FORMAT_INFO_TWO_ARGS, 1, + [get_format_info uses pixel_format and modifier parameters]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 325d7911fb6c3..ebabc406a863e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -298,6 +298,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMF_INSERT_MIXED_MKWRITE_LONG_PFN AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_FB_CREATE_FORMAT_INFO + AC_AMDGPU_DRM_GET_FORMAT_INFO_2_ARGS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 4b3f3229f9ed9a6ad58bf50a5a408c6ef91534e9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Wed, 24 Sep 2025 13:38:34 +0200 Subject: [PATCH 2133/2653] drm/amd/display: Reject modes with too high pixel clock on DCE6-10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reject modes with a pixel clock higher than the maximum display clock. Use 400 MHz as a fallback value when the maximum display clock is not known. Pixel clocks that are higher than the display clock just won't work and are not supported. With the addition of the YUV422 fallback, DC can now accidentally select a mode requiring higher pixel clock than actually supported when the DP version supports the required bandwidth but the clock is otherwise too high for the display engine. DCE 6-10 don't support these modes but they don't have a bandwidth calculation to reject them properly. Fixes: 5d53fdc0971f ("drm/amd/display: Add fallback path for YCBCR422") Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Mario Limonciello --- Change-Id: Ie003cc591fd11d29e1121bcda116d3f9f0c752df --- .../drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 3 +++ .../drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 5 +++++ .../amd/display/dc/resource/dce100/dce100_resource.c | 10 +++++++++- .../drm/amd/display/dc/resource/dce60/dce60_resource.c | 10 +++++++++- .../drm/amd/display/dc/resource/dce80/dce80_resource.c | 10 +++++++++- 5 files changed, 35 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index dbd6ef1b60a0b..6131ede2db7a2 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -463,6 +463,9 @@ void dce_clk_mgr_construct( clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; + base->clks.max_supported_dispclk_khz = + clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz; + dce_clock_read_integrated_info(clk_mgr); dce_clock_read_ss_info(clk_mgr); } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c index a39641a0ff09e..69dd80d9f7388 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c @@ -147,6 +147,8 @@ void dce60_clk_mgr_construct( struct dc_context *ctx, struct clk_mgr_internal *clk_mgr) { + struct clk_mgr *base = &clk_mgr->base; + dce_clk_mgr_construct(ctx, clk_mgr); memcpy(clk_mgr->max_clks_by_state, @@ -157,5 +159,8 @@ void dce60_clk_mgr_construct( clk_mgr->clk_mgr_shift = &disp_clk_shift; clk_mgr->clk_mgr_mask = &disp_clk_mask; clk_mgr->base.funcs = &dce60_funcs; + + base->clks.max_supported_dispclk_khz = + clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz; } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index 3a51be63f0208..f36ec4edf0aec 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -29,6 +29,7 @@ #include "stream_encoder.h" #include "resource.h" +#include "clk_mgr.h" #include "include/irq_service_interface.h" #include "virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" @@ -843,10 +844,17 @@ static enum dc_status dce100_validate_bandwidth( { int i; bool at_least_one_pipe = false; + struct dc_stream_state *stream = NULL; + const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000); for (i = 0; i < dc->res_pool->pipe_count; i++) { - if (context->res_ctx.pipe_ctx[i].stream) + stream = context->res_ctx.pipe_ctx[i].stream; + if (stream) { at_least_one_pipe = true; + + if (stream->timing.pix_clk_100hz >= max_pix_clk_khz * 10) + return DC_FAIL_BANDWIDTH_VALIDATE; + } } if (at_least_one_pipe) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c index c164d2500c2a4..b5433349fc7a6 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c @@ -34,6 +34,7 @@ #include "stream_encoder.h" #include "resource.h" +#include "clk_mgr.h" #include "include/irq_service_interface.h" #include "irq/dce60/irq_service_dce60.h" #include "dce110/dce110_timing_generator.h" @@ -870,10 +871,17 @@ static enum dc_status dce60_validate_bandwidth( { int i; bool at_least_one_pipe = false; + struct dc_stream_state *stream = NULL; + const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000); for (i = 0; i < dc->res_pool->pipe_count; i++) { - if (context->res_ctx.pipe_ctx[i].stream) + stream = context->res_ctx.pipe_ctx[i].stream; + if (stream) { at_least_one_pipe = true; + + if (stream->timing.pix_clk_100hz >= max_pix_clk_khz * 10) + return DC_FAIL_BANDWIDTH_VALIDATE; + } } if (at_least_one_pipe) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c index 3e8b0ac11d906..538eafea82d5f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c @@ -32,6 +32,7 @@ #include "stream_encoder.h" #include "resource.h" +#include "clk_mgr.h" #include "include/irq_service_interface.h" #include "irq/dce80/irq_service_dce80.h" #include "dce110/dce110_timing_generator.h" @@ -876,10 +877,17 @@ static enum dc_status dce80_validate_bandwidth( { int i; bool at_least_one_pipe = false; + struct dc_stream_state *stream = NULL; + const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000); for (i = 0; i < dc->res_pool->pipe_count; i++) { - if (context->res_ctx.pipe_ctx[i].stream) + stream = context->res_ctx.pipe_ctx[i].stream; + if (stream) { at_least_one_pipe = true; + + if (stream->timing.pix_clk_100hz >= max_pix_clk_khz * 10) + return DC_FAIL_BANDWIDTH_VALIDATE; + } } if (at_least_one_pipe) { From 3f67d9312c8718364c38fe27daeafd53543d1986 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 24 Sep 2025 23:19:14 +0800 Subject: [PATCH 2134/2653] amd/amdkfd: enhance kfd process check in switch partition current switch partition only check if kfd_processes_table is empty. kfd_prcesses_table entry is deleted in kfd_process_notifier_release, but kfd_process tear down is in kfd_process_wq_release. consider two processes: Process A (workqueue) -> kfd_process_wq_release -> Access kfd_node member Process B switch partition -> amdgpu_xcp_pre_partition_switch -> amdgpu_amdkfd_device_fini_sw -> kfd_node tear down. Process A and B may trigger a race as shown in dmesg log. This patch is to resolve the race by adding an atomic kfd_process counter kfd_processes_count, it increment as create kfd process, decrement as finish kfd_process_wq_release. v2: Put kfd_processes_count per kfd_dev, move decrement to kfd_process_destroy_pdds and bug fix. (Philip Yang) [3966658.307702] divide error: 0000 [#1] SMP NOPTI [3966658.350818] i10nm_edac [3966658.356318] CPU: 124 PID: 38435 Comm: kworker/124:0 Kdump: loaded Tainted [3966658.356890] Workqueue: kfd_process_wq kfd_process_wq_release [amdgpu] [3966658.362839] nfit [3966658.366457] RIP: 0010:kfd_get_num_sdma_engines+0x17/0x40 [amdgpu] [3966658.366460] Code: 00 00 e9 ac 81 02 00 66 66 2e 0f 1f 84 00 00 00 00 00 90 0f 1f 44 00 00 48 8b 4f 08 48 8b b7 00 01 00 00 8b 81 58 26 03 00 99 be b8 01 00 00 80 b9 70 2e 00 00 00 74 0b 83 f8 02 ba 02 00 00 [3966658.380967] x86_pkg_temp_thermal [3966658.391529] RSP: 0018:ffffc900a0edfdd8 EFLAGS: 00010246 [3966658.391531] RAX: 0000000000000008 RBX: ffff8974e593b800 RCX: ffff888645900000 [3966658.391531] RDX: 0000000000000000 RSI: ffff888129154400 RDI: ffff888129151c00 [3966658.391532] RBP: ffff8883ad79d400 R08: 0000000000000000 R09: ffff8890d2750af4 [3966658.391532] R10: 0000000000000018 R11: 0000000000000018 R12: 0000000000000000 [3966658.391533] R13: ffff8883ad79d400 R14: ffffe87ff662ba00 R15: ffff8974e593b800 [3966658.391533] FS: 0000000000000000(0000) GS:ffff88fe7f600000(0000) knlGS:0000000000000000 [3966658.391534] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [3966658.391534] CR2: 0000000000d71000 CR3: 000000dd0e970004 CR4: 0000000002770ee0 [3966658.391535] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [3966658.391535] DR3: 0000000000000000 DR6: 00000000fffe07f0 DR7: 0000000000000400 [3966658.391536] PKRU: 55555554 [3966658.391536] Call Trace: [3966658.391674] deallocate_sdma_queue+0x38/0xa0 [amdgpu] [3966658.391762] process_termination_cpsch+0x1ed/0x480 [amdgpu] [3966658.399754] intel_powerclamp [3966658.402831] kfd_process_dequeue_from_all_devices+0x5b/0xc0 [amdgpu] [3966658.402908] kfd_process_wq_release+0x1a/0x1a0 [amdgpu] [3966658.410516] coretemp [3966658.434016] process_one_work+0x1ad/0x380 [3966658.434021] worker_thread+0x49/0x310 [3966658.438963] kvm_intel [3966658.446041] ? process_one_work+0x380/0x380 [3966658.446045] kthread+0x118/0x140 [3966658.446047] ? __kthread_bind_mask+0x60/0x60 [3966658.446050] ret_from_fork+0x1f/0x30 [3966658.446053] Modules linked in: kpatch_20765354(OEK) [3966658.455310] kvm [3966658.464534] mptcp_diag xsk_diag raw_diag unix_diag af_packet_diag netlink_diag udp_diag act_pedit act_mirred act_vlan cls_flower kpatch_21951273(OEK) kpatch_18424469(OEK) kpatch_19749756(OEK) [3966658.473462] idxd_mdev [3966658.482306] kpatch_17971294(OEK) sch_ingress xt_conntrack amdgpu(OE) amdxcp(OE) amddrm_buddy(OE) amd_sched(OE) amdttm(OE) amdkcl(OE) intel_ifs iptable_mangle tcm_loop target_core_pscsi tcp_diag target_core_file inet_diag target_core_iblock target_core_user target_core_mod coldpgs kpatch_18383292(OEK) ip6table_nat ip6table_filter ip6_tables ip_set_hash_ipportip ip_set_hash_ipportnet ip_set_hash_ipport ip_set_bitmap_port xt_comment iptable_nat nf_nat iptable_filter ip_tables ip_set ip_vs_sh ip_vs_wrr ip_vs_rr ip_vs nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 sn_core_odd(OE) i40e overlay binfmt_misc tun bonding(OE) aisqos(OE) aisqos_hotfixes(OE) rfkill uio_pci_generic uio cuse fuse nf_tables nfnetlink intel_rapl_msr intel_rapl_common intel_uncore_frequency intel_uncore_frequency_common i10nm_edac nfit x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel kvm idxd_mdev [3966658.491237] vfio_pci [3966658.501196] vfio_pci vfio_virqfd mdev vfio_iommu_type1 vfio iax_crypto intel_pmt_telemetry iTCO_wdt intel_pmt_class iTCO_vendor_support irqbypass crct10dif_pclmul crc32_pclmul ghash_clmulni_intel rapl intel_cstate snd_hda_intel snd_intel_dspcfg snd_hda_codec snd_hda_core snd_hwdep snd_seq [3966658.508537] vfio_virqfd [3966658.517569] snd_seq_device ipmi_ssif isst_if_mbox_pci isst_if_mmio pcspkr snd_pcm idxd intel_uncore ses isst_if_common intel_vsec idxd_bus enclosure snd_timer mei_me snd i2c_i801 i2c_smbus mei i2c_ismt soundcore joydev acpi_ipmi ipmi_si ipmi_devintf ipmi_msghandler acpi_power_meter acpi_pad vfat fat [3966658.526851] mdev [3966658.536096] nfsd auth_rpcgss nfs_acl lockd grace slb_vtoa(OE) sunrpc dm_mod hookers mlx5_ib(OE) ast i2c_algo_bit drm_vram_helper drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops drm_ttm_helper ttm mlx5_core(OE) mlxfw(OE) [3966658.540381] vfio_iommu_type1 [3966658.544341] nvme mpt3sas tls drm nvme_core pci_hyperv_intf raid_class psample libcrc32c crc32c_intel mlxdevm(OE) i2c_core [3966658.551254] vfio [3966658.558742] scsi_transport_sas wmi pinctrl_emmitsburg sd_mod t10_pi sg ahci libahci libata rdma_ucm(OE) ib_uverbs(OE) rdma_cm(OE) iw_cm(OE) ib_cm(OE) ib_umad(OE) ib_core(OE) ib_ucm(OE) mlx_compat(OE) [3966658.563004] iax_crypto [3966658.570988] [last unloaded: diagnose] [3966658.571027] ---[ end trace cc9dbb180f9ae537 ]--- Signed-off-by: Yifan Zhang Reviewed-by: Philip.Yang --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 10 ++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 ++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 ++++ 3 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index d1803abbd5f6d..784c28fbaddab 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -496,6 +496,7 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) mutex_init(&kfd->doorbell_mutex); ida_init(&kfd->doorbell_ida); + atomic_set(&kfd->kfd_processes_count, 0); return kfd; } @@ -1515,6 +1516,15 @@ int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd) mutex_lock(&kfd_processes_mutex); + /* kfd_processes_count is per kfd_dev, return -EBUSY without + * further check + */ + if (!!atomic_read(&kfd->kfd_processes_count)) { + pr_debug("process_wq_release not finished\n"); + r = -EBUSY; + goto out; + } + if (hash_empty(kfd_processes_table) && !kfd_is_locked(kfd)) goto out; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 6189d62d48625..cfcf8f30b2341 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -442,6 +442,8 @@ struct kfd_dev { /* for dynamic partitioning */ int kfd_dev_lock; + atomic_t kfd_processes_count; + /* Lock for profiler process */ struct mutex profiler_lock; /* Process currently holding the lock */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 6700dbec94316..c61e61acfb044 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1092,6 +1092,8 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) pdd->runtime_inuse = false; } + atomic_dec(&pdd->dev->kfd->kfd_processes_count); + kfree(pdd); p->pdds[i] = NULL; } @@ -1711,6 +1713,8 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, /* Init idr used for memory handle translation */ idr_init(&pdd->alloc_idr); + atomic_inc(&dev->kfd->kfd_processes_count); + return pdd; } From 7176c411a3c9335e61fbc908de8b5d63d05886b0 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Wed, 24 Sep 2025 16:00:06 +0800 Subject: [PATCH 2135/2653] drm/amdgpu: Fix fence signaling race condition in userqueue MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit fixes a potential race condition in the userqueue fence signaling mechanism by replacing dma_fence_is_signaled_locked() with dma_fence_is_signaled(). The issue occurred because: 1. dma_fence_is_signaled_locked() should only be used when holding the fence's individual lock, not just the fence list lock 2. Using the locked variant without the proper fence lock could lead to double-signaling scenarios: - Hardware completion signals the fence - Software path also tries to signal the same fence By using dma_fence_is_signaled() instead, we properly handle the locking hierarchy and avoid the race condition while still maintaining the necessary synchronization through the fence_list_lock. v2: drop the comment (Christian) Reviewed-by: Christian König Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index 90d79cfe21146..c7a22997ed72c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -348,7 +348,7 @@ static int amdgpu_userq_fence_create(struct amdgpu_usermode_queue *userq, /* Check if hardware has already processed the job */ spin_lock_irqsave(&fence_drv->fence_list_lock, flags); - if (!dma_fence_is_signaled_locked(fence)) + if (!dma_fence_is_signaled(fence)) list_add_tail(&userq_fence->link, &fence_drv->fences); else dma_fence_put(fence); From 91acd42eb2b9c1a0c719fc240be67d4e46ed33e5 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Wed, 3 Sep 2025 20:03:52 -0400 Subject: [PATCH 2136/2653] amdgpu/amdkfd: peerdirect support address lookup Add look-up for the BO by address. This is required for memory allocations where the virtual address are reserved outside of KFD and then later mapped to GPU memory. Signed-off-by: David Yat Sin Reviewed-by: Felix Kuehling ' --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 16 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 + drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 67 ++++++++++++++------- 3 files changed, 64 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index d58b15803e372..bd7e5059865c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2752,6 +2752,22 @@ int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) vma->vm_ops = &amdgpu_ttm_vm_ops; return 0; } + +/* This function should be called with mm lock held */ +bool amdgpu_vma_is_amdgpu_bo(struct vm_area_struct *vma) +{ + if (vma->vm_ops == &amdgpu_ttm_vm_ops) + return true; + + return false; +} +#else +bool amdgpu_vma_is_amdgpu_bo(struct vm_area_struct *vma) +{ + pr_err_once("bo from address verification not supported\n"); + + return false; +} #endif /* HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 5d6affae526fc..dd8b15e0fc9e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -175,6 +175,9 @@ int amdgpu_ttm_init(struct amdgpu_device *adev); void amdgpu_ttm_fini(struct amdgpu_device *adev); void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable); + +bool amdgpu_vma_is_amdgpu_bo(struct vm_area_struct *vma); + int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, uint64_t dst_offset, uint32_t byte_count, struct dma_resv *resv, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index 09461f004377e..f7cd9661d5047 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -171,8 +171,12 @@ static int amd_acquire(unsigned long addr, size_t size, char *peer_mem_name, void **client_context) { struct kfd_process *p; - struct kfd_bo *buf_obj; struct amd_mem_context *mem_context; + struct kfd_bo *buf_obj = NULL; + struct kfd_node *dev = NULL; + struct amdgpu_bo *bo = NULL; + unsigned long offset = 0; + uint32_t flags = 0; if (peer_mem_name == rdma_name) { p = peer_mem_private_data; @@ -187,34 +191,54 @@ static int amd_acquire(unsigned long addr, size_t size, align_addr_size(&addr, &size); mutex_lock(&p->mutex); - buf_obj = kfd_process_find_bo_from_interval(p, addr, - addr + size - 1); - if (!buf_obj) { - pr_debug("Cannot find a kfd_bo for the range\n"); - goto out_unlock; - } + buf_obj = kfd_process_find_bo_from_interval(p, addr, addr + size - 1); + if (buf_obj) { + offset = addr - buf_obj->it.start; + bo = amdgpu_amdkfd_gpuvm_get_bo_ref(buf_obj->mem, &flags); - /* Initialize context used for operation with given address */ - mem_context = kzalloc(sizeof(*mem_context), GFP_KERNEL); - if (!mem_context) - goto out_unlock; + dev = buf_obj->dev; + } else { + struct vm_area_struct *vma; + struct amdgpu_device *adev; + + mmap_read_lock(p->mm); + vma = find_vma(p->mm, addr); + + if (!vma || + !amdgpu_vma_is_amdgpu_bo(vma) || + vma->vm_start > addr || + vma->vm_end < addr + size) { + mmap_read_unlock(p->mm); + goto out_unlock; + } - mem_context->pid = p->lead_thread->pid; + bo = ttm_to_amdgpu_bo(vma->vm_private_data); + drm_gem_object_get(&bo->tbo.base); + mmap_read_unlock(p->mm); - pr_debug("addr: %#lx, size: %#lx, pid: %d\n", - addr, size, mem_context->pid); + offset = addr - vma->vm_start; - mem_context->va = addr; - mem_context->size = size; - mem_context->offset = addr - buf_obj->it.start; + flags = bo->kfd_bo->alloc_flags; + adev = amdgpu_ttm_adev(bo->tbo.bdev); + dev = adev->kfd.dev->nodes[bo->xcp_id]; + } - mem_context->bo = amdgpu_amdkfd_gpuvm_get_bo_ref(buf_obj->mem, - &mem_context->flags); - mem_context->dev = buf_obj->dev; + mem_context = kzalloc(sizeof(*mem_context), GFP_KERNEL); + if (unlikely(!mem_context)) { + drm_gem_object_put(&bo->tbo.base); + goto out_unlock; + } mutex_unlock(&p->mutex); + pr_debug("addr: %#lx, size: %#lx, pid: %d\n", addr, size, mem_context->pid); - pr_debug("Client context: 0x%p\n", mem_context); + mem_context->pid = p->lead_thread->pid; + mem_context->va = addr; + mem_context->size = size; + mem_context->dev = dev; + mem_context->offset = offset; + mem_context->bo = bo; + mem_context->flags = flags; /* Return pointer to allocated context */ *client_context = mem_context; @@ -223,7 +247,6 @@ static int amd_acquire(unsigned long addr, size_t size, * by AMD GPU driver */ return 1; - out_unlock: mutex_unlock(&p->mutex); return 0; From 68586d289daede09cdbb9b2fa815e572b2cea614 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Wed, 24 Sep 2025 13:38:35 +0200 Subject: [PATCH 2137/2653] drm/amd/display: Share dce100_validate_bandwidth with DCE6-8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DCE6-8 have very similar capabilities to DCE10, they support the same DP and HDMI versions and work similarly. Share dce100_validate_bandwidth between DCE6-10 to reduce code duplication in the DC driver. Signed-off-by: Timur Kristóf Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- Change-Id: Ie502053bef29f474d8dc1c8f18cd6e66cc308e15 --- .../dc/resource/dce100/dce100_resource.c | 13 +++++- .../dc/resource/dce100/dce100_resource.h | 5 +++ .../dc/resource/dce60/dce60_resource.c | 43 +------------------ .../dc/resource/dce80/dce80_resource.c | 34 +-------------- 4 files changed, 18 insertions(+), 77 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index f36ec4edf0aec..6421a56ffd23c 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -837,7 +837,7 @@ static enum dc_status build_mapped_resource( return DC_OK; } -static enum dc_status dce100_validate_bandwidth( +enum dc_status dce100_validate_bandwidth( struct dc *dc, struct dc_state *context, enum dc_validate_mode validate_mode) @@ -862,7 +862,16 @@ static enum dc_status dce100_validate_bandwidth( context->bw_ctx.bw.dce.dispclk_khz = 681000; context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; } else { - context->bw_ctx.bw.dce.dispclk_khz = 0; + /* On DCE 6.0 and 6.4 the PLL0 is both the display engine clock and + * the DP clock, and shouldn't be turned off. Just select the display + * clock value from its low power mode. + */ + if (dc->ctx->dce_version == DCE_VERSION_6_0 || + dc->ctx->dce_version == DCE_VERSION_6_4) + context->bw_ctx.bw.dce.dispclk_khz = 352000; + else + context->bw_ctx.bw.dce.dispclk_khz = 0; + context->bw_ctx.bw.dce.yclk_khz = 0; } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h index fecab7c560f5b..08e045601a770 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h @@ -41,6 +41,11 @@ struct resource_pool *dce100_create_resource_pool( enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps); +enum dc_status dce100_validate_bandwidth( + struct dc *dc, + struct dc_state *context, + enum dc_validate_mode validate_mode); + enum dc_status dce100_add_stream_to_ctx( struct dc *dc, struct dc_state *new_ctx, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c index b5433349fc7a6..61ad3703461e9 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c @@ -864,47 +864,6 @@ static void dce60_resource_destruct(struct dce110_resource_pool *pool) } } -static enum dc_status dce60_validate_bandwidth( - struct dc *dc, - struct dc_state *context, - enum dc_validate_mode validate_mode) -{ - int i; - bool at_least_one_pipe = false; - struct dc_stream_state *stream = NULL; - const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000); - - for (i = 0; i < dc->res_pool->pipe_count; i++) { - stream = context->res_ctx.pipe_ctx[i].stream; - if (stream) { - at_least_one_pipe = true; - - if (stream->timing.pix_clk_100hz >= max_pix_clk_khz * 10) - return DC_FAIL_BANDWIDTH_VALIDATE; - } - } - - if (at_least_one_pipe) { - /* TODO implement when needed but for now hardcode max value*/ - context->bw_ctx.bw.dce.dispclk_khz = 681000; - context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; - } else { - /* On DCE 6.0 and 6.4 the PLL0 is both the display engine clock and - * the DP clock, and shouldn't be turned off. Just select the display - * clock value from its low power mode. - */ - if (dc->ctx->dce_version == DCE_VERSION_6_0 || - dc->ctx->dce_version == DCE_VERSION_6_4) - context->bw_ctx.bw.dce.dispclk_khz = 352000; - else - context->bw_ctx.bw.dce.dispclk_khz = 0; - - context->bw_ctx.bw.dce.yclk_khz = 0; - } - - return DC_OK; -} - static bool dce60_validate_surface_sets( struct dc_state *context) { @@ -948,7 +907,7 @@ static const struct resource_funcs dce60_res_pool_funcs = { .destroy = dce60_destroy_resource_pool, .link_enc_create = dce60_link_encoder_create, .panel_cntl_create = dce60_panel_cntl_create, - .validate_bandwidth = dce60_validate_bandwidth, + .validate_bandwidth = dce100_validate_bandwidth, .validate_plane = dce100_validate_plane, .add_stream_to_ctx = dce100_add_stream_to_ctx, .validate_global = dce60_validate_global, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c index 538eafea82d5f..0c9a39bf7ff4f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c @@ -870,38 +870,6 @@ static void dce80_resource_destruct(struct dce110_resource_pool *pool) } } -static enum dc_status dce80_validate_bandwidth( - struct dc *dc, - struct dc_state *context, - enum dc_validate_mode validate_mode) -{ - int i; - bool at_least_one_pipe = false; - struct dc_stream_state *stream = NULL; - const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000); - - for (i = 0; i < dc->res_pool->pipe_count; i++) { - stream = context->res_ctx.pipe_ctx[i].stream; - if (stream) { - at_least_one_pipe = true; - - if (stream->timing.pix_clk_100hz >= max_pix_clk_khz * 10) - return DC_FAIL_BANDWIDTH_VALIDATE; - } - } - - if (at_least_one_pipe) { - /* TODO implement when needed but for now hardcode max value*/ - context->bw_ctx.bw.dce.dispclk_khz = 681000; - context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; - } else { - context->bw_ctx.bw.dce.dispclk_khz = 0; - context->bw_ctx.bw.dce.yclk_khz = 0; - } - - return DC_OK; -} - static bool dce80_validate_surface_sets( struct dc_state *context) { @@ -945,7 +913,7 @@ static const struct resource_funcs dce80_res_pool_funcs = { .destroy = dce80_destroy_resource_pool, .link_enc_create = dce80_link_encoder_create, .panel_cntl_create = dce80_panel_cntl_create, - .validate_bandwidth = dce80_validate_bandwidth, + .validate_bandwidth = dce100_validate_bandwidth, .validate_plane = dce100_validate_plane, .add_stream_to_ctx = dce100_add_stream_to_ctx, .validate_global = dce80_validate_global, From 577fd7944ffb568a5e96a7c5c38777993b3b4958 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Wed, 24 Sep 2025 13:38:36 +0200 Subject: [PATCH 2138/2653] drm/amd/display: Share dce100_validate_global with DCE6-8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The dce100_validate_global function was verbatim exactly the same as dce60_validate_global and dce80_validate_global. Share dce100_validate_global between DCE6-10 to save code size. Signed-off-by: Timur Kristóf Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- Change-Id: I3202969eae000a30ff20577c7b7cde0ac08d6f0b --- .../dc/resource/dce100/dce100_resource.c | 2 +- .../dc/resource/dce100/dce100_resource.h | 4 +++ .../dc/resource/dce60/dce60_resource.c | 32 +------------------ .../dc/resource/dce80/dce80_resource.c | 32 +------------------ 4 files changed, 7 insertions(+), 63 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index 6421a56ffd23c..c4b4dc3ad8c9d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -898,7 +898,7 @@ static bool dce100_validate_surface_sets( return true; } -static enum dc_status dce100_validate_global( +enum dc_status dce100_validate_global( struct dc *dc, struct dc_state *context) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h index 08e045601a770..dd150a4b46105 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.h @@ -41,6 +41,10 @@ struct resource_pool *dce100_create_resource_pool( enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps); +enum dc_status dce100_validate_global( + struct dc *dc, + struct dc_state *context); + enum dc_status dce100_validate_bandwidth( struct dc *dc, struct dc_state *context, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c index 61ad3703461e9..53c67ebe779ff 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c @@ -864,36 +864,6 @@ static void dce60_resource_destruct(struct dce110_resource_pool *pool) } } -static bool dce60_validate_surface_sets( - struct dc_state *context) -{ - int i; - - for (i = 0; i < context->stream_count; i++) { - if (context->stream_status[i].plane_count == 0) - continue; - - if (context->stream_status[i].plane_count > 1) - return false; - - if (context->stream_status[i].plane_states[0]->format - >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) - return false; - } - - return true; -} - -static enum dc_status dce60_validate_global( - struct dc *dc, - struct dc_state *context) -{ - if (!dce60_validate_surface_sets(context)) - return DC_FAIL_SURFACE_VALIDATE; - - return DC_OK; -} - static void dce60_destroy_resource_pool(struct resource_pool **pool) { struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); @@ -910,7 +880,7 @@ static const struct resource_funcs dce60_res_pool_funcs = { .validate_bandwidth = dce100_validate_bandwidth, .validate_plane = dce100_validate_plane, .add_stream_to_ctx = dce100_add_stream_to_ctx, - .validate_global = dce60_validate_global, + .validate_global = dce100_validate_global, .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link }; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c index 0c9a39bf7ff4f..5b77697452022 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c @@ -870,36 +870,6 @@ static void dce80_resource_destruct(struct dce110_resource_pool *pool) } } -static bool dce80_validate_surface_sets( - struct dc_state *context) -{ - int i; - - for (i = 0; i < context->stream_count; i++) { - if (context->stream_status[i].plane_count == 0) - continue; - - if (context->stream_status[i].plane_count > 1) - return false; - - if (context->stream_status[i].plane_states[0]->format - >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) - return false; - } - - return true; -} - -static enum dc_status dce80_validate_global( - struct dc *dc, - struct dc_state *context) -{ - if (!dce80_validate_surface_sets(context)) - return DC_FAIL_SURFACE_VALIDATE; - - return DC_OK; -} - static void dce80_destroy_resource_pool(struct resource_pool **pool) { struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); @@ -916,7 +886,7 @@ static const struct resource_funcs dce80_res_pool_funcs = { .validate_bandwidth = dce100_validate_bandwidth, .validate_plane = dce100_validate_plane, .add_stream_to_ctx = dce100_add_stream_to_ctx, - .validate_global = dce80_validate_global, + .validate_global = dce100_validate_global, .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link }; From 34d9f8a0ba95b3b28ff5265ff5e5878d7a545c5c Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Wed, 24 Sep 2025 11:16:22 -0500 Subject: [PATCH 2139/2653] drm/amd: Use dynamic array size declaration for amdgpu_connector_add_common_modes() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [Why] Adding or removing a mode from common_modes[] can be fragile if a user forgot to update the for loop boundaries. [How] Use ARRAY_SIZE() to detect size of the array and use that instead. Cc: Timur Kristóf Reviewed-by: Alex Deucher Reviewed-by: Timur Kristóf Link: https://lore.kernel.org/r/20250924161624.1975819-4-mario.limonciello@amd.com Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 051025d6e3c67..54a449010524f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -439,10 +439,11 @@ static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, struct drm_display_mode *mode = NULL; struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; int i; + int n; static const struct mode_size { int w; int h; - } common_modes[17] = { + } common_modes[] = { { 640, 480}, { 720, 480}, { 800, 600}, @@ -462,7 +463,9 @@ static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, {1920, 1200} }; - for (i = 0; i < 17; i++) { + n = ARRAY_SIZE(common_modes); + + for (i = 0; i < n; i++) { if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { if (common_modes[i].w > 1024 || common_modes[i].h > 768) From 9e60936b82d7baa9fef316d11e65aa5cbc1017c2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 15 Nov 2024 08:56:33 -0500 Subject: [PATCH 2140/2653] drm/amdgpu: update MODULE_PARM_DESC for freesync_video MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To better describe what it does. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3756 Reviewed-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 9a6ff1464c75e..e3ef935a64f77 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -980,7 +980,7 @@ module_param_named(tmz, amdgpu_tmz, int, 0444); */ MODULE_PARM_DESC( freesync_video, - "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); + "Adds additional modes via VRR for refresh changes without a full modeset (0 = off (default), 1 = on)"); module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); /** From 1b9c4cc4f2e95355ffdc71c83170f9de7c556bea Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Wed, 24 Sep 2025 11:16:23 -0500 Subject: [PATCH 2141/2653] drm/amd: Drop some common modes from amdgpu_connector_add_common_modes() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [Why] DC and non-DC codepaths have different sets of common modes that are added for eDP and LVDS cases. This can cause different behaviors for turning on DC on hardware that can support both. [How] Drop extra modes from amdgpu_connector_add_common_modes() not present in amdgpu_dm_connector_add_common_modes(). Cc: Timur Kristóf Reviewed-by: Timur Kristóf Reviewed-by: Alex Deucher Link: https://lore.kernel.org/r/20250924161624.1975819-5-mario.limonciello@amd.com Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 54a449010524f..b65c3f42f3144 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -445,18 +445,12 @@ static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, int h; } common_modes[] = { { 640, 480}, - { 720, 480}, { 800, 600}, - { 848, 480}, {1024, 768}, - {1152, 768}, {1280, 720}, {1280, 800}, - {1280, 854}, - {1280, 960}, {1280, 1024}, {1440, 900}, - {1400, 1050}, {1680, 1050}, {1600, 1200}, {1920, 1080}, From 867505b7241963c39c0c0c42fb23de12bbde173e Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Wed, 24 Sep 2025 11:16:24 -0500 Subject: [PATCH 2142/2653] drm/amd: Add name to modes from amdgpu_connector_add_common_modes() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [Why] When DC adds common modes it adds modes with a string to match what they are. Non-DC doesn't. This can be inconsistent when turning on/off DC support. [How] Add a name member to common_modes[] and copy it into the drm display mode. Cc: Timur Kristóf Reviewed-by: Alex Deucher Reviewed-by: Timur Kristóf Link: https://lore.kernel.org/r/20250924161624.1975819-6-mario.limonciello@amd.com Signed-off-by: Mario Limonciello --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 26 ++++++++++--------- 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index b65c3f42f3144..fbce16fdd3411 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -440,21 +440,22 @@ static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; int i; int n; - static const struct mode_size { + struct mode_size { + char name[DRM_DISPLAY_MODE_LEN]; int w; int h; } common_modes[] = { - { 640, 480}, - { 800, 600}, - {1024, 768}, - {1280, 720}, - {1280, 800}, - {1280, 1024}, - {1440, 900}, - {1680, 1050}, - {1600, 1200}, - {1920, 1080}, - {1920, 1200} + { "640x480", 640, 480}, + { "800x600", 800, 600}, + { "1024x768", 1024, 768}, + { "1280x720", 1280, 720}, + { "1280x800", 1280, 800}, + {"1280x1024", 1280, 1024}, + { "1440x900", 1440, 900}, + {"1680x1050", 1680, 1050}, + {"1600x1200", 1600, 1200}, + {"1920x1080", 1920, 1080}, + {"1920x1200", 1920, 1200} }; n = ARRAY_SIZE(common_modes); @@ -476,6 +477,7 @@ static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); if (!mode) return; + strscpy(mode->name, common_modes[i].name, DRM_DISPLAY_MODE_LEN); drm_mode_probed_add(connector, mode); } From 83371f40473b230a6db81de15d34e85874878150 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 25 Sep 2025 20:45:21 +0200 Subject: [PATCH 2143/2653] drm/amdgpu: Add additional DCE6 SCL registers Fixes: 102b2f587ac8 ("drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init (v2)") Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h | 7 +++++++ drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h index 9de01ae574c03..067eddd9c62d8 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h @@ -4115,6 +4115,7 @@ #define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1B55 #define mmSCL0_SCL_COEF_RAM_SELECT 0x1B40 #define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1B41 +#define mmSCL0_SCL_SCALER_ENABLE 0x1B42 #define mmSCL0_SCL_CONTROL 0x1B44 #define mmSCL0_SCL_DEBUG 0x1B6A #define mmSCL0_SCL_DEBUG2 0x1B69 @@ -4144,6 +4145,7 @@ #define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1E55 #define mmSCL1_SCL_COEF_RAM_SELECT 0x1E40 #define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1E41 +#define mmSCL1_SCL_SCALER_ENABLE 0x1E42 #define mmSCL1_SCL_CONTROL 0x1E44 #define mmSCL1_SCL_DEBUG 0x1E6A #define mmSCL1_SCL_DEBUG2 0x1E69 @@ -4173,6 +4175,7 @@ #define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 #define mmSCL2_SCL_COEF_RAM_SELECT 0x4140 #define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141 +#define mmSCL2_SCL_SCALER_ENABLE 0x4142 #define mmSCL2_SCL_CONTROL 0x4144 #define mmSCL2_SCL_DEBUG 0x416A #define mmSCL2_SCL_DEBUG2 0x4169 @@ -4202,6 +4205,7 @@ #define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455 #define mmSCL3_SCL_COEF_RAM_SELECT 0x4440 #define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441 +#define mmSCL3_SCL_SCALER_ENABLE 0x4442 #define mmSCL3_SCL_CONTROL 0x4444 #define mmSCL3_SCL_DEBUG 0x446A #define mmSCL3_SCL_DEBUG2 0x4469 @@ -4231,6 +4235,7 @@ #define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755 #define mmSCL4_SCL_COEF_RAM_SELECT 0x4740 #define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741 +#define mmSCL4_SCL_SCALER_ENABLE 0x4742 #define mmSCL4_SCL_CONTROL 0x4744 #define mmSCL4_SCL_DEBUG 0x476A #define mmSCL4_SCL_DEBUG2 0x4769 @@ -4260,6 +4265,7 @@ #define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4A55 #define mmSCL5_SCL_COEF_RAM_SELECT 0x4A40 #define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4A41 +#define mmSCL5_SCL_SCALER_ENABLE 0x4A42 #define mmSCL5_SCL_CONTROL 0x4A44 #define mmSCL5_SCL_DEBUG 0x4A6A #define mmSCL5_SCL_DEBUG2 0x4A69 @@ -4287,6 +4293,7 @@ #define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1B55 #define mmSCL_COEF_RAM_SELECT 0x1B40 #define mmSCL_COEF_RAM_TAP_DATA 0x1B41 +#define mmSCL_SCALER_ENABLE 0x1B42 #define mmSCL_CONTROL 0x1B44 #define mmSCL_DEBUG 0x1B6A #define mmSCL_DEBUG2 0x1B69 diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h index 2d6a598a6c25c..9317a7afa6211 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h @@ -8650,6 +8650,8 @@ #define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x00000000 #define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L #define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x00000000 +#define SCL_SCALER_ENABLE__SCL_SCALE_EN_MASK 0x00000001L +#define SCL_SCALER_ENABLE__SCL_SCALE_EN__SHIFT 0x00000000 #define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L #define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x00000000 #define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L From bb27424caf1c3614aeeda481f7ac7d7824758811 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 25 Sep 2025 20:45:22 +0200 Subject: [PATCH 2144/2653] drm/amd/display: Add missing DCE6 SCL_HORZ_FILTER_INIT* SRIs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Without these, it's impossible to program these registers. Fixes: 102b2f587ac8 ("drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init (v2)") Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h index cbce194ec7b82..ff746fba850bc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h @@ -155,6 +155,8 @@ SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \ SRI(VIEWPORT_START, SCL, id), \ SRI(VIEWPORT_SIZE, SCL, id), \ + SRI(SCL_HORZ_FILTER_INIT_RGB_LUMA, SCL, id), \ + SRI(SCL_HORZ_FILTER_INIT_CHROMA, SCL, id), \ SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \ SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \ SRI(SCL_VERT_FILTER_INIT, SCL, id), \ From 5967712ac4cb02297e6e8d084cb8cc8dce897e37 Mon Sep 17 00:00:00 2001 From: Heng Zhou Date: Fri, 26 Sep 2025 11:07:44 +0800 Subject: [PATCH 2145/2653] drm/amdgpu: Fix for GPU reset being blocked by KIQ I/O. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is some probability that reset workqueue is blocked by KIQ I/O for 10+ seconds after gpu hangs. So we need to add a in_reset check during each KIQ register poll. Signed-off-by: Heng Zhou Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 89fc1015d3a68..7f02e36ccc1ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -1102,6 +1102,9 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_ might_sleep(); while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { + if (amdgpu_in_reset(adev)) + goto failed_kiq_read; + msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); } @@ -1171,6 +1174,8 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint3 might_sleep(); while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { + if (amdgpu_in_reset(adev)) + goto failed_kiq_write; msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); From c16f25e7a77776acbbddcf6e5d736db65bbd02c5 Mon Sep 17 00:00:00 2001 From: Shaoyun Liu Date: Wed, 24 Sep 2025 21:40:57 -0400 Subject: [PATCH 2146/2653] drm/amd/amdgpu: Fix the mes version that support inv_tlbs MES version 0x83 is not stable to use the inv_tlbs API. Defer it to 0x84 vertsion. Signed-off-by: Shaoyun Liu Reviewed-by: Michael Chen --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 404cc8c2ff2c1..f4a19357ccbc6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -337,7 +337,7 @@ static void gmc_v12_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, int vmid, i; if (adev->enable_uni_mes && adev->mes.ring[AMDGPU_MES_SCHED_PIPE].sched.ready && - (adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x83) { + (adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x84) { struct mes_inv_tlbs_pasid_input input = {0}; input.pasid = pasid; input.flush_type = flush_type; From a1e6510e586b0ae0ba687dbb687e3f73a01b5b30 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Wed, 24 Sep 2025 12:23:26 +0530 Subject: [PATCH 2147/2653] drm/amdgpu: use user provided hmm_range buffer in amdgpu_ttm_tt_get_user_pages MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit update the amdgpu_ttm_tt_get_user_pages and all dependent function along with it callers to use a user allocated hmm_range buffer instead hmm layer allocates the buffer. This is a need to get hmm_range pointers easily accessible without accessing the bo and that is a requirement for the userqueue to lock the userptrs effectively. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 16 ++++++++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 +++++- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 12 +++++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 11 +---------- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 7 +++++-- 8 files changed, 40 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 66c44cc4fffdc..c8150377b03f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1153,8 +1153,15 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, } #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - ret = amdgpu_ttm_tt_get_user_pages(bo, &range); + range = kzalloc(sizeof(*range), GFP_KERNEL); + if (unlikely(!range)) { + ret = -ENOMEM; + goto unregister_out; + } + + ret = amdgpu_ttm_tt_get_user_pages(bo, range); if (ret) { + kfree(range); if (ret == -EAGAIN) pr_debug("Failed to get user pages, try again\n"); else @@ -2944,9 +2951,14 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, } #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED + mem->range = kzalloc(sizeof(*mem->range), GFP_KERNEL); + if (unlikely(!mem->range)) + return -ENOMEM; /* Get updated user pages */ - ret = amdgpu_ttm_tt_get_user_pages(bo, &mem->range); + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->range); if (ret) { + kfree(mem->range); + mem->range = NULL; pr_debug("Failed %d to get user pages\n", ret); /* Return -EFAULT bad address error as success. It will diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index a097d4a50a05c..5551befba7913 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -909,9 +909,13 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { bool userpage_invalidated = false; struct amdgpu_bo *bo = e->bo; + e->range = kzalloc(sizeof(*e->range), GFP_KERNEL); + if (unlikely(!e->range)) + return -ENOMEM; + int i; - r = amdgpu_ttm_tt_get_user_pages(bo, &e->range); + r = amdgpu_ttm_tt_get_user_pages(bo, e->range); if (r) goto out_free_user_pages; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index f6c79cb9aa3d7..0ea9ab4c0b26c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -644,14 +644,20 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - r = amdgpu_ttm_tt_get_user_pages(bo, &range); + range = kzalloc(sizeof(*range), GFP_KERNEL); + if (unlikely(!range)) + return -ENOMEM; + r = amdgpu_ttm_tt_get_user_pages(bo, range); #else r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &range); #endif - if (r) + if (r) { +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED + kfree(range); +#endif goto release_object; - + } r = amdgpu_bo_reserve(bo, true); if (r) goto user_pages_done; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index f13a169a26dbb..14e62c2be1149 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -843,18 +843,13 @@ const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, void *owner, - struct hmm_range **phmm_range) + struct hmm_range *hmm_range) { - struct hmm_range *hmm_range; unsigned long end; unsigned long timeout; unsigned long *pfns; int r = 0; - hmm_range = kzalloc(sizeof(*hmm_range), GFP_KERNEL); - if (unlikely(!hmm_range)) - return -ENOMEM; - pfns = kvmalloc_array(npages, sizeof(*pfns), GFP_KERNEL); if (unlikely(!pfns)) { r = -ENOMEM; @@ -914,15 +909,11 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, hmm_range->start = start; hmm_range->hmm_pfns = pfns; - *phmm_range = hmm_range; - return 0; out_free_pfns: kvfree(pfns); out_free_range: - kfree(hmm_range); - if (r == -EBUSY) r = -EAGAIN; return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index bce7baa1adcb2..e078aa4905e38 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -86,7 +86,7 @@ static inline struct page *hmm_pfn_to_page(unsigned long hmm_pfn) int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, void *owner, - struct hmm_range **phmm_range); + struct hmm_range *hmm_range); bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range); #if defined(CONFIG_HMM_MIRROR) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index bd7e5059865c0..a7d108f64e15f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -779,10 +779,11 @@ struct amdgpu_ttm_tt { * memory and start HMM tracking CPU page table update * * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only - * once afterwards to stop HMM tracking + * once afterwards to stop HMM tracking. Its the caller responsibility to ensure + * that range is a valid memory and it is freed too. */ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, - struct hmm_range **range) + struct hmm_range *range) { struct ttm_tt *ttm = bo->tbo.ttm; struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); @@ -792,9 +793,6 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, bool readonly; int r = 0; - /* Make sure get_user_pages_done() can cleanup gracefully */ - *range = NULL; - mm = bo->notifier.mm; if (unlikely(!mm)) { DRM_DEBUG_DRIVER("BO is not registered?\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index dd8b15e0fc9e8..60cf8588a6b81 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -209,7 +209,7 @@ uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, - struct hmm_range **range); + struct hmm_range *range); #else int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, struct hmm_range **range); @@ -221,7 +221,7 @@ bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, #else #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, - struct hmm_range **range) + struct hmm_range *range) { return -EPERM; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index cd8f2e5b7410b..e6968e211d3fd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1741,12 +1741,15 @@ static int svm_range_validate_and_map(struct mm_struct *mm, } WRITE_ONCE(p->svms.faulting_task, current); + hmm_range = kzalloc(sizeof(*hmm_range), GFP_KERNEL); r = amdgpu_hmm_range_get_pages(&prange->notifier, addr, npages, readonly, owner, - &hmm_range); + hmm_range); WRITE_ONCE(p->svms.faulting_task, NULL); - if (r) + if (r) { + kfree(hmm_range); pr_debug("failed %d to get svm range pages\n", r); + } } else { r = -EFAULT; } From 77faa9dc58e235b994adaff853b0299f1d58659f Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Wed, 24 Sep 2025 18:03:07 +0530 Subject: [PATCH 2148/2653] drm/amdgpu: remove the redeclaration of variable i MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Variable "i" has been redeclared as integer later in the function which is wrong and not serving any purpose. Also add an extra line between variable initialisation and code. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 5551befba7913..a484f9212c573 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -909,12 +909,11 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { bool userpage_invalidated = false; struct amdgpu_bo *bo = e->bo; + e->range = kzalloc(sizeof(*e->range), GFP_KERNEL); if (unlikely(!e->range)) return -ENOMEM; - int i; - r = amdgpu_ttm_tt_get_user_pages(bo, e->range); if (r) goto out_free_user_pages; From 67474b8696ad0f80d17ad27c453c54bcb917f902 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Tue, 27 May 2025 11:09:53 -0400 Subject: [PATCH 2149/2653] drm/amdkfd: Fix kfd process ref leaking when userptr unmapping kfd_lookup_process_by_pid hold the kfd process reference to ensure it doesn't get destroyed while sending the segfault event to user space. Calling kfd_lookup_process_by_pid as function parameter leaks the kfd process refcount and miss the NULL pointer check if app process is already destroyed. Fixes: 7a566d7f56f4 ("amd/amdkfd: Trigger segfault for early userptr unmmapping") Signed-off-by: Philip Yang Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index c8150377b03f6..44d5a9e6d5ad5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2975,12 +2975,17 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, * from the KFD, trigger a segmentation fault in VM debug mode. */ if (amdgpu_ttm_adev(bo->tbo.bdev)->debug_vm_userptr) { + struct kfd_process *p; + pr_err("Pid %d unmapped memory before destroying userptr at GPU addr 0x%llx\n", pid_nr(process_info->pid), mem->va); // Send GPU VM fault to user space - kfd_signal_vm_fault_event_with_userptr(kfd_lookup_process_by_pid(process_info->pid), - mem->va); + p = kfd_lookup_process_by_pid(process_info->pid); + if (p) { + kfd_signal_vm_fault_event_with_userptr(p, mem->va); + kfd_unref_process(p); + } } ret = 0; From 6c23ddbe45a617367271c5943e820f1f644d5ba8 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Mon, 15 Sep 2025 15:57:32 -0400 Subject: [PATCH 2150/2653] drm/amdkfd: Fix mmap write lock not release If mmap write lock is taken while draining retry fault, mmap write lock is not released because svm_range_restore_pages calls mmap_read_unlock then returns. This causes deadlock and system hangs later because mmap read or write lock cannot be taken. Downgrade mmap write lock to read lock if draining retry fault fix this bug. Signed-off-by: Philip Yang Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index e6968e211d3fd..5492b0e74260f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -3052,6 +3052,8 @@ svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid, if (svms->checkpoint_ts[gpuidx] != 0) { if (amdgpu_ih_ts_after_or_equal(ts, svms->checkpoint_ts[gpuidx])) { pr_debug("draining retry fault, drop fault 0x%llx\n", addr); + if (write_locked) + mmap_write_downgrade(mm); r = -EAGAIN; goto out_unlock_svms; } else { From 673192f3e2e28bdcc62cbb120c6fcd3a1d5aec86 Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Thu, 11 Sep 2025 15:37:32 -0400 Subject: [PATCH 2151/2653] drm/amd/display: DML2.1 Reintegration [Summary of changes] - Updated structs - Renaming of variables for clarity Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Roman Li Tested-by: Dan Wheeler --- .../dml21/inc/dml_top_display_cfg_types.h | 11 + .../dml21/inc/dml_top_soc_parameter_types.h | 7 +- .../display/dc/dml2/dml21/inc/dml_top_types.h | 13 + .../src/dml2_core/dml2_core_dcn4_calcs.c | 55 ++- .../dml21/src/dml2_core/dml2_core_factory.c | 2 + .../src/dml2_core/dml2_core_shared_types.h | 10 +- .../dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 459 +++++++++--------- .../src/inc/dml2_internal_shared_types.h | 36 +- 8 files changed, 336 insertions(+), 257 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h index e8dc6471c0bec..13749c9fcf18b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h @@ -49,6 +49,11 @@ enum dml2_source_format_class { dml2_422_packed_12 = 18 }; +enum dml2_sample_positioning { + dml2_interstitial = 0, + dml2_cosited = 1 +}; + enum dml2_rotation_angle { dml2_rotation_0 = 0, dml2_rotation_90 = 1, @@ -222,7 +227,11 @@ struct dml2_composition_cfg { struct { bool enabled; + bool easf_enabled; + bool isharp_enabled; bool upsp_enabled; + enum dml2_sample_positioning upsp_sample_positioning; + unsigned int upsp_vtaps; struct { double h_ratio; double v_ratio; @@ -385,6 +394,7 @@ struct dml2_plane_parameters { // The actual reserved vblank time used for the corresponding stream in mode_programming would be at least as much as this per-plane override. long reserved_vblank_time_ns; unsigned int max_vactive_det_fill_delay_us; // 0 = no reserved time, +ve = explicit max delay + unsigned int vactive_latency_to_hide_for_pstate_admissibility_us; unsigned int gpuvm_min_page_size_kbytes; unsigned int hostvm_min_page_size_kbytes; @@ -456,6 +466,7 @@ struct dml2_display_cfg { bool enable; bool value; } force_nom_det_size_kbytes; + bool mode_support_check_disable; bool mcache_admissibility_check_disable; bool surface_viewport_size_check_disable; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h index 176f559476644..4a9a0d5a09b76 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h @@ -145,6 +145,8 @@ struct dml2_soc_bb { struct dml2_soc_vmin_clock_limits vmin_limit; double lower_bound_bandwidth_dchub; + double fraction_of_urgent_bandwidth_nominal_target; + double fraction_of_urgent_bandwidth_flip_target; unsigned int dprefclk_mhz; unsigned int xtalclk_mhz; unsigned int pcie_refclk_mhz; @@ -170,6 +172,7 @@ struct dml2_soc_bb { struct dml2_ip_capabilities { unsigned int pipe_count; unsigned int otg_count; + unsigned int TDLUT_33cube_count; unsigned int num_dsc; unsigned int max_num_dp2p0_streams; unsigned int max_num_hdmi_frl_outputs; @@ -188,7 +191,9 @@ struct dml2_ip_capabilities { unsigned int subvp_prefetch_end_to_mall_start_us; unsigned int subvp_fw_processing_delay; unsigned int max_vactive_det_fill_delay_us; - + unsigned int ppt_max_allow_delay_ns; + unsigned int temp_read_max_allow_delay_us; + unsigned int dummy_pstate_max_allow_delay_us; /* FAMS2 delays */ struct { unsigned int max_allow_delay_us; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h index 41adb1104d0fd..8646ce5f1c01f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h @@ -70,6 +70,8 @@ struct dml2_pmo_options { bool disable_dyn_odm; bool disable_dyn_odm_for_multi_stream; bool disable_dyn_odm_for_stream_with_svp; + struct dml2_pmo_pstate_strategy *override_strategy_lists[DML2_MAX_PLANES]; + unsigned int num_override_strategies_per_list[DML2_MAX_PLANES]; }; struct dml2_options { @@ -193,6 +195,14 @@ struct dml2_mcache_surface_allocation { } informative; }; +enum dml2_pstate_type { + dml2_pstate_type_uclk, + dml2_pstate_type_ppt, + dml2_pstate_type_temp_read, + dml2_pstate_type_dummy_pstate, + dml2_pstate_type_count +}; + enum dml2_pstate_method { dml2_pstate_method_na = 0, /* hw exclusive modes */ @@ -310,6 +320,7 @@ struct dml2_mode_support_info { bool NumberOfOTGSupport; bool NumberOfHDMIFRLSupport; bool NumberOfDP2p0Support; + bool NumberOfTDLUT33cubeSupport; bool WritebackScaleRatioAndTapsSupport; bool CursorSupport; bool PitchSupport; @@ -357,6 +368,8 @@ struct dml2_mode_support_info { unsigned int AlignedCPitch[DML2_MAX_PLANES]; bool g6_temp_read_support; bool temp_read_or_ppt_support; + bool qos_bandwidth_support; + bool dcfclk_support; }; // dml2_mode_support_info struct dml2_display_cfg_programming { diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index bf62d42b3f78b..4ccdb179b001d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -12756,7 +12756,7 @@ void dml2_core_calcs_get_stream_fams2_programming(const struct dml2_core_interna { const struct dml2_plane_parameters *plane_descriptor = &display_cfg->display_config.plane_descriptors[plane_index]; const struct dml2_stream_parameters *stream_descriptor = &display_cfg->display_config.stream_descriptors[plane_descriptor->stream_index]; - const struct dml2_fams2_meta *stream_fams2_meta = &display_cfg->stage3.stream_fams2_meta[plane_descriptor->stream_index]; + const struct dml2_pstate_meta *stream_pstate_meta = &display_cfg->stage3.stream_pstate_meta[plane_descriptor->stream_index]; struct dmub_fams2_cmd_stream_static_base_state *base_programming = &fams2_base_programming->stream_v1.base; union dmub_fams2_cmd_stream_static_sub_state *sub_programming = &fams2_sub_programming->stream_v1.sub_state; @@ -12771,24 +12771,24 @@ void dml2_core_calcs_get_stream_fams2_programming(const struct dml2_core_interna /* from display configuration */ base_programming->htotal = (uint16_t)stream_descriptor->timing.h_total; base_programming->vtotal = (uint16_t)stream_descriptor->timing.v_total; - base_programming->vblank_start = (uint16_t)(stream_fams2_meta->nom_vtotal - + base_programming->vblank_start = (uint16_t)(stream_pstate_meta->nom_vtotal - stream_descriptor->timing.v_front_porch); - base_programming->vblank_end = (uint16_t)(stream_fams2_meta->nom_vtotal - + base_programming->vblank_end = (uint16_t)(stream_pstate_meta->nom_vtotal - stream_descriptor->timing.v_front_porch - stream_descriptor->timing.v_active); base_programming->config.bits.is_drr = stream_descriptor->timing.drr_config.enabled; /* from meta */ base_programming->otg_vline_time_ns = - (unsigned int)(stream_fams2_meta->otg_vline_time_us * 1000.0); - base_programming->scheduling_delay_otg_vlines = (uint8_t)stream_fams2_meta->scheduling_delay_otg_vlines; - base_programming->contention_delay_otg_vlines = (uint8_t)stream_fams2_meta->contention_delay_otg_vlines; - base_programming->vline_int_ack_delay_otg_vlines = (uint8_t)stream_fams2_meta->vertical_interrupt_ack_delay_otg_vlines; - base_programming->drr_keepout_otg_vline = (uint16_t)(stream_fams2_meta->nom_vtotal - + (unsigned int)(stream_pstate_meta->otg_vline_time_us * 1000.0); + base_programming->scheduling_delay_otg_vlines = (uint8_t)stream_pstate_meta->scheduling_delay_otg_vlines; + base_programming->contention_delay_otg_vlines = (uint8_t)stream_pstate_meta->contention_delay_otg_vlines; + base_programming->vline_int_ack_delay_otg_vlines = (uint8_t)stream_pstate_meta->vertical_interrupt_ack_delay_otg_vlines; + base_programming->drr_keepout_otg_vline = (uint16_t)(stream_pstate_meta->nom_vtotal - stream_descriptor->timing.v_front_porch - - stream_fams2_meta->method_drr.programming_delay_otg_vlines); - base_programming->allow_to_target_delay_otg_vlines = (uint8_t)stream_fams2_meta->allow_to_target_delay_otg_vlines; - base_programming->max_vtotal = (uint16_t)stream_fams2_meta->max_vtotal; + stream_pstate_meta->method_drr.programming_delay_otg_vlines); + base_programming->allow_to_target_delay_otg_vlines = (uint8_t)stream_pstate_meta->allow_to_target_delay_otg_vlines; + base_programming->max_vtotal = (uint16_t)stream_pstate_meta->max_vtotal; /* from core */ base_programming->config.bits.min_ttu_vblank_usable = true; @@ -12807,11 +12807,11 @@ void dml2_core_calcs_get_stream_fams2_programming(const struct dml2_core_interna /* legacy vactive */ base_programming->type = FAMS2_STREAM_TYPE_VACTIVE; sub_programming->legacy.vactive_det_fill_delay_otg_vlines = - (uint8_t)stream_fams2_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines; + (uint8_t)stream_pstate_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines; base_programming->allow_start_otg_vline = - (uint16_t)stream_fams2_meta->method_vactive.common.allow_start_otg_vline; + (uint16_t)stream_pstate_meta->method_vactive.common.allow_start_otg_vline; base_programming->allow_end_otg_vline = - (uint16_t)stream_fams2_meta->method_vactive.common.allow_end_otg_vline; + (uint16_t)stream_pstate_meta->method_vactive.common.allow_end_otg_vline; base_programming->config.bits.clamp_vtotal_min = true; break; case dml2_pstate_method_vblank: @@ -12819,22 +12819,22 @@ void dml2_core_calcs_get_stream_fams2_programming(const struct dml2_core_interna /* legacy vblank */ base_programming->type = FAMS2_STREAM_TYPE_VBLANK; base_programming->allow_start_otg_vline = - (uint16_t)stream_fams2_meta->method_vblank.common.allow_start_otg_vline; + (uint16_t)stream_pstate_meta->method_vblank.common.allow_start_otg_vline; base_programming->allow_end_otg_vline = - (uint16_t)stream_fams2_meta->method_vblank.common.allow_end_otg_vline; + (uint16_t)stream_pstate_meta->method_vblank.common.allow_end_otg_vline; base_programming->config.bits.clamp_vtotal_min = true; break; case dml2_pstate_method_fw_drr: /* drr */ base_programming->type = FAMS2_STREAM_TYPE_DRR; sub_programming->drr.programming_delay_otg_vlines = - (uint8_t)stream_fams2_meta->method_drr.programming_delay_otg_vlines; + (uint8_t)stream_pstate_meta->method_drr.programming_delay_otg_vlines; sub_programming->drr.nom_stretched_vtotal = - (uint16_t)stream_fams2_meta->method_drr.stretched_vtotal; + (uint16_t)stream_pstate_meta->method_drr.stretched_vtotal; base_programming->allow_start_otg_vline = - (uint16_t)stream_fams2_meta->method_drr.common.allow_start_otg_vline; + (uint16_t)stream_pstate_meta->method_drr.common.allow_start_otg_vline; base_programming->allow_end_otg_vline = - (uint16_t)stream_fams2_meta->method_drr.common.allow_end_otg_vline; + (uint16_t)stream_pstate_meta->method_drr.common.allow_end_otg_vline; /* drr only clamps to vtotal min for single display */ base_programming->config.bits.clamp_vtotal_min = display_cfg->display_config.num_streams == 1; sub_programming->drr.only_stretch_if_required = true; @@ -12847,13 +12847,13 @@ void dml2_core_calcs_get_stream_fams2_programming(const struct dml2_core_interna (uint16_t)(plane_descriptor->composition.scaler_info.plane0.v_ratio * 1000.0); sub_programming->subvp.vratio_denominator = 1000; sub_programming->subvp.programming_delay_otg_vlines = - (uint8_t)stream_fams2_meta->method_subvp.programming_delay_otg_vlines; + (uint8_t)stream_pstate_meta->method_subvp.programming_delay_otg_vlines; sub_programming->subvp.prefetch_to_mall_otg_vlines = - (uint8_t)stream_fams2_meta->method_subvp.prefetch_to_mall_delay_otg_vlines; + (uint8_t)stream_pstate_meta->method_subvp.prefetch_to_mall_delay_otg_vlines; sub_programming->subvp.phantom_vtotal = - (uint16_t)stream_fams2_meta->method_subvp.phantom_vtotal; + (uint16_t)stream_pstate_meta->method_subvp.phantom_vtotal; sub_programming->subvp.phantom_vactive = - (uint16_t)stream_fams2_meta->method_subvp.phantom_vactive; + (uint16_t)stream_pstate_meta->method_subvp.phantom_vactive; sub_programming->subvp.config.bits.is_multi_planar = plane_descriptor->surface.plane1.height > 0; sub_programming->subvp.config.bits.is_yuv420 = @@ -12862,9 +12862,9 @@ void dml2_core_calcs_get_stream_fams2_programming(const struct dml2_core_interna plane_descriptor->pixel_format == dml2_420_12; base_programming->allow_start_otg_vline = - (uint16_t)stream_fams2_meta->method_subvp.common.allow_start_otg_vline; + (uint16_t)stream_pstate_meta->method_subvp.common.allow_start_otg_vline; base_programming->allow_end_otg_vline = - (uint16_t)stream_fams2_meta->method_subvp.common.allow_end_otg_vline; + (uint16_t)stream_pstate_meta->method_subvp.common.allow_end_otg_vline; base_programming->config.bits.clamp_vtotal_min = true; break; case dml2_pstate_method_reserved_hw: @@ -13027,7 +13027,10 @@ void dml2_core_calcs_get_informative(const struct dml2_core_internal_display_mod out->informative.mode_support_info.VRatioInPrefetchSupported = mode_lib->ms.support.VRatioInPrefetchSupported; out->informative.mode_support_info.DISPCLK_DPPCLK_Support = mode_lib->ms.support.DISPCLK_DPPCLK_Support; out->informative.mode_support_info.TotalAvailablePipesSupport = mode_lib->ms.support.TotalAvailablePipesSupport; + out->informative.mode_support_info.NumberOfTDLUT33cubeSupport = mode_lib->ms.support.NumberOfTDLUT33cubeSupport; out->informative.mode_support_info.ViewportSizeSupport = mode_lib->ms.support.ViewportSizeSupport; + out->informative.mode_support_info.qos_bandwidth_support = mode_lib->ms.support.qos_bandwidth_support; + out->informative.mode_support_info.dcfclk_support = mode_lib->ms.support.dcfclk_support; for (k = 0; k < out->display_config.num_planes; k++) { diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c index 640087e862f84..cc4f0663c6d67 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c @@ -15,6 +15,8 @@ bool dml2_core_create(enum dml2_project_id project_id, struct dml2_core_instance memset(out, 0, sizeof(struct dml2_core_instance)); + out->project_id = project_id; + switch (project_id) { case dml2_project_dcn4x_stage1: result = false; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h index ffb8c09f37a5c..ff1c47347610a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h @@ -37,6 +37,7 @@ struct dml2_core_ip_params { unsigned int writeback_interface_buffer_size_kbytes; unsigned int max_num_dpp; unsigned int max_num_otg; + unsigned int TDLUT_33cube_count; unsigned int max_num_wb; unsigned int max_dchub_pscl_bw_pix_per_clk; unsigned int max_pscl_lb_bw_pix_per_clk; @@ -46,6 +47,7 @@ struct dml2_core_ip_params { double max_vscl_ratio; unsigned int max_hscl_taps; unsigned int max_vscl_taps; + unsigned int odm_combine_support_mask; unsigned int num_dsc; unsigned int maximum_dsc_bits_per_component; unsigned int maximum_pixels_per_line_per_dsc_unit; @@ -82,7 +84,6 @@ struct dml2_core_ip_params { unsigned int subvp_swath_height_margin_lines; unsigned int subvp_fw_processing_delay_us; unsigned int subvp_pstate_allow_width_us; - // MRQ bool dcn_mrq_present; unsigned int zero_size_buffer_entries; @@ -103,6 +104,8 @@ struct dml2_core_internal_DmlPipe { unsigned int DPPPerSurface; bool ScalerEnabled; bool UPSPEnabled; + unsigned int UPSPVTaps; + enum dml2_sample_positioning UPSPSamplePositioning; enum dml2_rotation_angle RotationAngle; bool mirrored; unsigned int ViewportHeight; @@ -230,6 +233,7 @@ struct dml2_core_internal_mode_support_info { bool MSOOrODMSplitWithNonDPLink; bool NotEnoughLanesForMSO; bool NumberOfOTGSupport; + bool NumberOfTDLUT33cubeSupport; bool NumberOfHDMIFRLSupport; bool NumberOfDP2p0Support; bool WritebackScaleRatioAndTapsSupport; @@ -1306,7 +1310,7 @@ struct dml2_core_calcs_CalculateVMRowAndSwath_params { unsigned int HostVMMinPageSize; unsigned int DCCMetaBufferSizeBytes; bool mrq_present; - enum dml2_pstate_method pstate_switch_modes[DML2_MAX_PLANES]; + enum dml2_pstate_method *pstate_switch_modes; // Output bool *PTEBufferSizeNotExceeded; @@ -2308,6 +2312,7 @@ struct dml2_core_calcs_mode_support_ex { const struct dml2_display_cfg *in_display_cfg; const struct dml2_mcg_min_clock_table *min_clk_table; int min_clk_index; + enum dml2_project_id project_id; //unsigned int in_state_index; struct dml2_core_internal_mode_support_info *out_evaluation_info; }; @@ -2320,6 +2325,7 @@ struct dml2_core_calcs_mode_programming_ex { const struct dml2_mcg_min_clock_table *min_clk_table; const struct core_display_cfg_support_info *cfg_support_info; int min_clk_index; + enum dml2_project_id project_id; struct dml2_display_cfg_programming *programming; }; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c index d88b3e0082dd4..5769c2638f9ad 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c @@ -642,6 +642,11 @@ bool pmo_dcn4_fams2_initialize(struct dml2_pmo_initialize_in_out *in_out) int i = 0; struct dml2_pmo_instance *pmo = in_out->instance; + unsigned int base_list_size = 0; + const struct dml2_pmo_pstate_strategy *base_list = NULL; + unsigned int *expanded_list_size = NULL; + struct dml2_pmo_pstate_strategy *expanded_list = NULL; + pmo->soc_bb = in_out->soc_bb; pmo->ip_caps = in_out->ip_caps; pmo->mpc_combine_limit = 2; @@ -656,53 +661,71 @@ bool pmo_dcn4_fams2_initialize(struct dml2_pmo_initialize_in_out *in_out) pmo->options = in_out->options; /* generate permutations of p-state configs from base strategy list */ - for (i = 1; i <= PMO_DCN4_MAX_DISPLAYS; i++) { - switch (i) { + for (i = 0; i < PMO_DCN4_MAX_DISPLAYS; i++) { + switch (i+1) { case 1: - DML_ASSERT(base_strategy_list_1_display_size <= PMO_DCN4_MAX_BASE_STRATEGIES); - - /* populate list */ - pmo_dcn4_fams2_expand_base_pstate_strategies( - base_strategy_list_1_display, - base_strategy_list_1_display_size, - i, - pmo->init_data.pmo_dcn4.expanded_strategy_list_1_display, - &pmo->init_data.pmo_dcn4.num_expanded_strategies_per_list[i - 1]); + if (pmo->options->override_strategy_lists[i] && pmo->options->num_override_strategies_per_list[i]) { + base_list = pmo->options->override_strategy_lists[i]; + base_list_size = pmo->options->num_override_strategies_per_list[i]; + } else { + base_list = base_strategy_list_1_display; + base_list_size = base_strategy_list_1_display_size; + } + + expanded_list_size = &pmo->init_data.pmo_dcn4.num_expanded_strategies_per_list[i]; + expanded_list = pmo->init_data.pmo_dcn4.expanded_strategy_list_1_display; + break; case 2: - DML_ASSERT(base_strategy_list_2_display_size <= PMO_DCN4_MAX_BASE_STRATEGIES); - - /* populate list */ - pmo_dcn4_fams2_expand_base_pstate_strategies( - base_strategy_list_2_display, - base_strategy_list_2_display_size, - i, - pmo->init_data.pmo_dcn4.expanded_strategy_list_2_display, - &pmo->init_data.pmo_dcn4.num_expanded_strategies_per_list[i - 1]); + if (pmo->options->override_strategy_lists[i] && pmo->options->num_override_strategies_per_list[i]) { + base_list = pmo->options->override_strategy_lists[i]; + base_list_size = pmo->options->num_override_strategies_per_list[i]; + } else { + base_list = base_strategy_list_2_display; + base_list_size = base_strategy_list_2_display_size; + } + + expanded_list_size = &pmo->init_data.pmo_dcn4.num_expanded_strategies_per_list[i]; + expanded_list = pmo->init_data.pmo_dcn4.expanded_strategy_list_2_display; + break; case 3: - DML_ASSERT(base_strategy_list_3_display_size <= PMO_DCN4_MAX_BASE_STRATEGIES); - - /* populate list */ - pmo_dcn4_fams2_expand_base_pstate_strategies( - base_strategy_list_3_display, - base_strategy_list_3_display_size, - i, - pmo->init_data.pmo_dcn4.expanded_strategy_list_3_display, - &pmo->init_data.pmo_dcn4.num_expanded_strategies_per_list[i - 1]); + if (pmo->options->override_strategy_lists[i] && pmo->options->num_override_strategies_per_list[i]) { + base_list = pmo->options->override_strategy_lists[i]; + base_list_size = pmo->options->num_override_strategies_per_list[i]; + } else { + base_list = base_strategy_list_3_display; + base_list_size = base_strategy_list_3_display_size; + } + + expanded_list_size = &pmo->init_data.pmo_dcn4.num_expanded_strategies_per_list[i]; + expanded_list = pmo->init_data.pmo_dcn4.expanded_strategy_list_3_display; + break; case 4: - DML_ASSERT(base_strategy_list_4_display_size <= PMO_DCN4_MAX_BASE_STRATEGIES); - - /* populate list */ - pmo_dcn4_fams2_expand_base_pstate_strategies( - base_strategy_list_4_display, - base_strategy_list_4_display_size, - i, - pmo->init_data.pmo_dcn4.expanded_strategy_list_4_display, - &pmo->init_data.pmo_dcn4.num_expanded_strategies_per_list[i - 1]); + if (pmo->options->override_strategy_lists[i] && pmo->options->num_override_strategies_per_list[i]) { + base_list = pmo->options->override_strategy_lists[i]; + base_list_size = pmo->options->num_override_strategies_per_list[i]; + } else { + base_list = base_strategy_list_4_display; + base_list_size = base_strategy_list_4_display_size; + } + + expanded_list_size = &pmo->init_data.pmo_dcn4.num_expanded_strategies_per_list[i]; + expanded_list = pmo->init_data.pmo_dcn4.expanded_strategy_list_4_display; + break; } + + DML_ASSERT(base_list_size <= PMO_DCN4_MAX_BASE_STRATEGIES); + + /* populate list */ + pmo_dcn4_fams2_expand_base_pstate_strategies( + base_list, + base_list_size, + i + 1, + expanded_list, + expanded_list_size); } return true; @@ -1026,13 +1049,13 @@ static bool all_timings_support_vblank(const struct dml2_pmo_instance *pmo, return synchronizable; } -static unsigned int calc_svp_microschedule(const struct dml2_fams2_meta *fams2_meta) +static unsigned int calc_svp_microschedule(const struct dml2_pstate_meta *pstate_meta) { - return fams2_meta->contention_delay_otg_vlines + - fams2_meta->method_subvp.programming_delay_otg_vlines + - fams2_meta->method_subvp.phantom_vtotal + - fams2_meta->method_subvp.prefetch_to_mall_delay_otg_vlines + - fams2_meta->dram_clk_change_blackout_otg_vlines; + return pstate_meta->contention_delay_otg_vlines + + pstate_meta->method_subvp.programming_delay_otg_vlines + + pstate_meta->method_subvp.phantom_vtotal + + pstate_meta->method_subvp.prefetch_to_mall_delay_otg_vlines + + pstate_meta->blackout_otg_vlines; } static bool all_timings_support_drr(const struct dml2_pmo_instance *pmo, @@ -1042,29 +1065,29 @@ static bool all_timings_support_drr(const struct dml2_pmo_instance *pmo, unsigned int i; for (i = 0; i < DML2_MAX_PLANES; i++) { const struct dml2_stream_parameters *stream_descriptor; - const struct dml2_fams2_meta *stream_fams2_meta; + const struct dml2_pstate_meta *stream_pstate_meta; if (is_bit_set_in_bitfield(mask, i)) { stream_descriptor = &display_config->display_config.stream_descriptors[i]; - stream_fams2_meta = &pmo->scratch.pmo_dcn4.stream_fams2_meta[i]; + stream_pstate_meta = &pmo->scratch.pmo_dcn4.stream_pstate_meta[i]; if (!stream_descriptor->timing.drr_config.enabled) return false; /* cannot support required vtotal */ - if (stream_fams2_meta->method_drr.stretched_vtotal > stream_fams2_meta->max_vtotal) { + if (stream_pstate_meta->method_drr.stretched_vtotal > stream_pstate_meta->max_vtotal) { return false; } /* check rr is within bounds */ - if (stream_fams2_meta->nom_refresh_rate_hz < pmo->fams_params.v2.drr.refresh_rate_limit_min || - stream_fams2_meta->nom_refresh_rate_hz > pmo->fams_params.v2.drr.refresh_rate_limit_max) { + if (stream_pstate_meta->nom_refresh_rate_hz < pmo->fams_params.v2.drr.refresh_rate_limit_min || + stream_pstate_meta->nom_refresh_rate_hz > pmo->fams_params.v2.drr.refresh_rate_limit_max) { return false; } /* check required stretch is allowed */ if (stream_descriptor->timing.drr_config.max_instant_vtotal_delta > 0 && - stream_fams2_meta->method_drr.stretched_vtotal - stream_fams2_meta->nom_vtotal > stream_descriptor->timing.drr_config.max_instant_vtotal_delta) { + stream_pstate_meta->method_drr.stretched_vtotal - stream_pstate_meta->nom_vtotal > stream_descriptor->timing.drr_config.max_instant_vtotal_delta) { return false; } } @@ -1079,7 +1102,7 @@ static bool all_timings_support_svp(const struct dml2_pmo_instance *pmo, { const struct dml2_stream_parameters *stream_descriptor; const struct dml2_plane_parameters *plane_descriptor; - const struct dml2_fams2_meta *stream_fams2_meta; + const struct dml2_pstate_meta *stream_pstate_meta; unsigned int microschedule_vlines; unsigned int i; unsigned int mcaches_per_plane; @@ -1124,13 +1147,13 @@ static bool all_timings_support_svp(const struct dml2_pmo_instance *pmo, for (i = 0; i < DML2_MAX_PLANES; i++) { if (is_bit_set_in_bitfield(mask, i)) { stream_descriptor = &display_config->display_config.stream_descriptors[i]; - stream_fams2_meta = &pmo->scratch.pmo_dcn4.stream_fams2_meta[i]; + stream_pstate_meta = &pmo->scratch.pmo_dcn4.stream_pstate_meta[i]; if (stream_descriptor->overrides.disable_subvp) { return false; } - microschedule_vlines = calc_svp_microschedule(&pmo->scratch.pmo_dcn4.stream_fams2_meta[i]); + microschedule_vlines = calc_svp_microschedule(&pmo->scratch.pmo_dcn4.stream_pstate_meta[i]); /* block if using an interlaced timing */ if (stream_descriptor->timing.interlaced) { @@ -1141,8 +1164,8 @@ static bool all_timings_support_svp(const struct dml2_pmo_instance *pmo, * 2) refresh rate must be within the allowed bounds */ if (microschedule_vlines >= stream_descriptor->timing.v_active || - (stream_fams2_meta->nom_refresh_rate_hz < pmo->fams_params.v2.subvp.refresh_rate_limit_min || - stream_fams2_meta->nom_refresh_rate_hz > pmo->fams_params.v2.subvp.refresh_rate_limit_max)) { + (stream_pstate_meta->nom_refresh_rate_hz < pmo->fams_params.v2.subvp.refresh_rate_limit_min || + stream_pstate_meta->nom_refresh_rate_hz > pmo->fams_params.v2.subvp.refresh_rate_limit_max)) { return false; } } @@ -1232,43 +1255,43 @@ static bool all_planes_match_method(const struct display_configuation_with_meta } static void build_method_scheduling_params( - struct dml2_fams2_per_method_common_meta *stream_method_fams2_meta, - struct dml2_fams2_meta *stream_fams2_meta) + struct dml2_pstate_per_method_common_meta *stream_method_pstate_meta, + struct dml2_pstate_meta *stream_pstate_meta) { - stream_method_fams2_meta->allow_time_us = - (double)((int)stream_method_fams2_meta->allow_end_otg_vline - (int)stream_method_fams2_meta->allow_start_otg_vline) * - stream_fams2_meta->otg_vline_time_us; - if (stream_method_fams2_meta->allow_time_us >= stream_method_fams2_meta->period_us) { + stream_method_pstate_meta->allow_time_us = + (double)((int)stream_method_pstate_meta->allow_end_otg_vline - (int)stream_method_pstate_meta->allow_start_otg_vline) * + stream_pstate_meta->otg_vline_time_us; + if (stream_method_pstate_meta->allow_time_us >= stream_method_pstate_meta->period_us) { /* when allow wave overlaps an entire frame, it is always schedulable (DRR can do this)*/ - stream_method_fams2_meta->disallow_time_us = 0.0; + stream_method_pstate_meta->disallow_time_us = 0.0; } else { - stream_method_fams2_meta->disallow_time_us = - stream_method_fams2_meta->period_us - stream_method_fams2_meta->allow_time_us; + stream_method_pstate_meta->disallow_time_us = + stream_method_pstate_meta->period_us - stream_method_pstate_meta->allow_time_us; } } -static struct dml2_fams2_per_method_common_meta *get_per_method_common_meta( +static struct dml2_pstate_per_method_common_meta *get_per_method_common_meta( struct dml2_pmo_instance *pmo, enum dml2_pstate_method stream_pstate_method, int stream_idx) { - struct dml2_fams2_per_method_common_meta *stream_method_fams2_meta = NULL; + struct dml2_pstate_per_method_common_meta *stream_method_pstate_meta = NULL; switch (stream_pstate_method) { case dml2_pstate_method_vactive: case dml2_pstate_method_fw_vactive_drr: - stream_method_fams2_meta = &pmo->scratch.pmo_dcn4.stream_fams2_meta[stream_idx].method_vactive.common; + stream_method_pstate_meta = &pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_idx].method_vactive.common; break; case dml2_pstate_method_vblank: case dml2_pstate_method_fw_vblank_drr: - stream_method_fams2_meta = &pmo->scratch.pmo_dcn4.stream_fams2_meta[stream_idx].method_vblank.common; + stream_method_pstate_meta = &pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_idx].method_vblank.common; break; case dml2_pstate_method_fw_svp: case dml2_pstate_method_fw_svp_drr: - stream_method_fams2_meta = &pmo->scratch.pmo_dcn4.stream_fams2_meta[stream_idx].method_subvp.common; + stream_method_pstate_meta = &pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_idx].method_subvp.common; break; case dml2_pstate_method_fw_drr: - stream_method_fams2_meta = &pmo->scratch.pmo_dcn4.stream_fams2_meta[stream_idx].method_drr.common; + stream_method_pstate_meta = &pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_idx].method_drr.common; break; case dml2_pstate_method_reserved_hw: case dml2_pstate_method_reserved_fw: @@ -1277,10 +1300,10 @@ static struct dml2_fams2_per_method_common_meta *get_per_method_common_meta( case dml2_pstate_method_count: case dml2_pstate_method_na: default: - stream_method_fams2_meta = NULL; + stream_method_pstate_meta = NULL; } - return stream_method_fams2_meta; + return stream_method_pstate_meta; } static bool is_timing_group_schedulable( @@ -1288,10 +1311,10 @@ static bool is_timing_group_schedulable( const struct display_configuation_with_meta *display_cfg, const struct dml2_pmo_pstate_strategy *pstate_strategy, const unsigned int timing_group_idx, - struct dml2_fams2_per_method_common_meta *group_fams2_meta) + struct dml2_pstate_per_method_common_meta *group_pstate_meta) { unsigned int i; - struct dml2_fams2_per_method_common_meta *stream_method_fams2_meta; + struct dml2_pstate_per_method_common_meta *stream_method_pstate_meta; unsigned int base_stream_idx = 0; struct dml2_pmo_scratch *s = &pmo->scratch; @@ -1305,31 +1328,31 @@ static bool is_timing_group_schedulable( } /* init allow start and end lines for timing group */ - stream_method_fams2_meta = get_per_method_common_meta(pmo, pstate_strategy->per_stream_pstate_method[base_stream_idx], base_stream_idx); - if (!stream_method_fams2_meta) + stream_method_pstate_meta = get_per_method_common_meta(pmo, pstate_strategy->per_stream_pstate_method[base_stream_idx], base_stream_idx); + if (!stream_method_pstate_meta) return false; - group_fams2_meta->allow_start_otg_vline = stream_method_fams2_meta->allow_start_otg_vline; - group_fams2_meta->allow_end_otg_vline = stream_method_fams2_meta->allow_end_otg_vline; - group_fams2_meta->period_us = stream_method_fams2_meta->period_us; + group_pstate_meta->allow_start_otg_vline = stream_method_pstate_meta->allow_start_otg_vline; + group_pstate_meta->allow_end_otg_vline = stream_method_pstate_meta->allow_end_otg_vline; + group_pstate_meta->period_us = stream_method_pstate_meta->period_us; for (i = base_stream_idx + 1; i < display_cfg->display_config.num_streams; i++) { if (is_bit_set_in_bitfield(pmo->scratch.pmo_dcn4.synchronized_timing_group_masks[timing_group_idx], i)) { - stream_method_fams2_meta = get_per_method_common_meta(pmo, pstate_strategy->per_stream_pstate_method[i], i); - if (!stream_method_fams2_meta) + stream_method_pstate_meta = get_per_method_common_meta(pmo, pstate_strategy->per_stream_pstate_method[i], i); + if (!stream_method_pstate_meta) continue; - if (group_fams2_meta->allow_start_otg_vline < stream_method_fams2_meta->allow_start_otg_vline) { + if (group_pstate_meta->allow_start_otg_vline < stream_method_pstate_meta->allow_start_otg_vline) { /* set group allow start to larger otg vline */ - group_fams2_meta->allow_start_otg_vline = stream_method_fams2_meta->allow_start_otg_vline; + group_pstate_meta->allow_start_otg_vline = stream_method_pstate_meta->allow_start_otg_vline; } - if (group_fams2_meta->allow_end_otg_vline > stream_method_fams2_meta->allow_end_otg_vline) { + if (group_pstate_meta->allow_end_otg_vline > stream_method_pstate_meta->allow_end_otg_vline) { /* set group allow end to smaller otg vline */ - group_fams2_meta->allow_end_otg_vline = stream_method_fams2_meta->allow_end_otg_vline; + group_pstate_meta->allow_end_otg_vline = stream_method_pstate_meta->allow_end_otg_vline; } /* check waveform still has positive width */ - if (group_fams2_meta->allow_start_otg_vline >= group_fams2_meta->allow_end_otg_vline) { + if (group_pstate_meta->allow_start_otg_vline >= group_pstate_meta->allow_end_otg_vline) { /* timing group is not schedulable */ return false; } @@ -1337,10 +1360,10 @@ static bool is_timing_group_schedulable( } /* calculate the rest of the meta */ - build_method_scheduling_params(group_fams2_meta, &pmo->scratch.pmo_dcn4.stream_fams2_meta[base_stream_idx]); + build_method_scheduling_params(group_pstate_meta, &pmo->scratch.pmo_dcn4.stream_pstate_meta[base_stream_idx]); - return group_fams2_meta->allow_time_us > 0.0 && - group_fams2_meta->disallow_time_us < pmo->ip_caps->fams2.max_allow_delay_us; + return group_pstate_meta->allow_time_us > 0.0 && + group_pstate_meta->disallow_time_us < pmo->ip_caps->fams2.max_allow_delay_us; } static bool is_config_schedulable( @@ -1354,7 +1377,7 @@ static bool is_config_schedulable( double max_allow_delay_us = 0.0; - memset(s->pmo_dcn4.group_common_fams2_meta, 0, sizeof(s->pmo_dcn4.group_common_fams2_meta)); + memset(s->pmo_dcn4.group_common_pstate_meta, 0, sizeof(s->pmo_dcn4.group_common_pstate_meta)); memset(s->pmo_dcn4.sorted_group_gtl_disallow_index, 0, sizeof(unsigned int) * DML2_MAX_PLANES); /* search for a general solution to the schedule */ @@ -1369,12 +1392,12 @@ static bool is_config_schedulable( for (i = 0; i < s->pmo_dcn4.num_timing_groups; i++) { s->pmo_dcn4.sorted_group_gtl_disallow_index[i] = i; s->pmo_dcn4.sorted_group_gtl_period_index[i] = i; - if (!is_timing_group_schedulable(pmo, display_cfg, pstate_strategy, i, &s->pmo_dcn4.group_common_fams2_meta[i])) { + if (!is_timing_group_schedulable(pmo, display_cfg, pstate_strategy, i, &s->pmo_dcn4.group_common_pstate_meta[i])) { /* synchronized timing group was not schedulable */ schedulable = false; break; } - max_allow_delay_us += s->pmo_dcn4.group_common_fams2_meta[i].disallow_time_us; + max_allow_delay_us += s->pmo_dcn4.group_common_pstate_meta[i].disallow_time_us; } if ((schedulable && s->pmo_dcn4.num_timing_groups <= 1) || !schedulable) { @@ -1391,8 +1414,8 @@ static bool is_config_schedulable( bool swapped = false; for (j = 0; j < s->pmo_dcn4.num_timing_groups - 1; j++) { - double j_disallow_us = s->pmo_dcn4.group_common_fams2_meta[s->pmo_dcn4.sorted_group_gtl_disallow_index[j]].disallow_time_us; - double jp1_disallow_us = s->pmo_dcn4.group_common_fams2_meta[s->pmo_dcn4.sorted_group_gtl_disallow_index[j + 1]].disallow_time_us; + double j_disallow_us = s->pmo_dcn4.group_common_pstate_meta[s->pmo_dcn4.sorted_group_gtl_disallow_index[j]].disallow_time_us; + double jp1_disallow_us = s->pmo_dcn4.group_common_pstate_meta[s->pmo_dcn4.sorted_group_gtl_disallow_index[j + 1]].disallow_time_us; if (j_disallow_us < jp1_disallow_us) { /* swap as A < B */ swap(s->pmo_dcn4.sorted_group_gtl_disallow_index[j], @@ -1410,19 +1433,19 @@ static bool is_config_schedulable( * other display, or when >2 streams continue to halve the remaining allow time. */ for (i = 0; i < s->pmo_dcn4.num_timing_groups; i++) { - if (s->pmo_dcn4.group_common_fams2_meta[i].disallow_time_us <= 0.0) { + if (s->pmo_dcn4.group_common_pstate_meta[i].disallow_time_us <= 0.0) { /* this timing group always allows */ continue; } - double max_allow_time_us = s->pmo_dcn4.group_common_fams2_meta[i].allow_time_us; + double max_allow_time_us = s->pmo_dcn4.group_common_pstate_meta[i].allow_time_us; for (j = 0; j < s->pmo_dcn4.num_timing_groups; j++) { unsigned int sorted_j = s->pmo_dcn4.sorted_group_gtl_disallow_index[j]; /* stream can't overlap itself */ - if (i != sorted_j && s->pmo_dcn4.group_common_fams2_meta[sorted_j].disallow_time_us > 0.0) { + if (i != sorted_j && s->pmo_dcn4.group_common_pstate_meta[sorted_j].disallow_time_us > 0.0) { max_allow_time_us = math_min2( - s->pmo_dcn4.group_common_fams2_meta[sorted_j].allow_time_us, - (max_allow_time_us - s->pmo_dcn4.group_common_fams2_meta[sorted_j].disallow_time_us) / 2); + s->pmo_dcn4.group_common_pstate_meta[sorted_j].allow_time_us, + (max_allow_time_us - s->pmo_dcn4.group_common_pstate_meta[sorted_j].disallow_time_us) / 2); if (max_allow_time_us < 0.0) { /* failed exit early */ @@ -1450,8 +1473,8 @@ static bool is_config_schedulable( bool swapped = false; for (j = 0; j < s->pmo_dcn4.num_timing_groups - 1; j++) { - double j_period_us = s->pmo_dcn4.group_common_fams2_meta[s->pmo_dcn4.sorted_group_gtl_period_index[j]].period_us; - double jp1_period_us = s->pmo_dcn4.group_common_fams2_meta[s->pmo_dcn4.sorted_group_gtl_period_index[j + 1]].period_us; + double j_period_us = s->pmo_dcn4.group_common_pstate_meta[s->pmo_dcn4.sorted_group_gtl_period_index[j]].period_us; + double jp1_period_us = s->pmo_dcn4.group_common_pstate_meta[s->pmo_dcn4.sorted_group_gtl_period_index[j + 1]].period_us; if (j_period_us < jp1_period_us) { /* swap as A < B */ swap(s->pmo_dcn4.sorted_group_gtl_period_index[j], @@ -1470,7 +1493,7 @@ static bool is_config_schedulable( unsigned int sorted_i = s->pmo_dcn4.sorted_group_gtl_period_index[i]; unsigned int sorted_ip1 = s->pmo_dcn4.sorted_group_gtl_period_index[i + 1]; - if (s->pmo_dcn4.group_common_fams2_meta[sorted_i].allow_time_us < s->pmo_dcn4.group_common_fams2_meta[sorted_ip1].period_us || + if (s->pmo_dcn4.group_common_pstate_meta[sorted_i].allow_time_us < s->pmo_dcn4.group_common_pstate_meta[sorted_ip1].period_us || (s->pmo_dcn4.group_is_drr_enabled[sorted_ip1] && s->pmo_dcn4.group_is_drr_active[sorted_ip1])) { schedulable = false; break; @@ -1492,18 +1515,18 @@ static bool is_config_schedulable( /* default period_0 > period_1 */ unsigned int lrg_idx = 0; unsigned int sml_idx = 1; - if (s->pmo_dcn4.group_common_fams2_meta[0].period_us < s->pmo_dcn4.group_common_fams2_meta[1].period_us) { + if (s->pmo_dcn4.group_common_pstate_meta[0].period_us < s->pmo_dcn4.group_common_pstate_meta[1].period_us) { /* period_0 < period_1 */ lrg_idx = 1; sml_idx = 0; } - period_ratio = s->pmo_dcn4.group_common_fams2_meta[lrg_idx].period_us / s->pmo_dcn4.group_common_fams2_meta[sml_idx].period_us; - shift_per_period = s->pmo_dcn4.group_common_fams2_meta[sml_idx].period_us * (period_ratio - math_floor(period_ratio)); - max_shift_us = s->pmo_dcn4.group_common_fams2_meta[lrg_idx].disallow_time_us - s->pmo_dcn4.group_common_fams2_meta[sml_idx].allow_time_us; - max_allow_delay_us = max_shift_us / shift_per_period * s->pmo_dcn4.group_common_fams2_meta[lrg_idx].period_us; + period_ratio = s->pmo_dcn4.group_common_pstate_meta[lrg_idx].period_us / s->pmo_dcn4.group_common_pstate_meta[sml_idx].period_us; + shift_per_period = s->pmo_dcn4.group_common_pstate_meta[sml_idx].period_us * (period_ratio - math_floor(period_ratio)); + max_shift_us = s->pmo_dcn4.group_common_pstate_meta[lrg_idx].disallow_time_us - s->pmo_dcn4.group_common_pstate_meta[sml_idx].allow_time_us; + max_allow_delay_us = max_shift_us / shift_per_period * s->pmo_dcn4.group_common_pstate_meta[lrg_idx].period_us; if (shift_per_period > 0.0 && - shift_per_period < s->pmo_dcn4.group_common_fams2_meta[lrg_idx].allow_time_us + s->pmo_dcn4.group_common_fams2_meta[sml_idx].allow_time_us && + shift_per_period < s->pmo_dcn4.group_common_pstate_meta[lrg_idx].allow_time_us + s->pmo_dcn4.group_common_pstate_meta[sml_idx].allow_time_us && max_allow_delay_us < pmo->ip_caps->fams2.max_allow_delay_us) { schedulable = true; } @@ -1661,7 +1684,7 @@ static unsigned int get_vactive_det_fill_latency_delay_us(const struct display_c return max_vactive_fill_us; } -static void build_fams2_meta_per_stream(struct dml2_pmo_instance *pmo, +static void build_pstate_meta_per_stream(struct dml2_pmo_instance *pmo, struct display_configuation_with_meta *display_config, int stream_index) { @@ -1669,7 +1692,7 @@ static void build_fams2_meta_per_stream(struct dml2_pmo_instance *pmo, const struct dml2_stream_parameters *stream_descriptor = &display_config->display_config.stream_descriptors[stream_index]; const struct core_stream_support_info *stream_info = &display_config->mode_support_result.cfg_support_info.stream_support_info[stream_index]; const struct dml2_timing_cfg *timing = &stream_descriptor->timing; - struct dml2_fams2_meta *stream_fams2_meta = &pmo->scratch.pmo_dcn4.stream_fams2_meta[stream_index]; + struct dml2_pstate_meta *stream_pstate_meta = &pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_index]; /* worst case all other streams require some programming at the same time, 0 if only 1 stream */ unsigned int contention_delay_us = (ip_caps->fams2.vertical_interrupt_ack_delay_us + @@ -1677,142 +1700,142 @@ static void build_fams2_meta_per_stream(struct dml2_pmo_instance *pmo, (display_config->display_config.num_streams - 1); /* common */ - stream_fams2_meta->valid = true; - stream_fams2_meta->otg_vline_time_us = (double)timing->h_total / timing->pixel_clock_khz * 1000.0; - stream_fams2_meta->nom_vtotal = stream_descriptor->timing.vblank_nom + stream_descriptor->timing.v_active; - stream_fams2_meta->nom_refresh_rate_hz = timing->pixel_clock_khz * 1000.0 / - (stream_fams2_meta->nom_vtotal * timing->h_total); - stream_fams2_meta->nom_frame_time_us = - (double)stream_fams2_meta->nom_vtotal * stream_fams2_meta->otg_vline_time_us; - stream_fams2_meta->vblank_start = timing->v_blank_end + timing->v_active; + stream_pstate_meta->valid = true; + stream_pstate_meta->otg_vline_time_us = (double)timing->h_total / timing->pixel_clock_khz * 1000.0; + stream_pstate_meta->nom_vtotal = stream_descriptor->timing.vblank_nom + stream_descriptor->timing.v_active; + stream_pstate_meta->nom_refresh_rate_hz = timing->pixel_clock_khz * 1000.0 / + (stream_pstate_meta->nom_vtotal * timing->h_total); + stream_pstate_meta->nom_frame_time_us = + (double)stream_pstate_meta->nom_vtotal * stream_pstate_meta->otg_vline_time_us; + stream_pstate_meta->vblank_start = timing->v_blank_end + timing->v_active; if (stream_descriptor->timing.drr_config.enabled == true) { if (stream_descriptor->timing.drr_config.min_refresh_uhz != 0.0) { - stream_fams2_meta->max_vtotal = (unsigned int)math_floor((double)stream_descriptor->timing.pixel_clock_khz / + stream_pstate_meta->max_vtotal = (unsigned int)math_floor((double)stream_descriptor->timing.pixel_clock_khz / ((double)stream_descriptor->timing.drr_config.min_refresh_uhz * stream_descriptor->timing.h_total) * 1e9); } else { /* assume min of 48Hz */ - stream_fams2_meta->max_vtotal = (unsigned int)math_floor((double)stream_descriptor->timing.pixel_clock_khz / + stream_pstate_meta->max_vtotal = (unsigned int)math_floor((double)stream_descriptor->timing.pixel_clock_khz / (48000000.0 * stream_descriptor->timing.h_total) * 1e9); } } else { - stream_fams2_meta->max_vtotal = stream_fams2_meta->nom_vtotal; - } - stream_fams2_meta->min_refresh_rate_hz = timing->pixel_clock_khz * 1000.0 / - (stream_fams2_meta->max_vtotal * timing->h_total); - stream_fams2_meta->max_frame_time_us = - (double)stream_fams2_meta->max_vtotal * stream_fams2_meta->otg_vline_time_us; - - stream_fams2_meta->scheduling_delay_otg_vlines = - (unsigned int)math_ceil(ip_caps->fams2.scheduling_delay_us / stream_fams2_meta->otg_vline_time_us); - stream_fams2_meta->vertical_interrupt_ack_delay_otg_vlines = - (unsigned int)math_ceil(ip_caps->fams2.vertical_interrupt_ack_delay_us / stream_fams2_meta->otg_vline_time_us); - stream_fams2_meta->contention_delay_otg_vlines = - (unsigned int)math_ceil(contention_delay_us / stream_fams2_meta->otg_vline_time_us); + stream_pstate_meta->max_vtotal = stream_pstate_meta->nom_vtotal; + } + stream_pstate_meta->min_refresh_rate_hz = timing->pixel_clock_khz * 1000.0 / + (stream_pstate_meta->max_vtotal * timing->h_total); + stream_pstate_meta->max_frame_time_us = + (double)stream_pstate_meta->max_vtotal * stream_pstate_meta->otg_vline_time_us; + + stream_pstate_meta->scheduling_delay_otg_vlines = + (unsigned int)math_ceil(ip_caps->fams2.scheduling_delay_us / stream_pstate_meta->otg_vline_time_us); + stream_pstate_meta->vertical_interrupt_ack_delay_otg_vlines = + (unsigned int)math_ceil(ip_caps->fams2.vertical_interrupt_ack_delay_us / stream_pstate_meta->otg_vline_time_us); + stream_pstate_meta->contention_delay_otg_vlines = + (unsigned int)math_ceil(contention_delay_us / stream_pstate_meta->otg_vline_time_us); /* worst case allow to target needs to account for all streams' allow events overlapping, and 1 line for error */ - stream_fams2_meta->allow_to_target_delay_otg_vlines = - (unsigned int)(math_ceil((ip_caps->fams2.vertical_interrupt_ack_delay_us + contention_delay_us + ip_caps->fams2.allow_programming_delay_us) / stream_fams2_meta->otg_vline_time_us)) + 1; - stream_fams2_meta->min_allow_width_otg_vlines = - (unsigned int)math_ceil(ip_caps->fams2.min_allow_width_us / stream_fams2_meta->otg_vline_time_us); + stream_pstate_meta->allow_to_target_delay_otg_vlines = + (unsigned int)(math_ceil((ip_caps->fams2.vertical_interrupt_ack_delay_us + contention_delay_us + ip_caps->fams2.allow_programming_delay_us) / stream_pstate_meta->otg_vline_time_us)) + 1; + stream_pstate_meta->min_allow_width_otg_vlines = + (unsigned int)math_ceil(ip_caps->fams2.min_allow_width_us / stream_pstate_meta->otg_vline_time_us); /* this value should account for urgent latency */ - stream_fams2_meta->dram_clk_change_blackout_otg_vlines = + stream_pstate_meta->blackout_otg_vlines = (unsigned int)math_ceil(pmo->soc_bb->power_management_parameters.dram_clk_change_blackout_us / - stream_fams2_meta->otg_vline_time_us); + stream_pstate_meta->otg_vline_time_us); /* scheduling params should be built based on the worst case for allow_time:disallow_time */ /* vactive */ if (display_config->display_config.num_streams == 1) { /* for single stream, guarantee at least an instant of allow */ - stream_fams2_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines = (unsigned int)math_floor( + stream_pstate_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines = (unsigned int)math_floor( math_max2(0.0, - timing->v_active - math_max2(1.0, stream_fams2_meta->min_allow_width_otg_vlines) - stream_fams2_meta->dram_clk_change_blackout_otg_vlines)); + timing->v_active - math_max2(1.0, stream_pstate_meta->min_allow_width_otg_vlines) - stream_pstate_meta->blackout_otg_vlines)); } else { /* for multi stream, bound to a max fill time defined by IP caps */ - stream_fams2_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines = - (unsigned int)math_floor((double)ip_caps->max_vactive_det_fill_delay_us / stream_fams2_meta->otg_vline_time_us); + stream_pstate_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines = + (unsigned int)math_floor((double)ip_caps->max_vactive_det_fill_delay_us / stream_pstate_meta->otg_vline_time_us); } - stream_fams2_meta->method_vactive.max_vactive_det_fill_delay_us = stream_fams2_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines * stream_fams2_meta->otg_vline_time_us; + stream_pstate_meta->method_vactive.max_vactive_det_fill_delay_us = stream_pstate_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines * stream_pstate_meta->otg_vline_time_us; - if (stream_fams2_meta->method_vactive.max_vactive_det_fill_delay_us > 0.0) { - stream_fams2_meta->method_vactive.common.allow_start_otg_vline = - timing->v_blank_end + stream_fams2_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines; - stream_fams2_meta->method_vactive.common.allow_end_otg_vline = - stream_fams2_meta->vblank_start - - stream_fams2_meta->dram_clk_change_blackout_otg_vlines; + if (stream_pstate_meta->method_vactive.max_vactive_det_fill_delay_us > 0.0) { + stream_pstate_meta->method_vactive.common.allow_start_otg_vline = + timing->v_blank_end + stream_pstate_meta->method_vactive.max_vactive_det_fill_delay_otg_vlines; + stream_pstate_meta->method_vactive.common.allow_end_otg_vline = + stream_pstate_meta->vblank_start - + stream_pstate_meta->blackout_otg_vlines; } else { - stream_fams2_meta->method_vactive.common.allow_start_otg_vline = 0; - stream_fams2_meta->method_vactive.common.allow_end_otg_vline = 0; + stream_pstate_meta->method_vactive.common.allow_start_otg_vline = 0; + stream_pstate_meta->method_vactive.common.allow_end_otg_vline = 0; } - stream_fams2_meta->method_vactive.common.period_us = stream_fams2_meta->nom_frame_time_us; - build_method_scheduling_params(&stream_fams2_meta->method_vactive.common, stream_fams2_meta); + stream_pstate_meta->method_vactive.common.period_us = stream_pstate_meta->nom_frame_time_us; + build_method_scheduling_params(&stream_pstate_meta->method_vactive.common, stream_pstate_meta); /* vblank */ - stream_fams2_meta->method_vblank.common.allow_start_otg_vline = stream_fams2_meta->vblank_start; - stream_fams2_meta->method_vblank.common.allow_end_otg_vline = - stream_fams2_meta->method_vblank.common.allow_start_otg_vline + 1; - stream_fams2_meta->method_vblank.common.period_us = stream_fams2_meta->nom_frame_time_us; - build_method_scheduling_params(&stream_fams2_meta->method_vblank.common, stream_fams2_meta); + stream_pstate_meta->method_vblank.common.allow_start_otg_vline = stream_pstate_meta->vblank_start; + stream_pstate_meta->method_vblank.common.allow_end_otg_vline = + stream_pstate_meta->method_vblank.common.allow_start_otg_vline + 1; + stream_pstate_meta->method_vblank.common.period_us = stream_pstate_meta->nom_frame_time_us; + build_method_scheduling_params(&stream_pstate_meta->method_vblank.common, stream_pstate_meta); /* subvp */ - stream_fams2_meta->method_subvp.programming_delay_otg_vlines = - (unsigned int)math_ceil(ip_caps->fams2.subvp_programming_delay_us / stream_fams2_meta->otg_vline_time_us); - stream_fams2_meta->method_subvp.df_throttle_delay_otg_vlines = - (unsigned int)math_ceil(ip_caps->fams2.subvp_df_throttle_delay_us / stream_fams2_meta->otg_vline_time_us); - stream_fams2_meta->method_subvp.prefetch_to_mall_delay_otg_vlines = - (unsigned int)math_ceil(ip_caps->fams2.subvp_prefetch_to_mall_delay_us / stream_fams2_meta->otg_vline_time_us); - stream_fams2_meta->method_subvp.phantom_vactive = - stream_fams2_meta->allow_to_target_delay_otg_vlines + - stream_fams2_meta->min_allow_width_otg_vlines + + stream_pstate_meta->method_subvp.programming_delay_otg_vlines = + (unsigned int)math_ceil(ip_caps->fams2.subvp_programming_delay_us / stream_pstate_meta->otg_vline_time_us); + stream_pstate_meta->method_subvp.df_throttle_delay_otg_vlines = + (unsigned int)math_ceil(ip_caps->fams2.subvp_df_throttle_delay_us / stream_pstate_meta->otg_vline_time_us); + stream_pstate_meta->method_subvp.prefetch_to_mall_delay_otg_vlines = + (unsigned int)math_ceil(ip_caps->fams2.subvp_prefetch_to_mall_delay_us / stream_pstate_meta->otg_vline_time_us); + stream_pstate_meta->method_subvp.phantom_vactive = + stream_pstate_meta->allow_to_target_delay_otg_vlines + + stream_pstate_meta->min_allow_width_otg_vlines + stream_info->phantom_min_v_active; - stream_fams2_meta->method_subvp.phantom_vfp = - stream_fams2_meta->method_subvp.df_throttle_delay_otg_vlines; + stream_pstate_meta->method_subvp.phantom_vfp = + stream_pstate_meta->method_subvp.df_throttle_delay_otg_vlines; /* phantom vtotal = v_bp(vstartup) + v_sync(1) + v_fp(throttle_delay) + v_active(allow_to_target + min_allow + min_vactive)*/ - stream_fams2_meta->method_subvp.phantom_vtotal = + stream_pstate_meta->method_subvp.phantom_vtotal = stream_info->phantom_v_startup + - stream_fams2_meta->method_subvp.phantom_vfp + + stream_pstate_meta->method_subvp.phantom_vfp + 1 + - stream_fams2_meta->method_subvp.df_throttle_delay_otg_vlines + - stream_fams2_meta->method_subvp.phantom_vactive; - stream_fams2_meta->method_subvp.common.allow_start_otg_vline = + stream_pstate_meta->method_subvp.df_throttle_delay_otg_vlines + + stream_pstate_meta->method_subvp.phantom_vactive; + stream_pstate_meta->method_subvp.common.allow_start_otg_vline = stream_descriptor->timing.v_blank_end + - stream_fams2_meta->contention_delay_otg_vlines + - stream_fams2_meta->method_subvp.programming_delay_otg_vlines + - stream_fams2_meta->method_subvp.phantom_vtotal + - stream_fams2_meta->method_subvp.prefetch_to_mall_delay_otg_vlines + - stream_fams2_meta->allow_to_target_delay_otg_vlines; - stream_fams2_meta->method_subvp.common.allow_end_otg_vline = - stream_fams2_meta->vblank_start - - stream_fams2_meta->dram_clk_change_blackout_otg_vlines; - stream_fams2_meta->method_subvp.common.period_us = stream_fams2_meta->nom_frame_time_us; - build_method_scheduling_params(&stream_fams2_meta->method_subvp.common, stream_fams2_meta); + stream_pstate_meta->contention_delay_otg_vlines + + stream_pstate_meta->method_subvp.programming_delay_otg_vlines + + stream_pstate_meta->method_subvp.phantom_vtotal + + stream_pstate_meta->method_subvp.prefetch_to_mall_delay_otg_vlines + + stream_pstate_meta->allow_to_target_delay_otg_vlines; + stream_pstate_meta->method_subvp.common.allow_end_otg_vline = + stream_pstate_meta->vblank_start - + stream_pstate_meta->blackout_otg_vlines; + stream_pstate_meta->method_subvp.common.period_us = stream_pstate_meta->nom_frame_time_us; + build_method_scheduling_params(&stream_pstate_meta->method_subvp.common, stream_pstate_meta); /* drr */ - stream_fams2_meta->method_drr.programming_delay_otg_vlines = - (unsigned int)math_ceil(ip_caps->fams2.drr_programming_delay_us / stream_fams2_meta->otg_vline_time_us); - stream_fams2_meta->method_drr.common.allow_start_otg_vline = - stream_fams2_meta->vblank_start + - stream_fams2_meta->allow_to_target_delay_otg_vlines; - stream_fams2_meta->method_drr.common.period_us = stream_fams2_meta->nom_frame_time_us; + stream_pstate_meta->method_drr.programming_delay_otg_vlines = + (unsigned int)math_ceil(ip_caps->fams2.drr_programming_delay_us / stream_pstate_meta->otg_vline_time_us); + stream_pstate_meta->method_drr.common.allow_start_otg_vline = + stream_pstate_meta->vblank_start + + stream_pstate_meta->allow_to_target_delay_otg_vlines; + stream_pstate_meta->method_drr.common.period_us = stream_pstate_meta->nom_frame_time_us; if (display_config->display_config.num_streams <= 1) { /* only need to stretch vblank for blackout time */ - stream_fams2_meta->method_drr.stretched_vtotal = - stream_fams2_meta->nom_vtotal + - stream_fams2_meta->allow_to_target_delay_otg_vlines + - stream_fams2_meta->min_allow_width_otg_vlines + - stream_fams2_meta->dram_clk_change_blackout_otg_vlines; + stream_pstate_meta->method_drr.stretched_vtotal = + stream_pstate_meta->nom_vtotal + + stream_pstate_meta->allow_to_target_delay_otg_vlines + + stream_pstate_meta->min_allow_width_otg_vlines + + stream_pstate_meta->blackout_otg_vlines; } else { /* multi display needs to always be schedulable */ - stream_fams2_meta->method_drr.stretched_vtotal = - stream_fams2_meta->nom_vtotal * 2 + - stream_fams2_meta->allow_to_target_delay_otg_vlines + - stream_fams2_meta->min_allow_width_otg_vlines + - stream_fams2_meta->dram_clk_change_blackout_otg_vlines; - } - stream_fams2_meta->method_drr.common.allow_end_otg_vline = - stream_fams2_meta->method_drr.stretched_vtotal - - stream_fams2_meta->dram_clk_change_blackout_otg_vlines; - build_method_scheduling_params(&stream_fams2_meta->method_drr.common, stream_fams2_meta); + stream_pstate_meta->method_drr.stretched_vtotal = + stream_pstate_meta->nom_vtotal * 2 + + stream_pstate_meta->allow_to_target_delay_otg_vlines + + stream_pstate_meta->min_allow_width_otg_vlines + + stream_pstate_meta->blackout_otg_vlines; + } + stream_pstate_meta->method_drr.common.allow_end_otg_vline = + stream_pstate_meta->method_drr.stretched_vtotal - + stream_pstate_meta->blackout_otg_vlines; + build_method_scheduling_params(&stream_pstate_meta->method_drr.common, stream_pstate_meta); } static void build_subvp_meta_per_stream(struct dml2_pmo_instance *pmo, @@ -1820,14 +1843,14 @@ static void build_subvp_meta_per_stream(struct dml2_pmo_instance *pmo, int stream_index) { struct dml2_implicit_svp_meta *stream_svp_meta = &pmo->scratch.pmo_dcn4.stream_svp_meta[stream_index]; - struct dml2_fams2_meta *stream_fams2_meta = &pmo->scratch.pmo_dcn4.stream_fams2_meta[stream_index]; + struct dml2_pstate_meta *stream_pstate_meta = &pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_index]; stream_svp_meta->valid = true; /* PMO FAMS2 precaulcates these values */ - stream_svp_meta->v_active = stream_fams2_meta->method_subvp.phantom_vactive; - stream_svp_meta->v_front_porch = stream_fams2_meta->method_subvp.phantom_vfp; - stream_svp_meta->v_total = stream_fams2_meta->method_subvp.phantom_vtotal; + stream_svp_meta->v_active = stream_pstate_meta->method_subvp.phantom_vactive; + stream_svp_meta->v_front_porch = stream_pstate_meta->method_subvp.phantom_vfp; + stream_svp_meta->v_total = stream_pstate_meta->method_subvp.phantom_vtotal; } bool pmo_dcn4_fams2_init_for_pstate_support(struct dml2_pmo_init_for_pstate_support_in_out *in_out) @@ -1879,7 +1902,7 @@ bool pmo_dcn4_fams2_init_for_pstate_support(struct dml2_pmo_init_for_pstate_supp set_bit_in_bitfield(&s->pmo_dcn4.stream_vactive_capability_mask, stream_index); /* FAMS2 meta */ - build_fams2_meta_per_stream(pmo, display_config, stream_index); + build_pstate_meta_per_stream(pmo, display_config, stream_index); /* SVP meta */ build_subvp_meta_per_stream(pmo, display_config, stream_index); @@ -2077,7 +2100,7 @@ static void setup_planes_for_vactive_by_mask(struct display_configuation_with_me if (!pmo->options->disable_vactive_det_fill_bw_pad) { display_config->display_config.plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us = - (unsigned int)math_floor(pmo->scratch.pmo_dcn4.stream_fams2_meta[stream_index].method_vactive.max_vactive_det_fill_delay_us); + (unsigned int)math_floor(pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_index].method_vactive.max_vactive_det_fill_delay_us); } } } @@ -2098,7 +2121,7 @@ static void setup_planes_for_vactive_drr_by_mask(struct display_configuation_wit if (!pmo->options->disable_vactive_det_fill_bw_pad) { display_config->display_config.plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us = - (unsigned int)math_floor(pmo->scratch.pmo_dcn4.stream_fams2_meta[stream_index].method_vactive.max_vactive_det_fill_delay_us); + (unsigned int)math_floor(pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_index].method_vactive.max_vactive_det_fill_delay_us); } } } @@ -2144,9 +2167,9 @@ static bool setup_display_config(struct display_configuation_with_meta *display_ /* copy FAMS2 meta */ if (success) { display_config->stage3.fams2_required = fams2_required; - memcpy(&display_config->stage3.stream_fams2_meta, - &scratch->pmo_dcn4.stream_fams2_meta, - sizeof(struct dml2_fams2_meta) * DML2_MAX_PLANES); + memcpy(&display_config->stage3.stream_pstate_meta, + &scratch->pmo_dcn4.stream_pstate_meta, + sizeof(struct dml2_pstate_meta) * DML2_MAX_PLANES); } return success; @@ -2188,12 +2211,12 @@ bool pmo_dcn4_fams2_test_for_pstate_support(struct dml2_pmo_test_for_pstate_supp return false; for (stream_index = 0; stream_index < in_out->base_display_config->display_config.num_streams; stream_index++) { - struct dml2_fams2_meta *stream_fams2_meta = &s->pmo_dcn4.stream_fams2_meta[stream_index]; + struct dml2_pstate_meta *stream_pstate_meta = &s->pmo_dcn4.stream_pstate_meta[stream_index]; if (s->pmo_dcn4.pstate_strategy_candidates[s->pmo_dcn4.cur_pstate_candidate].per_stream_pstate_method[stream_index] == dml2_pstate_method_vactive || s->pmo_dcn4.pstate_strategy_candidates[s->pmo_dcn4.cur_pstate_candidate].per_stream_pstate_method[stream_index] == dml2_pstate_method_fw_vactive_drr) { if (get_vactive_pstate_margin(in_out->base_display_config, s->pmo_dcn4.stream_plane_mask[stream_index]) < (MIN_VACTIVE_MARGIN_PCT * in_out->instance->soc_bb->power_management_parameters.dram_clk_change_blackout_us) || - get_vactive_det_fill_latency_delay_us(in_out->base_display_config, s->pmo_dcn4.stream_plane_mask[stream_index]) > stream_fams2_meta->method_vactive.max_vactive_det_fill_delay_us) { + get_vactive_det_fill_latency_delay_us(in_out->base_display_config, s->pmo_dcn4.stream_plane_mask[stream_index]) > stream_pstate_meta->method_vactive.max_vactive_det_fill_delay_us) { p_state_supported = false; break; } diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h index d52aa82283b36..9f562f0c47970 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h @@ -255,7 +255,7 @@ struct dml2_implicit_svp_meta { unsigned long v_front_porch; }; -struct dml2_fams2_per_method_common_meta { +struct dml2_pstate_per_method_common_meta { /* generic params */ unsigned int allow_start_otg_vline; unsigned int allow_end_otg_vline; @@ -265,7 +265,7 @@ struct dml2_fams2_per_method_common_meta { double period_us; }; -struct dml2_fams2_meta { +struct dml2_pstate_meta { bool valid; double otg_vline_time_us; unsigned int scheduling_delay_otg_vlines; @@ -280,14 +280,14 @@ struct dml2_fams2_meta { unsigned int max_vtotal; double min_refresh_rate_hz; double max_frame_time_us; - unsigned int dram_clk_change_blackout_otg_vlines; + unsigned int blackout_otg_vlines; struct { double max_vactive_det_fill_delay_us; unsigned int max_vactive_det_fill_delay_otg_vlines; - struct dml2_fams2_per_method_common_meta common; + struct dml2_pstate_per_method_common_meta common; } method_vactive; struct { - struct dml2_fams2_per_method_common_meta common; + struct dml2_pstate_per_method_common_meta common; } method_vblank; struct { unsigned int programming_delay_otg_vlines; @@ -296,15 +296,24 @@ struct dml2_fams2_meta { unsigned long phantom_vactive; unsigned long phantom_vfp; unsigned long phantom_vtotal; - struct dml2_fams2_per_method_common_meta common; + struct dml2_pstate_per_method_common_meta common; } method_subvp; struct { unsigned int programming_delay_otg_vlines; unsigned int stretched_vtotal; - struct dml2_fams2_per_method_common_meta common; + struct dml2_pstate_per_method_common_meta common; } method_drr; }; +/* mask of synchronized timings by stream index */ +struct dml2_pmo_synchronized_timing_groups { + unsigned int num_timing_groups; + unsigned int synchronized_timing_group_masks[DML2_MAX_PLANES]; + bool group_is_drr_enabled[DML2_MAX_PLANES]; + bool group_is_drr_active[DML2_MAX_PLANES]; + double group_line_time_us[DML2_MAX_PLANES]; +}; + struct dml2_optimization_stage3_state { bool performed; bool success; @@ -319,7 +328,7 @@ struct dml2_optimization_stage3_state { // Meta-data for FAMS2 bool fams2_required; - struct dml2_fams2_meta stream_fams2_meta[DML2_MAX_PLANES]; + struct dml2_pstate_meta stream_pstate_meta[DML2_MAX_PLANES]; int min_clk_index_for_latency; }; @@ -472,6 +481,7 @@ struct dml2_core_scratch { }; struct dml2_core_instance { + enum dml2_project_id project_id; struct dml2_mcg_min_clock_table *minimum_clock_table; struct dml2_core_internal_state_inputs inputs; struct dml2_core_internal_state_intermediates intermediates; @@ -619,6 +629,12 @@ struct dml2_pmo_optimize_for_stutter_in_out { #define PMO_DCN4_MAX_NUM_VARIANTS 2 #define PMO_DCN4_MAX_BASE_STRATEGIES 10 +struct dml2_scheduling_check_locals { + struct dml2_pstate_per_method_common_meta group_common_pstate_meta[DML2_MAX_PLANES]; + unsigned int sorted_group_gtl_disallow_index[DML2_MAX_PLANES]; + unsigned int sorted_group_gtl_period_index[DML2_MAX_PLANES]; +}; + struct dml2_pmo_scratch { union { struct { @@ -648,7 +664,7 @@ struct dml2_pmo_scratch { // Stores all the implicit SVP meta information indexed by stream index of the display // configuration under inspection, built at optimization stage init struct dml2_implicit_svp_meta stream_svp_meta[DML2_MAX_PLANES]; - struct dml2_fams2_meta stream_fams2_meta[DML2_MAX_PLANES]; + struct dml2_pstate_meta stream_pstate_meta[DML2_MAX_PLANES]; unsigned int optimal_vblank_reserved_time_for_stutter_us[DML2_PMO_STUTTER_CANDIDATE_LIST_SIZE]; unsigned int num_stutter_candidates; @@ -663,7 +679,7 @@ struct dml2_pmo_scratch { double group_line_time_us[DML2_MAX_PLANES]; /* scheduling check locals */ - struct dml2_fams2_per_method_common_meta group_common_fams2_meta[DML2_MAX_PLANES]; + struct dml2_pstate_per_method_common_meta group_common_pstate_meta[DML2_MAX_PLANES]; unsigned int sorted_group_gtl_disallow_index[DML2_MAX_PLANES]; unsigned int sorted_group_gtl_period_index[DML2_MAX_PLANES]; double group_phase_offset[DML2_MAX_PLANES]; From d94d2e5e59b29a0542311d50da97986feb8f1eed Mon Sep 17 00:00:00 2001 From: Relja Vojvodic Date: Wed, 17 Sep 2025 12:30:51 -0400 Subject: [PATCH 2152/2653] drm/amd/display: Correct slice width calculation for YCbCr420 [Why] -OVT compliance testing for 5120x2880p300Hz YCbCr420 was failing due to incorrect slice width being calculated [How] -Ensure slice width is divisible by 2 for 420 to comply with spec Reviewed-by: Wenjing Liu Signed-off-by: Relja Vojvodic Signed-off-by: Roman Li Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 2 +- drivers/gpu/drm/amd/display/dc/dsc/dsc.h | 1 + drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 1 + drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 1 + drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 1 + drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 2 ++ drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 1 + 7 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c index b7495777c58de..d7bacc3249a23 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c @@ -409,7 +409,7 @@ bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0; // Need to find the ceiling value for the slice width - dsc_reg_vals->pps.slice_width = (dsc_cfg->pic_width + dsc_cfg->dc_dsc_cfg.num_slices_h - 1) / dsc_cfg->dc_dsc_cfg.num_slices_h; + dsc_reg_vals->pps.slice_width = (dsc_cfg->pic_width + dsc_cfg->dsc_padding + dsc_cfg->dc_dsc_cfg.num_slices_h - 1) / dsc_cfg->dc_dsc_cfg.num_slices_h; // TODO: in addition to validating slice height (pic height must be divisible by slice height), // see what happens when the same condition doesn't apply for slice_width/pic_width. dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dsc.h index b0bd1f9425b5c..b433e16842bf6 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dsc.h @@ -41,6 +41,7 @@ struct dsc_config { enum dc_color_depth color_depth; /* Bits per component */ bool is_odm; struct dc_dsc_config dc_dsc_cfg; + uint32_t dsc_padding; }; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c index f925f669f2a4d..4ee6ed610de0b 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c @@ -108,6 +108,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; + dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index d4d8d03efbd64..ba7748e92113d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -1060,6 +1060,7 @@ void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; + dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; if (should_use_dto_dscclk) dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 05011061822cf..7ea3fe48b329e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -364,6 +364,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; + dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index 5ff6a0849c4d8..a9387c3a72b1b 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -841,6 +841,7 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; + dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; if (should_use_dto_dscclk) dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); @@ -970,6 +971,7 @@ bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immedi dsc_cfg.color_depth = stream->timing.display_color_depth; dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; + dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index ac37088285464..d4e75cf6d0b21 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -1661,6 +1661,7 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; + dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) return false; From 6680245a6c2cb7b870ca5e01f2502e500abb3b8f Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Wed, 17 Sep 2025 11:21:30 -0400 Subject: [PATCH 2153/2653] drm/amd/display: Consolidate two DML2 FP guards [Why&How] Consolidate two FP guards into one in dml2 since they are separated by one line of code, independent from the guard. Reviewed-by: Dillon Varone Signed-off-by: Ivan Lipski Signed-off-by: Roman Li Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c index 08f7f03b10231..43d333d6608e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c @@ -283,9 +283,7 @@ static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *co mode_support->dml2_instance = dml_init->dml2_instance; DC_FP_START(); dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); - DC_FP_END(); dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.programming; - DC_FP_START(); is_supported = dml2_check_mode_supported(mode_support); DC_FP_END(); if (!is_supported) From 212c8d492ddf7e9e2ee772eeb8a174947b6e0eec Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Tue, 16 Sep 2025 13:57:17 -0400 Subject: [PATCH 2154/2653] drm/amd/display: Support possibly NULL link for should_use_dmub_lock [Why] It's possible to have a stream enabled without a link or link encoder. There are cases where we'd still like to interlock the driver programming from firmware programming to ensure that we don't put the hardware in an undefined (or error) state if two programming sequences are simultaneously executed on the same hardware blocks. [How] Add an explicit DC parameter to should_use_dmub_lock(). Make pointers to should_use_dmub_lock() const since it's a checker function that shouldn't modify state. Update the callsites to pass in DC explicitly. Check that the link is non-NULL before deferencing and performing link based checks. Reviewed-by: Alvin Lee Signed-off-by: Nicholas Kazlauskas Signed-off-by: Roman Li Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +-- .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 29 ++++++++++--------- .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.h | 2 +- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 2 +- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 +- .../display/dc/link/accessories/link_dp_cts.c | 4 +-- 6 files changed, 23 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 3e86283675780..9baa6b5c682b1 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -4150,7 +4150,7 @@ static void commit_planes_for_stream(struct dc *dc, if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) if (top_pipe_to_program && top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) { - if (should_use_dmub_lock(stream->link)) { + if (should_use_dmub_lock(dc, stream->link)) { union dmub_hw_lock_flags hw_locks = { 0 }; struct dmub_hw_lock_inst_flags inst_flags = { 0 }; @@ -4420,7 +4420,7 @@ static void commit_planes_for_stream(struct dc *dc, top_pipe_to_program->stream_res.tg, CRTC_STATE_VACTIVE); - if (should_use_dmub_lock(stream->link)) { + if (should_use_dmub_lock(dc, stream->link)) { union dmub_hw_lock_flags hw_locks = { 0 }; struct dmub_hw_lock_inst_flags inst_flags = { 0 }; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c index d37ecfdde4f1b..17c30c5b16794 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c @@ -61,27 +61,30 @@ void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv, dc_dmub_srv_wait_for_inbox0_ack(dmub_srv); } -bool should_use_dmub_lock(struct dc_link *link) +bool should_use_dmub_lock(const struct dc *dc, const struct dc_link *link) { /* ASIC doesn't support DMUB */ - if (!link->ctx->dmub_srv) + if (!dc->ctx->dmub_srv) return false; - if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) - return true; + if (link) { - if (link->replay_settings.replay_feature_enabled) - return true; + if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) + return true; + + if (link->replay_settings.replay_feature_enabled) + return true; - /* only use HW lock for PSR1 on single eDP */ - if (link->psr_settings.psr_version == DC_PSR_VERSION_1) { - struct dc_link *edp_links[MAX_NUM_EDP]; - int edp_num; + /* only use HW lock for PSR1 on single eDP */ + if (link->psr_settings.psr_version == DC_PSR_VERSION_1) { + struct dc_link *edp_links[MAX_NUM_EDP]; + int edp_num; - dc_get_edp_links(link->dc, edp_links, &edp_num); + dc_get_edp_links(dc, edp_links, &edp_num); - if (edp_num == 1) - return true; + if (edp_num == 1) + return true; + } } return false; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h index 5a72b168fb4ae..6e88638776869 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h @@ -37,6 +37,6 @@ void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv, void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_cmd_lock_hw hw_lock_cmd); -bool should_use_dmub_lock(struct dc_link *link); +bool should_use_dmub_lock(const struct dc *dc, const struct dc_link *link); #endif /*_DMUB_HW_LOCK_MGR_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index e9fe97f0c4ea8..cb915abac15a6 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -2245,7 +2245,7 @@ void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock) if (lock) delay_cursor_until_vupdate(dc, pipe); - if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) { + if (pipe->stream && should_use_dmub_lock(dc, pipe->stream->link)) { union dmub_hw_lock_flags hw_locks = { 0 }; struct dmub_hw_lock_inst_flags inst_flags = { 0 }; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 9477c9f9e1963..650a1697557b2 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -1449,7 +1449,7 @@ void dcn20_pipe_control_lock( !flip_immediate) dcn20_setup_gsl_group_as_lock(dc, pipe, false); - if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) { + if (pipe->stream && should_use_dmub_lock(dc, pipe->stream->link)) { union dmub_hw_lock_flags hw_locks = { 0 }; struct dmub_hw_lock_inst_flags inst_flags = { 0 }; diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c index 9e33bf937a692..3c8eb1510226c 100644 --- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c +++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c @@ -876,7 +876,7 @@ bool dp_set_test_pattern( return false; if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) { - if (should_use_dmub_lock(pipe_ctx->stream->link)) { + if (should_use_dmub_lock(pipe_ctx->stream->link->dc, pipe_ctx->stream->link)) { union dmub_hw_lock_flags hw_locks = { 0 }; struct dmub_hw_lock_inst_flags inst_flags = { 0 }; @@ -924,7 +924,7 @@ bool dp_set_test_pattern( CRTC_STATE_VACTIVE); if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) { - if (should_use_dmub_lock(pipe_ctx->stream->link)) { + if (should_use_dmub_lock(pipe_ctx->stream->link->dc, pipe_ctx->stream->link)) { union dmub_hw_lock_flags hw_locks = { 0 }; struct dmub_hw_lock_inst_flags inst_flags = { 0 }; From 962813fc0bd9dd4166b8f57f1ebaa68f27ebd29c Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Wed, 17 Sep 2025 11:46:56 -0400 Subject: [PATCH 2155/2653] drm/amd/display: Rename should_use_dmub_lock to reflect inbox1 usage [Why] Newer DCN use the DMCUB HW lock via inbox0 for performance reasons while older ones will use inbox1. The should_use_dmub_lock() function does not describe whether the lock in general should be used, but whether it should be used via inbox1. [How] Rename the function to should_use_dmub_inbox1_lock() to reflect this. Reviewed-by: Alvin Lee Signed-off-by: Nicholas Kazlauskas Signed-off-by: Roman Li Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 2 +- drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h | 10 +++++++++- .../gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 2 +- .../gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 +- .../drm/amd/display/dc/link/accessories/link_dp_cts.c | 4 ++-- 6 files changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 9baa6b5c682b1..2e2095bba30b1 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -4150,7 +4150,7 @@ static void commit_planes_for_stream(struct dc *dc, if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) if (top_pipe_to_program && top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) { - if (should_use_dmub_lock(dc, stream->link)) { + if (should_use_dmub_inbox1_lock(dc, stream->link)) { union dmub_hw_lock_flags hw_locks = { 0 }; struct dmub_hw_lock_inst_flags inst_flags = { 0 }; @@ -4420,7 +4420,7 @@ static void commit_planes_for_stream(struct dc *dc, top_pipe_to_program->stream_res.tg, CRTC_STATE_VACTIVE); - if (should_use_dmub_lock(dc, stream->link)) { + if (should_use_dmub_inbox1_lock(dc, stream->link)) { union dmub_hw_lock_flags hw_locks = { 0 }; struct dmub_hw_lock_inst_flags inst_flags = { 0 }; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c index 17c30c5b16794..39f5fa73c43e6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c @@ -61,7 +61,7 @@ void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv, dc_dmub_srv_wait_for_inbox0_ack(dmub_srv); } -bool should_use_dmub_lock(const struct dc *dc, const struct dc_link *link) +bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link) { /* ASIC doesn't support DMUB */ if (!dc->ctx->dmub_srv) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h index 6e88638776869..9f53d2ea5fa59 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h @@ -37,6 +37,14 @@ void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv, void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_cmd_lock_hw hw_lock_cmd); -bool should_use_dmub_lock(const struct dc *dc, const struct dc_link *link); +/** + * should_use_dmub_inbox1_lock() - Checks if the DMCUB hardware lock via inbox1 should be used. + * + * @dc: pointer to DC object + * @link: optional pointer to the link object to check for enabled link features + * + * Return: true if the inbox1 lock should be used, false otherwise + */ +bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link); #endif /*_DMUB_HW_LOCK_MGR_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index cb915abac15a6..c88781de6d18a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -2245,7 +2245,7 @@ void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock) if (lock) delay_cursor_until_vupdate(dc, pipe); - if (pipe->stream && should_use_dmub_lock(dc, pipe->stream->link)) { + if (pipe->stream && should_use_dmub_inbox1_lock(dc, pipe->stream->link)) { union dmub_hw_lock_flags hw_locks = { 0 }; struct dmub_hw_lock_inst_flags inst_flags = { 0 }; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 650a1697557b2..cf9e8ce784ce1 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -1449,7 +1449,7 @@ void dcn20_pipe_control_lock( !flip_immediate) dcn20_setup_gsl_group_as_lock(dc, pipe, false); - if (pipe->stream && should_use_dmub_lock(dc, pipe->stream->link)) { + if (pipe->stream && should_use_dmub_inbox1_lock(dc, pipe->stream->link)) { union dmub_hw_lock_flags hw_locks = { 0 }; struct dmub_hw_lock_inst_flags inst_flags = { 0 }; diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c index 3c8eb1510226c..1593412354cf8 100644 --- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c +++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c @@ -876,7 +876,7 @@ bool dp_set_test_pattern( return false; if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) { - if (should_use_dmub_lock(pipe_ctx->stream->link->dc, pipe_ctx->stream->link)) { + if (should_use_dmub_inbox1_lock(pipe_ctx->stream->link->dc, pipe_ctx->stream->link)) { union dmub_hw_lock_flags hw_locks = { 0 }; struct dmub_hw_lock_inst_flags inst_flags = { 0 }; @@ -924,7 +924,7 @@ bool dp_set_test_pattern( CRTC_STATE_VACTIVE); if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) { - if (should_use_dmub_lock(pipe_ctx->stream->link->dc, pipe_ctx->stream->link)) { + if (should_use_dmub_inbox1_lock(pipe_ctx->stream->link->dc, pipe_ctx->stream->link)) { union dmub_hw_lock_flags hw_locks = { 0 }; struct dmub_hw_lock_inst_flags inst_flags = { 0 }; From 092c815371005a060df6b36efe5a8382eab15eec Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Wed, 17 Sep 2025 13:00:58 -0400 Subject: [PATCH 2156/2653] drm/amd/display: Rename FAMS2 global control lock to DMUB HW control lock [Why] FAMS2 dictates whether the inbox0 HW lock is required, but it is not the only feature that may determine this. In order to leverage the faster inbox0 HW lock in place of the inbox1 ringbuffer based control lock it's desirable to utilize the HWSS based locking protocol FAMS2 has already implemented. [How] Rename the FAMS2 global control lock to DMUB HW control lock. This is purely a refactor with no functional change, the logic that will determine which features need to enable this HW lock will be added in a future commit. Reviewed-by: Alvin Lee Signed-off-by: Nicholas Kazlauskas Signed-off-by: Roman Li Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 29 +++++++++---------- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 24 +++++++-------- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 18 ++++++------ .../amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 4 +-- .../amd/display/dc/hwss/dcn401/dcn401_init.c | 4 +-- .../drm/amd/display/dc/hwss/hw_sequencer.h | 10 +++---- 6 files changed, 44 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 2e2095bba30b1..e33fdf08c8f63 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2158,8 +2158,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c */ if (dc->hwss.subvp_pipe_control_lock) dc->hwss.subvp_pipe_control_lock(dc, context, true, true, NULL, subvp_prev_use); - if (dc->hwss.fams2_global_control_lock) - dc->hwss.fams2_global_control_lock(dc, context, true); + if (dc->hwss.dmub_hw_control_lock) + dc->hwss.dmub_hw_control_lock(dc, context, true); if (dc->hwss.update_dsc_pg) dc->hwss.update_dsc_pg(dc, context, false); @@ -2229,8 +2229,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c dc->hwss.commit_subvp_config(dc, context); if (dc->hwss.subvp_pipe_control_lock) dc->hwss.subvp_pipe_control_lock(dc, context, false, true, NULL, subvp_prev_use); - if (dc->hwss.fams2_global_control_lock) - dc->hwss.fams2_global_control_lock(dc, context, false); + if (dc->hwss.dmub_hw_control_lock) + dc->hwss.dmub_hw_control_lock(dc, context, false); for (i = 0; i < context->stream_count; i++) { const struct dc_link *link = context->streams[i]->link; @@ -4177,16 +4177,16 @@ static void commit_planes_for_stream(struct dc *dc, if (dc->hwss.subvp_pipe_control_lock) dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, NULL, subvp_prev_use); - if (dc->hwss.fams2_global_control_lock) - dc->hwss.fams2_global_control_lock(dc, context, true); + if (dc->hwss.dmub_hw_control_lock) + dc->hwss.dmub_hw_control_lock(dc, context, true); dc->hwss.interdependent_update_lock(dc, context, true); } else { if (dc->hwss.subvp_pipe_control_lock) dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use); - if (dc->hwss.fams2_global_control_lock) - dc->hwss.fams2_global_control_lock(dc, context, true); + if (dc->hwss.dmub_hw_control_lock) + dc->hwss.dmub_hw_control_lock(dc, context, true); /* Lock the top pipe while updating plane addrs, since freesync requires * plane addr update event triggers to be synchronized. @@ -4229,9 +4229,8 @@ static void commit_planes_for_stream(struct dc *dc, dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use); - if (dc->hwss.fams2_global_control_lock) - dc->hwss.fams2_global_control_lock(dc, context, false); - + if (dc->hwss.dmub_hw_control_lock) + dc->hwss.dmub_hw_control_lock(dc, context, false); return; } @@ -4468,13 +4467,13 @@ static void commit_planes_for_stream(struct dc *dc, if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) { if (dc->hwss.subvp_pipe_control_lock) dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use); - if (dc->hwss.fams2_global_control_lock) - dc->hwss.fams2_global_control_lock(dc, context, false); + if (dc->hwss.dmub_hw_control_lock) + dc->hwss.dmub_hw_control_lock(dc, context, false); } else { if (dc->hwss.subvp_pipe_control_lock) dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use); - if (dc->hwss.fams2_global_control_lock) - dc->hwss.fams2_global_control_lock(dc, context, false); + if (dc->hwss.dmub_hw_control_lock) + dc->hwss.dmub_hw_control_lock(dc, context, false); } // Fire manual trigger only when bottom plane is flipped diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index d82b1cb467f4b..25a07e5f4ed77 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -755,11 +755,11 @@ void hwss_build_fast_sequence(struct dc *dc, block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST; (*num_steps)++; } - if (dc->hwss.fams2_global_control_lock_fast) { - block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.dc = dc; - block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.lock = true; - block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context); - block_sequence[*num_steps].func = DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST; + if (dc->hwss.dmub_hw_control_lock_fast) { + block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc; + block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = true; + block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context); + block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST; (*num_steps)++; } if (dc->hwss.pipe_control_lock) { @@ -894,11 +894,11 @@ void hwss_build_fast_sequence(struct dc *dc, block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST; (*num_steps)++; } - if (dc->hwss.fams2_global_control_lock_fast) { - block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.dc = dc; - block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.lock = false; - block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context); - block_sequence[*num_steps].func = DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST; + if (dc->hwss.dmub_hw_control_lock_fast) { + block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc; + block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = false; + block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context); + block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST; (*num_steps)++; } @@ -1001,8 +1001,8 @@ void hwss_execute_sequence(struct dc *dc, params->wait_for_dcc_meta_propagation_params.dc, params->wait_for_dcc_meta_propagation_params.top_pipe_to_program); break; - case DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST: - dc->hwss.fams2_global_control_lock_fast(params); + case DMUB_HW_CONTROL_LOCK_FAST: + dc->hwss.dmub_hw_control_lock_fast(params); break; default: ASSERT(false); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 7c276c3190867..ab21da435a36d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1404,9 +1404,9 @@ void dcn401_prepare_bandwidth(struct dc *dc, } if (dc->debug.fams2_config.bits.enable) { - dcn401_fams2_global_control_lock(dc, context, true); + dcn401_dmub_hw_control_lock(dc, context, true); dcn401_fams2_update_config(dc, context, false); - dcn401_fams2_global_control_lock(dc, context, false); + dcn401_dmub_hw_control_lock(dc, context, false); } if (p_state_change_support != context->bw_ctx.bw.dcn.clk.p_state_change_support) { @@ -1425,9 +1425,9 @@ void dcn401_optimize_bandwidth( /* enable fams2 if needed */ if (dc->debug.fams2_config.bits.enable) { - dcn401_fams2_global_control_lock(dc, context, true); + dcn401_dmub_hw_control_lock(dc, context, true); dcn401_fams2_update_config(dc, context, true); - dcn401_fams2_global_control_lock(dc, context, false); + dcn401_dmub_hw_control_lock(dc, context, false); } /* program dchubbub watermarks */ @@ -1466,7 +1466,7 @@ void dcn401_optimize_bandwidth( } } -void dcn401_fams2_global_control_lock(struct dc *dc, +void dcn401_dmub_hw_control_lock(struct dc *dc, struct dc_state *context, bool lock) { @@ -1483,12 +1483,12 @@ void dcn401_fams2_global_control_lock(struct dc *dc, dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); } -void dcn401_fams2_global_control_lock_fast(union block_sequence_params *params) +void dcn401_dmub_hw_control_lock_fast(union block_sequence_params *params) { - struct dc *dc = params->fams2_global_control_lock_fast_params.dc; - bool lock = params->fams2_global_control_lock_fast_params.lock; + struct dc *dc = params->dmub_hw_control_lock_fast_params.dc; + bool lock = params->dmub_hw_control_lock_fast_params.lock; - if (params->fams2_global_control_lock_fast_params.is_required) { + if (params->dmub_hw_control_lock_fast_params.is_required) { union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h index 2621b7725267e..9591657d8eee3 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h @@ -73,11 +73,11 @@ void dcn401_optimize_bandwidth( struct dc *dc, struct dc_state *context); -void dcn401_fams2_global_control_lock(struct dc *dc, +void dcn401_dmub_hw_control_lock(struct dc *dc, struct dc_state *context, bool lock); void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable); -void dcn401_fams2_global_control_lock_fast(union block_sequence_params *params); +void dcn401_dmub_hw_control_lock_fast(union block_sequence_params *params); void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings); void dcn401_hardware_release(struct dc *dc); void dcn401_update_odm(struct dc *dc, struct dc_state *context, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c index d6e11b7e4fcef..a221b8cb6d4dd 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c @@ -95,9 +95,9 @@ static const struct hw_sequencer_funcs dcn401_funcs = { .apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom, .wait_for_dcc_meta_propagation = dcn401_wait_for_dcc_meta_propagation, .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless, - .fams2_global_control_lock = dcn401_fams2_global_control_lock, + .dmub_hw_control_lock = dcn401_dmub_hw_control_lock, .fams2_update_config = dcn401_fams2_update_config, - .fams2_global_control_lock_fast = dcn401_fams2_global_control_lock_fast, + .dmub_hw_control_lock_fast = dcn401_dmub_hw_control_lock_fast, .program_outstanding_updates = dcn401_program_outstanding_updates, .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, .detect_pipe_changes = dcn401_detect_pipe_changes, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index 1723bbcf2c46a..619ac4dfff078 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -148,7 +148,7 @@ struct wait_for_dcc_meta_propagation_params { const struct pipe_ctx *top_pipe_to_program; }; -struct fams2_global_control_lock_fast_params { +struct dmub_hw_control_lock_fast_params { struct dc *dc; bool is_required; bool lock; @@ -173,7 +173,7 @@ union block_sequence_params { struct set_ocsc_default_params set_ocsc_default_params; struct subvp_save_surf_addr subvp_save_surf_addr; struct wait_for_dcc_meta_propagation_params wait_for_dcc_meta_propagation_params; - struct fams2_global_control_lock_fast_params fams2_global_control_lock_fast_params; + struct dmub_hw_control_lock_fast_params dmub_hw_control_lock_fast_params; }; enum block_sequence_func { @@ -195,7 +195,7 @@ enum block_sequence_func { MPC_SET_OCSC_DEFAULT, DMUB_SUBVP_SAVE_SURF_ADDR, HUBP_WAIT_FOR_DCC_META_PROP, - DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST, + DMUB_HW_CONTROL_LOCK_FAST, /* This must be the last value in this enum, add new ones above */ HWSS_BLOCK_SEQUENCE_FUNC_COUNT }; @@ -452,13 +452,13 @@ struct hw_sequencer_funcs { const struct dc_state *new_ctx); void (*wait_for_dcc_meta_propagation)(const struct dc *dc, const struct pipe_ctx *top_pipe_to_program); - void (*fams2_global_control_lock)(struct dc *dc, + void (*dmub_hw_control_lock)(struct dc *dc, struct dc_state *context, bool lock); void (*fams2_update_config)(struct dc *dc, struct dc_state *context, bool enable); - void (*fams2_global_control_lock_fast)(union block_sequence_params *params); + void (*dmub_hw_control_lock_fast)(union block_sequence_params *params); void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max); void (*program_outstanding_updates)(struct dc *dc, struct dc_state *context); From 075903cfd80e6f92ad84888e472f8a39c5057cc5 Mon Sep 17 00:00:00 2001 From: Peichen Huang Date: Thu, 11 Sep 2025 13:41:16 +0800 Subject: [PATCH 2157/2653] drm/amd/display: lttpr cap should be nrd cap in bw_alloc mode [WHY] When bw allocation mode enabled, dpia may reports lttpr cap with reduced common cap. It would cause driver not start pre-training with max available bandwidth. [How] When bw allocation mode enabled, use NRD cap as lttpr cap. Reviewed-by: Cruise Hung Reviewed-by: Wenjing Liu Signed-off-by: Peichen Huang Signed-off-by: Roman Li Tested-by: Dan Wheeler --- .../dc/link/protocols/link_dp_capability.c | 38 ++++++++++++++++++- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 92ca475ca2d6c..e26d5f89e9d79 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -424,6 +424,21 @@ static enum dc_link_rate get_link_rate_from_max_link_bw( return link_rate; } +static enum dc_lane_count get_lttpr_max_lane_count(struct dc_link *link) +{ + enum dc_lane_count lttpr_max_lane_count = LANE_COUNT_UNKNOWN; + + if (link->dpcd_caps.lttpr_caps.max_lane_count <= LANE_COUNT_DP_MAX) + lttpr_max_lane_count = link->dpcd_caps.lttpr_caps.max_lane_count; + + /* if bw_allocation is enabled and nrd_max_lane_count is set, use it */ + if (link->dpia_bw_alloc_config.bw_alloc_enabled && + link->dpia_bw_alloc_config.nrd_max_lane_count > 0) + lttpr_max_lane_count = link->dpia_bw_alloc_config.nrd_max_lane_count; + + return lttpr_max_lane_count; +} + static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link) { @@ -438,6 +453,11 @@ static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link) break; } + /* if bw_allocation is enabled and nrd_max_link_rate is set, use it */ + if (link->dpia_bw_alloc_config.bw_alloc_enabled && + link->dpia_bw_alloc_config.nrd_max_link_rate > 0) + lttpr_max_link_rate = link->dpia_bw_alloc_config.nrd_max_link_rate; + if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR20) lttpr_max_link_rate = LINK_RATE_UHBR20; else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5) @@ -2242,6 +2262,7 @@ const struct dc_link_settings *dp_get_verified_link_cap( struct dc_link_settings dp_get_max_link_cap(struct dc_link *link) { struct dc_link_settings max_link_cap = {0}; + enum dc_lane_count lttpr_max_lane_count; enum dc_link_rate lttpr_max_link_rate; enum dc_link_rate cable_max_link_rate; struct resource_context *res_ctx = &link->dc->current_state->res_ctx; @@ -2306,8 +2327,11 @@ struct dc_link_settings dp_get_max_link_cap(struct dc_link *link) /* Some LTTPR devices do not report valid DPCD revisions, if so, do not take it's link cap into consideration. */ if (link->dpcd_caps.lttpr_caps.revision.raw >= DPCD_REV_14) { - if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count) - max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count; + lttpr_max_lane_count = get_lttpr_max_lane_count(link); + + if (lttpr_max_lane_count < max_link_cap.lane_count) + max_link_cap.lane_count = lttpr_max_lane_count; + lttpr_max_link_rate = get_lttpr_max_link_rate(link); if (lttpr_max_link_rate < max_link_cap.link_rate) @@ -2413,6 +2437,11 @@ bool dp_verify_link_cap_with_retries( dp_trace_detect_lt_init(link); + DC_LOG_HW_LINK_TRAINING("%s: Link[%d] LinkRate=0x%x LaneCount=%d", + __func__, link->link_index, + known_limit_link_setting->link_rate, + known_limit_link_setting->lane_count); + if (link->link_enc && link->link_enc->features.flags.bits.DP_IS_USB_C && link->dc->debug.usbc_combo_phy_reset_wa) apply_usbc_combo_phy_reset_wa(link, known_limit_link_setting); @@ -2449,6 +2478,11 @@ bool dp_verify_link_cap_with_retries( dp_trace_lt_fail_count_update(link, fail_count, true); dp_trace_set_lt_end_timestamp(link, true); + DC_LOG_HW_LINK_TRAINING("%s: Link[%d] Exit. is_success=%d fail_count=%d", + __func__, link->link_index, + success, + fail_count); + return success; } From 4d5595be20566fea6118e2989ce93edbc6df8d6e Mon Sep 17 00:00:00 2001 From: Fangzhi Zuo Date: Thu, 18 Sep 2025 16:25:45 -0400 Subject: [PATCH 2158/2653] drm/amd/display: Prevent Gating DTBCLK before It Is Properly Latched [why] 1. With allow_0_dtb_clk enabled, the time required to latch DTBCLK to 600 MHz depends on the SMU. If DTBCLK is not latched to 600 MHz before set_mode completes, gating DTBCLK causes the DP2 sink to lose its clock source. 2. The existing DTBCLK gating sequence ungates DTBCLK based on both pix_clk and ref_dtbclk, but gates DTBCLK when either pix_clk or ref_dtbclk is zero. pix_clk can be zero outside the set_mode sequence before DTBCLK is properly latched, which can lead to DTBCLK being gated by mistake. [how] Consider both pixel_clk and ref_dtbclk when determining when it is safe to gate DTBCLK; this is more accurate. Reviewed-by: Charlene Liu Reviewed-by: Aurabindo Pillai Signed-off-by: Fangzhi Zuo Signed-off-by: Roman Li Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 4 +++- drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index b11383fba35f1..1eb04772f5da2 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -394,6 +394,8 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, display_count = dcn35_get_active_display_cnt_wa(dc, context, &all_active_disps); if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz) new_clocks->ref_dtbclk_khz = 600000; + else if (!new_clocks->dtbclk_en && new_clocks->ref_dtbclk_khz > 590000) + new_clocks->ref_dtbclk_khz = 0; /* * if it is safe to lower, but we are already in the lower state, we don't have to do anything @@ -435,7 +437,7 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, actual_dtbclk = REG_READ(CLK1_CLK4_CURRENT_CNT); - if (actual_dtbclk) { + if (actual_dtbclk > 590000) { clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz; clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; } diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index de6d62401362e..c899c09ea31b8 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -1411,7 +1411,7 @@ static void dccg35_set_dtbclk_dto( __func__, params->otg_inst, params->pixclk_khz, params->ref_dtbclk_khz, req_dtbclk_khz, phase, modulo); - } else { + } else if (!params->ref_dtbclk_khz && !req_dtbclk_khz) { switch (params->otg_inst) { case 0: REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 0); From 10028de2dd756a2d7d53e5c00830a36a35e52151 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 19 Sep 2025 16:22:48 -0400 Subject: [PATCH 2159/2653] drm/amd/display: [FW Promotion] Release 0.1.29.0 Add new interface for offloading cursor programming to DMUB. Reviewed-by: Sun peng (Leo) Li Signed-off-by: Taimur Hassan Signed-off-by: Roman Li Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 204 +++++++++++++++++- 1 file changed, 203 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 4e6290f19fe7c..9d2a02bd00e28 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -629,6 +629,112 @@ struct dmub_visual_confirm_color { uint16_t panel_inst; }; +/** + * struct dmub_cursor_offload_pipe_data_dcn30_v1 - DCN30+ per pipe data. + */ +struct dmub_cursor_offload_pipe_data_dcn30_v1 { + uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS; + uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH; + uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16; + uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16; + uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16; + uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16; + uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16; + uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16; + uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13; + uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1; + uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3; + uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1; + uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2; + uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5; + uint32_t reserved0[4]; + uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1; + uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3; + uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1; + uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1; + uint32_t CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24; + uint32_t CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24; + uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS : 16; + uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE, : 16; + uint32_t reserved1[5]; + uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8; + uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8; + uint32_t reserved2[3]; +}; + +/** + * struct dmub_cursor_offload_pipe_data_dcn401_v1 - DCN401 per pipe data. + */ +struct dmub_cursor_offload_pipe_data_dcn401_v1 { + uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS; + uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH; + uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16; + uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16; + uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16; + uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16; + uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16; + uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16; + uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13; + uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1; + uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3; + uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1; + uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2; + uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5; + uint32_t reserved0[4]; + uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1; + uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3; + uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1; + uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1; + uint32_t CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24; + uint32_t CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24; + uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y : 16; + uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y, : 16; + uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB : 16; + uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB : 16; + uint32_t reserved1[4]; + uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8; + uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8; + uint32_t HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR : 1; + uint32_t reserved2[3]; +}; + +/** + * struct dmub_cursor_offload_pipe_data_v1 - Per pipe data for cursor offload. + */ +struct dmub_cursor_offload_pipe_data_v1 { + union { + struct dmub_cursor_offload_pipe_data_dcn30_v1 dcn30; /**< DCN30 cursor data. */ + struct dmub_cursor_offload_pipe_data_dcn401_v1 dcn401; /**< DCN401 cursor data. */ + uint8_t payload[96]; /**< Guarantees the cursor pipe data size per-pipe. */ + }; +}; + +/** + * struct dmub_cursor_offload_payload_data_v1 - A payload of stream data. + */ +struct dmub_cursor_offload_payload_data_v1 { + uint32_t write_idx_start; /**< Write index, updated before pipe_data is written. */ + uint32_t write_idx_finish; /**< Write index, updated after pipe_data is written. */ + uint32_t pipe_mask; /**< Mask of pipes to update. */ + uint32_t reserved; /**< Reserved for future use. */ + struct dmub_cursor_offload_pipe_data_v1 pipe_data[6]; /**< Per-pipe cursor data. */ +}; + +/** + * struct dmub_cursor_offload_stream_v1 - Per-stream data for cursor offload. + */ +struct dmub_cursor_offload_stream_v1 { + struct dmub_cursor_offload_payload_data_v1 payloads[4]; /**< A small buffer of cursor payloads. */ + uint32_t write_idx; /**< The index of the last written payload. */ +}; + +/** + * struct dmub_cursor_offload_v1 - Cursor offload feature state. + */ +struct dmub_cursor_offload_v1 { + struct dmub_cursor_offload_stream_v1 offload_streams[6]; /**< Per-stream cursor offload data */ +}; + //============================================================================== //================================================================= //============================================================================== @@ -648,7 +754,8 @@ struct dmub_visual_confirm_color { union dmub_fw_meta_feature_bits { struct { uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ - uint32_t reserved : 31; + uint32_t cursor_offload_v1_support: 1; /**< 1 supports cursor offload */ + uint32_t reserved : 30; } bits; /**< status bits */ uint32_t all; /**< 32-bit access to status bits */ }; @@ -813,6 +920,28 @@ enum dmub_ips_comand_type { DMUB_CMD__IPS_QUERY_RESIDENCY_INFO = 1, }; +/** + * enum dmub_cursor_offload_comand_type - Cursor offload subcommands. + */ +enum dmub_cursor_offload_comand_type { + /** + * Initializes the cursor offload feature. + */ + DMUB_CMD__CURSOR_OFFLOAD_INIT = 0, + /** + * Enables cursor offloading for a stream and updates the timing parameters. + */ + DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE = 1, + /** + * Disables cursor offloading for a given stream. + */ + DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE = 2, + /** + * Programs the latest data for a given stream. + */ + DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM = 3, +}; + /** * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 */ @@ -877,6 +1006,7 @@ enum dmub_shared_state_feature_id { DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, + DMUB_SHARED_STATE_FEATURE__CURSOR_OFFLOAD_V1 = 4, DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ }; @@ -957,6 +1087,22 @@ struct dmub_shared_state_ips_driver { uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ }; /* 248-bytes, fixed */ +/** + * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload. + */ +struct dmub_shared_state_cursor_offload_stream_v1 { + uint32_t last_write_idx; /**< Last write index */ + uint8_t reserved[28]; /**< Reserved bytes. */ +}; /* 32-bytes, fixed */ + +/** + * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload. + */ +struct dmub_shared_state_cursor_offload_v1 { + struct dmub_shared_state_cursor_offload_stream_v1 offload_streams[6]; /**< stream state, 32-bytes each */ + uint8_t reserved[56]; /**< reserved for future use */ +}; /* 248-bytes, fixed */ + /** * enum dmub_shared_state_feature_common - Generic payload. */ @@ -983,6 +1129,7 @@ struct dmub_shared_state_feature_block { struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ + struct dmub_shared_state_cursor_offload_v1 cursor_offload_v1; /**< Cursor offload */ } data; /**< Shared state data. */ }; /* 256-bytes, fixed */ @@ -1572,6 +1719,14 @@ enum dmub_cmd_type { */ DMUB_CMD__IPS = 91, + /** + * Command type use for Cursor offload. + */ + DMUB_CMD__CURSOR_OFFLOAD = 92, + + /** + * Command type use for VBIOS shared commands. + */ DMUB_CMD__VBIOS = 128, }; @@ -4664,6 +4819,7 @@ enum hw_lock_client { */ HW_LOCK_CLIENT_REPLAY = 4, HW_LOCK_CLIENT_FAMS2 = 5, + HW_LOCK_CLIENT_CURSOR_OFFLOAD = 6, /** * Invalid client. */ @@ -6075,6 +6231,40 @@ struct dmub_rb_cmd_ips_query_residency_info { struct dmub_cmd_ips_query_residency_info_data info_data; }; +/** + * struct dmub_cmd_cursor_offload_init_data - Payload for cursor offload init command. + */ +struct dmub_cmd_cursor_offload_init_data { + union dmub_addr state_addr; /**< State address for dmub_cursor_offload */ + uint32_t state_size; /**< State size for dmub_cursor_offload */ +}; + +/** + * struct dmub_rb_cmd_cursor_offload_init - Data for initializing cursor offload. + */ +struct dmub_rb_cmd_cursor_offload_init { + struct dmub_cmd_header header; + struct dmub_cmd_cursor_offload_init_data init_data; +}; + +/** + * struct dmub_cmd_cursor_offload_stream_data - Payload for cursor offload stream command. + */ +struct dmub_cmd_cursor_offload_stream_data { + uint32_t otg_inst: 4; /**< OTG instance to control */ + uint32_t reserved: 28; /**< Reserved for future use */ + uint32_t line_time_in_ns; /**< Line time in ns for the OTG */ + uint32_t v_total_max; /**< OTG v_total_max */ +}; + +/** + * struct dmub_rb_cmd_cursor_offload_stream_cntl - Controls a stream for cursor offload. + */ +struct dmub_rb_cmd_cursor_offload_stream_cntl { + struct dmub_cmd_header header; + struct dmub_cmd_cursor_offload_stream_data data; +}; + /** * union dmub_rb_cmd - DMUB inbox command. */ @@ -6404,6 +6594,18 @@ union dmub_rb_cmd { struct dmub_rb_cmd_ips_residency_cntl ips_residency_cntl; struct dmub_rb_cmd_ips_query_residency_info ips_query_residency_info; + /** + * Definition of a DMUB_CMD__CURSOR_OFFLOAD_INIT command. + */ + struct dmub_rb_cmd_cursor_offload_init cursor_offload_init; + /** + * Definition of a DMUB_CMD__CURSOR_OFFLOAD control commands. + * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE + * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE + * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM + * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_UPDATE_DRR + */ + struct dmub_rb_cmd_cursor_offload_stream_cntl cursor_offload_stream_ctnl; }; /** From 88e213ba1966a1659322196c55dbba31ab2d4853 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 19 Sep 2025 17:20:17 -0500 Subject: [PATCH 2160/2653] drm/amd/display: Promote DC to 3.2.352 - Fix slice width calculation for YCbCr420 - Fix DTBCLK gating - Use NRD cap as lttpr cap - Consolidate DML2 FP guards - DML2.1 Update - Firmware Release 0.1.29.0 changes Reviewed-by: Sun peng (Leo) Li Signed-off-by: Taimur Hassan Signed-off-by: Roman Li Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5d7eeca78c02f..f5208a070a915 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.351" +#define DC_VER "3.2.352" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From fdfda020be716b0542c3917930b537d83898a3be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 25 Sep 2025 20:45:23 +0200 Subject: [PATCH 2161/2653] drm/amd/display: Properly clear SCL_*_FILTER_CONTROL on DCE6 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Previously, the code would set a bit field which didn't exist on DCE6 so it would be effectively a no-op. Fixes: b70aaf5586f2 ("drm/amd/display: dce_transform: add DCE6 specific macros,functions") Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index 2b1673d69ea83..e5c2fb134d14d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -527,8 +527,7 @@ static void dce60_transform_set_scaler( if (coeffs_v != xfm_dce->filter_v || coeffs_h != xfm_dce->filter_h) { /* 4. Program vertical filters */ if (xfm_dce->filter_v == NULL) - REG_SET(SCL_VERT_FILTER_CONTROL, 0, - SCL_V_2TAP_HARDCODE_COEF_EN, 0); + REG_WRITE(SCL_VERT_FILTER_CONTROL, 0); program_multi_taps_filter( xfm_dce, data->taps.v_taps, @@ -542,8 +541,7 @@ static void dce60_transform_set_scaler( /* 5. Program horizontal filters */ if (xfm_dce->filter_h == NULL) - REG_SET(SCL_HORZ_FILTER_CONTROL, 0, - SCL_H_2TAP_HARDCODE_COEF_EN, 0); + REG_WRITE(SCL_HORZ_FILTER_CONTROL, 0); program_multi_taps_filter( xfm_dce, data->taps.h_taps, From 34df87a3a487026bb74904b012a4abd4b562be2c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 25 Sep 2025 20:45:24 +0200 Subject: [PATCH 2162/2653] drm/amd/display: Properly disable scaling on DCE6 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SCL_SCALER_ENABLE can be used to enable/disable the scaler on DCE6. Program it to 0 when scaling isn't used, 1 when used. Additionally, clear some other registers when scaling is disabled and program the SCL_UPDATE register as recommended. This fixes visible glitches for users whose BIOS sets up a mode with scaling at boot, which DC was unable to clean up. Fixes: b70aaf5586f2 ("drm/amd/display: dce_transform: add DCE6 specific macros,functions") Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dce/dce_transform.c | 15 +++++++++++---- .../gpu/drm/amd/display/dc/dce/dce_transform.h | 2 ++ 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index e5c2fb134d14d..1ab5ae9b5ea51 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -154,10 +154,13 @@ static bool dce60_setup_scaling_configuration( REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0); if (data->taps.h_taps + data->taps.v_taps <= 2) { - /* Set bypass */ - - /* DCE6 has no SCL_MODE register, skip scale mode programming */ + /* Disable scaler functionality */ + REG_WRITE(SCL_SCALER_ENABLE, 0); + /* Clear registers that can cause glitches even when the scaler is off */ + REG_WRITE(SCL_TAP_CONTROL, 0); + REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0); + REG_WRITE(SCL_F_SHARP_CONTROL, 0); return false; } @@ -165,7 +168,7 @@ static bool dce60_setup_scaling_configuration( SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1, SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1); - /* DCE6 has no SCL_MODE register, skip scale mode programming */ + REG_WRITE(SCL_SCALER_ENABLE, 1); /* DCE6 has no SCL_BOUNDARY_MODE bit, skip replace out of bound pixels */ @@ -502,6 +505,8 @@ static void dce60_transform_set_scaler( REG_SET(DC_LB_MEM_SIZE, 0, DC_LB_MEM_SIZE, xfm_dce->lb_memory_size); + REG_WRITE(SCL_UPDATE, 0x00010000); + /* Clear SCL_F_SHARP_CONTROL value to 0 */ REG_WRITE(SCL_F_SHARP_CONTROL, 0); @@ -564,6 +569,8 @@ static void dce60_transform_set_scaler( /* DCE6 has no SCL_COEF_UPDATE_COMPLETE bit to flip to new coefficient memory */ /* DCE6 DATA_FORMAT register does not support ALPHA_EN */ + + REG_WRITE(SCL_UPDATE, 0); } #endif diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h index ff746fba850bc..eb716e8337e23 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h @@ -155,6 +155,7 @@ SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \ SRI(VIEWPORT_START, SCL, id), \ SRI(VIEWPORT_SIZE, SCL, id), \ + SRI(SCL_SCALER_ENABLE, SCL, id), \ SRI(SCL_HORZ_FILTER_INIT_RGB_LUMA, SCL, id), \ SRI(SCL_HORZ_FILTER_INIT_CHROMA, SCL, id), \ SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \ @@ -592,6 +593,7 @@ struct dce_transform_registers { uint32_t SCL_VERT_FILTER_SCALE_RATIO; uint32_t SCL_HORZ_FILTER_INIT; #if defined(CONFIG_DRM_AMD_DC_SI) + uint32_t SCL_SCALER_ENABLE; uint32_t SCL_HORZ_FILTER_INIT_RGB_LUMA; uint32_t SCL_HORZ_FILTER_INIT_CHROMA; #endif From 8368e816661095eedd3157cb4db1d6b5c6a40699 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 25 Sep 2025 20:45:25 +0200 Subject: [PATCH 2163/2653] drm/amd/display: Disable scaling on DCE6 for now MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Scaling doesn't work on DCE6 at the moment, the current register programming produces incorrect output when using fractional scaling (between 100-200%) on resolutions higher than 1080p. Disable it until we figure out how to program it properly. Fixes: 7c15fd86aaec ("drm/amd/display: dc/dce: add initial DCE6 support (v10)") Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c index 53c67ebe779ff..b75be6ad64f6c 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c @@ -404,13 +404,13 @@ static const struct dc_plane_cap plane_cap = { }, .max_upscale_factor = { - .argb8888 = 16000, + .argb8888 = 1, .nv12 = 1, .fp16 = 1 }, .max_downscale_factor = { - .argb8888 = 250, + .argb8888 = 1, .nv12 = 1, .fp16 = 1 } From 58afd13fa73a7822f8a40e104b9ba3fa2f774075 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 25 Sep 2025 14:10:57 -0500 Subject: [PATCH 2164/2653] drm/amd: Check whether secure display TA loaded successfully [Why] Not all renoir hardware supports secure display. If the TA is present but the feature isn't supported it will fail to load or send commands. This shows ERR messages to the user that make it seems like there is a problem. [How] Check the resp_status of the context to see if there was an error before trying to send any secure display commands. Reviewed-by: Alex Deucher Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/1415 Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 5e6040d901bd3..0ac7fa2794edc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -2352,7 +2352,7 @@ static int psp_securedisplay_initialize(struct psp_context *psp) } ret = psp_ta_load(psp, &psp->securedisplay_context.context); - if (!ret) { + if (!ret && !psp->securedisplay_context.context.resp_status) { psp->securedisplay_context.context.initialized = true; mutex_init(&psp->securedisplay_context.mutex); } else From 6727b0196b00be6f73b1061d48f5e12e1e28bec7 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Thu, 25 Sep 2025 18:02:18 +0800 Subject: [PATCH 2165/2653] drm/amdgpu: Merge amdgpu_vm_set_pasid into amdgpu_vm_init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As KFD no longer uses a separate PASID, the global amdgpu_vm_set_pasid()function is no longer necessary. Merge its functionality directly intoamdgpu_vm_init() to simplify code flow and eliminate redundant locking. v2: remove superflous check adjust amdgpu_vm_fin and remove amdgpu_vm_set_pasid (Chritian) v3: drop amdgpu_vm_assert_locked (Chritian) Reviewed-by: Christian König . Suggested-by: Christian König Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 +--- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 80 +++++++------------------ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 5 +- 3 files changed, 24 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 517583e17875c..6510d59421cc1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1464,14 +1464,10 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) amdgpu_debugfs_vm_init(file_priv); - r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id); + r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id, pasid); if (r) goto error_pasid; - r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); - if (r) - goto error_vm; - fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); if (!fpriv->prt_va) { r = -ENOMEM; @@ -1513,10 +1509,8 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) amdgpu_vm_fini(adev, &fpriv->vm); error_pasid: - if (pasid) { + if (pasid) amdgpu_pasid_free(pasid); - amdgpu_vm_set_pasid(adev, &fpriv->vm, 0); - } kfree(fpriv); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 5112168a8caa7..33e3bdd4e5609 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -138,63 +138,6 @@ static void amdgpu_vm_assert_locked(struct amdgpu_vm *vm) dma_resv_assert_held(vm->root.bo->tbo.base.resv); } -/** - * amdgpu_vm_set_pasid - manage pasid and vm ptr mapping - * - * @adev: amdgpu_device pointer - * @vm: amdgpu_vm pointer - * @pasid: the pasid the VM is using on this GPU - * - * Set the pasid this VM is using on this GPU, can also be used to remove the - * pasid by passing in zero. - * - */ -int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, - u32 pasid) -{ - int r = 0; - - amdgpu_vm_assert_locked(vm); - -#ifdef HAVE_STRUCT_XARRAY - if (vm->pasid == pasid) - return 0; - - if (vm->pasid) { - r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid)); - if (r < 0) - return r; - - vm->pasid = 0; - } - - if (pasid) { - r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm, - GFP_KERNEL)); - if (r < 0) - return r; - - vm->pasid = pasid; - } -#else - unsigned long flags; - - spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); - if (pasid) { - r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, - GFP_ATOMIC); - } else if (vm->pasid) { - idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); - } - spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); - if (r < 0) - return r; - vm->pasid = pasid; -#endif - - return 0; -} - /** * amdgpu_vm_bo_evicted - vm_bo is evicted * @@ -2600,6 +2543,7 @@ void amdgpu_vm_set_task_info(struct amdgpu_vm *vm) * @adev: amdgpu_device pointer * @vm: requested vm * @xcp_id: GPU partition selection id + * @pasid: the pasid the VM is using on this GPU * * Init @vm fields. * @@ -2607,7 +2551,7 @@ void amdgpu_vm_set_task_info(struct amdgpu_vm *vm) * 0 for success, error for failure. */ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, - int32_t xcp_id) + int32_t xcp_id, uint32_t pasid) { struct amdgpu_bo *root_bo; struct amdgpu_bo_vm *root; @@ -2688,12 +2632,26 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, if (r) dev_dbg(adev->dev, "Failed to create task info for VM\n"); + /* Store new PASID in XArray (if non-zero) */ + if (pasid != 0) { + r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm, GFP_KERNEL)); + if (r < 0) + goto error_free_root; + + vm->pasid = pasid; + } + amdgpu_bo_unreserve(vm->root.bo); amdgpu_bo_unref(&root_bo); return 0; error_free_root: + /* If PASID was partially set, erase it from XArray before failing */ + if (vm->pasid != 0) { + xa_erase_irq(&adev->vm_manager.pasids, vm->pasid); + vm->pasid = 0; + } amdgpu_vm_pt_free_root(adev, vm); amdgpu_bo_unreserve(vm->root.bo); amdgpu_bo_unref(&root_bo); @@ -2799,7 +2757,11 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) root = amdgpu_bo_ref(vm->root.bo); amdgpu_bo_reserve(root, true); - amdgpu_vm_set_pasid(adev, vm, 0); + /* Remove PASID mapping before destroying VM */ + if (vm->pasid != 0) { + xa_erase_irq(&adev->vm_manager.pasids, vm->pasid); + vm->pasid = 0; + } dma_fence_wait(vm->last_unlocked, false); dma_fence_put(vm->last_unlocked); dma_fence_wait(vm->last_tlb_flush, false); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index a4461753a4844..8cc74a30af1bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -512,11 +512,8 @@ extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; void amdgpu_vm_manager_init(struct amdgpu_device *adev); void amdgpu_vm_manager_fini(struct amdgpu_device *adev); -int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, - u32 pasid); - long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); -int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id); +int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id, uint32_t pasid); int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec, From 594f4e1295a82821ac0a0ad7ad569a4d9578fea1 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Wed, 3 Sep 2025 20:03:52 -0400 Subject: [PATCH 2166/2653] amdgpu/amdkfd: peerdirect support address lookup Add look-up for the BO by address. This is required for memory allocations where the virtual address are reserved outside of KFD and then later mapped to GPU memory. Signed-off-by: David Yat Sin Reviewed-by: Felix Kuehling ' --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 16 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 + drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 67 ++++++++++++++------- 3 files changed, 64 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 8a29165344f43..1aa96a244af0e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2749,6 +2749,22 @@ int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) vma->vm_ops = &amdgpu_ttm_vm_ops; return 0; } + +/* This function should be called with mm lock held */ +bool amdgpu_vma_is_amdgpu_bo(struct vm_area_struct *vma) +{ + if (vma->vm_ops == &amdgpu_ttm_vm_ops) + return true; + + return false; +} +#else +bool amdgpu_vma_is_amdgpu_bo(struct vm_area_struct *vma) +{ + pr_err_once("bo from address verification not supported\n"); + + return false; +} #endif /* HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 2a81a7dd10f43..58705a9d0bff1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -175,6 +175,9 @@ int amdgpu_ttm_init(struct amdgpu_device *adev); void amdgpu_ttm_fini(struct amdgpu_device *adev); void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable); + +bool amdgpu_vma_is_amdgpu_bo(struct vm_area_struct *vma); + int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, uint64_t dst_offset, uint32_t byte_count, struct dma_resv *resv, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index 09461f004377e..f7cd9661d5047 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -171,8 +171,12 @@ static int amd_acquire(unsigned long addr, size_t size, char *peer_mem_name, void **client_context) { struct kfd_process *p; - struct kfd_bo *buf_obj; struct amd_mem_context *mem_context; + struct kfd_bo *buf_obj = NULL; + struct kfd_node *dev = NULL; + struct amdgpu_bo *bo = NULL; + unsigned long offset = 0; + uint32_t flags = 0; if (peer_mem_name == rdma_name) { p = peer_mem_private_data; @@ -187,34 +191,54 @@ static int amd_acquire(unsigned long addr, size_t size, align_addr_size(&addr, &size); mutex_lock(&p->mutex); - buf_obj = kfd_process_find_bo_from_interval(p, addr, - addr + size - 1); - if (!buf_obj) { - pr_debug("Cannot find a kfd_bo for the range\n"); - goto out_unlock; - } + buf_obj = kfd_process_find_bo_from_interval(p, addr, addr + size - 1); + if (buf_obj) { + offset = addr - buf_obj->it.start; + bo = amdgpu_amdkfd_gpuvm_get_bo_ref(buf_obj->mem, &flags); - /* Initialize context used for operation with given address */ - mem_context = kzalloc(sizeof(*mem_context), GFP_KERNEL); - if (!mem_context) - goto out_unlock; + dev = buf_obj->dev; + } else { + struct vm_area_struct *vma; + struct amdgpu_device *adev; + + mmap_read_lock(p->mm); + vma = find_vma(p->mm, addr); + + if (!vma || + !amdgpu_vma_is_amdgpu_bo(vma) || + vma->vm_start > addr || + vma->vm_end < addr + size) { + mmap_read_unlock(p->mm); + goto out_unlock; + } - mem_context->pid = p->lead_thread->pid; + bo = ttm_to_amdgpu_bo(vma->vm_private_data); + drm_gem_object_get(&bo->tbo.base); + mmap_read_unlock(p->mm); - pr_debug("addr: %#lx, size: %#lx, pid: %d\n", - addr, size, mem_context->pid); + offset = addr - vma->vm_start; - mem_context->va = addr; - mem_context->size = size; - mem_context->offset = addr - buf_obj->it.start; + flags = bo->kfd_bo->alloc_flags; + adev = amdgpu_ttm_adev(bo->tbo.bdev); + dev = adev->kfd.dev->nodes[bo->xcp_id]; + } - mem_context->bo = amdgpu_amdkfd_gpuvm_get_bo_ref(buf_obj->mem, - &mem_context->flags); - mem_context->dev = buf_obj->dev; + mem_context = kzalloc(sizeof(*mem_context), GFP_KERNEL); + if (unlikely(!mem_context)) { + drm_gem_object_put(&bo->tbo.base); + goto out_unlock; + } mutex_unlock(&p->mutex); + pr_debug("addr: %#lx, size: %#lx, pid: %d\n", addr, size, mem_context->pid); - pr_debug("Client context: 0x%p\n", mem_context); + mem_context->pid = p->lead_thread->pid; + mem_context->va = addr; + mem_context->size = size; + mem_context->dev = dev; + mem_context->offset = offset; + mem_context->bo = bo; + mem_context->flags = flags; /* Return pointer to allocated context */ *client_context = mem_context; @@ -223,7 +247,6 @@ static int amd_acquire(unsigned long addr, size_t size, * by AMD GPU driver */ return 1; - out_unlock: mutex_unlock(&p->mutex); return 0; From e6461c53f3e0c808d73bc7ab2b3db6e9b07fc088 Mon Sep 17 00:00:00 2001 From: Shaoyun Liu Date: Wed, 24 Sep 2025 21:40:57 -0400 Subject: [PATCH 2167/2653] drm/amd/amdgpu: Fix the mes version that support inv_tlbs MES version 0x83 is not stable to use the inv_tlbs API. Defer it to 0x84 vertsion. Signed-off-by: Shaoyun Liu Reviewed-by: Michael Chen --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 404cc8c2ff2c1..f4a19357ccbc6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -337,7 +337,7 @@ static void gmc_v12_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, int vmid, i; if (adev->enable_uni_mes && adev->mes.ring[AMDGPU_MES_SCHED_PIPE].sched.ready && - (adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x83) { + (adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x84) { struct mes_inv_tlbs_pasid_input input = {0}; input.pasid = pasid; input.flush_type = flush_type; From 2f8ab8fe0731b62e457c8133ef84cf6d4c58d94c Mon Sep 17 00:00:00 2001 From: Yang Su Date: Mon, 29 Sep 2025 10:52:21 +0800 Subject: [PATCH 2168/2653] Bump AMDGPU version to 6.16.5 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index b4639482f6eb3..1add5a27e2584 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.16.4) +AC_INIT(amdgpu-dkms, 6.16.5) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From a8157f363f1db85f693a785212efa2478cf7d1b0 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Tue, 30 Sep 2025 14:29:12 +0800 Subject: [PATCH 2169/2653] Bump AMDGPU version to 6.16.6 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 1add5a27e2584..7e7df2e411476 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.16.5) +AC_INIT(amdgpu-dkms, 6.16.6) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From a54b254ac36ab8fd8865c934079d5ee3d0deb464 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Sat, 4 Oct 2025 22:39:24 +0800 Subject: [PATCH 2170/2653] drm/amd/pm: Disable VCN queue reset on SMU v13.0.6 due to regression Disable VCN reset capability for the program 4 as it's causing regressions. Reviewed-by: Lijo Lazar Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index c2bb578150fbf..6f70ea756ce1a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -458,8 +458,7 @@ static void smu_v13_0_6_init_caps(struct smu_context *smu) ((pgm == 4) && (fw_ver >= 0x4557000))) smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET)); - if (((pgm == 0) && (fw_ver >= 0x00558200)) || - ((pgm == 4) && (fw_ver >= 0x04557100))) + if ((pgm == 0) && (fw_ver >= 0x00558200)) smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET)); } From a03cb4b9d80776f3833fa4b70d001444097b0f70 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Sat, 4 Oct 2025 22:39:24 +0800 Subject: [PATCH 2171/2653] drm/amd/pm: Disable VCN queue reset on SMU v13.0.6 due to regression Disable VCN reset capability for the program 4 as it's causing regressions. Reviewed-by: Lijo Lazar Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index c2bb578150fbf..6f70ea756ce1a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -458,8 +458,7 @@ static void smu_v13_0_6_init_caps(struct smu_context *smu) ((pgm == 4) && (fw_ver >= 0x4557000))) smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET)); - if (((pgm == 0) && (fw_ver >= 0x00558200)) || - ((pgm == 4) && (fw_ver >= 0x04557100))) + if ((pgm == 0) && (fw_ver >= 0x00558200)) smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET)); } From 3bd25643d3ca11550e12e5046fa5ab5a1a3189d3 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 19 Sep 2025 11:04:44 +0530 Subject: [PATCH 2172/2653] drm/amd/pm: Avoid interface mismatch messaging PMFW interface version is not used by some IP implementations like SMU v13.0.6/12, instead rely on PMFW version checks. Avoid the log if interface version is not used. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 ++- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 2 ++ 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index b8e6169481c4d..f32ccc9108647 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -288,7 +288,8 @@ int smu_v13_0_check_fw_version(struct smu_context *smu) * Considering above, we just leave user a verbal message instead * of halt driver loading. */ - if (if_version != smu->smc_driver_if_version) { + if (smu->smc_driver_if_version != SMU_IGNORE_IF_VERSION && + if_version != smu->smc_driver_if_version) { dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n", smu->smc_driver_if_version, if_version, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 6f70ea756ce1a..465333bc298d7 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -4102,7 +4102,7 @@ void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu) smu->feature_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ? smu_v13_0_12_feature_mask_map : smu_v13_0_6_feature_mask_map; smu->table_map = smu_v13_0_6_table_map; - smu->smc_driver_if_version = SMU13_0_6_DRIVER_IF_VERSION; + smu->smc_driver_if_version = SMU_IGNORE_IF_VERSION; smu->smc_fw_caps |= SMU_FW_CAP_RAS_PRI; smu_v13_0_set_smu_mailbox_registers(smu); smu_v13_0_6_set_temp_funcs(smu); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h index d588f74b98de3..0ae91c8b6d72d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h @@ -40,6 +40,8 @@ #define SMU_IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL 0x8 #define SMU_IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY 0x9 +#define SMU_IGNORE_IF_VERSION 0xFFFFFFFF + #define smu_cmn_init_soft_gpu_metrics(ptr, frev, crev) \ do { \ typecheck(struct gpu_metrics_v##frev##_##crev *, (ptr)); \ From 00eaa73259b0a9fa9eb13ed1f86703d5883b0d74 Mon Sep 17 00:00:00 2001 From: Clay King Date: Mon, 22 Sep 2025 10:33:21 -0400 Subject: [PATCH 2173/2653] drm/amd/display: Remove inaccessible URL [WHAT] Remove inaccessible link. Reviewed-by: Joshua Aberback Signed-off-by: Clay King Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c index e2740482e1cfb..08ea0a1b9e7fe 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c @@ -73,8 +73,6 @@ * On any mode switch, if the new reg values are smaller than the current values, * then update the regs with the new values. * - * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142 - * */ void apply_DEDCN21_142_wa_for_hostvm_deadline( struct hubp *hubp, From f59f73b1ce89e188d6211d20f81546bbd43eac2f Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Wed, 24 Sep 2025 09:27:35 -0600 Subject: [PATCH 2174/2653] drm/amd/display: Remove comparing uint32_t to zero [WHAT] These *bypass are uint32_t and they will never be less than zero. Reviewed-by: Aurabindo Pillai Signed-off-by: Alex Hung --- .../drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c | 8 ++++---- .../gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c index 9e63fa72101cc..db687a13174d5 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c @@ -509,16 +509,16 @@ void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_b regs_and_bypass->dtbclk = internal.CLK1_CLK4_CURRENT_CNT / 10; regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007; - if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4) + if (regs_and_bypass->dppclk_bypass > 4) regs_and_bypass->dppclk_bypass = 0; regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007; - if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4) + if (regs_and_bypass->dcfclk_bypass > 4) regs_and_bypass->dcfclk_bypass = 0; regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007; - if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4) + if (regs_and_bypass->dispclk_bypass > 4) regs_and_bypass->dispclk_bypass = 0; regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007; - if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4) + if (regs_and_bypass->dprefclk_bypass > 4) regs_and_bypass->dprefclk_bypass = 0; } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index 1eb04772f5da2..35d20a663d67a 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -635,16 +635,16 @@ static void dcn35_save_clk_registers(struct clk_state_registers_and_bypass *regs regs_and_bypass->dtbclk = internal.CLK1_CLK4_CURRENT_CNT / 10; regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007; - if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4) + if (regs_and_bypass->dppclk_bypass > 4) regs_and_bypass->dppclk_bypass = 0; regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007; - if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4) + if (regs_and_bypass->dcfclk_bypass > 4) regs_and_bypass->dcfclk_bypass = 0; regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007; - if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4) + if (regs_and_bypass->dispclk_bypass > 4) regs_and_bypass->dispclk_bypass = 0; regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007; - if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4) + if (regs_and_bypass->dprefclk_bypass > 4) regs_and_bypass->dprefclk_bypass = 0; if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) { From 2ada912a4813d5a227b63c539bcd8cb65a58b1d3 Mon Sep 17 00:00:00 2001 From: Fangzhi Zuo Date: Wed, 24 Sep 2025 14:37:01 -0400 Subject: [PATCH 2175/2653] drm/amd/display: Enable Dynamic DTBCLK Switch [WHAT] Since dcn35, DTBCLK can be disabled when no DP2 sink connected for power saving purpose. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Aurabindo Pillai Signed-off-by: Fangzhi Zuo Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 76289a68809b2..098d018073c66 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2017,6 +2017,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) init_data.flags.disable_ips_in_vpb = 0; + /* DCN35 and above supports dynamic DTBCLK switch */ + if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0)) + init_data.flags.allow_0_dtb_clk = true; + /* Enable DWB for tested platforms only */ if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) init_data.num_virtual_links = 1; From 6726c0323dc6346fbf62f28667d4b3730617d461 Mon Sep 17 00:00:00 2001 From: Jesse Agate Date: Fri, 13 Jun 2025 14:20:53 -0400 Subject: [PATCH 2176/2653] drm/amd/display: Incorrect Mirror Cositing [WHY] hinit/vinit are incorrect in the case of mirroring. [HOW] Cositing sign must be flipped when image is mirrored in the vertical or horizontal direction. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Samson Tam Signed-off-by: Jesse Agate Signed-off-by: Brendan Leder Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c index 55b929ca79829..b1fb0f8a253a5 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c @@ -641,16 +641,16 @@ static void spl_calculate_inits_and_viewports(struct spl_in *spl_in, /* this gives the direction of the cositing (negative will move * left, right otherwise) */ - int sign = 1; + int h_sign = flip_horz_scan_dir ? -1 : 1; + int v_sign = flip_vert_scan_dir ? -1 : 1; switch (spl_in->basic_in.cositing) { - case CHROMA_COSITING_TOPLEFT: - init_adj_h = spl_fixpt_from_fraction(sign, 4); - init_adj_v = spl_fixpt_from_fraction(sign, 4); + init_adj_h = spl_fixpt_from_fraction(h_sign, 4); + init_adj_v = spl_fixpt_from_fraction(v_sign, 4); break; case CHROMA_COSITING_LEFT: - init_adj_h = spl_fixpt_from_fraction(sign, 4); + init_adj_h = spl_fixpt_from_fraction(h_sign, 4); init_adj_v = spl_fixpt_zero; break; case CHROMA_COSITING_NONE: From f8d6bcee78489e0592e98e8fb102366cd64350b0 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Tue, 26 Aug 2025 17:12:44 -0400 Subject: [PATCH 2177/2653] drm/amd/display: Driver implementation for cursor offloading to DMU [Why] We require an interlock between driver and firmware for upcoming features and given that this could possibly happen on any single cursor programming call (and that we can't asynchronously wait for firmware to respond because of it) we'd be regressing cursor performance by at least an extra 40us per call. When we could possibly have cursor update every 20us - 100s from high frequency gaming mice this means that we'd be stuttering or dropping updates and impacting overall cursor performance. We want a solution that can: 1. Interlock between other firmware features 2. Not stall out or require the DMCUB lock for every single update [How] When cursor offloading is enabled and supported by an ASIC driver will route the cursor programming through to DMU as part of the regular DC stream cursor programming interfaces for attributes and position. The atomic pipe programming version will not be updated: this will still follow the existing programming path by keeping track of a field that specifies when the register writes should be deferred to DMU. Cursor locking is not required when cursor offload is in progress since the updates are consolidated and processed by DMU once at the end of the frame in a periodic manner. The shared buffer the firmware queries from is allocated along with the rest of the scratch state region in an area that's accessible by both firmware and driver. The size of the cursor offload (v1) state will not change, but it does have a unique union per ASIC version with room for expansion if needed. When firmware features notifying DMU of DRR updates are not enabled we now send an explicit vtotal min/max update via driver to DMU firmware whenever the vtotal max changes. This is to allow the cursor programming to determine the appropriate latch update point offset from vupdate. Reviewed-by: Dillon Varone Signed-off-by: Nicholas Kazlauskas Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/core/dc.c | 12 ++ .../drm/amd/display/dc/core/dc_hw_sequencer.c | 12 ++ .../gpu/drm/amd/display/dc/core/dc_stream.c | 42 ++++-- drivers/gpu/drm/amd/display/dc/dc.h | 1 + drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 99 +++++++++++++ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 36 +++++ .../drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c | 19 ++- .../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 20 ++- .../amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c | 42 ++++-- .../amd/display/dc/hubp/dcn10/dcn10_hubp.c | 1 + .../amd/display/dc/hubp/dcn20/dcn20_hubp.c | 69 +++++---- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 3 + .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 3 + .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 138 ++++++++++++++++++ .../amd/display/dc/hwss/dcn35/dcn35_hwseq.h | 8 + .../amd/display/dc/hwss/dcn35/dcn35_init.c | 6 + .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 60 +++++++- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 2 + .../amd/display/dc/hwss/dcn401/dcn401_init.c | 7 + .../drm/amd/display/dc/hwss/hw_sequencer.h | 14 ++ .../amd/display/dc/inc/hw/cursor_reg_cache.h | 22 +++ drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 1 + drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 1 + drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 6 +- .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 22 +-- 25 files changed, 567 insertions(+), 79 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e33fdf08c8f63..fe7af5b3425ab 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -496,6 +496,10 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, return true; } } + + if (dc->hwss.notify_cursor_offload_drr_update) + dc->hwss.notify_cursor_offload_drr_update(dc, dc->current_state, stream); + return false; } @@ -2188,8 +2192,14 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe); } + for (i = 0; i < dc->current_state->stream_count; i++) + dc_dmub_srv_control_cursor_offload(dc, dc->current_state, dc->current_state->streams[i], false); + result = dc->hwss.apply_ctx_to_hw(dc, context); + for (i = 0; i < context->stream_count; i++) + dc_dmub_srv_control_cursor_offload(dc, context, context->streams[i], true); + if (result != DC_OK) { /* Application of dc_state to hardware stopped. */ dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY; @@ -4489,6 +4499,8 @@ static void commit_planes_for_stream(struct dc *dc, pipe_ctx->plane_state->skip_manual_trigger) continue; + if (dc->hwss.program_cursor_offload_now) + dc->hwss.program_cursor_offload_now(dc, pipe_ctx); if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger) pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 25a07e5f4ed77..1bed3b14a287e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -911,6 +911,13 @@ void hwss_build_fast_sequence(struct dc *dc, current_mpc_pipe->stream && current_mpc_pipe->plane_state && current_mpc_pipe->plane_state->update_flags.bits.addr_update && !current_mpc_pipe->plane_state->skip_manual_trigger) { + if (dc->hwss.program_cursor_offload_now) { + block_sequence[*num_steps].params.program_cursor_update_now_params.dc = dc; + block_sequence[*num_steps].params.program_cursor_update_now_params.pipe_ctx = current_mpc_pipe; + block_sequence[*num_steps].func = PROGRAM_CURSOR_UPDATE_NOW; + (*num_steps)++; + } + block_sequence[*num_steps].params.program_manual_trigger_params.pipe_ctx = current_mpc_pipe; block_sequence[*num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER; (*num_steps)++; @@ -1004,6 +1011,11 @@ void hwss_execute_sequence(struct dc *dc, case DMUB_HW_CONTROL_LOCK_FAST: dc->hwss.dmub_hw_control_lock_fast(params); break; + case PROGRAM_CURSOR_UPDATE_NOW: + dc->hwss.program_cursor_offload_now( + params->program_cursor_update_now_params.dc, + params->program_cursor_update_now_params.pipe_ctx); + break; default: ASSERT(false); break; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 9ac2d41f8fcae..ccaf37d3e7e4a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -231,6 +231,7 @@ void program_cursor_attributes( int i; struct resource_context *res_ctx; struct pipe_ctx *pipe_to_program = NULL; + bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); if (!stream) return; @@ -245,9 +246,14 @@ void program_cursor_attributes( if (!pipe_to_program) { pipe_to_program = pipe_ctx; - dc->hwss.cursor_lock(dc, pipe_to_program, true); - if (pipe_to_program->next_odm_pipe) - dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, true); + + if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) { + dc->hwss.begin_cursor_offload_update(dc, pipe_ctx); + } else { + dc->hwss.cursor_lock(dc, pipe_to_program, true); + if (pipe_to_program->next_odm_pipe) + dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, true); + } } dc->hwss.set_cursor_attribute(pipe_ctx); @@ -255,12 +261,18 @@ void program_cursor_attributes( dc_send_update_cursor_info_to_dmu(pipe_ctx, i); if (dc->hwss.set_cursor_sdr_white_level) dc->hwss.set_cursor_sdr_white_level(pipe_ctx); + if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) + dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx); } if (pipe_to_program) { - dc->hwss.cursor_lock(dc, pipe_to_program, false); - if (pipe_to_program->next_odm_pipe) - dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, false); + if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) { + dc->hwss.commit_cursor_offload_update(dc, pipe_to_program); + } else { + dc->hwss.cursor_lock(dc, pipe_to_program, false); + if (pipe_to_program->next_odm_pipe) + dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, false); + } } } @@ -366,6 +378,7 @@ void program_cursor_position( int i; struct resource_context *res_ctx; struct pipe_ctx *pipe_to_program = NULL; + bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); if (!stream) return; @@ -384,16 +397,27 @@ void program_cursor_position( if (!pipe_to_program) { pipe_to_program = pipe_ctx; - dc->hwss.cursor_lock(dc, pipe_to_program, true); + + if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) + dc->hwss.begin_cursor_offload_update(dc, pipe_ctx); + else + dc->hwss.cursor_lock(dc, pipe_to_program, true); } dc->hwss.set_cursor_position(pipe_ctx); + if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) + dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx); + if (dc->ctx->dmub_srv) dc_send_update_cursor_info_to_dmu(pipe_ctx, i); } - if (pipe_to_program) - dc->hwss.cursor_lock(dc, pipe_to_program, false); + if (pipe_to_program) { + if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) + dc->hwss.commit_cursor_offload_update(dc, pipe_to_program); + else + dc->hwss.cursor_lock(dc, pipe_to_program, false); + } } bool dc_stream_set_cursor_position( diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f5208a070a915..63c8ccd9378d3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -530,6 +530,7 @@ struct dc_config { bool set_pipe_unlock_order; bool enable_dpia_pre_training; bool unify_link_enc_assignment; + bool enable_cursor_offload; struct spl_sharpness_range dcn_sharpness_range; struct spl_sharpness_range dcn_override_sharpness_range; }; diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index 53a088ebddefe..c75663aefcf3f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -1174,6 +1174,100 @@ void dc_dmub_srv_subvp_save_surf_addr(const struct dc_dmub_srv *dc_dmub_srv, con dmub_srv_subvp_save_surf_addr(dc_dmub_srv->dmub, addr, subvp_index); } +void dc_dmub_srv_cursor_offload_init(struct dc *dc) +{ + struct dmub_rb_cmd_cursor_offload_init *init; + struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv; + union dmub_rb_cmd cmd; + + if (!dc->config.enable_cursor_offload) + return; + + if (!dc_dmub_srv->dmub->meta_info.feature_bits.bits.cursor_offload_v1_support) + return; + + if (!dc_dmub_srv->dmub->cursor_offload_fb.gpu_addr || !dc_dmub_srv->dmub->cursor_offload_fb.cpu_addr) + return; + + if (!dc_dmub_srv->dmub->cursor_offload_v1) + return; + + if (!dc_dmub_srv->dmub->shared_state) + return; + + memset(&cmd, 0, sizeof(cmd)); + + init = &cmd.cursor_offload_init; + init->header.type = DMUB_CMD__CURSOR_OFFLOAD; + init->header.sub_type = DMUB_CMD__CURSOR_OFFLOAD_INIT; + init->header.payload_bytes = sizeof(init->init_data); + init->init_data.state_addr.quad_part = dc_dmub_srv->dmub->cursor_offload_fb.gpu_addr; + init->init_data.state_size = dc_dmub_srv->dmub->cursor_offload_fb.size; + + dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); + + dc_dmub_srv->cursor_offload_enabled = true; +} + +void dc_dmub_srv_control_cursor_offload(struct dc *dc, struct dc_state *context, + const struct dc_stream_state *stream, bool enable) +{ + struct pipe_ctx const *pipe_ctx; + struct dmub_rb_cmd_cursor_offload_stream_cntl *cntl; + union dmub_rb_cmd cmd; + + if (!dc_dmub_srv_is_cursor_offload_enabled(dc)) + return; + + if (!stream) + return; + + pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); + if (!pipe_ctx || !pipe_ctx->stream_res.tg || pipe_ctx->stream != stream) + return; + + memset(&cmd, 0, sizeof(cmd)); + + cntl = &cmd.cursor_offload_stream_ctnl; + cntl->header.type = DMUB_CMD__CURSOR_OFFLOAD; + cntl->header.sub_type = + enable ? DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE : DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE; + cntl->header.payload_bytes = sizeof(cntl->data); + + cntl->data.otg_inst = pipe_ctx->stream_res.tg->inst; + cntl->data.line_time_in_ns = 1u + (uint32_t)(div64_u64(stream->timing.h_total * 1000000ull, + stream->timing.pix_clk_100hz / 10)); + + cntl->data.v_total_max = stream->adjust.v_total_max > stream->timing.v_total ? + stream->adjust.v_total_max : + stream->timing.v_total; + + dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, + enable ? DM_DMUB_WAIT_TYPE_NO_WAIT : DM_DMUB_WAIT_TYPE_WAIT); +} + +void dc_dmub_srv_program_cursor_now(struct dc *dc, const struct pipe_ctx *pipe) +{ + struct dmub_rb_cmd_cursor_offload_stream_cntl *cntl; + union dmub_rb_cmd cmd; + + if (!dc_dmub_srv_is_cursor_offload_enabled(dc)) + return; + + if (!pipe || !pipe->stream || !pipe->stream_res.tg) + return; + + memset(&cmd, 0, sizeof(cmd)); + + cntl = &cmd.cursor_offload_stream_ctnl; + cntl->header.type = DMUB_CMD__CURSOR_OFFLOAD; + cntl->header.sub_type = DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM; + cntl->header.payload_bytes = sizeof(cntl->data); + cntl->data.otg_inst = pipe->stream_res.tg->inst; + + dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); +} + bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait) { struct dc_context *dc_ctx; @@ -2231,6 +2325,11 @@ bool dmub_lsdma_send_poll_reg_write_command(struct dc_dmub_srv *dc_dmub_srv, uin return result; } +bool dc_dmub_srv_is_cursor_offload_enabled(const struct dc *dc) +{ + return dc->ctx->dmub_srv && dc->ctx->dmub_srv->cursor_offload_enabled; +} + void dc_dmub_srv_release_hw(const struct dc *dc) { struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv; diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h index 7ef93444ef3cf..9bb00d48fd5e1 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h @@ -56,6 +56,7 @@ struct dc_dmub_srv { union dmub_shared_state_ips_driver_signals driver_signals; bool idle_allowed; bool needs_idle_wake; + bool cursor_offload_enabled; }; bool dc_dmub_srv_wait_for_pending(struct dc_dmub_srv *dc_dmub_srv); @@ -325,6 +326,41 @@ bool dc_dmub_srv_ips_query_residency_info(const struct dc_context *ctx, uint8_t struct dmub_ips_residency_info *driver_info, enum ips_residency_mode ips_mode); +/** + * dc_dmub_srv_cursor_offload_init() - Enables or disables cursor offloading for a stream. + * + * @dc: pointer to DC object + */ +void dc_dmub_srv_cursor_offload_init(struct dc *dc); + +/** + * dc_dmub_srv_control_cursor_offload() - Enables or disables cursor offloading for a stream. + * + * @dc: pointer to DC object + * @context: the DC context to reference for pipe allocations + * @stream: the stream to control + * @enable: true to enable cursor offload, false to disable + */ +void dc_dmub_srv_control_cursor_offload(struct dc *dc, struct dc_state *context, + const struct dc_stream_state *stream, bool enable); + +/** + * dc_dmub_srv_program_cursor_now() - Requests immediate cursor programming for a given pipe. + * + * @dc: pointer to DC object + * @pipe: top-most pipe for a stream. + */ +void dc_dmub_srv_program_cursor_now(struct dc *dc, const struct pipe_ctx *pipe); + +/** + * dc_dmub_srv_is_cursor_offload_enabled() - Checks if cursor offload is supported. + * + * @dc: pointer to DC object + * + * Return: true if cursor offload is supported, false otherwise + */ +bool dc_dmub_srv_is_cursor_offload_enabled(const struct dc *dc); + /** * dc_dmub_srv_release_hw() - Notifies DMUB service that HW access is no longer required. * diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c index 01480a04f85ef..ce91e5d289567 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c @@ -199,6 +199,8 @@ void dpp_reset(struct dpp *dpp_base) memset(&dpp->scl_data, 0, sizeof(dpp->scl_data)); memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data)); + + dpp_base->cursor_offload = false; } @@ -484,10 +486,12 @@ void dpp1_set_cursor_position( cur_en = 0; /* not visible beyond top edge*/ if (dpp_base->pos.cur0_ctl.bits.cur0_enable != cur_en) { - REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en); - - dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en; + if (!dpp_base->cursor_offload) + REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en); } + + dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en; + dpp_base->att.cur0_ctl.bits.cur0_enable = cur_en; } void dpp1_cnv_set_optional_cursor_attributes( @@ -497,8 +501,13 @@ void dpp1_cnv_set_optional_cursor_attributes( struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); if (attr) { - REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, attr->bias); - REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, attr->scale); + if (!dpp_base->cursor_offload) { + REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, attr->bias); + REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, attr->scale); + } + + dpp_base->att.fp_scale_bias.bits.fp_bias = attr->bias; + dpp_base->att.fp_scale_bias.bits.fp_scale = attr->scale; } } diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c index 09be2a90cc79d..94d0dc3461d26 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c @@ -396,17 +396,21 @@ void dpp3_set_cursor_attributes( } } - REG_UPDATE_3(CURSOR0_CONTROL, - CUR0_MODE, color_format, - CUR0_EXPANSION_MODE, 0, - CUR0_ROM_EN, cur_rom_en); + if (!dpp_base->cursor_offload) + REG_UPDATE_3(CURSOR0_CONTROL, + CUR0_MODE, color_format, + CUR0_EXPANSION_MODE, 0, + CUR0_ROM_EN, cur_rom_en); if (color_format == CURSOR_MODE_MONO) { /* todo: clarify what to program these to */ - REG_UPDATE(CURSOR0_COLOR0, - CUR0_COLOR0, 0x00000000); - REG_UPDATE(CURSOR0_COLOR1, - CUR0_COLOR1, 0xFFFFFFFF); + + if (!dpp_base->cursor_offload) { + REG_UPDATE(CURSOR0_COLOR0, + CUR0_COLOR0, 0x00000000); + REG_UPDATE(CURSOR0_COLOR1, + CUR0_COLOR1, 0xFFFFFFFF); + } } dpp_base->att.cur0_ctl.bits.expansion_mode = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c index 7aab77b588694..3adc17f2fc35b 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c @@ -103,17 +103,21 @@ void dpp401_set_cursor_attributes( } } - REG_UPDATE_3(CURSOR0_CONTROL, - CUR0_MODE, color_format, - CUR0_EXPANSION_MODE, 0, - CUR0_ROM_EN, cur_rom_en); + if (!dpp_base->cursor_offload) + REG_UPDATE_3(CURSOR0_CONTROL, + CUR0_MODE, color_format, + CUR0_EXPANSION_MODE, 0, + CUR0_ROM_EN, cur_rom_en); if (color_format == CURSOR_MODE_MONO) { /* todo: clarify what to program these to */ - REG_UPDATE(CURSOR0_COLOR0, - CUR0_COLOR0, 0x00000000); - REG_UPDATE(CURSOR0_COLOR1, - CUR0_COLOR1, 0xFFFFFFFF); + + if (!dpp_base->cursor_offload) { + REG_UPDATE(CURSOR0_COLOR0, + CUR0_COLOR0, 0x00000000); + REG_UPDATE(CURSOR0_COLOR1, + CUR0_COLOR1, 0xFFFFFFFF); + } } dpp_base->att.cur0_ctl.bits.expansion_mode = 0; @@ -132,10 +136,11 @@ void dpp401_set_cursor_position( uint32_t cur_en = pos->enable ? 1 : 0; if (dpp_base->pos.cur0_ctl.bits.cur0_enable != cur_en) { - REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en); - - dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en; + if (!dpp_base->cursor_offload) + REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en); } + + dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en; } void dpp401_set_optional_cursor_attributes( @@ -145,10 +150,17 @@ void dpp401_set_optional_cursor_attributes( struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); if (attr) { - REG_UPDATE(CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_BIAS_G_Y, attr->bias); - REG_UPDATE(CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_SCALE_G_Y, attr->scale); - REG_UPDATE(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_BIAS_RB_CRCB, attr->bias); - REG_UPDATE(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_SCALE_RB_CRCB, attr->scale); + if (!dpp_base->cursor_offload) { + REG_UPDATE(CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_BIAS_G_Y, attr->bias); + REG_UPDATE(CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_SCALE_G_Y, attr->scale); + REG_UPDATE(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_BIAS_RB_CRCB, attr->bias); + REG_UPDATE(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_SCALE_RB_CRCB, attr->scale); + } + + dpp_base->att.fp_scale_bias_g_y.bits.fp_bias_g_y = attr->bias; + dpp_base->att.fp_scale_bias_g_y.bits.fp_scale_g_y = attr->scale; + dpp_base->att.fp_scale_bias_rb_crcb.bits.fp_bias_rb_crcb = attr->bias; + dpp_base->att.fp_scale_bias_rb_crcb.bits.fp_scale_rb_crcb = attr->scale; } } diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c index 9b026600b90e8..6378e3fd72494 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c @@ -550,6 +550,7 @@ void hubp_reset(struct hubp *hubp) { memset(&hubp->pos, 0, sizeof(hubp->pos)); memset(&hubp->att, 0, sizeof(hubp->att)); + hubp->cursor_offload = false; } void hubp1_program_surface_config( diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c index 91259b896e032..92288de4cc10c 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c @@ -613,26 +613,28 @@ void hubp2_cursor_set_attributes( hubp->curs_attr = *attr; - REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, - CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); - REG_UPDATE(CURSOR_SURFACE_ADDRESS, - CURSOR_SURFACE_ADDRESS, attr->address.low_part); - - REG_UPDATE_2(CURSOR_SIZE, - CURSOR_WIDTH, attr->width, - CURSOR_HEIGHT, attr->height); - - REG_UPDATE_4(CURSOR_CONTROL, - CURSOR_MODE, attr->color_format, - CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION, - CURSOR_PITCH, hw_pitch, - CURSOR_LINES_PER_CHUNK, lpc); - - REG_SET_2(CURSOR_SETTINGS, 0, - /* no shift of the cursor HDL schedule */ - CURSOR0_DST_Y_OFFSET, 0, - /* used to shift the cursor chunk request deadline */ - CURSOR0_CHUNK_HDL_ADJUST, 3); + if (!hubp->cursor_offload) { + REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, + CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); + REG_UPDATE(CURSOR_SURFACE_ADDRESS, + CURSOR_SURFACE_ADDRESS, attr->address.low_part); + + REG_UPDATE_2(CURSOR_SIZE, + CURSOR_WIDTH, attr->width, + CURSOR_HEIGHT, attr->height); + + REG_UPDATE_4(CURSOR_CONTROL, + CURSOR_MODE, attr->color_format, + CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION, + CURSOR_PITCH, hw_pitch, + CURSOR_LINES_PER_CHUNK, lpc); + + REG_SET_2(CURSOR_SETTINGS, 0, + /* no shift of the cursor HDL schedule */ + CURSOR0_DST_Y_OFFSET, 0, + /* used to shift the cursor chunk request deadline */ + CURSOR0_CHUNK_HDL_ADJUST, 3); + } hubp->att.SURFACE_ADDR_HIGH = attr->address.high_part; hubp->att.SURFACE_ADDR = attr->address.low_part; @@ -1059,23 +1061,28 @@ void hubp2_cursor_set_position( cur_en = 0; /* not visible beyond top edge*/ if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) { - if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) + bool cursor_not_programmed = hubp->att.SURFACE_ADDR == 0 && hubp->att.SURFACE_ADDR_HIGH == 0; + + if (cur_en && cursor_not_programmed) hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); - REG_UPDATE(CURSOR_CONTROL, - CURSOR_ENABLE, cur_en); + if (!hubp->cursor_offload) + REG_UPDATE(CURSOR_CONTROL, CURSOR_ENABLE, cur_en); } - REG_SET_2(CURSOR_POSITION, 0, - CURSOR_X_POSITION, pos->x, - CURSOR_Y_POSITION, pos->y); + if (!hubp->cursor_offload) { + REG_SET_2(CURSOR_POSITION, 0, + CURSOR_X_POSITION, pos->x, + CURSOR_Y_POSITION, pos->y); - REG_SET_2(CURSOR_HOT_SPOT, 0, - CURSOR_HOT_SPOT_X, pos->x_hotspot, - CURSOR_HOT_SPOT_Y, pos->y_hotspot); + REG_SET_2(CURSOR_HOT_SPOT, 0, + CURSOR_HOT_SPOT_X, pos->x_hotspot, + CURSOR_HOT_SPOT_Y, pos->y_hotspot); + + REG_SET(CURSOR_DST_OFFSET, 0, + CURSOR_DST_X_OFFSET, dst_x_offset); + } - REG_SET(CURSOR_DST_OFFSET, 0, - CURSOR_DST_X_OFFSET, dst_x_offset); /* TODO Handle surface pixel formats other than 4:4:4 */ /* Cursor Position Register Config */ hubp->pos.cur_ctl.bits.cur_enable = cur_en; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index c88781de6d18a..fa62e40a98586 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -3090,6 +3090,9 @@ static void dcn10_update_dchubp_dpp( } if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { + if (dc->hwss.abort_cursor_offload_update) + dc->hwss.abort_cursor_offload_update(dc, pipe_ctx); + dc->hwss.set_cursor_attribute(pipe_ctx); dc->hwss.set_cursor_position(pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index cf9e8ce784ce1..6bd905905984b 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -1793,6 +1793,9 @@ void dcn20_update_dchubp_dpp( if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || pipe_ctx->update_flags.bits.scaler || viewport_changed == true) && pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { + if (dc->hwss.abort_cursor_offload_update) + dc->hwss.abort_cursor_offload_update(dc, pipe_ctx); + dc->hwss.set_cursor_attribute(pipe_ctx); dc->hwss.set_cursor_position(pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 7ea3fe48b329e..404ff00c71300 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -1593,3 +1593,141 @@ void dcn35_hardware_release(struct dc *dc) if (dc->hwss.hw_block_power_up) dc->hwss.hw_block_power_up(dc, &pg_update_state); } + +void dcn35_abort_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe) +{ + if (!dc_dmub_srv_is_cursor_offload_enabled(dc)) + return; + + /* + * Insert a blank update to modify the write index and set pipe_mask to 0. + * + * While the DMU is interlocked with driver full pipe programming via + * the DMU HW lock, if the cursor update begins to execute after a full + * pipe programming occurs there are two possible issues: + * + * 1. Outdated cursor information is programmed, replacing the current update + * 2. The cursor update in firmware holds the cursor lock, preventing + * the current update from being latched atomically in the same frame + * as the rest of the update. + * + * This blank update, treated as a no-op, will allow the firmware to skip + * the programming. + */ + + if (dc->hwss.begin_cursor_offload_update) + dc->hwss.begin_cursor_offload_update(dc, pipe); + + if (dc->hwss.commit_cursor_offload_update) + dc->hwss.commit_cursor_offload_update(dc, pipe); +} + +void dcn35_begin_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe) +{ + volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1; + const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe); + uint32_t stream_idx, write_idx, payload_idx; + + if (!top_pipe) + return; + + stream_idx = top_pipe->pipe_idx; + write_idx = cs->offload_streams[stream_idx].write_idx + 1; /* new payload (+1) */ + payload_idx = write_idx % ARRAY_SIZE(cs->offload_streams[stream_idx].payloads); + + cs->offload_streams[stream_idx].payloads[payload_idx].write_idx_start = write_idx; + + if (pipe->plane_res.hubp) + pipe->plane_res.hubp->cursor_offload = true; + + if (pipe->plane_res.dpp) + pipe->plane_res.dpp->cursor_offload = true; +} + +void dcn35_commit_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe) +{ + volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1; + volatile struct dmub_shared_state_cursor_offload_stream_v1 *shared_stream; + const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe); + uint32_t stream_idx, write_idx, payload_idx; + + if (pipe->plane_res.hubp) + pipe->plane_res.hubp->cursor_offload = false; + + if (pipe->plane_res.dpp) + pipe->plane_res.dpp->cursor_offload = false; + + if (!top_pipe) + return; + + stream_idx = top_pipe->pipe_idx; + write_idx = cs->offload_streams[stream_idx].write_idx + 1; /* new payload (+1) */ + payload_idx = write_idx % ARRAY_SIZE(cs->offload_streams[stream_idx].payloads); + + shared_stream = &dc->ctx->dmub_srv->dmub->shared_state[DMUB_SHARED_STATE_FEATURE__CURSOR_OFFLOAD_V1] + .data.cursor_offload_v1.offload_streams[stream_idx]; + + shared_stream->last_write_idx = write_idx; + + cs->offload_streams[stream_idx].write_idx = write_idx; + cs->offload_streams[stream_idx].payloads[payload_idx].write_idx_finish = write_idx; +} + +void dcn35_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe) +{ + volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1; + const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe); + const struct hubp *hubp = pipe->plane_res.hubp; + const struct dpp *dpp = pipe->plane_res.dpp; + volatile struct dmub_cursor_offload_pipe_data_dcn30_v1 *p; + uint32_t stream_idx, write_idx, payload_idx; + + if (!top_pipe || !hubp || !dpp) + return; + + stream_idx = top_pipe->pipe_idx; + write_idx = cs->offload_streams[stream_idx].write_idx + 1; /* new payload (+1) */ + payload_idx = write_idx % ARRAY_SIZE(cs->offload_streams[stream_idx].payloads); + + p = &cs->offload_streams[stream_idx].payloads[payload_idx].pipe_data[pipe->pipe_idx].dcn30; + + p->CURSOR0_0_CURSOR_SURFACE_ADDRESS = hubp->att.SURFACE_ADDR; + p->CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH = hubp->att.SURFACE_ADDR_HIGH; + p->CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH = hubp->att.size.bits.width; + p->CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT = hubp->att.size.bits.height; + p->CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION = hubp->pos.position.bits.x_pos; + p->CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION = hubp->pos.position.bits.y_pos; + p->CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X = hubp->pos.hot_spot.bits.x_hot; + p->CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y = hubp->pos.hot_spot.bits.y_hot; + p->CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET = hubp->pos.dst_offset.bits.dst_x_offset; + p->CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE = hubp->pos.cur_ctl.bits.cur_enable; + p->CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE = hubp->att.cur_ctl.bits.mode; + p->CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY = hubp->pos.cur_ctl.bits.cur_2x_magnify; + p->CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH = hubp->att.cur_ctl.bits.pitch; + p->CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK = hubp->pos.cur_ctl.bits.line_per_chunk; + + p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE = dpp->att.cur0_ctl.bits.cur0_enable; + p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE = dpp->att.cur0_ctl.bits.mode; + p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE = dpp->att.cur0_ctl.bits.expansion_mode; + p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN = dpp->att.cur0_ctl.bits.cur0_rom_en; + p->CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 = 0x000000; + p->CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 = 0xFFFFFF; + p->CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS = dpp->att.fp_scale_bias.bits.fp_bias; + p->CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE = dpp->att.fp_scale_bias.bits.fp_scale; + + p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET = hubp->att.settings.bits.dst_y_offset; + p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST = hubp->att.settings.bits.chunk_hdl_adjust; + + cs->offload_streams[stream_idx].payloads[payload_idx].pipe_mask |= (1u << pipe->pipe_idx); +} + +void dcn35_notify_cursor_offload_drr_update(struct dc *dc, struct dc_state *context, + const struct dc_stream_state *stream) +{ + dc_dmub_srv_control_cursor_offload(dc, context, stream, true); +} + +void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe) +{ + dc_dmub_srv_program_cursor_now(dc, pipe); +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h index 0b1d6f608edd7..1ff41dba556c0 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h @@ -101,4 +101,12 @@ bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx); void dcn35_hardware_release(struct dc *dc); +void dcn35_abort_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe); +void dcn35_begin_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe); +void dcn35_commit_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe); +void dcn35_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe); +void dcn35_notify_cursor_offload_drr_update(struct dc *dc, struct dc_state *context, + const struct dc_stream_state *stream); +void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe); + #endif /* __DC_HWSS_DCN35_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c index f2f16a0bdb4f3..5a66c9db26709 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c @@ -86,6 +86,12 @@ static const struct hw_sequencer_funcs dcn35_funcs = { .set_cursor_position = dcn10_set_cursor_position, .set_cursor_attribute = dcn10_set_cursor_attribute, .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level, + .abort_cursor_offload_update = dcn35_abort_cursor_offload_update, + .begin_cursor_offload_update = dcn35_begin_cursor_offload_update, + .commit_cursor_offload_update = dcn35_commit_cursor_offload_update, + .update_cursor_offload_pipe = dcn35_update_cursor_offload_pipe, + .notify_cursor_offload_drr_update = dcn35_notify_cursor_offload_drr_update, + .program_cursor_offload_now = dcn35_program_cursor_offload_now, .setup_periodic_interrupt = dcn10_setup_periodic_interrupt, .set_clock = dcn10_set_clock, .get_clock = dcn10_get_clock, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index ab21da435a36d..71c2cfa4df755 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1473,7 +1473,10 @@ void dcn401_dmub_hw_control_lock(struct dc *dc, /* use always for now */ union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; - if (!dc->ctx || !dc->ctx->dmub_srv || !dc->debug.fams2_config.bits.enable) + if (!dc->ctx || !dc->ctx->dmub_srv) + return; + + if (!dc->debug.fams2_config.bits.enable && !dc_dmub_srv_is_cursor_offload_enabled(dc)) return; hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; @@ -2669,3 +2672,58 @@ void dcn401_plane_atomic_power_down(struct dc *dc, if (hws->funcs.dpp_root_clock_control) hws->funcs.dpp_root_clock_control(hws, dpp->inst, false); } + +void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe) +{ + volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1; + const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe); + const struct hubp *hubp = pipe->plane_res.hubp; + const struct dpp *dpp = pipe->plane_res.dpp; + volatile struct dmub_cursor_offload_pipe_data_dcn401_v1 *p; + uint32_t stream_idx, write_idx, payload_idx; + + if (!top_pipe || !hubp || !dpp) + return; + + stream_idx = top_pipe->pipe_idx; + write_idx = cs->offload_streams[stream_idx].write_idx; + payload_idx = write_idx % ARRAY_SIZE(cs->offload_streams[stream_idx].payloads); + + p = &cs->offload_streams[stream_idx].payloads[payload_idx].pipe_data[pipe->pipe_idx].dcn401; + + p->CURSOR0_0_CURSOR_SURFACE_ADDRESS = hubp->att.SURFACE_ADDR; + p->CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH = hubp->att.SURFACE_ADDR_HIGH; + p->CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH = hubp->att.size.bits.width; + p->CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT = hubp->att.size.bits.height; + p->CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION = hubp->pos.position.bits.x_pos; + p->CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION = hubp->pos.position.bits.y_pos; + p->CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X = hubp->pos.hot_spot.bits.x_hot; + p->CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y = hubp->pos.hot_spot.bits.y_hot; + p->CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET = hubp->pos.dst_offset.bits.dst_x_offset; + p->CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE = hubp->pos.cur_ctl.bits.cur_enable; + p->CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE = hubp->att.cur_ctl.bits.mode; + p->CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY = hubp->pos.cur_ctl.bits.cur_2x_magnify; + p->CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH = hubp->att.cur_ctl.bits.pitch; + p->CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK = hubp->pos.cur_ctl.bits.line_per_chunk; + + p->CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE = dpp->att.cur0_ctl.bits.cur0_enable; + p->CM_CUR0_CURSOR0_CONTROL__CUR0_MODE = dpp->att.cur0_ctl.bits.mode; + p->CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE = dpp->att.cur0_ctl.bits.expansion_mode; + p->CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN = dpp->att.cur0_ctl.bits.cur0_rom_en; + p->CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 = 0x000000; + p->CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 = 0xFFFFFF; + + p->CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y = + dpp->att.fp_scale_bias_g_y.bits.fp_bias_g_y; + p->CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y = + dpp->att.fp_scale_bias_g_y.bits.fp_scale_g_y; + p->CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB = + dpp->att.fp_scale_bias_rb_crcb.bits.fp_bias_rb_crcb; + p->CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB = + dpp->att.fp_scale_bias_rb_crcb.bits.fp_scale_rb_crcb; + + p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET = hubp->att.settings.bits.dst_y_offset; + p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST = hubp->att.settings.bits.chunk_hdl_adjust; + + cs->offload_streams[stream_idx].payloads[payload_idx].pipe_mask |= (1u << pipe->pipe_idx); +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h index 9591657d8eee3..f489bb7a4c268 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h @@ -110,4 +110,6 @@ void dcn401_plane_atomic_power_down(struct dc *dc, struct dpp *dpp, struct hubp *hubp); void dcn401_initialize_min_clocks(struct dc *dc); +void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe); + #endif /* __DC_HWSS_DCN401_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c index a221b8cb6d4dd..1c736b7e33001 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c @@ -9,6 +9,7 @@ #include "dcn30/dcn30_hwseq.h" #include "dcn31/dcn31_hwseq.h" #include "dcn32/dcn32_hwseq.h" +#include "dcn35/dcn35_hwseq.h" #include "dcn401/dcn401_hwseq.h" #include "dcn401_init.h" @@ -60,6 +61,12 @@ static const struct hw_sequencer_funcs dcn401_funcs = { .set_cursor_position = dcn401_set_cursor_position, .set_cursor_attribute = dcn10_set_cursor_attribute, .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level, + .abort_cursor_offload_update = dcn35_abort_cursor_offload_update, + .begin_cursor_offload_update = dcn35_begin_cursor_offload_update, + .commit_cursor_offload_update = dcn35_commit_cursor_offload_update, + .update_cursor_offload_pipe = dcn401_update_cursor_offload_pipe, + .notify_cursor_offload_drr_update = dcn35_notify_cursor_offload_drr_update, + .program_cursor_offload_now = dcn35_program_cursor_offload_now, .setup_periodic_interrupt = dcn10_setup_periodic_interrupt, .set_clock = dcn10_set_clock, .get_clock = dcn10_get_clock, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index 619ac4dfff078..a937a2b2135e7 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -154,6 +154,11 @@ struct dmub_hw_control_lock_fast_params { bool lock; }; +struct program_cursor_update_now_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; +}; + union block_sequence_params { struct update_plane_addr_params update_plane_addr_params; struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params; @@ -174,6 +179,7 @@ union block_sequence_params { struct subvp_save_surf_addr subvp_save_surf_addr; struct wait_for_dcc_meta_propagation_params wait_for_dcc_meta_propagation_params; struct dmub_hw_control_lock_fast_params dmub_hw_control_lock_fast_params; + struct program_cursor_update_now_params program_cursor_update_now_params; }; enum block_sequence_func { @@ -196,6 +202,7 @@ enum block_sequence_func { DMUB_SUBVP_SAVE_SURF_ADDR, HUBP_WAIT_FOR_DCC_META_PROP, DMUB_HW_CONTROL_LOCK_FAST, + PROGRAM_CURSOR_UPDATE_NOW, /* This must be the last value in this enum, add new ones above */ HWSS_BLOCK_SEQUENCE_FUNC_COUNT }; @@ -310,6 +317,13 @@ struct hw_sequencer_funcs { void (*set_cursor_position)(struct pipe_ctx *pipe); void (*set_cursor_attribute)(struct pipe_ctx *pipe); void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); + void (*abort_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe); + void (*begin_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe); + void (*commit_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe); + void (*update_cursor_offload_pipe)(struct dc *dc, const struct pipe_ctx *pipe); + void (*notify_cursor_offload_drr_update)(struct dc *dc, struct dc_state *context, + const struct dc_stream_state *stream); + void (*program_cursor_offload_now)(struct dc *dc, const struct pipe_ctx *pipe); /* Colour Related */ void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h b/drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h index 45645f9fd86c4..081831230821a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h @@ -83,12 +83,34 @@ union reg_cur0_control_cfg { } bits; uint32_t raw; }; + struct cursor_position_cache_dpp { union reg_cur0_control_cfg cur0_ctl; }; struct cursor_attribute_cache_dpp { union reg_cur0_control_cfg cur0_ctl; + union reg_cur0_fp_scale_bias { + struct { + uint32_t fp_bias: 16; + uint32_t fp_scale: 16; + } bits; + uint32_t raw; + } fp_scale_bias; + union reg_cur0_fp_scale_bias_g_y { + struct { + uint32_t fp_bias_g_y: 16; + uint32_t fp_scale_g_y: 16; + } bits; + uint32_t raw; + } fp_scale_bias_g_y; + union reg_cur0_fp_scale_bias_rb_crcb { + struct { + uint32_t fp_bias_rb_crcb: 16; + uint32_t fp_scale_rb_crcb: 16; + } bits; + uint32_t raw; + } fp_scale_bias_rb_crcb; }; struct cursor_attributes_cfg { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h index 1b7c085dc2cc1..09c224691618a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h @@ -84,6 +84,7 @@ struct dpp { struct pwl_params shaper_params; bool cm_bypass_mode; + bool cursor_offload; struct cursor_position_cache_dpp pos; struct cursor_attribute_cache_dpp att; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index 2b874d2cc61c5..5998a20a18c4f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -126,6 +126,7 @@ struct hubp { int mpcc_id; struct dc_cursor_attributes curs_attr; struct dc_cursor_position curs_pos; + bool cursor_offload; bool power_gated; struct cursor_position_cache_hubp pos; diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index 338fdc651f2cf..9012a7ba16021 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -132,6 +132,7 @@ enum dmub_window_id { DMUB_WINDOW_IB_MEM, DMUB_WINDOW_SHARED_STATE, DMUB_WINDOW_LSDMA_BUFFER, + DMUB_WINDOW_CURSOR_OFFLOAD, DMUB_WINDOW_TOTAL, }; @@ -535,7 +536,8 @@ struct dmub_srv_create_params { * @fw_version: the current firmware version, if any * @is_virtual: false if hardware support only * @shared_state: dmub shared state between firmware and driver - * @fw_state: dmub firmware state pointer + * @cursor_offload_v1: Cursor offload state + * @fw_state: dmub firmware state pointer (debug purpose only) */ struct dmub_srv { enum dmub_asic asic; @@ -544,7 +546,9 @@ struct dmub_srv { bool is_virtual; struct dmub_fb scratch_mem_fb; struct dmub_fb ib_mem_gart; + struct dmub_fb cursor_offload_fb; volatile struct dmub_shared_state_feature_block *shared_state; + volatile struct dmub_cursor_offload_v1 *cursor_offload_v1; volatile const struct dmub_fw_state *fw_state; /* private: internal use only */ diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c index b17a19400c067..0244c9b44eccf 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c @@ -564,10 +564,11 @@ enum dmub_status window_sizes[DMUB_WINDOW_4_MAILBOX] = DMUB_MAILBOX_SIZE; window_sizes[DMUB_WINDOW_5_TRACEBUFF] = trace_buffer_size; window_sizes[DMUB_WINDOW_6_FW_STATE] = fw_state_size; - window_sizes[DMUB_WINDOW_7_SCRATCH_MEM] = DMUB_SCRATCH_MEM_SIZE; + window_sizes[DMUB_WINDOW_7_SCRATCH_MEM] = dmub_align(DMUB_SCRATCH_MEM_SIZE, 64); window_sizes[DMUB_WINDOW_IB_MEM] = DMUB_IB_MEM_SIZE; window_sizes[DMUB_WINDOW_SHARED_STATE] = max(DMUB_FW_HEADER_SHARED_STATE_SIZE, shared_state_size); window_sizes[DMUB_WINDOW_LSDMA_BUFFER] = DMUB_LSDMA_RB_SIZE; + window_sizes[DMUB_WINDOW_CURSOR_OFFLOAD] = dmub_align(sizeof(struct dmub_cursor_offload_v1), 64); out->fb_size = dmub_srv_calc_regions_for_memory_type(params, out, window_sizes, DMUB_WINDOW_MEMORY_TYPE_FB); @@ -652,21 +653,22 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; - struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; - struct dmub_fb *ib_mem_gart = params->fb[DMUB_WINDOW_IB_MEM]; struct dmub_fb *shared_state_fb = params->fb[DMUB_WINDOW_SHARED_STATE]; struct dmub_rb_init_params rb_params, outbox0_rb_params; struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6; struct dmub_region inbox1, outbox1, outbox0; + uint32_t i; + if (!dmub->sw_init) return DMUB_STATUS_INVALID; - if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb || - !tracebuff_fb || !fw_state_fb || !scratch_mem_fb || !ib_mem_gart) { - ASSERT(0); - return DMUB_STATUS_INVALID; + for (i = 0; i < DMUB_WINDOW_TOTAL; ++i) { + if (!params->fb[i]) { + ASSERT(0); + return DMUB_STATUS_INVALID; + } } dmub->fb_base = params->fb_base; @@ -748,9 +750,11 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, dmub->shared_state = shared_state_fb->cpu_addr; - dmub->scratch_mem_fb = *scratch_mem_fb; + dmub->scratch_mem_fb = *params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; + dmub->ib_mem_gart = *params->fb[DMUB_WINDOW_IB_MEM]; - dmub->ib_mem_gart = *ib_mem_gart; + dmub->cursor_offload_fb = *params->fb[DMUB_WINDOW_CURSOR_OFFLOAD]; + dmub->cursor_offload_v1 = (struct dmub_cursor_offload_v1 *)dmub->cursor_offload_fb.cpu_addr; if (dmub->hw_funcs.setup_windows) dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6, ®ion6); From 0f5266c2add1b4942d81b42d85854ef0c2d31797 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 26 Sep 2025 16:15:01 -0400 Subject: [PATCH 2178/2653] drm/amd/display: [FW Promotion] Release 0.1.30.0 Add new SMART_POWER_HDR commands to optimize power consumption on certain OLED LED panels by sending MaxCLL per frame to TCON. Reviewed-by: Aurabindo Pillai Signed-off-by: Taimur Hassan Signed-off-by: Alex Hung --- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 104 ++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 9d2a02bd00e28..5df050a906344 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -1724,6 +1724,11 @@ enum dmub_cmd_type { */ DMUB_CMD__CURSOR_OFFLOAD = 92, + /** + * Command type used for all SMART_POWER_HDR commands. + */ + DMUB_CMD__SMART_POWER_HDR = 93, + /** * Command type use for VBIOS shared commands. */ @@ -4392,6 +4397,45 @@ enum replay_enable { REPLAY_ENABLE = 1, }; +/** + * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_HDR_ENABLE command. + */ +struct dmub_rb_cmd_smart_power_hdr_enable_data { + /** + * SMART_POWER_HDR enable or disable. + */ + uint8_t enable; + /** + * Panel Instance. + * Panel isntance to identify which replay_state to use + * Currently the support is only for 0 or 1 + */ + uint8_t panel_inst; + + uint16_t peak_nits; + /** + * OTG HW instance. + */ + uint8_t otg_inst; + /** + * DIG FE HW instance. + */ + uint8_t digfe_inst; + /** + * DIG BE HW instance. + */ + uint8_t digbe_inst; + uint8_t debugcontrol; + /* + * vertical interrupt trigger line + */ + uint32_t triggerline; + + uint16_t fixed_max_cll; + + uint8_t pad[2]; +}; + /** * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. */ @@ -4737,6 +4781,58 @@ union dmub_replay_cmd_set { struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; }; +/** + * SMART POWER HDR command sub-types. + */ +enum dmub_cmd_smart_power_hdr_type { + + /** + * Enable/Disable SMART_POWER_HDR. + */ + DMUB_CMD__SMART_POWER_HDR_ENABLE = 1, + /** + * Get current MaxCLL value if SMART POWER HDR is enabled. + */ + DMUB_CMD__SMART_POWER_HDR_GETMAXCLL = 2, +}; + +/** + * Definition of a DMUB_CMD__SMART_POWER_HDR command. + */ +struct dmub_rb_cmd_smart_power_hdr_enable { + /** + * Command header. + */ + struct dmub_cmd_header header; + + struct dmub_rb_cmd_smart_power_hdr_enable_data data; +}; + +struct dmub_cmd_smart_power_hdr_getmaxcll_input { + uint8_t panel_inst; + uint8_t pad[3]; +}; + +struct dmub_cmd_smart_power_hdr_getmaxcll_output { + uint16_t current_max_cll; + uint8_t pad[2]; +}; + +/** + * Definition of a DMUB_CMD__SMART_POWER_HDR command. + */ +struct dmub_rb_cmd_smart_power_hdr_getmaxcll { + struct dmub_cmd_header header; /**< Command header */ + /** + * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_HDR_GETMAXCLL command. + */ + union dmub_cmd_smart_power_hdr_getmaxcll_data { + struct dmub_cmd_smart_power_hdr_getmaxcll_input input; /**< Input */ + struct dmub_cmd_smart_power_hdr_getmaxcll_output output; /**< Output */ + uint32_t output_raw; /**< Raw data output */ + } data; +}; + /** * Set of HW components that can be locked. * @@ -6606,6 +6702,14 @@ union dmub_rb_cmd { * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_UPDATE_DRR */ struct dmub_rb_cmd_cursor_offload_stream_cntl cursor_offload_stream_ctnl; + /** + * Definition of a DMUB_CMD__SMART_POWER_HDR_ENABLE command. + */ + struct dmub_rb_cmd_smart_power_hdr_enable smart_power_hdr_enable; + /** + * Definition of a DMUB_CMD__DMUB_CMD__SMART_POWER_HDR_GETMAXCLL command. + */ + struct dmub_rb_cmd_smart_power_hdr_getmaxcll smart_power_hdr_getmaxcll; }; /** From d5e48603ae29ed50d0c5208b02cf7bb7d4d92397 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Fri, 3 Oct 2025 16:05:46 -0400 Subject: [PATCH 2179/2653] drm/amdkfd: Fix two comments in kfd_ioctl.h Queue read and write pointers are "to KFD", not "from KFD". Suggested-by: Robert Liu Signed-off-by: Felix Kuehling Reviewed-by: Alex Deucher Reviewed-by: Robert Liu --- include/uapi/linux/kfd_ioctl.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index bdeebc8caebff..dbe848a1490b1 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -67,8 +67,8 @@ struct kfd_ioctl_get_version_args { struct kfd_ioctl_create_queue_args { __u64 ring_base_address; /* to KFD */ - __u64 write_pointer_address; /* from KFD */ - __u64 read_pointer_address; /* from KFD */ + __u64 write_pointer_address; /* to KFD */ + __u64 read_pointer_address; /* to KFD */ __u64 doorbell_offset; /* from KFD */ __u32 ring_size; /* to KFD */ From 56597e991c6b4431eae80863a0f88305d3b5a5ab Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 26 Sep 2025 18:58:54 -0500 Subject: [PATCH 2180/2653] drm/amd/display: Promote DC to 3.2.353 - [FW Promotion] Release 0.1.30.0 - Driver implementation for cursor offloading to DMU - Incorrect Mirror Cositing - Enable Dynamic DTBCLK Switch - Remove comparing uint32_t to zero - Remove inaccessible URL Reviewed-by: Aurabindo Pillai Signed-off-by: Taimur Hassan Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 63c8ccd9378d3..1c77541e0bf59 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.352" +#define DC_VER "3.2.353" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From 1a33a8f3839b39ca1e55dee02bdbfcba97d12688 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 29 Sep 2025 17:59:26 +0530 Subject: [PATCH 2181/2653] drm/amdgpu: Check swus/ds for switch state save For saving switch state, check if the GPU is having SWUS/DS architecture. Otherwise, skip saving. Reported-by: Roman Elshin Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4602 Fixes: 1dd2fa0e00f1 ("drm/amdgpu: Save and restore switch state") Signed-off-by: Lijo Lazar Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 23 ++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 5f075ac74d611..9bb1133b16b8f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -7219,28 +7219,35 @@ void amdgpu_pci_resume(struct pci_dev *pdev) static void amdgpu_device_cache_switch_state(struct amdgpu_device *adev) { - struct pci_dev *parent = pci_upstream_bridge(adev->pdev); + struct pci_dev *swus, *swds; int r; - if (!parent || parent->vendor != PCI_VENDOR_ID_ATI) + swds = pci_upstream_bridge(adev->pdev); + if (!swds || swds->vendor != PCI_VENDOR_ID_ATI || + pci_pcie_type(swds) != PCI_EXP_TYPE_DOWNSTREAM) + return; + swus = pci_upstream_bridge(swds); + if (!swus || + (swus->vendor != PCI_VENDOR_ID_ATI && + swus->vendor != PCI_VENDOR_ID_AMD) || + pci_pcie_type(swus) != PCI_EXP_TYPE_UPSTREAM) return; /* If already saved, return */ if (adev->pcie_reset_ctx.swus) return; /* Upstream bridge is ATI, assume it's SWUS/DS architecture */ - r = pci_save_state(parent); + r = pci_save_state(swds); if (r) return; - adev->pcie_reset_ctx.swds_pcistate = pci_store_saved_state(parent); + adev->pcie_reset_ctx.swds_pcistate = pci_store_saved_state(swds); - parent = pci_upstream_bridge(parent); - r = pci_save_state(parent); + r = pci_save_state(swus); if (r) return; - adev->pcie_reset_ctx.swus_pcistate = pci_store_saved_state(parent); + adev->pcie_reset_ctx.swus_pcistate = pci_store_saved_state(swus); - adev->pcie_reset_ctx.swus = parent; + adev->pcie_reset_ctx.swus = swus; } static void amdgpu_device_load_switch_state(struct amdgpu_device *adev) From 58f1b83c91f4fc13c289f1182fff1ceb588a5a27 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Mon, 29 Sep 2025 16:44:28 +0800 Subject: [PATCH 2182/2653] drm/amdgpu: Fix general protection fault in amdgpu_vm_bo_reset_state_machine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After GPU reset with VRAM loss, a general protection fault occurs during user queue restoration when accessing vm_bo->vm after spinlock release in amdgpu_vm_bo_reset_state_machine. The root cause is that vm_bo points to the last entry from the list_for_each_entry loop, but this becomes invalid after the spinlock is released. Accessing vm_bo->vm at this point leads to memory corruption. Crash log shows: [ 326.981811] Oops: general protection fault, probably for non-canonical address 0x4156415741e58ac8: 0000 [#1] SMP NOPTI [ 326.981820] CPU: 13 UID: 0 PID: 1035 Comm: kworker/13:3 Tainted: G E 6.16.0+ #25 PREEMPT(voluntary) [ 326.981826] Tainted: [E]=UNSIGNED_MODULE [ 326.981827] Hardware name: Gigabyte Technology Co., Ltd. X870E AORUS PRO ICE/X870E AORUS PRO ICE, BIOS F3i 12/19/2024 [ 326.981831] Workqueue: events amdgpu_userq_restore_worker [amdgpu] [ 326.981999] RIP: 0010:amdgpu_vm_assert_locked+0x16/0x70 [amdgpu] [ 326.982094] Code: 00 00 00 00 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 48 85 ff 74 45 48 8b 87 80 03 00 00 48 85 c0 74 40 <48> 8b b8 80 01 00 00 48 85 ff 74 3b 8b 05 0c b7 0e f0 85 c0 75 05 [ 326.982098] RSP: 0018:ffffaa91c2a6bc20 EFLAGS: 00010206 [ 326.982100] RAX: 4156415741e58948 RBX: ffff9e8f013e8330 RCX: 0000000000000000 [ 326.982102] RDX: 0000000000000005 RSI: 000000001d254e88 RDI: ffffffffc144814a [ 326.982104] RBP: ffffaa91c2a6bc68 R08: 0000004c21a25674 R09: 0000000000000001 [ 326.982106] R10: 0000000000000001 R11: dccaf3f2f82863fc R12: ffff9e8f013e8000 [ 326.982108] R13: ffff9e8f013e8000 R14: 0000000000000000 R15: ffff9e8f09980000 [ 326.982110] FS: 0000000000000000(0000) GS:ffff9e9e79995000(0000) knlGS:0000000000000000 [ 326.982112] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 326.982114] CR2: 000055ed6c9caa80 CR3: 0000000797060000 CR4: 0000000000750ef0 [ 326.982116] PKRU: 55555554 Reviewed-by: Christian König Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 33e3bdd4e5609..17d08b51aaf9b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -265,7 +265,7 @@ static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm) vm_bo->moved = true; spin_unlock(&vm->invalidated_lock); - amdgpu_vm_assert_locked(vm_bo->vm); + amdgpu_vm_assert_locked(vm); list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) { struct amdgpu_bo *bo = vm_bo->bo; From c1f7ba7f9ab5a0292502549be42c323f33381952 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Thu, 2 Oct 2025 23:00:45 +0200 Subject: [PATCH 2183/2653] drm/amd/display: Fix unsafe uses of kernel mode FPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The point of isolating code that uses kernel mode FPU in separate compilation units is to ensure that even implicit uses of, e.g., SIMD registers for spilling occur only in a context where this is permitted, i.e., from inside a kernel_fpu_begin/end block. This is important on arm64, which uses -mgeneral-regs-only to build all kernel code, with the exception of such compilation units where FP or SIMD registers are expected to be used. Given that the compiler may invent uses of FP/SIMD anywhere in such a unit, none of its code may be accessible from outside a kernel_fpu_begin/end block. This means that all callers into such compilation units must use the DC_FP start/end macros, which must not occur there themselves. For robustness, all functions with external linkage that reside there should call dc_assert_fp_enabled() to assert that the FPU context was set up correctly. Fix this for the DCN35, DCN351 and DCN36 implementations. Cc: Austin Zheng Cc: Jun Lei Cc: Harry Wentland Cc: Leo Li Cc: Rodrigo Siqueira Cc: Alex Deucher Cc: "Christian König" Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Ard Biesheuvel Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 4 ++++ .../drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 6 ++++-- .../drm/amd/display/dc/dml/dcn351/dcn351_fpu.c | 4 ++-- .../display/dc/resource/dcn35/dcn35_resource.c | 16 +++++++++++++++- .../dc/resource/dcn351/dcn351_resource.c | 17 ++++++++++++++++- .../display/dc/resource/dcn36/dcn36_resource.c | 16 +++++++++++++++- 6 files changed, 56 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c index 17a21bcbde172..1a28061bb9ff7 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c @@ -808,6 +808,8 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param int dcn_get_max_non_odm_pix_rate_100hz(struct _vcs_dpi_soc_bounding_box_st *soc) { + dc_assert_fp_enabled(); + return soc->clock_limits[0].dispclk_mhz * 10000.0 / (1.0 + soc->dcn_downspread_percent / 100.0); } @@ -815,6 +817,8 @@ int dcn_get_approx_det_segs_required_for_pstate( struct _vcs_dpi_soc_bounding_box_st *soc, int pix_clk_100hz, int bpp, int seg_size_kb) { + dc_assert_fp_enabled(); + /* Roughly calculate required crb to hide latency. In practice there is slightly * more buffer available for latency hiding */ diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c index c9dd920744c92..817a370e80a77 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c @@ -445,6 +445,8 @@ int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc, bool upscaled = false; const unsigned int max_allowed_vblank_nom = 1023; + dc_assert_fp_enabled(); + dcn31_populate_dml_pipes_from_context(dc, context, pipes, validate_mode); @@ -498,9 +500,7 @@ int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc, pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; - DC_FP_START(); dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); - DC_FP_END(); pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; pipes[pipe_cnt].pipe.src.dcc_rate = 3; @@ -581,6 +581,8 @@ void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context) unsigned int i, plane_count = 0; DC_LOGGER_INIT(dc->ctx->logger); + dc_assert_fp_enabled(); + for (i = 0; i < dc->res_pool->pipe_count; i++) { if (context->res_ctx.pipe_ctx[i].plane_state) plane_count++; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c index 8cda18ce1a760..77023b619f1e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c @@ -478,6 +478,8 @@ int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc, bool upscaled = false; const unsigned int max_allowed_vblank_nom = 1023; + dc_assert_fp_enabled(); + dcn31_populate_dml_pipes_from_context(dc, context, pipes, validate_mode); @@ -531,9 +533,7 @@ int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc, pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; - DC_FP_START(); dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); - DC_FP_END(); pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; pipes[pipe_cnt].pipe.src.dcc_rate = 3; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c index 07552445e424f..fff57f23f4f7a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c @@ -1760,6 +1760,20 @@ enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_stat } +static int populate_dml_pipes_from_context_fpu(struct dc *dc, + struct dc_state *context, + display_e2e_pipe_params_st *pipes, + enum dc_validate_mode validate_mode) +{ + int ret; + + DC_FP_START(); + ret = dcn35_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode); + DC_FP_END(); + + return ret; +} + static struct resource_funcs dcn35_res_pool_funcs = { .destroy = dcn35_destroy_resource_pool, .link_enc_create = dcn35_link_encoder_create, @@ -1770,7 +1784,7 @@ static struct resource_funcs dcn35_res_pool_funcs = { .validate_bandwidth = dcn35_validate_bandwidth, .calculate_wm_and_dlg = NULL, .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, - .populate_dml_pipes = dcn35_populate_dml_pipes_from_context_fpu, + .populate_dml_pipes = populate_dml_pipes_from_context_fpu, .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c index cb0478a9a34da..0abd163b425e5 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c @@ -1732,6 +1732,21 @@ static enum dc_status dcn351_validate_bandwidth(struct dc *dc, return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; } +static int populate_dml_pipes_from_context_fpu(struct dc *dc, + struct dc_state *context, + display_e2e_pipe_params_st *pipes, + enum dc_validate_mode validate_mode) +{ + int ret; + + DC_FP_START(); + ret = dcn351_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode); + DC_FP_END(); + + return ret; + +} + static struct resource_funcs dcn351_res_pool_funcs = { .destroy = dcn351_destroy_resource_pool, .link_enc_create = dcn35_link_encoder_create, @@ -1742,7 +1757,7 @@ static struct resource_funcs dcn351_res_pool_funcs = { .validate_bandwidth = dcn351_validate_bandwidth, .calculate_wm_and_dlg = NULL, .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, - .populate_dml_pipes = dcn351_populate_dml_pipes_from_context_fpu, + .populate_dml_pipes = populate_dml_pipes_from_context_fpu, .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c index 126090c9bb8a8..ca125ee6c2fb3 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c @@ -1734,6 +1734,20 @@ static enum dc_status dcn35_validate_bandwidth(struct dc *dc, } +static int populate_dml_pipes_from_context_fpu(struct dc *dc, + struct dc_state *context, + display_e2e_pipe_params_st *pipes, + enum dc_validate_mode validate_mode) +{ + int ret; + + DC_FP_START(); + ret = dcn35_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode); + DC_FP_END(); + + return ret; +} + static struct resource_funcs dcn36_res_pool_funcs = { .destroy = dcn36_destroy_resource_pool, .link_enc_create = dcn35_link_encoder_create, @@ -1744,7 +1758,7 @@ static struct resource_funcs dcn36_res_pool_funcs = { .validate_bandwidth = dcn35_validate_bandwidth, .calculate_wm_and_dlg = NULL, .update_soc_for_wm_a = dcn31_update_soc_for_wm_a, - .populate_dml_pipes = dcn35_populate_dml_pipes_from_context_fpu, + .populate_dml_pipes = populate_dml_pipes_from_context_fpu, .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, From 31123f951a143d59d636aeea56edaacacf492671 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 6 Oct 2025 10:39:03 +0530 Subject: [PATCH 2184/2653] drm/amdgpu: Report individual reset error If reinitialization of one of the GPUs fails after reset, it logs failure on all subsequent GPUs eventhough they have resumed successfully. A sample log where only device at 0000:95:00.0 had a failure - amdgpu 0000:15:00.0: amdgpu: GPU reset(19) succeeded! amdgpu 0000:65:00.0: amdgpu: GPU reset(19) succeeded! amdgpu 0000:75:00.0: amdgpu: GPU reset(19) succeeded! amdgpu 0000:85:00.0: amdgpu: GPU reset(19) succeeded! amdgpu 0000:95:00.0: amdgpu: GPU reset(19) failed amdgpu 0000:e5:00.0: amdgpu: GPU reset(19) failed amdgpu 0000:f5:00.0: amdgpu: GPU reset(19) failed amdgpu 0000:05:00.0: amdgpu: GPU reset(19) failed amdgpu 0000:15:00.0: amdgpu: GPU reset end with ret = -5 To avoid confusion, report the error for each device separately and return the first error as the overall result. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 25 +++++++++++++--------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 9bb1133b16b8f..a221678e893e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6442,23 +6442,28 @@ static int amdgpu_device_sched_resume(struct list_head *device_list, if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled) drm_helper_resume_force_mode(adev_to_drm(tmp_adev)); - if (tmp_adev->asic_reset_res) - r = tmp_adev->asic_reset_res; - - tmp_adev->asic_reset_res = 0; - - if (r) { + if (tmp_adev->asic_reset_res) { /* bad news, how to tell it to userspace ? * for ras error, we should report GPU bad status instead of * reset failure */ if (reset_context->src != AMDGPU_RESET_SRC_RAS || !amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) - dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", - atomic_read(&tmp_adev->gpu_reset_counter)); - amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); + dev_info( + tmp_adev->dev, + "GPU reset(%d) failed with error %d \n", + atomic_read( + &tmp_adev->gpu_reset_counter), + tmp_adev->asic_reset_res); + amdgpu_vf_error_put(tmp_adev, + AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, + tmp_adev->asic_reset_res); + if (!r) + r = tmp_adev->asic_reset_res; + tmp_adev->asic_reset_res = 0; } else { - dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter)); + dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", + atomic_read(&tmp_adev->gpu_reset_counter)); if (amdgpu_acpi_smart_shift_update(tmp_adev, AMDGPU_SS_DEV_D0)) dev_warn(tmp_adev->dev, From 2db5414c773dd1833a1921f39caf741c98705d56 Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Tue, 22 Jul 2025 11:14:28 +0800 Subject: [PATCH 2185/2653] drm/amdgpu/userq: extend userq state Extend the userq state for identifying the userq invalid cases. Signed-off-by: Prike Liang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index 70895c10276d3..f2bee4ed5d10a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -37,6 +37,7 @@ enum amdgpu_userq_state { AMDGPU_USERQ_STATE_MAPPED, AMDGPU_USERQ_STATE_PREEMPTED, AMDGPU_USERQ_STATE_HUNG, + AMDGPU_USERQ_STATE_INVALID_VA, }; struct amdgpu_mqd_prop; From 9be93730f0dd9ba4a0aba4bc2067e0fb6aaebcca Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 16 Sep 2025 11:20:42 +0530 Subject: [PATCH 2186/2653] drm/amdgpu: Remove redundant return value gfx_v9_4_3_xcc_kcq_init_queue doesn't have a fail condition. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 59cba26049f17..72cdaacead31e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2176,7 +2176,8 @@ static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) return 0; } -static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, bool restore) +static void gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, + bool restore) { struct amdgpu_device *adev = ring->adev; struct v9_mqd *mqd = ring->mqd_ptr; @@ -2210,8 +2211,6 @@ static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, b atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); amdgpu_ring_clear_ring(ring); } - - return 0; } static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) @@ -2244,7 +2243,7 @@ static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) { struct amdgpu_ring *ring; - int i, r; + int i; gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); @@ -2252,9 +2251,7 @@ static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; - r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false); - if (r) - return r; + gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false); } return amdgpu_gfx_enable_kcq(adev, xcc_id); @@ -3769,11 +3766,8 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, return r; } - r = gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true); - if (r) { - dev_err(adev->dev, "fail to init kcq\n"); - return r; - } + gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true); + spin_lock_irqsave(&kiq->ring_lock, flags); r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); if (r) { From 6657253d1dcf3c0a0377ee9d5b3ccf5777545a82 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Fri, 5 Sep 2025 10:19:29 +0200 Subject: [PATCH 2187/2653] drm/amdgpu: make non-NULL out fence mandatory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit amdgpu_ttm_copy_mem_to_mem has a single caller, make sure the out fence is non-NULL to simplify the code. Since none of the pointers should be NULL, we can enable __attribute__((nonnull))__. While at it make the function static since it's only used from amdgpuu_ttm.c. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 17 ++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 6 ------ 2 files changed, 8 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index a7d108f64e15f..820ad6266db80 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -315,12 +315,13 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, * move and different for a BO to BO copy. * */ -int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, - const struct amdgpu_copy_mem *src, - const struct amdgpu_copy_mem *dst, - uint64_t size, bool tmz, - struct dma_resv *resv, - struct dma_fence **f) +__attribute__((nonnull)) +static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, + const struct amdgpu_copy_mem *src, + const struct amdgpu_copy_mem *dst, + uint64_t size, bool tmz, + struct dma_resv *resv, + struct dma_fence **f) { struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; struct amdgpu_res_cursor src_mm, dst_mm; @@ -394,9 +395,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, } error: mutex_unlock(&adev->mman.gtt_window_lock); - if (f) - *f = dma_fence_get(fence); - dma_fence_put(fence); + *f = fence; return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 60cf8588a6b81..4df65ac85dc5f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -183,12 +183,6 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, struct dma_resv *resv, struct dma_fence **fence, bool direct_submit, bool vm_needs_flush, uint32_t copy_flags); -int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, - const struct amdgpu_copy_mem *src, - const struct amdgpu_copy_mem *dst, - uint64_t size, bool tmz, - struct dma_resv *resv, - struct dma_fence **f); int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, struct dma_resv *resv, struct dma_fence **fence); From dd889a641ca5ed2dc21ec04c47b67e67e4e931c8 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 30 Sep 2025 13:45:11 +0530 Subject: [PATCH 2188/2653] drm/amdgpu: clean up amdgpu hmm range functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clean up the amdgpu hmm range functions for clearer definition of each. a. Split amdgpu_ttm_tt_get_user_pages_done into two: 1. amdgpu_hmm_range_valid: To check if the user pages are valid and update seq num 2. amdgpu_hmm_range_free: Clean up the hmm range and pfn memory. b. amdgpu_ttm_tt_get_user_pages_done and amdgpu_ttm_tt_discard_user_pages are similar function so remove discard and directly use amdgpu_hmm_range_free to clean up the hmm range and pfn memory. Suggested-by: Christian König Signed-off-by: Sunil Khatri Reviewed-by: Christian König Change-Id: I88a09440b1ba09c159a8996b4a3c550579ae6e5c --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 18 ++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 10 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 6 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 23 ++++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 17 ++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 38 ------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 13 ------- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 9 +++-- 8 files changed, 55 insertions(+), 79 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 44d5a9e6d5ad5..253b663c088a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1153,7 +1153,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, } #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - range = kzalloc(sizeof(*range), GFP_KERNEL); + range = amdgpu_hmm_range_alloc(); if (unlikely(!range)) { ret = -ENOMEM; goto unregister_out; @@ -1161,7 +1161,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, ret = amdgpu_ttm_tt_get_user_pages(bo, range); if (ret) { - kfree(range); + amdgpu_hmm_range_free(range); if (ret == -EAGAIN) pr_debug("Failed to get user pages, try again\n"); else @@ -1210,7 +1210,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, release_out: #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); + amdgpu_hmm_range_free(range); #else if (ret) amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, NULL); @@ -2032,7 +2032,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( amdgpu_hmm_unregister(mem->bo); #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mutex_lock(&process_info->notifier_lock); - amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range); + amdgpu_hmm_range_free(mem->range); mutex_unlock(&process_info->notifier_lock); #else /* Free user pages if necessary */ @@ -2925,7 +2925,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, bo = mem->bo; #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range); + amdgpu_hmm_range_free(mem->range); mem->range = NULL; #endif @@ -2951,13 +2951,13 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, } #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - mem->range = kzalloc(sizeof(*mem->range), GFP_KERNEL); + mem->range = amdgpu_hmm_range_alloc(); if (unlikely(!mem->range)) return -ENOMEM; /* Get updated user pages */ ret = amdgpu_ttm_tt_get_user_pages(bo, mem->range); if (ret) { - kfree(mem->range); + amdgpu_hmm_range_free(mem->range); mem->range = NULL; pr_debug("Failed %d to get user pages\n", ret); @@ -3189,8 +3189,8 @@ static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_i continue; /* Only check mem with hmm range associated */ - valid = amdgpu_ttm_tt_get_user_pages_done( - mem->bo->tbo.ttm, mem->range); + valid = amdgpu_hmm_range_valid(mem->range); + amdgpu_hmm_range_free(mem->range); mem->range = NULL; if (!valid) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index a484f9212c573..d209d17a08ee8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -910,7 +910,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, bool userpage_invalidated = false; struct amdgpu_bo *bo = e->bo; - e->range = kzalloc(sizeof(*e->range), GFP_KERNEL); + e->range = amdgpu_hmm_range_alloc(); if (unlikely(!e->range)) return -ENOMEM; @@ -1104,9 +1104,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, out_free_user_pages: #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { - struct amdgpu_bo *bo = e->bo; - - amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, e->range); + amdgpu_hmm_range_free(e->range); e->range = NULL; } #else @@ -1456,8 +1454,8 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, */ r = 0; amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { - r |= !amdgpu_ttm_tt_get_user_pages_done(e->bo->tbo.ttm, - e->range); + r |= !amdgpu_hmm_range_valid(e->range); + amdgpu_hmm_range_free(e->range); e->range = NULL; } if (r) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 0ea9ab4c0b26c..478184576f0ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -644,7 +644,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - range = kzalloc(sizeof(*range), GFP_KERNEL); + range = amdgpu_hmm_range_alloc(); if (unlikely(!range)) return -ENOMEM; r = amdgpu_ttm_tt_get_user_pages(bo, range); @@ -654,7 +654,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, #endif if (r) { #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - kfree(range); + amdgpu_hmm_range_free(range); #endif goto release_object; } @@ -692,7 +692,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, user_pages_done: #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) - amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); + amdgpu_hmm_range_free(range); #else release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 14e62c2be1149..55b2359799ae4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -919,19 +919,30 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, return r; } -bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range) +bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range) { - bool r; + if (!hmm_range) + return false; + + return !mmu_interval_read_retry(hmm_range->notifier, + hmm_range->notifier_seq); +} + +struct hmm_range *amdgpu_hmm_range_alloc(void) +{ + return kzalloc(sizeof(struct hmm_range), GFP_KERNEL); +} + +void amdgpu_hmm_range_free(struct hmm_range *hmm_range) +{ + if (!hmm_range) + return; - r = mmu_interval_read_retry(hmm_range->notifier, - hmm_range->notifier_seq); #ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT kvfree(hmm_range->pfns); #else kvfree(hmm_range->hmm_pfns); #endif kfree(hmm_range); - - return r; } #endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index e078aa4905e38..4ec014a918514 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -87,9 +87,11 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, void *owner, struct hmm_range *hmm_range); -bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range); #if defined(CONFIG_HMM_MIRROR) +bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range); +struct hmm_range *amdgpu_hmm_range_alloc(void); +void amdgpu_hmm_range_free(struct hmm_range *hmm_range); int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr); void amdgpu_hmm_unregister(struct amdgpu_bo *bo); #else @@ -99,7 +101,20 @@ static inline int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) "add CONFIG_ZONE_DEVICE=y in config file to fix this\n"); return -ENODEV; } + static inline void amdgpu_hmm_unregister(struct amdgpu_bo *bo) {} + +static inline bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range) +{ + return false; +} + +static inline struct hmm_range *amdgpu_hmm_range_alloc(void) +{ + return NULL; +} + +static inline void amdgpu_hmm_range_free(struct hmm_range *hmm_range) {} #endif #endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 820ad6266db80..271a342bae40b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -826,44 +826,6 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, return r; } -/* amdgpu_ttm_tt_discard_user_pages - Discard range and pfn array allocations - */ -void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, - struct hmm_range *range) -{ - struct amdgpu_ttm_tt *gtt = (void *)ttm; - - if (gtt && gtt->userptr && range) - amdgpu_hmm_range_get_pages_done(range); -} - -/* - * amdgpu_ttm_tt_get_user_pages_done - stop HMM track the CPU page table change - * Check if the pages backing this ttm range have been invalidated - * - * Returns: true if pages are still valid - */ -bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, - struct hmm_range *range) -{ - struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); - - if (!gtt || !gtt->userptr || !range) - return false; - - DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", - gtt->userptr, ttm->num_pages); - -#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT - WARN_ONCE(!range->pfns, -#else - WARN_ONCE(!range->hmm_pfns, -#endif - "No user pages to check\n"); - - return !amdgpu_hmm_range_get_pages_done(range); -} - #else /* * amdgpu_ttm_tt_get_user_pages - Pin pages of memory pointed to by a USERPTR diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 4df65ac85dc5f..848568bb83d86 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -208,10 +208,6 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, struct hmm_range **range); #endif -void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, - struct hmm_range *range); -bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, - struct hmm_range *range); #else #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, @@ -226,15 +222,6 @@ static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page return -EPERM; } #endif -static inline void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, - struct hmm_range *range) -{ -} -static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, - struct hmm_range *range) -{ - return false; -} #endif #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 5492b0e74260f..5639a51212e05 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1741,13 +1741,13 @@ static int svm_range_validate_and_map(struct mm_struct *mm, } WRITE_ONCE(p->svms.faulting_task, current); - hmm_range = kzalloc(sizeof(*hmm_range), GFP_KERNEL); + hmm_range = amdgpu_hmm_range_alloc(); r = amdgpu_hmm_range_get_pages(&prange->notifier, addr, npages, readonly, owner, hmm_range); WRITE_ONCE(p->svms.faulting_task, NULL); if (r) { - kfree(hmm_range); + amdgpu_hmm_range_free(hmm_range); pr_debug("failed %d to get svm range pages\n", r); } } else { @@ -1768,10 +1768,13 @@ static int svm_range_validate_and_map(struct mm_struct *mm, * Overrride return value to TRY AGAIN only if prior returns * were successful */ - if (hmm_range && amdgpu_hmm_range_get_pages_done(hmm_range) && !r) { + if (hmm_range && !amdgpu_hmm_range_valid(hmm_range) && !r) { pr_debug("hmm update the range, need validate again\n"); r = -EAGAIN; } + /* Free the hmm range */ + amdgpu_hmm_range_free(hmm_range); + if (!r && !list_empty(&prange->child_list)) { pr_debug("range split by unmap in parallel, validate again\n"); From 85aa9d615ec979171eb97b2d5d1df06fb9c39e78 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 6 Oct 2025 12:45:25 +0200 Subject: [PATCH 2189/2653] drm/amdgpu: partially revert "revert to old status lock handling v3" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The CI systems are pointing out list corruptions, so we still need to fix something here. Keep the asserts, but revert the lock changes for now. Signed-off-by: Christian König Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 146 ++++++++++++++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 15 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 4 + 4 files changed, 105 insertions(+), 68 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 7ba1ad907e2dc..72ae7c346738f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -731,12 +731,12 @@ amdgpu_userq_bo_validate(struct amdgpu_device *adev, struct drm_exec *exec, struct amdgpu_bo *bo; int ret; - spin_lock(&vm->invalidated_lock); + spin_lock(&vm->status_lock); while (!list_empty(&vm->invalidated)) { bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, base.vm_status); - spin_unlock(&vm->invalidated_lock); + spin_unlock(&vm->status_lock); bo = bo_va->base.bo; ret = drm_exec_prepare_obj(exec, &bo->tbo.base, 2); @@ -753,9 +753,9 @@ amdgpu_userq_bo_validate(struct amdgpu_device *adev, struct drm_exec *exec, if (ret) return ret; - spin_lock(&vm->invalidated_lock); + spin_lock(&vm->status_lock); } - spin_unlock(&vm->invalidated_lock); + spin_unlock(&vm->status_lock); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 17d08b51aaf9b..4a3e24dbe95fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -153,10 +153,12 @@ static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo) vm_bo->moved = true; amdgpu_vm_assert_locked(vm); + spin_lock(&vm_bo->vm->status_lock); if (bo->tbo.type == ttm_bo_type_kernel) list_move(&vm_bo->vm_status, &vm->evicted); else list_move_tail(&vm_bo->vm_status, &vm->evicted); + spin_unlock(&vm_bo->vm->status_lock); } /** * amdgpu_vm_bo_moved - vm_bo is moved @@ -169,7 +171,9 @@ static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo) static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo) { amdgpu_vm_assert_locked(vm_bo->vm); + spin_lock(&vm_bo->vm->status_lock); list_move(&vm_bo->vm_status, &vm_bo->vm->moved); + spin_unlock(&vm_bo->vm->status_lock); } /** @@ -183,7 +187,9 @@ static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo) static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo) { amdgpu_vm_assert_locked(vm_bo->vm); + spin_lock(&vm_bo->vm->status_lock); list_move(&vm_bo->vm_status, &vm_bo->vm->idle); + spin_unlock(&vm_bo->vm->status_lock); vm_bo->moved = false; } @@ -197,9 +203,9 @@ static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo) */ static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo) { - spin_lock(&vm_bo->vm->invalidated_lock); + spin_lock(&vm_bo->vm->status_lock); list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated); - spin_unlock(&vm_bo->vm->invalidated_lock); + spin_unlock(&vm_bo->vm->status_lock); } /** @@ -212,9 +218,10 @@ static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo) */ static void amdgpu_vm_bo_evicted_user(struct amdgpu_vm_bo_base *vm_bo) { - amdgpu_vm_assert_locked(vm_bo->vm); vm_bo->moved = true; + spin_lock(&vm_bo->vm->status_lock); list_move(&vm_bo->vm_status, &vm_bo->vm->evicted_user); + spin_unlock(&vm_bo->vm->status_lock); } /** @@ -228,10 +235,13 @@ static void amdgpu_vm_bo_evicted_user(struct amdgpu_vm_bo_base *vm_bo) static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo) { amdgpu_vm_assert_locked(vm_bo->vm); - if (vm_bo->bo->parent) + if (vm_bo->bo->parent) { + spin_lock(&vm_bo->vm->status_lock); list_move(&vm_bo->vm_status, &vm_bo->vm->relocated); - else + spin_unlock(&vm_bo->vm->status_lock); + } else { amdgpu_vm_bo_idle(vm_bo); + } } /** @@ -245,7 +255,9 @@ static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo) static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo) { amdgpu_vm_assert_locked(vm_bo->vm); + spin_lock(&vm_bo->vm->status_lock); list_move(&vm_bo->vm_status, &vm_bo->vm->done); + spin_unlock(&vm_bo->vm->status_lock); } /** @@ -259,13 +271,13 @@ static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm) { struct amdgpu_vm_bo_base *vm_bo, *tmp; - spin_lock(&vm->invalidated_lock); + amdgpu_vm_assert_locked(vm); + + spin_lock(&vm->status_lock); list_splice_init(&vm->done, &vm->invalidated); list_for_each_entry(vm_bo, &vm->invalidated, vm_status) vm_bo->moved = true; - spin_unlock(&vm->invalidated_lock); - amdgpu_vm_assert_locked(vm); list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) { struct amdgpu_bo *bo = vm_bo->bo; @@ -275,13 +287,14 @@ static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm) else if (bo->parent) list_move(&vm_bo->vm_status, &vm_bo->vm->relocated); } + spin_unlock(&vm->status_lock); } /** * amdgpu_vm_update_shared - helper to update shared memory stat * @base: base structure for tracking BO usage in a VM * - * Takes the vm stats_lock and updates the shared memory stat. If the basic + * Takes the vm status_lock and updates the shared memory stat. If the basic * stat changed (e.g. buffer was moved) amdgpu_vm_update_stats need to be called * as well. */ @@ -294,7 +307,7 @@ static void amdgpu_vm_update_shared(struct amdgpu_vm_bo_base *base) bool shared; dma_resv_assert_held(bo->tbo.base.resv); - spin_lock(&vm->stats_lock); + spin_lock(&vm->status_lock); shared = drm_gem_object_is_shared_for_memory_stats(&bo->tbo.base); if (base->shared != shared) { base->shared = shared; @@ -306,7 +319,7 @@ static void amdgpu_vm_update_shared(struct amdgpu_vm_bo_base *base) vm->stats[bo_memtype].drm.private += size; } } - spin_unlock(&vm->stats_lock); + spin_unlock(&vm->status_lock); } /** @@ -331,11 +344,11 @@ void amdgpu_vm_bo_update_shared(struct amdgpu_bo *bo) * be bo->tbo.resource * @sign: if we should add (+1) or subtract (-1) from the stat * - * Caller need to have the vm stats_lock held. Useful for when multiple update + * Caller need to have the vm status_lock held. Useful for when multiple update * need to happen at the same time. */ static void amdgpu_vm_update_stats_locked(struct amdgpu_vm_bo_base *base, - struct ttm_resource *res, int sign) + struct ttm_resource *res, int sign) { struct amdgpu_vm *vm = base->vm; struct amdgpu_bo *bo = base->bo; @@ -359,8 +372,7 @@ static void amdgpu_vm_update_stats_locked(struct amdgpu_vm_bo_base *base, */ if (bo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) vm->stats[res_memtype].drm.purgeable += size; - if (!(bo->preferred_domains & - amdgpu_mem_type_to_domain(res_memtype))) + if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(res_memtype))) vm->stats[bo_memtype].evicted += size; } } @@ -379,9 +391,9 @@ void amdgpu_vm_update_stats(struct amdgpu_vm_bo_base *base, { struct amdgpu_vm *vm = base->vm; - spin_lock(&vm->stats_lock); + spin_lock(&vm->status_lock); amdgpu_vm_update_stats_locked(base, res, sign); - spin_unlock(&vm->stats_lock); + spin_unlock(&vm->status_lock); } /** @@ -407,10 +419,10 @@ void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, base->next = bo->vm_bo; bo->vm_bo = base; - spin_lock(&vm->stats_lock); + spin_lock(&vm->status_lock); base->shared = drm_gem_object_is_shared_for_memory_stats(&bo->tbo.base); amdgpu_vm_update_stats_locked(base, bo->tbo.resource, +1); - spin_unlock(&vm->stats_lock); + spin_unlock(&vm->status_lock); if (!amdgpu_vm_is_bo_always_valid(vm, bo)) return; @@ -469,10 +481,10 @@ int amdgpu_vm_lock_done_list(struct amdgpu_vm *vm, struct drm_exec *exec, int ret; /* We can only trust prev->next while holding the lock */ - spin_lock(&vm->invalidated_lock); + spin_lock(&vm->status_lock); while (!list_is_head(prev->next, &vm->done)) { bo_va = list_entry(prev->next, typeof(*bo_va), base.vm_status); - spin_unlock(&vm->invalidated_lock); + spin_unlock(&vm->status_lock); bo = bo_va->base.bo; if (bo) { @@ -480,10 +492,10 @@ int amdgpu_vm_lock_done_list(struct amdgpu_vm *vm, struct drm_exec *exec, if (unlikely(ret)) return ret; } - spin_lock(&vm->invalidated_lock); + spin_lock(&vm->status_lock); prev = prev->next; } - spin_unlock(&vm->invalidated_lock); + spin_unlock(&vm->status_lock); return 0; } @@ -579,7 +591,7 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, void *param) { uint64_t new_vm_generation = amdgpu_vm_generation(adev, vm); - struct amdgpu_vm_bo_base *bo_base, *tmp; + struct amdgpu_vm_bo_base *bo_base; struct amdgpu_bo *bo; int r; @@ -592,7 +604,13 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, return r; } - list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) { + spin_lock(&vm->status_lock); + while (!list_empty(&vm->evicted)) { + bo_base = list_first_entry(&vm->evicted, + struct amdgpu_vm_bo_base, + vm_status); + spin_unlock(&vm->status_lock); + bo = bo_base->bo; r = validate(param, bo); @@ -605,21 +623,26 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, vm->update_funcs->map_table(to_amdgpu_bo_vm(bo)); amdgpu_vm_bo_relocated(bo_base); } + spin_lock(&vm->status_lock); } + while (ticket && !list_empty(&vm->evicted_user)) { + bo_base = list_first_entry(&vm->evicted_user, + struct amdgpu_vm_bo_base, + vm_status); + spin_unlock(&vm->status_lock); - if (ticket) { - list_for_each_entry_safe(bo_base, tmp, &vm->evicted_user, - vm_status) { - bo = bo_base->bo; - dma_resv_assert_held(bo->tbo.base.resv); + bo = bo_base->bo; + dma_resv_assert_held(bo->tbo.base.resv); - r = validate(param, bo); - if (r) - return r; + r = validate(param, bo); + if (r) + return r; - amdgpu_vm_bo_invalidated(bo_base); - } + amdgpu_vm_bo_invalidated(bo_base); + + spin_lock(&vm->status_lock); } + spin_unlock(&vm->status_lock); amdgpu_vm_eviction_lock(vm); vm->evicting = false; @@ -648,7 +671,9 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm) ret = !vm->evicting; amdgpu_vm_eviction_unlock(vm); + spin_lock(&vm->status_lock); ret &= list_empty(&vm->evicted); + spin_unlock(&vm->status_lock); spin_lock(&vm->immediate.lock); ret &= !vm->immediate.stopped; @@ -939,13 +964,18 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev, struct amdgpu_vm *vm, bool immediate) { struct amdgpu_vm_update_params params; - struct amdgpu_vm_bo_base *entry, *tmp; + struct amdgpu_vm_bo_base *entry; bool flush_tlb_needed = false; + LIST_HEAD(relocated); int r, idx; amdgpu_vm_assert_locked(vm); - if (list_empty(&vm->relocated)) + spin_lock(&vm->status_lock); + list_splice_init(&vm->relocated, &relocated); + spin_unlock(&vm->status_lock); + + if (list_empty(&relocated)) return 0; if (!drm_dev_enter(adev_to_drm(adev), &idx)) @@ -960,7 +990,7 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev, if (r) goto error; - list_for_each_entry(entry, &vm->relocated, vm_status) { + list_for_each_entry(entry, &relocated, vm_status) { /* vm_flush_needed after updating moved PDEs */ flush_tlb_needed |= entry->moved; @@ -976,7 +1006,9 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev, if (flush_tlb_needed) atomic64_inc(&vm->tlb_seq); - list_for_each_entry_safe(entry, tmp, &vm->relocated, vm_status) { + while (!list_empty(&relocated)) { + entry = list_first_entry(&relocated, struct amdgpu_vm_bo_base, + vm_status); amdgpu_vm_bo_idle(entry); } @@ -1216,9 +1248,9 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, void amdgpu_vm_get_memory(struct amdgpu_vm *vm, struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM]) { - spin_lock(&vm->stats_lock); + spin_lock(&vm->status_lock); memcpy(stats, vm->stats, sizeof(*stats) * __AMDGPU_PL_NUM); - spin_unlock(&vm->stats_lock); + spin_unlock(&vm->status_lock); } /** @@ -1598,24 +1630,29 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket) { - struct amdgpu_bo_va *bo_va, *tmp; + struct amdgpu_bo_va *bo_va; struct dma_resv *resv; bool clear, unlock; int r; - list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) { + spin_lock(&vm->status_lock); + while (!list_empty(&vm->moved)) { + bo_va = list_first_entry(&vm->moved, struct amdgpu_bo_va, + base.vm_status); + spin_unlock(&vm->status_lock); + /* Per VM BOs never need to bo cleared in the page tables */ r = amdgpu_vm_bo_update(adev, bo_va, false); if (r) return r; + spin_lock(&vm->status_lock); } - spin_lock(&vm->invalidated_lock); while (!list_empty(&vm->invalidated)) { bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, base.vm_status); resv = amdkcl_ttm_resvp(&bo_va->base.bo->tbo); - spin_unlock(&vm->invalidated_lock); + spin_unlock(&vm->status_lock); /* Try to reserve the BO to avoid clearing its ptes */ if (!adev->debug_vm && dma_resv_trylock(resv)) { @@ -1647,9 +1684,9 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev, bo_va->base.bo->tbo.resource->mem_type == TTM_PL_SYSTEM)) amdgpu_vm_bo_evicted_user(&bo_va->base); - spin_lock(&vm->invalidated_lock); + spin_lock(&vm->status_lock); } - spin_unlock(&vm->invalidated_lock); + spin_unlock(&vm->status_lock); return 0; } @@ -2178,9 +2215,9 @@ void amdgpu_vm_bo_del(struct amdgpu_device *adev, } } - spin_lock(&vm->invalidated_lock); + spin_lock(&vm->status_lock); list_del(&bo_va->base.vm_status); - spin_unlock(&vm->invalidated_lock); + spin_unlock(&vm->status_lock); list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { list_del(&mapping->list); @@ -2288,10 +2325,10 @@ void amdgpu_vm_bo_move(struct amdgpu_bo *bo, struct ttm_resource *new_mem, for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { struct amdgpu_vm *vm = bo_base->vm; - spin_lock(&vm->stats_lock); + spin_lock(&vm->status_lock); amdgpu_vm_update_stats_locked(bo_base, bo->tbo.resource, -1); amdgpu_vm_update_stats_locked(bo_base, new_mem, +1); - spin_unlock(&vm->stats_lock); + spin_unlock(&vm->status_lock); } amdgpu_vm_bo_invalidate(bo, evicted); @@ -2569,12 +2606,11 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, INIT_LIST_HEAD(&vm->relocated); INIT_LIST_HEAD(&vm->moved); INIT_LIST_HEAD(&vm->idle); - spin_lock_init(&vm->invalidated_lock); INIT_LIST_HEAD(&vm->invalidated); + spin_lock_init(&vm->status_lock); INIT_LIST_HEAD(&vm->freed); INIT_LIST_HEAD(&vm->done); INIT_KFIFO(vm->faults); - spin_lock_init(&vm->stats_lock); r = amdgpu_vm_init_entities(adev, vm); if (r) @@ -3086,6 +3122,7 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m) amdgpu_vm_assert_locked(vm); + spin_lock(&vm->status_lock); seq_puts(m, "\tIdle BOs:\n"); list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) { if (!bo_va->base.bo) @@ -3123,13 +3160,11 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m) id = 0; seq_puts(m, "\tInvalidated BOs:\n"); - spin_lock(&vm->invalidated_lock); list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) { if (!bo_va->base.bo) continue; total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m); } - spin_unlock(&vm->invalidated_lock); total_invalidated_objs = id; id = 0; @@ -3139,6 +3174,7 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m) continue; total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m); } + spin_unlock(&vm->status_lock); total_done_objs = id; seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 8cc74a30af1bf..12812408298e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -203,11 +203,11 @@ struct amdgpu_vm_bo_base { /* protected by bo being reserved */ struct amdgpu_vm_bo_base *next; - /* protected by vm reservation and invalidated_lock */ + /* protected by vm status_lock */ struct list_head vm_status; /* if the bo is counted as shared in mem stats - * protected by vm BO being reserved */ + * protected by vm status_lock */ bool shared; /* protected by the BO being reserved */ @@ -347,8 +347,10 @@ struct amdgpu_vm { bool evicting; unsigned int saved_flags; - /* Memory statistics for this vm, protected by stats_lock */ - spinlock_t stats_lock; + /* Lock to protect vm_bo add/del/move on all lists of vm */ + spinlock_t status_lock; + + /* Memory statistics for this vm, protected by status_lock */ struct amdgpu_mem_stats stats[__AMDGPU_PL_NUM]; /* @@ -356,8 +358,6 @@ struct amdgpu_vm { * PDs, PTs or per VM BOs. The state transits are: * * evicted -> relocated (PDs, PTs) or moved (per VM BOs) -> idle - * - * Lists are protected by the root PD dma_resv lock. */ /* Per-VM and PT BOs who needs a validation */ @@ -378,10 +378,7 @@ struct amdgpu_vm { * state transits are: * * evicted_user or invalidated -> done - * - * Lists are protected by the invalidated_lock. */ - spinlock_t invalidated_lock; /* BOs for user mode queues that need a validation */ struct list_head evicted_user; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c index 528c5a100716b..10f31d6bd6a46 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c @@ -541,7 +541,9 @@ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry) entry->bo->vm_bo = NULL; ttm_bo_set_bulk_move(&entry->bo->tbo, NULL); + spin_lock(&entry->vm->status_lock); list_del(&entry->vm_status); + spin_unlock(&entry->vm->status_lock); amdgpu_bo_unref(&entry->bo); } @@ -585,6 +587,7 @@ static void amdgpu_vm_pt_add_list(struct amdgpu_vm_update_params *params, struct amdgpu_vm_pt_cursor seek; struct amdgpu_vm_bo_base *entry; + spin_lock(¶ms->vm->status_lock); for_each_amdgpu_vm_pt_dfs_safe(params->adev, params->vm, cursor, seek, entry) { if (entry && entry->bo) list_move(&entry->vm_status, ¶ms->tlb_flush_waitlist); @@ -592,6 +595,7 @@ static void amdgpu_vm_pt_add_list(struct amdgpu_vm_update_params *params, /* enter start node now */ list_move(&cursor->entry->vm_status, ¶ms->tlb_flush_waitlist); + spin_unlock(¶ms->vm->status_lock); } /** From c232e44acf78360688438a31ca90b8c463fd6bd8 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Mon, 15 Sep 2025 14:25:44 +0200 Subject: [PATCH 2190/2653] drm/amdgpu: remove gart_window_lock usage from gmc v12 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This lock was part of the SDMA workaround originally implemented in gmc_v10_0_flush_gpu_tlb (a70cb2176f7ef6f moved it to amdgpu_gmc_flush_gpu_tlb). This means this lock is useless and be safely dropped. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index f4a19357ccbc6..cad2d19105c4c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -312,9 +312,7 @@ static void gmc_v12_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, return; } - mutex_lock(&adev->mman.gtt_window_lock); gmc_v12_0_flush_vm_hub(adev, vmid, vmhub, 0); - mutex_unlock(&adev->mman.gtt_window_lock); return; } From 4700397f4071ddb5c38003efb0d52b2e9336a544 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 8 Oct 2025 10:26:47 +0530 Subject: [PATCH 2191/2653] drm/amdgpu: Skip SDMA suspend during mode-2 reset For SDMA IP versions >= v4.4.2, firmware will take care of quiescing SDMA before mode-2 reset. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/aldebaran.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c b/drivers/gpu/drm/amd/amdgpu/aldebaran.c index 9569dc16dd3da..daa7b23bc7750 100644 --- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c @@ -88,6 +88,10 @@ static int aldebaran_mode2_suspend_ip(struct amdgpu_device *adev) uint32_t ip_block; int r, i; + /* Skip suspend of SDMA IP versions >= 4.4.2. They are multi-aid */ + if (adev->aid_mask) + ip_block_mask &= ~BIT(AMD_IP_BLOCK_TYPE_SDMA); + amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); From a057a1e4772bca4fb3ef77beaf3b875be0bfdfad Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 6 Oct 2025 14:23:59 -0400 Subject: [PATCH 2192/2653] drm/amdgpu/mes: adjust the VMID masks The firmware limits the max vmid, but align the settings with the hw limits as well just to be safe. Reviewed-by: Shaoyun liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 5bf9be073cddf..8d03e8c9cc6dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -105,8 +105,8 @@ int amdgpu_mes_init(struct amdgpu_device *adev) spin_lock_init(&adev->mes.ring_lock[i]); adev->mes.total_max_queue = AMDGPU_FENCE_MES_QUEUE_ID_MASK; - adev->mes.vmid_mask_mmhub = 0xffffff00; - adev->mes.vmid_mask_gfxhub = adev->gfx.disable_kq ? 0xfffffffe : 0xffffff00; + adev->mes.vmid_mask_mmhub = 0xFF00; + adev->mes.vmid_mask_gfxhub = adev->gfx.disable_kq ? 0xFFFE : 0xFF00; num_pipes = adev->gfx.me.num_pipe_per_me * adev->gfx.me.num_me; if (num_pipes > AMDGPU_MES_MAX_GFX_PIPES) From 24b9fdb9eca434344d4a388723a863be5aaea398 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Mon, 6 Oct 2025 11:16:20 -0500 Subject: [PATCH 2193/2653] drm/amd: Adjust whitespace for vangogh_ppt A few changes have more whitespace than needed. Clean them up. Reviewed-by: Lijo Lazar Tested-by: Robert Beckett Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index a4b4c01b9bd95..4c8e8e8379d06 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -2312,8 +2312,7 @@ static int vangogh_get_power_limit(struct smu_context *smu, uint32_t *max_power_limit, uint32_t *min_power_limit) { - struct smu_11_5_power_context *power_context = - smu->smu_power.power_context; + struct smu_11_5_power_context *power_context = smu->smu_power.power_context; uint32_t ppt_limit; int ret = 0; @@ -2349,12 +2348,11 @@ static int vangogh_get_power_limit(struct smu_context *smu, } static int vangogh_get_ppt_limit(struct smu_context *smu, - uint32_t *ppt_limit, - enum smu_ppt_limit_type type, - enum smu_ppt_limit_level level) + uint32_t *ppt_limit, + enum smu_ppt_limit_type type, + enum smu_ppt_limit_level level) { - struct smu_11_5_power_context *power_context = - smu->smu_power.power_context; + struct smu_11_5_power_context *power_context = smu->smu_power.power_context; if (!power_context) return -EOPNOTSUPP; From 28ec7d5df16136334c8c4c08af774ec2b53fd68a Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Wed, 1 Oct 2025 13:03:33 -0500 Subject: [PATCH 2194/2653] drm/amd: Remove some unncessary header includes Unnecessary headers can slow down the build, drop em. No intended functional changes. Reviewed-by: Lijo Lazar Tested-by: Robert Beckett Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index 554492dfa3c00..fb595a70bbd11 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -20,7 +20,6 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#include "pp_debug.h" #include #include #include @@ -28,12 +27,10 @@ #include #include #include "amd_shared.h" -#include "amd_powerplay.h" #include "power_state.h" #include "amdgpu.h" #include "hwmgr.h" #include "amdgpu_dpm_internal.h" -#include "amdgpu_display.h" static const struct amd_pm_funcs pp_dpm_funcs; From ef9aa65a9da21065e2f715957d4ddd167f4f2d56 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 25 Sep 2025 12:09:56 +0200 Subject: [PATCH 2195/2653] drm/amdgpu: reduce queue timeout to 2 seconds v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There has been multiple complains that 10 seconds are usually to long. The original requirement for longer timeout came from compute tests on AMDVLK, since that is no longer a topic reduce the timeout back to 2 seconds for all queues. While at it also remove any special handling for compute queues under SRIOV or pass through. v2: fix checkpatch warning. Signed-off-by: Christian König Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 85 ++++++++++------------ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 20 ++--- 2 files changed, 47 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index a221678e893e8..58b4e75a1a684 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4303,58 +4303,53 @@ static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) long timeout; int ret = 0; - /* - * By default timeout for jobs is 10 sec - */ - adev->compute_timeout = adev->gfx_timeout = msecs_to_jiffies(10000); - adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; + /* By default timeout for all queues is 2 sec */ + adev->gfx_timeout = adev->compute_timeout = adev->sdma_timeout = + adev->video_timeout = msecs_to_jiffies(2000); - if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { - while ((timeout_setting = strsep(&input, ",")) && - strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { - ret = kstrtol(timeout_setting, 0, &timeout); - if (ret) - return ret; + if (!strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) + return 0; - if (timeout == 0) { - index++; - continue; - } else if (timeout < 0) { - timeout = MAX_SCHEDULE_TIMEOUT; - dev_warn(adev->dev, "lockup timeout disabled"); - add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK); - } else { - timeout = msecs_to_jiffies(timeout); - } + while ((timeout_setting = strsep(&input, ",")) && + strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { + ret = kstrtol(timeout_setting, 0, &timeout); + if (ret) + return ret; - switch (index++) { - case 0: - adev->gfx_timeout = timeout; - break; - case 1: - adev->compute_timeout = timeout; - break; - case 2: - adev->sdma_timeout = timeout; - break; - case 3: - adev->video_timeout = timeout; - break; - default: - break; - } + if (timeout == 0) { + index++; + continue; + } else if (timeout < 0) { + timeout = MAX_SCHEDULE_TIMEOUT; + dev_warn(adev->dev, "lockup timeout disabled"); + add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK); + } else { + timeout = msecs_to_jiffies(timeout); } - /* - * There is only one value specified and - * it should apply to all non-compute jobs. - */ - if (index == 1) { - adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; - if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev)) - adev->compute_timeout = adev->gfx_timeout; + + switch (index++) { + case 0: + adev->gfx_timeout = timeout; + break; + case 1: + adev->compute_timeout = timeout; + break; + case 2: + adev->sdma_timeout = timeout; + break; + case 3: + adev->video_timeout = timeout; + break; + default: + break; } } + /* When only one value specified apply it to all queues. */ + if (index == 1) + adev->gfx_timeout = adev->compute_timeout = adev->sdma_timeout = + adev->video_timeout = timeout; + return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index e3ef935a64f77..a1a82bebf6607 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -355,22 +355,16 @@ module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint * DOC: lockup_timeout (string) * Set GPU scheduler timeout value in ms. * - * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or - * multiple values specified. 0 and negative values are invalidated. They will be adjusted - * to the default timeout. + * The format can be [single value] for setting all timeouts at once or + * [GFX,Compute,SDMA,Video] to set individual timeouts. + * Negative values mean infinity. * - * - With one value specified, the setting will apply to all non-compute jobs. - * - With multiple values specified, the first one will be for GFX. - * The second one is for Compute. The third and fourth ones are - * for SDMA and Video. - * - * By default(with no lockup_timeout settings), the timeout for all jobs is 10000. + * By default(with no lockup_timeout settings), the timeout for all queues is 2000. */ MODULE_PARM_DESC(lockup_timeout, - "GPU lockup timeout in ms (default: 10000 for all jobs. " - "0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " - "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); -module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); + "GPU lockup timeout in ms (default: 2000. 0: keep default value. negative: infinity timeout), format: [single value for all] or [GFX,Compute,SDMA,Video]."); +module_param_string(lockup_timeout, amdgpu_lockup_timeout, + sizeof(amdgpu_lockup_timeout), 0444); /** * DOC: dpm (int) From 02fdc6bd473459034137f04908355b4f6988c282 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Tue, 7 Oct 2025 10:10:52 +0200 Subject: [PATCH 2196/2653] drm/amdgpu: hide VRAM sysfs attributes on GPUs without VRAM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Otherwise accessing them can cause a crash. Signed-off-by: Christian König Tested-by: Mangesh Gadre Acked-by: Alex Deucher Reviewed-by: Arunpravin Paneer Selvam --- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 02cbf9aaa2c60..3487bc738ba46 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -239,6 +239,9 @@ static umode_t amdgpu_vram_attrs_is_visible(struct kobject *kobj, !adev->gmc.vram_vendor) return 0; + if (!ttm_resource_manager_used(&adev->mman.vram_mgr.manager)) + return 0; + return attr->mode; } From a3b51ddc5a4c19bff77741d18f087179ae045cff Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Mon, 29 Sep 2025 13:52:13 +0800 Subject: [PATCH 2197/2653] drm/amdgpu: add userq object va track helpers Add the userq object virtual address list_add() helpers for tracking the userq obj va address usage. Signed-off-by: Prike Liang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 44 ++++++++++++++++------ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 12 ++++-- drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 16 ++++---- 4 files changed, 52 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 6abb7d6e6532e..6eea59ba81cbc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -96,6 +96,7 @@ struct amdgpu_bo_va { * if non-zero, cannot unmap from GPU because user queues may still access it */ unsigned int queue_refcount; + atomic_t userq_va_mapped; }; struct amdgpu_bo { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 72ae7c346738f..caf6588ec3c86 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -44,10 +44,29 @@ u32 amdgpu_userq_get_supported_ip_mask(struct amdgpu_device *adev) return userq_ip_mask; } -int amdgpu_userq_input_va_validate(struct amdgpu_vm *vm, u64 addr, - u64 expected_size) +static int amdgpu_userq_buffer_va_list_add(struct amdgpu_usermode_queue *queue, + struct amdgpu_bo_va_mapping *va_map, u64 addr) +{ + struct amdgpu_userq_va_cursor *va_cursor; + struct userq_va_list; + + va_cursor = kzalloc(sizeof(*va_cursor), GFP_KERNEL); + if (!va_cursor) + return -ENOMEM; + + INIT_LIST_HEAD(&va_cursor->list); + va_cursor->gpu_addr = addr; + atomic_set(&va_map->bo_va->userq_va_mapped, 1); + list_add(&va_cursor->list, &queue->userq_va_list); + + return 0; +} + +int amdgpu_userq_input_va_validate(struct amdgpu_usermode_queue *queue, + u64 addr, u64 expected_size) { struct amdgpu_bo_va_mapping *va_map; + struct amdgpu_vm *vm = queue->vm; u64 user_addr; u64 size; int r = 0; @@ -67,6 +86,7 @@ int amdgpu_userq_input_va_validate(struct amdgpu_vm *vm, u64 addr, /* Only validate the userq whether resident in the VM mapping range */ if (user_addr >= va_map->start && va_map->last - user_addr + 1 >= size) { + amdgpu_userq_buffer_va_list_add(queue, va_map, user_addr); amdgpu_bo_unreserve(vm->root.bo); return 0; } @@ -185,6 +205,7 @@ amdgpu_userq_cleanup(struct amdgpu_userq_mgr *uq_mgr, uq_funcs->mqd_destroy(uq_mgr, queue); amdgpu_userq_fence_driver_free(queue); idr_remove(&uq_mgr->userq_idr, queue_id); + list_del(&queue->userq_va_list); kfree(queue); } @@ -505,14 +526,7 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) goto unlock; } - /* Validate the userq virtual address.*/ - if (amdgpu_userq_input_va_validate(&fpriv->vm, args->in.queue_va, args->in.queue_size) || - amdgpu_userq_input_va_validate(&fpriv->vm, args->in.rptr_va, AMDGPU_GPU_PAGE_SIZE) || - amdgpu_userq_input_va_validate(&fpriv->vm, args->in.wptr_va, AMDGPU_GPU_PAGE_SIZE)) { - r = -EINVAL; - kfree(queue); - goto unlock; - } + INIT_LIST_HEAD(&queue->userq_va_list); queue->doorbell_handle = args->in.doorbell_handle; queue->queue_type = args->in.ip_type; queue->vm = &fpriv->vm; @@ -523,6 +537,15 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) db_info.db_obj = &queue->db_obj; db_info.doorbell_offset = args->in.doorbell_offset; + /* Validate the userq virtual address.*/ + if (amdgpu_userq_input_va_validate(queue, args->in.queue_va, args->in.queue_size) || + amdgpu_userq_input_va_validate(queue, args->in.rptr_va, AMDGPU_GPU_PAGE_SIZE) || + amdgpu_userq_input_va_validate(queue, args->in.wptr_va, AMDGPU_GPU_PAGE_SIZE)) { + r = -EINVAL; + kfree(queue); + goto unlock; + } + /* Convert relative doorbell offset into absolute doorbell index */ index = amdgpu_userq_get_doorbell_index(uq_mgr, &db_info, filp); if (index == (uint64_t)-EINVAL) { @@ -553,7 +576,6 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) goto unlock; } - qid = idr_alloc(&uq_mgr->userq_idr, queue, 1, AMDGPU_MAX_USERQ_COUNT, GFP_KERNEL); if (qid < 0) { drm_file_err(uq_mgr->file, "Failed to allocate a queue id\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index f2bee4ed5d10a..d559d4b5ea534 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -48,6 +48,11 @@ struct amdgpu_userq_obj { struct amdgpu_bo *obj; }; +struct amdgpu_userq_va_cursor { + u64 gpu_addr; + struct list_head list; +}; + struct amdgpu_usermode_queue { int queue_type; enum amdgpu_userq_state state; @@ -72,6 +77,8 @@ struct amdgpu_usermode_queue { u32 xcp_id; int priority; struct dentry *debugfs_queue; + + struct list_head userq_va_list; }; struct amdgpu_userq_funcs { @@ -142,7 +149,6 @@ int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev, u32 idx); int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev, u32 idx); - -int amdgpu_userq_input_va_validate(struct amdgpu_vm *vm, u64 addr, - u64 expected_size); +int amdgpu_userq_input_va_validate(struct amdgpu_usermode_queue *queue, + u64 addr, u64 expected_size); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index 2db9b2c63693d..829129ad7bd16 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -298,8 +298,9 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, goto free_mqd; } - if (amdgpu_userq_input_va_validate(queue->vm, compute_mqd->eop_va, - max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE))) + r = amdgpu_userq_input_va_validate(queue, compute_mqd->eop_va, + max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE)); + if (r) goto free_mqd; userq_props->eop_gpu_addr = compute_mqd->eop_va; @@ -330,8 +331,9 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, userq_props->tmz_queue = mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; - if (amdgpu_userq_input_va_validate(queue->vm, mqd_gfx_v11->shadow_va, - shadow_info.shadow_size)) + r = amdgpu_userq_input_va_validate(queue, mqd_gfx_v11->shadow_va, + shadow_info.shadow_size); + if (r) goto free_mqd; kfree(mqd_gfx_v11); @@ -350,9 +352,9 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, r = -ENOMEM; goto free_mqd; } - - if (amdgpu_userq_input_va_validate(queue->vm, mqd_sdma_v11->csa_va, - shadow_info.csa_size)) + r = amdgpu_userq_input_va_validate(queue, mqd_sdma_v11->csa_va, + shadow_info.csa_size); + if (r) goto free_mqd; userq_props->csa_addr = mqd_sdma_v11->csa_va; From 942cf036676e5fdd4691dbc68f81239870282fd3 Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Thu, 9 Oct 2025 16:44:31 +0800 Subject: [PATCH 2198/2653] drm/amdgpu: track the userq bo va for its obj management Track the userq obj for its life time, and reference and dereference the buffer flag at its creating and destroying period. Suggested-by: Alex Deucher Signed-off-by: Prike Liang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index caf6588ec3c86..4d382b8d0f57b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -97,6 +97,40 @@ int amdgpu_userq_input_va_validate(struct amdgpu_usermode_queue *queue, return r; } +static void amdgpu_userq_buffer_va_list_del(struct amdgpu_bo_va_mapping *mapping, + struct amdgpu_userq_va_cursor *va_cursor) +{ + atomic_set(&mapping->bo_va->userq_va_mapped, 0); + list_del(&va_cursor->list); + kfree(va_cursor); +} + +static int amdgpu_userq_buffer_vas_list_cleanup(struct amdgpu_device *adev, + struct amdgpu_usermode_queue *queue) +{ + struct amdgpu_userq_va_cursor *va_cursor, *tmp; + struct amdgpu_bo_va_mapping *mapping; + int r; + + r = amdgpu_bo_reserve(queue->vm->root.bo, false); + if (r) + return r; + + list_for_each_entry_safe(va_cursor, tmp, &queue->userq_va_list, list) { + mapping = amdgpu_vm_bo_lookup_mapping(queue->vm, va_cursor->gpu_addr); + if (!mapping) { + r = -EINVAL; + goto err; + } + amdgpu_userq_buffer_va_list_del(mapping, va_cursor); + dev_dbg(adev->dev, "delete the userq:%p va:%llx\n", + queue, va_cursor->gpu_addr); + } +err: + amdgpu_bo_unreserve(queue->vm->root.bo); + return r; +} + static int amdgpu_userq_preempt_helper(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_queue *queue) @@ -202,6 +236,8 @@ amdgpu_userq_cleanup(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_device *adev = uq_mgr->adev; const struct amdgpu_userq_funcs *uq_funcs = adev->userq_funcs[queue->queue_type]; + /* Drop the userq reference. */ + amdgpu_userq_buffer_vas_list_cleanup(adev, queue); uq_funcs->mqd_destroy(uq_mgr, queue); amdgpu_userq_fence_driver_free(queue); idr_remove(&uq_mgr->userq_idr, queue_id); From 4705b6b532f2526cde7f1af80eacda8a8e4314ae Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Tue, 22 Jul 2025 13:43:51 +0800 Subject: [PATCH 2199/2653] drm/amdgpu: keeping waiting userq fence infinitely Keeping waiting the userq fence infinitely until hang detection, and then suspend the hang queue and set the fence error. Signed-off-by: Prike Liang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 4d382b8d0f57b..f8537a064a6ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -213,19 +213,24 @@ amdgpu_userq_map_helper(struct amdgpu_userq_mgr *uq_mgr, return r; } -static void +static int amdgpu_userq_wait_for_last_fence(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_queue *queue) { struct dma_fence *f = queue->last_fence; - int ret; + int ret = 0; if (f && !dma_fence_is_signaled(f)) { - ret = dma_fence_wait_timeout(f, true, msecs_to_jiffies(100)); - if (ret <= 0) + ret = dma_fence_wait_timeout(f, true, MAX_SCHEDULE_TIMEOUT); + if (ret <= 0) { drm_file_err(uq_mgr->file, "Timed out waiting for fence=%llu:%llu\n", f->context, f->seqno); + queue->state = AMDGPU_USERQ_STATE_HUNG; + return -ETIME; + } } + + return ret; } static void From b7ff54ae3854be9cd24b0d182faedccdad35176a Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Thu, 9 Oct 2025 16:45:27 +0800 Subject: [PATCH 2200/2653] drm/amdgpu: validate the queue va for resuming the queue It requires validating the userq VA whether is mapped before trying to resume the queue. Signed-off-by: Prike Liang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 44 +++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index f8537a064a6ac..f0d0ea1bc997d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -97,6 +97,42 @@ int amdgpu_userq_input_va_validate(struct amdgpu_usermode_queue *queue, return r; } +static bool amdgpu_userq_buffer_va_mapped(struct amdgpu_vm *vm, u64 addr) +{ + struct amdgpu_bo_va_mapping *mapping; + bool r; + + if (amdgpu_bo_reserve(vm->root.bo, false)) + return false; + + mapping = amdgpu_vm_bo_lookup_mapping(vm, addr); + if (!IS_ERR_OR_NULL(mapping) && atomic_read(&mapping->bo_va->userq_va_mapped)) + r = true; + else + r = false; + amdgpu_bo_unreserve(vm->root.bo); + + return r; +} + +static bool amdgpu_userq_buffer_vas_mapped(struct amdgpu_usermode_queue *queue) +{ + struct amdgpu_userq_va_cursor *va_cursor, *tmp; + int r = 0; + + list_for_each_entry_safe(va_cursor, tmp, &queue->userq_va_list, list) { + r += amdgpu_userq_buffer_va_mapped(queue->vm, va_cursor->gpu_addr); + dev_dbg(queue->userq_mgr->adev->dev, + "validate the userq mapping:%p va:%llx r:%d\n", + queue, va_cursor->gpu_addr, r); + } + + if (r != 0) + return true; + + return false; +} + static void amdgpu_userq_buffer_va_list_del(struct amdgpu_bo_va_mapping *mapping, struct amdgpu_userq_va_cursor *va_cursor) { @@ -766,6 +802,14 @@ amdgpu_userq_restore_all(struct amdgpu_userq_mgr *uq_mgr) /* Resume all the queues for this process */ idr_for_each_entry(&uq_mgr->userq_idr, queue, queue_id) { + + if (!amdgpu_userq_buffer_vas_mapped(queue)) { + drm_file_err(uq_mgr->file, + "trying restore queue without va mapping\n"); + queue->state = AMDGPU_USERQ_STATE_INVALID_VA; + continue; + } + r = amdgpu_userq_restore_helper(uq_mgr, queue); if (r) ret = r; From d11aa2df3455468c7071120f6377648e7f214b34 Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Fri, 19 Sep 2025 15:14:41 +0800 Subject: [PATCH 2201/2653] drm/amdgpu: validate userq va for GEM unmap MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When a user unmaps a userq VA, the driver must ensure the queue has no in-flight jobs. If there is pending work, the kernel should wait for the attached eviction (bookkeeping) fence to signal before deleting the mapping. Suggested-by: Christian König Signed-off-by: Prike Liang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 31 +++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 3 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 12 +++++++++ 3 files changed, 46 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index f0d0ea1bc997d..f721bf64edd80 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -1200,3 +1200,34 @@ int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev, mutex_unlock(&adev->userq_mutex); return ret; } + +int amdgpu_userq_gem_va_unmap_validate(struct amdgpu_device *adev, + struct amdgpu_bo_va_mapping *mapping, + uint64_t saddr) +{ + u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev); + struct amdgpu_bo_va *bo_va = mapping->bo_va; + struct dma_resv *resv = bo_va->base.bo->tbo.base.resv; + int ret = 0; + + if (!ip_mask) + return 0; + + dev_warn_once(adev->dev, "now unmapping a vital queue va:%llx\n", saddr); + /** + * The userq VA mapping reservation should include the eviction fence, + * if the eviction fence can't signal successfully during unmapping, + * then driver will warn to flag this improper unmap of the userq VA. + * Note: The eviction fence may be attached to different BOs, and this + * unmap is only for one kind of userq VAs, so at this point suppose + * the eviction fence is always unsignaled. + */ + if (!dma_resv_test_signaled(resv, DMA_RESV_USAGE_BOOKKEEP)) { + ret = dma_resv_wait_timeout(resv, DMA_RESV_USAGE_BOOKKEEP, true, + MAX_SCHEDULE_TIMEOUT); + if (ret <= 0) + return -EBUSY; + } + + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index d559d4b5ea534..7c4bb06c2d1b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -151,4 +151,7 @@ int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev, u32 idx); int amdgpu_userq_input_va_validate(struct amdgpu_usermode_queue *queue, u64 addr, u64 expected_size); +int amdgpu_userq_gem_va_unmap_validate(struct amdgpu_device *adev, + struct amdgpu_bo_va_mapping *mapping, + uint64_t saddr); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 4a3e24dbe95fe..6eb1c1acb14e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1977,6 +1977,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, struct amdgpu_bo_va_mapping *mapping; struct amdgpu_vm *vm = bo_va->base.vm; bool valid = true; + int r; saddr /= AMDGPU_GPU_PAGE_SIZE; @@ -1997,6 +1998,17 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, return -ENOENT; } + /* It's unlikely to happen that the mapping userq hasn't been idled + * during user requests GEM unmap IOCTL except for forcing the unmap + * from user space. + */ + if (unlikely(atomic_read(&bo_va->userq_va_mapped) > 0)) { + r = amdgpu_userq_gem_va_unmap_validate(adev, mapping, saddr); + if (unlikely(r == -EBUSY)) + dev_warn_once(adev->dev, + "Attempt to unmap an active userq buffer\n"); + } + list_del(&mapping->list); amdgpu_vm_it_remove(mapping, &vm->va); mapping->bo_va = NULL; From ff9976bb2912ea4554054c68c0b1bc2d49567dc9 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 2 Oct 2025 12:42:39 -0500 Subject: [PATCH 2202/2653] drm/amd: Unify shutdown() callback behavior [Why] The shutdown() callback uses amdgpu_ip_suspend() which doesn't notify drm clients during shutdown. This could lead to hangs. [How] Change amdgpu_pci_shutdown() to call the same sequence as suspend/resume. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index a1a82bebf6607..320b836b90e24 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2613,7 +2613,8 @@ amdgpu_pci_shutdown(struct pci_dev *pdev) */ if (!amdgpu_passthrough(adev)) adev->mp1_state = PP_MP1_STATE_UNLOAD; - amdgpu_device_ip_suspend(adev); + amdgpu_device_prepare(dev); + amdgpu_device_suspend(dev, true); adev->mp1_state = PP_MP1_STATE_NONE; } From 94c8e34ec7e312acf019859600a4f475a924ccae Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 2 Oct 2025 12:42:40 -0500 Subject: [PATCH 2203/2653] drm/amd: Stop exporting amdgpu_device_ip_suspend() outside amdgpu_device amdgpu_device_ip_suspend() doesn't have a caller outside of amdgpu_device.c. Make it static. No intended functional changes. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 7ef0bc4c1cc91..395424529c0b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1672,7 +1672,6 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, struct drm_file *file_priv); void amdgpu_driver_release_kms(struct drm_device *dev); -int amdgpu_device_ip_suspend(struct amdgpu_device *adev); int amdgpu_device_prepare(struct drm_device *dev); void amdgpu_device_complete(struct drm_device *dev); int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 58b4e75a1a684..e5bfa50328f9d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3913,7 +3913,7 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) * in each IP into a state suitable for suspend. * Returns 0 on success, negative error code on failure. */ -int amdgpu_device_ip_suspend(struct amdgpu_device *adev) +static int amdgpu_device_ip_suspend(struct amdgpu_device *adev) { int r; From 3dc6a24e5fc751cc13aa96aa60720d3f97a27477 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 2 Oct 2025 12:42:41 -0500 Subject: [PATCH 2204/2653] drm/amd: Remove comment about handling errors in amdgpu_device_ip_suspend_phase1() Error handling was introduced in commit e095026f0066e ("drm/amdgpu: validate suspend before function call") so the comment about TODO is no longer needed. Fixes: e095026f0066e ("drm/amdgpu: validate suspend before function call") Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index e5bfa50328f9d..602e19cf627e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3798,7 +3798,6 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE) continue; - /* XXX handle errors */ r = amdgpu_ip_block_suspend(&adev->ip_blocks[i]); if (r) return r; From 94a233c4ff4a1714dde514ae67ca4650f792bca4 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 2 Oct 2025 12:42:42 -0500 Subject: [PATCH 2205/2653] drm/amd: Don't always set IP block HW status to false amdgpu_device_ip_suspend_phase2() calls amdgpu_ip_block_suspend() which already sets HW block status to false when succeeding with IP suspend. Remove the explicit call in amdgpu_device_ip_suspend_phase2() so that the status is accurate. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 602e19cf627e3..ebb4161f22417 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3882,7 +3882,6 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) /* XXX handle errors */ r = amdgpu_ip_block_suspend(&adev->ip_blocks[i]); - adev->ip_blocks[i].status.hw = false; /* handle putting the SMC in the appropriate state */ if (!amdgpu_sriov_vf(adev)) { From 9ef66910b50155812148f89d16350c0a6e605656 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 2 Oct 2025 12:42:43 -0500 Subject: [PATCH 2206/2653] drm/amd: Pass IP suspend errors up to callers If IP suspend fails the callers should be notified so that they can potentially react. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index ebb4161f22417..0a80f977201ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3880,8 +3880,9 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) continue; - /* XXX handle errors */ r = amdgpu_ip_block_suspend(&adev->ip_blocks[i]); + if (r) + return r; /* handle putting the SMC in the appropriate state */ if (!amdgpu_sriov_vf(adev)) { @@ -5262,7 +5263,9 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients) amdgpu_ras_suspend(adev); - amdgpu_device_ip_suspend_phase1(adev); + r = amdgpu_device_ip_suspend_phase1(adev); + if (r) + return r; amdgpu_amdkfd_suspend(adev, !amdgpu_sriov_vf(adev) && !adev->in_runpm); amdgpu_userq_suspend(adev); @@ -5275,7 +5278,9 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients) amdgpu_fence_driver_hw_fini(adev); - amdgpu_device_ip_suspend_phase2(adev); + r = amdgpu_device_ip_suspend_phase2(adev); + if (r) + return r; if (amdgpu_sriov_vf(adev)) amdgpu_virt_release_full_gpu(adev, false); From 69fc8ea91653bdf37ae998968942fc1a58215a1e Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 2 Oct 2025 12:42:44 -0500 Subject: [PATCH 2207/2653] drm/amd: Fix error handling with multiple userq IDRs If multiple userq IDR are in use and there is an error handling one at suspend or resume it will be silently discarded. Switch the suspend/resume() code to use guards and return immediately. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 25 ++++++++++------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index f721bf64edd80..7a5d4803b3276 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -1081,27 +1081,25 @@ int amdgpu_userq_suspend(struct amdgpu_device *adev) struct amdgpu_usermode_queue *queue; struct amdgpu_userq_mgr *uqm, *tmp; int queue_id; - int ret = 0, r; + int r; if (!ip_mask) return 0; - mutex_lock(&adev->userq_mutex); + guard(mutex)(&adev->userq_mutex); list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { cancel_delayed_work_sync(&uqm->resume_work); - mutex_lock(&uqm->userq_mutex); + guard(mutex)(&uqm->userq_mutex); idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { if (adev->in_s0ix) r = amdgpu_userq_preempt_helper(uqm, queue); else r = amdgpu_userq_unmap_helper(uqm, queue); if (r) - ret = r; + return r; } - mutex_unlock(&uqm->userq_mutex); } - mutex_unlock(&adev->userq_mutex); - return ret; + return 0; } int amdgpu_userq_resume(struct amdgpu_device *adev) @@ -1110,26 +1108,25 @@ int amdgpu_userq_resume(struct amdgpu_device *adev) struct amdgpu_usermode_queue *queue; struct amdgpu_userq_mgr *uqm, *tmp; int queue_id; - int ret = 0, r; + int r; if (!ip_mask) return 0; - mutex_lock(&adev->userq_mutex); + guard(mutex)(&adev->userq_mutex); list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { - mutex_lock(&uqm->userq_mutex); + guard(mutex)(&uqm->userq_mutex); idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { if (adev->in_s0ix) r = amdgpu_userq_restore_helper(uqm, queue); else r = amdgpu_userq_map_helper(uqm, queue); if (r) - ret = r; + return r; } - mutex_unlock(&uqm->userq_mutex); } - mutex_unlock(&adev->userq_mutex); - return ret; + + return 0; } int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev, From 432d278a7457117405ba5cd092057bd24e318e8a Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 2 Oct 2025 12:42:45 -0500 Subject: [PATCH 2208/2653] drm/amd: Pass userq suspend failures up to caller If a userq failed to suspend the rest of the suspend sequence may have problems. Pass the error code up to the caller for a decision on what to do. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 0a80f977201ae..7cf99cbec94b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5268,7 +5268,9 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients) return r; amdgpu_amdkfd_suspend(adev, !amdgpu_sriov_vf(adev) && !adev->in_runpm); - amdgpu_userq_suspend(adev); + r = amdgpu_userq_suspend(adev); + if (r) + return r; r = amdgpu_device_evict_resources(adev); if (r) From 9f2adaa6514f2301f6463d66fc0bea4035bc28aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:26:12 +0200 Subject: [PATCH 2209/2653] drm/amd/pm: Disable MCLK switching on SI at high pixel clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On various SI GPUs, a flickering can be observed near the bottom edge of the screen when using a single 4K 60Hz monitor over DP. Disabling MCLK switching works around this problem. Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index cf9932e68055f..3a9522c17fee3 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -3500,6 +3500,11 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev, * for these GPUs to calculate bandwidth requirements. */ if (high_pixelclock_count) { + /* Work around flickering lines at the bottom edge + * of the screen when using a single 4K 60Hz monitor. + */ + disable_mclk_switching = true; + /* On Oland, we observe some flickering when two 4K 60Hz * displays are connected, possibly because voltage is too low. * Raise the voltage by requiring a higher SCLK. From 39bd0f5f412078c816098656aae1398ac761a5d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:26:13 +0200 Subject: [PATCH 2210/2653] drm/amd: Disable ASPM on SI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enabling ASPM causes randoms hangs on Tahiti and Oland on Zen4. It's unclear if this is a platform-specific or GPU-specific issue. Disable ASPM on SI for the time being. Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 7cf99cbec94b5..4cb5e433ce648 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1891,6 +1891,13 @@ static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device static bool amdgpu_device_aspm_support_quirk(struct amdgpu_device *adev) { + /* Enabling ASPM causes randoms hangs on Tahiti and Oland on Zen4. + * It's unclear if this is a platform-specific or GPU-specific issue. + * Disable ASPM on SI for the time being. + */ + if (adev->family == AMDGPU_FAMILY_SI) + return true; + #if IS_ENABLED(CONFIG_X86) struct cpuinfo_x86 *c = &cpu_data(0); From e27f6c25b470e2f40fc21a1cd7435e6448ce0c3e Mon Sep 17 00:00:00 2001 From: Matthew Schwartz Date: Thu, 9 Oct 2025 14:19:00 +0200 Subject: [PATCH 2211/2653] Revert "drm/amd/display: Only restore backlight after amdgpu_dm_init or dm_resume" This fix regressed the original issue that commit 7875afafba84 ("drm/amd/display: Fix brightness level not retained over reboot") solved, so revert it until a different approach to solve the regression that it caused with AMD_PRIVATE_COLOR is found. Fixes: a490c8d77d50 ("drm/amd/display: Only restore backlight after amdgpu_dm_init or dm_resume") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4620 Cc: stable@vger.kernel.org Signed-off-by: Matthew Schwartz Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ++++-------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 7 ------- 2 files changed, 4 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 098d018073c66..e493aa4470f8d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2121,8 +2121,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) dc_hardware_init(adev->dm.dc); - adev->dm.restore_backlight = true; - adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev); if (!adev->dm.hpd_rx_offload_wq) { drm_err(adev_to_drm(adev), "failed to create hpd rx offload workqueue.\n"); @@ -3483,7 +3481,6 @@ static int dm_resume(struct amdgpu_ip_block *ip_block) dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); dc_resume(dm->dc); - adev->dm.restore_backlight = true; amdgpu_dm_irq_resume_early(adev); @@ -10263,6 +10260,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, bool mode_set_reset_required = false; u32 i; struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count}; + bool set_backlight_level = false; /* Disable writeback */ for_each_old_connector_in_state(state, connector, old_con_state, i) { @@ -10382,6 +10380,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, acrtc->hw_mode = new_crtc_state->mode; crtc->hwmode = new_crtc_state->mode; mode_set_reset_required = true; + set_backlight_level = true; } else if (modereset_required(new_crtc_state)) { drm_dbg_atomic(dev, "Atomic commit: RESET. crtc id %d:[%p]\n", @@ -10438,16 +10437,13 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, * to fix a flicker issue. * It will cause the dm->actual_brightness is not the current panel brightness * level. (the dm->brightness is the correct panel level) - * So we set the backlight level with dm->brightness value after initial - * set mode. Use restore_backlight flag to avoid setting backlight level - * for every subsequent mode set. + * So we set the backlight level with dm->brightness value after set mode */ - if (dm->restore_backlight) { + if (set_backlight_level) { for (i = 0; i < dm->num_of_edps; i++) { if (dm->backlight_dev[i]) amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); } - dm->restore_backlight = false; } } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 96b8ce00ac4cb..691450143488b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -632,13 +632,6 @@ struct amdgpu_display_manager { */ u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; - /** - * @restore_backlight: - * - * Flag to indicate whether to restore backlight after modeset. - */ - bool restore_backlight; - /** * @aux_hpd_discon_quirk: * From 615e2498220ce126ec4a4fce3c6371be2fe0ff33 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 26 Sep 2025 17:31:32 -0400 Subject: [PATCH 2212/2653] drm/amdgpu: fix handling of harvesting for ip_discovery firmware Chips which use the IP discovery firmware loaded by the driver reported incorrect harvesting information in the ip discovery table in sysfs because the driver only uses the ip discovery firmware for populating sysfs and not for direct parsing for the driver itself as such, the fields that are used to print the harvesting info in sysfs report incorrect data for some IPs. Populate the relevant fields for this case as well. Fixes: 514678da56da ("drm/amdgpu/discovery: fix fw based ip discovery") Acked-by: Tom St Denis Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index bc5327b98e162..5c9908b6a10ba 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1049,7 +1049,9 @@ static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, /* Until a uniform way is figured, get mask based on hwid */ switch (hw_id) { case VCN_HWID: - harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; + /* VCN vs UVD+VCE */ + if (!amdgpu_ip_version(adev, VCE_HWIP, 0)) + harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; break; case DMU_HWID: if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) @@ -2581,7 +2583,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) amdgpu_discovery_init(adev); vega10_reg_base_init(adev); adev->sdma.num_instances = 2; + adev->sdma.sdma_mask = 3; adev->gmc.num_umc = 4; + adev->gfx.xcc_mask = 1; adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); @@ -2608,7 +2612,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) amdgpu_discovery_init(adev); vega10_reg_base_init(adev); adev->sdma.num_instances = 2; + adev->sdma.sdma_mask = 3; adev->gmc.num_umc = 4; + adev->gfx.xcc_mask = 1; adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); @@ -2635,8 +2641,10 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) amdgpu_discovery_init(adev); vega10_reg_base_init(adev); adev->sdma.num_instances = 1; + adev->sdma.sdma_mask = 1; adev->vcn.num_vcn_inst = 1; adev->gmc.num_umc = 2; + adev->gfx.xcc_mask = 1; if (adev->apu_flags & AMD_APU_IS_RAVEN2) { adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); @@ -2681,7 +2689,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) amdgpu_discovery_init(adev); vega20_reg_base_init(adev); adev->sdma.num_instances = 2; + adev->sdma.sdma_mask = 3; adev->gmc.num_umc = 8; + adev->gfx.xcc_mask = 1; adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); @@ -2709,8 +2719,10 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) amdgpu_discovery_init(adev); arct_reg_base_init(adev); adev->sdma.num_instances = 8; + adev->sdma.sdma_mask = 0xff; adev->vcn.num_vcn_inst = 2; adev->gmc.num_umc = 8; + adev->gfx.xcc_mask = 1; adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); @@ -2742,8 +2754,10 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) amdgpu_discovery_init(adev); aldebaran_reg_base_init(adev); adev->sdma.num_instances = 5; + adev->sdma.sdma_mask = 0x1f; adev->vcn.num_vcn_inst = 2; adev->gmc.num_umc = 4; + adev->gfx.xcc_mask = 1; adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); @@ -2778,6 +2792,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) } else { cyan_skillfish_reg_base_init(adev); adev->sdma.num_instances = 2; + adev->sdma.sdma_mask = 3; + adev->gfx.xcc_mask = 1; adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3); adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3); adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1); From 17ba4b345a4ad8c1de73ad718bf9ae6e0536791b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 8 Oct 2025 15:07:53 -0400 Subject: [PATCH 2213/2653] drm/amdgpu/userq: drop VCN and VPE doorbell handling VCN and VPE userqs are not yet supported and this code is not correct. Userspace should provide the correct doorbell offset with in their doorbell page for the IP. Adjusting it here will not work as expected as userspace and the queue itself will have different offsets. We need to add a INFO IOCTL query to get the offset and range for each IP within the doorbell page to handle this properly. Cc: Saleemkhan Jamadar Reviewed-by: Saleemkhan Jamadar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 7a5d4803b3276..b270ec2d92130 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -417,17 +417,6 @@ amdgpu_userq_get_doorbell_index(struct amdgpu_userq_mgr *uq_mgr, case AMDGPU_HW_IP_DMA: db_size = sizeof(u64); break; - - case AMDGPU_HW_IP_VCN_ENC: - db_size = sizeof(u32); - db_info->doorbell_offset += AMDGPU_NAVI10_DOORBELL64_VCN0_1 << 1; - break; - - case AMDGPU_HW_IP_VPE: - db_size = sizeof(u32); - db_info->doorbell_offset += AMDGPU_NAVI10_DOORBELL64_VPE << 1; - break; - default: drm_file_err(uq_mgr->file, "[Usermode queues] IP %d not support\n", db_info->queue_type); From 762ede13e54d89c2be5c4c9d561b099ca9f04e0f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 15 Sep 2025 12:37:32 -0400 Subject: [PATCH 2214/2653] drm/amdgpu: handle wrap around in reemit handling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Compare the sequence numbers directly. Fixes: 77cc0da39c7c ("drm/amdgpu: track ring state associated with a fence") Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index bb17c1a0a4438..5cead05dd279d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -789,14 +789,19 @@ void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring, struct dma_fence *unprocessed; struct dma_fence __rcu **ptr; struct amdgpu_fence *fence; - u64 wptr, i, seqno; + u64 wptr; + u32 seq, last_seq; - seqno = amdgpu_fence_read(ring); + last_seq = amdgpu_fence_read(ring) & ring->fence_drv.num_fences_mask; + seq = ring->fence_drv.sync_seq & ring->fence_drv.num_fences_mask; wptr = ring->fence_drv.signalled_wptr; ring->ring_backup_entries_to_copy = 0; - for (i = seqno + 1; i <= ring->fence_drv.sync_seq; ++i) { - ptr = &ring->fence_drv.fences[i & ring->fence_drv.num_fences_mask]; + do { + last_seq++; + last_seq &= ring->fence_drv.num_fences_mask; + + ptr = &ring->fence_drv.fences[last_seq]; rcu_read_lock(); unprocessed = rcu_dereference(*ptr); @@ -812,7 +817,7 @@ void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring, wptr = fence->wptr; } rcu_read_unlock(); - } + } while (last_seq != seq); } /* From 8922d361f39e2b6b5080bcc18a4d7a99605a0e1d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 3 Sep 2025 13:48:23 -0400 Subject: [PATCH 2215/2653] drm/amdgpu: set an error on all fences from a bad context MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When we backup ring contents to reemit after a queue reset, we don't backup ring contents from the bad context. When we signal the fences, we should set an error on those fences as well. v2: misc cleanups v3: add locking for fence error, fix comment (Christian) v4: fix wrap around, locking (Christian) Fixes: 77cc0da39c7c ("drm/amdgpu: track ring state associated with a fence") Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 39 ++++++++++++++++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +- 3 files changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 5cead05dd279d..9dc0001f97da8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -757,11 +757,42 @@ void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) * @fence: fence of the ring to signal * */ -void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *fence) +void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af) { - dma_fence_set_error(&fence->base, -ETIME); - amdgpu_fence_write(fence->ring, fence->seq); - amdgpu_fence_process(fence->ring); + struct dma_fence *unprocessed; + struct dma_fence __rcu **ptr; + struct amdgpu_fence *fence; + struct amdgpu_ring *ring = af->ring; + unsigned long flags; + u32 seq, last_seq; + + last_seq = amdgpu_fence_read(ring) & ring->fence_drv.num_fences_mask; + seq = ring->fence_drv.sync_seq & ring->fence_drv.num_fences_mask; + + /* mark all fences from the guilty context with an error */ + spin_lock_irqsave(&ring->fence_drv.lock, flags); + do { + last_seq++; + last_seq &= ring->fence_drv.num_fences_mask; + + ptr = &ring->fence_drv.fences[last_seq]; + rcu_read_lock(); + unprocessed = rcu_dereference(*ptr); + + if (unprocessed && !dma_fence_is_signaled_locked(unprocessed)) { + fence = container_of(unprocessed, struct amdgpu_fence, base); + + if (fence == af) + dma_fence_set_error(&fence->base, -ETIME); + else if (fence->context == af->context) + dma_fence_set_error(&fence->base, -ECANCELED); + } + rcu_read_unlock(); + } while (last_seq != seq); + spin_unlock_irqrestore(&ring->fence_drv.lock, flags); + /* signal the guilty fence */ + amdgpu_fence_write(ring, af->seq); + amdgpu_fence_process(ring); } void amdgpu_fence_save_wptr(struct dma_fence *fence) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 0137f45c6cd43..59d8632b7bc13 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -809,7 +809,7 @@ int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring, if (r) return r; - /* signal the fence of the bad job */ + /* signal the guilty fence and set an error on all fences from the context */ if (guilty_fence) amdgpu_fence_driver_guilty_force_completion(guilty_fence); /* Re-emit the non-guilty commands */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index b6b6491797761..4b46e3c26ff39 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -155,7 +155,7 @@ extern const struct drm_sched_backend_ops amdgpu_sched_ops; void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring); void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error); void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); -void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *fence); +void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af); void amdgpu_fence_save_wptr(struct dma_fence *fence); int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); From 966d9a86db3d5a18f199f2ab4153cdbf2665009d Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 9 Oct 2025 15:59:04 -0500 Subject: [PATCH 2216/2653] drm/amd: Stop overloading power limit with limit type When passed around internally the upper 8 bits of power limit include the limit type. This is non-obvious without digging into the nuances of each function. Instead pass the limit type as an argument to all applicable layers. Reviewed-by: Lijo Lazar Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/include/kgd_pp_interface.h | 2 +- drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 3 ++- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 3 +-- drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 2 +- drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 10 ++++------ drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 1 - 7 files changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index e23a10157f506..cb436d470c210 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -463,7 +463,7 @@ struct amd_pm_funcs { bool gate, int inst); int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); - int (*set_power_limit)(void *handle, uint32_t n); + int (*set_power_limit)(void *handle, uint32_t limit_type, uint32_t n); int (*get_power_limit)(void *handle, uint32_t *limit, enum pp_power_limit_level pp_limit_level, enum pp_power_type power_type); diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index f3a5777c67c3c..758f5ea4b68f0 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -1616,6 +1616,7 @@ int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, } int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, + uint32_t limit_type, uint32_t limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; @@ -1626,7 +1627,7 @@ int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, mutex_lock(&adev->pm.mutex); ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, - limit); + limit_type, limit); mutex_unlock(&adev->pm.mutex); return ret; diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 0b621a8265cfb..6b1ce52f4acf5 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -3390,13 +3390,12 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, return err; value = value / 1000000; /* convert to Watt */ - value |= limit_type << 24; err = amdgpu_pm_get_access(adev); if (err < 0) return err; - err = amdgpu_dpm_set_power_limit(adev, value); + err = amdgpu_dpm_set_power_limit(adev, limit_type, value); amdgpu_pm_put_access(adev); diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h index cda2d7f77c015..f824bc4bba9e7 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h @@ -553,7 +553,7 @@ int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, enum pp_power_limit_level pp_limit_level, enum pp_power_type power_type); int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, - uint32_t limit); + uint32_t limit_type, uint32_t limit); int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev); int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, struct seq_file *m); diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index fb595a70bbd11..76a5353d7f4a1 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -952,7 +952,7 @@ static int pp_dpm_switch_power_profile(void *handle, return 0; } -static int pp_set_power_limit(void *handle, uint32_t limit) +static int pp_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit) { struct pp_hwmgr *hwmgr = handle; uint32_t max_power_limit; diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 91e112491dec2..fc0bc8b5a640c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -68,7 +68,7 @@ static int smu_handle_task(struct smu_context *smu, static int smu_reset(struct smu_context *smu); static int smu_set_fan_speed_pwm(void *handle, u32 speed); static int smu_set_fan_control_mode(void *handle, u32 value); -static int smu_set_power_limit(void *handle, uint32_t limit); +static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit); static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); @@ -510,7 +510,7 @@ static void smu_restore_dpm_user_profile(struct smu_context *smu) /* set the user dpm power limit */ if (smu->user_dpm_profile.power_limit) { - ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); + ret = smu_set_power_limit(smu, SMU_DEFAULT_PPT_LIMIT, smu->current_power_limit); if (ret) dev_err(smu->adev->dev, "Failed to set power limit value\n"); } @@ -2258,7 +2258,7 @@ static int smu_resume(struct amdgpu_ip_block *ip_block) adev->pm.dpm_enabled = true; if (smu->current_power_limit) { - ret = smu_set_power_limit(smu, smu->current_power_limit); + ret = smu_set_power_limit(smu, SMU_DEFAULT_PPT_LIMIT, smu->current_power_limit); if (ret && ret != -EOPNOTSUPP) return ret; } @@ -2958,16 +2958,14 @@ int smu_get_power_limit(void *handle, return ret; } -static int smu_set_power_limit(void *handle, uint32_t limit) +static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit) { struct smu_context *smu = handle; - uint32_t limit_type = limit >> 24; int ret = 0; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) return -EOPNOTSUPP; - limit &= (1<<24)-1; if (limit_type != SMU_DEFAULT_PPT_LIMIT) if (smu->ppt_funcs->set_power_limit) return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index 4c8e8e8379d06..a35e61f1d3f0f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -2401,7 +2401,6 @@ static int vangogh_set_power_limit(struct smu_context *smu, smu->current_power_limit = ppt_limit; break; case SMU_FAST_PPT_LIMIT: - ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24); if (ppt_limit > power_context->max_fast_ppt_limit) { dev_err(smu->adev->dev, "New power limit (%d) is over the max allowed %d\n", From d497fac7701e3585dbd698d79de66e39b70c9662 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 9 Oct 2025 15:59:05 -0500 Subject: [PATCH 2217/2653] drm/amd: Remove second call to set_power_limit() The min/max limits only make sense for default PPT. Restructure smu_set_power_limit() to only use them in that case. Reviewed-by: Lijo Lazar Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index fc0bc8b5a640c..9492b26943e65 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2966,20 +2966,17 @@ static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) return -EOPNOTSUPP; - if (limit_type != SMU_DEFAULT_PPT_LIMIT) - if (smu->ppt_funcs->set_power_limit) - return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); - - if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { - dev_err(smu->adev->dev, - "New power limit (%d) is out of range [%d,%d]\n", - limit, smu->min_power_limit, smu->max_power_limit); - return -EINVAL; + if (limit_type == SMU_DEFAULT_PPT_LIMIT) { + if (!limit) + limit = smu->current_power_limit; + if ((limit > smu->max_power_limit) || (limit < smu->min_power_limit)) { + dev_err(smu->adev->dev, + "New power limit (%d) is out of range [%d,%d]\n", + limit, smu->min_power_limit, smu->max_power_limit); + return -EINVAL; + } } - if (!limit) - limit = smu->current_power_limit; - if (smu->ppt_funcs->set_power_limit) { ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) From a96dcae1e96469f10923f5f7cd8ff08b0f0a4256 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 9 Oct 2025 15:59:06 -0500 Subject: [PATCH 2218/2653] drm/amd: Save and restore all limit types Vangogh has separate limits for default PPT and fast PPT. Add infrastructure to save both of these limits and restore both of them. Reviewed-by: Lijo Lazar Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 19 ++++++++++++------- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 3 ++- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 9492b26943e65..421b6816444ea 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -508,11 +508,14 @@ static void smu_restore_dpm_user_profile(struct smu_context *smu) /* Enable restore flag */ smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; - /* set the user dpm power limit */ - if (smu->user_dpm_profile.power_limit) { - ret = smu_set_power_limit(smu, SMU_DEFAULT_PPT_LIMIT, smu->current_power_limit); + /* set the user dpm power limits */ + for (int i = SMU_DEFAULT_PPT_LIMIT; i < SMU_LIMIT_TYPE_COUNT; i++) { + if (!smu->user_dpm_profile.power_limits[i]) + continue; + ret = smu_set_power_limit(smu, i, + smu->user_dpm_profile.power_limits[i]); if (ret) - dev_err(smu->adev->dev, "Failed to set power limit value\n"); + dev_err(smu->adev->dev, "Failed to set %d power limit value\n", i); } /* set the user dpm clock configurations */ @@ -2979,11 +2982,13 @@ static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit if (smu->ppt_funcs->set_power_limit) { ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); - if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) - smu->user_dpm_profile.power_limit = limit; + if (ret) + return ret; + if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) + smu->user_dpm_profile.power_limits[limit_type] = limit; } - return ret; + return 0; } static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 148153b3025b7..4c00f6edebaec 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -212,6 +212,7 @@ enum smu_power_src_type { enum smu_ppt_limit_type { SMU_DEFAULT_PPT_LIMIT = 0, SMU_FAST_PPT_LIMIT, + SMU_LIMIT_TYPE_COUNT, }; enum smu_ppt_limit_level { @@ -231,7 +232,7 @@ enum smu_memory_pool_size { struct smu_user_dpm_profile { uint32_t fan_mode; - uint32_t power_limit; + uint32_t power_limits[SMU_LIMIT_TYPE_COUNT]; uint32_t fan_speed_pwm; uint32_t fan_speed_rpm; uint32_t flags; From 5cb48b2358554cd192a0764232b0e6901736084a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 27 Aug 2025 11:34:14 -0400 Subject: [PATCH 2219/2653] drm/amdgpu: clean up and unify hw fence handling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Decouple the amdgpu fence from the amdgpu_job structure. This lets us clean up the separate fence ops for the embedded fence and other fences. This also allows us to allocate the vm fence up front when we allocate the job. v2: Additional cleanup suggested by Christian v3: Additional cleanups suggested by Christian v4: Additional cleanups suggested by David and vm fence fix v5: cast seqno (David) Cc: David.Wu3@amd.com Cc: christian.koenig@amd.com Tested-by: David (Ming Qiang) Wu Reviewed-by: David (Ming Qiang) Wu Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 143 ++------------------ drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 17 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 43 ++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 7 +- 8 files changed, 63 insertions(+), 167 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 6fdcd9c783247..186f5412a6197 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -1906,7 +1906,7 @@ static void amdgpu_ib_preempt_mark_partial_job(struct amdgpu_ring *ring) continue; } job = to_amdgpu_job(s_job); - if (preempted && (&job->hw_fence.base) == fence) + if (preempted && (&job->hw_fence->base) == fence) /* mark the job as preempted */ job->preemption_status |= AMDGPU_IB_PREEMPTED; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 4cb5e433ce648..e77bc1870486f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5860,11 +5860,6 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, if (!amdgpu_ring_sched_ready(ring)) continue; - /* Clear job fence from fence drv to avoid force_completion - * leave NULL and vm flush fence in fence drv - */ - amdgpu_fence_driver_clear_job_fences(ring); - /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ amdgpu_fence_driver_force_completion(ring); } @@ -6598,7 +6593,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, * * job->base holds a reference to parent fence */ - if (job && dma_fence_is_signaled(&job->hw_fence.base)) { + if (job && dma_fence_is_signaled(&job->hw_fence->base)) { job_signaled = true; dev_info(adev->dev, "Guilty job already signaled, skipping HW reset"); goto skip_hw_reset; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 9dc0001f97da8..52d8522381ad8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -45,16 +45,11 @@ * Cast helper */ static const struct dma_fence_ops amdgpu_fence_ops; -static const struct dma_fence_ops amdgpu_job_fence_ops; static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f) { struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); - if (__f->base.ops == &amdgpu_fence_ops || - __f->base.ops == &amdgpu_job_fence_ops) - return __f; - - return NULL; + return __f; } /** @@ -98,51 +93,32 @@ static u32 amdgpu_fence_read(struct amdgpu_ring *ring) * amdgpu_fence_emit - emit a fence on the requested ring * * @ring: ring the fence is associated with - * @f: resulting fence object * @af: amdgpu fence input * @flags: flags to pass into the subordinate .emit_fence() call * * Emits a fence command on the requested ring (all asics). * Returns 0 on success, -ENOMEM on failure. */ -int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, - struct amdgpu_fence *af, unsigned int flags) +int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, + unsigned int flags) { struct amdgpu_device *adev = ring->adev; struct dma_fence *fence; - struct amdgpu_fence *am_fence; struct dma_fence __rcu **ptr; uint32_t seq; int r; - if (!af) { - /* create a separate hw fence */ - am_fence = kzalloc(sizeof(*am_fence), GFP_KERNEL); - if (!am_fence) - return -ENOMEM; - } else { - am_fence = af; - } - fence = &am_fence->base; - am_fence->ring = ring; + fence = &af->base; + af->ring = ring; seq = ++ring->fence_drv.sync_seq; - am_fence->seq = seq; - if (af) { - dma_fence_init(fence, &amdgpu_job_fence_ops, - &ring->fence_drv.lock, - adev->fence_context + ring->idx, seq); - /* Against remove in amdgpu_job_{free, free_cb} */ - dma_fence_get(fence); - } else { - dma_fence_init(fence, &amdgpu_fence_ops, - &ring->fence_drv.lock, - adev->fence_context + ring->idx, seq); - } + dma_fence_init(fence, &amdgpu_fence_ops, + &ring->fence_drv.lock, + adev->fence_context + ring->idx, seq); amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, seq, flags | AMDGPU_FENCE_FLAG_INT); - amdgpu_fence_save_wptr(fence); + amdgpu_fence_save_wptr(af); pm_runtime_get_noresume(adev_to_drm(adev)->dev); ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; if (unlikely(rcu_dereference_protected(*ptr, 1))) { @@ -167,8 +143,6 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, */ rcu_assign_pointer(*ptr, dma_fence_get(fence)); - *f = fence; - return 0; } @@ -669,36 +643,6 @@ void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev) } } -/** - * amdgpu_fence_driver_clear_job_fences - clear job embedded fences of ring - * - * @ring: fence of the ring to be cleared - * - */ -void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring) -{ - int i; - struct dma_fence *old, **ptr; - - for (i = 0; i <= ring->fence_drv.num_fences_mask; i++) { - ptr = &ring->fence_drv.fences[i]; - old = rcu_dereference_protected(*ptr, 1); - if (old && old->ops == &amdgpu_job_fence_ops) { - struct amdgpu_job *job; - - /* For non-scheduler bad job, i.e. failed ib test, we need to signal - * it right here or we won't be able to track them in fence_drv - * and they will remain unsignaled during sa_bo free. - */ - job = container_of(old, struct amdgpu_job, hw_fence.base); - if (!job->base.s_fence && !dma_fence_is_signaled(old)) - dma_fence_signal(old); - RCU_INIT_POINTER(*ptr, NULL); - dma_fence_put(old); - } - } -} - /** * amdgpu_fence_driver_set_error - set error code on fences * @ring: the ring which contains the fences @@ -754,7 +698,7 @@ void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) /** * amdgpu_fence_driver_guilty_force_completion - force signal of specified sequence * - * @fence: fence of the ring to signal + * @af: fence of the ring to signal * */ void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af) @@ -791,15 +735,13 @@ void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af) } while (last_seq != seq); spin_unlock_irqrestore(&ring->fence_drv.lock, flags); /* signal the guilty fence */ - amdgpu_fence_write(ring, af->seq); + amdgpu_fence_write(ring, (u32)af->base.seqno); amdgpu_fence_process(ring); } -void amdgpu_fence_save_wptr(struct dma_fence *fence) +void amdgpu_fence_save_wptr(struct amdgpu_fence *af) { - struct amdgpu_fence *am_fence = container_of(fence, struct amdgpu_fence, base); - - am_fence->wptr = am_fence->ring->wptr; + af->wptr = af->ring->wptr; } static void amdgpu_ring_backup_unprocessed_command(struct amdgpu_ring *ring, @@ -865,13 +807,6 @@ static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f) return (const char *)to_amdgpu_fence(f)->ring->name; } -static const char *amdgpu_job_fence_get_timeline_name(struct dma_fence *f) -{ - struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence.base); - - return (const char *)to_amdgpu_ring(job->base.sched)->name; -} - /** * amdgpu_fence_enable_signaling - enable signalling on fence * @f: fence @@ -888,23 +823,6 @@ static bool amdgpu_fence_enable_signaling(struct dma_fence *f) return true; } -/** - * amdgpu_job_fence_enable_signaling - enable signalling on job fence - * @f: fence - * - * This is the simliar function with amdgpu_fence_enable_signaling above, it - * only handles the job embedded fence. - */ -static bool amdgpu_job_fence_enable_signaling(struct dma_fence *f) -{ - struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence.base); - - if (!timer_pending(&to_amdgpu_ring(job->base.sched)->fence_drv.fallback_timer)) - amdgpu_fence_schedule_fallback(to_amdgpu_ring(job->base.sched)); - - return true; -} - /** * amdgpu_fence_free - free up the fence memory * @@ -920,21 +838,6 @@ static void amdgpu_fence_free(struct rcu_head *rcu) kfree(to_amdgpu_fence(f)); } -/** - * amdgpu_job_fence_free - free up the job with embedded fence - * - * @rcu: RCU callback head - * - * Free up the job with embedded fence after the RCU grace period. - */ -static void amdgpu_job_fence_free(struct rcu_head *rcu) -{ - struct dma_fence *f = container_of(rcu, struct dma_fence, rcu); - - /* free job if fence has a parent job */ - kfree(container_of(f, struct amdgpu_job, hw_fence.base)); -} - /** * amdgpu_fence_release - callback that fence can be freed * @@ -948,19 +851,6 @@ static void amdgpu_fence_release(struct dma_fence *f) call_rcu(&f->rcu, amdgpu_fence_free); } -/** - * amdgpu_job_fence_release - callback that job embedded fence can be freed - * - * @f: fence - * - * This is the simliar function with amdgpu_fence_release above, it - * only handles the job embedded fence. - */ -static void amdgpu_job_fence_release(struct dma_fence *f) -{ - call_rcu(&f->rcu, amdgpu_job_fence_free); -} - static const struct dma_fence_ops amdgpu_fence_ops = { .get_driver_name = amdgpu_fence_get_driver_name, .get_timeline_name = amdgpu_fence_get_timeline_name, @@ -968,13 +858,6 @@ static const struct dma_fence_ops amdgpu_fence_ops = { .release = amdgpu_fence_release, }; -static const struct dma_fence_ops amdgpu_job_fence_ops = { - .get_driver_name = amdgpu_fence_get_driver_name, - .get_timeline_name = amdgpu_job_fence_get_timeline_name, - .enable_signaling = amdgpu_job_fence_enable_signaling, - .release = amdgpu_job_fence_release, -}; - /* * Fence debugfs */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 85aad8a233f9a..c8def27b6d1cd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -150,17 +150,19 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, if (job) { vm = job->vm; fence_ctx = job->base.s_fence ? - job->base.s_fence->scheduled.context : 0; + job->base.s_fence->finished.context : 0; shadow_va = job->shadow_va; csa_va = job->csa_va; gds_va = job->gds_va; init_shadow = job->init_shadow; - af = &job->hw_fence; + af = job->hw_fence; /* Save the context of the job for reset handling. * The driver needs this so it can skip the ring * contents for guilty contexts. */ - af->context = job->base.s_fence ? job->base.s_fence->finished.context : 0; + af->context = fence_ctx; + /* the vm fence is also part of the job's context */ + job->hw_vm_fence->context = fence_ctx; } else { vm = NULL; fence_ctx = 0; @@ -168,7 +170,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, csa_va = 0; gds_va = 0; init_shadow = false; - af = NULL; + af = kzalloc(sizeof(*af), GFP_ATOMIC); + if (!af) + return -ENOMEM; } if (!ring->sched.ready) { @@ -297,7 +301,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr); } - r = amdgpu_fence_emit(ring, f, af, fence_flags); + r = amdgpu_fence_emit(ring, af, fence_flags); if (r) { dev_err(adev->dev, "failed to emit fence (%d)\n", r); if (job && job->vmid) @@ -305,6 +309,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, amdgpu_ring_undo(ring); return r; } + *f = &af->base; if (ring->funcs->insert_end) ring->funcs->insert_end(ring); @@ -325,7 +330,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, * fence so we know what rings contents to backup * after we reset the queue. */ - amdgpu_fence_save_wptr(*f); + amdgpu_fence_save_wptr(af); amdgpu_ring_ib_end(ring); amdgpu_ring_commit(ring); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 172620880cada..55c7e104d5ca0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -137,7 +137,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) ring->funcs->reset) { dev_err(adev->dev, "Starting %s ring reset\n", s_job->sched->name); - r = amdgpu_ring_reset(ring, job->vmid, &job->hw_fence); + r = amdgpu_ring_reset(ring, job->vmid, job->hw_fence); if (!r) { atomic_inc(&ring->adev->gpu_reset_counter); dev_err(adev->dev, "Ring %s reset succeeded\n", @@ -187,6 +187,9 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int num_ibs, struct amdgpu_job **job, u64 drm_client_id) { + struct amdgpu_fence *af; + int r; + if (num_ibs == 0) return -EINVAL; @@ -194,6 +197,20 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm, if (!*job) return -ENOMEM; + af = kzalloc(sizeof(struct amdgpu_fence), GFP_KERNEL); + if (!af) { + r = -ENOMEM; + goto err_job; + } + (*job)->hw_fence = af; + + af = kzalloc(sizeof(struct amdgpu_fence), GFP_KERNEL); + if (!af) { + r = -ENOMEM; + goto err_fence; + } + (*job)->hw_vm_fence = af; + (*job)->vm = vm; amdgpu_sync_create(&(*job)->explicit_sync); @@ -205,6 +222,13 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm, return drm_sched_job_init(&(*job)->base, entity, 1, owner, drm_client_id); + +err_fence: + kfree((*job)->hw_fence); +err_job: + kfree(*job); + + return r; } int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, @@ -251,11 +275,11 @@ void amdgpu_job_free_resources(struct amdgpu_job *job) struct dma_fence *f; unsigned i; - /* Check if any fences where initialized */ + /* Check if any fences were initialized */ if (job->base.s_fence && job->base.s_fence->finished.ops) f = &job->base.s_fence->finished; - else if (job->hw_fence.base.ops) - f = &job->hw_fence.base; + else if (job->hw_fence && job->hw_fence->base.ops) + f = &job->hw_fence->base; else f = NULL; @@ -271,11 +295,7 @@ static void amdgpu_job_free_cb(struct drm_sched_job *s_job) amdgpu_sync_free(&job->explicit_sync); - /* only put the hw fence if has embedded fence */ - if (!job->hw_fence.base.ops) - kfree(job); - else - dma_fence_put(&job->hw_fence.base); + kfree(job); } void amdgpu_job_set_gang_leader(struct amdgpu_job *job, @@ -304,10 +324,7 @@ void amdgpu_job_free(struct amdgpu_job *job) if (job->gang_submit != &job->base.s_fence->scheduled) dma_fence_put(job->gang_submit); - if (!job->hw_fence.base.ops) - kfree(job); - else - dma_fence_put(&job->hw_fence.base); + kfree(job); } struct dma_fence *amdgpu_job_submit(struct amdgpu_job *job) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h index 2f302266662bc..d25f1fcf0242e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h @@ -48,7 +48,8 @@ struct amdgpu_job { struct drm_sched_job base; struct amdgpu_vm *vm; struct amdgpu_sync explicit_sync; - struct amdgpu_fence hw_fence; + struct amdgpu_fence *hw_fence; + struct amdgpu_fence *hw_vm_fence; struct dma_fence *gang_submit; uint32_t preamble_status; uint32_t preemption_status; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 4b46e3c26ff39..87b962df54607 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -147,16 +147,14 @@ struct amdgpu_fence { u64 wptr; /* fence context for resets */ u64 context; - uint32_t seq; }; extern const struct drm_sched_backend_ops amdgpu_sched_ops; -void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring); void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error); void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af); -void amdgpu_fence_save_wptr(struct dma_fence *fence); +void amdgpu_fence_save_wptr(struct amdgpu_fence *af); int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, @@ -166,8 +164,8 @@ void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev); void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev); int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev); void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev); -int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, - struct amdgpu_fence *af, unsigned int flags); +int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, + unsigned int flags); int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s, uint32_t timeout); bool amdgpu_fence_process(struct amdgpu_ring *ring); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 6eb1c1acb14e3..e4a085d75a3cd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -779,7 +779,6 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool cleaner_shader_needed = false; bool pasid_mapping_needed = false; struct dma_fence *fence = NULL; - struct amdgpu_fence *af; unsigned int patch; int r; @@ -842,12 +841,10 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, } if (vm_flush_needed || pasid_mapping_needed || cleaner_shader_needed) { - r = amdgpu_fence_emit(ring, &fence, NULL, 0); + r = amdgpu_fence_emit(ring, job->hw_vm_fence, 0); if (r) return r; - /* this is part of the job's context */ - af = container_of(fence, struct amdgpu_fence, base); - af->context = job->base.s_fence ? job->base.s_fence->finished.context : 0; + fence = &job->hw_vm_fence->base; } if (vm_flush_needed) { From f72c0179d8407660cdbfb3af96723d1b477d09ed Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Fri, 10 Oct 2025 16:24:01 +0800 Subject: [PATCH 2220/2653] drm/amdkcl: fix suballoc helper availability for distro kernels Some distribution kernels include drm/drm_suballoc.h header but have CONFIG_DRM_SUBALLOC_HELPER disabled. This causes build failures as the suballoc symbols are unavailable from the main DRM subsystem. Move the #endif directive for HAVE_DRM_DRM_SUBALLOC_H to properly expose KCL suballoc fallback implementations when the main DRM suballoc helper is not available. This ensures amdgpu can use kcl_drm_suballoc functions as fallback and resolves DKMS build failures on such configurations. Signed-off-by: Perry Yuan Reviewed-by: Bob Zhou --- include/kcl/kcl_drm_suballoc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_drm_suballoc.h b/include/kcl/kcl_drm_suballoc.h index 7629274cc4a0a..8a176ebc933ed 100644 --- a/include/kcl/kcl_drm_suballoc.h +++ b/include/kcl/kcl_drm_suballoc.h @@ -51,6 +51,7 @@ struct drm_suballoc { size_t eoffset; struct dma_fence *fence; }; +#endif /*HAVE_DRM_DRM_SUBALLOC_H*/ #ifndef HAVE_DRM_SUBALLOC_MANAGER_INIT void kcl_drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, @@ -119,6 +120,5 @@ kcl_drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, #define drm_suballoc_dump_debug_info kcl_drm_suballoc_dump_debug_info #endif /* HAVE_DRM_SUBALLOC_MANAGER_INIT */ -#endif /*HAVE_DRM_DRM_SUBALLOC_H*/ #endif /* _KCL_DRM_SUBALLOC_H_ */ From 800ee72960c247a91d1f64482a169100ed0ea54d Mon Sep 17 00:00:00 2001 From: Gui-Dong Han Date: Wed, 8 Oct 2025 03:43:27 +0000 Subject: [PATCH 2221/2653] drm/amdgpu: use atomic functions with memory barriers for vm fault info The atomic variable vm_fault_info_updated is used to synchronize access to adev->gmc.vm_fault_info between the interrupt handler and get_vm_fault_info(). The default atomic functions like atomic_set() and atomic_read() do not provide memory barriers. This allows for CPU instruction reordering, meaning the memory accesses to vm_fault_info and the vm_fault_info_updated flag are not guaranteed to occur in the intended order. This creates a race condition that can lead to inconsistent or stale data being used. The previous implementation, which used an explicit mb(), was incomplete and inefficient. It failed to account for all potential CPU reorderings, such as the access of vm_fault_info being reordered before the atomic_read of the flag. This approach is also more verbose and less performant than using the proper atomic functions with acquire/release semantics. Fix this by switching to atomic_set_release() and atomic_read_acquire(). These functions provide the necessary acquire and release semantics, which act as memory barriers to ensure the correct order of operations. It is also more efficient and idiomatic than using explicit full memory barriers. Fixes: b97dfa27ef3a ("drm/amdgpu: save vm fault information for amdkfd") Cc: stable@vger.kernel.org Signed-off-by: Gui-Dong Han Signed-off-by: Felix Kuehling Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 ++--- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 7 +++---- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 7 +++---- 3 files changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 253b663c088a1..568a8573da99a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2459,10 +2459,9 @@ void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem) int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, struct kfd_vm_fault_info *mem) { - if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) { + if (atomic_read_acquire(&adev->gmc.vm_fault_info_updated) == 1) { *mem = *adev->gmc.vm_fault_info; - mb(); /* make sure read happened */ - atomic_set(&adev->gmc.vm_fault_info_updated, 0); + atomic_set_release(&adev->gmc.vm_fault_info_updated, 0); } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 3851033f4bd5b..590458aa83e4c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1067,7 +1067,7 @@ static int gmc_v7_0_sw_init(struct amdgpu_ip_block *ip_block) GFP_KERNEL); if (!adev->gmc.vm_fault_info) return -ENOMEM; - atomic_set(&adev->gmc.vm_fault_info_updated, 0); + atomic_set_release(&adev->gmc.vm_fault_info_updated, 0); return 0; } @@ -1289,7 +1289,7 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) - && !atomic_read(&adev->gmc.vm_fault_info_updated)) { + && !atomic_read_acquire(&adev->gmc.vm_fault_info_updated)) { struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, @@ -1305,8 +1305,7 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, info->prot_read = protections & 0x8 ? true : false; info->prot_write = protections & 0x10 ? true : false; info->prot_exec = protections & 0x20 ? true : false; - mb(); - atomic_set(&adev->gmc.vm_fault_info_updated, 1); + atomic_set_release(&adev->gmc.vm_fault_info_updated, 1); } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 7ea209a3da202..6cd6fc2062dc9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1187,7 +1187,7 @@ static int gmc_v8_0_sw_init(struct amdgpu_ip_block *ip_block) GFP_KERNEL); if (!adev->gmc.vm_fault_info) return -ENOMEM; - atomic_set(&adev->gmc.vm_fault_info_updated, 0); + atomic_set_release(&adev->gmc.vm_fault_info_updated, 0); return 0; } @@ -1482,7 +1482,7 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) - && !atomic_read(&adev->gmc.vm_fault_info_updated)) { + && !atomic_read_acquire(&adev->gmc.vm_fault_info_updated)) { struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, @@ -1498,8 +1498,7 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, info->prot_read = protections & 0x8 ? true : false; info->prot_write = protections & 0x10 ? true : false; info->prot_exec = protections & 0x20 ? true : false; - mb(); - atomic_set(&adev->gmc.vm_fault_info_updated, 1); + atomic_set_release(&adev->gmc.vm_fault_info_updated, 1); } return 0; From 08322d5cf8a21f443a5bd565e12b3c681266008d Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 10 Oct 2025 17:12:52 +0530 Subject: [PATCH 2222/2653] drm/amdgpu: Add amdgpu_discovery_info Add amdgpu_discovery_info structure to keep all discovery related information. Signed-off-by: Lijo Lazar Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 10 +- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 7 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 192 ++++++++++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 11 + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- 6 files changed, 129 insertions(+), 97 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 395424529c0b4..2ab128d8bd0bb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -856,8 +856,6 @@ struct amd_powerplay { const struct amd_pm_funcs *pp_funcs; }; -struct ip_discovery_top; - /* polaris10 kickers */ #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ ((rid == 0xE3) || \ @@ -989,8 +987,7 @@ struct amdgpu_device { struct notifier_block acpi_nb; struct notifier_block pm_nb; struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; - struct debugfs_blob_wrapper debugfs_vbios_blob; - struct debugfs_blob_wrapper debugfs_discovery_blob; + struct debugfs_blob_wrapper debugfs_vbios_blob; struct mutex srbm_mutex; /* GRBM index mutex. Protects concurrent access to GRBM index */ struct mutex grbm_idx_mutex; @@ -1083,6 +1080,9 @@ struct amdgpu_device { u32 log2_max_MBps; } mm_stats; + /* discovery*/ + struct amdgpu_discovery_info discovery; + /* display */ bool enable_virtual_display; struct amdgpu_vkms_output *amdgpu_vkms_output; @@ -1293,8 +1293,6 @@ struct amdgpu_device { struct list_head ras_list; - struct ip_discovery_top *ip_top; - struct amdgpu_reset_domain *reset_domain; struct mutex benchmark_mutex; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 186f5412a6197..8f380619cab13 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -2131,10 +2131,9 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) debugfs_create_blob("amdgpu_vbios", 0444, root, &adev->debugfs_vbios_blob); - adev->debugfs_discovery_blob.data = adev->mman.discovery_bin; - adev->debugfs_discovery_blob.size = adev->mman.discovery_tmr_size; - debugfs_create_blob("amdgpu_discovery", 0444, root, - &adev->debugfs_discovery_blob); + if (adev->discovery.debugfs_blob.size) + debugfs_create_blob("amdgpu_discovery", 0444, root, + &adev->discovery.debugfs_blob); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index e77bc1870486f..e21ce1eb365bb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2658,7 +2658,7 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) chip_name = "arcturus"; break; case CHIP_NAVI12: - if (adev->mman.discovery_bin) + if (adev->discovery.bin) return 0; chip_name = "navi12"; break; @@ -5096,7 +5096,7 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev) if (IS_ENABLED(CONFIG_PERF_EVENTS)) amdgpu_pmu_fini(adev); - if (adev->mman.discovery_bin) + if (adev->discovery.bin) amdgpu_discovery_fini(adev); amdgpu_reset_put_reset_domain(adev->reset_domain); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 5c9908b6a10ba..223b5da4f21af 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -254,9 +254,9 @@ static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; /* This region is read-only and reserved from system use */ - discv_regn = memremap(pos, adev->mman.discovery_tmr_size, MEMREMAP_WC); + discv_regn = memremap(pos, adev->discovery.size, MEMREMAP_WC); if (discv_regn) { - memcpy(binary, discv_regn, adev->mman.discovery_tmr_size); + memcpy(binary, discv_regn, adev->discovery.size); memunmap(discv_regn); return 0; } @@ -301,7 +301,7 @@ static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, if (sz_valid) { uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, - adev->mman.discovery_tmr_size, false); + adev->discovery.size, false); } else { ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); } @@ -389,6 +389,7 @@ static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, struct binary_header *bhdr) { + uint8_t *discovery_bin = adev->discovery.bin; struct table_info *info; uint16_t checksum; uint16_t offset; @@ -398,14 +399,14 @@ static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, checksum = le16_to_cpu(info->checksum); struct nps_info_header *nhdr = - (struct nps_info_header *)(adev->mman.discovery_bin + offset); + (struct nps_info_header *)(discovery_bin + offset); if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); return -EINVAL; } - if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, + if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, le32_to_cpu(nhdr->size_bytes), checksum)) { dev_dbg(adev->dev, "invalid nps info data table checksum\n"); @@ -447,49 +448,53 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) { struct table_info *info; struct binary_header *bhdr; + uint8_t *discovery_bin; const char *fw_name; uint16_t offset; uint16_t size; uint16_t checksum; int r; - adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE; - adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL); - if (!adev->mman.discovery_bin) + adev->discovery.bin = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL); + if (!adev->discovery.bin) return -ENOMEM; + adev->discovery.size = DISCOVERY_TMR_SIZE; + adev->discovery.debugfs_blob.data = adev->discovery.bin; + adev->discovery.debugfs_blob.size = adev->discovery.size; + discovery_bin = adev->discovery.bin; /* Read from file if it is the preferred option */ fw_name = amdgpu_discovery_get_fw_name(adev); if (fw_name != NULL) { drm_dbg(&adev->ddev, "use ip discovery information from file"); - r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin, fw_name); + r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin, + fw_name); if (r) goto out; } else { drm_dbg(&adev->ddev, "use ip discovery information from memory"); - r = amdgpu_discovery_read_binary_from_mem( - adev, adev->mman.discovery_bin); + r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin); if (r) goto out; } /* check the ip discovery binary signature */ - if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) { + if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) { dev_err(adev->dev, "get invalid ip discovery binary signature\n"); r = -EINVAL; goto out; } - bhdr = (struct binary_header *)adev->mman.discovery_bin; + bhdr = (struct binary_header *)discovery_bin; offset = offsetof(struct binary_header, binary_checksum) + sizeof(bhdr->binary_checksum); size = le16_to_cpu(bhdr->binary_size) - offset; checksum = le16_to_cpu(bhdr->binary_checksum); - if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, - size, checksum)) { + if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, size, + checksum)) { dev_err(adev->dev, "invalid ip discovery binary checksum\n"); r = -EINVAL; goto out; @@ -501,15 +506,16 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) if (offset) { struct ip_discovery_header *ihdr = - (struct ip_discovery_header *)(adev->mman.discovery_bin + offset); + (struct ip_discovery_header *)(discovery_bin + offset); if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { dev_err(adev->dev, "invalid ip discovery data table signature\n"); r = -EINVAL; goto out; } - if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, - le16_to_cpu(ihdr->size), checksum)) { + if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, + le16_to_cpu(ihdr->size), + checksum)) { dev_err(adev->dev, "invalid ip discovery data table checksum\n"); r = -EINVAL; goto out; @@ -522,7 +528,7 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) if (offset) { struct gpu_info_header *ghdr = - (struct gpu_info_header *)(adev->mman.discovery_bin + offset); + (struct gpu_info_header *)(discovery_bin + offset); if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { dev_err(adev->dev, "invalid ip discovery gc table id\n"); @@ -530,8 +536,9 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) goto out; } - if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, - le32_to_cpu(ghdr->size), checksum)) { + if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, + le32_to_cpu(ghdr->size), + checksum)) { dev_err(adev->dev, "invalid gc data table checksum\n"); r = -EINVAL; goto out; @@ -544,7 +551,7 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) if (offset) { struct harvest_info_header *hhdr = - (struct harvest_info_header *)(adev->mman.discovery_bin + offset); + (struct harvest_info_header *)(discovery_bin + offset); if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); @@ -552,8 +559,9 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) goto out; } - if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, - sizeof(struct harvest_table), checksum)) { + if (!amdgpu_discovery_verify_checksum( + discovery_bin + offset, + sizeof(struct harvest_table), checksum)) { dev_err(adev->dev, "invalid harvest data table checksum\n"); r = -EINVAL; goto out; @@ -566,7 +574,7 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) if (offset) { struct vcn_info_header *vhdr = - (struct vcn_info_header *)(adev->mman.discovery_bin + offset); + (struct vcn_info_header *)(discovery_bin + offset); if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { dev_err(adev->dev, "invalid ip discovery vcn table id\n"); @@ -574,8 +582,9 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) goto out; } - if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, - le32_to_cpu(vhdr->size_bytes), checksum)) { + if (!amdgpu_discovery_verify_checksum( + discovery_bin + offset, + le32_to_cpu(vhdr->size_bytes), checksum)) { dev_err(adev->dev, "invalid vcn data table checksum\n"); r = -EINVAL; goto out; @@ -588,7 +597,7 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) if (0 && offset) { struct mall_info_header *mhdr = - (struct mall_info_header *)(adev->mman.discovery_bin + offset); + (struct mall_info_header *)(discovery_bin + offset); if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { dev_err(adev->dev, "invalid ip discovery mall table id\n"); @@ -596,8 +605,9 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) goto out; } - if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset, - le32_to_cpu(mhdr->size_bytes), checksum)) { + if (!amdgpu_discovery_verify_checksum( + discovery_bin + offset, + le32_to_cpu(mhdr->size_bytes), checksum)) { dev_err(adev->dev, "invalid mall data table checksum\n"); r = -EINVAL; goto out; @@ -607,8 +617,8 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) return 0; out: - kfree(adev->mman.discovery_bin); - adev->mman.discovery_bin = NULL; + kfree(adev->discovery.bin); + adev->discovery.bin = NULL; if ((amdgpu_discovery != 2) && (RREG32(mmIP_DISCOVERY_VERSION) == 4)) amdgpu_ras_query_boot_status(adev, 4); @@ -620,8 +630,8 @@ static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev); void amdgpu_discovery_fini(struct amdgpu_device *adev) { amdgpu_discovery_sysfs_fini(adev); - kfree(adev->mman.discovery_bin); - adev->mman.discovery_bin = NULL; + kfree(adev->discovery.bin); + adev->discovery.bin = NULL; } static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev, @@ -646,6 +656,7 @@ static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev, static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, uint32_t *vcn_harvest_count) { + uint8_t *discovery_bin = adev->discovery.bin; struct binary_header *bhdr; struct ip_discovery_header *ihdr; struct die_header *dhdr; @@ -655,21 +666,21 @@ static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, uint8_t inst; int i, j; - bhdr = (struct binary_header *)adev->mman.discovery_bin; - ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + - le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); + bhdr = (struct binary_header *)discovery_bin; + ihdr = (struct ip_discovery_header + *)(discovery_bin + + le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); num_dies = le16_to_cpu(ihdr->num_dies); /* scan harvest bit of all IP data structures */ for (i = 0; i < num_dies; i++) { die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); - dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); + dhdr = (struct die_header *)(discovery_bin + die_offset); num_ips = le16_to_cpu(dhdr->num_ips); ip_offset = die_offset + sizeof(*dhdr); for (j = 0; j < num_ips; j++) { - ip = (struct ip *)(adev->mman.discovery_bin + - ip_offset); + ip = (struct ip *)(discovery_bin + ip_offset); inst = ip->number_instance; hw_id = le16_to_cpu(ip->hw_id); if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) @@ -711,13 +722,14 @@ static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, uint32_t *vcn_harvest_count, uint32_t *umc_harvest_count) { + uint8_t *discovery_bin = adev->discovery.bin; struct binary_header *bhdr; struct harvest_table *harvest_info; u16 offset; int i; uint32_t umc_harvest_config = 0; - bhdr = (struct binary_header *)adev->mman.discovery_bin; + bhdr = (struct binary_header *)discovery_bin; offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); if (!offset) { @@ -725,7 +737,7 @@ static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, return; } - harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset); + harvest_info = (struct harvest_table *)(discovery_bin + offset); for (i = 0; i < 32; i++) { if (le16_to_cpu(harvest_info->list[i].hw_id) == 0) @@ -1037,8 +1049,8 @@ static void ip_disc_release(struct kobject *kobj) kobj); struct amdgpu_device *adev = ip_top->adev; - adev->ip_top = NULL; kfree(ip_top); + adev->discovery.ip_top = NULL; } static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, @@ -1078,6 +1090,7 @@ static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, const size_t _ip_offset, const int num_ips, bool reg_base_64) { + uint8_t *discovery_bin = adev->discovery.bin; int ii, jj, kk, res; uint16_t hw_id; uint8_t inst; @@ -1095,7 +1108,7 @@ static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, struct ip_v4 *ip; struct ip_hw_instance *ip_hw_instance; - ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); + ip = (struct ip_v4 *)(discovery_bin + ip_offset); inst = ip->instance_number; hw_id = le16_to_cpu(ip->hw_id); if (amdgpu_discovery_validate_ip(adev, inst, hw_id) || @@ -1182,17 +1195,20 @@ static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) { + struct ip_discovery_top *ip_top = adev->discovery.ip_top; + uint8_t *discovery_bin = adev->discovery.bin; struct binary_header *bhdr; struct ip_discovery_header *ihdr; struct die_header *dhdr; - struct kset *die_kset = &adev->ip_top->die_kset; + struct kset *die_kset = &ip_top->die_kset; u16 num_dies, die_offset, num_ips; size_t ip_offset; int ii, res; - bhdr = (struct binary_header *)adev->mman.discovery_bin; - ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + - le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); + bhdr = (struct binary_header *)discovery_bin; + ihdr = (struct ip_discovery_header + *)(discovery_bin + + le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); num_dies = le16_to_cpu(ihdr->num_dies); DRM_DEBUG("number of dies: %d\n", num_dies); @@ -1201,7 +1217,7 @@ static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) struct ip_die_entry *ip_die_entry; die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); - dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); + dhdr = (struct die_header *)(discovery_bin + die_offset); num_ips = le16_to_cpu(dhdr->num_ips); ip_offset = die_offset + sizeof(*dhdr); @@ -1235,30 +1251,32 @@ static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) { + uint8_t *discovery_bin = adev->discovery.bin; + struct ip_discovery_top *ip_top; struct kset *die_kset; int res, ii; - if (!adev->mman.discovery_bin) + if (!discovery_bin) return -EINVAL; - adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); - if (!adev->ip_top) + ip_top = kzalloc(sizeof(*ip_top), GFP_KERNEL); + if (!ip_top) return -ENOMEM; - adev->ip_top->adev = adev; - - res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype, + ip_top->adev = adev; + adev->discovery.ip_top = ip_top; + res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype, &adev->dev->kobj, "ip_discovery"); if (res) { DRM_ERROR("Couldn't init and add ip_discovery/"); goto Err; } - die_kset = &adev->ip_top->die_kset; + die_kset = &ip_top->die_kset; kobject_set_name(&die_kset->kobj, "%s", "die"); - die_kset->kobj.parent = &adev->ip_top->kobj; + die_kset->kobj.parent = &ip_top->kobj; die_kset->kobj.ktype = &die_kobj_ktype; - res = kset_register(&adev->ip_top->die_kset); + res = kset_register(&ip_top->die_kset); if (res) { DRM_ERROR("Couldn't register die_kset"); goto Err; @@ -1272,7 +1290,7 @@ static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) return res; Err: - kobject_put(&adev->ip_top->kobj); + kobject_put(&ip_top->kobj); return res; } @@ -1317,10 +1335,11 @@ static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) { + struct ip_discovery_top *ip_top = adev->discovery.ip_top; struct list_head *el, *tmp; struct kset *die_kset; - die_kset = &adev->ip_top->die_kset; + die_kset = &ip_top->die_kset; spin_lock(&die_kset->list_lock); list_for_each_prev_safe(el, tmp, &die_kset->list) { list_del_init(el); @@ -1329,8 +1348,8 @@ static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) spin_lock(&die_kset->list_lock); } spin_unlock(&die_kset->list_lock); - kobject_put(&adev->ip_top->die_kset.kobj); - kobject_put(&adev->ip_top->kobj); + kobject_put(&ip_top->die_kset.kobj); + kobject_put(&ip_top->kobj); } /* ================================================== */ @@ -1341,6 +1360,7 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) struct binary_header *bhdr; struct ip_discovery_header *ihdr; struct die_header *dhdr; + uint8_t *discovery_bin; struct ip_v4 *ip; uint16_t die_offset; uint16_t ip_offset; @@ -1356,22 +1376,23 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) r = amdgpu_discovery_init(adev); if (r) return r; - + discovery_bin = adev->discovery.bin; wafl_ver = 0; adev->gfx.xcc_mask = 0; adev->sdma.sdma_mask = 0; adev->vcn.inst_mask = 0; adev->jpeg.inst_mask = 0; - bhdr = (struct binary_header *)adev->mman.discovery_bin; - ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + - le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); + bhdr = (struct binary_header *)discovery_bin; + ihdr = (struct ip_discovery_header + *)(discovery_bin + + le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); num_dies = le16_to_cpu(ihdr->num_dies); DRM_DEBUG("number of dies: %d\n", num_dies); for (i = 0; i < num_dies; i++) { die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); - dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset); + dhdr = (struct die_header *)(discovery_bin + die_offset); num_ips = le16_to_cpu(dhdr->num_ips); ip_offset = die_offset + sizeof(*dhdr); @@ -1385,7 +1406,7 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) le16_to_cpu(dhdr->die_id), num_ips); for (j = 0; j < num_ips; j++) { - ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset); + ip = (struct ip_v4 *)(discovery_bin + ip_offset); inst = ip->instance_number; hw_id = le16_to_cpu(ip->hw_id); @@ -1535,16 +1556,16 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) { + uint8_t *discovery_bin = adev->discovery.bin; struct ip_discovery_header *ihdr; struct binary_header *bhdr; int vcn_harvest_count = 0; int umc_harvest_count = 0; uint16_t offset, ihdr_ver; - bhdr = (struct binary_header *)adev->mman.discovery_bin; + bhdr = (struct binary_header *)discovery_bin; offset = le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset); - ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + - offset); + ihdr = (struct ip_discovery_header *)(discovery_bin + offset); ihdr_ver = le16_to_cpu(ihdr->version); /* * Harvest table does not fit Navi1x and legacy GPUs, @@ -1591,22 +1612,23 @@ union gc_info { static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) { + uint8_t *discovery_bin = adev->discovery.bin; struct binary_header *bhdr; union gc_info *gc_info; u16 offset; - if (!adev->mman.discovery_bin) { + if (!discovery_bin) { DRM_ERROR("ip discovery uninitialized\n"); return -EINVAL; } - bhdr = (struct binary_header *)adev->mman.discovery_bin; + bhdr = (struct binary_header *)discovery_bin; offset = le16_to_cpu(bhdr->table_list[GC].offset); if (!offset) return 0; - gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); + gc_info = (union gc_info *)(discovery_bin + offset); switch (le16_to_cpu(gc_info->v1.header.version_major)) { case 1: @@ -1699,24 +1721,25 @@ union mall_info { static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) { + uint8_t *discovery_bin = adev->discovery.bin; struct binary_header *bhdr; union mall_info *mall_info; u32 u, mall_size_per_umc, m_s_present, half_use; u64 mall_size; u16 offset; - if (!adev->mman.discovery_bin) { + if (!discovery_bin) { DRM_ERROR("ip discovery uninitialized\n"); return -EINVAL; } - bhdr = (struct binary_header *)adev->mman.discovery_bin; + bhdr = (struct binary_header *)discovery_bin; offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); if (!offset) return 0; - mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); + mall_info = (union mall_info *)(discovery_bin + offset); switch (le16_to_cpu(mall_info->v1.header.version_major)) { case 1: @@ -1755,12 +1778,13 @@ union vcn_info { static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) { + uint8_t *discovery_bin = adev->discovery.bin; struct binary_header *bhdr; union vcn_info *vcn_info; u16 offset; int v; - if (!adev->mman.discovery_bin) { + if (!discovery_bin) { DRM_ERROR("ip discovery uninitialized\n"); return -EINVAL; } @@ -1775,13 +1799,13 @@ static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) return -EINVAL; } - bhdr = (struct binary_header *)adev->mman.discovery_bin; + bhdr = (struct binary_header *)discovery_bin; offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); if (!offset) return 0; - vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); + vcn_info = (union vcn_info *)(discovery_bin + offset); switch (le16_to_cpu(vcn_info->v1.header.version_major)) { case 1: @@ -1841,6 +1865,7 @@ int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, struct amdgpu_gmc_memrange **ranges, int *range_cnt, bool refresh) { + uint8_t *discovery_bin = adev->discovery.bin; struct amdgpu_gmc_memrange *mem_ranges; struct binary_header *bhdr; union nps_info *nps_info; @@ -1857,13 +1882,13 @@ int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, return r; nps_info = &nps_data; } else { - if (!adev->mman.discovery_bin) { + if (!discovery_bin) { dev_err(adev->dev, "fetch mem range failed, ip discovery uninitialized\n"); return -EINVAL; } - bhdr = (struct binary_header *)adev->mman.discovery_bin; + bhdr = (struct binary_header *)discovery_bin; offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset); if (!offset) @@ -1873,8 +1898,7 @@ int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, if (amdgpu_discovery_verify_npsinfo(adev, bhdr)) return -ENOENT; - nps_info = - (union nps_info *)(adev->mman.discovery_bin + offset); + nps_info = (union nps_info *)(discovery_bin + offset); } switch (le16_to_cpu(nps_info->v1.header.version_major)) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h index b44d56465c5b9..b1eec3af3c4a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h @@ -24,9 +24,20 @@ #ifndef __AMDGPU_DISCOVERY__ #define __AMDGPU_DISCOVERY__ +#include + #define DISCOVERY_TMR_SIZE (10 << 10) #define DISCOVERY_TMR_OFFSET (64 << 10) +struct ip_discovery_top; + +struct amdgpu_discovery_info { + struct debugfs_blob_wrapper debugfs_blob; + struct ip_discovery_top *ip_top; + uint32_t size; + uint8_t *bin; +}; + void amdgpu_discovery_fini(struct amdgpu_device *adev); int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 271a342bae40b..782d877415b4c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2364,7 +2364,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) * If IP discovery enabled, a block of memory should be * reserved for IP discovey. */ - if (adev->mman.discovery_bin) { + if (adev->discovery.bin) { r = amdgpu_ttm_reserve_tmr(adev); if (r) return r; From f2617c978d7975744ef0c80b302dfb6c5f2d2b84 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 7 Oct 2025 18:30:24 +0530 Subject: [PATCH 2223/2653] drm/amdgpu: Move reset-on-init sequence earlier Complete reset-on-init sequence before sysfs interfaces are created. Devices get properly initiaized only after reset, and then only sysfs interfaces should be made available. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index e21ce1eb365bb..4bf2a5c15f7ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4848,6 +4848,8 @@ int amdgpu_device_init(struct amdgpu_device *adev, flush_delayed_work(&adev->delayed_init_work); } + if (adev->init_lvl->level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI) + amdgpu_xgmi_reset_on_init(adev); /* * Place those sysfs registering after `late_init`. As some of those * operations performed in `late_init` might affect the sysfs @@ -4915,9 +4917,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, if (px) vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); - if (adev->init_lvl->level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI) - amdgpu_xgmi_reset_on_init(adev); - amdgpu_device_check_iommu_direct_map(adev); adev->pm_nb.notifier_call = amdgpu_device_pm_notifier; From 92cd3bffe487d53a4e77d48ac19e4c051100a331 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 27 Aug 2025 14:47:23 +0200 Subject: [PATCH 2224/2653] drm/amdgpu: remove two invalid BUG_ON()s MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Those can be triggered trivially by userspace. Signed-off-by: Christian König Reviewed-by: Alex Deucher Acked-by: Timur Kristóf --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 -- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 2 -- 2 files changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 39e8cbb2b5034..4adaba2d85de7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -5863,8 +5863,6 @@ static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, unsigned vmid = AMDGPU_JOB_GET_VMID(job); u32 header, control = 0; - BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); - header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); control |= ib->length_dw | (vmid << 24); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index c95d907f1faa1..25a20cab71a2f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -4420,8 +4420,6 @@ static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, unsigned vmid = AMDGPU_JOB_GET_VMID(job); u32 header, control = 0; - BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE); - header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); control |= ib->length_dw | (vmid << 24); From bd845f9afc9dbf7efc2188e99c0e7664c1a723cb Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 8 Oct 2025 13:07:13 +0530 Subject: [PATCH 2225/2653] drm/amd/pm: Grant interface access after full init Allow access to user interfaces like sysfs/hwmon only after full initialization of the device. When device is part of XGMI hive and a reset is required during initialization, the inteface files will be created as part of minimal device initialization. Full initialization of the device will be done only after all devices in XGMI hive are probed and a reset is done together on all. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 6b1ce52f4acf5..91f8f9547ee76 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -108,8 +108,9 @@ const char * const amdgpu_pp_profile_name[] = { static int amdgpu_pm_dev_state_check(struct amdgpu_device *adev, bool runpm) { bool runpm_check = runpm ? adev->in_runpm : false; + bool full_init = (adev->init_lvl->level == AMDGPU_INIT_LEVEL_DEFAULT); - if (amdgpu_in_reset(adev)) + if (amdgpu_in_reset(adev) || !full_init) return -EBUSY; if (adev->in_suspend && !runpm_check) From 03b982fc470c23bb4a437500c8d95eb6dae4619b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 22 Sep 2025 14:18:16 +0200 Subject: [PATCH 2226/2653] drm/amdgpu: block CE CS if not explicitely allowed by module option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Constant Engine found on gfx6-gfx10 HW has been a notorious source of problems. RADV never used it in the first place, radeonsi only used it for a few releases around 2017 for gfx6-gfx9 before dropping support for it as well. While investigating another problem I just recently found that submitting to the CE seems to be completely broken on gfx9 for quite a while. Since nobody complained about that problem it most likely means that nobody is using any of the affected radeonsi versions on current Linux kernels any more. So to potentially phase out the support for the CE and eliminate another source of problems block submitting CE IBs unless it is enabled again using a debug flag. Signed-off-by: Christian König Reviewed-by: Alex Deucher Acked-by: Timur Kristóf --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 +++++++- 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 2ab128d8bd0bb..ad578ea8116d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1316,6 +1316,7 @@ struct amdgpu_device { bool debug_disable_gpu_ring_reset; bool debug_vm_userptr; bool debug_disable_ce_logs; + bool debug_enable_ce_cs; /* Protection for the following isolation structure */ struct mutex enforce_isolation_mutex; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index d209d17a08ee8..63562a978c6bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -374,6 +374,12 @@ static int amdgpu_cs_p2_ib(struct amdgpu_cs_parser *p, if (p->uf_bo && ring->funcs->no_user_fence) return -EINVAL; + if (!p->adev->debug_enable_ce_cs && + chunk_ib->flags & AMDGPU_IB_FLAG_CE) { + dev_err_ratelimited(p->adev->dev, "CE CS is blocked, use debug=0x400 to override\n"); + return -EINVAL; + } + if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) { if (chunk_ib->flags & AMDGPU_IB_FLAG_CE) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 320b836b90e24..9a754ba2cdd24 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -144,7 +144,8 @@ enum AMDGPU_DEBUG_MASK { AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6), AMDGPU_DEBUG_SMU_POOL = BIT(7), AMDGPU_DEBUG_VM_USERPTR = BIT(8), - AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9) + AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9), + AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10) }; unsigned int amdgpu_vram_limit = UINT_MAX; @@ -2307,6 +2308,11 @@ static void amdgpu_init_debug_options(struct amdgpu_device *adev) pr_info("debug: disable kernel logs of correctable errors\n"); adev->debug_disable_ce_logs = true; } + + if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_CE_CS) { + pr_info("debug: allowing command submission to CE engine\n"); + adev->debug_enable_ce_cs = true; + } } static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) From 30e6d237f81defa24989ef2a0da0fcdf2203af07 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 7 Oct 2025 18:12:04 +0530 Subject: [PATCH 2227/2653] drm/amdgpu: Reorganize sysfs ini/fini calls Aggregate sysfs ini/fini calls into separate functions. No functional change. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 95 +++++++++++++--------- 1 file changed, 55 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 4bf2a5c15f7ad..0accf31aa80cd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4410,6 +4410,59 @@ static void amdgpu_device_set_mcbp(struct amdgpu_device *adev) dev_info(adev->dev, "MCBP is enabled\n"); } +static int amdgpu_device_sys_interface_init(struct amdgpu_device *adev) +{ + int r; + +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS + r = amdgpu_atombios_sysfs_init(adev); + if (r) + drm_err(&adev->ddev, + "registering atombios sysfs failed (%d).\n", r); +#endif + + r = amdgpu_pm_sysfs_init(adev); + if (r) + dev_err(adev->dev, "registering pm sysfs failed (%d).\n", r); + + r = amdgpu_ucode_sysfs_init(adev); + if (r) { + adev->ucode_sysfs_en = false; + dev_err(adev->dev, "Creating firmware sysfs failed (%d).\n", r); + } else + adev->ucode_sysfs_en = true; + + r = amdgpu_device_attr_sysfs_init(adev); + if (r) + dev_err(adev->dev, "Could not create amdgpu device attr\n"); + +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS + r = devm_device_add_group(adev->dev, &amdgpu_board_attrs_group); + if (r) + dev_err(adev->dev, + "Could not create amdgpu board attributes\n"); +#endif + + amdgpu_fru_sysfs_init(adev); + amdgpu_reg_state_sysfs_init(adev); + amdgpu_xcp_sysfs_init(adev); + + return r; +} + +static void amdgpu_device_sys_interface_fini(struct amdgpu_device *adev) +{ + if (adev->pm.sysfs_initialized) + amdgpu_pm_sysfs_fini(adev); + if (adev->ucode_sysfs_en) + amdgpu_ucode_sysfs_fini(adev); + amdgpu_device_attr_sysfs_fini(adev); + amdgpu_fru_sysfs_fini(adev); + + amdgpu_reg_state_sysfs_fini(adev); + amdgpu_xcp_sysfs_fini(adev); +} + /** * amdgpu_device_init - initialize the driver * @@ -4855,37 +4908,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, * operations performed in `late_init` might affect the sysfs * interfaces creating. */ -#ifdef HAVE_PCI_DRIVER_DEV_GROUPS - r = amdgpu_atombios_sysfs_init(adev); - if (r) - drm_err(&adev->ddev, - "registering atombios sysfs failed (%d).\n", r); -#endif - - r = amdgpu_pm_sysfs_init(adev); - if (r) - dev_err(adev->dev, "registering pm sysfs failed (%d).\n", r); - - r = amdgpu_ucode_sysfs_init(adev); - if (r) { - adev->ucode_sysfs_en = false; - dev_err(adev->dev, "Creating firmware sysfs failed (%d).\n", r); - } else - adev->ucode_sysfs_en = true; - - r = amdgpu_device_attr_sysfs_init(adev); - if (r) - dev_err(adev->dev, "Could not create amdgpu device attr\n"); -#ifdef HAVE_PCI_DRIVER_DEV_GROUPS - r = devm_device_add_group(adev->dev, &amdgpu_board_attrs_group); - if (r) - dev_err(adev->dev, - "Could not create amdgpu board attributes\n"); -#endif - - amdgpu_fru_sysfs_init(adev); - amdgpu_reg_state_sysfs_init(adev); - amdgpu_xcp_sysfs_init(adev); + r = amdgpu_device_sys_interface_init(adev); if (IS_ENABLED(CONFIG_PERF_EVENTS)) r = amdgpu_pmu_init(adev); @@ -5008,15 +5031,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) } amdgpu_fence_driver_hw_fini(adev); - if (adev->pm.sysfs_initialized) - amdgpu_pm_sysfs_fini(adev); - if (adev->ucode_sysfs_en) - amdgpu_ucode_sysfs_fini(adev); - amdgpu_device_attr_sysfs_fini(adev); - amdgpu_fru_sysfs_fini(adev); - - amdgpu_reg_state_sysfs_fini(adev); - amdgpu_xcp_sysfs_fini(adev); + amdgpu_device_sys_interface_fini(adev); /* disable ras feature must before hw fini */ amdgpu_ras_pre_fini(adev); From 9df713ccc60fdb8be4e2dc421a7b938fb36258a8 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Mon, 13 Oct 2025 10:16:37 +0800 Subject: [PATCH 2228/2653] Bump AMDGPU version to 6.16.7 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 7e7df2e411476..88d1a3dacee49 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.16.6) +AC_INIT(amdgpu-dkms, 6.16.7) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 340bab1bee0375462dc7abd77685cb18fc211a20 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Tue, 30 Sep 2025 10:46:05 +0800 Subject: [PATCH 2229/2653] drm/amd/pm: export a function amdgpu_smu_ras_send_msg to allow send msg directly provide a interface that allows ras client send msg to smu/pmfw directly. Signed-off-by: Yang Wang Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 11 ++++++++++ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 11 ++++++++++ .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 20 +++++++++++++++++++ 3 files changed, 42 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 421b6816444ea..ec22e07957409 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -612,6 +612,17 @@ bool is_support_cclk_dpm(struct amdgpu_device *adev) return true; } +int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg, + uint32_t param, uint32_t *read_arg) +{ + struct smu_context *smu = adev->powerplay.pp_handle; + int ret = -EOPNOTSUPP; + + if (smu->ppt_funcs && smu->ppt_funcs->ras_send_msg) + ret = smu->ppt_funcs->ras_send_msg(smu, msg, param, read_arg); + + return ret; +} static int smu_sys_get_pp_table(void *handle, char **table) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 4c00f6edebaec..fab1ec2b3cc6a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -1553,6 +1553,15 @@ struct pptable_funcs { */ ssize_t (*get_xcp_metrics)(struct smu_context *smu, int xcp_id, void *table); + /** + * @ras_send_msg: Send a message with a parameter from Ras + * &msg: Type of message. + * ¶m: Message parameter. + * &read_arg: SMU response (optional). + */ + int (*ras_send_msg)(struct smu_context *smu, + enum smu_message_type msg, uint32_t param, uint32_t *read_arg); + }; typedef enum { @@ -1825,6 +1834,8 @@ int smu_get_phase_det_param(struct smu_context *smu, int smu_phase_det_enable(struct smu_context *smu, bool enable); void amdgpu_smu_phase_det_debugfs_init(struct amdgpu_device *adev); +int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg, + uint32_t param, uint32_t *readarg); #endif void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 465333bc298d7..7dbd8b099fbb4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -3385,6 +3385,25 @@ static int smu_v13_0_6_reset_vcn(struct smu_context *smu, uint32_t inst_mask) return ret; } +static int smu_v13_0_6_ras_send_msg(struct smu_context *smu, enum smu_message_type msg, uint32_t param, uint32_t *read_arg) +{ + int ret; + + switch (msg) { + case SMU_MSG_QueryValidMcaCount: + case SMU_MSG_QueryValidMcaCeCount: + case SMU_MSG_McaBankDumpDW: + case SMU_MSG_McaBankCeDumpDW: + case SMU_MSG_ClearMcaOnRead: + ret = smu_cmn_send_smc_msg_with_param(smu, msg, param, read_arg); + break; + default: + ret = -EPERM; + } + + return ret; +} + static int smu_v13_0_6_post_init(struct smu_context *smu) { struct smu_dpm_context *smu_dpm = &smu->smu_dpm; @@ -4091,6 +4110,7 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { .reset_sdma = smu_v13_0_6_reset_sdma, .dpm_reset_vcn = smu_v13_0_6_reset_vcn, .post_init = smu_v13_0_6_post_init, + .ras_send_msg = smu_v13_0_6_ras_send_msg, }; void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu) From 17726b3be55eb65605a73adbf0d7ab2ac3e58a8b Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 10 Oct 2025 17:23:33 +0530 Subject: [PATCH 2230/2653] drm/amdgpu: Reserve discovery TMR only if needed For legacy SOCs, discovery binary is sideloaded. Instead of checking for binary blob, use a flag to determine if discovery region needs to be reserved. Signed-off-by: Lijo Lazar Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 10 ++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 22 ++++++++----------- 3 files changed, 19 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 223b5da4f21af..e7d0c146cc788 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -298,10 +298,15 @@ static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, else vram_size <<= 20; + /* + * If in VRAM, discovery TMR is marked for reservation. If it is in system mem, + * then it is not required to be reserved. + */ if (sz_valid) { uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, adev->discovery.size, false); + adev->discovery.reserve_tmr = true; } else { ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); } @@ -418,8 +423,11 @@ static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev) { - if (amdgpu_discovery == 2) + if (amdgpu_discovery == 2) { + /* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */ + adev->discovery.reserve_tmr = true; return "amdgpu/ip_discovery.bin"; + } switch (adev->asic_type) { case CHIP_VEGA10: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h index b1eec3af3c4a8..4ce04486cc319 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h @@ -36,6 +36,7 @@ struct amdgpu_discovery_info { struct ip_discovery_top *ip_top; uint32_t size; uint8_t *bin; + bool reserve_tmr; }; void amdgpu_discovery_fini(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 782d877415b4c..ce0712bbf1123 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2068,18 +2068,14 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; } - if (!adev->gmc.is_app_apu) { - ret = amdgpu_bo_create_kernel_at( - adev, adev->gmc.real_vram_size - reserve_size, - reserve_size, &adev->mman.fw_reserved_memory, NULL); - if (ret) { - dev_err(adev->dev, "alloc tmr failed(%d)!\n", ret); - amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, - NULL, NULL); - return ret; - } - } else { - DRM_DEBUG_DRIVER("backdoor fw loading path for PSP TMR, no reservation needed\n"); + ret = amdgpu_bo_create_kernel_at( + adev, adev->gmc.real_vram_size - reserve_size, reserve_size, + &adev->mman.fw_reserved_memory, NULL); + if (ret) { + dev_err(adev->dev, "alloc tmr failed(%d)!\n", ret); + amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, NULL, + NULL); + return ret; } return 0; @@ -2364,7 +2360,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) * If IP discovery enabled, a block of memory should be * reserved for IP discovey. */ - if (adev->discovery.bin) { + if (adev->discovery.reserve_tmr) { r = amdgpu_ttm_reserve_tmr(adev); if (r) return r; From 8662d4180c4248309df7b617a453331f3c5a40c8 Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Fri, 10 Oct 2025 23:32:40 +0530 Subject: [PATCH 2231/2653] drm/amdgpu: fix bit shift logic BIT_ULL(n) sets nth bit, remove explicit shift and set the position Fixes: e30383fce4cb ("drm/amdgpu: fix shift-out-of-bounds in amdgpu_debugfs_jpeg_sched_mask_set") Signed-off-by: Sathishkumar S Reviewed-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c index e7b4b768f7d21..91678621f1ff7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c @@ -370,7 +370,7 @@ static int amdgpu_debugfs_jpeg_sched_mask_set(void *data, u64 val) for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { ring = &adev->jpeg.inst[i].ring_dec[j]; - if (val & (BIT_ULL(1) << ((i * adev->jpeg.num_jpeg_rings) + j))) + if (val & (BIT_ULL((i * adev->jpeg.num_jpeg_rings) + j))) ring->sched.ready = true; else ring->sched.ready = false; From a2a0300b700644737956508690b8ddbdefa2e758 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Mon, 13 Oct 2025 13:46:12 +0800 Subject: [PATCH 2232/2653] drm/amdgpu: Fix NULL pointer dereference in VRAM logic for APU devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Previously, APU platforms (and other scenarios with uninitialized VRAM managers) triggered a NULL pointer dereference in `ttm_resource_manager_usage()`. The root cause is not that the `struct ttm_resource_manager *man` pointer itself is NULL, but that `man->bdev` (the backing device pointer within the manager) remains uninitialized (NULL) on APUs—since APUs lack dedicated VRAM and do not fully set up VRAM manager structures. When `ttm_resource_manager_usage()` attempts to acquire `man->bdev->lru_lock`, it dereferences the NULL `man->bdev`, leading to a kernel OOPS. 1. **amdgpu_cs.c**: Extend the existing bandwidth control check in `amdgpu_cs_get_threshold_for_moves()` to include a check for `ttm_resource_manager_used()`. If the manager is not used (uninitialized `bdev`), return 0 for migration thresholds immediately—skipping VRAM-specific logic that would trigger the NULL dereference. 2. **amdgpu_kms.c**: Update the `AMDGPU_INFO_VRAM_USAGE` ioctl and memory info reporting to use a conditional: if the manager is used, return the real VRAM usage; otherwise, return 0. This avoids accessing `man->bdev` when it is NULL. 3. **amdgpu_virt.c**: Modify the vf2pf (virtual function to physical function) data write path. Use `ttm_resource_manager_used()` to check validity: if the manager is usable, calculate `fb_usage` from VRAM usage; otherwise, set `fb_usage` to 0 (APUs have no discrete framebuffer to report). This approach is more robust than APU-specific checks because it: - Works for all scenarios where the VRAM manager is uninitialized (not just APUs), - Aligns with TTM's design by using its native helper function, - Preserves correct behavior for discrete GPUs (which have fully initialized `man->bdev` and pass the `ttm_resource_manager_used()` check). v4: use ttm_resource_manager_used(&adev->mman.vram_mgr.manager) instead of checking the adev->gmc.is_app_apu flag (Christian) Reviewed-by: Christian König Suggested-by: Lijo Lazar Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 7 ++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 4 ++-- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 63562a978c6bf..caef2774b6950 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -728,7 +728,7 @@ static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev, */ const s64 us_upper_bound = 200000; - if (!adev->mm_stats.log2_max_MBps) { + if ((!adev->mm_stats.log2_max_MBps) || !ttm_resource_manager_used(&adev->mman.vram_mgr.manager)) { *max_bytes = 0; *max_vis_bytes = 0; return; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 6510d59421cc1..302400368a08d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -776,7 +776,8 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; case AMDGPU_INFO_VRAM_USAGE: - ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); + ui64 = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? + ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) : 0; return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; case AMDGPU_INFO_VIS_VRAM_USAGE: ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); @@ -822,8 +823,8 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) mem.vram.usable_heap_size = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size) - AMDGPU_VM_RESERVED_VRAM; - mem.vram.heap_usage = - ttm_resource_manager_usage(vram_man); + mem.vram.heap_usage = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? + ttm_resource_manager_usage(vram_man) : 0; mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; mem.cpu_accessible_vram.total_heap_size = diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 3328ab63376bb..f96beb96c75cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -598,8 +598,8 @@ static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev) vf2pf_info->driver_cert = 0; vf2pf_info->os_info.all = 0; - vf2pf_info->fb_usage = - ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20; + vf2pf_info->fb_usage = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? + ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20 : 0; vf2pf_info->fb_vis_usage = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20; vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20; From 44c09ede97addc6e059e58eacbd6fb964264674b Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Thu, 9 Oct 2025 10:45:42 -0400 Subject: [PATCH 2233/2653] drm/amdgpu: fix gfx12 mes packet status return check GFX12 MES uses low 32 bits of status return for success (1 or 0) and high bits for debug information if low bits are 0. GFX11 MES doesn't do this so checking full 64-bit status return for 1 or 0 is still valid. Signed-off-by: Jonathan Kim Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index ca6134265b5e1..ddf3c2fbf1f01 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -228,7 +228,12 @@ static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, pipe, x_pkt->header.opcode); r = amdgpu_fence_wait_polling(ring, seq, timeout); - if (r < 1 || !*status_ptr) { + + /* + * status_ptr[31:0] == 0 (fail) or status_ptr[63:0] == 1 (success). + * If status_ptr[31:0] == 0 then status_ptr[63:32] will have debug error information. + */ + if (r < 1 || !(lower_32_bits(*status_ptr))) { if (misc_op_str) dev_err(adev->dev, "MES(%d) failed to respond to msg=%s (%s)\n", From 23a55d107035ae458974cb15b21374b9c6126353 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Thu, 9 Oct 2025 10:48:09 -0400 Subject: [PATCH 2234/2653] drm/amdgpu: fix initialization of doorbell array for detect and hang Initialized doorbells should be set to invalid rather than 0 to prevent driver from over counting hung doorbells since it checks against the invalid value to begin with. Signed-off-by: Jonathan Kim Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 8d03e8c9cc6dd..c698e183bedad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -409,7 +409,7 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, return -EINVAL; /* Clear the doorbell array before detection */ - memset(adev->mes.hung_queue_db_array_cpu_addr, 0, + memset(adev->mes.hung_queue_db_array_cpu_addr, AMDGPU_MES_INVALID_DB_OFFSET, adev->mes.hung_queue_db_array_size * sizeof(u32)); input.queue_type = queue_type; input.detect_only = detect_only; From d7484c76cff9f84d5e895f024f551263dc5eb5ca Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Thu, 9 Oct 2025 11:28:19 -0400 Subject: [PATCH 2235/2653] drm/amdgpu: fix hung reset queue array memory allocation By design the MES will return an array result that is twice the number of hung doorbells it can report. i.e. if up k reported doorbells are supported, then the second half of the array, also of length k, holds the HQD information (type/queue/pipe) where queue 1 corresponds to index 0 and k, queue 2 corresponds to index 1 and k + 1 etc ... The driver will use the HDQ info to target queue/pipe reset for hardware scheduled user compute queues. Signed-off-by: Jonathan Kim Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 7 ++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 1 + drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 8 +++++--- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 8 +++++--- 5 files changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index c698e183bedad..22763b4051466 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -420,12 +420,17 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, dev_err(adev->dev, "failed to detect and reset\n"); } else { *hung_db_num = 0; - for (i = 0; i < adev->mes.hung_queue_db_array_size; i++) { + for (i = 0; i < adev->mes.hung_queue_hqd_info_offset; i++) { if (db_array[i] != AMDGPU_MES_INVALID_DB_OFFSET) { hung_db_array[i] = db_array[i]; *hung_db_num += 1; } } + + /* + * TODO: return HQD info for MES scheduled user compute queue reset cases + * stored in hung_db_array hqd info offset to full array size + */ } return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 49942a1cb8f52..a14bfffcb4cf5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -149,6 +149,7 @@ struct amdgpu_mes { void *resource_1_addr[AMDGPU_MAX_MES_PIPES]; int hung_queue_db_array_size; + int hung_queue_hqd_info_offset; struct amdgpu_bo *hung_queue_db_array_gpu_obj; uint64_t hung_queue_db_array_gpu_addr; void *hung_queue_db_array_cpu_addr; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index 829129ad7bd16..5c63480dda9c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -208,10 +208,10 @@ static int mes_userq_detect_and_reset(struct amdgpu_device *adev, struct amdgpu_userq_mgr *uqm, *tmp; unsigned int hung_db_num = 0; int queue_id, r, i; - u32 db_array[4]; + u32 db_array[8]; - if (db_array_size > 4) { - dev_err(adev->dev, "DB array size (%d vs 4) too small\n", + if (db_array_size > 8) { + dev_err(adev->dev, "DB array size (%d vs 8) too small\n", db_array_size); return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index e82188431f796..da575bb1377f1 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -66,7 +66,8 @@ static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); #define GFX_MES_DRAM_SIZE 0x80000 #define MES11_HW_RESOURCE_1_SIZE (128 * AMDGPU_GPU_PAGE_SIZE) -#define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 4 +#define MES11_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset, [4:7] = hqd info */ +#define MES11_HUNG_HQD_INFO_OFFSET 4 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) { @@ -1720,8 +1721,9 @@ static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; int pipe, r; - adev->mes.hung_queue_db_array_size = - MES11_HUNG_DB_OFFSET_ARRAY_SIZE; + adev->mes.hung_queue_db_array_size = MES11_HUNG_DB_OFFSET_ARRAY_SIZE; + adev->mes.hung_queue_hqd_info_offset = MES11_HUNG_HQD_INFO_OFFSET; + for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) continue; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index ddf3c2fbf1f01..1ecb842b3830b 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -47,7 +47,8 @@ static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev); #define MES_EOP_SIZE 2048 -#define MES12_HUNG_DB_OFFSET_ARRAY_SIZE 4 +#define MES12_HUNG_DB_OFFSET_ARRAY_SIZE 8 /* [0:3] = db offset [4:7] hqd info */ +#define MES12_HUNG_HQD_INFO_OFFSET 4 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring) { @@ -1904,8 +1905,9 @@ static int mes_v12_0_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; int pipe, r; - adev->mes.hung_queue_db_array_size = - MES12_HUNG_DB_OFFSET_ARRAY_SIZE; + adev->mes.hung_queue_db_array_size = MES12_HUNG_DB_OFFSET_ARRAY_SIZE; + adev->mes.hung_queue_hqd_info_offset = MES12_HUNG_HQD_INFO_OFFSET; + for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { r = amdgpu_mes_init_microcode(adev, pipe); if (r) From 00f534b73accc64e22417bef6c81a6f359c2f596 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Thu, 5 Jun 2025 10:18:37 -0400 Subject: [PATCH 2236/2653] drm/amdgpu: enable suspend/resume all for gfx 12 Suspend/resume all gangs has been available for GFX12 for a while now so enable it. Signed-off-by: Jonathan Kim Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 22763b4051466..45bf8309cb375 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -691,14 +691,11 @@ int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe) bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev) { uint32_t mes_rev = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; - bool is_supported = false; - if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && - amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0) && - mes_rev >= 0x63) - is_supported = true; - - return is_supported; + return ((amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && + amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0) && + mes_rev >= 0x63) || + amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)); } /* Fix me -- node_id is used to identify the correct MES instances in the future */ From b03e03739c9f17bcce483fd65d974e20068116d6 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Wed, 18 Jun 2025 10:31:15 -0400 Subject: [PATCH 2237/2653] drm/amdkfd: fix suspend/resume all calls in mes based eviction path Suspend/resume all gangs should be done with the device lock is held. Signed-off-by: Jonathan Kim Acked-by: Alex Deucher Reviewed-by: Harish Kasiviswanathan --- .../drm/amd/amdkfd/kfd_device_queue_manager.c | 73 ++++++------------- 1 file changed, 21 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index b11c1e9c873da..90a60f16d8080 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -1264,6 +1264,15 @@ static int evict_process_queues_cpsch(struct device_queue_manager *dqm, pr_debug_ratelimited("Evicting process pid %d queues\n", pdd->process->lead_thread->pid); + if (dqm->dev->kfd->shared_resources.enable_mes) { + pdd->last_evict_timestamp = get_jiffies_64(); + retval = suspend_all_queues_mes(dqm); + if (retval) { + dev_err(dev, "Suspending all queues failed"); + goto out; + } + } + /* Mark all queues as evicted. Deactivate all active queues on * the qpd. */ @@ -1276,23 +1285,27 @@ static int evict_process_queues_cpsch(struct device_queue_manager *dqm, decrement_queue_count(dqm, qpd, q); if (dqm->dev->kfd->shared_resources.enable_mes) { - int err; - - err = remove_queue_mes(dqm, q, qpd); - if (err) { + retval = remove_queue_mes(dqm, q, qpd); + if (retval) { dev_err(dev, "Failed to evict queue %d\n", q->properties.queue_id); - retval = err; + goto out; } } } - pdd->last_evict_timestamp = get_jiffies_64(); - if (!dqm->dev->kfd->shared_resources.enable_mes) + + if (!dqm->dev->kfd->shared_resources.enable_mes) { + pdd->last_evict_timestamp = get_jiffies_64(); retval = execute_queues_cpsch(dqm, qpd->is_debug ? KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES : KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); + } else { + retval = resume_all_queues_mes(dqm); + if (retval) + dev_err(dev, "Resuming all queues failed"); + } out: dqm_unlock(dqm); @@ -3154,61 +3167,17 @@ int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbel return ret; } -static int kfd_dqm_evict_pasid_mes(struct device_queue_manager *dqm, - struct qcm_process_device *qpd) -{ - struct device *dev = dqm->dev->adev->dev; - int ret = 0; - - /* Check if process is already evicted */ - dqm_lock(dqm); - if (qpd->evicted) { - /* Increment the evicted count to make sure the - * process stays evicted before its terminated. - */ - qpd->evicted++; - dqm_unlock(dqm); - goto out; - } - dqm_unlock(dqm); - - ret = suspend_all_queues_mes(dqm); - if (ret) { - dev_err(dev, "Suspending all queues failed"); - goto out; - } - - ret = dqm->ops.evict_process_queues(dqm, qpd); - if (ret) { - dev_err(dev, "Evicting process queues failed"); - goto out; - } - - ret = resume_all_queues_mes(dqm); - if (ret) - dev_err(dev, "Resuming all queues failed"); - -out: - return ret; -} - int kfd_evict_process_device(struct kfd_process_device *pdd) { struct device_queue_manager *dqm; struct kfd_process *p; - int ret = 0; p = pdd->process; dqm = pdd->dev->dqm; WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); - if (dqm->dev->kfd->shared_resources.enable_mes) - ret = kfd_dqm_evict_pasid_mes(dqm, &pdd->qpd); - else - ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd); - - return ret; + return dqm->ops.evict_process_queues(dqm, &pdd->qpd); } int reserve_debug_trap_vmid(struct device_queue_manager *dqm, From f25186d5143a548064fed175212089065f54ca0c Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Wed, 18 Jun 2025 10:45:55 -0400 Subject: [PATCH 2238/2653] drm/amdgpu: update remove after reset flag for MES remove queue Remove queue after reset flag is required to remove a queue that has been successfully reset to clean up the MES' internal state. Signed-off-by: Jonathan Kim Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 1 + drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 4 ++++ drivers/gpu/drm/amd/include/mes_v11_api_def.h | 3 ++- drivers/gpu/drm/amd/include/mes_v12_api_def.h | 3 ++- 5 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index a14bfffcb4cf5..b0941ef33c9ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -239,6 +239,7 @@ struct mes_add_queue_input { struct mes_remove_queue_input { uint32_t doorbell_offset; uint64_t gang_context_addr; + bool remove_queue_after_reset; }; struct mes_map_legacy_queue_input { diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index da575bb1377f1..3a52754b5cadb 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -369,6 +369,7 @@ static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, struct mes_remove_queue_input *input) { union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; + uint32_t mes_rev = mes->sched_version & AMDGPU_MES_VERSION_MASK; memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); @@ -379,6 +380,9 @@ static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; + if (mes_rev >= 0x60) + mes_remove_queue_pkt.remove_queue_after_reset = input->remove_queue_after_reset; + return mes_v11_0_submit_pkt_and_poll_completion(mes, &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), offsetof(union MESAPI__REMOVE_QUEUE, api_status)); diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index 1ecb842b3830b..01725cbb93667 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -361,6 +361,7 @@ static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes, struct mes_remove_queue_input *input) { union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; + uint32_t mes_rev = mes->sched_version & AMDGPU_MES_VERSION_MASK; memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); @@ -371,6 +372,9 @@ static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes, mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; + if (mes_rev >= 0x5a) + mes_remove_queue_pkt.remove_queue_after_reset = input->remove_queue_after_reset; + return mes_v12_0_submit_pkt_and_poll_completion(mes, AMDGPU_MES_SCHED_PIPE, &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), diff --git a/drivers/gpu/drm/amd/include/mes_v11_api_def.h b/drivers/gpu/drm/amd/include/mes_v11_api_def.h index ab1cfc92dbeb1..f9629d42ada27 100644 --- a/drivers/gpu/drm/amd/include/mes_v11_api_def.h +++ b/drivers/gpu/drm/amd/include/mes_v11_api_def.h @@ -345,7 +345,8 @@ union MESAPI__REMOVE_QUEUE { uint32_t unmap_kiq_utility_queue : 1; uint32_t preempt_legacy_gfx_queue : 1; uint32_t unmap_legacy_queue : 1; - uint32_t reserved : 28; + uint32_t remove_queue_after_reset : 1; + uint32_t reserved : 27; }; struct MES_API_STATUS api_status; diff --git a/drivers/gpu/drm/amd/include/mes_v12_api_def.h b/drivers/gpu/drm/amd/include/mes_v12_api_def.h index 69611c7e30e35..2f12cba4eb662 100644 --- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h +++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h @@ -399,7 +399,8 @@ union MESAPI__REMOVE_QUEUE { uint32_t unmap_kiq_utility_queue : 1; uint32_t preempt_legacy_gfx_queue : 1; uint32_t unmap_legacy_queue : 1; - uint32_t reserved : 28; + uint32_t remove_queue_after_reset : 1; + uint32_t reserved : 27; }; struct MES_API_STATUS api_status; From 760825364318f574ac75607904ac3c9448f19c21 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 10 Oct 2025 16:40:57 -0400 Subject: [PATCH 2239/2653] drm/amdgpu: drop unused structures in amdgpu_drm.h These were never used and are duplicated with the interface that is used. Maybe leftovers from a previous revision of the patch that added them. Fixes: 90c448fef312 ("drm/amdgpu: add new AMDGPU_INFO subquery for userq objects") Reviewed-by: Prike Liang Signed-off-by: Alex Deucher --- include/uapi/drm/amdgpu_drm.h | 21 --------------------- 1 file changed, 21 deletions(-) diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index bf67fe9e6a427..ac7dd9dd365e5 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -1633,27 +1633,6 @@ struct drm_amdgpu_info_hw_ip { __u32 userq_num_slots; }; -/* GFX metadata BO sizes and alignment info (in bytes) */ -struct drm_amdgpu_info_uq_fw_areas_gfx { - /* shadow area size */ - __u32 shadow_size; - /* shadow area base virtual mem alignment */ - __u32 shadow_alignment; - /* context save area size */ - __u32 csa_size; - /* context save area base virtual mem alignment */ - __u32 csa_alignment; -}; - -/* IP specific fw related information used in the - * subquery AMDGPU_INFO_UQ_FW_AREAS - */ -struct drm_amdgpu_info_uq_fw_areas { - union { - struct drm_amdgpu_info_uq_fw_areas_gfx gfx; - }; -}; - struct drm_amdgpu_info_num_handles { /** Max handles as supported by firmware for UVD */ __u32 uvd_max_handles; From 8facf72f90b5255de16e4da9f0a1e3f416c538dc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 13 Oct 2025 08:06:42 +0200 Subject: [PATCH 2240/2653] drm/amd/powerplay: Fix CIK shutdown temperature MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove extra multiplication. CIK GPUs such as Hawaii appear to use PP_TABLE_V0 in which case the shutdown temperature is hardcoded in smu7_init_dpm_defaults and is already multiplied by 1000. The value was mistakenly multiplied another time by smu7_get_thermal_temperature_range. Fixes: 4ba082572a42 ("drm/amd/powerplay: export the thermal ranges of VI asics (V2)") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/1676 Reviewed-by: Alex Deucher Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c index 8da882c518565..9b28c07282699 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c @@ -5444,8 +5444,7 @@ static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, thermal_data->max = table_info->cac_dtp_table->usSoftwareShutdownTemp * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; else if (hwmgr->pp_table_version == PP_TABLE_V0) - thermal_data->max = data->thermal_temp_setting.temperature_shutdown * - PP_TEMPERATURE_UNITS_PER_CENTIGRADES; + thermal_data->max = data->thermal_temp_setting.temperature_shutdown; thermal_data->sw_ctf_threshold = thermal_data->max; From ded40716be03a6d94f13049520d4bde6b783e977 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 9 Oct 2025 15:59:07 -0500 Subject: [PATCH 2241/2653] drm/amd: Drop calls to restore power limit and clock from smu_resume() User requested power limits and clock settings are already restored as part of smu_restore_dpm_user_profile(). It's unnecessary to call the same restore as part of smu_resume(). Revert the following commits to drop that extra restore: commit ed4efe426a49 ("drm/amd: Restore cached power limit during resume") commit 796ff8a7e01b ("drm/amd: Restore cached manual clock settings during resume") commit f9b80514a722 ("drm/amd: Only restore cached manual clock settings in restore if OD enabled") Suggested-by: Lijo Lazar Reviewed-by: Lijo Lazar Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index ec22e07957409..9af0d8e1f79ed 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2239,7 +2239,6 @@ static int smu_resume(struct amdgpu_ip_block *ip_block) int ret; struct amdgpu_device *adev = ip_block->adev; struct smu_context *smu = adev->powerplay.pp_handle; - struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); if (amdgpu_sriov_multi_vf_mode(adev)) return 0; @@ -2271,18 +2270,6 @@ static int smu_resume(struct amdgpu_ip_block *ip_block) adev->pm.dpm_enabled = true; - if (smu->current_power_limit) { - ret = smu_set_power_limit(smu, SMU_DEFAULT_PPT_LIMIT, smu->current_power_limit); - if (ret && ret != -EOPNOTSUPP) - return ret; - } - - if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL && smu->od_enabled) { - ret = smu_od_edit_dpm_table(smu, PP_OD_COMMIT_DPM_TABLE, NULL, 0); - if (ret) - return ret; - } - dev_info(adev->dev, "SMU is resumed successfully!\n"); return 0; From 5e0ed4b28541faa91f3f3cc3732fb83f13350001 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Fri, 10 Oct 2025 18:09:57 +0530 Subject: [PATCH 2242/2653] drm/amdgpu: update the functions to use amdgpu version of hmm MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit At times we need a bo reference for hmm and for that add a new struct amdgpu_hmm_range which will hold an optional bo member and hmm_range. Use amdgpu_hmm_range instead of hmm_range and let the bo as an optional argument for the caller if they want to the bo reference to be taken or they want to handle that explicitly. Signed-off-by: Sunil Khatri Reviewed-by: Christian König Change-Id: If2c9e000f933062e5949ca24c267a604d4092648 --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 6 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 33 ++++++++++++------- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 18 ++++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 7 ++-- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 1 - drivers/gpu/drm/amd/amdkfd/kfd_migrate.h | 1 - drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 14 ++++---- drivers/gpu/drm/amd/amdkfd/kfd_svm.h | 1 - 13 files changed, 56 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index bcdafcf91c272..40c46e6c88988 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -73,7 +73,7 @@ struct kgd_mem { struct kfd_ipc_obj *ipc_obj; struct dma_buf *dmabuf; #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - struct hmm_range *range; + struct amdgpu_hmm_range *range; #else struct page **user_pages; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 568a8573da99a..9a83c18812c90 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1120,7 +1120,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, struct amdkfd_process_info *process_info = mem->process_info; struct amdgpu_bo *bo = mem->bo; struct ttm_operation_ctx ctx = { true, false }; - struct hmm_range *range; + struct amdgpu_hmm_range *range; int ret = 0; mutex_lock(&process_info->lock); @@ -1153,7 +1153,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, } #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - range = amdgpu_hmm_range_alloc(); + range = amdgpu_hmm_range_alloc(NULL); if (unlikely(!range)) { ret = -ENOMEM; goto unregister_out; @@ -2950,7 +2950,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, } #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - mem->range = amdgpu_hmm_range_alloc(); + mem->range = amdgpu_hmm_range_alloc(NULL); if (unlikely(!mem->range)) return -ENOMEM; /* Get updated user pages */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h index e3f75a65fcb6b..43862a8082110 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h @@ -39,7 +39,7 @@ struct amdgpu_bo_list_entry { struct amdgpu_bo *bo; struct amdgpu_bo_va *bo_va; uint32_t priority; - struct hmm_range *range; + struct amdgpu_hmm_range *range; #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool user_invalidated; #else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index caef2774b6950..63482f7397caa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include @@ -916,7 +915,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, bool userpage_invalidated = false; struct amdgpu_bo *bo = e->bo; - e->range = amdgpu_hmm_range_alloc(); + e->range = amdgpu_hmm_range_alloc(NULL); if (unlikely(!e->range)) return -ENOMEM; @@ -925,7 +924,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto out_free_user_pages; for (i = 0; i < bo->tbo.ttm->num_pages; i++) { - if (bo->tbo.ttm->pages[i] != hmm_pfn_to_page(e->range->hmm_pfns[i])) { + if (bo->tbo.ttm->pages[i] != + hmm_pfn_to_page(e->range->hmm_range.hmm_pfns[i])) { userpage_invalidated = true; break; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 478184576f0ce..018ca29fc8cd7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -602,7 +602,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_amdgpu_gem_userptr *args = data; struct amdgpu_fpriv *fpriv = filp->driver_priv; struct drm_gem_object *gobj; - struct hmm_range *range; + struct amdgpu_hmm_range *range; struct amdgpu_bo *bo; uint32_t handle; int r; @@ -644,7 +644,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - range = amdgpu_hmm_range_alloc(); + range = amdgpu_hmm_range_alloc(NULL); if (unlikely(!range)) return -ENOMEM; r = amdgpu_ttm_tt_get_user_pages(bo, range); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 55b2359799ae4..e4a1858609991 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -843,12 +843,13 @@ const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, void *owner, - struct hmm_range *hmm_range) + struct amdgpu_hmm_range *range) { unsigned long end; unsigned long timeout; unsigned long *pfns; int r = 0; + struct hmm_range *hmm_range = &range->hmm_range; pfns = kvmalloc_array(npages, sizeof(*pfns), GFP_KERNEL); if (unlikely(!pfns)) { @@ -919,30 +920,38 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, return r; } -bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range) +bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range) { - if (!hmm_range) + if (!range) return false; - return !mmu_interval_read_retry(hmm_range->notifier, - hmm_range->notifier_seq); + return !mmu_interval_read_retry(range->hmm_range.notifier, + range->hmm_range.notifier_seq); } -struct hmm_range *amdgpu_hmm_range_alloc(void) +struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo) { - return kzalloc(sizeof(struct hmm_range), GFP_KERNEL); + struct amdgpu_hmm_range *range; + + range = kzalloc(sizeof(*range), GFP_KERNEL); + if (!range) + return NULL; + + range->bo = amdgpu_bo_ref(bo); + return range; } -void amdgpu_hmm_range_free(struct hmm_range *hmm_range) +void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range) { - if (!hmm_range) + if (!range) return; #ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT - kvfree(hmm_range->pfns); + kvfree(range->hmm_range.pfns); #else - kvfree(hmm_range->hmm_pfns); + kvfree(range->hmm_range.hmm_pfns); #endif - kfree(hmm_range); + amdgpu_bo_unref(&range->bo); + kfree(range); } #endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index 4ec014a918514..e73a6809e0d6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -82,16 +82,20 @@ static inline struct page *hmm_pfn_to_page(unsigned long hmm_pfn) return hmm_device_entry_to_page(&hmm_range, hmm_pfn); } #endif +struct amdgpu_hmm_range { + struct hmm_range hmm_range; + struct amdgpu_bo *bo; +}; int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, void *owner, - struct hmm_range *hmm_range); + struct amdgpu_hmm_range *range); #if defined(CONFIG_HMM_MIRROR) -bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range); -struct hmm_range *amdgpu_hmm_range_alloc(void); -void amdgpu_hmm_range_free(struct hmm_range *hmm_range); +bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range); +struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo); +void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range); int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr); void amdgpu_hmm_unregister(struct amdgpu_bo *bo); #else @@ -104,17 +108,17 @@ static inline int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) static inline void amdgpu_hmm_unregister(struct amdgpu_bo *bo) {} -static inline bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range) +static inline bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range) { return false; } -static inline struct hmm_range *amdgpu_hmm_range_alloc(void) +static inline struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo) { return NULL; } -static inline void amdgpu_hmm_range_free(struct hmm_range *hmm_range) {} +static inline void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range) {} #endif #endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index ce0712bbf1123..1c368a1840425 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -782,7 +782,7 @@ struct amdgpu_ttm_tt { * that range is a valid memory and it is freed too. */ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, - struct hmm_range *range) + struct amdgpu_hmm_range *range) { struct ttm_tt *ttm = bo->tbo.ttm; struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); @@ -917,12 +917,12 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, * that backs user memory and will ultimately be mapped into the device * address space. */ -void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct hmm_range *range) +void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range) { unsigned long i; for (i = 0; i < ttm->num_pages; ++i) - ttm->pages[i] = range ? hmm_pfn_to_page(range->hmm_pfns[i]) : NULL; + ttm->pages[i] = range ? hmm_pfn_to_page(range->hmm_range.hmm_pfns[i]) : NULL; } #else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 848568bb83d86..92c381eeb6d92 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -28,6 +28,7 @@ #include #include #include "amdgpu_vram_mgr.h" +#include "amdgpu_hmm.h" #define AMDGPU_PL_GDS (TTM_PL_PRIV + 0) #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1) @@ -203,7 +204,7 @@ uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, - struct hmm_range *range); + struct amdgpu_hmm_range *range); #else int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, struct hmm_range **range); @@ -211,7 +212,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, #else #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, - struct hmm_range *range) + struct amdgpu_hmm_range *range) { return -EPERM; } @@ -225,7 +226,7 @@ static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page #endif #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED -void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct hmm_range *range); +void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range); #else void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages); #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index d0bb8ecf3045e..ddc42699dd3cc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -21,7 +21,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h index 2eebf67f9c2ce..2b7fd442d29c6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h @@ -31,7 +31,6 @@ #include #include #include -#include #include "kfd_priv.h" #include "kfd_svm.h" diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 5639a51212e05..5fe318b27a5f4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1702,7 +1702,7 @@ static int svm_range_validate_and_map(struct mm_struct *mm, start = map_start << PAGE_SHIFT; end = (map_last + 1) << PAGE_SHIFT; for (addr = start; !r && addr < end; ) { - struct hmm_range *hmm_range = NULL; + struct amdgpu_hmm_range *range = NULL; unsigned long map_start_vma; unsigned long map_last_vma; struct vm_area_struct *vma; @@ -1741,13 +1741,13 @@ static int svm_range_validate_and_map(struct mm_struct *mm, } WRITE_ONCE(p->svms.faulting_task, current); - hmm_range = amdgpu_hmm_range_alloc(); + range = amdgpu_hmm_range_alloc(NULL); r = amdgpu_hmm_range_get_pages(&prange->notifier, addr, npages, readonly, owner, - hmm_range); + range); WRITE_ONCE(p->svms.faulting_task, NULL); if (r) { - amdgpu_hmm_range_free(hmm_range); + amdgpu_hmm_range_free(range); pr_debug("failed %d to get svm range pages\n", r); } } else { @@ -1757,7 +1757,7 @@ static int svm_range_validate_and_map(struct mm_struct *mm, if (!r) { offset = (addr >> PAGE_SHIFT) - prange->start; r = svm_range_dma_map(prange, ctx->bitmap, offset, npages, - hmm_range->hmm_pfns); + range->hmm_range.hmm_pfns); if (r) pr_debug("failed %d to dma map range\n", r); } @@ -1768,12 +1768,12 @@ static int svm_range_validate_and_map(struct mm_struct *mm, * Overrride return value to TRY AGAIN only if prior returns * were successful */ - if (hmm_range && !amdgpu_hmm_range_valid(hmm_range) && !r) { + if (range && !amdgpu_hmm_range_valid(range) && !r) { pr_debug("hmm update the range, need validate again\n"); r = -EAGAIN; } /* Free the hmm range */ - amdgpu_hmm_range_free(hmm_range); + amdgpu_hmm_range_free(range); if (!r && !list_empty(&prange->child_list)) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h index 01c7a48779044..a63dfc95b602b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h @@ -31,7 +31,6 @@ #include #include #include -#include #include "amdgpu.h" #include "kfd_priv.h" From 4f985b04fac98db812725ca729c096b5261735f1 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 14 Oct 2025 10:17:44 +0800 Subject: [PATCH 2243/2653] drm/amdkcl: update the functions to use amdgpu version of hmm on non-upstream code It's caused by the commit: 5e0ed4b "drm/amdgpu: update the functions to use amdgpu version of hmm" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 6 ++---- 5 files changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 9a83c18812c90..9096ad37613dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1183,7 +1183,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, goto unregister_out; } - ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages, NULL); + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); if (ret) { pr_err("%s: Failed to get user pages: %d\n", __func__, ret); goto free_out; @@ -3006,7 +3006,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, } /* Get updated user pages */ - ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages, NULL); + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); if (ret) { mem->user_pages[0] = NULL; pr_debug("%s: Failed to get user pages: %d\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 63482f7397caa..b75d56d6de338 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1059,7 +1059,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto error_free_pages; } - r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages, NULL); + r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages); if (r) { DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); kvfree(e->user_pages); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 018ca29fc8cd7..bbe0ee582a618 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -649,8 +649,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, return -ENOMEM; r = amdgpu_ttm_tt_get_user_pages(bo, range); #else - r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, - &range); + r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages); #endif if (r) { #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 1c368a1840425..ab6cf41201049 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -835,8 +835,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, * This provides a wrapper around the get_user_pages() call to provide * device accessible pages that back user memory. */ -int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, - struct hmm_range **range) +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) { struct ttm_tt *ttm = bo->tbo.ttm; struct amdgpu_ttm_tt *gtt = (void *)ttm; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 92c381eeb6d92..c46943daaee02 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -206,8 +206,7 @@ uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct amdgpu_hmm_range *range); #else -int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, - struct hmm_range **range); +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages); #endif #else #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED @@ -217,8 +216,7 @@ static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, return -EPERM; } #else -static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, - struct hmm_range **range) +static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) { return -EPERM; } From 72c344647733b8cabdd4e0aa5e5411b33bdc271a Mon Sep 17 00:00:00 2001 From: Harry VanZyllDeJong Date: Wed, 17 Sep 2025 16:46:13 -0400 Subject: [PATCH 2244/2653] drm/amd/display: fix duplicate aux command with AMD aux backlight when using AMD aux backlight control, we avoid sending backlight update commands to DMUB firmware because it is controlled by aux commands in driver. Reviewed-by: Iswara Nagulendran Reviewed-by: Aric Cyr Signed-off-by: Harry VanZyllDeJong Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index 7b85a2b9fefa9..e446385e30bf2 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -709,7 +709,8 @@ bool dcn31_set_backlight_level(struct pipe_ctx *pipe_ctx, panel_cntl->inst, panel_cntl->pwrseq_inst); - dmub_abm_set_backlight(dc, backlight_level_params, panel_cntl->inst); + if (backlight_level_params->control_type != BACKLIGHT_CONTROL_AMD_AUX) + dmub_abm_set_backlight(dc, backlight_level_params, panel_cntl->inst); return true; } From dbd7a681c37c87c447f134b636da0daf67133b10 Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Thu, 25 Sep 2025 15:01:23 -0400 Subject: [PATCH 2245/2653] drm/amd/display: Add debug option to override EASF scaler taps [Why & How] Add new option override_easf to use in_taps instead of internal taps policy for debugging Reviewed-by: Alvin Lee Signed-off-by: Samson Tam Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/dc/dc_spl_translate.c | 2 ++ drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c | 15 +++++++++++++++ .../gpu/drm/amd/display/dc/sspl/dc_spl_types.h | 1 + 3 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c index 55704d4457ef1..37d1a79e8241e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c @@ -147,6 +147,8 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl spl_in->prefer_easf = false; else if (pipe_ctx->stream->ctx->dc->debug.force_easf == 2) spl_in->disable_easf = true; + else if (pipe_ctx->stream->ctx->dc->debug.force_easf == 3) + spl_in->override_easf = true; /* Translate adaptive sharpening preference */ unsigned int sharpness_setting = pipe_ctx->stream->ctx->dc->debug.force_sharpness; unsigned int force_sharpness_level = pipe_ctx->stream->ctx->dc->debug.force_sharpness_level; diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c index b1fb0f8a253a5..7a839984dbc00 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c @@ -1018,6 +1018,21 @@ static bool spl_get_optimal_number_of_taps( spl_scratch->scl_data.taps.h_taps_c = 6; spl_scratch->scl_data.taps.v_taps_c = 6; } + + /* Override mode: keep EASF enabled but use input taps if valid */ + if (spl_in->override_easf) { + spl_scratch->scl_data.taps.h_taps = (in_taps->h_taps != 0) ? in_taps->h_taps : spl_scratch->scl_data.taps.h_taps; + spl_scratch->scl_data.taps.v_taps = (in_taps->v_taps != 0) ? in_taps->v_taps : spl_scratch->scl_data.taps.v_taps; + spl_scratch->scl_data.taps.h_taps_c = (in_taps->h_taps_c != 0) ? in_taps->h_taps_c : spl_scratch->scl_data.taps.h_taps_c; + spl_scratch->scl_data.taps.v_taps_c = (in_taps->v_taps_c != 0) ? in_taps->v_taps_c : spl_scratch->scl_data.taps.v_taps_c; + + if ((spl_scratch->scl_data.taps.h_taps > 6) || (spl_scratch->scl_data.taps.v_taps > 6)) + skip_easf = true; + if ((spl_scratch->scl_data.taps.h_taps > 1) && (spl_scratch->scl_data.taps.h_taps % 2)) + spl_scratch->scl_data.taps.h_taps--; + if ((spl_scratch->scl_data.taps.h_taps_c > 1) && (spl_scratch->scl_data.taps.h_taps_c % 2)) + spl_scratch->scl_data.taps.h_taps_c--; + } } /*Ensure we can support the requested number of vtaps*/ diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_types.h b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_types.h index 23d254dea18f2..20e4e52a77ac7 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_types.h +++ b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_types.h @@ -545,6 +545,7 @@ struct spl_in { enum linear_light_scaling lls_pref; // Linear Light Scaling bool prefer_easf; bool disable_easf; + bool override_easf; /* If true, keep EASF enabled but use provided in_taps */ struct spl_debug debug; bool is_fullscreen; bool is_hdr_on; From 05d61aea2fc9971cdfbff6f15517b3536805561a Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Fri, 26 Sep 2025 15:51:15 -0400 Subject: [PATCH 2246/2653] drm/amd/display: add dispclk ramping to dcn35. [why] this is a required logic based on HW programming guide. tested/ported on dcn401. Reviewed-by: Yihan Zhu Signed-off-by: Charlene Liu Signed-off-by: Aurabindo Pillai --- .../gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index c899c09ea31b8..e097d52956b60 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -1114,6 +1114,16 @@ static void dccg35_trigger_dio_fifo_resync(struct dccg *dccg) if (dispclk_rdivider_value != 0) REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value); } +static void dccg35_wait_for_dentist_change_done( + struct dccg *dccg) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + uint32_t dentist_dispclk_value = REG_READ(DENTIST_DISPCLK_CNTL); + + REG_WRITE(DENTIST_DISPCLK_CNTL, dentist_dispclk_value); + REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000); +} static void dcn35_set_dppclk_enable(struct dccg *dccg, uint32_t dpp_inst, uint32_t enable) @@ -1300,6 +1310,8 @@ static void dccg35_set_pixel_rate_div( BREAK_TO_DEBUGGER(); return; } + if (otg_inst < 4) + dccg35_wait_for_dentist_change_done(dccg); } static void dccg35_set_dtbclk_p_src( From 1b4df5d0d8e735da7e1dd6c8c45523cfd1d6e649 Mon Sep 17 00:00:00 2001 From: Meenakshikumar Somasundaram Date: Mon, 29 Sep 2025 14:28:34 -0400 Subject: [PATCH 2247/2653] drm/amd/display: Fix NULL pointer dereference [Why] On a mst branch with multi display setup, dc context is obselete after updating the first stream. Referencing the same dc context for the next stream update to fetch dc pointer leads to NULL pointer dereference. [How] Get the dc pointer from the link rather than context. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Charlene Liu Signed-off-by: Meenakshikumar Somasundaram Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c index 1593412354cf8..1045c268672e2 100644 --- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c +++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c @@ -78,6 +78,7 @@ static void dp_retrain_link_dp_test(struct dc_link *link, struct audio_output audio_output[MAX_PIPES]; struct dc_stream_state *streams_on_link[MAX_PIPES]; int num_streams_on_link = 0; + struct dc *dc = (struct dc *)link->dc; needs_divider_update = (link->dc->link_srv->dp_get_encoding_format(link_setting) != link->dc->link_srv->dp_get_encoding_format((const struct dc_link_settings *) &link->cur_link_settings)); @@ -150,7 +151,7 @@ static void dp_retrain_link_dp_test(struct dc_link *link, if (streams_on_link[i] && streams_on_link[i]->link && streams_on_link[i]->link == link) { stream_update.stream = streams_on_link[i]; stream_update.dpms_off = &dpms_off; - dc_update_planes_and_stream(state->clk_mgr->ctx->dc, NULL, 0, streams_on_link[i], &stream_update); + dc_update_planes_and_stream(dc, NULL, 0, streams_on_link[i], &stream_update); } } } From 4ae945048407e7bb7904b1d15bb089ca2c112c54 Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Mon, 29 Sep 2025 14:47:51 -0400 Subject: [PATCH 2248/2653] drm/amd/display: Remove unused field in DML Remove unused fields. Reviewed-by: Austin Zheng Signed-off-by: Alvin Lee Signed-off-by: Aurabindo Pillai --- .../drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h index 91955bbe24b86..8e5a30287220f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h @@ -46,7 +46,6 @@ struct dml2_display_dlg_regs { uint32_t dst_y_delta_drq_limit; uint32_t refcyc_per_vm_dmdata; uint32_t dmdata_dl_delta; - uint32_t dst_y_svp_drq_limit; // MRQ uint32_t refcyc_per_meta_chunk_vblank_l; From 3461a0960ae43553a750366c94a408d560dcfcf1 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Mon, 29 Sep 2025 15:15:13 -0400 Subject: [PATCH 2249/2653] drm/amd/display: add dccg dfs mask def [why] add some register masks for DCCG Reviewed-by: Yihan Zhu Reviewed-by: Alvin Lee Signed-off-by: Charlene Liu Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h index 51f98c5c51c41..ad7a5850d31b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h @@ -231,6 +231,14 @@ DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\ DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\ DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\ struct dccg *dccg35_create( struct dc_context *ctx, From c3f70af44d10bd889b17bdbd3ee4f3caaf80ed76 Mon Sep 17 00:00:00 2001 From: Adi Gollamudi Date: Sun, 12 Oct 2025 12:13:19 -0700 Subject: [PATCH 2250/2653] drm/amd/display: fix typo in display_mode_core_structs.h Fix a typo in a comment, change "enviroment" to "environment" in drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h Signed-off-by: Aditya Gollamudi Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h index dbeb084660922..d57717b023ebf 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h @@ -1894,7 +1894,7 @@ struct display_mode_lib_scratch_st { struct CalculatePrefetchSchedule_params_st CalculatePrefetchSchedule_params; }; -/// @brief Represent the overall soc/ip enviroment. It contains data structure represent the soc/ip characteristic and also structures that hold calculation output +/// @brief Represent the overall soc/ip environment. It contains data structure represent the soc/ip characteristic and also structures that hold calculation output struct display_mode_lib_st { dml_uint_t project; From 68344883494b2ba3d59b40aa635941f7ffd15080 Mon Sep 17 00:00:00 2001 From: Relja Vojvodic Date: Wed, 24 Sep 2025 09:33:35 -0400 Subject: [PATCH 2251/2653] drm/amd/display: Rework HDMI data channel reads Fix the HDMI data channel reads to respect scdc_present field to pass compliance test. Reviewed-by: Wenjing Liu Signed-off-by: Relja Vojvodic Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/dc/dc_types.h | 1 + drivers/gpu/drm/amd/display/dc/link/link_detection.c | 4 ++++ drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c | 3 ++- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index b5aa03a3e39cf..8f8ccde7ad94e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -212,6 +212,7 @@ struct dc_edid_caps { bool edid_hdmi; bool hdr_supported; bool rr_capable; + bool scdc_present; struct dc_panel_patch panel_patch; }; diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index 85303167a5531..82a9e52d5ae5f 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -270,6 +270,10 @@ static void read_scdc_caps(struct ddc_service *ddc_service, uint8_t slave_address = HDMI_SCDC_ADDRESS; uint8_t offset = HDMI_SCDC_MANUFACTURER_OUI; + if (ddc_service->link->local_sink && + !ddc_service->link->local_sink->edid_caps.scdc_present) + return; + link_query_ddc_data(ddc_service, slave_address, &offset, sizeof(offset), sink->scdc_caps.manufacturer_OUI.byte, sizeof(sink->scdc_caps.manufacturer_OUI.byte)); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c index 267180e7bc48f..5d2bcce2f669d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c @@ -549,7 +549,8 @@ void write_scdc_data(struct ddc_service *ddc_service, /*Lower than 340 Scramble bit from SCDC caps*/ if (ddc_service->link->local_sink && - ddc_service->link->local_sink->edid_caps.panel_patch.skip_scdc_overwrite) + (ddc_service->link->local_sink->edid_caps.panel_patch.skip_scdc_overwrite || + !ddc_service->link->local_sink->edid_caps.scdc_present)) return; link_query_ddc_data(ddc_service, slave_address, &offset, From 6988e189dec0eef0bb555597bd49bd7925acece7 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Mon, 29 Sep 2025 20:29:30 -0400 Subject: [PATCH 2252/2653] drm/amd/display: increase max link count and fix link->enc NULL pointer access [why] 1.) dc->links[MAX_LINKS] array size smaller than actual requested. max_connector + max_dpia + 4 virtual = 14. increase from 12 to 14. 2.) hw_init() access null LINK_ENC for dpia non display_endpoint. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Meenakshikumar Somasundaram Reviewed-by: Chris Park Signed-off-by: Charlene Liu Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 3 +++ drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 8 +++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 71c2cfa4df755..2b49b83273742 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -200,6 +200,9 @@ void dcn401_init_hw(struct dc *dc) */ struct dc_link *link = dc->links[i]; + if (link->ep_type != DISPLAY_ENDPOINT_PHY) + continue; + link->link_enc->funcs->hw_init(link->link_enc); /* Check for enabled DIG to identify enabled display */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index 41c76ba9ba569..62a39204fe0b7 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -44,7 +44,13 @@ */ #define MAX_PIPES 6 #define MAX_PHANTOM_PIPES (MAX_PIPES / 2) -#define MAX_LINKS (MAX_PIPES * 2 +2) + +#define MAX_DPIA 6 +#define MAX_CONNECTOR 6 +#define MAX_VIRTUAL_LINKS 4 + +#define MAX_LINKS (MAX_DPIA + MAX_CONNECTOR + MAX_VIRTUAL_LINKS) + #define MAX_DIG_LINK_ENCODERS 7 #define MAX_DWB_PIPES 1 #define MAX_HPO_DP2_ENCODERS 4 From 14f78b2c6a28fe6506a4bdba70a83f2eaa96d15d Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Tue, 30 Sep 2025 17:28:54 -0400 Subject: [PATCH 2253/2653] drm/amd/display: Update DCN401 path for cursor offload [Description] The DCN401 cursor offload path needs to take into account use_mall_for_cursor, and also need to ensure the dcn32 function assigns the cursor cache fields (DCN401 uses the dcn32 implementation). Reviewed-by: Nicholas Kazlauskas Signed-off-by: Alvin Lee Signed-off-by: Aurabindo Pillai --- .../amd/display/dc/hubp/dcn32/dcn32_hubp.c | 70 ++++++++++++------- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 1 + drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 1 + 3 files changed, 45 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c index a5f23bb2a76a1..41c8f78efdc34 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c @@ -118,29 +118,7 @@ void hubp32_cursor_set_attributes( uint32_t cursor_width = ((attr->width + 63) / 64) * 64; uint32_t cursor_height = attr->height; uint32_t cursor_size = cursor_width * cursor_height; - - hubp->curs_attr = *attr; - - REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, - CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); - REG_UPDATE(CURSOR_SURFACE_ADDRESS, - CURSOR_SURFACE_ADDRESS, attr->address.low_part); - - REG_UPDATE_2(CURSOR_SIZE, - CURSOR_WIDTH, attr->width, - CURSOR_HEIGHT, attr->height); - - REG_UPDATE_4(CURSOR_CONTROL, - CURSOR_MODE, attr->color_format, - CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION, - CURSOR_PITCH, hw_pitch, - CURSOR_LINES_PER_CHUNK, lpc); - - REG_SET_2(CURSOR_SETTINGS, 0, - /* no shift of the cursor HDL schedule */ - CURSOR0_DST_Y_OFFSET, 0, - /* used to shift the cursor chunk request deadline */ - CURSOR0_CHUNK_HDL_ADJUST, 3); + bool use_mall_for_cursor; switch (attr->color_format) { case CURSOR_MODE_MONO: @@ -158,11 +136,49 @@ void hubp32_cursor_set_attributes( cursor_size *= 8; break; } + use_mall_for_cursor = cursor_size > 16384 ? 1 : 0; + + hubp->curs_attr = *attr; - if (cursor_size > 16384) - REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, true); - else - REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, false); + if (!hubp->cursor_offload) { + REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, + CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); + REG_UPDATE(CURSOR_SURFACE_ADDRESS, + CURSOR_SURFACE_ADDRESS, attr->address.low_part); + + REG_UPDATE_2(CURSOR_SIZE, + CURSOR_WIDTH, attr->width, + CURSOR_HEIGHT, attr->height); + + REG_UPDATE_4(CURSOR_CONTROL, + CURSOR_MODE, attr->color_format, + CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION, + CURSOR_PITCH, hw_pitch, + CURSOR_LINES_PER_CHUNK, lpc); + + REG_SET_2(CURSOR_SETTINGS, 0, + /* no shift of the cursor HDL schedule */ + CURSOR0_DST_Y_OFFSET, 0, + /* used to shift the cursor chunk request deadline */ + CURSOR0_CHUNK_HDL_ADJUST, 3); + + REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, use_mall_for_cursor); + } + hubp->att.SURFACE_ADDR_HIGH = attr->address.high_part; + hubp->att.SURFACE_ADDR = attr->address.low_part; + hubp->att.size.bits.width = attr->width; + hubp->att.size.bits.height = attr->height; + hubp->att.cur_ctl.bits.mode = attr->color_format; + + hubp->cur_rect.w = attr->width; + hubp->cur_rect.h = attr->height; + + hubp->att.cur_ctl.bits.pitch = hw_pitch; + hubp->att.cur_ctl.bits.line_per_chunk = lpc; + hubp->att.cur_ctl.bits.cur_2x_magnify = attr->attribute_flags.bits.ENABLE_MAGNIFICATION; + hubp->att.settings.bits.dst_y_offset = 0; + hubp->att.settings.bits.chunk_hdl_adjust = 3; + hubp->use_mall_for_cursor = use_mall_for_cursor; } void hubp32_init(struct hubp *hubp) { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 2b49b83273742..41699ff7256f7 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -2727,6 +2727,7 @@ void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pip p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET = hubp->att.settings.bits.dst_y_offset; p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST = hubp->att.settings.bits.chunk_hdl_adjust; + p->HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR = hubp->use_mall_for_cursor; cs->offload_streams[stream_idx].payloads[payload_idx].pipe_mask |= (1u << pipe->pipe_idx); } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index 5998a20a18c4f..b0c13b506c11a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -132,6 +132,7 @@ struct hubp { struct cursor_position_cache_hubp pos; struct cursor_attribute_cache_hubp att; struct cursor_rect cur_rect; + bool use_mall_for_cursor; }; struct surface_flip_registers { From 4d4b0c4778f2c22ab3305582cc5a5df4babdcd00 Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Wed, 1 Oct 2025 13:40:57 -0400 Subject: [PATCH 2254/2653] drm/amd/display: Update spacing in struct Update spacing so that fields with longer name will still be aligned correctly (new fields to be added). Reviewed-by: Nicholas Kazlauskas Signed-off-by: Alvin Lee Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h b/drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h index 081831230821a..7ce2f417f86ad 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h @@ -57,9 +57,9 @@ struct cursor_attribute_cache_hubp { } size; union reg_cursor_settings_cfg { struct { - uint32_t dst_y_offset: 8; - uint32_t chunk_hdl_adjust: 2; - uint32_t reserved: 22; + uint32_t dst_y_offset: 8; + uint32_t chunk_hdl_adjust: 2; + uint32_t reserved: 22; } bits; uint32_t raw; } settings; From 962d78cf4cefd227475b10949c852222a9a756aa Mon Sep 17 00:00:00 2001 From: Peichen Huang Date: Tue, 30 Sep 2025 13:39:02 +0800 Subject: [PATCH 2255/2653] drm/amd/display: not skip hpd irq for bw alloc mode [WHY] Driver only process hpd irq when a branch device or when the link is established. It would cause some irq for bw_alloc mode of dp tunneling are ignored. [HOW] Driver should process hpd irq if bw_alloc and dp tunneling are enabled. Reviewed-by: Cruise Hung Signed-off-by: Peichen Huang Signed-off-by: Aurabindo Pillai --- .../dc/link/protocols/link_dp_dpia_bw.c | 19 +++++++++++++++---- .../dc/link/protocols/link_dp_irq_handler.c | 4 +++- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c index 8a3c18ae97a7b..b16eb97ae11c9 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c @@ -273,17 +273,28 @@ bool link_dpia_enable_usb4_dp_bw_alloc_mode(struct dc_link *link) */ void link_dp_dpia_handle_bw_alloc_status(struct dc_link *link, uint8_t status) { - link->dpia_bw_alloc_config.estimated_bw = get_estimated_bw(link); - if (status & DP_TUNNELING_BW_REQUEST_SUCCEEDED) { DC_LOG_DEBUG("%s: BW Allocation request succeeded on link(%d)", __func__, link->link_index); - } else if (status & DP_TUNNELING_BW_REQUEST_FAILED) { + } + + if (status & DP_TUNNELING_BW_REQUEST_FAILED) { DC_LOG_DEBUG("%s: BW Allocation request failed on link(%d) allocated/estimated BW=%d", __func__, link->link_index, link->dpia_bw_alloc_config.estimated_bw); link_dpia_send_bw_alloc_request(link, link->dpia_bw_alloc_config.estimated_bw); - } else if (status & DP_TUNNELING_ESTIMATED_BW_CHANGED) { + } + + if (status & DP_TUNNELING_BW_ALLOC_CAP_CHANGED) { + link->dpia_bw_alloc_config.bw_granularity = get_bw_granularity(link); + + DC_LOG_DEBUG("%s: Granularity changed on link(%d) new granularity=%d", + __func__, link->link_index, link->dpia_bw_alloc_config.bw_granularity); + } + + if (status & DP_TUNNELING_ESTIMATED_BW_CHANGED) { + link->dpia_bw_alloc_config.estimated_bw = get_estimated_bw(link); + DC_LOG_DEBUG("%s: Estimated BW changed on link(%d) new estimated BW=%d", __func__, link->link_index, link->dpia_bw_alloc_config.estimated_bw); } diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c index 6934774133471..4b01ab0a5a7f0 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c @@ -398,10 +398,12 @@ bool dp_should_allow_hpd_rx_irq(const struct dc_link *link) * Don't handle RX IRQ unless one of following is met: * 1) The link is established (cur_link_settings != unknown) * 2) We know we're dealing with a branch device, SST or MST + * 3) The link is bw_alloc enabled. */ if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || - is_dp_branch_device(link)) + is_dp_branch_device(link) || + link->dpia_bw_alloc_config.bw_alloc_enabled) return true; return false; From ac3abd12b5284e513b24687fb470525a9a544da5 Mon Sep 17 00:00:00 2001 From: Yihan Zhu Date: Fri, 26 Sep 2025 10:07:46 -0400 Subject: [PATCH 2256/2653] drm/amd/display: fix dppclk rcg poweron check [WHY & HOW] dppclk rcg power down will flip the poweron flag in the cache to cause dppclk rcg will never run the rcg ungate sequence in some condition. Wait 10us to let dpp dto fully ramp. Reviewed-by: Ovidiu (Ovi) Bunea Reviewed-by: Nicholas Kazlauskas Signed-off-by: Yihan Zhu Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index e097d52956b60..856615e7648b1 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -1187,6 +1187,7 @@ static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, /*we have this in hwss: disable_plane*/ //dccg35_set_dppclk_rcg(dccg, dpp_inst, true); } + udelay(10); dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; } @@ -1676,7 +1677,7 @@ static void dccg35_dpp_root_clock_control( { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - if (dccg->dpp_clock_gated[dpp_inst] == clock_on) + if (dccg->dpp_clock_gated[dpp_inst] != clock_on) return; if (clock_on) { @@ -1697,6 +1698,9 @@ static void dccg35_dpp_root_clock_control( //dccg35_set_dppclk_rcg(dccg, dpp_inst, true); } + // wait for clock to fully ramp + udelay(10); + dccg->dpp_clock_gated[dpp_inst] = !clock_on; DC_LOG_DEBUG("%s: dpp_inst(%d) clock_on = %d\n", __func__, dpp_inst, clock_on); } From f8b8803522249b5f112b3940c8f4217a564b86a2 Mon Sep 17 00:00:00 2001 From: Wenjing Liu Date: Thu, 2 Oct 2025 14:20:02 -0400 Subject: [PATCH 2257/2653] drm/amd/display: update perfmon measurement interfaces [how] The commit update interfaces for dchubbub perfmon meansurement to better reflect our requirements. Reviewed-by: Alvin Lee Signed-off-by: Wenjing Liu Signed-off-by: Aurabindo Pillai --- .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 36 +++++++++++++++---- 1 file changed, 29 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h index 843a18287c83f..2ce47c403840e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h @@ -244,15 +244,37 @@ struct hubbub_funcs { bool (*program_arbiter)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower); void (*get_det_sizes)(struct hubbub *hubbub, uint32_t *curr_det_sizes, uint32_t *target_det_sizes); uint32_t (*compbuf_config_error)(struct hubbub *hubbub); - struct hubbub_perfmon_funcs{ - void (*start_system_latency_measurement)(struct hubbub *hubbub); - void (*get_system_latency_result)(struct hubbub *hubbub, uint32_t refclk_mhz, struct hubbub_system_latencies *latencies); - void (*start_in_order_bandwidth_measurement)(struct hubbub *hubbub); - void (*get_in_order_bandwidth_result)(struct hubbub *hubbub, uint32_t refclk_mhz, uint32_t *bandwidth_mbps); - void (*start_urgent_ramp_latency_measurement)(struct hubbub *hubbub, const struct hubbub_urgent_latency_params *params); - void (*get_urgent_ramp_latency_result)(struct hubbub *hubbub, uint32_t refclk_mhz, uint32_t *latency_ns); + struct hubbub_perfmon_funcs { void (*reset)(struct hubbub *hubbub); + void (*start_measuring_max_memory_latency_ns)( + struct hubbub *hubbub); + uint32_t (*get_max_memory_latency_ns)(struct hubbub *hubbub, + uint32_t refclk_mhz, uint32_t *sample_count); + void (*start_measuring_average_memory_latency_ns)( + struct hubbub *hubbub); + uint32_t (*get_average_memory_latency_ns)(struct hubbub *hubbub, + uint32_t refclk_mhz, uint32_t *sample_count); + void (*start_measuring_urgent_ramp_latency_ns)( + struct hubbub *hubbub, + const struct hubbub_urgent_latency_params *params); + uint32_t (*get_urgent_ramp_latency_ns)(struct hubbub *hubbub, + uint32_t refclk_mhz); + void (*start_measuring_unbounded_bandwidth_mbps)( + struct hubbub *hubbub); + uint32_t (*get_unbounded_bandwidth_mbps)(struct hubbub *hubbub, + uint32_t refclk_mhz, uint32_t *duration_ns); + void (*start_measuring_average_bandwidth_mbps)( + struct hubbub *hubbub); + uint32_t (*get_average_bandwidth_mbps)(struct hubbub *hubbub, + uint32_t refclk_mhz, uint32_t min_duration_ns, + uint32_t *duration_ns); } perfmon; + + struct hubbub_qos_funcs { + void (*force_display_nominal_profile)(struct hubbub *hubbub); + void (*force_display_urgent_profile)(struct hubbub *hubbub); + void (*reset_display_qos_profile)(struct hubbub *hubbub); + } qos; }; struct hubbub { From 135cf139ca6b43473579eb3af1f22cb963fce7b7 Mon Sep 17 00:00:00 2001 From: Ovidiu Bunea Date: Thu, 2 Oct 2025 17:47:36 -0400 Subject: [PATCH 2258/2653] drm/amd/display: Move all DCCG RCG into HWSS root_clock_control [why & how] Enabling/disabling DCCG RCG should be done as a last-level step when enabling/disable blocks. This is handled by HWSS root_clock_control already during optimize_bandwidth. However, dccg35_dpp_root_clock_control was missing the RCG enable call on the disable path. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Ovidiu Bunea Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 5 ++--- drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 5 ----- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index 856615e7648b1..0aa41759f79d3 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -1184,8 +1184,7 @@ static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, dcn35_set_dppclk_enable(dccg, dpp_inst, true); } else { dcn35_set_dppclk_enable(dccg, dpp_inst, false); - /*we have this in hwss: disable_plane*/ - //dccg35_set_dppclk_rcg(dccg, dpp_inst, true); + dccg35_set_dppclk_rcg(dccg, dpp_inst, true); } udelay(10); dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; @@ -1695,7 +1694,7 @@ static void dccg35_dpp_root_clock_control( DPPCLK0_DTO_PHASE, 0, DPPCLK0_DTO_MODULO, 1); /*we have this in hwss: disable_plane*/ - //dccg35_set_dppclk_rcg(dccg, dpp_inst, true); + dccg35_set_dppclk_rcg(dccg, dpp_inst, true); } // wait for clock to fully ramp diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 404ff00c71300..9333b7fde3bcb 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -817,8 +817,6 @@ void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_state *context) { struct dpp *dpp = pipe_ctx->plane_res.dpp; - struct dccg *dccg = dc->res_pool->dccg; - /* enable DCFCLK current DCHUB */ pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); @@ -826,7 +824,6 @@ void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, /* initialize HUBP on power up */ pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); /*make sure DPPCLK is on*/ - dccg->funcs->dccg_root_gate_disable_control(dccg, dpp->inst, true); dpp->funcs->dpp_dppclk_control(dpp, false, true); /* make sure OPP_PIPE_CLOCK_EN = 1 */ pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( @@ -860,7 +857,6 @@ void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) { struct hubp *hubp = pipe_ctx->plane_res.hubp; struct dpp *dpp = pipe_ctx->plane_res.dpp; - struct dccg *dccg = dc->res_pool->dccg; dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); @@ -879,7 +875,6 @@ void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) hubp->funcs->hubp_clk_cntl(hubp, false); dpp->funcs->dpp_dppclk_control(dpp, false, false); - dccg->funcs->dccg_root_gate_disable_control(dccg, dpp->inst, false); hubp->power_gated = true; From f290557087271afb7667bf1ac1abbba93ec20cd6 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Mon, 29 Sep 2025 16:06:28 -0400 Subject: [PATCH 2259/2653] drm/amd/display: Add sink/link debug logs Add some extra logs to better help triage blackscreen issues. * Dump all the links to see if they have sinks associated. * Print the edid manufacturer & product id associated with a stream that was just created. Reviewed-by: Jerry Zuo Signed-off-by: Aurabindo Pillai --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 73 +++++++++++++++++++ .../gpu/drm/amd/display/dc/core/dc_stream.c | 6 +- 2 files changed, 77 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e493aa4470f8d..4a0d671f3a694 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3433,6 +3433,67 @@ static void apply_delay_after_dpcd_poweroff(struct amdgpu_device *adev, } } +/** + * amdgpu_dm_dump_links_and_sinks - Debug dump of all DC links and their sinks + * @adev: amdgpu device pointer + * + * Iterates through all DC links and dumps information about local and remote + * (MST) sinks. Should be called after connector detection is complete to see + * the final state of all links. + */ +static void amdgpu_dm_dump_links_and_sinks(struct amdgpu_device *adev) +{ + struct dc *dc = adev->dm.dc; + struct drm_device *dev = adev_to_drm(adev); + int li; + + if (!dc) + return; + + for (li = 0; li < dc->link_count; li++) { + struct dc_link *l = dc->links[li]; + const char *name = NULL; + int rs; + + if (!l) + continue; + if (l->local_sink && l->local_sink->edid_caps.display_name[0]) + name = l->local_sink->edid_caps.display_name; + else + name = "n/a"; + + drm_dbg_kms(dev, + "LINK_DUMP[%d]: local_sink=%p type=%d sink_signal=%d sink_count=%u edid_name=%s mst_capable=%d mst_alloc_streams=%d\n", + li, + l->local_sink, + l->type, + l->local_sink ? l->local_sink->sink_signal : SIGNAL_TYPE_NONE, + l->sink_count, + name, + l->dpcd_caps.is_mst_capable, + l->mst_stream_alloc_table.stream_count); + + /* Dump remote (MST) sinks if any */ + for (rs = 0; rs < l->sink_count; rs++) { + struct dc_sink *rsink = l->remote_sinks[rs]; + const char *rname = NULL; + + if (!rsink) + continue; + if (rsink->edid_caps.display_name[0]) + rname = rsink->edid_caps.display_name; + else + rname = "n/a"; + drm_dbg_kms(dev, + " REMOTE_SINK[%d:%d]: sink=%p signal=%d edid_name=%s\n", + li, rs, + rsink, + rsink->sink_signal, + rname); + } + } +} + static int dm_resume(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -3617,6 +3678,12 @@ static int dm_resume(struct amdgpu_ip_block *ip_block) } drm_connector_list_iter_end(&iter); + /* Debug dump: list all DC links and their associated sinks after detection + * is complete for all connectors. This provides a comprehensive view of the + * final state without repeating the dump for each connector. + */ + amdgpu_dm_dump_links_and_sinks(adev); + amdgpu_dm_irq_resume_late(adev); amdgpu_dm_smu_write_watermarks_table(adev); @@ -5467,6 +5534,12 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) amdgpu_set_panel_orientation(&aconnector->base); } + /* Debug dump: list all DC links and their associated sinks after detection + * is complete for all connectors. This provides a comprehensive view of the + * final state without repeating the dump for each connector. + */ + amdgpu_dm_dump_links_and_sinks(adev); + /* Software is initialized. Now we can register interrupt handlers. */ switch (adev->asic_type) { #if defined(CONFIG_DRM_AMD_DC_SI) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index ccaf37d3e7e4a..096fbb8ad24cd 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -879,9 +879,11 @@ void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream) stream->sink->sink_signal != SIGNAL_TYPE_NONE) { DC_LOG_DC( - "\tdispname: %s signal: %x\n", + "\tsignal: %x dispname: %s manufacturer_id: 0x%x product_id: 0x%x\n", + stream->signal, stream->sink->edid_caps.display_name, - stream->signal); + stream->sink->edid_caps.manufacturer_id, + stream->sink->edid_caps.product_id); } } } From 654f9e1fbb4fc6508a5525c88ad94508ac28e0e4 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Thu, 25 Sep 2025 10:23:59 -0400 Subject: [PATCH 2260/2653] drm/amd/display: use GFP_NOWAIT for allocation in interrupt handler schedule_dc_vmin_vmax() is called by dm_crtc_high_irq(). Hence, we cannot have the former sleep. Use GFP_NOWAIT for allocation in this function. Fixes: 288ec2b5d06d5 ("drm/amd/display: fix dmub access race condition") Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Sun peng (Leo) Li Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4a0d671f3a694..8414e707f66a0 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -560,13 +560,13 @@ static void schedule_dc_vmin_vmax(struct amdgpu_device *adev, struct dc_stream_state *stream, struct dc_crtc_timing_adjust *adjust) { - struct vupdate_offload_work *offload_work = kzalloc(sizeof(*offload_work), GFP_KERNEL); + struct vupdate_offload_work *offload_work = kzalloc(sizeof(*offload_work), GFP_NOWAIT); if (!offload_work) { drm_dbg_driver(adev_to_drm(adev), "Failed to allocate vupdate_offload_work\n"); return; } - struct dc_crtc_timing_adjust *adjust_copy = kzalloc(sizeof(*adjust_copy), GFP_KERNEL); + struct dc_crtc_timing_adjust *adjust_copy = kzalloc(sizeof(*adjust_copy), GFP_NOWAIT); if (!adjust_copy) { drm_dbg_driver(adev_to_drm(adev), "Failed to allocate adjust_copy\n"); kfree(offload_work); From 3ad4356ff2c0c3f55cdd003464991e7623ff7e3d Mon Sep 17 00:00:00 2001 From: Dominik Kaszewski Date: Tue, 15 Jul 2025 14:02:40 +0200 Subject: [PATCH 2261/2653] drm/amd/display: Remove dc state from check_update [Why] dc_check_update_surfaces_for_stream should not have access to entire DC, especially not a mutable one. Concurrent checks should be able to run independently of one another, without risk of changing state. [How] * Remove access to dc state other than debug and capacity. * Move some checks from DC to DM caller. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Dominik Kaszewski Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/dc/core/dc.c | 81 ++++++++++++------------ 1 file changed, 41 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index fe7af5b3425ab..280d9cdb7e06f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2725,21 +2725,32 @@ static enum surface_update_type get_plane_info_update_type(const struct dc *dc, elevate_update_type(&update_type, UPDATE_TYPE_MED); } + const struct dc_tiling_info *tiling = &u->plane_info->tiling_info; - if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info, - sizeof(struct dc_tiling_info)) != 0) { + if (memcmp(tiling, &u->surface->tiling_info, sizeof(*tiling)) != 0) { update_flags->bits.swizzle_change = 1; elevate_update_type(&update_type, UPDATE_TYPE_MED); - /* todo: below are HW dependent, we should add a hook to - * DCE/N resource and validated there. - */ - if (!dc->debug.skip_full_updated_if_possible) { - /* swizzled mode requires RQ to be setup properly, - * thus need to run DML to calculate RQ settings - */ - update_flags->bits.bandwidth_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_FULL); + switch (tiling->gfxversion) { + case DcGfxVersion9: + case DcGfxVersion10: + case DcGfxVersion11: + if (tiling->gfx9.swizzle != DC_SW_LINEAR) { + elevate_update_type(&update_type, UPDATE_TYPE_FULL); + update_flags->bits.bandwidth_change = 1; + } + break; + case DcGfxAddr3: + if (tiling->gfx_addr3.swizzle != DC_ADDR3_SW_LINEAR) { + elevate_update_type(&update_type, UPDATE_TYPE_FULL); + update_flags->bits.bandwidth_change = 1; + } + break; + case DcGfxVersion7: + case DcGfxVersion8: + case DcGfxVersionUnknown: + default: + break; } } @@ -2808,12 +2819,11 @@ static enum surface_update_type get_scaling_info_update_type( static enum surface_update_type det_surface_update(const struct dc *dc, const struct dc_surface_update *u) { - const struct dc_state *context = dc->current_state; enum surface_update_type type; enum surface_update_type overall_type = UPDATE_TYPE_FAST; union surface_update_flags *update_flags = &u->surface->update_flags; - if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) { + if (u->surface->force_full_update) { update_flags->raw = 0xFFFFFFFF; return UPDATE_TYPE_FULL; } @@ -2944,12 +2954,6 @@ static enum surface_update_type check_update_surfaces_for_stream( int i; enum surface_update_type overall_type = UPDATE_TYPE_FAST; - if (dc->idle_optimizations_allowed || dc_can_clear_cursor_limit(dc)) - overall_type = UPDATE_TYPE_FULL; - - if (stream_status == NULL || stream_status->plane_count != surface_count) - overall_type = UPDATE_TYPE_FULL; - if (stream_update && stream_update->pending_test_pattern) { overall_type = UPDATE_TYPE_FULL; } @@ -3046,27 +3050,6 @@ enum surface_update_type dc_check_update_surfaces_for_stream( updates[i].surface->update_flags.raw = 0; type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status); - if (type == UPDATE_TYPE_FULL) { - if (stream_update) { - uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed; - stream_update->stream->update_flags.raw = 0xFFFFFFFF; - stream_update->stream->update_flags.bits.dsc_changed = dsc_changed; - } - for (i = 0; i < surface_count; i++) - updates[i].surface->update_flags.raw = 0xFFFFFFFF; - } - - if (type == UPDATE_TYPE_FAST) { - // If there's an available clock comparator, we use that. - if (dc->clk_mgr->funcs->are_clock_states_equal) { - if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk)) - dc->optimized_required = true; - // Else we fallback to mem compare. - } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) { - dc->optimized_required = true; - } - } - return type; } @@ -3437,6 +3420,12 @@ static void update_seamless_boot_flags(struct dc *dc, } } +static bool full_update_required(struct dc *dc, + struct dc_surface_update *srf_updates, + int surface_count, + struct dc_stream_update *stream_update, + struct dc_stream_state *stream); + /** * update_planes_and_stream_state() - The function takes planes and stream * updates as inputs and determines the appropriate update type. If update type @@ -3484,6 +3473,8 @@ static bool update_planes_and_stream_state(struct dc *dc, context = dc->current_state; update_type = dc_check_update_surfaces_for_stream( dc, srf_updates, surface_count, stream_update, stream_status); + if (full_update_required(dc, srf_updates, surface_count, stream_update, stream)) + update_type = UPDATE_TYPE_FULL; /* It is possible to receive a flip for one plane while there are multiple flip_immediate planes in the same stream. * E.g. Desktop and MPO plane are flip_immediate but only the MPO plane received a flip * Force the other flip_immediate planes to flip so GSL doesn't wait for a flip that won't come. @@ -3515,6 +3506,16 @@ static bool update_planes_and_stream_state(struct dc *dc, } } + if (update_type == UPDATE_TYPE_FULL) { + if (stream_update) { + uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed; + stream_update->stream->update_flags.raw = 0xFFFFFFFF; + stream_update->stream->update_flags.bits.dsc_changed = dsc_changed; + } + for (i = 0; i < surface_count; i++) + srf_updates[i].surface->update_flags.raw = 0xFFFFFFFF; + } + if (update_type >= update_surface_trace_level) update_surface_trace(dc, srf_updates, surface_count); From f3c47b6e45820b0620deb0cf21a55e5393c64941 Mon Sep 17 00:00:00 2001 From: Dominik Kaszewski Date: Fri, 3 Oct 2025 11:50:55 +0200 Subject: [PATCH 2262/2653] drm/amd/display: Fix performance regression from full updates [Why] full_update_required is too strict at update_planes_and_stream_state, causing a performance regression due to too many updates being full. [How] * Carve out weak version of full_update_required for use inside update_planes_and_stream_state. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Dominik Kaszewski Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/dc/core/dc.c | 54 +++++++++++++++--------- 1 file changed, 34 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 280d9cdb7e06f..55aab3b190b88 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3420,7 +3420,7 @@ static void update_seamless_boot_flags(struct dc *dc, } } -static bool full_update_required(struct dc *dc, +static bool full_update_required_weak(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, struct dc_stream_update *stream_update, @@ -3473,8 +3473,10 @@ static bool update_planes_and_stream_state(struct dc *dc, context = dc->current_state; update_type = dc_check_update_surfaces_for_stream( dc, srf_updates, surface_count, stream_update, stream_status); - if (full_update_required(dc, srf_updates, surface_count, stream_update, stream)) + + if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream)) update_type = UPDATE_TYPE_FULL; + /* It is possible to receive a flip for one plane while there are multiple flip_immediate planes in the same stream. * E.g. Desktop and MPO plane are flip_immediate but only the MPO plane received a flip * Force the other flip_immediate planes to flip so GSL doesn't wait for a flip that won't come. @@ -5048,18 +5050,42 @@ bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_ return false; } -static bool full_update_required(struct dc *dc, +static bool full_update_required_weak(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, struct dc_stream_update *stream_update, struct dc_stream_state *stream) { - - int i; - struct dc_stream_status *stream_status; const struct dc_state *context = dc->current_state; + if (srf_updates) + for (int i = 0; i < surface_count; i++) + if (!is_surface_in_context(context, srf_updates[i].surface)) + return true; - for (i = 0; i < surface_count; i++) { + if (stream) { + const struct dc_stream_status *stream_status = dc_stream_get_status(stream); + if (stream_status == NULL || stream_status->plane_count != surface_count) + return true; + } + if (dc->idle_optimizations_allowed) + return true; + + if (dc_can_clear_cursor_limit(dc)) + return true; + + return false; +} + +static bool full_update_required(struct dc *dc, + struct dc_surface_update *srf_updates, + int surface_count, + struct dc_stream_update *stream_update, + struct dc_stream_state *stream) +{ + if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream)) + return true; + + for (int i = 0; i < surface_count; i++) { if (srf_updates && (srf_updates[i].plane_info || srf_updates[i].scaling_info || @@ -5075,8 +5101,7 @@ static bool full_update_required(struct dc *dc, srf_updates[i].flip_addr->address.tmz_surface != srf_updates[i].surface->address.tmz_surface) || (srf_updates[i].cm2_params && (srf_updates[i].cm2_params->component_settings.shaper_3dlut_setting != srf_updates[i].surface->mcm_shaper_3dlut_setting || - srf_updates[i].cm2_params->component_settings.lut1d_enable != srf_updates[i].surface->mcm_lut1d_enable)) || - !is_surface_in_context(context, srf_updates[i].surface))) + srf_updates[i].cm2_params->component_settings.lut1d_enable != srf_updates[i].surface->mcm_lut1d_enable)))) return true; } @@ -5112,17 +5137,6 @@ static bool full_update_required(struct dc *dc, stream_update->hw_cursor_req)) return true; - if (stream) { - stream_status = dc_stream_get_status(stream); - if (stream_status == NULL || stream_status->plane_count != surface_count) - return true; - } - if (dc->idle_optimizations_allowed) - return true; - - if (dc_can_clear_cursor_limit(dc)) - return true; - return false; } From 8509d30e387ea569ae82e0dcd8776f2159fe844c Mon Sep 17 00:00:00 2001 From: Wenjing Liu Date: Thu, 2 Oct 2025 11:02:39 -0400 Subject: [PATCH 2263/2653] drm/amd/display: add additional hdcp traces [why] Current hdcp trace only tracks hdcp errors. We need to expand the trace structure for more tracing information. [how] Add following traces for hdcp1: - attempt_count - downstream_device_count Add following traces for hdcp2: - attempt_count - downstream_device_count - hdcp1_device_downstream - hdcp2_legacy_device_downstream Reviewed-by: Sung Lee Signed-off-by: Wenjing Liu Signed-off-by: Aurabindo Pillai --- .../gpu/drm/amd/display/modules/hdcp/hdcp.c | 6 +++--- .../gpu/drm/amd/display/modules/hdcp/hdcp.h | 2 +- .../display/modules/hdcp/hdcp1_execution.c | 13 +++++++++++-- .../display/modules/hdcp/hdcp2_execution.c | 19 ++++++++++++++++--- .../drm/amd/display/modules/hdcp/hdcp_log.h | 6 ++++++ .../drm/amd/display/modules/inc/mod_hdcp.h | 14 ++++++++++++++ 6 files changed, 51 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c index c760216a62405..ca402ddcdacc8 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c @@ -354,7 +354,7 @@ enum mod_hdcp_status mod_hdcp_add_display(struct mod_hdcp *hdcp, /* reset retry counters */ reset_retry_counts(hdcp); - /* reset error trace */ + /* reset trace */ memset(&hdcp->connection.trace, 0, sizeof(hdcp->connection.trace)); /* add display to connection */ @@ -400,7 +400,7 @@ enum mod_hdcp_status mod_hdcp_remove_display(struct mod_hdcp *hdcp, /* clear retry counters */ reset_retry_counts(hdcp); - /* reset error trace */ + /* reset trace */ memset(&hdcp->connection.trace, 0, sizeof(hdcp->connection.trace)); /* remove display */ @@ -464,7 +464,7 @@ enum mod_hdcp_status mod_hdcp_update_display(struct mod_hdcp *hdcp, /* clear retry counters */ reset_retry_counts(hdcp); - /* reset error trace */ + /* reset trace */ memset(&hdcp->connection.trace, 0, sizeof(hdcp->connection.trace)); /* set new adjustment */ diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h index a37634942b075..b883d626f1c37 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h @@ -508,7 +508,7 @@ static inline void set_auth_complete(struct mod_hdcp *hdcp, struct mod_hdcp_output *output) { output->auth_complete = 1; - mod_hdcp_log_ddc_trace(hdcp); + HDCP_AUTH_COMPLETE_TRACE(hdcp); } /* connection topology helpers */ diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c index 8bc377560787b..1bbd728d4345f 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp1_execution.c @@ -29,6 +29,7 @@ static inline enum mod_hdcp_status validate_bksv(struct mod_hdcp *hdcp) { uint64_t n = 0; uint8_t count = 0; + enum mod_hdcp_status status; u8 bksv[sizeof(n)] = { }; memcpy(bksv, hdcp->auth.msg.hdcp1.bksv, sizeof(hdcp->auth.msg.hdcp1.bksv)); @@ -38,8 +39,14 @@ static inline enum mod_hdcp_status validate_bksv(struct mod_hdcp *hdcp) count++; n &= (n - 1); } - return (count == 20) ? MOD_HDCP_STATUS_SUCCESS : - MOD_HDCP_STATUS_HDCP1_INVALID_BKSV; + + if (count == 20) { + hdcp->connection.trace.hdcp1.attempt_count++; + status = MOD_HDCP_STATUS_SUCCESS; + } else { + status = MOD_HDCP_STATUS_HDCP1_INVALID_BKSV; + } + return status; } static inline enum mod_hdcp_status check_ksv_ready(struct mod_hdcp *hdcp) @@ -135,6 +142,8 @@ static inline enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp) if (get_device_count(hdcp) == 0) return MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE; + hdcp->connection.trace.hdcp1.downstream_device_count = get_device_count(hdcp); + /* Some MST display may choose to report the internal panel as an HDCP RX. * To update this condition with 1(because the immediate repeater's internal * panel is possibly not included in DEVICE_COUNT) + get_device_count(hdcp). diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c index bb8ae80b37f85..5628f0ef73fd1 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c @@ -48,6 +48,7 @@ static inline enum mod_hdcp_status check_receiver_id_list_ready(struct mod_hdcp static inline enum mod_hdcp_status check_hdcp2_capable(struct mod_hdcp *hdcp) { enum mod_hdcp_status status; + struct mod_hdcp_trace *trace = &hdcp->connection.trace; if (is_dp_hdcp(hdcp)) status = (hdcp->auth.msg.hdcp2.rxcaps_dp[0] == HDCP_2_2_RX_CAPS_VERSION_VAL) && @@ -55,9 +56,14 @@ static inline enum mod_hdcp_status check_hdcp2_capable(struct mod_hdcp *hdcp) MOD_HDCP_STATUS_SUCCESS : MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE; else - status = (hdcp->auth.msg.hdcp2.hdcp2version_hdmi & HDCP_2_2_HDMI_SUPPORT_MASK) ? - MOD_HDCP_STATUS_SUCCESS : - MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE; + status = (hdcp->auth.msg.hdcp2.hdcp2version_hdmi + & HDCP_2_2_HDMI_SUPPORT_MASK) + ? MOD_HDCP_STATUS_SUCCESS + : MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE; + + if (status == MOD_HDCP_STATUS_SUCCESS) + trace->hdcp2.attempt_count++; + return status; } @@ -201,10 +207,17 @@ static inline uint8_t get_device_count(struct mod_hdcp *hdcp) static enum mod_hdcp_status check_device_count(struct mod_hdcp *hdcp) { + struct mod_hdcp_trace *trace = &hdcp->connection.trace; + /* Avoid device count == 0 to do authentication */ if (get_device_count(hdcp) == 0) return MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE; + trace->hdcp2.downstream_device_count = get_device_count(hdcp); + trace->hdcp2.hdcp1_device_downstream = + HDCP_2_2_HDCP1_DEVICE_CONNECTED(hdcp->auth.msg.hdcp2.rx_id_list[2]); + trace->hdcp2.hdcp2_legacy_device_downstream = + HDCP_2_2_HDCP_2_0_REP_CONNECTED(hdcp->auth.msg.hdcp2.rx_id_list[2]); /* Some MST display may choose to report the internal panel as an HDCP RX. */ /* To update this condition with 1(because the immediate repeater's internal */ /* panel is possibly not included in DEVICE_COUNT) + get_device_count(hdcp). */ diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h index 1d83c1b9da104..26553aa4c5cae 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.h @@ -31,6 +31,7 @@ #define HDCP_LOG_FSM(hdcp, ...) DRM_DEBUG_KMS(__VA_ARGS__) #define HDCP_LOG_TOP(hdcp, ...) pr_debug("[HDCP_TOP]:"__VA_ARGS__) #define HDCP_LOG_DDC(hdcp, ...) pr_debug("[HDCP_DDC]:"__VA_ARGS__) +#define HDCP_LOG_TRA(hdcp) do {} while (0) /* default logs */ #define HDCP_ERROR_TRACE(hdcp, status) \ @@ -131,4 +132,9 @@ HDCP_LOG_TOP(hdcp, "[Link %d] %s display %d", hdcp->config.index, __func__, i); \ } while (0) +#define HDCP_AUTH_COMPLETE_TRACE(hdcp) do { \ + mod_hdcp_log_ddc_trace(hdcp); \ + HDCP_LOG_TRA(hdcp); \ +} while (0) + #endif // MOD_HDCP_LOG_H_ diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h index b51ddf2846df8..46e52fb3a1180 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h @@ -230,9 +230,23 @@ struct mod_hdcp_error { uint8_t state_id; }; +struct mod_hdcp1_trace { + uint8_t attempt_count; + uint8_t downstream_device_count; +}; + +struct mod_hdcp2_trace { + uint8_t attempt_count; + uint8_t downstream_device_count; + uint8_t hdcp1_device_downstream; + uint8_t hdcp2_legacy_device_downstream; +}; + struct mod_hdcp_trace { struct mod_hdcp_error errors[MAX_NUM_OF_ERROR_TRACE]; uint8_t error_count; + struct mod_hdcp1_trace hdcp1; + struct mod_hdcp2_trace hdcp2; }; enum mod_hdcp_encryption_status { From 9d74ddf4a0ebbce5e786030d58830f2e7d673338 Mon Sep 17 00:00:00 2001 From: Ilya Bakoulin Date: Wed, 3 Sep 2025 14:07:41 -0400 Subject: [PATCH 2264/2653] drm/amd/display: add new block sequence-building/executing functions [Why/How] Create functions for building/executing HW block programming steps Reviewed-by: Alvin Lee Signed-off-by: Ilya Bakoulin Signed-off-by: Aurabindo Pillai --- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 3161 ++++++++++++++++- drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 1352 ++++++- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 98 + .../amd/display/dc/hwss/dcn401/dcn401_init.c | 17 + .../drm/amd/display/dc/hwss/hw_sequencer.h | 1409 +++++++- .../display/dc/hwss/hw_sequencer_private.h | 36 + 7 files changed, 5878 insertions(+), 196 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 1bed3b14a287e..16d916986fed6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -32,6 +32,12 @@ #include "resource.h" #include "dc_dmub_srv.h" #include "dc_state_priv.h" +#include "opp.h" +#include "dsc.h" +#include "dchubbub.h" +#include "dccg.h" +#include "abm.h" +#include "dcn10/dcn10_hubbub.h" #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) #define MAX_NUM_MCACHE 8 @@ -784,7 +790,7 @@ void hwss_build_fast_sequence(struct dc *dc, while (current_mpc_pipe) { if (current_mpc_pipe->plane_state) { if (dc->hwss.set_flip_control_gsl && current_mpc_pipe->plane_state->update_flags.raw) { - block_sequence[*num_steps].params.set_flip_control_gsl_params.pipe_ctx = current_mpc_pipe; + block_sequence[*num_steps].params.set_flip_control_gsl_params.hubp = current_mpc_pipe->plane_res.hubp; block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe->plane_state->flip_immediate; block_sequence[*num_steps].func = HUBP_SET_FLIP_CONTROL_GSL; (*num_steps)++; @@ -949,8 +955,9 @@ void hwss_execute_sequence(struct dc *dc, params->pipe_control_lock_params.lock); break; case HUBP_SET_FLIP_CONTROL_GSL: - dc->hwss.set_flip_control_gsl(params->set_flip_control_gsl_params.pipe_ctx, - params->set_flip_control_gsl_params.flip_immediate); + params->set_flip_control_gsl_params.hubp->funcs->hubp_set_flip_control_surface_gsl( + params->set_flip_control_gsl_params.hubp, + params->set_flip_control_gsl_params.flip_immediate); break; case HUBP_PROGRAM_TRIPLEBUFFER: dc->hwss.program_triplebuffer(params->program_triplebuffer_params.dc, @@ -1011,11 +1018,296 @@ void hwss_execute_sequence(struct dc *dc, case DMUB_HW_CONTROL_LOCK_FAST: dc->hwss.dmub_hw_control_lock_fast(params); break; + case HUBP_PROGRAM_SURFACE_CONFIG: + hwss_program_surface_config(params); + break; + case HUBP_PROGRAM_MCACHE_ID: + hwss_program_mcache_id_and_split_coordinate(params); + break; case PROGRAM_CURSOR_UPDATE_NOW: dc->hwss.program_cursor_offload_now( params->program_cursor_update_now_params.dc, params->program_cursor_update_now_params.pipe_ctx); break; + case HUBP_WAIT_PIPE_READ_START: + params->hubp_wait_pipe_read_start_params.hubp->funcs->hubp_wait_pipe_read_start( + params->hubp_wait_pipe_read_start_params.hubp); + break; + case HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM: + dc->hwss.apply_update_flags_for_phantom(params->apply_update_flags_for_phantom_params.pipe_ctx); + break; + case HWS_UPDATE_PHANTOM_VP_POSITION: + dc->hwss.update_phantom_vp_position(params->update_phantom_vp_position_params.dc, + params->update_phantom_vp_position_params.context, + params->update_phantom_vp_position_params.pipe_ctx); + break; + case OPTC_SET_ODM_COMBINE: + hwss_set_odm_combine(params); + break; + case OPTC_SET_ODM_BYPASS: + hwss_set_odm_bypass(params); + break; + case OPP_PIPE_CLOCK_CONTROL: + hwss_opp_pipe_clock_control(params); + break; + case OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL: + hwss_opp_program_left_edge_extra_pixel(params); + break; + case DCCG_SET_DTO_DSCCLK: + hwss_dccg_set_dto_dscclk(params); + break; + case DSC_SET_CONFIG: + hwss_dsc_set_config(params); + break; + case DSC_ENABLE: + hwss_dsc_enable(params); + break; + case TG_SET_DSC_CONFIG: + hwss_tg_set_dsc_config(params); + break; + case DSC_DISCONNECT: + hwss_dsc_disconnect(params); + break; + case DSC_READ_STATE: + hwss_dsc_read_state(params); + break; + case DSC_CALCULATE_AND_SET_CONFIG: + hwss_dsc_calculate_and_set_config(params); + break; + case DSC_ENABLE_WITH_OPP: + hwss_dsc_enable_with_opp(params); + break; + case TG_PROGRAM_GLOBAL_SYNC: + hwss_tg_program_global_sync(params); + break; + case TG_WAIT_FOR_STATE: + hwss_tg_wait_for_state(params); + break; + case TG_SET_VTG_PARAMS: + hwss_tg_set_vtg_params(params); + break; + case TG_SETUP_VERTICAL_INTERRUPT2: + hwss_tg_setup_vertical_interrupt2(params); + break; + case DPP_SET_HDR_MULTIPLIER: + hwss_dpp_set_hdr_multiplier(params); + break; + case HUBP_PROGRAM_DET_SIZE: + hwss_program_det_size(params); + break; + case HUBP_PROGRAM_DET_SEGMENTS: + hwss_program_det_segments(params); + break; + case OPP_SET_DYN_EXPANSION: + hwss_opp_set_dyn_expansion(params); + break; + case OPP_PROGRAM_FMT: + hwss_opp_program_fmt(params); + break; + case OPP_PROGRAM_BIT_DEPTH_REDUCTION: + hwss_opp_program_bit_depth_reduction(params); + break; + case OPP_SET_DISP_PATTERN_GENERATOR: + hwss_opp_set_disp_pattern_generator(params); + break; + case ABM_SET_PIPE: + hwss_set_abm_pipe(params); + break; + case ABM_SET_LEVEL: + hwss_set_abm_level(params); + break; + case ABM_SET_IMMEDIATE_DISABLE: + hwss_set_abm_immediate_disable(params); + break; + case MPC_REMOVE_MPCC: + hwss_mpc_remove_mpcc(params); + break; + case OPP_SET_MPCC_DISCONNECT_PENDING: + hwss_opp_set_mpcc_disconnect_pending(params); + break; + case DC_SET_OPTIMIZED_REQUIRED: + hwss_dc_set_optimized_required(params); + break; + case HUBP_DISCONNECT: + hwss_hubp_disconnect(params); + break; + case HUBBUB_FORCE_PSTATE_CHANGE_CONTROL: + hwss_hubbub_force_pstate_change_control(params); + break; + case TG_ENABLE_CRTC: + hwss_tg_enable_crtc(params); + break; + case TG_SET_GSL: + hwss_tg_set_gsl(params); + break; + case TG_SET_GSL_SOURCE_SELECT: + hwss_tg_set_gsl_source_select(params); + break; + case HUBP_WAIT_FLIP_PENDING: + hwss_hubp_wait_flip_pending(params); + break; + case TG_WAIT_DOUBLE_BUFFER_PENDING: + hwss_tg_wait_double_buffer_pending(params); + break; + case UPDATE_FORCE_PSTATE: + hwss_update_force_pstate(params); + break; + case HUBBUB_APPLY_DEDCN21_147_WA: + hwss_hubbub_apply_dedcn21_147_wa(params); + break; + case HUBBUB_ALLOW_SELF_REFRESH_CONTROL: + hwss_hubbub_allow_self_refresh_control(params); + break; + case TG_GET_FRAME_COUNT: + hwss_tg_get_frame_count(params); + break; + case MPC_SET_DWB_MUX: + hwss_mpc_set_dwb_mux(params); + break; + case MPC_DISABLE_DWB_MUX: + hwss_mpc_disable_dwb_mux(params); + break; + case MCIF_WB_CONFIG_BUF: + hwss_mcif_wb_config_buf(params); + break; + case MCIF_WB_CONFIG_ARB: + hwss_mcif_wb_config_arb(params); + break; + case MCIF_WB_ENABLE: + hwss_mcif_wb_enable(params); + break; + case MCIF_WB_DISABLE: + hwss_mcif_wb_disable(params); + break; + case DWBC_ENABLE: + hwss_dwbc_enable(params); + break; + case DWBC_DISABLE: + hwss_dwbc_disable(params); + break; + case DWBC_UPDATE: + hwss_dwbc_update(params); + break; + case HUBP_UPDATE_MALL_SEL: + hwss_hubp_update_mall_sel(params); + break; + case HUBP_PREPARE_SUBVP_BUFFERING: + hwss_hubp_prepare_subvp_buffering(params); + break; + case HUBP_SET_BLANK_EN: + hwss_hubp_set_blank_en(params); + break; + case HUBP_DISABLE_CONTROL: + hwss_hubp_disable_control(params); + break; + case HUBBUB_SOFT_RESET: + hwss_hubbub_soft_reset(params); + break; + case HUBP_CLK_CNTL: + hwss_hubp_clk_cntl(params); + break; + case HUBP_INIT: + hwss_hubp_init(params); + break; + case HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS: + hwss_hubp_set_vm_system_aperture_settings(params); + break; + case HUBP_SET_FLIP_INT: + hwss_hubp_set_flip_int(params); + break; + case DPP_DPPCLK_CONTROL: + hwss_dpp_dppclk_control(params); + break; + case DISABLE_PHANTOM_CRTC: + hwss_disable_phantom_crtc(params); + break; + case DSC_PG_STATUS: + hwss_dsc_pg_status(params); + break; + case DSC_WAIT_DISCONNECT_PENDING_CLEAR: + hwss_dsc_wait_disconnect_pending_clear(params); + break; + case DSC_DISABLE: + hwss_dsc_disable(params); + break; + case DCCG_SET_REF_DSCCLK: + hwss_dccg_set_ref_dscclk(params); + break; + case DPP_PG_CONTROL: + hwss_dpp_pg_control(params); + break; + case HUBP_PG_CONTROL: + hwss_hubp_pg_control(params); + break; + case HUBP_RESET: + hwss_hubp_reset(params); + break; + case DPP_RESET: + hwss_dpp_reset(params); + break; + case DPP_ROOT_CLOCK_CONTROL: + hwss_dpp_root_clock_control(params); + break; + case DC_IP_REQUEST_CNTL: + hwss_dc_ip_request_cntl(params); + break; + case DCCG_UPDATE_DPP_DTO: + hwss_dccg_update_dpp_dto(params); + break; + case HUBP_VTG_SEL: + hwss_hubp_vtg_sel(params); + break; + case HUBP_SETUP2: + hwss_hubp_setup2(params); + break; + case HUBP_SETUP: + hwss_hubp_setup(params); + break; + case HUBP_SET_UNBOUNDED_REQUESTING: + hwss_hubp_set_unbounded_requesting(params); + break; + case HUBP_SETUP_INTERDEPENDENT2: + hwss_hubp_setup_interdependent2(params); + break; + case HUBP_SETUP_INTERDEPENDENT: + hwss_hubp_setup_interdependent(params); + break; + case DPP_SET_CURSOR_MATRIX: + hwss_dpp_set_cursor_matrix(params); + break; + case MPC_UPDATE_BLENDING: + hwss_mpc_update_blending(params); + break; + case MPC_ASSERT_IDLE_MPCC: + hwss_mpc_assert_idle_mpcc(params); + break; + case MPC_INSERT_PLANE: + hwss_mpc_insert_plane(params); + break; + case DPP_SET_SCALER: + hwss_dpp_set_scaler(params); + break; + case HUBP_MEM_PROGRAM_VIEWPORT: + hwss_hubp_mem_program_viewport(params); + break; + case SET_CURSOR_ATTRIBUTE: + hwss_set_cursor_attribute(params); + break; + case SET_CURSOR_POSITION: + hwss_set_cursor_position(params); + break; + case SET_CURSOR_SDR_WHITE_LEVEL: + hwss_set_cursor_sdr_white_level(params); + break; + case PROGRAM_OUTPUT_CSC: + hwss_program_output_csc(params); + break; + case HUBP_SET_BLANK: + hwss_hubp_set_blank(params); + break; + case PHANTOM_HUBP_POST_ENABLE: + hwss_phantom_hubp_post_enable(params); + break; default: ASSERT(false); break; @@ -1023,256 +1315,2749 @@ void hwss_execute_sequence(struct dc *dc, } } -void hwss_send_dmcub_cmd(union block_sequence_params *params) +/** + * Helper function to add OPTC pipe control lock to block sequence + */ +void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx, + bool lock) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].params.pipe_control_lock_params.lock = lock; + seq_state->steps[*seq_state->num_steps].func = OPTC_PIPE_CONTROL_LOCK; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add HUBP set flip control GSL to block sequence + */ +void hwss_add_hubp_set_flip_control_gsl(struct block_sequence_state *seq_state, + struct hubp *hubp, + bool flip_immediate) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.set_flip_control_gsl_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.set_flip_control_gsl_params.flip_immediate = flip_immediate; + seq_state->steps[*seq_state->num_steps].func = HUBP_SET_FLIP_CONTROL_GSL; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add HUBP program triplebuffer to block sequence + */ +void hwss_add_hubp_program_triplebuffer(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx, + bool enableTripleBuffer) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].params.program_triplebuffer_params.enableTripleBuffer = enableTripleBuffer; + seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add HUBP update plane address to block sequence + */ +void hwss_add_hubp_update_plane_addr(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.update_plane_addr_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.update_plane_addr_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].func = HUBP_UPDATE_PLANE_ADDR; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add DPP set input transfer function to block sequence + */ +void hwss_add_dpp_set_input_transfer_func(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_plane_state *plane_state) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].params.set_input_transfer_func_params.plane_state = plane_state; + seq_state->steps[*seq_state->num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add DPP program gamut remap to block sequence + */ +void hwss_add_dpp_program_gamut_remap(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.program_gamut_remap_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_GAMUT_REMAP; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add DPP program bias and scale to block sequence + */ +void hwss_add_dpp_program_bias_and_scale(struct block_sequence_state *seq_state, struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.program_bias_and_scale_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add OPTC program manual trigger to block sequence + */ +void hwss_add_optc_program_manual_trigger(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.program_manual_trigger_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add DPP set output transfer function to block sequence + */ +void hwss_add_dpp_set_output_transfer_func(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_stream_state *stream) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.stream = stream; + seq_state->steps[*seq_state->num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add MPC update visual confirm to block sequence + */ +void hwss_add_mpc_update_visual_confirm(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx, + int mpcc_id) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].params.update_visual_confirm_params.mpcc_id = mpcc_id; + seq_state->steps[*seq_state->num_steps].func = MPC_UPDATE_VISUAL_CONFIRM; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add MPC power on MPC mem PWR to block sequence + */ +void hwss_add_mpc_power_on_mpc_mem_pwr(struct block_sequence_state *seq_state, + struct mpc *mpc, + int mpcc_id, + bool power_on) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.mpc = mpc; + seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = mpcc_id; + seq_state->steps[*seq_state->num_steps].params.power_on_mpc_mem_pwr_params.power_on = power_on; + seq_state->steps[*seq_state->num_steps].func = MPC_POWER_ON_MPC_MEM_PWR; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add MPC set output CSC to block sequence + */ +void hwss_add_mpc_set_output_csc(struct block_sequence_state *seq_state, + struct mpc *mpc, + int opp_id, + const uint16_t *regval, + enum mpc_output_csc_mode ocsc_mode) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.mpc = mpc; + seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.opp_id = opp_id; + seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.regval = regval; + seq_state->steps[*seq_state->num_steps].params.set_output_csc_params.ocsc_mode = ocsc_mode; + seq_state->steps[*seq_state->num_steps].func = MPC_SET_OUTPUT_CSC; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add MPC set OCSC default to block sequence + */ +void hwss_add_mpc_set_ocsc_default(struct block_sequence_state *seq_state, + struct mpc *mpc, + int opp_id, + enum dc_color_space colorspace, + enum mpc_output_csc_mode ocsc_mode) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.mpc = mpc; + seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.opp_id = opp_id; + seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.color_space = colorspace; + seq_state->steps[*seq_state->num_steps].params.set_ocsc_default_params.ocsc_mode = ocsc_mode; + seq_state->steps[*seq_state->num_steps].func = MPC_SET_OCSC_DEFAULT; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add DMUB send DMCUB command to block sequence + */ +void hwss_add_dmub_send_dmcub_cmd(struct block_sequence_state *seq_state, + struct dc_context *ctx, + union dmub_rb_cmd *cmd, + enum dm_dmub_wait_type wait_type) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.send_dmcub_cmd_params.ctx = ctx; + seq_state->steps[*seq_state->num_steps].params.send_dmcub_cmd_params.cmd = cmd; + seq_state->steps[*seq_state->num_steps].params.send_dmcub_cmd_params.wait_type = wait_type; + seq_state->steps[*seq_state->num_steps].func = DMUB_SEND_DMCUB_CMD; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add DMUB SubVP save surface address to block sequence + */ +void hwss_add_dmub_subvp_save_surf_addr(struct block_sequence_state *seq_state, + struct dc_dmub_srv *dc_dmub_srv, + struct dc_plane_address *addr, + uint8_t subvp_index) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc_dmub_srv; + seq_state->steps[*seq_state->num_steps].params.subvp_save_surf_addr.addr = addr; + seq_state->steps[*seq_state->num_steps].params.subvp_save_surf_addr.subvp_index = subvp_index; + seq_state->steps[*seq_state->num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add HUBP wait for DCC meta propagation to block sequence + */ +void hwss_add_hubp_wait_for_dcc_meta_prop(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *top_pipe_to_program) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = top_pipe_to_program; + seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add HUBP wait pipe read start to block sequence + */ +void hwss_add_hubp_wait_pipe_read_start(struct block_sequence_state *seq_state, + struct hubp *hubp) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.hubp_wait_pipe_read_start_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_PIPE_READ_START; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add HWS apply update flags for phantom to block sequence + */ +void hwss_add_hws_apply_update_flags_for_phantom(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.apply_update_flags_for_phantom_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].func = HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add HWS update phantom VP position to block sequence + */ +void hwss_add_hws_update_phantom_vp_position(struct block_sequence_state *seq_state, + struct dc *dc, + struct dc_state *context, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.context = context; + seq_state->steps[*seq_state->num_steps].params.update_phantom_vp_position_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].func = HWS_UPDATE_PHANTOM_VP_POSITION; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add OPTC set ODM combine to block sequence + */ +void hwss_add_optc_set_odm_combine(struct block_sequence_state *seq_state, + struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count, + int odm_slice_width, int last_odm_slice_width) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.tg = tg; + memcpy(seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.opp_inst, opp_inst, sizeof(int) * MAX_PIPES); + seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.opp_head_count = opp_head_count; + seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.odm_slice_width = odm_slice_width; + seq_state->steps[*seq_state->num_steps].params.set_odm_combine_params.last_odm_slice_width = last_odm_slice_width; + seq_state->steps[*seq_state->num_steps].func = OPTC_SET_ODM_COMBINE; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add OPTC set ODM bypass to block sequence + */ +void hwss_add_optc_set_odm_bypass(struct block_sequence_state *seq_state, + struct timing_generator *tg, struct dc_crtc_timing *timing) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.set_odm_bypass_params.tg = tg; + seq_state->steps[*seq_state->num_steps].params.set_odm_bypass_params.timing = timing; + seq_state->steps[*seq_state->num_steps].func = OPTC_SET_ODM_BYPASS; + (*seq_state->num_steps)++; + } +} + +void hwss_send_dmcub_cmd(union block_sequence_params *params) +{ + struct dc_context *ctx = params->send_dmcub_cmd_params.ctx; + union dmub_rb_cmd *cmd = params->send_dmcub_cmd_params.cmd; + enum dm_dmub_wait_type wait_type = params->send_dmcub_cmd_params.wait_type; + + dc_wake_and_execute_dmub_cmd(ctx, cmd, wait_type); +} + +/** + * Helper function to add TG program global sync to block sequence + */ +void hwss_add_tg_program_global_sync(struct block_sequence_state *seq_state, + struct timing_generator *tg, + int vready_offset, + unsigned int vstartup_lines, + unsigned int vupdate_offset_pixels, + unsigned int vupdate_vupdate_width_pixels, + unsigned int pstate_keepout_start_lines) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.tg = tg; + seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vready_offset = vready_offset; + seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vstartup_lines = vstartup_lines; + seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vupdate_offset_pixels = vupdate_offset_pixels; + seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.vupdate_vupdate_width_pixels = vupdate_vupdate_width_pixels; + seq_state->steps[*seq_state->num_steps].params.tg_program_global_sync_params.pstate_keepout_start_lines = pstate_keepout_start_lines; + seq_state->steps[*seq_state->num_steps].func = TG_PROGRAM_GLOBAL_SYNC; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add TG wait for state to block sequence + */ +void hwss_add_tg_wait_for_state(struct block_sequence_state *seq_state, + struct timing_generator *tg, + enum crtc_state state) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.tg_wait_for_state_params.tg = tg; + seq_state->steps[*seq_state->num_steps].params.tg_wait_for_state_params.state = state; + seq_state->steps[*seq_state->num_steps].func = TG_WAIT_FOR_STATE; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add TG set VTG params to block sequence + */ +void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state, + struct timing_generator *tg, + struct dc_crtc_timing *dc_crtc_timing, + bool program_fp2) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.tg = tg; + seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.timing = dc_crtc_timing; + seq_state->steps[*seq_state->num_steps].params.tg_set_vtg_params_params.program_fp2 = program_fp2; + seq_state->steps[*seq_state->num_steps].func = TG_SET_VTG_PARAMS; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add TG setup vertical interrupt2 to block sequence + */ +void hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state *seq_state, + struct timing_generator *tg, int start_line) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt2_params.tg = tg; + seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt2_params.start_line = start_line; + seq_state->steps[*seq_state->num_steps].func = TG_SETUP_VERTICAL_INTERRUPT2; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add DPP set HDR multiplier to block sequence + */ +void hwss_add_dpp_set_hdr_multiplier(struct block_sequence_state *seq_state, + struct dpp *dpp, uint32_t hw_mult) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.dpp_set_hdr_multiplier_params.dpp = dpp; + seq_state->steps[*seq_state->num_steps].params.dpp_set_hdr_multiplier_params.hw_mult = hw_mult; + seq_state->steps[*seq_state->num_steps].func = DPP_SET_HDR_MULTIPLIER; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add HUBP program DET size to block sequence + */ +void hwss_add_hubp_program_det_size(struct block_sequence_state *seq_state, + struct hubbub *hubbub, + unsigned int hubp_inst, + unsigned int det_buffer_size_kb) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.program_det_size_params.hubbub = hubbub; + seq_state->steps[*seq_state->num_steps].params.program_det_size_params.hubp_inst = hubp_inst; + seq_state->steps[*seq_state->num_steps].params.program_det_size_params.det_buffer_size_kb = det_buffer_size_kb; + seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_DET_SIZE; + (*seq_state->num_steps)++; + } +} + +void hwss_add_hubp_program_mcache_id(struct block_sequence_state *seq_state, + struct hubp *hubp, + struct dml2_hubp_pipe_mcache_regs *mcache_regs) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.program_mcache_id_and_split_coordinate.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.program_mcache_id_and_split_coordinate.mcache_regs = mcache_regs; + seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_MCACHE_ID; + (*seq_state->num_steps)++; + } +} + +void hwss_add_hubbub_force_pstate_change_control(struct block_sequence_state *seq_state, + struct hubbub *hubbub, + bool enable, + bool wait) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.hubbub_force_pstate_change_control_params.hubbub = hubbub; + seq_state->steps[*seq_state->num_steps].params.hubbub_force_pstate_change_control_params.enable = enable; + seq_state->steps[*seq_state->num_steps].params.hubbub_force_pstate_change_control_params.wait = wait; + seq_state->steps[*seq_state->num_steps].func = HUBBUB_FORCE_PSTATE_CHANGE_CONTROL; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add HUBP program DET segments to block sequence + */ +void hwss_add_hubp_program_det_segments(struct block_sequence_state *seq_state, + struct hubbub *hubbub, + unsigned int hubp_inst, + unsigned int det_size) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.program_det_segments_params.hubbub = hubbub; + seq_state->steps[*seq_state->num_steps].params.program_det_segments_params.hubp_inst = hubp_inst; + seq_state->steps[*seq_state->num_steps].params.program_det_segments_params.det_size = det_size; + seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_DET_SEGMENTS; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add OPP set dynamic expansion to block sequence + */ +void hwss_add_opp_set_dyn_expansion(struct block_sequence_state *seq_state, + struct output_pixel_processor *opp, + enum dc_color_space color_space, + enum dc_color_depth color_depth, + enum signal_type signal) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.opp = opp; + seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.color_space = color_space; + seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.color_depth = color_depth; + seq_state->steps[*seq_state->num_steps].params.opp_set_dyn_expansion_params.signal = signal; + seq_state->steps[*seq_state->num_steps].func = OPP_SET_DYN_EXPANSION; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add OPP program FMT to block sequence + */ +void hwss_add_opp_program_fmt(struct block_sequence_state *seq_state, + struct output_pixel_processor *opp, + struct bit_depth_reduction_params *fmt_bit_depth, + struct clamping_and_pixel_encoding_params *clamping) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.opp_program_fmt_params.opp = opp; + seq_state->steps[*seq_state->num_steps].params.opp_program_fmt_params.fmt_bit_depth = fmt_bit_depth; + seq_state->steps[*seq_state->num_steps].params.opp_program_fmt_params.clamping = clamping; + seq_state->steps[*seq_state->num_steps].func = OPP_PROGRAM_FMT; + (*seq_state->num_steps)++; + } +} + +void hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state *seq_state, + struct output_pixel_processor *opp, + enum dc_pixel_encoding pixel_encoding, + bool is_otg_master) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL; + seq_state->steps[*seq_state->num_steps].params.opp_program_left_edge_extra_pixel_params.opp = opp; + seq_state->steps[*seq_state->num_steps].params.opp_program_left_edge_extra_pixel_params.pixel_encoding = pixel_encoding; + seq_state->steps[*seq_state->num_steps].params.opp_program_left_edge_extra_pixel_params.is_otg_master = is_otg_master; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add ABM set pipe to block sequence + */ +void hwss_add_abm_set_pipe(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.set_abm_pipe_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.set_abm_pipe_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].func = ABM_SET_PIPE; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add ABM set level to block sequence + */ +void hwss_add_abm_set_level(struct block_sequence_state *seq_state, + struct abm *abm, + uint32_t abm_level) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.set_abm_level_params.abm = abm; + seq_state->steps[*seq_state->num_steps].params.set_abm_level_params.abm_level = abm_level; + seq_state->steps[*seq_state->num_steps].func = ABM_SET_LEVEL; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add TG enable CRTC to block sequence + */ +void hwss_add_tg_enable_crtc(struct block_sequence_state *seq_state, + struct timing_generator *tg) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.tg_enable_crtc_params.tg = tg; + seq_state->steps[*seq_state->num_steps].func = TG_ENABLE_CRTC; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add HUBP wait flip pending to block sequence + */ +void hwss_add_hubp_wait_flip_pending(struct block_sequence_state *seq_state, + struct hubp *hubp, + unsigned int timeout_us, + unsigned int polling_interval_us) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.timeout_us = timeout_us; + seq_state->steps[*seq_state->num_steps].params.hubp_wait_flip_pending_params.polling_interval_us = polling_interval_us; + seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_FLIP_PENDING; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add TG wait double buffer pending to block sequence + */ +void hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state *seq_state, + struct timing_generator *tg, + unsigned int timeout_us, + unsigned int polling_interval_us) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].params.tg_wait_double_buffer_pending_params.tg = tg; + seq_state->steps[*seq_state->num_steps].params.tg_wait_double_buffer_pending_params.timeout_us = timeout_us; + seq_state->steps[*seq_state->num_steps].params.tg_wait_double_buffer_pending_params.polling_interval_us = polling_interval_us; + seq_state->steps[*seq_state->num_steps].func = TG_WAIT_DOUBLE_BUFFER_PENDING; + (*seq_state->num_steps)++; + } +} + +void hwss_program_manual_trigger(union block_sequence_params *params) +{ + struct pipe_ctx *pipe_ctx = params->program_manual_trigger_params.pipe_ctx; + + if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger) + pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); +} + +void hwss_setup_dpp(union block_sequence_params *params) +{ + struct pipe_ctx *pipe_ctx = params->setup_dpp_params.pipe_ctx; + struct dpp *dpp = pipe_ctx->plane_res.dpp; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; + + if (!plane_state) + return; + + if (dpp && dpp->funcs->dpp_setup) { + // program the input csc + dpp->funcs->dpp_setup(dpp, + plane_state->format, + EXPANSION_MODE_ZERO, + plane_state->input_csc_color_matrix, + plane_state->color_space, + NULL); + } +} + +void hwss_program_bias_and_scale(union block_sequence_params *params) +{ + struct pipe_ctx *pipe_ctx = params->program_bias_and_scale_params.pipe_ctx; + struct dpp *dpp = pipe_ctx->plane_res.dpp; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; + struct dc_bias_and_scale bns_params = plane_state->bias_and_scale; + + //TODO :for CNVC set scale and bias registers if necessary + if (dpp->funcs->dpp_program_bias_and_scale) { + dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); + } +} + +void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params) +{ + struct mpc *mpc = params->power_on_mpc_mem_pwr_params.mpc; + int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id; + bool power_on = params->power_on_mpc_mem_pwr_params.power_on; + + if (mpc->funcs->power_on_mpc_mem_pwr) + mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on); +} + +void hwss_set_output_csc(union block_sequence_params *params) +{ + struct mpc *mpc = params->set_output_csc_params.mpc; + int opp_id = params->set_output_csc_params.opp_id; + const uint16_t *matrix = params->set_output_csc_params.regval; + enum mpc_output_csc_mode ocsc_mode = params->set_output_csc_params.ocsc_mode; + + if (mpc->funcs->set_output_csc != NULL) + mpc->funcs->set_output_csc(mpc, + opp_id, + matrix, + ocsc_mode); +} + +void hwss_set_ocsc_default(union block_sequence_params *params) +{ + struct mpc *mpc = params->set_ocsc_default_params.mpc; + int opp_id = params->set_ocsc_default_params.opp_id; + enum dc_color_space colorspace = params->set_ocsc_default_params.color_space; + enum mpc_output_csc_mode ocsc_mode = params->set_ocsc_default_params.ocsc_mode; + + if (mpc->funcs->set_ocsc_default != NULL) + mpc->funcs->set_ocsc_default(mpc, + opp_id, + colorspace, + ocsc_mode); +} + +void hwss_subvp_save_surf_addr(union block_sequence_params *params) +{ + struct dc_dmub_srv *dc_dmub_srv = params->subvp_save_surf_addr.dc_dmub_srv; + const struct dc_plane_address *addr = params->subvp_save_surf_addr.addr; + uint8_t subvp_index = params->subvp_save_surf_addr.subvp_index; + + dc_dmub_srv_subvp_save_surf_addr(dc_dmub_srv, addr, subvp_index); +} + +void hwss_program_surface_config(union block_sequence_params *params) +{ + struct hubp *hubp = params->program_surface_config_params.hubp; + enum surface_pixel_format format = params->program_surface_config_params.format; + struct dc_tiling_info *tiling_info = params->program_surface_config_params.tiling_info; + struct plane_size size = params->program_surface_config_params.plane_size; + enum dc_rotation_angle rotation = params->program_surface_config_params.rotation; + struct dc_plane_dcc_param *dcc = params->program_surface_config_params.dcc; + bool horizontal_mirror = params->program_surface_config_params.horizontal_mirror; + int compat_level = params->program_surface_config_params.compat_level; + + hubp->funcs->hubp_program_surface_config( + hubp, + format, + tiling_info, + &size, + rotation, + dcc, + horizontal_mirror, + compat_level); + + hubp->power_gated = false; +} + +void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *params) +{ + struct hubp *hubp = params->program_mcache_id_and_split_coordinate.hubp; + struct dml2_hubp_pipe_mcache_regs *mcache_regs = params->program_mcache_id_and_split_coordinate.mcache_regs; + + hubp->funcs->hubp_program_mcache_id_and_split_coordinate(hubp, mcache_regs); + +} + +void get_surface_tile_visual_confirm_color( + struct pipe_ctx *pipe_ctx, + struct tg_color *color) +{ + uint32_t color_value = MAX_TG_COLOR_VALUE; + /* Determine the overscan color based on the bottom-most plane's context */ + struct pipe_ctx *bottom_pipe_ctx = pipe_ctx; + + while (bottom_pipe_ctx->bottom_pipe != NULL) + bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe; + + switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { + case DC_SW_LINEAR: + /* LINEAR Surface - set border color to red */ + color->color_r_cr = color_value; + break; + default: + break; + } +} + +/** + * hwss_wait_for_all_blank_complete - wait for all active OPPs to finish pending blank + * pattern updates + * + * @dc: [in] dc reference + * @context: [in] hardware context in use + */ +void hwss_wait_for_all_blank_complete(struct dc *dc, + struct dc_state *context) +{ + struct pipe_ctx *opp_head; + struct dce_hwseq *hws = dc->hwseq; + int i; + + if (!hws->funcs.wait_for_blank_complete) + return; + + for (i = 0; i < MAX_PIPES; i++) { + opp_head = &context->res_ctx.pipe_ctx[i]; + + if (!resource_is_pipe_type(opp_head, OPP_HEAD) || + dc_state_get_pipe_subvp_type(context, opp_head) == SUBVP_PHANTOM) + continue; + + hws->funcs.wait_for_blank_complete(opp_head->stream_res.opp); + } +} + +void hwss_wait_for_odm_update_pending_complete(struct dc *dc, struct dc_state *context) +{ + struct pipe_ctx *otg_master; + struct timing_generator *tg; + int i; + + for (i = 0; i < MAX_PIPES; i++) { + otg_master = &context->res_ctx.pipe_ctx[i]; + if (!resource_is_pipe_type(otg_master, OTG_MASTER) || + dc_state_get_pipe_subvp_type(context, otg_master) == SUBVP_PHANTOM) + continue; + tg = otg_master->stream_res.tg; + if (tg->funcs->wait_odm_doublebuffer_pending_clear) + tg->funcs->wait_odm_doublebuffer_pending_clear(tg); + if (tg->funcs->wait_otg_disable) + tg->funcs->wait_otg_disable(tg); + } + + /* ODM update may require to reprogram blank pattern for each OPP */ + hwss_wait_for_all_blank_complete(dc, context); +} + +void hwss_wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context) +{ + int i; + for (i = 0; i < MAX_PIPES; i++) { + int count = 0; + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + + if (!pipe->plane_state || dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) + continue; + + /* Timeout 100 ms */ + while (count < 100000) { + /* Must set to false to start with, due to OR in update function */ + pipe->plane_state->status.is_flip_pending = false; + dc->hwss.update_pending_status(pipe); + if (!pipe->plane_state->status.is_flip_pending) + break; + udelay(1); + count++; + } + ASSERT(!pipe->plane_state->status.is_flip_pending); + } +} + +void hwss_wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context) +{ +/* + * This function calls HWSS to wait for any potentially double buffered + * operations to complete. It should be invoked as a pre-amble prior + * to full update programming before asserting any HW locks. + */ + int pipe_idx; + int opp_inst; + int opp_count = dc->res_pool->res_cap->num_opp; + struct hubp *hubp; + int mpcc_inst; + const struct pipe_ctx *pipe_ctx; + + for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { + pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx]; + + if (!pipe_ctx->stream) + continue; + + /* For full update we must wait for all double buffer updates, not just DRR updates. This + * is particularly important for minimal transitions. Only check for OTG_MASTER pipes, + * as non-OTG Master pipes share the same OTG as + */ + if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && dc->hwss.wait_for_all_pending_updates) { + dc->hwss.wait_for_all_pending_updates(pipe_ctx); + } + + hubp = pipe_ctx->plane_res.hubp; + if (!hubp) + continue; + + mpcc_inst = hubp->inst; + // MPCC inst is equal to pipe index in practice + for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { + if ((dc->res_pool->opps[opp_inst] != NULL) && + (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) { + dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); + dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; + break; + } + } + } + hwss_wait_for_odm_update_pending_complete(dc, dc_context); +} + +void hwss_process_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context) +{ + /* wait for outstanding updates */ + hwss_wait_for_outstanding_hw_updates(dc, dc_context); + + /* perform outstanding post update programming */ + if (dc->hwss.program_outstanding_updates) + dc->hwss.program_outstanding_updates(dc, dc_context); +} + +void hwss_set_odm_combine(union block_sequence_params *params) +{ + struct timing_generator *tg = params->set_odm_combine_params.tg; + int *opp_inst = params->set_odm_combine_params.opp_inst; + int opp_head_count = params->set_odm_combine_params.opp_head_count; + int odm_slice_width = params->set_odm_combine_params.odm_slice_width; + int last_odm_slice_width = params->set_odm_combine_params.last_odm_slice_width; + + if (tg && tg->funcs->set_odm_combine) + tg->funcs->set_odm_combine(tg, opp_inst, opp_head_count, + odm_slice_width, last_odm_slice_width); +} + +void hwss_set_odm_bypass(union block_sequence_params *params) +{ + struct timing_generator *tg = params->set_odm_bypass_params.tg; + const struct dc_crtc_timing *timing = params->set_odm_bypass_params.timing; + + if (tg && tg->funcs->set_odm_bypass) + tg->funcs->set_odm_bypass(tg, timing); +} + +void hwss_opp_pipe_clock_control(union block_sequence_params *params) +{ + struct output_pixel_processor *opp = params->opp_pipe_clock_control_params.opp; + bool enable = params->opp_pipe_clock_control_params.enable; + + if (opp && opp->funcs->opp_pipe_clock_control) + opp->funcs->opp_pipe_clock_control(opp, enable); +} + +void hwss_opp_program_left_edge_extra_pixel(union block_sequence_params *params) +{ + struct output_pixel_processor *opp = params->opp_program_left_edge_extra_pixel_params.opp; + enum dc_pixel_encoding pixel_encoding = params->opp_program_left_edge_extra_pixel_params.pixel_encoding; + bool is_otg_master = params->opp_program_left_edge_extra_pixel_params.is_otg_master; + + if (opp && opp->funcs->opp_program_left_edge_extra_pixel) + opp->funcs->opp_program_left_edge_extra_pixel(opp, pixel_encoding, is_otg_master); +} + +void hwss_dccg_set_dto_dscclk(union block_sequence_params *params) +{ + struct dccg *dccg = params->dccg_set_dto_dscclk_params.dccg; + int inst = params->dccg_set_dto_dscclk_params.inst; + int num_slices_h = params->dccg_set_dto_dscclk_params.num_slices_h; + + if (dccg && dccg->funcs->set_dto_dscclk) + dccg->funcs->set_dto_dscclk(dccg, inst, num_slices_h); +} + +void hwss_dsc_set_config(union block_sequence_params *params) +{ + struct display_stream_compressor *dsc = params->dsc_set_config_params.dsc; + struct dsc_config *dsc_cfg = params->dsc_set_config_params.dsc_cfg; + struct dsc_optc_config *dsc_optc_cfg = params->dsc_set_config_params.dsc_optc_cfg; + + if (dsc && dsc->funcs->dsc_set_config) + dsc->funcs->dsc_set_config(dsc, dsc_cfg, dsc_optc_cfg); +} + +void hwss_dsc_enable(union block_sequence_params *params) +{ + struct display_stream_compressor *dsc = params->dsc_enable_params.dsc; + int opp_inst = params->dsc_enable_params.opp_inst; + + if (dsc && dsc->funcs->dsc_enable) + dsc->funcs->dsc_enable(dsc, opp_inst); +} + +void hwss_tg_set_dsc_config(union block_sequence_params *params) +{ + struct timing_generator *tg = params->tg_set_dsc_config_params.tg; + enum optc_dsc_mode optc_dsc_mode = OPTC_DSC_DISABLED; + uint32_t bytes_per_pixel = 0; + uint32_t slice_width = 0; + + if (params->tg_set_dsc_config_params.enable) { + struct dsc_optc_config *dsc_optc_cfg = params->tg_set_dsc_config_params.dsc_optc_cfg; + if (dsc_optc_cfg) { + bytes_per_pixel = dsc_optc_cfg->bytes_per_pixel; + slice_width = dsc_optc_cfg->slice_width; + optc_dsc_mode = dsc_optc_cfg->is_pixel_format_444 ? + OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; + } + } + + if (tg && tg->funcs->set_dsc_config) + tg->funcs->set_dsc_config(tg, optc_dsc_mode, bytes_per_pixel, slice_width); +} + +void hwss_dsc_disconnect(union block_sequence_params *params) +{ + struct display_stream_compressor *dsc = params->dsc_disconnect_params.dsc; + + if (dsc && dsc->funcs->dsc_disconnect) + dsc->funcs->dsc_disconnect(dsc); +} + +void hwss_dsc_read_state(union block_sequence_params *params) +{ + struct display_stream_compressor *dsc = params->dsc_read_state_params.dsc; + struct dcn_dsc_state *dsc_state = params->dsc_read_state_params.dsc_state; + + if (dsc && dsc->funcs->dsc_read_state) + dsc->funcs->dsc_read_state(dsc, dsc_state); +} + +void hwss_dsc_calculate_and_set_config(union block_sequence_params *params) +{ + struct pipe_ctx *pipe_ctx = params->dsc_calculate_and_set_config_params.pipe_ctx; + struct pipe_ctx *top_pipe = pipe_ctx; + bool enable = params->dsc_calculate_and_set_config_params.enable; + int opp_cnt = params->dsc_calculate_and_set_config_params.opp_cnt; + + struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; + struct dc_stream_state *stream = pipe_ctx->stream; + + if (!dsc || !enable) + return; + + /* Calculate DSC configuration - extracted from dcn32_update_dsc_on_stream */ + struct dsc_config dsc_cfg; + + while (top_pipe->prev_odm_pipe) + top_pipe = top_pipe->prev_odm_pipe; + + dsc_cfg.pic_width = (stream->timing.h_addressable + top_pipe->dsc_padding_params.dsc_hactive_padding + + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; + dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; + dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; + dsc_cfg.color_depth = stream->timing.display_color_depth; + dsc_cfg.is_odm = top_pipe->next_odm_pipe ? true : false; + dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; + dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; + dsc_cfg.dsc_padding = top_pipe->dsc_padding_params.dsc_hactive_padding; + + /* Set DSC configuration */ + if (dsc->funcs->dsc_set_config) + dsc->funcs->dsc_set_config(dsc, &dsc_cfg, + ¶ms->dsc_calculate_and_set_config_params.dsc_optc_cfg); +} + +void hwss_dsc_enable_with_opp(union block_sequence_params *params) +{ + struct pipe_ctx *pipe_ctx = params->dsc_enable_with_opp_params.pipe_ctx; + struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; + + if (dsc && dsc->funcs->dsc_enable) + dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); +} + +void hwss_tg_program_global_sync(union block_sequence_params *params) +{ + struct timing_generator *tg = params->tg_program_global_sync_params.tg; + int vready_offset = params->tg_program_global_sync_params.vready_offset; + unsigned int vstartup_lines = params->tg_program_global_sync_params.vstartup_lines; + unsigned int vupdate_offset_pixels = params->tg_program_global_sync_params.vupdate_offset_pixels; + unsigned int vupdate_vupdate_width_pixels = params->tg_program_global_sync_params.vupdate_vupdate_width_pixels; + unsigned int pstate_keepout_start_lines = params->tg_program_global_sync_params.pstate_keepout_start_lines; + + if (tg->funcs->program_global_sync) { + tg->funcs->program_global_sync(tg, vready_offset, vstartup_lines, + vupdate_offset_pixels, vupdate_vupdate_width_pixels, pstate_keepout_start_lines); + } +} + +void hwss_tg_wait_for_state(union block_sequence_params *params) +{ + struct timing_generator *tg = params->tg_wait_for_state_params.tg; + enum crtc_state state = params->tg_wait_for_state_params.state; + + if (tg->funcs->wait_for_state) { + tg->funcs->wait_for_state(tg, state); + } +} + +void hwss_tg_set_vtg_params(union block_sequence_params *params) +{ + struct timing_generator *tg = params->tg_set_vtg_params_params.tg; + struct dc_crtc_timing *timing = params->tg_set_vtg_params_params.timing; + bool program_fp2 = params->tg_set_vtg_params_params.program_fp2; + + if (tg->funcs->set_vtg_params) { + tg->funcs->set_vtg_params(tg, timing, program_fp2); + } +} + +void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params) +{ + struct timing_generator *tg = params->tg_setup_vertical_interrupt2_params.tg; + int start_line = params->tg_setup_vertical_interrupt2_params.start_line; + + if (tg->funcs->setup_vertical_interrupt2) { + tg->funcs->setup_vertical_interrupt2(tg, start_line); + } +} + +void hwss_dpp_set_hdr_multiplier(union block_sequence_params *params) +{ + struct dpp *dpp = params->dpp_set_hdr_multiplier_params.dpp; + uint32_t hw_mult = params->dpp_set_hdr_multiplier_params.hw_mult; + + if (dpp->funcs->dpp_set_hdr_multiplier) { + dpp->funcs->dpp_set_hdr_multiplier(dpp, hw_mult); + } +} + +void hwss_program_det_size(union block_sequence_params *params) +{ + struct hubbub *hubbub = params->program_det_size_params.hubbub; + unsigned int hubp_inst = params->program_det_size_params.hubp_inst; + unsigned int det_buffer_size_kb = params->program_det_size_params.det_buffer_size_kb; + + if (hubbub->funcs->program_det_size) { + hubbub->funcs->program_det_size(hubbub, hubp_inst, det_buffer_size_kb); + } +} + +void hwss_program_det_segments(union block_sequence_params *params) +{ + struct hubbub *hubbub = params->program_det_segments_params.hubbub; + unsigned int hubp_inst = params->program_det_segments_params.hubp_inst; + unsigned int det_size = params->program_det_segments_params.det_size; + + if (hubbub->funcs->program_det_segments) { + hubbub->funcs->program_det_segments(hubbub, hubp_inst, det_size); + } +} + +void hwss_opp_set_dyn_expansion(union block_sequence_params *params) +{ + struct output_pixel_processor *opp = params->opp_set_dyn_expansion_params.opp; + enum dc_color_space color_space = params->opp_set_dyn_expansion_params.color_space; + enum dc_color_depth color_depth = params->opp_set_dyn_expansion_params.color_depth; + enum signal_type signal = params->opp_set_dyn_expansion_params.signal; + + if (opp->funcs->opp_set_dyn_expansion) { + opp->funcs->opp_set_dyn_expansion(opp, color_space, color_depth, signal); + } +} + +void hwss_opp_program_fmt(union block_sequence_params *params) +{ + struct output_pixel_processor *opp = params->opp_program_fmt_params.opp; + struct bit_depth_reduction_params *fmt_bit_depth = params->opp_program_fmt_params.fmt_bit_depth; + struct clamping_and_pixel_encoding_params *clamping = params->opp_program_fmt_params.clamping; + + if (opp->funcs->opp_program_fmt) { + opp->funcs->opp_program_fmt(opp, fmt_bit_depth, clamping); + } +} + +void hwss_opp_program_bit_depth_reduction(union block_sequence_params *params) +{ + struct output_pixel_processor *opp = params->opp_program_bit_depth_reduction_params.opp; + bool use_default_params = params->opp_program_bit_depth_reduction_params.use_default_params; + struct pipe_ctx *pipe_ctx = params->opp_program_bit_depth_reduction_params.pipe_ctx; + struct bit_depth_reduction_params bit_depth_params; + + if (use_default_params) { + memset(&bit_depth_params, 0, sizeof(bit_depth_params)); + } else { + resource_build_bit_depth_reduction_params(pipe_ctx->stream, &bit_depth_params); + } + + if (opp->funcs->opp_program_bit_depth_reduction) { + opp->funcs->opp_program_bit_depth_reduction(opp, &bit_depth_params); + } +} + +void hwss_opp_set_disp_pattern_generator(union block_sequence_params *params) +{ + struct output_pixel_processor *opp = params->opp_set_disp_pattern_generator_params.opp; + enum controller_dp_test_pattern test_pattern = params->opp_set_disp_pattern_generator_params.test_pattern; + enum controller_dp_color_space color_space = params->opp_set_disp_pattern_generator_params.color_space; + enum dc_color_depth color_depth = params->opp_set_disp_pattern_generator_params.color_depth; + struct tg_color *solid_color = params->opp_set_disp_pattern_generator_params.use_solid_color ? + ¶ms->opp_set_disp_pattern_generator_params.solid_color : NULL; + int width = params->opp_set_disp_pattern_generator_params.width; + int height = params->opp_set_disp_pattern_generator_params.height; + int offset = params->opp_set_disp_pattern_generator_params.offset; + + if (opp && opp->funcs->opp_set_disp_pattern_generator) { + opp->funcs->opp_set_disp_pattern_generator(opp, test_pattern, color_space, + color_depth, solid_color, width, height, offset); + } +} + +void hwss_set_abm_pipe(union block_sequence_params *params) +{ + struct dc *dc = params->set_abm_pipe_params.dc; + struct pipe_ctx *pipe_ctx = params->set_abm_pipe_params.pipe_ctx; + + dc->hwss.set_pipe(pipe_ctx); +} + +void hwss_set_abm_level(union block_sequence_params *params) +{ + struct abm *abm = params->set_abm_level_params.abm; + unsigned int abm_level = params->set_abm_level_params.abm_level; + + if (abm->funcs->set_abm_level) { + abm->funcs->set_abm_level(abm, abm_level); + } +} + +void hwss_set_abm_immediate_disable(union block_sequence_params *params) +{ + struct dc *dc = params->set_abm_immediate_disable_params.dc; + struct pipe_ctx *pipe_ctx = params->set_abm_immediate_disable_params.pipe_ctx; + + if (dc && dc->hwss.set_abm_immediate_disable) { + dc->hwss.set_abm_immediate_disable(pipe_ctx); + } +} + +void hwss_mpc_remove_mpcc(union block_sequence_params *params) +{ + struct mpc *mpc = params->mpc_remove_mpcc_params.mpc; + struct mpc_tree *mpc_tree_params = params->mpc_remove_mpcc_params.mpc_tree_params; + struct mpcc *mpcc_to_remove = params->mpc_remove_mpcc_params.mpcc_to_remove; + + mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove); +} + +void hwss_opp_set_mpcc_disconnect_pending(union block_sequence_params *params) +{ + struct output_pixel_processor *opp = params->opp_set_mpcc_disconnect_pending_params.opp; + int mpcc_inst = params->opp_set_mpcc_disconnect_pending_params.mpcc_inst; + bool pending = params->opp_set_mpcc_disconnect_pending_params.pending; + + opp->mpcc_disconnect_pending[mpcc_inst] = pending; +} + +void hwss_dc_set_optimized_required(union block_sequence_params *params) +{ + struct dc *dc = params->dc_set_optimized_required_params.dc; + bool optimized_required = params->dc_set_optimized_required_params.optimized_required; + + dc->optimized_required = optimized_required; +} + +void hwss_hubp_disconnect(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_disconnect_params.hubp; + + if (hubp->funcs->hubp_disconnect) + hubp->funcs->hubp_disconnect(hubp); +} + +void hwss_hubbub_force_pstate_change_control(union block_sequence_params *params) +{ + struct hubbub *hubbub = params->hubbub_force_pstate_change_control_params.hubbub; + bool enable = params->hubbub_force_pstate_change_control_params.enable; + bool wait = params->hubbub_force_pstate_change_control_params.wait; + + if (hubbub->funcs->force_pstate_change_control) { + hubbub->funcs->force_pstate_change_control(hubbub, enable, wait); + /* Add delay when enabling pstate change control */ + if (enable) + udelay(500); + } +} + +void hwss_tg_enable_crtc(union block_sequence_params *params) +{ + struct timing_generator *tg = params->tg_enable_crtc_params.tg; + + if (tg->funcs->enable_crtc) + tg->funcs->enable_crtc(tg); +} + +void hwss_tg_set_gsl(union block_sequence_params *params) +{ + struct timing_generator *tg = params->tg_set_gsl_params.tg; + struct gsl_params *gsl = ¶ms->tg_set_gsl_params.gsl; + + if (tg->funcs->set_gsl) + tg->funcs->set_gsl(tg, gsl); +} + +void hwss_tg_set_gsl_source_select(union block_sequence_params *params) +{ + struct timing_generator *tg = params->tg_set_gsl_source_select_params.tg; + int group_idx = params->tg_set_gsl_source_select_params.group_idx; + uint32_t gsl_ready_signal = params->tg_set_gsl_source_select_params.gsl_ready_signal; + + if (tg->funcs->set_gsl_source_select) + tg->funcs->set_gsl_source_select(tg, group_idx, gsl_ready_signal); +} + +void hwss_hubp_wait_flip_pending(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_wait_flip_pending_params.hubp; + unsigned int timeout_us = params->hubp_wait_flip_pending_params.timeout_us; + unsigned int polling_interval_us = params->hubp_wait_flip_pending_params.polling_interval_us; + int j = 0; + + for (j = 0; j < timeout_us / polling_interval_us + && hubp->funcs->hubp_is_flip_pending(hubp); j++) + udelay(polling_interval_us); +} + +void hwss_tg_wait_double_buffer_pending(union block_sequence_params *params) +{ + struct timing_generator *tg = params->tg_wait_double_buffer_pending_params.tg; + unsigned int timeout_us = params->tg_wait_double_buffer_pending_params.timeout_us; + unsigned int polling_interval_us = params->tg_wait_double_buffer_pending_params.polling_interval_us; + int j = 0; + + if (tg->funcs->get_optc_double_buffer_pending) { + for (j = 0; j < timeout_us / polling_interval_us + && tg->funcs->get_optc_double_buffer_pending(tg); j++) + udelay(polling_interval_us); + } +} + +void hwss_update_force_pstate(union block_sequence_params *params) +{ + struct dc *dc = params->update_force_pstate_params.dc; + struct dc_state *context = params->update_force_pstate_params.context; + struct dce_hwseq *hwseq = dc->hwseq; + + if (hwseq->funcs.update_force_pstate) + hwseq->funcs.update_force_pstate(dc, context); +} + +void hwss_hubbub_apply_dedcn21_147_wa(union block_sequence_params *params) +{ + struct hubbub *hubbub = params->hubbub_apply_dedcn21_147_wa_params.hubbub; + + hubbub->funcs->apply_DEDCN21_147_wa(hubbub); +} + +void hwss_hubbub_allow_self_refresh_control(union block_sequence_params *params) +{ + struct hubbub *hubbub = params->hubbub_allow_self_refresh_control_params.hubbub; + bool allow = params->hubbub_allow_self_refresh_control_params.allow; + + hubbub->funcs->allow_self_refresh_control(hubbub, allow); + + if (!allow && params->hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied) + *params->hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied = true; +} + +void hwss_tg_get_frame_count(union block_sequence_params *params) +{ + struct timing_generator *tg = params->tg_get_frame_count_params.tg; + unsigned int *frame_count = params->tg_get_frame_count_params.frame_count; + + *frame_count = tg->funcs->get_frame_count(tg); +} + +void hwss_mpc_set_dwb_mux(union block_sequence_params *params) +{ + struct mpc *mpc = params->mpc_set_dwb_mux_params.mpc; + int dwb_id = params->mpc_set_dwb_mux_params.dwb_id; + int mpcc_id = params->mpc_set_dwb_mux_params.mpcc_id; + + if (mpc->funcs->set_dwb_mux) + mpc->funcs->set_dwb_mux(mpc, dwb_id, mpcc_id); +} + +void hwss_mpc_disable_dwb_mux(union block_sequence_params *params) +{ + struct mpc *mpc = params->mpc_disable_dwb_mux_params.mpc; + unsigned int dwb_id = params->mpc_disable_dwb_mux_params.dwb_id; + + if (mpc->funcs->disable_dwb_mux) + mpc->funcs->disable_dwb_mux(mpc, dwb_id); +} + +void hwss_mcif_wb_config_buf(union block_sequence_params *params) +{ + struct mcif_wb *mcif_wb = params->mcif_wb_config_buf_params.mcif_wb; + struct mcif_buf_params *mcif_buf_params = params->mcif_wb_config_buf_params.mcif_buf_params; + unsigned int dest_height = params->mcif_wb_config_buf_params.dest_height; + + if (mcif_wb->funcs->config_mcif_buf) + mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, dest_height); +} + +void hwss_mcif_wb_config_arb(union block_sequence_params *params) +{ + struct mcif_wb *mcif_wb = params->mcif_wb_config_arb_params.mcif_wb; + struct mcif_arb_params *mcif_arb_params = params->mcif_wb_config_arb_params.mcif_arb_params; + + if (mcif_wb->funcs->config_mcif_arb) + mcif_wb->funcs->config_mcif_arb(mcif_wb, mcif_arb_params); +} + +void hwss_mcif_wb_enable(union block_sequence_params *params) +{ + struct mcif_wb *mcif_wb = params->mcif_wb_enable_params.mcif_wb; + + if (mcif_wb->funcs->enable_mcif) + mcif_wb->funcs->enable_mcif(mcif_wb); +} + +void hwss_mcif_wb_disable(union block_sequence_params *params) +{ + struct mcif_wb *mcif_wb = params->mcif_wb_disable_params.mcif_wb; + + if (mcif_wb->funcs->disable_mcif) + mcif_wb->funcs->disable_mcif(mcif_wb); +} + +void hwss_dwbc_enable(union block_sequence_params *params) +{ + struct dwbc *dwb = params->dwbc_enable_params.dwb; + struct dc_dwb_params *dwb_params = params->dwbc_enable_params.dwb_params; + + if (dwb->funcs->enable) + dwb->funcs->enable(dwb, dwb_params); +} + +void hwss_dwbc_disable(union block_sequence_params *params) +{ + struct dwbc *dwb = params->dwbc_disable_params.dwb; + + if (dwb->funcs->disable) + dwb->funcs->disable(dwb); +} + +void hwss_dwbc_update(union block_sequence_params *params) +{ + struct dwbc *dwb = params->dwbc_update_params.dwb; + struct dc_dwb_params *dwb_params = params->dwbc_update_params.dwb_params; + + if (dwb->funcs->update) + dwb->funcs->update(dwb, dwb_params); +} + +void hwss_hubp_update_mall_sel(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_update_mall_sel_params.hubp; + uint32_t mall_sel = params->hubp_update_mall_sel_params.mall_sel; + bool cache_cursor = params->hubp_update_mall_sel_params.cache_cursor; + + if (hubp && hubp->funcs->hubp_update_mall_sel) + hubp->funcs->hubp_update_mall_sel(hubp, mall_sel, cache_cursor); +} + +void hwss_hubp_prepare_subvp_buffering(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_prepare_subvp_buffering_params.hubp; + bool enable = params->hubp_prepare_subvp_buffering_params.enable; + + if (hubp && hubp->funcs->hubp_prepare_subvp_buffering) + hubp->funcs->hubp_prepare_subvp_buffering(hubp, enable); +} + +void hwss_hubp_set_blank_en(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_set_blank_en_params.hubp; + bool enable = params->hubp_set_blank_en_params.enable; + + if (hubp && hubp->funcs->set_hubp_blank_en) + hubp->funcs->set_hubp_blank_en(hubp, enable); +} + +void hwss_hubp_disable_control(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_disable_control_params.hubp; + bool disable = params->hubp_disable_control_params.disable; + + if (hubp && hubp->funcs->hubp_disable_control) + hubp->funcs->hubp_disable_control(hubp, disable); +} + +void hwss_hubbub_soft_reset(union block_sequence_params *params) +{ + struct hubbub *hubbub = params->hubbub_soft_reset_params.hubbub; + bool reset = params->hubbub_soft_reset_params.reset; + + if (hubbub) + params->hubbub_soft_reset_params.hubbub_soft_reset(hubbub, reset); +} + +void hwss_hubp_clk_cntl(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_clk_cntl_params.hubp; + bool enable = params->hubp_clk_cntl_params.enable; + + if (hubp && hubp->funcs->hubp_clk_cntl) { + hubp->funcs->hubp_clk_cntl(hubp, enable); + hubp->power_gated = !enable; + } +} + +void hwss_hubp_init(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_init_params.hubp; + + if (hubp && hubp->funcs->hubp_init) { + hubp->funcs->hubp_init(hubp); + } +} + +void hwss_hubp_set_vm_system_aperture_settings(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_set_vm_system_aperture_settings_params.hubp; + //struct vm_system_aperture_param *apt = ¶ms->hubp_set_vm_system_aperture_settings_params.apt; + struct vm_system_aperture_param apt; + + apt.sys_default = params->hubp_set_vm_system_aperture_settings_params.sys_default; + apt.sys_high = params->hubp_set_vm_system_aperture_settings_params.sys_high; + apt.sys_low = params->hubp_set_vm_system_aperture_settings_params.sys_low; + + if (hubp && hubp->funcs->hubp_set_vm_system_aperture_settings) { + //hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, apt); + hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt); + } +} + +void hwss_hubp_set_flip_int(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_set_flip_int_params.hubp; + + if (hubp && hubp->funcs->hubp_set_flip_int) { + hubp->funcs->hubp_set_flip_int(hubp); + } +} + +void hwss_dpp_dppclk_control(union block_sequence_params *params) +{ + struct dpp *dpp = params->dpp_dppclk_control_params.dpp; + bool dppclk_div = params->dpp_dppclk_control_params.dppclk_div; + bool enable = params->dpp_dppclk_control_params.enable; + + if (dpp && dpp->funcs->dpp_dppclk_control) + dpp->funcs->dpp_dppclk_control(dpp, dppclk_div, enable); +} + +void hwss_disable_phantom_crtc(union block_sequence_params *params) +{ + struct timing_generator *tg = params->disable_phantom_crtc_params.tg; + + if (tg && tg->funcs->disable_phantom_crtc) + tg->funcs->disable_phantom_crtc(tg); +} + +void hwss_dsc_pg_status(union block_sequence_params *params) +{ + struct dce_hwseq *hws = params->dsc_pg_status_params.hws; + int dsc_inst = params->dsc_pg_status_params.dsc_inst; + + if (hws && hws->funcs.dsc_pg_status) + params->dsc_pg_status_params.is_ungated = hws->funcs.dsc_pg_status(hws, dsc_inst); +} + +void hwss_dsc_wait_disconnect_pending_clear(union block_sequence_params *params) +{ + struct display_stream_compressor *dsc = params->dsc_wait_disconnect_pending_clear_params.dsc; + + if (!params->dsc_wait_disconnect_pending_clear_params.is_ungated) + return; + if (*params->dsc_wait_disconnect_pending_clear_params.is_ungated == false) + return; + + if (dsc && dsc->funcs->dsc_wait_disconnect_pending_clear) + dsc->funcs->dsc_wait_disconnect_pending_clear(dsc); +} + +void hwss_dsc_disable(union block_sequence_params *params) +{ + struct display_stream_compressor *dsc = params->dsc_disable_params.dsc; + + if (!params->dsc_disable_params.is_ungated) + return; + if (*params->dsc_disable_params.is_ungated == false) + return; + + if (dsc && dsc->funcs->dsc_disable) + dsc->funcs->dsc_disable(dsc); +} + +void hwss_dccg_set_ref_dscclk(union block_sequence_params *params) +{ + struct dccg *dccg = params->dccg_set_ref_dscclk_params.dccg; + int dsc_inst = params->dccg_set_ref_dscclk_params.dsc_inst; + + if (!params->dccg_set_ref_dscclk_params.is_ungated) + return; + if (*params->dccg_set_ref_dscclk_params.is_ungated == false) + return; + + if (dccg && dccg->funcs->set_ref_dscclk) + dccg->funcs->set_ref_dscclk(dccg, dsc_inst); +} + +void hwss_dpp_pg_control(union block_sequence_params *params) +{ + struct dce_hwseq *hws = params->dpp_pg_control_params.hws; + unsigned int dpp_inst = params->dpp_pg_control_params.dpp_inst; + bool power_on = params->dpp_pg_control_params.power_on; + + if (hws->funcs.dpp_pg_control) + hws->funcs.dpp_pg_control(hws, dpp_inst, power_on); +} + +void hwss_hubp_pg_control(union block_sequence_params *params) +{ + struct dce_hwseq *hws = params->hubp_pg_control_params.hws; + unsigned int hubp_inst = params->hubp_pg_control_params.hubp_inst; + bool power_on = params->hubp_pg_control_params.power_on; + + if (hws->funcs.hubp_pg_control) + hws->funcs.hubp_pg_control(hws, hubp_inst, power_on); +} + +void hwss_hubp_reset(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_reset_params.hubp; + + if (hubp && hubp->funcs->hubp_reset) + hubp->funcs->hubp_reset(hubp); +} + +void hwss_dpp_reset(union block_sequence_params *params) +{ + struct dpp *dpp = params->dpp_reset_params.dpp; + + if (dpp && dpp->funcs->dpp_reset) + dpp->funcs->dpp_reset(dpp); +} + +void hwss_dpp_root_clock_control(union block_sequence_params *params) +{ + struct dce_hwseq *hws = params->dpp_root_clock_control_params.hws; + unsigned int dpp_inst = params->dpp_root_clock_control_params.dpp_inst; + bool clock_on = params->dpp_root_clock_control_params.clock_on; + + if (hws->funcs.dpp_root_clock_control) + hws->funcs.dpp_root_clock_control(hws, dpp_inst, clock_on); +} + +void hwss_dc_ip_request_cntl(union block_sequence_params *params) +{ + struct dc *dc = params->dc_ip_request_cntl_params.dc; + bool enable = params->dc_ip_request_cntl_params.enable; + struct dce_hwseq *hws = dc->hwseq; + + if (hws->funcs.dc_ip_request_cntl) + hws->funcs.dc_ip_request_cntl(dc, enable); +} + +void hwss_dccg_update_dpp_dto(union block_sequence_params *params) +{ + struct dccg *dccg = params->dccg_update_dpp_dto_params.dccg; + int dpp_inst = params->dccg_update_dpp_dto_params.dpp_inst; + int dppclk_khz = params->dccg_update_dpp_dto_params.dppclk_khz; + + if (dccg && dccg->funcs->update_dpp_dto) + dccg->funcs->update_dpp_dto(dccg, dpp_inst, dppclk_khz); +} + +void hwss_hubp_vtg_sel(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_vtg_sel_params.hubp; + uint32_t otg_inst = params->hubp_vtg_sel_params.otg_inst; + + if (hubp && hubp->funcs->hubp_vtg_sel) + hubp->funcs->hubp_vtg_sel(hubp, otg_inst); +} + +void hwss_hubp_setup2(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_setup2_params.hubp; + struct dml2_dchub_per_pipe_register_set *hubp_regs = params->hubp_setup2_params.hubp_regs; + union dml2_global_sync_programming *global_sync = params->hubp_setup2_params.global_sync; + struct dc_crtc_timing *timing = params->hubp_setup2_params.timing; + + if (hubp && hubp->funcs->hubp_setup2) + hubp->funcs->hubp_setup2(hubp, hubp_regs, global_sync, timing); +} + +void hwss_hubp_setup(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_setup_params.hubp; + struct _vcs_dpi_display_dlg_regs_st *dlg_regs = params->hubp_setup_params.dlg_regs; + struct _vcs_dpi_display_ttu_regs_st *ttu_regs = params->hubp_setup_params.ttu_regs; + struct _vcs_dpi_display_rq_regs_st *rq_regs = params->hubp_setup_params.rq_regs; + struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest = params->hubp_setup_params.pipe_dest; + + if (hubp && hubp->funcs->hubp_setup) + hubp->funcs->hubp_setup(hubp, dlg_regs, ttu_regs, rq_regs, pipe_dest); +} + +void hwss_hubp_set_unbounded_requesting(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_set_unbounded_requesting_params.hubp; + bool unbounded_req = params->hubp_set_unbounded_requesting_params.unbounded_req; + + if (hubp && hubp->funcs->set_unbounded_requesting) + hubp->funcs->set_unbounded_requesting(hubp, unbounded_req); +} + +void hwss_hubp_setup_interdependent2(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_setup_interdependent2_params.hubp; + struct dml2_dchub_per_pipe_register_set *hubp_regs = params->hubp_setup_interdependent2_params.hubp_regs; + + if (hubp && hubp->funcs->hubp_setup_interdependent2) + hubp->funcs->hubp_setup_interdependent2(hubp, hubp_regs); +} + +void hwss_hubp_setup_interdependent(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_setup_interdependent_params.hubp; + struct _vcs_dpi_display_dlg_regs_st *dlg_regs = params->hubp_setup_interdependent_params.dlg_regs; + struct _vcs_dpi_display_ttu_regs_st *ttu_regs = params->hubp_setup_interdependent_params.ttu_regs; + + if (hubp && hubp->funcs->hubp_setup_interdependent) + hubp->funcs->hubp_setup_interdependent(hubp, dlg_regs, ttu_regs); +} + +void hwss_dpp_set_cursor_matrix(union block_sequence_params *params) +{ + struct dpp *dpp = params->dpp_set_cursor_matrix_params.dpp; + enum dc_color_space color_space = params->dpp_set_cursor_matrix_params.color_space; + struct dc_csc_transform *cursor_csc_color_matrix = params->dpp_set_cursor_matrix_params.cursor_csc_color_matrix; + + if (dpp && dpp->funcs->set_cursor_matrix) + dpp->funcs->set_cursor_matrix(dpp, color_space, *cursor_csc_color_matrix); +} + +void hwss_mpc_update_mpcc(union block_sequence_params *params) +{ + struct dc *dc = params->mpc_update_mpcc_params.dc; + struct pipe_ctx *pipe_ctx = params->mpc_update_mpcc_params.pipe_ctx; + struct dce_hwseq *hws = dc->hwseq; + + if (hws->funcs.update_mpcc) + hws->funcs.update_mpcc(dc, pipe_ctx); +} + +void hwss_mpc_update_blending(union block_sequence_params *params) +{ + struct mpc *mpc = params->mpc_update_blending_params.mpc; + struct mpcc_blnd_cfg *blnd_cfg = ¶ms->mpc_update_blending_params.blnd_cfg; + int mpcc_id = params->mpc_update_blending_params.mpcc_id; + + if (mpc && mpc->funcs->update_blending) + mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id); +} + +void hwss_mpc_assert_idle_mpcc(union block_sequence_params *params) +{ + struct mpc *mpc = params->mpc_assert_idle_mpcc_params.mpc; + //struct pipe_ctx *pipe_ctx = params->mpc_assert_idle_mpcc_params.pipe_ctx; + int mpcc_id = params->mpc_assert_idle_mpcc_params.mpcc_id; + + if (mpc && mpc->funcs->wait_for_idle) + mpc->funcs->wait_for_idle(mpc, mpcc_id); + + //pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_id] = false; +} + +void hwss_mpc_insert_plane(union block_sequence_params *params) +{ + struct mpc *mpc = params->mpc_insert_plane_params.mpc; + struct mpc_tree *tree = params->mpc_insert_plane_params.mpc_tree_params; + struct mpcc_blnd_cfg *blnd_cfg = ¶ms->mpc_insert_plane_params.blnd_cfg; + struct mpcc_sm_cfg *sm_cfg = params->mpc_insert_plane_params.sm_cfg; + struct mpcc *insert_above_mpcc = params->mpc_insert_plane_params.insert_above_mpcc; + int mpcc_id = params->mpc_insert_plane_params.mpcc_id; + int dpp_id = params->mpc_insert_plane_params.dpp_id; + + if (mpc && mpc->funcs->insert_plane) + mpc->funcs->insert_plane(mpc, tree, blnd_cfg, sm_cfg, insert_above_mpcc, + dpp_id, mpcc_id); +} + +void hwss_dpp_set_scaler(union block_sequence_params *params) +{ + struct dpp *dpp = params->dpp_set_scaler_params.dpp; + const struct scaler_data *scl_data = params->dpp_set_scaler_params.scl_data; + + if (dpp && dpp->funcs->dpp_set_scaler) + dpp->funcs->dpp_set_scaler(dpp, scl_data); +} + +void hwss_hubp_mem_program_viewport(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_mem_program_viewport_params.hubp; + const struct rect *viewport = params->hubp_mem_program_viewport_params.viewport; + const struct rect *viewport_c = params->hubp_mem_program_viewport_params.viewport_c; + + if (hubp && hubp->funcs->mem_program_viewport) + hubp->funcs->mem_program_viewport(hubp, viewport, viewport_c); +} + +void hwss_set_cursor_attribute(union block_sequence_params *params) +{ + struct dc *dc = params->set_cursor_attribute_params.dc; + struct pipe_ctx *pipe_ctx = params->set_cursor_attribute_params.pipe_ctx; + + if (dc && dc->hwss.set_cursor_attribute) + dc->hwss.set_cursor_attribute(pipe_ctx); +} + +void hwss_set_cursor_position(union block_sequence_params *params) +{ + struct dc *dc = params->set_cursor_position_params.dc; + struct pipe_ctx *pipe_ctx = params->set_cursor_position_params.pipe_ctx; + + if (dc && dc->hwss.set_cursor_position) + dc->hwss.set_cursor_position(pipe_ctx); +} + +void hwss_set_cursor_sdr_white_level(union block_sequence_params *params) +{ + struct dc *dc = params->set_cursor_sdr_white_level_params.dc; + struct pipe_ctx *pipe_ctx = params->set_cursor_sdr_white_level_params.pipe_ctx; + + if (dc && dc->hwss.set_cursor_sdr_white_level) + dc->hwss.set_cursor_sdr_white_level(pipe_ctx); +} + +void hwss_program_output_csc(union block_sequence_params *params) +{ + struct dc *dc = params->program_output_csc_params.dc; + struct pipe_ctx *pipe_ctx = params->program_output_csc_params.pipe_ctx; + enum dc_color_space colorspace = params->program_output_csc_params.colorspace; + uint16_t *matrix = params->program_output_csc_params.matrix; + int opp_id = params->program_output_csc_params.opp_id; + + if (dc && dc->hwss.program_output_csc) + dc->hwss.program_output_csc(dc, pipe_ctx, colorspace, matrix, opp_id); +} + +void hwss_hubp_set_blank(union block_sequence_params *params) +{ + struct hubp *hubp = params->hubp_set_blank_params.hubp; + bool blank = params->hubp_set_blank_params.blank; + + if (hubp && hubp->funcs->set_blank) + hubp->funcs->set_blank(hubp, blank); +} + +void hwss_phantom_hubp_post_enable(union block_sequence_params *params) +{ + struct hubp *hubp = params->phantom_hubp_post_enable_params.hubp; + + if (hubp && hubp->funcs->phantom_hubp_post_enable) + hubp->funcs->phantom_hubp_post_enable(hubp); +} + +void hwss_add_dccg_set_dto_dscclk(struct block_sequence_state *seq_state, + struct dccg *dccg, int inst, int num_slices_h) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DCCG_SET_DTO_DSCCLK; + seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.dccg = dccg; + seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.inst = inst; + seq_state->steps[*seq_state->num_steps].params.dccg_set_dto_dscclk_params.num_slices_h = num_slices_h; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dsc_calculate_and_set_config(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx, bool enable, int opp_cnt) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DSC_CALCULATE_AND_SET_CONFIG; + seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.enable = enable; + seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.opp_cnt = opp_cnt; + (*seq_state->num_steps)++; + } +} + +void hwss_add_mpc_remove_mpcc(struct block_sequence_state *seq_state, + struct mpc *mpc, struct mpc_tree *mpc_tree_params, struct mpcc *mpcc_to_remove) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = MPC_REMOVE_MPCC; + seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpc = mpc; + seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpc_tree_params = mpc_tree_params; + seq_state->steps[*seq_state->num_steps].params.mpc_remove_mpcc_params.mpcc_to_remove = mpcc_to_remove; + (*seq_state->num_steps)++; + } +} + +void hwss_add_opp_set_mpcc_disconnect_pending(struct block_sequence_state *seq_state, + struct output_pixel_processor *opp, int mpcc_inst, bool pending) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = OPP_SET_MPCC_DISCONNECT_PENDING; + seq_state->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.opp = opp; + seq_state->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.mpcc_inst = mpcc_inst; + seq_state->steps[*seq_state->num_steps].params.opp_set_mpcc_disconnect_pending_params.pending = pending; + (*seq_state->num_steps)++; + } +} + +void hwss_add_hubp_disconnect(struct block_sequence_state *seq_state, + struct hubp *hubp) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_DISCONNECT; + seq_state->steps[*seq_state->num_steps].params.hubp_disconnect_params.hubp = hubp; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dsc_enable_with_opp(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DSC_ENABLE_WITH_OPP; + seq_state->steps[*seq_state->num_steps].params.dsc_enable_with_opp_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_tg_set_dsc_config(struct block_sequence_state *seq_state, + struct timing_generator *tg, struct dsc_optc_config *dsc_optc_cfg, bool enable) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = TG_SET_DSC_CONFIG; + seq_state->steps[*seq_state->num_steps].params.tg_set_dsc_config_params.tg = tg; + seq_state->steps[*seq_state->num_steps].params.tg_set_dsc_config_params.dsc_optc_cfg = dsc_optc_cfg; + seq_state->steps[*seq_state->num_steps].params.tg_set_dsc_config_params.enable = enable; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dsc_disconnect(struct block_sequence_state *seq_state, + struct display_stream_compressor *dsc) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DSC_DISCONNECT; + seq_state->steps[*seq_state->num_steps].params.dsc_disconnect_params.dsc = dsc; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dc_set_optimized_required(struct block_sequence_state *seq_state, + struct dc *dc, bool optimized_required) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DC_SET_OPTIMIZED_REQUIRED; + seq_state->steps[*seq_state->num_steps].params.dc_set_optimized_required_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.dc_set_optimized_required_params.optimized_required = optimized_required; + (*seq_state->num_steps)++; + } +} + +void hwss_add_abm_set_immediate_disable(struct block_sequence_state *seq_state, + struct dc *dc, struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = ABM_SET_IMMEDIATE_DISABLE; + seq_state->steps[*seq_state->num_steps].params.set_abm_immediate_disable_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.set_abm_immediate_disable_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_opp_set_disp_pattern_generator(struct block_sequence_state *seq_state, + struct output_pixel_processor *opp, + enum controller_dp_test_pattern test_pattern, + enum controller_dp_color_space color_space, + enum dc_color_depth color_depth, + struct tg_color solid_color, + bool use_solid_color, + int width, + int height, + int offset) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = OPP_SET_DISP_PATTERN_GENERATOR; + seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.opp = opp; + seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.test_pattern = test_pattern; + seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.color_space = color_space; + seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.color_depth = color_depth; + seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.solid_color = solid_color; + seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.use_solid_color = use_solid_color; + seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.width = width; + seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.height = height; + seq_state->steps[*seq_state->num_steps].params.opp_set_disp_pattern_generator_params.offset = offset; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add MPC update blending to block sequence + */ +void hwss_add_mpc_update_blending(struct block_sequence_state *seq_state, + struct mpc *mpc, + struct mpcc_blnd_cfg blnd_cfg, + int mpcc_id) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = MPC_UPDATE_BLENDING; + seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.mpc = mpc; + seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.blnd_cfg = blnd_cfg; + seq_state->steps[*seq_state->num_steps].params.mpc_update_blending_params.mpcc_id = mpcc_id; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add MPC insert plane to block sequence + */ +void hwss_add_mpc_insert_plane(struct block_sequence_state *seq_state, + struct mpc *mpc, + struct mpc_tree *mpc_tree_params, + struct mpcc_blnd_cfg blnd_cfg, + struct mpcc_sm_cfg *sm_cfg, + struct mpcc *insert_above_mpcc, + int dpp_id, + int mpcc_id) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = MPC_INSERT_PLANE; + seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpc = mpc; + seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpc_tree_params = mpc_tree_params; + seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.blnd_cfg = blnd_cfg; + seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.sm_cfg = sm_cfg; + seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.insert_above_mpcc = insert_above_mpcc; + seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.dpp_id = dpp_id; + seq_state->steps[*seq_state->num_steps].params.mpc_insert_plane_params.mpcc_id = mpcc_id; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add MPC assert idle MPCC to block sequence + */ +void hwss_add_mpc_assert_idle_mpcc(struct block_sequence_state *seq_state, + struct mpc *mpc, + int mpcc_id) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = MPC_ASSERT_IDLE_MPCC; + seq_state->steps[*seq_state->num_steps].params.mpc_assert_idle_mpcc_params.mpc = mpc; + seq_state->steps[*seq_state->num_steps].params.mpc_assert_idle_mpcc_params.mpcc_id = mpcc_id; + (*seq_state->num_steps)++; + } +} + +/** + * Helper function to add HUBP set blank to block sequence + */ +void hwss_add_hubp_set_blank(struct block_sequence_state *seq_state, + struct hubp *hubp, + bool blank) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_SET_BLANK; + seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_params.blank = blank; + (*seq_state->num_steps)++; + } +} + +void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_state, + struct output_pixel_processor *opp, + bool use_default_params, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = OPP_PROGRAM_BIT_DEPTH_REDUCTION; + seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.opp = opp; + seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.use_default_params = use_default_params; + seq_state->steps[*seq_state->num_steps].params.opp_program_bit_depth_reduction_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state, + struct dc *dc, + bool enable) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DC_IP_REQUEST_CNTL; + seq_state->steps[*seq_state->num_steps].params.dc_ip_request_cntl_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.dc_ip_request_cntl_params.enable = enable; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dwbc_update(struct block_sequence_state *seq_state, + struct dwbc *dwb, + struct dc_dwb_params *dwb_params) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DWBC_UPDATE; + seq_state->steps[*seq_state->num_steps].params.dwbc_update_params.dwb = dwb; + seq_state->steps[*seq_state->num_steps].params.dwbc_update_params.dwb_params = dwb_params; + (*seq_state->num_steps)++; + } +} + +void hwss_add_mcif_wb_config_buf(struct block_sequence_state *seq_state, + struct mcif_wb *mcif_wb, + struct mcif_buf_params *mcif_buf_params, + unsigned int dest_height) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = MCIF_WB_CONFIG_BUF; + seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_buf_params.mcif_wb = mcif_wb; + seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_buf_params.mcif_buf_params = mcif_buf_params; + seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_buf_params.dest_height = dest_height; + (*seq_state->num_steps)++; + } +} + +void hwss_add_mcif_wb_config_arb(struct block_sequence_state *seq_state, + struct mcif_wb *mcif_wb, + struct mcif_arb_params *mcif_arb_params) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = MCIF_WB_CONFIG_ARB; + seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_arb_params.mcif_wb = mcif_wb; + seq_state->steps[*seq_state->num_steps].params.mcif_wb_config_arb_params.mcif_arb_params = mcif_arb_params; + (*seq_state->num_steps)++; + } +} + +void hwss_add_mcif_wb_enable(struct block_sequence_state *seq_state, + struct mcif_wb *mcif_wb) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = MCIF_WB_ENABLE; + seq_state->steps[*seq_state->num_steps].params.mcif_wb_enable_params.mcif_wb = mcif_wb; + (*seq_state->num_steps)++; + } +} + +void hwss_add_mcif_wb_disable(struct block_sequence_state *seq_state, + struct mcif_wb *mcif_wb) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = MCIF_WB_DISABLE; + seq_state->steps[*seq_state->num_steps].params.mcif_wb_disable_params.mcif_wb = mcif_wb; + (*seq_state->num_steps)++; + } +} + +void hwss_add_mpc_set_dwb_mux(struct block_sequence_state *seq_state, + struct mpc *mpc, + int dwb_id, + int mpcc_id) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = MPC_SET_DWB_MUX; + seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.mpc = mpc; + seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.dwb_id = dwb_id; + seq_state->steps[*seq_state->num_steps].params.mpc_set_dwb_mux_params.mpcc_id = mpcc_id; + (*seq_state->num_steps)++; + } +} + +void hwss_add_mpc_disable_dwb_mux(struct block_sequence_state *seq_state, + struct mpc *mpc, + unsigned int dwb_id) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = MPC_DISABLE_DWB_MUX; + seq_state->steps[*seq_state->num_steps].params.mpc_disable_dwb_mux_params.mpc = mpc; + seq_state->steps[*seq_state->num_steps].params.mpc_disable_dwb_mux_params.dwb_id = dwb_id; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dwbc_enable(struct block_sequence_state *seq_state, + struct dwbc *dwb, + struct dc_dwb_params *dwb_params) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DWBC_ENABLE; + seq_state->steps[*seq_state->num_steps].params.dwbc_enable_params.dwb = dwb; + seq_state->steps[*seq_state->num_steps].params.dwbc_enable_params.dwb_params = dwb_params; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dwbc_disable(struct block_sequence_state *seq_state, + struct dwbc *dwb) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DWBC_DISABLE; + seq_state->steps[*seq_state->num_steps].params.dwbc_disable_params.dwb = dwb; + (*seq_state->num_steps)++; + } +} + +void hwss_add_tg_set_gsl(struct block_sequence_state *seq_state, + struct timing_generator *tg, + struct gsl_params gsl) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = TG_SET_GSL; + seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_params.tg = tg; + seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_params.gsl = gsl; + (*seq_state->num_steps)++; + } +} + +void hwss_add_tg_set_gsl_source_select(struct block_sequence_state *seq_state, + struct timing_generator *tg, + int group_idx, + uint32_t gsl_ready_signal) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = TG_SET_GSL_SOURCE_SELECT; + seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.tg = tg; + seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.group_idx = group_idx; + seq_state->steps[*seq_state->num_steps].params.tg_set_gsl_source_select_params.gsl_ready_signal = gsl_ready_signal; + (*seq_state->num_steps)++; + } +} + +void hwss_add_hubp_update_mall_sel(struct block_sequence_state *seq_state, + struct hubp *hubp, + uint32_t mall_sel, + bool cache_cursor) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_UPDATE_MALL_SEL; + seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.mall_sel = mall_sel; + seq_state->steps[*seq_state->num_steps].params.hubp_update_mall_sel_params.cache_cursor = cache_cursor; + (*seq_state->num_steps)++; + } +} + +void hwss_add_hubp_prepare_subvp_buffering(struct block_sequence_state *seq_state, + struct hubp *hubp, + bool enable) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_PREPARE_SUBVP_BUFFERING; + seq_state->steps[*seq_state->num_steps].params.hubp_prepare_subvp_buffering_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.hubp_prepare_subvp_buffering_params.enable = enable; + (*seq_state->num_steps)++; + } +} + +void hwss_add_hubp_set_blank_en(struct block_sequence_state *seq_state, + struct hubp *hubp, + bool enable) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_SET_BLANK_EN; + seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_en_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.hubp_set_blank_en_params.enable = enable; + (*seq_state->num_steps)++; + } +} + +void hwss_add_hubp_disable_control(struct block_sequence_state *seq_state, + struct hubp *hubp, + bool disable) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_DISABLE_CONTROL; + seq_state->steps[*seq_state->num_steps].params.hubp_disable_control_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.hubp_disable_control_params.disable = disable; + (*seq_state->num_steps)++; + } +} + +void hwss_add_hubbub_soft_reset(struct block_sequence_state *seq_state, + struct hubbub *hubbub, + void (*hubbub_soft_reset)(struct hubbub *hubbub, bool reset), + bool reset) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBBUB_SOFT_RESET; + seq_state->steps[*seq_state->num_steps].params.hubbub_soft_reset_params.hubbub = hubbub; + seq_state->steps[*seq_state->num_steps].params.hubbub_soft_reset_params.hubbub_soft_reset = hubbub_soft_reset; + seq_state->steps[*seq_state->num_steps].params.hubbub_soft_reset_params.reset = reset; + (*seq_state->num_steps)++; + } +} + +void hwss_add_hubp_clk_cntl(struct block_sequence_state *seq_state, + struct hubp *hubp, + bool enable) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_CLK_CNTL; + seq_state->steps[*seq_state->num_steps].params.hubp_clk_cntl_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.hubp_clk_cntl_params.enable = enable; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dpp_dppclk_control(struct block_sequence_state *seq_state, + struct dpp *dpp, + bool dppclk_div, + bool enable) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DPP_DPPCLK_CONTROL; + seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.dpp = dpp; + seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.dppclk_div = dppclk_div; + seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.enable = enable; + (*seq_state->num_steps)++; + } +} + +void hwss_add_disable_phantom_crtc(struct block_sequence_state *seq_state, + struct timing_generator *tg) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DISABLE_PHANTOM_CRTC; + seq_state->steps[*seq_state->num_steps].params.disable_phantom_crtc_params.tg = tg; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dsc_pg_status(struct block_sequence_state *seq_state, + struct dce_hwseq *hws, + int dsc_inst, + bool is_ungated) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DSC_PG_STATUS; + seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.hws = hws; + seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.dsc_inst = dsc_inst; + seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.is_ungated = is_ungated; + (*seq_state->num_steps)++; + } +} + +void hwss_add_dsc_wait_disconnect_pending_clear(struct block_sequence_state *seq_state, + struct display_stream_compressor *dsc, + bool *is_ungated) { - struct dc_context *ctx = params->send_dmcub_cmd_params.ctx; - union dmub_rb_cmd *cmd = params->send_dmcub_cmd_params.cmd; - enum dm_dmub_wait_type wait_type = params->send_dmcub_cmd_params.wait_type; - - dc_wake_and_execute_dmub_cmd(ctx, cmd, wait_type); + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DSC_WAIT_DISCONNECT_PENDING_CLEAR; + seq_state->steps[*seq_state->num_steps].params.dsc_wait_disconnect_pending_clear_params.dsc = dsc; + seq_state->steps[*seq_state->num_steps].params.dsc_wait_disconnect_pending_clear_params.is_ungated = is_ungated; + (*seq_state->num_steps)++; + } } -void hwss_program_manual_trigger(union block_sequence_params *params) +void hwss_add_dsc_disable(struct block_sequence_state *seq_state, + struct display_stream_compressor *dsc, + bool *is_ungated) { - struct pipe_ctx *pipe_ctx = params->program_manual_trigger_params.pipe_ctx; - - if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger) - pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DSC_DISABLE; + seq_state->steps[*seq_state->num_steps].params.dsc_disable_params.dsc = dsc; + seq_state->steps[*seq_state->num_steps].params.dsc_disable_params.is_ungated = is_ungated; + (*seq_state->num_steps)++; + } } -void hwss_setup_dpp(union block_sequence_params *params) +void hwss_add_dccg_set_ref_dscclk(struct block_sequence_state *seq_state, + struct dccg *dccg, + int dsc_inst, + bool *is_ungated) { - struct pipe_ctx *pipe_ctx = params->setup_dpp_params.pipe_ctx; - struct dpp *dpp = pipe_ctx->plane_res.dpp; - struct dc_plane_state *plane_state = pipe_ctx->plane_state; - - if (!plane_state) - return; - - if (dpp && dpp->funcs->dpp_setup) { - // program the input csc - dpp->funcs->dpp_setup(dpp, - plane_state->format, - EXPANSION_MODE_ZERO, - plane_state->input_csc_color_matrix, - plane_state->color_space, - NULL); + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DCCG_SET_REF_DSCCLK; + seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.dccg = dccg; + seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.dsc_inst = dsc_inst; + seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.is_ungated = is_ungated; + (*seq_state->num_steps)++; } +} - if (dpp && dpp->funcs->set_cursor_matrix) { - dpp->funcs->set_cursor_matrix(dpp, - plane_state->color_space, - plane_state->cursor_csc_color_matrix); +void hwss_add_dpp_root_clock_control(struct block_sequence_state *seq_state, + struct dce_hwseq *hws, + unsigned int dpp_inst, + bool clock_on) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DPP_ROOT_CLOCK_CONTROL; + seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.hws = hws; + seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.dpp_inst = dpp_inst; + seq_state->steps[*seq_state->num_steps].params.dpp_root_clock_control_params.clock_on = clock_on; + (*seq_state->num_steps)++; } } -void hwss_program_bias_and_scale(union block_sequence_params *params) +void hwss_add_dpp_pg_control(struct block_sequence_state *seq_state, + struct dce_hwseq *hws, + unsigned int dpp_inst, + bool power_on) { - struct pipe_ctx *pipe_ctx = params->program_bias_and_scale_params.pipe_ctx; - struct dpp *dpp = pipe_ctx->plane_res.dpp; - struct dc_plane_state *plane_state = pipe_ctx->plane_state; - struct dc_bias_and_scale bns_params = plane_state->bias_and_scale; - - //TODO :for CNVC set scale and bias registers if necessary - if (dpp->funcs->dpp_program_bias_and_scale) { - dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DPP_PG_CONTROL; + seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.hws = hws; + seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.dpp_inst = dpp_inst; + seq_state->steps[*seq_state->num_steps].params.dpp_pg_control_params.power_on = power_on; + (*seq_state->num_steps)++; } } -void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params) +void hwss_add_hubp_pg_control(struct block_sequence_state *seq_state, + struct dce_hwseq *hws, + unsigned int hubp_inst, + bool power_on) { - struct mpc *mpc = params->power_on_mpc_mem_pwr_params.mpc; - int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id; - bool power_on = params->power_on_mpc_mem_pwr_params.power_on; - - if (mpc->funcs->power_on_mpc_mem_pwr) - mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on); + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_PG_CONTROL; + seq_state->steps[*seq_state->num_steps].params.hubp_pg_control_params.hws = hws; + seq_state->steps[*seq_state->num_steps].params.hubp_pg_control_params.hubp_inst = hubp_inst; + seq_state->steps[*seq_state->num_steps].params.hubp_pg_control_params.power_on = power_on; + (*seq_state->num_steps)++; + } } -void hwss_set_output_csc(union block_sequence_params *params) +void hwss_add_hubp_init(struct block_sequence_state *seq_state, + struct hubp *hubp) { - struct mpc *mpc = params->set_output_csc_params.mpc; - int opp_id = params->set_output_csc_params.opp_id; - const uint16_t *matrix = params->set_output_csc_params.regval; - enum mpc_output_csc_mode ocsc_mode = params->set_output_csc_params.ocsc_mode; - - if (mpc->funcs->set_output_csc != NULL) - mpc->funcs->set_output_csc(mpc, - opp_id, - matrix, - ocsc_mode); + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_INIT; + seq_state->steps[*seq_state->num_steps].params.hubp_init_params.hubp = hubp; + (*seq_state->num_steps)++; + } } -void hwss_set_ocsc_default(union block_sequence_params *params) +void hwss_add_hubp_reset(struct block_sequence_state *seq_state, + struct hubp *hubp) { - struct mpc *mpc = params->set_ocsc_default_params.mpc; - int opp_id = params->set_ocsc_default_params.opp_id; - enum dc_color_space colorspace = params->set_ocsc_default_params.color_space; - enum mpc_output_csc_mode ocsc_mode = params->set_ocsc_default_params.ocsc_mode; + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_RESET; + seq_state->steps[*seq_state->num_steps].params.hubp_reset_params.hubp = hubp; + (*seq_state->num_steps)++; + } +} - if (mpc->funcs->set_ocsc_default != NULL) - mpc->funcs->set_ocsc_default(mpc, - opp_id, - colorspace, - ocsc_mode); +void hwss_add_dpp_reset(struct block_sequence_state *seq_state, + struct dpp *dpp) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DPP_RESET; + seq_state->steps[*seq_state->num_steps].params.dpp_reset_params.dpp = dpp; + (*seq_state->num_steps)++; + } } -void hwss_subvp_save_surf_addr(union block_sequence_params *params) +void hwss_add_opp_pipe_clock_control(struct block_sequence_state *seq_state, + struct output_pixel_processor *opp, + bool enable) { - struct dc_dmub_srv *dc_dmub_srv = params->subvp_save_surf_addr.dc_dmub_srv; - const struct dc_plane_address *addr = params->subvp_save_surf_addr.addr; - uint8_t subvp_index = params->subvp_save_surf_addr.subvp_index; + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = OPP_PIPE_CLOCK_CONTROL; + seq_state->steps[*seq_state->num_steps].params.opp_pipe_clock_control_params.opp = opp; + seq_state->steps[*seq_state->num_steps].params.opp_pipe_clock_control_params.enable = enable; + (*seq_state->num_steps)++; + } +} - dc_dmub_srv_subvp_save_surf_addr(dc_dmub_srv, addr, subvp_index); +void hwss_add_hubp_set_vm_system_aperture_settings(struct block_sequence_state *seq_state, + struct hubp *hubp, + uint64_t sys_default, + uint64_t sys_low, + uint64_t sys_high) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS; + seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_default.quad_part = sys_default; + seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_low.quad_part = sys_low; + seq_state->steps[*seq_state->num_steps].params.hubp_set_vm_system_aperture_settings_params.sys_high.quad_part = sys_high; + (*seq_state->num_steps)++; + } } -void get_surface_tile_visual_confirm_color( - struct pipe_ctx *pipe_ctx, - struct tg_color *color) +void hwss_add_hubp_set_flip_int(struct block_sequence_state *seq_state, + struct hubp *hubp) { - uint32_t color_value = MAX_TG_COLOR_VALUE; - /* Determine the overscan color based on the bottom-most plane's context */ - struct pipe_ctx *bottom_pipe_ctx = pipe_ctx; + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_SET_FLIP_INT; + seq_state->steps[*seq_state->num_steps].params.hubp_set_flip_int_params.hubp = hubp; + (*seq_state->num_steps)++; + } +} - while (bottom_pipe_ctx->bottom_pipe != NULL) - bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe; +void hwss_add_dccg_update_dpp_dto(struct block_sequence_state *seq_state, + struct dccg *dccg, + int dpp_inst, + int dppclk_khz) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DCCG_UPDATE_DPP_DTO; + seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dccg = dccg; + seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dpp_inst = dpp_inst; + seq_state->steps[*seq_state->num_steps].params.dccg_update_dpp_dto_params.dppclk_khz = dppclk_khz; + (*seq_state->num_steps)++; + } +} - switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { - case DC_SW_LINEAR: - /* LINEAR Surface - set border color to red */ - color->color_r_cr = color_value; - break; - default: - break; +void hwss_add_hubp_vtg_sel(struct block_sequence_state *seq_state, + struct hubp *hubp, + uint32_t otg_inst) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_VTG_SEL; + seq_state->steps[*seq_state->num_steps].params.hubp_vtg_sel_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.hubp_vtg_sel_params.otg_inst = otg_inst; + (*seq_state->num_steps)++; } } -/** - * hwss_wait_for_all_blank_complete - wait for all active OPPs to finish pending blank - * pattern updates - * - * @dc: [in] dc reference - * @context: [in] hardware context in use - */ -void hwss_wait_for_all_blank_complete(struct dc *dc, - struct dc_state *context) +void hwss_add_hubp_setup2(struct block_sequence_state *seq_state, + struct hubp *hubp, + struct dml2_dchub_per_pipe_register_set *hubp_regs, + union dml2_global_sync_programming *global_sync, + struct dc_crtc_timing *timing) { - struct pipe_ctx *opp_head; - struct dce_hwseq *hws = dc->hwseq; - int i; + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP2; + seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.hubp_regs = hubp_regs; + seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.global_sync = global_sync; + seq_state->steps[*seq_state->num_steps].params.hubp_setup2_params.timing = timing; + (*seq_state->num_steps)++; + } +} - if (!hws->funcs.wait_for_blank_complete) - return; +void hwss_add_hubp_setup(struct block_sequence_state *seq_state, + struct hubp *hubp, + struct _vcs_dpi_display_dlg_regs_st *dlg_regs, + struct _vcs_dpi_display_ttu_regs_st *ttu_regs, + struct _vcs_dpi_display_rq_regs_st *rq_regs, + struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP; + seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.dlg_regs = dlg_regs; + seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.ttu_regs = ttu_regs; + seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.rq_regs = rq_regs; + seq_state->steps[*seq_state->num_steps].params.hubp_setup_params.pipe_dest = pipe_dest; + (*seq_state->num_steps)++; + } +} - for (i = 0; i < MAX_PIPES; i++) { - opp_head = &context->res_ctx.pipe_ctx[i]; +void hwss_add_hubp_set_unbounded_requesting(struct block_sequence_state *seq_state, + struct hubp *hubp, + bool unbounded_req) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_SET_UNBOUNDED_REQUESTING; + seq_state->steps[*seq_state->num_steps].params.hubp_set_unbounded_requesting_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.hubp_set_unbounded_requesting_params.unbounded_req = unbounded_req; + (*seq_state->num_steps)++; + } +} - if (!resource_is_pipe_type(opp_head, OPP_HEAD) || - dc_state_get_pipe_subvp_type(context, opp_head) == SUBVP_PHANTOM) - continue; +void hwss_add_hubp_setup_interdependent2(struct block_sequence_state *seq_state, + struct hubp *hubp, + struct dml2_dchub_per_pipe_register_set *hubp_regs) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP_INTERDEPENDENT2; + seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent2_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent2_params.hubp_regs = hubp_regs; + (*seq_state->num_steps)++; + } +} - hws->funcs.wait_for_blank_complete(opp_head->stream_res.opp); +void hwss_add_hubp_setup_interdependent(struct block_sequence_state *seq_state, + struct hubp *hubp, + struct _vcs_dpi_display_dlg_regs_st *dlg_regs, + struct _vcs_dpi_display_ttu_regs_st *ttu_regs) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_SETUP_INTERDEPENDENT; + seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.dlg_regs = dlg_regs; + seq_state->steps[*seq_state->num_steps].params.hubp_setup_interdependent_params.ttu_regs = ttu_regs; + (*seq_state->num_steps)++; } } -void hwss_wait_for_odm_update_pending_complete(struct dc *dc, struct dc_state *context) +void hwss_add_hubp_program_surface_config(struct block_sequence_state *seq_state, + struct hubp *hubp, + enum surface_pixel_format format, + struct dc_tiling_info *tiling_info, + struct plane_size plane_size, + enum dc_rotation_angle rotation, + struct dc_plane_dcc_param *dcc, + bool horizontal_mirror, + int compat_level) { - struct pipe_ctx *otg_master; - struct timing_generator *tg; - int i; + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_PROGRAM_SURFACE_CONFIG; + seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.format = format; + seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.tiling_info = tiling_info; + seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.plane_size = plane_size; + seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.rotation = rotation; + seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.dcc = dcc; + seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.horizontal_mirror = horizontal_mirror; + seq_state->steps[*seq_state->num_steps].params.program_surface_config_params.compat_level = compat_level; + (*seq_state->num_steps)++; + } +} - for (i = 0; i < MAX_PIPES; i++) { - otg_master = &context->res_ctx.pipe_ctx[i]; - if (!resource_is_pipe_type(otg_master, OTG_MASTER) || - dc_state_get_pipe_subvp_type(context, otg_master) == SUBVP_PHANTOM) - continue; - tg = otg_master->stream_res.tg; - if (tg->funcs->wait_odm_doublebuffer_pending_clear) - tg->funcs->wait_odm_doublebuffer_pending_clear(tg); - if (tg->funcs->wait_otg_disable) - tg->funcs->wait_otg_disable(tg); +void hwss_add_dpp_setup_dpp(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DPP_SETUP_DPP; + seq_state->steps[*seq_state->num_steps].params.setup_dpp_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; } +} - /* ODM update may require to reprogram blank pattern for each OPP */ - hwss_wait_for_all_blank_complete(dc, context); +void hwss_add_dpp_set_cursor_matrix(struct block_sequence_state *seq_state, + struct dpp *dpp, + enum dc_color_space color_space, + struct dc_csc_transform *cursor_csc_color_matrix) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DPP_SET_CURSOR_MATRIX; + seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.dpp = dpp; + seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.color_space = color_space; + seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.cursor_csc_color_matrix = cursor_csc_color_matrix; + (*seq_state->num_steps)++; + } } -void hwss_wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context) +void hwss_add_dpp_set_scaler(struct block_sequence_state *seq_state, + struct dpp *dpp, + const struct scaler_data *scl_data) { - int i; - for (i = 0; i < MAX_PIPES; i++) { - int count = 0; - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DPP_SET_SCALER; + seq_state->steps[*seq_state->num_steps].params.dpp_set_scaler_params.dpp = dpp; + seq_state->steps[*seq_state->num_steps].params.dpp_set_scaler_params.scl_data = scl_data; + (*seq_state->num_steps)++; + } +} - if (!pipe->plane_state || dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) - continue; +void hwss_add_hubp_mem_program_viewport(struct block_sequence_state *seq_state, + struct hubp *hubp, + const struct rect *viewport, + const struct rect *viewport_c) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBP_MEM_PROGRAM_VIEWPORT; + seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.hubp = hubp; + seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.viewport = viewport; + seq_state->steps[*seq_state->num_steps].params.hubp_mem_program_viewport_params.viewport_c = viewport_c; + (*seq_state->num_steps)++; + } +} - /* Timeout 100 ms */ - while (count < 100000) { - /* Must set to false to start with, due to OR in update function */ - pipe->plane_state->status.is_flip_pending = false; - dc->hwss.update_pending_status(pipe); - if (!pipe->plane_state->status.is_flip_pending) - break; - udelay(1); - count++; - } - ASSERT(!pipe->plane_state->status.is_flip_pending); +void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_ATTRIBUTE; + seq_state->steps[*seq_state->num_steps].params.set_cursor_attribute_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.set_cursor_attribute_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; } } -void hwss_wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context) +void hwss_add_set_cursor_position(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx) { -/* - * This function calls HWSS to wait for any potentially double buffered - * operations to complete. It should be invoked as a pre-amble prior - * to full update programming before asserting any HW locks. - */ - int pipe_idx; - int opp_inst; - int opp_count = dc->res_pool->res_cap->num_opp; - struct hubp *hubp; - int mpcc_inst; - const struct pipe_ctx *pipe_ctx; + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_POSITION; + seq_state->steps[*seq_state->num_steps].params.set_cursor_position_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.set_cursor_position_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} - for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { - pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx]; +void hwss_add_set_cursor_sdr_white_level(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = SET_CURSOR_SDR_WHITE_LEVEL; + seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.set_cursor_sdr_white_level_params.pipe_ctx = pipe_ctx; + (*seq_state->num_steps)++; + } +} - if (!pipe_ctx->stream) - continue; +void hwss_add_program_output_csc(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx, + enum dc_color_space colorspace, + uint16_t *matrix, + int opp_id) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = PROGRAM_OUTPUT_CSC; + seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.pipe_ctx = pipe_ctx; + seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.colorspace = colorspace; + seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.matrix = matrix; + seq_state->steps[*seq_state->num_steps].params.program_output_csc_params.opp_id = opp_id; + (*seq_state->num_steps)++; + } +} - /* For full update we must wait for all double buffer updates, not just DRR updates. This - * is particularly important for minimal transitions. Only check for OTG_MASTER pipes, - * as non-OTG Master pipes share the same OTG as - */ - if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && dc->hwss.wait_for_all_pending_updates) { - dc->hwss.wait_for_all_pending_updates(pipe_ctx); - } +void hwss_add_phantom_hubp_post_enable(struct block_sequence_state *seq_state, + struct hubp *hubp) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = PHANTOM_HUBP_POST_ENABLE; + seq_state->steps[*seq_state->num_steps].params.phantom_hubp_post_enable_params.hubp = hubp; + (*seq_state->num_steps)++; + } +} - hubp = pipe_ctx->plane_res.hubp; - if (!hubp) - continue; +void hwss_add_update_force_pstate(struct block_sequence_state *seq_state, + struct dc *dc, + struct dc_state *context) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = UPDATE_FORCE_PSTATE; + seq_state->steps[*seq_state->num_steps].params.update_force_pstate_params.dc = dc; + seq_state->steps[*seq_state->num_steps].params.update_force_pstate_params.context = context; + (*seq_state->num_steps)++; + } +} - mpcc_inst = hubp->inst; - // MPCC inst is equal to pipe index in practice - for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { - if ((dc->res_pool->opps[opp_inst] != NULL) && - (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) { - dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); - dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; - break; - } - } +void hwss_add_hubbub_apply_dedcn21_147_wa(struct block_sequence_state *seq_state, + struct hubbub *hubbub) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBBUB_APPLY_DEDCN21_147_WA; + seq_state->steps[*seq_state->num_steps].params.hubbub_apply_dedcn21_147_wa_params.hubbub = hubbub; + (*seq_state->num_steps)++; } - hwss_wait_for_odm_update_pending_complete(dc, dc_context); } -void hwss_process_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context) +void hwss_add_hubbub_allow_self_refresh_control(struct block_sequence_state *seq_state, + struct hubbub *hubbub, + bool allow, + bool *disallow_self_refresh_applied) { - /* wait for outstanding updates */ - hwss_wait_for_outstanding_hw_updates(dc, dc_context); + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = HUBBUB_ALLOW_SELF_REFRESH_CONTROL; + seq_state->steps[*seq_state->num_steps].params.hubbub_allow_self_refresh_control_params.hubbub = hubbub; + seq_state->steps[*seq_state->num_steps].params.hubbub_allow_self_refresh_control_params.allow = allow; + seq_state->steps[*seq_state->num_steps].params.hubbub_allow_self_refresh_control_params.disallow_self_refresh_applied = disallow_self_refresh_applied; + (*seq_state->num_steps)++; + } +} - /* perform outstanding post update programming */ - if (dc->hwss.program_outstanding_updates) - dc->hwss.program_outstanding_updates(dc, dc_context); +void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state, + struct timing_generator *tg, + unsigned int *frame_count) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = TG_GET_FRAME_COUNT; + seq_state->steps[*seq_state->num_steps].params.tg_get_frame_count_params.tg = tg; + seq_state->steps[*seq_state->num_steps].params.tg_get_frame_count_params.frame_count = frame_count; + (*seq_state->num_steps)++; + } } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 1c77541e0bf59..021bfdb1d3a65 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1168,6 +1168,7 @@ struct dc_debug_options { short auxless_alpm_lfps_t1t2_offset_us; bool enable_pg_cntl_debug_logs; bool disable_stutter_for_wm_program; + bool enable_block_sequence_programming; }; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 41699ff7256f7..e6d3ff8598f52 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -26,9 +26,11 @@ #include "clk_mgr.h" #include "dsc.h" #include "link_service.h" +#include "custom_float.h" #include "dce/dmub_hw_lock_mgr.h" #include "dcn10/dcn10_cm_common.h" +#include "dcn10/dcn10_hubbub.h" #include "dcn20/dcn20_optc.h" #include "dcn30/dcn30_cm_common.h" #include "dcn32/dcn32_hwseq.h" @@ -36,6 +38,7 @@ #include "dcn401/dcn401_resource.h" #include "dc_state_priv.h" #include "link_enc_cfg.h" +#include "../hw_sequencer.h" #define DC_LOGGER_INIT(logger) @@ -1601,6 +1604,143 @@ void dcn401_update_odm(struct dc *dc, struct dc_state *context, dc->hwseq->funcs.blank_pixel_data(dc, otg_master, true); } +static void dcn401_add_dsc_sequence_for_odm_change(struct dc *dc, struct dc_state *context, + struct pipe_ctx *otg_master, struct block_sequence_state *seq_state) +{ + struct pipe_ctx *old_pipe; + struct pipe_ctx *new_pipe; + struct pipe_ctx *old_opp_heads[MAX_PIPES]; + struct pipe_ctx *old_otg_master; + int old_opp_head_count = 0; + int i; + + old_otg_master = &dc->current_state->res_ctx.pipe_ctx[otg_master->pipe_idx]; + + if (resource_is_pipe_type(old_otg_master, OTG_MASTER)) { + old_opp_head_count = resource_get_opp_heads_for_otg_master(old_otg_master, + &dc->current_state->res_ctx, + old_opp_heads); + } else { + old_otg_master = NULL; + } + + /* Process new DSC configuration if DSC is enabled */ + if (otg_master->stream_res.dsc && otg_master->stream->timing.flags.DSC) { + struct dc_stream_state *stream = otg_master->stream; + struct pipe_ctx *odm_pipe; + int opp_cnt = 1; + int last_dsc_calc = 0; + bool should_use_dto_dscclk = (dc->res_pool->dccg->funcs->set_dto_dscclk != NULL) && + stream->timing.pix_clk_100hz > 480000; + + /* Count ODM pipes */ + for (odm_pipe = otg_master->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) + opp_cnt++; + + int num_slices_h = stream->timing.dsc_cfg.num_slices_h / opp_cnt; + + /* Step 1: Set DTO DSCCLK for main DSC if needed */ + if (should_use_dto_dscclk) { + hwss_add_dccg_set_dto_dscclk(seq_state, dc->res_pool->dccg, + otg_master->stream_res.dsc->inst, num_slices_h); + } + + /* Step 2: Calculate and set DSC config for main DSC */ + last_dsc_calc = *seq_state->num_steps; + hwss_add_dsc_calculate_and_set_config(seq_state, otg_master, true, opp_cnt); + + /* Step 3: Enable main DSC block */ + hwss_add_dsc_enable_with_opp(seq_state, otg_master); + + /* Step 4: Configure and enable ODM DSC blocks */ + for (odm_pipe = otg_master->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { + if (!odm_pipe->stream_res.dsc) + continue; + + /* Set DTO DSCCLK for ODM DSC if needed */ + if (should_use_dto_dscclk) { + hwss_add_dccg_set_dto_dscclk(seq_state, dc->res_pool->dccg, + odm_pipe->stream_res.dsc->inst, num_slices_h); + } + + /* Calculate and set DSC config for ODM DSC */ + last_dsc_calc = *seq_state->num_steps; + hwss_add_dsc_calculate_and_set_config(seq_state, odm_pipe, true, opp_cnt); + + /* Enable ODM DSC block */ + hwss_add_dsc_enable_with_opp(seq_state, odm_pipe); + } + + /* Step 5: Configure DSC in timing generator */ + hwss_add_tg_set_dsc_config(seq_state, otg_master->stream_res.tg, + &seq_state->steps[last_dsc_calc].params.dsc_calculate_and_set_config_params.dsc_optc_cfg, true); + } else if (otg_master->stream_res.dsc && !otg_master->stream->timing.flags.DSC) { + /* Disable DSC in OPTC */ + hwss_add_tg_set_dsc_config(seq_state, otg_master->stream_res.tg, NULL, false); + + hwss_add_dsc_disconnect(seq_state, otg_master->stream_res.dsc); + } + + /* Disable DSC for old pipes that no longer need it */ + if (old_otg_master && old_otg_master->stream_res.dsc) { + for (i = 0; i < old_opp_head_count; i++) { + old_pipe = old_opp_heads[i]; + new_pipe = &context->res_ctx.pipe_ctx[old_pipe->pipe_idx]; + + /* If old pipe had DSC but new pipe doesn't, disable the old DSC */ + if (old_pipe->stream_res.dsc && !new_pipe->stream_res.dsc) { + /* Then disconnect DSC block */ + hwss_add_dsc_disconnect(seq_state, old_pipe->stream_res.dsc); + } + } + } +} + +void dcn401_update_odm_sequence(struct dc *dc, struct dc_state *context, + struct pipe_ctx *otg_master, struct block_sequence_state *seq_state) +{ + struct pipe_ctx *opp_heads[MAX_PIPES]; + int opp_inst[MAX_PIPES] = {0}; + int opp_head_count; + int odm_slice_width = resource_get_odm_slice_dst_width(otg_master, false); + int last_odm_slice_width = resource_get_odm_slice_dst_width(otg_master, true); + int i; + + opp_head_count = resource_get_opp_heads_for_otg_master( + otg_master, &context->res_ctx, opp_heads); + + for (i = 0; i < opp_head_count; i++) + opp_inst[i] = opp_heads[i]->stream_res.opp->inst; + + /* Add ODM combine/bypass operation to sequence */ + if (opp_head_count > 1) { + hwss_add_optc_set_odm_combine(seq_state, otg_master->stream_res.tg, opp_inst, + opp_head_count, odm_slice_width, last_odm_slice_width); + } else { + hwss_add_optc_set_odm_bypass(seq_state, otg_master->stream_res.tg, &otg_master->stream->timing); + } + + /* Add OPP operations to sequence */ + for (i = 0; i < opp_head_count; i++) { + /* Add OPP pipe clock control operation */ + hwss_add_opp_pipe_clock_control(seq_state, opp_heads[i]->stream_res.opp, true); + + /* Add OPP program left edge extra pixel operation */ + hwss_add_opp_program_left_edge_extra_pixel(seq_state, opp_heads[i]->stream_res.opp, + opp_heads[i]->stream->timing.pixel_encoding, resource_is_pipe_type(opp_heads[i], OTG_MASTER)); + } + + /* Add DSC update operations to sequence */ + dcn401_add_dsc_sequence_for_odm_change(dc, context, otg_master, seq_state); + + /* Add blank pixel data operation if needed */ + if (!resource_is_pipe_type(otg_master, DPP_PIPE)) { + if (dc->hwseq->funcs.blank_pixel_data_sequence) + dc->hwseq->funcs.blank_pixel_data_sequence( + dc, otg_master, true, seq_state); + } +} + void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings) { @@ -2089,6 +2229,148 @@ void dcn401_program_pipe( } } +/* + * dcn401_program_pipe_sequence - Sequence-based version of dcn401_program_pipe + * + * This function creates a sequence-based version of the original dcn401_program_pipe + * function. Instead of directly calling hardware programming functions, it appends + * sequence steps to the provided block_sequence array that can later be executed + * as part of hwss_execute_sequence. + * + */ +void dcn401_program_pipe_sequence( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_state *context, + struct block_sequence_state *seq_state) +{ + struct dce_hwseq *hws = dc->hwseq; + + /* Only need to unblank on top pipe */ + if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) { + if (pipe_ctx->update_flags.bits.enable || + pipe_ctx->update_flags.bits.odm || + pipe_ctx->stream->update_flags.bits.abm_level) { + if (dc->hwseq->funcs.blank_pixel_data_sequence) + dc->hwseq->funcs.blank_pixel_data_sequence(dc, pipe_ctx, + !pipe_ctx->plane_state || !pipe_ctx->plane_state->visible, + seq_state); + } + } + + /* Only update TG on top pipe */ + if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe + && !pipe_ctx->prev_odm_pipe) { + + /* Step 1: Program global sync */ + hwss_add_tg_program_global_sync(seq_state, pipe_ctx->stream_res.tg, + dcn401_calculate_vready_offset_for_group(pipe_ctx), + (unsigned int)pipe_ctx->global_sync.dcn4x.vstartup_lines, + (unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_offset_pixels, + (unsigned int)pipe_ctx->global_sync.dcn4x.vupdate_vupdate_width_pixels, + (unsigned int)pipe_ctx->global_sync.dcn4x.pstate_keepout_start_lines); + + /* Step 2: Wait for VACTIVE state (if not phantom pipe) */ + if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) { + hwss_add_tg_wait_for_state(seq_state, pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); + } + + /* Step 3: Set VTG params */ + hwss_add_tg_set_vtg_params(seq_state, pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true); + + /* Step 4: Setup vupdate interrupt (if available) */ + if (hws->funcs.setup_vupdate_interrupt) { + dcn401_setup_vupdate_interrupt_sequence(dc, pipe_ctx, seq_state); + } + } + + if (pipe_ctx->update_flags.bits.odm) { + if (hws->funcs.update_odm_sequence) + hws->funcs.update_odm_sequence(dc, context, pipe_ctx, seq_state); + } + + if (pipe_ctx->update_flags.bits.enable) { + if (dc->hwss.enable_plane_sequence) + dc->hwss.enable_plane_sequence(dc, pipe_ctx, context, seq_state); + } + + if (pipe_ctx->update_flags.bits.det_size) { + if (dc->res_pool->hubbub->funcs->program_det_size) { + hwss_add_hubp_program_det_size(seq_state, dc->res_pool->hubbub, + pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb); + } + + if (dc->res_pool->hubbub->funcs->program_det_segments) { + hwss_add_hubp_program_det_segments(seq_state, dc->res_pool->hubbub, + pipe_ctx->plane_res.hubp->inst, pipe_ctx->hubp_regs.det_size); + } + } + + if (pipe_ctx->plane_state && (pipe_ctx->update_flags.raw || + pipe_ctx->plane_state->update_flags.raw || + pipe_ctx->stream->update_flags.raw)) { + + if (dc->hwss.update_dchubp_dpp_sequence) + dc->hwss.update_dchubp_dpp_sequence(dc, pipe_ctx, context, seq_state); + } + + if (pipe_ctx->plane_state && (pipe_ctx->update_flags.bits.enable || + pipe_ctx->plane_state->update_flags.bits.hdr_mult)) { + + hws->funcs.set_hdr_multiplier_sequence(pipe_ctx, seq_state); + } + + if (pipe_ctx->plane_state && + (pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || + pipe_ctx->plane_state->update_flags.bits.gamma_change || + pipe_ctx->plane_state->update_flags.bits.lut_3d || + pipe_ctx->update_flags.bits.enable)) { + + hwss_add_dpp_set_input_transfer_func(seq_state, dc, pipe_ctx, pipe_ctx->plane_state); + } + + /* dcn10_translate_regamma_to_hw_format takes 750us to finish + * only do gamma programming for powering on, internal memcmp to avoid + * updating on slave planes + */ + if (pipe_ctx->update_flags.bits.enable || + pipe_ctx->update_flags.bits.plane_changed || + pipe_ctx->stream->update_flags.bits.out_tf) { + hwss_add_dpp_set_output_transfer_func(seq_state, dc, pipe_ctx, pipe_ctx->stream); + } + + /* If the pipe has been enabled or has a different opp, we + * should reprogram the fmt. This deals with cases where + * interation between mpc and odm combine on different streams + * causes a different pipe to be chosen to odm combine with. + */ + if (pipe_ctx->update_flags.bits.enable + || pipe_ctx->update_flags.bits.opp_changed) { + + hwss_add_opp_set_dyn_expansion(seq_state, pipe_ctx->stream_res.opp, COLOR_SPACE_YCBCR601, pipe_ctx->stream->timing.display_color_depth, pipe_ctx->stream->signal); + + hwss_add_opp_program_fmt(seq_state, pipe_ctx->stream_res.opp, &pipe_ctx->stream->bit_depth_params, &pipe_ctx->stream->clamping); + } + + /* Set ABM pipe after other pipe configurations done */ + if ((pipe_ctx->plane_state && pipe_ctx->plane_state->visible)) { + if (pipe_ctx->stream_res.abm) { + hwss_add_abm_set_pipe(seq_state, dc, pipe_ctx); + + hwss_add_abm_set_level(seq_state, pipe_ctx->stream_res.abm, pipe_ctx->stream->abm_level); + } + } + + if (pipe_ctx->update_flags.bits.test_pattern_changed) { + struct output_pixel_processor *odm_opp = pipe_ctx->stream_res.opp; + + hwss_add_opp_program_bit_depth_reduction(seq_state, odm_opp, true, pipe_ctx); + + hwss_add_opp_set_disp_pattern_generator(seq_state, odm_opp, pipe_ctx->stream_res.test_pattern_params.test_pattern, pipe_ctx->stream_res.test_pattern_params.color_space, pipe_ctx->stream_res.test_pattern_params.color_depth, (struct tg_color){0}, false, pipe_ctx->stream_res.test_pattern_params.width, pipe_ctx->stream_res.test_pattern_params.height, pipe_ctx->stream_res.test_pattern_params.offset); + } + +} + void dcn401_program_front_end_for_ctx( struct dc *dc, struct dc_state *context) @@ -2166,7 +2448,6 @@ void dcn401_program_front_end_for_ctx( && context->res_ctx.pipe_ctx[i].stream) hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); - /* Disconnect mpcc */ for (i = 0; i < dc->res_pool->pipe_count; i++) if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable @@ -2245,11 +2526,11 @@ void dcn401_program_front_end_for_ctx( /* Avoid underflow by check of pipe line read when adding 2nd plane. */ if (hws->wa.wait_hubpret_read_start_during_mpo_transition && - !pipe->top_pipe && - pipe->stream && - pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start && - dc->current_state->stream_status[0].plane_count == 1 && - context->stream_status[0].plane_count > 1) { + !pipe->top_pipe && + pipe->stream && + pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start && + dc->current_state->stream_status[0].plane_count == 1 && + context->stream_status[0].plane_count > 1) { pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp); } } @@ -2361,7 +2642,6 @@ void dcn401_post_unlock_program_front_end( */ if (hwseq->funcs.update_force_pstate) dc->hwseq->funcs.update_force_pstate(dc, context); - /* Only program the MALL registers after all the main and phantom pipes * are done programming. */ @@ -2731,3 +3011,1061 @@ void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pip cs->offload_streams[stream_idx].payloads[payload_idx].pipe_mask |= (1u << pipe->pipe_idx); } + +void dcn401_plane_atomic_power_down_sequence(struct dc *dc, + struct dpp *dpp, + struct hubp *hubp, + struct block_sequence_state *seq_state) +{ + struct dce_hwseq *hws = dc->hwseq; + uint32_t org_ip_request_cntl = 0; + + DC_LOGGER_INIT(dc->ctx->logger); + + /* Check and set DC_IP_REQUEST_CNTL if needed */ + if (REG(DC_IP_REQUEST_CNTL)) { + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) { + hwss_add_dc_ip_request_cntl(seq_state, dc, true); + } + } + + /* DPP power gating control */ + hwss_add_dpp_pg_control(seq_state, hws, dpp->inst, false); + + /* HUBP power gating control */ + hwss_add_hubp_pg_control(seq_state, hws, hubp->inst, false); + + /* HUBP reset */ + hwss_add_hubp_reset(seq_state, hubp); + + /* DPP reset */ + hwss_add_dpp_reset(seq_state, dpp); + + /* Restore DC_IP_REQUEST_CNTL if it was originally 0 */ + if (org_ip_request_cntl == 0 && REG(DC_IP_REQUEST_CNTL)) { + hwss_add_dc_ip_request_cntl(seq_state, dc, false); + } + + DC_LOG_DEBUG("Power gated front end %d\n", hubp->inst); + + /* DPP root clock control */ + hwss_add_dpp_root_clock_control(seq_state, hws, dpp->inst, false); +} + +/* trigger HW to start disconnect plane from stream on the next vsync using block sequence */ +void dcn401_plane_atomic_disconnect_sequence(struct dc *dc, + struct dc_state *state, + struct pipe_ctx *pipe_ctx, + struct block_sequence_state *seq_state) +{ + struct hubp *hubp = pipe_ctx->plane_res.hubp; + int dpp_id = pipe_ctx->plane_res.dpp->inst; + struct mpc *mpc = dc->res_pool->mpc; + struct mpc_tree *mpc_tree_params; + struct mpcc *mpcc_to_remove = NULL; + struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; + + mpc_tree_params = &(opp->mpc_tree_params); + mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id); + + /*Already reset*/ + if (mpcc_to_remove == NULL) + return; + + /* Step 1: Remove MPCC from MPC tree */ + hwss_add_mpc_remove_mpcc(seq_state, mpc, mpc_tree_params, mpcc_to_remove); + + // Phantom pipes have OTG disabled by default, so MPCC_STATUS will never assert idle, + // so don't wait for MPCC_IDLE in the programming sequence + if (dc_state_get_pipe_subvp_type(state, pipe_ctx) != SUBVP_PHANTOM) { + /* Step 2: Set MPCC disconnect pending flag */ + hwss_add_opp_set_mpcc_disconnect_pending(seq_state, opp, pipe_ctx->plane_res.mpcc_inst, true); + } + + /* Step 3: Set optimized required flag */ + hwss_add_dc_set_optimized_required(seq_state, dc, true); + + /* Step 4: Disconnect HUBP if function exists */ + if (hubp->funcs->hubp_disconnect) { + hwss_add_hubp_disconnect(seq_state, hubp); + } + + /* Step 5: Verify pstate change high if debug sanity checks are enabled */ + if (dc->debug.sanity_checks) { + dc->hwseq->funcs.verify_allow_pstate_change_high_sequence(dc, seq_state); + } +} + +void dcn401_blank_pixel_data_sequence( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + bool blank, + struct block_sequence_state *seq_state) +{ + struct tg_color black_color = {0}; + struct stream_resource *stream_res = &pipe_ctx->stream_res; + struct dc_stream_state *stream = pipe_ctx->stream; + enum dc_color_space color_space = stream->output_color_space; + enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; + enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; + struct pipe_ctx *odm_pipe; + struct rect odm_slice_src; + + if (stream->link->test_pattern_enabled) + return; + + /* get opp dpg blank color */ + color_space_to_black_color(dc, color_space, &black_color); + + if (blank) { + /* Set ABM immediate disable */ + hwss_add_abm_set_immediate_disable(seq_state, dc, pipe_ctx); + + if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { + test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; + test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; + } + } else { + test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; + } + + odm_pipe = pipe_ctx; + + /* Set display pattern generator for all ODM pipes */ + while (odm_pipe->next_odm_pipe) { + odm_slice_src = resource_get_odm_slice_src_rect(odm_pipe); + + hwss_add_opp_set_disp_pattern_generator(seq_state, + odm_pipe->stream_res.opp, + test_pattern, + test_pattern_color_space, + stream->timing.display_color_depth, + black_color, + true, + odm_slice_src.width, + odm_slice_src.height, + odm_slice_src.x); + + odm_pipe = odm_pipe->next_odm_pipe; + } + + /* Set display pattern generator for final ODM pipe */ + odm_slice_src = resource_get_odm_slice_src_rect(odm_pipe); + + hwss_add_opp_set_disp_pattern_generator(seq_state, + odm_pipe->stream_res.opp, + test_pattern, + test_pattern_color_space, + stream->timing.display_color_depth, + black_color, + true, + odm_slice_src.width, + odm_slice_src.height, + odm_slice_src.x); + + /* Handle ABM level setting when not blanking */ + if (!blank) { + if (stream_res->abm) { + /* Set pipe for ABM */ + hwss_add_abm_set_pipe(seq_state, dc, pipe_ctx); + + /* Set ABM level */ + hwss_add_abm_set_level(seq_state, stream_res->abm, stream->abm_level); + } + } +} + +void dcn401_program_all_writeback_pipes_in_tree_sequence( + struct dc *dc, + const struct dc_stream_state *stream, + struct dc_state *context, + struct block_sequence_state *seq_state) +{ + struct dwbc *dwb; + int i_wb, i_pipe; + + if (!stream || stream->num_wb_info > dc->res_pool->res_cap->num_dwb) + return; + + /* For each writeback pipe */ + for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) { + /* Get direct pointer to writeback info */ + struct dc_writeback_info *wb_info = (struct dc_writeback_info *)&stream->writeback_info[i_wb]; + int mpcc_inst = -1; + + if (wb_info->wb_enabled) { + /* Get the MPCC instance for writeback_source_plane */ + for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe]; + + if (!pipe_ctx->plane_state) + continue; + + if (pipe_ctx->plane_state == wb_info->writeback_source_plane) { + mpcc_inst = pipe_ctx->plane_res.mpcc_inst; + break; + } + } + + if (mpcc_inst == -1) { + /* Disable writeback pipe and disconnect from MPCC + * if source plane has been removed + */ + dcn401_disable_writeback_sequence(dc, wb_info, seq_state); + continue; + } + + ASSERT(wb_info->dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); + dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; + + if (dwb->funcs->is_enabled(dwb)) { + /* Writeback pipe already enabled, only need to update */ + dcn401_update_writeback_sequence(dc, wb_info, context, seq_state); + } else { + /* Enable writeback pipe and connect to MPCC */ + dcn401_enable_writeback_sequence(dc, wb_info, context, mpcc_inst, seq_state); + } + } else { + /* Disable writeback pipe and disconnect from MPCC */ + dcn401_disable_writeback_sequence(dc, wb_info, seq_state); + } + } +} + +void dcn401_enable_writeback_sequence( + struct dc *dc, + struct dc_writeback_info *wb_info, + struct dc_state *context, + int mpcc_inst, + struct block_sequence_state *seq_state) +{ + struct dwbc *dwb; + struct mcif_wb *mcif_wb; + + if (!wb_info->wb_enabled || wb_info->dwb_pipe_inst >= dc->res_pool->res_cap->num_dwb) + return; + + dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; + mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; + + /* Update DWBC with new parameters */ + hwss_add_dwbc_update(seq_state, dwb, &wb_info->dwb_params); + + /* Configure MCIF_WB buffer settings */ + hwss_add_mcif_wb_config_buf(seq_state, mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); + + /* Configure MCIF_WB arbitration */ + hwss_add_mcif_wb_config_arb(seq_state, mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); + + /* Enable MCIF_WB */ + hwss_add_mcif_wb_enable(seq_state, mcif_wb); + + /* Set DWB MUX to connect writeback to MPCC */ + hwss_add_mpc_set_dwb_mux(seq_state, dc->res_pool->mpc, wb_info->dwb_pipe_inst, mpcc_inst); + + /* Enable DWBC */ + hwss_add_dwbc_enable(seq_state, dwb, &wb_info->dwb_params); +} + +void dcn401_disable_writeback_sequence( + struct dc *dc, + struct dc_writeback_info *wb_info, + struct block_sequence_state *seq_state) +{ + struct dwbc *dwb; + struct mcif_wb *mcif_wb; + + if (wb_info->dwb_pipe_inst >= dc->res_pool->res_cap->num_dwb) + return; + + dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; + mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; + + /* Disable DWBC */ + hwss_add_dwbc_disable(seq_state, dwb); + + /* Disable DWB MUX */ + hwss_add_mpc_disable_dwb_mux(seq_state, dc->res_pool->mpc, wb_info->dwb_pipe_inst); + + /* Disable MCIF_WB */ + hwss_add_mcif_wb_disable(seq_state, mcif_wb); +} + +void dcn401_update_writeback_sequence( + struct dc *dc, + struct dc_writeback_info *wb_info, + struct dc_state *context, + struct block_sequence_state *seq_state) +{ + struct dwbc *dwb; + struct mcif_wb *mcif_wb; + + if (!wb_info->wb_enabled || wb_info->dwb_pipe_inst >= dc->res_pool->res_cap->num_dwb) + return; + + dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; + mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; + + /* Update writeback pipe */ + hwss_add_dwbc_update(seq_state, dwb, &wb_info->dwb_params); + + /* Update MCIF_WB buffer settings if needed */ + hwss_add_mcif_wb_config_buf(seq_state, mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); +} + +static int find_free_gsl_group(const struct dc *dc) +{ + if (dc->res_pool->gsl_groups.gsl_0 == 0) + return 1; + if (dc->res_pool->gsl_groups.gsl_1 == 0) + return 2; + if (dc->res_pool->gsl_groups.gsl_2 == 0) + return 3; + + return 0; +} + +void dcn401_setup_gsl_group_as_lock_sequence( + const struct dc *dc, + struct pipe_ctx *pipe_ctx, + bool enable, + struct block_sequence_state *seq_state) +{ + struct gsl_params gsl; + int group_idx; + + memset(&gsl, 0, sizeof(struct gsl_params)); + + if (enable) { + /* return if group already assigned since GSL was set up + * for vsync flip, we would unassign so it can't be "left over" + */ + if (pipe_ctx->stream_res.gsl_group > 0) + return; + + group_idx = find_free_gsl_group(dc); + ASSERT(group_idx != 0); + pipe_ctx->stream_res.gsl_group = group_idx; + + /* set gsl group reg field and mark resource used */ + switch (group_idx) { + case 1: + gsl.gsl0_en = 1; + dc->res_pool->gsl_groups.gsl_0 = 1; + break; + case 2: + gsl.gsl1_en = 1; + dc->res_pool->gsl_groups.gsl_1 = 1; + break; + case 3: + gsl.gsl2_en = 1; + dc->res_pool->gsl_groups.gsl_2 = 1; + break; + default: + BREAK_TO_DEBUGGER(); + return; // invalid case + } + gsl.gsl_master_en = 1; + } else { + group_idx = pipe_ctx->stream_res.gsl_group; + if (group_idx == 0) + return; // if not in use, just return + + pipe_ctx->stream_res.gsl_group = 0; + + /* unset gsl group reg field and mark resource free */ + switch (group_idx) { + case 1: + gsl.gsl0_en = 0; + dc->res_pool->gsl_groups.gsl_0 = 0; + break; + case 2: + gsl.gsl1_en = 0; + dc->res_pool->gsl_groups.gsl_1 = 0; + break; + case 3: + gsl.gsl2_en = 0; + dc->res_pool->gsl_groups.gsl_2 = 0; + break; + default: + BREAK_TO_DEBUGGER(); + return; + } + gsl.gsl_master_en = 0; + } + + hwss_add_tg_set_gsl(seq_state, pipe_ctx->stream_res.tg, gsl); + hwss_add_tg_set_gsl_source_select(seq_state, pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); +} + +void dcn401_disable_plane_sequence( + struct dc *dc, + struct dc_state *state, + struct pipe_ctx *pipe_ctx, + struct block_sequence_state *seq_state) +{ + bool is_phantom = dc_state_get_pipe_subvp_type(state, pipe_ctx) == SUBVP_PHANTOM; + struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL; + + if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) + return; + + /* Wait for MPCC disconnect */ + if (dc->hwss.wait_for_mpcc_disconnect_sequence) + dc->hwss.wait_for_mpcc_disconnect_sequence(dc, dc->res_pool, pipe_ctx, seq_state); + + /* In flip immediate with pipe splitting case GSL is used for synchronization + * so we must disable it when the plane is disabled. + */ + if (pipe_ctx->stream_res.gsl_group != 0) { + dcn401_setup_gsl_group_as_lock_sequence(dc, pipe_ctx, false, seq_state); + } + + /* Update HUBP mall sel */ + if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs->hubp_update_mall_sel) { + hwss_add_hubp_update_mall_sel(seq_state, pipe_ctx->plane_res.hubp, 0, false); + } + + /* Set flip control GSL */ + hwss_add_hubp_set_flip_control_gsl(seq_state, pipe_ctx->plane_res.hubp, false); + + /* HUBP clock control */ + hwss_add_hubp_clk_cntl(seq_state, pipe_ctx->plane_res.hubp, false); + + /* DPP clock control */ + hwss_add_dpp_dppclk_control(seq_state, pipe_ctx->plane_res.dpp, false, false); + + /* Plane atomic power down */ + if (dc->hwseq->funcs.plane_atomic_power_down_sequence) + dc->hwseq->funcs.plane_atomic_power_down_sequence(dc, pipe_ctx->plane_res.dpp, + pipe_ctx->plane_res.hubp, seq_state); + + pipe_ctx->stream = NULL; + memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); + memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); + pipe_ctx->top_pipe = NULL; + pipe_ctx->bottom_pipe = NULL; + pipe_ctx->prev_odm_pipe = NULL; + pipe_ctx->next_odm_pipe = NULL; + pipe_ctx->plane_state = NULL; + + /* Turn back off the phantom OTG after the phantom plane is fully disabled */ + if (is_phantom && tg && tg->funcs->disable_phantom_crtc) { + hwss_add_disable_phantom_crtc(seq_state, tg); + } +} + +void dcn401_post_unlock_reset_opp_sequence( + struct dc *dc, + struct pipe_ctx *opp_head, + struct block_sequence_state *seq_state) +{ + struct display_stream_compressor *dsc = opp_head->stream_res.dsc; + struct dccg *dccg = dc->res_pool->dccg; + + /* Wait for all DPP pipes in current mpc blending tree completes double + * buffered disconnection before resetting OPP + */ + if (dc->hwss.wait_for_mpcc_disconnect_sequence) + dc->hwss.wait_for_mpcc_disconnect_sequence(dc, dc->res_pool, opp_head, seq_state); + + if (dsc) { + bool *is_ungated = NULL; + /* Check DSC power gate status */ + if (dc->hwseq && dc->hwseq->funcs.dsc_pg_status) { + hwss_add_dsc_pg_status(seq_state, dc->hwseq, dsc->inst, false); + } + + /* Seamless update specific where we will postpone non + * double buffered DSCCLK disable logic in post unlock + * sequence after DSC is disconnected from OPP but not + * yet power gated. + */ + + /* DSC wait disconnect pending clear */ + hwss_add_dsc_wait_disconnect_pending_clear(seq_state, dsc, is_ungated); + + /* DSC disable */ + hwss_add_dsc_disable(seq_state, dsc, is_ungated); + + /* Set reference DSCCLK */ + if (dccg && dccg->funcs->set_ref_dscclk) { + hwss_add_dccg_set_ref_dscclk(seq_state, dccg, dsc->inst, 0); + } + } +} + +void dcn401_dc_ip_request_cntl(struct dc *dc, bool enable) +{ + struct dce_hwseq *hws = dc->hwseq; + + if (REG(DC_IP_REQUEST_CNTL)) { + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, enable ? 1 : 0); + } +} + +void dcn401_enable_plane_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx, + struct dc_state *context, + struct block_sequence_state *seq_state) +{ + struct dce_hwseq *hws = dc->hwseq; + uint32_t org_ip_request_cntl = 0; + + if (!pipe_ctx->plane_res.dpp || !pipe_ctx->plane_res.hubp || !pipe_ctx->stream_res.opp) { + return; + } + + if (REG(DC_IP_REQUEST_CNTL)) + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + + /* Step 1: DPP root clock control - enable clock */ + if (hws->funcs.dpp_root_clock_control) { + hwss_add_dpp_root_clock_control(seq_state, hws, pipe_ctx->plane_res.dpp->inst, true); + } + + /* Step 2: Enable DC IP request (if needed) */ + if (hws->funcs.dc_ip_request_cntl) { + hwss_add_dc_ip_request_cntl(seq_state, dc, true); + } + + /* Step 3: DPP power gating control - power on */ + if (REG(DC_IP_REQUEST_CNTL) && hws->funcs.dpp_pg_control) { + hwss_add_dpp_pg_control(seq_state, hws, pipe_ctx->plane_res.dpp->inst, true); + } + + /* Step 4: HUBP power gating control - power on */ + if (REG(DC_IP_REQUEST_CNTL) && hws->funcs.hubp_pg_control) { + hwss_add_hubp_pg_control(seq_state, hws, pipe_ctx->plane_res.hubp->inst, true); + } + + /* Step 5: Disable DC IP request (restore state) */ + if (org_ip_request_cntl == 0 && hws->funcs.dc_ip_request_cntl) { + hwss_add_dc_ip_request_cntl(seq_state, dc, false); + } + + /* Step 6: HUBP clock control - enable DCFCLK */ + if (pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl) { + hwss_add_hubp_clk_cntl(seq_state, pipe_ctx->plane_res.hubp, true); + } + + /* Step 7: HUBP initialization */ + if (pipe_ctx->plane_res.hubp->funcs->hubp_init) { + hwss_add_hubp_init(seq_state, pipe_ctx->plane_res.hubp); + } + + /* Step 8: OPP pipe clock control - enable */ + if (pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control) { + hwss_add_opp_pipe_clock_control(seq_state, pipe_ctx->stream_res.opp, true); + } + + /* Step 9: VM system aperture settings */ + if (dc->vm_pa_config.valid && pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings) { + hwss_add_hubp_set_vm_system_aperture_settings(seq_state, pipe_ctx->plane_res.hubp, 0, + dc->vm_pa_config.system_aperture.start_addr, dc->vm_pa_config.system_aperture.end_addr); + } + + /* Step 10: Flip interrupt setup */ + if (!pipe_ctx->top_pipe + && pipe_ctx->plane_state + && pipe_ctx->plane_state->flip_int_enabled + && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) { + hwss_add_hubp_set_flip_int(seq_state, pipe_ctx->plane_res.hubp); + } +} + +void dcn401_update_dchubp_dpp_sequence(struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_state *context, + struct block_sequence_state *seq_state) +{ + struct dce_hwseq *hws = dc->hwseq; + struct hubp *hubp = pipe_ctx->plane_res.hubp; + struct dpp *dpp = pipe_ctx->plane_res.dpp; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; + struct dccg *dccg = dc->res_pool->dccg; + bool viewport_changed = false; + enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe_ctx); + + if (!hubp || !dpp || !plane_state) { + return; + } + + /* Step 1: DPP DPPCLK control */ + if (pipe_ctx->update_flags.bits.dppclk) { + hwss_add_dpp_dppclk_control(seq_state, dpp, false, true); + } + + /* Step 2: DCCG update DPP DTO */ + if (pipe_ctx->update_flags.bits.enable) { + hwss_add_dccg_update_dpp_dto(seq_state, dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); + } + + /* Step 3: HUBP VTG selection */ + if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { + hwss_add_hubp_vtg_sel(seq_state, hubp, pipe_ctx->stream_res.tg->inst); + + /* Step 4: HUBP setup (choose setup2 or setup) */ + if (hubp->funcs->hubp_setup2) { + hwss_add_hubp_setup2(seq_state, hubp, &pipe_ctx->hubp_regs, + &pipe_ctx->global_sync, &pipe_ctx->stream->timing); + } else if (hubp->funcs->hubp_setup) { + hwss_add_hubp_setup(seq_state, hubp, &pipe_ctx->dlg_regs, + &pipe_ctx->ttu_regs, &pipe_ctx->rq_regs, &pipe_ctx->pipe_dlg_param); + } + } + + /* Step 5: Set unbounded requesting */ + if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting) { + hwss_add_hubp_set_unbounded_requesting(seq_state, hubp, pipe_ctx->unbounded_req); + } + + /* Step 6: HUBP interdependent setup */ + if (pipe_ctx->update_flags.bits.hubp_interdependent) { + if (hubp->funcs->hubp_setup_interdependent2) { + hwss_add_hubp_setup_interdependent2(seq_state, hubp, &pipe_ctx->hubp_regs); + } else if (hubp->funcs->hubp_setup_interdependent) { + hwss_add_hubp_setup_interdependent(seq_state, hubp, &pipe_ctx->dlg_regs, &pipe_ctx->ttu_regs); + } + } + + /* Step 7: DPP setup - input CSC and format setup */ + if (pipe_ctx->update_flags.bits.enable || + pipe_ctx->update_flags.bits.plane_changed || + plane_state->update_flags.bits.bpp_change || + plane_state->update_flags.bits.input_csc_change || + plane_state->update_flags.bits.color_space_change || + plane_state->update_flags.bits.coeff_reduction_change) { + hwss_add_dpp_setup_dpp(seq_state, pipe_ctx); + + /* Step 8: DPP cursor matrix setup */ + if (dpp->funcs->set_cursor_matrix) { + hwss_add_dpp_set_cursor_matrix(seq_state, dpp, plane_state->color_space, + &plane_state->cursor_csc_color_matrix); + } + + /* Step 9: DPP program bias and scale */ + if (dpp->funcs->dpp_program_bias_and_scale) { + hwss_add_dpp_program_bias_and_scale(seq_state, pipe_ctx); + } + } + + /* Step 10: MPCC updates */ + if (pipe_ctx->update_flags.bits.mpcc || + pipe_ctx->update_flags.bits.plane_changed || + plane_state->update_flags.bits.global_alpha_change || + plane_state->update_flags.bits.per_pixel_alpha_change) { + + /* Check if update_mpcc_sequence is implemented and prefer it over single MPC_UPDATE_MPCC step */ + if (hws->funcs.update_mpcc_sequence) + hws->funcs.update_mpcc_sequence(dc, pipe_ctx, seq_state); + } + + /* Step 11: DPP scaler setup */ + if (pipe_ctx->update_flags.bits.scaler || + plane_state->update_flags.bits.scaling_change || + plane_state->update_flags.bits.position_change || + plane_state->update_flags.bits.per_pixel_alpha_change || + pipe_ctx->stream->update_flags.bits.scaling) { + pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; + ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP); + hwss_add_dpp_set_scaler(seq_state, pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); + } + + /* Step 12: HUBP viewport programming */ + if (pipe_ctx->update_flags.bits.viewport || + (context == dc->current_state && plane_state->update_flags.bits.position_change) || + (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || + (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { + hwss_add_hubp_mem_program_viewport(seq_state, hubp, + &pipe_ctx->plane_res.scl_data.viewport, &pipe_ctx->plane_res.scl_data.viewport_c); + viewport_changed = true; + } + + /* Step 13: HUBP program mcache if available */ + if (hubp->funcs->hubp_program_mcache_id_and_split_coordinate) { + hwss_add_hubp_program_mcache_id(seq_state, hubp, &pipe_ctx->mcache_regs); + } + + /* Step 14: Cursor attribute setup */ + if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || + pipe_ctx->update_flags.bits.scaler || viewport_changed == true) && + pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { + + hwss_add_set_cursor_attribute(seq_state, dc, pipe_ctx); + + /* Step 15: Cursor position setup */ + hwss_add_set_cursor_position(seq_state, dc, pipe_ctx); + + /* Step 16: Cursor SDR white level */ + if (dc->hwss.set_cursor_sdr_white_level) { + hwss_add_set_cursor_sdr_white_level(seq_state, dc, pipe_ctx); + } + } + + /* Step 17: Gamut remap and output CSC */ + if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || + pipe_ctx->update_flags.bits.plane_changed || + pipe_ctx->stream->update_flags.bits.gamut_remap || + plane_state->update_flags.bits.gamut_remap_change || + pipe_ctx->stream->update_flags.bits.out_csc) { + + /* Gamut remap */ + hwss_add_dpp_program_gamut_remap(seq_state, pipe_ctx); + + /* Output CSC */ + hwss_add_program_output_csc(seq_state, dc, pipe_ctx, pipe_ctx->stream->output_color_space, + pipe_ctx->stream->csc_color_matrix.matrix, hubp->opp_id); + } + + /* Step 18: HUBP surface configuration */ + if (pipe_ctx->update_flags.bits.enable || + pipe_ctx->update_flags.bits.plane_changed || + pipe_ctx->update_flags.bits.opp_changed || + plane_state->update_flags.bits.pixel_format_change || + plane_state->update_flags.bits.horizontal_mirror_change || + plane_state->update_flags.bits.rotation_change || + plane_state->update_flags.bits.swizzle_change || + plane_state->update_flags.bits.dcc_change || + plane_state->update_flags.bits.bpp_change || + plane_state->update_flags.bits.scaling_change || + plane_state->update_flags.bits.plane_size_change) { + struct plane_size size = plane_state->plane_size; + + size.surface_size = pipe_ctx->plane_res.scl_data.viewport; + hwss_add_hubp_program_surface_config(seq_state, hubp, + plane_state->format, &plane_state->tiling_info, size, + plane_state->rotation, &plane_state->dcc, + plane_state->horizontal_mirror, 0); + hubp->power_gated = false; + } + + /* Step 19: Update plane address (with SubVP support) */ + if (pipe_ctx->update_flags.bits.enable || + pipe_ctx->update_flags.bits.plane_changed || + plane_state->update_flags.bits.addr_update) { + + /* SubVP save surface address if needed */ + if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_mall_type == SUBVP_MAIN) { + hwss_add_dmub_subvp_save_surf_addr(seq_state, dc->ctx->dmub_srv, &pipe_ctx->plane_state->address, pipe_ctx->subvp_index); + } + + /* Update plane address */ + hwss_add_hubp_update_plane_addr(seq_state, dc, pipe_ctx); + } + + /* Step 20: HUBP set blank - enable plane */ + if (pipe_ctx->update_flags.bits.enable) { + hwss_add_hubp_set_blank(seq_state, hubp, false); + } + + /* Step 21: Phantom HUBP post enable */ + if (pipe_mall_type == SUBVP_PHANTOM && hubp->funcs->phantom_hubp_post_enable) { + hwss_add_phantom_hubp_post_enable(seq_state, hubp); + } +} + +void dcn401_update_mpcc_sequence(struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct block_sequence_state *seq_state) +{ + struct hubp *hubp = pipe_ctx->plane_res.hubp; + struct mpcc_blnd_cfg blnd_cfg = {0}; + bool per_pixel_alpha; + int mpcc_id; + struct mpcc *new_mpcc; + struct mpc *mpc = dc->res_pool->mpc; + struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); + + if (!hubp || !pipe_ctx->plane_state) { + return; + } + + per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; + + /* Initialize blend configuration */ + blnd_cfg.overlap_only = false; + blnd_cfg.global_gain = 0xff; + + if (per_pixel_alpha) { + blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha; + if (pipe_ctx->plane_state->global_alpha) { + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; + blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; + } else { + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; + } + } else { + blnd_cfg.pre_multiplied_alpha = false; + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; + } + + if (pipe_ctx->plane_state->global_alpha) + blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; + else + blnd_cfg.global_alpha = 0xff; + + blnd_cfg.background_color_bpc = 4; + blnd_cfg.bottom_gain_mode = 0; + blnd_cfg.top_gain = 0x1f000; + blnd_cfg.bottom_inside_gain = 0x1f000; + blnd_cfg.bottom_outside_gain = 0x1f000; + + if (pipe_ctx->plane_state->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) + blnd_cfg.pre_multiplied_alpha = false; + + /* MPCC instance is equal to HUBP instance */ + mpcc_id = hubp->inst; + + /* Step 1: Update blending if no full update needed */ + if (!pipe_ctx->plane_state->update_flags.bits.full_update && + !pipe_ctx->update_flags.bits.mpcc) { + + /* Update blending configuration */ + hwss_add_mpc_update_blending(seq_state, mpc, blnd_cfg, mpcc_id); + + /* Update visual confirm color */ + hwss_add_mpc_update_visual_confirm(seq_state, dc, pipe_ctx, mpcc_id); + return; + } + + /* Step 2: Get existing MPCC for DPP */ + new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); + + /* Step 3: Remove MPCC if being used */ + if (new_mpcc != NULL) { + hwss_add_mpc_remove_mpcc(seq_state, mpc, mpc_tree_params, new_mpcc); + } else { + /* Step 4: Assert MPCC idle (debug only) */ + if (dc->debug.sanity_checks) { + hwss_add_mpc_assert_idle_mpcc(seq_state, mpc, mpcc_id); + } + } + + /* Step 5: Insert new plane into MPC tree */ + hwss_add_mpc_insert_plane(seq_state, mpc, mpc_tree_params, blnd_cfg, NULL, NULL, hubp->inst, mpcc_id); + + /* Step 6: Update visual confirm color */ + hwss_add_mpc_update_visual_confirm(seq_state, dc, pipe_ctx, mpcc_id); + + /* Step 7: Set HUBP OPP and MPCC IDs */ + hubp->opp_id = pipe_ctx->stream_res.opp->inst; + hubp->mpcc_id = mpcc_id; +} + +static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst) +{ + int i; + + for (i = 0; i < res_pool->pipe_count; i++) { + if (res_pool->hubps[i]->inst == mpcc_inst) + return res_pool->hubps[i]; + } + ASSERT(false); + return NULL; +} + +void dcn401_wait_for_mpcc_disconnect_sequence( + struct dc *dc, + struct resource_pool *res_pool, + struct pipe_ctx *pipe_ctx, + struct block_sequence_state *seq_state) +{ + int mpcc_inst; + + if (dc->debug.sanity_checks) { + dc->hwseq->funcs.verify_allow_pstate_change_high_sequence(dc, seq_state); + } + + if (!pipe_ctx->stream_res.opp) + return; + + for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) { + if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) { + struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst); + + if (pipe_ctx->stream_res.tg && + pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) { + hwss_add_mpc_assert_idle_mpcc(seq_state, res_pool->mpc, mpcc_inst); + } + pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false; + if (hubp) { + hwss_add_hubp_set_blank(seq_state, hubp, true); + } + } + } + + if (dc->debug.sanity_checks) { + dc->hwseq->funcs.verify_allow_pstate_change_high_sequence(dc, seq_state); + } +} + +void dcn401_setup_vupdate_interrupt_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx, + struct block_sequence_state *seq_state) +{ + struct timing_generator *tg = pipe_ctx->stream_res.tg; + int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); + + if (start_line < 0) + start_line = 0; + + if (tg->funcs->setup_vertical_interrupt2) { + hwss_add_tg_setup_vertical_interrupt2(seq_state, tg, start_line); + } +} + +void dcn401_set_hdr_multiplier_sequence(struct pipe_ctx *pipe_ctx, + struct block_sequence_state *seq_state) +{ + struct fixed31_32 multiplier = pipe_ctx->plane_state->hdr_mult; + uint32_t hw_mult = 0x1f000; // 1.0 default multiplier + struct custom_float_format fmt; + + fmt.exponenta_bits = 6; + fmt.mantissa_bits = 12; + fmt.sign = true; + + if (!dc_fixpt_eq(multiplier, dc_fixpt_from_int(0))) // check != 0 + convert_to_custom_float_format(multiplier, &fmt, &hw_mult); + + hwss_add_dpp_set_hdr_multiplier(seq_state, pipe_ctx->plane_res.dpp, hw_mult); +} + +void dcn401_program_mall_pipe_config_sequence(struct dc *dc, struct dc_state *context, + struct block_sequence_state *seq_state) +{ + int i; + unsigned int num_ways = dcn401_calculate_cab_allocation(dc, context); + bool cache_cursor = false; + + // Don't force p-state disallow -- can't block dummy p-state + + // Update MALL_SEL register for each pipe (break down update_mall_sel call) + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct hubp *hubp = pipe->plane_res.hubp; + + if (pipe->stream && pipe->plane_state && hubp && hubp->funcs->hubp_update_mall_sel) { + int cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; + + switch (hubp->curs_attr.color_format) { + case CURSOR_MODE_MONO: + cursor_size /= 2; + break; + case CURSOR_MODE_COLOR_1BIT_AND: + case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: + case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: + cursor_size *= 4; + break; + + case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: + case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: + default: + cursor_size *= 8; + break; + } + + if (cursor_size > 16384) + cache_cursor = true; + + if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) { + hwss_add_hubp_update_mall_sel(seq_state, hubp, 1, false); + } else { + // MALL not supported with Stereo3D + uint32_t mall_sel = (num_ways <= dc->caps.cache_num_ways && + pipe->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED && + pipe->plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO && + !pipe->plane_state->address.tmz_surface) ? 2 : 0; + hwss_add_hubp_update_mall_sel(seq_state, hubp, mall_sel, cache_cursor); + } + } + } + + // Program FORCE_ONE_ROW_FOR_FRAME and CURSOR_REQ_MODE for main subvp pipes + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct hubp *hubp = pipe->plane_res.hubp; + + if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) { + if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) { + hwss_add_hubp_prepare_subvp_buffering(seq_state, hubp, true); + } + } + } +} + +void dcn401_verify_allow_pstate_change_high_sequence(struct dc *dc, + struct block_sequence_state *seq_state) +{ + struct hubbub *hubbub = dc->res_pool->hubbub; + + if (!hubbub->funcs->verify_allow_pstate_change_high) + return; + + if (!hubbub->funcs->verify_allow_pstate_change_high(hubbub)) { + /* Attempt hardware workaround force recovery */ + dcn401_hw_wa_force_recovery_sequence(dc, seq_state); + } +} + +bool dcn401_hw_wa_force_recovery_sequence(struct dc *dc, + struct block_sequence_state *seq_state) +{ + struct hubp *hubp; + unsigned int i; + + if (!dc->debug.recovery_enabled) + return false; + + /* Step 1: Set HUBP_BLANK_EN=1 for all active pipes */ + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + if (pipe_ctx != NULL) { + hubp = pipe_ctx->plane_res.hubp; + if (hubp != NULL && hubp->funcs->set_hubp_blank_en) { + hwss_add_hubp_set_blank_en(seq_state, hubp, true); + } + } + } + + /* Step 2: DCHUBBUB_GLOBAL_SOFT_RESET=1 */ + hwss_add_hubbub_soft_reset(seq_state, dc->res_pool->hubbub, hubbub1_soft_reset, true); + + /* Step 3: Set HUBP_DISABLE=1 for all active pipes */ + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + if (pipe_ctx != NULL) { + hubp = pipe_ctx->plane_res.hubp; + if (hubp != NULL && hubp->funcs->hubp_disable_control) { + hwss_add_hubp_disable_control(seq_state, hubp, true); + } + } + } + + /* Step 4: Set HUBP_DISABLE=0 for all active pipes */ + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + if (pipe_ctx != NULL) { + hubp = pipe_ctx->plane_res.hubp; + if (hubp != NULL && hubp->funcs->hubp_disable_control) { + hwss_add_hubp_disable_control(seq_state, hubp, false); + } + } + } + + /* Step 5: DCHUBBUB_GLOBAL_SOFT_RESET=0 */ + hwss_add_hubbub_soft_reset(seq_state, dc->res_pool->hubbub, hubbub1_soft_reset, false); + + /* Step 6: Set HUBP_BLANK_EN=0 for all active pipes */ + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + if (pipe_ctx != NULL) { + hubp = pipe_ctx->plane_res.hubp; + if (hubp != NULL && hubp->funcs->set_hubp_blank_en) { + hwss_add_hubp_set_blank_en(seq_state, hubp, false); + } + } + } + + return true; +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h index f489bb7a4c268..f78162ab859b4 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h @@ -9,6 +9,7 @@ #include "dc.h" #include "dc_stream.h" #include "hw_sequencer_private.h" +#include "hwss/hw_sequencer.h" #include "dcn401/dcn401_dccg.h" struct dc; @@ -82,6 +83,8 @@ void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *l void dcn401_hardware_release(struct dc *dc); void dcn401_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master); +void dcn401_update_odm_sequence(struct dc *dc, struct dc_state *context, + struct pipe_ctx *otg_master, struct block_sequence_state *seq_state); void adjust_hotspot_between_slices_for_2x_magnify(uint32_t cursor_width, struct dc_cursor_position *pos_cpy); void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master); void dcn401_interdependent_update_lock(struct dc *dc, struct dc_state *context, bool lock); @@ -97,6 +100,11 @@ void dcn401_program_pipe( struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_state *context); +void dcn401_program_pipe_sequence( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_state *context, + struct block_sequence_state *seq_state); void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx); void dcn401_program_front_end_for_ctx(struct dc *dc, struct dc_state *context); void dcn401_post_unlock_program_front_end(struct dc *dc, struct dc_state *context); @@ -109,7 +117,97 @@ void dcn401_detect_pipe_changes( void dcn401_plane_atomic_power_down(struct dc *dc, struct dpp *dpp, struct hubp *hubp); +void dcn401_plane_atomic_power_down_sequence(struct dc *dc, + struct dpp *dpp, + struct hubp *hubp, + struct block_sequence_state *seq_state); +void dcn401_plane_atomic_disconnect_sequence(struct dc *dc, + struct dc_state *state, + struct pipe_ctx *pipe_ctx, + struct block_sequence_state *seq_state); +void dcn401_blank_pixel_data_sequence( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + bool blank, + struct block_sequence_state *seq_state); void dcn401_initialize_min_clocks(struct dc *dc); void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe); +void dcn401_program_all_writeback_pipes_in_tree_sequence( + struct dc *dc, + const struct dc_stream_state *stream, + struct dc_state *context, + struct block_sequence_state *seq_state); + +void dcn401_enable_writeback_sequence( + struct dc *dc, + struct dc_writeback_info *wb_info, + struct dc_state *context, + int mpcc_inst, + struct block_sequence_state *seq_state); + +void dcn401_disable_writeback_sequence( + struct dc *dc, + struct dc_writeback_info *wb_info, + struct block_sequence_state *seq_state); + +void dcn401_update_writeback_sequence( + struct dc *dc, + struct dc_writeback_info *wb_info, + struct dc_state *context, + struct block_sequence_state *seq_state); + +void dcn401_setup_gsl_group_as_lock_sequence( + const struct dc *dc, + struct pipe_ctx *pipe_ctx, + bool enable, + struct block_sequence_state *seq_state); + +void dcn401_disable_plane_sequence( + struct dc *dc, + struct dc_state *state, + struct pipe_ctx *pipe_ctx, + struct block_sequence_state *seq_state); + +void dcn401_post_unlock_reset_opp_sequence( + struct dc *dc, + struct pipe_ctx *opp_head, + struct block_sequence_state *seq_state); + +void dcn401_dc_ip_request_cntl(struct dc *dc, bool enable); + +void dcn401_enable_plane_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx, + struct dc_state *context, + struct block_sequence_state *seq_state); + +void dcn401_update_dchubp_dpp_sequence(struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_state *context, + struct block_sequence_state *seq_state); + +void dcn401_update_mpcc_sequence(struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct block_sequence_state *seq_state); + +void dcn401_wait_for_mpcc_disconnect_sequence( + struct dc *dc, + struct resource_pool *res_pool, + struct pipe_ctx *pipe_ctx, + struct block_sequence_state *seq_state); + +void dcn401_setup_vupdate_interrupt_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx, + struct block_sequence_state *seq_state); + +void dcn401_set_hdr_multiplier_sequence(struct pipe_ctx *pipe_ctx, + struct block_sequence_state *seq_state); + +void dcn401_program_mall_pipe_config_sequence(struct dc *dc, struct dc_state *context, + struct block_sequence_state *seq_state); + +void dcn401_verify_allow_pstate_change_high_sequence(struct dc *dc, + struct block_sequence_state *seq_state); + +bool dcn401_hw_wa_force_recovery_sequence(struct dc *dc, + struct block_sequence_state *seq_state); + #endif /* __DC_HWSS_DCN401_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c index 1c736b7e33001..162096ce0bdfb 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c @@ -39,6 +39,7 @@ static const struct hw_sequencer_funcs dcn401_funcs = { .enable_audio_stream = dce110_enable_audio_stream, .disable_audio_stream = dce110_disable_audio_stream, .disable_plane = dcn20_disable_plane, + .disable_plane_sequence = dcn401_disable_plane_sequence, .pipe_control_lock = dcn20_pipe_control_lock, .interdependent_update_lock = dcn401_interdependent_update_lock, .cursor_lock = dcn10_cursor_lock, @@ -54,6 +55,7 @@ static const struct hw_sequencer_funcs dcn401_funcs = { .get_hw_state = dcn10_get_hw_state, .clear_status_bits = dcn10_clear_status_bits, .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, + .wait_for_mpcc_disconnect_sequence = dcn401_wait_for_mpcc_disconnect_sequence, .edp_backlight_control = dce110_edp_backlight_control, .edp_power_control = dce110_edp_power_control, .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, @@ -109,48 +111,63 @@ static const struct hw_sequencer_funcs dcn401_funcs = { .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, .detect_pipe_changes = dcn401_detect_pipe_changes, .enable_plane = dcn20_enable_plane, + .enable_plane_sequence = dcn401_enable_plane_sequence, .update_dchubp_dpp = dcn20_update_dchubp_dpp, + .update_dchubp_dpp_sequence = dcn401_update_dchubp_dpp_sequence, .post_unlock_reset_opp = dcn20_post_unlock_reset_opp, + .post_unlock_reset_opp_sequence = dcn401_post_unlock_reset_opp_sequence, .get_underflow_debug_data = dcn30_get_underflow_debug_data, }; static const struct hwseq_private_funcs dcn401_private_funcs = { .init_pipes = dcn10_init_pipes, .plane_atomic_disconnect = dcn10_plane_atomic_disconnect, + .plane_atomic_disconnect_sequence = dcn401_plane_atomic_disconnect_sequence, .update_mpcc = dcn20_update_mpcc, + .update_mpcc_sequence = dcn401_update_mpcc_sequence, .set_input_transfer_func = dcn32_set_input_transfer_func, .set_output_transfer_func = dcn401_set_output_transfer_func, .power_down = dce110_power_down, .enable_display_power_gating = dcn10_dummy_display_power_gating, .blank_pixel_data = dcn20_blank_pixel_data, + .blank_pixel_data_sequence = dcn401_blank_pixel_data_sequence, .reset_hw_ctx_wrap = dcn401_reset_hw_ctx_wrap, .enable_stream_timing = dcn401_enable_stream_timing, .edp_backlight_control = dce110_edp_backlight_control, .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt, + .setup_vupdate_interrupt_sequence = dcn401_setup_vupdate_interrupt_sequence, .did_underflow_occur = dcn10_did_underflow_occur, .init_blank = dcn32_init_blank, .disable_vga = dcn20_disable_vga, .bios_golden_init = dcn10_bios_golden_init, .plane_atomic_disable = dcn20_plane_atomic_disable, .plane_atomic_power_down = dcn401_plane_atomic_power_down, + .plane_atomic_power_down_sequence = dcn401_plane_atomic_power_down_sequence, .enable_power_gating_plane = dcn32_enable_power_gating_plane, .hubp_pg_control = dcn32_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, + .program_all_writeback_pipes_in_tree_sequence = dcn401_program_all_writeback_pipes_in_tree_sequence, .update_odm = dcn401_update_odm, + .update_odm_sequence = dcn401_update_odm_sequence, .dsc_pg_control = dcn32_dsc_pg_control, .dsc_pg_status = dcn32_dsc_pg_status, .set_hdr_multiplier = dcn10_set_hdr_multiplier, + .set_hdr_multiplier_sequence = dcn401_set_hdr_multiplier_sequence, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, + .verify_allow_pstate_change_high_sequence = dcn401_verify_allow_pstate_change_high_sequence, .wait_for_blank_complete = dcn20_wait_for_blank_complete, .dccg_init = dcn20_dccg_init, .set_mcm_luts = dcn401_set_mcm_luts, .program_mall_pipe_config = dcn32_program_mall_pipe_config, + .program_mall_pipe_config_sequence = dcn401_program_mall_pipe_config_sequence, .update_mall_sel = dcn32_update_mall_sel, .calculate_dccg_k1_k2_values = NULL, .apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw, .reset_back_end_for_pipe = dcn401_reset_back_end_for_pipe, .populate_mcm_luts = NULL, .perform_3dlut_wa_unlock = dcn401_perform_3dlut_wa_unlock, + .program_pipe_sequence = dcn401_program_pipe_sequence, + .dc_ip_request_cntl = dcn401_dc_ip_request_cntl, }; void dcn401_hw_sequencer_init_functions(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index a937a2b2135e7..3772b4aa11cc1 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -31,6 +31,8 @@ #include "inc/hw/opp.h" #include "inc/hw/link_encoder.h" #include "inc/core_status.h" +#include "inc/hw/hw_shared.h" +#include "dsc/dsc.h" struct pipe_ctx; struct dc_state; @@ -48,6 +50,8 @@ struct dc_dmub_cmd; struct pg_block_update; struct drr_params; struct dc_underflow_debug_data; +struct dsc_optc_config; +struct vm_system_aperture_param; struct subvp_pipe_control_lock_fast_params { struct dc *dc; @@ -62,7 +66,7 @@ struct pipe_control_lock_params { }; struct set_flip_control_gsl_params { - struct pipe_ctx *pipe_ctx; + struct hubp *hubp; bool flip_immediate; }; @@ -154,11 +158,576 @@ struct dmub_hw_control_lock_fast_params { bool lock; }; +struct program_surface_config_params { + struct hubp *hubp; + enum surface_pixel_format format; + struct dc_tiling_info *tiling_info; + struct plane_size plane_size; + enum dc_rotation_angle rotation; + struct dc_plane_dcc_param *dcc; + bool horizontal_mirror; + int compat_level; +}; + +struct program_mcache_id_and_split_coordinate { + struct hubp *hubp; + struct dml2_hubp_pipe_mcache_regs *mcache_regs; +}; + struct program_cursor_update_now_params { struct dc *dc; struct pipe_ctx *pipe_ctx; }; +struct hubp_wait_pipe_read_start_params { + struct hubp *hubp; +}; + +struct apply_update_flags_for_phantom_params { + struct pipe_ctx *pipe_ctx; +}; + +struct update_phantom_vp_position_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; + struct dc_state *context; +}; + +struct set_odm_combine_params { + struct timing_generator *tg; + int opp_inst[MAX_PIPES]; + int opp_head_count; + int odm_slice_width; + int last_odm_slice_width; +}; + +struct set_odm_bypass_params { + struct timing_generator *tg; + const struct dc_crtc_timing *timing; +}; + +struct opp_pipe_clock_control_params { + struct output_pixel_processor *opp; + bool enable; +}; + +struct opp_program_left_edge_extra_pixel_params { + struct output_pixel_processor *opp; + enum dc_pixel_encoding pixel_encoding; + bool is_otg_master; +}; + +struct dccg_set_dto_dscclk_params { + struct dccg *dccg; + int inst; + int num_slices_h; +}; + +struct dsc_set_config_params { + struct display_stream_compressor *dsc; + struct dsc_config *dsc_cfg; + struct dsc_optc_config *dsc_optc_cfg; +}; + +struct dsc_enable_params { + struct display_stream_compressor *dsc; + int opp_inst; +}; + +struct tg_set_dsc_config_params { + struct timing_generator *tg; + struct dsc_optc_config *dsc_optc_cfg; + bool enable; +}; + +struct dsc_disconnect_params { + struct display_stream_compressor *dsc; +}; + +struct dsc_read_state_params { + struct display_stream_compressor *dsc; + struct dcn_dsc_state *dsc_state; +}; + +struct dsc_calculate_and_set_config_params { + struct pipe_ctx *pipe_ctx; + struct dsc_optc_config dsc_optc_cfg; + bool enable; + int opp_cnt; +}; + +struct dsc_enable_with_opp_params { + struct pipe_ctx *pipe_ctx; +}; + +struct program_tg_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; + struct dc_state *context; +}; + +struct tg_program_global_sync_params { + struct timing_generator *tg; + int vready_offset; + unsigned int vstartup_lines; + unsigned int vupdate_offset_pixels; + unsigned int vupdate_vupdate_width_pixels; + unsigned int pstate_keepout_start_lines; +}; + +struct tg_wait_for_state_params { + struct timing_generator *tg; + enum crtc_state state; +}; + +struct tg_set_vtg_params_params { + struct timing_generator *tg; + struct dc_crtc_timing *timing; + bool program_fp2; +}; + +struct tg_set_gsl_params { + struct timing_generator *tg; + struct gsl_params gsl; +}; + +struct tg_set_gsl_source_select_params { + struct timing_generator *tg; + int group_idx; + uint32_t gsl_ready_signal; +}; + +struct setup_vupdate_interrupt_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; +}; + +struct tg_setup_vertical_interrupt2_params { + struct timing_generator *tg; + int start_line; +}; + +struct dpp_set_hdr_multiplier_params { + struct dpp *dpp; + uint32_t hw_mult; +}; + +struct program_det_size_params { + struct hubbub *hubbub; + unsigned int hubp_inst; + unsigned int det_buffer_size_kb; +}; + +struct program_det_segments_params { + struct hubbub *hubbub; + unsigned int hubp_inst; + unsigned int det_size; +}; + +struct update_dchubp_dpp_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; + struct dc_state *context; +}; + +struct opp_set_dyn_expansion_params { + struct output_pixel_processor *opp; + enum dc_color_space color_space; + enum dc_color_depth color_depth; + enum signal_type signal; +}; + +struct opp_program_fmt_params { + struct output_pixel_processor *opp; + struct bit_depth_reduction_params *fmt_bit_depth; + struct clamping_and_pixel_encoding_params *clamping; +}; + +struct opp_program_bit_depth_reduction_params { + struct output_pixel_processor *opp; + bool use_default_params; + struct pipe_ctx *pipe_ctx; +}; + +struct opp_set_disp_pattern_generator_params { + struct output_pixel_processor *opp; + enum controller_dp_test_pattern test_pattern; + enum controller_dp_color_space color_space; + enum dc_color_depth color_depth; + struct tg_color solid_color; + bool use_solid_color; + int width; + int height; + int offset; +}; + +struct set_abm_pipe_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; +}; + +struct set_abm_level_params { + struct abm *abm; + unsigned int abm_level; +}; + +struct set_abm_immediate_disable_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; +}; + +struct set_disp_pattern_generator_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; + enum controller_dp_test_pattern test_pattern; + enum controller_dp_color_space color_space; + enum dc_color_depth color_depth; + const struct tg_color *solid_color; + int width; + int height; + int offset; +}; + +struct mpc_update_blending_params { + struct mpc *mpc; + struct mpcc_blnd_cfg blnd_cfg; + int mpcc_id; +}; + +struct mpc_assert_idle_mpcc_params { + struct mpc *mpc; + int mpcc_id; +}; + +struct mpc_insert_plane_params { + struct mpc *mpc; + struct mpc_tree *mpc_tree_params; + struct mpcc_blnd_cfg blnd_cfg; + struct mpcc_sm_cfg *sm_cfg; + struct mpcc *insert_above_mpcc; + int dpp_id; + int mpcc_id; +}; + +struct mpc_remove_mpcc_params { + struct mpc *mpc; + struct mpc_tree *mpc_tree_params; + struct mpcc *mpcc_to_remove; +}; + +struct opp_set_mpcc_disconnect_pending_params { + struct output_pixel_processor *opp; + int mpcc_inst; + bool pending; +}; + +struct dc_set_optimized_required_params { + struct dc *dc; + bool optimized_required; +}; + +struct hubp_disconnect_params { + struct hubp *hubp; +}; + +struct hubbub_force_pstate_change_control_params { + struct hubbub *hubbub; + bool enable; + bool wait; +}; + +struct tg_enable_crtc_params { + struct timing_generator *tg; +}; + +struct hubp_wait_flip_pending_params { + struct hubp *hubp; + unsigned int timeout_us; + unsigned int polling_interval_us; +}; + +struct tg_wait_double_buffer_pending_params { + struct timing_generator *tg; + unsigned int timeout_us; + unsigned int polling_interval_us; +}; + +struct update_force_pstate_params { + struct dc *dc; + struct dc_state *context; +}; + +struct hubbub_apply_dedcn21_147_wa_params { + struct hubbub *hubbub; +}; + +struct hubbub_allow_self_refresh_control_params { + struct hubbub *hubbub; + bool allow; + bool *disallow_self_refresh_applied; +}; + +struct tg_get_frame_count_params { + struct timing_generator *tg; + unsigned int *frame_count; +}; + +struct mpc_set_dwb_mux_params { + struct mpc *mpc; + int dwb_id; + int mpcc_id; +}; + +struct mpc_disable_dwb_mux_params { + struct mpc *mpc; + unsigned int dwb_id; +}; + +struct mcif_wb_config_buf_params { + struct mcif_wb *mcif_wb; + struct mcif_buf_params *mcif_buf_params; + unsigned int dest_height; +}; + +struct mcif_wb_config_arb_params { + struct mcif_wb *mcif_wb; + struct mcif_arb_params *mcif_arb_params; +}; + +struct mcif_wb_enable_params { + struct mcif_wb *mcif_wb; +}; + +struct mcif_wb_disable_params { + struct mcif_wb *mcif_wb; +}; + +struct dwbc_enable_params { + struct dwbc *dwb; + struct dc_dwb_params *dwb_params; +}; + +struct dwbc_disable_params { + struct dwbc *dwb; +}; + +struct dwbc_update_params { + struct dwbc *dwb; + struct dc_dwb_params *dwb_params; +}; + +struct hubp_update_mall_sel_params { + struct hubp *hubp; + uint32_t mall_sel; + bool cache_cursor; +}; + +struct hubp_prepare_subvp_buffering_params { + struct hubp *hubp; + bool enable; +}; + +struct hubp_set_blank_en_params { + struct hubp *hubp; + bool enable; +}; + +struct hubp_disable_control_params { + struct hubp *hubp; + bool disable; +}; + +struct hubbub_soft_reset_params { + struct hubbub *hubbub; + void (*hubbub_soft_reset)(struct hubbub *hubbub, bool reset); + bool reset; +}; + +struct hubp_clk_cntl_params { + struct hubp *hubp; + bool enable; +}; + +struct hubp_init_params { + struct hubp *hubp; +}; + +struct hubp_set_vm_system_aperture_settings_params { + struct hubp *hubp; + //struct vm_system_aperture_param apt; + PHYSICAL_ADDRESS_LOC sys_default; + PHYSICAL_ADDRESS_LOC sys_low; + PHYSICAL_ADDRESS_LOC sys_high; +}; + +struct hubp_set_flip_int_params { + struct hubp *hubp; +}; + +struct dpp_dppclk_control_params { + struct dpp *dpp; + bool dppclk_div; + bool enable; +}; + +struct disable_phantom_crtc_params { + struct timing_generator *tg; +}; + +struct dpp_pg_control_params { + struct dce_hwseq *hws; + unsigned int dpp_inst; + bool power_on; +}; + +struct hubp_pg_control_params { + struct dce_hwseq *hws; + unsigned int hubp_inst; + bool power_on; +}; + +struct hubp_reset_params { + struct hubp *hubp; +}; + +struct dpp_reset_params { + struct dpp *dpp; +}; + +struct dpp_root_clock_control_params { + struct dce_hwseq *hws; + unsigned int dpp_inst; + bool clock_on; +}; + +struct dc_ip_request_cntl_params { + struct dc *dc; + bool enable; +}; + +struct dsc_pg_status_params { + struct dce_hwseq *hws; + int dsc_inst; + bool is_ungated; +}; + +struct dsc_wait_disconnect_pending_clear_params { + struct display_stream_compressor *dsc; + bool *is_ungated; +}; + +struct dsc_disable_params { + struct display_stream_compressor *dsc; + bool *is_ungated; +}; + +struct dccg_set_ref_dscclk_params { + struct dccg *dccg; + int dsc_inst; + bool *is_ungated; +}; + +struct dccg_update_dpp_dto_params { + struct dccg *dccg; + int dpp_inst; + int dppclk_khz; +}; + +struct hubp_vtg_sel_params { + struct hubp *hubp; + uint32_t otg_inst; +}; + +struct hubp_setup2_params { + struct hubp *hubp; + struct dml2_dchub_per_pipe_register_set *hubp_regs; + union dml2_global_sync_programming *global_sync; + struct dc_crtc_timing *timing; +}; + +struct hubp_setup_params { + struct hubp *hubp; + struct _vcs_dpi_display_dlg_regs_st *dlg_regs; + struct _vcs_dpi_display_ttu_regs_st *ttu_regs; + struct _vcs_dpi_display_rq_regs_st *rq_regs; + struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest; +}; + +struct hubp_set_unbounded_requesting_params { + struct hubp *hubp; + bool unbounded_req; +}; + +struct hubp_setup_interdependent2_params { + struct hubp *hubp; + struct dml2_dchub_per_pipe_register_set *hubp_regs; +}; + +struct hubp_setup_interdependent_params { + struct hubp *hubp; + struct _vcs_dpi_display_dlg_regs_st *dlg_regs; + struct _vcs_dpi_display_ttu_regs_st *ttu_regs; +}; + +struct dpp_set_cursor_matrix_params { + struct dpp *dpp; + enum dc_color_space color_space; + struct dc_csc_transform *cursor_csc_color_matrix; +}; + +struct mpc_update_mpcc_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; +}; + +struct dpp_set_scaler_params { + struct dpp *dpp; + const struct scaler_data *scl_data; +}; + +struct hubp_mem_program_viewport_params { + struct hubp *hubp; + const struct rect *viewport; + const struct rect *viewport_c; +}; + +struct hubp_program_mcache_id_and_split_coordinate_params { + struct hubp *hubp; + struct mcache_regs_struct *mcache_regs; +}; + +struct set_cursor_attribute_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; +}; + +struct set_cursor_position_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; +}; + +struct set_cursor_sdr_white_level_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; +}; + +struct program_output_csc_params { + struct dc *dc; + struct pipe_ctx *pipe_ctx; + enum dc_color_space colorspace; + uint16_t *matrix; + int opp_id; +}; + +struct hubp_set_blank_params { + struct hubp *hubp; + bool blank; +}; + +struct phantom_hubp_post_enable_params { + struct hubp *hubp; +}; + union block_sequence_params { struct update_plane_addr_params update_plane_addr_params; struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params; @@ -179,7 +748,106 @@ union block_sequence_params { struct subvp_save_surf_addr subvp_save_surf_addr; struct wait_for_dcc_meta_propagation_params wait_for_dcc_meta_propagation_params; struct dmub_hw_control_lock_fast_params dmub_hw_control_lock_fast_params; + struct program_surface_config_params program_surface_config_params; + struct program_mcache_id_and_split_coordinate program_mcache_id_and_split_coordinate; struct program_cursor_update_now_params program_cursor_update_now_params; + struct hubp_wait_pipe_read_start_params hubp_wait_pipe_read_start_params; + struct apply_update_flags_for_phantom_params apply_update_flags_for_phantom_params; + struct update_phantom_vp_position_params update_phantom_vp_position_params; + struct set_odm_combine_params set_odm_combine_params; + struct set_odm_bypass_params set_odm_bypass_params; + struct opp_pipe_clock_control_params opp_pipe_clock_control_params; + struct opp_program_left_edge_extra_pixel_params opp_program_left_edge_extra_pixel_params; + struct dccg_set_dto_dscclk_params dccg_set_dto_dscclk_params; + struct dsc_set_config_params dsc_set_config_params; + struct dsc_enable_params dsc_enable_params; + struct tg_set_dsc_config_params tg_set_dsc_config_params; + struct dsc_disconnect_params dsc_disconnect_params; + struct dsc_read_state_params dsc_read_state_params; + struct dsc_calculate_and_set_config_params dsc_calculate_and_set_config_params; + struct dsc_enable_with_opp_params dsc_enable_with_opp_params; + struct program_tg_params program_tg_params; + struct tg_program_global_sync_params tg_program_global_sync_params; + struct tg_wait_for_state_params tg_wait_for_state_params; + struct tg_set_vtg_params_params tg_set_vtg_params_params; + struct tg_setup_vertical_interrupt2_params tg_setup_vertical_interrupt2_params; + struct dpp_set_hdr_multiplier_params dpp_set_hdr_multiplier_params; + struct tg_set_gsl_params tg_set_gsl_params; + struct tg_set_gsl_source_select_params tg_set_gsl_source_select_params; + struct setup_vupdate_interrupt_params setup_vupdate_interrupt_params; + struct program_det_size_params program_det_size_params; + struct program_det_segments_params program_det_segments_params; + struct update_dchubp_dpp_params update_dchubp_dpp_params; + struct opp_set_dyn_expansion_params opp_set_dyn_expansion_params; + struct opp_program_fmt_params opp_program_fmt_params; + struct opp_program_bit_depth_reduction_params opp_program_bit_depth_reduction_params; + struct opp_set_disp_pattern_generator_params opp_set_disp_pattern_generator_params; + struct set_abm_pipe_params set_abm_pipe_params; + struct set_abm_level_params set_abm_level_params; + struct set_abm_immediate_disable_params set_abm_immediate_disable_params; + struct set_disp_pattern_generator_params set_disp_pattern_generator_params; + struct mpc_remove_mpcc_params mpc_remove_mpcc_params; + struct opp_set_mpcc_disconnect_pending_params opp_set_mpcc_disconnect_pending_params; + struct dc_set_optimized_required_params dc_set_optimized_required_params; + struct hubp_disconnect_params hubp_disconnect_params; + struct hubbub_force_pstate_change_control_params hubbub_force_pstate_change_control_params; + struct tg_enable_crtc_params tg_enable_crtc_params; + struct hubp_wait_flip_pending_params hubp_wait_flip_pending_params; + struct tg_wait_double_buffer_pending_params tg_wait_double_buffer_pending_params; + struct update_force_pstate_params update_force_pstate_params; + struct hubbub_apply_dedcn21_147_wa_params hubbub_apply_dedcn21_147_wa_params; + struct hubbub_allow_self_refresh_control_params hubbub_allow_self_refresh_control_params; + struct tg_get_frame_count_params tg_get_frame_count_params; + struct mpc_set_dwb_mux_params mpc_set_dwb_mux_params; + struct mpc_disable_dwb_mux_params mpc_disable_dwb_mux_params; + struct mcif_wb_config_buf_params mcif_wb_config_buf_params; + struct mcif_wb_config_arb_params mcif_wb_config_arb_params; + struct mcif_wb_enable_params mcif_wb_enable_params; + struct mcif_wb_disable_params mcif_wb_disable_params; + struct dwbc_enable_params dwbc_enable_params; + struct dwbc_disable_params dwbc_disable_params; + struct dwbc_update_params dwbc_update_params; + struct hubp_update_mall_sel_params hubp_update_mall_sel_params; + struct hubp_prepare_subvp_buffering_params hubp_prepare_subvp_buffering_params; + struct hubp_set_blank_en_params hubp_set_blank_en_params; + struct hubp_disable_control_params hubp_disable_control_params; + struct hubbub_soft_reset_params hubbub_soft_reset_params; + struct hubp_clk_cntl_params hubp_clk_cntl_params; + struct hubp_init_params hubp_init_params; + struct hubp_set_vm_system_aperture_settings_params hubp_set_vm_system_aperture_settings_params; + struct hubp_set_flip_int_params hubp_set_flip_int_params; + struct dpp_dppclk_control_params dpp_dppclk_control_params; + struct disable_phantom_crtc_params disable_phantom_crtc_params; + struct dpp_pg_control_params dpp_pg_control_params; + struct hubp_pg_control_params hubp_pg_control_params; + struct hubp_reset_params hubp_reset_params; + struct dpp_reset_params dpp_reset_params; + struct dpp_root_clock_control_params dpp_root_clock_control_params; + struct dc_ip_request_cntl_params dc_ip_request_cntl_params; + struct dsc_pg_status_params dsc_pg_status_params; + struct dsc_wait_disconnect_pending_clear_params dsc_wait_disconnect_pending_clear_params; + struct dsc_disable_params dsc_disable_params; + struct dccg_set_ref_dscclk_params dccg_set_ref_dscclk_params; + struct dccg_update_dpp_dto_params dccg_update_dpp_dto_params; + struct hubp_vtg_sel_params hubp_vtg_sel_params; + struct hubp_setup2_params hubp_setup2_params; + struct hubp_setup_params hubp_setup_params; + struct hubp_set_unbounded_requesting_params hubp_set_unbounded_requesting_params; + struct hubp_setup_interdependent2_params hubp_setup_interdependent2_params; + struct hubp_setup_interdependent_params hubp_setup_interdependent_params; + struct dpp_set_cursor_matrix_params dpp_set_cursor_matrix_params; + struct mpc_update_mpcc_params mpc_update_mpcc_params; + struct mpc_update_blending_params mpc_update_blending_params; + struct mpc_assert_idle_mpcc_params mpc_assert_idle_mpcc_params; + struct mpc_insert_plane_params mpc_insert_plane_params; + struct dpp_set_scaler_params dpp_set_scaler_params; + struct hubp_mem_program_viewport_params hubp_mem_program_viewport_params; + struct set_cursor_attribute_params set_cursor_attribute_params; + struct set_cursor_position_params set_cursor_position_params; + struct set_cursor_sdr_white_level_params set_cursor_sdr_white_level_params; + struct program_output_csc_params program_output_csc_params; + struct hubp_set_blank_params hubp_set_blank_params; + struct phantom_hubp_post_enable_params phantom_hubp_post_enable_params; }; enum block_sequence_func { @@ -195,6 +863,7 @@ enum block_sequence_func { DPP_SETUP_DPP, DPP_PROGRAM_BIAS_AND_SCALE, DPP_SET_OUTPUT_TRANSFER_FUNC, + DPP_SET_HDR_MULTIPLIER, MPC_UPDATE_VISUAL_CONFIRM, MPC_POWER_ON_MPC_MEM_PWR, MPC_SET_OUTPUT_CSC, @@ -202,7 +871,102 @@ enum block_sequence_func { DMUB_SUBVP_SAVE_SURF_ADDR, HUBP_WAIT_FOR_DCC_META_PROP, DMUB_HW_CONTROL_LOCK_FAST, + HUBP_PROGRAM_SURFACE_CONFIG, + HUBP_PROGRAM_MCACHE_ID, PROGRAM_CURSOR_UPDATE_NOW, + HUBP_WAIT_PIPE_READ_START, + HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM, + HWS_UPDATE_PHANTOM_VP_POSITION, + OPTC_SET_ODM_COMBINE, + OPTC_SET_ODM_BYPASS, + OPP_PIPE_CLOCK_CONTROL, + OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL, + DCCG_SET_DTO_DSCCLK, + DSC_SET_CONFIG, + DSC_ENABLE, + TG_SET_DSC_CONFIG, + DSC_DISCONNECT, + DSC_READ_STATE, + DSC_CALCULATE_AND_SET_CONFIG, + DSC_ENABLE_WITH_OPP, + TG_PROGRAM_GLOBAL_SYNC, + TG_WAIT_FOR_STATE, + TG_SET_VTG_PARAMS, + TG_SETUP_VERTICAL_INTERRUPT2, + HUBP_PROGRAM_DET_SIZE, + HUBP_PROGRAM_DET_SEGMENTS, + OPP_SET_DYN_EXPANSION, + OPP_PROGRAM_FMT, + OPP_PROGRAM_BIT_DEPTH_REDUCTION, + OPP_SET_DISP_PATTERN_GENERATOR, + ABM_SET_PIPE, + ABM_SET_LEVEL, + ABM_SET_IMMEDIATE_DISABLE, + MPC_REMOVE_MPCC, + OPP_SET_MPCC_DISCONNECT_PENDING, + DC_SET_OPTIMIZED_REQUIRED, + HUBP_DISCONNECT, + HUBBUB_FORCE_PSTATE_CHANGE_CONTROL, + TG_ENABLE_CRTC, + TG_SET_GSL, + TG_SET_GSL_SOURCE_SELECT, + HUBP_WAIT_FLIP_PENDING, + TG_WAIT_DOUBLE_BUFFER_PENDING, + UPDATE_FORCE_PSTATE, + PROGRAM_MALL_PIPE_CONFIG, + HUBBUB_APPLY_DEDCN21_147_WA, + HUBBUB_ALLOW_SELF_REFRESH_CONTROL, + TG_GET_FRAME_COUNT, + MPC_SET_DWB_MUX, + MPC_DISABLE_DWB_MUX, + MCIF_WB_CONFIG_BUF, + MCIF_WB_CONFIG_ARB, + MCIF_WB_ENABLE, + MCIF_WB_DISABLE, + DWBC_ENABLE, + DWBC_DISABLE, + DWBC_UPDATE, + HUBP_UPDATE_MALL_SEL, + HUBP_PREPARE_SUBVP_BUFFERING, + HUBP_SET_BLANK_EN, + HUBP_DISABLE_CONTROL, + HUBBUB_SOFT_RESET, + HUBP_CLK_CNTL, + HUBP_INIT, + HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS, + HUBP_SET_FLIP_INT, + DPP_DPPCLK_CONTROL, + DISABLE_PHANTOM_CRTC, + DSC_PG_STATUS, + DSC_WAIT_DISCONNECT_PENDING_CLEAR, + DSC_DISABLE, + DCCG_SET_REF_DSCCLK, + DPP_PG_CONTROL, + HUBP_PG_CONTROL, + HUBP_RESET, + DPP_RESET, + DPP_ROOT_CLOCK_CONTROL, + DC_IP_REQUEST_CNTL, + DCCG_UPDATE_DPP_DTO, + HUBP_VTG_SEL, + HUBP_SETUP2, + HUBP_SETUP, + HUBP_SET_UNBOUNDED_REQUESTING, + HUBP_SETUP_INTERDEPENDENT2, + HUBP_SETUP_INTERDEPENDENT, + DPP_SET_CURSOR_MATRIX, + MPC_UPDATE_BLENDING, + MPC_ASSERT_IDLE_MPCC, + MPC_INSERT_PLANE, + DPP_SET_SCALER, + HUBP_MEM_PROGRAM_VIEWPORT, + SET_CURSOR_ATTRIBUTE, + SET_CURSOR_POSITION, + SET_CURSOR_SDR_WHITE_LEVEL, + PROGRAM_OUTPUT_CSC, + HUBP_SET_LEGACY_TILING_COMPAT_LEVEL, + HUBP_SET_BLANK, + PHANTOM_HUBP_POST_ENABLE, /* This must be the last value in this enum, add new ones above */ HWSS_BLOCK_SEQUENCE_FUNC_COUNT }; @@ -212,6 +976,11 @@ struct block_sequence { enum block_sequence_func func; }; +struct block_sequence_state { + struct block_sequence *steps; + unsigned int *num_steps; +}; + #define MAX_HWSS_BLOCK_SEQUENCE_SIZE (HWSS_BLOCK_SEQUENCE_FUNC_COUNT * MAX_PIPES) struct hw_sequencer_funcs { @@ -229,6 +998,8 @@ struct hw_sequencer_funcs { enum dc_status (*apply_ctx_to_hw)(struct dc *dc, struct dc_state *context); void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx); + void (*disable_plane_sequence)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx, + struct block_sequence_state *seq_state); void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank); void (*apply_ctx_for_surface)(struct dc *dc, const struct dc_stream_state *stream, @@ -246,6 +1017,10 @@ struct hw_sequencer_funcs { void (*wait_for_mpcc_disconnect)(struct dc *dc, struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx); + void (*wait_for_mpcc_disconnect_sequence)(struct dc *dc, + struct resource_pool *res_pool, + struct pipe_ctx *pipe_ctx, + struct block_sequence_state *seq_state); void (*edp_backlight_control)( struct dc_link *link, bool enable); @@ -485,11 +1260,23 @@ struct hw_sequencer_funcs { void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_state *context); + void (*enable_plane_sequence)(struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_state *context, + struct block_sequence_state *seq_state); void (*update_dchubp_dpp)(struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_state *context); + void (*update_dchubp_dpp_sequence)(struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_state *context, + struct block_sequence_state *seq_state); void (*post_unlock_reset_opp)(struct dc *dc, struct pipe_ctx *opp_head); + void (*post_unlock_reset_opp_sequence)( + struct dc *dc, + struct pipe_ctx *opp_head, + struct block_sequence_state *seq_state); void (*get_underflow_debug_data)(const struct dc *dc, struct timing_generator *tg, struct dc_underflow_debug_data *out_data); @@ -602,4 +1389,624 @@ void hwss_set_ocsc_default(union block_sequence_params *params); void hwss_subvp_save_surf_addr(union block_sequence_params *params); +void hwss_program_surface_config(union block_sequence_params *params); + +void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *params); + +void hwss_set_odm_combine(union block_sequence_params *params); + +void hwss_set_odm_bypass(union block_sequence_params *params); + +void hwss_opp_pipe_clock_control(union block_sequence_params *params); + +void hwss_opp_program_left_edge_extra_pixel(union block_sequence_params *params); + +void hwss_blank_pixel_data(union block_sequence_params *params); + +void hwss_dccg_set_dto_dscclk(union block_sequence_params *params); + +void hwss_dsc_set_config(union block_sequence_params *params); + +void hwss_dsc_enable(union block_sequence_params *params); + +void hwss_tg_set_dsc_config(union block_sequence_params *params); + +void hwss_dsc_disconnect(union block_sequence_params *params); + +void hwss_dsc_read_state(union block_sequence_params *params); + +void hwss_dsc_calculate_and_set_config(union block_sequence_params *params); + +void hwss_dsc_enable_with_opp(union block_sequence_params *params); + +void hwss_program_tg(union block_sequence_params *params); + +void hwss_tg_program_global_sync(union block_sequence_params *params); + +void hwss_tg_wait_for_state(union block_sequence_params *params); + +void hwss_tg_set_vtg_params(union block_sequence_params *params); + +void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params); + +void hwss_dpp_set_hdr_multiplier(union block_sequence_params *params); + +void hwss_program_det_size(union block_sequence_params *params); + +void hwss_program_det_segments(union block_sequence_params *params); + +void hwss_opp_set_dyn_expansion(union block_sequence_params *params); + +void hwss_opp_program_fmt(union block_sequence_params *params); + +void hwss_opp_program_bit_depth_reduction(union block_sequence_params *params); + +void hwss_opp_set_disp_pattern_generator(union block_sequence_params *params); + +void hwss_set_abm_pipe(union block_sequence_params *params); + +void hwss_set_abm_level(union block_sequence_params *params); + +void hwss_set_abm_immediate_disable(union block_sequence_params *params); + +void hwss_mpc_remove_mpcc(union block_sequence_params *params); + +void hwss_opp_set_mpcc_disconnect_pending(union block_sequence_params *params); + +void hwss_dc_set_optimized_required(union block_sequence_params *params); + +void hwss_hubp_disconnect(union block_sequence_params *params); + +void hwss_hubbub_force_pstate_change_control(union block_sequence_params *params); + +void hwss_tg_enable_crtc(union block_sequence_params *params); + +void hwss_tg_set_gsl(union block_sequence_params *params); + +void hwss_tg_set_gsl_source_select(union block_sequence_params *params); + +void hwss_hubp_wait_flip_pending(union block_sequence_params *params); + +void hwss_tg_wait_double_buffer_pending(union block_sequence_params *params); + +void hwss_update_force_pstate(union block_sequence_params *params); + +void hwss_hubbub_apply_dedcn21_147_wa(union block_sequence_params *params); + +void hwss_hubbub_allow_self_refresh_control(union block_sequence_params *params); + +void hwss_tg_get_frame_count(union block_sequence_params *params); + +void hwss_mpc_set_dwb_mux(union block_sequence_params *params); + +void hwss_mpc_disable_dwb_mux(union block_sequence_params *params); + +void hwss_mcif_wb_config_buf(union block_sequence_params *params); + +void hwss_mcif_wb_config_arb(union block_sequence_params *params); + +void hwss_mcif_wb_enable(union block_sequence_params *params); + +void hwss_mcif_wb_disable(union block_sequence_params *params); + +void hwss_dwbc_enable(union block_sequence_params *params); + +void hwss_dwbc_disable(union block_sequence_params *params); + +void hwss_dwbc_update(union block_sequence_params *params); + +void hwss_hubp_update_mall_sel(union block_sequence_params *params); + +void hwss_hubp_prepare_subvp_buffering(union block_sequence_params *params); + +void hwss_hubp_set_blank_en(union block_sequence_params *params); + +void hwss_hubp_disable_control(union block_sequence_params *params); + +void hwss_hubbub_soft_reset(union block_sequence_params *params); + +void hwss_hubp_clk_cntl(union block_sequence_params *params); + +void hwss_hubp_init(union block_sequence_params *params); + +void hwss_hubp_set_vm_system_aperture_settings(union block_sequence_params *params); + +void hwss_hubp_set_flip_int(union block_sequence_params *params); + +void hwss_dpp_dppclk_control(union block_sequence_params *params); + +void hwss_disable_phantom_crtc(union block_sequence_params *params); + +void hwss_dsc_pg_status(union block_sequence_params *params); + +void hwss_dsc_wait_disconnect_pending_clear(union block_sequence_params *params); + +void hwss_dsc_disable(union block_sequence_params *params); + +void hwss_dccg_set_ref_dscclk(union block_sequence_params *params); + +void hwss_dpp_pg_control(union block_sequence_params *params); + +void hwss_hubp_pg_control(union block_sequence_params *params); + +void hwss_hubp_reset(union block_sequence_params *params); + +void hwss_dpp_reset(union block_sequence_params *params); + +void hwss_dpp_root_clock_control(union block_sequence_params *params); + +void hwss_dc_ip_request_cntl(union block_sequence_params *params); + +void hwss_dccg_update_dpp_dto(union block_sequence_params *params); + +void hwss_hubp_vtg_sel(union block_sequence_params *params); + +void hwss_hubp_setup2(union block_sequence_params *params); + +void hwss_hubp_setup(union block_sequence_params *params); + +void hwss_hubp_set_unbounded_requesting(union block_sequence_params *params); + +void hwss_hubp_setup_interdependent2(union block_sequence_params *params); + +void hwss_hubp_setup_interdependent(union block_sequence_params *params); + +void hwss_dpp_set_cursor_matrix(union block_sequence_params *params); + +void hwss_mpc_update_mpcc(union block_sequence_params *params); + +void hwss_mpc_update_blending(union block_sequence_params *params); + +void hwss_mpc_assert_idle_mpcc(union block_sequence_params *params); + +void hwss_mpc_insert_plane(union block_sequence_params *params); + +void hwss_dpp_set_scaler(union block_sequence_params *params); + +void hwss_hubp_mem_program_viewport(union block_sequence_params *params); + +void hwss_set_cursor_attribute(union block_sequence_params *params); + +void hwss_set_cursor_position(union block_sequence_params *params); + +void hwss_set_cursor_sdr_white_level(union block_sequence_params *params); + +void hwss_program_output_csc(union block_sequence_params *params); + +void hwss_hubp_set_legacy_tiling_compat_level(union block_sequence_params *params); + +void hwss_hubp_set_blank(union block_sequence_params *params); + +void hwss_phantom_hubp_post_enable(union block_sequence_params *params); + +void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state, + struct dc *dc, struct pipe_ctx *pipe_ctx, bool lock); + +void hwss_add_hubp_set_flip_control_gsl(struct block_sequence_state *seq_state, + struct hubp *hubp, bool flip_immediate); + +void hwss_add_hubp_program_triplebuffer(struct block_sequence_state *seq_state, + struct dc *dc, struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); + +void hwss_add_hubp_update_plane_addr(struct block_sequence_state *seq_state, + struct dc *dc, struct pipe_ctx *pipe_ctx); + +void hwss_add_dpp_set_input_transfer_func(struct block_sequence_state *seq_state, + struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state); + +void hwss_add_dpp_program_gamut_remap(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_dpp_program_bias_and_scale(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_optc_program_manual_trigger(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_dpp_set_output_transfer_func(struct block_sequence_state *seq_state, + struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_stream_state *stream); + +void hwss_add_mpc_update_visual_confirm(struct block_sequence_state *seq_state, + struct dc *dc, struct pipe_ctx *pipe_ctx, int mpcc_id); + +void hwss_add_mpc_power_on_mpc_mem_pwr(struct block_sequence_state *seq_state, + struct mpc *mpc, int mpcc_id, bool power_on); + +void hwss_add_mpc_set_output_csc(struct block_sequence_state *seq_state, + struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode); + +void hwss_add_mpc_set_ocsc_default(struct block_sequence_state *seq_state, + struct mpc *mpc, int opp_id, enum dc_color_space colorspace, enum mpc_output_csc_mode ocsc_mode); + +void hwss_add_dmub_send_dmcub_cmd(struct block_sequence_state *seq_state, + struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type); + +void hwss_add_dmub_subvp_save_surf_addr(struct block_sequence_state *seq_state, + struct dc_dmub_srv *dc_dmub_srv, struct dc_plane_address *addr, uint8_t subvp_index); + +void hwss_add_hubp_wait_for_dcc_meta_prop(struct block_sequence_state *seq_state, + struct dc *dc, struct pipe_ctx *top_pipe_to_program); + +void hwss_add_hubp_wait_pipe_read_start(struct block_sequence_state *seq_state, + struct hubp *hubp); + +void hwss_add_hws_apply_update_flags_for_phantom(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_hws_update_phantom_vp_position(struct block_sequence_state *seq_state, + struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); + +void hwss_add_optc_set_odm_combine(struct block_sequence_state *seq_state, + struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count, + int odm_slice_width, int last_odm_slice_width); + +void hwss_add_optc_set_odm_bypass(struct block_sequence_state *seq_state, + struct timing_generator *optc, struct dc_crtc_timing *timing); + +void hwss_add_tg_program_global_sync(struct block_sequence_state *seq_state, + struct timing_generator *tg, + int vready_offset, + unsigned int vstartup_lines, + unsigned int vupdate_offset_pixels, + unsigned int vupdate_vupdate_width_pixels, + unsigned int pstate_keepout_start_lines); + +void hwss_add_tg_wait_for_state(struct block_sequence_state *seq_state, + struct timing_generator *tg, enum crtc_state state); + +void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state, + struct timing_generator *tg, struct dc_crtc_timing *dc_crtc_timing, bool program_fp2); + +void hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state *seq_state, + struct timing_generator *tg, int start_line); + +void hwss_add_dpp_set_hdr_multiplier(struct block_sequence_state *seq_state, + struct dpp *dpp, uint32_t hw_mult); + +void hwss_add_hubp_program_det_size(struct block_sequence_state *seq_state, + struct hubbub *hubbub, unsigned int hubp_inst, unsigned int det_buffer_size_kb); + +void hwss_add_hubp_program_mcache_id(struct block_sequence_state *seq_state, + struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs); + +void hwss_add_hubbub_force_pstate_change_control(struct block_sequence_state *seq_state, + struct hubbub *hubbub, bool enable, bool wait); + +void hwss_add_hubp_program_det_segments(struct block_sequence_state *seq_state, + struct hubbub *hubbub, unsigned int hubp_inst, unsigned int det_size); + +void hwss_add_opp_set_dyn_expansion(struct block_sequence_state *seq_state, + struct output_pixel_processor *opp, enum dc_color_space color_sp, + enum dc_color_depth color_dpth, enum signal_type signal); + +void hwss_add_opp_program_fmt(struct block_sequence_state *seq_state, + struct output_pixel_processor *opp, struct bit_depth_reduction_params *fmt_bit_depth, + struct clamping_and_pixel_encoding_params *clamping); + +void hwss_add_abm_set_pipe(struct block_sequence_state *seq_state, + struct dc *dc, struct pipe_ctx *pipe_ctx); + +void hwss_add_abm_set_level(struct block_sequence_state *seq_state, + struct abm *abm, uint32_t abm_level); + +void hwss_add_tg_enable_crtc(struct block_sequence_state *seq_state, + struct timing_generator *tg); + +void hwss_add_hubp_wait_flip_pending(struct block_sequence_state *seq_state, + struct hubp *hubp, unsigned int timeout_us, unsigned int polling_interval_us); + +void hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state *seq_state, + struct timing_generator *tg, unsigned int timeout_us, unsigned int polling_interval_us); + +void hwss_add_dccg_set_dto_dscclk(struct block_sequence_state *seq_state, + struct dccg *dccg, int inst, int num_slices_h); + +void hwss_add_dsc_calculate_and_set_config(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx, bool enable, int opp_cnt); + +void hwss_add_mpc_remove_mpcc(struct block_sequence_state *seq_state, + struct mpc *mpc, struct mpc_tree *mpc_tree_params, struct mpcc *mpcc_to_remove); + +void hwss_add_opp_set_mpcc_disconnect_pending(struct block_sequence_state *seq_state, + struct output_pixel_processor *opp, int mpcc_inst, bool pending); + +void hwss_add_hubp_disconnect(struct block_sequence_state *seq_state, + struct hubp *hubp); + +void hwss_add_dsc_enable_with_opp(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_dsc_disconnect(struct block_sequence_state *seq_state, + struct display_stream_compressor *dsc); + +void hwss_add_dc_set_optimized_required(struct block_sequence_state *seq_state, + struct dc *dc, bool optimized_required); + +void hwss_add_abm_set_immediate_disable(struct block_sequence_state *seq_state, + struct dc *dc, struct pipe_ctx *pipe_ctx); + +void hwss_add_opp_set_disp_pattern_generator(struct block_sequence_state *seq_state, + struct output_pixel_processor *opp, + enum controller_dp_test_pattern test_pattern, + enum controller_dp_color_space color_space, + enum dc_color_depth color_depth, + struct tg_color solid_color, + bool use_solid_color, + int width, + int height, + int offset); + +void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_state, + struct output_pixel_processor *opp, + bool use_default_params, + struct pipe_ctx *pipe_ctx); + +void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state, + struct dc *dc, + bool enable); + +void hwss_add_dwbc_update(struct block_sequence_state *seq_state, + struct dwbc *dwb, + struct dc_dwb_params *dwb_params); + +void hwss_add_mcif_wb_config_buf(struct block_sequence_state *seq_state, + struct mcif_wb *mcif_wb, + struct mcif_buf_params *mcif_buf_params, + unsigned int dest_height); + +void hwss_add_mcif_wb_config_arb(struct block_sequence_state *seq_state, + struct mcif_wb *mcif_wb, + struct mcif_arb_params *mcif_arb_params); + +void hwss_add_mcif_wb_enable(struct block_sequence_state *seq_state, + struct mcif_wb *mcif_wb); + +void hwss_add_mcif_wb_disable(struct block_sequence_state *seq_state, + struct mcif_wb *mcif_wb); + +void hwss_add_mpc_set_dwb_mux(struct block_sequence_state *seq_state, + struct mpc *mpc, + int dwb_id, + int mpcc_id); + +void hwss_add_mpc_disable_dwb_mux(struct block_sequence_state *seq_state, + struct mpc *mpc, + unsigned int dwb_id); + +void hwss_add_dwbc_enable(struct block_sequence_state *seq_state, + struct dwbc *dwb, + struct dc_dwb_params *dwb_params); + +void hwss_add_dwbc_disable(struct block_sequence_state *seq_state, + struct dwbc *dwb); + +void hwss_add_tg_set_gsl(struct block_sequence_state *seq_state, + struct timing_generator *tg, + struct gsl_params gsl); + +void hwss_add_tg_set_gsl_source_select(struct block_sequence_state *seq_state, + struct timing_generator *tg, + int group_idx, + uint32_t gsl_ready_signal); + +void hwss_add_hubp_update_mall_sel(struct block_sequence_state *seq_state, + struct hubp *hubp, + uint32_t mall_sel, + bool cache_cursor); + +void hwss_add_hubp_prepare_subvp_buffering(struct block_sequence_state *seq_state, + struct hubp *hubp, + bool enable); + +void hwss_add_hubp_set_blank_en(struct block_sequence_state *seq_state, + struct hubp *hubp, + bool enable); + +void hwss_add_hubp_disable_control(struct block_sequence_state *seq_state, + struct hubp *hubp, + bool disable); + +void hwss_add_hubbub_soft_reset(struct block_sequence_state *seq_state, + struct hubbub *hubbub, + void (*hubbub_soft_reset)(struct hubbub *hubbub, bool reset), + bool reset); + +void hwss_add_hubp_clk_cntl(struct block_sequence_state *seq_state, + struct hubp *hubp, + bool enable); + +void hwss_add_dpp_dppclk_control(struct block_sequence_state *seq_state, + struct dpp *dpp, + bool dppclk_div, + bool enable); + +void hwss_add_disable_phantom_crtc(struct block_sequence_state *seq_state, + struct timing_generator *tg); + +void hwss_add_dsc_pg_status(struct block_sequence_state *seq_state, + struct dce_hwseq *hws, + int dsc_inst, + bool is_ungated); + +void hwss_add_dsc_wait_disconnect_pending_clear(struct block_sequence_state *seq_state, + struct display_stream_compressor *dsc, + bool *is_ungated); + +void hwss_add_dsc_disable(struct block_sequence_state *seq_state, + struct display_stream_compressor *dsc, + bool *is_ungated); + +void hwss_add_dccg_set_ref_dscclk(struct block_sequence_state *seq_state, + struct dccg *dccg, + int dsc_inst, + bool *is_ungated); + +void hwss_add_dpp_root_clock_control(struct block_sequence_state *seq_state, + struct dce_hwseq *hws, + unsigned int dpp_inst, + bool clock_on); + +void hwss_add_dpp_pg_control(struct block_sequence_state *seq_state, + struct dce_hwseq *hws, + unsigned int dpp_inst, + bool power_on); + +void hwss_add_hubp_pg_control(struct block_sequence_state *seq_state, + struct dce_hwseq *hws, + unsigned int hubp_inst, + bool power_on); + +void hwss_add_hubp_set_blank(struct block_sequence_state *seq_state, + struct hubp *hubp, + bool blank); + +void hwss_add_hubp_init(struct block_sequence_state *seq_state, + struct hubp *hubp); + +void hwss_add_hubp_reset(struct block_sequence_state *seq_state, + struct hubp *hubp); + +void hwss_add_dpp_reset(struct block_sequence_state *seq_state, + struct dpp *dpp); + +void hwss_add_opp_pipe_clock_control(struct block_sequence_state *seq_state, + struct output_pixel_processor *opp, + bool enable); + +void hwss_add_hubp_set_vm_system_aperture_settings(struct block_sequence_state *seq_state, + struct hubp *hubp, + uint64_t sys_default, + uint64_t sys_low, + uint64_t sys_high); + +void hwss_add_hubp_set_flip_int(struct block_sequence_state *seq_state, + struct hubp *hubp); + +void hwss_add_dccg_update_dpp_dto(struct block_sequence_state *seq_state, + struct dccg *dccg, + int dpp_inst, + int dppclk_khz); + +void hwss_add_hubp_vtg_sel(struct block_sequence_state *seq_state, + struct hubp *hubp, + uint32_t otg_inst); + +void hwss_add_hubp_setup2(struct block_sequence_state *seq_state, + struct hubp *hubp, + struct dml2_dchub_per_pipe_register_set *hubp_regs, + union dml2_global_sync_programming *global_sync, + struct dc_crtc_timing *timing); + +void hwss_add_hubp_setup(struct block_sequence_state *seq_state, + struct hubp *hubp, + struct _vcs_dpi_display_dlg_regs_st *dlg_regs, + struct _vcs_dpi_display_ttu_regs_st *ttu_regs, + struct _vcs_dpi_display_rq_regs_st *rq_regs, + struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); + +void hwss_add_hubp_set_unbounded_requesting(struct block_sequence_state *seq_state, + struct hubp *hubp, + bool unbounded_req); + +void hwss_add_hubp_setup_interdependent2(struct block_sequence_state *seq_state, + struct hubp *hubp, + struct dml2_dchub_per_pipe_register_set *hubp_regs); + +void hwss_add_hubp_setup_interdependent(struct block_sequence_state *seq_state, + struct hubp *hubp, + struct _vcs_dpi_display_dlg_regs_st *dlg_regs, + struct _vcs_dpi_display_ttu_regs_st *ttu_regs); +void hwss_add_hubp_program_surface_config(struct block_sequence_state *seq_state, + struct hubp *hubp, + enum surface_pixel_format format, + struct dc_tiling_info *tiling_info, + struct plane_size plane_size, + enum dc_rotation_angle rotation, + struct dc_plane_dcc_param *dcc, + bool horizontal_mirror, + int compat_level); + +void hwss_add_dpp_setup_dpp(struct block_sequence_state *seq_state, + struct pipe_ctx *pipe_ctx); + +void hwss_add_dpp_set_cursor_matrix(struct block_sequence_state *seq_state, + struct dpp *dpp, + enum dc_color_space color_space, + struct dc_csc_transform *cursor_csc_color_matrix); + +void hwss_add_mpc_update_blending(struct block_sequence_state *seq_state, + struct mpc *mpc, + struct mpcc_blnd_cfg blnd_cfg, + int mpcc_id); + +void hwss_add_mpc_assert_idle_mpcc(struct block_sequence_state *seq_state, + struct mpc *mpc, + int mpcc_id); + +void hwss_add_mpc_insert_plane(struct block_sequence_state *seq_state, + struct mpc *mpc, + struct mpc_tree *mpc_tree_params, + struct mpcc_blnd_cfg blnd_cfg, + struct mpcc_sm_cfg *sm_cfg, + struct mpcc *insert_above_mpcc, + int dpp_id, + int mpcc_id); + +void hwss_add_dpp_set_scaler(struct block_sequence_state *seq_state, + struct dpp *dpp, + const struct scaler_data *scl_data); + +void hwss_add_hubp_mem_program_viewport(struct block_sequence_state *seq_state, + struct hubp *hubp, + const struct rect *viewport, + const struct rect *viewport_c); + +void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx); + +void hwss_add_set_cursor_position(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx); + +void hwss_add_set_cursor_sdr_white_level(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx); + +void hwss_add_program_output_csc(struct block_sequence_state *seq_state, + struct dc *dc, + struct pipe_ctx *pipe_ctx, + enum dc_color_space colorspace, + uint16_t *matrix, + int opp_id); + +void hwss_add_phantom_hubp_post_enable(struct block_sequence_state *seq_state, + struct hubp *hubp); + +void hwss_add_update_force_pstate(struct block_sequence_state *seq_state, + struct dc *dc, + struct dc_state *context); + +void hwss_add_hubbub_apply_dedcn21_147_wa(struct block_sequence_state *seq_state, + struct hubbub *hubbub); + +void hwss_add_hubbub_allow_self_refresh_control(struct block_sequence_state *seq_state, + struct hubbub *hubbub, + bool allow, + bool *disallow_self_refresh_applied); + +void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state, + struct timing_generator *tg, + unsigned int *frame_count); + +void hwss_add_tg_set_dsc_config(struct block_sequence_state *seq_state, + struct timing_generator *tg, + struct dsc_optc_config *dsc_optc_cfg, + bool enable); + +void hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state *seq_state, + struct output_pixel_processor *opp, + enum dc_pixel_encoding pixel_encoding, + bool is_otg_master); + #endif /* __DC_HW_SEQUENCER_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h index 1e2d247fbbacd..406db231bc72a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h @@ -27,6 +27,7 @@ #define __DC_HW_SEQUENCER_PRIVATE_H__ #include "dc_types.h" +#include "hw_sequencer.h" enum pipe_gating_control { PIPE_GATING_CONTROL_DISABLE = 0, @@ -80,7 +81,13 @@ struct hwseq_private_funcs { void (*plane_atomic_disconnect)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx); + void (*plane_atomic_disconnect_sequence)(struct dc *dc, + struct dc_state *state, + struct pipe_ctx *pipe_ctx, + struct block_sequence_state *seq_state); void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx); + void (*update_mpcc_sequence)(struct dc *dc, struct pipe_ctx *pipe_ctx, + struct block_sequence_state *seq_state); bool (*set_input_transfer_func)(struct dc *dc, struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state); @@ -97,6 +104,10 @@ struct hwseq_private_funcs { void (*blank_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank); + void (*blank_pixel_data_sequence)(struct dc *dc, + struct pipe_ctx *pipe_ctx, + bool blank, + struct block_sequence_state *seq_state); enum dc_status (*enable_stream_timing)( struct pipe_ctx *pipe_ctx, struct dc_state *context, @@ -105,6 +116,8 @@ struct hwseq_private_funcs { bool enable); void (*setup_vupdate_interrupt)(struct dc *dc, struct pipe_ctx *pipe_ctx); + void (*setup_vupdate_interrupt_sequence)(struct dc *dc, struct pipe_ctx *pipe_ctx, + struct block_sequence_state *seq_state); bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx); void (*init_blank)(struct dc *dc, struct timing_generator *tg); void (*disable_vga)(struct dce_hwseq *hws); @@ -112,6 +125,10 @@ struct hwseq_private_funcs { void (*plane_atomic_power_down)(struct dc *dc, struct dpp *dpp, struct hubp *hubp); + void (*plane_atomic_power_down_sequence)(struct dc *dc, + struct dpp *dpp, + struct hubp *hubp, + struct block_sequence_state *seq_state); void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx); void (*enable_power_gating_plane)(struct dce_hwseq *hws, bool enable); @@ -140,15 +157,31 @@ struct hwseq_private_funcs { unsigned int dsc_inst); void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); + void (*update_odm_sequence)(struct dc *dc, struct dc_state *context, + struct pipe_ctx *pipe_ctx, struct block_sequence_state *seq_state); void (*program_all_writeback_pipes_in_tree)(struct dc *dc, const struct dc_stream_state *stream, struct dc_state *context); + void (*program_all_writeback_pipes_in_tree_sequence)( + struct dc *dc, + const struct dc_stream_state *stream, + struct dc_state *context, + struct block_sequence_state *seq_state); bool (*s0i3_golden_init_wa)(struct dc *dc); void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx); + void (*set_hdr_multiplier_sequence)(struct pipe_ctx *pipe_ctx, + struct block_sequence_state *seq_state); void (*verify_allow_pstate_change_high)(struct dc *dc); + void (*verify_allow_pstate_change_high_sequence)(struct dc *dc, + struct block_sequence_state *seq_state); void (*program_pipe)(struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_state *context); + void (*program_pipe_sequence)( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_state *context, + struct block_sequence_state *seq_state); bool (*wait_for_blank_complete)(struct output_pixel_processor *opp); void (*dccg_init)(struct dce_hwseq *hws); bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx, @@ -163,6 +196,8 @@ struct hwseq_private_funcs { void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_state *context); void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context); + void (*program_mall_pipe_config_sequence)(struct dc *dc, struct dc_state *context, + struct block_sequence_state *seq_state); void (*update_force_pstate)(struct dc *dc, struct dc_state *context); void (*update_mall_sel)(struct dc *dc, struct dc_state *context); unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx, @@ -186,6 +221,7 @@ struct hwseq_private_funcs { void (*perform_3dlut_wa_unlock)(struct pipe_ctx *pipe_ctx); void (*wait_for_pipe_update_if_needed)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only); void (*set_wait_for_update_needed_for_pipe)(struct dc *dc, struct pipe_ctx *pipe_ctx); + void (*dc_ip_request_cntl)(struct dc *dc, bool enable); }; struct dce_hwseq { From b0914d36fe0ce91d4d653970dbcdd65d22cd768e Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 3 Oct 2025 16:19:27 -0400 Subject: [PATCH 2265/2653] drm/amd/display: [FW Promotion] Release 0.1.31.0 Release highlights: DCN35/351/36: * fix video lag with replay * DPP DTO programming sequence fix * IPS exit programming sequence fix DCN 3.1.5: * fix video lag with replay Signed-off-by: Taimur Hassan Signed-off-by: Aurabindo Pillai Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 5df050a906344..c0a833ae606b0 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -973,7 +973,8 @@ union dmub_fw_boot_options { uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ uint32_t override_hbr3_pll_vco: 1; /**< 1 to override the hbr3 pll vco to 0 */ - uint32_t reserved : 5; /**< reserved */ + uint32_t disable_dpia_bw_allocation: 1; /**< 1 to disable the USB4 DPIA BW allocation */ + uint32_t reserved : 4; /**< reserved */ } bits; /**< boot bits */ uint32_t all; /**< 32-bit access to bits */ }; From b0f69818a6b913c5608842325fb16bb09f461fbe Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 3 Oct 2025 18:31:30 -0500 Subject: [PATCH 2266/2653] drm/amd/display: Promote DC to 3.2.354 Display Core v3.2.354 release highlights: * DCN35 dispclk, dppclk & other fixes * DCN401 cursor offload fix * Add new block seqeunce-building/executing functions * null ptr fixes * DPIA hpd fix * debug improvements * Fix performance regression from full updates * Firmware Release 0.1.31.0 Signed-off-by: Taimur Hassan Signed-off-by: Aurabindo Pillai Reviewed-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 021bfdb1d3a65..196b1416c4b91 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.353" +#define DC_VER "3.2.354" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From a279ec82c5272e0b28db86820554e85fea823744 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Thu, 11 Sep 2025 12:41:40 +0100 Subject: [PATCH 2267/2653] drm/amdgpu: Use memset32 for IB padding Use memset32 instead of open coding it, just because it is that bit nicer. Signed-off-by: Tvrtko Ursulin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 59d8632b7bc13..bf6f1a8827880 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -159,8 +159,16 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) */ void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) { - while (ib->length_dw & ring->funcs->align_mask) - ib->ptr[ib->length_dw++] = ring->funcs->nop; + u32 align_mask = ring->funcs->align_mask; + u32 count = ib->length_dw & align_mask; + + if (count) { + count = align_mask + 1 - count; + + memset32(&ib->ptr[ib->length_dw], ring->funcs->nop, count); + + ib->length_dw += count; + } } /** From 94bfe61749ba3778e6ab0b186ff0ea2c5dc0bc95 Mon Sep 17 00:00:00 2001 From: Ilya Zlobintsev Date: Mon, 13 Oct 2025 19:30:42 +0300 Subject: [PATCH 2268/2653] drm/amd/pm: Avoid writing nulls into `pp_od_clk_voltage` Calling `smu_cmn_get_sysfs_buf` aligns the offset used by `sysfs_emit_at` to the current page boundary, which was previously directly returned from the various `print_clk_levels` implementations to be added to the buffer position. Instead, only the relative offset showing how much was written to the buffer should be returned, regardless of how it was changed for alignment purposes. Reviewed-by: Lijo Lazar Signed-off-by: Ilya Zlobintsev Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 5 +++-- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 15 ++++++++------- .../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 5 +++-- drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 10 ++++++---- drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 7 ++++--- .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 7 ++++--- .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 5 +++-- .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 5 +++-- .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 7 ++++--- .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 7 ++++--- .../gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 5 +++-- .../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 5 +++-- .../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 7 ++++--- 13 files changed, 52 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c index 9548bd3c624bd..55401e6b2b0be 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c @@ -291,11 +291,12 @@ static int cyan_skillfish_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) { - int ret = 0, size = 0; + int ret = 0, size = 0, start_offset = 0; uint32_t cur_value = 0; int i; smu_cmn_get_sysfs_buf(&buf, &size); + start_offset = size; switch (clk_type) { case SMU_OD_SCLK: @@ -353,7 +354,7 @@ static int cyan_skillfish_print_clk_levels(struct smu_context *smu, return ret; } - return size; + return size - start_offset; } static bool cyan_skillfish_is_dpm_running(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index 0028f10ead423..bbf09aec91525 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -1469,7 +1469,7 @@ static int navi10_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) { uint16_t *curve_settings; - int i, levels, size = 0, ret = 0; + int i, levels, size = 0, ret = 0, start_offset = 0; uint32_t cur_value = 0, value = 0, count = 0; uint32_t freq_values[3] = {0}; uint32_t mark_index = 0; @@ -1484,6 +1484,7 @@ static int navi10_print_clk_levels(struct smu_context *smu, uint32_t min_value, max_value; smu_cmn_get_sysfs_buf(&buf, &size); + start_offset = size; switch (clk_type) { case SMU_GFXCLK: @@ -1497,11 +1498,11 @@ static int navi10_print_clk_levels(struct smu_context *smu, case SMU_DCEFCLK: ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); if (ret) - return size; + return size - start_offset; ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); if (ret) - return size; + return size - start_offset; ret = navi10_is_support_fine_grained_dpm(smu, clk_type); if (ret < 0) @@ -1511,7 +1512,7 @@ static int navi10_print_clk_levels(struct smu_context *smu, for (i = 0; i < count; i++) { ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); if (ret) - return size; + return size - start_offset; size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, cur_value == value ? "*" : ""); @@ -1519,10 +1520,10 @@ static int navi10_print_clk_levels(struct smu_context *smu, } else { ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); if (ret) - return size; + return size - start_offset; ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); if (ret) - return size; + return size - start_offset; freq_values[1] = cur_value; mark_index = cur_value == freq_values[0] ? 0 : @@ -1653,7 +1654,7 @@ static int navi10_print_clk_levels(struct smu_context *smu, break; } - return size; + return size - start_offset; } static int navi10_force_clk_levels(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 4ce4c1fbe09fa..32792e69fe3e3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -1281,7 +1281,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu, struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings; OverDriveTable_t *od_table = (OverDriveTable_t *)table_context->overdrive_table; - int i, size = 0, ret = 0; + int i, size = 0, ret = 0, start_offset = 0; uint32_t cur_value = 0, value = 0, count = 0; uint32_t freq_values[3] = {0}; uint32_t mark_index = 0; @@ -1289,6 +1289,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu, uint32_t min_value, max_value; smu_cmn_get_sysfs_buf(&buf, &size); + start_offset = size; switch (clk_type) { case SMU_GFXCLK: @@ -1434,7 +1435,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu, } print_clk_out: - return size; + return size - start_offset; } static int sienna_cichlid_force_clk_levels(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index a35e61f1d3f0f..09b68c1fa1998 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -569,7 +569,7 @@ static int vangogh_print_legacy_clk_levels(struct smu_context *smu, DpmClocks_t *clk_table = smu->smu_table.clocks_table; SmuMetrics_legacy_t metrics; struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); - int i, idx, size = 0, ret = 0; + int i, idx, size = 0, ret = 0, start_offset = 0; uint32_t cur_value = 0, value = 0, count = 0; bool cur_value_match_level = false; @@ -580,6 +580,7 @@ static int vangogh_print_legacy_clk_levels(struct smu_context *smu, return ret; smu_cmn_get_sysfs_buf(&buf, &size); + start_offset = size; switch (clk_type) { case SMU_OD_SCLK: @@ -662,7 +663,7 @@ static int vangogh_print_legacy_clk_levels(struct smu_context *smu, break; } - return size; + return size - start_offset; } static int vangogh_print_clk_levels(struct smu_context *smu, @@ -670,7 +671,7 @@ static int vangogh_print_clk_levels(struct smu_context *smu, { DpmClocks_t *clk_table = smu->smu_table.clocks_table; SmuMetrics_t metrics; - int i, idx, size = 0, ret = 0; + int i, idx, size = 0, ret = 0, start_offset = 0; uint32_t cur_value = 0, value = 0, count = 0; bool cur_value_match_level = false; uint32_t min, max; @@ -682,6 +683,7 @@ static int vangogh_print_clk_levels(struct smu_context *smu, return ret; smu_cmn_get_sysfs_buf(&buf, &size); + start_offset = size; switch (clk_type) { case SMU_OD_SCLK: @@ -783,7 +785,7 @@ static int vangogh_print_clk_levels(struct smu_context *smu, break; } - return size; + return size - start_offset; } static int vangogh_common_print_clk_levels(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c index 3baf20f4c3736..eaa9ea162f169 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c @@ -494,7 +494,7 @@ static int renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) static int renoir_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) { - int i, idx, size = 0, ret = 0; + int i, idx, size = 0, ret = 0, start_offset = 0; uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; SmuMetrics_t metrics; bool cur_value_match_level = false; @@ -506,6 +506,7 @@ static int renoir_print_clk_levels(struct smu_context *smu, return ret; smu_cmn_get_sysfs_buf(&buf, &size); + start_offset = size; switch (clk_type) { case SMU_OD_RANGE: @@ -550,7 +551,7 @@ static int renoir_print_clk_levels(struct smu_context *smu, size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max, i == 2 ? "*" : ""); } - return size; + return size - start_offset; case SMU_SOCCLK: count = NUM_SOCCLK_DPM_LEVELS; cur_value = metrics.ClockFrequency[CLOCK_SOCCLK]; @@ -607,7 +608,7 @@ static int renoir_print_clk_levels(struct smu_context *smu, break; } - return size; + return size - start_offset; } static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index 3cea7dc733f4b..d8871a0f05420 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -1195,15 +1195,16 @@ static int smu_v13_0_0_print_clk_levels(struct smu_context *smu, struct smu_13_0_dpm_table *single_dpm_table; struct smu_13_0_pcie_table *pcie_table; uint32_t gen_speed, lane_width; - int i, curr_freq, size = 0; + int i, curr_freq, size = 0, start_offset = 0; int32_t min_value, max_value; int ret = 0; smu_cmn_get_sysfs_buf(&buf, &size); + start_offset = size; if (amdgpu_ras_intr_triggered()) { size += sysfs_emit_at(buf, size, "unavailable\n"); - return size; + return size - start_offset; } switch (clk_type) { @@ -1534,7 +1535,7 @@ static int smu_v13_0_0_print_clk_levels(struct smu_context *smu, break; } - return size; + return size - start_offset; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c index b081ae3e8f43c..6908f9930f169 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c @@ -497,11 +497,12 @@ static int smu_v13_0_4_get_dpm_level_count(struct smu_context *smu, static int smu_v13_0_4_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) { - int i, idx, size = 0, ret = 0; + int i, idx, size = 0, ret = 0, start_offset = 0; uint32_t cur_value = 0, value = 0, count = 0; uint32_t min, max; smu_cmn_get_sysfs_buf(&buf, &size); + start_offset = size; switch (clk_type) { case SMU_OD_SCLK: @@ -565,7 +566,7 @@ static int smu_v13_0_4_print_clk_levels(struct smu_context *smu, break; } - return size; + return size - start_offset; } static int smu_v13_0_4_read_sensor(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c index f5db181ef489a..4576bf008b22d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c @@ -861,11 +861,12 @@ static int smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu, static int smu_v13_0_5_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) { - int i, idx, size = 0, ret = 0; + int i, idx, size = 0, ret = 0, start_offset = 0; uint32_t cur_value = 0, value = 0, count = 0; uint32_t min = 0, max = 0; smu_cmn_get_sysfs_buf(&buf, &size); + start_offset = size; switch (clk_type) { case SMU_OD_SCLK: @@ -928,7 +929,7 @@ static int smu_v13_0_5_print_clk_levels(struct smu_context *smu, } print_clk_out: - return size; + return size - start_offset; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 7dbd8b099fbb4..91d7da1d7cba9 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -1587,7 +1587,7 @@ static int smu_v13_0_6_print_clks(struct smu_context *smu, char *buf, int size, static int smu_v13_0_6_print_clk_levels(struct smu_context *smu, enum smu_clk_type type, char *buf) { - int now, size = 0; + int now, size = 0, start_offset = 0; int ret = 0; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; struct smu_13_0_dpm_table *single_dpm_table; @@ -1596,10 +1596,11 @@ static int smu_v13_0_6_print_clk_levels(struct smu_context *smu, uint32_t min_clk, max_clk; smu_cmn_get_sysfs_buf(&buf, &size); + start_offset = size; if (amdgpu_ras_intr_triggered()) { size += sysfs_emit_at(buf, size, "unavailable\n"); - return size; + return size - start_offset; } dpm_context = smu_dpm->dpm_context; @@ -1734,7 +1735,7 @@ static int smu_v13_0_6_print_clk_levels(struct smu_context *smu, break; } - return size; + return size - start_offset; } static int smu_v13_0_6_upload_dpm_level(struct smu_context *smu, bool max, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index c96fa5e49ed65..a3fc35b9011e4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -1184,15 +1184,16 @@ static int smu_v13_0_7_print_clk_levels(struct smu_context *smu, struct smu_13_0_dpm_table *single_dpm_table; struct smu_13_0_pcie_table *pcie_table; uint32_t gen_speed, lane_width; - int i, curr_freq, size = 0; + int i, curr_freq, size = 0, start_offset = 0; int32_t min_value, max_value; int ret = 0; smu_cmn_get_sysfs_buf(&buf, &size); + start_offset = size; if (amdgpu_ras_intr_triggered()) { size += sysfs_emit_at(buf, size, "unavailable\n"); - return size; + return size - start_offset; } switch (clk_type) { @@ -1523,7 +1524,7 @@ static int smu_v13_0_7_print_clk_levels(struct smu_context *smu, break; } - return size; + return size - start_offset; } static int smu_v13_0_7_od_restore_table_single(struct smu_context *smu, long input) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c index 73b4506ef5a87..5d7e671fa3c3a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c @@ -1041,12 +1041,13 @@ static uint32_t yellow_carp_get_umd_pstate_clk_default(struct smu_context *smu, static int yellow_carp_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) { - int i, idx, size = 0, ret = 0; + int i, idx, size = 0, ret = 0, start_offset = 0; uint32_t cur_value = 0, value = 0, count = 0; uint32_t min, max; uint32_t clk_limit = 0; smu_cmn_get_sysfs_buf(&buf, &size); + start_offset = size; switch (clk_type) { case SMU_OD_SCLK: @@ -1111,7 +1112,7 @@ static int yellow_carp_print_clk_levels(struct smu_context *smu, } print_clk_out: - return size; + return size - start_offset; } static int yellow_carp_force_clk_levels(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c index fe00c84b1cc66..b1bd946d8e309 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c @@ -1132,11 +1132,12 @@ static int smu_v14_0_common_get_dpm_level_count(struct smu_context *smu, static int smu_v14_0_0_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) { - int i, idx, ret = 0, size = 0; + int i, idx, ret = 0, size = 0, start_offset = 0; uint32_t cur_value = 0, value = 0, count = 0; uint32_t min, max; smu_cmn_get_sysfs_buf(&buf, &size); + start_offset = size; switch (clk_type) { case SMU_OD_SCLK: @@ -1202,7 +1203,7 @@ static int smu_v14_0_0_print_clk_levels(struct smu_context *smu, break; } - return size; + return size - start_offset; } static int smu_v14_0_0_set_soft_freq_limited_range(struct smu_context *smu, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index 086501cc5213b..2cea688c604f2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -1056,15 +1056,16 @@ static int smu_v14_0_2_print_clk_levels(struct smu_context *smu, struct smu_14_0_dpm_table *single_dpm_table; struct smu_14_0_pcie_table *pcie_table; uint32_t gen_speed, lane_width; - int i, curr_freq, size = 0; + int i, curr_freq, size = 0, start_offset = 0; int32_t min_value, max_value; int ret = 0; smu_cmn_get_sysfs_buf(&buf, &size); + start_offset = size; if (amdgpu_ras_intr_triggered()) { size += sysfs_emit_at(buf, size, "unavailable\n"); - return size; + return size - start_offset; } switch (clk_type) { @@ -1374,7 +1375,7 @@ static int smu_v14_0_2_print_clk_levels(struct smu_context *smu, break; } - return size; + return size - start_offset; } static int smu_v14_0_2_force_clk_levels(struct smu_context *smu, From 9e92e33d94b4bf64aaf983c149fe0b6b7e0dceb9 Mon Sep 17 00:00:00 2001 From: Alysa Liu Date: Fri, 10 Oct 2025 17:18:09 -0400 Subject: [PATCH 2269/2653] drm/amdgpu: Fix vram_usage underflow vram_usage was subtracting non-vram memory size, which caused it to become negative. Signed-off-by: Alysa Liu Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 9096ad37613dc..34940ba10e2aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2080,9 +2080,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( */ if (size) { if (!is_imported && - (mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM || - (adev->apu_prefer_gtt && - mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_GTT))) + mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) *size = bo_size; else *size = 0; From 1e04ca01af74b972eaf471f65c90053cfeff43fe Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Fri, 28 Mar 2025 12:10:33 -0400 Subject: [PATCH 2270/2653] drm/amdkcl: Add Peerdirect checks for KFD Certain kernels may have integrated peer_mem into their base Linux module, while others may have it as a separate module. Create a stub function to ensure that we don't fault out if we have the support in a separate module. Also link against the ofa_kernel as a last resort in case that's the only option available. Some older NICs can't support dma_buf, so this is required in order to get PeerDirect to work on NICs that don't support dma_buf Signed-off-by: Kent Russell Reviewed-by: Perry Yuan --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_peerdirect.c | 44 +++++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 11 +++++- drivers/gpu/drm/amd/dkms/Kbuild | 13 +++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 | 31 +++++++++++++++ 8 files changed, 104 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_peerdirect.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 54408a4967250..def3b0820b89e 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -17,7 +17,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o kcl_drm_drv.o \ - kcl_dma_fence_array.o kcl_dma_fence_unwrap.o kcl_drm_probe_helper.o kcl_i2c_core_base.o + kcl_dma_fence_array.o kcl_dma_fence_unwrap.o kcl_drm_probe_helper.o kcl_i2c_core_base.o \ + kcl_peerdirect.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o kcl_debugfs_file.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_peerdirect.c b/drivers/gpu/drm/amd/amdkcl/kcl_peerdirect.c new file mode 100644 index 0000000000000..ba404d8ec2ce4 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_peerdirect.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include + +/* If there is no peerdirect support, set up KCL function stubs to avoid any compilation failures */ +#ifndef HAVE_KFD_PEERDIRECT_SUPPORT + +void* (*_kcl_ib_register_peer_memory_client)(struct peer_memory_client + *peer_client, + invalidate_peer_memory + *invalidate_callback); +EXPORT_SYMBOL(_kcl_ib_register_peer_memory_client); + +void (*_kcl_ib_unregister_peer_memory_client)(void *reg_handle); +EXPORT_SYMBOL(_kcl_ib_unregister_peer_memory_client); +#endif + +void amdkcl_peerdirect_init(void) +{ +#ifndef HAVE_KFD_PEERDIRECT_SUPPORT + _kcl_ib_register_peer_memory_client = amdkcl_fp_setup("ib_register_peer_memory_client", NULL); + _kcl_ib_unregister_peer_memory_client = amdkcl_fp_setup("ib_unregister_peer_memory_client", NULL); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index d7956a35cae96..f5c09e0bf5d08 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -10,6 +10,7 @@ extern void amdkcl_numa_init(void); extern void amdkcl_workqueue_init(void); extern void amdkcl_prime_init(void); extern void amdkcl_security_init(void); +extern void amdkcl_peerdirect_init(void); int __init amdkcl_init(void) { @@ -21,6 +22,7 @@ int __init amdkcl_init(void) amdkcl_workqueue_init(); amdkcl_prime_init(); amdkcl_security_init(); + amdkcl_peerdirect_init(); return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index f7cd9661d5047..a77eeea39fc16 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -465,6 +465,10 @@ void kfd_init_peer_direct(void) pr_debug("Try to initialize PeerDirect support\n"); +#if defined(HAVE_KFD_PEERDIRECT_SUPPORT) + pfn_ib_register_peer_memory_client = ib_register_peer_memory_client; + pfn_ib_unregister_peer_memory_client = ib_unregister_peer_memory_client; +#else pfn_ib_register_peer_memory_client = (void *(*)(struct peer_memory_client *, invalidate_peer_memory *)) @@ -473,6 +477,7 @@ void kfd_init_peer_direct(void) pfn_ib_unregister_peer_memory_client = (void (*)(void *)) symbol_request(ib_unregister_peer_memory_client); +#endif if (!pfn_ib_register_peer_memory_client || !pfn_ib_unregister_peer_memory_client) { pr_debug("PeerDirect interface was not detected\n"); @@ -505,13 +510,15 @@ void kfd_close_peer_direct(void) if (pfn_ib_unregister_peer_memory_client) { if (ib_reg_handle) pfn_ib_unregister_peer_memory_client(ib_reg_handle); - +#if !defined(HAVE_KFD_PEERDIRECT_SUPPORT) symbol_put(ib_unregister_peer_memory_client); +#endif } +#if !defined(HAVE_KFD_PEERDIRECT_SUPPORT) if (pfn_ib_register_peer_memory_client) symbol_put(ib_register_peer_memory_client); - +#endif /* Reset pointers to be safe */ pfn_ib_unregister_peer_memory_client = NULL; diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index 02fb141c1d995..b2484432c11b6 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -32,6 +32,16 @@ LINUX_SRCTREE_INCLUDE := \ $(filter-out -I%/uapi "-include %/kconfig.h",$(_KCL_LINUXINCLUDE)) USER_INCLUDE := $(filter-out $(LINUX_SRCTREE_INCLUDE), $(_KCL_LINUXINCLUDE)) +# In the peerdirect m4, we determine if the p2p symbols are in the ofa_kernel's Module.symvers +# If so, we need to include the path for the function pointers, as well as the include path for +# rdma/peer_mem.h, since the ofa_kernel isn't integrated into the base kernel in that configuration +OFA_INCLUDE="" +_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") +ifeq ($(call _is_kcl_macro_defined,HAVE_KFD_PEERDIRECT_SUPPORT_NEED_OFAPATH),y) +KBUILD_EXTRA_SYMBOLS += /usr/src/ofa_kernel/x86_64/$(KERNELRELEASE)/Module.symvers +OFA_INCLUDE := -I/usr/src/ofa_kernel/x86_64/$(KERNELRELEASE)/include +endif + LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/kcl/header \ @@ -40,7 +50,8 @@ LINUXINCLUDE := \ -include $(src)/amd/dkms/config/config.h \ $(LINUX_SRCTREE_INCLUDE) \ -I$(src)/include/uapi \ - $(USER_INCLUDE) + $(USER_INCLUDE) \ + $(OFA_INCLUDE) export CONFIG_DRM_TTM=m export CONFIG_DRM_AMDGPU=m diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ebdae68c26743..a051966eb7093 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -862,6 +862,9 @@ /* kernel_write() take arg type of position as pointer */ #define HAVE_KERNEL_WRITE_PPOS 1 +/* HAVE_KFD_PEERDIRECT_SUPPORT is available */ +/* #undef HAVE_KFD_PEERDIRECT_SUPPORT */ + /* kfifo_out_linear() available */ #define HAVE_KFIFO_OUT_LINEAR 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7d8b00ac6905f..3c1e8baa846d2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -301,6 +301,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VFS_IOCB_ITER_READ AC_AMDGPU_LIST_IS_HEAD AC_AMDGPU_DEVM_I2C_ADD_ADAPTER + AC_AMDGPU_KFD_PEERDIRECT_SUPPORT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 b/drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 new file mode 100644 index 0000000000000..6447b6c16afac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 @@ -0,0 +1,31 @@ +dnl # +dnl # +dnl # PEER DIRECT support +dnl # +dnl # Note that some kernels will have rdma/peer_mem.h and general P2P +dnl # support included. We should check for that case first. If so, we +dnl # set p2p support to 1. +dnl # If the system uses the ofa_kernel, which is present outside of the +dnl # base kernel, then check if it exists and has a p2p symbol present. +dnl # If so, we set p2p support to 1, but also require setting the path +dnl # to the ofa_kernel, which is checked in Kbuild. +dnl # This way we can support configs that have p2p integrated into the +dnl # base kernel, or configs using the ofa_kernel +AC_DEFUN([AC_AMDGPU_KFD_PEERDIRECT_SUPPORT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct peer_memory_client client; + ib_register_peer_memory_client(&client, NULL); + ], [ + AC_DEFINE(HAVE_KFD_PEERDIRECT_SUPPORT, 1, [HAVE_KFD_PEERDIRECT_SUPPORT is available]) + ], [ + AS_IF([ grep -qw ib_register_peer_memory_client /usr/src/ofa_kernel/x86_64/${KERNELVER}/Module.symvers ], [ + AC_DEFINE(HAVE_KFD_PEERDIRECT_SUPPORT, 1, [HAVE_KFD_PEERDIRECT_SUPPORT is available]) + AC_DEFINE(HAVE_KFD_PEERDIRECT_SUPPORT_NEED_OFAPATH, 1, [HAVE_KFD_PEERDIRECT_SUPPORT is available and needs OFA path]) + ]) + ]) + ]) +]) + From 1bcd16e7982fcfea5c39e8cbbc72404119b0e8c6 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Fri, 17 Oct 2025 14:25:47 +0800 Subject: [PATCH 2271/2653] Revert "drm/amdkcl: Add Peerdirect checks for KFD" This reverts commit 1e04ca01af74b972eaf471f65c90053cfeff43fe. --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_peerdirect.c | 44 --------------------- drivers/gpu/drm/amd/amdkcl/main.c | 2 - drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 11 +----- drivers/gpu/drm/amd/dkms/Kbuild | 13 +----- drivers/gpu/drm/amd/dkms/config/config.h | 3 -- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 | 31 --------------- 8 files changed, 4 insertions(+), 104 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_peerdirect.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index def3b0820b89e..54408a4967250 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -17,8 +17,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o kcl_drm_drv.o \ - kcl_dma_fence_array.o kcl_dma_fence_unwrap.o kcl_drm_probe_helper.o kcl_i2c_core_base.o \ - kcl_peerdirect.o + kcl_dma_fence_array.o kcl_dma_fence_unwrap.o kcl_drm_probe_helper.o kcl_i2c_core_base.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o kcl_debugfs_file.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_peerdirect.c b/drivers/gpu/drm/amd/amdkcl/kcl_peerdirect.c deleted file mode 100644 index ba404d8ec2ce4..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_peerdirect.c +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright 2025 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include - -/* If there is no peerdirect support, set up KCL function stubs to avoid any compilation failures */ -#ifndef HAVE_KFD_PEERDIRECT_SUPPORT - -void* (*_kcl_ib_register_peer_memory_client)(struct peer_memory_client - *peer_client, - invalidate_peer_memory - *invalidate_callback); -EXPORT_SYMBOL(_kcl_ib_register_peer_memory_client); - -void (*_kcl_ib_unregister_peer_memory_client)(void *reg_handle); -EXPORT_SYMBOL(_kcl_ib_unregister_peer_memory_client); -#endif - -void amdkcl_peerdirect_init(void) -{ -#ifndef HAVE_KFD_PEERDIRECT_SUPPORT - _kcl_ib_register_peer_memory_client = amdkcl_fp_setup("ib_register_peer_memory_client", NULL); - _kcl_ib_unregister_peer_memory_client = amdkcl_fp_setup("ib_unregister_peer_memory_client", NULL); -#endif -} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index f5c09e0bf5d08..d7956a35cae96 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -10,7 +10,6 @@ extern void amdkcl_numa_init(void); extern void amdkcl_workqueue_init(void); extern void amdkcl_prime_init(void); extern void amdkcl_security_init(void); -extern void amdkcl_peerdirect_init(void); int __init amdkcl_init(void) { @@ -22,7 +21,6 @@ int __init amdkcl_init(void) amdkcl_workqueue_init(); amdkcl_prime_init(); amdkcl_security_init(); - amdkcl_peerdirect_init(); return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index a77eeea39fc16..f7cd9661d5047 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -465,10 +465,6 @@ void kfd_init_peer_direct(void) pr_debug("Try to initialize PeerDirect support\n"); -#if defined(HAVE_KFD_PEERDIRECT_SUPPORT) - pfn_ib_register_peer_memory_client = ib_register_peer_memory_client; - pfn_ib_unregister_peer_memory_client = ib_unregister_peer_memory_client; -#else pfn_ib_register_peer_memory_client = (void *(*)(struct peer_memory_client *, invalidate_peer_memory *)) @@ -477,7 +473,6 @@ void kfd_init_peer_direct(void) pfn_ib_unregister_peer_memory_client = (void (*)(void *)) symbol_request(ib_unregister_peer_memory_client); -#endif if (!pfn_ib_register_peer_memory_client || !pfn_ib_unregister_peer_memory_client) { pr_debug("PeerDirect interface was not detected\n"); @@ -510,15 +505,13 @@ void kfd_close_peer_direct(void) if (pfn_ib_unregister_peer_memory_client) { if (ib_reg_handle) pfn_ib_unregister_peer_memory_client(ib_reg_handle); -#if !defined(HAVE_KFD_PEERDIRECT_SUPPORT) + symbol_put(ib_unregister_peer_memory_client); -#endif } -#if !defined(HAVE_KFD_PEERDIRECT_SUPPORT) if (pfn_ib_register_peer_memory_client) symbol_put(ib_register_peer_memory_client); -#endif + /* Reset pointers to be safe */ pfn_ib_unregister_peer_memory_client = NULL; diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index b2484432c11b6..02fb141c1d995 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -32,16 +32,6 @@ LINUX_SRCTREE_INCLUDE := \ $(filter-out -I%/uapi "-include %/kconfig.h",$(_KCL_LINUXINCLUDE)) USER_INCLUDE := $(filter-out $(LINUX_SRCTREE_INCLUDE), $(_KCL_LINUXINCLUDE)) -# In the peerdirect m4, we determine if the p2p symbols are in the ofa_kernel's Module.symvers -# If so, we need to include the path for the function pointers, as well as the include path for -# rdma/peer_mem.h, since the ofa_kernel isn't integrated into the base kernel in that configuration -OFA_INCLUDE="" -_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") -ifeq ($(call _is_kcl_macro_defined,HAVE_KFD_PEERDIRECT_SUPPORT_NEED_OFAPATH),y) -KBUILD_EXTRA_SYMBOLS += /usr/src/ofa_kernel/x86_64/$(KERNELRELEASE)/Module.symvers -OFA_INCLUDE := -I/usr/src/ofa_kernel/x86_64/$(KERNELRELEASE)/include -endif - LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/kcl/header \ @@ -50,8 +40,7 @@ LINUXINCLUDE := \ -include $(src)/amd/dkms/config/config.h \ $(LINUX_SRCTREE_INCLUDE) \ -I$(src)/include/uapi \ - $(USER_INCLUDE) \ - $(OFA_INCLUDE) + $(USER_INCLUDE) export CONFIG_DRM_TTM=m export CONFIG_DRM_AMDGPU=m diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a051966eb7093..ebdae68c26743 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -862,9 +862,6 @@ /* kernel_write() take arg type of position as pointer */ #define HAVE_KERNEL_WRITE_PPOS 1 -/* HAVE_KFD_PEERDIRECT_SUPPORT is available */ -/* #undef HAVE_KFD_PEERDIRECT_SUPPORT */ - /* kfifo_out_linear() available */ #define HAVE_KFIFO_OUT_LINEAR 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3c1e8baa846d2..7d8b00ac6905f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -301,7 +301,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VFS_IOCB_ITER_READ AC_AMDGPU_LIST_IS_HEAD AC_AMDGPU_DEVM_I2C_ADD_ADAPTER - AC_AMDGPU_KFD_PEERDIRECT_SUPPORT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 b/drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 deleted file mode 100644 index 6447b6c16afac..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 +++ /dev/null @@ -1,31 +0,0 @@ -dnl # -dnl # -dnl # PEER DIRECT support -dnl # -dnl # Note that some kernels will have rdma/peer_mem.h and general P2P -dnl # support included. We should check for that case first. If so, we -dnl # set p2p support to 1. -dnl # If the system uses the ofa_kernel, which is present outside of the -dnl # base kernel, then check if it exists and has a p2p symbol present. -dnl # If so, we set p2p support to 1, but also require setting the path -dnl # to the ofa_kernel, which is checked in Kbuild. -dnl # This way we can support configs that have p2p integrated into the -dnl # base kernel, or configs using the ofa_kernel -AC_DEFUN([AC_AMDGPU_KFD_PEERDIRECT_SUPPORT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct peer_memory_client client; - ib_register_peer_memory_client(&client, NULL); - ], [ - AC_DEFINE(HAVE_KFD_PEERDIRECT_SUPPORT, 1, [HAVE_KFD_PEERDIRECT_SUPPORT is available]) - ], [ - AS_IF([ grep -qw ib_register_peer_memory_client /usr/src/ofa_kernel/x86_64/${KERNELVER}/Module.symvers ], [ - AC_DEFINE(HAVE_KFD_PEERDIRECT_SUPPORT, 1, [HAVE_KFD_PEERDIRECT_SUPPORT is available]) - AC_DEFINE(HAVE_KFD_PEERDIRECT_SUPPORT_NEED_OFAPATH, 1, [HAVE_KFD_PEERDIRECT_SUPPORT is available and needs OFA path]) - ]) - ]) - ]) -]) - From 7b1678d465404d4708feff1ef49f653c21b812d9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 17 Oct 2025 11:31:47 +0800 Subject: [PATCH 2272/2653] Revert "drm/amdkcl: modify autoconf to check drm_client_setup symbol" This reverts commit bb6320f70d1f0fbbf72f9cf70517d67b7584e169. Ubuntu HWE kernel 6.11.28 without fb dev has been drop, so reverting this work around avoid to block fbk 6.16.1 support. Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/drm-client.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 index 8dcc7e1ef03ee..2c58adc325572 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 @@ -4,7 +4,7 @@ dnl # drm: Add client-agnostic setup helper dnl # AC_DEFUN([AC_AMDGPU_DRM_CLIENT_SETUP], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ + AC_KERNEL_TRY_COMPILE([ #ifdef HAVE_DRM_DRM_CLIENT_SETUP_H #include #endif @@ -13,7 +13,7 @@ AC_DEFUN([AC_AMDGPU_DRM_CLIENT_SETUP], [ #endif ], [ drm_client_setup(NULL, NULL); - ], [drm_client_setup],[drivers/gpu/drm/clients/drm_client_setup.c],[ + ], [ AC_DEFINE(HAVE_DRM_CLIENT_SETUP, 1, [drm_client_setup() is available]) ]) From a6d5e5485a391ba12455ea7fa22effb0c06e93be Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Tue, 14 Oct 2025 14:30:35 -0500 Subject: [PATCH 2273/2653] drm/amd: Add a helper to tell whether an IP block HW is enabled There is already a helper for telling if a block is valid, but if IP handling wants to check if it's HW is enabled no such helper exists. Reviewed-by: Harry Wentland Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 23 +++++++++++++++++++++- 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index ad578ea8116d9..ff333213c4942 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -374,6 +374,8 @@ void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, u64 *flags); int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, enum amd_ip_block_type block_type); +bool amdgpu_device_ip_is_hw(struct amdgpu_device *adev, + enum amd_ip_block_type block_type); bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, enum amd_ip_block_type block_type); int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 0accf31aa80cd..d6e1ec1d4888d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2412,7 +2412,7 @@ int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, } /** - * amdgpu_device_ip_is_valid - is the hardware IP enabled + * amdgpu_device_ip_is_hw - is the hardware IP enabled * * @adev: amdgpu_device pointer * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) @@ -2420,6 +2420,27 @@ int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, * Check if the hardware IP is enable or not. * Returns true if it the IP is enable, false if not. */ +bool amdgpu_device_ip_is_hw(struct amdgpu_device *adev, + enum amd_ip_block_type block_type) +{ + int i; + + for (i = 0; i < adev->num_ip_blocks; i++) { + if (adev->ip_blocks[i].version->type == block_type) + return adev->ip_blocks[i].status.hw; + } + return false; +} + +/** + * amdgpu_device_ip_is_valid - is the hardware IP valid + * + * @adev: amdgpu_device pointer + * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) + * + * Check if the hardware IP is valid or not. + * Returns true if it the IP is valid, false if not. + */ bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, enum amd_ip_block_type block_type) { From 4b92929ba05862901a21bff1c0dea0d726517a51 Mon Sep 17 00:00:00 2001 From: Victor Zhao Date: Thu, 9 Oct 2025 10:38:28 +0800 Subject: [PATCH 2274/2653] drm/amdgpu: Add kiq hdp flush callbacks Add kiq hdp flush callbacks for gfx ips to support gpu hdp flush when no ring presents Reviewed-by: Lijo Lazar Signed-off-by: Victor Zhao --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 + 6 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 279be67679994..7e2d47ff7f630 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -10083,6 +10083,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { .emit_wreg = gfx_v10_0_ring_emit_wreg, .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, + .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, }; static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 4adaba2d85de7..42d914c896232 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -2438,7 +2438,7 @@ static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) if (version_minor == 3) gfx_v11_0_load_rlcp_rlcv_microcode(adev); } - + return 0; } @@ -3886,7 +3886,7 @@ static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) } memcpy(fw, fw_data, fw_size); - + amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); @@ -7329,6 +7329,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { .emit_wreg = gfx_v11_0_ring_emit_wreg, .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, + .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush, }; static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 25a20cab71a2f..445a569896035 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -5606,6 +5606,7 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { .emit_wreg = gfx_v12_0_ring_emit_wreg, .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, + .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush, }; static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 7f740daf7415e..12a740f954d0f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -7067,6 +7067,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = { .pad_ib = amdgpu_ring_generic_pad_ib, .emit_rreg = gfx_v8_0_ring_emit_rreg, .emit_wreg = gfx_v8_0_ring_emit_wreg, + .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, }; static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 63ccded25aa46..81cd7bdba23f4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -7715,6 +7715,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { .emit_wreg = gfx_v9_0_ring_emit_wreg, .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, + .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, }; static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 72cdaacead31e..94273c4f574da 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -4956,6 +4956,7 @@ static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { .emit_wreg = gfx_v9_4_3_ring_emit_wreg, .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, + .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, }; static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) From b3cf6d09acd1fc2948e2b7522215b5ed602d39ec Mon Sep 17 00:00:00 2001 From: Victor Zhao Date: Thu, 9 Oct 2025 10:42:48 +0800 Subject: [PATCH 2275/2653] drm/amdgpu: use GPU_HDP_FLUSH for sriov Currently SRIOV runtime will use kiq to write HDP_MEM_FLUSH_CNTL for hdp flush. This register need to be write from CPU for nbif to aware, otherwise it will not work. Implement amdgpu_kiq_hdp_flush and use kiq to do gpu hdp flush during sriov runtime. v2: - fallback to amdgpu_asic_flush_hdp when amdgpu_kiq_hdp_flush failed - add function amdgpu_mes_hdp_flush v3: - changed returned error Reviewed-by: Lijo Lazar Signed-off-by: Victor Zhao --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 13 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 71 ++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 12 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 1 + 5 files changed, 95 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index d6e1ec1d4888d..2088069a1fa9b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -7378,10 +7378,17 @@ void amdgpu_device_flush_hdp(struct amdgpu_device *adev, if (adev->gmc.xgmi.connected_to_cpu) return; - if (ring && ring->funcs->emit_hdp_flush) + if (ring && ring->funcs->emit_hdp_flush) { amdgpu_ring_emit_hdp_flush(ring); - else - amdgpu_asic_flush_hdp(adev, ring); + return; + } + + if (!ring && amdgpu_sriov_runtime(adev)) { + if (!amdgpu_kiq_hdp_flush(adev)) + return; + } + + amdgpu_asic_flush_hdp(adev, ring); } void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 7f02e36ccc1ea..3d24f9cd750a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -33,6 +33,7 @@ #include "amdgpu_reset.h" #include "amdgpu_xcp.h" #include "amdgpu_xgmi.h" +#include "amdgpu_mes.h" #include "nvd.h" /* delay 0.1 second to enable gfx off feature */ @@ -1194,6 +1195,75 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint3 dev_err(adev->dev, "failed to write reg:%x\n", reg); } +int amdgpu_kiq_hdp_flush(struct amdgpu_device *adev) +{ + signed long r, cnt = 0; + unsigned long flags; + uint32_t seq; + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; + struct amdgpu_ring *ring = &kiq->ring; + + if (amdgpu_device_skip_hw_access(adev)) + return 0; + + if (adev->enable_mes_kiq && adev->mes.ring[0].sched.ready) + return amdgpu_mes_hdp_flush(adev); + + if (!ring->funcs->emit_hdp_flush) { + return -EOPNOTSUPP; + } + + spin_lock_irqsave(&kiq->ring_lock, flags); + r = amdgpu_ring_alloc(ring, 32); + if (r) + goto failed_unlock; + + amdgpu_ring_emit_hdp_flush(ring); + r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); + if (r) + goto failed_undo; + + amdgpu_ring_commit(ring); + spin_unlock_irqrestore(&kiq->ring_lock, flags); + + r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); + + /* don't wait anymore for gpu reset case because this way may + * block gpu_recover() routine forever, e.g. this virt_kiq_rreg + * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will + * never return if we keep waiting in virt_kiq_rreg, which cause + * gpu_recover() hang there. + * + * also don't wait anymore for IRQ context + * */ + if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt())) + goto failed_kiq_hdp_flush; + + might_sleep(); + while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { + if (amdgpu_in_reset(adev)) + goto failed_kiq_hdp_flush; + + msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); + r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); + } + + if (cnt > MAX_KIQ_REG_TRY) { + dev_err(adev->dev, "failed to flush HDP via KIQ timeout\n"); + return -ETIMEDOUT; + } + + return 0; + +failed_undo: + amdgpu_ring_undo(ring); +failed_unlock: + spin_unlock_irqrestore(&kiq->ring_lock, flags); +failed_kiq_hdp_flush: + dev_err(adev->dev, "failed to flush HDP via KIQ\n"); + return r < 0 ? r : -EIO; +} + int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev) { if (amdgpu_num_kcq == -1) { @@ -2484,3 +2554,4 @@ void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev) &amdgpu_debugfs_compute_sched_mask_fops); #endif } + diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 57e75a8078464..c1523bdee992c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -626,6 +626,7 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry); uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id); void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id); +int amdgpu_kiq_hdp_flush(struct amdgpu_device *adev); int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev); void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 45bf8309cb375..9c182ce501af4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -528,6 +528,18 @@ int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, return r; } +int amdgpu_mes_hdp_flush(struct amdgpu_device *adev) +{ + uint32_t hdp_flush_req_offset, hdp_flush_done_offset, ref_and_mask; + + hdp_flush_req_offset = adev->nbio.funcs->get_hdp_flush_req_offset(adev); + hdp_flush_done_offset = adev->nbio.funcs->get_hdp_flush_done_offset(adev); + ref_and_mask = adev->nbio.hdp_flush_reg->ref_and_mask_cp0; + + return amdgpu_mes_reg_write_reg_wait(adev, hdp_flush_req_offset, hdp_flush_done_offset, + ref_and_mask, ref_and_mask); +} + int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, uint64_t process_context_addr, uint32_t spi_gdbg_per_vmid_cntl, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index b0941ef33c9ad..6d2e9776b2e03 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -428,6 +428,7 @@ int amdgpu_mes_wreg(struct amdgpu_device *adev, int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, uint32_t reg0, uint32_t reg1, uint32_t ref, uint32_t mask); +int amdgpu_mes_hdp_flush(struct amdgpu_device *adev); int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, uint64_t process_context_addr, uint32_t spi_gdbg_per_vmid_cntl, From a69f8892eecfa270c45fb254420deaa970e9b41e Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Fri, 3 Oct 2025 16:06:53 -0400 Subject: [PATCH 2276/2653] drm/amd/display: Fix GFP_ATOMIC abuse There is a lot GFP_ATOMIC allocations which are not in interrupt context. Change them to use GFP_KERNEL instead. Reviewed-by: Leo Li Signed-off-by: Aurabindo Pillai Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- .../amd/display/dc/dccg/dcn20/dcn20_dccg.c | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 6 ++-- .../dc/resource/dcn20/dcn20_resource.c | 28 ++++++++--------- .../dc/resource/dcn201/dcn201_resource.c | 30 +++++++++---------- 6 files changed, 33 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8414e707f66a0..f8f03cfc5f475 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10910,7 +10910,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) * Here we create an empty update on each plane. * To fix this, DC should permit updating only stream properties. */ - dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC); + dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_KERNEL); if (!dummy_updates) { drm_err(adev_to_drm(adev), "Failed to allocate memory for dummy_updates.\n"); continue; diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c index 5999b2da3a018..33d8bd91cb014 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c @@ -148,7 +148,7 @@ struct dccg *dccg2_create( const struct dccg_shift *dccg_shift, const struct dccg_mask *dccg_mask) { - struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_ATOMIC); + struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL); struct dccg *base; if (dccg_dcn == NULL) { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c index a6006776333d1..2dcf394edf223 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c @@ -283,7 +283,7 @@ struct abm *dce_abm_create( const struct dce_abm_shift *abm_shift, const struct dce_abm_mask *abm_mask) { - struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_ATOMIC); + struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL); if (abm_dce == NULL) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c index a8e79104b684e..5f8fba45d98db 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c @@ -1126,7 +1126,7 @@ struct dmcu *dcn10_dmcu_create( const struct dce_dmcu_shift *dmcu_shift, const struct dce_dmcu_mask *dmcu_mask) { - struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC); + struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); if (dmcu_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -1147,7 +1147,7 @@ struct dmcu *dcn20_dmcu_create( const struct dce_dmcu_shift *dmcu_shift, const struct dce_dmcu_mask *dmcu_mask) { - struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC); + struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); if (dmcu_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -1168,7 +1168,7 @@ struct dmcu *dcn21_dmcu_create( const struct dce_dmcu_shift *dmcu_shift, const struct dce_dmcu_mask *dmcu_mask) { - struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_ATOMIC); + struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); if (dmcu_dce == NULL) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index d4e75cf6d0b21..f28e6efdc23d0 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -733,7 +733,7 @@ struct dpp *dcn20_dpp_create( uint32_t inst) { struct dcn20_dpp *dpp = - kzalloc(sizeof(struct dcn20_dpp), GFP_ATOMIC); + kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL); if (!dpp) return NULL; @@ -751,7 +751,7 @@ struct input_pixel_processor *dcn20_ipp_create( struct dc_context *ctx, uint32_t inst) { struct dcn10_ipp *ipp = - kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC); + kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -768,7 +768,7 @@ struct output_pixel_processor *dcn20_opp_create( struct dc_context *ctx, uint32_t inst) { struct dcn20_opp *opp = - kzalloc(sizeof(struct dcn20_opp), GFP_ATOMIC); + kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); if (!opp) { BREAK_TO_DEBUGGER(); @@ -785,7 +785,7 @@ struct dce_aux *dcn20_aux_engine_create( uint32_t inst) { struct aux_engine_dce110 *aux_engine = - kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC); + kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); if (!aux_engine) return NULL; @@ -823,7 +823,7 @@ struct dce_i2c_hw *dcn20_i2c_hw_create( uint32_t inst) { struct dce_i2c_hw *dce_i2c_hw = - kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC); + kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); if (!dce_i2c_hw) return NULL; @@ -835,8 +835,7 @@ struct dce_i2c_hw *dcn20_i2c_hw_create( } struct mpc *dcn20_mpc_create(struct dc_context *ctx) { - struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), - GFP_ATOMIC); + struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), GFP_KERNEL); if (!mpc20) return NULL; @@ -853,8 +852,7 @@ struct mpc *dcn20_mpc_create(struct dc_context *ctx) struct hubbub *dcn20_hubbub_create(struct dc_context *ctx) { int i; - struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), - GFP_ATOMIC); + struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); if (!hubbub) return NULL; @@ -882,7 +880,7 @@ struct timing_generator *dcn20_timing_generator_create( uint32_t instance) { struct optc *tgn10 = - kzalloc(sizeof(struct optc), GFP_ATOMIC); + kzalloc(sizeof(struct optc), GFP_KERNEL); if (!tgn10) return NULL; @@ -962,7 +960,7 @@ static struct clock_source *dcn20_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC); + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -1060,7 +1058,7 @@ struct display_stream_compressor *dcn20_dsc_create( struct dc_context *ctx, uint32_t inst) { struct dcn20_dsc *dsc = - kzalloc(sizeof(struct dcn20_dsc), GFP_ATOMIC); + kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); if (!dsc) { BREAK_TO_DEBUGGER(); @@ -1196,7 +1194,7 @@ struct hubp *dcn20_hubp_create( uint32_t inst) { struct dcn20_hubp *hubp2 = - kzalloc(sizeof(struct dcn20_hubp), GFP_ATOMIC); + kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); if (!hubp2) return NULL; @@ -2280,7 +2278,7 @@ bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx) { - struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC); + struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); if (!pp_smu) return pp_smu; @@ -2759,7 +2757,7 @@ struct resource_pool *dcn20_create_resource_pool( struct dc *dc) { struct dcn20_resource_pool *pool = - kzalloc(sizeof(struct dcn20_resource_pool), GFP_ATOMIC); + kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c index e4a1338d21e01..9a80bebcee485 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c @@ -629,7 +629,7 @@ static struct dpp *dcn201_dpp_create( uint32_t inst) { struct dcn201_dpp *dpp = - kzalloc(sizeof(struct dcn201_dpp), GFP_ATOMIC); + kzalloc(sizeof(struct dcn201_dpp), GFP_KERNEL); if (!dpp) return NULL; @@ -646,7 +646,7 @@ static struct input_pixel_processor *dcn201_ipp_create( struct dc_context *ctx, uint32_t inst) { struct dcn10_ipp *ipp = - kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC); + kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); if (!ipp) { return NULL; @@ -662,7 +662,7 @@ static struct output_pixel_processor *dcn201_opp_create( struct dc_context *ctx, uint32_t inst) { struct dcn201_opp *opp = - kzalloc(sizeof(struct dcn201_opp), GFP_ATOMIC); + kzalloc(sizeof(struct dcn201_opp), GFP_KERNEL); if (!opp) { return NULL; @@ -677,7 +677,7 @@ static struct dce_aux *dcn201_aux_engine_create(struct dc_context *ctx, uint32_t inst) { struct aux_engine_dce110 *aux_engine = - kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC); + kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); if (!aux_engine) return NULL; @@ -710,7 +710,7 @@ static struct dce_i2c_hw *dcn201_i2c_hw_create(struct dc_context *ctx, uint32_t inst) { struct dce_i2c_hw *dce_i2c_hw = - kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC); + kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); if (!dce_i2c_hw) return NULL; @@ -723,8 +723,7 @@ static struct dce_i2c_hw *dcn201_i2c_hw_create(struct dc_context *ctx, static struct mpc *dcn201_mpc_create(struct dc_context *ctx, uint32_t num_mpcc) { - struct dcn201_mpc *mpc201 = kzalloc(sizeof(struct dcn201_mpc), - GFP_ATOMIC); + struct dcn201_mpc *mpc201 = kzalloc(sizeof(struct dcn201_mpc), GFP_KERNEL); if (!mpc201) return NULL; @@ -740,8 +739,7 @@ static struct mpc *dcn201_mpc_create(struct dc_context *ctx, uint32_t num_mpcc) static struct hubbub *dcn201_hubbub_create(struct dc_context *ctx) { - struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), - GFP_ATOMIC); + struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); if (!hubbub) return NULL; @@ -759,7 +757,7 @@ static struct timing_generator *dcn201_timing_generator_create( uint32_t instance) { struct optc *tgn10 = - kzalloc(sizeof(struct optc), GFP_ATOMIC); + kzalloc(sizeof(struct optc), GFP_KERNEL); if (!tgn10) return NULL; @@ -793,7 +791,7 @@ static struct link_encoder *dcn201_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dcn20_link_encoder *enc20 = - kzalloc(sizeof(struct dcn20_link_encoder), GFP_ATOMIC); + kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); struct dcn10_link_encoder *enc10; if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) @@ -821,7 +819,7 @@ static struct clock_source *dcn201_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC); + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -856,7 +854,7 @@ static struct stream_encoder *dcn201_stream_encoder_create( struct dc_context *ctx) { struct dcn10_stream_encoder *enc1 = - kzalloc(sizeof(struct dcn10_stream_encoder), GFP_ATOMIC); + kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); if (!enc1) return NULL; @@ -883,7 +881,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dcn201_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_ATOMIC); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -983,7 +981,7 @@ static struct hubp *dcn201_hubp_create( uint32_t inst) { struct dcn201_hubp *hubp201 = - kzalloc(sizeof(struct dcn201_hubp), GFP_ATOMIC); + kzalloc(sizeof(struct dcn201_hubp), GFP_KERNEL); if (!hubp201) return NULL; @@ -1303,7 +1301,7 @@ struct resource_pool *dcn201_create_resource_pool( struct dc *dc) { struct dcn201_resource_pool *pool = - kzalloc(sizeof(struct dcn201_resource_pool), GFP_ATOMIC); + kzalloc(sizeof(struct dcn201_resource_pool), GFP_KERNEL); if (!pool) return NULL; From 693e1bca01f448a274d8831c243e3eff22d78531 Mon Sep 17 00:00:00 2001 From: Meenakshikumar Somasundaram Date: Mon, 6 Oct 2025 22:02:31 -0400 Subject: [PATCH 2277/2653] drm/amd/display: Check disable_fec flag before enabling fec. [Why] dc debug option disable_fec was not working. [How] Check dc debug option disable_fec flag before enabling fec in dp_should_enable_fec(). Reviewed-by: Wenjing Liu Signed-off-by: Meenakshikumar Somasundaram Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/link/protocols/link_dp_capability.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index e26d5f89e9d79..7c2135c240aca 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -357,7 +357,9 @@ bool dp_should_enable_fec(const struct dc_link *link) { bool force_disable = false; - if (link->fec_state == dc_link_fec_enabled) + if (link->dc->debug.disable_fec) + force_disable = true; + else if (link->fec_state == dc_link_fec_enabled) force_disable = false; else if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST && link->local_sink && From f8b9f758072f61259c6a3531ef1fb8ed34c8c02b Mon Sep 17 00:00:00 2001 From: Nicholas Carbones Date: Fri, 3 Oct 2025 18:36:18 -0400 Subject: [PATCH 2278/2653] drm/amd/display: Set DCN32 to use update planes and stream version 3 [Why] Old minimal transition does not always wait for updates to complete before proceeding, which can lead to corruption in multi display scenarios for DCN32. [How] Set DCN32 to use update_planes_and_stream_v3 for better pipe transition handling. Reviewed-by: Dillon Varone Signed-off-by: Nicholas Carbones Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 55aab3b190b88..2900bc7b0704f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -5377,7 +5377,8 @@ bool dc_update_planes_and_stream(struct dc *dc, * specially handle compatibility problems with transitions among those * features as they are now transparent to the new sequence. */ - if (dc->ctx->dce_version >= DCN_VERSION_4_01) + if (dc->ctx->dce_version >= DCN_VERSION_4_01 || dc->ctx->dce_version == DCN_VERSION_3_2 || + dc->ctx->dce_version == DCN_VERSION_3_21) ret = update_planes_and_stream_v3(dc, srf_updates, surface_count, stream, stream_update); else From 642267a9f639d130b25928bb807263e06b233684 Mon Sep 17 00:00:00 2001 From: Lewis Huang Date: Tue, 7 Oct 2025 16:46:59 +0800 Subject: [PATCH 2279/2653] drm/amd/display: Change clean dsc blocks condition in accelerated mode [Why] On system resume from S4 with the lid closed, DSC was not cleared because DPMS was already off. [How] In accelerated mode, to clean up DSC blocks if eDP dpms off is true to align the DSC and dpms state when we are not in fast boot and seamless boot. Reviewed-by: Wenjing Liu Signed-off-by: Lewis Huang Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 24184b4eb3529..6b0566baa2f27 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -1913,6 +1913,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) bool can_apply_edp_fast_boot = false; bool can_apply_seamless_boot = false; bool keep_edp_vdd_on = false; + bool should_clean_dsc_block = true; struct dc_bios *dcb = dc->ctx->dc_bios; DC_LOGGER_INIT(); @@ -2005,9 +2006,15 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) power_down_all_hw_blocks(dc); /* DSC could be enabled on eDP during VBIOS post. - * To clean up dsc blocks if eDP is in link but not active. + * To clean up dsc blocks if all eDP dpms_off is true. */ - if (edp_link_with_sink && (edp_stream_num == 0)) + for (i = 0; i < edp_stream_num; i++) { + if (!edp_streams[i]->dpms_off) { + should_clean_dsc_block = false; + } + } + + if (should_clean_dsc_block) clean_up_dsc_blocks(dc); disable_vga_and_power_gate_all_controllers(dc); From 774ecdc2ed01da349dc91d7c8b69247e135759ca Mon Sep 17 00:00:00 2001 From: Ilya Bakoulin Date: Tue, 7 Oct 2025 16:34:09 -0400 Subject: [PATCH 2280/2653] drm/amd/display: Fix misc. checkpatch issues [Why/How] Addresses various checkpatch issues related to the HWSS block sequence function change. Reviewed-by: Aurabindo Pillai Signed-off-by: Ilya Bakoulin Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 57 +++---- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 160 ++++++++---------- 2 files changed, 86 insertions(+), 131 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 16d916986fed6..f95cb0cf4b8a6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -1962,9 +1962,8 @@ void hwss_program_bias_and_scale(union block_sequence_params *params) struct dc_bias_and_scale bns_params = plane_state->bias_and_scale; //TODO :for CNVC set scale and bias registers if necessary - if (dpp->funcs->dpp_program_bias_and_scale) { + if (dpp->funcs->dpp_program_bias_and_scale) dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); - } } void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params) @@ -2121,6 +2120,7 @@ void hwss_wait_for_odm_update_pending_complete(struct dc *dc, struct dc_state *c void hwss_wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context) { int i; + for (i = 0; i < MAX_PIPES; i++) { int count = 0; struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; @@ -2277,6 +2277,7 @@ void hwss_tg_set_dsc_config(union block_sequence_params *params) if (params->tg_set_dsc_config_params.enable) { struct dsc_optc_config *dsc_optc_cfg = params->tg_set_dsc_config_params.dsc_optc_cfg; + if (dsc_optc_cfg) { bytes_per_pixel = dsc_optc_cfg->bytes_per_pixel; slice_width = dsc_optc_cfg->slice_width; @@ -2370,9 +2371,8 @@ void hwss_tg_wait_for_state(union block_sequence_params *params) struct timing_generator *tg = params->tg_wait_for_state_params.tg; enum crtc_state state = params->tg_wait_for_state_params.state; - if (tg->funcs->wait_for_state) { + if (tg->funcs->wait_for_state) tg->funcs->wait_for_state(tg, state); - } } void hwss_tg_set_vtg_params(union block_sequence_params *params) @@ -2381,9 +2381,8 @@ void hwss_tg_set_vtg_params(union block_sequence_params *params) struct dc_crtc_timing *timing = params->tg_set_vtg_params_params.timing; bool program_fp2 = params->tg_set_vtg_params_params.program_fp2; - if (tg->funcs->set_vtg_params) { + if (tg->funcs->set_vtg_params) tg->funcs->set_vtg_params(tg, timing, program_fp2); - } } void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params) @@ -2391,9 +2390,8 @@ void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params) struct timing_generator *tg = params->tg_setup_vertical_interrupt2_params.tg; int start_line = params->tg_setup_vertical_interrupt2_params.start_line; - if (tg->funcs->setup_vertical_interrupt2) { + if (tg->funcs->setup_vertical_interrupt2) tg->funcs->setup_vertical_interrupt2(tg, start_line); - } } void hwss_dpp_set_hdr_multiplier(union block_sequence_params *params) @@ -2401,9 +2399,8 @@ void hwss_dpp_set_hdr_multiplier(union block_sequence_params *params) struct dpp *dpp = params->dpp_set_hdr_multiplier_params.dpp; uint32_t hw_mult = params->dpp_set_hdr_multiplier_params.hw_mult; - if (dpp->funcs->dpp_set_hdr_multiplier) { + if (dpp->funcs->dpp_set_hdr_multiplier) dpp->funcs->dpp_set_hdr_multiplier(dpp, hw_mult); - } } void hwss_program_det_size(union block_sequence_params *params) @@ -2412,9 +2409,8 @@ void hwss_program_det_size(union block_sequence_params *params) unsigned int hubp_inst = params->program_det_size_params.hubp_inst; unsigned int det_buffer_size_kb = params->program_det_size_params.det_buffer_size_kb; - if (hubbub->funcs->program_det_size) { + if (hubbub->funcs->program_det_size) hubbub->funcs->program_det_size(hubbub, hubp_inst, det_buffer_size_kb); - } } void hwss_program_det_segments(union block_sequence_params *params) @@ -2423,9 +2419,8 @@ void hwss_program_det_segments(union block_sequence_params *params) unsigned int hubp_inst = params->program_det_segments_params.hubp_inst; unsigned int det_size = params->program_det_segments_params.det_size; - if (hubbub->funcs->program_det_segments) { + if (hubbub->funcs->program_det_segments) hubbub->funcs->program_det_segments(hubbub, hubp_inst, det_size); - } } void hwss_opp_set_dyn_expansion(union block_sequence_params *params) @@ -2435,9 +2430,8 @@ void hwss_opp_set_dyn_expansion(union block_sequence_params *params) enum dc_color_depth color_depth = params->opp_set_dyn_expansion_params.color_depth; enum signal_type signal = params->opp_set_dyn_expansion_params.signal; - if (opp->funcs->opp_set_dyn_expansion) { + if (opp->funcs->opp_set_dyn_expansion) opp->funcs->opp_set_dyn_expansion(opp, color_space, color_depth, signal); - } } void hwss_opp_program_fmt(union block_sequence_params *params) @@ -2446,9 +2440,8 @@ void hwss_opp_program_fmt(union block_sequence_params *params) struct bit_depth_reduction_params *fmt_bit_depth = params->opp_program_fmt_params.fmt_bit_depth; struct clamping_and_pixel_encoding_params *clamping = params->opp_program_fmt_params.clamping; - if (opp->funcs->opp_program_fmt) { + if (opp->funcs->opp_program_fmt) opp->funcs->opp_program_fmt(opp, fmt_bit_depth, clamping); - } } void hwss_opp_program_bit_depth_reduction(union block_sequence_params *params) @@ -2458,15 +2451,13 @@ void hwss_opp_program_bit_depth_reduction(union block_sequence_params *params) struct pipe_ctx *pipe_ctx = params->opp_program_bit_depth_reduction_params.pipe_ctx; struct bit_depth_reduction_params bit_depth_params; - if (use_default_params) { + if (use_default_params) memset(&bit_depth_params, 0, sizeof(bit_depth_params)); - } else { + else resource_build_bit_depth_reduction_params(pipe_ctx->stream, &bit_depth_params); - } - if (opp->funcs->opp_program_bit_depth_reduction) { + if (opp->funcs->opp_program_bit_depth_reduction) opp->funcs->opp_program_bit_depth_reduction(opp, &bit_depth_params); - } } void hwss_opp_set_disp_pattern_generator(union block_sequence_params *params) @@ -2500,9 +2491,8 @@ void hwss_set_abm_level(union block_sequence_params *params) struct abm *abm = params->set_abm_level_params.abm; unsigned int abm_level = params->set_abm_level_params.abm_level; - if (abm->funcs->set_abm_level) { + if (abm->funcs->set_abm_level) abm->funcs->set_abm_level(abm, abm_level); - } } void hwss_set_abm_immediate_disable(union block_sequence_params *params) @@ -2510,9 +2500,8 @@ void hwss_set_abm_immediate_disable(union block_sequence_params *params) struct dc *dc = params->set_abm_immediate_disable_params.dc; struct pipe_ctx *pipe_ctx = params->set_abm_immediate_disable_params.pipe_ctx; - if (dc && dc->hwss.set_abm_immediate_disable) { + if (dc && dc->hwss.set_abm_immediate_disable) dc->hwss.set_abm_immediate_disable(pipe_ctx); - } } void hwss_mpc_remove_mpcc(union block_sequence_params *params) @@ -2793,34 +2782,29 @@ void hwss_hubp_init(union block_sequence_params *params) { struct hubp *hubp = params->hubp_init_params.hubp; - if (hubp && hubp->funcs->hubp_init) { + if (hubp && hubp->funcs->hubp_init) hubp->funcs->hubp_init(hubp); - } } void hwss_hubp_set_vm_system_aperture_settings(union block_sequence_params *params) { struct hubp *hubp = params->hubp_set_vm_system_aperture_settings_params.hubp; - //struct vm_system_aperture_param *apt = ¶ms->hubp_set_vm_system_aperture_settings_params.apt; struct vm_system_aperture_param apt; apt.sys_default = params->hubp_set_vm_system_aperture_settings_params.sys_default; apt.sys_high = params->hubp_set_vm_system_aperture_settings_params.sys_high; apt.sys_low = params->hubp_set_vm_system_aperture_settings_params.sys_low; - if (hubp && hubp->funcs->hubp_set_vm_system_aperture_settings) { - //hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, apt); + if (hubp && hubp->funcs->hubp_set_vm_system_aperture_settings) hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt); - } } void hwss_hubp_set_flip_int(union block_sequence_params *params) { struct hubp *hubp = params->hubp_set_flip_int_params.hubp; - if (hubp && hubp->funcs->hubp_set_flip_int) { + if (hubp && hubp->funcs->hubp_set_flip_int) hubp->funcs->hubp_set_flip_int(hubp); - } } void hwss_dpp_dppclk_control(union block_sequence_params *params) @@ -3049,13 +3033,10 @@ void hwss_mpc_update_blending(union block_sequence_params *params) void hwss_mpc_assert_idle_mpcc(union block_sequence_params *params) { struct mpc *mpc = params->mpc_assert_idle_mpcc_params.mpc; - //struct pipe_ctx *pipe_ctx = params->mpc_assert_idle_mpcc_params.pipe_ctx; int mpcc_id = params->mpc_assert_idle_mpcc_params.mpcc_id; if (mpc && mpc->funcs->wait_for_idle) mpc->funcs->wait_for_idle(mpc, mpcc_id); - - //pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_id] = false; } void hwss_mpc_insert_plane(union block_sequence_params *params) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index e6d3ff8598f52..23ecab4bcbba8 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -2271,17 +2271,15 @@ void dcn401_program_pipe_sequence( (unsigned int)pipe_ctx->global_sync.dcn4x.pstate_keepout_start_lines); /* Step 2: Wait for VACTIVE state (if not phantom pipe) */ - if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) { + if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) hwss_add_tg_wait_for_state(seq_state, pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); - } /* Step 3: Set VTG params */ hwss_add_tg_set_vtg_params(seq_state, pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true); /* Step 4: Setup vupdate interrupt (if available) */ - if (hws->funcs.setup_vupdate_interrupt) { + if (hws->funcs.setup_vupdate_interrupt) dcn401_setup_vupdate_interrupt_sequence(dc, pipe_ctx, seq_state); - } } if (pipe_ctx->update_flags.bits.odm) { @@ -2347,9 +2345,11 @@ void dcn401_program_pipe_sequence( if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed) { - hwss_add_opp_set_dyn_expansion(seq_state, pipe_ctx->stream_res.opp, COLOR_SPACE_YCBCR601, pipe_ctx->stream->timing.display_color_depth, pipe_ctx->stream->signal); + hwss_add_opp_set_dyn_expansion(seq_state, pipe_ctx->stream_res.opp, COLOR_SPACE_YCBCR601, + pipe_ctx->stream->timing.display_color_depth, pipe_ctx->stream->signal); - hwss_add_opp_program_fmt(seq_state, pipe_ctx->stream_res.opp, &pipe_ctx->stream->bit_depth_params, &pipe_ctx->stream->clamping); + hwss_add_opp_program_fmt(seq_state, pipe_ctx->stream_res.opp, + &pipe_ctx->stream->bit_depth_params, &pipe_ctx->stream->clamping); } /* Set ABM pipe after other pipe configurations done */ @@ -2366,7 +2366,16 @@ void dcn401_program_pipe_sequence( hwss_add_opp_program_bit_depth_reduction(seq_state, odm_opp, true, pipe_ctx); - hwss_add_opp_set_disp_pattern_generator(seq_state, odm_opp, pipe_ctx->stream_res.test_pattern_params.test_pattern, pipe_ctx->stream_res.test_pattern_params.color_space, pipe_ctx->stream_res.test_pattern_params.color_depth, (struct tg_color){0}, false, pipe_ctx->stream_res.test_pattern_params.width, pipe_ctx->stream_res.test_pattern_params.height, pipe_ctx->stream_res.test_pattern_params.offset); + hwss_add_opp_set_disp_pattern_generator(seq_state, + odm_opp, + pipe_ctx->stream_res.test_pattern_params.test_pattern, + pipe_ctx->stream_res.test_pattern_params.color_space, + pipe_ctx->stream_res.test_pattern_params.color_depth, + (struct tg_color){0}, + false, + pipe_ctx->stream_res.test_pattern_params.width, + pipe_ctx->stream_res.test_pattern_params.height, + pipe_ctx->stream_res.test_pattern_params.offset); } } @@ -3025,9 +3034,8 @@ void dcn401_plane_atomic_power_down_sequence(struct dc *dc, /* Check and set DC_IP_REQUEST_CNTL if needed */ if (REG(DC_IP_REQUEST_CNTL)) { REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); - if (org_ip_request_cntl == 0) { + if (org_ip_request_cntl == 0) hwss_add_dc_ip_request_cntl(seq_state, dc, true); - } } /* DPP power gating control */ @@ -3043,9 +3051,8 @@ void dcn401_plane_atomic_power_down_sequence(struct dc *dc, hwss_add_dpp_reset(seq_state, dpp); /* Restore DC_IP_REQUEST_CNTL if it was originally 0 */ - if (org_ip_request_cntl == 0 && REG(DC_IP_REQUEST_CNTL)) { + if (org_ip_request_cntl == 0 && REG(DC_IP_REQUEST_CNTL)) hwss_add_dc_ip_request_cntl(seq_state, dc, false); - } DC_LOG_DEBUG("Power gated front end %d\n", hubp->inst); @@ -3087,14 +3094,12 @@ void dcn401_plane_atomic_disconnect_sequence(struct dc *dc, hwss_add_dc_set_optimized_required(seq_state, dc, true); /* Step 4: Disconnect HUBP if function exists */ - if (hubp->funcs->hubp_disconnect) { + if (hubp->funcs->hubp_disconnect) hwss_add_hubp_disconnect(seq_state, hubp); - } /* Step 5: Verify pstate change high if debug sanity checks are enabled */ - if (dc->debug.sanity_checks) { + if (dc->debug.sanity_checks) dc->hwseq->funcs.verify_allow_pstate_change_high_sequence(dc, seq_state); - } } void dcn401_blank_pixel_data_sequence( @@ -3418,14 +3423,12 @@ void dcn401_disable_plane_sequence( /* In flip immediate with pipe splitting case GSL is used for synchronization * so we must disable it when the plane is disabled. */ - if (pipe_ctx->stream_res.gsl_group != 0) { + if (pipe_ctx->stream_res.gsl_group != 0) dcn401_setup_gsl_group_as_lock_sequence(dc, pipe_ctx, false, seq_state); - } /* Update HUBP mall sel */ - if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs->hubp_update_mall_sel) { + if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs->hubp_update_mall_sel) hwss_add_hubp_update_mall_sel(seq_state, pipe_ctx->plane_res.hubp, 0, false); - } /* Set flip control GSL */ hwss_add_hubp_set_flip_control_gsl(seq_state, pipe_ctx->plane_res.hubp, false); @@ -3451,9 +3454,8 @@ void dcn401_disable_plane_sequence( pipe_ctx->plane_state = NULL; /* Turn back off the phantom OTG after the phantom plane is fully disabled */ - if (is_phantom && tg && tg->funcs->disable_phantom_crtc) { + if (is_phantom && tg && tg->funcs->disable_phantom_crtc) hwss_add_disable_phantom_crtc(seq_state, tg); - } } void dcn401_post_unlock_reset_opp_sequence( @@ -3473,15 +3475,14 @@ void dcn401_post_unlock_reset_opp_sequence( if (dsc) { bool *is_ungated = NULL; /* Check DSC power gate status */ - if (dc->hwseq && dc->hwseq->funcs.dsc_pg_status) { + if (dc->hwseq && dc->hwseq->funcs.dsc_pg_status) hwss_add_dsc_pg_status(seq_state, dc->hwseq, dsc->inst, false); - } /* Seamless update specific where we will postpone non - * double buffered DSCCLK disable logic in post unlock - * sequence after DSC is disconnected from OPP but not - * yet power gated. - */ + * double buffered DSCCLK disable logic in post unlock + * sequence after DSC is disconnected from OPP but not + * yet power gated. + */ /* DSC wait disconnect pending clear */ hwss_add_dsc_wait_disconnect_pending_clear(seq_state, dsc, is_ungated); @@ -3490,9 +3491,8 @@ void dcn401_post_unlock_reset_opp_sequence( hwss_add_dsc_disable(seq_state, dsc, is_ungated); /* Set reference DSCCLK */ - if (dccg && dccg->funcs->set_ref_dscclk) { + if (dccg && dccg->funcs->set_ref_dscclk) hwss_add_dccg_set_ref_dscclk(seq_state, dccg, dsc->inst, 0); - } } } @@ -3500,9 +3500,8 @@ void dcn401_dc_ip_request_cntl(struct dc *dc, bool enable) { struct dce_hwseq *hws = dc->hwseq; - if (REG(DC_IP_REQUEST_CNTL)) { + if (REG(DC_IP_REQUEST_CNTL)) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, enable ? 1 : 0); - } } void dcn401_enable_plane_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx, @@ -3512,52 +3511,43 @@ void dcn401_enable_plane_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx, struct dce_hwseq *hws = dc->hwseq; uint32_t org_ip_request_cntl = 0; - if (!pipe_ctx->plane_res.dpp || !pipe_ctx->plane_res.hubp || !pipe_ctx->stream_res.opp) { + if (!pipe_ctx->plane_res.dpp || !pipe_ctx->plane_res.hubp || !pipe_ctx->stream_res.opp) return; - } if (REG(DC_IP_REQUEST_CNTL)) REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); /* Step 1: DPP root clock control - enable clock */ - if (hws->funcs.dpp_root_clock_control) { + if (hws->funcs.dpp_root_clock_control) hwss_add_dpp_root_clock_control(seq_state, hws, pipe_ctx->plane_res.dpp->inst, true); - } /* Step 2: Enable DC IP request (if needed) */ - if (hws->funcs.dc_ip_request_cntl) { + if (hws->funcs.dc_ip_request_cntl) hwss_add_dc_ip_request_cntl(seq_state, dc, true); - } /* Step 3: DPP power gating control - power on */ - if (REG(DC_IP_REQUEST_CNTL) && hws->funcs.dpp_pg_control) { + if (REG(DC_IP_REQUEST_CNTL) && hws->funcs.dpp_pg_control) hwss_add_dpp_pg_control(seq_state, hws, pipe_ctx->plane_res.dpp->inst, true); - } /* Step 4: HUBP power gating control - power on */ - if (REG(DC_IP_REQUEST_CNTL) && hws->funcs.hubp_pg_control) { + if (REG(DC_IP_REQUEST_CNTL) && hws->funcs.hubp_pg_control) hwss_add_hubp_pg_control(seq_state, hws, pipe_ctx->plane_res.hubp->inst, true); - } /* Step 5: Disable DC IP request (restore state) */ - if (org_ip_request_cntl == 0 && hws->funcs.dc_ip_request_cntl) { + if (org_ip_request_cntl == 0 && hws->funcs.dc_ip_request_cntl) hwss_add_dc_ip_request_cntl(seq_state, dc, false); - } /* Step 6: HUBP clock control - enable DCFCLK */ - if (pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl) { + if (pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl) hwss_add_hubp_clk_cntl(seq_state, pipe_ctx->plane_res.hubp, true); - } /* Step 7: HUBP initialization */ - if (pipe_ctx->plane_res.hubp->funcs->hubp_init) { + if (pipe_ctx->plane_res.hubp->funcs->hubp_init) hwss_add_hubp_init(seq_state, pipe_ctx->plane_res.hubp); - } /* Step 8: OPP pipe clock control - enable */ - if (pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control) { + if (pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control) hwss_add_opp_pipe_clock_control(seq_state, pipe_ctx->stream_res.opp, true); - } /* Step 9: VM system aperture settings */ if (dc->vm_pa_config.valid && pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings) { @@ -3587,19 +3577,16 @@ void dcn401_update_dchubp_dpp_sequence(struct dc *dc, bool viewport_changed = false; enum mall_stream_type pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe_ctx); - if (!hubp || !dpp || !plane_state) { + if (!hubp || !dpp || !plane_state) return; - } /* Step 1: DPP DPPCLK control */ - if (pipe_ctx->update_flags.bits.dppclk) { + if (pipe_ctx->update_flags.bits.dppclk) hwss_add_dpp_dppclk_control(seq_state, dpp, false, true); - } /* Step 2: DCCG update DPP DTO */ - if (pipe_ctx->update_flags.bits.enable) { + if (pipe_ctx->update_flags.bits.enable) hwss_add_dccg_update_dpp_dto(seq_state, dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); - } /* Step 3: HUBP VTG selection */ if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { @@ -3616,17 +3603,15 @@ void dcn401_update_dchubp_dpp_sequence(struct dc *dc, } /* Step 5: Set unbounded requesting */ - if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting) { + if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting) hwss_add_hubp_set_unbounded_requesting(seq_state, hubp, pipe_ctx->unbounded_req); - } /* Step 6: HUBP interdependent setup */ if (pipe_ctx->update_flags.bits.hubp_interdependent) { - if (hubp->funcs->hubp_setup_interdependent2) { + if (hubp->funcs->hubp_setup_interdependent2) hwss_add_hubp_setup_interdependent2(seq_state, hubp, &pipe_ctx->hubp_regs); - } else if (hubp->funcs->hubp_setup_interdependent) { + else if (hubp->funcs->hubp_setup_interdependent) hwss_add_hubp_setup_interdependent(seq_state, hubp, &pipe_ctx->dlg_regs, &pipe_ctx->ttu_regs); - } } /* Step 7: DPP setup - input CSC and format setup */ @@ -3645,9 +3630,8 @@ void dcn401_update_dchubp_dpp_sequence(struct dc *dc, } /* Step 9: DPP program bias and scale */ - if (dpp->funcs->dpp_program_bias_and_scale) { + if (dpp->funcs->dpp_program_bias_and_scale) hwss_add_dpp_program_bias_and_scale(seq_state, pipe_ctx); - } } /* Step 10: MPCC updates */ @@ -3683,9 +3667,8 @@ void dcn401_update_dchubp_dpp_sequence(struct dc *dc, } /* Step 13: HUBP program mcache if available */ - if (hubp->funcs->hubp_program_mcache_id_and_split_coordinate) { + if (hubp->funcs->hubp_program_mcache_id_and_split_coordinate) hwss_add_hubp_program_mcache_id(seq_state, hubp, &pipe_ctx->mcache_regs); - } /* Step 14: Cursor attribute setup */ if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || @@ -3698,9 +3681,8 @@ void dcn401_update_dchubp_dpp_sequence(struct dc *dc, hwss_add_set_cursor_position(seq_state, dc, pipe_ctx); /* Step 16: Cursor SDR white level */ - if (dc->hwss.set_cursor_sdr_white_level) { + if (dc->hwss.set_cursor_sdr_white_level) hwss_add_set_cursor_sdr_white_level(seq_state, dc, pipe_ctx); - } } /* Step 17: Gamut remap and output CSC */ @@ -3747,7 +3729,8 @@ void dcn401_update_dchubp_dpp_sequence(struct dc *dc, /* SubVP save surface address if needed */ if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_mall_type == SUBVP_MAIN) { - hwss_add_dmub_subvp_save_surf_addr(seq_state, dc->ctx->dmub_srv, &pipe_ctx->plane_state->address, pipe_ctx->subvp_index); + hwss_add_dmub_subvp_save_surf_addr(seq_state, dc->ctx->dmub_srv, + &pipe_ctx->plane_state->address, pipe_ctx->subvp_index); } /* Update plane address */ @@ -3755,14 +3738,12 @@ void dcn401_update_dchubp_dpp_sequence(struct dc *dc, } /* Step 20: HUBP set blank - enable plane */ - if (pipe_ctx->update_flags.bits.enable) { + if (pipe_ctx->update_flags.bits.enable) hwss_add_hubp_set_blank(seq_state, hubp, false); - } /* Step 21: Phantom HUBP post enable */ - if (pipe_mall_type == SUBVP_PHANTOM && hubp->funcs->phantom_hubp_post_enable) { + if (pipe_mall_type == SUBVP_PHANTOM && hubp->funcs->phantom_hubp_post_enable) hwss_add_phantom_hubp_post_enable(seq_state, hubp); - } } void dcn401_update_mpcc_sequence(struct dc *dc, @@ -3777,9 +3758,8 @@ void dcn401_update_mpcc_sequence(struct dc *dc, struct mpc *mpc = dc->res_pool->mpc; struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); - if (!hubp || !pipe_ctx->plane_state) { + if (!hubp || !pipe_ctx->plane_state) return; - } per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; @@ -3837,9 +3817,8 @@ void dcn401_update_mpcc_sequence(struct dc *dc, hwss_add_mpc_remove_mpcc(seq_state, mpc, mpc_tree_params, new_mpcc); } else { /* Step 4: Assert MPCC idle (debug only) */ - if (dc->debug.sanity_checks) { + if (dc->debug.sanity_checks) hwss_add_mpc_assert_idle_mpcc(seq_state, mpc, mpcc_id); - } } /* Step 5: Insert new plane into MPC tree */ @@ -3873,9 +3852,8 @@ void dcn401_wait_for_mpcc_disconnect_sequence( { int mpcc_inst; - if (dc->debug.sanity_checks) { + if (dc->debug.sanity_checks) dc->hwseq->funcs.verify_allow_pstate_change_high_sequence(dc, seq_state); - } if (!pipe_ctx->stream_res.opp) return; @@ -3889,15 +3867,13 @@ void dcn401_wait_for_mpcc_disconnect_sequence( hwss_add_mpc_assert_idle_mpcc(seq_state, res_pool->mpc, mpcc_inst); } pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false; - if (hubp) { + if (hubp) hwss_add_hubp_set_blank(seq_state, hubp, true); - } } } - if (dc->debug.sanity_checks) { + if (dc->debug.sanity_checks) dc->hwseq->funcs.verify_allow_pstate_change_high_sequence(dc, seq_state); - } } void dcn401_setup_vupdate_interrupt_sequence(struct dc *dc, struct pipe_ctx *pipe_ctx, @@ -3909,9 +3885,8 @@ void dcn401_setup_vupdate_interrupt_sequence(struct dc *dc, struct pipe_ctx *pip if (start_line < 0) start_line = 0; - if (tg->funcs->setup_vertical_interrupt2) { + if (tg->funcs->setup_vertical_interrupt2) hwss_add_tg_setup_vertical_interrupt2(seq_state, tg, start_line); - } } void dcn401_set_hdr_multiplier_sequence(struct pipe_ctx *pipe_ctx, @@ -3987,9 +3962,8 @@ void dcn401_program_mall_pipe_config_sequence(struct dc *dc, struct dc_state *co struct hubp *hubp = pipe->plane_res.hubp; if (pipe->stream && hubp && hubp->funcs->hubp_prepare_subvp_buffering) { - if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) { + if (dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) hwss_add_hubp_prepare_subvp_buffering(seq_state, hubp, true); - } } } } @@ -4020,11 +3994,11 @@ bool dcn401_hw_wa_force_recovery_sequence(struct dc *dc, /* Step 1: Set HUBP_BLANK_EN=1 for all active pipes */ for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + if (pipe_ctx != NULL) { hubp = pipe_ctx->plane_res.hubp; - if (hubp != NULL && hubp->funcs->set_hubp_blank_en) { + if (hubp != NULL && hubp->funcs->set_hubp_blank_en) hwss_add_hubp_set_blank_en(seq_state, hubp, true); - } } } @@ -4034,22 +4008,22 @@ bool dcn401_hw_wa_force_recovery_sequence(struct dc *dc, /* Step 3: Set HUBP_DISABLE=1 for all active pipes */ for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + if (pipe_ctx != NULL) { hubp = pipe_ctx->plane_res.hubp; - if (hubp != NULL && hubp->funcs->hubp_disable_control) { + if (hubp != NULL && hubp->funcs->hubp_disable_control) hwss_add_hubp_disable_control(seq_state, hubp, true); - } } } /* Step 4: Set HUBP_DISABLE=0 for all active pipes */ for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + if (pipe_ctx != NULL) { hubp = pipe_ctx->plane_res.hubp; - if (hubp != NULL && hubp->funcs->hubp_disable_control) { + if (hubp != NULL && hubp->funcs->hubp_disable_control) hwss_add_hubp_disable_control(seq_state, hubp, false); - } } } @@ -4059,11 +4033,11 @@ bool dcn401_hw_wa_force_recovery_sequence(struct dc *dc, /* Step 6: Set HUBP_BLANK_EN=0 for all active pipes */ for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + if (pipe_ctx != NULL) { hubp = pipe_ctx->plane_res.hubp; - if (hubp != NULL && hubp->funcs->set_hubp_blank_en) { + if (hubp != NULL && hubp->funcs->set_hubp_blank_en) hwss_add_hubp_set_blank_en(seq_state, hubp, false); - } } } From 8ed59513827106f6f78144cde5a8e6f1611dd8d0 Mon Sep 17 00:00:00 2001 From: Cruise Hung Date: Wed, 8 Oct 2025 14:44:29 +0800 Subject: [PATCH 2281/2653] drm/amd/display: Control BW allocation in FW side [Why] The BW allocation feature should be controlled in FW side. [How] Pass the control bit to FW boot option. Reviewed-by: Meenakshikumar Somasundaram Reviewed-by: Nicholas Kazlauskas Signed-off-by: Cruise Hung Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 3 +-- .../gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c | 5 ----- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 + drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c | 1 + drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 1 + 5 files changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 196b1416c4b91..5803453312bb5 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -850,8 +850,7 @@ union dpia_debug_options { uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ uint32_t disable_usb4_pm_support:1; /* bit 5 */ uint32_t enable_usb4_bw_zero_alloc_patch:1; /* bit 6 */ - uint32_t enable_bw_allocation_mode:1; /* bit 7 */ - uint32_t reserved:24; + uint32_t reserved:25; } bits; uint32_t raw; }; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c index b16eb97ae11c9..c958d3f600c8f 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c @@ -225,11 +225,6 @@ bool link_dpia_enable_usb4_dp_bw_alloc_mode(struct dc_link *link) bool ret = false; uint8_t val; - if (link->dc->debug.dpia_debug.bits.enable_bw_allocation_mode == false) { - DC_LOG_DEBUG("%s: link[%d] DPTX BW allocation mode disabled", __func__, link->link_index); - return false; - } - val = DPTX_BW_ALLOC_MODE_ENABLE | DPTX_BW_ALLOC_UNMASK_IRQ; if (core_link_write_dpcd(link, DPTX_BW_ALLOCATION_MODE_CONTROL, &val, sizeof(uint8_t)) == DC_OK) { diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index 9012a7ba16021..f25c2fc2f98fd 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -318,6 +318,7 @@ struct dmub_srv_hw_params { bool enable_non_transparent_setconfig; bool lower_hbr3_phy_ssc; bool override_hbr3_pll_vco; + bool disable_dpia_bw_allocation; }; /** diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c index 4777c7203b2c2..cd04d7c756c3d 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c @@ -380,6 +380,7 @@ void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu boot_options.bits.override_hbr3_pll_vco = params->override_hbr3_pll_vco; boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic == DMUB_ASIC_DCN31B) ? 1 : 0; + boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation; REG_WRITE(DMCUB_SCRATCH14, boot_options.all); } diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c index 834e5434ccb88..b40482dbd6ad6 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c @@ -418,6 +418,7 @@ void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu boot_options.bits.disable_sldo_opt = params->disable_sldo_opt; boot_options.bits.enable_non_transparent_setconfig = params->enable_non_transparent_setconfig; boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc; + boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation; REG_WRITE(DMCUB_SCRATCH14, boot_options.all); } From 2d6f5b8753f423009fb0efbeb66a6b8440d7978e Mon Sep 17 00:00:00 2001 From: Meenakshikumar Somasundaram Date: Wed, 8 Oct 2025 13:35:07 -0400 Subject: [PATCH 2282/2653] drm/amd/display: write segment pointer with mot enabled for mst [Why] Some mst branches NAK's segment pointer writes with mot disabled. So reset of segment pointer to 0 should be performed with mot enabled. [How] Write segment pointer of mst branch devices with mot enabled. Reviewed-by: Cruise Hung Signed-off-by: Meenakshikumar Somasundaram Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/link/link_factory.c | 3 --- .../drm/amd/display/dc/link/protocols/link_dp_capability.c | 6 ++++++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c index 31a73867cd4cf..f06af98d46ee8 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@ -817,9 +817,6 @@ static bool construct_dpia(struct dc_link *link, link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; - /* Some docks seem to NAK I2C writes to segment pointer with mot=0. */ - link->wa_flags.dp_mot_reset_segment = true; - return true; ddc_create_fail: diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 7c2135c240aca..e480a87e7cf61 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -1868,6 +1868,12 @@ static bool retrieve_link_cap(struct dc_link *link) link->dpcd_caps.is_mst_capable = read_is_mst_supported(link); DC_LOG_DC("%s: MST_Support: %s\n", __func__, str_yes_no(link->dpcd_caps.is_mst_capable)); + /* Some MST docks seem to NAK I2C writes to segment pointer with mot=0. */ + if (link->dpcd_caps.is_mst_capable) + link->wa_flags.dp_mot_reset_segment = true; + else + link->wa_flags.dp_mot_reset_segment = false; + get_active_converter_info(ds_port.byte, link); dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data)); From 90dcd089f6004a51d00579630d8966638d2eb287 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 10 Oct 2025 19:21:13 -0500 Subject: [PATCH 2283/2653] drm/amd/display: Promote DC to 3.2.355 This version brings along following update: -Fix GFP_ATOMIC abuse -Fix several checkpatch issues -Set DCN32 to use update planes and stream version 3 -Write segment pointer with mot enabled for MST -Control BW allocation in FW side -Change clean dsc blocks condition in accelerated mode -Check disable_fec flag before enabling FEC Acked-by: Wayne Lin Signed-off-by: Taimur Hassan Signed-off-by: Tom Chung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5803453312bb5..e917c65eedd78 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.354" +#define DC_VER "3.2.355" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From eb6294aa70400100663330281e2ceecc9250c73d Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 25 Sep 2025 14:31:54 +0530 Subject: [PATCH 2284/2653] drm/amdgpu/userqueue: validate userptrs for userqueues MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit userptrs could be changed by the user at any time and hence while locking all the bos before GPU start processing validate all the userptr bos. Signed-off-by: Sunil Khatri Reviewed-by: Christian König Change-Id: I4a90c100bade114f0ff4f56a029599eb61c7cdd3 --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 79 +++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index b270ec2d92130..d91b4cb05ef1c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -29,6 +29,7 @@ #include "amdgpu.h" #include "amdgpu_vm.h" #include "amdgpu_userq.h" +#include "amdgpu_hmm.h" #include "amdgpu_userq_fence.h" u32 amdgpu_userq_get_supported_ip_mask(struct amdgpu_device *adev) @@ -861,12 +862,21 @@ static int amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) { struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr); + bool invalidated = false, new_addition = false; + struct ttm_operation_ctx ctx = { true, false }; struct amdgpu_device *adev = uq_mgr->adev; + struct amdgpu_hmm_range *range; struct amdgpu_vm *vm = &fpriv->vm; + unsigned long key, tmp_key; struct amdgpu_bo_va *bo_va; + struct amdgpu_bo *bo; struct drm_exec exec; + struct xarray xa; int ret; + xa_init(&xa); + +retry_lock: drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); drm_exec_until_all_locked(&exec) { ret = amdgpu_vm_lock_pd(vm, &exec, 1); @@ -893,10 +903,72 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) goto unlock_all; } + if (invalidated) { + xa_for_each(&xa, tmp_key, range) { + bo = range->bo; + amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); + ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); + if (ret) + goto unlock_all; + + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, range); + + amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); + ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); + if (ret) + goto unlock_all; + } + invalidated = false; + } + ret = amdgpu_vm_handle_moved(adev, vm, NULL); if (ret) goto unlock_all; + key = 0; + /* Validate User Ptr BOs */ + list_for_each_entry(bo_va, &vm->done, base.vm_status) { + bo = bo_va->base.bo; + + if (!amdgpu_ttm_tt_is_userptr(bo->tbo.ttm)) + continue; + + range = xa_load(&xa, key); + if (range && range->bo != bo) { + xa_erase(&xa, key); + amdgpu_hmm_range_free(range); + range = NULL; + } + + if (!range) { + range = amdgpu_hmm_range_alloc(bo); + if (!range) { + ret = -ENOMEM; + goto unlock_all; + } + + xa_store(&xa, key, range, GFP_KERNEL); + new_addition = true; + } + key++; + } + + if (new_addition) { + drm_exec_fini(&exec); + xa_for_each(&xa, tmp_key, range) { + if (!range) + continue; + bo = range->bo; + ret = amdgpu_ttm_tt_get_user_pages(bo, range); + if (ret) + goto unlock_all; + } + + invalidated = true; + new_addition = false; + goto retry_lock; + } + ret = amdgpu_vm_update_pdes(adev, vm, false); if (ret) goto unlock_all; @@ -916,6 +988,13 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) unlock_all: drm_exec_fini(&exec); + xa_for_each(&xa, tmp_key, range) { + if (!range) + continue; + bo = range->bo; + amdgpu_hmm_range_free(range); + } + xa_destroy(&xa); return ret; } From 63d057f0e83f920eed3cb21ca76464b13848c5a7 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 14 Oct 2025 11:12:56 +0800 Subject: [PATCH 2285/2653] drm/amdkcl: wrap code under macro define HAVE_AMDKCL_HMM_MIRROR_ENABLED It's caused by the commit: 7fa2cac7 "drm/amdgpu/userqueue: validate userptrs for userqueues" Signed-off-by: Chengjun Yao Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index d91b4cb05ef1c..e3fe7e1901a84 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -862,21 +862,28 @@ static int amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) { struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr); + struct amdgpu_device *adev = uq_mgr->adev; + struct amdgpu_vm *vm = &fpriv->vm; + struct amdgpu_bo_va *bo_va; + struct drm_exec exec; + int ret; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool invalidated = false, new_addition = false; struct ttm_operation_ctx ctx = { true, false }; - struct amdgpu_device *adev = uq_mgr->adev; struct amdgpu_hmm_range *range; - struct amdgpu_vm *vm = &fpriv->vm; unsigned long key, tmp_key; - struct amdgpu_bo_va *bo_va; struct amdgpu_bo *bo; - struct drm_exec exec; struct xarray xa; - int ret; xa_init(&xa); retry_lock: +#else + dev_warn_once(adev->dev, "HMM is not functional; falling back to legacy path. " + "Legacy path is untested and may be unstable. " + "Please enable HMM or refer to documentation for supported kernels.\n"); + WARN_ON_ONCE(1); +#endif drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); drm_exec_until_all_locked(&exec) { ret = amdgpu_vm_lock_pd(vm, &exec, 1); @@ -903,6 +910,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) goto unlock_all; } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (invalidated) { xa_for_each(&xa, tmp_key, range) { bo = range->bo; @@ -920,11 +928,13 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) } invalidated = false; } +#endif ret = amdgpu_vm_handle_moved(adev, vm, NULL); if (ret) goto unlock_all; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED key = 0; /* Validate User Ptr BOs */ list_for_each_entry(bo_va, &vm->done, base.vm_status) { @@ -968,6 +978,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) new_addition = false; goto retry_lock; } +#endif ret = amdgpu_vm_update_pdes(adev, vm, false); if (ret) @@ -988,6 +999,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) unlock_all: drm_exec_fini(&exec); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED xa_for_each(&xa, tmp_key, range) { if (!range) continue; @@ -995,6 +1007,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) amdgpu_hmm_range_free(range); } xa_destroy(&xa); +#endif return ret; } From e3a1b01e1aa7ed94d250f2f0bf5a89bae7baf59b Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 15 Oct 2025 11:12:39 +0800 Subject: [PATCH 2286/2653] drm/amdkcl: fake dev_printk.h header It's caused by the commit: 19da88431 "drm/amd/ras: Add amdgpu ras system functions" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/linux/dev_printk.h | 11 +++++++++++ 3 files changed, 19 insertions(+) create mode 100644 include/kcl/header/linux/dev_printk.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ebdae68c26743..9b035a4f1f1ed 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -952,6 +952,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DEVICE_CLASS_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DEV_PRINTK_H 1 + /* Define to 1 if you have the header file. */ /* #undef HAVE_LINUX_DMA_ATTRS_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index bf27afe78e544..640ce25dcfd15 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -179,4 +179,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #kunit: support failure from dynamic analysis tools dnl AC_KERNEL_CHECK_HEADERS([kunit/test-bug.h]) + + dnl #v5.5-rc2-4-gaf628aae8640 + dnl #device.h: move dev_printk()-like functions to dev_printk.h + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dev_printk.h]) ]) diff --git a/include/kcl/header/linux/dev_printk.h b/include/kcl/header/linux/dev_printk.h new file mode 100644 index 0000000000000..876e5c2928554 --- /dev/null +++ b/include/kcl/header/linux/dev_printk.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_DEV_PRINTK_H +#define _KCL_HEADER_LINUX_DEV_PRINTK_H + +#ifdef HAVE_LINUX_DEV_PRINTK_H +#include_next +#else +#include +#endif + +#endif \ No newline at end of file From ee4d6ed8e6fb1ba029198739942a334844264ae3 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 15 Oct 2025 13:56:35 +0800 Subject: [PATCH 2287/2653] drm/amdkcl: test whether mempool_alloc_preallocated is available It's caused by the commit: 0d5cdd74 "drm/amd/ras: Use ring buffer to record ras ecc data" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_mempool.c | 40 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/mempool_alloc_preallocated.m4 | 17 ++++++++ include/kcl/kcl_mempool.h | 15 +++++++ 7 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_mempool.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/mempool_alloc_preallocated.m4 create mode 100644 include/kcl/kcl_mempool.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 54408a4967250..b6a62c65e41ca 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -17,7 +17,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_timeconv.o kcl_drm_drv.o \ - kcl_dma_fence_array.o kcl_dma_fence_unwrap.o kcl_drm_probe_helper.o kcl_i2c_core_base.o + kcl_dma_fence_array.o kcl_dma_fence_unwrap.o kcl_drm_probe_helper.o kcl_i2c_core_base.o \ + kcl_mempool.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o kcl_debugfs_file.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mempool.c b/drivers/gpu/drm/amd/amdkcl/kcl_mempool.c new file mode 100644 index 0000000000000..aaa84255aff5d --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mempool.c @@ -0,0 +1,40 @@ +#include +#include + +#ifndef HAVE_MEMPOOL_ALLOC_PREALLOCATED +/* + * Backport of mempool_alloc_preallocated from commit 37dcc69ad17a0 + * (mempool: introduce mempool_use_prealloc_only). + */ +static void *remove_element(mempool_t *pool) +{ + void *element = pool->elements[--pool->curr_nr]; + + BUG_ON(pool->curr_nr < 0); + return element; +} + +void *kcl_mempool_alloc_preallocated(mempool_t *pool) +{ + void *element; + unsigned long flags; + + spin_lock_irqsave(&pool->lock, flags); + if (likely(pool->curr_nr)) { + element = remove_element(pool); + spin_unlock_irqrestore(&pool->lock, flags); + /* paired with rmb in mempool_free(), read comment there */ + smp_wmb(); + /* + * Update the allocation stack trace as this is more useful + * for debugging. + */ + kmemleak_update_trace(element); + return element; + } + spin_unlock_irqrestore(&pool->lock, flags); + + return NULL; +} +EXPORT_SYMBOL_GPL(kcl_mempool_alloc_preallocated); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index be369146360ab..53692b14fe277 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -154,5 +154,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9b035a4f1f1ed..fea8ce89b8f46 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1033,6 +1033,9 @@ /* memalloc_noreclaim_save() is available */ #define HAVE_MEMALLOC_NORECLAIM_SAVE 1 +/* mempool_alloc_preallocated() is available */ +#define HAVE_MEMPOOL_ALLOC_PREALLOCATED 1 + /* migrate_disable() is available */ #define HAVE_MIGRATE_DISABLE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7d8b00ac6905f..28aa0921c254c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -301,6 +301,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VFS_IOCB_ITER_READ AC_AMDGPU_LIST_IS_HEAD AC_AMDGPU_DEVM_I2C_ADD_ADAPTER + AC_AMDGPU_MEMPOOL_ALLOC_PREALLOCATED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/mempool_alloc_preallocated.m4 b/drivers/gpu/drm/amd/dkms/m4/mempool_alloc_preallocated.m4 new file mode 100644 index 0000000000000..8f11b7597c3a6 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mempool_alloc_preallocated.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.7-rc4-323-g37dcc69ad17a +dnl # mempool: introduce mempool_use_prealloc_only +dnl # +AC_DEFUN([AC_AMDGPU_MEMPOOL_ALLOC_PREALLOCATED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + mempool_alloc_preallocated(NULL); + ],[mempool_alloc_preallocated], [mm/mempool.c],[ + AC_DEFINE(HAVE_MEMPOOL_ALLOC_PREALLOCATED, 1, + [mempool_alloc_preallocated() is available]) + ]) + ]) +]) + \ No newline at end of file diff --git a/include/kcl/kcl_mempool.h b/include/kcl/kcl_mempool.h new file mode 100644 index 0000000000000..4bcc809d30aee --- /dev/null +++ b/include/kcl/kcl_mempool.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDGPU_BACKPORT_KCL_MEMPOOL_H +#define AMDGPU_BACKPORT_KCL_MEMPOOL_H + +#include + +#ifndef HAVE_MEMPOOL_ALLOC_PREALLOCATED + +extern void *kcl_mempool_alloc_preallocated(mempool_t *pool) __malloc; + +#define mempool_alloc_preallocated kcl_mempool_alloc_preallocated + +#endif + +#endif From da455aac582577ff15998fe0ac7c87dc50ff2f92 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Tue, 30 Sep 2025 10:47:49 +0800 Subject: [PATCH 2288/2653] drm/amdgpu: Add ras module files into amdgpu Add ras module files into amdgpu. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/Makefile | 8 +++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 1 + drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c | 2 +- drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 2 +- drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h | 1 + drivers/gpu/drm/amd/ras/rascore/ras_aca.c | 2 +- drivers/gpu/drm/amd/ras/rascore/ras_cmd.c | 9 ++------- drivers/gpu/drm/amd/ras/rascore/ras_core.c | 3 +-- drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c | 4 ++-- drivers/gpu/drm/amd/ras/rascore/ras_mp1.c | 2 +- drivers/gpu/drm/amd/ras/rascore/ras_psp.c | 4 ++-- 11 files changed, 20 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 273daa144480f..2aea62e324ff0 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -37,7 +37,8 @@ ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \ -I$(FULL_AMD_DISPLAY_PATH)/modules/inc \ -I$(FULL_AMD_DISPLAY_PATH)/dc \ -I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm \ - -I$(FULL_AMD_PATH)/amdkfd + -I$(FULL_AMD_PATH)/amdkfd \ + -I$(FULL_AMD_PATH)/ras/ras_mgr # Locally disable W=1 warnings enabled in drm subsystem Makefile subdir-ccflags-y += -Wno-override-init @@ -325,6 +326,11 @@ amdgpu-y += \ isp_v4_1_1.o endif +AMD_GPU_RAS_PATH := ../ras +AMD_GPU_RAS_FULL_PATH := $(FULL_AMD_PATH)/ras +include $(AMD_GPU_RAS_FULL_PATH)/Makefile +amdgpu-y += $(AMD_GPU_RAS_FILES) + include $(FULL_AMD_PATH)/backport/Makefile obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index 6cf0dfd38be8b..9f21b6cf87245 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -504,6 +504,7 @@ struct ras_critical_region { }; struct amdgpu_ras { + void *ras_mgr; /* ras infrastructure */ /* for ras itself. */ uint32_t features; diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c index 195ca51a96d5a..4706e737969a1 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c @@ -68,7 +68,7 @@ static struct ras_core_context *ras_cmd_get_ras_core(uint64_t dev_handle) if (!dev_handle || (dev_handle == RAS_CMD_DEV_HANDLE_MAGIC)) return NULL; - ras_core = (struct ras_core_context *)(dev_handle ^ RAS_CMD_DEV_HANDLE_MAGIC); + ras_core = (struct ras_core_context *)(uintptr_t)(dev_handle ^ RAS_CMD_DEV_HANDLE_MAGIC); if (ras_cmd_get_dev_handle(ras_core) == dev_handle) return ras_core; diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c index a038c87c045d8..e66d915831a96 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -373,7 +373,7 @@ struct amdgpu_ras_mgr *amdgpu_ras_mgr_get_context(struct amdgpu_device *adev) return (struct amdgpu_ras_mgr *)adev->psp.ras_context.ras->ras_mgr; } -static const struct amd_ip_funcs ras_v1_0_ip_funcs = { +static const struct amd_ip_funcs __maybe_unused ras_v1_0_ip_funcs = { .name = "ras_v1_0", .sw_init = amdgpu_ras_mgr_sw_init, .sw_fini = amdgpu_ras_mgr_sw_fini, diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h b/drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h index c48ff26525d6e..8156531a7b637 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h +++ b/drivers/gpu/drm/amd/ras/ras_mgr/ras_sys.h @@ -27,6 +27,7 @@ #include #include #include +#include #include "amdgpu.h" #define RAS_DEV_ERR(device, fmt, ...) \ diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_aca.c b/drivers/gpu/drm/amd/ras/rascore/ras_aca.c index f9b8a1fa4f1fc..e433c70d29891 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_aca.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_aca.c @@ -350,7 +350,7 @@ static int aca_banks_update(struct ras_core_context *ras_core, struct aca_bank_ecc bank_ecc; struct ras_log_batch_tag *batch_tag = NULL; u32 count = 0; - int ret; + int ret = 0; int i; mutex_lock(&ras_core->ras_aca.bank_op_lock); diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c index 697619b30ea27..6fe3b115986c5 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c @@ -32,7 +32,7 @@ static int ras_cmd_add_device(struct ras_core_context *ras_core) { INIT_LIST_HEAD(&ras_core->ras_cmd.head); ras_core->ras_cmd.ras_core = ras_core; - ras_core->ras_cmd.dev_handle = (uint64_t)ras_core ^ RAS_CMD_DEV_HANDLE_MAGIC; + ras_core->ras_cmd.dev_handle = (uintptr_t)ras_core ^ RAS_CMD_DEV_HANDLE_MAGIC; return 0; } @@ -212,11 +212,6 @@ static int ras_cmd_get_cper_records(struct ras_core_context *ras_core, if (!req->buf_size || !req->buf_ptr || !req->cper_num) return RAS_CMD__ERROR_INVALID_INPUT_DATA; - if (!access_ok((void *)req->buf_ptr, req->buf_size)) { - RAS_DEV_ERR(ras_core->dev, "Invalid cper buffer memory!\n"); - return RAS_CMD__ERROR_INVALID_INPUT_DATA; - } - buffer = kzalloc(req->buf_size, GFP_KERNEL); if (!buffer) return RAS_CMD__ERROR_GENERIC; @@ -240,7 +235,7 @@ static int ras_cmd_get_cper_records(struct ras_core_context *ras_core, } if ((ret && (ret != -ENOMEM)) || - copy_to_user((void *)req->buf_ptr, buffer, offset)) { + copy_to_user(u64_to_user_ptr(req->buf_ptr), buffer, offset)) { kfree(buffer); return RAS_CMD__ERROR_GENERIC; } diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c index 41fc9f0d84e4f..45fc0608043f8 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c @@ -68,8 +68,7 @@ int ras_core_convert_timestamp_to_time(struct ras_core_context *ras_core, int seconds_per_minute = 60; int days, remaining_seconds; - days = timestamp / seconds_per_day; - remaining_seconds = timestamp % seconds_per_day; + days = div64_u64_rem(timestamp, seconds_per_day, (uint64_t *)&remaining_seconds); /* utc_timestamp follows the Unix epoch */ year = 1970; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c b/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c index bca094058f91f..d0621464f1a76 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c @@ -67,7 +67,7 @@ static int ras_log_ring_add_data(struct ras_core_context *ras_core, { struct ras_log_ring *log_ring = &ras_core->ras_log_ring; unsigned long flags = 0; - int ret; + int ret = 0; if (batch_tag && (batch_tag->sub_seqno >= MAX_RECORD_PER_BATCH)) { RAS_DEV_ERR(ras_core->dev, @@ -200,7 +200,7 @@ struct ras_log_batch_tag *ras_log_ring_create_batch_tag(struct ras_core_context { struct ras_log_ring *log_ring = &ras_core->ras_log_ring; struct ras_log_batch_tag *batch_tag; - unsigned long flags; + unsigned long flags = 0; batch_tag = kzalloc(sizeof(*batch_tag), GFP_KERNEL); if (!batch_tag) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_mp1.c b/drivers/gpu/drm/amd/ras/rascore/ras_mp1.c index 92f250e2466d5..f3321df850212 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_mp1.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_mp1.c @@ -52,7 +52,7 @@ int ras_mp1_get_bank_count(struct ras_core_context *ras_core, } int ras_mp1_dump_bank(struct ras_core_context *ras_core, - enum ras_err_type type, u32 idx, u32 reg_idx, u64 *val) + u32 type, u32 idx, u32 reg_idx, u64 *val) { struct ras_mp1 *mp1 = &ras_core->ras_mp1; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_psp.c b/drivers/gpu/drm/amd/ras/rascore/ras_psp.c index c94effd4b1140..ccdb42d2dd605 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_psp.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_psp.c @@ -173,7 +173,7 @@ static uint32_t __get_ring_frame_slot(struct ras_core_context *ras_core) ras_ring_wptr_dw = psp->ip_func->psp_ras_ring_wptr_get(ras_core); - return (ras_ring_wptr_dw << 2) / sizeof(struct psp_gfx_rb_frame); + return div64_u64((ras_ring_wptr_dw << 2), sizeof(struct psp_gfx_rb_frame)); } static int __set_ring_frame_slot(struct ras_core_context *ras_core, @@ -200,7 +200,7 @@ static int write_frame_to_ras_psp_ring(struct ras_core_context *ras_core, return -ENOMEM; max_frame_slot = - ring_mem->mem_size / sizeof(struct psp_gfx_rb_frame); + div64_u64(ring_mem->mem_size, sizeof(struct psp_gfx_rb_frame)); rb_frame = (struct psp_gfx_rb_frame *)ring_mem->mem_cpu_addr; From bafcb226b0f36ce4e8d26cf70d8391e7e62d4030 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Sun, 28 Sep 2025 14:25:27 +0800 Subject: [PATCH 2289/2653] drm/amdgpu: Intercept ras interrupts to ras module Intercept ras interrupts to ras module. V2: Change function names in ras module. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 15 +++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 16 ++++++++++++++++ drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 4 ++-- drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h | 4 ++-- 4 files changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 70f5334775a6f..39d712e3e692a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -36,6 +36,7 @@ #include "amdgpu_ras.h" #include "amdgpu_umc.h" #include "amdgpu_reset.h" +#include "amdgpu_ras_mgr.h" /* Total memory size in system memory and all GPU VRAM. Used to * estimate worst case amount of memory to reserve for page tables @@ -756,6 +757,20 @@ void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device *ad enum amdgpu_ras_block block, uint16_t pasid, pasid_notify pasid_fn, void *data, uint32_t reset) { + + if (amdgpu_uniras_enabled(adev)) { + struct ras_ih_info ih_info; + + memset(&ih_info, 0, sizeof(ih_info)); + ih_info.block = block; + ih_info.pasid = pasid; + ih_info.reset = reset; + ih_info.pasid_fn = pasid_fn; + ih_info.data = data; + amdgpu_ras_mgr_handle_consumer_interrupt(adev, &ih_info); + return; + } + amdgpu_umc_pasid_poison_handler(adev, block, pasid, pasid_fn, data, reset); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index c6f3a327108b8..0609242fa481d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -41,6 +41,7 @@ #include "atom.h" #include "amdgpu_reset.h" #include "amdgpu_psp.h" +#include "amdgpu_ras_mgr.h" #ifdef CONFIG_X86_MCE_AMD #include @@ -2253,6 +2254,11 @@ void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev) amdgpu_ras_is_err_state(adev, AMDGPU_RAS_BLOCK__ANY)) return; + if (amdgpu_uniras_enabled(adev)) { + amdgpu_ras_mgr_handle_fatal_interrupt(adev, NULL); + return; + } + if (adev->nbio.ras && adev->nbio.ras->handle_ras_controller_intr_no_bifring) adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev); @@ -2425,6 +2431,16 @@ int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, struct ras_manager *obj; struct ras_ih_data *data; + if (amdgpu_uniras_enabled(adev)) { + struct ras_ih_info ih_info; + + memset(&ih_info, 0, sizeof(ih_info)); + ih_info.block = info->head.block; + memcpy(&ih_info.iv_entry, info->entry, sizeof(struct amdgpu_iv_entry)); + + return amdgpu_ras_mgr_handle_controller_interrupt(adev, &ih_info); + } + obj = amdgpu_ras_find_obj(adev, &info->head); if (!obj) return -EINVAL; diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c index e66d915831a96..a8d02bd42f908 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -381,7 +381,7 @@ static const struct amd_ip_funcs __maybe_unused ras_v1_0_ip_funcs = { .hw_fini = amdgpu_ras_mgr_hw_fini, }; -int amdgpu_enable_unified_ras(struct amdgpu_device *adev, bool enable) +int amdgpu_enable_uniras(struct amdgpu_device *adev, bool enable) { struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); @@ -395,7 +395,7 @@ int amdgpu_enable_unified_ras(struct amdgpu_device *adev, bool enable) return ras_core_set_status(ras_mgr->ras_core, enable); } -bool amdgpu_unified_ras_enabled(struct amdgpu_device *adev) +bool amdgpu_uniras_enabled(struct amdgpu_device *adev) { struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h index fa761de381c19..8d6a1873b6669 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h @@ -56,8 +56,8 @@ struct amdgpu_ras_mgr { struct amdgpu_ras_mgr *amdgpu_ras_mgr_get_context( struct amdgpu_device *adev); -int amdgpu_enable_unified_ras(struct amdgpu_device *adev, bool enable); -bool amdgpu_unified_ras_enabled(struct amdgpu_device *adev); +int amdgpu_enable_uniras(struct amdgpu_device *adev, bool enable); +bool amdgpu_uniras_enabled(struct amdgpu_device *adev); int amdgpu_ras_mgr_handle_fatal_interrupt(struct amdgpu_device *adev, void *data); int amdgpu_ras_mgr_handle_controller_interrupt(struct amdgpu_device *adev, void *data); int amdgpu_ras_mgr_handle_consumer_interrupt(struct amdgpu_device *adev, void *data); From 6a3529dab89272c93b6785ac76466d09a9b42cd4 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 21 Jul 2025 15:14:03 +0800 Subject: [PATCH 2290/2653] drm/amdgpu: Improve ras fatal error handling function In multi-gpu case, a fatal error will generate several fatal error interrupts. After improving this function, the ras module can reuse this function to only handle the first interrupt. V3: Initialize event_id using RAS_EVENT_INVALID_ID. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 16 ++++++++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 2 +- drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c | 5 +++++ 3 files changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 0609242fa481d..77aaeae1022c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -4677,20 +4677,18 @@ u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type return id; } -void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) +int amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) { if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); enum ras_event_type type = RAS_EVENT_TYPE_FATAL; - u64 event_id; + u64 event_id = RAS_EVENT_INVALID_ID; - if (amdgpu_ras_mark_ras_event(adev, type)) { - dev_err(adev->dev, - "uncorrectable hardware error (ERREVENT_ATHUB_INTERRUPT) detected!\n"); - return; - } + if (amdgpu_uniras_enabled(adev)) + return 0; - event_id = amdgpu_ras_acquire_event_id(adev, type); + if (!amdgpu_ras_mark_ras_event(adev, type)) + event_id = amdgpu_ras_acquire_event_id(adev, type); RAS_EVENT_LOG(adev, event_id, "uncorrectable hardware error" "(ERREVENT_ATHUB_INTERRUPT) detected!\n"); @@ -4699,6 +4697,8 @@ void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET; amdgpu_ras_reset_gpu(adev); } + + return -EBUSY; } bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index 9f21b6cf87245..556cf4d7b5ef8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -910,7 +910,7 @@ static inline void amdgpu_ras_intr_cleared(void) atomic_set(&amdgpu_ras_in_intr, 0); } -void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev); +int amdgpu_ras_global_ras_isr(struct amdgpu_device *adev); void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready); diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c index 40071b8763336..f21cd55a25be9 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c @@ -29,8 +29,13 @@ static int amdgpu_ras_sys_detect_fatal_event(struct ras_core_context *ras_core, void *data) { struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + int ret; uint64_t seq_no; + ret = amdgpu_ras_global_ras_isr(adev); + if (ret) + return ret; + seq_no = amdgpu_ras_mgr_gen_ras_event_seqno(adev, RAS_SEQNO_TYPE_UE); RAS_DEV_INFO(adev, "{%llu} Uncorrectable hardware error(ERREVENT_ATHUB_INTERRUPT) detected!\n", From 500af08d0b58cc6083828f725eef4f3d6f278808 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Tue, 17 Jun 2025 15:16:59 +0800 Subject: [PATCH 2291/2653] drm/amdgpu: add ras module rma check Add ras module rma check. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 77aaeae1022c0..789ffc9f2cf72 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -5457,6 +5457,9 @@ bool amdgpu_ras_is_rma(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + if (amdgpu_uniras_enabled(adev)) + return amdgpu_ras_mgr_is_rma(adev); + if (!con) return false; From 103b114a4bf4019d9f089d699f7e14215202a0b2 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 21 Jul 2025 15:15:53 +0800 Subject: [PATCH 2292/2653] drm/amdgpu: Avoid loading bad pages into legacy ras When ras module is enabled, the bad pages will be loaded by ras module. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 789ffc9f2cf72..d76b7766bcf00 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3628,6 +3628,9 @@ int amdgpu_ras_init_badpage_info(struct amdgpu_device *adev) if (!con || amdgpu_sriov_vf(adev)) return 0; + if (amdgpu_uniras_enabled(adev)) + return 0; + control = &con->eeprom_control; ret = amdgpu_ras_eeprom_init(control); control->is_eeprom_valid = !ret; From 138ab0b6fec952fc48f3f6801befa53ab7832239 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 24 Mar 2025 18:20:17 +0800 Subject: [PATCH 2293/2653] drm/amdgpu: Add poison consumption sequence numbers for gfx and sdma Add poison consumption sequence numbers for gfx and sdma. V3: Use RAS_EVENT_LOG to print ras log info. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c index 4ceb251312a65..d76fb61869c75 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c @@ -28,6 +28,7 @@ #include "kfd_device_queue_manager.h" #include "kfd_smi_events.h" #include "amdgpu_ras.h" +#include "amdgpu_ras_mgr.h" /* * GFX9 SQ Interrupts @@ -228,7 +229,11 @@ static void event_interrupt_poison_consumption_v9(struct kfd_node *dev, kfd_signal_poison_consumed_event(dev, pasid); - event_id = amdgpu_ras_acquire_event_id(dev->adev, type); + if (amdgpu_uniras_enabled(dev->adev)) + event_id = amdgpu_ras_mgr_gen_ras_event_seqno(dev->adev, + RAS_SEQNO_TYPE_POISON_CONSUMPTION); + else + event_id = amdgpu_ras_acquire_event_id(dev->adev, type); RAS_EVENT_LOG(dev->adev, event_id, "poison is consumed by client %d, kick off gpu reset flow\n", client_id); From 5f9fcdd8c53ae2d2aeb79e6d0eb017e0a824ebe1 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Tue, 25 Mar 2025 14:11:10 +0800 Subject: [PATCH 2294/2653] drm/amdgpu: Avoid hive seqno increment in legacy ras The hive->event_mgr variable is used by both ras module and legacy ras. To ensure the continuity of hive seqno growth, after enabling ras module, it is forbidden to operate the event_mgr variable in legacy ras. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index d76b7766bcf00..a0adb4868a1f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -4630,6 +4630,9 @@ int amdgpu_ras_mark_ras_event_caller(struct amdgpu_device *adev, enum ras_event_ struct ras_event_state *event_state; int ret = 0; + if (amdgpu_uniras_enabled(adev)) + return 0; + if (type >= RAS_EVENT_TYPE_COUNT) { ret = -EINVAL; goto out; From 0013ea346e7f0e3ada29f3ea4fac21883936fc79 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Wed, 26 Mar 2025 18:03:49 +0800 Subject: [PATCH 2295/2653] drm/amdgpu: Add ras module eeprom safety watermark check Add ras module eeprom safety watermark check. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 3eb3fb55ccb05..5a7bf0661dbfb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -32,6 +32,7 @@ #include #include "amdgpu_reset.h" +#include "amdgpu_ras_mgr.h" /* These are memory addresses as would be seen by one or more EEPROM * chips strung on the I2C bus, usually by manipulating pins 1-3 of a @@ -556,6 +557,9 @@ bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + if (amdgpu_uniras_enabled(adev)) + return amdgpu_ras_mgr_check_eeprom_safety_watermark(adev); + if (!__is_ras_eeprom_supported(adev) || !amdgpu_bad_page_threshold) return false; From e2a02b80eefc5845c48f184bc8eea588a8f267e6 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 14 Oct 2025 13:11:02 +0530 Subject: [PATCH 2296/2653] drm/amdgpu: add the kernel docs for alloc/free/valid range MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add kernel docs for the functions related to hmm_range. Documents added for functions: amdgpu_hmm_range_valid amdgpu_hmm_range_alloc amdgpu_hmm_range_free Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 33 +++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index e4a1858609991..9076b8a74eed3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -920,6 +920,19 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, return r; } +/** + * amdgpu_hmm_range_valid - check if an HMM range is still valid + * @range: pointer to the &struct amdgpu_hmm_range to validate + * + * Determines whether the given HMM range @range is still valid by + * checking for invalidations via the MMU notifier sequence. This is + * typically used to verify that the range has not been invalidated + * by concurrent address space updates before it is accessed. + * + * Return: + * * true if @range is valid and can be used safely + * * false if @range is NULL or has been invalidated + */ bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range) { if (!range) @@ -929,6 +942,17 @@ bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range) range->hmm_range.notifier_seq); } +/** + * amdgpu_hmm_range_alloc - allocate and initialize an AMDGPU HMM range + * @bo: optional buffer object to associate with this HMM range + * + * Allocates memory for amdgpu_hmm_range and associates it with the @bo passed. + * The reference count of the @bo is incremented. + * + * Return: + * Pointer to a newly allocated struct amdgpu_hmm_range on success, + * or NULL if memory allocation fails. + */ struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo) { struct amdgpu_hmm_range *range; @@ -941,6 +965,15 @@ struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo) return range; } +/** + * amdgpu_hmm_range_free - release an AMDGPU HMM range + * @range: pointer to the range object to free + * + * Releases all resources held by @range, including the associated + * hmm_pfns and the dropping reference of associated bo if any. + * + * Return: void + */ void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range) { if (!range) From cd14e7a68fee806028769e9b887478d330e5e333 Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Wed, 15 Oct 2025 16:19:07 +0800 Subject: [PATCH 2297/2653] drm/amdgpu: check save count before RAS bad page saving It's possible that unit_num is larger than 0 but save_count is zero, since we do get bad page address but the address is invalid. Check unit_num and save_count together. Signed-off-by: Tao Zhou Reviewed-by: Candice Li --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index a0adb4868a1f8..0a1d5bba15f37 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3156,7 +3156,7 @@ int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev, *new_cnt = unit_num; /* only new entries are saved */ - if (unit_num > 0) { + if (unit_num && save_count) { /*old asics only save pa to eeprom like before*/ if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12) { if (amdgpu_ras_eeprom_append(control, From 19fdf8d82307f6de9db35f670d7cc491ecfa49fa Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 31 Mar 2025 11:12:58 +0800 Subject: [PATCH 2298/2653] drm/amdgpu: Add ras module ip block to amdgpu discovery Add ras module ip block to amdgpu discovery. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 20 +++++++++++++++++++ drivers/gpu/drm/amd/include/amd_shared.h | 1 + .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 8 ++++++++ .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h | 2 ++ 5 files changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index ff333213c4942..76e70d3ceaeb7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -382,7 +382,7 @@ int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block); int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block); -#define AMDGPU_MAX_IP_NUM 16 +#define AMDGPU_MAX_IP_NUM AMD_IP_BLOCK_TYPE_NUM struct amdgpu_ip_block_status { bool valid; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index e7d0c146cc788..615f35363b2b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -107,6 +107,7 @@ #include "vcn_v5_0_1.h" #include "jpeg_v5_0_0.h" #include "jpeg_v5_0_1.h" +#include "amdgpu_ras_mgr.h" #include "amdgpu_vpe.h" #if defined(CONFIG_DRM_AMD_ISP) @@ -2409,6 +2410,21 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) amdgpu_ip_version(adev, SDMA0_HWIP, 0)); return -EINVAL; } + + return 0; +} + +static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev) +{ + switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { + case IP_VERSION(13, 0, 6): + case IP_VERSION(13, 0, 12): + case IP_VERSION(13, 0, 14): + amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block); + break; + default: + break; + } return 0; } @@ -3189,6 +3205,10 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) if (r) return r; + r = amdgpu_discovery_set_ras_ip_blocks(adev); + if (r) + return r; + if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && !amdgpu_sriov_vf(adev)) || (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 75efda2969cfb..17945094a1383 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -109,6 +109,7 @@ enum amd_ip_block_type { AMD_IP_BLOCK_TYPE_VPE, AMD_IP_BLOCK_TYPE_UMSCH_MM, AMD_IP_BLOCK_TYPE_ISP, + AMD_IP_BLOCK_TYPE_RAS, AMD_IP_BLOCK_TYPE_NUM, }; diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c index a8d02bd42f908..3ae843d078d85 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -381,6 +381,14 @@ static const struct amd_ip_funcs __maybe_unused ras_v1_0_ip_funcs = { .hw_fini = amdgpu_ras_mgr_hw_fini, }; +const struct amdgpu_ip_block_version ras_v1_0_ip_block = { + .type = AMD_IP_BLOCK_TYPE_RAS, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &ras_v1_0_ip_funcs, +}; + int amdgpu_enable_uniras(struct amdgpu_device *adev, bool enable) { struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h index 8d6a1873b6669..814b65ef1c62e 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h @@ -54,6 +54,8 @@ struct amdgpu_ras_mgr { bool ras_is_ready; }; +extern const struct amdgpu_ip_block_version ras_v1_0_ip_block; + struct amdgpu_ras_mgr *amdgpu_ras_mgr_get_context( struct amdgpu_device *adev); int amdgpu_enable_uniras(struct amdgpu_device *adev, bool enable); From b3ba56a3f68cbb3e81f655a8be01462ecb23a5f0 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Thu, 16 Oct 2025 14:51:17 +0800 Subject: [PATCH 2299/2653] drm/amd: Fix set but not used warnings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are many set but not used warnings under drivers/gpu/drm/amd when compiling with the latest upstream mainline GCC: drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c:305:18: warning: variable ‘p’ set but not used [-Wunused-but-set-variable=] drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h:103:26: warning: variable ‘internal_reg_offset’ set but not used [-Wunused-but-set-variable=] ... drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h:164:26: warning: variable ‘internal_reg_offset’ set but not used [-Wunused-but-set-variable=] ... drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:445:13: warning: variable ‘pipe_idx’ set but not used [-Wunused-but-set-variable=] drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:875:21: warning: variable ‘pipe_idx’ set but not used [-Wunused-but-set-variable=] Remove the variables actually not used or add __maybe_unused attribute for the variables actually used to fix them, compile tested only. Signed-off-by: Tiezhu Yang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 4 +--- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 6 ++++-- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 9 +++------ 3 files changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index b2033f8352f50..83f3b94ed975a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -302,7 +302,6 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, int pages) { unsigned t; - unsigned p; int i, j; u64 page_base; /* Starting from VEGA10, system bit must be 0 to mean invalid. */ @@ -316,8 +315,7 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, return; t = offset / AMDGPU_GPU_PAGE_SIZE; - p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE; - for (i = 0; i < pages; i++, p++) { + for (i = 0; i < pages; i++) { page_base = adev->dummy_page_addr; if (!adev->gart.ptr) continue; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index dc8a17bcc3c8d..82624b44e661a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -100,7 +100,8 @@ #define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) \ ({ \ - uint32_t internal_reg_offset, addr; \ + /* To avoid a -Wunused-but-set-variable warning. */ \ + uint32_t internal_reg_offset __maybe_unused, addr; \ bool video_range, video1_range, aon_range, aon1_range; \ \ addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \ @@ -161,7 +162,8 @@ #define SOC24_DPG_MODE_OFFSET(ip, inst_idx, reg) \ ({ \ - uint32_t internal_reg_offset, addr; \ + /* To avoid a -Wunused-but-set-variable warning. */ \ + uint32_t internal_reg_offset __maybe_unused, addr; \ bool video_range, video1_range, aon_range, aon1_range; \ \ addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \ diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index c75663aefcf3f..4b20c01bf6461 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -442,7 +442,6 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru int i = 0, k = 0; int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it. uint8_t visual_confirm_enabled; - int pipe_idx = 0; struct dc_stream_status *stream_status = NULL; if (dc == NULL) @@ -457,7 +456,7 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled; if (should_manage_pstate) { - for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; if (!pipe->stream) @@ -472,7 +471,6 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us; break; } - pipe_idx++; } } @@ -872,7 +870,7 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc, bool enable) { uint8_t cmd_pipe_index = 0; - uint32_t i, pipe_idx; + uint32_t i; uint8_t subvp_count = 0; union dmub_rb_cmd cmd; struct pipe_ctx *subvp_pipes[2]; @@ -899,7 +897,7 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc, if (enable) { // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd - for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { + for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; pipe_mall_type = dc_state_get_pipe_subvp_type(context, pipe); @@ -922,7 +920,6 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc, populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); } - pipe_idx++; } if (subvp_count == 2) { update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes); From 2a38636e3a068a63bb78ddd694969765ceca9cb6 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Thu, 20 Mar 2025 17:04:14 +0800 Subject: [PATCH 2300/2653] drm/amdgpu: Enable ras module Enable ras module, disabled by default. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c index 3ae843d078d85..13c207c8a8430 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -335,6 +335,11 @@ static int amdgpu_ras_mgr_hw_init(struct amdgpu_ip_block *ip_block) struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); int ret; + /* Currently only debug mode can enable the ras module + */ + if (!adev->debug_enable_ras_aca) + return 0; + if (!ras_mgr || !ras_mgr->ras_core) return -EINVAL; @@ -346,6 +351,8 @@ static int amdgpu_ras_mgr_hw_init(struct amdgpu_ip_block *ip_block) ras_mgr->ras_is_ready = true; + amdgpu_enable_uniras(adev, true); + RAS_DEV_INFO(adev, "AMDGPU RAS Is Ready.\n"); return 0; } @@ -355,6 +362,11 @@ static int amdgpu_ras_mgr_hw_fini(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + /* Currently only debug mode can enable the ras module + */ + if (!adev->debug_enable_ras_aca) + return 0; + if (!ras_mgr || !ras_mgr->ras_core) return -EINVAL; From 2e552735a5d59b76413a68b92a318c18abe9bf6b Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Thu, 25 Sep 2025 16:12:28 +0800 Subject: [PATCH 2301/2653] drm/amd/ras: Update ras command context structure name According to the actual usage of this structure, it is more appropriate to call it context, the structure name with ioctl is easy to cause misunderstanding. V2: Update commit message content. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c | 14 ++++++------- .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h | 2 +- drivers/gpu/drm/amd/ras/rascore/ras_cmd.c | 20 +++++++++---------- drivers/gpu/drm/amd/ras/rascore/ras_cmd.h | 8 ++++---- 4 files changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c index 4706e737969a1..6a281ad8e2556 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c @@ -37,7 +37,7 @@ #define AMDGPU_RAS_TYPE_VF 0x3 static int amdgpu_ras_query_interface_info(struct ras_core_context *ras_core, - struct ras_cmd_ioctl *cmd) + struct ras_cmd_ctx *cmd) { struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; struct ras_query_interface_info_rsp *output_data = @@ -77,7 +77,7 @@ static struct ras_core_context *ras_cmd_get_ras_core(uint64_t dev_handle) } static int amdgpu_ras_get_devices_info(struct ras_core_context *ras_core, - struct ras_cmd_ioctl *cmd) + struct ras_cmd_ctx *cmd) { struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; struct ras_cmd_devices_info_rsp *output_data = @@ -146,7 +146,7 @@ static uint64_t local_addr_to_xgmi_global_addr(struct ras_core_context *ras_core } static int amdgpu_ras_inject_error(struct ras_core_context *ras_core, - struct ras_cmd_ioctl *cmd, void *data) + struct ras_cmd_ctx *cmd, void *data) { struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; struct ras_cmd_inject_error_req *req = @@ -189,7 +189,7 @@ static int amdgpu_ras_inject_error(struct ras_core_context *ras_core, } static int amdgpu_ras_get_ras_safe_fb_addr_ranges(struct ras_core_context *ras_core, - struct ras_cmd_ioctl *cmd, void *data) + struct ras_cmd_ctx *cmd, void *data) { struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; struct ras_cmd_dev_handle *input_data = @@ -259,7 +259,7 @@ static int ras_translate_fb_address(struct ras_core_context *ras_core, } static int amdgpu_ras_translate_fb_address(struct ras_core_context *ras_core, - struct ras_cmd_ioctl *cmd, void *data) + struct ras_cmd_ctx *cmd, void *data) { struct ras_cmd_translate_fb_address_req *req_buff = (struct ras_cmd_translate_fb_address_req *)cmd->input_buff_raw; @@ -291,7 +291,7 @@ static struct ras_cmd_func_map amdgpu_ras_cmd_maps[] = { {RAS_CMD__TRANSLATE_FB_ADDRESS, amdgpu_ras_translate_fb_address}, }; -int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ioctl *cmd, void *data) +int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx *cmd, void *data) { struct ras_cmd_func_map *ras_cmd = NULL; int i, res; @@ -314,7 +314,7 @@ int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ioct int amdgpu_ras_cmd_ioctl_handler(struct ras_core_context *ras_core, uint8_t *cmd_buf, uint32_t buf_size) { - struct ras_cmd_ioctl *cmd = (struct ras_cmd_ioctl *)cmd_buf; + struct ras_cmd_ctx *cmd = (struct ras_cmd_ctx *)cmd_buf; struct ras_core_context *cmd_core = NULL; struct ras_cmd_dev_handle *cmd_handle = NULL; int timeout = 60; diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h index 7017198f1bac2..73832c28cb553 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h @@ -48,7 +48,7 @@ struct ras_cmd_translate_memory_fd_rsp { }; int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core, - struct ras_cmd_ioctl *cmd, void *data); + struct ras_cmd_ctx *cmd, void *data); int amdgpu_ras_cmd_ioctl_handler(struct ras_core_context *ras_core, uint8_t *cmd_buf, uint32_t buf_size); diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c index 6fe3b115986c5..94e6d7420d94e 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c @@ -43,7 +43,7 @@ static int ras_cmd_remove_device(struct ras_core_context *ras_core) } static int ras_get_block_ecc_info(struct ras_core_context *ras_core, - struct ras_cmd_ioctl *cmd, void *data) + struct ras_cmd_ctx *cmd, void *data) { struct ras_cmd_block_ecc_info_req *input_data = (struct ras_cmd_block_ecc_info_req *)cmd->input_buff_raw; @@ -119,7 +119,7 @@ static int ras_cmd_get_group_bad_pages(struct ras_core_context *ras_core, } static int ras_cmd_get_bad_pages(struct ras_core_context *ras_core, - struct ras_cmd_ioctl *cmd, void *data) + struct ras_cmd_ctx *cmd, void *data) { struct ras_cmd_bad_pages_info_req *input_data = (struct ras_cmd_bad_pages_info_req *)cmd->input_buff_raw; @@ -141,7 +141,7 @@ static int ras_cmd_get_bad_pages(struct ras_core_context *ras_core, } static int ras_cmd_clear_bad_page_info(struct ras_core_context *ras_core, - struct ras_cmd_ioctl *cmd, void *data) + struct ras_cmd_ctx *cmd, void *data) { if (cmd->input_size != sizeof(struct ras_cmd_dev_handle)) return RAS_CMD__ERROR_INVALID_INPUT_SIZE; @@ -156,7 +156,7 @@ static int ras_cmd_clear_bad_page_info(struct ras_core_context *ras_core, } static int ras_cmd_reset_all_error_counts(struct ras_core_context *ras_core, - struct ras_cmd_ioctl *cmd, void *data) + struct ras_cmd_ctx *cmd, void *data) { if (cmd->input_size != sizeof(struct ras_cmd_dev_handle)) return RAS_CMD__ERROR_INVALID_INPUT_SIZE; @@ -171,7 +171,7 @@ static int ras_cmd_reset_all_error_counts(struct ras_core_context *ras_core, } static int ras_cmd_get_cper_snapshot(struct ras_core_context *ras_core, - struct ras_cmd_ioctl *cmd, void *data) + struct ras_cmd_ctx *cmd, void *data) { struct ras_cmd_cper_snapshot_rsp *output_data = (struct ras_cmd_cper_snapshot_rsp *)cmd->output_buff_raw; @@ -193,7 +193,7 @@ static int ras_cmd_get_cper_snapshot(struct ras_core_context *ras_core, } static int ras_cmd_get_cper_records(struct ras_core_context *ras_core, - struct ras_cmd_ioctl *cmd, void *data) + struct ras_cmd_ctx *cmd, void *data) { struct ras_cmd_cper_record_req *req = (struct ras_cmd_cper_record_req *)cmd->input_buff_raw; @@ -253,7 +253,7 @@ static int ras_cmd_get_cper_records(struct ras_core_context *ras_core, } static int ras_cmd_get_batch_trace_snapshot(struct ras_core_context *ras_core, - struct ras_cmd_ioctl *cmd, void *data) + struct ras_cmd_ctx *cmd, void *data) { struct ras_cmd_batch_trace_snapshot_rsp *rsp = (struct ras_cmd_batch_trace_snapshot_rsp *)cmd->output_buff_raw; @@ -275,7 +275,7 @@ static int ras_cmd_get_batch_trace_snapshot(struct ras_core_context *ras_core, } static int ras_cmd_get_batch_trace_records(struct ras_core_context *ras_core, - struct ras_cmd_ioctl *cmd, void *data) + struct ras_cmd_ctx *cmd, void *data) { struct ras_cmd_batch_trace_record_req *input_data = (struct ras_cmd_batch_trace_record_req *)cmd->input_buff_raw; @@ -400,7 +400,7 @@ static enum ras_ta_error_type __get_ras_ta_err_type(enum ras_ecc_err_type error) } static int ras_cmd_inject_error(struct ras_core_context *ras_core, - struct ras_cmd_ioctl *cmd, void *data) + struct ras_cmd_ctx *cmd, void *data) { struct ras_cmd_inject_error_req *req = (struct ras_cmd_inject_error_req *)cmd->input_buff_raw; @@ -441,7 +441,7 @@ static struct ras_cmd_func_map ras_cmd_maps[] = { }; int rascore_handle_cmd(struct ras_core_context *ras_core, - struct ras_cmd_ioctl *cmd, void *data) + struct ras_cmd_ctx *cmd, void *data) { struct ras_cmd_func_map *ras_cmd = NULL; int i; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h index 6df8c70f5ad83..751ed50b9584b 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h @@ -101,7 +101,7 @@ enum ras_error_type { }; struct ras_core_context; -struct ras_cmd_ioctl; +struct ras_cmd_ctx; struct ras_cmd_mgr { struct list_head head; @@ -112,7 +112,7 @@ struct ras_cmd_mgr { struct ras_cmd_func_map { uint32_t cmd_id; int (*func)(struct ras_core_context *ras_core, - struct ras_cmd_ioctl *cmd, void *data); + struct ras_cmd_ctx *cmd, void *data); }; struct ras_device_bdf { @@ -133,7 +133,7 @@ struct ras_cmd_param { }; #pragma pack(push, 8) -struct ras_cmd_ioctl { +struct ras_cmd_ctx { uint32_t magic; union { struct { @@ -414,7 +414,7 @@ struct ras_cmd_batch_trace_record_rsp { int ras_cmd_init(struct ras_core_context *ras_core); int ras_cmd_fini(struct ras_core_context *ras_core); -int rascore_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ioctl *cmd, void *data); +int rascore_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx *cmd, void *data); uint64_t ras_cmd_get_dev_handle(struct ras_core_context *ras_core); int ras_cmd_query_interface_info(struct ras_core_context *ras_core, struct ras_query_interface_info_rsp *rsp); From a2db5462fc54d52bc998ffa9d8c1126300cd7516 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Fri, 17 Oct 2025 15:27:56 +0800 Subject: [PATCH 2302/2653] drm/amd/ras: Update function and remove redundant code Update function and remove redundant code: 1. Update function to prepare for internal use. 2. Remove unused function code previously prepared for ioctl. V2: Update commit message content. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c | 110 +++--------------- .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h | 3 +- .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 31 +++++ .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h | 3 + drivers/gpu/drm/amd/ras/rascore/ras_cmd.h | 3 +- drivers/gpu/drm/amd/ras/rascore/ras_core.c | 3 +- drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c | 29 ----- 7 files changed, 55 insertions(+), 127 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c index 6a281ad8e2556..78419b7f7729a 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c @@ -36,67 +36,6 @@ #define AMDGPU_RAS_TYPE_AMDGPU 0x2 #define AMDGPU_RAS_TYPE_VF 0x3 -static int amdgpu_ras_query_interface_info(struct ras_core_context *ras_core, - struct ras_cmd_ctx *cmd) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; - struct ras_query_interface_info_rsp *output_data = - (struct ras_query_interface_info_rsp *)cmd->output_buff_raw; - int ret; - - if (cmd->input_size != sizeof(struct ras_query_interface_info_req)) - return RAS_CMD__ERROR_INVALID_INPUT_SIZE; - - ret = ras_cmd_query_interface_info(ras_core, output_data); - if (!ret) { - output_data->plat_major_ver = 0; - output_data->plat_minor_ver = 0; - - output_data->interface_type = amdgpu_sriov_vf(adev) ? - RAS_CMD_INTERFACE_TYPE_VF : RAS_CMD_INTERFACE_TYPE_AMDGPU; - - cmd->output_size = sizeof(struct ras_query_interface_info_rsp); - } - - return ret; -} - -static struct ras_core_context *ras_cmd_get_ras_core(uint64_t dev_handle) -{ - struct ras_core_context *ras_core; - - if (!dev_handle || (dev_handle == RAS_CMD_DEV_HANDLE_MAGIC)) - return NULL; - - ras_core = (struct ras_core_context *)(uintptr_t)(dev_handle ^ RAS_CMD_DEV_HANDLE_MAGIC); - - if (ras_cmd_get_dev_handle(ras_core) == dev_handle) - return ras_core; - - return NULL; -} - -static int amdgpu_ras_get_devices_info(struct ras_core_context *ras_core, - struct ras_cmd_ctx *cmd) -{ - struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; - struct ras_cmd_devices_info_rsp *output_data = - (struct ras_cmd_devices_info_rsp *)cmd->output_buff_raw; - struct ras_cmd_dev_info *dev_info; - - dev_info = &output_data->devs[0]; - dev_info->dev_handle = ras_cmd_get_dev_handle(ras_core); - dev_info->oam_id = adev->smuio.funcs->get_socket_id(adev); - dev_info->ecc_enabled = 1; - dev_info->ecc_supported = 1; - - output_data->dev_num = 1; - output_data->version = 0; - cmd->output_size = sizeof(struct ras_cmd_devices_info_rsp); - - return 0; -} - static int amdgpu_ras_trigger_error_prepare(struct ras_core_context *ras_core, struct ras_cmd_inject_error_req *block_info) { @@ -311,51 +250,34 @@ int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx return res; } -int amdgpu_ras_cmd_ioctl_handler(struct ras_core_context *ras_core, - uint8_t *cmd_buf, uint32_t buf_size) +int amdgpu_ras_submit_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx *cmd) { - struct ras_cmd_ctx *cmd = (struct ras_cmd_ctx *)cmd_buf; - struct ras_core_context *cmd_core = NULL; - struct ras_cmd_dev_handle *cmd_handle = NULL; + struct ras_core_context *cmd_core = ras_core; int timeout = 60; int res; cmd->cmd_res = RAS_CMD__ERROR_INVALID_CMD; cmd->output_size = 0; - if (!ras_core_is_enabled(ras_core)) + if (!ras_core_is_enabled(cmd_core)) return RAS_CMD__ERROR_ACCESS_DENIED; - if (cmd->cmd_id == RAS_CMD__QUERY_INTERFACE_INFO) { - cmd->cmd_res = amdgpu_ras_query_interface_info(ras_core, cmd); - } else if (cmd->cmd_id == RAS_CMD__GET_DEVICES_INFO) { - cmd->cmd_res = amdgpu_ras_get_devices_info(ras_core, cmd); - } else { - cmd_handle = (struct ras_cmd_dev_handle *)cmd->input_buff_raw; - cmd_core = ras_cmd_get_ras_core(cmd_handle->dev_handle); - if (!cmd_core) - return RAS_CMD__ERROR_INVALID_INPUT_DATA; - - while (ras_core_gpu_in_reset(cmd_core)) { - msleep(1000); - if (!timeout--) - return RAS_CMD__ERROR_TIMEOUT; - } - - - if (!ras_core_is_enabled(cmd_core)) - return RAS_CMD__ERROR_ACCESS_DENIED; + while (ras_core_gpu_in_reset(cmd_core)) { + msleep(1000); + if (!timeout--) + return RAS_CMD__ERROR_TIMEOUT; + } - res = amdgpu_ras_handle_cmd(cmd_core, cmd, NULL); - if (res == RAS_CMD__ERROR_UKNOWN_CMD) - res = rascore_handle_cmd(cmd_core, cmd, NULL); + res = amdgpu_ras_handle_cmd(cmd_core, cmd, NULL); + if (res == RAS_CMD__ERROR_UKNOWN_CMD) + res = rascore_handle_cmd(cmd_core, cmd, NULL); - cmd->cmd_res = res; - } + cmd->cmd_res = res; - if ((cmd->cmd_res == RAS_CMD__SUCCESS) && - ((cmd->output_size + sizeof(*cmd)) > buf_size)) { - RAS_INFO("Insufficient command buffer size 0x%x!\n", buf_size); + if (cmd->output_size > cmd->output_buf_size) { + RAS_DEV_ERR(cmd_core->dev, + "Output size 0x%x exceeds output buffer size 0x%x!\n", + cmd->output_size, cmd->output_buf_size); return RAS_CMD__SUCCESS_EXEED_BUFFER; } diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h index 73832c28cb553..5973b156cc856 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h @@ -49,7 +49,6 @@ struct ras_cmd_translate_memory_fd_rsp { int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx *cmd, void *data); -int amdgpu_ras_cmd_ioctl_handler(struct ras_core_context *ras_core, - uint8_t *cmd_buf, uint32_t buf_size); +int amdgpu_ras_submit_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx *cmd); #endif diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c index 13c207c8a8430..8007e49951d81 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -578,3 +578,34 @@ bool amdgpu_ras_mgr_is_rma(struct amdgpu_device *adev) return ras_core_gpu_is_rma(ras_mgr->ras_core); } + +int amdgpu_ras_mgr_handle_ras_cmd(struct amdgpu_device *adev, + uint32_t cmd_id, void *input, uint32_t input_size, + void *output, uint32_t out_size) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + struct ras_cmd_ctx *cmd_ctx; + uint32_t ctx_buf_size = PAGE_SIZE; + int ret; + + if (!amdgpu_ras_mgr_is_ready(adev)) + return -EPERM; + + cmd_ctx = kzalloc(ctx_buf_size, GFP_KERNEL); + if (!cmd_ctx) + return -ENOMEM; + + cmd_ctx->cmd_id = cmd_id; + + memcpy(cmd_ctx->input_buff_raw, input, input_size); + cmd_ctx->input_size = input_size; + cmd_ctx->output_buf_size = ctx_buf_size - sizeof(*cmd_ctx); + + ret = amdgpu_ras_submit_cmd(ras_mgr->ras_core, cmd_ctx); + if (!ret && !cmd_ctx->cmd_res && output && (out_size == cmd_ctx->output_size)) + memcpy(output, cmd_ctx->output_buff_raw, cmd_ctx->output_size); + + kfree(cmd_ctx); + + return ret; +} diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h index 814b65ef1c62e..42f190a8feb94 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h @@ -72,4 +72,7 @@ int amdgpu_ras_mgr_get_curr_nps_mode(struct amdgpu_device *adev, uint32_t *nps_m bool amdgpu_ras_mgr_check_retired_addr(struct amdgpu_device *adev, uint64_t addr); bool amdgpu_ras_mgr_is_rma(struct amdgpu_device *adev); +int amdgpu_ras_mgr_handle_ras_cmd(struct amdgpu_device *adev, + uint32_t cmd_id, void *input, uint32_t input_size, + void *output, uint32_t out_size); #endif diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h index 751ed50b9584b..48a0715eb8218 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h @@ -153,7 +153,8 @@ struct ras_cmd_ctx { uint32_t cmd_res; uint32_t input_size; uint32_t output_size; - uint32_t reserved[6]; + uint32_t output_buf_size; + uint32_t reserved[5]; uint8_t input_buff_raw[RAS_CMD_MAX_IN_SIZE]; uint8_t output_buff_raw[]; }; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c index 45fc0608043f8..01122b55c98ab 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c @@ -62,7 +62,8 @@ int ras_core_convert_timestamp_to_time(struct ras_core_context *ras_core, uint64_t timestamp, struct ras_time *tm) { int days_in_month[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; - uint64_t year = 0, month = 0, day = 0, hour = 0, minute = 0, second = 0; + uint64_t month = 0, day = 0, hour = 0, minute = 0, second = 0; + uint32_t year = 0; int seconds_per_day = 24 * 60 * 60; int seconds_per_hour = 60 * 60; int seconds_per_minute = 60; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c index 9e0a4f605db06..cd6b057bdaf3b 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c @@ -199,17 +199,6 @@ static int __ras_eeprom_xfer(struct ras_core_context *ras_core, u32 eeprom_addr, return -EINVAL; } - -/** - * __eeprom_xfer -- Read/write from/to an I2C EEPROM device - * @i2c_adap: pointer to the I2C adapter to use - * @eeprom_addr: EEPROM address from which to read/write - * @eeprom_buf: pointer to data buffer to read into/write from - * @buf_size: the size of @eeprom_buf - * @read: True if reading from the EEPROM, false if writing - * - * Returns the number of bytes read/written; -errno on error. - */ static int __eeprom_xfer(struct ras_core_context *ras_core, u32 eeprom_addr, u8 *eeprom_buf, u32 buf_size, bool read) { @@ -454,13 +443,6 @@ static void ras_set_eeprom_table_version(struct ras_eeprom_control *control) hdr->version = RAS_TABLE_VER_V3; } -/** - * ras_eeprom_reset_table -- Reset the RAS EEPROM table - * @control: pointer to control structure - * - * Reset the contents of the header of the RAS EEPROM table. - * Return 0 on success, -errno on error. - */ int ras_eeprom_reset_table(struct ras_core_context *ras_core) { struct ras_eeprom_control *control = &ras_core->ras_eeprom; @@ -928,17 +910,6 @@ static int __ras_eeprom_read(struct ras_eeprom_control *control, return res; } -/** - * ras_eeprom_read -- read EEPROM - * @control: pointer to control structure - * @record: array of records to read into - * @num: number of records in @record - * - * Reads num records from the RAS table in EEPROM and - * writes the data into @record array. - * - * Returns 0 on success, -errno on error. - */ int ras_eeprom_read(struct ras_core_context *ras_core, struct eeprom_umc_record *record, const u32 num) { From 3d10f8684c03aca9fa42fac5b5958b657c20f90f Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Tue, 14 Oct 2025 15:30:58 +0800 Subject: [PATCH 2303/2653] drm/amdgpu: ras module supports error injection ras module supports error injection. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 0a1d5bba15f37..80e2279a55a99 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1597,6 +1597,27 @@ int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, return 0; } +static int amdgpu_uniras_error_inject(struct amdgpu_device *adev, + struct ras_inject_if *info) +{ + struct ras_cmd_inject_error_req inject_req; + struct ras_cmd_inject_error_rsp rsp; + + if (!info) + return -EINVAL; + + memset(&inject_req, 0, sizeof(inject_req)); + inject_req.block_id = info->head.block; + inject_req.subblock_id = info->head.sub_block_index; + inject_req.address = info->address; + inject_req.error_type = info->head.type; + inject_req.instance_mask = info->instance_mask; + inject_req.value = info->value; + + return amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__INJECT_ERROR, + &inject_req, sizeof(inject_req), &rsp, sizeof(rsp)); +} + /* wrapper of psp_ras_trigger_error */ int amdgpu_ras_error_inject(struct amdgpu_device *adev, struct ras_inject_if *info) @@ -1614,6 +1635,9 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev, info->head.block, info->head.sub_block_index); + if (amdgpu_uniras_enabled(adev)) + return amdgpu_uniras_error_inject(adev, info); + /* inject on guest isn't allowed, return success directly */ if (amdgpu_sriov_vf(adev)) return 0; From be09d48d0677b2d732d5c179225c791b693f1582 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Sat, 11 Oct 2025 10:49:55 +0800 Subject: [PATCH 2304/2653] drm/amdgpu: query bad page info of ras module Query bad page info of ras module. V2: Update code to reuse bad page output code. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 142 ++++++++++++++++-------- 1 file changed, 98 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 80e2279a55a99..9df0914de8430 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1782,7 +1782,9 @@ int amdgpu_ras_query_error_count(struct amdgpu_device *adev, /* sysfs begin */ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, - struct ras_badpage **bps, unsigned int *count); + struct ras_badpage *bps, uint32_t count, uint32_t start); +static int amdgpu_uniras_badpages_read(struct amdgpu_device *adev, + struct ras_badpage *bps, uint32_t count, uint32_t start); static char *amdgpu_ras_badpage_flags_str(unsigned int flags) { @@ -1844,19 +1846,50 @@ static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, unsigned int end = div64_ul(ppos + count - 1, element_size); ssize_t s = 0; struct ras_badpage *bps = NULL; - unsigned int bps_count = 0; + int bps_count = 0, i, status; + uint64_t address; memset(buf, 0, count); - if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) + bps_count = end - start; + bps = kmalloc_array(bps_count, sizeof(*bps), GFP_KERNEL); + if (!bps) + return 0; + + memset(bps, 0, sizeof(*bps) * bps_count); + + if (amdgpu_uniras_enabled(adev)) + bps_count = amdgpu_uniras_badpages_read(adev, bps, bps_count, start); + else + bps_count = amdgpu_ras_badpages_read(adev, bps, bps_count, start); + + if (bps_count <= 0) { + kfree(bps); return 0; + } + + for (i = 0; i < bps_count; i++) { + address = ((uint64_t)bps[i].bp) << AMDGPU_GPU_PAGE_SHIFT; + if (amdgpu_ras_check_critical_address(adev, address)) + continue; + + bps[i].size = AMDGPU_GPU_PAGE_SIZE; + + status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr, + address); + if (status == -EBUSY) + bps[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; + else if (status == -ENOENT) + bps[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; + else + bps[i].flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED; - for (; start < end && start < bps_count; start++) s += scnprintf(&buf[s], element_size + 1, "0x%08x : 0x%08x : %1s\n", - bps[start].bp, - bps[start].size, - amdgpu_ras_badpage_flags_str(bps[start].flags)); + bps[i].bp, + bps[i].size, + amdgpu_ras_badpage_flags_str(bps[i].flags)); + } kfree(bps); @@ -2659,62 +2692,83 @@ static void amdgpu_ras_query_err_status(struct amdgpu_device *adev) } } -/* recovery begin */ - -/* return 0 on success. - * caller need free bps. - */ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, - struct ras_badpage **bps, unsigned int *count) + struct ras_badpage *bps, uint32_t count, uint32_t start) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct ras_err_handler_data *data; - int i = 0; - int ret = 0, status; + int r = 0; + uint32_t i; if (!con || !con->eh_data || !bps || !count) return -EINVAL; mutex_lock(&con->recovery_lock); data = con->eh_data; - if (!data || data->count == 0) { - *bps = NULL; - ret = -EINVAL; - goto out; + if (start < data->count) { + for (i = start; i < data->count; i++) { + if (!data->bps[i].ts) + continue; + + bps[r].bp = data->bps[i].retired_page; + r++; + if (r >= count) + break; + } } + mutex_unlock(&con->recovery_lock); - *bps = kmalloc_array(data->count, sizeof(struct ras_badpage), GFP_KERNEL); - if (!*bps) { - ret = -ENOMEM; - goto out; - } + return r; +} - for (; i < data->count; i++) { - if (!data->bps[i].ts) - continue; +static int amdgpu_uniras_badpages_read(struct amdgpu_device *adev, + struct ras_badpage *bps, uint32_t count, uint32_t start) +{ + struct ras_cmd_bad_pages_info_req cmd_input; + struct ras_cmd_bad_pages_info_rsp *output; + uint32_t group, start_group, end_group; + uint32_t pos, pos_in_group; + int r = 0, i; - (*bps)[i] = (struct ras_badpage){ - .bp = data->bps[i].retired_page, - .size = AMDGPU_GPU_PAGE_SIZE, - .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, - }; + if (!bps || !count) + return -EINVAL; - if (amdgpu_ras_check_critical_address(adev, - data->bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT)) - continue; + output = kmalloc(sizeof(*output), GFP_KERNEL); + if (!output) + return -ENOMEM; - status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr, - data->bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT); - if (status == -EBUSY) - (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; - else if (status == -ENOENT) - (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; + memset(&cmd_input, 0, sizeof(cmd_input)); + + start_group = start / RAS_CMD_MAX_BAD_PAGES_PER_GROUP; + end_group = (start + count + RAS_CMD_MAX_BAD_PAGES_PER_GROUP - 1) / + RAS_CMD_MAX_BAD_PAGES_PER_GROUP; + + pos = start; + for (group = start_group; group < end_group; group++) { + memset(output, 0, sizeof(*output)); + cmd_input.group_index = group; + if (amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__GET_BAD_PAGES, + &cmd_input, sizeof(cmd_input), output, sizeof(*output))) + goto out; + + if (pos >= output->bp_total_cnt) + goto out; + + pos_in_group = pos - group * RAS_CMD_MAX_BAD_PAGES_PER_GROUP; + for (i = pos_in_group; i < output->bp_in_group; i++, pos++) { + if (!output->records[i].ts) + continue; + + bps[r].bp = output->records[i].retired_page; + r++; + if (r >= count) + goto out; + } } - *count = con->bad_page_num; out: - mutex_unlock(&con->recovery_lock); - return ret; + kfree(output); + return r; } static void amdgpu_ras_set_fed_all(struct amdgpu_device *adev, From 371b6b54143860462387a7e1947079569f8d9644 Mon Sep 17 00:00:00 2001 From: Ellen Pan Date: Mon, 6 Oct 2025 15:47:45 -0500 Subject: [PATCH 2305/2653] drm/amdgpu: Updated naming of SRIOV critical region offsets/sizes with _V1 suffix - This change prepares the later patches to intro _v2 suffix to SRIOV critical regions Signed-off-by: Ellen Pan Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 20 ++++----- drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 50 +++++++++++++++------ 2 files changed, 46 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index f96beb96c75cc..8cd02eb605c54 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -686,7 +686,7 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) /* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/ adev->virt.fw_reserve.p_pf2vf = (struct amd_sriov_msg_pf2vf_info_header *) - (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); + (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10)); amdgpu_virt_read_pf2vf_data(adev); } @@ -703,21 +703,21 @@ void amdgpu_virt_exchange_data(struct amdgpu_device *adev) if (adev->mman.fw_vram_usage_va) { adev->virt.fw_reserve.p_pf2vf = (struct amd_sriov_msg_pf2vf_info_header *) - (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); + (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10)); adev->virt.fw_reserve.p_vf2pf = (struct amd_sriov_msg_vf2pf_info_header *) - (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); + (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 << 10)); adev->virt.fw_reserve.ras_telemetry = - (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB << 10)); + (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 << 10)); } else if (adev->mman.drv_vram_usage_va) { adev->virt.fw_reserve.p_pf2vf = (struct amd_sriov_msg_pf2vf_info_header *) - (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); + (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10)); adev->virt.fw_reserve.p_vf2pf = (struct amd_sriov_msg_vf2pf_info_header *) - (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); + (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 << 10)); adev->virt.fw_reserve.ras_telemetry = - (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB << 10)); + (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 << 10)); } amdgpu_virt_read_pf2vf_data(adev); @@ -1304,7 +1304,7 @@ static int amdgpu_virt_cache_host_error_counts(struct amdgpu_device *adev, checksum = host_telemetry->header.checksum; used_size = host_telemetry->header.used_size; - if (used_size > (AMD_SRIOV_RAS_TELEMETRY_SIZE_KB << 10)) + if (used_size > (AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1 << 10)) return 0; tmp = kmemdup(&host_telemetry->body.error_count, used_size, GFP_KERNEL); @@ -1383,7 +1383,7 @@ amdgpu_virt_write_cpers_to_ring(struct amdgpu_device *adev, checksum = host_telemetry->header.checksum; used_size = host_telemetry->header.used_size; - if (used_size > (AMD_SRIOV_RAS_TELEMETRY_SIZE_KB << 10)) + if (used_size > (AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1 << 10)) return -EINVAL; cper_dump = kmemdup(&host_telemetry->body.cper_dump, used_size, GFP_KERNEL); @@ -1515,7 +1515,7 @@ static int amdgpu_virt_cache_chk_criti_hit(struct amdgpu_device *adev, checksum = host_telemetry->header.checksum; used_size = host_telemetry->header.used_size; - if (used_size > (AMD_SRIOV_RAS_TELEMETRY_SIZE_KB << 10)) + if (used_size > (AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1 << 10)) return 0; tmp = kmemdup(&host_telemetry->body.chk_criti, used_size, GFP_KERNEL); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h index 3a79ed7d8031e..7509756b9ac5a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h @@ -23,26 +23,48 @@ #ifndef AMDGV_SRIOV_MSG__H_ #define AMDGV_SRIOV_MSG__H_ -/* unit in kilobytes */ -#define AMD_SRIOV_MSG_VBIOS_OFFSET 0 -#define AMD_SRIOV_MSG_VBIOS_SIZE_KB 64 -#define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB AMD_SRIOV_MSG_VBIOS_SIZE_KB -#define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB 4 -#define AMD_SRIOV_MSG_TMR_OFFSET_KB 2048 -#define AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB 2 -#define AMD_SRIOV_RAS_TELEMETRY_SIZE_KB 64 +#define AMD_SRIOV_MSG_SIZE_KB 1 + /* - * layout + * layout v1 * 0 64KB 65KB 66KB 68KB 132KB * | VBIOS | PF2VF | VF2PF | Bad Page | RAS Telemetry Region | ... * | 64KB | 1KB | 1KB | 2KB | 64KB | ... */ -#define AMD_SRIOV_MSG_SIZE_KB 1 -#define AMD_SRIOV_MSG_PF2VF_OFFSET_KB AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB -#define AMD_SRIOV_MSG_VF2PF_OFFSET_KB (AMD_SRIOV_MSG_PF2VF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB) -#define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB (AMD_SRIOV_MSG_VF2PF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB) -#define AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB (AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB + AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB) +/* + * layout v2 (offsets are dynamically allocated and the offsets below are examples) + * 0 1KB 64KB 65KB 66KB 68KB 132KB + * | INITD_H | VBIOS | PF2VF | VF2PF | Bad Page | RAS Telemetry Region | ... + * | 1KB | 64KB | 1KB | 1KB | 2KB | 64KB | ... + * + * Note: PF2VF + VF2PF + Bad Page = DataExchange region (allocated contiguously) + */ + +/* v1 layout sizes */ +#define AMD_SRIOV_MSG_VBIOS_SIZE_KB_V1 64 +#define AMD_SRIOV_MSG_PF2VF_SIZE_KB_V1 1 +#define AMD_SRIOV_MSG_VF2PF_SIZE_KB_V1 1 +#define AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB_V1 2 +#define AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1 64 +#define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB_V1 \ + (AMD_SRIOV_MSG_PF2VF_SIZE_KB_V1 + AMD_SRIOV_MSG_VF2PF_SIZE_KB_V1 + \ + AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB_V1) + +/* v1 offsets */ +#define AMD_SRIOV_MSG_VBIOS_OFFSET_V1 0 +#define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB_V1 AMD_SRIOV_MSG_VBIOS_SIZE_KB_V1 +#define AMD_SRIOV_MSG_TMR_OFFSET_KB 2048 +#define AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB_V1 +#define AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 \ + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 + AMD_SRIOV_MSG_SIZE_KB) +#define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB_V1 \ + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 + AMD_SRIOV_MSG_SIZE_KB) +#define AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 \ + (AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB_V1 + AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB_V1) +#define AMD_SRIOV_MSG_INIT_DATA_TOT_SIZE_KB_V1 \ + (AMD_SRIOV_MSG_VBIOS_SIZE_KB_V1 + AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB_V1 + \ + AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1) /* * PF2VF history log: From 1f9d1b7a9164658bb2d643e570809c2e5e379e6e Mon Sep 17 00:00:00 2001 From: Ellen Pan Date: Tue, 7 Oct 2025 09:46:16 -0500 Subject: [PATCH 2306/2653] drm/amdgpu: Add SRIOV crit_region_version support 1. Added enum amd_sriov_crit_region_version to support multi versions 2. Added logic in SRIOV mailbox to regonize crit_region version during req_gpu_init_data Signed-off-by: Ellen Pan Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 8 +++++++ drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 5 +++++ drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 23 ++++++++++++++------- 4 files changed, 32 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 8cd02eb605c54..56573fb27f633 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -150,9 +150,10 @@ void amdgpu_virt_request_init_data(struct amdgpu_device *adev) virt->ops->req_init_data(adev); if (adev->virt.req_init_data_ver > 0) - DRM_INFO("host supports REQ_INIT_DATA handshake\n"); + dev_info(adev->dev, "host supports REQ_INIT_DATA handshake of critical_region_version %d\n", + adev->virt.req_init_data_ver); else - DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n"); + dev_warn(adev->dev, "host doesn't support REQ_INIT_DATA handshake\n"); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index d1172c8e58c47..36247a160aa63 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -262,6 +262,11 @@ struct amdgpu_virt_ras { DECLARE_ATTR_CAP_CLASS(amdgpu_virt, AMDGPU_VIRT_CAPS_LIST); +struct amdgpu_virt_region { + uint32_t offset; + uint32_t size_kb; +}; + /* GPU virtualization */ struct amdgpu_virt { uint32_t caps; @@ -289,6 +294,9 @@ struct amdgpu_virt { bool ras_init_done; uint32_t reg_access; + /* dynamic(v2) critical regions */ + struct amdgpu_virt_region init_data_header; + /* vf2pf message */ struct delayed_work vf2pf_work; uint32_t vf2pf_update_interval_ms; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h index 7509756b9ac5a..9228fd2c6dfd9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h @@ -66,6 +66,11 @@ (AMD_SRIOV_MSG_VBIOS_SIZE_KB_V1 + AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB_V1 + \ AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1) +enum amd_sriov_crit_region_version { + GPU_CRIT_REGION_V1 = 1, + GPU_CRIT_REGION_V2 = 2, +}; + /* * PF2VF history log: * v1 defined in amdgim diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c index e5282a5d05d95..cd5b2f07edb89 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c @@ -222,12 +222,20 @@ static int xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev, adev->virt.req_init_data_ver = 0; } else { if (req == IDH_REQ_GPU_INIT_DATA) { - adev->virt.req_init_data_ver = - RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW1); - - /* assume V1 in case host doesn't set version number */ - if (adev->virt.req_init_data_ver < 1) - adev->virt.req_init_data_ver = 1; + switch (RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW1)) { + case GPU_CRIT_REGION_V2: + adev->virt.req_init_data_ver = GPU_CRIT_REGION_V2; + adev->virt.init_data_header.offset = + RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW2); + adev->virt.init_data_header.size_kb = + RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW3); + break; + default: + adev->virt.req_init_data_ver = GPU_CRIT_REGION_V1; + adev->virt.init_data_header.offset = -1; + adev->virt.init_data_header.size_kb = 0; + break; + } } } @@ -285,7 +293,8 @@ static int xgpu_nv_release_full_gpu_access(struct amdgpu_device *adev, static int xgpu_nv_request_init_data(struct amdgpu_device *adev) { - return xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_INIT_DATA); + return xgpu_nv_send_access_requests_with_param(adev, IDH_REQ_GPU_INIT_DATA, + 0, GPU_CRIT_REGION_V2, 0); } static int xgpu_nv_mailbox_ack_irq(struct amdgpu_device *adev, From 43b4004088942aabe87b1e4fbb90dceecb5f9056 Mon Sep 17 00:00:00 2001 From: Ellen Pan Date: Tue, 7 Oct 2025 11:00:16 -0500 Subject: [PATCH 2307/2653] drm/amdgpu: Introduce SRIOV critical regions v2 during VF init 1. Introduced amdgpu_virt_init_critical_region during VF init. - VFs use init_data_header_offset and init_data_header_size_kb transmitted via PF2VF mailbox to fetch the offset of critical regions' offsets/sizes in VRAM and save to adev->virt.crit_region_offsets and adev->virt.crit_region_sizes_kb. Signed-off-by: Ellen Pan Reviewed-by: Alex Deucher Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 174 ++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 11 ++ drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 31 ++++ 4 files changed, 220 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2088069a1fa9b..882fff5a7598d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2807,6 +2807,10 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) r = amdgpu_virt_request_full_gpu(adev, true); if (r) return r; + + r = amdgpu_virt_init_critical_region(adev); + if (r) + return r; } switch (adev->asic_type) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 56573fb27f633..1779b1ac30d22 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -44,6 +44,18 @@ vf2pf_info->ucode_info[ucode].version = ver; \ } while (0) +#define mmRCC_CONFIG_MEMSIZE 0xde3 + +const char *amdgpu_virt_dynamic_crit_table_name[] = { + "IP DISCOVERY", + "VBIOS IMG", + "RAS TELEMETRY", + "DATA EXCHANGE", + "BAD PAGE INFO", + "INIT HEADER", + "LAST", +}; + bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) { /* By now all MMIO pages except mailbox are blocked */ @@ -843,6 +855,168 @@ static void amdgpu_virt_init_ras(struct amdgpu_device *adev) adev->virt.ras.cper_rptr = 0; } +static uint8_t amdgpu_virt_crit_region_calc_checksum(uint8_t *buf_start, uint8_t *buf_end) +{ + uint32_t sum = 0; + + if (buf_start >= buf_end) + return 0; + + for (; buf_start < buf_end; buf_start++) + sum += buf_start[0]; + + return 0xffffffff - sum; +} + +int amdgpu_virt_init_critical_region(struct amdgpu_device *adev) +{ + struct amd_sriov_msg_init_data_header *init_data_hdr = NULL; + uint32_t init_hdr_offset = adev->virt.init_data_header.offset; + uint32_t init_hdr_size = adev->virt.init_data_header.size_kb << 10; + uint64_t vram_size; + int r = 0; + uint8_t checksum = 0; + + /* Skip below init if critical region version != v2 */ + if (adev->virt.req_init_data_ver != GPU_CRIT_REGION_V2) + return 0; + + if (init_hdr_offset < 0) { + dev_err(adev->dev, "Invalid init header offset\n"); + return -EINVAL; + } + + vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); + if (!vram_size || vram_size == U32_MAX) + return -EINVAL; + vram_size <<= 20; + + if ((init_hdr_offset + init_hdr_size) > vram_size) { + dev_err(adev->dev, "init_data_header exceeds VRAM size, exiting\n"); + return -EINVAL; + } + + /* Allocate for init_data_hdr */ + init_data_hdr = kzalloc(sizeof(struct amd_sriov_msg_init_data_header), GFP_KERNEL); + if (!init_data_hdr) + return -ENOMEM; + + amdgpu_device_vram_access(adev, (uint64_t)init_hdr_offset, (uint32_t *)init_data_hdr, + sizeof(struct amd_sriov_msg_init_data_header), false); + + /* Table validation */ + if (strncmp(init_data_hdr->signature, + AMDGPU_SRIOV_CRIT_DATA_SIGNATURE, + AMDGPU_SRIOV_CRIT_DATA_SIG_LEN) != 0) { + dev_err(adev->dev, "Invalid init data signature: %.4s\n", + init_data_hdr->signature); + r = -EINVAL; + goto out; + } + + checksum = amdgpu_virt_crit_region_calc_checksum( + (uint8_t *)&init_data_hdr->initdata_offset, + (uint8_t *)init_data_hdr + + sizeof(struct amd_sriov_msg_init_data_header)); + if (checksum != init_data_hdr->checksum) { + dev_err(adev->dev, "Found unmatching checksum from calculation 0x%x and init_data 0x%x\n", + checksum, init_data_hdr->checksum); + r = -EINVAL; + goto out; + } + + memset(&adev->virt.crit_regn, 0, sizeof(adev->virt.crit_regn)); + memset(adev->virt.crit_regn_tbl, 0, sizeof(adev->virt.crit_regn_tbl)); + + adev->virt.crit_regn.offset = init_data_hdr->initdata_offset; + adev->virt.crit_regn.size_kb = init_data_hdr->initdata_size_in_kb; + + /* Validation and initialization for each table entry */ + if (IS_SRIOV_CRIT_REGN_ENTRY_VALID(init_data_hdr, AMD_SRIOV_MSG_IPD_TABLE_ID)) { + if (!init_data_hdr->ip_discovery_size_in_kb || + init_data_hdr->ip_discovery_size_in_kb > DISCOVERY_TMR_SIZE) { + dev_err(adev->dev, "Invalid %s size: 0x%x\n", + amdgpu_virt_dynamic_crit_table_name[AMD_SRIOV_MSG_IPD_TABLE_ID], + init_data_hdr->ip_discovery_size_in_kb); + r = -EINVAL; + goto out; + } + + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset = + init_data_hdr->ip_discovery_offset; + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb = + init_data_hdr->ip_discovery_size_in_kb; + } + + if (IS_SRIOV_CRIT_REGN_ENTRY_VALID(init_data_hdr, AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID)) { + if (!init_data_hdr->vbios_img_size_in_kb) { + dev_err(adev->dev, "Invalid %s size: 0x%x\n", + amdgpu_virt_dynamic_crit_table_name[AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID], + init_data_hdr->vbios_img_size_in_kb); + r = -EINVAL; + goto out; + } + + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID].offset = + init_data_hdr->vbios_img_offset; + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID].size_kb = + init_data_hdr->vbios_img_size_in_kb; + } + + if (IS_SRIOV_CRIT_REGN_ENTRY_VALID(init_data_hdr, AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID)) { + if (!init_data_hdr->ras_tele_info_size_in_kb) { + dev_err(adev->dev, "Invalid %s size: 0x%x\n", + amdgpu_virt_dynamic_crit_table_name[AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID], + init_data_hdr->ras_tele_info_size_in_kb); + r = -EINVAL; + goto out; + } + + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID].offset = + init_data_hdr->ras_tele_info_offset; + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID].size_kb = + init_data_hdr->ras_tele_info_size_in_kb; + } + + if (IS_SRIOV_CRIT_REGN_ENTRY_VALID(init_data_hdr, AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID)) { + if (!init_data_hdr->dataexchange_size_in_kb) { + dev_err(adev->dev, "Invalid %s size: 0x%x\n", + amdgpu_virt_dynamic_crit_table_name[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID], + init_data_hdr->dataexchange_size_in_kb); + r = -EINVAL; + goto out; + } + + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].offset = + init_data_hdr->dataexchange_offset; + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].size_kb = + init_data_hdr->dataexchange_size_in_kb; + } + + if (IS_SRIOV_CRIT_REGN_ENTRY_VALID(init_data_hdr, AMD_SRIOV_MSG_BAD_PAGE_INFO_TABLE_ID)) { + if (!init_data_hdr->bad_page_size_in_kb) { + dev_err(adev->dev, "Invalid %s size: 0x%x\n", + amdgpu_virt_dynamic_crit_table_name[AMD_SRIOV_MSG_BAD_PAGE_INFO_TABLE_ID], + init_data_hdr->bad_page_size_in_kb); + r = -EINVAL; + goto out; + } + + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_BAD_PAGE_INFO_TABLE_ID].offset = + init_data_hdr->bad_page_info_offset; + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_BAD_PAGE_INFO_TABLE_ID].size_kb = + init_data_hdr->bad_page_size_in_kb; + } + + adev->virt.is_dynamic_crit_regn_enabled = true; + +out: + kfree(init_data_hdr); + init_data_hdr = NULL; + + return r; +} + void amdgpu_virt_init(struct amdgpu_device *adev) { bool is_sriov = false; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 36247a160aa63..8d03a8620de9a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -54,6 +54,12 @@ #define AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT 2 +/* Signature used to validate the SR-IOV dynamic critical region init data header ("INDA") */ +#define AMDGPU_SRIOV_CRIT_DATA_SIGNATURE "INDA" +#define AMDGPU_SRIOV_CRIT_DATA_SIG_LEN 4 + +#define IS_SRIOV_CRIT_REGN_ENTRY_VALID(hdr, id) ((hdr)->valid_tables & (1 << (id))) + enum amdgpu_sriov_vf_mode { SRIOV_VF_MODE_BARE_METAL = 0, SRIOV_VF_MODE_ONE_VF, @@ -296,6 +302,9 @@ struct amdgpu_virt { /* dynamic(v2) critical regions */ struct amdgpu_virt_region init_data_header; + struct amdgpu_virt_region crit_regn; + struct amdgpu_virt_region crit_regn_tbl[AMD_SRIOV_MSG_MAX_TABLE_ID]; + bool is_dynamic_crit_regn_enabled; /* vf2pf message */ struct delayed_work vf2pf_work; @@ -432,6 +441,8 @@ void amdgpu_virt_exchange_data(struct amdgpu_device *adev); void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev); void amdgpu_virt_init(struct amdgpu_device *adev); +int amdgpu_virt_init_critical_region(struct amdgpu_device *adev); + bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h index 9228fd2c6dfd9..1cee083fb6bd6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h @@ -71,6 +71,37 @@ enum amd_sriov_crit_region_version { GPU_CRIT_REGION_V2 = 2, }; +/* v2 layout offset enum (in order of allocation) */ +enum amd_sriov_msg_table_id_enum { + AMD_SRIOV_MSG_IPD_TABLE_ID = 0, + AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID, + AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID, + AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID, + AMD_SRIOV_MSG_BAD_PAGE_INFO_TABLE_ID, + AMD_SRIOV_MSG_INITD_H_TABLE_ID, + AMD_SRIOV_MSG_MAX_TABLE_ID, +}; + +struct amd_sriov_msg_init_data_header { + char signature[4]; /* "INDA" */ + uint32_t version; + uint32_t checksum; + uint32_t initdata_offset; /* 0 */ + uint32_t initdata_size_in_kb; /* 5MB */ + uint32_t valid_tables; + uint32_t vbios_img_offset; + uint32_t vbios_img_size_in_kb; + uint32_t dataexchange_offset; + uint32_t dataexchange_size_in_kb; + uint32_t ras_tele_info_offset; + uint32_t ras_tele_info_size_in_kb; + uint32_t ip_discovery_offset; + uint32_t ip_discovery_size_in_kb; + uint32_t bad_page_info_offset; + uint32_t bad_page_size_in_kb; + uint32_t reserved[8]; +}; + /* * PF2VF history log: * v1 defined in amdgim From bb4182d6787b2f4e43007066888e777003d7e4da Mon Sep 17 00:00:00 2001 From: Ellen Pan Date: Wed, 8 Oct 2025 15:01:10 -0500 Subject: [PATCH 2308/2653] drm/amdgpu: Reuse fw_vram_usage_* for dynamic critical region in SRIOV - During guest driver init, asa VFs receive PF msg to init dynamic critical region(v2), VFs reuse fw_vram_usage_* from ttm to store critical region tables in a 5MB chunk. Signed-off-by: Ellen Pan Reviewed-by: Alex Deucher --- .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 29 ++++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 10 +++---- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 9 ++++++ 3 files changed, 30 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c index c7d32fb216e4e..636385c80f643 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c @@ -181,19 +181,22 @@ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev) u8 frev, crev; int usage_bytes = 0; - if (amdgpu_atom_parse_data_header(ctx, index, NULL, &frev, &crev, &data_offset)) { - if (frev == 2 && crev == 1) { - fw_usage_v2_1 = - (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset); - amdgpu_atomfirmware_allocate_fb_v2_1(adev, - fw_usage_v2_1, - &usage_bytes); - } else if (frev >= 2 && crev >= 2) { - fw_usage_v2_2 = - (struct vram_usagebyfirmware_v2_2 *)(ctx->bios + data_offset); - amdgpu_atomfirmware_allocate_fb_v2_2(adev, - fw_usage_v2_2, - &usage_bytes); + /* Skip atomfirmware allocation for SRIOV VFs when dynamic crit regn is enabled */ + if (!(amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled)) { + if (amdgpu_atom_parse_data_header(ctx, index, NULL, &frev, &crev, &data_offset)) { + if (frev == 2 && crev == 1) { + fw_usage_v2_1 = + (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset); + amdgpu_atomfirmware_allocate_fb_v2_1(adev, + fw_usage_v2_1, + &usage_bytes); + } else if (frev >= 2 && crev >= 2) { + fw_usage_v2_2 = + (struct vram_usagebyfirmware_v2_2 *)(ctx->bios + data_offset); + amdgpu_atomfirmware_allocate_fb_v2_2(adev, + fw_usage_v2_2, + &usage_bytes); + } } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index ab6cf41201049..a681be90a3033 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2347,17 +2347,17 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) return r; /* - *The reserved vram for driver must be pinned to the specified - *place on the VRAM, so reserve it early. + * The reserved VRAM for the driver must be pinned to a specific + * location in VRAM, so reserve it early. */ r = amdgpu_ttm_drv_reserve_vram_init(adev); if (r) return r; /* - * only NAVI10 and onwards ASIC support for IP discovery. - * If IP discovery enabled, a block of memory should be - * reserved for IP discovey. + * only NAVI10 and later ASICs support IP discovery. + * If IP discovery is enabled, a block of memory should be + * reserved for it. */ if (adev->discovery.reserve_tmr) { r = amdgpu_ttm_reserve_tmr(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 1779b1ac30d22..7cabcbdb50e17 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -1008,6 +1008,15 @@ int amdgpu_virt_init_critical_region(struct amdgpu_device *adev) init_data_hdr->bad_page_size_in_kb; } + /* reserved memory starts from crit region base offset with the size of 5MB */ + adev->mman.fw_vram_usage_start_offset = adev->virt.crit_regn.offset; + adev->mman.fw_vram_usage_size = adev->virt.crit_regn.size_kb << 10; + dev_info(adev->dev, + "critical region v%d requested to reserve memory start at %08llx with %llu KB.\n", + init_data_hdr->version, + adev->mman.fw_vram_usage_start_offset, + adev->mman.fw_vram_usage_size >> 10); + adev->virt.is_dynamic_crit_regn_enabled = true; out: From b9127ca70773cdbc7666d0d9b7c5ad9a54e1253f Mon Sep 17 00:00:00 2001 From: Ellen Pan Date: Tue, 7 Oct 2025 11:12:39 -0500 Subject: [PATCH 2309/2653] drm/amdgpu: Add logic for VF ipd and VF bios to init from dynamic crit_region offsets 1. Added VF logic in amdgpu_virt to init IP discovery using the offsets from dynamic(v2) critical regions; 2. Added VF logic in amdgpu_virt to init bios image using the offsets from dynamic(v2) critical regions; Signed-off-by: Ellen Pan Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 34 ++++++++++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 26 ++++++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 37 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 2 + 4 files changed, 85 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c index 00e96419fcdad..db705bf723f12 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -96,11 +96,12 @@ void amdgpu_bios_release(struct amdgpu_device *adev) * part of the system bios. On boot, the system bios puts a * copy of the igp rom at the start of vram if a discrete card is * present. - * For SR-IOV, the vbios image is also put in VRAM in the VF. + * For SR-IOV, if dynamic critical region is not enabled, + * the vbios image is also put at the start of VRAM in the VF. */ static bool amdgpu_read_bios_from_vram(struct amdgpu_device *adev) { - uint8_t __iomem *bios; + uint8_t __iomem *bios = NULL; resource_size_t vram_base; resource_size_t size = 256 * 1024; /* ??? */ @@ -114,18 +115,33 @@ static bool amdgpu_read_bios_from_vram(struct amdgpu_device *adev) adev->bios = NULL; vram_base = pci_resource_start(adev->pdev, 0); - bios = ioremap_wc(vram_base, size); - if (!bios) - return false; adev->bios = kmalloc(size, GFP_KERNEL); - if (!adev->bios) { - iounmap(bios); + if (!adev->bios) return false; + + /* For SRIOV with dynamic critical region is enabled, + * the vbios image is put at a dynamic offset of VRAM in the VF. + * If dynamic critical region is disabled, follow the existing logic as on baremetal. + */ + if (amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled) { + if (amdgpu_virt_get_dynamic_data_info(adev, + AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID, adev->bios, (uint64_t *)&size)) { + amdgpu_bios_release(adev); + return false; + } + } else { + bios = ioremap_wc(vram_base, size); + if (!bios) { + amdgpu_bios_release(adev); + return false; + } + + memcpy_fromio(adev->bios, bios, size); + iounmap(bios); } + adev->bios_size = size; - memcpy_fromio(adev->bios, bios, size); - iounmap(bios); if (!check_atom_bios(adev, size)) { amdgpu_bios_release(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 615f35363b2b5..f8c3a27c9f1cf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -304,10 +304,26 @@ static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, * then it is not required to be reserved. */ if (sz_valid) { - uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; - amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, - adev->discovery.size, false); - adev->discovery.reserve_tmr = true; + if (amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled) { + /* For SRIOV VFs with dynamic critical region enabled, + * we will get the IPD binary via below call. + * If dynamic critical is disabled, fall through to normal seq. + */ + if (amdgpu_virt_get_dynamic_data_info(adev, + AMD_SRIOV_MSG_IPD_TABLE_ID, binary, + (uint64_t *)&adev->discovery.size)) { + dev_err(adev->dev, + "failed to read discovery info from dynamic critical region."); + ret = -EINVAL; + goto exit; + } + } else { + uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; + + amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, + adev->discovery.size, false); + adev->discovery.reserve_tmr = true; + } } else { ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); } @@ -316,7 +332,7 @@ static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, dev_err(adev->dev, "failed to read discovery info from memory, vram size read: %llx", vram_size); - +exit: return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 7cabcbdb50e17..bf0fd95919e6c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -1008,6 +1008,14 @@ int amdgpu_virt_init_critical_region(struct amdgpu_device *adev) init_data_hdr->bad_page_size_in_kb; } + /* Validation for critical region info */ + if (adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb > DISCOVERY_TMR_SIZE) { + dev_err(adev->dev, "Invalid IP discovery size: 0x%x\n", + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb); + r = -EINVAL; + goto out; + } + /* reserved memory starts from crit region base offset with the size of 5MB */ adev->mman.fw_vram_usage_start_offset = adev->virt.crit_regn.offset; adev->mman.fw_vram_usage_size = adev->virt.crit_regn.size_kb << 10; @@ -1026,6 +1034,35 @@ int amdgpu_virt_init_critical_region(struct amdgpu_device *adev) return r; } +int amdgpu_virt_get_dynamic_data_info(struct amdgpu_device *adev, + int data_id, uint8_t *binary, uint64_t *size) +{ + uint32_t data_offset = 0; + uint32_t data_size = 0; + enum amd_sriov_msg_table_id_enum data_table_id = data_id; + + if (data_table_id >= AMD_SRIOV_MSG_MAX_TABLE_ID) + return -EINVAL; + + data_offset = adev->virt.crit_regn_tbl[data_table_id].offset; + data_size = adev->virt.crit_regn_tbl[data_table_id].size_kb << 10; + + /* Validate on input params */ + if (!binary || !size || *size < (uint64_t)data_size) + return -EINVAL; + + /* Proceed to copy the dynamic content */ + amdgpu_device_vram_access(adev, + (uint64_t)data_offset, (uint32_t *)binary, data_size, false); + *size = (uint64_t)data_size; + + dev_dbg(adev->dev, + "Got %s info from dynamic crit_region_table at offset 0x%x with size of 0x%x bytes.\n", + amdgpu_virt_dynamic_crit_table_name[data_id], data_offset, data_size); + + return 0; +} + void amdgpu_virt_init(struct amdgpu_device *adev) { bool is_sriov = false; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 8d03a8620de9a..2a13cc892a139 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -442,6 +442,8 @@ void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev); void amdgpu_virt_init(struct amdgpu_device *adev); int amdgpu_virt_init_critical_region(struct amdgpu_device *adev); +int amdgpu_virt_get_dynamic_data_info(struct amdgpu_device *adev, + int data_id, uint8_t *binary, uint64_t *size); bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); From 618f86dfdbee122b94f331d5c73842999b6f11de Mon Sep 17 00:00:00 2001 From: Ellen Pan Date: Wed, 8 Oct 2025 15:36:50 -0500 Subject: [PATCH 2310/2653] drm/amdgpu: Add logic for VF data exchange region to init from dynamic crit_region offsets 1. Added VF logic to init data exchange region using the offsets from dynamic(v2) critical regions; Signed-off-by: Ellen Pan Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 104 ++++++++++++++++++----- 1 file changed, 85 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index bf0fd95919e6c..66e9cd1035974 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -218,12 +218,12 @@ int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev) &adev->virt.mm_table.gpu_addr, (void *)&adev->virt.mm_table.cpu_addr); if (r) { - DRM_ERROR("failed to alloc mm table and error = %d.\n", r); + dev_err(adev->dev, "failed to alloc mm table and error = %d.\n", r); return r; } memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE); - DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n", + dev_info(adev->dev, "MM table gpu addr = 0x%llx, cpu addr = %p.\n", adev->virt.mm_table.gpu_addr, adev->virt.mm_table.cpu_addr); return 0; @@ -403,7 +403,9 @@ static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev) if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, AMDGPU_GPU_PAGE_SIZE, &bo, NULL)) - DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp); + dev_dbg(adev->dev, + "RAS WARN: reserve vram for retired page %llx fail\n", + bp); data->bps_bo[i] = bo; } data->last_reserved = i + 1; @@ -671,10 +673,34 @@ static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work) schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms); } +static int amdgpu_virt_read_exchange_data_from_mem(struct amdgpu_device *adev, uint32_t *pfvf_data) +{ + uint32_t dataexchange_offset = + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].offset; + uint32_t dataexchange_size = + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].size_kb << 10; + uint64_t pos = 0; + + dev_info(adev->dev, + "Got data exchange info from dynamic crit_region_table at offset 0x%x with size of 0x%x bytes.\n", + dataexchange_offset, dataexchange_size); + + if (!IS_ALIGNED(dataexchange_offset, 4) || !IS_ALIGNED(dataexchange_size, 4)) { + dev_err(adev->dev, "Data exchange data not aligned to 4 bytes\n"); + return -EINVAL; + } + + pos = (uint64_t)dataexchange_offset; + amdgpu_device_vram_access(adev, pos, pfvf_data, + dataexchange_size, false); + + return 0; +} + void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev) { if (adev->virt.vf2pf_update_interval_ms != 0) { - DRM_INFO("clean up the vf2pf work item\n"); + dev_info(adev->dev, "clean up the vf2pf work item\n"); cancel_delayed_work_sync(&adev->virt.vf2pf_work); adev->virt.vf2pf_update_interval_ms = 0; } @@ -682,13 +708,15 @@ void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev) void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) { + uint32_t *pfvf_data = NULL; + adev->virt.fw_reserve.p_pf2vf = NULL; adev->virt.fw_reserve.p_vf2pf = NULL; adev->virt.vf2pf_update_interval_ms = 0; adev->virt.vf2pf_update_retry_cnt = 0; if (adev->mman.fw_vram_usage_va && adev->mman.drv_vram_usage_va) { - DRM_WARN("Currently fw_vram and drv_vram should not have values at the same time!"); + dev_warn(adev->dev, "Currently fw_vram and drv_vram should not have values at the same time!"); } else if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { /* go through this logic in ip_init and reset to init workqueue*/ amdgpu_virt_exchange_data(adev); @@ -697,11 +725,34 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms)); } else if (adev->bios != NULL) { /* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/ - adev->virt.fw_reserve.p_pf2vf = - (struct amd_sriov_msg_pf2vf_info_header *) - (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10)); + if (adev->virt.req_init_data_ver == GPU_CRIT_REGION_V2) { + pfvf_data = + kzalloc(adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].size_kb << 10, + GFP_KERNEL); + if (!pfvf_data) { + dev_err(adev->dev, "Failed to allocate memory for pfvf_data\n"); + return; + } - amdgpu_virt_read_pf2vf_data(adev); + if (amdgpu_virt_read_exchange_data_from_mem(adev, pfvf_data)) + goto free_pfvf_data; + + adev->virt.fw_reserve.p_pf2vf = + (struct amd_sriov_msg_pf2vf_info_header *)pfvf_data; + + amdgpu_virt_read_pf2vf_data(adev); + +free_pfvf_data: + kfree(pfvf_data); + pfvf_data = NULL; + adev->virt.fw_reserve.p_pf2vf = NULL; + } else { + adev->virt.fw_reserve.p_pf2vf = + (struct amd_sriov_msg_pf2vf_info_header *) + (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10)); + + amdgpu_virt_read_pf2vf_data(adev); + } } } @@ -714,14 +765,29 @@ void amdgpu_virt_exchange_data(struct amdgpu_device *adev) if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { if (adev->mman.fw_vram_usage_va) { - adev->virt.fw_reserve.p_pf2vf = - (struct amd_sriov_msg_pf2vf_info_header *) - (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10)); - adev->virt.fw_reserve.p_vf2pf = - (struct amd_sriov_msg_vf2pf_info_header *) - (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 << 10)); - adev->virt.fw_reserve.ras_telemetry = - (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 << 10)); + if (adev->virt.req_init_data_ver == GPU_CRIT_REGION_V2) { + adev->virt.fw_reserve.p_pf2vf = + (struct amd_sriov_msg_pf2vf_info_header *) + (adev->mman.fw_vram_usage_va + + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].offset); + adev->virt.fw_reserve.p_vf2pf = + (struct amd_sriov_msg_vf2pf_info_header *) + (adev->mman.fw_vram_usage_va + + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].offset + + (AMD_SRIOV_MSG_SIZE_KB << 10)); + adev->virt.fw_reserve.ras_telemetry = + (adev->mman.fw_vram_usage_va + + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID].offset); + } else { + adev->virt.fw_reserve.p_pf2vf = + (struct amd_sriov_msg_pf2vf_info_header *) + (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10)); + adev->virt.fw_reserve.p_vf2pf = + (struct amd_sriov_msg_vf2pf_info_header *) + (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 << 10)); + adev->virt.fw_reserve.ras_telemetry = + (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 << 10)); + } } else if (adev->mman.drv_vram_usage_va) { adev->virt.fw_reserve.p_pf2vf = (struct amd_sriov_msg_pf2vf_info_header *) @@ -829,7 +895,7 @@ static bool amdgpu_virt_init_req_data(struct amdgpu_device *adev, u32 reg) break; default: /* other chip doesn't support SRIOV */ is_sriov = false; - DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type); + dev_err(adev->dev, "Unknown asic type: %d!\n", adev->asic_type); break; } } @@ -1510,7 +1576,7 @@ amdgpu_ras_block_to_sriov(struct amdgpu_device *adev, enum amdgpu_ras_block bloc case AMDGPU_RAS_BLOCK__MPIO: return RAS_TELEMETRY_GPU_BLOCK_MPIO; default: - DRM_WARN_ONCE("Unsupported SRIOV RAS telemetry block 0x%x\n", + dev_warn(adev->dev, "Unsupported SRIOV RAS telemetry block 0x%x\n", block); return RAS_TELEMETRY_GPU_BLOCK_COUNT; } From e460a5660655af658423d5baf7ef9cfb6ea6a56b Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Sat, 11 Oct 2025 16:52:17 +0800 Subject: [PATCH 2311/2653] drm/amdgpu: query block error count of ras module Query block error count of ras module. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 29 ++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 9df0914de8430..a0d92e2266699 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1543,9 +1543,36 @@ static int amdgpu_ras_query_error_status_with_event(struct amdgpu_device *adev, return ret; } +static int amdgpu_uniras_query_block_ecc(struct amdgpu_device *adev, + struct ras_query_if *info) +{ + struct ras_cmd_block_ecc_info_req req = {0}; + struct ras_cmd_block_ecc_info_rsp rsp = {0}; + int ret; + + if (!info) + return -EINVAL; + + req.block_id = info->head.block; + req.subblock_id = info->head.sub_block_index; + + ret = amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__GET_BLOCK_ECC_STATUS, + &req, sizeof(req), &rsp, sizeof(rsp)); + if (!ret) { + info->ce_count = rsp.ce_count; + info->ue_count = rsp.ue_count; + info->de_count = rsp.de_count; + } + + return ret; +} + int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_if *info) { - return amdgpu_ras_query_error_status_with_event(adev, info, RAS_EVENT_TYPE_INVALID); + if (amdgpu_uniras_enabled(adev)) + return amdgpu_uniras_query_block_ecc(adev, info); + else + return amdgpu_ras_query_error_status_with_event(adev, info, RAS_EVENT_TYPE_INVALID); } int amdgpu_ras_reset_error_count(struct amdgpu_device *adev, From c7db91225f3af278a828f63dd14430d6f010c215 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 16 Oct 2025 18:49:18 +0530 Subject: [PATCH 2312/2653] drm/amdgpu: Remove unused members in amdgpu_mman Discovery related members are now part of amdgpu_discovery_info. Signed-off-by: Lijo Lazar Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index c46943daaee02..9c4282c7e32e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -93,9 +93,6 @@ struct amdgpu_mman { uint64_t stolen_reserved_offset; uint64_t stolen_reserved_size; - /* discovery */ - uint8_t *discovery_bin; - uint32_t discovery_tmr_size; /* fw reserved memory */ struct amdgpu_bo *fw_reserved_memory; struct amdgpu_bo *fw_reserved_memory_extend; From 4914bc2f0cac7102feb72c91eba8b6760e5dac9c Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 16 Oct 2025 13:55:27 -0500 Subject: [PATCH 2313/2653] drm/amd: Check that VPE has reached DPM0 in idle handler [Why] Newer VPE microcode has functionality that will decrease DPM level only when a workload has run for 2 or more seconds. If VPE is turned off before this DPM decrease and the PMFW doesn't reset it when power gating VPE, the SOC can get stuck with a higher DPM level. This can happen from amdgpu's ring buffer test because it's a short quick workload for VPE and VPE is turned off after 1s. [How] In idle handler besides checking fences are drained check PMFW version to determine if it will reset DPM when power gating VPE. If PMFW will not do this, then check VPE DPM level. If it is not DPM0 reschedule delayed work again until it is. Cc: stable@vger.kernel.org Cc: Peyton.Lee@amd.com Reported-by: Sultan Alsawaf Reviewed-by: Sultan Alsawaf Tested-by: Sultan Alsawaf Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4615 Reviewed-by: Lijo Lazar Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 33 ++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c index 474bfe36c0c2f..f4932339d79db 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c @@ -322,6 +322,26 @@ static int vpe_early_init(struct amdgpu_ip_block *ip_block) return 0; } +static bool vpe_need_dpm0_at_power_down(struct amdgpu_device *adev) +{ + switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { + case IP_VERSION(6, 1, 1): + return adev->pm.fw_version < 0x0a640500; + default: + return false; + } +} + +static int vpe_get_dpm_level(struct amdgpu_device *adev) +{ + struct amdgpu_vpe *vpe = &adev->vpe; + + if (!adev->pm.dpm_enabled) + return 0; + + return RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_lv)); +} + static void vpe_idle_work_handler(struct work_struct *work) { struct amdgpu_device *adev = @@ -329,11 +349,16 @@ static void vpe_idle_work_handler(struct work_struct *work) unsigned int fences = 0; fences += amdgpu_fence_count_emitted(&adev->vpe.ring); + if (fences) + goto reschedule; - if (fences == 0) - amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE); - else - schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT); + if (vpe_need_dpm0_at_power_down(adev) && vpe_get_dpm_level(adev) != 0) + goto reschedule; + + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE); + +reschedule: + schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT); } static int vpe_common_init(struct amdgpu_vpe *vpe) From 393da5a4af7c76340a1581cd6c45a9fd9605cfb4 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Thu, 11 Sep 2025 12:41:41 +0100 Subject: [PATCH 2314/2653] drm/amdgpu: More compact VCE IB emission Avoid constant register reloads while emitting IBs by using a local write pointer and only updating the size at the end of each helper. Signed-off-by: Tvrtko Ursulin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 94 +++++++++++++------------ 1 file changed, 50 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index b9060bcd48064..60e54d3c384be 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -444,6 +444,7 @@ static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, struct amdgpu_ib ib_msg; struct dma_fence *f = NULL; uint64_t addr; + u32 *ptr; int i, r; r = amdgpu_job_alloc_with_ib(ring->adev, &ring->adev->vce.entity, @@ -462,45 +463,47 @@ static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, goto err; ib = &job->ibs[0]; + ptr = ib->ptr; /* let addr point to page boundary */ addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg.gpu_addr); /* stitch together an VCE create msg */ - ib->length_dw = 0; - ib->ptr[ib->length_dw++] = 0x0000000c; /* len */ - ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */ - ib->ptr[ib->length_dw++] = handle; + *ptr++ = 0x0000000c; /* len */ + *ptr++ = 0x00000001; /* session cmd */ + *ptr++ = handle; if ((ring->adev->vce.fw_version >> 24) >= 52) - ib->ptr[ib->length_dw++] = 0x00000040; /* len */ + *ptr++ = 0x00000040; /* len */ else - ib->ptr[ib->length_dw++] = 0x00000030; /* len */ - ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */ - ib->ptr[ib->length_dw++] = 0x00000000; - ib->ptr[ib->length_dw++] = 0x00000042; - ib->ptr[ib->length_dw++] = 0x0000000a; - ib->ptr[ib->length_dw++] = 0x00000001; - ib->ptr[ib->length_dw++] = 0x00000080; - ib->ptr[ib->length_dw++] = 0x00000060; - ib->ptr[ib->length_dw++] = 0x00000100; - ib->ptr[ib->length_dw++] = 0x00000100; - ib->ptr[ib->length_dw++] = 0x0000000c; - ib->ptr[ib->length_dw++] = 0x00000000; + *ptr++ = 0x00000030; /* len */ + *ptr++ = 0x01000001; /* create cmd */ + *ptr++ = 0x00000000; + *ptr++ = 0x00000042; + *ptr++ = 0x0000000a; + *ptr++ = 0x00000001; + *ptr++ = 0x00000080; + *ptr++ = 0x00000060; + *ptr++ = 0x00000100; + *ptr++ = 0x00000100; + *ptr++ = 0x0000000c; + *ptr++ = 0x00000000; if ((ring->adev->vce.fw_version >> 24) >= 52) { - ib->ptr[ib->length_dw++] = 0x00000000; - ib->ptr[ib->length_dw++] = 0x00000000; - ib->ptr[ib->length_dw++] = 0x00000000; - ib->ptr[ib->length_dw++] = 0x00000000; + *ptr++ = 0x00000000; + *ptr++ = 0x00000000; + *ptr++ = 0x00000000; + *ptr++ = 0x00000000; } - ib->ptr[ib->length_dw++] = 0x00000014; /* len */ - ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */ - ib->ptr[ib->length_dw++] = upper_32_bits(addr); - ib->ptr[ib->length_dw++] = addr; - ib->ptr[ib->length_dw++] = 0x00000001; + *ptr++ = 0x00000014; /* len */ + *ptr++ = 0x05000005; /* feedback buffer */ + *ptr++ = upper_32_bits(addr); + *ptr++ = addr; + *ptr++ = 0x00000001; + + ib->length_dw = ptr - ib->ptr; for (i = ib->length_dw; i < ib_size_dw; ++i) - ib->ptr[i] = 0x0; + *ptr++ = 0x0; r = amdgpu_job_submit_direct(job, ring, &f); amdgpu_ib_free(&ib_msg, f); @@ -534,6 +537,7 @@ static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, struct amdgpu_job *job; struct amdgpu_ib *ib; struct dma_fence *f = NULL; + u32 *ptr; int i, r; r = amdgpu_job_alloc_with_ib(ring->adev, &ring->adev->vce.entity, @@ -545,27 +549,29 @@ static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, return r; ib = &job->ibs[0]; + ptr = ib->ptr; /* stitch together an VCE destroy msg */ - ib->length_dw = 0; - ib->ptr[ib->length_dw++] = 0x0000000c; /* len */ - ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */ - ib->ptr[ib->length_dw++] = handle; - - ib->ptr[ib->length_dw++] = 0x00000020; /* len */ - ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ - ib->ptr[ib->length_dw++] = 0xffffffff; /* next task info, set to 0xffffffff if no */ - ib->ptr[ib->length_dw++] = 0x00000001; /* destroy session */ - ib->ptr[ib->length_dw++] = 0x00000000; - ib->ptr[ib->length_dw++] = 0x00000000; - ib->ptr[ib->length_dw++] = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */ - ib->ptr[ib->length_dw++] = 0x00000000; - - ib->ptr[ib->length_dw++] = 0x00000008; /* len */ - ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */ + *ptr++ = 0x0000000c; /* len */ + *ptr++ = 0x00000001; /* session cmd */ + *ptr++ = handle; + + *ptr++ = 0x00000020; /* len */ + *ptr++ = 0x00000002; /* task info */ + *ptr++ = 0xffffffff; /* next task info, set to 0xffffffff if no */ + *ptr++ = 0x00000001; /* destroy session */ + *ptr++ = 0x00000000; + *ptr++ = 0x00000000; + *ptr++ = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */ + *ptr++ = 0x00000000; + + *ptr++ = 0x00000008; /* len */ + *ptr++ = 0x02000001; /* destroy cmd */ + + ib->length_dw = ptr - ib->ptr; for (i = ib->length_dw; i < ib_size_dw; ++i) - ib->ptr[i] = 0x0; + *ptr++ = 0x0; if (direct) r = amdgpu_job_submit_direct(job, ring, &f); From cae0510c46dd3a79e03337dc213bb29b111d0950 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Mon, 20 Oct 2025 17:34:34 -0500 Subject: [PATCH 2315/2653] drm/amd: Add missing return for VPE idle handler Adjusting the idle handler for DPM0 handling forgot a return statement which causes the system to not be able to enter s0i3. Add the missing return statement. Cc: stable@vger.kernel.org Reported-by: Sultan Alsawaf Closes: https://lore.kernel.org/amd-gfx/aPawCXBY9eM8oZvG@sultan-box/ Reviewed-by: Alex Deucher Reviewed-by: Sultan Alsawaf Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c index f4932339d79db..aa78c2ee9e21c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c @@ -356,6 +356,7 @@ static void vpe_idle_work_handler(struct work_struct *work) goto reschedule; amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE); + return; reschedule: schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT); From dc4905c7a9c35f26c176dae141411bc09db5d7d8 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Mon, 20 Oct 2025 16:51:08 +0800 Subject: [PATCH 2316/2653] Revert "drm/amdkcl: update the functions to use amdgpu version of hmm on non-upstream code" This reverts commit 4f985b04fac98db812725ca729c096b5261735f1. --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 6 ++++-- 5 files changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 34940ba10e2aa..741307be39678 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1183,7 +1183,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, goto unregister_out; } - ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages, NULL); if (ret) { pr_err("%s: Failed to get user pages: %d\n", __func__, ret); goto free_out; @@ -3004,7 +3004,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, } /* Get updated user pages */ - ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages, NULL); if (ret) { mem->user_pages[0] = NULL; pr_debug("%s: Failed to get user pages: %d\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index b75d56d6de338..63482f7397caa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1059,7 +1059,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto error_free_pages; } - r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages); + r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages, NULL); if (r) { DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); kvfree(e->user_pages); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index bbe0ee582a618..018ca29fc8cd7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -649,7 +649,8 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, return -ENOMEM; r = amdgpu_ttm_tt_get_user_pages(bo, range); #else - r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages); + r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, + &range); #endif if (r) { #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index a681be90a3033..7322c0336e0b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -835,7 +835,8 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, * This provides a wrapper around the get_user_pages() call to provide * device accessible pages that back user memory. */ -int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, + struct hmm_range **range) { struct ttm_tt *ttm = bo->tbo.ttm; struct amdgpu_ttm_tt *gtt = (void *)ttm; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 9c4282c7e32e5..dad6fe2528124 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -203,7 +203,8 @@ uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct amdgpu_hmm_range *range); #else -int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages); +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, + struct hmm_range **range); #endif #else #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED @@ -213,7 +214,8 @@ static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, return -EPERM; } #else -static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) +static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, + struct hmm_range **range) { return -EPERM; } From 840ff710ef102f92b34382e9195359c1cd720b66 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Tue, 21 Oct 2025 17:49:23 +0800 Subject: [PATCH 2317/2653] Revert "drm/amdgpu: add the kernel docs for alloc/free/valid range" This reverts commit e2a02b80eefc5845c48f184bc8eea588a8f267e6. --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 33 ------------------------- 1 file changed, 33 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 9076b8a74eed3..e4a1858609991 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -920,19 +920,6 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, return r; } -/** - * amdgpu_hmm_range_valid - check if an HMM range is still valid - * @range: pointer to the &struct amdgpu_hmm_range to validate - * - * Determines whether the given HMM range @range is still valid by - * checking for invalidations via the MMU notifier sequence. This is - * typically used to verify that the range has not been invalidated - * by concurrent address space updates before it is accessed. - * - * Return: - * * true if @range is valid and can be used safely - * * false if @range is NULL or has been invalidated - */ bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range) { if (!range) @@ -942,17 +929,6 @@ bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range) range->hmm_range.notifier_seq); } -/** - * amdgpu_hmm_range_alloc - allocate and initialize an AMDGPU HMM range - * @bo: optional buffer object to associate with this HMM range - * - * Allocates memory for amdgpu_hmm_range and associates it with the @bo passed. - * The reference count of the @bo is incremented. - * - * Return: - * Pointer to a newly allocated struct amdgpu_hmm_range on success, - * or NULL if memory allocation fails. - */ struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo) { struct amdgpu_hmm_range *range; @@ -965,15 +941,6 @@ struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo) return range; } -/** - * amdgpu_hmm_range_free - release an AMDGPU HMM range - * @range: pointer to the range object to free - * - * Releases all resources held by @range, including the associated - * hmm_pfns and the dropping reference of associated bo if any. - * - * Return: void - */ void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range) { if (!range) From 47077ec6d19c77682a076d77895f8d4de22df664 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Tue, 21 Oct 2025 17:49:30 +0800 Subject: [PATCH 2318/2653] Revert "drm/amdkcl: wrap code under macro define HAVE_AMDKCL_HMM_MIRROR_ENABLED" This reverts commit 63d057f0e83f920eed3cb21ca76464b13848c5a7. --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 23 +++++------------------ 1 file changed, 5 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index e3fe7e1901a84..d91b4cb05ef1c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -862,28 +862,21 @@ static int amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) { struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr); - struct amdgpu_device *adev = uq_mgr->adev; - struct amdgpu_vm *vm = &fpriv->vm; - struct amdgpu_bo_va *bo_va; - struct drm_exec exec; - int ret; -#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool invalidated = false, new_addition = false; struct ttm_operation_ctx ctx = { true, false }; + struct amdgpu_device *adev = uq_mgr->adev; struct amdgpu_hmm_range *range; + struct amdgpu_vm *vm = &fpriv->vm; unsigned long key, tmp_key; + struct amdgpu_bo_va *bo_va; struct amdgpu_bo *bo; + struct drm_exec exec; struct xarray xa; + int ret; xa_init(&xa); retry_lock: -#else - dev_warn_once(adev->dev, "HMM is not functional; falling back to legacy path. " - "Legacy path is untested and may be unstable. " - "Please enable HMM or refer to documentation for supported kernels.\n"); - WARN_ON_ONCE(1); -#endif drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); drm_exec_until_all_locked(&exec) { ret = amdgpu_vm_lock_pd(vm, &exec, 1); @@ -910,7 +903,6 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) goto unlock_all; } -#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (invalidated) { xa_for_each(&xa, tmp_key, range) { bo = range->bo; @@ -928,13 +920,11 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) } invalidated = false; } -#endif ret = amdgpu_vm_handle_moved(adev, vm, NULL); if (ret) goto unlock_all; -#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED key = 0; /* Validate User Ptr BOs */ list_for_each_entry(bo_va, &vm->done, base.vm_status) { @@ -978,7 +968,6 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) new_addition = false; goto retry_lock; } -#endif ret = amdgpu_vm_update_pdes(adev, vm, false); if (ret) @@ -999,7 +988,6 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) unlock_all: drm_exec_fini(&exec); -#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED xa_for_each(&xa, tmp_key, range) { if (!range) continue; @@ -1007,7 +995,6 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) amdgpu_hmm_range_free(range); } xa_destroy(&xa); -#endif return ret; } From 71f86fc3a289dc4d79bfe7181942dd03e8a590b0 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Tue, 21 Oct 2025 17:49:39 +0800 Subject: [PATCH 2319/2653] Revert "drm/amdgpu/userqueue: validate userptrs for userqueues" This reverts commit eb6294aa70400100663330281e2ceecc9250c73d. --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 79 ----------------------- 1 file changed, 79 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index d91b4cb05ef1c..b270ec2d92130 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -29,7 +29,6 @@ #include "amdgpu.h" #include "amdgpu_vm.h" #include "amdgpu_userq.h" -#include "amdgpu_hmm.h" #include "amdgpu_userq_fence.h" u32 amdgpu_userq_get_supported_ip_mask(struct amdgpu_device *adev) @@ -862,21 +861,12 @@ static int amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) { struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr); - bool invalidated = false, new_addition = false; - struct ttm_operation_ctx ctx = { true, false }; struct amdgpu_device *adev = uq_mgr->adev; - struct amdgpu_hmm_range *range; struct amdgpu_vm *vm = &fpriv->vm; - unsigned long key, tmp_key; struct amdgpu_bo_va *bo_va; - struct amdgpu_bo *bo; struct drm_exec exec; - struct xarray xa; int ret; - xa_init(&xa); - -retry_lock: drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); drm_exec_until_all_locked(&exec) { ret = amdgpu_vm_lock_pd(vm, &exec, 1); @@ -903,72 +893,10 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) goto unlock_all; } - if (invalidated) { - xa_for_each(&xa, tmp_key, range) { - bo = range->bo; - amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); - ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); - if (ret) - goto unlock_all; - - amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, range); - - amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); - ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); - if (ret) - goto unlock_all; - } - invalidated = false; - } - ret = amdgpu_vm_handle_moved(adev, vm, NULL); if (ret) goto unlock_all; - key = 0; - /* Validate User Ptr BOs */ - list_for_each_entry(bo_va, &vm->done, base.vm_status) { - bo = bo_va->base.bo; - - if (!amdgpu_ttm_tt_is_userptr(bo->tbo.ttm)) - continue; - - range = xa_load(&xa, key); - if (range && range->bo != bo) { - xa_erase(&xa, key); - amdgpu_hmm_range_free(range); - range = NULL; - } - - if (!range) { - range = amdgpu_hmm_range_alloc(bo); - if (!range) { - ret = -ENOMEM; - goto unlock_all; - } - - xa_store(&xa, key, range, GFP_KERNEL); - new_addition = true; - } - key++; - } - - if (new_addition) { - drm_exec_fini(&exec); - xa_for_each(&xa, tmp_key, range) { - if (!range) - continue; - bo = range->bo; - ret = amdgpu_ttm_tt_get_user_pages(bo, range); - if (ret) - goto unlock_all; - } - - invalidated = true; - new_addition = false; - goto retry_lock; - } - ret = amdgpu_vm_update_pdes(adev, vm, false); if (ret) goto unlock_all; @@ -988,13 +916,6 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) unlock_all: drm_exec_fini(&exec); - xa_for_each(&xa, tmp_key, range) { - if (!range) - continue; - bo = range->bo; - amdgpu_hmm_range_free(range); - } - xa_destroy(&xa); return ret; } From 3cec490711b54974cedb91267b56c8f1c92b4547 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Tue, 21 Oct 2025 17:49:49 +0800 Subject: [PATCH 2320/2653] Revert "drm/amdgpu: update the functions to use amdgpu version of hmm" This reverts commit 5e0ed4b28541faa91f3f3cc3732fb83f13350001. --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 6 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 33 +++++++------------ drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 18 ++++------ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 7 ++-- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_migrate.h | 1 + drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 14 ++++---- drivers/gpu/drm/amd/amdkfd/kfd_svm.h | 1 + 13 files changed, 45 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 40c46e6c88988..bcdafcf91c272 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -73,7 +73,7 @@ struct kgd_mem { struct kfd_ipc_obj *ipc_obj; struct dma_buf *dmabuf; #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - struct amdgpu_hmm_range *range; + struct hmm_range *range; #else struct page **user_pages; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 741307be39678..62fd4a370943d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1120,7 +1120,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, struct amdkfd_process_info *process_info = mem->process_info; struct amdgpu_bo *bo = mem->bo; struct ttm_operation_ctx ctx = { true, false }; - struct amdgpu_hmm_range *range; + struct hmm_range *range; int ret = 0; mutex_lock(&process_info->lock); @@ -1153,7 +1153,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, } #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - range = amdgpu_hmm_range_alloc(NULL); + range = amdgpu_hmm_range_alloc(); if (unlikely(!range)) { ret = -ENOMEM; goto unregister_out; @@ -2948,7 +2948,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, } #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - mem->range = amdgpu_hmm_range_alloc(NULL); + mem->range = amdgpu_hmm_range_alloc(); if (unlikely(!mem->range)) return -ENOMEM; /* Get updated user pages */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h index 43862a8082110..e3f75a65fcb6b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h @@ -39,7 +39,7 @@ struct amdgpu_bo_list_entry { struct amdgpu_bo *bo; struct amdgpu_bo_va *bo_va; uint32_t priority; - struct amdgpu_hmm_range *range; + struct hmm_range *range; #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool user_invalidated; #else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 63482f7397caa..caef2774b6950 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -915,7 +916,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, bool userpage_invalidated = false; struct amdgpu_bo *bo = e->bo; - e->range = amdgpu_hmm_range_alloc(NULL); + e->range = amdgpu_hmm_range_alloc(); if (unlikely(!e->range)) return -ENOMEM; @@ -924,8 +925,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto out_free_user_pages; for (i = 0; i < bo->tbo.ttm->num_pages; i++) { - if (bo->tbo.ttm->pages[i] != - hmm_pfn_to_page(e->range->hmm_range.hmm_pfns[i])) { + if (bo->tbo.ttm->pages[i] != hmm_pfn_to_page(e->range->hmm_pfns[i])) { userpage_invalidated = true; break; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 018ca29fc8cd7..478184576f0ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -602,7 +602,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_amdgpu_gem_userptr *args = data; struct amdgpu_fpriv *fpriv = filp->driver_priv; struct drm_gem_object *gobj; - struct amdgpu_hmm_range *range; + struct hmm_range *range; struct amdgpu_bo *bo; uint32_t handle; int r; @@ -644,7 +644,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - range = amdgpu_hmm_range_alloc(NULL); + range = amdgpu_hmm_range_alloc(); if (unlikely(!range)) return -ENOMEM; r = amdgpu_ttm_tt_get_user_pages(bo, range); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index e4a1858609991..55b2359799ae4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -843,13 +843,12 @@ const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, void *owner, - struct amdgpu_hmm_range *range) + struct hmm_range *hmm_range) { unsigned long end; unsigned long timeout; unsigned long *pfns; int r = 0; - struct hmm_range *hmm_range = &range->hmm_range; pfns = kvmalloc_array(npages, sizeof(*pfns), GFP_KERNEL); if (unlikely(!pfns)) { @@ -920,38 +919,30 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, return r; } -bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range) +bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range) { - if (!range) + if (!hmm_range) return false; - return !mmu_interval_read_retry(range->hmm_range.notifier, - range->hmm_range.notifier_seq); + return !mmu_interval_read_retry(hmm_range->notifier, + hmm_range->notifier_seq); } -struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo) +struct hmm_range *amdgpu_hmm_range_alloc(void) { - struct amdgpu_hmm_range *range; - - range = kzalloc(sizeof(*range), GFP_KERNEL); - if (!range) - return NULL; - - range->bo = amdgpu_bo_ref(bo); - return range; + return kzalloc(sizeof(struct hmm_range), GFP_KERNEL); } -void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range) +void amdgpu_hmm_range_free(struct hmm_range *hmm_range) { - if (!range) + if (!hmm_range) return; #ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT - kvfree(range->hmm_range.pfns); + kvfree(hmm_range->pfns); #else - kvfree(range->hmm_range.hmm_pfns); + kvfree(hmm_range->hmm_pfns); #endif - amdgpu_bo_unref(&range->bo); - kfree(range); + kfree(hmm_range); } #endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index e73a6809e0d6d..4ec014a918514 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -82,20 +82,16 @@ static inline struct page *hmm_pfn_to_page(unsigned long hmm_pfn) return hmm_device_entry_to_page(&hmm_range, hmm_pfn); } #endif -struct amdgpu_hmm_range { - struct hmm_range hmm_range; - struct amdgpu_bo *bo; -}; int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, void *owner, - struct amdgpu_hmm_range *range); + struct hmm_range *hmm_range); #if defined(CONFIG_HMM_MIRROR) -bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range); -struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo); -void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range); +bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range); +struct hmm_range *amdgpu_hmm_range_alloc(void); +void amdgpu_hmm_range_free(struct hmm_range *hmm_range); int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr); void amdgpu_hmm_unregister(struct amdgpu_bo *bo); #else @@ -108,17 +104,17 @@ static inline int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) static inline void amdgpu_hmm_unregister(struct amdgpu_bo *bo) {} -static inline bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range) +static inline bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range) { return false; } -static inline struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo) +static inline struct hmm_range *amdgpu_hmm_range_alloc(void) { return NULL; } -static inline void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range) {} +static inline void amdgpu_hmm_range_free(struct hmm_range *hmm_range) {} #endif #endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 7322c0336e0b6..205b70ebfb19f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -782,7 +782,7 @@ struct amdgpu_ttm_tt { * that range is a valid memory and it is freed too. */ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, - struct amdgpu_hmm_range *range) + struct hmm_range *range) { struct ttm_tt *ttm = bo->tbo.ttm; struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); @@ -917,12 +917,12 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, * that backs user memory and will ultimately be mapped into the device * address space. */ -void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range) +void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct hmm_range *range) { unsigned long i; for (i = 0; i < ttm->num_pages; ++i) - ttm->pages[i] = range ? hmm_pfn_to_page(range->hmm_range.hmm_pfns[i]) : NULL; + ttm->pages[i] = range ? hmm_pfn_to_page(range->hmm_pfns[i]) : NULL; } #else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index dad6fe2528124..27dd8129cd565 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -28,7 +28,6 @@ #include #include #include "amdgpu_vram_mgr.h" -#include "amdgpu_hmm.h" #define AMDGPU_PL_GDS (TTM_PL_PRIV + 0) #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1) @@ -201,7 +200,7 @@ uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, - struct amdgpu_hmm_range *range); + struct hmm_range *range); #else int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, struct hmm_range **range); @@ -209,7 +208,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, #else #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, - struct amdgpu_hmm_range *range) + struct hmm_range *range) { return -EPERM; } @@ -223,7 +222,7 @@ static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page #endif #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED -void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range); +void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct hmm_range *range); #else void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages); #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index ddc42699dd3cc..d0bb8ecf3045e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -21,6 +21,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h index 2b7fd442d29c6..2eebf67f9c2ce 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h @@ -31,6 +31,7 @@ #include #include #include +#include #include "kfd_priv.h" #include "kfd_svm.h" diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 5fe318b27a5f4..5639a51212e05 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1702,7 +1702,7 @@ static int svm_range_validate_and_map(struct mm_struct *mm, start = map_start << PAGE_SHIFT; end = (map_last + 1) << PAGE_SHIFT; for (addr = start; !r && addr < end; ) { - struct amdgpu_hmm_range *range = NULL; + struct hmm_range *hmm_range = NULL; unsigned long map_start_vma; unsigned long map_last_vma; struct vm_area_struct *vma; @@ -1741,13 +1741,13 @@ static int svm_range_validate_and_map(struct mm_struct *mm, } WRITE_ONCE(p->svms.faulting_task, current); - range = amdgpu_hmm_range_alloc(NULL); + hmm_range = amdgpu_hmm_range_alloc(); r = amdgpu_hmm_range_get_pages(&prange->notifier, addr, npages, readonly, owner, - range); + hmm_range); WRITE_ONCE(p->svms.faulting_task, NULL); if (r) { - amdgpu_hmm_range_free(range); + amdgpu_hmm_range_free(hmm_range); pr_debug("failed %d to get svm range pages\n", r); } } else { @@ -1757,7 +1757,7 @@ static int svm_range_validate_and_map(struct mm_struct *mm, if (!r) { offset = (addr >> PAGE_SHIFT) - prange->start; r = svm_range_dma_map(prange, ctx->bitmap, offset, npages, - range->hmm_range.hmm_pfns); + hmm_range->hmm_pfns); if (r) pr_debug("failed %d to dma map range\n", r); } @@ -1768,12 +1768,12 @@ static int svm_range_validate_and_map(struct mm_struct *mm, * Overrride return value to TRY AGAIN only if prior returns * were successful */ - if (range && !amdgpu_hmm_range_valid(range) && !r) { + if (hmm_range && !amdgpu_hmm_range_valid(hmm_range) && !r) { pr_debug("hmm update the range, need validate again\n"); r = -EAGAIN; } /* Free the hmm range */ - amdgpu_hmm_range_free(range); + amdgpu_hmm_range_free(hmm_range); if (!r && !list_empty(&prange->child_list)) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h index a63dfc95b602b..01c7a48779044 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h @@ -31,6 +31,7 @@ #include #include #include +#include #include "amdgpu.h" #include "kfd_priv.h" From 3d66ab9cd3c2e39a5776d7a2d939e0ed317b62d7 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Tue, 21 Oct 2025 17:50:02 +0800 Subject: [PATCH 2321/2653] Revert "drm/amdgpu: clean up amdgpu hmm range functions" it's caused by https://ontrack-internal.amd.com/browse/SWDEV-561693 This reverts commit dd889a641ca5ed2dc21ec04c47b67e67e4e931c8. --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 18 ++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 10 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 6 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 23 +++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 17 +-------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 38 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 13 +++++++ drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 9 ++--- 8 files changed, 79 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 62fd4a370943d..d4acda7bda131 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1153,7 +1153,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, } #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - range = amdgpu_hmm_range_alloc(); + range = kzalloc(sizeof(*range), GFP_KERNEL); if (unlikely(!range)) { ret = -ENOMEM; goto unregister_out; @@ -1161,7 +1161,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, ret = amdgpu_ttm_tt_get_user_pages(bo, range); if (ret) { - amdgpu_hmm_range_free(range); + kfree(range); if (ret == -EAGAIN) pr_debug("Failed to get user pages, try again\n"); else @@ -1210,7 +1210,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, release_out: #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - amdgpu_hmm_range_free(range); + amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); #else if (ret) amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, NULL); @@ -2032,7 +2032,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( amdgpu_hmm_unregister(mem->bo); #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mutex_lock(&process_info->notifier_lock); - amdgpu_hmm_range_free(mem->range); + amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range); mutex_unlock(&process_info->notifier_lock); #else /* Free user pages if necessary */ @@ -2922,7 +2922,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, bo = mem->bo; #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - amdgpu_hmm_range_free(mem->range); + amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range); mem->range = NULL; #endif @@ -2948,13 +2948,13 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, } #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - mem->range = amdgpu_hmm_range_alloc(); + mem->range = kzalloc(sizeof(*mem->range), GFP_KERNEL); if (unlikely(!mem->range)) return -ENOMEM; /* Get updated user pages */ ret = amdgpu_ttm_tt_get_user_pages(bo, mem->range); if (ret) { - amdgpu_hmm_range_free(mem->range); + kfree(mem->range); mem->range = NULL; pr_debug("Failed %d to get user pages\n", ret); @@ -3186,8 +3186,8 @@ static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_i continue; /* Only check mem with hmm range associated */ - valid = amdgpu_hmm_range_valid(mem->range); - amdgpu_hmm_range_free(mem->range); + valid = amdgpu_ttm_tt_get_user_pages_done( + mem->bo->tbo.ttm, mem->range); mem->range = NULL; if (!valid) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index caef2774b6950..6c03ae3e37ae8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -916,7 +916,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, bool userpage_invalidated = false; struct amdgpu_bo *bo = e->bo; - e->range = amdgpu_hmm_range_alloc(); + e->range = kzalloc(sizeof(*e->range), GFP_KERNEL); if (unlikely(!e->range)) return -ENOMEM; @@ -1110,7 +1110,9 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, out_free_user_pages: #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { - amdgpu_hmm_range_free(e->range); + struct amdgpu_bo *bo = e->bo; + + amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, e->range); e->range = NULL; } #else @@ -1460,8 +1462,8 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, */ r = 0; amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { - r |= !amdgpu_hmm_range_valid(e->range); - amdgpu_hmm_range_free(e->range); + r |= !amdgpu_ttm_tt_get_user_pages_done(e->bo->tbo.ttm, + e->range); e->range = NULL; } if (r) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 478184576f0ce..0ea9ab4c0b26c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -644,7 +644,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - range = amdgpu_hmm_range_alloc(); + range = kzalloc(sizeof(*range), GFP_KERNEL); if (unlikely(!range)) return -ENOMEM; r = amdgpu_ttm_tt_get_user_pages(bo, range); @@ -654,7 +654,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, #endif if (r) { #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - amdgpu_hmm_range_free(range); + kfree(range); #endif goto release_object; } @@ -692,7 +692,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, user_pages_done: #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) - amdgpu_hmm_range_free(range); + amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); #else release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 55b2359799ae4..14e62c2be1149 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -919,30 +919,19 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, return r; } -bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range) +bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range) { - if (!hmm_range) - return false; - - return !mmu_interval_read_retry(hmm_range->notifier, - hmm_range->notifier_seq); -} - -struct hmm_range *amdgpu_hmm_range_alloc(void) -{ - return kzalloc(sizeof(struct hmm_range), GFP_KERNEL); -} - -void amdgpu_hmm_range_free(struct hmm_range *hmm_range) -{ - if (!hmm_range) - return; + bool r; + r = mmu_interval_read_retry(hmm_range->notifier, + hmm_range->notifier_seq); #ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT kvfree(hmm_range->pfns); #else kvfree(hmm_range->hmm_pfns); #endif kfree(hmm_range); + + return r; } #endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index 4ec014a918514..e078aa4905e38 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -87,11 +87,9 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, void *owner, struct hmm_range *hmm_range); +bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range); #if defined(CONFIG_HMM_MIRROR) -bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range); -struct hmm_range *amdgpu_hmm_range_alloc(void); -void amdgpu_hmm_range_free(struct hmm_range *hmm_range); int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr); void amdgpu_hmm_unregister(struct amdgpu_bo *bo); #else @@ -101,20 +99,7 @@ static inline int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) "add CONFIG_ZONE_DEVICE=y in config file to fix this\n"); return -ENODEV; } - static inline void amdgpu_hmm_unregister(struct amdgpu_bo *bo) {} - -static inline bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range) -{ - return false; -} - -static inline struct hmm_range *amdgpu_hmm_range_alloc(void) -{ - return NULL; -} - -static inline void amdgpu_hmm_range_free(struct hmm_range *hmm_range) {} #endif #endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 205b70ebfb19f..6b129b9de809c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -826,6 +826,44 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, return r; } +/* amdgpu_ttm_tt_discard_user_pages - Discard range and pfn array allocations + */ +void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, + struct hmm_range *range) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + + if (gtt && gtt->userptr && range) + amdgpu_hmm_range_get_pages_done(range); +} + +/* + * amdgpu_ttm_tt_get_user_pages_done - stop HMM track the CPU page table change + * Check if the pages backing this ttm range have been invalidated + * + * Returns: true if pages are still valid + */ +bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, + struct hmm_range *range) +{ + struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); + + if (!gtt || !gtt->userptr || !range) + return false; + + DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", + gtt->userptr, ttm->num_pages); + +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + WARN_ONCE(!range->pfns, +#else + WARN_ONCE(!range->hmm_pfns, +#endif + "No user pages to check\n"); + + return !amdgpu_hmm_range_get_pages_done(range); +} + #else /* * amdgpu_ttm_tt_get_user_pages - Pin pages of memory pointed to by a USERPTR diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 27dd8129cd565..a042b8c446b4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -205,6 +205,10 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, struct hmm_range **range); #endif +void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, + struct hmm_range *range); +bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, + struct hmm_range *range); #else #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, @@ -219,6 +223,15 @@ static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page return -EPERM; } #endif +static inline void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, + struct hmm_range *range) +{ +} +static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, + struct hmm_range *range) +{ + return false; +} #endif #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 5639a51212e05..5492b0e74260f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1741,13 +1741,13 @@ static int svm_range_validate_and_map(struct mm_struct *mm, } WRITE_ONCE(p->svms.faulting_task, current); - hmm_range = amdgpu_hmm_range_alloc(); + hmm_range = kzalloc(sizeof(*hmm_range), GFP_KERNEL); r = amdgpu_hmm_range_get_pages(&prange->notifier, addr, npages, readonly, owner, hmm_range); WRITE_ONCE(p->svms.faulting_task, NULL); if (r) { - amdgpu_hmm_range_free(hmm_range); + kfree(hmm_range); pr_debug("failed %d to get svm range pages\n", r); } } else { @@ -1768,13 +1768,10 @@ static int svm_range_validate_and_map(struct mm_struct *mm, * Overrride return value to TRY AGAIN only if prior returns * were successful */ - if (hmm_range && !amdgpu_hmm_range_valid(hmm_range) && !r) { + if (hmm_range && amdgpu_hmm_range_get_pages_done(hmm_range) && !r) { pr_debug("hmm update the range, need validate again\n"); r = -EAGAIN; } - /* Free the hmm range */ - amdgpu_hmm_range_free(hmm_range); - if (!r && !list_empty(&prange->child_list)) { pr_debug("range split by unmap in parallel, validate again\n"); From e1022f76e20a4d3dc0044636f6d233a6de2b0320 Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Fri, 28 Mar 2025 12:10:33 -0400 Subject: [PATCH 2322/2653] drm/amdkcl: Add Peerdirect checks for KFD Certain kernels may have integrated peer_mem into their base Linux module, while others may have it as a separate module. Link against the ofa_kernel as a last resort in case that's the only option available. Some older NICs can't support dma_buf, so this is required in order to get PeerDirect to work on NICs that don't support dma_buf Signed-off-by: Kent Russell Reviewed-by: Perry Yuan --- drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 13 ++++++--- drivers/gpu/drm/amd/dkms/Kbuild | 9 ++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 | 31 +++++++++++++++++++++ 5 files changed, 53 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index f7cd9661d5047..cd75d2432a9f8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -86,7 +86,6 @@ */ #define IB_PEER_MEMORY_NAME_MAX 64 #define IB_PEER_MEMORY_VER_MAX 16 - struct peer_memory_client { char name[IB_PEER_MEMORY_NAME_MAX]; char version[IB_PEER_MEMORY_VER_MAX]; @@ -117,7 +116,6 @@ void *ib_register_peer_memory_client(struct peer_memory_client *peer_client, invalidate_peer_memory *invalidate_callback); void ib_unregister_peer_memory_client(void *reg_handle); - /*------------------- PeerDirect bridge driver ------------------------------*/ #define AMD_PEER_BRIDGE_DRIVER_VERSION "1.0" @@ -465,6 +463,10 @@ void kfd_init_peer_direct(void) pr_debug("Try to initialize PeerDirect support\n"); +#if defined(HAVE_KFD_PEERDIRECT_SUPPORT) + pfn_ib_register_peer_memory_client = ib_register_peer_memory_client; + pfn_ib_unregister_peer_memory_client = ib_unregister_peer_memory_client; +#else pfn_ib_register_peer_memory_client = (void *(*)(struct peer_memory_client *, invalidate_peer_memory *)) @@ -473,6 +475,7 @@ void kfd_init_peer_direct(void) pfn_ib_unregister_peer_memory_client = (void (*)(void *)) symbol_request(ib_unregister_peer_memory_client); +#endif if (!pfn_ib_register_peer_memory_client || !pfn_ib_unregister_peer_memory_client) { pr_debug("PeerDirect interface was not detected\n"); @@ -505,13 +508,15 @@ void kfd_close_peer_direct(void) if (pfn_ib_unregister_peer_memory_client) { if (ib_reg_handle) pfn_ib_unregister_peer_memory_client(ib_reg_handle); - +#if !defined(HAVE_KFD_PEERDIRECT_SUPPORT) symbol_put(ib_unregister_peer_memory_client); +#endif } +#if !defined(HAVE_KFD_PEERDIRECT_SUPPORT) if (pfn_ib_register_peer_memory_client) symbol_put(ib_register_peer_memory_client); - +#endif /* Reset pointers to be safe */ pfn_ib_unregister_peer_memory_client = NULL; diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild index 02fb141c1d995..96a6424ce8378 100644 --- a/drivers/gpu/drm/amd/dkms/Kbuild +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -32,6 +32,15 @@ LINUX_SRCTREE_INCLUDE := \ $(filter-out -I%/uapi "-include %/kconfig.h",$(_KCL_LINUXINCLUDE)) USER_INCLUDE := $(filter-out $(LINUX_SRCTREE_INCLUDE), $(_KCL_LINUXINCLUDE)) +# In the peerdirect m4, we determine if the p2p symbols are in the ofa_kernel's Module.symvers +# If so, we need to include the path for the function pointers, as well as the include path for +# rdma/peer_mem.h, since the ofa_kernel isn't integrated into the base kernel in that configuration +_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") +ifeq ($(call _is_kcl_macro_defined,HAVE_KFD_PEERDIRECT_SUPPORT_NEED_OFAPATH),y) +KBUILD_EXTRA_SYMBOLS += /usr/src/ofa_kernel/x86_64/$(KERNELRELEASE)/Module.symvers +USER_INCLUDE += -I/usr/src/ofa_kernel/x86_64/$(KERNELRELEASE)/include +endif + LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/kcl/header \ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index fea8ce89b8f46..ff5f22fac2d20 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -862,6 +862,9 @@ /* kernel_write() take arg type of position as pointer */ #define HAVE_KERNEL_WRITE_PPOS 1 +/* HAVE_KFD_PEERDIRECT_SUPPORT is available */ +/* #undef HAVE_KFD_PEERDIRECT_SUPPORT */ + /* kfifo_out_linear() available */ #define HAVE_KFIFO_OUT_LINEAR 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 28aa0921c254c..98df10ba8eee7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -302,6 +302,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LIST_IS_HEAD AC_AMDGPU_DEVM_I2C_ADD_ADAPTER AC_AMDGPU_MEMPOOL_ALLOC_PREALLOCATED + AC_AMDGPU_KFD_PEERDIRECT_SUPPORT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 b/drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 new file mode 100644 index 0000000000000..6447b6c16afac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 @@ -0,0 +1,31 @@ +dnl # +dnl # +dnl # PEER DIRECT support +dnl # +dnl # Note that some kernels will have rdma/peer_mem.h and general P2P +dnl # support included. We should check for that case first. If so, we +dnl # set p2p support to 1. +dnl # If the system uses the ofa_kernel, which is present outside of the +dnl # base kernel, then check if it exists and has a p2p symbol present. +dnl # If so, we set p2p support to 1, but also require setting the path +dnl # to the ofa_kernel, which is checked in Kbuild. +dnl # This way we can support configs that have p2p integrated into the +dnl # base kernel, or configs using the ofa_kernel +AC_DEFUN([AC_AMDGPU_KFD_PEERDIRECT_SUPPORT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct peer_memory_client client; + ib_register_peer_memory_client(&client, NULL); + ], [ + AC_DEFINE(HAVE_KFD_PEERDIRECT_SUPPORT, 1, [HAVE_KFD_PEERDIRECT_SUPPORT is available]) + ], [ + AS_IF([ grep -qw ib_register_peer_memory_client /usr/src/ofa_kernel/x86_64/${KERNELVER}/Module.symvers ], [ + AC_DEFINE(HAVE_KFD_PEERDIRECT_SUPPORT, 1, [HAVE_KFD_PEERDIRECT_SUPPORT is available]) + AC_DEFINE(HAVE_KFD_PEERDIRECT_SUPPORT_NEED_OFAPATH, 1, [HAVE_KFD_PEERDIRECT_SUPPORT is available and needs OFA path]) + ]) + ]) + ]) +]) + From b513dd510ec8514ceb3b56f4b48f5b3389227e3c Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Thu, 11 Sep 2025 12:41:42 +0100 Subject: [PATCH 2323/2653] drm/amdgpu: More compact VCN IB emission Avoid constant register reloads while emitting IBs by using a local write pointer and only updating the size at the end of each helper. Signed-off-by: Tvrtko Ursulin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 101 +++++++++++++----------- 1 file changed, 55 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 5ae7cc0d5f57a..78c9e6b293892 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -760,16 +760,19 @@ static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib, uint32_t ib_pack_in_dw, bool enc) { uint32_t *ib_checksum; + u32 *ptr = &ib->ptr[ib->length_dw]; - ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */ - ib->ptr[ib->length_dw++] = 0x30000002; - ib_checksum = &ib->ptr[ib->length_dw++]; - ib->ptr[ib->length_dw++] = ib_pack_in_dw; + *ptr++ = 0x00000010; /* single queue checksum */ + *ptr++ = 0x30000002; + ib_checksum = ptr++; + *ptr++ = ib_pack_in_dw; - ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */ - ib->ptr[ib->length_dw++] = 0x30000001; - ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3; - ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t); + *ptr++ = 0x00000010; /* engine info */ + *ptr++ = 0x30000001; + *ptr++ = enc ? 0x2 : 0x3; + *ptr++ = ib_pack_in_dw * sizeof(uint32_t); + + ib->length_dw = ptr - ib->ptr; return ib_checksum; } @@ -799,6 +802,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); uint32_t *ib_checksum; uint32_t ib_pack_in_dw; + u32 *ptr; int i, r; if (adev->vcn.inst[ring->me].using_unified_queue) @@ -811,7 +815,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, goto err; ib = &job->ibs[0]; - ib->length_dw = 0; + ptr = ib->ptr; /* single queue headers */ if (adev->vcn.inst[ring->me].using_unified_queue) { @@ -820,10 +824,11 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false); } - ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; - ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); - decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); - ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; + *ptr++ = sizeof(struct amdgpu_vcn_decode_buffer) + 8; + *ptr++ = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); + decode_buffer = (struct amdgpu_vcn_decode_buffer *)ptr; + ib->length_dw = ptr - ib->ptr + + sizeof(struct amdgpu_vcn_decode_buffer) / 4; memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); @@ -831,7 +836,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); for (i = ib->length_dw; i < ib_size_dw; ++i) - ib->ptr[i] = 0x0; + *ptr++ = 0x0; if (adev->vcn.inst[ring->me].using_unified_queue) amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw); @@ -929,6 +934,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand struct dma_fence *f = NULL; uint32_t *ib_checksum = NULL; uint64_t addr; + u32 *ptr; int i, r; if (adev->vcn.inst[ring->me].using_unified_queue) @@ -941,31 +947,32 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand return r; ib = &job->ibs[0]; + ptr = ib->ptr; addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); - ib->length_dw = 0; - if (adev->vcn.inst[ring->me].using_unified_queue) ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); - ib->ptr[ib->length_dw++] = 0x00000018; - ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ - ib->ptr[ib->length_dw++] = handle; - ib->ptr[ib->length_dw++] = upper_32_bits(addr); - ib->ptr[ib->length_dw++] = addr; - ib->ptr[ib->length_dw++] = 0x00000000; + *ptr++ = 0x00000018; + *ptr++ = 0x00000001; /* session info */ + *ptr++ = handle; + *ptr++ = upper_32_bits(addr); + *ptr++ = addr; + *ptr++ = 0x00000000; + + *ptr++ = 0x00000014; + *ptr++ = 0x00000002; /* task info */ + *ptr++ = 0x0000001c; + *ptr++ = 0x00000000; + *ptr++ = 0x00000000; - ib->ptr[ib->length_dw++] = 0x00000014; - ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ - ib->ptr[ib->length_dw++] = 0x0000001c; - ib->ptr[ib->length_dw++] = 0x00000000; - ib->ptr[ib->length_dw++] = 0x00000000; + *ptr++ = 0x00000008; + *ptr++ = 0x08000001; /* op initialize */ - ib->ptr[ib->length_dw++] = 0x00000008; - ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ + ib->length_dw = ptr - ib->ptr; for (i = ib->length_dw; i < ib_size_dw; ++i) - ib->ptr[i] = 0x0; + *ptr++ = 0x0; if (adev->vcn.inst[ring->me].using_unified_queue) amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); @@ -996,6 +1003,7 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han struct dma_fence *f = NULL; uint32_t *ib_checksum = NULL; uint64_t addr; + u32 *ptr; int i, r; if (adev->vcn.inst[ring->me].using_unified_queue) @@ -1008,31 +1016,32 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han return r; ib = &job->ibs[0]; + ptr = ib->ptr; addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); - ib->length_dw = 0; - if (adev->vcn.inst[ring->me].using_unified_queue) ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); - ib->ptr[ib->length_dw++] = 0x00000018; - ib->ptr[ib->length_dw++] = 0x00000001; - ib->ptr[ib->length_dw++] = handle; - ib->ptr[ib->length_dw++] = upper_32_bits(addr); - ib->ptr[ib->length_dw++] = addr; - ib->ptr[ib->length_dw++] = 0x00000000; + *ptr++ = 0x00000018; + *ptr++ = 0x00000001; + *ptr++ = handle; + *ptr++ = upper_32_bits(addr); + *ptr++ = addr; + *ptr++ = 0x00000000; + + *ptr++ = 0x00000014; + *ptr++ = 0x00000002; + *ptr++ = 0x0000001c; + *ptr++ = 0x00000000; + *ptr++ = 0x00000000; - ib->ptr[ib->length_dw++] = 0x00000014; - ib->ptr[ib->length_dw++] = 0x00000002; - ib->ptr[ib->length_dw++] = 0x0000001c; - ib->ptr[ib->length_dw++] = 0x00000000; - ib->ptr[ib->length_dw++] = 0x00000000; + *ptr++ = 0x00000008; + *ptr++ = 0x08000002; /* op close session */ - ib->ptr[ib->length_dw++] = 0x00000008; - ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ + ib->length_dw = ptr - ib->ptr; for (i = ib->length_dw; i < ib_size_dw; ++i) - ib->ptr[i] = 0x0; + *ptr++ = 0x0; if (adev->vcn.inst[ring->me].using_unified_queue) amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); From 58ec3e38ba36ca3d6471fce7343f644e0ef3f91c Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Thu, 11 Sep 2025 12:41:43 +0100 Subject: [PATCH 2324/2653] drm/amdgpu: More compact UVD 6 IB emission Avoid constant register reloads while emitting IBs by using a local write pointer and only updating the size at the end of each helper.uvd 6 Signed-off-by: Tvrtko Ursulin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 66 +++++++++++++++------------ 1 file changed, 36 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 1c07b701d0e4f..edbdb44ac1f87 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -214,6 +214,7 @@ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle struct amdgpu_ib *ib; struct dma_fence *f = NULL; uint64_t addr; + u32 *ptr; int i, r; r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, @@ -222,27 +223,29 @@ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle return r; ib = &job->ibs[0]; + ptr = ib->ptr; addr = amdgpu_bo_gpu_offset(bo); - ib->length_dw = 0; - ib->ptr[ib->length_dw++] = 0x00000018; - ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ - ib->ptr[ib->length_dw++] = handle; - ib->ptr[ib->length_dw++] = 0x00010000; - ib->ptr[ib->length_dw++] = upper_32_bits(addr); - ib->ptr[ib->length_dw++] = addr; + *ptr++ = 0x00000018; + *ptr++ = 0x00000001; /* session info */ + *ptr++ = handle; + *ptr++ = 0x00010000; + *ptr++ = upper_32_bits(addr); + *ptr++ = addr; - ib->ptr[ib->length_dw++] = 0x00000014; - ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ - ib->ptr[ib->length_dw++] = 0x0000001c; - ib->ptr[ib->length_dw++] = 0x00000001; - ib->ptr[ib->length_dw++] = 0x00000000; + *ptr++ = 0x00000014; + *ptr++ = 0x00000002; /* task info */ + *ptr++ = 0x0000001c; + *ptr++ = 0x00000001; + *ptr++ = 0x00000000; - ib->ptr[ib->length_dw++] = 0x00000008; - ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ + *ptr++ = 0x00000008; + *ptr++ = 0x08000001; /* op initialize */ + + ib->length_dw = ptr - ib->ptr; for (i = ib->length_dw; i < ib_size_dw; ++i) - ib->ptr[i] = 0x0; + *ptr++ = 0x0; r = amdgpu_job_submit_direct(job, ring, &f); if (r) @@ -278,6 +281,7 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring, struct amdgpu_ib *ib; struct dma_fence *f = NULL; uint64_t addr; + u32 *ptr; int i, r; r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, @@ -286,27 +290,29 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring, return r; ib = &job->ibs[0]; + ptr = ib->ptr; addr = amdgpu_bo_gpu_offset(bo); - ib->length_dw = 0; - ib->ptr[ib->length_dw++] = 0x00000018; - ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ - ib->ptr[ib->length_dw++] = handle; - ib->ptr[ib->length_dw++] = 0x00010000; - ib->ptr[ib->length_dw++] = upper_32_bits(addr); - ib->ptr[ib->length_dw++] = addr; + *ptr++ = 0x00000018; + *ptr++ = 0x00000001; /* session info */ + *ptr++ = handle; + *ptr++ = 0x00010000; + *ptr++ = upper_32_bits(addr); + *ptr++ = addr; + + *ptr++ = 0x00000014; + *ptr++ = 0x00000002; /* task info */ + *ptr++ = 0x0000001c; + *ptr++ = 0x00000001; + *ptr++ = 0x00000000; - ib->ptr[ib->length_dw++] = 0x00000014; - ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ - ib->ptr[ib->length_dw++] = 0x0000001c; - ib->ptr[ib->length_dw++] = 0x00000001; - ib->ptr[ib->length_dw++] = 0x00000000; + *ptr++ = 0x00000008; + *ptr++ = 0x08000002; /* op close session */ - ib->ptr[ib->length_dw++] = 0x00000008; - ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ + ib->length_dw = ptr - ib->ptr; for (i = ib->length_dw; i < ib_size_dw; ++i) - ib->ptr[i] = 0x0; + *ptr++ = 0x0; r = amdgpu_job_submit_direct(job, ring, &f); if (r) From 3ae4b4a4eceeeef7203772e9813ac3110decfb2d Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Thu, 11 Sep 2025 12:41:44 +0100 Subject: [PATCH 2325/2653] drm/amdgpu: More compact UVD 7 IB emission Avoid constant register reloads while emitting IBs by using a local write pointer and only updating the size at the end of each helper. Signed-off-by: Tvrtko Ursulin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 66 +++++++++++++++------------ 1 file changed, 36 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 9d237b5937fb0..5634c587c97f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -222,6 +222,7 @@ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, u32 handle, struct amdgpu_ib *ib; struct dma_fence *f = NULL; uint64_t addr; + u32 *ptr; int i, r; r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, @@ -230,27 +231,29 @@ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, u32 handle, return r; ib = &job->ibs[0]; + ptr = ib->ptr; addr = amdgpu_bo_gpu_offset(bo); - ib->length_dw = 0; - ib->ptr[ib->length_dw++] = 0x00000018; - ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ - ib->ptr[ib->length_dw++] = handle; - ib->ptr[ib->length_dw++] = 0x00000000; - ib->ptr[ib->length_dw++] = upper_32_bits(addr); - ib->ptr[ib->length_dw++] = addr; + *ptr++ = 0x00000018; + *ptr++ = 0x00000001; /* session info */ + *ptr++ = handle; + *ptr++ = 0x00000000; + *ptr++ = upper_32_bits(addr); + *ptr++ = addr; - ib->ptr[ib->length_dw++] = 0x00000014; - ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ - ib->ptr[ib->length_dw++] = 0x0000001c; - ib->ptr[ib->length_dw++] = 0x00000000; - ib->ptr[ib->length_dw++] = 0x00000000; + *ptr++ = 0x00000014; + *ptr++ = 0x00000002; /* task info */ + *ptr++ = 0x0000001c; + *ptr++ = 0x00000000; + *ptr++ = 0x00000000; - ib->ptr[ib->length_dw++] = 0x00000008; - ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ + *ptr++ = 0x00000008; + *ptr++ = 0x08000001; /* op initialize */ + + ib->length_dw = ptr - ib->ptr; for (i = ib->length_dw; i < ib_size_dw; ++i) - ib->ptr[i] = 0x0; + *ptr++ = 0x0; r = amdgpu_job_submit_direct(job, ring, &f); if (r) @@ -285,6 +288,7 @@ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, u32 handle, struct amdgpu_ib *ib; struct dma_fence *f = NULL; uint64_t addr; + u32 *ptr; int i, r; r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, @@ -293,27 +297,29 @@ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, u32 handle, return r; ib = &job->ibs[0]; + ptr = ib->ptr; addr = amdgpu_bo_gpu_offset(bo); - ib->length_dw = 0; - ib->ptr[ib->length_dw++] = 0x00000018; - ib->ptr[ib->length_dw++] = 0x00000001; - ib->ptr[ib->length_dw++] = handle; - ib->ptr[ib->length_dw++] = 0x00000000; - ib->ptr[ib->length_dw++] = upper_32_bits(addr); - ib->ptr[ib->length_dw++] = addr; + *ptr++ = 0x00000018; + *ptr++ = 0x00000001; + *ptr++ = handle; + *ptr++ = 0x00000000; + *ptr++ = upper_32_bits(addr); + *ptr++ = addr; + + *ptr++ = 0x00000014; + *ptr++ = 0x00000002; + *ptr++ = 0x0000001c; + *ptr++ = 0x00000000; + *ptr++ = 0x00000000; - ib->ptr[ib->length_dw++] = 0x00000014; - ib->ptr[ib->length_dw++] = 0x00000002; - ib->ptr[ib->length_dw++] = 0x0000001c; - ib->ptr[ib->length_dw++] = 0x00000000; - ib->ptr[ib->length_dw++] = 0x00000000; + *ptr++ = 0x00000008; + *ptr++ = 0x08000002; /* op close session */ - ib->ptr[ib->length_dw++] = 0x00000008; - ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ + ib->length_dw = ptr - ib->ptr; for (i = ib->length_dw; i < ib_size_dw; ++i) - ib->ptr[i] = 0x0; + *ptr++ = 0x0; r = amdgpu_job_submit_direct(job, ring, &f); if (r) From b5f687a8d08ff6acbac35dc014ddb87cc316ea86 Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Fri, 28 Mar 2025 10:34:57 +0800 Subject: [PATCH 2326/2653] drm/amd/display: pause the workload setting in dm v1: Pause the workload setting in dm when doinn idle optimization v2: Rebase patch to latest kernel code base (kernel 6.16) Reviewed-by: Alex Deucher Signed-off-by: Kenneth Feng Signed-off-by: Alex Deucher Signed-off-by: Yang Wang --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 0aafee3f8f20b..914a1781ad38e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -248,6 +248,8 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work) struct vblank_control_work *vblank_work = container_of(work, struct vblank_control_work, work); struct amdgpu_display_manager *dm = vblank_work->dm; + struct amdgpu_device *adev = drm_to_adev(dm->ddev); + int r; mutex_lock(&dm->dc_lock); @@ -277,7 +279,16 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work) if (dm->active_vblank_irq_count == 0) { dc_post_update_surfaces_to_stream(dm->dc); + + r = amdgpu_dpm_pause_power_profile(adev, true); + if (r) + dev_warn(adev->dev, "failed to set default power profile mode\n"); + dc_allow_idle_optimizations(dm->dc, true); + + r = amdgpu_dpm_pause_power_profile(adev, false); + if (r) + dev_warn(adev->dev, "failed to restore the power profile mode\n"); } mutex_unlock(&dm->dc_lock); From 186219d755c9c57db92cf92f9ac6d0a034349777 Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Thu, 11 Sep 2025 12:41:45 +0100 Subject: [PATCH 2327/2653] drm/amdgpu: More compact SI SDMA emission Avoid constant register reloads while emitting IBs by using a local write pointer and only updating the size at the end of each helper. Signed-off-by: Tvrtko Ursulin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/si_dma.c | 84 +++++++++++++++++------------ 1 file changed, 51 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 7f18e4875287c..9e26c7598d74b 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -323,14 +323,16 @@ static void si_dma_vm_copy_pte(struct amdgpu_ib *ib, uint64_t pe, uint64_t src, unsigned count) { + u32 *ptr = &ib->ptr[ib->length_dw]; unsigned bytes = count * 8; - ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, - 1, 0, 0, bytes); - ib->ptr[ib->length_dw++] = lower_32_bits(pe); - ib->ptr[ib->length_dw++] = lower_32_bits(src); - ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; - ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; + *ptr++ = DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, bytes); + *ptr++ = lower_32_bits(pe); + *ptr++ = lower_32_bits(src); + *ptr++ = upper_32_bits(pe) & 0xff; + *ptr++ = upper_32_bits(src) & 0xff; + + ib->length_dw = ptr - ib->ptr; } /** @@ -348,16 +350,19 @@ static void si_dma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, uint64_t value, unsigned count, uint32_t incr) { + u32 *ptr = &ib->ptr[ib->length_dw]; unsigned ndw = count * 2; - ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw); - ib->ptr[ib->length_dw++] = lower_32_bits(pe); - ib->ptr[ib->length_dw++] = upper_32_bits(pe); + *ptr++ = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw); + *ptr++ = lower_32_bits(pe); + *ptr++ = upper_32_bits(pe); for (; ndw > 0; ndw -= 2) { - ib->ptr[ib->length_dw++] = lower_32_bits(value); - ib->ptr[ib->length_dw++] = upper_32_bits(value); + *ptr++ = lower_32_bits(value); + *ptr++ = upper_32_bits(value); value += incr; } + + ib->length_dw = ptr - ib->ptr; } /** @@ -377,6 +382,7 @@ static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t addr, unsigned count, uint32_t incr, uint64_t flags) { + u32 *ptr = &ib->ptr[ib->length_dw]; uint64_t value; unsigned ndw; @@ -391,19 +397,21 @@ static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib, value = 0; /* for physically contiguous pages (vram) */ - ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw); - ib->ptr[ib->length_dw++] = pe; /* dst addr */ - ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; - ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ - ib->ptr[ib->length_dw++] = upper_32_bits(flags); - ib->ptr[ib->length_dw++] = value; /* value */ - ib->ptr[ib->length_dw++] = upper_32_bits(value); - ib->ptr[ib->length_dw++] = incr; /* increment size */ - ib->ptr[ib->length_dw++] = 0; + *ptr++ = DMA_PTE_PDE_PACKET(ndw); + *ptr++ = pe; /* dst addr */ + *ptr++ = upper_32_bits(pe) & 0xff; + *ptr++ = lower_32_bits(flags); /* mask */ + *ptr++ = upper_32_bits(flags); + *ptr++ = value; /* value */ + *ptr++ = upper_32_bits(value); + *ptr++ = incr; /* increment size */ + *ptr++ = 0; pe += ndw * 4; addr += (ndw / 2) * incr; count -= ndw / 2; } + + ib->length_dw = ptr - ib->ptr; } /** @@ -415,8 +423,12 @@ static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib, */ static void si_dma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) { - while (ib->length_dw & 0x7) - ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0); + int pad = 8 - (ib->length_dw & 0x7); + + if (pad && pad < 8) { + memset32(ib->ptr, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), pad); + ib->length_dw += pad; + } } /** @@ -783,12 +795,15 @@ static void si_dma_emit_copy_buffer(struct amdgpu_ib *ib, uint32_t byte_count, uint32_t copy_flags) { - ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, - 1, 0, 0, byte_count); - ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); - ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); - ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) & 0xff; - ib->ptr[ib->length_dw++] = upper_32_bits(src_offset) & 0xff; + u32 *ptr = &ib->ptr[ib->length_dw]; + + *ptr++ = DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, byte_count); + *ptr++ = lower_32_bits(dst_offset); + *ptr++ = lower_32_bits(src_offset); + *ptr++ = upper_32_bits(dst_offset) & 0xff; + *ptr++ = upper_32_bits(src_offset) & 0xff; + + ib->length_dw = ptr - ib->ptr; } /** @@ -806,11 +821,14 @@ static void si_dma_emit_fill_buffer(struct amdgpu_ib *ib, uint64_t dst_offset, uint32_t byte_count) { - ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_CONSTANT_FILL, - 0, 0, 0, byte_count / 4); - ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); - ib->ptr[ib->length_dw++] = src_data; - ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) << 16; + u32 *ptr = &ib->ptr[ib->length_dw]; + + *ptr++ = DMA_PACKET(DMA_PACKET_CONSTANT_FILL, 0, 0, 0, byte_count / 4); + *ptr++ = lower_32_bits(dst_offset); + *ptr++ = src_data; + *ptr++ = upper_32_bits(dst_offset) << 16; + + ib->length_dw = ptr - ib->ptr; } From 54ef43ea7a414df4879b1dd7602af8784b3c896d Mon Sep 17 00:00:00 2001 From: Jinzhou Su Date: Wed, 15 Oct 2025 09:39:44 +0800 Subject: [PATCH 2328/2653] drm/amdgpu: clear bad page info of ras module Clear bad page info of ras module. Signed-off-by: Jinzhou Su Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index a0d92e2266699..214f581ab4766 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -612,6 +612,8 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, return size; } +static int amdgpu_uniras_clear_badpages_info(struct amdgpu_device *adev); + /** * DOC: AMDGPU RAS debugfs EEPROM table reset interface * @@ -636,6 +638,11 @@ static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, (struct amdgpu_device *)file_inode(f)->i_private; int ret; + if (amdgpu_uniras_enabled(adev)) { + ret = amdgpu_uniras_clear_badpages_info(adev); + return ret ? ret : size; + } + ret = amdgpu_ras_eeprom_reset_table( &(amdgpu_ras_get_context(adev)->eeprom_control)); @@ -1543,6 +1550,21 @@ static int amdgpu_ras_query_error_status_with_event(struct amdgpu_device *adev, return ret; } +static int amdgpu_uniras_clear_badpages_info(struct amdgpu_device *adev) +{ + struct ras_cmd_dev_handle req = {0}; + int ret; + + ret = amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__CLEAR_BAD_PAGE_INFO, + &req, sizeof(req), NULL, 0); + if (ret) { + dev_err(adev->dev, "Failed to clear bad pages info, ret: %d\n", ret); + return ret; + } + + return 0; +} + static int amdgpu_uniras_query_block_ecc(struct amdgpu_device *adev, struct ras_query_if *info) { From 4aaad8da267572e1dfee45dc54cd70bd17fe433d Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Thu, 11 Sep 2025 12:41:46 +0100 Subject: [PATCH 2329/2653] drm/amdgpu: More compact CIK SDMA IB emission Avoid constant register reloads while emitting IBs by using a local write pointer and only updating the size at the end of each helper. Signed-off-by: Tvrtko Ursulin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 105 +++++++++++++++----------- 1 file changed, 63 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 9e8715b4739da..bf3049200fcdd 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -718,16 +718,18 @@ static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib, uint64_t pe, uint64_t src, unsigned count) { + u32 *ptr = &ib->ptr[ib->length_dw]; unsigned bytes = count * 8; - ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, - SDMA_WRITE_SUB_OPCODE_LINEAR, 0); - ib->ptr[ib->length_dw++] = bytes; - ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ - ib->ptr[ib->length_dw++] = lower_32_bits(src); - ib->ptr[ib->length_dw++] = upper_32_bits(src); - ib->ptr[ib->length_dw++] = lower_32_bits(pe); - ib->ptr[ib->length_dw++] = upper_32_bits(pe); + *ptr++ = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); + *ptr++ = bytes; + *ptr++ = 0; /* src/dst endian swap */ + *ptr++ = lower_32_bits(src); + *ptr++ = upper_32_bits(src); + *ptr++ = lower_32_bits(pe); + *ptr++ = upper_32_bits(pe); + + ib->length_dw = ptr - ib->ptr; } /** @@ -745,18 +747,21 @@ static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, uint64_t value, unsigned count, uint32_t incr) { + u32 *ptr = &ib->ptr[ib->length_dw]; unsigned ndw = count * 2; - ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, - SDMA_WRITE_SUB_OPCODE_LINEAR, 0); - ib->ptr[ib->length_dw++] = lower_32_bits(pe); - ib->ptr[ib->length_dw++] = upper_32_bits(pe); - ib->ptr[ib->length_dw++] = ndw; + *ptr++ = SDMA_PACKET(SDMA_OPCODE_WRITE, + SDMA_WRITE_SUB_OPCODE_LINEAR, 0); + *ptr++ = lower_32_bits(pe); + *ptr++ = upper_32_bits(pe); + *ptr++ = ndw; for (; ndw > 0; ndw -= 2) { - ib->ptr[ib->length_dw++] = lower_32_bits(value); - ib->ptr[ib->length_dw++] = upper_32_bits(value); + *ptr++ = lower_32_bits(value); + *ptr++ = upper_32_bits(value); value += incr; } + + ib->length_dw = ptr - ib->ptr; } /** @@ -775,17 +780,21 @@ static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint64_t flags) { + u32 *ptr = &ib->ptr[ib->length_dw]; + /* for physically contiguous pages (vram) */ - ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); - ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ - ib->ptr[ib->length_dw++] = upper_32_bits(pe); - ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ - ib->ptr[ib->length_dw++] = upper_32_bits(flags); - ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ - ib->ptr[ib->length_dw++] = upper_32_bits(addr); - ib->ptr[ib->length_dw++] = incr; /* increment size */ - ib->ptr[ib->length_dw++] = 0; - ib->ptr[ib->length_dw++] = count; /* number of entries */ + *ptr++ = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); + *ptr++ = lower_32_bits(pe); /* dst addr */ + *ptr++ = upper_32_bits(pe); + *ptr++ = lower_32_bits(flags); /* mask */ + *ptr++ = upper_32_bits(flags); + *ptr++ = lower_32_bits(addr); /* value */ + *ptr++ = upper_32_bits(addr); + *ptr++ = incr; /* increment size */ + *ptr++ = 0; + *ptr++ = count; /* number of entries */ + + ib->length_dw = ptr - ib->ptr; } /** @@ -798,18 +807,22 @@ static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) { struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); + u32 *ptr = &ib->ptr[ib->length_dw]; u32 pad_count; int i; pad_count = (-ib->length_dw) & 7; + if (!pad_count) + return; + for (i = 0; i < pad_count; i++) if (sdma && sdma->burst_nop && (i == 0)) - ib->ptr[ib->length_dw++] = - SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) | - SDMA_NOP_COUNT(pad_count - 1); + *ptr++ = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) | + SDMA_NOP_COUNT(pad_count - 1); else - ib->ptr[ib->length_dw++] = - SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); + *ptr++ = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); + + ib->length_dw += pad_count; } /** @@ -1290,13 +1303,17 @@ static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib, uint32_t byte_count, uint32_t copy_flags) { - ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); - ib->ptr[ib->length_dw++] = byte_count; - ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ - ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); - ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); - ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); - ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); + u32 *ptr = &ib->ptr[ib->length_dw]; + + *ptr++ = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); + *ptr++ = byte_count; + *ptr++ = 0; /* src/dst endian swap */ + *ptr++ = lower_32_bits(src_offset); + *ptr++ = upper_32_bits(src_offset); + *ptr++ = lower_32_bits(dst_offset); + *ptr++ = upper_32_bits(dst_offset); + + ib->length_dw = ptr - ib->ptr; } /** @@ -1314,11 +1331,15 @@ static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib, uint64_t dst_offset, uint32_t byte_count) { - ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0); - ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); - ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); - ib->ptr[ib->length_dw++] = src_data; - ib->ptr[ib->length_dw++] = byte_count; + u32 *ptr = &ib->ptr[ib->length_dw]; + + *ptr++ = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0); + *ptr++ = lower_32_bits(dst_offset); + *ptr++ = upper_32_bits(dst_offset); + *ptr++ = src_data; + *ptr++ = byte_count; + + ib->length_dw = ptr - ib->ptr; } static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = { From e3a09bd62fa321e046685812883bd6b5f3446524 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 14 Oct 2025 15:05:19 +0800 Subject: [PATCH 2330/2653] drm/amdgpu: get rev_id from strap register or IP-discovery table Query the sub-revision field in the IP Discovery table for the VFs to obtain their revision ID. Meanwhile, read the revision ID from the strap register for the PF. Signed-off-by: Perry Yuan Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c | 24 +++++++++++++----------- 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 2041737a5fbe0..72897cf1ac818 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1841,6 +1841,10 @@ static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) && + adev->rev_id == 0x3) + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; + if (!(adev->flags & AMD_IS_APU) && !amdgpu_sriov_vf(adev)) { vram_info = RREG32(regBIF_BIOS_SCRATCH_4); adev->gmc.vram_vendor = vram_info & 0xF; diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c index 1c22bc11c1f85..bdfd2917e3cab 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c @@ -41,19 +41,21 @@ static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev) static u32 nbio_v7_9_get_rev_id(struct amdgpu_device *adev) { - u32 tmp; - - tmp = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0)); - /* If it is VF or subrevision holds a non-zero value, that should be used */ - if (tmp || amdgpu_sriov_vf(adev)) - return tmp; + u32 rev_id; - /* If discovery subrev is not updated, use register version */ - tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); - tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0, - STRAP_ATI_REV_ID_DEV0_F0); + /* + * fetch the sub-revision field from the IP-discovery table + * (returns zero if the table entry is not populated). + */ + if (amdgpu_sriov_vf(adev)) { + rev_id = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0)); + } else { + rev_id = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); + rev_id = REG_GET_FIELD(rev_id, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0, + STRAP_ATI_REV_ID_DEV0_F0); + } - return tmp; + return rev_id; } static void nbio_v7_9_mc_access_enable(struct amdgpu_device *adev, bool enable) From 8fe0074387aa77494a98afdaea71160c6f480899 Mon Sep 17 00:00:00 2001 From: Matthew Schwartz Date: Mon, 20 Oct 2025 16:09:34 -0700 Subject: [PATCH 2331/2653] drm/amd/display: Don't program BLNDGAM_MEM_PWR_FORCE when CM low-power is disabled on DCN30 Before commit 33056a97ae5e ("drm/amd/display: Remove double checks for `debug.enable_mem_low_power.bits.cm`"), dpp3_program_blnd_lut(NULL) checked the low-power debug flag before calling dpp3_power_on_blnd_lut(false). After commit 33056a97ae5e ("drm/amd/display: Remove double checks for `debug.enable_mem_low_power.bits.cm`"), dpp3_program_blnd_lut(NULL) unconditionally calls dpp3_power_on_blnd_lut(false). The BLNDGAM power helper writes BLNDGAM_MEM_PWR_FORCE when CM low-power is disabled, causing immediate SRAM power toggles instead of deferring at vupdate. This can disrupt atomic color/LUT sequencing during transitions between direct scanout and composition within gamescope's DRM backend on Steam Deck OLED. To fix this, leave the BLNDGAM power state unchanged when low-power is disabled, matching dpp3_power_on_hdr3dlut and dpp3_power_on_shaper. Cc: stable@vger.kernel.org Fixes: 33056a97ae5e ("drm/amd/display: Remove double checks for `debug.enable_mem_low_power.bits.cm`") Signed-off-by: Matthew Schwartz Reviewed-by: Harry Wentland Reviewed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c index 94d0dc3461d26..fe52df01caf7b 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c @@ -582,9 +582,6 @@ static void dpp3_power_on_blnd_lut( dpp_base->ctx->dc->optimized_required = true; dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true; } - } else { - REG_SET(CM_MEM_PWR_CTRL, 0, - BLNDGAM_MEM_PWR_FORCE, power_on == true ? 0 : 1); } } From 45b599106b6f798d7712feb21b471e5dc834d705 Mon Sep 17 00:00:00 2001 From: Jinzhou Su Date: Tue, 21 Oct 2025 09:31:11 +0800 Subject: [PATCH 2332/2653] drm/amdgpu: Add uniras version in sysfs Display uniras version in sysfs version interface when uniras enable. v2: display ras version detail info Signed-off-by: Jinzhou Su Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 32 ++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 214f581ab4766..cf2bd6c8bb590 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1954,12 +1954,42 @@ static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, return sysfs_emit(buf, "feature mask: 0x%x\n", con->features); } +static bool amdgpu_ras_get_version_info(struct amdgpu_device *adev, u32 *major, + u32 *minor, u32 *rev) +{ + int i; + + if (!adev || !major || !minor || !rev || !amdgpu_uniras_enabled(adev)) + return false; + + for (i = 0; i < adev->num_ip_blocks; i++) { + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_RAS) { + *major = adev->ip_blocks[i].version->major; + *minor = adev->ip_blocks[i].version->minor; + *rev = adev->ip_blocks[i].version->rev; + return true; + } + } + + return false; +} + static ssize_t amdgpu_ras_sysfs_version_show(struct device *dev, struct device_attribute *attr, char *buf) { struct amdgpu_ras *con = container_of(attr, struct amdgpu_ras, version_attr); - return sysfs_emit(buf, "table version: 0x%x\n", con->eeprom_control.tbl_hdr.version); + u32 major, minor, rev; + ssize_t size = 0; + + size += sysfs_emit_at(buf, size, "table version: 0x%x\n", + con->eeprom_control.tbl_hdr.version); + + if (amdgpu_ras_get_version_info(con->adev, &major, &minor, &rev)) + size += sysfs_emit_at(buf, size, "ras version: %u.%u.%u\n", + major, minor, rev); + + return size; } static ssize_t amdgpu_ras_sysfs_schema_show(struct device *dev, From 8405ba82bab9ea2c6cbc504f42d9c3567009ad16 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 14 Oct 2025 15:05:19 +0800 Subject: [PATCH 2333/2653] drm/amdgpu: get rev_id from strap register or IP-discovery table Query the sub-revision field in the IP Discovery table for the VFs to obtain their revision ID. Meanwhile, read the revision ID from the strap register for the PF. Signed-off-by: Perry Yuan Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c | 24 +++++++++++++----------- 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 2041737a5fbe0..72897cf1ac818 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1841,6 +1841,10 @@ static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) && + adev->rev_id == 0x3) + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; + if (!(adev->flags & AMD_IS_APU) && !amdgpu_sriov_vf(adev)) { vram_info = RREG32(regBIF_BIOS_SCRATCH_4); adev->gmc.vram_vendor = vram_info & 0xF; diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c index 1c22bc11c1f85..bdfd2917e3cab 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c @@ -41,19 +41,21 @@ static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev) static u32 nbio_v7_9_get_rev_id(struct amdgpu_device *adev) { - u32 tmp; - - tmp = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0)); - /* If it is VF or subrevision holds a non-zero value, that should be used */ - if (tmp || amdgpu_sriov_vf(adev)) - return tmp; + u32 rev_id; - /* If discovery subrev is not updated, use register version */ - tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); - tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0, - STRAP_ATI_REV_ID_DEV0_F0); + /* + * fetch the sub-revision field from the IP-discovery table + * (returns zero if the table entry is not populated). + */ + if (amdgpu_sriov_vf(adev)) { + rev_id = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0)); + } else { + rev_id = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); + rev_id = REG_GET_FIELD(rev_id, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0, + STRAP_ATI_REV_ID_DEV0_F0); + } - return tmp; + return rev_id; } static void nbio_v7_9_mc_access_enable(struct amdgpu_device *adev, bool enable) From febab6243e189817cbb3052900d4d7e0318228c0 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Wed, 22 Oct 2025 14:12:21 +0800 Subject: [PATCH 2334/2653] drm/amd/pm: fix smu table id bound check issue in smu_cmn_update_table() 'table_index' is a variable defined by the smu driver (kmd) 'table_id' is a variable defined by the hw smu (pmfw) This code should use table_index as a bounds check. Fixes: caad2613dc4bd ("drm/amd/powerplay: move table setting common code to smu_cmn.c") Signed-off-by: Yang Wang Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index f4d32f0c072f0..64ebda5f22a08 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -974,7 +974,7 @@ int smu_cmn_update_table(struct smu_context *smu, table_index); uint32_t table_size; int ret = 0; - if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0) + if (!table_data || table_index >= SMU_TABLE_COUNT || table_id < 0) return -EINVAL; table_size = smu_table->tables[table_index].size; From 66e919c9c297ba6b6007f0d862024e57be087262 Mon Sep 17 00:00:00 2001 From: John Smith Date: Tue, 21 Oct 2025 11:08:13 +0200 Subject: [PATCH 2335/2653] drm/amd/pm/powerplay/smumgr: Fix PCIeBootLinkLevel value on Fiji Previously this was initialized with zero which represented PCIe Gen 1.0 instead of using the maximum value from the speed table which is the behaviour of all other smumgr implementations. Fixes: 18edef19ea44 ("drm/amd/powerplay: implement fw image related smu interface for Fiji.") Signed-off-by: John Smith Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c index d2dbd90bb427e..0a876c840c79c 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c @@ -2024,7 +2024,7 @@ static int fiji_init_smc_table(struct pp_hwmgr *hwmgr) table->VoltageResponseTime = 0; table->PhaseResponseTime = 0; table->MemoryThermThrottleEnable = 1; - table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/ + table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count); table->PCIeGenInterval = 1; table->VRConfig = 0; From e1f05ce964886e7f58c381e3c872ac4613a0d429 Mon Sep 17 00:00:00 2001 From: John Smith Date: Tue, 21 Oct 2025 11:09:09 +0200 Subject: [PATCH 2336/2653] drm/amd/pm/powerplay/smumgr: Fix PCIeBootLinkLevel value on Iceland Previously this was initialized with zero which represented PCIe Gen 1.0 instead of using the maximum value from the speed table which is the behaviour of all other smumgr implementations. Fixes: 18aafc59b106 ("drm/amd/powerplay: implement fw related smu interface for iceland.") Signed-off-by: John Smith Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c index 1f50f1e74c487..aa3ae9b115c42 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c @@ -2028,7 +2028,7 @@ static int iceland_init_smc_table(struct pp_hwmgr *hwmgr) table->VoltageResponseTime = 0; table->PhaseResponseTime = 0; table->MemoryThermThrottleEnable = 1; - table->PCIeBootLinkLevel = 0; + table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count); table->PCIeGenInterval = 1; result = iceland_populate_smc_svi2_config(hwmgr, table); From 3e429e6214a3abd65b05788cdc577127e3694618 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 22 Oct 2025 14:03:24 +0300 Subject: [PATCH 2337/2653] drm/amdgpu/userqueue: Fix use after free in amdgpu_userq_buffer_vas_list_cleanup() The amdgpu_userq_buffer_va_list_del() function frees "va_cursor" but it is dereferenced on the next line when we print the debug message. Print the debug message first and then free it. Fixes: 2a28f9665dca ("drm/amdgpu: track the userq bo va for its obj management") Signed-off-by: Dan Carpenter Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index b270ec2d92130..f32004e469bb1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -158,9 +158,9 @@ static int amdgpu_userq_buffer_vas_list_cleanup(struct amdgpu_device *adev, r = -EINVAL; goto err; } - amdgpu_userq_buffer_va_list_del(mapping, va_cursor); dev_dbg(adev->dev, "delete the userq:%p va:%llx\n", queue, va_cursor->gpu_addr); + amdgpu_userq_buffer_va_list_del(mapping, va_cursor); } err: amdgpu_bo_unreserve(queue->vm->root.bo); From f7f9fa26c1db62b192bbf1c574e9db2619c68020 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 22 Oct 2025 09:12:54 -0400 Subject: [PATCH 2338/2653] drm/amdgpu: fix SPDX headers on amdgpu_cper.c/h These should be MIT. The driver in general is MIT and the license text at the top of the files is MIT so fix it. Fixes: 92d5d2a09de1 ("drm/amdgpu: Introduce funcs for populating CPER") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4654 Reviewed-by: Mario Limonciello Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_cper.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c index ef996493115fa..425a3e5643608 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: MIT /* * Copyright 2025 Advanced Micro Devices, Inc. * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.h index bcb97d245673b..353421807387e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ /* * Copyright 2025 Advanced Micro Devices, Inc. * From 70f11f2d7457d518803fa9fb8c352a75d6280258 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 22 Oct 2025 09:14:55 -0400 Subject: [PATCH 2339/2653] drm/amdgpu: fix SPDX header on amd_cper.h This should be MIT. The driver in general is MIT and the license text at the top of the file is MIT so fix it. Fixes: 523b69c65445 ("drm/amd/include: Add amd cper header") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4654 Reviewed-by: Mario Limonciello Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/amd_cper.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/include/amd_cper.h b/drivers/gpu/drm/amd/include/amd_cper.h index 086869264425c..a252ee4c7874c 100644 --- a/drivers/gpu/drm/amd/include/amd_cper.h +++ b/drivers/gpu/drm/amd/include/amd_cper.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ /* * Copyright 2025 Advanced Micro Devices, Inc. * From 91139b570cef42e000b91a394436c60d717d0a72 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 22 Oct 2025 09:17:37 -0400 Subject: [PATCH 2340/2653] drm/amdgpu: fix SPDX header on irqsrcs_vcn_5_0.h This should be MIT. The driver in general is MIT and the license text at the top of the file is MIT so fix it. Fixes: d1bb64651095 ("drm/amdgpu: add irq source ids for VCN5_0/JPEG5_0") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4654 Reviewed-by: Mario Limonciello Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_5_0.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_5_0.h b/drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_5_0.h index 64b553e7de1ae..e7fdcee22a714 100644 --- a/drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_5_0.h +++ b/drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_5_0.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: MIT */ /* * Copyright 2024 Advanced Micro Devices, Inc. All rights reserved. From 0e6cac137feda743b8e484fea46f5f8da5739d38 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 22 Oct 2025 09:19:55 -0400 Subject: [PATCH 2341/2653] drm/amdgpu: fix SPDX header on cyan_skillfish_reg_init.c This should be MIT. The driver in general is MIT and the license text at the top of the file is MIT so fix it. Fixes: e8529dbc75ca ("drm/amdgpu: add ip offset support for cyan skillfish") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4654 Reviewed-by: Mario Limonciello Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c b/drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c index 96616a865aac7..ed1e25661706e 100644 --- a/drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c +++ b/drivers/gpu/drm/amd/amdgpu/cyan_skillfish_reg_init.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: MIT /* * Copyright 2018 Advanced Micro Devices, Inc. * From be5cbe01735b3917c8cb6316778fd6c9d9bfc5d9 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 22 Oct 2025 17:46:26 +0530 Subject: [PATCH 2342/2653] drm/amdgpu: Make SR-IOV critical region checks overflow-safe MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The function amdgpu_virt_init_critical_region() contained an invalid check for a negative init_hdr_offset value: if (init_hdr_offset < 0) Since init_hdr_offset is an unsigned 32-bit integer, this condition can never be true and triggers a Smatch warning: warn: unsigned 'init_hdr_offset' is never less than zero In addition, the subsequent bounds check: if ((init_hdr_offset + init_hdr_size) > vram_size) was vulnerable to integer overflow when adding the two unsigned values. Thus, by promoting offset and size to 64-bit and using check_add_overflow() to safely validate the sum against VRAM size. Fixes: a5d4d72eee03 ("drm/amdgpu: Introduce SRIOV critical regions v2 during VF init") Reported by: Dan Carpenter Cc: Ellen Pan Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Ellen Pan Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 66e9cd1035974..45f2ad083338b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -937,9 +937,10 @@ static uint8_t amdgpu_virt_crit_region_calc_checksum(uint8_t *buf_start, uint8_t int amdgpu_virt_init_critical_region(struct amdgpu_device *adev) { struct amd_sriov_msg_init_data_header *init_data_hdr = NULL; - uint32_t init_hdr_offset = adev->virt.init_data_header.offset; - uint32_t init_hdr_size = adev->virt.init_data_header.size_kb << 10; - uint64_t vram_size; + u64 init_hdr_offset = adev->virt.init_data_header.offset; + u64 init_hdr_size = (u64)adev->virt.init_data_header.size_kb << 10; /* KB → bytes */ + u64 vram_size; + u64 end; int r = 0; uint8_t checksum = 0; @@ -957,7 +958,7 @@ int amdgpu_virt_init_critical_region(struct amdgpu_device *adev) return -EINVAL; vram_size <<= 20; - if ((init_hdr_offset + init_hdr_size) > vram_size) { + if (check_add_overflow(init_hdr_offset, init_hdr_size, &end) || end > vram_size) { dev_err(adev->dev, "init_data_header exceeds VRAM size, exiting\n"); return -EINVAL; } From 723e96058507b7b2b26401081fc27ca4e7c05747 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Tue, 21 Oct 2025 10:01:46 +0800 Subject: [PATCH 2343/2653] drm/amd/pm: smu13: Enable VCN_RESET for pgm 7 with appropriate firmware version This patch extends the VCN_RESET capability check to include pgm 7 when the firmware version is 0x07551400 or newer. Signed-off-by: Jesse Zhang Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 91d7da1d7cba9..7c94aa9c86aba 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -458,7 +458,8 @@ static void smu_v13_0_6_init_caps(struct smu_context *smu) ((pgm == 4) && (fw_ver >= 0x4557000))) smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET)); - if ((pgm == 0) && (fw_ver >= 0x00558200)) + if ((pgm == 0 && fw_ver >= 0x00558200) || + (pgm == 7 && fw_ver >= 0x07551400)) smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET)); } From e0740b4aca690d1a379aa1d96b1c37888ed3aa1e Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Thu, 23 Oct 2025 10:52:21 +0530 Subject: [PATCH 2344/2653] drm/amdgpu: Fix pointer casts when reading dynamic region sizes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The function amdgpu_virt_get_dynamic_data_info() writes a 64-bit size value. In two places (amdgpu_bios.c and amdgpu_discovery.c), the code passed the address of a smaller variable by casting it to u64 *, which is unsafe. This could make the function write more bytes than the smaller variable can hold, possibly overwriting nearby memory. Reported by static analysis tools. v2: Dynamic region size comes from the host (SR-IOV setup) and is always fixed to 5 MB. (Lijo/Ellen) 5 MB easily fits inside a 32-bit value, so using a 64-bit type is not needed. It also avoids extra type casts Fixes: ae92010fb321 ("drm/amdgpu: Add logic for VF ipd and VF bios to init from dynamic crit_region offsets") Reported by: Dan Carpenter Cc: Ellen Pan Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c index db705bf723f12..35d04e69aec09 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -103,7 +103,7 @@ static bool amdgpu_read_bios_from_vram(struct amdgpu_device *adev) { uint8_t __iomem *bios = NULL; resource_size_t vram_base; - resource_size_t size = 256 * 1024; /* ??? */ + u32 size = 256U * 1024U; /* ??? */ if (!(adev->flags & AMD_IS_APU)) if (amdgpu_device_need_post(adev)) @@ -126,7 +126,7 @@ static bool amdgpu_read_bios_from_vram(struct amdgpu_device *adev) */ if (amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled) { if (amdgpu_virt_get_dynamic_data_info(adev, - AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID, adev->bios, (uint64_t *)&size)) { + AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID, adev->bios, &size)) { amdgpu_bios_release(adev); return false; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index f8c3a27c9f1cf..355b0b590a9c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -311,7 +311,7 @@ static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, */ if (amdgpu_virt_get_dynamic_data_info(adev, AMD_SRIOV_MSG_IPD_TABLE_ID, binary, - (uint64_t *)&adev->discovery.size)) { + &adev->discovery.size)) { dev_err(adev->dev, "failed to read discovery info from dynamic critical region."); ret = -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 45f2ad083338b..f2ce8f506aa8a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -1102,7 +1102,7 @@ int amdgpu_virt_init_critical_region(struct amdgpu_device *adev) } int amdgpu_virt_get_dynamic_data_info(struct amdgpu_device *adev, - int data_id, uint8_t *binary, uint64_t *size) + int data_id, uint8_t *binary, u32 *size) { uint32_t data_offset = 0; uint32_t data_size = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 2a13cc892a139..14d864be5800a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -443,7 +443,7 @@ void amdgpu_virt_init(struct amdgpu_device *adev); int amdgpu_virt_init_critical_region(struct amdgpu_device *adev); int amdgpu_virt_get_dynamic_data_info(struct amdgpu_device *adev, - int data_id, uint8_t *binary, uint64_t *size); + int data_id, uint8_t *binary, u32 *size); bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); From d825e53b1174923c3c6ec55298d2345f21b71ba3 Mon Sep 17 00:00:00 2001 From: Alexander Deucher Date: Thu, 23 Oct 2025 14:17:28 -0400 Subject: [PATCH 2345/2653] Revert "drm/amdgpu: More compact VCN IB emission" This reverts commit 98dcea494da1f6ecf2dc85109bcd6403c45c8007. Change-Id: I12e323a835b4fc96f6b94dab19db78c741559c27 --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 101 +++++++++++------------- 1 file changed, 46 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 78c9e6b293892..5ae7cc0d5f57a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -760,19 +760,16 @@ static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib, uint32_t ib_pack_in_dw, bool enc) { uint32_t *ib_checksum; - u32 *ptr = &ib->ptr[ib->length_dw]; - *ptr++ = 0x00000010; /* single queue checksum */ - *ptr++ = 0x30000002; - ib_checksum = ptr++; - *ptr++ = ib_pack_in_dw; + ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */ + ib->ptr[ib->length_dw++] = 0x30000002; + ib_checksum = &ib->ptr[ib->length_dw++]; + ib->ptr[ib->length_dw++] = ib_pack_in_dw; - *ptr++ = 0x00000010; /* engine info */ - *ptr++ = 0x30000001; - *ptr++ = enc ? 0x2 : 0x3; - *ptr++ = ib_pack_in_dw * sizeof(uint32_t); - - ib->length_dw = ptr - ib->ptr; + ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */ + ib->ptr[ib->length_dw++] = 0x30000001; + ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3; + ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t); return ib_checksum; } @@ -802,7 +799,6 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); uint32_t *ib_checksum; uint32_t ib_pack_in_dw; - u32 *ptr; int i, r; if (adev->vcn.inst[ring->me].using_unified_queue) @@ -815,7 +811,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, goto err; ib = &job->ibs[0]; - ptr = ib->ptr; + ib->length_dw = 0; /* single queue headers */ if (adev->vcn.inst[ring->me].using_unified_queue) { @@ -824,11 +820,10 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false); } - *ptr++ = sizeof(struct amdgpu_vcn_decode_buffer) + 8; - *ptr++ = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); - decode_buffer = (struct amdgpu_vcn_decode_buffer *)ptr; - ib->length_dw = ptr - ib->ptr + - sizeof(struct amdgpu_vcn_decode_buffer) / 4; + ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; + ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER); + decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]); + ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4; memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer)); decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER); @@ -836,7 +831,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr); for (i = ib->length_dw; i < ib_size_dw; ++i) - *ptr++ = 0x0; + ib->ptr[i] = 0x0; if (adev->vcn.inst[ring->me].using_unified_queue) amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw); @@ -934,7 +929,6 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand struct dma_fence *f = NULL; uint32_t *ib_checksum = NULL; uint64_t addr; - u32 *ptr; int i, r; if (adev->vcn.inst[ring->me].using_unified_queue) @@ -947,32 +941,31 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand return r; ib = &job->ibs[0]; - ptr = ib->ptr; addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); + ib->length_dw = 0; + if (adev->vcn.inst[ring->me].using_unified_queue) ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); - *ptr++ = 0x00000018; - *ptr++ = 0x00000001; /* session info */ - *ptr++ = handle; - *ptr++ = upper_32_bits(addr); - *ptr++ = addr; - *ptr++ = 0x00000000; - - *ptr++ = 0x00000014; - *ptr++ = 0x00000002; /* task info */ - *ptr++ = 0x0000001c; - *ptr++ = 0x00000000; - *ptr++ = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000018; + ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ + ib->ptr[ib->length_dw++] = handle; + ib->ptr[ib->length_dw++] = upper_32_bits(addr); + ib->ptr[ib->length_dw++] = addr; + ib->ptr[ib->length_dw++] = 0x00000000; - *ptr++ = 0x00000008; - *ptr++ = 0x08000001; /* op initialize */ + ib->ptr[ib->length_dw++] = 0x00000014; + ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ + ib->ptr[ib->length_dw++] = 0x0000001c; + ib->ptr[ib->length_dw++] = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000000; - ib->length_dw = ptr - ib->ptr; + ib->ptr[ib->length_dw++] = 0x00000008; + ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ for (i = ib->length_dw; i < ib_size_dw; ++i) - *ptr++ = 0x0; + ib->ptr[i] = 0x0; if (adev->vcn.inst[ring->me].using_unified_queue) amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); @@ -1003,7 +996,6 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han struct dma_fence *f = NULL; uint32_t *ib_checksum = NULL; uint64_t addr; - u32 *ptr; int i, r; if (adev->vcn.inst[ring->me].using_unified_queue) @@ -1016,32 +1008,31 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han return r; ib = &job->ibs[0]; - ptr = ib->ptr; addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr); + ib->length_dw = 0; + if (adev->vcn.inst[ring->me].using_unified_queue) ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true); - *ptr++ = 0x00000018; - *ptr++ = 0x00000001; - *ptr++ = handle; - *ptr++ = upper_32_bits(addr); - *ptr++ = addr; - *ptr++ = 0x00000000; - - *ptr++ = 0x00000014; - *ptr++ = 0x00000002; - *ptr++ = 0x0000001c; - *ptr++ = 0x00000000; - *ptr++ = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000018; + ib->ptr[ib->length_dw++] = 0x00000001; + ib->ptr[ib->length_dw++] = handle; + ib->ptr[ib->length_dw++] = upper_32_bits(addr); + ib->ptr[ib->length_dw++] = addr; + ib->ptr[ib->length_dw++] = 0x00000000; - *ptr++ = 0x00000008; - *ptr++ = 0x08000002; /* op close session */ + ib->ptr[ib->length_dw++] = 0x00000014; + ib->ptr[ib->length_dw++] = 0x00000002; + ib->ptr[ib->length_dw++] = 0x0000001c; + ib->ptr[ib->length_dw++] = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000000; - ib->length_dw = ptr - ib->ptr; + ib->ptr[ib->length_dw++] = 0x00000008; + ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ for (i = ib->length_dw; i < ib_size_dw; ++i) - *ptr++ = 0x0; + ib->ptr[i] = 0x0; if (adev->vcn.inst[ring->me].using_unified_queue) amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11); From a7e48e5d3600ee9e24ca927c236e80de6315bebf Mon Sep 17 00:00:00 2001 From: Alexander Deucher Date: Thu, 23 Oct 2025 14:18:01 -0400 Subject: [PATCH 2346/2653] Revert "drm/amdgpu: More compact UVD 6 IB emission" This reverts commit 321ec5ac9d9d71fb9444119fbcffa5a4e4155705. Change-Id: If279710c0b2e6404ef289fdbc6bd73d25634d89b --- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 66 ++++++++++++--------------- 1 file changed, 30 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index edbdb44ac1f87..1c07b701d0e4f 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -214,7 +214,6 @@ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle struct amdgpu_ib *ib; struct dma_fence *f = NULL; uint64_t addr; - u32 *ptr; int i, r; r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, @@ -223,29 +222,27 @@ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle return r; ib = &job->ibs[0]; - ptr = ib->ptr; addr = amdgpu_bo_gpu_offset(bo); - *ptr++ = 0x00000018; - *ptr++ = 0x00000001; /* session info */ - *ptr++ = handle; - *ptr++ = 0x00010000; - *ptr++ = upper_32_bits(addr); - *ptr++ = addr; + ib->length_dw = 0; + ib->ptr[ib->length_dw++] = 0x00000018; + ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ + ib->ptr[ib->length_dw++] = handle; + ib->ptr[ib->length_dw++] = 0x00010000; + ib->ptr[ib->length_dw++] = upper_32_bits(addr); + ib->ptr[ib->length_dw++] = addr; - *ptr++ = 0x00000014; - *ptr++ = 0x00000002; /* task info */ - *ptr++ = 0x0000001c; - *ptr++ = 0x00000001; - *ptr++ = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000014; + ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ + ib->ptr[ib->length_dw++] = 0x0000001c; + ib->ptr[ib->length_dw++] = 0x00000001; + ib->ptr[ib->length_dw++] = 0x00000000; - *ptr++ = 0x00000008; - *ptr++ = 0x08000001; /* op initialize */ - - ib->length_dw = ptr - ib->ptr; + ib->ptr[ib->length_dw++] = 0x00000008; + ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ for (i = ib->length_dw; i < ib_size_dw; ++i) - *ptr++ = 0x0; + ib->ptr[i] = 0x0; r = amdgpu_job_submit_direct(job, ring, &f); if (r) @@ -281,7 +278,6 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring, struct amdgpu_ib *ib; struct dma_fence *f = NULL; uint64_t addr; - u32 *ptr; int i, r; r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, @@ -290,29 +286,27 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring, return r; ib = &job->ibs[0]; - ptr = ib->ptr; addr = amdgpu_bo_gpu_offset(bo); - *ptr++ = 0x00000018; - *ptr++ = 0x00000001; /* session info */ - *ptr++ = handle; - *ptr++ = 0x00010000; - *ptr++ = upper_32_bits(addr); - *ptr++ = addr; - - *ptr++ = 0x00000014; - *ptr++ = 0x00000002; /* task info */ - *ptr++ = 0x0000001c; - *ptr++ = 0x00000001; - *ptr++ = 0x00000000; + ib->length_dw = 0; + ib->ptr[ib->length_dw++] = 0x00000018; + ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ + ib->ptr[ib->length_dw++] = handle; + ib->ptr[ib->length_dw++] = 0x00010000; + ib->ptr[ib->length_dw++] = upper_32_bits(addr); + ib->ptr[ib->length_dw++] = addr; - *ptr++ = 0x00000008; - *ptr++ = 0x08000002; /* op close session */ + ib->ptr[ib->length_dw++] = 0x00000014; + ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ + ib->ptr[ib->length_dw++] = 0x0000001c; + ib->ptr[ib->length_dw++] = 0x00000001; + ib->ptr[ib->length_dw++] = 0x00000000; - ib->length_dw = ptr - ib->ptr; + ib->ptr[ib->length_dw++] = 0x00000008; + ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ for (i = ib->length_dw; i < ib_size_dw; ++i) - *ptr++ = 0x0; + ib->ptr[i] = 0x0; r = amdgpu_job_submit_direct(job, ring, &f); if (r) From 1ad783f3120f2a05f3476a0b1125524b756f96d5 Mon Sep 17 00:00:00 2001 From: Alexander Deucher Date: Thu, 23 Oct 2025 14:18:22 -0400 Subject: [PATCH 2347/2653] Revert "drm/amdgpu: More compact UVD 7 IB emission" This reverts commit 4400702d23ca58656d9730aac8de45b8909e4917. Change-Id: Iff9f0f055d335489dac124386e106a690fc6876d --- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 66 ++++++++++++--------------- 1 file changed, 30 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 5634c587c97f2..9d237b5937fb0 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -222,7 +222,6 @@ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, u32 handle, struct amdgpu_ib *ib; struct dma_fence *f = NULL; uint64_t addr; - u32 *ptr; int i, r; r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, @@ -231,29 +230,27 @@ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, u32 handle, return r; ib = &job->ibs[0]; - ptr = ib->ptr; addr = amdgpu_bo_gpu_offset(bo); - *ptr++ = 0x00000018; - *ptr++ = 0x00000001; /* session info */ - *ptr++ = handle; - *ptr++ = 0x00000000; - *ptr++ = upper_32_bits(addr); - *ptr++ = addr; + ib->length_dw = 0; + ib->ptr[ib->length_dw++] = 0x00000018; + ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ + ib->ptr[ib->length_dw++] = handle; + ib->ptr[ib->length_dw++] = 0x00000000; + ib->ptr[ib->length_dw++] = upper_32_bits(addr); + ib->ptr[ib->length_dw++] = addr; - *ptr++ = 0x00000014; - *ptr++ = 0x00000002; /* task info */ - *ptr++ = 0x0000001c; - *ptr++ = 0x00000000; - *ptr++ = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000014; + ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ + ib->ptr[ib->length_dw++] = 0x0000001c; + ib->ptr[ib->length_dw++] = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000000; - *ptr++ = 0x00000008; - *ptr++ = 0x08000001; /* op initialize */ - - ib->length_dw = ptr - ib->ptr; + ib->ptr[ib->length_dw++] = 0x00000008; + ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ for (i = ib->length_dw; i < ib_size_dw; ++i) - *ptr++ = 0x0; + ib->ptr[i] = 0x0; r = amdgpu_job_submit_direct(job, ring, &f); if (r) @@ -288,7 +285,6 @@ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, u32 handle, struct amdgpu_ib *ib; struct dma_fence *f = NULL; uint64_t addr; - u32 *ptr; int i, r; r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, @@ -297,29 +293,27 @@ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, u32 handle, return r; ib = &job->ibs[0]; - ptr = ib->ptr; addr = amdgpu_bo_gpu_offset(bo); - *ptr++ = 0x00000018; - *ptr++ = 0x00000001; - *ptr++ = handle; - *ptr++ = 0x00000000; - *ptr++ = upper_32_bits(addr); - *ptr++ = addr; - - *ptr++ = 0x00000014; - *ptr++ = 0x00000002; - *ptr++ = 0x0000001c; - *ptr++ = 0x00000000; - *ptr++ = 0x00000000; + ib->length_dw = 0; + ib->ptr[ib->length_dw++] = 0x00000018; + ib->ptr[ib->length_dw++] = 0x00000001; + ib->ptr[ib->length_dw++] = handle; + ib->ptr[ib->length_dw++] = 0x00000000; + ib->ptr[ib->length_dw++] = upper_32_bits(addr); + ib->ptr[ib->length_dw++] = addr; - *ptr++ = 0x00000008; - *ptr++ = 0x08000002; /* op close session */ + ib->ptr[ib->length_dw++] = 0x00000014; + ib->ptr[ib->length_dw++] = 0x00000002; + ib->ptr[ib->length_dw++] = 0x0000001c; + ib->ptr[ib->length_dw++] = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000000; - ib->length_dw = ptr - ib->ptr; + ib->ptr[ib->length_dw++] = 0x00000008; + ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ for (i = ib->length_dw; i < ib_size_dw; ++i) - *ptr++ = 0x0; + ib->ptr[i] = 0x0; r = amdgpu_job_submit_direct(job, ring, &f); if (r) From 4cc315d7706ef858d24855c5ce76e6d4071a3567 Mon Sep 17 00:00:00 2001 From: Alexander Deucher Date: Thu, 23 Oct 2025 14:18:42 -0400 Subject: [PATCH 2348/2653] Revert "drm/amdgpu: More compact SI SDMA emission" This reverts commit a7b21c267835f43d60baababb4a43376047934e9. Change-Id: Idd3bf23f48dbf15f1a75ddc977acb58b498a043b --- drivers/gpu/drm/amd/amdgpu/si_dma.c | 84 ++++++++++++----------------- 1 file changed, 33 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 9e26c7598d74b..7f18e4875287c 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -323,16 +323,14 @@ static void si_dma_vm_copy_pte(struct amdgpu_ib *ib, uint64_t pe, uint64_t src, unsigned count) { - u32 *ptr = &ib->ptr[ib->length_dw]; unsigned bytes = count * 8; - *ptr++ = DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, bytes); - *ptr++ = lower_32_bits(pe); - *ptr++ = lower_32_bits(src); - *ptr++ = upper_32_bits(pe) & 0xff; - *ptr++ = upper_32_bits(src) & 0xff; - - ib->length_dw = ptr - ib->ptr; + ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, + 1, 0, 0, bytes); + ib->ptr[ib->length_dw++] = lower_32_bits(pe); + ib->ptr[ib->length_dw++] = lower_32_bits(src); + ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; + ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; } /** @@ -350,19 +348,16 @@ static void si_dma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, uint64_t value, unsigned count, uint32_t incr) { - u32 *ptr = &ib->ptr[ib->length_dw]; unsigned ndw = count * 2; - *ptr++ = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw); - *ptr++ = lower_32_bits(pe); - *ptr++ = upper_32_bits(pe); + ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw); + ib->ptr[ib->length_dw++] = lower_32_bits(pe); + ib->ptr[ib->length_dw++] = upper_32_bits(pe); for (; ndw > 0; ndw -= 2) { - *ptr++ = lower_32_bits(value); - *ptr++ = upper_32_bits(value); + ib->ptr[ib->length_dw++] = lower_32_bits(value); + ib->ptr[ib->length_dw++] = upper_32_bits(value); value += incr; } - - ib->length_dw = ptr - ib->ptr; } /** @@ -382,7 +377,6 @@ static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t addr, unsigned count, uint32_t incr, uint64_t flags) { - u32 *ptr = &ib->ptr[ib->length_dw]; uint64_t value; unsigned ndw; @@ -397,21 +391,19 @@ static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib, value = 0; /* for physically contiguous pages (vram) */ - *ptr++ = DMA_PTE_PDE_PACKET(ndw); - *ptr++ = pe; /* dst addr */ - *ptr++ = upper_32_bits(pe) & 0xff; - *ptr++ = lower_32_bits(flags); /* mask */ - *ptr++ = upper_32_bits(flags); - *ptr++ = value; /* value */ - *ptr++ = upper_32_bits(value); - *ptr++ = incr; /* increment size */ - *ptr++ = 0; + ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw); + ib->ptr[ib->length_dw++] = pe; /* dst addr */ + ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; + ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ + ib->ptr[ib->length_dw++] = upper_32_bits(flags); + ib->ptr[ib->length_dw++] = value; /* value */ + ib->ptr[ib->length_dw++] = upper_32_bits(value); + ib->ptr[ib->length_dw++] = incr; /* increment size */ + ib->ptr[ib->length_dw++] = 0; pe += ndw * 4; addr += (ndw / 2) * incr; count -= ndw / 2; } - - ib->length_dw = ptr - ib->ptr; } /** @@ -423,12 +415,8 @@ static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib, */ static void si_dma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) { - int pad = 8 - (ib->length_dw & 0x7); - - if (pad && pad < 8) { - memset32(ib->ptr, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), pad); - ib->length_dw += pad; - } + while (ib->length_dw & 0x7) + ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0); } /** @@ -795,15 +783,12 @@ static void si_dma_emit_copy_buffer(struct amdgpu_ib *ib, uint32_t byte_count, uint32_t copy_flags) { - u32 *ptr = &ib->ptr[ib->length_dw]; - - *ptr++ = DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, byte_count); - *ptr++ = lower_32_bits(dst_offset); - *ptr++ = lower_32_bits(src_offset); - *ptr++ = upper_32_bits(dst_offset) & 0xff; - *ptr++ = upper_32_bits(src_offset) & 0xff; - - ib->length_dw = ptr - ib->ptr; + ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, + 1, 0, 0, byte_count); + ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); + ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); + ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) & 0xff; + ib->ptr[ib->length_dw++] = upper_32_bits(src_offset) & 0xff; } /** @@ -821,14 +806,11 @@ static void si_dma_emit_fill_buffer(struct amdgpu_ib *ib, uint64_t dst_offset, uint32_t byte_count) { - u32 *ptr = &ib->ptr[ib->length_dw]; - - *ptr++ = DMA_PACKET(DMA_PACKET_CONSTANT_FILL, 0, 0, 0, byte_count / 4); - *ptr++ = lower_32_bits(dst_offset); - *ptr++ = src_data; - *ptr++ = upper_32_bits(dst_offset) << 16; - - ib->length_dw = ptr - ib->ptr; + ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_CONSTANT_FILL, + 0, 0, 0, byte_count / 4); + ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); + ib->ptr[ib->length_dw++] = src_data; + ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) << 16; } From ba099443caa0583325e6a96359bddcf86a4158e1 Mon Sep 17 00:00:00 2001 From: Alexander Deucher Date: Thu, 23 Oct 2025 14:18:59 -0400 Subject: [PATCH 2349/2653] Revert "drm/amdgpu: More compact CIK SDMA IB emission" This reverts commit b10f9aa636814fdad65c0bdcc421dd6ccb27d372. Change-Id: I81b636c357e59a6d3179258c7e07c508ca45aa5d --- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 105 +++++++++++--------------- 1 file changed, 42 insertions(+), 63 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index bf3049200fcdd..9e8715b4739da 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -718,18 +718,16 @@ static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib, uint64_t pe, uint64_t src, unsigned count) { - u32 *ptr = &ib->ptr[ib->length_dw]; unsigned bytes = count * 8; - *ptr++ = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); - *ptr++ = bytes; - *ptr++ = 0; /* src/dst endian swap */ - *ptr++ = lower_32_bits(src); - *ptr++ = upper_32_bits(src); - *ptr++ = lower_32_bits(pe); - *ptr++ = upper_32_bits(pe); - - ib->length_dw = ptr - ib->ptr; + ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, + SDMA_WRITE_SUB_OPCODE_LINEAR, 0); + ib->ptr[ib->length_dw++] = bytes; + ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ + ib->ptr[ib->length_dw++] = lower_32_bits(src); + ib->ptr[ib->length_dw++] = upper_32_bits(src); + ib->ptr[ib->length_dw++] = lower_32_bits(pe); + ib->ptr[ib->length_dw++] = upper_32_bits(pe); } /** @@ -747,21 +745,18 @@ static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, uint64_t value, unsigned count, uint32_t incr) { - u32 *ptr = &ib->ptr[ib->length_dw]; unsigned ndw = count * 2; - *ptr++ = SDMA_PACKET(SDMA_OPCODE_WRITE, - SDMA_WRITE_SUB_OPCODE_LINEAR, 0); - *ptr++ = lower_32_bits(pe); - *ptr++ = upper_32_bits(pe); - *ptr++ = ndw; + ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, + SDMA_WRITE_SUB_OPCODE_LINEAR, 0); + ib->ptr[ib->length_dw++] = lower_32_bits(pe); + ib->ptr[ib->length_dw++] = upper_32_bits(pe); + ib->ptr[ib->length_dw++] = ndw; for (; ndw > 0; ndw -= 2) { - *ptr++ = lower_32_bits(value); - *ptr++ = upper_32_bits(value); + ib->ptr[ib->length_dw++] = lower_32_bits(value); + ib->ptr[ib->length_dw++] = upper_32_bits(value); value += incr; } - - ib->length_dw = ptr - ib->ptr; } /** @@ -780,21 +775,17 @@ static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint64_t flags) { - u32 *ptr = &ib->ptr[ib->length_dw]; - /* for physically contiguous pages (vram) */ - *ptr++ = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); - *ptr++ = lower_32_bits(pe); /* dst addr */ - *ptr++ = upper_32_bits(pe); - *ptr++ = lower_32_bits(flags); /* mask */ - *ptr++ = upper_32_bits(flags); - *ptr++ = lower_32_bits(addr); /* value */ - *ptr++ = upper_32_bits(addr); - *ptr++ = incr; /* increment size */ - *ptr++ = 0; - *ptr++ = count; /* number of entries */ - - ib->length_dw = ptr - ib->ptr; + ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); + ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ + ib->ptr[ib->length_dw++] = upper_32_bits(pe); + ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ + ib->ptr[ib->length_dw++] = upper_32_bits(flags); + ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ + ib->ptr[ib->length_dw++] = upper_32_bits(addr); + ib->ptr[ib->length_dw++] = incr; /* increment size */ + ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = count; /* number of entries */ } /** @@ -807,22 +798,18 @@ static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) { struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); - u32 *ptr = &ib->ptr[ib->length_dw]; u32 pad_count; int i; pad_count = (-ib->length_dw) & 7; - if (!pad_count) - return; - for (i = 0; i < pad_count; i++) if (sdma && sdma->burst_nop && (i == 0)) - *ptr++ = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) | - SDMA_NOP_COUNT(pad_count - 1); + ib->ptr[ib->length_dw++] = + SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) | + SDMA_NOP_COUNT(pad_count - 1); else - *ptr++ = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); - - ib->length_dw += pad_count; + ib->ptr[ib->length_dw++] = + SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); } /** @@ -1303,17 +1290,13 @@ static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib, uint32_t byte_count, uint32_t copy_flags) { - u32 *ptr = &ib->ptr[ib->length_dw]; - - *ptr++ = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); - *ptr++ = byte_count; - *ptr++ = 0; /* src/dst endian swap */ - *ptr++ = lower_32_bits(src_offset); - *ptr++ = upper_32_bits(src_offset); - *ptr++ = lower_32_bits(dst_offset); - *ptr++ = upper_32_bits(dst_offset); - - ib->length_dw = ptr - ib->ptr; + ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); + ib->ptr[ib->length_dw++] = byte_count; + ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ + ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); + ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); + ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); + ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); } /** @@ -1331,15 +1314,11 @@ static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib, uint64_t dst_offset, uint32_t byte_count) { - u32 *ptr = &ib->ptr[ib->length_dw]; - - *ptr++ = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0); - *ptr++ = lower_32_bits(dst_offset); - *ptr++ = upper_32_bits(dst_offset); - *ptr++ = src_data; - *ptr++ = byte_count; - - ib->length_dw = ptr - ib->ptr; + ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0); + ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); + ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); + ib->ptr[ib->length_dw++] = src_data; + ib->ptr[ib->length_dw++] = byte_count; } static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = { From f0138835edabd4bd01d7c4dc90544c737c3c527d Mon Sep 17 00:00:00 2001 From: Alexander Deucher Date: Thu, 23 Oct 2025 17:52:43 -0400 Subject: [PATCH 2350/2653] Revert "drm/amdgpu: More compact VCE IB emission" This reverts commit 848ee95e9cd75025efd288e1e153f8e97490dfbe. Change-Id: I1f6e1ea72763296ed275dffa5d285972d7f899b8 --- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 94 ++++++++++++------------- 1 file changed, 44 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 60e54d3c384be..b9060bcd48064 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -444,7 +444,6 @@ static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, struct amdgpu_ib ib_msg; struct dma_fence *f = NULL; uint64_t addr; - u32 *ptr; int i, r; r = amdgpu_job_alloc_with_ib(ring->adev, &ring->adev->vce.entity, @@ -463,47 +462,45 @@ static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, goto err; ib = &job->ibs[0]; - ptr = ib->ptr; /* let addr point to page boundary */ addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg.gpu_addr); /* stitch together an VCE create msg */ - *ptr++ = 0x0000000c; /* len */ - *ptr++ = 0x00000001; /* session cmd */ - *ptr++ = handle; + ib->length_dw = 0; + ib->ptr[ib->length_dw++] = 0x0000000c; /* len */ + ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */ + ib->ptr[ib->length_dw++] = handle; if ((ring->adev->vce.fw_version >> 24) >= 52) - *ptr++ = 0x00000040; /* len */ + ib->ptr[ib->length_dw++] = 0x00000040; /* len */ else - *ptr++ = 0x00000030; /* len */ - *ptr++ = 0x01000001; /* create cmd */ - *ptr++ = 0x00000000; - *ptr++ = 0x00000042; - *ptr++ = 0x0000000a; - *ptr++ = 0x00000001; - *ptr++ = 0x00000080; - *ptr++ = 0x00000060; - *ptr++ = 0x00000100; - *ptr++ = 0x00000100; - *ptr++ = 0x0000000c; - *ptr++ = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000030; /* len */ + ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */ + ib->ptr[ib->length_dw++] = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000042; + ib->ptr[ib->length_dw++] = 0x0000000a; + ib->ptr[ib->length_dw++] = 0x00000001; + ib->ptr[ib->length_dw++] = 0x00000080; + ib->ptr[ib->length_dw++] = 0x00000060; + ib->ptr[ib->length_dw++] = 0x00000100; + ib->ptr[ib->length_dw++] = 0x00000100; + ib->ptr[ib->length_dw++] = 0x0000000c; + ib->ptr[ib->length_dw++] = 0x00000000; if ((ring->adev->vce.fw_version >> 24) >= 52) { - *ptr++ = 0x00000000; - *ptr++ = 0x00000000; - *ptr++ = 0x00000000; - *ptr++ = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000000; } - *ptr++ = 0x00000014; /* len */ - *ptr++ = 0x05000005; /* feedback buffer */ - *ptr++ = upper_32_bits(addr); - *ptr++ = addr; - *ptr++ = 0x00000001; - - ib->length_dw = ptr - ib->ptr; + ib->ptr[ib->length_dw++] = 0x00000014; /* len */ + ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */ + ib->ptr[ib->length_dw++] = upper_32_bits(addr); + ib->ptr[ib->length_dw++] = addr; + ib->ptr[ib->length_dw++] = 0x00000001; for (i = ib->length_dw; i < ib_size_dw; ++i) - *ptr++ = 0x0; + ib->ptr[i] = 0x0; r = amdgpu_job_submit_direct(job, ring, &f); amdgpu_ib_free(&ib_msg, f); @@ -537,7 +534,6 @@ static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, struct amdgpu_job *job; struct amdgpu_ib *ib; struct dma_fence *f = NULL; - u32 *ptr; int i, r; r = amdgpu_job_alloc_with_ib(ring->adev, &ring->adev->vce.entity, @@ -549,29 +545,27 @@ static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, return r; ib = &job->ibs[0]; - ptr = ib->ptr; /* stitch together an VCE destroy msg */ - *ptr++ = 0x0000000c; /* len */ - *ptr++ = 0x00000001; /* session cmd */ - *ptr++ = handle; - - *ptr++ = 0x00000020; /* len */ - *ptr++ = 0x00000002; /* task info */ - *ptr++ = 0xffffffff; /* next task info, set to 0xffffffff if no */ - *ptr++ = 0x00000001; /* destroy session */ - *ptr++ = 0x00000000; - *ptr++ = 0x00000000; - *ptr++ = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */ - *ptr++ = 0x00000000; - - *ptr++ = 0x00000008; /* len */ - *ptr++ = 0x02000001; /* destroy cmd */ - - ib->length_dw = ptr - ib->ptr; + ib->length_dw = 0; + ib->ptr[ib->length_dw++] = 0x0000000c; /* len */ + ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */ + ib->ptr[ib->length_dw++] = handle; + + ib->ptr[ib->length_dw++] = 0x00000020; /* len */ + ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ + ib->ptr[ib->length_dw++] = 0xffffffff; /* next task info, set to 0xffffffff if no */ + ib->ptr[ib->length_dw++] = 0x00000001; /* destroy session */ + ib->ptr[ib->length_dw++] = 0x00000000; + ib->ptr[ib->length_dw++] = 0x00000000; + ib->ptr[ib->length_dw++] = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */ + ib->ptr[ib->length_dw++] = 0x00000000; + + ib->ptr[ib->length_dw++] = 0x00000008; /* len */ + ib->ptr[ib->length_dw++] = 0x02000001; /* destroy cmd */ for (i = ib->length_dw; i < ib_size_dw; ++i) - *ptr++ = 0x0; + ib->ptr[i] = 0x0; if (direct) r = amdgpu_job_submit_direct(job, ring, &f); From e9753def8ddf4c61bb514292d46d069eeb5c307f Mon Sep 17 00:00:00 2001 From: Yang Su Date: Tue, 21 Oct 2025 17:50:02 +0800 Subject: [PATCH 2351/2653] Revert "drm/amdgpu: clean up amdgpu hmm range functions" it's caused by https://ontrack-internal.amd.com/browse/SWDEV-561693 This reverts commit dd889a641ca5ed2dc21ec04c47b67e67e4e931c8. --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 18 ++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 10 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 6 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 23 +++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 17 +-------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 38 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 13 +++++++ drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 9 ++--- 8 files changed, 79 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 568a8573da99a..701193f2869fd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1153,7 +1153,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, } #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - range = amdgpu_hmm_range_alloc(); + range = kzalloc(sizeof(*range), GFP_KERNEL); if (unlikely(!range)) { ret = -ENOMEM; goto unregister_out; @@ -1161,7 +1161,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, ret = amdgpu_ttm_tt_get_user_pages(bo, range); if (ret) { - amdgpu_hmm_range_free(range); + kfree(range); if (ret == -EAGAIN) pr_debug("Failed to get user pages, try again\n"); else @@ -1210,7 +1210,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, release_out: #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - amdgpu_hmm_range_free(range); + amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); #else if (ret) amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, NULL); @@ -2032,7 +2032,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( amdgpu_hmm_unregister(mem->bo); #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mutex_lock(&process_info->notifier_lock); - amdgpu_hmm_range_free(mem->range); + amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range); mutex_unlock(&process_info->notifier_lock); #else /* Free user pages if necessary */ @@ -2924,7 +2924,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, bo = mem->bo; #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - amdgpu_hmm_range_free(mem->range); + amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range); mem->range = NULL; #endif @@ -2950,13 +2950,13 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, } #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - mem->range = amdgpu_hmm_range_alloc(); + mem->range = kzalloc(sizeof(*mem->range), GFP_KERNEL); if (unlikely(!mem->range)) return -ENOMEM; /* Get updated user pages */ ret = amdgpu_ttm_tt_get_user_pages(bo, mem->range); if (ret) { - amdgpu_hmm_range_free(mem->range); + kfree(mem->range); mem->range = NULL; pr_debug("Failed %d to get user pages\n", ret); @@ -3188,8 +3188,8 @@ static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_i continue; /* Only check mem with hmm range associated */ - valid = amdgpu_hmm_range_valid(mem->range); - amdgpu_hmm_range_free(mem->range); + valid = amdgpu_ttm_tt_get_user_pages_done( + mem->bo->tbo.ttm, mem->range); mem->range = NULL; if (!valid) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index d209d17a08ee8..a484f9212c573 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -910,7 +910,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, bool userpage_invalidated = false; struct amdgpu_bo *bo = e->bo; - e->range = amdgpu_hmm_range_alloc(); + e->range = kzalloc(sizeof(*e->range), GFP_KERNEL); if (unlikely(!e->range)) return -ENOMEM; @@ -1104,7 +1104,9 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, out_free_user_pages: #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { - amdgpu_hmm_range_free(e->range); + struct amdgpu_bo *bo = e->bo; + + amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, e->range); e->range = NULL; } #else @@ -1454,8 +1456,8 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, */ r = 0; amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { - r |= !amdgpu_hmm_range_valid(e->range); - amdgpu_hmm_range_free(e->range); + r |= !amdgpu_ttm_tt_get_user_pages_done(e->bo->tbo.ttm, + e->range); e->range = NULL; } if (r) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 478184576f0ce..0ea9ab4c0b26c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -644,7 +644,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - range = amdgpu_hmm_range_alloc(); + range = kzalloc(sizeof(*range), GFP_KERNEL); if (unlikely(!range)) return -ENOMEM; r = amdgpu_ttm_tt_get_user_pages(bo, range); @@ -654,7 +654,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, #endif if (r) { #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - amdgpu_hmm_range_free(range); + kfree(range); #endif goto release_object; } @@ -692,7 +692,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, user_pages_done: #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) - amdgpu_hmm_range_free(range); + amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); #else release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 55b2359799ae4..14e62c2be1149 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -919,30 +919,19 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, return r; } -bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range) +bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range) { - if (!hmm_range) - return false; - - return !mmu_interval_read_retry(hmm_range->notifier, - hmm_range->notifier_seq); -} - -struct hmm_range *amdgpu_hmm_range_alloc(void) -{ - return kzalloc(sizeof(struct hmm_range), GFP_KERNEL); -} - -void amdgpu_hmm_range_free(struct hmm_range *hmm_range) -{ - if (!hmm_range) - return; + bool r; + r = mmu_interval_read_retry(hmm_range->notifier, + hmm_range->notifier_seq); #ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT kvfree(hmm_range->pfns); #else kvfree(hmm_range->hmm_pfns); #endif kfree(hmm_range); + + return r; } #endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index 4ec014a918514..e078aa4905e38 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -87,11 +87,9 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, void *owner, struct hmm_range *hmm_range); +bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range); #if defined(CONFIG_HMM_MIRROR) -bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range); -struct hmm_range *amdgpu_hmm_range_alloc(void); -void amdgpu_hmm_range_free(struct hmm_range *hmm_range); int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr); void amdgpu_hmm_unregister(struct amdgpu_bo *bo); #else @@ -101,20 +99,7 @@ static inline int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) "add CONFIG_ZONE_DEVICE=y in config file to fix this\n"); return -ENODEV; } - static inline void amdgpu_hmm_unregister(struct amdgpu_bo *bo) {} - -static inline bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range) -{ - return false; -} - -static inline struct hmm_range *amdgpu_hmm_range_alloc(void) -{ - return NULL; -} - -static inline void amdgpu_hmm_range_free(struct hmm_range *hmm_range) {} #endif #endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 782d877415b4c..ee81b5174ccb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -826,6 +826,44 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, return r; } +/* amdgpu_ttm_tt_discard_user_pages - Discard range and pfn array allocations + */ +void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, + struct hmm_range *range) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + + if (gtt && gtt->userptr && range) + amdgpu_hmm_range_get_pages_done(range); +} + +/* + * amdgpu_ttm_tt_get_user_pages_done - stop HMM track the CPU page table change + * Check if the pages backing this ttm range have been invalidated + * + * Returns: true if pages are still valid + */ +bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, + struct hmm_range *range) +{ + struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); + + if (!gtt || !gtt->userptr || !range) + return false; + + DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", + gtt->userptr, ttm->num_pages); + +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + WARN_ONCE(!range->pfns, +#else + WARN_ONCE(!range->hmm_pfns, +#endif + "No user pages to check\n"); + + return !amdgpu_hmm_range_get_pages_done(range); +} + #else /* * amdgpu_ttm_tt_get_user_pages - Pin pages of memory pointed to by a USERPTR diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 848568bb83d86..4df65ac85dc5f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -208,6 +208,10 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, struct hmm_range **range); #endif +void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, + struct hmm_range *range); +bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, + struct hmm_range *range); #else #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, @@ -222,6 +226,15 @@ static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page return -EPERM; } #endif +static inline void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, + struct hmm_range *range) +{ +} +static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, + struct hmm_range *range) +{ + return false; +} #endif #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 5639a51212e05..5492b0e74260f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1741,13 +1741,13 @@ static int svm_range_validate_and_map(struct mm_struct *mm, } WRITE_ONCE(p->svms.faulting_task, current); - hmm_range = amdgpu_hmm_range_alloc(); + hmm_range = kzalloc(sizeof(*hmm_range), GFP_KERNEL); r = amdgpu_hmm_range_get_pages(&prange->notifier, addr, npages, readonly, owner, hmm_range); WRITE_ONCE(p->svms.faulting_task, NULL); if (r) { - amdgpu_hmm_range_free(hmm_range); + kfree(hmm_range); pr_debug("failed %d to get svm range pages\n", r); } } else { @@ -1768,13 +1768,10 @@ static int svm_range_validate_and_map(struct mm_struct *mm, * Overrride return value to TRY AGAIN only if prior returns * were successful */ - if (hmm_range && !amdgpu_hmm_range_valid(hmm_range) && !r) { + if (hmm_range && amdgpu_hmm_range_get_pages_done(hmm_range) && !r) { pr_debug("hmm update the range, need validate again\n"); r = -EAGAIN; } - /* Free the hmm range */ - amdgpu_hmm_range_free(hmm_range); - if (!r && !list_empty(&prange->child_list)) { pr_debug("range split by unmap in parallel, validate again\n"); From d058365aeeb4534f0f4b0e8a1e61a3de1f328e14 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Fri, 24 Oct 2025 13:26:53 +0800 Subject: [PATCH 2352/2653] Bump AMDGPU version to 6.16.8 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 88d1a3dacee49..361d3d80c513c 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.16.7) +AC_INIT(amdgpu-dkms, 6.16.8) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 652a4cf511b4dd60fda3a6fe6c73223597708e8d Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Mon, 6 Oct 2025 10:09:09 -0500 Subject: [PATCH 2353/2653] drm/amd/display: Bump minimum for frame_warn_limit [Why] The bigger of CONFIG_FRAME_WARN and frame_warn_limit is used to trigger warnings about large stack frames. The dml_core_mode_support() stack frame has grown to 2056. [How] Update frame_warn_limit to 2056 so that CONFIG_FRAME_WARN of 2048 doesn't cause a failure. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4609 Reviewed-by: Aurabindo Pillai Signed-off-by: Mario Limonciello Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dml2/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/Makefile b/drivers/gpu/drm/amd/display/dc/dml2/Makefile index 9a6cc5b79b778..66177fcea4308 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml2/Makefile @@ -73,7 +73,7 @@ ifneq ($(CONFIG_FRAME_WARN),0) frame_warn_limit := 3072 endif else - frame_warn_limit := 2048 + frame_warn_limit := 2056 endif ifeq ($(call test-lt, $(CONFIG_FRAME_WARN), $(frame_warn_limit)),y) From a2e7dd772043ca7658fd58e8815def5095410dd5 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Tue, 30 Sep 2025 12:17:13 -0400 Subject: [PATCH 2354/2653] drm/amd/display: Fix DMUB reset sequence for DCN32 [WHY&HOW] Backport reset sequence fixes implemented on DCN401 to DCN32 to address stability issues when resetting the DMUB. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Dillon Varone Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/dmub/src/dmub_dcn32.c | 50 ++++++++++++------- .../drm/amd/display/dmub/src/dmub_dcn401.c | 17 +++++-- 2 files changed, 45 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c index ce041f6239dc7..7e98562899108 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c @@ -89,50 +89,58 @@ static inline void dmub_dcn32_translate_addr(const union dmub_addr *addr_in, void dmub_dcn32_reset(struct dmub_srv *dmub) { union dmub_gpint_data_register cmd; - const uint32_t timeout = 100000; - uint32_t in_reset, is_enabled, scratch, i, pwait_mode; + const uint32_t timeout_us = 1 * 1000 * 1000; //1s + const uint32_t poll_delay_us = 1; //1us + uint32_t i = 0; + uint32_t enabled, in_reset, scratch, pwait_mode; - REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); - REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled); + REG_GET(DMCUB_CNTL, + DMCUB_ENABLE, &enabled); + REG_GET(DMCUB_CNTL2, + DMCUB_SOFT_RESET, &in_reset); - if (in_reset == 0 && is_enabled != 0) { + if (enabled && in_reset == 0) { cmd.bits.status = 1; cmd.bits.command_code = DMUB_GPINT__STOP_FW; cmd.bits.param = 0; dmub->hw_funcs.set_gpint(dmub, cmd); - for (i = 0; i < timeout; ++i) { - if (dmub->hw_funcs.is_gpint_acked(dmub, cmd)) - break; - - udelay(1); - } - - for (i = 0; i < timeout; ++i) { + for (; i < timeout_us; i++) { scratch = REG_READ(DMCUB_SCRATCH7); if (scratch == DMUB_GPINT__STOP_FW_RESPONSE) break; - udelay(1); + udelay(poll_delay_us); } - for (i = 0; i < timeout; ++i) { + for (; i < timeout_us; i++) { REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode); if (pwait_mode & (1 << 0)) break; - udelay(1); + udelay(poll_delay_us); } - /* Force reset in case we timed out, DMCUB is likely hung. */ } - if (is_enabled) { + if (enabled) { REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1); udelay(1); REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); } + if (i >= timeout_us) { + /* timeout should never occur */ + BREAK_TO_DEBUGGER(); + } + + REG_UPDATE(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE, 0); + REG_UPDATE(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE, 0); + REG_UPDATE(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE, 0); + REG_UPDATE(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE, 0); + REG_UPDATE(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, 0); + REG_UPDATE(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE, 0); + REG_WRITE(DMCUB_INBOX1_RPTR, 0); REG_WRITE(DMCUB_INBOX1_WPTR, 0); REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); @@ -141,7 +149,7 @@ void dmub_dcn32_reset(struct dmub_srv *dmub) REG_WRITE(DMCUB_OUTBOX0_WPTR, 0); REG_WRITE(DMCUB_SCRATCH0, 0); - /* Clear the GPINT command manually so we don't send anything during boot. */ + /* Clear the GPINT command manually so we don't reset again. */ cmd.all = 0; dmub->hw_funcs.set_gpint(dmub, cmd); } @@ -163,7 +171,9 @@ void dmub_dcn32_backdoor_load(struct dmub_srv *dmub, dmub_dcn32_get_fb_base_offset(dmub, &fb_base, &fb_offset); + /* reset and disable DMCUB and MMHUBBUB DMUIF */ REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); + REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); dmub_dcn32_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); @@ -193,7 +203,9 @@ void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub, { union dmub_addr offset; + /* reset and disable DMCUB and MMHUBBUB DMUIF */ REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); + REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); offset = cw0->offset; diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c index b31adbd0d685f..95542299e3b38 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c @@ -81,7 +81,7 @@ void dmub_dcn401_reset(struct dmub_srv *dmub) dmub->hw_funcs.set_gpint(dmub, cmd); for (; i < timeout_us; i++) { - scratch = dmub->hw_funcs.get_gpint_response(dmub); + scratch = REG_READ(DMCUB_SCRATCH7); if (scratch == DMUB_GPINT__STOP_FW_RESPONSE) break; @@ -97,11 +97,24 @@ void dmub_dcn401_reset(struct dmub_srv *dmub) } } + if (enabled) { + REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1); + udelay(1); + REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); + } + if (i >= timeout_us) { /* timeout should never occur */ BREAK_TO_DEBUGGER(); } + REG_UPDATE(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE, 0); + REG_UPDATE(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE, 0); + REG_UPDATE(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE, 0); + REG_UPDATE(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE, 0); + REG_UPDATE(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, 0); + REG_UPDATE(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE, 0); + REG_WRITE(DMCUB_INBOX1_RPTR, 0); REG_WRITE(DMCUB_INBOX1_WPTR, 0); REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); @@ -134,7 +147,6 @@ void dmub_dcn401_backdoor_load(struct dmub_srv *dmub, /* reset and disable DMCUB and MMHUBBUB DMUIF */ REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); - REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1); REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); dmub_dcn401_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); @@ -168,7 +180,6 @@ void dmub_dcn401_backdoor_load_zfb_mode(struct dmub_srv *dmub, /* reset and disable DMCUB and MMHUBBUB DMUIF */ REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); - REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1); REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); offset = cw0->offset; From 78609cac6205007707c970a5ec3e411aeaa98c09 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Tue, 14 Oct 2025 13:05:26 -0400 Subject: [PATCH 2355/2653] drm/amd/display: Add opp count validation to dml2.1 Newer asics can have mismatching dpp and opp counts and dml needs to account for this. Reviewed-by: Charlene Liu Signed-off-by: Dmytro Laktyushkin Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- .../dml2/dml21/src/dml2_core/dml2_core_dcn4.c | 1 + .../src/dml2_core/dml2_core_dcn4_calcs.c | 27 ++++++++++++++++--- .../src/dml2_core/dml2_core_shared_types.h | 3 +++ 3 files changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c index 6ee37386f6728..eba948e187c11 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c @@ -28,6 +28,7 @@ struct dml2_core_ip_params core_dcn4_ip_caps_base = { .writeback_interface_buffer_size_kbytes = 90, //Number of pipes after DCN Pipe harvesting .max_num_dpp = 4, + .max_num_opp = 4, .max_num_otg = 4, .max_num_wb = 1, .max_dchub_pscl_bw_pix_per_clk = 4, diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index 4ccdb179b001d..f16792f79befa 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -4047,7 +4047,9 @@ static bool ValidateODMMode(enum dml2_odm_mode ODMMode, bool UseDSC, unsigned int NumberOfDSCSlices, unsigned int TotalNumberOfActiveDPP, + unsigned int TotalNumberOfActiveOPP, unsigned int MaxNumDPP, + unsigned int MaxNumOPP, double DISPCLKRequired, unsigned int NumberOfDPPRequired, unsigned int MaxHActiveForDSC, @@ -4063,7 +4065,7 @@ static bool ValidateODMMode(enum dml2_odm_mode ODMMode, if (DISPCLKRequired > MaxDispclk) return false; - if ((TotalNumberOfActiveDPP + NumberOfDPPRequired) > MaxNumDPP) + if ((TotalNumberOfActiveDPP + NumberOfDPPRequired) > MaxNumDPP || (TotalNumberOfActiveOPP + NumberOfDPPRequired) > MaxNumOPP) return false; if (are_odm_segments_symmetrical) { if (HActive % (NumberOfDPPRequired * pixels_per_clock_cycle)) @@ -4109,7 +4111,9 @@ static noinline_for_stack void CalculateODMMode( double MaxDispclk, bool DSCEnable, unsigned int TotalNumberOfActiveDPP, + unsigned int TotalNumberOfActiveOPP, unsigned int MaxNumDPP, + unsigned int MaxNumOPP, double PixelClock, unsigned int NumberOfDSCSlices, @@ -4179,7 +4183,9 @@ static noinline_for_stack void CalculateODMMode( UseDSC, NumberOfDSCSlices, TotalNumberOfActiveDPP, + TotalNumberOfActiveOPP, MaxNumDPP, + MaxNumOPP, DISPCLKRequired, NumberOfDPPRequired, MaxHActiveForDSC, @@ -8358,6 +8364,7 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out CalculateSwathAndDETConfiguration(&mode_lib->scratch, CalculateSwathAndDETConfiguration_params); mode_lib->ms.TotalNumberOfActiveDPP = 0; + mode_lib->ms.TotalNumberOfActiveOPP = 0; mode_lib->ms.support.TotalAvailablePipesSupport = true; for (k = 0; k < mode_lib->ms.num_active_planes; ++k) { @@ -8393,7 +8400,9 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out mode_lib->ms.max_dispclk_freq_mhz, false, // DSCEnable mode_lib->ms.TotalNumberOfActiveDPP, + mode_lib->ms.TotalNumberOfActiveOPP, mode_lib->ip.max_num_dpp, + mode_lib->ip.max_num_opp, ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000), mode_lib->ms.support.NumberOfDSCSlices[k], @@ -8412,7 +8421,9 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out mode_lib->ms.max_dispclk_freq_mhz, true, // DSCEnable mode_lib->ms.TotalNumberOfActiveDPP, + mode_lib->ms.TotalNumberOfActiveOPP, mode_lib->ip.max_num_dpp, + mode_lib->ip.max_num_opp, ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.pixel_clock_khz / 1000), mode_lib->ms.support.NumberOfDSCSlices[k], @@ -8516,20 +8527,23 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out for (k = 0; k < mode_lib->ms.num_active_planes; ++k) { mode_lib->ms.MPCCombine[k] = false; mode_lib->ms.NoOfDPP[k] = 1; + mode_lib->ms.NoOfOPP[k] = 1; if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_4to1) { mode_lib->ms.MPCCombine[k] = false; mode_lib->ms.NoOfDPP[k] = 4; + mode_lib->ms.NoOfOPP[k] = 4; } else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_3to1) { mode_lib->ms.MPCCombine[k] = false; mode_lib->ms.NoOfDPP[k] = 3; + mode_lib->ms.NoOfOPP[k] = 3; } else if (mode_lib->ms.ODMMode[k] == dml2_odm_mode_combine_2to1) { mode_lib->ms.MPCCombine[k] = false; mode_lib->ms.NoOfDPP[k] = 2; + mode_lib->ms.NoOfOPP[k] = 2; } else if (display_cfg->plane_descriptors[k].overrides.mpcc_combine_factor == 2) { mode_lib->ms.MPCCombine[k] = true; mode_lib->ms.NoOfDPP[k] = 2; - mode_lib->ms.TotalNumberOfActiveDPP++; } else if (display_cfg->plane_descriptors[k].overrides.mpcc_combine_factor == 1) { mode_lib->ms.MPCCombine[k] = false; mode_lib->ms.NoOfDPP[k] = 1; @@ -8540,7 +8554,6 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out if ((mode_lib->ms.MinDPPCLKUsingSingleDPP[k] > mode_lib->ms.max_dppclk_freq_mhz) || !mode_lib->ms.SingleDPPViewportSizeSupportPerSurface[k]) { mode_lib->ms.MPCCombine[k] = true; mode_lib->ms.NoOfDPP[k] = 2; - mode_lib->ms.TotalNumberOfActiveDPP++; } } #if defined(__DML_VBA_DEBUG__) @@ -8548,8 +8561,16 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out #endif } + mode_lib->ms.TotalNumberOfActiveDPP = 0; + mode_lib->ms.TotalNumberOfActiveOPP = 0; + for (k = 0; k < mode_lib->ms.num_active_planes; ++k) { + mode_lib->ms.TotalNumberOfActiveDPP += mode_lib->ms.NoOfDPP[k]; + mode_lib->ms.TotalNumberOfActiveOPP += mode_lib->ms.NoOfOPP[k]; + } if (mode_lib->ms.TotalNumberOfActiveDPP > (unsigned int)mode_lib->ip.max_num_dpp) mode_lib->ms.support.TotalAvailablePipesSupport = false; + if (mode_lib->ms.TotalNumberOfActiveOPP > (unsigned int)mode_lib->ip.max_num_opp) + mode_lib->ms.support.TotalAvailablePipesSupport = false; mode_lib->ms.TotalNumberOfSingleDPPSurfaces = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h index ff1c47347610a..051c31ec2f0e4 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h @@ -36,6 +36,7 @@ struct dml2_core_ip_params { unsigned int max_line_buffer_lines; unsigned int writeback_interface_buffer_size_kbytes; unsigned int max_num_dpp; + unsigned int max_num_opp; unsigned int max_num_otg; unsigned int TDLUT_33cube_count; unsigned int max_num_wb; @@ -570,6 +571,7 @@ struct dml2_core_internal_mode_support { enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; unsigned int SurfaceSizeInMALL[DML2_MAX_PLANES]; unsigned int NoOfDPP[DML2_MAX_PLANES]; + unsigned int NoOfOPP[DML2_MAX_PLANES]; bool MPCCombine[DML2_MAX_PLANES]; double dcfclk_deepsleep; double MinDPPCLKUsingSingleDPP[DML2_MAX_PLANES]; @@ -580,6 +582,7 @@ struct dml2_core_internal_mode_support { bool PTEBufferSizeNotExceeded[DML2_MAX_PLANES]; bool DCCMetaBufferSizeNotExceeded[DML2_MAX_PLANES]; unsigned int TotalNumberOfActiveDPP; + unsigned int TotalNumberOfActiveOPP; unsigned int TotalNumberOfSingleDPPSurfaces; unsigned int TotalNumberOfDCCActiveDPP; unsigned int Total3dlutActive; From e3497f20147fa701359dc7777faddf42c6530ca1 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Tue, 7 Oct 2025 10:40:26 -0400 Subject: [PATCH 2356/2653] drm/amd/display: Fix wrong index for DCN401 cursor offload [Why] Payloads are ignored because the wrong index is written as part of the pipe update implementation for DCN401. [How] Align it to the DCN35 implementation and ensure the + 1 is added. Reviewed-by: Alvin Lee Signed-off-by: Nicholas Kazlauskas Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 23ecab4bcbba8..b9c357a407074 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -2978,7 +2978,7 @@ void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pip return; stream_idx = top_pipe->pipe_idx; - write_idx = cs->offload_streams[stream_idx].write_idx; + write_idx = cs->offload_streams[stream_idx].write_idx + 1; /* new payload (+1) */ payload_idx = write_idx % ARRAY_SIZE(cs->offload_streams[stream_idx].payloads); p = &cs->offload_streams[stream_idx].payloads[payload_idx].pipe_data[pipe->pipe_idx].dcn401; From 15147850c751003683a22573511f22807679456f Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Tue, 7 Oct 2025 10:39:07 -0400 Subject: [PATCH 2357/2653] drm/amd/display: Fix notification of vtotal to DMU for cursor offload [Why] It was placed after the early return and the notification is never sent. [How] Place it after .set_drr and before the return. Reviewed-by: Alvin Lee Signed-off-by: Nicholas Kazlauskas Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 2900bc7b0704f..3f89ede61e73f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -493,13 +493,14 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, 1, *adjust); stream->adjust.timing_adjust_pending = false; + + if (dc->hwss.notify_cursor_offload_drr_update) + dc->hwss.notify_cursor_offload_drr_update(dc, dc->current_state, stream); + return true; } } - if (dc->hwss.notify_cursor_offload_drr_update) - dc->hwss.notify_cursor_offload_drr_update(dc, dc->current_state, stream); - return false; } From 7f0414985f59bb752ddb87a0872eec376709e799 Mon Sep 17 00:00:00 2001 From: Karen Chen Date: Wed, 15 Oct 2025 11:13:07 -0400 Subject: [PATCH 2358/2653] drm/amd/display: Add more DC HW state info to underflow logging [Why] Debugging underflow issues frequently requires knowing the HW state at the time of underflow. To enable capturing this HW state information, interface functions are needed for the various DC HW blocks. [How] This change adds the interface functions to read HW state for the following DC HW blocks: - HUBBUB - HUBP - DPP - MPC - OPP - DSC - OPTC - DCCG Reviewed-by: George Shen Signed-off-by: Karen Chen Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 30 ++-- .../amd/display/dc/dccg/dcn20/dcn20_dccg.h | 64 +++++++- .../amd/display/dc/dccg/dcn31/dcn31_dccg.c | 123 +++++++++++++++ .../amd/display/dc/dccg/dcn31/dcn31_dccg.h | 2 + .../amd/display/dc/dccg/dcn314/dcn314_dccg.c | 3 +- .../amd/display/dc/dccg/dcn314/dcn314_dccg.h | 3 +- .../amd/display/dc/dccg/dcn35/dcn35_dccg.c | 1 + .../amd/display/dc/dccg/dcn35/dcn35_dccg.h | 5 +- .../amd/display/dc/dccg/dcn401/dcn401_dccg.c | 1 + .../drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h | 4 +- .../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 16 ++ .../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h | 2 + .../drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c | 1 + .../drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c | 1 + .../amd/display/dc/dpp/dcn401/dcn401_dpp.c | 1 + .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 8 + .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h | 1 + .../drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c | 1 + .../amd/display/dc/dsc/dcn401/dcn401_dsc.c | 1 + drivers/gpu/drm/amd/display/dc/dsc/dsc.h | 5 + .../display/dc/hubbub/dcn30/dcn30_hubbub.c | 33 +--- .../display/dc/hubbub/dcn30/dcn30_hubbub.h | 6 +- .../display/dc/hubbub/dcn31/dcn31_hubbub.c | 3 +- .../display/dc/hubbub/dcn32/dcn32_hubbub.c | 3 +- .../display/dc/hubbub/dcn35/dcn35_hubbub.c | 3 +- .../display/dc/hubbub/dcn401/dcn401_hubbub.c | 3 +- .../amd/display/dc/hubp/dcn10/dcn10_hubp.h | 136 +++++++++++++++- .../amd/display/dc/hubp/dcn20/dcn20_hubp.h | 8 +- .../amd/display/dc/hubp/dcn30/dcn30_hubp.c | 147 ++++++++++++++---- .../amd/display/dc/hubp/dcn30/dcn30_hubp.h | 2 + .../amd/display/dc/hubp/dcn31/dcn31_hubp.c | 4 +- .../amd/display/dc/hubp/dcn32/dcn32_hubp.c | 4 +- .../amd/display/dc/hubp/dcn35/dcn35_hubp.c | 4 +- .../amd/display/dc/hubp/dcn401/dcn401_hubp.c | 4 +- .../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 76 ++++----- drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 121 +++++++++++++- .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 12 +- drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 16 +- drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 1 + drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 27 ++++ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 13 ++ .../amd/display/dc/inc/hw/timing_generator.h | 130 ++++++++++++++++ .../drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c | 16 ++ .../drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h | 5 + .../drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c | 1 + .../amd/display/dc/mpc/dcn401/dcn401_mpc.c | 1 + .../drm/amd/display/dc/opp/dcn10/dcn10_opp.c | 14 +- .../drm/amd/display/dc/opp/dcn10/dcn10_opp.h | 6 +- .../drm/amd/display/dc/opp/dcn20/dcn20_opp.c | 13 ++ .../drm/amd/display/dc/opp/dcn20/dcn20_opp.h | 6 +- .../drm/amd/display/dc/opp/dcn35/dcn35_opp.c | 13 ++ .../drm/amd/display/dc/opp/dcn35/dcn35_opp.h | 4 +- .../amd/display/dc/optc/dcn10/dcn10_optc.h | 38 ++++- .../amd/display/dc/optc/dcn31/dcn31_optc.c | 131 ++++++++++++++++ .../amd/display/dc/optc/dcn31/dcn31_optc.h | 2 + .../amd/display/dc/optc/dcn314/dcn314_optc.c | 1 + .../amd/display/dc/optc/dcn32/dcn32_optc.c | 1 + .../amd/display/dc/optc/dcn35/dcn35_optc.c | 1 + .../amd/display/dc/optc/dcn401/dcn401_optc.c | 1 + 59 files changed, 1133 insertions(+), 150 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e917c65eedd78..319630c813bc9 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -54,6 +54,14 @@ struct abm_save_restore; struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; +struct dcn_hubbub_reg_state; +struct dcn_hubp_reg_state; +struct dcn_dpp_reg_state; +struct dcn_mpc_reg_state; +struct dcn_opp_reg_state; +struct dcn_dsc_reg_state; +struct dcn_optc_reg_state; +struct dcn_dccg_reg_state; #define DC_VER "3.2.355" @@ -1834,20 +1842,14 @@ struct dc_surface_update { }; struct dc_underflow_debug_data { - uint32_t otg_inst; - uint32_t otg_underflow; - uint32_t h_position; - uint32_t v_position; - uint32_t otg_frame_count; - struct dc_underflow_per_hubp_debug_data { - uint32_t hubp_underflow; - uint32_t hubp_in_blank; - uint32_t hubp_readline; - uint32_t det_config_error; - } hubps[MAX_PIPES]; - uint32_t curr_det_sizes[MAX_PIPES]; - uint32_t target_det_sizes[MAX_PIPES]; - uint32_t compbuf_config_error; + struct dcn_hubbub_reg_state *hubbub_reg_state; + struct dcn_hubp_reg_state *hubp_reg_state[MAX_PIPES]; + struct dcn_dpp_reg_state *dpp_reg_state[MAX_PIPES]; + struct dcn_mpc_reg_state *mpc_reg_state[MAX_PIPES]; + struct dcn_opp_reg_state *opp_reg_state[MAX_PIPES]; + struct dcn_dsc_reg_state *dsc_reg_state[MAX_PIPES]; + struct dcn_optc_reg_state *optc_reg_state[MAX_PIPES]; + struct dcn_dccg_reg_state *dccg_reg_state[MAX_PIPES]; }; /* diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h index a9b88f5e0c04e..8bdffd9ff31b1 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h @@ -425,7 +425,69 @@ struct dccg_mask { uint32_t SYMCLKD_CLOCK_ENABLE; \ uint32_t SYMCLKE_CLOCK_ENABLE; \ uint32_t DP_DTO_MODULO[MAX_PIPES]; \ - uint32_t DP_DTO_PHASE[MAX_PIPES] + uint32_t DP_DTO_PHASE[MAX_PIPES]; \ + uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; \ + uint32_t DCCG_AUDIO_DTO0_MODULE; \ + uint32_t DCCG_AUDIO_DTO0_PHASE; \ + uint32_t DCCG_AUDIO_DTO1_MODULE; \ + uint32_t DCCG_AUDIO_DTO1_PHASE; \ + uint32_t DCCG_CAC_STATUS; \ + uint32_t DCCG_CAC_STATUS2; \ + uint32_t DCCG_DISP_CNTL_REG; \ + uint32_t DCCG_DS_CNTL; \ + uint32_t DCCG_DS_DTO_INCR; \ + uint32_t DCCG_DS_DTO_MODULO; \ + uint32_t DCCG_DS_HW_CAL_INTERVAL; \ + uint32_t DCCG_GTC_CNTL; \ + uint32_t DCCG_GTC_CURRENT; \ + uint32_t DCCG_GTC_DTO_INCR; \ + uint32_t DCCG_GTC_DTO_MODULO; \ + uint32_t DCCG_PERFMON_CNTL; \ + uint32_t DCCG_PERFMON_CNTL2; \ + uint32_t DCCG_SOFT_RESET; \ + uint32_t DCCG_TEST_CLK_SEL; \ + uint32_t DCCG_VSYNC_CNT_CTRL; \ + uint32_t DCCG_VSYNC_CNT_INT_CTRL; \ + uint32_t DCCG_VSYNC_OTG0_LATCH_VALUE; \ + uint32_t DCCG_VSYNC_OTG1_LATCH_VALUE; \ + uint32_t DCCG_VSYNC_OTG2_LATCH_VALUE; \ + uint32_t DCCG_VSYNC_OTG3_LATCH_VALUE; \ + uint32_t DCCG_VSYNC_OTG4_LATCH_VALUE; \ + uint32_t DCCG_VSYNC_OTG5_LATCH_VALUE; \ + uint32_t DISPCLK_CGTT_BLK_CTRL_REG; \ + uint32_t DP_DTO_DBUF_EN; \ + uint32_t DPIACLK_540M_DTO_MODULO; \ + uint32_t DPIACLK_540M_DTO_PHASE; \ + uint32_t DPIACLK_810M_DTO_MODULO; \ + uint32_t DPIACLK_810M_DTO_PHASE; \ + uint32_t DPIACLK_DTO_CNTL; \ + uint32_t DPIASYMCLK_CNTL; \ + uint32_t DPPCLK_CGTT_BLK_CTRL_REG; \ + uint32_t DPREFCLK_CGTT_BLK_CTRL_REG; \ + uint32_t DPREFCLK_CNTL; \ + uint32_t DTBCLK_DTO_DBUF_EN; \ + uint32_t FORCE_SYMCLK_DISABLE; \ + uint32_t HDMICHARCLK0_CLOCK_CNTL; \ + uint32_t MICROSECOND_TIME_BASE_DIV; \ + uint32_t MILLISECOND_TIME_BASE_DIV; \ + uint32_t OTG0_PHYPLL_PIXEL_RATE_CNTL; \ + uint32_t OTG0_PIXEL_RATE_CNTL; \ + uint32_t OTG1_PHYPLL_PIXEL_RATE_CNTL; \ + uint32_t OTG1_PIXEL_RATE_CNTL; \ + uint32_t OTG2_PHYPLL_PIXEL_RATE_CNTL; \ + uint32_t OTG2_PIXEL_RATE_CNTL; \ + uint32_t OTG3_PHYPLL_PIXEL_RATE_CNTL; \ + uint32_t OTG3_PIXEL_RATE_CNTL; \ + uint32_t PHYPLLA_PIXCLK_RESYNC_CNTL; \ + uint32_t PHYPLLB_PIXCLK_RESYNC_CNTL; \ + uint32_t PHYPLLC_PIXCLK_RESYNC_CNTL; \ + uint32_t PHYPLLD_PIXCLK_RESYNC_CNTL; \ + uint32_t PHYPLLE_PIXCLK_RESYNC_CNTL; \ + uint32_t REFCLK_CGTT_BLK_CTRL_REG; \ + uint32_t SOCCLK_CGTT_BLK_CTRL_REG; \ + uint32_t SYMCLK_CGTT_BLK_CTRL_REG; \ + uint32_t SYMCLK_PSP_CNTL + struct dccg_registers { DCCG_REG_VARIABLE_LIST; }; diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c index 8664f0c4c9b76..97df04b7e39d1 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c @@ -709,6 +709,128 @@ void dccg31_otg_drop_pixel(struct dccg *dccg, OTG_DROP_PIXEL[otg_inst], 1); } +void dccg31_read_reg_state(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + dccg_reg_state->dc_mem_global_pwr_req_cntl = REG_READ(DC_MEM_GLOBAL_PWR_REQ_CNTL); + dccg_reg_state->dccg_audio_dtbclk_dto_modulo = REG_READ(DCCG_AUDIO_DTBCLK_DTO_MODULO); + dccg_reg_state->dccg_audio_dtbclk_dto_phase = REG_READ(DCCG_AUDIO_DTBCLK_DTO_PHASE); + dccg_reg_state->dccg_audio_dto_source = REG_READ(DCCG_AUDIO_DTO_SOURCE); + dccg_reg_state->dccg_audio_dto0_module = REG_READ(DCCG_AUDIO_DTO0_MODULE); + dccg_reg_state->dccg_audio_dto0_phase = REG_READ(DCCG_AUDIO_DTO0_PHASE); + dccg_reg_state->dccg_audio_dto1_module = REG_READ(DCCG_AUDIO_DTO1_MODULE); + dccg_reg_state->dccg_audio_dto1_phase = REG_READ(DCCG_AUDIO_DTO1_PHASE); + dccg_reg_state->dccg_cac_status = REG_READ(DCCG_CAC_STATUS); + dccg_reg_state->dccg_cac_status2 = REG_READ(DCCG_CAC_STATUS2); + dccg_reg_state->dccg_disp_cntl_reg = REG_READ(DCCG_DISP_CNTL_REG); + dccg_reg_state->dccg_ds_cntl = REG_READ(DCCG_DS_CNTL); + dccg_reg_state->dccg_ds_dto_incr = REG_READ(DCCG_DS_DTO_INCR); + dccg_reg_state->dccg_ds_dto_modulo = REG_READ(DCCG_DS_DTO_MODULO); + dccg_reg_state->dccg_ds_hw_cal_interval = REG_READ(DCCG_DS_HW_CAL_INTERVAL); + dccg_reg_state->dccg_gate_disable_cntl = REG_READ(DCCG_GATE_DISABLE_CNTL); + dccg_reg_state->dccg_gate_disable_cntl2 = REG_READ(DCCG_GATE_DISABLE_CNTL2); + dccg_reg_state->dccg_gate_disable_cntl3 = REG_READ(DCCG_GATE_DISABLE_CNTL3); + dccg_reg_state->dccg_gate_disable_cntl4 = REG_READ(DCCG_GATE_DISABLE_CNTL4); + dccg_reg_state->dccg_gate_disable_cntl5 = REG_READ(DCCG_GATE_DISABLE_CNTL5); + dccg_reg_state->dccg_gate_disable_cntl6 = REG_READ(DCCG_GATE_DISABLE_CNTL6); + dccg_reg_state->dccg_global_fgcg_rep_cntl = REG_READ(DCCG_GLOBAL_FGCG_REP_CNTL); + dccg_reg_state->dccg_gtc_cntl = REG_READ(DCCG_GTC_CNTL); + dccg_reg_state->dccg_gtc_current = REG_READ(DCCG_GTC_CURRENT); + dccg_reg_state->dccg_gtc_dto_incr = REG_READ(DCCG_GTC_DTO_INCR); + dccg_reg_state->dccg_gtc_dto_modulo = REG_READ(DCCG_GTC_DTO_MODULO); + dccg_reg_state->dccg_perfmon_cntl = REG_READ(DCCG_PERFMON_CNTL); + dccg_reg_state->dccg_perfmon_cntl2 = REG_READ(DCCG_PERFMON_CNTL2); + dccg_reg_state->dccg_soft_reset = REG_READ(DCCG_SOFT_RESET); + dccg_reg_state->dccg_test_clk_sel = REG_READ(DCCG_TEST_CLK_SEL); + dccg_reg_state->dccg_vsync_cnt_ctrl = REG_READ(DCCG_VSYNC_CNT_CTRL); + dccg_reg_state->dccg_vsync_cnt_int_ctrl = REG_READ(DCCG_VSYNC_CNT_INT_CTRL); + dccg_reg_state->dccg_vsync_otg0_latch_value = REG_READ(DCCG_VSYNC_OTG0_LATCH_VALUE); + dccg_reg_state->dccg_vsync_otg1_latch_value = REG_READ(DCCG_VSYNC_OTG1_LATCH_VALUE); + dccg_reg_state->dccg_vsync_otg2_latch_value = REG_READ(DCCG_VSYNC_OTG2_LATCH_VALUE); + dccg_reg_state->dccg_vsync_otg3_latch_value = REG_READ(DCCG_VSYNC_OTG3_LATCH_VALUE); + dccg_reg_state->dccg_vsync_otg4_latch_value = REG_READ(DCCG_VSYNC_OTG4_LATCH_VALUE); + dccg_reg_state->dccg_vsync_otg5_latch_value = REG_READ(DCCG_VSYNC_OTG5_LATCH_VALUE); + dccg_reg_state->dispclk_cgtt_blk_ctrl_reg = REG_READ(DISPCLK_CGTT_BLK_CTRL_REG); + dccg_reg_state->dispclk_freq_change_cntl = REG_READ(DISPCLK_FREQ_CHANGE_CNTL); + dccg_reg_state->dp_dto_dbuf_en = REG_READ(DP_DTO_DBUF_EN); + dccg_reg_state->dp_dto0_modulo = REG_READ(DP_DTO_MODULO[0]); + dccg_reg_state->dp_dto0_phase = REG_READ(DP_DTO_PHASE[0]); + dccg_reg_state->dp_dto1_modulo = REG_READ(DP_DTO_MODULO[1]); + dccg_reg_state->dp_dto1_phase = REG_READ(DP_DTO_PHASE[1]); + dccg_reg_state->dp_dto2_modulo = REG_READ(DP_DTO_MODULO[2]); + dccg_reg_state->dp_dto2_phase = REG_READ(DP_DTO_PHASE[2]); + dccg_reg_state->dp_dto3_modulo = REG_READ(DP_DTO_MODULO[3]); + dccg_reg_state->dp_dto3_phase = REG_READ(DP_DTO_PHASE[3]); + dccg_reg_state->dpiaclk_540m_dto_modulo = REG_READ(DPIACLK_540M_DTO_MODULO); + dccg_reg_state->dpiaclk_540m_dto_phase = REG_READ(DPIACLK_540M_DTO_PHASE); + dccg_reg_state->dpiaclk_810m_dto_modulo = REG_READ(DPIACLK_810M_DTO_MODULO); + dccg_reg_state->dpiaclk_810m_dto_phase = REG_READ(DPIACLK_810M_DTO_PHASE); + dccg_reg_state->dpiaclk_dto_cntl = REG_READ(DPIACLK_DTO_CNTL); + dccg_reg_state->dpiasymclk_cntl = REG_READ(DPIASYMCLK_CNTL); + dccg_reg_state->dppclk_cgtt_blk_ctrl_reg = REG_READ(DPPCLK_CGTT_BLK_CTRL_REG); + dccg_reg_state->dppclk_ctrl = REG_READ(DPPCLK_CTRL); + dccg_reg_state->dppclk_dto_ctrl = REG_READ(DPPCLK_DTO_CTRL); + dccg_reg_state->dppclk0_dto_param = REG_READ(DPPCLK_DTO_PARAM[0]); + dccg_reg_state->dppclk1_dto_param = REG_READ(DPPCLK_DTO_PARAM[1]); + dccg_reg_state->dppclk2_dto_param = REG_READ(DPPCLK_DTO_PARAM[2]); + dccg_reg_state->dppclk3_dto_param = REG_READ(DPPCLK_DTO_PARAM[3]); + dccg_reg_state->dprefclk_cgtt_blk_ctrl_reg = REG_READ(DPREFCLK_CGTT_BLK_CTRL_REG); + dccg_reg_state->dprefclk_cntl = REG_READ(DPREFCLK_CNTL); + dccg_reg_state->dpstreamclk_cntl = REG_READ(DPSTREAMCLK_CNTL); + dccg_reg_state->dscclk_dto_ctrl = REG_READ(DSCCLK_DTO_CTRL); + dccg_reg_state->dscclk0_dto_param = REG_READ(DSCCLK0_DTO_PARAM); + dccg_reg_state->dscclk1_dto_param = REG_READ(DSCCLK1_DTO_PARAM); + dccg_reg_state->dscclk2_dto_param = REG_READ(DSCCLK2_DTO_PARAM); + dccg_reg_state->dscclk3_dto_param = REG_READ(DSCCLK3_DTO_PARAM); + dccg_reg_state->dtbclk_dto_dbuf_en = REG_READ(DTBCLK_DTO_DBUF_EN); + dccg_reg_state->dtbclk_dto0_modulo = REG_READ(DTBCLK_DTO_MODULO[0]); + dccg_reg_state->dtbclk_dto0_phase = REG_READ(DTBCLK_DTO_PHASE[0]); + dccg_reg_state->dtbclk_dto1_modulo = REG_READ(DTBCLK_DTO_MODULO[1]); + dccg_reg_state->dtbclk_dto1_phase = REG_READ(DTBCLK_DTO_PHASE[1]); + dccg_reg_state->dtbclk_dto2_modulo = REG_READ(DTBCLK_DTO_MODULO[2]); + dccg_reg_state->dtbclk_dto2_phase = REG_READ(DTBCLK_DTO_PHASE[2]); + dccg_reg_state->dtbclk_dto3_modulo = REG_READ(DTBCLK_DTO_MODULO[3]); + dccg_reg_state->dtbclk_dto3_phase = REG_READ(DTBCLK_DTO_PHASE[3]); + dccg_reg_state->dtbclk_p_cntl = REG_READ(DTBCLK_P_CNTL); + dccg_reg_state->force_symclk_disable = REG_READ(FORCE_SYMCLK_DISABLE); + dccg_reg_state->hdmicharclk0_clock_cntl = REG_READ(HDMICHARCLK0_CLOCK_CNTL); + dccg_reg_state->hdmistreamclk_cntl = REG_READ(HDMISTREAMCLK_CNTL); + dccg_reg_state->hdmistreamclk0_dto_param = REG_READ(HDMISTREAMCLK0_DTO_PARAM); + dccg_reg_state->microsecond_time_base_div = REG_READ(MICROSECOND_TIME_BASE_DIV); + dccg_reg_state->millisecond_time_base_div = REG_READ(MILLISECOND_TIME_BASE_DIV); + dccg_reg_state->otg_pixel_rate_div = REG_READ(OTG_PIXEL_RATE_DIV); + dccg_reg_state->otg0_phypll_pixel_rate_cntl = REG_READ(OTG0_PHYPLL_PIXEL_RATE_CNTL); + dccg_reg_state->otg0_pixel_rate_cntl = REG_READ(OTG0_PIXEL_RATE_CNTL); + dccg_reg_state->otg1_phypll_pixel_rate_cntl = REG_READ(OTG1_PHYPLL_PIXEL_RATE_CNTL); + dccg_reg_state->otg1_pixel_rate_cntl = REG_READ(OTG1_PIXEL_RATE_CNTL); + dccg_reg_state->otg2_phypll_pixel_rate_cntl = REG_READ(OTG2_PHYPLL_PIXEL_RATE_CNTL); + dccg_reg_state->otg2_pixel_rate_cntl = REG_READ(OTG2_PIXEL_RATE_CNTL); + dccg_reg_state->otg3_phypll_pixel_rate_cntl = REG_READ(OTG3_PHYPLL_PIXEL_RATE_CNTL); + dccg_reg_state->otg3_pixel_rate_cntl = REG_READ(OTG3_PIXEL_RATE_CNTL); + dccg_reg_state->phyasymclk_clock_cntl = REG_READ(PHYASYMCLK_CLOCK_CNTL); + dccg_reg_state->phybsymclk_clock_cntl = REG_READ(PHYBSYMCLK_CLOCK_CNTL); + dccg_reg_state->phycsymclk_clock_cntl = REG_READ(PHYCSYMCLK_CLOCK_CNTL); + dccg_reg_state->phydsymclk_clock_cntl = REG_READ(PHYDSYMCLK_CLOCK_CNTL); + dccg_reg_state->phyesymclk_clock_cntl = REG_READ(PHYESYMCLK_CLOCK_CNTL); + dccg_reg_state->phyplla_pixclk_resync_cntl = REG_READ(PHYPLLA_PIXCLK_RESYNC_CNTL); + dccg_reg_state->phypllb_pixclk_resync_cntl = REG_READ(PHYPLLB_PIXCLK_RESYNC_CNTL); + dccg_reg_state->phypllc_pixclk_resync_cntl = REG_READ(PHYPLLC_PIXCLK_RESYNC_CNTL); + dccg_reg_state->phyplld_pixclk_resync_cntl = REG_READ(PHYPLLD_PIXCLK_RESYNC_CNTL); + dccg_reg_state->phyplle_pixclk_resync_cntl = REG_READ(PHYPLLE_PIXCLK_RESYNC_CNTL); + dccg_reg_state->refclk_cgtt_blk_ctrl_reg = REG_READ(REFCLK_CGTT_BLK_CTRL_REG); + dccg_reg_state->socclk_cgtt_blk_ctrl_reg = REG_READ(SOCCLK_CGTT_BLK_CTRL_REG); + dccg_reg_state->symclk_cgtt_blk_ctrl_reg = REG_READ(SYMCLK_CGTT_BLK_CTRL_REG); + dccg_reg_state->symclk_psp_cntl = REG_READ(SYMCLK_PSP_CNTL); + dccg_reg_state->symclk32_le_cntl = REG_READ(SYMCLK32_LE_CNTL); + dccg_reg_state->symclk32_se_cntl = REG_READ(SYMCLK32_SE_CNTL); + dccg_reg_state->symclka_clock_enable = REG_READ(SYMCLKA_CLOCK_ENABLE); + dccg_reg_state->symclkb_clock_enable = REG_READ(SYMCLKB_CLOCK_ENABLE); + dccg_reg_state->symclkc_clock_enable = REG_READ(SYMCLKC_CLOCK_ENABLE); + dccg_reg_state->symclkd_clock_enable = REG_READ(SYMCLKD_CLOCK_ENABLE); + dccg_reg_state->symclke_clock_enable = REG_READ(SYMCLKE_CLOCK_ENABLE); +} + static const struct dccg_funcs dccg31_funcs = { .update_dpp_dto = dccg31_update_dpp_dto, .get_dccg_ref_freq = dccg31_get_dccg_ref_freq, @@ -727,6 +849,7 @@ static const struct dccg_funcs dccg31_funcs = { .set_dispclk_change_mode = dccg31_set_dispclk_change_mode, .disable_dsc = dccg31_disable_dscclk, .enable_dsc = dccg31_enable_dscclk, + .dccg_read_reg_state = dccg31_read_reg_state, }; struct dccg *dccg31_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h index cd261051dc2c5..bf659920d4cc2 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h @@ -236,4 +236,6 @@ void dccg31_disable_dscclk(struct dccg *dccg, int inst); void dccg31_enable_dscclk(struct dccg *dccg, int inst); +void dccg31_read_reg_state(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state); + #endif //__DCN31_DCCG_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c index 8f6edd8e9bebb..ef3db6beba25c 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c @@ -377,7 +377,8 @@ static const struct dccg_funcs dccg314_funcs = { .get_pixel_rate_div = dccg314_get_pixel_rate_div, .trigger_dio_fifo_resync = dccg314_trigger_dio_fifo_resync, .set_valid_pixel_rate = dccg314_set_valid_pixel_rate, - .set_dtbclk_p_src = dccg314_set_dtbclk_p_src + .set_dtbclk_p_src = dccg314_set_dtbclk_p_src, + .dccg_read_reg_state = dccg31_read_reg_state }; struct dccg *dccg314_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h index 60ea1d248deba..a609635f35dbd 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h @@ -74,8 +74,7 @@ SR(DCCG_GATE_DISABLE_CNTL3),\ SR(HDMISTREAMCLK0_DTO_PARAM),\ SR(OTG_PIXEL_RATE_DIV),\ - SR(DTBCLK_P_CNTL),\ - SR(DCCG_AUDIO_DTO_SOURCE) + SR(DTBCLK_P_CNTL) #define DCCG_MASK_SH_LIST_DCN314_COMMON(mask_sh) \ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index 0aa41759f79d3..bd2f528137b20 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -2453,6 +2453,7 @@ static const struct dccg_funcs dccg35_funcs = { .disable_symclk_se = dccg35_disable_symclk_se, .set_dtbclk_p_src = dccg35_set_dtbclk_p_src, .dccg_root_gate_disable_control = dccg35_root_gate_disable_control, + .dccg_read_reg_state = dccg31_read_reg_state, }; struct dccg *dccg35_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h index ad7a5850d31b5..7b9c36456cd9b 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h @@ -41,8 +41,9 @@ SR(SYMCLKA_CLOCK_ENABLE),\ SR(SYMCLKB_CLOCK_ENABLE),\ SR(SYMCLKC_CLOCK_ENABLE),\ - SR(SYMCLKD_CLOCK_ENABLE),\ - SR(SYMCLKE_CLOCK_ENABLE) + SR(SYMCLKD_CLOCK_ENABLE), \ + SR(SYMCLKE_CLOCK_ENABLE),\ + SR(SYMCLK_PSP_CNTL) #define DCCG_MASK_SH_LIST_DCN35(mask_sh) \ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c index 0b8ed9b94d3c5..663a18ee51628 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c @@ -886,6 +886,7 @@ static const struct dccg_funcs dccg401_funcs = { .enable_symclk_se = dccg401_enable_symclk_se, .disable_symclk_se = dccg401_disable_symclk_se, .set_dtbclk_p_src = dccg401_set_dtbclk_p_src, + .dccg_read_reg_state = dccg31_read_reg_state }; struct dccg *dccg401_create( diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h index f466182963f75..b12f34345a586 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h @@ -1348,7 +1348,8 @@ struct dcn_dpp_mask { uint32_t CURSOR0_COLOR1; \ uint32_t DPP_CONTROL; \ uint32_t CM_HDR_MULT_COEF; \ - uint32_t CURSOR0_FP_SCALE_BIAS; + uint32_t CURSOR0_FP_SCALE_BIAS; \ + uint32_t OBUF_CONTROL; struct dcn_dpp_registers { DPP_COMMON_REG_VARIABLE_LIST @@ -1450,7 +1451,6 @@ void dpp1_set_degamma( void dpp1_set_degamma_pwl(struct dpp *dpp_base, const struct pwl_params *params); - void dpp_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s); diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c index fe52df01caf7b..ef4a161171814 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c @@ -84,6 +84,22 @@ void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) } } +void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state) +{ + struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); + + dpp_reg_state->recout_start = REG_READ(RECOUT_START); + dpp_reg_state->recout_size = REG_READ(RECOUT_SIZE); + dpp_reg_state->scl_horz_filter_scale_ratio = REG_READ(SCL_HORZ_FILTER_SCALE_RATIO); + dpp_reg_state->scl_vert_filter_scale_ratio = REG_READ(SCL_VERT_FILTER_SCALE_RATIO); + dpp_reg_state->scl_mode = REG_READ(SCL_MODE); + dpp_reg_state->cm_control = REG_READ(CM_CONTROL); + dpp_reg_state->dpp_control = REG_READ(DPP_CONTROL); + dpp_reg_state->dscl_control = REG_READ(DSCL_CONTROL); + dpp_reg_state->obuf_control = REG_READ(OBUF_CONTROL); + dpp_reg_state->mpc_size = REG_READ(MPC_SIZE); +} + /*program post scaler scs block in dpp CM*/ void dpp3_program_post_csc( struct dpp *dpp_base, diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h index f236824126e94..d4a70b4379eaf 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h @@ -594,6 +594,8 @@ void dpp3_program_CM_dealpha( void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s); +void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state); + bool dpp3_get_optimal_number_of_taps( struct dpp *dpp, struct scaler_data *scl_data, diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c index fa67e54bf94e6..8a5aa5e86850e 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c @@ -134,6 +134,7 @@ static struct dpp_funcs dcn32_dpp_funcs = { .dpp_dppclk_control = dpp1_dppclk_control, .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier, .dpp_get_gamut_remap = dpp3_cm_get_gamut_remap, + .dpp_read_reg_state = dpp30_read_reg_state, }; diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c index f7a373a3d70a5..977d83bf7741c 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c @@ -95,6 +95,7 @@ void dpp35_program_bias_and_scale_fcnv( static struct dpp_funcs dcn35_dpp_funcs = { .dpp_program_gamcor_lut = dpp3_program_gamcor_lut, .dpp_read_state = dpp30_read_state, + .dpp_read_reg_state = dpp30_read_reg_state, .dpp_reset = dpp_reset, .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale, .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps, diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c index 36187f890d5d0..96c2c853de42c 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c @@ -248,6 +248,7 @@ static struct dpp_funcs dcn401_dpp_funcs = { .set_optional_cursor_attributes = dpp401_set_optional_cursor_attributes, .dpp_dppclk_control = dpp1_dppclk_control, .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier, + .dpp_read_reg_state = dpp30_read_reg_state, .set_cursor_matrix = dpp401_set_cursor_matrix, }; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c index d7bacc3249a23..8111e738f5d53 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c @@ -35,6 +35,7 @@ static void dsc_write_to_registers(struct display_stream_compressor *dsc, const static const struct dsc_funcs dcn20_dsc_funcs = { .dsc_get_enc_caps = dsc2_get_enc_caps, .dsc_read_state = dsc2_read_state, + .dsc_read_reg_state = dsc2_read_reg_state, .dsc_validate_stream = dsc2_validate_stream, .dsc_set_config = dsc2_set_config, .dsc_get_packed_pps = dsc2_get_packed_pps, @@ -155,6 +156,13 @@ void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source); } +void dsc2_read_reg_state(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_reg_state) +{ + struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); + + dccg_reg_state->dsc_top_control = REG_READ(DSC_TOP_CONTROL); + dccg_reg_state->dscc_interrupt_control_status = REG_READ(DSCC_INTERRUPT_CONTROL_STATUS); +} bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) { diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h index 315c2b67d8dbe..e32299982bbec 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h @@ -606,6 +606,7 @@ bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, uint8_t *dsc_packed_pps); void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s); +void dsc2_read_reg_state(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_reg_state); bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, struct dsc_optc_config *dsc_optc_cfg); diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c index 6f4f5a3c48614..f9c6377ac66cf 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c @@ -32,6 +32,7 @@ static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe); static const struct dsc_funcs dcn35_dsc_funcs = { .dsc_get_enc_caps = dsc2_get_enc_caps, .dsc_read_state = dsc2_read_state, + .dsc_read_reg_state = dsc2_read_reg_state, .dsc_validate_stream = dsc2_validate_stream, .dsc_set_config = dsc2_set_config, .dsc_get_packed_pps = dsc2_get_packed_pps, diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c index 7bd92ae8b13e1..c1bdbb38c690b 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c @@ -26,6 +26,7 @@ static const struct dsc_funcs dcn401_dsc_funcs = { .dsc_disconnect = dsc401_disconnect, .dsc_wait_disconnect_pending_clear = dsc401_wait_disconnect_pending_clear, .dsc_get_single_enc_caps = dsc401_get_single_enc_caps, + .dsc_read_reg_state = dsc2_read_reg_state }; /* Macro definitios for REG_SET macros*/ diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dsc.h index b433e16842bf6..81c83d5fe0422 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dsc.h @@ -66,6 +66,10 @@ struct dcn_dsc_state { uint32_t dsc_opp_source; }; +struct dcn_dsc_reg_state { + uint32_t dsc_top_control; + uint32_t dscc_interrupt_control_status; +}; /* DSC encoder capabilities * They differ from the DPCD DSC caps because they are based on AMD DSC encoder caps. @@ -100,6 +104,7 @@ struct dsc_enc_caps { struct dsc_funcs { void (*dsc_get_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz); void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s); + void (*dsc_read_reg_state)(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_reg_state); bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, struct dsc_optc_config *dsc_optc_cfg); diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c index e7e5f6d4778e0..181a93dc46e69 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c @@ -440,33 +440,15 @@ void hubbub3_init_watermarks(struct hubbub *hubbub) REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, reg); } -void hubbub3_get_det_sizes(struct hubbub *hubbub, uint32_t *curr_det_sizes, uint32_t *target_det_sizes) +void hubbub3_read_reg_state(struct hubbub *hubbub, struct dcn_hubbub_reg_state *hubbub_reg_state) { struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); - REG_GET_2(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, &curr_det_sizes[0], - DET0_SIZE, &target_det_sizes[0]); - - REG_GET_2(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, &curr_det_sizes[1], - DET1_SIZE, &target_det_sizes[1]); - - REG_GET_2(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, &curr_det_sizes[2], - DET2_SIZE, &target_det_sizes[2]); - - REG_GET_2(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, &curr_det_sizes[3], - DET3_SIZE, &target_det_sizes[3]); - -} - -uint32_t hubbub3_compbuf_config_error(struct hubbub *hubbub) -{ - struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); - uint32_t compbuf_config_error = 0; - - REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, - &compbuf_config_error); - - return compbuf_config_error; + hubbub_reg_state->det0_ctrl = REG_READ(DCHUBBUB_DET0_CTRL); + hubbub_reg_state->det1_ctrl = REG_READ(DCHUBBUB_DET1_CTRL); + hubbub_reg_state->det2_ctrl = REG_READ(DCHUBBUB_DET2_CTRL); + hubbub_reg_state->det3_ctrl = REG_READ(DCHUBBUB_DET3_CTRL); + hubbub_reg_state->compbuf_ctrl = REG_READ(DCHUBBUB_COMPBUF_CTRL); } static const struct hubbub_funcs hubbub30_funcs = { @@ -486,8 +468,7 @@ static const struct hubbub_funcs hubbub30_funcs = { .force_pstate_change_control = hubbub3_force_pstate_change_control, .init_watermarks = hubbub3_init_watermarks, .hubbub_read_state = hubbub2_read_state, - .get_det_sizes = hubbub3_get_det_sizes, - .compbuf_config_error = hubbub3_compbuf_config_error, + .hubbub_read_reg_state = hubbub3_read_reg_state }; void hubbub3_construct(struct dcn20_hubbub *hubbub3, diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h index 49a469969d361..9e14de3ccaeec 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.h @@ -133,10 +133,6 @@ void hubbub3_force_pstate_change_control(struct hubbub *hubbub, void hubbub3_init_watermarks(struct hubbub *hubbub); -void hubbub3_get_det_sizes(struct hubbub *hubbub, - uint32_t *curr_det_sizes, - uint32_t *target_det_sizes); - -uint32_t hubbub3_compbuf_config_error(struct hubbub *hubbub); +void hubbub3_read_reg_state(struct hubbub *hubbub, struct dcn_hubbub_reg_state *hubbub_reg_state); #endif diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c index cdb20251a1549..d1aaa58b7db35 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c @@ -1071,8 +1071,7 @@ static const struct hubbub_funcs hubbub31_funcs = { .program_compbuf_size = dcn31_program_compbuf_size, .init_crb = dcn31_init_crb, .hubbub_read_state = hubbub2_read_state, - .get_det_sizes = hubbub3_get_det_sizes, - .compbuf_config_error = hubbub3_compbuf_config_error, + .hubbub_read_reg_state = hubbub3_read_reg_state }; void hubbub31_construct(struct dcn20_hubbub *hubbub31, diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c index 4d4ca6d77bbda..237331b353786 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c @@ -1037,8 +1037,7 @@ static const struct hubbub_funcs hubbub32_funcs = { .force_usr_retraining_allow = hubbub32_force_usr_retraining_allow, .set_request_limit = hubbub32_set_request_limit, .get_mall_en = hubbub32_get_mall_en, - .get_det_sizes = hubbub3_get_det_sizes, - .compbuf_config_error = hubbub3_compbuf_config_error, + .hubbub_read_reg_state = hubbub3_read_reg_state }; void hubbub32_construct(struct dcn20_hubbub *hubbub2, diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c index a443722a8632c..1b7746a6549ab 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c @@ -589,8 +589,7 @@ static const struct hubbub_funcs hubbub35_funcs = { .hubbub_read_state = hubbub2_read_state, .force_usr_retraining_allow = hubbub32_force_usr_retraining_allow, .dchubbub_init = hubbub35_init, - .get_det_sizes = hubbub3_get_det_sizes, - .compbuf_config_error = hubbub3_compbuf_config_error, + .hubbub_read_reg_state = hubbub3_read_reg_state }; void hubbub35_construct(struct dcn20_hubbub *hubbub2, diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c index a36273a528808..d11afd1ce72a2 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c @@ -1247,8 +1247,7 @@ static const struct hubbub_funcs hubbub4_01_funcs = { .program_compbuf_segments = dcn401_program_compbuf_segments, .wait_for_det_update = dcn401_wait_for_det_update, .program_arbiter = dcn401_program_arbiter, - .get_det_sizes = hubbub3_get_det_sizes, - .compbuf_config_error = hubbub3_compbuf_config_error, + .hubbub_read_reg_state = hubbub3_read_reg_state }; void hubbub401_construct(struct dcn20_hubbub *hubbub2, diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h index cf2eb9793008d..f2571076fc501 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h @@ -105,7 +105,9 @@ SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\ SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\ SRI(HUBP_CLK_CNTL, HUBP, id),\ - SRI(HUBPRET_READ_LINE_VALUE, HUBPRET, id) + SRI(HUBPRET_READ_LINE_VALUE, HUBPRET, id),\ + SRI(HUBP_MEASURE_WIN_CTRL_DCFCLK, HUBP, id),\ + SRI(HUBP_MEASURE_WIN_CTRL_DPPCLK, HUBP, id) /* Register address initialization macro for ASICs with VM */ #define HUBP_REG_LIST_DCN_VM(id)\ @@ -251,7 +253,19 @@ uint32_t CURSOR_HOT_SPOT; \ uint32_t CURSOR_DST_OFFSET; \ uint32_t HUBP_CLK_CNTL; \ - uint32_t HUBPRET_READ_LINE_VALUE + uint32_t HUBPRET_READ_LINE_VALUE; \ + uint32_t HUBP_MEASURE_WIN_CTRL_DCFCLK; \ + uint32_t HUBP_MEASURE_WIN_CTRL_DPPCLK; \ + uint32_t HUBPRET_INTERRUPT; \ + uint32_t HUBPRET_MEM_PWR_CTRL; \ + uint32_t HUBPRET_MEM_PWR_STATUS; \ + uint32_t HUBPRET_READ_LINE_CTRL0; \ + uint32_t HUBPRET_READ_LINE_CTRL1; \ + uint32_t HUBPRET_READ_LINE0; \ + uint32_t HUBPRET_READ_LINE1; \ + uint32_t HUBPREQ_MEM_PWR_CTRL; \ + uint32_t HUBPREQ_MEM_PWR_STATUS + #define HUBP_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -688,6 +702,123 @@ struct dcn_fl_regs_st { uint32_t lut_fl_mode; uint32_t lut_fl_format; }; +struct dcn_hubp_reg_state { + uint32_t hubp_cntl; + uint32_t mall_config; + uint32_t mall_sub_vp; + uint32_t hubp_req_size_config; + uint32_t hubp_req_size_config_c; + uint32_t vmpg_config; + uint32_t addr_config; + uint32_t pri_viewport_dimension; + uint32_t pri_viewport_dimension_c; + uint32_t pri_viewport_start; + uint32_t pri_viewport_start_c; + uint32_t sec_viewport_dimension; + uint32_t sec_viewport_dimension_c; + uint32_t sec_viewport_start; + uint32_t sec_viewport_start_c; + uint32_t surface_config; + uint32_t tiling_config; + uint32_t clk_cntl; + uint32_t mall_status; + uint32_t measure_win_ctrl_dcfclk; + uint32_t measure_win_ctrl_dppclk; + + uint32_t blank_offset_0; + uint32_t blank_offset_1; + uint32_t cursor_settings; + uint32_t dcn_cur0_ttu_cntl0; + uint32_t dcn_cur0_ttu_cntl1; + uint32_t dcn_cur1_ttu_cntl0; + uint32_t dcn_cur1_ttu_cntl1; + uint32_t dcn_dmdat_vm_cntl; + uint32_t dcn_expansion_mode; + uint32_t dcn_global_ttu_cntl; + uint32_t dcn_surf0_ttu_cntl0; + uint32_t dcn_surf0_ttu_cntl1; + uint32_t dcn_surf1_ttu_cntl0; + uint32_t dcn_surf1_ttu_cntl1; + uint32_t dcn_ttu_qos_wm; + uint32_t dcn_vm_mx_l1_tlb_cntl; + uint32_t dcn_vm_system_aperture_high_addr; + uint32_t dcn_vm_system_aperture_low_addr; + uint32_t dcsurf_flip_control; + uint32_t dcsurf_flip_control2; + uint32_t dcsurf_primary_meta_surface_address; + uint32_t dcsurf_primary_meta_surface_address_c; + uint32_t dcsurf_primary_meta_surface_address_high; + uint32_t dcsurf_primary_meta_surface_address_high_c; + uint32_t dcsurf_primary_surface_address; + uint32_t dcsurf_primary_surface_address_c; + uint32_t dcsurf_primary_surface_address_high; + uint32_t dcsurf_primary_surface_address_high_c; + uint32_t dcsurf_secondary_meta_surface_address; + uint32_t dcsurf_secondary_meta_surface_address_c; + uint32_t dcsurf_secondary_meta_surface_address_high; + uint32_t dcsurf_secondary_meta_surface_address_high_c; + uint32_t dcsurf_secondary_surface_address; + uint32_t dcsurf_secondary_surface_address_c; + uint32_t dcsurf_secondary_surface_address_high; + uint32_t dcsurf_secondary_surface_address_high_c; + uint32_t dcsurf_surface_control; + uint32_t dcsurf_surface_earliest_inuse; + uint32_t dcsurf_surface_earliest_inuse_c; + uint32_t dcsurf_surface_earliest_inuse_high; + uint32_t dcsurf_surface_earliest_inuse_high_c; + uint32_t dcsurf_surface_flip_interrupt; + uint32_t dcsurf_surface_inuse; + uint32_t dcsurf_surface_inuse_c; + uint32_t dcsurf_surface_inuse_high; + uint32_t dcsurf_surface_inuse_high_c; + uint32_t dcsurf_surface_pitch; + uint32_t dcsurf_surface_pitch_c; + uint32_t dst_after_scaler; + uint32_t dst_dimensions; + uint32_t dst_y_delta_drq_limit; + uint32_t flip_parameters_0; + uint32_t flip_parameters_1; + uint32_t flip_parameters_2; + uint32_t flip_parameters_3; + uint32_t flip_parameters_4; + uint32_t flip_parameters_5; + uint32_t flip_parameters_6; + uint32_t hubpreq_mem_pwr_ctrl; + uint32_t hubpreq_mem_pwr_status; + uint32_t nom_parameters_0; + uint32_t nom_parameters_1; + uint32_t nom_parameters_2; + uint32_t nom_parameters_3; + uint32_t nom_parameters_4; + uint32_t nom_parameters_5; + uint32_t nom_parameters_6; + uint32_t nom_parameters_7; + uint32_t per_line_delivery; + uint32_t per_line_delivery_pre; + uint32_t prefetch_settings; + uint32_t prefetch_settings_c; + uint32_t ref_freq_to_pix_freq; + uint32_t uclk_pstate_force; + uint32_t vblank_parameters_0; + uint32_t vblank_parameters_1; + uint32_t vblank_parameters_2; + uint32_t vblank_parameters_3; + uint32_t vblank_parameters_4; + uint32_t vblank_parameters_5; + uint32_t vblank_parameters_6; + uint32_t vmid_settings_0; + + uint32_t hubpret_control; + uint32_t hubpret_interrupt; + uint32_t hubpret_mem_pwr_ctrl; + uint32_t hubpret_mem_pwr_status; + uint32_t hubpret_read_line_ctrl0; + uint32_t hubpret_read_line_ctrl1; + uint32_t hubpret_read_line_status; + uint32_t hubpret_read_line_value; + uint32_t hubpret_read_line0; + uint32_t hubpret_read_line1; +}; struct dcn_hubp_state { struct _vcs_dpi_display_dlg_regs_st dlg_attr; @@ -718,7 +849,6 @@ struct dcn_hubp_state { uint32_t hubp_cntl; uint32_t flip_control; }; - struct dcn10_hubp { struct hubp base; struct dcn_hubp_state state; diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h index f325db555102b..7062e6653062a 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h @@ -145,7 +145,8 @@ uint32_t FLIP_PARAMETERS_2;\ uint32_t DCN_CUR1_TTU_CNTL0;\ uint32_t DCN_CUR1_TTU_CNTL1;\ - uint32_t VMID_SETTINGS_0 + uint32_t VMID_SETTINGS_0;\ + uint32_t DST_Y_DELTA_DRQ_LIMIT /*shared with dcn3.x*/ #define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \ @@ -176,7 +177,10 @@ uint32_t HUBP_3DLUT_CONTROL;\ uint32_t HUBP_3DLUT_DLG_PARAM;\ uint32_t DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE;\ - uint32_t DCHUBP_MCACHEID_CONFIG + uint32_t DCHUBP_MCACHEID_CONFIG;\ + uint32_t DCHUBP_MALL_SUB_VP;\ + uint32_t DCHUBP_ADDR_CONFIG;\ + uint32_t HUBP_MALL_STATUS #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \ DCN_HUBP_REG_FIELD_BASE_LIST(type); \ diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c index 556214b2227da..0cc6f45589898 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c @@ -476,6 +476,126 @@ void hubp3_read_state(struct hubp *hubp) } +void hubp3_read_reg_state(struct hubp *hubp, struct dcn_hubp_reg_state *reg_state) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + reg_state->hubp_cntl = REG_READ(DCHUBP_CNTL); + reg_state->mall_config = REG_READ(DCHUBP_MALL_CONFIG); + reg_state->mall_sub_vp = REG_READ(DCHUBP_MALL_SUB_VP); + reg_state->hubp_req_size_config = REG_READ(DCHUBP_REQ_SIZE_CONFIG); + reg_state->hubp_req_size_config_c = REG_READ(DCHUBP_REQ_SIZE_CONFIG_C); + reg_state->vmpg_config = REG_READ(DCHUBP_VMPG_CONFIG); + reg_state->addr_config = REG_READ(DCSURF_ADDR_CONFIG); + reg_state->pri_viewport_dimension = REG_READ(DCSURF_PRI_VIEWPORT_DIMENSION); + reg_state->pri_viewport_dimension_c = REG_READ(DCSURF_PRI_VIEWPORT_DIMENSION_C); + reg_state->pri_viewport_start = REG_READ(DCSURF_PRI_VIEWPORT_START); + reg_state->pri_viewport_start_c = REG_READ(DCSURF_PRI_VIEWPORT_START_C); + reg_state->sec_viewport_dimension = REG_READ(DCSURF_SEC_VIEWPORT_DIMENSION); + reg_state->sec_viewport_dimension_c = REG_READ(DCSURF_SEC_VIEWPORT_DIMENSION_C); + reg_state->sec_viewport_start = REG_READ(DCSURF_SEC_VIEWPORT_START); + reg_state->sec_viewport_start_c = REG_READ(DCSURF_SEC_VIEWPORT_START_C); + reg_state->surface_config = REG_READ(DCSURF_SURFACE_CONFIG); + reg_state->tiling_config = REG_READ(DCSURF_TILING_CONFIG); + reg_state->clk_cntl = REG_READ(HUBP_CLK_CNTL); + reg_state->mall_status = REG_READ(HUBP_MALL_STATUS); + reg_state->measure_win_ctrl_dcfclk = REG_READ(HUBP_MEASURE_WIN_CTRL_DCFCLK); + reg_state->measure_win_ctrl_dppclk = REG_READ(HUBP_MEASURE_WIN_CTRL_DPPCLK); + + reg_state->blank_offset_0 = REG_READ(BLANK_OFFSET_0); + reg_state->blank_offset_1 = REG_READ(BLANK_OFFSET_1); + reg_state->cursor_settings = REG_READ(CURSOR_SETTINGS); + reg_state->dcn_cur0_ttu_cntl0 = REG_READ(DCN_CUR0_TTU_CNTL0); + reg_state->dcn_cur0_ttu_cntl1 = REG_READ(DCN_CUR0_TTU_CNTL1); + reg_state->dcn_cur1_ttu_cntl0 = REG_READ(DCN_CUR1_TTU_CNTL0); + reg_state->dcn_cur1_ttu_cntl1 = REG_READ(DCN_CUR1_TTU_CNTL1); + reg_state->dcn_dmdat_vm_cntl = REG_READ(DCN_DMDATA_VM_CNTL); + reg_state->dcn_expansion_mode = REG_READ(DCN_EXPANSION_MODE); + reg_state->dcn_global_ttu_cntl = REG_READ(DCN_GLOBAL_TTU_CNTL); + reg_state->dcn_surf0_ttu_cntl0 = REG_READ(DCN_SURF0_TTU_CNTL0); + reg_state->dcn_surf0_ttu_cntl1 = REG_READ(DCN_SURF0_TTU_CNTL1); + reg_state->dcn_surf1_ttu_cntl0 = REG_READ(DCN_SURF1_TTU_CNTL0); + reg_state->dcn_surf1_ttu_cntl1 = REG_READ(DCN_SURF1_TTU_CNTL1); + reg_state->dcn_ttu_qos_wm = REG_READ(DCN_TTU_QOS_WM); + reg_state->dcn_vm_mx_l1_tlb_cntl = REG_READ(DCN_VM_MX_L1_TLB_CNTL); + reg_state->dcn_vm_system_aperture_high_addr = REG_READ(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR); + reg_state->dcn_vm_system_aperture_low_addr = REG_READ(DCN_VM_SYSTEM_APERTURE_LOW_ADDR); + reg_state->dcsurf_flip_control = REG_READ(DCSURF_FLIP_CONTROL); + reg_state->dcsurf_flip_control2 = REG_READ(DCSURF_FLIP_CONTROL2); + reg_state->dcsurf_primary_meta_surface_address = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS); + reg_state->dcsurf_primary_meta_surface_address_c = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C); + reg_state->dcsurf_primary_meta_surface_address_high = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH); + reg_state->dcsurf_primary_meta_surface_address_high_c = REG_READ(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C); + reg_state->dcsurf_primary_surface_address = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS); + reg_state->dcsurf_primary_surface_address_c = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS_C); + reg_state->dcsurf_primary_surface_address_high = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH); + reg_state->dcsurf_primary_surface_address_high_c = REG_READ(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C); + reg_state->dcsurf_secondary_meta_surface_address = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS); + reg_state->dcsurf_secondary_meta_surface_address_c = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C); + reg_state->dcsurf_secondary_meta_surface_address_high = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH); + reg_state->dcsurf_secondary_meta_surface_address_high_c = REG_READ(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C); + reg_state->dcsurf_secondary_surface_address = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS); + reg_state->dcsurf_secondary_surface_address_c = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS_C); + reg_state->dcsurf_secondary_surface_address_high = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH); + reg_state->dcsurf_secondary_surface_address_high_c = REG_READ(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C); + reg_state->dcsurf_surface_control = REG_READ(DCSURF_SURFACE_CONTROL); + reg_state->dcsurf_surface_earliest_inuse = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE); + reg_state->dcsurf_surface_earliest_inuse_c = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE_C); + reg_state->dcsurf_surface_earliest_inuse_high = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE_HIGH); + reg_state->dcsurf_surface_earliest_inuse_high_c = REG_READ(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C); + reg_state->dcsurf_surface_flip_interrupt = REG_READ(DCSURF_SURFACE_FLIP_INTERRUPT); + reg_state->dcsurf_surface_inuse = REG_READ(DCSURF_SURFACE_INUSE); + reg_state->dcsurf_surface_inuse_c = REG_READ(DCSURF_SURFACE_INUSE_C); + reg_state->dcsurf_surface_inuse_high = REG_READ(DCSURF_SURFACE_INUSE_HIGH); + reg_state->dcsurf_surface_inuse_high_c = REG_READ(DCSURF_SURFACE_INUSE_HIGH_C); + reg_state->dcsurf_surface_pitch = REG_READ(DCSURF_SURFACE_PITCH); + reg_state->dcsurf_surface_pitch_c = REG_READ(DCSURF_SURFACE_PITCH_C); + reg_state->dst_after_scaler = REG_READ(DST_AFTER_SCALER); + reg_state->dst_dimensions = REG_READ(DST_DIMENSIONS); + reg_state->dst_y_delta_drq_limit = REG_READ(DST_Y_DELTA_DRQ_LIMIT); + reg_state->flip_parameters_0 = REG_READ(FLIP_PARAMETERS_0); + reg_state->flip_parameters_1 = REG_READ(FLIP_PARAMETERS_1); + reg_state->flip_parameters_2 = REG_READ(FLIP_PARAMETERS_2); + reg_state->flip_parameters_3 = REG_READ(FLIP_PARAMETERS_3); + reg_state->flip_parameters_4 = REG_READ(FLIP_PARAMETERS_4); + reg_state->flip_parameters_5 = REG_READ(FLIP_PARAMETERS_5); + reg_state->flip_parameters_6 = REG_READ(FLIP_PARAMETERS_6); + reg_state->hubpreq_mem_pwr_ctrl = REG_READ(HUBPREQ_MEM_PWR_CTRL); + reg_state->hubpreq_mem_pwr_status = REG_READ(HUBPREQ_MEM_PWR_STATUS); + reg_state->nom_parameters_0 = REG_READ(NOM_PARAMETERS_0); + reg_state->nom_parameters_1 = REG_READ(NOM_PARAMETERS_1); + reg_state->nom_parameters_2 = REG_READ(NOM_PARAMETERS_2); + reg_state->nom_parameters_3 = REG_READ(NOM_PARAMETERS_3); + reg_state->nom_parameters_4 = REG_READ(NOM_PARAMETERS_4); + reg_state->nom_parameters_5 = REG_READ(NOM_PARAMETERS_5); + reg_state->nom_parameters_6 = REG_READ(NOM_PARAMETERS_6); + reg_state->nom_parameters_7 = REG_READ(NOM_PARAMETERS_7); + reg_state->per_line_delivery = REG_READ(PER_LINE_DELIVERY); + reg_state->per_line_delivery_pre = REG_READ(PER_LINE_DELIVERY_PRE); + reg_state->prefetch_settings = REG_READ(PREFETCH_SETTINGS); + reg_state->prefetch_settings_c = REG_READ(PREFETCH_SETTINGS_C); + reg_state->ref_freq_to_pix_freq = REG_READ(REF_FREQ_TO_PIX_FREQ); + reg_state->uclk_pstate_force = REG_READ(UCLK_PSTATE_FORCE); + reg_state->vblank_parameters_0 = REG_READ(VBLANK_PARAMETERS_0); + reg_state->vblank_parameters_1 = REG_READ(VBLANK_PARAMETERS_1); + reg_state->vblank_parameters_2 = REG_READ(VBLANK_PARAMETERS_2); + reg_state->vblank_parameters_3 = REG_READ(VBLANK_PARAMETERS_3); + reg_state->vblank_parameters_4 = REG_READ(VBLANK_PARAMETERS_4); + reg_state->vblank_parameters_5 = REG_READ(VBLANK_PARAMETERS_5); + reg_state->vblank_parameters_6 = REG_READ(VBLANK_PARAMETERS_6); + reg_state->vmid_settings_0 = REG_READ(VMID_SETTINGS_0); + reg_state->hubpret_control = REG_READ(HUBPRET_CONTROL); + reg_state->hubpret_interrupt = REG_READ(HUBPRET_INTERRUPT); + reg_state->hubpret_mem_pwr_ctrl = REG_READ(HUBPRET_MEM_PWR_CTRL); + reg_state->hubpret_mem_pwr_status = REG_READ(HUBPRET_MEM_PWR_STATUS); + reg_state->hubpret_read_line_ctrl0 = REG_READ(HUBPRET_READ_LINE_CTRL0); + reg_state->hubpret_read_line_ctrl1 = REG_READ(HUBPRET_READ_LINE_CTRL1); + reg_state->hubpret_read_line_status = REG_READ(HUBPRET_READ_LINE_STATUS); + reg_state->hubpret_read_line_value = REG_READ(HUBPRET_READ_LINE_VALUE); + reg_state->hubpret_read_line0 = REG_READ(HUBPRET_READ_LINE0); + reg_state->hubpret_read_line1 = REG_READ(HUBPRET_READ_LINE1); +} + void hubp3_setup( struct hubp *hubp, struct _vcs_dpi_display_dlg_regs_st *dlg_attr, @@ -505,30 +625,6 @@ void hubp3_init(struct hubp *hubp) hubp_reset(hubp); } -uint32_t hubp3_get_current_read_line(struct hubp *hubp) -{ - uint32_t read_line = 0; - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - REG_GET(HUBPRET_READ_LINE_VALUE, - PIPE_READ_LINE, - &read_line); - - return read_line; -} - -unsigned int hubp3_get_underflow_status(struct hubp *hubp) -{ - uint32_t hubp_underflow = 0; - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - REG_GET(DCHUBP_CNTL, - HUBP_UNDERFLOW_STATUS, - &hubp_underflow); - - return hubp_underflow; -} - static struct hubp_funcs dcn30_hubp_funcs = { .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, @@ -558,8 +654,7 @@ static struct hubp_funcs dcn30_hubp_funcs = { .hubp_soft_reset = hubp1_soft_reset, .hubp_set_flip_int = hubp1_set_flip_int, .hubp_clear_tiling = hubp3_clear_tiling, - .hubp_get_underflow_status = hubp3_get_underflow_status, - .hubp_get_current_read_line = hubp3_get_current_read_line, + .hubp_read_reg_state = hubp3_read_reg_state }; bool hubp3_construct( diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h index 842f4eb72cc82..c767e9f4f9b31 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h @@ -296,6 +296,8 @@ void hubp3_dmdata_set_attributes( void hubp3_read_state(struct hubp *hubp); +void hubp3_read_reg_state(struct hubp *hubp, struct dcn_hubp_reg_state *reg_state); + void hubp3_init(struct hubp *hubp); void hubp3_clear_tiling(struct hubp *hubp); diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c index 47101847c2b7b..189045f850399 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn31/dcn31_hubp.c @@ -110,9 +110,7 @@ static struct hubp_funcs dcn31_hubp_funcs = { .hubp_in_blank = hubp1_in_blank, .program_extended_blank = hubp31_program_extended_blank, .hubp_clear_tiling = hubp3_clear_tiling, - .hubp_get_underflow_status = hubp3_get_underflow_status, - .hubp_get_current_read_line = hubp3_get_current_read_line, - .hubp_get_det_config_error = hubp31_get_det_config_error, + .hubp_read_reg_state = hubp3_read_reg_state, }; bool hubp31_construct( diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c index 41c8f78efdc34..a781085b046b5 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c @@ -222,9 +222,7 @@ static struct hubp_funcs dcn32_hubp_funcs = { .hubp_update_mall_sel = hubp32_update_mall_sel, .hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering, .hubp_clear_tiling = hubp3_clear_tiling, - .hubp_get_underflow_status = hubp3_get_underflow_status, - .hubp_get_current_read_line = hubp3_get_current_read_line, - .hubp_get_det_config_error = hubp31_get_det_config_error, + .hubp_read_reg_state = hubp3_read_reg_state }; bool hubp32_construct( diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c index b140808f21aff..79c583e258c78 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c @@ -209,6 +209,7 @@ static struct hubp_funcs dcn35_hubp_funcs = { .dmdata_load = hubp2_dmdata_load, .dmdata_status_done = hubp2_dmdata_status_done, .hubp_read_state = hubp3_read_state, + .hubp_read_reg_state = hubp3_read_reg_state, .hubp_clear_underflow = hubp2_clear_underflow, .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, .hubp_init = hubp35_init, @@ -218,9 +219,6 @@ static struct hubp_funcs dcn35_hubp_funcs = { .hubp_in_blank = hubp1_in_blank, .program_extended_blank = hubp31_program_extended_blank_value, .hubp_clear_tiling = hubp3_clear_tiling, - .hubp_get_underflow_status = hubp3_get_underflow_status, - .hubp_get_current_read_line = hubp3_get_current_read_line, - .hubp_get_det_config_error = hubp31_get_det_config_error, }; bool hubp35_construct( diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c index 0fcbc6a35be67..3a2e0848173e9 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c @@ -1071,9 +1071,7 @@ static struct hubp_funcs dcn401_hubp_funcs = { .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done, .hubp_clear_tiling = hubp401_clear_tiling, .hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config, - .hubp_get_underflow_status = hubp3_get_underflow_status, - .hubp_get_current_read_line = hubp3_get_current_read_line, - .hubp_get_det_config_error = hubp31_get_det_config_error, + .hubp_read_reg_state = hubp3_read_reg_state }; bool hubp401_construct( diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index e47ed5571dfdd..81bcadf5e57ed 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -53,7 +53,8 @@ #include "link_service.h" #include "dc_state_priv.h" - +#define TO_DCN_DCCG(dccg)\ + container_of(dccg, struct dcn_dccg, base) #define DC_LOGGER_INIT(logger) @@ -1235,44 +1236,47 @@ void dcn30_get_underflow_debug_data(const struct dc *dc, { struct hubbub *hubbub = dc->res_pool->hubbub; - if (tg) { - uint32_t v_blank_start = 0, v_blank_end = 0; - - out_data->otg_inst = tg->inst; - - tg->funcs->get_scanoutpos(tg, - &v_blank_start, - &v_blank_end, - &out_data->h_position, - &out_data->v_position); - - out_data->otg_frame_count = tg->funcs->get_frame_count(tg); - - out_data->otg_underflow = tg->funcs->is_optc_underflow_occurred(tg); + if (hubbub) { + if (hubbub->funcs->hubbub_read_reg_state) { + hubbub->funcs->hubbub_read_reg_state(hubbub, out_data->hubbub_reg_state); + } } for (int i = 0; i < MAX_PIPES; i++) { struct hubp *hubp = dc->res_pool->hubps[i]; - - if (hubp) { - if (hubp->funcs->hubp_get_underflow_status) - out_data->hubps[i].hubp_underflow = hubp->funcs->hubp_get_underflow_status(hubp); - - if (hubp->funcs->hubp_in_blank) - out_data->hubps[i].hubp_in_blank = hubp->funcs->hubp_in_blank(hubp); - - if (hubp->funcs->hubp_get_current_read_line) - out_data->hubps[i].hubp_readline = hubp->funcs->hubp_get_current_read_line(hubp); - - if (hubp->funcs->hubp_get_det_config_error) - out_data->hubps[i].det_config_error = hubp->funcs->hubp_get_det_config_error(hubp); - } + struct dpp *dpp = dc->res_pool->dpps[i]; + struct output_pixel_processor *opp = dc->res_pool->opps[i]; + struct display_stream_compressor *dsc = dc->res_pool->dscs[i]; + struct mpc *mpc = dc->res_pool->mpc; + struct timing_generator *optc = dc->res_pool->timing_generators[i]; + struct dccg *dccg = dc->res_pool->dccg; + + if (hubp) + if (hubp->funcs->hubp_read_reg_state) + hubp->funcs->hubp_read_reg_state(hubp, out_data->hubp_reg_state[i]); + + if (dpp) + if (dpp->funcs->dpp_read_reg_state) + dpp->funcs->dpp_read_reg_state(dpp, out_data->dpp_reg_state[i]); + + if (opp) + if (opp->funcs->opp_read_reg_state) + opp->funcs->opp_read_reg_state(opp, out_data->opp_reg_state[i]); + + if (dsc) + if (dsc->funcs->dsc_read_reg_state) + dsc->funcs->dsc_read_reg_state(dsc, out_data->dsc_reg_state[i]); + + if (mpc) + if (mpc->funcs->mpc_read_reg_state) + mpc->funcs->mpc_read_reg_state(mpc, i, out_data->mpc_reg_state[i]); + + if (optc) + if (optc->funcs->optc_read_reg_state) + optc->funcs->optc_read_reg_state(optc, out_data->optc_reg_state[i]); + + if (dccg) + if (dccg->funcs->dccg_read_reg_state) + dccg->funcs->dccg_read_reg_state(dccg, out_data->dccg_reg_state[i]); } - - if (hubbub->funcs->get_det_sizes) - hubbub->funcs->get_det_sizes(hubbub, out_data->curr_det_sizes, out_data->target_det_sizes); - - if (hubbub->funcs->compbuf_config_error) - out_data->compbuf_config_error = hubbub->funcs->compbuf_config_error(hubbub); - } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index 61c4d2a7db1ce..500a601e99b50 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -71,6 +71,125 @@ enum pixel_rate_div { PIXEL_RATE_DIV_NA = 0xF }; +struct dcn_dccg_reg_state { + uint32_t dc_mem_global_pwr_req_cntl; + uint32_t dccg_audio_dtbclk_dto_modulo; + uint32_t dccg_audio_dtbclk_dto_phase; + uint32_t dccg_audio_dto_source; + uint32_t dccg_audio_dto0_module; + uint32_t dccg_audio_dto0_phase; + uint32_t dccg_audio_dto1_module; + uint32_t dccg_audio_dto1_phase; + uint32_t dccg_cac_status; + uint32_t dccg_cac_status2; + uint32_t dccg_disp_cntl_reg; + uint32_t dccg_ds_cntl; + uint32_t dccg_ds_dto_incr; + uint32_t dccg_ds_dto_modulo; + uint32_t dccg_ds_hw_cal_interval; + uint32_t dccg_gate_disable_cntl; + uint32_t dccg_gate_disable_cntl2; + uint32_t dccg_gate_disable_cntl3; + uint32_t dccg_gate_disable_cntl4; + uint32_t dccg_gate_disable_cntl5; + uint32_t dccg_gate_disable_cntl6; + uint32_t dccg_global_fgcg_rep_cntl; + uint32_t dccg_gtc_cntl; + uint32_t dccg_gtc_current; + uint32_t dccg_gtc_dto_incr; + uint32_t dccg_gtc_dto_modulo; + uint32_t dccg_perfmon_cntl; + uint32_t dccg_perfmon_cntl2; + uint32_t dccg_soft_reset; + uint32_t dccg_test_clk_sel; + uint32_t dccg_vsync_cnt_ctrl; + uint32_t dccg_vsync_cnt_int_ctrl; + uint32_t dccg_vsync_otg0_latch_value; + uint32_t dccg_vsync_otg1_latch_value; + uint32_t dccg_vsync_otg2_latch_value; + uint32_t dccg_vsync_otg3_latch_value; + uint32_t dccg_vsync_otg4_latch_value; + uint32_t dccg_vsync_otg5_latch_value; + uint32_t dispclk_cgtt_blk_ctrl_reg; + uint32_t dispclk_freq_change_cntl; + uint32_t dp_dto_dbuf_en; + uint32_t dp_dto0_modulo; + uint32_t dp_dto0_phase; + uint32_t dp_dto1_modulo; + uint32_t dp_dto1_phase; + uint32_t dp_dto2_modulo; + uint32_t dp_dto2_phase; + uint32_t dp_dto3_modulo; + uint32_t dp_dto3_phase; + uint32_t dpiaclk_540m_dto_modulo; + uint32_t dpiaclk_540m_dto_phase; + uint32_t dpiaclk_810m_dto_modulo; + uint32_t dpiaclk_810m_dto_phase; + uint32_t dpiaclk_dto_cntl; + uint32_t dpiasymclk_cntl; + uint32_t dppclk_cgtt_blk_ctrl_reg; + uint32_t dppclk_ctrl; + uint32_t dppclk_dto_ctrl; + uint32_t dppclk0_dto_param; + uint32_t dppclk1_dto_param; + uint32_t dppclk2_dto_param; + uint32_t dppclk3_dto_param; + uint32_t dprefclk_cgtt_blk_ctrl_reg; + uint32_t dprefclk_cntl; + uint32_t dpstreamclk_cntl; + uint32_t dscclk_dto_ctrl; + uint32_t dscclk0_dto_param; + uint32_t dscclk1_dto_param; + uint32_t dscclk2_dto_param; + uint32_t dscclk3_dto_param; + uint32_t dtbclk_dto_dbuf_en; + uint32_t dtbclk_dto0_modulo; + uint32_t dtbclk_dto0_phase; + uint32_t dtbclk_dto1_modulo; + uint32_t dtbclk_dto1_phase; + uint32_t dtbclk_dto2_modulo; + uint32_t dtbclk_dto2_phase; + uint32_t dtbclk_dto3_modulo; + uint32_t dtbclk_dto3_phase; + uint32_t dtbclk_p_cntl; + uint32_t force_symclk_disable; + uint32_t hdmicharclk0_clock_cntl; + uint32_t hdmistreamclk_cntl; + uint32_t hdmistreamclk0_dto_param; + uint32_t microsecond_time_base_div; + uint32_t millisecond_time_base_div; + uint32_t otg_pixel_rate_div; + uint32_t otg0_phypll_pixel_rate_cntl; + uint32_t otg0_pixel_rate_cntl; + uint32_t otg1_phypll_pixel_rate_cntl; + uint32_t otg1_pixel_rate_cntl; + uint32_t otg2_phypll_pixel_rate_cntl; + uint32_t otg2_pixel_rate_cntl; + uint32_t otg3_phypll_pixel_rate_cntl; + uint32_t otg3_pixel_rate_cntl; + uint32_t phyasymclk_clock_cntl; + uint32_t phybsymclk_clock_cntl; + uint32_t phycsymclk_clock_cntl; + uint32_t phydsymclk_clock_cntl; + uint32_t phyesymclk_clock_cntl; + uint32_t phyplla_pixclk_resync_cntl; + uint32_t phypllb_pixclk_resync_cntl; + uint32_t phypllc_pixclk_resync_cntl; + uint32_t phyplld_pixclk_resync_cntl; + uint32_t phyplle_pixclk_resync_cntl; + uint32_t refclk_cgtt_blk_ctrl_reg; + uint32_t socclk_cgtt_blk_ctrl_reg; + uint32_t symclk_cgtt_blk_ctrl_reg; + uint32_t symclk_psp_cntl; + uint32_t symclk32_le_cntl; + uint32_t symclk32_se_cntl; + uint32_t symclka_clock_enable; + uint32_t symclkb_clock_enable; + uint32_t symclkc_clock_enable; + uint32_t symclkd_clock_enable; + uint32_t symclke_clock_enable; +}; + struct dccg { struct dc_context *ctx; const struct dccg_funcs *funcs; @@ -81,7 +200,6 @@ struct dccg { //int audio_dtbclk_khz;/* TODO needs to be removed */ //int ref_dtbclk_khz;/* TODO needs to be removed */ }; - struct dtbclk_dto_params { const struct dc_crtc_timing *timing; int otg_inst; @@ -214,6 +332,7 @@ struct dccg_funcs { void (*set_dto_dscclk)(struct dccg *dccg, uint32_t dsc_inst, uint32_t num_slices_h); void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst); void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating); + void (*dccg_read_reg_state)(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state); }; #endif //__DAL_DCCG_H__ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h index 2ce47c403840e..dafc8490efb5d 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h @@ -137,6 +137,14 @@ struct dcn_hubbub_state { uint32_t dram_state_cntl; }; +struct dcn_hubbub_reg_state { + uint32_t det0_ctrl; + uint32_t det1_ctrl; + uint32_t det2_ctrl; + uint32_t det3_ctrl; + uint32_t compbuf_ctrl; +}; + struct hubbub_system_latencies { uint32_t max_latency_ns; uint32_t avg_latency_ns; @@ -216,6 +224,8 @@ struct hubbub_funcs { void (*init_watermarks)(struct hubbub *hubbub); + void (*hubbub_read_reg_state)(struct hubbub *hubbub, struct dcn_hubbub_reg_state *hubbub_reg_state); + /** * @program_det_size: * @@ -242,8 +252,6 @@ struct hubbub_funcs { void (*program_compbuf_segments)(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase); void (*wait_for_det_update)(struct hubbub *hubbub, int hubp_inst); bool (*program_arbiter)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower); - void (*get_det_sizes)(struct hubbub *hubbub, uint32_t *curr_det_sizes, uint32_t *target_det_sizes); - uint32_t (*compbuf_config_error)(struct hubbub *hubbub); struct hubbub_perfmon_funcs { void (*reset)(struct hubbub *hubbub); void (*start_measuring_max_memory_latency_ns)( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h index 09c224691618a..d88b57d4f5125 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h @@ -65,7 +65,6 @@ union defer_reg_writes { } bits; uint32_t raw; }; - struct dpp { const struct dpp_funcs *funcs; struct dc_context *ctx; @@ -203,6 +202,19 @@ struct dcn_dpp_state { uint32_t gamcor_mode; }; +struct dcn_dpp_reg_state { + uint32_t recout_start; + uint32_t recout_size; + uint32_t scl_horz_filter_scale_ratio; + uint32_t scl_vert_filter_scale_ratio; + uint32_t scl_mode; + uint32_t cm_control; + uint32_t dpp_control; + uint32_t dscl_control; + uint32_t obuf_control; + uint32_t mpc_size; +}; + struct CM_bias_params { uint32_t cm_bias_cr_r; uint32_t cm_bias_y_g; @@ -226,6 +238,8 @@ struct dpp_funcs { void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s); + void (*dpp_read_reg_state)(struct dpp *dpp, struct dcn_dpp_reg_state *dpp_reg_state); + void (*dpp_reset)(struct dpp *dpp); void (*dpp_set_scaler)(struct dpp *dpp, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index b0c13b506c11a..90bf86e83fb13 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -238,6 +238,7 @@ struct hubp_funcs { void (*hubp_clk_cntl)(struct hubp *hubp, bool enable); void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst); void (*hubp_read_state)(struct hubp *hubp); + void (*hubp_read_reg_state)(struct hubp *hubp, struct dcn_hubp_reg_state *reg_state); void (*hubp_clear_underflow)(struct hubp *hubp); void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp); unsigned int (*hubp_get_underflow_status)(struct hubp *hubp); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index 22960ee03dee4..a8d1abe20f62c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -350,6 +350,15 @@ struct mpcc_state { struct mpc_rmcm_regs rmcm_regs; }; +struct dcn_mpc_reg_state { + uint32_t mpcc_bot_sel; + uint32_t mpcc_control; + uint32_t mpcc_status; + uint32_t mpcc_top_sel; + uint32_t mpcc_opp_id; + uint32_t mpcc_ogam_control; +}; + /** * struct mpc_funcs - funcs */ @@ -373,6 +382,24 @@ struct mpc_funcs { struct mpc *mpc, int mpcc_inst, struct mpcc_state *s); + /** + * @mpc_read_reg_state: + * + * Read MPC register state for debugging underflow purposes. + * + * Parameters: + * + * - [in] mpc - MPC context + * - [out] reg_state - MPC register state structure + * + * Return: + * + * void + */ + void (*mpc_read_reg_state)( + struct mpc *mpc, + int mpcc_inst, + struct dcn_mpc_reg_state *mpc_reg_state); /** * @insert_plane: diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index 747679cb49449..e1428a83ecbc3 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -297,6 +297,16 @@ struct oppbuf_params { uint32_t num_segment_padded_pixels; }; +struct dcn_opp_reg_state { + uint32_t dpg_control; + uint32_t fmt_control; + uint32_t oppbuf_control; + uint32_t opp_pipe_control; + uint32_t opp_pipe_crc_control; + uint32_t opp_abm_control; + uint32_t dscrm_dsc_forward_config; +}; + struct opp_funcs { @@ -368,6 +378,9 @@ struct opp_funcs { struct output_pixel_processor *opp, enum dc_pixel_encoding pixel_encoding, bool is_primary); + + void (*opp_read_reg_state)( + struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index f2de2cf23859e..da7bf59c4b9d1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -175,6 +175,135 @@ struct dcn_otg_state { uint32_t otg_double_buffer_control; }; +struct dcn_optc_reg_state { + uint32_t optc_bytes_per_pixel; + uint32_t optc_data_format_control; + uint32_t optc_data_source_select; + uint32_t optc_input_clock_control; + uint32_t optc_input_global_control; + uint32_t optc_input_spare_register; + uint32_t optc_memory_config; + uint32_t optc_rsmu_underflow; + uint32_t optc_underflow_threshold; + uint32_t optc_width_control; + + uint32_t otg_3d_structure_control; + uint32_t otg_clock_control; + uint32_t otg_control; + uint32_t otg_count_control; + uint32_t otg_count_reset; + uint32_t otg_crc_cntl; + uint32_t otg_crc_sig_blue_control_mask; + uint32_t otg_crc_sig_red_green_mask; + uint32_t otg_crc0_data_b; + uint32_t otg_crc0_data_rg; + uint32_t otg_crc0_windowa_x_control; + uint32_t otg_crc0_windowa_x_control_readback; + uint32_t otg_crc0_windowa_y_control; + uint32_t otg_crc0_windowa_y_control_readback; + uint32_t otg_crc0_windowb_x_control; + uint32_t otg_crc0_windowb_x_control_readback; + uint32_t otg_crc0_windowb_y_control; + uint32_t otg_crc0_windowb_y_control_readback; + uint32_t otg_crc1_data_b; + uint32_t otg_crc1_data_rg; + uint32_t otg_crc1_windowa_x_control; + uint32_t otg_crc1_windowa_x_control_readback; + uint32_t otg_crc1_windowa_y_control; + uint32_t otg_crc1_windowa_y_control_readback; + uint32_t otg_crc1_windowb_x_control; + uint32_t otg_crc1_windowb_x_control_readback; + uint32_t otg_crc1_windowb_y_control; + uint32_t otg_crc1_windowb_y_control_readback; + uint32_t otg_crc2_data_b; + uint32_t otg_crc2_data_rg; + uint32_t otg_crc3_data_b; + uint32_t otg_crc3_data_rg; + uint32_t otg_dlpc_control; + uint32_t otg_double_buffer_control; + uint32_t otg_drr_control2; + uint32_t otg_drr_control; + uint32_t otg_drr_timing_int_status; + uint32_t otg_drr_trigger_window; + uint32_t otg_drr_v_total_change; + uint32_t otg_drr_v_total_reach_range; + uint32_t otg_dsc_start_position; + uint32_t otg_force_count_now_cntl; + uint32_t otg_global_control0; + uint32_t otg_global_control1; + uint32_t otg_global_control2; + uint32_t otg_global_control3; + uint32_t otg_global_control4; + uint32_t otg_global_sync_status; + uint32_t otg_gsl_control; + uint32_t otg_gsl_vsync_gap; + uint32_t otg_gsl_window_x; + uint32_t otg_gsl_window_y; + uint32_t otg_h_blank_start_end; + uint32_t otg_h_sync_a; + uint32_t otg_h_sync_a_cntl; + uint32_t otg_h_timing_cntl; + uint32_t otg_h_total; + uint32_t otg_interlace_control; + uint32_t otg_interlace_status; + uint32_t otg_interrupt_control; + uint32_t otg_long_vblank_status; + uint32_t otg_m_const_dto0; + uint32_t otg_m_const_dto1; + uint32_t otg_manual_force_vsync_next_line; + uint32_t otg_master_en; + uint32_t otg_master_update_lock; + uint32_t otg_master_update_mode; + uint32_t otg_nom_vert_position; + uint32_t otg_pipe_update_status; + uint32_t otg_pixel_data_readback0; + uint32_t otg_pixel_data_readback1; + uint32_t otg_request_control; + uint32_t otg_snapshot_control; + uint32_t otg_snapshot_frame; + uint32_t otg_snapshot_position; + uint32_t otg_snapshot_status; + uint32_t otg_spare_register; + uint32_t otg_static_screen_control; + uint32_t otg_status; + uint32_t otg_status_frame_count; + uint32_t otg_status_hv_count; + uint32_t otg_status_position; + uint32_t otg_status_vf_count; + uint32_t otg_stereo_control; + uint32_t otg_stereo_force_next_eye; + uint32_t otg_stereo_status; + uint32_t otg_trig_manual_control; + uint32_t otg_triga_cntl; + uint32_t otg_triga_manual_trig; + uint32_t otg_trigb_cntl; + uint32_t otg_trigb_manual_trig; + uint32_t otg_update_lock; + uint32_t otg_v_blank_start_end; + uint32_t otg_v_count_stop_control; + uint32_t otg_v_count_stop_control2; + uint32_t otg_v_sync_a; + uint32_t otg_v_sync_a_cntl; + uint32_t otg_v_total; + uint32_t otg_v_total_control; + uint32_t otg_v_total_int_status; + uint32_t otg_v_total_max; + uint32_t otg_v_total_mid; + uint32_t otg_v_total_min; + uint32_t otg_vert_sync_control; + uint32_t otg_vertical_interrupt0_control; + uint32_t otg_vertical_interrupt0_position; + uint32_t otg_vertical_interrupt1_control; + uint32_t otg_vertical_interrupt1_position; + uint32_t otg_vertical_interrupt2_control; + uint32_t otg_vertical_interrupt2_position; + uint32_t otg_vready_param; + uint32_t otg_vstartup_param; + uint32_t otg_vsync_nom_int_status; + uint32_t otg_vupdate_keepout; + uint32_t otg_vupdate_param; +}; + /** * struct timing_generator - Entry point to Output Timing Generator feature. */ @@ -381,6 +510,7 @@ struct timing_generator_funcs { void (*set_vupdate_keepout)(struct timing_generator *tg, bool enable); bool (*wait_update_lock_status)(struct timing_generator *tg, bool locked); void (*read_otg_state)(struct timing_generator *tg, struct dcn_otg_state *s); + void (*optc_read_reg_state)(struct timing_generator *tg, struct dcn_optc_reg_state *optc_reg_state); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c index 85298b8a1b5ef..6bfd2c1294e5b 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c @@ -1514,6 +1514,21 @@ static void mpc3_read_mpcc_state( MPCC_OGAM_SELECT_CURRENT, &s->rgam_lut); } +void mpc3_read_reg_state( + struct mpc *mpc, + int mpcc_inst, struct dcn_mpc_reg_state *mpc_reg_state) +{ + struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); + + mpc_reg_state->mpcc_bot_sel = REG_READ(MPCC_BOT_SEL[mpcc_inst]); + mpc_reg_state->mpcc_control = REG_READ(MPCC_CONTROL[mpcc_inst]); + mpc_reg_state->mpcc_ogam_control = REG_READ(MPCC_OGAM_CONTROL[mpcc_inst]); + mpc_reg_state->mpcc_opp_id = REG_READ(MPCC_OPP_ID[mpcc_inst]); + mpc_reg_state->mpcc_status = REG_READ(MPCC_STATUS[mpcc_inst]); + mpc_reg_state->mpcc_top_sel = REG_READ(MPCC_TOP_SEL[mpcc_inst]); + +} + static const struct mpc_funcs dcn30_mpc_funcs = { .read_mpcc_state = mpc3_read_mpcc_state, .insert_plane = mpc1_insert_plane, @@ -1544,6 +1559,7 @@ static const struct mpc_funcs dcn30_mpc_funcs = { .release_rmu = mpcc3_release_rmu, .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut, .get_mpc_out_mux = mpc1_get_mpc_out_mux, + .mpc_read_reg_state = mpc3_read_reg_state, .set_bg_color = mpc1_set_bg_color, .set_mpc_mem_lp_mode = mpc3_set_mpc_mem_lp_mode, }; diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h index 103f29900a2c7..e2f147d17178b 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.h @@ -1096,6 +1096,11 @@ void mpc3_power_on_ogam_lut( struct mpc *mpc, int mpcc_id, bool power_on); +void mpc3_read_reg_state( + struct mpc *mpc, + int mpcc_inst, + struct dcn_mpc_reg_state *mpc_reg_state); + void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst); enum dc_lut_mode mpc3_get_ogam_current( diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c index 6f0e017a8ae29..83bbbf34bcac7 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c @@ -1020,6 +1020,7 @@ static const struct mpc_funcs dcn32_mpc_funcs = { .release_rmu = NULL, .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut, .get_mpc_out_mux = mpc1_get_mpc_out_mux, + .mpc_read_reg_state = mpc3_read_reg_state, .set_bg_color = mpc1_set_bg_color, }; diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c index e1a0308dee57a..eeac13fdd6f55 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c @@ -598,6 +598,7 @@ static const struct mpc_funcs dcn401_mpc_funcs = { .release_rmu = NULL, .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut, .get_mpc_out_mux = mpc1_get_mpc_out_mux, + .mpc_read_reg_state = mpc3_read_reg_state, .set_bg_color = mpc1_set_bg_color, .set_movable_cm_location = mpc401_set_movable_cm_location, .update_3dlut_fast_load_select = mpc401_update_3dlut_fast_load_select, diff --git a/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c index 71e9288d60ed7..45d418636d0c1 100644 --- a/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.c @@ -372,6 +372,17 @@ void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable) REG_UPDATE(OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, regval); } + +void opp1_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state) +{ + struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); + + opp_reg_state->fmt_control = REG_READ(FMT_CONTROL); + opp_reg_state->opp_pipe_control = REG_READ(OPP_PIPE_CONTROL); + opp_reg_state->opp_pipe_crc_control = REG_READ(OPP_PIPE_CRC_CONTROL); + opp_reg_state->oppbuf_control = REG_READ(OPPBUF_CONTROL); +} + /*****************************************/ /* Constructor, Destructor */ /*****************************************/ @@ -392,7 +403,8 @@ static const struct opp_funcs dcn10_opp_funcs = { .opp_program_dpg_dimensions = NULL, .dpg_is_blanked = NULL, .dpg_is_pending = NULL, - .opp_destroy = opp1_destroy + .opp_destroy = opp1_destroy, + .opp_read_reg_state = opp1_read_reg_state }; void dcn10_opp_construct(struct dcn10_opp *oppn10, diff --git a/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h index c87de68a509e4..38d0d530a9b7d 100644 --- a/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h +++ b/drivers/gpu/drm/amd/display/dc/opp/dcn10/dcn10_opp.h @@ -63,7 +63,8 @@ uint32_t OPPBUF_CONTROL1; \ uint32_t OPPBUF_3D_PARAMETERS_0; \ uint32_t OPPBUF_3D_PARAMETERS_1; \ - uint32_t OPP_PIPE_CONTROL + uint32_t OPP_PIPE_CONTROL; \ + uint32_t OPP_PIPE_CRC_CONTROL #define OPP_MASK_SH_LIST_DCN(mask_sh) \ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \ @@ -153,7 +154,6 @@ struct dcn10_opp { const struct dcn10_opp_registers *regs; const struct dcn10_opp_shift *opp_shift; const struct dcn10_opp_mask *opp_mask; - bool is_write_to_ram_a_safe; }; @@ -188,4 +188,6 @@ void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable); void opp1_destroy(struct output_pixel_processor **opp); +void opp1_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c index f5fe0cac7cb06..ce826a5be4c71 100644 --- a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c +++ b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c @@ -377,6 +377,18 @@ uint32_t opp2_get_left_edge_extra_pixel_count(struct output_pixel_processor *opp return 0; } +void opp2_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state) +{ + struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp); + + opp_reg_state->dpg_control = REG_READ(DPG_CONTROL); + opp_reg_state->fmt_control = REG_READ(FMT_CONTROL); + opp_reg_state->opp_pipe_control = REG_READ(OPP_PIPE_CONTROL); + opp_reg_state->opp_pipe_crc_control = REG_READ(OPP_PIPE_CRC_CONTROL); + opp_reg_state->oppbuf_control = REG_READ(OPPBUF_CONTROL); + opp_reg_state->dscrm_dsc_forward_config = REG_READ(DSCRM_DSC_FORWARD_CONFIG); +} + /*****************************************/ /* Constructor, Destructor */ /*****************************************/ @@ -395,6 +407,7 @@ static struct opp_funcs dcn20_opp_funcs = { .opp_destroy = opp1_destroy, .opp_program_left_edge_extra_pixel = opp2_program_left_edge_extra_pixel, .opp_get_left_edge_extra_pixel_count = opp2_get_left_edge_extra_pixel_count, + .opp_read_reg_state = opp2_read_reg_state }; void dcn20_opp_construct(struct dcn20_opp *oppn20, diff --git a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h index 34936e6c49f3f..fb0c047c1788e 100644 --- a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h +++ b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h @@ -59,7 +59,8 @@ uint32_t DPG_COLOUR_G_Y; \ uint32_t DPG_COLOUR_R_CR; \ uint32_t DPG_RAMP_CONTROL; \ - uint32_t DPG_STATUS + uint32_t DPG_STATUS; \ + uint32_t DSCRM_DSC_FORWARD_CONFIG #define OPP_DPG_MASK_SH_LIST(mask_sh) \ OPP_SF(DPG0_DPG_CONTROL, DPG_EN, mask_sh), \ @@ -171,4 +172,7 @@ void opp2_program_left_edge_extra_pixel ( uint32_t opp2_get_left_edge_extra_pixel_count(struct output_pixel_processor *opp, enum dc_pixel_encoding pixel_encoding, bool is_primary); + +void opp2_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c b/drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c index 3542b51c9aacf..e11c4e16402f5 100644 --- a/drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c +++ b/drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.c @@ -51,3 +51,16 @@ void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable) { REG_UPDATE(OPP_TOP_CLK_CONTROL, OPP_FGCG_REP_DIS, !enable); } + +void dcn35_opp_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state) +{ + struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp); + + opp_reg_state->dpg_control = REG_READ(DPG_CONTROL); + opp_reg_state->fmt_control = REG_READ(FMT_CONTROL); + opp_reg_state->opp_abm_control = REG_READ(OPP_ABM_CONTROL); + opp_reg_state->opp_pipe_control = REG_READ(OPP_PIPE_CONTROL); + opp_reg_state->opp_pipe_crc_control = REG_READ(OPP_PIPE_CRC_CONTROL); + opp_reg_state->oppbuf_control = REG_READ(OPPBUF_CONTROL); + opp_reg_state->dscrm_dsc_forward_config = REG_READ(DSCRM_DSC_FORWARD_CONFIG); +} diff --git a/drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.h b/drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.h index a9a4135278012..c6cace90e8f22 100644 --- a/drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.h +++ b/drivers/gpu/drm/amd/display/dc/opp/dcn35/dcn35_opp.h @@ -31,7 +31,8 @@ #define OPP_REG_VARIABLE_LIST_DCN3_5 \ OPP_REG_VARIABLE_LIST_DCN2_0; \ - uint32_t OPP_TOP_CLK_CONTROL + uint32_t OPP_TOP_CLK_CONTROL; \ + uint32_t OPP_ABM_CONTROL #define OPP_MASK_SH_LIST_DCN35(mask_sh) \ OPP_MASK_SH_LIST_DCN20(mask_sh), \ @@ -64,4 +65,5 @@ void dcn35_opp_construct(struct dcn20_opp *oppn20, void dcn35_opp_set_fgcg(struct dcn20_opp *oppn20, bool enable); +void dcn35_opp_read_reg_state(struct output_pixel_processor *opp, struct dcn_opp_reg_state *opp_reg_state); #endif diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h index 8b2a8455eb56a..803bcc25601c0 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h @@ -209,7 +209,43 @@ uint32_t OPTC_WIDTH_CONTROL2; \ uint32_t OTG_PSTATE_REGISTER; \ uint32_t OTG_PIPE_UPDATE_STATUS; \ - uint32_t INTERRUPT_DEST + uint32_t INTERRUPT_DEST; \ + uint32_t OPTC_INPUT_SPARE_REGISTER; \ + uint32_t OPTC_RSMU_UNDERFLOW; \ + uint32_t OPTC_UNDERFLOW_THRESHOLD; \ + uint32_t OTG_COUNT_CONTROL; \ + uint32_t OTG_COUNT_RESET; \ + uint32_t OTG_CRC_SIG_BLUE_CONTROL_MASK; \ + uint32_t OTG_CRC_SIG_RED_GREEN_MASK; \ + uint32_t OTG_DLPC_CONTROL; \ + uint32_t OTG_DRR_CONTROL2; \ + uint32_t OTG_DRR_TIMING_INT_STATUS; \ + uint32_t OTG_GLOBAL_CONTROL3; \ + uint32_t OTG_GLOBAL_SYNC_STATUS; \ + uint32_t OTG_GSL_VSYNC_GAP; \ + uint32_t OTG_INTERLACE_STATUS; \ + uint32_t OTG_INTERRUPT_CONTROL; \ + uint32_t OTG_LONG_VBLANK_STATUS; \ + uint32_t OTG_MANUAL_FORCE_VSYNC_NEXT_LINE; \ + uint32_t OTG_MASTER_EN; \ + uint32_t OTG_PIXEL_DATA_READBACK0; \ + uint32_t OTG_PIXEL_DATA_READBACK1; \ + uint32_t OTG_REQUEST_CONTROL; \ + uint32_t OTG_SNAPSHOT_CONTROL; \ + uint32_t OTG_SNAPSHOT_FRAME; \ + uint32_t OTG_SNAPSHOT_POSITION; \ + uint32_t OTG_SNAPSHOT_STATUS; \ + uint32_t OTG_SPARE_REGISTER; \ + uint32_t OTG_STATUS_HV_COUNT; \ + uint32_t OTG_STATUS_VF_COUNT; \ + uint32_t OTG_STEREO_FORCE_NEXT_EYE; \ + uint32_t OTG_TRIG_MANUAL_CONTROL; \ + uint32_t OTG_TRIGB_CNTL; \ + uint32_t OTG_TRIGB_MANUAL_TRIG; \ + uint32_t OTG_UPDATE_LOCK; \ + uint32_t OTG_V_TOTAL_INT_STATUS; \ + uint32_t OTG_VSYNC_NOM_INT_STATUS + struct dcn_optc_registers { OPTC_REG_VARIABLE_LIST_DCN; diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c index 4f1830ba619f0..c6417538090f2 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c @@ -315,6 +315,136 @@ void optc31_read_otg_state(struct timing_generator *optc, s->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL); } +void optc31_read_reg_state(struct timing_generator *optc, struct dcn_optc_reg_state *optc_reg_state) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + optc_reg_state->optc_bytes_per_pixel = REG_READ(OPTC_BYTES_PER_PIXEL); + optc_reg_state->optc_data_format_control = REG_READ(OPTC_DATA_FORMAT_CONTROL); + optc_reg_state->optc_data_source_select = REG_READ(OPTC_DATA_SOURCE_SELECT); + optc_reg_state->optc_input_clock_control = REG_READ(OPTC_INPUT_CLOCK_CONTROL); + optc_reg_state->optc_input_global_control = REG_READ(OPTC_INPUT_GLOBAL_CONTROL); + optc_reg_state->optc_input_spare_register = REG_READ(OPTC_INPUT_SPARE_REGISTER); + optc_reg_state->optc_memory_config = REG_READ(OPTC_MEMORY_CONFIG); + optc_reg_state->optc_rsmu_underflow = REG_READ(OPTC_RSMU_UNDERFLOW); + optc_reg_state->optc_underflow_threshold = REG_READ(OPTC_UNDERFLOW_THRESHOLD); + optc_reg_state->optc_width_control = REG_READ(OPTC_WIDTH_CONTROL); + optc_reg_state->otg_3d_structure_control = REG_READ(OTG_3D_STRUCTURE_CONTROL); + optc_reg_state->otg_clock_control = REG_READ(OTG_CLOCK_CONTROL); + optc_reg_state->otg_control = REG_READ(OTG_CONTROL); + optc_reg_state->otg_count_control = REG_READ(OTG_COUNT_CONTROL); + optc_reg_state->otg_count_reset = REG_READ(OTG_COUNT_RESET); + optc_reg_state->otg_crc_cntl = REG_READ(OTG_CRC_CNTL); + optc_reg_state->otg_crc_sig_blue_control_mask = REG_READ(OTG_CRC_SIG_BLUE_CONTROL_MASK); + optc_reg_state->otg_crc_sig_red_green_mask = REG_READ(OTG_CRC_SIG_RED_GREEN_MASK); + optc_reg_state->otg_crc0_data_b = REG_READ(OTG_CRC0_DATA_B); + optc_reg_state->otg_crc0_data_rg = REG_READ(OTG_CRC0_DATA_RG); + optc_reg_state->otg_crc0_windowa_x_control = REG_READ(OTG_CRC0_WINDOWA_X_CONTROL); + optc_reg_state->otg_crc0_windowa_x_control_readback = REG_READ(OTG_CRC0_WINDOWA_X_CONTROL_READBACK); + optc_reg_state->otg_crc0_windowa_y_control = REG_READ(OTG_CRC0_WINDOWA_Y_CONTROL); + optc_reg_state->otg_crc0_windowa_y_control_readback = REG_READ(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK); + optc_reg_state->otg_crc0_windowb_x_control = REG_READ(OTG_CRC0_WINDOWB_X_CONTROL); + optc_reg_state->otg_crc0_windowb_x_control_readback = REG_READ(OTG_CRC0_WINDOWB_X_CONTROL_READBACK); + optc_reg_state->otg_crc0_windowb_y_control = REG_READ(OTG_CRC0_WINDOWB_Y_CONTROL); + optc_reg_state->otg_crc0_windowb_y_control_readback = REG_READ(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK); + optc_reg_state->otg_crc1_data_b = REG_READ(OTG_CRC1_DATA_B); + optc_reg_state->otg_crc1_data_rg = REG_READ(OTG_CRC1_DATA_RG); + optc_reg_state->otg_crc1_windowa_x_control = REG_READ(OTG_CRC1_WINDOWA_X_CONTROL); + optc_reg_state->otg_crc1_windowa_x_control_readback = REG_READ(OTG_CRC1_WINDOWA_X_CONTROL_READBACK); + optc_reg_state->otg_crc1_windowa_y_control = REG_READ(OTG_CRC1_WINDOWA_Y_CONTROL); + optc_reg_state->otg_crc1_windowa_y_control_readback = REG_READ(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK); + optc_reg_state->otg_crc1_windowb_x_control = REG_READ(OTG_CRC1_WINDOWB_X_CONTROL); + optc_reg_state->otg_crc1_windowb_x_control_readback = REG_READ(OTG_CRC1_WINDOWB_X_CONTROL_READBACK); + optc_reg_state->otg_crc1_windowb_y_control = REG_READ(OTG_CRC1_WINDOWB_Y_CONTROL); + optc_reg_state->otg_crc1_windowb_y_control_readback = REG_READ(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK); + optc_reg_state->otg_crc2_data_b = REG_READ(OTG_CRC2_DATA_B); + optc_reg_state->otg_crc2_data_rg = REG_READ(OTG_CRC2_DATA_RG); + optc_reg_state->otg_crc3_data_b = REG_READ(OTG_CRC3_DATA_B); + optc_reg_state->otg_crc3_data_rg = REG_READ(OTG_CRC3_DATA_RG); + optc_reg_state->otg_dlpc_control = REG_READ(OTG_DLPC_CONTROL); + optc_reg_state->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL); + optc_reg_state->otg_drr_control2 = REG_READ(OTG_DRR_CONTROL2); + optc_reg_state->otg_drr_control = REG_READ(OTG_DRR_CONTROL); + optc_reg_state->otg_drr_timing_int_status = REG_READ(OTG_DRR_TIMING_INT_STATUS); + optc_reg_state->otg_drr_trigger_window = REG_READ(OTG_DRR_TRIGGER_WINDOW); + optc_reg_state->otg_drr_v_total_change = REG_READ(OTG_DRR_V_TOTAL_CHANGE); + optc_reg_state->otg_dsc_start_position = REG_READ(OTG_DSC_START_POSITION); + optc_reg_state->otg_force_count_now_cntl = REG_READ(OTG_FORCE_COUNT_NOW_CNTL); + optc_reg_state->otg_global_control0 = REG_READ(OTG_GLOBAL_CONTROL0); + optc_reg_state->otg_global_control1 = REG_READ(OTG_GLOBAL_CONTROL1); + optc_reg_state->otg_global_control2 = REG_READ(OTG_GLOBAL_CONTROL2); + optc_reg_state->otg_global_control3 = REG_READ(OTG_GLOBAL_CONTROL3); + optc_reg_state->otg_global_control4 = REG_READ(OTG_GLOBAL_CONTROL4); + optc_reg_state->otg_global_sync_status = REG_READ(OTG_GLOBAL_SYNC_STATUS); + optc_reg_state->otg_gsl_control = REG_READ(OTG_GSL_CONTROL); + optc_reg_state->otg_gsl_vsync_gap = REG_READ(OTG_GSL_VSYNC_GAP); + optc_reg_state->otg_gsl_window_x = REG_READ(OTG_GSL_WINDOW_X); + optc_reg_state->otg_gsl_window_y = REG_READ(OTG_GSL_WINDOW_Y); + optc_reg_state->otg_h_blank_start_end = REG_READ(OTG_H_BLANK_START_END); + optc_reg_state->otg_h_sync_a = REG_READ(OTG_H_SYNC_A); + optc_reg_state->otg_h_sync_a_cntl = REG_READ(OTG_H_SYNC_A_CNTL); + optc_reg_state->otg_h_timing_cntl = REG_READ(OTG_H_TIMING_CNTL); + optc_reg_state->otg_h_total = REG_READ(OTG_H_TOTAL); + optc_reg_state->otg_interlace_control = REG_READ(OTG_INTERLACE_CONTROL); + optc_reg_state->otg_interlace_status = REG_READ(OTG_INTERLACE_STATUS); + optc_reg_state->otg_interrupt_control = REG_READ(OTG_INTERRUPT_CONTROL); + optc_reg_state->otg_long_vblank_status = REG_READ(OTG_LONG_VBLANK_STATUS); + optc_reg_state->otg_m_const_dto0 = REG_READ(OTG_M_CONST_DTO0); + optc_reg_state->otg_m_const_dto1 = REG_READ(OTG_M_CONST_DTO1); + optc_reg_state->otg_manual_force_vsync_next_line = REG_READ(OTG_MANUAL_FORCE_VSYNC_NEXT_LINE); + optc_reg_state->otg_master_en = REG_READ(OTG_MASTER_EN); + optc_reg_state->otg_master_update_lock = REG_READ(OTG_MASTER_UPDATE_LOCK); + optc_reg_state->otg_master_update_mode = REG_READ(OTG_MASTER_UPDATE_MODE); + optc_reg_state->otg_nom_vert_position = REG_READ(OTG_NOM_VERT_POSITION); + optc_reg_state->otg_pipe_update_status = REG_READ(OTG_PIPE_UPDATE_STATUS); + optc_reg_state->otg_pixel_data_readback0 = REG_READ(OTG_PIXEL_DATA_READBACK0); + optc_reg_state->otg_pixel_data_readback1 = REG_READ(OTG_PIXEL_DATA_READBACK1); + optc_reg_state->otg_request_control = REG_READ(OTG_REQUEST_CONTROL); + optc_reg_state->otg_snapshot_control = REG_READ(OTG_SNAPSHOT_CONTROL); + optc_reg_state->otg_snapshot_frame = REG_READ(OTG_SNAPSHOT_FRAME); + optc_reg_state->otg_snapshot_position = REG_READ(OTG_SNAPSHOT_POSITION); + optc_reg_state->otg_snapshot_status = REG_READ(OTG_SNAPSHOT_STATUS); + optc_reg_state->otg_spare_register = REG_READ(OTG_SPARE_REGISTER); + optc_reg_state->otg_static_screen_control = REG_READ(OTG_STATIC_SCREEN_CONTROL); + optc_reg_state->otg_status = REG_READ(OTG_STATUS); + optc_reg_state->otg_status_frame_count = REG_READ(OTG_STATUS_FRAME_COUNT); + optc_reg_state->otg_status_hv_count = REG_READ(OTG_STATUS_HV_COUNT); + optc_reg_state->otg_status_position = REG_READ(OTG_STATUS_POSITION); + optc_reg_state->otg_status_vf_count = REG_READ(OTG_STATUS_VF_COUNT); + optc_reg_state->otg_stereo_control = REG_READ(OTG_STEREO_CONTROL); + optc_reg_state->otg_stereo_force_next_eye = REG_READ(OTG_STEREO_FORCE_NEXT_EYE); + optc_reg_state->otg_stereo_status = REG_READ(OTG_STEREO_STATUS); + optc_reg_state->otg_trig_manual_control = REG_READ(OTG_TRIG_MANUAL_CONTROL); + optc_reg_state->otg_triga_cntl = REG_READ(OTG_TRIGA_CNTL); + optc_reg_state->otg_triga_manual_trig = REG_READ(OTG_TRIGA_MANUAL_TRIG); + optc_reg_state->otg_trigb_cntl = REG_READ(OTG_TRIGB_CNTL); + optc_reg_state->otg_trigb_manual_trig = REG_READ(OTG_TRIGB_MANUAL_TRIG); + optc_reg_state->otg_update_lock = REG_READ(OTG_UPDATE_LOCK); + optc_reg_state->otg_v_blank_start_end = REG_READ(OTG_V_BLANK_START_END); + optc_reg_state->otg_v_count_stop_control = REG_READ(OTG_V_COUNT_STOP_CONTROL); + optc_reg_state->otg_v_count_stop_control2 = REG_READ(OTG_V_COUNT_STOP_CONTROL2); + optc_reg_state->otg_v_sync_a = REG_READ(OTG_V_SYNC_A); + optc_reg_state->otg_v_sync_a_cntl = REG_READ(OTG_V_SYNC_A_CNTL); + optc_reg_state->otg_v_total = REG_READ(OTG_V_TOTAL); + optc_reg_state->otg_v_total_control = REG_READ(OTG_V_TOTAL_CONTROL); + optc_reg_state->otg_v_total_int_status = REG_READ(OTG_V_TOTAL_INT_STATUS); + optc_reg_state->otg_v_total_max = REG_READ(OTG_V_TOTAL_MAX); + optc_reg_state->otg_v_total_mid = REG_READ(OTG_V_TOTAL_MID); + optc_reg_state->otg_v_total_min = REG_READ(OTG_V_TOTAL_MIN); + optc_reg_state->otg_vert_sync_control = REG_READ(OTG_VERT_SYNC_CONTROL); + optc_reg_state->otg_vertical_interrupt0_control = REG_READ(OTG_VERTICAL_INTERRUPT0_CONTROL); + optc_reg_state->otg_vertical_interrupt0_position = REG_READ(OTG_VERTICAL_INTERRUPT0_POSITION); + optc_reg_state->otg_vertical_interrupt1_control = REG_READ(OTG_VERTICAL_INTERRUPT1_CONTROL); + optc_reg_state->otg_vertical_interrupt1_position = REG_READ(OTG_VERTICAL_INTERRUPT1_POSITION); + optc_reg_state->otg_vertical_interrupt2_control = REG_READ(OTG_VERTICAL_INTERRUPT2_CONTROL); + optc_reg_state->otg_vertical_interrupt2_position = REG_READ(OTG_VERTICAL_INTERRUPT2_POSITION); + optc_reg_state->otg_vready_param = REG_READ(OTG_VREADY_PARAM); + optc_reg_state->otg_vstartup_param = REG_READ(OTG_VSTARTUP_PARAM); + optc_reg_state->otg_vsync_nom_int_status = REG_READ(OTG_VSYNC_NOM_INT_STATUS); + optc_reg_state->otg_vupdate_keepout = REG_READ(OTG_VUPDATE_KEEPOUT); + optc_reg_state->otg_vupdate_param = REG_READ(OTG_VUPDATE_PARAM); +} + static const struct timing_generator_funcs dcn31_tg_funcs = { .validate_timing = optc1_validate_timing, .program_timing = optc1_program_timing, @@ -377,6 +507,7 @@ static const struct timing_generator_funcs dcn31_tg_funcs = { .init_odm = optc3_init_odm, .is_two_pixels_per_container = optc1_is_two_pixels_per_container, .read_otg_state = optc31_read_otg_state, + .optc_read_reg_state = optc31_read_reg_state, }; void dcn31_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h index 0f72c274f40bb..98f7d2e299c5a 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h @@ -274,4 +274,6 @@ void optc3_init_odm(struct timing_generator *optc); void optc31_read_otg_state(struct timing_generator *optc, struct dcn_otg_state *s); +void optc31_read_reg_state(struct timing_generator *optc, struct dcn_optc_reg_state *optc_reg_state); + #endif /* __DC_OPTC_DCN31_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c index 4a2caca372556..43ff957288b27 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c @@ -256,6 +256,7 @@ static const struct timing_generator_funcs dcn314_tg_funcs = { .set_h_timing_div_manual_mode = optc314_set_h_timing_div_manual_mode, .is_two_pixels_per_container = optc1_is_two_pixels_per_container, .read_otg_state = optc31_read_otg_state, + .optc_read_reg_state = optc31_read_reg_state, }; void dcn314_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index b2b226bcd871c..3dcb0d0c931cf 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -365,6 +365,7 @@ static const struct timing_generator_funcs dcn32_tg_funcs = { .get_otg_double_buffer_pending = optc3_get_otg_update_pending, .get_pipe_update_pending = optc3_get_pipe_update_pending, .read_otg_state = optc31_read_otg_state, + .optc_read_reg_state = optc31_read_reg_state, }; void dcn32_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c index 52d5ea98c86b1..f699e95059f3e 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c @@ -511,6 +511,7 @@ static const struct timing_generator_funcs dcn35_tg_funcs = { .set_long_vtotal = optc35_set_long_vtotal, .is_two_pixels_per_container = optc1_is_two_pixels_per_container, .read_otg_state = optc31_read_otg_state, + .optc_read_reg_state = optc31_read_reg_state, }; void dcn35_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c index 5af13706e6014..a8e978d1fae87 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c @@ -533,6 +533,7 @@ static const struct timing_generator_funcs dcn401_tg_funcs = { .set_vupdate_keepout = optc401_set_vupdate_keepout, .wait_update_lock_status = optc401_wait_update_lock_status, .read_otg_state = optc31_read_otg_state, + .optc_read_reg_state = optc31_read_reg_state, }; void dcn401_timing_generator_init(struct optc *optc1) From 2948d97b83226ea857393900f3922ecce88a6031 Mon Sep 17 00:00:00 2001 From: Meenakshikumar Somasundaram Date: Thu, 9 Oct 2025 09:13:49 -0400 Subject: [PATCH 2359/2653] drm/amd/display: update link encoder assignment [Why] Map a link encoder instance matching stream encoder instance if possible. [How] Get the stream encoder instance and assign the same link encoder instance if available. Reviewed-by: PeiChen Huang Signed-off-by: Meenakshikumar Somasundaram Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/dc/core/dc_resource.c | 43 ++++++++++++++----- 1 file changed, 33 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index bc5dedf5f60c3..c59173a4fd751 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -2690,17 +2690,40 @@ static inline int find_fixed_dio_link_enc(const struct dc_link *link) } static inline int find_free_dio_link_enc(const struct resource_context *res_ctx, - const struct dc_link *link, const struct resource_pool *pool) + const struct dc_link *link, const struct resource_pool *pool, struct dc_stream_state *stream) { - int i; + int i, j = -1; + int stream_enc_inst = -1; int enc_count = pool->dig_link_enc_count; - /* for dpia, check preferred encoder first and then the next one */ - for (i = 0; i < enc_count; i++) - if (res_ctx->dio_link_enc_ref_cnts[(link->dpia_preferred_eng_id + i) % enc_count] == 0) - break; + /* Find stream encoder instance for the stream */ + if (stream) { + for (i = 0; i < pool->pipe_count; i++) { + if ((res_ctx->pipe_ctx[i].stream == stream) && + (res_ctx->pipe_ctx[i].stream_res.stream_enc != NULL)) { + stream_enc_inst = res_ctx->pipe_ctx[i].stream_res.stream_enc->id; + break; + } + } + } - return (i >= 0 && i < enc_count) ? (link->dpia_preferred_eng_id + i) % enc_count : -1; + /* Assign dpia preferred > stream enc instance > available */ + for (i = 0; i < enc_count; i++) { + if (res_ctx->dio_link_enc_ref_cnts[i] == 0) { + if (j == -1) + j = i; + + if (link->dpia_preferred_eng_id == i) { + j = i; + break; + } + + if (stream_enc_inst == i) { + j = stream_enc_inst; + } + } + } + return j; } static inline void acquire_dio_link_enc( @@ -2781,7 +2804,7 @@ static bool add_dio_link_enc_to_ctx(const struct dc *dc, retain_dio_link_enc(res_ctx, enc_index); } else { if (stream->link->is_dig_mapping_flexible) - enc_index = find_free_dio_link_enc(res_ctx, stream->link, pool); + enc_index = find_free_dio_link_enc(res_ctx, stream->link, pool, stream); else { int link_index = 0; @@ -2791,7 +2814,7 @@ static bool add_dio_link_enc_to_ctx(const struct dc *dc, * one into the acquiring link. */ if (enc_index >= 0 && is_dio_enc_acquired_by_other_link(stream->link, enc_index, &link_index)) { - int new_enc_index = find_free_dio_link_enc(res_ctx, dc->links[link_index], pool); + int new_enc_index = find_free_dio_link_enc(res_ctx, dc->links[link_index], pool, stream); if (new_enc_index >= 0) swap_dio_link_enc_to_muxable_ctx(context, pool, new_enc_index, enc_index); @@ -5201,7 +5224,7 @@ struct link_encoder *get_temp_dio_link_enc( enc_index = link->eng_id; if (enc_index < 0) - enc_index = find_free_dio_link_enc(res_ctx, link, pool); + enc_index = find_free_dio_link_enc(res_ctx, link, pool, NULL); if (enc_index >= 0) link_enc = pool->link_encoders[enc_index]; From 705c4c4e1d649cd20302023288f3fc6fd7636c3e Mon Sep 17 00:00:00 2001 From: Dominik Kaszewski Date: Thu, 16 Oct 2025 08:44:08 +0200 Subject: [PATCH 2360/2653] drm/amd/display: Remove dc param from check_update [Why] dc_check_update_surfaces_for_stream should not have access to entire DC, especially not a mutable one. Concurrent checks should be able to run independently of one another, without risk of changing state. [How] * Replace dc and stream_status structs with new dc_check_config. * Move required fields from dc_debug and dc_caps to dc_check_config. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Dominik Kaszewski Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 51 +++++++++---------- drivers/gpu/drm/amd/display/dc/dc.h | 17 ++++--- drivers/gpu/drm/amd/display/dc/dc_stream.h | 5 +- .../dc/resource/dce100/dce100_resource.c | 7 ++- .../dc/resource/dce110/dce110_resource.c | 5 +- .../dc/resource/dce112/dce112_resource.c | 7 ++- .../dc/resource/dce120/dce120_resource.c | 8 ++- .../dc/resource/dce80/dce80_resource.c | 8 ++- .../dc/resource/dcn10/dcn10_resource.c | 7 ++- .../dc/resource/dcn20/dcn20_resource.c | 6 ++- .../dc/resource/dcn201/dcn201_resource.c | 6 ++- .../dc/resource/dcn21/dcn21_resource.c | 6 ++- .../dc/resource/dcn30/dcn30_resource.c | 6 ++- .../dc/resource/dcn301/dcn301_resource.c | 6 ++- .../dc/resource/dcn302/dcn302_resource.c | 6 ++- .../dc/resource/dcn303/dcn303_resource.c | 6 ++- .../dc/resource/dcn31/dcn31_resource.c | 6 ++- .../dc/resource/dcn314/dcn314_resource.c | 6 ++- .../dc/resource/dcn315/dcn315_resource.c | 6 ++- .../dc/resource/dcn316/dcn316_resource.c | 6 ++- .../dc/resource/dcn32/dcn32_resource.c | 6 ++- .../dc/resource/dcn321/dcn321_resource.c | 6 ++- .../dc/resource/dcn35/dcn35_resource.c | 6 ++- .../dc/resource/dcn351/dcn351_resource.c | 6 ++- .../dc/resource/dcn36/dcn36_resource.c | 6 ++- .../dc/resource/dcn401/dcn401_resource.c | 6 ++- 26 files changed, 152 insertions(+), 65 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 3f89ede61e73f..81769325e1a20 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1148,8 +1148,8 @@ static bool dc_construct(struct dc *dc, /* set i2c speed if not done by the respective dcnxxx__resource.c */ if (dc->caps.i2c_speed_in_khz_hdcp == 0) dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz; - if (dc->caps.max_optimizable_video_width == 0) - dc->caps.max_optimizable_video_width = 5120; + if (dc->check_config.max_optimizable_video_width == 0) + dc->check_config.max_optimizable_video_width = 5120; dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); if (!dc->clk_mgr) goto fail; @@ -2656,7 +2656,7 @@ static bool is_surface_in_context( return false; } -static enum surface_update_type get_plane_info_update_type(const struct dc *dc, const struct dc_surface_update *u) +static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u) { union surface_update_flags *update_flags = &u->surface->update_flags; enum surface_update_type update_type = UPDATE_TYPE_FAST; @@ -2760,7 +2760,7 @@ static enum surface_update_type get_plane_info_update_type(const struct dc *dc, } static enum surface_update_type get_scaling_info_update_type( - const struct dc *dc, + const struct dc_check_config *check_config, const struct dc_surface_update *u) { union surface_update_flags *update_flags = &u->surface->update_flags; @@ -2790,7 +2790,7 @@ static enum surface_update_type get_scaling_info_update_type( /* Making dst rect smaller requires a bandwidth change */ update_flags->bits.bandwidth_change = 1; - if (u->scaling_info->src_rect.width > dc->caps.max_optimizable_video_width && + if (u->scaling_info->src_rect.width > check_config->max_optimizable_video_width && (u->scaling_info->clip_rect.width > u->surface->clip_rect.width || u->scaling_info->clip_rect.height > u->surface->clip_rect.height)) /* Changing clip size of a large surface may result in MPC slice count change */ @@ -2817,7 +2817,8 @@ static enum surface_update_type get_scaling_info_update_type( return UPDATE_TYPE_FAST; } -static enum surface_update_type det_surface_update(const struct dc *dc, +static enum surface_update_type det_surface_update( + const struct dc_check_config *check_config, const struct dc_surface_update *u) { enum surface_update_type type; @@ -2831,10 +2832,10 @@ static enum surface_update_type det_surface_update(const struct dc *dc, update_flags->raw = 0; // Reset all flags - type = get_plane_info_update_type(dc, u); + type = get_plane_info_update_type(u); elevate_update_type(&overall_type, type); - type = get_scaling_info_update_type(dc, u); + type = get_scaling_info_update_type(check_config, u); elevate_update_type(&overall_type, type); if (u->flip_addr) { @@ -2911,7 +2912,7 @@ static enum surface_update_type det_surface_update(const struct dc *dc, elevate_update_type(&overall_type, type); } - if (dc->debug.enable_legacy_fast_update && + if (check_config->enable_legacy_fast_update && (update_flags->bits.gamma_change || update_flags->bits.gamut_remap_change || update_flags->bits.input_csc_change || @@ -2946,11 +2947,11 @@ static void force_immediate_gsl_plane_flip(struct dc *dc, struct dc_surface_upda } static enum surface_update_type check_update_surfaces_for_stream( - struct dc *dc, + const struct dc_check_config *check_config, struct dc_surface_update *updates, int surface_count, - struct dc_stream_update *stream_update, - const struct dc_stream_status *stream_status) + struct dc_stream_update *stream_update +) { int i; enum surface_update_type overall_type = UPDATE_TYPE_FAST; @@ -2972,7 +2973,7 @@ static enum surface_update_type check_update_surfaces_for_stream( stream_update->integer_scaling_update) su_flags->bits.scaling = 1; - if (dc->debug.enable_legacy_fast_update && stream_update->out_transfer_func) + if (check_config->enable_legacy_fast_update && stream_update->out_transfer_func) su_flags->bits.out_tf = 1; if (stream_update->abm_level) @@ -3016,13 +3017,13 @@ static enum surface_update_type check_update_surfaces_for_stream( /* Output transfer function changes do not require bandwidth recalculation, * so don't trigger a full update */ - if (!dc->debug.enable_legacy_fast_update && stream_update->out_transfer_func) + if (!check_config->enable_legacy_fast_update && stream_update->out_transfer_func) su_flags->bits.out_tf = 1; } for (i = 0 ; i < surface_count; i++) { enum surface_update_type type = - det_surface_update(dc, &updates[i]); + det_surface_update(check_config, &updates[i]); elevate_update_type(&overall_type, type); } @@ -3036,22 +3037,17 @@ static enum surface_update_type check_update_surfaces_for_stream( * See :c:type:`enum surface_update_type ` for explanation of update types */ enum surface_update_type dc_check_update_surfaces_for_stream( - struct dc *dc, + const struct dc_check_config *check_config, struct dc_surface_update *updates, int surface_count, - struct dc_stream_update *stream_update, - const struct dc_stream_status *stream_status) + struct dc_stream_update *stream_update) { - int i; - enum surface_update_type type; - if (stream_update) stream_update->stream->update_flags.raw = 0; - for (i = 0; i < surface_count; i++) + for (size_t i = 0; i < surface_count; i++) updates[i].surface->update_flags.raw = 0; - type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status); - return type; + return check_update_surfaces_for_stream(check_config, updates, surface_count, stream_update); } static struct dc_stream_status *stream_get_status( @@ -3473,8 +3469,7 @@ static bool update_planes_and_stream_state(struct dc *dc, context = dc->current_state; update_type = dc_check_update_surfaces_for_stream( - dc, srf_updates, surface_count, stream_update, stream_status); - + &dc->check_config, srf_updates, surface_count, stream_update); if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream)) update_type = UPDATE_TYPE_FULL; @@ -5209,7 +5204,7 @@ static bool update_planes_and_stream_v2(struct dc *dc, commit_minimal_transition_state_in_dc_update(dc, context, stream, srf_updates, surface_count); - if (is_fast_update_only && !dc->debug.enable_legacy_fast_update) { + if (is_fast_update_only && !dc->check_config.enable_legacy_fast_update) { commit_planes_for_stream_fast(dc, srf_updates, surface_count, @@ -5252,7 +5247,7 @@ static void commit_planes_and_stream_update_on_current_context(struct dc *dc, stream_update); if (fast_update_only(dc, fast_update, srf_updates, surface_count, stream_update, stream) && - !dc->debug.enable_legacy_fast_update) + !dc->check_config.enable_legacy_fast_update) commit_planes_for_stream_fast(dc, srf_updates, surface_count, diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 319630c813bc9..38890e5b5c294 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -286,6 +286,15 @@ struct dc_scl_caps { bool sharpener_support; }; +struct dc_check_config { + /** + * max video plane width that can be safely assumed to be always + * supported by single DPP pipe. + */ + unsigned int max_optimizable_video_width; + bool enable_legacy_fast_update; +}; + struct dc_caps { uint32_t max_streams; uint32_t max_links; @@ -301,11 +310,6 @@ struct dc_caps { unsigned int max_cursor_size; unsigned int max_buffered_cursor_size; unsigned int max_video_width; - /* - * max video plane width that can be safely assumed to be always - * supported by single DPP pipe. - */ - unsigned int max_optimizable_video_width; unsigned int min_horizontal_blanking_period; int linear_pitch_alignment; bool dcc_const_color; @@ -1131,7 +1135,6 @@ struct dc_debug_options { uint32_t fpo_vactive_min_active_margin_us; uint32_t fpo_vactive_max_blank_us; bool enable_hpo_pg_support; - bool enable_legacy_fast_update; bool disable_dc_mode_overwrite; bool replay_skip_crtc_disabled; bool ignore_pg;/*do nothing, let pmfw control it*/ @@ -1163,7 +1166,6 @@ struct dc_debug_options { bool enable_ips_visual_confirm; unsigned int sharpen_policy; unsigned int scale_to_sharpness_policy; - bool skip_full_updated_if_possible; unsigned int enable_oled_edp_power_up_opt; bool enable_hblank_borrow; bool force_subvp_df_throttle; @@ -1714,6 +1716,7 @@ struct dc { struct dc_debug_options debug; struct dc_versions versions; struct dc_caps caps; + struct dc_check_config check_config; struct dc_cap_funcs cap_funcs; struct dc_config config; struct dc_bounding_box_overrides bb_overrides; diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 76cf9fdedab0e..c68153c779725 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -474,11 +474,10 @@ void dc_enable_stereo( void dc_trigger_sync(struct dc *dc, struct dc_state *context); enum surface_update_type dc_check_update_surfaces_for_stream( - struct dc *dc, + const struct dc_check_config *check_config, struct dc_surface_update *updates, int surface_count, - struct dc_stream_update *stream_update, - const struct dc_stream_status *stream_status); + struct dc_stream_update *stream_update); /** * Create a new default stream for the requested sink diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index c4b4dc3ad8c9d..550466de1a660 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -402,8 +402,10 @@ static const struct dc_plane_cap plane_cap = { } }; -static const struct dc_debug_options debug_defaults = { - .enable_legacy_fast_update = true, +static const struct dc_debug_options debug_defaults = { 0 }; + +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = true, }; #define CTX ctx @@ -1093,6 +1095,7 @@ static bool dce100_resource_construct( dc->caps.disable_dp_clk_share = true; dc->caps.extended_aux_timeout_support = false; dc->debug = debug_defaults; + dc->check_config = config_defaults; for (i = 0; i < pool->base.pipe_count; i++) { pool->base.timing_generators[i] = diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c index cccde5a6f3cdf..9e14ffb3c9428 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c @@ -424,7 +424,9 @@ static const struct dc_plane_cap plane_cap = { 64 }; -static const struct dc_debug_options debug_defaults = { +static const struct dc_debug_options debug_defaults = { 0 }; + +static const struct dc_check_config config_defaults = { .enable_legacy_fast_update = true, }; @@ -1376,6 +1378,7 @@ static bool dce110_resource_construct( dc->caps.is_apu = true; dc->caps.extended_aux_timeout_support = false; dc->debug = debug_defaults; + dc->check_config = config_defaults; /************************************************* * Create resources * diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c index 869a8e515fc09..62977bcdeaa09 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c @@ -429,8 +429,10 @@ static const struct dc_plane_cap plane_cap = { 64 }; -static const struct dc_debug_options debug_defaults = { - .enable_legacy_fast_update = true, +static const struct dc_debug_options debug_defaults = { 0 }; + +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = true, }; #define CTX ctx @@ -1247,6 +1249,7 @@ static bool dce112_resource_construct( dc->caps.dual_link_dvi = true; dc->caps.extended_aux_timeout_support = false; dc->debug = debug_defaults; + dc->check_config = config_defaults; /************************************************* * Create resources * diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c index 540e04ec1e2d9..0770ea37183f9 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c @@ -526,8 +526,11 @@ static const struct dc_plane_cap plane_cap = { }; static const struct dc_debug_options debug_defaults = { - .disable_clock_gate = true, - .enable_legacy_fast_update = true, + .disable_clock_gate = true, +}; + +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = true, }; static struct clock_source *dce120_clock_source_create( @@ -1089,6 +1092,7 @@ static bool dce120_resource_construct( dc->caps.psp_setup_panel_mode = true; dc->caps.extended_aux_timeout_support = false; dc->debug = debug_defaults; + dc->check_config = config_defaults; /************************************************* * Create resources * diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c index 5b77697452022..c4a56ec60b82d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c @@ -418,8 +418,10 @@ static const struct dc_plane_cap plane_cap = { } }; -static const struct dc_debug_options debug_defaults = { - .enable_legacy_fast_update = true, +static const struct dc_debug_options debug_defaults = { 0 }; + +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = true, }; static const struct dce_dmcu_registers dmcu_regs = { @@ -919,6 +921,7 @@ static bool dce80_construct( dc->caps.dual_link_dvi = true; dc->caps.extended_aux_timeout_support = false; dc->debug = debug_defaults; + dc->check_config = config_defaults; /************************************************* * Create resources * @@ -1320,6 +1323,7 @@ static bool dce83_construct( dc->caps.min_horizontal_blanking_period = 80; dc->caps.is_apu = true; dc->debug = debug_defaults; + dc->check_config = config_defaults; /************************************************* * Create resources * diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c index 652c05c354947..f12367adf1451 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c @@ -556,10 +556,13 @@ static const struct dc_debug_options debug_defaults_drv = { .recovery_enabled = false, /*enable this by default after testing.*/ .max_downscale_src_width = 3840, .underflow_assert_delay_us = 0xFFFFFFFF, - .enable_legacy_fast_update = true, .using_dml2 = false, }; +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = true, +}; + static void dcn10_dpp_destroy(struct dpp **dpp) { kfree(TO_DCN10_DPP(*dpp)); @@ -1395,6 +1398,8 @@ static bool dcn10_resource_construct( dc->caps.color.mpc.ogam_rom_caps.pq = 0; dc->caps.color.mpc.ogam_rom_caps.hlg = 0; dc->caps.color.mpc.ocsc = 0; + dc->debug = debug_defaults_drv; + dc->check_config = config_defaults; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index f28e6efdc23d0..cc3a0bf9fc76e 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -718,10 +718,13 @@ static const struct dc_debug_options debug_defaults_drv = { .scl_reset_length10 = true, .sanity_checks = false, .underflow_assert_delay_us = 0xFFFFFFFF, - .enable_legacy_fast_update = true, .using_dml2 = false, }; +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = true, +}; + void dcn20_dpp_destroy(struct dpp **dpp) { kfree(TO_DCN20_DPP(*dpp)); @@ -2464,6 +2467,7 @@ static bool dcn20_resource_construct( dc->caps.color.mpc.ocsc = 1; dc->caps.dp_hdmi21_pcon_support = true; + dc->check_config = config_defaults; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c index 9a80bebcee485..055107843a70a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c @@ -614,10 +614,13 @@ static const struct dc_debug_options debug_defaults_drv = { .sanity_checks = false, .underflow_assert_delay_us = 0xFFFFFFFF, .enable_tri_buf = true, - .enable_legacy_fast_update = true, .using_dml2 = false, }; +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = true, +}; + static void dcn201_dpp_destroy(struct dpp **dpp) { kfree(TO_DCN201_DPP(*dpp)); @@ -1151,6 +1154,7 @@ static bool dcn201_resource_construct( dc->caps.color.mpc.ocsc = 1; dc->debug = debug_defaults_drv; + dc->check_config = config_defaults; /*a0 only, remove later*/ dc->work_arounds.no_connect_phy_config = true; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 1f94e4afca1e1..a41f33923b239 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -626,10 +626,13 @@ static const struct dc_debug_options debug_defaults_drv = { .usbc_combo_phy_reset_wa = true, .dmub_command_table = true, .use_max_lb = true, - .enable_legacy_fast_update = true, .using_dml2 = false, }; +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = true, +}; + static const struct dc_panel_config panel_config_defaults = { .psr = { .disable_psr = false, @@ -1457,6 +1460,7 @@ static bool dcn21_resource_construct( dc->caps.color.mpc.ocsc = 1; dc->caps.dp_hdmi21_pcon_support = true; + dc->check_config = config_defaults; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c index ff63f59ff928a..d0ebb733e8024 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c @@ -727,10 +727,13 @@ static const struct dc_debug_options debug_defaults_drv = { .dmub_command_table = true, .use_max_lb = true, .exit_idle_opt_for_cursor_updates = true, - .enable_legacy_fast_update = false, .using_dml2 = false, }; +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = false, +}; + static const struct dc_panel_config panel_config_defaults = { .psr = { .disable_psr = false, @@ -2374,6 +2377,7 @@ static bool dcn30_resource_construct( dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; } } + dc->check_config = config_defaults; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index 7cbf7cbc7d9db..f77b913a684ad 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -701,10 +701,13 @@ static const struct dc_debug_options debug_defaults_drv = { .dmub_command_table = true, .use_max_lb = false, .exit_idle_opt_for_cursor_updates = true, - .enable_legacy_fast_update = true, .using_dml2 = false, }; +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = true, +}; + static void dcn301_dpp_destroy(struct dpp **dpp) { kfree(TO_DCN20_DPP(*dpp)); @@ -1497,6 +1500,7 @@ static bool dcn301_resource_construct( bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled); dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; } + dc->check_config = config_defaults; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c index 61623cb518d9c..c0d4a1dc94f8a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c @@ -98,10 +98,13 @@ static const struct dc_debug_options debug_defaults_drv = { .dmub_command_table = true, .use_max_lb = true, .exit_idle_opt_for_cursor_updates = true, - .enable_legacy_fast_update = false, .using_dml2 = false, }; +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = false, +}; + static const struct dc_panel_config panel_config_defaults = { .psr = { .disable_psr = false, @@ -1290,6 +1293,7 @@ static bool dcn302_resource_construct( &is_vbios_interop_enabled); dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; } + dc->check_config = config_defaults; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c index 02b9a84f2db3b..75e09c2c283e0 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c @@ -98,10 +98,13 @@ static const struct dc_debug_options debug_defaults_drv = { .dmub_command_table = true, .use_max_lb = true, .exit_idle_opt_for_cursor_updates = true, - .enable_legacy_fast_update = false, .using_dml2 = false, }; +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = false, +}; + static const struct dc_panel_config panel_config_defaults = { .psr = { .disable_psr = false, @@ -1234,6 +1237,7 @@ static bool dcn303_resource_construct( bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled); dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; } + dc->check_config = config_defaults; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c index 3ed7f50554e21..0d667b54ccf81 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c @@ -888,12 +888,15 @@ static const struct dc_debug_options debug_defaults_drv = { } }, .disable_z10 = true, - .enable_legacy_fast_update = true, .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/ .dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE, .using_dml2 = false, }; +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = true, +}; + static const struct dc_panel_config panel_config_defaults = { .psr = { .disable_psr = false, @@ -1978,6 +1981,7 @@ static bool dcn31_resource_construct( dc->caps.vbios_lttpr_aware = true; } } + dc->check_config = config_defaults; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c index d4917a35b991a..3ccde75a4ecbf 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c @@ -924,12 +924,15 @@ static const struct dc_debug_options debug_defaults_drv = { }, .seamless_boot_odm_combine = true, - .enable_legacy_fast_update = true, .using_dml2 = false, .disable_dsc_power_gate = true, .min_disp_clk_khz = 100000, }; +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = true, +}; + static const struct dc_panel_config panel_config_defaults = { .psr = { .disable_psr = false, @@ -1910,6 +1913,7 @@ static bool dcn314_resource_construct( dc->caps.vbios_lttpr_aware = true; } } + dc->check_config = config_defaults; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index 82cc78c291d82..38f6328cda92a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -887,11 +887,14 @@ static const struct dc_debug_options debug_defaults_drv = { .afmt = true, } }, - .enable_legacy_fast_update = true, .psr_power_use_phy_fsm = 0, .using_dml2 = false, }; +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = true, +}; + static const struct dc_panel_config panel_config_defaults = { .psr = { .disable_psr = false, @@ -1939,6 +1942,7 @@ static bool dcn315_resource_construct( dc->caps.vbios_lttpr_aware = true; } } + dc->check_config = config_defaults; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c index ad65ec167cf0b..fd077f19e77d5 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c @@ -883,10 +883,13 @@ static const struct dc_debug_options debug_defaults_drv = { .afmt = true, } }, - .enable_legacy_fast_update = true, .using_dml2 = false, }; +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = true, +}; + static const struct dc_panel_config panel_config_defaults = { .psr = { .disable_psr = false, @@ -1816,6 +1819,7 @@ static bool dcn316_resource_construct( dc->caps.vbios_lttpr_aware = true; } } + dc->check_config = config_defaults; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index 3965a7f1b64b7..fcf69a020c485 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -738,10 +738,13 @@ static const struct dc_debug_options debug_defaults_drv = { .disable_dp_plus_plus_wa = true, .fpo_vactive_min_active_margin_us = 200, .fpo_vactive_max_blank_us = 1000, - .enable_legacy_fast_update = false, .disable_stutter_for_wm_program = true }; +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = false, +}; + static struct dce_aux *dcn32_aux_engine_create( struct dc_context *ctx, uint32_t inst) @@ -2294,6 +2297,7 @@ static bool dcn32_resource_construct( dc->caps.vbios_lttpr_aware = true; } } + dc->check_config = config_defaults; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c index b8410724a156c..9d0726aff5e9b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c @@ -730,11 +730,14 @@ static const struct dc_debug_options debug_defaults_drv = { .disable_subvp_high_refresh = false, .fpo_vactive_min_active_margin_us = 200, .fpo_vactive_max_blank_us = 1000, - .enable_legacy_fast_update = false, .disable_dc_mode_overwrite = true, .using_dml2 = false, }; +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = false, +}; + static struct dce_aux *dcn321_aux_engine_create( struct dc_context *ctx, uint32_t inst) @@ -1795,6 +1798,7 @@ static bool dcn321_resource_construct( dc->caps.vbios_lttpr_aware = true; } } + dc->check_config = config_defaults; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c index fff57f23f4f7a..c247749acb44e 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c @@ -767,7 +767,6 @@ static const struct dc_debug_options debug_defaults_drv = { .using_dml2 = true, .support_eDP1_5 = true, .enable_hpo_pg_support = false, - .enable_legacy_fast_update = true, .enable_single_display_2to1_odm_policy = true, .disable_idle_power_optimizations = false, .dmcub_emulation = false, @@ -788,6 +787,10 @@ static const struct dc_debug_options debug_defaults_drv = { .min_disp_clk_khz = 50000, }; +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = true, +}; + static const struct dc_panel_config panel_config_defaults = { .psr = { .disable_psr = false, @@ -1946,6 +1949,7 @@ static bool dcn35_resource_construct( dc->caps.vbios_lttpr_aware = true; } } + dc->check_config = config_defaults; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c index 0abd163b425e5..15479a0290090 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c @@ -747,7 +747,6 @@ static const struct dc_debug_options debug_defaults_drv = { .using_dml2 = true, .support_eDP1_5 = true, .enable_hpo_pg_support = false, - .enable_legacy_fast_update = true, .enable_single_display_2to1_odm_policy = true, .disable_idle_power_optimizations = false, .dmcub_emulation = false, @@ -768,6 +767,10 @@ static const struct dc_debug_options debug_defaults_drv = { .min_disp_clk_khz = 50000, }; +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = true, +}; + static const struct dc_panel_config panel_config_defaults = { .psr = { .disable_psr = false, @@ -1917,6 +1920,7 @@ static bool dcn351_resource_construct( dc->caps.vbios_lttpr_aware = true; } } + dc->check_config = config_defaults; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c index ca125ee6c2fb3..a5d64eaa0791f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c @@ -748,7 +748,6 @@ static const struct dc_debug_options debug_defaults_drv = { .using_dml2 = true, .support_eDP1_5 = true, .enable_hpo_pg_support = false, - .enable_legacy_fast_update = true, .enable_single_display_2to1_odm_policy = true, .disable_idle_power_optimizations = false, .dmcub_emulation = false, @@ -769,6 +768,10 @@ static const struct dc_debug_options debug_defaults_drv = { .min_disp_clk_khz = 50000, }; +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = true, +}; + static const struct dc_panel_config panel_config_defaults = { .psr = { .disable_psr = false, @@ -1918,6 +1921,7 @@ static bool dcn36_resource_construct( dc->caps.vbios_lttpr_aware = true; } } + dc->check_config = config_defaults; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 1d18807e47495..1b813e7a99a68 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -721,7 +721,6 @@ static const struct dc_debug_options debug_defaults_drv = { .alloc_extra_way_for_cursor = true, .min_prefetch_in_strobe_ns = 60000, // 60us .disable_unbounded_requesting = false, - .enable_legacy_fast_update = false, .dcc_meta_propagation_delay_us = 10, .fams_version = { .minor = 1, @@ -737,6 +736,10 @@ static const struct dc_debug_options debug_defaults_drv = { .force_cositing = CHROMA_COSITING_NONE + 1, }; +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = false, +}; + static struct dce_aux *dcn401_aux_engine_create( struct dc_context *ctx, uint32_t inst) @@ -1995,6 +1998,7 @@ static bool dcn401_resource_construct( dc->caps.vbios_lttpr_aware = true; } } + dc->check_config = config_defaults; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; From b42afb3c689d45b4ff845380acb60c54f928ccfe Mon Sep 17 00:00:00 2001 From: Zhongwei Zhang Date: Tue, 14 Oct 2025 10:46:49 +0800 Subject: [PATCH 2361/2653] drm/amd/display: init dispclk from bootup clock for DCN315 [Why] Driver does not pick up and save vbios's clocks during init clocks, the dispclk in clk_mgr will keep 0. OS might change the timing (lower the pixel clock) after boot. Then driver will set the dispclk to lower when safe_to_lower is false, for in clk_mgr dispclk is zero, it's illegal and causes garbage. [How] Dump and save the vbios's clocks, and init the dispclk in dcn315_init_clocks. Reviewed-by: Charlene Liu Signed-off-by: Zhongwei Zhang Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- .../dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 87 ++++++++++++++++++- .../dc/clk_mgr/dcn315/dcn315_clk_mgr.h | 1 + .../dc/resource/dcn315/dcn315_resource.c | 1 + 3 files changed, 87 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c index b315ed91e010b..3a881451e9da4 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c @@ -40,7 +40,7 @@ #include "dm_helpers.h" #include "dc_dmub_srv.h" - +#include "reg_helper.h" #include "logger_types.h" #undef DC_LOGGER #define DC_LOGGER \ @@ -48,9 +48,43 @@ #include "link_service.h" +#define MAX_INSTANCE 7 +#define MAX_SEGMENT 8 + +struct IP_BASE_INSTANCE { + unsigned int segment[MAX_SEGMENT]; +}; + +struct IP_BASE { + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; +}; + +static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0, 0, 0 } }, + { { 0x00016E00, 0x02401C00, 0, 0, 0, 0, 0, 0 } }, + { { 0x00017000, 0x02402000, 0, 0, 0, 0, 0, 0 } }, + { { 0x00017200, 0x02402400, 0, 0, 0, 0, 0, 0 } }, + { { 0x0001B000, 0x0242D800, 0, 0, 0, 0, 0, 0 } }, + { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0, 0, 0 } } } }; + +#define regCLK1_CLK0_CURRENT_CNT 0x0314 +#define regCLK1_CLK0_CURRENT_CNT_BASE_IDX 0 +#define regCLK1_CLK1_CURRENT_CNT 0x0315 +#define regCLK1_CLK1_CURRENT_CNT_BASE_IDX 0 +#define regCLK1_CLK2_CURRENT_CNT 0x0316 +#define regCLK1_CLK2_CURRENT_CNT_BASE_IDX 0 +#define regCLK1_CLK3_CURRENT_CNT 0x0317 +#define regCLK1_CLK3_CURRENT_CNT_BASE_IDX 0 +#define regCLK1_CLK4_CURRENT_CNT 0x0318 +#define regCLK1_CLK4_CURRENT_CNT_BASE_IDX 0 +#define regCLK1_CLK5_CURRENT_CNT 0x0319 +#define regCLK1_CLK5_CURRENT_CNT_BASE_IDX 0 + #define TO_CLK_MGR_DCN315(clk_mgr)\ container_of(clk_mgr, struct clk_mgr_dcn315, base) +#define REG(reg_name) \ + (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) + #define UNSUPPORTED_DCFCLK 10000000 #define MIN_DPP_DISP_CLK 100000 @@ -245,9 +279,38 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); } +static void dcn315_dump_clk_registers_internal(struct dcn35_clk_internal *internal, struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + + // read dtbclk + internal->CLK1_CLK4_CURRENT_CNT = REG_READ(CLK1_CLK4_CURRENT_CNT); + + // read dcfclk + internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT); + + // read dppclk + internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT); + + // read dprefclk + internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT); + + // read dispclk + internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT); +} + static void dcn315_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) { + struct dcn35_clk_internal internal = {0}; + + dcn315_dump_clk_registers_internal(&internal, clk_mgr_base); + + regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; + regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10; + regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10; + regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; + regs_and_bypass->dtbclk = internal.CLK1_CLK4_CURRENT_CNT / 10; return; } @@ -594,13 +657,32 @@ static struct clk_mgr_funcs dcn315_funcs = { .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, .update_clocks = dcn315_update_clocks, - .init_clocks = dcn31_init_clocks, + .init_clocks = dcn315_init_clocks, .enable_pme_wa = dcn315_enable_pme_wa, .are_clock_states_equal = dcn31_are_clock_states_equal, .notify_wm_ranges = dcn315_notify_wm_ranges }; extern struct clk_mgr_funcs dcn3_fpga_funcs; +void dcn315_init_clocks(struct clk_mgr *clk_mgr) +{ + struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr); + uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; + struct clk_mgr_dcn315 *clk_mgr_dcn315 = TO_CLK_MGR_DCN315(clk_mgr_int); + struct clk_log_info log_info = {0}; + + memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); + // Assumption is that boot state always supports pstate + clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk + clk_mgr->clks.p_state_change_support = true; + clk_mgr->clks.prev_p_state_change_support = true; + clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; + clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN; + + dcn315_dump_clk_registers(&clk_mgr->boot_snapshot, &clk_mgr_dcn315->base.base, &log_info); + clk_mgr->clks.dispclk_khz = clk_mgr->boot_snapshot.dispclk * 1000; +} + void dcn315_clk_mgr_construct( struct dc_context *ctx, struct clk_mgr_dcn315 *clk_mgr, @@ -661,6 +743,7 @@ void dcn315_clk_mgr_construct( /* Saved clocks configured at boot for debug purposes */ dcn315_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info); + clk_mgr->base.base.clks.dispclk_khz = clk_mgr->base.base.boot_snapshot.dispclk * 1000; clk_mgr->base.base.dprefclk_khz = 600000; clk_mgr->base.base.dprefclk_khz = dcn315_smu_get_dpref_clk(&clk_mgr->base); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h index ac36ddf5dd1af..642ae3d4a7909 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h @@ -44,6 +44,7 @@ void dcn315_clk_mgr_construct(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg); +void dcn315_init_clocks(struct clk_mgr *clk_mgr); void dcn315_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int); #endif //__DCN315_CLK_MGR_H__ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index 38f6328cda92a..4e962f522f1be 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -889,6 +889,7 @@ static const struct dc_debug_options debug_defaults_drv = { }, .psr_power_use_phy_fsm = 0, .using_dml2 = false, + .min_disp_clk_khz = 100000, }; static const struct dc_check_config config_defaults = { From bc9d74004b24783e69a43872100e41ee32be9174 Mon Sep 17 00:00:00 2001 From: Meenakshikumar Somasundaram Date: Wed, 15 Oct 2025 14:45:43 -0400 Subject: [PATCH 2362/2653] drm/amd/display: Add dc interface to log pre os firmware information [Why] Pre os firmware information is useful to debug pre os to post os fw transition issues. [How] Add dc interface dc_log_preos_dmcub_info() to log pre os firmware information. Reviewed-by: Cruise Hung Signed-off-by: Meenakshikumar Somasundaram Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +++ drivers/gpu/drm/amd/display/dc/dc.h | 2 + drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 21 ++++++++++ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 7 ++++ drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 25 ++++++++++++ .../gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 39 +++++++++++++++++++ .../gpu/drm/amd/display/dmub/src/dmub_dcn35.h | 2 + .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 9 +++++ 8 files changed, 110 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 81769325e1a20..e6205267f38e0 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -6402,3 +6402,8 @@ void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, if (dc->hwss.get_underflow_debug_data) dc->hwss.get_underflow_debug_data(dc, tg, out_data); } + +void dc_log_preos_dmcub_info(const struct dc *dc) +{ + dc_dmub_srv_log_preos_dmcub_info(dc->ctx->dmub_srv); +} diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 38890e5b5c294..cac3aa93cc55c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -2730,6 +2730,8 @@ unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context); bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index); +void dc_log_preos_dmcub_info(const struct dc *dc); + /* DSC Interfaces */ #include "dc_dsc.h" diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index 4b20c01bf6461..fffbf1983143d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -2344,3 +2344,24 @@ void dc_dmub_srv_release_hw(const struct dc *dc) dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); } + +void dc_dmub_srv_log_preos_dmcub_info(struct dc_dmub_srv *dc_dmub_srv) +{ + struct dmub_srv *dmub; + + if (!dc_dmub_srv || !dc_dmub_srv->dmub) + return; + + dmub = dc_dmub_srv->dmub; + + if (dmub_srv_get_preos_info(dmub)) { + DC_LOG_DEBUG("%s: PreOS DMCUB Info", __func__); + DC_LOG_DEBUG("fw_version : 0x%08x", dmub->preos_info.fw_version); + DC_LOG_DEBUG("boot_options : 0x%08x", dmub->preos_info.boot_options); + DC_LOG_DEBUG("boot_status : 0x%08x", dmub->preos_info.boot_status); + DC_LOG_DEBUG("trace_buffer_phy_addr : 0x%016llx", dmub->preos_info.trace_buffer_phy_addr); + DC_LOG_DEBUG("trace_buffer_size_bytes : 0x%08x", dmub->preos_info.trace_buffer_size); + DC_LOG_DEBUG("fb_base : 0x%016llx", dmub->preos_info.fb_base); + DC_LOG_DEBUG("fb_offset : 0x%016llx", dmub->preos_info.fb_offset); + } +} diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h index 9bb00d48fd5e1..72e0a41f39f04 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h @@ -367,4 +367,11 @@ bool dc_dmub_srv_is_cursor_offload_enabled(const struct dc *dc); * @dc - pointer to DC object */ void dc_dmub_srv_release_hw(const struct dc *dc); + +/** + * dc_dmub_srv_log_preos_dmcub_info() - Logs preos dmcub fw info. + * + * @dc - pointer to DC object + */ +void dc_dmub_srv_log_preos_dmcub_info(struct dc_dmub_srv *dc_dmub_srv); #endif /* _DMUB_DC_SRV_H_ */ diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index f25c2fc2f98fd..9d0168986fe7a 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -363,6 +363,19 @@ struct dmub_diagnostic_data { uint8_t is_pwait : 1; }; +/** + * struct dmub_preos_info - preos fw info before loading post os fw. + */ +struct dmub_preos_info { + uint64_t fb_base; + uint64_t fb_offset; + uint64_t trace_buffer_phy_addr; + uint32_t trace_buffer_size; + uint32_t fw_version; + uint32_t boot_status; + uint32_t boot_options; +}; + struct dmub_srv_inbox { /* generic status */ uint64_t num_submitted; @@ -488,6 +501,7 @@ struct dmub_srv_hw_funcs { uint32_t (*get_current_time)(struct dmub_srv *dmub); void (*get_diagnostic_data)(struct dmub_srv *dmub); + bool (*get_preos_fw_info)(struct dmub_srv *dmub); bool (*should_detect)(struct dmub_srv *dmub); void (*init_reg_offsets)(struct dmub_srv *dmub, struct dc_context *ctx); @@ -588,6 +602,7 @@ struct dmub_srv { enum dmub_srv_power_state_type power_state; struct dmub_diagnostic_data debug; struct dmub_fb lsdma_rb_fb; + struct dmub_preos_info preos_info; }; /** @@ -1073,4 +1088,14 @@ enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub, */ enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub); +/** + * dmub_srv_get_preos_info() - retrieves preos fw info + * @dmub: the dmub service + * + * Return: + * true - preos fw info retrieved successfully + * false - preos fw info not retrieved successfully + */ +bool dmub_srv_get_preos_info(struct dmub_srv *dmub); + #endif /* _DMUB_SRV_H_ */ diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c index b40482dbd6ad6..e13557ed97be5 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c @@ -521,6 +521,45 @@ void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub) dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); } + +bool dmub_dcn35_get_preos_fw_info(struct dmub_srv *dmub) +{ + uint64_t region3_cw5_offset; + uint32_t top_addr, top_addr_enable, offset_low; + uint32_t offset_high, base_addr, fw_version; + bool is_vbios_fw = false; + + memset(&dmub->preos_info, 0, sizeof(dmub->preos_info)); + + fw_version = REG_READ(DMCUB_SCRATCH1); + is_vbios_fw = ((fw_version >> 6) & 0x01) ? true : false; + if (!is_vbios_fw) + return false; + + dmub->preos_info.boot_status = REG_READ(DMCUB_SCRATCH0); + dmub->preos_info.fw_version = REG_READ(DMCUB_SCRATCH1); + dmub->preos_info.boot_options = REG_READ(DMCUB_SCRATCH14); + REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS, + DMCUB_REGION3_CW5_ENABLE, &top_addr_enable); + if (top_addr_enable) { + dmub_dcn35_get_fb_base_offset(dmub, + &dmub->preos_info.fb_base, &dmub->preos_info.fb_offset); + offset_low = REG_READ(DMCUB_REGION3_CW5_OFFSET); + offset_high = REG_READ(DMCUB_REGION3_CW5_OFFSET_HIGH); + region3_cw5_offset = ((uint64_t)offset_high << 32) | offset_low; + dmub->preos_info.trace_buffer_phy_addr = region3_cw5_offset + - dmub->preos_info.fb_base + dmub->preos_info.fb_offset; + + REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS, + DMCUB_REGION3_CW5_TOP_ADDRESS, &top_addr); + base_addr = REG_READ(DMCUB_REGION3_CW5_BASE_ADDRESS) & 0x1FFFFFFF; + dmub->preos_info.trace_buffer_size = + (top_addr > base_addr) ? (top_addr - base_addr + 1) : 0; + } + + return true; +} + void dmub_dcn35_configure_dmub_in_system_memory(struct dmub_srv *dmub) { /* DMCUB_REGION3_TMR_AXI_SPACE values: diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h index 39fcb7275da51..92e6695a2c9ba 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h @@ -285,4 +285,6 @@ bool dmub_dcn35_is_hw_powered_up(struct dmub_srv *dmub); void dmub_srv_dcn35_regs_init(struct dmub_srv *dmub, struct dc_context *ctx); +bool dmub_dcn35_get_preos_fw_info(struct dmub_srv *dmub); + #endif /* _DMUB_DCN35_H_ */ diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c index 0244c9b44eccf..a657efda89ce3 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c @@ -359,6 +359,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) funcs->get_current_time = dmub_dcn35_get_current_time; funcs->get_diagnostic_data = dmub_dcn35_get_diagnostic_data; + funcs->get_preos_fw_info = dmub_dcn35_get_preos_fw_info; funcs->init_reg_offsets = dmub_srv_dcn35_regs_init; if (asic == DMUB_ASIC_DCN351) @@ -1372,3 +1373,11 @@ enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub) return DMUB_STATUS_OK; } + +bool dmub_srv_get_preos_info(struct dmub_srv *dmub) +{ + if (!dmub || !dmub->hw_funcs.get_preos_fw_info) + return false; + + return dmub->hw_funcs.get_preos_fw_info(dmub); +} From 0863056221bf5da7bda222eb53b77db4d65c6c1d Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Thu, 2 Oct 2025 12:44:19 -0400 Subject: [PATCH 2363/2653] drm/amd/display: Update cursor offload assignments [Why & How] - Cursor lines per chunk must be assigned from hubp->att and not hubp->pos (the one in hubp->pos is unassigned) - In DCN401 DPP, cur0_enable in attribute struct must be assigned as this is the field passed to DMU - DCN401 should not program position in driver if offload is enabled Reviewed-by: Nicholas Kazlauskas Signed-off-by: Alvin Lee Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- .../amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c | 1 + .../amd/display/dc/hubp/dcn401/dcn401_hubp.c | 24 ++++++++++--------- .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 2 +- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 2 +- 4 files changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c index 3adc17f2fc35b..62bf7cea21d82 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c @@ -141,6 +141,7 @@ void dpp401_set_cursor_position( } dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en; + dpp_base->att.cur0_ctl.bits.cur0_enable = cur_en; } void dpp401_set_optional_cursor_attributes( diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c index 3a2e0848173e9..f01eae50d02f7 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c @@ -783,21 +783,23 @@ void hubp401_cursor_set_position( if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); - REG_UPDATE(CURSOR_CONTROL, - CURSOR_ENABLE, cur_en); + if (!hubp->cursor_offload) + REG_UPDATE(CURSOR_CONTROL, + CURSOR_ENABLE, cur_en); } - REG_SET_2(CURSOR_POSITION, 0, - CURSOR_X_POSITION, x_pos, - CURSOR_Y_POSITION, y_pos); + if (!hubp->cursor_offload) { + REG_SET_2(CURSOR_POSITION, 0, + CURSOR_X_POSITION, x_pos, + CURSOR_Y_POSITION, y_pos); - REG_SET_2(CURSOR_HOT_SPOT, 0, - CURSOR_HOT_SPOT_X, pos->x_hotspot, - CURSOR_HOT_SPOT_Y, pos->y_hotspot); - - REG_SET(CURSOR_DST_OFFSET, 0, - CURSOR_DST_X_OFFSET, dst_x_offset); + REG_SET_2(CURSOR_HOT_SPOT, 0, + CURSOR_HOT_SPOT_X, pos->x_hotspot, + CURSOR_HOT_SPOT_Y, pos->y_hotspot); + REG_SET(CURSOR_DST_OFFSET, 0, + CURSOR_DST_X_OFFSET, dst_x_offset); + } /* Cursor Position Register Config */ hubp->pos.cur_ctl.bits.cur_enable = cur_en; hubp->pos.position.bits.x_pos = pos->x; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 9333b7fde3bcb..7aa0f452e8f7a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -1699,7 +1699,7 @@ void dcn35_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe p->CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE = hubp->att.cur_ctl.bits.mode; p->CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY = hubp->pos.cur_ctl.bits.cur_2x_magnify; p->CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH = hubp->att.cur_ctl.bits.pitch; - p->CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK = hubp->pos.cur_ctl.bits.line_per_chunk; + p->CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK = hubp->att.cur_ctl.bits.line_per_chunk; p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE = dpp->att.cur0_ctl.bits.cur0_enable; p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE = dpp->att.cur0_ctl.bits.mode; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index b9c357a407074..f02edc9371b0a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -2996,7 +2996,7 @@ void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pip p->CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE = hubp->att.cur_ctl.bits.mode; p->CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY = hubp->pos.cur_ctl.bits.cur_2x_magnify; p->CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH = hubp->att.cur_ctl.bits.pitch; - p->CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK = hubp->pos.cur_ctl.bits.line_per_chunk; + p->CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK = hubp->att.cur_ctl.bits.line_per_chunk; p->CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE = dpp->att.cur0_ctl.bits.cur0_enable; p->CM_CUR0_CURSOR0_CONTROL__CUR0_MODE = dpp->att.cur0_ctl.bits.mode; From 74b9bfbb0cbaf23a9b983f3dd16353d89f7bb60f Mon Sep 17 00:00:00 2001 From: Dominik Kaszewski Date: Wed, 30 Jul 2025 15:16:15 +0200 Subject: [PATCH 2364/2653] drm/amd/display: Add lock descriptor to check_update [Why] DM locks the global DC lock during all updates, even if multiple updates touch different resources and could be run in parallel. [How] Add extra enum specifying which kind of resources should be locked. Reviewed-by: Aric Cyr Signed-off-by: Dominik Kaszewski Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 125 +++++++++++---------- drivers/gpu/drm/amd/display/dc/dc.h | 13 +++ drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 +- 3 files changed, 82 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e6205267f38e0..c9c940f669613 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -148,10 +148,16 @@ static const char DC_BUILD_ID[] = "production-build"; /* Private functions */ -static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new) +static inline void elevate_update_type( + struct surface_update_descriptor *descriptor, + enum surface_update_type new_type, + enum dc_lock_descriptor new_locks +) { - if (new > *original) - *original = new; + if (new_type > descriptor->update_type) + descriptor->update_type = new_type; + + descriptor->lock_descriptor |= new_locks; } static void destroy_links(struct dc *dc) @@ -2656,47 +2662,49 @@ static bool is_surface_in_context( return false; } -static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u) +static struct surface_update_descriptor get_plane_info_update_type(const struct dc_surface_update *u) { union surface_update_flags *update_flags = &u->surface->update_flags; - enum surface_update_type update_type = UPDATE_TYPE_FAST; + struct surface_update_descriptor update_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE }; if (!u->plane_info) - return UPDATE_TYPE_FAST; + return update_type; + + elevate_update_type(&update_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_PLANE); if (u->plane_info->color_space != u->surface->color_space) { update_flags->bits.color_space_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_MED); + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); } if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) { update_flags->bits.horizontal_mirror_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_MED); + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); } if (u->plane_info->rotation != u->surface->rotation) { update_flags->bits.rotation_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_FULL); + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); } if (u->plane_info->format != u->surface->format) { update_flags->bits.pixel_format_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_FULL); + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); } if (u->plane_info->stereo_format != u->surface->stereo_format) { update_flags->bits.stereo_format_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_FULL); + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); } if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) { update_flags->bits.per_pixel_alpha_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_MED); + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); } if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) { update_flags->bits.global_alpha_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_MED); + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); } if (u->plane_info->dcc.enable != u->surface->dcc.enable @@ -2708,7 +2716,7 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa * recalculate stutter period. */ update_flags->bits.dcc_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_FULL); + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); } if (resource_pixel_format_to_bpp(u->plane_info->format) != @@ -2717,33 +2725,33 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa * and DML calculation */ update_flags->bits.bpp_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_FULL); + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); } if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) { update_flags->bits.plane_size_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_MED); + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); } const struct dc_tiling_info *tiling = &u->plane_info->tiling_info; if (memcmp(tiling, &u->surface->tiling_info, sizeof(*tiling)) != 0) { update_flags->bits.swizzle_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_MED); + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); switch (tiling->gfxversion) { case DcGfxVersion9: case DcGfxVersion10: case DcGfxVersion11: if (tiling->gfx9.swizzle != DC_SW_LINEAR) { - elevate_update_type(&update_type, UPDATE_TYPE_FULL); + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); update_flags->bits.bandwidth_change = 1; } break; case DcGfxAddr3: if (tiling->gfx_addr3.swizzle != DC_ADDR3_SW_LINEAR) { - elevate_update_type(&update_type, UPDATE_TYPE_FULL); + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); update_flags->bits.bandwidth_change = 1; } break; @@ -2759,14 +2767,17 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa return update_type; } -static enum surface_update_type get_scaling_info_update_type( +static struct surface_update_descriptor get_scaling_info_update_type( const struct dc_check_config *check_config, const struct dc_surface_update *u) { union surface_update_flags *update_flags = &u->surface->update_flags; + struct surface_update_descriptor update_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE }; if (!u->scaling_info) - return UPDATE_TYPE_FAST; + return update_type; + + elevate_update_type(&update_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_PLANE); if (u->scaling_info->src_rect.width != u->surface->src_rect.width || u->scaling_info->src_rect.height != u->surface->src_rect.height @@ -2809,40 +2820,41 @@ static enum surface_update_type get_scaling_info_update_type( if (update_flags->bits.clock_change || update_flags->bits.bandwidth_change || update_flags->bits.scaling_change) - return UPDATE_TYPE_FULL; + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); if (update_flags->bits.position_change) - return UPDATE_TYPE_MED; + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); - return UPDATE_TYPE_FAST; + return update_type; } -static enum surface_update_type det_surface_update( +static struct surface_update_descriptor det_surface_update( const struct dc_check_config *check_config, - const struct dc_surface_update *u) + struct dc_surface_update *u) { - enum surface_update_type type; - enum surface_update_type overall_type = UPDATE_TYPE_FAST; + struct surface_update_descriptor overall_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE }; union surface_update_flags *update_flags = &u->surface->update_flags; if (u->surface->force_full_update) { update_flags->raw = 0xFFFFFFFF; - return UPDATE_TYPE_FULL; + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); + return overall_type; } update_flags->raw = 0; // Reset all flags - type = get_plane_info_update_type(u); - elevate_update_type(&overall_type, type); + struct surface_update_descriptor inner_type = get_plane_info_update_type(u); - type = get_scaling_info_update_type(check_config, u); - elevate_update_type(&overall_type, type); + elevate_update_type(&overall_type, inner_type.update_type, inner_type.lock_descriptor); + + inner_type = get_scaling_info_update_type(check_config, u); + elevate_update_type(&overall_type, inner_type.update_type, inner_type.lock_descriptor); if (u->flip_addr) { update_flags->bits.addr_update = 1; if (u->flip_addr->address.tmz_surface != u->surface->address.tmz_surface) { update_flags->bits.tmz_changed = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FULL); + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); } } if (u->in_transfer_func) @@ -2878,13 +2890,15 @@ static enum surface_update_type det_surface_update( if (u->hdr_mult.value) if (u->hdr_mult.value != u->surface->hdr_mult.value) { update_flags->bits.hdr_mult = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_MED); + // TODO: Should be fast? + elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); } if (u->sdr_white_level_nits) if (u->sdr_white_level_nits != u->surface->sdr_white_level_nits) { update_flags->bits.sdr_white_level_nits = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FULL); + // TODO: Should be fast? + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); } if (u->cm2_params) { @@ -2898,18 +2912,16 @@ static enum surface_update_type det_surface_update( update_flags->bits.mcm_transfer_function_enable_change = 1; } if (update_flags->bits.in_transfer_func_change) { - type = UPDATE_TYPE_MED; - elevate_update_type(&overall_type, type); + // TODO: Fast? + elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); } if (update_flags->bits.lut_3d && u->surface->mcm_luts.lut3d_data.lut3d_src != DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { - type = UPDATE_TYPE_FULL; - elevate_update_type(&overall_type, type); + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); } if (update_flags->bits.mcm_transfer_function_enable_change) { - type = UPDATE_TYPE_FULL; - elevate_update_type(&overall_type, type); + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); } if (check_config->enable_legacy_fast_update && @@ -2917,8 +2929,7 @@ static enum surface_update_type det_surface_update( update_flags->bits.gamut_remap_change || update_flags->bits.input_csc_change || update_flags->bits.coeff_reduction_change)) { - type = UPDATE_TYPE_FULL; - elevate_update_type(&overall_type, type); + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); } return overall_type; } @@ -2946,28 +2957,28 @@ static void force_immediate_gsl_plane_flip(struct dc *dc, struct dc_surface_upda } } -static enum surface_update_type check_update_surfaces_for_stream( +static struct surface_update_descriptor check_update_surfaces_for_stream( const struct dc_check_config *check_config, struct dc_surface_update *updates, int surface_count, - struct dc_stream_update *stream_update -) + struct dc_stream_update *stream_update) { - int i; - enum surface_update_type overall_type = UPDATE_TYPE_FAST; + struct surface_update_descriptor overall_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE }; if (stream_update && stream_update->pending_test_pattern) { - overall_type = UPDATE_TYPE_FULL; + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); } if (stream_update && stream_update->hw_cursor_req) { - overall_type = UPDATE_TYPE_FULL; + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); } /* some stream updates require passive update */ if (stream_update) { union stream_update_flags *su_flags = &stream_update->stream->update_flags; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + if ((stream_update->src.height != 0 && stream_update->src.width != 0) || (stream_update->dst.height != 0 && stream_update->dst.width != 0) || stream_update->integer_scaling_update) @@ -3009,7 +3020,7 @@ static enum surface_update_type check_update_surfaces_for_stream( su_flags->bits.out_csc = 1; if (su_flags->raw != 0) - overall_type = UPDATE_TYPE_FULL; + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); if (stream_update->output_csc_transform) su_flags->bits.out_csc = 1; @@ -3021,11 +3032,11 @@ static enum surface_update_type check_update_surfaces_for_stream( su_flags->bits.out_tf = 1; } - for (i = 0 ; i < surface_count; i++) { - enum surface_update_type type = + for (int i = 0 ; i < surface_count; i++) { + struct surface_update_descriptor inner_type = det_surface_update(check_config, &updates[i]); - elevate_update_type(&overall_type, type); + elevate_update_type(&overall_type, inner_type.update_type, inner_type.lock_descriptor); } return overall_type; @@ -3036,7 +3047,7 @@ static enum surface_update_type check_update_surfaces_for_stream( * * See :c:type:`enum surface_update_type ` for explanation of update types */ -enum surface_update_type dc_check_update_surfaces_for_stream( +struct surface_update_descriptor dc_check_update_surfaces_for_stream( const struct dc_check_config *check_config, struct dc_surface_update *updates, int surface_count, @@ -3469,7 +3480,7 @@ static bool update_planes_and_stream_state(struct dc *dc, context = dc->current_state; update_type = dc_check_update_surfaces_for_stream( - &dc->check_config, srf_updates, surface_count, stream_update); + &dc->check_config, srf_updates, surface_count, stream_update).update_type; if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream)) update_type = UPDATE_TYPE_FULL; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index cac3aa93cc55c..76dd3f7fd67e4 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -467,6 +467,19 @@ enum surface_update_type { UPDATE_TYPE_FULL, /* may need to shuffle resources */ }; +enum dc_lock_descriptor { + LOCK_DESCRIPTOR_NONE = 0x0, + LOCK_DESCRIPTOR_STATE = 0x1, + LOCK_DESCRIPTOR_LINK = 0x2, + LOCK_DESCRIPTOR_STREAM = 0x4, + LOCK_DESCRIPTOR_PLANE = 0x8, +}; + +struct surface_update_descriptor { + enum surface_update_type update_type; + enum dc_lock_descriptor lock_descriptor; +}; + /* Forward declaration*/ struct dc; struct dc_plane_state; diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index c68153c779725..75869eed1d3a5 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -473,7 +473,7 @@ void dc_enable_stereo( /* Triggers multi-stream synchronization. */ void dc_trigger_sync(struct dc *dc, struct dc_state *context); -enum surface_update_type dc_check_update_surfaces_for_stream( +struct surface_update_descriptor dc_check_update_surfaces_for_stream( const struct dc_check_config *check_config, struct dc_surface_update *updates, int surface_count, From c49c109c9fd0d52c4e4ad5246811e389583e7f6f Mon Sep 17 00:00:00 2001 From: Dominik Kaszewski Date: Thu, 16 Oct 2025 13:46:25 +0200 Subject: [PATCH 2365/2653] drm/amd/display: Make observers const-correct [Why] Observers which do not modify their pointer arguments should take them as const. This clearly signals their intent to the caller, making it clear that the function is safe to call multiple times, or remove the call if the result is no longer necessary. [How] Made const-correct all of the functions below: * full_update_required[_weak] * fast_updates_exist * fast_update_only * dc_can_clear_cursor_limit * dc_stream_get_status (added const named overload) Reviewed-by: Nicholas Kazlauskas Signed-off-by: Dominik Kaszewski Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 44 ++++++++++--------- .../gpu/drm/amd/display/dc/core/dc_stream.c | 8 ++++ drivers/gpu/drm/amd/display/dc/dc.h | 2 +- drivers/gpu/drm/amd/display/dc/dc_stream.h | 4 +- 4 files changed, 35 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index c9c940f669613..0d7f0b416a745 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3428,11 +3428,12 @@ static void update_seamless_boot_flags(struct dc *dc, } } -static bool full_update_required_weak(struct dc *dc, - struct dc_surface_update *srf_updates, +static bool full_update_required_weak( + const struct dc *dc, + const struct dc_surface_update *srf_updates, int surface_count, - struct dc_stream_update *stream_update, - struct dc_stream_state *stream); + const struct dc_stream_update *stream_update, + const struct dc_stream_state *stream); /** * update_planes_and_stream_state() - The function takes planes and stream @@ -5016,7 +5017,7 @@ void populate_fast_updates(struct dc_fast_update *fast_update, } } -static bool fast_updates_exist(struct dc_fast_update *fast_update, int surface_count) +static bool fast_updates_exist(const struct dc_fast_update *fast_update, int surface_count) { int i; @@ -5057,11 +5058,12 @@ bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_ return false; } -static bool full_update_required_weak(struct dc *dc, - struct dc_surface_update *srf_updates, +static bool full_update_required_weak( + const struct dc *dc, + const struct dc_surface_update *srf_updates, int surface_count, - struct dc_stream_update *stream_update, - struct dc_stream_state *stream) + const struct dc_stream_update *stream_update, + const struct dc_stream_state *stream) { const struct dc_state *context = dc->current_state; if (srf_updates) @@ -5070,7 +5072,7 @@ static bool full_update_required_weak(struct dc *dc, return true; if (stream) { - const struct dc_stream_status *stream_status = dc_stream_get_status(stream); + const struct dc_stream_status *stream_status = dc_stream_get_status_const(stream); if (stream_status == NULL || stream_status->plane_count != surface_count) return true; } @@ -5083,11 +5085,12 @@ static bool full_update_required_weak(struct dc *dc, return false; } -static bool full_update_required(struct dc *dc, - struct dc_surface_update *srf_updates, +static bool full_update_required( + const struct dc *dc, + const struct dc_surface_update *srf_updates, int surface_count, - struct dc_stream_update *stream_update, - struct dc_stream_state *stream) + const struct dc_stream_update *stream_update, + const struct dc_stream_state *stream) { if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream)) return true; @@ -5147,12 +5150,13 @@ static bool full_update_required(struct dc *dc, return false; } -static bool fast_update_only(struct dc *dc, - struct dc_fast_update *fast_update, - struct dc_surface_update *srf_updates, +static bool fast_update_only( + const struct dc *dc, + const struct dc_fast_update *fast_update, + const struct dc_surface_update *srf_updates, int surface_count, - struct dc_stream_update *stream_update, - struct dc_stream_state *stream) + const struct dc_stream_update *stream_update, + const struct dc_stream_state *stream) { return fast_updates_exist(fast_update, surface_count) && !full_update_required(dc, srf_updates, surface_count, stream_update, stream); @@ -6384,7 +6388,7 @@ bool dc_is_cursor_limit_pending(struct dc *dc) return false; } -bool dc_can_clear_cursor_limit(struct dc *dc) +bool dc_can_clear_cursor_limit(const struct dc *dc) { uint32_t i; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 096fbb8ad24cd..6d309c3202533 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -224,6 +224,14 @@ struct dc_stream_status *dc_stream_get_status( return dc_state_get_stream_status(dc->current_state, stream); } +const struct dc_stream_status *dc_stream_get_status_const( + const struct dc_stream_state *stream) +{ + struct dc *dc = stream->ctx->dc; + + return dc_state_get_stream_status(dc->current_state, stream); +} + void program_cursor_attributes( struct dc *dc, struct dc_stream_state *stream) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 76dd3f7fd67e4..268b572b2b63e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -2760,7 +2760,7 @@ bool dc_is_timing_changed(struct dc_stream_state *cur_stream, struct dc_stream_state *new_stream); bool dc_is_cursor_limit_pending(struct dc *dc); -bool dc_can_clear_cursor_limit(struct dc *dc); +bool dc_can_clear_cursor_limit(const struct dc *dc); /** * dc_get_underflow_debug_data_for_otg() - Retrieve underflow debug data. diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 75869eed1d3a5..321cfe92d799a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -491,8 +491,8 @@ void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink); void dc_stream_retain(struct dc_stream_state *dc_stream); void dc_stream_release(struct dc_stream_state *dc_stream); -struct dc_stream_status *dc_stream_get_status( - struct dc_stream_state *dc_stream); +struct dc_stream_status *dc_stream_get_status(struct dc_stream_state *dc_stream); +const struct dc_stream_status *dc_stream_get_status_const(const struct dc_stream_state *dc_stream); /******************************************************************************* * Cursor interfaces - To manages the cursor within a stream From 263bb374f09eacde3f947d1ad16666bfdb62b546 Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Thu, 16 Oct 2025 20:08:10 -0600 Subject: [PATCH 2366/2653] drm/amd/display: Add HDR workaround for a specific eDP [WHY & HOW] Some eDP panels suffer from flicking when HDR is enabled in KDE or Gnome. This add another quirk to worksaround to skip VSC that is incompatible with an eDP panel. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/4452 Reviewed-by: Aurabindo Pillai Signed-off-by: Alex Hung Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 715aa904155bf..8c5f045ea25b4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -118,6 +118,7 @@ static void apply_edid_quirks(struct drm_device *dev, struct edid *edid, struct edid_caps->panel_patch.remove_sink_ext_caps = true; break; case drm_edid_encode_panel_id('S', 'D', 'C', 0x4154): + case drm_edid_encode_panel_id('S', 'D', 'C', 0x4171): drm_dbg_driver(dev, "Disabling VSC on monitor with panel id %X\n", panel_id); edid_caps->panel_patch.disable_colorimetry = true; break; From a76a8348e11fc511efbad19ff890ff554b9a9d73 Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Wed, 17 Sep 2025 11:00:02 -0400 Subject: [PATCH 2367/2653] drm/amd/display: Fix incorrect return of vblank enable on unconfigured crtc [Why&How] Return -EINVAL when userspace asks us to enable vblank on a crtc that is not yet enabled. Suggested-by: Aurabindo Pillai Reviewed-by: Aurabindo Pillai Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/1856 Signed-off-by: Ivan Lipski Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 914a1781ad38e..1500a13861d65 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -308,8 +308,12 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) int irq_type; int rc = 0; - if (acrtc->otg_inst == -1) - goto skip; + if (enable && !acrtc->base.enabled) { + drm_dbg_vbl(crtc->dev, + "Reject vblank enable on unconfigured CRTC %d (enabled=%d)\n", + acrtc->crtc_id, acrtc->base.enabled); + return -EINVAL; + } irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); @@ -396,7 +400,7 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) return rc; } #endif -skip: + if (amdgpu_in_reset(adev)) return 0; From ec9f55dc56cc0cc52aac683b4000b8c365fcd0a7 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 17 Oct 2025 17:20:46 -0400 Subject: [PATCH 2368/2653] drm/amd/display: [FW Promotion] Release 0.1.33.0 [Why & How] - Extend reply debug flags, define a new bit as debug_log_enabled - Replace the padding to frame_skip_number in struct dmub_cmd_replay_set_coasting_vtotal_data Acked-by: Tom Chung Signed-off-by: Taimur Hassan Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index c0a833ae606b0..ae6e17a26bbb3 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -485,7 +485,13 @@ union replay_debug_flags { */ uint32_t enable_visual_confirm_debug : 1; - uint32_t reserved : 18; + /** + * 0x4000 (bit 14) + * @debug_log_enabled: Debug Log Enabled + */ + uint32_t debug_log_enabled : 1; + + uint32_t reserved : 17; } bitfields; uint32_t u32All; @@ -4620,9 +4626,9 @@ struct dmub_cmd_replay_set_coasting_vtotal_data { */ uint16_t coasting_vtotal_high; /** - * Explicit padding to 4 byte boundary. + * frame skip number. */ - uint8_t pad[2]; + uint16_t frame_skip_number; }; /** From cf64ca7edf45b9ae9a23e8d47b6c4442374eb3aa Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 17 Oct 2025 19:22:02 -0500 Subject: [PATCH 2369/2653] drm/amd/display: Promote DC to 3.2.356 This version brings along following update: - Fix incorrect return of vblank enable on unconfigured crtc - Add HDR workaround for a specific eDP - Make observers const-correct - Add lock descriptor to check_update - Update cursor offload assignments - Add dc interface to log pre os firmware information - Init dispclk from bootup clock for DCN315 - Remove dc param from check_update - Update link encoder assignment - Add more DC HW state info to underflow logging - Rename dml2 to dml2_0 folder - Fix notification of vtotal to DMU for cursor offload - Fix wrong index for DCN401 cursor offload - Add opp count validation to dml2.1 - Fix DMUB reset sequence for DCN32 - Bump minimum for frame_warn_limit Acked-by: Tom Chung Signed-off-by: Taimur Hassan Signed-off-by: Wayne Lin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 268b572b2b63e..e02f3c128e113 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.355" +#define DC_VER "3.2.356" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From 3ce98bd9442b4398b2147e5199188d68c7be4eaa Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Fri, 18 Jul 2025 14:20:45 -0500 Subject: [PATCH 2370/2653] drm/amd: Re-introduce property to control adaptive backlight modulation commit 0887054d14ae2 ("drm/amd: Drop abm_level property") dropped the abm level property in favor of sysfs control. Since then there have been discussions that compositors showed an interest in modifying a vendor specific property instead. So re-introduce the abm level property, but with different semantics. Rather than being an integer it's now an enum. One of the enum options is 'sysfs', and that is because there is still a sysfs file for use by userspace when the compositor doesn't support this property. If usespace has not modified this property, the default value will be for sysfs to control it. Once userspace has set the property stop allowing sysfs control. The property is only attached to non-OLED eDP panels. Cc: Xaver Hugl Reviewed-by: Harry Wentland Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 60 ++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_display.h | 7 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 39 +++++++++++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + 5 files changed, 106 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 5c15ecfa80d7b..71536460c5a50 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1441,6 +1441,64 @@ static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = { { AMDGPU_FMT_DITHER_ENABLE, "on" }, }; +/** + * DOC: property for adaptive backlight modulation + * + * The 'adaptive backlight modulation' property is used for the compositor to + * directly control the adaptive backlight modulation power savings feature + * that is part of DCN hardware. + * + * The property will be attached specifically to eDP panels that support it. + * + * The property is by default set to 'sysfs' to allow the sysfs file 'panel_power_savings' + * to be able to control it. + * If set to 'off' the compositor will ensure it stays off. + * The other values 'min', 'bias min', 'bias max', and 'max' will control the + * intensity of the power savings. + * + * Modifying this value can have implications on color accuracy, so tread + * carefully. + */ +static int amdgpu_display_setup_abm_prop(struct amdgpu_device *adev) +{ + const struct drm_prop_enum_list props[] = { + { ABM_SYSFS_CONTROL, "sysfs" }, + { ABM_LEVEL_OFF, "off" }, + { ABM_LEVEL_MIN, "min" }, + { ABM_LEVEL_BIAS_MIN, "bias min" }, + { ABM_LEVEL_BIAS_MAX, "bias max" }, + { ABM_LEVEL_MAX, "max" }, + }; + struct drm_property *prop; + int i; + + if (!adev->dc_enabled) + return 0; + + prop = drm_property_create(adev_to_drm(adev), DRM_MODE_PROP_ENUM, + "adaptive backlight modulation", + 6); + if (!prop) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(props); i++) { + int ret; + + ret = drm_property_add_enum(prop, props[i].type, + props[i].name); + + if (ret) { + drm_property_destroy(adev_to_drm(adev), prop); + + return ret; + } + } + + adev->mode_info.abm_level_property = prop; + + return 0; +} + int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) { int sz; @@ -1487,7 +1545,7 @@ int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) "dither", amdgpu_dither_enum_list, sz); - return 0; + return amdgpu_display_setup_abm_prop(adev); } void amdgpu_display_update_priority(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h index c999addc3e939..dd4c421510685 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h @@ -59,4 +59,11 @@ int amdgpu_display_get_scanout_buffer(struct drm_plane *plane, struct drm_scanout_buffer *sb); #endif +#define ABM_SYSFS_CONTROL -1 +#define ABM_LEVEL_OFF 0 +#define ABM_LEVEL_MIN 1 +#define ABM_LEVEL_BIAS_MIN 2 +#define ABM_LEVEL_BIAS_MAX 3 +#define ABM_LEVEL_MAX 4 + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index cef3774efa98c..18676682df3e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -326,6 +326,8 @@ struct amdgpu_mode_info { struct drm_property *audio_property; /* FMT dithering */ struct drm_property *dither_property; + /* Adaptive Backlight Modulation (power feature) */ + struct drm_property *abm_level_property; /* hardcoded DFP edid from BIOS */ const struct drm_edid *bios_hardcoded_edid; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f8f03cfc5f475..f34a0e589431a 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5260,6 +5260,7 @@ static int initialize_plane(struct amdgpu_display_manager *dm, static void setup_backlight_device(struct amdgpu_display_manager *dm, struct amdgpu_dm_connector *aconnector) { + struct amdgpu_dm_backlight_caps *caps; struct dc_link *link = aconnector->dc_link; int bl_idx = dm->num_of_edps; @@ -5279,6 +5280,13 @@ static void setup_backlight_device(struct amdgpu_display_manager *dm, dm->num_of_edps++; update_connector_ext_caps(aconnector); + caps = &dm->backlight_caps[aconnector->bl_idx]; + + /* Only offer ABM property when non-OLED and user didn't turn off by module parameter */ + if (!caps->ext_caps->bits.oled && amdgpu_dm_abm_level < 0) + drm_object_attach_property(&aconnector->base.base, + dm->adev->mode_info.abm_level_property, + ABM_SYSFS_CONTROL); } static void amdgpu_set_panel_orientation(struct drm_connector *connector); @@ -7411,6 +7419,20 @@ int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, } else if (property == adev->mode_info.underscan_property) { dm_new_state->underscan_enable = val; ret = 0; + } else if (property == adev->mode_info.abm_level_property) { + switch (val) { + case ABM_SYSFS_CONTROL: + dm_new_state->abm_sysfs_forbidden = false; + break; + case ABM_LEVEL_OFF: + dm_new_state->abm_sysfs_forbidden = true; + dm_new_state->abm_level = ABM_LEVEL_IMMEDIATE_DISABLE; + break; + default: + dm_new_state->abm_sysfs_forbidden = true; + dm_new_state->abm_level = val; + }; + ret = 0; } return ret; @@ -7453,6 +7475,13 @@ int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, } else if (property == adev->mode_info.underscan_property) { *val = dm_state->underscan_enable; ret = 0; + } else if (property == adev->mode_info.abm_level_property) { + if (!dm_state->abm_sysfs_forbidden) + *val = ABM_SYSFS_CONTROL; + else + *val = (dm_state->abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ? + dm_state->abm_level : 0; + ret = 0; } return ret; @@ -7505,10 +7534,16 @@ static ssize_t panel_power_savings_store(struct device *device, return -EINVAL; drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); - to_dm_connector_state(connector->state)->abm_level = val ?: - ABM_LEVEL_IMMEDIATE_DISABLE; + if (to_dm_connector_state(connector->state)->abm_sysfs_forbidden) + ret = -EBUSY; + else + to_dm_connector_state(connector->state)->abm_level = val ?: + ABM_LEVEL_IMMEDIATE_DISABLE; drm_modeset_unlock(&dev->mode_config.connection_mutex); + if (ret) + return ret; + drm_kms_helper_hotplug_event(dev); return count; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 691450143488b..ca8750412ac10 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -999,6 +999,7 @@ struct dm_connector_state { bool underscan_enable; bool freesync_capable; bool update_hdcp; + bool abm_sysfs_forbidden; uint8_t abm_level; #if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) int vcpi_slots; From 64ed04bf90f35b2fca362c9b1f3559a052427963 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 30 Sep 2025 13:45:11 +0530 Subject: [PATCH 2371/2653] drm/amdgpu: clean up amdgpu hmm range functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clean up the amdgpu hmm range functions for clearer definition of each. a. Split amdgpu_ttm_tt_get_user_pages_done into two: 1. amdgpu_hmm_range_valid: To check if the user pages are valid and update seq num 2. amdgpu_hmm_range_free: Clean up the hmm range and pfn memory. b. amdgpu_ttm_tt_get_user_pages_done and amdgpu_ttm_tt_discard_user_pages are similar function so remove discard and directly use amdgpu_hmm_range_free to clean up the hmm range and pfn memory. Suggested-by: Christian König Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 18 ++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 10 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 6 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 23 ++++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 17 ++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 38 ------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 13 ------- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 9 +++-- 8 files changed, 55 insertions(+), 79 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index d4acda7bda131..62fd4a370943d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1153,7 +1153,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, } #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - range = kzalloc(sizeof(*range), GFP_KERNEL); + range = amdgpu_hmm_range_alloc(); if (unlikely(!range)) { ret = -ENOMEM; goto unregister_out; @@ -1161,7 +1161,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, ret = amdgpu_ttm_tt_get_user_pages(bo, range); if (ret) { - kfree(range); + amdgpu_hmm_range_free(range); if (ret == -EAGAIN) pr_debug("Failed to get user pages, try again\n"); else @@ -1210,7 +1210,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, release_out: #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); + amdgpu_hmm_range_free(range); #else if (ret) amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, NULL); @@ -2032,7 +2032,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( amdgpu_hmm_unregister(mem->bo); #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mutex_lock(&process_info->notifier_lock); - amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range); + amdgpu_hmm_range_free(mem->range); mutex_unlock(&process_info->notifier_lock); #else /* Free user pages if necessary */ @@ -2922,7 +2922,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, bo = mem->bo; #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range); + amdgpu_hmm_range_free(mem->range); mem->range = NULL; #endif @@ -2948,13 +2948,13 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, } #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - mem->range = kzalloc(sizeof(*mem->range), GFP_KERNEL); + mem->range = amdgpu_hmm_range_alloc(); if (unlikely(!mem->range)) return -ENOMEM; /* Get updated user pages */ ret = amdgpu_ttm_tt_get_user_pages(bo, mem->range); if (ret) { - kfree(mem->range); + amdgpu_hmm_range_free(mem->range); mem->range = NULL; pr_debug("Failed %d to get user pages\n", ret); @@ -3186,8 +3186,8 @@ static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_i continue; /* Only check mem with hmm range associated */ - valid = amdgpu_ttm_tt_get_user_pages_done( - mem->bo->tbo.ttm, mem->range); + valid = amdgpu_hmm_range_valid(mem->range); + amdgpu_hmm_range_free(mem->range); mem->range = NULL; if (!valid) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 6c03ae3e37ae8..caef2774b6950 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -916,7 +916,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, bool userpage_invalidated = false; struct amdgpu_bo *bo = e->bo; - e->range = kzalloc(sizeof(*e->range), GFP_KERNEL); + e->range = amdgpu_hmm_range_alloc(); if (unlikely(!e->range)) return -ENOMEM; @@ -1110,9 +1110,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, out_free_user_pages: #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { - struct amdgpu_bo *bo = e->bo; - - amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, e->range); + amdgpu_hmm_range_free(e->range); e->range = NULL; } #else @@ -1462,8 +1460,8 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, */ r = 0; amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { - r |= !amdgpu_ttm_tt_get_user_pages_done(e->bo->tbo.ttm, - e->range); + r |= !amdgpu_hmm_range_valid(e->range); + amdgpu_hmm_range_free(e->range); e->range = NULL; } if (r) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 0ea9ab4c0b26c..478184576f0ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -644,7 +644,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - range = kzalloc(sizeof(*range), GFP_KERNEL); + range = amdgpu_hmm_range_alloc(); if (unlikely(!range)) return -ENOMEM; r = amdgpu_ttm_tt_get_user_pages(bo, range); @@ -654,7 +654,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, #endif if (r) { #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - kfree(range); + amdgpu_hmm_range_free(range); #endif goto release_object; } @@ -692,7 +692,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, user_pages_done: #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) - amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); + amdgpu_hmm_range_free(range); #else release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 14e62c2be1149..55b2359799ae4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -919,19 +919,30 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, return r; } -bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range) +bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range) { - bool r; + if (!hmm_range) + return false; + + return !mmu_interval_read_retry(hmm_range->notifier, + hmm_range->notifier_seq); +} + +struct hmm_range *amdgpu_hmm_range_alloc(void) +{ + return kzalloc(sizeof(struct hmm_range), GFP_KERNEL); +} + +void amdgpu_hmm_range_free(struct hmm_range *hmm_range) +{ + if (!hmm_range) + return; - r = mmu_interval_read_retry(hmm_range->notifier, - hmm_range->notifier_seq); #ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT kvfree(hmm_range->pfns); #else kvfree(hmm_range->hmm_pfns); #endif kfree(hmm_range); - - return r; } #endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index e078aa4905e38..4ec014a918514 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -87,9 +87,11 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, void *owner, struct hmm_range *hmm_range); -bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range); #if defined(CONFIG_HMM_MIRROR) +bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range); +struct hmm_range *amdgpu_hmm_range_alloc(void); +void amdgpu_hmm_range_free(struct hmm_range *hmm_range); int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr); void amdgpu_hmm_unregister(struct amdgpu_bo *bo); #else @@ -99,7 +101,20 @@ static inline int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) "add CONFIG_ZONE_DEVICE=y in config file to fix this\n"); return -ENODEV; } + static inline void amdgpu_hmm_unregister(struct amdgpu_bo *bo) {} + +static inline bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range) +{ + return false; +} + +static inline struct hmm_range *amdgpu_hmm_range_alloc(void) +{ + return NULL; +} + +static inline void amdgpu_hmm_range_free(struct hmm_range *hmm_range) {} #endif #endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 6b129b9de809c..205b70ebfb19f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -826,44 +826,6 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, return r; } -/* amdgpu_ttm_tt_discard_user_pages - Discard range and pfn array allocations - */ -void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, - struct hmm_range *range) -{ - struct amdgpu_ttm_tt *gtt = (void *)ttm; - - if (gtt && gtt->userptr && range) - amdgpu_hmm_range_get_pages_done(range); -} - -/* - * amdgpu_ttm_tt_get_user_pages_done - stop HMM track the CPU page table change - * Check if the pages backing this ttm range have been invalidated - * - * Returns: true if pages are still valid - */ -bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, - struct hmm_range *range) -{ - struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); - - if (!gtt || !gtt->userptr || !range) - return false; - - DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", - gtt->userptr, ttm->num_pages); - -#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT - WARN_ONCE(!range->pfns, -#else - WARN_ONCE(!range->hmm_pfns, -#endif - "No user pages to check\n"); - - return !amdgpu_hmm_range_get_pages_done(range); -} - #else /* * amdgpu_ttm_tt_get_user_pages - Pin pages of memory pointed to by a USERPTR diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index a042b8c446b4a..27dd8129cd565 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -205,10 +205,6 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, struct hmm_range **range); #endif -void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, - struct hmm_range *range); -bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, - struct hmm_range *range); #else #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, @@ -223,15 +219,6 @@ static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page return -EPERM; } #endif -static inline void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm, - struct hmm_range *range) -{ -} -static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, - struct hmm_range *range) -{ - return false; -} #endif #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 5492b0e74260f..5639a51212e05 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1741,13 +1741,13 @@ static int svm_range_validate_and_map(struct mm_struct *mm, } WRITE_ONCE(p->svms.faulting_task, current); - hmm_range = kzalloc(sizeof(*hmm_range), GFP_KERNEL); + hmm_range = amdgpu_hmm_range_alloc(); r = amdgpu_hmm_range_get_pages(&prange->notifier, addr, npages, readonly, owner, hmm_range); WRITE_ONCE(p->svms.faulting_task, NULL); if (r) { - kfree(hmm_range); + amdgpu_hmm_range_free(hmm_range); pr_debug("failed %d to get svm range pages\n", r); } } else { @@ -1768,10 +1768,13 @@ static int svm_range_validate_and_map(struct mm_struct *mm, * Overrride return value to TRY AGAIN only if prior returns * were successful */ - if (hmm_range && amdgpu_hmm_range_get_pages_done(hmm_range) && !r) { + if (hmm_range && !amdgpu_hmm_range_valid(hmm_range) && !r) { pr_debug("hmm update the range, need validate again\n"); r = -EAGAIN; } + /* Free the hmm range */ + amdgpu_hmm_range_free(hmm_range); + if (!r && !list_empty(&prange->child_list)) { pr_debug("range split by unmap in parallel, validate again\n"); From c96d7cf43f26a23b0bffabc62c09fe7d053ae556 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Fri, 10 Oct 2025 18:09:57 +0530 Subject: [PATCH 2372/2653] drm/amdgpu: update the functions to use amdgpu version of hmm MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit At times we need a bo reference for hmm and for that add a new struct amdgpu_hmm_range which will hold an optional bo member and hmm_range. Use amdgpu_hmm_range instead of hmm_range and let the bo as an optional argument for the caller if they want to the bo reference to be taken or they want to handle that explicitly. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 6 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 33 ++++++++++++------- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 18 ++++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 7 ++-- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 1 - drivers/gpu/drm/amd/amdkfd/kfd_migrate.h | 1 - drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 14 ++++---- drivers/gpu/drm/amd/amdkfd/kfd_svm.h | 1 - 13 files changed, 56 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index bcdafcf91c272..40c46e6c88988 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -73,7 +73,7 @@ struct kgd_mem { struct kfd_ipc_obj *ipc_obj; struct dma_buf *dmabuf; #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - struct hmm_range *range; + struct amdgpu_hmm_range *range; #else struct page **user_pages; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 62fd4a370943d..741307be39678 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1120,7 +1120,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, struct amdkfd_process_info *process_info = mem->process_info; struct amdgpu_bo *bo = mem->bo; struct ttm_operation_ctx ctx = { true, false }; - struct hmm_range *range; + struct amdgpu_hmm_range *range; int ret = 0; mutex_lock(&process_info->lock); @@ -1153,7 +1153,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, } #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - range = amdgpu_hmm_range_alloc(); + range = amdgpu_hmm_range_alloc(NULL); if (unlikely(!range)) { ret = -ENOMEM; goto unregister_out; @@ -2948,7 +2948,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, } #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - mem->range = amdgpu_hmm_range_alloc(); + mem->range = amdgpu_hmm_range_alloc(NULL); if (unlikely(!mem->range)) return -ENOMEM; /* Get updated user pages */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h index e3f75a65fcb6b..43862a8082110 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h @@ -39,7 +39,7 @@ struct amdgpu_bo_list_entry { struct amdgpu_bo *bo; struct amdgpu_bo_va *bo_va; uint32_t priority; - struct hmm_range *range; + struct amdgpu_hmm_range *range; #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool user_invalidated; #else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index caef2774b6950..63482f7397caa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include @@ -916,7 +915,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, bool userpage_invalidated = false; struct amdgpu_bo *bo = e->bo; - e->range = amdgpu_hmm_range_alloc(); + e->range = amdgpu_hmm_range_alloc(NULL); if (unlikely(!e->range)) return -ENOMEM; @@ -925,7 +924,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto out_free_user_pages; for (i = 0; i < bo->tbo.ttm->num_pages; i++) { - if (bo->tbo.ttm->pages[i] != hmm_pfn_to_page(e->range->hmm_pfns[i])) { + if (bo->tbo.ttm->pages[i] != + hmm_pfn_to_page(e->range->hmm_range.hmm_pfns[i])) { userpage_invalidated = true; break; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 478184576f0ce..018ca29fc8cd7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -602,7 +602,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_amdgpu_gem_userptr *args = data; struct amdgpu_fpriv *fpriv = filp->driver_priv; struct drm_gem_object *gobj; - struct hmm_range *range; + struct amdgpu_hmm_range *range; struct amdgpu_bo *bo; uint32_t handle; int r; @@ -644,7 +644,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED - range = amdgpu_hmm_range_alloc(); + range = amdgpu_hmm_range_alloc(NULL); if (unlikely(!range)) return -ENOMEM; r = amdgpu_ttm_tt_get_user_pages(bo, range); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 55b2359799ae4..e4a1858609991 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -843,12 +843,13 @@ const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, void *owner, - struct hmm_range *hmm_range) + struct amdgpu_hmm_range *range) { unsigned long end; unsigned long timeout; unsigned long *pfns; int r = 0; + struct hmm_range *hmm_range = &range->hmm_range; pfns = kvmalloc_array(npages, sizeof(*pfns), GFP_KERNEL); if (unlikely(!pfns)) { @@ -919,30 +920,38 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, return r; } -bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range) +bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range) { - if (!hmm_range) + if (!range) return false; - return !mmu_interval_read_retry(hmm_range->notifier, - hmm_range->notifier_seq); + return !mmu_interval_read_retry(range->hmm_range.notifier, + range->hmm_range.notifier_seq); } -struct hmm_range *amdgpu_hmm_range_alloc(void) +struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo) { - return kzalloc(sizeof(struct hmm_range), GFP_KERNEL); + struct amdgpu_hmm_range *range; + + range = kzalloc(sizeof(*range), GFP_KERNEL); + if (!range) + return NULL; + + range->bo = amdgpu_bo_ref(bo); + return range; } -void amdgpu_hmm_range_free(struct hmm_range *hmm_range) +void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range) { - if (!hmm_range) + if (!range) return; #ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT - kvfree(hmm_range->pfns); + kvfree(range->hmm_range.pfns); #else - kvfree(hmm_range->hmm_pfns); + kvfree(range->hmm_range.hmm_pfns); #endif - kfree(hmm_range); + amdgpu_bo_unref(&range->bo); + kfree(range); } #endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index 4ec014a918514..e73a6809e0d6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -82,16 +82,20 @@ static inline struct page *hmm_pfn_to_page(unsigned long hmm_pfn) return hmm_device_entry_to_page(&hmm_range, hmm_pfn); } #endif +struct amdgpu_hmm_range { + struct hmm_range hmm_range; + struct amdgpu_bo *bo; +}; int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, void *owner, - struct hmm_range *hmm_range); + struct amdgpu_hmm_range *range); #if defined(CONFIG_HMM_MIRROR) -bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range); -struct hmm_range *amdgpu_hmm_range_alloc(void); -void amdgpu_hmm_range_free(struct hmm_range *hmm_range); +bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range); +struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo); +void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range); int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr); void amdgpu_hmm_unregister(struct amdgpu_bo *bo); #else @@ -104,17 +108,17 @@ static inline int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) static inline void amdgpu_hmm_unregister(struct amdgpu_bo *bo) {} -static inline bool amdgpu_hmm_range_valid(struct hmm_range *hmm_range) +static inline bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range) { return false; } -static inline struct hmm_range *amdgpu_hmm_range_alloc(void) +static inline struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo) { return NULL; } -static inline void amdgpu_hmm_range_free(struct hmm_range *hmm_range) {} +static inline void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range) {} #endif #endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 205b70ebfb19f..7322c0336e0b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -782,7 +782,7 @@ struct amdgpu_ttm_tt { * that range is a valid memory and it is freed too. */ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, - struct hmm_range *range) + struct amdgpu_hmm_range *range) { struct ttm_tt *ttm = bo->tbo.ttm; struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm); @@ -917,12 +917,12 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, * that backs user memory and will ultimately be mapped into the device * address space. */ -void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct hmm_range *range) +void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range) { unsigned long i; for (i = 0; i < ttm->num_pages; ++i) - ttm->pages[i] = range ? hmm_pfn_to_page(range->hmm_pfns[i]) : NULL; + ttm->pages[i] = range ? hmm_pfn_to_page(range->hmm_range.hmm_pfns[i]) : NULL; } #else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 27dd8129cd565..dad6fe2528124 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -28,6 +28,7 @@ #include #include #include "amdgpu_vram_mgr.h" +#include "amdgpu_hmm.h" #define AMDGPU_PL_GDS (TTM_PL_PRIV + 0) #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1) @@ -200,7 +201,7 @@ uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, - struct hmm_range *range); + struct amdgpu_hmm_range *range); #else int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, struct hmm_range **range); @@ -208,7 +209,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, #else #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, - struct hmm_range *range) + struct amdgpu_hmm_range *range) { return -EPERM; } @@ -222,7 +223,7 @@ static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page #endif #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED -void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct hmm_range *range); +void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range); #else void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages); #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index d0bb8ecf3045e..ddc42699dd3cc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -21,7 +21,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h index 2eebf67f9c2ce..2b7fd442d29c6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.h @@ -31,7 +31,6 @@ #include #include #include -#include #include "kfd_priv.h" #include "kfd_svm.h" diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 5639a51212e05..5fe318b27a5f4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1702,7 +1702,7 @@ static int svm_range_validate_and_map(struct mm_struct *mm, start = map_start << PAGE_SHIFT; end = (map_last + 1) << PAGE_SHIFT; for (addr = start; !r && addr < end; ) { - struct hmm_range *hmm_range = NULL; + struct amdgpu_hmm_range *range = NULL; unsigned long map_start_vma; unsigned long map_last_vma; struct vm_area_struct *vma; @@ -1741,13 +1741,13 @@ static int svm_range_validate_and_map(struct mm_struct *mm, } WRITE_ONCE(p->svms.faulting_task, current); - hmm_range = amdgpu_hmm_range_alloc(); + range = amdgpu_hmm_range_alloc(NULL); r = amdgpu_hmm_range_get_pages(&prange->notifier, addr, npages, readonly, owner, - hmm_range); + range); WRITE_ONCE(p->svms.faulting_task, NULL); if (r) { - amdgpu_hmm_range_free(hmm_range); + amdgpu_hmm_range_free(range); pr_debug("failed %d to get svm range pages\n", r); } } else { @@ -1757,7 +1757,7 @@ static int svm_range_validate_and_map(struct mm_struct *mm, if (!r) { offset = (addr >> PAGE_SHIFT) - prange->start; r = svm_range_dma_map(prange, ctx->bitmap, offset, npages, - hmm_range->hmm_pfns); + range->hmm_range.hmm_pfns); if (r) pr_debug("failed %d to dma map range\n", r); } @@ -1768,12 +1768,12 @@ static int svm_range_validate_and_map(struct mm_struct *mm, * Overrride return value to TRY AGAIN only if prior returns * were successful */ - if (hmm_range && !amdgpu_hmm_range_valid(hmm_range) && !r) { + if (range && !amdgpu_hmm_range_valid(range) && !r) { pr_debug("hmm update the range, need validate again\n"); r = -EAGAIN; } /* Free the hmm range */ - amdgpu_hmm_range_free(hmm_range); + amdgpu_hmm_range_free(range); if (!r && !list_empty(&prange->child_list)) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h index 01c7a48779044..a63dfc95b602b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h @@ -31,7 +31,6 @@ #include #include #include -#include #include "amdgpu.h" #include "kfd_priv.h" From 5fc865f9b5381d138c026b8e8f5e19d182916545 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 14 Oct 2025 10:17:44 +0800 Subject: [PATCH 2373/2653] drm/amdkcl: update the functions to use amdgpu version of hmm on non-upstream code It's caused by the commit: 5e0ed4b "drm/amdgpu: update the functions to use amdgpu version of hmm" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 6 ++---- 5 files changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 741307be39678..34940ba10e2aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1183,7 +1183,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, goto unregister_out; } - ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages, NULL); + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); if (ret) { pr_err("%s: Failed to get user pages: %d\n", __func__, ret); goto free_out; @@ -3004,7 +3004,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, } /* Get updated user pages */ - ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages, NULL); + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); if (ret) { mem->user_pages[0] = NULL; pr_debug("%s: Failed to get user pages: %d\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 63482f7397caa..b75d56d6de338 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1059,7 +1059,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto error_free_pages; } - r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages, NULL); + r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages); if (r) { DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); kvfree(e->user_pages); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 018ca29fc8cd7..bbe0ee582a618 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -649,8 +649,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, return -ENOMEM; r = amdgpu_ttm_tt_get_user_pages(bo, range); #else - r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, - &range); + r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages); #endif if (r) { #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 7322c0336e0b6..a681be90a3033 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -835,8 +835,7 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, * This provides a wrapper around the get_user_pages() call to provide * device accessible pages that back user memory. */ -int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, - struct hmm_range **range) +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) { struct ttm_tt *ttm = bo->tbo.ttm; struct amdgpu_ttm_tt *gtt = (void *)ttm; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index dad6fe2528124..9c4282c7e32e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -203,8 +203,7 @@ uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct amdgpu_hmm_range *range); #else -int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, - struct hmm_range **range); +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages); #endif #else #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED @@ -214,8 +213,7 @@ static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, return -EPERM; } #else -static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, - struct hmm_range **range) +static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) { return -EPERM; } From b0edc709d2f9ae97322d1f9f24170e505f01e5d2 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 25 Sep 2025 14:31:54 +0530 Subject: [PATCH 2374/2653] drm/amdgpu/userqueue: validate userptrs for userqueues MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit userptrs could be changed by the user at any time and hence while locking all the bos before GPU start processing validate all the userptr bos. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 79 +++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index f32004e469bb1..9175e794a31c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -29,6 +29,7 @@ #include "amdgpu.h" #include "amdgpu_vm.h" #include "amdgpu_userq.h" +#include "amdgpu_hmm.h" #include "amdgpu_userq_fence.h" u32 amdgpu_userq_get_supported_ip_mask(struct amdgpu_device *adev) @@ -861,12 +862,21 @@ static int amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) { struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr); + bool invalidated = false, new_addition = false; + struct ttm_operation_ctx ctx = { true, false }; struct amdgpu_device *adev = uq_mgr->adev; + struct amdgpu_hmm_range *range; struct amdgpu_vm *vm = &fpriv->vm; + unsigned long key, tmp_key; struct amdgpu_bo_va *bo_va; + struct amdgpu_bo *bo; struct drm_exec exec; + struct xarray xa; int ret; + xa_init(&xa); + +retry_lock: drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); drm_exec_until_all_locked(&exec) { ret = amdgpu_vm_lock_pd(vm, &exec, 1); @@ -893,10 +903,72 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) goto unlock_all; } + if (invalidated) { + xa_for_each(&xa, tmp_key, range) { + bo = range->bo; + amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); + ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); + if (ret) + goto unlock_all; + + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, range); + + amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); + ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); + if (ret) + goto unlock_all; + } + invalidated = false; + } + ret = amdgpu_vm_handle_moved(adev, vm, NULL); if (ret) goto unlock_all; + key = 0; + /* Validate User Ptr BOs */ + list_for_each_entry(bo_va, &vm->done, base.vm_status) { + bo = bo_va->base.bo; + + if (!amdgpu_ttm_tt_is_userptr(bo->tbo.ttm)) + continue; + + range = xa_load(&xa, key); + if (range && range->bo != bo) { + xa_erase(&xa, key); + amdgpu_hmm_range_free(range); + range = NULL; + } + + if (!range) { + range = amdgpu_hmm_range_alloc(bo); + if (!range) { + ret = -ENOMEM; + goto unlock_all; + } + + xa_store(&xa, key, range, GFP_KERNEL); + new_addition = true; + } + key++; + } + + if (new_addition) { + drm_exec_fini(&exec); + xa_for_each(&xa, tmp_key, range) { + if (!range) + continue; + bo = range->bo; + ret = amdgpu_ttm_tt_get_user_pages(bo, range); + if (ret) + goto unlock_all; + } + + invalidated = true; + new_addition = false; + goto retry_lock; + } + ret = amdgpu_vm_update_pdes(adev, vm, false); if (ret) goto unlock_all; @@ -916,6 +988,13 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) unlock_all: drm_exec_fini(&exec); + xa_for_each(&xa, tmp_key, range) { + if (!range) + continue; + bo = range->bo; + amdgpu_hmm_range_free(range); + } + xa_destroy(&xa); return ret; } From 2184789178c3d08f75822b932f284db2b8aa2928 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Tue, 14 Oct 2025 11:12:56 +0800 Subject: [PATCH 2375/2653] drm/amdkcl: wrap code under macro define HAVE_AMDKCL_HMM_MIRROR_ENABLED It's caused by the commit: 7fa2cac7 "drm/amdgpu/userqueue: validate userptrs for userqueues" Signed-off-by: Chengjun Yao Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 9175e794a31c0..d185f1751c6ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -862,21 +862,28 @@ static int amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) { struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr); + struct amdgpu_device *adev = uq_mgr->adev; + struct amdgpu_vm *vm = &fpriv->vm; + struct amdgpu_bo_va *bo_va; + struct drm_exec exec; + int ret; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool invalidated = false, new_addition = false; struct ttm_operation_ctx ctx = { true, false }; - struct amdgpu_device *adev = uq_mgr->adev; struct amdgpu_hmm_range *range; - struct amdgpu_vm *vm = &fpriv->vm; unsigned long key, tmp_key; - struct amdgpu_bo_va *bo_va; struct amdgpu_bo *bo; - struct drm_exec exec; struct xarray xa; - int ret; xa_init(&xa); retry_lock: +#else + dev_warn_once(adev->dev, "HMM is not functional; falling back to legacy path. " + "Legacy path is untested and may be unstable. " + "Please enable HMM or refer to documentation for supported kernels.\n"); + WARN_ON_ONCE(1); +#endif drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); drm_exec_until_all_locked(&exec) { ret = amdgpu_vm_lock_pd(vm, &exec, 1); @@ -903,6 +910,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) goto unlock_all; } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (invalidated) { xa_for_each(&xa, tmp_key, range) { bo = range->bo; @@ -920,11 +928,13 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) } invalidated = false; } +#endif ret = amdgpu_vm_handle_moved(adev, vm, NULL); if (ret) goto unlock_all; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED key = 0; /* Validate User Ptr BOs */ list_for_each_entry(bo_va, &vm->done, base.vm_status) { @@ -968,6 +978,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) new_addition = false; goto retry_lock; } +#endif ret = amdgpu_vm_update_pdes(adev, vm, false); if (ret) @@ -988,6 +999,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) unlock_all: drm_exec_fini(&exec); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED xa_for_each(&xa, tmp_key, range) { if (!range) continue; @@ -995,6 +1007,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) amdgpu_hmm_range_free(range); } xa_destroy(&xa); +#endif return ret; } From 2375c77c47d5c62c9fb660cb54e2fc1dca8aa9db Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 14 Oct 2025 13:11:02 +0530 Subject: [PATCH 2376/2653] drm/amdgpu: add the kernel docs for alloc/free/valid range MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add kernel docs for the functions related to hmm_range. Documents added for functions: amdgpu_hmm_range_valid amdgpu_hmm_range_alloc amdgpu_hmm_range_free Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 33 +++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index e4a1858609991..9076b8a74eed3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -920,6 +920,19 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, return r; } +/** + * amdgpu_hmm_range_valid - check if an HMM range is still valid + * @range: pointer to the &struct amdgpu_hmm_range to validate + * + * Determines whether the given HMM range @range is still valid by + * checking for invalidations via the MMU notifier sequence. This is + * typically used to verify that the range has not been invalidated + * by concurrent address space updates before it is accessed. + * + * Return: + * * true if @range is valid and can be used safely + * * false if @range is NULL or has been invalidated + */ bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range) { if (!range) @@ -929,6 +942,17 @@ bool amdgpu_hmm_range_valid(struct amdgpu_hmm_range *range) range->hmm_range.notifier_seq); } +/** + * amdgpu_hmm_range_alloc - allocate and initialize an AMDGPU HMM range + * @bo: optional buffer object to associate with this HMM range + * + * Allocates memory for amdgpu_hmm_range and associates it with the @bo passed. + * The reference count of the @bo is incremented. + * + * Return: + * Pointer to a newly allocated struct amdgpu_hmm_range on success, + * or NULL if memory allocation fails. + */ struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo) { struct amdgpu_hmm_range *range; @@ -941,6 +965,15 @@ struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo *bo) return range; } +/** + * amdgpu_hmm_range_free - release an AMDGPU HMM range + * @range: pointer to the range object to free + * + * Releases all resources held by @range, including the associated + * hmm_pfns and the dropping reference of associated bo if any. + * + * Return: void + */ void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range) { if (!range) From f4e85ae8e5e07048ef25c33d7b9d7823cf7f3d76 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 21 Oct 2025 15:14:06 +0530 Subject: [PATCH 2377/2653] drm/amdgpu: null check for hmm_pfns ptr before freeing it Due to low memory or when num of pages is too big to be accomodated, allocation could fail for pfn's. Chekc hmm_pfns for NULL before calling the kvfree for the it. Signed-off-by: Sunil Khatri Acked-by: Arunpravin Paneer Selvam --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 9076b8a74eed3..1a9101a3d68bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -980,9 +980,11 @@ void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range) return; #ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT - kvfree(range->hmm_range.pfns); + if (range->hmm_range.pfns) + kvfree(range->hmm_range.pfns); #else - kvfree(range->hmm_range.hmm_pfns); + if (range->hmm_range.hmm_pfns) + kvfree(range->hmm_range.hmm_pfns); #endif amdgpu_bo_unref(&range->bo); kfree(range); From e54dee3501146c716be311bec6d5ffe9fe8acf8e Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Tue, 21 Oct 2025 13:52:58 +0800 Subject: [PATCH 2378/2653] drm/amd/display: Rename dml2 to dml2_0 folder [Why] dml2 folder contains all logic for all versions of DML2 This is currently DML2.0 and DML2.1. Rename dml2 to dml2_0 folder to reflect this better (dml2_0 for DML2.0). [How] Rename dml2 to dml2_0 folder and update dml2 references to use dml2_0 folder. Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: waynelin Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/Makefile | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- .../gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- .../gpu/drm/amd/display/dc/core/dc_state.c | 4 +- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- drivers/gpu/drm/amd/display/dc/dml2/Makefile | 179 ------------------ .../gpu/drm/amd/display/dc/dml2_0/Makefile | 178 +++++++++++++++++ .../display/dc/{dml2 => dml2_0}/cmntypes.h | 18 +- .../dc/{dml2 => dml2_0}/display_mode_core.c | 2 + .../dc/{dml2 => dml2_0}/display_mode_core.h | 0 .../display_mode_core_structs.h | 3 +- .../display_mode_lib_defines.h | 2 +- .../dc/{dml2 => dml2_0}/display_mode_util.c | 0 .../dc/{dml2 => dml2_0}/display_mode_util.h | 2 - .../dml21/dml21_translation_helper.c | 0 .../dml21/dml21_translation_helper.h | 0 .../dc/{dml2 => dml2_0}/dml21/dml21_utils.c | 0 .../dc/{dml2 => dml2_0}/dml21/dml21_utils.h | 0 .../dc/{dml2 => dml2_0}/dml21/dml21_wrapper.c | 4 +- .../dc/{dml2 => dml2_0}/dml21/dml21_wrapper.h | 0 .../dml21/inc/bounding_boxes/dcn4_soc_bb.h | 1 - .../dml21/inc/dml2_external_lib_deps.h | 0 .../dc/{dml2 => dml2_0}/dml21/inc/dml_top.h | 0 .../dml21/inc/dml_top_dchub_registers.h | 0 .../dml21/inc/dml_top_display_cfg_types.h | 0 .../dml21/inc/dml_top_policy_types.h | 0 .../dml21/inc/dml_top_soc_parameter_types.h | 0 .../dml21/inc/dml_top_types.h | 0 .../dml21/src/dml2_core/dml2_core_dcn4.c | 0 .../dml21/src/dml2_core/dml2_core_dcn4.h | 0 .../src/dml2_core/dml2_core_dcn4_calcs.c | 2 + .../src/dml2_core/dml2_core_dcn4_calcs.h | 0 .../dml21/src/dml2_core/dml2_core_factory.c | 0 .../dml21/src/dml2_core/dml2_core_factory.h | 0 .../src/dml2_core/dml2_core_shared_types.h | 0 .../dml21/src/dml2_core/dml2_core_utils.c | 0 .../dml21/src/dml2_core/dml2_core_utils.h | 0 .../dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c | 0 .../dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h | 0 .../dml21/src/dml2_dpmm/dml2_dpmm_factory.c | 0 .../dml21/src/dml2_dpmm/dml2_dpmm_factory.h | 0 .../dml21/src/dml2_mcg/dml2_mcg_dcn4.c | 0 .../dml21/src/dml2_mcg/dml2_mcg_dcn4.h | 2 +- .../dml21/src/dml2_mcg/dml2_mcg_factory.c | 0 .../dml21/src/dml2_mcg/dml2_mcg_factory.h | 0 .../dml21/src/dml2_pmo/dml2_pmo_dcn3.c | 0 .../dml21/src/dml2_pmo/dml2_pmo_dcn3.h | 0 .../dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 0 .../dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h | 0 .../dml21/src/dml2_pmo/dml2_pmo_factory.c | 0 .../dml21/src/dml2_pmo/dml2_pmo_factory.h | 2 +- .../lib_float_math.c | 0 .../lib_float_math.h | 0 .../dml21/src/dml2_top/dml2_top_interfaces.c | 0 .../dml21/src/dml2_top/dml2_top_legacy.c | 0 .../dml21/src/dml2_top/dml2_top_legacy.h | 0 .../dml21/src/dml2_top/dml2_top_soc15.c | 0 .../dml21/src/dml2_top/dml2_top_soc15.h | 0 .../dml21/src/inc/dml2_debug.h | 0 .../src/inc/dml2_internal_shared_types.h | 0 .../{dml2 => dml2_0}/dml2_dc_resource_mgmt.c | 0 .../{dml2 => dml2_0}/dml2_dc_resource_mgmt.h | 0 .../dc/{dml2 => dml2_0}/dml2_dc_types.h | 0 .../dc/{dml2 => dml2_0}/dml2_internal_types.h | 2 +- .../dc/{dml2 => dml2_0}/dml2_mall_phantom.c | 1 + .../dc/{dml2 => dml2_0}/dml2_mall_phantom.h | 0 .../display/dc/{dml2 => dml2_0}/dml2_policy.c | 0 .../display/dc/{dml2 => dml2_0}/dml2_policy.h | 0 .../dml2_translation_helper.c | 3 + .../dml2_translation_helper.h | 0 .../display/dc/{dml2 => dml2_0}/dml2_utils.c | 0 .../display/dc/{dml2 => dml2_0}/dml2_utils.h | 0 .../dc/{dml2 => dml2_0}/dml2_wrapper.c | 0 .../dc/{dml2 => dml2_0}/dml2_wrapper.h | 0 .../display/dc/{dml2 => dml2_0}/dml_assert.h | 0 .../dc/{dml2 => dml2_0}/dml_depedencies.h | 1 + .../dml_display_rq_dlg_calc.c | 0 .../dml_display_rq_dlg_calc.h | 0 .../display/dc/{dml2 => dml2_0}/dml_logging.h | 1 + .../amd/display/dc/hubp/dcn401/dcn401_hubp.h | 2 +- .../gpu/drm/amd/display/dc/inc/core_types.h | 4 +- drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 4 +- .../gpu/drm/amd/display/dc/inc/hw/mem_input.h | 2 +- .../dc/resource/dcn32/dcn32_resource.c | 2 +- .../dc/resource/dcn35/dcn35_resource.c | 2 +- .../dc/resource/dcn351/dcn351_resource.c | 2 +- .../dc/resource/dcn36/dcn36_resource.c | 2 +- .../dc/resource/dcn401/dcn401_resource.c | 2 +- .../dcn401/dcn401_soc_and_ip_translator.h | 2 +- 89 files changed, 221 insertions(+), 218 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/dml2/Makefile create mode 100644 drivers/gpu/drm/amd/display/dc/dml2_0/Makefile rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/cmntypes.h (93%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/display_mode_core.c (99%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/display_mode_core.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/display_mode_core_structs.h (99%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/display_mode_lib_defines.h (95%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/display_mode_util.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/display_mode_util.h (99%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/dml21_translation_helper.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/dml21_translation_helper.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/dml21_utils.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/dml21_utils.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/dml21_wrapper.c (99%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/dml21_wrapper.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/inc/bounding_boxes/dcn4_soc_bb.h (99%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/inc/dml2_external_lib_deps.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/inc/dml_top.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/inc/dml_top_dchub_registers.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/inc/dml_top_display_cfg_types.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/inc/dml_top_policy_types.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/inc/dml_top_soc_parameter_types.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/inc/dml_top_types.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_core/dml2_core_dcn4.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_core/dml2_core_dcn4.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_core/dml2_core_dcn4_calcs.c (99%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_core/dml2_core_dcn4_calcs.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_core/dml2_core_factory.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_core/dml2_core_factory.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_core/dml2_core_shared_types.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_core/dml2_core_utils.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_core/dml2_core_utils.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_dpmm/dml2_dpmm_factory.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_dpmm/dml2_dpmm_factory.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_mcg/dml2_mcg_dcn4.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_mcg/dml2_mcg_dcn4.h (97%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_mcg/dml2_mcg_factory.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_mcg/dml2_mcg_factory.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_pmo/dml2_pmo_dcn3.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_pmo/dml2_pmo_dcn3.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_pmo/dml2_pmo_factory.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_pmo/dml2_pmo_factory.h (97%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_standalone_libraries/lib_float_math.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_standalone_libraries/lib_float_math.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_top/dml2_top_interfaces.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_top/dml2_top_legacy.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_top/dml2_top_legacy.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_top/dml2_top_soc15.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/dml2_top/dml2_top_soc15.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/inc/dml2_debug.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml21/src/inc/dml2_internal_shared_types.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml2_dc_resource_mgmt.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml2_dc_resource_mgmt.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml2_dc_types.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml2_internal_types.h (99%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml2_mall_phantom.c (99%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml2_mall_phantom.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml2_policy.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml2_policy.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml2_translation_helper.c (99%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml2_translation_helper.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml2_utils.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml2_utils.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml2_wrapper.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml2_wrapper.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml_assert.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml_depedencies.h (99%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml_display_rq_dlg_calc.c (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml_display_rq_dlg_calc.h (100%) rename drivers/gpu/drm/amd/display/dc/{dml2 => dml2_0}/dml_logging.h (99%) diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index dc943abd6dba3..7277ed21552f3 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -36,7 +36,7 @@ DC_LIBS += dcn30 DC_LIBS += dcn301 DC_LIBS += dcn31 DC_LIBS += dml -DC_LIBS += dml2 +DC_LIBS += dml2_0 DC_LIBS += soc_and_ip_translator endif diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 0d7f0b416a745..e168e2494d9a1 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -83,7 +83,7 @@ #include "hw_sequencer_private.h" #if defined(CONFIG_DRM_AMD_DC_FP) -#include "dml2/dml2_internal_types.h" +#include "dml2_0/dml2_internal_types.h" #include "soc_and_ip_translator.h" #endif diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index c59173a4fd751..89fe72820f6a1 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -95,7 +95,7 @@ #define DC_LOGGER \ dc->ctx->logger #define DC_LOGGER_INIT(logger) -#include "dml2/dml2_wrapper.h" +#include "dml2_0/dml2_wrapper.h" #define UNABLE_TO_SPLIT -1 diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c index c61300a7cb1c9..2de8ef4a58ec6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c @@ -35,8 +35,8 @@ #include "link_enc_cfg.h" #if defined(CONFIG_DRM_AMD_DC_FP) -#include "dml2/dml2_wrapper.h" -#include "dml2/dml2_internal_types.h" +#include "dml2_0/dml2_wrapper.h" +#include "dml2_0/dml2_internal_types.h" #endif #define DC_LOGGER \ diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e02f3c128e113..b59fb0795f136 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -42,7 +42,7 @@ #include "inc/hw/dmcu.h" #include "dml/display_mode_lib.h" -#include "dml2/dml2_wrapper.h" +#include "dml2_0/dml2_wrapper.h" #include "dmub/inc/dmub_cmd.h" diff --git a/drivers/gpu/drm/amd/display/dc/dml2/Makefile b/drivers/gpu/drm/amd/display/dc/dml2/Makefile deleted file mode 100644 index 66177fcea4308..0000000000000 --- a/drivers/gpu/drm/amd/display/dc/dml2/Makefile +++ /dev/null @@ -1,179 +0,0 @@ -# SPDX-License-Identifier: MIT */ -# -# Copyright 2023 Advanced Micro Devices, Inc. -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -# OTHER DEALINGS IN THE SOFTWARE. -# -# Authors: AMD -# -# Makefile for dml2. - -ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT -dml2_ccflags := $(CC_FLAGS_FPU) -dml2_rcflags := $(CC_FLAGS_NO_FPU) -else -ifdef CONFIG_X86 -dml2_ccflags-$(CONFIG_CC_IS_GCC) := -mhard-float -dml2_ccflags := $(dml2_ccflags-y) -msse -endif - -ifdef CONFIG_PPC64 -dml2_ccflags := -mhard-float -maltivec -endif - -ifdef CONFIG_ARM64 -dml2_rcflags := -mgeneral-regs-only -endif - -ifdef CONFIG_LOONGARCH -dml2_ccflags := -mfpu=64 -dml2_rcflags := -msoft-float -endif - -ifdef CONFIG_CC_IS_GCC -ifeq ($(call cc-ifversion, -lt, 0701, y), y) -IS_OLD_GCC = 1 -endif -endif - -ifdef CONFIG_X86 -ifdef IS_OLD_GCC -# Stack alignment mismatch, proceed with caution. -# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 -# (8B stack alignment). -dml2_ccflags += -mpreferred-stack-boundary=4 -else -dml2_ccflags += -msse2 -endif -endif - -endif #CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT - -ifneq ($(CONFIG_FRAME_WARN),0) - ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) - ifeq ($(CONFIG_CC_IS_CLANG)$(CONFIG_COMPILE_TEST),yy) - frame_warn_limit := 4096 - else - frame_warn_limit := 3072 - endif - else - frame_warn_limit := 2056 - endif - - ifeq ($(call test-lt, $(CONFIG_FRAME_WARN), $(frame_warn_limit)),y) - frame_warn_flag := -Wframe-larger-than=$(frame_warn_limit) - endif -endif - -subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2 -subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_core -subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_mcg/ -subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_dpmm/ -subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_pmo/ -subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/dml2_standalone_libraries/ -subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/src/inc -subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/inc -subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2/dml21/ - -CFLAGS_$(AMDDALPATH)/dc/dml2/display_mode_core.o := $(dml2_ccflags) $(frame_warn_flag) -CFLAGS_$(AMDDALPATH)/dc/dml2/display_mode_util.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_wrapper.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_utils.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_policy.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_translation_helper.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_mall_phantom.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml_display_rq_dlg_calc.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml2_dc_resource_mgmt.o := $(dml2_ccflags) - -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/display_mode_core.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/display_mode_util.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml2_wrapper.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml2_utils.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml2_policy.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml2_translation_helper.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml2_mall_phantom.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml_display_rq_dlg_calc.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml2_dc_resource_mgmt.o := $(dml2_rcflags) - -DML2 = display_mode_core.o display_mode_util.o dml2_wrapper.o \ - dml2_utils.o dml2_policy.o dml2_translation_helper.o dml2_dc_resource_mgmt.o dml2_mall_phantom.o \ - dml_display_rq_dlg_calc.o - -AMD_DAL_DML2 = $(addprefix $(AMDDALPATH)/dc/dml2/,$(DML2)) - -AMD_DISPLAY_FILES += $(AMD_DAL_DML2) - -CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_ccflags) $(frame_warn_flag) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_ccflags) $(frame_warn_flag) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml21_wrapper.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/dml21_translation_helper.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/dml21_utils.o := $(dml2_ccflags) - -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml21_wrapper.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/dml21_translation_helper.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/dml21_utils.o := $(dml2_rcflags) - -DML21 := src/dml2_top/dml2_top_interfaces.o -DML21 += src/dml2_top/dml2_top_soc15.o -DML21 += src/dml2_core/dml2_core_dcn4.o -DML21 += src/dml2_core/dml2_core_utils.o -DML21 += src/dml2_core/dml2_core_factory.o -DML21 += src/dml2_core/dml2_core_dcn4_calcs.o -DML21 += src/dml2_dpmm/dml2_dpmm_dcn4.o -DML21 += src/dml2_dpmm/dml2_dpmm_factory.o -DML21 += src/dml2_mcg/dml2_mcg_dcn4.o -DML21 += src/dml2_mcg/dml2_mcg_factory.o -DML21 += src/dml2_pmo/dml2_pmo_dcn3.o -DML21 += src/dml2_pmo/dml2_pmo_factory.o -DML21 += src/dml2_pmo/dml2_pmo_dcn4_fams2.o -DML21 += src/dml2_standalone_libraries/lib_float_math.o -DML21 += dml21_translation_helper.o -DML21 += dml21_wrapper.o -DML21 += dml21_utils.o - -AMD_DAL_DML21 = $(addprefix $(AMDDALPATH)/dc/dml2/dml21/,$(DML21)) - -AMD_DISPLAY_FILES += $(AMD_DAL_DML21) - diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile b/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile new file mode 100644 index 0000000000000..0433756980d7b --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: MIT */ +# +# Copyright 2023 Advanced Micro Devices, Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +# OTHER DEALINGS IN THE SOFTWARE. +# +# Authors: AMD +# +# Makefile for dml2. + +ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT +dml2_ccflags := $(CC_FLAGS_FPU) +dml2_rcflags := $(CC_FLAGS_NO_FPU) +else +ifdef CONFIG_X86 +dml2_ccflags-$(CONFIG_CC_IS_GCC) := -mhard-float +dml2_ccflags := $(dml2_ccflags-y) -msse +endif + +ifdef CONFIG_PPC64 +dml2_ccflags := -mhard-float -maltivec +endif + +ifdef CONFIG_ARM64 +dml2_rcflags := -mgeneral-regs-only +endif + +ifdef CONFIG_LOONGARCH +dml2_ccflags := -mfpu=64 +dml2_rcflags := -msoft-float +endif + +ifdef CONFIG_CC_IS_GCC +ifeq ($(call cc-ifversion, -lt, 0701, y), y) +IS_OLD_GCC = 1 +endif +endif + +ifdef CONFIG_X86 +ifdef IS_OLD_GCC +# Stack alignment mismatch, proceed with caution. +# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 +# (8B stack alignment). +dml2_ccflags += -mpreferred-stack-boundary=4 +else +dml2_ccflags += -msse2 +endif +endif + +endif #CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT + +ifneq ($(CONFIG_FRAME_WARN),0) + ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) + ifeq ($(CONFIG_CC_IS_CLANG)$(CONFIG_COMPILE_TEST),yy) + frame_warn_limit := 4096 + else + frame_warn_limit := 3072 + endif + else + frame_warn_limit := 2056 + endif + + ifeq ($(call test-lt, $(CONFIG_FRAME_WARN), $(frame_warn_limit)),y) + frame_warn_flag := -Wframe-larger-than=$(frame_warn_limit) + endif +endif + +subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0 +subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_core +subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_mcg/ +subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_dpmm/ +subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_pmo/ +subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/dml2_standalone_libraries/ +subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/src/inc +subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/inc +subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/ + +CFLAGS_$(AMDDALPATH)/dc/dml2_0/display_mode_core.o := $(dml2_ccflags) $(frame_warn_flag) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/display_mode_util.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_utils.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_policy.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_translation_helper.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_mall_phantom.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml_display_rq_dlg_calc.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_dc_resource_mgmt.o := $(dml2_ccflags) + +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/display_mode_core.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/display_mode_util.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_utils.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_policy.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_translation_helper.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_mall_phantom.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml_display_rq_dlg_calc.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_dc_resource_mgmt.o := $(dml2_rcflags) + +DML2 = display_mode_core.o display_mode_util.o dml2_wrapper.o \ + dml2_utils.o dml2_policy.o dml2_translation_helper.o dml2_dc_resource_mgmt.o dml2_mall_phantom.o \ + dml_display_rq_dlg_calc.o + +AMD_DAL_DML2 = $(addprefix $(AMDDALPATH)/dc/dml2_0/,$(DML2)) + +AMD_DISPLAY_FILES += $(AMD_DAL_DML2) + +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_ccflags) $(frame_warn_flag) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_ccflags) $(frame_warn_flag) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml21_wrapper.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_translation_helper.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_utils.o := $(dml2_ccflags) + +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml21_wrapper.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_translation_helper.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_utils.o := $(dml2_rcflags) + +DML21 := src/dml2_top/dml2_top_interfaces.o +DML21 += src/dml2_top/dml2_top_soc15.o +DML21 += src/dml2_core/dml2_core_dcn4.o +DML21 += src/dml2_core/dml2_core_utils.o +DML21 += src/dml2_core/dml2_core_factory.o +DML21 += src/dml2_core/dml2_core_dcn4_calcs.o +DML21 += src/dml2_dpmm/dml2_dpmm_dcn4.o +DML21 += src/dml2_dpmm/dml2_dpmm_factory.o +DML21 += src/dml2_mcg/dml2_mcg_dcn4.o +DML21 += src/dml2_mcg/dml2_mcg_factory.o +DML21 += src/dml2_pmo/dml2_pmo_dcn3.o +DML21 += src/dml2_pmo/dml2_pmo_factory.o +DML21 += src/dml2_pmo/dml2_pmo_dcn4_fams2.o +DML21 += src/dml2_standalone_libraries/lib_float_math.o +DML21 += dml21_translation_helper.o +DML21 += dml21_wrapper.o +DML21 += dml21_utils.o + +AMD_DAL_DML21 = $(addprefix $(AMDDALPATH)/dc/dml2_0/dml21/,$(DML21)) + +AMD_DISPLAY_FILES += $(AMD_DAL_DML21) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/cmntypes.h b/drivers/gpu/drm/amd/display/dc/dml2_0/cmntypes.h similarity index 93% rename from drivers/gpu/drm/amd/display/dc/dml2/cmntypes.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/cmntypes.h index e450445bc05d0..b954c9648fbe4 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/cmntypes.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/cmntypes.h @@ -53,17 +53,17 @@ typedef const void *const_pvoid; typedef const char *const_pchar; typedef struct rgba_struct { - uint8 a; - uint8 r; - uint8 g; - uint8 b; + uint8 a; + uint8 r; + uint8 g; + uint8 b; } rgba_t; typedef struct { - uint8 blue; - uint8 green; - uint8 red; - uint8 alpha; + uint8 blue; + uint8 green; + uint8 red; + uint8 alpha; } gen_color_t; typedef union { @@ -87,7 +87,7 @@ typedef union { } uintfloat64; #ifndef UNREFERENCED_PARAMETER -#define UNREFERENCED_PARAMETER(x) x = x +#define UNREFERENCED_PARAMETER(x) (x = x) #endif #endif diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c similarity index 99% rename from drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c index 4b9b2e84d3811..c468f492b8768 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c @@ -10205,6 +10205,7 @@ dml_bool_t dml_get_is_phantom_pipe(struct display_mode_lib_st *mode_lib, dml_uin return (mode_lib->ms.cache_display_cfg.plane.UseMALLForPStateChange[plane_idx] == dml_use_mall_pstate_change_phantom_pipe); } + #define dml_get_per_surface_var_func(variable, type, interval_var) type dml_get_##variable(struct display_mode_lib_st *mode_lib, dml_uint_t surface_idx) \ { \ dml_uint_t plane_idx; \ @@ -10333,3 +10334,4 @@ dml_get_per_surface_var_func(bigk_fragment_size, dml_uint_t, mode_lib->mp.BIGK_F dml_get_per_surface_var_func(dpte_bytes_per_row, dml_uint_t, mode_lib->mp.PixelPTEBytesPerRow); dml_get_per_surface_var_func(meta_bytes_per_row, dml_uint_t, mode_lib->mp.MetaRowByte); dml_get_per_surface_var_func(det_buffer_size_kbytes, dml_uint_t, mode_lib->ms.DETBufferSizeInKByte); + diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.h b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core_structs.h similarity index 99% rename from drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core_structs.h index d57717b023ebf..3b1d92e7697fe 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core_structs.h @@ -274,7 +274,6 @@ enum dml_clk_cfg_policy { dml_use_state_freq = 2 }; - struct soc_state_bounding_box_st { dml_float_t socclk_mhz; dml_float_t dscclk_mhz; @@ -1894,7 +1893,7 @@ struct display_mode_lib_scratch_st { struct CalculatePrefetchSchedule_params_st CalculatePrefetchSchedule_params; }; -/// @brief Represent the overall soc/ip environment. It contains data structure represent the soc/ip characteristic and also structures that hold calculation output +/// @brief Represent the overall soc/ip enviroment. It contains data structure represent the soc/ip characteristic and also structures that hold calculation output struct display_mode_lib_st { dml_uint_t project; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_lib_defines.h b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_lib_defines.h similarity index 95% rename from drivers/gpu/drm/amd/display/dc/dml2/display_mode_lib_defines.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_lib_defines.h index 14d3895252967..e574c81edf5e5 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_lib_defines.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_lib_defines.h @@ -52,7 +52,7 @@ #define __DML_VBA_DEBUG__ #define __DML_VBA_ENABLE_INLINE_CHECK_ 0 #define __DML_VBA_MIN_VSTARTUP__ 9 //config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); /* Populate stream, plane mappings and other fields in display config. */ - DC_FP_START(); result = dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); - DC_FP_END(); if (!result) return false; @@ -281,9 +279,9 @@ static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *co dml_ctx->config.svp_pstate.callbacks.release_phantom_streams_and_planes(in_dc, context); mode_support->dml2_instance = dml_init->dml2_instance; - DC_FP_START(); dml21_map_dc_state_into_dml_display_cfg(in_dc, context, dml_ctx); dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.programming; + DC_FP_START(); is_supported = dml2_check_mode_supported(mode_support); DC_FP_END(); if (!is_supported) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/dcn4_soc_bb.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn4_soc_bb.h similarity index 99% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/dcn4_soc_bb.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn4_soc_bb.h index 793e1c038efd0..16a4f97bca4eb 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/dcn4_soc_bb.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn4_soc_bb.h @@ -2,7 +2,6 @@ // // Copyright 2024 Advanced Micro Devices, Inc. - #ifndef __DML_DML_DCN4_SOC_BB__ #define __DML_DML_DCN4_SOC_BB__ diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml2_external_lib_deps.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml2_external_lib_deps.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml2_external_lib_deps.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml2_external_lib_deps.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_dchub_registers.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_dchub_registers.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_policy_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_policy_types.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_policy_types.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_policy_types.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c similarity index 99% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index f16792f79befa..f809c4073b430 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -1303,6 +1303,7 @@ static double TruncToValidBPP( MinDSCBPP = 8; MaxDSCBPP = 16; } else { + if (Output == dml2_hdmi || Output == dml2_hdmifrl) { NonDSCBPP0 = 24; NonDSCBPP1 = 24; @@ -1320,6 +1321,7 @@ static double TruncToValidBPP( MaxDSCBPP = 16; } } + if (Output == dml2_dp2p0) { MaxLinkBPP = LinkBitRate * Lanes / PixelClock * 128.0 / 132.0 * 383.0 / 384.0 * 65536.0 / 65540.0; } else if (DSCEnable && Output == dml2_dp) { diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h similarity index 97% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h index 02da6f45cbf75..f54fde8fba906 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h @@ -10,4 +10,4 @@ bool mcg_dcn4_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out); bool mcg_dcn4_unit_test(void); -#endif +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.h similarity index 97% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.h index 7218de1824cca..b90f6263cd85d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.h @@ -10,4 +10,4 @@ bool dml2_pmo_create(enum dml2_project_id project_id, struct dml2_pmo_instance *out); -#endif +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_interfaces.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_legacy.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_legacy.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_legacy.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_legacy.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/dml2_debug.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_debug.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/dml2_debug.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_debug.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_types.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_types.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_types.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h similarity index 99% rename from drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h index 140ec01545db8..55b3e3ca54f79 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_internal_types.h @@ -23,7 +23,7 @@ * Authors: AMD * */ - + #ifndef __DML2_INTERNAL_TYPES_H__ #define __DML2_INTERNAL_TYPES_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c similarity index 99% rename from drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c index c59f825cfae96..66040c877d68a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c @@ -24,6 +24,7 @@ * */ + #include "dml2_dc_types.h" #include "dml2_internal_types.h" #include "dml2_utils.h" diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml2_mall_phantom.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c similarity index 99% rename from drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c index 3b866e876bf4d..d834cb595afab 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c @@ -301,6 +301,7 @@ void dml2_init_socbb_params(struct dml2_context *dml2, const struct dc *in_dc, s out->pct_ideal_dram_bw_after_urgent_pixel_only = 65.0; break; + case dml_project_dcn401: out->pct_ideal_fabric_bw_after_urgent = 76; //67; out->max_avg_sdp_bw_use_normal_percent = 75; //80; @@ -424,6 +425,8 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc, p->in_states->state_array[1].dcfclk_mhz = 1434.0; p->in_states->state_array[1].dram_speed_mts = 1000 * transactions_per_mem_clock; break; + + case dml_project_dcn401: p->in_states->num_states = 2; transactions_per_mem_clock = 16; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml_assert.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml_assert.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml_assert.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml_assert.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml_depedencies.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml_depedencies.h similarity index 99% rename from drivers/gpu/drm/amd/display/dc/dml2/dml_depedencies.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml_depedencies.h index f7d30b47beff5..d459f93cf40b2 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml_depedencies.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml_depedencies.h @@ -31,3 +31,4 @@ */ #include "os_types.h" #include "cmntypes.h" + diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.c rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/dml2/dml_display_rq_dlg_calc.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml_logging.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml_logging.h similarity index 99% rename from drivers/gpu/drm/amd/display/dc/dml2/dml_logging.h rename to drivers/gpu/drm/amd/display/dc/dml2_0/dml_logging.h index 2a2f84e07ca88..7fadbe6d7af4e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml_logging.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml_logging.h @@ -23,6 +23,7 @@ * Authors: AMD * */ + #ifndef __DML_LOGGING_H__ #define __DML_LOGGING_H__ diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h index fdabbeec8ffa3..4570b8016de5a 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h @@ -31,7 +31,7 @@ #include "dcn30/dcn30_hubp.h" #include "dcn31/dcn31_hubp.h" #include "dcn32/dcn32_hubp.h" -#include "dml2/dml21/inc/dml_top_dchub_registers.h" +#include "dml2_0/dml21/inc/dml_top_dchub_registers.h" #define HUBP_3DLUT_FL_REG_LIST_DCN401(inst)\ SRI_ARR_US(_3DLUT_FL_CONFIG, HUBP, inst),\ diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index a74d753dce819..36688733e208e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -58,8 +58,8 @@ #include "transform.h" #include "dpp.h" -#include "dml2/dml21/inc/dml_top_dchub_registers.h" -#include "dml2/dml21/inc/dml_top_types.h" +#include "dml2_0/dml21/inc/dml_top_dchub_registers.h" +#include "dml2_0/dml21/inc/dml_top_types.h" struct resource_pool; struct dc_state; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index 90bf86e83fb13..a79019365af8c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -41,8 +41,8 @@ #include "mem_input.h" #include "cursor_reg_cache.h" -#include "dml2/dml21/inc/dml_top_dchub_registers.h" -#include "dml2/dml21/inc/dml_top_types.h" +#include "dml2_0/dml21/inc/dml_top_dchub_registers.h" +#include "dml2_0/dml21/inc/dml_top_types.h" #define OPP_ID_INVALID 0xf #define MAX_TTU 0xffffff diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 42fbc70f7056a..d468bc85566a1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -29,7 +29,7 @@ #include "include/grph_object_id.h" #include "dml/display_mode_structs.h" -#include "dml2/dml21/inc/dml_top_dchub_registers.h" +#include "dml2_0/dml21/inc/dml_top_dchub_registers.h" struct dchub_init_data; struct cstate_pstate_watermarks_st { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index fcf69a020c485..81e64e17d0cb9 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -92,7 +92,7 @@ #include "dc_state_priv.h" -#include "dml2/dml2_wrapper.h" +#include "dml2_0/dml2_wrapper.h" #define DC_LOGGER_INIT(logger) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c index c247749acb44e..ef69898d2cc5d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c @@ -33,7 +33,7 @@ #include "resource.h" #include "include/irq_service_interface.h" #include "dcn35_resource.h" -#include "dml2/dml2_wrapper.h" +#include "dml2_0/dml2_wrapper.h" #include "dcn20/dcn20_resource.h" #include "dcn30/dcn30_resource.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c index 15479a0290090..f3c614c4490ce 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c @@ -83,7 +83,7 @@ #include "vm_helper.h" #include "dcn20/dcn20_vmid.h" -#include "dml2/dml2_wrapper.h" +#include "dml2_0/dml2_wrapper.h" #include "link_enc_cfg.h" #define DC_LOGGER_INIT(logger) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c index a5d64eaa0791f..6469d5fe2e6d4 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c @@ -11,7 +11,7 @@ #include "resource.h" #include "include/irq_service_interface.h" #include "dcn36_resource.h" -#include "dml2/dml2_wrapper.h" +#include "dml2_0/dml2_wrapper.h" #include "dcn20/dcn20_resource.h" #include "dcn30/dcn30_resource.h" diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 1b813e7a99a68..130058d7a70cd 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -73,7 +73,7 @@ #include "dc_state_priv.h" -#include "dml2/dml2_wrapper.h" +#include "dml2_0/dml2_wrapper.h" #define DC_LOGGER_INIT(logger) diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h index 21d8428576011..88c11b6be0046 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h @@ -9,7 +9,7 @@ #include "dc.h" #include "clk_mgr.h" #include "soc_and_ip_translator.h" -#include "dml2/dml21/inc/dml_top_soc_parameter_types.h" +#include "dml2_0/dml21/inc/dml_top_soc_parameter_types.h" void dcn401_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc_and_ip_translator); From bf9c18308ccac45d7d34ea321a7b00fbac5cd527 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:42 +0200 Subject: [PATCH 2379/2653] drm/amd/display: Add analog bit to edid_caps (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The new analog bit will be used with DVI-I connectors. DVI-I connectors can connect to both digital and analog monitors and this bit will help distinguish between those. v2: Sanitize analog bit based on connector type. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 1 + drivers/gpu/drm/amd/display/dc/dc_types.h | 5 +++++ drivers/gpu/drm/amd/display/dc/link/link_detection.c | 2 ++ drivers/gpu/drm/amd/display/include/grph_object_id.h | 7 +++++++ 4 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 8c5f045ea25b4..ae7f4a0e64542 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -166,6 +166,7 @@ enum dc_edid_status dm_helpers_parse_edid_caps( edid_caps->serial_number = edid_buf->serial; edid_caps->manufacture_week = edid_buf->mfg_week; edid_caps->manufacture_year = edid_buf->mfg_year; + edid_caps->analog = !(edid_buf->input & DRM_EDID_INPUT_DIGITAL); drm_edid_get_monitor_name(edid_buf, edid_caps->display_name, diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 8f8ccde7ad94e..9989c8af5174a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -185,6 +185,10 @@ struct dc_panel_patch { unsigned int wait_after_dpcd_poweroff_ms; }; +/** + * struct dc_edid_caps - Capabilities read from EDID. + * @analog: Whether the monitor is analog. Used by DVI-I handling. + */ struct dc_edid_caps { /* sink identification */ uint16_t manufacturer_id; @@ -213,6 +217,7 @@ struct dc_edid_caps { bool hdr_supported; bool rr_capable; bool scdc_present; + bool analog; struct dc_panel_patch panel_patch; }; diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index 82a9e52d5ae5f..801c94efa7fca 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -1107,6 +1107,8 @@ static bool detect_link_and_local_sink(struct dc_link *link, break; } + sink->edid_caps.analog &= dc_connector_supports_analog(link->link_id.id); + // Check if edid is the same if ((prev_sink) && (edid_status == EDID_THE_SAME || edid_status == EDID_OK)) diff --git a/drivers/gpu/drm/amd/display/include/grph_object_id.h b/drivers/gpu/drm/amd/display/include/grph_object_id.h index 54e33062b3c02..1386fa124e850 100644 --- a/drivers/gpu/drm/amd/display/include/grph_object_id.h +++ b/drivers/gpu/drm/amd/display/include/grph_object_id.h @@ -310,4 +310,11 @@ static inline bool dal_graphics_object_id_equal( } return false; } + +static inline bool dc_connector_supports_analog(const enum connector_id conn) +{ + return conn == CONNECTOR_ID_VGA || + conn == CONNECTOR_ID_SINGLE_LINK_DVII || + conn == CONNECTOR_ID_DUAL_LINK_DVII; +} #endif From 16ae730ff75a9e25e81a1074e9b941295f4d7e18 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:43 +0200 Subject: [PATCH 2380/2653] drm/amd/display: Introduce MAX_LINK_ENCODERS (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We are going to support analog encoders as well, not just digital, so we need to make space for them in various arrays. v2: Fix typo. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- .../drm/amd/display/dc/core/dc_link_enc_cfg.c | 4 ++-- .../gpu/drm/amd/display/dc/inc/core_types.h | 8 +++---- .../gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 24 +++++++++++++++++++ 3 files changed, 30 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c index a180f68f711c2..deb23d20bca67 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c @@ -522,10 +522,10 @@ struct link_encoder *link_enc_cfg_get_link_enc_used_by_link( struct link_encoder *link_enc_cfg_get_next_avail_link_enc(struct dc *dc) { struct link_encoder *link_enc = NULL; - enum engine_id encs_assigned[MAX_DIG_LINK_ENCODERS]; + enum engine_id encs_assigned[MAX_LINK_ENCODERS]; int i; - for (i = 0; i < MAX_DIG_LINK_ENCODERS; i++) + for (i = 0; i < MAX_LINK_ENCODERS; i++) encs_assigned[i] = ENGINE_ID_UNKNOWN; /* Add assigned encoders to list. */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 36688733e208e..65251214c9b53 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -273,7 +273,7 @@ struct resource_pool { /* An array for accessing the link encoder objects that have been created. * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA */ - struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; + struct link_encoder *link_encoders[MAX_LINK_ENCODERS]; /* Number of DIG link encoder objects created - i.e. number of valid * entries in link_encoders array. */ @@ -513,7 +513,7 @@ struct pipe_ctx { struct link_enc_cfg_context { enum link_enc_cfg_mode mode; struct link_enc_assignment link_enc_assignments[MAX_PIPES]; - enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; + enum engine_id link_enc_avail[MAX_LINK_ENCODERS]; struct link_enc_assignment transient_assignments[MAX_PIPES]; }; @@ -525,8 +525,8 @@ struct resource_context { uint8_t dp_clock_source_ref_count; bool is_dsc_acquired[MAX_PIPES]; struct link_enc_cfg_context link_enc_cfg_ctx; - unsigned int dio_link_enc_to_link_idx[MAX_DIG_LINK_ENCODERS]; - int dio_link_enc_ref_cnts[MAX_DIG_LINK_ENCODERS]; + unsigned int dio_link_enc_to_link_idx[MAX_LINK_ENCODERS]; + int dio_link_enc_ref_cnts[MAX_LINK_ENCODERS]; bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index 62a39204fe0b7..5e2813e9ae2fe 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -51,6 +51,30 @@ #define MAX_LINKS (MAX_DPIA + MAX_CONNECTOR + MAX_VIRTUAL_LINKS) +/** + * define MAX_DIG_LINK_ENCODERS - maximum number of digital encoders + * + * Digital encoders are ENGINE_ID_DIGA...G, there are at most 7, + * although not every GPU may have that many. + */ +#define MAX_DIG_LINK_ENCODERS 7 + +/** + * define MAX_DAC_LINK_ENCODERS - maximum number of analog link encoders + * + * Analog encoders are ENGINE_ID_DACA/B, there are at most 2, + * although not every GPU may have that many. Modern GPUs typically + * don't have analog encoders. + */ +#define MAX_DAC_LINK_ENCODERS 2 + +/** + * define MAX_LINK_ENCODERS - maximum number link encoders in total + * + * This includes both analog and digital encoders. + */ +#define MAX_LINK_ENCODERS (MAX_DIG_LINK_ENCODERS + MAX_DAC_LINK_ENCODERS) + #define MAX_DIG_LINK_ENCODERS 7 #define MAX_DWB_PIPES 1 #define MAX_HPO_DP2_ENCODERS 4 From 4a0f75dfee259d053157bd3bf956bd9b03905dec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:44 +0200 Subject: [PATCH 2381/2653] drm/amd/display: Hook up DAC to bios_parser_encoder_control MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the codebase to use encoder_control() when the encoder engine is one of the DACs. The BIOS parser already supports calling the DAC1EncoderControl function from the VBIOS, but it was not exposed anywhere. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- .../gpu/drm/amd/display/dc/bios/bios_parser.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index 154fd2c18e884..318be0bb5549e 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -742,6 +742,22 @@ static enum bp_result bios_parser_encoder_control( { struct bios_parser *bp = BP_FROM_DCB(dcb); + if (cntl->engine_id == ENGINE_ID_DACA) { + if (!bp->cmd_tbl.dac1_encoder_control) + return BP_RESULT_FAILURE; + + return bp->cmd_tbl.dac1_encoder_control( + bp, cntl->action == ENCODER_CONTROL_ENABLE, + cntl->pixel_clock, ATOM_DAC1_PS2); + } else if (cntl->engine_id == ENGINE_ID_DACB) { + if (!bp->cmd_tbl.dac2_encoder_control) + return BP_RESULT_FAILURE; + + return bp->cmd_tbl.dac2_encoder_control( + bp, cntl->action == ENCODER_CONTROL_ENABLE, + cntl->pixel_clock, ATOM_DAC1_PS2); + } + if (!bp->cmd_tbl.dig_encoder_control) return BP_RESULT_FAILURE; From 2f00b0ccd69442fa7614435cfff5216e9952ab50 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:45 +0200 Subject: [PATCH 2382/2653] drm/amd/display: Add SelectCRTC_Source to BIOS parser MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SelectCRTC_Source command will be used to change which CRTC should be connected to which encoder. For reference, see the legacy display code: amdgpu_atombios_encoder_set_crtc_source Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- .../gpu/drm/amd/display/dc/bios/bios_parser.c | 14 ++ .../drm/amd/display/dc/bios/command_table.c | 194 ++++++++++++++++++ .../drm/amd/display/dc/bios/command_table.h | 3 + .../gpu/drm/amd/display/dc/dc_bios_types.h | 3 + .../amd/display/include/bios_parser_types.h | 6 +- 5 files changed, 215 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index 318be0bb5549e..c7875edea3213 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -736,6 +736,18 @@ static enum bp_result bios_parser_transmitter_control( return bp->cmd_tbl.transmitter_control(bp, cntl); } +static enum bp_result bios_parser_select_crtc_source( + struct dc_bios *dcb, + struct bp_crtc_source_select *bp_params) +{ + struct bios_parser *bp = BP_FROM_DCB(dcb); + + if (!bp->cmd_tbl.select_crtc_source) + return BP_RESULT_FAILURE; + + return bp->cmd_tbl.select_crtc_source(bp, bp_params); +} + static enum bp_result bios_parser_encoder_control( struct dc_bios *dcb, struct bp_encoder_control *cntl) @@ -2845,6 +2857,8 @@ static const struct dc_vbios_funcs vbios_funcs = { .is_device_id_supported = bios_parser_is_device_id_supported, /* COMMANDS */ + .select_crtc_source = bios_parser_select_crtc_source, + .encoder_control = bios_parser_encoder_control, .transmitter_control = bios_parser_transmitter_control, diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c index 58e88778da7ff..dbd84477ceb7d 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c @@ -52,6 +52,7 @@ static void init_transmitter_control(struct bios_parser *bp); static void init_set_pixel_clock(struct bios_parser *bp); static void init_enable_spread_spectrum_on_ppll(struct bios_parser *bp); static void init_adjust_display_pll(struct bios_parser *bp); +static void init_select_crtc_source(struct bios_parser *bp); static void init_dac_encoder_control(struct bios_parser *bp); static void init_dac_output_control(struct bios_parser *bp); static void init_set_crtc_timing(struct bios_parser *bp); @@ -69,6 +70,7 @@ void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp) init_set_pixel_clock(bp); init_enable_spread_spectrum_on_ppll(bp); init_adjust_display_pll(bp); + init_select_crtc_source(bp); init_dac_encoder_control(bp); init_dac_output_control(bp); init_set_crtc_timing(bp); @@ -1609,6 +1611,198 @@ static enum bp_result adjust_display_pll_v3( return result; } +/******************************************************************************* + ******************************************************************************** + ** + ** SELECT CRTC SOURCE + ** + ******************************************************************************** + *******************************************************************************/ + +static enum bp_result select_crtc_source_v1( + struct bios_parser *bp, + struct bp_crtc_source_select *bp_params); +static enum bp_result select_crtc_source_v2( + struct bios_parser *bp, + struct bp_crtc_source_select *bp_params); +static enum bp_result select_crtc_source_v3( + struct bios_parser *bp, + struct bp_crtc_source_select *bp_params); + +static void init_select_crtc_source(struct bios_parser *bp) +{ + switch (BIOS_CMD_TABLE_PARA_REVISION(SelectCRTC_Source)) { + case 1: + bp->cmd_tbl.select_crtc_source = select_crtc_source_v1; + break; + case 2: + bp->cmd_tbl.select_crtc_source = select_crtc_source_v2; + break; + case 3: + bp->cmd_tbl.select_crtc_source = select_crtc_source_v3; + break; + default: + bp->cmd_tbl.select_crtc_source = NULL; + break; + } +} + +static enum bp_result select_crtc_source_v1( + struct bios_parser *bp, + struct bp_crtc_source_select *bp_params) +{ + enum bp_result result = BP_RESULT_FAILURE; + SELECT_CRTC_SOURCE_PS_ALLOCATION params; + + if (!bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, ¶ms.ucCRTC)) + return BP_RESULT_BADINPUT; + + switch (bp_params->engine_id) { + case ENGINE_ID_DACA: + params.ucDevice = ATOM_DEVICE_CRT1_INDEX; + break; + case ENGINE_ID_DACB: + params.ucDevice = ATOM_DEVICE_CRT2_INDEX; + break; + default: + return BP_RESULT_BADINPUT; + } + + if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params)) + result = BP_RESULT_OK; + + return result; +} + +static bool select_crtc_source_v2_encoder_id( + enum engine_id engine_id, uint8_t *out_encoder_id) +{ + uint8_t encoder_id = 0; + + switch (engine_id) { + case ENGINE_ID_DIGA: + encoder_id = ASIC_INT_DIG1_ENCODER_ID; + break; + case ENGINE_ID_DIGB: + encoder_id = ASIC_INT_DIG2_ENCODER_ID; + break; + case ENGINE_ID_DIGC: + encoder_id = ASIC_INT_DIG3_ENCODER_ID; + break; + case ENGINE_ID_DIGD: + encoder_id = ASIC_INT_DIG4_ENCODER_ID; + break; + case ENGINE_ID_DIGE: + encoder_id = ASIC_INT_DIG5_ENCODER_ID; + break; + case ENGINE_ID_DIGF: + encoder_id = ASIC_INT_DIG6_ENCODER_ID; + break; + case ENGINE_ID_DIGG: + encoder_id = ASIC_INT_DIG7_ENCODER_ID; + break; + case ENGINE_ID_DACA: + encoder_id = ASIC_INT_DAC1_ENCODER_ID; + break; + case ENGINE_ID_DACB: + encoder_id = ASIC_INT_DAC2_ENCODER_ID; + break; + default: + return false; + } + + *out_encoder_id = encoder_id; + return true; +} + +static bool select_crtc_source_v2_encoder_mode( + enum signal_type signal_type, uint8_t *out_encoder_mode) +{ + uint8_t encoder_mode = 0; + + switch (signal_type) { + case SIGNAL_TYPE_DVI_SINGLE_LINK: + case SIGNAL_TYPE_DVI_DUAL_LINK: + encoder_mode = ATOM_ENCODER_MODE_DVI; + break; + case SIGNAL_TYPE_HDMI_TYPE_A: + encoder_mode = ATOM_ENCODER_MODE_HDMI; + break; + case SIGNAL_TYPE_LVDS: + encoder_mode = ATOM_ENCODER_MODE_LVDS; + break; + case SIGNAL_TYPE_RGB: + encoder_mode = ATOM_ENCODER_MODE_CRT; + break; + case SIGNAL_TYPE_DISPLAY_PORT: + encoder_mode = ATOM_ENCODER_MODE_DP; + break; + case SIGNAL_TYPE_DISPLAY_PORT_MST: + encoder_mode = ATOM_ENCODER_MODE_DP_MST; + break; + case SIGNAL_TYPE_EDP: + encoder_mode = ATOM_ENCODER_MODE_DP; + break; + default: + return false; + } + + *out_encoder_mode = encoder_mode; + return true; +} + +static enum bp_result select_crtc_source_v2( + struct bios_parser *bp, + struct bp_crtc_source_select *bp_params) +{ + enum bp_result result = BP_RESULT_FAILURE; + SELECT_CRTC_SOURCE_PARAMETERS_V3 params; + + if (!bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, ¶ms.ucCRTC)) + return BP_RESULT_BADINPUT; + + if (!select_crtc_source_v2_encoder_id( + bp_params->engine_id, + ¶ms.ucEncoderID)) + return BP_RESULT_BADINPUT; + if (!select_crtc_source_v2_encoder_mode( + bp_params->sink_signal, + ¶ms.ucEncodeMode)) + return BP_RESULT_BADINPUT; + + if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params)) + result = BP_RESULT_OK; + + return result; +} + +static enum bp_result select_crtc_source_v3( + struct bios_parser *bp, + struct bp_crtc_source_select *bp_params) +{ + enum bp_result result = BP_RESULT_FAILURE; + SELECT_CRTC_SOURCE_PARAMETERS_V3 params; + + if (!bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, ¶ms.ucCRTC)) + return BP_RESULT_BADINPUT; + + if (!select_crtc_source_v2_encoder_id( + bp_params->engine_id, + ¶ms.ucEncoderID)) + return BP_RESULT_BADINPUT; + if (!select_crtc_source_v2_encoder_mode( + bp_params->sink_signal, + ¶ms.ucEncodeMode)) + return BP_RESULT_BADINPUT; + + params.ucDstBpc = bp_params->bit_depth; + + if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params)) + result = BP_RESULT_OK; + + return result; +} + /******************************************************************************* ******************************************************************************** ** diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.h b/drivers/gpu/drm/amd/display/dc/bios/command_table.h index ad533775e7242..8b04b903e93d0 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.h +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.h @@ -52,6 +52,9 @@ struct cmd_tbl { enum bp_result (*adjust_display_pll)( struct bios_parser *bp, struct bp_adjust_pixel_clock_parameters *bp_params); + enum bp_result (*select_crtc_source)( + struct bios_parser *bp, + struct bp_crtc_source_select *bp_params); enum bp_result (*dac1_encoder_control)( struct bios_parser *bp, bool enable, diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h index 5fa5e2b63fb7c..545ce1e15eaeb 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h @@ -91,6 +91,9 @@ struct dc_vbios_funcs { struct device_id id); /* COMMANDS */ + enum bp_result (*select_crtc_source)( + struct dc_bios *bios, + struct bp_crtc_source_select *bp_params); enum bp_result (*encoder_control)( struct dc_bios *bios, struct bp_encoder_control *cntl); diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h index 812377d9e48f6..d9e58a6a0d369 100644 --- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h +++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h @@ -135,12 +135,8 @@ struct bp_external_encoder_control { struct bp_crtc_source_select { enum engine_id engine_id; enum controller_id controller_id; - /* from GPU Tx aka asic_signal */ - enum signal_type signal; - /* sink_signal may differ from asicSignal if Translator encoder */ enum signal_type sink_signal; - enum display_output_bit_depth display_output_bit_depth; - bool enable_dp_audio; + uint8_t bit_depth; }; struct bp_transmitter_control { From abb95f08b6e566979d12a3c737ac1ff100db820a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:46 +0200 Subject: [PATCH 2383/2653] drm/amd/display: Get maximum pixel clock from VBIOS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We will use this for validating the pixel clock when an analog monitor is connected to VGA or DVI-I connectors. For reference, see the legacy display code: amdgpu_connector_vga_mode_valid Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 2 ++ drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index c7875edea3213..33d0ec38ded71 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -441,6 +441,7 @@ static enum bp_result get_firmware_info_v1_4( le32_to_cpu(firmware_info->ulMinPixelClockPLL_Output) * 10; info->pll_info.max_output_pxl_clk_pll_frequency = le32_to_cpu(firmware_info->ulMaxPixelClockPLL_Output) * 10; + info->max_pixel_clock = le16_to_cpu(firmware_info->usMaxPixelClock) * 10; if (firmware_info->usFirmwareCapability.sbfAccess.MemoryClockSS_Support) /* Since there is no information on the SS, report conservative @@ -497,6 +498,7 @@ static enum bp_result get_firmware_info_v2_1( info->external_clock_source_frequency_for_dp = le16_to_cpu(firmwareInfo->usUniphyDPModeExtClkFreq) * 10; info->min_allowed_bl_level = firmwareInfo->ucMinAllowedBL_Level; + info->max_pixel_clock = le16_to_cpu(firmwareInfo->usMaxPixelClock) * 10; /* There should be only one entry in the SS info table for Memory Clock */ diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h index cc467031651da..38a77fa9b4afd 100644 --- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h +++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h @@ -169,6 +169,7 @@ struct dc_firmware_info { uint32_t engine_clk_ss_percentage; } feature; + uint32_t max_pixel_clock; /* in KHz */ uint32_t default_display_engine_pll_frequency; /* in KHz */ uint32_t external_clock_source_frequency_for_dp; /* in KHz */ uint32_t smu_gpu_pll_output_freq; /* in KHz */ From 3c5112c6e726f721e45791579fc9b75d94e83e87 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Tue, 21 Oct 2025 13:01:06 +0800 Subject: [PATCH 2384/2653] drm/amdgpu: Convert amdgpu userqueue management from IDR to XArray MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit refactors the AMDGPU userqueue management subsystem to replace IDR (ID Allocation) with XArray for improved performance, scalability, and maintainability. The changes address several issues with the previous IDR implementation and provide better locking semantics. Key changes: 1. **Global XArray Introduction**: - Added `userq_doorbell_xa` to `struct amdgpu_device` for global queue tracking - Uses doorbell_index as key for efficient global lookup - Replaces the previous `userq_mgr_list` linked list approach 2. **Per-process XArray Conversion**: - Replaced `userq_idr` with `userq_mgr_xa` in `struct amdgpu_userq_mgr` - Maintains per-process queue tracking with queue_id as key - Uses XA_FLAGS_ALLOC for automatic ID allocation 3. **Locking Improvements**: - Removed global `userq_mutex` from `struct amdgpu_device` - Replaced with fine-grained XArray locking using XArray's internal spinlocks 4. **Runtime Idle Check Optimization**: - Updated `amdgpu_runtime_idle_check_userq()` to use xa_empty 5. **Queue Management Functions**: - Converted all IDR operations to equivalent XArray functions: - `idr_alloc()` → `xa_alloc()` - `idr_find()` → `xa_load()` - `idr_remove()` → `xa_erase()` - `idr_for_each()` → `xa_for_each()` Benefits: - **Performance**: XArray provides better scalability for large numbers of queues - **Memory Efficiency**: Reduced memory overhead compared to IDR - **Thread Safety**: Improved locking semantics with XArray's internal spinlocks v2: rename userq_global_xa/userq_xa to userq_doorbell_xa/userq_mgr_xa Remove xa_lock and use its own lock. v3: Set queue->userq_mgr = uq_mgr in amdgpu_userq_create() v4: use xa_store_irq (Christian) hold the read side of the reset lock while creating/destroying queues and the manager data structure. (Chritian) Acked-by: Alex Deucher Suggested-by: Christian König Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 16 +- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 151 +++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 8 +- .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 4 +- drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 22 ++- 7 files changed, 101 insertions(+), 111 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 76e70d3ceaeb7..247fc584429aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1202,6 +1202,12 @@ struct amdgpu_device { struct idr userq_idr; spinlock_t userq_lock; #endif + /** + * @userq_doorbell_xa: Global user queue map (doorbell index → queue) + * Key: doorbell_index (unique global identifier for the queue) + * Value: struct amdgpu_usermode_queue + */ + struct xarray userq_doorbell_xa; /* df */ struct amdgpu_df df; @@ -1337,8 +1343,6 @@ struct amdgpu_device { */ bool apu_prefer_gtt; - struct list_head userq_mgr_list; - struct mutex userq_mutex; bool userq_halt_for_enforce_isolation; struct amdgpu_uid *uid_info; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 882fff5a7598d..41dfc031feb3e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4589,7 +4589,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->gfx.userq_sch_mutex); mutex_init(&adev->gfx.workload_profile_mutex); mutex_init(&adev->vcn.workload_profile_mutex); - mutex_init(&adev->userq_mutex); amdgpu_device_init_apu_flags(adev); @@ -4622,7 +4621,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, INIT_LIST_HEAD(&adev->pm.od_kobj_list); - INIT_LIST_HEAD(&adev->userq_mgr_list); + xa_init(&adev->userq_doorbell_xa); INIT_DELAYED_WORK(&adev->delayed_init_work, amdgpu_device_delayed_init_work_handler); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 9a754ba2cdd24..20ad52c9c288c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2839,22 +2839,8 @@ static int amdgpu_runtime_idle_check_userq(struct device *dev) struct pci_dev *pdev = to_pci_dev(dev); struct drm_device *drm_dev = pci_get_drvdata(pdev); struct amdgpu_device *adev = drm_to_adev(drm_dev); - struct amdgpu_usermode_queue *queue; - struct amdgpu_userq_mgr *uqm, *tmp; - int queue_id; - int ret = 0; - - mutex_lock(&adev->userq_mutex); - list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { - idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { - ret = -EBUSY; - goto done; - } - } -done: - mutex_unlock(&adev->userq_mutex); - return ret; + return xa_empty(&adev->userq_doorbell_xa) ? 0 : -EBUSY; } static int amdgpu_pmops_runtime_suspend(struct device *dev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index d185f1751c6ac..a4fd34a5fcc63 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -30,6 +30,7 @@ #include "amdgpu_vm.h" #include "amdgpu_userq.h" #include "amdgpu_hmm.h" +#include "amdgpu_reset.h" #include "amdgpu_userq_fence.h" u32 amdgpu_userq_get_supported_ip_mask(struct amdgpu_device *adev) @@ -278,19 +279,27 @@ amdgpu_userq_cleanup(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_device *adev = uq_mgr->adev; const struct amdgpu_userq_funcs *uq_funcs = adev->userq_funcs[queue->queue_type]; + /* Wait for mode-1 reset to complete */ + down_read(&adev->reset_domain->sem); + /* Drop the userq reference. */ amdgpu_userq_buffer_vas_list_cleanup(adev, queue); uq_funcs->mqd_destroy(uq_mgr, queue); amdgpu_userq_fence_driver_free(queue); - idr_remove(&uq_mgr->userq_idr, queue_id); + /* Use interrupt-safe locking since IRQ handlers may access these XArrays */ + xa_erase_irq(&uq_mgr->userq_mgr_xa, (unsigned long)queue_id); + xa_erase_irq(&adev->userq_doorbell_xa, queue->doorbell_index); + queue->userq_mgr = NULL; list_del(&queue->userq_va_list); kfree(queue); + + up_read(&adev->reset_domain->sem); } static struct amdgpu_usermode_queue * amdgpu_userq_find(struct amdgpu_userq_mgr *uq_mgr, int qid) { - return idr_find(&uq_mgr->userq_idr, qid); + return xa_load(&uq_mgr->userq_mgr_xa, qid); } void @@ -551,8 +560,9 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) struct amdgpu_db_info db_info; char *queue_name; bool skip_map_queue; + u32 qid; uint64_t index; - int qid, r = 0; + int r = 0; int priority = (args->in.flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK) >> AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT; @@ -575,7 +585,6 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) * * This will also make sure we have a valid eviction fence ready to be used. */ - mutex_lock(&adev->userq_mutex); amdgpu_userq_ensure_ev_fence(&fpriv->userq_mgr, &fpriv->evf_mgr); uq_funcs = adev->userq_funcs[args->in.ip_type]; @@ -643,15 +652,27 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) goto unlock; } - qid = idr_alloc(&uq_mgr->userq_idr, queue, 1, AMDGPU_MAX_USERQ_COUNT, GFP_KERNEL); - if (qid < 0) { + /* Wait for mode-1 reset to complete */ + down_read(&adev->reset_domain->sem); + r = xa_err(xa_store_irq(&adev->userq_doorbell_xa, index, queue, GFP_KERNEL)); + if (r) { + kfree(queue); + up_read(&adev->reset_domain->sem); + goto unlock; + } + + r = xa_alloc(&uq_mgr->userq_mgr_xa, &qid, queue, XA_LIMIT(1, AMDGPU_MAX_USERQ_COUNT), GFP_KERNEL); + if (r) { drm_file_err(uq_mgr->file, "Failed to allocate a queue id\n"); amdgpu_userq_fence_driver_free(queue); uq_funcs->mqd_destroy(uq_mgr, queue); kfree(queue); r = -ENOMEM; + up_read(&adev->reset_domain->sem); goto unlock; } + up_read(&adev->reset_domain->sem); + queue->userq_mgr = uq_mgr; /* don't map the queue if scheduling is halted */ if (adev->userq_halt_for_enforce_isolation && @@ -664,7 +685,7 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) r = amdgpu_userq_map_helper(uq_mgr, queue); if (r) { drm_file_err(uq_mgr->file, "Failed to map Queue\n"); - idr_remove(&uq_mgr->userq_idr, qid); + xa_erase(&uq_mgr->userq_mgr_xa, qid); amdgpu_userq_fence_driver_free(queue); uq_funcs->mqd_destroy(uq_mgr, queue); kfree(queue); @@ -689,7 +710,6 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) unlock: mutex_unlock(&uq_mgr->userq_mutex); - mutex_unlock(&adev->userq_mutex); return r; } @@ -787,11 +807,11 @@ static int amdgpu_userq_restore_all(struct amdgpu_userq_mgr *uq_mgr) { struct amdgpu_usermode_queue *queue; - int queue_id; + unsigned long queue_id; int ret = 0, r; /* Resume all the queues for this process */ - idr_for_each_entry(&uq_mgr->userq_idr, queue, queue_id) { + xa_for_each(&uq_mgr->userq_mgr_xa, queue_id, queue) { if (!amdgpu_userq_buffer_vas_mapped(queue)) { drm_file_err(uq_mgr->file, @@ -1041,11 +1061,11 @@ static int amdgpu_userq_evict_all(struct amdgpu_userq_mgr *uq_mgr) { struct amdgpu_usermode_queue *queue; - int queue_id; + unsigned long queue_id; int ret = 0, r; /* Try to unmap all the queues in this process ctx */ - idr_for_each_entry(&uq_mgr->userq_idr, queue, queue_id) { + xa_for_each(&uq_mgr->userq_mgr_xa, queue_id, queue) { r = amdgpu_userq_preempt_helper(uq_mgr, queue); if (r) ret = r; @@ -1060,9 +1080,10 @@ static int amdgpu_userq_wait_for_signal(struct amdgpu_userq_mgr *uq_mgr) { struct amdgpu_usermode_queue *queue; - int queue_id, ret; + unsigned long queue_id; + int ret; - idr_for_each_entry(&uq_mgr->userq_idr, queue, queue_id) { + xa_for_each(&uq_mgr->userq_mgr_xa, queue_id, queue) { struct dma_fence *f = queue->last_fence; if (!f || dma_fence_is_signaled(f)) @@ -1115,44 +1136,30 @@ int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *f struct amdgpu_device *adev) { mutex_init(&userq_mgr->userq_mutex); - idr_init_base(&userq_mgr->userq_idr, 1); + xa_init_flags(&userq_mgr->userq_mgr_xa, XA_FLAGS_ALLOC); userq_mgr->adev = adev; userq_mgr->file = file_priv; - mutex_lock(&adev->userq_mutex); - list_add(&userq_mgr->list, &adev->userq_mgr_list); - mutex_unlock(&adev->userq_mutex); - INIT_DELAYED_WORK(&userq_mgr->resume_work, amdgpu_userq_restore_worker); return 0; } void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr) { - struct amdgpu_device *adev = userq_mgr->adev; struct amdgpu_usermode_queue *queue; - struct amdgpu_userq_mgr *uqm, *tmp; - uint32_t queue_id; + unsigned long queue_id; cancel_delayed_work_sync(&userq_mgr->resume_work); - mutex_lock(&adev->userq_mutex); mutex_lock(&userq_mgr->userq_mutex); - idr_for_each_entry(&userq_mgr->userq_idr, queue, queue_id) { + xa_for_each(&userq_mgr->userq_mgr_xa, queue_id, queue) { amdgpu_userq_wait_for_last_fence(userq_mgr, queue); amdgpu_userq_unmap_helper(userq_mgr, queue); amdgpu_userq_cleanup(userq_mgr, queue, queue_id); } - list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { - if (uqm == userq_mgr) { - list_del(&uqm->list); - break; - } - } - idr_destroy(&userq_mgr->userq_idr); + xa_destroy(&userq_mgr->userq_mgr_xa); mutex_unlock(&userq_mgr->userq_mutex); - mutex_unlock(&adev->userq_mutex); mutex_destroy(&userq_mgr->userq_mutex); } @@ -1160,25 +1167,23 @@ int amdgpu_userq_suspend(struct amdgpu_device *adev) { u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev); struct amdgpu_usermode_queue *queue; - struct amdgpu_userq_mgr *uqm, *tmp; - int queue_id; + struct amdgpu_userq_mgr *uqm; + unsigned long queue_id; int r; if (!ip_mask) return 0; - guard(mutex)(&adev->userq_mutex); - list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { + xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { + uqm = queue->userq_mgr; cancel_delayed_work_sync(&uqm->resume_work); guard(mutex)(&uqm->userq_mutex); - idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { - if (adev->in_s0ix) - r = amdgpu_userq_preempt_helper(uqm, queue); - else - r = amdgpu_userq_unmap_helper(uqm, queue); - if (r) - return r; - } + if (adev->in_s0ix) + r = amdgpu_userq_preempt_helper(uqm, queue); + else + r = amdgpu_userq_unmap_helper(uqm, queue); + if (r) + return r; } return 0; } @@ -1187,24 +1192,22 @@ int amdgpu_userq_resume(struct amdgpu_device *adev) { u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev); struct amdgpu_usermode_queue *queue; - struct amdgpu_userq_mgr *uqm, *tmp; - int queue_id; + struct amdgpu_userq_mgr *uqm; + unsigned long queue_id; int r; if (!ip_mask) return 0; - guard(mutex)(&adev->userq_mutex); - list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { + xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { + uqm = queue->userq_mgr; guard(mutex)(&uqm->userq_mutex); - idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { - if (adev->in_s0ix) - r = amdgpu_userq_restore_helper(uqm, queue); - else - r = amdgpu_userq_map_helper(uqm, queue); - if (r) - return r; - } + if (adev->in_s0ix) + r = amdgpu_userq_restore_helper(uqm, queue); + else + r = amdgpu_userq_map_helper(uqm, queue); + if (r) + return r; } return 0; @@ -1215,33 +1218,31 @@ int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev, { u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev); struct amdgpu_usermode_queue *queue; - struct amdgpu_userq_mgr *uqm, *tmp; - int queue_id; + struct amdgpu_userq_mgr *uqm; + unsigned long queue_id; int ret = 0, r; /* only need to stop gfx/compute */ if (!(ip_mask & ((1 << AMDGPU_HW_IP_GFX) | (1 << AMDGPU_HW_IP_COMPUTE)))) return 0; - mutex_lock(&adev->userq_mutex); if (adev->userq_halt_for_enforce_isolation) dev_warn(adev->dev, "userq scheduling already stopped!\n"); adev->userq_halt_for_enforce_isolation = true; - list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { + xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { + uqm = queue->userq_mgr; cancel_delayed_work_sync(&uqm->resume_work); mutex_lock(&uqm->userq_mutex); - idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { - if (((queue->queue_type == AMDGPU_HW_IP_GFX) || - (queue->queue_type == AMDGPU_HW_IP_COMPUTE)) && - (queue->xcp_id == idx)) { - r = amdgpu_userq_preempt_helper(uqm, queue); - if (r) - ret = r; - } + if (((queue->queue_type == AMDGPU_HW_IP_GFX) || + (queue->queue_type == AMDGPU_HW_IP_COMPUTE)) && + (queue->xcp_id == idx)) { + r = amdgpu_userq_preempt_helper(uqm, queue); + if (r) + ret = r; } mutex_unlock(&uqm->userq_mutex); } - mutex_unlock(&adev->userq_mutex); + return ret; } @@ -1250,21 +1251,20 @@ int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev, { u32 ip_mask = amdgpu_userq_get_supported_ip_mask(adev); struct amdgpu_usermode_queue *queue; - struct amdgpu_userq_mgr *uqm, *tmp; - int queue_id; + struct amdgpu_userq_mgr *uqm; + unsigned long queue_id; int ret = 0, r; /* only need to stop gfx/compute */ if (!(ip_mask & ((1 << AMDGPU_HW_IP_GFX) | (1 << AMDGPU_HW_IP_COMPUTE)))) return 0; - mutex_lock(&adev->userq_mutex); if (!adev->userq_halt_for_enforce_isolation) dev_warn(adev->dev, "userq scheduling already started!\n"); adev->userq_halt_for_enforce_isolation = false; - list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { + xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { + uqm = queue->userq_mgr; mutex_lock(&uqm->userq_mutex); - idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { if (((queue->queue_type == AMDGPU_HW_IP_GFX) || (queue->queue_type == AMDGPU_HW_IP_COMPUTE)) && (queue->xcp_id == idx)) { @@ -1272,10 +1272,9 @@ int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev, if (r) ret = r; } - } mutex_unlock(&uqm->userq_mutex); } - mutex_unlock(&adev->userq_mutex); + return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index 7c4bb06c2d1b9..bd6c226be36b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -101,11 +101,15 @@ struct amdgpu_userq_funcs { /* Usermode queues for gfx */ struct amdgpu_userq_mgr { - struct idr userq_idr; + /** + * @userq_mgr_xa: Per-process user queue map (queue ID → queue) + * Key: queue_id (unique ID within the process's userq manager) + * Value: struct amdgpu_usermode_queue + */ + struct xarray userq_mgr_xa; struct mutex userq_mutex; struct amdgpu_device *adev; struct delayed_work resume_work; - struct list_head list; struct drm_file *file; }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index c7a22997ed72c..10c07ae876c5d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -600,7 +600,7 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, } /* Retrieve the user queue */ - queue = idr_find(&userq_mgr->userq_idr, args->queue_id); + queue = xa_load(&userq_mgr->userq_mgr_xa, args->queue_id); if (!queue) { r = -ENOENT; goto put_gobj_write; @@ -962,7 +962,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, */ num_fences = dma_fence_dedup_array(fences, num_fences); - waitq = idr_find(&userq_mgr->userq_idr, wait_info->waitq_id); + waitq = xa_load(&userq_mgr->userq_mgr_xa, wait_info->waitq_id); if (!waitq) { r = -EINVAL; goto free_fences; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index 5c63480dda9c4..9894a3eed2152 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -205,10 +205,10 @@ static int mes_userq_detect_and_reset(struct amdgpu_device *adev, int db_array_size = amdgpu_mes_get_hung_queue_db_array_size(adev); struct mes_detect_and_reset_queue_input input; struct amdgpu_usermode_queue *queue; - struct amdgpu_userq_mgr *uqm, *tmp; unsigned int hung_db_num = 0; - int queue_id, r, i; + unsigned long queue_id; u32 db_array[8]; + int r, i; if (db_array_size > 8) { dev_err(adev->dev, "DB array size (%d vs 8) too small\n", @@ -227,16 +227,14 @@ static int mes_userq_detect_and_reset(struct amdgpu_device *adev, if (r) { dev_err(adev->dev, "Failed to detect and reset queues, err (%d)\n", r); } else if (hung_db_num) { - list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) { - idr_for_each_entry(&uqm->userq_idr, queue, queue_id) { - if (queue->queue_type == queue_type) { - for (i = 0; i < hung_db_num; i++) { - if (queue->doorbell_index == db_array[i]) { - queue->state = AMDGPU_USERQ_STATE_HUNG; - atomic_inc(&adev->gpu_reset_counter); - amdgpu_userq_fence_driver_force_completion(queue); - drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, NULL); - } + xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { + if (queue->queue_type == queue_type) { + for (i = 0; i < hung_db_num; i++) { + if (queue->doorbell_index == db_array[i]) { + queue->state = AMDGPU_USERQ_STATE_HUNG; + atomic_inc(&adev->gpu_reset_counter); + amdgpu_userq_fence_driver_force_completion(queue); + drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, NULL); } } } From cddd9a488ba819821aa008b5e863eea2b7b063e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:41 +0200 Subject: [PATCH 2385/2653] drm/amd/display: Determine DVI-I connector type (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DC determines the DRM connector type based on the signal type, which becomes problematic when a connector may support different signal types, such as DVI-I. With this patch, it is now determined according to the actual connector type for DVI-D and DVI-I connectors. Also set the HPD (hotplug detection) flag for DVI-I connectors to prevent regressing their digital functionality, which has been already working. A subsequent commit will also implement polling for DVI-I. v2: Only use connector type for DVI to prevent regressions for other signal types. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f34a0e589431a..42afa9a13711e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8497,7 +8497,7 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, } #endif -static int to_drm_connector_type(enum signal_type st) +static int to_drm_connector_type(enum signal_type st, uint32_t connector_id) { switch (st) { case SIGNAL_TYPE_HDMI_TYPE_A: @@ -8513,6 +8513,10 @@ static int to_drm_connector_type(enum signal_type st) return DRM_MODE_CONNECTOR_DisplayPort; case SIGNAL_TYPE_DVI_DUAL_LINK: case SIGNAL_TYPE_DVI_SINGLE_LINK: + if (connector_id == CONNECTOR_ID_SINGLE_LINK_DVII || + connector_id == CONNECTOR_ID_DUAL_LINK_DVII) + return DRM_MODE_CONNECTOR_DVII; + return DRM_MODE_CONNECTOR_DVID; case SIGNAL_TYPE_VIRTUAL: return DRM_MODE_CONNECTOR_VIRTUAL; @@ -8935,6 +8939,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, link->link_enc->features.dp_ycbcr420_supported ? true : false; break; case DRM_MODE_CONNECTOR_DVID: + case DRM_MODE_CONNECTOR_DVII: aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; break; default: @@ -9148,7 +9153,7 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, goto out_free; } - connector_type = to_drm_connector_type(link->connector_signal); + connector_type = to_drm_connector_type(link->connector_signal, link->link_id.id); res = drm_connector_init_with_ddc( dm->ddev, From 932f9052443765c9829e6d84f626c2b353818c4e Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Fri, 24 Oct 2025 10:14:56 +0530 Subject: [PATCH 2386/2653] drm/amdkfd: add missing return value check for range amdgpu_hmm_range_alloc could fails in case of low memory condition and hence we should have a check for the return value. Signed-off-by: Sunil Khatri Reviewed-by: Shirish S --- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 5fe318b27a5f4..5fcc97a07d454 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1742,6 +1742,11 @@ static int svm_range_validate_and_map(struct mm_struct *mm, WRITE_ONCE(p->svms.faulting_task, current); range = amdgpu_hmm_range_alloc(NULL); + if (unlikely(!range)) { + r = -ENOMEM; + goto free_ctx; + } + r = amdgpu_hmm_range_get_pages(&prange->notifier, addr, npages, readonly, owner, range); From 8519a3f0a6c7afca01577505f6f975d82f18b76d Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Wed, 15 Oct 2025 15:17:54 -0400 Subject: [PATCH 2387/2653] drm/amdkfd: Dequeue user queues when process mm released Move dequeue user queues and destroy user queues from kfd_process_wq_release to mmu notifier release callback, to ensure no system memory access from GPU because the process memory is going to free from CPU after mmu release notifier callback returns. Destroy queue releases the svm prange queue_refcount, this also removes fake flase positive warning message "Freeing queue vital buffer" message if application crash or killed. Suggested-by: Felix Kuehling Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index c61e61acfb044..b6dc44395c408 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1166,9 +1166,6 @@ static void kfd_process_wq_release(struct work_struct *work) release_work); struct dma_fence *ef; - kfd_process_dequeue_from_all_devices(p); - pqm_uninit(&p->pqm); - /* * If GPU in reset, user queues may still running, wait for reset complete. */ @@ -1242,6 +1239,14 @@ static void kfd_process_notifier_release_internal(struct kfd_process *p) cancel_delayed_work_sync(&p->eviction_work); cancel_delayed_work_sync(&p->restore_work); + /* + * Dequeue and destroy user queues, it is not safe for GPU to access + * system memory after mmu release notifier callback returns because + * exit_mmap free process memory afterwards. + */ + kfd_process_dequeue_from_all_devices(p); + pqm_uninit(&p->pqm); + for (i = 0; i < p->n_pdds; i++) { struct kfd_process_device *pdd = p->pdds[i]; From 68f5d27872f54faa51cc32e1217a3b89a7de6d54 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 10 Oct 2025 15:21:02 -0400 Subject: [PATCH 2388/2653] drm/amdgpu/userq: fix SDMA and compute validation The CSA and EOP buffers have different alignement requirements. Hardcode them for now as a bug fix. A proper query will be added in a subsequent patch. v2: verify gfx shadow helper callback (Prike) Fixes: 9e46b8bb0539 ("drm/amdgpu: validate userq buffer virtual address and size") Reviewed-by: Prike Liang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index 9894a3eed2152..b1ee9473d6280 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -252,7 +252,6 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_mqd *mqd_hw_default = &adev->mqds[queue->queue_type]; struct drm_amdgpu_userq_in *mqd_user = args_in; struct amdgpu_mqd_prop *userq_props; - struct amdgpu_gfx_shadow_info shadow_info; int r; /* Structure to initialize MQD for userqueue using generic MQD init function */ @@ -278,8 +277,6 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, userq_props->doorbell_index = queue->doorbell_index; userq_props->fence_address = queue->fence_drv->gpu_addr; - if (adev->gfx.funcs->get_gfx_shadow_info) - adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow_info, true); if (queue->queue_type == AMDGPU_HW_IP_COMPUTE) { struct drm_amdgpu_userq_mqd_compute_gfx11 *compute_mqd; @@ -297,7 +294,7 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, } r = amdgpu_userq_input_va_validate(queue, compute_mqd->eop_va, - max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE)); + 2048); if (r) goto free_mqd; @@ -310,6 +307,14 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, kfree(compute_mqd); } else if (queue->queue_type == AMDGPU_HW_IP_GFX) { struct drm_amdgpu_userq_mqd_gfx11 *mqd_gfx_v11; + struct amdgpu_gfx_shadow_info shadow_info; + + if (adev->gfx.funcs->get_gfx_shadow_info) { + adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow_info, true); + } else { + r = -EINVAL; + goto free_mqd; + } if (mqd_user->mqd_size != sizeof(*mqd_gfx_v11) || !mqd_user->mqd) { DRM_ERROR("Invalid GFX MQD\n"); @@ -333,6 +338,10 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, shadow_info.shadow_size); if (r) goto free_mqd; + r = amdgpu_userq_input_va_validate(queue, mqd_gfx_v11->csa_va, + shadow_info.csa_size); + if (r) + goto free_mqd; kfree(mqd_gfx_v11); } else if (queue->queue_type == AMDGPU_HW_IP_DMA) { @@ -351,7 +360,7 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, goto free_mqd; } r = amdgpu_userq_input_va_validate(queue, mqd_sdma_v11->csa_va, - shadow_info.csa_size); + 32); if (r) goto free_mqd; From e1aea6393ecd51ee9d8a07a17e786e869b371484 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Fri, 24 Oct 2025 22:29:00 +0530 Subject: [PATCH 2389/2653] drm/amdkfd: fix the clean up when amdgpu_hmm_range_alloc fails we need to unreserve the bo's too during clean up along with freeing the memory of context. Fixes: c549912cd8ab ("drm/amdkfd: add missing return value check for range") Signed-off-by: Sunil Khatri Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 5fcc97a07d454..9dbe2b69e5386 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1742,14 +1742,11 @@ static int svm_range_validate_and_map(struct mm_struct *mm, WRITE_ONCE(p->svms.faulting_task, current); range = amdgpu_hmm_range_alloc(NULL); - if (unlikely(!range)) { + if (likely(range)) + r = amdgpu_hmm_range_get_pages(&prange->notifier, addr, npages, + readonly, owner, range); + else r = -ENOMEM; - goto free_ctx; - } - - r = amdgpu_hmm_range_get_pages(&prange->notifier, addr, npages, - readonly, owner, - range); WRITE_ONCE(p->svms.faulting_task, NULL); if (r) { amdgpu_hmm_range_free(range); From 8fc83128055e3709e8d23355bda7e77dee6a02d4 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Thu, 23 Oct 2025 19:54:16 +0530 Subject: [PATCH 2390/2653] drm/amdkfd: Fix use-after-free of HMM range in svm_range_validate_and_map() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The function svm_range_validate_and_map() was freeing `range` when amdgpu_hmm_range_get_pages() failed. But later, the code still used the same `range` pointer and freed it again. This could cause a use-after-free and double-free issue. The fix sets `range = NULL` right after it is freed and checks for `range` before using or freeing it again. v2: Removed duplicate !r check in the condition for clarity. v3: In amdgpu_hmm_range_get_pages(), when hmm_range_fault() fails, we kvfree(pfns) but leave the pointer in hmm_range->hmm_pfns still pointing to freed memory. The caller (or amdgpu_hmm_range_free(range)) may try to free range->hmm_range.hmm_pfns again, causing a double free, Setting hmm_range->hmm_pfns = NULL immediately after kvfree(pfns) prevents both double free. (Philip) In svm_range_validate_and_map(), When r == 0, it means success → range is not NULL. When r != 0, it means failure → already made range = NULL. So checking both (!r && range) is unnecessary because the moment r == 0, we automatically know range exists and is safe to use. (Philip) Fixes: c5e357c924e5 ("drm/amdgpu: update the functions to use amdgpu version of hmm") Reported by: Dan Carpenter Cc: Philip Yang Cc: Sunil Khatri Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Philip Yang --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 6 ++++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 1a9101a3d68bf..df99c4b4c6a11 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -914,6 +914,7 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, out_free_pfns: kvfree(pfns); + hmm_range->hmm_pfns = NULL; out_free_range: if (r == -EBUSY) r = -EAGAIN; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 9dbe2b69e5386..59e2edcef37a3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1750,6 +1750,7 @@ static int svm_range_validate_and_map(struct mm_struct *mm, WRITE_ONCE(p->svms.faulting_task, NULL); if (r) { amdgpu_hmm_range_free(range); + range = NULL; pr_debug("failed %d to get svm range pages\n", r); } } else { @@ -1767,7 +1768,7 @@ static int svm_range_validate_and_map(struct mm_struct *mm, svm_range_lock(prange); /* Free backing memory of hmm_range if it was initialized - * Overrride return value to TRY AGAIN only if prior returns + * Override return value to TRY AGAIN only if prior returns * were successful */ if (range && !amdgpu_hmm_range_valid(range) && !r) { @@ -1775,7 +1776,8 @@ static int svm_range_validate_and_map(struct mm_struct *mm, r = -EAGAIN; } /* Free the hmm range */ - amdgpu_hmm_range_free(range); + if (range) + amdgpu_hmm_range_free(range); if (!r && !list_empty(&prange->child_list)) { From 29f14fc86d6c6819dd8b9ebc284ee1529631b14d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:47 +0200 Subject: [PATCH 2391/2653] drm/amd/display: Don't use stereo sync and audio on RGB signals (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Analog video signals on VGA or DVI-A (analog part of DVI-I) don't support audio, so avoid calling any audio related functions on analog signals. Stereo sync was not set up for analog signals in the legacy display code either, so there is no loss of functionality if we omit it from DC for now. Also add a dc_is_rgb_signal similar to other dc_is_*_signal. v2: Added comment to clarify what we mean by RGB in this context. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- .../gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c | 3 ++- drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 6 ++++-- drivers/gpu/drm/amd/display/include/signal_types.h | 12 ++++++++++++ 3 files changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c index 892907991f912..80344cbd1f995 100644 --- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c +++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c @@ -115,7 +115,8 @@ void setup_dio_stream_attribute(struct pipe_ctx *pipe_ctx) struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->link; - if (!dc_is_virtual_signal(stream->signal)) + if (!dc_is_virtual_signal(stream->signal) && + !dc_is_rgb_signal(stream->signal)) stream_encoder->funcs->setup_stereo_sync( stream_encoder, pipe_ctx->stream_res.tg->inst, diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index a9387c3a72b1b..3407331527313 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -2453,7 +2453,8 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx) set_avmute(pipe_ctx, true); } - dc->hwss.disable_audio_stream(pipe_ctx); + if (!dc_is_rgb_signal(pipe_ctx->stream->signal)) + dc->hwss.disable_audio_stream(pipe_ctx); update_psp_stream_config(pipe_ctx, true); dc->hwss.blank_stream(pipe_ctx); @@ -2737,7 +2738,8 @@ void link_set_dpms_on( enable_stream_features(pipe_ctx); update_psp_stream_config(pipe_ctx, false); - dc->hwss.enable_audio_stream(pipe_ctx); + if (!dc_is_rgb_signal(pipe_ctx->stream->signal)) + dc->hwss.enable_audio_stream(pipe_ctx); if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { set_avmute(pipe_ctx, false); diff --git a/drivers/gpu/drm/amd/display/include/signal_types.h b/drivers/gpu/drm/amd/display/include/signal_types.h index a10d6b988aab2..3a2c2d2fb6291 100644 --- a/drivers/gpu/drm/amd/display/include/signal_types.h +++ b/drivers/gpu/drm/amd/display/include/signal_types.h @@ -118,6 +118,18 @@ static inline bool dc_is_dvi_signal(enum signal_type signal) } } +/** + * dc_is_rgb_signal() - Whether the signal is analog RGB. + * + * Returns whether the given signal type is an analog RGB signal + * that is used with a DAC on VGA or DVI-I connectors. + * Not to be confused with other uses of "RGB", such as RGB color space. + */ +static inline bool dc_is_rgb_signal(enum signal_type signal) +{ + return (signal == SIGNAL_TYPE_RGB); +} + static inline bool dc_is_tmds_signal(enum signal_type signal) { switch (signal) { From b5d4fe23011d942f05eef009f4a0778b05092fd3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:48 +0200 Subject: [PATCH 2392/2653] drm/amd/display: Don't try to enable/disable HPD when unavailable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit VGA connectors don't have HPD (hotplug detection), so don't touch any HPD related registers for VGA. Determine whether hotplug detection is available by checking that the interrupt source is invalid. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 8c8eeb5fb8606..a011fc5bfa8f3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -768,6 +768,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us int max_param_num = 11; enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; bool disable_hpd = false; + bool supports_hpd = link->irq_source_hpd != DC_IRQ_SOURCE_INVALID; bool valid_test_pattern = false; uint8_t param_nums = 0; /* init with default 80bit custom pattern */ @@ -859,7 +860,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us * because it might have been disabled after a test pattern was set. * AUX depends on HPD * sequence dependent, do not move! */ - if (!disable_hpd) + if (supports_hpd && !disable_hpd) dc_link_enable_hpd(link); prefer_link_settings.lane_count = link->verified_link_cap.lane_count; @@ -897,7 +898,7 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us * Need disable interrupt to avoid SW driver disable DP output. This is * done after the test pattern is set. */ - if (valid_test_pattern && disable_hpd) + if (valid_test_pattern && supports_hpd && disable_hpd) dc_link_disable_hpd(link); kfree(wr_buf); From 2bafd749657aa452b7555d5cd281e8754d28f57b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:49 +0200 Subject: [PATCH 2393/2653] drm/amd/display: Determine early if a link has supported encoders (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid initializing DDC, HPD, etc. when we know that the link is not going to be constructed because it has no supported encoders. This is mainly useful for old GPUs which may have encoders such as TRAVIS and NUTMEG that are not yet supported by DC. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- .../drm/amd/display/dc/link/link_factory.c | 23 +++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c index f06af98d46ee8..8899797f64a9c 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@ -451,6 +451,14 @@ static enum channel_id get_ddc_line(struct dc_link *link) return channel; } +static bool transmitter_supported(const enum transmitter transmitter) +{ + return transmitter != TRANSMITTER_UNKNOWN && + transmitter != TRANSMITTER_NUTMEG_CRT && + transmitter != TRANSMITTER_TRAVIS_CRT && + transmitter != TRANSMITTER_TRAVIS_LCD; +} + static bool construct_phy(struct dc_link *link, const struct link_init_data *init_params) { @@ -482,6 +490,17 @@ static bool construct_phy(struct dc_link *link, link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index); + /* Determine early if the link has any supported encoders, + * so that we avoid initializing DDC and HPD, etc. + */ + bp_funcs->get_src_obj(bios, link->link_id, 0, &enc_init_data.encoder); + enc_init_data.transmitter = translate_encoder_to_transmitter(enc_init_data.encoder); + + if (!transmitter_supported(enc_init_data.transmitter)) { + DC_LOG_WARNING("link_id %d has unsupported encoder\n", link->link_id.id); + return false; + } + link->ep_type = DISPLAY_ENDPOINT_PHY; DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id); @@ -611,16 +630,12 @@ static bool construct_phy(struct dc_link *link, dal_ddc_get_line(get_ddc_pin(link->ddc)); enc_init_data.ctx = dc_ctx; - bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, - &enc_init_data.encoder); enc_init_data.connector = link->link_id; enc_init_data.channel = get_ddc_line(link); enc_init_data.hpd_source = get_hpd_line(link); link->hpd_src = enc_init_data.hpd_source; - enc_init_data.transmitter = - translate_encoder_to_transmitter(enc_init_data.encoder); link->link_enc = link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data); From c24877ab2bfde8962d59d54536ebf18edb9d03cc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:50 +0200 Subject: [PATCH 2394/2653] drm/amd/display: Add concept of analog encoders (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a num_analog_stream_encoders field to indicate how many analog stream encoders are present. When analog stream encoders are present, create them. Additionally, add an analog_engine field to link encoders and search for supported analog encoders in the BIOS for each link. When connecting an RGB signal, search for analog stream encoders. The actual DCE analog link and stream encoder is going to be added in a subsequent commit. v2: Add check to see if an analog engine is really supported. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- .../gpu/drm/amd/display/dc/core/dc_resource.c | 8 +++++ .../drm/amd/display/dc/inc/hw/link_encoder.h | 2 ++ drivers/gpu/drm/amd/display/dc/inc/resource.h | 1 + .../drm/amd/display/dc/link/link_factory.c | 36 ++++++++++++++++++- .../dc/resource/dce100/dce100_resource.c | 7 ++-- 5 files changed, 51 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 89fe72820f6a1..dc0c4065a92cb 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -446,6 +446,14 @@ bool resource_construct( DC_ERR("DC: failed to create stream_encoder!\n"); pool->stream_enc_count++; } + + for (i = 0; i < caps->num_analog_stream_encoder; i++) { + pool->stream_enc[caps->num_stream_encoder + i] = + create_funcs->create_stream_encoder(ENGINE_ID_DACA + i, ctx); + if (pool->stream_enc[caps->num_stream_encoder + i] == NULL) + DC_ERR("DC: failed to create analog stream_encoder %d!\n", i); + pool->stream_enc_count++; + } } pool->hpo_dp_stream_enc_count = 0; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 08c16ba52a51f..df512920a9fab 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -47,6 +47,7 @@ struct encoder_init_data { enum hpd_source_id hpd_source; /* TODO: in DAL2, here was pointer to EventManagerInterface */ struct graphics_object_id encoder; + enum engine_id analog_engine; struct dc_context *ctx; enum transmitter transmitter; }; @@ -83,6 +84,7 @@ struct link_encoder { struct graphics_object_id connector; uint32_t output_signals; enum engine_id preferred_engine; + enum engine_id analog_engine; struct encoder_feature_support features; enum transmitter transmitter; enum hpd_source_id hpd_source; diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 4e26a16a8743f..79746d931471a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -49,6 +49,7 @@ struct resource_caps { int num_video_plane; int num_audio; int num_stream_encoder; + int num_analog_stream_encoder; int num_pll; int num_dwb; int num_ddc; diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c index 8899797f64a9c..ebc3798e7d25d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@ -451,6 +451,32 @@ static enum channel_id get_ddc_line(struct dc_link *link) return channel; } +static enum engine_id find_analog_engine(struct dc_link *link) +{ + struct dc_bios *bp = link->ctx->dc_bios; + struct graphics_object_id encoder = {0}; + enum bp_result bp_result = BP_RESULT_OK; + int i; + + for (i = 0; i < 3; i++) { + bp_result = bp->funcs->get_src_obj(bp, link->link_id, i, &encoder); + + if (bp_result != BP_RESULT_OK) + return ENGINE_ID_UNKNOWN; + + switch (encoder.id) { + case ENCODER_ID_INTERNAL_DAC1: + case ENCODER_ID_INTERNAL_KLDSCP_DAC1: + return ENGINE_ID_DACA; + case ENCODER_ID_INTERNAL_DAC2: + case ENCODER_ID_INTERNAL_KLDSCP_DAC2: + return ENGINE_ID_DACB; + } + } + + return ENGINE_ID_UNKNOWN; +} + static bool transmitter_supported(const enum transmitter transmitter) { return transmitter != TRANSMITTER_UNKNOWN && @@ -459,6 +485,12 @@ static bool transmitter_supported(const enum transmitter transmitter) transmitter != TRANSMITTER_TRAVIS_LCD; } +static bool analog_engine_supported(const enum engine_id engine_id) +{ + return engine_id == ENGINE_ID_DACA || + engine_id == ENGINE_ID_DACB; +} + static bool construct_phy(struct dc_link *link, const struct link_init_data *init_params) { @@ -495,8 +527,10 @@ static bool construct_phy(struct dc_link *link, */ bp_funcs->get_src_obj(bios, link->link_id, 0, &enc_init_data.encoder); enc_init_data.transmitter = translate_encoder_to_transmitter(enc_init_data.encoder); + enc_init_data.analog_engine = find_analog_engine(link); - if (!transmitter_supported(enc_init_data.transmitter)) { + if (!transmitter_supported(enc_init_data.transmitter) && + !analog_engine_supported(enc_init_data.analog_engine)) { DC_LOG_WARNING("link_id %d has unsupported encoder\n", link->link_id.id); return false; } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index 550466de1a660..7573f5130ea97 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -954,6 +954,10 @@ struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link( int i; int j = -1; struct dc_link *link = stream->link; + enum engine_id preferred_engine = link->link_enc->preferred_engine; + + if (dc_is_rgb_signal(stream->signal)) + preferred_engine = link->link_enc->analog_engine; for (i = 0; i < pool->stream_enc_count; i++) { if (!res_ctx->is_stream_enc_acquired[i] && @@ -962,8 +966,7 @@ struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link( * in daisy chain use case */ j = i; - if (pool->stream_enc[i]->id == - link->link_enc->preferred_engine) + if (pool->stream_enc[i]->id == preferred_engine) return pool->stream_enc[i]; } } From 165b205a143a63ae762941e6fcd615476e81107a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:51 +0200 Subject: [PATCH 2395/2653] drm/amd/display: Implement DCE analog stream encoders MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add analog stream encoders for DCE which will be used when connecting an analog display through VGA or DVI-I. Considering that all stream encoder functions currently deal with digital streams, there is nothing for an analog stream encoder to do, making them basically a no-op. That being said, we still need some kind of stream encoder to represent an analog stream, and it is beneficial to split them from digital stream encoders in the code to make sure they don't accidentally write any DIG* registers. On supported chips there is currently up to 1 analog encoder, which is DACA. There are references to DACB in some code such as VBIOS commands and register files but it seems to be not present on DCE 6 and newer. Set num_analog_stream_encoder = 1 so that we can support the analog connectors on DCE 6-10, for now. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- .../drm/amd/display/dc/dce/dce_stream_encoder.c | 14 ++++++++++++++ .../drm/amd/display/dc/dce/dce_stream_encoder.h | 5 +++++ .../display/dc/resource/dce100/dce100_resource.c | 6 ++++++ .../amd/display/dc/resource/dce60/dce60_resource.c | 8 ++++++++ .../amd/display/dc/resource/dce80/dce80_resource.c | 8 ++++++++ 5 files changed, 41 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index 1130d7619b263..f8996ee2856b4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -1567,3 +1567,17 @@ void dce110_stream_encoder_construct( enc110->se_shift = se_shift; enc110->se_mask = se_mask; } + +static const struct stream_encoder_funcs dce110_an_str_enc_funcs = {0}; + +void dce110_analog_stream_encoder_construct( + struct dce110_stream_encoder *enc110, + struct dc_context *ctx, + struct dc_bios *bp, + enum engine_id eng_id) +{ + enc110->base.funcs = &dce110_an_str_enc_funcs; + enc110->base.ctx = ctx; + enc110->base.id = eng_id; + enc110->base.bp = bp; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h index cc5020a8e1e1e..068de1392121e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h @@ -708,6 +708,11 @@ void dce110_stream_encoder_construct( const struct dce_stream_encoder_shift *se_shift, const struct dce_stream_encoder_mask *se_mask); +void dce110_analog_stream_encoder_construct( + struct dce110_stream_encoder *enc110, + struct dc_context *ctx, + struct dc_bios *bp, + enum engine_id eng_id); void dce110_se_audio_mute_control( struct stream_encoder *enc, bool mute); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index 7573f5130ea97..3856477981c62 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -375,6 +375,7 @@ static const struct bios_registers bios_regs = { static const struct resource_caps res_cap = { .num_timing_generator = 6, .num_audio = 6, + .num_analog_stream_encoder = 1, .num_stream_encoder = 6, .num_pll = 3, .num_ddc = 6, @@ -486,6 +487,11 @@ static struct stream_encoder *dce100_stream_encoder_create( if (!enc110) return NULL; + if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) { + dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id); + return &enc110->base; + } + dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, &stream_enc_regs[eng_id], &se_shift, &se_mask); return &enc110->base; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c index b75be6ad64f6c..7195f435e3f76 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c @@ -373,6 +373,7 @@ static const struct bios_registers bios_regs = { static const struct resource_caps res_cap = { .num_timing_generator = 6, .num_audio = 6, + .num_analog_stream_encoder = 1, .num_stream_encoder = 6, .num_pll = 3, .num_ddc = 6, @@ -382,6 +383,7 @@ static const struct resource_caps res_cap_61 = { .num_timing_generator = 4, .num_audio = 6, .num_stream_encoder = 6, + .num_analog_stream_encoder = 1, .num_pll = 3, .num_ddc = 6, }; @@ -389,6 +391,7 @@ static const struct resource_caps res_cap_61 = { static const struct resource_caps res_cap_64 = { .num_timing_generator = 2, .num_audio = 2, + .num_analog_stream_encoder = 1, .num_stream_encoder = 2, .num_pll = 3, .num_ddc = 2, @@ -599,6 +602,11 @@ static struct stream_encoder *dce60_stream_encoder_create( if (!enc110) return NULL; + if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) { + dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id); + return &enc110->base; + } + dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, &stream_enc_regs[eng_id], &se_shift, &se_mask); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c index c4a56ec60b82d..e9b79db37d1be 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c @@ -375,6 +375,7 @@ static const struct bios_registers bios_regs = { static const struct resource_caps res_cap = { .num_timing_generator = 6, .num_audio = 6, + .num_analog_stream_encoder = 1, .num_stream_encoder = 6, .num_pll = 3, .num_ddc = 6, @@ -383,6 +384,7 @@ static const struct resource_caps res_cap = { static const struct resource_caps res_cap_81 = { .num_timing_generator = 4, .num_audio = 7, + .num_analog_stream_encoder = 1, .num_stream_encoder = 7, .num_pll = 3, .num_ddc = 6, @@ -391,6 +393,7 @@ static const struct resource_caps res_cap_81 = { static const struct resource_caps res_cap_83 = { .num_timing_generator = 2, .num_audio = 6, + .num_analog_stream_encoder = 1, .num_stream_encoder = 6, .num_pll = 2, .num_ddc = 2, @@ -607,6 +610,11 @@ static struct stream_encoder *dce80_stream_encoder_create( if (!enc110) return NULL; + if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) { + dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id); + return &enc110->base; + } + dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, &stream_enc_regs[eng_id], &se_shift, &se_mask); From d41ff1a31d01c7152c72d6ad9ba93d71506ae956 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:52 +0200 Subject: [PATCH 2396/2653] drm/amd/display: Implement DCE analog link encoders (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We support two kinds of analog connections: 1. DVI-I, which allows both digital and analog signals: The DC code base only allows 1 encoder per connector, and the preferred engine type is still going to be digital. So, for DVI-I to work, we need to make sure the pre-existing link encoder can also work with analog signals. 1. VGA, which only supports analog signals: For VGA, we need to create a link encoder that only works with the DAC without perturbing any digital transmitter functionality. Since dce110_link_encoder already supports analog DVI-I, just reuse that code for VGA as well. v2: Reduce code churn by reusing same link encoder for VGA and DVI-I. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- .../drm/amd/display/dc/dce/dce_link_encoder.c | 85 +++++++++++++++++++ .../drm/amd/display/dc/dce/dce_link_encoder.h | 16 ++-- .../dc/resource/dce100/dce100_resource.c | 16 +++- .../dc/resource/dce60/dce60_resource.c | 19 ++++- .../dc/resource/dce80/dce80_resource.c | 16 +++- 5 files changed, 141 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 0c50fe266c8a1..87dbb8d7ed27d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -302,6 +302,10 @@ static void setup_panel_mode( if (ctx->dc->caps.psp_setup_panel_mode) return; + /* The code below is only applicable to encoders with a digital transmitter. */ + if (enc110->base.transmitter == TRANSMITTER_UNKNOWN) + return; + ASSERT(REG(DP_DPHY_INTERNAL_CTRL)); value = REG_READ(DP_DPHY_INTERNAL_CTRL); @@ -804,6 +808,33 @@ bool dce110_link_encoder_validate_dp_output( return true; } +static bool dce110_link_encoder_validate_rgb_output( + const struct dce110_link_encoder *enc110, + const struct dc_crtc_timing *crtc_timing) +{ + /* When the VBIOS doesn't specify any limits, use 400 MHz. + * The value comes from amdgpu_atombios_get_clock_info. + */ + uint32_t max_pixel_clock_khz = 400000; + + if (enc110->base.ctx->dc_bios->fw_info_valid && + enc110->base.ctx->dc_bios->fw_info.max_pixel_clock) { + max_pixel_clock_khz = + enc110->base.ctx->dc_bios->fw_info.max_pixel_clock; + } + + if (crtc_timing->pix_clk_100hz > max_pixel_clock_khz * 10) + return false; + + if (crtc_timing->display_color_depth != COLOR_DEPTH_888) + return false; + + if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB) + return false; + + return true; +} + void dce110_link_encoder_construct( struct dce110_link_encoder *enc110, const struct encoder_init_data *init_data, @@ -824,6 +855,7 @@ void dce110_link_encoder_construct( enc110->base.connector = init_data->connector; enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; + enc110->base.analog_engine = init_data->analog_engine; enc110->base.features = *enc_features; @@ -847,6 +879,11 @@ void dce110_link_encoder_construct( SIGNAL_TYPE_EDP | SIGNAL_TYPE_HDMI_TYPE_A; + if ((enc110->base.connector.id == CONNECTOR_ID_DUAL_LINK_DVII || + enc110->base.connector.id == CONNECTOR_ID_SINGLE_LINK_DVII) && + enc110->base.analog_engine != ENGINE_ID_UNKNOWN) + enc110->base.output_signals |= SIGNAL_TYPE_RGB; + /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer @@ -885,6 +922,13 @@ void dce110_link_encoder_construct( enc110->base.preferred_engine = ENGINE_ID_DIGG; break; default: + if (init_data->analog_engine != ENGINE_ID_UNKNOWN) { + /* The connector is analog-only, ie. VGA */ + enc110->base.preferred_engine = init_data->analog_engine; + enc110->base.output_signals = SIGNAL_TYPE_RGB; + enc110->base.transmitter = TRANSMITTER_UNKNOWN; + break; + } ASSERT_CRITICAL(false); enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; } @@ -939,6 +983,10 @@ bool dce110_link_encoder_validate_output_with_stream( is_valid = dce110_link_encoder_validate_dp_output( enc110, &stream->timing); break; + case SIGNAL_TYPE_RGB: + is_valid = dce110_link_encoder_validate_rgb_output( + enc110, &stream->timing); + break; case SIGNAL_TYPE_EDP: case SIGNAL_TYPE_LVDS: is_valid = stream->timing.pixel_encoding == PIXEL_ENCODING_RGB; @@ -969,6 +1017,10 @@ void dce110_link_encoder_hw_init( cntl.coherent = false; cntl.hpd_sel = enc110->base.hpd_source; + /* The code below is only applicable to encoders with a digital transmitter. */ + if (enc110->base.transmitter == TRANSMITTER_UNKNOWN) + return; + if (enc110->base.connector.id == CONNECTOR_ID_EDP) cntl.signal = SIGNAL_TYPE_EDP; @@ -1034,6 +1086,8 @@ void dce110_link_encoder_setup( /* DP MST */ REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5); break; + case SIGNAL_TYPE_RGB: + break; default: ASSERT_CRITICAL(false); /* invalid mode ! */ @@ -1282,6 +1336,24 @@ void dce110_link_encoder_disable_output( struct bp_transmitter_control cntl = { 0 }; enum bp_result result; + switch (enc->analog_engine) { + case ENGINE_ID_DACA: + REG_UPDATE(DAC_ENABLE, DAC_ENABLE, 0); + break; + case ENGINE_ID_DACB: + /* DACB doesn't seem to be present on DCE6+, + * although there are references to it in the register file. + */ + DC_LOG_ERROR("%s DACB is unsupported\n", __func__); + break; + default: + break; + } + + /* The code below only applies to connectors that support digital signals. */ + if (enc->transmitter == TRANSMITTER_UNKNOWN) + return; + if (!dce110_is_dig_enabled(enc)) { /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */ return; @@ -1726,6 +1798,7 @@ void dce60_link_encoder_construct( enc110->base.connector = init_data->connector; enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; + enc110->base.analog_engine = init_data->analog_engine; enc110->base.features = *enc_features; @@ -1749,6 +1822,11 @@ void dce60_link_encoder_construct( SIGNAL_TYPE_EDP | SIGNAL_TYPE_HDMI_TYPE_A; + if ((enc110->base.connector.id == CONNECTOR_ID_DUAL_LINK_DVII || + enc110->base.connector.id == CONNECTOR_ID_SINGLE_LINK_DVII) && + enc110->base.analog_engine != ENGINE_ID_UNKNOWN) + enc110->base.output_signals |= SIGNAL_TYPE_RGB; + /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer @@ -1787,6 +1865,13 @@ void dce60_link_encoder_construct( enc110->base.preferred_engine = ENGINE_ID_DIGG; break; default: + if (init_data->analog_engine != ENGINE_ID_UNKNOWN) { + /* The connector is analog-only, ie. VGA */ + enc110->base.preferred_engine = init_data->analog_engine; + enc110->base.output_signals = SIGNAL_TYPE_RGB; + enc110->base.transmitter = TRANSMITTER_UNKNOWN; + break; + } ASSERT_CRITICAL(false); enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index 261c70e01e331..c58b69bc319b7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -101,18 +101,21 @@ SRI(DP_SEC_CNTL, DP, id), \ SRI(DP_VID_STREAM_CNTL, DP, id), \ SRI(DP_DPHY_FAST_TRAINING, DP, id), \ - SRI(DP_SEC_CNTL1, DP, id) + SRI(DP_SEC_CNTL1, DP, id), \ + SR(DAC_ENABLE) #endif #define LE_DCE80_REG_LIST(id)\ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ - LE_COMMON_REG_LIST_BASE(id) + LE_COMMON_REG_LIST_BASE(id), \ + SR(DAC_ENABLE) #define LE_DCE100_REG_LIST(id)\ LE_COMMON_REG_LIST_BASE(id), \ SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ - SR(DCI_MEM_PWR_STATUS) + SR(DCI_MEM_PWR_STATUS), \ + SR(DAC_ENABLE) #define LE_DCE110_REG_LIST(id)\ LE_COMMON_REG_LIST_BASE(id), \ @@ -181,6 +184,9 @@ struct dce110_link_enc_registers { uint32_t DP_DPHY_BS_SR_SWAP_CNTL; uint32_t DP_DPHY_HBR2_PATTERN_CONTROL; uint32_t DP_SEC_CNTL1; + + /* DAC registers */ + uint32_t DAC_ENABLE; }; struct dce110_link_encoder { @@ -215,10 +221,6 @@ bool dce110_link_encoder_validate_dvi_output( enum signal_type signal, const struct dc_crtc_timing *crtc_timing); -bool dce110_link_encoder_validate_rgb_output( - const struct dce110_link_encoder *enc110, - const struct dc_crtc_timing *crtc_timing); - bool dce110_link_encoder_validate_dp_output( const struct dce110_link_encoder *enc110, const struct dc_crtc_timing *crtc_timing); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index 3856477981c62..85ea219e4fd4f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -225,6 +225,7 @@ static const struct dce110_link_enc_registers link_enc_regs[] = { link_regs(4), link_regs(5), link_regs(6), + { .DAC_ENABLE = mmDAC_ENABLE }, }; #define stream_enc_regs(id)\ @@ -632,7 +633,20 @@ static struct link_encoder *dce100_link_encoder_create( kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); int link_regs_id; - if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) + if (!enc110) + return NULL; + + if (enc_init_data->connector.id == CONNECTOR_ID_VGA) { + dce110_link_encoder_construct(enc110, + enc_init_data, + &link_enc_feature, + &link_enc_regs[ENGINE_ID_DACA], + NULL, + NULL); + return &enc110->base; + } + + if (enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) return NULL; link_regs_id = diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c index 7195f435e3f76..6e89b7020b612 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c @@ -240,7 +240,9 @@ static const struct dce110_link_enc_registers link_enc_regs[] = { link_regs(2), link_regs(3), link_regs(4), - link_regs(5) + link_regs(5), + {0}, + { .DAC_ENABLE = mmDAC_ENABLE }, }; #define stream_enc_regs(id)\ @@ -726,7 +728,20 @@ static struct link_encoder *dce60_link_encoder_create( kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); int link_regs_id; - if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) + if (!enc110) + return NULL; + + if (enc_init_data->connector.id == CONNECTOR_ID_VGA) { + dce110_link_encoder_construct(enc110, + enc_init_data, + &link_enc_feature, + &link_enc_regs[ENGINE_ID_DACA], + NULL, + NULL); + return &enc110->base; + } + + if (enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) return NULL; link_regs_id = diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c index e9b79db37d1be..a1ad7398e39f7 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c @@ -241,6 +241,7 @@ static const struct dce110_link_enc_registers link_enc_regs[] = { link_regs(4), link_regs(5), link_regs(6), + { .DAC_ENABLE = mmDAC_ENABLE }, }; #define stream_enc_regs(id)\ @@ -734,7 +735,20 @@ static struct link_encoder *dce80_link_encoder_create( kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); int link_regs_id; - if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) + if (!enc110) + return NULL; + + if (enc_init_data->connector.id == CONNECTOR_ID_VGA) { + dce110_link_encoder_construct(enc110, + enc_init_data, + &link_enc_feature, + &link_enc_regs[ENGINE_ID_DACA], + NULL, + NULL); + return &enc110->base; + } + + if (enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) return NULL; link_regs_id = From 763f4d6e0cb6d648e2ea0ec126a4f2af86240f09 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:53 +0200 Subject: [PATCH 2397/2653] drm/amd/display: Support DAC in dce110_hwseq MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The dce110_hwseq is used by all DCE hardware, so add the DAC support here. When enabling/disabling a stream for a RGB signal, this will call the VBIOS to enable/disable the DAC. Additionally, when applying the controller context, call SelectCRTC_Source from VBIOS in order to direct the CRTC output to the DAC. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 75 ++++++++++++++++++- 1 file changed, 73 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 6b0566baa2f27..3005115c85051 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -659,6 +659,20 @@ void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) } } +static void +dce110_dac_encoder_control(struct pipe_ctx *pipe_ctx, bool enable) +{ + struct dc_link *link = pipe_ctx->stream->link; + struct dc_bios *bios = link->ctx->dc_bios; + struct bp_encoder_control encoder_control = {0}; + + encoder_control.action = enable ? ENCODER_CONTROL_ENABLE : ENCODER_CONTROL_DISABLE; + encoder_control.engine_id = link->link_enc->analog_engine; + encoder_control.pixel_clock = pipe_ctx->stream->timing.pix_clk_100hz / 10; + + bios->funcs->encoder_control(bios, &encoder_control); +} + void dce110_enable_stream(struct pipe_ctx *pipe_ctx) { enum dc_lane_count lane_count = @@ -689,6 +703,9 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) early_control = lane_count; tg->funcs->set_early_control(tg, early_control); + + if (dc_is_rgb_signal(pipe_ctx->stream->signal)) + dce110_dac_encoder_control(pipe_ctx, true); } static enum bp_result link_transmitter_control( @@ -1176,7 +1193,8 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( pipe_ctx->stream_res.stream_enc); - dc->hwss.disable_audio_stream(pipe_ctx); + if (!dc_is_rgb_signal(pipe_ctx->stream->signal)) + dc->hwss.disable_audio_stream(pipe_ctx); link_hwss->reset_stream_encoder(pipe_ctx); @@ -1196,6 +1214,9 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst, link_enc->transmitter - TRANSMITTER_UNIPHY_A); } + + if (dc_is_rgb_signal(pipe_ctx->stream->signal)) + dce110_dac_encoder_control(pipe_ctx, false); } void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, @@ -1581,6 +1602,51 @@ static enum dc_status dce110_enable_stream_timing( return DC_OK; } +static void +dce110_select_crtc_source(struct pipe_ctx *pipe_ctx) +{ + struct dc_link *link = pipe_ctx->stream->link; + struct dc_bios *bios = link->ctx->dc_bios; + struct bp_crtc_source_select crtc_source_select = {0}; + enum engine_id engine_id = link->link_enc->preferred_engine; + uint8_t bit_depth; + + if (dc_is_rgb_signal(pipe_ctx->stream->signal)) + engine_id = link->link_enc->analog_engine; + + switch (pipe_ctx->stream->timing.display_color_depth) { + case COLOR_DEPTH_UNDEFINED: + bit_depth = 0; + break; + case COLOR_DEPTH_666: + bit_depth = 6; + break; + default: + case COLOR_DEPTH_888: + bit_depth = 8; + break; + case COLOR_DEPTH_101010: + bit_depth = 10; + break; + case COLOR_DEPTH_121212: + bit_depth = 12; + break; + case COLOR_DEPTH_141414: + bit_depth = 14; + break; + case COLOR_DEPTH_161616: + bit_depth = 16; + break; + } + + crtc_source_select.controller_id = CONTROLLER_ID_D0 + pipe_ctx->stream_res.tg->inst; + crtc_source_select.bit_depth = bit_depth; + crtc_source_select.engine_id = engine_id; + crtc_source_select.sink_signal = pipe_ctx->stream->signal; + + bios->funcs->select_crtc_source(bios, &crtc_source_select); +} + enum dc_status dce110_apply_single_controller_ctx_to_hw( struct pipe_ctx *pipe_ctx, struct dc_state *context, @@ -1600,6 +1666,10 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw( hws->funcs.disable_stream_gating(dc, pipe_ctx); } + if (pipe_ctx->stream->signal == SIGNAL_TYPE_RGB) { + dce110_select_crtc_source(pipe_ctx); + } + if (pipe_ctx->stream_res.audio != NULL) { struct audio_output audio_output = {0}; @@ -1679,7 +1749,8 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw( pipe_ctx->stream_res.tg->funcs->set_static_screen_control( pipe_ctx->stream_res.tg, event_triggers, 2); - if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) + if (!dc_is_virtual_signal(pipe_ctx->stream->signal) && + !dc_is_rgb_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( pipe_ctx->stream_res.stream_enc, pipe_ctx->stream_res.tg->inst); From 68e29e7bace972b8ace7de2df7153404c2a93150 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:54 +0200 Subject: [PATCH 2398/2653] drm/amd/display: Add analog link detection (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Analog displays typically have a DDC connection which can be used by the GPU to read EDID. This commit adds the capability to probe analog displays using DDC, reading the EDID header and deciding whether the analog link is connected based on the data that was read. Note that VGA has no HPD (hotplug detection), so we need to to do analog link detection for VGA before checking HPD. In case of DVI-I, while the connector supports HPD, not all analog cables connect the HPD pins, so we can't rely on HPD either. For reference, see the legacy display code: amdgpu_connector_vga_detect amdgpu_display_ddc_probe DAC load detection will be implemented in a separate commit. v2: Fix crash / black screen on newer GPUs during link detection. Ignore HPD pin for analog connectors. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- .../amd/display/dc/link/hwss/link_hwss_dio.c | 16 ++-- .../drm/amd/display/dc/link/link_detection.c | 86 ++++++++++++++++++- .../gpu/drm/amd/display/dc/link/link_dpms.c | 3 + .../drm/amd/display/dc/link/link_factory.c | 3 + 4 files changed, 101 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c index 80344cbd1f995..befa67b2b2ae0 100644 --- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c +++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c @@ -58,8 +58,9 @@ void setup_dio_stream_encoder(struct pipe_ctx *pipe_ctx) return; } - link_enc->funcs->connect_dig_be_to_fe(link_enc, - pipe_ctx->stream_res.stream_enc->id, true); + if (!dc_is_rgb_signal(pipe_ctx->stream->signal)) + link_enc->funcs->connect_dig_be_to_fe(link_enc, + pipe_ctx->stream_res.stream_enc->id, true); if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_BE); @@ -98,10 +99,13 @@ void reset_dio_stream_encoder(struct pipe_ctx *pipe_ctx) if (stream_enc->funcs->enable_stream) stream_enc->funcs->enable_stream(stream_enc, pipe_ctx->stream->signal, false); - link_enc->funcs->connect_dig_be_to_fe( - link_enc, - pipe_ctx->stream_res.stream_enc->id, - false); + + if (!dc_is_rgb_signal(pipe_ctx->stream->signal)) + link_enc->funcs->connect_dig_be_to_fe( + link_enc, + pipe_ctx->stream_res.stream_enc->id, + false); + if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence( pipe_ctx->stream->link, diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index 801c94efa7fca..d83fd52cb1b0a 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -862,6 +862,48 @@ static void verify_link_capability(struct dc_link *link, struct dc_sink *sink, verify_link_capability_non_destructive(link); } +/** + * link_detect_evaluate_edid_header() - Evaluate if an EDID header is acceptable. + * + * Evaluates an 8-byte EDID header to check if it's good enough + * for the purpose of determining whether a display is connected + * without reading the full EDID. + */ +static bool link_detect_evaluate_edid_header(uint8_t edid_header[8]) +{ + int edid_header_score = 0; + int i; + + for (i = 0; i < 8; ++i) + edid_header_score += edid_header[i] == ((i == 0 || i == 7) ? 0x00 : 0xff); + + return edid_header_score >= 6; +} + +/** + * link_detect_ddc_probe() - Probe the DDC to see if a display is connected. + * + * Detect whether a display is connected to DDC without reading full EDID. + * Reads only the EDID header (the first 8 bytes of EDID) from DDC and + * evaluates whether that matches. + */ +static bool link_detect_ddc_probe(struct dc_link *link) +{ + if (!link->ddc) + return false; + + uint8_t edid_header[8] = {0}; + bool ddc_probed = i2c_read(link->ddc, 0x50, edid_header, sizeof(edid_header)); + + if (!ddc_probed) + return false; + + if (!link_detect_evaluate_edid_header(edid_header)) + return false; + + return true; +} + /* * detect_link_and_local_sink() - Detect if a sink is attached to a given link * @@ -946,6 +988,12 @@ static bool detect_link_and_local_sink(struct dc_link *link, break; } + case SIGNAL_TYPE_RGB: { + sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; + sink_caps.signal = SIGNAL_TYPE_RGB; + break; + } + case SIGNAL_TYPE_LVDS: { sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; sink_caps.signal = SIGNAL_TYPE_LVDS; @@ -1139,9 +1187,17 @@ static bool detect_link_and_local_sink(struct dc_link *link, sink = prev_sink; prev_sink = NULL; } - query_hdcp_capability(sink->sink_signal, link); + + if (!sink->edid_caps.analog) + query_hdcp_capability(sink->sink_signal, link); } + /* DVI-I connector connected to analog display. */ + if ((link->link_id.id == CONNECTOR_ID_DUAL_LINK_DVII || + link->link_id.id == CONNECTOR_ID_SINGLE_LINK_DVII) && + sink->edid_caps.analog) + sink->sink_signal = SIGNAL_TYPE_RGB; + /* HDMI-DVI Dongle */ if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A && !sink->edid_caps.edid_hdmi) @@ -1238,6 +1294,23 @@ static bool detect_link_and_local_sink(struct dc_link *link, return true; } +/** + * link_detect_analog() - Determines if an analog sink is connected. + */ +static bool link_detect_analog(struct dc_link *link, enum dc_connection_type *type) +{ + /* Don't care about connectors that don't support an analog signal. */ + ASSERT(dc_connector_supports_analog(link->link_id.id)); + + if (link_detect_ddc_probe(link)) { + *type = dc_connection_single; + return true; + } + + *type = dc_connection_none; + return true; +} + /* * link_detect_connection_type() - Determine if there is a sink connected * @@ -1254,6 +1327,17 @@ bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type * return true; } + /* Ignore the HPD pin (if any) for analog connectors. + * Instead rely on DDC. + * + * - VGA connectors don't have any HPD at all. + * - Some DVI-A cables don't connect the HPD pin. + * - Some DVI-A cables pull up the HPD pin. + * (So it's high even when no display is connected.) + */ + if (dc_connector_supports_analog(link->link_id.id)) + return link_detect_analog(link, type); + if (link->connector_signal == SIGNAL_TYPE_EDP) { /*in case it is not on*/ if (!link->dc->config.edp_no_power_sequencing) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index 3407331527313..8fd41d21a5d1f 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -2340,6 +2340,9 @@ static enum dc_status enable_link( enable_link_lvds(pipe_ctx); status = DC_OK; break; + case SIGNAL_TYPE_RGB: + status = DC_OK; + break; case SIGNAL_TYPE_VIRTUAL: status = enable_link_virtual(pipe_ctx); break; diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c index ebc3798e7d25d..7989baf3843c9 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@ -583,6 +583,9 @@ static bool construct_phy(struct dc_link *link, case CONNECTOR_ID_DUAL_LINK_DVII: link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK; break; + case CONNECTOR_ID_VGA: + link->connector_signal = SIGNAL_TYPE_RGB; + break; case CONNECTOR_ID_DISPLAY_PORT: case CONNECTOR_ID_MXM: case CONNECTOR_ID_USBC: From 1b0b939c19d87346948d46ea7ffd94e906217c52 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:55 +0200 Subject: [PATCH 2399/2653] drm/amd/display: Refactor amdgpu_dm_connector_detect (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Prepare for polling analog connectors. Document the function better. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 35 ++++++++++--------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 42afa9a13711e..5d588569eaebf 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7346,29 +7346,32 @@ create_stream_for_sink(struct drm_connector *connector, return stream; } +/** + * amdgpu_dm_connector_detect() - Detect whether a DRM connector is connected to a display + * + * A connector is considered connected when it has a sink that is not NULL. + * For connectors that support HPD (hotplug detection), the connection is + * handled in the HPD interrupt. + * + * Notes: + * 1. This interface is NOT called in context of HPD irq. + * 2. This interface *is called* in context of user-mode ioctl. Which + * makes it a bad place for *any* MST-related activity. + */ static enum drm_connector_status amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) { - bool connected; struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); - /* - * Notes: - * 1. This interface is NOT called in context of HPD irq. - * 2. This interface *is called* in context of user-mode ioctl. Which - * makes it a bad place for *any* MST-related activity. - */ - - if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && - !aconnector->fake_enable) - connected = (aconnector->dc_sink != NULL); - else - connected = (aconnector->base.force == DRM_FORCE_ON || - aconnector->base.force == DRM_FORCE_ON_DIGITAL); - update_subconnector_property(aconnector); - return (connected ? connector_status_connected : + if (aconnector->base.force == DRM_FORCE_ON || + aconnector->base.force == DRM_FORCE_ON_DIGITAL) + return connector_status_connected; + else if (aconnector->base.force == DRM_FORCE_OFF) + return connector_status_disconnected; + + return (aconnector->dc_sink ? connector_status_connected : connector_status_disconnected); } From a410191b77b24b0230c07a3f0a642b750131e239 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:56 +0200 Subject: [PATCH 2400/2653] drm/amd/display: Poll analog connectors (v3) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit VGA connectors don't support any hotplug detection, so the kernel needs to periodically poll them to see if a display is connected. DVI-I connectors have hotplug detection for digital signals, and some analog DVI cables pull up that pin to work with that. However, in general not all DVI cables do this so we can't rely on this feature, therefore we need to poll DVI-I connectors as well. v2: Call drm_kms_helper_poll_fini in amdgpu_dm_hpd_fini. Disable/enable polling on suspend/resume. Don't call full link detection when already connected. v3: Encounter CLANG build failure. Remove unused variable: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_irq.c:980:7: error: variable 'use_polling' set but not used [-Werror,-Wunused-but- set-variable] 980 | bool use_polling = false; Signed-off-by: Timur Kristóf Signed-off-by: Wayne Lin Reviewed-by: Harry Wentland --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 73 ++++++++++++++++++- .../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 17 +++++ 2 files changed, 88 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5d588569eaebf..310774246c6ef 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3893,7 +3893,9 @@ void amdgpu_dm_update_connector_after_detect( drm_dbg_kms(dev, "DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", aconnector->connector_id, aconnector->dc_sink, sink); - guard(mutex)(&dev->mode_config.mutex); + /* When polling, DRM has already locked the mutex for us. */ + if (!drm_kms_helper_is_poll_worker()) + mutex_lock(&dev->mode_config.mutex); /* * 1. Update status of the drm connector @@ -3976,6 +3978,10 @@ void amdgpu_dm_update_connector_after_detect( } update_subconnector_property(aconnector); + + /* When polling, the mutex will be unlocked for us by DRM. */ + if (!drm_kms_helper_is_poll_worker()) + mutex_unlock(&dev->mode_config.mutex); } static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) @@ -7346,12 +7352,63 @@ create_stream_for_sink(struct drm_connector *connector, return stream; } +/** + * amdgpu_dm_connector_poll() - Poll a connector to see if it's connected to a display + * + * Used for connectors that don't support HPD (hotplug detection) + * to periodically checked whether the connector is connected to a display. + */ +static enum drm_connector_status +amdgpu_dm_connector_poll(struct amdgpu_dm_connector *aconnector, bool force) +{ + struct drm_connector *connector = &aconnector->base; + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = drm_to_adev(dev); + struct dc_link *link = aconnector->dc_link; + enum dc_connection_type conn_type = dc_connection_none; + enum drm_connector_status status = connector_status_disconnected; + + mutex_lock(&aconnector->hpd_lock); + + if (dc_link_detect_connection_type(aconnector->dc_link, &conn_type) && + conn_type != dc_connection_none) { + mutex_lock(&adev->dm.dc_lock); + + /* Only call full link detection when a sink isn't created yet, + * ie. just when the display is plugged in, otherwise we risk flickering. + */ + if (link->local_sink || + dc_link_detect(link, DETECT_REASON_HPD)) + status = connector_status_connected; + + mutex_unlock(&adev->dm.dc_lock); + } + + if (connector->status != status) { + if (status == connector_status_disconnected) { + if (link->local_sink) + dc_sink_release(link->local_sink); + + link->local_sink = NULL; + link->dpcd_sink_count = 0; + link->type = dc_connection_none; + } + + amdgpu_dm_update_connector_after_detect(aconnector); + } + + mutex_unlock(&aconnector->hpd_lock); + return status; +} + /** * amdgpu_dm_connector_detect() - Detect whether a DRM connector is connected to a display * * A connector is considered connected when it has a sink that is not NULL. * For connectors that support HPD (hotplug detection), the connection is * handled in the HPD interrupt. + * For connectors that may not support HPD, such as analog connectors, + * DRM will call this function repeatedly to poll them. * * Notes: * 1. This interface is NOT called in context of HPD irq. @@ -7371,6 +7428,14 @@ amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) else if (aconnector->base.force == DRM_FORCE_OFF) return connector_status_disconnected; + /* Poll analog connectors and only when either + * disconnected or connected to an analog display. + */ + if (drm_kms_helper_is_poll_worker() && + dc_connector_supports_analog(aconnector->dc_link->link_id.id) && + (!aconnector->dc_sink || aconnector->dc_sink->edid_caps.analog)) + return amdgpu_dm_connector_poll(aconnector, force); + return (aconnector->dc_sink ? connector_status_connected : connector_status_disconnected); } @@ -8942,9 +9007,13 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, link->link_enc->features.dp_ycbcr420_supported ? true : false; break; case DRM_MODE_CONNECTOR_DVID: - case DRM_MODE_CONNECTOR_DVII: aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; break; + case DRM_MODE_CONNECTOR_DVII: + case DRM_MODE_CONNECTOR_VGA: + aconnector->base.polled = + DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; + break; default: break; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index a1c722112c224..0a2a3f233a0e2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -476,6 +476,7 @@ void amdgpu_dm_irq_fini(struct amdgpu_device *adev) void amdgpu_dm_irq_suspend(struct amdgpu_device *adev) { + struct drm_device *dev = adev_to_drm(adev); int src; struct list_head *hnd_list_h; struct list_head *hnd_list_l; @@ -512,6 +513,9 @@ void amdgpu_dm_irq_suspend(struct amdgpu_device *adev) } DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags); + + if (dev->mode_config.poll_enabled) + drm_kms_helper_poll_disable(dev); } void amdgpu_dm_irq_resume_early(struct amdgpu_device *adev) @@ -537,6 +541,7 @@ void amdgpu_dm_irq_resume_early(struct amdgpu_device *adev) void amdgpu_dm_irq_resume_late(struct amdgpu_device *adev) { + struct drm_device *dev = adev_to_drm(adev); int src; struct list_head *hnd_list_h, *hnd_list_l; unsigned long irq_table_flags; @@ -557,6 +562,9 @@ void amdgpu_dm_irq_resume_late(struct amdgpu_device *adev) } DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags); + + if (dev->mode_config.poll_enabled) + drm_kms_helper_poll_enable(dev); } /* @@ -893,6 +901,7 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev) struct drm_connector_list_iter iter; int irq_type; int i; + bool use_polling = false; /* First, clear all hpd and hpdrx interrupts */ for (i = DC_IRQ_SOURCE_HPD1; i <= DC_IRQ_SOURCE_HPD6RX; i++) { @@ -906,6 +915,8 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev) struct amdgpu_dm_connector *amdgpu_dm_connector; const struct dc_link *dc_link; + use_polling |= connector->polled != DRM_CONNECTOR_POLL_HPD; + if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -947,6 +958,9 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev) } } drm_connector_list_iter_end(&iter); + + if (use_polling) + drm_kms_helper_poll_init(dev); } /** @@ -997,4 +1011,7 @@ void amdgpu_dm_hpd_fini(struct amdgpu_device *adev) } } drm_connector_list_iter_end(&iter); + + if (dev->mode_config.poll_enabled) + drm_kms_helper_poll_fini(dev); } From 5e12064d7710acc0d4fbdac1c60f304fff93489e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:57 +0200 Subject: [PATCH 2401/2653] drm/amd/display: Add DCE BIOS_SCRATCH_0 register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The BIOS uses this register to write the results of the DAC_LoadDetection command, so we'll need to read this in order to make DAC load detection work. As a reference, I used the mmBIOS_SCRATCH_0 definition from the amdgpu legacy display code. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dc_bios_types.h | 1 + .../gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c | 2 ++ .../gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c | 2 ++ .../gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c | 2 ++ .../gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c | 1 + drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c | 2 ++ drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c | 2 ++ 7 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h index 545ce1e15eaeb..50c8906b74c59 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h @@ -168,6 +168,7 @@ struct dc_vbios_funcs { }; struct bios_registers { + uint32_t BIOS_SCRATCH_0; uint32_t BIOS_SCRATCH_3; uint32_t BIOS_SCRATCH_6; }; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index 85ea219e4fd4f..d40d91ec2035f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -78,6 +78,7 @@ #endif #ifndef mmBIOS_SCRATCH_2 + #define mmBIOS_SCRATCH_0 0x05C9 #define mmBIOS_SCRATCH_2 0x05CB #define mmBIOS_SCRATCH_3 0x05CC #define mmBIOS_SCRATCH_6 0x05CF @@ -369,6 +370,7 @@ static const struct dce_abm_mask abm_mask = { #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03 static const struct bios_registers bios_regs = { + .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0, .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 }; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c index 9e14ffb3c9428..cd54382c0af3e 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c @@ -82,6 +82,7 @@ #endif #ifndef mmBIOS_SCRATCH_2 + #define mmBIOS_SCRATCH_0 0x05C9 #define mmBIOS_SCRATCH_2 0x05CB #define mmBIOS_SCRATCH_3 0x05CC #define mmBIOS_SCRATCH_6 0x05CF @@ -377,6 +378,7 @@ static const struct dce110_clk_src_mask cs_mask = { }; static const struct bios_registers bios_regs = { + .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0, .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 }; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c index 62977bcdeaa09..3f0a6bc4dcc23 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c @@ -76,6 +76,7 @@ #endif #ifndef mmBIOS_SCRATCH_2 + #define mmBIOS_SCRATCH_0 0x05C9 #define mmBIOS_SCRATCH_2 0x05CB #define mmBIOS_SCRATCH_3 0x05CC #define mmBIOS_SCRATCH_6 0x05CF @@ -385,6 +386,7 @@ static const struct dce110_clk_src_mask cs_mask = { }; static const struct bios_registers bios_regs = { + .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0, .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 }; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c index 0770ea37183f9..b1570b6b1af30 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c @@ -491,6 +491,7 @@ static struct dce_i2c_hw *dce120_i2c_hw_create( return dce_i2c_hw; } static const struct bios_registers bios_regs = { + .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0 + NBIO_BASE(mmBIOS_SCRATCH_0_BASE_IDX), .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX), .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX) }; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c index 6e89b7020b612..f0152933bee2c 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c @@ -80,6 +80,7 @@ #ifndef mmBIOS_SCRATCH_2 + #define mmBIOS_SCRATCH_0 0x05C9 #define mmBIOS_SCRATCH_2 0x05CB #define mmBIOS_SCRATCH_3 0x05CC #define mmBIOS_SCRATCH_6 0x05CF @@ -368,6 +369,7 @@ static const struct dce110_clk_src_mask cs_mask = { }; static const struct bios_registers bios_regs = { + .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0, .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 }; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c index a1ad7398e39f7..8687104cabb72 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c @@ -78,6 +78,7 @@ #ifndef mmBIOS_SCRATCH_2 + #define mmBIOS_SCRATCH_0 0x05C9 #define mmBIOS_SCRATCH_2 0x05CB #define mmBIOS_SCRATCH_3 0x05CC #define mmBIOS_SCRATCH_6 0x05CF @@ -369,6 +370,7 @@ static const struct dce110_clk_src_mask cs_mask = { }; static const struct bios_registers bios_regs = { + .BIOS_SCRATCH_0 = mmBIOS_SCRATCH_0, .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 }; From 873b2eaeb775dcfdace077beec65db2e9796d561 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:58 +0200 Subject: [PATCH 2402/2653] drm/amd/display: Make get_support_mask_for_device_id reusable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This will be reused by DAC load detection. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index 33d0ec38ded71..a126ca3a53fb8 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -67,7 +67,9 @@ static ATOM_HPD_INT_RECORD *get_hpd_record(struct bios_parser *bp, ATOM_OBJECT *object); static struct device_id device_type_from_device_id(uint16_t device_id); static uint32_t signal_to_ss_id(enum as_signal_type signal); -static uint32_t get_support_mask_for_device_id(struct device_id device_id); +static uint32_t get_support_mask_for_device_id( + enum dal_device_type device_type, + uint32_t enum_id); static ATOM_ENCODER_CAP_RECORD_V2 *get_encoder_cap_record( struct bios_parser *bp, ATOM_OBJECT *object); @@ -888,7 +890,7 @@ static bool bios_parser_is_device_id_supported( { struct bios_parser *bp = BP_FROM_DCB(dcb); - uint32_t mask = get_support_mask_for_device_id(id); + uint32_t mask = get_support_mask_for_device_id(id.device_type, id.enum_id); return (le16_to_cpu(bp->object_info_tbl.v1_1->usDeviceSupport) & mask) != 0; } @@ -2179,11 +2181,10 @@ static uint32_t signal_to_ss_id(enum as_signal_type signal) return clk_id_ss; } -static uint32_t get_support_mask_for_device_id(struct device_id device_id) +static uint32_t get_support_mask_for_device_id( + enum dal_device_type device_type, + uint32_t enum_id) { - enum dal_device_type device_type = device_id.device_type; - uint32_t enum_id = device_id.enum_id; - switch (device_type) { case DEVICE_TYPE_LCD: switch (enum_id) { From ba0c64812d88b9585ea90519f3bea363b308e918 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:01:59 +0200 Subject: [PATCH 2403/2653] drm/amd/display: Add DAC_LoadDetection to BIOS parser (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DAC_LoadDetection can be used to determine whether something is connected to an analog connector by determining if there is an analog load. This causes visible flickering on displays, so we only resort to using this when the connected display doesn't have an EDID. For reference, see the legacy display code: amdgpu_atombios_encoder_dac_load_detect v2: Only clear corresponding bit from BIOS_SCRATCH_0. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- .../gpu/drm/amd/display/dc/bios/bios_parser.c | 50 ++++++++++ .../drm/amd/display/dc/bios/command_table.c | 92 +++++++++++++++++++ .../drm/amd/display/dc/bios/command_table.h | 3 + .../gpu/drm/amd/display/dc/dc_bios_types.h | 5 + .../amd/display/include/bios_parser_types.h | 5 + 5 files changed, 155 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index a126ca3a53fb8..4120d6c4c5e45 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -780,6 +780,54 @@ static enum bp_result bios_parser_encoder_control( return bp->cmd_tbl.dig_encoder_control(bp, cntl); } +static enum bp_result bios_parser_dac_load_detection( + struct dc_bios *dcb, + enum engine_id engine_id, + enum dal_device_type device_type, + uint32_t enum_id) +{ + struct bios_parser *bp = BP_FROM_DCB(dcb); + struct dc_context *ctx = dcb->ctx; + struct bp_load_detection_parameters bp_params = {0}; + enum bp_result bp_result; + uint32_t bios_0_scratch; + uint32_t device_id_mask = 0; + + bp_params.engine_id = engine_id; + bp_params.device_id = get_support_mask_for_device_id(device_type, enum_id); + + if (engine_id != ENGINE_ID_DACA && + engine_id != ENGINE_ID_DACB) + return BP_RESULT_UNSUPPORTED; + + if (!bp->cmd_tbl.dac_load_detection) + return BP_RESULT_UNSUPPORTED; + + if (bp_params.device_id == ATOM_DEVICE_CRT1_SUPPORT) + device_id_mask = ATOM_S0_CRT1_MASK; + else if (bp_params.device_id == ATOM_DEVICE_CRT1_SUPPORT) + device_id_mask = ATOM_S0_CRT2_MASK; + else + return BP_RESULT_UNSUPPORTED; + + /* BIOS will write the detected devices to BIOS_SCRATCH_0, clear corresponding bit */ + bios_0_scratch = dm_read_reg(ctx, bp->base.regs->BIOS_SCRATCH_0); + bios_0_scratch &= ~device_id_mask; + dm_write_reg(ctx, bp->base.regs->BIOS_SCRATCH_0, bios_0_scratch); + + bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params); + + if (bp_result != BP_RESULT_OK) + return bp_result; + + bios_0_scratch = dm_read_reg(ctx, bp->base.regs->BIOS_SCRATCH_0); + + if (bios_0_scratch & device_id_mask) + return BP_RESULT_OK; + + return BP_RESULT_FAILURE; +} + static enum bp_result bios_parser_adjust_pixel_clock( struct dc_bios *dcb, struct bp_adjust_pixel_clock_parameters *bp_params) @@ -2864,6 +2912,8 @@ static const struct dc_vbios_funcs vbios_funcs = { .encoder_control = bios_parser_encoder_control, + .dac_load_detection = bios_parser_dac_load_detection, + .transmitter_control = bios_parser_transmitter_control, .enable_crtc = bios_parser_enable_crtc, diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c index dbd84477ceb7d..22457f417e65c 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c @@ -54,6 +54,7 @@ static void init_enable_spread_spectrum_on_ppll(struct bios_parser *bp); static void init_adjust_display_pll(struct bios_parser *bp); static void init_select_crtc_source(struct bios_parser *bp); static void init_dac_encoder_control(struct bios_parser *bp); +static void init_dac_load_detection(struct bios_parser *bp); static void init_dac_output_control(struct bios_parser *bp); static void init_set_crtc_timing(struct bios_parser *bp); static void init_enable_crtc(struct bios_parser *bp); @@ -72,6 +73,7 @@ void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp) init_adjust_display_pll(bp); init_select_crtc_source(bp); init_dac_encoder_control(bp); + init_dac_load_detection(bp); init_dac_output_control(bp); init_set_crtc_timing(bp); init_enable_crtc(bp); @@ -1902,6 +1904,96 @@ static enum bp_result dac2_encoder_control_v1( return result; } +/******************************************************************************* + ******************************************************************************** + ** + ** DAC LOAD DETECTION + ** + ******************************************************************************** + *******************************************************************************/ + +static enum bp_result dac_load_detection_v1( + struct bios_parser *bp, + struct bp_load_detection_parameters *bp_params); + +static enum bp_result dac_load_detection_v3( + struct bios_parser *bp, + struct bp_load_detection_parameters *bp_params); + +static void init_dac_load_detection(struct bios_parser *bp) +{ + switch (BIOS_CMD_TABLE_PARA_REVISION(DAC_LoadDetection)) { + case 1: + case 2: + bp->cmd_tbl.dac_load_detection = dac_load_detection_v1; + break; + case 3: + default: + bp->cmd_tbl.dac_load_detection = dac_load_detection_v3; + break; + } +} + +static void dac_load_detect_prepare_params( + struct _DAC_LOAD_DETECTION_PS_ALLOCATION *params, + enum engine_id engine_id, + uint16_t device_id, + uint8_t misc) +{ + uint8_t dac_type = ENGINE_ID_DACA; + + if (engine_id == ENGINE_ID_DACB) + dac_type = ATOM_DAC_B; + + params->sDacload.usDeviceID = cpu_to_le16(device_id); + params->sDacload.ucDacType = dac_type; + params->sDacload.ucMisc = misc; +} + +static enum bp_result dac_load_detection_v1( + struct bios_parser *bp, + struct bp_load_detection_parameters *bp_params) +{ + enum bp_result result = BP_RESULT_FAILURE; + DAC_LOAD_DETECTION_PS_ALLOCATION params; + + dac_load_detect_prepare_params( + ¶ms, + bp_params->engine_id, + bp_params->device_id, + 0); + + if (EXEC_BIOS_CMD_TABLE(DAC_LoadDetection, params)) + result = BP_RESULT_OK; + + return result; +} + +static enum bp_result dac_load_detection_v3( + struct bios_parser *bp, + struct bp_load_detection_parameters *bp_params) +{ + enum bp_result result = BP_RESULT_FAILURE; + DAC_LOAD_DETECTION_PS_ALLOCATION params; + + uint8_t misc = 0; + + if (bp_params->device_id == ATOM_DEVICE_CV_SUPPORT || + bp_params->device_id == ATOM_DEVICE_TV1_SUPPORT) + misc = DAC_LOAD_MISC_YPrPb; + + dac_load_detect_prepare_params( + ¶ms, + bp_params->engine_id, + bp_params->device_id, + misc); + + if (EXEC_BIOS_CMD_TABLE(DAC_LoadDetection, params)) + result = BP_RESULT_OK; + + return result; +} + /******************************************************************************* ******************************************************************************** ** diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.h b/drivers/gpu/drm/amd/display/dc/bios/command_table.h index 8b04b903e93d0..e89b1ba0048b9 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.h +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.h @@ -71,6 +71,9 @@ struct cmd_tbl { enum bp_result (*dac2_output_control)( struct bios_parser *bp, bool enable); + enum bp_result (*dac_load_detection)( + struct bios_parser *bp, + struct bp_load_detection_parameters *bp_params); enum bp_result (*set_crtc_timing)( struct bios_parser *bp, struct bp_hw_crtc_timing_parameters *bp_params); diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h index 50c8906b74c59..40d7a7d83c406 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h @@ -97,6 +97,11 @@ struct dc_vbios_funcs { enum bp_result (*encoder_control)( struct dc_bios *bios, struct bp_encoder_control *cntl); + enum bp_result (*dac_load_detection)( + struct dc_bios *bios, + enum engine_id engine_id, + enum dal_device_type device_type, + uint32_t enum_id); enum bp_result (*transmitter_control)( struct dc_bios *bios, struct bp_transmitter_control *cntl); diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h index d9e58a6a0d369..973b6bdbac63e 100644 --- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h +++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h @@ -162,6 +162,11 @@ struct bp_transmitter_control { bool single_pll_mode; }; +struct bp_load_detection_parameters { + enum engine_id engine_id; + uint16_t device_id; +}; + struct bp_hw_crtc_timing_parameters { enum controller_id controller_id; /* horizontal part */ From 27a74faf949d4789f789ad3a48bec6069fbb46a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:02:00 +0200 Subject: [PATCH 2404/2653] drm/amd/display: Use DAC load detection on analog connectors (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This feature is useful for analog connections without EDID: - Really old monitors with a VGA connector - Cheap DVI/VGA adapters that don't connect DDC pins When a connection is established through DAC load detection, the driver is supposed to fill in the supported modes for the display, which we already do in amdgpu_dm_connector_get_modes. Also, because the load detection causes visible glitches, do not attempt to poll the connector again after it was detected this way. Note that it will still be polled after sleep/resume or when force is enabled, which is okay. v2: Add dc_connection_dac_load connection type. Properly release sink when no display is connected. Don't print error when EDID isn't read from an analog display. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +++ drivers/gpu/drm/amd/display/dc/dc_types.h | 3 +- .../drm/amd/display/dc/link/link_detection.c | 61 ++++++++++++++++++- 3 files changed, 72 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 310774246c6ef..970657e94f93e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7368,6 +7368,16 @@ amdgpu_dm_connector_poll(struct amdgpu_dm_connector *aconnector, bool force) enum dc_connection_type conn_type = dc_connection_none; enum drm_connector_status status = connector_status_disconnected; + /* When we determined the connection using DAC load detection, + * do NOT poll the connector do detect disconnect because + * that would run DAC load detection again which can cause + * visible visual glitches. + * + * Only allow to poll such a connector again when forcing. + */ + if (!force && link->local_sink && link->type == dc_connection_dac_load) + return connector->status; + mutex_lock(&aconnector->hpd_lock); if (dc_link_detect_connection_type(aconnector->dc_link, &conn_type) && diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 9989c8af5174a..ea6b71c43d2c8 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -353,7 +353,8 @@ enum dc_connection_type { dc_connection_none, dc_connection_single, dc_connection_mst_branch, - dc_connection_sst_branch + dc_connection_sst_branch, + dc_connection_dac_load }; struct dc_csc_adjustments { diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index d83fd52cb1b0a..c417780f37bca 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -904,6 +904,37 @@ static bool link_detect_ddc_probe(struct dc_link *link) return true; } +/** + * link_detect_dac_load_detect() - Performs DAC load detection. + * + * Load detection can be used to detect the presence of an + * analog display when we can't read DDC. This causes a visible + * visual glitch so it should be used sparingly. + */ +static bool link_detect_dac_load_detect(struct dc_link *link) +{ + struct dc_bios *bios = link->ctx->dc_bios; + struct link_encoder *link_enc = link->link_enc; + enum engine_id engine_id = link_enc->preferred_engine; + enum dal_device_type device_type = DEVICE_TYPE_CRT; + enum bp_result bp_result; + uint32_t enum_id; + + switch (engine_id) { + case ENGINE_ID_DACB: + enum_id = 2; + break; + case ENGINE_ID_DACA: + default: + engine_id = ENGINE_ID_DACA; + enum_id = 1; + break; + } + + bp_result = bios->funcs->dac_load_detection(bios, engine_id, device_type, enum_id); + return bp_result == BP_RESULT_OK; +} + /* * detect_link_and_local_sink() - Detect if a sink is attached to a given link * @@ -1118,7 +1149,30 @@ static bool detect_link_and_local_sink(struct dc_link *link, DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n"); break; case EDID_NO_RESPONSE: + /* Analog connectors without EDID: + * - old monitor that actually doesn't have EDID + * - cheap DVI-A cable or adapter that doesn't connect DDC + */ + if (dc_connector_supports_analog(link->link_id.id)) { + /* If we didn't do DAC load detection yet, do it now + * to verify there really is a display connected. + */ + if (link->type != dc_connection_dac_load && + !link_detect_dac_load_detect(link)) { + if (prev_sink) + dc_sink_release(prev_sink); + link_disconnect_sink(link); + return false; + } + + DC_LOG_INFO("%s detected analog display without EDID\n", __func__); + link->type = dc_connection_dac_load; + sink->edid_caps.analog = true; + break; + } + DC_LOG_ERROR("No EDID read.\n"); + /* * Abort detection for non-DP connectors if we have * no EDID @@ -1307,6 +1361,11 @@ static bool link_detect_analog(struct dc_link *link, enum dc_connection_type *ty return true; } + if (link_detect_dac_load_detect(link)) { + *type = dc_connection_dac_load; + return true; + } + *type = dc_connection_none; return true; } @@ -1328,7 +1387,7 @@ bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type * } /* Ignore the HPD pin (if any) for analog connectors. - * Instead rely on DDC. + * Instead rely on DDC and DAC. * * - VGA connectors don't have any HPD at all. * - Some DVI-A cables don't connect the HPD pin. From 11b66b23294c3c1165dbbb499155e98d9f9ededc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:02:01 +0200 Subject: [PATCH 2405/2653] drm/amd/display: Add common modes to analog displays without EDID MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When the EDID of an analog display is not available, we can't know the possible modes supported by the display. However, we still need to offer the user to select from a variety of common modes. It will be up to the user to select the best one, though. This is how it works on other operating systems as well as the legacy display code path in amdgpu. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 46 +++++++++++-------- 1 file changed, 28 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 970657e94f93e..b6bad1ac363fe 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8635,7 +8635,7 @@ static void amdgpu_dm_get_native_mode(struct drm_connector *connector) static struct drm_display_mode * amdgpu_dm_create_common_mode(struct drm_encoder *encoder, - char *name, + const char *name, int hdisplay, int vdisplay) { struct drm_device *dev = encoder->dev; @@ -8658,6 +8658,24 @@ amdgpu_dm_create_common_mode(struct drm_encoder *encoder, } +static const struct amdgpu_dm_mode_size { + char name[DRM_DISPLAY_MODE_LEN]; + int w; + int h; +} common_modes[] = { + { "640x480", 640, 480}, + { "800x600", 800, 600}, + { "1024x768", 1024, 768}, + { "1280x720", 1280, 720}, + { "1280x800", 1280, 800}, + {"1280x1024", 1280, 1024}, + { "1440x900", 1440, 900}, + {"1680x1050", 1680, 1050}, + {"1600x1200", 1600, 1200}, + {"1920x1080", 1920, 1080}, + {"1920x1200", 1920, 1200} +}; + static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, struct drm_connector *connector) { @@ -8668,23 +8686,6 @@ static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, to_amdgpu_dm_connector(connector); int i; int n; - struct mode_size { - char name[DRM_DISPLAY_MODE_LEN]; - int w; - int h; - } common_modes[] = { - { "640x480", 640, 480}, - { "800x600", 800, 600}, - { "1024x768", 1024, 768}, - { "1280x720", 1280, 720}, - { "1280x800", 1280, 800}, - {"1280x1024", 1280, 1024}, - { "1440x900", 1440, 900}, - {"1680x1050", 1680, 1050}, - {"1600x1200", 1600, 1200}, - {"1920x1080", 1920, 1080}, - {"1920x1200", 1920, 1200} - }; if ((connector->connector_type != DRM_MODE_CONNECTOR_eDP) && (connector->connector_type != DRM_MODE_CONNECTOR_LVDS)) @@ -8943,6 +8944,15 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) amdgpu_dm_connector->num_modes += drm_add_modes_noedid(connector, 1920, 1080); + + if (amdgpu_dm_connector->dc_sink->edid_caps.analog) { + /* Analog monitor connected by DAC load detection. + * Add common modes. It will be up to the user to select one that works. + */ + for (int i = 0; i < ARRAY_SIZE(common_modes); i++) + amdgpu_dm_connector->num_modes += drm_add_modes_noedid( + connector, common_modes[i].w, common_modes[i].h); + } } else { #ifdef HAVE_DRM_DP_MST_EDID_READ amdgpu_dm_connector_ddc_get_modes(connector, drm_edid); From b0f1942810a0db935f4b26d31e0bd6726b58ea3d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:02:02 +0200 Subject: [PATCH 2406/2653] drm/amd/display: Don't add freesync modes to analog displays (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit VRR is not supported on analog signals. Don't add freesync modes to analog displays or when VRR is unsupported by DC. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b6bad1ac363fe..b234d7c96429a 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8913,6 +8913,10 @@ static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connect #endif return; + if (!amdgpu_dm_connector->dc_sink || amdgpu_dm_connector->dc_sink->edid_caps.analog || + !dc_supports_vrr(amdgpu_dm_connector->dc_sink->ctx->dce_version)) + return; + if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) amdgpu_dm_connector->num_modes += add_fs_modes(amdgpu_dm_connector); From 99f33a435e6c43fc8e69549136a0a4cb8f052487 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:02:03 +0200 Subject: [PATCH 2407/2653] drm/amdgpu: Use DC by default for Bonaire MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that DC supports analog connectors, there is nothing stopping us from using it by default on Bonaire. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 41dfc031feb3e..3dced3db91db8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4240,7 +4240,6 @@ bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, #else return false; #endif - case CHIP_BONAIRE: case CHIP_KAVERI: case CHIP_KABINI: case CHIP_MULLINS: From 01a06591faf403333201e850a77c74187af74d1a Mon Sep 17 00:00:00 2001 From: Sunday Clement Date: Fri, 17 Oct 2025 10:15:50 -0400 Subject: [PATCH 2408/2653] drm/amdkfd: Fix Unchecked Return Value Properly check the return values for function, as done elsewhere. Signed-off-by: Sunday Clement Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 90a60f16d8080..849297aec8975 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -1952,6 +1952,8 @@ static int start_cpsch(struct device_queue_manager *dqm) static int stop_cpsch(struct device_queue_manager *dqm) { + int ret = 0; + dqm_lock(dqm); if (!dqm->sched_running) { dqm_unlock(dqm); @@ -1959,9 +1961,10 @@ static int stop_cpsch(struct device_queue_manager *dqm) } if (!dqm->dev->kfd->shared_resources.enable_mes) - unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false); + ret = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, + 0, USE_DEFAULT_GRACE_PERIOD, false); else - remove_all_kfd_queues_mes(dqm); + ret = remove_all_kfd_queues_mes(dqm); dqm->sched_running = false; @@ -1975,7 +1978,7 @@ static int stop_cpsch(struct device_queue_manager *dqm) dqm->detect_hang_info = NULL; dqm_unlock(dqm); - return 0; + return ret; } static int create_kernel_queue_cpsch(struct device_queue_manager *dqm, From c5b34adb5a2390d19a81ee426afec4a956a54568 Mon Sep 17 00:00:00 2001 From: "Mario Limonciello (AMD)" Date: Thu, 25 Sep 2025 13:51:07 -0500 Subject: [PATCH 2409/2653] PM: hibernate: Add pm_hibernation_mode_is_suspend() Some drivers have different flows for hibernation and suspend. If the driver opportunistically will skip thaw() then it needs a hint to know what is happening after the hibernate. Introduce a new symbol pm_hibernation_mode_is_suspend() that drivers can call to determine if suspending the system for this purpose. Tested-by: Ionut Nechita Tested-by: Kenneth Crudup Acked-by: Alex Deucher Signed-off-by: Mario Limonciello (AMD) Signed-off-by: Rafael J. Wysocki (cherry picked from commit 495c8d35035edb66e3284113bef01f3b1b843832) --- include/linux/suspend.h | 2 ++ kernel/power/hibernate.c | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/include/linux/suspend.h b/include/linux/suspend.h index 317ae31e89b37..0664c685f0b24 100644 --- a/include/linux/suspend.h +++ b/include/linux/suspend.h @@ -276,6 +276,7 @@ extern void arch_suspend_enable_irqs(void); extern int pm_suspend(suspend_state_t state); extern bool sync_on_suspend_enabled; +bool pm_hibernation_mode_is_suspend(void); #else /* !CONFIG_SUSPEND */ #define suspend_valid_only_mem NULL @@ -288,6 +289,7 @@ static inline bool pm_suspend_via_firmware(void) { return false; } static inline bool pm_resume_via_firmware(void) { return false; } static inline bool pm_suspend_no_platform(void) { return false; } static inline bool pm_suspend_default_s2idle(void) { return false; } +static inline bool pm_hibernation_mode_is_suspend(void) { return false; } static inline void suspend_set_ops(const struct platform_suspend_ops *ops) {} static inline int pm_suspend(suspend_state_t state) { return -ENOSYS; } diff --git a/kernel/power/hibernate.c b/kernel/power/hibernate.c index 1f1f30cca5732..77e5ad02cb548 100644 --- a/kernel/power/hibernate.c +++ b/kernel/power/hibernate.c @@ -80,6 +80,17 @@ static const struct platform_hibernation_ops *hibernation_ops; static atomic_t hibernate_atomic = ATOMIC_INIT(1); +#ifdef CONFIG_SUSPEND +/** + * pm_hibernation_mode_is_suspend - Check if hibernation has been set to suspend + */ +bool pm_hibernation_mode_is_suspend(void) +{ + return hibernation_mode == HIBERNATION_SUSPEND; +} +EXPORT_SYMBOL_GPL(pm_hibernation_mode_is_suspend); +#endif + bool hibernate_acquire(void) { return atomic_add_unless(&hibernate_atomic, -1, 0); From 031b3904cbd2c8c7496f5886490f89f57fe1f896 Mon Sep 17 00:00:00 2001 From: "Mario Limonciello (AMD)" Date: Thu, 25 Sep 2025 13:51:08 -0500 Subject: [PATCH 2410/2653] drm/amd: Fix hybrid sleep [Why] commit 530694f54dd5e ("drm/amdgpu: do not resume device in thaw for normal hibernation") optimized the flow for systems that are going into S4 where the power would be turned off. Basically the thaw() callback wouldn't resume the device if the hibernation image was successfully created since the system would be powered off. This however isn't the correct flow for a system entering into s0i3 after the hibernation image is created. Some of the amdgpu callbacks have different behavior depending upon the intended state of the suspend. [How] Use pm_hibernation_mode_is_suspend() as an input to decide whether to run resume during thaw() callback. Reported-by: Ionut Nechita Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4573 Tested-by: Ionut Nechita Fixes: 530694f54dd5e ("drm/amdgpu: do not resume device in thaw for normal hibernation") Acked-by: Alex Deucher Tested-by: Kenneth Crudup Signed-off-by: Mario Limonciello (AMD) Cc: 6.17+ # 6.17+: 495c8d35035e: PM: hibernate: Add pm_hibernation_mode_is_suspend() Signed-off-by: Rafael J. Wysocki (cherry picked from commit 0a6e9e098fcc318fec0f45a05a5c4743a81a60d9) --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 20ad52c9c288c..609fb7270c7e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2741,7 +2741,7 @@ static int amdgpu_pmops_thaw(struct device *dev) #if defined(HAVE_PM_HIBERNATE_IS_RECOVERING) || !defined(CONFIG_PM_SLEEP) /* do not resume device if it's normal hibernation */ - if (!pm_hibernate_is_recovering()) + if (!pm_hibernate_is_recovering() && !pm_hibernation_mode_is_suspend()) return 0; #endif From 59db155ad84e912d4072ed79834e2f4018ffe97f Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 23 Oct 2025 11:30:16 +0800 Subject: [PATCH 2411/2653] drm/amdkcl: test whether pm_hibernation_mode_is_suspend() is available It's caused by the commit: 1fcbc0b6a8 "drm/amd: Fix hybrid sleep" Signed-off-by: Chengjun Yao Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../dkms/m4/pm_hibernation_mode_is_suspend.m4 | 16 ++++++++++++++++ include/kcl/kcl_suspend.h | 12 ++++++++---- 5 files changed, 29 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pm_hibernation_mode_is_suspend.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 609fb7270c7e6..c20f605c470c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2739,7 +2739,7 @@ static int amdgpu_pmops_thaw(struct device *dev) { struct drm_device *drm_dev = dev_get_drvdata(dev); -#if defined(HAVE_PM_HIBERNATE_IS_RECOVERING) || !defined(CONFIG_PM_SLEEP) +#if defined(HAVE_PM_HIBERNATION_MODE_IS_SUSPEND) || defined(HAVE_PM_HIBERNATE_IS_RECOVERING) /* do not resume device if it's normal hibernation */ if (!pm_hibernate_is_recovering() && !pm_hibernation_mode_is_suspend()) return 0; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ff5f22fac2d20..b7275bfc56889 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1117,6 +1117,9 @@ /* pm_hibernate_is_recovering() is available */ #define HAVE_PM_HIBERNATE_IS_RECOVERING 1 +/* pm_hibernation_mode_is_suspend() is available */ +#define HAVE_PM_HIBERNATION_MODE_IS_SUSPEND 1 + /* pm_runtime_get_if_active() has one parameters */ #define HAVE_PM_RUNTIME_GET_IF_ACTIVE_1ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 98df10ba8eee7..a691bb2d0a0f8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -284,6 +284,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SHMEM_WRITEOUT AC_AMDGPU_KMAP_LOCAL_PAGE_TRY_FROM_PANIC AC_AMDGPU_PM_HIBERNATE_IS_RECOVERING + AC_AMDGPU_PM_HIBERNATION_MODE_IS_SUSPEND AC_AMDGPU_DRM_GEM_IS_IMPORTED AC_AMDGPU_DMA_FENCE_INIT64 AC_AMDGPU_DRM_FILE_DEBUGFS_CLIENT diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_hibernation_mode_is_suspend.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_hibernation_mode_is_suspend.m4 new file mode 100644 index 0000000000000..c160029bddfd1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm_hibernation_mode_is_suspend.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.16-2076-gbed9bcd014c2 +dnl # PM: hibernate: Add pm_hibernation_mode_is_suspend() +dnl # +AC_DEFUN([AC_AMDGPU_PM_HIBERNATION_MODE_IS_SUSPEND], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pm_hibernation_mode_is_suspend(); + ], [ + AC_DEFINE(HAVE_PM_HIBERNATION_MODE_IS_SUSPEND, 1, + [pm_hibernation_mode_is_suspend() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_suspend.h b/include/kcl/kcl_suspend.h index ca37c821757b4..2f46b1d2dc3ee 100644 --- a/include/kcl/kcl_suspend.h +++ b/include/kcl/kcl_suspend.h @@ -17,10 +17,6 @@ static inline void ksys_sync_helper(void) #ifndef HAVE_KSYS_SYNC_HELPER static inline void ksys_sync_helper(void) {} #endif /* HAVE_KSYS_SYNC_HELPER */ - -#ifndef HAVE_PM_HIBERNATE_IS_RECOVERING -static inline bool pm_hibernate_is_recovering(void) { return false; } -#endif #endif /* CONFIG_PM_SLEEP */ #ifndef HAVE_PM_SUSPEND_VIA_FIRMWARE @@ -29,4 +25,12 @@ static inline bool pm_suspend_via_firmware(void) { return false; } static inline bool pm_resume_via_firmware(void) { return false; } #endif /* HAVE_PM_SUSPEND_VIA_FIRMWARE */ +#ifndef HAVE_PM_HIBERNATE_IS_RECOVERING +static inline bool pm_hibernate_is_recovering(void) { return false; } +#endif /* HAVE_PM_HIBERNATE_IS_RECOVERING */ + +#ifndef HAVE_PM_HIBERNATION_MODE_IS_SUSPEND +static inline bool pm_hibernation_mode_is_suspend(void) { return false; } +#endif /* HAVE_PM_HIBERNATEION_MODE_IS_SUSPEND */ + #endif /* AMDKCL_SUSPEND_H */ From 47a0d3cabc4f6759b449f09a434ae209e95d6ce7 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Tue, 28 Oct 2025 17:09:40 +0800 Subject: [PATCH 2412/2653] Bump AMDGPU version to 6.16.9 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 361d3d80c513c..d395c1833b0ef 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.16.8) +AC_INIT(amdgpu-dkms, 6.16.9) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 478f84b8de66e83afc9d853327080d5dd653af76 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 11 Aug 2025 17:30:40 +0530 Subject: [PATCH 2413/2653] drm/amdgpu/pm: Add definition for gpu_metrics v1.9 Add gpu metrics definition which is only a set of gpu metrics attributes. A field is encoded by its id, type and number of instances. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- .../gpu/drm/amd/include/kgd_pp_interface.h | 117 ++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index cb436d470c210..94375cf9ba616 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -541,6 +541,110 @@ struct metrics_table_header { uint8_t content_revision; }; +enum amdgpu_metrics_attr_id { + AMDGPU_METRICS_ATTR_ID_TEMPERATURE_HOTSPOT, + AMDGPU_METRICS_ATTR_ID_TEMPERATURE_MEM, + AMDGPU_METRICS_ATTR_ID_TEMPERATURE_VRSOC, + AMDGPU_METRICS_ATTR_ID_CURR_SOCKET_POWER, + AMDGPU_METRICS_ATTR_ID_AVERAGE_GFX_ACTIVITY, + AMDGPU_METRICS_ATTR_ID_AVERAGE_UMC_ACTIVITY, + AMDGPU_METRICS_ATTR_ID_MEM_MAX_BANDWIDTH, + AMDGPU_METRICS_ATTR_ID_ENERGY_ACCUMULATOR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_CLOCK_COUNTER, + AMDGPU_METRICS_ATTR_ID_ACCUMULATION_COUNTER, + AMDGPU_METRICS_ATTR_ID_PROCHOT_RESIDENCY_ACC, + AMDGPU_METRICS_ATTR_ID_PPT_RESIDENCY_ACC, + AMDGPU_METRICS_ATTR_ID_SOCKET_THM_RESIDENCY_ACC, + AMDGPU_METRICS_ATTR_ID_VR_THM_RESIDENCY_ACC, + AMDGPU_METRICS_ATTR_ID_HBM_THM_RESIDENCY_ACC, + AMDGPU_METRICS_ATTR_ID_GFXCLK_LOCK_STATUS, + AMDGPU_METRICS_ATTR_ID_PCIE_LINK_WIDTH, + AMDGPU_METRICS_ATTR_ID_PCIE_LINK_SPEED, + AMDGPU_METRICS_ATTR_ID_XGMI_LINK_WIDTH, + AMDGPU_METRICS_ATTR_ID_XGMI_LINK_SPEED, + AMDGPU_METRICS_ATTR_ID_GFX_ACTIVITY_ACC, + AMDGPU_METRICS_ATTR_ID_MEM_ACTIVITY_ACC, + AMDGPU_METRICS_ATTR_ID_PCIE_BANDWIDTH_ACC, + AMDGPU_METRICS_ATTR_ID_PCIE_BANDWIDTH_INST, + AMDGPU_METRICS_ATTR_ID_PCIE_L0_TO_RECOV_COUNT_ACC, + AMDGPU_METRICS_ATTR_ID_PCIE_REPLAY_COUNT_ACC, + AMDGPU_METRICS_ATTR_ID_PCIE_REPLAY_ROVER_COUNT_ACC, + AMDGPU_METRICS_ATTR_ID_PCIE_NAK_SENT_COUNT_ACC, + AMDGPU_METRICS_ATTR_ID_PCIE_NAK_RCVD_COUNT_ACC, + AMDGPU_METRICS_ATTR_ID_XGMI_READ_DATA_ACC, + AMDGPU_METRICS_ATTR_ID_XGMI_WRITE_DATA_ACC, + AMDGPU_METRICS_ATTR_ID_XGMI_LINK_STATUS, + AMDGPU_METRICS_ATTR_ID_FIRMWARE_TIMESTAMP, + AMDGPU_METRICS_ATTR_ID_CURRENT_GFXCLK, + AMDGPU_METRICS_ATTR_ID_CURRENT_SOCCLK, + AMDGPU_METRICS_ATTR_ID_CURRENT_VCLK0, + AMDGPU_METRICS_ATTR_ID_CURRENT_DCLK0, + AMDGPU_METRICS_ATTR_ID_CURRENT_UCLK, + AMDGPU_METRICS_ATTR_ID_NUM_PARTITION, + AMDGPU_METRICS_ATTR_ID_PCIE_LC_PERF_OTHER_END_RECOVERY, + AMDGPU_METRICS_ATTR_ID_GFX_BUSY_INST, + AMDGPU_METRICS_ATTR_ID_JPEG_BUSY, + AMDGPU_METRICS_ATTR_ID_VCN_BUSY, + AMDGPU_METRICS_ATTR_ID_GFX_BUSY_ACC, + AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_PPT_ACC, + AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_THM_ACC, + AMDGPU_METRICS_ATTR_ID_GFX_LOW_UTILIZATION_ACC, + AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_TOTAL_ACC, + AMDGPU_METRICS_ATTR_ID_MAX, +}; + +enum amdgpu_metrics_attr_type { + AMDGPU_METRICS_TYPE_U8, + AMDGPU_METRICS_TYPE_S8, + AMDGPU_METRICS_TYPE_U16, + AMDGPU_METRICS_TYPE_S16, + AMDGPU_METRICS_TYPE_U32, + AMDGPU_METRICS_TYPE_S32, + AMDGPU_METRICS_TYPE_U64, + AMDGPU_METRICS_TYPE_S64, + AMDGPU_METRICS_TYPE_MAX, +}; + +enum amdgpu_metrics_attr_unit { + /* None */ + AMDGPU_METRICS_UNIT_NONE, + /* MHz*/ + AMDGPU_METRICS_UNIT_CLOCK_1, + /* Degree Celsius*/ + AMDGPU_METRICS_UNIT_TEMP_1, + /* Watts*/ + AMDGPU_METRICS_UNIT_POWER_1, + /* In nanoseconds*/ + AMDGPU_METRICS_UNIT_TIME_1, + /* In 10 nanoseconds*/ + AMDGPU_METRICS_UNIT_TIME_2, + /* Speed in GT/s */ + AMDGPU_METRICS_UNIT_SPEED_1, + /* Speed in 0.1 GT/s */ + AMDGPU_METRICS_UNIT_SPEED_2, + /* Bandwidth GB/s */ + AMDGPU_METRICS_UNIT_BW_1, + /* Data in KB */ + AMDGPU_METRICS_UNIT_DATA_1, + /* Percentage */ + AMDGPU_METRICS_UNIT_PERCENT, + AMDGPU_METRICS_UNIT_MAX, +}; + +#define AMDGPU_METRICS_ATTR_UNIT_MASK 0xFF000000 +#define AMDGPU_METRICS_ATTR_UNIT_SHIFT 24 +#define AMDGPU_METRICS_ATTR_TYPE_MASK 0x00F00000 +#define AMDGPU_METRICS_ATTR_TYPE_SHIFT 20 +#define AMDGPU_METRICS_ATTR_ID_MASK 0x000FFC00 +#define AMDGPU_METRICS_ATTR_ID_SHIFT 10 +#define AMDGPU_METRICS_ATTR_INST_MASK 0x000003FF +#define AMDGPU_METRICS_ATTR_INST_SHIFT 0 + +#define AMDGPU_METRICS_ENC_ATTR(unit, type, id, inst) \ + (((u64)(unit) << AMDGPU_METRICS_ATTR_UNIT_SHIFT) | \ + ((u64)(type) << AMDGPU_METRICS_ATTR_TYPE_SHIFT) | \ + ((u64)(id) << AMDGPU_METRICS_ATTR_ID_SHIFT) | (inst)) + /* * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. * Use gpu_metrics_v1_1 or later instead. @@ -1230,6 +1334,19 @@ struct gpu_metrics_v1_8 { uint32_t pcie_lc_perf_other_end_recovery; }; +struct gpu_metrics_attr { + /* Field type encoded with AMDGPU_METRICS_ENC_ATTR */ + uint64_t attr_encoding; + /* Attribute value, depends on attr_encoding */ + void *attr_value; +}; + +struct gpu_metrics_v1_9 { + struct metrics_table_header common_header; + int attr_count; + struct gpu_metrics_attr metrics_attrs[]; +}; + /* * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. * Use gpu_metrics_v2_1 or later instead. From 6ff71095eb24faf9211f1ed42995f1722c01e706 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 28 Oct 2025 13:49:24 +0530 Subject: [PATCH 2414/2653] drm/amdkfd: clean up the code to free hmm_range MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit a. hmm_range is either NULL or a valid pointer so we do not need to set range to NULL ever. b. keep the hmm_range_free in the end irrespective of the other conditions to avoid some additional checks and also avoid double free issue. Signed-off-by: Sunil Khatri Reviewed-by: Felix Kuehling Acked-by: Christian König --- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 59e2edcef37a3..52a01b414ce25 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1748,11 +1748,8 @@ static int svm_range_validate_and_map(struct mm_struct *mm, else r = -ENOMEM; WRITE_ONCE(p->svms.faulting_task, NULL); - if (r) { - amdgpu_hmm_range_free(range); - range = NULL; + if (r) pr_debug("failed %d to get svm range pages\n", r); - } } else { r = -EFAULT; } @@ -1775,10 +1772,9 @@ static int svm_range_validate_and_map(struct mm_struct *mm, pr_debug("hmm update the range, need validate again\n"); r = -EAGAIN; } - /* Free the hmm range */ - if (range) - amdgpu_hmm_range_free(range); + /* Free the hmm range */ + amdgpu_hmm_range_free(range); if (!r && !list_empty(&prange->child_list)) { pr_debug("range split by unmap in parallel, validate again\n"); From 0185a22782015faf04e7df3a0dc9841ac71d38f2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 14 Oct 2025 16:45:17 -0400 Subject: [PATCH 2415/2653] drm/amdgpu: set default gfx reset masks for gfx6-8 These were not set so soft recovery was inadvertantly disabled. Fixes: 6ac55eab4fc4 ("drm/amdgpu: move reset support type checks into the caller") Reviewed-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 5 +++++ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 5 +++++ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 7693b79534267..80565392313f1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -3102,6 +3102,11 @@ static int gfx_v6_0_sw_init(struct amdgpu_ip_block *ip_block) return r; } + adev->gfx.gfx_supported_reset = + amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); + adev->gfx.compute_supported_reset = + amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); + return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 00eb3ded8c27f..66a4e4998106f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4400,6 +4400,11 @@ static int gfx_v7_0_sw_init(struct amdgpu_ip_block *ip_block) gfx_v7_0_gpu_early_init(adev); + adev->gfx.gfx_supported_reset = + amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); + adev->gfx.compute_supported_reset = + amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); + return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 12a740f954d0f..58e7a4a2a880e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -2029,6 +2029,11 @@ static int gfx_v8_0_sw_init(struct amdgpu_ip_block *ip_block) if (r) return r; + adev->gfx.gfx_supported_reset = + amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); + adev->gfx.compute_supported_reset = + amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); + return 0; } From 11082ce18db0176f581d7a62e2015fcfc866543c Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Mon, 27 Oct 2025 18:11:52 +0800 Subject: [PATCH 2416/2653] drm/amdgpu: Update invalidate and flush hdp function Update asic_invalidate_hdp and asic_flush_hdp function to check if ip function exist, if not return void v2: Use else/if (Kevin) Update function name (Lijo) Signed-off-by: Asad Kamal Suggested-by: Lijo Lazar Reviewed-by: Yang Wang Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 ++----- drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c | 16 ++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h | 4 ++++ 3 files changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 247fc584429aa..e213d2c4da35c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1567,11 +1567,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) -#define amdgpu_asic_flush_hdp(adev, r) \ - ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) -#define amdgpu_asic_invalidate_hdp(adev, r) \ - ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ - ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) +#define amdgpu_asic_flush_hdp(adev, r) amdgpu_hdp_flush(adev, r) +#define amdgpu_asic_invalidate_hdp(adev, r) amdgpu_hdp_invalidate(adev, r) #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c index 6e02fb9ac2f67..5a60d69a3e1fd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c @@ -66,3 +66,19 @@ void amdgpu_hdp_generic_flush(struct amdgpu_device *adev, 0); } } + +void amdgpu_hdp_invalidate(struct amdgpu_device *adev, struct amdgpu_ring *ring) +{ + if (adev->asic_funcs && adev->asic_funcs->invalidate_hdp) + adev->asic_funcs->invalidate_hdp(adev, ring); + else if (adev->hdp.funcs && adev->hdp.funcs->invalidate_hdp) + adev->hdp.funcs->invalidate_hdp(adev, ring); +} + +void amdgpu_hdp_flush(struct amdgpu_device *adev, struct amdgpu_ring *ring) +{ + if (adev->asic_funcs && adev->asic_funcs->flush_hdp) + adev->asic_funcs->flush_hdp(adev, ring); + else if (adev->hdp.funcs && adev->hdp.funcs->flush_hdp) + adev->hdp.funcs->flush_hdp(adev, ring); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h index 4cfd932b7e91e..d9f488fa76b94 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h @@ -46,4 +46,8 @@ struct amdgpu_hdp { int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev); void amdgpu_hdp_generic_flush(struct amdgpu_device *adev, struct amdgpu_ring *ring); +void amdgpu_hdp_invalidate(struct amdgpu_device *adev, + struct amdgpu_ring *ring); +void amdgpu_hdp_flush(struct amdgpu_device *adev, + struct amdgpu_ring *ring); #endif /* __AMDGPU_HDP_H__ */ From b96d8774326f5226edb43af17e4cfa61c8371669 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 14 Oct 2025 17:01:05 -0400 Subject: [PATCH 2417/2653] drm/amdgpu: move reset debug disable handling Move everything to the supported resets masks rather than having an explicit misc checks for this. Reviewed-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 3 --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 ++- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 3 ++- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 8 ++++++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 3 ++- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 3 ++- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 3 ++- 12 files changed, 32 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 55c7e104d5ca0..fd6aade7ee9e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -130,11 +130,9 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) } /* attempt a per ring reset */ - if (unlikely(adev->debug_disable_gpu_ring_reset)) { - dev_err(adev->dev, "Ring reset disabled by debug mask\n"); - } else if (amdgpu_gpu_recovery && - amdgpu_ring_is_reset_type_supported(ring, AMDGPU_RESET_TYPE_PER_QUEUE) && - ring->funcs->reset) { + if (amdgpu_gpu_recovery && + amdgpu_ring_is_reset_type_supported(ring, AMDGPU_RESET_TYPE_PER_QUEUE) && + ring->funcs->reset) { dev_err(adev->dev, "Starting %s ring reset\n", s_job->sched->name); r = amdgpu_ring_reset(ring, job->vmid, job->hw_fence); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index bf6f1a8827880..9b8add4fc6a34 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -468,9 +468,6 @@ bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, ktime_t deadline; bool ret; - if (unlikely(ring->adev->debug_disable_soft_recovery)) - return false; - deadline = ktime_add_us(ktime_get(), 10000); if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 7e2d47ff7f630..eac4317393dff 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4963,7 +4963,8 @@ static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block) amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); adev->gfx.compute_supported_reset = amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); - if (!amdgpu_sriov_vf(adev)) { + if (!amdgpu_sriov_vf(adev) && + !adev->debug_disable_gpu_ring_reset) { adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 42d914c896232..797d0562431b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -1821,13 +1821,15 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block) case IP_VERSION(11, 0, 3): if ((adev->gfx.me_fw_version >= 2280) && (adev->gfx.mec_fw_version >= 2410) && - !amdgpu_sriov_vf(adev)) { + !amdgpu_sriov_vf(adev) && + !adev->debug_disable_gpu_ring_reset) { adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; } break; default: - if (!amdgpu_sriov_vf(adev)) { + if (!amdgpu_sriov_vf(adev) && + !adev->debug_disable_gpu_ring_reset) { adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 445a569896035..8a424390dcc4c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -1548,7 +1548,8 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) case IP_VERSION(12, 0, 1): if ((adev->gfx.me_fw_version >= 2660) && (adev->gfx.mec_fw_version >= 2920) && - !amdgpu_sriov_vf(adev)) { + !amdgpu_sriov_vf(adev) && + !adev->debug_disable_gpu_ring_reset) { adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 81cd7bdba23f4..0fb95b8e48910 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2416,7 +2416,7 @@ static int gfx_v9_0_sw_init(struct amdgpu_ip_block *ip_block) amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); adev->gfx.compute_supported_reset = amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); - if (!amdgpu_sriov_vf(adev)) + if (!amdgpu_sriov_vf(adev) && !adev->debug_disable_gpu_ring_reset) adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 94273c4f574da..de2212cfa7177 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -1158,14 +1158,16 @@ static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) case IP_VERSION(9, 4, 3): case IP_VERSION(9, 4, 4): if ((adev->gfx.mec_fw_version >= 155) && - !amdgpu_sriov_vf(adev)) { + !amdgpu_sriov_vf(adev) && + !adev->debug_disable_gpu_ring_reset) { adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; } break; case IP_VERSION(9, 5, 0): if ((adev->gfx.mec_fw_version >= 21) && - !amdgpu_sriov_vf(adev)) { + !amdgpu_sriov_vf(adev) && + !adev->debug_disable_gpu_ring_reset) { adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index 36b1ca73c2ed3..a1443990d5c60 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -2361,11 +2361,15 @@ static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev) switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { case IP_VERSION(9, 4, 3): case IP_VERSION(9, 4, 4): - if ((adev->gfx.mec_fw_version >= 0xb0) && amdgpu_dpm_reset_sdma_is_supported(adev)) + if ((adev->gfx.mec_fw_version >= 0xb0) && + amdgpu_dpm_reset_sdma_is_supported(adev) && + !adev->debug_disable_gpu_ring_reset) adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; break; case IP_VERSION(9, 5, 0): - if ((adev->gfx.mec_fw_version >= 0xf) && amdgpu_dpm_reset_sdma_is_supported(adev)) + if ((adev->gfx.mec_fw_version >= 0xf) && + amdgpu_dpm_reset_sdma_is_supported(adev) && + !adev->debug_disable_gpu_ring_reset) adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 7dc67a22a7a01..8ddc4df06a1fd 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1429,7 +1429,8 @@ static int sdma_v5_0_sw_init(struct amdgpu_ip_block *ip_block) case IP_VERSION(5, 0, 2): case IP_VERSION(5, 0, 5): if ((adev->sdma.instance[0].fw_version >= 35) && - !amdgpu_sriov_vf(adev)) + !amdgpu_sriov_vf(adev) && + !adev->debug_disable_gpu_ring_reset) adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 3bd44c24f692d..c6a619514a8ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1348,12 +1348,14 @@ static int sdma_v5_2_sw_init(struct amdgpu_ip_block *ip_block) case IP_VERSION(5, 2, 3): case IP_VERSION(5, 2, 4): if ((adev->sdma.instance[0].fw_version >= 76) && - !amdgpu_sriov_vf(adev)) + !amdgpu_sriov_vf(adev) && + !adev->debug_disable_gpu_ring_reset) adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; break; case IP_VERSION(5, 2, 5): if ((adev->sdma.instance[0].fw_version >= 34) && - !amdgpu_sriov_vf(adev)) + !amdgpu_sriov_vf(adev) && + !adev->debug_disable_gpu_ring_reset) adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 0e2f8cd0b5ceb..37f0f0944d2e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1356,7 +1356,8 @@ static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block) case IP_VERSION(6, 0, 2): case IP_VERSION(6, 0, 3): if ((adev->sdma.instance[0].fw_version >= 21) && - !amdgpu_sriov_vf(adev)) + !amdgpu_sriov_vf(adev) && + !adev->debug_disable_gpu_ring_reset) adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index 64139cbe8fd2d..edbfb1782d84b 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1337,7 +1337,8 @@ static int sdma_v7_0_sw_init(struct amdgpu_ip_block *ip_block) adev->sdma.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); - if (!amdgpu_sriov_vf(adev)) + if (!amdgpu_sriov_vf(adev) && + !adev->debug_disable_gpu_ring_reset) adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; r = amdgpu_sdma_sysfs_reset_mask_init(adev); From 731c47485ca92c7c45358921844ac222c6163f0f Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 28 Oct 2025 17:39:27 +0530 Subject: [PATCH 2418/2653] drm/amdgpu: caller should make sure not to double free MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the NULL check from amdgpu_hmm_range_free for hmm_pfns as caller is responsible not to call amdgpu_hmm_range_free more than once. Signed-off-by: Sunil Khatri Reviewed-by: Christian König Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index df99c4b4c6a11..2ffc6f5fc6fff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -981,11 +981,9 @@ void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range) return; #ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT - if (range->hmm_range.pfns) - kvfree(range->hmm_range.pfns); + kvfree(range->hmm_range.pfns); #else - if (range->hmm_range.hmm_pfns) - kvfree(range->hmm_range.hmm_pfns); + kvfree(range->hmm_range.hmm_pfns); #endif amdgpu_bo_unref(&range->bo); kfree(range); From f027f4436657923bb901b165cf00e0e1ddd4581b Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Wed, 29 Oct 2025 16:42:33 +0800 Subject: [PATCH 2419/2653] Revert "drm/amd/display: Add common modes to analog displays without EDID" This reverts commit 11b66b23294c3c1165dbbb499155e98d9f9ededc. It's caused the Jira ticket: SWDEV-563655, so revert it temporarily. Signed-off-by: Chengjun Yao --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 46 ++++++++----------- 1 file changed, 18 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b234d7c96429a..a1a0dae1e5bef 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8635,7 +8635,7 @@ static void amdgpu_dm_get_native_mode(struct drm_connector *connector) static struct drm_display_mode * amdgpu_dm_create_common_mode(struct drm_encoder *encoder, - const char *name, + char *name, int hdisplay, int vdisplay) { struct drm_device *dev = encoder->dev; @@ -8658,24 +8658,6 @@ amdgpu_dm_create_common_mode(struct drm_encoder *encoder, } -static const struct amdgpu_dm_mode_size { - char name[DRM_DISPLAY_MODE_LEN]; - int w; - int h; -} common_modes[] = { - { "640x480", 640, 480}, - { "800x600", 800, 600}, - { "1024x768", 1024, 768}, - { "1280x720", 1280, 720}, - { "1280x800", 1280, 800}, - {"1280x1024", 1280, 1024}, - { "1440x900", 1440, 900}, - {"1680x1050", 1680, 1050}, - {"1600x1200", 1600, 1200}, - {"1920x1080", 1920, 1080}, - {"1920x1200", 1920, 1200} -}; - static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, struct drm_connector *connector) { @@ -8686,6 +8668,23 @@ static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, to_amdgpu_dm_connector(connector); int i; int n; + struct mode_size { + char name[DRM_DISPLAY_MODE_LEN]; + int w; + int h; + } common_modes[] = { + { "640x480", 640, 480}, + { "800x600", 800, 600}, + { "1024x768", 1024, 768}, + { "1280x720", 1280, 720}, + { "1280x800", 1280, 800}, + {"1280x1024", 1280, 1024}, + { "1440x900", 1440, 900}, + {"1680x1050", 1680, 1050}, + {"1600x1200", 1600, 1200}, + {"1920x1080", 1920, 1080}, + {"1920x1200", 1920, 1200} + }; if ((connector->connector_type != DRM_MODE_CONNECTOR_eDP) && (connector->connector_type != DRM_MODE_CONNECTOR_LVDS)) @@ -8948,15 +8947,6 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) amdgpu_dm_connector->num_modes += drm_add_modes_noedid(connector, 1920, 1080); - - if (amdgpu_dm_connector->dc_sink->edid_caps.analog) { - /* Analog monitor connected by DAC load detection. - * Add common modes. It will be up to the user to select one that works. - */ - for (int i = 0; i < ARRAY_SIZE(common_modes); i++) - amdgpu_dm_connector->num_modes += drm_add_modes_noedid( - connector, common_modes[i].w, common_modes[i].h); - } } else { #ifdef HAVE_DRM_DP_MST_EDID_READ amdgpu_dm_connector_ddc_get_modes(connector, drm_edid); From 37e2be99dd9a0ec8012e8e1f9dee52eb8a2689da Mon Sep 17 00:00:00 2001 From: Xiang Liu Date: Wed, 22 Oct 2025 15:11:42 +0800 Subject: [PATCH 2420/2653] drm/amd/ras: Add CPER ring read for uniras Read CPER raw data from debugfs node "/sys/kernel/debug/dri/*/ amdgpu_ring_cper". Signed-off-by: Xiang Liu Reviewed-by: Tao Zhou Reviewed-by: Yang Wang Change-Id: I01753bf4a1052a22144f6c2758a39d2b91c2212d --- .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 59 +++++++++++++++++++ 2 files changed, 61 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 5a7bf0661dbfb..011fa47480840 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -770,7 +770,8 @@ amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) "Saved bad pages %d reaches threshold value %d\n", control->ras_num_bad_pages, ras->bad_page_cnt_threshold); - if (adev->cper.enabled && amdgpu_cper_generate_bp_threshold_record(adev)) + if (adev->cper.enabled && !amdgpu_uniras_enabled(adev) && + amdgpu_cper_generate_bp_threshold_record(adev)) dev_warn(adev->dev, "fail to generate bad page threshold cper records\n"); if ((amdgpu_bad_page_threshold != -1) && diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 9b8add4fc6a34..6cc22eb947c12 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -33,6 +33,7 @@ #include #include "amdgpu.h" +#include "amdgpu_ras_mgr.h" #include "atom.h" /* @@ -495,6 +496,61 @@ bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, */ #if defined(CONFIG_DEBUG_FS) +static ssize_t amdgpu_ras_cper_debugfs_read(struct file *f, char __user *buf, + size_t size, loff_t *offset) +{ + const uint8_t ring_header_size = 12; + struct amdgpu_ring *ring = file_inode(f)->i_private; + struct ras_cmd_cper_snapshot_req *snapshot_req __free(kfree) = + kzalloc(sizeof(struct ras_cmd_cper_snapshot_req), GFP_KERNEL); + struct ras_cmd_cper_snapshot_rsp *snapshot_rsp __free(kfree) = + kzalloc(sizeof(struct ras_cmd_cper_snapshot_rsp), GFP_KERNEL); + struct ras_cmd_cper_record_req *record_req __free(kfree) = + kzalloc(sizeof(struct ras_cmd_cper_record_req), GFP_KERNEL); + struct ras_cmd_cper_record_rsp *record_rsp __free(kfree) = + kzalloc(sizeof(struct ras_cmd_cper_record_rsp), GFP_KERNEL); + uint8_t *ring_header __free(kfree) = + kzalloc(ring_header_size, GFP_KERNEL); + uint32_t total_cper_num; + uint64_t start_cper_id; + int r; + + if (!snapshot_req || !snapshot_rsp || !record_req || !record_rsp || + !ring_header) + return -ENOMEM; + + if (!(*offset)) { + if (copy_to_user(buf, ring_header, ring_header_size)) + return -EFAULT; + buf += ring_header_size; + } + + r = amdgpu_ras_mgr_handle_ras_cmd(ring->adev, + RAS_CMD__GET_CPER_SNAPSHOT, + snapshot_req, sizeof(struct ras_cmd_cper_snapshot_req), + snapshot_rsp, sizeof(struct ras_cmd_cper_snapshot_rsp)); + if (r || !snapshot_rsp->total_cper_num) + return r; + + start_cper_id = snapshot_rsp->start_cper_id; + total_cper_num = snapshot_rsp->total_cper_num; + + record_req->buf_ptr = (uint64_t)(uintptr_t)buf; + record_req->buf_size = size; + record_req->cper_start_id = start_cper_id + *offset; + record_req->cper_num = total_cper_num; + r = amdgpu_ras_mgr_handle_ras_cmd(ring->adev, RAS_CMD__GET_CPER_RECORD, + record_req, sizeof(struct ras_cmd_cper_record_req), + record_rsp, sizeof(struct ras_cmd_cper_record_rsp)); + if (r) + return r; + + r = *offset ? record_rsp->real_data_size : record_rsp->real_data_size + ring_header_size; + (*offset) += record_rsp->real_cper_num; + + return r; +} + /* Layout of file is 12 bytes consisting of * - rptr * - wptr @@ -511,6 +567,9 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, loff_t i; int r; + if (ring->funcs->type == AMDGPU_RING_TYPE_CPER && amdgpu_uniras_enabled(ring->adev)) + return amdgpu_ras_cper_debugfs_read(f, buf, size, pos); + if (*pos & 3 || size & 3) return -EINVAL; From cecebfc7c88c27bfe073f39ea3b3cd35cb891f91 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Tue, 28 Oct 2025 22:08:28 +0800 Subject: [PATCH 2421/2653] drm/amdgpu: Remove invalidate and flush hdp macros MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove amdgpu_asic_flush_hdp & amdgpu_asic_invalidate_hdp functions and directly use the mapped ones Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 -- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 +- drivers/gpu/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c | 4 ++-- drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c | 4 ++-- drivers/gpu/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c | 4 ++-- drivers/gpu/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c | 8 ++++---- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 6 +++--- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 4 ++-- 11 files changed, 20 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index e213d2c4da35c..8dbe378b53d43 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1567,8 +1567,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) -#define amdgpu_asic_flush_hdp(adev, r) amdgpu_hdp_flush(adev, r) -#define amdgpu_asic_invalidate_hdp(adev, r) amdgpu_hdp_invalidate(adev, r) #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 3dced3db91db8..e475d7eee21f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -7390,7 +7390,7 @@ void amdgpu_device_flush_hdp(struct amdgpu_device *adev, return; } - amdgpu_asic_flush_hdp(adev, ring); + amdgpu_hdp_flush(adev, ring); } void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, @@ -7403,7 +7403,7 @@ void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, if (adev->gmc.xgmi.connected_to_cpu) return; - amdgpu_asic_invalidate_hdp(adev, ring); + amdgpu_hdp_invalidate(adev, ring); } int amdgpu_in_reset(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index c6a619514a8ad..51101b0aa2fab 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -342,7 +342,7 @@ static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; if (ring->me > 1) { - amdgpu_asic_flush_hdp(adev, ring); + amdgpu_hdp_flush(adev, ring); } else { ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c index ac9ec8257f82a..38e19e5cad4d0 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/smu10_smumgr.c @@ -139,7 +139,7 @@ static int smu10_copy_table_from_smc(struct pp_hwmgr *hwmgr, priv->smu_tables.entry[table_id].table_id, NULL); - amdgpu_asic_invalidate_hdp(adev, NULL); + amdgpu_hdp_invalidate(adev, NULL); memcpy(table, (uint8_t *)priv->smu_tables.entry[table_id].table, priv->smu_tables.entry[table_id].size); @@ -164,7 +164,7 @@ static int smu10_copy_table_to_smc(struct pp_hwmgr *hwmgr, memcpy(priv->smu_tables.entry[table_id].table, table, priv->smu_tables.entry[table_id].size); - amdgpu_asic_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetDriverDramAddrHigh, diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c index f9c0f117725dd..0bf1bf5528c27 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega10_smumgr.c @@ -60,7 +60,7 @@ static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr, priv->smu_tables.entry[table_id].table_id, NULL); - amdgpu_asic_invalidate_hdp(adev, NULL); + amdgpu_hdp_invalidate(adev, NULL); memcpy(table, priv->smu_tables.entry[table_id].table, priv->smu_tables.entry[table_id].size); @@ -90,7 +90,7 @@ static int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr, memcpy(priv->smu_tables.entry[table_id].table, table, priv->smu_tables.entry[table_id].size); - amdgpu_asic_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetDriverDramAddrHigh, diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c index d3ff6a831ed5d..e2ba593faa5d7 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega12_smumgr.c @@ -68,7 +68,7 @@ static int vega12_copy_table_from_smc(struct pp_hwmgr *hwmgr, "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!", return -EINVAL); - amdgpu_asic_invalidate_hdp(adev, NULL); + amdgpu_hdp_invalidate(adev, NULL); memcpy(table, priv->smu_tables.entry[table_id].table, priv->smu_tables.entry[table_id].size); @@ -98,7 +98,7 @@ static int vega12_copy_table_to_smc(struct pp_hwmgr *hwmgr, memcpy(priv->smu_tables.entry[table_id].table, table, priv->smu_tables.entry[table_id].size); - amdgpu_asic_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetDriverDramAddrHigh, diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c index a5c95b1806729..e3515156d26f7 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/vega20_smumgr.c @@ -192,7 +192,7 @@ static int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr, "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!", return ret); - amdgpu_asic_invalidate_hdp(adev, NULL); + amdgpu_hdp_invalidate(adev, NULL); memcpy(table, priv->smu_tables.entry[table_id].table, priv->smu_tables.entry[table_id].size); @@ -223,7 +223,7 @@ static int vega20_copy_table_to_smc(struct pp_hwmgr *hwmgr, memcpy(priv->smu_tables.entry[table_id].table, table, priv->smu_tables.entry[table_id].size); - amdgpu_asic_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetDriverDramAddrHigh, @@ -256,7 +256,7 @@ int vega20_set_activity_monitor_coeff(struct pp_hwmgr *hwmgr, memcpy(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table, table, priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].size); - amdgpu_asic_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetDriverDramAddrHigh, @@ -306,7 +306,7 @@ int vega20_get_activity_monitor_coeff(struct pp_hwmgr *hwmgr, "[GetActivityMonitor] Attempt to Transfer Table From SMU Failed!", return ret); - amdgpu_asic_invalidate_hdp(adev, NULL); + amdgpu_hdp_invalidate(adev, NULL); memcpy(table, priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table, priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].size); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index bbf09aec91525..7c9f77124ab26 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -2889,7 +2889,7 @@ static int navi10_set_dummy_pstates_table_location(struct smu_context *smu) dummy_table += 0x1000; } - amdgpu_asic_flush_hdp(smu->adev, NULL); + amdgpu_hdp_flush(smu->adev, NULL); ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index cb3fea9e8cf31..a0c844bf852cc 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -449,7 +449,7 @@ static int smu_v13_0_12_get_system_metrics_table(struct smu_context *smu) return ret; } - amdgpu_asic_invalidate_hdp(smu->adev, NULL); + amdgpu_hdp_invalidate(smu->adev, NULL); smu_table_cache_update_time(sys_table, jiffies); memcpy(sys_table->cache.buffer, table->cpu_addr, smu_v13_0_12_get_system_metrics_size()); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 7c94aa9c86aba..75be50050328b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -916,7 +916,7 @@ int smu_v13_0_6_get_metrics_table(struct smu_context *smu, void *metrics_table, return ret; } - amdgpu_asic_invalidate_hdp(smu->adev, NULL); + amdgpu_hdp_invalidate(smu->adev, NULL); memcpy(smu_table->metrics_table, table->cpu_addr, table_size); smu_table->metrics_time = jiffies; @@ -995,7 +995,7 @@ int smu_v13_0_6_get_static_metrics_table(struct smu_context *smu) return ret; } - amdgpu_asic_invalidate_hdp(smu->adev, NULL); + amdgpu_hdp_invalidate(smu->adev, NULL); memcpy(smu_table->metrics_table, table->cpu_addr, table_size); return 0; @@ -2544,7 +2544,7 @@ static int smu_v13_0_6_request_i2c_xfer(struct smu_context *smu, memcpy(table->cpu_addr, table_data, table_size); /* Flush hdp cache */ - amdgpu_asic_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RequestI2cTransaction, NULL); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 64ebda5f22a08..fc0d2fe0c9b2b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -985,7 +985,7 @@ int smu_cmn_update_table(struct smu_context *smu, * Flush hdp cache: to guard the content seen by * GPU is consitent with CPU. */ - amdgpu_asic_flush_hdp(adev, NULL); + amdgpu_hdp_flush(adev, NULL); } ret = smu_cmn_send_smc_msg_with_param(smu, drv2smu ? @@ -997,7 +997,7 @@ int smu_cmn_update_table(struct smu_context *smu, return ret; if (!drv2smu) { - amdgpu_asic_invalidate_hdp(adev, NULL); + amdgpu_hdp_invalidate(adev, NULL); memcpy(table_data, table->cpu_addr, table_size); } From 7383a9cf7fb3cd49ba779a8eb5ddfdfbfa5274fb Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Tue, 28 Oct 2025 16:34:34 +0800 Subject: [PATCH 2422/2653] drm/amd/ras: Fix the error of undefined reference to `__udivdi3' Fix the error: drivers/gpu/drm/amd/amdgpu/../ras/ras_mgr/amdgpu_ras_mgr.c:132:undefined reference to `__udivdi3' Fixs:b5bae0f01786d("drm/amd/ras: Add amdgpu ras management function") Reported-by: kernel test robot Closes:https://lore.kernel.org/oe-kbuild-all/202510272144.6SUHUoWx-lkp@intel.com/ Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Yang Wang --- drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c index 8007e49951d81..dc2a4c6c19074 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -37,7 +37,7 @@ #define MAX_XCD_NUM_PER_AID 2 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */ -#define ESTIMATE_BAD_PAGE_THRESHOLD(size) ((size)/(100 * 1024 * 1024ULL)) +#define TYPICAL_ECC_BAD_PAGE_RATE (100ULL * SZ_1M) #define COUNT_BAD_PAGE_THRESHOLD(size) (((size) >> 21) << 4) @@ -129,7 +129,7 @@ static int amdgpu_ras_mgr_init_eeprom_config(struct amdgpu_device *adev, */ if (amdgpu_bad_page_threshold == NONSTOP_OVER_THRESHOLD) eeprom_cfg->eeprom_record_threshold_count = - ESTIMATE_BAD_PAGE_THRESHOLD(adev->gmc.mc_vram_size); + div64_u64(adev->gmc.mc_vram_size, TYPICAL_ECC_BAD_PAGE_RATE); else if (amdgpu_bad_page_threshold == WARN_NONSTOP_OVER_THRESHOLD) eeprom_cfg->eeprom_record_threshold_count = COUNT_BAD_PAGE_THRESHOLD(RAS_RESERVED_VRAM_SIZE_DEFAULT); From 1e10f8b189c0e57330e7916f802f31c04ddcbe8c Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Tue, 28 Oct 2025 16:30:12 +0800 Subject: [PATCH 2423/2653] drm/amdgpu: Fix error injection parameter error Fix error injection parameter error. Signed-off-by: YiPeng Chai Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index cf2bd6c8bb590..0453ff6e79a6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1661,7 +1661,7 @@ static int amdgpu_uniras_error_inject(struct amdgpu_device *adev, inject_req.address = info->address; inject_req.error_type = info->head.type; inject_req.instance_mask = info->instance_mask; - inject_req.value = info->value; + inject_req.method = info->value; return amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__INJECT_ERROR, &inject_req, sizeof(inject_req), &rsp, sizeof(rsp)); From f729bfb8e84c29b685b5fbded8e7228305a19573 Mon Sep 17 00:00:00 2001 From: Xiang Liu Date: Mon, 20 Oct 2025 15:45:23 +0800 Subject: [PATCH 2424/2653] drm/amd/ras: Update IPID value for bad page threshold CPER The IPID register value for bad page threshold CPER holds socket_id info now according to the latest definition. Signed-off-by: Xiang Liu Reviewed-by: Tao Zhou Change-Id: I847509f0282e246a171194c4fdbe1dfe0b297bb0 --- drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c b/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c index d0621464f1a76..0a838fdcb2f61 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_log_ring.c @@ -226,7 +226,9 @@ void ras_log_ring_add_log_event(struct ras_core_context *ras_core, enum ras_log_event event, void *data, struct ras_log_batch_tag *batch_tag) { struct ras_log_ring *log_ring = &ras_core->ras_log_ring; + struct device_system_info dev_info = {0}; struct ras_log_info *log; + uint64_t socket_id; void *obj; obj = mempool_alloc_preallocated(log_ring->ras_log_mempool); @@ -252,8 +254,13 @@ void ras_log_ring_add_log_event(struct ras_core_context *ras_core, if (data) memcpy(&log->aca_reg, data, sizeof(log->aca_reg)); - if (event == RAS_LOG_EVENT_RMA) + if (event == RAS_LOG_EVENT_RMA) { memcpy(&log->aca_reg, ras_rma_aca_reg, sizeof(log->aca_reg)); + ras_core_get_device_system_info(ras_core, &dev_info); + socket_id = dev_info.socket_id; + log->aca_reg.regs[ACA_REG_IDX__IPID] |= ((socket_id / 4) & 0x01); + log->aca_reg.regs[ACA_REG_IDX__IPID] |= (((socket_id % 4) & 0x3) << 44); + } ras_log_ring_add_data(ras_core, log, batch_tag); } From 20a65973838e9bebff4990a95707fc41a3dd4927 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 26 Sep 2025 20:02:01 +0200 Subject: [PATCH 2425/2653] drm/amd/display: Add common modes to analog displays without EDID MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When the EDID of an analog display is not available, we can't know the possible modes supported by the display. However, we still need to offer the user to select from a variety of common modes. It will be up to the user to select the best one, though. This is how it works on other operating systems as well as the legacy display code path in amdgpu. Signed-off-by: Timur Kristóf Reviewed-by: Harry Wentland --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 46 +++++++++++-------- 1 file changed, 28 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a1a0dae1e5bef..b234d7c96429a 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8635,7 +8635,7 @@ static void amdgpu_dm_get_native_mode(struct drm_connector *connector) static struct drm_display_mode * amdgpu_dm_create_common_mode(struct drm_encoder *encoder, - char *name, + const char *name, int hdisplay, int vdisplay) { struct drm_device *dev = encoder->dev; @@ -8658,6 +8658,24 @@ amdgpu_dm_create_common_mode(struct drm_encoder *encoder, } +static const struct amdgpu_dm_mode_size { + char name[DRM_DISPLAY_MODE_LEN]; + int w; + int h; +} common_modes[] = { + { "640x480", 640, 480}, + { "800x600", 800, 600}, + { "1024x768", 1024, 768}, + { "1280x720", 1280, 720}, + { "1280x800", 1280, 800}, + {"1280x1024", 1280, 1024}, + { "1440x900", 1440, 900}, + {"1680x1050", 1680, 1050}, + {"1600x1200", 1600, 1200}, + {"1920x1080", 1920, 1080}, + {"1920x1200", 1920, 1200} +}; + static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, struct drm_connector *connector) { @@ -8668,23 +8686,6 @@ static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, to_amdgpu_dm_connector(connector); int i; int n; - struct mode_size { - char name[DRM_DISPLAY_MODE_LEN]; - int w; - int h; - } common_modes[] = { - { "640x480", 640, 480}, - { "800x600", 800, 600}, - { "1024x768", 1024, 768}, - { "1280x720", 1280, 720}, - { "1280x800", 1280, 800}, - {"1280x1024", 1280, 1024}, - { "1440x900", 1440, 900}, - {"1680x1050", 1680, 1050}, - {"1600x1200", 1600, 1200}, - {"1920x1080", 1920, 1080}, - {"1920x1200", 1920, 1200} - }; if ((connector->connector_type != DRM_MODE_CONNECTOR_eDP) && (connector->connector_type != DRM_MODE_CONNECTOR_LVDS)) @@ -8947,6 +8948,15 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) amdgpu_dm_connector->num_modes += drm_add_modes_noedid(connector, 1920, 1080); + + if (amdgpu_dm_connector->dc_sink->edid_caps.analog) { + /* Analog monitor connected by DAC load detection. + * Add common modes. It will be up to the user to select one that works. + */ + for (int i = 0; i < ARRAY_SIZE(common_modes); i++) + amdgpu_dm_connector->num_modes += drm_add_modes_noedid( + connector, common_modes[i].w, common_modes[i].h); + } } else { #ifdef HAVE_DRM_DP_MST_EDID_READ amdgpu_dm_connector_ddc_get_modes(connector, drm_edid); From f054494ec0ff7824e972769b9bc41063a4bbd70c Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 29 Oct 2025 10:28:14 -0400 Subject: [PATCH 2426/2653] drm/amd/display: Fix null pointer on analog detection MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Check if we have an amdgpu_dm_connector->dc_sink first before adding common modes for analog outputs. If we don't have a sink yet we can safely skip this. Fixes: 0c9f9ca99238 ("drm/amd/display: Add common modes to analog displays without EDID") Signed-off-by: Harry Wentland Reviewed-by: Timur Kristóf --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b234d7c96429a..9070dfa4f3ec2 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8949,7 +8949,7 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) amdgpu_dm_connector->num_modes += drm_add_modes_noedid(connector, 1920, 1080); - if (amdgpu_dm_connector->dc_sink->edid_caps.analog) { + if (amdgpu_dm_connector->dc_sink && amdgpu_dm_connector->dc_sink->edid_caps.analog) { /* Analog monitor connected by DAC load detection. * Add common modes. It will be up to the user to select one that works. */ From 0b5f7c9d4dd4a23150f9b1c1a21b48848273d95c Mon Sep 17 00:00:00 2001 From: Yang Su Date: Fri, 31 Oct 2025 12:43:24 +0800 Subject: [PATCH 2427/2653] Bump AMDGPU version to 6.16.10 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index d395c1833b0ef..28b1119000266 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.16.9) +AC_INIT(amdgpu-dkms, 6.16.10) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From bf794550f510efce6095dacaee713e8e7df6012c Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Mon, 27 Oct 2025 15:22:54 +0800 Subject: [PATCH 2428/2653] drm/amd/pm: fix the issue of size calculation error for smu 13.0.6 v1: the driver should handle return value of smu_v13_0_6_printk_clk_levels() to return the correct size for sysfs reads. v2: fix the issue of size calculation error in smu_v13_0_6_print_clks() Fixes: 0354cd650daa ("drm/amd/pm: Avoid writing nulls into `pp_od_clk_voltage`") Signed-off-by: Yang Wang Reviewed-by: Lijo Lazar --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 42 ++++++++++++++----- 1 file changed, 31 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 75be50050328b..378c669d14d57 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -1553,7 +1553,7 @@ static int smu_v13_0_6_print_clks(struct smu_context *smu, char *buf, int size, return -EINVAL; if (curr_clk < SMU_13_0_6_DSCLK_THRESHOLD) { - size = sysfs_emit_at(buf, size, "S: %uMhz *\n", curr_clk); + size += sysfs_emit_at(buf, size, "S: %uMhz *\n", curr_clk); for (i = 0; i < clocks.num_levels; i++) size += sysfs_emit_at(buf, size, "%d: %uMhz\n", i, clocks.data[i].clocks_in_khz / @@ -1673,9 +1673,13 @@ static int smu_v13_0_6_print_clk_levels(struct smu_context *smu, single_dpm_table = &(dpm_context->dpm_tables.uclk_table); - return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, - now, "mclk"); + ret = smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, + now, "mclk"); + if (ret < 0) + return ret; + size += ret; + break; case SMU_SOCCLK: ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now); @@ -1687,9 +1691,13 @@ static int smu_v13_0_6_print_clk_levels(struct smu_context *smu, single_dpm_table = &(dpm_context->dpm_tables.soc_table); - return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, - now, "socclk"); + ret = smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, + now, "socclk"); + if (ret < 0) + return ret; + size += ret; + break; case SMU_FCLK: ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_FCLK, &now); @@ -1701,9 +1709,13 @@ static int smu_v13_0_6_print_clk_levels(struct smu_context *smu, single_dpm_table = &(dpm_context->dpm_tables.fclk_table); - return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, - now, "fclk"); + ret = smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, + now, "fclk"); + if (ret < 0) + return ret; + size += ret; + break; case SMU_VCLK: ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_VCLK, &now); @@ -1715,9 +1727,13 @@ static int smu_v13_0_6_print_clk_levels(struct smu_context *smu, single_dpm_table = &(dpm_context->dpm_tables.vclk_table); - return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, - now, "vclk"); + ret = smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, + now, "vclk"); + if (ret < 0) + return ret; + size += ret; + break; case SMU_DCLK: ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_DCLK, &now); @@ -1729,9 +1745,13 @@ static int smu_v13_0_6_print_clk_levels(struct smu_context *smu, single_dpm_table = &(dpm_context->dpm_tables.dclk_table); - return smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, - now, "dclk"); + ret = smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, + now, "dclk"); + if (ret < 0) + return ret; + size += ret; + break; default: break; } From 71a2ab617a02e91bcf0fe78a13b344abd0e418bd Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Thu, 30 Oct 2025 13:06:24 +0800 Subject: [PATCH 2429/2653] drm/amd/pm: fix missing device_attr cleanup in amdgpu_pm_sysfs_init() Use the correct label to complete all cleanup work. Fixes: 4d154b1ca580f ("drm/amd/pm: Add support for DPM policies") Fixes: d2e690ff5d3cf ("drm/amd/pm: Add temperature metrics sysfs entry") Signed-off-by: Yang Wang Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 91f8f9547ee76..a0500200266b8 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -4725,7 +4725,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) ret = devm_device_add_group(adev->dev, &amdgpu_pm_policy_attr_group); if (ret) - goto err_out0; + goto err_out1; } #endif @@ -4733,7 +4733,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) ret = devm_device_add_group(adev->dev, &amdgpu_board_attr_group); if (ret) - goto err_out0; + goto err_out1; if (amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT, (void *)&tmp) != -EOPNOTSUPP) { sysfs_add_file_to_group(&adev->dev->kobj, From c2b581c165a79b04b9ae14d85b6ba190df80fc4e Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 11 Aug 2025 19:07:05 +0530 Subject: [PATCH 2430/2653] drm/amd/pm: Add helper functions for gpu metrics Add helper macros to define metrics struct definitions. It will define structs with field type followed by actual field. A helper macro is also added to initialize the field encoding for all fields and to initialize the field members to 0xFFs. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 67 ++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h index 0ae91c8b6d72d..8d7c4814c68f0 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h @@ -202,5 +202,72 @@ void smu_cmn_get_backend_workload_mask(struct smu_context *smu, u32 workload_mask, u32 *backend_workload_mask); +/*SMU gpu metrics */ + +/* Attribute ID mapping */ +#define SMU_MATTR(X) AMDGPU_METRICS_ATTR_ID_##X +/* Type ID mapping */ +#define SMU_MTYPE(X) AMDGPU_METRICS_TYPE_##X +/* Unit ID mapping */ +#define SMU_MUNIT(X) AMDGPU_METRICS_UNIT_##X + +/* Map TYPEID to C type */ +#define SMU_CTYPE(TYPEID) SMU_CTYPE_##TYPEID + +#define SMU_CTYPE_AMDGPU_METRICS_TYPE_U8 u8 +#define SMU_CTYPE_AMDGPU_METRICS_TYPE_S8 s8 +#define SMU_CTYPE_AMDGPU_METRICS_TYPE_U16 u16 +#define SMU_CTYPE_AMDGPU_METRICS_TYPE_S16 s16 +#define SMU_CTYPE_AMDGPU_METRICS_TYPE_U32 u32 +#define SMU_CTYPE_AMDGPU_METRICS_TYPE_S32 s32 +#define SMU_CTYPE_AMDGPU_METRICS_TYPE_U64 u64 +#define SMU_CTYPE_AMDGPU_METRICS_TYPE_S64 s64 + +/* struct members */ +#define SMU_METRICS_SCALAR(ID, UNIT, TYPEID, NAME) \ + u64 NAME##_ftype; \ + SMU_CTYPE(TYPEID) NAME + +#define SMU_METRICS_ARRAY(ID, UNIT, TYPEID, NAME, SIZE) \ + u64 NAME##_ftype; \ + SMU_CTYPE(TYPEID) NAME[SIZE] + +/* Init functions for scalar/array fields - init to 0xFFs */ +#define SMU_METRICS_INIT_SCALAR(ID, UNIT, TYPEID, NAME) \ + do { \ + obj->NAME##_ftype = \ + AMDGPU_METRICS_ENC_ATTR(UNIT, TYPEID, ID, 1); \ + obj->NAME = (SMU_CTYPE(TYPEID)) ~0; \ + count++; \ + } while (0) + +#define SMU_METRICS_INIT_ARRAY(ID, UNIT, TYPEID, NAME, SIZE) \ + do { \ + obj->NAME##_ftype = \ + AMDGPU_METRICS_ENC_ATTR(UNIT, TYPEID, ID, SIZE); \ + memset(obj->NAME, 0xFF, sizeof(obj->NAME)); \ + count++; \ + } while (0) + +/* Declare Metrics Class and Template object */ +#define DECLARE_SMU_METRICS_CLASS(CLASSNAME, SMU_METRICS_FIELD_LIST) \ + struct __packed CLASSNAME { \ + struct metrics_table_header header; \ + int attr_count; \ + SMU_METRICS_FIELD_LIST(SMU_METRICS_SCALAR, SMU_METRICS_ARRAY); \ + }; \ + static inline void CLASSNAME##_init(struct CLASSNAME *obj, \ + uint8_t frev, uint8_t crev) \ + { \ + int count = 0; \ + memset(obj, 0xFF, sizeof(*obj)); \ + obj->header.format_revision = frev; \ + obj->header.content_revision = crev; \ + obj->header.structure_size = sizeof(*obj); \ + SMU_METRICS_FIELD_LIST(SMU_METRICS_INIT_SCALAR, \ + SMU_METRICS_INIT_ARRAY) \ + obj->attr_count = count; \ + } + #endif #endif From 6115a3a7d1a2e6b821ce3622b5245a3285bb9282 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 12 Aug 2025 18:26:59 +0530 Subject: [PATCH 2431/2653] drm/amd/pm: Use gpu metrics 1.9 for SMUv13.0.6 Fill and publish GPU metrics in v1.9 format for SMUv13.0.6 SOCs Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 113 +++++++++-------- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 120 ++++++++++++++++++ 2 files changed, 179 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 378c669d14d57..abb373bdaaabf 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -558,6 +558,7 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu) struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; void *gpu_metrics_table __free(kfree) = NULL; + struct smu_v13_0_6_gpu_metrics *gpu_metrics; void *driver_pptable __free(kfree) = NULL; void *metrics_table __free(kfree) = NULL; struct amdgpu_device *adev = smu->adev; @@ -597,11 +598,22 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu) if (!driver_pptable) return -ENOMEM; + ret = smu_table_cache_init(smu, SMU_TABLE_SMU_METRICS, + sizeof(struct smu_v13_0_6_gpu_metrics), 1); + if (ret) + return ret; + + gpu_metrics = (struct smu_v13_0_6_gpu_metrics + *)(tables[SMU_TABLE_SMU_METRICS].cache.buffer); + + smu_v13_0_6_gpu_metrics_init(gpu_metrics, 1, 9); if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) { ret = smu_v13_0_12_tables_init(smu); - if (ret) + if (ret) { + smu_table_cache_fini(smu, SMU_TABLE_SMU_METRICS); return ret; + } } smu_table->gpu_metrics_table = no_free_ptr(gpu_metrics_table); @@ -882,6 +894,7 @@ static int smu_v13_0_6_fini_smc_tables(struct smu_context *smu) { if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) smu_v13_0_12_tables_fini(smu); + smu_table_cache_fini(smu, SMU_TABLE_SMU_METRICS); return smu_v13_0_fini_smc_tables(smu); } @@ -2921,18 +2934,16 @@ static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id, static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table) { struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v1_8 *gpu_metrics = - (struct gpu_metrics_v1_8 *)smu_table->gpu_metrics_table; + struct smu_table *tables = smu_table->tables; + struct smu_v13_0_6_gpu_metrics *gpu_metrics; int version = smu_v13_0_6_get_metrics_version(smu); MetricsTableV0_t *metrics_v0 __free(kfree) = NULL; - int ret = 0, xcc_id, inst, i, j, k, idx; struct amdgpu_device *adev = smu->adev; + int ret = 0, xcc_id, inst, i, j; MetricsTableV1_t *metrics_v1; MetricsTableV2_t *metrics_v2; - struct amdgpu_xcp *xcp; u16 link_width_level; u8 num_jpeg_rings; - u32 inst_mask; bool per_inst; metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL); @@ -2947,8 +2958,8 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table metrics_v1 = (MetricsTableV1_t *)metrics_v0; metrics_v2 = (MetricsTableV2_t *)metrics_v0; - - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 8); + gpu_metrics = (struct smu_v13_0_6_gpu_metrics + *)(tables[SMU_TABLE_SMU_METRICS].cache.buffer); gpu_metrics->temperature_hotspot = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version)); @@ -3070,55 +3081,49 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table gpu_metrics->xgmi_link_status[j] = ret; } - gpu_metrics->num_partition = adev->xcp_mgr->num_xcps; - per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS)); num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3; - for_each_xcp(adev->xcp_mgr, xcp, i) { - amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); - idx = 0; - for_each_inst(k, inst_mask) { - /* Both JPEG and VCN has same instances */ - inst = GET_INST(VCN, k); - - for (j = 0; j < num_jpeg_rings; ++j) { - gpu_metrics->xcp_stats[i].jpeg_busy - [(idx * num_jpeg_rings) + j] = - SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, version) - [(inst * num_jpeg_rings) + j]); - } - gpu_metrics->xcp_stats[i].vcn_busy[idx] = - SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]); - idx++; - - } + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { + inst = GET_INST(JPEG, i); + for (j = 0; j < num_jpeg_rings; ++j) + gpu_metrics->jpeg_busy[(i * num_jpeg_rings) + j] = + SMUQ10_ROUND(GET_METRIC_FIELD( + JpegBusy, + version)[(inst * num_jpeg_rings) + j]); + } + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + inst = GET_INST(VCN, i); + gpu_metrics->vcn_busy[i] = + SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]); + } - if (per_inst) { - amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); - idx = 0; - for_each_inst(k, inst_mask) { - inst = GET_INST(GC, k); - gpu_metrics->xcp_stats[i].gfx_busy_inst[idx] = - SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]); - gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] = - SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusyAcc, - version)[inst]); - if (smu_v13_0_6_cap_supported(smu, SMU_CAP(HST_LIMIT_METRICS))) { - gpu_metrics->xcp_stats[i].gfx_below_host_limit_ppt_acc[idx] = - SMUQ10_ROUND - (metrics_v0->GfxclkBelowHostLimitPptAcc[inst]); - gpu_metrics->xcp_stats[i].gfx_below_host_limit_thm_acc[idx] = - SMUQ10_ROUND - (metrics_v0->GfxclkBelowHostLimitThmAcc[inst]); - gpu_metrics->xcp_stats[i].gfx_low_utilization_acc[idx] = - SMUQ10_ROUND - (metrics_v0->GfxclkLowUtilizationAcc[inst]); - gpu_metrics->xcp_stats[i].gfx_below_host_limit_total_acc[idx] = - SMUQ10_ROUND - (metrics_v0->GfxclkBelowHostLimitTotalAcc[inst]); - } - idx++; + if (per_inst) { + for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) { + inst = GET_INST(GC, i); + gpu_metrics->gfx_busy_inst[i] = SMUQ10_ROUND( + GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]); + gpu_metrics->gfx_busy_acc[i] = SMUQ10_ROUND( + GET_GPU_METRIC_FIELD(GfxBusyAcc, + version)[inst]); + if (smu_v13_0_6_cap_supported( + smu, SMU_CAP(HST_LIMIT_METRICS))) { + gpu_metrics->gfx_below_host_limit_ppt_acc + [i] = SMUQ10_ROUND( + metrics_v0->GfxclkBelowHostLimitPptAcc + [inst]); + gpu_metrics->gfx_below_host_limit_thm_acc + [i] = SMUQ10_ROUND( + metrics_v0->GfxclkBelowHostLimitThmAcc + [inst]); + gpu_metrics->gfx_low_utilization_acc + [i] = SMUQ10_ROUND( + metrics_v0 + ->GfxclkLowUtilizationAcc[inst]); + gpu_metrics->gfx_below_host_limit_total_acc + [i] = SMUQ10_ROUND( + metrics_v0->GfxclkBelowHostLimitTotalAcc + [inst]); } } } @@ -3128,7 +3133,7 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, version); - *table = (void *)gpu_metrics; + *table = tables[SMU_TABLE_SMU_METRICS].cache.buffer; return sizeof(*gpu_metrics); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h index 7ef5f3e66c273..3f57e2a33fb4a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h @@ -75,6 +75,13 @@ enum smu_v13_0_6_caps { SMU_CAP(ALL), }; +#define SMU_13_0_6_NUM_XGMI_LINKS 8 +#define SMU_13_0_6_MAX_GFX_CLKS 8 +#define SMU_13_0_6_MAX_CLKS 4 +#define SMU_13_0_6_MAX_XCC 8 +#define SMU_13_0_6_MAX_VCN 4 +#define SMU_13_0_6_MAX_JPEG 40 + extern void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu); bool smu_v13_0_6_cap_supported(struct smu_context *smu, enum smu_v13_0_6_caps cap); int smu_v13_0_6_get_static_metrics_table(struct smu_context *smu); @@ -99,4 +106,117 @@ int smu_v13_0_12_get_npm_data(struct smu_context *smu, extern const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[]; extern const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[]; extern const struct smu_temp_funcs smu_v13_0_12_temp_funcs; + +#if defined(SWSMU_CODE_LAYER_L2) +#include "smu_cmn.h" + +/* SMUv 13.0.6 GPU metrics*/ +#define SMU_13_0_6_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY) \ + SMU_SCALAR(SMU_MATTR(TEMPERATURE_HOTSPOT), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_hotspot); \ + SMU_SCALAR(SMU_MATTR(TEMPERATURE_MEM), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_mem); \ + SMU_SCALAR(SMU_MATTR(TEMPERATURE_VRSOC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_vrsoc); \ + SMU_SCALAR(SMU_MATTR(CURR_SOCKET_POWER), SMU_MUNIT(POWER_1), \ + SMU_MTYPE(U16), curr_socket_power); \ + SMU_SCALAR(SMU_MATTR(AVERAGE_GFX_ACTIVITY), SMU_MUNIT(PERCENT), \ + SMU_MTYPE(U16), average_gfx_activity); \ + SMU_SCALAR(SMU_MATTR(AVERAGE_UMC_ACTIVITY), SMU_MUNIT(PERCENT), \ + SMU_MTYPE(U16), average_umc_activity); \ + SMU_SCALAR(SMU_MATTR(MEM_MAX_BANDWIDTH), SMU_MUNIT(BW_1), \ + SMU_MTYPE(U64), mem_max_bandwidth); \ + SMU_SCALAR(SMU_MATTR(ENERGY_ACCUMULATOR), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), energy_accumulator); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_CLOCK_COUNTER), SMU_MUNIT(TIME_1), \ + SMU_MTYPE(U64), system_clock_counter); \ + SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \ + SMU_MTYPE(U32), accumulation_counter); \ + SMU_SCALAR(SMU_MATTR(PROCHOT_RESIDENCY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U32), prochot_residency_acc); \ + SMU_SCALAR(SMU_MATTR(PPT_RESIDENCY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U32), ppt_residency_acc); \ + SMU_SCALAR(SMU_MATTR(SOCKET_THM_RESIDENCY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U32), socket_thm_residency_acc); \ + SMU_SCALAR(SMU_MATTR(VR_THM_RESIDENCY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U32), vr_thm_residency_acc); \ + SMU_SCALAR(SMU_MATTR(HBM_THM_RESIDENCY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U32), hbm_thm_residency_acc); \ + SMU_SCALAR(SMU_MATTR(GFXCLK_LOCK_STATUS), SMU_MUNIT(NONE), \ + SMU_MTYPE(U32), gfxclk_lock_status); \ + SMU_SCALAR(SMU_MATTR(PCIE_LINK_WIDTH), SMU_MUNIT(NONE), \ + SMU_MTYPE(U16), pcie_link_width); \ + SMU_SCALAR(SMU_MATTR(PCIE_LINK_SPEED), SMU_MUNIT(SPEED_2), \ + SMU_MTYPE(U16), pcie_link_speed); \ + SMU_SCALAR(SMU_MATTR(XGMI_LINK_WIDTH), SMU_MUNIT(NONE), \ + SMU_MTYPE(U16), xgmi_link_width); \ + SMU_SCALAR(SMU_MATTR(XGMI_LINK_SPEED), SMU_MUNIT(SPEED_1), \ + SMU_MTYPE(U16), xgmi_link_speed); \ + SMU_SCALAR(SMU_MATTR(GFX_ACTIVITY_ACC), SMU_MUNIT(PERCENT), \ + SMU_MTYPE(U32), gfx_activity_acc); \ + SMU_SCALAR(SMU_MATTR(MEM_ACTIVITY_ACC), SMU_MUNIT(PERCENT), \ + SMU_MTYPE(U32), mem_activity_acc); \ + SMU_SCALAR(SMU_MATTR(PCIE_BANDWIDTH_ACC), SMU_MUNIT(PERCENT), \ + SMU_MTYPE(U64), pcie_bandwidth_acc); \ + SMU_SCALAR(SMU_MATTR(PCIE_BANDWIDTH_INST), SMU_MUNIT(BW_1), \ + SMU_MTYPE(U64), pcie_bandwidth_inst); \ + SMU_SCALAR(SMU_MATTR(PCIE_L0_TO_RECOV_COUNT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), pcie_l0_to_recov_count_acc); \ + SMU_SCALAR(SMU_MATTR(PCIE_REPLAY_COUNT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), pcie_replay_count_acc); \ + SMU_SCALAR(SMU_MATTR(PCIE_REPLAY_ROVER_COUNT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), pcie_replay_rover_count_acc); \ + SMU_SCALAR(SMU_MATTR(PCIE_NAK_SENT_COUNT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U32), pcie_nak_sent_count_acc); \ + SMU_SCALAR(SMU_MATTR(PCIE_NAK_RCVD_COUNT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U32), pcie_nak_rcvd_count_acc); \ + SMU_ARRAY(SMU_MATTR(XGMI_READ_DATA_ACC), SMU_MUNIT(DATA_1), \ + SMU_MTYPE(U64), xgmi_read_data_acc, \ + SMU_13_0_6_NUM_XGMI_LINKS); \ + SMU_ARRAY(SMU_MATTR(XGMI_WRITE_DATA_ACC), SMU_MUNIT(DATA_1), \ + SMU_MTYPE(U64), xgmi_write_data_acc, \ + SMU_13_0_6_NUM_XGMI_LINKS); \ + SMU_ARRAY(SMU_MATTR(XGMI_LINK_STATUS), SMU_MUNIT(NONE), \ + SMU_MTYPE(U16), xgmi_link_status, \ + SMU_13_0_6_NUM_XGMI_LINKS); \ + SMU_SCALAR(SMU_MATTR(FIRMWARE_TIMESTAMP), SMU_MUNIT(TIME_2), \ + SMU_MTYPE(U64), firmware_timestamp); \ + SMU_ARRAY(SMU_MATTR(CURRENT_GFXCLK), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_gfxclk, SMU_13_0_6_MAX_GFX_CLKS); \ + SMU_ARRAY(SMU_MATTR(CURRENT_SOCCLK), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_socclk, SMU_13_0_6_MAX_CLKS); \ + SMU_ARRAY(SMU_MATTR(CURRENT_VCLK0), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_vclk0, SMU_13_0_6_MAX_CLKS); \ + SMU_ARRAY(SMU_MATTR(CURRENT_DCLK0), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_dclk0, SMU_13_0_6_MAX_CLKS); \ + SMU_SCALAR(SMU_MATTR(CURRENT_UCLK), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_uclk); \ + SMU_SCALAR(SMU_MATTR(PCIE_LC_PERF_OTHER_END_RECOVERY), \ + SMU_MUNIT(NONE), SMU_MTYPE(U32), \ + pcie_lc_perf_other_end_recovery); \ + SMU_ARRAY(SMU_MATTR(GFX_BUSY_INST), SMU_MUNIT(PERCENT), \ + SMU_MTYPE(U32), gfx_busy_inst, SMU_13_0_6_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(JPEG_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U16), \ + jpeg_busy, SMU_13_0_6_MAX_JPEG); \ + SMU_ARRAY(SMU_MATTR(VCN_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U16), \ + vcn_busy, SMU_13_0_6_MAX_VCN); \ + SMU_ARRAY(SMU_MATTR(GFX_BUSY_ACC), SMU_MUNIT(PERCENT), SMU_MTYPE(U64), \ + gfx_busy_acc, SMU_13_0_6_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_PPT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_below_host_limit_ppt_acc, \ + SMU_13_0_6_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_THM_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_below_host_limit_thm_acc, \ + SMU_13_0_6_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_LOW_UTILIZATION_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_low_utilization_acc, \ + SMU_13_0_6_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_TOTAL_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_below_host_limit_total_acc, \ + SMU_13_0_6_MAX_XCC); + +DECLARE_SMU_METRICS_CLASS(smu_v13_0_6_gpu_metrics, SMU_13_0_6_METRICS_FIELDS); + +#endif /* SWSMU_CODE_LAYER_L2 */ + #endif From 1a3bbe48a93f49807cf0b83920cd71c2815ebf70 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Thu, 30 Oct 2025 10:15:56 +0100 Subject: [PATCH 2432/2653] drm/amd/pm/si: Delete unused structs and fields MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The contents of si_dpm.h seem to have been copied from the old radeon driver, including a lot of structs and fields which were only relevant to GPU generations even older than SI. A lot of these can be deleted without causing much churn to the actual SI DPM code. Let's delete them to make the code easier to understand. Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 10 +- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.h | 557 --------------------- 2 files changed, 1 insertion(+), 566 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 3a9522c17fee3..020e05c137e43 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -2558,18 +2558,13 @@ static int si_enable_power_containment(struct amdgpu_device *adev, if (enable) { if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive); - if (smc_result != PPSMC_Result_OK) { + if (smc_result != PPSMC_Result_OK) ret = -EINVAL; - ni_pi->pc_enabled = false; - } else { - ni_pi->pc_enabled = true; - } } } else { smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive); if (smc_result != PPSMC_Result_OK) ret = -EINVAL; - ni_pi->pc_enabled = false; } } @@ -7509,8 +7504,6 @@ static int si_dpm_init(struct amdgpu_device *adev) pi->pasi = CYPRESS_HASI_DFLT; pi->vrc = SISLANDS_VRC_DFLT; - pi->gfx_clock_gating = true; - eg_pi->sclk_deep_sleep = true; si_pi->sclk_deep_sleep_above_low = false; @@ -7521,7 +7514,6 @@ static int si_dpm_init(struct amdgpu_device *adev) eg_pi->dynamic_ac_timing = true; - eg_pi->light_sleep = true; #if defined(CONFIG_ACPI) eg_pi->pcie_performance_request = amdgpu_acpi_is_pcie_performance_request_supported(adev); diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.h b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.h index 11cb7874a6bbd..3aed75fbf913b 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.h +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.h @@ -38,11 +38,7 @@ #define MC_ARB_DRAM_TIMING2_2 0xa00 #define MC_ARB_DRAM_TIMING2_3 0xa01 -#define MAX_NO_OF_MVDD_VALUES 2 -#define MAX_NO_VREG_STEPS 32 #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 -#define SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 32 -#define SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20 #define RV770_ASI_DFLT 1000 #define CYPRESS_HASI_DFLT 400000 #define PCIE_PERF_REQ_PECI_GEN1 2 @@ -51,11 +47,6 @@ #define RV770_DEFAULT_VCLK_FREQ 53300 /* 10 khz */ #define RV770_DEFAULT_DCLK_FREQ 40000 /* 10 khz */ -#define SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE 16 - -#define RV770_SMC_TABLE_ADDRESS 0xB000 -#define RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 3 - #define SMC_STROBE_RATIO 0x0F #define SMC_STROBE_ENABLE 0x10 @@ -64,27 +55,6 @@ #define SMC_MC_RTT_ENABLE 0x04 #define SMC_MC_STUTTER_EN 0x08 -#define RV770_SMC_VOLTAGEMASK_VDDC 0 -#define RV770_SMC_VOLTAGEMASK_MVDD 1 -#define RV770_SMC_VOLTAGEMASK_VDDCI 2 -#define RV770_SMC_VOLTAGEMASK_MAX 4 - -#define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 -#define NISLANDS_SMC_STROBE_RATIO 0x0F -#define NISLANDS_SMC_STROBE_ENABLE 0x10 - -#define NISLANDS_SMC_MC_EDC_RD_FLAG 0x01 -#define NISLANDS_SMC_MC_EDC_WR_FLAG 0x02 -#define NISLANDS_SMC_MC_RTT_ENABLE 0x04 -#define NISLANDS_SMC_MC_STUTTER_EN 0x08 - -#define MAX_NO_VREG_STEPS 32 - -#define NISLANDS_SMC_VOLTAGEMASK_VDDC 0 -#define NISLANDS_SMC_VOLTAGEMASK_MVDD 1 -#define NISLANDS_SMC_VOLTAGEMASK_VDDCI 2 -#define NISLANDS_SMC_VOLTAGEMASK_MAX 4 - #define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT 0 #define SISLANDS_MCREGISTERTABLE_ACPI_SLOT 1 #define SISLANDS_MCREGISTERTABLE_ULV_SLOT 2 @@ -219,32 +189,6 @@ enum si_cac_config_reg_type SISLANDS_CACCONFIG_MAX }; -enum si_power_level { - SI_POWER_LEVEL_LOW = 0, - SI_POWER_LEVEL_MEDIUM = 1, - SI_POWER_LEVEL_HIGH = 2, - SI_POWER_LEVEL_CTXSW = 3, -}; - -enum si_td { - SI_TD_AUTO, - SI_TD_UP, - SI_TD_DOWN, -}; - -enum si_display_watermark { - SI_DISPLAY_WATERMARK_LOW = 0, - SI_DISPLAY_WATERMARK_HIGH = 1, -}; - -enum si_display_gap -{ - SI_PM_DISPLAY_GAP_VBLANK_OR_WM = 0, - SI_PM_DISPLAY_GAP_VBLANK = 1, - SI_PM_DISPLAY_GAP_WATERMARK = 2, - SI_PM_DISPLAY_GAP_IGNORE = 3, -}; - extern const struct amdgpu_ip_block_version si_smu_ip_block; struct ni_leakage_coeffients @@ -258,56 +202,6 @@ struct ni_leakage_coeffients u32 t_ref; }; -struct SMC_Evergreen_MCRegisterAddress -{ - uint16_t s0; - uint16_t s1; -}; - -typedef struct SMC_Evergreen_MCRegisterAddress SMC_Evergreen_MCRegisterAddress; - -struct evergreen_mc_reg_entry { - u32 mclk_max; - u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; -}; - -struct evergreen_mc_reg_table { - u8 last; - u8 num_entries; - u16 valid_flag; - struct evergreen_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; - SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; -}; - -struct SMC_Evergreen_MCRegisterSet -{ - uint32_t value[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; -}; - -typedef struct SMC_Evergreen_MCRegisterSet SMC_Evergreen_MCRegisterSet; - -struct SMC_Evergreen_MCRegisters -{ - uint8_t last; - uint8_t reserved[3]; - SMC_Evergreen_MCRegisterAddress address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; - SMC_Evergreen_MCRegisterSet data[5]; -}; - -typedef struct SMC_Evergreen_MCRegisters SMC_Evergreen_MCRegisters; - -struct SMC_NIslands_MCRegisterSet -{ - uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; -}; - -typedef struct SMC_NIslands_MCRegisterSet SMC_NIslands_MCRegisterSet; - -struct ni_mc_reg_entry { - u32 mclk_max; - u32 mc_data[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; -}; - struct SMC_NIslands_MCRegisterAddress { uint16_t s0; @@ -316,257 +210,20 @@ struct SMC_NIslands_MCRegisterAddress typedef struct SMC_NIslands_MCRegisterAddress SMC_NIslands_MCRegisterAddress; -struct SMC_NIslands_MCRegisters -{ - uint8_t last; - uint8_t reserved[3]; - SMC_NIslands_MCRegisterAddress address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; - SMC_NIslands_MCRegisterSet data[SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT]; -}; - -typedef struct SMC_NIslands_MCRegisters SMC_NIslands_MCRegisters; - -struct evergreen_ulv_param { - bool supported; - struct rv7xx_pl *pl; -}; - -struct evergreen_arb_registers { - u32 mc_arb_dram_timing; - u32 mc_arb_dram_timing2; - u32 mc_arb_rfsh_rate; - u32 mc_arb_burst_time; -}; - -struct at { - u32 rlp; - u32 rmp; - u32 lhp; - u32 lmp; -}; - -struct ni_clock_registers { - u32 cg_spll_func_cntl; - u32 cg_spll_func_cntl_2; - u32 cg_spll_func_cntl_3; - u32 cg_spll_func_cntl_4; - u32 cg_spll_spread_spectrum; - u32 cg_spll_spread_spectrum_2; - u32 mclk_pwrmgt_cntl; - u32 dll_cntl; - u32 mpll_ad_func_cntl; - u32 mpll_ad_func_cntl_2; - u32 mpll_dq_func_cntl; - u32 mpll_dq_func_cntl_2; - u32 mpll_ss1; - u32 mpll_ss2; -}; - -struct RV770_SMC_SCLK_VALUE -{ - uint32_t vCG_SPLL_FUNC_CNTL; - uint32_t vCG_SPLL_FUNC_CNTL_2; - uint32_t vCG_SPLL_FUNC_CNTL_3; - uint32_t vCG_SPLL_SPREAD_SPECTRUM; - uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; - uint32_t sclk_value; -}; - -typedef struct RV770_SMC_SCLK_VALUE RV770_SMC_SCLK_VALUE; - -struct RV770_SMC_MCLK_VALUE -{ - uint32_t vMPLL_AD_FUNC_CNTL; - uint32_t vMPLL_AD_FUNC_CNTL_2; - uint32_t vMPLL_DQ_FUNC_CNTL; - uint32_t vMPLL_DQ_FUNC_CNTL_2; - uint32_t vMCLK_PWRMGT_CNTL; - uint32_t vDLL_CNTL; - uint32_t vMPLL_SS; - uint32_t vMPLL_SS2; - uint32_t mclk_value; -}; - -typedef struct RV770_SMC_MCLK_VALUE RV770_SMC_MCLK_VALUE; - - -struct RV730_SMC_MCLK_VALUE -{ - uint32_t vMCLK_PWRMGT_CNTL; - uint32_t vDLL_CNTL; - uint32_t vMPLL_FUNC_CNTL; - uint32_t vMPLL_FUNC_CNTL2; - uint32_t vMPLL_FUNC_CNTL3; - uint32_t vMPLL_SS; - uint32_t vMPLL_SS2; - uint32_t mclk_value; -}; - -typedef struct RV730_SMC_MCLK_VALUE RV730_SMC_MCLK_VALUE; - -struct RV770_SMC_VOLTAGE_VALUE -{ - uint16_t value; - uint8_t index; - uint8_t padding; -}; - -typedef struct RV770_SMC_VOLTAGE_VALUE RV770_SMC_VOLTAGE_VALUE; - -union RV7XX_SMC_MCLK_VALUE -{ - RV770_SMC_MCLK_VALUE mclk770; - RV730_SMC_MCLK_VALUE mclk730; -}; - -typedef union RV7XX_SMC_MCLK_VALUE RV7XX_SMC_MCLK_VALUE, *LPRV7XX_SMC_MCLK_VALUE; - -struct RV770_SMC_HW_PERFORMANCE_LEVEL -{ - uint8_t arbValue; - union{ - uint8_t seqValue; - uint8_t ACIndex; - }; - uint8_t displayWatermark; - uint8_t gen2PCIE; - uint8_t gen2XSP; - uint8_t backbias; - uint8_t strobeMode; - uint8_t mcFlags; - uint32_t aT; - uint32_t bSP; - RV770_SMC_SCLK_VALUE sclk; - RV7XX_SMC_MCLK_VALUE mclk; - RV770_SMC_VOLTAGE_VALUE vddc; - RV770_SMC_VOLTAGE_VALUE mvdd; - RV770_SMC_VOLTAGE_VALUE vddci; - uint8_t reserved1; - uint8_t reserved2; - uint8_t stateFlags; - uint8_t padding; -}; - -typedef struct RV770_SMC_HW_PERFORMANCE_LEVEL RV770_SMC_HW_PERFORMANCE_LEVEL; - -struct RV770_SMC_SWSTATE -{ - uint8_t flags; - uint8_t padding1; - uint8_t padding2; - uint8_t padding3; - RV770_SMC_HW_PERFORMANCE_LEVEL levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; -}; - -typedef struct RV770_SMC_SWSTATE RV770_SMC_SWSTATE; - -struct RV770_SMC_VOLTAGEMASKTABLE -{ - uint8_t highMask[RV770_SMC_VOLTAGEMASK_MAX]; - uint32_t lowMask[RV770_SMC_VOLTAGEMASK_MAX]; -}; - -typedef struct RV770_SMC_VOLTAGEMASKTABLE RV770_SMC_VOLTAGEMASKTABLE; - -struct RV770_SMC_STATETABLE -{ - uint8_t thermalProtectType; - uint8_t systemFlags; - uint8_t maxVDDCIndexInPPTable; - uint8_t extraFlags; - uint8_t highSMIO[MAX_NO_VREG_STEPS]; - uint32_t lowSMIO[MAX_NO_VREG_STEPS]; - RV770_SMC_VOLTAGEMASKTABLE voltageMaskTable; - RV770_SMC_SWSTATE initialState; - RV770_SMC_SWSTATE ACPIState; - RV770_SMC_SWSTATE driverState; - RV770_SMC_SWSTATE ULVState; -}; - -typedef struct RV770_SMC_STATETABLE RV770_SMC_STATETABLE; - -struct vddc_table_entry { - u16 vddc; - u8 vddc_index; - u8 high_smio; - u32 low_smio; -}; - -struct rv770_clock_registers { - u32 cg_spll_func_cntl; - u32 cg_spll_func_cntl_2; - u32 cg_spll_func_cntl_3; - u32 cg_spll_spread_spectrum; - u32 cg_spll_spread_spectrum_2; - u32 mpll_ad_func_cntl; - u32 mpll_ad_func_cntl_2; - u32 mpll_dq_func_cntl; - u32 mpll_dq_func_cntl_2; - u32 mclk_pwrmgt_cntl; - u32 dll_cntl; - u32 mpll_ss1; - u32 mpll_ss2; -}; - -struct rv730_clock_registers { - u32 cg_spll_func_cntl; - u32 cg_spll_func_cntl_2; - u32 cg_spll_func_cntl_3; - u32 cg_spll_spread_spectrum; - u32 cg_spll_spread_spectrum_2; - u32 mclk_pwrmgt_cntl; - u32 dll_cntl; - u32 mpll_func_cntl; - u32 mpll_func_cntl2; - u32 mpll_func_cntl3; - u32 mpll_ss; - u32 mpll_ss2; -}; - -union r7xx_clock_registers { - struct rv770_clock_registers rv770; - struct rv730_clock_registers rv730; -}; - struct rv7xx_power_info { /* flags */ - bool mem_gddr5; - bool pcie_gen2; - bool dynamic_pcie_gen2; - bool acpi_pcie_gen2; - bool boot_in_gen2; bool voltage_control; /* vddc */ bool mvdd_control; bool sclk_ss; bool mclk_ss; bool dynamic_ss; - bool gfx_clock_gating; - bool mg_clock_gating; - bool mgcgtssm; - bool power_gating; bool thermal_protection; - bool display_gap; - bool dcodt; - bool ulps; - /* registers */ - union r7xx_clock_registers clk_regs; - u32 s0_vid_lower_smio_cntl; /* voltage */ - u32 vddc_mask_low; - u32 mvdd_mask_low; u32 mvdd_split_frequency; - u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES]; u16 max_vddc; u16 max_vddc_in_table; u16 min_vddc_in_table; - struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS]; - u8 valid_vddc_entries; - /* dc odt */ - u32 mclk_odt_threshold; - u8 odt_value_0[2]; - u8 odt_value_1[2]; /* stored values */ - u32 boot_sclk; u16 acpi_vddc; u32 ref_div; u32 active_auto_throttle_sources; @@ -582,17 +239,6 @@ struct rv7xx_power_info { u32 asi; u32 pasi; u32 vrc; - u32 restricted_levels; - u32 rlp; - u32 rmp; - u32 lhp; - u32 lmp; - /* smc offsets */ - u16 state_table_start; - u16 soft_regs_start; - u16 sram_end; - /* scratch structs */ - RV770_SMC_STATETABLE smc_statetable; }; enum si_pcie_gen { @@ -611,44 +257,12 @@ struct rv7xx_pl { enum si_pcie_gen pcie_gen; /* si+ only */ }; -struct rv7xx_ps { - struct rv7xx_pl high; - struct rv7xx_pl medium; - struct rv7xx_pl low; - bool dc_compatible; -}; - struct si_ps { u16 performance_level_count; bool dc_compatible; struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; }; -struct ni_mc_reg_table { - u8 last; - u8 num_entries; - u16 valid_flag; - struct ni_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; - SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; -}; - -struct ni_cac_data -{ - struct ni_leakage_coeffients leakage_coefficients; - u32 i_leakage; - s32 leakage_minimum_temperature; - u32 pwr_const; - u32 dc_cac_value; - u32 bif_cac_value; - u32 lkge_pwr; - u8 mc_wr_weight; - u8 mc_rd_weight; - u8 allow_ovrflw; - u8 num_win_tdp; - u8 l2num_win_tdp; - u8 lts_truncate_n; -}; - struct evergreen_power_info { /* must be first! */ struct rv7xx_power_info rv7xx; @@ -657,203 +271,33 @@ struct evergreen_power_info { bool dynamic_ac_timing; bool abm; bool mcls; - bool light_sleep; - bool memory_transition; bool pcie_performance_request; - bool pcie_performance_request_registered; bool sclk_deep_sleep; - bool dll_default_on; - bool ls_clock_gating; bool smu_uvd_hs; bool uvd_enabled; /* stored values */ u16 acpi_vddci; - u8 mvdd_high_index; - u8 mvdd_low_index; u32 mclk_edc_wr_enable_threshold; - struct evergreen_mc_reg_table mc_reg_table; struct atom_voltage_table vddc_voltage_table; struct atom_voltage_table vddci_voltage_table; - struct evergreen_arb_registers bootup_arb_registers; - struct evergreen_ulv_param ulv; - struct at ats[2]; - /* smc offsets */ - u16 mc_reg_table_start; struct amdgpu_ps current_rps; - struct rv7xx_ps current_ps; struct amdgpu_ps requested_rps; - struct rv7xx_ps requested_ps; -}; - -struct PP_NIslands_Dpm2PerfLevel -{ - uint8_t MaxPS; - uint8_t TgtAct; - uint8_t MaxPS_StepInc; - uint8_t MaxPS_StepDec; - uint8_t PSST; - uint8_t NearTDPDec; - uint8_t AboveSafeInc; - uint8_t BelowSafeInc; - uint8_t PSDeltaLimit; - uint8_t PSDeltaWin; - uint8_t Reserved[6]; -}; - -typedef struct PP_NIslands_Dpm2PerfLevel PP_NIslands_Dpm2PerfLevel; - -struct PP_NIslands_DPM2Parameters -{ - uint32_t TDPLimit; - uint32_t NearTDPLimit; - uint32_t SafePowerLimit; - uint32_t PowerBoostLimit; -}; -typedef struct PP_NIslands_DPM2Parameters PP_NIslands_DPM2Parameters; - -struct NISLANDS_SMC_SCLK_VALUE -{ - uint32_t vCG_SPLL_FUNC_CNTL; - uint32_t vCG_SPLL_FUNC_CNTL_2; - uint32_t vCG_SPLL_FUNC_CNTL_3; - uint32_t vCG_SPLL_FUNC_CNTL_4; - uint32_t vCG_SPLL_SPREAD_SPECTRUM; - uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; - uint32_t sclk_value; -}; - -typedef struct NISLANDS_SMC_SCLK_VALUE NISLANDS_SMC_SCLK_VALUE; - -struct NISLANDS_SMC_MCLK_VALUE -{ - uint32_t vMPLL_FUNC_CNTL; - uint32_t vMPLL_FUNC_CNTL_1; - uint32_t vMPLL_FUNC_CNTL_2; - uint32_t vMPLL_AD_FUNC_CNTL; - uint32_t vMPLL_AD_FUNC_CNTL_2; - uint32_t vMPLL_DQ_FUNC_CNTL; - uint32_t vMPLL_DQ_FUNC_CNTL_2; - uint32_t vMCLK_PWRMGT_CNTL; - uint32_t vDLL_CNTL; - uint32_t vMPLL_SS; - uint32_t vMPLL_SS2; - uint32_t mclk_value; -}; - -typedef struct NISLANDS_SMC_MCLK_VALUE NISLANDS_SMC_MCLK_VALUE; - -struct NISLANDS_SMC_VOLTAGE_VALUE -{ - uint16_t value; - uint8_t index; - uint8_t padding; -}; - -typedef struct NISLANDS_SMC_VOLTAGE_VALUE NISLANDS_SMC_VOLTAGE_VALUE; - -struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL -{ - uint8_t arbValue; - uint8_t ACIndex; - uint8_t displayWatermark; - uint8_t gen2PCIE; - uint8_t reserved1; - uint8_t reserved2; - uint8_t strobeMode; - uint8_t mcFlags; - uint32_t aT; - uint32_t bSP; - NISLANDS_SMC_SCLK_VALUE sclk; - NISLANDS_SMC_MCLK_VALUE mclk; - NISLANDS_SMC_VOLTAGE_VALUE vddc; - NISLANDS_SMC_VOLTAGE_VALUE mvdd; - NISLANDS_SMC_VOLTAGE_VALUE vddci; - NISLANDS_SMC_VOLTAGE_VALUE std_vddc; - uint32_t powergate_en; - uint8_t hUp; - uint8_t hDown; - uint8_t stateFlags; - uint8_t arbRefreshState; - uint32_t SQPowerThrottle; - uint32_t SQPowerThrottle_2; - uint32_t reserved[2]; - PP_NIslands_Dpm2PerfLevel dpm2; -}; - -typedef struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL NISLANDS_SMC_HW_PERFORMANCE_LEVEL; - -struct NISLANDS_SMC_SWSTATE -{ - uint8_t flags; - uint8_t levelCount; - uint8_t padding2; - uint8_t padding3; - NISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[]; -}; - -typedef struct NISLANDS_SMC_SWSTATE NISLANDS_SMC_SWSTATE; - -struct NISLANDS_SMC_VOLTAGEMASKTABLE -{ - uint8_t highMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; - uint32_t lowMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; -}; - -typedef struct NISLANDS_SMC_VOLTAGEMASKTABLE NISLANDS_SMC_VOLTAGEMASKTABLE; - -#define NISLANDS_MAX_NO_VREG_STEPS 32 - -struct NISLANDS_SMC_STATETABLE -{ - uint8_t thermalProtectType; - uint8_t systemFlags; - uint8_t maxVDDCIndexInPPTable; - uint8_t extraFlags; - uint8_t highSMIO[NISLANDS_MAX_NO_VREG_STEPS]; - uint32_t lowSMIO[NISLANDS_MAX_NO_VREG_STEPS]; - NISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable; - PP_NIslands_DPM2Parameters dpm2Params; - NISLANDS_SMC_SWSTATE initialState; - NISLANDS_SMC_SWSTATE ACPIState; - NISLANDS_SMC_SWSTATE ULVState; - NISLANDS_SMC_SWSTATE driverState; - NISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1]; }; -typedef struct NISLANDS_SMC_STATETABLE NISLANDS_SMC_STATETABLE; - struct ni_power_info { /* must be first! */ struct evergreen_power_info eg; - struct ni_clock_registers clock_registers; - struct ni_mc_reg_table mc_reg_table; u32 mclk_rtt_mode_threshold; /* flags */ - bool use_power_boost_limit; bool support_cac_long_term_average; bool cac_enabled; bool cac_configuration_required; bool driver_calculate_cac_leakage; - bool pc_enabled; bool enable_power_containment; bool enable_cac; bool enable_sq_ramping; - /* smc offsets */ - u16 arb_table_start; - u16 fan_table_start; - u16 cac_table_start; - u16 spll_table_start; - /* CAC stuff */ - struct ni_cac_data cac_data; - u32 dc_cac_table[NISLANDS_DCCAC_MAX_LEVELS]; - const struct ni_cac_weights *cac_weights; - u8 lta_window_size; - u8 lts_truncate; struct si_ps current_ps; struct si_ps requested_ps; - /* scratch structs */ - SMC_NIslands_MCRegisters smc_mc_reg_table; - NISLANDS_SMC_STATETABLE smc_statetable; }; struct si_cac_config_reg @@ -952,7 +396,6 @@ struct si_leakage_voltage struct si_leakage_voltage_entry entries[SISLANDS_MAX_LEAKAGE_COUNT]; }; - struct si_ulv_param { bool supported; u32 cg_ulv_control; From 0885f782e851a4b1e6b110b1b8376ebaf4b267c7 Mon Sep 17 00:00:00 2001 From: Jiapeng Chong Date: Thu, 30 Oct 2025 09:56:31 +0800 Subject: [PATCH 2433/2653] drm/amd/display: remove unneeded semicolon No functional modification involved. ./drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c:1674:3-4: Unneeded semicolon. Reported-by: Abaci Robot Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=26821 Signed-off-by: Jiapeng Chong Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 130058d7a70cd..875ae97489d32 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -1671,7 +1671,7 @@ enum dc_status dcn401_validate_bandwidth(struct dc *dc, dc_state_set_stream_cursor_subvp_limit(stream, context, true); status = DC_FAIL_HW_CURSOR_SUPPORT; } - }; + } } if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_FAIL_HW_CURSOR_SUPPORT) { From fef978b2a39944772a21530b0a762f227a5ad4ef Mon Sep 17 00:00:00 2001 From: Jiapeng Chong Date: Thu, 30 Oct 2025 09:56:30 +0800 Subject: [PATCH 2434/2653] drm/amd/display: remove unneeded semicolon No functional modification involved. ./drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c:1850:3-4: Unneeded semicolon. Reported-by: Abaci Robot Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=26821 Signed-off-by: Jiapeng Chong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index 81e64e17d0cb9..df0b664c0cd29 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -1847,7 +1847,7 @@ enum dc_status dcn32_validate_bandwidth(struct dc *dc, dc_state_set_stream_cursor_subvp_limit(stream, context, true); status = DC_FAIL_HW_CURSOR_SUPPORT; } - }; + } } if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_FAIL_HW_CURSOR_SUPPORT) { From 3a0fef3bfc67e1f220b0a8ad08405be64690fb04 Mon Sep 17 00:00:00 2001 From: Jiapeng Chong Date: Thu, 30 Oct 2025 09:56:29 +0800 Subject: [PATCH 2435/2653] drm/amd/display: remove unneeded semicolon No functional modification involved. ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:7392:3-4: Unneeded semicolon. Reported-by: Abaci Robot Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=26821 Signed-off-by: Jiapeng Chong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9070dfa4f3ec2..ae3b8b7b64dee 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7509,7 +7509,7 @@ int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, default: dm_new_state->abm_sysfs_forbidden = true; dm_new_state->abm_level = val; - }; + } ret = 0; } From d6fc78aca28d73848d3031e4a4ecf67c52e6f15e Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Thu, 30 Oct 2025 15:37:37 +0100 Subject: [PATCH 2436/2653] MAINTAINERS: adjust file entry in AMD DISPLAY CORE - DML Commit e6a8a000cfe6 ("drm/amd/display: Rename dml2 to dml2_0 folder") renames the directory dml2 to dml2_0 in ./drivers/gpu/drm/amd/display/dc, but misses to adjust the file entry in AMD DISPLAY CORE - DML. Adjust the file entry after this directory renaming. Signed-off-by: Lukas Bulwahn Signed-off-by: Alex Deucher --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 3af8183fa1050..9c11f3a47ddd6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1071,7 +1071,7 @@ M: Austin Zheng M: Jun Lei S: Supported F: drivers/gpu/drm/amd/display/dc/dml/ -F: drivers/gpu/drm/amd/display/dc/dml2/ +F: drivers/gpu/drm/amd/display/dc/dml2_0/ AMD FAM15H PROCESSOR POWER MONITORING DRIVER M: Huang Rui From 2bf4dfdee4db3b21b9879870a062bd9acd6776cc Mon Sep 17 00:00:00 2001 From: Xiang Liu Date: Mon, 20 Oct 2025 16:44:29 +0800 Subject: [PATCH 2437/2653] drm/amd/ras: Correct info field of bad page threshold exceed CPER Correct valid_bits and ms_chk_bits of section info field for bad page threshold exceed CPER to match OOB's behavior. Signed-off-by: Xiang Liu Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/ras/rascore/ras_cper.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cper.c b/drivers/gpu/drm/amd/ras/rascore/ras_cper.c index 2343991adccf3..c2e9fa7c3e6cb 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_cper.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cper.c @@ -65,7 +65,6 @@ static void fill_section_hdr(struct ras_core_context *ras_core, hdr->error_severity = sev; hdr->valid_bits.platform_id = 1; - hdr->valid_bits.partition_id = 1; hdr->valid_bits.timestamp = 1; ras_core_get_device_system_info(ras_core, &dev_info); @@ -147,13 +146,19 @@ static int fill_section_fatal(struct ras_core_context *ras_core, } static int fill_section_runtime(struct ras_core_context *ras_core, - struct cper_section_runtime *runtime, struct ras_log_info *trace) + struct cper_section_runtime *runtime, struct ras_log_info *trace, + enum ras_cper_severity sev) { runtime->hdr.valid_bits.err_info_cnt = 1; runtime->hdr.valid_bits.err_context_cnt = 1; runtime->descriptor.error_type = RUNTIME; runtime->descriptor.ms_chk_bits.err_type_valid = 1; + if (sev == RAS_CPER_SEV_RMA) { + runtime->descriptor.valid_bits.ms_chk = 1; + runtime->descriptor.ms_chk_bits.err_type = 1; + runtime->descriptor.ms_chk_bits.pcc = 1; + } runtime->reg.reg_ctx_type = CPER_CTX_TYPE__CRASH; runtime->reg.reg_arr_size = sizeof(runtime->reg.reg_dump); @@ -189,7 +194,7 @@ static int cper_generate_runtime_record(struct ras_core_context *ras_core, fill_section_descriptor(ras_core, descriptor, sev, RUNTIME, RAS_NONSTD_SEC_OFFSET(hdr->sec_cnt, i), sizeof(struct cper_section_runtime)); - fill_section_runtime(ras_core, runtime, trace_arr[i]); + fill_section_runtime(ras_core, runtime, trace_arr[i], sev); } return 0; From 95eaa592efb7c4d7754f3b5b2ab451355ebd8e51 Mon Sep 17 00:00:00 2001 From: Xiang Liu Date: Thu, 23 Oct 2025 10:10:02 +0800 Subject: [PATCH 2438/2653] drm/amd/ras: Use correct severity for BP threshold exceed event The severity of CPER for BP threshold exceed event should be set as FATAL to match the OOB implementation. Signed-off-by: Xiang Liu Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/ras/rascore/ras_cper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cper.c b/drivers/gpu/drm/amd/ras/rascore/ras_cper.c index c2e9fa7c3e6cb..3c5bfa1c93f66 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_cper.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cper.c @@ -62,7 +62,7 @@ static void fill_section_hdr(struct ras_core_context *ras_core, hdr->signature[3] = 'R'; hdr->revision = CPER_HDR__REV_1; hdr->signature_end = 0xFFFFFFFF; - hdr->error_severity = sev; + hdr->error_severity = (sev == RAS_CPER_SEV_RMA ? RAS_CPER_SEV_FATAL_UE : sev); hdr->valid_bits.platform_id = 1; hdr->valid_bits.timestamp = 1; @@ -115,7 +115,7 @@ static int fill_section_descriptor(struct ras_core_context *ras_core, descriptor->sec_length = section_length; descriptor->valid_bits.fru_text = 1; descriptor->flag_bits.primary = 1; - descriptor->severity = sev; + descriptor->severity = (sev == RAS_CPER_SEV_RMA ? RAS_CPER_SEV_FATAL_UE : sev); descriptor->sec_type = sec_type; ras_core_get_device_system_info(ras_core, &dev_info); From 7c5a837663a0ab87ae997db205560bc75b56dc08 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Sat, 25 Oct 2025 23:29:36 -0500 Subject: [PATCH 2439/2653] drm/amdgpu: Drop PMFW RLC notifier from amdgpu_device_suspend() For S3 on vangogh, PMFW needs to be notified before the driver powers down RLC. This already happens in smu_disable_dpms() so drop the superfluous call in amdgpu_device_suspend(). Signed-off-by: Alex Deucher Co-developed-by: Mario Limonciello (AMD) Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello (AMD) --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ---- drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 18 ------------------ drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 2 -- 3 files changed, 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index e475d7eee21f8..cd51fafa4f55f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5331,10 +5331,6 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients) if (amdgpu_sriov_vf(adev)) amdgpu_virt_release_full_gpu(adev, false); - r = amdgpu_dpm_notify_rlc_state(adev, false); - if (r) - return r; - return 0; } diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index 758f5ea4b68f0..4b3de22f2ecc3 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -195,24 +195,6 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, return ret; } -int amdgpu_dpm_notify_rlc_state(struct amdgpu_device *adev, bool en) -{ - int ret = 0; - const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - - if (pp_funcs && pp_funcs->notify_rlc_state) { - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->notify_rlc_state( - adev->powerplay.pp_handle, - en); - - mutex_unlock(&adev->pm.mutex); - } - - return ret; -} - int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h index f824bc4bba9e7..ba6e650d66c91 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h @@ -424,8 +424,6 @@ int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev); int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, enum pp_mp1_state mp1_state); -int amdgpu_dpm_notify_rlc_state(struct amdgpu_device *adev, bool en); - int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev); int amdgpu_dpm_baco_exit(struct amdgpu_device *adev); From 5a127ad128cce7a32998925c54e05b31147f0775 Mon Sep 17 00:00:00 2001 From: "Mario Limonciello (AMD)" Date: Sat, 25 Oct 2025 23:29:37 -0500 Subject: [PATCH 2440/2653] drm/amd: Add an unwind for failures in amdgpu_device_ip_suspend_phase1() If any hardware IPs involved with the first phase of suspend fail, unwind all steps to restore back to original state. Signed-off-by: Mario Limonciello (AMD) Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index cd51fafa4f55f..320a594c90efb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -180,6 +180,7 @@ struct amdgpu_init_level amdgpu_init_minimal_xgmi = { BIT(AMD_IP_BLOCK_TYPE_COMMON) | BIT(AMD_IP_BLOCK_TYPE_IH) | BIT(AMD_IP_BLOCK_TYPE_PSP) }; +static int amdgpu_device_ip_resume_phase3(struct amdgpu_device *adev); static void amdgpu_device_load_switch_state(struct amdgpu_device *adev); @@ -3809,7 +3810,7 @@ static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) */ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) { - int i, r; + int i, r, rec; amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); @@ -3832,10 +3833,23 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) r = amdgpu_ip_block_suspend(&adev->ip_blocks[i]); if (r) - return r; + goto unwind; } return 0; +unwind: + rec = amdgpu_device_ip_resume_phase3(adev); + if (rec) + dev_err(adev->dev, + "amdgpu_device_ip_resume_phase3 failed during unwind: %d\n", + rec); + + amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW); + + amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); + amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); + + return r; } /** From a384ff5eea8c8745adf1f06bb85e4bc55fc1d069 Mon Sep 17 00:00:00 2001 From: "Mario Limonciello (AMD)" Date: Sat, 25 Oct 2025 23:29:38 -0500 Subject: [PATCH 2441/2653] drm/amd: Add an unwind for failures in amdgpu_device_ip_suspend_phase2() If any hardware IPs involved with the second phase of suspend fail, unwind all steps to restore back to original state. Signed-off-by: Mario Limonciello (AMD) Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 36 ++++++++++++++++++++-- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 320a594c90efb..a7e99e5a5910a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -180,6 +180,9 @@ struct amdgpu_init_level amdgpu_init_minimal_xgmi = { BIT(AMD_IP_BLOCK_TYPE_COMMON) | BIT(AMD_IP_BLOCK_TYPE_IH) | BIT(AMD_IP_BLOCK_TYPE_PSP) }; + +static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev); +static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev); static int amdgpu_device_ip_resume_phase3(struct amdgpu_device *adev); static void amdgpu_device_load_switch_state(struct amdgpu_device *adev); @@ -3865,7 +3868,7 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) */ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) { - int i, r; + int i, r, rec; if (adev->in_s0ix) amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry); @@ -3928,7 +3931,7 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) r = amdgpu_ip_block_suspend(&adev->ip_blocks[i]); if (r) - return r; + goto unwind; /* handle putting the SMC in the appropriate state */ if (!amdgpu_sriov_vf(adev)) { @@ -3938,13 +3941,40 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) dev_err(adev->dev, "SMC failed to set mp1 state %d, %d\n", adev->mp1_state, r); - return r; + goto unwind; } } } } return 0; +unwind: + /* suspend phase 2 = resume phase 1 + resume phase 2 */ + rec = amdgpu_device_ip_resume_phase1(adev); + if (rec) { + dev_err(adev->dev, + "amdgpu_device_ip_resume_phase1 failed during unwind: %d\n", + rec); + return r; + } + + rec = amdgpu_device_fw_loading(adev); + if (rec) { + dev_err(adev->dev, + "amdgpu_device_fw_loading failed during unwind: %d\n", + rec); + return r; + } + + rec = amdgpu_device_ip_resume_phase2(adev); + if (rec) { + dev_err(adev->dev, + "amdgpu_device_ip_resume_phase2 failed during unwind: %d\n", + rec); + return r; + } + + return r; } /** From d08fbf544c3bc0dd16e7c41985044e34f6cee07e Mon Sep 17 00:00:00 2001 From: "Mario Limonciello (AMD)" Date: Sat, 25 Oct 2025 23:29:39 -0500 Subject: [PATCH 2442/2653] drm/amd: Unwind for failed device suspend If device suspend has failed, add a recovery flow that will attempt to unwind the suspend and get things back up and running. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4627 Signed-off-by: Mario Limonciello (AMD) Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 65 +++++++++++++++++++--- 1 file changed, 58 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index a7e99e5a5910a..58e1986ac087e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5325,7 +5325,7 @@ void amdgpu_device_complete(struct drm_device *dev) int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients) { struct amdgpu_device *adev = drm_to_adev(dev); - int r = 0; + int r, rec; if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) return 0; @@ -5341,8 +5341,9 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients) return r; } - if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DEV_D3)) - dev_warn(adev->dev, "smart shift update failed\n"); + r = amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DEV_D3); + if (r) + goto unwind_sriov; if (notify_clients) drm_client_dev_suspend(adev_to_drm(adev), false); @@ -5353,16 +5354,16 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients) r = amdgpu_device_ip_suspend_phase1(adev); if (r) - return r; + goto unwind_smartshift; amdgpu_amdkfd_suspend(adev, !amdgpu_sriov_vf(adev) && !adev->in_runpm); r = amdgpu_userq_suspend(adev); if (r) - return r; + goto unwind_ip_phase1; r = amdgpu_device_evict_resources(adev); if (r) - return r; + goto unwind_userq; amdgpu_ttm_set_buffer_funcs_status(adev, false); @@ -5370,12 +5371,62 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients) r = amdgpu_device_ip_suspend_phase2(adev); if (r) - return r; + goto unwind_evict; if (amdgpu_sriov_vf(adev)) amdgpu_virt_release_full_gpu(adev, false); return 0; + +unwind_evict: + if (adev->mman.buffer_funcs_ring->sched.ready) + amdgpu_ttm_set_buffer_funcs_status(adev, true); + amdgpu_fence_driver_hw_init(adev); + +unwind_userq: + rec = amdgpu_userq_resume(adev); + if (rec) { + dev_warn(adev->dev, "failed to re-initialize user queues: %d\n", rec); + return r; + } + rec = amdgpu_amdkfd_resume(adev, !amdgpu_sriov_vf(adev) && !adev->in_runpm); + if (rec) { + dev_warn(adev->dev, "failed to re-initialize kfd: %d\n", rec); + return r; + } + +unwind_ip_phase1: + /* suspend phase 1 = resume phase 3 */ + rec = amdgpu_device_ip_resume_phase3(adev); + if (rec) { + dev_warn(adev->dev, "failed to re-initialize IPs phase1: %d\n", rec); + return r; + } + +unwind_smartshift: + rec = amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DEV_D0); + if (rec) { + dev_warn(adev->dev, "failed to re-update smart shift: %d\n", rec); + return r; + } + + if (notify_clients) + drm_client_dev_resume(adev_to_drm(adev), false); + + amdgpu_ras_resume(adev); + +unwind_sriov: + if (amdgpu_sriov_vf(adev)) { + rec = amdgpu_virt_request_full_gpu(adev, true); + if (rec) { + dev_warn(adev->dev, "failed to reinitialize sriov: %d\n", rec); + return r; + } + } + + adev->in_suspend = adev->in_s0ix = adev->in_s3 = false; + + return r; } static inline int amdgpu_virt_resume(struct amdgpu_device *adev) From a75f10a95687b99d7b1cb228f6899d8740372bed Mon Sep 17 00:00:00 2001 From: Sunday Clement Date: Mon, 27 Oct 2025 14:00:59 -0400 Subject: [PATCH 2443/2653] drm/amdkfd: Fix Unchecked Return Values Properly Check for return values from calls to debug functions in runtime_disable(). v2: storing the last non zero returned value from the loop. Signed-off-by: Sunday Clement Reviewed-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 2ddb83ae6f578..7dca694561504 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -3072,7 +3072,7 @@ static int runtime_enable(struct kfd_process *p, uint64_t r_debug, static int runtime_disable(struct kfd_process *p) { - int i = 0, ret; + int i = 0, ret = 0; bool was_enabled = p->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED; p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_DISABLED; @@ -3109,6 +3109,7 @@ static int runtime_disable(struct kfd_process *p) /* disable ttmp setup */ for (i = 0; i < p->n_pdds; i++) { struct kfd_process_device *pdd = p->pdds[i]; + int last_err = 0; if (kfd_dbg_is_per_vmid_supported(pdd->dev)) { pdd->spi_dbg_override = @@ -3118,14 +3119,17 @@ static int runtime_disable(struct kfd_process *p) pdd->dev->vm_info.last_vmid_kfd); if (!pdd->dev->kfd->shared_resources.enable_mes) - debug_refresh_runlist(pdd->dev->dqm); + last_err = debug_refresh_runlist(pdd->dev->dqm); else - kfd_dbg_set_mes_debug_mode(pdd, + last_err = kfd_dbg_set_mes_debug_mode(pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev)); + + if (last_err) + ret = last_err; } } - return 0; + return ret; } static int kfd_ioctl_runtime_enable(struct file *filep, struct kfd_process *p, void *data) From 136271260166ef5ac2aac53611e4dd46d3486499 Mon Sep 17 00:00:00 2001 From: "Mario Limonciello (AMD)" Date: Thu, 30 Oct 2025 14:39:43 -0500 Subject: [PATCH 2444/2653] drm/amd/display: Don't stretch non-native images by default in eDP commit 978fa2f6d0b12 ("drm/amd/display: Use scaling for non-native resolutions on eDP") started using the GPU scaler hardware to scale when a non-native resolution was picked on eDP. This scaling was done to fill the screen instead of maintain aspect ratio. The idea was supposed to be that if a different scaling behavior is preferred then the compositor would request it. The not following aspect ratio behavior however isn't desirable, so adjust it to follow aspect ratio and still try to fill screen. Note: This will lead to black bars in some cases for non-native resolutions. Compositors can request the previous behavior if desired. Fixes: 978fa2f6d0b12 ("drm/amd/display: Use scaling for non-native resolutions on eDP") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4538 Signed-off-by: Mario Limonciello (AMD) Acked-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ae3b8b7b64dee..7ca40ad8eb9f2 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8430,7 +8430,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, "mode %dx%d@%dHz is not native, enabling scaling\n", adjusted_mode->hdisplay, adjusted_mode->vdisplay, drm_mode_vrefresh(adjusted_mode)); - dm_new_connector_state->scaling = RMX_FULL; + dm_new_connector_state->scaling = RMX_ASPECT; } return 0; } From 04b8a89483331d094f60fde2ed2a5274e077bdf3 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Fri, 24 Oct 2025 10:51:52 +0800 Subject: [PATCH 2445/2653] drm/amdgpu: Implement user queue reset functionality This patch adds robust reset handling for user queues (userq) to improve recovery from queue failures. The key components include: 1. Queue detection and reset logic: - amdgpu_userq_detect_and_reset_queues() identifies failed queues - Per-IP detect_and_reset callbacks for targeted recovery - Falls back to full GPU reset when needed 2. Reset infrastructure: - Adds userq_reset_work workqueue for async reset handling - Implements pre/post reset handlers for queue state management - Integrates with existing GPU reset framework 3. Error handling improvements: - Enhanced state tracking with HUNG state - Automatic reset triggering on critical failures - VRAM loss handling during recovery 4. Integration points: - Added to device init/reset paths - Called during queue destroy, suspend, and isolation events - Handles both individual queue and full GPU resets The reset functionality works with both gfx/compute and sdma queues, providing better resilience against queue failures while minimizing disruption to unaffected queues. v2: add detection and reset calls when preemption/unmaped fails. add a per device userq counter for each user queue type.(Alex) v3: make sure we hold the adev->userq_mutex when we call amdgpu_userq_detect_and_reset_queues. (Alex) warn if the adev->userq_mutex is not held. v4: make sure we have all of the uqm->userq_mutex held. warn if the uqm->userq_mutex is not held. v5: Use array for user queue type counters.(Alex) all of the uqm->userq_mutex need to be held when calling detect and reset. (Alex) v6: fix lock dep warning in amdgpu_userq_fence_dence_driver_process v7: add the queue types in an array and use a loop in amdgpu_userq_detect_and_reset_queues (Lijo) v8: remove atomic_set(&userq_mgr->userq_count[i], 0). it should already be 0 since we kzalloc the structure (Alex) v9: For consistency with kernel queues, We may want something like: amdgpu_userq_is_reset_type_supported (Alex) Signed-off-by: Alex Deucher Signed-off-by: Jesse Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 + drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 214 +++++++++++++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 5 + 5 files changed, 217 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 8dbe378b53d43..1c812d5aa3f87 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1344,6 +1344,7 @@ struct amdgpu_device { bool apu_prefer_gtt; bool userq_halt_for_enforce_isolation; + struct work_struct userq_reset_work; struct amdgpu_uid *uid_info; /* KFD diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 58e1986ac087e..194df738635cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4687,6 +4687,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, } INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); + INIT_WORK(&adev->userq_reset_work, amdgpu_userq_reset_work); adev->gfx.gfx_off_req_count = 1; adev->gfx.gfx_off_residency = 0; @@ -6132,6 +6133,10 @@ int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context) if (r) goto out; + r = amdgpu_userq_post_reset(tmp_adev, vram_lost); + if (r) + goto out; + drm_client_dev_resume(adev_to_drm(tmp_adev), false); /* @@ -6356,6 +6361,7 @@ static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev) if (!amdgpu_sriov_vf(adev)) cancel_work(&adev->reset_work); #endif + cancel_work(&adev->userq_reset_work); if (adev->kfd.dev) cancel_work(&adev->kfd.reset_work); @@ -6476,6 +6482,8 @@ static void amdgpu_device_halt_activities(struct amdgpu_device *adev, amdgpu_device_ip_need_full_reset(tmp_adev)) amdgpu_ras_suspend(tmp_adev); + amdgpu_userq_pre_reset(tmp_adev); + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { struct amdgpu_ring *ring = tmp_adev->rings[i]; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 87b962df54607..7a27c6c4bb440 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -83,6 +83,7 @@ enum amdgpu_ring_type { AMDGPU_RING_TYPE_MES, AMDGPU_RING_TYPE_UMSCH_MM, AMDGPU_RING_TYPE_CPER, + AMDGPU_RING_TYPE_MAX, }; enum amdgpu_ib_pool_type { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index a4fd34a5fcc63..45adebf1042bb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -25,8 +25,10 @@ #include #include #include +#include #include "amdgpu.h" +#include "amdgpu_reset.h" #include "amdgpu_vm.h" #include "amdgpu_userq.h" #include "amdgpu_hmm.h" @@ -46,6 +48,107 @@ u32 amdgpu_userq_get_supported_ip_mask(struct amdgpu_device *adev) return userq_ip_mask; } +static bool amdgpu_userq_is_reset_type_supported(struct amdgpu_device *adev, + enum amdgpu_ring_type ring_type, int reset_type) +{ + + if (ring_type < 0 || ring_type >= AMDGPU_RING_TYPE_MAX) + return false; + + switch (ring_type) { + case AMDGPU_RING_TYPE_GFX: + if (adev->gfx.gfx_supported_reset & reset_type) + return true; + break; + case AMDGPU_RING_TYPE_COMPUTE: + if (adev->gfx.compute_supported_reset & reset_type) + return true; + break; + case AMDGPU_RING_TYPE_SDMA: + if (adev->sdma.supported_reset & reset_type) + return true; + break; + case AMDGPU_RING_TYPE_VCN_DEC: + case AMDGPU_RING_TYPE_VCN_ENC: + if (adev->vcn.supported_reset & reset_type) + return true; + break; + case AMDGPU_RING_TYPE_VCN_JPEG: + if (adev->jpeg.supported_reset & reset_type) + return true; + break; + default: + break; + } + return false; +} + +static void amdgpu_userq_gpu_reset(struct amdgpu_device *adev) +{ + if (amdgpu_device_should_recover_gpu(adev)) { + amdgpu_reset_domain_schedule(adev->reset_domain, + &adev->userq_reset_work); + /* Wait for the reset job to complete */ + flush_work(&adev->userq_reset_work); + } +} + +static int +amdgpu_userq_detect_and_reset_queues(struct amdgpu_userq_mgr *uq_mgr) +{ + struct amdgpu_device *adev = uq_mgr->adev; + const int queue_types[] = { + AMDGPU_RING_TYPE_COMPUTE, + AMDGPU_RING_TYPE_GFX, + AMDGPU_RING_TYPE_SDMA + }; + const int num_queue_types = ARRAY_SIZE(queue_types); + bool gpu_reset = false; + int r = 0; + int i; + + /* Warning if current process mutex is not held */ + WARN_ON(!mutex_is_locked(&uq_mgr->userq_mutex)); + + if (unlikely(adev->debug_disable_gpu_ring_reset)) { + dev_err(adev->dev, "userq reset disabled by debug mask\n"); + return 0; + } + + /* + * If GPU recovery feature is disabled system-wide, + * skip all reset detection logic + */ + if (!amdgpu_gpu_recovery) + return 0; + + /* + * Iterate through all queue types to detect and reset problematic queues + * Process each queue type in the defined order + */ + for (i = 0; i < num_queue_types; i++) { + int ring_type = queue_types[i]; + const struct amdgpu_userq_funcs *funcs = adev->userq_funcs[ring_type]; + + if (!amdgpu_userq_is_reset_type_supported(adev, ring_type, AMDGPU_RESET_TYPE_PER_QUEUE)) + continue; + + if (atomic_read(&uq_mgr->userq_count[ring_type]) > 0 && + funcs && funcs->detect_and_reset) { + r = funcs->detect_and_reset(adev, ring_type); + if (r) { + gpu_reset = true; + break; + } + } + } + + if (gpu_reset) + amdgpu_userq_gpu_reset(adev); + + return r; +} + static int amdgpu_userq_buffer_va_list_add(struct amdgpu_usermode_queue *queue, struct amdgpu_bo_va_mapping *va_map, u64 addr) { @@ -176,17 +279,22 @@ amdgpu_userq_preempt_helper(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_device *adev = uq_mgr->adev; const struct amdgpu_userq_funcs *userq_funcs = adev->userq_funcs[queue->queue_type]; + bool found_hung_queue = false; int r = 0; if (queue->state == AMDGPU_USERQ_STATE_MAPPED) { r = userq_funcs->preempt(uq_mgr, queue); if (r) { queue->state = AMDGPU_USERQ_STATE_HUNG; + found_hung_queue = true; } else { queue->state = AMDGPU_USERQ_STATE_PREEMPTED; } } + if (found_hung_queue) + amdgpu_userq_detect_and_reset_queues(uq_mgr); + return r; } @@ -218,16 +326,23 @@ amdgpu_userq_unmap_helper(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_device *adev = uq_mgr->adev; const struct amdgpu_userq_funcs *userq_funcs = adev->userq_funcs[queue->queue_type]; + bool found_hung_queue = false; int r = 0; if ((queue->state == AMDGPU_USERQ_STATE_MAPPED) || (queue->state == AMDGPU_USERQ_STATE_PREEMPTED)) { r = userq_funcs->unmap(uq_mgr, queue); - if (r) + if (r) { queue->state = AMDGPU_USERQ_STATE_HUNG; - else + found_hung_queue = true; + } else { queue->state = AMDGPU_USERQ_STATE_UNMAPPED; + } } + + if (found_hung_queue) + amdgpu_userq_detect_and_reset_queues(uq_mgr); + return r; } @@ -244,10 +359,12 @@ amdgpu_userq_map_helper(struct amdgpu_userq_mgr *uq_mgr, r = userq_funcs->map(uq_mgr, queue); if (r) { queue->state = AMDGPU_USERQ_STATE_HUNG; + amdgpu_userq_detect_and_reset_queues(uq_mgr); } else { queue->state = AMDGPU_USERQ_STATE_MAPPED; } } + return r; } @@ -475,10 +592,11 @@ amdgpu_userq_destroy(struct drm_file *filp, int queue_id) amdgpu_bo_unreserve(queue->db_obj.obj); } amdgpu_bo_unref(&queue->db_obj.obj); - + atomic_dec(&uq_mgr->userq_count[queue->queue_type]); #if defined(CONFIG_DEBUG_FS) debugfs_remove_recursive(queue->debugfs_queue); #endif + amdgpu_userq_detect_and_reset_queues(uq_mgr); r = amdgpu_userq_unmap_helper(uq_mgr, queue); /*TODO: It requires a reset for userq hw unmap error*/ if (unlikely(r != AMDGPU_USERQ_STATE_UNMAPPED)) { @@ -707,6 +825,7 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) #endif args->out.queue_id = qid; + atomic_inc(&uq_mgr->userq_count[queue->queue_type]); unlock: mutex_unlock(&uq_mgr->userq_mutex); @@ -1064,6 +1183,7 @@ amdgpu_userq_evict_all(struct amdgpu_userq_mgr *uq_mgr) unsigned long queue_id; int ret = 0, r; + amdgpu_userq_detect_and_reset_queues(uq_mgr); /* Try to unmap all the queues in this process ctx */ xa_for_each(&uq_mgr->userq_mgr_xa, queue_id, queue) { r = amdgpu_userq_preempt_helper(uq_mgr, queue); @@ -1076,6 +1196,23 @@ amdgpu_userq_evict_all(struct amdgpu_userq_mgr *uq_mgr) return ret; } +void amdgpu_userq_reset_work(struct work_struct *work) +{ + struct amdgpu_device *adev = container_of(work, struct amdgpu_device, + userq_reset_work); + struct amdgpu_reset_context reset_context; + + memset(&reset_context, 0, sizeof(reset_context)); + + reset_context.method = AMD_RESET_METHOD_NONE; + reset_context.reset_req_dev = adev; + reset_context.src = AMDGPU_RESET_SRC_USERQ; + set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); + /*set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags);*/ + + amdgpu_device_gpu_recover(adev, NULL, &reset_context); +} + static int amdgpu_userq_wait_for_signal(struct amdgpu_userq_mgr *uq_mgr) { @@ -1103,22 +1240,19 @@ void amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_eviction_fence *ev_fence) { - int ret; struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr); struct amdgpu_eviction_fence_mgr *evf_mgr = &fpriv->evf_mgr; + struct amdgpu_device *adev = uq_mgr->adev; + int ret; /* Wait for any pending userqueue fence work to finish */ ret = amdgpu_userq_wait_for_signal(uq_mgr); - if (ret) { - drm_file_err(uq_mgr->file, "Not evicting userqueue, timeout waiting for work\n"); - return; - } + if (ret) + dev_err(adev->dev, "Not evicting userqueue, timeout waiting for work\n"); ret = amdgpu_userq_evict_all(uq_mgr); - if (ret) { - drm_file_err(uq_mgr->file, "Failed to evict userqueue\n"); - return; - } + if (ret) + dev_err(adev->dev, "Failed to evict userqueue\n"); /* Signal current eviction fence */ amdgpu_eviction_fence_signal(evf_mgr, ev_fence); @@ -1152,6 +1286,7 @@ void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr) cancel_delayed_work_sync(&userq_mgr->resume_work); mutex_lock(&userq_mgr->userq_mutex); + amdgpu_userq_detect_and_reset_queues(userq_mgr); xa_for_each(&userq_mgr->userq_mgr_xa, queue_id, queue) { amdgpu_userq_wait_for_last_fence(userq_mgr, queue); amdgpu_userq_unmap_helper(userq_mgr, queue); @@ -1178,6 +1313,7 @@ int amdgpu_userq_suspend(struct amdgpu_device *adev) uqm = queue->userq_mgr; cancel_delayed_work_sync(&uqm->resume_work); guard(mutex)(&uqm->userq_mutex); + amdgpu_userq_detect_and_reset_queues(uqm); if (adev->in_s0ix) r = amdgpu_userq_preempt_helper(uqm, queue); else @@ -1236,6 +1372,7 @@ int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev, if (((queue->queue_type == AMDGPU_HW_IP_GFX) || (queue->queue_type == AMDGPU_HW_IP_COMPUTE)) && (queue->xcp_id == idx)) { + amdgpu_userq_detect_and_reset_queues(uqm); r = amdgpu_userq_preempt_helper(uqm, queue); if (r) ret = r; @@ -1308,3 +1445,56 @@ int amdgpu_userq_gem_va_unmap_validate(struct amdgpu_device *adev, return 0; } + +void amdgpu_userq_pre_reset(struct amdgpu_device *adev) +{ + const struct amdgpu_userq_funcs *userq_funcs; + struct amdgpu_usermode_queue *queue; + struct amdgpu_userq_mgr *uqm; + unsigned long queue_id; + + xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { + uqm = queue->userq_mgr; + cancel_delayed_work_sync(&uqm->resume_work); + if (queue->state == AMDGPU_USERQ_STATE_MAPPED) { + amdgpu_userq_wait_for_last_fence(uqm, queue); + userq_funcs = adev->userq_funcs[queue->queue_type]; + userq_funcs->unmap(uqm, queue); + /* just mark all queues as hung at this point. + * if unmap succeeds, we could map again + * in amdgpu_userq_post_reset() if vram is not lost + */ + queue->state = AMDGPU_USERQ_STATE_HUNG; + amdgpu_userq_fence_driver_force_completion(queue); + } + } +} + +int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost) +{ + /* if any queue state is AMDGPU_USERQ_STATE_UNMAPPED + * at this point, we should be able to map it again + * and continue if vram is not lost. + */ + struct amdgpu_userq_mgr *uqm; + struct amdgpu_usermode_queue *queue; + const struct amdgpu_userq_funcs *userq_funcs; + unsigned long queue_id; + int r = 0; + + xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { + uqm = queue->userq_mgr; + if (queue->state == AMDGPU_USERQ_STATE_HUNG && !vram_lost) { + userq_funcs = adev->userq_funcs[queue->queue_type]; + /* Re-map queue */ + r = userq_funcs->map(uqm, queue); + if (r) { + dev_err(adev->dev, "Failed to remap queue %ld\n", queue_id); + continue; + } + queue->state = AMDGPU_USERQ_STATE_MAPPED; + } + } + + return r; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index bd6c226be36b0..56accf5232217 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -111,6 +111,7 @@ struct amdgpu_userq_mgr { struct amdgpu_device *adev; struct delayed_work resume_work; struct drm_file *file; + atomic_t userq_count[AMDGPU_RING_TYPE_MAX]; }; struct amdgpu_db_info { @@ -153,6 +154,10 @@ int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev, u32 idx); int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev, u32 idx); +void amdgpu_userq_reset_work(struct work_struct *work); +void amdgpu_userq_pre_reset(struct amdgpu_device *adev); +int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost); + int amdgpu_userq_input_va_validate(struct amdgpu_usermode_queue *queue, u64 addr, u64 expected_size); int amdgpu_userq_gem_va_unmap_validate(struct amdgpu_device *adev, From 77f086bdf9a1bc26abf822134d3a621296b3e9ca Mon Sep 17 00:00:00 2001 From: Wenjing Liu Date: Fri, 3 Oct 2025 11:59:39 -0400 Subject: [PATCH 2446/2653] drm/amd/display: fw locality check refactors [why] There are some new changes for HDCP2 firmware locality check. The implementation doesn't perfectly fit the intended design and clarity. 1. Clarify and consolidate variable responsibilities. The previous implementation introduced the following variables: - config.ddc.funcs.atomic_write_poll_read_i2c (optional pointer) - hdcp->config.ddc.funcs.atomic_write_poll_read_aux (optional pointer) - hdcp->connection.link.adjust.hdcp2.force_sw_locality_check (bool) - hdcp->config.debug.lc_enable_sw_fallback (bool) - use_fw (bool) They will be used together to determine two operations: - Whether to use FW locality check - Whether to use SW fallback on FW locality check failure The refactor streamlines this by introducing two variables in the hdcp2 link adjustment, while ensuring function pointers are always assigned and remain independent from policy decisions: - use_fw_locality_check (bool) -> true if fw locality should be used. - use_sw_locality_fallback (bool) -> true to reset use_fw_locality_check back to false and retry on fw locality check failure. 2. Mixed meanings of l_prime_read transition input l_prime_read originally means if l_prime is read when sw locality check is used. When FW locality check is used, l_prime_read means if lc init write, l prime poll and l_prime read combo operation is successful. The mix of meanings is confusing. The refactor introduces a new variable l_prime_combo_read to isolate the second meaning into its own variable. 3. Missing specific error code on firmware locality error. The original change reuses the generic DDC failure error code when firmware fails to return locality check result. This is not ideal as DDC failure indicates an error occurred during an I2C/AUX transaction. FW locality failure could be caused by polling timeout in firmware or failure to acquire firmware access. Which sits at a higher level of abstraction above DDC hardware. An incorrect error code could mislead the debug into a wrong direction. 4. Correcting misplaced comments. The previous implementation of the firmware locality check resulted in some comments in hdcp2_transition being incorrectly positioned. This refactor relocates those comments to their appropriate locations for better clarity. Reviewed-by: Aric Cyr Signed-off-by: Wenjing Liu Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 18 ++--- .../gpu/drm/amd/display/modules/hdcp/hdcp.h | 1 + .../display/modules/hdcp/hdcp2_execution.c | 68 ++++++------------- .../display/modules/hdcp/hdcp2_transition.c | 61 +++++++++-------- .../drm/amd/display/modules/hdcp/hdcp_ddc.c | 2 +- .../drm/amd/display/modules/hdcp/hdcp_log.c | 2 + .../drm/amd/display/modules/inc/mod_hdcp.h | 10 ++- 7 files changed, 71 insertions(+), 91 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index 9601dfa1651a0..206d3beccf829 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -201,6 +201,7 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_work, struct mod_hdcp_link_adjustment link_adjust; struct mod_hdcp_display_adjustment display_adjust; unsigned int conn_index = aconnector->base.index; + const struct dc *dc = aconnector->dc_link->dc; guard(mutex)(&hdcp_w->mutex); drm_connector_get(&aconnector->base); @@ -231,6 +232,9 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_work, link_adjust.hdcp1.disable = 1; link_adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_1; } + link_adjust.hdcp2.use_fw_locality_check = + (dc->caps.fused_io_supported || dc->debug.hdcp_lc_force_fw_enable); + link_adjust.hdcp2.use_sw_locality_fallback = dc->debug.hdcp_lc_enable_sw_fallback; schedule_delayed_work(&hdcp_w->property_validate_dwork, msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS)); @@ -540,6 +544,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; struct dc_sink *sink = NULL; bool link_is_hdcp14 = false; + const struct dc *dc = aconnector->dc_link->dc; if (config->dpms_off) { hdcp_remove_display(hdcp_work, link_index, aconnector); @@ -581,6 +586,8 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) link->adjust.auth_delay = 2; link->adjust.retry_limit = MAX_NUM_OF_ATTEMPTS; link->adjust.hdcp1.disable = 0; + link->adjust.hdcp2.use_fw_locality_check = (dc->caps.fused_io_supported || dc->debug.hdcp_lc_force_fw_enable); + link->adjust.hdcp2.use_sw_locality_fallback = dc->debug.hdcp_lc_enable_sw_fallback; hdcp_w->encryption_status[display->index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; #ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE @@ -807,15 +814,8 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, ddc_funcs->read_i2c = lp_read_i2c; ddc_funcs->write_dpcd = lp_write_dpcd; ddc_funcs->read_dpcd = lp_read_dpcd; - - config->debug.lc_enable_sw_fallback = dc->debug.hdcp_lc_enable_sw_fallback; - if (dc->caps.fused_io_supported || dc->debug.hdcp_lc_force_fw_enable) { - ddc_funcs->atomic_write_poll_read_i2c = lp_atomic_write_poll_read_i2c; - ddc_funcs->atomic_write_poll_read_aux = lp_atomic_write_poll_read_aux; - } else { - ddc_funcs->atomic_write_poll_read_i2c = NULL; - ddc_funcs->atomic_write_poll_read_aux = NULL; - } + ddc_funcs->atomic_write_poll_read_i2c = lp_atomic_write_poll_read_i2c; + ddc_funcs->atomic_write_poll_read_aux = lp_atomic_write_poll_read_aux; memset(hdcp_work[i].aconnector, 0, sizeof(struct amdgpu_dm_connector *) * diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h index b883d626f1c37..26a351a184f33 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h @@ -88,6 +88,7 @@ struct mod_hdcp_transition_input_hdcp2 { uint8_t lc_init_write; uint8_t l_prime_available_poll; uint8_t l_prime_read; + uint8_t l_prime_combo_read; uint8_t l_prime_validation; uint8_t eks_prepare; uint8_t eks_write; diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c index 5628f0ef73fd1..27500abf9fee3 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_execution.c @@ -465,54 +465,11 @@ static enum mod_hdcp_status validate_h_prime(struct mod_hdcp *hdcp, return status; } -static enum mod_hdcp_status locality_check_sw(struct mod_hdcp *hdcp, - struct mod_hdcp_event_context *event_ctx, - struct mod_hdcp_transition_input_hdcp2 *input) -{ - enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS; - - if (!mod_hdcp_execute_and_set(mod_hdcp_write_lc_init, - &input->lc_init_write, &status, - hdcp, "lc_init_write")) - goto out; - if (is_dp_hdcp(hdcp)) - msleep(16); - else - if (!mod_hdcp_execute_and_set(poll_l_prime_available, - &input->l_prime_available_poll, &status, - hdcp, "l_prime_available_poll")) - goto out; - if (!mod_hdcp_execute_and_set(mod_hdcp_read_l_prime, - &input->l_prime_read, &status, - hdcp, "l_prime_read")) - goto out; -out: - return status; -} - -static enum mod_hdcp_status locality_check_fw(struct mod_hdcp *hdcp, - struct mod_hdcp_event_context *event_ctx, - struct mod_hdcp_transition_input_hdcp2 *input) -{ - enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS; - - if (!mod_hdcp_execute_and_set(mod_hdcp_write_poll_read_lc_fw, - &input->l_prime_read, &status, - hdcp, "l_prime_read")) - goto out; - -out: - return status; -} - static enum mod_hdcp_status locality_check(struct mod_hdcp *hdcp, struct mod_hdcp_event_context *event_ctx, struct mod_hdcp_transition_input_hdcp2 *input) { enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS; - const bool use_fw = hdcp->config.ddc.funcs.atomic_write_poll_read_i2c - && hdcp->config.ddc.funcs.atomic_write_poll_read_aux - && !hdcp->connection.link.adjust.hdcp2.force_sw_locality_check; if (event_ctx->event != MOD_HDCP_EVENT_CALLBACK) { event_ctx->unexpected_event = 1; @@ -524,9 +481,28 @@ static enum mod_hdcp_status locality_check(struct mod_hdcp *hdcp, hdcp, "lc_init_prepare")) goto out; - status = (use_fw ? locality_check_fw : locality_check_sw)(hdcp, event_ctx, input); - if (status != MOD_HDCP_STATUS_SUCCESS) - goto out; + if (hdcp->connection.link.adjust.hdcp2.use_fw_locality_check) { + if (!mod_hdcp_execute_and_set(mod_hdcp_write_poll_read_lc_fw, + &input->l_prime_combo_read, &status, + hdcp, "l_prime_combo_read")) + goto out; + } else { + if (!mod_hdcp_execute_and_set(mod_hdcp_write_lc_init, + &input->lc_init_write, &status, + hdcp, "lc_init_write")) + goto out; + if (is_dp_hdcp(hdcp)) + msleep(16); + else + if (!mod_hdcp_execute_and_set(poll_l_prime_available, + &input->l_prime_available_poll, &status, + hdcp, "l_prime_available_poll")) + goto out; + if (!mod_hdcp_execute_and_set(mod_hdcp_read_l_prime, + &input->l_prime_read, &status, + hdcp, "l_prime_read")) + goto out; + } if (!mod_hdcp_execute_and_set(mod_hdcp_hdcp2_validate_l_prime, &input->l_prime_validation, &status, diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c index 89ffb89e19325..9316312a4df5b 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c @@ -184,31 +184,33 @@ enum mod_hdcp_status mod_hdcp_hdcp2_transition(struct mod_hdcp *hdcp, callback_in_ms(0, output); set_state_id(hdcp, output, H2_A2_LOCALITY_CHECK); break; - case H2_A2_LOCALITY_CHECK: { - const bool use_fw = hdcp->config.ddc.funcs.atomic_write_poll_read_i2c - && !adjust->hdcp2.force_sw_locality_check; - - /* - * 1A-05: consider disconnection after LC init a failure - * 1A-13-1: consider invalid l' a failure - * 1A-13-2: consider l' timeout a failure - */ + case H2_A2_LOCALITY_CHECK: + /* 1A-05: consider disconnection after LC init a failure */ if (hdcp->state.stay_count > 10 || - input->lc_init_prepare != PASS || - (!use_fw && input->lc_init_write != PASS) || - (!use_fw && input->l_prime_available_poll != PASS)) { + input->lc_init_prepare != PASS) { fail_and_restart_in_ms(0, &status, output); break; - } else if (input->l_prime_read != PASS) { - if (use_fw && hdcp->config.debug.lc_enable_sw_fallback) { - adjust->hdcp2.force_sw_locality_check = true; + } else if (adjust->hdcp2.use_fw_locality_check && + input->l_prime_combo_read != PASS) { + /* 1A-13-2: consider l' timeout a failure */ + if (adjust->hdcp2.use_sw_locality_fallback) { + /* switch to software locality check */ + adjust->hdcp2.use_fw_locality_check = 0; callback_in_ms(0, output); + increment_stay_counter(hdcp); break; } - + fail_and_restart_in_ms(0, &status, output); + break; + } else if (!adjust->hdcp2.use_fw_locality_check && + (input->lc_init_write != PASS || + input->l_prime_available_poll != PASS || + input->l_prime_read != PASS)) { + /* 1A-13-2: consider l' timeout a failure */ fail_and_restart_in_ms(0, &status, output); break; } else if (input->l_prime_validation != PASS) { + /* 1A-13-1: consider invalid l' a failure */ callback_in_ms(0, output); increment_stay_counter(hdcp); break; @@ -216,7 +218,6 @@ enum mod_hdcp_status mod_hdcp_hdcp2_transition(struct mod_hdcp *hdcp, callback_in_ms(0, output); set_state_id(hdcp, output, H2_A3_EXCHANGE_KS_AND_TEST_FOR_REPEATER); break; - } case H2_A3_EXCHANGE_KS_AND_TEST_FOR_REPEATER: if (input->eks_prepare != PASS || input->eks_write != PASS) { @@ -510,26 +511,29 @@ enum mod_hdcp_status mod_hdcp_hdcp2_dp_transition(struct mod_hdcp *hdcp, callback_in_ms(0, output); set_state_id(hdcp, output, D2_A2_LOCALITY_CHECK); break; - case D2_A2_LOCALITY_CHECK: { - const bool use_fw = hdcp->config.ddc.funcs.atomic_write_poll_read_aux - && !adjust->hdcp2.force_sw_locality_check; - + case D2_A2_LOCALITY_CHECK: if (hdcp->state.stay_count > 10 || - input->lc_init_prepare != PASS || - (!use_fw && input->lc_init_write != PASS)) { - /* 1A-12: consider invalid l' a failure */ + input->lc_init_prepare != PASS) { fail_and_restart_in_ms(0, &status, output); break; - } else if (input->l_prime_read != PASS) { - if (use_fw && hdcp->config.debug.lc_enable_sw_fallback) { - adjust->hdcp2.force_sw_locality_check = true; + } else if (adjust->hdcp2.use_fw_locality_check && + input->l_prime_combo_read != PASS) { + if (adjust->hdcp2.use_sw_locality_fallback) { + /* switch to software locality check */ + adjust->hdcp2.use_fw_locality_check = 0; callback_in_ms(0, output); + increment_stay_counter(hdcp); break; } - + fail_and_restart_in_ms(0, &status, output); + break; + } else if (!adjust->hdcp2.use_fw_locality_check && + (input->lc_init_write != PASS || + input->l_prime_read != PASS)) { fail_and_restart_in_ms(0, &status, output); break; } else if (input->l_prime_validation != PASS) { + /* 1A-12: consider invalid l' a failure */ callback_in_ms(0, output); increment_stay_counter(hdcp); break; @@ -537,7 +541,6 @@ enum mod_hdcp_status mod_hdcp_hdcp2_dp_transition(struct mod_hdcp *hdcp, callback_in_ms(0, output); set_state_id(hdcp, output, D2_A34_EXCHANGE_KS_AND_TEST_FOR_REPEATER); break; - } case D2_A34_EXCHANGE_KS_AND_TEST_FOR_REPEATER: if (input->eks_prepare != PASS || input->eks_write != PASS) { diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c index 2e64085791948..0ca39873f8073 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c @@ -758,6 +758,6 @@ enum mod_hdcp_status mod_hdcp_write_poll_read_lc_fw(struct mod_hdcp *hdcp) { const bool success = (is_dp_hdcp(hdcp) ? write_stall_read_lc_fw_aux : write_poll_read_lc_fw_i2c)(hdcp); - return success ? MOD_HDCP_STATUS_SUCCESS : MOD_HDCP_STATUS_DDC_FAILURE; + return success ? MOD_HDCP_STATUS_SUCCESS : MOD_HDCP_STATUS_HDCP2_LOCALITY_COMBO_READ_FAILURE; } diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c index 6b3b5f610907d..ac44ee1532fda 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c @@ -248,6 +248,8 @@ char *mod_hdcp_status_to_str(int32_t status) return "MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE"; case MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE: return "MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE"; + case MOD_HDCP_STATUS_HDCP2_LOCALITY_COMBO_READ_FAILURE: + return "MOD_HDCP_STATUS_HDCP2_LOCALITY_COMBO_READ_FAILURE"; default: return "MOD_HDCP_STATUS_UNKNOWN"; } diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h index 46e52fb3a1180..264348989e9bc 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h @@ -98,6 +98,7 @@ enum mod_hdcp_status { MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE, MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE, MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE, + MOD_HDCP_STATUS_HDCP2_LOCALITY_COMBO_READ_FAILURE, }; struct mod_hdcp_displayport { @@ -214,8 +215,9 @@ struct mod_hdcp_link_adjustment_hdcp2 { uint8_t force_type : 2; uint8_t force_no_stored_km : 1; uint8_t increase_h_prime_timeout: 1; - uint8_t force_sw_locality_check : 1; - uint8_t reserved : 2; + uint8_t use_fw_locality_check : 1; + uint8_t use_sw_locality_fallback: 1; + uint8_t reserved : 1; }; struct mod_hdcp_link_adjustment { @@ -317,10 +319,6 @@ struct mod_hdcp_display_query { struct mod_hdcp_config { struct mod_hdcp_psp psp; struct mod_hdcp_ddc ddc; - struct { - uint8_t lc_enable_sw_fallback : 1; - uint8_t reserved : 7; - } debug; uint8_t index; }; From 33279eb8f585a2ec9b9429a68d14d43144aa1c9c Mon Sep 17 00:00:00 2001 From: Andrew Mazour Date: Wed, 15 Oct 2025 12:19:49 -0400 Subject: [PATCH 2447/2653] drm/amd/display: Extend inbox0 lock to run Replay/PSR [Why] The inbox1 infrastructure is deprecated, so to support display power features requiring a DMUB interlock moving forward extend the inbox0 locking conditions to also include Replay or PSR. [How] Implemented a series of changes to improve HW lock handling: - Deprecated should_use_dmub_inbox1_lock() and guarded it with DCN401 flag. - Migrated lock checks into inbox0 helpers and added PSR/Replay enablement checks to ensure correct behavior. - Updated HWSS fast update path to acquire HW lock as needed using the new helpers. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Andrew Mazour Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 5 +- .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.c | 52 +++++++++++++------ .../drm/amd/display/dc/dce/dmub_hw_lock_mgr.h | 2 + 3 files changed, 41 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index f95cb0cf4b8a6..a7ec633b26c06 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -38,6 +38,7 @@ #include "dccg.h" #include "abm.h" #include "dcn10/dcn10_hubbub.h" +#include "dce/dmub_hw_lock_mgr.h" #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) #define MAX_NUM_MCACHE 8 @@ -764,7 +765,9 @@ void hwss_build_fast_sequence(struct dc *dc, if (dc->hwss.dmub_hw_control_lock_fast) { block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc; block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = true; - block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context); + block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = + dc_state_is_fams2_in_use(dc, context) || + dmub_hw_lock_mgr_does_link_require_lock(dc, stream->link); block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST; (*num_steps)++; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c index 39f5fa73c43e6..5bfa2b0d2afdc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c @@ -61,31 +61,49 @@ void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv, dc_dmub_srv_wait_for_inbox0_ack(dmub_srv); } -bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link) +bool dmub_hw_lock_mgr_does_link_require_lock(const struct dc *dc, const struct dc_link *link) { - /* ASIC doesn't support DMUB */ - if (!dc->ctx->dmub_srv) + if (!link) return false; - if (link) { + if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) + return true; - if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) - return true; + if (link->replay_settings.replay_feature_enabled) + return true; - if (link->replay_settings.replay_feature_enabled) - return true; + if (link->psr_settings.psr_version == DC_PSR_VERSION_1) { + struct dc_link *edp_links[MAX_NUM_EDP]; + int edp_num; - /* only use HW lock for PSR1 on single eDP */ - if (link->psr_settings.psr_version == DC_PSR_VERSION_1) { - struct dc_link *edp_links[MAX_NUM_EDP]; - int edp_num; + dc_get_edp_links(dc, edp_links, &edp_num); + if (edp_num == 1) + return true; + } + return false; +} - dc_get_edp_links(dc, edp_links, &edp_num); +bool dmub_hw_lock_mgr_does_context_require_lock(const struct dc *dc, const struct dc_state *context) +{ + if (!context) + return false; + for (int i = 0; i < context->stream_count; i++) { + const struct dc_link *link = context->streams[i]->link; - if (edp_num == 1) - return true; - } + if (dmub_hw_lock_mgr_does_link_require_lock(dc, link)) + return true; } - return false; } + +bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link) +{ + /* ASIC doesn't support DMUB */ + if (!dc->ctx->dmub_srv) + return false; + + if (dc->ctx->dce_version >= DCN_VERSION_4_01) + return false; + + return dmub_hw_lock_mgr_does_link_require_lock(dc, link); +} diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h index 9f53d2ea5fa59..4c80ca8484ad3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h @@ -46,5 +46,7 @@ void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv, * Return: true if the inbox1 lock should be used, false otherwise */ bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link); +bool dmub_hw_lock_mgr_does_link_require_lock(const struct dc *dc, const struct dc_link *link); +bool dmub_hw_lock_mgr_does_context_require_lock(const struct dc *dc, const struct dc_state *context); #endif /*_DMUB_HW_LOCK_MGR_H_ */ From 630cd9da4758f8df78778ea1fe8cb54b84bc13d7 Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Wed, 17 Sep 2025 10:38:37 -0500 Subject: [PATCH 2448/2653] drm/amd/display: Add pte_buffer_mode and force_one_row_for_frame in dchub reg [Why & How] Update structs for rq regs Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../amd/display/dc/dml2_0/dml21/inc/dml_top_dchub_registers.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_dchub_registers.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_dchub_registers.h index 8e5a30287220f..bf57df42d1d95 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_dchub_registers.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_dchub_registers.h @@ -121,6 +121,8 @@ struct dml2_display_rq_regs { uint32_t crq_expansion_mode; uint32_t plane1_base_address; uint32_t unbounded_request_enabled; + bool pte_buffer_mode; + bool force_one_row_for_frame; // MRQ uint32_t mrq_expansion_mode; From ad47af35241d05bbf24422e99f38d476d654c8fb Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Wed, 17 Sep 2025 12:56:00 -0400 Subject: [PATCH 2449/2653] drm/amd/display: Remove old PMO options [Why & How] Removes deprecated or unused PMO options. Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h | 2 -- .../dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h | 4 ++-- .../dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 6 +----- 3 files changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h index 13749c9fcf18b..da8e5c8b22446 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h @@ -423,7 +423,6 @@ struct dml2_stream_parameters { bool disable_dynamic_odm; bool disable_subvp; int minimum_vblank_idle_requirement_us; - bool minimize_active_latency_hiding; struct { struct { @@ -489,7 +488,6 @@ struct dml2_display_cfg { bool synchronize_ddr_displays_for_uclk_pstate_change; bool max_outstanding_when_urgent_expected_disable; bool enable_subvp_implicit_pmo; //enables PMO to switch pipe uclk strategy to subvp, and generate phantom programming - unsigned int best_effort_min_active_latency_hiding_us; bool all_streams_blanked; } overrides; }; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h index 4a9a0d5a09b76..e87d04a734b51 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h @@ -89,8 +89,8 @@ struct dml2_soc_qos_parameters { struct dml2_soc_power_management_parameters { double dram_clk_change_blackout_us; - double dram_clk_change_read_only_us; - double dram_clk_change_write_only_us; + double dram_clk_change_read_only_us; // deprecated + double dram_clk_change_write_only_us; // deprecated double fclk_change_blackout_us; double g7_ppt_blackout_us; double g7_temperature_read_blackout_us; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c index 5769c2638f9ad..abd210401fe22 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c @@ -1962,9 +1962,6 @@ static void reset_display_configuration(struct display_configuation_with_meta *d for (stream_index = 0; stream_index < display_config->display_config.num_streams; stream_index++) { display_config->stage3.stream_svp_meta[stream_index].valid = false; - - display_config->display_config.stream_descriptors[stream_index].overrides.minimize_active_latency_hiding = false; - display_config->display_config.overrides.best_effort_min_active_latency_hiding_us = 0; } for (plane_index = 0; plane_index < display_config->display_config.num_planes; plane_index++) { @@ -1997,7 +1994,6 @@ static void setup_planes_for_drr_by_mask(struct display_configuation_with_meta * plane->overrides.uclk_pstate_change_strategy = dml2_uclk_pstate_change_strategy_force_drr; display_config->stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_fw_drr; - } } } @@ -2063,7 +2059,6 @@ static void setup_planes_for_vblank_by_mask(struct display_configuation_with_met plane->overrides.reserved_vblank_time_ns); display_config->stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_vblank; - } } } @@ -2078,6 +2073,7 @@ static void setup_planes_for_vblank_drr_by_mask(struct display_configuation_with for (plane_index = 0; plane_index < display_config->display_config.num_planes; plane_index++) { if (is_bit_set_in_bitfield(plane_mask, plane_index)) { plane = &display_config->display_config.plane_descriptors[plane_index]; + plane->overrides.reserved_vblank_time_ns = (long)(pmo->soc_bb->power_management_parameters.dram_clk_change_blackout_us * 1000); display_config->stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_fw_vblank_drr; From 19ebb645bad4f2fe304d9c559c7efde7ae5f0365 Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Wed, 24 Sep 2025 10:23:24 -0400 Subject: [PATCH 2450/2653] drm/amd/display: Update P-state naming for clarity. [Why & How] P-state can refer to different things like UCLK P-state, PPT, or temp read Update naming for clarity Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../dml21/src/dml2_core/dml2_core_dcn4_calcs.c | 2 +- .../src/dml2_core/dml2_core_shared_types.h | 18 ++++++++++++------ .../dml21/src/dml2_core/dml2_core_utils.c | 2 ++ 3 files changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index f809c4073b430..e7a0f46e12898 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -13024,7 +13024,7 @@ void dml2_core_calcs_get_informative(const struct dml2_core_internal_display_mod out->informative.mode_support_info.InvalidCombinationOfMALLUseForPState = mode_lib->ms.support.InvalidCombinationOfMALLUseForPState; out->informative.mode_support_info.ExceededMALLSize = mode_lib->ms.support.ExceededMALLSize; out->informative.mode_support_info.EnoughWritebackUnits = mode_lib->ms.support.EnoughWritebackUnits; - out->informative.mode_support_info.temp_read_or_ppt_support = mode_lib->ms.support.temp_read_or_ppt_support; + out->informative.mode_support_info.temp_read_or_ppt_support = mode_lib->ms.support.global_temp_read_or_ppt_supported; out->informative.mode_support_info.g6_temp_read_support = mode_lib->ms.support.g6_temp_read_support; out->informative.mode_support_info.ExceededMultistreamSlots = mode_lib->ms.support.ExceededMultistreamSlots; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h index 051c31ec2f0e4..6d13d4c9b69a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h @@ -264,8 +264,11 @@ struct dml2_core_internal_mode_support_info { bool DCCMetaBufferSizeNotExceeded; enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES]; enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES]; + enum dml2_pstate_change_support temp_read_or_ppt_support[DML2_MAX_PLANES]; + bool global_dram_clock_change_support_required; bool global_dram_clock_change_supported; bool global_fclk_change_supported; + bool global_temp_read_or_ppt_supported; bool USRRetrainingSupport; bool AvgBandwidthSupport; bool UrgVactiveBandwidthSupport; @@ -336,7 +339,6 @@ struct dml2_core_internal_mode_support_info { bool incorrect_imall_usage; bool g6_temp_read_support; - bool temp_read_or_ppt_support; struct dml2_core_internal_watermarks watermarks; bool dcfclk_support; @@ -646,7 +648,7 @@ struct dml2_core_internal_mode_support { unsigned int DSTYAfterScaler[DML2_MAX_PLANES]; unsigned int DSTXAfterScaler[DML2_MAX_PLANES]; - enum dml2_pstate_method pstate_switch_modes[DML2_MAX_PLANES]; + enum dml2_pstate_method uclk_pstate_switch_modes[DML2_MAX_PLANES]; }; /// @brief A mega structure that houses various info for model programming step. @@ -837,6 +839,7 @@ struct dml2_core_internal_mode_program { double max_urgent_latency_us; double df_response_time_us; + enum dml2_pstate_method uclk_pstate_switch_modes[DML2_MAX_PLANES]; // ------------------- // Output // ------------------- @@ -963,11 +966,12 @@ struct dml2_core_internal_mode_program { double MaxActiveFCLKChangeLatencySupported; bool USRRetrainingSupport; bool g6_temp_read_support; - bool temp_read_or_ppt_support; enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES]; enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES]; + enum dml2_pstate_change_support temp_read_or_ppt_support[DML2_MAX_PLANES]; bool global_dram_clock_change_supported; bool global_fclk_change_supported; + bool global_temp_read_or_ppt_supported; double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES]; double WritebackAllowFCLKChangeEndPosition[DML2_MAX_PLANES]; double WritebackAllowDRAMClockChangeEndPosition[DML2_MAX_PLANES]; @@ -1313,7 +1317,7 @@ struct dml2_core_calcs_CalculateVMRowAndSwath_params { unsigned int HostVMMinPageSize; unsigned int DCCMetaBufferSizeBytes; bool mrq_present; - enum dml2_pstate_method *pstate_switch_modes; + enum dml2_pstate_method *uclk_pstate_switch_modes; // Output bool *PTEBufferSizeNotExceeded; @@ -1740,10 +1744,12 @@ struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_param unsigned int max_request_size_bytes; unsigned int *meta_row_height_l; unsigned int *meta_row_height_c; + enum dml2_pstate_method *uclk_pstate_switch_modes; // Output struct dml2_core_internal_watermarks *Watermark; enum dml2_pstate_change_support *DRAMClockChangeSupport; + bool *global_dram_clock_change_support_required; bool *global_dram_clock_change_supported; double *MaxActiveDRAMClockChangeLatencySupported; unsigned int *SubViewportLinesNeededInMALL; @@ -1754,10 +1760,10 @@ struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_param double *VActiveLatencyHidingMargin; double *VActiveLatencyHidingUs; bool *g6_temp_read_support; - bool *temp_read_or_ppt_support; + enum dml2_pstate_change_support *temp_read_or_ppt_support; + bool *global_temp_read_or_ppt_supported; }; - struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params { const struct dml2_display_cfg *display_cfg; unsigned int ConfigReturnBufferSizeInKByte; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c index 5f301befed167..b57d0f6ea6a1c 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c @@ -306,6 +306,8 @@ void dml2_core_utils_print_mode_support_info(const struct dml2_core_internal_mod DML_LOG_VERBOSE("DML: support: ExceededMALLSize = %d\n", support->ExceededMALLSize); if (!fail_only || support->g6_temp_read_support == 0) DML_LOG_VERBOSE("DML: support: g6_temp_read_support = %d\n", support->g6_temp_read_support); + if (!fail_only || (support->global_dram_clock_change_supported == 0 && support->global_dram_clock_change_support_required)) + DML_LOG_VERBOSE("DML: support: dram_clock_change_support = %d\n", support->global_dram_clock_change_supported); if (!fail_only || support->ImmediateFlipSupport == 0) DML_LOG_VERBOSE("DML: support: ImmediateFlipSupport = %d\n", support->ImmediateFlipSupport); if (!fail_only || support->LinkCapacitySupport == 0) From 0c507783d82b244b5fe38c549b06e18529efffed Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Fri, 3 Oct 2025 10:39:49 -0400 Subject: [PATCH 2451/2653] drm/amd/display: Refactor VActive implementation [Why & How] Refactors VActive accounting in PMO, and breaks down fill time requirement by P-State type as it can result in drasitcally different bandwidth requirements depending on the blackout length. Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../dml21/inc/dml_top_display_cfg_types.h | 12 +++++- .../dml21/inc/dml_top_soc_parameter_types.h | 2 +- .../dc/dml2_0/dml21/inc/dml_top_types.h | 8 ---- .../src/dml2_core/dml2_core_dcn4_calcs.c | 37 ++++++++-------- .../src/dml2_core/dml2_core_shared_types.h | 16 +++---- .../dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 14 +++---- .../src/inc/dml2_internal_shared_types.h | 42 +++++++++++-------- 7 files changed, 69 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h index da8e5c8b22446..35aa954248cdc 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h @@ -87,6 +87,15 @@ enum dml2_output_link_dp_rate { dml2_dp_rate_uhbr20 = 6 }; +enum dml2_pstate_type { + dml2_pstate_type_uclk = 0, + dml2_pstate_type_fclk = 1, + dml2_pstate_type_ppt = 2, + dml2_pstate_type_temp_read = 3, + dml2_pstate_type_dummy_pstate = 4, + dml2_pstate_type_count = 5 +}; + enum dml2_uclk_pstate_change_strategy { dml2_uclk_pstate_change_strategy_auto = 0, dml2_uclk_pstate_change_strategy_force_vactive = 1, @@ -393,8 +402,7 @@ struct dml2_plane_parameters { // reserved_vblank_time_ns is the minimum time to reserve in vblank for Twait // The actual reserved vblank time used for the corresponding stream in mode_programming would be at least as much as this per-plane override. long reserved_vblank_time_ns; - unsigned int max_vactive_det_fill_delay_us; // 0 = no reserved time, +ve = explicit max delay - unsigned int vactive_latency_to_hide_for_pstate_admissibility_us; + unsigned int max_vactive_det_fill_delay_us[dml2_pstate_type_count]; // 0 = no reserved time, +ve = explicit max delay unsigned int gpuvm_min_page_size_kbytes; unsigned int hostvm_min_page_size_kbytes; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h index e87d04a734b51..1fbc520c25404 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h @@ -191,7 +191,7 @@ struct dml2_ip_capabilities { unsigned int subvp_prefetch_end_to_mall_start_us; unsigned int subvp_fw_processing_delay; unsigned int max_vactive_det_fill_delay_us; - unsigned int ppt_max_allow_delay_ns; + unsigned int ppt_max_allow_delay_us; unsigned int temp_read_max_allow_delay_us; unsigned int dummy_pstate_max_allow_delay_us; /* FAMS2 delays */ diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h index 8646ce5f1c01f..d2584b00a19c7 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h @@ -195,14 +195,6 @@ struct dml2_mcache_surface_allocation { } informative; }; -enum dml2_pstate_type { - dml2_pstate_type_uclk, - dml2_pstate_type_ppt, - dml2_pstate_type_temp_read, - dml2_pstate_type_dummy_pstate, - dml2_pstate_type_count -}; - enum dml2_pstate_method { dml2_pstate_method_na = 0, /* hw exclusive modes */ diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index e7a0f46e12898..df81bd963bb88 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -6972,7 +6972,7 @@ static void calculate_bytes_to_fetch_required_to_hide_latency( stream_index = p->display_cfg->plane_descriptors[plane_index].stream_index; - dst_lines_to_hide = (unsigned int)math_ceil(p->latency_to_hide_us / + dst_lines_to_hide = (unsigned int)math_ceil(p->latency_to_hide_us[0] / ((double)p->display_cfg->stream_descriptors[stream_index].timing.h_total / (double)p->display_cfg->stream_descriptors[stream_index].timing.pixel_clock_khz * 1000.0)); @@ -7069,9 +7069,9 @@ static void calculate_excess_vactive_bandwidth_required( excess_vactive_fill_bw_l[plane_index] = 0.0; excess_vactive_fill_bw_c[plane_index] = 0.0; - if (display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us > 0) { - excess_vactive_fill_bw_l[plane_index] = (double)bytes_required_l[plane_index] / (double)display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us; - excess_vactive_fill_bw_c[plane_index] = (double)bytes_required_c[plane_index] / (double)display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us; + if (display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[dml2_pstate_type_uclk] > 0) { + excess_vactive_fill_bw_l[plane_index] = (double)bytes_required_l[plane_index] / (double)display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[dml2_pstate_type_uclk]; + excess_vactive_fill_bw_c[plane_index] = (double)bytes_required_c[plane_index] / (double)display_cfg->plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[dml2_pstate_type_uclk]; } } } @@ -9051,11 +9051,11 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out calculate_bytes_to_fetch_required_to_hide_latency_params->swath_width_c = mode_lib->ms.SwathWidthC; calculate_bytes_to_fetch_required_to_hide_latency_params->swath_height_l = mode_lib->ms.SwathHeightY; calculate_bytes_to_fetch_required_to_hide_latency_params->swath_height_c = mode_lib->ms.SwathHeightC; - calculate_bytes_to_fetch_required_to_hide_latency_params->latency_to_hide_us = mode_lib->soc.power_management_parameters.dram_clk_change_blackout_us; + calculate_bytes_to_fetch_required_to_hide_latency_params->latency_to_hide_us[0] = mode_lib->soc.power_management_parameters.dram_clk_change_blackout_us; /* outputs */ - calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_l = s->pstate_bytes_required_l; - calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_c = s->pstate_bytes_required_c; + calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_l = s->pstate_bytes_required_l[dml2_pstate_type_uclk]; + calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_c = s->pstate_bytes_required_c[dml2_pstate_type_uclk]; calculate_bytes_to_fetch_required_to_hide_latency(calculate_bytes_to_fetch_required_to_hide_latency_params); @@ -9063,8 +9063,8 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out calculate_excess_vactive_bandwidth_required( display_cfg, mode_lib->ms.num_active_planes, - s->pstate_bytes_required_l, - s->pstate_bytes_required_c, + s->pstate_bytes_required_l[dml2_pstate_type_uclk], + s->pstate_bytes_required_c[dml2_pstate_type_uclk], /* outputs */ mode_lib->ms.excess_vactive_fill_bw_l, mode_lib->ms.excess_vactive_fill_bw_c); @@ -9506,8 +9506,8 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out calculate_vactive_det_fill_latency( display_cfg, mode_lib->ms.num_active_planes, - s->pstate_bytes_required_l, - s->pstate_bytes_required_c, + s->pstate_bytes_required_l[dml2_pstate_type_uclk], + s->pstate_bytes_required_c[dml2_pstate_type_uclk], mode_lib->ms.dcc_dram_bw_nom_overhead_factor_p0, mode_lib->ms.dcc_dram_bw_nom_overhead_factor_p1, mode_lib->ms.vactive_sw_bw_l, @@ -9515,7 +9515,7 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out mode_lib->ms.surface_avg_vactive_required_bw, mode_lib->ms.surface_peak_required_bw, /* outputs */ - mode_lib->ms.dram_change_vactive_det_fill_delay_us); + mode_lib->ms.pstate_vactive_det_fill_delay_us[dml2_pstate_type_uclk]); #ifdef __DML_VBA_DEBUG__ DML_LOG_VERBOSE("DML::%s: max_urgent_latency_us = %f\n", __func__, s->mSOCParameters.max_urgent_latency_us); @@ -11009,11 +11009,11 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex calculate_bytes_to_fetch_required_to_hide_latency_params->swath_width_c = mode_lib->mp.SwathWidthC; calculate_bytes_to_fetch_required_to_hide_latency_params->swath_height_l = mode_lib->mp.SwathHeightY; calculate_bytes_to_fetch_required_to_hide_latency_params->swath_height_c = mode_lib->mp.SwathHeightC; - calculate_bytes_to_fetch_required_to_hide_latency_params->latency_to_hide_us = mode_lib->soc.power_management_parameters.dram_clk_change_blackout_us; + calculate_bytes_to_fetch_required_to_hide_latency_params->latency_to_hide_us[0] = mode_lib->soc.power_management_parameters.dram_clk_change_blackout_us; /* outputs */ - calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_l = s->pstate_bytes_required_l; - calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_c = s->pstate_bytes_required_c; + calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_l = s->pstate_bytes_required_l[dml2_pstate_type_uclk]; + calculate_bytes_to_fetch_required_to_hide_latency_params->bytes_required_c = s->pstate_bytes_required_c[dml2_pstate_type_uclk]; calculate_bytes_to_fetch_required_to_hide_latency(calculate_bytes_to_fetch_required_to_hide_latency_params); @@ -11021,8 +11021,8 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex calculate_excess_vactive_bandwidth_required( display_cfg, s->num_active_planes, - s->pstate_bytes_required_l, - s->pstate_bytes_required_c, + s->pstate_bytes_required_l[dml2_pstate_type_uclk], + s->pstate_bytes_required_c[dml2_pstate_type_uclk], /* outputs */ mode_lib->mp.excess_vactive_fill_bw_l, mode_lib->mp.excess_vactive_fill_bw_c); @@ -12943,7 +12943,8 @@ void dml2_core_calcs_get_plane_support_info(const struct dml2_display_cfg *displ out->active_latency_hiding_us = (int)mode_lib->ms.VActiveLatencyHidingUs[plane_idx]; - out->dram_change_vactive_det_fill_delay_us = (unsigned int)math_ceil(mode_lib->ms.dram_change_vactive_det_fill_delay_us[plane_idx]); + out->vactive_det_fill_delay_us[dml2_pstate_type_uclk] = + (unsigned int)math_ceil(mode_lib->ms.pstate_vactive_det_fill_delay_us[plane_idx][dml2_pstate_type_uclk]); } void dml2_core_calcs_get_stream_support_info(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct core_stream_support_info *out, int plane_index) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h index 6d13d4c9b69a1..1087a8c926ff1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h @@ -593,7 +593,7 @@ struct dml2_core_internal_mode_support { double VActiveLatencyHidingMargin[DML2_MAX_PLANES]; double VActiveLatencyHidingUs[DML2_MAX_PLANES]; unsigned int MaxVStartupLines[DML2_MAX_PLANES]; - double dram_change_vactive_det_fill_delay_us[DML2_MAX_PLANES]; + double pstate_vactive_det_fill_delay_us[dml2_pstate_type_count][DML2_MAX_PLANES]; unsigned int num_mcaches_l[DML2_MAX_PLANES]; unsigned int mcache_row_bytes_l[DML2_MAX_PLANES]; @@ -623,8 +623,8 @@ struct dml2_core_internal_mode_support { unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; - unsigned int pstate_bytes_required_l[DML2_MAX_PLANES]; - unsigned int pstate_bytes_required_c[DML2_MAX_PLANES]; + unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES]; + unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES]; unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; @@ -1138,8 +1138,8 @@ struct dml2_core_calcs_mode_support_locals { unsigned int cursor_bytes[DML2_MAX_PLANES]; bool stream_visited[DML2_MAX_PLANES]; - unsigned int pstate_bytes_required_l[DML2_MAX_PLANES]; - unsigned int pstate_bytes_required_c[DML2_MAX_PLANES]; + unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES]; + unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES]; double prefetch_sw_bytes[DML2_MAX_PLANES]; double Tpre_rounded[DML2_MAX_PLANES]; @@ -1230,8 +1230,8 @@ struct dml2_core_calcs_mode_programming_locals { double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES]; - unsigned int pstate_bytes_required_l[DML2_MAX_PLANES]; - unsigned int pstate_bytes_required_c[DML2_MAX_PLANES]; + unsigned int pstate_bytes_required_l[dml2_pstate_type_count][DML2_MAX_PLANES]; + unsigned int pstate_bytes_required_c[dml2_pstate_type_count][DML2_MAX_PLANES]; double prefetch_sw_bytes[DML2_MAX_PLANES]; double Tpre_rounded[DML2_MAX_PLANES]; @@ -2253,7 +2253,7 @@ struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params unsigned int *swath_width_c; unsigned int *swath_height_l; unsigned int *swath_height_c; - double latency_to_hide_us; + double latency_to_hide_us[DML2_MAX_PLANES]; /* outputs */ unsigned int *bytes_required_l; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c index abd210401fe22..c26e100fcaf2e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c @@ -1087,7 +1087,7 @@ static bool all_timings_support_drr(const struct dml2_pmo_instance *pmo, /* check required stretch is allowed */ if (stream_descriptor->timing.drr_config.max_instant_vtotal_delta > 0 && - stream_pstate_meta->method_drr.stretched_vtotal - stream_pstate_meta->nom_vtotal > stream_descriptor->timing.drr_config.max_instant_vtotal_delta) { + stream_pstate_meta->method_drr.stretched_vtotal - stream_pstate_meta->nom_vtotal > (int)stream_descriptor->timing.drr_config.max_instant_vtotal_delta) { return false; } } @@ -1669,15 +1669,15 @@ static int get_vactive_pstate_margin(const struct display_configuation_with_meta return min_vactive_margin_us; } -static unsigned int get_vactive_det_fill_latency_delay_us(const struct display_configuation_with_meta *display_cfg, int plane_mask) +static int get_vactive_det_fill_latency_delay_us(const struct display_configuation_with_meta *display_cfg, int plane_mask) { unsigned char i; - unsigned int max_vactive_fill_us = 0; + int max_vactive_fill_us = 0; for (i = 0; i < DML2_MAX_PLANES; i++) { if (is_bit_set_in_bitfield(plane_mask, i)) { - if (display_cfg->mode_support_result.cfg_support_info.plane_support_info[i].dram_change_vactive_det_fill_delay_us > max_vactive_fill_us) - max_vactive_fill_us = display_cfg->mode_support_result.cfg_support_info.plane_support_info[i].dram_change_vactive_det_fill_delay_us; + if (display_cfg->mode_support_result.cfg_support_info.plane_support_info[i].vactive_det_fill_delay_us[dml2_pstate_type_uclk] > max_vactive_fill_us) + max_vactive_fill_us = display_cfg->mode_support_result.cfg_support_info.plane_support_info[i].vactive_det_fill_delay_us[dml2_pstate_type_uclk]; } } @@ -2095,7 +2095,7 @@ static void setup_planes_for_vactive_by_mask(struct display_configuation_with_me display_config->stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_vactive; if (!pmo->options->disable_vactive_det_fill_bw_pad) { - display_config->display_config.plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us = + display_config->display_config.plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[dml2_pstate_type_uclk] = (unsigned int)math_floor(pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_index].method_vactive.max_vactive_det_fill_delay_us); } } @@ -2116,7 +2116,7 @@ static void setup_planes_for_vactive_drr_by_mask(struct display_configuation_wit display_config->stage3.pstate_switch_modes[plane_index] = dml2_pstate_method_fw_vactive_drr; if (!pmo->options->disable_vactive_det_fill_bw_pad) { - display_config->display_config.plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us = + display_config->display_config.plane_descriptors[plane_index].overrides.max_vactive_det_fill_delay_us[dml2_pstate_type_uclk] = (unsigned int)math_floor(pmo->scratch.pmo_dcn4.stream_pstate_meta[stream_index].method_vactive.max_vactive_det_fill_delay_us); } } diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h index 9f562f0c47970..1a6c0727cd2af 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h @@ -152,7 +152,7 @@ struct core_plane_support_info { int active_latency_hiding_us; int mall_svp_size_requirement_ways; int nominal_vblank_pstate_latency_hiding_us; - unsigned int dram_change_vactive_det_fill_delay_us; + int vactive_det_fill_delay_us[dml2_pstate_type_count]; }; struct core_stream_support_info { @@ -209,6 +209,7 @@ struct dml2_core_mode_support_result { unsigned int uclk_pstate_supported; unsigned int fclk_pstate_supported; + struct dml2_core_internal_watermarks watermarks; } global; struct { @@ -257,8 +258,8 @@ struct dml2_implicit_svp_meta { struct dml2_pstate_per_method_common_meta { /* generic params */ - unsigned int allow_start_otg_vline; - unsigned int allow_end_otg_vline; + int allow_start_otg_vline; + int allow_end_otg_vline; /* scheduling params */ double allow_time_us; double disallow_time_us; @@ -268,39 +269,44 @@ struct dml2_pstate_per_method_common_meta { struct dml2_pstate_meta { bool valid; double otg_vline_time_us; - unsigned int scheduling_delay_otg_vlines; - unsigned int vertical_interrupt_ack_delay_otg_vlines; - unsigned int allow_to_target_delay_otg_vlines; - unsigned int contention_delay_otg_vlines; - unsigned int min_allow_width_otg_vlines; - unsigned int nom_vtotal; - unsigned int vblank_start; + int scheduling_delay_otg_vlines; + int vertical_interrupt_ack_delay_otg_vlines; + int allow_to_target_delay_otg_vlines; + int contention_delay_otg_vlines; + int min_allow_width_otg_vlines; + int nom_vtotal; + int vblank_start; double nom_refresh_rate_hz; double nom_frame_time_us; - unsigned int max_vtotal; + int max_vtotal; double min_refresh_rate_hz; double max_frame_time_us; - unsigned int blackout_otg_vlines; + int blackout_otg_vlines; + int max_allow_delay_otg_vlines; + double nom_vblank_time_us; struct { double max_vactive_det_fill_delay_us; - unsigned int max_vactive_det_fill_delay_otg_vlines; + double vactive_latency_hiding_us; + double reserved_vblank_required_us; + int max_vactive_det_fill_delay_otg_vlines; + int reserved_blank_required_vlines; struct dml2_pstate_per_method_common_meta common; } method_vactive; struct { struct dml2_pstate_per_method_common_meta common; } method_vblank; struct { - unsigned int programming_delay_otg_vlines; - unsigned int df_throttle_delay_otg_vlines; - unsigned int prefetch_to_mall_delay_otg_vlines; + int programming_delay_otg_vlines; + int df_throttle_delay_otg_vlines; + int prefetch_to_mall_delay_otg_vlines; unsigned long phantom_vactive; unsigned long phantom_vfp; unsigned long phantom_vtotal; struct dml2_pstate_per_method_common_meta common; } method_subvp; struct { - unsigned int programming_delay_otg_vlines; - unsigned int stretched_vtotal; + int programming_delay_otg_vlines; + int stretched_vtotal; struct dml2_pstate_per_method_common_meta common; } method_drr; }; From 607b93716b40ead0a86a0f4b701ee6f46c9b6c08 Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Tue, 30 Sep 2025 14:32:03 -0500 Subject: [PATCH 2452/2653] drm/amd/display: Add Pstate viewport reduction [Why/How] Add struct to hold calculated reduced viewport pstate recout reduction lines per plane Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h index d2584b00a19c7..452e4a2e72c01 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h @@ -676,6 +676,8 @@ struct dml2_display_cfg_programming { unsigned int PrefetchMode[DML2_MAX_PLANES]; // LEGACY_ONLY bool ROBUrgencyAvoidance; double LowestPrefetchMargin; + + unsigned int pstate_recout_reduction_lines[DML2_MAX_PLANES]; } misc; struct dml2_mode_support_info mode_support_info; From 070564f0c5f1a1dc2e89ee2e9fa112efd87aee89 Mon Sep 17 00:00:00 2001 From: Joshua Aberback Date: Thu, 23 Oct 2025 16:43:56 -0400 Subject: [PATCH 2453/2653] drm/amd/display: Persist stream refcount through restore [Why & How] Overwriting the refcount on stream restore can lead to double-free errors or memory leaks if an unbalanced number of retains and releases occurs between a backup and restore. Reviewed-by: Dillon Varone Signed-off-by: Joshua Aberback Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e168e2494d9a1..4a592998f8e6b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3390,7 +3390,11 @@ static void restore_planes_and_stream_state( for (i = 0; i < status->plane_count; i++) { dc_plane_copy_config(status->plane_states[i], &scratch->plane_states[i]); } + + // refcount is persistent + struct kref temp_refcount = stream->refcount; *stream = scratch->stream_state; + stream->refcount = temp_refcount; } /** From 2fff1307029282b8f4f8023fe93d68ea7c6084e8 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Thu, 23 Oct 2025 17:07:04 -0400 Subject: [PATCH 2454/2653] drm/amd/display: Revert DCN4 max buffered cursor size to 64 [Why & How] The buffered cursor cap is expressed assuming a square cursor, and usage of the cursor buffer is limited by the request size. For greater than 32 pixels, the request size is fixed at 256 bytes, so the maximum width must be floored to the nearest 256th byte. At 4bpp this means even with 24kB DCN4 can only hold a 64x64 cursor in the buffer as even 65 pixels would require 512 bytes per line instead of 256. Reviewed-by: Alvin Lee Signed-off-by: Dillon Varone Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index df0b664c0cd29..b276fec3e479a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -2200,7 +2200,8 @@ static bool dcn32_resource_construct( dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/ dc->caps.max_cursor_size = 64; - dc->caps.max_buffered_cursor_size = 64; // sqrt(16 * 1024 / 4) + /* floor(sqrt(buf_size_bytes / bpp ) * bpp, fixed_req_size) / bpp = max_width */ + dc->caps.max_buffered_cursor_size = 64; // floor(sqrt(16 * 1024 / 4) * 4, 256) / 4 = 64 dc->caps.min_horizontal_blanking_period = 80; dc->caps.dmdata_alloc_size = 2048; dc->caps.mall_size_per_mem_channel = 4; From f5902c9abc57921f52318b7dfc393debb875705d Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Thu, 23 Oct 2025 13:56:32 -0400 Subject: [PATCH 2455/2653] drm/amd/display: Increase IB mem size [Why & How] Increase IB mem size to match size of largest structure that will use IB transfer between driver and DMU. Reviewed-by: Oleh Kuzhylnyi Signed-off-by: Alvin Lee Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c index a657efda89ce3..a6ae1d2e9685b 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c @@ -66,7 +66,7 @@ #define DMUB_SCRATCH_MEM_SIZE (1024) /* Default indirect buffer size. */ -#define DMUB_IB_MEM_SIZE (1280) +#define DMUB_IB_MEM_SIZE (2560) /* Default LSDMA ring buffer size. */ #define DMUB_LSDMA_RB_SIZE (64 * 1024) From 19b630efd840e53fcafd21a58f0906f53183dc96 Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Wed, 22 Oct 2025 16:19:34 -0600 Subject: [PATCH 2456/2653] drm/amd/display: Fix black screen with HDMI outputs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [Why & How] This fixes the black screen issue on certain APUs with HDMI, accompanied by the following messages: amdgpu 0000:c4:00.0: amdgpu: [drm] Failed to setup vendor info frame on connector DP-1: -22 amdgpu 0000:c4:00.0: [drm] Cannot find any crtc or sizes [drm] Cannot find any crtc or sizes Fixes: 99ff9bc57b02 ("drm/amd/display: Fix DVI-D/HDMI adapters") Suggested-by: Timur Kristóf Reviewed-by: Harry Wentland Signed-off-by: Alex Hung Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/link/link_detection.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index c417780f37bca..5d287874c125d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -1257,6 +1257,7 @@ static bool detect_link_and_local_sink(struct dc_link *link, !sink->edid_caps.edid_hdmi) sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK; else if (dc_is_dvi_signal(sink->sink_signal) && + dc_is_dvi_signal(link->connector_signal) && aud_support->hdmi_audio_native && sink->edid_caps.edid_hdmi) sink->sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; From b6f0292c6690dafb694c11550147922d3539c7e2 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 24 Oct 2025 18:42:39 -0400 Subject: [PATCH 2457/2653] drm/amd/display: [FW Promotion] Release 0.1.34.0 Release hightlights DCN35/36 * Dynamically clock gate before and after prefetch Acked-by: Wayne Lin Signed-off-by: Taimur Hassan Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 439 ++++++++++++++++-- 1 file changed, 407 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index ae6e17a26bbb3..a0ffa046d8c2b 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -599,6 +599,104 @@ union replay_hw_flags { uint32_t u32All; }; +/** + * Flags that can be set by driver to change some Panel Replay behaviour. + */ +union pr_debug_flags { + struct { + /** + * 0x1 (bit 0) + * Enable visual confirm in FW. + */ + uint32_t visual_confirm : 1; + + /** + * 0x2 (bit 1) + * @skip_crc: Set if need to skip CRC. + */ + uint32_t skip_crc : 1; + + /** + * 0x4 (bit 2) + * @force_link_power_on: Force disable ALPM control + */ + uint32_t force_link_power_on : 1; + + /** + * 0x8 (bit 3) + * @force_phy_power_on: Force phy power on + */ + uint32_t force_phy_power_on : 1; + + /** + * 0x10 (bit 4) + * @skip_crtc_disabled: CRTC disable skipped + */ + uint32_t skip_crtc_disabled : 1; + + /* + * 0x20 (bit 5) + * @visual_confirm_rate_control: Enable Visual Confirm rate control detection + */ + uint32_t visual_confirm_rate_control : 1; + + uint32_t reserved : 26; + } bitfields; + + uint32_t u32All; +}; + +union pr_hw_flags { + struct { + /** + * @allow_alpm_fw_standby_mode: To indicate whether the + * ALPM FW standby mode is allowed + */ + uint32_t allow_alpm_fw_standby_mode : 1; + + /* + * @dsc_enable_status: DSC enable status in driver + */ + uint32_t dsc_enable_status : 1; + + /** + * @fec_enable_status: receive fec enable/disable status from driver + */ + uint32_t fec_enable_status : 1; + + /* + * @smu_optimizations_en: SMU power optimization. + * Only when active display is Replay capable and display enters Replay. + * Trigger interrupt to SMU to powerup/down. + */ + uint32_t smu_optimizations_en : 1; + + /** + * @phy_power_state: Indicates current phy power state + */ + uint32_t phy_power_state : 1; + + /** + * @link_power_state: Indicates current link power state + */ + uint32_t link_power_state : 1; + /** + * Use TPS3 signal when restore main link. + */ + uint32_t force_wakeup_by_tps3 : 1; + /** + * @is_alpm_initialized: Indicates whether ALPM is initialized + */ + uint32_t is_alpm_initialized : 1; + /** + * @alpm_mode: Indicates ALPM mode selected + */ + uint32_t alpm_mode : 2; + } bitfields; + + uint32_t u32All; +}; + union fw_assisted_mclk_switch_version { struct { uint8_t minor : 5; @@ -1732,9 +1830,15 @@ enum dmub_cmd_type { DMUB_CMD__CURSOR_OFFLOAD = 92, /** - * Command type used for all SMART_POWER_HDR commands. + * Command type used for all SMART_POWER_OLED commands. + */ + DMUB_CMD__SMART_POWER_OLED = 93, + + /** + * Command type use for all Panel Replay commands. */ - DMUB_CMD__SMART_POWER_HDR = 93, + DMUB_CMD__PR = 94, + /** * Command type use for VBIOS shared commands. @@ -4147,6 +4251,33 @@ enum replay_state { REPLAY_STATE_INVALID = 0xFF, }; +/** + * Definition of a panel replay state + */ +enum pr_state { + PR_STATE_0 = 0x00, // State 0 steady state + // Pending SDP and Unlock before back to State 0 + PR_STATE_0_PENDING_SDP_AND_UNLOCK = 0x01, + PR_STATE_1 = 0x10, // State 1 + PR_STATE_2 = 0x20, // State 2 steady state + // Pending frame transmission before transition to State 2 + PR_STATE_2_PENDING_FRAME_TRANSMISSION = 0x30, + // Active and Powered Up + PR_STATE_2_POWERED = 0x31, + // Active and Powered Down, but need to blank HUBP after DPG_EN latch + PR_STATE_2_PENDING_HUBP_BLANK = 0x32, + // Active and Pending Power Up + PR_STATE_2_PENDING_POWER_UP = 0x33, + // Active and Powered Up, Pending DPG latch + PR_STATE_2_PENDING_LOCK_FOR_DPG_POWER_ON = 0x34, + // Active and Powered Up, Pending SDP and Unlock + PR_STATE_2_PENDING_SDP_AND_UNLOCK = 0x35, + // Pending transmission of AS SDP for timing sync, but no rfb update + PR_STATE_2_PENDING_AS_SDP = 0x36, + // Invalid + PR_STATE_INVALID = 0xFF, +}; + /** * Replay command sub-types. */ @@ -4197,6 +4328,25 @@ enum dmub_cmd_replay_type { DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, }; +/* + * Panel Replay sub-types + */ +enum dmub_cmd_panel_replay_type { + DMUB_CMD__PR_ENABLE = 0, + DMUB_CMD__PR_COPY_SETTINGS = 1, + DMUB_CMD__PR_UPDATE_STATE = 2, + DMUB_CMD__PR_GENERAL_CMD = 3, +}; + +enum dmub_cmd_panel_replay_state_update_subtype { + PR_STATE_UPDATE_COASTING_VTOTAL = 0x1, + PR_STATE_UPDATE_SYNC_MODE = 0x2, +}; + +enum dmub_cmd_panel_replay_general_subtype { + PR_GENERAL_CMD_DEBUG_OPTION = 0x1, +}; + /** * Replay general command sub-types. */ @@ -4349,17 +4499,13 @@ struct dmub_cmd_replay_set_version_data { */ uint8_t panel_inst; /** - * PSR version that FW should implement. + * Replay version that FW should implement. */ enum replay_version version; - /** - * PSR control version. - */ - uint8_t cmd_version; /** * Explicit padding to 4 byte boundary. */ - uint8_t pad[2]; + uint8_t pad[3]; }; /** @@ -4405,11 +4551,11 @@ enum replay_enable { }; /** - * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_HDR_ENABLE command. + * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_ENABLE command. */ -struct dmub_rb_cmd_smart_power_hdr_enable_data { +struct dmub_rb_cmd_smart_power_oled_enable_data { /** - * SMART_POWER_HDR enable or disable. + * SMART_POWER_OLED enable or disable. */ uint8_t enable; /** @@ -4789,53 +4935,53 @@ union dmub_replay_cmd_set { }; /** - * SMART POWER HDR command sub-types. + * SMART POWER OLED command sub-types. */ -enum dmub_cmd_smart_power_hdr_type { +enum dmub_cmd_smart_power_oled_type { /** - * Enable/Disable SMART_POWER_HDR. + * Enable/Disable SMART_POWER_OLED. */ - DMUB_CMD__SMART_POWER_HDR_ENABLE = 1, + DMUB_CMD__SMART_POWER_OLED_ENABLE = 1, /** - * Get current MaxCLL value if SMART POWER HDR is enabled. + * Get current MaxCLL value if SMART POWER OLED is enabled. */ - DMUB_CMD__SMART_POWER_HDR_GETMAXCLL = 2, + DMUB_CMD__SMART_POWER_OLED_GETMAXCLL = 2, }; /** - * Definition of a DMUB_CMD__SMART_POWER_HDR command. + * Definition of a DMUB_CMD__SMART_POWER_OLED command. */ -struct dmub_rb_cmd_smart_power_hdr_enable { +struct dmub_rb_cmd_smart_power_oled_enable { /** * Command header. */ struct dmub_cmd_header header; - struct dmub_rb_cmd_smart_power_hdr_enable_data data; + struct dmub_rb_cmd_smart_power_oled_enable_data data; }; -struct dmub_cmd_smart_power_hdr_getmaxcll_input { +struct dmub_cmd_smart_power_oled_getmaxcll_input { uint8_t panel_inst; uint8_t pad[3]; }; -struct dmub_cmd_smart_power_hdr_getmaxcll_output { +struct dmub_cmd_smart_power_oled_getmaxcll_output { uint16_t current_max_cll; uint8_t pad[2]; }; /** - * Definition of a DMUB_CMD__SMART_POWER_HDR command. + * Definition of a DMUB_CMD__SMART_POWER_OLED command. */ -struct dmub_rb_cmd_smart_power_hdr_getmaxcll { +struct dmub_rb_cmd_smart_power_oled_getmaxcll { struct dmub_cmd_header header; /**< Command header */ /** - * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_HDR_GETMAXCLL command. + * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command. */ - union dmub_cmd_smart_power_hdr_getmaxcll_data { - struct dmub_cmd_smart_power_hdr_getmaxcll_input input; /**< Input */ - struct dmub_cmd_smart_power_hdr_getmaxcll_output output; /**< Output */ + union dmub_cmd_smart_power_oled_getmaxcll_data { + struct dmub_cmd_smart_power_oled_getmaxcll_input input; /**< Input */ + struct dmub_cmd_smart_power_oled_getmaxcll_output output; /**< Output */ uint32_t output_raw; /**< Raw data output */ } data; }; @@ -6368,6 +6514,223 @@ struct dmub_rb_cmd_cursor_offload_stream_cntl { struct dmub_cmd_cursor_offload_stream_data data; }; +/** + * Data passed from driver to FW in a DMUB_CMD__PR_ENABLE command. + */ +struct dmub_cmd_pr_enable_data { + /** + * Panel Replay enable or disable. + */ + uint8_t enable; + /** + * Panel Instance. + * Panel isntance to identify which replay_state to use + * Currently the support is only for 0 or 1 + */ + uint8_t panel_inst; + /** + * Phy state to enter. + * Values to use are defined in dmub_phy_fsm_state + */ + uint8_t phy_fsm_state; + /** + * Phy rate for DP - RBR/HBR/HBR2/HBR3. + * Set this using enum phy_link_rate. + * This does not support HDMI/DP2 for now. + */ + uint8_t phy_rate; + /** + * @hpo_stream_enc_inst: HPO stream encoder instance + */ + uint8_t hpo_stream_enc_inst; + /** + * @hpo_link_enc_inst: HPO link encoder instance + */ + uint8_t hpo_link_enc_inst; + /** + * @pad: Align structure to 4 byte boundary. + */ + uint8_t pad[2]; +}; + +/** + * Definition of a DMUB_CMD__PR_ENABLE command. + * Panel Replay enable/disable is controlled using action in data. + */ +struct dmub_rb_cmd_pr_enable { + /** + * Command header. + */ + struct dmub_cmd_header header; + + struct dmub_cmd_pr_enable_data data; +}; + +/** + * Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command. + */ +struct dmub_cmd_pr_copy_settings_data { + /** + * Flags that can be set by driver to change some replay behaviour. + */ + union pr_debug_flags debug; + + /** + * @flags: Flags used to determine feature functionality. + */ + union pr_hw_flags flags; + + /** + * DPP HW instance. + */ + uint8_t dpp_inst; + /** + * OTG HW instance. + */ + uint8_t otg_inst; + /** + * DIG FE HW instance. + */ + uint8_t digfe_inst; + /** + * DIG BE HW instance. + */ + uint8_t digbe_inst; + /** + * AUX HW instance. + */ + uint8_t aux_inst; + /** + * Panel Instance. + * Panel isntance to identify which psr_state to use + * Currently the support is only for 0 or 1 + */ + uint8_t panel_inst; + /** + * Length of each horizontal line in ns. + */ + uint32_t line_time_in_ns; + /** + * PHY instance. + */ + uint8_t dpphy_inst; + /** + * Determines if SMU optimzations are enabled/disabled. + */ + uint8_t smu_optimizations_en; + /* + * Use FSM state for Replay power up/down + */ + uint8_t use_phy_fsm; + /* + * Use FSFT afftet pixel clk + */ + uint32_t pix_clk_100hz; + /* + * Use Original pixel clock + */ + uint32_t sink_pix_clk_100hz; + /** + * Use for AUX-less ALPM LFPS wake operation + */ + struct dmub_alpm_auxless_data auxless_alpm_data; + /** + * @hpo_stream_enc_inst: HPO stream encoder instance + */ + uint8_t hpo_stream_enc_inst; + /** + * @hpo_link_enc_inst: HPO link encoder instance + */ + uint8_t hpo_link_enc_inst; + /** + * @pad: Align structure to 4 byte boundary. + */ + uint8_t pad[2]; +}; + +/** + * Definition of a DMUB_CMD__PR_COPY_SETTINGS command. + */ +struct dmub_rb_cmd_pr_copy_settings { + /** + * Command header. + */ + struct dmub_cmd_header header; + /** + * Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command. + */ + struct dmub_cmd_pr_copy_settings_data data; +}; + +struct dmub_cmd_pr_update_state_data { + /** + * Panel Instance. + * Panel isntance to identify which psr_state to use + * Currently the support is only for 0 or 1 + */ + uint8_t panel_inst; + + uint8_t pad[3]; // align to 4-byte boundary + /* + * Update flags to control the update behavior. + */ + uint32_t update_flag; + /** + * state/data to set. + */ + uint32_t coasting_vtotal; + uint32_t sync_mode; +}; + +struct dmub_cmd_pr_general_cmd_data { + /** + * Panel Instance. + * Panel isntance to identify which psr_state to use + * Currently the support is only for 0 or 1 + */ + uint8_t panel_inst; + /** + * subtype: PR general cmd sub type + */ + uint8_t subtype; + + uint8_t pad[2]; + /** + * config data by different subtypes + */ + union { + uint32_t u32All; + } data; +}; + +/** + * Definition of a DMUB_CMD__PR_UPDATE_STATE command. + */ +struct dmub_rb_cmd_pr_update_state { + /** + * Command header. + */ + struct dmub_cmd_header header; + /** + * Data passed from driver to FW in a DMUB_CMD__PR_UPDATE_STATE command. + */ + struct dmub_cmd_pr_update_state_data data; +}; + +/** + * Definition of a DMUB_CMD__PR_GENERAL_CMD command. + */ +struct dmub_rb_cmd_pr_general_cmd { + /** + * Command header. + */ + struct dmub_cmd_header header; + /** + * Data passed from driver to FW in a DMUB_CMD__PR_GENERAL_CMD command. + */ + struct dmub_cmd_pr_general_cmd_data data; +}; + /** * union dmub_rb_cmd - DMUB inbox command. */ @@ -6710,13 +7073,25 @@ union dmub_rb_cmd { */ struct dmub_rb_cmd_cursor_offload_stream_cntl cursor_offload_stream_ctnl; /** - * Definition of a DMUB_CMD__SMART_POWER_HDR_ENABLE command. + * Definition of a DMUB_CMD__SMART_POWER_OLED_ENABLE command. */ - struct dmub_rb_cmd_smart_power_hdr_enable smart_power_hdr_enable; + struct dmub_rb_cmd_smart_power_oled_enable smart_power_oled_enable; /** - * Definition of a DMUB_CMD__DMUB_CMD__SMART_POWER_HDR_GETMAXCLL command. + * Definition of a DMUB_CMD__DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command. */ - struct dmub_rb_cmd_smart_power_hdr_getmaxcll smart_power_hdr_getmaxcll; + struct dmub_rb_cmd_smart_power_oled_getmaxcll smart_power_oled_getmaxcll; + /* + * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. + */ + struct dmub_rb_cmd_pr_copy_settings pr_copy_settings; + /** + * Definition of a DMUB_CMD__REPLAY_ENABLE command. + */ + struct dmub_rb_cmd_pr_enable pr_enable; + + struct dmub_rb_cmd_pr_update_state pr_update_state; + + struct dmub_rb_cmd_pr_general_cmd pr_general_cmd; }; /** From f3f260b426bf1f74c529cdbb5f79c34d7d724068 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 24 Oct 2025 19:38:14 -0500 Subject: [PATCH 2458/2653] drm/amd/display: Promote DC to 3.2.357 This version brings along following update: - HDCP2 FW locality check refactors - Fix black screen issue with HDMI output - Increase IB mem size - Revert max buffered cursor size to 64 - Extend inbox0 lock to run Replay / PSR - Refactor VActive implementation - Add Pstate viewport reduction - Persist stream refcount through restore Acked-by: Wayne Lin Signed-off-by: Taimur Hassan Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index b59fb0795f136..9e0e97686b674 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.356" +#define DC_VER "3.2.357" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From 917db145b105b3e6a85b60e1df7cc29d6660fcf1 Mon Sep 17 00:00:00 2001 From: Xiang Liu Date: Thu, 30 Oct 2025 22:38:49 +0800 Subject: [PATCH 2459/2653] drm/amd/ras: Fix format truncation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ../ras/rascore/ras_cper.c: In function ‘cper_generate_fatal_record.isra’: ../ras/rascore/ras_cper.c:75:36: error: ‘%llX’ directive output may be truncated writing between 1 and 14 bytes into a region of size between 0 and 7 [-Werror=format-truncation=] 75 | snprintf(record_id, 9, "%d:%llX", dev_info.socket_id, | ^~~~ ../ras/rascore/ras_cper.c:75:32: note: directive argument in the range [0, 72057594037927935] 75 | snprintf(record_id, 9, "%d:%llX", dev_info.socket_id, | ^~~~~~~~~ ../ras/rascore/ras_cper.c:75:9: note: ‘snprintf’ output between 4 and 27 bytes into a destination of size 9 75 | snprintf(record_id, 9, "%d:%llX", dev_info.socket_id, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 76 | RAS_LOG_SEQNO_TO_BATCH_IDX(trace->seqno)); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../ras/rascore/ras_cper.c: In function ‘cper_generate_runtime_record.isra’: ../ras/rascore/ras_cper.c:75:36: error: ‘%llX’ directive output may be truncated writing between 1 and 14 bytes into a region of size between 0 and 7 [-Werror=format-truncation=] 75 | snprintf(record_id, 9, "%d:%llX", dev_info.socket_id, | ^~~~ ../ras/rascore/ras_cper.c:75:32: note: directive argument in the range [0, 72057594037927935] 75 | snprintf(record_id, 9, "%d:%llX", dev_info.socket_id, | ^~~~~~~~~ ../ras/rascore/ras_cper.c:75:9: note: ‘snprintf’ output between 4 and 27 bytes into a destination of size 9 75 | snprintf(record_id, 9, "%d:%llX", dev_info.socket_id, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 76 | RAS_LOG_SEQNO_TO_BATCH_IDX(trace->seqno)); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors Signed-off-by: Xiang Liu Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/ras/rascore/ras_cper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cper.c b/drivers/gpu/drm/amd/ras/rascore/ras_cper.c index 3c5bfa1c93f66..0fc7522b7ab6b 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_cper.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cper.c @@ -54,7 +54,7 @@ static void fill_section_hdr(struct ras_core_context *ras_core, enum ras_cper_severity sev, struct ras_log_info *trace) { struct device_system_info dev_info = {0}; - char record_id[16]; + char record_id[32]; hdr->signature[0] = 'C'; hdr->signature[1] = 'P'; @@ -71,7 +71,7 @@ static void fill_section_hdr(struct ras_core_context *ras_core, cper_get_timestamp(ras_core, &hdr->timestamp, trace->timestamp); - snprintf(record_id, 9, "%d:%llX", dev_info.socket_id, + snprintf(record_id, sizeof(record_id), "%d:%llX", dev_info.socket_id, RAS_LOG_SEQNO_TO_BATCH_IDX(trace->seqno)); memcpy(hdr->record_id, record_id, 8); From 4a9fcc5ba1ffad03851e69204da37b28689d4e5a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Fri, 31 Oct 2025 09:21:36 +0100 Subject: [PATCH 2460/2653] drm/amdgpu: grab a BO reference in vm_lock_done_list. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Otherwise it is possible that between dropping the status lock and locking the BO that the BO is freed up. Signed-off-by: Christian König Reviewed-by: Sunil Khatri --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index e4a085d75a3cd..f0eb2ee45dfb1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -484,15 +484,19 @@ int amdgpu_vm_lock_done_list(struct amdgpu_vm *vm, struct drm_exec *exec, spin_lock(&vm->status_lock); while (!list_is_head(prev->next, &vm->done)) { bo_va = list_entry(prev->next, typeof(*bo_va), base.vm_status); - spin_unlock(&vm->status_lock); bo = bo_va->base.bo; if (bo) { + amdgpu_bo_ref(bo); + spin_unlock(&vm->status_lock); + ret = drm_exec_prepare_obj(exec, &bo->tbo.base, 1); + amdgpu_bo_unref(&bo); if (unlikely(ret)) return ret; + + spin_lock(&vm->status_lock); } - spin_lock(&vm->status_lock); prev = prev->next; } spin_unlock(&vm->status_lock); From 2c6ed4c5003b7b0ece81edccaddd023a05dd2fc9 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Tue, 28 Oct 2025 14:09:05 +0100 Subject: [PATCH 2461/2653] drm/amdgpu: lock bo before calling amdgpu_vm_bo_update_shared MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BO's reservation object must be locked before using amdgpu_vm_bo_update_shared otherwise dma_resv_assert_held will complain in amdgpu_vm_update_shared. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 9a0bce3ba24c9..87097666beb57 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -258,6 +258,7 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, struct drm_gem_object *obj = dmabuf->priv; struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + int r; #ifdef HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER if (!amdgpu_dmabuf_is_xgmi_accessible(attach_adev, bo) && @@ -265,8 +266,14 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, attach->peer2peer = false; #endif + r = dma_resv_lock(bo->tbo.base.resv, NULL); + if (r) + return r; + amdgpu_vm_bo_update_shared(bo); + dma_resv_unlock(bo->tbo.base.resv); + return 0; } From fc23d4f74c585c7193590ecfbe337c2f57959b7d Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Fri, 31 Oct 2025 14:10:13 +0530 Subject: [PATCH 2462/2653] drm/amdgpu: validate the bo from done list for NULL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make sure the bo is valid before using it. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 45adebf1042bb..3da606b9b9eb5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -1078,6 +1078,8 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) /* Validate User Ptr BOs */ list_for_each_entry(bo_va, &vm->done, base.vm_status) { bo = bo_va->base.bo; + if (!bo) + continue; if (!amdgpu_ttm_tt_is_userptr(bo->tbo.ttm)) continue; From 74b6fdefb41c6e972f0fe223504802b1b347d9ec Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 14 Aug 2025 16:35:39 +0530 Subject: [PATCH 2463/2653] drm/amd/pm: Use gpu metrics 1.9 for SMUv13.0.12 Fill and publish GPU metrics in v1.9 format for SMUv13.0.12 SOCs Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 89 ++++++++----------- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 25 +++--- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 4 +- 3 files changed, 51 insertions(+), 67 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index a0c844bf852cc..f4bf0b558d868 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -58,7 +58,7 @@ #define NUM_JPEG_RINGS_FW 10 #define NUM_JPEG_RINGS_GPU_METRICS(gpu_metrics) \ - (ARRAY_SIZE(gpu_metrics->xcp_stats[0].jpeg_busy) / 4) + (ARRAY_SIZE(gpu_metrics->jpeg_busy) / 4) const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[SMU_FEATURE_COUNT] = { SMU_13_0_12_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATION), @@ -772,22 +772,17 @@ ssize_t smu_v13_0_12_get_xcp_metrics(struct smu_context *smu, struct amdgpu_xcp return sizeof(*xcp_metrics); } -ssize_t smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, void *smu_metrics) +void smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, + void *smu_metrics, + struct smu_v13_0_6_gpu_metrics *gpu_metrics) { - struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v1_8 *gpu_metrics = - (struct gpu_metrics_v1_8 *)smu_table->gpu_metrics_table; - int ret = 0, xcc_id, inst, i, j, k, idx; struct amdgpu_device *adev = smu->adev; + int ret = 0, xcc_id, inst, i, j; u8 num_jpeg_rings_gpu_metrics; MetricsTable_t *metrics; - struct amdgpu_xcp *xcp; - u32 inst_mask; metrics = (MetricsTable_t *)smu_metrics; - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 8); - gpu_metrics->temperature_hotspot = SMUQ10_ROUND(metrics->MaxSocketTemperature); /* Individual HBM stack temperature is not reported */ @@ -877,57 +872,47 @@ ssize_t smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, void gpu_metrics->xgmi_link_status[j] = ret; } - gpu_metrics->num_partition = adev->xcp_mgr->num_xcps; - num_jpeg_rings_gpu_metrics = NUM_JPEG_RINGS_GPU_METRICS(gpu_metrics); - for_each_xcp(adev->xcp_mgr, xcp, i) { - amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); - idx = 0; - for_each_inst(k, inst_mask) { - /* Both JPEG and VCN has same instances */ - inst = GET_INST(VCN, k); - - for (j = 0; j < num_jpeg_rings_gpu_metrics; ++j) { - gpu_metrics->xcp_stats[i].jpeg_busy - [(idx * num_jpeg_rings_gpu_metrics) + j] = - SMUQ10_ROUND(metrics->JpegBusy - [(inst * NUM_JPEG_RINGS_FW) + j]); - } - gpu_metrics->xcp_stats[i].vcn_busy[idx] = - SMUQ10_ROUND(metrics->VcnBusy[inst]); - idx++; + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + inst = GET_INST(VCN, i); + + for (j = 0; j < num_jpeg_rings_gpu_metrics; ++j) { + gpu_metrics->jpeg_busy[(i * num_jpeg_rings_gpu_metrics) + + j] = + SMUQ10_ROUND( + metrics->JpegBusy[(inst * + NUM_JPEG_RINGS_FW) + + j]); } + gpu_metrics->vcn_busy[i] = SMUQ10_ROUND(metrics->VcnBusy[inst]); + } - amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); - idx = 0; - for_each_inst(k, inst_mask) { - inst = GET_INST(GC, k); - gpu_metrics->xcp_stats[i].gfx_busy_inst[idx] = - SMUQ10_ROUND(metrics->GfxBusy[inst]); - gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] = - SMUQ10_ROUND(metrics->GfxBusyAcc[inst]); - if (smu_v13_0_6_cap_supported(smu, SMU_CAP(HST_LIMIT_METRICS))) { - gpu_metrics->xcp_stats[i].gfx_below_host_limit_ppt_acc[idx] = - SMUQ10_ROUND(metrics->GfxclkBelowHostLimitPptAcc[inst]); - gpu_metrics->xcp_stats[i].gfx_below_host_limit_thm_acc[idx] = - SMUQ10_ROUND(metrics->GfxclkBelowHostLimitThmAcc[inst]); - gpu_metrics->xcp_stats[i].gfx_low_utilization_acc[idx] = - SMUQ10_ROUND(metrics->GfxclkLowUtilizationAcc[inst]); - gpu_metrics->xcp_stats[i].gfx_below_host_limit_total_acc[idx] = - SMUQ10_ROUND(metrics->GfxclkBelowHostLimitTotalAcc[inst]); - } - idx++; - } + for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) { + inst = GET_INST(GC, i); + gpu_metrics->gfx_busy_inst[i] = + SMUQ10_ROUND(metrics->GfxBusy[inst]); + gpu_metrics->gfx_busy_acc[i] = + SMUQ10_ROUND(metrics->GfxBusyAcc[inst]); + if (smu_v13_0_6_cap_supported(smu, + SMU_CAP(HST_LIMIT_METRICS))) { + gpu_metrics + ->gfx_below_host_limit_ppt_acc[i] = SMUQ10_ROUND( + metrics->GfxclkBelowHostLimitPptAcc[inst]); + gpu_metrics + ->gfx_below_host_limit_thm_acc[i] = SMUQ10_ROUND( + metrics->GfxclkBelowHostLimitThmAcc[inst]); + gpu_metrics->gfx_low_utilization_acc[i] = SMUQ10_ROUND( + metrics->GfxclkLowUtilizationAcc[inst]); + gpu_metrics->gfx_below_host_limit_total_acc + [i] = SMUQ10_ROUND( + metrics->GfxclkBelowHostLimitTotalAcc[inst]); + }; } gpu_metrics->xgmi_link_width = metrics->XgmiWidth; gpu_metrics->xgmi_link_speed = metrics->XgmiBitrate; gpu_metrics->firmware_timestamp = metrics->Timestamp; - - *table = (void *)gpu_metrics; - - return sizeof(*gpu_metrics); } const struct smu_temp_funcs smu_v13_0_12_temp_funcs = { diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index abb373bdaaabf..ca8a177841804 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -557,7 +557,6 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; - void *gpu_metrics_table __free(kfree) = NULL; struct smu_v13_0_6_gpu_metrics *gpu_metrics; void *driver_pptable __free(kfree) = NULL; void *metrics_table __free(kfree) = NULL; @@ -588,12 +587,6 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu) return -ENOMEM; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_8); - gpu_metrics_table = - kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); - if (!gpu_metrics_table) - return -ENOMEM; - driver_pptable = kzalloc(sizeof(struct PPTable_t), GFP_KERNEL); if (!driver_pptable) return -ENOMEM; @@ -616,7 +609,6 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu) } } - smu_table->gpu_metrics_table = no_free_ptr(gpu_metrics_table); smu_table->metrics_table = no_free_ptr(metrics_table); smu_table->driver_pptable = no_free_ptr(driver_pptable); @@ -2951,16 +2943,20 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table if (ret) return ret; - if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == - IP_VERSION(13, 0, 12) && - smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) - return smu_v13_0_12_get_gpu_metrics(smu, table, metrics_v0); - - metrics_v1 = (MetricsTableV1_t *)metrics_v0; metrics_v2 = (MetricsTableV2_t *)metrics_v0; gpu_metrics = (struct smu_v13_0_6_gpu_metrics *)(tables[SMU_TABLE_SMU_METRICS].cache.buffer); + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) && + smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) { + smu_v13_0_12_get_gpu_metrics(smu, table, metrics_v0, + gpu_metrics); + goto fill; + } + + metrics_v1 = (MetricsTableV1_t *)metrics_v0; + metrics_v2 = (MetricsTableV2_t *)metrics_v0; + gpu_metrics->temperature_hotspot = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version)); /* Individual HBM stack temperature is not reported */ @@ -3133,6 +3129,7 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, version); +fill: *table = tables[SMU_TABLE_SMU_METRICS].cache.buffer; return sizeof(*gpu_metrics); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h index 3f57e2a33fb4a..86d82044a255d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h @@ -94,7 +94,6 @@ size_t smu_v13_0_12_get_system_metrics_size(void); int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu); int smu_v13_0_12_get_smu_metrics_data(struct smu_context *smu, MetricsMember_t member, uint32_t *value); -ssize_t smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, void *smu_metrics); ssize_t smu_v13_0_12_get_xcp_metrics(struct smu_context *smu, struct amdgpu_xcp *xcp, void *table, void *smu_metrics); @@ -216,6 +215,9 @@ extern const struct smu_temp_funcs smu_v13_0_12_temp_funcs; SMU_13_0_6_MAX_XCC); DECLARE_SMU_METRICS_CLASS(smu_v13_0_6_gpu_metrics, SMU_13_0_6_METRICS_FIELDS); +void smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, + void *smu_metrics, + struct smu_v13_0_6_gpu_metrics *gpu_metrics); #endif /* SWSMU_CODE_LAYER_L2 */ From b2a30fd7df1fb945f2ba7b6167bf06cdd7de1c0d Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 18 Aug 2025 12:03:41 +0530 Subject: [PATCH 2464/2653] drm/amd/pm: Add schema v1.1 for parition metrics Use a schema similar to gpu metrics v1.9 for partition metrics also. It will have field type encoded followed by the field value(s). The attribute ids used will be shared with gpu metrics. The structure definition is only to distinguish between gpu metrics and partition metrics though both gpu metrics v1.9 and partition metrics v1.1 follow the same definition. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/include/kgd_pp_interface.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index 94375cf9ba616..514bd5168832a 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -1829,4 +1829,10 @@ struct amdgpu_partition_metrics_v1_0 { uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; }; +struct amdgpu_partition_metrics_v1_1 { + struct metrics_table_header common_header; + int attr_count; + struct gpu_metrics_attr metrics_attrs[]; +}; + #endif From 0d6ee7aedef70378f69a053aa1129dc6daeba141 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 18 Aug 2025 12:21:23 +0530 Subject: [PATCH 2465/2653] drm/amd/pm: Update SMUv13.0.6 partition metrics For SMU v13.0.6 SOCs, move to partition metrics v1.1 schema Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 6 ++-- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 35 +++++++++++++++++++ 2 files changed, 38 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index ca8a177841804..9e6a672cd9b13 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -2813,7 +2813,7 @@ static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id, { const u8 num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3; int version = smu_v13_0_6_get_metrics_version(smu); - struct amdgpu_partition_metrics_v1_0 *xcp_metrics; + struct smu_v13_0_6_partition_metrics *xcp_metrics; MetricsTableV0_t *metrics_v0 __free(kfree) = NULL; struct amdgpu_device *adev = smu->adev; int ret, inst, i, j, k, idx; @@ -2833,8 +2833,8 @@ static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id, if (i == adev->xcp_mgr->num_xcps) return -EINVAL; - xcp_metrics = (struct amdgpu_partition_metrics_v1_0 *)table; - smu_cmn_init_partition_metrics(xcp_metrics, 1, 0); + xcp_metrics = (struct smu_v13_0_6_partition_metrics *)table; + smu_v13_0_6_partition_metrics_init(xcp_metrics, 1, 1); metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL); if (!metrics_v0) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h index 86d82044a255d..ba865ae7eca2a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h @@ -219,6 +219,41 @@ void smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, void *smu_metrics, struct smu_v13_0_6_gpu_metrics *gpu_metrics); +#define SMU_13_0_6_PARTITION_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY) \ + SMU_ARRAY(SMU_MATTR(CURRENT_GFXCLK), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_gfxclk, SMU_13_0_6_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(CURRENT_SOCCLK), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_socclk, SMU_13_0_6_MAX_CLKS); \ + SMU_ARRAY(SMU_MATTR(CURRENT_VCLK0), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_vclk0, SMU_13_0_6_MAX_CLKS); \ + SMU_ARRAY(SMU_MATTR(CURRENT_DCLK0), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_dclk0, SMU_13_0_6_MAX_CLKS); \ + SMU_SCALAR(SMU_MATTR(CURRENT_UCLK), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_uclk); \ + SMU_ARRAY(SMU_MATTR(GFX_BUSY_INST), SMU_MUNIT(PERCENT), \ + SMU_MTYPE(U32), gfx_busy_inst, SMU_13_0_6_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(JPEG_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U16), \ + jpeg_busy, SMU_13_0_6_MAX_JPEG); \ + SMU_ARRAY(SMU_MATTR(VCN_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U16), \ + vcn_busy, SMU_13_0_6_MAX_VCN); \ + SMU_ARRAY(SMU_MATTR(GFX_BUSY_ACC), SMU_MUNIT(PERCENT), SMU_MTYPE(U64), \ + gfx_busy_acc, SMU_13_0_6_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_PPT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_below_host_limit_ppt_acc, \ + SMU_13_0_6_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_THM_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_below_host_limit_thm_acc, \ + SMU_13_0_6_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_LOW_UTILIZATION_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_low_utilization_acc, \ + SMU_13_0_6_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_TOTAL_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_below_host_limit_total_acc, \ + SMU_13_0_6_MAX_XCC); + +DECLARE_SMU_METRICS_CLASS(smu_v13_0_6_partition_metrics, + SMU_13_0_6_PARTITION_METRICS_FIELDS); + #endif /* SWSMU_CODE_LAYER_L2 */ #endif From 92f15ae016ac3f7e69bafa603df5d81f7f451797 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 18 Aug 2025 12:25:50 +0530 Subject: [PATCH 2466/2653] drm/amd/pm: Update SMUv13.0.12 partition metrics Update SMUv13.0.12 partition metrics to partition metrics v1.1 schema. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index f4bf0b558d868..c6cf0d0c4b825 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -719,15 +719,14 @@ static ssize_t smu_v13_0_12_get_temp_metrics(struct smu_context *smu, ssize_t smu_v13_0_12_get_xcp_metrics(struct smu_context *smu, struct amdgpu_xcp *xcp, void *table, void *smu_metrics) { const u8 num_jpeg_rings = NUM_JPEG_RINGS_FW; - struct amdgpu_partition_metrics_v1_0 *xcp_metrics; + struct smu_v13_0_6_partition_metrics *xcp_metrics; struct amdgpu_device *adev = smu->adev; MetricsTable_t *metrics; int inst, j, k, idx; u32 inst_mask; metrics = (MetricsTable_t *)smu_metrics; - xcp_metrics = (struct amdgpu_partition_metrics_v1_0 *) table; - smu_cmn_init_partition_metrics(xcp_metrics, 1, 0); + xcp_metrics = (struct smu_v13_0_6_partition_metrics *)table; amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); idx = 0; for_each_inst(k, inst_mask) { From f89e5a3ba2b8dc9e2fb9a493ac1757c6aafc9c9a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 24 Oct 2025 13:08:11 -0400 Subject: [PATCH 2467/2653] drm/amdgpu/smu: Handle S0ix for vangogh Fix the flows for S0ix. There is no need to stop rlc or reintialize PMFW in S0ix. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659 Signed-off-by: Alex Deucher Reviewed-by: Mario Limonciello Reported-by: Antheas Kapenekakis Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659 Tested-by: Antheas Kapenekakis --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 6 ++++++ drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 3 +++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 9af0d8e1f79ed..ef51964dfc902 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2054,6 +2054,12 @@ static int smu_disable_dpms(struct smu_context *smu) smu->is_apu && (amdgpu_in_reset(adev) || adev->in_s0ix)) return 0; + /* vangogh s0ix */ + if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) || + amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2)) && + adev->in_s0ix) + return 0; + /* * For gpu reset, runpm and hibernation through BACO, * BACO feature has to be kept enabled. diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index 09b68c1fa1998..5ac1ca5a6bcdf 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -2223,6 +2223,9 @@ static int vangogh_post_smu_init(struct smu_context *smu) uint32_t total_cu = adev->gfx.config.max_cu_per_sh * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; + if (adev->in_s0ix) + return 0; + /* allow message will be sent after enable message on Vangogh*/ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { From b9c8ae1240e537c417863e32108537ece2103812 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Tue, 15 Jul 2025 10:26:22 +0200 Subject: [PATCH 2468/2653] Revert "drm/amdgpu: Use dma_buf from GEM object instance" This reverts commit 515986100d176663d0a03219a3056e4252f729e6. The dma_buf field in struct drm_gem_object is not stable over the object instance's lifetime. The field becomes NULL when user space releases the final GEM handle on the buffer object. This resulted in a NULL-pointer deref. Workarounds in commit 5307dce878d4 ("drm/gem: Acquire references on GEM handles for framebuffers") and commit f6bfc9afc751 ("drm/framebuffer: Acquire internal references on GEM handles") only solved the problem partially. They especially don't work for buffer objects without a DRM framebuffer associated. Hence, this revert to going back to using .import_attach->dmabuf. Signed-off-by: Thomas Zimmermann Reviewed-by: Simona Vetter Acked-by: Alex Deucher Link: https://lore.kernel.org/r/20250715082635.34974-1-tzimmermann@suse.de --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 87097666beb57..b8008bec65896 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -864,7 +864,7 @@ bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev, return false; if (drm_gem_is_imported(obj)) { - struct dma_buf *dma_buf = obj->dma_buf; + struct dma_buf *dma_buf = obj->import_attach->dmabuf; if (dma_buf->ops != &amdgpu_dmabuf_ops) /* No XGMI with non AMD GPUs */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index bbe0ee582a618..2fbf8d58b718b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -372,7 +372,8 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj, */ if (!vm->is_compute_context || !vm->process_info) return 0; - if (!drm_gem_is_imported(obj) || !dma_buf_is_dynamic(obj->dma_buf)) + if (!drm_gem_is_imported(obj) || + !dma_buf_is_dynamic(obj->import_attach->dmabuf)) return 0; mutex_lock_nested(&vm->process_info->lock, 1); if (!WARN_ON(!vm->process_info->eviction_fence)) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index f0eb2ee45dfb1..e2906f55bac51 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1308,7 +1308,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, struct drm_gem_object *obj = &bo->tbo.base; if (drm_gem_is_imported(obj) && bo_va->is_xgmi) { - struct dma_buf *dma_buf = obj->dma_buf; + struct dma_buf *dma_buf = obj->import_attach->dmabuf; struct drm_gem_object *gobj = dma_buf->priv; struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); From 3f583514221dce28343084d405188d751fc8a6ef Mon Sep 17 00:00:00 2001 From: Yang Su Date: Mon, 3 Nov 2025 11:34:09 +0800 Subject: [PATCH 2469/2653] drm/amdkcl: modify the return of drm_gem_is_imported() in KCL The dma_buf retrieval method was changed by Revert "drm/amdgpu: Use dma_buf from GEM object instance". The KCL must be updated accordingly to stay in sync with driver&kernel. Signed-off-by: Yang Su Reviewed-by: Bob Zhou --- include/kcl/kcl_drm_gem.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/kcl/kcl_drm_gem.h b/include/kcl/kcl_drm_gem.h index 82485f6798b69..af931dc7d12ce 100644 --- a/include/kcl/kcl_drm_gem.h +++ b/include/kcl/kcl_drm_gem.h @@ -92,8 +92,7 @@ static inline bool drm_gem_object_is_shared_for_memory_stats(struct drm_gem_obje */ static inline bool drm_gem_is_imported(const struct drm_gem_object *obj) { - /* The dma-buf's priv field points to the original GEM object. */ - return obj->dma_buf && (obj->dma_buf->priv != obj); + return !!obj->import_attach; } #endif #endif From 755290eb22e8a30b7a683e524b01623b280af4ba Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Fri, 31 Oct 2025 13:37:30 +0800 Subject: [PATCH 2470/2653] drm/amd/ras: Increase ras switch control range Increase ras switch control range. Signed-off-by: YiPeng Chai Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 3 +++ .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 25 ++++++++++++++----- 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index 556cf4d7b5ef8..40c0bf85f1d34 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -591,6 +591,9 @@ struct amdgpu_ras { /* Protect poison injection */ struct mutex poison_lock; + + /* Disable/Enable uniras switch */ + bool uniras_enabled; }; struct ras_fs_data { diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c index dc2a4c6c19074..f8ec0f26a9e79 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -283,6 +283,18 @@ static int amdgpu_ras_mgr_sw_init(struct amdgpu_ip_block *ip_block) struct amdgpu_ras_mgr *ras_mgr; int ret = 0; + /* Disabled by default */ + con->uniras_enabled = false; + + /* Enabled only in debug mode */ + if (adev->debug_enable_ras_aca) { + con->uniras_enabled = true; + RAS_DEV_INFO(adev, "Debug amdgpu uniras!"); + } + + if (!con->uniras_enabled) + return 0; + ras_mgr = kzalloc(sizeof(*ras_mgr), GFP_KERNEL); if (!ras_mgr) return -EINVAL; @@ -315,6 +327,9 @@ static int amdgpu_ras_mgr_sw_fini(struct amdgpu_ip_block *ip_block) struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct amdgpu_ras_mgr *ras_mgr = (struct amdgpu_ras_mgr *)con->ras_mgr; + if (!con->uniras_enabled) + return 0; + if (!ras_mgr) return 0; @@ -332,12 +347,11 @@ static int amdgpu_ras_mgr_sw_fini(struct amdgpu_ip_block *ip_block) static int amdgpu_ras_mgr_hw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); int ret; - /* Currently only debug mode can enable the ras module - */ - if (!adev->debug_enable_ras_aca) + if (!con->uniras_enabled) return 0; if (!ras_mgr || !ras_mgr->ras_core) @@ -360,11 +374,10 @@ static int amdgpu_ras_mgr_hw_init(struct amdgpu_ip_block *ip_block) static int amdgpu_ras_mgr_hw_fini(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); - /* Currently only debug mode can enable the ras module - */ - if (!adev->debug_enable_ras_aca) + if (!con->uniras_enabled) return 0; if (!ras_mgr || !ras_mgr->ras_core) From c1517970fbb86b872577c5d8fad1efdeac1ccb7a Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Fri, 31 Oct 2025 14:33:18 +0800 Subject: [PATCH 2471/2653] drm/amdgpu: Add ras ip block name Add ras ip block name. Signed-off-by: YiPeng Chai Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 194df738635cb..5f1bda51df034 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2523,6 +2523,7 @@ static const char *ip_block_names[] = { [AMD_IP_BLOCK_TYPE_VPE] = "vpe", [AMD_IP_BLOCK_TYPE_UMSCH_MM] = "umsch_mm", [AMD_IP_BLOCK_TYPE_ISP] = "isp", + [AMD_IP_BLOCK_TYPE_RAS] = "ras", }; static const char *ip_block_name(struct amdgpu_device *adev, enum amd_ip_block_type type) From 3c22f93caab8704de181f2b037feedd86db917be Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Fri, 31 Oct 2025 15:41:26 +0800 Subject: [PATCH 2472/2653] drm/amd/ras: Add ras support for nbio v7_9_1 Add ras support for nbio v7_9_1. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 3 ++- drivers/gpu/drm/amd/ras/rascore/ras_nbio.c | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c index f8ec0f26a9e79..e31ffebd32d91 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -172,12 +172,13 @@ static int amdgpu_ras_mgr_init_nbio_config(struct amdgpu_device *adev, switch (config->nbio_ip_version) { case IP_VERSION(7, 9, 0): + case IP_VERSION(7, 9, 1): nbio_cfg->nbio_sys_fn = &amdgpu_ras_nbio_sys_func_v7_9; break; default: RAS_DEV_ERR(adev, "The nbio(0x%x) ras config is not right!\n", - config->mp1_ip_version); + config->nbio_ip_version); ret = -EINVAL; break; } diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_nbio.c b/drivers/gpu/drm/amd/ras/rascore/ras_nbio.c index 8bf1f35d595e6..bfddd104d5486 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_nbio.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_nbio.c @@ -31,6 +31,7 @@ static const struct ras_nbio_ip_func *ras_nbio_get_ip_funcs( { switch (ip_version) { case IP_VERSION(7, 9, 0): + case IP_VERSION(7, 9, 1): return &ras_nbio_v7_9; default: RAS_DEV_ERR(ras_core->dev, From c55452d49150fa4dae481e625a8329c2c18309c0 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Fri, 31 Oct 2025 15:39:20 +0800 Subject: [PATCH 2473/2653] drm/amd/ras: Add ras support for umc v12_5_0 Add ras support for umc v12_5_0. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 3 ++- drivers/gpu/drm/amd/ras/rascore/ras_umc.c | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c index e31ffebd32d91..adb01bdee0037 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -259,7 +259,8 @@ static struct ras_core_context *amdgpu_ras_mgr_create_ras_core(struct amdgpu_dev init_config.nbio_ip_version = amdgpu_ip_version(adev, NBIO_HWIP, 0); init_config.psp_ip_version = amdgpu_ip_version(adev, MP1_HWIP, 0); - if (init_config.umc_ip_version == IP_VERSION(12, 0, 0)) + if (init_config.umc_ip_version == IP_VERSION(12, 0, 0) || + init_config.umc_ip_version == IP_VERSION(12, 5, 0)) init_config.aca_ip_version = IP_VERSION(1, 0, 0); init_config.sys_fn = &amdgpu_ras_sys_fn; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c index 4067359bb2993..4dae64c424a24 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c @@ -71,6 +71,7 @@ static const struct ras_umc_ip_func *ras_umc_get_ip_func( { switch (ip_version) { case IP_VERSION(12, 0, 0): + case IP_VERSION(12, 5, 0): return &ras_umc_func_v12_0; default: RAS_DEV_ERR(ras_core->dev, From 3952cb6998a357a83bfcd688b20e3bc739a0ad15 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Fri, 31 Oct 2025 10:50:02 -0400 Subject: [PATCH 2474/2653] drm/amdkfd: Don't clear PT after process killed MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If process is killed. the vm entity is stopped, submit pt update job will trigger the error message "*ERROR* Trying to push to a killed entity", job will not execute. Suggested-by: Christian König Signed-off-by: Philip Yang Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 34940ba10e2aa..d53080493e6ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1371,6 +1371,10 @@ static int unmap_bo_from_gpuvm(struct kgd_mem *mem, (void)amdgpu_vm_bo_unmap(adev, bo_va, entry->va); + /* VM entity stopped if process killed, don't clear freed pt bo */ + if (!amdgpu_vm_ready(vm)) + return 0; + (void)amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update); (void)amdgpu_sync_fence(sync, bo_va->last_pt_update, GFP_KERNEL); From c30b17e9c657581eff794cc676432700846ef658 Mon Sep 17 00:00:00 2001 From: Rong Zhang Date: Tue, 14 Oct 2025 00:47:35 +0800 Subject: [PATCH 2475/2653] drm/amd/display: Fix NULL deref in debugfs odm_combine_segments When a connector is connected but inactive (e.g., disabled by desktop environments), pipe_ctx->stream_res.tg will be destroyed. Then, reading odm_combine_segments causes kernel NULL pointer dereference. BUG: kernel NULL pointer dereference, address: 0000000000000000 #PF: supervisor read access in kernel mode #PF: error_code(0x0000) - not-present page PGD 0 P4D 0 Oops: Oops: 0000 [#1] SMP NOPTI CPU: 16 UID: 0 PID: 26474 Comm: cat Not tainted 6.17.0+ #2 PREEMPT(lazy) e6a17af9ee6db7c63e9d90dbe5b28ccab67520c6 Hardware name: LENOVO 21Q4/LNVNB161216, BIOS PXCN25WW 03/27/2025 RIP: 0010:odm_combine_segments_show+0x93/0xf0 [amdgpu] Code: 41 83 b8 b0 00 00 00 01 75 6e 48 98 ba a1 ff ff ff 48 c1 e0 0c 48 8d 8c 07 d8 02 00 00 48 85 c9 74 2d 48 8b bc 07 f0 08 00 00 <48> 8b 07 48 8b 80 08 02 00> RSP: 0018:ffffd1bf4b953c58 EFLAGS: 00010286 RAX: 0000000000005000 RBX: ffff8e35976b02d0 RCX: ffff8e3aeed052d8 RDX: 00000000ffffffa1 RSI: ffff8e35a3120800 RDI: 0000000000000000 RBP: 0000000000000000 R08: ffff8e3580eb0000 R09: ffff8e35976b02d0 R10: ffffd1bf4b953c78 R11: 0000000000000000 R12: ffffd1bf4b953d08 R13: 0000000000040000 R14: 0000000000000001 R15: 0000000000000001 FS: 00007f44d3f9f740(0000) GS:ffff8e3caa47f000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000000 CR3: 00000006485c2000 CR4: 0000000000f50ef0 PKRU: 55555554 Call Trace: seq_read_iter+0x125/0x490 ? __alloc_frozen_pages_noprof+0x18f/0x350 seq_read+0x12c/0x170 full_proxy_read+0x51/0x80 vfs_read+0xbc/0x390 ? __handle_mm_fault+0xa46/0xef0 ? do_syscall_64+0x71/0x900 ksys_read+0x73/0xf0 do_syscall_64+0x71/0x900 ? count_memcg_events+0xc2/0x190 ? handle_mm_fault+0x1d7/0x2d0 ? do_user_addr_fault+0x21a/0x690 ? exc_page_fault+0x7e/0x1a0 entry_SYSCALL_64_after_hwframe+0x6c/0x74 RIP: 0033:0x7f44d4031687 Code: 48 89 fa 4c 89 df e8 58 b3 00 00 8b 93 08 03 00 00 59 5e 48 83 f8 fc 74 1a 5b c3 0f 1f 84 00 00 00 00 00 48 8b 44 24 10 0f 05 <5b> c3 0f 1f 80 00 00 00 00> RSP: 002b:00007ffdb4b5f0b0 EFLAGS: 00000202 ORIG_RAX: 0000000000000000 RAX: ffffffffffffffda RBX: 00007f44d3f9f740 RCX: 00007f44d4031687 RDX: 0000000000040000 RSI: 00007f44d3f5e000 RDI: 0000000000000003 RBP: 0000000000040000 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000202 R12: 00007f44d3f5e000 R13: 0000000000000003 R14: 0000000000000000 R15: 0000000000040000 Modules linked in: tls tcp_diag inet_diag xt_mark ccm snd_hrtimer snd_seq_dummy snd_seq_midi snd_seq_oss snd_seq_midi_event snd_rawmidi snd_seq snd_seq_device x> snd_hda_codec_atihdmi snd_hda_codec_realtek_lib lenovo_wmi_helpers think_lmi snd_hda_codec_generic snd_hda_codec_hdmi snd_soc_core kvm snd_compress uvcvideo sn> platform_profile joydev amd_pmc mousedev mac_hid sch_fq_codel uinput i2c_dev parport_pc ppdev lp parport nvme_fabrics loop nfnetlink ip_tables x_tables dm_cryp> CR2: 0000000000000000 ---[ end trace 0000000000000000 ]--- RIP: 0010:odm_combine_segments_show+0x93/0xf0 [amdgpu] Code: 41 83 b8 b0 00 00 00 01 75 6e 48 98 ba a1 ff ff ff 48 c1 e0 0c 48 8d 8c 07 d8 02 00 00 48 85 c9 74 2d 48 8b bc 07 f0 08 00 00 <48> 8b 07 48 8b 80 08 02 00> RSP: 0018:ffffd1bf4b953c58 EFLAGS: 00010286 RAX: 0000000000005000 RBX: ffff8e35976b02d0 RCX: ffff8e3aeed052d8 RDX: 00000000ffffffa1 RSI: ffff8e35a3120800 RDI: 0000000000000000 RBP: 0000000000000000 R08: ffff8e3580eb0000 R09: ffff8e35976b02d0 R10: ffffd1bf4b953c78 R11: 0000000000000000 R12: ffffd1bf4b953d08 R13: 0000000000040000 R14: 0000000000000001 R15: 0000000000000001 FS: 00007f44d3f9f740(0000) GS:ffff8e3caa47f000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000000 CR3: 00000006485c2000 CR4: 0000000000f50ef0 PKRU: 55555554 Fix this by checking pipe_ctx->stream_res.tg before dereferencing. Fixes: 07926ba8a44f ("drm/amd/display: Add debugfs interface for ODM combine info") Cc: stable@vger.kernel.org Signed-off-by: Rong Zhang Reviewed-by: Mario Limoncello Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index a011fc5bfa8f3..1f579e6c83289 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -1312,7 +1312,8 @@ static int odm_combine_segments_show(struct seq_file *m, void *unused) if (connector->status != connector_status_connected) return -ENODEV; - if (pipe_ctx != NULL && pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments) + if (pipe_ctx && pipe_ctx->stream_res.tg && + pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments) pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments); seq_printf(m, "%d\n", segments); From 867b1631e04bfbc7f813c62bd37b2315f5681a75 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Wed, 29 Oct 2025 09:41:04 -0400 Subject: [PATCH 2476/2653] Revert "drm/amdkfd: Improve signal event slow path" To fix regression report on gfx8, which requires the exhaustive search path for signaled event. The high CPU usage of KFD interrupt wq issus is gone after HIP/ROCr add option to reduce HW event interrupts, safe to revert this optimization patch now. This reverts commit de844846f72b152119faaef1b363448dc8ea368f. Signed-off-by: Philip Yang Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_events.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index 766b061d9fd98..4be85487983a1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -760,16 +760,6 @@ void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, uint64_t *slots = page_slots(p->signal_page); uint32_t id; - /* - * If id is valid but slot is not signaled, GPU may signal the same event twice - * before driver have chance to process the first interrupt, then signal slot is - * auto-reset after set_event wakeup the user space, just drop the second event as - * the application only need wakeup once. - */ - if ((valid_id_bits > 31 || (1U << valid_id_bits) >= KFD_SIGNAL_EVENT_LIMIT) && - partial_id < KFD_SIGNAL_EVENT_LIMIT && slots[partial_id] == UNSIGNALED_EVENT_SLOT) - goto out_unlock; - if (valid_id_bits) pr_debug_ratelimited("Partial ID invalid: %u (%u valid bits)\n", partial_id, valid_id_bits); @@ -798,7 +788,6 @@ void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, } } -out_unlock: rcu_read_unlock(); kfd_unref_process(p); } From f263887a4d52748e95456387b186b2342cc59bb1 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Mon, 8 Sep 2025 17:08:29 +0800 Subject: [PATCH 2477/2653] drm/amd/pm: add new message definitions for pmfw eeprom interface Add new message definitions for pmfw eeprom interface Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- .../pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h | 16 ++++++---------- drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 9 ++++++++- .../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 7 +++++++ 3 files changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h index 4b066c42e0ec9..fe1b3ac50a75b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h @@ -105,19 +105,15 @@ #define PPSMC_MSG_UpdatePccWaitDecMaxStr 0x4C #define PPSMC_MSG_ResetSDMA 0x4D #define PPSMC_MSG_GetRasTableVersion 0x4E -#define PPSMC_MSG_GetRmaStatus 0x4F -#define PPSMC_MSG_GetErrorCount 0x50 -#define PPSMC_MSG_GetBadPageCount 0x51 -#define PPSMC_MSG_GetBadPageInfo 0x52 -#define PPSMC_MSG_GetBadPagePaAddrLoHi 0x53 -#define PPSMC_MSG_SetTimestampLoHi 0x54 -#define PPSMC_MSG_GetTimestampLoHi 0x55 -#define PPSMC_MSG_GetRasPolicy 0x56 -#define PPSMC_MSG_DumpErrorRecord 0x57 +#define PPSMC_MSG_GetBadPageCount 0x50 +#define PPSMC_MSG_GetBadPageMcaAddress 0x51 +#define PPSMC_MSG_SetTimestamp 0x53 +#define PPSMC_MSG_SetTimestampHi 0x54 +#define PPSMC_MSG_GetTimestamp 0x55 +#define PPSMC_MSG_GetBadPageIpIdLoHi 0x57 #define PPSMC_MSG_EraseRasTable 0x58 #define PPSMC_MSG_GetStaticMetricsTable 0x59 #define PPSMC_MSG_ResetVfArbitersByIndex 0x5A -#define PPSMC_MSG_GetBadPageSeverity 0x5B #define PPSMC_MSG_GetSystemMetricsTable 0x5C #define PPSMC_MSG_GetSystemMetricsVersion 0x5D #define PPSMC_MSG_ResetVCN 0x5E diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h index 71e8b6f52a042..4a1d964333b03 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -286,7 +286,14 @@ __SMU_DUMMY_MAP(ResetSDMA), \ __SMU_DUMMY_MAP(ResetVCN), \ __SMU_DUMMY_MAP(GetStaticMetricsTable), \ - __SMU_DUMMY_MAP(GetSystemMetricsTable), + __SMU_DUMMY_MAP(GetSystemMetricsTable), \ + __SMU_DUMMY_MAP(GetRASTableVersion), \ + __SMU_DUMMY_MAP(GetBadPageCount), \ + __SMU_DUMMY_MAP(GetBadPageMcaAddr), \ + __SMU_DUMMY_MAP(SetTimestamp), \ + __SMU_DUMMY_MAP(GetTimestamp), \ + __SMU_DUMMY_MAP(GetBadPageIpid), \ + __SMU_DUMMY_MAP(EraseRasTable), #undef __SMU_DUMMY_MAP #define __SMU_DUMMY_MAP(type) SMU_MSG_##type diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index c6cf0d0c4b825..f2e3cae43fda2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -139,6 +139,13 @@ const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[SMU_MSG_MAX_COUNT] = MSG_MAP(ResetVCN, PPSMC_MSG_ResetVCN, 0), MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 1), MSG_MAP(GetSystemMetricsTable, PPSMC_MSG_GetSystemMetricsTable, 1), + MSG_MAP(GetRASTableVersion, PPSMC_MSG_GetRasTableVersion, 0), + MSG_MAP(GetBadPageCount, PPSMC_MSG_GetBadPageCount, 0), + MSG_MAP(GetBadPageMcaAddr, PPSMC_MSG_GetBadPageMcaAddress, 0), + MSG_MAP(SetTimestamp, PPSMC_MSG_SetTimestamp, 0), + MSG_MAP(GetTimestamp, PPSMC_MSG_GetTimestamp, 0), + MSG_MAP(GetBadPageIpid, PPSMC_MSG_GetBadPageIpIdLoHi, 0), + MSG_MAP(EraseRasTable, PPSMC_MSG_EraseRasTable, 0), }; int smu_v13_0_12_tables_init(struct smu_context *smu) From 1e28a9b0ff505e6344f0253bc55086082213fe86 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Fri, 12 Sep 2025 12:43:35 +0800 Subject: [PATCH 2478/2653] drm/amd/pm: implement ras_smu_drv interface for smu v13.0.12 implement ras_smu_drv interface for smu v13.0.12 Signed-off-by: Gangliang Xie Signed-off-by: Yang Wang Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 26 ++++ .../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 129 ++++++++++++++++++ .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 1 + 3 files changed, 156 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index 40c0bf85f1d34..3c0b36dd37bf8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -503,6 +503,32 @@ struct ras_critical_region { uint64_t size; }; +struct ras_eeprom_table_version { + uint32_t minor : 16; + uint32_t major : 16; +}; + +struct ras_eeprom_smu_funcs { + int (*get_ras_table_version)(struct amdgpu_device *adev, + uint32_t *table_version); + int (*get_badpage_count)(struct amdgpu_device *adev, uint32_t *count, uint32_t timeout); + int (*get_badpage_mca_addr)(struct amdgpu_device *adev, uint16_t index, uint64_t *mca_addr); + int (*set_timestamp)(struct amdgpu_device *adev, uint64_t timestamp); + int (*get_timestamp)(struct amdgpu_device *adev, + uint16_t index, uint64_t *timestamp); + int (*get_badpage_ipid)(struct amdgpu_device *adev, uint16_t index, uint64_t *ipid); + int (*erase_ras_table)(struct amdgpu_device *adev, uint32_t *result); +}; + +enum ras_smu_feature_flags { + RAS_SMU_FEATURE_BIT__RAS_EEPROM = BIT_ULL(0), +}; + +struct ras_smu_drv { + const struct ras_eeprom_smu_funcs *smu_eeprom_funcs; + void (*ras_smu_feature_flags)(struct amdgpu_device *adev, uint64_t *flags); +}; + struct amdgpu_ras { void *ras_mgr; /* ras infrastructure */ diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index f2e3cae43fda2..24aaef1494a46 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -34,6 +34,7 @@ #include "amdgpu_fru_eeprom.h" #include #include "smu_cmn.h" +#include "amdgpu_ras.h" #undef MP1_Public #undef smnMP1_FIRMWARE_FLAGS @@ -925,3 +926,131 @@ const struct smu_temp_funcs smu_v13_0_12_temp_funcs = { .temp_metrics_is_supported = smu_v13_0_12_is_temp_metrics_supported, .get_temp_metrics = smu_v13_0_12_get_temp_metrics, }; + +static int smu_v13_0_12_get_ras_table_version(struct amdgpu_device *adev, + uint32_t *table_version) +{ + struct smu_context *smu = adev->powerplay.pp_handle; + + return smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_GetRASTableVersion, 0, table_version); +} + +static int smu_v13_0_12_get_badpage_count(struct amdgpu_device *adev, uint32_t *count, + uint32_t timeout) +{ + struct smu_context *smu = adev->powerplay.pp_handle; + uint64_t end, now; + int ret = 0; + + now = (uint64_t)ktime_to_ms(ktime_get()); + end = now + timeout; + do { + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_GetBadPageCount, 0, count); + /* eeprom is not ready */ + if (ret != -EBUSY) + return ret; + mdelay(10); + now = (uint64_t)ktime_to_ms(ktime_get()); + } while (now < end); + + return ret; +} + +static int smu_v13_0_12_set_timestamp(struct amdgpu_device *adev, uint64_t timestamp) +{ + struct smu_context *smu = adev->powerplay.pp_handle; + + return smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_SetTimestamp, (uint32_t)timestamp, 0); +} + +static int smu_v13_0_12_get_timestamp(struct amdgpu_device *adev, + uint16_t index, uint64_t *timestamp) +{ + struct smu_context *smu = adev->powerplay.pp_handle; + uint32_t temp; + int ret; + + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_GetTimestamp, index, &temp); + if (!ret) + *timestamp = temp; + + return ret; +} + +static int smu_v13_0_12_get_badpage_ipid(struct amdgpu_device *adev, + uint16_t index, uint64_t *ipid) +{ + struct smu_context *smu = adev->powerplay.pp_handle; + uint32_t temp_arg, temp_ipid_lo, temp_ipid_high; + int ret; + + temp_arg = index | (1 << 16); + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_GetBadPageIpid, temp_arg, &temp_ipid_lo); + if (ret) + return ret; + + temp_arg = index | (2 << 16); + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_GetBadPageIpid, temp_arg, &temp_ipid_high); + if (!ret) + *ipid = (uint64_t)temp_ipid_high << 32 | temp_ipid_lo; + return ret; +} + +static int smu_v13_0_12_erase_ras_table(struct amdgpu_device *adev, + uint32_t *result) +{ + struct smu_context *smu = adev->powerplay.pp_handle; + + return smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_EraseRasTable, 0, result); +} + +static int smu_v13_0_12_get_badpage_mca_addr(struct amdgpu_device *adev, + uint16_t index, uint64_t *mca_addr) +{ + struct smu_context *smu = adev->powerplay.pp_handle; + uint32_t temp_arg, temp_addr_lo, temp_addr_high; + int ret; + + temp_arg = index | (1 << 16); + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_GetBadPageMcaAddr, temp_arg, &temp_addr_lo); + if (ret) + return ret; + + temp_arg = index | (2 << 16); + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_GetBadPageMcaAddr, temp_arg, &temp_addr_high); + if (!ret) + *mca_addr = (uint64_t)temp_addr_high << 32 | temp_addr_lo; + return ret; +} + +static const struct ras_eeprom_smu_funcs smu_v13_0_12_eeprom_smu_funcs = { + .get_ras_table_version = smu_v13_0_12_get_ras_table_version, + .get_badpage_count = smu_v13_0_12_get_badpage_count, + .get_badpage_mca_addr = smu_v13_0_12_get_badpage_mca_addr, + .set_timestamp = smu_v13_0_12_set_timestamp, + .get_timestamp = smu_v13_0_12_get_timestamp, + .get_badpage_ipid = smu_v13_0_12_get_badpage_ipid, + .erase_ras_table = smu_v13_0_12_erase_ras_table, +}; + +static void smu_v13_0_12_ras_smu_feature_flags(struct amdgpu_device *adev, uint64_t *flags) +{ + if (!flags) + return; + + *flags = 0ULL; +} + +const struct ras_smu_drv smu_v13_0_12_ras_smu_drv = { + .smu_eeprom_funcs = &smu_v13_0_12_eeprom_smu_funcs, + .ras_smu_feature_flags = smu_v13_0_12_ras_smu_feature_flags, +}; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h index ba865ae7eca2a..ecec7af8a64f9 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h @@ -105,6 +105,7 @@ int smu_v13_0_12_get_npm_data(struct smu_context *smu, extern const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[]; extern const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[]; extern const struct smu_temp_funcs smu_v13_0_12_temp_funcs; +extern const struct ras_smu_drv smu_v13_0_12_ras_smu_drv; #if defined(SWSMU_CODE_LAYER_L2) #include "smu_cmn.h" From 420323b6a4d8ef79e687488f5e4fb1943ebfa80b Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Mon, 15 Sep 2025 12:52:35 +0800 Subject: [PATCH 2479/2653] drm/amd/pm: add smu ras driver framework add functions to get smu ras driver Signed-off-by: Gangliang Xie Signed-off-by: Yang Wang Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 1 + drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 7 +++++++ drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 1 + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 11 ++++++++++ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 7 +++++++ .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 21 +++++++++++++++++++ drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 1 + 7 files changed, 49 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index 3c0b36dd37bf8..674bcd3c814c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -620,6 +620,7 @@ struct amdgpu_ras { /* Disable/Enable uniras switch */ bool uniras_enabled; + const struct ras_smu_drv *ras_smu_drv; }; struct ras_fs_data { diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index 4b3de22f2ecc3..3e8ad5b91a49f 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -2130,3 +2130,10 @@ void amdgpu_dpm_phase_det_debugfs_init(struct amdgpu_device *adev) amdgpu_smu_phase_det_debugfs_init(adev); } + +const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct amdgpu_device *adev) +{ + void *pp_handle = adev->powerplay.pp_handle; + + return smu_get_ras_smu_driver(pp_handle); +} diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h index ba6e650d66c91..6a73df27088e4 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h @@ -613,5 +613,6 @@ int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask); bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev); bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev, enum smu_temp_metric_type type); +const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index ef51964dfc902..f97cb2a27689e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2803,6 +2803,17 @@ const struct amdgpu_ip_block_version smu_v14_0_ip_block = { .funcs = &smu_ip_funcs, }; +const struct ras_smu_drv *smu_get_ras_smu_driver(void *handle) +{ + struct smu_context *smu = (struct smu_context *)handle; + const struct ras_smu_drv *tmp = NULL; + int ret; + + ret = smu_get_ras_smu_drv(smu, &tmp); + + return ret ? NULL : tmp; +} + static int smu_load_microcode(void *handle) { struct smu_context *smu = handle; diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index fab1ec2b3cc6a..4d5dfd936ee24 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -1562,6 +1562,12 @@ struct pptable_funcs { int (*ras_send_msg)(struct smu_context *smu, enum smu_message_type msg, uint32_t param, uint32_t *read_arg); + + /** + * @get_ras_smu_drv: Get RAS smu driver interface + * Return: ras_smu_drv * + */ + int (*get_ras_smu_drv)(struct smu_context *smu, const struct ras_smu_drv **ras_smu_drv); }; typedef enum { @@ -1826,6 +1832,7 @@ int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, int level); ssize_t smu_get_pm_policy_info(struct smu_context *smu, enum pp_pm_policy p_type, char *sysbuf); +const struct ras_smu_drv *smu_get_ras_smu_driver(void *handle); int smu_set_phase_det_param(struct smu_context *smu, enum pp_pm_phase_det_param_id id, uint32_t val); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 9e6a672cd9b13..f341942303c59 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -4076,6 +4076,26 @@ static void smu_v13_0_6_set_temp_funcs(struct smu_context *smu) == IP_VERSION(13, 0, 12)) ? &smu_v13_0_12_temp_funcs : NULL; } +static int smu_v13_0_6_get_ras_smu_drv(struct smu_context *smu, const struct ras_smu_drv **ras_smu_drv) +{ + if (!ras_smu_drv) + return -EINVAL; + + if (amdgpu_sriov_vf(smu->adev)) + return -EOPNOTSUPP; + + switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) { + case IP_VERSION(13, 0, 12): + *ras_smu_drv = &smu_v13_0_12_ras_smu_drv; + break; + default: + *ras_smu_drv = NULL; + break; + } + + return 0; +} + static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { /* init dpm */ .get_allowed_feature_mask = smu_v13_0_6_get_allowed_feature_mask, @@ -4135,6 +4155,7 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { .dpm_reset_vcn = smu_v13_0_6_reset_vcn, .post_init = smu_v13_0_6_post_init, .ras_send_msg = smu_v13_0_6_ras_send_msg, + .get_ras_smu_drv = smu_v13_0_6_get_ras_smu_drv, }; void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h index c09ecf1a68a0d..34f6b4b1c3ba0 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h @@ -100,6 +100,7 @@ #define smu_is_asic_wbrf_supported(smu) smu_ppt_funcs(is_asic_wbrf_supported, false, smu) #define smu_enable_uclk_shadow(smu, enable) smu_ppt_funcs(enable_uclk_shadow, 0, smu, enable) #define smu_set_wbrf_exclusion_ranges(smu, freq_band_range) smu_ppt_funcs(set_wbrf_exclusion_ranges, -EOPNOTSUPP, smu, freq_band_range) +#define smu_get_ras_smu_drv(smu, ras_smu_drv) smu_ppt_funcs(get_ras_smu_drv, -EOPNOTSUPP, smu, ras_smu_drv) #endif #endif From 3ea69ed5494d2351948b43f29a7551bd906e0647 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Mon, 15 Sep 2025 12:55:36 +0800 Subject: [PATCH 2480/2653] drm/amdgpu: add function to check if pmfw eeprom is supported add function to check if pmfw is supported, skip eeprom check and recover when pmfw eeprom is supported Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 + .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 46 ++++++++++++++++++- .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h | 2 + 3 files changed, 48 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 0453ff6e79a6d..7c929f93842ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3789,6 +3789,8 @@ int amdgpu_ras_init_badpage_info(struct amdgpu_device *adev) return 0; control = &con->eeprom_control; + con->ras_smu_drv = amdgpu_dpm_get_ras_smu_driver(adev); + ret = amdgpu_ras_eeprom_init(control); control->is_eeprom_valid = !ret; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 011fa47480840..89d0def82797d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -1546,7 +1546,8 @@ void amdgpu_ras_eeprom_check_and_recover(struct amdgpu_device *adev) struct amdgpu_ras_eeprom_control *control; int res; - if (!__is_ras_eeprom_supported(adev) || !ras) + if (!__is_ras_eeprom_supported(adev) || !ras || + amdgpu_ras_smu_eeprom_supported(adev)) return; control = &ras->eeprom_control; if (!control->is_eeprom_valid) @@ -1566,4 +1567,45 @@ void amdgpu_ras_eeprom_check_and_recover(struct amdgpu_device *adev) control->is_eeprom_valid = false; } return; -} \ No newline at end of file +} + +static const struct ras_smu_drv *amdgpu_ras_get_smu_ras_drv(struct amdgpu_device *adev) +{ + struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); + + if (!ras) + return NULL; + + return ras->ras_smu_drv; +} + +static uint64_t amdgpu_ras_smu_get_feature_flags(struct amdgpu_device *adev) +{ + const struct ras_smu_drv *ras_smu_drv = amdgpu_ras_get_smu_ras_drv(adev); + uint64_t flags = 0ULL; + + if (!ras_smu_drv) + goto out; + + if (ras_smu_drv->ras_smu_feature_flags) + ras_smu_drv->ras_smu_feature_flags(adev, &flags); + +out: + return flags; +} + +bool amdgpu_ras_smu_eeprom_supported(struct amdgpu_device *adev) +{ + const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); + uint64_t flags = 0ULL; + + if (!__is_ras_eeprom_supported(adev) || !smu_ras_drv) + return false; + + if (!smu_ras_drv->smu_eeprom_funcs) + return false; + + flags = amdgpu_ras_smu_get_feature_flags(adev); + + return !!(flags & RAS_SMU_FEATURE_BIT__RAS_EEPROM); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h index ebfca4cb5688b..feff46b22b6ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h @@ -163,6 +163,8 @@ int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control); void amdgpu_ras_eeprom_check_and_recover(struct amdgpu_device *adev); +bool amdgpu_ras_smu_eeprom_supported(struct amdgpu_device *adev); + extern const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops; extern const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops; From 057fa5108c8f3cc75a6b33aaeb89f8d01bc8c848 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Mon, 15 Sep 2025 17:13:25 +0800 Subject: [PATCH 2481/2653] drm/amdgpu: add wrapper functions for pmfw eeprom interface add wrapper functions for pmfw eeprom interface, for these interfaces to be easily and safely called Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 98 +++++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h | 21 ++++ 2 files changed, 119 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 89d0def82797d..258ff0f121a29 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -1609,3 +1609,101 @@ bool amdgpu_ras_smu_eeprom_supported(struct amdgpu_device *adev) return !!(flags & RAS_SMU_FEATURE_BIT__RAS_EEPROM); } + +int amdgpu_ras_smu_get_table_version(struct amdgpu_device *adev, + uint32_t *table_version) +{ + const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); + + if (!amdgpu_ras_smu_eeprom_supported(adev)) + return -EOPNOTSUPP; + + if (smu_ras_drv->smu_eeprom_funcs->get_ras_table_version) + return smu_ras_drv->smu_eeprom_funcs->get_ras_table_version(adev, + table_version); + return -EOPNOTSUPP; +} + +int amdgpu_ras_smu_get_badpage_count(struct amdgpu_device *adev, + uint32_t *count, uint32_t timeout) +{ + const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); + + if (!amdgpu_ras_smu_eeprom_supported(adev)) + return -EOPNOTSUPP; + + if (smu_ras_drv->smu_eeprom_funcs->get_badpage_count) + return smu_ras_drv->smu_eeprom_funcs->get_badpage_count(adev, + count, timeout); + return -EOPNOTSUPP; +} + +int amdgpu_ras_smu_get_badpage_mca_addr(struct amdgpu_device *adev, + uint16_t index, uint64_t *mca_addr) +{ + const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); + + if (!amdgpu_ras_smu_eeprom_supported(adev)) + return -EOPNOTSUPP; + + if (smu_ras_drv->smu_eeprom_funcs->get_badpage_mca_addr) + return smu_ras_drv->smu_eeprom_funcs->get_badpage_mca_addr(adev, + index, mca_addr); + return -EOPNOTSUPP; +} + +int amdgpu_ras_smu_set_timestamp(struct amdgpu_device *adev, + uint64_t timestamp) +{ + const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); + + if (!amdgpu_ras_smu_eeprom_supported(adev)) + return -EOPNOTSUPP; + + if (smu_ras_drv->smu_eeprom_funcs->set_timestamp) + return smu_ras_drv->smu_eeprom_funcs->set_timestamp(adev, + timestamp); + return -EOPNOTSUPP; +} + +int amdgpu_ras_smu_get_timestamp(struct amdgpu_device *adev, + uint16_t index, uint64_t *timestamp) +{ + const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); + + if (!amdgpu_ras_smu_eeprom_supported(adev)) + return -EOPNOTSUPP; + + if (smu_ras_drv->smu_eeprom_funcs->get_timestamp) + return smu_ras_drv->smu_eeprom_funcs->get_timestamp(adev, + index, timestamp); + return -EOPNOTSUPP; +} + +int amdgpu_ras_smu_get_badpage_ipid(struct amdgpu_device *adev, + uint16_t index, uint64_t *ipid) +{ + const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); + + if (!amdgpu_ras_smu_eeprom_supported(adev)) + return -EOPNOTSUPP; + + if (smu_ras_drv->smu_eeprom_funcs->get_badpage_ipid) + return smu_ras_drv->smu_eeprom_funcs->get_badpage_ipid(adev, + index, ipid); + return -EOPNOTSUPP; +} + +int amdgpu_ras_smu_erase_ras_table(struct amdgpu_device *adev, + uint32_t *result) +{ + const struct ras_smu_drv *smu_ras_drv = amdgpu_ras_get_smu_ras_drv(adev); + + if (!amdgpu_ras_smu_eeprom_supported(adev)) + return -EOPNOTSUPP; + + if (smu_ras_drv->smu_eeprom_funcs->erase_ras_table) + return smu_ras_drv->smu_eeprom_funcs->erase_ras_table(adev, + result); + return -EOPNOTSUPP; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h index feff46b22b6ff..cfbd402ddea2f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h @@ -165,6 +165,27 @@ void amdgpu_ras_eeprom_check_and_recover(struct amdgpu_device *adev); bool amdgpu_ras_smu_eeprom_supported(struct amdgpu_device *adev); +int amdgpu_ras_smu_get_table_version(struct amdgpu_device *adev, + uint32_t *table_version); + +int amdgpu_ras_smu_get_badpage_count(struct amdgpu_device *adev, + uint32_t *count, uint32_t timeout); + +int amdgpu_ras_smu_get_badpage_mca_addr(struct amdgpu_device *adev, + uint16_t index, uint64_t *mca_addr); + +int amdgpu_ras_smu_set_timestamp(struct amdgpu_device *adev, + uint64_t timestamp); + +int amdgpu_ras_smu_get_timestamp(struct amdgpu_device *adev, + uint16_t index, uint64_t *timestamp); + +int amdgpu_ras_smu_get_badpage_ipid(struct amdgpu_device *adev, + uint16_t index, uint64_t *ipid); + +int amdgpu_ras_smu_erase_ras_table(struct amdgpu_device *adev, + uint32_t *result); + extern const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops; extern const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops; From 96ac1006fb3ddff72ce86e081955c9d4dd979798 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Tue, 28 Oct 2025 16:18:31 +0800 Subject: [PATCH 2482/2653] drm/amdgpu: suspend ras module before gpu reset During gpu reset, all GPU-related resources are inaccessible. To avoid affecting ras functionality, suspend ras module before gpu reset and resume it after gpu reset is complete. V2: Rename functions to avoid misunderstanding. V3: Move flush_delayed_work to amdgpu_ras_process_pause, Move schedule_delayed_work to amdgpu_ras_process_unpause. V4: Rename functions. V5: Move the function to amdgpu_ras.c. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang Acked-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 30 ++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 5 ++ .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c | 22 +++++++ .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h | 5 ++ .../drm/amd/ras/ras_mgr/amdgpu_ras_process.c | 64 +++++++++++++++++++ .../drm/amd/ras/ras_mgr/amdgpu_ras_process.h | 4 ++ .../gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c | 6 ++ drivers/gpu/drm/amd/ras/rascore/ras.h | 2 + drivers/gpu/drm/amd/ras/rascore/ras_process.c | 7 ++ 10 files changed, 148 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 5f1bda51df034..7ee3dabc0cf58 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -73,6 +73,7 @@ #include "amdgpu_xgmi.h" #include "amdgpu_ras.h" +#include "amdgpu_ras_mgr.h" #include "amdgpu_pmu.h" #include "amdgpu_fru_eeprom.h" #include "amdgpu_reset.h" @@ -6717,6 +6718,9 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, goto end_reset; } + /* Cannot be called after locking reset domain */ + amdgpu_ras_pre_reset(adev, &device_list); + /* We need to lock reset domain only once both for XGMI and single device */ amdgpu_device_recovery_get_reset_lock(adev, &device_list); @@ -6748,6 +6752,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, reset_unlock: amdgpu_device_recovery_put_reset_lock(adev, &device_list); end_reset: + amdgpu_ras_post_reset(adev, &device_list); if (hive) { mutex_unlock(&hive->hive_lock); amdgpu_put_xgmi_hive(hive); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 7c929f93842ce..3e8d752612fcd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2935,8 +2935,12 @@ static void amdgpu_ras_do_recovery(struct work_struct *work) type = amdgpu_ras_get_fatal_error_event(adev); list_for_each_entry(remote_adev, device_list_handle, gmc.xgmi.head) { - amdgpu_ras_query_err_status(remote_adev); - amdgpu_ras_log_on_err_counter(remote_adev, type); + if (amdgpu_uniras_enabled(remote_adev)) { + amdgpu_ras_mgr_update_ras_ecc(remote_adev); + } else { + amdgpu_ras_query_err_status(remote_adev); + amdgpu_ras_log_on_err_counter(remote_adev, type); + } } } @@ -5707,3 +5711,25 @@ bool amdgpu_ras_check_critical_address(struct amdgpu_device *adev, uint64_t addr return ret; } + +void amdgpu_ras_pre_reset(struct amdgpu_device *adev, + struct list_head *device_list) +{ + struct amdgpu_device *tmp_adev = NULL; + + list_for_each_entry(tmp_adev, device_list, reset_list) { + if (amdgpu_uniras_enabled(tmp_adev)) + amdgpu_ras_mgr_pre_reset(tmp_adev); + } +} + +void amdgpu_ras_post_reset(struct amdgpu_device *adev, + struct list_head *device_list) +{ + struct amdgpu_device *tmp_adev = NULL; + + list_for_each_entry(tmp_adev, device_list, reset_list) { + if (amdgpu_uniras_enabled(tmp_adev)) + amdgpu_ras_mgr_post_reset(tmp_adev); + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index 674bcd3c814c0..ff44190d7d98e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -1039,4 +1039,9 @@ void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id, const char *fmt, ...); bool amdgpu_ras_is_rma(struct amdgpu_device *adev); + +void amdgpu_ras_pre_reset(struct amdgpu_device *adev, + struct list_head *device_list); +void amdgpu_ras_post_reset(struct amdgpu_device *adev, + struct list_head *device_list); #endif diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c index adb01bdee0037..afe8135b62586 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -624,3 +624,25 @@ int amdgpu_ras_mgr_handle_ras_cmd(struct amdgpu_device *adev, return ret; } + +int amdgpu_ras_mgr_pre_reset(struct amdgpu_device *adev) +{ + if (!amdgpu_ras_mgr_is_ready(adev)) { + RAS_DEV_ERR(adev, "Invalid ras suspend!\n"); + return -EPERM; + } + + amdgpu_ras_process_pre_reset(adev); + return 0; +} + +int amdgpu_ras_mgr_post_reset(struct amdgpu_device *adev) +{ + if (!amdgpu_ras_mgr_is_ready(adev)) { + RAS_DEV_ERR(adev, "Invalid ras resume!\n"); + return -EPERM; + } + + amdgpu_ras_process_post_reset(adev); + return 0; +} diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h index 42f190a8feb94..8fb7eb4b8f132 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h @@ -52,6 +52,9 @@ struct amdgpu_ras_mgr { struct ras_event_manager ras_event_mgr; uint64_t last_poison_consumption_seqno; bool ras_is_ready; + + bool is_paused; + struct completion ras_event_done; }; extern const struct amdgpu_ip_block_version ras_v1_0_ip_block; @@ -75,4 +78,6 @@ bool amdgpu_ras_mgr_is_rma(struct amdgpu_device *adev); int amdgpu_ras_mgr_handle_ras_cmd(struct amdgpu_device *adev, uint32_t cmd_id, void *input, uint32_t input_size, void *output, uint32_t out_size); +int amdgpu_ras_mgr_pre_reset(struct amdgpu_device *adev); +int amdgpu_ras_mgr_post_reset(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c index 6727fc9a2b9b7..5782c007de71c 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c @@ -29,6 +29,7 @@ #include "amdgpu_ras_process.h" #define RAS_MGR_RETIRE_PAGE_INTERVAL 100 +#define RAS_EVENT_PROCESS_TIMEOUT 1200 static void ras_process_retire_page_dwork(struct work_struct *work) { @@ -57,6 +58,9 @@ int amdgpu_ras_process_init(struct amdgpu_device *adev) { struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + ras_mgr->is_paused = false; + init_completion(&ras_mgr->ras_event_done); + INIT_DELAYED_WORK(&ras_mgr->retire_page_dwork, ras_process_retire_page_dwork); return 0; @@ -66,6 +70,7 @@ int amdgpu_ras_process_fini(struct amdgpu_device *adev) { struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + ras_mgr->is_paused = false; /* Save all cached bad pages to eeprom */ flush_delayed_work(&ras_mgr->retire_page_dwork); cancel_delayed_work_sync(&ras_mgr->retire_page_dwork); @@ -124,3 +129,62 @@ int amdgpu_ras_process_handle_consumption_interrupt(struct amdgpu_device *adev, return ras_process_add_interrupt_req(ras_mgr->ras_core, &req, false); } + +int amdgpu_ras_process_begin(struct amdgpu_device *adev) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + + if (ras_mgr->is_paused) + return -EAGAIN; + + reinit_completion(&ras_mgr->ras_event_done); + return 0; +} + +int amdgpu_ras_process_end(struct amdgpu_device *adev) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + + complete(&ras_mgr->ras_event_done); + return 0; +} + +int amdgpu_ras_process_pre_reset(struct amdgpu_device *adev) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + long rc; + + if (!ras_mgr || !ras_mgr->ras_core) + return -EINVAL; + + if (!ras_mgr->ras_core->is_initialized) + return -EPERM; + + ras_mgr->is_paused = true; + + /* Wait for RAS event processing to complete */ + rc = wait_for_completion_interruptible_timeout(&ras_mgr->ras_event_done, + msecs_to_jiffies(RAS_EVENT_PROCESS_TIMEOUT)); + if (rc <= 0) + RAS_DEV_WARN(adev, "Waiting for ras process to complete %s\n", + rc ? "interrupted" : "timeout"); + + flush_delayed_work(&ras_mgr->retire_page_dwork); + return 0; +} + +int amdgpu_ras_process_post_reset(struct amdgpu_device *adev) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + + if (!ras_mgr || !ras_mgr->ras_core) + return -EINVAL; + + if (!ras_mgr->ras_core->is_initialized) + return -EPERM; + + ras_mgr->is_paused = false; + + schedule_delayed_work(&ras_mgr->retire_page_dwork, 0); + return 0; +} diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.h index b9502bd21bebe..d55cdaeac4410 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.h +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.h @@ -34,4 +34,8 @@ int amdgpu_ras_process_handle_unexpected_interrupt(struct amdgpu_device *adev, void *data); int amdgpu_ras_process_handle_consumption_interrupt(struct amdgpu_device *adev, void *data); +int amdgpu_ras_process_begin(struct amdgpu_device *adev); +int amdgpu_ras_process_end(struct amdgpu_device *adev); +int amdgpu_ras_process_pre_reset(struct amdgpu_device *adev); +int amdgpu_ras_process_post_reset(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c index f21cd55a25be9..45ed8c3b5563b 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c @@ -142,6 +142,12 @@ static int amdgpu_ras_sys_event_notifier(struct ras_core_context *ras_core, case RAS_EVENT_ID__RESET_GPU: ret = amdgpu_ras_mgr_reset_gpu(ras_core->dev, *(uint32_t *)data); break; + case RAS_EVENT_ID__RAS_EVENT_PROC_BEGIN: + ret = amdgpu_ras_process_begin(ras_core->dev); + break; + case RAS_EVENT_ID__RAS_EVENT_PROC_END: + ret = amdgpu_ras_process_end(ras_core->dev); + break; default: RAS_DEV_WARN(ras_core->dev, "Invalid ras notify event:%d\n", event_id); break; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h index fa224b36e3f2d..3396b2e0949df 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras.h @@ -115,6 +115,8 @@ enum ras_notify_event { RAS_EVENT_ID__FATAL_ERROR_DETECTED, RAS_EVENT_ID__RESET_GPU, RAS_EVENT_ID__RESET_VF, + RAS_EVENT_ID__RAS_EVENT_PROC_BEGIN, + RAS_EVENT_ID__RAS_EVENT_PROC_END, }; enum ras_gpu_status { diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_process.c b/drivers/gpu/drm/amd/ras/rascore/ras_process.c index 02f0657f78a39..3267dcdb169cd 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_process.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_process.c @@ -162,6 +162,11 @@ int ras_process_handle_ras_event(struct ras_core_context *ras_core) uint32_t umc_event_count; int ret; + ret = ras_core_event_notify(ras_core, + RAS_EVENT_ID__RAS_EVENT_PROC_BEGIN, NULL); + if (ret) + return ret; + ras_aca_clear_fatal_flag(ras_core); ras_umc_log_pending_bad_bank(ras_core); @@ -185,6 +190,8 @@ int ras_process_handle_ras_event(struct ras_core_context *ras_core) atomic_set(&ras_proc->umc_interrupt_count, 0); } + ras_core_event_notify(ras_core, + RAS_EVENT_ID__RAS_EVENT_PROC_END, NULL); return ret; } From 27cb50613618e12787f5de943ff4c62b2a13b1ad Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 22 Oct 2025 17:11:38 -0400 Subject: [PATCH 2483/2653] drm/amdgpu: fix possible fence leaks from job structure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If we don't end up initializing the fences, free them when we free the job. We can't set the hw_fence to NULL after emitting it because we need it in the cleanup path for the submit direct case. v2: take a reference to the fences if we emit them v3: handle non-job fence in error paths Fixes: db36632ea51e ("drm/amdgpu: clean up and unify hw fence handling") Reviewed-by: Jesse Zhang (v1) Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 19 +++++++++++++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 18 ++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 ++ 3 files changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index c8def27b6d1cd..3ef00b154e25f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -177,18 +177,21 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, if (!ring->sched.ready) { dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name); - return -EINVAL; + r = -EINVAL; + goto free_fence; } if (vm && !job->vmid) { dev_err(adev->dev, "VM IB without ID\n"); - return -EINVAL; + r = -EINVAL; + goto free_fence; } if ((ib->flags & AMDGPU_IB_FLAGS_SECURE) && (!ring->funcs->secure_submission_supported)) { dev_err(adev->dev, "secure submissions not supported on ring <%s>\n", ring->name); - return -EINVAL; + r = -EINVAL; + goto free_fence; } alloc_size = ring->funcs->emit_frame_size + num_ibs * @@ -202,7 +205,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, r = amdgpu_ring_alloc(ring, alloc_size); if (r) { dev_err(adev->dev, "scheduling IB failed (%d).\n", r); - return r; + goto free_fence; } need_ctx_switch = ring->current_ctx != fence_ctx; @@ -310,6 +313,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, return r; } *f = &af->base; + /* get a ref for the job */ + if (job) + dma_fence_get(*f); if (ring->funcs->insert_end) ring->funcs->insert_end(ring); @@ -336,6 +342,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, amdgpu_ring_commit(ring); return 0; + +free_fence: + if (!job) + kfree(af); + return r; } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index fd6aade7ee9e3..efa3281145f6c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -293,6 +293,15 @@ static void amdgpu_job_free_cb(struct drm_sched_job *s_job) amdgpu_sync_free(&job->explicit_sync); + if (job->hw_fence->base.ops) + dma_fence_put(&job->hw_fence->base); + else + kfree(job->hw_fence); + if (job->hw_vm_fence->base.ops) + dma_fence_put(&job->hw_vm_fence->base); + else + kfree(job->hw_vm_fence); + kfree(job); } @@ -322,6 +331,15 @@ void amdgpu_job_free(struct amdgpu_job *job) if (job->gang_submit != &job->base.s_fence->scheduled) dma_fence_put(job->gang_submit); + if (job->hw_fence->base.ops) + dma_fence_put(&job->hw_fence->base); + else + kfree(job->hw_fence); + if (job->hw_vm_fence->base.ops) + dma_fence_put(&job->hw_vm_fence->base); + else + kfree(job->hw_vm_fence); + kfree(job); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index e2906f55bac51..ca5a825e4665d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -849,6 +849,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, if (r) return r; fence = &job->hw_vm_fence->base; + /* get a ref for the job */ + dma_fence_get(fence); } if (vm_flush_needed) { From 12de3ab0b831f35ada60c0fe88ec4e4eea91f0da Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Thu, 4 Sep 2025 18:04:33 +0800 Subject: [PATCH 2484/2653] drm/amdgpu: adapt reset function for pmfw eeprom adapt reset function for pmfw eeprom Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 61 +++++++++++-------- 1 file changed, 36 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 258ff0f121a29..e9c5781e4376c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -444,40 +444,51 @@ int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + u32 erase_res = 0; u8 csum; int res; mutex_lock(&control->ras_tbl_mutex); - hdr->header = RAS_TABLE_HDR_VAL; - amdgpu_ras_set_eeprom_table_version(control); + if (!amdgpu_ras_smu_eeprom_supported(adev)) { + hdr->header = RAS_TABLE_HDR_VAL; + amdgpu_ras_set_eeprom_table_version(control); - if (hdr->version >= RAS_TABLE_VER_V2_1) { - hdr->first_rec_offset = RAS_RECORD_START_V2_1; - hdr->tbl_size = RAS_TABLE_HEADER_SIZE + - RAS_TABLE_V2_1_INFO_SIZE; - rai->rma_status = GPU_HEALTH_USABLE; - /** - * GPU health represented as a percentage. - * 0 means worst health, 100 means fully health. - */ - rai->health_percent = 100; - /* ecc_page_threshold = 0 means disable bad page retirement */ - rai->ecc_page_threshold = con->bad_page_cnt_threshold; + if (hdr->version >= RAS_TABLE_VER_V2_1) { + hdr->first_rec_offset = RAS_RECORD_START_V2_1; + hdr->tbl_size = RAS_TABLE_HEADER_SIZE + + RAS_TABLE_V2_1_INFO_SIZE; + rai->rma_status = GPU_HEALTH_USABLE; + /** + * GPU health represented as a percentage. + * 0 means worst health, 100 means fully health. + */ + rai->health_percent = 100; + /* ecc_page_threshold = 0 means disable bad page retirement */ + rai->ecc_page_threshold = con->bad_page_cnt_threshold; + } else { + hdr->first_rec_offset = RAS_RECORD_START; + hdr->tbl_size = RAS_TABLE_HEADER_SIZE; + } + + csum = __calc_hdr_byte_sum(control); + if (hdr->version >= RAS_TABLE_VER_V2_1) + csum += __calc_ras_info_byte_sum(control); + csum = -csum; + hdr->checksum = csum; + res = __write_table_header(control); + if (!res && hdr->version > RAS_TABLE_VER_V1) + res = __write_table_ras_info(control); } else { - hdr->first_rec_offset = RAS_RECORD_START; - hdr->tbl_size = RAS_TABLE_HEADER_SIZE; + res = amdgpu_ras_smu_erase_ras_table(adev, &erase_res); + if (res || erase_res) { + dev_warn(adev->dev, "RAS EEPROM reset failed, res:%d result:%d", + res, erase_res); + if (!res) + res = -EIO; + } } - csum = __calc_hdr_byte_sum(control); - if (hdr->version >= RAS_TABLE_VER_V2_1) - csum += __calc_ras_info_byte_sum(control); - csum = -csum; - hdr->checksum = csum; - res = __write_table_header(control); - if (!res && hdr->version > RAS_TABLE_VER_V1) - res = __write_table_ras_info(control); - control->ras_num_recs = 0; control->ras_num_bad_pages = 0; control->ras_num_mca_recs = 0; From 88a917d1403f7a0fda71fa66cabbaa08c2570778 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Thu, 4 Sep 2025 18:07:40 +0800 Subject: [PATCH 2485/2653] drm/amdgpu: add initialization function for pmfw eeprom add initialization function for pmfw eeprom Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index e9c5781e4376c..6b51574530a4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -1386,6 +1386,42 @@ static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control) return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res; } +static int amdgpu_ras_smu_eeprom_init(struct amdgpu_ras_eeprom_control *control) +{ + struct amdgpu_device *adev = to_amdgpu_device(control); + struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; + struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); + uint64_t local_time; + int res; + + ras->is_rma = false; + + if (!__is_ras_eeprom_supported(adev)) + return 0; + mutex_init(&control->ras_tbl_mutex); + + res = amdgpu_ras_smu_get_table_version(adev, &(hdr->version)); + if (res) + return res; + + res = amdgpu_ras_smu_get_badpage_count(adev, + &(control->ras_num_recs), 100); + if (res) + return res; + + local_time = (uint64_t)ktime_get_real_seconds(); + res = amdgpu_ras_smu_set_timestamp(adev, local_time); + if (res) + return res; + + control->ras_max_record_count = 4000; + + control->ras_num_mca_recs = 0; + control->ras_num_pa_recs = 0; + + return 0; +} + int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) { struct amdgpu_device *adev = to_amdgpu_device(control); @@ -1394,6 +1430,9 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); int res; + if (amdgpu_ras_smu_eeprom_supported(adev)) + return amdgpu_ras_smu_eeprom_init(control); + ras->is_rma = false; if (!__is_ras_eeprom_supported(adev)) From 17db650454583681cfa23d454ba8836407beaab6 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Thu, 4 Sep 2025 18:09:40 +0800 Subject: [PATCH 2486/2653] drm/amdgpu: add check function for pmfw eeprom add check function for pmfw eeprom Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 6b51574530a4a..3c646d9dad778 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -1499,6 +1499,47 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) return 0; } +static int amdgpu_ras_smu_eeprom_check(struct amdgpu_ras_eeprom_control *control) +{ + struct amdgpu_device *adev = to_amdgpu_device(control); + struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); + + if (!__is_ras_eeprom_supported(adev)) + return 0; + + control->ras_num_bad_pages = ras->bad_page_num; + + if ((ras->bad_page_cnt_threshold < control->ras_num_bad_pages) && + amdgpu_bad_page_threshold != 0) { + dev_warn(adev->dev, + "RAS records:%d exceed threshold:%d\n", + control->ras_num_bad_pages, ras->bad_page_cnt_threshold); + if ((amdgpu_bad_page_threshold == -1) || + (amdgpu_bad_page_threshold == -2)) { + dev_warn(adev->dev, + "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n"); + } else { + ras->is_rma = true; + dev_warn(adev->dev, + "User defined threshold is set, runtime service will be halt when threshold is reached\n"); + } + + return 0; + } + + dev_dbg(adev->dev, + "Found existing EEPROM table with %d records", + control->ras_num_bad_pages); + + /* Warn if we are at 90% of the threshold or above + */ + if (10 * control->ras_num_bad_pages >= 9 * ras->bad_page_cnt_threshold) + dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", + control->ras_num_bad_pages, + ras->bad_page_cnt_threshold); + return 0; +} + int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) { struct amdgpu_device *adev = to_amdgpu_device(control); @@ -1506,6 +1547,9 @@ int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); int res = 0; + if (amdgpu_ras_smu_eeprom_supported(adev)) + return amdgpu_ras_smu_eeprom_check(control); + if (!__is_ras_eeprom_supported(adev)) return 0; From ffcc9883a4ad6fc4b2c347d58ad615dbcf5c5306 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Wed, 22 Oct 2025 10:36:40 +0800 Subject: [PATCH 2487/2653] drm/amd/pm: check pmfw eeprom feature bit get and check the pmfw eeprom feature bit to decide if pmfw eeprom is supported Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- .../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h | 2 +- drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 ++- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 7 +++++++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 3 +++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 1 + 5 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h index bf6aa9620911b..fa43d2e229a09 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h @@ -87,7 +87,7 @@ typedef enum { /*37*/ FEATURE_DVO = 37, /*38*/ FEATURE_XVMINORPSM_CLKSTOP_DS = 38, /*39*/ FEATURE_GLOBAL_DPM = 39, -/*40*/ FEATURE_NODE_POWER_MANAGER = 40, +/*40*/ FEATURE_HROM_EN = 40, /*41*/ NUM_FEATURES = 41 } FEATURE_LIST_e; diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h index 4a1d964333b03..bd759b0990e42 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -472,7 +472,8 @@ enum smu_clk_type { __SMU_DUMMY_MAP(GFX_EDC_XVMIN), \ __SMU_DUMMY_MAP(GFX_DIDT_XVMIN), \ __SMU_DUMMY_MAP(FAN_ABNORMAL), \ - __SMU_DUMMY_MAP(PIT), + __SMU_DUMMY_MAP(PIT), \ + __SMU_DUMMY_MAP(HROM_EN), #undef __SMU_DUMMY_MAP #define __SMU_DUMMY_MAP(feature) SMU_FEATURE_##feature##_BIT diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index 24aaef1494a46..0ce8cff27bf94 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -82,6 +82,7 @@ const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[SMU_FEATURE_COUNT] = SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_MPIOCLK_BIT, FEATURE_DS_MPIOCLK), SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_MP0CLK_BIT, FEATURE_DS_MP0CLK), SMU_13_0_12_FEA_MAP(SMU_FEATURE_PIT_BIT, FEATURE_PIT), + SMU_13_0_12_FEA_MAP(SMU_FEATURE_HROM_EN_BIT, FEATURE_HROM_EN), }; const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[SMU_MSG_MAX_COUNT] = { @@ -1044,10 +1045,16 @@ static const struct ras_eeprom_smu_funcs smu_v13_0_12_eeprom_smu_funcs = { static void smu_v13_0_12_ras_smu_feature_flags(struct amdgpu_device *adev, uint64_t *flags) { + struct smu_context *smu = adev->powerplay.pp_handle; + if (!flags) return; *flags = 0ULL; + + if (smu_v13_0_6_cap_supported(smu, SMU_CAP(RAS_EEPROM))) + *flags |= RAS_SMU_FEATURE_BIT__RAS_EEPROM; + } const struct ras_smu_drv smu_v13_0_12_ras_smu_drv = { diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index f341942303c59..61dd49f2a756d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -4084,6 +4084,9 @@ static int smu_v13_0_6_get_ras_smu_drv(struct smu_context *smu, const struct ras if (amdgpu_sriov_vf(smu->adev)) return -EOPNOTSUPP; + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_HROM_EN_BIT)) + smu_v13_0_6_cap_set(smu, SMU_CAP(RAS_EEPROM)); + switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) { case IP_VERSION(13, 0, 12): *ras_smu_drv = &smu_v13_0_12_ras_smu_drv; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h index ecec7af8a64f9..367102cdbf093 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h @@ -72,6 +72,7 @@ enum smu_v13_0_6_caps { SMU_CAP(PLDM_VERSION), SMU_CAP(TEMP_METRICS), SMU_CAP(NPM_METRICS), + SMU_CAP(RAS_EEPROM), SMU_CAP(ALL), }; From c59e572d2fca3d315cd6852bc5b1f322e43db424 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Fri, 31 Oct 2025 13:41:36 +0800 Subject: [PATCH 2488/2653] drm/amdgpu: initialize max record count after table reset initialize max record count and record offset after table reset Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 3c646d9dad778..d7e2a81bc2743 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -459,6 +459,9 @@ int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) hdr->tbl_size = RAS_TABLE_HEADER_SIZE + RAS_TABLE_V2_1_INFO_SIZE; rai->rma_status = GPU_HEALTH_USABLE; + + control->ras_record_offset = RAS_RECORD_START_V2_1; + control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; /** * GPU health represented as a percentage. * 0 means worst health, 100 means fully health. @@ -469,6 +472,9 @@ int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) } else { hdr->first_rec_offset = RAS_RECORD_START; hdr->tbl_size = RAS_TABLE_HEADER_SIZE; + + control->ras_record_offset = RAS_RECORD_START; + control->ras_max_record_count = RAS_MAX_RECORD_COUNT; } csum = __calc_hdr_byte_sum(control); From 792c408b15ab541c18b846633bf046a400599994 Mon Sep 17 00:00:00 2001 From: "David (Ming Qiang) Wu" Date: Tue, 28 Oct 2025 18:42:05 -0400 Subject: [PATCH 2489/2653] drm/amdgpu/userq: need to unref bo unref bo after amdgpu_bo_reserve() failure as it has called amdgpu_bo_ref() already Reviewed-by: Alex Deucher Signed-off-by: David (Ming Qiang) Wu --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index 10c07ae876c5d..2018dd85fdfbe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -449,6 +449,7 @@ static int amdgpu_userq_fence_read_wptr(struct amdgpu_usermode_queue *queue, amdgpu_bo_unreserve(queue->vm->root.bo); r = amdgpu_bo_reserve(bo, true); if (r) { + amdgpu_bo_unref(&bo); DRM_ERROR("Failed to reserve userqueue wptr bo"); return r; } From 2fc71cae3fca4c87eca7a53796c2e04336668d03 Mon Sep 17 00:00:00 2001 From: Ahmad Rehman Date: Tue, 4 Nov 2025 12:23:09 -0500 Subject: [PATCH 2490/2653] amdkfd: Do nto wait for queue op response during reset This patch adds the condition to not wait for the queue response for unmap, if the gpu is in reset. Signed-off-by: Ahmad Rehman Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 849297aec8975..9776c9deeca5f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -2149,7 +2149,8 @@ int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm, while (*fence_addr != fence_value) { /* Fatal err detected, this response won't come */ - if (amdgpu_amdkfd_is_fed(dqm->dev->adev)) + if (amdgpu_amdkfd_is_fed(dqm->dev->adev) || + amdgpu_in_reset(dqm->dev->adev)) return -EIO; if (time_after(jiffies, end_jiffies)) { From e91095037fe3f06f15c5e1645bfc2c5508ab7e71 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Tue, 4 Nov 2025 20:07:58 +0800 Subject: [PATCH 2491/2653] drm/amd/ras: ras supports i2c eeprom for mp1 v13_0_12 ras supports i2c eeprom for mp1 v13_0_12. Signed-off-by: YiPeng Chai Acked-by: Alex Deucher Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.c index 1bb7b7001ec7e..3ed3ff42b7e14 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_eeprom_i2c.c @@ -85,6 +85,7 @@ static int ras_eeprom_i2c_config(struct ras_core_context *ras_core) case IP_VERSION(13, 0, 5): case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 10): + case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): control->i2c_address = EEPROM_I2C_MADDR_4; return 0; From 4fd5529f6d0d6c131b8393c53a1a86652c59e552 Mon Sep 17 00:00:00 2001 From: Samuel Zhang Date: Wed, 5 Nov 2025 03:04:08 +0000 Subject: [PATCH 2492/2653] drm/amdgpu: fix gpu page fault after hibernation on PF passthrough On PF passthrough environment, after hibernate and then resume, coralgemm will cause gpu page fault. Mode1 reset happens during hibernate, but partition mode is not restored on resume, register mmCP_HYP_XCP_CTL and mmCP_PSP_XCP_CTL is not right after resume. When CP access the MQD BO, wrong stride size is used, this will cause out of bound access on the MQD BO, resulting page fault. The fix is to ensure gfx_v9_4_3_switch_compute_partition() is called when resume from a hibernation. KFD resume is called separately during a reset recovery or resume from suspend sequence. Hence it's not required to be called as part of partition switch. Signed-off-by: Samuel Zhang Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 3 ++- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c index 811124ff88a88..f9e2edf5260bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c +++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c @@ -407,7 +407,8 @@ static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, return -EINVAL; } - if (adev->kfd.init_complete && !amdgpu_in_reset(adev)) + if (adev->kfd.init_complete && !amdgpu_in_reset(adev) && + !adev->in_suspend) flags |= AMDGPU_XCP_OPS_KFD; if (flags & AMDGPU_XCP_OPS_KFD) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index de2212cfa7177..25bedf39390ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2315,7 +2315,9 @@ static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); } else { - if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, + if (adev->in_suspend) + amdgpu_xcp_restore_partition_mode(adev->xcp_mgr); + else if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, AMDGPU_XCP_FL_NONE) == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) r = amdgpu_xcp_switch_partition_mode( From 7bc5cd5da46dcda2ff2c1a401cd55026be11d81a Mon Sep 17 00:00:00 2001 From: Ahmad Rehman Date: Tue, 4 Nov 2025 12:23:09 -0500 Subject: [PATCH 2493/2653] amdkfd: Do nto wait for queue op response during reset This patch adds the condition to not wait for the queue response for unmap, if the gpu is in reset. Signed-off-by: Ahmad Rehman Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 90a60f16d8080..d3f84e6f92f52 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -2146,7 +2146,8 @@ int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm, while (*fence_addr != fence_value) { /* Fatal err detected, this response won't come */ - if (amdgpu_amdkfd_is_fed(dqm->dev->adev)) + if (amdgpu_amdkfd_is_fed(dqm->dev->adev) || + amdgpu_in_reset(dqm->dev->adev)) return -EIO; if (time_after(jiffies, end_jiffies)) { From 879cfcc77c45231164f451462c3bf47089296437 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Wed, 5 Nov 2025 17:25:37 +0800 Subject: [PATCH 2494/2653] drm/amd/ras: Fix the issue of incorrect function call When amdgpu_device_health_check fails, amdgpu_ras_pre_reset will not be called and therefore amdgpu_ras_post_reset cannot be called either. Signed-off-by: YiPeng Chai Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 7ee3dabc0cf58..eca11fbc637ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6751,8 +6751,8 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, amdgpu_device_gpu_resume(adev, &device_list, need_emergency_restart); reset_unlock: amdgpu_device_recovery_put_reset_lock(adev, &device_list); -end_reset: amdgpu_ras_post_reset(adev, &device_list); +end_reset: if (hive) { mutex_unlock(&hive->hive_lock); amdgpu_put_xgmi_hive(hive); From e054a73d974f5300dee451b96d54e56a26af0e89 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Tue, 4 Nov 2025 13:38:02 -0600 Subject: [PATCH 2495/2653] drm/amd: Fix suspend failure with secure display TA commit c760bcda83571 ("drm/amd: Check whether secure display TA loaded successfully") attempted to fix extra messages, but failed to port the cleanup that was in commit 5c6d52ff4b61e ("drm/amd: Don't try to enable secure display TA multiple times") to prevent multiple tries. Add that to the failure handling path even on a quick failure. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4679 Fixes: c760bcda83571 ("drm/amd: Check whether secure display TA loaded successfully") Signed-off-by: Mario Limonciello Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 0ac7fa2794edc..e1de1dc1c940a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -2355,8 +2355,11 @@ static int psp_securedisplay_initialize(struct psp_context *psp) if (!ret && !psp->securedisplay_context.context.resp_status) { psp->securedisplay_context.context.initialized = true; mutex_init(&psp->securedisplay_context.mutex); - } else + } else { + /* don't try again */ + psp->securedisplay_context.context.bin_desc.size_bytes = 0; return ret; + } mutex_lock(&psp->securedisplay_context.mutex); From e5edf0aa72d6916a56814ca49be61c8aeb3d0841 Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Tue, 30 Sep 2025 10:56:00 +0800 Subject: [PATCH 2496/2653] drm/amdgpu: make MCA IPID parse global So we can call it in other blocks. v2: add a new IPID parse interface for umc and we can implement it for each ASIC. Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 2 ++ drivers/gpu/drm/amd/amdgpu/umc_v12_0.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h index ec203f9e5ffab..28dff750c47e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h @@ -113,6 +113,8 @@ struct amdgpu_umc_ras { uint32_t (*get_die_id_from_pa)(struct amdgpu_device *adev, uint64_t mca_addr, uint64_t retired_page); void (*get_retire_flip_bits)(struct amdgpu_device *adev); + void (*mca_ipid_parse)(struct amdgpu_device *adev, uint64_t ipid, + uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid); }; struct amdgpu_umc_funcs { diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c index 8dc32787d6250..0f5b1719fda56 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c @@ -711,6 +711,19 @@ static uint32_t umc_v12_0_get_die_id(struct amdgpu_device *adev, return die; } +static void umc_v12_0_mca_ipid_parse(struct amdgpu_device *adev, uint64_t ipid, + uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid) +{ + if (did) + *did = MCA_IPID_2_DIE_ID(ipid); + if (ch) + *ch = MCA_IPID_2_UMC_CH(ipid); + if (umc_inst) + *umc_inst = MCA_IPID_2_UMC_INST(ipid); + if (sid) + *sid = MCA_IPID_2_SOCKET_ID(ipid); +} + struct amdgpu_umc_ras umc_v12_0_ras = { .ras_block = { .hw_ops = &umc_v12_0_ras_hw_ops, @@ -724,5 +737,6 @@ struct amdgpu_umc_ras umc_v12_0_ras = { .convert_ras_err_addr = umc_v12_0_convert_error_address, .get_die_id_from_pa = umc_v12_0_get_die_id, .get_retire_flip_bits = umc_v12_0_get_retire_flip_bits, + .mca_ipid_parse = umc_v12_0_mca_ipid_parse, }; From 375c01900cd09f9e8c2a85fa94aaefcd7755c419 Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Wed, 23 Jul 2025 19:04:17 +0800 Subject: [PATCH 2497/2653] drm/amdgpu: add ras_eeprom_read_idx interface PMFW will manage RAS eeprom data by itself, add new interface to read eeprom data via PMFW, we can read part of records by setting index. v2: use IPID parse interface. pa is not used and set it to a fixed value. v3: optimize the null pointer check for IPID parse interface. Signed-off-by: Tao Zhou Reviewed-by: Yang Wang Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 51 +++++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h | 4 ++ 2 files changed, 55 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index d7e2a81bc2743..9854238ce7bfa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -970,6 +970,50 @@ static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, return res; } +int amdgpu_ras_eeprom_read_idx(struct amdgpu_ras_eeprom_control *control, + struct eeprom_table_record *record, u32 rec_idx, + const u32 num) +{ + struct amdgpu_device *adev = to_amdgpu_device(control); + uint64_t ts, end_idx; + int i, ret; + u64 mca, ipid; + + if (!amdgpu_ras_smu_eeprom_supported(adev)) + return 0; + + if (!adev->umc.ras || !adev->umc.ras->mca_ipid_parse) + return -EOPNOTSUPP; + + end_idx = rec_idx + num; + for (i = rec_idx; i < end_idx; i++) { + ret = amdgpu_ras_smu_get_badpage_mca_addr(adev, i, &mca); + if (ret) + return ret; + + ret = amdgpu_ras_smu_get_badpage_ipid(adev, i, &ipid); + if (ret) + return ret; + + ret = amdgpu_ras_smu_get_timestamp(adev, i, &ts); + if (ret) + return ret; + + record[i - rec_idx].address = mca; + /* retired_page (pa) is unused now */ + record[i - rec_idx].retired_page = 0x1ULL; + record[i - rec_idx].ts = ts; + record[i - rec_idx].err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE; + record[i - rec_idx].cu = 0; + + adev->umc.ras->mca_ipid_parse(adev, ipid, NULL, + (uint32_t *)&(record[i - rec_idx].mem_channel), + (uint32_t *)&(record[i - rec_idx].mcumc_id), NULL); + } + + return 0; +} + /** * amdgpu_ras_eeprom_read -- read EEPROM * @control: pointer to control structure @@ -991,6 +1035,9 @@ int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, u8 *buf, *pp; u32 g0, g1; + if (amdgpu_ras_smu_eeprom_supported(adev)) + return amdgpu_ras_eeprom_read_idx(control, record, 0, num); + if (!__is_ras_eeprom_supported(adev)) return 0; @@ -1162,6 +1209,10 @@ static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf, int res = -EFAULT; size_t data_len; + /* pmfw manages eeprom data by itself */ + if (amdgpu_ras_smu_eeprom_supported(adev)) + return 0; + mutex_lock(&control->ras_tbl_mutex); /* We want *pos - data_len > 0, which means there's diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h index cfbd402ddea2f..e881007f715b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h @@ -186,6 +186,10 @@ int amdgpu_ras_smu_get_badpage_ipid(struct amdgpu_device *adev, int amdgpu_ras_smu_erase_ras_table(struct amdgpu_device *adev, uint32_t *result); +int amdgpu_ras_eeprom_read_idx(struct amdgpu_ras_eeprom_control *control, + struct eeprom_table_record *record, u32 rec_idx, + const u32 num); + extern const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops; extern const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops; From 7d10d9e32b2a7b9b4d7bbafed2df1e51bf45b053 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 3 Nov 2025 16:21:50 +0530 Subject: [PATCH 2498/2653] drm/amdgpu: Fix wait after reset sequence in S3 For a mode-1 reset done at the end of S3 on PSPv11 dGPUs, only check if TOS is unloaded. Fixes: 440cec4ca1c2 ("drm/amdgpu: Wait for bootloader after PSPv11 reset") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4649 Signed-off-by: Lijo Lazar Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 +++++++-- drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 26 ++++++++++++++++++++++++- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index c20f605c470c0..a76444202f712 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2692,9 +2692,14 @@ static int amdgpu_pmops_suspend_noirq(struct device *dev) { struct drm_device *drm_dev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(drm_dev); + int r; - if (amdgpu_acpi_should_gpu_reset(adev)) - return amdgpu_asic_reset(adev); + if (amdgpu_acpi_should_gpu_reset(adev)) { + amdgpu_device_lock_reset_domain(adev->reset_domain); + r = amdgpu_asic_reset(adev); + amdgpu_device_unlock_reset_domain(adev->reset_domain); + return r; + } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c index 64b240b51f1aa..a9be7a5050268 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c @@ -142,13 +142,37 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) return err; } -static int psp_v11_0_wait_for_bootloader(struct psp_context *psp) +static int psp_v11_wait_for_tos_unload(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; + uint32_t sol_reg1, sol_reg2; + int retry_loop; + /* Wait for the TOS to be unloaded */ + for (retry_loop = 0; retry_loop < 20; retry_loop++) { + sol_reg1 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); + usleep_range(1000, 2000); + sol_reg2 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); + if (sol_reg1 == sol_reg2) + return 0; + } + dev_err(adev->dev, "TOS unload failed, C2PMSG_33: %x C2PMSG_81: %x", + RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_33), + RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81)); + + return -ETIME; +} + +static int psp_v11_0_wait_for_bootloader(struct psp_context *psp) +{ + struct amdgpu_device *adev = psp->adev; int ret; int retry_loop; + /* For a reset done at the end of S3, only wait for TOS to be unloaded */ + if (adev->in_s3 && !(adev->flags & AMD_IS_APU) && amdgpu_in_reset(adev)) + return psp_v11_wait_for_tos_unload(psp); + for (retry_loop = 0; retry_loop < 20; retry_loop++) { /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ From a71bad7efbd4348301d0122bc9f90525f887a6ca Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Thu, 24 Jul 2025 15:01:03 +0800 Subject: [PATCH 2499/2653] drm/amdgpu: support to load RAS bad pages from PMFW PMFW manages eeprom bad page records, update bad page loading accrodingly. Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 3e8d752612fcd..e71dbd6228c22 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3172,8 +3172,12 @@ static int __amdgpu_ras_convert_rec_from_rom(struct amdgpu_device *adev, int i = 0; enum amdgpu_memory_partition save_nps; - save_nps = (bps->retired_page >> UMC_NPS_SHIFT) & UMC_NPS_MASK; - bps->retired_page &= ~(UMC_NPS_MASK << UMC_NPS_SHIFT); + if (!amdgpu_ras_smu_eeprom_supported(adev)) { + save_nps = (bps->retired_page >> UMC_NPS_SHIFT) & UMC_NPS_MASK; + bps->retired_page &= ~(UMC_NPS_MASK << UMC_NPS_SHIFT); + } else { + save_nps = nps; + } if (save_nps == nps) { if (amdgpu_umc_pages_in_a_row(adev, err_data, @@ -3239,7 +3243,8 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, if (from_rom) { /* there is no pa recs in V3, so skip pa recs processing */ - if (control->tbl_hdr.version < RAS_TABLE_VER_V3) { + if ((control->tbl_hdr.version < RAS_TABLE_VER_V3) && + !amdgpu_ras_smu_eeprom_supported(adev)) { for (i = 0; i < pages; i++) { if (control->ras_num_recs - i >= adev->umc.retire_unit) { if ((bps[i].address == bps[i + 1].address) && @@ -3370,7 +3375,8 @@ static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) /*In V3, there is no pa recs, and some cases(when address==0) may be parsed as pa recs, so add verion check to avoid it. */ - if (control->tbl_hdr.version < RAS_TABLE_VER_V3) { + if ((control->tbl_hdr.version < RAS_TABLE_VER_V3) && + !amdgpu_ras_smu_eeprom_supported(adev)) { for (i = 0; i < control->ras_num_recs; i++) { if ((control->ras_num_recs - i) >= adev->umc.retire_unit) { if ((bps[i].address == bps[i + 1].address) && From ba60bbb85ff45f546a731f9ea37dd0514d71627a Mon Sep 17 00:00:00 2001 From: Wayne Lin Date: Wed, 5 Nov 2025 10:36:31 +0800 Subject: [PATCH 2500/2653] drm/amd/display: Enable mst when it's detected but yet to be initialized [Why] drm_dp_mst_topology_queue_probe() is used under the assumption that mst is already initialized. If we connect system with SST first then switch to the mst branch during suspend, we will fail probing topology by calling the wrong API since the mst manager is yet to be initialized. [How] At dm_resume(), once it's detected as mst branc connected, check if the mst is initialized already. If not, call dm_helpers_dp_mst_start_top_mgr() instead to initialize mst V2: Adjust the commit msg a bit Fixes: bc068194f548 ("drm/amd/display: Don't write DP_MSTM_CTRL after LT") Cc: Fangzhi Zuo Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Tom Chung Signed-off-by: Wayne Lin --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7ca40ad8eb9f2..9d549526fd469 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3665,6 +3665,7 @@ static int dm_resume(struct amdgpu_ip_block *ip_block) /* Do mst topology probing after resuming cached state*/ drm_connector_list_iter_begin(ddev, &iter); drm_for_each_connector_iter(connector, &iter) { + bool init = false; if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -3674,7 +3675,14 @@ static int dm_resume(struct amdgpu_ip_block *ip_block) aconnector->mst_root) continue; - drm_dp_mst_topology_queue_probe(&aconnector->mst_mgr); + scoped_guard(mutex, &aconnector->mst_mgr.lock) { + init = !aconnector->mst_mgr.mst_primary; + } + if (init) + dm_helpers_dp_mst_start_top_mgr(aconnector->dc_link->ctx, + aconnector->dc_link, false); + else + drm_dp_mst_topology_queue_probe(&aconnector->mst_mgr); } drm_connector_list_iter_end(&iter); From d4b11160207e6cda2f83edf29d98bd8585d725bd Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Mon, 8 Sep 2025 20:39:49 +0800 Subject: [PATCH 2501/2653] drm/amdgpu: skip writing eeprom when PMFW manages RAS data Only update bad page number in legacy eeprom write path. v2: add null pointer check for con. Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 20 ++++++++++++++++++- .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h | 3 +++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 9854238ce7bfa..670c0dedf4e92 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -871,6 +871,18 @@ amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) return res; } +int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *control) +{ + struct amdgpu_device *adev = to_amdgpu_device(control); + + if (!amdgpu_ras_smu_eeprom_supported(adev)) + return 0; + + control->ras_num_recs_old = control->ras_num_recs; + return amdgpu_ras_smu_get_badpage_count(adev, + &(control->ras_num_recs), 12); +} + /** * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table * @control: pointer to control structure @@ -889,12 +901,18 @@ int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, const u32 num) { struct amdgpu_device *adev = to_amdgpu_device(control); + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); int res, i; uint64_t nps = AMDGPU_NPS1_PARTITION_MODE; - if (!__is_ras_eeprom_supported(adev)) + if (!__is_ras_eeprom_supported(adev) || !con) return 0; + if (amdgpu_ras_smu_eeprom_supported(adev)) { + control->ras_num_bad_pages = con->bad_page_num; + return 0; + } + if (num == 0) { dev_err(adev->dev, "will not append 0 records\n"); return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h index e881007f715b0..2e5d63957e714 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h @@ -82,6 +82,7 @@ struct amdgpu_ras_eeprom_control { /* Number of records in the table. */ u32 ras_num_recs; + u32 ras_num_recs_old; /* the bad page number is ras_num_recs or * ras_num_recs * umc.retire_unit @@ -190,6 +191,8 @@ int amdgpu_ras_eeprom_read_idx(struct amdgpu_ras_eeprom_control *control, struct eeprom_table_record *record, u32 rec_idx, const u32 num); +int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *control); + extern const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops; extern const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops; From 3f80ff04825807d8dfcdf7f9b50eb8554d29925d Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Thu, 6 Nov 2025 14:11:45 +0800 Subject: [PATCH 2502/2653] drm/amd/pm: Update default power1_cap Update default power1_cap to max limit for smu_v13_0_6 and smu_v13_0_12 Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Reviewed-by: Yang Wang --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 61dd49f2a756d..188b968f4d25c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -2031,7 +2031,7 @@ static int smu_v13_0_6_get_power_limit(struct smu_context *smu, if (current_power_limit) *current_power_limit = power_limit; if (default_power_limit) - *default_power_limit = power_limit; + *default_power_limit = pptable->MaxSocketPowerLimit; if (max_power_limit) { *max_power_limit = pptable->MaxSocketPowerLimit; From 3f669c7b5aeb79aa02837242396be1c3750a95f3 Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Fri, 25 Jul 2025 10:47:35 +0800 Subject: [PATCH 2503/2653] drm/amdgpu: load RAS bad page from PMFW in page retirement In legacy way, bad page is queried from MCA registers, switch to getting it from PMFW when PMFW manages eeprom data. Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 137 ++++++++++++++---------- 2 files changed, 90 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index e71dbd6228c22..effcf8a7e5441 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3314,7 +3314,13 @@ int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev, mutex_lock(&con->recovery_lock); control = &con->eeprom_control; data = con->eh_data; - unit_num = data->count / adev->umc.retire_unit - control->ras_num_recs; + if (amdgpu_ras_smu_eeprom_supported(adev)) + unit_num = control->ras_num_recs - + control->ras_num_recs_old; + else + unit_num = data->count / adev->umc.retire_unit - + control->ras_num_recs; + save_count = con->bad_page_num - control->ras_num_bad_pages; mutex_unlock(&con->recovery_lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c index 983a428eddd4a..f540ee37a4acc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c @@ -96,67 +96,96 @@ void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev, { struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + struct amdgpu_ras_eeprom_control *control = &con->eeprom_control; unsigned int error_query_mode; int ret = 0; unsigned long err_count; amdgpu_ras_get_error_query_mode(adev, &error_query_mode); + err_data->err_addr = + kcalloc(adev->umc.max_ras_err_cnt_per_query, + sizeof(struct eeprom_table_record), GFP_KERNEL); + + /* still call query_ras_error_address to clear error status + * even NOMEM error is encountered + */ + if (!err_data->err_addr) + dev_warn(adev->dev, + "Failed to alloc memory for umc error address record!\n"); + else + err_data->err_addr_len = adev->umc.max_ras_err_cnt_per_query; + mutex_lock(&con->page_retirement_lock); - ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(con->umc_ecc)); - if (ret == -EOPNOTSUPP && - error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) { - if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && - adev->umc.ras->ras_block.hw_ops->query_ras_error_count) - adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status); - - if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && - adev->umc.ras->ras_block.hw_ops->query_ras_error_address && - adev->umc.max_ras_err_cnt_per_query) { - err_data->err_addr = - kcalloc(adev->umc.max_ras_err_cnt_per_query, - sizeof(struct eeprom_table_record), GFP_KERNEL); - - /* still call query_ras_error_address to clear error status - * even NOMEM error is encountered - */ - if(!err_data->err_addr) - dev_warn(adev->dev, "Failed to alloc memory for " - "umc error address record!\n"); - else - err_data->err_addr_len = adev->umc.max_ras_err_cnt_per_query; - - /* umc query_ras_error_address is also responsible for clearing - * error status - */ - adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, ras_error_status); + if (!amdgpu_ras_smu_eeprom_supported(adev)) { + ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(con->umc_ecc)); + if (ret == -EOPNOTSUPP && + error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) { + if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && + adev->umc.ras->ras_block.hw_ops->query_ras_error_count) + adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, + ras_error_status); + + if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && + adev->umc.ras->ras_block.hw_ops->query_ras_error_address && + adev->umc.max_ras_err_cnt_per_query) { + err_data->err_addr = + kcalloc(adev->umc.max_ras_err_cnt_per_query, + sizeof(struct eeprom_table_record), GFP_KERNEL); + + /* still call query_ras_error_address to clear error status + * even NOMEM error is encountered + */ + if (!err_data->err_addr) + dev_warn(adev->dev, + "Failed to alloc memory for umc error address record!\n"); + else + err_data->err_addr_len = + adev->umc.max_ras_err_cnt_per_query; + + /* umc query_ras_error_address is also responsible for clearing + * error status + */ + adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, + ras_error_status); + } + } else if (error_query_mode == AMDGPU_RAS_FIRMWARE_ERROR_QUERY || + (!ret && error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY)) { + if (adev->umc.ras && + adev->umc.ras->ecc_info_query_ras_error_count) + adev->umc.ras->ecc_info_query_ras_error_count(adev, + ras_error_status); + + if (adev->umc.ras && + adev->umc.ras->ecc_info_query_ras_error_address && + adev->umc.max_ras_err_cnt_per_query) { + err_data->err_addr = + kcalloc(adev->umc.max_ras_err_cnt_per_query, + sizeof(struct eeprom_table_record), GFP_KERNEL); + + /* still call query_ras_error_address to clear error status + * even NOMEM error is encountered + */ + if (!err_data->err_addr) + dev_warn(adev->dev, + "Failed to alloc memory for umc error address record!\n"); + else + err_data->err_addr_len = + adev->umc.max_ras_err_cnt_per_query; + + /* umc query_ras_error_address is also responsible for clearing + * error status + */ + adev->umc.ras->ecc_info_query_ras_error_address(adev, + ras_error_status); + } } - } else if (error_query_mode == AMDGPU_RAS_FIRMWARE_ERROR_QUERY || - (!ret && error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY)) { - if (adev->umc.ras && - adev->umc.ras->ecc_info_query_ras_error_count) - adev->umc.ras->ecc_info_query_ras_error_count(adev, ras_error_status); - - if (adev->umc.ras && - adev->umc.ras->ecc_info_query_ras_error_address && - adev->umc.max_ras_err_cnt_per_query) { - err_data->err_addr = - kcalloc(adev->umc.max_ras_err_cnt_per_query, - sizeof(struct eeprom_table_record), GFP_KERNEL); - - /* still call query_ras_error_address to clear error status - * even NOMEM error is encountered - */ - if(!err_data->err_addr) - dev_warn(adev->dev, "Failed to alloc memory for " - "umc error address record!\n"); - else - err_data->err_addr_len = adev->umc.max_ras_err_cnt_per_query; - - /* umc query_ras_error_address is also responsible for clearing - * error status - */ - adev->umc.ras->ecc_info_query_ras_error_address(adev, ras_error_status); + } else { + if (!amdgpu_ras_eeprom_update_record_num(control)) { + err_data->err_addr_cnt = err_data->de_count = + control->ras_num_recs - control->ras_num_recs_old; + amdgpu_ras_eeprom_read_idx(control, err_data->err_addr, + control->ras_num_recs_old, err_data->de_count); } } @@ -166,7 +195,7 @@ void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev, if ((amdgpu_bad_page_threshold != 0) && err_data->err_addr_cnt) { amdgpu_ras_add_bad_pages(adev, err_data->err_addr, - err_data->err_addr_cnt, false); + err_data->err_addr_cnt, amdgpu_ras_smu_eeprom_supported(adev)); amdgpu_ras_save_bad_pages(adev, &err_count); amdgpu_dpm_send_hbm_bad_pages_num(adev, From 3717487c21cc4a7f01b5a4901c733c678908c161 Mon Sep 17 00:00:00 2001 From: Wenjing Liu Date: Thu, 6 Nov 2025 13:49:18 +0800 Subject: [PATCH 2504/2653] drm/amd/display: add macros to simplify code [Why & How] Adding macros to simplify the process of adding new error codes. Currently, to add an error code, the developer needs to add both the enum and the string translation. This is error prone and can lead to inconsistencies. The refactor adds a macro to automatically add the string translation based on the enum. Reviewed-by: Aric Cyr Signed-off-by: Wenjing Liu Signed-off-by: Ray Wu Tested-by: Daniel Wheeler --- .../drm/amd/display/modules/hdcp/hdcp_log.c | 125 +---------------- .../drm/amd/display/modules/inc/mod_hdcp.h | 126 +++++++++--------- 2 files changed, 68 insertions(+), 183 deletions(-) diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c index ac44ee1532fda..409a7d0e70fab 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c @@ -125,131 +125,12 @@ void mod_hdcp_log_ddc_trace(struct mod_hdcp *hdcp) } } +#define CASE_FORMAT(entry) case entry: return #entry; + char *mod_hdcp_status_to_str(int32_t status) { switch (status) { - case MOD_HDCP_STATUS_SUCCESS: - return "MOD_HDCP_STATUS_SUCCESS"; - case MOD_HDCP_STATUS_FAILURE: - return "MOD_HDCP_STATUS_FAILURE"; - case MOD_HDCP_STATUS_RESET_NEEDED: - return "MOD_HDCP_STATUS_RESET_NEEDED"; - case MOD_HDCP_STATUS_DISPLAY_OUT_OF_BOUND: - return "MOD_HDCP_STATUS_DISPLAY_OUT_OF_BOUND"; - case MOD_HDCP_STATUS_DISPLAY_NOT_FOUND: - return "MOD_HDCP_STATUS_DISPLAY_NOT_FOUND"; - case MOD_HDCP_STATUS_INVALID_STATE: - return "MOD_HDCP_STATUS_INVALID_STATE"; - case MOD_HDCP_STATUS_NOT_IMPLEMENTED: - return "MOD_HDCP_STATUS_NOT_IMPLEMENTED"; - case MOD_HDCP_STATUS_INTERNAL_POLICY_FAILURE: - return "MOD_HDCP_STATUS_INTERNAL_POLICY_FAILURE"; - case MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE: - return "MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE"; - case MOD_HDCP_STATUS_CREATE_PSP_SERVICE_FAILURE: - return "MOD_HDCP_STATUS_CREATE_PSP_SERVICE_FAILURE"; - case MOD_HDCP_STATUS_DESTROY_PSP_SERVICE_FAILURE: - return "MOD_HDCP_STATUS_DESTROY_PSP_SERVICE_FAILURE"; - case MOD_HDCP_STATUS_HDCP1_CREATE_SESSION_FAILURE: - return "MOD_HDCP_STATUS_HDCP1_CREATE_SESSION_FAILURE"; - case MOD_HDCP_STATUS_HDCP1_DESTROY_SESSION_FAILURE: - return "MOD_HDCP_STATUS_HDCP1_DESTROY_SESSION_FAILURE"; - case MOD_HDCP_STATUS_HDCP1_VALIDATE_ENCRYPTION_FAILURE: - return "MOD_HDCP_STATUS_HDCP1_VALIDATE_ENCRYPTION_FAILURE"; - case MOD_HDCP_STATUS_HDCP1_NOT_HDCP_REPEATER: - return "MOD_HDCP_STATUS_HDCP1_NOT_HDCP_REPEATER"; - case MOD_HDCP_STATUS_HDCP1_NOT_CAPABLE: - return "MOD_HDCP_STATUS_HDCP1_NOT_CAPABLE"; - case MOD_HDCP_STATUS_HDCP1_R0_PRIME_PENDING: - return "MOD_HDCP_STATUS_HDCP1_R0_PRIME_PENDING"; - case MOD_HDCP_STATUS_HDCP1_VALIDATE_RX_FAILURE: - return "MOD_HDCP_STATUS_HDCP1_VALIDATE_RX_FAILURE"; - case MOD_HDCP_STATUS_HDCP1_BKSV_REVOKED: - return "MOD_HDCP_STATUS_HDCP1_BKSV_REVOKED"; - case MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY: - return "MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY"; - case MOD_HDCP_STATUS_HDCP1_VALIDATE_KSV_LIST_FAILURE: - return "MOD_HDCP_STATUS_HDCP1_VALIDATE_KSV_LIST_FAILURE"; - case MOD_HDCP_STATUS_HDCP1_KSV_LIST_REVOKED: - return "MOD_HDCP_STATUS_HDCP1_KSV_LIST_REVOKED"; - case MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION_FAILURE: - return "MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION_FAILURE"; - case MOD_HDCP_STATUS_HDCP1_ENABLE_STREAM_ENCRYPTION_FAILURE: - return "MOD_HDCP_STATUS_HDCP1_ENABLE_STREAM_ENCRYPTION_FAILURE"; - case MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE: - return "MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE"; - case MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE: - return "MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE"; - case MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE: - return "MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE"; - case MOD_HDCP_STATUS_HDCP1_LINK_INTEGRITY_FAILURE: - return "MOD_HDCP_STATUS_HDCP1_LINK_INTEGRITY_FAILURE"; - case MOD_HDCP_STATUS_HDCP1_REAUTH_REQUEST_ISSUED: - return "MOD_HDCP_STATUS_HDCP1_REAUTH_REQUEST_ISSUED"; - case MOD_HDCP_STATUS_HDCP1_LINK_MAINTENANCE_FAILURE: - return "MOD_HDCP_STATUS_HDCP1_LINK_MAINTENANCE_FAILURE"; - case MOD_HDCP_STATUS_HDCP1_INVALID_BKSV: - return "MOD_HDCP_STATUS_HDCP1_INVALID_BKSV"; - case MOD_HDCP_STATUS_DDC_FAILURE: - return "MOD_HDCP_STATUS_DDC_FAILURE"; - case MOD_HDCP_STATUS_INVALID_OPERATION: - return "MOD_HDCP_STATUS_INVALID_OPERATION"; - case MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE: - return "MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE"; - case MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE: - return "MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE"; - case MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE: - return "MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE"; - case MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE: - return "MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE"; - case MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING: - return "MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING"; - case MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING: - return "MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING"; - case MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING: - return "MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING"; - case MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE: - return "MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE"; - case MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED: - return "MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED"; - case MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE: - return "MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE"; - case MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE: - return "MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE"; - case MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE: - return "MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE"; - case MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING: - return "MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING"; - case MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE: - return "MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE"; - case MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE: - return "MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE"; - case MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE: - return "MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE"; - case MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE: - return "MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE"; - case MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_REVOKED: - return "MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_REVOKED"; - case MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY: - return "MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY"; - case MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION_FAILURE: - return "MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION_FAILURE"; - case MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING: - return "MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING"; - case MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE: - return "MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE"; - case MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE: - return "MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE"; - case MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST: - return "MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST"; - case MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE: - return "MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE"; - case MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE: - return "MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE"; - case MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE: - return "MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE"; - case MOD_HDCP_STATUS_HDCP2_LOCALITY_COMBO_READ_FAILURE: - return "MOD_HDCP_STATUS_HDCP2_LOCALITY_COMBO_READ_FAILURE"; + MOD_HDCP_STATUS_LIST(CASE_FORMAT) default: return "MOD_HDCP_STATUS_UNKNOWN"; } diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h index 264348989e9bc..8354672254589 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h @@ -35,70 +35,74 @@ struct mod_hdcp; #define MAX_NUM_OF_DISPLAYS 6 #define MAX_NUM_OF_ATTEMPTS 4 #define MAX_NUM_OF_ERROR_TRACE 10 +#define MOD_HDCP_STATUS_LIST(FORMAT) \ + FORMAT(MOD_HDCP_STATUS_SUCCESS) \ + FORMAT(MOD_HDCP_STATUS_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_RESET_NEEDED) \ + FORMAT(MOD_HDCP_STATUS_DISPLAY_OUT_OF_BOUND) \ + FORMAT(MOD_HDCP_STATUS_DISPLAY_NOT_FOUND) \ + FORMAT(MOD_HDCP_STATUS_INVALID_STATE) \ + FORMAT(MOD_HDCP_STATUS_NOT_IMPLEMENTED) \ + FORMAT(MOD_HDCP_STATUS_INTERNAL_POLICY_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_CREATE_PSP_SERVICE_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_DESTROY_PSP_SERVICE_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_CREATE_SESSION_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_DESTROY_SESSION_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_VALIDATE_ENCRYPTION_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_NOT_HDCP_REPEATER) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_NOT_CAPABLE) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_R0_PRIME_PENDING) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_VALIDATE_RX_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_BKSV_REVOKED) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_VALIDATE_KSV_LIST_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_KSV_LIST_REVOKED) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_ENABLE_STREAM_ENCRYPTION_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_LINK_INTEGRITY_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_REAUTH_REQUEST_ISSUED) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_LINK_MAINTENANCE_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP1_INVALID_BKSV) \ + FORMAT(MOD_HDCP_STATUS_DDC_FAILURE) /* TODO: specific errors */ \ + FORMAT(MOD_HDCP_STATUS_INVALID_OPERATION) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_REVOKED) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE) \ + FORMAT(MOD_HDCP_STATUS_HDCP2_LOCALITY_COMBO_READ_FAILURE) + +#define ENUM_FORMAT(entry) entry, /* detailed return status */ enum mod_hdcp_status { - MOD_HDCP_STATUS_SUCCESS = 0, - MOD_HDCP_STATUS_FAILURE, - MOD_HDCP_STATUS_RESET_NEEDED, - MOD_HDCP_STATUS_DISPLAY_OUT_OF_BOUND, - MOD_HDCP_STATUS_DISPLAY_NOT_FOUND, - MOD_HDCP_STATUS_INVALID_STATE, - MOD_HDCP_STATUS_NOT_IMPLEMENTED, - MOD_HDCP_STATUS_INTERNAL_POLICY_FAILURE, - MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE, - MOD_HDCP_STATUS_CREATE_PSP_SERVICE_FAILURE, - MOD_HDCP_STATUS_DESTROY_PSP_SERVICE_FAILURE, - MOD_HDCP_STATUS_HDCP1_CREATE_SESSION_FAILURE, - MOD_HDCP_STATUS_HDCP1_DESTROY_SESSION_FAILURE, - MOD_HDCP_STATUS_HDCP1_VALIDATE_ENCRYPTION_FAILURE, - MOD_HDCP_STATUS_HDCP1_NOT_HDCP_REPEATER, - MOD_HDCP_STATUS_HDCP1_NOT_CAPABLE, - MOD_HDCP_STATUS_HDCP1_R0_PRIME_PENDING, - MOD_HDCP_STATUS_HDCP1_VALIDATE_RX_FAILURE, - MOD_HDCP_STATUS_HDCP1_BKSV_REVOKED, - MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY, - MOD_HDCP_STATUS_HDCP1_VALIDATE_KSV_LIST_FAILURE, - MOD_HDCP_STATUS_HDCP1_KSV_LIST_REVOKED, - MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION_FAILURE, - MOD_HDCP_STATUS_HDCP1_ENABLE_STREAM_ENCRYPTION_FAILURE, - MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE, - MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE, - MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE, - MOD_HDCP_STATUS_HDCP1_LINK_INTEGRITY_FAILURE, - MOD_HDCP_STATUS_HDCP1_REAUTH_REQUEST_ISSUED, - MOD_HDCP_STATUS_HDCP1_LINK_MAINTENANCE_FAILURE, - MOD_HDCP_STATUS_HDCP1_INVALID_BKSV, - MOD_HDCP_STATUS_DDC_FAILURE, /* TODO: specific errors */ - MOD_HDCP_STATUS_INVALID_OPERATION, - MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE, - MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE, - MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE, - MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE, - MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING, - MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING, - MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING, - MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE, - MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED, - MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE, - MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE, - MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE, - MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING, - MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE, - MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE, - MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE, - MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY, - MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE, - MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_REVOKED, - MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION_FAILURE, - MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING, - MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE, - MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE, - MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST, - MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE, - MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE, - MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE, - MOD_HDCP_STATUS_HDCP2_LOCALITY_COMBO_READ_FAILURE, + MOD_HDCP_STATUS_LIST(ENUM_FORMAT) }; struct mod_hdcp_displayport { From fbdd9d67bb820acd2e78bff59ace3be08d488dd2 Mon Sep 17 00:00:00 2001 From: "Mario Limonciello (AMD)" Date: Thu, 6 Nov 2025 14:55:27 -0600 Subject: [PATCH 2505/2653] drm/amd: Clarify that amdgpu.audio only works for non-DC The comment already explains it bu the module parameter help text doesn't. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4684 Signed-off-by: Mario Limonciello (AMD) Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index a76444202f712..b406163a106a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -314,7 +314,7 @@ module_param_named(moverate, amdgpu_moverate, int, 0600); * DOC: audio (int) * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. */ -MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); +MODULE_PARM_DESC(audio, "HDMI/DP Audio enable for non DC displays (-1 = auto, 0 = disable, 1 = enable)"); module_param_named(audio, amdgpu_audio, int, 0444); /** From 3130715ccee272042aff277d7356f34d9871a317 Mon Sep 17 00:00:00 2001 From: Vitaly Prosyak Date: Thu, 6 Nov 2025 12:35:53 -0500 Subject: [PATCH 2506/2653] drm/amdgpu: disable peer-to-peer access for DCC-enabled GC12 VRAM surfaces MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Certain multi-GPU configurations (especially GFX12) may hit data corruption when a DCC-compressed VRAM surface is shared across GPUs using peer-to-peer (P2P) DMA transfers. Such surfaces rely on device-local metadata and cannot be safely accessed through a remote GPU’s page tables. Attempting to import a DCC-enabled surface through P2P leads to incorrect rendering or GPU faults. This change disables P2P for DCC-enabled VRAM buffers that are contiguous and allocated on GFX12+ hardware. In these cases, the importer falls back to the standard system-memory path, avoiding invalid access to compressed surfaces. Future work could consider optional migration (VRAM→System→VRAM) if a performance regression is observed when `attach->peer2peer = false`. Tested on: - Dual RX 9700 XT (Navi4x) setup - GNOME and Wayland compositor scenarios - Confirmed no corruption after disabling P2P under these conditions v2: Remove check TTM_PL_VRAM & TTM_PL_FLAG_CONTIGUOUS. Suggested-by: Christian König Signed-off-by: Vitaly Prosyak Reviewed-by: Christian König Change-Id: I1f713d4168d20e6204cacc4c0be3f5c7a69a24c9 --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index b8008bec65896..f9022c5d74c1e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -261,11 +261,25 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, int r; #ifdef HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER + /* + * Disable peer-to-peer access for DCC-enabled VRAM surfaces on GFX12+. + * Such buffers cannot be safely accessed over P2P due to device-local + * compression metadata. Fallback to system-memory path instead. + * Device supports GFX12 (GC 12.x or newer) + * BO was created with the AMDGPU_GEM_CREATE_GFX12_DCC flag + * + */ + if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(12, 0, 0) && + bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC) { + attach->peer2peer = false; + goto lock_and_update_vm; + } if (!amdgpu_dmabuf_is_xgmi_accessible(attach_adev, bo) && pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0) attach->peer2peer = false; -#endif +lock_and_update_vm: +#endif r = dma_resv_lock(bo->tbo.base.resv, NULL); if (r) return r; From d46c7702962588955d5f331c086a133accecaada Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Wed, 27 Aug 2025 15:48:06 +0800 Subject: [PATCH 2507/2653] drm/amdgpu: get RAS bad page address from MCA address Instead of from physical address. v2: add comment to make the code more readable Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 15 ++++++++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 4 ++-- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index effcf8a7e5441..506cc4936d95f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3028,8 +3028,13 @@ static int amdgpu_ras_mca2pa_by_idx(struct amdgpu_device *adev, addr_in.ma.err_addr = bps->address; addr_in.ma.socket_id = socket; addr_in.ma.ch_inst = bps->mem_channel; - /* tell RAS TA the node instance is not used */ - addr_in.ma.node_inst = TA_RAS_INV_NODE; + if (!amdgpu_ras_smu_eeprom_supported(adev)) { + /* tell RAS TA the node instance is not used */ + addr_in.ma.node_inst = TA_RAS_INV_NODE; + } else { + addr_in.ma.umc_inst = bps->mcumc_id; + addr_in.ma.node_inst = bps->cu; + } if (adev->umc.ras && adev->umc.ras->convert_ras_err_addr) ret = adev->umc.ras->convert_ras_err_addr(adev, err_data, @@ -3176,7 +3181,11 @@ static int __amdgpu_ras_convert_rec_from_rom(struct amdgpu_device *adev, save_nps = (bps->retired_page >> UMC_NPS_SHIFT) & UMC_NPS_MASK; bps->retired_page &= ~(UMC_NPS_MASK << UMC_NPS_SHIFT); } else { - save_nps = nps; + /* if pmfw manages eeprom, save_nps is not stored on eeprom, + * we should always convert mca address into physical address, + * make save_nps different from nps + */ + save_nps = nps + 1; } if (save_nps == nps) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 670c0dedf4e92..ec248ca6ef930 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -1022,9 +1022,9 @@ int amdgpu_ras_eeprom_read_idx(struct amdgpu_ras_eeprom_control *control, record[i - rec_idx].retired_page = 0x1ULL; record[i - rec_idx].ts = ts; record[i - rec_idx].err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE; - record[i - rec_idx].cu = 0; - adev->umc.ras->mca_ipid_parse(adev, ipid, NULL, + adev->umc.ras->mca_ipid_parse(adev, ipid, + (uint32_t *)&(record[i - rec_idx].cu), (uint32_t *)&(record[i - rec_idx].mem_channel), (uint32_t *)&(record[i - rec_idx].mcumc_id), NULL); } From db7eca73c9c96c1de3a257e2442eff035ccc3327 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Thu, 6 Nov 2025 23:47:29 +0800 Subject: [PATCH 2508/2653] drm/amd/pm: Add NULL check for power limit Add NULL check for smu power limit pointer v2: Update error code on failure (Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index f97cb2a27689e..e9fada94c8739 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2907,6 +2907,9 @@ int smu_get_power_limit(void *handle, if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) return -EOPNOTSUPP; + if (!limit) + return -EINVAL; + switch (pp_power_type) { case PP_PWR_TYPE_SUSTAINED: limit_type = SMU_DEFAULT_PPT_LIMIT; From 2b81bc0b20f039034f57c4a4f87843c8b672185d Mon Sep 17 00:00:00 2001 From: Ahmad Rehman Date: Wed, 5 Nov 2025 09:48:08 -0500 Subject: [PATCH 2509/2653] amdkfd: Fixing the clang format This patch fixes the formatting in the patch "amdkfd: Do nto wait for queue op response during reset" Signed-off-by: Ahmad Rehman Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 9776c9deeca5f..025cef14be49b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -2150,7 +2150,7 @@ int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm, while (*fence_addr != fence_value) { /* Fatal err detected, this response won't come */ if (amdgpu_amdkfd_is_fed(dqm->dev->adev) || - amdgpu_in_reset(dqm->dev->adev)) + amdgpu_in_reset(dqm->dev->adev)) return -EIO; if (time_after(jiffies, end_jiffies)) { From 908c797573d6e04b2680edb49a71794cbe40da0c Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Tue, 4 Nov 2025 10:42:45 +0100 Subject: [PATCH 2510/2653] drm/amdgpu: jump to the correct label on failure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drm_sched_entity_init wasn't called yet, so the only thing to do is to release allocated memory. This doesn't fix any bug since entity is zero allocated and drm_sched_entity_fini does nothing in this case. Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Tvrtko Ursulin Acked-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index fc623067e60ad..e3a780ac92522 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -238,7 +238,7 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, r = amdgpu_xcp_select_scheds(adev, hw_ip, hw_prio, fpriv, &num_scheds, &scheds); if (r) - goto cleanup_entity; + goto error_free_entity; } /* disable load balance if the hw engine retains context among dependent jobs */ From d37962a5cbfe4a2433b28018cea857121d1ed614 Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Wed, 27 Aug 2025 19:33:02 +0800 Subject: [PATCH 2511/2653] drm/amdgpu: try for more times if RAS bad page number is not updated RAS info update in PMFW is time cost, wait for it. Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index ec248ca6ef930..01b38a6e198e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -874,13 +874,33 @@ amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *control) { struct amdgpu_device *adev = to_amdgpu_device(control); + int ret, timeout = 1000; if (!amdgpu_ras_smu_eeprom_supported(adev)) return 0; control->ras_num_recs_old = control->ras_num_recs; - return amdgpu_ras_smu_get_badpage_count(adev, + + do { + ret = amdgpu_ras_smu_get_badpage_count(adev, &(control->ras_num_recs), 12); + if (!ret && + (control->ras_num_recs_old == control->ras_num_recs)) { + /* record number update in PMFW needs some time */ + msleep(50); + timeout -= 50; + } else { + break; + } + } while (timeout); + + /* no update of record number is not a real failure, + * don't print warning here + */ + if (!ret && (control->ras_num_recs_old == control->ras_num_recs)) + ret = -EINVAL; + + return ret; } /** From 245891955478e7ba542456623a262e34cc39b6dc Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Fri, 24 Oct 2025 16:09:25 +0800 Subject: [PATCH 2512/2653] drm/amdgpu: fix lock warning in amdgpu_userq_fence_driver_process MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix a potential deadlock caused by inconsistent spinlock usage between interrupt and process contexts in the userq fence driver. The issue occurs when amdgpu_userq_fence_driver_process() is called from both: - Interrupt context: gfx_v11_0_eop_irq() -> amdgpu_userq_fence_driver_process() - Process context: amdgpu_eviction_fence_suspend_worker() -> amdgpu_userq_fence_driver_force_completion() -> amdgpu_userq_fence_driver_process() In interrupt context, the spinlock was acquired without disabling interrupts, leaving it in {IN-HARDIRQ-W} state. When the same lock is acquired in process context, the kernel detects inconsistent locking since the process context acquisition would enable interrupts while holding a lock previously acquired in interrupt context. Kernel log shows: [ 4039.310790] inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage. [ 4039.310804] kworker/7:2/409 [HC0[0]:SC0[0]:HE1:SE1] takes: [ 4039.310818] ffff9284e1bed000 (&fence_drv->fence_list_lock){?...}-{3:3}, [ 4039.310993] {IN-HARDIRQ-W} state was registered at: [ 4039.311004] lock_acquire+0xc6/0x300 [ 4039.311018] _raw_spin_lock+0x39/0x80 [ 4039.311031] amdgpu_userq_fence_driver_process.part.0+0x30/0x180 [amdgpu] [ 4039.311146] amdgpu_userq_fence_driver_process+0x17/0x30 [amdgpu] [ 4039.311257] gfx_v11_0_eop_irq+0x132/0x170 [amdgpu] Fix by using spin_lock_irqsave()/spin_unlock_irqrestore() to properly manage interrupt state regardless of calling context. Reviewed-by: Christian König Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index 2018dd85fdfbe..5bd02153ddf2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -183,15 +183,16 @@ void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_d { struct amdgpu_userq_fence *userq_fence, *tmp; struct dma_fence *fence; + unsigned long flags; u64 rptr; int i; if (!fence_drv) return; + spin_lock_irqsave(&fence_drv->fence_list_lock, flags); rptr = amdgpu_userq_fence_read(fence_drv); - spin_lock(&fence_drv->fence_list_lock); list_for_each_entry_safe(userq_fence, tmp, &fence_drv->fences, link) { fence = &userq_fence->base; @@ -206,7 +207,7 @@ void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_d list_del(&userq_fence->link); dma_fence_put(fence); } - spin_unlock(&fence_drv->fence_list_lock); + spin_unlock_irqrestore(&fence_drv->fence_list_lock, flags); } void amdgpu_userq_fence_driver_destroy(struct kref *ref) From a487a67aa87c82eacc8c479cbf0c3fe1460f5883 Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Wed, 24 Sep 2025 17:52:24 +0800 Subject: [PATCH 2513/2653] drm/amdgpu: add RAS bad page threshold handling for PMFW manages eeprom Check if bad page threshold is reached and take actions accordingly. v2: remove rma message sent to smu when pmfw manages eeprom. v3: add null pointer check for con. Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 36 +++++++++++++++---- 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 01b38a6e198e4..99aa1908833d3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -903,6 +903,33 @@ int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *contro return ret; } +static int amdgpu_ras_smu_eeprom_append(struct amdgpu_ras_eeprom_control *control) +{ + struct amdgpu_device *adev = to_amdgpu_device(control); + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + + if (!amdgpu_ras_smu_eeprom_supported(adev) || !con) + return 0; + + control->ras_num_bad_pages = con->bad_page_num; + + if (amdgpu_bad_page_threshold != 0 && + control->ras_num_bad_pages > con->bad_page_cnt_threshold) { + dev_warn(adev->dev, + "Saved bad pages %d reaches threshold value %d\n", + control->ras_num_bad_pages, con->bad_page_cnt_threshold); + + if (adev->cper.enabled && amdgpu_cper_generate_bp_threshold_record(adev)) + dev_warn(adev->dev, "fail to generate bad page threshold cper records\n"); + + if ((amdgpu_bad_page_threshold != -1) && + (amdgpu_bad_page_threshold != -2)) + con->is_rma = true; + } + + return 0; +} + /** * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table * @control: pointer to control structure @@ -921,17 +948,14 @@ int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, const u32 num) { struct amdgpu_device *adev = to_amdgpu_device(control); - struct amdgpu_ras *con = amdgpu_ras_get_context(adev); int res, i; uint64_t nps = AMDGPU_NPS1_PARTITION_MODE; - if (!__is_ras_eeprom_supported(adev) || !con) + if (!__is_ras_eeprom_supported(adev)) return 0; - if (amdgpu_ras_smu_eeprom_supported(adev)) { - control->ras_num_bad_pages = con->bad_page_num; - return 0; - } + if (amdgpu_ras_smu_eeprom_supported(adev)) + return amdgpu_ras_smu_eeprom_append(control); if (num == 0) { dev_err(adev->dev, "will not append 0 records\n"); From f0ca3f556063c6c68e9290808f86a734e79372c2 Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Thu, 6 Nov 2025 16:26:56 +0800 Subject: [PATCH 2514/2653] drm/amdgpu: optimize timeout implemention in ras_eeprom_update_record_num The busy status returned by ras_eeprom_update_record_num may not be an error, increase timeout to exclude false busy status. Also add more comments to make the code readable. v2: define a macro for the timeout value. Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 99aa1908833d3..64dd7a81bff5f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -124,6 +124,8 @@ RAS_TABLE_V2_1_INFO_SIZE) \ / RAS_TABLE_RECORD_SIZE) +#define RAS_SMU_MESSAGE_TIMEOUT_MS 1000 /* 1s */ + /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM * offset off of RAS_TABLE_START. That is, this is something you can * add to control->i2c_address, and then tell I2C layer to read @@ -874,7 +876,7 @@ amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *control) { struct amdgpu_device *adev = to_amdgpu_device(control); - int ret, timeout = 1000; + int ret, retry = 20; if (!amdgpu_ras_smu_eeprom_supported(adev)) return 0; @@ -882,17 +884,23 @@ int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *contro control->ras_num_recs_old = control->ras_num_recs; do { + /* 1000ms timeout is long enough, smu_get_badpage_count won't + * return -EBUSY before timeout. + */ ret = amdgpu_ras_smu_get_badpage_count(adev, - &(control->ras_num_recs), 12); + &(control->ras_num_recs), RAS_SMU_MESSAGE_TIMEOUT_MS); if (!ret && (control->ras_num_recs_old == control->ras_num_recs)) { - /* record number update in PMFW needs some time */ + /* record number update in PMFW needs some time, + * smu_get_badpage_count may return immediately without + * count update, sleep for a while and retry again. + */ msleep(50); - timeout -= 50; + retry--; } else { break; } - } while (timeout); + } while (retry); /* no update of record number is not a real failure, * don't print warning here From 15b34bae1facd01e4824f30e80ee50629ac0e43a Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Thu, 6 Nov 2025 11:06:21 +0800 Subject: [PATCH 2515/2653] drm/amd/pm: remove unnecessary prints for smu busy smu busy is a normal case when calling SMU_MSG_GetBadPageCount, so no need to print error status at each time.Instead, only print error status when timeout given by user is reached. Signed-off-by: Gangliang Xie Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 2 ++ drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 10 +++++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index 0ce8cff27bf94..fc580800609c0 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -956,6 +956,8 @@ static int smu_v13_0_12_get_badpage_count(struct amdgpu_device *adev, uint32_t * now = (uint64_t)ktime_to_ms(ktime_get()); } while (now < end); + dev_err(adev->dev, + "smu get bad page count timeout!\n"); return ret; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index fc0d2fe0c9b2b..85fc1690945c2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -164,9 +164,13 @@ static void __smu_cmn_reg_print_error(struct smu_context *smu, msg_index, param, message); break; case SMU_RESP_BUSY_OTHER: - dev_err_ratelimited(adev->dev, - "SMU: I'm very busy for your command: index:%d param:0x%08X message:%s", - msg_index, param, message); + /* It is normal for SMU_MSG_GetBadPageCount to return busy + * so don't print error at this case. + */ + if (msg != SMU_MSG_GetBadPageCount) + dev_err_ratelimited(adev->dev, + "SMU: I'm very busy for your command: index:%d param:0x%08X message:%s", + msg_index, param, message); break; case SMU_RESP_DEBUG_END: dev_err_ratelimited(adev->dev, From ed071e0dcba7d798753483033148b206ef7ff340 Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Thu, 23 Oct 2025 15:26:33 -0400 Subject: [PATCH 2516/2653] drm/amd/display: Only initialize LSDMA if it is supported in DMU Need to check caps flag to determine whether LSDMA is supported in DMU Reviewed-by: Rafal Ostrowski Signed-off-by: Alvin Lee Signed-off-by: Fangzhi Zuo Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 3 +++ drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index fffbf1983143d..7b09af1cb306e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -2084,6 +2084,9 @@ bool dmub_lsdma_init(struct dc_dmub_srv *dc_dmub_srv) struct dmub_cmd_lsdma_data *lsdma_data = &cmd.lsdma.lsdma_data; bool result; + if (!dc_dmub_srv->dmub->feature_caps.lsdma_support_in_dmu) + return false; + memset(&cmd, 0, sizeof(cmd)); cmd.cmd_common.header.type = DMUB_CMD__LSDMA; diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index a0ffa046d8c2b..067949d6eeb86 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -721,6 +721,7 @@ struct dmub_feature_caps { uint8_t replay_supported; uint8_t replay_reserved[3]; uint8_t abm_aux_backlight_support; + uint8_t lsdma_support_in_dmu; }; struct dmub_visual_confirm_color { From 7667a1409fa748fe91098747c4692f6ba3c9b34b Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Mon, 27 Oct 2025 12:11:15 -0400 Subject: [PATCH 2517/2653] drm/amd/display: Fix index bug for fill latency [WHY&HOW] This array should be indexed by pstate type followed by plane index. Reviewed-by: Austin Zheng Signed-off-by: Dillon Varone Signed-off-by: Fangzhi Zuo Tested-by: Dan Wheeler --- .../dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index df81bd963bb88..a02e9fd6b5ca4 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -12944,7 +12944,7 @@ void dml2_core_calcs_get_plane_support_info(const struct dml2_display_cfg *displ out->active_latency_hiding_us = (int)mode_lib->ms.VActiveLatencyHidingUs[plane_idx]; out->vactive_det_fill_delay_us[dml2_pstate_type_uclk] = - (unsigned int)math_ceil(mode_lib->ms.pstate_vactive_det_fill_delay_us[plane_idx][dml2_pstate_type_uclk]); + (unsigned int)math_ceil(mode_lib->ms.pstate_vactive_det_fill_delay_us[dml2_pstate_type_uclk][plane_idx]); } void dml2_core_calcs_get_stream_support_info(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct core_stream_support_info *out, int plane_index) From f131e3f52e77b010478ea68cccc1d896b2a08841 Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Thu, 23 Oct 2025 10:03:59 -0400 Subject: [PATCH 2518/2653] drm/amd/display: Allow VRR params change if unsynced with the stream MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [Why] When changing resolution (e.g., 4K → FHD) in mirror/clone mode with certain monitors, the monitor blanks and loses connection due to an early exit in vrr_settings_require_update(). The function only checks if VRR state, fixed refresh target, or min/max refresh rate range has changed. During mode changes, if the calculated min/max refresh values remain the same even though the stream's v_total changed, the function returns early without updating vrr_params.adjust.v_total_min/max, leaving the monitor's VRR timing parameters unsynced with the new mode, causing it to blank out. [How] Explicitly adjust VRR parameters to the stream's nominal v_total when VRR is supported, but inactive. Fixes: 3fd606f57448 ("drm/amd/display: more liberal vmin/vmax update for freesync") Reviewed-by: Aurabindo Pillai Signed-off-by: Ivan Lipski Signed-off-by: Fangzhi Zuo Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/modules/freesync/freesync.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index ce421bcddcb08..1aae46d703ba0 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -1260,6 +1260,17 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, update_v_total_for_static_ramp( core_freesync, stream, in_out_vrr); } + + /* + * If VRR is inactive, set vtotal min and max to nominal vtotal + */ + if (in_out_vrr->state == VRR_STATE_INACTIVE) { + in_out_vrr->adjust.v_total_min = + mod_freesync_calc_v_total_from_refresh(stream, + in_out_vrr->max_refresh_in_uhz); + in_out_vrr->adjust.v_total_max = in_out_vrr->adjust.v_total_min; + return; + } } unsigned long long mod_freesync_calc_nominal_field_rate( From 8a997167be6826e392549d22fe668dfc22989c51 Mon Sep 17 00:00:00 2001 From: George Shen Date: Mon, 6 Oct 2025 11:23:31 -0400 Subject: [PATCH 2519/2653] drm/amd/display: Add interface to capture power feature status for debug logging [Why] The status of various power features is often important information when debugging certain issues, such as underflow. This info helps to narrow down the potential sources of errors. [How] Add dc interface to capture power feature enablement status. Reviewed-by: Dillon Varone Signed-off-by: George Shen Signed-off-by: Fangzhi Zuo Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 7 +++++++ drivers/gpu/drm/amd/display/dc/dc.h | 14 ++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 4a592998f8e6b..d23187cf63875 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -6422,6 +6422,13 @@ void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, dc->hwss.get_underflow_debug_data(dc, tg, out_data); } +void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst, + struct power_features *out_data) +{ + out_data->uclk_p_state = dc->current_state->clk_mgr->clks.p_state_change_support; + out_data->fams = dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching; +} + void dc_log_preos_dmcub_info(const struct dc *dc) { dc_dmub_srv_log_preos_dmcub_info(dc->ctx->dmub_srv); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 9e0e97686b674..6dafd74f9a9ad 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1868,6 +1868,18 @@ struct dc_underflow_debug_data { struct dcn_dccg_reg_state *dccg_reg_state[MAX_PIPES]; }; +struct power_features { + bool ips; + bool rcg; + bool replay; + bool dds; + bool sprs; + bool psr; + bool fams; + bool mpo; + bool uclk_p_state; +}; + /* * Create a new surface with default parameters; */ @@ -2775,4 +2787,6 @@ bool dc_can_clear_cursor_limit(const struct dc *dc); */ void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data); +void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst, struct power_features *out_data); + #endif /* DC_INTERFACE_H_ */ From 7f4b5436c40cf11d10097888e44fea341f2e1eb2 Mon Sep 17 00:00:00 2001 From: Ian Chen Date: Tue, 13 May 2025 16:38:35 +0800 Subject: [PATCH 2520/2653] drm/amd/display: Add new SMART POWER OLED interfaces [why && how] To optimize power consumption on certain OLED LED panels by sending MaxCLL per frame to TCON Reviewed-by: Aric Cyr Signed-off-by: Ian Chen Signed-off-by: Fangzhi Zuo Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 89 ++++++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dc.h | 7 ++ 2 files changed, 96 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index d23187cf63875..fc9510e21dd31 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -5978,6 +5978,95 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc, return true; } +bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_t peak_nits, + uint8_t debug_control, uint16_t fixed_CLL, uint32_t triggerline) +{ + bool status = false; + struct dc *dc = link->ctx->dc; + union dmub_rb_cmd cmd; + uint8_t otg_inst = 0; + unsigned int panel_inst = 0; + struct pipe_ctx *pipe_ctx = NULL; + struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx; + int i = 0; + + // get panel_inst + if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) + return status; + + // get otg_inst + for (i = 0; i < MAX_PIPES; i++) { + if (res_ctx && + res_ctx->pipe_ctx[i].stream && + res_ctx->pipe_ctx[i].stream->link && + res_ctx->pipe_ctx[i].stream->link == link && + res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) { + pipe_ctx = &res_ctx->pipe_ctx[i]; + //TODO: refactor for multi edp support + break; + } + } + + if (pipe_ctx) + otg_inst = pipe_ctx->stream_res.tg->inst; + + // fill in cmd + memset(&cmd, 0, sizeof(cmd)); + + cmd.smart_power_oled_enable.header.type = DMUB_CMD__SMART_POWER_OLED; + cmd.smart_power_oled_enable.header.sub_type = DMUB_CMD__SMART_POWER_OLED_ENABLE; + cmd.smart_power_oled_enable.header.payload_bytes = + sizeof(struct dmub_rb_cmd_smart_power_oled_enable_data) - sizeof(struct dmub_cmd_header); + cmd.smart_power_oled_enable.header.ret_status = 1; + cmd.smart_power_oled_enable.data.enable = enable; + cmd.smart_power_oled_enable.data.panel_inst = panel_inst; + cmd.smart_power_oled_enable.data.peak_nits = peak_nits; + cmd.smart_power_oled_enable.data.otg_inst = otg_inst; + cmd.smart_power_oled_enable.data.digfe_inst = link->link_enc->preferred_engine; + cmd.smart_power_oled_enable.data.digbe_inst = link->link_enc->transmitter; + + cmd.smart_power_oled_enable.data.debugcontrol = debug_control; + cmd.smart_power_oled_enable.data.triggerline = triggerline; + cmd.smart_power_oled_enable.data.fixed_max_cll = fixed_CLL; + + // send cmd + status = dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); + + return status; +} + +bool dc_smart_power_oled_get_max_cll(const struct dc_link *link, unsigned int *pCurrent_MaxCLL) +{ + struct dc *dc = link->ctx->dc; + union dmub_rb_cmd cmd; + bool status = false; + unsigned int panel_inst = 0; + + // get panel_inst + if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) + return status; + + // fill in cmd + memset(&cmd, 0, sizeof(cmd)); + + cmd.smart_power_oled_getmaxcll.header.type = DMUB_CMD__SMART_POWER_OLED; + cmd.smart_power_oled_getmaxcll.header.sub_type = DMUB_CMD__SMART_POWER_OLED_GETMAXCLL; + cmd.smart_power_oled_getmaxcll.header.payload_bytes = sizeof(cmd.smart_power_oled_getmaxcll.data); + cmd.smart_power_oled_getmaxcll.header.ret_status = 1; + + cmd.smart_power_oled_getmaxcll.data.input.panel_inst = panel_inst; + + // send cmd and wait for reply + status = dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY); + + if (status) + *pCurrent_MaxCLL = cmd.smart_power_oled_getmaxcll.data.output.current_max_cll; + else + *pCurrent_MaxCLL = 0; + + return status; +} + uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, uint8_t dpia_port_index) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 6dafd74f9a9ad..4b0577e522cce 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -2722,6 +2722,13 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc, uint32_t link_index, struct aux_payload *payload); +/* + * smart power OLED Interfaces + */ +bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_t peak_nits, + uint8_t debug_control, uint16_t fixed_CLL, uint32_t triggerline); +bool dc_smart_power_oled_get_max_cll(const struct dc_link *link, unsigned int *pCurrent_MaxCLL); + /* Get dc link index from dpia port index */ uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, uint8_t dpia_port_index); From a269560e803cec5a789c7dfdd245a0c776f1af1a Mon Sep 17 00:00:00 2001 From: Mohit Bawa Date: Thu, 23 Oct 2025 10:40:41 -0400 Subject: [PATCH 2521/2653] drm/amd/display: refactor DSC cap calculation for dcn35 why: dcn35 currently uses a hardcoded DSC display clock value which is incorrect for some asic types. Newer DCN versions retrieve dsc display clock from clk_mgr. The same can be done for dcn35. how: Refactor the DSC cap calculation using pre-existing logic. Handle ODM combine requirements in dc_dsc.c. Replace hardcoded display clock with actual value retrieved from clk_mgr. Reviewed-by: Nicholas Kazlauskas Reviewed-by: Charlene Liu Reviewed-by: Wenjing Liu Signed-off-by: Mohit Bawa Signed-off-by: Fangzhi Zuo Tested-by: Dan Wheeler --- .../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 30 ++++++++++++++++++ .../drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c | 31 ++++++++++++++++++- 2 files changed, 60 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index 35d20a663d67a..dfd0c9505af09 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -1295,6 +1295,35 @@ static void dcn35_update_clocks_fpga(struct clk_mgr *clk_mgr, dcn35_update_clocks_update_dtb_dto(clk_mgr_int, context, clk_mgr->clks.ref_dtbclk_khz); } +static unsigned int dcn35_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + + unsigned int num_clk_levels; + + switch (clk_type) { + case CLK_TYPE_DISPCLK: + num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; + return num_clk_levels ? + clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 : + clk_mgr->base.boot_snapshot.dispclk; + case CLK_TYPE_DPPCLK: + num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels; + return num_clk_levels ? + clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dppclk_mhz * 1000 : + clk_mgr->base.boot_snapshot.dppclk; + case CLK_TYPE_DSCCLK: + num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; + return num_clk_levels ? + clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 / 3 : + clk_mgr->base.boot_snapshot.dispclk / 3; + default: + break; + } + + return 0; +} + static struct clk_mgr_funcs dcn35_funcs = { .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, @@ -1306,6 +1335,7 @@ static struct clk_mgr_funcs dcn35_funcs = { .set_low_power_state = dcn35_set_low_power_state, .exit_low_power_state = dcn35_exit_low_power_state, .is_ips_supported = dcn35_is_ips_supported, + .get_max_clock_khz = dcn35_get_max_clock_khz, }; struct clk_mgr_funcs dcn35_fpga_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c index f9c6377ac66cf..e712985f7abdb 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c @@ -28,9 +28,9 @@ #include "reg_helper.h" static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe); +static void dsc35_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz); static const struct dsc_funcs dcn35_dsc_funcs = { - .dsc_get_enc_caps = dsc2_get_enc_caps, .dsc_read_state = dsc2_read_state, .dsc_read_reg_state = dsc2_read_reg_state, .dsc_validate_stream = dsc2_validate_stream, @@ -40,6 +40,7 @@ static const struct dsc_funcs dcn35_dsc_funcs = { .dsc_disable = dsc2_disable, .dsc_disconnect = dsc2_disconnect, .dsc_wait_disconnect_pending_clear = dsc2_wait_disconnect_pending_clear, + .dsc_get_single_enc_caps = dsc35_get_single_enc_caps, }; /* Macro definitios for REG_SET macros*/ @@ -111,3 +112,31 @@ void dsc35_set_fgcg(struct dcn20_dsc *dsc20, bool enable) { REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable); } + +void dsc35_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz) +{ + dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */ + + dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1; + dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1; + dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1; + dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1; + + dsc_enc_caps->lb_bit_depth = 13; + dsc_enc_caps->is_block_pred_supported = true; + + dsc_enc_caps->color_formats.bits.RGB = 1; + dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; + dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; + dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; + dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; + + dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1; + dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1; + dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1; + + dsc_enc_caps->max_total_throughput_mps = max_dscclk_khz * 3 / 1000; + + dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */ + dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */ +} From d4874d65e9f5aee5dc281ff208eaadff3c4d4f15 Mon Sep 17 00:00:00 2001 From: Dominik Kaszewski Date: Mon, 20 Oct 2025 15:16:07 +0200 Subject: [PATCH 2522/2653] drm/amd/display: Change lock descriptor values [Why] Review of usage scenarios requires dc_lock_descriptor modification. [How] Replace STATE/LINK/STREAM/PLANE with GLOBAL/STREAM/LINK, where the first means all streams to be locked. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Dominik Kaszewski Signed-off-by: Fangzhi Zuo Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 146 +++++++++++------------ drivers/gpu/drm/amd/display/dc/dc.h | 5 +- 2 files changed, 72 insertions(+), 79 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index fc9510e21dd31..5caf8eecd8f0c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2670,41 +2670,42 @@ static struct surface_update_descriptor get_plane_info_update_type(const struct if (!u->plane_info) return update_type; - elevate_update_type(&update_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_PLANE); + // `plane_info` present means at least `STREAM` lock is required + elevate_update_type(&update_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); if (u->plane_info->color_space != u->surface->color_space) { update_flags->bits.color_space_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); } if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) { update_flags->bits.horizontal_mirror_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); } if (u->plane_info->rotation != u->surface->rotation) { update_flags->bits.rotation_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } if (u->plane_info->format != u->surface->format) { update_flags->bits.pixel_format_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } if (u->plane_info->stereo_format != u->surface->stereo_format) { update_flags->bits.stereo_format_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) { update_flags->bits.per_pixel_alpha_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); } if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) { update_flags->bits.global_alpha_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); } if (u->plane_info->dcc.enable != u->surface->dcc.enable @@ -2716,7 +2717,7 @@ static struct surface_update_descriptor get_plane_info_update_type(const struct * recalculate stutter period. */ update_flags->bits.dcc_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } if (resource_pixel_format_to_bpp(u->plane_info->format) != @@ -2725,34 +2726,34 @@ static struct surface_update_descriptor get_plane_info_update_type(const struct * and DML calculation */ update_flags->bits.bpp_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) { update_flags->bits.plane_size_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); } const struct dc_tiling_info *tiling = &u->plane_info->tiling_info; if (memcmp(tiling, &u->surface->tiling_info, sizeof(*tiling)) != 0) { update_flags->bits.swizzle_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); switch (tiling->gfxversion) { case DcGfxVersion9: case DcGfxVersion10: case DcGfxVersion11: if (tiling->gfx9.swizzle != DC_SW_LINEAR) { - elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); update_flags->bits.bandwidth_change = 1; + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } break; case DcGfxAddr3: if (tiling->gfx_addr3.swizzle != DC_ADDR3_SW_LINEAR) { - elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); update_flags->bits.bandwidth_change = 1; + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } break; case DcGfxVersion7: @@ -2777,7 +2778,8 @@ static struct surface_update_descriptor get_scaling_info_update_type( if (!u->scaling_info) return update_type; - elevate_update_type(&update_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_PLANE); + // `scaling_info` present means at least `STREAM` lock is required + elevate_update_type(&update_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); if (u->scaling_info->src_rect.width != u->surface->src_rect.width || u->scaling_info->src_rect.height != u->surface->src_rect.height @@ -2788,6 +2790,7 @@ static struct surface_update_descriptor get_scaling_info_update_type( || u->scaling_info->scaling_quality.integer_scaling != u->surface->scaling_quality.integer_scaling) { update_flags->bits.scaling_change = 1; + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); if (u->scaling_info->src_rect.width > u->surface->src_rect.width || u->scaling_info->src_rect.height > u->surface->src_rect.height) @@ -2813,17 +2816,10 @@ static struct surface_update_descriptor get_scaling_info_update_type( || u->scaling_info->clip_rect.x != u->surface->clip_rect.x || u->scaling_info->clip_rect.y != u->surface->clip_rect.y || u->scaling_info->dst_rect.x != u->surface->dst_rect.x - || u->scaling_info->dst_rect.y != u->surface->dst_rect.y) + || u->scaling_info->dst_rect.y != u->surface->dst_rect.y) { + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); update_flags->bits.position_change = 1; - - /* process every update flag before returning */ - if (update_flags->bits.clock_change - || update_flags->bits.bandwidth_change - || update_flags->bits.scaling_change) - elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); - - if (update_flags->bits.position_change) - elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); + } return update_type; } @@ -2837,7 +2833,7 @@ static struct surface_update_descriptor det_surface_update( if (u->surface->force_full_update) { update_flags->raw = 0xFFFFFFFF; - elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); return overall_type; } @@ -2852,76 +2848,69 @@ static struct surface_update_descriptor det_surface_update( if (u->flip_addr) { update_flags->bits.addr_update = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + if (u->flip_addr->address.tmz_surface != u->surface->address.tmz_surface) { update_flags->bits.tmz_changed = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } } - if (u->in_transfer_func) + if (u->in_transfer_func) { update_flags->bits.in_transfer_func_change = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } - if (u->input_csc_color_matrix) + if (u->input_csc_color_matrix) { update_flags->bits.input_csc_change = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } - if (u->coeff_reduction_factor) + if (u->coeff_reduction_factor) { update_flags->bits.coeff_reduction_change = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } - if (u->gamut_remap_matrix) + if (u->gamut_remap_matrix) { update_flags->bits.gamut_remap_change = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } - if (u->blend_tf) + if (u->blend_tf || (u->gamma && dce_use_lut(u->plane_info ? u->plane_info->format : u->surface->format))) { update_flags->bits.gamma_change = 1; - - if (u->gamma) { - enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN; - - if (u->plane_info) - format = u->plane_info->format; - else - format = u->surface->format; - - if (dce_use_lut(format)) - update_flags->bits.gamma_change = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } - if (u->lut3d_func || u->func_shaper) + if (u->lut3d_func || u->func_shaper) { update_flags->bits.lut_3d = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } if (u->hdr_mult.value) if (u->hdr_mult.value != u->surface->hdr_mult.value) { - update_flags->bits.hdr_mult = 1; // TODO: Should be fast? - elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); + update_flags->bits.hdr_mult = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); } if (u->sdr_white_level_nits) if (u->sdr_white_level_nits != u->surface->sdr_white_level_nits) { - update_flags->bits.sdr_white_level_nits = 1; // TODO: Should be fast? - elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); + update_flags->bits.sdr_white_level_nits = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } if (u->cm2_params) { - if ((u->cm2_params->component_settings.shaper_3dlut_setting - != u->surface->mcm_shaper_3dlut_setting) - || (u->cm2_params->component_settings.lut1d_enable - != u->surface->mcm_lut1d_enable)) - update_flags->bits.mcm_transfer_function_enable_change = 1; - if (u->cm2_params->cm2_luts.lut3d_data.lut3d_src - != u->surface->mcm_luts.lut3d_data.lut3d_src) + if (u->cm2_params->component_settings.shaper_3dlut_setting != u->surface->mcm_shaper_3dlut_setting + || u->cm2_params->component_settings.lut1d_enable != u->surface->mcm_lut1d_enable + || u->cm2_params->cm2_luts.lut3d_data.lut3d_src != u->surface->mcm_luts.lut3d_data.lut3d_src) { update_flags->bits.mcm_transfer_function_enable_change = 1; - } - if (update_flags->bits.in_transfer_func_change) { - // TODO: Fast? - elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STATE); + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); + } } if (update_flags->bits.lut_3d && u->surface->mcm_luts.lut3d_data.lut3d_src != DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { - elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); - } - if (update_flags->bits.mcm_transfer_function_enable_change) { - elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } if (check_config->enable_legacy_fast_update && @@ -2929,7 +2918,7 @@ static struct surface_update_descriptor det_surface_update( update_flags->bits.gamut_remap_change || update_flags->bits.input_csc_change || update_flags->bits.coeff_reduction_change)) { - elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } return overall_type; } @@ -2966,19 +2955,19 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( struct surface_update_descriptor overall_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE }; if (stream_update && stream_update->pending_test_pattern) { - elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } if (stream_update && stream_update->hw_cursor_req) { - elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } /* some stream updates require passive update */ if (stream_update) { - union stream_update_flags *su_flags = &stream_update->stream->update_flags; - elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + union stream_update_flags *su_flags = &stream_update->stream->update_flags; + if ((stream_update->src.height != 0 && stream_update->src.width != 0) || (stream_update->dst.height != 0 && stream_update->dst.width != 0) || stream_update->integer_scaling_update) @@ -2990,8 +2979,10 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( if (stream_update->abm_level) su_flags->bits.abm_level = 1; - if (stream_update->dpms_off) + if (stream_update->dpms_off) { su_flags->bits.dpms_off = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL | LOCK_DESCRIPTOR_LINK); + } if (stream_update->gamut_remap) su_flags->bits.gamut_remap = 1; @@ -3019,17 +3010,20 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( if (stream_update->output_color_space) su_flags->bits.out_csc = 1; - if (su_flags->raw != 0) - elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STATE); + // TODO: Make each elevation explicit, as to not override fast stream in crct_timing_adjust + if (su_flags->raw) + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); - if (stream_update->output_csc_transform) + // Non-global cases + if (stream_update->output_csc_transform) { su_flags->bits.out_csc = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } - /* Output transfer function changes do not require bandwidth recalculation, - * so don't trigger a full update - */ - if (!check_config->enable_legacy_fast_update && stream_update->out_transfer_func) + if (!check_config->enable_legacy_fast_update && stream_update->out_transfer_func) { su_flags->bits.out_tf = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } } for (int i = 0 ; i < surface_count; i++) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 4b0577e522cce..833ec6369bf33 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -469,10 +469,9 @@ enum surface_update_type { enum dc_lock_descriptor { LOCK_DESCRIPTOR_NONE = 0x0, - LOCK_DESCRIPTOR_STATE = 0x1, + LOCK_DESCRIPTOR_STREAM = 0x1, LOCK_DESCRIPTOR_LINK = 0x2, - LOCK_DESCRIPTOR_STREAM = 0x4, - LOCK_DESCRIPTOR_PLANE = 0x8, + LOCK_DESCRIPTOR_GLOBAL = 0x4, }; struct surface_update_descriptor { From a5e17c2d5dc70afe46321f6dfb83dd44c5aa3e37 Mon Sep 17 00:00:00 2001 From: Chuntao Tso Date: Fri, 31 Oct 2025 10:02:51 +0800 Subject: [PATCH 2523/2653] drm/amd/display: To support Replay frame skip mode [Why & How] The change is to optimize the Replay power saving by reducing the refresh rate with frame skipping mode Reviewed-by: Robin Chen Signed-off-by: Chuntao Tso Signed-off-by: Fangzhi Zuo Tested-by: Dan Wheeler --- .../amd/display/amdgpu_dm/amdgpu_dm_replay.c | 2 +- drivers/gpu/drm/amd/display/dc/dc_types.h | 6 ++++ .../gpu/drm/amd/display/dc/dce/dmub_replay.c | 7 +++-- .../gpu/drm/amd/display/dc/dce/dmub_replay.h | 5 ++-- .../gpu/drm/amd/display/dc/inc/link_service.h | 4 +-- .../link/protocols/link_edp_panel_control.c | 17 +++++++---- .../link/protocols/link_edp_panel_control.h | 4 +-- .../amd/display/modules/power/power_helpers.c | 30 +++++++++++++++++++ .../amd/display/modules/power/power_helpers.h | 5 ++++ 9 files changed, 65 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c index 80704d709e44a..da94e3544b657 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c @@ -162,7 +162,7 @@ bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool wait) if (link) { link->dc->link_srv->edp_setup_replay(link, stream); - link->dc->link_srv->edp_set_coasting_vtotal(link, stream->timing.v_total); + link->dc->link_srv->edp_set_coasting_vtotal(link, stream->timing.v_total, 0); DRM_DEBUG_DRIVER("Enabling replay...\n"); link->dc->link_srv->edp_set_replay_allow_active(link, &replay_active, wait, false, NULL); return true; diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index ea6b71c43d2c8..0495e6cfcca07 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -1184,6 +1184,10 @@ struct replay_settings { uint32_t coasting_vtotal_table[PR_COASTING_TYPE_NUM]; /* Defer Update Coasting vtotal table */ uint32_t defer_update_coasting_vtotal_table[PR_COASTING_TYPE_NUM]; + /* Skip frame number table */ + uint32_t frame_skip_number_table[PR_COASTING_TYPE_NUM]; + /* Defer skip frame number table */ + uint32_t defer_frame_skip_number_table[PR_COASTING_TYPE_NUM]; /* Maximum link off frame count */ uint32_t link_off_frame_count; /* Replay pseudo vtotal for low refresh rate*/ @@ -1192,6 +1196,8 @@ struct replay_settings { uint16_t last_pseudo_vtotal; /* Replay desync error */ uint32_t replay_desync_error_fail_count; + /* The frame skip number dal send to DMUB */ + uint16_t frame_skip_number; }; /* To split out "global" and "per-panel" config settings. diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c index f9542edff14bb..fd8244c946874 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c @@ -213,7 +213,8 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub, */ static void dmub_replay_set_coasting_vtotal(struct dmub_replay *dmub, uint32_t coasting_vtotal, - uint8_t panel_inst) + uint8_t panel_inst, + uint16_t frame_skip_number) { union dmub_rb_cmd cmd; struct dc_context *dc = dmub->ctx; @@ -227,6 +228,7 @@ static void dmub_replay_set_coasting_vtotal(struct dmub_replay *dmub, pCmd->header.payload_bytes = sizeof(struct dmub_cmd_replay_set_coasting_vtotal_data); pCmd->replay_set_coasting_vtotal_data.coasting_vtotal = (coasting_vtotal & 0xFFFF); pCmd->replay_set_coasting_vtotal_data.coasting_vtotal_high = (coasting_vtotal & 0xFFFF0000) >> 16; + pCmd->replay_set_coasting_vtotal_data.frame_skip_number = frame_skip_number; dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); } @@ -283,7 +285,7 @@ static void dmub_replay_residency(struct dmub_replay *dmub, uint8_t panel_inst, * Set REPLAY power optimization flags and coasting vtotal. */ static void dmub_replay_set_power_opt_and_coasting_vtotal(struct dmub_replay *dmub, - unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal) + unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal, uint16_t frame_skip_number) { union dmub_rb_cmd cmd; struct dc_context *dc = dmub->ctx; @@ -301,6 +303,7 @@ static void dmub_replay_set_power_opt_and_coasting_vtotal(struct dmub_replay *dm pCmd->replay_set_power_opt_data.panel_inst = panel_inst; pCmd->replay_set_coasting_vtotal_data.coasting_vtotal = (coasting_vtotal & 0xFFFF); pCmd->replay_set_coasting_vtotal_data.coasting_vtotal_high = (coasting_vtotal & 0xFFFF0000) >> 16; + pCmd->replay_set_coasting_vtotal_data.frame_skip_number = frame_skip_number; dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT); } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h index e6346c0ffc0e4..07c79739a9809 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h @@ -27,11 +27,12 @@ struct dmub_replay_funcs { void (*replay_send_cmd)(struct dmub_replay *dmub, enum replay_FW_Message_type msg, union dmub_replay_cmd_set *cmd_element); void (*replay_set_coasting_vtotal)(struct dmub_replay *dmub, uint32_t coasting_vtotal, - uint8_t panel_inst); + uint8_t panel_inst, uint16_t frame_skip_number); void (*replay_residency)(struct dmub_replay *dmub, uint8_t panel_inst, uint32_t *residency, const bool is_start, const enum pr_residency_mode mode); void (*replay_set_power_opt_and_coasting_vtotal)(struct dmub_replay *dmub, - unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal); + unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal, + uint16_t frame_skip_number); }; struct dmub_replay *dmub_replay_create(struct dc_context *ctx); diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_service.h b/drivers/gpu/drm/amd/display/dc/inc/link_service.h index 140812c637b92..e3b935aebaaa4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/link_service.h +++ b/drivers/gpu/drm/amd/display/dc/inc/link_service.h @@ -291,12 +291,12 @@ struct link_service { enum replay_FW_Message_type msg, union dmub_replay_cmd_set *cmd_data); bool (*edp_set_coasting_vtotal)( - struct dc_link *link, uint32_t coasting_vtotal); + struct dc_link *link, uint32_t coasting_vtotal, uint16_t frame_skip_number); bool (*edp_replay_residency)(const struct dc_link *link, unsigned int *residency, const bool is_start, const enum pr_residency_mode mode); bool (*edp_set_replay_power_opt_and_coasting_vtotal)(struct dc_link *link, - const unsigned int *power_opts, uint32_t coasting_vtotal); + const unsigned int *power_opts, uint32_t coasting_vtotal, uint16_t frame_skip_number); bool (*edp_wait_for_t12)(struct dc_link *link); bool (*edp_is_ilr_optimization_required)(struct dc_link *link, diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 5e806edbb9f61..9391c75a30e57 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -1110,7 +1110,7 @@ bool edp_send_replay_cmd(struct dc_link *link, return true; } -bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal) +bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal, uint16_t frame_skip_number) { struct dc *dc = link->ctx->dc; struct dmub_replay *replay = dc->res_pool->replay; @@ -1122,9 +1122,11 @@ bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal) if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) return false; - if (coasting_vtotal && link->replay_settings.coasting_vtotal != coasting_vtotal) { - replay->funcs->replay_set_coasting_vtotal(replay, coasting_vtotal, panel_inst); + if (coasting_vtotal && (link->replay_settings.coasting_vtotal != coasting_vtotal || + link->replay_settings.frame_skip_number != frame_skip_number)) { + replay->funcs->replay_set_coasting_vtotal(replay, coasting_vtotal, panel_inst, frame_skip_number); link->replay_settings.coasting_vtotal = coasting_vtotal; + link->replay_settings.frame_skip_number = frame_skip_number; } return true; @@ -1152,7 +1154,7 @@ bool edp_replay_residency(const struct dc_link *link, } bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link, - const unsigned int *power_opts, uint32_t coasting_vtotal) + const unsigned int *power_opts, uint32_t coasting_vtotal, uint16_t frame_skip_number) { struct dc *dc = link->ctx->dc; struct dmub_replay *replay = dc->res_pool->replay; @@ -1163,13 +1165,16 @@ bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link, /* Only both power and coasting vtotal changed, this func could return true */ if (power_opts && link->replay_settings.replay_power_opt_active != *power_opts && - coasting_vtotal && link->replay_settings.coasting_vtotal != coasting_vtotal) { + (coasting_vtotal && + (link->replay_settings.coasting_vtotal != coasting_vtotal || + link->replay_settings.frame_skip_number != frame_skip_number))) { if (link->replay_settings.replay_feature_enabled && replay->funcs->replay_set_power_opt_and_coasting_vtotal) { replay->funcs->replay_set_power_opt_and_coasting_vtotal(replay, - *power_opts, panel_inst, coasting_vtotal); + *power_opts, panel_inst, coasting_vtotal, frame_skip_number); link->replay_settings.replay_power_opt_active = *power_opts; link->replay_settings.coasting_vtotal = coasting_vtotal; + link->replay_settings.frame_skip_number = frame_skip_number; } else return false; } else diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h index 62a6344e613e3..dd79c7cd2828d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h @@ -59,12 +59,12 @@ bool edp_setup_replay(struct dc_link *link, bool edp_send_replay_cmd(struct dc_link *link, enum replay_FW_Message_type msg, union dmub_replay_cmd_set *cmd_data); -bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal); +bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal, uint16_t frame_skip_number); bool edp_replay_residency(const struct dc_link *link, unsigned int *residency, const bool is_start, const enum pr_residency_mode mode); bool edp_get_replay_state(const struct dc_link *link, uint64_t *state); bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link, - const unsigned int *power_opts, uint32_t coasting_vtotal); + const unsigned int *power_opts, uint32_t coasting_vtotal, uint16_t frame_skip_number); bool edp_wait_for_t12(struct dc_link *link); bool edp_is_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing); diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c index 29ccd3532d139..88b5b716a0847 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c @@ -975,6 +975,34 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link, return true; } +void set_replay_frame_skip_number(struct dc_link *link, + enum replay_coasting_vtotal_type type, + uint32_t coasting_vtotal_refresh_rate_mhz, + uint32_t flicker_free_refresh_rate_mhz, + bool is_defer) +{ + uint32_t *frame_skip_number_array = NULL; + uint32_t frame_skip_number = 0; + + if (link == NULL || flicker_free_refresh_rate_mhz == 0 || coasting_vtotal_refresh_rate_mhz == 0) + return; + + if (is_defer) + frame_skip_number_array = link->replay_settings.defer_frame_skip_number_table; + else + frame_skip_number_array = link->replay_settings.frame_skip_number_table; + + if (frame_skip_number_array == NULL) + return; + + frame_skip_number = coasting_vtotal_refresh_rate_mhz / flicker_free_refresh_rate_mhz; + + if (frame_skip_number >= 1) + frame_skip_number_array[type] = frame_skip_number - 1; + else + frame_skip_number_array[type] = 0; +} + void set_replay_defer_update_coasting_vtotal(struct dc_link *link, enum replay_coasting_vtotal_type type, uint32_t vtotal) @@ -987,6 +1015,8 @@ void update_replay_coasting_vtotal_from_defer(struct dc_link *link, { link->replay_settings.coasting_vtotal_table[type] = link->replay_settings.defer_update_coasting_vtotal_table[type]; + link->replay_settings.frame_skip_number_table[type] = + link->replay_settings.defer_frame_skip_number_table[type]; } void set_replay_coasting_vtotal(struct dc_link *link, diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h index 391209a3bf298..87d31d9dce5a6 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h @@ -60,6 +60,11 @@ void set_replay_coasting_vtotal(struct dc_link *link, void set_replay_defer_update_coasting_vtotal(struct dc_link *link, enum replay_coasting_vtotal_type type, uint32_t vtotal); +void set_replay_frame_skip_number(struct dc_link *link, + enum replay_coasting_vtotal_type type, + uint32_t coasting_vtotal_refresh_rate_Mhz, + uint32_t flicker_free_refresh_rate_Mhz, + bool is_defer); void update_replay_coasting_vtotal_from_defer(struct dc_link *link, enum replay_coasting_vtotal_type type); void set_replay_low_rr_full_screen_video_src_vtotal(struct dc_link *link, uint16_t vtotal); From aed66ba8071eca09f76227738e255d405a5dc4ce Mon Sep 17 00:00:00 2001 From: Dominik Kaszewski Date: Fri, 31 Oct 2025 09:35:58 +0100 Subject: [PATCH 2524/2653] drm/amd/display: Revert in_transfer_func_change to MED [Why] Last commit accidentally changed handling of in_transfer_func_change from MED to FAST. [How] * Revert the line. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Dominik Kaszewski Signed-off-by: Fangzhi Zuo Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 5caf8eecd8f0c..3d90ce0815c21 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2857,7 +2857,7 @@ static struct surface_update_descriptor det_surface_update( } if (u->in_transfer_func) { update_flags->bits.in_transfer_func_change = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); } if (u->input_csc_color_matrix) { From 4e02ce4bbe8eae3ee4227e5ef9fbc2789d791b16 Mon Sep 17 00:00:00 2001 From: Leo Chen Date: Fri, 31 Oct 2025 15:25:47 -0400 Subject: [PATCH 2525/2653] drm/amd/display: dynamically clock gate before and after prefetch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [Why] An invalidation request arriving during prefetch can potentially hang the system if dynamic clock gating is enabled and memory power requests are disabled. [How] • Disable clock gating and enable memory power requests for the duration of the prefetch. • Turn on clock gating and disable memory power requests again after prefetch is complete. Limit the scope for DCN35 and DCN42 only. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Leo Chen Signed-off-by: Fangzhi Zuo Tested-by: Dan Wheeler --- .../display/dc/hubbub/dcn31/dcn31_hubbub.c | 7 +-- .../display/dc/hubbub/dcn35/dcn35_hubbub.c | 52 ++++++++++++++++++- .../display/dc/hubbub/dcn35/dcn35_hubbub.h | 1 + .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 2 + 4 files changed, 58 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c index d1aaa58b7db35..5a03758e3de6f 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c @@ -933,8 +933,8 @@ int hubbub31_init_dchub_sys_ctx(struct hubbub *hubbub, dcn20_vmid_setup(&hubbub2->vmid[15], &phys_config); } - - dcn21_dchvm_init(hubbub); + if (hubbub->funcs->dchvm_init) + hubbub->funcs->dchvm_init(hubbub); return NUM_VMID; } @@ -1071,7 +1071,8 @@ static const struct hubbub_funcs hubbub31_funcs = { .program_compbuf_size = dcn31_program_compbuf_size, .init_crb = dcn31_init_crb, .hubbub_read_state = hubbub2_read_state, - .hubbub_read_reg_state = hubbub3_read_reg_state + .hubbub_read_reg_state = hubbub3_read_reg_state, + .dchvm_init = dcn21_dchvm_init }; void hubbub31_construct(struct dcn20_hubbub *hubbub31, diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c index 1b7746a6549ab..43ba399f48226 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c @@ -549,6 +549,55 @@ void hubbub35_init(struct hubbub *hubbub) memset(&hubbub2->watermarks.a.cstate_pstate, 0, sizeof(hubbub2->watermarks.a.cstate_pstate)); } +void dcn35_dchvm_init(struct hubbub *hubbub) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + uint32_t riommu_active; + int i; + + //Init DCHVM block + REG_UPDATE(DCHVM_CTRL0, HOSTVM_INIT_REQ, 1); + + //Poll until RIOMMU_ACTIVE = 1 + for (i = 0; i < 100; i++) { + REG_GET(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, &riommu_active); + + if (riommu_active) + break; + else + udelay(5); + } + + if (riommu_active) { + // Disable gating and memory power requests + REG_UPDATE(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, 1); + REG_UPDATE_4(DCHVM_CLK_CTRL, + HVM_DISPCLK_R_GATE_DIS, 1, + HVM_DISPCLK_G_GATE_DIS, 1, + HVM_DCFCLK_R_GATE_DIS, 1, + HVM_DCFCLK_G_GATE_DIS, 1); + + //Reflect the power status of DCHUBBUB + REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1); + + //Start rIOMMU prefetching + REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1); + + //Poll until HOSTVM_PREFETCH_DONE = 1 + REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100); + + //Enable memory power requests + REG_UPDATE(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, 0); + // Enable dynamic clock gating + REG_UPDATE_4(DCHVM_CLK_CTRL, + HVM_DISPCLK_R_GATE_DIS, 0, + HVM_DISPCLK_G_GATE_DIS, 0, + HVM_DCFCLK_R_GATE_DIS, 0, + HVM_DCFCLK_G_GATE_DIS, 0); + hubbub->riommu_active = true; + } +} + /*static void hubbub35_set_request_limit(struct hubbub *hubbub, int memory_channel_count, int words_per_channel) @@ -589,7 +638,8 @@ static const struct hubbub_funcs hubbub35_funcs = { .hubbub_read_state = hubbub2_read_state, .force_usr_retraining_allow = hubbub32_force_usr_retraining_allow, .dchubbub_init = hubbub35_init, - .hubbub_read_reg_state = hubbub3_read_reg_state + .hubbub_read_reg_state = hubbub3_read_reg_state, + .dchvm_init = dcn35_dchvm_init }; void hubbub35_construct(struct dcn20_hubbub *hubbub2, diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h index 23fecf88556c8..9f65fff1bd4d5 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.h @@ -168,4 +168,5 @@ void dcn35_program_compbuf_size(struct hubbub *hubbub, unsigned int compbuf_size_kb, bool safe_to_increase); void dcn35_init_crb(struct hubbub *hubbub); void hubbub35_init(struct hubbub *hubbub); +void dcn35_dchvm_init(struct hubbub *hubbub); #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h index dafc8490efb5d..1ddfa30411c83 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h @@ -252,6 +252,8 @@ struct hubbub_funcs { void (*program_compbuf_segments)(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase); void (*wait_for_det_update)(struct hubbub *hubbub, int hubp_inst); bool (*program_arbiter)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower); + void (*dchvm_init)(struct hubbub *hubbub); + struct hubbub_perfmon_funcs { void (*reset)(struct hubbub *hubbub); void (*start_measuring_max_memory_latency_ns)( From 626d2f7027ec1b31235b79dc8d8f5efdfc6b9f2c Mon Sep 17 00:00:00 2001 From: Wenjing Liu Date: Tue, 4 Nov 2025 16:40:53 -0500 Subject: [PATCH 2526/2653] drm/amd/display: Refactor HDCP Status Log Format Add missing part for drm/amd/display: fw locality check refactors Reviewed-by: Aurabindo Pillai Signed-off-by: Wenjing Liu Signed-off-by: Fangzhi Zuo Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c index 409a7d0e70fab..5cb979c2cf8c4 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c @@ -126,7 +126,6 @@ void mod_hdcp_log_ddc_trace(struct mod_hdcp *hdcp) } #define CASE_FORMAT(entry) case entry: return #entry; - char *mod_hdcp_status_to_str(int32_t status) { switch (status) { From 5b1f9223d5758e628779506cc39dfc9a0ec91900 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 31 Oct 2025 19:00:47 -0400 Subject: [PATCH 2527/2653] drm/amd/display: [FW Promotion] Release 0.1.35.0 Summary for changes in firmware: * Use panel_inst instead of otg_inst when getting fw state * Contrast strength improves when HDR desktop mode * Ensure pipes have no outstanding HUBP requests prior to IPS RCG entry * Check for vm request and vm idle status in IPS1/2 entry sequence Reviewed-by: Aurabindo Pillai Signed-off-by: Taimur Hassan Signed-off-by: Fangzhi Zuo Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 067949d6eeb86..815b4ec82c118 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -491,7 +491,13 @@ union replay_debug_flags { */ uint32_t debug_log_enabled : 1; - uint32_t reserved : 17; + /** + * 0x8000 (bit 15) + * @enable_sub_feature_visual_confirm: Enable Sub Feature Visual Confirm + */ + uint32_t enable_sub_feature_visual_confirm : 1; + + uint32_t reserved : 16; } bitfields; uint32_t u32All; @@ -4363,6 +4369,7 @@ enum dmub_cmd_replay_general_subtype { REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, + REPLAY_GENERAL_CMD_VIDEO_CONFERENCING, }; struct dmub_alpm_auxless_data { From a790d916fef21502ac27757e96626e622edecb1f Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 31 Oct 2025 20:07:35 -0500 Subject: [PATCH 2528/2653] drm/amd/display: Promote DC to 3.2.358 Summary: * Enable VRR when unsynced with the stream * Refactor DSC cap calculation for dcn35 * Add debug log for power feature * Fix fill latency issue * Do not initialize LSDMA if it is not supported by DMU Reviewed-by: Aurabindo Pillai Signed-off-by: Taimur Hassan Signed-off-by: Fangzhi Zuo --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 833ec6369bf33..74737f00fabfc 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.357" +#define DC_VER "3.2.358" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From 68d121e8e14829d47f1bda661465af8719c9035c Mon Sep 17 00:00:00 2001 From: Sultan Alsawaf Date: Fri, 7 Nov 2025 13:07:13 -0500 Subject: [PATCH 2529/2653] drm/amd/amdgpu: Ensure isp_kernel_buffer_alloc() creates a new BO When the BO pointer provided to amdgpu_bo_create_kernel() points to non-NULL, amdgpu_bo_create_kernel() takes it as a hint to pin that address rather than allocate a new BO. This functionality is never desired for allocating ISP buffers. A new BO should always be created when isp_kernel_buffer_alloc() is called, per the description for isp_kernel_buffer_alloc(). Ensure this by zeroing *bo right before the amdgpu_bo_create_kernel() call. Fixes: 55d42f616976 ("drm/amd/amdgpu: Add helper functions for isp buffers") Reviewed-by: Mario Limonciello (AMD) Reviewed-by: Pratap Nirujogi Signed-off-by: Sultan Alsawaf --- drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c index 9cddbf50442a4..37270c4dab8dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c @@ -280,6 +280,8 @@ int isp_kernel_buffer_alloc(struct device *dev, u64 size, if (ret) return ret; + /* Ensure *bo is NULL so a new BO will be created */ + *bo = NULL; ret = amdgpu_bo_create_kernel(adev, size, ISP_MC_ADDR_ALIGN, From eb8949cd31134dffcfc952d9728554e2884f8500 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Fri, 7 Nov 2025 19:36:18 +0530 Subject: [PATCH 2530/2653] drm/amd/display: Fix annotations for connector poll/detect parameters MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds the missing @aconnector, @connector, and @force descriptions: @aconnector – This is the DM (Display Manager) connector. It gives access to the DRM connector, the DC link, and hotplug/poll state. The code uses it to check the link, update the sink, and manage connector state changes. @connector – This is the main DRM connector given by the DRM core. Inside the detect function, it is converted to amdgpu_dm_connector so we can run DC link detection, either light or full. @force – This flag tells the function whether to run a full detect again. If false, we avoid heavy DAC load detect steps to prevent flicker. If true, we force a re-detect even when we normally skip it. Fixes the below with gcc W=1: function param 'aconnector' not described in 'amdgpu_dm_connector_poll' function param 'force' not described in 'amdgpu_dm_connector_poll' function param 'connector' not described in 'amdgpu_dm_connector_detect' function param 'force' not described in 'amdgpu_dm_connector_detect' Cc: Aurabindo Pillai Cc: Roman Li Cc: Harry Wentland Cc: Tom Chung Signed-off-by: Srinivasan Shanmugam Reviewed-by: Aurabindo Pillai --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 22 ++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9d549526fd469..5d71c757d679f 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7361,10 +7361,18 @@ create_stream_for_sink(struct drm_connector *connector, } /** - * amdgpu_dm_connector_poll() - Poll a connector to see if it's connected to a display + * amdgpu_dm_connector_poll - Poll a connector to see if it's connected to a display + * @aconnector: DM connector to poll (owns @base drm_connector and @dc_link) + * @force: if true, force polling even when DAC load detection was used * - * Used for connectors that don't support HPD (hotplug detection) - * to periodically checked whether the connector is connected to a display. + * Used for connectors that don't support HPD (hotplug detection) to + * periodically check whether the connector is connected to a display. + * + * When connection was determined via DAC load detection, we avoid + * re-running it on normal polls to prevent visible glitches, unless + * @force is set. + * + * Return: The probed connector status (connected/disconnected/unknown). */ static enum drm_connector_status amdgpu_dm_connector_poll(struct amdgpu_dm_connector *aconnector, bool force) @@ -7432,6 +7440,14 @@ amdgpu_dm_connector_poll(struct amdgpu_dm_connector *aconnector, bool force) * 1. This interface is NOT called in context of HPD irq. * 2. This interface *is called* in context of user-mode ioctl. Which * makes it a bad place for *any* MST-related activity. + * + * @connector: The DRM connector we are checking. We convert it to + * amdgpu_dm_connector so we can read the DC link and state. + * @force: If true, do a full detect again. This is used even when + * a lighter check would normally be used to avoid flicker. + * + * Return: The connector status (connected, disconnected, or unknown). + * */ static enum drm_connector_status amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) From 781e112318eeccb165465bc5a880428783b9e173 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Fri, 7 Nov 2025 19:56:15 +0530 Subject: [PATCH 2531/2653] drm/amd/display: Add kdoc params/returns in dc/link detection helpers The link detection helpers in dc/link/link_detection.c were missing kdoc annotations for parameters and return values. Fixes the below with gcc W=1: ...link_detection.c:872 parameter 'edid_header' not described ...link_detection.c:890 parameter 'link' not described ...link_detection.c:914 parameter 'link' not described ...link_detection.c:1355 parameter 'link' not described ...link_detection.c:1355 parameter 'type' not described Cc: Aurabindo Pillai Cc: Roman Li Cc: Harry Wentland Cc: Tom Chung Signed-off-by: Srinivasan Shanmugam Reviewed-by: Aurabindo Pillai --- .../drm/amd/display/dc/link/link_detection.c | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index 5d287874c125d..d163360a2bf67 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -868,6 +868,11 @@ static void verify_link_capability(struct dc_link *link, struct dc_sink *sink, * Evaluates an 8-byte EDID header to check if it's good enough * for the purpose of determining whether a display is connected * without reading the full EDID. + * + * @edid_header: The first 8 bytes of the EDID read from DDC. + * + * Return: true if the header looks valid (>= 6 of 8 bytes match the + * expected 00/FF pattern), false otherwise. */ static bool link_detect_evaluate_edid_header(uint8_t edid_header[8]) { @@ -886,6 +891,11 @@ static bool link_detect_evaluate_edid_header(uint8_t edid_header[8]) * Detect whether a display is connected to DDC without reading full EDID. * Reads only the EDID header (the first 8 bytes of EDID) from DDC and * evaluates whether that matches. + * + * @link: DC link whose DDC/I2C is probed for the EDID header. + * + * Return: true if the EDID header was read and passes validation, + * false otherwise. */ static bool link_detect_ddc_probe(struct dc_link *link) { @@ -910,6 +920,11 @@ static bool link_detect_ddc_probe(struct dc_link *link) * Load detection can be used to detect the presence of an * analog display when we can't read DDC. This causes a visible * visual glitch so it should be used sparingly. + * + * @link: DC link to test using the DAC load-detect path. + * + * Return: true if the VBIOS load-detect call reports OK, false + * otherwise. */ static bool link_detect_dac_load_detect(struct dc_link *link) { @@ -1351,6 +1366,14 @@ static bool detect_link_and_local_sink(struct dc_link *link, /** * link_detect_analog() - Determines if an analog sink is connected. + * + * @link: DC link to evaluate (must support analog signalling). + * @type: Updated with the detected connection type: + * dc_connection_single (analog via DDC), + * dc_connection_dac_load (via load-detect), + * or dc_connection_none. + * + * Return: true if detection completed. */ static bool link_detect_analog(struct dc_link *link, enum dc_connection_type *type) { From 5f6d3d2408c020695fdedcf1507506d441b5d43d Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Sun, 19 Oct 2025 19:03:51 +0800 Subject: [PATCH 2532/2653] drm/amd/pm: Update pmfw headers for smu_v13_0_12 Update pmfw headers for smu_v13_0_12 to include ppt1 messages and static parameters Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- .../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h | 7 ++++++- .../gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h | 4 +++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h index fa43d2e229a09..dd30d96e1ca2d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h @@ -189,7 +189,7 @@ typedef enum { SVI_MAX_TEMP_ENTRIES, // 13 } SVI_TEMP_e; -#define SMU_METRICS_TABLE_VERSION 0x14 +#define SMU_METRICS_TABLE_VERSION 0x15 #define SMU_SYSTEM_METRICS_TABLE_VERSION 0x1 @@ -367,6 +367,11 @@ typedef struct { //Node Power Limit uint32_t MaxNodePowerLimit; + + // PPT1 Configuration + uint32_t PPT1Max; + uint32_t PPT1Min; + uint32_t PPT1Default; } StaticMetricsTable_t; #pragma pack(pop) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h index fe1b3ac50a75b..d09b6ae9827ef 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_ppsmc.h @@ -117,7 +117,9 @@ #define PPSMC_MSG_GetSystemMetricsTable 0x5C #define PPSMC_MSG_GetSystemMetricsVersion 0x5D #define PPSMC_MSG_ResetVCN 0x5E -#define PPSMC_Message_Count 0x5F +#define PPSMC_MSG_SetFastPptLimit 0x5F +#define PPSMC_MSG_GetFastPptLimit 0x60 +#define PPSMC_Message_Count 0x61 //PPSMC Reset Types for driver msg argument #define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET 0x1 From 9b17de840f1969306f4dfe76a6120a403938224c Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Sun, 19 Oct 2025 23:22:22 +0800 Subject: [PATCH 2533/2653] drm/amd/pm: Add ppt1 support for smu_v13_0_12 Add support to configure and retrieve ppt1 limit for smu_v13_0_12 v2: Add update_caps function and update ppt1 cap based on max ppt1 value, optimize the return values (Lijo) v3: Add Null ptr check, return not supported in case of invalid level/type (Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 4 +- .../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 8 ++ .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 80 ++++++++++++++++++- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 4 + 4 files changed, 92 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h index bd759b0990e42..45a52023deac8 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -293,7 +293,9 @@ __SMU_DUMMY_MAP(SetTimestamp), \ __SMU_DUMMY_MAP(GetTimestamp), \ __SMU_DUMMY_MAP(GetBadPageIpid), \ - __SMU_DUMMY_MAP(EraseRasTable), + __SMU_DUMMY_MAP(EraseRasTable), \ + __SMU_DUMMY_MAP(SetFastPptLimit), \ + __SMU_DUMMY_MAP(GetFastPptLimit), #undef __SMU_DUMMY_MAP #define __SMU_DUMMY_MAP(type) SMU_MSG_##type diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index fc580800609c0..9e635f733fbfd 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -148,6 +148,8 @@ const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[SMU_MSG_MAX_COUNT] = MSG_MAP(GetTimestamp, PPSMC_MSG_GetTimestamp, 0), MSG_MAP(GetBadPageIpid, PPSMC_MSG_GetBadPageIpIdLoHi, 0), MSG_MAP(EraseRasTable, PPSMC_MSG_EraseRasTable, 0), + MSG_MAP(SetFastPptLimit, PPSMC_MSG_SetFastPptLimit, 1), + MSG_MAP(GetFastPptLimit, PPSMC_MSG_GetFastPptLimit, 1), }; int smu_v13_0_12_tables_init(struct smu_context *smu) @@ -354,6 +356,12 @@ int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu) if (smu_v13_0_6_cap_supported(smu, SMU_CAP(NPM_METRICS))) pptable->MaxNodePowerLimit = SMUQ10_ROUND(static_metrics->MaxNodePowerLimit); + if (smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT)) && + static_metrics->PPT1Max) { + pptable->PPT1Max = static_metrics->PPT1Max; + pptable->PPT1Min = static_metrics->PPT1Min; + pptable->PPT1Default = static_metrics->PPT1Default; + } smu_v13_0_12_init_xgmi_data(smu, static_metrics); pptable->Init = true; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 188b968f4d25c..7bee4cab14acc 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -1006,6 +1006,17 @@ int smu_v13_0_6_get_static_metrics_table(struct smu_context *smu) return 0; } +static void smu_v13_0_6_update_caps(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct PPTable_t *pptable = + (struct PPTable_t *)smu_table->driver_pptable; + + if (smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT)) && + !pptable->PPT1Max) + smu_v13_0_6_cap_clear(smu, SMU_CAP(FAST_PPT)); +} + static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; @@ -1022,8 +1033,12 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu) uint8_t max_width; if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) && - smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) - return smu_v13_0_12_setup_driver_pptable(smu); + smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) { + ret = smu_v13_0_12_setup_driver_pptable(smu); + if (ret) + return ret; + goto out; + } /* Store one-time values in driver PPTable */ if (!pptable->Init) { @@ -1103,7 +1118,8 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu) smu_v13_0_6_fill_static_metrics_table(smu, static_metrics); } } - +out: + smu_v13_0_6_update_caps(smu); return 0; } @@ -2046,9 +2062,66 @@ static int smu_v13_0_6_set_power_limit(struct smu_context *smu, enum smu_ppt_limit_type limit_type, uint32_t limit) { + struct smu_table_context *smu_table = &smu->smu_table; + struct PPTable_t *pptable = + (struct PPTable_t *)smu_table->driver_pptable; + int ret; + + if (limit_type == SMU_FAST_PPT_LIMIT) { + if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT))) + return -EOPNOTSUPP; + if (limit > pptable->PPT1Max || limit < pptable->PPT1Min) { + dev_err(smu->adev->dev, + "New power limit (%d) should be between min %d max %d\n", + limit, pptable->PPT1Min, pptable->PPT1Max); + return -EINVAL; + } + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetFastPptLimit, + limit, NULL); + if (ret) + dev_err(smu->adev->dev, "Set fast PPT limit failed!\n"); + return ret; + } + return smu_v13_0_set_power_limit(smu, limit_type, limit); } +static int smu_v13_0_6_get_ppt_limit(struct smu_context *smu, + uint32_t *ppt_limit, + enum smu_ppt_limit_type type, + enum smu_ppt_limit_level level) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct PPTable_t *pptable = + (struct PPTable_t *)smu_table->driver_pptable; + int ret = 0; + + if (type == SMU_FAST_PPT_LIMIT) { + if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT))) + return -EOPNOTSUPP; + switch (level) { + case SMU_PPT_LIMIT_MAX: + *ppt_limit = pptable->PPT1Max; + break; + case SMU_PPT_LIMIT_CURRENT: + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPptLimit, ppt_limit); + if (ret) + dev_err(smu->adev->dev, "Get fast PPT limit failed!\n"); + break; + case SMU_PPT_LIMIT_DEFAULT: + *ppt_limit = pptable->PPT1Default; + break; + case SMU_PPT_LIMIT_MIN: + *ppt_limit = pptable->PPT1Min; + break; + default: + return -EOPNOTSUPP; + } + return ret; + } + return -EOPNOTSUPP; +} + static int smu_v13_0_6_irq_process(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) @@ -4130,6 +4203,7 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { .get_enabled_mask = smu_v13_0_6_get_enabled_mask, .feature_is_enabled = smu_cmn_feature_is_enabled, .set_power_limit = smu_v13_0_6_set_power_limit, + .get_ppt_limit = smu_v13_0_6_get_ppt_limit, .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate, .register_irq_handler = smu_v13_0_6_register_irq_handler, .enable_thermal_alert = smu_v13_0_enable_thermal_alert, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h index 367102cdbf093..6cbdd7c5ded9b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h @@ -50,6 +50,9 @@ struct PPTable_t { uint32_t MinLclkDpmRange; uint64_t PublicSerialNumber_AID; uint32_t MaxNodePowerLimit; + uint32_t PPT1Max; + uint32_t PPT1Min; + uint32_t PPT1Default; bool Init; }; @@ -73,6 +76,7 @@ enum smu_v13_0_6_caps { SMU_CAP(TEMP_METRICS), SMU_CAP(NPM_METRICS), SMU_CAP(RAS_EEPROM), + SMU_CAP(FAST_PPT), SMU_CAP(ALL), }; From 868da0543e1e9b9265a790aa59e5f1962bf9f701 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Mon, 20 Oct 2025 03:26:01 +0800 Subject: [PATCH 2534/2653] drm/amd/pm: Expose ppt1 limit for gc_v9_5_0 Expose power2_cap hwmon node for retrieving and configuring ppt1 limit on supported boards for gc_v9_5_0 v2: Remove version check (Lijo) v3: Remove power2_average (Lijo) v4: Put back power2_average, will be removed separately (Lijo) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 12 ++++++++---- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 ++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index a0500200266b8..360cdeabef28f 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -3373,7 +3373,9 @@ static ssize_t amdgpu_hwmon_show_power_label(struct device *dev, to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ? "fastPPT" : "slowPPT"); else - return sysfs_emit(buf, "PPT\n"); + return sysfs_emit(buf, "%s\n", + to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ? + "PPT1" : "PPT"); } static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, @@ -3826,13 +3828,15 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, return 0; /* only Vangogh has fast PPT limit and power labels */ - if (!(gc_ver == IP_VERSION(10, 3, 1)) && - (attr == &sensor_dev_attr_power2_average.dev_attr.attr || + if ((attr == &sensor_dev_attr_power2_average.dev_attr.attr || attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr || attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr || attr == &sensor_dev_attr_power2_cap.dev_attr.attr || attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr || - attr == &sensor_dev_attr_power2_label.dev_attr.attr)) + attr == &sensor_dev_attr_power2_label.dev_attr.attr) && + (amdgpu_dpm_get_power_limit(adev, &tmp, + PP_PWR_LIMIT_MAX, + PP_PWR_TYPE_FAST) == -EOPNOTSUPP)) return 0; return effective_mode; diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index e9fada94c8739..833e3e80453fd 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2941,6 +2941,8 @@ int smu_get_power_limit(void *handle, if (limit_type != SMU_DEFAULT_PPT_LIMIT) { if (smu->ppt_funcs->get_ppt_limit) ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); + else + return -EOPNOTSUPP; } else { switch (limit_level) { case SMU_PPT_LIMIT_CURRENT: From b007632dd07f2976abfbeafbc88859a9561f516e Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Mon, 20 Oct 2025 04:01:10 +0800 Subject: [PATCH 2535/2653] drm/amd/pm: Enable ppt1 caps for smu_v13_0_12 Enable ppt1 caps to fetch and configure ppt1 for smu_v13_0_12 Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 7bee4cab14acc..ed957c0cb4015 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -364,6 +364,9 @@ static void smu_v13_0_12_init_caps(struct smu_context *smu) if (fw_ver > 0x04560900) smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET)); + if (fw_ver >= 0x04560D00) + smu_v13_0_6_cap_set(smu, SMU_CAP(FAST_PPT)); + if (fw_ver >= 0x04560700) { if (fw_ver >= 0x04560900) { smu_v13_0_6_cap_set(smu, SMU_CAP(TEMP_METRICS)); From b375b48bf59c7ec7314245781aecc984513d4ac0 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Fri, 7 Nov 2025 00:56:32 +0800 Subject: [PATCH 2536/2653] drm/amd/pm: Remove power2_average node SOC power consumption is reported by power1_average. power2_cap_default/min/max only represent second level limits and don't represent a different type of power or power consumption by a subsection of the SOC. Therefore power2_average does not serve any purpose and hence removing power2_average sysfs node Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 360cdeabef28f..dd5c5cd6d2ab6 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -3580,7 +3580,6 @@ static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_m static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0); static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0); static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0); -static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1); static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1); static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1); static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1); @@ -3629,7 +3628,6 @@ static struct attribute *hwmon_attributes[] = { &sensor_dev_attr_power1_cap.dev_attr.attr, &sensor_dev_attr_power1_cap_default.dev_attr.attr, &sensor_dev_attr_power1_label.dev_attr.attr, - &sensor_dev_attr_power2_average.dev_attr.attr, &sensor_dev_attr_power2_cap_max.dev_attr.attr, &sensor_dev_attr_power2_cap_min.dev_attr.attr, &sensor_dev_attr_power2_cap.dev_attr.attr, @@ -3828,8 +3826,7 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, return 0; /* only Vangogh has fast PPT limit and power labels */ - if ((attr == &sensor_dev_attr_power2_average.dev_attr.attr || - attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr || + if ((attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr || attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr || attr == &sensor_dev_attr_power2_cap.dev_attr.attr || attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr || From 4e996e1b2eb745ddaf6903c52d4671ac902ea044 Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Tue, 7 Oct 2025 13:17:51 +0530 Subject: [PATCH 2537/2653] drm/amdgpu/jpeg: Add parse_cs for JPEG5_0_1 enable parse_cs callback for JPEG5_0_1. Signed-off-by: Sathishkumar S Reviewed-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c index baf097d2e1ac9..ab0bf880d3d8a 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c @@ -878,6 +878,7 @@ static const struct amdgpu_ring_funcs jpeg_v5_0_1_dec_ring_vm_funcs = { .get_rptr = jpeg_v5_0_1_dec_ring_get_rptr, .get_wptr = jpeg_v5_0_1_dec_ring_get_wptr, .set_wptr = jpeg_v5_0_1_dec_ring_set_wptr, + .parse_cs = amdgpu_jpeg_dec_parse_cs, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + From c38d92164aa59b9f1d0749df7ace7e015630de63 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Fri, 7 Nov 2025 19:19:08 +0800 Subject: [PATCH 2538/2653] drm/amdgpu: resume MES scheduling after user queue hang detection and recovery This patch ensures the Micro-Engine Scheduler (MES) is properly resumed after detecting and recovering from a user queue hang condition. Key changes: 1. Track when a hung user queue is detected using found_hung_queue flag 2. Call amdgpu_mes_resume() to restart MES scheduling after completing the hang recovery process 3. This complements the existing recovery steps (fence force completion and device wedging) by ensuring the scheduler can process new work Without this resume call, the MES scheduler may remain in a paused state even after the hung queue has been handled, preventing newly submitted work from being processed and leading to system stalls. Acked-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index b1ee9473d6280..64cae89357b65 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -208,6 +208,7 @@ static int mes_userq_detect_and_reset(struct amdgpu_device *adev, unsigned int hung_db_num = 0; unsigned long queue_id; u32 db_array[8]; + bool found_hung_queue = false; int r, i; if (db_array_size > 8) { @@ -232,6 +233,7 @@ static int mes_userq_detect_and_reset(struct amdgpu_device *adev, for (i = 0; i < hung_db_num; i++) { if (queue->doorbell_index == db_array[i]) { queue->state = AMDGPU_USERQ_STATE_HUNG; + found_hung_queue = true; atomic_inc(&adev->gpu_reset_counter); amdgpu_userq_fence_driver_force_completion(queue); drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, NULL); @@ -241,6 +243,11 @@ static int mes_userq_detect_and_reset(struct amdgpu_device *adev, } } + if (found_hung_queue) { + /* Resume scheduling after hang recovery */ + r = amdgpu_mes_resume(adev); + } + return r; } From 5a7273be0b7f5d9fb3205f6673435529de20f4f7 Mon Sep 17 00:00:00 2001 From: Jiapeng Chong Date: Thu, 6 Nov 2025 09:47:47 +0800 Subject: [PATCH 2539/2653] drm/amdgpu/userqueue: Remove duplicate amdgpu_reset.h header ./drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c: amdgpu_reset.h is included more than once. Reported-by: Abaci Robot Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=26930 Signed-off-by: Jiapeng Chong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 3da606b9b9eb5..fb4bae73e822d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -32,7 +32,6 @@ #include "amdgpu_vm.h" #include "amdgpu_userq.h" #include "amdgpu_hmm.h" -#include "amdgpu_reset.h" #include "amdgpu_userq_fence.h" u32 amdgpu_userq_get_supported_ip_mask(struct amdgpu_device *adev) From 7e3fdedff1ff1edac473c0a28e99ea3f2489ab6e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 7 Nov 2025 16:57:34 +0100 Subject: [PATCH 2540/2653] drm/amdgpu/gmc6: Place gart at low address range MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of using a best-fit algorithm to determine which part of the VMID 0 address space to use for GART, always use the low address range. A subsequent commit will use this to map the VCPU BO in GART for the VCE1 IP block. Split this into a separate patch to make it easier to bisect, in case there are any errors in the future. Signed-off-by: Timur Kristóf Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 41eedb6d1628f..72532b5bfb987 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -212,7 +212,7 @@ static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, base <<= 24; amdgpu_gmc_vram_location(adev, mc, base); - amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); + amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_LOW); } static void gmc_v6_0_mc_program(struct amdgpu_device *adev) From 16e71eab419222c0b7e1b481c0efc9fa28568bbe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 7 Nov 2025 16:57:35 +0100 Subject: [PATCH 2541/2653] drm/amdgpu/gart: Add helper to bind VRAM pages (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Binds pages that located in VRAM to the GART page table. Useful when a kernel BO is located in VRAM but needs to be accessed from the GART address space, for example to give a kernel BO a 32-bit address when GART is placed in LOW address space. v2: - Refactor function to be more reusable Signed-off-by: Timur Kristóf Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 36 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h | 3 ++ 2 files changed, 39 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index 83f3b94ed975a..d2237ce9da70e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -367,6 +367,42 @@ void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, drm_dev_exit(idx); } +/** + * amdgpu_gart_map_vram_range - map VRAM pages into the GART page table + * + * @adev: amdgpu_device pointer + * @pa: physical address of the first page to be mapped + * @start_page: first page to map in the GART aperture + * @num_pages: number of pages to be mapped + * @flags: page table entry flags + * @dst: CPU address of the GART table + * + * Binds a BO that is allocated in VRAM to the GART page table + * (all ASICs). + * + * Useful when a kernel BO is located in VRAM but + * needs to be accessed from the GART address space. + */ +void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa, + uint64_t start_page, uint64_t num_pages, + uint64_t flags, void *dst) +{ + u32 i, idx; + + /* The SYSTEM flag indicates the pages aren't in VRAM. */ + WARN_ON_ONCE(flags & AMDGPU_PTE_SYSTEM); + + if (!drm_dev_enter(adev_to_drm(adev), &idx)) + return; + + for (i = 0; i < num_pages; ++i) { + amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr, + start_page + i, pa + AMDGPU_GPU_PAGE_SIZE * i, flags); + } + + drm_dev_exit(idx); +} + /** * amdgpu_gart_bind - bind pages into the gart page table * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h index 7cc980bf4725d..d3118275ddae8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h @@ -64,5 +64,8 @@ void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, void *dst); void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, int pages, dma_addr_t *dma_addr, uint64_t flags); +void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa, + uint64_t start_page, uint64_t num_pages, + uint64_t flags, void *dst); void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev); #endif From cfdc90b13f306b8f80b76a9f646ce89cfa830ad3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Sun, 9 Nov 2025 19:26:40 +0100 Subject: [PATCH 2542/2653] drm/amdgpu: Use DC by default on SI dGPUs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that DC supports analog connectors, it has reached feature parity with the legacy non-DC display driver on SI dGPUs. Use the DC display driver by default on SI dGPUs, unless it is explicitly disabled using the amdgpu.dc=0 module parameter. DC brings proper support for DP/HDMI audio, DP MST, 10-bit colors, some HDR features, atomic modesetting, etc. Also clarify the comment about what is missing to have full DC support for CIK APUs. Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index eca11fbc637ad..b94bfbbf621b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4274,24 +4274,13 @@ bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, case CHIP_PITCAIRN: case CHIP_VERDE: case CHIP_OLAND: - /* - * We have systems in the wild with these ASICs that require - * LVDS and VGA support which is not supported with DC. - * - * Fallback to the non-DC driver here by default so as not to - * cause regressions. - */ -#if defined(CONFIG_DRM_AMD_DC_SI) - return amdgpu_dc > 0; -#else - return false; -#endif + return amdgpu_dc != 0 && IS_ENABLED(CONFIG_DRM_AMD_DC_SI); case CHIP_KAVERI: case CHIP_KABINI: case CHIP_MULLINS: /* * We have systems in the wild with these ASICs that require - * VGA support which is not supported with DC. + * TRAVIS and NUTMEG support which is not supported with DC. * * Fallback to the non-DC driver here by default so as not to * cause regressions. From 8c009634cc12d250a40d4fd3a8291e22e797c157 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Thu, 6 Nov 2025 10:17:06 -0500 Subject: [PATCH 2543/2653] drm/amdkfd: relax checks for over allocation of save area Over allocation of save area is not fatal, only under allocation is. ROCm has various components that independently claim authority over save area size. Unless KFD decides to claim single authority, relax size checks. Signed-off-by: Jonathan Kim Reviewed-by: Philip Yang --- drivers/gpu/drm/amd/amdkfd/kfd_queue.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_queue.c index a65c67cf56ff3..f1e7583650c41 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_queue.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_queue.c @@ -297,16 +297,16 @@ int kfd_queue_acquire_buffers(struct kfd_process_device *pdd, struct queue_prope goto out_err_unreserve; } - if (properties->ctx_save_restore_area_size != topo_dev->node_props.cwsr_size) { - pr_debug("queue cwsr size 0x%x not equal to node cwsr size 0x%x\n", + if (properties->ctx_save_restore_area_size < topo_dev->node_props.cwsr_size) { + pr_debug("queue cwsr size 0x%x not sufficient for node cwsr size 0x%x\n", properties->ctx_save_restore_area_size, topo_dev->node_props.cwsr_size); err = -EINVAL; goto out_err_unreserve; } - total_cwsr_size = (topo_dev->node_props.cwsr_size + topo_dev->node_props.debug_memory_size) - * NUM_XCC(pdd->dev->xcc_mask); + total_cwsr_size = (properties->ctx_save_restore_area_size + + topo_dev->node_props.debug_memory_size) * NUM_XCC(pdd->dev->xcc_mask); total_cwsr_size = ALIGN(total_cwsr_size, PAGE_SIZE); err = kfd_queue_buffer_get(vm, (void *)properties->ctx_save_restore_area_address, @@ -352,8 +352,8 @@ int kfd_queue_release_buffers(struct kfd_process_device *pdd, struct queue_prope topo_dev = kfd_topology_device_by_id(pdd->dev->id); if (!topo_dev) return -EINVAL; - total_cwsr_size = (topo_dev->node_props.cwsr_size + topo_dev->node_props.debug_memory_size) - * NUM_XCC(pdd->dev->xcc_mask); + total_cwsr_size = (properties->ctx_save_restore_area_size + + topo_dev->node_props.debug_memory_size) * NUM_XCC(pdd->dev->xcc_mask); total_cwsr_size = ALIGN(total_cwsr_size, PAGE_SIZE); kfd_queue_buffer_svm_put(pdd, properties->ctx_save_restore_area_address, total_cwsr_size); From 58f86d18a44ff7582aac5d2c059e45a6068af9e7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 7 Nov 2025 16:57:36 +0100 Subject: [PATCH 2544/2653] drm/amdgpu/ttm: Use GART helper to map VRAM pages (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the GART helper function introduced in the previous commit to map the VRAM pages of the transfer window to GART. No functional changes, just code cleanup. Split this into a separate commit to make it easier to bisect, in case there are problems in the future. Signed-off-by: Timur Kristóf Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index a681be90a3033..93666b02c39ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -218,7 +218,6 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, struct amdgpu_job *job; void *cpu_addr; uint64_t flags; - unsigned int i; int r; BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < @@ -284,16 +283,9 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT]; amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr); } else { - dma_addr_t dma_address; - - dma_address = mm_cur->start; - dma_address += adev->vm_manager.vram_base_offset; + u64 pa = mm_cur->start + adev->vm_manager.vram_base_offset; - for (i = 0; i < num_pages; ++i) { - amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, &dma_address, - flags, cpu_addr); - dma_address += PAGE_SIZE; - } + amdgpu_gart_map_vram_range(adev, pa, 0, num_pages, flags, cpu_addr); } dma_fence_put(amdgpu_job_submit(job)); From 787c379f056813bd991df4af77f9686f93269402 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 7 Nov 2025 16:57:37 +0100 Subject: [PATCH 2545/2653] drm/amdgpu/vce: Move firmware load to amdgpu_vce_early_init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Try to load the VCE firmware at early_init. When the correct firmware is not found, return -ENOENT. This way, the driver initialization will complete even without VCE, and the GPU will be functional, albeit without video encoding capabilities. This is necessary because we are planning to add support for the VCE1, and AMD hasn't yet publised the correct firmware for this version. So we need to anticipate that users will try to boot amdgpu on SI GPUs without the correct VCE1 firmware present on their system. Signed-off-by: Timur Kristóf Reviewed-by: Christian König Reviewed-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 121 +++++++++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 1 + drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 5 + drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 5 + drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 5 + 5 files changed, 91 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index b9060bcd48064..c4e9d18621087 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -88,82 +88,87 @@ static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, bool direct, struct dma_fence **fence); /** - * amdgpu_vce_sw_init - allocate memory, load vce firmware + * amdgpu_vce_firmware_name() - determine the firmware file name for VCE * * @adev: amdgpu_device pointer - * @size: size for the new BO * - * First step to get VCE online, allocate memory and load the firmware + * Each chip that has VCE IP may need a different firmware. + * This function returns the name of the VCE firmware file + * appropriate for the current chip. */ -int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) +static const char *amdgpu_vce_firmware_name(struct amdgpu_device *adev) { - const char *fw_name; - const struct common_firmware_header *hdr; - unsigned int ucode_version, version_major, version_minor, binary_id; - int i, r; - switch (adev->asic_type) { #ifdef CONFIG_DRM_AMDGPU_CIK case CHIP_BONAIRE: - fw_name = FIRMWARE_BONAIRE; - break; + return FIRMWARE_BONAIRE; case CHIP_KAVERI: - fw_name = FIRMWARE_KAVERI; - break; + return FIRMWARE_KAVERI; case CHIP_KABINI: - fw_name = FIRMWARE_KABINI; - break; + return FIRMWARE_KABINI; case CHIP_HAWAII: - fw_name = FIRMWARE_HAWAII; - break; + return FIRMWARE_HAWAII; case CHIP_MULLINS: - fw_name = FIRMWARE_MULLINS; - break; + return FIRMWARE_MULLINS; #endif case CHIP_TONGA: - fw_name = FIRMWARE_TONGA; - break; + return FIRMWARE_TONGA; case CHIP_CARRIZO: - fw_name = FIRMWARE_CARRIZO; - break; + return FIRMWARE_CARRIZO; case CHIP_FIJI: - fw_name = FIRMWARE_FIJI; - break; + return FIRMWARE_FIJI; case CHIP_STONEY: - fw_name = FIRMWARE_STONEY; - break; + return FIRMWARE_STONEY; case CHIP_POLARIS10: - fw_name = FIRMWARE_POLARIS10; - break; + return FIRMWARE_POLARIS10; case CHIP_POLARIS11: - fw_name = FIRMWARE_POLARIS11; - break; + return FIRMWARE_POLARIS11; case CHIP_POLARIS12: - fw_name = FIRMWARE_POLARIS12; - break; + return FIRMWARE_POLARIS12; case CHIP_VEGAM: - fw_name = FIRMWARE_VEGAM; - break; + return FIRMWARE_VEGAM; case CHIP_VEGA10: - fw_name = FIRMWARE_VEGA10; - break; + return FIRMWARE_VEGA10; case CHIP_VEGA12: - fw_name = FIRMWARE_VEGA12; - break; + return FIRMWARE_VEGA12; case CHIP_VEGA20: - fw_name = FIRMWARE_VEGA20; - break; + return FIRMWARE_VEGA20; default: - return -EINVAL; + return NULL; } +} + +/** + * amdgpu_vce_early_init() - try to load VCE firmware + * + * @adev: amdgpu_device pointer + * + * Tries to load the VCE firmware. + * + * When not found, returns ENOENT so that the driver can + * still load and initialize the rest of the IP blocks. + * The GPU can function just fine without VCE, they will just + * not support video encoding. + */ +int amdgpu_vce_early_init(struct amdgpu_device *adev) +{ + const char *fw_name = amdgpu_vce_firmware_name(adev); + const struct common_firmware_header *hdr; + unsigned int ucode_version, version_major, version_minor, binary_id; + int r; + + if (!fw_name) + return -ENOENT; r = amdgpu_ucode_request(adev, &adev->vce.fw, AMDGPU_UCODE_REQUIRED, "%s", fw_name); if (r) { - dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n", - fw_name); + dev_err(adev->dev, + "amdgpu_vce: Firmware \"%s\" not found or failed to validate (%d)\n", + fw_name, r); + amdgpu_ucode_release(&adev->vce.fw); - return r; + return -ENOENT; } hdr = (const struct common_firmware_header *)adev->vce.fw->data; @@ -172,11 +177,35 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) version_major = (ucode_version >> 20) & 0xfff; version_minor = (ucode_version >> 8) & 0xfff; binary_id = ucode_version & 0xff; - DRM_INFO("Found VCE firmware Version: %d.%d Binary ID: %d\n", + dev_info(adev->dev, "Found VCE firmware Version: %d.%d Binary ID: %d\n", version_major, version_minor, binary_id); adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) | (binary_id << 8)); + return 0; +} + +/** + * amdgpu_vce_sw_init() - allocate memory for VCE BO + * + * @adev: amdgpu_device pointer + * @size: size for the new BO + * + * First step to get VCE online: allocate memory for VCE BO. + * The VCE firmware binary is copied into the VCE BO later, + * in amdgpu_vce_resume. The VCE executes its code from the + * VCE BO and also uses the space in this BO for its stack and data. + * + * Ideally this BO should be placed in VRAM for optimal performance, + * although technically it also runs from system RAM (albeit slowly). + */ +int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) +{ + int i, r; + + if (!adev->vce.fw) + return -ENOENT; + r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h index 6e53f872d084a..22acd7b359451 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h @@ -53,6 +53,7 @@ struct amdgpu_vce { unsigned num_rings; }; +int amdgpu_vce_early_init(struct amdgpu_device *adev); int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size); int amdgpu_vce_sw_fini(struct amdgpu_device *adev); int amdgpu_vce_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index bee3e904a6bc7..8ea8a6193492f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -407,6 +407,11 @@ static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable, static int vce_v2_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; + int r; + + r = amdgpu_vce_early_init(adev); + if (r) + return r; adev->vce.num_rings = 2; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 708123899c416..719e9643c43d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -399,6 +399,7 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev) static int vce_v3_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; + int r; adev->vce.harvest_config = vce_v3_0_get_harvest_config(adev); @@ -407,6 +408,10 @@ static int vce_v3_0_early_init(struct amdgpu_ip_block *ip_block) (AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1)) return -ENOENT; + r = amdgpu_vce_early_init(adev); + if (r) + return r; + adev->vce.num_rings = 3; vce_v3_0_set_ring_funcs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 335bda64ff5bc..2d64002bed61f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -410,6 +410,11 @@ static int vce_v4_0_stop(struct amdgpu_device *adev) static int vce_v4_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; + int r; + + r = amdgpu_vce_early_init(adev); + if (r) + return r; if (amdgpu_sriov_vf(adev)) /* currently only VCN0 support SRIOV */ adev->vce.num_rings = 1; From f774d0b72cfd4b07d71dcfe3d3d8e6ba92eb3351 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 7 Nov 2025 16:57:38 +0100 Subject: [PATCH 2546/2653] drm/amdgpu/vce: Clear VCPU BO, don't unmap/unreserve (v4) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The VCPU BO doesn't only contain the VCE firmware but also other ranges that the VCE uses for its stack and data. Let's initialize this to zero to avoid having garbage in the VCPU BO. Additionally, don't unmap/unreserve the VCPU BO. The VCPU BO needs to stay at the same location before and after sleep/resume because the FW code is not relocatable once it's started. Signed-off-by: Timur Kristóf Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 23 +++-------------------- 1 file changed, 3 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index c4e9d18621087..3a986e3589a5c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -314,40 +314,23 @@ int amdgpu_vce_suspend(struct amdgpu_device *adev) */ int amdgpu_vce_resume(struct amdgpu_device *adev) { - void *cpu_addr; const struct common_firmware_header *hdr; unsigned int offset; - int r, idx; + int idx; if (adev->vce.vcpu_bo == NULL) return -EINVAL; - r = amdgpu_bo_reserve(adev->vce.vcpu_bo, false); - if (r) { - dev_err(adev->dev, "(%d) failed to reserve VCE bo\n", r); - return r; - } - - r = amdgpu_bo_kmap(adev->vce.vcpu_bo, &cpu_addr); - if (r) { - amdgpu_bo_unreserve(adev->vce.vcpu_bo); - dev_err(adev->dev, "(%d) VCE map failed\n", r); - return r; - } - hdr = (const struct common_firmware_header *)adev->vce.fw->data; offset = le32_to_cpu(hdr->ucode_array_offset_bytes); if (drm_dev_enter(adev_to_drm(adev), &idx)) { - memcpy_toio(cpu_addr, adev->vce.fw->data + offset, + memset_io(adev->vce.cpu_addr, 0, amdgpu_bo_size(adev->vce.vcpu_bo)); + memcpy_toio(adev->vce.cpu_addr, adev->vce.fw->data + offset, adev->vce.fw->size - offset); drm_dev_exit(idx); } - amdgpu_bo_kunmap(adev->vce.vcpu_bo); - - amdgpu_bo_unreserve(adev->vce.vcpu_bo); - return 0; } From 7695aef5ee8bbd4ddb0533b8b9c8872754998a31 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 7 Nov 2025 16:57:39 +0100 Subject: [PATCH 2547/2653] drm/amdgpu/vce1: Clean up register definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The sid.h header contained some VCE1 register definitions, but they were using byte offsets (probably copied from the old radeon driver). Move all of these to the proper VCE1 headers and ensure they are in dword offsets. Also add the register definitions that we need for the firmware validation mechanism in VCE1. Signed-off-by: Timur Kristóf Co-developed-by: Alexandre Demers Signed-off-by: Alexandre Demers Acked-by: Christian König --- drivers/gpu/drm/amd/amdgpu/sid.h | 40 ------------------- .../drm/amd/include/asic_reg/vce/vce_1_0_d.h | 5 +++ .../include/asic_reg/vce/vce_1_0_sh_mask.h | 10 +++++ 3 files changed, 15 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h b/drivers/gpu/drm/amd/amdgpu/sid.h index cbd4f8951cfae..561462a8332e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/sid.h +++ b/drivers/gpu/drm/amd/amdgpu/sid.h @@ -582,45 +582,6 @@ #define DMA_PACKET_NOP 0xf /* VCE */ -#define VCE_STATUS 0x20004 -#define VCE_VCPU_CNTL 0x20014 -#define VCE_CLK_EN (1 << 0) -#define VCE_VCPU_CACHE_OFFSET0 0x20024 -#define VCE_VCPU_CACHE_SIZE0 0x20028 -#define VCE_VCPU_CACHE_OFFSET1 0x2002c -#define VCE_VCPU_CACHE_SIZE1 0x20030 -#define VCE_VCPU_CACHE_OFFSET2 0x20034 -#define VCE_VCPU_CACHE_SIZE2 0x20038 -#define VCE_SOFT_RESET 0x20120 -#define VCE_ECPU_SOFT_RESET (1 << 0) -#define VCE_FME_SOFT_RESET (1 << 2) -#define VCE_RB_BASE_LO2 0x2016c -#define VCE_RB_BASE_HI2 0x20170 -#define VCE_RB_SIZE2 0x20174 -#define VCE_RB_RPTR2 0x20178 -#define VCE_RB_WPTR2 0x2017c -#define VCE_RB_BASE_LO 0x20180 -#define VCE_RB_BASE_HI 0x20184 -#define VCE_RB_SIZE 0x20188 -#define VCE_RB_RPTR 0x2018c -#define VCE_RB_WPTR 0x20190 -#define VCE_CLOCK_GATING_A 0x202f8 -#define VCE_CLOCK_GATING_B 0x202fc -#define VCE_UENC_CLOCK_GATING 0x205bc -#define VCE_UENC_REG_CLOCK_GATING 0x205c0 -#define VCE_FW_REG_STATUS 0x20e10 -# define VCE_FW_REG_STATUS_BUSY (1 << 0) -# define VCE_FW_REG_STATUS_PASS (1 << 3) -# define VCE_FW_REG_STATUS_DONE (1 << 11) -#define VCE_LMI_FW_START_KEYSEL 0x20e18 -#define VCE_LMI_FW_PERIODIC_CTRL 0x20e20 -#define VCE_LMI_CTRL2 0x20e74 -#define VCE_LMI_CTRL 0x20e98 -#define VCE_LMI_VM_CTRL 0x20ea0 -#define VCE_LMI_SWAP_CNTL 0x20eb4 -#define VCE_LMI_SWAP_CNTL1 0x20eb8 -#define VCE_LMI_CACHE_CTRL 0x20ef4 - #define VCE_CMD_NO_OP 0x00000000 #define VCE_CMD_END 0x00000001 #define VCE_CMD_IB 0x00000002 @@ -629,7 +590,6 @@ #define VCE_CMD_IB_AUTO 0x00000005 #define VCE_CMD_SEMAPHORE 0x00000006 - //#dce stupp /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) //(0x6df0 - 0x6df0)/4 diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h index 2176548e9203b..9778822dd2a07 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_d.h @@ -60,5 +60,10 @@ #define mmVCE_VCPU_CACHE_SIZE1 0x800C #define mmVCE_VCPU_CACHE_SIZE2 0x800E #define mmVCE_VCPU_CNTL 0x8005 +#define mmVCE_VCPU_SCRATCH7 0x8037 +#define mmVCE_FW_REG_STATUS 0x8384 +#define mmVCE_LMI_FW_PERIODIC_CTRL 0x8388 +#define mmVCE_LMI_FW_START_KEYSEL 0x8386 + #endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h index ea5b26b11cb14..1f82d6f5abdec 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_1_0_sh_mask.h @@ -61,6 +61,8 @@ #define VCE_RB_WPTR__RB_WPTR__SHIFT 0x00000004 #define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x00000001L #define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x00000000 +#define VCE_SOFT_RESET__FME_SOFT_RESET_MASK 0x00000004L +#define VCE_SOFT_RESET__FME_SOFT_RESET__SHIFT 0x00000002 #define VCE_STATUS__JOB_BUSY_MASK 0x00000001L #define VCE_STATUS__JOB_BUSY__SHIFT 0x00000000 #define VCE_STATUS__UENC_BUSY_MASK 0x00000100L @@ -95,5 +97,13 @@ #define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x00000000 #define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00040000L #define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x00000012 +#define VCE_CLOCK_GATING_A__CGC_DYN_CLOCK_MODE_MASK 0x00010000 +#define VCE_CLOCK_GATING_A__CGC_DYN_CLOCK_MODE_SHIFT 0x00000010 +#define VCE_FW_REG_STATUS__BUSY_MASK 0x0000001 +#define VCE_FW_REG_STATUS__BUSY__SHIFT 0x0000001 +#define VCE_FW_REG_STATUS__PASS_MASK 0x0000008 +#define VCE_FW_REG_STATUS__PASS__SHIFT 0x0000003 +#define VCE_FW_REG_STATUS__DONE_MASK 0x0000800 +#define VCE_FW_REG_STATUS__DONE__SHIFT 0x000000b #endif From 27bbfc8a3a0c38bf995704c0b69c3321ab071fd1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 7 Nov 2025 16:57:40 +0100 Subject: [PATCH 2548/2653] drm/amdgpu/vce1: Load VCE1 firmware MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Load VCE1 firmware using amdgpu_ucode_request, just like it is done for other VCE versions. All SI chips share the same VCE1 firmware file: vce_1_0_0.bin which will be sent to linux-firmware soon. Signed-off-by: Timur Kristóf Co-developed-by: Alexandre Demers Signed-off-by: Alexandre Demers Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 3a986e3589a5c..7fead2eebd362 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -41,6 +41,9 @@ #define VCE_IDLE_TIMEOUT msecs_to_jiffies(1000) /* Firmware Names */ +#ifdef CONFIG_DRM_AMDGPU_SI +#define FIRMWARE_VCE_V1_0 "amdgpu/vce_1_0_0.bin" +#endif #ifdef CONFIG_DRM_AMDGPU_CIK #define FIRMWARE_BONAIRE "amdgpu/bonaire_vce.bin" #define FIRMWARE_KABINI "amdgpu/kabini_vce.bin" @@ -61,6 +64,9 @@ #define FIRMWARE_VEGA12 "amdgpu/vega12_vce.bin" #define FIRMWARE_VEGA20 "amdgpu/vega20_vce.bin" +#ifdef CONFIG_DRM_AMDGPU_SI +MODULE_FIRMWARE(FIRMWARE_VCE_V1_0); +#endif #ifdef CONFIG_DRM_AMDGPU_CIK MODULE_FIRMWARE(FIRMWARE_BONAIRE); MODULE_FIRMWARE(FIRMWARE_KABINI); @@ -99,6 +105,12 @@ static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, static const char *amdgpu_vce_firmware_name(struct amdgpu_device *adev) { switch (adev->asic_type) { +#ifdef CONFIG_DRM_AMDGPU_SI + case CHIP_PITCAIRN: + case CHIP_TAHITI: + case CHIP_VERDE: + return FIRMWARE_VCE_V1_0; +#endif #ifdef CONFIG_DRM_AMDGPU_CIK case CHIP_BONAIRE: return FIRMWARE_BONAIRE; From 44fef0bf6312097453181c9b98689a9dcbf4cdbc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 7 Nov 2025 16:57:41 +0100 Subject: [PATCH 2549/2653] drm/amdgpu/vce1: Implement VCE1 IP block (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement the necessary functionality to support the VCE1. This implementation is based on: - VCE2 code from amdgpu - VCE1 code from radeon (the old driver) - Some trial and error A subsequent commit will ensure correct mapping for the VCPU BO, which will make this actually work. v2: - Use memset_io more. - Use memcpy_toio more. - Remove __func__ from warnings. - Don't reserve and map the VCPU BO anymore. - Add empty line to multi-line comments Signed-off-by: Timur Kristóf Co-developed-by: Alexandre Demers Signed-off-by: Alexandre Demers Acked-by: Christian König --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 1 + drivers/gpu/drm/amd/amdgpu/vce_v1_0.c | 784 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/vce_v1_0.h | 32 + 4 files changed, 818 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v1_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v1_0.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 2aea62e324ff0..9d2038ca34e56 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -78,7 +78,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o \ dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o \ - uvd_v3_1.o + uvd_v3_1.o vce_v1_0.o amdgpu-y += \ vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h index 22acd7b359451..0507838026231 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h @@ -51,6 +51,7 @@ struct amdgpu_vce { struct drm_sched_entity entity; uint32_t srbm_soft_reset; unsigned num_rings; + uint32_t keyselect; }; int amdgpu_vce_early_init(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c new file mode 100644 index 0000000000000..bf9f943852cbc --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c @@ -0,0 +1,784 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2013 Advanced Micro Devices, Inc. + * Copyright 2025 Valve Corporation + * Copyright 2025 Alexandre Demers + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * Authors: Christian König + * Timur Kristóf + * Alexandre Demers + */ + +#include + +#include "amdgpu.h" +#include "amdgpu_vce.h" +#include "sid.h" +#include "vce_v1_0.h" +#include "vce/vce_1_0_d.h" +#include "vce/vce_1_0_sh_mask.h" +#include "oss/oss_1_0_d.h" +#include "oss/oss_1_0_sh_mask.h" + +#define VCE_V1_0_FW_SIZE (256 * 1024) +#define VCE_V1_0_STACK_SIZE (64 * 1024) +#define VCE_V1_0_DATA_SIZE (7808 * (AMDGPU_MAX_VCE_HANDLES + 1)) +#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02 + +static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev); +static void vce_v1_0_set_irq_funcs(struct amdgpu_device *adev); + +struct vce_v1_0_fw_signature { + int32_t offset; + uint32_t length; + int32_t number; + struct { + uint32_t chip_id; + uint32_t keyselect; + uint32_t nonce[4]; + uint32_t sigval[4]; + } val[8]; +}; + +/** + * vce_v1_0_ring_get_rptr - get read pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware read pointer + */ +static uint64_t vce_v1_0_ring_get_rptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring->me == 0) + return RREG32(mmVCE_RB_RPTR); + else + return RREG32(mmVCE_RB_RPTR2); +} + +/** + * vce_v1_0_ring_get_wptr - get write pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware write pointer + */ +static uint64_t vce_v1_0_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring->me == 0) + return RREG32(mmVCE_RB_WPTR); + else + return RREG32(mmVCE_RB_WPTR2); +} + +/** + * vce_v1_0_ring_set_wptr - set write pointer + * + * @ring: amdgpu_ring pointer + * + * Commits the write pointer to the hardware + */ +static void vce_v1_0_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring->me == 0) + WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); + else + WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); +} + +static int vce_v1_0_lmi_clean(struct amdgpu_device *adev) +{ + int i, j; + + for (i = 0; i < 10; ++i) { + for (j = 0; j < 100; ++j) { + if (RREG32(mmVCE_LMI_STATUS) & 0x337f) + return 0; + + mdelay(10); + } + } + + return -ETIMEDOUT; +} + +static int vce_v1_0_firmware_loaded(struct amdgpu_device *adev) +{ + int i, j; + + for (i = 0; i < 10; ++i) { + for (j = 0; j < 100; ++j) { + if (RREG32(mmVCE_STATUS) & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK) + return 0; + mdelay(10); + } + + dev_err(adev->dev, "VCE not responding, trying to reset the ECPU\n"); + + WREG32_P(mmVCE_SOFT_RESET, + VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + mdelay(10); + WREG32_P(mmVCE_SOFT_RESET, 0, + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); + mdelay(10); + } + + return -ETIMEDOUT; +} + +static void vce_v1_0_init_cg(struct amdgpu_device *adev) +{ + u32 tmp; + + tmp = RREG32(mmVCE_CLOCK_GATING_A); + tmp |= VCE_CLOCK_GATING_A__CGC_DYN_CLOCK_MODE_MASK; + WREG32(mmVCE_CLOCK_GATING_A, tmp); + + tmp = RREG32(mmVCE_CLOCK_GATING_B); + tmp |= 0x1e; + tmp &= ~0xe100e1; + WREG32(mmVCE_CLOCK_GATING_B, tmp); + + tmp = RREG32(mmVCE_UENC_CLOCK_GATING); + tmp &= ~0xff9ff000; + WREG32(mmVCE_UENC_CLOCK_GATING, tmp); + + tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING); + tmp &= ~0x3ff; + WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp); +} + +/** + * vce_v1_0_load_fw_signature - load firmware signature into VCPU BO + * + * @adev: amdgpu_device pointer + * + * The VCE1 firmware validation mechanism needs a firmware signature. + * This function finds the signature appropriate for the current + * ASIC and writes that into the VCPU BO. + */ +static int vce_v1_0_load_fw_signature(struct amdgpu_device *adev) +{ + const struct common_firmware_header *hdr; + struct vce_v1_0_fw_signature *sign; + unsigned int ucode_offset; + uint32_t chip_id; + u32 *cpu_addr; + int i; + + hdr = (const struct common_firmware_header *)adev->vce.fw->data; + ucode_offset = le32_to_cpu(hdr->ucode_array_offset_bytes); + cpu_addr = adev->vce.cpu_addr; + + sign = (void *)adev->vce.fw->data + ucode_offset; + + switch (adev->asic_type) { + case CHIP_TAHITI: + chip_id = 0x01000014; + break; + case CHIP_VERDE: + chip_id = 0x01000015; + break; + case CHIP_PITCAIRN: + chip_id = 0x01000016; + break; + default: + dev_err(adev->dev, "asic_type %#010x was not found!", adev->asic_type); + return -EINVAL; + } + + for (i = 0; i < le32_to_cpu(sign->number); ++i) { + if (le32_to_cpu(sign->val[i].chip_id) == chip_id) + break; + } + + if (i == le32_to_cpu(sign->number)) { + dev_err(adev->dev, "chip_id 0x%x for %s was not found in VCE firmware", + chip_id, amdgpu_asic_name[adev->asic_type]); + return -EINVAL; + } + + cpu_addr += (256 - 64) / 4; + memcpy_toio(&cpu_addr[0], &sign->val[i].nonce[0], 16); + cpu_addr[4] = cpu_to_le32(le32_to_cpu(sign->length) + 64); + + memset_io(&cpu_addr[5], 0, 44); + memcpy_toio(&cpu_addr[16], &sign[1], hdr->ucode_size_bytes - sizeof(*sign)); + + cpu_addr += (le32_to_cpu(sign->length) + 64) / 4; + memcpy_toio(&cpu_addr[0], &sign->val[i].sigval[0], 16); + + adev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect); + + return 0; +} + +static int vce_v1_0_wait_for_fw_validation(struct amdgpu_device *adev) +{ + int i; + + dev_dbg(adev->dev, "VCE keyselect: %d", adev->vce.keyselect); + WREG32(mmVCE_LMI_FW_START_KEYSEL, adev->vce.keyselect); + + for (i = 0; i < 10; ++i) { + mdelay(10); + if (RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__DONE_MASK) + break; + } + + if (!(RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__DONE_MASK)) { + dev_err(adev->dev, "VCE FW validation timeout\n"); + return -ETIMEDOUT; + } + + if (!(RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__PASS_MASK)) { + dev_err(adev->dev, "VCE FW validation failed\n"); + return -EINVAL; + } + + for (i = 0; i < 10; ++i) { + mdelay(10); + if (!(RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__BUSY_MASK)) + break; + } + + if (RREG32(mmVCE_FW_REG_STATUS) & VCE_FW_REG_STATUS__BUSY_MASK) { + dev_err(adev->dev, "VCE FW busy timeout\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int vce_v1_0_mc_resume(struct amdgpu_device *adev) +{ + uint32_t offset; + uint32_t size; + + /* + * When the keyselect is already set, don't perturb VCE FW. + * Validation seems to always fail the second time. + */ + if (RREG32(mmVCE_LMI_FW_START_KEYSEL)) { + dev_dbg(adev->dev, "keyselect already set: 0x%x (on CPU: 0x%x)\n", + RREG32(mmVCE_LMI_FW_START_KEYSEL), adev->vce.keyselect); + + WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); + return 0; + } + + WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); + WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); + WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); + WREG32(mmVCE_CLOCK_GATING_B, 0); + + WREG32_P(mmVCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4); + + WREG32(mmVCE_LMI_CTRL, 0x00398000); + + WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1); + WREG32(mmVCE_LMI_SWAP_CNTL, 0); + WREG32(mmVCE_LMI_SWAP_CNTL1, 0); + WREG32(mmVCE_LMI_VM_CTRL, 0); + + WREG32(mmVCE_VCPU_SCRATCH7, AMDGPU_MAX_VCE_HANDLES); + + offset = adev->vce.gpu_addr + AMDGPU_VCE_FIRMWARE_OFFSET; + size = VCE_V1_0_FW_SIZE; + WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); + WREG32(mmVCE_VCPU_CACHE_SIZE0, size); + + offset += size; + size = VCE_V1_0_STACK_SIZE; + WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); + WREG32(mmVCE_VCPU_CACHE_SIZE1, size); + + offset += size; + size = VCE_V1_0_DATA_SIZE; + WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff); + WREG32(mmVCE_VCPU_CACHE_SIZE2, size); + + WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); + + return vce_v1_0_wait_for_fw_validation(adev); +} + +/** + * vce_v1_0_is_idle() - Check idle status of VCE1 IP block + * + * @ip_block: amdgpu_ip_block pointer + * + * Check whether VCE is busy according to VCE_STATUS. + * Also check whether the SRBM thinks VCE is busy, although + * SRBM_STATUS.VCE_BUSY seems to be bogus because it + * appears to mirror the VCE_STATUS.VCPU_REPORT_FW_LOADED bit. + */ +static bool vce_v1_0_is_idle(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + bool busy = + (RREG32(mmVCE_STATUS) & (VCE_STATUS__JOB_BUSY_MASK | VCE_STATUS__UENC_BUSY_MASK)) || + (RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK); + + return !busy; +} + +static int vce_v1_0_wait_for_idle(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + unsigned int i; + + for (i = 0; i < adev->usec_timeout; i++) { + udelay(1); + if (vce_v1_0_is_idle(ip_block)) + return 0; + } + return -ETIMEDOUT; +} + +/** + * vce_v1_0_start - start VCE block + * + * @adev: amdgpu_device pointer + * + * Setup and start the VCE block + */ +static int vce_v1_0_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + int r; + + WREG32_P(mmVCE_STATUS, 1, ~1); + + r = vce_v1_0_mc_resume(adev); + if (r) + return r; + + ring = &adev->vce.ring[0]; + WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr)); + WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); + WREG32(mmVCE_RB_BASE_LO, lower_32_bits(ring->gpu_addr)); + WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); + WREG32(mmVCE_RB_SIZE, ring->ring_size / 4); + + ring = &adev->vce.ring[1]; + WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr)); + WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); + WREG32(mmVCE_RB_BASE_LO2, lower_32_bits(ring->gpu_addr)); + WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); + WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4); + + WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, + ~VCE_VCPU_CNTL__CLK_EN_MASK); + + WREG32_P(mmVCE_SOFT_RESET, + VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK | + VCE_SOFT_RESET__FME_SOFT_RESET_MASK, + ~(VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK | + VCE_SOFT_RESET__FME_SOFT_RESET_MASK)); + + mdelay(100); + + WREG32_P(mmVCE_SOFT_RESET, 0, + ~(VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK | + VCE_SOFT_RESET__FME_SOFT_RESET_MASK)); + + r = vce_v1_0_firmware_loaded(adev); + + /* Clear VCE_STATUS, otherwise SRBM thinks VCE1 is busy. */ + WREG32(mmVCE_STATUS, 0); + + if (r) { + dev_err(adev->dev, "VCE not responding, giving up\n"); + return r; + } + + return 0; +} + +static int vce_v1_0_stop(struct amdgpu_device *adev) +{ + struct amdgpu_ip_block *ip_block; + int status; + int i; + + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE); + if (!ip_block) + return -EINVAL; + + if (vce_v1_0_lmi_clean(adev)) + dev_warn(adev->dev, "VCE not idle\n"); + + if (vce_v1_0_wait_for_idle(ip_block)) + dev_warn(adev->dev, "VCE busy: VCE_STATUS=0x%x, SRBM_STATUS2=0x%x\n", + RREG32(mmVCE_STATUS), RREG32(mmSRBM_STATUS2)); + + /* Stall UMC and register bus before resetting VCPU */ + WREG32_P(mmVCE_LMI_CTRL2, 1 << 8, ~(1 << 8)); + + for (i = 0; i < 100; ++i) { + status = RREG32(mmVCE_LMI_STATUS); + if (status & 0x240) + break; + mdelay(1); + } + + WREG32_P(mmVCE_VCPU_CNTL, 0, ~VCE_VCPU_CNTL__CLK_EN_MASK); + + WREG32_P(mmVCE_SOFT_RESET, + VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK | + VCE_SOFT_RESET__FME_SOFT_RESET_MASK, + ~(VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK | + VCE_SOFT_RESET__FME_SOFT_RESET_MASK)); + + WREG32(mmVCE_STATUS, 0); + + return 0; +} + +static void vce_v1_0_enable_mgcg(struct amdgpu_device *adev, bool enable) +{ + u32 tmp; + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) { + tmp = RREG32(mmVCE_CLOCK_GATING_A); + tmp |= VCE_CLOCK_GATING_A__CGC_DYN_CLOCK_MODE_MASK; + WREG32(mmVCE_CLOCK_GATING_A, tmp); + + tmp = RREG32(mmVCE_UENC_CLOCK_GATING); + tmp &= ~0x1ff000; + tmp |= 0xff800000; + WREG32(mmVCE_UENC_CLOCK_GATING, tmp); + + tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING); + tmp &= ~0x3ff; + WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp); + } else { + tmp = RREG32(mmVCE_CLOCK_GATING_A); + tmp &= ~VCE_CLOCK_GATING_A__CGC_DYN_CLOCK_MODE_MASK; + WREG32(mmVCE_CLOCK_GATING_A, tmp); + + tmp = RREG32(mmVCE_UENC_CLOCK_GATING); + tmp |= 0x1ff000; + tmp &= ~0xff800000; + WREG32(mmVCE_UENC_CLOCK_GATING, tmp); + + tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING); + tmp |= 0x3ff; + WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp); + } +} + +static int vce_v1_0_early_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int r; + + r = amdgpu_vce_early_init(adev); + if (r) + return r; + + adev->vce.num_rings = 2; + + vce_v1_0_set_ring_funcs(adev); + vce_v1_0_set_irq_funcs(adev); + + return 0; +} + +static int vce_v1_0_sw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_ring *ring; + int r, i; + + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 167, &adev->vce.irq); + if (r) + return r; + + r = amdgpu_vce_sw_init(adev, VCE_V1_0_FW_SIZE + + VCE_V1_0_STACK_SIZE + VCE_V1_0_DATA_SIZE); + if (r) + return r; + + r = amdgpu_vce_resume(adev); + if (r) + return r; + r = vce_v1_0_load_fw_signature(adev); + if (r) + return r; + + for (i = 0; i < adev->vce.num_rings; i++) { + enum amdgpu_ring_priority_level hw_prio = amdgpu_vce_get_ring_prio(i); + + ring = &adev->vce.ring[i]; + sprintf(ring->name, "vce%d", i); + r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0, + hw_prio, NULL); + if (r) + return r; + } + + return r; +} + +static int vce_v1_0_sw_fini(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int r; + + r = amdgpu_vce_suspend(adev); + if (r) + return r; + + return amdgpu_vce_sw_fini(adev); +} + +/** + * vce_v1_0_hw_init - start and test VCE block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Initialize the hardware, boot up the VCPU and do some testing + */ +static int vce_v1_0_hw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int i, r; + + if (adev->pm.dpm_enabled) + amdgpu_dpm_enable_vce(adev, true); + else + amdgpu_asic_set_vce_clocks(adev, 10000, 10000); + + for (i = 0; i < adev->vce.num_rings; i++) { + r = amdgpu_ring_test_helper(&adev->vce.ring[i]); + if (r) + return r; + } + + dev_info(adev->dev, "VCE initialized successfully.\n"); + + return 0; +} + +static int vce_v1_0_hw_fini(struct amdgpu_ip_block *ip_block) +{ + int r; + + r = vce_v1_0_stop(ip_block->adev); + if (r) + return r; + + cancel_delayed_work_sync(&ip_block->adev->vce.idle_work); + return 0; +} + +static int vce_v1_0_suspend(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int r; + + /* + * Proper cleanups before halting the HW engine: + * - cancel the delayed idle work + * - enable powergating + * - enable clockgating + * - disable dpm + * + * TODO: to align with the VCN implementation, move the + * jobs for clockgating/powergating/dpm setting to + * ->set_powergating_state(). + */ + cancel_delayed_work_sync(&adev->vce.idle_work); + + if (adev->pm.dpm_enabled) { + amdgpu_dpm_enable_vce(adev, false); + } else { + amdgpu_asic_set_vce_clocks(adev, 0, 0); + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_PG_STATE_GATE); + amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, + AMD_CG_STATE_GATE); + } + + r = vce_v1_0_hw_fini(ip_block); + if (r) { + dev_err(adev->dev, "vce_v1_0_hw_fini() failed with error %i", r); + return r; + } + + return amdgpu_vce_suspend(adev); +} + +static int vce_v1_0_resume(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int r; + + r = amdgpu_vce_resume(adev); + if (r) + return r; + r = vce_v1_0_load_fw_signature(adev); + if (r) + return r; + + return vce_v1_0_hw_init(ip_block); +} + +static int vce_v1_0_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + uint32_t val = 0; + + if (state == AMDGPU_IRQ_STATE_ENABLE) + val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK; + + WREG32_P(mmVCE_SYS_INT_EN, val, + ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); + return 0; +} + +static int vce_v1_0_process_interrupt(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + dev_dbg(adev->dev, "IH: VCE\n"); + switch (entry->src_data[0]) { + case 0: + case 1: + amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]); + break; + default: + dev_err(adev->dev, "Unhandled interrupt: %d %d\n", + entry->src_id, entry->src_data[0]); + break; + } + + return 0; +} + +static int vce_v1_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, + enum amd_clockgating_state state) +{ + struct amdgpu_device *adev = ip_block->adev; + + vce_v1_0_init_cg(adev); + vce_v1_0_enable_mgcg(adev, state == AMD_CG_STATE_GATE); + + return 0; +} + +static int vce_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block, + enum amd_powergating_state state) +{ + struct amdgpu_device *adev = ip_block->adev; + + /* + * This doesn't actually powergate the VCE block. + * That's done in the dpm code via the SMC. This + * just re-inits the block as necessary. The actual + * gating still happens in the dpm code. We should + * revisit this when there is a cleaner line between + * the smc and the hw blocks + */ + if (state == AMD_PG_STATE_GATE) + return vce_v1_0_stop(adev); + else + return vce_v1_0_start(adev); +} + +static const struct amd_ip_funcs vce_v1_0_ip_funcs = { + .name = "vce_v1_0", + .early_init = vce_v1_0_early_init, + .sw_init = vce_v1_0_sw_init, + .sw_fini = vce_v1_0_sw_fini, + .hw_init = vce_v1_0_hw_init, + .hw_fini = vce_v1_0_hw_fini, + .suspend = vce_v1_0_suspend, + .resume = vce_v1_0_resume, + .is_idle = vce_v1_0_is_idle, + .wait_for_idle = vce_v1_0_wait_for_idle, + .set_clockgating_state = vce_v1_0_set_clockgating_state, + .set_powergating_state = vce_v1_0_set_powergating_state, +}; + +static const struct amdgpu_ring_funcs vce_v1_0_ring_funcs = { + .type = AMDGPU_RING_TYPE_VCE, + .align_mask = 0xf, + .nop = VCE_CMD_NO_OP, + .support_64bit_ptrs = false, + .no_user_fence = true, + .get_rptr = vce_v1_0_ring_get_rptr, + .get_wptr = vce_v1_0_ring_get_wptr, + .set_wptr = vce_v1_0_ring_set_wptr, + .parse_cs = amdgpu_vce_ring_parse_cs, + .emit_frame_size = 6, /* amdgpu_vce_ring_emit_fence x1 no user fence */ + .emit_ib_size = 4, /* amdgpu_vce_ring_emit_ib */ + .emit_ib = amdgpu_vce_ring_emit_ib, + .emit_fence = amdgpu_vce_ring_emit_fence, + .test_ring = amdgpu_vce_ring_test_ring, + .test_ib = amdgpu_vce_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, + .pad_ib = amdgpu_ring_generic_pad_ib, + .begin_use = amdgpu_vce_ring_begin_use, + .end_use = amdgpu_vce_ring_end_use, +}; + +static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->vce.num_rings; i++) { + adev->vce.ring[i].funcs = &vce_v1_0_ring_funcs; + adev->vce.ring[i].me = i; + } +}; + +static const struct amdgpu_irq_src_funcs vce_v1_0_irq_funcs = { + .set = vce_v1_0_set_interrupt_state, + .process = vce_v1_0_process_interrupt, +}; + +static void vce_v1_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->vce.irq.num_types = 1; + adev->vce.irq.funcs = &vce_v1_0_irq_funcs; +}; + +const struct amdgpu_ip_block_version vce_v1_0_ip_block = { + .type = AMD_IP_BLOCK_TYPE_VCE, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &vce_v1_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.h b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.h new file mode 100644 index 0000000000000..206e7bec897f7 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * Copyright 2025 Valve Corporation + * Copyright 2025 Alexandre Demers + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __VCE_V1_0_H__ +#define __VCE_V1_0_H__ + +extern const struct amdgpu_ip_block_version vce_v1_0_ip_block; + +#endif From 729707b2dd2c9a435c2b28e798434ea87a88d2bb Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 6 Nov 2025 18:44:29 +0530 Subject: [PATCH 2550/2653] drm/amdgpu: Check if AID is active before access Access XGMI registers only if AID is active. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index 95f3611d743b7..59f9408cc94f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -333,6 +333,10 @@ static u32 xgmi_v6_4_get_link_status(struct amdgpu_device *adev, int global_link } i = global_link_num / n; + + if (!(adev->aid_mask & BIT(i))) + return U32_MAX; + addr += adev->asic_funcs->encode_ext_smn_addressing(i); return RREG32_PCIE_EXT(addr); From cd7ad0005f637ea1fbcebd1b864ce73b24c63d51 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 7 Nov 2025 16:57:42 +0100 Subject: [PATCH 2551/2653] drm/amdgpu/vce1: Ensure VCPU BO is in lower 32-bit address space (v3) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Based on research and ideas by Alexandre and Christian. VCE1 actually executes its code from the VCPU BO. Due to various hardware limitations, the VCE1 requires the VCPU BO to be in the low 32 bit address range. However, VRAM is typically mapped at the high address range, which means the VCPU can't access VRAM through the FB aperture. To solve this, we write a few page table entries to map the VCPU BO in the GART address range. And we make sure that the GART is located at the low address range. That way the VCE1 can access the VCPU BO. v2: - Adjust to v2 of the GART helper commit. - Add empty line to multi-line comment. v3: - Instead of relying on gmc_v6 to set the GART space before GTT, add a new function amdgpu_vce_required_gart_pages() which is called from amdgpu_gtt_mgr_init() directly. Signed-off-by: Timur Kristóf Co-developed-by: Alexandre Demers Signed-off-by: Alexandre Demers Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 18 +++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 1 + drivers/gpu/drm/amd/amdgpu/vce_v1_0.c | 55 +++++++++++++++++++++ 4 files changed, 75 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index 071241ccfb646..f7a867002b9cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -289,6 +289,7 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size) ttm_resource_manager_init(man, &adev->mman.bdev, gtt_size); start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS; + start += amdgpu_vce_required_gart_pages(adev); size = (adev->gmc.gart_size >> PAGE_SHIFT) - start; drm_mm_init(&mgr->mm, start, size); spin_lock_init(&mgr->lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 7fead2eebd362..709ca369cb524 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -450,6 +450,24 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp) } } +/** + * amdgpu_vce_required_gart_pages() - gets number of GART pages required by VCE + * + * @adev: amdgpu_device pointer + * + * Returns how many GART pages we need before GTT for the VCE IP block. + * For VCE1, see vce_v1_0_ensure_vcpu_bo_32bit_addr for details. + * For VCE2+, this is not needed so return zero. + */ +u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev) +{ + /* VCE IP block not added yet, so can't use amdgpu_ip_version */ + if (adev->family == AMDGPU_FAMILY_SI) + return 512; + + return 0; +} + /** * amdgpu_vce_get_create_msg - generate a VCE create msg * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h index 0507838026231..1c3464ce50378 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h @@ -61,6 +61,7 @@ int amdgpu_vce_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring) int amdgpu_vce_suspend(struct amdgpu_device *adev); int amdgpu_vce_resume(struct amdgpu_device *adev); void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp); +u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev); int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, struct amdgpu_job *job, struct amdgpu_ib *ib); int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c index bf9f943852cbc..9ae4246185560 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c @@ -34,6 +34,7 @@ #include "amdgpu.h" #include "amdgpu_vce.h" +#include "amdgpu_gart.h" #include "sid.h" #include "vce_v1_0.h" #include "vce/vce_1_0_d.h" @@ -46,6 +47,11 @@ #define VCE_V1_0_DATA_SIZE (7808 * (AMDGPU_MAX_VCE_HANDLES + 1)) #define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02 +#define VCE_V1_0_GART_PAGE_START \ + (AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS) +#define VCE_V1_0_GART_ADDR_START \ + (VCE_V1_0_GART_PAGE_START * AMDGPU_GPU_PAGE_SIZE) + static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev); static void vce_v1_0_set_irq_funcs(struct amdgpu_device *adev); @@ -513,6 +519,49 @@ static int vce_v1_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } +/** + * vce_v1_0_ensure_vcpu_bo_32bit_addr() - ensure the VCPU BO has a 32-bit address + * + * @adev: amdgpu_device pointer + * + * Due to various hardware limitations, the VCE1 requires + * the VCPU BO to be in the low 32 bit address range. + * Ensure that the VCPU BO has a 32-bit GPU address, + * or return an error code when that isn't possible. + * + * To accomodate that, we put GART to the LOW address range + * and reserve some GART pages where we map the VCPU BO, + * so that it gets a 32-bit address. + */ +static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct amdgpu_device *adev) +{ + u64 gpu_addr = amdgpu_bo_gpu_offset(adev->vce.vcpu_bo); + u64 bo_size = amdgpu_bo_size(adev->vce.vcpu_bo); + u64 max_vcpu_bo_addr = 0xffffffff - bo_size; + u64 num_pages = ALIGN(bo_size, AMDGPU_GPU_PAGE_SIZE) / AMDGPU_GPU_PAGE_SIZE; + u64 pa = amdgpu_gmc_vram_pa(adev, adev->vce.vcpu_bo); + u64 flags = AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | AMDGPU_PTE_VALID; + + /* + * Check if the VCPU BO already has a 32-bit address. + * Eg. if MC is configured to put VRAM in the low address range. + */ + if (gpu_addr <= max_vcpu_bo_addr) + return 0; + + /* Check if we can map the VCPU BO in GART to a 32-bit address. */ + if (adev->gmc.gart_start + VCE_V1_0_GART_ADDR_START > max_vcpu_bo_addr) + return -EINVAL; + + amdgpu_gart_map_vram_range(adev, pa, VCE_V1_0_GART_PAGE_START, + num_pages, flags, adev->gart.ptr); + adev->vce.gpu_addr = adev->gmc.gart_start + VCE_V1_0_GART_ADDR_START; + if (adev->vce.gpu_addr > max_vcpu_bo_addr) + return -EINVAL; + + return 0; +} + static int vce_v1_0_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -532,6 +581,9 @@ static int vce_v1_0_sw_init(struct amdgpu_ip_block *ip_block) if (r) return r; r = vce_v1_0_load_fw_signature(adev); + if (r) + return r; + r = vce_v1_0_ensure_vcpu_bo_32bit_addr(adev); if (r) return r; @@ -647,6 +699,9 @@ static int vce_v1_0_resume(struct amdgpu_ip_block *ip_block) if (r) return r; r = vce_v1_0_load_fw_signature(adev); + if (r) + return r; + r = vce_v1_0_ensure_vcpu_bo_32bit_addr(adev); if (r) return r; From 738a01a458eda1948fffbbd9789fda539b6106ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 7 Nov 2025 16:57:43 +0100 Subject: [PATCH 2552/2653] drm/amd/pm/si: Hook up VCE1 to SI DPM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On SI GPUs, the SMC needs to be aware of whether or not the VCE1 is used. The VCE1 is enabled/disabled through the DPM code. Also print VCE clocks in amdgpu_pm_info. Users can inspect the current power state using: cat /sys/kernel/debug/dri//amdgpu_pm_info Signed-off-by: Timur Kristóf Reviewed-by: Christian König --- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 020e05c137e43..1f539cc65f41f 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -7046,13 +7046,20 @@ static void si_set_vce_clock(struct amdgpu_device *adev, if ((old_rps->evclk != new_rps->evclk) || (old_rps->ecclk != new_rps->ecclk)) { /* Turn the clocks on when encoding, off otherwise */ + dev_dbg(adev->dev, "set VCE clocks: %u, %u\n", new_rps->evclk, new_rps->ecclk); + if (new_rps->evclk || new_rps->ecclk) { - /* Place holder for future VCE1.0 porting to amdgpu - vce_v1_0_enable_mgcg(adev, false, false);*/ + amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk); + amdgpu_device_ip_set_clockgating_state( + adev, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_UNGATE); + amdgpu_device_ip_set_powergating_state( + adev, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_UNGATE); } else { - /* Place holder for future VCE1.0 porting to amdgpu - vce_v1_0_enable_mgcg(adev, true, false); - amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk);*/ + amdgpu_device_ip_set_powergating_state( + adev, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_GATE); + amdgpu_device_ip_set_clockgating_state( + adev, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_GATE); + amdgpu_asic_set_vce_clocks(adev, 0, 0); } } } @@ -7574,6 +7581,7 @@ static void si_dpm_debugfs_print_current_performance_level(void *handle, } else { pl = &ps->performance_levels[current_index]; seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); + seq_printf(m, "vce evclk: %d ecclk: %d\n", rps->evclk, rps->ecclk); seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); } From 86f5c9683648f6c4a909ba97e6dfeb35fa8593b4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 7 Nov 2025 16:57:44 +0100 Subject: [PATCH 2553/2653] drm/amdgpu/vce1: Enable VCE1 on Tahiti, Pitcairn, Cape Verde GPUs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the VCE1 IP block to the SI GPUs that have it. Advertise the encoder capabilities corresponding to VCE1, so the userspace applications can detect and use it. Signed-off-by: Timur Kristóf Co-developed-by: Alexandre Demers Signed-off-by: Alexandre Demers Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/si.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index e0f139de79915..9d769222784c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -45,6 +45,7 @@ #include "dce_v6_0.h" #include "si.h" #include "uvd_v3_1.h" +#include "vce_v1_0.h" #include "uvd/uvd_4_0_d.h" @@ -921,8 +922,6 @@ static const u32 hainan_mgcg_cgcg_init[] = 0x3630, 0xfffffff0, 0x00000100, }; -/* XXX: update when we support VCE */ -#if 0 /* tahiti, pitcairn, verde */ static const struct amdgpu_video_codec_info tahiti_video_codecs_encode_array[] = { @@ -940,13 +939,7 @@ static const struct amdgpu_video_codecs tahiti_video_codecs_encode = .codec_count = ARRAY_SIZE(tahiti_video_codecs_encode_array), .codec_array = tahiti_video_codecs_encode_array, }; -#else -static const struct amdgpu_video_codecs tahiti_video_codecs_encode = -{ - .codec_count = 0, - .codec_array = NULL, -}; -#endif + /* oland and hainan don't support encode */ static const struct amdgpu_video_codecs hainan_video_codecs_encode = { @@ -2717,7 +2710,7 @@ int si_set_ip_blocks(struct amdgpu_device *adev) else amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block); amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); - /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */ + amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); break; case CHIP_OLAND: amdgpu_device_ip_block_add(adev, &si_common_ip_block); @@ -2735,7 +2728,6 @@ int si_set_ip_blocks(struct amdgpu_device *adev) else amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block); amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); - /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */ break; case CHIP_HAINAN: amdgpu_device_ip_block_add(adev, &si_common_ip_block); From 28d26b8b9ebe3a953d83a9828ecd4f607fb52255 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 7 Nov 2025 16:57:45 +0100 Subject: [PATCH 2554/2653] drm/amdgpu/vce1: Workaround PLL timeout on FirePro W9000 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sometimes the VCE PLL times out waiting for CTLACK/CTLACK2. When it happens, the VCE still works, but much slower. Observed on a Tahiti GPU, but not all: - FirePro W9000 has the issue - Radeon R9 280X not affected - Radeon HD 7990 not affected As a workaround, on the affected chip just don't put the VCE PLL in sleep mode. Leaving the VCE PLL in bypass mode or reset mode both work. Using bypass mode is simpler. Signed-off-by: Timur Kristóf Acked-by: Christian König --- drivers/gpu/drm/amd/amdgpu/si.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 9d769222784c4..f7288372ee613 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1918,6 +1918,14 @@ static int si_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) ~VCEPLL_BYPASS_EN_MASK); if (!evclk || !ecclk) { + /* + * On some chips, the PLL takes way too long to get out of + * sleep mode, causing a timeout waiting on CTLACK/CTLACK2. + * Leave the PLL running in bypass mode. + */ + if (adev->pdev->device == 0x6780) + return 0; + /* Keep the Bypass mode, put PLL to sleep */ WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK, ~VCEPLL_SLEEP_MASK); From b078b96d729c91745f6afbeee8d38ee017459e06 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Tue, 28 Oct 2025 14:37:07 -0400 Subject: [PATCH 2555/2653] drm/amdkfd: Fix GPU mappings for APU after prefetch Fix the following corner case:- Consider a 2M huge page SVM allocation, followed by prefetch call for the first 4K page. The whole range is initially mapped with single PTE. After the prefetch, this range gets split to first page + rest of the pages. Currently, the first page mapping is not updated on MI300A (APU) since page hasn't migrated. However, after range split PTE mapping it not valid. Fix this by forcing page table update for the whole range when prefetch is called. Calling prefetch on APU doesn't improve performance. If all it deteriotes. However, functionality has to be supported. v2: Use apu_prefer_gtt as this issue doesn't apply to APUs with carveout VRAM v3: Simplify by setting the flag for all ASICs as it doesn't affect dGPU v4: Remove v2 and v3 changes. Force update_mapping when range is split at a size that is not aligned to prange granularity Suggested-by: Philip Yang Signed-off-by: Harish Kasiviswanathan Reviewed-by: Philip Yang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 52a01b414ce25..89529104bc011 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -3697,6 +3697,8 @@ svm_range_set_attr(struct kfd_process *p, struct mm_struct *mm, svm_range_apply_attrs(p, prange, nattr, attrs, &update_mapping); /* TODO: unmap ranges from GPU that lost access */ } + update_mapping |= !p->xnack_enabled && !list_empty(&remap_list); + list_for_each_entry_safe(prange, next, &remove_list, update_list) { pr_debug("unlink old 0x%p prange 0x%p [0x%lx 0x%lx]\n", prange->svms, prange, prange->start, From d36b750f3d144b6a3481f1db6f527acf71973418 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Wed, 12 Nov 2025 11:35:58 +0800 Subject: [PATCH 2556/2653] Bump AMDGPU version to 6.16.11 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 28b1119000266..0cd465a6869d1 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.16.10) +AC_INIT(amdgpu-dkms, 6.16.11) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 0ab53bfd863c98154af31565dc36a825f7d22aca Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 6 Nov 2025 13:49:59 +0530 Subject: [PATCH 2557/2653] drm/amdgpu: Avoid xgmi register access On single GPU systems, avoid accesses to XGMI link registers. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index 59f9408cc94f9..9f6b4dd6315e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -298,6 +298,9 @@ int amdgpu_xgmi_get_ext_link(struct amdgpu_device *adev, int link_num) { int link_map_6_4_x[8] = { 0, 3, 1, 2, 7, 6, 4, 5 }; + if (adev->gmc.xgmi.num_physical_nodes <= 1) + return -EINVAL; + switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) { case IP_VERSION(6, 4, 0): case IP_VERSION(6, 4, 1): @@ -346,6 +349,9 @@ int amdgpu_get_xgmi_link_status(struct amdgpu_device *adev, int global_link_num) { u32 xgmi_state_reg_val; + if (adev->gmc.xgmi.num_physical_nodes <= 1) + return -EINVAL; + switch (amdgpu_ip_version(adev, XGMI_HWIP, 0)) { case IP_VERSION(6, 4, 0): case IP_VERSION(6, 4, 1): From a3d58b88554f514184ddd1306cc2fd9308aafb99 Mon Sep 17 00:00:00 2001 From: Will Aitken Date: Tue, 30 Sep 2025 16:24:07 +0000 Subject: [PATCH 2558/2653] drm/amdgpu: Refactor sriov xgmi topology filling to common code amdgpu_xgmi_fill_topology_info and psp_xgmi_reflect_topology_info perform the same logic of copying topology info of one node to every other node in the hive. Instead of having two functions that purport to do the same thing, this refactoring moves the logic of the fill function to the reflect function and adds reflecting port number info as well for complete functionality. Signed-off-by: Will Aitken Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 19 ++++++++++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 27 ------------------------ 2 files changed, 14 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index e1de1dc1c940a..a5ceda87a3e11 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1539,6 +1539,7 @@ static void psp_xgmi_reflect_topology_info(struct psp_context *psp, uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; uint64_t dst_node_id = node_info.node_id; uint8_t dst_num_hops = node_info.num_hops; + uint8_t dst_is_sharing_enabled = node_info.is_sharing_enabled; uint8_t dst_num_links = node_info.num_links; hive = amdgpu_get_xgmi_hive(psp->adev); @@ -1558,13 +1559,20 @@ static void psp_xgmi_reflect_topology_info(struct psp_context *psp, continue; mirror_top_info->nodes[j].num_hops = dst_num_hops; - /* - * prevent 0 num_links value re-reflection since reflection + mirror_top_info->nodes[j].is_sharing_enabled = dst_is_sharing_enabled; + /* prevent 0 num_links value re-reflection since reflection * criteria is based on num_hops (direct or indirect). - * */ - if (dst_num_links) + if (dst_num_links) { mirror_top_info->nodes[j].num_links = dst_num_links; + /* swap src and dst due to frame of reference */ + for (int k = 0; k < dst_num_links; k++) { + mirror_top_info->nodes[j].port_num[k].src_xgmi_port_num = + node_info.port_num[k].dst_xgmi_port_num; + mirror_top_info->nodes[j].port_num[k].dst_xgmi_port_num = + node_info.port_num[k].src_xgmi_port_num; + } + } break; } @@ -1639,7 +1647,8 @@ int psp_xgmi_get_topology_info(struct psp_context *psp, amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == - IP_VERSION(13, 0, 14); + IP_VERSION(13, 0, 14) || + amdgpu_sriov_vf(psp->adev); bool ta_port_num_support = amdgpu_sriov_vf(psp->adev) ? 0 : psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index 9f6b4dd6315e4..5adb88477ce49 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -974,28 +974,6 @@ static int amdgpu_xgmi_initialize_hive_get_data_partition(struct amdgpu_hive_inf return 0; } -static void amdgpu_xgmi_fill_topology_info(struct amdgpu_device *adev, - struct amdgpu_device *peer_adev) -{ - struct psp_xgmi_topology_info *top_info = &adev->psp.xgmi_context.top_info; - struct psp_xgmi_topology_info *peer_info = &peer_adev->psp.xgmi_context.top_info; - - for (int i = 0; i < peer_info->num_nodes; i++) { - if (peer_info->nodes[i].node_id == adev->gmc.xgmi.node_id) { - for (int j = 0; j < top_info->num_nodes; j++) { - if (top_info->nodes[j].node_id == peer_adev->gmc.xgmi.node_id) { - peer_info->nodes[i].num_hops = top_info->nodes[j].num_hops; - peer_info->nodes[i].is_sharing_enabled = - top_info->nodes[j].is_sharing_enabled; - peer_info->nodes[i].num_links = - top_info->nodes[j].num_links; - return; - } - } - } - } -} - int amdgpu_xgmi_add_device(struct amdgpu_device *adev) { struct psp_xgmi_topology_info *top_info; @@ -1081,11 +1059,6 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev) /* To do: continue with some node failed or disable the whole hive*/ goto exit_unlock; } - - /* fill the topology info for peers instead of getting from PSP */ - list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { - amdgpu_xgmi_fill_topology_info(adev, tmp_adev); - } } else { /* get latest topology info for each device from psp */ list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { From 7f4f35c05a1e9d47f26767c941fc10d9debb466d Mon Sep 17 00:00:00 2001 From: Will Aitken Date: Tue, 7 Oct 2025 14:19:45 +0000 Subject: [PATCH 2559/2653] drm/amdgpu: Update headers for sriov xgmi ext peer link support feature flag Adds new sriov msg flag to match host, feature flag in the amdgim enum, and a wrapper macro to check it. Signed-off-by: Will Aitken Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 14d864be5800a..4fd194a9a972e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -150,6 +150,7 @@ enum AMDGIM_FEATURE_FLAG { AMDGIM_FEATURE_RAS_CAPS = (1 << 9), AMDGIM_FEATURE_RAS_TELEMETRY = (1 << 10), AMDGIM_FEATURE_RAS_CPER = (1 << 11), + AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK = (1 << 12), }; enum AMDGIM_REG_ACCESS_FLAG { @@ -395,6 +396,9 @@ struct amdgpu_video_codec_info; #define amdgpu_sriov_ras_cper_en(adev) \ ((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CPER) +#define amdgpu_sriov_xgmi_ta_ext_peer_link_en(adev) \ +((adev)->virt.gim_feature & AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK) + static inline bool is_virtual_machine(void) { #if defined(CONFIG_X86) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h index 1cee083fb6bd6..ba23bf982d7b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h @@ -160,7 +160,8 @@ union amd_sriov_msg_feature_flags { uint32_t ras_caps : 1; uint32_t ras_telemetry : 1; uint32_t ras_cper : 1; - uint32_t reserved : 20; + uint32_t xgmi_ta_ext_peer_link : 1; + uint32_t reserved : 19; } flags; uint32_t all; }; From 8f9169365d5028fc3298b093cde18b3527d24db0 Mon Sep 17 00:00:00 2001 From: Will Aitken Date: Tue, 7 Oct 2025 14:49:15 +0000 Subject: [PATCH 2560/2653] drm/amdgpu: Enable xgmi extended peer links for sriov guest The amd-smi tool relies on extended peer link information to report xgmi link metrics. The necessary xgmi ta command, GET_EXTEND_PEER_LINKS, has been enabled in the host driver and this change is necessary for the guest to make use of it. To handle the case where the host driver does not have the latest xgmi ta, the guest driver checks for guest support through a pf2vf feature flag before invoking psp. Signed-off-by: Will Aitken Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index a5ceda87a3e11..c574666525246 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1649,8 +1649,8 @@ int psp_xgmi_get_topology_info(struct psp_context *psp, amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || amdgpu_sriov_vf(psp->adev); - bool ta_port_num_support = amdgpu_sriov_vf(psp->adev) ? 0 : - psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG; + bool ta_port_num_support = psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG || + amdgpu_sriov_xgmi_ta_ext_peer_link_en(psp->adev); /* popluate the shared output buffer rather than the cmd input buffer * with node_ids as the input for GET_PEER_LINKS command execution. From 1fd8d526c6b784b4cca8e5ab6b47750f19c94be6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Sun, 9 Nov 2025 16:41:05 +0100 Subject: [PATCH 2561/2653] drm/amdgpu: Refactor how SI and CIK support is determined MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the determination into a separate function. Change amdgpu.si_support and amdgpu.cik_support so that their default value is -1 (default). This prepares the code for changing the default driver based on the chip. Also adjust the module param documentation. Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 153 ++++++++++++++---------- 1 file changed, 88 insertions(+), 65 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index b406163a106a7..0385af1937f36 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -626,37 +626,37 @@ module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); /** * DOC: si_support (int) - * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, - * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, - * otherwise using amdgpu driver. - */ + * 1 = enabled, 0 = disabled, -1 = default + * + * SI (Southern Islands) are first generation GCN GPUs, supported by both + * drivers: radeon (old) and amdgpu (new). This parameter controls whether + * amdgpu should support SI. + * By default, SI chips are supported by radeon (except when radeon is not built). + * Only relevant when CONFIG_DRM_AMDGPU_SI is enabled to build SI support in amdgpu. + * See also radeon.si_support which should be disabled when amdgpu.si_support is + * enabled, and vice versa. + */ +int amdgpu_si_support = -1; #ifdef CONFIG_DRM_AMDGPU_SI - -#if (0 && (IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE))) -int amdgpu_si_support; -MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); -#else -int amdgpu_si_support = 1; -MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); -#endif +MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled, -1 = default)"); module_param_named(si_support, amdgpu_si_support, int, 0444); #endif /** * DOC: cik_support (int) - * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, - * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, - * otherwise using amdgpu driver. - */ + * 1 = enabled, 0 = disabled, -1 = default + * + * CIK (Sea Islands) are second generation GCN GPUs, supported by both + * drivers: radeon (old) and amdgpu (new). This parameter controls whether + * amdgpu should support CIK. + * By default, CIK chips are supported by radeon (except when radeon is not built). + * Only relevant when CONFIG_DRM_AMDGPU_CIK is enabled to build CIK support in amdgpu. + * See also radeon.cik_support which should be disabled when amdgpu.cik_support is + * enabled, and vice versa. + */ +int amdgpu_cik_support = -1; #ifdef CONFIG_DRM_AMDGPU_CIK - -#if (0 && (IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE))) -int amdgpu_cik_support; -MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); -#else -int amdgpu_cik_support = 1; -MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); -#endif +MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled, -1 = default)"); module_param_named(cik_support, amdgpu_cik_support, int, 0444); #endif @@ -2331,6 +2331,69 @@ static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long fl return flags; } +static bool amdgpu_support_enabled(struct device *dev, + const enum amd_asic_type family) +{ + const char *gen; + const char *param; + int module_param = -1; + bool radeon_support_built = IS_ENABLED(CONFIG_DRM_RADEON); + bool amdgpu_support_built = false; + bool support_by_default = false; + + switch (family) { + case CHIP_TAHITI: + case CHIP_PITCAIRN: + case CHIP_VERDE: + case CHIP_OLAND: + case CHIP_HAINAN: + gen = "SI"; + param = "si_support"; + module_param = amdgpu_si_support; + amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_SI); + break; + + case CHIP_BONAIRE: + case CHIP_HAWAII: + case CHIP_KAVERI: + case CHIP_KABINI: + case CHIP_MULLINS: + gen = "CIK"; + param = "cik_support"; + module_param = amdgpu_cik_support; + amdgpu_support_built = IS_ENABLED(CONFIG_DRM_AMDGPU_CIK); + break; + + default: + /* All other chips are supported by amdgpu only */ + return true; + } + + if (!amdgpu_support_built) { + dev_info(dev, "amdgpu built without %s support\n", gen); + return false; + } + + if ((module_param == -1 && (support_by_default || !radeon_support_built)) || + module_param == 1) { + if (radeon_support_built) + dev_info(dev, "%s support provided by amdgpu.\n" + "Use radeon.%s=1 amdgpu.%s=0 to override.\n", + gen, param, param); + + return true; + } + + if (radeon_support_built) + dev_info(dev, "%s support provided by radeon.\n" + "Use radeon.%s=0 amdgpu.%s=1 to override.\n", + gen, param, param); + else if (module_param == 0) + dev_info(dev, "%s support disabled by module param\n", gen); + + return false; +} + static int amdgpu_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { @@ -2380,48 +2443,8 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, return -ENOTSUPP; } - switch (flags & AMD_ASIC_MASK) { - case CHIP_TAHITI: - case CHIP_PITCAIRN: - case CHIP_VERDE: - case CHIP_OLAND: - case CHIP_HAINAN: -#ifdef CONFIG_DRM_AMDGPU_SI - if (!amdgpu_si_support) { - dev_info(&pdev->dev, - "SI support provided by radeon.\n"); - dev_info(&pdev->dev, - "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" - ); - return -ENODEV; - } - break; -#else - dev_info(&pdev->dev, "amdgpu is built without SI support.\n"); + if (!amdgpu_support_enabled(&pdev->dev, flags & AMD_ASIC_MASK)) return -ENODEV; -#endif - case CHIP_KAVERI: - case CHIP_BONAIRE: - case CHIP_HAWAII: - case CHIP_KABINI: - case CHIP_MULLINS: -#ifdef CONFIG_DRM_AMDGPU_CIK - if (!amdgpu_cik_support) { - dev_info(&pdev->dev, - "CIK support provided by radeon.\n"); - dev_info(&pdev->dev, - "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" - ); - return -ENODEV; - } - break; -#else - dev_info(&pdev->dev, "amdgpu is built without CIK support.\n"); - return -ENODEV; -#endif - default: - break; - } adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); if (IS_ERR(adev)) From fc49b483611ee35f7c342692ab9b2783d80272c0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Sun, 9 Nov 2025 16:41:06 +0100 Subject: [PATCH 2562/2653] drm/amdgpu: Use amdgpu by default on CIK dedicated GPUs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The amdgpu driver has been working well on CIK dGPUs for years. Now that the DC analog connector support landed, these GPUs are at feature parity with the old radeon driver. Additionally, amdgpu yields extra performance, supports Vulkan and provides more display features through DC as well as more robust power management. Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 0385af1937f36..20f014166f1ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -649,7 +649,9 @@ module_param_named(si_support, amdgpu_si_support, int, 0444); * CIK (Sea Islands) are second generation GCN GPUs, supported by both * drivers: radeon (old) and amdgpu (new). This parameter controls whether * amdgpu should support CIK. - * By default, CIK chips are supported by radeon (except when radeon is not built). + * By default: + * - CIK dedicated GPUs are supported by amdgpu. + * - CIK APUs are supported by radeon (except when radeon is not built). * Only relevant when CONFIG_DRM_AMDGPU_CIK is enabled to build CIK support in amdgpu. * See also radeon.cik_support which should be disabled when amdgpu.cik_support is * enabled, and vice versa. @@ -2355,6 +2357,8 @@ static bool amdgpu_support_enabled(struct device *dev, case CHIP_BONAIRE: case CHIP_HAWAII: + support_by_default = true; + fallthrough; case CHIP_KAVERI: case CHIP_KABINI: case CHIP_MULLINS: From 27971b27b47f77fb19c4b95bb036e521938e4619 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 13 Nov 2025 18:08:01 +0800 Subject: [PATCH 2563/2653] Bump AMDGPU version to 6.16.12 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 0cd465a6869d1..e2eccb6f2b84f 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.16.11) +AC_INIT(amdgpu-dkms, 6.16.12) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 502360c9a3913a3c66e308738971951ca1ddaa3e Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Wed, 12 Nov 2025 12:18:14 -0500 Subject: [PATCH 2564/2653] drm/amdkfd: Fix AIS deinit warnings Device manager releases device-specific resources when a driver disconnects from a device, devm_memunmap_pages is redundant. It causes below warning trace when module is removed Call Trace: dump_stack_lvl+0x76/0xa0 dump_stack+0x10/0x20 bad_page+0x76/0x120 free_page_is_bad_report+0x86/0xa0 free_unref_page_prepare+0x279/0x3d0 free_unref_page+0x34/0x180 __free_pages+0x112/0x130 free_pages+0x3d/0x60 free_pagetable+0xc4/0xe0 remove_pud_table+0x1c3/0x270 remove_p4d_table+0xf8/0x1b0 remove_pagetable+0xd7/0x160 arch_remove_memory+0x3d/0x50 memunmap_pages+0xbe/0x300 devm_memremap_pages_release+0xe/0x20 devm_action_release+0x15/0x30 release_nodes+0x45/0xd0 devres_release_all+0x97/0xe0 device_unbind_cleanup+0x12/0x80 device_release_driver_internal+0x230/0x270 driver_detach+0x4a/0xa0 bus_remove_driver+0x83/0x110 driver_unregister+0x2f/0x60 pci_unregister_driver+0x40/0x90 amdgpu_exit+0x15/0x3b [amdgpu] __do_sys_delete_module.constprop.0+0x1a3/0x300 __x64_sys_delete_module+0x12/0x20 x64_sys_call+0x14e9/0x24b0 do_syscall_64+0x81/0x170 entry_SYSCALL_64_after_hwframe+0x78/0x80 Fixes: b70e506746de ("drm/amdkfd: Add AMD Infinity Storage (AIS) support") Signed-off-by: Harish Kasiviswanathan Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdkfd/kfd_ais.c | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c index f4dd34909cfd4..4533393b02249 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c @@ -154,24 +154,7 @@ int kfd_ais_init(struct amdgpu_device *adev) void kfd_ais_deinit(struct amdgpu_device *adev) { - if (adev->kfd.dev->ais_initialized) { - unsigned long pci_start_pfn = PHYS_PFN(pci_resource_start(adev->pdev, 0)); - struct page *p2p_page = NULL; - - if (pfn_valid(pci_start_pfn)) { - p2p_page = pfn_to_page(pci_start_pfn); -#ifdef HAVE_PAGE_PGMAP - if (p2p_page && is_pci_p2pdma_page(p2p_page) && - page_pgmap(p2p_page)) - devm_memunmap_pages(&adev->pdev->dev, page_pgmap(p2p_page)); -#else - if (p2p_page && is_pci_p2pdma_page(p2p_page) && - p2p_page->pgmap) - devm_memunmap_pages(&adev->pdev->dev, p2p_page->pgmap); -#endif - } - adev->kfd.dev->ais_initialized = false; - } + adev->kfd.dev->ais_initialized = false; } int kfd_ais_rw_file(struct amdgpu_device *adev, struct amdgpu_bo *bo, From 908e34696555ce58dbad4266921ed3ea22c2ac42 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 29 Oct 2025 15:36:32 +0100 Subject: [PATCH 2565/2653] drm/amdgpu: avoid memory allocation in the critical code path v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When we run out of VMIDs we need to wait for some to become available. Previously we were using a dma_fence_array for that, but this means that we have to allocate memory. Instead just wait for the first not signaled fence from the least recently used VMID to signal. That is not as efficient since we end up in this function multiple times again, but allocating memory can easily fail or deadlock if we have to wait for memory to become available. v2: remove now unused VM manager fields v3: fix dma_fence reference Signed-off-by: Christian König Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4258 Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 52 +++++++------------------ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 7 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 -- 3 files changed, 14 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c index 3ef5bc95642ca..b2af2cc6826c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c @@ -201,58 +201,34 @@ static int amdgpu_vmid_grab_idle(struct amdgpu_ring *ring, struct amdgpu_device *adev = ring->adev; unsigned vmhub = ring->vm_hub; struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; - struct dma_fence **fences; - unsigned i; + /* If anybody is waiting for a VMID let everybody wait for fairness */ if (!dma_fence_is_signaled(ring->vmid_wait)) { *fence = dma_fence_get(ring->vmid_wait); return 0; } - fences = kmalloc_array(id_mgr->num_ids, sizeof(void *), GFP_NOWAIT); - if (!fences) - return -ENOMEM; - /* Check if we have an idle VMID */ - i = 0; - list_for_each_entry((*idle), &id_mgr->ids_lru, list) { + list_for_each_entry_reverse((*idle), &id_mgr->ids_lru, list) { /* Don't use per engine and per process VMID at the same time */ struct amdgpu_ring *r = adev->vm_manager.concurrent_flush ? NULL : ring; - fences[i] = amdgpu_sync_peek_fence(&(*idle)->active, r); - if (!fences[i]) - break; - ++i; + *fence = amdgpu_sync_peek_fence(&(*idle)->active, r); + if (!(*fence)) + return 0; } - /* If we can't find a idle VMID to use, wait till one becomes available */ - if (&(*idle)->list == &id_mgr->ids_lru) { - u64 fence_context = adev->vm_manager.fence_context + ring->idx; - unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; - struct dma_fence_array *array; - unsigned j; - - *idle = NULL; - for (j = 0; j < i; ++j) - dma_fence_get(fences[j]); - - array = dma_fence_array_create(i, fences, fence_context, - seqno, true); - if (!array) { - for (j = 0; j < i; ++j) - dma_fence_put(fences[j]); - kfree(fences); - return -ENOMEM; - } - - *fence = dma_fence_get(&array->base); - dma_fence_put(ring->vmid_wait); - ring->vmid_wait = &array->base; - return 0; - } - kfree(fences); + /* + * If we can't find a idle VMID to use, wait on a fence from the least + * recently used in the hope that it will be available soon. + */ + *idle = NULL; + dma_fence_put(ring->vmid_wait); + ring->vmid_wait = dma_fence_get(*fence); + /* This is the reference we return */ + dma_fence_get(*fence); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index ca5a825e4665d..a6f466d6fd2a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2886,8 +2886,6 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) */ void amdgpu_vm_manager_init(struct amdgpu_device *adev) { - unsigned i; - /* Concurrent flushes are only possible starting with Vega10 and * are broken on Navi10 and Navi14. */ @@ -2896,11 +2894,6 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev) adev->asic_type == CHIP_NAVI14); amdgpu_vmid_mgr_init(adev); - adev->vm_manager.fence_context = - dma_fence_context_alloc(AMDGPU_MAX_RINGS); - for (i = 0; i < AMDGPU_MAX_RINGS; ++i) - adev->vm_manager.seqno[i] = 0; - spin_lock_init(&adev->vm_manager.prt_lock); atomic_set(&adev->vm_manager.num_prt_users, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 12812408298e3..d13d51df2052f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -457,10 +457,6 @@ struct amdgpu_vm_manager { unsigned int first_kfd_vmid; bool concurrent_flush; - /* Handling of VM fences */ - u64 fence_context; - unsigned seqno[AMDGPU_MAX_RINGS]; - uint64_t max_pfn; uint32_t num_level; uint32_t block_size; From 3211e629faed631394818c5308b348bb96d2bb46 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Tue, 28 Oct 2025 11:16:12 +0100 Subject: [PATCH 2566/2653] drm/amdgpu: use GFP_ATOMIC instead of NOWAIT in the critical path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Otherwise job submissions can fail with ENOMEM. We probably need to re-design the per VMID tracking at some point. Signed-off-by: Christian König Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4258 Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c index b2af2cc6826c4..9cab36322c165 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c @@ -289,7 +289,7 @@ static int amdgpu_vmid_grab_reserved(struct amdgpu_vm *vm, * user of the VMID. */ r = amdgpu_sync_fence(&(*id)->active, &job->base.s_fence->finished, - GFP_NOWAIT); + GFP_ATOMIC); if (r) return r; @@ -349,7 +349,7 @@ static int amdgpu_vmid_grab_used(struct amdgpu_vm *vm, */ r = amdgpu_sync_fence(&(*id)->active, &job->base.s_fence->finished, - GFP_NOWAIT); + GFP_ATOMIC); if (r) return r; @@ -402,7 +402,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring, /* Remember this submission as user of the VMID */ r = amdgpu_sync_fence(&id->active, &job->base.s_fence->finished, - GFP_NOWAIT); + GFP_ATOMIC); if (r) goto error; From 69f622aed94d16e883bf162da3803882c90557da Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Thu, 6 Nov 2025 11:12:37 +0800 Subject: [PATCH 2567/2653] drm/amdgpu: add new performance monitor PSP interfaces Introduce new psp interfaces and structures for performance monitoring hardware control. Signed-off-by: Perry Yuan Reviewed-by: Lijo Lazar Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 22 ++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 18 ++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 022b70522d763..58862d0fa44c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -357,6 +357,28 @@ struct spirom_bo { }; #endif +enum psp_ptl_cmd { + PSP_PTL_PERF_MON_QUERY = 0xA0000000, + PSP_PTL_PERF_MON_SET = 0xA0000001, +}; + +enum psp_ptl_format_type +{ + GFX_FTYPE_I8 = 0x00000000, + GFX_FTYPE_F16 = 0x00000001, + GFX_FTYPE_BF16 = 0x00000002, + GFX_FTYPE_F32 = 0x00000003, + GFX_FTYPE_F64 = 0x00000004, + GFX_FTYPE_INVALID = 0xFFFFFFFF, +}; + +struct psp_ptl_perf_req { + enum psp_ptl_cmd req; + uint32_t ptl_state; + uint32_t pref_format1; + uint32_t pref_format2; +}; + struct psp_context { struct amdgpu_device *adev; struct psp_ring km_ring; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h index 333d59f3eb119..bcb36951dc4cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h +++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h @@ -107,6 +107,7 @@ enum psp_gfx_cmd_id GFX_CMD_ID_CONFIG_SQ_PERFMON = 0x00000046, /* Config CGTT_SQ_CLK_CTRL */ /* Dynamic memory partitioninig (NPS mode change)*/ GFX_CMD_ID_FB_NPS_MODE = 0x00000048, /* Configure memory partitioning mode */ + GFX_CMD_ID_PERF_HW = 0x0000004C, /* performance monitor */ GFX_CMD_ID_FB_FW_RESERV_ADDR = 0x00000050, /* Query FW reservation addr */ GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR = 0x00000051, /* Query FW reservation extended addr */ }; @@ -371,6 +372,13 @@ struct psp_gfx_cmd_fb_memory_part { uint32_t resvd; }; +struct psp_gfx_cmd_req_perf_hw { + uint32_t req; + uint32_t ptl_state; + uint32_t pref_format1; + uint32_t pref_format2; +}; + /* All GFX ring buffer commands. */ union psp_gfx_commands { @@ -387,6 +395,7 @@ union psp_gfx_commands struct psp_gfx_cmd_sriov_spatial_part cmd_spatial_part; struct psp_gfx_cmd_config_sq_perfmon config_sq_perfmon; struct psp_gfx_cmd_fb_memory_part cmd_memory_part; + struct psp_gfx_cmd_req_perf_hw cmd_req_perf_hw; }; struct psp_gfx_uresp_reserved @@ -413,12 +422,21 @@ struct psp_gfx_uresp_fw_reserve_info { uint32_t reserve_size; }; +struct psp_gfx_uresp_perf_hw +{ + uint32_t resp; + uint32_t ptl_state; + uint32_t pref_format1; + uint32_t pref_format2; +}; + /* Union of command-specific responses for GPCOM ring. */ union psp_gfx_uresp { struct psp_gfx_uresp_reserved reserved; struct psp_gfx_uresp_bootcfg boot_cfg; struct psp_gfx_uresp_fwar_db_info fwar_db_info; struct psp_gfx_uresp_fw_reserve_info fw_reserve_info; + struct psp_gfx_uresp_perf_hw perf_hw_info; }; /* Structure of GFX Response buffer. From 47989c953b9c96c53c7968ba3b8d058c38252158 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 4 Nov 2025 17:45:55 +0800 Subject: [PATCH 2568/2653] drm/amdgpu: add psp interfaces for peak tops limiter driver Introduce a Peak Tops Limiter (PTL) driver that dynamically caps engine frequency to ensure delivered TOPS never exceeds a defined TOPS_limit. This initial implementation provides core data structures and kernel-space interfaces (set/get, enable/disable) to manage PTL state. PTL performs a firmware handshake to initialize its state and update predefined format types. It supports updating these format types at runtime while user-space tools automatically switch PTL state, and also allows explicitly switching PTL state via newly added commands. Signed-off-by: Perry Yuan Reviewed-by: Lijo Lazar Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 80 +++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 6 ++ include/uapi/linux/kfd_ioctl.h | 9 +++ 3 files changed, 95 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index c574666525246..4ec1949584e26 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -670,6 +670,8 @@ static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) return "SPATIAL_PARTITION"; case GFX_CMD_ID_FB_NPS_MODE: return "NPS_MODE_CHANGE"; + case GFX_CMD_ID_PERF_HW: + return "PERF MONITORING HW"; default: return "UNKNOWN CMD"; } @@ -1200,6 +1202,84 @@ int psp_memory_partition(struct psp_context *psp, int mode) return ret; } +static int psp_ptl_fmt_verify(struct psp_context *psp, enum amdgpu_ptl_fmt fmt, + uint32_t *ptl_fmt) +{ + struct amdgpu_device *adev = psp->adev; + + if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) + return -EINVAL; + + switch (fmt) { + case AMDGPU_PTL_FMT_I8: + *ptl_fmt = GFX_FTYPE_I8; + break; + case AMDGPU_PTL_FMT_F16: + *ptl_fmt = GFX_FTYPE_F16; + break; + case AMDGPU_PTL_FMT_BF16: + *ptl_fmt = GFX_FTYPE_BF16; + break; + case AMDGPU_PTL_FMT_F32: + *ptl_fmt = GFX_FTYPE_F32; + break; + case AMDGPU_PTL_FMT_F64: + *ptl_fmt = GFX_FTYPE_F64; + break; + default: + return -EINVAL; + } + + return 0; +} + +int psp_performance_monitor_hw(struct psp_context *psp, u32 req_code, + uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2) +{ + struct psp_gfx_cmd_resp *cmd; + uint32_t ptl_fmt1, ptl_fmt2; + int ret; + + if (!psp || !ptl_state || !fmt1 || !fmt2) + return -EINVAL; + + if (amdgpu_sriov_vf(psp->adev)) + return 0; + + if (psp_ptl_fmt_verify(psp, *fmt1, &ptl_fmt1) || + psp_ptl_fmt_verify(psp, *fmt2, &ptl_fmt2)) + return -EINVAL; + + cmd = acquire_psp_cmd_buf(psp); + + cmd->cmd_id = GFX_CMD_ID_PERF_HW; + cmd->cmd.cmd_req_perf_hw.req = req_code; + cmd->cmd.cmd_req_perf_hw.ptl_state = *ptl_state; + cmd->cmd.cmd_req_perf_hw.pref_format1 = ptl_fmt1; + cmd->cmd.cmd_req_perf_hw.pref_format2 = ptl_fmt2; + + ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); + if (ret) + goto out; + + switch (req_code) { + case PSP_PTL_PERF_MON_QUERY: + *ptl_state = cmd->resp.uresp.perf_hw_info.ptl_state; + *fmt1 = cmd->resp.uresp.perf_hw_info.pref_format1; + *fmt2 = cmd->resp.uresp.perf_hw_info.pref_format2; + break; + case PSP_PTL_PERF_MON_SET: + psp->ptl_enabled = *ptl_state; + psp->ptl_fmt1 = ptl_fmt1; + psp->ptl_fmt2 = ptl_fmt2; + break; + } + +out: + release_psp_cmd_buf(psp); + return ret; +} + int psp_spatial_partition(struct psp_context *psp, int mode) { struct psp_gfx_cmd_resp *cmd; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 58862d0fa44c0..eb979108c74d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -469,6 +469,10 @@ struct psp_context { #if defined(CONFIG_DEBUG_FS) struct spirom_bo *spirom_dump_trip; #endif + enum amdgpu_ptl_fmt ptl_fmt1; + enum amdgpu_ptl_fmt ptl_fmt2; + bool ptl_enabled; + bool ptl_hw_supported; }; struct amdgpu_psp_funcs { @@ -644,5 +648,7 @@ int amdgpu_psp_reg_program_no_ring(struct psp_context *psp, uint32_t val, enum psp_reg_prog_id id); void amdgpu_psp_debugfs_init(struct amdgpu_device *adev); +int psp_performance_monitor_hw(struct psp_context *psp, u32 req_code, + u32 *ptl_state, u32 *fmt1, u32 *fmt2); #endif diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index dbe848a1490b1..58cb6b04f10fd 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1700,6 +1700,15 @@ enum kfd_ioctl_pc_sample_op { KFD_IOCTL_PCS_OP_STOP, }; +enum amdgpu_ptl_fmt { + AMDGPU_PTL_FMT_I8 = 0, + AMDGPU_PTL_FMT_F16 = 1, + AMDGPU_PTL_FMT_BF16 = 2, + AMDGPU_PTL_FMT_F32 = 3, + AMDGPU_PTL_FMT_F64 = 4, + AMDGPU_PTL_FMT_INVALID = 5, +}; + /* Values have to be a power of 2*/ #define KFD_IOCTL_PCS_FLAG_POWER_OF_2 0x00000001 From 949f93a842543eb7475b55e1b3722afd7b599129 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 4 Nov 2025 17:53:18 +0800 Subject: [PATCH 2569/2653] drm/amdgpu: add PTL enable/query gfx control support for GC 9.4.4 Introduce hardware detection, runtime state tracking and a kgd->ptl_ctrl() callback to enable/disable/query PTL via the PSP performance-monitor interface (commands 0xA0000000/1). The driver now exposes PTL capability to KFD and keeps the software state in sync with the hardware. Signed-off-by: Perry Yuan Reviewed-by: Lijo Lazar Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 36 +++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 25bedf39390ab..a81400fdb674c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2393,11 +2393,45 @@ static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) return r; } +static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool state) +{ + uint32_t fmt1, fmt2; + uint32_t ptl_state = state ? 1 : 0; + int r; + + if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) + return -ENOTSUPP; + + if (!adev->psp.funcs) + return -EOPNOTSUPP; + + if (!adev->psp.ptl_hw_supported) { + fmt1 = GFX_FTYPE_I8; + fmt2 = GFX_FTYPE_BF16; + } else { + fmt1 = adev->psp.ptl_fmt1; + fmt2 = adev->psp.ptl_fmt2; + } + + /* initialize PTL with default formats: GFX_FTYPE_I8 & GFX_FTYPE_BF16 */ + r = psp_performance_monitor_hw(&adev->psp, PSP_PTL_PERF_MON_SET, &ptl_state, + &fmt1, &fmt2); + if (r) + return r; + + adev->psp.ptl_hw_supported = true; + + return 0; +} + static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; int i, num_xcc; + if (adev->psp.ptl_hw_supported) + gfx_v9_4_3_perf_monitor_ptl_init(adev, 0); + amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.spm_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); @@ -2677,6 +2711,8 @@ static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) adev->gfx.ras->enable_watchdog_timer) adev->gfx.ras->enable_watchdog_timer(adev); + gfx_v9_4_3_perf_monitor_ptl_init(adev, 1); + return 0; } From ce6d867e7cbf31361d5e1e3d483d2bd7859f143f Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 4 Nov 2025 17:57:30 +0800 Subject: [PATCH 2570/2653] drm/amdkfd: add kgd control interface for ptl Add kgd->ptl_ctrl() callback so KFD can query/enable/disable PTL state through the PSP performance monitor interface. Signed-off-by: Perry Yuan Reviewed-by: Lijo Lazar Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 11 +++++++++++ drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 5 +++++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c index a577e1ff00401..a6058a1c5a3e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c @@ -550,6 +550,16 @@ static uint32_t kgd_v9_4_3_trigger_pc_sample_trap(struct amdgpu_device *adev, target_simd, target_wave_slot, method, inst); } +static uint32_t kgd_v9_4_3_ptl_ctrl(struct amdgpu_device *adev, + uint32_t cmd, + uint32_t *ptl_state, + enum amdgpu_ptl_fmt *fmt1, + enum amdgpu_ptl_fmt *fmt2) +{ + return psp_performance_monitor_hw(&adev->psp, cmd, + ptl_state, fmt1, fmt2); +} + static uint32_t kgd_v9_4_3_setup_stoch_sampling(struct amdgpu_device *adev, uint32_t compute_vmid_bitmap, bool enable, @@ -613,4 +623,5 @@ const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .trigger_pc_sample_trap = kgd_v9_4_3_trigger_pc_sample_trap, .override_core_cg = kgd_gfx_v9_4_3_override_core_cg, .setup_stoch_sampling = kgd_v9_4_3_setup_stoch_sampling, + .ptl_ctrl = kgd_v9_4_3_ptl_ctrl, }; diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index df5b578a5e6b1..e1c25444a0fab 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -355,6 +355,11 @@ struct kfd2kgd_calls { enum kfd_ioctl_pc_sample_type type, uint64_t intval, uint32_t inst); + uint32_t (*ptl_ctrl)(struct amdgpu_device *adev, + uint32_t cmd, + uint32_t *ptl_state, + enum amdgpu_ptl_fmt *fmt1, + enum amdgpu_ptl_fmt *fmt2); }; #endif /* KGD_KFD_INTERFACE_H_INCLUDED */ From e19fc2a6ad3d1fa5537e9c0e583b34b36b0cbbab Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 11 Nov 2025 15:41:12 +0800 Subject: [PATCH 2571/2653] drm/amdgpu: integrate PTL control with PMC device locking Combine PTL hardware control with the existing PMC device locking mechanism to ensure proper synchronization and hardware state management during profiling operations. Signed-off-by: Perry Yuan Reviewed-by: Lijo Lazar Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 7dca694561504..91ef095147baa 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1888,6 +1888,27 @@ static int kfd_ioctl_pc_sample(struct file *filep, return ret; } +static int kfd_ptl_control(struct kfd_process_device *pdd, bool enable) +{ + struct amdgpu_device *adev = pdd->dev->adev; + enum amdgpu_ptl_fmt pref_format1 = adev->psp.ptl_fmt1; + enum amdgpu_ptl_fmt pref_format2 = adev->psp.ptl_fmt2; + uint32_t ptl_state = enable ? 1 : 0; + int ret; + + if (!adev->psp.ptl_hw_supported) + return -EOPNOTSUPP; + + if (!pdd->dev->kfd2kgd || !pdd->dev->kfd2kgd->ptl_ctrl) + return -EOPNOTSUPP; + + ret = pdd->dev->kfd2kgd->ptl_ctrl(adev, PSP_PTL_PERF_MON_SET, + &ptl_state, + &pref_format1, + &pref_format2); + return ret; +} + static int criu_checkpoint_process(struct kfd_process *p, uint8_t __user *user_priv_data, uint64_t *priv_offset) @@ -3396,6 +3417,7 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, if (!kfd->profiler_process) { kfd->profiler_process = p; status = 0; + kfd_ptl_control(pdd, false); } else if (kfd->profiler_process == p) { status = -EALREADY; } else { @@ -3404,6 +3426,7 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, } else if (op == 0 && kfd->profiler_process == p) { kfd->profiler_process = NULL; status = 0; + kfd_ptl_control(pdd, true); } mutex_unlock(&kfd->profiler_lock); From 5f3a2d6c81c22c2015c63c0d752aea09aeea6b05 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Fri, 14 Nov 2025 00:15:54 +0800 Subject: [PATCH 2572/2653] drm/amdkfd: enable PTL while kfd_process profiler release When the profiler is released it needs to enable PTL again to make sure PTL state is restored to preivous state. Signed-off-by: Perry Yuan Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 ++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 91ef095147baa..1f31932d1bed8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1888,7 +1888,7 @@ static int kfd_ioctl_pc_sample(struct file *filep, return ret; } -static int kfd_ptl_control(struct kfd_process_device *pdd, bool enable) +int kfd_ptl_control(struct kfd_process_device *pdd, bool enable) { struct amdgpu_device *adev = pdd->dev->adev; enum amdgpu_ptl_fmt pref_format1 = adev->psp.ptl_fmt1; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index cfcf8f30b2341..36b4b9afe6a53 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1748,6 +1748,8 @@ int kfd_ais_init(struct amdgpu_device *adev); void kfd_ais_deinit(struct amdgpu_device *adev); int kfd_ais_rw_file(struct amdgpu_device *adev, struct amdgpu_bo *bo, struct kfd_ais_in_args *in, uint64_t *size_copied); +/* PTL support */ +int kfd_ptl_control(struct kfd_process_device *pdd, bool enable); /* Debugfs */ #if defined(CONFIG_DEBUG_FS) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index b6dc44395c408..5b87e0999a447 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1042,6 +1042,7 @@ static void kfd_process_profiler_release(struct kfd_process *p, struct kfd_proce mutex_lock(&pdd->dev->kfd->profiler_lock); if (pdd->dev->kfd->profiler_process == p) { pdd->qpd.dqm->ops.set_perfcount(pdd->qpd.dqm, 0); + kfd_ptl_control(pdd, true); pdd->dev->kfd->profiler_process = NULL; } mutex_unlock(&pdd->dev->kfd->profiler_lock); From 2f890ff6f1ac388ae3771b40dead1649e15db45d Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Tue, 11 Nov 2025 16:56:35 +0800 Subject: [PATCH 2573/2653] drm/amdgpu: Synchronize sriov host to add block_mmsch bit field Synchronize sriov host to add block_mmsch bit field. Signed-off-by: YiPeng Chai Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h index ba23bf982d7b8..3cdb1e0eca377 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h @@ -199,8 +199,9 @@ union amd_sriov_ras_caps { uint64_t block_jpeg : 1; uint64_t block_ih : 1; uint64_t block_mpio : 1; + uint64_t block_mmsch : 1; uint64_t poison_propogation_mode : 1; - uint64_t reserved : 44; + uint64_t reserved : 43; } bits; uint64_t all; }; From 6af341bd866828fe80fa0903a07fd45c6126a253 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Mon, 21 Jul 2025 15:22:27 +0800 Subject: [PATCH 2574/2653] drm/amdgpu: Add lock to serialize sriov command execution Add lock to serialize sriov command execution. Signed-off-by: YiPeng Chai Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 2 ++ drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 17 ++++++++++++----- 3 files changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index f2ce8f506aa8a..47a6ce4fdc744 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -917,6 +917,7 @@ static void amdgpu_virt_init_ras(struct amdgpu_device *adev) RATELIMIT_MSG_ON_RELEASE); mutex_init(&adev->virt.ras.ras_telemetry_mutex); + mutex_init(&adev->virt.access_req_mutex); adev->virt.ras.cper_rptr = 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 4fd194a9a972e..01d5bca2dee16 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -325,6 +325,8 @@ struct amdgpu_virt { /* Spinlock to protect access to the RLCG register interface */ spinlock_t rlcg_reg_lock; + struct mutex access_req_mutex; + union amd_sriov_ras_caps ras_en_caps; union amd_sriov_ras_caps ras_telemetry_en_caps; struct amdgpu_virt_ras ras; diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c index cd5b2f07edb89..e7cd07383d56e 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c @@ -173,13 +173,17 @@ static void xgpu_nv_mailbox_trans_msg (struct amdgpu_device *adev, static int xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev, enum idh_request req, u32 data1, u32 data2, u32 data3) { - int r, retry = 1; + struct amdgpu_virt *virt = &adev->virt; + int r = 0, retry = 1; enum idh_event event = -1; + mutex_lock(&virt->access_req_mutex); send_request: - if (amdgpu_ras_is_rma(adev)) - return -ENODEV; + if (amdgpu_ras_is_rma(adev)) { + r = -ENODEV; + goto out; + } xgpu_nv_mailbox_trans_msg(adev, req, data1, data2, data3); @@ -217,7 +221,7 @@ static int xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev, if (req != IDH_REQ_GPU_INIT_DATA) { dev_err(adev->dev, "Doesn't get msg:%d from pf, error=%d\n", event, r); - return r; + goto out; } else /* host doesn't support REQ_GPU_INIT_DATA handshake */ adev->virt.req_init_data_ver = 0; } else { @@ -246,7 +250,10 @@ static int xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev, } } - return 0; +out: + mutex_unlock(&virt->access_req_mutex); + + return r; } static int xgpu_nv_send_access_requests(struct amdgpu_device *adev, From a14278769ed16c8a34b9463cb1ba553691c19262 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Thu, 23 Oct 2025 14:47:07 +0800 Subject: [PATCH 2575/2653] drm/amdgpu: Fix the issue of missing ras message on sriov host This code only applies to amdgpu processing poison consumption after uniras is enabled, but not to sriov. Signed-off-by: YiPeng Chai Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 15 --------------- drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 10 ++++++++++ 2 files changed, 10 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 39d712e3e692a..70f5334775a6f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -36,7 +36,6 @@ #include "amdgpu_ras.h" #include "amdgpu_umc.h" #include "amdgpu_reset.h" -#include "amdgpu_ras_mgr.h" /* Total memory size in system memory and all GPU VRAM. Used to * estimate worst case amount of memory to reserve for page tables @@ -757,20 +756,6 @@ void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device *ad enum amdgpu_ras_block block, uint16_t pasid, pasid_notify pasid_fn, void *data, uint32_t reset) { - - if (amdgpu_uniras_enabled(adev)) { - struct ras_ih_info ih_info; - - memset(&ih_info, 0, sizeof(ih_info)); - ih_info.block = block; - ih_info.pasid = pasid; - ih_info.reset = reset; - ih_info.pasid_fn = pasid_fn; - ih_info.data = data; - amdgpu_ras_mgr_handle_consumer_interrupt(adev, &ih_info); - return; - } - amdgpu_umc_pasid_poison_handler(adev, block, pasid, pasid_fn, data, reset); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c index f540ee37a4acc..a662758b4f75d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c @@ -24,6 +24,7 @@ #include #include "amdgpu.h" #include "umc_v6_7.h" +#include "amdgpu_ras_mgr.h" #define MAX_UMC_POISON_POLLING_TIME_SYNC 20 //ms #define MAX_UMC_HASH_STRING_SIZE 256 @@ -273,6 +274,15 @@ int amdgpu_umc_pasid_poison_handler(struct amdgpu_device *adev, } amdgpu_ras_error_data_fini(&err_data); + } else if (amdgpu_uniras_enabled(adev)) { + struct ras_ih_info ih_info = {0}; + + ih_info.block = block; + ih_info.pasid = pasid; + ih_info.reset = reset; + ih_info.pasid_fn = pasid_fn; + ih_info.data = data; + amdgpu_ras_mgr_handle_consumer_interrupt(adev, &ih_info); } else { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); int ret; From c7cb16d06781c52e5b5179212ed14162e825be7f Mon Sep 17 00:00:00 2001 From: George Shen Date: Wed, 29 Oct 2025 11:27:32 -0400 Subject: [PATCH 2576/2653] drm/amd/display: Add interface to capture expected HW state from SW state [Why] To debug certain issues, such as underflow, it is common practice to dump the HW state of all registers for analysis. The first thing to check with the dump is to ensure all values are programmed as expected according to SW state. [How] Add interface to DC to capture expected HW register values based on SW state. Reviewed-by: Dillon Varone Signed-off-by: George Shen Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 561 +++++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dc.h | 487 ++++++++++++++++++++ 2 files changed, 1048 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 3d90ce0815c21..a14016a3bea4f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -6512,6 +6512,567 @@ void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst, out_data->fams = dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching; } +bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state) +{ + struct dc_state *context; + struct resource_context *res_ctx; + int i; + + if (!dc || !dc->current_state || !state) { + if (state) + state->state_valid = false; + return false; + } + + /* Initialize the state structure */ + memset(state, 0, sizeof(struct dc_register_software_state)); + + context = dc->current_state; + res_ctx = &context->res_ctx; + + /* Count active pipes and streams */ + state->active_pipe_count = 0; + state->active_stream_count = context->stream_count; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (res_ctx->pipe_ctx[i].stream) + state->active_pipe_count++; + } + + /* Capture HUBP programming state for each pipe */ + for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; + + state->hubp[i].valid_stream = false; + if (!pipe_ctx->stream) + continue; + + state->hubp[i].valid_stream = true; + + /* HUBP register programming variables */ + if (pipe_ctx->stream_res.tg) + state->hubp[i].vtg_sel = pipe_ctx->stream_res.tg->inst; + + state->hubp[i].hubp_clock_enable = (pipe_ctx->plane_res.hubp != NULL) ? 1 : 0; + + state->hubp[i].valid_plane_state = false; + if (pipe_ctx->plane_state) { + state->hubp[i].valid_plane_state = true; + state->hubp[i].surface_pixel_format = pipe_ctx->plane_state->format; + state->hubp[i].rotation_angle = pipe_ctx->plane_state->rotation; + state->hubp[i].h_mirror_en = pipe_ctx->plane_state->horizontal_mirror ? 1 : 0; + + /* Surface size */ + if (pipe_ctx->plane_state->plane_size.surface_size.width > 0) { + state->hubp[i].surface_size_width = pipe_ctx->plane_state->plane_size.surface_size.width; + state->hubp[i].surface_size_height = pipe_ctx->plane_state->plane_size.surface_size.height; + } + + /* Viewport dimensions from scaler data */ + if (pipe_ctx->plane_state->src_rect.width > 0) { + state->hubp[i].pri_viewport_width = pipe_ctx->plane_state->src_rect.width; + state->hubp[i].pri_viewport_height = pipe_ctx->plane_state->src_rect.height; + state->hubp[i].pri_viewport_x_start = pipe_ctx->plane_state->src_rect.x; + state->hubp[i].pri_viewport_y_start = pipe_ctx->plane_state->src_rect.y; + } + + /* DCC settings */ + state->hubp[i].surface_dcc_en = (pipe_ctx->plane_state->dcc.enable) ? 1 : 0; + state->hubp[i].surface_dcc_ind_64b_blk = pipe_ctx->plane_state->dcc.independent_64b_blks; + state->hubp[i].surface_dcc_ind_128b_blk = pipe_ctx->plane_state->dcc.dcc_ind_blk; + + /* Surface pitch */ + state->hubp[i].surface_pitch = pipe_ctx->plane_state->plane_size.surface_pitch; + state->hubp[i].meta_pitch = pipe_ctx->plane_state->dcc.meta_pitch; + state->hubp[i].chroma_pitch = pipe_ctx->plane_state->plane_size.chroma_pitch; + state->hubp[i].meta_pitch_c = pipe_ctx->plane_state->dcc.meta_pitch_c; + + /* Surface addresses - primary */ + state->hubp[i].primary_surface_address_low = pipe_ctx->plane_state->address.grph.addr.low_part; + state->hubp[i].primary_surface_address_high = pipe_ctx->plane_state->address.grph.addr.high_part; + state->hubp[i].primary_meta_surface_address_low = pipe_ctx->plane_state->address.grph.meta_addr.low_part; + state->hubp[i].primary_meta_surface_address_high = pipe_ctx->plane_state->address.grph.meta_addr.high_part; + + /* TMZ settings */ + state->hubp[i].primary_surface_tmz = pipe_ctx->plane_state->address.tmz_surface; + state->hubp[i].primary_meta_surface_tmz = pipe_ctx->plane_state->address.tmz_surface; + + /* Tiling configuration */ + state->hubp[i].min_dc_gfx_version9 = false; + if (pipe_ctx->plane_state->tiling_info.gfxversion >= DcGfxVersion9) { + state->hubp[i].min_dc_gfx_version9 = true; + state->hubp[i].sw_mode = pipe_ctx->plane_state->tiling_info.gfx9.swizzle; + state->hubp[i].num_pipes = pipe_ctx->plane_state->tiling_info.gfx9.num_pipes; + state->hubp[i].num_banks = pipe_ctx->plane_state->tiling_info.gfx9.num_banks; + state->hubp[i].pipe_interleave = pipe_ctx->plane_state->tiling_info.gfx9.pipe_interleave; + state->hubp[i].num_shader_engines = pipe_ctx->plane_state->tiling_info.gfx9.num_shader_engines; + state->hubp[i].num_rb_per_se = pipe_ctx->plane_state->tiling_info.gfx9.num_rb_per_se; + state->hubp[i].num_pkrs = pipe_ctx->plane_state->tiling_info.gfx9.num_pkrs; + } + } + + /* DML Request Size Configuration */ + if (pipe_ctx->rq_regs.rq_regs_l.chunk_size > 0) { + state->hubp[i].rq_chunk_size = pipe_ctx->rq_regs.rq_regs_l.chunk_size; + state->hubp[i].rq_min_chunk_size = pipe_ctx->rq_regs.rq_regs_l.min_chunk_size; + state->hubp[i].rq_meta_chunk_size = pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size; + state->hubp[i].rq_min_meta_chunk_size = pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size; + state->hubp[i].rq_dpte_group_size = pipe_ctx->rq_regs.rq_regs_l.dpte_group_size; + state->hubp[i].rq_mpte_group_size = pipe_ctx->rq_regs.rq_regs_l.mpte_group_size; + state->hubp[i].rq_swath_height_l = pipe_ctx->rq_regs.rq_regs_l.swath_height; + state->hubp[i].rq_pte_row_height_l = pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear; + } + + /* Chroma request size configuration */ + if (pipe_ctx->rq_regs.rq_regs_c.chunk_size > 0) { + state->hubp[i].rq_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.chunk_size; + state->hubp[i].rq_min_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.min_chunk_size; + state->hubp[i].rq_meta_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.meta_chunk_size; + state->hubp[i].rq_min_meta_chunk_size_c = pipe_ctx->rq_regs.rq_regs_c.min_meta_chunk_size; + state->hubp[i].rq_dpte_group_size_c = pipe_ctx->rq_regs.rq_regs_c.dpte_group_size; + state->hubp[i].rq_mpte_group_size_c = pipe_ctx->rq_regs.rq_regs_c.mpte_group_size; + state->hubp[i].rq_swath_height_c = pipe_ctx->rq_regs.rq_regs_c.swath_height; + state->hubp[i].rq_pte_row_height_c = pipe_ctx->rq_regs.rq_regs_c.pte_row_height_linear; + } + + /* DML expansion modes */ + state->hubp[i].drq_expansion_mode = pipe_ctx->rq_regs.drq_expansion_mode; + state->hubp[i].prq_expansion_mode = pipe_ctx->rq_regs.prq_expansion_mode; + state->hubp[i].mrq_expansion_mode = pipe_ctx->rq_regs.mrq_expansion_mode; + state->hubp[i].crq_expansion_mode = pipe_ctx->rq_regs.crq_expansion_mode; + + /* DML DLG parameters - nominal */ + state->hubp[i].dst_y_per_vm_vblank = pipe_ctx->dlg_regs.dst_y_per_vm_vblank; + state->hubp[i].dst_y_per_row_vblank = pipe_ctx->dlg_regs.dst_y_per_row_vblank; + state->hubp[i].dst_y_per_vm_flip = pipe_ctx->dlg_regs.dst_y_per_vm_flip; + state->hubp[i].dst_y_per_row_flip = pipe_ctx->dlg_regs.dst_y_per_row_flip; + + /* DML prefetch settings */ + state->hubp[i].dst_y_prefetch = pipe_ctx->dlg_regs.dst_y_prefetch; + state->hubp[i].vratio_prefetch = pipe_ctx->dlg_regs.vratio_prefetch; + state->hubp[i].vratio_prefetch_c = pipe_ctx->dlg_regs.vratio_prefetch_c; + + /* TTU parameters */ + state->hubp[i].qos_level_low_wm = pipe_ctx->ttu_regs.qos_level_low_wm; + state->hubp[i].qos_level_high_wm = pipe_ctx->ttu_regs.qos_level_high_wm; + state->hubp[i].qos_level_flip = pipe_ctx->ttu_regs.qos_level_flip; + state->hubp[i].min_ttu_vblank = pipe_ctx->ttu_regs.min_ttu_vblank; + } + + /* Capture HUBBUB programming state */ + if (dc->res_pool->hubbub) { + /* Individual DET buffer sizes - software state variables that program DET registers */ + for (i = 0; i < 4 && i < dc->res_pool->pipe_count; i++) { + uint32_t det_size = res_ctx->pipe_ctx[i].det_buffer_size_kb; + switch (i) { + case 0: + state->hubbub.det0_size = det_size; + break; + case 1: + state->hubbub.det1_size = det_size; + break; + case 2: + state->hubbub.det2_size = det_size; + break; + case 3: + state->hubbub.det3_size = det_size; + break; + } + } + + /* Compression buffer configuration - software state that programs COMPBUF_SIZE register */ + // TODO: Handle logic for legacy DCN pre-DCN401 + state->hubbub.compbuf_size = context->bw_ctx.bw.dcn.arb_regs.compbuf_size; + } + + /* Capture DPP programming state for each pipe */ + for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; + + if (!pipe_ctx->stream) + continue; + + state->dpp[i].dpp_clock_enable = (pipe_ctx->plane_res.dpp != NULL) ? 1 : 0; + + if (pipe_ctx->plane_state && pipe_ctx->plane_res.scl_data.recout.width > 0) { + /* Access dscl_prog_data directly - this contains the actual software state used for register programming */ + struct dscl_prog_data *dscl_data = &pipe_ctx->plane_res.scl_data.dscl_prog_data; + + /* Recout (Rectangle of Interest) configuration - software state that programs RECOUT registers */ + state->dpp[i].recout_start_x = dscl_data->recout.x; + state->dpp[i].recout_start_y = dscl_data->recout.y; + state->dpp[i].recout_width = dscl_data->recout.width; + state->dpp[i].recout_height = dscl_data->recout.height; + + /* MPC (Multiple Pipe/Plane Combiner) size - software state that programs MPC_SIZE registers */ + state->dpp[i].mpc_width = dscl_data->mpc_size.width; + state->dpp[i].mpc_height = dscl_data->mpc_size.height; + + /* DSCL mode - software state that programs SCL_MODE registers */ + state->dpp[i].dscl_mode = dscl_data->dscl_mode; + + /* Scaler ratios - software state that programs scale ratio registers (use actual programmed ratios) */ + state->dpp[i].horz_ratio_int = dscl_data->ratios.h_scale_ratio >> 19; // Extract integer part from programmed ratio + state->dpp[i].vert_ratio_int = dscl_data->ratios.v_scale_ratio >> 19; // Extract integer part from programmed ratio + + /* Basic scaler taps - software state that programs tap control registers (use actual programmed taps) */ + state->dpp[i].h_taps = dscl_data->taps.h_taps + 1; // dscl_prog_data.taps stores (taps - 1), so add 1 back + state->dpp[i].v_taps = dscl_data->taps.v_taps + 1; // dscl_prog_data.taps stores (taps - 1), so add 1 back + } + } + + /* Capture essential clock state for underflow analysis */ + if (dc->clk_mgr && dc->clk_mgr->clks.dispclk_khz > 0) { + /* Core display clocks affecting bandwidth and timing */ + state->dccg.dispclk_khz = dc->clk_mgr->clks.dispclk_khz; + + /* Per-pipe clock configuration - only capture what's essential */ + for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; + if (pipe_ctx->stream) { + /* Essential clocks that directly affect underflow risk */ + state->dccg.dppclk_khz[i] = dc->clk_mgr->clks.dppclk_khz; + state->dccg.pixclk_khz[i] = pipe_ctx->stream->timing.pix_clk_100hz / 10; + state->dccg.dppclk_enable[i] = 1; + + /* DP stream clock only for DP signals */ + if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || + pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { + state->dccg.dpstreamclk_enable[i] = 1; + } else { + state->dccg.dpstreamclk_enable[i] = 0; + } + } else { + /* Inactive pipe - no clocks */ + state->dccg.dppclk_khz[i] = 0; + state->dccg.pixclk_khz[i] = 0; + state->dccg.dppclk_enable[i] = 0; + if (i < 4) { + state->dccg.dpstreamclk_enable[i] = 0; + } + } + } + + /* DSC clock state - only when actually using DSC */ + for (i = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe_ctx = (i < dc->res_pool->pipe_count) ? &res_ctx->pipe_ctx[i] : NULL; + if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->timing.dsc_cfg.num_slices_h > 0) { + state->dccg.dscclk_khz[i] = 400000; /* Typical DSC clock frequency */ + } else { + state->dccg.dscclk_khz[i] = 0; + } + } + + /* SYMCLK32 LE Control - only the essential HPO state for underflow analysis */ + for (i = 0; i < 2; i++) { + state->dccg.symclk32_le_enable[i] = 0; /* Default: disabled */ + } + + } + + /* Capture essential DSC configuration for underflow analysis */ + for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; + + if (pipe_ctx->stream && pipe_ctx->stream->timing.dsc_cfg.num_slices_h > 0) { + /* DSC is enabled - capture essential configuration */ + state->dsc[i].dsc_clock_enable = 1; + + /* DSC configuration affecting bandwidth and timing */ + struct dc_dsc_config *dsc_cfg = &pipe_ctx->stream->timing.dsc_cfg; + state->dsc[i].dsc_num_slices_h = dsc_cfg->num_slices_h; + state->dsc[i].dsc_num_slices_v = dsc_cfg->num_slices_v; + state->dsc[i].dsc_bits_per_pixel = dsc_cfg->bits_per_pixel; + + /* OPP pipe source for DSC forwarding */ + if (pipe_ctx->stream_res.opp) { + state->dsc[i].dscrm_dsc_forward_enable = 1; + state->dsc[i].dscrm_dsc_opp_pipe_source = pipe_ctx->stream_res.opp->inst; + } else { + state->dsc[i].dscrm_dsc_forward_enable = 0; + state->dsc[i].dscrm_dsc_opp_pipe_source = 0; + } + } else { + /* DSC not enabled - clear all fields */ + memset(&state->dsc[i], 0, sizeof(state->dsc[i])); + } + } + + /* Capture MPC programming state - comprehensive register field coverage */ + for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; + + if (pipe_ctx->plane_state && pipe_ctx->stream) { + struct dc_plane_state *plane_state = pipe_ctx->plane_state; + + /* MPCC blending tree and mode control - capture actual blend configuration */ + state->mpc.mpcc_mode[i] = (plane_state->blend_tf.type != TF_TYPE_BYPASS) ? 1 : 0; + state->mpc.mpcc_alpha_blend_mode[i] = plane_state->per_pixel_alpha ? 1 : 0; + state->mpc.mpcc_alpha_multiplied_mode[i] = plane_state->pre_multiplied_alpha ? 1 : 0; + state->mpc.mpcc_blnd_active_overlap_only[i] = 0; /* Default - no overlap restriction */ + state->mpc.mpcc_global_alpha[i] = plane_state->global_alpha_value; + state->mpc.mpcc_global_gain[i] = plane_state->global_alpha ? 255 : 0; + state->mpc.mpcc_bg_bpc[i] = 8; /* Standard 8-bit background */ + state->mpc.mpcc_bot_gain_mode[i] = 0; /* Standard gain mode */ + + /* MPCC blending tree connections - capture tree topology */ + if (pipe_ctx->bottom_pipe) { + state->mpc.mpcc_bot_sel[i] = pipe_ctx->bottom_pipe->pipe_idx; + } else { + state->mpc.mpcc_bot_sel[i] = 0xF; /* No bottom connection */ + } + state->mpc.mpcc_top_sel[i] = pipe_ctx->pipe_idx; /* This pipe's DPP ID */ + + /* MPCC output gamma control - capture gamma programming */ + if (plane_state->gamma_correction.type != GAMMA_CS_TFM_1D && plane_state->gamma_correction.num_entries > 0) { + state->mpc.mpcc_ogam_mode[i] = 1; /* Gamma enabled */ + state->mpc.mpcc_ogam_select[i] = 0; /* Bank A selection */ + state->mpc.mpcc_ogam_pwl_disable[i] = 0; /* PWL enabled */ + } else { + state->mpc.mpcc_ogam_mode[i] = 0; /* Bypass mode */ + state->mpc.mpcc_ogam_select[i] = 0; + state->mpc.mpcc_ogam_pwl_disable[i] = 1; /* PWL disabled */ + } + + /* MPCC pipe assignment and operational status */ + if (pipe_ctx->stream_res.opp) { + state->mpc.mpcc_opp_id[i] = pipe_ctx->stream_res.opp->inst; + } else { + state->mpc.mpcc_opp_id[i] = 0xF; /* No OPP assignment */ + } + + /* MPCC status indicators - active pipe state */ + state->mpc.mpcc_idle[i] = 0; /* Active pipe - not idle */ + state->mpc.mpcc_busy[i] = 1; /* Active pipe - busy processing */ + + } else { + /* Pipe not active - set disabled/idle state for all fields */ + state->mpc.mpcc_mode[i] = 0; + state->mpc.mpcc_alpha_blend_mode[i] = 0; + state->mpc.mpcc_alpha_multiplied_mode[i] = 0; + state->mpc.mpcc_blnd_active_overlap_only[i] = 0; + state->mpc.mpcc_global_alpha[i] = 0; + state->mpc.mpcc_global_gain[i] = 0; + state->mpc.mpcc_bg_bpc[i] = 0; + state->mpc.mpcc_bot_gain_mode[i] = 0; + state->mpc.mpcc_bot_sel[i] = 0xF; /* No bottom connection */ + state->mpc.mpcc_top_sel[i] = 0xF; /* No top connection */ + state->mpc.mpcc_ogam_mode[i] = 0; /* Bypass */ + state->mpc.mpcc_ogam_select[i] = 0; + state->mpc.mpcc_ogam_pwl_disable[i] = 1; /* PWL disabled */ + state->mpc.mpcc_opp_id[i] = 0xF; /* No OPP assignment */ + state->mpc.mpcc_idle[i] = 1; /* Idle */ + state->mpc.mpcc_busy[i] = 0; /* Not busy */ + } + } + + /* Capture OPP programming state for each pipe - comprehensive register field coverage */ + for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; + + if (!pipe_ctx->stream) + continue; + + if (pipe_ctx->stream_res.opp) { + struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; + + /* OPP Pipe Control */ + state->opp[i].opp_pipe_clock_enable = 1; /* Active pipe has clock enabled */ + + /* Display Pattern Generator (DPG) Control - 19 fields */ + if (pipe_ctx->stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) { + state->opp[i].dpg_enable = 1; + } else { + /* Video mode - DPG disabled */ + state->opp[i].dpg_enable = 0; + } + + /* Format Control (FMT) - 18 fields */ + state->opp[i].fmt_pixel_encoding = timing->pixel_encoding; + + /* Chroma subsampling mode based on pixel encoding */ + if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) { + state->opp[i].fmt_subsampling_mode = 1; /* 4:2:0 subsampling */ + } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { + state->opp[i].fmt_subsampling_mode = 2; /* 4:2:2 subsampling */ + } else { + state->opp[i].fmt_subsampling_mode = 0; /* No subsampling (4:4:4) */ + } + + state->opp[i].fmt_cbcr_bit_reduction_bypass = (timing->pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0; + state->opp[i].fmt_stereosync_override = (timing->timing_3d_format != TIMING_3D_FORMAT_NONE) ? 1 : 0; + + /* Dithering control based on bit depth */ + if (timing->display_color_depth < COLOR_DEPTH_121212) { + state->opp[i].fmt_spatial_dither_frame_counter_max = 15; /* Typical frame counter max */ + state->opp[i].fmt_spatial_dither_frame_counter_bit_swap = 0; /* No bit swapping */ + state->opp[i].fmt_spatial_dither_enable = 1; + state->opp[i].fmt_spatial_dither_mode = 0; /* Spatial dithering mode */ + state->opp[i].fmt_spatial_dither_depth = timing->display_color_depth; + state->opp[i].fmt_temporal_dither_enable = 0; /* Spatial dithering preferred */ + } else { + state->opp[i].fmt_spatial_dither_frame_counter_max = 0; + state->opp[i].fmt_spatial_dither_frame_counter_bit_swap = 0; + state->opp[i].fmt_spatial_dither_enable = 0; + state->opp[i].fmt_spatial_dither_mode = 0; + state->opp[i].fmt_spatial_dither_depth = 0; + state->opp[i].fmt_temporal_dither_enable = 0; + } + + /* Truncation control for bit depth reduction */ + if (timing->display_color_depth < COLOR_DEPTH_121212) { + state->opp[i].fmt_truncate_enable = 1; + state->opp[i].fmt_truncate_depth = timing->display_color_depth; + state->opp[i].fmt_truncate_mode = 0; /* Round mode */ + } else { + state->opp[i].fmt_truncate_enable = 0; + state->opp[i].fmt_truncate_depth = 0; + state->opp[i].fmt_truncate_mode = 0; + } + + /* Data clamping control */ + state->opp[i].fmt_clamp_data_enable = 1; /* Clamping typically enabled */ + state->opp[i].fmt_clamp_color_format = timing->pixel_encoding; + + /* Dynamic expansion for limited range content */ + if (timing->pixel_encoding != PIXEL_ENCODING_RGB) { + state->opp[i].fmt_dynamic_exp_enable = 1; /* YCbCr typically needs expansion */ + state->opp[i].fmt_dynamic_exp_mode = 0; /* Standard expansion */ + } else { + state->opp[i].fmt_dynamic_exp_enable = 0; /* RGB typically full range */ + state->opp[i].fmt_dynamic_exp_mode = 0; + } + + /* Legacy field for compatibility */ + state->opp[i].fmt_bit_depth_control = timing->display_color_depth; + + /* Output Buffer (OPPBUF) Control - 6 fields */ + state->opp[i].oppbuf_active_width = timing->h_addressable; + state->opp[i].oppbuf_pixel_repetition = 0; /* No pixel repetition by default */ + + /* Multi-Stream Output (MSO) / ODM segmentation */ + if (pipe_ctx->next_odm_pipe) { + state->opp[i].oppbuf_display_segmentation = 1; /* Segmented display */ + state->opp[i].oppbuf_overlap_pixel_num = 0; /* ODM overlap pixels */ + } else { + state->opp[i].oppbuf_display_segmentation = 0; /* Single segment */ + state->opp[i].oppbuf_overlap_pixel_num = 0; + } + + /* 3D/Stereo control */ + if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE) { + state->opp[i].oppbuf_3d_vact_space1_size = 30; /* Typical stereo blanking */ + state->opp[i].oppbuf_3d_vact_space2_size = 30; + } else { + state->opp[i].oppbuf_3d_vact_space1_size = 0; + state->opp[i].oppbuf_3d_vact_space2_size = 0; + } + + /* DSC Forward Config - 3 fields */ + if (timing->dsc_cfg.num_slices_h > 0) { + state->opp[i].dscrm_dsc_forward_enable = 1; + state->opp[i].dscrm_dsc_opp_pipe_source = pipe_ctx->stream_res.opp->inst; + state->opp[i].dscrm_dsc_forward_enable_status = 1; /* Status follows enable */ + } else { + state->opp[i].dscrm_dsc_forward_enable = 0; + state->opp[i].dscrm_dsc_opp_pipe_source = 0; + state->opp[i].dscrm_dsc_forward_enable_status = 0; + } + } else { + /* No OPP resource - set all fields to disabled state */ + memset(&state->opp[i], 0, sizeof(state->opp[i])); + } + } + + /* Capture OPTC programming state for each pipe - comprehensive register field coverage */ + for (i = 0; i < MAX_PIPES && i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; + + if (!pipe_ctx->stream) + continue; + + if (pipe_ctx->stream_res.tg) { + struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; + + state->optc[i].otg_master_inst = pipe_ctx->stream_res.tg->inst; + + /* OTG_CONTROL register - 5 fields */ + state->optc[i].otg_master_enable = 1; /* Active stream */ + state->optc[i].otg_disable_point_cntl = 0; /* Normal operation */ + state->optc[i].otg_start_point_cntl = 0; /* Normal start */ + state->optc[i].otg_field_number_cntl = (timing->flags.INTERLACE) ? 1 : 0; + state->optc[i].otg_out_mux = 0; /* Direct output */ + + /* OTG Horizontal Timing - 7 fields */ + state->optc[i].otg_h_total = timing->h_total; + state->optc[i].otg_h_blank_start = timing->h_addressable; + state->optc[i].otg_h_blank_end = timing->h_total - timing->h_front_porch; + state->optc[i].otg_h_sync_start = timing->h_addressable + timing->h_front_porch; + state->optc[i].otg_h_sync_end = timing->h_addressable + timing->h_front_porch + timing->h_sync_width; + state->optc[i].otg_h_sync_polarity = timing->flags.HSYNC_POSITIVE_POLARITY ? 0 : 1; + state->optc[i].otg_h_timing_div_mode = (pipe_ctx->next_odm_pipe) ? 1 : 0; /* ODM divide mode */ + + /* OTG Vertical Timing - 7 fields */ + state->optc[i].otg_v_total = timing->v_total; + state->optc[i].otg_v_blank_start = timing->v_addressable; + state->optc[i].otg_v_blank_end = timing->v_total - timing->v_front_porch; + state->optc[i].otg_v_sync_start = timing->v_addressable + timing->v_front_porch; + state->optc[i].otg_v_sync_end = timing->v_addressable + timing->v_front_porch + timing->v_sync_width; + state->optc[i].otg_v_sync_polarity = timing->flags.VSYNC_POSITIVE_POLARITY ? 0 : 1; + state->optc[i].otg_v_sync_mode = 0; /* Normal sync mode */ + + /* Initialize remaining core fields with appropriate defaults */ + // TODO: Update logic for accurate vtotal min/max + state->optc[i].otg_v_total_max = timing->v_total + 100; /* Typical DRR range */ + state->optc[i].otg_v_total_min = timing->v_total - 50; + state->optc[i].otg_v_total_mid = timing->v_total; + + /* ODM configuration */ + // TODO: Update logic to have complete ODM mappings (e.g. 3:1 and 4:1) stored in single pipe + if (pipe_ctx->next_odm_pipe) { + state->optc[i].optc_seg0_src_sel = pipe_ctx->stream_res.opp ? pipe_ctx->stream_res.opp->inst : 0; + state->optc[i].optc_seg1_src_sel = pipe_ctx->next_odm_pipe->stream_res.opp ? pipe_ctx->next_odm_pipe->stream_res.opp->inst : 0; + state->optc[i].optc_num_of_input_segment = 1; /* 2 segments - 1 */ + } else { + state->optc[i].optc_seg0_src_sel = pipe_ctx->stream_res.opp ? pipe_ctx->stream_res.opp->inst : 0; + state->optc[i].optc_seg1_src_sel = 0; + state->optc[i].optc_num_of_input_segment = 0; /* Single segment */ + } + + /* DSC configuration */ + if (timing->dsc_cfg.num_slices_h > 0) { + state->optc[i].optc_dsc_mode = 1; /* DSC enabled */ + state->optc[i].optc_dsc_bytes_per_pixel = timing->dsc_cfg.bits_per_pixel / 16; /* Convert to bytes */ + state->optc[i].optc_dsc_slice_width = timing->h_addressable / timing->dsc_cfg.num_slices_h; + } else { + state->optc[i].optc_dsc_mode = 0; + state->optc[i].optc_dsc_bytes_per_pixel = 0; + state->optc[i].optc_dsc_slice_width = 0; + } + + /* Essential control fields */ + state->optc[i].otg_stereo_enable = (timing->timing_3d_format != TIMING_3D_FORMAT_NONE) ? 1 : 0; + state->optc[i].otg_interlace_enable = timing->flags.INTERLACE ? 1 : 0; + state->optc[i].otg_clock_enable = 1; /* OTG clock enabled */ + state->optc[i].vtg0_enable = 1; /* VTG enabled for timing generation */ + + /* Initialize other key fields to defaults */ + state->optc[i].optc_input_pix_clk_en = 1; + state->optc[i].optc_segment_width = (pipe_ctx->next_odm_pipe) ? (timing->h_addressable / 2) : timing->h_addressable; + state->optc[i].otg_vready_offset = 1; + state->optc[i].otg_vstartup_start = timing->v_addressable + 10; + state->optc[i].otg_vupdate_offset = 0; + state->optc[i].otg_vupdate_width = 5; + } else { + /* No timing generator resource - initialize all fields to 0 */ + memset(&state->optc[i], 0, sizeof(state->optc[i])); + } + } + + state->state_valid = true; + return true; +} + void dc_log_preos_dmcub_info(const struct dc *dc) { dc_dmub_srv_log_preos_dmcub_info(dc->ctx->dmub_srv); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 74737f00fabfc..4ffc9786117f5 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -2795,4 +2795,491 @@ void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, st void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst, struct power_features *out_data); +/** + * Software state variables used to program register fields across the display pipeline + */ +struct dc_register_software_state { + /* HUBP register programming variables for each pipe */ + struct { + bool valid_plane_state; + bool valid_stream; + bool min_dc_gfx_version9; + uint32_t vtg_sel; /* DCHUBP_CNTL->HUBP_VTG_SEL from pipe_ctx->stream_res.tg->inst */ + uint32_t hubp_clock_enable; /* HUBP_CLK_CNTL->HUBP_CLOCK_ENABLE from power management */ + uint32_t surface_pixel_format; /* DCSURF_SURFACE_CONFIG->SURFACE_PIXEL_FORMAT from plane_state->format */ + uint32_t rotation_angle; /* DCSURF_SURFACE_CONFIG->ROTATION_ANGLE from plane_state->rotation */ + uint32_t h_mirror_en; /* DCSURF_SURFACE_CONFIG->H_MIRROR_EN from plane_state->horizontal_mirror */ + uint32_t surface_dcc_en; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_EN from dcc->enable */ + uint32_t surface_size_width; /* HUBP_SIZE->SURFACE_SIZE_WIDTH from plane_size.surface_size.width */ + uint32_t surface_size_height; /* HUBP_SIZE->SURFACE_SIZE_HEIGHT from plane_size.surface_size.height */ + uint32_t pri_viewport_width; /* DCSURF_PRI_VIEWPORT_DIMENSION->PRI_VIEWPORT_WIDTH from scaler_data.viewport.width */ + uint32_t pri_viewport_height; /* DCSURF_PRI_VIEWPORT_DIMENSION->PRI_VIEWPORT_HEIGHT from scaler_data.viewport.height */ + uint32_t pri_viewport_x_start; /* DCSURF_PRI_VIEWPORT_START->PRI_VIEWPORT_X_START from scaler_data.viewport.x */ + uint32_t pri_viewport_y_start; /* DCSURF_PRI_VIEWPORT_START->PRI_VIEWPORT_Y_START from scaler_data.viewport.y */ + uint32_t cursor_enable; /* CURSOR_CONTROL->CURSOR_ENABLE from cursor_attributes.enable */ + uint32_t cursor_width; /* CURSOR_SETTINGS->CURSOR_WIDTH from cursor_position.width */ + uint32_t cursor_height; /* CURSOR_SETTINGS->CURSOR_HEIGHT from cursor_position.height */ + + /* Additional DCC configuration */ + uint32_t surface_dcc_ind_64b_blk; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_IND_64B_BLK from dcc.independent_64b_blks */ + uint32_t surface_dcc_ind_128b_blk; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_IND_128B_BLK from dcc.independent_128b_blks */ + + /* Surface pitch configuration */ + uint32_t surface_pitch; /* DCSURF_SURFACE_PITCH->PITCH from plane_size.surface_pitch */ + uint32_t meta_pitch; /* DCSURF_SURFACE_PITCH->META_PITCH from dcc.meta_pitch */ + uint32_t chroma_pitch; /* DCSURF_SURFACE_PITCH_C->PITCH_C from plane_size.chroma_pitch */ + uint32_t meta_pitch_c; /* DCSURF_SURFACE_PITCH_C->META_PITCH_C from dcc.meta_pitch_c */ + + /* Surface addresses */ + uint32_t primary_surface_address_low; /* DCSURF_PRIMARY_SURFACE_ADDRESS->PRIMARY_SURFACE_ADDRESS from address.grph.addr.low_part */ + uint32_t primary_surface_address_high; /* DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH->PRIMARY_SURFACE_ADDRESS_HIGH from address.grph.addr.high_part */ + uint32_t primary_meta_surface_address_low; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS->PRIMARY_META_SURFACE_ADDRESS from address.grph.meta_addr.low_part */ + uint32_t primary_meta_surface_address_high; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH->PRIMARY_META_SURFACE_ADDRESS_HIGH from address.grph.meta_addr.high_part */ + + /* TMZ configuration */ + uint32_t primary_surface_tmz; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_TMZ from address.tmz_surface */ + uint32_t primary_meta_surface_tmz; /* DCSURF_SURFACE_CONTROL->PRIMARY_META_SURFACE_TMZ from address.tmz_surface */ + + /* Tiling configuration */ + uint32_t sw_mode; /* DCSURF_TILING_CONFIG->SW_MODE from tiling_info.gfx9.swizzle */ + uint32_t num_pipes; /* DCSURF_ADDR_CONFIG->NUM_PIPES from tiling_info.gfx9.num_pipes */ + uint32_t num_banks; /* DCSURF_ADDR_CONFIG->NUM_BANKS from tiling_info.gfx9.num_banks */ + uint32_t pipe_interleave; /* DCSURF_ADDR_CONFIG->PIPE_INTERLEAVE from tiling_info.gfx9.pipe_interleave */ + uint32_t num_shader_engines; /* DCSURF_ADDR_CONFIG->NUM_SE from tiling_info.gfx9.num_shader_engines */ + uint32_t num_rb_per_se; /* DCSURF_ADDR_CONFIG->NUM_RB_PER_SE from tiling_info.gfx9.num_rb_per_se */ + uint32_t num_pkrs; /* DCSURF_ADDR_CONFIG->NUM_PKRS from tiling_info.gfx9.num_pkrs */ + + /* DML Request Size Configuration - Luma */ + uint32_t rq_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->CHUNK_SIZE from rq_regs.rq_regs_l.chunk_size */ + uint32_t rq_min_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->MIN_CHUNK_SIZE from rq_regs.rq_regs_l.min_chunk_size */ + uint32_t rq_meta_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->META_CHUNK_SIZE from rq_regs.rq_regs_l.meta_chunk_size */ + uint32_t rq_min_meta_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->MIN_META_CHUNK_SIZE from rq_regs.rq_regs_l.min_meta_chunk_size */ + uint32_t rq_dpte_group_size; /* DCHUBP_REQ_SIZE_CONFIG->DPTE_GROUP_SIZE from rq_regs.rq_regs_l.dpte_group_size */ + uint32_t rq_mpte_group_size; /* DCHUBP_REQ_SIZE_CONFIG->MPTE_GROUP_SIZE from rq_regs.rq_regs_l.mpte_group_size */ + uint32_t rq_swath_height_l; /* DCHUBP_REQ_SIZE_CONFIG->SWATH_HEIGHT_L from rq_regs.rq_regs_l.swath_height */ + uint32_t rq_pte_row_height_l; /* DCHUBP_REQ_SIZE_CONFIG->PTE_ROW_HEIGHT_L from rq_regs.rq_regs_l.pte_row_height */ + + /* DML Request Size Configuration - Chroma */ + uint32_t rq_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->CHUNK_SIZE_C from rq_regs.rq_regs_c.chunk_size */ + uint32_t rq_min_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MIN_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_chunk_size */ + uint32_t rq_meta_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->META_CHUNK_SIZE_C from rq_regs.rq_regs_c.meta_chunk_size */ + uint32_t rq_min_meta_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MIN_META_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_meta_chunk_size */ + uint32_t rq_dpte_group_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->DPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.dpte_group_size */ + uint32_t rq_mpte_group_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.mpte_group_size */ + uint32_t rq_swath_height_c; /* DCHUBP_REQ_SIZE_CONFIG_C->SWATH_HEIGHT_C from rq_regs.rq_regs_c.swath_height */ + uint32_t rq_pte_row_height_c; /* DCHUBP_REQ_SIZE_CONFIG_C->PTE_ROW_HEIGHT_C from rq_regs.rq_regs_c.pte_row_height */ + + /* DML Expansion Modes */ + uint32_t drq_expansion_mode; /* DCN_EXPANSION_MODE->DRQ_EXPANSION_MODE from rq_regs.drq_expansion_mode */ + uint32_t prq_expansion_mode; /* DCN_EXPANSION_MODE->PRQ_EXPANSION_MODE from rq_regs.prq_expansion_mode */ + uint32_t mrq_expansion_mode; /* DCN_EXPANSION_MODE->MRQ_EXPANSION_MODE from rq_regs.mrq_expansion_mode */ + uint32_t crq_expansion_mode; /* DCN_EXPANSION_MODE->CRQ_EXPANSION_MODE from rq_regs.crq_expansion_mode */ + + /* DML DLG parameters - nominal */ + uint32_t dst_y_per_vm_vblank; /* NOM_PARAMETERS_0->DST_Y_PER_VM_VBLANK from dlg_regs.dst_y_per_vm_vblank */ + uint32_t dst_y_per_row_vblank; /* NOM_PARAMETERS_0->DST_Y_PER_ROW_VBLANK from dlg_regs.dst_y_per_row_vblank */ + uint32_t dst_y_per_vm_flip; /* NOM_PARAMETERS_1->DST_Y_PER_VM_FLIP from dlg_regs.dst_y_per_vm_flip */ + uint32_t dst_y_per_row_flip; /* NOM_PARAMETERS_1->DST_Y_PER_ROW_FLIP from dlg_regs.dst_y_per_row_flip */ + + /* DML prefetch settings */ + uint32_t dst_y_prefetch; /* PREFETCH_SETTINS->DST_Y_PREFETCH from dlg_regs.dst_y_prefetch */ + uint32_t vratio_prefetch; /* PREFETCH_SETTINS->VRATIO_PREFETCH from dlg_regs.vratio_prefetch */ + uint32_t vratio_prefetch_c; /* PREFETCH_SETTINS_C->VRATIO_PREFETCH_C from dlg_regs.vratio_prefetch_c */ + + /* TTU parameters */ + uint32_t qos_level_low_wm; /* TTU_CNTL1->QoSLevelLowWaterMark from ttu_regs.qos_level_low_wm */ + uint32_t qos_level_high_wm; /* TTU_CNTL1->QoSLevelHighWaterMark from ttu_regs.qos_level_high_wm */ + uint32_t qos_level_flip; /* TTU_CNTL2->QoS_LEVEL_FLIP_L from ttu_regs.qos_level_flip */ + uint32_t min_ttu_vblank; /* DCN_GLOBAL_TTU_CNTL->MIN_TTU_VBLANK from ttu_regs.min_ttu_vblank */ + } hubp[MAX_PIPES]; + + /* HUBBUB register programming variables */ + struct { + /* Individual DET buffer control per pipe - software state that programs DET registers */ + uint32_t det0_size; /* DCHUBBUB_DET0_CTRL->DET0_SIZE from hubbub->funcs->program_det_size(hubbub, 0, det_buffer_size_kb) */ + uint32_t det1_size; /* DCHUBBUB_DET1_CTRL->DET1_SIZE from hubbub->funcs->program_det_size(hubbub, 1, det_buffer_size_kb) */ + uint32_t det2_size; /* DCHUBBUB_DET2_CTRL->DET2_SIZE from hubbub->funcs->program_det_size(hubbub, 2, det_buffer_size_kb) */ + uint32_t det3_size; /* DCHUBBUB_DET3_CTRL->DET3_SIZE from hubbub->funcs->program_det_size(hubbub, 3, det_buffer_size_kb) */ + + /* Compression buffer control - software state that programs COMPBUF registers */ + uint32_t compbuf_size; /* DCHUBBUB_COMPBUF_CTRL->COMPBUF_SIZE from hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, safe_to_increase) */ + uint32_t compbuf_reserved_space_64b; /* COMPBUF_RESERVED_SPACE->COMPBUF_RESERVED_SPACE_64B from hubbub2->pixel_chunk_size / 32 */ + uint32_t compbuf_reserved_space_zs; /* COMPBUF_RESERVED_SPACE->COMPBUF_RESERVED_SPACE_ZS from hubbub2->pixel_chunk_size / 128 */ + } hubbub; + + /* DPP register programming variables for each pipe (simplified for available fields) */ + struct { + uint32_t dpp_clock_enable; /* DPP_CONTROL->DPP_CLOCK_ENABLE from dppclk_enable */ + + /* Recout (Rectangle of Interest) configuration */ + uint32_t recout_start_x; /* RECOUT_START->RECOUT_START_X from pipe_ctx->plane_res.scl_data.recout.x */ + uint32_t recout_start_y; /* RECOUT_START->RECOUT_START_Y from pipe_ctx->plane_res.scl_data.recout.y */ + uint32_t recout_width; /* RECOUT_SIZE->RECOUT_WIDTH from pipe_ctx->plane_res.scl_data.recout.width */ + uint32_t recout_height; /* RECOUT_SIZE->RECOUT_HEIGHT from pipe_ctx->plane_res.scl_data.recout.height */ + + /* MPC (Multiple Pipe/Plane Combiner) size configuration */ + uint32_t mpc_width; /* MPC_SIZE->MPC_WIDTH from pipe_ctx->plane_res.scl_data.h_active */ + uint32_t mpc_height; /* MPC_SIZE->MPC_HEIGHT from pipe_ctx->plane_res.scl_data.v_active */ + + /* DSCL mode configuration */ + uint32_t dscl_mode; /* SCL_MODE->DSCL_MODE from pipe_ctx->plane_res.scl_data.dscl_prog_data.dscl_mode */ + + /* Scaler ratios (simplified to integer parts) */ + uint32_t horz_ratio_int; /* SCL_HORZ_FILTER_SCALE_RATIO->SCL_H_SCALE_RATIO integer part from ratios.horz */ + uint32_t vert_ratio_int; /* SCL_VERT_FILTER_SCALE_RATIO->SCL_V_SCALE_RATIO integer part from ratios.vert */ + + /* Basic scaler taps */ + uint32_t h_taps; /* SCL_TAP_CONTROL->SCL_H_NUM_TAPS from taps.h_taps */ + uint32_t v_taps; /* SCL_TAP_CONTROL->SCL_V_NUM_TAPS from taps.v_taps */ + } dpp[MAX_PIPES]; + + /* DCCG register programming variables */ + struct { + /* Core Display Clock Control */ + uint32_t dispclk_khz; /* DENTIST_DISPCLK_CNTL->DENTIST_DISPCLK_WDIVIDER from clk_mgr.dispclk_khz */ + uint32_t dc_mem_global_pwr_req_dis; /* DC_MEM_GLOBAL_PWR_REQ_CNTL->DC_MEM_GLOBAL_PWR_REQ_DIS from memory power management settings */ + + /* DPP Clock Control - 4 fields per pipe */ + uint32_t dppclk_khz[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK_R_GATE_DISABLE from dpp_clocks[pipe] */ + uint32_t dppclk_enable[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK0_EN,DPPCLK1_EN,DPPCLK2_EN,DPPCLK3_EN from dccg31_update_dpp_dto() */ + uint32_t dppclk_dto_enable[MAX_PIPES]; /* DPPCLK_DTO_CTRL->DPPCLK_DTO_ENABLE from dccg->dpp_clock_gated[dpp_inst] state */ + uint32_t dppclk_dto_phase[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_PHASE from phase calculation req_dppclk/ref_dppclk */ + uint32_t dppclk_dto_modulo[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_MODULO from modulo = 0xff */ + + /* DSC Clock Control - 4 fields per DSC resource */ + uint32_t dscclk_khz[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK_DTO_ENABLE from dsc_clocks */ + uint32_t dscclk_dto_enable[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK0_DTO_ENABLE,DSCCLK1_DTO_ENABLE,DSCCLK2_DTO_ENABLE,DSCCLK3_DTO_ENABLE */ + uint32_t dscclk_dto_phase[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_PHASE from dccg31_enable_dscclk() */ + uint32_t dscclk_dto_modulo[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_MODULO from dccg31_enable_dscclk() */ + + /* Pixel Clock Control - per pipe */ + uint32_t pixclk_khz[MAX_PIPES]; /* PIXCLK_RESYNC_CNTL->PIXCLK_RESYNC_ENABLE from stream.timing.pix_clk_100hz */ + uint32_t otg_pixel_rate_div[MAX_PIPES]; /* OTG_PIXEL_RATE_DIV->OTG_PIXEL_RATE_DIV from OTG pixel rate divider control */ + uint32_t dtbclk_dto_enable[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_ENABLE from dccg31_set_dtbclk_dto() */ + uint32_t pipe_dto_src_sel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->PIPE_DTO_SRC_SEL from dccg31_set_dtbclk_dto() source selection */ + uint32_t dtbclk_dto_div[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_DIV from dtbdto_div calculation */ + uint32_t otg_add_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_ADD_PIXEL from dccg31_otg_add_pixel() */ + uint32_t otg_drop_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_DROP_PIXEL from dccg31_otg_drop_pixel() */ + + /* DTBCLK DTO Control - 4 DTOs */ + uint32_t dtbclk_dto_modulo[4]; /* DTBCLK_DTO0_MODULO->DTBCLK_DTO0_MODULO from dccg31_set_dtbclk_dto() modulo calculation */ + uint32_t dtbclk_dto_phase[4]; /* DTBCLK_DTO0_PHASE->DTBCLK_DTO0_PHASE from phase calculation pixclk_khz/ref_dtbclk_khz */ + uint32_t dtbclk_dto_dbuf_en; /* DTBCLK_DTO_DBUF_EN->DTBCLK DTO data buffer enable */ + + /* DP Stream Clock Control - 4 pipes */ + uint32_t dpstreamclk_enable[MAX_PIPES]; /* DPSTREAMCLK_CNTL->DPSTREAMCLK_PIPE0_EN,DPSTREAMCLK_PIPE1_EN,DPSTREAMCLK_PIPE2_EN,DPSTREAMCLK_PIPE3_EN */ + uint32_t dp_dto_modulo[4]; /* DP_DTO0_MODULO->DP_DTO0_MODULO from DP stream DTO programming */ + uint32_t dp_dto_phase[4]; /* DP_DTO0_PHASE->DP_DTO0_PHASE from DP stream DTO programming */ + uint32_t dp_dto_dbuf_en; /* DP_DTO_DBUF_EN->DP DTO data buffer enable */ + + /* PHY Symbol Clock Control - 5 PHYs (A,B,C,D,E) */ + uint32_t phy_symclk_force_en[5]; /* PHYASYMCLK_CLOCK_CNTL->PHYASYMCLK_FORCE_EN from dccg31_set_physymclk() force_enable */ + uint32_t phy_symclk_force_src_sel[5]; /* PHYASYMCLK_CLOCK_CNTL->PHYASYMCLK_FORCE_SRC_SEL from dccg31_set_physymclk() clk_src */ + uint32_t phy_symclk_gate_disable[5]; /* DCCG_GATE_DISABLE_CNTL2->PHYASYMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.physymclk */ + + /* SYMCLK32 SE Control - 4 instances */ + uint32_t symclk32_se_src_sel[4]; /* SYMCLK32_SE_CNTL->SYMCLK32_SE0_SRC_SEL from dccg31_enable_symclk32_se() with get_phy_mux_symclk() mapping */ + uint32_t symclk32_se_enable[4]; /* SYMCLK32_SE_CNTL->SYMCLK32_SE0_EN from dccg31_enable_symclk32_se() enable */ + uint32_t symclk32_se_gate_disable[4]; /* DCCG_GATE_DISABLE_CNTL3->SYMCLK32_SE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_se */ + + /* SYMCLK32 LE Control - 2 instances */ + uint32_t symclk32_le_src_sel[2]; /* SYMCLK32_LE_CNTL->SYMCLK32_LE0_SRC_SEL from dccg31_enable_symclk32_le() phyd32clk source */ + uint32_t symclk32_le_enable[2]; /* SYMCLK32_LE_CNTL->SYMCLK32_LE0_EN from dccg31_enable_symclk32_le() enable */ + uint32_t symclk32_le_gate_disable[2]; /* DCCG_GATE_DISABLE_CNTL3->SYMCLK32_LE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_le */ + + /* DPIA Clock Control */ + uint32_t dpiaclk_540m_dto_modulo; /* DPIACLK_540M_DTO_MODULO->DPIA 540MHz DTO modulo */ + uint32_t dpiaclk_540m_dto_phase; /* DPIACLK_540M_DTO_PHASE->DPIA 540MHz DTO phase */ + uint32_t dpiaclk_810m_dto_modulo; /* DPIACLK_810M_DTO_MODULO->DPIA 810MHz DTO modulo */ + uint32_t dpiaclk_810m_dto_phase; /* DPIACLK_810M_DTO_PHASE->DPIA 810MHz DTO phase */ + uint32_t dpiaclk_dto_cntl; /* DPIACLK_DTO_CNTL->DPIA clock DTO control */ + uint32_t dpiasymclk_cntl; /* DPIASYMCLK_CNTL->DPIA symbol clock control */ + + /* Clock Gating Control */ + uint32_t dccg_gate_disable_cntl; /* DCCG_GATE_DISABLE_CNTL->Clock gate disable control from dccg31_init() */ + uint32_t dpstreamclk_gate_disable; /* DCCG_GATE_DISABLE_CNTL3->DPSTREAMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */ + uint32_t dpstreamclk_root_gate_disable; /* DCCG_GATE_DISABLE_CNTL3->DPSTREAMCLK_ROOT_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */ + + /* VSync Control */ + uint32_t vsync_cnt_ctrl; /* DCCG_VSYNC_CNT_CTRL->VSync counter control */ + uint32_t vsync_cnt_int_ctrl; /* DCCG_VSYNC_CNT_INT_CTRL->VSync counter interrupt control */ + uint32_t vsync_otg_latch_value[6]; /* DCCG_VSYNC_OTG0_LATCH_VALUE->OTG0 VSync latch value (for OTG0-5) */ + + /* Time Base Control */ + uint32_t microsecond_time_base_div; /* MICROSECOND_TIME_BASE_DIV->Microsecond time base divider */ + uint32_t millisecond_time_base_div; /* MILLISECOND_TIME_BASE_DIV->Millisecond time base divider */ + } dccg; + + /* DSC essential configuration for underflow analysis */ + struct { + /* DSC active state - critical for bandwidth analysis */ + uint32_t dsc_clock_enable; /* DSC enabled - affects bandwidth requirements */ + + /* DSC configuration affecting bandwidth and timing */ + uint32_t dsc_num_slices_h; /* Horizontal slice count - affects throughput */ + uint32_t dsc_num_slices_v; /* Vertical slice count - affects throughput */ + uint32_t dsc_bits_per_pixel; /* Compression ratio - affects bandwidth */ + + /* OPP integration - affects pipeline flow */ + uint32_t dscrm_dsc_forward_enable; /* DSC forwarding to OPP enabled */ + uint32_t dscrm_dsc_opp_pipe_source; /* Which OPP receives DSC output */ + } dsc[MAX_PIPES]; + + /* MPC register programming variables */ + struct { + /* MPCC blending tree and mode control */ + uint32_t mpcc_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_MODE from blend_cfg.blend_mode */ + uint32_t mpcc_alpha_blend_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_BLND_MODE from blend_cfg.alpha_mode */ + uint32_t mpcc_alpha_multiplied_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_MULTIPLIED_MODE from blend_cfg.pre_multiplied_alpha */ + uint32_t mpcc_blnd_active_overlap_only[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BLND_ACTIVE_OVERLAP_ONLY from blend_cfg.overlap_only */ + uint32_t mpcc_global_alpha[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_ALPHA from blend_cfg.global_alpha */ + uint32_t mpcc_global_gain[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_GAIN from blend_cfg.global_gain */ + uint32_t mpcc_bg_bpc[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BG_BPC from background color depth */ + uint32_t mpcc_bot_gain_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BOT_GAIN_MODE from bottom layer gain control */ + + /* MPCC blending tree connections */ + uint32_t mpcc_bot_sel[MAX_PIPES]; /* MPCC_BOT_SEL->MPCC_BOT_SEL from mpcc_state->bot_sel */ + uint32_t mpcc_top_sel[MAX_PIPES]; /* MPCC_TOP_SEL->MPCC_TOP_SEL from mpcc_state->dpp_id */ + + /* MPCC output gamma control */ + uint32_t mpcc_ogam_mode[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_MODE from output gamma mode */ + uint32_t mpcc_ogam_select[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_SELECT from gamma LUT bank selection */ + uint32_t mpcc_ogam_pwl_disable[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_PWL_DISABLE from PWL control */ + + /* MPCC pipe assignment and status */ + uint32_t mpcc_opp_id[MAX_PIPES]; /* MPCC_OPP_ID->MPCC_OPP_ID from mpcc_state->opp_id */ + uint32_t mpcc_idle[MAX_PIPES]; /* MPCC_STATUS->MPCC_IDLE from mpcc idle status */ + uint32_t mpcc_busy[MAX_PIPES]; /* MPCC_STATUS->MPCC_BUSY from mpcc busy status */ + + /* MPC output processing */ + uint32_t mpc_out_csc_mode; /* MPC_OUT_CSC_COEF->MPC_OUT_CSC_MODE from output_csc */ + uint32_t mpc_out_gamma_mode; /* MPC_OUT_GAMMA_LUT->MPC_OUT_GAMMA_MODE from output_gamma */ + } mpc; + + /* OPP register programming variables for each pipe */ + struct { + /* Display Pattern Generator (DPG) Control - 19 fields from DPG_CONTROL register */ + uint32_t dpg_enable; /* DPG_CONTROL->DPG_EN from test_pattern parameter (enable/disable) */ + + /* Format Control (FMT) - 18 fields from FMT_CONTROL register */ + uint32_t fmt_pixel_encoding; /* FMT_CONTROL->FMT_PIXEL_ENCODING from clamping->pixel_encoding */ + uint32_t fmt_subsampling_mode; /* FMT_CONTROL->FMT_SUBSAMPLING_MODE from force_chroma_subsampling_1tap */ + uint32_t fmt_cbcr_bit_reduction_bypass; /* FMT_CONTROL->FMT_CBCR_BIT_REDUCTION_BYPASS from pixel_encoding bypass control */ + uint32_t fmt_stereosync_override; /* FMT_CONTROL->FMT_STEREOSYNC_OVERRIDE from stereo timing override */ + uint32_t fmt_spatial_dither_frame_counter_max; /* FMT_CONTROL->FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX from fmt_bit_depth->flags */ + uint32_t fmt_spatial_dither_frame_counter_bit_swap; /* FMT_CONTROL->FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP from dither control */ + uint32_t fmt_truncate_enable; /* FMT_CONTROL->FMT_TRUNCATE_EN from fmt_bit_depth->flags.TRUNCATE_ENABLED */ + uint32_t fmt_truncate_depth; /* FMT_CONTROL->FMT_TRUNCATE_DEPTH from fmt_bit_depth->flags.TRUNCATE_DEPTH */ + uint32_t fmt_truncate_mode; /* FMT_CONTROL->FMT_TRUNCATE_MODE from fmt_bit_depth->flags.TRUNCATE_MODE */ + uint32_t fmt_spatial_dither_enable; /* FMT_CONTROL->FMT_SPATIAL_DITHER_EN from fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED */ + uint32_t fmt_spatial_dither_mode; /* FMT_CONTROL->FMT_SPATIAL_DITHER_MODE from fmt_bit_depth->flags.SPATIAL_DITHER_MODE */ + uint32_t fmt_spatial_dither_depth; /* FMT_CONTROL->FMT_SPATIAL_DITHER_DEPTH from fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH */ + uint32_t fmt_temporal_dither_enable; /* FMT_CONTROL->FMT_TEMPORAL_DITHER_EN from fmt_bit_depth->flags.TEMPORAL_DITHER_ENABLED */ + uint32_t fmt_clamp_data_enable; /* FMT_CONTROL->FMT_CLAMP_DATA_EN from clamping->clamping_range enable */ + uint32_t fmt_clamp_color_format; /* FMT_CONTROL->FMT_CLAMP_COLOR_FORMAT from clamping->color_format */ + uint32_t fmt_dynamic_exp_enable; /* FMT_CONTROL->FMT_DYNAMIC_EXP_EN from color_sp/color_dpth/signal */ + uint32_t fmt_dynamic_exp_mode; /* FMT_CONTROL->FMT_DYNAMIC_EXP_MODE from color space mode mapping */ + uint32_t fmt_bit_depth_control; /* Legacy field - kept for compatibility */ + + /* OPP Pipe Control - 1 field from OPP_PIPE_CONTROL register */ + uint32_t opp_pipe_clock_enable; /* OPP_PIPE_CONTROL->OPP_PIPE_CLOCK_EN from enable parameter (bool) */ + + /* OPP CRC Control - 3 fields from OPP_PIPE_CRC_CONTROL register */ + uint32_t opp_crc_enable; /* OPP_PIPE_CRC_CONTROL->CRC_EN from CRC enable control */ + uint32_t opp_crc_select_source; /* OPP_PIPE_CRC_CONTROL->CRC_SELECT_SOURCE from CRC source selection */ + uint32_t opp_crc_stereo_cont; /* OPP_PIPE_CRC_CONTROL->CRC_STEREO_CONT from stereo continuous CRC */ + + /* Output Buffer (OPPBUF) Control - 6 fields from OPPBUF_CONTROL register */ + uint32_t oppbuf_active_width; /* OPPBUF_CONTROL->OPPBUF_ACTIVE_WIDTH from oppbuf_params->active_width */ + uint32_t oppbuf_pixel_repetition; /* OPPBUF_CONTROL->OPPBUF_PIXEL_REPETITION from oppbuf_params->pixel_repetition */ + uint32_t oppbuf_display_segmentation; /* OPPBUF_CONTROL->OPPBUF_DISPLAY_SEGMENTATION from oppbuf_params->mso_segmentation */ + uint32_t oppbuf_overlap_pixel_num; /* OPPBUF_CONTROL->OPPBUF_OVERLAP_PIXEL_NUM from oppbuf_params->mso_overlap_pixel_num */ + uint32_t oppbuf_3d_vact_space1_size; /* OPPBUF_CONTROL->OPPBUF_3D_VACT_SPACE1_SIZE from 3D timing space1_size */ + uint32_t oppbuf_3d_vact_space2_size; /* OPPBUF_CONTROL->OPPBUF_3D_VACT_SPACE2_SIZE from 3D timing space2_size */ + + /* DSC Forward Config - 3 fields from DSCRM_DSC_FORWARD_CONFIG register */ + uint32_t dscrm_dsc_forward_enable; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_FORWARD_EN from DSC forward enable control */ + uint32_t dscrm_dsc_opp_pipe_source; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_OPP_PIPE_SOURCE from opp_pipe parameter */ + uint32_t dscrm_dsc_forward_enable_status; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_FORWARD_EN_STATUS from DSC forward status (read-only) */ + } opp[MAX_PIPES]; + + /* OPTC register programming variables for each pipe */ + struct { + uint32_t otg_master_inst; + + /* OTG_CONTROL register - 5 fields for OTG control */ + uint32_t otg_master_enable; /* OTG_CONTROL->OTG_MASTER_EN from timing enable/disable control */ + uint32_t otg_disable_point_cntl; /* OTG_CONTROL->OTG_DISABLE_POINT_CNTL from disable timing control */ + uint32_t otg_start_point_cntl; /* OTG_CONTROL->OTG_START_POINT_CNTL from start timing control */ + uint32_t otg_field_number_cntl; /* OTG_CONTROL->OTG_FIELD_NUMBER_CNTL from interlace field control */ + uint32_t otg_out_mux; /* OTG_CONTROL->OTG_OUT_MUX from output mux selection */ + + /* OTG Horizontal Timing - 7 fields */ + uint32_t otg_h_total; /* OTG_H_TOTAL->OTG_H_TOTAL from dc_crtc_timing->h_total */ + uint32_t otg_h_blank_start; /* OTG_H_BLANK_START_END->OTG_H_BLANK_START from dc_crtc_timing->h_front_porch */ + uint32_t otg_h_blank_end; /* OTG_H_BLANK_START_END->OTG_H_BLANK_END from dc_crtc_timing->h_addressable_video_pixel_width */ + uint32_t otg_h_sync_start; /* OTG_H_SYNC_A->OTG_H_SYNC_A_START from dc_crtc_timing->h_sync_width */ + uint32_t otg_h_sync_end; /* OTG_H_SYNC_A->OTG_H_SYNC_A_END from calculated sync end position */ + uint32_t otg_h_sync_polarity; /* OTG_H_SYNC_A_CNTL->OTG_H_SYNC_A_POL from dc_crtc_timing->flags.HSYNC_POSITIVE_POLARITY */ + uint32_t otg_h_timing_div_mode; /* OTG_H_TIMING_CNTL->OTG_H_TIMING_DIV_MODE from horizontal timing division mode */ + + /* OTG Vertical Timing - 7 fields */ + uint32_t otg_v_total; /* OTG_V_TOTAL->OTG_V_TOTAL from dc_crtc_timing->v_total */ + uint32_t otg_v_blank_start; /* OTG_V_BLANK_START_END->OTG_V_BLANK_START from dc_crtc_timing->v_front_porch */ + uint32_t otg_v_blank_end; /* OTG_V_BLANK_START_END->OTG_V_BLANK_END from dc_crtc_timing->v_addressable_video_line_width */ + uint32_t otg_v_sync_start; /* OTG_V_SYNC_A->OTG_V_SYNC_A_START from dc_crtc_timing->v_sync_width */ + uint32_t otg_v_sync_end; /* OTG_V_SYNC_A->OTG_V_SYNC_A_END from calculated sync end position */ + uint32_t otg_v_sync_polarity; /* OTG_V_SYNC_A_CNTL->OTG_V_SYNC_A_POL from dc_crtc_timing->flags.VSYNC_POSITIVE_POLARITY */ + uint32_t otg_v_sync_mode; /* OTG_V_SYNC_A_CNTL->OTG_V_SYNC_MODE from sync mode selection */ + + /* OTG DRR (Dynamic Refresh Rate) Control - 8 fields */ + uint32_t otg_v_total_max; /* OTG_V_TOTAL_MAX->OTG_V_TOTAL_MAX from drr_params->vertical_total_max */ + uint32_t otg_v_total_min; /* OTG_V_TOTAL_MIN->OTG_V_TOTAL_MIN from drr_params->vertical_total_min */ + uint32_t otg_v_total_mid; /* OTG_V_TOTAL_MID->OTG_V_TOTAL_MID from drr_params->vertical_total_mid */ + uint32_t otg_v_total_max_sel; /* OTG_V_TOTAL_CONTROL->OTG_V_TOTAL_MAX_SEL from DRR max selection enable */ + uint32_t otg_v_total_min_sel; /* OTG_V_TOTAL_CONTROL->OTG_V_TOTAL_MIN_SEL from DRR min selection enable */ + uint32_t otg_vtotal_mid_replacing_max_en; /* OTG_V_TOTAL_CONTROL->OTG_VTOTAL_MID_REPLACING_MAX_EN from DRR mid-frame enable */ + uint32_t otg_vtotal_mid_frame_num; /* OTG_V_TOTAL_CONTROL->OTG_VTOTAL_MID_FRAME_NUM from drr_params->vertical_total_mid_frame_num */ + uint32_t otg_set_v_total_min_mask; /* OTG_V_TOTAL_CONTROL->OTG_SET_V_TOTAL_MIN_MASK from DRR trigger mask */ + uint32_t otg_force_lock_on_event; /* OTG_V_TOTAL_CONTROL->OTG_FORCE_LOCK_ON_EVENT from DRR force lock control */ + + /* OPTC Data Source and ODM - 6 fields */ + uint32_t optc_seg0_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG0_SRC_SEL from opp_id[0] ODM segment 0 source */ + uint32_t optc_seg1_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG1_SRC_SEL from opp_id[1] ODM segment 1 source */ + uint32_t optc_seg2_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG2_SRC_SEL from opp_id[2] ODM segment 2 source */ + uint32_t optc_seg3_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG3_SRC_SEL from opp_id[3] ODM segment 3 source */ + uint32_t optc_num_of_input_segment; /* OPTC_DATA_SOURCE_SELECT->OPTC_NUM_OF_INPUT_SEGMENT from opp_cnt-1 number of input segments */ + uint32_t optc_mem_sel; /* OPTC_MEMORY_CONFIG->OPTC_MEM_SEL from memory_mask ODM memory selection */ + + /* OPTC Data Format and DSC - 4 fields */ + uint32_t optc_data_format; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DATA_FORMAT from data format selection */ + uint32_t optc_dsc_mode; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DSC_MODE from dsc_mode parameter */ + uint32_t optc_dsc_bytes_per_pixel; /* OPTC_BYTES_PER_PIXEL->OPTC_DSC_BYTES_PER_PIXEL from dsc_bytes_per_pixel parameter */ + uint32_t optc_segment_width; /* OPTC_WIDTH_CONTROL->OPTC_SEGMENT_WIDTH from segment_width parameter */ + uint32_t optc_dsc_slice_width; /* OPTC_WIDTH_CONTROL->OPTC_DSC_SLICE_WIDTH from dsc_slice_width parameter */ + + /* OPTC Clock and Underflow Control - 4 fields */ + uint32_t optc_input_pix_clk_en; /* OPTC_INPUT_CLOCK_CONTROL->OPTC_INPUT_PIX_CLK_EN from pixel clock enable */ + uint32_t optc_underflow_occurred_status; /* OPTC_INPUT_GLOBAL_CONTROL->OPTC_UNDERFLOW_OCCURRED_STATUS from underflow status (read-only) */ + uint32_t optc_underflow_clear; /* OPTC_INPUT_GLOBAL_CONTROL->OPTC_UNDERFLOW_CLEAR from underflow clear control */ + uint32_t otg_clock_enable; /* OTG_CLOCK_CONTROL->OTG_CLOCK_EN from OTG clock enable */ + uint32_t otg_clock_gate_dis; /* OTG_CLOCK_CONTROL->OTG_CLOCK_GATE_DIS from clock gate disable */ + + /* OTG Stereo and 3D Control - 6 fields */ + uint32_t otg_stereo_enable; /* OTG_STEREO_CONTROL->OTG_STEREO_EN from stereo enable control */ + uint32_t otg_stereo_sync_output_line_num; /* OTG_STEREO_CONTROL->OTG_STEREO_SYNC_OUTPUT_LINE_NUM from timing->stereo_3d_format line num */ + uint32_t otg_stereo_sync_output_polarity; /* OTG_STEREO_CONTROL->OTG_STEREO_SYNC_OUTPUT_POLARITY from stereo polarity control */ + uint32_t otg_3d_structure_en; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_EN from 3D structure enable */ + uint32_t otg_3d_structure_v_update_mode; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_V_UPDATE_MODE from 3D vertical update mode */ + uint32_t otg_3d_structure_stereo_sel_ovr; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_STEREO_SEL_OVR from 3D stereo selection override */ + uint32_t otg_interlace_enable; /* OTG_INTERLACE_CONTROL->OTG_INTERLACE_ENABLE from dc_crtc_timing->flags.INTERLACE */ + + /* OTG GSL (Global Sync Lock) Control - 5 fields */ + uint32_t otg_gsl0_en; /* OTG_GSL_CONTROL->OTG_GSL0_EN from GSL group 0 enable */ + uint32_t otg_gsl1_en; /* OTG_GSL_CONTROL->OTG_GSL1_EN from GSL group 1 enable */ + uint32_t otg_gsl2_en; /* OTG_GSL_CONTROL->OTG_GSL2_EN from GSL group 2 enable */ + uint32_t otg_gsl_master_en; /* OTG_GSL_CONTROL->OTG_GSL_MASTER_EN from GSL master enable */ + uint32_t otg_gsl_master_mode; /* OTG_GSL_CONTROL->OTG_GSL_MASTER_MODE from gsl_params->gsl_master mode */ + + /* OTG DRR Advanced Control - 4 fields */ + uint32_t otg_v_total_last_used_by_drr; /* OTG_DRR_CONTROL->OTG_V_TOTAL_LAST_USED_BY_DRR from last used DRR V_TOTAL (read-only) */ + uint32_t otg_drr_trigger_window_start_x; /* OTG_DRR_TRIGGER_WINDOW->OTG_DRR_TRIGGER_WINDOW_START_X from window_start parameter */ + uint32_t otg_drr_trigger_window_end_x; /* OTG_DRR_TRIGGER_WINDOW->OTG_DRR_TRIGGER_WINDOW_END_X from window_end parameter */ + uint32_t otg_drr_v_total_change_limit; /* OTG_DRR_V_TOTAL_CHANGE->OTG_DRR_V_TOTAL_CHANGE_LIMIT from limit parameter */ + + /* OTG DSC Position Control - 2 fields */ + uint32_t otg_dsc_start_position_x; /* OTG_DSC_START_POSITION->OTG_DSC_START_POSITION_X from DSC start X position */ + uint32_t otg_dsc_start_position_line_num; /* OTG_DSC_START_POSITION->OTG_DSC_START_POSITION_LINE_NUM from DSC start line number */ + + /* OTG Double Buffer Control - 2 fields */ + uint32_t otg_drr_timing_dbuf_update_mode; /* OTG_DOUBLE_BUFFER_CONTROL->OTG_DRR_TIMING_DBUF_UPDATE_MODE from DRR double buffer mode */ + uint32_t otg_blank_data_double_buffer_en; /* OTG_DOUBLE_BUFFER_CONTROL->OTG_BLANK_DATA_DOUBLE_BUFFER_EN from blank data double buffer enable */ + + /* OTG Vertical Interrupts - 6 fields */ + uint32_t otg_vertical_interrupt0_int_enable; /* OTG_VERTICAL_INTERRUPT0_CONTROL->OTG_VERTICAL_INTERRUPT0_INT_ENABLE from interrupt 0 enable */ + uint32_t otg_vertical_interrupt0_line_start; /* OTG_VERTICAL_INTERRUPT0_POSITION->OTG_VERTICAL_INTERRUPT0_LINE_START from start_line parameter */ + uint32_t otg_vertical_interrupt1_int_enable; /* OTG_VERTICAL_INTERRUPT1_CONTROL->OTG_VERTICAL_INTERRUPT1_INT_ENABLE from interrupt 1 enable */ + uint32_t otg_vertical_interrupt1_line_start; /* OTG_VERTICAL_INTERRUPT1_POSITION->OTG_VERTICAL_INTERRUPT1_LINE_START from start_line parameter */ + uint32_t otg_vertical_interrupt2_int_enable; /* OTG_VERTICAL_INTERRUPT2_CONTROL->OTG_VERTICAL_INTERRUPT2_INT_ENABLE from interrupt 2 enable */ + uint32_t otg_vertical_interrupt2_line_start; /* OTG_VERTICAL_INTERRUPT2_POSITION->OTG_VERTICAL_INTERRUPT2_LINE_START from start_line parameter */ + + /* OTG Global Sync Parameters - 6 fields */ + uint32_t otg_vready_offset; /* OTG_VREADY_PARAM->OTG_VREADY_OFFSET from vready_offset parameter */ + uint32_t otg_vstartup_start; /* OTG_VSTARTUP_PARAM->OTG_VSTARTUP_START from vstartup_start parameter */ + uint32_t otg_vupdate_offset; /* OTG_VUPDATE_PARAM->OTG_VUPDATE_OFFSET from vupdate_offset parameter */ + uint32_t otg_vupdate_width; /* OTG_VUPDATE_PARAM->OTG_VUPDATE_WIDTH from vupdate_width parameter */ + uint32_t master_update_lock_vupdate_keepout_start_offset; /* OTG_VUPDATE_KEEPOUT->MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET from pstate_keepout start */ + uint32_t master_update_lock_vupdate_keepout_end_offset; /* OTG_VUPDATE_KEEPOUT->MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET from pstate_keepout end */ + + /* OTG Manual Trigger Control - 11 fields */ + uint32_t otg_triga_source_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_SOURCE_SELECT from trigger A source selection */ + uint32_t otg_triga_source_pipe_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_SOURCE_PIPE_SELECT from trigger A pipe selection */ + uint32_t otg_triga_rising_edge_detect_cntl; /* OTG_TRIGA_CNTL->OTG_TRIGA_RISING_EDGE_DETECT_CNTL from trigger A rising edge detect */ + uint32_t otg_triga_falling_edge_detect_cntl; /* OTG_TRIGA_CNTL->OTG_TRIGA_FALLING_EDGE_DETECT_CNTL from trigger A falling edge detect */ + uint32_t otg_triga_polarity_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_POLARITY_SELECT from trigger A polarity selection */ + uint32_t otg_triga_frequency_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_FREQUENCY_SELECT from trigger A frequency selection */ + uint32_t otg_triga_delay; /* OTG_TRIGA_CNTL->OTG_TRIGA_DELAY from trigger A delay */ + uint32_t otg_triga_clear; /* OTG_TRIGA_CNTL->OTG_TRIGA_CLEAR from trigger A clear */ + uint32_t otg_triga_manual_trig; /* OTG_TRIGA_MANUAL_TRIG->OTG_TRIGA_MANUAL_TRIG from manual trigger A */ + uint32_t otg_trigb_source_select; /* OTG_TRIGB_CNTL->OTG_TRIGB_SOURCE_SELECT from trigger B source selection */ + uint32_t otg_trigb_polarity_select; /* OTG_TRIGB_CNTL->OTG_TRIGB_POLARITY_SELECT from trigger B polarity selection */ + uint32_t otg_trigb_manual_trig; /* OTG_TRIGB_MANUAL_TRIG->OTG_TRIGB_MANUAL_TRIG from manual trigger B */ + + /* OTG Static Screen and Update Control - 6 fields */ + uint32_t otg_static_screen_event_mask; /* OTG_STATIC_SCREEN_CONTROL->OTG_STATIC_SCREEN_EVENT_MASK from event_triggers parameter */ + uint32_t otg_static_screen_frame_count; /* OTG_STATIC_SCREEN_CONTROL->OTG_STATIC_SCREEN_FRAME_COUNT from num_frames parameter */ + uint32_t master_update_lock; /* OTG_MASTER_UPDATE_LOCK->MASTER_UPDATE_LOCK from update lock control */ + uint32_t master_update_mode; /* OTG_MASTER_UPDATE_MODE->MASTER_UPDATE_MODE from update mode selection */ + uint32_t otg_force_count_now_mode; /* OTG_FORCE_COUNT_NOW_CNTL->OTG_FORCE_COUNT_NOW_MODE from force count mode */ + uint32_t otg_force_count_now_clear; /* OTG_FORCE_COUNT_NOW_CNTL->OTG_FORCE_COUNT_NOW_CLEAR from force count clear */ + + /* VTG Control - 3 fields */ + uint32_t vtg0_enable; /* CONTROL->VTG0_ENABLE from VTG enable control */ + uint32_t vtg0_fp2; /* CONTROL->VTG0_FP2 from VTG front porch 2 */ + uint32_t vtg0_vcount_init; /* CONTROL->VTG0_VCOUNT_INIT from VTG vertical count init */ + + /* OTG Status (Read-Only) - 12 fields */ + uint32_t otg_v_blank; /* OTG_STATUS->OTG_V_BLANK from vertical blank status (read-only) */ + uint32_t otg_v_active_disp; /* OTG_STATUS->OTG_V_ACTIVE_DISP from vertical active display (read-only) */ + uint32_t otg_frame_count; /* OTG_STATUS_FRAME_COUNT->OTG_FRAME_COUNT from frame count (read-only) */ + uint32_t otg_horz_count; /* OTG_STATUS_POSITION->OTG_HORZ_COUNT from horizontal position (read-only) */ + uint32_t otg_vert_count; /* OTG_STATUS_POSITION->OTG_VERT_COUNT from vertical position (read-only) */ + uint32_t otg_horz_count_hv; /* OTG_STATUS_HV_COUNT->OTG_HORZ_COUNT from horizontal count (read-only) */ + uint32_t otg_vert_count_nom; /* OTG_STATUS_HV_COUNT->OTG_VERT_COUNT_NOM from vertical count nominal (read-only) */ + uint32_t otg_flip_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_FLIP_PENDING from flip pending status (read-only) */ + uint32_t otg_dc_reg_update_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_DC_REG_UPDATE_PENDING from DC register update pending (read-only) */ + uint32_t otg_cursor_update_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_CURSOR_UPDATE_PENDING from cursor update pending (read-only) */ + uint32_t otg_vupdate_keepout_status; /* OTG_PIPE_UPDATE_STATUS->OTG_VUPDATE_KEEPOUT_STATUS from VUPDATE keepout status (read-only) */ + } optc[MAX_PIPES]; + + /* Metadata */ + uint32_t active_pipe_count; + uint32_t active_stream_count; + bool state_valid; +}; + +/** + * dc_capture_register_software_state() - Capture software state for register programming + * @dc: DC context containing current display configuration + * @state: Pointer to dc_register_software_state structure to populate + * + * Extracts all software state variables that are used to program hardware register + * fields across the display driver pipeline. This provides a complete snapshot + * of the software configuration that drives hardware register programming. + * + * The function traverses the DC context and extracts values from: + * - Stream configurations (timing, format, DSC settings) + * - Plane states (surface format, rotation, scaling, cursor) + * - Pipe contexts (resource allocation, blending, viewport) + * - Clock manager (display clocks, DPP clocks, pixel clocks) + * - Resource context (DET buffer allocation, ODM configuration) + * + * This is essential for underflow debugging as it captures the exact software + * state that determines how registers are programmed, allowing analysis of + * whether underflow is caused by incorrect register programming or timing issues. + * + * Return: true if state was successfully captured, false on error + */ +bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state); + #endif /* DC_INTERFACE_H_ */ From d6dfbc7a42f9fcff903e66f6af132fb376ff0909 Mon Sep 17 00:00:00 2001 From: Jack Chang Date: Fri, 8 Aug 2025 11:20:56 +0800 Subject: [PATCH 2577/2653] drm/amd/display: Add panel replay capability detection [Why&How] For supporting VESA PR, add flow to determine the support capability Reviewed-by: Robin Chen Signed-off-by: Jack Chang Signed-off-by: Leon Huang Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 1 + drivers/gpu/drm/amd/display/dc/dc_types.h | 9 +++++++++ drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c | 13 +++++++++++++ drivers/gpu/drm/amd/display/dc/link/link_factory.c | 2 ++ 4 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index a14016a3bea4f..1b630da638155 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -303,6 +303,7 @@ static bool create_links( link->link_id.id = CONNECTOR_ID_VIRTUAL; link->link_id.enum_id = ENUM_ID_1; link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; + link->replay_settings.config.replay_version = DC_REPLAY_VERSION_UNSUPPORTED; link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL); if (!link->link_enc) { diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 0495e6cfcca07..f46039f642034 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -941,6 +941,12 @@ enum dc_psr_version { DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, }; +enum dc_replay_version { + DC_FREESYNC_REPLAY = 0, + DC_VESA_PANEL_REPLAY = 1, + DC_REPLAY_VERSION_UNSUPPORTED = 0XFF, +}; + /* Possible values of display_endpoint_id.endpoint */ enum display_endpoint_type { DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */ @@ -1093,6 +1099,7 @@ enum replay_FW_Message_type { Replay_Set_Residency_Frameupdate_Timer, Replay_Set_Pseudo_VTotal, Replay_Disabled_Adaptive_Sync_SDP, + Replay_Set_Version, Replay_Set_General_Cmd, }; @@ -1128,6 +1135,8 @@ union replay_low_refresh_rate_enable_options { }; struct replay_config { + /* Replay version */ + enum dc_replay_version replay_version; /* Replay feature is supported */ bool replay_supported; /* Replay caps support DPCD & EDID caps*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c index fd8244c946874..cf1372aaff6c9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c @@ -387,6 +387,19 @@ static void dmub_replay_send_cmd(struct dmub_replay *dmub, cmd.replay_disabled_adaptive_sync_sdp.data.force_disabled = cmd_element->disabled_adaptive_sync_sdp_data.force_disabled; break; + case Replay_Set_Version: + //Header + cmd.replay_set_version.header.sub_type = + DMUB_CMD__REPLAY_SET_VERSION; + cmd.replay_set_version.header.payload_bytes = + sizeof(struct dmub_rb_cmd_replay_set_version) - + sizeof(struct dmub_cmd_header); + //Cmd Body + cmd.replay_set_version.replay_set_version_data.panel_inst = + cmd_element->version_data.panel_inst; + cmd.replay_set_version.replay_set_version_data.version = + cmd_element->version_data.version; + break; case Replay_Set_General_Cmd: //Header cmd.replay_set_general_cmd.header.sub_type = diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c index 7989baf3843c9..5229f2a9a794d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@ -787,6 +787,7 @@ static bool construct_phy(struct dc_link *link, link->psr_settings.psr_vtotal_control_support = false; link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; + link->replay_settings.config.replay_version = DC_REPLAY_VERSION_UNSUPPORTED; DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__); return true; @@ -868,6 +869,7 @@ static bool construct_dpia(struct dc_link *link, /* TODO: Create link encoder */ link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; + link->replay_settings.config.replay_version = DC_REPLAY_VERSION_UNSUPPORTED; return true; From a832be6a07bcbe5b7628ef0314cc04661643e7ed Mon Sep 17 00:00:00 2001 From: Jack Chang Date: Thu, 21 Aug 2025 13:19:23 +0800 Subject: [PATCH 2578/2653] drm/amd/display: Add panel replay enablement option and logic [Why&How] 1.Add flow to enable and configure panel replay enablement and configuration 2.Add registry key for enable option 3.Add replay version check to be compatible with freesync replay 4.Add AC/DC switch function to notify ac/dc change. 5.Add flow in set event function to check and decide Replay enable/disable Reviewed-by: Robin Chen Signed-off-by: Jack Chang Signed-off-by: Leon Huang Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 25 ++++ .../link/protocols/link_edp_panel_control.c | 126 +++++++++++++++++- .../gpu/drm/amd/display/include/dpcd_defs.h | 16 +++ .../amd/display/modules/power/power_helpers.c | 3 + 4 files changed, 168 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index db669ccb1d587..17bcff25a2626 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -1346,6 +1346,31 @@ union dpcd_replay_configuration { unsigned char raw; }; +union panel_replay_enable_and_configuration_1 { + struct { + unsigned char PANEL_REPLAY_ENABLE :1; + unsigned char PANEL_REPLAY_CRC_ENABLE :1; + unsigned char IRQ_HPD_ASSDP_MISSING :1; + unsigned char IRQ_HPD_VSCSDP_UNCORRECTABLE_ERROR :1; + unsigned char IRQ_HPD_RFB_ERROR :1; + unsigned char IRQ_HPD_ACTIVE_FRAME_CRC_ERROR :1; + unsigned char PANEL_REPLAY_SELECTIVE_UPDATE_ENABLE :1; + unsigned char PANEL_REPLAY_EARLY_TRANSPORT_ENABLE :1; + } bits; + unsigned char raw; +}; + +union panel_replay_enable_and_configuration_2 { + struct { + unsigned char SINK_REFRESH_RATE_UNLOCK_GRANTED :1; + unsigned char RESERVED :1; + unsigned char SU_Y_GRANULARITY_EXT_VALUE_ENABLED :1; + unsigned char SU_Y_GRANULARITY_EXT_VALUE :4; + unsigned char SU_REGION_SCAN_LINE_CAPTURE_INDICATION :1; + } bits; + unsigned char raw; +}; + union dpcd_alpm_configuration { struct { unsigned char ENABLE : 1; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 9391c75a30e57..c56e69eb27efe 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -949,7 +949,7 @@ bool edp_set_replay_allow_active(struct dc_link *link, const bool *allow_active, /* Set power optimization flag */ if (power_opts && link->replay_settings.replay_power_opt_active != *power_opts) { if (replay != NULL && link->replay_settings.replay_feature_enabled && - replay->funcs->replay_set_power_opt) { + replay->funcs->replay_set_power_opt) { replay->funcs->replay_set_power_opt(replay, *power_opts, panel_inst); link->replay_settings.replay_power_opt_active = *power_opts; } @@ -984,7 +984,117 @@ bool edp_get_replay_state(const struct dc_link *link, uint64_t *state) return true; } -bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream) +static bool edp_setup_panel_replay(struct dc_link *link, const struct dc_stream_state *stream) +{ + /* To-do: Setup Replay */ + struct dc *dc; + struct dmub_replay *replay; + int i; + unsigned int panel_inst; + struct replay_context replay_context = { 0 }; + unsigned int lineTimeInNs = 0; + + union panel_replay_enable_and_configuration_1 pr_config_1 = { 0 }; + union panel_replay_enable_and_configuration_2 pr_config_2 = { 0 }; + + union dpcd_alpm_configuration alpm_config; + + replay_context.controllerId = CONTROLLER_ID_UNDEFINED; + + if (!link) + return false; + + //Clear Panel Replay enable & config + dm_helpers_dp_write_dpcd(link->ctx, link, + DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1, + (uint8_t *)&(pr_config_1.raw), sizeof(uint8_t)); + + dm_helpers_dp_write_dpcd(link->ctx, link, + DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2, + (uint8_t *)&(pr_config_2.raw), sizeof(uint8_t)); + + if (!(link->replay_settings.config.replay_supported)) + return false; + + dc = link->ctx->dc; + + //not sure should keep or not + replay = dc->res_pool->replay; + + if (!replay) + return false; + + if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) + return false; + + replay_context.aux_inst = link->ddc->ddc_pin->hw_info.ddc_channel; + replay_context.digbe_inst = link->link_enc->transmitter; + replay_context.digfe_inst = link->link_enc->preferred_engine; + + for (i = 0; i < MAX_PIPES; i++) { + if (dc->current_state->res_ctx.pipe_ctx[i].stream + == stream) { + /* dmcu -1 for all controller id values, + * therefore +1 here + */ + replay_context.controllerId = + dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1; + break; + } + } + + lineTimeInNs = + ((stream->timing.h_total * 1000000) / + (stream->timing.pix_clk_100hz / 10)) + 1; + + replay_context.line_time_in_ns = lineTimeInNs; + + link->replay_settings.replay_feature_enabled = + replay->funcs->replay_copy_settings(replay, link, &replay_context, panel_inst); + + if (link->replay_settings.replay_feature_enabled) { + pr_config_1.bits.PANEL_REPLAY_ENABLE = 1; + pr_config_1.bits.PANEL_REPLAY_CRC_ENABLE = 1; + pr_config_1.bits.IRQ_HPD_ASSDP_MISSING = 1; + pr_config_1.bits.IRQ_HPD_VSCSDP_UNCORRECTABLE_ERROR = 1; + pr_config_1.bits.IRQ_HPD_RFB_ERROR = 1; + pr_config_1.bits.IRQ_HPD_ACTIVE_FRAME_CRC_ERROR = 1; + pr_config_1.bits.PANEL_REPLAY_SELECTIVE_UPDATE_ENABLE = 1; + pr_config_1.bits.PANEL_REPLAY_EARLY_TRANSPORT_ENABLE = 1; + + pr_config_2.bits.SINK_REFRESH_RATE_UNLOCK_GRANTED = 0; + pr_config_2.bits.SU_Y_GRANULARITY_EXT_VALUE_ENABLED = 0; + pr_config_2.bits.SU_REGION_SCAN_LINE_CAPTURE_INDICATION = 0; + + dm_helpers_dp_write_dpcd(link->ctx, link, + DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1, + (uint8_t *)&(pr_config_1.raw), sizeof(uint8_t)); + + dm_helpers_dp_write_dpcd(link->ctx, link, + DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2, + (uint8_t *)&(pr_config_2.raw), sizeof(uint8_t)); + + //ALPM Setup + memset(&alpm_config, 0, sizeof(alpm_config)); + alpm_config.bits.ENABLE = link->replay_settings.config.alpm_mode != DC_ALPM_UNSUPPORTED ? 1 : 0; + + if (link->replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) { + alpm_config.bits.ALPM_MODE_SEL = 1; + alpm_config.bits.ACDS_PERIOD_DURATION = 1; + } + + dm_helpers_dp_write_dpcd( + link->ctx, + link, + DP_RECEIVER_ALPM_CONFIG, + &alpm_config.raw, + sizeof(alpm_config.raw)); + } + + return true; +} + +static bool edp_setup_freesync_replay(struct dc_link *link, const struct dc_stream_state *stream) { /* To-do: Setup Replay */ struct dc *dc; @@ -1080,6 +1190,18 @@ bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream return true; } +bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream) +{ + if (!link) + return false; + if (link->replay_settings.config.replay_version == DC_VESA_PANEL_REPLAY) + return edp_setup_panel_replay(link, stream); + else if (link->replay_settings.config.replay_version == DC_FREESYNC_REPLAY) + return edp_setup_freesync_replay(link, stream); + else + return false; +} + /* * This is general Interface for Replay to set an 32 bit variable to dmub * replay_FW_Message_type: Indicates which instruction or variable pass to DMUB diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h b/drivers/gpu/drm/amd/display/include/dpcd_defs.h index de8f3cfed6c84..07b937b92efc7 100644 --- a/drivers/gpu/drm/amd/display/include/dpcd_defs.h +++ b/drivers/gpu/drm/amd/display/include/dpcd_defs.h @@ -30,6 +30,22 @@ #ifndef DP_SINK_HW_REVISION_START // can remove this once the define gets into linux drm_dp_helper.h #define DP_SINK_HW_REVISION_START 0x409 #endif +/* Panel Replay*/ +#ifndef DP_PANEL_REPLAY_CAPABILITY_SUPPORT // can remove this once the define gets into linux drm_dp_helper.h +#define DP_PANEL_REPLAY_CAPABILITY_SUPPORT 0x0b0 +#endif /* DP_PANEL_REPLAY_CAPABILITY_SUPPORT */ +#ifndef DP_PANEL_REPLAY_CAPABILITY // can remove this once the define gets into linux drm_dp_helper.h +#define DP_PANEL_REPLAY_CAPABILITY 0x0b1 +#endif /* DP_PANEL_REPLAY_CAPABILITY */ +#ifndef DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1 // can remove this once the define gets into linux drm_dp_helper.h +#define DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1 0x1b0 +#endif /* DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1 */ +#ifndef DP_PANEL_REPLAY_ENABLE // can remove this once the define gets into linux drm_dp_helper.h +#define DP_PANEL_REPLAY_ENABLE (1 << 0) +#endif /* DP_PANEL_REPLAY_ENABLE */ +#ifndef DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 // can remove this once the define gets into linux drm_dp_helper.h +#define DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 0x1b1 +#endif /* DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 */ enum dpcd_revision { DPCD_REV_10 = 0x10, diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c index 88b5b716a0847..fd139b219bf9a 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c @@ -1037,6 +1037,9 @@ void calculate_replay_link_off_frame_count(struct dc_link *link, uint8_t max_link_off_frame_count = 0; uint16_t max_deviation_line = 0, pixel_deviation_per_line = 0; + if (!link || link->replay_settings.config.replay_version != DC_FREESYNC_REPLAY) + return; + max_deviation_line = link->dpcd_caps.pr_info.max_deviation_line; pixel_deviation_per_line = link->dpcd_caps.pr_info.pixel_deviation_per_line; From a1e34604c0f61eda72208006f83d4431165ceeec Mon Sep 17 00:00:00 2001 From: Jack Chang Date: Wed, 20 Aug 2025 16:59:08 +0800 Subject: [PATCH 2579/2653] drm/amd/display: Get panel replay capability from DPCD [Why&How] Read Panel replay caps from DPCD when retrieving link capability Reviewed-by: Robin Chen Signed-off-by: Jack Chang Signed-off-by: Leon Huang Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 11 +++++++++++ .../display/dc/link/protocols/link_dp_capability.c | 5 +++++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index 17bcff25a2626..79e1696def630 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -1157,6 +1157,16 @@ struct dprx_states { bool cable_id_written; }; +union dpcd_panel_replay_capability_supported { + struct { + unsigned char PANEL_REPLAY_SUPPORT :1; + unsigned char SELECTIVE_UPDATE_SUPPORT :1; + unsigned char EARLY_TRANSPORT_SUPPORT :1; + unsigned char RESERVED :5; + } bits; + unsigned char raw; +}; + enum dpcd_downstream_port_max_bpc { DOWN_STREAM_MAX_8BPC = 0, DOWN_STREAM_MAX_10BPC, @@ -1280,6 +1290,7 @@ struct dpcd_caps { struct edp_psr_info psr_info; struct replay_info pr_info; + union dpcd_panel_replay_capability_supported pr_caps_supported; uint16_t edp_oled_emission_rate; union dp_receive_port0_cap receive_port0_cap; /* Indicates the number of SST links supported by MSO (Multi-Stream Output) */ diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index e480a87e7cf61..68cfb86deee12 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -2092,6 +2092,11 @@ static bool retrieve_link_cap(struct dc_link *link) link->dpcd_caps.max_uncompressed_pixel_rate_cap.raw, sizeof(link->dpcd_caps.max_uncompressed_pixel_rate_cap.raw)); + core_link_read_dpcd(link, + DP_PANEL_REPLAY_CAPABILITY_SUPPORT, + &link->dpcd_caps.pr_caps_supported.raw, + sizeof(link->dpcd_caps.pr_caps_supported.raw)); + /* Read DP tunneling information. */ status = dpcd_get_tunneling_device_data(link); if (status != DC_OK) From 816edac9fefa63b126212468d1a44cbd36bf46e9 Mon Sep 17 00:00:00 2001 From: Paul Hsieh Date: Thu, 30 Oct 2025 12:17:53 +0800 Subject: [PATCH 2580/2653] drm/amd/display: Re-check seamless boot can be enabled or not [Why] If the seamless boot feature has already been enabled, and dc_commit_streams is called again before receiving a flip, the driver will adjust the engine clock without turning off the screen, which will cause garbage to occur. However, in reality, the Pixel Clock from the first dc_commit_streams and the second dc_commit_streams are different. [How] If the apply seamless boot flag in the previous stream has not been cleared, and dc_commit_streams is received again, we need to recheck whether seamless boot should be disabled Reviewed-by: Nicholas Kazlauskas Signed-off-by: Paul Hsieh Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 1b630da638155..7c5a2fa5b0e11 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2147,6 +2147,14 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c if (!dcb->funcs->is_accelerated_mode(dcb)) { disable_vbios_mode_if_required(dc, context); dc->hwss.enable_accelerated_mode(dc, context); + } else if (get_seamless_boot_stream_count(dc->current_state) > 0) { + /* If the previous Stream still retains the apply seamless boot flag, + * it means the OS has not actually performed a flip yet. + * At this point, if we receive dc_commit_streams again, we should + * once more check whether the actual HW timing matches what the OS + * has provided + */ + disable_vbios_mode_if_required(dc, context); } if (dc->hwseq->funcs.wait_for_pipe_update_if_needed) { From 9867884348c284a2d05b9c1b28ae0c5c038f12fa Mon Sep 17 00:00:00 2001 From: "Mario Limonciello (AMD)" Date: Mon, 3 Nov 2025 11:17:44 -0600 Subject: [PATCH 2581/2653] drm/amd/display: Move sleep into each retry for retrieve_link_cap() [Why] When a monitor is booting it's possible that it isn't ready to retrieve link caps and this can lead to an EDID read failure: ``` [drm:retrieve_link_cap [amdgpu]] *ERROR* retrieve_link_cap: Read receiver caps dpcd data failed. amdgpu 0000:c5:00.0: [drm] *ERROR* No EDID read. ``` [How] Rather than msleep once and try a few times, msleep each time. Should be no changes for existing working monitors, but should correct reading caps on a monitor that is slow to boot. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4672 Reviewed-by: Alex Hung Signed-off-by: Mario Limonciello (AMD) Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- .../amd/display/dc/link/protocols/link_dp_capability.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 68cfb86deee12..31851720808de 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -1757,12 +1757,13 @@ static bool retrieve_link_cap(struct dc_link *link) } dpcd_set_source_specific_data(link); - /* Sink may need to configure internals based on vendor, so allow some - * time before proceeding with possibly vendor specific transactions - */ - msleep(post_oui_delay); for (i = 0; i < read_dpcd_retry_cnt; i++) { + /* + * Sink may need to configure internals based on vendor, so allow some + * time before proceeding with possibly vendor specific transactions + */ + msleep(post_oui_delay); status = core_link_read_dpcd( link, DP_DPCD_REV, From 49c54079db1e2f57e287d9ae41fd89ab202f58e2 Mon Sep 17 00:00:00 2001 From: "Mario Limonciello (AMD)" Date: Mon, 3 Nov 2025 12:11:31 -0600 Subject: [PATCH 2582/2653] drm/amd/display: Increase DPCD read retries [Why] Empirical measurement of some monitors that fail to read EDID while booting shows that the number of retries with a 30ms delay between tries is as high as 16. [How] Increase number of retries to 20. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4672 Reviewed-by: Alex Hung Signed-off-by: Mario Limonciello (AMD) Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 31851720808de..5a8e7043aeef2 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -1714,7 +1714,7 @@ static bool retrieve_link_cap(struct dc_link *link) union edp_configuration_cap edp_config_cap; union dp_downstream_port_present ds_port = { 0 }; enum dc_status status = DC_ERROR_UNEXPECTED; - uint32_t read_dpcd_retry_cnt = 3; + uint32_t read_dpcd_retry_cnt = 20; int i; struct dp_sink_hw_fw_revision dp_hw_fw_revision; const uint32_t post_oui_delay = 30; // 30ms From f65ee2d1e9cc92cb1a38de171909086ced750712 Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Thu, 30 Oct 2025 11:25:33 -0400 Subject: [PATCH 2583/2653] drm/amd/display: Add an HPD filter for HDMI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [Why] Some monitors perform rapid “autoscan” HPD re‑assertions right after a disconnect or powersaving mode enablement. These appear as a quick disconnect→reconnect with an identical EDID. Since Linux has no HDMI hotplug detection (HPD) filter, these quick reconnects are seen as hotplug events, which can unintentionally wake a system with DPMS off. An example: https://gitlab.freedesktop.org/drm/amd/-/issues/2876 Such 'fake reconnects' are considered when the interval between a disconnect and a connect is within 1500ms (experimentally chosen using several monitors), and the two connections have the same EDID. [How] Implement a time-based debounce mechanism: 1. On HDMI disconnect detection, instead of immediately processing the HPD event, save the current sink and schedule delayed work (default 1500ms) 2. If another HDMI disconnect HPD event arrives during the debounce period, it reschedules the pending work, ensuring only the final state is processed. 3. When the debounce timer expires, re-detect the display and compare the new sink with the cached one using EDID comparison. 4. If sinks match (same EDID), this was a spontaneous HPD toggle: - Update connector state internally - Skip hotplug event to prevent desktop rearrangement If sinks differ, this was a real display change: - Process normally with the hotplug event The debounce delay is configurable via module parameter 'hdmi_hpd_debounce_delay_ms'. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2876 Reviewed-by: Sun peng (Leo) Li Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 138 ++++++++++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 6 + 2 files changed, 144 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5d71c757d679f..9a4f66c34a320 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3992,6 +3992,97 @@ void amdgpu_dm_update_connector_after_detect( mutex_unlock(&dev->mode_config.mutex); } +static bool are_sinks_equal(const struct dc_sink *sink1, const struct dc_sink *sink2) +{ + if (!sink1 || !sink2) + return false; + if (sink1->sink_signal != sink2->sink_signal) + return false; + + if (sink1->dc_edid.length != sink2->dc_edid.length) + return false; + + if (memcmp(sink1->dc_edid.raw_edid, sink2->dc_edid.raw_edid, + sink1->dc_edid.length) != 0) + return false; + return true; +} + + +/** + * DOC: hdmi_hpd_debounce_work + * + * HDMI HPD debounce delay in milliseconds. When an HDMI display toggles HPD + * (such as during power save transitions), this delay determines how long to + * wait before processing the HPD event. This allows distinguishing between a + * physical unplug (>hdmi_hpd_debounce_delay) + * and a spontaneous RX HPD toggle (base; + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = drm_to_adev(dev); + struct dc *dc = aconnector->dc_link->ctx->dc; + bool fake_reconnect = false; + bool reallow_idle = false; + bool ret = false; + guard(mutex)(&aconnector->hpd_lock); + + /* Re-detect the display */ + scoped_guard(mutex, &adev->dm.dc_lock) { + if (dc->caps.ips_support && dc->ctx->dmub_srv->idle_allowed) { + dc_allow_idle_optimizations(dc, false); + reallow_idle = true; + } + ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); + } + + if (ret) { + /* Apply workaround delay for certain panels */ + apply_delay_after_dpcd_poweroff(adev, aconnector->dc_sink); + /* Compare sinks to determine if this was a spontaneous HPD toggle */ + if (are_sinks_equal(aconnector->dc_link->local_sink, aconnector->hdmi_prev_sink)) { + /* + * Sinks match - this was a spontaneous HDMI HPD toggle. + */ + drm_dbg_kms(dev, "HDMI HPD: Sink unchanged after debounce, internal re-enable\n"); + fake_reconnect = true; + } + + /* Update connector state */ + amdgpu_dm_update_connector_after_detect(aconnector); + + drm_modeset_lock_all(dev); + dm_restore_drm_connector_state(dev, connector); + drm_modeset_unlock_all(dev); + + /* Only notify OS if sink actually changed */ + if (!fake_reconnect && aconnector->base.force == DRM_FORCE_UNSPECIFIED) + drm_kms_helper_hotplug_event(dev); + } + + /* Release the cached sink reference */ + if (aconnector->hdmi_prev_sink) { + dc_sink_release(aconnector->hdmi_prev_sink); + aconnector->hdmi_prev_sink = NULL; + } + + scoped_guard(mutex, &adev->dm.dc_lock) { + if (reallow_idle && dc->caps.ips_support) + dc_allow_idle_optimizations(dc, true); + } +} + static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) { struct drm_connector *connector = &aconnector->base; @@ -4001,6 +4092,7 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); struct dc *dc = aconnector->dc_link->ctx->dc; bool ret = false; + bool debounce_required = false; if (adev->dm.disable_hpd_irq) return; @@ -4023,6 +4115,14 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); + /* + * Check for HDMI disconnect with debounce enabled. + */ + debounce_required = (aconnector->hdmi_hpd_debounce_delay_ms > 0 && + dc_is_hdmi_signal(aconnector->dc_link->connector_signal) && + new_connection_type == dc_connection_none && + aconnector->dc_link->local_sink != NULL); + if (aconnector->base.force && new_connection_type == dc_connection_none) { emulated_link_detect(aconnector->dc_link); @@ -4032,7 +4132,34 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) drm_kms_helper_connector_hotplug_event(connector); + } else if (debounce_required) { + /* + * HDMI disconnect detected - schedule delayed work instead of + * processing immediately. This allows us to coalesce spurious + * HDMI signals from physical unplugs. + */ + drm_dbg_kms(dev, "HDMI HPD: Disconnect detected, scheduling debounce work (%u ms)\n", + aconnector->hdmi_hpd_debounce_delay_ms); + + /* Cache the current sink for later comparison */ + if (aconnector->hdmi_prev_sink) + dc_sink_release(aconnector->hdmi_prev_sink); + aconnector->hdmi_prev_sink = aconnector->dc_link->local_sink; + if (aconnector->hdmi_prev_sink) + dc_sink_retain(aconnector->hdmi_prev_sink); + + /* Schedule delayed detection. */ + if (mod_delayed_work(system_wq, + &aconnector->hdmi_hpd_debounce_work, + msecs_to_jiffies(aconnector->hdmi_hpd_debounce_delay_ms))) + drm_dbg_kms(dev, "HDMI HPD: Re-scheduled debounce work\n"); + } else { + + /* If the aconnector->hdmi_hpd_debounce_work is scheduled, exit early */ + if (delayed_work_pending(&aconnector->hdmi_hpd_debounce_work)) + return; + scoped_guard(mutex, &adev->dm.dc_lock) { dc_exit_ips_for_hw_access(dc); ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); @@ -7710,6 +7837,13 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector) if (aconnector->mst_mgr.dev) drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); + /* Cancel and flush any pending HDMI HPD debounce work */ + cancel_delayed_work_sync(&aconnector->hdmi_hpd_debounce_work); + if (aconnector->hdmi_prev_sink) { + dc_sink_release(aconnector->hdmi_prev_sink); + aconnector->hdmi_prev_sink = NULL; + } + if (aconnector->bl_idx != -1) { backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]); dm->backlight_dev[aconnector->bl_idx] = NULL; @@ -9036,6 +9170,10 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, mutex_init(&aconnector->hpd_lock); mutex_init(&aconnector->handle_mst_msg_ready); + aconnector->hdmi_hpd_debounce_delay_ms = AMDGPU_DM_HDMI_HPD_DEBOUNCE_MS; + INIT_DELAYED_WORK(&aconnector->hdmi_hpd_debounce_work, hdmi_hpd_debounce_work); + aconnector->hdmi_prev_sink = NULL; + /* * configure support HPD hot plug connector_>polled default value is 0 * which means HPD hot plug not supported diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index ca8750412ac10..f840cf8e8056d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -59,6 +59,7 @@ #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) +#define AMDGPU_DM_HDMI_HPD_DEBOUNCE_MS 1500 /* #include "include/amdgpu_dal_power_if.h" #include "amdgpu_dm_irq.h" @@ -825,6 +826,11 @@ struct amdgpu_dm_connector { bool pack_sdp_v1_3; enum adaptive_sync_type as_type; struct amdgpu_hdmi_vsdb_info vsdb_info; + + /* HDMI HPD debounce support */ + unsigned int hdmi_hpd_debounce_delay_ms; + struct delayed_work hdmi_hpd_debounce_work; + struct dc_sink *hdmi_prev_sink; }; static inline void amdgpu_dm_set_mst_status(uint8_t *status, From ac4cb7b307aabfe79f9bbe8ef6dee2ce715d7da7 Mon Sep 17 00:00:00 2001 From: Nicholas Carbones Date: Fri, 31 Oct 2025 16:36:09 -0400 Subject: [PATCH 2584/2653] drm/amd/display: Add pipe topology history to dc [Why] There is no way to check pipe topology update history through a dump. [How] Add a topology history structure to dc with snapshots of the most recent pipe topology updates. Reviewed-by: George Shen Signed-off-by: Nicholas Carbones Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- .../gpu/drm/amd/display/dc/core/dc_resource.c | 76 +++++++++++++++++-- drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 26 +++++++ 3 files changed, 97 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index dc0c4065a92cb..848c267ef11e7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -99,6 +99,40 @@ #define UNABLE_TO_SPLIT -1 +static void capture_pipe_topology_data(struct dc *dc, int plane_idx, int slice_idx, int stream_idx, + int dpp_inst, int opp_inst, int tg_inst, bool is_phantom_pipe) +{ + struct pipe_topology_snapshot *current_snapshot = &dc->debug_data.topology_history.snapshots[dc->debug_data.topology_history.current_snapshot_index]; + + if (current_snapshot->line_count >= MAX_PIPES) + return; + + current_snapshot->pipe_log_lines[current_snapshot->line_count].is_phantom_pipe = is_phantom_pipe; + current_snapshot->pipe_log_lines[current_snapshot->line_count].plane_idx = plane_idx; + current_snapshot->pipe_log_lines[current_snapshot->line_count].slice_idx = slice_idx; + current_snapshot->pipe_log_lines[current_snapshot->line_count].stream_idx = stream_idx; + current_snapshot->pipe_log_lines[current_snapshot->line_count].dpp_inst = dpp_inst; + current_snapshot->pipe_log_lines[current_snapshot->line_count].opp_inst = opp_inst; + current_snapshot->pipe_log_lines[current_snapshot->line_count].tg_inst = tg_inst; + + current_snapshot->line_count++; +} + +static void start_new_topology_snapshot(struct dc *dc, struct dc_state *state) +{ + // Move to next snapshot slot (circular buffer) + dc->debug_data.topology_history.current_snapshot_index = (dc->debug_data.topology_history.current_snapshot_index + 1) % MAX_TOPOLOGY_SNAPSHOTS; + + // Clear the new snapshot + struct pipe_topology_snapshot *current_snapshot = &dc->debug_data.topology_history.snapshots[dc->debug_data.topology_history.current_snapshot_index]; + memset(current_snapshot, 0, sizeof(*current_snapshot)); + + // Set metadata + current_snapshot->timestamp_us = dm_get_timestamp(dc->ctx); + current_snapshot->stream_count = state->stream_count; + current_snapshot->phantom_stream_count = state->phantom_stream_count; +} + enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) { enum dce_version dc_version = DCE_VERSION_UNKNOWN; @@ -2311,10 +2345,11 @@ bool resource_is_odm_topology_changed(const struct pipe_ctx *otg_master_a, static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe, int stream_idx, int slice_idx, int plane_idx, int slice_count, - bool is_primary) + bool is_primary, bool is_phantom_pipe) { DC_LOGGER_INIT(dc->ctx->logger); + // new format for logging: bit storing code if (slice_idx == 0 && plane_idx == 0 && is_primary) { /* case 0 (OTG master pipe with plane) */ DC_LOG_DC(" | plane%d slice%d stream%d|", @@ -2323,6 +2358,10 @@ static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe, pipe->plane_res.dpp->inst, pipe->stream_res.opp->inst, pipe->stream_res.tg->inst); + capture_pipe_topology_data(dc, plane_idx, slice_idx, stream_idx, + pipe->plane_res.dpp->inst, + pipe->stream_res.opp->inst, + pipe->stream_res.tg->inst, is_phantom_pipe); } else if (slice_idx == 0 && plane_idx == -1) { /* case 1 (OTG master pipe without plane) */ DC_LOG_DC(" | slice%d stream%d|", @@ -2331,6 +2370,10 @@ static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe, pipe->stream_res.opp->inst, pipe->stream_res.opp->inst, pipe->stream_res.tg->inst); + capture_pipe_topology_data(dc, 0xF, slice_idx, stream_idx, + pipe->plane_res.dpp->inst, + pipe->stream_res.opp->inst, + pipe->stream_res.tg->inst, is_phantom_pipe); } else if (slice_idx != 0 && plane_idx == 0 && is_primary) { /* case 2 (OPP head pipe with plane) */ DC_LOG_DC(" | plane%d slice%d | |", @@ -2338,27 +2381,43 @@ static void resource_log_pipe(struct dc *dc, struct pipe_ctx *pipe, DC_LOG_DC(" |DPP%d----OPP%d----| |", pipe->plane_res.dpp->inst, pipe->stream_res.opp->inst); + capture_pipe_topology_data(dc, plane_idx, slice_idx, stream_idx, + pipe->plane_res.dpp->inst, + pipe->stream_res.opp->inst, + pipe->stream_res.tg->inst, is_phantom_pipe); } else if (slice_idx != 0 && plane_idx == -1) { /* case 3 (OPP head pipe without plane) */ DC_LOG_DC(" | slice%d | |", slice_idx); DC_LOG_DC(" |DPG%d----OPP%d----| |", pipe->plane_res.dpp->inst, pipe->stream_res.opp->inst); + capture_pipe_topology_data(dc, 0xF, slice_idx, stream_idx, + pipe->plane_res.dpp->inst, + pipe->stream_res.opp->inst, + pipe->stream_res.tg->inst, is_phantom_pipe); } else if (slice_idx == slice_count - 1) { /* case 4 (DPP pipe in last slice) */ DC_LOG_DC(" | plane%d | |", plane_idx); DC_LOG_DC(" |DPP%d----| |", pipe->plane_res.dpp->inst); + capture_pipe_topology_data(dc, plane_idx, slice_idx, stream_idx, + pipe->plane_res.dpp->inst, + pipe->stream_res.opp->inst, + pipe->stream_res.tg->inst, is_phantom_pipe); } else { /* case 5 (DPP pipe not in last slice) */ DC_LOG_DC(" | plane%d | | |", plane_idx); DC_LOG_DC(" |DPP%d----| | |", pipe->plane_res.dpp->inst); + capture_pipe_topology_data(dc, plane_idx, slice_idx, stream_idx, + pipe->plane_res.dpp->inst, + pipe->stream_res.opp->inst, + pipe->stream_res.tg->inst, is_phantom_pipe); } } static void resource_log_pipe_for_stream(struct dc *dc, struct dc_state *state, - struct pipe_ctx *otg_master, int stream_idx) + struct pipe_ctx *otg_master, int stream_idx, bool is_phantom_pipe) { struct pipe_ctx *opp_heads[MAX_PIPES]; struct pipe_ctx *dpp_pipes[MAX_PIPES]; @@ -2384,12 +2443,12 @@ static void resource_log_pipe_for_stream(struct dc *dc, struct dc_state *state, resource_log_pipe(dc, dpp_pipes[dpp_idx], stream_idx, slice_idx, plane_idx, slice_count, - is_primary); + is_primary, is_phantom_pipe); } } else { resource_log_pipe(dc, opp_heads[slice_idx], stream_idx, slice_idx, plane_idx, - slice_count, true); + slice_count, true, is_phantom_pipe); } } @@ -2420,6 +2479,10 @@ void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state) struct pipe_ctx *otg_master; int stream_idx, phantom_stream_idx; DC_LOGGER_INIT(dc->ctx->logger); + bool is_phantom_pipe = false; + + // Start a new snapshot for this topology update + start_new_topology_snapshot(dc, state); DC_LOG_DC(" pipe topology update"); DC_LOG_DC(" ________________________"); @@ -2433,9 +2496,10 @@ void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state) if (!otg_master) continue; - resource_log_pipe_for_stream(dc, state, otg_master, stream_idx); + resource_log_pipe_for_stream(dc, state, otg_master, stream_idx, is_phantom_pipe); } if (state->phantom_stream_count > 0) { + is_phantom_pipe = true; DC_LOG_DC(" | (phantom pipes) |"); for (stream_idx = 0; stream_idx < state->stream_count; stream_idx++) { if (state->stream_status[stream_idx].mall_stream_config.type != SUBVP_MAIN) @@ -2448,7 +2512,7 @@ void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state) if (!otg_master) continue; - resource_log_pipe_for_stream(dc, state, otg_master, stream_idx); + resource_log_pipe_for_stream(dc, state, otg_master, stream_idx, is_phantom_pipe); } } DC_LOG_DC(" |________________________|\n"); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 4ffc9786117f5..525f0017029ef 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -899,6 +899,7 @@ struct dc_debug_data { uint32_t ltFailCount; uint32_t i2cErrorCount; uint32_t auxErrorCount; + struct pipe_topology_history topology_history; }; struct dc_phy_addr_space_config { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index 5e2813e9ae2fe..2bc86777dfb61 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -80,6 +80,32 @@ #define MAX_HPO_DP2_ENCODERS 4 #define MAX_HPO_DP2_LINK_ENCODERS 4 +/* Pipe topology snapshot structures */ +#define MAX_TOPOLOGY_SNAPSHOTS 4 + +struct pipe_topology_line { + bool is_phantom_pipe; + int plane_idx; + int slice_idx; + int stream_idx; + int dpp_inst; + int opp_inst; + int tg_inst; +}; + +struct pipe_topology_snapshot { + struct pipe_topology_line pipe_log_lines[MAX_PIPES]; + int line_count; + uint64_t timestamp_us; + int stream_count; + int phantom_stream_count; +}; + +struct pipe_topology_history { + struct pipe_topology_snapshot snapshots[MAX_TOPOLOGY_SNAPSHOTS]; + int current_snapshot_index; +}; + struct gamma_curve { uint32_t offset; uint32_t segments_num; From be345d3b9735bbc3a18d3dadfe90aa41005a9790 Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Wed, 5 Nov 2025 15:27:42 -0500 Subject: [PATCH 2585/2653] drm/amd/display: Clear the CUR_ENABLE register on DCN20 on DPP5 [Why] On DCN20 & DCN30, the 6th DPP's & HUBP's are powered on permanently and cannot be power gated. Thus, when dpp_reset() is invoked for the DPP5, while it's still powered on, the cached cursor_state (dpp_base->pos.cur0_ctl.bits.cur0_enable) and the actual state (CUR0_ENABLE) bit are unsycned. This can cause a double cursor in full screen with non-native scaling. [How] Force disable cursor on DPP5 on plane powerdown for ASICs w/ 6 DPPs/HUBPs. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4673 Reviewed-by: Aric Cyr Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 6bd905905984b..1460d3fc7115a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -614,6 +614,14 @@ void dcn20_dpp_pg_control( * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, * 1, 1000); */ + + /* Force disable cursor on plane powerdown on DPP 5 using dpp_force_disable_cursor */ + if (!power_on) { + struct dpp *dpp5 = hws->ctx->dc->res_pool->dpps[dpp_inst]; + if (dpp5 && dpp5->funcs->dpp_force_disable_cursor) + dpp5->funcs->dpp_force_disable_cursor(dpp5); + } + break; default: BREAK_TO_DEBUGGER(); From efc6219477a5dd6c1dff5dcedb2a98f6d5b347c1 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Thu, 6 Nov 2025 18:10:30 -0500 Subject: [PATCH 2586/2653] drm/amd/display: Add null pointer check in link_dpms [why] Check that the stream exists to add link->local_sink null pointer access protection. Reviewed-by: Harold Sun Reviewed-by: Ethan Cheung Signed-off-by: Charlene Liu Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index 8fd41d21a5d1f..256cb143e989c 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -2308,7 +2308,11 @@ static enum dc_status enable_link( { enum dc_status status = DC_ERROR_UNEXPECTED; struct dc_stream_state *stream = pipe_ctx->stream; - struct dc_link *link = stream->link; + struct dc_link *link = NULL; + + if (stream == NULL) + return DC_ERROR_UNEXPECTED; + link = stream->link; /* There's some scenarios where driver is unloaded with display * still enabled. When driver is reloaded, it may cause a display From 479d447a129057c6dd5b44c02f84b5a914053e46 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Mon, 27 Oct 2025 21:40:21 -0400 Subject: [PATCH 2587/2653] drm/amd/display: Check DCCG_AUDIO_DTO2 register mask exist [Why&How] Check DCCG_AUDIO_DTO2 register mask exist before access. Also, add a existing DIO_CLOCK_control register for later use. Reviewed-by: Roman Li Signed-off-by: Charlene Liu Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 3 ++- .../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c index eeed840073fe4..fcad61c618a1a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c @@ -1143,7 +1143,8 @@ void dce_aud_wall_dto_setup( REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); - REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, + if (aud->masks->DCCG_AUDIO_DTO2_USE_512FBR_DTO) + REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1); } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h index 0fc66487d8007..e1fa2e80a15ac 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h @@ -227,7 +227,8 @@ void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context); #define LE_DCN401_REG_LIST_RI(id) \ LE_DCN3_REG_LIST_RI(id), \ SRI_ARR(DP_DPHY_INTERNAL_CTRL, DP, id), \ - SRI_ARR(DIG_BE_CLK_CNTL, DIG, id) + SRI_ARR(DIG_BE_CLK_CNTL, DIG, id),\ + SR_ARR(DIO_CLK_CNTL, id) /* DPP */ #define DPP_REG_LIST_DCN401_COMMON_RI(id) \ From c4fedb381d014fc0c46af6cdec89c307fead81f7 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 7 Nov 2025 16:14:42 -0500 Subject: [PATCH 2588/2653] drm/amd/display: Ignore Coverity false positive [Why&How] Ignore Coverity false positive analysis in the dmub_cmd.h Reviewed-by: Leo Li Signed-off-by: Taimur Hassan Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 815b4ec82c118..173bc2bdf50f1 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -2647,6 +2647,7 @@ struct dmub_cmd_fams2_global_config { union dmub_cmd_fams2_config { struct dmub_cmd_fams2_global_config global; +// coverity[cert_dcl37_c_violation:FALSE] errno.h, stddef.h, stdint.h not included in atombios.h struct dmub_fams2_stream_static_state stream; //v0 union { struct dmub_fams2_cmd_stream_static_base_state base; From 3c1175eac9622e30577086bb703607b3af459819 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 7 Nov 2025 20:15:20 -0500 Subject: [PATCH 2589/2653] drm/amd/display: Promote DC to 3.2.359 This version brings along the following updates: - Add interface to capture expected HW state from SW state - Add panel Replay capability detection, DPCD reading, and enablement logic - Re-check seamless boot enablement on subsequent dc_commit_streams - Improve DPCD link capability retrieval with increased retries and per-retry delays - Add HPD filter for HDMI - Add pipe topology history tracking to DC - Fix MST initialization on resume when switching from SST to MST during suspend - Fix double cursor on DCN20 & DCN30 in non-native scaling - Check DCCG_AUDIO_DTO2 register mask before access - Fix pbn to kbps conversion Reviewed-by: Leo Li Signed-off-by: Taimur Hassan Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 525f0017029ef..25d90f7030d05 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.358" +#define DC_VER "3.2.359" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From b54dd7a71373a5692837375aceedc21c03567caf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 14 Nov 2025 09:26:08 -0500 Subject: [PATCH 2590/2653] drm/amdgpu: Use amdgpu by default on CIK dedicated GPUs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The amdgpu driver has been working well on CIK dGPUs for years. Now that the DC analog connector support landed, amdgpu is at feature parity with the old radeon driver on CIK dGPUs. Enabling the amdgpu driver by default for CIK dGPUs has the following benefits: - More stable OpenGL support through RadeonSI - Vulkan support through RADV - Improved performance - Better display features through DC Users who want to keep using the old driver can do so using: amdgpu.cik_support=0 radeon.cik_support=1 v2: - Update documentation in Kconfig file v3: - Rebase documentation updates (Alex) Reviewed-by: Christian König Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/Kconfig | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig index 40cdfd4f5a7fe..883f324288713 100644 --- a/drivers/gpu/drm/amd/amdgpu/Kconfig +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig @@ -59,10 +59,16 @@ config DRM_AMDGPU_CIK Choose this option if you want to enable support for CIK (Sea Islands) asics. - CIK is already supported in radeon. If you enable this option, - support for CIK will be provided by amdgpu and disabled in - radeon by default. Use module options to override this: + CIK (Sea Islands) are second generation GCN GPUs, + supported by both drivers: radeon (old) and amdgpu (new). + By default, + CIK dedicated GPUs are supported by amdgpu + CIK APUs are supported by radeon + Use module options to override this: + To use amdgpu for CIK, + radeon.cik_support=0 amdgpu.cik_support=1 + To use radeon for CIK, radeon.cik_support=1 amdgpu.cik_support=0 config DRM_AMDGPU_USERPTR From 05d6c03fea61ced55a43859ec03b7a7e4585cd40 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Wed, 19 Nov 2025 10:47:03 +0800 Subject: [PATCH 2591/2653] Bump AMDGPU version to 6.16.13 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index e2eccb6f2b84f..d2a6daea8a5bc 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.16.12) +AC_INIT(amdgpu-dkms, 6.16.13) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From f8be668b6aa2d0368c016dc1fbe935f0241c6669 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Thu, 13 Nov 2025 16:20:27 -0500 Subject: [PATCH 2592/2653] drm/amdkfd: Don't remap PCI P2P range Commit 502360c9a391 ("drm/amdkfd: Fix AIS deinit warnings") removed devm_memunmap_pages from kfd_ais_deinit(). kfd_ais_init() gets called again when compute or memory partitions are changed. Don't remap P2P range again if P2P range has already been initialized. Fixes: 502360c9a391 ("drm/amdkfd: Fix AIS deinit warnings") Signed-off-by: Harish Kasiviswanathan Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdkfd/kfd_ais.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c index 4533393b02249..6ebd0cd026512 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c @@ -123,6 +123,8 @@ int kfd_ais_init(struct amdgpu_device *adev) { #ifdef CONFIG_PCI_P2PDMA int ret; + struct page *p2p_page = NULL; + unsigned long pci_start_pfn = PHYS_PFN(pci_resource_start(adev->pdev, 0)); unsigned long size = ALIGN(adev->gmc.real_vram_size, 2ULL << 20); bool is_large_bar = adev->gmc.visible_vram_size && adev->gmc.real_vram_size == adev->gmc.visible_vram_size; @@ -133,6 +135,13 @@ int kfd_ais_init(struct amdgpu_device *adev) return 0; } + p2p_page = pfn_valid(pci_start_pfn) ? pfn_to_page(pci_start_pfn) : NULL; + if (p2p_page && is_pci_p2pdma_page(p2p_page)) { + adev->kfd.dev->ais_initialized = true; + dev_dbg(adev->dev, "AIS: PCI P2PDMA resource already exists\n"); + return 0; + } + ret = pci_p2pdma_add_resource(adev->pdev, 0 /*bar*/, 0 /*whole VRAM*/, 0 /*offset*/); if (ret) { From 22bd2efb3cacfb747ba2907d8ae96aec48a528af Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 24 Nov 2025 13:25:02 +0800 Subject: [PATCH 2593/2653] drm/amdgpu: add amdgpu_ptl.h for PTL format and command definitions Collect amdgpu_ptl_fmt, psp_ptl_format_type and psp_ptl_perf_req in one header so both GFX and PSP drivers can share them without duplication. Signed-off-by: Perry Yuan Suggested-by: Alex Deucher Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 23 +------ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 1 + drivers/gpu/drm/amd/include/amdgpu_ptl.h | 66 +++++++++++++++++++ .../gpu/drm/amd/include/kgd_kfd_interface.h | 1 + include/uapi/linux/kfd_ioctl.h | 9 --- 6 files changed, 70 insertions(+), 31 deletions(-) create mode 100644 drivers/gpu/drm/amd/include/amdgpu_ptl.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 40c46e6c88988..5b1021c9d0d13 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -37,6 +37,7 @@ #include "amdgpu_sync.h" #include "amdgpu_vm.h" #include "amdgpu_xcp.h" +#include "amdgpu_ptl.h" extern uint64_t amdgpu_amdkfd_total_mem_size; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index eb979108c74d0..76e507a78fbbb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -31,6 +31,7 @@ #include "ta_ras_if.h" #include "ta_rap_if.h" #include "ta_secureDisplay_if.h" +#include "amdgpu_ptl.h" #define PSP_FENCE_BUFFER_SIZE 0x1000 #define PSP_CMD_BUFFER_SIZE 0x1000 @@ -357,28 +358,6 @@ struct spirom_bo { }; #endif -enum psp_ptl_cmd { - PSP_PTL_PERF_MON_QUERY = 0xA0000000, - PSP_PTL_PERF_MON_SET = 0xA0000001, -}; - -enum psp_ptl_format_type -{ - GFX_FTYPE_I8 = 0x00000000, - GFX_FTYPE_F16 = 0x00000001, - GFX_FTYPE_BF16 = 0x00000002, - GFX_FTYPE_F32 = 0x00000003, - GFX_FTYPE_F64 = 0x00000004, - GFX_FTYPE_INVALID = 0xFFFFFFFF, -}; - -struct psp_ptl_perf_req { - enum psp_ptl_cmd req; - uint32_t ptl_state; - uint32_t pref_format1; - uint32_t pref_format2; -}; - struct psp_context { struct amdgpu_device *adev; struct psp_ring km_ring; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 1f31932d1bed8..b50224d529694 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -48,6 +48,7 @@ #include "kfd_smi_events.h" #include "amdgpu_dma_buf.h" #include "kfd_debug.h" +#include "amdgpu_ptl.h" static long kfd_ioctl(struct file *, unsigned int, unsigned long); static int kfd_open(struct inode *, struct file *); diff --git a/drivers/gpu/drm/amd/include/amdgpu_ptl.h b/drivers/gpu/drm/amd/include/amdgpu_ptl.h new file mode 100644 index 0000000000000..9216ed4f230ae --- /dev/null +++ b/drivers/gpu/drm/amd/include/amdgpu_ptl.h @@ -0,0 +1,66 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __AMDGPU_PTL_H__ +#define __AMDGPU_PTL_H__ + +enum amdgpu_ptl_fmt { + AMDGPU_PTL_FMT_I8 = 0, + AMDGPU_PTL_FMT_F16 = 1, + AMDGPU_PTL_FMT_BF16 = 2, + AMDGPU_PTL_FMT_F32 = 3, + AMDGPU_PTL_FMT_F64 = 4, + AMDGPU_PTL_FMT_INVALID = 5, +}; + +static const char * const amdgpu_ptl_fmt_str[] = { + [AMDGPU_PTL_FMT_I8] = "I8", + [AMDGPU_PTL_FMT_F16] = "F16", + [AMDGPU_PTL_FMT_BF16] = "BF16", + [AMDGPU_PTL_FMT_F32] = "F32", + [AMDGPU_PTL_FMT_F64] = "F64", + [AMDGPU_PTL_FMT_INVALID] = "INVALID", +}; + +enum psp_ptl_cmd { + PSP_PTL_PERF_MON_QUERY = 0xA0000000, + PSP_PTL_PERF_MON_SET = 0xA0000001, +}; + +enum psp_ptl_format_type +{ + GFX_FTYPE_I8 = 0x00000000, + GFX_FTYPE_F16 = 0x00000001, + GFX_FTYPE_BF16 = 0x00000002, + GFX_FTYPE_F32 = 0x00000003, + GFX_FTYPE_F64 = 0x00000004, + GFX_FTYPE_INVALID = 0xFFFFFFFF, +}; + +struct psp_ptl_perf_req { + enum psp_ptl_cmd req; + uint32_t ptl_state; + uint32_t pref_format1; + uint32_t pref_format2; +}; + +#endif /* __AMDGPU_PTL_H__ */ diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index e1c25444a0fab..d34c869b182ff 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -35,6 +35,7 @@ #include "amdgpu_irq.h" #include "amdgpu_gfx.h" +#include "amdgpu_ptl.h" struct pci_dev; struct amdgpu_device; diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 58cb6b04f10fd..dbe848a1490b1 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1700,15 +1700,6 @@ enum kfd_ioctl_pc_sample_op { KFD_IOCTL_PCS_OP_STOP, }; -enum amdgpu_ptl_fmt { - AMDGPU_PTL_FMT_I8 = 0, - AMDGPU_PTL_FMT_F16 = 1, - AMDGPU_PTL_FMT_BF16 = 2, - AMDGPU_PTL_FMT_F32 = 3, - AMDGPU_PTL_FMT_F64 = 4, - AMDGPU_PTL_FMT_INVALID = 5, -}; - /* Values have to be a power of 2*/ #define KFD_IOCTL_PCS_FLAG_POWER_OF_2 0x00000001 From 3324dd526ca0fbca3532f890f8b83de088e90a2b Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Fri, 21 Nov 2025 00:00:09 +0800 Subject: [PATCH 2594/2653] Documentation/amdgpu: Add documentation for Peak Tops Limiter (PTL) sysfs interface The PTL (Peak Tops Limiter) feature exposes per-GPU sysfs files under /sys/class/drm/cardX/device/ptl/ to allow users to enable or disable PTL, configure preferred data formats, and query supported formats. The usage of these sysfs files is not always obvious, so add documentation to describe their purpose and provide concrete usage examples. V3 changes: * format show will display preferred formats instead of N/A (Alex) Signed-off-by: Perry Yuan Suggested-by: Alex Deucher Reviewed-by: Yifan Zhang --- Documentation/gpu/amdgpu/index.rst | 1 + Documentation/gpu/amdgpu/ptl.rst | 94 ++++++++++++++++++++++++++++++ 2 files changed, 95 insertions(+) create mode 100644 Documentation/gpu/amdgpu/ptl.rst diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst index 45523e9860fc5..10945c6263388 100644 --- a/Documentation/gpu/amdgpu/index.rst +++ b/Documentation/gpu/amdgpu/index.rst @@ -22,3 +22,4 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures. debugfs process-isolation amdgpu-glossary + ptl diff --git a/Documentation/gpu/amdgpu/ptl.rst b/Documentation/gpu/amdgpu/ptl.rst new file mode 100644 index 0000000000000..c7f16dea79546 --- /dev/null +++ b/Documentation/gpu/amdgpu/ptl.rst @@ -0,0 +1,94 @@ +======================================= +Peak Tops Limiter (PTL) sysfs Interface +======================================= + +Overview +-------- +The Peak Tops Limiter (PTL) sysfs interface enables users to control and +configure the PTL feature for each GPU individually. All PTL-related +sysfs files are located under `/sys/class/drm/cardX/device/ptl/`, where +`X` is the GPU index. Through these files, users can enable or disable +PTL, set preferred data formats, and query supported formats for each GPU. + +PTL sysfs files +---------------- +The following files are available under `/sys/class/drm/cardX/device/ptl/`: + +- `ptl_enable` +- `ptl_format` +- `ptl_supported_formats` + +PTL Enable/Disable +------------------ +File: `ptl_enable` +Type: Read/Write (rw) + +Read: Returns the current PTL status as a string: `enabled` if PTL +is active, or `disabled` if inactive. + +Write: + +- Write `1` or `enabled` to enable PTL +- Write `0` or `disabled` to disable PTL + +Examples:: + + # Query PTL status + cat /sys/class/drm/card1/device/ptl/ptl_enable + # Output: enabled + + # Enable PTL + sudo bash -c "echo 1 > /sys/class/drm/card1/device/ptl/ptl_enable" + + # Disable PTL + sudo bash -c "echo 0 > /sys/class/drm/card1/device/ptl/ptl_enable" + +PTL Format (Preferred Data Formats) +----------------------------------- +File: `ptl_format` +Type: Read/Write (rw) + +Read: Returns the two preferred formats, e.g. `I8,F32`. + +Write: Accepts two formats separated by a comma, e.g. `I8,F32`. + +- Both formats must be supported and different. +- If an invalid format is provided (not supported, or both formats are the + same), the driver will return "write error: Invalid argument". + +Examples:: + + # Query PTL formats + cat /sys/class/drm/card1/device/ptl/ptl_format + # Output: I8,F32 + + # Set PTL formats + sudo bash -c "echo I8,F32 > /sys/class/drm/card1/device/ptl/ptl_format" + +Supported Formats +----------------- +File: `ptl_supported_formats` +Type: Read-only (r) + +Read: Returns a comma-separated list of supported formats, e.g. +`I8,F16,BF16,F32,F64`. + +Example:: + + # Check supported formats + cat /sys/class/drm/card1/device/ptl/ptl_supported_formats + # Output: I8,F16,BF16,F32,F64 + +Behavioral Notes +---------------- +- PTL formats can only be set when PTL is enabled. +- If PTL is disabled, `ptl_format` returns `N/A`. +- Only two formats can be set at a time, and they must be from the supported set and different.. +- All commands support per-GPU targeting. +- Root permission is required to enable/disable PTL or change formats. +- If the hardware does not support PTL, the PTL sysfs directory will not + be created. + +Implementation +-------------- +The PTL sysfs nodes are implemented in `drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c`. From 586918a0aaa437c58ecad225ef4ab3c4b5b13ed1 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 17 Nov 2025 14:29:30 +0800 Subject: [PATCH 2595/2653] drm/amdgpu: add sysfs for Peak Tops Limiter (PTL) Add per-GPU sysfs files under /sys/class/drm/cardX/device/ptl to control the Peak Tops Limiter (PTL) feature. Exposes ptl_enable (enable/disable PTL), ptl_format (set/query preferred formats), and ptl_supported_formats (list supported formats) Example usage ------------- Query PTL status: `cat /sys/class/drm/card1/device/ptl/ptl_enable` Enable PTL: `sudo bash -c "echo 1 > /sys/class/drm/card1/device/ptl/ptl_enable"` Disable PTL: `sudo bash -c "echo 0 > /sys/class/drm/card1/device/ptl/ptl_enable"` Set PTL preferred formats: `sudo bash -c "echo I8,F32 > /sys/class/drm/card1/device/ptl/ptl_format"` Query supported formats: `cat /sys/class/drm/card1/device/ptl/ptl_supported_formats` v3 changes: * move N/A to previous format in format show(Alex) * fix format check for format store(Alex) * drop the ptl declarations into amdgpu_ptl.h(Alex) v2 changes: * add usage commands in commit info (Alex) * move amdgpu_ptl_fmt into kgd_kfd_interface.h (Alex) Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 159 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 + 3 files changed, 161 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 20f014166f1ea..1ac5de8e14829 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3279,6 +3279,7 @@ static const struct attribute_group *amdgpu_sysfs_groups[] = { &amdgpu_vram_mgr_attr_group, &amdgpu_gtt_mgr_attr_group, &amdgpu_flash_attr_group, + &amdgpu_ptl_attr_group, NULL, }; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 4ec1949584e26..02af6046bce57 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1280,6 +1280,140 @@ int psp_performance_monitor_hw(struct psp_context *psp, u32 req_code, return ret; } +static enum amdgpu_ptl_fmt str_to_ptl_fmt(const char *str) +{ + int i; + + for (i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { + if (!strcmp(str, amdgpu_ptl_fmt_str[i])) + return (enum amdgpu_ptl_fmt)i; + } + + return AMDGPU_PTL_FMT_INVALID; +} + +static ssize_t ptl_supported_formats_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + ssize_t len = 0; + + for (int i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { + len += sysfs_emit_at(buf, len, "%s%s", + amdgpu_ptl_fmt_str[i], + (i < AMDGPU_PTL_FMT_INVALID - 1) ? "," : "\n"); + } + + return len; +} + +static ssize_t ptl_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + struct psp_context *psp = &adev->psp; + bool enable, cur_enabled; + uint32_t ptl_state, fmt1, fmt2; + int ret; + + if (sysfs_streq(buf, "enabled") || sysfs_streq(buf, "1")) + enable = true; + else if (sysfs_streq(buf, "disabled") || sysfs_streq(buf, "0")) + enable = false; + else + return -EINVAL; + + fmt1 = psp->ptl_fmt1; + fmt2 = psp->ptl_fmt2; + ptl_state = enable ? 1 : 0; + + cur_enabled = READ_ONCE(psp->ptl_enabled); + if (cur_enabled == enable) + return count; + + ret = psp_performance_monitor_hw(psp, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); + if (ret) { + dev_err(adev->dev, "Failed to set PTL err = %d\n", ret); + return ret; + } + + return count; +} + +static ssize_t ptl_enable_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + struct psp_context *psp = &adev->psp; + + return sysfs_emit(buf, "%s\n", psp->ptl_enabled ? "enabled" : "disabled"); +} + +static ssize_t ptl_format_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + struct psp_context *psp = &adev->psp; + char fmt1_str[8], fmt2_str[8]; + enum amdgpu_ptl_fmt fmt1_enum, fmt2_enum; + uint32_t ptl_state, fmt1, fmt2; + int ret; + + /* Only allow format update when PTL is enabled */ + if (!psp->ptl_enabled) + return -EPERM; + + /* Parse input, expecting "FMT1,FMT2" */ + if (sscanf(buf, "%7[^,],%7s", fmt1_str, fmt2_str) != 2) + return -EINVAL; + + fmt1_enum = str_to_ptl_fmt(fmt1_str); + fmt2_enum = str_to_ptl_fmt(fmt2_str); + + if (fmt1_enum >= AMDGPU_PTL_FMT_INVALID || + fmt2_enum >= AMDGPU_PTL_FMT_INVALID || + fmt1_enum == fmt2_enum) + return -EINVAL; + + ptl_state = psp->ptl_enabled; + fmt1 = fmt1_enum; + fmt2 = fmt2_enum; + ret = psp_performance_monitor_hw(psp, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); + if (ret) { + dev_err(adev->dev, "Failed to update PTL err = %d\n", ret); + return ret; + } + + return count; +} + +static ssize_t ptl_format_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + struct psp_context *psp = &adev->psp; + + return sysfs_emit(buf, "%s,%s\n", + amdgpu_ptl_fmt_str[psp->ptl_fmt1], + amdgpu_ptl_fmt_str[psp->ptl_fmt2]); +} + +static umode_t amdgpu_ptl_is_visible(struct kobject *kobj, struct attribute *attr, int idx) +{ + struct device *dev = kobj_to_dev(kobj); + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + + /* Only show PTL sysfs files if PTL hardware is supported */ + if (!adev->psp.ptl_hw_supported) + return 0; + + return attr->mode; +} + int psp_spatial_partition(struct psp_context *psp, int mode) { struct psp_gfx_cmd_resp *cmd; @@ -4260,6 +4394,31 @@ void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size static DEVICE_ATTR(usbc_pd_fw, 0644, psp_usbc_pd_fw_sysfs_read, psp_usbc_pd_fw_sysfs_write); +/** + * DOC: PTL sysfs attributes + * These sysfs files under /sys/class/drm/cardX/device/ptl allow users to enable or disable + * the Peak Tops Limiter (PTL), configure preferred PTL data formats, and query supported + * formats for each GPU. + */ +static DEVICE_ATTR(ptl_enable, 0644, + ptl_enable_show, ptl_enable_store); +static DEVICE_ATTR(ptl_format, 0644, + ptl_format_show, ptl_format_store); +static DEVICE_ATTR(ptl_supported_formats, 0444, + ptl_supported_formats_show, NULL); + +static struct attribute *ptl_attrs[] = { + &dev_attr_ptl_enable.attr, + &dev_attr_ptl_format.attr, + &dev_attr_ptl_supported_formats.attr, + NULL, +}; + +const struct attribute_group amdgpu_ptl_attr_group = { + .name = "ptl", + .attrs = ptl_attrs, + .is_visible = amdgpu_ptl_is_visible, +}; int is_psp_fw_valid(struct psp_bin_desc bin) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 76e507a78fbbb..fb19308492121 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -64,6 +64,7 @@ #define MBOX_TOS_RESP_MASK (GFX_CMD_RESPONSE_MASK | GFX_CMD_STATUS_MASK) extern const struct attribute_group amdgpu_flash_attr_group; +extern const struct attribute_group amdgpu_ptl_attr_group; enum psp_shared_mem_size { PSP_ASD_SHARED_MEM_SIZE = 0x0, From 6cdcf578672528d75abebd3edf80aa41f4518753 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 25 Nov 2025 13:48:31 +0800 Subject: [PATCH 2596/2653] drm/amdgpu: fix intree build error for amdgpu_ptl_fmt_str move amdgpu_ptl_fmt_str to amdgpu_psp.c file to fix compiler complaining with gcc -Werror, the error will happen on the intree build. Signed-off-by: Perry Yuan Reported-by: Chengjun Yao Reviewed-by: Chengjun Yao --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 9 +++++++++ drivers/gpu/drm/amd/include/amdgpu_ptl.h | 9 --------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 02af6046bce57..70f81040c9cdb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -50,6 +50,15 @@ static int psp_load_smu_fw(struct psp_context *psp); static int psp_rap_terminate(struct psp_context *psp); static int psp_securedisplay_terminate(struct psp_context *psp); +static const char * const amdgpu_ptl_fmt_str[] = { + [AMDGPU_PTL_FMT_I8] = "I8", + [AMDGPU_PTL_FMT_F16] = "F16", + [AMDGPU_PTL_FMT_BF16] = "BF16", + [AMDGPU_PTL_FMT_F32] = "F32", + [AMDGPU_PTL_FMT_F64] = "F64", + [AMDGPU_PTL_FMT_INVALID] = "INVALID", +}; + static int psp_ring_init(struct psp_context *psp, enum psp_ring_type ring_type) { diff --git a/drivers/gpu/drm/amd/include/amdgpu_ptl.h b/drivers/gpu/drm/amd/include/amdgpu_ptl.h index 9216ed4f230ae..529b93082c86e 100644 --- a/drivers/gpu/drm/amd/include/amdgpu_ptl.h +++ b/drivers/gpu/drm/amd/include/amdgpu_ptl.h @@ -32,15 +32,6 @@ enum amdgpu_ptl_fmt { AMDGPU_PTL_FMT_INVALID = 5, }; -static const char * const amdgpu_ptl_fmt_str[] = { - [AMDGPU_PTL_FMT_I8] = "I8", - [AMDGPU_PTL_FMT_F16] = "F16", - [AMDGPU_PTL_FMT_BF16] = "BF16", - [AMDGPU_PTL_FMT_F32] = "F32", - [AMDGPU_PTL_FMT_F64] = "F64", - [AMDGPU_PTL_FMT_INVALID] = "INVALID", -}; - enum psp_ptl_cmd { PSP_PTL_PERF_MON_QUERY = 0xA0000000, PSP_PTL_PERF_MON_SET = 0xA0000001, From 166d267e6f478d5b6e677e8967eee6cb7f9f7a80 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 2 Dec 2025 16:09:40 +0800 Subject: [PATCH 2597/2653] drm/amdgpu: add firmware version check for PTL support PTL (Peak TOPS Limiter) functionality is only available starting from firmware 0x0036081a. Add the same firmware version gate in both places that already verify PTL hardware capability: v2 change: * move psp and gc version check into psp_performance_monitor_hw() Signed-off-by: Perry Yuan Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 3 --- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 70f81040c9cdb..b8e84d17a1506 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1255,6 +1255,10 @@ int psp_performance_monitor_hw(struct psp_context *psp, u32 req_code, if (amdgpu_sriov_vf(psp->adev)) return 0; + if (amdgpu_ip_version(psp->adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) || + psp->sos.fw_version < 0x0036081a) + return -EOPNOTSUPP; + if (psp_ptl_fmt_verify(psp, *fmt1, &ptl_fmt1) || psp_ptl_fmt_verify(psp, *fmt2, &ptl_fmt2)) return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index a81400fdb674c..89163b19808da 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2399,9 +2399,6 @@ static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool sta uint32_t ptl_state = state ? 1 : 0; int r; - if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) - return -ENOTSUPP; - if (!adev->psp.funcs) return -EOPNOTSUPP; From 03168c7b942c563cf6edcd355c4e87d44edb3da3 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Thu, 4 Dec 2025 16:21:10 +0800 Subject: [PATCH 2598/2653] drm/amdgpu: add PTL sysfs interface for old kernels some old kernels do not export pci_driver.dev_groups, so the "ptl" sub-directory is not create whle HAVE_PCI_DRIVER_DEV_GROUPS is set as false by kcl. Move the sysfs creation path into amdgpu_device_sys_interface_init() / amdgpu_device_sys_interface_fini() so that both new and old kernels use the same amdgpu_ptl_attr_group definition while keeping the implementation in one place. Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 16 ++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 - drivers/gpu/drm/amd/include/amdgpu_ptl.h | 4 ++++ 5 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index b94bfbbf621b2..7cac943c641f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4505,6 +4505,7 @@ static int amdgpu_device_sys_interface_init(struct amdgpu_device *adev) amdgpu_fru_sysfs_init(adev); amdgpu_reg_state_sysfs_init(adev); amdgpu_xcp_sysfs_init(adev); + amdgpu_ptl_sysfs_init(adev); return r; } @@ -4520,6 +4521,7 @@ static void amdgpu_device_sys_interface_fini(struct amdgpu_device *adev) amdgpu_reg_state_sysfs_fini(adev); amdgpu_xcp_sysfs_fini(adev); + amdgpu_ptl_sysfs_fini(adev); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 1ac5de8e14829..20f014166f1ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3279,7 +3279,6 @@ static const struct attribute_group *amdgpu_sysfs_groups[] = { &amdgpu_vram_mgr_attr_group, &amdgpu_gtt_mgr_attr_group, &amdgpu_flash_attr_group, - &amdgpu_ptl_attr_group, NULL, }; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index b8e84d17a1506..3ef5ee858e06f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1427,6 +1427,22 @@ static umode_t amdgpu_ptl_is_visible(struct kobject *kobj, struct attribute *att return attr->mode; } +int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev) +{ + if (!adev->psp.ptl_hw_supported) + return 0; + + return sysfs_create_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); +} + +void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev) +{ + if (!adev->psp.ptl_hw_supported) + return; + + sysfs_remove_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); +} + int psp_spatial_partition(struct psp_context *psp, int mode) { struct psp_gfx_cmd_resp *cmd; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index fb19308492121..76e507a78fbbb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -64,7 +64,6 @@ #define MBOX_TOS_RESP_MASK (GFX_CMD_RESPONSE_MASK | GFX_CMD_STATUS_MASK) extern const struct attribute_group amdgpu_flash_attr_group; -extern const struct attribute_group amdgpu_ptl_attr_group; enum psp_shared_mem_size { PSP_ASD_SHARED_MEM_SIZE = 0x0, diff --git a/drivers/gpu/drm/amd/include/amdgpu_ptl.h b/drivers/gpu/drm/amd/include/amdgpu_ptl.h index 529b93082c86e..1a5c6fd6b74dd 100644 --- a/drivers/gpu/drm/amd/include/amdgpu_ptl.h +++ b/drivers/gpu/drm/amd/include/amdgpu_ptl.h @@ -54,4 +54,8 @@ struct psp_ptl_perf_req { uint32_t pref_format2; }; +extern const struct attribute_group amdgpu_ptl_attr_group; +int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev); +void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev); + #endif /* __AMDGPU_PTL_H__ */ From 2fe99f61fb34d9f23e13b2166347d3409d62329a Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 19 Nov 2025 20:19:22 +0530 Subject: [PATCH 2599/2653] drm/amdkfd: Disable AIS on virtualized environment AIS is not supported on virtualization yet. Change-Id: Ifa5b9b4a4914f85592870076645f8c2397b8fd9e Signed-off-by: Lijo Lazar Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdkfd/kfd_ais.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c index 6ebd0cd026512..9e59c32f9516f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c @@ -129,6 +129,11 @@ int kfd_ais_init(struct amdgpu_device *adev) bool is_large_bar = adev->gmc.visible_vram_size && adev->gmc.real_vram_size == adev->gmc.visible_vram_size; + if (amdgpu_sriov_vf(adev)) { + dev_dbg(adev->dev, "AIS: not supported on SRIOV\n"); + return 0; + } + /* AIS support limited to large BAR dGPUs */ if (adev->flags & AMD_IS_APU || adev->gmc.xgmi.connected_to_cpu || !is_large_bar) { dev_dbg(adev->dev, "AIS: only supported for large BAR dGPU\n"); From 204f2dea4592ded16dcb1a6aa34c64e7660640e8 Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Wed, 19 Nov 2025 15:21:43 +0800 Subject: [PATCH 2600/2653] drm/amdgpu: fix the calculation of RAS bad page number __amdgpu_ras_restore_bad_pages is responsible for the maintenance of bad page number, drop the unnecessary bad page number update in the error handling path of add_bad_pages. Change-Id: I9d81a40b8cc8f9b050613475e3b3686773961f66 Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang (cherry picked from commit 4328fe9d5aa752f8348ca6a8a67a9650256f689a) --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 506cc4936d95f..3db54088596f4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3261,8 +3261,6 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, /* deal with retire_unit records a time */ ret = __amdgpu_ras_convert_rec_array_from_rom(adev, &bps[i], &err_data, nps); - if (ret) - con->bad_page_num -= adev->umc.retire_unit; i += (adev->umc.retire_unit - 1); } else { break; @@ -3275,8 +3273,6 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, for (; i < pages; i++) { ret = __amdgpu_ras_convert_rec_from_rom(adev, &bps[i], &err_data, nps); - if (ret) - con->bad_page_num -= adev->umc.retire_unit; } con->eh_data->count_saved = con->eh_data->count; From f2a8a3709ebb24b2dfa194cd7f7eceaad7899d08 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Fri, 21 Nov 2025 00:46:23 +0800 Subject: [PATCH 2601/2653] drm/amdgpu/ras: Move ras data alloc before bad page check In the rare event if eeprom has only invalid address entries, allocation is skipped, this causes following NULL pointer issue [ 547.103445] BUG: kernel NULL pointer dereference, address: 0000000000000010 [ 547.118897] #PF: supervisor read access in kernel mode [ 547.130292] #PF: error_code(0x0000) - not-present page [ 547.141689] PGD 124757067 P4D 0 [ 547.148842] Oops: 0000 [#1] PREEMPT SMP NOPTI [ 547.158504] CPU: 49 PID: 8167 Comm: cat Tainted: G OE 6.8.0-38-generic #38-Ubuntu [ 547.177998] Hardware name: Supermicro AS -8126GS-TNMR/H14DSG-OD, BIOS 1.7 09/12/2025 [ 547.195178] RIP: 0010:amdgpu_ras_sysfs_badpages_read+0x2f2/0x5d0 [amdgpu] [ 547.210375] Code: e8 63 78 82 c0 45 31 d2 45 3b 75 08 48 8b 45 a0 73 44 44 89 f1 48 8b 7d 88 48 89 ca 48 c1 e2 05 48 29 ca 49 8b 4d 00 48 01 d1 <48> 83 79 10 00 74 17 49 63 f2 48 8b 49 08 41 83 c2 01 48 8d 34 76 [ 547.252045] RSP: 0018:ffa0000067287ac0 EFLAGS: 00010246 [ 547.263636] RAX: ff11000167c28130 RBX: ff11000127600000 RCX: 0000000000000000 [ 547.279467] RDX: 0000000000000000 RSI: 0000000000000000 RDI: ff11000125b1c800 [ 547.295298] RBP: ffa0000067287b50 R08: 0000000000000000 R09: 0000000000000000 [ 547.311129] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000 [ 547.326959] R13: ff11000217b1de00 R14: 0000000000000000 R15: 0000000000000092 [ 547.342790] FS: 0000746e59d14740(0000) GS:ff11017dfda80000(0000) knlGS:0000000000000000 [ 547.360744] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 547.373489] CR2: 0000000000000010 CR3: 000000019585e001 CR4: 0000000000f71ef0 [ 547.389321] PKRU: 55555554 [ 547.395316] Call Trace: [ 547.400737] [ 547.405386] ? show_regs+0x6d/0x80 [ 547.412929] ? __die+0x24/0x80 [ 547.419697] ? page_fault_oops+0x99/0x1b0 [ 547.428588] ? do_user_addr_fault+0x2ee/0x6b0 [ 547.438249] ? exc_page_fault+0x83/0x1b0 [ 547.446949] ? asm_exc_page_fault+0x27/0x30 [ 547.456225] ? amdgpu_ras_sysfs_badpages_read+0x2f2/0x5d0 [amdgpu] [ 547.470040] ? mas_wr_modify+0xcd/0x140 [ 547.478548] sysfs_kf_bin_read+0x63/0xb0 [ 547.487248] kernfs_file_read_iter+0xa1/0x190 [ 547.496909] kernfs_fop_read_iter+0x25/0x40 [ 547.506182] vfs_read+0x255/0x390 This also result in space left assigned to negative values. Moving data alloc call before bad page check resolves both the issue. Change-Id: I42f518e2ed046ed501cdead368e7ea5dd85854b7 Signed-off-by: Asad Kamal Suggested-by: Lijo Lazar Reviewed-by: Hawking Zhang Reviewed-by: Lijo Lazar (cherry picked from commit 8bb1c7368f6deeb9223c3598585514f93f65866b) --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 3db54088596f4..2b2c24269b386 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3088,6 +3088,11 @@ static int __amdgpu_ras_restore_bad_pages(struct amdgpu_device *adev, struct ras_err_handler_data *data = con->eh_data; for (j = 0; j < count; j++) { + if (!data->space_left && + amdgpu_ras_realloc_eh_data_space(adev, data, 256)) { + return -ENOMEM; + } + if (amdgpu_ras_check_bad_page_unlock(con, bps[j].retired_page << AMDGPU_GPU_PAGE_SHIFT)) { data->count++; @@ -3095,11 +3100,6 @@ static int __amdgpu_ras_restore_bad_pages(struct amdgpu_device *adev, continue; } - if (!data->space_left && - amdgpu_ras_realloc_eh_data_space(adev, data, 256)) { - return -ENOMEM; - } - amdgpu_ras_reserve_page(adev, bps[j].retired_page); memcpy(&data->bps[data->count], &(bps[j]), From 9dbadd8866110a9c4249b7037f712cff87840c49 Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Mon, 22 Dec 2025 16:48:22 +0800 Subject: [PATCH 2602/2653] drm/amdgpu: only check critical address when it is not reserved when an address is reserved already, no need to check if it is in critical or not, to save time Signed-off-by: Gangliang Xie Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 2b2c24269b386..5c137a28f9ac8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1919,8 +1919,6 @@ static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, for (i = 0; i < bps_count; i++) { address = ((uint64_t)bps[i].bp) << AMDGPU_GPU_PAGE_SHIFT; - if (amdgpu_ras_check_critical_address(adev, address)) - continue; bps[i].size = AMDGPU_GPU_PAGE_SIZE; @@ -1933,6 +1931,10 @@ static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, else bps[i].flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED; + if ((bps[i].flags != AMDGPU_RAS_RETIRE_PAGE_RESERVED) && + amdgpu_ras_check_critical_address(adev, address)) + bps[i].flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED; + s += scnprintf(&buf[s], element_size + 1, "0x%08x : 0x%08x : %1s\n", bps[i].bp, From 9b87c667ace8627c92229fb063603665b6e3bf0a Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 5 Jan 2026 15:22:52 +0800 Subject: [PATCH 2603/2653] drm/amdkfd: Add PTL control IOCTL Option and unify refcount logic Introduce a new IOCTL option to allow userspace explicit control over the Peak Tops Limiter (PTL) state for profiling Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 + drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 + drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 89 +++++++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 6 ++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 5 +- include/uapi/linux/kfd_ioctl.h | 7 ++ 6 files changed, 108 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 76e507a78fbbb..4b2e82628d812 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -452,6 +452,8 @@ struct psp_context { enum amdgpu_ptl_fmt ptl_fmt2; bool ptl_enabled; bool ptl_hw_supported; + /* PTL disable reference counting */ + atomic_t ptl_disable_ref; }; struct amdgpu_psp_funcs { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 89163b19808da..9436bf42d5fd0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2418,6 +2418,8 @@ static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool sta adev->psp.ptl_hw_supported = true; + atomic_set(&adev->psp.ptl_disable_ref, 0); + return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index b50224d529694..9e9cdcf8b6359 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1910,6 +1910,88 @@ int kfd_ptl_control(struct kfd_process_device *pdd, bool enable) return ret; } +int kfd_ptl_disable_request(struct kfd_process_device *pdd, + struct kfd_process *p) +{ + struct amdgpu_device *adev; + int ret = 0; + + if (!pdd) + return -ENODEV; + + adev = pdd->dev->adev; + mutex_lock(&p->mutex); + + if (pdd->ptl_disable_req) + goto out; + + if (atomic_inc_return(&adev->psp.ptl_disable_ref) == 1) { + ret = kfd_ptl_control(pdd, false); + if (ret) { + atomic_dec(&adev->psp.ptl_disable_ref); + dev_warn(pdd->dev->adev->dev, + "failed to disable PTL\n"); + goto out; + } + } + pdd->ptl_disable_req = true; + +out: + mutex_unlock(&p->mutex); + return ret; +} + +int kfd_ptl_disable_release(struct kfd_process_device *pdd, + struct kfd_process *p) +{ + struct amdgpu_device *adev; + int ret = 0; + + if (!pdd) + return -ENODEV; + + adev = pdd->dev->adev; + mutex_lock(&p->mutex); + if (!pdd->ptl_disable_req) + goto out; + + if (atomic_dec_return(&adev->psp.ptl_disable_ref) == 0) { + ret = kfd_ptl_control(pdd, true); + if (ret) { + atomic_inc(&adev->psp.ptl_disable_ref); + dev_warn(pdd->dev->adev->dev, + "failed to enable PTL\n"); + goto out; + } + } + pdd->ptl_disable_req = false; + +out: + mutex_unlock(&p->mutex); + return ret; +} + +static int kfd_profiler_ptl_control(struct kfd_process *p, + struct kfd_ioctl_ptl_control *args) +{ + struct kfd_process_device *pdd; + int ret; + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + mutex_unlock(&p->mutex); + + if (!pdd) + return -ENODEV; + + if (args->enable == 0) + ret = kfd_ptl_disable_request(pdd, p); + else + ret = kfd_ptl_disable_release(pdd, p); + + return ret; +} + static int criu_checkpoint_process(struct kfd_process *p, uint8_t __user *user_priv_data, uint64_t *priv_offset) @@ -3418,7 +3500,7 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, if (!kfd->profiler_process) { kfd->profiler_process = p; status = 0; - kfd_ptl_control(pdd, false); + kfd_ptl_disable_request(pdd, p); } else if (kfd->profiler_process == p) { status = -EALREADY; } else { @@ -3427,7 +3509,8 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, } else if (op == 0 && kfd->profiler_process == p) { kfd->profiler_process = NULL; status = 0; - kfd_ptl_control(pdd, true); + kfd_ptl_disable_release(pdd, p); + } mutex_unlock(&kfd->profiler_lock); @@ -3472,6 +3555,8 @@ static int kfd_ioctl_profiler(struct file *filep, struct kfd_process *p, void *d return kfd_ioctl_pc_sample(filep, p, &args->pc_sample); case KFD_IOC_PROFILER_PMC: return kfd_profiler_pmc(p, &args->pmc); + case KFD_IOC_PROFILER_PTL_CONTROL: + return kfd_profiler_ptl_control(p, &args->ptl); } return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 36b4b9afe6a53..f5ec2c1c9266b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -975,6 +975,8 @@ struct kfd_process_device { bool has_reset_queue; u32 pasid; + /* Indicates this process has requested PTL stay disabled */ + bool ptl_disable_req; }; #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd) @@ -1750,6 +1752,10 @@ int kfd_ais_rw_file(struct amdgpu_device *adev, struct amdgpu_bo *bo, struct kfd_ais_in_args *in, uint64_t *size_copied); /* PTL support */ int kfd_ptl_control(struct kfd_process_device *pdd, bool enable); +int kfd_ptl_disable_request(struct kfd_process_device *pdd, + struct kfd_process *p); +int kfd_ptl_disable_release(struct kfd_process_device *pdd, + struct kfd_process *p); /* Debugfs */ #if defined(CONFIG_DEBUG_FS) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 5b87e0999a447..359064f8e7736 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1042,7 +1042,6 @@ static void kfd_process_profiler_release(struct kfd_process *p, struct kfd_proce mutex_lock(&pdd->dev->kfd->profiler_lock); if (pdd->dev->kfd->profiler_process == p) { pdd->qpd.dqm->ops.set_perfcount(pdd->qpd.dqm, 0); - kfd_ptl_control(pdd, true); pdd->dev->kfd->profiler_process = NULL; } mutex_unlock(&pdd->dev->kfd->profiler_lock); @@ -1061,6 +1060,10 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) pdd->dev->id, p->lead_thread->pid); kfd_process_profiler_release(p, pdd); + + if (pdd->ptl_disable_req) + kfd_ptl_disable_release(pdd, p); + kfd_pc_sample_release(pdd); kfd_spm_release_process_device(pdd); diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index dbe848a1490b1..1036653dea528 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1744,6 +1744,7 @@ enum kfd_profiler_ops { KFD_IOC_PROFILER_PMC = 0, KFD_IOC_PROFILER_PC_SAMPLE = 1, KFD_IOC_PROFILER_VERSION = 2, + KFD_IOC_PROFILER_PTL_CONTROL = 3, }; /** @@ -1755,11 +1756,17 @@ struct kfd_ioctl_pmc_settings { __u32 perfcount_enable; /* Force Perfcount Enable for queues on GPU */ }; +struct kfd_ioctl_ptl_control { + __u32 gpu_id; /* user_gpu_id */ + __u32 enable; /* set 1 to enable PTL, set 0 to disable PTL */ +}; + struct kfd_ioctl_profiler_args { __u32 op; /* kfd_profiler_op */ union { struct kfd_ioctl_pc_sample_args pc_sample; struct kfd_ioctl_pmc_settings pmc; + struct kfd_ioctl_ptl_control ptl; __u32 version; /* KFD_IOC_PROFILER_VERSION_NUM */ }; }; From cbcb39b3a621227101ee76cf8bbb87cb4babf507 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Wed, 7 Jan 2026 15:16:52 +0800 Subject: [PATCH 2604/2653] drm/amdkfd: suspend scheduler during PTL re-enabling Stop the scheduler before releasing the PTL disable request to ensure the GPU is quiescent during the PTL state transition. This prevents potential queue preemption failures and GPU resets caused by modifying PTL state while waves are executing v1->v2: only stop/start the scheduler when the PTL state actually needs to transition(Yifan) Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 9e9cdcf8b6359..dad7d628da0f4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1956,7 +1956,11 @@ int kfd_ptl_disable_release(struct kfd_process_device *pdd, goto out; if (atomic_dec_return(&adev->psp.ptl_disable_ref) == 0) { + if (adev->kfd.init_complete) + amdgpu_amdkfd_stop_sched(adev, pdd->dev->node_id); ret = kfd_ptl_control(pdd, true); + if (adev->kfd.init_complete) + amdgpu_amdkfd_start_sched(adev, pdd->dev->node_id); if (ret) { atomic_inc(&adev->psp.ptl_disable_ref); dev_warn(pdd->dev->adev->dev, @@ -1964,6 +1968,7 @@ int kfd_ptl_disable_release(struct kfd_process_device *pdd, goto out; } } + pdd->ptl_disable_req = false; out: From d0d3a7bbe4979ee0588c36f500016d78186b002e Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Wed, 7 Jan 2026 15:16:52 +0800 Subject: [PATCH 2605/2653] drm/amdkfd: suspend scheduler during PTL re-enabling Stop the scheduler before releasing the PTL disable request to ensure the GPU is quiescent during the PTL state transition. This prevents potential queue preemption failures and GPU resets caused by modifying PTL state while waves are executing v1->v2: only stop/start the scheduler when the PTL state actually needs to transition(Yifan) Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang From 07b1c1ae7b2a66c970a0d344569528455972600b Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Thu, 25 Dec 2025 16:43:49 +0800 Subject: [PATCH 2606/2653] drm/amd/pm: Disable MMIO access during SMU Mode 1 reset During Mode 1 reset, the ASIC undergoes a reset cycle and becomes temporarily inaccessible via PCIe. Any attempt to access MMIO registers during this window (e.g., from interrupt handlers or other driver threads) can result in uncompleted PCIe transactions, leading to NMI panics or system hangs. To prevent this, set the `no_hw_access` flag to true immediately after triggering the reset. This signals other driver components to skip register accesses while the device is offline. A memory barrier `smp_mb()` is added to ensure the flag update is globally visible to all cores before the driver enters the sleep/wait state. Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 7 ++++++- drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 9 +++++++-- 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 7cac943c641f8..3665b7bd75946 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5906,6 +5906,9 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev) if (ret) goto mode1_reset_failed; + /* enable mmio access after mode 1 reset completed */ + adev->no_hw_access = false; + amdgpu_device_load_pci_state(adev->pdev); ret = amdgpu_psp_wait_for_bootloader(adev); if (ret) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index d8871a0f05420..4d3af8a68675c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -2923,8 +2923,13 @@ static int smu_v13_0_0_mode1_reset(struct smu_context *smu) break; } - if (!ret) + if (!ret) { + /* disable mmio access while doing mode 1 reset*/ + smu->adev->no_hw_access = true; + /* ensure no_hw_access is globally visible before any MMIO */ + smp_mb(); msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); + } return ret; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index 2cea688c604f2..33c3cd2e1e244 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -2143,10 +2143,15 @@ static int smu_v14_0_2_mode1_reset(struct smu_context *smu) ret = smu_cmn_send_debug_smc_msg(smu, DEBUGSMC_MSG_Mode1Reset); if (!ret) { - if (amdgpu_emu_mode == 1) + if (amdgpu_emu_mode == 1) { msleep(50000); - else + } else { + /* disable mmio access while doing mode 1 reset*/ + smu->adev->no_hw_access = true; + /* ensure no_hw_access is globally visible before any MMIO */ + smp_mb(); msleep(1000); + } } return ret; From 33970e1351f5e511029602454979f3de7e22260f Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Fri, 9 Jan 2026 22:12:42 +0800 Subject: [PATCH 2607/2653] drm/amdkfd: Refactor PTL control and add HW support check This is a design change to move the scheduler suspension and resumption logic directly into kfd_ptl_control. This ensures the KFD scheduler is always stopped during PTL switching command execution, which is required for the updated PTL control flow. Additionally, update profile_lock_device() to check for ptl_hw_supported before attempting to enable or disable PTL restrictions. Signed-off-by: Perry Yuan Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 27 ++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index dad7d628da0f4..c50346154c0e1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1903,10 +1903,17 @@ int kfd_ptl_control(struct kfd_process_device *pdd, bool enable) if (!pdd->dev->kfd2kgd || !pdd->dev->kfd2kgd->ptl_ctrl) return -EOPNOTSUPP; + if (adev->kfd.init_complete) + amdgpu_amdkfd_stop_sched(adev, pdd->dev->node_id); + ret = pdd->dev->kfd2kgd->ptl_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &pref_format1, &pref_format2); + + if (adev->kfd.init_complete) + amdgpu_amdkfd_start_sched(adev, pdd->dev->node_id); + return ret; } @@ -1956,11 +1963,7 @@ int kfd_ptl_disable_release(struct kfd_process_device *pdd, goto out; if (atomic_dec_return(&adev->psp.ptl_disable_ref) == 0) { - if (adev->kfd.init_complete) - amdgpu_amdkfd_stop_sched(adev, pdd->dev->node_id); ret = kfd_ptl_control(pdd, true); - if (adev->kfd.init_complete) - amdgpu_amdkfd_start_sched(adev, pdd->dev->node_id); if (ret) { atomic_inc(&adev->psp.ptl_disable_ref); dev_warn(pdd->dev->adev->dev, @@ -3505,7 +3508,13 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, if (!kfd->profiler_process) { kfd->profiler_process = p; status = 0; - kfd_ptl_disable_request(pdd, p); + if (pdd->dev->adev->psp.ptl_hw_supported) { + status = kfd_ptl_disable_request(pdd, p); + if (status != 0) + dev_err(kfd_device, + "Failed to lock device %d for profiling, error %d\n", + gpu_id, status); + } } else if (kfd->profiler_process == p) { status = -EALREADY; } else { @@ -3514,8 +3523,14 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, } else if (op == 0 && kfd->profiler_process == p) { kfd->profiler_process = NULL; status = 0; - kfd_ptl_disable_release(pdd, p); + if (pdd->dev->adev->psp.ptl_hw_supported) { + status = kfd_ptl_disable_release(pdd, p); + if (status) + dev_err(kfd_device, + "Failed to unlock device %d for profiling, error %d\n", + gpu_id, status); + } } mutex_unlock(&kfd->profiler_lock); From 94e97e16748e37b122afb347d8199fed8253e321 Mon Sep 17 00:00:00 2001 From: Shikang Fan Date: Wed, 19 Nov 2025 18:05:10 +0800 Subject: [PATCH 2608/2653] drm/amdgpu: Add sriov vf check for VCN per queue reset support. Add SRIOV check when setting VCN ring's supported reset mask. Signed-off-by: Shikang Fan Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index eacf4e93ba2fe..cb7123ec1a5d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -141,7 +141,7 @@ static int vcn_v4_0_3_late_init(struct amdgpu_ip_block *ip_block) adev->vcn.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); - if (amdgpu_dpm_reset_vcn_is_supported(adev)) + if (amdgpu_dpm_reset_vcn_is_supported(adev) && !amdgpu_sriov_vf(adev)) adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c index 714350cabf2fc..8bd457dea4cff 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c @@ -122,7 +122,9 @@ static int vcn_v5_0_1_late_init(struct amdgpu_ip_block *ip_block) switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { case IP_VERSION(13, 0, 12): - if ((adev->psp.sos.fw_version >= 0x00450025) && amdgpu_dpm_reset_vcn_is_supported(adev)) + if ((adev->psp.sos.fw_version >= 0x00450025) && + amdgpu_dpm_reset_vcn_is_supported(adev) && + !amdgpu_sriov_vf(adev)) adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; break; default: From 55769e53f79d1f0c634b478f8399df90bdb08995 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 12 Jan 2026 12:42:59 +0800 Subject: [PATCH 2609/2653] drm/amdkfd: Optimize PTL locking to fix potential deadlock Release profiler_lock before calling kfd_ptl_disable_request and kfd_ptl_disable_release to resolve potential deadlock Introduce a dedicated adev->psp.ptl_mutex to protect PTL state instead of relying on the KFD process mutex. This optimization ensures thread safety independent of the process lock hierarchy. Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 16 +++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 + drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 12 ++++++++---- 4 files changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 3665b7bd75946..30492a76f999b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4609,6 +4609,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->virt.vf_errors.lock); hash_init(adev->mn_hash); mutex_init(&adev->psp.mutex); + mutex_init(&adev->psp.ptl_mutex); #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mutex_init(&adev->notifier_lock); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 3ef5ee858e06f..7f60cc6648a7e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1263,6 +1263,15 @@ int psp_performance_monitor_hw(struct psp_context *psp, u32 req_code, psp_ptl_fmt_verify(psp, *fmt2, &ptl_fmt2)) return -EINVAL; + /* + * Add check to skip if state and formats are identical to current ones + */ + if (req_code == PSP_PTL_PERF_MON_SET && + psp->ptl_enabled == *ptl_state && + psp->ptl_fmt1 == ptl_fmt1 && + psp->ptl_fmt2 == ptl_fmt2) + return 0; + cmd = acquire_psp_cmd_buf(psp); cmd->cmd_id = GFX_CMD_ID_PERF_HW; @@ -1337,19 +1346,24 @@ static ssize_t ptl_enable_store(struct device *dev, else return -EINVAL; + mutex_lock(&psp->ptl_mutex); fmt1 = psp->ptl_fmt1; fmt2 = psp->ptl_fmt2; ptl_state = enable ? 1 : 0; cur_enabled = READ_ONCE(psp->ptl_enabled); - if (cur_enabled == enable) + if (cur_enabled == enable) { + mutex_unlock(&psp->ptl_mutex); return count; + } ret = psp_performance_monitor_hw(psp, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); if (ret) { dev_err(adev->dev, "Failed to set PTL err = %d\n", ret); + mutex_unlock(&psp->ptl_mutex); return ret; } + mutex_unlock(&psp->ptl_mutex); return count; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 4b2e82628d812..f08b1f985ef89 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -454,6 +454,7 @@ struct psp_context { bool ptl_hw_supported; /* PTL disable reference counting */ atomic_t ptl_disable_ref; + struct mutex ptl_mutex; }; struct amdgpu_psp_funcs { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index c50346154c0e1..a6a4c130b9e00 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1927,7 +1927,7 @@ int kfd_ptl_disable_request(struct kfd_process_device *pdd, return -ENODEV; adev = pdd->dev->adev; - mutex_lock(&p->mutex); + mutex_lock(&adev->psp.ptl_mutex); if (pdd->ptl_disable_req) goto out; @@ -1944,7 +1944,7 @@ int kfd_ptl_disable_request(struct kfd_process_device *pdd, pdd->ptl_disable_req = true; out: - mutex_unlock(&p->mutex); + mutex_unlock(&adev->psp.ptl_mutex); return ret; } @@ -1958,7 +1958,7 @@ int kfd_ptl_disable_release(struct kfd_process_device *pdd, return -ENODEV; adev = pdd->dev->adev; - mutex_lock(&p->mutex); + mutex_lock(&adev->psp.ptl_mutex); if (!pdd->ptl_disable_req) goto out; @@ -1975,7 +1975,7 @@ int kfd_ptl_disable_release(struct kfd_process_device *pdd, pdd->ptl_disable_req = false; out: - mutex_unlock(&p->mutex); + mutex_unlock(&adev->psp.ptl_mutex); return ret; } @@ -3508,6 +3508,7 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, if (!kfd->profiler_process) { kfd->profiler_process = p; status = 0; + mutex_unlock(&kfd->profiler_lock); if (pdd->dev->adev->psp.ptl_hw_supported) { status = kfd_ptl_disable_request(pdd, p); if (status != 0) @@ -3515,6 +3516,7 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, "Failed to lock device %d for profiling, error %d\n", gpu_id, status); } + return status; } else if (kfd->profiler_process == p) { status = -EALREADY; } else { @@ -3523,6 +3525,7 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, } else if (op == 0 && kfd->profiler_process == p) { kfd->profiler_process = NULL; status = 0; + mutex_unlock(&kfd->profiler_lock); if (pdd->dev->adev->psp.ptl_hw_supported) { status = kfd_ptl_disable_release(pdd, p); @@ -3531,6 +3534,7 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, "Failed to unlock device %d for profiling, error %d\n", gpu_id, status); } + return status; } mutex_unlock(&kfd->profiler_lock); From 62d17b54fc6e061770bd75369bb0c4bf500aaf2e Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 20 Jan 2026 16:09:19 +0800 Subject: [PATCH 2610/2653] drm/amdgpu: update PTL sysfs mutex protection section extends the critical section of 'ptl_mutex' to cover the PTL sysfs update operation. Signed-off-by: Perry Yuan Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 7f60cc6648a7e..02b8f88c7d0f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1339,14 +1339,16 @@ static ssize_t ptl_enable_store(struct device *dev, uint32_t ptl_state, fmt1, fmt2; int ret; - if (sysfs_streq(buf, "enabled") || sysfs_streq(buf, "1")) + mutex_lock(&psp->ptl_mutex); + if (sysfs_streq(buf, "enabled") || sysfs_streq(buf, "1")) { enable = true; - else if (sysfs_streq(buf, "disabled") || sysfs_streq(buf, "0")) + } else if (sysfs_streq(buf, "disabled") || sysfs_streq(buf, "0")) { enable = false; - else + } else { + mutex_unlock(&psp->ptl_mutex); return -EINVAL; + } - mutex_lock(&psp->ptl_mutex); fmt1 = psp->ptl_fmt1; fmt2 = psp->ptl_fmt2; ptl_state = enable ? 1 : 0; @@ -1393,17 +1395,22 @@ static ssize_t ptl_format_store(struct device *dev, if (!psp->ptl_enabled) return -EPERM; + mutex_lock(&psp->ptl_mutex); /* Parse input, expecting "FMT1,FMT2" */ - if (sscanf(buf, "%7[^,],%7s", fmt1_str, fmt2_str) != 2) + if (sscanf(buf, "%7[^,],%7s", fmt1_str, fmt2_str) != 2) { + mutex_unlock(&psp->ptl_mutex); return -EINVAL; + } fmt1_enum = str_to_ptl_fmt(fmt1_str); fmt2_enum = str_to_ptl_fmt(fmt2_str); if (fmt1_enum >= AMDGPU_PTL_FMT_INVALID || fmt2_enum >= AMDGPU_PTL_FMT_INVALID || - fmt1_enum == fmt2_enum) + fmt1_enum == fmt2_enum) { + mutex_unlock(&psp->ptl_mutex); return -EINVAL; + } ptl_state = psp->ptl_enabled; fmt1 = fmt1_enum; @@ -1411,8 +1418,10 @@ static ssize_t ptl_format_store(struct device *dev, ret = psp_performance_monitor_hw(psp, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); if (ret) { dev_err(adev->dev, "Failed to update PTL err = %d\n", ret); + mutex_unlock(&psp->ptl_mutex); return ret; } + mutex_unlock(&psp->ptl_mutex); return count; } From e19304d17e3230a4b6e45b5bfa6687c899ddc465 Mon Sep 17 00:00:00 2001 From: Victor Zhao Date: Thu, 18 Dec 2025 18:41:35 +0800 Subject: [PATCH 2611/2653] drm/amdgpu: add generic interfaces for PTL requests in virtualization Add Performance Throttle Limiter (PTL) support for SR-IOV guest. Since VF cannot communicate with PSP directly at runtime in SR-IOV environment, use mailbox data fields to pass PTL parameters to PF, and parse response status from host mailbox registers. v2: - remove redundent checks - remove unused marco Signed-off-by: Victor Zhao Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 12 +++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 36 +++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 12 +++++++ drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 30 ++++++++++++++++- drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 30 ++++++++++++++++- drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h | 6 +++- 6 files changed, 121 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 02b8f88c7d0f7..de3731329904c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1246,14 +1246,22 @@ int psp_performance_monitor_hw(struct psp_context *psp, u32 req_code, uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2) { struct psp_gfx_cmd_resp *cmd; + struct amdgpu_device *adev = psp->adev; uint32_t ptl_fmt1, ptl_fmt2; int ret; if (!psp || !ptl_state || !fmt1 || !fmt2) return -EINVAL; - if (amdgpu_sriov_vf(psp->adev)) - return 0; + if (amdgpu_sriov_vf(adev)) { + ret = amdgpu_virt_ptl_request(adev, req_code, ptl_state, fmt1, fmt2); + if (!ret) { + psp->ptl_enabled = *ptl_state; + psp->ptl_fmt1 = *fmt1; + psp->ptl_fmt2 = *fmt2; + } + return ret; + } if (amdgpu_ip_version(psp->adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) || psp->sos.fw_version < 0x0036081a) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 47a6ce4fdc744..828eb3549b882 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -1845,3 +1845,39 @@ int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, b return r; } + +int amdgpu_virt_ptl_request(struct amdgpu_device *adev, u32 req_code, + uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2) +{ + int ret; + + if (!ptl_state || !fmt1 || !fmt2) + return -EINVAL; + + if (!amdgpu_sriov_ptl_support(adev) || + !adev->virt.ops || !adev->virt.ops->req_ptl_update) + return -EOPNOTSUPP; + + if (req_code == PSP_PTL_PERF_MON_SET && *ptl_state) { + if (*fmt1 == *fmt2) { + dev_warn(adev->dev, + "PTL formats must be different (fmt1=%u, fmt2=%u)\n", + *fmt1, *fmt2); + return -EINVAL; + } + } + + ret = adev->virt.ops->req_ptl_update(adev, req_code, *ptl_state, *fmt1, *fmt2); + if (ret) { + dev_warn(adev->dev, "VF PTL update request failed: %d\n", ret); + return ret; + } + + if (req_code == PSP_PTL_PERF_MON_QUERY) { + *ptl_state = adev->virt.ptl_state; + *fmt1 = adev->virt.ptl_pref_format1; + *fmt2 = adev->virt.ptl_pref_format2; + } + + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 01d5bca2dee16..29f1697ca76fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -105,6 +105,8 @@ struct amdgpu_virt_ops { int (*req_ras_cper_dump)(struct amdgpu_device *adev, u64 vf_rptr); int (*req_bad_pages)(struct amdgpu_device *adev); int (*req_ras_chk_criti)(struct amdgpu_device *adev, u64 addr); + int (*req_ptl_update)(struct amdgpu_device *adev, + u32 req_code, u32 ptl_state, u32 fmt1, u32 fmt2); }; /* @@ -151,6 +153,7 @@ enum AMDGIM_FEATURE_FLAG { AMDGIM_FEATURE_RAS_TELEMETRY = (1 << 10), AMDGIM_FEATURE_RAS_CPER = (1 << 11), AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK = (1 << 12), + AMDGIM_FEATURE_PTL_SUPPORT = (1 << 13), }; enum AMDGIM_REG_ACCESS_FLAG { @@ -325,6 +328,11 @@ struct amdgpu_virt { /* Spinlock to protect access to the RLCG register interface */ spinlock_t rlcg_reg_lock; + /* PTL (Performance Throttle Limiter) response from host */ + uint32_t ptl_state; + uint32_t ptl_pref_format1; + uint32_t ptl_pref_format2; + struct mutex access_req_mutex; union amd_sriov_ras_caps ras_en_caps; @@ -426,6 +434,8 @@ static inline bool is_virtual_machine(void) ((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE) #define amdgpu_sriov_is_mes_info_enable(adev) \ ((adev)->virt.gim_feature & AMDGIM_FEATURE_MES_INFO_ENABLE) +#define amdgpu_sriov_ptl_support(adev) \ + ((adev)->virt.gim_feature & AMDGIM_FEATURE_PTL_SUPPORT) #define amdgpu_virt_xgmi_migrate_enabled(adev) \ ((adev)->virt.is_xgmi_node_migrate_enabled && (adev)->gmc.xgmi.node_segment_size != 0) @@ -436,6 +446,8 @@ int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); void amdgpu_virt_request_init_data(struct amdgpu_device *adev); +int amdgpu_virt_ptl_request(struct amdgpu_device *adev, u32 req_code, + uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2); void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev); int amdgpu_virt_wait_reset(struct amdgpu_device *adev); int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h index 3cdb1e0eca377..499287c3f5cc8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h @@ -161,7 +161,8 @@ union amd_sriov_msg_feature_flags { uint32_t ras_telemetry : 1; uint32_t ras_cper : 1; uint32_t xgmi_ta_ext_peer_link : 1; - uint32_t reserved : 19; + uint32_t ptl_support : 1; + uint32_t reserved : 18; } flags; uint32_t all; }; @@ -393,6 +394,9 @@ enum amd_sriov_mailbox_request_message { MB_REQ_RAS_ERROR_COUNT = 203, MB_REQ_RAS_CPER_DUMP = 204, MB_REQ_RAS_BAD_PAGES = 205, + MB_REQ_RAS_CHK_CRITI = 206, + MB_REQ_RAS_REMOTE_CMD = 207, + MB_REQ_MSG_PTL_UPDATE = 208, }; /* mailbox message send from host to guest */ @@ -413,9 +417,33 @@ enum amd_sriov_mailbox_response_message { MB_RES_MSG_RAS_BAD_PAGES_READY = 15, MB_RES_MSG_RAS_BAD_PAGES_NOTIFICATION = 16, MB_RES_MSG_UNRECOV_ERR_NOTIFICATION = 17, + MB_RES_RAS_CHK_CRITI_READY = 18, + MB_RES_RAS_REMOTE_CMD_READY = 19, + MB_RES_MSG_PTL_UPDATE_READY = 20, MB_RES_MSG_TEXT_MESSAGE = 255 }; +/* + * Generic response status codes for mailbox data fields. + * Used in msg_data[1..N] to indicate operation result. + */ +enum amd_sriov_response_status { + AMD_SRIOV_RESP_SUCCESS = 0, + AMD_SRIOV_RESP_FAIL = 1, + AMD_SRIOV_RESP_UNSUPPORTED = 2, +}; + +/* + * PTL mailbox data format: + * Request: msg_data[1]=req_code, msg_data[2]=ptl_state, msg_data[3]=(fmt1<<16)|fmt2 + * Response: msg_data[1]=(status<<16)|ptl_state, msg_data[2]=(fmt1<<16)|fmt2 + */ +#define AMD_SRIOV_PTL_PACK_FORMATS(fmt1, fmt2) ((((fmt1) & 0xFFFF) << 16) | ((fmt2) & 0xFFFF)) +#define AMD_SRIOV_PTL_UNPACK_STATUS(dw) (((dw) >> 16) & 0xFFFF) +#define AMD_SRIOV_PTL_UNPACK_STATE(dw) ((dw) & 0xFFFF) +#define AMD_SRIOV_PTL_UNPACK_FMT1(dw) (((dw) >> 16) & 0xFFFF) +#define AMD_SRIOV_PTL_UNPACK_FMT2(dw) ((dw) & 0xFFFF) + enum amd_sriov_ras_telemetry_gpu_block { RAS_TELEMETRY_GPU_BLOCK_UMC = 0, RAS_TELEMETRY_GPU_BLOCK_SDMA = 1, diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c index e7cd07383d56e..e977f525fd4a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c @@ -209,6 +209,9 @@ static int xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev, case IDH_REQ_RAS_CHK_CRITI: event = IDH_REQ_RAS_CHK_CRITI_READY; break; + case IDH_REQ_PTL_UPDATE: + event = IDH_PTL_UPDATE_READY; + break; default: break; } @@ -248,6 +251,23 @@ static int xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev, adev->virt.fw_reserve.checksum_key = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW2); } + + /* Retrieve PTL response from mailbox */ + if (req == IDH_REQ_PTL_UPDATE) { + u32 dw1 = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW1); + u32 dw2 = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW2); + u32 status = AMD_SRIOV_PTL_UNPACK_STATUS(dw1); + + if (status == AMD_SRIOV_RESP_UNSUPPORTED) { + r = -EOPNOTSUPP; + } else if (status == AMD_SRIOV_RESP_FAIL) { + r = -EIO; + } else { + adev->virt.ptl_state = AMD_SRIOV_PTL_UNPACK_STATE(dw1); + adev->virt.ptl_pref_format1 = AMD_SRIOV_PTL_UNPACK_FMT1(dw2); + adev->virt.ptl_pref_format2 = AMD_SRIOV_PTL_UNPACK_FMT2(dw2); + } + } } out: @@ -585,6 +605,13 @@ static int xgpu_nv_check_vf_critical_region(struct amdgpu_device *adev, u64 addr adev, IDH_REQ_RAS_CHK_CRITI, addr_hi, addr_lo, 0); } +static int xgpu_nv_req_ptl_update(struct amdgpu_device *adev, + u32 req_code, u32 ptl_state, u32 fmt1, u32 fmt2) +{ + return xgpu_nv_send_access_requests_with_param(adev, IDH_REQ_PTL_UPDATE, + req_code, ptl_state, AMD_SRIOV_PTL_PACK_FORMATS(fmt1, fmt2)); +} + const struct amdgpu_virt_ops xgpu_nv_virt_ops = { .req_full_gpu = xgpu_nv_request_full_gpu_access, .rel_full_gpu = xgpu_nv_release_full_gpu_access, @@ -598,5 +625,6 @@ const struct amdgpu_virt_ops xgpu_nv_virt_ops = { .req_ras_err_count = xgpu_nv_req_ras_err_count, .req_ras_cper_dump = xgpu_nv_req_ras_cper_dump, .req_bad_pages = xgpu_nv_req_ras_bad_pages, - .req_ras_chk_criti = xgpu_nv_check_vf_critical_region + .req_ras_chk_criti = xgpu_nv_check_vf_critical_region, + .req_ptl_update = xgpu_nv_req_ptl_update, }; diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h index c1083e5e41e02..5023113e76008 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h @@ -43,7 +43,9 @@ enum idh_request { IDH_REQ_RAS_ERROR_COUNT = 203, IDH_REQ_RAS_CPER_DUMP = 204, IDH_REQ_RAS_BAD_PAGES = 205, - IDH_REQ_RAS_CHK_CRITI = 206 + IDH_REQ_RAS_CHK_CRITI = 206, + IDH_REQ_RAS_REMOTE_CMD = 207, + IDH_REQ_PTL_UPDATE = 208 }; enum idh_event { @@ -64,6 +66,8 @@ enum idh_event { IDH_RAS_BAD_PAGES_NOTIFICATION = 16, IDH_UNRECOV_ERR_NOTIFICATION = 17, IDH_REQ_RAS_CHK_CRITI_READY = 18, + IDH_REQ_RAS_REMOTE_CMD_READY = 19, + IDH_PTL_UPDATE_READY = 20, IDH_TEXT_MESSAGE = 255, }; From e1e685eac76d9fca62e01470ef0c2351ca03c4a0 Mon Sep 17 00:00:00 2001 From: Victor Zhao Date: Thu, 18 Dec 2025 18:41:52 +0800 Subject: [PATCH 2612/2653] drm/amdgpu: always get PTL state from PSP under sriov In SR-IOV mode, always query the latest PTL status from host via psp_performance_monitor_hw() to ensure the sysfs shows real-time hardware state. Signed-off-by: Victor Zhao Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index de3731329904c..e6362c165da22 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1383,6 +1383,15 @@ static ssize_t ptl_enable_show(struct device *dev, struct device_attribute *attr struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(ddev); struct psp_context *psp = &adev->psp; + uint32_t ptl_state, fmt1, fmt2; + int ret; + + if (amdgpu_sriov_vf(adev)) { + ret = psp_performance_monitor_hw(psp, PSP_PTL_PERF_MON_QUERY, + &ptl_state, &fmt1, &fmt2); + if (ret) + return ret; + } return sysfs_emit(buf, "%s\n", psp->ptl_enabled ? "enabled" : "disabled"); } @@ -1439,6 +1448,15 @@ static ssize_t ptl_format_show(struct device *dev, struct device_attribute *attr struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(ddev); struct psp_context *psp = &adev->psp; + uint32_t ptl_state, fmt1, fmt2; + int ret; + + if (amdgpu_sriov_vf(adev)) { + ret = psp_performance_monitor_hw(psp, PSP_PTL_PERF_MON_QUERY, + &ptl_state, &fmt1, &fmt2); + if (ret) + return ret; + } return sysfs_emit(buf, "%s,%s\n", amdgpu_ptl_fmt_str[psp->ptl_fmt1], From 06e8667e51245bfe2d136b5e60d25b2aa6cfb905 Mon Sep 17 00:00:00 2001 From: Victor Zhao Date: Thu, 18 Dec 2025 18:42:04 +0800 Subject: [PATCH 2613/2653] drm/amdgpu: convert ptl_hw_supported to enum Convert ptl_hw_supported to enum with three states: - AMDGPU_PTL_HW_UNINIT: not yet initialized - AMDGPU_PTL_HW_SUPPORTED: initialized and supported - AMDGPU_PTL_HW_NOT_SUPPORTED: initialized and not supported This allows skipping PTL initialization attempts when hardware is known to not support it, avoiding repeated initialization failures after GPU resets. v2:move ptl_hw_supported_state to AMDGPU_PTL_HW_NOT_SUPPORTED regardless of error code during first time initialization. Print init fail log when error code is not EOPNOTSUPP. Signed-off-by: Victor Zhao Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 20 +++++++++++++++----- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 +++--- drivers/gpu/drm/amd/include/amdgpu_ptl.h | 6 ++++++ 5 files changed, 28 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index e6362c165da22..62414b97a50e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1470,7 +1470,7 @@ static umode_t amdgpu_ptl_is_visible(struct kobject *kobj, struct attribute *att struct amdgpu_device *adev = drm_to_adev(ddev); /* Only show PTL sysfs files if PTL hardware is supported */ - if (!adev->psp.ptl_hw_supported) + if (adev->psp.ptl_hw_supported_state != AMDGPU_PTL_HW_SUPPORTED) return 0; return attr->mode; @@ -1478,7 +1478,7 @@ static umode_t amdgpu_ptl_is_visible(struct kobject *kobj, struct attribute *att int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev) { - if (!adev->psp.ptl_hw_supported) + if (adev->psp.ptl_hw_supported_state != AMDGPU_PTL_HW_SUPPORTED) return 0; return sysfs_create_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); @@ -1486,7 +1486,7 @@ int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev) void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev) { - if (!adev->psp.ptl_hw_supported) + if (adev->psp.ptl_hw_supported_state != AMDGPU_PTL_HW_SUPPORTED) return; sysfs_remove_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index f08b1f985ef89..4ca1e2a0fb889 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -451,10 +451,10 @@ struct psp_context { enum amdgpu_ptl_fmt ptl_fmt1; enum amdgpu_ptl_fmt ptl_fmt2; bool ptl_enabled; - bool ptl_hw_supported; /* PTL disable reference counting */ atomic_t ptl_disable_ref; struct mutex ptl_mutex; + enum amdgpu_ptl_hw_supported_state ptl_hw_supported_state; }; struct amdgpu_psp_funcs { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 9436bf42d5fd0..ebf0956c0e433 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2402,7 +2402,10 @@ static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool sta if (!adev->psp.funcs) return -EOPNOTSUPP; - if (!adev->psp.ptl_hw_supported) { + if (adev->psp.ptl_hw_supported_state == AMDGPU_PTL_HW_NOT_SUPPORTED) + return -EOPNOTSUPP; + + if (adev->psp.ptl_hw_supported_state == AMDGPU_PTL_HW_UNINIT) { fmt1 = GFX_FTYPE_I8; fmt2 = GFX_FTYPE_BF16; } else { @@ -2412,11 +2415,18 @@ static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool sta /* initialize PTL with default formats: GFX_FTYPE_I8 & GFX_FTYPE_BF16 */ r = psp_performance_monitor_hw(&adev->psp, PSP_PTL_PERF_MON_SET, &ptl_state, - &fmt1, &fmt2); - if (r) + &fmt1, &fmt2); + if (r) { + if (adev->psp.ptl_hw_supported_state == AMDGPU_PTL_HW_UNINIT) + adev->psp.ptl_hw_supported_state = AMDGPU_PTL_HW_NOT_SUPPORTED; + + if (r != -EOPNOTSUPP) + dev_err(adev->dev, "PTL initialization failed (%d)\n", r); + return r; + } - adev->psp.ptl_hw_supported = true; + adev->psp.ptl_hw_supported_state = AMDGPU_PTL_HW_SUPPORTED; atomic_set(&adev->psp.ptl_disable_ref, 0); @@ -2428,7 +2438,7 @@ static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; int i, num_xcc; - if (adev->psp.ptl_hw_supported) + if (adev->psp.ptl_hw_supported_state == AMDGPU_PTL_HW_SUPPORTED) gfx_v9_4_3_perf_monitor_ptl_init(adev, 0); amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index a6a4c130b9e00..30ec29b4dde5a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1897,7 +1897,7 @@ int kfd_ptl_control(struct kfd_process_device *pdd, bool enable) uint32_t ptl_state = enable ? 1 : 0; int ret; - if (!adev->psp.ptl_hw_supported) + if (adev->psp.ptl_hw_supported_state != AMDGPU_PTL_HW_SUPPORTED) return -EOPNOTSUPP; if (!pdd->dev->kfd2kgd || !pdd->dev->kfd2kgd->ptl_ctrl) @@ -3509,7 +3509,7 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, kfd->profiler_process = p; status = 0; mutex_unlock(&kfd->profiler_lock); - if (pdd->dev->adev->psp.ptl_hw_supported) { + if (pdd->dev->adev->psp.ptl_hw_supported_state == AMDGPU_PTL_HW_SUPPORTED) { status = kfd_ptl_disable_request(pdd, p); if (status != 0) dev_err(kfd_device, @@ -3527,7 +3527,7 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, status = 0; mutex_unlock(&kfd->profiler_lock); - if (pdd->dev->adev->psp.ptl_hw_supported) { + if (pdd->dev->adev->psp.ptl_hw_supported_state == AMDGPU_PTL_HW_SUPPORTED) { status = kfd_ptl_disable_release(pdd, p); if (status) dev_err(kfd_device, diff --git a/drivers/gpu/drm/amd/include/amdgpu_ptl.h b/drivers/gpu/drm/amd/include/amdgpu_ptl.h index 1a5c6fd6b74dd..67d114ae9718a 100644 --- a/drivers/gpu/drm/amd/include/amdgpu_ptl.h +++ b/drivers/gpu/drm/amd/include/amdgpu_ptl.h @@ -32,6 +32,12 @@ enum amdgpu_ptl_fmt { AMDGPU_PTL_FMT_INVALID = 5, }; +enum amdgpu_ptl_hw_supported_state { + AMDGPU_PTL_HW_UNINIT = 0, /* Not yet initialized */ + AMDGPU_PTL_HW_SUPPORTED, /* Initialized and supported */ + AMDGPU_PTL_HW_NOT_SUPPORTED, /* Initialized and not supported */ +}; + enum psp_ptl_cmd { PSP_PTL_PERF_MON_QUERY = 0xA0000000, PSP_PTL_PERF_MON_SET = 0xA0000001, From 59f0fcb2c762673bba3a87d5d3a73523ef840539 Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Wed, 19 Nov 2025 15:07:10 -0500 Subject: [PATCH 2614/2653] drm/amdkfd: assign AID to uuid in topology for SPX mode XCD id is assigned to uuid, which causes some performance drop in SPX mode, assigning AID back will resolve the issue. Fixes: "drm/amdkfd: set uuid for each partition in topology" Signed-off-by: Eric Huang Reviewed-by: Harish Kasiviswanathan (cherry picked from commit 1854c159e4c741149162b9ba6850ffd4f1c916b6) Change-Id: If11d75a63825d6ca593dbd3d214f08ae945f5377 --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 8644039777b85..185ca078c8f3c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -546,7 +546,9 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr, sysfs_show_32bit_prop(buffer, offs, "sdma_fw_version", dev->gpu->kfd->sdma_fw_version); sysfs_show_64bit_prop(buffer, offs, "unique_id", - dev->gpu->xcp ? + dev->gpu->xcp && + (dev->gpu->xcp->xcp_mgr->mode != + AMDGPU_SPX_PARTITION_MODE) ? dev->gpu->xcp->unique_id : dev->gpu->adev->unique_id); sysfs_show_32bit_prop(buffer, offs, "num_xcc", From c684b124f815c1db6f8a2f6131296bb4850c65a7 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 19 Jan 2024 10:02:14 +0800 Subject: [PATCH 2615/2653] drm/amdgpu: Fix possible null pointer dereference mem = bo->tbo.resource may be NULL in amdgpu_vm_bo_update. Fixes: 180253782038 ("drm/ttm: stop allocating dummy resources during BO creation") Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index a6f466d6fd2a0..ff2d1a96f8e47 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1322,7 +1322,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, if (mem && (mem->mem_type == TTM_PL_TT || mem->mem_type == AMDGPU_PL_PREEMPT)) pages_addr = bo->tbo.ttm->dma_address; - else if (mem->mem_type == AMDGPU_PL_DGMA_IMPORT) + else if (mem && mem->mem_type == AMDGPU_PL_DGMA_IMPORT) pages_addr = (dma_addr_t *)bo->dgma_addr; /* Implicitly sync to moving fences before mapping anything */ From d9b4219f8e1ed4999e8d42f17bc883b634457fab Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Fri, 16 Jan 2026 11:32:08 +0800 Subject: [PATCH 2616/2653] drm/amdgpu: mark invalid records with U64_MAX set retired_page of invalid ras records to U64_MAX, and skip them when reading ras records Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou (cherry picked from commit dd653962d38def77d9fff77cf46b5d7293334623) Change-Id: Ib47f1e642120a239635cf9fe4c526d2ca636de72 --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 5c137a28f9ac8..459a01745d56e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2791,6 +2791,10 @@ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, if (!data->bps[i].ts) continue; + /* U64_MAX is used to mark the record as invalid */ + if (data->bps[i].retired_page == U64_MAX) + continue; + bps[r].bp = data->bps[i].retired_page; r++; if (r >= count) @@ -3097,6 +3101,8 @@ static int __amdgpu_ras_restore_bad_pages(struct amdgpu_device *adev, if (amdgpu_ras_check_bad_page_unlock(con, bps[j].retired_page << AMDGPU_GPU_PAGE_SHIFT)) { + /* set to U64_MAX to mark it as invalid */ + data->bps[data->count].retired_page = U64_MAX; data->count++; data->space_left--; continue; From 146ae3b49ea6ab83142b70e73a8aacf6bc7b21c8 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 12 Dec 2025 11:46:48 -0500 Subject: [PATCH 2617/2653] drm/amdgpu: avoid a warning in timedout job handler MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Only set an error on the fence if the fence is not signalled. We can end up with a warning if the per queue reset path signals the fence and sets an error as part of the reset, but fails to recover. Reviewed-by: Timur Kristóf Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index efa3281145f6c..c46e41d35393f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -147,7 +147,8 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) dev_err(adev->dev, "Ring %s reset failed\n", ring->sched.name); } - dma_fence_set_error(&s_job->s_fence->finished, -ETIME); + if (dma_fence_get_status(&s_job->s_fence->finished) == 0) + dma_fence_set_error(&s_job->s_fence->finished, -ETIME); amdgpu_vm_put_task_info(ti); From ec36c1c4b70f5d043007cd2de2d254994daef244 Mon Sep 17 00:00:00 2001 From: Harish Kasiviswanathan Date: Sun, 11 Jan 2026 16:53:18 -0500 Subject: [PATCH 2618/2653] drm/amdkfd: No need to suspend whole MES to evict process Each queue of the process is individually removed and there is not need to suspend whole mes. Suspending mes stops kernel mode queues also causing unnecessary timeouts when running mixed work loads Fixes: 079ae5118e1f ("drm/amdkfd: fix suspend/resume all calls in mes based eviction path") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4765 Signed-off-by: Harish Kasiviswanathan Reviewed-by: Alex Deucher (cherry picked from commit db4ea4701e720f68882b55de7e815283d3c546ba) Change-Id: Iaa020dd15cf275e5b04081bf9000318a334c84da --- .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 025cef14be49b..3dd04b99bd892 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -1264,14 +1264,8 @@ static int evict_process_queues_cpsch(struct device_queue_manager *dqm, pr_debug_ratelimited("Evicting process pid %d queues\n", pdd->process->lead_thread->pid); - if (dqm->dev->kfd->shared_resources.enable_mes) { + if (dqm->dev->kfd->shared_resources.enable_mes) pdd->last_evict_timestamp = get_jiffies_64(); - retval = suspend_all_queues_mes(dqm); - if (retval) { - dev_err(dev, "Suspending all queues failed"); - goto out; - } - } /* Mark all queues as evicted. Deactivate all active queues on * the qpd. @@ -1301,10 +1295,6 @@ static int evict_process_queues_cpsch(struct device_queue_manager *dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES : KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); - } else { - retval = resume_all_queues_mes(dqm); - if (retval) - dev_err(dev, "Resuming all queues failed"); } out: From acb9afecfb2829958121c965ab61dc94d0e74d7a Mon Sep 17 00:00:00 2001 From: Arunpravin Paneer Selvam Date: Mon, 6 Oct 2025 15:21:22 +0530 Subject: [PATCH 2619/2653] drm/buddy: Optimize free block management with RB tree Replace the freelist (O(n)) used for free block management with a red-black tree, providing more efficient O(log n) search, insert, and delete operations. This improves scalability and performance when managing large numbers of free blocks per order (e.g., hundreds or thousands). In the VK-CTS memory stress subtest, the buddy manager merges fragmented memory and inserts freed blocks into the freelist. Since freelist insertion is O(n), this becomes a bottleneck as fragmentation increases. Benchmarking shows list_insert_sorted() consumes ~52.69% CPU with the freelist, compared to just 0.03% with the RB tree (rbtree_insert.isra.0), despite performing the same sorted insert. This also improves performance in heavily fragmented workloads, such as games or graphics tests that stress memory. As the buddy allocator evolves with new features such as clear-page tracking, the resulting fragmentation and complexity have grown. These RB-tree based design changes are introduced to address that growth and ensure the allocator continues to perform efficiently under fragmented conditions. The RB tree implementation with separate clear/dirty trees provides: - O(n log n) aggregate complexity for all operations instead of O(n^2) - Elimination of soft lockups and system instability - Improved code maintainability and clarity - Better scalability for large memory systems - Predictable performance under fragmentation v3(Matthew): - Remove RB_EMPTY_NODE check in force_merge function. - Rename rb for loop macros to have less generic names and move to .c file. - Make the rb node rb and link field as union. v4(Jani Nikula): - The kernel-doc comment should be "/**" - Move all the rbtree macros to rbtree.h and add parens to ensure correct precedence. v5: - Remove the inline in a .c file (Jani Nikula). v6(Peter Zijlstra): - Add rb_add() function replacing the existing rbtree_insert() code. v7: - A full walk iteration in rbtree is slower than the list (Peter Zijlstra). - The existing rbtree_postorder_for_each_entry_safe macro should be used in scenarios where traversal order is not a critical factor (Christian). v8(Matthew): - Remove the rbtree_is_empty() check in this patch as well. Cc: stable@vger.kernel.org Fixes: a68c7eaa7a8f ("drm/amdgpu: Enable clear page functionality") Signed-off-by: Arunpravin Paneer Selvam Reviewed-by: Matthew Auld Link: https://lore.kernel.org/r/20251006095124.1663-1-Arunpravin.PaneerSelvam@amd.com --- drivers/gpu/drm/drm_buddy.c | 195 ++++++++++++++++++++++-------------- include/drm/drm_buddy.h | 11 +- 2 files changed, 126 insertions(+), 80 deletions(-) diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c index a94061f373de5..c87210a06c318 100644 --- a/drivers/gpu/drm/drm_buddy.c +++ b/drivers/gpu/drm/drm_buddy.c @@ -14,6 +14,8 @@ static struct kmem_cache *slab_blocks; +#define rbtree_get_free_block(node) rb_entry((node), struct drm_buddy_block, rb) + static struct drm_buddy_block *drm_block_alloc(struct drm_buddy *mm, struct drm_buddy_block *parent, unsigned int order, @@ -31,6 +33,8 @@ static struct drm_buddy_block *drm_block_alloc(struct drm_buddy *mm, block->header |= order; block->parent = parent; + RB_CLEAR_NODE(&block->rb); + BUG_ON(block->header & DRM_BUDDY_HEADER_UNUSED); return block; } @@ -41,23 +45,49 @@ static void drm_block_free(struct drm_buddy *mm, kmem_cache_free(slab_blocks, block); } -static void list_insert_sorted(struct drm_buddy *mm, - struct drm_buddy_block *block) +static bool drm_buddy_block_offset_less(const struct drm_buddy_block *block, + const struct drm_buddy_block *node) { - struct drm_buddy_block *node; - struct list_head *head; + return drm_buddy_block_offset(block) < drm_buddy_block_offset(node); +} - head = &mm->free_list[drm_buddy_block_order(block)]; - if (list_empty(head)) { - list_add(&block->link, head); - return; - } +static bool rbtree_block_offset_less(struct rb_node *block, + const struct rb_node *node) +{ + return drm_buddy_block_offset_less(rbtree_get_free_block(block), + rbtree_get_free_block(node)); +} - list_for_each_entry(node, head, link) - if (drm_buddy_block_offset(block) < drm_buddy_block_offset(node)) - break; +static void rbtree_insert(struct drm_buddy *mm, + struct drm_buddy_block *block) +{ + rb_add(&block->rb, + &mm->free_tree[drm_buddy_block_order(block)], + rbtree_block_offset_less); +} + +static void rbtree_remove(struct drm_buddy *mm, + struct drm_buddy_block *block) +{ + struct rb_root *root; + + root = &mm->free_tree[drm_buddy_block_order(block)]; + rb_erase(&block->rb, root); + + RB_CLEAR_NODE(&block->rb); +} + +static struct drm_buddy_block * +rbtree_last_entry(struct drm_buddy *mm, unsigned int order) +{ + struct rb_node *node = rb_last(&mm->free_tree[order]); + + return node ? rb_entry(node, struct drm_buddy_block, rb) : NULL; +} - __list_add(&block->link, node->link.prev, &node->link); +static bool rbtree_is_empty(struct drm_buddy *mm, unsigned int order) +{ + return RB_EMPTY_ROOT(&mm->free_tree[order]); } static void clear_reset(struct drm_buddy_block *block) @@ -70,12 +100,13 @@ static void mark_cleared(struct drm_buddy_block *block) block->header |= DRM_BUDDY_HEADER_CLEAR; } -static void mark_allocated(struct drm_buddy_block *block) +static void mark_allocated(struct drm_buddy *mm, + struct drm_buddy_block *block) { block->header &= ~DRM_BUDDY_HEADER_STATE; block->header |= DRM_BUDDY_ALLOCATED; - list_del(&block->link); + rbtree_remove(mm, block); } static void mark_free(struct drm_buddy *mm, @@ -84,15 +115,16 @@ static void mark_free(struct drm_buddy *mm, block->header &= ~DRM_BUDDY_HEADER_STATE; block->header |= DRM_BUDDY_FREE; - list_insert_sorted(mm, block); + rbtree_insert(mm, block); } -static void mark_split(struct drm_buddy_block *block) +static void mark_split(struct drm_buddy *mm, + struct drm_buddy_block *block) { block->header &= ~DRM_BUDDY_HEADER_STATE; block->header |= DRM_BUDDY_SPLIT; - list_del(&block->link); + rbtree_remove(mm, block); } static inline bool overlaps(u64 s1, u64 e1, u64 s2, u64 e2) @@ -148,7 +180,7 @@ static unsigned int __drm_buddy_free(struct drm_buddy *mm, mark_cleared(parent); } - list_del(&buddy->link); + rbtree_remove(mm, buddy); if (force_merge && drm_buddy_block_is_clear(buddy)) mm->clear_avail -= drm_buddy_block_size(mm, buddy); @@ -179,13 +211,19 @@ static int __force_merge(struct drm_buddy *mm, return -EINVAL; for (i = min_order - 1; i >= 0; i--) { - struct drm_buddy_block *block, *prev; + struct rb_root *root = &mm->free_tree[i]; + struct rb_node *iter; + + iter = rb_last(root); - list_for_each_entry_safe_reverse(block, prev, &mm->free_list[i], link) { - struct drm_buddy_block *buddy; + while (iter) { + struct drm_buddy_block *block, *buddy; u64 block_start, block_end; - if (!block->parent) + block = rbtree_get_free_block(iter); + iter = rb_prev(iter); + + if (!block || !block->parent) continue; block_start = drm_buddy_block_offset(block); @@ -201,15 +239,10 @@ static int __force_merge(struct drm_buddy *mm, WARN_ON(drm_buddy_block_is_clear(block) == drm_buddy_block_is_clear(buddy)); - /* - * If the prev block is same as buddy, don't access the - * block in the next iteration as we would free the - * buddy block as part of the free function. - */ - if (prev == buddy) - prev = list_prev_entry(prev, link); + if (iter == &buddy->rb) + iter = rb_prev(iter); - list_del(&block->link); + rbtree_remove(mm, block); if (drm_buddy_block_is_clear(block)) mm->clear_avail -= drm_buddy_block_size(mm, block); @@ -237,7 +270,7 @@ static int __force_merge(struct drm_buddy *mm, int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) { unsigned int i; - u64 offset; + u64 offset = 0; if (size < chunk_size) return -EINVAL; @@ -258,14 +291,14 @@ int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) BUG_ON(mm->max_order > DRM_BUDDY_MAX_ORDER); - mm->free_list = kmalloc_array(mm->max_order + 1, - sizeof(struct list_head), + mm->free_tree = kmalloc_array(mm->max_order + 1, + sizeof(struct rb_root), GFP_KERNEL); - if (!mm->free_list) + if (!mm->free_tree) return -ENOMEM; for (i = 0; i <= mm->max_order; ++i) - INIT_LIST_HEAD(&mm->free_list[i]); + mm->free_tree[i] = RB_ROOT; mm->n_roots = hweight64(size); @@ -273,9 +306,8 @@ int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) sizeof(struct drm_buddy_block *), GFP_KERNEL); if (!mm->roots) - goto out_free_list; + goto out_free_tree; - offset = 0; i = 0; /* @@ -312,8 +344,8 @@ int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) while (i--) drm_block_free(mm, mm->roots[i]); kfree(mm->roots); -out_free_list: - kfree(mm->free_list); +out_free_tree: + kfree(mm->free_tree); return -ENOMEM; } EXPORT_SYMBOL(drm_buddy_init); @@ -323,7 +355,7 @@ EXPORT_SYMBOL(drm_buddy_init); * * @mm: DRM buddy manager to free * - * Cleanup memory manager resources and the freelist + * Cleanup memory manager resources and the freetree */ void drm_buddy_fini(struct drm_buddy *mm) { @@ -350,7 +382,7 @@ void drm_buddy_fini(struct drm_buddy *mm) WARN_ON(mm->avail != mm->size); kfree(mm->roots); - kfree(mm->free_list); + kfree(mm->free_tree); } EXPORT_SYMBOL(drm_buddy_fini); @@ -383,7 +415,7 @@ static int split_block(struct drm_buddy *mm, clear_reset(block); } - mark_split(block); + mark_split(mm, block); return 0; } @@ -412,7 +444,7 @@ EXPORT_SYMBOL(drm_get_buddy); * @is_clear: blocks clear state * * Reset the clear state based on @is_clear value for each block - * in the freelist. + * in the freetree. */ void drm_buddy_reset_clear(struct drm_buddy *mm, bool is_clear) { @@ -431,9 +463,9 @@ void drm_buddy_reset_clear(struct drm_buddy *mm, bool is_clear) } for (i = 0; i <= mm->max_order; ++i) { - struct drm_buddy_block *block; + struct drm_buddy_block *block, *tmp; - list_for_each_entry_reverse(block, &mm->free_list[i], link) { + rbtree_postorder_for_each_entry_safe(block, tmp, &mm->free_tree[i], rb) { if (is_clear != drm_buddy_block_is_clear(block)) { if (is_clear) { mark_cleared(block); @@ -639,14 +671,18 @@ get_maxblock(struct drm_buddy *mm, unsigned int order, unsigned int i; for (i = order; i <= mm->max_order; ++i) { + struct rb_node *iter = rb_last(&mm->free_tree[i]); struct drm_buddy_block *tmp_block; - list_for_each_entry_reverse(tmp_block, &mm->free_list[i], link) { - if (block_incompatible(tmp_block, flags)) - continue; + while (iter) { + tmp_block = rbtree_get_free_block(iter); - block = tmp_block; - break; + if (!block_incompatible(tmp_block, flags)) { + block = tmp_block; + break; + } + + iter = rb_prev(iter); } if (!block) @@ -667,7 +703,7 @@ get_maxblock(struct drm_buddy *mm, unsigned int order, } static struct drm_buddy_block * -alloc_from_freelist(struct drm_buddy *mm, +alloc_from_freetree(struct drm_buddy *mm, unsigned int order, unsigned long flags) { @@ -682,14 +718,18 @@ alloc_from_freelist(struct drm_buddy *mm, tmp = drm_buddy_block_order(block); } else { for (tmp = order; tmp <= mm->max_order; ++tmp) { + struct rb_node *iter = rb_last(&mm->free_tree[tmp]); struct drm_buddy_block *tmp_block; - list_for_each_entry_reverse(tmp_block, &mm->free_list[tmp], link) { - if (block_incompatible(tmp_block, flags)) - continue; + while (iter) { + tmp_block = rbtree_get_free_block(iter); - block = tmp_block; - break; + if (!block_incompatible(tmp_block, flags)) { + block = tmp_block; + break; + } + + iter = rb_prev(iter); } if (block) @@ -700,13 +740,9 @@ alloc_from_freelist(struct drm_buddy *mm, if (!block) { /* Fallback method */ for (tmp = order; tmp <= mm->max_order; ++tmp) { - if (!list_empty(&mm->free_list[tmp])) { - block = list_last_entry(&mm->free_list[tmp], - struct drm_buddy_block, - link); - if (block) - break; - } + block = rbtree_last_entry(mm, tmp); + if (block) + break; } if (!block) @@ -771,7 +807,7 @@ static int __alloc_range(struct drm_buddy *mm, if (contains(start, end, block_start, block_end)) { if (drm_buddy_block_is_free(block)) { - mark_allocated(block); + mark_allocated(mm, block); total_allocated += drm_buddy_block_size(mm, block); mm->avail -= drm_buddy_block_size(mm, block); if (drm_buddy_block_is_clear(block)) @@ -849,8 +885,8 @@ static int __alloc_contig_try_harder(struct drm_buddy *mm, { u64 rhs_offset, lhs_offset, lhs_size, filled; struct drm_buddy_block *block; - struct list_head *list; LIST_HEAD(blocks_lhs); + struct rb_node *iter; unsigned long pages; unsigned int order; u64 modify_size; @@ -862,11 +898,14 @@ static int __alloc_contig_try_harder(struct drm_buddy *mm, if (order == 0) return -ENOSPC; - list = &mm->free_list[order]; - if (list_empty(list)) + if (rbtree_is_empty(mm, order)) return -ENOSPC; - list_for_each_entry_reverse(block, list, link) { + iter = rb_last(&mm->free_tree[order]); + + while (iter) { + block = rbtree_get_free_block(iter); + /* Allocate blocks traversing RHS */ rhs_offset = drm_buddy_block_offset(block); err = __drm_buddy_alloc_range(mm, rhs_offset, size, @@ -891,6 +930,8 @@ static int __alloc_contig_try_harder(struct drm_buddy *mm, } /* Free blocks for the next iteration */ drm_buddy_free_list_internal(mm, blocks); + + iter = rb_prev(iter); } return -ENOSPC; @@ -976,7 +1017,7 @@ int drm_buddy_block_trim(struct drm_buddy *mm, list_add(&block->tmp_link, &dfs); err = __alloc_range(mm, &dfs, new_start, new_size, blocks, NULL); if (err) { - mark_allocated(block); + mark_allocated(mm, block); mm->avail -= drm_buddy_block_size(mm, block); if (drm_buddy_block_is_clear(block)) mm->clear_avail -= drm_buddy_block_size(mm, block); @@ -999,8 +1040,8 @@ __drm_buddy_alloc_blocks(struct drm_buddy *mm, return __drm_buddy_alloc_range_bias(mm, start, end, order, flags); else - /* Allocate from freelist */ - return alloc_from_freelist(mm, order, flags); + /* Allocate from freetree */ + return alloc_from_freetree(mm, order, flags); } /** @@ -1017,8 +1058,8 @@ __drm_buddy_alloc_blocks(struct drm_buddy *mm, * alloc_range_bias() called on range limitations, which traverses * the tree and returns the desired block. * - * alloc_from_freelist() called when *no* range restrictions - * are enforced, which picks the block from the freelist. + * alloc_from_freetree() called when *no* range restrictions + * are enforced, which picks the block from the freetree. * * Returns: * 0 on success, error code on failure. @@ -1120,7 +1161,7 @@ int drm_buddy_alloc_blocks(struct drm_buddy *mm, } } while (1); - mark_allocated(block); + mark_allocated(mm, block); mm->avail -= drm_buddy_block_size(mm, block); if (drm_buddy_block_is_clear(block)) mm->clear_avail -= drm_buddy_block_size(mm, block); @@ -1201,10 +1242,10 @@ void drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p) mm->chunk_size >> 10, mm->size >> 20, mm->avail >> 20, mm->clear_avail >> 20); for (order = mm->max_order; order >= 0; order--) { - struct drm_buddy_block *block; + struct drm_buddy_block *block, *tmp; u64 count = 0, free; - list_for_each_entry(block, &mm->free_list[order], link) { + rbtree_postorder_for_each_entry_safe(block, tmp, &mm->free_tree[order], rb) { BUG_ON(!drm_buddy_block_is_free(block)); count++; } diff --git a/include/drm/drm_buddy.h b/include/drm/drm_buddy.h index 513837632b7d3..9ee105d4309f4 100644 --- a/include/drm/drm_buddy.h +++ b/include/drm/drm_buddy.h @@ -10,6 +10,7 @@ #include #include #include +#include #include @@ -53,7 +54,11 @@ struct drm_buddy_block { * a list, if so desired. As soon as the block is freed with * drm_buddy_free* ownership is given back to the mm. */ - struct list_head link; + union { + struct rb_node rb; + struct list_head link; + }; + struct list_head tmp_link; }; @@ -68,7 +73,7 @@ struct drm_buddy_block { */ struct drm_buddy { /* Maintain a free list for each order. */ - struct list_head *free_list; + struct rb_root *free_tree; /* * Maintain explicit binary tree(s) to track the allocation of the @@ -94,7 +99,7 @@ struct drm_buddy { }; static inline u64 -drm_buddy_block_offset(struct drm_buddy_block *block) +drm_buddy_block_offset(const struct drm_buddy_block *block) { return block->header & DRM_BUDDY_HEADER_OFFSET; } From 518aa49a88d4f95cbb87d0b35c83724ab6477abb Mon Sep 17 00:00:00 2001 From: Arunpravin Paneer Selvam Date: Mon, 6 Oct 2025 15:21:23 +0530 Subject: [PATCH 2620/2653] drm/buddy: Separate clear and dirty free block trees Maintain two separate RB trees per order - one for clear (zeroed) blocks and another for dirty (uncleared) blocks. This separation improves code clarity and makes it more obvious which tree is being searched during allocation. It also improves scalability and efficiency when searching for a specific type of block, avoiding unnecessary checks and making the allocator more predictable under fragmentation. The changes have been validated using the existing drm_buddy_test KUnit test cases, along with selected graphics workloads, to ensure correctness and avoid regressions. v2: Missed adding the suggested-by tag. Added it in v2. v3(Matthew): - Remove the double underscores from the internal functions. - Rename the internal functions to have less generic names. - Fix the error handling code. - Pass tree argument for the tree macro. - Use the existing dirty/free bit instead of new tree field. - Make free_trees[] instead of clear_tree and dirty_tree for more cleaner approach. v4: - A bug was reported by Intel CI and it is fixed by Matthew Auld. - Replace the get_root function with &mm->free_trees[tree][order] (Matthew) - Remove the unnecessary rbtree_is_empty() check (Matthew) - Remove the unnecessary get_tree_for_flags() function. - Rename get_tree_for_block() name with get_block_tree() for more clarity. v5(Jani Nikula): - Don't use static inline in .c files. - enum free_tree and enumerator names are quite generic for a header and usage and the whole enum should be an implementation detail. v6: - Rewrite the __force_merge() function using the rb_last() and rb_prev(). v7(Matthew): - Replace the open-coded tree iteration for loops with the for_each_free_tree() macro throughout the code. - Fixed out_free_roots to prevent double decrement of i, addressing potential crash. - Replaced enum drm_buddy_free_tree with unsigned int in for_each_free_tree loops. Cc: stable@vger.kernel.org Fixes: a68c7eaa7a8f ("drm/amdgpu: Enable clear page functionality") Signed-off-by: Arunpravin Paneer Selvam Suggested-by: Matthew Auld Reviewed-by: Matthew Auld Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4260 Link: https://lore.kernel.org/r/20251006095124.1663-2-Arunpravin.PaneerSelvam@amd.com --- drivers/gpu/drm/drm_buddy.c | 333 ++++++++++++++++++++---------------- include/drm/drm_buddy.h | 2 +- 2 files changed, 188 insertions(+), 147 deletions(-) diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c index c87210a06c318..f2c92902e4a30 100644 --- a/drivers/gpu/drm/drm_buddy.c +++ b/drivers/gpu/drm/drm_buddy.c @@ -12,9 +12,16 @@ #include +enum drm_buddy_free_tree { + DRM_BUDDY_CLEAR_TREE = 0, + DRM_BUDDY_DIRTY_TREE, + DRM_BUDDY_MAX_FREE_TREES, +}; + static struct kmem_cache *slab_blocks; -#define rbtree_get_free_block(node) rb_entry((node), struct drm_buddy_block, rb) +#define for_each_free_tree(tree) \ + for ((tree) = 0; (tree) < DRM_BUDDY_MAX_FREE_TREES; (tree)++) static struct drm_buddy_block *drm_block_alloc(struct drm_buddy *mm, struct drm_buddy_block *parent, @@ -45,6 +52,30 @@ static void drm_block_free(struct drm_buddy *mm, kmem_cache_free(slab_blocks, block); } +static enum drm_buddy_free_tree +get_block_tree(struct drm_buddy_block *block) +{ + return drm_buddy_block_is_clear(block) ? + DRM_BUDDY_CLEAR_TREE : DRM_BUDDY_DIRTY_TREE; +} + +static struct drm_buddy_block * +rbtree_get_free_block(const struct rb_node *node) +{ + return node ? rb_entry(node, struct drm_buddy_block, rb) : NULL; +} + +static struct drm_buddy_block * +rbtree_last_free_block(struct rb_root *root) +{ + return rbtree_get_free_block(rb_last(root)); +} + +static bool rbtree_is_empty(struct rb_root *root) +{ + return RB_EMPTY_ROOT(root); +} + static bool drm_buddy_block_offset_less(const struct drm_buddy_block *block, const struct drm_buddy_block *node) { @@ -59,37 +90,28 @@ static bool rbtree_block_offset_less(struct rb_node *block, } static void rbtree_insert(struct drm_buddy *mm, - struct drm_buddy_block *block) + struct drm_buddy_block *block, + enum drm_buddy_free_tree tree) { rb_add(&block->rb, - &mm->free_tree[drm_buddy_block_order(block)], + &mm->free_trees[tree][drm_buddy_block_order(block)], rbtree_block_offset_less); } static void rbtree_remove(struct drm_buddy *mm, struct drm_buddy_block *block) { + unsigned int order = drm_buddy_block_order(block); + enum drm_buddy_free_tree tree; struct rb_root *root; - root = &mm->free_tree[drm_buddy_block_order(block)]; - rb_erase(&block->rb, root); + tree = get_block_tree(block); + root = &mm->free_trees[tree][order]; + rb_erase(&block->rb, root); RB_CLEAR_NODE(&block->rb); } -static struct drm_buddy_block * -rbtree_last_entry(struct drm_buddy *mm, unsigned int order) -{ - struct rb_node *node = rb_last(&mm->free_tree[order]); - - return node ? rb_entry(node, struct drm_buddy_block, rb) : NULL; -} - -static bool rbtree_is_empty(struct drm_buddy *mm, unsigned int order) -{ - return RB_EMPTY_ROOT(&mm->free_tree[order]); -} - static void clear_reset(struct drm_buddy_block *block) { block->header &= ~DRM_BUDDY_HEADER_CLEAR; @@ -112,10 +134,13 @@ static void mark_allocated(struct drm_buddy *mm, static void mark_free(struct drm_buddy *mm, struct drm_buddy_block *block) { + enum drm_buddy_free_tree tree; + block->header &= ~DRM_BUDDY_HEADER_STATE; block->header |= DRM_BUDDY_FREE; - rbtree_insert(mm, block); + tree = get_block_tree(block); + rbtree_insert(mm, block, tree); } static void mark_split(struct drm_buddy *mm, @@ -201,7 +226,7 @@ static int __force_merge(struct drm_buddy *mm, u64 end, unsigned int min_order) { - unsigned int order; + unsigned int tree, order; int i; if (!min_order) @@ -210,45 +235,48 @@ static int __force_merge(struct drm_buddy *mm, if (min_order > mm->max_order) return -EINVAL; - for (i = min_order - 1; i >= 0; i--) { - struct rb_root *root = &mm->free_tree[i]; - struct rb_node *iter; + for_each_free_tree(tree) { + for (i = min_order - 1; i >= 0; i--) { + struct rb_node *iter = rb_last(&mm->free_trees[tree][i]); - iter = rb_last(root); - - while (iter) { - struct drm_buddy_block *block, *buddy; - u64 block_start, block_end; + while (iter) { + struct drm_buddy_block *block, *buddy; + u64 block_start, block_end; - block = rbtree_get_free_block(iter); - iter = rb_prev(iter); + block = rbtree_get_free_block(iter); + iter = rb_prev(iter); - if (!block || !block->parent) - continue; + if (!block || !block->parent) + continue; - block_start = drm_buddy_block_offset(block); - block_end = block_start + drm_buddy_block_size(mm, block) - 1; + block_start = drm_buddy_block_offset(block); + block_end = block_start + drm_buddy_block_size(mm, block) - 1; - if (!contains(start, end, block_start, block_end)) - continue; + if (!contains(start, end, block_start, block_end)) + continue; - buddy = __get_buddy(block); - if (!drm_buddy_block_is_free(buddy)) - continue; + buddy = __get_buddy(block); + if (!drm_buddy_block_is_free(buddy)) + continue; - WARN_ON(drm_buddy_block_is_clear(block) == - drm_buddy_block_is_clear(buddy)); + WARN_ON(drm_buddy_block_is_clear(block) == + drm_buddy_block_is_clear(buddy)); - if (iter == &buddy->rb) - iter = rb_prev(iter); + /* + * Advance to the next node when the current node is the buddy, + * as freeing the block will also remove its buddy from the tree. + */ + if (iter == &buddy->rb) + iter = rb_prev(iter); - rbtree_remove(mm, block); - if (drm_buddy_block_is_clear(block)) - mm->clear_avail -= drm_buddy_block_size(mm, block); + rbtree_remove(mm, block); + if (drm_buddy_block_is_clear(block)) + mm->clear_avail -= drm_buddy_block_size(mm, block); - order = __drm_buddy_free(mm, block, true); - if (order >= min_order) - return 0; + order = __drm_buddy_free(mm, block, true); + if (order >= min_order) + return 0; + } } } @@ -269,7 +297,7 @@ static int __force_merge(struct drm_buddy *mm, */ int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) { - unsigned int i; + unsigned int i, j, root_count = 0; u64 offset = 0; if (size < chunk_size) @@ -291,14 +319,22 @@ int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) BUG_ON(mm->max_order > DRM_BUDDY_MAX_ORDER); - mm->free_tree = kmalloc_array(mm->max_order + 1, - sizeof(struct rb_root), - GFP_KERNEL); - if (!mm->free_tree) + mm->free_trees = kmalloc_array(DRM_BUDDY_MAX_FREE_TREES, + sizeof(*mm->free_trees), + GFP_KERNEL); + if (!mm->free_trees) return -ENOMEM; - for (i = 0; i <= mm->max_order; ++i) - mm->free_tree[i] = RB_ROOT; + for_each_free_tree(i) { + mm->free_trees[i] = kmalloc_array(mm->max_order + 1, + sizeof(struct rb_root), + GFP_KERNEL); + if (!mm->free_trees[i]) + goto out_free_tree; + + for (j = 0; j <= mm->max_order; ++j) + mm->free_trees[i][j] = RB_ROOT; + } mm->n_roots = hweight64(size); @@ -308,8 +344,6 @@ int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) if (!mm->roots) goto out_free_tree; - i = 0; - /* * Split into power-of-two blocks, in case we are given a size that is * not itself a power-of-two. @@ -328,24 +362,26 @@ int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) mark_free(mm, root); - BUG_ON(i > mm->max_order); + BUG_ON(root_count > mm->max_order); BUG_ON(drm_buddy_block_size(mm, root) < chunk_size); - mm->roots[i] = root; + mm->roots[root_count] = root; offset += root_size; size -= root_size; - i++; + root_count++; } while (size); return 0; out_free_roots: - while (i--) - drm_block_free(mm, mm->roots[i]); + while (root_count--) + drm_block_free(mm, mm->roots[root_count]); kfree(mm->roots); out_free_tree: - kfree(mm->free_tree); + while (i--) + kfree(mm->free_trees[i]); + kfree(mm->free_trees); return -ENOMEM; } EXPORT_SYMBOL(drm_buddy_init); @@ -381,8 +417,9 @@ void drm_buddy_fini(struct drm_buddy *mm) WARN_ON(mm->avail != mm->size); + for_each_free_tree(i) + kfree(mm->free_trees[i]); kfree(mm->roots); - kfree(mm->free_tree); } EXPORT_SYMBOL(drm_buddy_fini); @@ -406,8 +443,7 @@ static int split_block(struct drm_buddy *mm, return -ENOMEM; } - mark_free(mm, block->left); - mark_free(mm, block->right); + mark_split(mm, block); if (drm_buddy_block_is_clear(block)) { mark_cleared(block->left); @@ -415,7 +451,8 @@ static int split_block(struct drm_buddy *mm, clear_reset(block); } - mark_split(mm, block); + mark_free(mm, block->left); + mark_free(mm, block->right); return 0; } @@ -448,6 +485,7 @@ EXPORT_SYMBOL(drm_get_buddy); */ void drm_buddy_reset_clear(struct drm_buddy *mm, bool is_clear) { + enum drm_buddy_free_tree src_tree, dst_tree; u64 root_size, size, start; unsigned int order; int i; @@ -462,19 +500,24 @@ void drm_buddy_reset_clear(struct drm_buddy *mm, bool is_clear) size -= root_size; } + src_tree = is_clear ? DRM_BUDDY_DIRTY_TREE : DRM_BUDDY_CLEAR_TREE; + dst_tree = is_clear ? DRM_BUDDY_CLEAR_TREE : DRM_BUDDY_DIRTY_TREE; + for (i = 0; i <= mm->max_order; ++i) { + struct rb_root *root = &mm->free_trees[src_tree][i]; struct drm_buddy_block *block, *tmp; - rbtree_postorder_for_each_entry_safe(block, tmp, &mm->free_tree[i], rb) { - if (is_clear != drm_buddy_block_is_clear(block)) { - if (is_clear) { - mark_cleared(block); - mm->clear_avail += drm_buddy_block_size(mm, block); - } else { - clear_reset(block); - mm->clear_avail -= drm_buddy_block_size(mm, block); - } + rbtree_postorder_for_each_entry_safe(block, tmp, root, rb) { + rbtree_remove(mm, block); + if (is_clear) { + mark_cleared(block); + mm->clear_avail += drm_buddy_block_size(mm, block); + } else { + clear_reset(block); + mm->clear_avail -= drm_buddy_block_size(mm, block); } + + rbtree_insert(mm, block, dst_tree); } } } @@ -664,27 +707,17 @@ __drm_buddy_alloc_range_bias(struct drm_buddy *mm, } static struct drm_buddy_block * -get_maxblock(struct drm_buddy *mm, unsigned int order, - unsigned long flags) +get_maxblock(struct drm_buddy *mm, + unsigned int order, + enum drm_buddy_free_tree tree) { struct drm_buddy_block *max_block = NULL, *block = NULL; + struct rb_root *root; unsigned int i; for (i = order; i <= mm->max_order; ++i) { - struct rb_node *iter = rb_last(&mm->free_tree[i]); - struct drm_buddy_block *tmp_block; - - while (iter) { - tmp_block = rbtree_get_free_block(iter); - - if (!block_incompatible(tmp_block, flags)) { - block = tmp_block; - break; - } - - iter = rb_prev(iter); - } - + root = &mm->free_trees[tree][i]; + block = rbtree_last_free_block(root); if (!block) continue; @@ -708,39 +741,37 @@ alloc_from_freetree(struct drm_buddy *mm, unsigned long flags) { struct drm_buddy_block *block = NULL; + struct rb_root *root; + enum drm_buddy_free_tree tree; unsigned int tmp; int err; + tree = (flags & DRM_BUDDY_CLEAR_ALLOCATION) ? + DRM_BUDDY_CLEAR_TREE : DRM_BUDDY_DIRTY_TREE; + if (flags & DRM_BUDDY_TOPDOWN_ALLOCATION) { - block = get_maxblock(mm, order, flags); + block = get_maxblock(mm, order, tree); if (block) /* Store the obtained block order */ tmp = drm_buddy_block_order(block); } else { for (tmp = order; tmp <= mm->max_order; ++tmp) { - struct rb_node *iter = rb_last(&mm->free_tree[tmp]); - struct drm_buddy_block *tmp_block; - - while (iter) { - tmp_block = rbtree_get_free_block(iter); - - if (!block_incompatible(tmp_block, flags)) { - block = tmp_block; - break; - } - - iter = rb_prev(iter); - } - + /* Get RB tree root for this order and tree */ + root = &mm->free_trees[tree][tmp]; + block = rbtree_last_free_block(root); if (block) break; } } if (!block) { - /* Fallback method */ + /* Try allocating from the other tree */ + tree = (tree == DRM_BUDDY_CLEAR_TREE) ? + DRM_BUDDY_DIRTY_TREE : DRM_BUDDY_CLEAR_TREE; + for (tmp = order; tmp <= mm->max_order; ++tmp) { - block = rbtree_last_entry(mm, tmp); + root = &mm->free_trees[tree][tmp]; + block = rbtree_last_free_block(root); if (block) break; } @@ -885,10 +916,9 @@ static int __alloc_contig_try_harder(struct drm_buddy *mm, { u64 rhs_offset, lhs_offset, lhs_size, filled; struct drm_buddy_block *block; + unsigned int tree, order; LIST_HEAD(blocks_lhs); - struct rb_node *iter; unsigned long pages; - unsigned int order; u64 modify_size; int err; @@ -898,40 +928,45 @@ static int __alloc_contig_try_harder(struct drm_buddy *mm, if (order == 0) return -ENOSPC; - if (rbtree_is_empty(mm, order)) - return -ENOSPC; + for_each_free_tree(tree) { + struct rb_root *root; + struct rb_node *iter; - iter = rb_last(&mm->free_tree[order]); - - while (iter) { - block = rbtree_get_free_block(iter); - - /* Allocate blocks traversing RHS */ - rhs_offset = drm_buddy_block_offset(block); - err = __drm_buddy_alloc_range(mm, rhs_offset, size, - &filled, blocks); - if (!err || err != -ENOSPC) - return err; - - lhs_size = max((size - filled), min_block_size); - if (!IS_ALIGNED(lhs_size, min_block_size)) - lhs_size = round_up(lhs_size, min_block_size); - - /* Allocate blocks traversing LHS */ - lhs_offset = drm_buddy_block_offset(block) - lhs_size; - err = __drm_buddy_alloc_range(mm, lhs_offset, lhs_size, - NULL, &blocks_lhs); - if (!err) { - list_splice(&blocks_lhs, blocks); - return 0; - } else if (err != -ENOSPC) { + root = &mm->free_trees[tree][order]; + if (rbtree_is_empty(root)) + continue; + + iter = rb_last(root); + while (iter) { + block = rbtree_get_free_block(iter); + + /* Allocate blocks traversing RHS */ + rhs_offset = drm_buddy_block_offset(block); + err = __drm_buddy_alloc_range(mm, rhs_offset, size, + &filled, blocks); + if (!err || err != -ENOSPC) + return err; + + lhs_size = max((size - filled), min_block_size); + if (!IS_ALIGNED(lhs_size, min_block_size)) + lhs_size = round_up(lhs_size, min_block_size); + + /* Allocate blocks traversing LHS */ + lhs_offset = drm_buddy_block_offset(block) - lhs_size; + err = __drm_buddy_alloc_range(mm, lhs_offset, lhs_size, + NULL, &blocks_lhs); + if (!err) { + list_splice(&blocks_lhs, blocks); + return 0; + } else if (err != -ENOSPC) { + drm_buddy_free_list_internal(mm, blocks); + return err; + } + /* Free blocks for the next iteration */ drm_buddy_free_list_internal(mm, blocks); - return err; - } - /* Free blocks for the next iteration */ - drm_buddy_free_list_internal(mm, blocks); - iter = rb_prev(iter); + iter = rb_prev(iter); + } } return -ENOSPC; @@ -1243,11 +1278,17 @@ void drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p) for (order = mm->max_order; order >= 0; order--) { struct drm_buddy_block *block, *tmp; + struct rb_root *root; u64 count = 0, free; + unsigned int tree; + + for_each_free_tree(tree) { + root = &mm->free_trees[tree][order]; - rbtree_postorder_for_each_entry_safe(block, tmp, &mm->free_tree[order], rb) { - BUG_ON(!drm_buddy_block_is_free(block)); - count++; + rbtree_postorder_for_each_entry_safe(block, tmp, root, rb) { + BUG_ON(!drm_buddy_block_is_free(block)); + count++; + } } drm_printf(p, "order-%2d ", order); diff --git a/include/drm/drm_buddy.h b/include/drm/drm_buddy.h index 9ee105d4309f4..d7891d08f67a3 100644 --- a/include/drm/drm_buddy.h +++ b/include/drm/drm_buddy.h @@ -73,7 +73,7 @@ struct drm_buddy_block { */ struct drm_buddy { /* Maintain a free list for each order. */ - struct rb_root *free_tree; + struct rb_root **free_trees; /* * Maintain explicit binary tree(s) to track the allocation of the From df9b5b0a54f952021520fe9deb02b0699e9d891a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 7 Nov 2025 16:56:25 +0800 Subject: [PATCH 2621/2653] drm/amdkcl: test if range_overflows() is available It's caused by d507ae0dc83b7f43cdf6760b8f1a30aac4fc405a drm/buddy: Add start address support to trim function Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/backport_drm_buddy.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/overflow.m4 | 14 +++++++++++ include/kcl/kcl_overflow.h | 24 +++++++++++++++++++ 4 files changed, 40 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h b/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h index c5ccbc3a8741c..297561aba8334 100644 --- a/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h +++ b/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h @@ -3,5 +3,6 @@ #define _KCL_BACKPORT_DRM_BUDDY_H #include +#include #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a691bb2d0a0f8..115b823231b7b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -273,6 +273,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FILE_ERR AC_AMDGPU_DRM_FILE_CLIENT_NAME AC_AMDGPU_SIZE_MUL + AC_AMDGPU_RANGE_OVERFLOWS AC_AMDGPU_DRM_CRTC_HELPER_MODE_VALID_FIXED AC_AMDGPU_BIN_ATTRIBUTE AC_AMDGPU_DRMM_CGROUP_REGISTER_REGION diff --git a/drivers/gpu/drm/amd/dkms/m4/overflow.m4 b/drivers/gpu/drm/amd/dkms/m4/overflow.m4 index 7ee5a99374193..e62b784d85e4c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/overflow.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/overflow.m4 @@ -14,4 +14,18 @@ AC_DEFUN([AC_AMDGPU_SIZE_MUL], [ [size_mul() is available]) ]) ]) +]) + +AC_DEFUN([AC_AMDGPU_RANGE_OVERFLOWS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool ret; + ret = range_overflows(0, 0, 0); + ], [ + AC_DEFINE(HAVE_RANGE_OVERFLOWS, 1, + [range_overflows() is available]) + ]) + ]) ]) \ No newline at end of file diff --git a/include/kcl/kcl_overflow.h b/include/kcl/kcl_overflow.h index 6a0403d4c05ec..95a8a93d6a9f9 100644 --- a/include/kcl/kcl_overflow.h +++ b/include/kcl/kcl_overflow.h @@ -6,4 +6,28 @@ #ifndef HAVE_SIZE_MUL #define size_mul array_size #endif + +#ifndef HAVE_RANGE_OVERFLOWS +/** + * range_overflows() - Check if a range is out of bounds + * @start: Start of the range. + * @size: Size of the range. + * @max: Exclusive upper boundary. + * + * A strict check to determine if the range [@start, @start + @size) is + * invalid with respect to the allowable range [0, @max). Any range + * starting at or beyond @max is considered an overflow, even if @size is 0. + * + * Returns: true if the range is out of bounds. + */ +#define range_overflows(start, size, max) ({ \ + typeof(start) start__ = (start); \ + typeof(size) size__ = (size); \ + typeof(max) max__ = (max); \ + (void)(&start__ == &size__); \ + (void)(&start__ == &max__); \ + start__ >= max__ || size__ > max__ - start__; \ +}) #endif + +#endif // _KCL_OVERFLOW_H_ From f0463abdd8a1d2fa84235d2eb5e1f3d176e7ace9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 5 Jan 2026 17:50:39 +0800 Subject: [PATCH 2622/2653] drm/amdkcl: add fake rb_add function support It's caused by v6.17-rc6-1174-gc178e534fff1 drm/buddy: Optimize free block management with RB tree Signed-off-by: Bob Zhou Reviewed-by: Chengjun Yao --- drivers/gpu/drm/amd/dkms/backport_drm_buddy.h | 1 + include/kcl/kcl_rbtree.h | 25 +++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h b/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h index 297561aba8334..32e17b11c0a7b 100644 --- a/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h +++ b/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h @@ -4,5 +4,6 @@ #include #include +#include #endif diff --git a/include/kcl/kcl_rbtree.h b/include/kcl/kcl_rbtree.h index 6a0f687a0801e..7146de25b3f24 100644 --- a/include/kcl/kcl_rbtree.h +++ b/include/kcl/kcl_rbtree.h @@ -94,6 +94,31 @@ rb_add_cached(struct rb_node *node, struct rb_root_cached *tree, return leftmost ? node : NULL; } + +/** + * rb_add() - insert @node into @tree + * @node: node to insert + * @tree: tree to insert @node into + * @less: operator defining the (partial) node order + */ +static __always_inline void +rb_add(struct rb_node *node, struct rb_root *tree, + bool (*less)(struct rb_node *, const struct rb_node *)) +{ + struct rb_node **link = &tree->rb_node; + struct rb_node *parent = NULL; + + while (*link) { + parent = *link; + if (less(node, parent)) + link = &parent->rb_left; + else + link = &parent->rb_right; + } + + rb_link_node(node, parent, link); + rb_insert_color(node, tree); +} #endif #endif From 0a48359d8031754d5b8e616ded004b9caa08e13f Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Wed, 14 Jan 2026 10:37:59 +0800 Subject: [PATCH 2623/2653] drm/amdgpu/vcn4.0.3: implement DPG pause mode handling for VCN 4.0.3 For MI projects, when Dynamic Power Gating (DPG) is enabled, VCN reset operations should be performed with DPG in pause mode. Otherwise, the hardware may perform undesirable reset operations Reviewed-by: Alex Deucher Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 41 +++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index cb7123ec1a5d1..0ce85dbd7abb1 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -847,6 +847,7 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_vcn_inst *vinst, int inst_idx = vinst->inst; struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; + struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__PAUSE}; struct amdgpu_ring *ring; int vcn_inst, ret; uint32_t tmp; @@ -951,6 +952,9 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_vcn_inst *vinst, ring = &adev->vcn.inst[inst_idx].ring_enc[0]; + /* Pause dpg */ + vcn_v4_0_3_pause_dpg_mode(vinst, &state); + /* program the RB_BASE for ring buffer */ WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, lower_32_bits(ring->gpu_addr)); @@ -1360,9 +1364,13 @@ static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) int inst_idx = vinst->inst; uint32_t tmp; int vcn_inst; + struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; vcn_inst = GET_INST(VCN, inst_idx); + /* Unpause dpg */ + vcn_v4_0_3_pause_dpg_mode(vinst, &state); + /* Wait for power status to be 1 */ SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); @@ -1486,6 +1494,39 @@ static int vcn_v4_0_3_stop(struct amdgpu_vcn_inst *vinst) static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, struct dpg_pause_state *new_state) { + struct amdgpu_device *adev = vinst->adev; + int inst_idx = vinst->inst; + uint32_t reg_data = 0; + int ret_code; + + /* pause/unpause if state is changed */ + if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { + DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", + adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); + reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & + (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); + + if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { + ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); + + if (!ret_code) { + /* pause DPG */ + reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; + WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); + + /* wait for ACK */ + SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, + UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, + UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); + } + } else { + /* unpause dpg, no need to wait */ + reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; + WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); + } + adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; + } return 0; } From 199b5faec1e071774b1839a8c0c82ffcd9e0cbe2 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Tue, 20 Jan 2026 10:23:35 +0800 Subject: [PATCH 2624/2653] drm/amdgpu/vcn4.0.3: rework reset handling Resetting VCN resets the entire tile, including jpeg. When resetting the VCN, we need to ensure that JPEG data blocks are accessible and we also need to handle the JPEG queue. Add a helper function to restore the JPEG queue during the VCN reset. v2: split the jpeg helper in two, in the top helper we can stop the sched workqueues and attempt to wait for any outstanding fences. Then in the bottom helper, we can force completion, re-init the rings, and restart the sched workqueues (Alex) v3: merge patches 1 and 2 into one patch (Alex) Signed-off-by: Alex Deucher Signed-off-by: Jesse Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 10 ++- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 93 +++++++++++++++++++++++- 2 files changed, 100 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index aae7328973d18..274f29156a462 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -1145,13 +1145,21 @@ static int jpeg_v4_0_3_ring_reset(struct amdgpu_ring *ring, unsigned int vmid, struct amdgpu_fence *timedout_fence) { + struct amdgpu_device *adev = ring->adev; + struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; + int r; + if (amdgpu_sriov_vf(ring->adev)) return -EOPNOTSUPP; + /* take the vcn reset mutex here because resetting VCN will reset jpeg as well */ + mutex_lock(&vinst->engine_reset_mutex); amdgpu_ring_reset_helper_begin(ring, timedout_fence); jpeg_v4_0_3_core_stall_reset(ring); jpeg_v4_0_3_start_jrbc(ring); - return amdgpu_ring_reset_helper_end(ring, timedout_fence); + r = amdgpu_ring_reset_helper_end(ring, timedout_fence); + mutex_unlock(&vinst->engine_reset_mutex); + return r; } static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 0ce85dbd7abb1..dd247abce1ab0 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -1637,6 +1637,60 @@ static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring) } } +static int vcn_v4_0_3_reset_jpeg_pre_helper(struct amdgpu_device *adev, int inst) +{ + struct amdgpu_ring *ring; + uint32_t wait_seq = 0; + int i; + + for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { + ring = &adev->jpeg.inst[inst].ring_dec[i]; + + drm_sched_wqueue_stop(&ring->sched); + /* Get the last emitted fence sequence */ + wait_seq = atomic_read(&ring->fence_drv.last_seq); + if (wait_seq) + continue; + + /* if Jobs are still pending after timeout, + * We'll handle them in the bottom helper + */ + amdgpu_fence_wait_polling(ring, wait_seq, adev->video_timeout); + } + + return 0; +} + +static int vcn_v4_0_3_reset_jpeg_post_helper(struct amdgpu_device *adev, int inst) +{ + struct amdgpu_ring *ring; + int i, r = 0; + + for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { + ring = &adev->jpeg.inst[inst].ring_dec[i]; + /* Force completion of any remaining jobs */ + amdgpu_fence_driver_force_completion(ring); + + if (ring->use_doorbell) + WREG32_SOC15_OFFSET( + VCN, GET_INST(VCN, inst), + regVCN_JPEG_DB_CTRL, + (ring->pipe ? (ring->pipe - 0x15) : 0), + ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | + VCN_JPEG_DB_CTRL__EN_MASK); + + r = amdgpu_ring_test_helper(ring); + if (r) + return r; + + drm_sched_wqueue_start(&ring->sched); + + DRM_DEV_DEBUG(adev->dev, "JPEG ring %d (inst %d) restored and sched restarted\n", + i, inst); + } + return 0; +} + static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, unsigned int vmid, struct amdgpu_fence *timedout_fence) @@ -1645,7 +1699,19 @@ static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, int vcn_inst; struct amdgpu_device *adev = ring->adev; struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; + bool pg_state = false; + + /* take the vcn reset mutex here because resetting VCN will reset jpeg as well */ + mutex_lock(&vinst->engine_reset_mutex); + mutex_lock(&adev->jpeg.jpeg_pg_lock); + /* Ensure JPEG is powered on during reset if currently gated */ + if (adev->jpeg.cur_state == AMD_PG_STATE_GATE) { + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, + AMD_PG_STATE_UNGATE); + pg_state = true; + } + vcn_v4_0_3_reset_jpeg_pre_helper(adev, ring->me); amdgpu_ring_reset_helper_begin(ring, timedout_fence); vcn_inst = GET_INST(VCN, ring->me); @@ -1653,7 +1719,12 @@ static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, if (r) { DRM_DEV_ERROR(adev->dev, "VCN reset fail : %d\n", r); - return r; + /* Restore JPEG power gating state if it was originally gated */ + if (pg_state) + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, + AMD_PG_STATE_GATE); + mutex_unlock(&adev->jpeg.jpeg_pg_lock); + goto unlock; } /* This flag is not set for VF, assumed to be disabled always */ @@ -1662,7 +1733,25 @@ static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, vcn_v4_0_3_hw_init_inst(vinst); vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[ring->me].indirect_sram); - return amdgpu_ring_reset_helper_end(ring, timedout_fence); + r = amdgpu_ring_reset_helper_end(ring, timedout_fence); + if (r) { + if (pg_state) + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, + AMD_PG_STATE_GATE); + mutex_unlock(&adev->jpeg.jpeg_pg_lock); + goto unlock; + } + + r = vcn_v4_0_3_reset_jpeg_post_helper(adev, ring->me); + if (pg_state) + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, + AMD_PG_STATE_GATE); + mutex_unlock(&adev->jpeg.jpeg_pg_lock); + +unlock: + mutex_unlock(&vinst->engine_reset_mutex); + + return r; } static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = { From bbb4b049719efd4c05075f2838572373b15ec038 Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Wed, 14 Jan 2026 10:51:52 +0800 Subject: [PATCH 2625/2653] drm/amdgpu/vcn5.0.1: rework reset handling Resetting VCN resets the entire tile, including jpeg. When resetting the VCN, we need to ensure that JPEG data blocks are accessible and we also need to handle the JPEG queue. Add a helper function to restore the JPEG queue during the VCN reset. v2: split the jpeg helper in two, in the top helper we can stop the sched workqueues and attempt to wait for any outstanding fences. Then in the bottom helper, we can force completion, re-init the rings, and restart the sched workqueues (Alex) v3: merge patches 4 and 5 into one patch (Alex) Signed-off-by: Alex Deucher Signed-off-by: Jesse Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c | 11 ++- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 93 +++++++++++++++++++++++- 2 files changed, 101 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c index ab0bf880d3d8a..edecbfe66c79a 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c @@ -844,10 +844,19 @@ static int jpeg_v5_0_1_ring_reset(struct amdgpu_ring *ring, unsigned int vmid, struct amdgpu_fence *timedout_fence) { + struct amdgpu_device *adev = ring->adev; + struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; + int r; + + /* take the vcn reset mutex here because resetting VCN will reset jpeg as well */ + mutex_lock(&vinst->engine_reset_mutex); + amdgpu_ring_reset_helper_begin(ring, timedout_fence); jpeg_v5_0_1_core_stall_reset(ring); jpeg_v5_0_1_init_jrbc(ring); - return amdgpu_ring_reset_helper_end(ring, timedout_fence); + r = amdgpu_ring_reset_helper_end(ring, timedout_fence); + mutex_unlock(&vinst->engine_reset_mutex); + return r; } static const struct amd_ip_funcs jpeg_v5_0_1_ip_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c index 8bd457dea4cff..c28c6aff17aaa 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c @@ -1301,6 +1301,59 @@ static void vcn_v5_0_1_unified_ring_set_wptr(struct amdgpu_ring *ring) } } +static int vcn_v5_0_1_reset_jpeg_pre_helper(struct amdgpu_device *adev, int inst) +{ + struct amdgpu_ring *ring; + uint32_t wait_seq = 0; + int i; + + for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { + ring = &adev->jpeg.inst[inst].ring_dec[i]; + + drm_sched_wqueue_stop(&ring->sched); + wait_seq = atomic_read(&ring->fence_drv.last_seq); + if (wait_seq) + continue; + + /* if Jobs are still pending after timeout, + * We'll handle them in the bottom helper + */ + amdgpu_fence_wait_polling(ring, wait_seq, adev->video_timeout); + } + + return 0; +} + +static int vcn_v5_0_1_reset_jpeg_post_helper(struct amdgpu_device *adev, int inst) +{ + struct amdgpu_ring *ring; + int i, r = 0; + + for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { + ring = &adev->jpeg.inst[inst].ring_dec[i]; + /* Force completion of any remaining jobs */ + amdgpu_fence_driver_force_completion(ring); + + if (ring->use_doorbell) + WREG32_SOC15_OFFSET( + VCN, GET_INST(VCN, inst), + regVCN_JPEG_DB_CTRL, + (ring->pipe ? (ring->pipe - 0x15) : 0), + ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | + VCN_JPEG_DB_CTRL__EN_MASK); + + r = amdgpu_ring_test_helper(ring); + if (r) + return r; + + drm_sched_wqueue_start(&ring->sched); + + DRM_DEV_DEBUG(adev->dev, "JPEG ring %d (inst %d) restored and sched restarted\n", + i, inst); + } + return 0; +} + static int vcn_v5_0_1_ring_reset(struct amdgpu_ring *ring, unsigned int vmid, struct amdgpu_fence *timedout_fence) @@ -1309,6 +1362,18 @@ static int vcn_v5_0_1_ring_reset(struct amdgpu_ring *ring, int vcn_inst; struct amdgpu_device *adev = ring->adev; struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; + bool pg_state = false; + + /* take the vcn reset mutex here because resetting VCN will reset jpeg as well */ + mutex_lock(&vinst->engine_reset_mutex); + vcn_v5_0_1_reset_jpeg_pre_helper(adev, ring->me); + mutex_lock(&adev->jpeg.jpeg_pg_lock); + /* Ensure JPEG is powered on during reset if currently gated */ + if (adev->jpeg.cur_state == AMD_PG_STATE_GATE) { + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, + AMD_PG_STATE_UNGATE); + pg_state = true; + } amdgpu_ring_reset_helper_begin(ring, timedout_fence); @@ -1317,13 +1382,37 @@ static int vcn_v5_0_1_ring_reset(struct amdgpu_ring *ring, if (r) { DRM_DEV_ERROR(adev->dev, "VCN reset fail : %d\n", r); - return r; + /* Restore JPEG power gating state if it was originally gated */ + if (pg_state) + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, + AMD_PG_STATE_GATE); + mutex_unlock(&adev->jpeg.jpeg_pg_lock); + goto unlock; } vcn_v5_0_1_hw_init_inst(adev, ring->me); vcn_v5_0_1_start_dpg_mode(vinst, vinst->indirect_sram); - return amdgpu_ring_reset_helper_end(ring, timedout_fence); + r = amdgpu_ring_reset_helper_end(ring, timedout_fence); + if (r) { + if (pg_state) + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, + AMD_PG_STATE_GATE); + mutex_unlock(&adev->jpeg.jpeg_pg_lock); + goto unlock; + } + + if (pg_state) + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, + AMD_PG_STATE_GATE); + mutex_unlock(&adev->jpeg.jpeg_pg_lock); + + r = vcn_v5_0_1_reset_jpeg_post_helper(adev, ring->me); + +unlock: + mutex_unlock(&vinst->engine_reset_mutex); + + return r; } static const struct amdgpu_ring_funcs vcn_v5_0_1_unified_ring_vm_funcs = { From 4d5b06591095af558fa0e40967d5a249b798864d Mon Sep 17 00:00:00 2001 From: "Jesse.Zhang" Date: Tue, 27 Jan 2026 15:01:27 +0800 Subject: [PATCH 2626/2653] drm/amdgpu: Fix jpeg ring test order in vcn_v4_0_3 Fix the vcn reset sequence in vcn_v4_0_3_ring_reset() to restore JPEG power state and unlock the JPEG powergating mutex before running the JPEG ring post-reset helper. Fixes: c50beca39115 ("drm/amdgpu/vcn4.0.3: rework reset handling") Reviewed-by: Lijo Lazar Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index dd247abce1ab0..e78526a4e521e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -1742,11 +1742,11 @@ static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, goto unlock; } - r = vcn_v4_0_3_reset_jpeg_post_helper(adev, ring->me); if (pg_state) amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, AMD_PG_STATE_GATE); mutex_unlock(&adev->jpeg.jpeg_pg_lock); + r = vcn_v4_0_3_reset_jpeg_post_helper(adev, ring->me); unlock: mutex_unlock(&vinst->engine_reset_mutex); From c61fab057ed1a11ae68cb9ff5e7aa638c375fa6a Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Fri, 6 Feb 2026 13:49:06 +0800 Subject: [PATCH 2627/2653] drm/amdgpu: Wait for GFX idle before PTL state transition Ensure GFX engine is idle before switching PTL state to prevent register access violations and CP hang. This addresses the race condition where in-flight GPU commands could conflict with PTL state changes. Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 30ec29b4dde5a..151dc24f35b49 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1906,6 +1906,11 @@ int kfd_ptl_control(struct kfd_process_device *pdd, bool enable) if (adev->kfd.init_complete) amdgpu_amdkfd_stop_sched(adev, pdd->dev->node_id); + /* Wait for GFX to be idle before PTL operation */ + ret = amdgpu_device_ip_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GFX); + if (ret) + return -ETIMEDOUT; + ret = pdd->dev->kfd2kgd->ptl_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &pref_format1, From 55e416451f6135c197997c99a108a2f35a6c74b2 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 16 Jan 2026 10:17:59 +0530 Subject: [PATCH 2628/2653] drm/amdgpu: Avoid excessive dmesg log KIQ access is not guaranteed to work reliably under all reset situations. Avoid flooding dmesg with HDP flush failure messages. Signed-off-by: Lijo Lazar Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 3d24f9cd750a0..9a3e0ddf18f5d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -1260,7 +1260,8 @@ int amdgpu_kiq_hdp_flush(struct amdgpu_device *adev) failed_unlock: spin_unlock_irqrestore(&kiq->ring_lock, flags); failed_kiq_hdp_flush: - dev_err(adev->dev, "failed to flush HDP via KIQ\n"); + if (!amdgpu_in_reset(adev)) + dev_err(adev->dev, "failed to flush HDP via KIQ\n"); return r < 0 ? r : -EIO; } From c91dd7b271a790d0b5f229f30024b135d5d53a61 Mon Sep 17 00:00:00 2001 From: Victor Zhao Date: Wed, 4 Feb 2026 23:15:04 +0800 Subject: [PATCH 2629/2653] drm/amdgpu: avoid sdma ring reset in sriov sdma ring reset is not supported in SRIOV. kfd driver does not check reset mask, and could queue sdma ring reset during unmap_queues_cpsch. Avoid the ring reset for sriov. Signed-off-by: Victor Zhao Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index 8b8a04138711c..321310ba2c08e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c @@ -558,6 +558,9 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id, struct amdgpu_ring *gfx_ring = &sdma_instance->ring; struct amdgpu_ring *page_ring = &sdma_instance->page; + if (amdgpu_sriov_vf(adev)) + return -EOPNOTSUPP; + mutex_lock(&sdma_instance->engine_reset_mutex); if (!caller_handles_kernel_queues) { From e9a192f73cfc41a77e3b8733b17622221e9aade9 Mon Sep 17 00:00:00 2001 From: chong li Date: Fri, 28 Nov 2025 10:51:51 +0800 Subject: [PATCH 2630/2653] drm/amdgpu: fix mes packet params issue when flush hdp. v4: use func "amdgpu_gfx_get_hdp_flush_mask" to get ref_and_mask for gfx9 through gfx12. v3: Unify the get_ref_and_mask function in amdgpu_gfx_funcs, to support both GFX11 and earlier generations v2: place "get_ref_and_mask" in amdgpu_gfx_funcs instead of amdgpu_ring, since this function only assigns the cp entry. v1: both gfx ring and mes ring use cp0 to flush hdp, cause conflict. use function get_ref_and_mask to assign the cp entry. reassign mes to use cp8 instead. Signed-off-by: chong li Acked-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 34 ++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 4 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 13 +++++- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 21 +++------ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 21 +++------ drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 21 +++------ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 59 ++++++++++++++++++------- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 59 ++++++++++++++++++------- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 21 +++------ drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 21 +++------ 10 files changed, 160 insertions(+), 114 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 9a3e0ddf18f5d..04e95de4f315d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -1195,6 +1195,40 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint3 dev_err(adev->dev, "failed to write reg:%x\n", reg); } +void amdgpu_gfx_get_hdp_flush_mask(struct amdgpu_ring *ring, + uint32_t *hdp_flush_mask, uint32_t *reg_mem_engine) +{ + + if (!ring || !hdp_flush_mask || !reg_mem_engine) { + DRM_INFO("%s:invalid params\n", __func__); + return; + } + + const struct nbio_hdp_flush_reg *nbio_hf_reg = ring->adev->nbio.hdp_flush_reg; + + switch (ring->funcs->type) { + case AMDGPU_RING_TYPE_GFX: + *hdp_flush_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; + *reg_mem_engine = 1; /* pfp */ + break; + case AMDGPU_RING_TYPE_COMPUTE: + *hdp_flush_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; + *reg_mem_engine = 0; + break; + case AMDGPU_RING_TYPE_MES: + *hdp_flush_mask = nbio_hf_reg->ref_and_mask_cp8; + *reg_mem_engine = 0; + break; + case AMDGPU_RING_TYPE_KIQ: + *hdp_flush_mask = nbio_hf_reg->ref_and_mask_cp9; + *reg_mem_engine = 0; + break; + default: + DRM_ERROR("%s:unsupported ring type %d\n", __func__, ring->funcs->type); + return; + } +} + int amdgpu_kiq_hdp_flush(struct amdgpu_device *adev) { signed long r, cnt = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index c1523bdee992c..1acd6b9a88385 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -365,6 +365,8 @@ struct amdgpu_gfx_funcs { int num_xccs_per_xcp); int (*ih_node_to_logical_xcc)(struct amdgpu_device *adev, int ih_node); int (*get_xccs_per_xcp)(struct amdgpu_device *adev); + void (*get_hdp_flush_mask)(struct amdgpu_ring *ring, + uint32_t *ref_and_mask, uint32_t *reg_mem_engine); }; struct sq_work { @@ -626,6 +628,8 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry); uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id); void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id); +void amdgpu_gfx_get_hdp_flush_mask(struct amdgpu_ring *ring, + uint32_t *ref_and_mask, uint32_t *reg_mem_engine); int amdgpu_kiq_hdp_flush(struct amdgpu_device *adev); int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev); void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 9c182ce501af4..2af98e0013e76 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -530,11 +530,20 @@ int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, int amdgpu_mes_hdp_flush(struct amdgpu_device *adev) { - uint32_t hdp_flush_req_offset, hdp_flush_done_offset, ref_and_mask; + uint32_t hdp_flush_req_offset, hdp_flush_done_offset; + struct amdgpu_ring *mes_ring; + uint32_t ref_and_mask = 0, reg_mem_engine = 0; + if (!adev->gfx.funcs->get_hdp_flush_mask) { + dev_err(adev->dev, "mes hdp flush is not supported.\n"); + return -EINVAL; + } + + mes_ring = &adev->mes.ring[0]; hdp_flush_req_offset = adev->nbio.funcs->get_hdp_flush_req_offset(adev); hdp_flush_done_offset = adev->nbio.funcs->get_hdp_flush_done_offset(adev); - ref_and_mask = adev->nbio.hdp_flush_reg->ref_and_mask_cp0; + + adev->gfx.funcs->get_hdp_flush_mask(mes_ring, &ref_and_mask, ®_mem_engine); return amdgpu_mes_reg_write_reg_wait(adev, hdp_flush_req_offset, hdp_flush_done_offset, ref_and_mask, ref_and_mask); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index eac4317393dff..3ea96fe97be47 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4575,6 +4575,7 @@ static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, + .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, }; static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) @@ -8715,25 +8716,13 @@ static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; u32 ref_and_mask, reg_mem_engine; - const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; - if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { - switch (ring->me) { - case 1: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; - break; - case 2: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; - break; - default: - return; - } - reg_mem_engine = 0; - } else { - ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; - reg_mem_engine = 1; /* pfp */ + if (!adev->gfx.funcs->get_hdp_flush_mask) { + dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); + return; } + adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, adev->nbio.funcs->get_hdp_flush_req_offset(adev), adev->nbio.funcs->get_hdp_flush_done_offset(adev), diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 797d0562431b1..e5a41bcd66a9c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -1080,6 +1080,7 @@ static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk, .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info, + .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, }; static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) @@ -5832,25 +5833,13 @@ static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; u32 ref_and_mask, reg_mem_engine; - const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; - if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { - switch (ring->me) { - case 1: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; - break; - case 2: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; - break; - default: - return; - } - reg_mem_engine = 0; - } else { - ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; - reg_mem_engine = 1; /* pfp */ + if (!adev->gfx.funcs->get_hdp_flush_mask) { + dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); + return; } + adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, adev->nbio.funcs->get_hdp_flush_req_offset(adev), adev->nbio.funcs->get_hdp_flush_done_offset(adev), diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 8a424390dcc4c..e85c058fb871f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -937,6 +937,7 @@ static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, .get_gfx_shadow_info = &gfx_v12_0_get_gfx_shadow_info, + .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, }; static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) @@ -4388,25 +4389,13 @@ static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; u32 ref_and_mask, reg_mem_engine; - const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; - if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { - switch (ring->me) { - case 1: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; - break; - case 2: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; - break; - default: - return; - } - reg_mem_engine = 0; - } else { - ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; - reg_mem_engine = 1; /* pfp */ + if (!adev->gfx.funcs->get_hdp_flush_mask) { + dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); + return; } + adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, adev->nbio.funcs->get_hdp_flush_req_offset(adev), adev->nbio.funcs->get_hdp_flush_done_offset(adev), diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 66a4e4998106f..9c0bcf836b2ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2068,23 +2068,15 @@ static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { u32 ref_and_mask; - int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; + int usepfp; + struct amdgpu_device *adev = ring->adev; - if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { - switch (ring->me) { - case 1: - ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; - break; - case 2: - ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; - break; - default: - return; - } - } else { - ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; + if (!adev->gfx.funcs->get_hdp_flush_mask) { + dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); + return; } + adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, &usepfp); amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ WAIT_REG_MEM_FUNCTION(3) | /* == */ @@ -4075,12 +4067,49 @@ static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev, cik_srbm_select(adev, me, pipe, q, vm); } +/** + * gfx_v7_0_get_hdp_flush_mask - get the reference and mask for HDP flush + * + * @ring: amdgpu_ring structure holding ring information + * @ref_and_mask: pointer to store the reference and mask + * @reg_mem_engine: pointer to store the register memory engine + * + * Calculates the reference and mask for HDP flush based on the ring type and me. + */ +static void gfx_v7_0_get_hdp_flush_mask(struct amdgpu_ring *ring, + uint32_t *ref_and_mask, uint32_t *reg_mem_engine) +{ + if (!ring || !ref_and_mask || !reg_mem_engine) { + DRM_INFO("%s:invalid params\n", __func__); + return; + } + + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE || + ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { + switch (ring->me) { + case 1: + *ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; + break; + case 2: + *ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; + break; + default: + return; + } + *reg_mem_engine = 0; + } else { + *ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; + *reg_mem_engine = 1; + } +} + static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, .select_se_sh = &gfx_v7_0_select_se_sh, .read_wave_data = &gfx_v7_0_read_wave_data, .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs, - .select_me_pipe_q = &gfx_v7_0_select_me_pipe_q + .select_me_pipe_q = &gfx_v7_0_select_me_pipe_q, + .get_hdp_flush_mask = &gfx_v7_0_get_hdp_flush_mask, }; static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 58e7a4a2a880e..e831f3f80b07d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -5218,13 +5218,49 @@ static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id start + SQIND_WAVE_SGPRS_OFFSET, size, dst); } +/** + * gfx_v8_0_get_hdp_flush_mask - get the reference and mask for HDP flush + * + * @ring: amdgpu_ring structure holding ring information + * @ref_and_mask: pointer to store the reference and mask + * @reg_mem_engine: pointer to store the register memory engine + * + * Calculates the reference and mask for HDP flush based on the ring type and me. + */ +static void gfx_v8_0_get_hdp_flush_mask(struct amdgpu_ring *ring, + uint32_t *ref_and_mask, uint32_t *reg_mem_engine) +{ + if (!ring || !ref_and_mask || !reg_mem_engine) { + DRM_INFO("%s:invalid params\n", __func__); + return; + } + + if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) || + (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)) { + switch (ring->me) { + case 1: + *ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; + break; + case 2: + *ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; + break; + default: + return; + } + *reg_mem_engine = 0; + } else { + *ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; + *reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */ + } +} static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = { .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter, .select_se_sh = &gfx_v8_0_select_se_sh, .read_wave_data = &gfx_v8_0_read_wave_data, .read_wave_sgprs = &gfx_v8_0_read_wave_sgprs, - .select_me_pipe_q = &gfx_v8_0_select_me_pipe_q + .select_me_pipe_q = &gfx_v8_0_select_me_pipe_q, + .get_hdp_flush_mask = &gfx_v8_0_get_hdp_flush_mask, }; static void gfx_v8_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, @@ -6103,25 +6139,14 @@ static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { u32 ref_and_mask, reg_mem_engine; + struct amdgpu_device *adev = ring->adev; - if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) || - (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)) { - switch (ring->me) { - case 1: - ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; - break; - case 2: - ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; - break; - default: - return; - } - reg_mem_engine = 0; - } else { - ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; - reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */ + if (!adev->gfx.funcs->get_hdp_flush_mask) { + dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); + return; } + adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ WAIT_REG_MEM_FUNCTION(3) | /* == */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 0fb95b8e48910..8841b33bb1d84 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2004,6 +2004,7 @@ static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, + .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, }; const struct amdgpu_ras_block_hw_ops gfx_v9_0_ras_ops = { @@ -5482,25 +5483,13 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; u32 ref_and_mask, reg_mem_engine; - const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; - if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { - switch (ring->me) { - case 1: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; - break; - case 2: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; - break; - default: - return; - } - reg_mem_engine = 0; - } else { - ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; - reg_mem_engine = 1; /* pfp */ + if (!adev->gfx.funcs->get_hdp_flush_mask) { + dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); + return; } + adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, adev->nbio.funcs->get_hdp_flush_req_offset(adev), adev->nbio.funcs->get_hdp_flush_done_offset(adev), diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index ebf0956c0e433..0edd7d76e16a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -850,6 +850,7 @@ static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, .get_xccs_per_xcp = &gfx_v9_4_3_get_xccs_per_xcp, + .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, }; static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, @@ -2992,25 +2993,13 @@ static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; u32 ref_and_mask, reg_mem_engine; - const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; - if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { - switch (ring->me) { - case 1: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; - break; - case 2: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; - break; - default: - return; - } - reg_mem_engine = 0; - } else { - ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; - reg_mem_engine = 1; /* pfp */ + if (!adev->gfx.funcs->get_hdp_flush_mask) { + dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); + return; } + adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, adev->nbio.funcs->get_hdp_flush_req_offset(adev), adev->nbio.funcs->get_hdp_flush_done_offset(adev), From 1562589320b35bd1980df3fe8bfc2233aba09ecf Mon Sep 17 00:00:00 2001 From: Xiaogang Chen Date: Tue, 13 Jan 2026 20:45:14 -0600 Subject: [PATCH 2631/2653] drm/amdkfd: kfd driver supports hot unplug/replug amdgpu devices This patch allows kfd driver function correctly when AMD gpu devices got unplug/replug at run time. When an AMD gpu device got unplug kfd driver gracefully terminates existing kfd processes after stops all queues by sending SIGBUS to user process. After that user space can still use remaining AMD gpu devices. When all AMD gpu devices at system got removed kfd driver will not response new requests. Unplugged AMD gpu devices can be re-plugged. kfd driver will use added devices to function as usual. The purpose of this patch is having kfd driver behavior as expected during and after AMD gpu devices unplug/replug at run time. Signed-off-by: Xiaogang Chen Acked-by: Alex Deucher (cherry picked from commit a482d054b7e7c7f2a35161d79e6629fa0f7f29d1) Change-Id: Ie33ea428914708546f7f96a627747f01bc6fcfdd --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 5 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 11 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_device.c | 76 +++++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_events.c | 29 +++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 + drivers/gpu/drm/amd/amdkfd/kfd_process.c | 19 ++++++ drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 22 +++++++ 8 files changed, 164 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 70f5334775a6f..01e98fb523593 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -249,6 +249,11 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); } +void amdgpu_amdkfd_teardown_processes(struct amdgpu_device *adev) +{ + kgd2kfd_teardown_processes(adev); +} + void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc) { if (adev->kfd.dev) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 5b1021c9d0d13..0d33e251b9185 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -162,6 +162,7 @@ struct amdkfd_process_info { int amdgpu_amdkfd_init(void); void amdgpu_amdkfd_fini(void); +void amdgpu_amdkfd_teardown_processes(struct amdgpu_device *adev); void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc); int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc); @@ -507,6 +508,8 @@ int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd); bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id); bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, bool retry_fault); +void kgd2kfd_lock_kfd(void); +void kgd2kfd_teardown_processes(struct amdgpu_device *adev); #else static inline int kgd2kfd_init(void) @@ -619,5 +622,13 @@ static inline bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct return false; } +static inline void kgd2kfd_lock_kfd(void) +{ +} + +static inline void kgd2kfd_teardown_processes(struct amdgpu_device *adev) +{ +} + #endif #endif /* AMDGPU_AMDKFD_H_INCLUDED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 30492a76f999b..0a8fb9a085ded 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3687,6 +3687,7 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); amdgpu_amdkfd_suspend(adev, true); + amdgpu_amdkfd_teardown_processes(adev); amdgpu_userq_suspend(adev); /* Workaround for ASICs need to disable SMC first */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 784c28fbaddab..12b48aef094d9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -978,6 +978,9 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd) } kfree(kfd); + + /* after remove a kfd device unlock kfd driver */ + kgd2kfd_unlock_kfd(NULL); } int kgd2kfd_pre_reset(struct kfd_dev *kfd, @@ -1561,10 +1564,14 @@ int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd) return r; } +/* unlock a kfd dev or kfd driver */ void kgd2kfd_unlock_kfd(struct kfd_dev *kfd) { mutex_lock(&kfd_processes_mutex); - --kfd->kfd_dev_lock; + if (kfd) + --kfd->kfd_dev_lock; + else + --kfd_locked; mutex_unlock(&kfd_processes_mutex); } @@ -1728,6 +1735,73 @@ bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entr return false; } +/* check if there is kfd process still uses adev */ +static bool kgd2kfd_check_device_idle(struct amdgpu_device *adev) +{ + struct kfd_process *p; + struct hlist_node *p_temp; + unsigned int temp; + struct kfd_node *dev; + + mutex_lock(&kfd_processes_mutex); + + if (hash_empty(kfd_processes_table)) { + mutex_unlock(&kfd_processes_mutex); + return true; + } + + /* check if there is device still use adev */ + hash_for_each_safe(kfd_processes_table, temp, p_temp, p, kfd_processes) { + for (int i = 0; i < p->n_pdds; i++) { + dev = p->pdds[i]->dev; + if (dev->adev == adev) { + mutex_unlock(&kfd_processes_mutex); + return false; + } + } + } + + mutex_unlock(&kfd_processes_mutex); + + return true; +} + +/** kgd2kfd_teardown_processes - gracefully tear down existing + * kfd processes that use adev + * + * @adev: amdgpu_device where kfd processes run on and will be + * teardown + * + */ +void kgd2kfd_teardown_processes(struct amdgpu_device *adev) +{ + struct hlist_node *p_temp; + struct kfd_process *p; + struct kfd_node *dev; + unsigned int temp; + + mutex_lock(&kfd_processes_mutex); + + if (hash_empty(kfd_processes_table)) { + mutex_unlock(&kfd_processes_mutex); + return; + } + + hash_for_each_safe(kfd_processes_table, temp, p_temp, p, kfd_processes) { + for (int i = 0; i < p->n_pdds; i++) { + dev = p->pdds[i]->dev; + if (dev->adev == adev) + kfd_signal_process_terminate_event(p); + } + } + + mutex_unlock(&kfd_processes_mutex); + + /* wait all kfd processes use adev terminate */ + while (!kgd2kfd_check_device_idle(adev)) + cond_resched(); +} + #if defined(CONFIG_DEBUG_FS) /* This function will send a package to HIQ to hang the HWS diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index 4be85487983a1..1b5396537ded1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -1392,3 +1392,32 @@ void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid) kfd_unref_process(p); } + +/* signal KFD_EVENT_TYPE_SIGNAL events from process p + * send signal SIGBUS to correspondent user space process + */ +void kfd_signal_process_terminate_event(struct kfd_process *p) +{ + struct kfd_event *ev; + u32 id; + + rcu_read_lock(); + + /* iterate from id 1 for KFD_EVENT_TYPE_SIGNAL events */ + id = 1; + idr_for_each_entry_continue(&p->event_idr, ev, id) + if (ev->type == KFD_EVENT_TYPE_SIGNAL) { + spin_lock(&ev->lock); + set_event(ev); + spin_unlock(&ev->lock); + } + + /* Send SIGBUS to p->lead_thread */ + dev_notice(kfd_device, + "Sending SIGBUS to process %d", + p->lead_thread->pid); + + send_sig(SIGBUS, p->lead_thread, 0); + + rcu_read_unlock(); +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index f5ec2c1c9266b..acc7ebbf40191 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1324,6 +1324,7 @@ static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev, } int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev); int kfd_numa_node_to_apic_id(int numa_node_id); +uint32_t kfd_gpu_node_num(void); /* Interrupts */ #define KFD_IRQ_FENCE_CLIENTID 0xff @@ -1683,6 +1684,7 @@ void kfd_signal_vm_fault_event(struct kfd_process_device *pdd, void kfd_signal_reset_event(struct kfd_node *dev); void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid); +void kfd_signal_process_terminate_event(struct kfd_process *p); static inline void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 359064f8e7736..1a72d272b8946 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -842,6 +842,12 @@ struct kfd_process *kfd_create_process(struct task_struct *thread) */ mutex_lock(&kfd_processes_mutex); + if (kfd_gpu_node_num() <= 0) { + pr_warn("no gpu node! Cannot create KFD process"); + process = ERR_PTR(-EINVAL); + goto out; + } + if (kfd_is_locked(NULL)) { pr_debug("KFD is locked! Cannot create process"); process = ERR_PTR(-EINVAL); @@ -1184,7 +1190,15 @@ static void kfd_process_wq_release(struct work_struct *work) if (ef) dma_fence_signal(ef); +<<<<<<< HEAD (4d5b06 drm/amdgpu: Fix jpeg ring test order in vcn_v4_0_3) kfd_process_remove_sysfs(p); +======= + if (p->context_id != KFD_CONTEXT_ID_PRIMARY) + kfd_process_free_id(p); + else + ida_destroy(&p->id_table); + +>>>>>>> CHANGE (a482d0 drm/amdkfd: kfd driver supports hot unplug/replug amdgpu dev) kfd_debugfs_remove_process(p); kfd_process_kunmap_signal_bo(p); @@ -1200,6 +1214,11 @@ static void kfd_process_wq_release(struct work_struct *work) put_task_struct(p->lead_thread); + /* the last step is removing process entries under /sys + * to indicate the process has been terminated. + */ + kfd_process_remove_sysfs(p); + kfree(p); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 185ca078c8f3c..5fea0a34c6596 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -2424,6 +2424,28 @@ int kfd_numa_node_to_apic_id(int numa_node_id) return kfd_cpumask_to_apic_id(cpumask_of_node(numa_node_id)); } +/* kfd_gpu_node_num - Return kfd gpu node number at system */ +uint32_t kfd_gpu_node_num(void) +{ + struct kfd_node *dev; + u8 gpu_num = 0; + u8 id = 0; + + while (kfd_topology_enum_kfd_devices(id, &dev) == 0) { + if (!dev || kfd_devcgroup_check_permission(dev)) { + /* Skip non GPU devices and devices to which the + * current process have no access to + */ + id++; + continue; + } + id++; + gpu_num++; + } + + return gpu_num; +} + #if defined(CONFIG_DEBUG_FS) int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data) From e42b8e0d45c4b5e9d0bbe9e2d14919667928dc93 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Mon, 2 Feb 2026 13:17:39 +0800 Subject: [PATCH 2632/2653] drm/amdgpu: Protect GPU register accesses in powergated state in some paths Ungate GPU CG/PG in device_fini_hw and device_halt to protect GPU register accesses, e.g. GC registers are accessed in amdgpu_irq_disable_all() and amdgpu_fence_driver_hw_fini(). Signed-off-by: Yifan Zhang Acked-by: Alex Deucher Reviewed-by: Lijo Lazar (cherry picked from commit 33fe740db26e0c94791dde8b2926d3ab36c9e6ae) Change-Id: I09895beaff20b3caf125b15e17bc330392552393 --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 0a8fb9a085ded..028ce2a514645 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3683,9 +3683,6 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) } } - amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); - amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); - amdgpu_amdkfd_suspend(adev, true); amdgpu_amdkfd_teardown_processes(adev); amdgpu_userq_suspend(adev); @@ -5084,6 +5081,9 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) amdgpu_virt_fini_data_exchange(adev); } + amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); + amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); + /* disable all interrupts */ amdgpu_irq_disable_all(adev); if (adev->mode_info.mode_config_initialized) { @@ -7540,6 +7540,9 @@ void amdgpu_device_halt(struct amdgpu_device *adev) amdgpu_xcp_dev_unplug(adev); drm_dev_unplug(ddev); + amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); + amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); + amdgpu_irq_disable_all(adev); amdgpu_fence_driver_hw_fini(adev); From ff677bf7b07ed7c31c229aae99ba14c883720d96 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 10 Feb 2026 05:12:46 -0500 Subject: [PATCH 2633/2653] Revert "drm/amdgpu: Wait for GFX idle before PTL state transition" This reverts commit c61fab057ed1a11ae68cb9ff5e7aa638c375fa6a. Reason for revert: revert the patch as it causes performance drop,tested by CE team. revert this patch requested by management team. Change-Id: I0db3f9f819554566e259bbb1292e7690db958ced --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 151dc24f35b49..30ec29b4dde5a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1906,11 +1906,6 @@ int kfd_ptl_control(struct kfd_process_device *pdd, bool enable) if (adev->kfd.init_complete) amdgpu_amdkfd_stop_sched(adev, pdd->dev->node_id); - /* Wait for GFX to be idle before PTL operation */ - ret = amdgpu_device_ip_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GFX); - if (ret) - return -ETIMEDOUT; - ret = pdd->dev->kfd2kgd->ptl_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &pref_format1, From e27c484e17682a47b8f41608ebf193c885f1ba6d Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Thu, 22 Jan 2026 16:25:16 +0800 Subject: [PATCH 2634/2653] drm/amdgpu: Refactor PTL control into public API and internal implementation Separate the PTL (Peak Tops Limiter) control logic into a stable public API layer and an internal implementation layer. Signed-off-by: Perry Yuan Suggested-by: Alex Deucher Reviewed-by: Yifan Zhang --- .../drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 87 +++++++++++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 +- 4 files changed, 54 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c index a6058a1c5a3e1..63c0b2992ea38 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c @@ -556,7 +556,7 @@ static uint32_t kgd_v9_4_3_ptl_ctrl(struct amdgpu_device *adev, enum amdgpu_ptl_fmt *fmt1, enum amdgpu_ptl_fmt *fmt2) { - return psp_performance_monitor_hw(&adev->psp, cmd, + return amdgpu_ptl_perf_monitor_ctrl(adev, cmd, ptl_state, fmt1, fmt2); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 62414b97a50e3..bec08e269eefe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1242,15 +1242,52 @@ static int psp_ptl_fmt_verify(struct psp_context *psp, enum amdgpu_ptl_fmt fmt, return 0; } -int psp_performance_monitor_hw(struct psp_context *psp, u32 req_code, - uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2) +static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, + uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2) { struct psp_gfx_cmd_resp *cmd; - struct amdgpu_device *adev = psp->adev; + int ret; + + cmd = acquire_psp_cmd_buf(psp); + + cmd->cmd_id = GFX_CMD_ID_PERF_HW; + cmd->cmd.cmd_req_perf_hw.req = req_code; + cmd->cmd.cmd_req_perf_hw.ptl_state = *ptl_state; + cmd->cmd.cmd_req_perf_hw.pref_format1 = *fmt1; + cmd->cmd.cmd_req_perf_hw.pref_format2 = *fmt2; + + ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); + if (ret) + goto out; + + /* Parse response */ + switch (req_code) { + case PSP_PTL_PERF_MON_QUERY: + *ptl_state = cmd->resp.uresp.perf_hw_info.ptl_state; + *fmt1 = cmd->resp.uresp.perf_hw_info.pref_format1; + *fmt2 = cmd->resp.uresp.perf_hw_info.pref_format2; + break; + case PSP_PTL_PERF_MON_SET: + /* Update cached state only on success */ + psp->ptl_enabled = *ptl_state; + psp->ptl_fmt1 = *fmt1; + psp->ptl_fmt2 = *fmt2; + break; + } + +out: + release_psp_cmd_buf(psp); + return ret; +} + +int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, + uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2) +{ uint32_t ptl_fmt1, ptl_fmt2; + struct psp_context *psp; int ret; - if (!psp || !ptl_state || !fmt1 || !fmt2) + if (!adev || !ptl_state || !fmt1 || !fmt2) return -EINVAL; if (amdgpu_sriov_vf(adev)) { @@ -1263,10 +1300,13 @@ int psp_performance_monitor_hw(struct psp_context *psp, u32 req_code, return ret; } - if (amdgpu_ip_version(psp->adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) || + psp = &adev->psp; + + if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) || psp->sos.fw_version < 0x0036081a) return -EOPNOTSUPP; + /* Verify formats */ if (psp_ptl_fmt_verify(psp, *fmt1, &ptl_fmt1) || psp_ptl_fmt_verify(psp, *fmt2, &ptl_fmt2)) return -EINVAL; @@ -1280,34 +1320,7 @@ int psp_performance_monitor_hw(struct psp_context *psp, u32 req_code, psp->ptl_fmt2 == ptl_fmt2) return 0; - cmd = acquire_psp_cmd_buf(psp); - - cmd->cmd_id = GFX_CMD_ID_PERF_HW; - cmd->cmd.cmd_req_perf_hw.req = req_code; - cmd->cmd.cmd_req_perf_hw.ptl_state = *ptl_state; - cmd->cmd.cmd_req_perf_hw.pref_format1 = ptl_fmt1; - cmd->cmd.cmd_req_perf_hw.pref_format2 = ptl_fmt2; - - ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); - if (ret) - goto out; - - switch (req_code) { - case PSP_PTL_PERF_MON_QUERY: - *ptl_state = cmd->resp.uresp.perf_hw_info.ptl_state; - *fmt1 = cmd->resp.uresp.perf_hw_info.pref_format1; - *fmt2 = cmd->resp.uresp.perf_hw_info.pref_format2; - break; - case PSP_PTL_PERF_MON_SET: - psp->ptl_enabled = *ptl_state; - psp->ptl_fmt1 = ptl_fmt1; - psp->ptl_fmt2 = ptl_fmt2; - break; - } - -out: - release_psp_cmd_buf(psp); - return ret; + return psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); } static enum amdgpu_ptl_fmt str_to_ptl_fmt(const char *str) @@ -1367,7 +1380,7 @@ static ssize_t ptl_enable_store(struct device *dev, return count; } - ret = psp_performance_monitor_hw(psp, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); + ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); if (ret) { dev_err(adev->dev, "Failed to set PTL err = %d\n", ret); mutex_unlock(&psp->ptl_mutex); @@ -1387,7 +1400,7 @@ static ssize_t ptl_enable_show(struct device *dev, struct device_attribute *attr int ret; if (amdgpu_sriov_vf(adev)) { - ret = psp_performance_monitor_hw(psp, PSP_PTL_PERF_MON_QUERY, + ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_QUERY, &ptl_state, &fmt1, &fmt2); if (ret) return ret; @@ -1432,7 +1445,7 @@ static ssize_t ptl_format_store(struct device *dev, ptl_state = psp->ptl_enabled; fmt1 = fmt1_enum; fmt2 = fmt2_enum; - ret = psp_performance_monitor_hw(psp, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); + ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); if (ret) { dev_err(adev->dev, "Failed to update PTL err = %d\n", ret); mutex_unlock(&psp->ptl_mutex); @@ -1452,7 +1465,7 @@ static ssize_t ptl_format_show(struct device *dev, struct device_attribute *attr int ret; if (amdgpu_sriov_vf(adev)) { - ret = psp_performance_monitor_hw(psp, PSP_PTL_PERF_MON_QUERY, + ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_QUERY, &ptl_state, &fmt1, &fmt2); if (ret) return ret; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 4ca1e2a0fb889..6faf27546d2bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -630,7 +630,7 @@ int amdgpu_psp_reg_program_no_ring(struct psp_context *psp, uint32_t val, enum psp_reg_prog_id id); void amdgpu_psp_debugfs_init(struct amdgpu_device *adev); -int psp_performance_monitor_hw(struct psp_context *psp, u32 req_code, +int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, u32 *ptl_state, u32 *fmt1, u32 *fmt2); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 0edd7d76e16a4..56e3e8677ff71 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2415,8 +2415,8 @@ static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool sta } /* initialize PTL with default formats: GFX_FTYPE_I8 & GFX_FTYPE_BF16 */ - r = psp_performance_monitor_hw(&adev->psp, PSP_PTL_PERF_MON_SET, &ptl_state, - &fmt1, &fmt2); + r = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, + &fmt1, &fmt2); if (r) { if (adev->psp.ptl_hw_supported_state == AMDGPU_PTL_HW_UNINIT) adev->psp.ptl_hw_supported_state = AMDGPU_PTL_HW_NOT_SUPPORTED; From d5a51b9155aef1aece419df0b706d7287e40a89d Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 27 Jan 2026 16:09:51 +0800 Subject: [PATCH 2635/2653] drm/amdgpu: add new data types F8 and Vector for PTL Add F8 and VECTOR to amdgpu_ptl_fmt and PSP format mapping. Update PTL format strings and GFX format enum to keep PSP/KFD in sync. Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 8 ++++++++ drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 ++-- drivers/gpu/drm/amd/include/amdgpu_ptl.h | 6 +++++- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index bec08e269eefe..83a332a870716 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -56,6 +56,8 @@ static const char * const amdgpu_ptl_fmt_str[] = { [AMDGPU_PTL_FMT_BF16] = "BF16", [AMDGPU_PTL_FMT_F32] = "F32", [AMDGPU_PTL_FMT_F64] = "F64", + [AMDGPU_PTL_FMT_F8] = "F8", + [AMDGPU_PTL_FMT_VECTOR] = "VECTOR", [AMDGPU_PTL_FMT_INVALID] = "INVALID", }; @@ -1235,6 +1237,12 @@ static int psp_ptl_fmt_verify(struct psp_context *psp, enum amdgpu_ptl_fmt fmt, case AMDGPU_PTL_FMT_F64: *ptl_fmt = GFX_FTYPE_F64; break; + case AMDGPU_PTL_FMT_F8: + *ptl_fmt = GFX_FTYPE_F8; + break; + case AMDGPU_PTL_FMT_VECTOR: + *ptl_fmt = GFX_FTYPE_VECTOR; + break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 56e3e8677ff71..b5119c31f2620 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2407,8 +2407,8 @@ static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool sta return -EOPNOTSUPP; if (adev->psp.ptl_hw_supported_state == AMDGPU_PTL_HW_UNINIT) { - fmt1 = GFX_FTYPE_I8; - fmt2 = GFX_FTYPE_BF16; + fmt1 = GFX_FTYPE_VECTOR; + fmt2 = GFX_FTYPE_F8; } else { fmt1 = adev->psp.ptl_fmt1; fmt2 = adev->psp.ptl_fmt2; diff --git a/drivers/gpu/drm/amd/include/amdgpu_ptl.h b/drivers/gpu/drm/amd/include/amdgpu_ptl.h index 67d114ae9718a..235f826c9f153 100644 --- a/drivers/gpu/drm/amd/include/amdgpu_ptl.h +++ b/drivers/gpu/drm/amd/include/amdgpu_ptl.h @@ -29,7 +29,9 @@ enum amdgpu_ptl_fmt { AMDGPU_PTL_FMT_BF16 = 2, AMDGPU_PTL_FMT_F32 = 3, AMDGPU_PTL_FMT_F64 = 4, - AMDGPU_PTL_FMT_INVALID = 5, + AMDGPU_PTL_FMT_F8 = 5, + AMDGPU_PTL_FMT_VECTOR = 6, + AMDGPU_PTL_FMT_INVALID = 7, }; enum amdgpu_ptl_hw_supported_state { @@ -50,6 +52,8 @@ enum psp_ptl_format_type GFX_FTYPE_BF16 = 0x00000002, GFX_FTYPE_F32 = 0x00000003, GFX_FTYPE_F64 = 0x00000004, + GFX_FTYPE_F8 = 0x00000005, + GFX_FTYPE_VECTOR = 0x00000006, GFX_FTYPE_INVALID = 0xFFFFFFFF, }; From e637806823b45c15c57110bf15cd9934399f58a3 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Fri, 23 Jan 2026 16:25:46 +0800 Subject: [PATCH 2636/2653] drm/amdgpu: Track PTL disable requests by source Use a bitmap to track PTL disable requests from sysfs and profiler. PTL is only re-enabled once all sources have released their disable requests, avoiding premature enablement. Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 32 +++++++++++++++++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 ++ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 4 +++ drivers/gpu/drm/amd/include/amdgpu_ptl.h | 6 +++++ 4 files changed, 38 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 83a332a870716..c776167f2071a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1328,6 +1328,21 @@ int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, psp->ptl_fmt2 == ptl_fmt2) return 0; + /* If enabling PTL, check disable bitmap */ + if (req_code == PSP_PTL_PERF_MON_SET && *ptl_state == 1) { + if (!bitmap_empty(psp->disable_bitmap, + AMDGPU_PTL_DISABLE_MAX)) { + dev_dbg(adev->dev, + "PTL enable blocked: SYSFS=%d, PROFILER=%d (ref=%d)\n", + test_bit(AMDGPU_PTL_DISABLE_SYSFS, + psp->disable_bitmap), + test_bit(AMDGPU_PTL_DISABLE_PROFILER, + psp->disable_bitmap), + atomic_read(&psp->ptl_disable_ref)); + return 0; + } + } + return psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); } @@ -1364,9 +1379,10 @@ static ssize_t ptl_enable_store(struct device *dev, struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(ddev); struct psp_context *psp = &adev->psp; - bool enable, cur_enabled; uint32_t ptl_state, fmt1, fmt2; int ret; + bool enable; + bool bit_changed = false; mutex_lock(&psp->ptl_mutex); if (sysfs_streq(buf, "enabled") || sysfs_streq(buf, "1")) { @@ -1382,18 +1398,22 @@ static ssize_t ptl_enable_store(struct device *dev, fmt2 = psp->ptl_fmt2; ptl_state = enable ? 1 : 0; - cur_enabled = READ_ONCE(psp->ptl_enabled); - if (cur_enabled == enable) { - mutex_unlock(&psp->ptl_mutex); - return count; - } + if (enable) + bit_changed = test_and_clear_bit(AMDGPU_PTL_DISABLE_SYSFS, + psp->disable_bitmap); ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); if (ret) { dev_err(adev->dev, "Failed to set PTL err = %d\n", ret); + if (enable && bit_changed) + set_bit(AMDGPU_PTL_DISABLE_SYSFS, psp->disable_bitmap); mutex_unlock(&psp->ptl_mutex); return ret; } + + if (!enable) + set_bit(AMDGPU_PTL_DISABLE_SYSFS, psp->disable_bitmap); + mutex_unlock(&psp->ptl_mutex); return count; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 6faf27546d2bd..8833e9126c1af 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -32,6 +32,7 @@ #include "ta_rap_if.h" #include "ta_secureDisplay_if.h" #include "amdgpu_ptl.h" +#include #define PSP_FENCE_BUFFER_SIZE 0x1000 #define PSP_CMD_BUFFER_SIZE 0x1000 @@ -455,6 +456,7 @@ struct psp_context { atomic_t ptl_disable_ref; struct mutex ptl_mutex; enum amdgpu_ptl_hw_supported_state ptl_hw_supported_state; + DECLARE_BITMAP(disable_bitmap, AMDGPU_PTL_DISABLE_MAX); }; struct amdgpu_psp_funcs { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 30ec29b4dde5a..8a45126ba1187 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1941,6 +1941,8 @@ int kfd_ptl_disable_request(struct kfd_process_device *pdd, goto out; } } + + set_bit(AMDGPU_PTL_DISABLE_PROFILER, adev->psp.disable_bitmap); pdd->ptl_disable_req = true; out: @@ -1963,11 +1965,13 @@ int kfd_ptl_disable_release(struct kfd_process_device *pdd, goto out; if (atomic_dec_return(&adev->psp.ptl_disable_ref) == 0) { + clear_bit(AMDGPU_PTL_DISABLE_PROFILER, adev->psp.disable_bitmap); ret = kfd_ptl_control(pdd, true); if (ret) { atomic_inc(&adev->psp.ptl_disable_ref); dev_warn(pdd->dev->adev->dev, "failed to enable PTL\n"); + set_bit(AMDGPU_PTL_DISABLE_PROFILER, adev->psp.disable_bitmap); goto out; } } diff --git a/drivers/gpu/drm/amd/include/amdgpu_ptl.h b/drivers/gpu/drm/amd/include/amdgpu_ptl.h index 235f826c9f153..315476f4d560d 100644 --- a/drivers/gpu/drm/amd/include/amdgpu_ptl.h +++ b/drivers/gpu/drm/amd/include/amdgpu_ptl.h @@ -64,6 +64,12 @@ struct psp_ptl_perf_req { uint32_t pref_format2; }; +enum amdgpu_ptl_disable_source { + AMDGPU_PTL_DISABLE_SYSFS = 0, + AMDGPU_PTL_DISABLE_PROFILER, + AMDGPU_PTL_DISABLE_MAX, +}; + extern const struct attribute_group amdgpu_ptl_attr_group; int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev); void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev); From 114b298d8d8e5f3a364181571a94dcec30c741fc Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Sun, 25 Jan 2026 14:31:47 +0800 Subject: [PATCH 2637/2653] drm/amdgpu: add amdgpu.ptl module parameter for PTL control Add a new kernel module parameter 'amdgpu.ptl' to allow users to enable or disable PTL feature at driver loading time. Parameter values: *) 0 or -1: disable PTL (default) *) 1: enable PTL *) 2: permanently disable PTL Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 13 ++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 9 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 28 ++++++++++++++++++++++++- 5 files changed, 51 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 1c812d5aa3f87..6d1f4acab78e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -274,6 +274,7 @@ extern int amdgpu_rebar; extern int amdgpu_wbrf; extern int amdgpu_user_queue; +extern int amdgpu_ptl; #define AMDGPU_VM_MAX_NUM_CTX 4096 #define AMDGPU_SG_THRESHOLD (256*1024*1024) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 20f014166f1ea..3bcb7917384b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -248,6 +248,7 @@ int amdgpu_damage_clips = -1; /* auto */ int amdgpu_umsch_mm_fwlog; int amdgpu_rebar = -1; /* auto */ int amdgpu_user_queue = -1; +int amdgpu_ptl = -1; /* auto */ DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, "DRM_UT_CORE", @@ -1144,6 +1145,18 @@ module_param_named(rebar, amdgpu_rebar, int, 0444); MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)"); module_param_named(user_queue, amdgpu_user_queue, int, 0444); +/** + * DOC: ptl (int) + * Enable PTL feature at boot time. Possible values: + * + * - -1 = auto (ASIC specific default) + * - 0 = disable PTL (default) + * - 1 = enable PTL + * - 2 = permanently disable PTL (cannot be re-enabled at runtime) + */ +MODULE_PARM_DESC(ptl, "Enable PTL (-1 = auto, 0 = disable (default), 1 = enable, 2 = permanently disable)"); +module_param_named(ptl, amdgpu_ptl, int, 0444); + /* These devices are not supported by amdgpu. * They are supported by the mach64, r128, radeon drivers */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index c776167f2071a..391e440a6c481 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1310,6 +1310,9 @@ int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, psp = &adev->psp; + if (psp->permanently_disabled && *ptl_state == 1) + return 0; + if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) || psp->sos.fw_version < 0x0036081a) return -EOPNOTSUPP; @@ -1394,6 +1397,12 @@ static ssize_t ptl_enable_store(struct device *dev, return -EINVAL; } + /* Block enable when permanently disabled */ + if (psp->permanently_disabled) { + mutex_unlock(&psp->ptl_mutex); + return -EPERM; + } + fmt1 = psp->ptl_fmt1; fmt2 = psp->ptl_fmt2; ptl_state = enable ? 1 : 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 8833e9126c1af..e7257915698b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -457,6 +457,7 @@ struct psp_context { struct mutex ptl_mutex; enum amdgpu_ptl_hw_supported_state ptl_hw_supported_state; DECLARE_BITMAP(disable_bitmap, AMDGPU_PTL_DISABLE_MAX); + bool permanently_disabled; }; struct amdgpu_psp_funcs { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index b5119c31f2620..01e5422ccce2b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2434,6 +2434,32 @@ static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool sta return 0; } +static int gfx_v9_4_3_ptl_hw_init(struct amdgpu_device *adev) +{ + struct psp_context *psp = &adev->psp; + bool enable; + + switch (amdgpu_ptl) { + case 1: + enable = true; + break; + case 2: + /* Permanently disabled - cannot be re-enabled */ + enable = false; + psp->permanently_disabled = true; + break; + case -1: + case 0: + default: + enable = false; + break; + } + + gfx_v9_4_3_perf_monitor_ptl_init(adev, enable ? 1 : 0); + + return 0; +} + static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -2721,7 +2747,7 @@ static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) adev->gfx.ras->enable_watchdog_timer) adev->gfx.ras->enable_watchdog_timer(adev); - gfx_v9_4_3_perf_monitor_ptl_init(adev, 1); + gfx_v9_4_3_ptl_hw_init(adev); return 0; } From 9155d3d1808ff4b5965432f29ae41cf45411a106 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 10 Feb 2026 13:50:36 +0800 Subject: [PATCH 2638/2653] drm/amdgpu: check PSP response status in psp_ptl_invoke Add an explicit check on cmd->resp.status after psp_cmd_submit_buf() returns to ensure PTL state is only updated on actual success. Signed-off-by: Perry Yuan Reviewed-by: Lijo Lazar Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 391e440a6c481..dc991f847d216 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1268,6 +1268,18 @@ static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, if (ret) goto out; + /* + * Check response status explicitly to avoid + * updating cached PTL state with invalid data. + */ + if (cmd->resp.status) { + dev_err(psp->adev->dev, + "PTL command 0x%x failed, PSP response status: 0x%X\n", + req_code, cmd->resp.status); + ret = -EIO; + goto out; + } + /* Parse response */ switch (req_code) { case PSP_PTL_PERF_MON_QUERY: From 28f5e8a12bc919daca1e58edc8b6ab22b874e78a Mon Sep 17 00:00:00 2001 From: Jenny-Jing Liu Date: Wed, 11 Feb 2026 09:40:31 -0500 Subject: [PATCH 2639/2653] Revert "drm/amdkfd: kfd driver supports hot unplug/replug amdgpu devices" This reverts commit 1562589320b35bd1980df3fe8bfc2233aba09ecf. Reason for revert: Change-Id: If54b6c5f703eb136db61770d5ddafcba22bf4620 --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 5 -- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 11 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 - drivers/gpu/drm/amd/amdkfd/kfd_device.c | 76 +--------------------- drivers/gpu/drm/amd/amdkfd/kfd_events.c | 29 --------- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 - drivers/gpu/drm/amd/amdkfd/kfd_process.c | 19 ------ drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 22 ------- 8 files changed, 1 insertion(+), 164 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 01e98fb523593..70f5334775a6f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -249,11 +249,6 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); } -void amdgpu_amdkfd_teardown_processes(struct amdgpu_device *adev) -{ - kgd2kfd_teardown_processes(adev); -} - void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc) { if (adev->kfd.dev) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 0d33e251b9185..5b1021c9d0d13 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -162,7 +162,6 @@ struct amdkfd_process_info { int amdgpu_amdkfd_init(void); void amdgpu_amdkfd_fini(void); -void amdgpu_amdkfd_teardown_processes(struct amdgpu_device *adev); void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc); int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc); @@ -508,8 +507,6 @@ int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd); bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id); bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, bool retry_fault); -void kgd2kfd_lock_kfd(void); -void kgd2kfd_teardown_processes(struct amdgpu_device *adev); #else static inline int kgd2kfd_init(void) @@ -622,13 +619,5 @@ static inline bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct return false; } -static inline void kgd2kfd_lock_kfd(void) -{ -} - -static inline void kgd2kfd_teardown_processes(struct amdgpu_device *adev) -{ -} - #endif #endif /* AMDGPU_AMDKFD_H_INCLUDED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 028ce2a514645..db6c566030944 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3684,7 +3684,6 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) } amdgpu_amdkfd_suspend(adev, true); - amdgpu_amdkfd_teardown_processes(adev); amdgpu_userq_suspend(adev); /* Workaround for ASICs need to disable SMC first */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 12b48aef094d9..784c28fbaddab 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -978,9 +978,6 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd) } kfree(kfd); - - /* after remove a kfd device unlock kfd driver */ - kgd2kfd_unlock_kfd(NULL); } int kgd2kfd_pre_reset(struct kfd_dev *kfd, @@ -1564,14 +1561,10 @@ int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd) return r; } -/* unlock a kfd dev or kfd driver */ void kgd2kfd_unlock_kfd(struct kfd_dev *kfd) { mutex_lock(&kfd_processes_mutex); - if (kfd) - --kfd->kfd_dev_lock; - else - --kfd_locked; + --kfd->kfd_dev_lock; mutex_unlock(&kfd_processes_mutex); } @@ -1735,73 +1728,6 @@ bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entr return false; } -/* check if there is kfd process still uses adev */ -static bool kgd2kfd_check_device_idle(struct amdgpu_device *adev) -{ - struct kfd_process *p; - struct hlist_node *p_temp; - unsigned int temp; - struct kfd_node *dev; - - mutex_lock(&kfd_processes_mutex); - - if (hash_empty(kfd_processes_table)) { - mutex_unlock(&kfd_processes_mutex); - return true; - } - - /* check if there is device still use adev */ - hash_for_each_safe(kfd_processes_table, temp, p_temp, p, kfd_processes) { - for (int i = 0; i < p->n_pdds; i++) { - dev = p->pdds[i]->dev; - if (dev->adev == adev) { - mutex_unlock(&kfd_processes_mutex); - return false; - } - } - } - - mutex_unlock(&kfd_processes_mutex); - - return true; -} - -/** kgd2kfd_teardown_processes - gracefully tear down existing - * kfd processes that use adev - * - * @adev: amdgpu_device where kfd processes run on and will be - * teardown - * - */ -void kgd2kfd_teardown_processes(struct amdgpu_device *adev) -{ - struct hlist_node *p_temp; - struct kfd_process *p; - struct kfd_node *dev; - unsigned int temp; - - mutex_lock(&kfd_processes_mutex); - - if (hash_empty(kfd_processes_table)) { - mutex_unlock(&kfd_processes_mutex); - return; - } - - hash_for_each_safe(kfd_processes_table, temp, p_temp, p, kfd_processes) { - for (int i = 0; i < p->n_pdds; i++) { - dev = p->pdds[i]->dev; - if (dev->adev == adev) - kfd_signal_process_terminate_event(p); - } - } - - mutex_unlock(&kfd_processes_mutex); - - /* wait all kfd processes use adev terminate */ - while (!kgd2kfd_check_device_idle(adev)) - cond_resched(); -} - #if defined(CONFIG_DEBUG_FS) /* This function will send a package to HIQ to hang the HWS diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index 1b5396537ded1..4be85487983a1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -1392,32 +1392,3 @@ void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid) kfd_unref_process(p); } - -/* signal KFD_EVENT_TYPE_SIGNAL events from process p - * send signal SIGBUS to correspondent user space process - */ -void kfd_signal_process_terminate_event(struct kfd_process *p) -{ - struct kfd_event *ev; - u32 id; - - rcu_read_lock(); - - /* iterate from id 1 for KFD_EVENT_TYPE_SIGNAL events */ - id = 1; - idr_for_each_entry_continue(&p->event_idr, ev, id) - if (ev->type == KFD_EVENT_TYPE_SIGNAL) { - spin_lock(&ev->lock); - set_event(ev); - spin_unlock(&ev->lock); - } - - /* Send SIGBUS to p->lead_thread */ - dev_notice(kfd_device, - "Sending SIGBUS to process %d", - p->lead_thread->pid); - - send_sig(SIGBUS, p->lead_thread, 0); - - rcu_read_unlock(); -} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index acc7ebbf40191..f5ec2c1c9266b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1324,7 +1324,6 @@ static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev, } int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev); int kfd_numa_node_to_apic_id(int numa_node_id); -uint32_t kfd_gpu_node_num(void); /* Interrupts */ #define KFD_IRQ_FENCE_CLIENTID 0xff @@ -1684,7 +1683,6 @@ void kfd_signal_vm_fault_event(struct kfd_process_device *pdd, void kfd_signal_reset_event(struct kfd_node *dev); void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid); -void kfd_signal_process_terminate_event(struct kfd_process *p); static inline void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 1a72d272b8946..359064f8e7736 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -842,12 +842,6 @@ struct kfd_process *kfd_create_process(struct task_struct *thread) */ mutex_lock(&kfd_processes_mutex); - if (kfd_gpu_node_num() <= 0) { - pr_warn("no gpu node! Cannot create KFD process"); - process = ERR_PTR(-EINVAL); - goto out; - } - if (kfd_is_locked(NULL)) { pr_debug("KFD is locked! Cannot create process"); process = ERR_PTR(-EINVAL); @@ -1190,15 +1184,7 @@ static void kfd_process_wq_release(struct work_struct *work) if (ef) dma_fence_signal(ef); -<<<<<<< HEAD (4d5b06 drm/amdgpu: Fix jpeg ring test order in vcn_v4_0_3) kfd_process_remove_sysfs(p); -======= - if (p->context_id != KFD_CONTEXT_ID_PRIMARY) - kfd_process_free_id(p); - else - ida_destroy(&p->id_table); - ->>>>>>> CHANGE (a482d0 drm/amdkfd: kfd driver supports hot unplug/replug amdgpu dev) kfd_debugfs_remove_process(p); kfd_process_kunmap_signal_bo(p); @@ -1214,11 +1200,6 @@ static void kfd_process_wq_release(struct work_struct *work) put_task_struct(p->lead_thread); - /* the last step is removing process entries under /sys - * to indicate the process has been terminated. - */ - kfd_process_remove_sysfs(p); - kfree(p); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 5fea0a34c6596..185ca078c8f3c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -2424,28 +2424,6 @@ int kfd_numa_node_to_apic_id(int numa_node_id) return kfd_cpumask_to_apic_id(cpumask_of_node(numa_node_id)); } -/* kfd_gpu_node_num - Return kfd gpu node number at system */ -uint32_t kfd_gpu_node_num(void) -{ - struct kfd_node *dev; - u8 gpu_num = 0; - u8 id = 0; - - while (kfd_topology_enum_kfd_devices(id, &dev) == 0) { - if (!dev || kfd_devcgroup_check_permission(dev)) { - /* Skip non GPU devices and devices to which the - * current process have no access to - */ - id++; - continue; - } - id++; - gpu_num++; - } - - return gpu_num; -} - #if defined(CONFIG_DEBUG_FS) int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data) From dad072fb776b68fa490eab5125d503b64f8d4246 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Mon, 9 Feb 2026 18:54:45 +0100 Subject: [PATCH 2640/2653] drm/amdgpu: fix sync handling in amdgpu_dma_buf_move_notify MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Invalidating a dmabuf will impact other users of the shared BO. In the scenario where process A moves the BO, it needs to inform process B about the move and process B will need to update its page table. The commit fixes a synchronisation bug caused by the use of the ticket: it made amdgpu_vm_handle_moved behave as if updating the page table immediately was correct but in this case it's not. An example is the following scenario, with 2 GPUs and glxgears running on GPU0 and Xorg running on GPU1, on a system where P2P PCI isn't supported: glxgears: export linear buffer from GPU0 and import using GPU1 submit frame rendering to GPU0 submit tiled->linear blit Xorg: copy of linear buffer The sequence of jobs would be: drm_sched_job_run # GPU0, frame rendering drm_sched_job_queue # GPU0, blit drm_sched_job_done # GPU0, frame rendering drm_sched_job_run # GPU0, blit move linear buffer for GPU1 access # amdgpu_dma_buf_move_notify -> update pt # GPU0 It this point the blit job on GPU0 is still running and would likely produce a page fault. Cc: stable@vger.kernel.org Fixes: a448cb003edc ("drm/amdgpu: implement amdgpu_gem_prime_move_notify v2") Signed-off-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index f9022c5d74c1e..22adc2c0948cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -792,8 +792,15 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) r = dma_resv_reserve_fences(resv, 2); if (!r) r = amdgpu_vm_clear_freed(adev, vm, NULL); + + /* Don't pass 'ticket' to amdgpu_vm_handle_moved: we want the clear=true + * path to be used otherwise we might update the PT of another process + * while it's using the BO. + * With clear=true, amdgpu_vm_bo_update will sync to command submission + * from the same VM. + */ if (!r) - r = amdgpu_vm_handle_moved(adev, vm, ticket); + r = amdgpu_vm_handle_moved(adev, vm, NULL); if (r && r != -EBUSY) DRM_ERROR("Failed to invalidate VM page tables (%d))\n", From e1c20a2ecc8e0f1009137c6714aaa324c90d37a4 Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Tue, 3 Feb 2026 09:48:23 -0500 Subject: [PATCH 2641/2653] drm/amdgpu: Send applicable RMA CPERs at end of RAS init Firmware and monitoring tools may not be ready to receive a CPER when we read the bad pages, so send the CPERs at the end of RAS initialization to ensure that the FW is ready to receive and process the CPER. This removes the previous CPER submission that was added during bad page load, and sends both in-band and out-of-band at the same time. Signed-off-by: Kent Russell Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 ++ .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 23 +++++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h | 2 ++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 459a01745d56e..e1b2f0b254ed5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -4669,6 +4669,8 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev) amdgpu_ras_block_late_init_default(adev, &obj->ras_comm); } + amdgpu_ras_check_bad_page_status(adev); + return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 64dd7a81bff5f..2c5d7f87e593e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -1928,3 +1928,26 @@ int amdgpu_ras_smu_erase_ras_table(struct amdgpu_device *adev, result); return -EOPNOTSUPP; } + +void amdgpu_ras_check_bad_page_status(struct amdgpu_device *adev) +{ + struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); + struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; + + if (!control || amdgpu_bad_page_threshold == 0) + return; + + if (control->ras_num_bad_pages >= ras->bad_page_cnt_threshold) { + if (amdgpu_dpm_send_rma_reason(adev)) + dev_warn(adev->dev, "Unable to send out-of-band RMA CPER"); + else + dev_dbg(adev->dev, "Sent out-of-band RMA CPER"); + + if (adev->cper.enabled && !amdgpu_uniras_enabled(adev)) { + if (amdgpu_cper_generate_bp_threshold_record(adev)) + dev_warn(adev->dev, "Unable to send in-band RMA CPER"); + else + dev_dbg(adev->dev, "Sent in-band RMA CPER"); + } + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h index 2e5d63957e714..a62114800a92a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h @@ -193,6 +193,8 @@ int amdgpu_ras_eeprom_read_idx(struct amdgpu_ras_eeprom_control *control, int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *control); +void amdgpu_ras_check_bad_page_status(struct amdgpu_device *adev); + extern const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops; extern const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops; From 0a212abb3232787b57450e1c9e3a50a8ef63604f Mon Sep 17 00:00:00 2001 From: Xiaogang Chen Date: Tue, 13 Jan 2026 20:45:14 -0600 Subject: [PATCH 2642/2653] drm/amdkfd: kfd driver supports hot unplug/replug amdgpu devices This patch allows kfd driver function correctly when AMD gpu devices got unplug/replug at run time. When an AMD gpu device got unplug kfd driver gracefully terminates existing kfd processes after stops all queues by sending SIGBUS to user process. After that user space can still use remaining AMD gpu devices. When all AMD gpu devices at system got removed kfd driver will not response new requests. Unplugged AMD gpu devices can be re-plugged. kfd driver will use added devices to function as usual. The purpose of this patch is having kfd driver behavior as expected during and after AMD gpu devices unplug/replug at run time. Signed-off-by: Xiaogang Chen Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 5 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 11 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_device.c | 76 +++++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_events.c | 29 +++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 + drivers/gpu/drm/amd/amdkfd/kfd_process.c | 12 +++- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 22 +++++++ 8 files changed, 156 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 70f5334775a6f..01e98fb523593 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -249,6 +249,11 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); } +void amdgpu_amdkfd_teardown_processes(struct amdgpu_device *adev) +{ + kgd2kfd_teardown_processes(adev); +} + void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc) { if (adev->kfd.dev) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 5b1021c9d0d13..0d33e251b9185 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -162,6 +162,7 @@ struct amdkfd_process_info { int amdgpu_amdkfd_init(void); void amdgpu_amdkfd_fini(void); +void amdgpu_amdkfd_teardown_processes(struct amdgpu_device *adev); void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc); int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc); @@ -507,6 +508,8 @@ int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd); bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id); bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, bool retry_fault); +void kgd2kfd_lock_kfd(void); +void kgd2kfd_teardown_processes(struct amdgpu_device *adev); #else static inline int kgd2kfd_init(void) @@ -619,5 +622,13 @@ static inline bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct return false; } +static inline void kgd2kfd_lock_kfd(void) +{ +} + +static inline void kgd2kfd_teardown_processes(struct amdgpu_device *adev) +{ +} + #endif #endif /* AMDGPU_AMDKFD_H_INCLUDED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index db6c566030944..028ce2a514645 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3684,6 +3684,7 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) } amdgpu_amdkfd_suspend(adev, true); + amdgpu_amdkfd_teardown_processes(adev); amdgpu_userq_suspend(adev); /* Workaround for ASICs need to disable SMC first */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 784c28fbaddab..12b48aef094d9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -978,6 +978,9 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd) } kfree(kfd); + + /* after remove a kfd device unlock kfd driver */ + kgd2kfd_unlock_kfd(NULL); } int kgd2kfd_pre_reset(struct kfd_dev *kfd, @@ -1561,10 +1564,14 @@ int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd) return r; } +/* unlock a kfd dev or kfd driver */ void kgd2kfd_unlock_kfd(struct kfd_dev *kfd) { mutex_lock(&kfd_processes_mutex); - --kfd->kfd_dev_lock; + if (kfd) + --kfd->kfd_dev_lock; + else + --kfd_locked; mutex_unlock(&kfd_processes_mutex); } @@ -1728,6 +1735,73 @@ bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entr return false; } +/* check if there is kfd process still uses adev */ +static bool kgd2kfd_check_device_idle(struct amdgpu_device *adev) +{ + struct kfd_process *p; + struct hlist_node *p_temp; + unsigned int temp; + struct kfd_node *dev; + + mutex_lock(&kfd_processes_mutex); + + if (hash_empty(kfd_processes_table)) { + mutex_unlock(&kfd_processes_mutex); + return true; + } + + /* check if there is device still use adev */ + hash_for_each_safe(kfd_processes_table, temp, p_temp, p, kfd_processes) { + for (int i = 0; i < p->n_pdds; i++) { + dev = p->pdds[i]->dev; + if (dev->adev == adev) { + mutex_unlock(&kfd_processes_mutex); + return false; + } + } + } + + mutex_unlock(&kfd_processes_mutex); + + return true; +} + +/** kgd2kfd_teardown_processes - gracefully tear down existing + * kfd processes that use adev + * + * @adev: amdgpu_device where kfd processes run on and will be + * teardown + * + */ +void kgd2kfd_teardown_processes(struct amdgpu_device *adev) +{ + struct hlist_node *p_temp; + struct kfd_process *p; + struct kfd_node *dev; + unsigned int temp; + + mutex_lock(&kfd_processes_mutex); + + if (hash_empty(kfd_processes_table)) { + mutex_unlock(&kfd_processes_mutex); + return; + } + + hash_for_each_safe(kfd_processes_table, temp, p_temp, p, kfd_processes) { + for (int i = 0; i < p->n_pdds; i++) { + dev = p->pdds[i]->dev; + if (dev->adev == adev) + kfd_signal_process_terminate_event(p); + } + } + + mutex_unlock(&kfd_processes_mutex); + + /* wait all kfd processes use adev terminate */ + while (!kgd2kfd_check_device_idle(adev)) + cond_resched(); +} + #if defined(CONFIG_DEBUG_FS) /* This function will send a package to HIQ to hang the HWS diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index 4be85487983a1..1b5396537ded1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -1392,3 +1392,32 @@ void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid) kfd_unref_process(p); } + +/* signal KFD_EVENT_TYPE_SIGNAL events from process p + * send signal SIGBUS to correspondent user space process + */ +void kfd_signal_process_terminate_event(struct kfd_process *p) +{ + struct kfd_event *ev; + u32 id; + + rcu_read_lock(); + + /* iterate from id 1 for KFD_EVENT_TYPE_SIGNAL events */ + id = 1; + idr_for_each_entry_continue(&p->event_idr, ev, id) + if (ev->type == KFD_EVENT_TYPE_SIGNAL) { + spin_lock(&ev->lock); + set_event(ev); + spin_unlock(&ev->lock); + } + + /* Send SIGBUS to p->lead_thread */ + dev_notice(kfd_device, + "Sending SIGBUS to process %d", + p->lead_thread->pid); + + send_sig(SIGBUS, p->lead_thread, 0); + + rcu_read_unlock(); +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index f5ec2c1c9266b..acc7ebbf40191 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1324,6 +1324,7 @@ static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev, } int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev); int kfd_numa_node_to_apic_id(int numa_node_id); +uint32_t kfd_gpu_node_num(void); /* Interrupts */ #define KFD_IRQ_FENCE_CLIENTID 0xff @@ -1683,6 +1684,7 @@ void kfd_signal_vm_fault_event(struct kfd_process_device *pdd, void kfd_signal_reset_event(struct kfd_node *dev); void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid); +void kfd_signal_process_terminate_event(struct kfd_process *p); static inline void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 359064f8e7736..4dcc82058e595 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -842,6 +842,12 @@ struct kfd_process *kfd_create_process(struct task_struct *thread) */ mutex_lock(&kfd_processes_mutex); + if (kfd_gpu_node_num() <= 0) { + pr_warn("no gpu node! Cannot create KFD process"); + process = ERR_PTR(-EINVAL); + goto out; + } + if (kfd_is_locked(NULL)) { pr_debug("KFD is locked! Cannot create process"); process = ERR_PTR(-EINVAL); @@ -1184,7 +1190,6 @@ static void kfd_process_wq_release(struct work_struct *work) if (ef) dma_fence_signal(ef); - kfd_process_remove_sysfs(p); kfd_debugfs_remove_process(p); kfd_process_kunmap_signal_bo(p); @@ -1200,6 +1205,11 @@ static void kfd_process_wq_release(struct work_struct *work) put_task_struct(p->lead_thread); + /* the last step is removing process entries under /sys + * to indicate the process has been terminated. + */ + kfd_process_remove_sysfs(p); + kfree(p); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 185ca078c8f3c..5fea0a34c6596 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -2424,6 +2424,28 @@ int kfd_numa_node_to_apic_id(int numa_node_id) return kfd_cpumask_to_apic_id(cpumask_of_node(numa_node_id)); } +/* kfd_gpu_node_num - Return kfd gpu node number at system */ +uint32_t kfd_gpu_node_num(void) +{ + struct kfd_node *dev; + u8 gpu_num = 0; + u8 id = 0; + + while (kfd_topology_enum_kfd_devices(id, &dev) == 0) { + if (!dev || kfd_devcgroup_check_permission(dev)) { + /* Skip non GPU devices and devices to which the + * current process have no access to + */ + id++; + continue; + } + id++; + gpu_num++; + } + + return gpu_num; +} + #if defined(CONFIG_DEBUG_FS) int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data) From 616dc4b04d8340446d8e7dbb6ad0214050b92d79 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 23 Feb 2026 23:20:50 +0800 Subject: [PATCH 2643/2653] drm/amdgpu: add SPI idle check for GC 9.4.4 in gfx_v9_4_3_is_idle() GC 9.4.4 uses SPI busy status for idle detection instead of GRBM GUI_ACTIVE. Add version check to use SPI_BUSY for 9.4.4 while keeping GRBM_STATUS GUI_ACTIVE check for other GC versions. v2: move this check into amdgpu_ptl_perf_monitor_ctrl(Lijo) Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 15 +++++++++++++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 15 ++++++++++++--- 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index dc991f847d216..f9641f91929ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1274,8 +1274,9 @@ static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, */ if (cmd->resp.status) { dev_err(psp->adev->dev, - "PTL command 0x%x failed, PSP response status: 0x%X\n", - req_code, cmd->resp.status); + "PTL command 0x%x failed, PSP response status: 0x%X fw resp=0x%X\n", + req_code, cmd->resp.status, + cmd->resp.uresp.perf_hw_info.resp); ret = -EIO; goto out; } @@ -1358,6 +1359,16 @@ int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, } } + /* Wait for GFX engine idle before PTL state transition */ + if (req_code == PSP_PTL_PERF_MON_SET) { + ret = amdgpu_device_ip_wait_for_idle(adev, + AMD_IP_BLOCK_TYPE_GFX); + if (ret) { + dev_err(adev->dev, "GFX not idle before PTL operation (%d)\n", ret); + return ret; + } + } + return psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 01e5422ccce2b..276e3cdd22588 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2495,12 +2495,21 @@ static bool gfx_v9_4_3_is_idle(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; int i, num_xcc; + u32 gc_ip_version; num_xcc = NUM_XCC(adev->gfx.xcc_mask); + gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); + for (i = 0; i < num_xcc; i++) { - if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), - GRBM_STATUS, GUI_ACTIVE)) - return false; + if (gc_ip_version == IP_VERSION(9, 4, 4)) { + if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), + GRBM_STATUS, SPI_BUSY)) + return false; + } else { + if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), + GRBM_STATUS, GUI_ACTIVE)) + return false; + } } return true; } From 8a07213d0a312000f45e98fa870dc511024a3bc6 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Thu, 26 Feb 2026 17:50:33 +0800 Subject: [PATCH 2644/2653] drm/amdgpu: Move KFD sched stop/start into PTL control path Move amdgpu_amdkfd_stop/start_sched calls from kfd_ptl_control() into amdgpu_ptl_perf_monitor_ctrl() so all PTL callers (KFD ioctl, sysfs, GFX init) get consistent scheduling management. Add amdgpu_amdkfd_stop/start_sched_all() wrappers to stop and restart KFD scheduling on all nodes without assuming node ID ordering. v3: * call start/stop for PTL Set Only v2: * move the stop/start sched function to amdgpu_ptl_perf_monitor_ctrl(Lijo) * add wrapper amdgpu_amdkfd_stop_sched_all and amdgpu_amdkfd_start_sched_all (Lijo) Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 12 ++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 10 ++++++++-- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 ------ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 16 ++++++++++++++++ 4 files changed, 36 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 0d33e251b9185..357a66379d15b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -465,6 +465,8 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, int xcc_id, void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, int xcc_id, struct amdgpu_vm *vm); void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr); void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev, int xcc_id); +int amdgpu_amdkfd_stop_sched_all(struct amdgpu_device *adev); +int amdgpu_amdkfd_start_sched_all(struct amdgpu_device *adev); #if IS_ENABLED(CONFIG_HSA_AMD_SVM) int kgd2kfd_init_zone_device(struct amdgpu_device *adev); @@ -601,6 +603,11 @@ static inline int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd) return 0; } +static inline int amdgpu_amdkfd_start_sched_all(struct kfd_dev *kfd) +{ + return 0; +} + static inline int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) { return 0; @@ -611,6 +618,11 @@ static inline int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd) return 0; } +static inline int amdgpu_amdkfd_stop_sched_all(struct kfd_dev *kfd) +{ + return 0; +} + static inline bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) { return false; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index f9641f91929ac..d6c9672b4a099 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1359,17 +1359,23 @@ int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, } } - /* Wait for GFX engine idle before PTL state transition */ if (req_code == PSP_PTL_PERF_MON_SET) { + amdgpu_amdkfd_stop_sched_all(adev); + /* Wait for GFX engine idle before PTL state transition */ ret = amdgpu_device_ip_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GFX); if (ret) { + amdgpu_amdkfd_start_sched_all(adev); dev_err(adev->dev, "GFX not idle before PTL operation (%d)\n", ret); return ret; } + ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); + amdgpu_amdkfd_start_sched_all(adev); + } else { + ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); } - return psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); + return ret; } static enum amdgpu_ptl_fmt str_to_ptl_fmt(const char *str) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 8a45126ba1187..a7faaea51b288 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1903,17 +1903,11 @@ int kfd_ptl_control(struct kfd_process_device *pdd, bool enable) if (!pdd->dev->kfd2kgd || !pdd->dev->kfd2kgd->ptl_ctrl) return -EOPNOTSUPP; - if (adev->kfd.init_complete) - amdgpu_amdkfd_stop_sched(adev, pdd->dev->node_id); - ret = pdd->dev->kfd2kgd->ptl_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &pref_format1, &pref_format2); - if (adev->kfd.init_complete) - amdgpu_amdkfd_start_sched(adev, pdd->dev->node_id); - return ret; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 12b48aef094d9..a73e42162e977 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -1650,6 +1650,22 @@ int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd) return 0; } +int amdgpu_amdkfd_stop_sched_all(struct amdgpu_device *adev) +{ + if (!adev->kfd.init_complete) + return 0; + + return kgd2kfd_stop_sched_all_nodes(adev->kfd.dev); +} + +int amdgpu_amdkfd_start_sched_all(struct amdgpu_device *adev) +{ + if (!adev->kfd.init_complete) + return 0; + + return kgd2kfd_start_sched_all_nodes(adev->kfd.dev); +} + bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) { struct kfd_node *node; From 0c53c6e13cc1267aeadac0faae31fb67bcdc9741 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Sat, 28 Feb 2026 13:38:58 +0800 Subject: [PATCH 2645/2653] drm/amdgpu: Set SYSFS disable bit on PTL init Set the AMDGPU_PTL_DISABLE_SYSFS bit in adev->psp.disable_bitmap during gfx_v9_4_3_perf_monitor_ptl_init(). This ensures that PTL is initially disabled via the SYSFS mechanism, matching the intended default state and preventing unintended PTL enablement before explicit user action. Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 276e3cdd22588..7b356a24393bb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2430,6 +2430,7 @@ static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool sta adev->psp.ptl_hw_supported_state = AMDGPU_PTL_HW_SUPPORTED; atomic_set(&adev->psp.ptl_disable_ref, 0); + set_bit(AMDGPU_PTL_DISABLE_SYSFS, adev->psp.disable_bitmap); return 0; } From 13f9e4395430d8dfac97321fcf5dc81b860b33d8 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 3 Mar 2026 16:37:11 +0800 Subject: [PATCH 2646/2653] drm/amdgpu: create PTL sysfs after XGMI reset-on-init restore Create PTL sysfs in xgmi_reset_on_init restore path for MINIMAL_XGMI Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 8 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 1 + 3 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index d6c9672b4a099..13ae52329fe3c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1559,7 +1559,10 @@ int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev) { if (adev->psp.ptl_hw_supported_state != AMDGPU_PTL_HW_SUPPORTED) return 0; + if (adev->psp.ptl_sysfs_created) + return 0; + adev->psp.ptl_sysfs_created = true; return sysfs_create_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); } @@ -1568,6 +1571,11 @@ void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev) if (adev->psp.ptl_hw_supported_state != AMDGPU_PTL_HW_SUPPORTED) return; + if (!adev->psp.ptl_sysfs_created) + return; + + adev->psp.ptl_sysfs_created = false; + sysfs_remove_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index e7257915698b9..fd764a8798f88 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -458,6 +458,7 @@ struct psp_context { enum amdgpu_ptl_hw_supported_state ptl_hw_supported_state; DECLARE_BITMAP(disable_bitmap, AMDGPU_PTL_DISABLE_MAX); bool permanently_disabled; + bool ptl_sysfs_created; }; struct amdgpu_psp_funcs { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c index 4c50530e7c327..d55538a03b6fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c @@ -90,6 +90,7 @@ static int amdgpu_reset_xgmi_reset_on_init_restore_hwctxt( kgd2kfd_init_zone_device(tmp_adev); amdgpu_amdkfd_device_init(tmp_adev); amdgpu_amdkfd_drm_client_create(tmp_adev); + amdgpu_ptl_sysfs_init(tmp_adev); } } From 5914d95e84706279f62c8937ee670e3b57565ed9 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 3 Mar 2026 16:39:35 +0800 Subject: [PATCH 2647/2653] drm/amdkfd: fix unhalt_cpsch warning during module unload Downgrade unhalt_cpsch warning to dev_dbg when sched is already stopped Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 3dd04b99bd892..f35547bcc0e03 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -1851,10 +1851,11 @@ static int halt_cpsch(struct device_queue_manager *dqm) static int unhalt_cpsch(struct device_queue_manager *dqm) { int ret = 0; + struct amdgpu_device *adev = dqm->dev->adev; dqm_lock(dqm); if (!dqm->sched_running || !dqm->sched_halt) { - WARN_ONCE(!dqm->sched_halt, "Scheduling is not on halt.\n"); + dev_dbg(adev->dev, "Scheduling is not on halt.\n"); dqm_unlock(dqm); return 0; } From fa0bd36c3fbebf462427fed9de7dfe17f264fc14 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 3 Mar 2026 16:42:45 +0800 Subject: [PATCH 2648/2653] drm/amdgpu: only set PTL SYSFS disable bit when PTL is disabled Only set the bit when PTL is actually being disabled (state=0) Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 7b356a24393bb..8d72e458a824b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2414,7 +2414,7 @@ static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool sta fmt2 = adev->psp.ptl_fmt2; } - /* initialize PTL with default formats: GFX_FTYPE_I8 & GFX_FTYPE_BF16 */ + /* initialize PTL with default formats: GFX_FTYPE_VECTOR & GFX_FTYPE_F8 */ r = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); if (r) { @@ -2430,7 +2430,13 @@ static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool sta adev->psp.ptl_hw_supported_state = AMDGPU_PTL_HW_SUPPORTED; atomic_set(&adev->psp.ptl_disable_ref, 0); - set_bit(AMDGPU_PTL_DISABLE_SYSFS, adev->psp.disable_bitmap); + if (!state) { + dev_dbg(adev->dev, + "PTL disabled (amdgpu.ptl=%d)\ + To enable, set amdgpu.ptl=1 via module param or kernel cmdline\n", + amdgpu_ptl); + set_bit(AMDGPU_PTL_DISABLE_SYSFS, adev->psp.disable_bitmap); + } return 0; } From dc79b34ad3adaccdc0a41c8a8cc3531dee415b9a Mon Sep 17 00:00:00 2001 From: Gangliang Xie Date: Mon, 9 Feb 2026 17:32:00 +0800 Subject: [PATCH 2649/2653] drm/amdgpu: return when ras table checksum is error end the function flow when ras table checksum is error Signed-off-by: Gangliang Xie Reviewed-by: Tao Zhou Reviewed-by: Kent Russell --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 2c5d7f87e593e..6fba9d5b29ea6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -1701,10 +1701,12 @@ int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) } res = __verify_ras_table_checksum(control); - if (res) + if (res) { dev_err(adev->dev, "RAS table incorrect checksum or error:%d\n", res); + return -EINVAL; + } /* Warn if we are at 90% of the threshold or above */ From ef22bd67ad9fafe4915c8bb7b1aee9e2f5a01cc9 Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Sat, 21 Feb 2026 10:48:14 +0800 Subject: [PATCH 2650/2653] drm/amdgpu: compatible with specific RAS old eeprom format Handle RAS eeprom record when UMC_CHANNEL_IDX_V2 is set. v2: get UMC_CHANNEL_IDX_V2 flag before the clear of it. Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index e1b2f0b254ed5..400bf117100e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3125,9 +3125,11 @@ static int __amdgpu_ras_convert_rec_array_from_rom(struct amdgpu_device *adev, enum amdgpu_memory_partition nps) { int i = 0; + uint64_t chan_idx_v2; enum amdgpu_memory_partition save_nps; save_nps = (bps[0].retired_page >> UMC_NPS_SHIFT) & UMC_NPS_MASK; + chan_idx_v2 = bps[0].retired_page & UMC_CHANNEL_IDX_V2; /*old asics just have pa in eeprom*/ if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12) { @@ -3139,7 +3141,7 @@ static int __amdgpu_ras_convert_rec_array_from_rom(struct amdgpu_device *adev, for (i = 0; i < adev->umc.retire_unit; i++) bps[i].retired_page &= ~(UMC_NPS_MASK << UMC_NPS_SHIFT); - if (save_nps) { + if (save_nps || chan_idx_v2) { if (save_nps == nps) { if (amdgpu_umc_pages_in_a_row(adev, err_data, bps[0].retired_page << AMDGPU_GPU_PAGE_SHIFT)) @@ -3183,10 +3185,12 @@ static int __amdgpu_ras_convert_rec_from_rom(struct amdgpu_device *adev, enum amdgpu_memory_partition nps) { int i = 0; + uint64_t chan_idx_v2; enum amdgpu_memory_partition save_nps; if (!amdgpu_ras_smu_eeprom_supported(adev)) { save_nps = (bps->retired_page >> UMC_NPS_SHIFT) & UMC_NPS_MASK; + chan_idx_v2 = bps->retired_page & UMC_CHANNEL_IDX_V2; bps->retired_page &= ~(UMC_NPS_MASK << UMC_NPS_SHIFT); } else { /* if pmfw manages eeprom, save_nps is not stored on eeprom, @@ -3208,16 +3212,19 @@ static int __amdgpu_ras_convert_rec_from_rom(struct amdgpu_device *adev, err_data->err_addr[i].mcumc_id = bps->mcumc_id; } } else { - if (bps->address) { + if (save_nps || chan_idx_v2) { if (amdgpu_ras_mca2pa_by_idx(adev, bps, err_data)) return -EINVAL; } else { /* for specific old eeprom data, mca address is not stored, * calc it from pa */ - if (amdgpu_umc_pa2mca(adev, bps->retired_page << AMDGPU_GPU_PAGE_SHIFT, - &(bps->address), AMDGPU_NPS1_PARTITION_MODE)) - return -EINVAL; + if (bps->address == 0) + if (amdgpu_umc_pa2mca(adev, + bps->retired_page << AMDGPU_GPU_PAGE_SHIFT, + &(bps->address), + AMDGPU_NPS1_PARTITION_MODE)) + return -EINVAL; if (amdgpu_ras_mca2pa(adev, bps, err_data)) return -EOPNOTSUPP; From 1c85654cdb5328917ed4a70dbe2bc57142654f99 Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Sat, 21 Feb 2026 20:11:03 +0800 Subject: [PATCH 2651/2653] drm/amdgpu: clear related counter after RAS eeprom reset Make eeprom data and its counter consistent. Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 6fba9d5b29ea6..44fba4b6aa92a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -508,6 +508,9 @@ int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) control->bad_channel_bitmap = 0; amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); con->update_channel_flag = false; + /* there is no record on eeprom now, clear the counter */ + if (con->eh_data) + con->eh_data->count_saved = 0; amdgpu_ras_debugfs_set_ret_size(control); From d2762fd86fce89f0b32614aeca806a548c7f6993 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 10 Mar 2026 10:39:08 +0800 Subject: [PATCH 2652/2653] drm/amdgpu: fix ptl state isssue after GPU reset or suspend Fix this by skipping the sysfs disable mapping when the GPU is currently undergoing a reset or suspend flow. Additionally, add debug logging in psp_ptl_invoke() to better trace PTL state and format queries/updates cmd. Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 13ae52329fe3c..9be9d4be06a86 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1287,12 +1287,16 @@ static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, *ptl_state = cmd->resp.uresp.perf_hw_info.ptl_state; *fmt1 = cmd->resp.uresp.perf_hw_info.pref_format1; *fmt2 = cmd->resp.uresp.perf_hw_info.pref_format2; + dev_dbg(psp->adev->dev, "PTL query: state=%d, fmt1=%d, fmt2=%d\n", + *ptl_state, *fmt1, *fmt2); break; case PSP_PTL_PERF_MON_SET: /* Update cached state only on success */ psp->ptl_enabled = *ptl_state; psp->ptl_fmt1 = *fmt1; psp->ptl_fmt2 = *fmt2; + dev_dbg(psp->adev->dev, "PTL set: state=%d, fmt1=%d, fmt2=%d\n", + *ptl_state, *fmt1, *fmt2); break; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 8d72e458a824b..06ab68e09a794 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2430,7 +2430,7 @@ static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool sta adev->psp.ptl_hw_supported_state = AMDGPU_PTL_HW_SUPPORTED; atomic_set(&adev->psp.ptl_disable_ref, 0); - if (!state) { + if (!state && !amdgpu_in_reset(adev) && !adev->in_suspend) { dev_dbg(adev->dev, "PTL disabled (amdgpu.ptl=%d)\ To enable, set amdgpu.ptl=1 via module param or kernel cmdline\n", From 579191ae3bd4a782fb47f477a891e461483bf3b1 Mon Sep 17 00:00:00 2001 From: Daniel Sanfte Date: Sun, 29 Mar 2026 13:51:15 +0100 Subject: [PATCH 2653/2653] dkms: remove CONFIG_DMABUF_MOVENOTIFY gate for P2P enablement The CONFIG_DMABUF_MOVENOTIFY kernel config option was an AMD out-of-tree config that existed in older patched kernels. Since mainline kernel ~5.12, the DMA-buf move_notify callback is built-in unconditionally (part of struct dma_buf_ops) with no separate Kconfig gate. On mainline kernels (tested on 6.14), CONFIG_DMABUF_MOVENOTIFY is never defined, which causes CONFIG_HSA_AMD_P2P to be disabled even when CONFIG_PCI_P2PDMA=y. This prevents GPU-to-GPU P2P access through PCIe switches (e.g., Broadcom PEX88096) because the IOMMU remap check in amdgpu_device_is_peer_accessible() is compiled out entirely. Without CONFIG_HSA_AMD_P2P, the driver falls back to raw DMA mask address checking which fails for GPUs behind PCIe switches where BAR addresses (e.g., 62 TiB) exceed the GPU's 44-bit DMA mask, even though IOMMU remapping would make P2P work correctly. The fix removes the CONFIG_DMABUF_MOVENOTIFY inner check, keeping only the CONFIG_PCI_P2PDMA gate which is the actual functional requirement for PCIe peer-to-peer DMA support. Tested on: - 2x AMD Instinct MI50 32GB behind Broadcom PEX88096 Gen4 switch - Kernel 6.14.0-37-generic (Ubuntu mainline) - ROCm 6.4.2 with amdgpu DKMS 6.12.12 - Verified: KFD p2p_links, hipDeviceCanAccessPeer, P2P memcpy, rocm-bandwidth-test bidirectional P2P all functional after fix Signed-off-by: Daniel Sanfte --- drivers/gpu/drm/amd/dkms/dkms-config.sh | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh index efe7089df9c36..c60e20695b462 100755 --- a/drivers/gpu/drm/amd/dkms/dkms-config.sh +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -108,9 +108,7 @@ append_mk "subdir-ccflags-y += -DDRM_VER=${DRM_VER} -DDRM_PATCH=${DRM_PATCH} -DD # Check for P2PDMA configuration _enable=0 if [[ "$(get_config CONFIG_PCI_P2PDMA)" == "y" ]]; then - if [[ "$(get_config CONFIG_DMABUF_MOVENOTIFY)" == "y" ]]; then - _enable=1 - fi + _enable=1 fi export_macro_mk CONFIG_HSA_AMD_P2P ${_enable}